diff --git a/library/Cargo.lock b/library/Cargo.lock index 940c8dd662869..4360a8fdbb4ba 100644 --- a/library/Cargo.lock +++ b/library/Cargo.lock @@ -4,9 +4,9 @@ version = 4 [[package]] name = "addr2line" -version = "0.25.1" +version = "0.27.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1b5d307320b3181d6d7954e663bd7c774a838b8220fe0593c86d9fb09f498b4b" +checksum = "e567177890eb1617b1f774005b66b26b2377afd138a2ca37aae7d8f0c81429d4" dependencies = [ "gimli", "rustc-std-workspace-alloc", @@ -82,9 +82,9 @@ dependencies = [ [[package]] name = "dlmalloc" -version = "0.2.11" +version = "0.2.14" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "06cdfe340b16dd990c54cce79743613fa09fbb16774f33a77c9fd196f8f3fa30" +checksum = "ad5208a115eaba24916f7456929832e310a81518c641f93fee4f89aa93aa3675" dependencies = [ "cfg-if", "libc", @@ -119,9 +119,9 @@ dependencies = [ [[package]] name = "gimli" -version = "0.32.3" +version = "0.34.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e629b9b98ef3dd8afe6ca2bd0f89306cec16d43d907889945bc5d6687f2f13c7" +checksum = "1033caf0b349c518623b5396bfb2cf0bddf44f0306d543a250e5743297aafd10" dependencies = [ "rustc-std-workspace-alloc", "rustc-std-workspace-core", @@ -129,9 +129,9 @@ dependencies = [ [[package]] name = "hashbrown" -version = "0.16.1" +version = "0.17.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "841d1cc9bed7f9236f321df977030373f4a4163ae1a7dbfe1a51a2c1a51d9100" +checksum = "ed5909b6e89a2db4456e54cd5f673791d7eca6732202bbf2a9cc504fe2f9b84a" dependencies = [ "foldhash", "rustc-std-workspace-alloc", @@ -150,27 +150,27 @@ dependencies = [ [[package]] name = "libc" -version = "0.2.178" +version = "0.2.189" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "37c93d8daa9d8a012fd8ab92f088405fb202ea0b6ab73ee2482ae66af4f42091" +checksum = "3eaf3ede3fee6db1a4c2ee091bf8a8b4dccdc6d17f656fb07896ee72867612f2" dependencies = [ "rustc-std-workspace-core", ] [[package]] name = "memchr" -version = "2.7.6" +version = "2.8.3" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f52b00d39961fc5b2736ea853c9cc86238e165017a493d1d5c8eac6bdc4cc273" +checksum = "cf8baf1c55e62ffcace7a9f06f4bd9cd3f0c4beb022d3b367256b91b87513d98" dependencies = [ "rustc-std-workspace-core", ] [[package]] name = "miniz_oxide" -version = "0.8.9" +version = "0.9.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1fa76a2c86f704bdb222d66965fb3d63269ce38518b83cb0575fca855ebb6316" +checksum = "b63fbc4a50860e98e7b2aa7804ded1db5cbc3aff9193adaff57a6931bf7c4b4c" dependencies = [ "adler2", "rustc-std-workspace-alloc", @@ -179,9 +179,9 @@ dependencies = [ [[package]] name = "moto-rt" -version = "0.16.0" +version = "0.16.3" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "29aea9f7dfeb258e030a84e0ec38a9c2ec2063d4f45eb2db31445cfc40b3dba1" +checksum = "bcd8eb21b606833bc3a8c1c343bc75eb1999b288b2c2d515ae872e9e2f153187" dependencies = [ "rustc-std-workspace-alloc", "rustc-std-workspace-core", @@ -189,9 +189,9 @@ dependencies = [ [[package]] name = "object" -version = "0.37.3" +version = "0.39.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ff76201f031d8863c38aa7f905eca4f53abbfa15f609db4277d44cd8938f33fe" +checksum = "2e5a6c098c7a3b6547378093f5cc30bc54fd361ce711e05293a5cc589562739b" dependencies = [ "memchr", "rustc-std-workspace-alloc", @@ -296,18 +296,18 @@ dependencies = [ [[package]] name = "rand" -version = "0.9.2" +version = "0.9.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "6db2770f06117d490610c7488547d543617b21bfa07796d7a12f6f1bd53850d1" +checksum = "b9ef1d0d795eb7d84685bca4f72f3649f064e6641543d3a8c415898726a57b41" dependencies = [ "rand_core", ] [[package]] name = "rand_core" -version = "0.9.3" +version = "0.9.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "99d9a13982dcf210057a8a78572b2217b667c3beacbf3a0d8b454f6f82837d38" +checksum = "76afc826de14238e6e8c374ddcc1fa19e374fd8dd986b0d2af0d02377261d83c" [[package]] name = "rand_xorshift" @@ -320,18 +320,18 @@ dependencies = [ [[package]] name = "rustc-demangle" -version = "0.1.27" +version = "0.1.28" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b50b8869d9fc858ce7266cce0194bd74df58b9d0e3f6df3a9fc8eb470d95c09d" +checksum = "b74b56ffa8bb2830709a538c2cbcae9aa062db0d2a42563bfb09bdaae44020eb" dependencies = [ "rustc-std-workspace-core", ] [[package]] name = "rustc-literal-escaper" -version = "0.0.7" +version = "0.0.8" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "8be87abb9e40db7466e0681dc8ecd9dcfd40360cb10b4c8fe24a7c4c3669b198" +checksum = "bfe6f213fb658c8fb95baabd5420393438cf5a98d707f5dd701d9197c705f71e" dependencies = [ "rustc-std-workspace-core", ] @@ -401,9 +401,10 @@ dependencies = [ "std_detect", "unwind", "vex-sdk", - "wasi 0.11.1+wasi-snapshot-preview1", - "wasi 0.14.4+wasi-0.2.4", - "windows-link 0.0.0", + "wasip1", + "wasip2", + "wasip3", + "windows-link", ] [[package]] @@ -473,9 +474,9 @@ dependencies = [ [[package]] name = "unwinding" -version = "0.2.8" +version = "0.2.10" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "60612c845ef41699f39dc8c5391f252942c0a88b7d15da672eff0d14101bbd6d" +checksum = "4b134ada16dda9e435abe2a6d76a01d497bc60707357845a15f9b0ed42dc88ce" dependencies = [ "gimli", "rustc-std-workspace-core", @@ -497,20 +498,20 @@ dependencies = [ ] [[package]] -name = "wasi" -version = "0.11.1+wasi-snapshot-preview1" +name = "wasip1" +version = "1.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ccf3ec651a847eb01de73ccad15eb7d99f80485de043efb2f370cd654f4ea44b" +checksum = "b5e26842486624357dbeb8f0381cf1fb42f022291fd787d4a816768fec8cc760" dependencies = [ "rustc-std-workspace-alloc", "rustc-std-workspace-core", ] [[package]] -name = "wasi" -version = "0.14.4+wasi-0.2.4" +name = "wasip2" +version = "1.0.4+wasi-0.2.12" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "88a5f4a424faf49c3c2c344f166f0662341d470ea185e939657aaff130f0ec4a" +checksum = "b67efb37e106e55ce722a510d6b5f9c17f083e5fc79afc2badeb12cc313d9487" dependencies = [ "rustc-std-workspace-alloc", "rustc-std-workspace-core", @@ -518,94 +519,29 @@ dependencies = [ ] [[package]] -name = "windows-link" -version = "0.0.0" - -[[package]] -name = "windows-link" -version = "0.2.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f0805222e57f7521d6a62e36fa9163bc891acd422f971defe97d64e70d0a4fe5" - -[[package]] -name = "windows-sys" -version = "0.60.2" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f2f500e4d28234f72040990ec9d39e3a6b950f9f22d3dba18416c35882612bcb" -dependencies = [ - "windows-targets", -] - -[[package]] -name = "windows-targets" -version = "0.53.5" +name = "wasip3" +version = "0.7.1+wasi-0.3.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "4945f9f551b88e0d65f3db0bc25c33b8acea4d9e41163edf90dcd0b19f9069f3" +checksum = "75e9ed91ee5a995b6fe16c89d4511a8c12eb76967be20b57557618e02e781bcc" dependencies = [ - "windows-link 0.2.1", - "windows_aarch64_gnullvm", - "windows_aarch64_msvc", - "windows_i686_gnu", - "windows_i686_gnullvm", - "windows_i686_msvc", - "windows_x86_64_gnu", - "windows_x86_64_gnullvm", - "windows_x86_64_msvc", + "rustc-std-workspace-alloc", + "rustc-std-workspace-core", + "wit-bindgen", ] [[package]] -name = "windows_aarch64_gnullvm" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a9d8416fa8b42f5c947f8482c43e7d89e73a173cead56d044f6a56104a6d1b53" - -[[package]] -name = "windows_aarch64_msvc" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b9d782e804c2f632e395708e99a94275910eb9100b2114651e04744e9b125006" - -[[package]] -name = "windows_i686_gnu" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "960e6da069d81e09becb0ca57a65220ddff016ff2d6af6a223cf372a506593a3" - -[[package]] -name = "windows_i686_gnullvm" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "fa7359d10048f68ab8b09fa71c3daccfb0e9b559aed648a8f95469c27057180c" - -[[package]] -name = "windows_i686_msvc" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1e7ac75179f18232fe9c285163565a57ef8d3c89254a30685b57d83a38d326c2" - -[[package]] -name = "windows_x86_64_gnu" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9c3842cdd74a865a8066ab39c8a7a473c0778a3f29370b5fd6b4b9aa7df4a499" - -[[package]] -name = "windows_x86_64_gnullvm" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "0ffa179e2d07eee8ad8f57493436566c7cc30ac536a3379fdf008f47f6bb7ae1" +name = "windows-link" +version = "0.0.0" [[package]] -name = "windows_x86_64_msvc" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d6bbff5f0aada427a1e5a6da5f1f98158182f26556f345ac9e04d36d0ebed650" +name = "windows-sys" +version = "0.61.100" [[package]] name = "wit-bindgen" -version = "0.45.1" +version = "0.57.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5c573471f125075647d03df72e026074b7203790d41351cd6edc96f46bcccd36" +checksum = "1ebf944e87a7c253233ad6766e082e3cd714b5d03812acc24c318f549614536e" dependencies = [ "rustc-std-workspace-alloc", "rustc-std-workspace-core", diff --git a/library/Cargo.toml b/library/Cargo.toml index 87df966bb6b87..788c990c16344 100644 --- a/library/Cargo.toml +++ b/library/Cargo.toml @@ -85,3 +85,6 @@ rustflags = [ rustc-std-workspace-core = { path = 'rustc-std-workspace-core' } rustc-std-workspace-alloc = { path = 'rustc-std-workspace-alloc' } rustc-std-workspace-std = { path = 'rustc-std-workspace-std' } + +# See comments in `library/windows-sys/Cargo.toml` for why this is patched +windows-sys = { path = 'windows-sys' } diff --git a/library/alloc/Cargo.toml b/library/alloc/Cargo.toml index bfe96a7b3bc94..c933eca3beb68 100644 --- a/library/alloc/Cargo.toml +++ b/library/alloc/Cargo.toml @@ -16,7 +16,7 @@ bench = false [dependencies] core = { path = "../core", public = true } -compiler_builtins = { path = "../compiler-builtins/compiler-builtins", features = ["rustc-dep-of-std"] } +compiler_builtins = { path = "../compiler-builtins/compiler-builtins", features = ["compiler-builtins"] } safety = { path = "../contracts/safety" } [features] diff --git a/library/alloc/src/alloc.rs b/library/alloc/src/alloc.rs index cd1c2ea8fcd1e..c0d7d8b605227 100644 --- a/library/alloc/src/alloc.rs +++ b/library/alloc/src/alloc.rs @@ -5,6 +5,7 @@ #[stable(feature = "alloc_module", since = "1.28.0")] #[doc(inline)] pub use core::alloc::*; +use core::mem::Alignment; use core::ptr::{self, NonNull}; use core::{cmp, hint}; @@ -18,19 +19,24 @@ unsafe extern "Rust" { #[rustc_nounwind] #[rustc_std_internal_symbol] #[rustc_allocator_zeroed_variant = "__rust_alloc_zeroed"] - fn __rust_alloc(size: usize, align: usize) -> *mut u8; + fn __rust_alloc(size: usize, align: Alignment) -> *mut u8; #[rustc_deallocator] #[rustc_nounwind] #[rustc_std_internal_symbol] - fn __rust_dealloc(ptr: *mut u8, size: usize, align: usize); + fn __rust_dealloc(ptr: NonNull, size: usize, align: Alignment); #[rustc_reallocator] #[rustc_nounwind] #[rustc_std_internal_symbol] - fn __rust_realloc(ptr: *mut u8, old_size: usize, align: usize, new_size: usize) -> *mut u8; + fn __rust_realloc( + ptr: NonNull, + old_size: usize, + align: Alignment, + new_size: usize, + ) -> *mut u8; #[rustc_allocator_zeroed] #[rustc_nounwind] #[rustc_std_internal_symbol] - fn __rust_alloc_zeroed(size: usize, align: usize) -> *mut u8; + fn __rust_alloc_zeroed(size: usize, align: Alignment) -> *mut u8; #[rustc_nounwind] #[rustc_std_internal_symbol] @@ -46,17 +52,46 @@ unsafe extern "Rust" { /// Note: while this type is unstable, the functionality it provides can be /// accessed through the [free functions in `alloc`](self#functions). #[unstable(feature = "allocator_api", issue = "32838")] -#[derive(Copy, Clone, Default, Debug)] +#[derive(Copy, Debug)] +#[derive_const(Clone, Default)] // the compiler needs to know when a Box uses the global allocator vs a custom one #[lang = "global_alloc_ty"] pub struct Global; +#[unstable(feature = "allocator_api", issue = "32838")] +unsafe impl core::alloc::AllocatorClone for Global {} + +#[unstable(feature = "allocator_api", issue = "32838")] +unsafe impl core::alloc::StaticAllocator for Global {} + /// Allocates memory with the global allocator. /// /// This function forwards calls to the [`GlobalAlloc::alloc`] method /// of the allocator registered with the `#[global_allocator]` attribute /// if there is one, or the `std` crate’s default. /// +/// Note, however, that invoking this function is *not* equivalent to invoking the underlying +/// [`GlobalAlloc::alloc`] method of the registered allocator directly. Users of this function +/// cannot assume anything about what the allocator does, other than the documented requirements. +/// This means: +/// +/// - This function may non-deterministically entirely skip the underlying allocator, e.g. if the +/// compiler can show that this allocation can be replaced by a stack variable. The compiler may +/// also merge multiple allocation operations into one, as long as it can also adjust all +/// corresponding deallocation operations accordingly. +/// - An allocation created by invoking this function has exactly the size and minimum alignment +/// defined by `layout`, even if the underlying allocator makes stronger promises. +/// - The allocation can only be freed by invoking [`dealloc`] or [`realloc`]. In particular, +/// passing a pointer to such an allocation directly to the underlying method on [`GlobalAlloc`] is +/// not permitted. Until one of those functions is called, it is undefined behavior to access the +/// memory that backs this allocation with any pointer not derived from the return value of this +/// function (e.g., with internal pointers the allocator might keep around). +/// - This function de-initializes the contents of the allocation before handing it to the user. So even +/// if you control the underlying allocator and know that it explicitly initialized this memory, +/// you cannot rely on it being initialized. +/// +/// Users of this function have to consider that in the future, allocators may be allowed to unwind. +/// /// This function is expected to be deprecated in favor of the `allocate` method /// of the [`Global`] type when it and the [`Allocator`] trait become stable. /// @@ -92,7 +127,7 @@ pub unsafe fn alloc(layout: Layout) -> *mut u8 { // stable code until it is actually stabilized. __rust_no_alloc_shim_is_unstable_v2(); - __rust_alloc(layout.size(), layout.align()) + __rust_alloc(layout.size(), layout.alignment()) } } @@ -102,6 +137,24 @@ pub unsafe fn alloc(layout: Layout) -> *mut u8 { /// of the allocator registered with the `#[global_allocator]` attribute /// if there is one, or the `std` crate’s default. /// +/// Note, however, that invoking this function is *not* equivalent to invoking the underlying +/// [`GlobalAlloc::dealloc`] method of the registered allocator directly. Users of this function +/// cannot assume anything about what the allocator does, other than the documented requirements. +/// This means: +/// +/// - This function may non-deterministically entirely skip the underlying allocator, e.g. if the +/// compiler can show that this allocation can be replaced by a stack variable. The compiler may +/// also merge multiple allocation operations into one, as long as it can also adjust all +/// corresponding deallocation operations accordingly. +/// - The pointer passed to this function must have been obtained by invoking [`alloc`], +/// [`alloc_zeroed`], or [`realloc`]. In particular, passing a pointer returned by the underlying +/// methods on [`GlobalAlloc`] is not permitted. +/// - This function de-initializes the contents of the allocation before handing it to the allocator. +/// So even if you know that the program previously initialized that memory, the allocator cannot +/// rely on it being initialized. +/// +/// Users of this function have to consider that in the future, allocators may be allowed to unwind. +/// /// This function is expected to be deprecated in favor of the `deallocate` method /// of the [`Global`] type when it and the [`Allocator`] trait become stable. /// @@ -112,7 +165,14 @@ pub unsafe fn alloc(layout: Layout) -> *mut u8 { #[inline] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces pub unsafe fn dealloc(ptr: *mut u8, layout: Layout) { - unsafe { __rust_dealloc(ptr, layout.size(), layout.align()) } + unsafe { dealloc_nonnull(NonNull::new_unchecked(ptr), layout) } +} + +/// Same as [`dealloc`] but when you already have a non-null pointer +#[inline] +#[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces +unsafe fn dealloc_nonnull(ptr: NonNull, layout: Layout) { + unsafe { __rust_dealloc(ptr, layout.size(), layout.alignment()) } } /// Reallocates memory with the global allocator. @@ -121,6 +181,32 @@ pub unsafe fn dealloc(ptr: *mut u8, layout: Layout) { /// of the allocator registered with the `#[global_allocator]` attribute /// if there is one, or the `std` crate’s default. /// +/// Note, however, that invoking this function is *not* equivalent to invoking the underlying +/// [`GlobalAlloc::realloc`] method of the registered allocator directly. Users of this function +/// cannot assume anything about what the allocator does, other than the documented requirements. +/// This means: +/// +/// - This function may non-deterministically entirely skip the underlying allocator, e.g. if the +/// compiler can show that this allocation can be replaced by a stack variable. The compiler may +/// also merge multiple allocation operations into one, as long as it can also adjust all +/// corresponding deallocation operations accordingly. +/// - The pointer passed to this function must have been obtained by invoking [`alloc`], +/// [`alloc_zeroed`], or [`realloc`]. In particular, passing a pointer returned by the underlying +/// methods on [`GlobalAlloc`] is not permitted. +/// - An allocation created by invoking this function has exactly the size and minimum alignment +/// defined by `layout`, even if the underlying allocator makes stronger promises. +/// - The allocation can only be freed by invoking [`dealloc`] or [`realloc`]. In particular, +/// passing a pointer to such an allocation directly to the underlying method on [`GlobalAlloc`] is +/// not permitted. Until one of those functions is called, it is undefined behavior to access the +/// memory that backs this allocation with any pointer not derived from the return value of this +/// function (e.g., with internal pointers the allocator might keep around). +/// - If this grows the allocation, the contents of the grown part of the new allocation allocation +/// are de-initialized by this function before returning. +/// - If this shrinks the allocation, the contents of the removed part of the old allocation are +/// de-initialized by this function before invoking the underlying allocator. +/// +/// Users of this function have to consider that in the future, allocators may be allowed to unwind. +/// /// This function is expected to be deprecated in favor of the `grow` and `shrink` methods /// of the [`Global`] type when it and the [`Allocator`] trait become stable. /// @@ -132,7 +218,14 @@ pub unsafe fn dealloc(ptr: *mut u8, layout: Layout) { #[inline] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces pub unsafe fn realloc(ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { - unsafe { __rust_realloc(ptr, layout.size(), layout.align(), new_size) } + unsafe { realloc_nonnull(NonNull::new_unchecked(ptr), layout, new_size) } +} + +/// Same as [`realloc`] but when you already have a non-null pointer +#[inline] +#[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces +unsafe fn realloc_nonnull(ptr: NonNull, layout: Layout, new_size: usize) -> *mut u8 { + unsafe { __rust_realloc(ptr, layout.size(), layout.alignment(), new_size) } } /// Allocates zero-initialized memory with the global allocator. @@ -141,6 +234,25 @@ pub unsafe fn realloc(ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 /// of the allocator registered with the `#[global_allocator]` attribute /// if there is one, or the `std` crate’s default. /// +/// Note, however, that invoking this function is *not* equivalent to invoking the underlying +/// [`GlobalAlloc::alloc_zeroed`] method of the registered allocator directly. Users of this +/// function cannot assume anything about what the allocator does, other than the documented +/// requirements. This means: +/// +/// - This function may non-deterministically entirely skip the underlying allocator, e.g. if the +/// compiler can show that this allocation can be replaced by a stack variable. The compiler may +/// also merge multiple allocation operations into one, as long as it can also adjust all +/// corresponding deallocation operations accordingly. +/// - The allocation can only be freed by invoking [`dealloc`] or [`realloc`]. In particular, +/// passing a pointer to such an allocation directly to the underlying method on [`GlobalAlloc`] is +/// not permitted. Until one of those functions is called, it is undefined behavior to access the +/// memory that backs this allocation with any pointer not derived from the return value of this +/// function (e.g., with internal pointers the allocator might keep around). +/// - An allocation created by invoking this function has exactly the size and minimum alignment +/// defined by `layout`, even if the underlying allocator makes stronger promises. +/// +/// Users of this function have to consider that in the future, allocators may be allowed to unwind. +/// /// This function is expected to be deprecated in favor of the `allocate_zeroed` method /// of the [`Global`] type when it and the [`Allocator`] trait become stable. /// @@ -175,7 +287,7 @@ pub unsafe fn alloc_zeroed(layout: Layout) -> *mut u8 { // stable code until it is actually stabilized. __rust_no_alloc_shim_is_unstable_v2(); - __rust_alloc_zeroed(layout.size(), layout.align()) + __rust_alloc_zeroed(layout.size(), layout.alignment()) } } @@ -184,12 +296,12 @@ impl Global { #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces fn alloc_impl_runtime(layout: Layout, zeroed: bool) -> Result, AllocError> { match layout.size() { - 0 => Ok(NonNull::slice_from_raw_parts(layout.dangling_ptr(), 0)), + 0 => Ok(layout.dangling_ptr().cast_slice(0)), // SAFETY: `layout` is non-zero in size, size => unsafe { let raw_ptr = if zeroed { alloc_zeroed(layout) } else { alloc(layout) }; let ptr = NonNull::new(raw_ptr).ok_or(AllocError)?; - Ok(NonNull::slice_from_raw_parts(ptr, size)) + Ok(ptr.cast_slice(size)) }, } } @@ -206,7 +318,7 @@ impl Global { // allocation than requested. // * Other conditions must be upheld by the caller, as per `Allocator::deallocate()`'s // safety documentation. - unsafe { dealloc(ptr.as_ptr(), layout) } + unsafe { dealloc_nonnull(ptr, layout) } } } @@ -236,12 +348,12 @@ impl Global { // `realloc` probably checks for `new_size >= old_layout.size()` or something similar. hint::assert_unchecked(new_size >= old_layout.size()); - let raw_ptr = realloc(ptr.as_ptr(), old_layout, new_size); + let raw_ptr = realloc_nonnull(ptr, old_layout, new_size); let ptr = NonNull::new(raw_ptr).ok_or(AllocError)?; if zeroed { raw_ptr.add(old_size).write_bytes(0, new_size - old_size); } - Ok(NonNull::slice_from_raw_parts(ptr, new_size)) + Ok(ptr.cast_slice(new_size)) }, // SAFETY: because `new_layout.size()` must be greater than or equal to `old_size`, @@ -277,7 +389,7 @@ impl Global { // SAFETY: conditions must be upheld by the caller 0 => unsafe { self.deallocate(ptr, old_layout); - Ok(NonNull::slice_from_raw_parts(new_layout.dangling_ptr(), 0)) + Ok(new_layout.dangling_ptr().cast_slice(0)) }, // SAFETY: `new_size` is non-zero. Other conditions must be upheld by the caller @@ -285,9 +397,9 @@ impl Global { // `realloc` probably checks for `new_size <= old_layout.size()` or something similar. hint::assert_unchecked(new_size <= old_layout.size()); - let raw_ptr = realloc(ptr.as_ptr(), old_layout, new_size); + let raw_ptr = realloc_nonnull(ptr, old_layout, new_size); let ptr = NonNull::new(raw_ptr).ok_or(AllocError)?; - Ok(NonNull::slice_from_raw_parts(ptr, new_size)) + Ok(ptr.cast_slice(new_size)) }, // SAFETY: because `new_size` must be smaller than or equal to `old_layout.size()`, @@ -368,7 +480,7 @@ impl Global { #[rustc_const_unstable(feature = "const_heap", issue = "79597")] const fn alloc_impl_const(layout: Layout, zeroed: bool) -> Result, AllocError> { match layout.size() { - 0 => Ok(NonNull::slice_from_raw_parts(layout.dangling_ptr(), 0)), + 0 => Ok(layout.dangling_ptr().cast_slice(0)), // SAFETY: `layout` is non-zero in size, size => unsafe { let raw_ptr = core::intrinsics::const_allocate(layout.size(), layout.align()); @@ -377,7 +489,7 @@ impl Global { // SAFETY: the pointer returned by `const_allocate` is valid to write to. ptr.write_bytes(0, size); } - Ok(NonNull::slice_from_raw_parts(ptr, size)) + Ok(ptr.cast_slice(size)) }, } } @@ -422,7 +534,7 @@ impl Global { #[unstable(feature = "allocator_api", issue = "32838")] #[rustc_const_unstable(feature = "const_heap", issue = "79597")] -unsafe impl const Allocator for Global { +const unsafe impl Allocator for Global { #[inline] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces fn allocate(&self, layout: Layout) -> Result, AllocError> { @@ -479,19 +591,6 @@ unsafe impl const Allocator for Global { } } -/// The allocator for `Box`. -#[cfg(not(no_global_oom_handling))] -#[lang = "exchange_malloc"] -#[inline] -#[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces -unsafe fn exchange_malloc(size: usize, align: usize) -> *mut u8 { - let layout = unsafe { Layout::from_size_align_unchecked(size, align) }; - match Global.allocate(layout) { - Ok(ptr) => ptr.as_mut_ptr(), - Err(_) => handle_alloc_error(layout), - } -} - // # Allocation error handler #[cfg(not(no_global_oom_handling))] diff --git a/library/alloc/src/borrow.rs b/library/alloc/src/borrow.rs index d1c7cd47da0f0..b6a7a1eae2a70 100644 --- a/library/alloc/src/borrow.rs +++ b/library/alloc/src/borrow.rs @@ -188,7 +188,7 @@ impl<'a, B: ?Sized + ToOwned> Borrow for Cow<'a, B> // B::Owned: [const] Borrow, { fn borrow(&self) -> &B { - &**self + self } } diff --git a/library/alloc/src/boxed.rs b/library/alloc/src/boxed.rs index 0844239826bf5..019749c77ae66 100644 --- a/library/alloc/src/boxed.rs +++ b/library/alloc/src/boxed.rs @@ -200,16 +200,16 @@ use core::ops::{ }; #[cfg(not(no_global_oom_handling))] use core::ops::{Residual, Try}; -use core::pin::{Pin, PinCoerceUnsized}; +use core::pin::{Pin, PinSafePointer}; use core::ptr::{self, NonNull, Unique}; use core::task::{Context, Poll}; #[cfg(not(no_global_oom_handling))] use crate::alloc::handle_alloc_error; -use crate::alloc::{AllocError, Allocator, Global, Layout}; +use crate::alloc::{AllocError, Allocator, Global, Layout, StaticAllocator}; use crate::raw_vec::RawVec; #[cfg(not(no_global_oom_handling))] -use crate::str::from_boxed_utf8_unchecked; +use crate::str::from_boxed_utf8_unchecked_in; /// Conversion related impls for `Box<_>` (`From`, `downcast`, etc) mod convert; @@ -218,6 +218,8 @@ mod iter; /// [`ThinBox`] implementation. mod thin; +#[stable(feature = "boxed_array_value_iter", since = "1.99.0")] +pub use iter::BoxedArrayIntoIter; #[unstable(feature = "thin_box", issue = "92791")] pub use thin::ThinBox; @@ -236,14 +238,36 @@ pub struct Box< #[unstable(feature = "allocator_api", issue = "32838")] A: Allocator = Global, >(Unique, A); -/// Constructs a `Box` by calling the `exchange_malloc` lang item and moving the argument into -/// the newly allocated memory. This is an intrinsic to avoid unnecessary copies. +/// Monomorphic function for allocating an uninit `Box`. +#[inline] +// The is a separate function to avoid doing it in every generic version, but it +// looks small to the mir inliner (particularly in panic=abort) so leave it to +// the backend to decide whether pulling it in everywhere is worth doing. +#[rustc_no_mir_inline] +#[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces +#[cfg(not(no_global_oom_handling))] +#[rustc_const_unstable(feature = "const_heap", issue = "79597")] +const fn box_new_uninit(layout: Layout) -> *mut u8 { + match Global.allocate(layout) { + Ok(ptr) => ptr.as_mut_ptr(), + Err(_) => handle_alloc_error(layout), + } +} + +/// Helper for `vec!`. /// -/// This is the surface syntax for `box ` expressions. +/// This is unsafe, but has to be marked as safe or else we couldn't use it in `vec!`. #[doc(hidden)] -#[rustc_intrinsic] #[unstable(feature = "liballoc_internals", issue = "none")] -pub fn box_new(x: T) -> Box; +#[rustc_const_unstable(feature = "const_heap", issue = "79597")] +#[inline(always)] +#[cfg(not(no_global_oom_handling))] +#[rustc_diagnostic_item = "box_assume_init_into_vec_unsafe"] +pub const fn box_assume_init_into_vec_unsafe( + b: Box>, +) -> crate::vec::Vec { + unsafe { (b.assume_init() as Box<[T]>).into_vec() } +} impl Box { /// Allocates memory on the heap and then places `x` into it. @@ -262,7 +286,13 @@ impl Box { #[rustc_diagnostic_item = "box_new"] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces pub fn new(x: T) -> Self { - return box_new(x); + // This is `Box::new_uninit` but inlined to avoid build time regressions. + let ptr = box_new_uninit(::LAYOUT) as *mut T; + // Nothing below can panic so we do not have to worry about deallocating `ptr`. + // SAFETY: we just allocated the box to store `x`. + unsafe { core::intrinsics::write_via_move(ptr, x) }; + // SAFETY: we just initialized the memory `ptr` points to. + unsafe { mem::transmute(ptr) } } /// Constructs a new box with uninitialized contents. @@ -279,10 +309,17 @@ impl Box { /// ``` #[cfg(not(no_global_oom_handling))] #[stable(feature = "new_uninit", since = "1.82.0")] + #[rustc_const_unstable(feature = "const_heap", issue = "79597")] #[must_use] - #[inline] - pub fn new_uninit() -> Box> { - Self::new_uninit_in(Global) + #[inline(always)] + #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces + pub const fn new_uninit() -> Box> { + // This is the same as `Self::new_uninit_in(Global)`, but manually inlined (just like + // `Box::new`). + + // SAFETY: + // - If `allocate` succeeds, the returned pointer exactly matches what `Box` needs. + unsafe { mem::transmute(box_new_uninit(::LAYOUT)) } } /// Constructs a new `Box` with uninitialized contents, with the memory @@ -663,13 +700,22 @@ impl Box { /// does the same as [Box::into_pin]\([Box::new_in]\(x, alloc)). Consider using /// [`into_pin`](Box::into_pin) if you already have a `Box`, or if you want to /// construct a (pinned) `Box` in a different way than with [`Box::new_in`]. + /// + /// # Examples + /// + /// ``` + /// #![feature(allocator_api)] + /// use std::alloc::System; + /// + /// let x = Box::pin_in(1, System); + /// ``` #[cfg(not(no_global_oom_handling))] #[unstable(feature = "allocator_api", issue = "32838")] #[must_use] #[inline(always)] pub fn pin_in(x: T, alloc: A) -> Pin where - A: 'static + Allocator, + A: StaticAllocator, { Self::into_pin(Self::new_in(x, alloc)) } @@ -965,26 +1011,6 @@ impl Box<[T]> { }; unsafe { Ok(RawVec::from_raw_parts_in(ptr.as_ptr(), len, Global).into_box(len)) } } - - /// Converts the boxed slice into a boxed array. - /// - /// This operation does not reallocate; the underlying array of the slice is simply reinterpreted as an array type. - /// - /// If `N` is not exactly equal to the length of `self`, then this method returns `None`. - #[unstable(feature = "alloc_slice_into_array", issue = "148082")] - #[inline] - #[must_use] - pub fn into_array(self) -> Option> { - if self.len() == N { - let ptr = Self::into_raw(self) as *mut [T; N]; - - // SAFETY: The underlying array of a slice has the exact same layout as an actual array `[T; N]` if `N` is equal to the slice's length. - let me = unsafe { Box::from_raw(ptr) }; - Some(me) - } else { - None - } - } } impl Box<[T], A> { @@ -1116,6 +1142,38 @@ impl Box<[T], A> { }; unsafe { Ok(RawVec::from_raw_parts_in(ptr.as_ptr(), len, alloc).into_box(len)) } } + + /// Converts the boxed slice into a boxed array. + /// + /// This operation does not reallocate; the underlying array of the slice is simply reinterpreted as an array type. + /// + /// # Errors + /// + /// Returns the original `Box<[T]>` in the `Err` variant if `self.len()` does not equal `N`. + /// + /// # Examples + /// + /// ``` + /// #![feature(alloc_slice_into_array)] + /// let box_slice: Box<[i32]> = Box::new([1, 2, 3]); + /// + /// let box_array: Box<[i32; 3]> = box_slice.into_array().unwrap(); + /// ``` + #[unstable(feature = "alloc_slice_into_array", issue = "148082")] + #[inline] + #[must_use] + pub fn into_array(self) -> Result, Self> { + if self.len() == N { + let (ptr, alloc) = Self::into_raw_with_allocator(self); + let ptr = ptr as *mut [T; N]; + + // SAFETY: The underlying array of a slice has the exact same layout as an actual array `[T; N]` if `N` is equal to the slice's length. + let me = unsafe { Box::from_raw_in(ptr, alloc) }; + Ok(me) + } else { + Err(self) + } + } } impl Box, A> { @@ -1142,10 +1200,13 @@ impl Box, A> { /// assert_eq!(*five, 5) /// ``` #[stable(feature = "new_uninit", since = "1.82.0")] - #[inline] - pub unsafe fn assume_init(self) -> Box { - let (raw, alloc) = Box::into_raw_with_allocator(self); - unsafe { Box::from_raw_in(raw as *mut T, alloc) } + #[rustc_const_unstable(feature = "const_heap", issue = "79597")] + #[inline(always)] + pub const unsafe fn assume_init(self) -> Box { + // This is used in the `vec!` macro, so we optimize for minimal IR generation + // even in debug builds. + // SAFETY: `Box` and `Box>` have the same layout. + unsafe { core::intrinsics::transmute_unchecked(self) } } /// Writes the value and converts to `Box`. @@ -1234,6 +1295,7 @@ impl Box { /// The raw pointer must point to a block of memory allocated by the global allocator. /// /// The safety conditions are described in the [memory layout] section. + /// Note that the [considerations for unsafe code] apply to all `Box` values. /// /// # Examples /// @@ -1259,6 +1321,7 @@ impl Box { /// ``` /// /// [memory layout]: self#memory-layout + /// [considerations for unsafe code]: self#considerations-for-unsafe-code #[stable(feature = "box_raw", since = "1.4.0")] #[inline] #[must_use = "call `drop(Box::from_raw(ptr))` if you intend to drop the `Box`"] @@ -1283,28 +1346,25 @@ impl Box { /// The non-null pointer must point to a block of memory allocated by the global allocator. /// /// The safety conditions are described in the [memory layout] section. + /// Note that the [considerations for unsafe code] apply to all `Box` values. /// /// # Examples /// /// Recreate a `Box` which was previously converted to a `NonNull` /// pointer using [`Box::into_non_null`]: /// ``` - /// #![feature(box_vec_non_null)] - /// /// let x = Box::new(5); /// let non_null = Box::into_non_null(x); /// let x = unsafe { Box::from_non_null(non_null) }; /// ``` /// Manually create a `Box` from scratch by using the global allocator: /// ``` - /// #![feature(box_vec_non_null)] - /// /// use std::alloc::{alloc, Layout}; /// use std::ptr::NonNull; /// /// unsafe { /// let non_null = NonNull::new(alloc(Layout::new::()).cast::()) - /// .expect("allocation failed"); + /// .expect("alloc should have successfully allocated memory"); /// // In general .write is required to avoid attempting to destruct /// // the (uninitialized) previous contents of `non_null`. /// non_null.write(5); @@ -1313,7 +1373,8 @@ impl Box { /// ``` /// /// [memory layout]: self#memory-layout - #[unstable(feature = "box_vec_non_null", issue = "130364")] + /// [considerations for unsafe code]: self#considerations-for-unsafe-code + #[stable(feature = "box_vec_non_null", since = "1.99.0")] #[inline] #[must_use = "call `drop(Box::from_non_null(ptr))` if you intend to drop the `Box`"] pub unsafe fn from_non_null(ptr: NonNull) -> Self { @@ -1373,9 +1434,13 @@ impl Box { pub fn into_raw(b: Self) -> *mut T { // Avoid `into_raw_with_allocator` as that interacts poorly with Miri's Stacked Borrows. let mut b = mem::ManuallyDrop::new(b); - // We go through the built-in deref for `Box`, which is crucial for Miri to recognize this - // operation for it's alias tracking. - &raw mut **b + // We need to give Miri (specifically, Stacked Borrows) a chance to recognize this as a + // safe-to-raw-pointer cast. To achieve this, we first create a mutable reference, and then + // cast that to a raw pointer -- this cast is recognized by the aliasing model and leads to + // a suitable retag. + // It would be wrong for `into_raw_with_allocator` to do the same as that would induce + // uniqueness assumptions (from the `&mut`) that we only want with the default allocator. + (&mut **b) as *mut T } /// Consumes the `Box`, returning a wrapped `NonNull` pointer. @@ -1398,8 +1463,6 @@ impl Box { /// Converting the `NonNull` pointer back into a `Box` with [`Box::from_non_null`] /// for automatic cleanup: /// ``` - /// #![feature(box_vec_non_null)] - /// /// let x = Box::new(String::from("Hello")); /// let non_null = Box::into_non_null(x); /// let x = unsafe { Box::from_non_null(non_null) }; @@ -1407,8 +1470,6 @@ impl Box { /// Manual cleanup by explicitly running the destructor and deallocating /// the memory: /// ``` - /// #![feature(box_vec_non_null)] - /// /// use std::alloc::{dealloc, Layout}; /// /// let x = Box::new(String::from("Hello")); @@ -1420,8 +1481,6 @@ impl Box { /// ``` /// Note: This is equivalent to the following: /// ``` - /// #![feature(box_vec_non_null)] - /// /// let x = Box::new(String::from("Hello")); /// let non_null = Box::into_non_null(x); /// unsafe { @@ -1431,9 +1490,13 @@ impl Box { /// /// [memory layout]: self#memory-layout #[must_use = "losing the pointer will leak memory"] - #[unstable(feature = "box_vec_non_null", issue = "130364")] + #[stable(feature = "box_vec_non_null", since = "1.99.0")] #[inline] pub fn into_non_null(b: Self) -> NonNull { + // As of August 2026, we cannot utilize `Box::leak` + // because whether or not you can reconstruct the `Box` + // later using `Box::from_raw` or `Box::from_non_null` is + // an open question. // SAFETY: `Box` is guaranteed to be non-null. unsafe { NonNull::new_unchecked(Self::into_raw(b)) } } @@ -1456,6 +1519,9 @@ impl Box { /// /// The raw pointer must point to a block of memory allocated by `alloc`. /// + /// The safety conditions are described in the [memory layout] section. + /// Note that the [considerations for unsafe code] apply to all `Box` values. + /// /// # Examples /// /// Recreate a `Box` which was previously converted to a raw pointer @@ -1487,6 +1553,7 @@ impl Box { /// ``` /// /// [memory layout]: self#memory-layout + /// [considerations for unsafe code]: self#considerations-for-unsafe-code #[unstable(feature = "allocator_api", issue = "32838")] #[inline] pub unsafe fn from_raw_in(raw: *mut T, alloc: A) -> Self { @@ -1509,12 +1576,15 @@ impl Box { /// /// The non-null pointer must point to a block of memory allocated by `alloc`. /// + /// The safety conditions are described in the [memory layout] section. + /// Note that the [considerations for unsafe code] apply to all `Box` values. + /// /// # Examples /// /// Recreate a `Box` which was previously converted to a `NonNull` pointer /// using [`Box::into_non_null_with_allocator`]: /// ``` - /// #![feature(allocator_api, box_vec_non_null)] + /// #![feature(allocator_api)] /// /// use std::alloc::System; /// @@ -1524,7 +1594,7 @@ impl Box { /// ``` /// Manually create a `Box` from scratch by using the system allocator: /// ``` - /// #![feature(allocator_api, box_vec_non_null, slice_ptr_get)] + /// #![feature(allocator_api)] /// /// use std::alloc::{Allocator, Layout, System}; /// @@ -1539,8 +1609,8 @@ impl Box { /// ``` /// /// [memory layout]: self#memory-layout + /// [considerations for unsafe code]: self#considerations-for-unsafe-code #[unstable(feature = "allocator_api", issue = "32838")] - // #[unstable(feature = "box_vec_non_null", issue = "130364")] #[inline] pub unsafe fn from_non_null_in(raw: NonNull, alloc: A) -> Self { // SAFETY: guaranteed by the caller. @@ -1595,8 +1665,9 @@ impl Box { /// [memory layout]: self#memory-layout #[must_use = "losing the pointer will leak memory"] #[unstable(feature = "allocator_api", issue = "32838")] + #[rustc_const_unstable(feature = "const_heap", issue = "79597")] #[inline] - pub fn into_raw_with_allocator(b: Self) -> (*mut T, A) { + pub const fn into_raw_with_allocator(b: Self) -> (*mut T, A) { let mut b = mem::ManuallyDrop::new(b); // We carefully get the raw pointer out in a way that Miri's aliasing model understands what // is happening: using the primitive "deref" of `Box`. In case `A` is *not* `Global`, we @@ -1629,7 +1700,7 @@ impl Box { /// Converting the `NonNull` pointer back into a `Box` with /// [`Box::from_non_null_in`] for automatic cleanup: /// ``` - /// #![feature(allocator_api, box_vec_non_null)] + /// #![feature(allocator_api)] /// /// use std::alloc::System; /// @@ -1640,7 +1711,7 @@ impl Box { /// Manual cleanup by explicitly running the destructor and deallocating /// the memory: /// ``` - /// #![feature(allocator_api, box_vec_non_null)] + /// #![feature(allocator_api)] /// /// use std::alloc::{Allocator, Layout, System}; /// @@ -1655,7 +1726,6 @@ impl Box { /// [memory layout]: self#memory-layout #[must_use = "losing the pointer will leak memory"] #[unstable(feature = "allocator_api", issue = "32838")] - // #[unstable(feature = "box_vec_non_null", issue = "130364")] #[inline] pub fn into_non_null_with_allocator(b: Self) -> (NonNull, A) { let (ptr, alloc) = Box::into_raw_with_allocator(b); @@ -1682,7 +1752,7 @@ impl Box { /// /// This method guarantees that for the purpose of the aliasing model, this method /// does not materialize a reference to the underlying memory, and thus the returned pointer - /// will remain valid when mixed with other calls to [`as_ptr`] and [`as_mut_ptr`]. + /// will remain valid when mixed with other calls to [`as_ptr`], [`as_mut_ptr`], and [`as_non_null`]. /// Note that calling other methods that materialize references to the memory /// may still invalidate this pointer. /// See the example below for how this guarantee can be used. @@ -1692,8 +1762,6 @@ impl Box { /// Due to the aliasing guarantee, the following code is legal: /// /// ```rust - /// #![feature(box_as_ptr)] - /// /// unsafe { /// let mut b = Box::new(0); /// let ptr1 = Box::as_mut_ptr(&mut b); @@ -1707,7 +1775,9 @@ impl Box { /// /// [`as_mut_ptr`]: Self::as_mut_ptr /// [`as_ptr`]: Self::as_ptr - #[unstable(feature = "box_as_ptr", issue = "129090")] + /// [`as_non_null`]: Self::as_non_null + #[must_use] + #[stable(feature = "box_as_ptr", since = "1.98.0")] #[rustc_never_returns_null_ptr] #[rustc_as_ptr] #[inline] @@ -1728,7 +1798,7 @@ impl Box { /// /// This method guarantees that for the purpose of the aliasing model, this method /// does not materialize a reference to the underlying memory, and thus the returned pointer - /// will remain valid when mixed with other calls to [`as_ptr`] and [`as_mut_ptr`]. + /// will remain valid when mixed with other calls to [`as_ptr`], [`as_mut_ptr`], and [`as_non_null`]. /// Note that calling other methods that materialize mutable references to the memory, /// as well as writing to this memory, may still invalidate this pointer. /// See the example below for how this guarantee can be used. @@ -1738,8 +1808,6 @@ impl Box { /// Due to the aliasing guarantee, the following code is legal: /// /// ```rust - /// #![feature(box_as_ptr)] - /// /// unsafe { /// let mut v = Box::new(0); /// let ptr1 = Box::as_ptr(&v); @@ -1756,7 +1824,9 @@ impl Box { /// /// [`as_mut_ptr`]: Self::as_mut_ptr /// [`as_ptr`]: Self::as_ptr - #[unstable(feature = "box_as_ptr", issue = "129090")] + /// [`as_non_null`]: Self::as_non_null + #[must_use] + #[stable(feature = "box_as_ptr", since = "1.98.0")] #[rustc_never_returns_null_ptr] #[rustc_as_ptr] #[inline] @@ -1766,6 +1836,48 @@ impl Box { &raw const **b } + /// Returns a `NonNull` pointer to the `Box`'s contents. + /// + /// The caller must ensure that the `Box` outlives the pointer this + /// function returns, or else it will end up dangling. + /// + /// This method guarantees that for the purpose of the aliasing model, this method + /// does not materialize a reference to the underlying memory, and thus the returned pointer + /// will remain valid when mixed with other calls to [`as_ptr`], [`as_mut_ptr`], and [`as_non_null`]. + /// Note that calling other methods that materialize references to the memory + /// may still invalidate this pointer. + /// See the example below for how this guarantee can be used. + /// + /// # Examples + /// + /// Due to the aliasing guarantee, the following code is legal: + /// + /// ```rust + /// #![feature(box_as_non_null)] + /// + /// unsafe { + /// let mut b = Box::new(0); + /// let ptr1 = Box::as_non_null(&mut b); + /// ptr1.write(1); + /// let ptr2 = Box::as_non_null(&mut b); + /// ptr2.write(2); + /// // Notably, the write to `ptr2` did *not* invalidate `ptr1`: + /// ptr1.write(3); + /// } + /// ``` + /// + /// [`as_mut_ptr`]: Self::as_mut_ptr + /// [`as_ptr`]: Self::as_ptr + /// [`as_non_null`]: Self::as_non_null + #[must_use] + #[unstable(feature = "box_as_non_null", issue = "157345")] + #[rustc_as_ptr] + #[inline] + pub fn as_non_null(b: &mut Self) -> NonNull { + // SAFETY: `Box` is guaranteed to be non-null. + unsafe { NonNull::new_unchecked(Self::as_mut_ptr(b)) } + } + /// Returns a reference to the underlying allocator. /// /// Note: this is an associated function, which means that you have @@ -1784,12 +1896,13 @@ impl Box { /// has only static references, or none at all, then this may be chosen to be /// `'static`. /// - /// This function is mainly useful for data that lives for the remainder of - /// the program's life. Dropping the returned reference will cause a memory - /// leak. If this is not acceptable, the reference should first be wrapped - /// with the [`Box::from_raw`] function producing a `Box`. This `Box` can - /// then be dropped which will properly destroy `T` and release the - /// allocated memory. + /// This function is mainly useful for data that lives for the remainder of the program's life, + /// i.e., memory that is meant to leak. If the memory should eventually be freed, prefer to use + /// [`Box::into_raw`] or [`Box::into_non_null`] instead. Reconstructing ("unleaking") a `Box` from + /// the mutable reference returned here (e.g. via [`Box::from_raw`]) is only possible if the + /// allocator is `Global`, and even then it is a grey area (meaning it is possible under specific + /// circumstances but many seemingly harmless ways of doing it are undefined behavior) and should + /// be avoided. /// /// Note: this is an associated function, which means that you have /// to call it as `Box::leak(b)` instead of `b.leak()`. This @@ -1864,7 +1977,7 @@ impl Box { #[stable(feature = "box_into_pin", since = "1.63.0")] pub fn into_pin(boxed: Self) -> Pin where - A: 'static, + A: StaticAllocator, { // It's not possible to move or replace the insides of a `Pin>` // when `T: !Unpin`, so it's safe to pin it directly without any @@ -1953,6 +2066,8 @@ where #[cfg(not(no_global_oom_handling))] #[stable(feature = "rust1", since = "1.0.0")] +// NB: This is not `AllocatorClone` since we don't care about allocator +// equivalence when cloning boxes. impl Clone for Box { /// Returns a new box with a `clone()` of this box's contents. /// @@ -2029,7 +2144,7 @@ impl Clone for Box<[T], A> { /// ``` fn clone_from(&mut self, source: &Self) { if self.len() == source.len() { - self.clone_from_slice(&source); + self.clone_from_slice(source); } else { *self = source.clone(); } @@ -2038,11 +2153,10 @@ impl Clone for Box<[T], A> { #[cfg(not(no_global_oom_handling))] #[stable(feature = "box_slice_clone", since = "1.3.0")] -impl Clone for Box { +impl Clone for Box { fn clone(&self) -> Self { - // this makes a copy of the data - let buf: Box<[u8]> = self.as_bytes().into(); - unsafe { from_boxed_utf8_unchecked(buf) } + let buf = Box::clone_from_ref_in(self.as_bytes(), self.1.clone()); + unsafe { from_boxed_utf8_unchecked_in(buf) } } } @@ -2181,14 +2295,14 @@ impl Deref for Box { type Target = T; fn deref(&self) -> &T { - &**self + self } } #[stable(feature = "rust1", since = "1.0.0")] impl DerefMut for Box { fn deref_mut(&mut self) -> &mut T { - &mut **self + self } } @@ -2253,8 +2367,27 @@ impl + ?Sized, A: Allocator> AsyncFn for Box #[unstable(feature = "coerce_unsized", issue = "18598")] impl, U: ?Sized, A: Allocator> CoerceUnsized> for Box {} +// A pointer can only be pin safe if it does not implement certain safe traits +// maliciously. Since `Box` is fundamental, downstream crates may be able to +// implement those traits for `Box`, so we must carefully check that +// this is not a problem for each trait. +// +// The `Box` type always implements `Deref` and `DerefMut`, so despite being +// fundamental, downstream crates cannot implement these traits for +// `Box`. +// +// Conversely, downstream crates are able to implement `Clone`, `Debug`, and +// `Display` for `Box` as long as `LocalType` does not implement +// said trait. However, the `Box` type does not treat the existence of an +// `&Box` as evidence that the `T` is not pinned, so this is not +// problematic. +// +// Finally, even if downstream crates provide their own implementation of +// `Clone` for `Box`, it is not problematic for the cloned box to be +// wrapped in `Pin`, since the same conversion could have been carried out +// safely as `Box::pin((*p).clone())`. #[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -unsafe impl PinCoerceUnsized for Box {} +unsafe impl PinSafePointer for Box {} // It is quite crucial that we only allow the `Global` allocator here. // Handling arbitrary custom allocators (which can affect the `Box` layout heavily!) @@ -2265,28 +2398,28 @@ impl, U: ?Sized> DispatchFromDyn> for Box Borrow for Box { fn borrow(&self) -> &T { - &**self + self } } #[stable(feature = "box_borrow", since = "1.1.0")] impl BorrowMut for Box { fn borrow_mut(&mut self) -> &mut T { - &mut **self + self } } #[stable(since = "1.5.0", feature = "smart_ptr_as_ref")] impl AsRef for Box { fn as_ref(&self) -> &T { - &**self + self } } #[stable(since = "1.5.0", feature = "smart_ptr_as_ref")] impl AsMut for Box { fn as_mut(&mut self) -> &mut T { - &mut **self + self } } diff --git a/library/alloc/src/boxed/convert.rs b/library/alloc/src/boxed/convert.rs index d6a8e78991b84..4f5dd89e6e3b3 100644 --- a/library/alloc/src/boxed/convert.rs +++ b/library/alloc/src/boxed/convert.rs @@ -5,7 +5,7 @@ use core::fmt; use core::mem; use core::pin::Pin; -use crate::alloc::Allocator; +use crate::alloc::{Allocator, StaticAllocator}; #[cfg(not(no_global_oom_handling))] use crate::borrow::Cow; use crate::boxed::Box; @@ -38,7 +38,7 @@ impl From for Box { #[stable(feature = "pin", since = "1.33.0")] impl From> for Pin> where - A: 'static, + A: StaticAllocator, { /// Converts a `Box` into a `Pin>`. If `T` does not implement [`Unpin`], then /// `*boxed` will be pinned in memory and unable to be moved. diff --git a/library/alloc/src/boxed/iter.rs b/library/alloc/src/boxed/iter.rs index 90582aa49c6d7..904e7e3c356a7 100644 --- a/library/alloc/src/boxed/iter.rs +++ b/library/alloc/src/boxed/iter.rs @@ -1,18 +1,19 @@ use core::async_iter::AsyncIterator; -use core::iter::FusedIterator; +use core::iter::{FusedIterator, TrustedLen}; +use core::num::NonZero; use core::pin::Pin; use core::slice; use core::task::{Context, Poll}; -use crate::alloc::Allocator; +use crate::alloc::{Allocator, Global}; #[cfg(not(no_global_oom_handling))] use crate::borrow::Cow; use crate::boxed::Box; #[cfg(not(no_global_oom_handling))] use crate::string::String; -use crate::vec; #[cfg(not(no_global_oom_handling))] use crate::vec::Vec; +use crate::{fmt, vec}; #[stable(feature = "rust1", since = "1.0.0")] impl Iterator for Box { @@ -192,3 +193,154 @@ impl<'a> FromIterator> for Box { String::from_iter(iter).into_boxed_str() } } + +/// This implementation is required to make sure that the `Box<[I; N]>: IntoIterator` +/// implementation doesn't overlap with `IntoIterator for T where T: Iterator` blanket. +#[stable(feature = "boxed_array_value_iter", since = "1.99.0")] +impl !Iterator for Box<[I; N], A> {} + +/// This implementation is required to make sure that the `&Box<[I; N]>: IntoIterator` +/// implementation doesn't overlap with `IntoIterator for T where T: Iterator` blanket. +#[stable(feature = "boxed_array_value_iter", since = "1.99.0")] +impl<'a, const N: usize, I, A: Allocator> !Iterator for &'a Box<[I; N], A> {} + +/// This implementation is required to make sure that the `&mut Box<[I; N]>: IntoIterator` +/// implementation doesn't overlap with `IntoIterator for T where T: Iterator` blanket. +#[stable(feature = "boxed_array_value_iter", since = "1.99.0")] +impl<'a, const N: usize, I, A: Allocator> !Iterator for &'a mut Box<[I; N], A> {} + +#[stable(feature = "boxed_array_value_iter", since = "1.99.0")] +impl<'a, T, const N: usize, A: Allocator> IntoIterator for &'a Box<[T; N], A> { + type IntoIter = slice::Iter<'a, T>; + type Item = &'a T; + fn into_iter(self) -> slice::Iter<'a, T> { + self.iter() + } +} + +#[stable(feature = "boxed_array_value_iter", since = "1.99.0")] +impl<'a, T, const N: usize, A: Allocator> IntoIterator for &'a mut Box<[T; N], A> { + type IntoIter = slice::IterMut<'a, T>; + type Item = &'a mut T; + fn into_iter(self) -> slice::IterMut<'a, T> { + self.iter_mut() + } +} + +/// A by-value `Box<[T; N]>` iterator. +#[stable(feature = "boxed_array_value_iter", since = "1.99.0")] +#[rustc_insignificant_dtor] +pub struct BoxedArrayIntoIter { + // FIXME: make a more efficient implementation (without the need to store capacity) + inner: vec::IntoIter, +} + +impl BoxedArrayIntoIter { + /// Returns an immutable slice of all elements that have not been yielded + /// yet. + #[stable(feature = "boxed_array_value_iter", since = "1.99.0")] + pub fn as_slice(&self) -> &[T] { + self.inner.as_slice() + } + + /// Returns a mutable slice of all elements that have not been yielded yet. + #[stable(feature = "boxed_array_value_iter", since = "1.99.0")] + pub fn as_mut_slice(&mut self) -> &mut [T] { + self.inner.as_mut_slice() + } +} + +#[stable(feature = "boxed_array_value_iter", since = "1.99.0")] +impl Iterator for BoxedArrayIntoIter { + type Item = T; + fn next(&mut self) -> Option { + self.inner.next() + } + + fn size_hint(&self) -> (usize, Option) { + let len = self.len(); + (len, Some(len)) + } + + #[inline] + fn fold(self, init: Acc, fold: Fold) -> Acc + where + Fold: FnMut(Acc, Self::Item) -> Acc, + { + self.inner.fold(init, fold) + } + + fn count(self) -> usize { + self.len() + } + + fn last(mut self) -> Option { + self.next_back() + } + + fn advance_by(&mut self, n: usize) -> Result<(), NonZero> { + self.inner.advance_by(n) + } +} + +#[stable(feature = "boxed_array_value_iter", since = "1.99.0")] +impl DoubleEndedIterator for BoxedArrayIntoIter { + fn next_back(&mut self) -> Option { + self.inner.next_back() + } + + #[inline] + fn rfold(self, init: Acc, rfold: Fold) -> Acc + where + Fold: FnMut(Acc, Self::Item) -> Acc, + { + self.inner.rfold(init, rfold) + } + + fn advance_back_by(&mut self, n: usize) -> Result<(), NonZero> { + self.inner.advance_back_by(n) + } +} + +#[stable(feature = "boxed_array_value_iter", since = "1.99.0")] +impl ExactSizeIterator for BoxedArrayIntoIter { + fn len(&self) -> usize { + self.inner.len() + } + + fn is_empty(&self) -> bool { + self.inner.is_empty() + } +} + +#[stable(feature = "boxed_array_value_iter", since = "1.99.0")] +impl FusedIterator for BoxedArrayIntoIter {} + +#[stable(feature = "boxed_array_value_iter", since = "1.99.0")] +unsafe impl TrustedLen for BoxedArrayIntoIter {} + +#[cfg(not(no_global_oom_handling))] +#[stable(feature = "boxed_array_value_iter", since = "1.99.0")] +impl Clone for BoxedArrayIntoIter { + fn clone(&self) -> Self { + Self { inner: self.inner.clone() } + } +} + +#[stable(feature = "boxed_array_value_iter", since = "1.99.0")] +impl fmt::Debug for BoxedArrayIntoIter { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + // Only print the elements that were not yielded yet: we cannot + // access the yielded elements anymore. + f.debug_tuple("BoxedArrayIntoIter").field(&self.as_slice()).finish() + } +} + +#[stable(feature = "boxed_array_value_iter", since = "1.99.0")] +impl IntoIterator for Box<[T; N], A> { + type IntoIter = BoxedArrayIntoIter; + type Item = T; + fn into_iter(self) -> BoxedArrayIntoIter { + BoxedArrayIntoIter { inner: (self as Box<[T], A>).into_vec().into_iter() } + } +} diff --git a/library/alloc/src/boxed/thin.rs b/library/alloc/src/boxed/thin.rs index b50810b8d923d..22c3d89e3ccdb 100644 --- a/library/alloc/src/boxed/thin.rs +++ b/library/alloc/src/boxed/thin.rs @@ -10,7 +10,8 @@ use core::marker::PhantomData; #[cfg(not(no_global_oom_handling))] use core::marker::Unsize; #[cfg(not(no_global_oom_handling))] -use core::mem::{self, SizedTypeProperties}; +use core::mem; +use core::mem::SizedTypeProperties; use core::ops::{Deref, DerefMut}; use core::ptr::{self, NonNull, Pointee}; @@ -112,7 +113,7 @@ impl ThinBox { where T: Unsize, { - if size_of::() == 0 { + if T::IS_ZST { let ptr = WithOpaqueHeader::new_unsize_zst::(value); ThinBox { ptr, _marker: PhantomData } } else { @@ -281,7 +282,7 @@ impl WithHeader { let ptr = if layout.size() == 0 { // Some paranoia checking, mostly so that the ThinBox tests are // more able to catch issues. - debug_assert!(value_offset == 0 && size_of::() == 0 && size_of::() == 0); + debug_assert!(value_offset == 0 && T::IS_ZST && H::IS_ZST); layout.dangling_ptr() } else { let ptr = alloc::alloc(layout); @@ -311,7 +312,7 @@ impl WithHeader { Dyn: Pointee + ?Sized, T: Unsize, { - assert!(size_of::() == 0); + assert!(T::IS_ZST); const fn max(a: usize, b: usize) -> usize { if a > b { a } else { b } @@ -430,3 +431,12 @@ impl Error for ThinBox { self.deref().source() } } + +#[cfg(not(no_global_oom_handling))] +#[unstable(feature = "thin_box", issue = "92791")] +impl From for ThinBox { + #[inline(always)] + fn from(value: T) -> Self { + Self::new(value) + } +} diff --git a/library/alloc/src/bstr.rs b/library/alloc/src/bstr.rs index 338c7ac7f8876..9aa3064da886f 100644 --- a/library/alloc/src/bstr.rs +++ b/library/alloc/src/bstr.rs @@ -12,7 +12,7 @@ use core::ops::{ Deref, DerefMut, DerefPure, Index, IndexMut, Range, RangeFrom, RangeFull, RangeInclusive, RangeTo, RangeToInclusive, }; -use core::str::FromStr; +use core::str::{FromStr, Utf8Error}; use core::{fmt, hash}; use crate::borrow::{Cow, ToOwned}; @@ -61,6 +61,24 @@ impl ByteString { pub(crate) fn as_mut_bytestr(&mut self) -> &mut ByteStr { ByteStr::from_bytes_mut(&mut self.0) } + /// Try to get a `String` representation of the `&ByteString`, if it is + /// valid UTF-8. + /// + /// This method is named `to_string()` because we want `ByteString` to + /// implement `Display`, but the `ToString` trait has a blanket + /// implementation for types that implement `Display`, and the trait version + /// will use the Unicode replacement character rather than returning a + /// `Result` and allowing for the possibility of the content not being UTF-8. + #[unstable(feature = "bstr_to_string", issue = "134915")] + #[rustc_allow_incoherent_impl] + pub fn to_string(&self) -> Result { + // Avoid allocating a copy of the contents for invalid UTF-8 + if let Err(e) = str::from_utf8(&self.0) { + return Err(e); + } + // SAFETY: we just checked that the contents are valid UTF-8 + Ok(unsafe { String::from_utf8_unchecked(self.0.clone()) }) + } } #[unstable(feature = "bstr", issue = "134915")] @@ -92,7 +110,7 @@ impl fmt::Debug for ByteString { } } -#[unstable(feature = "bstr", issue = "134915")] +#[unstable(feature = "bstr_to_string", issue = "134915")] impl fmt::Display for ByteString { #[inline] fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { @@ -477,9 +495,8 @@ impl PartialEq for ByteString { macro_rules! impl_partial_eq_ord_cow { ($lhs:ty, $rhs:ty) => { - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] - impl<'a> PartialEq<$rhs> for $lhs { + impl PartialEq<$rhs> for $lhs { #[inline] fn eq(&self, other: &$rhs) -> bool { let other: &[u8] = (&**other).as_ref(); @@ -487,9 +504,8 @@ macro_rules! impl_partial_eq_ord_cow { } } - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] - impl<'a> PartialEq<$lhs> for $rhs { + impl PartialEq<$lhs> for $rhs { #[inline] fn eq(&self, other: &$lhs) -> bool { let this: &[u8] = (&**self).as_ref(); @@ -497,9 +513,8 @@ macro_rules! impl_partial_eq_ord_cow { } } - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] - impl<'a> PartialOrd<$rhs> for $lhs { + impl PartialOrd<$rhs> for $lhs { #[inline] fn partial_cmp(&self, other: &$rhs) -> Option { let other: &[u8] = (&**other).as_ref(); @@ -507,9 +522,8 @@ macro_rules! impl_partial_eq_ord_cow { } } - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] - impl<'a> PartialOrd<$lhs> for $rhs { + impl PartialOrd<$lhs> for $rhs { #[inline] fn partial_cmp(&self, other: &$lhs) -> Option { let this: &[u8] = (&**self).as_ref(); @@ -667,9 +681,9 @@ impl From> for Arc<[u8]> { impl_partial_eq!(ByteStr, Vec); // PartialOrd with `String` omitted to avoid inference failures impl_partial_eq!(ByteStr, String); -impl_partial_eq_ord_cow!(&'a ByteStr, Cow<'a, ByteStr>); -impl_partial_eq_ord_cow!(&'a ByteStr, Cow<'a, str>); -impl_partial_eq_ord_cow!(&'a ByteStr, Cow<'a, [u8]>); +impl_partial_eq_ord_cow!(&ByteStr, Cow<'_, ByteStr>); +impl_partial_eq_ord_cow!(&ByteStr, Cow<'_, str>); +impl_partial_eq_ord_cow!(&ByteStr, Cow<'_, [u8]>); #[unstable(feature = "bstr", issue = "134915")] impl<'a> TryFrom<&'a ByteStr> for String { @@ -680,3 +694,24 @@ impl<'a> TryFrom<&'a ByteStr> for String { Ok(core::str::from_utf8(&s.0)?.into()) } } + +impl ByteStr { + /// Try to get a `String` representation of the `&ByteStr`, if it is valid + /// UTF-8. + /// + /// This method is named `to_string()` because we want `ByteStr` to + /// implement `Display`, but the `ToString` trait has a blanket + /// implementation for types that implement `Display`, and the trait version + /// will use the Unicode replacement character rather than returning a + /// `Result` and allowing for the possibility of the content not being UTF-8. + #[unstable(feature = "bstr_to_string", issue = "134915")] + #[rustc_allow_incoherent_impl] + pub fn to_string(&self) -> Result { + // Avoid allocating a copy of the contents for invalid UTF-8 + if let Err(e) = str::from_utf8(&self.0) { + return Err(e); + } + // SAFETY: we just checked that the contents are valid UTF-8 + Ok(unsafe { String::from_utf8_unchecked(self.0.to_vec()) }) + } +} diff --git a/library/alloc/src/collections/binary_heap/mod.rs b/library/alloc/src/collections/binary_heap/mod.rs index 97aafbc7b6994..98192e1fb5b01 100644 --- a/library/alloc/src/collections/binary_heap/mod.rs +++ b/library/alloc/src/collections/binary_heap/mod.rs @@ -549,8 +549,8 @@ impl BinaryHeap { /// /// use std::alloc::System; /// use std::collections::BinaryHeap; - /// let mut heap = BinaryHeap::new_in(System); - /// heap.push(4); + /// + /// let heap : BinaryHeap = BinaryHeap::new_in(System); /// ``` #[unstable(feature = "allocator_api", issue = "32838")] #[must_use] @@ -573,14 +573,48 @@ impl BinaryHeap { /// /// use std::alloc::System; /// use std::collections::BinaryHeap; - /// let mut heap = BinaryHeap::with_capacity_in(10, System); - /// heap.push(4); + /// + /// let heap: BinaryHeap = BinaryHeap::with_capacity_in(10, System); /// ``` #[unstable(feature = "allocator_api", issue = "32838")] #[must_use] pub fn with_capacity_in(capacity: usize, alloc: A) -> BinaryHeap { BinaryHeap { data: Vec::with_capacity_in(capacity, alloc) } } + + /// Creates a `BinaryHeap` using the supplied `vec`. This does not rebuild the heap, + /// so `vec` must already be a max-heap. + /// + /// # Safety + /// + /// The supplied `vec` must be a max-heap, i.e. for all indices `0 < i < vec.len()`, + /// `vec[(i - 1) / 2] >= vec[i]`. + /// + /// # Examples + /// + /// Basic usage: + /// + /// ``` + /// #![feature(binary_heap_from_raw_vec)] + /// + /// use std::collections::BinaryHeap; + /// let heap = BinaryHeap::from([1, 2, 3]); + /// let vec = heap.into_vec(); + /// + /// // Safety: vec is the output of heap.from_vec(), so is a max-heap. + /// let mut new_heap = unsafe { + /// BinaryHeap::from_raw_vec(vec) + /// }; + /// assert_eq!(new_heap.pop(), Some(3)); + /// assert_eq!(new_heap.pop(), Some(2)); + /// assert_eq!(new_heap.pop(), Some(1)); + /// assert_eq!(new_heap.pop(), None); + /// ``` + #[unstable(feature = "binary_heap_from_raw_vec", issue = "152500")] + #[must_use] + pub unsafe fn from_raw_vec(vec: Vec) -> BinaryHeap { + BinaryHeap { data: vec } + } } impl BinaryHeap { @@ -1224,7 +1258,7 @@ impl BinaryHeap { /// /// Ok(heap.pop()) /// } - /// # find_max_slow(&[1, 2, 3]).expect("why is the test harness OOMing on 12 bytes?"); + /// # find_max_slow(&[1, 2, 3]).expect("reserving capacity for 12 bytes should never fail"); /// ``` #[stable(feature = "try_reserve_2", since = "1.63.0")] pub fn try_reserve_exact(&mut self, additional: usize) -> Result<(), TryReserveError> { @@ -1260,7 +1294,7 @@ impl BinaryHeap { /// /// Ok(heap.pop()) /// } - /// # find_max_slow(&[1, 2, 3]).expect("why is the test harness OOMing on 12 bytes?"); + /// # find_max_slow(&[1, 2, 3]).expect("reserving capacity for 12 bytes should never fail"); /// ``` #[stable(feature = "try_reserve_2", since = "1.63.0")] pub fn try_reserve(&mut self, additional: usize) -> Result<(), TryReserveError> { @@ -1330,6 +1364,37 @@ impl BinaryHeap { self.data.as_slice() } + /// Returns a mutable slice of all values in the underlying vector. + /// + /// # Safety + /// + /// The caller must ensure that the slice remains a max-heap, i.e. for all indices + /// `0 < i < slice.len()`, `slice[(i - 1) / 2] >= slice[i]`, before the borrow ends + /// and the binary heap is used. + /// + /// # Examples + /// + /// Basic usage: + /// + /// ``` + /// #![feature(binary_heap_as_mut_slice)] + /// + /// use std::collections::BinaryHeap; + /// + /// let mut heap = BinaryHeap::::from([1, 2, 3, 4, 5, 6, 7]); + /// + /// unsafe { + /// for value in heap.as_mut_slice() { + /// *value = (*value).saturating_mul(2); + /// } + /// } + /// ``` + #[must_use] + #[unstable(feature = "binary_heap_as_mut_slice", issue = "154009")] + pub unsafe fn as_mut_slice(&mut self) -> &mut [T] { + self.data.as_mut_slice() + } + /// Consumes the `BinaryHeap` and returns the underlying vector /// in arbitrary order. /// diff --git a/library/alloc/src/collections/btree/append.rs b/library/alloc/src/collections/btree/append.rs index 66ea22e75247c..cc8d793e98e4d 100644 --- a/library/alloc/src/collections/btree/append.rs +++ b/library/alloc/src/collections/btree/append.rs @@ -1,38 +1,8 @@ use core::alloc::Allocator; -use core::iter::FusedIterator; -use super::merge_iter::MergeIterInner; use super::node::{self, Root}; impl Root { - /// Appends all key-value pairs from the union of two ascending iterators, - /// incrementing a `length` variable along the way. The latter makes it - /// easier for the caller to avoid a leak when a drop handler panicks. - /// - /// If both iterators produce the same key, this method drops the pair from - /// the left iterator and appends the pair from the right iterator. - /// - /// If you want the tree to end up in a strictly ascending order, like for - /// a `BTreeMap`, both iterators should produce keys in strictly ascending - /// order, each greater than all keys in the tree, including any keys - /// already in the tree upon entry. - pub(super) fn append_from_sorted_iters( - &mut self, - left: I, - right: I, - length: &mut usize, - alloc: A, - ) where - K: Ord, - I: Iterator + FusedIterator, - { - // We prepare to merge `left` and `right` into a sorted sequence in linear time. - let iter = MergeIter(MergeIterInner::new(left, right)); - - // Meanwhile, we build a tree from the sorted sequence in linear time. - self.bulk_push(iter, length, alloc) - } - /// Pushes all key-value pairs to the end of the tree, incrementing a /// `length` variable along the way. The latter makes it easier for the /// caller to avoid a leak when the iterator panicks. @@ -94,24 +64,3 @@ impl Root { self.fix_right_border_of_plentiful(); } } - -// An iterator for merging two sorted sequences into one -struct MergeIter>(MergeIterInner); - -impl Iterator for MergeIter -where - I: Iterator + FusedIterator, -{ - type Item = (K, V); - - /// If two keys are equal, returns the key from the left and the value from the right. - fn next(&mut self) -> Option<(K, V)> { - let (a_next, b_next) = self.0.nexts(|a: &(K, V), b: &(K, V)| K::cmp(&a.0, &b.0)); - match (a_next, b_next) { - (Some((a_k, _)), Some((_, b_v))) => Some((a_k, b_v)), - (Some(a), None) => Some(a), - (None, Some(b)) => Some(b), - (None, None) => None, - } - } -} diff --git a/library/alloc/src/collections/btree/map.rs b/library/alloc/src/collections/btree/map.rs index 426be364a56b0..d8421d3c3f70a 100644 --- a/library/alloc/src/collections/btree/map.rs +++ b/library/alloc/src/collections/btree/map.rs @@ -684,15 +684,14 @@ impl BTreeMap { /// ``` /// # #![feature(allocator_api)] /// # #![feature(btreemap_alloc)] + /// /// use std::collections::BTreeMap; /// use std::alloc::Global; /// - /// let mut map = BTreeMap::new_in(Global); - /// - /// // entries can now be inserted into the empty map - /// map.insert(1, "a"); + /// let map: BTreeMap = BTreeMap::new_in(Global); /// ``` #[unstable(feature = "btreemap_alloc", issue = "32838")] + #[must_use] pub const fn new_in(alloc: A) -> BTreeMap { BTreeMap { root: None, length: 0, alloc: ManuallyDrop::new(alloc), _marker: PhantomData } } @@ -1060,7 +1059,7 @@ impl BTreeMap { /// a mutable reference to the value in the entry. /// /// If the map already had this key present, nothing is updated, and - /// an error containing the occupied entry and the value is returned. + /// an error containing the occupied entry, key, and the value is returned. /// /// # Examples /// @@ -1075,6 +1074,7 @@ impl BTreeMap { /// let err = map.try_insert(37, "b").unwrap_err(); /// assert_eq!(err.entry.key(), &37); /// assert_eq!(err.entry.get(), &"a"); + /// assert_eq!(err.key, 37); /// assert_eq!(err.value, "b"); /// ``` #[unstable(feature = "map_try_insert", issue = "82766")] @@ -1082,10 +1082,30 @@ impl BTreeMap { where K: Ord, { - match self.entry(key) { - Occupied(entry) => Err(OccupiedError { entry, value }), - Vacant(entry) => Ok(entry.insert(value)), - } + let (map, dormant_map) = DormantMutRef::new(self); + let handle = match map.root { + Some(ref mut root) => match root.borrow_mut().search_tree(&key) { + Found(handle) => { + let entry = OccupiedEntry { + handle, + dormant_map, + alloc: (*map.alloc).clone(), + _marker: PhantomData, + }; + return Err(OccupiedError { entry, key, value }); + } + GoDown(handle) => Some(handle), + }, + None => None, + }; + let entry = VacantEntry { + key, + handle, + dormant_map, + alloc: (*map.alloc).clone(), + _marker: PhantomData, + }; + Ok(entry.insert(value)) } /// Removes a key from the map, returning the value at the key if the key @@ -1214,6 +1234,61 @@ impl BTreeMap { /// ``` #[stable(feature = "btree_append", since = "1.11.0")] pub fn append(&mut self, other: &mut Self) + where + K: Ord, + A: Clone, + { + let other = mem::replace(other, Self::new_in((*self.alloc).clone())); + self.merge(other, |_key, _self_val, other_val| other_val); + } + + /// Moves all elements from `other` into `self`, leaving `other` empty. + /// + /// If a key from `other` is already present in `self`, then the `conflict` + /// closure is used to return a value to `self`. The `conflict` + /// closure takes in a borrow of `self`'s key, `self`'s value, and `other`'s value + /// in that order. + /// + /// An example of why one might use this method over [`append`] + /// is to combine `self`'s value with `other`'s value when their keys conflict. + /// + /// Similar to [`insert`], though, the key is not overwritten, + /// which matters for types that can be `==` without being identical. + /// + /// [`insert`]: BTreeMap::insert + /// [`append`]: BTreeMap::append + /// + /// # Examples + /// + /// ``` + /// #![feature(btree_merge)] + /// use std::collections::BTreeMap; + /// + /// let mut a = BTreeMap::new(); + /// a.insert(1, String::from("a")); + /// a.insert(2, String::from("b")); + /// a.insert(3, String::from("c")); // Note: Key (3) also present in b. + /// + /// let mut b = BTreeMap::new(); + /// b.insert(3, String::from("d")); // Note: Key (3) also present in a. + /// b.insert(4, String::from("e")); + /// b.insert(5, String::from("f")); + /// + /// // concatenate a's value and b's value + /// a.merge(b, |_, a_val, b_val| { + /// format!("{a_val}{b_val}") + /// }); + /// + /// assert_eq!(a.len(), 5); // all of b's keys in a + /// + /// assert_eq!(a[&1], "a"); + /// assert_eq!(a[&2], "b"); + /// assert_eq!(a[&3], "cd"); // Note: "c" has been combined with "d". + /// assert_eq!(a[&4], "e"); + /// assert_eq!(a[&5], "f"); + /// ``` + #[unstable(feature = "btree_merge", issue = "152152")] + pub fn merge(&mut self, mut other: Self, mut conflict: impl FnMut(&K, V, V) -> V) where K: Ord, A: Clone, @@ -1225,19 +1300,102 @@ impl BTreeMap { // We can just swap `self` and `other` if `self` is empty. if self.is_empty() { - mem::swap(self, other); + mem::swap(self, &mut other); return; } - let self_iter = mem::replace(self, Self::new_in((*self.alloc).clone())).into_iter(); - let other_iter = mem::replace(other, Self::new_in((*self.alloc).clone())).into_iter(); - let root = self.root.get_or_insert_with(|| Root::new((*self.alloc).clone())); - root.append_from_sorted_iters( - self_iter, - other_iter, - &mut self.length, - (*self.alloc).clone(), - ) + let mut other_iter = other.into_iter(); + let (first_other_key, first_other_val) = other_iter.next().unwrap(); + + // find the first gap that has the smallest key greater than or equal to + // the first key from other + let mut self_cursor = self.lower_bound_mut(Bound::Included(&first_other_key)); + + if let Some((self_key, _)) = self_cursor.peek_next() { + match K::cmp(self_key, &first_other_key) { + Ordering::Equal => { + // if `f` unwinds, the next entry is already removed leaving + // the tree in valid state. + // FIXME: Once `MaybeDangling` is implemented, we can optimize + // this through using a drop handler and transmutating CursorMutKey + // to CursorMutKey, ManuallyDrop> (see PR #152418) + if let Some((k, v)) = self_cursor.remove_next() { + // SAFETY: we remove the K, V out of the next entry, + // apply 'f' to get a new (K, V), and insert it back + // into the next entry that the cursor is pointing at + let v = conflict(&k, v, first_other_val); + unsafe { self_cursor.insert_after_unchecked(k, v) }; + } + } + Ordering::Greater => + // SAFETY: we know our other_key's ordering is less than self_key, + // so inserting before will guarantee sorted order + unsafe { + self_cursor.insert_before_unchecked(first_other_key, first_other_val); + }, + Ordering::Less => { + unreachable!("Cursor's peek_next should return None."); + } + } + } else { + // SAFETY: reaching here means our cursor is at the end + // self BTreeMap so we just insert other_key here + unsafe { + self_cursor.insert_before_unchecked(first_other_key, first_other_val); + } + } + + for (other_key, other_val) in other_iter { + loop { + if let Some((self_key, _)) = self_cursor.peek_next() { + match K::cmp(self_key, &other_key) { + Ordering::Equal => { + // if `f` unwinds, the next entry is already removed leaving + // the tree in valid state. + // FIXME: Once `MaybeDangling` is implemented, we can optimize + // this through using a drop handler and transmutating CursorMutKey + // to CursorMutKey, ManuallyDrop> (see PR #152418) + if let Some((k, v)) = self_cursor.remove_next() { + // SAFETY: we remove the K, V out of the next entry, + // apply 'f' to get a new (K, V), and insert it back + // into the next entry that the cursor is pointing at + let v = conflict(&k, v, other_val); + unsafe { self_cursor.insert_after_unchecked(k, v) }; + } + break; + } + Ordering::Greater => { + // SAFETY: we know our self_key's ordering is greater than other_key, + // so inserting before will guarantee sorted order + unsafe { + self_cursor.insert_before_unchecked(other_key, other_val); + } + break; + } + Ordering::Less => { + // FIXME: instead of doing a linear search here, + // this can be optimized to search the tree by starting + // from self_cursor and going towards the root and then + // back down to the proper node -- that should probably + // be a new method on Cursor*. + self_cursor.next(); + } + } + } else { + // FIXME: If we get here, that means all of other's keys are greater than + // self's keys. For performance, this should really do a bulk insertion of items + // from other_iter into the end of self `BTreeMap`. Maybe this should be + // a method for Cursor*? + + // SAFETY: reaching here means our cursor is at the end + // self BTreeMap so we just insert other_key here + unsafe { + self_cursor.insert_before_unchecked(other_key, other_val); + } + break; + } + } + } } /// Constructs a double-ended iterator over a sub-range of elements in the map. @@ -1414,7 +1572,7 @@ impl BTreeMap { let right_root = left_root.split_off(key, (*self.alloc).clone()); - let (new_left_len, right_len) = Root::calc_split_length(total_num, &left_root, &right_root); + let (new_left_len, right_len) = Root::calc_split_length(total_num, left_root, &right_root); self.length = new_left_len; BTreeMap { @@ -1963,7 +2121,9 @@ impl Default for Values<'_, K, V> { } } -/// An iterator produced by calling `extract_if` on BTreeMap. +/// This `struct` is created by the [`extract_if`] method on [`BTreeMap`]. +/// +/// [`extract_if`]: BTreeMap::extract_if #[stable(feature = "btree_extract_if", since = "1.91.0")] #[must_use = "iterators are lazy and do nothing unless consumed; \ use `retain` or `extract_if().for_each(drop)` to remove and discard elements"] @@ -2048,8 +2208,8 @@ impl<'a, K, V, R> ExtractIfInner<'a, K, V, R> { // On creation, we navigated directly to the left bound, so we need only check the // right bound here to decide whether to stop. match self.range.end_bound() { - Bound::Included(ref end) if (*k).le(end) => (), - Bound::Excluded(ref end) if (*k).lt(end) => (), + Bound::Included(end) if (*k).le(end) => (), + Bound::Excluded(end) if (*k).lt(end) => (), Bound::Unbounded => (), _ => return None, } @@ -2434,7 +2594,8 @@ impl Hash for BTreeMap { } #[stable(feature = "rust1", since = "1.0.0")] -impl Default for BTreeMap { +#[rustc_const_unstable(feature = "const_default", issue = "143894")] +const impl Default for BTreeMap { /// Creates an empty `BTreeMap`. fn default() -> BTreeMap { BTreeMap::new() diff --git a/library/alloc/src/collections/btree/map/entry.rs b/library/alloc/src/collections/btree/map/entry.rs index add8782a9499a..1c2ad5c568e6a 100644 --- a/library/alloc/src/collections/btree/map/entry.rs +++ b/library/alloc/src/collections/btree/map/entry.rs @@ -97,8 +97,9 @@ impl Debug for OccupiedEntry<'_, /// The error returned by [`try_insert`](BTreeMap::try_insert) when the key already exists. /// -/// Contains the occupied entry, and the value that was not inserted. +/// Contains the occupied entry, key, and the value that was not inserted. #[unstable(feature = "map_try_insert", issue = "82766")] +#[non_exhaustive] pub struct OccupiedError< 'a, K: 'a, @@ -107,6 +108,8 @@ pub struct OccupiedError< > { /// The entry in the map that was already occupied. pub entry: OccupiedEntry<'a, K, V, A>, + /// The key which was not inserted, because the entry was already occupied. + pub key: K, /// The value which was not inserted, because the entry was already occupied. pub value: V, } @@ -116,33 +119,13 @@ impl Debug for OccupiedError<'_, fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { f.debug_struct("OccupiedError") .field("key", self.entry.key()) + .field("uninserted_key", &self.key) .field("old_value", self.entry.get()) .field("new_value", &self.value) .finish() } } -#[unstable(feature = "map_try_insert", issue = "82766")] -impl<'a, K: Debug + Ord, V: Debug, A: Allocator + Clone> fmt::Display - for OccupiedError<'a, K, V, A> -{ - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - write!( - f, - "failed to insert {:?}, key {:?} already exists with value {:?}", - self.value, - self.entry.key(), - self.entry.get(), - ) - } -} - -#[unstable(feature = "map_try_insert", issue = "82766")] -impl<'a, K: core::fmt::Debug + Ord, V: core::fmt::Debug> core::error::Error - for crate::collections::btree_map::OccupiedError<'a, K, V> -{ -} - impl<'a, K: Ord, V, A: Allocator + Clone> Entry<'a, K, V, A> { /// Ensures a value is in the entry by inserting the default if empty, and returns /// a mutable reference to the value in the entry. @@ -182,9 +165,42 @@ impl<'a, K: Ord, V, A: Allocator + Clone> Entry<'a, K, V, A> { /// ``` #[stable(feature = "rust1", since = "1.0.0")] pub fn or_insert_with V>(self, default: F) -> &'a mut V { + self.or_try_insert_with(|| Result::<_, !>::Ok(default())).unwrap() + } + + /// Ensures a value is in the entry by inserting the result of a fallible default function + /// if empty, and returns a mutable reference to the value in the entry. + /// + /// This method works identically to [`or_insert_with`] except that the default function + /// should return a `Result` and, in the case of an error, the error is propagated. + /// + /// [`or_insert_with`]: Self::or_insert_with + /// + /// # Examples + /// + /// ``` + /// #![feature(try_entry)] + /// # fn main() -> Result<(), std::num::ParseIntError> { + /// use std::collections::BTreeMap; + /// + /// let mut map: BTreeMap<&str, usize> = BTreeMap::new(); + /// let value = "42"; + /// + /// map.entry("poneyland").or_try_insert_with(|| value.parse())?; + /// + /// assert_eq!(map["poneyland"], 42); + /// # Ok(()) + /// # } + /// ``` + #[inline] + #[unstable(feature = "try_entry", issue = "157354")] + pub fn or_try_insert_with Result, E>( + self, + default: F, + ) -> Result<&'a mut V, E> { match self { - Occupied(entry) => entry.into_mut(), - Vacant(entry) => entry.insert(default()), + Occupied(entry) => Ok(entry.into_mut()), + Vacant(entry) => Ok(entry.insert(default()?)), } } @@ -210,11 +226,44 @@ impl<'a, K: Ord, V, A: Allocator + Clone> Entry<'a, K, V, A> { #[inline] #[stable(feature = "or_insert_with_key", since = "1.50.0")] pub fn or_insert_with_key V>(self, default: F) -> &'a mut V { + self.or_try_insert_with_key(|k| Result::<_, !>::Ok(default(k))).into_ok() + } + + /// Ensures a value is in the entry by inserting, if empty, the result of the default function. + /// This method allows for generating key-derived values for insertion by providing the default + /// function a reference to the key that was moved during the `entry(key)` method call. + /// + /// This method works identically to [`or_insert_with_key`] except that the default function + /// should return a `Result` and, in the case of an error, the error is propagated. + /// + /// [`or_insert_with_key`]: Self::or_insert_with_key + /// + /// # Examples + /// + /// ``` + /// #![feature(try_entry)] + /// # fn main() -> Result<(), std::num::ParseIntError> { + /// use std::collections::BTreeMap; + /// + /// let mut map: BTreeMap<&str, usize> = BTreeMap::new(); + /// + /// map.entry("42").or_try_insert_with_key(|key| key.parse())?; + /// + /// assert_eq!(map["42"], 42); + /// # Ok(()) + /// # } + /// ``` + #[inline] + #[unstable(feature = "try_entry", issue = "157354")] + pub fn or_try_insert_with_key Result, E>( + self, + default: F, + ) -> Result<&'a mut V, E> { match self { - Occupied(entry) => entry.into_mut(), + Occupied(entry) => Ok(entry.into_mut()), Vacant(entry) => { - let value = default(entry.key()); - entry.insert(value) + let value = default(entry.key())?; + Ok(entry.insert(value)) } } } diff --git a/library/alloc/src/collections/btree/map/tests.rs b/library/alloc/src/collections/btree/map/tests.rs index 938e867b85812..64348745aa07d 100644 --- a/library/alloc/src/collections/btree/map/tests.rs +++ b/library/alloc/src/collections/btree/map/tests.rs @@ -1,9 +1,9 @@ use core::assert_matches; -use std::iter; use std::ops::Bound::{Excluded, Included, Unbounded}; use std::panic::{AssertUnwindSafe, catch_unwind}; use std::sync::atomic::AtomicUsize; use std::sync::atomic::Ordering::SeqCst; +use std::{cmp, iter}; use super::*; use crate::boxed::Box; @@ -2128,6 +2128,86 @@ create_append_test!(test_append_239, 239); #[cfg(not(miri))] // Miri is too slow create_append_test!(test_append_1700, 1700); +// a inserts (0, 0)..(8, 8) to its own tree +// b inserts (5, 5 * 2)..($len, 2 * $len) to its own tree +// note that between a and b, there are duplicate keys +// between 5..min($len, 8), so on merge we add the values +// of these keys together +// we check that: +// - the merged tree 'a' has a length of max(8, $len) +// - all keys in 'a' have the correct value associated +// - removing and inserting an element into the merged +// tree 'a' still keeps it in valid tree form +macro_rules! create_merge_test { + ($name:ident, $len:expr) => { + #[test] + fn $name() { + let mut a = BTreeMap::new(); + for i in 0..8 { + a.insert(i, i); + } + + let mut b = BTreeMap::new(); + for i in 5..$len { + b.insert(i, 2 * i); + } + + a.merge(b, |_, a_val, b_val| a_val + b_val); + + assert_eq!(a.len(), cmp::max($len, 8)); + + for i in 0..cmp::max($len, 8) { + if i < 5 { + assert_eq!(a[&i], i); + } else { + if i < cmp::min($len, 8) { + assert_eq!(a[&i], i + 2 * i); + } else if i >= $len { + assert_eq!(a[&i], i); + } else { + assert_eq!(a[&i], 2 * i); + } + } + } + + a.check(); + assert_eq!( + a.remove(&($len - 1)), + if $len >= 5 && $len < 8 { + Some(($len - 1) + 2 * ($len - 1)) + } else { + Some(2 * ($len - 1)) + } + ); + assert_eq!(a.insert($len - 1, 20), None); + a.check(); + } + }; +} + +// These are mostly for testing the algorithm that "fixes" the right edge after insertion. +// Single node, merge conflicting key values. +create_merge_test!(test_merge_7, 7); +// Single node. +create_merge_test!(test_merge_9, 9); +// Two leafs that don't need fixing. +create_merge_test!(test_merge_17, 17); +// Two leafs where the second one ends up underfull and needs stealing at the end. +create_merge_test!(test_merge_14, 14); +// Two leafs where the second one ends up empty because the insertion finished at the root. +create_merge_test!(test_merge_12, 12); +// Three levels; insertion finished at the root. +create_merge_test!(test_merge_144, 144); +// Three levels; insertion finished at leaf while there is an empty node on the second level. +create_merge_test!(test_merge_145, 145); +// Tests for several randomly chosen sizes. +create_merge_test!(test_merge_170, 170); +create_merge_test!(test_merge_181, 181); +#[cfg(not(miri))] // Miri is too slow +create_merge_test!(test_merge_239, 239); +#[cfg(not(miri))] // Miri is too slow +create_merge_test!(test_merge_1700, 1700); + #[test] #[cfg_attr(not(panic = "unwind"), ignore = "test requires unwinding support")] fn test_append_drop_leak() { @@ -2144,7 +2224,7 @@ fn test_append_drop_leak() { catch_unwind(move || left.append(&mut right)).unwrap_err(); assert_eq!(a.dropped(), 1); - assert_eq!(b.dropped(), 1); // should be 2 were it not for Rust issue #47949 + assert_eq!(b.dropped(), 2); assert_eq!(c.dropped(), 2); } @@ -2169,6 +2249,84 @@ fn test_append_ord_chaos() { map2.check(); } +#[test] +#[cfg_attr(not(panic = "unwind"), ignore = "test requires unwinding support")] +fn test_merge_drop_leak() { + let a = CrashTestDummy::new(0); + let b = CrashTestDummy::new(1); + let c = CrashTestDummy::new(2); + let mut left = BTreeMap::new(); + let mut right = BTreeMap::new(); + left.insert(a.spawn(Panic::Never), ()); + left.insert(b.spawn(Panic::Never), ()); + left.insert(c.spawn(Panic::Never), ()); + right.insert(b.spawn(Panic::InDrop), ()); // first duplicate key, dropped during merge + right.insert(c.spawn(Panic::Never), ()); + + catch_unwind(move || left.merge(right, |_, _, _| ())).unwrap_err(); + assert_eq!(a.dropped(), 1); // this should not be dropped + assert_eq!(b.dropped(), 2); // key is dropped on panic + assert_eq!(c.dropped(), 2); // key is dropped on panic +} + +#[test] +#[cfg_attr(not(panic = "unwind"), ignore = "test requires unwinding support")] +fn test_merge_conflict_drop_leak() { + let a = CrashTestDummy::new(0); + let a_val_left = CrashTestDummy::new(0); + + let b = CrashTestDummy::new(1); + let b_val_left = CrashTestDummy::new(1); + let b_val_right = CrashTestDummy::new(1); + + let c = CrashTestDummy::new(2); + let c_val_left = CrashTestDummy::new(2); + let c_val_right = CrashTestDummy::new(2); + + let mut left = BTreeMap::new(); + let mut right = BTreeMap::new(); + + left.insert(a.spawn(Panic::Never), a_val_left.spawn(Panic::Never)); + left.insert(b.spawn(Panic::Never), b_val_left.spawn(Panic::Never)); + left.insert(c.spawn(Panic::Never), c_val_left.spawn(Panic::Never)); + right.insert(b.spawn(Panic::Never), b_val_right.spawn(Panic::Never)); + right.insert(c.spawn(Panic::Never), c_val_right.spawn(Panic::Never)); + + // First key that conflicts should + catch_unwind(move || { + left.merge(right, |_, _, _| panic!("Panic in conflict function")); + assert_eq!(left.len(), 1); // only 1 entry should be left + }) + .unwrap_err(); + assert_eq!(a.dropped(), 1); // should not panic + assert_eq!(a_val_left.dropped(), 1); // should not panic + assert_eq!(b.dropped(), 2); // should drop from panic (conflict) + assert_eq!(b_val_left.dropped(), 1); // should be 2 were it not for Rust issue #47949 + assert_eq!(b_val_right.dropped(), 1); // should be 2 were it not for Rust issue #47949 + assert_eq!(c.dropped(), 2); // should drop from panic (conflict) + assert_eq!(c_val_left.dropped(), 1); // should be 2 were it not for Rust issue #47949 + assert_eq!(c_val_right.dropped(), 1); // should be 2 were it not for Rust issue #47949 +} + +#[test] +fn test_merge_ord_chaos() { + let mut map1 = BTreeMap::new(); + map1.insert(Cyclic3::A, ()); + map1.insert(Cyclic3::B, ()); + let mut map2 = BTreeMap::new(); + map2.insert(Cyclic3::A, ()); + map2.insert(Cyclic3::B, ()); + map2.insert(Cyclic3::C, ()); // lands first, before A + map2.insert(Cyclic3::B, ()); // lands first, before C + map1.check(); + map2.check(); // keys are not unique but still strictly ascending + assert_eq!(map1.len(), 2); + assert_eq!(map2.len(), 4); + map1.merge(map2, |_, _, _| ()); + assert_eq!(map1.len(), 5); + map1.check(); +} + fn rand_data(len: usize) -> Vec<(u32, u32)> { let mut rng = DeterministicRng::new(); Vec::from_iter((0..len).map(|_| (rng.next(), rng.next()))) @@ -2615,3 +2773,25 @@ fn test_id_based_append() { assert_eq!(lhs.pop_first().unwrap().0.name, "lhs_k".to_string()); } + +#[test] +fn test_id_based_merge() { + let mut lhs = BTreeMap::new(); + let mut rhs = BTreeMap::new(); + + lhs.insert(IdBased { id: 0, name: "lhs_k".to_string() }, "1".to_string()); + rhs.insert(IdBased { id: 0, name: "rhs_k".to_string() }, "2".to_string()); + + lhs.merge(rhs, |_, mut lhs_val, rhs_val| { + // confirming that lhs_val comes from lhs tree, + // rhs_val comes from rhs tree + assert_eq!(lhs_val, String::from("1")); + assert_eq!(rhs_val, String::from("2")); + lhs_val.push_str(&rhs_val); + lhs_val + }); + + let merged_kv_pair = lhs.pop_first().unwrap(); + assert_eq!(merged_kv_pair.0.id, 0); + assert_eq!(merged_kv_pair.0.name, "lhs_k".to_string()); +} diff --git a/library/alloc/src/collections/btree/node.rs b/library/alloc/src/collections/btree/node.rs index 84dd4b7e49def..0c7afcc63b9b7 100644 --- a/library/alloc/src/collections/btree/node.rs +++ b/library/alloc/src/collections/btree/node.rs @@ -1430,7 +1430,7 @@ impl<'a, K: 'a, V: 'a> BalancingContext<'a, K, V> { left_node.val_area_mut(old_left_len + 1..new_left_len), ); - slice_remove(&mut parent_node.edge_area_mut(..old_parent_len + 1), parent_idx + 1); + slice_remove(parent_node.edge_area_mut(..old_parent_len + 1), parent_idx + 1); parent_node.correct_childrens_parent_links(parent_idx + 1..old_parent_len); *parent_node.len_mut() -= 1; diff --git a/library/alloc/src/collections/btree/set.rs b/library/alloc/src/collections/btree/set.rs index fd27e87b1f470..d06daa7c6c1b7 100644 --- a/library/alloc/src/collections/btree/set.rs +++ b/library/alloc/src/collections/btree/set.rs @@ -355,12 +355,14 @@ impl BTreeSet { /// # #![allow(unused_mut)] /// # #![feature(allocator_api)] /// # #![feature(btreemap_alloc)] + /// /// use std::collections::BTreeSet; /// use std::alloc::Global; /// - /// let mut set: BTreeSet = BTreeSet::new_in(Global); + /// let set: BTreeSet = BTreeSet::new_in(Global); /// ``` #[unstable(feature = "btreemap_alloc", issue = "32838")] + #[must_use] pub const fn new_in(alloc: A) -> BTreeSet { BTreeSet { map: BTreeMap::new_in(alloc) } } @@ -1546,7 +1548,9 @@ impl<'a, T, A: Allocator + Clone> IntoIterator for &'a BTreeSet { } } -/// An iterator produced by calling `extract_if` on BTreeSet. +/// This `struct` is created by the [`extract_if`] method on [`BTreeSet`]. +/// +/// [`extract_if`]: BTreeSet::extract_if #[stable(feature = "btree_extract_if", since = "1.91.0")] #[must_use = "iterators are lazy and do nothing unless consumed; \ use `retain` or `extract_if().for_each(drop)` to remove and discard elements"] @@ -1967,7 +1971,7 @@ impl<'a, T: Ord, A: Allocator + Clone> Iterator for Difference<'a, T, A> { } DifferenceInner::Search { self_iter, other_set } => loop { let self_next = self_iter.next()?; - if !other_set.contains(&self_next) { + if !other_set.contains(self_next) { return Some(self_next); } }, @@ -2064,7 +2068,7 @@ impl<'a, T: Ord, A: Allocator + Clone> Iterator for Intersection<'a, T, A> { } IntersectionInner::Search { small_iter, large_set } => loop { let small_next = small_iter.next()?; - if large_set.contains(&small_next) { + if large_set.contains(small_next) { return Some(small_next); } }, diff --git a/library/alloc/src/collections/linked_list.rs b/library/alloc/src/collections/linked_list.rs index 3889fca30bc87..788609f740d07 100644 --- a/library/alloc/src/collections/linked_list.rs +++ b/library/alloc/src/collections/linked_list.rs @@ -12,6 +12,7 @@ #![stable(feature = "rust1", since = "1.0.0")] +use core::alloc::AllocatorClone; use core::cmp::Ordering; use core::hash::{Hash, Hasher}; use core::iter::FusedIterator; @@ -340,7 +341,7 @@ impl LinkedList { at: usize, ) -> Self where - A: Clone, + A: AllocatorClone, { // The split node is the new head node of the second part if let Some(mut split_node) = split_node { @@ -383,7 +384,7 @@ impl LinkedList { at: usize, ) -> Self where - A: Clone, + A: AllocatorClone, { // The split node is the new tail node of the first part and owns // the head of the second part. @@ -509,7 +510,7 @@ impl LinkedList { /// use std::alloc::System; /// use std::collections::LinkedList; /// - /// let list: LinkedList = LinkedList::new_in(System); + /// let list: LinkedList = LinkedList::new_in(System); /// ``` #[inline] #[unstable(feature = "allocator_api", issue = "32838")] @@ -862,7 +863,7 @@ impl LinkedList { /// *ptr += 4; /// assert_eq!(dl.front().unwrap(), &6); /// ``` - #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "push_mut", since = "1.95.0")] #[must_use = "if you don't need a reference to the value, use `LinkedList::push_front` instead"] pub fn push_front_mut(&mut self, elt: T) -> &mut T { let mut node = @@ -933,7 +934,7 @@ impl LinkedList { /// *ptr += 4; /// assert_eq!(dl.back().unwrap(), &6); /// ``` - #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "push_mut", since = "1.95.0")] #[must_use = "if you don't need a reference to the value, use `LinkedList::push_back` instead"] pub fn push_back_mut(&mut self, elt: T) -> &mut T { let mut node = @@ -994,7 +995,7 @@ impl LinkedList { #[stable(feature = "rust1", since = "1.0.0")] pub fn split_off(&mut self, at: usize) -> LinkedList where - A: Clone, + A: AllocatorClone, { let len = self.len(); assert!(at <= len, "Cannot split off at a nonexistent index"); @@ -1748,7 +1749,7 @@ impl<'a, T, A: Allocator> CursorMut<'a, T, A> { #[unstable(feature = "linked_list_cursors", issue = "58533")] pub fn remove_current_as_list(&mut self) -> Option> where - A: Clone, + A: AllocatorClone, { let mut unlinked_node = self.current?; unsafe { @@ -1776,7 +1777,7 @@ impl<'a, T, A: Allocator> CursorMut<'a, T, A> { #[unstable(feature = "linked_list_cursors", issue = "58533")] pub fn split_after(&mut self) -> LinkedList where - A: Clone, + A: AllocatorClone, { let split_off_idx = if self.index == self.list.len { 0 } else { self.index + 1 }; if self.index == self.list.len { @@ -1795,7 +1796,7 @@ impl<'a, T, A: Allocator> CursorMut<'a, T, A> { #[unstable(feature = "linked_list_cursors", issue = "58533")] pub fn split_before(&mut self) -> LinkedList where - A: Clone, + A: AllocatorClone, { let split_off_idx = self.index; self.index = 0; @@ -1942,7 +1943,9 @@ impl<'a, T, A: Allocator> CursorMut<'a, T, A> { } } -/// An iterator produced by calling `extract_if` on LinkedList. +/// This `struct` is created by the [`extract_if`] method on [`LinkedList`]. +/// +/// [`extract_if`]: LinkedList::extract_if #[stable(feature = "extract_if", since = "1.87.0")] #[must_use = "iterators are lazy and do nothing unless consumed; \ use `extract_if().for_each(drop)` to remove and discard elements"] @@ -2165,12 +2168,15 @@ impl Clone for LinkedList { /// resources of `self`'s elements as well. fn clone_from(&mut self, source: &Self) { let mut source_iter = source.iter(); - if self.len() > source.len() { - self.split_off(source.len()); - } - for (elem, source_elem) in self.iter_mut().zip(&mut source_iter) { + for elem in self.iter_mut() { + let Some(source_elem) = source_iter.next() else { + break; + }; elem.clone_from(source_elem); } + while self.len() > source.len() { + self.pop_back(); + } if !source_iter.is_empty() { self.extend(source_iter.cloned()); } diff --git a/library/alloc/src/collections/mod.rs b/library/alloc/src/collections/mod.rs index d306d2016ea28..2cc6b8e894664 100644 --- a/library/alloc/src/collections/mod.rs +++ b/library/alloc/src/collections/mod.rs @@ -19,6 +19,7 @@ pub mod vec_deque; pub mod btree_map { //! An ordered map based on a B-Tree. #[stable(feature = "rust1", since = "1.0.0")] + #[cfg(not(test))] pub use super::btree::map::*; } @@ -128,7 +129,7 @@ pub enum TryReserveErrorKind { )] #[rustc_const_unstable(feature = "const_heap", issue = "79597")] #[cfg(not(test))] -impl const Clone for TryReserveErrorKind { +const impl Clone for TryReserveErrorKind { fn clone(&self) -> Self { match self { TryReserveErrorKind::CapacityOverflow => TryReserveErrorKind::CapacityOverflow, @@ -149,7 +150,7 @@ pub use realalloc::collections::TryReserveErrorKind; )] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] #[cfg(not(test))] -impl const From for TryReserveError { +const impl From for TryReserveError { #[inline] fn from(kind: TryReserveErrorKind) -> Self { Self { kind } @@ -159,7 +160,7 @@ impl const From for TryReserveError { #[unstable(feature = "try_reserve_kind", issue = "48043")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] #[cfg(not(test))] -impl const From for TryReserveErrorKind { +const impl From for TryReserveErrorKind { /// Always evaluates to [`TryReserveErrorKind::CapacityOverflow`]. #[inline] fn from(_: LayoutError) -> Self { diff --git a/library/alloc/src/collections/vec_deque/drain.rs b/library/alloc/src/collections/vec_deque/drain.rs index a43853604a2d2..da4b803c64d56 100644 --- a/library/alloc/src/collections/vec_deque/drain.rs +++ b/library/alloc/src/collections/vec_deque/drain.rs @@ -5,6 +5,7 @@ use core::ptr::NonNull; use core::{fmt, ptr}; use super::VecDeque; +use super::index::WrappedIndex; use crate::alloc::{Allocator, Global}; /// A draining iterator over the elements of a `VecDeque`. @@ -203,11 +204,11 @@ impl Drop for Drain<'_, T, A> { let (src, dst, len); if head_len < tail_len { src = source_deque.head; - dst = source_deque.to_physical_idx(drain_len); + dst = source_deque.to_wrapped_index(drain_len); len = head_len; } else { - src = source_deque.to_physical_idx(head_len + drain_len); - dst = source_deque.to_physical_idx(head_len); + src = source_deque.to_wrapped_index(head_len + drain_len); + dst = source_deque.to_wrapped_index(head_len); len = tail_len; }; @@ -220,10 +221,10 @@ impl Drop for Drain<'_, T, A> { if new_len == 0 { // Special case: If the entire deque was drained, reset the head back to 0, // like `.clear()` does. - source_deque.head = 0; + source_deque.head = WrappedIndex::zero(); } else if head_len < tail_len { // If we moved the head above, then we need to adjust the head index here. - source_deque.head = source_deque.to_physical_idx(drain_len); + source_deque.head = source_deque.to_wrapped_index(drain_len); } source_deque.len = new_len; } @@ -240,7 +241,7 @@ impl Iterator for Drain<'_, T, A> { if self.remaining == 0 { return None; } - let wrapped_idx = unsafe { self.deque.as_ref().to_physical_idx(self.idx) }; + let wrapped_idx = unsafe { self.deque.as_ref().to_wrapped_index(self.idx) }; self.idx += 1; self.remaining -= 1; Some(unsafe { self.deque.as_mut().buffer_read(wrapped_idx) }) @@ -261,7 +262,8 @@ impl DoubleEndedIterator for Drain<'_, T, A> { return None; } self.remaining -= 1; - let wrapped_idx = unsafe { self.deque.as_ref().to_physical_idx(self.idx + self.remaining) }; + let wrapped_idx = + unsafe { self.deque.as_ref().to_wrapped_index(self.idx + self.remaining) }; Some(unsafe { self.deque.as_mut().buffer_read(wrapped_idx) }) } } diff --git a/library/alloc/src/collections/vec_deque/extract_if.rs b/library/alloc/src/collections/vec_deque/extract_if.rs index 437f0d6dd5eb3..19439dfb4f05d 100644 --- a/library/alloc/src/collections/vec_deque/extract_if.rs +++ b/library/alloc/src/collections/vec_deque/extract_if.rs @@ -83,8 +83,8 @@ where // // Note: we can't use `vec.get_mut(i).unwrap()` here since the precondition for that // function is that i < vec.len, but we've set vec's length to zero. - let idx = self.vec.to_physical_idx(i); - let cur = unsafe { &mut *self.vec.ptr().add(idx) }; + let idx = self.vec.to_wrapped_index(i); + let cur = unsafe { &mut *self.vec.ptr().add(idx.as_index()) }; let drained = (self.pred)(cur); // Update the index *after* the predicate is called. If the index // is updated prior and the predicate panics, the element at this @@ -95,7 +95,7 @@ where // SAFETY: We never touch this element again after returning it. return Some(unsafe { ptr::read(cur) }); } else if self.del > 0 { - let hole_slot = self.vec.to_physical_idx(i - self.del); + let hole_slot = self.vec.to_wrapped_index(i - self.del); // SAFETY: `self.del` > 0, so the hole slot must not overlap with current element. // We use copy for move, and never touch this element again. unsafe { self.vec.wrap_copy(idx, hole_slot, 1) }; @@ -113,8 +113,8 @@ where impl Drop for ExtractIf<'_, T, F, A> { fn drop(&mut self) { if self.del > 0 { - let src = self.vec.to_physical_idx(self.idx); - let dst = self.vec.to_physical_idx(self.idx - self.del); + let src = self.vec.to_wrapped_index(self.idx); + let dst = self.vec.to_wrapped_index(self.idx - self.del); let len = self.old_len - self.idx; // SAFETY: Trailing unchecked items must be valid since we never touch them. unsafe { self.vec.wrap_copy(src, dst, len) }; @@ -131,7 +131,7 @@ where { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { let peek = if self.idx < self.end { - let idx = self.vec.to_physical_idx(self.idx); + let idx = self.vec.to_wrapped_index(self.idx); // This has to use pointer arithmetic as `self.vec[self.idx]` or // `self.vec.get_unchecked(self.idx)` wouldn't work since we // temporarily set the length of `self.vec` to zero. @@ -141,7 +141,7 @@ where // smaller than `self.old_len`, `idx` is valid for indexing the // buffer. Also, per the invariant of `self.idx`, this element // has not been inspected/moved out yet. - Some(unsafe { &*self.vec.ptr().add(idx) }) + Some(unsafe { &*self.vec.ptr().add(idx.as_index()) }) } else { None }; diff --git a/library/alloc/src/collections/vec_deque/into_iter.rs b/library/alloc/src/collections/vec_deque/into_iter.rs index 2b09a5e7ddc58..e18b85dd4b694 100644 --- a/library/alloc/src/collections/vec_deque/into_iter.rs +++ b/library/alloc/src/collections/vec_deque/into_iter.rs @@ -5,6 +5,7 @@ use core::ops::Try; use core::{array, fmt, ptr}; use super::VecDeque; +use super::index::WrappedIndex; use crate::alloc::{Allocator, Global}; /// An owning iterator over the elements of a `VecDeque`. @@ -86,7 +87,7 @@ impl Iterator for IntoIter { impl<'a, T, A: Allocator> Drop for Guard<'a, T, A> { fn drop(&mut self) { self.deque.len -= self.consumed; - self.deque.head = self.deque.to_physical_idx(self.consumed); + self.deque.head = self.deque.to_wrapped_index(self.consumed); } } @@ -140,7 +141,7 @@ impl Iterator for IntoIter { // SAFETY: By manually adjusting the head and length of the deque, we effectively // make it forget the first `N` elements, so taking ownership of them is safe. unsafe { ptr::copy_nonoverlapping(head.as_ptr(), raw_arr_ptr, N) }; - self.inner.head = self.inner.to_physical_idx(N); + self.inner.head = self.inner.to_wrapped_index(N); self.inner.len -= N; // SAFETY: We initialized the entire array with items from `head` return Ok(unsafe { raw_arr.transpose().assume_init() }); @@ -155,7 +156,7 @@ impl Iterator for IntoIter { unsafe { ptr::copy_nonoverlapping(tail.as_ptr(), raw_arr_ptr.add(head.len()), remaining) }; - self.inner.head = self.inner.to_physical_idx(N); + self.inner.head = self.inner.to_wrapped_index(N); self.inner.len -= N; // SAFETY: We initialized the entire array with items from `head` and `tail` Ok(unsafe { raw_arr.transpose().assume_init() }) @@ -166,7 +167,7 @@ impl Iterator for IntoIter { }; let init = head.len() + tail.len(); // We completely drained all the deques elements. - self.inner.head = 0; + self.inner.head = WrappedIndex::zero(); self.inner.len = 0; // SAFETY: We copied all elements from both slices to the beginning of the array, so // the given range is initialized. diff --git a/library/alloc/src/collections/vec_deque/mod.rs b/library/alloc/src/collections/vec_deque/mod.rs index 7b58915087294..593a1a526f3b7 100644 --- a/library/alloc/src/collections/vec_deque/mod.rs +++ b/library/alloc/src/collections/vec_deque/mod.rs @@ -110,7 +110,7 @@ pub struct VecDeque< > { // `self[0]`, if it exists, is `buf[head]`. // `head < buf.capacity()`, unless `buf.capacity() == 0` when `head == 0`. - head: usize, + head: WrappedIndex, // the number of initialized elements, starting from the one at `head` and potentially wrapping around. // if `len == 0`, the exact value of `head` is unimportant. // if `T` is zero-Sized, then `self.len <= usize::MAX`, otherwise `self.len <= isize::MAX as usize`. @@ -136,21 +136,21 @@ impl Clone for VecDeque { } } -#[stable(feature = "rust1", since = "1.0.0")] -unsafe impl<#[may_dangle] T, A: Allocator> Drop for VecDeque { - fn drop(&mut self) { - /// Runs the destructor for all items in the slice when it gets dropped (normally or - /// during unwinding). - struct Dropper<'a, T>(&'a mut [T]); +/// Runs the destructor for all items in the slice when it gets dropped (normally or +/// during unwinding). +struct Dropper<'a, T>(&'a mut [T]); - impl<'a, T> Drop for Dropper<'a, T> { - fn drop(&mut self) { - unsafe { - ptr::drop_in_place(self.0); - } - } +impl Drop for Dropper<'_, T> { + fn drop(&mut self) { + unsafe { + ptr::drop_in_place(self.0); } + } +} +#[stable(feature = "rust1", since = "1.0.0")] +unsafe impl<#[may_dangle] T, A: Allocator> Drop for VecDeque { + fn drop(&mut self) { let (front, back) = self.as_mut_slices(); unsafe { let _back_dropper = Dropper(back); @@ -186,7 +186,7 @@ impl VecDeque { unsafe fn push_unchecked(&mut self, element: T) { // SAFETY: Because of the precondition, it's guaranteed that there is space // in the logical array after the last element. - unsafe { self.buffer_write(self.to_physical_idx(self.len), element) }; + unsafe { self.buffer_write(self.to_wrapped_index(self.len), element) }; // This can't overflow because `deque.len() < deque.capacity() <= usize::MAX`. self.len += 1; } @@ -208,8 +208,8 @@ impl VecDeque { /// Moves an element out of the buffer #[inline] - unsafe fn buffer_read(&mut self, off: usize) -> T { - unsafe { ptr::read(self.ptr().add(off)) } + unsafe fn buffer_read(&mut self, off: WrappedIndex) -> T { + unsafe { ptr::read(self.ptr().add(off.as_index())) } } /// Writes an element into the buffer, moving it and returning a pointer to it. @@ -217,9 +217,9 @@ impl VecDeque { /// /// May only be called if `off < self.capacity()`. #[inline] - unsafe fn buffer_write(&mut self, off: usize, value: T) -> &mut T { + unsafe fn buffer_write(&mut self, off: WrappedIndex, value: T) -> &mut T { unsafe { - let ptr = self.ptr().add(off); + let ptr = self.ptr().add(off.as_index()); ptr::write(ptr, value); &mut *ptr } @@ -229,9 +229,7 @@ impl VecDeque { /// `range` must lie inside `0..self.capacity()`. #[inline] unsafe fn buffer_range(&self, range: Range) -> *mut [T] { - unsafe { - ptr::slice_from_raw_parts_mut(self.ptr().add(range.start), range.end - range.start) - } + unsafe { self.ptr().add(range.start).cast_slice(range.end - range.start) } } /// Returns `true` if the buffer is at full capacity. @@ -243,20 +241,23 @@ impl VecDeque { /// Returns the index in the underlying buffer for a given logical element /// index + addend. #[inline] - fn wrap_add(&self, idx: usize, addend: usize) -> usize { - wrap_index(idx.wrapping_add(addend), self.capacity()) + fn wrap_add(&self, idx: WrappedIndex, addend: usize) -> WrappedIndex { + wrap_index(idx.as_index().wrapping_add(addend), self.capacity()) } #[inline] - fn to_physical_idx(&self, idx: usize) -> usize { + fn to_wrapped_index(&self, idx: usize) -> WrappedIndex { self.wrap_add(self.head, idx) } /// Returns the index in the underlying buffer for a given logical element /// index - subtrahend. #[inline] - fn wrap_sub(&self, idx: usize, subtrahend: usize) -> usize { - wrap_index(idx.wrapping_sub(subtrahend).wrapping_add(self.capacity()), self.capacity()) + fn wrap_sub(&self, idx: WrappedIndex, subtrahend: usize) -> WrappedIndex { + wrap_index( + idx.as_index().wrapping_sub(subtrahend).wrapping_add(self.capacity()), + self.capacity(), + ) } /// Get source, destination and count (like the arguments to [`ptr::copy_nonoverlapping`]) @@ -269,14 +270,14 @@ impl VecDeque { /// /// - Ranges must not overlap: `src.abs_diff(dst) >= count`. /// - Ranges must be in bounds of the logical buffer: `src + count <= self.capacity()` and `dst + count <= self.capacity()`. - /// - `head` must be in bounds: `head < self.capacity()`. + /// - `head` must be in bounds: `head < self.capacity()`, unless `self.capacity() == 0`, in which case `head == 0`. #[cfg(not(no_global_oom_handling))] unsafe fn nonoverlapping_ranges( &mut self, src: usize, dst: usize, count: usize, - head: usize, + head: WrappedIndex, ) -> [(*const T, *mut T, usize); 2] { // "`src` and `dst` must be at least as far apart as `count`" debug_assert!( @@ -292,8 +293,8 @@ impl VecDeque { let wrapped_src = self.wrap_add(head, src); let wrapped_dst = self.wrap_add(head, dst); - let room_after_src = self.capacity() - wrapped_src; - let room_after_dst = self.capacity() - wrapped_dst; + let room_after_src = self.capacity() - wrapped_src.as_index(); + let room_after_dst = self.capacity() - wrapped_dst.as_index(); let src_wraps = room_after_src < count; let dst_wraps = room_after_dst < count; @@ -308,8 +309,8 @@ impl VecDeque { unsafe { let ptr = self.ptr(); - let src_ptr = ptr.add(wrapped_src); - let dst_ptr = ptr.add(wrapped_dst); + let src_ptr = ptr.add(wrapped_src.as_index()); + let dst_ptr = ptr.add(wrapped_dst.as_index()); if src_wraps { [ @@ -333,7 +334,7 @@ impl VecDeque { /// Copies a contiguous block of memory len long from src to dst #[inline] - unsafe fn copy(&mut self, src: usize, dst: usize, len: usize) { + unsafe fn copy(&mut self, src: WrappedIndex, dst: WrappedIndex, len: usize) { debug_assert!( dst + len <= self.capacity(), "cpy dst={} src={} len={} cap={}", @@ -351,13 +352,13 @@ impl VecDeque { self.capacity() ); unsafe { - ptr::copy(self.ptr().add(src), self.ptr().add(dst), len); + ptr::copy(self.ptr().add(src.as_index()), self.ptr().add(dst.as_index()), len); } } /// Copies a contiguous block of memory len long from src to dst #[inline] - unsafe fn copy_nonoverlapping(&mut self, src: usize, dst: usize, len: usize) { + unsafe fn copy_nonoverlapping(&mut self, src: WrappedIndex, dst: WrappedIndex, len: usize) { debug_assert!( dst + len <= self.capacity(), "cno dst={} src={} len={} cap={}", @@ -375,14 +376,18 @@ impl VecDeque { self.capacity() ); unsafe { - ptr::copy_nonoverlapping(self.ptr().add(src), self.ptr().add(dst), len); + ptr::copy_nonoverlapping( + self.ptr().add(src.as_index()), + self.ptr().add(dst.as_index()), + len, + ); } } /// Copies a potentially wrapping block of memory len long from src to dest. /// (abs(dst - src) + len) must be no larger than capacity() (There must be at /// most one continuous overlapping region between src and dest). - unsafe fn wrap_copy(&mut self, src: usize, dst: usize, len: usize) { + unsafe fn wrap_copy(&mut self, src: WrappedIndex, dst: WrappedIndex, len: usize) { debug_assert!( cmp::min(src.abs_diff(dst), self.capacity() - src.abs_diff(dst)) + len <= self.capacity(), @@ -398,10 +403,10 @@ impl VecDeque { return; } - let dst_after_src = self.wrap_sub(dst, src) < len; + let dst_after_src = self.wrap_sub(dst, src.as_index()) < len; - let src_pre_wrap_len = self.capacity() - src; - let dst_pre_wrap_len = self.capacity() - dst; + let src_pre_wrap_len = self.capacity() - src.as_index(); + let dst_pre_wrap_len = self.capacity() - dst.as_index(); let src_wraps = src_pre_wrap_len < len; let dst_wraps = dst_pre_wrap_len < len; @@ -429,7 +434,11 @@ impl VecDeque { // unsafe { self.copy(src, dst, dst_pre_wrap_len); - self.copy(src + dst_pre_wrap_len, 0, len - dst_pre_wrap_len); + self.copy( + src.add(dst_pre_wrap_len), + WrappedIndex::zero(), + len - dst_pre_wrap_len, + ); } } (true, false, true) => { @@ -442,7 +451,11 @@ impl VecDeque { // . . D . // unsafe { - self.copy(src + dst_pre_wrap_len, 0, len - dst_pre_wrap_len); + self.copy( + src.add(dst_pre_wrap_len), + WrappedIndex::zero(), + len - dst_pre_wrap_len, + ); self.copy(src, dst, dst_pre_wrap_len); } } @@ -457,7 +470,11 @@ impl VecDeque { // unsafe { self.copy(src, dst, src_pre_wrap_len); - self.copy(0, dst + src_pre_wrap_len, len - src_pre_wrap_len); + self.copy( + WrappedIndex::zero(), + dst.add(src_pre_wrap_len), + len - src_pre_wrap_len, + ); } } (true, true, false) => { @@ -470,7 +487,11 @@ impl VecDeque { // D . . . // unsafe { - self.copy(0, dst + src_pre_wrap_len, len - src_pre_wrap_len); + self.copy( + WrappedIndex::zero(), + dst.add(src_pre_wrap_len), + len - src_pre_wrap_len, + ); self.copy(src, dst, src_pre_wrap_len); } } @@ -488,8 +509,12 @@ impl VecDeque { let delta = dst_pre_wrap_len - src_pre_wrap_len; unsafe { self.copy(src, dst, src_pre_wrap_len); - self.copy(0, dst + src_pre_wrap_len, delta); - self.copy(delta, 0, len - dst_pre_wrap_len); + self.copy(WrappedIndex::zero(), dst.add(src_pre_wrap_len), delta); + self.copy( + WrappedIndex::from_arbitrary_number(delta), + WrappedIndex::zero(), + len - dst_pre_wrap_len, + ); } } (true, true, true) => { @@ -505,8 +530,16 @@ impl VecDeque { debug_assert!(src_pre_wrap_len > dst_pre_wrap_len); let delta = src_pre_wrap_len - dst_pre_wrap_len; unsafe { - self.copy(0, delta, len - src_pre_wrap_len); - self.copy(self.capacity() - delta, 0, delta); + self.copy( + WrappedIndex::zero(), + WrappedIndex::from_arbitrary_number(delta), + len - src_pre_wrap_len, + ); + self.copy( + WrappedIndex::from_arbitrary_number(self.capacity() - delta), + WrappedIndex::zero(), + delta, + ); self.copy(src, dst, dst_pre_wrap_len); } } @@ -516,17 +549,17 @@ impl VecDeque { /// Copies all values from `src` to `dst`, wrapping around if needed. /// Assumes capacity is sufficient. #[inline] - unsafe fn copy_slice(&mut self, dst: usize, src: &[T]) { + unsafe fn copy_slice(&mut self, dst: WrappedIndex, src: &[T]) { debug_assert!(src.len() <= self.capacity()); - let head_room = self.capacity() - dst; + let head_room = self.capacity() - dst.as_index(); if src.len() <= head_room { unsafe { - ptr::copy_nonoverlapping(src.as_ptr(), self.ptr().add(dst), src.len()); + ptr::copy_nonoverlapping(src.as_ptr(), self.ptr().add(dst.as_index()), src.len()); } } else { let (left, right) = src.split_at(head_room); unsafe { - ptr::copy_nonoverlapping(left.as_ptr(), self.ptr().add(dst), left.len()); + ptr::copy_nonoverlapping(left.as_ptr(), self.ptr().add(dst.as_index()), left.len()); ptr::copy_nonoverlapping(right.as_ptr(), self.ptr(), right.len()); } } @@ -536,7 +569,7 @@ impl VecDeque { /// Assumes capacity is sufficient. /// Equivalent to calling [`VecDeque::copy_slice`] with a [reversed](https://doc.rust-lang.org/std/primitive.slice.html#method.reverse) slice. #[inline] - unsafe fn copy_slice_reversed(&mut self, dst: usize, src: &[T]) { + unsafe fn copy_slice_reversed(&mut self, dst: WrappedIndex, src: &[T]) { /// # Safety /// /// See [`ptr::copy_nonoverlapping`]. @@ -547,15 +580,23 @@ impl VecDeque { } debug_assert!(src.len() <= self.capacity()); - let head_room = self.capacity() - dst; + let head_room = self.capacity() - dst.as_index(); if src.len() <= head_room { unsafe { - copy_nonoverlapping_reversed(src.as_ptr(), self.ptr().add(dst), src.len()); + copy_nonoverlapping_reversed( + src.as_ptr(), + self.ptr().add(dst.as_index()), + src.len(), + ); } } else { let (left, right) = src.split_at(src.len() - head_room); unsafe { - copy_nonoverlapping_reversed(right.as_ptr(), self.ptr().add(dst), right.len()); + copy_nonoverlapping_reversed( + right.as_ptr(), + self.ptr().add(dst.as_index()), + right.len(), + ); copy_nonoverlapping_reversed(left.as_ptr(), self.ptr(), left.len()); } } @@ -570,12 +611,12 @@ impl VecDeque { #[inline] unsafe fn write_iter( &mut self, - dst: usize, + dst: WrappedIndex, iter: impl Iterator, written: &mut usize, ) { iter.enumerate().for_each(|(i, element)| unsafe { - self.buffer_write(dst + i, element); + self.buffer_write(dst.add(i), element); *written += 1; }); } @@ -590,7 +631,7 @@ impl VecDeque { /// Assumes capacity is sufficient. unsafe fn write_iter_wrapping( &mut self, - dst: usize, + dst: WrappedIndex, mut iter: impl Iterator, len: usize, ) -> usize { @@ -605,7 +646,7 @@ impl VecDeque { } } - let head_room = self.capacity() - dst; + let head_room = self.capacity() - dst.as_index(); let mut guard = Guard { deque: self, written: 0 }; @@ -618,7 +659,7 @@ impl VecDeque { ByRefSized(&mut iter).take(head_room), &mut guard.written, ); - guard.deque.write_iter(0, iter, &mut guard.written) + guard.deque.write_iter(WrappedIndex::zero(), iter, &mut guard.written) }; } @@ -655,16 +696,20 @@ impl VecDeque { // A // Nop } else { - let head_len = old_capacity - self.head; + let head_len = old_capacity - self.head.as_index(); let tail_len = self.len - head_len; if head_len > tail_len && new_capacity - old_capacity >= tail_len { // B unsafe { - self.copy_nonoverlapping(0, old_capacity, tail_len); + self.copy_nonoverlapping( + WrappedIndex::zero(), + WrappedIndex::from_arbitrary_number(old_capacity), + tail_len, + ); } } else { // C - let new_head = new_capacity - head_len; + let new_head = WrappedIndex::from_arbitrary_number(new_capacity - head_len); unsafe { // can't use copy_nonoverlapping here, because if e.g. head_len = 2 // and new_capacity = old_capacity + 1, then the heads overlap. @@ -783,7 +828,7 @@ impl VecDeque { #[must_use] pub const fn new() -> VecDeque { // FIXME(const-hack): This should just be `VecDeque::new_in(Global)` once that hits stable. - VecDeque { head: 0, len: 0, buf: RawVec::new() } + VecDeque { head: WrappedIndex::zero(), len: 0, buf: RawVec::new() } } /// Creates an empty deque with space for at least `capacity` elements. @@ -793,7 +838,7 @@ impl VecDeque { /// ``` /// use std::collections::VecDeque; /// - /// let deque: VecDeque = VecDeque::with_capacity(10); + /// let deque: VecDeque = VecDeque::with_capacity(10); /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] @@ -823,7 +868,11 @@ impl VecDeque { #[inline] #[unstable(feature = "try_with_capacity", issue = "91913")] pub fn try_with_capacity(capacity: usize) -> Result, TryReserveError> { - Ok(VecDeque { head: 0, len: 0, buf: RawVec::try_with_capacity_in(capacity, Global)? }) + Ok(VecDeque { + head: WrappedIndex::zero(), + len: 0, + buf: RawVec::try_with_capacity_in(capacity, Global)?, + }) } } @@ -833,14 +882,17 @@ impl VecDeque { /// # Examples /// /// ``` + /// # #![feature(allocator_api)] + /// /// use std::collections::VecDeque; + /// use std::alloc::Global; /// - /// let deque: VecDeque = VecDeque::new(); + /// let deque: VecDeque = VecDeque::new_in(Global); /// ``` #[inline] #[unstable(feature = "allocator_api", issue = "32838")] pub const fn new_in(alloc: A) -> VecDeque { - VecDeque { head: 0, len: 0, buf: RawVec::new_in(alloc) } + VecDeque { head: WrappedIndex::zero(), len: 0, buf: RawVec::new_in(alloc) } } /// Creates an empty deque with space for at least `capacity` elements. @@ -848,13 +900,20 @@ impl VecDeque { /// # Examples /// /// ``` + /// # #![feature(allocator_api)] + /// /// use std::collections::VecDeque; + /// use std::alloc::Global; /// - /// let deque: VecDeque = VecDeque::with_capacity(10); + /// let deque: VecDeque = VecDeque::with_capacity_in(10, Global); /// ``` #[unstable(feature = "allocator_api", issue = "32838")] pub fn with_capacity_in(capacity: usize, alloc: A) -> VecDeque { - VecDeque { head: 0, len: 0, buf: RawVec::with_capacity_in(capacity, alloc) } + VecDeque { + head: WrappedIndex::zero(), + len: 0, + buf: RawVec::with_capacity_in(capacity, alloc), + } } /// Creates a `VecDeque` from a raw allocation, when the initialized @@ -883,7 +942,7 @@ impl VecDeque { // and that the allocation is valid for use in `RawVec`. unsafe { VecDeque { - head: initialized.start, + head: WrappedIndex::from_arbitrary_number(initialized.start), len: initialized.end.unchecked_sub(initialized.start), buf: RawVec::from_raw_parts_in(ptr, capacity, alloc), } @@ -909,8 +968,8 @@ impl VecDeque { #[stable(feature = "rust1", since = "1.0.0")] pub fn get(&self, index: usize) -> Option<&T> { if index < self.len { - let idx = self.to_physical_idx(index); - unsafe { Some(&*self.ptr().add(idx)) } + let idx = self.to_wrapped_index(index); + unsafe { Some(&*self.ptr().add(idx.as_index())) } } else { None } @@ -939,8 +998,8 @@ impl VecDeque { #[stable(feature = "rust1", since = "1.0.0")] pub fn get_mut(&mut self, index: usize) -> Option<&mut T> { if index < self.len { - let idx = self.to_physical_idx(index); - unsafe { Some(&mut *self.ptr().add(idx)) } + let idx = self.to_wrapped_index(index); + unsafe { Some(&mut *self.ptr().add(idx.as_index())) } } else { None } @@ -973,9 +1032,9 @@ impl VecDeque { pub fn swap(&mut self, i: usize, j: usize) { assert!(i < self.len()); assert!(j < self.len()); - let ri = self.to_physical_idx(i); - let rj = self.to_physical_idx(j); - unsafe { ptr::swap(self.ptr().add(ri), self.ptr().add(rj)) } + let ri = self.to_wrapped_index(i); + let rj = self.to_wrapped_index(j); + unsafe { ptr::swap(self.ptr().add(ri.as_index()), self.ptr().add(rj.as_index())) } } /// Returns the number of elements the deque can hold without @@ -1097,7 +1156,7 @@ impl VecDeque { /// /// Ok(output) /// } - /// # process_data(&[1, 2, 3]).expect("why is the test harness OOMing on 12 bytes?"); + /// # process_data(&[1, 2, 3]).expect("reserving capacity for 12 bytes should never fail"); /// ``` #[stable(feature = "try_reserve", since = "1.57.0")] pub fn try_reserve_exact(&mut self, additional: usize) -> Result<(), TryReserveError> { @@ -1145,7 +1204,7 @@ impl VecDeque { /// /// Ok(output) /// } - /// # process_data(&[1, 2, 3]).expect("why is the test harness OOMing on 12 bytes?"); + /// # process_data(&[1, 2, 3]).expect("reserving capacity for 12 bytes should never fail"); /// ``` #[stable(feature = "try_reserve", since = "1.57.0")] pub fn try_reserve(&mut self, additional: usize) -> Result<(), TryReserveError> { @@ -1226,8 +1285,8 @@ impl VecDeque { let old_head = self.head; if self.len == 0 { - self.head = 0; - } else if self.head >= target_cap && tail_outside { + self.head = WrappedIndex::zero(); + } else if self.head.as_index() >= target_cap && tail_outside { // Head and tail are both out of bounds, so copy all of them to the front. // // H := head @@ -1238,9 +1297,9 @@ impl VecDeque { // [o o o o o o o . ] unsafe { // nonoverlapping because `self.head >= target_cap >= self.len`. - self.copy_nonoverlapping(self.head, 0, self.len); + self.copy_nonoverlapping(self.head, WrappedIndex::zero(), self.len); } - self.head = 0; + self.head = WrappedIndex::zero(); } else if self.head < target_cap && tail_outside { // Head is in bounds, tail is out of bounds. // Copy the overflowing part to the beginning of the @@ -1253,8 +1312,13 @@ impl VecDeque { // L H // [o o . o o o o o ] let len = self.head + self.len - target_cap; + // Safety: head is < target_cap, so the index is wrapped unsafe { - self.copy_nonoverlapping(target_cap, 0, len); + self.copy_nonoverlapping( + WrappedIndex::from_arbitrary_number(target_cap), + WrappedIndex::zero(), + len, + ); } } else if !self.is_contiguous() { // The head slice is at least partially out of bounds, tail is in bounds. @@ -1267,8 +1331,10 @@ impl VecDeque { // [o o o o o . . . . . . . . . o o ] // L H // [o o o o o . o o ] - let head_len = self.capacity() - self.head; - let new_head = target_cap - head_len; + let head_len = self.capacity() - self.head.as_index(); + + // head_len is at least one, so new_head will be < target_cap + let new_head = WrappedIndex::from_arbitrary_number(target_cap - head_len); unsafe { // can't use `copy_nonoverlapping()` here because the new and old // regions for the head might overlap. @@ -1279,7 +1345,7 @@ impl VecDeque { struct Guard<'a, T, A: Allocator> { deque: &'a mut VecDeque, - old_head: usize, + old_head: WrappedIndex, target_cap: usize, } @@ -1311,7 +1377,7 @@ impl VecDeque { /// /// `old_head` refers to the head index before `shrink_to` was called. `target_cap` /// is the capacity that it was trying to shrink to. - unsafe fn abort_shrink(&mut self, old_head: usize, target_cap: usize) { + unsafe fn abort_shrink(&mut self, old_head: WrappedIndex, target_cap: usize) { // Moral equivalent of self.head + self.len <= target_cap. Won't overflow // because `self.len <= target_cap`. if self.head <= target_cap - self.len { @@ -1320,7 +1386,7 @@ impl VecDeque { } // `shrink_to` already copied the head to fit into the new capacity, so this won't overflow. - let head_len = target_cap - self.head; + let head_len = target_cap - self.head.as_index(); // `self.head > target_cap - self.len` => `self.len > target_cap - self.head =: head_len` so this must be positive. let tail_len = self.len - head_len; @@ -1331,7 +1397,11 @@ impl VecDeque { unsafe { // The old tail and the new tail can't overlap because the head slice lies between them. The // head slice ends at `target_cap`, so that's where we copy to. - self.copy_nonoverlapping(0, target_cap, tail_len); + self.copy_nonoverlapping( + WrappedIndex::zero(), + WrappedIndex::from_arbitrary_number(target_cap), + tail_len, + ); } } else { // Either there's not enough spare capacity to make the deque contiguous, or the head is shorter than the tail @@ -1363,20 +1433,9 @@ impl VecDeque { /// buf.truncate(1); /// assert_eq!(buf, [5]); /// ``` + #[doc(alias = "retain_front")] #[stable(feature = "deque_extras", since = "1.16.0")] pub fn truncate(&mut self, len: usize) { - /// Runs the destructor for all items in the slice when it gets dropped (normally or - /// during unwinding). - struct Dropper<'a, T>(&'a mut [T]); - - impl<'a, T> Drop for Dropper<'a, T> { - fn drop(&mut self) { - unsafe { - ptr::drop_in_place(self.0); - } - } - } - // Safe because: // // * Any slice passed to `drop_in_place` is valid; the second case has @@ -1417,7 +1476,6 @@ impl VecDeque { /// # Examples /// /// ``` - /// # #![feature(vec_deque_truncate_front)] /// use std::collections::VecDeque; /// /// let mut buf = VecDeque::new(); @@ -1426,23 +1484,12 @@ impl VecDeque { /// buf.push_front(15); /// assert_eq!(buf, [15, 10, 5]); /// assert_eq!(buf.as_slices(), (&[15, 10, 5][..], &[][..])); - /// buf.truncate_front(1); + /// buf.retain_back(1); /// assert_eq!(buf.as_slices(), (&[5][..], &[][..])); /// ``` - #[unstable(feature = "vec_deque_truncate_front", issue = "140667")] - pub fn truncate_front(&mut self, len: usize) { - /// Runs the destructor for all items in the slice when it gets dropped (normally or - /// during unwinding). - struct Dropper<'a, T>(&'a mut [T]); - - impl<'a, T> Drop for Dropper<'a, T> { - fn drop(&mut self) { - unsafe { - ptr::drop_in_place(self.0); - } - } - } - + #[doc(alias = "truncate_front")] + #[stable(feature = "vec_deque_truncate_front", since = "1.99.0")] + pub fn retain_back(&mut self, len: usize) { unsafe { if len >= self.len { // No action is taken @@ -1456,7 +1503,7 @@ impl VecDeque { // and end < front.len() let end = front.len() - (len - back.len()); let drop_front = front.get_unchecked_mut(..end) as *mut _; - self.head += end; + self.head = self.head.add(end); self.len = len; ptr::drop_in_place(drop_front); } else { @@ -1464,7 +1511,7 @@ impl VecDeque { // 'end' is non-negative by the condition above let end = back.len() - len; let drop_back = back.get_unchecked_mut(..end) as *mut _; - self.head = self.to_physical_idx(self.len - len); + self.head = self.to_wrapped_index(self.len - len); self.len = len; // Make sure the second half is dropped even when a destructor @@ -1475,6 +1522,92 @@ impl VecDeque { } } + /// Shortens the deque to the elements within `range`, dropping the rest. + /// + /// # Panics + /// + /// Panics if the starting point is greater than the end point or if + /// the end point is greater than the length of the deque. + /// + /// # Examples + /// + /// ``` + /// # #![feature(vec_deque_retain_range)] + /// use std::collections::VecDeque; + /// + /// let mut buf: VecDeque<_> = (0..6).collect(); + /// buf.truncate_to_range(2..5); + /// assert_eq!(buf, [2, 3, 4]); + /// ``` + #[unstable(feature = "vec_deque_retain_range", issue = "156215")] + pub fn truncate_to_range(&mut self, range: R) + where + R: RangeBounds, + { + let Range { start, end } = slice::range(range, ..self.len); + + if start == 0 && end == self.len { + return; + } else if start == end { + self.clear(); + return; + } else if start == 0 { + self.truncate(end); + return; + } else if end == self.len { + self.retain_back(self.len - start); + return; + } + + // Both the dropped prefix [0..start) and the dropped suffix [end..self.len) are + // non-empty. Plan up to three physical slices to drop, then update head/len, then + // drop. Only one of the dropped prefix or dropped suffix can cross between slices. + let (front, back) = self.as_mut_slices(); + let flen = front.len(); + let blen = back.len(); + let fptr = front.as_mut_ptr(); + let bptr = back.as_mut_ptr(); + + unsafe { + let (drop_a, drop_b, drop_c) = if end <= flen { + // Kept range lies in `front`. The dropped suffix is the rest of `front` + // plus all of `back`. + let pre = ptr::slice_from_raw_parts_mut(fptr, start); + let mid = ptr::slice_from_raw_parts_mut(fptr.add(end), flen - end); + (pre, mid, Some(back as *mut [T])) + } else if start >= flen { + // Kept range lies in `back`. The dropped prefix is all of `front` plus the + // start of `back`. + let mid = ptr::slice_from_raw_parts_mut(bptr, start - flen); + let suf = ptr::slice_from_raw_parts_mut(bptr.add(end - flen), blen - (end - flen)); + (front as *mut [T], mid, Some(suf)) + } else { + // Kept range straddles the boundary. The dropped prefix is in `front`, the + // dropped suffix is in `back`. Only two regions to drop. + let pre = ptr::slice_from_raw_parts_mut(fptr, start); + let suf = ptr::slice_from_raw_parts_mut(bptr.add(end - flen), blen - (end - flen)); + (pre, suf, None) + }; + + // Set these once only, then drop. If we called truncate + retain_back, a panic in + // a destructor could leave this truncation in a half completed state. + self.head = self.to_wrapped_index(start); + self.len = end - start; + + match drop_c { + Some(c) => { + let _g_a = Dropper(&mut *drop_a); + let _g_b = Dropper(&mut *drop_b); + ptr::drop_in_place(c); + } + None => { + let _g_a = Dropper(&mut *drop_a); + ptr::drop_in_place(drop_b); + } + } + } + } + /// Returns a reference to the underlying allocator. #[unstable(feature = "allocator_api", issue = "32838")] #[inline] @@ -1679,20 +1812,20 @@ impl VecDeque { // `slice::range` guarantees that `start <= end <= len`. // because `len != 0`, we know that `start < end`, so `start < len` // and the indexing is valid. - let wrapped_start = self.to_physical_idx(start); + let wrapped_start = self.to_wrapped_index(start); // this subtraction can never overflow because `wrapped_start` is // at most `self.capacity()` (and if `self.capacity != 0`, then `wrapped_start` is strictly less // than `self.capacity`). - let head_len = self.capacity() - wrapped_start; + let head_len = self.capacity() - wrapped_start.as_index(); if head_len >= len { // we know that `len + wrapped_start <= self.capacity <= usize::MAX`, so this addition can't overflow - (wrapped_start..wrapped_start + len, 0..0) + (wrapped_start.as_index()..wrapped_start + len, 0..0) } else { // can't overflow because of the if condition let tail_len = len - head_len; - (wrapped_start..self.capacity(), 0..tail_len) + (wrapped_start.as_index()..self.capacity(), 0..tail_len) } } } @@ -1923,7 +2056,7 @@ impl VecDeque { pub fn clear(&mut self) { self.truncate(0); // Not strictly necessary, but leaves things in a more consistent/predictable state. - self.head = 0; + self.head = WrappedIndex::zero(); } /// Returns `true` if the deque contains an element equal to the @@ -2069,7 +2202,7 @@ impl VecDeque { None } else { let old_head = self.head; - self.head = self.to_physical_idx(1); + self.head = self.to_wrapped_index(1); self.len -= 1; unsafe { core::hint::assert_unchecked(self.len < self.capacity()); @@ -2100,7 +2233,7 @@ impl VecDeque { self.len -= 1; unsafe { core::hint::assert_unchecked(self.len < self.capacity()); - Some(self.buffer_read(self.to_physical_idx(self.len))) + Some(self.buffer_read(self.to_wrapped_index(self.len))) } } } @@ -2178,7 +2311,7 @@ impl VecDeque { /// *x -= 1; /// assert_eq!(d.front(), Some(&7)); /// ``` - #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "push_mut", since = "1.95.0")] #[must_use = "if you don't need a reference to the value, use `VecDeque::push_front` instead"] pub fn push_front_mut(&mut self, value: T) -> &mut T { if self.is_full() { @@ -2221,7 +2354,7 @@ impl VecDeque { /// *x += 1; /// assert_eq!(d.back(), Some(&10)); /// ``` - #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "push_mut", since = "1.95.0")] #[must_use = "if you don't need a reference to the value, use `VecDeque::push_back` instead"] pub fn push_back_mut(&mut self, value: T) -> &mut T { if self.is_full() { @@ -2230,7 +2363,7 @@ impl VecDeque { let len = self.len; self.len += 1; - unsafe { self.buffer_write(self.to_physical_idx(len), value) } + unsafe { self.buffer_write(self.to_wrapped_index(len), value) } } /// Prepends all contents of the iterator to the front of the deque. @@ -2428,7 +2561,7 @@ impl VecDeque { /// *x += 7; /// assert_eq!(vec_deque, &[1, 12, 2, 3]); /// ``` - #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "push_mut", since = "1.95.0")] #[must_use = "if you don't need a reference to the value, use `VecDeque::insert` instead"] pub fn insert_mut(&mut self, index: usize, value: T) -> &mut T { assert!(index <= self.len(), "index out of bounds"); @@ -2444,9 +2577,9 @@ impl VecDeque { // and panicked. unsafe { // see `remove()` for explanation why this wrap_copy() call is safe. - self.wrap_copy(self.to_physical_idx(index), self.to_physical_idx(index + 1), k); + self.wrap_copy(self.to_wrapped_index(index), self.to_wrapped_index(index + 1), k); self.len += 1; - self.buffer_write(self.to_physical_idx(index), value) + self.buffer_write(self.to_wrapped_index(index), value) } } else { let old_head = self.head; @@ -2454,7 +2587,7 @@ impl VecDeque { unsafe { self.wrap_copy(old_head, self.head, index); self.len += 1; - self.buffer_write(self.to_physical_idx(index), value) + self.buffer_write(self.to_wrapped_index(index), value) } } } @@ -2487,7 +2620,7 @@ impl VecDeque { return None; } - let wrapped_idx = self.to_physical_idx(index); + let wrapped_idx = self.to_wrapped_index(index); let elem = unsafe { Some(self.buffer_read(wrapped_idx)) }; @@ -2500,7 +2633,7 @@ impl VecDeque { self.len -= 1; } else { let old_head = self.head; - self.head = self.to_physical_idx(1); + self.head = self.to_wrapped_index(1); unsafe { self.wrap_copy(old_head, self.head, index) }; self.len -= 1; } @@ -2604,23 +2737,23 @@ impl VecDeque { if T::IS_ZST { self.len = self.len.checked_add(other.len).expect("capacity overflow"); other.len = 0; - other.head = 0; + other.head = WrappedIndex::zero(); return; } self.reserve(other.len); unsafe { let (left, right) = other.as_slices(); - self.copy_slice(self.to_physical_idx(self.len), left); + self.copy_slice(self.to_wrapped_index(self.len), left); // no overflow, because self.capacity() >= old_cap + left.len() >= self.len + left.len() - self.copy_slice(self.to_physical_idx(self.len + left.len()), right); + self.copy_slice(self.to_wrapped_index(self.len + left.len()), right); } // SAFETY: Update pointers after copying to avoid leaving doppelganger // in case of panics. self.len += other.len; // Now that we own its values, forget everything in `other`. other.len = 0; - other.head = 0; + other.head = WrappedIndex::zero(); } /// Retains only the elements specified by the predicate. @@ -2828,11 +2961,13 @@ impl VecDeque { #[stable(feature = "deque_make_contiguous", since = "1.48.0")] pub fn make_contiguous(&mut self) -> &mut [T] { if T::IS_ZST { - self.head = 0; + self.head = WrappedIndex::zero(); } if self.is_contiguous() { - unsafe { return slice::from_raw_parts_mut(self.ptr().add(self.head), self.len) } + unsafe { + return slice::from_raw_parts_mut(self.ptr().add(self.head.as_index()), self.len); + } } let &mut Self { head, len, .. } = self; @@ -2840,9 +2975,13 @@ impl VecDeque { let cap = self.capacity(); let free = cap - len; - let head_len = cap - head; - let tail = len - head_len; - let tail_len = tail; + let head_len = cap - head.as_index(); + + // tail <= head < capacity + // head cannot be <= capacity, because we know that VecDeque is non-empty, since it is not + // contiguous at this point + let tail = WrappedIndex::from_arbitrary_number(len - head_len); + let tail_len = tail.as_index(); if free >= head_len { // there is enough free space to copy the head in one go, @@ -2852,13 +2991,17 @@ impl VecDeque { // from: DEFGH....ABC // to: ABCDEFGH.... unsafe { - self.copy(0, head_len, tail_len); + self.copy( + WrappedIndex::zero(), + WrappedIndex::from_arbitrary_number(head_len), + tail_len, + ); // ...DEFGH.ABC - self.copy_nonoverlapping(head, 0, head_len); + self.copy_nonoverlapping(head, WrappedIndex::zero(), head_len); // ABCDEFGH.... } - self.head = 0; + self.head = WrappedIndex::zero(); } else if free >= tail_len { // there is enough free space to copy the tail in one go, // this means that we first shift the head forwards, and then @@ -2869,7 +3012,7 @@ impl VecDeque { unsafe { self.copy(head, tail, head_len); // FGHABCDE.... - self.copy_nonoverlapping(0, tail + head_len, tail_len); + self.copy_nonoverlapping(WrappedIndex::zero(), tail.add(head_len), tail_len); // ...ABCDEFGH. } @@ -2905,7 +3048,11 @@ impl VecDeque { // because we only move the tail forward as much as there's free space // behind it, we don't overwrite any elements of the head slice, and // the slices end up right next to each other. - self.copy(0, free, tail_len); + self.copy( + WrappedIndex::zero(), + WrappedIndex::from_arbitrary_number(free), + tail_len, + ); } // We just copied the tail right next to the head slice, @@ -2918,7 +3065,7 @@ impl VecDeque { // the used part of the buffer now is `free..self.capacity()`, so set // `head` to the beginning of that range. - self.head = free; + self.head = WrappedIndex::from_arbitrary_number(free); } } else { // head is shorter so: @@ -2931,7 +3078,11 @@ impl VecDeque { // right next to each other and we don't need to move any memory. if free != 0 { // copy the head slice to lie right behind the tail slice. - self.copy(self.head, tail_len, head_len); + self.copy( + self.head, + WrappedIndex::from_arbitrary_number(tail_len), + head_len, + ); } // because we copied the head slice so that both slices lie right @@ -2944,12 +3095,12 @@ impl VecDeque { // the used part of the buffer now is `0..self.len`, so set // `head` to the beginning of that range. - self.head = 0; + self.head = WrappedIndex::zero(); } } } - unsafe { slice::from_raw_parts_mut(ptr.add(self.head), self.len) } + unsafe { slice::from_raw_parts_mut(ptr.add(self.head.as_index()), self.len) } } /// Rotates the double-ended queue `n` places to the left. @@ -3049,16 +3200,16 @@ impl VecDeque { unsafe fn rotate_left_inner(&mut self, mid: usize) { debug_assert!(mid * 2 <= self.len()); unsafe { - self.wrap_copy(self.head, self.to_physical_idx(self.len), mid); + self.wrap_copy(self.head, self.to_wrapped_index(self.len), mid); } - self.head = self.to_physical_idx(mid); + self.head = self.to_wrapped_index(mid); } unsafe fn rotate_right_inner(&mut self, k: usize) { debug_assert!(k * 2 <= self.len()); self.head = self.wrap_sub(self.head, k); unsafe { - self.wrap_copy(self.to_physical_idx(self.len), self.head, k); + self.wrap_copy(self.to_wrapped_index(self.len), self.head, k); } } @@ -3459,7 +3610,7 @@ impl SpecExtendFromWithin for VecDeque { let (src, dst, count) = ranges[1]; for offset in (0..count).rev() { dst.add(offset).write((*src.add(offset)).clone()); - self.head -= 1; + self.head = self.head.sub(1); self.len += 1; } @@ -3469,16 +3620,18 @@ impl SpecExtendFromWithin for VecDeque { if let Some(offset) = iter.next() { dst.add(offset).write((*src.add(offset)).clone()); // After the first clone of the second range, wrap `head` around - if self.head == 0 { - self.head = cap; + if self.head.is_zero() { + // SAFETY: the wrapped index may be temporarily equal to the capacity even if it + // is not zero, because we subtract it one line below. + self.head = WrappedIndex::from_arbitrary_number(cap); } - self.head -= 1; + self.head = self.head.sub(1); self.len += 1; // Continue like normal for offset in iter { dst.add(offset).write((*src.add(offset)).clone()); - self.head -= 1; + self.head = self.head.sub(1); self.len += 1; } } @@ -3532,15 +3685,109 @@ impl SpecExtendFromWithin for VecDeque { } } -/// Returns the index in the underlying buffer for a given logical element index. -#[inline] -fn wrap_index(logical_index: usize, capacity: usize) -> usize { - debug_assert!( - (logical_index == 0 && capacity == 0) - || logical_index < capacity - || (logical_index - capacity) < capacity - ); - if logical_index >= capacity { logical_index - capacity } else { logical_index } +use index::{WrappedIndex, wrap_index}; + +// The code is separated into a module to make it harder to construct a BufferIndex without +// going through wrapping. +mod index { + use core::cmp::Ordering; + + /// Returns the index in the underlying buffer for a given logical element index. + #[inline] + pub(super) fn wrap_index(logical_index: usize, capacity: usize) -> WrappedIndex { + debug_assert!( + (logical_index == 0 && capacity == 0) + || logical_index < capacity + || (logical_index - capacity) < capacity + ); + if logical_index >= capacity { + WrappedIndex(logical_index - capacity) + } else { + WrappedIndex(logical_index) + } + } + + /// Represents an index that can be safely used to index the VecDeque buffer. + /// It exists as a separate type to avoid passing logical (unwrapped) indices to various + /// VecDeque functions by accident. + /// + /// The invariant of this index is that it is always < VecDeque capacity, unless the VecDeque + /// is empty (in that case the index can be 0 when the capacity is 0). + #[derive(Copy, Clone, Debug, PartialOrd, Ord, PartialEq, Eq)] + #[repr(transparent)] + pub(super) struct WrappedIndex(usize); + + impl WrappedIndex { + /// The newly constructed index has to be in-bounds for the VecDeque + /// that uses the index. + #[inline(always)] + pub(super) fn from_arbitrary_number(index: usize) -> Self { + Self(index) + } + + /// Safety invariant: the newly constructed index must still be in-bounds for the VecDeque + #[inline(always)] + pub(super) unsafe fn add(self, offset: usize) -> Self { + Self(self.0 + offset) + } + + /// Safety invariant: the newly constructed index must still be in-bounds for the VecDeque + #[inline(always)] + pub(super) unsafe fn sub(self, offset: usize) -> Self { + debug_assert!(self.0 >= offset); + Self(self.0 - offset) + } + + #[inline(always)] + pub(super) const fn zero() -> Self { + Self(0) + } + + #[inline(always)] + pub(super) fn abs_diff(self, other: Self) -> usize { + self.0.abs_diff(other.0) + } + + #[inline(always)] + pub(super) fn as_index(self) -> usize { + self.0 + } + + #[inline(always)] + pub(super) fn is_zero(self) -> bool { + self.0 == 0 + } + } + + impl core::ops::Add for WrappedIndex { + // The output might not be wrapped anymore + type Output = usize; + + #[inline(always)] + fn add(self, rhs: usize) -> Self::Output { + self.0 + rhs + } + } + + impl core::fmt::Display for WrappedIndex { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.0.fmt(f) + } + } + + impl core::cmp::PartialEq for WrappedIndex { + #[inline(always)] + fn eq(&self, other: &usize) -> bool { + self.0.eq(other) + } + } + + impl core::cmp::PartialOrd for WrappedIndex { + #[inline(always)] + fn partial_cmp(&self, other: &usize) -> Option { + self.0.partial_cmp(other) + } + } } #[stable(feature = "rust1", since = "1.0.0")] @@ -3627,7 +3874,7 @@ impl Index for VecDeque { #[inline] fn index(&self, index: usize) -> &T { - self.get(index).expect("Out of bounds access") + self.get(index).expect("out of bounds access") } } @@ -3635,7 +3882,7 @@ impl Index for VecDeque { impl IndexMut for VecDeque { #[inline] fn index_mut(&mut self, index: usize) -> &mut T { - self.get_mut(index).expect("Out of bounds access") + self.get_mut(index).expect("out of bounds access") } } @@ -3747,8 +3994,12 @@ impl From> for VecDeque { /// any additional memory. #[inline] fn from(other: Vec) -> Self { - let (ptr, len, cap, alloc) = other.into_raw_parts_with_alloc(); - Self { head: 0, len, buf: unsafe { RawVec::from_raw_parts_in(ptr, cap, alloc) } } + let (ptr, len, cap, alloc) = other.into_raw_parts_with_allocator(); + Self { + head: WrappedIndex::zero(), + len, + buf: unsafe { RawVec::from_raw_parts_in(ptr, cap, alloc) }, + } } } @@ -3793,8 +4044,8 @@ impl From> for Vec { let cap = other.capacity(); let alloc = ptr::read(other.allocator()); - if other.head != 0 { - ptr::copy(buf.add(other.head), buf, len); + if !other.head.is_zero() { + ptr::copy(buf.add(other.head.as_index()), buf, len); } Vec::from_raw_parts_in(buf, len, cap, alloc) } @@ -3821,7 +4072,7 @@ impl From<[T; N]> for VecDeque { ptr::copy_nonoverlapping(arr.as_ptr(), deq.ptr(), N); } } - deq.head = 0; + deq.head = WrappedIndex::zero(); deq.len = N; deq } diff --git a/library/alloc/src/collections/vec_deque/spec_extend.rs b/library/alloc/src/collections/vec_deque/spec_extend.rs index 184e8b769347d..0699d403d9de5 100644 --- a/library/alloc/src/collections/vec_deque/spec_extend.rs +++ b/library/alloc/src/collections/vec_deque/spec_extend.rs @@ -58,7 +58,7 @@ where self.reserve(additional); let written = unsafe { - self.write_iter_wrapping(self.to_physical_idx(self.len), iter, additional) + self.write_iter_wrapping(self.to_wrapped_index(self.len), iter, additional) }; debug_assert_eq!( @@ -78,15 +78,15 @@ where #[cfg(not(test))] impl SpecExtend> for VecDeque { - fn spec_extend(&mut self, mut iterator: vec::IntoIter) { + fn spec_extend(&mut self, iterator: vec::IntoIter) { let slice = iterator.as_slice(); self.reserve(slice.len()); unsafe { - self.copy_slice(self.to_physical_idx(self.len), slice); + self.copy_slice(self.to_wrapped_index(self.len), slice); self.len += slice.len(); } - iterator.forget_remaining_elements(); + iterator.forget_remaining_elements_and_dealloc(); } } @@ -109,7 +109,7 @@ where self.reserve(slice.len()); unsafe { - self.copy_slice(self.to_physical_idx(self.len), slice); + self.copy_slice(self.to_wrapped_index(self.len), slice); self.len += slice.len(); } } @@ -155,12 +155,12 @@ where #[cfg(not(test))] impl SpecExtendFront> for VecDeque { #[track_caller] - fn spec_extend_front(&mut self, mut iterator: vec::IntoIter) { + fn spec_extend_front(&mut self, iterator: vec::IntoIter) { let slice = iterator.as_slice(); self.reserve(slice.len()); // SAFETY: `slice.len()` space was just reserved and elements in the slice are forgotten after this call unsafe { prepend_reversed(self, slice) }; - iterator.forget_remaining_elements(); + iterator.forget_remaining_elements_and_dealloc(); } } @@ -170,12 +170,12 @@ impl SpecExtendFront>) { - let mut iterator = iterator.into_inner(); + let iterator = iterator.into_inner(); let slice = iterator.as_slice(); self.reserve(slice.len()); // SAFETY: `slice.len()` space was just reserved and elements in the slice are forgotten after this call unsafe { prepend(self, slice) }; - iterator.forget_remaining_elements(); + iterator.forget_remaining_elements_and_dealloc(); } } diff --git a/library/alloc/src/collections/vec_deque/splice.rs b/library/alloc/src/collections/vec_deque/splice.rs index d7b9a96291c39..a29e9c3742564 100644 --- a/library/alloc/src/collections/vec_deque/splice.rs +++ b/library/alloc/src/collections/vec_deque/splice.rs @@ -120,7 +120,7 @@ impl Drain<'_, T, A> { for idx in range_start..range_end { if let Some(new_item) = replace_with.next() { - let index = deque.to_physical_idx(idx); + let index = deque.to_wrapped_index(idx); unsafe { deque.buffer_write(index, new_item) }; deque.len += 1; self.drain_len -= 1; @@ -138,17 +138,60 @@ impl Drain<'_, T, A> { /// self.deque must be valid. unsafe fn move_tail(&mut self, additional: usize) { let deque = unsafe { self.deque.as_mut() }; - let tail_start = deque.len + self.drain_len; - deque.buf.reserve(tail_start + self.tail_len, additional); + + // `Drain::new` modifies the deque's len (so does `Drain::fill` here) + // directly with the start bound of the range passed into + // `VecDeque::splice`. This causes a few different issue: + // - Most notably, there will be a hole at the end of the + // buffer when our buffer resizes in the case that our + // data wraps around. + // - We cannot use `VecDeque::reserve` directly because + // how it reserves more space and updates the `VecDeque`'s + // `head` field accordingly depends on the `VecDeque`'s + // actual `len`. + // - We cannot just directly modify `VecDeque`'s `len` and + // and call `VecDeque::reserve` afterward because if + // `VecDeque::reserve` panics on capacity overflow, + // well now our `VecDeque`'s head does not get updated + // and we still have a potential hole at the end of the + // buffer. + // Therefore, we manually reserve additional space (if necessary) + // based on calculating the actual `len` of the `VecDeque` and adjust + // `VecDeque`'s len right *after* the panicking region of `VecDeque::reserve` + // (that is `RawVec` `reserve()` call) + + let drain_start = deque.len; + let tail_start = drain_start + self.drain_len; + + // Actual VecDeque's len = drain_start + tail_len + drain_len + let actual_len = drain_start + self.tail_len + self.drain_len; + let new_cap = actual_len.checked_add(additional).expect("capacity overflow"); + let old_cap = deque.capacity(); + + if new_cap > old_cap { + deque.buf.reserve(actual_len, additional); + // If new_cap doesn't panic, we can safely set the `VecDeque` len to its + // actual len; this needs to be done in order to set deque.head correctly + // on `VecDeque::handle_capacity_increase` + deque.len = actual_len; + // SAFETY: this cannot panic since our internal buffer's new_cap should + // be bigger than the passed in old_cap + unsafe { + deque.handle_capacity_increase(old_cap); + } + } let new_tail_start = tail_start + additional; unsafe { deque.wrap_copy( - deque.to_physical_idx(tail_start), - deque.to_physical_idx(new_tail_start), + deque.to_wrapped_index(tail_start), + deque.to_wrapped_index(new_tail_start), self.tail_len, ); } + + // revert the `VecDeque` len to what it was before + deque.len = drain_start; self.drain_len += additional; } } diff --git a/library/alloc/src/collections/vec_deque/tests.rs b/library/alloc/src/collections/vec_deque/tests.rs index dc50cc34d9dac..d9cf56de7bb6b 100644 --- a/library/alloc/src/collections/vec_deque/tests.rs +++ b/library/alloc/src/collections/vec_deque/tests.rs @@ -12,7 +12,7 @@ fn bench_push_back_100(b: &mut test::Bencher) { for i in 0..100 { deq.push_back(i); } - deq.head = 0; + deq.head = WrappedIndex::zero(); deq.len = 0; }) } @@ -24,7 +24,7 @@ fn bench_push_front_100(b: &mut test::Bencher) { for i in 0..100 { deq.push_front(i); } - deq.head = 0; + deq.head = WrappedIndex::zero(); deq.len = 0; }) } @@ -38,7 +38,7 @@ fn bench_pop_back_100(b: &mut test::Bencher) { unsafe { deq.ptr().write_bytes(0u8, size + 1) }; b.iter(|| { - deq.head = 0; + deq.head = WrappedIndex::zero(); deq.len = 100; while !deq.is_empty() { test::black_box(deq.pop_back()); @@ -88,7 +88,7 @@ fn bench_pop_front_100(b: &mut test::Bencher) { unsafe { deq.ptr().write_bytes(0u8, size + 1) }; b.iter(|| { - deq.head = 0; + deq.head = WrappedIndex::zero(); deq.len = 100; while !deq.is_empty() { test::black_box(deq.pop_front()); @@ -109,7 +109,7 @@ fn test_swap_front_back_remove() { let expected: VecDeque<_> = if back { (0..len).collect() } else { (0..len).rev().collect() }; for head_pos in 0..usable_cap { - tester.head = head_pos; + tester.head = WrappedIndex::from_arbitrary_number(head_pos); tester.len = 0; if back { for i in 0..len * 2 { @@ -127,7 +127,7 @@ fn test_swap_front_back_remove() { assert_eq!(tester.swap_remove_front(idx), Some(len * 2 - 1 - i)); } } - assert!(tester.head <= tester.capacity()); + assert!(tester.head.as_index() <= tester.capacity()); assert!(tester.len <= tester.capacity()); assert_eq!(tester, expected); } @@ -155,7 +155,7 @@ fn test_insert() { let expected = (0..).take(len).collect::>(); for head_pos in 0..cap { for to_insert in 0..len { - tester.head = head_pos; + tester.head = WrappedIndex::from_arbitrary_number(head_pos); tester.len = 0; for i in 0..len { if i != to_insert { @@ -636,7 +636,7 @@ fn test_remove() { let expected = (0..).take(len).collect::>(); for head_pos in 0..cap { for to_remove in 0..=len { - tester.head = head_pos; + tester.head = WrappedIndex::from_arbitrary_number(head_pos); tester.len = 0; for i in 0..len { if i == to_remove { @@ -666,7 +666,7 @@ fn test_range() { for head in 0..=cap { for start in 0..=len { for end in start..=len { - tester.head = head; + tester.head = WrappedIndex::from_arbitrary_number(head); tester.len = 0; for i in 0..len { tester.push_back(i); @@ -691,7 +691,7 @@ fn test_range_mut() { for head in 0..=cap { for start in 0..=len { for end in start..=len { - tester.head = head; + tester.head = WrappedIndex::from_arbitrary_number(head); tester.len = 0; for i in 0..len { tester.push_back(i); @@ -725,7 +725,7 @@ fn test_drain() { for head in 0..cap { for drain_start in 0..=len { for drain_end in drain_start..=len { - tester.head = head; + tester.head = WrappedIndex::from_arbitrary_number(head); tester.len = 0; for i in 0..len { tester.push_back(i); @@ -782,7 +782,7 @@ fn test_shrink_to() { assert_eq!(deque.capacity(), cap); // we can let the head point anywhere in the buffer since the deque is empty. - deque.head = head; + deque.head = WrappedIndex::from_arbitrary_number(head); deque.extend(1..=len); deque.shrink_to(target_cap); @@ -811,7 +811,7 @@ fn test_shrink_to_fit() { let expected = (0..).take(len).collect::>(); for head_pos in 0..=max_cap { tester.reserve(head_pos); - tester.head = head_pos; + tester.head = WrappedIndex::from_arbitrary_number(head_pos); tester.len = 0; tester.reserve(63); for i in 0..len { @@ -848,7 +848,7 @@ fn test_split_off() { let expected_other = (at..).take(len - at).collect::>(); for head_pos in 0..cap { - tester.head = head_pos; + tester.head = WrappedIndex::from_arbitrary_number(head_pos); tester.len = 0; for i in 0..len { tester.push_back(i); diff --git a/library/alloc/src/ffi/c_str.rs b/library/alloc/src/ffi/c_str.rs index d6dcba7107a9c..b340cf9566f2e 100644 --- a/library/alloc/src/ffi/c_str.rs +++ b/library/alloc/src/ffi/c_str.rs @@ -84,7 +84,7 @@ use crate::vec::Vec; /// /// // We are certain that our string doesn't have 0 bytes in the middle, /// // so we can .expect() -/// let c_to_print = CString::new("Hello, world!").expect("CString::new failed"); +/// let c_to_print = CString::new("Hello, world!").expect("we provided a string without NUL bytes, so CString::new should not fail"); /// unsafe { /// my_printer(c_to_print.as_ptr()); /// } @@ -103,6 +103,7 @@ use crate::vec::Vec; /// and other memory errors. #[derive(PartialEq, PartialOrd, Eq, Ord, Hash, Clone)] #[rustc_diagnostic_item = "cstring_type"] +#[rustc_insignificant_dtor] #[stable(feature = "alloc_c_string", since = "1.64.0")] pub struct CString { // Invariant 1: the slice ends with a zero byte and has a length of at least one. @@ -241,7 +242,7 @@ impl CString { /// /// extern "C" { fn puts(s: *const c_char); } /// - /// let to_print = CString::new("Hello!").expect("CString::new failed"); + /// let to_print = CString::new("Hello!").expect("we provided a string without NUL bytes, so CString::new should not fail"); /// unsafe { /// puts(to_print.as_ptr()); /// } @@ -320,6 +321,10 @@ impl CString { /// assertion is made that `v` contains no 0 bytes, and it requires an /// actual byte vector, not anything that can be converted to one with Into. /// + /// # Safety + /// + /// The caller must ensure `v` contains no nul bytes in its contents. + /// /// # Examples /// /// ``` @@ -461,12 +466,12 @@ impl CString { /// use std::ffi::CString; /// /// let valid_utf8 = vec![b'f', b'o', b'o']; - /// let cstring = CString::new(valid_utf8).expect("CString::new failed"); - /// assert_eq!(cstring.into_string().expect("into_string() call failed"), "foo"); + /// let cstring = CString::new(valid_utf8).expect("we provided bytes that do not have a NUL byte, so CString::new should not fail"); + /// assert_eq!(cstring.into_string().expect("we provided bytes that are valid UTF-8, so `into_string` should not fail"), "foo"); /// /// let invalid_utf8 = vec![b'f', 0xff, b'o', b'o']; - /// let cstring = CString::new(invalid_utf8).expect("CString::new failed"); - /// let err = cstring.into_string().err().expect("into_string().err() failed"); + /// let cstring = CString::new(invalid_utf8).expect("we provided bytes that do not have a NUL byte, so CString::new should not fail"); + /// let err = cstring.into_string().expect_err("we provided bytes that are invalid UTF-8, so `into_string` should fail"); /// assert_eq!(err.utf8_error().valid_up_to(), 1); /// ``` #[stable(feature = "cstring_into", since = "1.7.0")] @@ -572,7 +577,7 @@ impl CString { /// let c_string = CString::from(c"foo"); /// let cstr = c_string.as_c_str(); /// assert_eq!(cstr, - /// CStr::from_bytes_with_nul(b"foo\0").expect("CStr::from_bytes_with_nul failed")); + /// CStr::from_bytes_with_nul(b"foo\0").expect("we provided bytes that has one NUL byte exactly at the end, so CStr::from_bytes_with_nul should not fail")); /// ``` #[inline] #[must_use] @@ -655,7 +660,7 @@ impl CString { /// use std::ffi::CString; /// assert_eq!( /// CString::from_vec_with_nul(b"abc\0".to_vec()) - /// .expect("CString::from_vec_with_nul failed"), + /// .expect("we provided bytes that has one NUL byte exactly at the end, so CString::from_vec_with_nul should not fail"), /// c"abc".to_owned() /// ); /// ``` @@ -694,7 +699,6 @@ impl CString { // memory-unsafe code from working by accident. Inline // to prevent LLVM from optimizing it away in debug builds. #[stable(feature = "cstring_drop", since = "1.13.0")] -#[rustc_insignificant_dtor] impl Drop for CString { #[inline] fn drop(&mut self) { @@ -1073,9 +1077,17 @@ impl ToOwned for CStr { } fn clone_into(&self, target: &mut CString) { - let mut b = mem::take(&mut target.inner).into_vec(); - self.to_bytes_with_nul().clone_into(&mut b); - target.inner = b.into_boxed_slice(); + let src = self.to_bytes_with_nul(); + // If the lengths match, we can reuse the existing allocation without any overhead. + if target.inner.len() == src.len() { + target.inner.copy_from_slice(src); + } else { + // Reuse the existing allocation's capacity by converting to a Vec. + // We temporarily replace `target` with a valid dummy to remain panic-safe. + let mut b = mem::replace(&mut target.inner, Box::new([0])).into_vec(); + self.to_bytes_with_nul().clone_into(&mut b); + target.inner = b.into_boxed_slice(); + } } } diff --git a/library/alloc/src/intrinsics.rs b/library/alloc/src/intrinsics.rs new file mode 100644 index 0000000000000..a1e358e077cb6 --- /dev/null +++ b/library/alloc/src/intrinsics.rs @@ -0,0 +1,15 @@ +//! Intrinsics that cannot be moved to `core` because they depend on `alloc` types. +#![unstable(feature = "liballoc_internals", issue = "none")] + +use core::mem::MaybeUninit; + +use crate::boxed::Box; + +/// Writes `x` into `b`. +/// +/// This is needed for `vec!`, which can't afford any extra copies of the argument (or else debug +/// builds regress), has to be written fully as a call chain without `let` (or else this breaks inference +/// of e.g. unsizing coercions), and can't use an `unsafe` block as that would then also +/// include the user-provided `$x`. +#[rustc_intrinsic] +pub fn write_box_via_move(b: Box>, x: T) -> Box>; diff --git a/library/alloc/src/io/buf_read.rs b/library/alloc/src/io/buf_read.rs new file mode 100644 index 0000000000000..bba1c2b8c8a45 --- /dev/null +++ b/library/alloc/src/io/buf_read.rs @@ -0,0 +1,500 @@ +use core::slice::memchr; + +use crate::io::{ErrorKind, Lines, Read, Result, Split, append_to_string, lines, split}; +use crate::string::String; +use crate::vec::Vec; + +/// A `BufRead` is a type of [`Read`]er which has an internal buffer, allowing it +/// to perform extra ways of reading. +/// +/// For example, reading line-by-line is inefficient without using a buffer, so +/// if you want to read by line, you'll need `BufRead`, which includes a +/// [`read_line`] method as well as a [`lines`] iterator. +/// +/// # Examples +/// +/// A locked standard input implements `BufRead`: +/// +/// ```no_run +/// use std::io; +/// use std::io::prelude::*; +/// +/// let stdin = io::stdin(); +/// for line in stdin.lock().lines() { +/// println!("{}", line?); +/// } +/// # std::io::Result::Ok(()) +/// ``` +/// +/// If you have something that implements [`Read`], you can use the `BufReader` +/// type to turn it into a `BufRead`. +/// +/// For example, `File` implements [`Read`], but not `BufRead`. +/// `BufReader` to the rescue! +/// +/// [`read_line`]: BufRead::read_line +/// [`lines`]: BufRead::lines +/// +/// ```no_run +/// use std::io::{self, BufReader}; +/// use std::io::prelude::*; +/// use std::fs::File; +/// +/// fn main() -> io::Result<()> { +/// let f = File::open("foo.txt")?; +/// let f = BufReader::new(f); +/// +/// for line in f.lines() { +/// let line = line?; +/// println!("{line}"); +/// } +/// +/// Ok(()) +/// } +/// ``` +#[stable(feature = "rust1", since = "1.0.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "IoBufRead")] +pub trait BufRead: Read { + /// Returns the contents of the internal buffer, filling it with more data, via [`Read`] methods, if empty. + /// + /// This is a lower-level method and is meant to be used together with [`consume`], + /// which can be used to mark bytes that should not be returned by subsequent calls to `read`. + /// + /// [`consume`]: BufRead::consume + /// + /// Returns an empty buffer when the stream has reached EOF. + /// + /// # Errors + /// + /// This function will return an I/O error if a [`Read`] method was called, but returned an error. + /// + /// # Examples + /// + /// A locked standard input implements `BufRead`: + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// + /// let stdin = io::stdin(); + /// let mut stdin = stdin.lock(); + /// + /// let buffer = stdin.fill_buf()?; + /// + /// // work with buffer + /// println!("{buffer:?}"); + /// + /// // mark the bytes we worked with as read + /// let length = buffer.len(); + /// stdin.consume(length); + /// # std::io::Result::Ok(()) + /// ``` + #[stable(feature = "rust1", since = "1.0.0")] + fn fill_buf(&mut self) -> Result<&[u8]>; + + /// Marks the given `amount` of additional bytes from the internal buffer as having been read. + /// Subsequent calls to `read` only return bytes that have not been marked as read. + /// + /// This is a lower-level method and is meant to be used together with [`fill_buf`], + /// which can be used to fill the internal buffer via [`Read`] methods. + /// + /// It is a logic error if `amount` exceeds the number of unread bytes in the internal buffer, which is returned by [`fill_buf`]. + /// + /// # Examples + /// + /// Since `consume()` is meant to be used with [`fill_buf`], + /// that method's example includes an example of `consume()`. + /// + /// [`fill_buf`]: BufRead::fill_buf + #[stable(feature = "rust1", since = "1.0.0")] + fn consume(&mut self, amount: usize); + + /// Checks if there is any data left to be `read`. + /// + /// This function may fill the buffer to check for data, + /// so this function returns `Result`, not `bool`. + /// + /// The default implementation calls `fill_buf` and checks that the + /// returned slice is empty (which means that there is no data left, + /// since EOF is reached). + /// + /// # Errors + /// + /// This function will return an I/O error if a [`Read`] method was called, but returned an error. + /// + /// Examples + /// + /// ``` + /// #![feature(buf_read_has_data_left)] + /// use std::io; + /// use std::io::prelude::*; + /// + /// let stdin = io::stdin(); + /// let mut stdin = stdin.lock(); + /// + /// while stdin.has_data_left()? { + /// let mut line = String::new(); + /// stdin.read_line(&mut line)?; + /// // work with line + /// println!("{line:?}"); + /// } + /// # std::io::Result::Ok(()) + /// ``` + #[unstable(feature = "buf_read_has_data_left", issue = "86423")] + fn has_data_left(&mut self) -> Result { + self.fill_buf().map(|b| !b.is_empty()) + } + + /// Reads all bytes into `buf` until the delimiter `byte` or EOF is reached. + /// + /// This function will read bytes from the underlying stream until the + /// delimiter or EOF is found. Once found, all bytes up to, and including, + /// the delimiter (if found) will be appended to `buf`. + /// + /// If successful, this function will return the total number of bytes read. + /// + /// This function is blocking and should be used carefully: it is possible for + /// an attacker to continuously send bytes without ever sending the delimiter + /// or EOF. + /// + /// # Errors + /// + /// This function will ignore all instances of [`ErrorKind::Interrupted`] and + /// will otherwise return any errors returned by [`fill_buf`]. + /// + /// If an I/O error is encountered then all bytes read so far will be + /// present in `buf` and its length will have been adjusted appropriately. + /// + /// [`fill_buf`]: BufRead::fill_buf + /// + /// # Examples + /// + /// [`std::io::Cursor`][`Cursor`] is a type that implements `BufRead`. In + /// this example, we use [`Cursor`] to read all the bytes in a byte slice + /// in hyphen delimited segments: + /// + /// [`Cursor`]: crate::io::Cursor + /// + /// ``` + /// use std::io::{self, BufRead}; + /// + /// let mut cursor = io::Cursor::new(b"lorem-ipsum"); + /// let mut buf = vec![]; + /// + /// // cursor is at 'l' + /// let num_bytes = cursor.read_until(b'-', &mut buf) + /// .expect("reading from cursor won't fail"); + /// assert_eq!(num_bytes, 6); + /// assert_eq!(buf, b"lorem-"); + /// buf.clear(); + /// + /// // cursor is at 'i' + /// let num_bytes = cursor.read_until(b'-', &mut buf) + /// .expect("reading from cursor won't fail"); + /// assert_eq!(num_bytes, 5); + /// assert_eq!(buf, b"ipsum"); + /// buf.clear(); + /// + /// // cursor is at EOF + /// let num_bytes = cursor.read_until(b'-', &mut buf) + /// .expect("reading from cursor won't fail"); + /// assert_eq!(num_bytes, 0); + /// assert_eq!(buf, b""); + /// ``` + #[stable(feature = "rust1", since = "1.0.0")] + fn read_until(&mut self, byte: u8, buf: &mut Vec) -> Result { + default_read_until(self, byte, buf) + } + + /// Skips all bytes until the delimiter `byte` or EOF is reached. + /// + /// This function will read (and discard) bytes from the underlying stream until the + /// delimiter or EOF is found. + /// + /// If successful, this function will return the total number of bytes read, + /// including the delimiter byte if found. + /// + /// This is useful for efficiently skipping data such as NUL-terminated strings + /// in binary file formats without buffering. + /// + /// This function is blocking and should be used carefully: it is possible for + /// an attacker to continuously send bytes without ever sending the delimiter + /// or EOF. + /// + /// # Errors + /// + /// This function will ignore all instances of [`ErrorKind::Interrupted`] and + /// will otherwise return any errors returned by [`fill_buf`]. + /// + /// If an I/O error is encountered then all bytes read so far will be + /// present in `buf` and its length will have been adjusted appropriately. + /// + /// [`fill_buf`]: BufRead::fill_buf + /// + /// # Examples + /// + /// [`std::io::Cursor`][`Cursor`] is a type that implements `BufRead`. In + /// this example, we use [`Cursor`] to read some NUL-terminated information + /// about Ferris from a binary string, skipping the fun fact: + /// + /// [`Cursor`]: crate::io::Cursor + /// + /// ``` + /// use std::io::{self, BufRead}; + /// + /// let mut cursor = io::Cursor::new(b"Ferris\0Likes long walks on the beach\0Crustacean\0!"); + /// + /// // read name + /// let mut name = Vec::new(); + /// let num_bytes = cursor.read_until(b'\0', &mut name) + /// .expect("reading from cursor won't fail"); + /// assert_eq!(num_bytes, 7); + /// assert_eq!(name, b"Ferris\0"); + /// + /// // skip fun fact + /// let num_bytes = cursor.skip_until(b'\0') + /// .expect("reading from cursor won't fail"); + /// assert_eq!(num_bytes, 30); + /// + /// // read animal type + /// let mut animal = Vec::new(); + /// let num_bytes = cursor.read_until(b'\0', &mut animal) + /// .expect("reading from cursor won't fail"); + /// assert_eq!(num_bytes, 11); + /// assert_eq!(animal, b"Crustacean\0"); + /// + /// // reach EOF + /// let num_bytes = cursor.skip_until(b'\0') + /// .expect("reading from cursor won't fail"); + /// assert_eq!(num_bytes, 1); + /// ``` + #[stable(feature = "bufread_skip_until", since = "1.83.0")] + fn skip_until(&mut self, byte: u8) -> Result { + default_skip_until(self, byte) + } + + /// Reads all bytes until a newline (the `0xA` byte) is reached, and append + /// them to the provided [`String`] buffer. + /// + /// Previous content of the buffer will be preserved. To avoid appending to + /// the buffer, you need to [`clear`] it first. + /// + /// This function will read bytes from the underlying stream until the + /// newline delimiter (the `0xA` byte) or EOF is found. Once found, all bytes + /// up to, and including, the delimiter (if found) will be appended to + /// `buf`. + /// + /// If successful, this function will return the total number of bytes read. + /// + /// If this function returns [`Ok(0)`], the stream has reached EOF. + /// + /// This function is blocking and should be used carefully: it is possible for + /// an attacker to continuously send bytes without ever sending a newline + /// or EOF. You can use [`take`] to limit the maximum number of bytes read. + /// + /// [`Ok(0)`]: Ok + /// [`clear`]: String::clear + /// [`take`]: crate::io::Read::take + /// + /// # Errors + /// + /// This function has the same error semantics as [`read_until`] and will + /// also return an error if the read bytes are not valid UTF-8. If an I/O + /// error is encountered then `buf` may contain some bytes already read in + /// the event that all data read so far was valid UTF-8. + /// + /// [`read_until`]: BufRead::read_until + /// + /// # Examples + /// + /// [`std::io::Cursor`][`Cursor`] is a type that implements `BufRead`. In + /// this example, we use [`Cursor`] to read all the lines in a byte slice: + /// + /// [`Cursor`]: crate::io::Cursor + /// + /// ``` + /// use std::io::{self, BufRead}; + /// + /// let mut cursor = io::Cursor::new(b"foo\nbar"); + /// let mut buf = String::new(); + /// + /// // cursor is at 'f' + /// let num_bytes = cursor.read_line(&mut buf) + /// .expect("reading from cursor won't fail"); + /// assert_eq!(num_bytes, 4); + /// assert_eq!(buf, "foo\n"); + /// buf.clear(); + /// + /// // cursor is at 'b' + /// let num_bytes = cursor.read_line(&mut buf) + /// .expect("reading from cursor won't fail"); + /// assert_eq!(num_bytes, 3); + /// assert_eq!(buf, "bar"); + /// buf.clear(); + /// + /// // cursor is at EOF + /// let num_bytes = cursor.read_line(&mut buf) + /// .expect("reading from cursor won't fail"); + /// assert_eq!(num_bytes, 0); + /// assert_eq!(buf, ""); + /// ``` + #[stable(feature = "rust1", since = "1.0.0")] + fn read_line(&mut self, buf: &mut String) -> Result { + // Note that we are not calling the `.read_until` method here, but + // rather our hardcoded implementation. For more details as to why, see + // the comments in `default_read_to_string`. + unsafe { append_to_string(buf, |b| default_read_until(self, b'\n', b)) } + } + + /// Returns an iterator over the contents of this reader split on the byte + /// `byte`. + /// + /// The iterator returned from this function will return instances of + /// [io::Result]<[Vec]\>. Each vector returned will *not* have + /// the delimiter byte at the end. + /// + /// This function will yield errors whenever [`read_until`] would have + /// also yielded an error. + /// + /// [io::Result]: self::Result "io::Result" + /// [`read_until`]: BufRead::read_until + /// + /// # Examples + /// + /// [`std::io::Cursor`][`Cursor`] is a type that implements `BufRead`. In + /// this example, we use [`Cursor`] to iterate over all hyphen delimited + /// segments in a byte slice + /// + /// [`Cursor`]: crate::io::Cursor + /// + /// ``` + /// use std::io::{self, BufRead}; + /// + /// let cursor = io::Cursor::new(b"lorem-ipsum-dolor"); + /// + /// let mut split_iter = cursor.split(b'-').map(|l| l.unwrap()); + /// assert_eq!(split_iter.next(), Some(b"lorem".to_vec())); + /// assert_eq!(split_iter.next(), Some(b"ipsum".to_vec())); + /// assert_eq!(split_iter.next(), Some(b"dolor".to_vec())); + /// assert_eq!(split_iter.next(), None); + /// ``` + #[stable(feature = "rust1", since = "1.0.0")] + fn split(self, byte: u8) -> Split + where + Self: Sized, + { + split(self, byte) + } + + /// Returns an iterator over the lines of this reader. + /// + /// The iterator returned from this function will yield instances of + /// [io::Result]<[String]>. Each string returned will *not* have a newline + /// byte (the `0xA` byte) or `CRLF` (`0xD`, `0xA` bytes) at the end. + /// + /// [io::Result]: crate::io::Result "io::Result" + /// + /// # Examples + /// + /// [`std::io::Cursor`][`Cursor`] is a type that implements `BufRead`. In + /// this example, we use [`Cursor`] to iterate over all the lines in a byte + /// slice. + /// + /// [`Cursor`]: crate::io::Cursor + /// + /// ``` + /// use std::io::{self, BufRead}; + /// + /// let cursor = io::Cursor::new(b"lorem\nipsum\r\ndolor"); + /// + /// let mut lines_iter = cursor.lines().map(|l| l.unwrap()); + /// assert_eq!(lines_iter.next(), Some(String::from("lorem"))); + /// assert_eq!(lines_iter.next(), Some(String::from("ipsum"))); + /// assert_eq!(lines_iter.next(), Some(String::from("dolor"))); + /// assert_eq!(lines_iter.next(), None); + /// ``` + /// + /// # Errors + /// + /// Each line of the iterator has the same error semantics as [`BufRead::read_line`]. + #[stable(feature = "rust1", since = "1.0.0")] + fn lines(self) -> Lines + where + Self: Sized, + { + lines(self) + } +} + +fn default_read_until( + r: &mut R, + delim: u8, + buf: &mut Vec, +) -> Result { + let mut read = 0; + loop { + let (done, used) = { + let available = match r.fill_buf() { + Ok(n) => n, + Err(ref e) if e.is_interrupted() => continue, + Err(e) => return Err(e), + }; + let (done, available) = match memchr::memchr(delim, available) { + Some(i) => (true, &available[..=i]), + None => (false, available), + }; + + cfg_select! { + no_global_oom_handling => { + let count = available.len(); + buf.try_reserve(count)?; + + // SAFETY: + // * self and buf are non-overlapping + // * buf[..len] is already initialized + // * buf[len..len + count] is initialized by copy_nonoverlapping + // * len + count is within the capacity of buf based on the reservation completed above + unsafe { + let len = buf.len(); + let src = available.as_ptr(); + let dst = buf.as_mut_ptr().add(len); + core::ptr::copy_nonoverlapping(src, dst, count); + buf.set_len(len + count); + } + } + _ => { + buf.extend_from_slice(available); + } + } + + (done, available.len()) + }; + r.consume(used); + read += used; + if done || used == 0 { + return Ok(read); + } + } +} + +fn default_skip_until(r: &mut R, delim: u8) -> Result { + let mut read = 0; + loop { + let (done, used) = { + let available = match r.fill_buf() { + Ok(n) => n, + Err(ref e) if e.kind() == ErrorKind::Interrupted => continue, + Err(e) => return Err(e), + }; + match memchr::memchr(delim, available) { + Some(i) => (true, i + 1), + None => (false, available.len()), + } + }; + r.consume(used); + read += used; + if done || used == 0 { + return Ok(read); + } + } +} diff --git a/library/std/src/io/buffered/bufreader.rs b/library/alloc/src/io/buffered/bufreader.rs similarity index 90% rename from library/std/src/io/buffered/bufreader.rs rename to library/alloc/src/io/buffered/bufreader.rs index 40441dc057d0d..e8b3302e29b98 100644 --- a/library/std/src/io/buffered/bufreader.rs +++ b/library/alloc/src/io/buffered/bufreader.rs @@ -7,6 +7,8 @@ use crate::io::{ self, BorrowedCursor, BufRead, DEFAULT_BUF_SIZE, IoSliceMut, Read, Seek, SeekFrom, SizeHint, SpecReadByte, uninlined_slow_read_byte, }; +use crate::string::String; +use crate::vec::Vec; /// The `BufReader` struct adds buffering to any reader. /// @@ -27,8 +29,9 @@ use crate::io::{ /// unwrapping the `BufReader` with [`BufReader::into_inner`] can also cause /// data loss. /// -/// [`TcpStream::read`]: crate::net::TcpStream::read -/// [`TcpStream`]: crate::net::TcpStream +// FIXME(#74481): Hard-links required to link from `alloc` to `std` +/// [`TcpStream::read`]: ../../std/net/struct.TcpStream.html#method.read +/// [`TcpStream`]: ../../std/net/struct.TcpStream.html /// /// # Examples /// @@ -48,6 +51,7 @@ use crate::io::{ /// } /// ``` #[stable(feature = "rust1", since = "1.0.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "IoBufReader")] pub struct BufReader { buf: Buffer, inner: R, @@ -69,17 +73,21 @@ impl BufReader { /// Ok(()) /// } /// ``` + #[cfg(not(no_global_oom_handling))] #[stable(feature = "rust1", since = "1.0.0")] pub fn new(inner: R) -> BufReader { BufReader::with_capacity(DEFAULT_BUF_SIZE, inner) } - pub(crate) fn try_new_buffer() -> io::Result { - Buffer::try_with_capacity(DEFAULT_BUF_SIZE) - } - - pub(crate) fn with_buffer(inner: R, buf: Buffer) -> Self { - Self { inner, buf } + /// Attempts to allocate an internal buffer, _then_ calls the provided function + /// to retrieve the inner reader `R`. + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + #[inline] + pub fn try_new_with(f: impl FnOnce() -> io::Result) -> io::Result { + let buf = Buffer::try_with_capacity(DEFAULT_BUF_SIZE)?; + let inner = f()?; + Ok(Self { inner, buf }) } /// Creates a new `BufReader` with the specified buffer capacity. @@ -98,6 +106,7 @@ impl BufReader { /// Ok(()) /// } /// ``` + #[cfg(not(no_global_oom_handling))] #[stable(feature = "rust1", since = "1.0.0")] pub fn with_capacity(capacity: usize, inner: R) -> BufReader { BufReader { inner, buf: Buffer::with_capacity(capacity) } @@ -279,16 +288,19 @@ impl BufReader { /// Invalidates all data in the internal buffer. #[inline] - pub(in crate::io) fn discard_buffer(&mut self) { + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub fn discard_buffer(&mut self) { self.buf.discard_buffer() } } // This is only used by a test which asserts that the initialization-tracking is correct. -#[cfg(test)] impl BufReader { + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] #[allow(missing_docs)] - pub fn initialized(&self) -> usize { + pub fn initialized(&self) -> bool { self.buf.initialized() } } @@ -317,6 +329,8 @@ impl BufReader { } } +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] impl SpecReadByte for BufReader where Self: Read, @@ -349,7 +363,7 @@ impl Read for BufReader { Ok(nread) } - fn read_buf(&mut self, mut cursor: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, mut cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { // If we don't have any buffered data and we're doing a massive read // (larger than our internal buffer), bypass our internal buffer // entirely. @@ -380,7 +394,7 @@ impl Read for BufReader { crate::io::default_read_exact(self, buf) } - fn read_buf_exact(&mut self, mut cursor: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf_exact(&mut self, mut cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { if self.buf.consume_with(cursor.capacity(), |claimed| cursor.append(claimed)) { return Ok(()); } @@ -410,7 +424,16 @@ impl Read for BufReader { fn read_to_end(&mut self, buf: &mut Vec) -> io::Result { let inner_buf = self.buffer(); buf.try_reserve(inner_buf.len())?; - buf.extend_from_slice(inner_buf); + + cfg_select! { + no_global_oom_handling => { + buf.try_extend_from_slice_of_bytes(inner_buf)?; + } + _ => { + buf.extend_from_slice(inner_buf); + } + } + let nread = inner_buf.len(); self.discard_buffer(); Ok(nread + self.inner.read_to_end(buf)?) @@ -442,7 +465,16 @@ impl Read for BufReader { let mut bytes = Vec::new(); self.read_to_end(&mut bytes)?; let string = crate::str::from_utf8(&bytes).map_err(|_| io::Error::INVALID_UTF8)?; - *buf += string; + + cfg_select! { + no_global_oom_handling => { + buf.try_push_str(string)?; + } + _ => { + buf.push_str(string); + } + } + Ok(string.len()) } } @@ -579,6 +611,8 @@ impl Seek for BufReader { } } +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] impl SizeHint for BufReader { #[inline] fn lower_bound(&self) -> usize { diff --git a/library/std/src/io/buffered/bufreader/buffer.rs b/library/alloc/src/io/buffered/bufreader/buffer.rs similarity index 64% rename from library/std/src/io/buffered/bufreader/buffer.rs rename to library/alloc/src/io/buffered/bufreader/buffer.rs index ad8608bf61908..316889d93f576 100644 --- a/library/std/src/io/buffered/bufreader/buffer.rs +++ b/library/alloc/src/io/buffered/bufreader/buffer.rs @@ -9,11 +9,13 @@ //! that user code which wants to do reads from a `BufReader` via `buffer` + `consume` can do so //! without encountering any runtime bounds checks. -use crate::cmp; +use core::cmp; +use core::mem::MaybeUninit; + +use crate::boxed::Box; use crate::io::{self, BorrowedBuf, ErrorKind, Read}; -use crate::mem::MaybeUninit; -pub struct Buffer { +pub(super) struct Buffer { // The buffer. buf: Box<[MaybeUninit]>, // The current seek offset into `buf`, must always be <= `filled`. @@ -21,25 +23,25 @@ pub struct Buffer { // Each call to `fill_buf` sets `filled` to indicate how many bytes at the start of `buf` are // initialized with bytes from a read. filled: usize, - // This is the max number of bytes returned across all `fill_buf` calls. We track this so that we - // can accurately tell `read_buf` how many bytes of buf are initialized, to bypass as much of its - // defensive initialization as possible. Note that while this often the same as `filled`, it - // doesn't need to be. Calls to `fill_buf` are not required to actually fill the buffer, and - // omitting this is a huge perf regression for `Read` impls that do not. - initialized: usize, + // Whether `buf` has been fully initialized. We track this so that we can accurately tell + // `read_buf` how many bytes of buf are initialized, to bypass as much of its defensive + // initialization as possible. Calls to `fill_buf` are not required to actually fill the buffer, + // and omitting this is a huge perf regression for `Read` impls that do not. + initialized: bool, } impl Buffer { + #[cfg(not(no_global_oom_handling))] #[inline] - pub fn with_capacity(capacity: usize) -> Self { + pub(super) fn with_capacity(capacity: usize) -> Self { let buf = Box::new_uninit_slice(capacity); - Self { buf, pos: 0, filled: 0, initialized: 0 } + Self { buf, pos: 0, filled: 0, initialized: false } } #[inline] - pub fn try_with_capacity(capacity: usize) -> io::Result { + pub(super) fn try_with_capacity(capacity: usize) -> io::Result { match Box::try_new_uninit_slice(capacity) { - Ok(buf) => Ok(Self { buf, pos: 0, filled: 0, initialized: 0 }), + Ok(buf) => Ok(Self { buf, pos: 0, filled: 0, initialized: false }), Err(_) => { Err(io::const_error!(ErrorKind::OutOfMemory, "failed to allocate read buffer")) } @@ -47,48 +49,47 @@ impl Buffer { } #[inline] - pub fn buffer(&self) -> &[u8] { + pub(super) fn buffer(&self) -> &[u8] { // SAFETY: self.pos and self.filled are valid, and self.filled >= self.pos, and // that region is initialized because those are all invariants of this type. unsafe { self.buf.get_unchecked(self.pos..self.filled).assume_init_ref() } } #[inline] - pub fn capacity(&self) -> usize { + pub(super) fn capacity(&self) -> usize { self.buf.len() } #[inline] - pub fn filled(&self) -> usize { + pub(super) fn filled(&self) -> usize { self.filled } #[inline] - pub fn pos(&self) -> usize { + pub(super) fn pos(&self) -> usize { self.pos } // This is only used by a test which asserts that the initialization-tracking is correct. - #[cfg(test)] - pub fn initialized(&self) -> usize { + pub(super) fn initialized(&self) -> bool { self.initialized } #[inline] - pub fn discard_buffer(&mut self) { + pub(super) fn discard_buffer(&mut self) { self.pos = 0; self.filled = 0; } #[inline] - pub fn consume(&mut self, amt: usize) { + pub(super) fn consume(&mut self, amt: usize) { self.pos = cmp::min(self.pos + amt, self.filled); } /// If there are `amt` bytes available in the buffer, pass a slice containing those bytes to /// `visitor` and return true. If there are not enough bytes available, return false. #[inline] - pub fn consume_with(&mut self, amt: usize, mut visitor: V) -> bool + pub(super) fn consume_with(&mut self, amt: usize, mut visitor: V) -> bool where V: FnMut(&[u8]), { @@ -103,32 +104,36 @@ impl Buffer { } #[inline] - pub fn unconsume(&mut self, amt: usize) { + pub(super) fn unconsume(&mut self, amt: usize) { self.pos = self.pos.saturating_sub(amt); } /// Read more bytes into the buffer without discarding any of its contents - pub fn read_more(&mut self, mut reader: impl Read) -> io::Result { + pub(super) fn read_more(&mut self, mut reader: impl Read) -> io::Result { let mut buf = BorrowedBuf::from(&mut self.buf[self.filled..]); - let old_init = self.initialized - self.filled; - unsafe { - buf.set_init(old_init); + + if self.initialized { + // SAFETY: `self.initialized` is only set after `self.buf` was + // fully initialized, and once `self.buf` is fully initialized + // no part will become uninitialized. + unsafe { buf.set_init() }; } + reader.read_buf(buf.unfilled())?; self.filled += buf.len(); - self.initialized += buf.init_len() - old_init; + self.initialized = buf.is_init(); Ok(buf.len()) } /// Remove bytes that have already been read from the buffer. - pub fn backshift(&mut self) { + pub(super) fn backshift(&mut self) { self.buf.copy_within(self.pos..self.filled, 0); self.filled -= self.pos; self.pos = 0; } #[inline] - pub fn fill_buf(&mut self, mut reader: impl Read) -> io::Result<&[u8]> { + pub(super) fn fill_buf(&mut self, mut reader: impl Read) -> io::Result<&[u8]> { // If we've reached the end of our internal buffer then we need to fetch // some more data from the reader. // Branch using `>=` instead of the more correct `==` @@ -137,16 +142,19 @@ impl Buffer { debug_assert!(self.pos == self.filled); let mut buf = BorrowedBuf::from(&mut *self.buf); - // SAFETY: `self.filled` bytes will always have been initialized. - unsafe { - buf.set_init(self.initialized); + + if self.initialized { + // SAFETY: `self.initialized` is only set after `self.buf` was + // fully initialized, and once `self.buf` is fully initialized + // no part will become uninitialized. + unsafe { buf.set_init() }; } let result = reader.read_buf(buf.unfilled()); self.pos = 0; self.filled = buf.len(); - self.initialized = buf.init_len(); + self.initialized = buf.is_init(); result?; } diff --git a/library/std/src/io/buffered/bufwriter.rs b/library/alloc/src/io/buffered/bufwriter.rs similarity index 91% rename from library/std/src/io/buffered/bufwriter.rs rename to library/alloc/src/io/buffered/bufwriter.rs index d569fed24c561..806e71c2772ae 100644 --- a/library/std/src/io/buffered/bufwriter.rs +++ b/library/alloc/src/io/buffered/bufwriter.rs @@ -1,8 +1,10 @@ +use core::mem::{self, ManuallyDrop}; +use core::{error, fmt, ptr}; + use crate::io::{ self, DEFAULT_BUF_SIZE, ErrorKind, IntoInnerError, IoSlice, Seek, SeekFrom, Write, }; -use crate::mem::{self, ManuallyDrop}; -use crate::{error, fmt, ptr}; +use crate::vec::Vec; /// Wraps a writer and buffers its output. /// @@ -60,8 +62,9 @@ use crate::{error, fmt, ptr}; /// together by the buffer and will all be written out in one system call when /// the `stream` is flushed. /// -/// [`TcpStream::write`]: crate::net::TcpStream::write -/// [`TcpStream`]: crate::net::TcpStream +// FIXME(#74481): Hard-links required to link from `alloc` to `std` +/// [`TcpStream::write`]: ../../std/net/struct.TcpStream.html#method.write +/// [`TcpStream`]: ../../std/net/struct.TcpStream.html /// [`flush`]: BufWriter::flush #[stable(feature = "rust1", since = "1.0.0")] pub struct BufWriter { @@ -87,21 +90,26 @@ impl BufWriter { /// use std::io::BufWriter; /// use std::net::TcpStream; /// + /// # #[expect(unused_mut)] /// let mut buffer = BufWriter::new(TcpStream::connect("127.0.0.1:34254").unwrap()); /// ``` + #[cfg(not(no_global_oom_handling))] #[stable(feature = "rust1", since = "1.0.0")] pub fn new(inner: W) -> BufWriter { BufWriter::with_capacity(DEFAULT_BUF_SIZE, inner) } - pub(crate) fn try_new_buffer() -> io::Result> { - Vec::try_with_capacity(DEFAULT_BUF_SIZE).map_err(|_| { + /// Attempts to allocate an internal buffer, _then_ calls the provided function + /// to retrieve the inner writer `W`. + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + #[inline] + pub fn try_new_with(f: impl FnOnce() -> io::Result) -> io::Result { + let buf = Vec::try_with_capacity(DEFAULT_BUF_SIZE).map_err(|_| { io::const_error!(ErrorKind::OutOfMemory, "failed to allocate write buffer") - }) - } - - pub(crate) fn with_buffer(inner: W, buf: Vec) -> Self { - Self { inner, buf, panicked: false } + })?; + let inner = f()?; + Ok(Self { inner, buf, panicked: false }) } /// Creates a new `BufWriter` with at least the specified buffer capacity. @@ -115,8 +123,10 @@ impl BufWriter { /// use std::net::TcpStream; /// /// let stream = TcpStream::connect("127.0.0.1:34254").unwrap(); + /// # #[expect(unused_mut)] /// let mut buffer = BufWriter::with_capacity(100, stream); /// ``` + #[cfg(not(no_global_oom_handling))] #[stable(feature = "rust1", since = "1.0.0")] pub fn with_capacity(capacity: usize, inner: W) -> BufWriter { BufWriter { inner, buf: Vec::with_capacity(capacity), panicked: false } @@ -136,6 +146,7 @@ impl BufWriter { /// use std::io::BufWriter; /// use std::net::TcpStream; /// + /// # #[expect(unused_mut)] /// let mut buffer = BufWriter::new(TcpStream::connect("127.0.0.1:34254").unwrap()); /// /// // unwrap the TcpStream and flush the buffer @@ -192,7 +203,13 @@ impl BufWriter { /// "successfully written" (by returning nonzero success values from /// `write`), any 0-length writes from `inner` must be reported as i/o /// errors from this method. - pub(in crate::io) fn flush_buf(&mut self) -> io::Result<()> { + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub fn flush_buf(&mut self) -> io::Result<()> { + // SAFETY: `::copy_from` assumes that + // this will not de-initialize any elements of `self.buf`'s spare + // capacity. + /// Helper struct to ensure the buffer is updated after all the writes /// are complete. It tracks the number of written bytes and drains them /// all from the front of the buffer when dropped. @@ -225,7 +242,16 @@ impl BufWriter { impl Drop for BufGuard<'_> { fn drop(&mut self) { if self.written > 0 { - self.buffer.drain(..self.written); + // Like `self.buffer.drain(..self.written)` but more obviously + // preserving the spare capacity; see note above. + let new_len = self.buffer.len() - self.written; + // SAFETY: Assumes `Vec::as_mut_slice` will not + // de-initialize any elements of `self.buf`'s spare capacity, + // and that `<&mut [u8]>::copy_within` will not do so either. + self.buffer.as_mut_slice().copy_within(self.written.., 0); + // SAFETY: Assumes `Vec::truncate` will not de-initialize + // any elements of `self.buf`'s spare capacity, + self.buffer.truncate(new_len); } } } @@ -274,6 +300,7 @@ impl BufWriter { /// use std::io::BufWriter; /// use std::net::TcpStream; /// + /// # #[expect(unused_mut)] /// let mut buffer = BufWriter::new(TcpStream::connect("127.0.0.1:34254").unwrap()); /// /// // we can use reference just like buffer @@ -330,7 +357,9 @@ impl BufWriter { /// That the buffer is a `Vec` is an implementation detail. /// Callers should not modify the capacity as there currently is no public API to do so /// and thus any capacity changes would be unexpected by the user. - pub(in crate::io) fn buffer_mut(&mut self) -> &mut Vec { + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub fn buffer_mut(&mut self) -> &mut Vec { &mut self.buf } @@ -461,6 +490,10 @@ impl BufWriter { /// # Example /// /// ``` +/// # // This test requires unwinding to work. +/// # // Disable it when unwinding isn't available. +/// # #[cfg(panic = "unwind")] +/// # fn main() { /// use std::io::{self, BufWriter, Write}; /// use std::panic::{catch_unwind, AssertUnwindSafe}; /// @@ -479,6 +512,9 @@ impl BufWriter { /// let (recovered_writer, buffered_data) = stream.into_parts(); /// assert!(matches!(recovered_writer, PanickingWriter)); /// assert_eq!(buffered_data.unwrap_err().into_inner(), b"some data"); +/// # } +/// # #[cfg(not(panic = "unwind"))] +/// # fn main() {} /// ``` pub struct WriterPanicked { buf: Vec, @@ -641,7 +677,8 @@ impl Write for BufWriter { } fn flush(&mut self) -> io::Result<()> { - self.flush_buf().and_then(|()| self.get_mut().flush()) + self.flush_buf()?; + self.get_mut().flush() } } diff --git a/library/std/src/io/buffered/linewriter.rs b/library/alloc/src/io/buffered/linewriter.rs similarity index 98% rename from library/std/src/io/buffered/linewriter.rs rename to library/alloc/src/io/buffered/linewriter.rs index cc6921b86dd0b..bdb979e931f2e 100644 --- a/library/std/src/io/buffered/linewriter.rs +++ b/library/alloc/src/io/buffered/linewriter.rs @@ -84,6 +84,7 @@ impl LineWriter { /// Ok(()) /// } /// ``` + #[cfg(not(no_global_oom_handling))] #[stable(feature = "rust1", since = "1.0.0")] pub fn new(inner: W) -> LineWriter { // Lines typically aren't that long, don't use a giant buffer @@ -105,6 +106,7 @@ impl LineWriter { /// Ok(()) /// } /// ``` + #[cfg(not(no_global_oom_handling))] #[stable(feature = "rust1", since = "1.0.0")] pub fn with_capacity(capacity: usize, inner: W) -> LineWriter { LineWriter { inner: BufWriter::with_capacity(capacity, inner) } diff --git a/library/std/src/io/buffered/linewritershim.rs b/library/alloc/src/io/buffered/linewritershim.rs similarity index 81% rename from library/std/src/io/buffered/linewritershim.rs rename to library/alloc/src/io/buffered/linewritershim.rs index 967e24812b9ff..35f448fc3aa8a 100644 --- a/library/std/src/io/buffered/linewritershim.rs +++ b/library/alloc/src/io/buffered/linewritershim.rs @@ -13,12 +13,12 @@ use crate::io::{self, BufWriter, IoSlice, Write}; /// `BufWriters` to be temporarily given line-buffering logic; this is what /// enables Stdout to be alternately in line-buffered or block-buffered mode. #[derive(Debug)] -pub struct LineWriterShim<'a, W: ?Sized + Write> { +pub(super) struct LineWriterShim<'a, W: ?Sized + Write> { buffer: &'a mut BufWriter, } impl<'a, W: ?Sized + Write> LineWriterShim<'a, W> { - pub fn new(buffer: &'a mut BufWriter) -> Self { + pub(super) fn new(buffer: &'a mut BufWriter) -> Self { Self { buffer } } @@ -40,15 +40,88 @@ impl<'a, W: ?Sized + Write> LineWriterShim<'a, W> { self.buffer.buffer() } - /// Flushes the buffer iff the last byte is a newline (indicating that an - /// earlier write only succeeded partially, and we want to retry flushing - /// the buffered line before continuing with a subsequent write). + /// Flushes the buffer if and only if the last byte is a newline + /// (indicating that an earlier write only succeeded partially, and we + /// want to retry flushing the buffered line before continuing with a + /// subsequent write). fn flush_if_completed_line(&mut self) -> io::Result<()> { match self.buffered().last().copied() { Some(b'\n') => self.buffer.flush_buf(), _ => Ok(()), } } + + /// Vectored line-buffered write over an already-capped list of buffers. + /// + /// The caller is responsible for trimming `bufs` to the prefix it is + /// willing to scan (see `MAX_BUFS_TO_SCAN`). This method only ever writes + /// or buffers bytes from `bufs`, so any newline it might bury in the + /// `BufWriter` is one it has itself scanned for -- buffers the caller + /// dropped past the cap can never end up stuck in the buffer. Bytes not + /// accounted for in the return value are left for the next call. + fn write_vectored_scanned(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { + // Find the buffer containing the last newline. + let last_newline_buf_idx = bufs + .iter() + .enumerate() + .rev() + .find_map(|(i, buf)| memchr::memchr(b'\n', buf).map(|_| i)); + + // If there are no new newlines (that is, if this write is less than + // one line), just do a regular buffered write. + let last_newline_buf_idx = match last_newline_buf_idx { + None => { + self.flush_if_completed_line()?; + return self.buffer.write_vectored(bufs); + } + Some(i) => i, + }; + + // Flush existing content to prepare for our write. + self.buffer.flush_buf()?; + + // This is what we're going to try to write directly to the inner + // writer. The rest will be buffered, if nothing goes wrong. + let (lines, tail) = bufs.split_at(last_newline_buf_idx + 1); + + // Write `lines` directly to the inner writer. In keeping with the + // `write` convention, make at most one attempt to add new (unbuffered) + // data. Because this write doesn't touch the BufWriter state directly, + // and the buffer is known to be empty, we don't need to worry about + // self.panicked here. + let flushed = self.inner_mut().write_vectored(lines)?; + + // If inner returns Ok(0), propagate that to the caller without + // doing additional buffering; otherwise we're just guaranteeing + // an "ErrorKind::WriteZero" later. + if flushed == 0 { + return Ok(0); + } + + // Don't try to reconstruct the exact amount written; just bail + // in the event of a partial write. + let mut lines_len: usize = 0; + for buf in lines { + // With overlapping/duplicate slices the total length may in theory + // exceed usize::MAX + lines_len = lines_len.saturating_add(buf.len()); + if flushed < lines_len { + return Ok(flushed); + } + } + + // Now that the write has succeeded, buffer the rest (or as much of the + // rest as possible). `tail` is the part of the scanned prefix after the + // last newline, so it cannot contain a newline of its own. + let buffered: usize = tail + .iter() + .filter(|buf| !buf.is_empty()) + .map(|buf| self.buffer.write_to_buf(buf)) + .take_while(|&n| n > 0) + .sum(); + + Ok(flushed + buffered) + } } impl<'a, W: ?Sized + Write> Write for LineWriterShim<'a, W> { @@ -185,71 +258,26 @@ impl<'a, W: ?Sized + Write> Write for LineWriterShim<'a, W> { }; } - // Find the buffer containing the last newline - // FIXME: This is overly slow if there are very many bufs and none contain - // newlines. e.g. writev() on Linux only writes up to 1024 slices, so - // scanning the rest is wasted effort. This makes write_all_vectored() - // quadratic. - let last_newline_buf_idx = bufs - .iter() - .enumerate() - .rev() - .find_map(|(i, buf)| memchr::memchr(b'\n', buf).map(|_| i)); - - // If there are no new newlines (that is, if this write is less than - // one line), just do a regular buffered write - let last_newline_buf_idx = match last_newline_buf_idx { - // No newlines; just do a normal buffered write - None => { - self.flush_if_completed_line()?; - return self.buffer.write_vectored(bufs); - } - Some(i) => i, - }; - - // Flush existing content to prepare for our write - self.buffer.flush_buf()?; - - // This is what we're going to try to write directly to the inner - // writer. The rest will be buffered, if nothing goes wrong. - let (lines, tail) = bufs.split_at(last_newline_buf_idx + 1); - - // Write `lines` directly to the inner writer. In keeping with the - // `write` convention, make at most one attempt to add new (unbuffered) - // data. Because this write doesn't touch the BufWriter state directly, - // and the buffer is known to be empty, we don't need to worry about - // self.panicked here. - let flushed = self.inner_mut().write_vectored(lines)?; - - // If inner returns Ok(0), propagate that to the caller without - // doing additional buffering; otherwise we're just guaranteeing - // an "ErrorKind::WriteZero" later. - if flushed == 0 { - return Ok(0); - } - - // Don't try to reconstruct the exact amount written; just bail - // in the event of a partial write - let mut lines_len: usize = 0; - for buf in lines { - // With overlapping/duplicate slices the total length may in theory - // exceed usize::MAX - lines_len = lines_len.saturating_add(buf.len()); - if flushed < lines_len { - return Ok(flushed); - } - } - - // Now that the write has succeeded, buffer the rest (or as much of the - // rest as possible) - let buffered: usize = tail - .iter() - .filter(|buf| !buf.is_empty()) - .map(|buf| self.buffer.write_to_buf(buf)) - .take_while(|&n| n > 0) - .sum(); - - Ok(flushed + buffered) + // Only scan (and operate on) the first MAX_BUFS_TO_SCAN slices. The cap + // is what keeps write_all_vectored() from going quadratic when callers + // pass many newline-free slices -- without it, every iteration of the + // outer loop rescans every remaining buffer. 1024 is a portable, + // generous upper bound: it is the value of UIO_MAXIOV / IOV_MAX on + // Linux and the BSDs (and the hardcoded cap in + // sys::net::connection::socket::solid), so on those platforms it also + // lines up with the most a single writev() can retire. On platforms + // whose syscall cap is smaller (POSIX requires only 16) or that have no + // cap at all (Windows), the constant still serves its primary purpose + // of bounding scan work. + // + // Everything past the cap is left untouched for the next call; the + // outer loop in write_all_vectored() makes forward progress via the + // short return value, and correctness is preserved everywhere. We hand + // the capped prefix to a helper so the rest of the logic can only ever + // see -- and therefore only ever write or buffer -- buffers we have + // actually scanned for newlines. + const MAX_BUFS_TO_SCAN: usize = 1024; + self.write_vectored_scanned(&bufs[..bufs.len().min(MAX_BUFS_TO_SCAN)]) } fn is_write_vectored(&self) -> bool { diff --git a/library/std/src/io/buffered/mod.rs b/library/alloc/src/io/buffered/mod.rs similarity index 96% rename from library/std/src/io/buffered/mod.rs rename to library/alloc/src/io/buffered/mod.rs index e36f2d92108d0..795a918b88533 100644 --- a/library/std/src/io/buffered/mod.rs +++ b/library/alloc/src/io/buffered/mod.rs @@ -5,17 +5,14 @@ mod bufwriter; mod linewriter; mod linewritershim; -#[cfg(test)] -mod tests; +use core::{error, fmt}; #[stable(feature = "bufwriter_into_parts", since = "1.56.0")] -pub use bufwriter::WriterPanicked; -use linewritershim::LineWriterShim; - +pub use self::bufwriter::WriterPanicked; +use self::linewritershim::LineWriterShim; #[stable(feature = "rust1", since = "1.0.0")] pub use self::{bufreader::BufReader, bufwriter::BufWriter, linewriter::LineWriter}; use crate::io::Error; -use crate::{error, fmt}; /// An error returned by [`BufWriter::into_inner`] which combines an error that /// happened while writing out the buffer, and the buffered writer object @@ -27,6 +24,7 @@ use crate::{error, fmt}; /// use std::io::BufWriter; /// use std::net::TcpStream; /// +/// # #[expect(unused_mut)] /// let mut stream = BufWriter::new(TcpStream::connect("127.0.0.1:34254").unwrap()); /// /// // do stuff with the stream @@ -69,6 +67,7 @@ impl IntoInnerError { /// use std::io::BufWriter; /// use std::net::TcpStream; /// + /// # #[expect(unused_mut)] /// let mut stream = BufWriter::new(TcpStream::connect("127.0.0.1:34254").unwrap()); /// /// // do stuff with the stream @@ -103,6 +102,7 @@ impl IntoInnerError { /// use std::io::BufWriter; /// use std::net::TcpStream; /// + /// # #[expect(unused_mut)] /// let mut stream = BufWriter::new(TcpStream::connect("127.0.0.1:34254").unwrap()); /// /// // do stuff with the stream @@ -132,6 +132,7 @@ impl IntoInnerError { /// obtain ownership of the underlying error. /// /// # Example + /// /// ``` /// use std::io::{BufWriter, ErrorKind, Write}; /// @@ -154,6 +155,7 @@ impl IntoInnerError { /// advanced error recovery. /// /// # Example + /// /// ``` /// use std::io::{BufWriter, ErrorKind, Write}; /// diff --git a/library/alloc/src/io/copy.rs b/library/alloc/src/io/copy.rs new file mode 100644 index 0000000000000..798bd2c1ec0a0 --- /dev/null +++ b/library/alloc/src/io/copy.rs @@ -0,0 +1,90 @@ +mod generic; +mod specialization; + +use self::generic::generic_copy; +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +pub use self::specialization::SpecCopy; +use self::specialization::SpecCopyInner; +use crate::io::{Read, Result, Write}; + +/// Used as a part of [copy specialization](SpecCopy) to communicate how many bytes +/// were copied, and whether copying is done. +/// +/// * [`Ended(n)`](CopyState::Ended) indicates copying completed, moving a total +/// of `n` bytes. +/// * [`Fallback(n)`](CopyState::Fallback) indicates copying is _might_ not be +/// complete, and so far `n` bytes have been copied using specialization. +/// The remaining must be copied using a fallback implementation. +/// +/// If a particular `Read` and `Write` combination do not implement a specialized +/// copy routine, the specialized function will return `Fallback(0)`. +#[derive(Debug)] +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +pub enum CopyState { + Ended(u64), + Fallback(u64), +} + +/// Copies the entire contents of a reader into a writer. +/// +/// This function will continuously read data from `reader` and then +/// write it into `writer` in a streaming fashion until `reader` +/// returns EOF. +/// +/// On success, the total number of bytes that were copied from +/// `reader` to `writer` is returned. +/// +/// If you want to copy the contents of one file to another and you’re +/// working with filesystem paths, see the [`fs::copy`] function. +/// +// FIXME(#74481): Hard-links required to link from `alloc` to `std` +/// [`fs::copy`]: ../../std/fs/fn.copy.html +/// +/// # Errors +/// +/// This function will return an error immediately if any call to [`read`] or +/// [`write`] returns an error. All instances of [`ErrorKind::Interrupted`] are +/// handled by this function and the underlying operation is retried. +/// +/// [`read`]: Read::read +/// [`write`]: Write::write +/// [`ErrorKind::Interrupted`]: crate::io::ErrorKind::Interrupted +/// +/// # Examples +/// +/// ``` +/// use std::io; +/// +/// fn main() -> io::Result<()> { +/// let mut reader: &[u8] = b"hello"; +/// let mut writer: Vec = vec![]; +/// +/// io::copy(&mut reader, &mut writer)?; +/// +/// assert_eq!(&b"hello"[..], &writer[..]); +/// Ok(()) +/// } +/// ``` +/// +/// # Platform-specific behavior +/// +/// On Linux (including Android), this function uses `copy_file_range(2)`, +/// `sendfile(2)` or `splice(2)` syscalls to move data directly between file +/// descriptors if possible. +/// +/// Note that platform-specific behavior may change in the future. +#[stable(feature = "rust1", since = "1.0.0")] +pub fn copy(reader: &mut R, writer: &mut W) -> Result +where + R: Read, + W: Write, +{ + match SpecCopyInner::copy(reader, writer)? { + CopyState::Ended(copied) => Ok(copied), + CopyState::Fallback(copied) => { + generic_copy(reader, writer).map(|additional| copied + additional) + } + } +} diff --git a/library/std/src/io/copy.rs b/library/alloc/src/io/copy/generic.rs similarity index 56% rename from library/std/src/io/copy.rs rename to library/alloc/src/io/copy/generic.rs index 2b558efb8885e..692b77fba730e 100644 --- a/library/std/src/io/copy.rs +++ b/library/alloc/src/io/copy/generic.rs @@ -1,99 +1,57 @@ -use super::{BorrowedBuf, BufReader, BufWriter, DEFAULT_BUF_SIZE, Read, Result, Write}; -use crate::alloc::Allocator; -use crate::cmp; -use crate::collections::VecDeque; -use crate::io::IoSlice; -use crate::mem::MaybeUninit; -use crate::sys::io::{CopyState, kernel_copy}; +use core::mem::MaybeUninit; -#[cfg(test)] -mod tests; +#[cfg(not(no_global_oom_handling))] +use crate::collections::VecDeque; +use crate::io::{BorrowedBuf, BufReader, BufWriter, DEFAULT_BUF_SIZE, Read, Result, Write}; +use crate::vec::Vec; +#[cfg_attr( + no_global_oom_handling, + expect(unused_imports, reason = "only required for VecDeque specialization") +)] +use crate::{alloc::Allocator, io::IoSlice}; -/// Copies the entire contents of a reader into a writer. -/// -/// This function will continuously read data from `reader` and then -/// write it into `writer` in a streaming fashion until `reader` -/// returns EOF. -/// -/// On success, the total number of bytes that were copied from -/// `reader` to `writer` is returned. -/// -/// If you want to copy the contents of one file to another and you’re -/// working with filesystem paths, see the [`fs::copy`] function. -/// -/// [`fs::copy`]: crate::fs::copy -/// -/// # Errors -/// -/// This function will return an error immediately if any call to [`read`] or -/// [`write`] returns an error. All instances of [`ErrorKind::Interrupted`] are -/// handled by this function and the underlying operation is retried. -/// -/// [`read`]: Read::read -/// [`write`]: Write::write -/// [`ErrorKind::Interrupted`]: crate::io::ErrorKind::Interrupted -/// -/// # Examples -/// -/// ``` -/// use std::io; -/// -/// fn main() -> io::Result<()> { -/// let mut reader: &[u8] = b"hello"; -/// let mut writer: Vec = vec![]; -/// -/// io::copy(&mut reader, &mut writer)?; -/// -/// assert_eq!(&b"hello"[..], &writer[..]); -/// Ok(()) -/// } -/// ``` -/// -/// # Platform-specific behavior +/// The userspace read-write-loop implementation of `io::copy` that is used when +/// OS-specific specializations for copy offloading are not available or not applicable. /// -/// On Linux (including Android), this function uses `copy_file_range(2)`, -/// `sendfile(2)` or `splice(2)` syscalls to move data directly between file -/// descriptors if possible. +/// This function is able to perform a mild amount of specialization based on +/// the size of the `reader` and `writer` buffers, if they have any. /// -/// Note that platform-specific behavior [may change in the future][changes]. +/// * If `reader`'s buffer is large enough ([`>=DEFAULT_BUF_SIZE`](DEFAULT_BUF_SIZE)), +/// _and_ it is larger than `writer`'s buffer, copying will be controlled by `R`. +/// * Otherwise, copying will be controlled by `writer`. /// -/// [changes]: crate::io#platform-specific-behavior -#[stable(feature = "rust1", since = "1.0.0")] -pub fn copy(reader: &mut R, writer: &mut W) -> Result +/// Currently, `[u8]`, `Vec`, `VecDeque`, `BufReader` and `BufWriter` +/// are specialized with. +pub(super) fn generic_copy(reader: &mut R, writer: &mut W) -> Result where R: Read, W: Write, { - match kernel_copy(reader, writer)? { - CopyState::Ended(copied) => Ok(copied), - CopyState::Fallback(copied) => { - generic_copy(reader, writer).map(|additional| copied + additional) - } - } -} + let read_priority = BufferedReaderSpec::buffer_priority(reader); + let write_priority = BufferedWriterSpec::buffer_priority(writer); -/// The userspace read-write-loop implementation of `io::copy` that is used when -/// OS-specific specializations for copy offloading are not available or not applicable. -fn generic_copy(reader: &mut R, writer: &mut W) -> Result -where - R: Read, - W: Write, -{ - let read_buf = BufferedReaderSpec::buffer_size(reader); - let write_buf = BufferedWriterSpec::buffer_size(writer); - - if read_buf >= DEFAULT_BUF_SIZE && read_buf >= write_buf { + if read_priority >= DEFAULT_BUF_SIZE && read_priority >= write_priority { return BufferedReaderSpec::copy_to(reader, writer); } BufferedWriterSpec::copy_from(writer, reader) } -/// Specialization of the read-write loop that reuses the internal -/// buffer of a BufReader. If there's no buffer then the writer side +/// This is used by [`generic_copy`] to decide whether to use [`BufferedReaderSpec::copy_to`] +/// or [`BufferedWriterSpec::copy_from`]. +type BufferPriority = usize; + +/// Unbuffered readers and writers have the lowest priority. +const UNBUFFERED: BufferPriority = BufferPriority::MIN; + +/// Readers and writers with their entire contents have the highest priority. +const IN_MEMORY: BufferPriority = BufferPriority::MAX; + +/// Specialization of the read-write loop in [`generic_copy`] that reuses the +/// internal buffer of a [`BufReader`]. If there's no buffer then the writer side /// should be used instead. trait BufferedReaderSpec { - fn buffer_size(&self) -> usize; + fn buffer_priority(&self) -> BufferPriority; fn copy_to(&mut self, to: &mut (impl Write + ?Sized)) -> Result; } @@ -104,8 +62,8 @@ where T: ?Sized, { #[inline] - default fn buffer_size(&self) -> usize { - 0 + default fn buffer_priority(&self) -> BufferPriority { + UNBUFFERED } default fn copy_to(&mut self, _to: &mut (impl Write + ?Sized)) -> Result { @@ -114,10 +72,8 @@ where } impl BufferedReaderSpec for &[u8] { - fn buffer_size(&self) -> usize { - // prefer this specialization since the source "buffer" is all we'll ever need, - // even if it's small - usize::MAX + fn buffer_priority(&self) -> BufferPriority { + IN_MEMORY } fn copy_to(&mut self, to: &mut (impl Write + ?Sized)) -> Result { @@ -128,11 +84,10 @@ impl BufferedReaderSpec for &[u8] { } } +#[cfg(not(no_global_oom_handling))] impl BufferedReaderSpec for VecDeque { - fn buffer_size(&self) -> usize { - // prefer this specialization since the source "buffer" is all we'll ever need, - // even if it's small - usize::MAX + fn buffer_priority(&self) -> BufferPriority { + IN_MEMORY } fn copy_to(&mut self, to: &mut (impl Write + ?Sized)) -> Result { @@ -150,7 +105,7 @@ where Self: Read, I: ?Sized, { - fn buffer_size(&self) -> usize { + fn buffer_priority(&self) -> BufferPriority { self.capacity() } @@ -168,7 +123,7 @@ where Err(e) => return Err(e), } let buf = self.buffer(); - if self.buffer().len() == 0 { + if self.buffer().is_empty() { return Ok(len); } @@ -184,45 +139,50 @@ where } } -/// Specialization of the read-write loop that either uses a stack buffer -/// or reuses the internal buffer of a BufWriter +/// Specialization of the read-write loop in `generic_copy` that either uses a +/// stack buffer or reuses the internal buffer of a [`BufWriter`]. trait BufferedWriterSpec: Write { - fn buffer_size(&self) -> usize; + fn buffer_priority(&self) -> BufferPriority; fn copy_from(&mut self, reader: &mut R) -> Result; } impl BufferedWriterSpec for W { #[inline] - default fn buffer_size(&self) -> usize { - 0 + default fn buffer_priority(&self) -> BufferPriority { + UNBUFFERED } default fn copy_from(&mut self, reader: &mut R) -> Result { + // Unlike `BufferedReaderSpec::copy_to`, this _will_ be called as the fallback + // when both the reader and writer provide no specialization. stack_buffer_copy(reader, self) } } impl BufferedWriterSpec for BufWriter { - fn buffer_size(&self) -> usize { + fn buffer_priority(&self) -> BufferPriority { self.capacity() } fn copy_from(&mut self, reader: &mut R) -> Result { if self.capacity() < DEFAULT_BUF_SIZE { + // Since neither this buffer nor the reader's buffer are large enough, + // fall back to the unspecialized implementation. return stack_buffer_copy(reader, self); } let mut len = 0; - let mut init = 0; + let mut init = false; loop { let buf = self.buffer_mut(); - let mut read_buf: BorrowedBuf<'_> = buf.spare_capacity_mut().into(); + let mut read_buf: BorrowedBuf<'_, u8> = buf.spare_capacity_mut().into(); - unsafe { - // SAFETY: init is either 0 or the init_len from the previous iteration. - read_buf.set_init(init); + if init { + // SAFETY: `init` is only true after `reader` initializes + // `read_buf`. See the comment about `flush_buf` below. + unsafe { read_buf.set_init() }; } if read_buf.capacity() >= DEFAULT_BUF_SIZE { @@ -235,7 +195,7 @@ impl BufferedWriterSpec for BufWriter { return Ok(len); } - init = read_buf.init_len() - bytes_read; + init = read_buf.is_init(); len += bytes_read as u64; // SAFETY: BorrowedBuf guarantees all of its filled bytes are init @@ -248,10 +208,8 @@ impl BufferedWriterSpec for BufWriter { Err(e) => return Err(e), } } else { - // All the bytes that were already in the buffer are initialized, - // treat them as such when the buffer is flushed. - init += buf.len(); - + // SAFETY: `flush_buf` will not de-initialize any elements of + // the spare capacity so we can remember `init` across this. self.flush_buf()?; } } @@ -259,8 +217,8 @@ impl BufferedWriterSpec for BufWriter { } impl BufferedWriterSpec for Vec { - fn buffer_size(&self) -> usize { - cmp::max(DEFAULT_BUF_SIZE, self.capacity() - self.len()) + fn buffer_priority(&self) -> BufferPriority { + self.capacity() - self.len() } fn copy_from(&mut self, reader: &mut R) -> Result { @@ -268,12 +226,13 @@ impl BufferedWriterSpec for Vec { } } +/// Copies from `reader` to `writer` using a stack-allocated buffer (a fixed sized array). fn stack_buffer_copy( reader: &mut R, writer: &mut W, ) -> Result { let buf: &mut [_] = &mut [MaybeUninit::uninit(); DEFAULT_BUF_SIZE]; - let mut buf: BorrowedBuf<'_> = buf.into(); + let mut buf: BorrowedBuf<'_, u8> = buf.into(); let mut len = 0; diff --git a/library/alloc/src/io/copy/specialization.rs b/library/alloc/src/io/copy/specialization.rs new file mode 100644 index 0000000000000..738f3af6beaae --- /dev/null +++ b/library/alloc/src/io/copy/specialization.rs @@ -0,0 +1,74 @@ +//! Provides specialization for `io::copy`. + +use super::CopyState; +use crate::io::{BufReader, Read, Result, Take, Write}; + +pub(super) trait SpecCopyInner { + /// The implementation of `io::copy` that can rely on platform specific specialization + /// provided by `libstd`. + fn copy(&mut self, writer: &mut W) -> Result; +} + +impl SpecCopyInner for R { + default fn copy(&mut self, _writer: &mut W) -> Result { + Ok(CopyState::Fallback(0)) + } +} + +impl SpecCopyInner for R { + fn copy(&mut self, writer: &mut W) -> Result { + ::copy(self, writer) + } +} + +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +#[rustc_specialization_trait] +pub trait SpecCopy: Read { + /// Attempt to copy from this reader to the provided writer using a specialized + /// process. + /// + /// Note that this function does _not_ take `self` as a parameter, and instead + /// is passed a generic `Read` type `R`. + /// This allows the `Self` type to provide specialized implementations for + /// any combination of `Read` and `Write` types. + /// However, in practice `Self` and types wrapping `Self` will be passed as + /// the `reader` argument. + /// + /// As of time of writing, `&mut R`, `Take`, and `BufReader` will + /// forward to `R` for a specialized copy implementation. + fn copy( + _reader: &mut R, + _writer: &mut W, + ) -> Result; +} + +impl SpecCopy for &mut T +where + T: SpecCopy, +{ + fn copy( + reader: &mut R, + writer: &mut W, + ) -> Result { + ::copy(reader, writer) + } +} + +impl SpecCopy for Take { + fn copy( + reader: &mut R, + writer: &mut W, + ) -> Result { + ::copy(reader, writer) + } +} + +impl SpecCopy for BufReader { + fn copy( + reader: &mut R, + writer: &mut W, + ) -> Result { + ::copy(reader, writer) + } +} diff --git a/library/alloc/src/io/cursor.rs b/library/alloc/src/io/cursor.rs new file mode 100644 index 0000000000000..4bd5a59e54fad --- /dev/null +++ b/library/alloc/src/io/cursor.rs @@ -0,0 +1,371 @@ +use crate::alloc::Allocator; +use crate::boxed::Box; +use crate::io::{ + self, BorrowedCursor, BufRead, Cursor, ErrorKind, IoSlice, IoSliceMut, Read, + WriteThroughCursor, slice_write, slice_write_all, slice_write_all_vectored, + slice_write_vectored, +}; +use crate::string::String; +use crate::vec::Vec; + +#[stable(feature = "rust1", since = "1.0.0")] +impl Read for Cursor +where + T: AsRef<[u8]>, +{ + fn read(&mut self, buf: &mut [u8]) -> io::Result { + let n = Read::read(&mut Cursor::split(self).1, buf)?; + self.set_position(self.position() + n as u64); + Ok(n) + } + + fn read_buf(&mut self, mut cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { + let prev_written = cursor.written(); + + Read::read_buf(&mut Cursor::split(self).1, cursor.reborrow())?; + + self.set_position(self.position() + (cursor.written() - prev_written) as u64); + + Ok(()) + } + + fn read_vectored(&mut self, bufs: &mut [IoSliceMut<'_>]) -> io::Result { + let mut nread = 0; + for buf in bufs { + let n = self.read(buf)?; + nread += n; + if n < buf.len() { + break; + } + } + Ok(nread) + } + + fn is_read_vectored(&self) -> bool { + true + } + + fn read_exact(&mut self, buf: &mut [u8]) -> io::Result<()> { + let result = Read::read_exact(&mut Cursor::split(self).1, buf); + + match result { + Ok(_) => self.set_position(self.position() + buf.len() as u64), + // The only possible error condition is EOF, so place the cursor at "EOF" + Err(_) => self.set_position(self.get_ref().as_ref().len() as u64), + } + + result + } + + fn read_buf_exact(&mut self, mut cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { + let prev_written = cursor.written(); + + let result = Read::read_buf_exact(&mut Cursor::split(self).1, cursor.reborrow()); + self.set_position(self.position() + (cursor.written() - prev_written) as u64); + + result + } + + fn read_to_end(&mut self, buf: &mut Vec) -> io::Result { + let content = Cursor::split(self).1; + let len = content.len(); + buf.try_reserve(len)?; + cfg_select! { + no_global_oom_handling => { + buf.try_extend_from_slice_of_bytes(content)?; + } + _ => { + buf.extend_from_slice(content); + } + } + self.set_position(self.position() + len as u64); + + Ok(len) + } + + fn read_to_string(&mut self, buf: &mut String) -> io::Result { + let content = + crate::str::from_utf8(Cursor::split(self).1).map_err(|_| io::Error::INVALID_UTF8)?; + let len = content.len(); + buf.try_reserve(len)?; + + cfg_select! { + no_global_oom_handling => { + buf.try_push_str(content)?; + } + _ => { + buf.push_str(content); + } + } + + self.set_position(self.position() + len as u64); + + Ok(len) + } +} + +#[stable(feature = "rust1", since = "1.0.0")] +impl BufRead for Cursor +where + T: AsRef<[u8]>, +{ + fn fill_buf(&mut self) -> io::Result<&[u8]> { + Ok(Cursor::split(self).1) + } + fn consume(&mut self, amt: usize) { + self.set_position(self.position() + amt as u64); + } +} + +/// Reserves the required space, and pads the vec with 0s if necessary. +fn reserve_and_pad( + pos_mut: &mut u64, + vec: &mut Vec, + buf_len: usize, +) -> io::Result { + let pos: usize = (*pos_mut).try_into().map_err(|_| { + io::const_error!( + ErrorKind::InvalidInput, + "cursor position exceeds maximum possible vector length", + ) + })?; + + // For safety reasons, we don't want these numbers to overflow + // otherwise our allocation won't be enough + let desired_cap = pos.saturating_add(buf_len); + if desired_cap > vec.capacity() { + // We want our vec's total capacity + // to have room for (pos+buf_len) bytes. Reserve allocates + // based on additional elements from the length, so we need to + // reserve the difference + cfg_select! { + no_global_oom_handling => { + vec.try_reserve(desired_cap - vec.len())?; + } + _ => { + vec.reserve(desired_cap - vec.len()); + } + } + } + // Pad if pos is above the current len. + if pos > vec.len() { + let diff = pos - vec.len(); + // Unfortunately, `resize()` would suffice but the optimiser does not + // realise the `reserve` it does can be eliminated. So we do it manually + // to eliminate that extra branch + let spare = vec.spare_capacity_mut(); + debug_assert!(spare.len() >= diff); + // Safety: we have allocated enough capacity for this. + // And we are only writing, not reading + unsafe { + spare.get_unchecked_mut(..diff).fill(core::mem::MaybeUninit::new(0)); + vec.set_len(pos); + } + } + + Ok(pos) +} + +/// Writes the slice to the vec without allocating. +/// +/// # Safety +/// +/// `vec` must have `buf.len()` spare capacity. +unsafe fn vec_write_all_unchecked(pos: usize, vec: &mut Vec, buf: &[u8]) -> usize +where + A: Allocator, +{ + debug_assert!(vec.capacity() >= pos + buf.len()); + unsafe { vec.as_mut_ptr().add(pos).copy_from(buf.as_ptr(), buf.len()) }; + pos + buf.len() +} + +/// Resizing `write_all` implementation for [`Cursor`]. +/// +/// Cursor is allowed to have a pre-allocated and initialised +/// vector body, but with a position of 0. This means the [`Write`] +/// will overwrite the contents of the vec. +/// +/// This also allows for the vec body to be empty, but with a position of N. +/// This means that [`Write`] will pad the vec with 0 initially, +/// before writing anything from that point +/// +/// [`Write`]: crate::io::Write +fn vec_write_all(pos_mut: &mut u64, vec: &mut Vec, buf: &[u8]) -> io::Result +where + A: Allocator, +{ + let buf_len = buf.len(); + let mut pos = reserve_and_pad(pos_mut, vec, buf_len)?; + + // Write the buf then progress the vec forward if necessary + // Safety: we have ensured that the capacity is available + // and that all bytes get written up to pos + unsafe { + pos = vec_write_all_unchecked(pos, vec, buf); + if pos > vec.len() { + vec.set_len(pos); + } + }; + + // Bump us forward + *pos_mut += buf_len as u64; + Ok(buf_len) +} + +/// Resizing `write_all_vectored` implementation for [`Cursor`]. +/// +/// Cursor is allowed to have a pre-allocated and initialised +/// vector body, but with a position of 0. This means the [`Write`] +/// will overwrite the contents of the vec. +/// +/// This also allows for the vec body to be empty, but with a position of N. +/// This means that [`Write`] will pad the vec with 0 initially, +/// before writing anything from that point +/// +/// [`Write`]: crate::io::Write +fn vec_write_all_vectored( + pos_mut: &mut u64, + vec: &mut Vec, + bufs: &[IoSlice<'_>], +) -> io::Result +where + A: Allocator, +{ + // For safety reasons, we don't want this sum to overflow ever. + // If this saturates, the reserve should panic to avoid any unsound writing. + let buf_len = bufs.iter().fold(0usize, |a, b| a.saturating_add(b.len())); + let mut pos = reserve_and_pad(pos_mut, vec, buf_len)?; + + // Write the buf then progress the vec forward if necessary + // Safety: we have ensured that the capacity is available + // and that all bytes get written up to the last pos + unsafe { + for buf in bufs { + pos = vec_write_all_unchecked(pos, vec, buf); + } + if pos > vec.len() { + vec.set_len(pos); + } + } + + // Bump us forward + *pos_mut += buf_len as u64; + Ok(buf_len) +} + +#[stable(feature = "cursor_mut_vec", since = "1.25.0")] +impl WriteThroughCursor for &mut Vec +where + A: Allocator, +{ + fn write(this: &mut Cursor, buf: &[u8]) -> io::Result { + let (pos, inner) = this.into_parts_mut(); + vec_write_all(pos, inner, buf) + } + + fn write_vectored(this: &mut Cursor, bufs: &[IoSlice<'_>]) -> io::Result { + let (pos, inner) = this.into_parts_mut(); + vec_write_all_vectored(pos, inner, bufs) + } + + #[inline] + fn is_write_vectored(_this: &Cursor) -> bool { + true + } + + fn write_all(this: &mut Cursor, buf: &[u8]) -> io::Result<()> { + let (pos, inner) = this.into_parts_mut(); + vec_write_all(pos, inner, buf)?; + Ok(()) + } + + fn write_all_vectored(this: &mut Cursor, bufs: &mut [IoSlice<'_>]) -> io::Result<()> { + let (pos, inner) = this.into_parts_mut(); + vec_write_all_vectored(pos, inner, bufs)?; + Ok(()) + } + + #[inline] + fn flush(_this: &mut Cursor) -> io::Result<()> { + Ok(()) + } +} + +#[stable(feature = "rust1", since = "1.0.0")] +impl WriteThroughCursor for Vec +where + A: Allocator, +{ + fn write(this: &mut Cursor, buf: &[u8]) -> io::Result { + let (pos, inner) = this.into_parts_mut(); + vec_write_all(pos, inner, buf) + } + + fn write_vectored(this: &mut Cursor, bufs: &[IoSlice<'_>]) -> io::Result { + let (pos, inner) = this.into_parts_mut(); + vec_write_all_vectored(pos, inner, bufs) + } + + #[inline] + fn is_write_vectored(_this: &Cursor) -> bool { + true + } + + fn write_all(this: &mut Cursor, buf: &[u8]) -> io::Result<()> { + let (pos, inner) = this.into_parts_mut(); + vec_write_all(pos, inner, buf)?; + Ok(()) + } + + fn write_all_vectored(this: &mut Cursor, bufs: &mut [IoSlice<'_>]) -> io::Result<()> { + let (pos, inner) = this.into_parts_mut(); + vec_write_all_vectored(pos, inner, bufs)?; + Ok(()) + } + + #[inline] + fn flush(_this: &mut Cursor) -> io::Result<()> { + Ok(()) + } +} + +#[stable(feature = "cursor_box_slice", since = "1.5.0")] +impl WriteThroughCursor for Box<[u8], A> +where + A: Allocator, +{ + #[inline] + fn write(this: &mut Cursor, buf: &[u8]) -> io::Result { + let (pos, inner) = this.into_parts_mut(); + slice_write(pos, inner, buf) + } + + #[inline] + fn write_vectored(this: &mut Cursor, bufs: &[IoSlice<'_>]) -> io::Result { + let (pos, inner) = this.into_parts_mut(); + slice_write_vectored(pos, inner, bufs) + } + + #[inline] + fn is_write_vectored(_this: &Cursor) -> bool { + true + } + + #[inline] + fn write_all(this: &mut Cursor, buf: &[u8]) -> io::Result<()> { + let (pos, inner) = this.into_parts_mut(); + slice_write_all(pos, inner, buf) + } + + #[inline] + fn write_all_vectored(this: &mut Cursor, bufs: &mut [IoSlice<'_>]) -> io::Result<()> { + let (pos, inner) = this.into_parts_mut(); + slice_write_all_vectored(pos, inner, bufs) + } + + #[inline] + fn flush(_this: &mut Cursor) -> io::Result<()> { + Ok(()) + } +} diff --git a/library/alloc/src/io/error.rs b/library/alloc/src/io/error.rs new file mode 100644 index 0000000000000..7b3e4b06ae38a --- /dev/null +++ b/library/alloc/src/io/error.rs @@ -0,0 +1,284 @@ +use core::io::Custom; +#[cfg_attr(no_global_oom_handling, expect(unused_imports))] +use core::io::CustomOwner; +use core::{error, result}; + +use crate::boxed::Box; +#[cfg_attr(any(no_rc, no_sync, no_global_oom_handling), expect(unused_imports))] +use crate::io::const_error; +use crate::io::{Error, ErrorKind}; + +impl Error { + /// Creates a new I/O error from a known kind of error as well as an + /// arbitrary error payload. + /// + /// This function is used to generically create I/O errors which do not + /// originate from the OS itself. The `error` argument is an arbitrary + /// payload which will be contained in this [`Error`]. + /// + /// Note that this function allocates memory on the heap. + /// If no extra payload is required, use the `From` conversion from + /// `ErrorKind`. + /// + /// # Examples + /// + /// ``` + /// use std::io::{Error, ErrorKind}; + /// + /// // errors can be created from strings + /// let custom_error = Error::new(ErrorKind::Other, "oh no!"); + /// + /// // errors can also be created from other errors + /// let custom_error2 = Error::new(ErrorKind::Interrupted, custom_error); + /// + /// // creating an error without payload (and without memory allocation) + /// let eof_error = Error::from(ErrorKind::UnexpectedEof); + /// ``` + #[cfg(not(no_global_oom_handling))] + #[stable(feature = "rust1", since = "1.0.0")] + #[cfg_attr(not(test), rustc_diagnostic_item = "io_error_new")] + #[inline(never)] + #[rustc_allow_incoherent_impl] + pub fn new(kind: ErrorKind, error: E) -> Error + where + E: Into>, + { + let custom = custom_owner_from_box(kind, error.into()); + + // SAFETY: `custom_owner` has been constructed from a `Box` from the `alloc` crate. + unsafe { Self::from_custom_owner(custom) } + } + + /// Creates a new I/O error from an arbitrary error payload. + /// + /// This function is used to generically create I/O errors which do not + /// originate from the OS itself. It is a shortcut for [`Error::new`][new] + /// with [`ErrorKind::Other`]. + /// + // FIXME(#74481): Hard-links required to link from `alloc` to `std` for incoherent method + /// [new]: struct.Error.html#method.new + /// + /// # Examples + /// + /// ``` + /// use std::io::Error; + /// + /// // errors can be created from strings + /// let custom_error = Error::other("oh no!"); + /// + /// // errors can also be created from other errors + /// let custom_error2 = Error::other(custom_error); + /// ``` + #[cfg(not(no_global_oom_handling))] + #[stable(feature = "io_error_other", since = "1.74.0")] + #[rustc_allow_incoherent_impl] + pub fn other(error: E) -> Error + where + E: Into>, + { + Self::new(ErrorKind::Other, error) + } + + /// Consumes the `Error`, returning its inner error (if any). + /// + /// If this [`Error`] was constructed via [`new`][new] or [`other`][other], + /// then this function will return [`Some`], + /// otherwise it will return [`None`]. + /// + // FIXME(#74481): Hard-links required to link from `alloc` to `std` for incoherent method + /// [new]: struct.Error.html#method.new + /// [other]: struct.Error.html#method.other + /// + /// # Examples + /// + /// ``` + /// use std::io::{Error, ErrorKind}; + /// + /// fn print_error(err: Error) { + /// if let Some(inner_err) = err.into_inner() { + /// println!("Inner error: {inner_err}"); + /// } else { + /// println!("No inner error"); + /// } + /// } + /// + /// fn main() { + /// // Will print "No inner error". + /// print_error(Error::last_os_error()); + /// // Will print "Inner error: ...". + /// print_error(Error::new(ErrorKind::Other, "oh no!")); + /// } + /// ``` + #[stable(feature = "io_error_inner", since = "1.3.0")] + #[must_use = "`self` will be dropped if the result is not used"] + #[inline] + #[rustc_allow_incoherent_impl] + pub fn into_inner(self) -> Option> { + let custom_owner = self.into_custom_owner().ok()?; + + let ptr = custom_owner.into_raw().as_ptr(); + + // SAFETY: + // `Error` can only contain a `CustomOwner` if it was constructed using `Box::into_raw`. + let custom = unsafe { Box::::from_raw(ptr) }; + + let ptr = custom.into_raw().as_ptr(); + + // SAFETY: + // Any `CustomOwner` from an `Error` was constructed by the `alloc` crate + // to contain a `Custom` which itself was constructed with `Box::into_raw`. + Some(unsafe { Box::from_raw(ptr) }) + } + + /// Attempts to downcast the custom boxed error to `E`. + /// + /// If this [`Error`] contains a custom boxed error, + /// then it would attempt downcasting on the boxed error, + /// otherwise it will return [`Err`]. + /// + /// If the custom boxed error has the same type as `E`, it will return [`Ok`], + /// otherwise it will also return [`Err`]. + /// + /// This method is meant to be a convenience routine for calling + /// `Box::downcast` on the custom boxed error, returned by + /// [`Error::into_inner`][into_inner]. + /// + // FIXME(#74481): Hard-links required to link from `alloc` to `std` for incoherent method + /// [into_inner]: struct.Error.html#method.into_inner + /// + /// # Examples + /// + /// ``` + /// use std::fmt; + /// use std::io; + /// use std::error::Error; + /// + /// #[derive(Debug)] + /// enum E { + /// Io(io::Error), + /// SomeOtherVariant, + /// } + /// + /// impl fmt::Display for E { + /// // ... + /// # fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + /// # todo!() + /// # } + /// } + /// impl Error for E {} + /// + /// impl From for E { + /// fn from(err: io::Error) -> E { + /// err.downcast::() + /// .unwrap_or_else(E::Io) + /// } + /// } + /// + /// impl From for io::Error { + /// fn from(err: E) -> io::Error { + /// match err { + /// E::Io(io_error) => io_error, + /// e => io::Error::new(io::ErrorKind::Other, e), + /// } + /// } + /// } + /// + /// # fn main() { + /// let e = E::SomeOtherVariant; + /// // Convert it to an io::Error + /// let io_error = io::Error::from(e); + /// // Cast it back to the original variant + /// let e = E::from(io_error); + /// assert!(matches!(e, E::SomeOtherVariant)); + /// + /// let io_error = io::Error::from(io::ErrorKind::AlreadyExists); + /// // Convert it to E + /// let e = E::from(io_error); + /// // Cast it back to the original variant + /// let io_error = io::Error::from(e); + /// assert_eq!(io_error.kind(), io::ErrorKind::AlreadyExists); + /// assert!(io_error.get_ref().is_none()); + /// assert!(io_error.raw_os_error().is_none()); + /// # } + /// ``` + #[stable(feature = "io_error_downcast", since = "1.79.0")] + #[rustc_allow_incoherent_impl] + pub fn downcast(self) -> result::Result + where + E: error::Error + Send + Sync + 'static, + { + if let Some(e) = self.get_ref() + && e.is::() + { + if let Some(b) = self.into_inner() + && let Ok(err) = b.downcast::() + { + Ok(*err) + } else { + // Safety: We have just checked that the condition is true + unsafe { core::hint::unreachable_unchecked() } + } + } else { + Err(self) + } + } +} + +#[cfg(all(not(no_rc), not(no_sync), not(no_global_oom_handling)))] +#[stable(feature = "rust1", since = "1.0.0")] +impl From for Error { + /// Converts a [`crate::ffi::NulError`] into a [`Error`]. + fn from(_: crate::ffi::NulError) -> Error { + const_error!(ErrorKind::InvalidInput, "data provided contains a nul byte") + } +} + +#[stable(feature = "io_error_from_try_reserve", since = "1.78.0")] +impl From for Error { + /// Converts `TryReserveError` to an error with [`ErrorKind::OutOfMemory`]. + /// + /// `TryReserveError` won't be available as the error `source()`, + /// but this may change in the future. + fn from(_: crate::collections::TryReserveError) -> Error { + // ErrorData::Custom allocates, which isn't great for handling OOM errors. + ErrorKind::OutOfMemory.into() + } +} + +#[cfg(not(no_global_oom_handling))] +fn custom_owner_from_box( + kind: ErrorKind, + error: Box, +) -> CustomOwner { + use core::ptr::NonNull; + + /// # Safety + /// + /// `ptr` must be valid to pass into `Box::from_raw`. + unsafe fn drop_box_raw(ptr: NonNull) { + // SAFETY + // Caller ensures `ptr` is valid to pass into `Box::from_raw`. + drop(unsafe { Box::from_non_null(ptr) }) + } + + let error = Box::into_non_null(error); + + // SAFETY: + // * `error` is valid up to a static lifetime, and owns its pointee. + // * `drop_box_raw` is safe to call for the pointer `error` exactly once. + // * `drop_box_raw` is safe to call on a pointer to this instance of `Custom`, + // and will be stored in a `CustomOwner`. + let custom = unsafe { + Custom::from_raw( + kind, + error, + drop_box_raw::, + drop_box_raw::, + ) + }; + + let custom = Box::into_non_null(Box::new(custom)); + + // SAFETY: the `outer_drop` provided to `custom` is valid for itself. + unsafe { CustomOwner::from_raw(custom) } +} diff --git a/library/std/src/io/impls.rs b/library/alloc/src/io/impls.rs similarity index 79% rename from library/std/src/io/impls.rs rename to library/alloc/src/io/impls.rs index d0245f3d4984c..0296cada74171 100644 --- a/library/std/src/io/impls.rs +++ b/library/alloc/src/io/impls.rs @@ -1,10 +1,17 @@ -#[cfg(test)] -mod tests; +use core::cmp; use crate::alloc::Allocator; +use crate::boxed::Box; +#[cfg(not(no_global_oom_handling))] use crate::collections::VecDeque; -use crate::io::{self, BorrowedCursor, BufRead, IoSlice, IoSliceMut, Read, Seek, SeekFrom, Write}; -use crate::{cmp, fmt, mem, str}; +use crate::fmt; +use crate::io::{ + self, BorrowedCursor, BufRead, IoSlice, IoSliceMut, Read, Seek, SeekFrom, SizeHint, Write, +}; +use crate::string::String; +#[cfg(all(not(no_rc), not(no_sync), target_has_atomic = "ptr"))] +use crate::sync::Arc; +use crate::vec::Vec; // ============================================================================= // Forwarding implementations @@ -17,7 +24,7 @@ impl Read for &mut R { } #[inline] - fn read_buf(&mut self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { (**self).read_buf(cursor) } @@ -47,75 +54,11 @@ impl Read for &mut R { } #[inline] - fn read_buf_exact(&mut self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf_exact(&mut self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { (**self).read_buf_exact(cursor) } } #[stable(feature = "rust1", since = "1.0.0")] -impl Write for &mut W { - #[inline] - fn write(&mut self, buf: &[u8]) -> io::Result { - (**self).write(buf) - } - - #[inline] - fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { - (**self).write_vectored(bufs) - } - - #[inline] - fn is_write_vectored(&self) -> bool { - (**self).is_write_vectored() - } - - #[inline] - fn flush(&mut self) -> io::Result<()> { - (**self).flush() - } - - #[inline] - fn write_all(&mut self, buf: &[u8]) -> io::Result<()> { - (**self).write_all(buf) - } - - #[inline] - fn write_all_vectored(&mut self, bufs: &mut [IoSlice<'_>]) -> io::Result<()> { - (**self).write_all_vectored(bufs) - } - - #[inline] - fn write_fmt(&mut self, fmt: fmt::Arguments<'_>) -> io::Result<()> { - (**self).write_fmt(fmt) - } -} -#[stable(feature = "rust1", since = "1.0.0")] -impl Seek for &mut S { - #[inline] - fn seek(&mut self, pos: SeekFrom) -> io::Result { - (**self).seek(pos) - } - - #[inline] - fn rewind(&mut self) -> io::Result<()> { - (**self).rewind() - } - - #[inline] - fn stream_len(&mut self) -> io::Result { - (**self).stream_len() - } - - #[inline] - fn stream_position(&mut self) -> io::Result { - (**self).stream_position() - } - - #[inline] - fn seek_relative(&mut self, offset: i64) -> io::Result<()> { - (**self).seek_relative(offset) - } -} -#[stable(feature = "rust1", since = "1.0.0")] impl BufRead for &mut B { #[inline] fn fill_buf(&mut self) -> io::Result<&[u8]> { @@ -156,7 +99,7 @@ impl Read for Box { } #[inline] - fn read_buf(&mut self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { (**self).read_buf(cursor) } @@ -186,10 +129,24 @@ impl Read for Box { } #[inline] - fn read_buf_exact(&mut self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf_exact(&mut self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { (**self).read_buf_exact(cursor) } } +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +impl SizeHint for Box { + #[inline] + fn lower_bound(&self) -> usize { + SizeHint::lower_bound(&**self) + } + + #[inline] + fn upper_bound(&self) -> Option { + SizeHint::upper_bound(&**self) + } +} + #[stable(feature = "rust1", since = "1.0.0")] impl Write for Box { #[inline] @@ -315,7 +272,7 @@ impl Read for &[u8] { } #[inline] - fn read_buf(&mut self, mut cursor: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, mut cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { let amt = cmp::min(cursor.capacity(), self.len()); let (a, b) = self.split_at(amt); @@ -367,10 +324,10 @@ impl Read for &[u8] { } #[inline] - fn read_buf_exact(&mut self, mut cursor: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf_exact(&mut self, mut cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { if cursor.capacity() > self.len() { // Append everything we can to the cursor. - cursor.append(*self); + cursor.append(self); *self = &self[self.len()..]; return Err(io::Error::READ_EXACT_EOF); } @@ -386,7 +343,16 @@ impl Read for &[u8] { fn read_to_end(&mut self, buf: &mut Vec) -> io::Result { let len = self.len(); buf.try_reserve(len)?; - buf.extend_from_slice(*self); + + cfg_select! { + no_global_oom_handling => { + buf.try_extend_from_slice_of_bytes(*self)?; + } + _ => { + buf.extend_from_slice(self); + } + } + *self = &self[len..]; Ok(len) } @@ -396,7 +362,16 @@ impl Read for &[u8] { let content = str::from_utf8(self).map_err(|_| io::Error::INVALID_UTF8)?; let len = self.len(); buf.try_reserve(len)?; - buf.push_str(content); + + cfg_select! { + no_global_oom_handling => { + buf.try_push_str(content)?; + } + _ => { + buf.push_str(content); + } + } + *self = &self[len..]; Ok(len) } @@ -415,81 +390,29 @@ impl BufRead for &[u8] { } } -/// Write is implemented for `&mut [u8]` by copying into the slice, overwriting -/// its data. -/// -/// Note that writing updates the slice to point to the yet unwritten part. -/// The slice will be empty when it has been completely overwritten. -/// -/// If the number of bytes to be written exceeds the size of the slice, write operations will -/// return short writes: ultimately, `Ok(0)`; in this situation, `write_all` returns an error of -/// kind `ErrorKind::WriteZero`. -#[stable(feature = "rust1", since = "1.0.0")] -impl Write for &mut [u8] { - #[inline] - fn write(&mut self, data: &[u8]) -> io::Result { - let amt = cmp::min(data.len(), self.len()); - let (a, b) = mem::take(self).split_at_mut(amt); - a.copy_from_slice(&data[..amt]); - *self = b; - Ok(amt) - } - - #[inline] - fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { - let mut nwritten = 0; - for buf in bufs { - nwritten += self.write(buf)?; - if self.is_empty() { - break; - } - } - - Ok(nwritten) - } - - #[inline] - fn is_write_vectored(&self) -> bool { - true - } - - #[inline] - fn write_all(&mut self, data: &[u8]) -> io::Result<()> { - if self.write(data)? < data.len() { Err(io::Error::WRITE_ALL_EOF) } else { Ok(()) } - } - - #[inline] - fn write_all_vectored(&mut self, bufs: &mut [IoSlice<'_>]) -> io::Result<()> { - for buf in bufs { - if self.write(buf)? < buf.len() { - return Err(io::Error::WRITE_ALL_EOF); - } - } - Ok(()) - } - - #[inline] - fn flush(&mut self) -> io::Result<()> { - Ok(()) - } -} - /// Write is implemented for `Vec` by appending to the vector. /// The vector will grow as needed. #[stable(feature = "rust1", since = "1.0.0")] impl Write for Vec { #[inline] fn write(&mut self, buf: &[u8]) -> io::Result { - self.extend_from_slice(buf); + ::write_all(self, buf)?; Ok(buf.len()) } #[inline] fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { let len = bufs.iter().map(|b| b.len()).sum(); - self.reserve(len); + cfg_select! { + no_global_oom_handling => { + self.try_reserve(len)?; + } + _ => { + self.reserve(len); + } + } for buf in bufs { - self.extend_from_slice(buf); + ::write_all(self, buf)?; } Ok(len) } @@ -501,7 +424,14 @@ impl Write for Vec { #[inline] fn write_all(&mut self, buf: &[u8]) -> io::Result<()> { - self.extend_from_slice(buf); + cfg_select! { + no_global_oom_handling => { + self.try_extend_from_slice_of_bytes(buf)?; + } + _ => { + self.extend_from_slice(buf); + } + } Ok(()) } @@ -518,6 +448,7 @@ impl Write for Vec { } /// Read is implemented for `VecDeque` by consuming bytes from the front of the `VecDeque`. +#[cfg(not(no_global_oom_handling))] #[stable(feature = "vecdeque_read_write", since = "1.63.0")] impl Read for VecDeque { /// Fill `buf` with the contents of the "front" slice as returned by @@ -556,7 +487,7 @@ impl Read for VecDeque { } #[inline] - fn read_buf(&mut self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { let (ref mut front, _) = self.as_slices(); let n = cmp::min(cursor.capacity(), front.len()); Read::read_buf(front, cursor)?; @@ -565,7 +496,7 @@ impl Read for VecDeque { } #[inline] - fn read_buf_exact(&mut self, mut cursor: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf_exact(&mut self, mut cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { let len = cursor.capacity(); let (front, back) = self.as_slices(); @@ -609,6 +540,7 @@ impl Read for VecDeque { } /// BufRead is implemented for `VecDeque` by reading bytes from the front of the `VecDeque`. +#[cfg(not(no_global_oom_handling))] #[stable(feature = "vecdeque_buf_read", since = "1.75.0")] impl BufRead for VecDeque { /// Returns the contents of the "front" slice as returned by @@ -627,6 +559,7 @@ impl BufRead for VecDeque { } /// Write is implemented for `VecDeque` by appending to the `VecDeque`, growing it as needed. +#[cfg(not(no_global_oom_handling))] #[stable(feature = "vecdeque_read_write", since = "1.63.0")] impl Write for VecDeque { #[inline] @@ -668,50 +601,124 @@ impl Write for VecDeque { } } -#[unstable(feature = "read_buf", issue = "78485")] -impl<'a> io::Write for core::io::BorrowedCursor<'a> { +#[cfg(all(not(no_rc), not(no_sync), target_has_atomic = "ptr"))] +#[stable(feature = "io_traits_arc", since = "1.73.0")] +impl Read for Arc +where + for<'a> &'a R: Read, + R: crate::io::IoHandle, +{ + #[inline] + fn read(&mut self, buf: &mut [u8]) -> io::Result { + (&**self).read(buf) + } + + #[inline] + fn read_buf(&mut self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { + (&**self).read_buf(cursor) + } + + #[inline] + fn read_vectored(&mut self, bufs: &mut [IoSliceMut<'_>]) -> io::Result { + (&**self).read_vectored(bufs) + } + + #[inline] + fn is_read_vectored(&self) -> bool { + (**self).is_read_vectored() + } + + #[inline] + fn read_to_end(&mut self, buf: &mut Vec) -> io::Result { + (&**self).read_to_end(buf) + } + + #[inline] + fn read_to_string(&mut self, buf: &mut String) -> io::Result { + (&**self).read_to_string(buf) + } + + #[inline] + fn read_exact(&mut self, buf: &mut [u8]) -> io::Result<()> { + (&**self).read_exact(buf) + } + + #[inline] + fn read_buf_exact(&mut self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { + (&**self).read_buf_exact(cursor) + } +} +#[cfg(all(not(no_rc), not(no_sync), target_has_atomic = "ptr"))] +#[stable(feature = "io_traits_arc", since = "1.73.0")] +impl Write for Arc +where + for<'a> &'a W: Write, + W: crate::io::IoHandle, +{ #[inline] fn write(&mut self, buf: &[u8]) -> io::Result { - let amt = cmp::min(buf.len(), self.capacity()); - self.append(&buf[..amt]); - Ok(amt) + (&**self).write(buf) } #[inline] fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { - let mut nwritten = 0; - for buf in bufs { - let n = self.write(buf)?; - nwritten += n; - if n < buf.len() { - break; - } - } - Ok(nwritten) + (&**self).write_vectored(bufs) } #[inline] fn is_write_vectored(&self) -> bool { - true + (**self).is_write_vectored() + } + + #[inline] + fn flush(&mut self) -> io::Result<()> { + (&**self).flush() } #[inline] fn write_all(&mut self, buf: &[u8]) -> io::Result<()> { - if self.write(buf)? < buf.len() { Err(io::Error::WRITE_ALL_EOF) } else { Ok(()) } + (&**self).write_all(buf) } #[inline] fn write_all_vectored(&mut self, bufs: &mut [IoSlice<'_>]) -> io::Result<()> { - for buf in bufs { - if self.write(buf)? < buf.len() { - return Err(io::Error::WRITE_ALL_EOF); - } - } - Ok(()) + (&**self).write_all_vectored(bufs) } #[inline] - fn flush(&mut self) -> io::Result<()> { - Ok(()) + fn write_fmt(&mut self, fmt: fmt::Arguments<'_>) -> io::Result<()> { + (&**self).write_fmt(fmt) + } +} +#[cfg(all(not(no_rc), not(no_sync), target_has_atomic = "ptr"))] +#[stable(feature = "io_traits_arc", since = "1.73.0")] +impl Seek for Arc +where + for<'a> &'a S: Seek, + S: crate::io::IoHandle, +{ + #[inline] + fn seek(&mut self, pos: SeekFrom) -> io::Result { + (&**self).seek(pos) + } + + #[inline] + fn rewind(&mut self) -> io::Result<()> { + (&**self).rewind() + } + + #[inline] + fn stream_len(&mut self) -> io::Result { + (&**self).stream_len() + } + + #[inline] + fn stream_position(&mut self) -> io::Result { + (&**self).stream_position() + } + + #[inline] + fn seek_relative(&mut self, offset: i64) -> io::Result<()> { + (&**self).seek_relative(offset) } } diff --git a/library/alloc/src/io/mod.rs b/library/alloc/src/io/mod.rs new file mode 100644 index 0000000000000..44d780292317f --- /dev/null +++ b/library/alloc/src/io/mod.rs @@ -0,0 +1,229 @@ +//! Traits, helpers, and type definitions for core I/O functionality. +//! +//! The `io` module contains a number of common things you'll need +//! when doing input and output. The most core part of this module is +//! the [`Read`] and [`Write`] traits, which provide the +//! most general interface for reading and writing input and output. +//! +//! ## Read and Write +//! +//! Because they are traits, [`Read`] and [`Write`] are implemented by a number +//! of other types, and you can implement them for your types too. As such, +//! you'll see a few different types of I/O throughout the documentation in +//! this module: [`File`]s, [`TcpStream`]s, and sometimes even [`Vec`]s. For +//! example, [`Read`] adds a [`read`][`Read::read`] method, which we can use on +//! [`File`]s: +//! +//! ```no_run +//! use std::io; +//! use std::io::prelude::*; +//! use std::fs::File; +//! +//! fn main() -> io::Result<()> { +//! let mut f = File::open("foo.txt")?; +//! let mut buffer = [0; 10]; +//! +//! // read up to 10 bytes +//! let n = f.read(&mut buffer)?; +//! +//! println!("The bytes: {:?}", &buffer[..n]); +//! Ok(()) +//! } +//! ``` +//! +//! [`Read`] and [`Write`] are so important, implementors of the two traits have a +//! nickname: readers and writers. So you'll sometimes see 'a reader' instead +//! of 'a type that implements the [`Read`] trait'. Much easier! +//! +//! ## Seek and BufRead +//! +//! Beyond that, there are two important traits that are provided: [`Seek`] +//! and [`BufRead`]. Both of these build on top of a reader to control +//! how the reading happens. [`Seek`] lets you control where the next byte is +//! coming from: +//! +//! ```no_run +//! use std::io; +//! use std::io::prelude::*; +//! use std::io::SeekFrom; +//! use std::fs::File; +//! +//! fn main() -> io::Result<()> { +//! let mut f = File::open("foo.txt")?; +//! let mut buffer = [0; 10]; +//! +//! // skip to the last 10 bytes of the file +//! f.seek(SeekFrom::End(-10))?; +//! +//! // read up to 10 bytes +//! let n = f.read(&mut buffer)?; +//! +//! println!("The bytes: {:?}", &buffer[..n]); +//! Ok(()) +//! } +//! ``` +//! +//! [`BufRead`] uses an internal buffer to provide a number of other ways to read, but +//! to show it off, we'll need to talk about buffers in general. Keep reading! +//! +//! ## BufReader and BufWriter +//! +//! Byte-based interfaces are unwieldy and can be inefficient, as we'd need to be +//! making near-constant calls to the operating system. To help with this, +//! `std::io` comes with two structs, [`BufReader`] and [`BufWriter`], which wrap +//! readers and writers. The wrapper uses a buffer, reducing the number of +//! calls and providing nicer methods for accessing exactly what you want. +//! +//! For example, [`BufReader`] works with the [`BufRead`] trait to add extra +//! methods to any reader: +//! +//! ```no_run +//! use std::io; +//! use std::io::prelude::*; +//! use std::io::BufReader; +//! use std::fs::File; +//! +//! fn main() -> io::Result<()> { +//! let f = File::open("foo.txt")?; +//! let mut reader = BufReader::new(f); +//! let mut buffer = String::new(); +//! +//! // read a line into buffer +//! reader.read_line(&mut buffer)?; +//! +//! println!("{buffer}"); +//! Ok(()) +//! } +//! ``` +//! +//! [`BufWriter`] doesn't add any new ways of writing; it just buffers every call +//! to [`write`][`Write::write`]: +//! +//! ```no_run +//! use std::io; +//! use std::io::prelude::*; +//! use std::io::BufWriter; +//! use std::fs::File; +//! +//! fn main() -> io::Result<()> { +//! let f = File::create("foo.txt")?; +//! { +//! let mut writer = BufWriter::new(f); +//! +//! // write a byte to the buffer +//! writer.write(&[42])?; +//! +//! } // the buffer is flushed once writer goes out of scope +//! +//! Ok(()) +//! } +//! ``` +//! +//! ## Iterator types +//! +//! A large number of the structures provided by `std::io` are for various +//! ways of iterating over I/O. For example, [`Lines`] is used to split over +//! lines: +//! +//! ```no_run +//! use std::io; +//! use std::io::prelude::*; +//! use std::io::BufReader; +//! use std::fs::File; +//! +//! fn main() -> io::Result<()> { +//! let f = File::open("foo.txt")?; +//! let reader = BufReader::new(f); +//! +//! for line in reader.lines() { +//! println!("{}", line?); +//! } +//! Ok(()) +//! } +//! ``` +//! +//! ## io::Result +//! +//! Last, but certainly not least, is [`io::Result`]. This type is used +//! as the return type of many `std::io` functions that can cause an error, and +//! can be returned from your own functions as well. Many of the examples in this +//! module use the [`?` operator]: +//! +//! ```no_run +//! use std::io; +//! +//! # #[allow(dead_code)] +//! fn read_input() -> io::Result<()> { +//! let mut input = String::new(); +//! +//! io::stdin().read_line(&mut input)?; +//! +//! println!("You typed: {}", input.trim()); +//! +//! Ok(()) +//! } +//! ``` +//! +//! The return type of `read_input()`, [`io::Result<()>`][`io::Result`], is a very +//! common type for functions which don't have a 'real' return value, but do want to +//! return errors if they happen. In this case, the only purpose of this function is +//! to read the line and print it, so we use `()`. +//! +//! [`File`]: ../../std/fs/struct.File.html +//! [`TcpStream`]: ../../std/net/struct.TcpStream.html +//! [`Vec`]: crate::vec::Vec +//! [`io::Result`]: self::Result +//! [`?` operator]: ../../book/appendix-02-operators.html + +mod buf_read; +mod buffered; +mod copy; +mod cursor; +mod error; +mod impls; +#[unstable(feature = "alloc_io", issue = "154046")] +pub mod prelude; +mod read; +mod util; + +#[unstable(feature = "raw_os_error_ty", issue = "107792")] +pub use core::io::RawOsError; +#[unstable(feature = "io_const_error_internals", issue = "none")] +pub use core::io::SimpleMessage; +#[unstable(feature = "io_const_error", issue = "133448")] +pub use core::io::const_error; +#[unstable(feature = "core_io_borrowed_buf", issue = "117693")] +pub use core::io::{BorrowedBuf, BorrowedCursor}; +#[unstable(feature = "alloc_io", issue = "154046")] +pub use core::io::{ + Chain, Cursor, Empty, Error, ErrorKind, IoSlice, IoSliceMut, Repeat, Result, Seek, SeekFrom, + Sink, Take, Write, empty, repeat, sink, +}; +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +pub use core::io::{IoHandle, OsFunctions, default_write_vectored, stream_len_default}; +use core::io::{ + SizeHint, WriteThroughCursor, chain, slice_write, slice_write_all, slice_write_all_vectored, + slice_write_vectored, take, +}; + +use self::read::{append_to_string, default_read_buf_exact, default_read_exact}; +use self::util::{bytes, lines, split, uninlined_slow_read_byte}; +#[unstable(feature = "alloc_io", issue = "154046")] +pub use self::{ + buf_read::BufRead, + buffered::{BufReader, BufWriter, IntoInnerError, LineWriter, WriterPanicked}, + copy::copy, + read::{Read, read_to_string}, + util::{Bytes, Lines, Split}, +}; +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +pub use self::{ + copy::{CopyState, SpecCopy}, + read::{ + DEFAULT_BUF_SIZE, default_read_buf, default_read_to_end, default_read_to_string, + default_read_vectored, + }, + util::SpecReadByte, +}; diff --git a/library/alloc/src/io/prelude.rs b/library/alloc/src/io/prelude.rs new file mode 100644 index 0000000000000..d3ebc373e6284 --- /dev/null +++ b/library/alloc/src/io/prelude.rs @@ -0,0 +1,13 @@ +//! The I/O Prelude. +//! +//! The purpose of this module is to alleviate imports of many common I/O traits +//! by adding a glob import to the top of I/O heavy modules: +//! +//! ``` +//! # #![feature(alloc_io)] +//! # #![allow(unused_imports)] +//! use alloc::io::prelude::*; +//! ``` + +#[stable(feature = "rust1", since = "1.0.0")] +pub use crate::io::{BufRead, Read, Seek, Write}; diff --git a/library/alloc/src/io/read.rs b/library/alloc/src/io/read.rs new file mode 100644 index 0000000000000..502eddc827bfc --- /dev/null +++ b/library/alloc/src/io/read.rs @@ -0,0 +1,1108 @@ +use core::mem::{DropGuard, MaybeUninit}; + +use crate::io::{ + BorrowedBuf, BorrowedCursor, Bytes, Chain, Error, IoSliceMut, Result, Take, bytes, chain, take, +}; +use crate::string::String; +use crate::vec::Vec; + +/// The `Read` trait allows for reading bytes from a source. +/// +/// Implementors of the `Read` trait are called 'readers'. +/// +/// Readers are defined by one required method, [`read()`]. Each call to [`read()`] +/// will attempt to pull bytes from this source into a provided buffer. A +/// number of other methods are implemented in terms of [`read()`], giving +/// implementors a number of ways to read bytes while only needing to implement +/// a single method. +/// +/// Readers are intended to be composable with one another. Many implementors +/// throughout [`std::io`] take and provide types which implement the `Read` +/// trait. +/// +/// Please note that each call to [`read()`] may involve a system call, and +/// therefore, using something that implements [`BufRead`], such as +/// `BufReader`, will be more efficient. +/// +/// [`BufRead`]: crate::io::BufRead +/// +/// Repeated calls to the reader use the same cursor, so for example +/// calling `read_to_end` twice on a `File` will only return the file's +/// contents once. It's recommended to first call `rewind()` in that case. +/// +/// # Examples +/// +/// `File`s implement `Read`: +/// +/// ```no_run +/// use std::io; +/// use std::io::prelude::*; +/// use std::fs::File; +/// +/// fn main() -> io::Result<()> { +/// let mut f = File::open("foo.txt")?; +/// let mut buffer = [0; 10]; +/// +/// // read up to 10 bytes +/// f.read(&mut buffer)?; +/// +/// let mut buffer = Vec::new(); +/// // read the whole file +/// f.read_to_end(&mut buffer)?; +/// +/// // read into a String, so that you don't need to do the conversion. +/// let mut buffer = String::new(); +/// f.read_to_string(&mut buffer)?; +/// +/// // and more! See the other methods for more details. +/// Ok(()) +/// } +/// ``` +/// +/// Read from [`&str`] because [`&[u8]`][prim@slice] implements `Read`: +/// +/// ```no_run +/// # use std::io; +/// use std::io::prelude::*; +/// +/// fn main() -> io::Result<()> { +/// let mut b = "This string will be read".as_bytes(); +/// let mut buffer = [0; 10]; +/// +/// // read up to 10 bytes +/// b.read(&mut buffer)?; +/// +/// // etc... it works exactly as a File does! +/// Ok(()) +/// } +/// ``` +/// +/// [`read()`]: Read::read +/// [`&str`]: prim@str +/// [`std::io`]: crate::io +#[stable(feature = "rust1", since = "1.0.0")] +#[doc(notable_trait)] +#[cfg_attr(not(test), rustc_diagnostic_item = "IoRead")] +#[rustc_must_implement_one_of(read_buf, read)] // Keep this order, it's important for rust-analyzer (the preferred-to-implement method should come first). +pub trait Read { + /// Pull some bytes from this source into the specified buffer, returning + /// how many bytes were read. + /// + /// This function does not provide any guarantees about whether it blocks + /// waiting for data, but if an object needs to block for a read and cannot, + /// it will typically signal this via an [`Err`] return value. + /// + /// If the return value of this method is [`Ok(n)`], then implementations must + /// guarantee that `0 <= n <= buf.len()`. A nonzero `n` value indicates + /// that the buffer `buf` has been filled in with `n` bytes of data from this + /// source. If `n` is `0`, then it can indicate one of two scenarios: + /// + /// 1. This reader has reached its "end of file" and will likely no longer + /// be able to produce bytes. Note that this does not mean that the + /// reader will *always* no longer be able to produce bytes. As an example, + /// on Linux, this method will call the `recv` syscall for a `TcpStream`, + /// where returning zero indicates the connection was shut down correctly. While + /// for `File`, it is possible to reach the end of file and get zero as result, + /// but if more data is appended to the file, future calls to `read` will return + /// more data. + /// 2. The buffer specified was 0 bytes in length. + /// + /// It is not an error if the returned value `n` is smaller than the buffer size, + /// even when the reader is not at the end of the stream yet. + /// This may happen for example because fewer bytes are actually available right now + /// (e. g. being close to end-of-file) or because read() was interrupted by a signal. + /// + /// As this trait is safe to implement, callers in unsafe code cannot rely on + /// `n <= buf.len()` for safety. + /// Extra care needs to be taken when `unsafe` functions are used to access the read bytes. + /// Callers have to ensure that no unchecked out-of-bounds accesses are possible even if + /// `n > buf.len()`. + /// + /// *Implementations* of this method can make no assumptions about the contents of `buf` when + /// this function is called. It is recommended that implementations only write data to `buf` + /// instead of reading its contents. + /// + /// Correspondingly, however, *callers* of this method in unsafe code must not assume + /// any guarantees about how the implementation uses `buf`. The trait is safe to implement, + /// so it is possible that the code that's supposed to write to the buffer might also read + /// from it. It is your responsibility to make sure that `buf` is initialized + /// before calling `read`. Calling `read` with an uninitialized `buf` (of the kind one + /// obtains via [`MaybeUninit`]) is not safe, and can lead to undefined behavior. + /// + /// [`MaybeUninit`]: core::mem::MaybeUninit + /// + /// # Errors + /// + /// If this function encounters any form of I/O or other error, an error + /// variant will be returned. If an error is returned then it must be + /// guaranteed that no bytes were read. + /// + /// An error of the [`ErrorKind::Interrupted`] kind is non-fatal and the read + /// operation should be retried if there is nothing else to do. + /// + /// # Examples + /// + /// `File`s implement `Read`: + /// + /// [`Ok(n)`]: Ok + /// [`ErrorKind::Interrupted`]: crate::io::ErrorKind::Interrupted + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let mut f = File::open("foo.txt")?; + /// let mut buffer = [0; 10]; + /// + /// // read up to 10 bytes + /// let n = f.read(&mut buffer[..])?; + /// + /// println!("The bytes: {:?}", &buffer[..n]); + /// Ok(()) + /// } + /// ``` + #[stable(feature = "rust1", since = "1.0.0")] + fn read(&mut self, buf: &mut [u8]) -> Result { + let mut buf = BorrowedBuf::from(buf); + self.read_buf(buf.unfilled()).map(|()| buf.len()) + } + + /// Like `read`, except that it reads into a slice of buffers. + /// + /// Data is copied to fill each buffer in order, with the final buffer + /// written to possibly being only partially filled. This method must + /// behave equivalently to a single call to `read` with concatenated + /// buffers. + /// + /// The default implementation calls `read` with either the first nonempty + /// buffer provided, or an empty one if none exists. + #[stable(feature = "iovec", since = "1.36.0")] + fn read_vectored(&mut self, bufs: &mut [IoSliceMut<'_>]) -> Result { + default_read_vectored(|b| self.read(b), bufs) + } + + /// Determines if this `Read`er has an efficient `read_vectored` + /// implementation. + /// + /// If a `Read`er does not override the default `read_vectored` + /// implementation, code using it may want to avoid the method all together + /// and coalesce writes into a single buffer for higher performance. + /// + /// The default implementation returns `false`. + #[unstable(feature = "can_vector", issue = "69941")] + fn is_read_vectored(&self) -> bool { + false + } + + /// Reads all bytes until EOF in this source, placing them into `buf`. + /// + /// All bytes read from this source will be appended to the specified buffer + /// `buf`. This function will continuously call [`read()`] to append more data to + /// `buf` until [`read()`] returns either [`Ok(0)`] or an error of + /// non-[`ErrorKind::Interrupted`] kind. + /// + /// If successful, this function will return the total number of bytes read. + /// + /// # Errors + /// + /// If this function encounters an error of the kind + /// [`ErrorKind::Interrupted`] then the error is ignored and the operation + /// will continue. + /// + /// If any other read error is encountered then this function immediately + /// returns. Any bytes which have already been read will be appended to + /// `buf`. + /// + /// # Examples + /// + /// `File`s implement `Read`: + /// + /// [`Ok(0)`]: Ok + /// [`ErrorKind::Interrupted`]: crate::io::ErrorKind::Interrupted + /// [`read()`]: Read::read + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let mut f = File::open("foo.txt")?; + /// let mut buffer = Vec::new(); + /// + /// // read the whole file + /// f.read_to_end(&mut buffer)?; + /// Ok(()) + /// } + /// ``` + /// + /// (See also the `std::fs::read` convenience function for reading from a + /// file.) + /// + /// ## Implementing `read_to_end` + /// + /// When implementing the `io::Read` trait, it is recommended to allocate + /// memory using [`Vec::try_reserve`]. However, this behavior is not guaranteed + /// by all implementations, and `read_to_end` may not handle out-of-memory + /// situations gracefully. + /// + /// ```no_run + /// # #![expect(dead_code)] + /// # use std::io::{self, BufRead}; + /// # struct Example { example_datasource: io::Empty } impl Example { + /// # fn get_some_data_for_the_example(&self) -> &'static [u8] { &[] } + /// fn read_to_end(&mut self, dest_vec: &mut Vec) -> io::Result { + /// let initial_vec_len = dest_vec.len(); + /// loop { + /// let src_buf = self.example_datasource.fill_buf()?; + /// if src_buf.is_empty() { + /// break; + /// } + /// dest_vec.try_reserve(src_buf.len())?; + /// dest_vec.extend_from_slice(src_buf); + /// + /// // Any irreversible side effects should happen after `try_reserve` succeeds, + /// // to avoid losing data on allocation error. + /// let read = src_buf.len(); + /// self.example_datasource.consume(read); + /// } + /// Ok(dest_vec.len() - initial_vec_len) + /// } + /// # } + /// ``` + /// + /// # Usage Notes + /// + /// `read_to_end` attempts to read a source until EOF, but many sources are continuous streams + /// that do not send EOF. In these cases, `read_to_end` will block indefinitely. Standard input + /// is one such stream which may be finite if piped, but is typically continuous. For example, + /// `cat file | my-rust-program` will correctly terminate with an `EOF` upon closure of cat. + /// Reading user input or running programs that remain open indefinitely will never terminate + /// the stream with `EOF` (e.g. `yes | my-rust-program`). + /// + /// Using `.lines()` with a `BufReader` or using [`read`] can provide a better solution + /// + /// [`read`]: Read::read + /// [`Vec::try_reserve`]: crate::vec::Vec::try_reserve + #[stable(feature = "rust1", since = "1.0.0")] + fn read_to_end(&mut self, buf: &mut Vec) -> Result { + default_read_to_end(self, buf, None) + } + + /// Reads all bytes until EOF in this source, appending them to `buf`. + /// + /// If successful, this function returns the number of bytes which were read + /// and appended to `buf`. + /// + /// # Errors + /// + /// If the data in this stream is *not* valid UTF-8 then an error is + /// returned and `buf` is unchanged. + /// + /// See [`read_to_end`] for other error semantics. + /// + /// [`read_to_end`]: Read::read_to_end + /// + /// # Examples + /// + /// `File`s implement `Read`: + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let mut f = File::open("foo.txt")?; + /// let mut buffer = String::new(); + /// + /// f.read_to_string(&mut buffer)?; + /// Ok(()) + /// } + /// ``` + /// + /// (See also the `std::fs::read_to_string` convenience function for + /// reading from a file.) + /// + /// # Usage Notes + /// + /// `read_to_string` attempts to read a source until EOF, but many sources are continuous streams + /// that do not send EOF. In these cases, `read_to_string` will block indefinitely. Standard input + /// is one such stream which may be finite if piped, but is typically continuous. For example, + /// `cat file | my-rust-program` will correctly terminate with an `EOF` upon closure of cat. + /// Reading user input or running programs that remain open indefinitely will never terminate + /// the stream with `EOF` (e.g. `yes | my-rust-program`). + /// + /// Using `.lines()` with a `BufReader` or using [`read`] can provide a better solution + /// + /// [`read`]: Read::read + #[stable(feature = "rust1", since = "1.0.0")] + fn read_to_string(&mut self, buf: &mut String) -> Result { + default_read_to_string(self, buf, None) + } + + /// Reads the exact number of bytes required to fill `buf`. + /// + /// This function reads as many bytes as necessary to completely fill the + /// specified buffer `buf`. + /// + /// *Implementations* of this method can make no assumptions about the contents of `buf` when + /// this function is called. It is recommended that implementations only write data to `buf` + /// instead of reading its contents. The documentation on [`read`] has a more detailed + /// explanation of this subject. + /// + /// # Errors + /// + /// If this function encounters an error of the kind + /// [`ErrorKind::Interrupted`] then the error is ignored and the operation + /// will continue. + /// + /// If this function encounters an "end of file" before completely filling + /// the buffer, it returns an error of the kind [`ErrorKind::UnexpectedEof`]. + /// The contents of `buf` are unspecified in this case. + /// + /// If any other read error is encountered then this function immediately + /// returns. The contents of `buf` are unspecified in this case. + /// + /// If this function returns an error, it is unspecified how many bytes it + /// has read, but it will never read more than would be necessary to + /// completely fill the buffer. + /// + /// # Examples + /// + /// `File`s implement `Read`: + /// + /// [`ErrorKind::Interrupted`]: crate::io::ErrorKind::Interrupted + /// [`ErrorKind::UnexpectedEof`]: crate::io::ErrorKind::UnexpectedEof + /// [`read`]: Read::read + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let mut f = File::open("foo.txt")?; + /// let mut buffer = [0; 10]; + /// + /// // read exactly 10 bytes + /// f.read_exact(&mut buffer)?; + /// Ok(()) + /// } + /// ``` + #[stable(feature = "read_exact", since = "1.6.0")] + fn read_exact(&mut self, buf: &mut [u8]) -> Result<()> { + default_read_exact(self, buf) + } + + /// Pull some bytes from this source into the specified buffer. + /// + /// This is equivalent to the [`read`](Read::read) method, except that it is passed a [`BorrowedCursor`] rather than `[u8]` to allow use + /// with uninitialized buffers. The new data will be appended to any existing contents of `buf`. + /// + /// The default implementation delegates to `read`. + /// + /// This method makes it possible to return both data and an error but it is advised against. + #[unstable(feature = "read_buf", issue = "78485")] + fn read_buf(&mut self, buf: BorrowedCursor<'_, u8>) -> Result<()> { + default_read_buf(|b| self.read(b), buf) + } + + /// Reads the exact number of bytes required to fill `cursor`. + /// + /// This is similar to the [`read_exact`](Read::read_exact) method, except + /// that it is passed a [`BorrowedCursor`] rather than `[u8]` to allow use + /// with uninitialized buffers. + /// + /// # Errors + /// + /// If this function encounters an error of the kind [`ErrorKind::Interrupted`] + /// then the error is ignored and the operation will continue. + /// + /// If this function encounters an "end of file" before completely filling + /// the buffer, it returns an error of the kind [`ErrorKind::UnexpectedEof`]. + /// + /// If any other read error is encountered then this function immediately + /// returns. + /// + /// If this function returns an error, all bytes read will be appended to `cursor`. + /// + /// [`ErrorKind::Interrupted`]: crate::io::ErrorKind::Interrupted + /// [`ErrorKind::UnexpectedEof`]: crate::io::ErrorKind::UnexpectedEof + #[unstable(feature = "read_buf", issue = "78485")] + #[doc(alias("read_exact_buf"))] + fn read_buf_exact(&mut self, cursor: BorrowedCursor<'_, u8>) -> Result<()> { + default_read_buf_exact(self, cursor) + } + + /// Creates a "by reference" adapter for this instance of `Read`. + /// + /// The returned adapter also implements `Read` and will simply borrow this + /// current reader. + /// + /// # Examples + /// + /// `File`s implement `Read`: + /// + /// ```no_run + /// use std::io; + /// use std::io::Read; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let mut f = File::open("foo.txt")?; + /// let mut buffer = Vec::new(); + /// let mut other_buffer = Vec::new(); + /// + /// { + /// let reference = f.by_ref(); + /// + /// // read at most 5 bytes + /// reference.take(5).read_to_end(&mut buffer)?; + /// + /// } // drop our &mut reference so we can use f again + /// + /// // original file still usable, read the rest + /// f.read_to_end(&mut other_buffer)?; + /// Ok(()) + /// } + /// ``` + #[stable(feature = "rust1", since = "1.0.0")] + fn by_ref(&mut self) -> &mut Self + where + Self: Sized, + { + self + } + + /// Transforms this `Read` instance to an [`Iterator`] over its bytes. + /// + /// The returned type implements [`Iterator`] where the [`Item`] is + /// [Result]<[u8], [io::Error]>. + /// The yielded item is [`Ok`] if a byte was successfully read and [`Err`] + /// otherwise. EOF is mapped to returning [`None`] from this iterator. + /// + /// The default implementation calls `read` for each byte, + /// which can be very inefficient for data that's not in memory, + /// such as `File`. Consider using a `BufReader` in such cases. + /// + /// # Errors + /// + /// When the returned iterator calls [`Iterator::next`], + /// if it encounters an error of the kind [`ErrorKind::Interrupted`] + /// then the error is ignored and it will try to read the byte again. + /// + /// [`ErrorKind::Interrupted`]: crate::io::ErrorKind::Interrupted + /// + /// # Examples + /// + /// `File`s implement `Read`: + /// + /// [`Item`]: Iterator::Item + /// [Result]: core::result::Result "Result" + /// [io::Error]: crate::io::Error "io::Error" + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// use std::io::BufReader; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let f = BufReader::new(File::open("foo.txt")?); + /// + /// for byte in f.bytes() { + /// println!("{}", byte?); + /// } + /// Ok(()) + /// } + /// ``` + #[stable(feature = "rust1", since = "1.0.0")] + fn bytes(self) -> Bytes + where + Self: Sized, + { + bytes(self) + } + + /// Creates an adapter which will chain this stream with another. + /// + /// The returned `Read` instance will first read all bytes from this object + /// until EOF is encountered. Afterwards the output is equivalent to the + /// output of `next`. + /// + /// # Examples + /// + /// `File`s implement `Read`: + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let f1 = File::open("foo.txt")?; + /// let f2 = File::open("bar.txt")?; + /// + /// let mut handle = f1.chain(f2); + /// let mut buffer = String::new(); + /// + /// // read the value into a String. We could use any Read method here, + /// // this is just one example. + /// handle.read_to_string(&mut buffer)?; + /// Ok(()) + /// } + /// ``` + #[stable(feature = "rust1", since = "1.0.0")] + fn chain(self, next: R) -> Chain + where + Self: Sized, + { + chain(self, next) + } + + /// Creates an adapter which will read at most `limit` bytes from it. + /// + /// This function returns a new instance of `Read` which will read at most + /// `limit` bytes, after which it will always return EOF ([`Ok(0)`]). Any + /// read errors will not count towards the number of bytes read and future + /// calls to [`read()`] may succeed. + /// + /// # Examples + /// + /// `File`s implement `Read`: + /// + /// [`Ok(0)`]: Ok + /// [`read()`]: Read::read + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let f = File::open("foo.txt")?; + /// let mut buffer = [0; 5]; + /// + /// // read at most five bytes + /// let mut handle = f.take(5); + /// + /// handle.read(&mut buffer)?; + /// Ok(()) + /// } + /// ``` + #[stable(feature = "rust1", since = "1.0.0")] + fn take(self, limit: u64) -> Take + where + Self: Sized, + { + take(self, limit) + } + + /// Read and return a fixed array of bytes from this source. + /// + /// This function uses an array sized based on a const generic size known at compile time. You + /// can specify the size with turbofish (`reader.read_array::<8>()`), or let type inference + /// determine the number of bytes needed based on how the return value gets used. For instance, + /// this function works well with functions like [`u64::from_le_bytes`] to turn an array of + /// bytes into an integer of the same size. + /// + /// Like `read_exact`, if this function encounters an "end of file" before reading the desired + /// number of bytes, it returns an error of the kind [`ErrorKind::UnexpectedEof`]. + /// + /// [`ErrorKind::UnexpectedEof`]: crate::io::ErrorKind::UnexpectedEof + /// + /// ``` + /// #![feature(read_array)] + /// use std::io::Cursor; + /// use std::io::prelude::*; + /// + /// fn main() -> std::io::Result<()> { + /// let mut buf = Cursor::new([1, 2, 3, 4, 5, 6, 7, 8, 9, 8, 7, 6, 5, 4, 3, 2]); + /// let x = u64::from_le_bytes(buf.read_array()?); + /// let y = u32::from_be_bytes(buf.read_array()?); + /// let z = u16::from_be_bytes(buf.read_array()?); + /// assert_eq!(x, 0x807060504030201); + /// assert_eq!(y, 0x9080706); + /// assert_eq!(z, 0x504); + /// Ok(()) + /// } + /// ``` + #[unstable(feature = "read_array", issue = "148848")] + fn read_array(&mut self) -> Result<[u8; N]> + where + Self: Sized, + { + let mut buf = [MaybeUninit::uninit(); N]; + let mut borrowed_buf = BorrowedBuf::from(buf.as_mut_slice()); + self.read_buf_exact(borrowed_buf.unfilled())?; + // Guard against incorrect `read_buf_exact` implementations. + assert_eq!(borrowed_buf.len(), N); + Ok(unsafe { MaybeUninit::array_assume_init(buf) }) + } + + /// Read and return a type (e.g. an integer) in little-endian order. + /// + /// You can specify the type with turbofish (`reader.read_le::()`), or let type inference + /// determine the type based on how the return value gets used. + /// + /// Like `read_exact`, if this function encounters an "end of file" before reading the desired + /// number of bytes, it returns an error of the kind [`ErrorKind::UnexpectedEof`]. + /// + /// [`ErrorKind::UnexpectedEof`]: crate::io::ErrorKind::UnexpectedEof + /// + /// ``` + /// #![feature(read_le)] + /// use std::io::Cursor; + /// use std::io::prelude::*; + /// + /// fn main() -> std::io::Result<()> { + /// let mut buf = Cursor::new([1, 2, 3, 4, 5, 6, 7, 8, 9, 8, 7, 6, 5, 4, 3, 2]); + /// let x: u64 = buf.read_le()?; + /// let y: u32 = buf.read_le()?; + /// let z = buf.read_le::()?; + /// assert_eq!(x, 0x807060504030201); + /// assert_eq!(y, 0x6070809); + /// assert_eq!(z, 0x405); + /// Ok(()) + /// } + /// ``` + #[unstable(feature = "read_le", issue = "156984")] + #[inline] + fn read_le(&mut self) -> Result + where + Self: Sized, + { + T::read_le_from(self) + } + + /// Read and return a type (e.g. an integer) in big-endian order. + /// + /// You can specify the type with turbofish (`reader.read_be::()`), or let type inference + /// determine the type based on how the return value gets used. + /// + /// Like `read_exact`, if this function encounters an "end of file" before reading the desired + /// number of bytes, it returns an error of the kind [`ErrorKind::UnexpectedEof`]. + /// + /// [`ErrorKind::UnexpectedEof`]: crate::io::ErrorKind::UnexpectedEof + /// + /// ``` + /// #![feature(read_le)] + /// use std::io::Cursor; + /// use std::io::prelude::*; + /// + /// fn main() -> std::io::Result<()> { + /// let mut buf = Cursor::new([1, 2, 3, 4, 5, 6, 7, 8, 9, 8, 7, 6, 5, 4, 3, 2]); + /// let x: u64 = buf.read_be()?; + /// let y: u32 = buf.read_be()?; + /// let z = buf.read_be::()?; + /// assert_eq!(x, 0x102030405060708); + /// assert_eq!(y, 0x9080706); + /// assert_eq!(z, 0x504); + /// Ok(()) + /// } + /// ``` + #[unstable(feature = "read_le", issue = "156984")] + #[inline] + fn read_be(&mut self) -> Result + where + Self: Sized, + { + T::read_be_from(self) + } +} + +/// Reads all bytes from a [reader][Read] into a new [`String`]. +/// +/// This is a convenience function for [`Read::read_to_string`]. Using this +/// function avoids having to create a variable first and provides more type +/// safety since you can only get the buffer out if there were no errors. (If you +/// use [`Read::read_to_string`] you have to remember to check whether the read +/// succeeded because otherwise your buffer will be empty or only partially full.) +/// +/// # Performance +/// +/// The downside of this function's increased ease of use and type safety is +/// that it gives you less control over performance. For example, you can't +/// pre-allocate memory like you can using [`String::with_capacity`] and +/// [`Read::read_to_string`]. Also, you can't re-use the buffer if an error +/// occurs while reading. +/// +/// In many cases, this function's performance will be adequate and the ease of use +/// and type safety tradeoffs will be worth it. However, there are cases where you +/// need more control over performance, and in those cases you should definitely use +/// [`Read::read_to_string`] directly. +/// +/// Note that in some special cases, such as when reading files, this function will +/// pre-allocate memory based on the size of the input it is reading. In those +/// cases, the performance should be as good as if you had used +/// [`Read::read_to_string`] with a manually pre-allocated buffer. +/// +/// # Errors +/// +/// This function forces you to handle errors because the output (the `String`) +/// is wrapped in a [`Result`]. See [`Read::read_to_string`] for the errors +/// that can occur. If any error occurs, you will get an [`Err`], so you +/// don't have to worry about your buffer being empty or partially full. +/// +/// # Examples +/// +/// ```no_run +/// # use std::io; +/// fn main() -> io::Result<()> { +/// let stdin = io::read_to_string(io::stdin())?; +/// println!("Stdin was:"); +/// println!("{stdin}"); +/// Ok(()) +/// } +/// ``` +/// +/// # Usage Notes +/// +/// `read_to_string` attempts to read a source until EOF, but many sources are continuous streams +/// that do not send EOF. In these cases, `read_to_string` will block indefinitely. Standard input +/// is one such stream which may be finite if piped, but is typically continuous. For example, +/// `cat file | my-rust-program` will correctly terminate with an `EOF` upon closure of cat. +/// Reading user input or running programs that remain open indefinitely will never terminate +/// the stream with `EOF` (e.g. `yes | my-rust-program`). +/// +/// Using `.lines()` with a `BufReader` or using [`read`] can provide a better solution +/// +/// [`read`]: Read::read +/// +#[stable(feature = "io_read_to_string", since = "1.65.0")] +pub fn read_to_string(mut reader: R) -> Result { + let mut buf = String::new(); + reader.read_to_string(&mut buf)?; + Ok(buf) +} + +/// Bare metal platforms usually have very small amounts of RAM +/// (in the order of hundreds of KB) +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +pub const DEFAULT_BUF_SIZE: usize = cfg_select! { + target_os = "espidf" => 512, + _ => 8 * 1024, +}; + +/// Several `read_to_string` and `read_line` methods in the standard library will +/// append data into a `String` buffer, but we need to be pretty careful when +/// doing this. The implementation will just call `.as_mut_vec()` and then +/// delegate to a byte-oriented reading method, but we must ensure that when +/// returning we never leave `buf` in a state such that it contains invalid UTF-8 +/// in its bounds. +/// +/// To this end, we use an RAII guard (to protect against panics) which updates +/// the length of the string when it is dropped. This guard initially truncates +/// the string to the prior length and only after we've validated that the +/// new contents are valid UTF-8 do we allow it to set a longer length. +/// +/// The unsafety in this function is twofold: +/// +/// 1. We're looking at the raw bytes of `buf`, so we take on the burden of UTF-8 +/// checks. +/// 2. We're passing a raw buffer to the function `f`, and it is expected that +/// the function only *appends* bytes to the buffer. We'll get undefined +/// behavior if existing bytes are overwritten to have non-UTF-8 data. +pub(super) unsafe fn append_to_string(buf: &mut String, f: F) -> Result +where + F: FnOnce(&mut Vec) -> Result, +{ + let len_original = buf.len(); + // SAFETY: invalid UTF-8 discarded before return or unwind + let buf_vec = unsafe { buf.as_mut_vec() }; + let mut g = DropGuard::new((len_original, buf_vec), |(len, buf)| unsafe { + buf.set_len(len); + }); + let ret = f(g.1); + + // SAFETY: the caller promises to only append data to `buf` + let appended = unsafe { g.1.get_unchecked(g.0..) }; + if str::from_utf8(appended).is_err() { + ret.and_then(|_| Err(Error::INVALID_UTF8)) + } else { + g.0 = g.1.len(); + ret + } +} + +/// Here we must serve many masters with conflicting goals: +/// +/// - avoid allocating unless necessary +/// - avoid overallocating if we know the exact size (#89165) +/// - avoid passing large buffers to readers that always initialize the free capacity if they perform short reads (#23815, #23820) +/// - avoid re-initializing unfilled bytes into the spare buffer if we initialized >PROBE_SIZE unfilled bytes in a previous loop (#158008) +/// - pass large buffers to readers that do not initialize the spare capacity. this can amortize per-call overheads +/// - pass not-too-small and not-too-large buffers to Windows read APIs because they manage to suffer from both problems +/// at the same time, i.e. small reads suffer from syscall overhead, all reads incur costs proportional to buffer size (#110650) +/// - also avoid <4 byte reads as this may split UTF-8 code points, which can be a problem for Windows console reads (#142847) +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +pub fn default_read_to_end( + r: &mut R, + buf: &mut Vec, + size_hint: Option, +) -> Result { + let start_len = buf.len(); + let start_cap = buf.capacity(); + // Optionally limit the maximum bytes read on each iteration. + // This adds an arbitrary fiddle factor to allow for more data than we expect. + let mut max_read_size = size_hint + .and_then(|s| s.checked_add(1024)?.checked_next_multiple_of(DEFAULT_BUF_SIZE)) + .unwrap_or(DEFAULT_BUF_SIZE); + + // Tracks how many bytes are initialized in the buffer + let mut init_until = buf.len(); + + const PROBE_SIZE: usize = 32; + + fn small_probe_read(r: &mut R, buf: &mut Vec) -> Result { + let mut probe = [0u8; PROBE_SIZE]; + + loop { + cfg_select! { + no_global_oom_handling => { + // Without global OOM handling we must proactively allocate the buffer + // to avoid failing after already reading data. + buf.try_reserve(PROBE_SIZE)?; + } + _ => {} + } + + match r.read(&mut probe) { + Ok(n) => { + cfg_select! { + no_global_oom_handling => { + // there is no way to recover from allocation failure here + // because the data has already been read. + buf.try_extend_from_slice_of_bytes(&probe[..n])?; + } + _ => { + // there is no way to recover from allocation failure here + // because the data has already been read. + buf.extend_from_slice(&probe[..n]); + } + } + return Ok(n); + } + Err(ref e) if e.is_interrupted() => continue, + Err(e) => return Err(e), + } + } + } + + // avoid inflating empty/small vecs before we have determined that there's anything to read + if (size_hint.is_none() || size_hint == Some(0)) && buf.capacity() - buf.len() < PROBE_SIZE { + let read = small_probe_read(r, buf)?; + + if read == 0 { + return Ok(0); + } + } + + loop { + if buf.spare_capacity_mut().len() < PROBE_SIZE && buf.capacity() == start_cap { + // The buffer might be an exact fit. Let's read into a probe buffer + // and see if it returns `Ok(0)`. If so, we've avoided an + // unnecessary doubling of the capacity. But if not, append the + // probe buffer to the primary buffer and let its capacity grow. + let read = small_probe_read(r, buf)?; + + if read == 0 { + return Ok(buf.len() - start_len); + } + + init_until = buf.len(); + // In the case of very short reads, continue to use the stack buffer + // until either we reach the end or we need to reallocate. + continue; + } + + // Avoid unnecessarily short reads by ensuring there's at least PROBE_SIZE space available. + // And assert that PROBE_SIZE is always at least large enough to fit any UTF-8 encoded code point. + const { assert!(PROBE_SIZE >= char::MAX_LEN_UTF8) } + if buf.spare_capacity_mut().len() < PROBE_SIZE { + buf.try_reserve(PROBE_SIZE)?; + // When reallocation occurs, we have to update init_until accordingly + // to re-calibrate how many bytes are actually initialized in the buffer + init_until = buf.len(); + } + + // We set a threshold of >PROBE_SIZE initialized yet unfilled bytes left in the + // spare buffer before determining that we need to initialize more bytes into + // the spare buffer + let buf_len = if init_until > buf.len() + PROBE_SIZE { + init_until - buf.len() + } else { + usize::min(max_read_size, buf.capacity() - buf.len()) + }; + let was_init = init_until >= buf.len() + buf_len; + + let mut spare = buf.spare_capacity_mut(); + spare = &mut spare[..buf_len]; + let mut read_buf: BorrowedBuf<'_, u8> = spare.into(); + + if was_init { + // SAFETY: These bytes were initialized but not filled in the previous loop + unsafe { read_buf.set_init() }; + } + + let mut cursor = read_buf.unfilled(); + let result = loop { + match r.read_buf(cursor.reborrow()) { + Err(e) if e.is_interrupted() => continue, + // Do not stop now in case of error: we might have received both data + // and an error + res => break res, + } + }; + + let bytes_read = cursor.written(); + let is_init = read_buf.is_init(); + + if is_init { + init_until = buf.len() + buf_len; + } + + // SAFETY: BorrowedBuf's invariants mean this much memory is initialized. + unsafe { + let new_len = bytes_read + buf.len(); + buf.set_len(new_len); + } + + // Now that all data is pushed to the vector, we can fail without data loss + result?; + + if bytes_read == 0 { + return Ok(buf.len() - start_len); + } + + // Use heuristics to determine the max read size if no initial size hint was provided + if size_hint.is_none() { + // The reader is returning short reads but it doesn't call ensure_init(). + // In that case we no longer need to restrict read sizes to avoid + // initialization costs. + // When reading from disk we usually don't get any short reads except at EOF. + // So we wait for at least 2 short reads before uncapping the read buffer; + // this helps with the Windows issue. + if !is_init { + max_read_size = usize::MAX; + } + // the spare buffer has initialized and read in `max_read_size` bytes. + // it's possible that we have more than `max_read_size` bytes to read + // left, so a larger buffer may be necessary to minimize the number of + // iterations of reading in bytes to the buffer + else if bytes_read == max_read_size { + max_read_size = max_read_size.saturating_mul(2); + } + } + } +} + +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +pub fn default_read_to_string( + r: &mut R, + buf: &mut String, + size_hint: Option, +) -> Result { + // Note that we do *not* call `r.read_to_end()` here. We are passing + // `&mut Vec` (the raw contents of `buf`) into the `read_to_end` + // method to fill it up. An arbitrary implementation could overwrite the + // entire contents of the vector, not just append to it (which is what + // we are expecting). + // + // To prevent extraneously checking the UTF-8-ness of the entire buffer + // we pass it to our hardcoded `default_read_to_end` implementation which + // we know is guaranteed to only read data into the end of the buffer. + unsafe { append_to_string(buf, |b| default_read_to_end(r, b, size_hint)) } +} + +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +pub fn default_read_vectored(read: F, bufs: &mut [IoSliceMut<'_>]) -> Result +where + F: FnOnce(&mut [u8]) -> Result, +{ + let buf = bufs.iter_mut().find(|b| !b.is_empty()).map_or(&mut [][..], |b| &mut **b); + read(buf) +} + +pub(super) fn default_read_exact(this: &mut R, mut buf: &mut [u8]) -> Result<()> { + while !buf.is_empty() { + match this.read(buf) { + Ok(0) => break, + Ok(n) => { + buf = &mut buf[n..]; + } + Err(ref e) if e.is_interrupted() => {} + Err(e) => return Err(e), + } + } + if !buf.is_empty() { Err(Error::READ_EXACT_EOF) } else { Ok(()) } +} + +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +pub fn default_read_buf(read: F, mut cursor: BorrowedCursor<'_, u8>) -> Result<()> +where + F: FnOnce(&mut [u8]) -> Result, +{ + let n = read(cursor.ensure_init())?; + cursor.advance_checked(n); + Ok(()) +} + +pub(super) fn default_read_buf_exact( + this: &mut R, + mut cursor: BorrowedCursor<'_, u8>, +) -> Result<()> { + while cursor.capacity() > 0 { + let prev_written = cursor.written(); + match this.read_buf(cursor.reborrow()) { + Ok(()) => {} + Err(e) if e.is_interrupted() => continue, + Err(e) => return Err(e), + } + + if cursor.written() == prev_written { + return Err(Error::READ_EXACT_EOF); + } + } + + Ok(()) +} + +/// Trait for types that can be converted from a fixed-size byte array with a specified endianness +#[unstable(feature = "read_le_be_internals", reason = "internals", issue = "none")] +// Once we can use associated consts in the types of method parameters, rewrite this to have +// `from_le_bytes` and `from_be_bytes` methods, move it to `core`, and make it public. +pub impl(self) trait FromEndianBytes: Sized { + #[doc(hidden)] + fn read_le_from(r: &mut impl Read) -> Result; + + #[doc(hidden)] + fn read_be_from(r: &mut impl Read) -> Result; +} + +macro_rules! impl_from_endian_bytes { + ($($t:ty),*$(,)?) => {$( + #[unstable(feature = "read_le_be_internals", reason = "internals", issue = "none")] + impl FromEndianBytes for $t { + #[inline] + fn read_le_from(r: &mut impl Read) -> Result { + Ok(<$t>::from_le_bytes(r.read_array()?)) + } + + #[inline] + fn read_be_from(r: &mut impl Read) -> Result { + Ok(<$t>::from_be_bytes(r.read_array()?)) + } + } + )*}; +} + +impl_from_endian_bytes!(u8, u16, u32, u64, u128, usize, i8, i16, i32, i64, i128, isize, f32, f64); diff --git a/library/alloc/src/io/util.rs b/library/alloc/src/io/util.rs new file mode 100644 index 0000000000000..9bf5a56dd7157 --- /dev/null +++ b/library/alloc/src/io/util.rs @@ -0,0 +1,474 @@ +use core::cmp; + +use crate::io::{ + self, BorrowedBuf, BorrowedCursor, BufRead, Chain, Empty, IoSliceMut, Read, Repeat, Result, + SizeHint, Take, +}; +use crate::slice; +use crate::string::String; +use crate::vec::Vec; + +#[stable(feature = "rust1", since = "1.0.0")] +impl Read for Empty { + #[inline] + fn read(&mut self, _buf: &mut [u8]) -> io::Result { + Ok(0) + } + + #[inline] + fn read_buf(&mut self, _cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { + Ok(()) + } + + #[inline] + fn read_vectored(&mut self, _bufs: &mut [IoSliceMut<'_>]) -> io::Result { + Ok(0) + } + + #[inline] + fn is_read_vectored(&self) -> bool { + // Do not force `Chain` or `Chain` to use vectored + // reads, unless the other reader is vectored. + false + } + + #[inline] + fn read_exact(&mut self, buf: &mut [u8]) -> io::Result<()> { + if !buf.is_empty() { Err(io::Error::READ_EXACT_EOF) } else { Ok(()) } + } + + #[inline] + fn read_buf_exact(&mut self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { + if cursor.capacity() != 0 { Err(io::Error::READ_EXACT_EOF) } else { Ok(()) } + } + + #[inline] + fn read_to_end(&mut self, _buf: &mut Vec) -> io::Result { + Ok(0) + } + + #[inline] + fn read_to_string(&mut self, _buf: &mut String) -> io::Result { + Ok(0) + } +} + +#[stable(feature = "rust1", since = "1.0.0")] +impl BufRead for Empty { + #[inline] + fn fill_buf(&mut self) -> io::Result<&[u8]> { + Ok(&[]) + } + + #[inline] + fn consume(&mut self, _n: usize) {} + + #[inline] + fn has_data_left(&mut self) -> io::Result { + Ok(false) + } + + #[inline] + fn read_until(&mut self, _byte: u8, _buf: &mut Vec) -> io::Result { + Ok(0) + } + + #[inline] + fn skip_until(&mut self, _byte: u8) -> io::Result { + Ok(0) + } + + #[inline] + fn read_line(&mut self, _buf: &mut String) -> io::Result { + Ok(0) + } +} + +#[stable(feature = "rust1", since = "1.0.0")] +impl Read for Repeat { + #[inline] + fn read(&mut self, buf: &mut [u8]) -> io::Result { + buf.fill(self.byte); + Ok(buf.len()) + } + + #[inline] + fn read_exact(&mut self, buf: &mut [u8]) -> io::Result<()> { + buf.fill(self.byte); + Ok(()) + } + + #[inline] + fn read_buf(&mut self, mut buf: BorrowedCursor<'_, u8>) -> io::Result<()> { + // SAFETY: No uninit bytes are being written. + unsafe { buf.as_mut() }.write_filled(self.byte); + // SAFETY: the entire unfilled portion of buf has been initialized. + unsafe { buf.advance(buf.capacity()) }; + Ok(()) + } + + #[inline] + fn read_buf_exact(&mut self, buf: BorrowedCursor<'_, u8>) -> io::Result<()> { + self.read_buf(buf) + } + + /// This function is not supported by `io::Repeat`, because there's no end of its data + fn read_to_end(&mut self, _: &mut Vec) -> io::Result { + Err(io::Error::from(io::ErrorKind::OutOfMemory)) + } + + /// This function is not supported by `io::Repeat`, because there's no end of its data + fn read_to_string(&mut self, _: &mut String) -> io::Result { + Err(io::Error::from(io::ErrorKind::OutOfMemory)) + } + + #[inline] + fn read_vectored(&mut self, bufs: &mut [IoSliceMut<'_>]) -> io::Result { + let mut nwritten = 0; + for buf in bufs { + nwritten += self.read(buf)?; + } + Ok(nwritten) + } + + #[inline] + fn is_read_vectored(&self) -> bool { + true + } +} + +#[stable(feature = "rust1", since = "1.0.0")] +impl Read for Chain { + fn read(&mut self, buf: &mut [u8]) -> Result { + if !self.done_first { + match self.first.read(buf)? { + 0 if !buf.is_empty() => self.done_first = true, + n => return Ok(n), + } + } + self.second.read(buf) + } + + fn read_vectored(&mut self, bufs: &mut [IoSliceMut<'_>]) -> Result { + if !self.done_first { + match self.first.read_vectored(bufs)? { + 0 if bufs.iter().any(|b| !b.is_empty()) => self.done_first = true, + n => return Ok(n), + } + } + self.second.read_vectored(bufs) + } + + #[inline] + fn is_read_vectored(&self) -> bool { + self.first.is_read_vectored() || self.second.is_read_vectored() + } + + fn read_to_end(&mut self, buf: &mut Vec) -> Result { + let mut read = 0; + if !self.done_first { + read += self.first.read_to_end(buf)?; + self.done_first = true; + } + read += self.second.read_to_end(buf)?; + Ok(read) + } + + // We don't override `read_to_string` here because an UTF-8 sequence could + // be split between the two parts of the chain + + fn read_buf(&mut self, mut buf: BorrowedCursor<'_, u8>) -> Result<()> { + if buf.capacity() == 0 { + return Ok(()); + } + + if !self.done_first { + let old_len = buf.written(); + self.first.read_buf(buf.reborrow())?; + + if buf.written() != old_len { + return Ok(()); + } else { + self.done_first = true; + } + } + self.second.read_buf(buf) + } +} + +#[stable(feature = "chain_bufread", since = "1.9.0")] +impl BufRead for Chain { + fn fill_buf(&mut self) -> Result<&[u8]> { + if !self.done_first { + match self.first.fill_buf()? { + buf if buf.is_empty() => self.done_first = true, + buf => return Ok(buf), + } + } + self.second.fill_buf() + } + + fn consume(&mut self, amt: usize) { + if !self.done_first { self.first.consume(amt) } else { self.second.consume(amt) } + } + + fn read_until(&mut self, byte: u8, buf: &mut Vec) -> Result { + let mut read = 0; + if !self.done_first { + let n = self.first.read_until(byte, buf)?; + read += n; + + match buf.last() { + Some(b) if *b == byte && n != 0 => return Ok(read), + _ => self.done_first = true, + } + } + read += self.second.read_until(byte, buf)?; + Ok(read) + } + + // We don't override `read_line` here because an UTF-8 sequence could be + // split between the two parts of the chain +} + +#[stable(feature = "rust1", since = "1.0.0")] +impl Read for Take { + fn read(&mut self, buf: &mut [u8]) -> Result { + // Don't call into inner reader at all at EOF because it may still block + if self.limit == 0 { + return Ok(0); + } + + let max = cmp::min(buf.len() as u64, self.limit) as usize; + let n = self.inner.read(&mut buf[..max])?; + assert!(n as u64 <= self.limit, "number of read bytes exceeds limit"); + self.limit -= n as u64; + Ok(n) + } + + fn read_buf(&mut self, mut buf: BorrowedCursor<'_, u8>) -> Result<()> { + // Don't call into inner reader at all at EOF because it may still block + if self.limit == 0 { + return Ok(()); + } + + if self.limit < buf.capacity() as u64 { + // The condition above guarantees that `self.limit` fits in `usize`. + let limit = self.limit as usize; + + let is_init = buf.is_init(); + + // SAFETY: no uninit data is written to ibuf + let mut sliced_buf = BorrowedBuf::from(unsafe { &mut buf.as_mut()[..limit] }); + + if is_init { + // SAFETY: `sliced_buf` is a subslice of `buf`, so if `buf` was initialized then + // `sliced_buf` is. + unsafe { sliced_buf.set_init() }; + } + + let result = self.inner.read_buf(sliced_buf.unfilled()); + + let did_init_up_to_limit = sliced_buf.is_init(); + let filled = sliced_buf.len(); + + // sliced_buf must drop here + + // Avoid accidentally quadratic behaviour by initializing the whole + // cursor if only part of it was initialized. + if did_init_up_to_limit && !is_init { + // SAFETY: No uninit data will be written. + let unfilled_before_advance = unsafe { buf.as_mut() }; + + unfilled_before_advance[limit..].write_filled(0); + + // SAFETY: `unfilled_before_advance[..limit]` was initialized by `T::read_buf`, and + // `unfilled_before_advance[limit..]` was just initialized. + unsafe { buf.set_init() }; + } + + unsafe { + // SAFETY: filled bytes have been filled + buf.advance(filled); + } + + self.limit -= filled as u64; + + result + } else { + let written = buf.written(); + let result = self.inner.read_buf(buf.reborrow()); + self.limit -= (buf.written() - written) as u64; + result + } + } +} + +#[stable(feature = "rust1", since = "1.0.0")] +impl BufRead for Take { + fn fill_buf(&mut self) -> Result<&[u8]> { + // Don't call into inner reader at all at EOF because it may still block + if self.limit == 0 { + return Ok(&[]); + } + + let buf = self.inner.fill_buf()?; + let cap = cmp::min(buf.len() as u64, self.limit) as usize; + Ok(&buf[..cap]) + } + + fn consume(&mut self, amt: usize) { + // Don't let callers reset the limit by passing an overlarge value + let amt = cmp::min(amt as u64, self.limit) as usize; + self.limit -= amt as u64; + self.inner.consume(amt); + } +} + +/// An iterator over `u8` values of a reader. +/// +/// This struct is generally created by calling [`bytes`] on a reader. +/// Please see the documentation of [`bytes`] for more details. +/// +/// [`bytes`]: Read::bytes +#[stable(feature = "rust1", since = "1.0.0")] +#[derive(Debug)] +pub struct Bytes { + inner: R, +} + +#[stable(feature = "rust1", since = "1.0.0")] +impl Iterator for Bytes { + type Item = Result; + + // Not `#[inline]`. This function gets inlined even without it, but having + // the inline annotation can result in worse code generation. See #116785. + fn next(&mut self) -> Option> { + SpecReadByte::spec_read_byte(&mut self.inner) + } + + #[inline] + fn size_hint(&self) -> (usize, Option) { + SizeHint::size_hint(&self.inner) + } +} + +/// For the specialization of `Bytes::next`. +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +pub trait SpecReadByte { + fn spec_read_byte(&mut self) -> Option>; +} + +impl SpecReadByte for R +where + Self: Read, +{ + #[inline] + default fn spec_read_byte(&mut self) -> Option> { + inlined_slow_read_byte(self) + } +} + +/// Reads a single byte in a slow, generic way. This is used by the default +/// `spec_read_byte`. +#[inline] +fn inlined_slow_read_byte(reader: &mut R) -> Option> { + let mut byte = 0; + loop { + return match reader.read(slice::from_mut(&mut byte)) { + Ok(0) => None, + Ok(..) => Some(Ok(byte)), + Err(ref e) if e.is_interrupted() => continue, + Err(e) => Some(Err(e)), + }; + } +} + +// Used by `BufReader::spec_read_byte`, for which the `inline(never)` is +// important. +#[inline(never)] +pub(super) fn uninlined_slow_read_byte(reader: &mut R) -> Option> { + inlined_slow_read_byte(reader) +} + +pub(super) const fn bytes(inner: R) -> Bytes { + Bytes { inner } +} + +/// An iterator over the contents of an instance of `BufRead` split on a +/// particular byte. +/// +/// This struct is generally created by calling [`split`] on a `BufRead`. +/// Please see the documentation of [`split`] for more details. +/// +/// [`split`]: BufRead::split +#[stable(feature = "rust1", since = "1.0.0")] +#[derive(Debug)] +#[cfg_attr(not(test), rustc_diagnostic_item = "IoSplit")] +pub struct Split { + buf: B, + delim: u8, +} + +#[stable(feature = "rust1", since = "1.0.0")] +impl Iterator for Split { + type Item = Result>; + + fn next(&mut self) -> Option>> { + let mut buf = Vec::new(); + match self.buf.read_until(self.delim, &mut buf) { + Ok(0) => None, + Ok(_n) => { + if buf[buf.len() - 1] == self.delim { + buf.pop(); + } + Some(Ok(buf)) + } + Err(e) => Some(Err(e)), + } + } +} + +pub(super) const fn split(buf: B, delim: u8) -> Split { + Split { buf, delim } +} + +/// An iterator over the lines of an instance of [`BufRead`]. +/// +/// This struct is generally created by calling [`lines`] on a [`BufRead`]. +/// Please see the documentation of [`lines`] for more details. +/// +/// [`lines`]: BufRead::lines +#[stable(feature = "rust1", since = "1.0.0")] +#[derive(Debug)] +#[cfg_attr(not(test), rustc_diagnostic_item = "IoLines")] +pub struct Lines { + buf: B, +} + +#[stable(feature = "rust1", since = "1.0.0")] +impl Iterator for Lines { + type Item = Result; + + fn next(&mut self) -> Option> { + let mut buf = String::new(); + match self.buf.read_line(&mut buf) { + Ok(0) => None, + Ok(_n) => { + if buf.ends_with('\n') { + buf.pop(); + if buf.ends_with('\r') { + buf.pop(); + } + } + Some(Ok(buf)) + } + Err(e) => Some(Err(e)), + } + } +} + +pub(super) const fn lines(buf: B) -> Lines { + Lines { buf } +} diff --git a/library/alloc/src/lib.rs b/library/alloc/src/lib.rs index 2503faa0f923c..5c477ac798e4c 100644 --- a/library/alloc/src/lib.rs +++ b/library/alloc/src/lib.rs @@ -56,22 +56,26 @@ //! [`Rc`]: rc //! [`RefCell`]: core::cell +#![allow(unused_features)] #![allow(incomplete_features)] #![allow(unused_attributes)] #![stable(feature = "alloc", since = "1.36.0")] #![doc( html_playground_url = "https://play.rust-lang.org/", issue_tracker_base_url = "https://github.com/rust-lang/rust/issues/", - test(no_crate_inject, attr(allow(unused_variables), deny(warnings))) + test(no_crate_inject, attr(allow(unused_variables, duplicate_features), deny(warnings))) )] -#![doc(auto_cfg(hide(no_global_oom_handling, no_rc, no_sync, target_has_atomic = "ptr")))] +#![doc(auto_cfg( + hide(no_global_oom_handling, no_rc, no_sync), + hide(target_has_atomic, values("ptr")), +))] #![doc(rust_logo)] #![feature(rustdoc_internals)] #![no_std] #![needs_allocator] // Lints: #![deny(unsafe_op_in_unsafe_fn)] -#![deny(fuzzy_provenance_casts)] +#![deny(implicit_provenance_casts)] #![warn(deprecated_in_future)] #![warn(missing_debug_implementations)] #![warn(missing_docs)] @@ -90,12 +94,13 @@ #![feature(allocator_api)] #![feature(array_into_iter_constructors)] #![feature(ascii_char)] -#![feature(assert_matches)] #![feature(async_fn_traits)] #![feature(async_iterator)] -#![feature(box_vec_non_null)] +#![feature(borrowed_buf_init)] #![feature(bstr)] #![feature(bstr_internals)] +#![feature(can_vector)] +#![feature(case_ignorable)] #![feature(cast_maybe_uninit)] #![feature(cell_get_cloned)] #![feature(char_internals)] @@ -106,15 +111,25 @@ #![feature(const_convert)] #![feature(const_default)] #![feature(const_destruct)] +#![feature(const_drop_in_place)] #![feature(const_eval_select)] #![feature(const_heap)] +#![feature(const_index)] #![feature(const_option_ops)] +#![feature(const_result_trait_fn)] #![feature(const_try)] #![feature(copied_into_inner)] #![feature(core_intrinsics)] +#![feature(core_io)] +#![feature(core_io_borrowed_buf)] +#![feature(core_io_internals)] +#![feature(cursor_split)] #![feature(deprecated_suggestion)] #![feature(deref_pure_trait)] +#![feature(derive_const)] +#![feature(diagnostic_on_move)] #![feature(dispatch_from_dyn)] +#![feature(drop_guard)] #![feature(ergonomic_clones)] #![feature(error_generic_member_access)] #![feature(exact_size_is_empty)] @@ -128,21 +143,29 @@ #![feature(generic_atomic)] #![feature(hasher_prefixfree_extras)] #![feature(inplace_iteration)] +#![feature(io_const_error)] +#![feature(io_const_error_internals)] +#![feature(io_slice_as_bytes)] #![feature(iter_advance_by)] #![feature(iter_next_chunk)] -#![feature(layout_for_ptr)] #![feature(legacy_receiver_trait)] #![feature(likely_unlikely)] #![feature(local_waker)] +#![feature(maybe_uninit_array_assume_init)] +#![feature(maybe_uninit_fill)] #![feature(maybe_uninit_uninit_array_transpose)] #![feature(panic_internals)] #![feature(pattern)] #![feature(pin_coerce_unsized_trait)] #![feature(ptr_alignment_type)] +#![feature(ptr_cast_slice)] #![feature(ptr_internals)] #![feature(ptr_metadata)] +#![feature(raw_os_error_ty)] #![feature(rev_into_inner)] +#![feature(seek_stream_len)] #![feature(set_ptr_value)] +#![feature(share_trait)] #![feature(sized_type_properties)] #![feature(slice_from_ptr_range)] #![feature(slice_index_methods)] @@ -150,8 +173,8 @@ #![feature(slice_ptr_get)] #![feature(slice_range)] #![feature(std_internals)] -#![feature(str_internals)] #![feature(temporary_niche_types)] +#![feature(titlecase)] #![feature(transmutability)] #![feature(trivial_clone)] #![feature(trusted_fused)] @@ -160,12 +183,12 @@ #![feature(try_blocks)] #![feature(try_trait_v2)] #![feature(try_trait_v2_residual)] -#![feature(try_with_capacity)] #![feature(tuple_trait)] #![feature(ub_checks)] #![feature(unicode_internals)] #![feature(unsize)] #![feature(unwrap_infallible)] +#![feature(write_all_vectored)] #![feature(wtf8_internals)] // tidy-alphabetical-end // @@ -174,14 +197,14 @@ #![feature(allocator_internals)] #![feature(allow_internal_unstable)] #![feature(cfg_sanitize)] +#![feature(const_closures)] #![feature(const_precise_live_drops)] #![feature(const_trait_impl)] #![feature(coroutine_trait)] #![feature(decl_macro)] -#![feature(derive_const)] #![feature(dropck_eyepatch)] #![feature(fundamental)] -#![feature(hashmap_internals)] +#![feature(impl_restriction)] #![feature(intrinsics)] #![feature(lang_items)] #![feature(min_specialization)] @@ -189,7 +212,6 @@ #![feature(negative_impls)] #![feature(never_type)] #![feature(optimize_attribute)] -#![feature(rustc_allow_const_fn_unstable)] #![feature(rustc_attrs)] #![feature(slice_internals)] #![feature(staged_api)] @@ -203,6 +225,7 @@ // // Rustdoc features: #![feature(doc_cfg)] +#![feature(doc_notable_trait)] // Technically, this is a bug in rustdoc: rustdoc sees the documentation on `#[lang = slice_alloc]` // blocks is for `&[T]`, which also has documentation using this feature in `core`, and gets mad // that the feature-gate isn't enabled. Ideally, it wouldn't check for the feature gate for docs @@ -231,6 +254,9 @@ pub mod collections; #[cfg(all(not(no_rc), not(no_sync), not(no_global_oom_handling)))] pub mod ffi; pub mod fmt; +pub mod intrinsics; +#[unstable(feature = "alloc_io", issue = "154046")] +pub mod io; #[cfg(not(no_rc))] pub mod rc; pub mod slice; diff --git a/library/alloc/src/macros.rs b/library/alloc/src/macros.rs index 1e6e2ae8c3675..d93e279df7cfb 100644 --- a/library/alloc/src/macros.rs +++ b/library/alloc/src/macros.rs @@ -39,6 +39,7 @@ #[stable(feature = "rust1", since = "1.0.0")] #[rustc_diagnostic_item = "vec_macro"] #[allow_internal_unstable(rustc_attrs, liballoc_internals)] +#[rustc_diagnostic_opaque] macro_rules! vec { () => ( $crate::vec::Vec::new() @@ -47,10 +48,16 @@ macro_rules! vec { $crate::vec::from_elem($elem, $n) ); ($($x:expr),+ $(,)?) => ( - <[_]>::into_vec( - // Using the intrinsic produces a dramatic improvement in stack usage for - // unoptimized programs using this code path to construct large Vecs. - $crate::boxed::box_new([$($x),+]) + // Using `write_box_via_move` produces a dramatic improvement in stack usage for unoptimized + // programs using this code path to construct large Vecs. We can't use `write_via_move` + // because this entire invocation has to remain a call chain without `let` bindings, or else + // inference and temporary lifetimes change and things break (see `vec-macro-rvalue-scope`, + // `vec-macro-coercions`, and `autoderef-vec-box-fn-36786` tests). + // + // `box_assume_init_into_vec_unsafe` isn't actually safe but the way we use it here is. We + // can't use an unsafe block as that would also wrap `$x`. + $crate::boxed::box_assume_init_into_vec_unsafe( + $crate::intrinsics::write_box_via_move($crate::boxed::Box::new_uninit(), [$($x),+]) ) ); } @@ -102,6 +109,7 @@ macro_rules! vec { #[stable(feature = "rust1", since = "1.0.0")] #[allow_internal_unstable(hint_must_use, liballoc_internals)] #[rustc_diagnostic_item = "format_macro"] +#[rustc_diagnostic_opaque] macro_rules! format { ($($arg:tt)*) => { $crate::__export::must_use({ diff --git a/library/alloc/src/raw_vec/mod.rs b/library/alloc/src/raw_vec/mod.rs index ff996ba93cd7f..5d4ad3ac4bf98 100644 --- a/library/alloc/src/raw_vec/mod.rs +++ b/library/alloc/src/raw_vec/mod.rs @@ -5,8 +5,8 @@ // run the tests. See the comment there for an explanation why this is the case. use core::marker::{Destruct, PhantomData}; -use core::mem::{ManuallyDrop, MaybeUninit, SizedTypeProperties}; -use core::ptr::{self, Alignment, NonNull, Unique}; +use core::mem::{Alignment, ManuallyDrop, MaybeUninit, SizedTypeProperties}; +use core::ptr::{self, NonNull, Unique}; use core::{cmp, hint}; #[cfg(not(no_global_oom_handling))] @@ -43,7 +43,7 @@ const ZERO_CAP: Cap = unsafe { Cap::new_unchecked(0) }; /// `Cap(cap)`, except if `T` is a ZST then `Cap::ZERO`. /// /// # Safety: cap must be <= `isize::MAX`. -unsafe fn new_cap(cap: usize) -> Cap { +const unsafe fn new_cap(cap: usize) -> Cap { if T::IS_ZST { ZERO_CAP } else { unsafe { Cap::new_unchecked(cap) } } } @@ -244,7 +244,7 @@ impl RawVec { let me = ManuallyDrop::new(self); unsafe { - let slice = ptr::slice_from_raw_parts_mut(me.ptr() as *mut MaybeUninit, len); + let slice = me.ptr().cast::>().cast_slice(len); Box::from_raw_in(slice, ptr::read(&me.inner.alloc)) } } @@ -260,7 +260,7 @@ impl RawVec { /// If the `ptr` and `capacity` come from a `RawVec` created via `alloc`, then this is /// guaranteed. #[inline] - pub(crate) unsafe fn from_raw_parts_in(ptr: *mut T, capacity: usize, alloc: A) -> Self { + pub(crate) const unsafe fn from_raw_parts_in(ptr: *mut T, capacity: usize, alloc: A) -> Self { // SAFETY: Precondition passed to the caller unsafe { let ptr = ptr.cast(); @@ -278,7 +278,8 @@ impl RawVec { /// /// See [`RawVec::from_raw_parts_in`]. #[inline] - pub(crate) unsafe fn from_nonnull_in(ptr: NonNull, capacity: usize, alloc: A) -> Self { + #[rustc_const_unstable(feature = "const_heap", issue = "79597")] + pub(crate) const unsafe fn from_nonnull_in(ptr: NonNull, capacity: usize, alloc: A) -> Self { // SAFETY: Precondition passed to the caller unsafe { let ptr = ptr.cast(); @@ -310,7 +311,7 @@ impl RawVec { /// Returns a shared reference to the allocator backing this `RawVec`. #[inline] - pub(crate) fn allocator(&self) -> &A { + pub(crate) const fn allocator(&self) -> &A { self.inner.allocator() } @@ -399,9 +400,25 @@ impl RawVec { // SAFETY: All calls on self.inner pass T::LAYOUT as the elem_layout unsafe { self.inner.shrink_to_fit(cap, T::LAYOUT) } } + + /// Shrinks the buffer down to the specified capacity. If the given amount + /// is 0, actually completely deallocates. + /// + /// # Errors + /// + /// This function returns an error if the allocator cannot shrink the allocation. + /// + /// # Panics + /// + /// Panics if the given amount is *larger* than the current capacity. + #[inline] + pub(crate) fn try_shrink_to_fit(&mut self, cap: usize) -> Result<(), TryReserveError> { + unsafe { self.inner.try_shrink_to_fit(cap, T::LAYOUT) } + } } -unsafe impl<#[may_dangle] T, A: Allocator> Drop for RawVec { +#[rustc_const_unstable(feature = "const_heap", issue = "79597")] +const unsafe impl<#[may_dangle] T, A: [const] Allocator + [const] Destruct> Drop for RawVec { /// Frees the memory owned by the `RawVec` *without* trying to drop its contents. fn drop(&mut self) { // SAFETY: We are in a Drop impl, self.inner will not be used again. @@ -543,18 +560,14 @@ const impl RawVecInner { self.alloc.allocate(new_layout) }; - // FIXME(const-hack): switch back to `map_err` - match memory { - Ok(memory) => Ok(memory), - Err(_) => Err(AllocError { layout: new_layout, non_exhaustive: () }.into()), - } + memory.map_err(const |_| AllocError { layout: new_layout, non_exhaustive: () }.into()) } } impl RawVecInner { #[inline] const fn new_in(alloc: A, align: Alignment) -> Self { - let ptr = Unique::from_non_null(NonNull::without_provenance(align.as_nonzero())); + let ptr = Unique::from_non_null(NonNull::without_provenance(align.as_nonzero_usize())); // `cap: 0` means "unallocated". zero-sized types are ignored. Self { ptr, cap: ZERO_CAP, alloc } } @@ -578,12 +591,13 @@ impl RawVecInner { } #[inline] - unsafe fn from_raw_parts_in(ptr: *mut u8, cap: Cap, alloc: A) -> Self { + const unsafe fn from_raw_parts_in(ptr: *mut u8, cap: Cap, alloc: A) -> Self { Self { ptr: unsafe { Unique::new_unchecked(ptr) }, cap, alloc } } #[inline] - unsafe fn from_nonnull_in(ptr: NonNull, cap: Cap, alloc: A) -> Self { + #[rustc_const_unstable(feature = "const_heap", issue = "79597")] + const unsafe fn from_nonnull_in(ptr: NonNull, cap: Cap, alloc: A) -> Self { Self { ptr: Unique::from(ptr), cap, alloc } } @@ -603,7 +617,7 @@ impl RawVecInner { } #[inline] - fn allocator(&self) -> &A { + const fn allocator(&self) -> &A { &self.alloc } @@ -731,6 +745,20 @@ impl RawVecInner { } } + /// # Safety + /// + /// - `elem_layout` must be valid for `self`, i.e. it must be the same `elem_layout` used to + /// initially construct `self` + /// - `elem_layout`'s size must be a multiple of its alignment + /// - `cap` must be less than or equal to `self.capacity(elem_layout.size())` + unsafe fn try_shrink_to_fit( + &mut self, + cap: usize, + elem_layout: Layout, + ) -> Result<(), TryReserveError> { + unsafe { self.shrink(cap, elem_layout) } + } + #[inline] const fn needs_to_grow(&self, len: usize, additional: usize, elem_layout: Layout) -> bool { additional > self.capacity(elem_layout.size()).wrapping_sub(len) @@ -778,7 +806,6 @@ impl RawVecInner { /// initially construct `self` /// - `elem_layout`'s size must be a multiple of its alignment /// - `cap` must be less than or equal to `self.capacity(elem_layout.size())` - #[cfg(not(no_global_oom_handling))] #[inline] unsafe fn shrink(&mut self, cap: usize, elem_layout: Layout) -> Result<(), TryReserveError> { assert!(cap <= self.capacity(elem_layout.size()), "Tried to shrink to a larger capacity"); @@ -796,7 +823,6 @@ impl RawVecInner { /// /// # Safety /// `cap <= self.capacity()` - #[cfg(not(no_global_oom_handling))] unsafe fn shrink_unchecked( &mut self, cap: usize, @@ -832,7 +858,10 @@ impl RawVecInner { } Ok(()) } +} +#[rustc_const_unstable(feature = "const_heap", issue = "79597")] +const impl RawVecInner { /// # Safety /// /// This function deallocates the owned allocation, but does not update `ptr` or `cap` to @@ -869,9 +898,5 @@ const fn layout_array(cap: usize, elem_layout: Layout) -> Result Ok(layout), - Err(_) => Err(CapacityOverflow.into()), - } + elem_layout.repeat_packed(cap).map_err(const |_| CapacityOverflow.into()) } diff --git a/library/alloc/src/rc.rs b/library/alloc/src/rc.rs index cec41524325e0..3655ee327bec2 100644 --- a/library/alloc/src/rc.rs +++ b/library/alloc/src/rc.rs @@ -245,14 +245,14 @@ use core::any::Any; use core::cell::{Cell, CloneFromCell}; #[cfg(not(no_global_oom_handling))] use core::clone::TrivialClone; -use core::clone::{CloneToUninit, UseCloned}; +use core::clone::{CloneToUninit, Share, UseCloned}; use core::cmp::Ordering; use core::hash::{Hash, Hasher}; use core::intrinsics::abort; #[cfg(not(no_global_oom_handling))] use core::iter; use core::marker::{PhantomData, Unsize}; -use core::mem::{self, ManuallyDrop}; +use core::mem::{self, Alignment, ManuallyDrop}; use core::num::NonZeroUsize; use core::ops::{CoerceUnsized, Deref, DerefMut, DerefPure, DispatchFromDyn, LegacyReceiver}; #[cfg(not(no_global_oom_handling))] @@ -260,15 +260,15 @@ use core::ops::{Residual, Try}; use core::panic::{RefUnwindSafe, UnwindSafe}; #[cfg(not(no_global_oom_handling))] use core::pin::Pin; -use core::pin::PinCoerceUnsized; -use core::ptr::{self, Alignment, NonNull, drop_in_place}; +use core::pin::PinSafePointer; +use core::ptr::{self, NonNull, drop_in_place}; #[cfg(not(no_global_oom_handling))] use core::slice::from_raw_parts_mut; use core::{borrow, fmt, hint}; #[cfg(not(no_global_oom_handling))] use crate::alloc::handle_alloc_error; -use crate::alloc::{AllocError, Allocator, Global, Layout}; +use crate::alloc::{AllocError, Allocator, AllocatorClone, Global, Layout}; use crate::borrow::{Cow, ToOwned}; use crate::boxed::Box; #[cfg(not(no_global_oom_handling))] @@ -294,7 +294,11 @@ fn rc_inner_layout_for_value_layout(layout: Layout) -> Layout { // Previously, layout was calculated on the expression // `&*(ptr as *const RcInner)`, but this created a misaligned // reference (see #54908). - Layout::new::>().extend(layout).unwrap().0.pad_to_align() + Layout::new::>() + .extend(layout) + .unwrap_or_else(|_| panic!("capacity overflow")) + .0 + .pad_to_align() } /// A single-threaded reference-counting pointer. 'Rc' stands for 'Reference @@ -311,6 +315,12 @@ fn rc_inner_layout_for_value_layout(layout: Layout) -> Layout { #[rustc_diagnostic_item = "Rc"] #[stable(feature = "rust1", since = "1.0.0")] #[rustc_insignificant_dtor] +#[diagnostic::on_move( + message = "the type `{Self}` does not implement `Copy`", + label = "this move could be avoided by cloning the original `{Self}`, which is inexpensive", + note = "consider using `Rc::clone`" +)] + pub struct Rc< T: ?Sized, #[unstable(feature = "allocator_api", issue = "32838")] A: Allocator = Global, @@ -332,9 +342,12 @@ impl !Send for Rc {} impl !Sync for Rc {} #[stable(feature = "catch_unwind", since = "1.9.0")] -impl UnwindSafe for Rc {} +impl UnwindSafe for Rc {} #[stable(feature = "rc_ref_unwind_safe", since = "1.58.0")] -impl RefUnwindSafe for Rc {} +impl RefUnwindSafe + for Rc +{ +} #[unstable(feature = "coerce_unsized", issue = "18598")] impl, U: ?Sized, A: Allocator> CoerceUnsized> for Rc {} @@ -737,6 +750,7 @@ impl Rc { /// /// ``` /// #![feature(allocator_api)] + /// /// use std::rc::Rc; /// use std::alloc::System; /// @@ -887,7 +901,7 @@ impl Rc { // otherwise. let data = data_fn(&weak); - let strong = unsafe { + unsafe { let inner = init_ptr.as_ptr(); ptr::write(&raw mut (*inner).value, data); @@ -902,9 +916,7 @@ impl Rc { let alloc = weak.into_raw_with_allocator().1; Rc::from_inner_in(init_ptr, alloc) - }; - - strong + } } /// Constructs a new `Rc` in the provided allocator, returning an error if the allocation @@ -1153,33 +1165,10 @@ impl Rc<[T]> { Rc::from_ptr(Rc::allocate_for_layout( Layout::array::(len).unwrap(), |layout| Global.allocate_zeroed(layout), - |mem| { - ptr::slice_from_raw_parts_mut(mem.cast::(), len) - as *mut RcInner<[mem::MaybeUninit]> - }, + |mem| mem.cast::().cast_slice(len) as *mut RcInner<[mem::MaybeUninit]>, )) } } - - /// Converts the reference-counted slice into a reference-counted array. - /// - /// This operation does not reallocate; the underlying array of the slice is simply reinterpreted as an array type. - /// - /// If `N` is not exactly equal to the length of `self`, then this method returns `None`. - #[unstable(feature = "alloc_slice_into_array", issue = "148082")] - #[inline] - #[must_use] - pub fn into_array(self) -> Option> { - if self.len() == N { - let ptr = Self::into_raw(self) as *const [T; N]; - - // SAFETY: The underlying array of a slice has the exact same layout as an actual array `[T; N]` if `N` is equal to the slice's length. - let me = unsafe { Rc::from_raw(ptr) }; - Some(me) - } else { - None - } - } } impl Rc<[T], A> { @@ -1244,15 +1233,46 @@ impl Rc<[T], A> { Rc::allocate_for_layout( Layout::array::(len).unwrap(), |layout| alloc.allocate_zeroed(layout), - |mem| { - ptr::slice_from_raw_parts_mut(mem.cast::(), len) - as *mut RcInner<[mem::MaybeUninit]> - }, + |mem| mem.cast::().cast_slice(len) as *mut RcInner<[mem::MaybeUninit]>, ), alloc, ) } } + + /// Converts the reference-counted slice into a reference-counted array. + /// + /// This operation does not reallocate; the underlying array of the slice is simply reinterpreted as an array type. + /// + /// # Errors + /// + /// Returns the original `Rc<[T]>` in the `Err` variant if `self.len()` does not equal `N`. + /// + /// # Examples + /// + /// ``` + /// #![feature(alloc_slice_into_array)] + /// use std::rc::Rc; + /// + /// let rc_slice: Rc<[i32]> = Rc::new([1, 2, 3]); + /// + /// let rc_array: Rc<[i32; 3]> = rc_slice.into_array().unwrap(); + /// ``` + #[unstable(feature = "alloc_slice_into_array", issue = "148082")] + #[inline] + #[must_use] + pub fn into_array(self) -> Result, Self> { + if self.len() == N { + let (ptr, alloc) = Self::into_raw_with_allocator(self); + let ptr = ptr as *const [T; N]; + + // SAFETY: The underlying array of a slice has the exact same layout as an actual array `[T; N]` if `N` is equal to the slice's length. + let me = unsafe { Rc::from_raw_in(ptr, alloc) }; + Ok(me) + } else { + Err(self) + } + } } impl Rc, A> { @@ -1347,14 +1367,12 @@ impl Rc { let mut in_progress: UniqueRcUninit = UniqueRcUninit::new(value, alloc); // Initialize with clone of value. - let initialized_clone = unsafe { + unsafe { // Clone. If the clone panics, `in_progress` will be dropped and clean up. value.clone_to_uninit(in_progress.data_ptr().cast()); // Cast type of pointer, now that it is initialized. in_progress.into_rc() - }; - - initialized_clone + } } /// Constructs a new `Rc` with a clone of `value` in the provided allocator, returning an error if allocation fails @@ -1430,29 +1448,32 @@ impl Rc { /// Constructs an `Rc` from a raw pointer. /// /// The raw pointer must have been previously returned by a call to - /// [`Rc::into_raw`][into_raw] with the following requirements: + /// [`Rc::into_raw`][into_raw] or [`Rc::into_raw_with_allocator`][into_raw_with_allocator]. /// + /// # Safety + /// + /// * Creating a `Rc` from a pointer other than one returned from + /// [`Rc::into_raw`][into_raw] or [`Rc::into_raw_with_allocator`][into_raw_with_allocator] + /// is undefined behavior. /// * If `U` is sized, it must have the same size and alignment as `T`. This /// is trivially true if `U` is `T`. /// * If `U` is unsized, its data pointer must have the same size and /// alignment as `T`. This is trivially true if `Rc` was constructed /// through `Rc` and then converted to `Rc` through an [unsized /// coercion]. - /// - /// Note that if `U` or `U`'s data pointer is not `T` but has the same size - /// and alignment, this is basically like transmuting references of - /// different types. See [`mem::transmute`][transmute] for more information - /// on what restrictions apply in this case. - /// - /// The raw pointer must point to a block of memory allocated by the global allocator - /// - /// The user of `from_raw` has to make sure a specific value of `T` is only - /// dropped once. + /// * Note that if `U` or `U`'s data pointer is not `T` but has the same size + /// and alignment, this is basically like transmuting references of + /// different types. See [`mem::transmute`][transmute] for more information + /// on what restrictions apply in this case. + /// * The raw pointer must point to a block of memory allocated by the global allocator + /// * The user of `from_raw` has to make sure a specific value of `T` is only + /// dropped once. /// /// This function is unsafe because improper use may lead to memory unsafety, /// even if the returned `Rc` is never accessed. /// /// [into_raw]: Rc::into_raw + /// [into_raw_with_allocator]: Rc::into_raw_with_allocator /// [transmute]: core::mem::transmute /// [unsized coercion]: https://doc.rust-lang.org/reference/type-coercions.html#unsized-coercions /// @@ -1523,14 +1544,12 @@ impl Rc { /// /// # Safety /// - /// The pointer must have been obtained through `Rc::into_raw` and must satisfy the - /// same layout requirements specified in [`Rc::from_raw_in`][from_raw_in]. + /// The pointer must have been obtained through [`Rc::into_raw`] and must satisfy the + /// same layout requirements specified in [`Rc::from_raw_in`]. /// The associated `Rc` instance must be valid (i.e. the strong count must be at /// least 1) for the duration of this method, and `ptr` must point to a block of memory /// allocated by the global allocator. /// - /// [from_raw_in]: Rc::from_raw_in - /// /// # Examples /// /// ``` @@ -1559,7 +1578,7 @@ impl Rc { /// /// # Safety /// - /// The pointer must have been obtained through `Rc::into_raw`and must satisfy the + /// The pointer must have been obtained through `Rc::into_raw` and must satisfy the /// same layout requirements specified in [`Rc::from_raw_in`][from_raw_in]. /// The associated `Rc` instance must be valid (i.e. the strong count must be at /// least 1) when invoking this method, and `ptr` must point to a block of memory @@ -1662,29 +1681,32 @@ impl Rc { /// Constructs an `Rc` from a raw pointer in the provided allocator. /// /// The raw pointer must have been previously returned by a call to [`Rc::into_raw`][into_raw] with the following requirements: + /// A>::into_raw`][into_raw] or [`Rc::into_raw_with_allocator`][into_raw_with_allocator]. /// + /// # Safety + /// + /// * Creating a `Rc` from a pointer other than one returned from + /// [`Rc::into_raw`][into_raw] or [`Rc::into_raw_with_allocator`][into_raw_with_allocator] + /// is undefined behavior. /// * If `U` is sized, it must have the same size and alignment as `T`. This /// is trivially true if `U` is `T`. /// * If `U` is unsized, its data pointer must have the same size and - /// alignment as `T`. This is trivially true if `Rc` was constructed - /// through `Rc` and then converted to `Rc` through an [unsized + /// alignment as `T`. This is trivially true if `Rc` was constructed + /// through `Rc` and then converted to `Rc` through an [unsized /// coercion]. - /// - /// Note that if `U` or `U`'s data pointer is not `T` but has the same size - /// and alignment, this is basically like transmuting references of - /// different types. See [`mem::transmute`][transmute] for more information - /// on what restrictions apply in this case. - /// - /// The raw pointer must point to a block of memory allocated by `alloc` - /// - /// The user of `from_raw` has to make sure a specific value of `T` is only - /// dropped once. + /// * Note that if `U` or `U`'s data pointer is not `T` but has the same size + /// and alignment, this is basically like transmuting references of + /// different types. See [`mem::transmute`][transmute] for more information + /// on what restrictions apply in this case. + /// * The raw pointer must point to a block of memory allocated by `alloc` + /// * The user of `from_raw` has to make sure a specific value of `T` is only + /// dropped once. /// /// This function is unsafe because improper use may lead to memory unsafety, - /// even if the returned `Rc` is never accessed. + /// even if the returned `Rc` is never accessed. /// /// [into_raw]: Rc::into_raw + /// [into_raw_with_allocator]: Rc::into_raw_with_allocator /// [transmute]: core::mem::transmute /// [unsized coercion]: https://doc.rust-lang.org/reference/type-coercions.html#unsized-coercions /// @@ -1752,7 +1774,7 @@ impl Rc { #[stable(feature = "rc_weak", since = "1.4.0")] pub fn downgrade(this: &Self) -> Weak where - A: Clone, + A: AllocatorClone, { this.inner().inc_weak(); // Make sure we do not create a dangling Weak @@ -1833,7 +1855,7 @@ impl Rc { #[unstable(feature = "allocator_api", issue = "32838")] pub unsafe fn increment_strong_count_in(ptr: *const T, alloc: A) where - A: Clone, + A: AllocatorClone, { // Retain Rc, but don't touch refcount by wrapping in ManuallyDrop let rc = unsafe { mem::ManuallyDrop::new(Rc::::from_raw_in(ptr, alloc)) }; @@ -2009,7 +2031,7 @@ impl Rc { } #[cfg(not(no_global_oom_handling))] -impl Rc { +impl Rc { /// Makes a mutable reference into the given `Rc`. /// /// If there are other `Rc` pointers to the same allocation, then `make_mut` will @@ -2071,8 +2093,6 @@ impl Rc { } else if Rc::weak_count(this) != 0 { // Can just steal the data, all that's left is Weaks - // We don't need panic-protection like the above branch does, but we might as well - // use the same mechanism. let mut in_progress: UniqueRcUninit = UniqueRcUninit::new(&**this, this.alloc.clone()); unsafe { @@ -2085,10 +2105,18 @@ impl Rc { size_of_val, ); + // This leaves us with 0 strong refs, so the data has + // effectively been moved to the new rc. this.inner().dec_strong(); + // Remove implicit strong-weak ref (no need to craft a fake // Weak here -- we know other Weaks can clean up for us) this.inner().dec_weak(); + + // Last chance to not accidentally forget the allocator. + // Only drop at the end of the scope to avoid panics. + let _alloc = ptr::read(&this.alloc); + // Replace `this` with newly constructed Rc that has the moved data. ptr::write(this, in_progress.into_rc()); } @@ -2284,7 +2312,7 @@ impl Rc { // Free the allocation without dropping its contents let (bptr, alloc) = Box::into_raw_with_allocator(src); - let src = Box::from_raw_in(bptr as *mut mem::ManuallyDrop, alloc.by_ref()); + let src = Box::from_raw_in(bptr as *mut mem::ManuallyDrop, &alloc); drop(src); Self::from_ptr_in(ptr, alloc) @@ -2300,7 +2328,7 @@ impl Rc<[T]> { Self::allocate_for_layout( Layout::array::(len).unwrap(), |layout| Global.allocate(layout), - |mem| ptr::slice_from_raw_parts_mut(mem.cast::(), len) as *mut RcInner<[T]>, + |mem| mem.cast::().cast_slice(len) as *mut RcInner<[T]>, ) } } @@ -2377,7 +2405,7 @@ impl Rc<[T], A> { Rc::<[T]>::allocate_for_layout( Layout::array::(len).unwrap(), |layout| alloc.allocate(layout), - |mem| ptr::slice_from_raw_parts_mut(mem.cast::(), len) as *mut RcInner<[T]>, + |mem| mem.cast::().cast_slice(len) as *mut RcInner<[T]>, ) } } @@ -2417,15 +2445,19 @@ impl Deref for Rc { } } +// The API of this pointer type enforces that if the `T` is pinned, then *all* +// clones of this `Rc` are wrapped as `Pin>`. Since an `&Rc` could +// be used to obtain an `Rc` that is not wrapped in `Pin` (and later used +// with `Rc::get_mut`), this means that this type treats `&Rc` as evidence +// that the `T` is not pinned. The implementations of various traits are written +// accordingly. Since this type is not fundamental, downstream crates cannot +// provide malicious implementations of any of the traits relevant for `Pin`. #[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -unsafe impl PinCoerceUnsized for Rc {} +unsafe impl PinSafePointer for Rc {} //#[unstable(feature = "unique_rc_arc", issue = "112566")] #[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -unsafe impl PinCoerceUnsized for UniqueRc {} - -#[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -unsafe impl PinCoerceUnsized for Weak {} +unsafe impl PinSafePointer for UniqueRc {} #[unstable(feature = "deref_pure_trait", issue = "87121")] unsafe impl DerefPure for Rc {} @@ -2476,7 +2508,7 @@ unsafe impl<#[may_dangle] T: ?Sized, A: Allocator> Drop for Rc { } #[stable(feature = "rust1", since = "1.0.0")] -impl Clone for Rc { +impl Clone for Rc { /// Makes a clone of the `Rc` pointer. /// /// This creates another pointer to the same allocation, increasing the @@ -2501,7 +2533,10 @@ impl Clone for Rc { } #[unstable(feature = "ergonomic_clones", issue = "132290")] -impl UseCloned for Rc {} +impl UseCloned for Rc {} + +#[unstable(feature = "share_trait", issue = "156756")] +impl Share for Rc {} #[cfg(not(no_global_oom_handling))] #[stable(feature = "rust1", since = "1.0.0")] @@ -2590,10 +2625,10 @@ impl RcEqIdent for Rc { } // Hack to allow specializing on `Eq` even though `Eq` has a method. -#[rustc_unsafe_specialization_marker] +#[unsafe(rustc_allow_lifetime_dependent_specialization)] pub(crate) trait MarkerEq: PartialEq {} -impl MarkerEq for T {} +impl MarkerEq for T {} /// We're doing this specialization here, and not as a more general optimization on `&T`, because it /// would otherwise add a cost to all equality checks on refs. We assume that `Rc`s are used to @@ -2606,12 +2641,12 @@ impl MarkerEq for T {} impl RcEqIdent for Rc { #[inline] fn eq(&self, other: &Rc) -> bool { - Rc::ptr_eq(self, other) || **self == **other + ptr::eq(self.ptr.as_ptr(), other.ptr.as_ptr()) || **self == **other } #[inline] fn ne(&self, other: &Rc) -> bool { - !Rc::ptr_eq(self, other) && **self != **other + !ptr::eq(self.ptr.as_ptr(), other.ptr.as_ptr()) && **self != **other } } @@ -2970,7 +3005,7 @@ impl From> for Rc { #[cfg(not(no_global_oom_handling))] #[stable(feature = "shared_from_slice", since = "1.21.0")] -impl From> for Rc<[T], A> { +impl From> for Rc<[T], A> { /// Allocates a reference-counted slice and moves `v`'s items into it. /// /// # Example @@ -2984,7 +3019,7 @@ impl From> for Rc<[T], A> { #[inline] fn from(v: Vec) -> Rc<[T], A> { unsafe { - let (vec_ptr, len, cap, alloc) = v.into_raw_parts_with_alloc(); + let (vec_ptr, len, cap, alloc) = v.into_raw_parts_with_allocator(); let rc_ptr = Self::allocate_for_slice_in(len, &alloc); ptr::copy_nonoverlapping(vec_ptr, (&raw mut (*rc_ptr).value) as *mut T, len); @@ -3491,7 +3526,13 @@ impl Weak { /// Attempts to upgrade the `Weak` pointer to an [`Rc`], delaying /// dropping of the inner value if successful. /// - /// Returns [`None`] if the inner value has since been dropped. + /// Returns [`None`] in the following cases: + /// + /// 1. The inner value has since been dropped or moved out. + /// + /// 2. This `Weak` does not point to an allocation. + /// + /// 3. The owning reference this `Weak` is associated with is either not fully-constructed or does not allow an upgrade. /// /// # Examples /// @@ -3516,7 +3557,7 @@ impl Weak { #[stable(feature = "rc_weak", since = "1.4.0")] pub fn upgrade(&self) -> Option> where - A: Clone, + A: AllocatorClone, { let inner = self.inner()?; @@ -3661,7 +3702,7 @@ unsafe impl<#[may_dangle] T: ?Sized, A: Allocator> Drop for Weak { } #[stable(feature = "rc_weak", since = "1.4.0")] -impl Clone for Weak { +impl Clone for Weak { /// Makes a clone of the `Weak` pointer that points to the same allocation. /// /// # Examples @@ -3683,7 +3724,7 @@ impl Clone for Weak { } #[unstable(feature = "ergonomic_clones", issue = "132290")] -impl UseCloned for Weak {} +impl UseCloned for Weak {} #[stable(feature = "rc_weak", since = "1.4.0")] impl fmt::Debug for Weak { @@ -3820,14 +3861,14 @@ impl<'a> RcInnerPtr for WeakInner<'a> { #[stable(feature = "rust1", since = "1.0.0")] impl borrow::Borrow for Rc { fn borrow(&self) -> &T { - &**self + self } } #[stable(since = "1.5.0", feature = "smart_ptr_as_ref")] impl AsRef for Rc { fn as_ref(&self) -> &T { - &**self + self } } @@ -3952,34 +3993,43 @@ impl fmt::Pointer for UniqueRc { #[unstable(feature = "unique_rc_arc", issue = "112566")] impl borrow::Borrow for UniqueRc { fn borrow(&self) -> &T { - &**self + self } } #[unstable(feature = "unique_rc_arc", issue = "112566")] impl borrow::BorrowMut for UniqueRc { fn borrow_mut(&mut self) -> &mut T { - &mut **self + self } } #[unstable(feature = "unique_rc_arc", issue = "112566")] impl AsRef for UniqueRc { fn as_ref(&self) -> &T { - &**self + self } } #[unstable(feature = "unique_rc_arc", issue = "112566")] impl AsMut for UniqueRc { fn as_mut(&mut self) -> &mut T { - &mut **self + self } } #[unstable(feature = "unique_rc_arc", issue = "112566")] impl Unpin for UniqueRc {} +#[cfg(not(no_global_oom_handling))] +#[unstable(feature = "unique_rc_arc", issue = "112566")] +impl From for UniqueRc { + #[inline(always)] + fn from(value: T) -> Self { + Self::new(value) + } +} + #[unstable(feature = "unique_rc_arc", issue = "112566")] impl PartialEq for UniqueRc { /// Equality for two `UniqueRc`s. @@ -4374,7 +4424,7 @@ impl UniqueRc { } } -impl UniqueRc { +impl UniqueRc { /// Creates a new weak reference to the `UniqueRc`. /// /// Attempting to upgrade this weak reference will fail before the `UniqueRc` has been converted @@ -4563,3 +4613,6 @@ unsafe impl Allocator for Rc { unsafe { (**self).shrink(ptr, old_layout, new_layout) } } } + +#[unstable(feature = "allocator_api", issue = "32838")] +unsafe impl AllocatorClone for Rc {} diff --git a/library/alloc/src/slice.rs b/library/alloc/src/slice.rs index cc8d80aee4569..e6b540f093ba5 100644 --- a/library/alloc/src/slice.rs +++ b/library/alloc/src/slice.rs @@ -476,9 +476,9 @@ impl [T] { /// ``` #[rustc_allow_incoherent_impl] #[stable(feature = "rust1", since = "1.0.0")] + #[rustc_const_unstable(feature = "const_heap", issue = "79597")] #[inline] - #[rustc_diagnostic_item = "slice_into_vec"] - pub fn into_vec(self: Box) -> Vec { + pub const fn into_vec(self: Box) -> Vec { unsafe { let len = self.len(); let (b, alloc) = Box::into_raw_with_allocator(self); @@ -639,9 +639,7 @@ impl [u8] { #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")] #[inline] pub fn to_ascii_uppercase(&self) -> Vec { - let mut me = self.to_vec(); - me.make_ascii_uppercase(); - me + self.iter().map(|b| b.to_ascii_uppercase()).collect() } /// Returns a vector containing a copy of this slice where each byte @@ -660,9 +658,7 @@ impl [u8] { #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")] #[inline] pub fn to_ascii_lowercase(&self) -> Vec { - let mut me = self.to_vec(); - me.make_ascii_lowercase(); - me + self.iter().map(|b| b.to_ascii_lowercase()).collect() } } diff --git a/library/alloc/src/str.rs b/library/alloc/src/str.rs index e772ac25a95c2..4c86d7e06ae44 100644 --- a/library/alloc/src/str.rs +++ b/library/alloc/src/str.rs @@ -126,6 +126,22 @@ macro_rules! copy_slice_and_advance { // the bounds for String-join are S: Borrow and for Vec-join Borrow<[T]> // [T] and str both impl AsRef<[T]> for some T // => s.borrow().as_ref() and we always have slices +// +// # Safety notes +// +// `Borrow` is a safe trait, and implementations are not required +// to be deterministic. An inconsistent `Borrow` implementation could return slices +// of different lengths on consecutive calls (e.g. by using interior mutability). +// +// This implementation calls `borrow()` multiple times: +// 1. To calculate `reserved_len`, all elements are borrowed once. +// 2. All elements, except the first, are borrowed a second time when building the mapped iterator. +// +// Risks and Mitigations: +// - If elements 2..N GROW on their second borrow, the target slice bounds set by `checked_sub` +// means that `split_at_mut` inside `copy_slice_and_advance!` will correctly panic. +// - If elements SHRINK on their second borrow, the spare space is never written, and the final +// length set via `set_len` masks trailing uninitialized bytes. #[cfg(not(no_global_oom_handling))] fn join_generic_copy(slice: &[S], sep: &[T]) -> Vec where @@ -137,8 +153,10 @@ where let mut iter = slice.iter(); // the first slice is the only one without a separator preceding it + // we take care to only borrow this once during the length calculation + // to avoid inconsistent Borrow implementations from breaking our assumptions let first = match iter.next() { - Some(first) => first, + Some(first) => first.borrow().as_ref(), None => return vec![], }; @@ -148,8 +166,11 @@ where // the entire Vec pre-allocated for safety let reserved_len = sep_len .checked_mul(iter.len()) + .and_then(|n| n.checked_add(first.len())) .and_then(|n| { - slice.iter().map(|s| s.borrow().as_ref().len()).try_fold(n, usize::checked_add) + // iter starts from the second element as we've already taken the first + // it's cloned so we can reuse the same iterator below + iter.clone().map(|s| s.borrow().as_ref().len()).try_fold(n, usize::checked_add) }) .expect("attempt to join into collection with len > usize::MAX"); @@ -157,23 +178,25 @@ where let mut result = Vec::with_capacity(reserved_len); debug_assert!(result.capacity() >= reserved_len); - result.extend_from_slice(first.borrow().as_ref()); + result.extend_from_slice(first); unsafe { let pos = result.len(); + debug_assert!(reserved_len >= pos); let target = result.spare_capacity_mut().get_unchecked_mut(..reserved_len - pos); // Convert the separator and slices to slices of MaybeUninit - // to simplify implementation in specialize_for_lengths + // to simplify implementation in specialize_for_lengths. let sep_uninit = core::slice::from_raw_parts(sep.as_ptr().cast(), sep.len()); let iter_uninit = iter.map(|it| { let it = it.borrow().as_ref(); core::slice::from_raw_parts(it.as_ptr().cast(), it.len()) }); - // copy separator and slices over without bounds checks - // generate loops with hardcoded offsets for small separators - // massive improvements possible (~ x2) + // copy separator and slices over without bounds checks. + // `specialize_for_lengths!` internally calls `s.borrow()`, but because it uses + // the bounds-checked `split_at_mut` any misbehaving implementation + // will not write out of bounds. let remain = specialize_for_lengths!(sep_uninit, target, iter_uninit; 0, 1, 2, 3, 4); // A weird borrow implementation may return different @@ -185,6 +208,23 @@ where result } +/// Helper for final sigma lowercase +#[cfg(not(no_global_oom_handling))] +fn map_uppercase_sigma(from: &str, i: usize) -> char { + fn case_ignorable_then_cased>(iter: I) -> bool { + match iter.skip_while(|&c| c.is_case_ignorable()).next() { + Some(c) => c.is_cased(), + None => false, + } + } + + // See https://www.unicode.org/versions/latest/core-spec/chapter-3/#G54277 + // for the definition of `Final_Sigma`. + let is_word_final = case_ignorable_then_cased(from[..i].chars().rev()) + && !case_ignorable_then_cased(from[i + const { 'Σ'.len_utf8() }..].chars()); + if is_word_final { 'ς' } else { 'σ' } +} + #[stable(feature = "rust1", since = "1.0.0")] impl Borrow for String { #[inline] @@ -268,7 +308,10 @@ impl str { pub fn replace(&self, from: P, to: &str) -> String { // Fast path for replacing a single ASCII character with another. if let Some(from_byte) = match from.as_utf8_pattern() { - Some(Utf8Pattern::StringPattern([from_byte])) => Some(*from_byte), + Some(Utf8Pattern::StringPattern(s)) => match s.as_bytes() { + [from_byte] => Some(*from_byte), + _ => None, + }, Some(Utf8Pattern::CharPattern(c)) => c.as_ascii().map(|ascii_char| ascii_char.to_u8()), _ => None, } { @@ -335,24 +378,30 @@ impl str { /// Returns the lowercase equivalent of this string slice, as a new [`String`]. /// - /// 'Lowercase' is defined according to the terms of the Unicode Derived Core Property - /// `Lowercase`. + /// 'Lowercase' is defined according to the terms of + /// [Chapter 3 (Conformance)](https://www.unicode.org/versions/latest/core-spec/chapter-3/#G34432) + /// of the Unicode standard. /// /// Since some characters can expand into multiple characters when changing /// the case, this function returns a [`String`] instead of modifying the /// parameter in-place. /// + /// Unlike [`char::to_lowercase()`], this method fully handles the context-dependent + /// casing of Greek sigma. However, like that method, it does not handle locale-specific + /// casing, like Turkish and Azeri I/ı/İ/i. See its documentation + /// for more information. + /// /// # Examples /// /// Basic usage: /// /// ``` - /// let s = "HELLO"; + /// let s = "HELLO WORLD"; /// - /// assert_eq!("hello", s.to_lowercase()); + /// assert_eq!("hello world", s.to_lowercase()); /// ``` /// - /// A tricky example, with sigma: + /// Tricky examples, with sigma: /// /// ``` /// let sigma = "Σ"; @@ -363,6 +412,10 @@ impl str { /// let odysseus = "ὈΔΥΣΣΕΎΣ"; /// /// assert_eq!("ὀδυσσεύς", odysseus.to_lowercase()); + /// + /// let odysseus_king_of_ithaca = "Ο ΟΔΥΣΣΈΑΣ ΒΑΣΙΛΙΆΣ ΤΗΣ ΙΘΆΚΗΣ"; + /// + /// assert_eq!("ο οδυσσέας βασιλιάς της ιθάκης", odysseus_king_of_ithaca.to_lowercase()); /// ``` /// /// Languages without case are not changed: @@ -378,7 +431,9 @@ impl str { without modifying the original"] #[stable(feature = "unicode_case_mapping", since = "1.2.0")] pub fn to_lowercase(&self) -> String { - let (mut s, rest) = convert_while_ascii(self, u8::to_ascii_lowercase); + // SAFETY: `to_ascii_lowercase` preserves ASCII bytes, so the converted + // prefix remains valid UTF-8. + let (mut s, rest) = unsafe { convert_while_ascii(self, u8::to_ascii_lowercase) }; let prefix_len = s.len(); @@ -406,42 +461,169 @@ impl str { } } } - return s; - - fn map_uppercase_sigma(from: &str, i: usize) -> char { - // See https://www.unicode.org/versions/Unicode7.0.0/ch03.pdf#G33992 - // for the definition of `Final_Sigma`. - debug_assert!('Σ'.len_utf8() == 2); - let is_word_final = case_ignorable_then_cased(from[..i].chars().rev()) - && !case_ignorable_then_cased(from[i + 2..].chars()); - if is_word_final { 'ς' } else { 'σ' } + s + } + + /// Returns the titlecase equivalent of this string slice, + /// which is assumed to represent a single word, + /// as a new [`String`]. + /// + /// Essentially, this consists of uppercasing the first cased letter + /// (with [`char::to_titlecase()`]), and lowercasing everything that follows. + /// + /// 'Titlecase' is defined according to the terms of + /// [Chapter 3 (Conformance)](https://www.unicode.org/versions/latest/core-spec/chapter-3/#G34082) + /// of the Unicode standard. + /// + /// Since some characters can expand into multiple characters when changing + /// the case, this function returns a [`String`] instead of modifying the + /// parameter in-place. + /// + /// Unlike [`char::to_lowercase()`], this method fully handles the context-dependent + /// casing of Greek sigma. However, like that method, it does not handle locale-specific + /// casing, like Turkish and Azeri I/ı/İ/i. See its documentation + /// for more information. + /// + /// This method does not perform any kind of word segmentation. + /// + /// # Examples + /// + /// Basic usage: + /// + /// ``` + /// #![feature(titlecase)] + /// let s = "HELLO WORLD"; + /// + /// assert_eq!("Hello world", s.word_to_titlecase()); + /// ``` + /// + /// The first *cased* letter is uppercased: + /// + /// ``` + /// #![feature(titlecase)] + /// let the_night_before_christmas = "'twas"; + /// + /// assert_eq!("'Twas", the_night_before_christmas.word_to_titlecase()); + /// ``` + /// + /// Languages without case are not changed: + /// + /// ``` + /// #![feature(titlecase)] + /// let new_year = "农历新年"; + /// + /// assert_eq!(new_year, new_year.word_to_titlecase()); + /// ``` + /// + /// Georgian uppercase ("Mtavruli") letters are not used in titlecase: + /// + /// ``` + /// #![feature(titlecase)] + /// let georgian = "ერთობაშია"; + /// + /// assert_eq!(georgian, georgian.word_to_titlecase()); + /// ``` + /// + /// No word segmentation is performed, + /// so only the first cased letter in the whole string gets uppercased: + /// + /// ``` + /// #![feature(titlecase)] + /// let blazingly_fast = "ferris and I"; + /// + /// assert_eq!("Ferris and i", blazingly_fast.word_to_titlecase()); + /// ``` + /// + /// Tricky examples, with sigma: + /// + /// ``` + /// #![feature(titlecase)] + /// let odysseus = "ὈΔΥΣΣΕΎΣ"; + /// + /// assert_eq!("Ὀδυσσεύς", odysseus.word_to_titlecase()); + /// + /// let odysseus_king_of_ithaca = "Ο ΟΔΥΣΣΈΑΣ ΒΑΣΙΛΙΆΣ ΤΗΣ ΙΘΆΚΗΣ"; + /// + /// assert_eq!("Ο οδυσσέας βασιλιάς της ιθάκης", odysseus_king_of_ithaca.word_to_titlecase()); + /// ``` + #[cfg(not(no_global_oom_handling))] + #[rustc_allow_incoherent_impl] + #[must_use = "this returns the titlecase word as a new String, \ + without modifying the original"] + #[unstable(feature = "titlecase", issue = "153892")] + pub fn word_to_titlecase(&self) -> String { + let mut s = String::with_capacity(self.len()); + let mut chars = self.char_indices(); + + // The first cased character is title-cased; leading uncased characters pass through. + 'until_first_cased_char: for (_, c) in chars.by_ref() { + if c.is_cased() { + s.extend(c.to_titlecase()); + break 'until_first_cased_char; + } else { + s.push(c); + } } - fn case_ignorable_then_cased>(iter: I) -> bool { - match iter.skip_while(|&c| c.is_case_ignorable()).next() { - Some(c) => c.is_cased(), - None => false, + // Everything after the first cased character is lower-cased. Use the ASCII fast + // path (auto-vectorized) for its ASCII prefix, mirroring `to_lowercase`. + let remainder = chars.as_str(); + let rest_start = self.len() - remainder.len(); + // SAFETY: `to_ascii_lowercase` preserves ASCII bytes, so the prefix stays valid UTF-8. + let (ascii, rest) = unsafe { convert_while_ascii(remainder, u8::to_ascii_lowercase) }; + s.push_str(&ascii); + let prefix_len = rest_start + ascii.len(); + + for (i, c) in rest.char_indices() { + if c == 'Σ' { + // Σ maps to σ, except at the end of a word where it maps to ς. + // This is the only conditional (contextual) but language-independent mapping + // in `SpecialCasing.txt`, + // so hard-code it rather than have a generic "condition" mechanism. + // See https://github.com/rust-lang/rust/issues/26035 + let sigma_lowercase = map_uppercase_sigma(self, prefix_len + i); + s.push(sigma_lowercase); + } else { + match conversions::to_lower(c) { + [a, '\0', _] => s.push(a), + [a, b, '\0'] => { + s.push(a); + s.push(b); + } + [a, b, c] => { + s.push(a); + s.push(b); + s.push(c); + } + } } } + + s } /// Returns the uppercase equivalent of this string slice, as a new [`String`]. /// - /// 'Uppercase' is defined according to the terms of the Unicode Derived Core Property - /// `Uppercase`. + /// 'Uppercase' is defined according to the terms of + /// [Chapter 3 (Conformance)](https://www.unicode.org/versions/latest/core-spec/chapter-3/#G34431) + /// of the Unicode standard. /// /// Since some characters can expand into multiple characters when changing /// the case, this function returns a [`String`] instead of modifying the /// parameter in-place. /// + /// Like [`char::to_uppercase()`] this method does not handle language-specific + /// casing, like Turkish and Azeri I/ı/İ/i. See that method's documentation + /// for more information. + /// /// # Examples /// /// Basic usage: /// /// ``` - /// let s = "hello"; + /// let s = "hello world"; /// - /// assert_eq!("HELLO", s.to_uppercase()); + /// assert_eq!("HELLO WORLD", s.to_uppercase()); /// ``` /// /// Scripts without case are not changed: @@ -464,7 +646,9 @@ impl str { without modifying the original"] #[stable(feature = "unicode_case_mapping", since = "1.2.0")] pub fn to_uppercase(&self) -> String { - let (mut s, rest) = convert_while_ascii(self, u8::to_ascii_uppercase); + // SAFETY: `to_ascii_uppercase` preserves ASCII bytes, so the converted + // prefix remains valid UTF-8. + let (mut s, rest) = unsafe { convert_while_ascii(self, u8::to_ascii_uppercase) }; for c in rest.chars() { match conversions::to_upper(c) { @@ -483,6 +667,108 @@ impl str { s } + /// Returns the case-folded equivalent of this string slice, as a new [`String`]. + /// + /// Case folding is a transformation, mostly matching lowercase, that is meant to be used + /// for case-insensitive string comparisons. Case-folded strings should not usually + /// be exposed directly to users. + /// + /// For the precise specification of case folding, see + /// [Chapter 3 (Conformance)](https://www.unicode.org/versions/latest/core-spec/chapter-3/#G63737) + /// of the Unicode standard. + /// + /// Since some characters can expand into multiple characters when case folding, + /// this function returns a [`String`] instead of modifying the parameter in-place. + /// + /// No [normalization] (e.g. NFC) is performed, so visually and semantically identical strings + /// might still casefold differently. For example, `"Å"` (U+00C5 LATIN CAPITAL LETTER A WITH RING ABOVE) + /// is considered distinct from `"Å"` (A followed by U+030A COMBINING RING ABOVE), + /// even though Unicode considers them canonically equivalent. + /// + /// Like [`char::to_casefold_unnormalized()`] this method does not handle language-specific + /// casing, like Turkish and Azeri I/ı/İ/i. See that method's documentation + /// for more information. + /// + /// # Examples + /// + /// Basic usage: + /// + /// ``` + /// #![feature(casefold)] + /// let s0 = "HELLO"; + /// let s1 = "Hello"; + /// + /// assert_eq!(s0.to_casefold_unnormalized(), s1.to_casefold_unnormalized()); + /// assert_eq!(s0.to_casefold_unnormalized(), "hello") + /// ``` + /// + /// Scripts without case are not changed: + /// + /// ``` + /// #![feature(casefold)] + /// let new_year = "农历新年"; + /// + /// assert_eq!(new_year, new_year.to_casefold_unnormalized()); + /// ``` + /// + /// One character can become multiple: + /// + /// ``` + /// #![feature(casefold)] + /// let s0 = "TSCHÜẞ"; + /// let s1 = "TSCHÜSS"; + /// let s2 = "tschüß"; + /// + /// assert_eq!(s0.to_casefold_unnormalized(), s1.to_casefold_unnormalized()); + /// assert_eq!(s0.to_casefold_unnormalized(), s2.to_casefold_unnormalized()); + /// assert_eq!(s0.to_casefold_unnormalized(), "tschüss"); + /// ``` + /// + /// No NFC [normalization] is performed: + /// + /// ```rust + /// #![feature(casefold)] + /// // These two strings are visually and semantically identical... + /// let comp = "Å"; + /// let decomp = "Å"; + /// + /// // ... but not codepoint-for-codepoint equal. + /// assert_eq!(comp, "\u{C5}"); + /// assert_eq!(decomp, "A\u{030A}"); + /// + /// // Their case-foldings are likewise unequal: + /// assert_eq!(comp.to_casefold_unnormalized(), "\u{E5}"); + /// assert_eq!(decomp.to_casefold_unnormalized(), "a\u{030A}"); + /// ``` + /// + /// [normalization]: https://www.unicode.org/faq/normalization.html + #[cfg(not(no_global_oom_handling))] + #[rustc_allow_incoherent_impl] + #[must_use = "this returns the case-folded string as a new String, \ + without modifying the original"] + #[unstable(feature = "casefold", issue = "157000")] + pub fn to_casefold_unnormalized(&self) -> String { + // SAFETY: `to_ascii_lowercase` preserves ASCII bytes, so the converted + // prefix remains valid UTF-8. + let (mut s, rest) = unsafe { convert_while_ascii(self, u8::to_ascii_lowercase) }; + + for c in rest.chars() { + match conversions::to_casefold(c) { + [a, '\0', _] => s.push(a), + [a, b, '\0'] => { + s.push(a); + s.push(b); + } + [a, b, c] => { + s.push(a); + s.push(b); + s.push(c); + } + } + } + s + } + /// Converts a [`Box`] into a [`String`] without copying or allocating. /// /// # Examples @@ -558,9 +844,10 @@ impl str { #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")] #[inline] pub fn to_ascii_uppercase(&self) -> String { - let mut s = self.to_owned(); - s.make_ascii_uppercase(); - s + let bytes = self.as_bytes().to_ascii_uppercase(); + // SAFETY: ASCII case conversion only maps a-z to A-Z and leaves + // all other bytes unchanged as valid UTF-8 + unsafe { String::from_utf8_unchecked(bytes) } } /// Returns a copy of this string where each character is mapped to its @@ -590,9 +877,10 @@ impl str { #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")] #[inline] pub fn to_ascii_lowercase(&self) -> String { - let mut s = self.to_owned(); - s.make_ascii_lowercase(); - s + let bytes = self.as_bytes().to_ascii_lowercase(); + // SAFETY: ASCII case conversion only maps A-Z to a-z and leaves + // all other bytes unchanged as valid UTF-8 + unsafe { String::from_utf8_unchecked(bytes) } } } @@ -618,6 +906,18 @@ pub unsafe fn from_boxed_utf8_unchecked(v: Box<[u8]>) -> Box { unsafe { Box::from_raw(Box::into_raw(v) as *mut str) } } +/// Internal; same as `from_boxed_utf8_unchecked` but allocator-generic. Name +/// probably not suitable for being made `pub` as-is. +#[must_use] +#[inline] +#[cfg(not(no_global_oom_handling))] +pub(crate) unsafe fn from_boxed_utf8_unchecked_in( + v: Box<[u8], A>, +) -> Box { + let (ptr, alloc) = Box::into_raw_with_allocator(v); + unsafe { Box::from_raw_in(ptr as *mut str, alloc) } +} + /// Converts leading ascii bytes in `s` by calling the `convert` function. /// /// For better average performance, this happens in chunks of `2*size_of::()`. @@ -627,11 +927,15 @@ pub unsafe fn from_boxed_utf8_unchecked(v: Box<[u8]>) -> Box { /// /// This function is only public so that it can be verified in a codegen test, /// see `issue-123712-str-to-lower-autovectorization.rs`. +/// +/// # Safety +/// +/// `convert` must return an ASCII byte for every ASCII input byte. #[unstable(feature = "str_internals", issue = "none")] #[doc(hidden)] #[inline] #[cfg(not(no_global_oom_handling))] -pub fn convert_while_ascii(s: &str, convert: fn(&u8) -> u8) -> (String, &str) { +pub unsafe fn convert_while_ascii(s: &str, convert: fn(&u8) -> u8) -> (String, &str) { // Process the input in chunks of 16 bytes to enable auto-vectorization. // Previously the chunk size depended on the size of `usize`, // but on 32-bit platforms with sse or neon is also the better choice. @@ -673,7 +977,7 @@ pub fn convert_while_ascii(s: &str, convert: fn(&u8) -> u8) -> (String, &str) { } // handle the remainder as individual bytes - while slice.len() > 0 { + while !slice.is_empty() { let byte = slice[0]; if byte > 127 { break; diff --git a/library/alloc/src/string.rs b/library/alloc/src/string.rs index 4100ee55a4c7b..256efc6c44f7d 100644 --- a/library/alloc/src/string.rs +++ b/library/alloc/src/string.rs @@ -410,7 +410,16 @@ pub struct FromUtf8Error { /// ``` #[stable(feature = "rust1", since = "1.0.0")] #[derive(Debug)] -pub struct FromUtf16Error(()); +pub struct FromUtf16Error { + kind: FromUtf16ErrorKind, +} + +#[cfg_attr(no_global_oom_handling, expect(dead_code))] +#[derive(Clone, PartialEq, Eq, Debug)] +enum FromUtf16ErrorKind { + LoneSurrogate, + OddBytes, +} impl String { /// Creates a new empty `String`. @@ -659,7 +668,6 @@ impl String { /// Basic usage: /// /// ``` - /// #![feature(string_from_utf8_lossy_owned)] /// // some bytes, in a vector /// let sparkle_heart = vec![240, 159, 146, 150]; /// @@ -671,7 +679,6 @@ impl String { /// Incorrect bytes: /// /// ``` - /// #![feature(string_from_utf8_lossy_owned)] /// // some invalid bytes /// let input: Vec = b"Hello \xF0\x90\x80World".into(); /// let output = String::from_utf8_lossy_owned(input); @@ -680,7 +687,7 @@ impl String { /// ``` #[must_use] #[cfg(not(no_global_oom_handling))] - #[unstable(feature = "string_from_utf8_lossy_owned", issue = "129436")] + #[stable(feature = "string_from_utf8_lossy_owned", since = "1.99.0")] pub fn from_utf8_lossy_owned(v: Vec) -> String { if let Cow::Owned(string) = String::from_utf8_lossy(&v) { string @@ -719,7 +726,7 @@ impl String { let mut ret = String::with_capacity(v.len()); for c in char::decode_utf16(v.iter().cloned()) { let Ok(c) = c else { - return Err(FromUtf16Error(())); + return Err(FromUtf16Error { kind: FromUtf16ErrorKind::LoneSurrogate }); }; ret.push(c); } @@ -766,7 +773,6 @@ impl String { /// Basic usage: /// /// ``` - /// #![feature(str_from_utf16_endian)] /// // 𝄞music /// let v = &[0x34, 0xD8, 0x1E, 0xDD, 0x6d, 0x00, 0x75, 0x00, /// 0x73, 0x00, 0x69, 0x00, 0x63, 0x00]; @@ -779,16 +785,16 @@ impl String { /// assert!(String::from_utf16le(v).is_err()); /// ``` #[cfg(not(no_global_oom_handling))] - #[unstable(feature = "str_from_utf16_endian", issue = "116258")] + #[stable(feature = "str_from_utf16_endian", since = "1.98.0")] pub fn from_utf16le(v: &[u8]) -> Result { let (chunks, []) = v.as_chunks::<2>() else { - return Err(FromUtf16Error(())); + return Err(FromUtf16Error { kind: FromUtf16ErrorKind::OddBytes }); }; match (cfg!(target_endian = "little"), unsafe { v.align_to::() }) { (true, ([], v, [])) => Self::from_utf16(v), _ => char::decode_utf16(chunks.iter().copied().map(u16::from_le_bytes)) .collect::>() - .map_err(|_| FromUtf16Error(())), + .map_err(|_| FromUtf16Error { kind: FromUtf16ErrorKind::LoneSurrogate }), } } @@ -808,7 +814,6 @@ impl String { /// Basic usage: /// /// ``` - /// #![feature(str_from_utf16_endian)] /// // 𝄞music /// let v = &[0x34, 0xD8, 0x1E, 0xDD, 0x6d, 0x00, 0x75, 0x00, /// 0x73, 0x00, 0x1E, 0xDD, 0x69, 0x00, 0x63, 0x00, @@ -818,7 +823,7 @@ impl String { /// String::from_utf16le_lossy(v)); /// ``` #[cfg(not(no_global_oom_handling))] - #[unstable(feature = "str_from_utf16_endian", issue = "116258")] + #[stable(feature = "str_from_utf16_endian", since = "1.98.0")] pub fn from_utf16le_lossy(v: &[u8]) -> String { match (cfg!(target_endian = "little"), unsafe { v.align_to::() }) { (true, ([], v, [])) => Self::from_utf16_lossy(v), @@ -841,7 +846,6 @@ impl String { /// Basic usage: /// /// ``` - /// #![feature(str_from_utf16_endian)] /// // 𝄞music /// let v = &[0xD8, 0x34, 0xDD, 0x1E, 0x00, 0x6d, 0x00, 0x75, /// 0x00, 0x73, 0x00, 0x69, 0x00, 0x63]; @@ -854,16 +858,16 @@ impl String { /// assert!(String::from_utf16be(v).is_err()); /// ``` #[cfg(not(no_global_oom_handling))] - #[unstable(feature = "str_from_utf16_endian", issue = "116258")] + #[stable(feature = "str_from_utf16_endian", since = "1.98.0")] pub fn from_utf16be(v: &[u8]) -> Result { let (chunks, []) = v.as_chunks::<2>() else { - return Err(FromUtf16Error(())); + return Err(FromUtf16Error { kind: FromUtf16ErrorKind::OddBytes }); }; match (cfg!(target_endian = "big"), unsafe { v.align_to::() }) { (true, ([], v, [])) => Self::from_utf16(v), _ => char::decode_utf16(chunks.iter().copied().map(u16::from_be_bytes)) .collect::>() - .map_err(|_| FromUtf16Error(())), + .map_err(|_| FromUtf16Error { kind: FromUtf16ErrorKind::LoneSurrogate }), } } @@ -883,7 +887,6 @@ impl String { /// Basic usage: /// /// ``` - /// #![feature(str_from_utf16_endian)] /// // 𝄞music /// let v = &[0xD8, 0x34, 0xDD, 0x1E, 0x00, 0x6d, 0x00, 0x75, /// 0x00, 0x73, 0xDD, 0x1E, 0x00, 0x69, 0x00, 0x63, @@ -893,7 +896,7 @@ impl String { /// String::from_utf16be_lossy(v)); /// ``` #[cfg(not(no_global_oom_handling))] - #[unstable(feature = "str_from_utf16_endian", issue = "116258")] + #[stable(feature = "str_from_utf16_endian", since = "1.98.0")] pub fn from_utf16be_lossy(v: &[u8]) -> String { match (cfg!(target_endian = "big"), unsafe { v.align_to::() }) { (true, ([], v, [])) => Self::from_utf16_lossy(v), @@ -1102,6 +1105,19 @@ impl String { self.vec.extend_from_slice(string.as_bytes()) } + /// Appends a given string slice onto the end of this `String`, returning + /// [`TryReserveError`] otherwise. + #[cfg_attr( + not(no_global_oom_handling), + expect( + dead_code, + reason = "currently only used in IO module when global OOM handling is disabled" + ) + )] + pub(crate) fn try_push_str(&mut self, string: &str) -> Result<(), TryReserveError> { + self.vec.try_extend_from_slice_of_bytes(string.as_bytes()) + } + #[cfg(not(no_global_oom_handling))] #[inline] fn push_str_slice(&mut self, slice: &[&str]) { @@ -1298,7 +1314,7 @@ impl String { /// /// Ok(output) /// } - /// # process_data("rust").expect("why is the test harness OOMing on 4 bytes?"); + /// # process_data("rust").expect("reserving capacity for 12 bytes should never fail"); /// ``` #[stable(feature = "try_reserve", since = "1.57.0")] pub fn try_reserve(&mut self, additional: usize) -> Result<(), TryReserveError> { @@ -1339,7 +1355,7 @@ impl String { /// /// Ok(output) /// } - /// # process_data("rust").expect("why is the test harness OOMing on 4 bytes?"); + /// # process_data("rust").expect("reserving capacity for 12 bytes should never fail"); /// ``` #[stable(feature = "try_reserve", since = "1.57.0")] pub fn try_reserve_exact(&mut self, additional: usize) -> Result<(), TryReserveError> { @@ -1420,7 +1436,7 @@ impl String { // SAFETY: Just reserved capacity for at least the length needed to encode `ch`. unsafe { - core::char::encode_utf8_raw_unchecked(ch as u32, self.vec.as_mut_ptr().add(self.len())); + core::char::encode_utf8_raw_unchecked(ch as u32, self.vec.as_mut_ptr().add(len)); self.vec.set_len(len + ch_len); } } @@ -2234,19 +2250,36 @@ impl FromUtf8Error { /// invalid sequences, and [`String::from_utf8_lossy_owned`] for the /// `String` function which corresponds to this function. /// + /// This is useful in conjunction with [`String::from_utf8`] when you need + /// to branch on whether the bytes are valid UTF-8, but still want to + /// recover a lossily converted `String` in the error case. Use + /// [`String::from_utf8_lossy_owned`] if you always need a lossily converted + /// `String`. + /// + /// Since the original [`String::from_utf8`] error records where validation + /// stopped, this method does not need to re-check the already valid prefix + /// of the byte sequence. + /// /// # Examples /// /// ``` - /// #![feature(string_from_utf8_lossy_owned)] /// // some invalid bytes /// let input: Vec = b"Hello \xF0\x90\x80World".into(); - /// let output = String::from_utf8(input).unwrap_or_else(|e| e.into_utf8_lossy()); + /// + /// let (output, had_invalid_utf8) = match String::from_utf8(input) { + /// Ok(output) => (output, false), + /// Err(error) => { + /// // The bytes were not valid UTF-8, but we can still recover a string. + /// (error.into_utf8_lossy(), true) + /// } + /// }; /// /// assert_eq!(String::from("Hello �World"), output); + /// assert!(had_invalid_utf8); /// ``` #[must_use] #[cfg(not(no_global_oom_handling))] - #[unstable(feature = "string_from_utf8_lossy_owned", issue = "129436")] + #[stable(feature = "string_from_utf8_lossy_owned", since = "1.99.0")] pub fn into_utf8_lossy(self) -> String { const REPLACEMENT: &str = "\u{FFFD}"; @@ -2335,7 +2368,11 @@ impl fmt::Display for FromUtf8Error { #[stable(feature = "rust1", since = "1.0.0")] impl fmt::Display for FromUtf16Error { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - fmt::Display::fmt("invalid utf-16: lone surrogate found", f) + match self.kind { + FromUtf16ErrorKind::LoneSurrogate => "invalid utf-16: lone surrogate found", + FromUtf16ErrorKind::OddBytes => "invalid utf-16: odd number of bytes", + } + .fmt(f) } } @@ -2654,15 +2691,14 @@ impl<'b> Pattern for &'b String { #[inline] fn as_utf8_pattern(&self) -> Option> { - Some(Utf8Pattern::StringPattern(self.as_bytes())) + Some(Utf8Pattern::StringPattern(self.as_str())) } } macro_rules! impl_eq { ($lhs:ty, $rhs: ty) => { #[stable(feature = "rust1", since = "1.0.0")] - #[allow(unused_lifetimes)] - impl<'a, 'b> PartialEq<$rhs> for $lhs { + impl PartialEq<$rhs> for $lhs { #[inline] fn eq(&self, other: &$rhs) -> bool { PartialEq::eq(&self[..], &other[..]) @@ -2674,8 +2710,7 @@ macro_rules! impl_eq { } #[stable(feature = "rust1", since = "1.0.0")] - #[allow(unused_lifetimes)] - impl<'a, 'b> PartialEq<$lhs> for $rhs { + impl PartialEq<$lhs> for $rhs { #[inline] fn eq(&self, other: &$lhs) -> bool { PartialEq::eq(&self[..], &other[..]) @@ -2689,17 +2724,17 @@ macro_rules! impl_eq { } impl_eq! { String, str } -impl_eq! { String, &'a str } +impl_eq! { String, &str } #[cfg(not(no_global_oom_handling))] -impl_eq! { Cow<'a, str>, str } +impl_eq! { Cow<'_, str>, str } #[cfg(not(no_global_oom_handling))] -impl_eq! { Cow<'a, str>, &'b str } +impl_eq! { Cow<'_, str>, &'_ str } #[cfg(not(no_global_oom_handling))] -impl_eq! { Cow<'a, str>, String } +impl_eq! { Cow<'_, str>, String } #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for String { +const impl Default for String { /// Creates an empty `String`. #[inline] fn default() -> String { diff --git a/library/alloc/src/sync.rs b/library/alloc/src/sync.rs index a5e4fab916aba..8ff3927aabf5e 100644 --- a/library/alloc/src/sync.rs +++ b/library/alloc/src/sync.rs @@ -12,21 +12,21 @@ use core::any::Any; use core::cell::CloneFromCell; #[cfg(not(no_global_oom_handling))] use core::clone::TrivialClone; -use core::clone::{CloneToUninit, UseCloned}; +use core::clone::{CloneToUninit, Share, UseCloned}; use core::cmp::Ordering; use core::hash::{Hash, Hasher}; use core::intrinsics::abort; #[cfg(not(no_global_oom_handling))] use core::iter; use core::marker::{PhantomData, Unsize}; -use core::mem::{self, ManuallyDrop}; +use core::mem::{self, Alignment, ManuallyDrop}; use core::num::NonZeroUsize; use core::ops::{CoerceUnsized, Deref, DerefMut, DerefPure, DispatchFromDyn, LegacyReceiver}; #[cfg(not(no_global_oom_handling))] use core::ops::{Residual, Try}; use core::panic::{RefUnwindSafe, UnwindSafe}; -use core::pin::{Pin, PinCoerceUnsized}; -use core::ptr::{self, Alignment, NonNull}; +use core::pin::{Pin, PinSafePointer}; +use core::ptr::{self, NonNull}; #[cfg(not(no_global_oom_handling))] use core::slice::from_raw_parts_mut; use core::sync::atomic::Ordering::{Acquire, Relaxed, Release}; @@ -35,7 +35,7 @@ use core::{borrow, fmt, hint}; #[cfg(not(no_global_oom_handling))] use crate::alloc::handle_alloc_error; -use crate::alloc::{AllocError, Allocator, Global, Layout}; +use crate::alloc::{AllocError, Allocator, AllocatorClone, Global, Layout}; use crate::borrow::{Cow, ToOwned}; use crate::boxed::Box; use crate::rc::is_dangling; @@ -55,8 +55,13 @@ use crate::vec::Vec; /// See comment in `Arc::clone`. const MAX_REFCOUNT: usize = (isize::MAX) as usize; -/// The error in case either counter reaches above `MAX_REFCOUNT`, and we can `panic` safely. -const INTERNAL_OVERFLOW_ERROR: &str = "Arc counter overflow"; +#[cold] +#[cfg_attr(not(panic = "immediate-abort"), inline(never))] +#[cfg_attr(panic = "immediate-abort", inline)] +#[track_caller] +fn panic_arc_overflow() -> ! { + panic!("Arc counter overflow"); +} #[cfg(not(sanitize = "thread"))] macro_rules! acquire { @@ -261,6 +266,11 @@ macro_rules! acquire { #[rustc_diagnostic_item = "Arc"] #[stable(feature = "rust1", since = "1.0.0")] #[rustc_insignificant_dtor] +#[diagnostic::on_move( + message = "the type `{Self}` does not implement `Copy`", + label = "this move could be avoided by cloning the original `{Self}`, which is inexpensive", + note = "consider using `Arc::clone`" +)] pub struct Arc< T: ?Sized, #[unstable(feature = "allocator_api", issue = "32838")] A: Allocator = Global, @@ -271,12 +281,15 @@ pub struct Arc< } #[stable(feature = "rust1", since = "1.0.0")] -unsafe impl Send for Arc {} +unsafe impl Send for Arc {} #[stable(feature = "rust1", since = "1.0.0")] unsafe impl Sync for Arc {} #[stable(feature = "catch_unwind", since = "1.9.0")] -impl UnwindSafe for Arc {} +impl UnwindSafe + for Arc +{ +} #[unstable(feature = "coerce_unsized", issue = "18598")] impl, U: ?Sized, A: Allocator> CoerceUnsized> for Arc {} @@ -354,7 +367,7 @@ pub struct Weak< } #[stable(feature = "arc_weak", since = "1.4.0")] -unsafe impl Send for Weak {} +unsafe impl Send for Weak {} #[stable(feature = "arc_weak", since = "1.4.0")] unsafe impl Sync for Weak {} @@ -384,8 +397,12 @@ struct ArcInner { strong: Atomic, // the value usize::MAX acts as a sentinel for temporarily "locking" the - // ability to upgrade weak pointers or downgrade strong ones; this is used - // to avoid races in `make_mut` and `get_mut`. + // weak count, preventing `Arc::downgrade` from racing to create new + // `Weak` references. `Arc::is_unique` (which backs `Arc::get_mut`) + // needs to observe both the strong and weak counts as indicating + // uniqueness in one logical atomic step; since they live in separate + // atomic words, it locks the weak count while reading the strong + // count to keep the two reads consistent. weak: Atomic, data: T, @@ -397,7 +414,11 @@ fn arcinner_layout_for_value_layout(layout: Layout) -> Layout { // Previously, layout was calculated on the expression // `&*(ptr as *const ArcInner)`, but this created a misaligned // reference (see #54908). - Layout::new::>().extend(layout).unwrap().0.pad_to_align() + Layout::new::>() + .extend(layout) + .unwrap_or_else(|_| panic!("capacity overflow")) + .0 + .pad_to_align() } unsafe impl Send for ArcInner {} @@ -908,7 +929,7 @@ impl Arc { // Now we can properly initialize the inner value and turn our weak // reference into a strong reference. - let strong = unsafe { + unsafe { let inner = init_ptr.as_ptr(); ptr::write(&raw mut (*inner).data, data); @@ -934,9 +955,7 @@ impl Arc { let alloc = weak.into_raw_with_allocator().1; Arc::from_inner_in(init_ptr, alloc) - }; - - strong + } } /// Constructs a new `Pin>` in the provided allocator. If `T` does not implement `Unpin`, @@ -1301,33 +1320,10 @@ impl Arc<[T]> { Arc::from_ptr(Arc::allocate_for_layout( Layout::array::(len).unwrap(), |layout| Global.allocate_zeroed(layout), - |mem| { - ptr::slice_from_raw_parts_mut(mem as *mut T, len) - as *mut ArcInner<[mem::MaybeUninit]> - }, + |mem| mem.cast::().cast_slice(len) as *mut ArcInner<[mem::MaybeUninit]>, )) } } - - /// Converts the reference-counted slice into a reference-counted array. - /// - /// This operation does not reallocate; the underlying array of the slice is simply reinterpreted as an array type. - /// - /// If `N` is not exactly equal to the length of `self`, then this method returns `None`. - #[unstable(feature = "alloc_slice_into_array", issue = "148082")] - #[inline] - #[must_use] - pub fn into_array(self) -> Option> { - if self.len() == N { - let ptr = Self::into_raw(self) as *const [T; N]; - - // SAFETY: The underlying array of a slice has the exact same layout as an actual array `[T; N]` if `N` is equal to the slice's length. - let me = unsafe { Arc::from_raw(ptr) }; - Some(me) - } else { - None - } - } } impl Arc<[T], A> { @@ -1393,15 +1389,46 @@ impl Arc<[T], A> { Arc::allocate_for_layout( Layout::array::(len).unwrap(), |layout| alloc.allocate_zeroed(layout), - |mem| { - ptr::slice_from_raw_parts_mut(mem.cast::(), len) - as *mut ArcInner<[mem::MaybeUninit]> - }, + |mem| mem.cast::().cast_slice(len) as *mut ArcInner<[mem::MaybeUninit]>, ), alloc, ) } } + + /// Converts the reference-counted slice into a reference-counted array. + /// + /// This operation does not reallocate; the underlying array of the slice is simply reinterpreted as an array type. + /// + /// # Errors + /// + /// Returns the original `Arc<[T]>` in the `Err` variant if `self.len()` does not equal `N`. + /// + /// # Examples + /// + /// ``` + /// #![feature(alloc_slice_into_array)] + /// use std::sync::Arc; + /// + /// let arc_slice: Arc<[i32]> = Arc::new([1, 2, 3]); + /// + /// let arc_array: Arc<[i32; 3]> = arc_slice.into_array().unwrap(); + /// ``` + #[unstable(feature = "alloc_slice_into_array", issue = "148082")] + #[inline] + #[must_use] + pub fn into_array(self) -> Result, Self> { + if self.len() == N { + let (ptr, alloc) = Self::into_raw_with_allocator(self); + let ptr = ptr as *const [T; N]; + + // SAFETY: The underlying array of a slice has the exact same layout as an actual array `[T; N]` if `N` is equal to the slice's length. + let me = unsafe { Arc::from_raw_in(ptr, alloc) }; + Ok(me) + } else { + Err(self) + } + } } impl Arc, A> { @@ -1497,14 +1524,12 @@ impl Arc { let mut in_progress: UniqueArcUninit = UniqueArcUninit::new(value, alloc); // Initialize with clone of value. - let initialized_clone = unsafe { + unsafe { // Clone. If the clone panics, `in_progress` will be dropped and clean up. value.clone_to_uninit(in_progress.data_ptr().cast()); // Cast type of pointer, now that it is initialized. in_progress.into_arc() - }; - - initialized_clone + } } /// Constructs a new `Arc` with a clone of `value` in the provided allocator, returning an error if allocation fails @@ -1581,29 +1606,32 @@ impl Arc { /// Constructs an `Arc` from a raw pointer. /// /// The raw pointer must have been previously returned by a call to - /// [`Arc::into_raw`][into_raw] with the following requirements: + /// [`Arc::into_raw`][into_raw] or [`Arc::into_raw_with_allocator`][into_raw_with_allocator]. + /// + /// # Safety /// + /// * Creating a `Arc` from a pointer other than one returned from + /// [`Arc::into_raw`][into_raw] or [`Arc::into_raw_with_allocator`][into_raw_with_allocator] + /// is undefined behavior. /// * If `U` is sized, it must have the same size and alignment as `T`. This /// is trivially true if `U` is `T`. /// * If `U` is unsized, its data pointer must have the same size and /// alignment as `T`. This is trivially true if `Arc` was constructed /// through `Arc` and then converted to `Arc` through an [unsized /// coercion]. - /// - /// Note that if `U` or `U`'s data pointer is not `T` but has the same size - /// and alignment, this is basically like transmuting references of - /// different types. See [`mem::transmute`][transmute] for more information - /// on what restrictions apply in this case. - /// - /// The raw pointer must point to a block of memory allocated by the global allocator. - /// - /// The user of `from_raw` has to make sure a specific value of `T` is only - /// dropped once. + /// * Note that if `U` or `U`'s data pointer is not `T` but has the same size + /// and alignment, this is basically like transmuting references of + /// different types. See [`mem::transmute`][transmute] for more information + /// on what restrictions apply in this case. + /// * The raw pointer must point to a block of memory allocated by the global allocator. + /// * The user of `from_raw` has to make sure a specific value of `T` is only + /// dropped once. /// /// This function is unsafe because improper use may lead to memory unsafety, /// even if the returned `Arc` is never accessed. /// /// [into_raw]: Arc::into_raw + /// [into_raw_with_allocator]: Arc::into_raw_with_allocator /// [transmute]: core::mem::transmute /// [unsized coercion]: https://doc.rust-lang.org/reference/type-coercions.html#unsized-coercions /// @@ -1819,29 +1847,32 @@ impl Arc { /// Constructs an `Arc` from a raw pointer. /// /// The raw pointer must have been previously returned by a call to [`Arc::into_raw`][into_raw] with the following requirements: + /// A>::into_raw`][into_raw] or [`Arc::into_raw_with_allocator`][into_raw_with_allocator]. + /// + /// # Safety /// + /// * Creating a `Arc` from a pointer other than one returned from + /// [`Arc::into_raw`][into_raw] or [`Arc::into_raw_with_allocator`][into_raw_with_allocator] + /// is undefined behavior. /// * If `U` is sized, it must have the same size and alignment as `T`. This /// is trivially true if `U` is `T`. /// * If `U` is unsized, its data pointer must have the same size and - /// alignment as `T`. This is trivially true if `Arc` was constructed - /// through `Arc` and then converted to `Arc` through an [unsized + /// alignment as `T`. This is trivially true if `Arc` was constructed + /// through `Arc` and then converted to `Arc` through an [unsized /// coercion]. - /// - /// Note that if `U` or `U`'s data pointer is not `T` but has the same size - /// and alignment, this is basically like transmuting references of - /// different types. See [`mem::transmute`][transmute] for more information - /// on what restrictions apply in this case. - /// - /// The raw pointer must point to a block of memory allocated by `alloc` - /// - /// The user of `from_raw` has to make sure a specific value of `T` is only - /// dropped once. + /// * Note that if `U` or `U`'s data pointer is not `T` but has the same size + /// and alignment, this is basically like transmuting references of + /// different types. See [`mem::transmute`][transmute] for more information + /// on what restrictions apply in this case. + /// * The raw pointer must point to a block of memory allocated by `alloc` + /// * The user of `from_raw` has to make sure a specific value of `T` is only + /// dropped once. /// /// This function is unsafe because improper use may lead to memory unsafety, /// even if the returned `Arc` is never accessed. /// /// [into_raw]: Arc::into_raw + /// [into_raw_with_allocator]: Arc::into_raw_with_allocator /// [transmute]: core::mem::transmute /// [unsized coercion]: https://doc.rust-lang.org/reference/type-coercions.html#unsized-coercions /// @@ -1912,7 +1943,7 @@ impl Arc { #[stable(feature = "arc_weak", since = "1.4.0")] pub fn downgrade(this: &Self) -> Weak where - A: Clone, + A: AllocatorClone, { // This Relaxed is OK because we're checking the value in the CAS // below. @@ -1927,8 +1958,9 @@ impl Arc { } // We can't allow the refcount to increase much past `MAX_REFCOUNT`. - assert!(cur <= MAX_REFCOUNT, "{}", INTERNAL_OVERFLOW_ERROR); - + if cur > MAX_REFCOUNT { + panic_arc_overflow(); + } // NOTE: this code currently ignores the possibility of overflow // into usize::MAX; in general both Rc and Arc need to be adjusted // to deal with overflow. @@ -2043,7 +2075,7 @@ impl Arc { #[unstable(feature = "allocator_api", issue = "32838")] pub unsafe fn increment_strong_count_in(ptr: *const T, alloc: A) where - A: Clone, + A: AllocatorClone, { // Retain Arc, but don't touch refcount by wrapping in ManuallyDrop let arc = unsafe { mem::ManuallyDrop::new(Arc::from_raw_in(ptr, alloc)) }; @@ -2231,7 +2263,7 @@ impl Arc { // Free the allocation without dropping its contents let (bptr, alloc) = Box::into_raw_with_allocator(src); - let src = Box::from_raw_in(bptr as *mut mem::ManuallyDrop, alloc.by_ref()); + let src = Box::from_raw_in(bptr as *mut mem::ManuallyDrop, &alloc); drop(src); Self::from_ptr_in(ptr, alloc) @@ -2247,7 +2279,7 @@ impl Arc<[T]> { Self::allocate_for_layout( Layout::array::(len).unwrap(), |layout| Global.allocate(layout), - |mem| ptr::slice_from_raw_parts_mut(mem.cast::(), len) as *mut ArcInner<[T]>, + |mem| mem.cast::().cast_slice(len) as *mut ArcInner<[T]>, ) } } @@ -2326,7 +2358,7 @@ impl Arc<[T], A> { Arc::allocate_for_layout( Layout::array::(len).unwrap(), |layout| alloc.allocate(layout), - |mem| ptr::slice_from_raw_parts_mut(mem.cast::(), len) as *mut ArcInner<[T]>, + |mem| mem.cast::().cast_slice(len) as *mut ArcInner<[T]>, ) } } @@ -2357,7 +2389,7 @@ impl ArcFromSlice for Arc<[T]> { } #[stable(feature = "rust1", since = "1.0.0")] -impl Clone for Arc { +impl Clone for Arc { /// Makes a clone of the `Arc` pointer. /// /// This creates another pointer to the same allocation, increasing the @@ -2411,7 +2443,10 @@ impl Clone for Arc { } #[unstable(feature = "ergonomic_clones", issue = "132290")] -impl UseCloned for Arc {} +impl UseCloned for Arc {} + +#[unstable(feature = "share_trait", issue = "156756")] +impl Share for Arc {} #[stable(feature = "rust1", since = "1.0.0")] impl Deref for Arc { @@ -2423,11 +2458,16 @@ impl Deref for Arc { } } +// The API of this pointer type enforces that if the `T` is pinned, then *all* +// clones of this `Arc` are wrapped as `Pin>`. Since an `&Arc` +// could be used to obtain an `Arc` that is not wrapped in `Pin` (and later +// used with `Arc::get_mut`), this means that this type treats `&Arc` as +// evidence that the `T` is not pinned. The implementations of various traits +// are written accordingly. Since this type is not fundamental, downstream +// crates cannot provide malicious implementations of any of the traits relevant +// for `Pin`. #[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -unsafe impl PinCoerceUnsized for Arc {} - -#[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -unsafe impl PinCoerceUnsized for Weak {} +unsafe impl PinSafePointer for Arc {} #[unstable(feature = "deref_pure_trait", issue = "87121")] unsafe impl DerefPure for Arc {} @@ -2436,7 +2476,7 @@ unsafe impl DerefPure for Arc {} impl LegacyReceiver for Arc {} #[cfg(not(no_global_oom_handling))] -impl Arc { +impl Arc { /// Makes a mutable reference into the given `Arc`. /// /// If there are other `Arc` pointers to the same allocation, then `make_mut` will @@ -2516,16 +2556,27 @@ impl Arc { // usize::MAX (i.e., locked), since the weak count can only be // locked by a thread with a strong reference. - // Materialize our own implicit weak pointer, so that it can clean - // up the ArcInner as needed. - let _weak = Weak { ptr: this.ptr, alloc: this.alloc.clone() }; + // Guard against panics while using the allocator. + // If we unwind before the Arc is overwritten, we expose a strong + // count of 0, resulting in a UAF (#155746, #157203). + // Until the new Arc is written, the old Arc must remain valid + struct Guard<'a, T: ?Sized> { + inner: &'a ArcInner, + } + impl<'a, T: ?Sized> Drop for Guard<'a, T> { + fn drop(&mut self) { + self.inner.strong.store(1, Release); + } + } + let guard = Guard { inner: this.inner() }; // Can just steal the data, all that's left is Weaks - // - // We don't need panic-protection like the above branch does, but we might as well - // use the same mechanism. + // Note that this can panic in two ways: + // - The allocation can fail + // - The allocator clone can fail let mut in_progress: UniqueArcUninit = UniqueArcUninit::new(&**this, this.alloc.clone()); + unsafe { // Initialize `in_progress` with move of **this. // We have to express this in terms of bytes because `T: ?Sized`; there is no @@ -2536,6 +2587,15 @@ impl Arc { size_of_val, ); + // We are now safe from panics. + mem::forget(guard); + + // Materialize our own implicit weak pointer, so that it can clean + // up the ArcInner as needed. + // Make sure the allocator is not leaked when the Arc is overwritten. + // Only drop at the end of the scope to avoid panics. + let _weak = Weak { ptr: this.ptr, alloc: ptr::read(&this.alloc) }; + ptr::write(this, in_progress.into_arc()); } } else { @@ -3224,7 +3284,13 @@ impl Weak { /// Attempts to upgrade the `Weak` pointer to an [`Arc`], delaying /// dropping of the inner value if successful. /// - /// Returns [`None`] if the inner value has since been dropped. + /// Returns [`None`] in the following cases: + /// + /// 1. The inner value has since been dropped or moved out. + /// + /// 2. This `Weak` does not point to an allocation. + /// + /// 3. The owning reference this `Weak` is associated with is either not fully-constructed or does not allow an upgrade. /// /// # Examples /// @@ -3249,7 +3315,7 @@ impl Weak { #[stable(feature = "arc_weak", since = "1.4.0")] pub fn upgrade(&self) -> Option> where - A: Clone, + A: AllocatorClone, { #[inline] fn checked_increment(n: usize) -> Option { @@ -3258,7 +3324,9 @@ impl Weak { return None; } // See comments in `Arc::clone` for why we do this (for `mem::forget`). - assert!(n <= MAX_REFCOUNT, "{}", INTERNAL_OVERFLOW_ERROR); + if n > MAX_REFCOUNT { + panic_arc_overflow(); + } Some(n + 1) } @@ -3270,7 +3338,7 @@ impl Weak { // Acquire is necessary for the success case to synchronise with `Arc::new_cyclic`, when the inner // value can be initialized after `Weak` references have already been created. In that case, we // expect to observe the fully initialized value. - if self.inner()?.strong.fetch_update(Acquire, Relaxed, checked_increment).is_ok() { + if self.inner()?.strong.try_update(Acquire, Relaxed, checked_increment).is_ok() { // SAFETY: pointer is not null, verified in checked_increment unsafe { Some(Arc::from_inner_in(self.ptr, self.alloc.clone())) } } else { @@ -3384,7 +3452,7 @@ impl Weak { } #[stable(feature = "arc_weak", since = "1.4.0")] -impl Clone for Weak { +impl Clone for Weak { /// Makes a clone of the `Weak` pointer that points to the same allocation. /// /// # Examples @@ -3416,7 +3484,7 @@ impl Clone for Weak { } #[unstable(feature = "ergonomic_clones", issue = "132290")] -impl UseCloned for Weak {} +impl UseCloned for Weak {} #[stable(feature = "downgraded_weak", since = "1.10.0")] impl Default for Weak { @@ -3523,12 +3591,12 @@ impl ArcEqIdent for Arc { impl ArcEqIdent for Arc { #[inline] fn eq(&self, other: &Arc) -> bool { - Arc::ptr_eq(self, other) || **self == **other + ptr::eq(self.ptr.as_ptr(), other.ptr.as_ptr()) || **self == **other } #[inline] fn ne(&self, other: &Arc) -> bool { - !Arc::ptr_eq(self, other) && **self != **other + !ptr::eq(self.ptr.as_ptr(), other.ptr.as_ptr()) && **self != **other } } @@ -3771,7 +3839,7 @@ impl Default for Arc { #[inline] fn default() -> Self { let arc: Arc<[u8]> = Default::default(); - debug_assert!(core::str::from_utf8(&*arc).is_ok()); + debug_assert!(core::str::from_utf8(&arc).is_ok()); let (ptr, alloc) = Arc::into_inner_with_allocator(arc); unsafe { Arc::from_ptr_in(ptr.as_ptr() as *mut ArcInner, alloc) } } @@ -4004,7 +4072,7 @@ impl From> for Arc { #[cfg(not(no_global_oom_handling))] #[stable(feature = "shared_from_slice", since = "1.21.0")] -impl From> for Arc<[T], A> { +impl From> for Arc<[T], A> { /// Allocates a reference-counted slice and moves `v`'s items into it. /// /// # Example @@ -4018,7 +4086,7 @@ impl From> for Arc<[T], A> { #[inline] fn from(v: Vec) -> Arc<[T], A> { unsafe { - let (vec_ptr, len, cap, alloc) = v.into_raw_parts_with_alloc(); + let (vec_ptr, len, cap, alloc) = v.into_raw_parts_with_allocator(); let rc_ptr = Self::allocate_for_slice_in(len, &alloc); ptr::copy_nonoverlapping(vec_ptr, (&raw mut (*rc_ptr).data) as *mut T, len); @@ -4181,14 +4249,14 @@ impl> ToArcSlice for I { #[stable(feature = "rust1", since = "1.0.0")] impl borrow::Borrow for Arc { fn borrow(&self) -> &T { - &**self + self } } #[stable(since = "1.5.0", feature = "smart_ptr_as_ref")] impl AsRef for Arc { fn as_ref(&self) -> &T { - &**self + self } } @@ -4278,7 +4346,6 @@ impl UniqueArcUninit { } } -#[cfg(not(no_global_oom_handling))] impl Drop for UniqueArcUninit { fn drop(&mut self) { // SAFETY: @@ -4359,7 +4426,7 @@ pub struct UniqueArc< } #[unstable(feature = "unique_rc_arc", issue = "112566")] -unsafe impl Send for UniqueArc {} +unsafe impl Send for UniqueArc {} #[unstable(feature = "unique_rc_arc", issue = "112566")] unsafe impl Sync for UniqueArc {} @@ -4399,28 +4466,37 @@ impl fmt::Pointer for UniqueArc { #[unstable(feature = "unique_rc_arc", issue = "112566")] impl borrow::Borrow for UniqueArc { fn borrow(&self) -> &T { - &**self + self } } #[unstable(feature = "unique_rc_arc", issue = "112566")] impl borrow::BorrowMut for UniqueArc { fn borrow_mut(&mut self) -> &mut T { - &mut **self + self } } #[unstable(feature = "unique_rc_arc", issue = "112566")] impl AsRef for UniqueArc { fn as_ref(&self) -> &T { - &**self + self } } #[unstable(feature = "unique_rc_arc", issue = "112566")] impl AsMut for UniqueArc { fn as_mut(&mut self) -> &mut T { - &mut **self + self + } +} + +#[cfg(not(no_global_oom_handling))] +#[unstable(feature = "unique_rc_arc", issue = "112566")] +impl From for UniqueArc { + #[inline(always)] + fn from(value: T) -> Self { + Self::new(value) } } @@ -4805,7 +4881,7 @@ impl UniqueArc { } } -impl UniqueArc { +impl UniqueArc { /// Creates a new weak reference to the `UniqueArc`. /// /// Attempting to upgrade this weak reference will fail before the `UniqueArc` has been converted @@ -4853,7 +4929,7 @@ impl Deref for UniqueArc { // #[unstable(feature = "unique_rc_arc", issue = "112566")] #[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -unsafe impl PinCoerceUnsized for UniqueArc {} +unsafe impl PinSafePointer for UniqueArc {} #[unstable(feature = "unique_rc_arc", issue = "112566")] impl DerefMut for UniqueArc { @@ -4934,3 +5010,6 @@ unsafe impl Allocator for Arc { unsafe { (**self).shrink(ptr, old_layout, new_layout) } } } + +#[unstable(feature = "allocator_api", issue = "32838")] +unsafe impl AllocatorClone for Arc {} diff --git a/library/alloc/src/task.rs b/library/alloc/src/task.rs index aa1901314e37c..0e36c91f466fd 100644 --- a/library/alloc/src/task.rs +++ b/library/alloc/src/task.rs @@ -37,6 +37,10 @@ use crate::sync::Arc; /// link ../../std/task/struct.Waker.html#impl-From%3CArc%3CW,+Global%3E%3E-for-Waker /// without getting a link-checking error in CI. --> /// +/// # Memory Ordering +/// +/// To avoid missed wakeups, all executors must adhere to the requirement described for [`Waker::wake`]. +/// /// # Examples /// /// A basic `block_on` function that takes a future and runs it to completion on @@ -87,6 +91,7 @@ use crate::sync::Arc; /// ``` #[cfg(target_has_atomic = "ptr")] #[stable(feature = "wake_trait", since = "1.51.0")] +#[rustc_diagnostic_item = "Wake"] pub trait Wake { /// Wake this task. #[stable(feature = "wake_trait", since = "1.51.0")] diff --git a/library/alloc/src/vec/drain.rs b/library/alloc/src/vec/drain.rs index 8705a9c3d2679..d12dea20b33cb 100644 --- a/library/alloc/src/vec/drain.rs +++ b/library/alloc/src/vec/drain.rs @@ -1,8 +1,7 @@ -use core::fmt; use core::iter::{FusedIterator, TrustedLen}; use core::mem::{self, ManuallyDrop, SizedTypeProperties}; use core::ptr::{self, NonNull}; -use core::slice::{self}; +use core::{fmt, slice}; use super::Vec; use crate::alloc::{Allocator, Global}; @@ -233,7 +232,7 @@ impl Drop for Drain<'_, T, A> { // invalidate raw pointers to it which some unsafe code might rely on. let vec_ptr = vec.as_mut().as_mut_ptr(); let drop_offset = drop_ptr.offset_from_unsigned(vec_ptr); - let to_drop = ptr::slice_from_raw_parts_mut(vec_ptr.add(drop_offset), drop_len); + let to_drop = vec_ptr.add(drop_offset).cast_slice(drop_len); ptr::drop_in_place(to_drop); } } diff --git a/library/alloc/src/vec/extract_if.rs b/library/alloc/src/vec/extract_if.rs index 35eb7549738df..a4c4c19682195 100644 --- a/library/alloc/src/vec/extract_if.rs +++ b/library/alloc/src/vec/extract_if.rs @@ -130,20 +130,25 @@ where A: Allocator, { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let peek = if self.idx < self.end { - // This has to use pointer arithmetic as `self.vec[self.idx]` or - // `self.vec.get_unchecked(self.idx)` wouldn't work since we - // temporarily set the length of `self.vec` to zero. - // - // SAFETY: - // Since `self.idx` is smaller than `self.end` and `self.end` is - // smaller than `self.old_len`, `idx` is valid for indexing the - // buffer. Also, per the invariant of `self.idx`, this element - // has not been inspected/moved out yet. - Some(unsafe { &*self.vec.as_ptr().add(self.idx) }) - } else { - None - }; - f.debug_struct("ExtractIf").field("peek", &peek).finish_non_exhaustive() + // We have to use pointer arithmetics here, + // because the length of `self.vec` is temporarily set to 0. + let start = self.vec.as_ptr(); + + // SAFETY: we always keep first `self.idx - self.del` elements valid. + let retained = unsafe { slice::from_raw_parts(start, self.idx - self.del) }; + + // SAFETY: we have not yet touched elements starting at `self.idx`. + let valid_tail = + unsafe { slice::from_raw_parts(start.add(self.idx), self.old_len - self.idx) }; + + // SAFETY: `end - idx <= old_len - idx`, because `end <= old_len`. Also `idx <= end` by invariant. + let (remainder, skipped_tail) = + unsafe { valid_tail.split_at_unchecked(self.end - self.idx) }; + + f.debug_struct("ExtractIf") + .field("retained", &retained) + .field("remainder", &remainder) + .field("skipped_tail", &skipped_tail) + .finish_non_exhaustive() } } diff --git a/library/alloc/src/vec/in_place_collect.rs b/library/alloc/src/vec/in_place_collect.rs index 8a7c0b92eccf6..a5566f70fea3c 100644 --- a/library/alloc/src/vec/in_place_collect.rs +++ b/library/alloc/src/vec/in_place_collect.rs @@ -328,9 +328,7 @@ where mem::forget(dst_guard); - let vec = unsafe { Vec::from_parts(dst_buf, len, dst_cap) }; - - vec + unsafe { Vec::from_parts(dst_buf, len, dst_cap) } } fn write_in_place_with_drop( diff --git a/library/alloc/src/vec/in_place_drop.rs b/library/alloc/src/vec/in_place_drop.rs index c8cc758ac15c4..5c3d598cdef0c 100644 --- a/library/alloc/src/vec/in_place_drop.rs +++ b/library/alloc/src/vec/in_place_drop.rs @@ -1,5 +1,5 @@ use core::marker::PhantomData; -use core::ptr::{self, NonNull, drop_in_place}; +use core::ptr::NonNull; use crate::alloc::Global; use crate::raw_vec::RawVec; @@ -20,9 +20,7 @@ impl InPlaceDrop { impl Drop for InPlaceDrop { #[inline] fn drop(&mut self) { - unsafe { - ptr::drop_in_place(ptr::slice_from_raw_parts_mut(self.inner, self.len())); - } + unsafe { self.inner.cast_slice(self.len()).drop_in_place() } } } @@ -42,7 +40,7 @@ impl Drop for InPlaceDstDataSrcBufDrop { unsafe { let _drop_allocation = RawVec::::from_nonnull_in(self.ptr.cast::(), self.src_cap, Global); - drop_in_place(core::ptr::slice_from_raw_parts_mut::(self.ptr.as_ptr(), self.len)); + self.ptr.as_ptr().cast_slice(self.len).drop_in_place(); }; } } diff --git a/library/alloc/src/vec/into_iter.rs b/library/alloc/src/vec/into_iter.rs index 8cbf1088ff845..db07fb546a9af 100644 --- a/library/alloc/src/vec/into_iter.rs +++ b/library/alloc/src/vec/into_iter.rs @@ -11,8 +11,7 @@ use core::num::NonZero; use core::ops::Deref; use core::panic::UnwindSafe; use core::ptr::{self, NonNull}; -use core::slice::{self}; -use core::{array, fmt}; +use core::{array, fmt, slice}; use safety::requires; @@ -120,7 +119,7 @@ impl IntoIter { } fn as_raw_mut_slice(&mut self) -> *mut [T] { - ptr::slice_from_raw_parts_mut(self.ptr.as_ptr(), self.len()) + self.ptr.as_ptr().cast_slice(self.len()) } /// Drops remaining elements and relinquishes the backing allocation. @@ -164,12 +163,51 @@ impl IntoIter { } /// Forgets to Drop the remaining elements while still allowing the backing allocation to be freed. + /// + /// This method does not consume `self`, and leaves deallocation to `impl Drop for IntoIter`. + /// If consuming `self` is possible, consider calling + /// [`Self::forget_remaining_elements_and_dealloc()`] instead. pub(crate) fn forget_remaining_elements(&mut self) { // For the ZST case, it is crucial that we mutate `end` here, not `ptr`. // `ptr` must stay aligned, while `end` may be unaligned. self.end = self.ptr.as_ptr(); } + /// Forgets to Drop the remaining elements and frees the backing allocation. + /// Consuming version of [`Self::forget_remaining_elements()`]. + /// + /// This can be used in place of `drop(self)` when `self` is known to be exhausted, + /// to avoid producing a needless `drop_in_place::<[T]>()`. + #[inline] + pub(crate) fn forget_remaining_elements_and_dealloc(self) { + let mut this = ManuallyDrop::new(self); + // SAFETY: `this` is in ManuallyDrop, so it will not be double-freed. + unsafe { + this.dealloc_only(); + } + } + + /// Frees the allocation, without checking or dropping anything else. + /// + /// The safe version of this method is [`Self::forget_remaining_elements_and_dealloc()`]. + /// This function exists only to share code between that method and the `impl Drop`. + /// + /// # Safety + /// + /// This function must only be called with an [`IntoIter`] that is not going to be dropped + /// or otherwise used in any way, either because it is being forgotten or because its `Drop` + /// is already executing; otherwise a double-free will occur, and possibly a read from freed + /// memory if there are any remaining elements. + #[inline] + unsafe fn dealloc_only(&mut self) { + unsafe { + // SAFETY: our caller promises not to touch `*self` again + let alloc = ManuallyDrop::take(&mut self.alloc); + // RawVec handles deallocation + let _ = RawVec::from_nonnull_in(self.buf, self.cap, alloc); + } + } + #[cfg(not(no_global_oom_handling))] #[inline] pub(crate) fn into_vecdeque(self) -> VecDeque { @@ -248,7 +286,7 @@ impl Iterator for IntoIter { #[inline] fn advance_by(&mut self, n: usize) -> Result<(), NonZero> { let step_size = self.len().min(n); - let to_drop = ptr::slice_from_raw_parts_mut(self.ptr.as_ptr(), step_size); + let to_drop = self.ptr.as_ptr().cast_slice(step_size); if T::IS_ZST { // See `next` for why we sub `end` here. self.end = self.end.wrapping_byte_sub(step_size); @@ -333,6 +371,12 @@ impl Iterator for IntoIter { accum = f(accum, tmp); } } + + // There are in fact no remaining elements to forget, but by doing this we can avoid + // potentially generating a needless loop to drop the elements that cannot exist at + // this point. + self.forget_remaining_elements_and_dealloc(); + accum } @@ -407,6 +451,47 @@ impl DoubleEndedIterator for IntoIter { } } + #[inline] + fn next_chunk_back(&mut self) -> Result<[T; N], core::array::IntoIter> { + let mut raw_ary = [const { MaybeUninit::uninit() }; N]; + + let len = self.len(); + + if T::IS_ZST { + if len < N { + self.forget_remaining_elements(); + // Safety: ZSTs can be conjured ex nihilo, only the amount has to be correct + return Err(unsafe { array::IntoIter::new_unchecked(raw_ary, N - len..N) }); + } + + self.end = self.end.wrapping_byte_sub(N); + // Safety: ditto + return Ok(unsafe { MaybeUninit::array_assume_init(raw_ary) }); + } + + if len < N { + // Safety: `len` indicates that this many elements are available and we just checked that + // it fits into the array. + unsafe { + ptr::copy_nonoverlapping(self.ptr.as_ptr(), raw_ary.as_mut_ptr() as *mut T, len); + self.forget_remaining_elements(); + return Err(array::IntoIter::new_unchecked(raw_ary, 0..len)); + } + } + + // Safety: `len` is larger than the array size. Copy a fixed amount here to fully initialize + // the array. + unsafe { + ptr::copy_nonoverlapping( + self.ptr.add(len - N).as_ptr(), + raw_ary.as_mut_ptr() as *mut T, + N, + ); + self.end = self.end.sub(N); + Ok(MaybeUninit::array_assume_init(raw_ary)) + } + } + #[inline] fn advance_back_by(&mut self, n: usize) -> Result<(), NonZero> { let step_size = self.len().min(n); @@ -419,9 +504,9 @@ impl DoubleEndedIterator for IntoIter { } let to_drop = if T::IS_ZST { // ZST may cause unalignment - ptr::slice_from_raw_parts_mut(ptr::NonNull::::dangling().as_ptr(), step_size) + ptr::NonNull::::dangling().as_ptr().cast_slice(step_size) } else { - ptr::slice_from_raw_parts_mut(self.end as *mut T, step_size) + self.end.cast::().cast_mut().cast_slice(step_size) }; // SAFETY: same as for advance_by() unsafe { @@ -472,8 +557,8 @@ where #[doc(hidden)] #[unstable(issue = "none", feature = "std_internals")] -#[rustc_unsafe_specialization_marker] -pub trait NonDrop {} +#[unsafe(rustc_allow_lifetime_dependent_specialization)] +trait NonDrop {} // T: Copy as approximation for !Drop since get_unchecked does not advance self.ptr // and thus we can't implement drop-handling @@ -507,10 +592,7 @@ unsafe impl<#[may_dangle] T, A: Allocator> Drop for IntoIter { impl Drop for DropGuard<'_, T, A> { fn drop(&mut self) { unsafe { - // `IntoIter::alloc` is not used anymore after this and will be dropped by RawVec - let alloc = ManuallyDrop::take(&mut self.0.alloc); - // RawVec handles deallocation - let _ = RawVec::from_nonnull_in(self.0.buf, self.0.cap, alloc); + self.0.dealloc_only(); } } } diff --git a/library/alloc/src/vec/mod.rs b/library/alloc/src/vec/mod.rs index 7530192fcb3e7..9e67a1e7f08e6 100644 --- a/library/alloc/src/vec/mod.rs +++ b/library/alloc/src/vec/mod.rs @@ -75,20 +75,16 @@ #[cfg(not(no_global_oom_handling))] use core::clone::TrivialClone; -#[cfg(not(no_global_oom_handling))] -use core::cmp; use core::cmp::Ordering; use core::hash::{Hash, Hasher}; #[cfg(not(no_global_oom_handling))] use core::iter; -#[cfg(not(no_global_oom_handling))] -use core::marker::Destruct; -use core::marker::{Freeze, PhantomData}; +use core::marker::{Destruct, Freeze, PhantomData}; use core::mem::{self, Assume, ManuallyDrop, MaybeUninit, SizedTypeProperties, TransmuteFrom}; use core::ops::{self, Index, IndexMut, Range, RangeBounds}; use core::ptr::{self, NonNull}; use core::slice::{self, SliceIndex}; -use core::{fmt, hint, intrinsics, ub_checks}; +use core::{cmp, fmt, hint, intrinsics, ub_checks}; #[stable(feature = "extract_if", since = "1.87.0")] pub use self::extract_if::ExtractIf; @@ -558,7 +554,7 @@ impl Vec { /// (`T` having a less strict alignment is not sufficient, the alignment really /// needs to be equal to satisfy the [`dealloc`] requirement that memory must be /// allocated and deallocated with the same layout.) - /// * The size of `T` times the `capacity` (ie. the allocated size in bytes), if + /// * The size of `T` times the `capacity` (i.e. the allocated size in bytes), if /// nonzero, needs to be the same size as the pointer was allocated with. /// (Because similar to alignment, [`dealloc`] must be called with the same /// layout `size`.) @@ -623,7 +619,7 @@ impl Vec { /// use std::alloc::{alloc, Layout}; /// /// fn main() { - /// let layout = Layout::array::(16).expect("overflow cannot happen"); + /// let layout = Layout::array::(16).expect("16 u32s take 64 bytes, so it shouldn't overflow"); /// /// let vec = unsafe { /// let mem = alloc(layout).cast::(); @@ -642,7 +638,8 @@ impl Vec { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] - pub unsafe fn from_raw_parts(ptr: *mut T, length: usize, capacity: usize) -> Self { + #[rustc_const_unstable(feature = "const_heap", issue = "79597")] + pub const unsafe fn from_raw_parts(ptr: *mut T, length: usize, capacity: usize) -> Self { unsafe { Self::from_raw_parts_in(ptr, length, capacity, Global) } } @@ -660,7 +657,7 @@ impl Vec { /// (`T` having a less strict alignment is not sufficient, the alignment really /// needs to be equal to satisfy the [`dealloc`] requirement that memory must be /// allocated and deallocated with the same layout.) - /// * The size of `T` times the `capacity` (ie. the allocated size in bytes) needs + /// * The size of `T` times the `capacity` (i.e. the allocated size in bytes) needs /// to be the same size as the pointer was allocated with. (Because similar to /// alignment, [`dealloc`] must be called with the same layout `size`.) /// * `length` needs to be less than or equal to `capacity`. @@ -698,8 +695,6 @@ impl Vec { /// # Examples /// /// ``` - /// #![feature(box_vec_non_null)] - /// /// let v = vec![1, 2, 3]; /// /// // Deconstruct the vector into parts. @@ -720,13 +715,11 @@ impl Vec { /// Using memory that was allocated elsewhere: /// /// ```rust - /// #![feature(box_vec_non_null)] - /// /// use std::alloc::{alloc, Layout}; /// use std::ptr::NonNull; /// /// fn main() { - /// let layout = Layout::array::(16).expect("overflow cannot happen"); + /// let layout = Layout::array::(16).expect("16 u32s take 64 bytes, so it shouldn't overflow"); /// /// let vec = unsafe { /// let Some(mem) = NonNull::new(alloc(layout).cast::()) else { @@ -743,8 +736,9 @@ impl Vec { /// } /// ``` #[inline] - #[unstable(feature = "box_vec_non_null", issue = "130364")] - pub unsafe fn from_parts(ptr: NonNull, length: usize, capacity: usize) -> Self { + #[stable(feature = "box_vec_non_null", since = "1.99.0")] + #[rustc_const_unstable(feature = "const_heap", issue = "79597")] + pub const unsafe fn from_parts(ptr: NonNull, length: usize, capacity: usize) -> Self { unsafe { Self::from_parts_in(ptr, length, capacity, Global) } } @@ -838,7 +832,8 @@ impl Vec { /// ``` #[must_use = "losing the pointer will leak memory"] #[stable(feature = "vec_into_raw_parts", since = "1.93.0")] - pub fn into_raw_parts(self) -> (*mut T, usize, usize) { + #[rustc_const_unstable(feature = "const_heap", issue = "79597")] + pub const fn into_raw_parts(self) -> (*mut T, usize, usize) { let mut me = ManuallyDrop::new(self); (me.as_mut_ptr(), me.len(), me.capacity()) } @@ -862,8 +857,6 @@ impl Vec { /// # Examples /// /// ``` - /// #![feature(box_vec_non_null)] - /// /// let v: Vec = vec![-1, 0, 1]; /// /// let (ptr, len, cap) = v.into_parts(); @@ -878,8 +871,9 @@ impl Vec { /// assert_eq!(rebuilt, [4294967295, 0, 1]); /// ``` #[must_use = "losing the pointer will leak memory"] - #[unstable(feature = "box_vec_non_null", issue = "130364")] - pub fn into_parts(self) -> (NonNull, usize, usize) { + #[stable(feature = "box_vec_non_null", since = "1.99.0")] + #[rustc_const_unstable(feature = "const_heap", issue = "79597")] + pub const fn into_parts(self) -> (NonNull, usize, usize) { let (ptr, len, capacity) = self.into_raw_parts(); // SAFETY: A `Vec` always has a non-null pointer. (unsafe { NonNull::new_unchecked(ptr) }, len, capacity) @@ -896,9 +890,17 @@ impl Vec { where T: Freeze, { - unsafe { core::intrinsics::const_make_global(self.as_mut_ptr().cast()) }; - let me = ManuallyDrop::new(self); - unsafe { slice::from_raw_parts(me.as_ptr(), me.len) } + // `const_make_global` requires the pointer to point to the beginning of a heap allocation, + // which is not the case when `self.capacity()` is 0, or if `T::IS_ZST`, + // which is why we instead return a new slice in this case. + if self.capacity() == 0 || T::IS_ZST { + let me = ManuallyDrop::new(self); + unsafe { slice::from_raw_parts(NonNull::::dangling().as_ptr(), me.len) } + } else { + unsafe { core::intrinsics::const_make_global(self.as_mut_ptr().cast()) }; + let me = ManuallyDrop::new(self); + unsafe { slice::from_raw_parts(me.as_ptr(), me.len) } + } } } @@ -1020,7 +1022,7 @@ const impl Vec { /// vector's elements to a larger allocation. This expensive operation is /// offset by the *capacity* *O*(1) insertions it allows. #[inline] - #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "push_mut", since = "1.95.0")] #[must_use = "if you don't need a reference to the value, use `Vec::push` instead"] pub fn push_mut(&mut self, value: T) -> &mut T { // Inform codegen that the length does not change across grow_one(). @@ -1052,8 +1054,7 @@ impl Vec { /// /// use std::alloc::System; /// - /// # #[allow(unused_mut)] - /// let mut vec: Vec = Vec::new_in(System); + /// let vec: Vec = Vec::new_in(System); /// ``` #[inline] #[unstable(feature = "allocator_api", issue = "32838")] @@ -1092,7 +1093,7 @@ impl Vec { /// (`T` having a less strict alignment is not sufficient, the alignment really /// needs to be equal to satisfy the [`dealloc`] requirement that memory must be /// allocated and deallocated with the same layout.) - /// * The size of `T` times the `capacity` (ie. the allocated size in bytes) needs + /// * The size of `T` times the `capacity` (i.e. the allocated size in bytes) needs /// to be the same size as the pointer was allocated with. (Because similar to /// alignment, [`dealloc`] must be called with the same layout `size`.) /// * `length` needs to be less than or equal to `capacity`. @@ -1139,7 +1140,7 @@ impl Vec { /// v.push(3); /// /// // Deconstruct the vector into parts. - /// let (p, len, cap, alloc) = v.into_raw_parts_with_alloc(); + /// let (p, len, cap, alloc) = v.into_raw_parts_with_allocator(); /// /// unsafe { /// // Overwrite memory with 4, 5, 6 @@ -1161,7 +1162,7 @@ impl Vec { /// use std::alloc::{AllocError, Allocator, Global, Layout}; /// /// fn main() { - /// let layout = Layout::array::(16).expect("overflow cannot happen"); + /// let layout = Layout::array::(16).expect("16 u32s take 64 bytes, so it shouldn't overflow"); /// /// let vec = unsafe { /// let mem = match Global.allocate(layout) { @@ -1180,7 +1181,13 @@ impl Vec { /// ``` #[inline] #[unstable(feature = "allocator_api", issue = "32838")] - pub unsafe fn from_raw_parts_in(ptr: *mut T, length: usize, capacity: usize, alloc: A) -> Self { + #[rustc_const_unstable(feature = "allocator_api", issue = "32838")] + pub const unsafe fn from_raw_parts_in( + ptr: *mut T, + length: usize, + capacity: usize, + alloc: A, + ) -> Self { ub_checks::assert_unsafe_precondition!( check_library_ub, "Vec::from_raw_parts_in requires that length <= capacity", @@ -1203,7 +1210,7 @@ impl Vec { /// (`T` having a less strict alignment is not sufficient, the alignment really /// needs to be equal to satisfy the [`dealloc`] requirement that memory must be /// allocated and deallocated with the same layout.) - /// * The size of `T` times the `capacity` (ie. the allocated size in bytes) needs + /// * The size of `T` times the `capacity` (i.e. the allocated size in bytes) needs /// to be the same size as the pointer was allocated with. (Because similar to /// alignment, [`dealloc`] must be called with the same layout `size`.) /// * `length` needs to be less than or equal to `capacity`. @@ -1238,7 +1245,7 @@ impl Vec { /// # Examples /// /// ``` - /// #![feature(allocator_api, box_vec_non_null)] + /// #![feature(allocator_api)] /// /// use std::alloc::System; /// @@ -1248,7 +1255,7 @@ impl Vec { /// v.push(3); /// /// // Deconstruct the vector into parts. - /// let (p, len, cap, alloc) = v.into_parts_with_alloc(); + /// let (p, len, cap, alloc) = v.into_parts_with_allocator(); /// /// unsafe { /// // Overwrite memory with 4, 5, 6 @@ -1265,12 +1272,12 @@ impl Vec { /// Using memory that was allocated elsewhere: /// /// ```rust - /// #![feature(allocator_api, box_vec_non_null)] + /// #![feature(allocator_api)] /// /// use std::alloc::{AllocError, Allocator, Global, Layout}; /// /// fn main() { - /// let layout = Layout::array::(16).expect("overflow cannot happen"); + /// let layout = Layout::array::(16).expect("16 u32s take 64 bytes, so it shouldn't overflow"); /// /// let vec = unsafe { /// let mem = match Global.allocate(layout) { @@ -1289,8 +1296,13 @@ impl Vec { /// ``` #[inline] #[unstable(feature = "allocator_api", issue = "32838")] - // #[unstable(feature = "box_vec_non_null", issue = "130364")] - pub unsafe fn from_parts_in(ptr: NonNull, length: usize, capacity: usize, alloc: A) -> Self { + #[rustc_const_unstable(feature = "allocator_api", issue = "32838")] + pub const unsafe fn from_parts_in( + ptr: NonNull, + length: usize, + capacity: usize, + alloc: A, + ) -> Self { ub_checks::assert_unsafe_precondition!( check_library_ub, "Vec::from_parts_in requires that length <= capacity", @@ -1325,7 +1337,7 @@ impl Vec { /// v.push(0); /// v.push(1); /// - /// let (ptr, len, cap, alloc) = v.into_raw_parts_with_alloc(); + /// let (ptr, len, cap, alloc) = v.into_raw_parts_with_allocator(); /// /// let rebuilt = unsafe { /// // We can now make changes to the components, such as @@ -1338,7 +1350,8 @@ impl Vec { /// ``` #[must_use = "losing the pointer will leak memory"] #[unstable(feature = "allocator_api", issue = "32838")] - pub fn into_raw_parts_with_alloc(self) -> (*mut T, usize, usize, A) { + #[rustc_const_unstable(feature = "allocator_api", issue = "32838")] + pub const fn into_raw_parts_with_allocator(self) -> (*mut T, usize, usize, A) { let mut me = ManuallyDrop::new(self); let len = me.len(); let capacity = me.capacity(); @@ -1365,7 +1378,7 @@ impl Vec { /// # Examples /// /// ``` - /// #![feature(allocator_api, box_vec_non_null)] + /// #![feature(allocator_api)] /// /// use std::alloc::System; /// @@ -1374,7 +1387,7 @@ impl Vec { /// v.push(0); /// v.push(1); /// - /// let (ptr, len, cap, alloc) = v.into_parts_with_alloc(); + /// let (ptr, len, cap, alloc) = v.into_parts_with_allocator(); /// /// let rebuilt = unsafe { /// // We can now make changes to the components, such as @@ -1387,9 +1400,9 @@ impl Vec { /// ``` #[must_use = "losing the pointer will leak memory"] #[unstable(feature = "allocator_api", issue = "32838")] - // #[unstable(feature = "box_vec_non_null", issue = "130364")] - pub fn into_parts_with_alloc(self) -> (NonNull, usize, usize, A) { - let (ptr, len, capacity, alloc) = self.into_raw_parts_with_alloc(); + #[rustc_const_unstable(feature = "allocator_api", issue = "32838")] + pub const fn into_parts_with_allocator(self) -> (NonNull, usize, usize, A) { + let (ptr, len, capacity, alloc) = self.into_raw_parts_with_allocator(); // SAFETY: A `Vec` always has a non-null pointer. (unsafe { NonNull::new_unchecked(ptr) }, len, capacity, alloc) } @@ -1508,7 +1521,7 @@ impl Vec { /// /// Ok(output) /// } - /// # process_data(&[1, 2, 3]).expect("why is the test harness OOMing on 12 bytes?"); + /// # process_data(&[1, 2, 3]).expect("this test needs 12 bytes, so it shouldn't fail"); /// ``` #[stable(feature = "try_reserve", since = "1.57.0")] pub fn try_reserve(&mut self, additional: usize) -> Result<(), TryReserveError> { @@ -1551,7 +1564,7 @@ impl Vec { /// /// Ok(output) /// } - /// # process_data(&[1, 2, 3]).expect("why is the test harness OOMing on 12 bytes?"); + /// # process_data(&[1, 2, 3]).expect("this test needs 12 bytes, so it shouldn't fail"); /// ``` #[stable(feature = "try_reserve", since = "1.57.0")] pub fn try_reserve_exact(&mut self, additional: usize) -> Result<(), TryReserveError> { @@ -1613,6 +1626,73 @@ impl Vec { } } + /// Tries to shrink the capacity of the vector as much as possible + /// + /// The behavior of this method depends on the allocator, which may either shrink the vector + /// in-place or reallocate. The resulting vector might still have some excess capacity, just as + /// is the case for [`with_capacity`]. See [`Allocator::shrink`] for more details. + /// + /// [`with_capacity`]: Vec::with_capacity + /// + /// # Errors + /// + /// This function returns an error if the allocator fails to shrink the allocation, + /// the vector thereafter is still safe to use, the capacity remains unchanged + /// however. See [`Allocator::shrink`]. + /// + /// # Examples + /// + /// ``` + /// #![feature(vec_fallible_shrink)] + /// + /// let mut vec = Vec::with_capacity(10); + /// vec.extend([1, 2, 3]); + /// assert!(vec.capacity() >= 10); + /// vec.try_shrink_to_fit().expect("for this test, shrink shouldn't fail"); + /// assert!(vec.capacity() >= 3); + /// ``` + #[unstable(feature = "vec_fallible_shrink", issue = "152350")] + #[inline] + pub fn try_shrink_to_fit(&mut self) -> Result<(), TryReserveError> { + if self.capacity() > self.len { self.buf.try_shrink_to_fit(self.len) } else { Ok(()) } + } + + /// Shrinks the capacity of the vector with a lower bound. + /// + /// The capacity will remain at least as large as both the length + /// and the supplied value. + /// + /// If the current capacity is less than the lower limit, this is a no-op. + /// + /// # Errors + /// + /// This function returns an error if the allocator fails to shrink the allocation, + /// the vector thereafter is still safe to use, the capacity remains unchanged + /// however. See [`Allocator::shrink`]. + /// + /// # Examples + /// + /// ``` + /// #![feature(vec_fallible_shrink)] + /// + /// let mut vec = Vec::with_capacity(10); + /// vec.extend([1, 2, 3]); + /// assert!(vec.capacity() >= 10); + /// vec.try_shrink_to(4).expect("for this test, shrink shouldn't fail"); + /// assert!(vec.capacity() >= 4); + /// vec.try_shrink_to(0).expect("this is a no-op and thus the allocator isn't involved."); + /// assert!(vec.capacity() >= 3); + /// ``` + #[unstable(feature = "vec_fallible_shrink", issue = "152350")] + #[inline] + pub fn try_shrink_to(&mut self, min_capacity: usize) -> Result<(), TryReserveError> { + if self.capacity() > min_capacity { + self.buf.try_shrink_to_fit(cmp::max(self.len, min_capacity)) + } else { + Ok(()) + } + } + /// Converts the vector into [`Box<[T]>`][owned slice]. /// /// Before doing the conversion, this method discards excess capacity like [`shrink_to_fit`]. @@ -1650,6 +1730,38 @@ impl Vec { } } + /// Converts the Vec into a boxed array. This conversion will discard any spare capacity, + /// if there is any, see [`Vec::shrink_to_fit`]. + /// If you merely wish for a reference to an array, use [`as_array`](https://doc.rust-lang.org/stable/std/primitive.slice.html#method.as_array). + /// + /// # Errors + /// + /// Returns the original `Vec` in the `Err` variant if [`Vec::len`] does not equal `N`. + /// + /// # Examples + /// + /// ``` + /// #![feature(alloc_slice_into_array)] + /// let vec: Vec = vec![1, 2, 3]; + /// let box_array: Box<[i32; 3]> = vec.clone().into_array().unwrap(); + /// let not_enough_elements: Result, Vec> = vec.into_array::<4>(); + /// assert_eq!(not_enough_elements, Err(vec![1, 2, 3])); + /// ``` + #[cfg(not(no_global_oom_handling))] + #[unstable(feature = "alloc_slice_into_array", issue = "148082")] + #[must_use] + pub fn into_array(self) -> Result, Self> { + if self.len() == N { + // SAFETY: `Box::into_array` is guaranteed to return `Ok` if the + // length of the slice is equal to `N`. + // `self.into_boxed_slice().len()` is equal to `self.len()`, + // which we just checked. + Ok(unsafe { self.into_boxed_slice().into_array().unwrap_unchecked() }) + } else { + Err(self) + } + } + /// Shortens the vector, keeping the first `len` elements and dropping /// the rest. /// @@ -1694,6 +1806,9 @@ impl Vec { /// [`drain`]: Vec::drain #[stable(feature = "rust1", since = "1.0.0")] pub fn truncate(&mut self, len: usize) { + // SAFETY: `BufWriter::flush_buf` assumes that this will not + // de-initialize any elements of the spare capacity. + // This is safe because: // // * the slice passed to `drop_in_place` is valid; the `len > self.len` @@ -1709,7 +1824,7 @@ impl Vec { return; } let remaining_len = self.len - len; - let s = ptr::slice_from_raw_parts_mut(self.as_mut_ptr().add(len), remaining_len); + let s = self.as_mut_ptr().add(len).cast_slice(remaining_len); self.len = len; ptr::drop_in_place(s); } @@ -1767,10 +1882,13 @@ impl Vec { #[rustc_diagnostic_item = "vec_as_mut_slice"] #[rustc_const_stable(feature = "const_vec_string_slice", since = "1.87.0")] pub const fn as_mut_slice(&mut self) -> &mut [T] { + // SAFETY: `BufWriter::flush_buf` assumes that this will not + // de-initialize any elements of the spare capacity. + // SAFETY: `slice::from_raw_parts_mut` requires pointee is a contiguous, aligned buffer of // size `len` containing properly-initialized `T`s. Data must not be accessed through any // other pointer for the returned lifetime. Further, `len * size_of::` <= - // `ISIZE::MAX` and allocation does not "wrap" through overflowing memory addresses. + // `isize::MAX` and allocation does not "wrap" through overflowing memory addresses. // // * Vec API guarantees that self.buf: // * contains only properly-initialized items within 0..len @@ -1955,7 +2073,7 @@ impl Vec { /// # Examples /// /// ``` - /// #![feature(box_vec_non_null)] + /// #![feature(vec_as_non_null)] /// /// // Allocate vector big enough for 4 elements. /// let size = 4; @@ -1975,7 +2093,7 @@ impl Vec { /// Due to the aliasing guarantee, the following code is legal: /// /// ```rust - /// #![feature(box_vec_non_null)] + /// #![feature(vec_as_non_null)] /// /// unsafe { /// let mut v = vec![0]; @@ -1991,8 +2109,9 @@ impl Vec { /// [`as_mut_ptr`]: Vec::as_mut_ptr /// [`as_ptr`]: Vec::as_ptr /// [`as_non_null`]: Vec::as_non_null - #[unstable(feature = "box_vec_non_null", issue = "130364")] - #[rustc_const_unstable(feature = "box_vec_non_null", issue = "130364")] + #[unstable(feature = "vec_as_non_null", issue = "157843")] + #[rustc_const_unstable(feature = "vec_as_non_null", issue = "157843")] + #[rustc_as_ptr] #[inline] pub const fn as_non_null(&mut self) -> NonNull { self.buf.non_null() @@ -2000,8 +2119,9 @@ impl Vec { /// Returns a reference to the underlying allocator. #[unstable(feature = "allocator_api", issue = "32838")] + #[rustc_const_unstable(feature = "const_heap", issue = "79597")] #[inline] - pub fn allocator(&self) -> &A { + pub const fn allocator(&self) -> &A { self.buf.allocator() } @@ -2093,7 +2213,8 @@ impl Vec { /// [`spare_capacity_mut()`]: Vec::spare_capacity_mut #[inline] #[stable(feature = "rust1", since = "1.0.0")] - pub unsafe fn set_len(&mut self, new_len: usize) { + #[rustc_const_unstable(feature = "const_heap", issue = "79597")] + pub const unsafe fn set_len(&mut self, new_len: usize) { ub_checks::assert_unsafe_precondition!( check_library_ub, "Vec::set_len requires that new_len <= capacity()", @@ -2206,7 +2327,7 @@ impl Vec { /// the insertion index is 0. #[cfg(not(no_global_oom_handling))] #[inline] - #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "push_mut", since = "1.95.0")] #[track_caller] #[must_use = "if you don't need a reference to the value, use `Vec::insert` instead"] pub fn insert_mut(&mut self, index: usize, element: T) -> &mut T { @@ -2501,23 +2622,49 @@ impl Vec { self.dedup_by(|a, b| key(a) == key(b)) } - /// Removes all but the first of consecutive elements in the vector satisfying a given equality - /// relation. + /// Removes all but the first of consecutive elements in the vector that are + /// "equal" according to the given predicate function. /// - /// The `same_bucket` function is passed references to two elements from the vector and - /// must determine if the elements compare equal. The elements are passed in opposite order - /// from their order in the slice, so if `same_bucket(a, b)` returns `true`, `a` is removed. + /// The predicate `same_bucket(x, p)` is passed references to two elements. + /// If it returns `true`, the element `x` is removed from the vector. /// - /// If the vector is sorted, this removes all duplicates. + /// The element `p` occurs *before* `x` in the vector (`[.., p, .., x, ..]`), + /// so `same_bucket(x, p)` is receiving them in reversed order (unlike [`windows`]). + /// + /// If the vector is sorted, this removes all duplicates. For more complicated predicates + /// however, the order (ascending vs. descending) can matter. + /// + /// [`windows`]: slice::windows /// /// # Examples /// /// ``` /// let mut vec = vec!["foo", "bar", "Bar", "baz", "bar"]; + /// vec.dedup_by(|x, p| x.eq_ignore_ascii_case(p)); + /// assert_eq!(vec, ["foo", "bar", "baz", "bar"]); + /// ``` /// - /// vec.dedup_by(|a, b| a.eq_ignore_ascii_case(b)); + /// Both references passed to `same_bucket` are mutable. + /// This allows merging elements by mutating `p` and returning `true`: /// - /// assert_eq!(vec, ["foo", "bar", "baz", "bar"]); + /// ``` + /// let mut ranges = vec![1..2, 2..4, 2..5, 8..9]; + /// + /// // Sort ranges by start, and if equal, by end (lexicographically) + /// // Sorting in reverse instead (`x.start.cmp(&p.start)...`) would later fail + /// ranges.sort_unstable_by(|p, x| p.start.cmp(&x.start).then(p.end.cmp(&x.end))); + /// + /// // Merge touching (`1..2` and `2..4`) and then overlapping (`1..4` and `2..5`) ranges + /// ranges.dedup_by(|x, p| { + /// if p.end >= x.start { + /// p.end = p.end.max(x.end); + /// true + /// } else { + /// false + /// } + /// }); + /// + /// assert_eq!(ranges, [1..5, 8..9]); /// ``` #[stable(feature = "dedup_by", since = "1.16.0")] pub fn dedup_by(&mut self, mut same_bucket: F) @@ -2810,8 +2957,26 @@ impl Vec { #[cfg(not(no_global_oom_handling))] #[inline] unsafe fn append_elements(&mut self, other: *const [T]) { + self.reserve(other.len()); + unsafe { + self.append_elements_unreserved(other); + } + } + + /// Appends elements to `self` from other buffer, returning [`TryReserveError`] on OOM. + #[inline] + unsafe fn try_append_elements(&mut self, other: *const [T]) -> Result<(), TryReserveError> { + self.try_reserve(other.len())?; + unsafe { + self.append_elements_unreserved(other); + } + Ok(()) + } + + /// Appends elements to `self` from other buffer without reserving additional capacity. + #[inline] + unsafe fn append_elements_unreserved(&mut self, other: *const [T]) { let count = other.len(); - self.reserve(count); let len = self.len(); if count > 0 { unsafe { @@ -2901,6 +3066,10 @@ impl Vec { #[inline] #[stable(feature = "rust1", since = "1.0.0")] pub fn clear(&mut self) { + // Though this is equivalent to `truncate(0)`, the manual version + // optimizes better, justifying the additional complexity + // (see #96002 and #154095 for context). + let elems: *mut [T] = self.as_mut_slice(); // SAFETY: @@ -3126,8 +3295,9 @@ impl Vec { /// assert_eq!(&v, &[0, 1, 2]); /// ``` #[stable(feature = "vec_spare_capacity", since = "1.60.0")] + #[rustc_const_unstable(feature = "const_heap", issue = "79597")] #[inline] - pub fn spare_capacity_mut(&mut self) -> &mut [MaybeUninit] { + pub const fn spare_capacity_mut(&mut self) -> &mut [MaybeUninit] { // Note: // This method is not implemented in terms of `split_at_spare_mut`, // to prevent invalidation of pointers to the buffer. @@ -3191,8 +3361,9 @@ impl Vec { /// assert_eq!(&v, &[1, 1, 2, 4, 8, 12, 16]); /// ``` #[unstable(feature = "vec_split_at_spare", issue = "81944")] + #[rustc_const_unstable(feature = "const_heap", issue = "79597")] #[inline] - pub fn split_at_spare_mut(&mut self) -> (&mut [T], &mut [MaybeUninit]) { + pub const fn split_at_spare_mut(&mut self) -> (&mut [T], &mut [MaybeUninit]) { // SAFETY: // - len is ignored and so never changed let (init, spare, _) = unsafe { self.split_at_spare_mut_with_len() }; @@ -3202,7 +3373,7 @@ impl Vec { /// Safety: changing returned .2 (&mut usize) is considered the same as calling `.set_len(_)`. /// /// This method provides unique access to all vec parts at once in `extend_from_within`. - unsafe fn split_at_spare_mut_with_len( + const unsafe fn split_at_spare_mut_with_len( &mut self, ) -> (&mut [T], &mut [MaybeUninit], &mut usize) { let ptr = self.as_mut_ptr(); @@ -3268,10 +3439,10 @@ impl Vec { self.buf.shrink_to_fit(cap - cap_remainder); } - let (ptr, _, _, alloc) = self.into_raw_parts_with_alloc(); + let (ptr, _, _, alloc) = self.into_raw_parts_with_allocator(); // SAFETY: - // - `ptr` and `alloc` were just returned from `self.into_raw_parts_with_alloc()` + // - `ptr` and `alloc` were just returned from `self.into_raw_parts_with_allocator()` // - `[T; N]` has the same alignment as `T` // - `size_of::<[T; N]>() * cap / N == size_of::() * cap` // - `len / N <= cap / N` because `len <= cap` @@ -3341,10 +3512,10 @@ impl Vec { assert!(size_of::() == size_of::()); assert!(align_of::() == align_of::()); }; - let (ptr, length, capacity, alloc) = self.into_parts_with_alloc(); + let (ptr, length, capacity, alloc) = self.into_parts_with_allocator(); debug_assert_eq!(length, 0); // SAFETY: - // - `ptr` and `alloc` were just returned from `self.into_raw_parts_with_alloc()` + // - `ptr` and `alloc` were just returned from `self.into_raw_parts_with_allocator()` // - `T` & `U` have the same layout, so `capacity` does not need to be changed and we can safely use `alloc.dealloc` later // - the original vector was cleared, so there is no problem with "transmuting" the stored values unsafe { Vec::from_parts_in(ptr.cast::(), length, capacity, alloc) } @@ -3477,6 +3648,22 @@ impl Vec { } } +impl Vec { + #[cfg_attr( + not(no_global_oom_handling), + expect( + dead_code, + reason = "currently only used in IO module when global OOM handling is disabled" + ) + )] + pub(crate) fn try_extend_from_slice_of_bytes( + &mut self, + other: &[u8], + ) -> Result<(), TryReserveError> { + unsafe { self.try_append_elements(other) } + } +} + impl Vec<[T; N], A> { /// Takes a `Vec<[T; N]>` and flattens it into a `Vec`. /// @@ -3499,9 +3686,12 @@ impl Vec<[T; N], A> { /// ``` #[stable(feature = "slice_flatten", since = "1.80.0")] pub fn into_flattened(self) -> Vec { - let (ptr, len, cap, alloc) = self.into_raw_parts_with_alloc(); + let (ptr, len, cap, alloc) = self.into_raw_parts_with_allocator(); let (new_len, new_cap) = if T::IS_ZST { - (len.checked_mul(N).expect("vec len overflow"), usize::MAX) + ( + len.checked_mul(N).expect("the product of vec len and N shouldn't overflow"), + usize::MAX, + ) } else { // SAFETY: // - `cap * N` cannot overflow because the allocation is already in @@ -3656,7 +3846,8 @@ impl ExtendFromWithinSpec for Vec { //////////////////////////////////////////////////////////////////////////////// #[stable(feature = "rust1", since = "1.0.0")] -impl ops::Deref for Vec { +#[rustc_const_unstable(feature = "const_convert", issue = "143773")] +const impl ops::Deref for Vec { type Target = [T]; #[inline] @@ -3666,7 +3857,8 @@ impl ops::Deref for Vec { } #[stable(feature = "rust1", since = "1.0.0")] -impl ops::DerefMut for Vec { +#[rustc_const_unstable(feature = "const_convert", issue = "143773")] +const impl ops::DerefMut for Vec { #[inline] fn deref_mut(&mut self) -> &mut [T] { self.as_mut_slice() @@ -3679,9 +3871,14 @@ unsafe impl ops::DerefPure for Vec {} #[cfg(not(no_global_oom_handling))] #[stable(feature = "rust1", since = "1.0.0")] impl Clone for Vec { + /// Creates a new `Vec` by deep-copying the contents of an existing `Vec`. + /// + /// This method will allocate a new `Vec` and `clone` all of `self`'s contents + /// into it. The capacity of the duplicate `Vec` is not forced to match the + /// capacity of the original. fn clone(&self) -> Self { let alloc = self.allocator().clone(); - <[T]>::to_vec_in(&**self, alloc) + <[T]>::to_vec_in(self, alloc) } /// Overwrites the contents of `self` with a clone of the contents of `source`. @@ -3731,7 +3928,8 @@ impl Hash for Vec { } #[stable(feature = "rust1", since = "1.0.0")] -impl, A: Allocator> Index for Vec { +#[rustc_const_unstable(feature = "const_index", issue = "143775")] +const impl, A: Allocator> Index for Vec { type Output = I::Output; #[inline] @@ -3741,7 +3939,8 @@ impl, A: Allocator> Index for Vec { } #[stable(feature = "rust1", since = "1.0.0")] -impl, A: Allocator> IndexMut for Vec { +#[rustc_const_unstable(feature = "const_index", issue = "143775")] +const impl, A: Allocator> IndexMut for Vec { #[inline] fn index_mut(&mut self, index: I) -> &mut Self::Output { IndexMut::index_mut(&mut **self, index) @@ -4150,13 +4349,16 @@ impl Ord for Vec { } #[stable(feature = "rust1", since = "1.0.0")] -unsafe impl<#[may_dangle] T, A: Allocator> Drop for Vec { +#[rustc_const_unstable(feature = "const_heap", issue = "79597")] +const unsafe impl<#[may_dangle] T: [const] Destruct, A: [const] Allocator + [const] Destruct> Drop + for Vec +{ fn drop(&mut self) { unsafe { // use drop for [T] // use a raw slice to refer to the elements of the vector as weakest necessary type; // could avoid questions of validity in certain cases - ptr::drop_in_place(ptr::slice_from_raw_parts_mut(self.as_mut_ptr(), self.len)) + self.as_mut_ptr().cast_slice(self.len).drop_in_place() } // RawVec handles deallocation } @@ -4164,7 +4366,7 @@ unsafe impl<#[may_dangle] T, A: Allocator> Drop for Vec { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for Vec { +const impl Default for Vec { /// Creates an empty `Vec`. /// /// The vector will not allocate until elements are pushed onto it. @@ -4369,7 +4571,10 @@ impl From<&str> for Vec { } #[stable(feature = "array_try_from_vec", since = "1.48.0")] -impl TryFrom> for [T; N] { +#[rustc_const_unstable(feature = "const_convert", issue = "143773")] +const impl + TryFrom> for [T; N] +{ type Error = Vec; /// Gets the entire contents of the `Vec` as an array, diff --git a/library/alloc/src/vec/partial_eq.rs b/library/alloc/src/vec/partial_eq.rs index 5e620c4b2efe7..943c9309836d3 100644 --- a/library/alloc/src/vec/partial_eq.rs +++ b/library/alloc/src/vec/partial_eq.rs @@ -4,11 +4,11 @@ use crate::alloc::Allocator; use crate::borrow::Cow; macro_rules! __impl_slice_eq1 { - ([$($vars:tt)*] $lhs:ty, $rhs:ty $(where $ty:ty: $bound:ident)?, #[$stability:meta]) => { - #[$stability] - impl PartialEq<$rhs> for $lhs + ($($const:ident, )? [$($vars:tt)*] $lhs:ty, $rhs:ty $(where $ty:ty: $bound:ident)?, $(#[$stability:meta])+ ) => { + $(#[$stability])+ + $($const)? impl PartialEq<$rhs> for $lhs where - T: PartialEq, + T: $([$const])? PartialEq, $($ty: $bound)? { #[inline] @@ -19,21 +19,21 @@ macro_rules! __impl_slice_eq1 { } } -__impl_slice_eq1! { [A1: Allocator, A2: Allocator] Vec, Vec, #[stable(feature = "rust1", since = "1.0.0")] } -__impl_slice_eq1! { [A: Allocator] Vec, &[U], #[stable(feature = "rust1", since = "1.0.0")] } -__impl_slice_eq1! { [A: Allocator] Vec, &mut [U], #[stable(feature = "rust1", since = "1.0.0")] } -__impl_slice_eq1! { [A: Allocator] &[T], Vec, #[stable(feature = "partialeq_vec_for_ref_slice", since = "1.46.0")] } -__impl_slice_eq1! { [A: Allocator] &mut [T], Vec, #[stable(feature = "partialeq_vec_for_ref_slice", since = "1.46.0")] } -__impl_slice_eq1! { [A: Allocator] Vec, [U], #[stable(feature = "partialeq_vec_for_slice", since = "1.48.0")] } -__impl_slice_eq1! { [A: Allocator] [T], Vec, #[stable(feature = "partialeq_vec_for_slice", since = "1.48.0")] } +__impl_slice_eq1! { const, [A1: Allocator, A2: Allocator] Vec, Vec, #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] #[stable(feature = "rust1", since = "1.0.0")] } +__impl_slice_eq1! { const, [A: Allocator] Vec, &[U], #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] #[stable(feature = "rust1", since = "1.0.0")] } +__impl_slice_eq1! { const, [A: Allocator] Vec, &mut [U], #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] #[stable(feature = "rust1", since = "1.0.0")] } +__impl_slice_eq1! { const, [A: Allocator] &[T], Vec, #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] #[stable(feature = "partialeq_vec_for_ref_slice", since = "1.46.0")] } +__impl_slice_eq1! { const, [A: Allocator] &mut [T], Vec, #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] #[stable(feature = "partialeq_vec_for_ref_slice", since = "1.46.0")] } +__impl_slice_eq1! { const, [A: Allocator] Vec, [U], #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] #[stable(feature = "partialeq_vec_for_slice", since = "1.48.0")] } +__impl_slice_eq1! { const, [A: Allocator] [T], Vec, #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] #[stable(feature = "partialeq_vec_for_slice", since = "1.48.0")] } #[cfg(not(no_global_oom_handling))] __impl_slice_eq1! { [A: Allocator] Cow<'_, [T]>, Vec where T: Clone, #[stable(feature = "rust1", since = "1.0.0")] } #[cfg(not(no_global_oom_handling))] __impl_slice_eq1! { [] Cow<'_, [T]>, &[U] where T: Clone, #[stable(feature = "rust1", since = "1.0.0")] } #[cfg(not(no_global_oom_handling))] __impl_slice_eq1! { [] Cow<'_, [T]>, &mut [U] where T: Clone, #[stable(feature = "rust1", since = "1.0.0")] } -__impl_slice_eq1! { [A: Allocator, const N: usize] Vec, [U; N], #[stable(feature = "rust1", since = "1.0.0")] } -__impl_slice_eq1! { [A: Allocator, const N: usize] Vec, &[U; N], #[stable(feature = "rust1", since = "1.0.0")] } +__impl_slice_eq1! { const, [A: Allocator, const N: usize] Vec, [U; N], #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] #[stable(feature = "rust1", since = "1.0.0")] } +__impl_slice_eq1! { const, [A: Allocator, const N: usize] Vec, &[U; N], #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] #[stable(feature = "rust1", since = "1.0.0")] } // NOTE: some less important impls are omitted to reduce code bloat // FIXME(Centril): Reconsider this? diff --git a/library/alloc/src/vec/spec_extend.rs b/library/alloc/src/vec/spec_extend.rs index 7c908841c90ec..b3fee7d094e20 100644 --- a/library/alloc/src/vec/spec_extend.rs +++ b/library/alloc/src/vec/spec_extend.rs @@ -1,6 +1,6 @@ use core::clone::TrivialClone; use core::iter::TrustedLen; -use core::slice::{self}; +use core::slice; use super::{IntoIter, Vec}; use crate::alloc::Allocator; @@ -29,11 +29,11 @@ where } impl SpecExtend> for Vec { - fn spec_extend(&mut self, mut iterator: IntoIter) { + fn spec_extend(&mut self, iterator: IntoIter) { unsafe { self.append_elements(iterator.as_slice() as _); } - iterator.forget_remaining_elements(); + iterator.forget_remaining_elements_and_dealloc(); } } diff --git a/library/alloc/src/vec/spec_from_iter.rs b/library/alloc/src/vec/spec_from_iter.rs index e1f0b639bdfd6..ccbc2936fb4e8 100644 --- a/library/alloc/src/vec/spec_from_iter.rs +++ b/library/alloc/src/vec/spec_from_iter.rs @@ -1,5 +1,5 @@ use core::mem::ManuallyDrop; -use core::ptr::{self}; +use core::ptr; use super::{IntoIter, SpecExtend, SpecFromIterNested, Vec}; diff --git a/library/alloc/src/vec/splice.rs b/library/alloc/src/vec/splice.rs index 46611f611dc2c..6436afd1ba12f 100644 --- a/library/alloc/src/vec/splice.rs +++ b/library/alloc/src/vec/splice.rs @@ -1,5 +1,4 @@ -use core::ptr::{self}; -use core::slice::{self}; +use core::ptr; use super::{Drain, Vec}; use crate::alloc::{Allocator, Global}; @@ -60,7 +59,7 @@ impl Drop for Splice<'_, I, A> { // Which means we can replace the slice::Iter with pointers that won't point to deallocated // memory, so that Drain::drop is still allowed to call iter.len(), otherwise it would break // the ptr.offset_from_unsigned contract. - self.drain.iter = (&[]).iter(); + self.drain.iter = [].iter(); unsafe { if self.drain.tail_len == 0 { @@ -108,15 +107,13 @@ impl Drain<'_, T, A> { let vec = unsafe { self.vec.as_mut() }; let range_start = vec.len; let range_end = self.tail_start; - let range_slice = unsafe { - slice::from_raw_parts_mut(vec.as_mut_ptr().add(range_start), range_end - range_start) - }; + // The elements in this range are not initialized so we avoid creating a slice. - for place in range_slice { + for idx in range_start..range_end { let Some(new_item) = replace_with.next() else { return false; }; - unsafe { ptr::write(place, new_item) }; + unsafe { vec.as_mut_ptr().add(idx).write(new_item) }; vec.len += 1; } true diff --git a/library/alloc/src/wtf8/mod.rs b/library/alloc/src/wtf8/mod.rs index e4834a24bf430..36ec32c549763 100644 --- a/library/alloc/src/wtf8/mod.rs +++ b/library/alloc/src/wtf8/mod.rs @@ -284,7 +284,7 @@ impl Wtf8Buf { /// like concatenating ill-formed UTF-16 strings effectively would. #[inline] pub fn push_wtf8(&mut self, other: &Wtf8) { - match ((&*self).final_lead_surrogate(), other.initial_trail_surrogate()) { + match ((*self).final_lead_surrogate(), other.initial_trail_surrogate()) { // Replace newly paired surrogates by a supplementary code point. (Some(lead), Some(trail)) => { let len_without_lead_surrogate = self.len() - 3; @@ -322,7 +322,7 @@ impl Wtf8Buf { #[inline] pub fn push(&mut self, code_point: CodePoint) { if let Some(trail) = code_point.to_trail_surrogate() { - if let Some(lead) = (&*self).final_lead_surrogate() { + if let Some(lead) = (*self).final_lead_surrogate() { let len_without_lead_surrogate = self.len() - 3; self.bytes.truncate(len_without_lead_surrogate); self.push_char(decode_surrogate_pair(lead, trail)); @@ -342,14 +342,18 @@ impl Wtf8Buf { /// Shortens a string to the specified length. /// + /// If `new_len` is greater than the string's current length, this has no + /// effect. + /// /// # Panics /// - /// Panics if `new_len` > current length, - /// or if `new_len` is not a code point boundary. + /// Panics if `new_len` does not lie on a code point boundary. #[inline] pub fn truncate(&mut self, new_len: usize) { - assert!(self.is_code_point_boundary(new_len)); - self.bytes.truncate(new_len) + if new_len <= self.len() { + assert!(self.is_code_point_boundary(new_len)); + self.bytes.truncate(new_len) + } } /// Consumes the WTF-8 string and tries to convert it to a vec of bytes. diff --git a/library/alloc/src/wtf8/tests.rs b/library/alloc/src/wtf8/tests.rs index a72ad0837d11e..79e0bbdef50f6 100644 --- a/library/alloc/src/wtf8/tests.rs +++ b/library/alloc/src/wtf8/tests.rs @@ -308,10 +308,10 @@ fn wtf8buf_truncate_fail_code_point_boundary() { } #[test] -#[should_panic] -fn wtf8buf_truncate_fail_longer() { +fn wtf8buf_truncate_invalid_len() { let mut string = Wtf8Buf::from_str("aé"); string.truncate(4); + assert_eq!(string, Wtf8Buf::from_str("aé")); } #[test] diff --git a/library/alloctests/Cargo.toml b/library/alloctests/Cargo.toml index 3b522bf80a217..791b8ecbafce3 100644 --- a/library/alloctests/Cargo.toml +++ b/library/alloctests/Cargo.toml @@ -22,6 +22,10 @@ rand_xorshift = "0.4.0" name = "alloctests" path = "tests/lib.rs" +[[test]] +name = "c_str_alloc_error" +path = "tests/c_str_alloc_error.rs" + [[test]] name = "vec_deque_alloc_error" path = "tests/vec_deque_alloc_error.rs" diff --git a/library/std/src/io/impls/tests.rs b/library/alloctests/benches/io.rs similarity index 59% rename from library/std/src/io/impls/tests.rs rename to library/alloctests/benches/io.rs index d1cd84a67ada5..f2e3f2cd3c998 100644 --- a/library/std/src/io/impls/tests.rs +++ b/library/alloctests/benches/io.rs @@ -1,4 +1,4 @@ -use crate::io::prelude::*; +use std::io::prelude::*; #[bench] fn bench_read_slice(b: &mut test::Bencher) { @@ -55,3 +55,26 @@ fn bench_write_vec(b: &mut test::Bencher) { } }) } + +#[bench] +#[cfg(unix)] +#[cfg_attr(target_os = "emscripten", ignore)] // no /dev +fn bench_copy_buf_reader(b: &mut test::Bencher) { + use std::fs::{File, OpenOptions}; + + let mut file_in = File::open("/dev/zero").expect("opening /dev/zero failed"); + // use dyn to avoid specializations unrelated to readbuf + let dyn_in = &mut file_in as &mut dyn Read; + let mut reader = std::io::BufReader::with_capacity(256 * 1024, dyn_in.take(0)); + let mut writer = + OpenOptions::new().write(true).open("/dev/null").expect("opening /dev/null failed"); + + const BYTES: u64 = 1024 * 1024; + + b.bytes = BYTES; + + b.iter(|| { + reader.get_mut().set_limit(BYTES); + std::io::copy(&mut reader, &mut writer).unwrap() + }); +} diff --git a/library/alloctests/benches/lib.rs b/library/alloctests/benches/lib.rs index 721d685527fec..974b389a765d5 100644 --- a/library/alloctests/benches/lib.rs +++ b/library/alloctests/benches/lib.rs @@ -1,16 +1,18 @@ -// Disabling in Miri as these would take too long. +// This is marked as `test = true` and hence picked up by `./x miri`, but that would be too slow. #![cfg(not(miri))] +#![allow(internal_features)] #![feature(iter_next_chunk)] #![feature(repr_simd)] #![feature(slice_partition_dedup)] #![feature(strict_provenance_lints)] #![feature(test)] -#![deny(fuzzy_provenance_casts)] +#![deny(implicit_provenance_casts)] extern crate test; mod binary_heap; mod btree; +mod io; mod linked_list; mod slice; mod str; diff --git a/library/alloctests/benches/vec_deque_append.rs b/library/alloctests/benches/vec_deque_append.rs index 7c805da973763..180981abc06f6 100644 --- a/library/alloctests/benches/vec_deque_append.rs +++ b/library/alloctests/benches/vec_deque_append.rs @@ -6,11 +6,6 @@ const WARMUP_N: usize = 100; const BENCH_N: usize = 1000; fn main() { - if cfg!(miri) { - // Don't benchmark Miri... - // (Due to bootstrap quirks, this gets picked up by `x.py miri library/alloc --no-doc`.) - return; - } let a: VecDeque = (0..VECDEQUE_LEN).collect(); let b: VecDeque = (0..VECDEQUE_LEN).collect(); diff --git a/library/alloctests/lib.rs b/library/alloctests/lib.rs index fe14480102e32..83b017b7625b9 100644 --- a/library/alloctests/lib.rs +++ b/library/alloctests/lib.rs @@ -16,15 +16,15 @@ // tidy-alphabetical-start #![feature(allocator_api)] #![feature(array_into_iter_constructors)] -#![feature(assert_matches)] -#![feature(box_vec_non_null)] #![feature(char_internals)] #![feature(const_alloc_error)] #![feature(const_cmp)] #![feature(const_convert)] +#![feature(const_default)] #![feature(const_destruct)] #![feature(const_heap)] #![feature(const_option_ops)] +#![feature(const_result_trait_fn)] #![feature(const_try)] #![feature(copied_into_inner)] #![feature(core_intrinsics)] @@ -37,6 +37,7 @@ #![feature(iter_next_chunk)] #![feature(maybe_uninit_uninit_array_transpose)] #![feature(ptr_alignment_type)] +#![feature(ptr_cast_slice)] #![feature(ptr_internals)] #![feature(rev_into_inner)] #![feature(sized_type_properties)] @@ -51,21 +52,19 @@ #![feature(trusted_random_access)] #![feature(try_reserve_kind)] #![feature(try_trait_v2)] +#![feature(unwrap_infallible)] #![feature(wtf8_internals)] // tidy-alphabetical-end // // Language features: // tidy-alphabetical-start -#![feature(cfg_sanitize)] +#![feature(const_closures)] #![feature(const_trait_impl)] #![feature(dropck_eyepatch)] -#![feature(lang_items)] #![feature(min_specialization)] -#![feature(negative_impls)] #![feature(never_type)] #![feature(optimize_attribute)] #![feature(prelude_import)] -#![feature(rustc_allow_const_fn_unstable)] #![feature(rustc_attrs)] #![feature(staged_api)] #![feature(test)] diff --git a/library/alloctests/tests/arc.rs b/library/alloctests/tests/arc.rs index 00bdf527133f7..4299fea4120d8 100644 --- a/library/alloctests/tests/arc.rs +++ b/library/alloctests/tests/arc.rs @@ -86,6 +86,34 @@ fn eq() { assert_eq!(*x.0.borrow(), 0); } +#[test] +fn eq_unsized() { + #[derive(Eq)] + struct TestEq(RefCell, T); + impl PartialEq for TestEq { + fn eq(&self, other: &TestEq) -> bool { + *self.0.borrow_mut() += 1; + *other.0.borrow_mut() += 1; + true + } + } + let x = Arc::>::new(TestEq(RefCell::new(0), [0, 1, 2])) as Arc>; + assert!(x == x); + assert!(!(x != x)); + assert_eq!(*x.0.borrow(), 0); +} + +#[test] +fn eq_unsized_slice() { + let a: Arc<[()]> = Arc::new([(); 3]); + let ptr: *const () = Arc::into_raw(a.clone()).cast(); + let b: Arc<[()]> = unsafe { Arc::from_raw(ptr.cast_slice(42)) }; + assert!(a == a); + assert!(!(a != a)); + assert!(a != b); + assert!(!(a == b)); +} + // The test code below is identical to that in `rc.rs`. // For better maintainability we therefore define this type alias. type Rc = Arc; @@ -300,3 +328,26 @@ mod pin_coerce_unsized { arg } } + +/// Test that `Arc::make_mut` does not forget an allocator when it steals the data. +#[test] +fn issue_158875_make_mut_dont_leak_allocator() { + use std::alloc::Global; + + let alloc = Rc::new(Global); + + { + let mut arc = Arc::new_in(123, alloc.clone()); + let weak = Arc::downgrade(&arc); // create a weak so make_mut steals the data + _ = Arc::make_mut(&mut arc); + assert_eq!(weak.upgrade(), None); + } + + assert_eq!(Rc::strong_count(&alloc), 1); // if this is >1, we have a memory leak! +} + +#[test] +#[should_panic = "capacity overflow"] +fn new_uninit_slice_capacity_overflow() { + let _ = Arc::<[u8]>::new_uninit_slice(isize::MAX as usize); +} diff --git a/library/alloctests/tests/boxed.rs b/library/alloctests/tests/boxed.rs index 83fd1ef7449a3..74db1c7de31e7 100644 --- a/library/alloctests/tests/boxed.rs +++ b/library/alloctests/tests/boxed.rs @@ -47,9 +47,9 @@ fn box_clone_from_ptr_stability() { for size in (0..8).map(|i| 2usize.pow(i)) { let control = vec![Dummy { _data: 42 }; size].into_boxed_slice(); let mut copy = vec![Dummy { _data: 84 }; size].into_boxed_slice(); - let copy_raw = copy.as_ptr() as usize; + let copy_raw = copy.as_ptr(); copy.clone_from(&control); - assert_eq!(copy.as_ptr() as usize, copy_raw); + assert_eq!(copy.as_ptr(), copy_raw); } } @@ -104,7 +104,7 @@ pub struct ConstAllocator; unsafe impl Allocator for ConstAllocator { fn allocate(&self, layout: Layout) -> Result, AllocError> { match layout.size() { - 0 => Ok(NonNull::slice_from_raw_parts(layout.dangling_ptr(), 0)), + 0 => Ok(layout.dangling_ptr().cast_slice(0)), _ => unsafe { let ptr = core::intrinsics::const_allocate(layout.size(), layout.align()); Ok(NonNull::new_unchecked(ptr as *mut [u8; 0] as *mut [u8])) @@ -211,13 +211,6 @@ unsafe impl Allocator for ConstAllocator { } Ok(new_ptr) } - - fn by_ref(&self) -> &Self - where - Self: Sized, - { - self - } } #[allow(unused)] diff --git a/library/alloctests/tests/bstr.rs b/library/alloctests/tests/bstr.rs new file mode 100644 index 0000000000000..64a1b901f1300 --- /dev/null +++ b/library/alloctests/tests/bstr.rs @@ -0,0 +1,84 @@ +use alloc::bstr::ByteString; +use core::assert_matches; + +#[test] +fn test_debug() { + let b1 = ByteString( + b"\0\x01\x02\x03\x04\x05\x06\x07\x08\t\n\x11\x12\r\x14\x15\x16\x17\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f \x7f\x80\x81\xfe\xff".to_vec() + ); + assert_eq!( + r#""\0\x01\x02\x03\x04\x05\x06\x07\x08\t\n\x11\x12\r\x14\x15\x16\x17\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f \x7f\x80\x81\xfe\xff""#, + format!("{:?}", b1), + ); +} + +#[test] +fn test_display() { + let b1 = ByteString(b"abc".to_vec()); + let b2 = ByteString(b"\xf0\x28\x8c\xbc".to_vec()); + + assert_eq!(&format!("{b1}"), "abc"); + assert_eq!(&format!("{b2}"), "�(��"); + + assert_eq!(&format!("{b1:<7}!"), "abc !"); + assert_eq!(&format!("{b1:>7}!"), " abc!"); + assert_eq!(&format!("{b1:^7}!"), " abc !"); + assert_eq!(&format!("{b1:^6}!"), " abc !"); + assert_eq!(&format!("{b1:-<7}!"), "abc----!"); + assert_eq!(&format!("{b1:->7}!"), "----abc!"); + assert_eq!(&format!("{b1:-^7}!"), "--abc--!"); + assert_eq!(&format!("{b1:-^6}!"), "-abc--!"); + + assert_eq!(&format!("{b2:<7}!"), "�(�� !"); + assert_eq!(&format!("{b2:>7}!"), " �(��!"); + assert_eq!(&format!("{b2:^7}!"), " �(�� !"); + assert_eq!(&format!("{b2:^6}!"), " �(�� !"); + assert_eq!(&format!("{b2:-<7}!"), "�(��---!"); + assert_eq!(&format!("{b2:->7}!"), "---�(��!"); + assert_eq!(&format!("{b2:-^7}!"), "-�(��--!"); + assert_eq!(&format!("{b2:-^6}!"), "-�(��-!"); + + assert_eq!(&format!("{b1:<2}!"), "abc!"); + assert_eq!(&format!("{b1:>2}!"), "abc!"); + assert_eq!(&format!("{b1:^2}!"), "abc!"); + assert_eq!(&format!("{b1:-<2}!"), "abc!"); + assert_eq!(&format!("{b1:->2}!"), "abc!"); + assert_eq!(&format!("{b1:-^2}!"), "abc!"); + + assert_eq!(&format!("{b2:<3}!"), "�(��!"); + assert_eq!(&format!("{b2:>3}!"), "�(��!"); + assert_eq!(&format!("{b2:^3}!"), "�(��!"); + assert_eq!(&format!("{b2:^2}!"), "�(��!"); + assert_eq!(&format!("{b2:-<3}!"), "�(��!"); + assert_eq!(&format!("{b2:->3}!"), "�(��!"); + assert_eq!(&format!("{b2:-^3}!"), "�(��!"); + assert_eq!(&format!("{b2:-^2}!"), "�(��!"); + + assert_eq!(&format!("{b1:.1}!"), &format!("{:.1}!", "abc")); + assert_eq!(&format!("{b1:.2}!"), &format!("{:.2}!", "abc")); + assert_eq!(&format!("{b1:.3}!"), &format!("{:.3}!", "abc")); + assert_eq!(&format!("{b1:-<5.2}!"), &format!("{:-<5.2}!", "abc")); + assert_eq!(&format!("{b1:-^5.2}!"), &format!("{:-^5.2}!", "abc")); + assert_eq!(&format!("{b1:->5.2}!"), &format!("{:->5.2}!", "abc")); + + assert_eq!(&format!("{b2:.1}!"), "�!"); + assert_eq!(&format!("{b2:.2}!"), "�(!"); + assert_eq!(&format!("{b2:.3}!"), "�(�!"); + assert_eq!(&format!("{b2:.4}!"), "�(��!"); + assert_eq!(&format!("{b2:-<6.3}!"), "�(�---!"); + assert_eq!(&format!("{b2:-^6.3}!"), "-�(�--!"); + assert_eq!(&format!("{b2:->6.3}!"), "---�(�!"); +} + +#[test] +fn test_to_string() { + let b1 = ByteString(b"abc".to_vec()); + let b2 = ByteString(b"\xf0\x28\x8c\xbc".to_vec()); + + assert_eq!(Ok("abc".to_string()), b1.to_string()); + assert_matches!(b2.to_string(), Err(core::str::Utf8Error { .. })); + + // Can still directly use the trait + assert_eq!("abc".to_string(), ToString::to_string(&b1)); + assert_eq!("�(��".to_string(), ToString::to_string(&b2)); +} diff --git a/library/alloctests/tests/c_str_alloc_error.rs b/library/alloctests/tests/c_str_alloc_error.rs new file mode 100644 index 0000000000000..669a783645baa --- /dev/null +++ b/library/alloctests/tests/c_str_alloc_error.rs @@ -0,0 +1,72 @@ +//! Regression test for the panic-safety fix in rust-lang/rust#155707. +//! +//! rust-lang/rust#70201 gave `::clone_into` a path that moved the +//! target `CString`'s buffer out before growing a `Vec`; if that growth's allocation +//! failed and unwound, the target was left without its nul terminator. This only +//! reproduces under Miri: in a normal build the `#[global_allocator]` below can't +//! intercept the reallocation inside `CString::clone_into` (it lives in libstd, which +//! library tests link with `-C prefer-dynamic`), so as a regular test it just checks +//! the happy path. + +// Disabled under Miri on Windows: a `#[global_allocator]` wrapping `System` trips +// Stacked Borrows there, and it affects libtest's own allocations, not just this test +// (so `#[ignore]` would not be enough). See . +#![cfg(not(all(miri, windows)))] +#![feature(alloc_error_hook)] + +use std::alloc::{GlobalAlloc, Layout, System, set_alloc_error_hook}; +use std::ffi::CString; +use std::panic::{AssertUnwindSafe, catch_unwind}; +use std::sync::atomic::{AtomicBool, Ordering}; + +// Once armed, the first allocation of 8 bytes or more fails and disarms, so the +// reallocation inside `clone_into`'s grow path fails while the runtime's own +// smaller allocations keep succeeding. +struct OneShotFailingAlloc; + +static ARMED: AtomicBool = AtomicBool::new(false); + +unsafe impl GlobalAlloc for OneShotFailingAlloc { + unsafe fn alloc(&self, layout: Layout) -> *mut u8 { + if layout.size() >= 8 && ARMED.swap(false, Ordering::SeqCst) { + return core::ptr::null_mut(); + } + unsafe { System.alloc(layout) } + } + + unsafe fn dealloc(&self, ptr: *mut u8, layout: Layout) { + unsafe { System.dealloc(ptr, layout) } + } + + unsafe fn realloc(&self, ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { + if new_size >= 8 && ARMED.swap(false, Ordering::SeqCst) { + return core::ptr::null_mut(); + } + unsafe { System.realloc(ptr, layout, new_size) } + } +} + +#[global_allocator] +static ALLOC: OneShotFailingAlloc = OneShotFailingAlloc; + +#[test] +#[cfg_attr(not(panic = "unwind"), ignore = "test requires unwinding support")] +fn clone_into_alloc_failure_leaves_target_valid() { + set_alloc_error_hook(|_| panic!("alloc error")); + + let src = CString::new("a fairly long value").unwrap(); + let mut target = CString::new("x").unwrap(); + + ARMED.store(true, Ordering::SeqCst); + // Under Miri the failing allocator is honored, so this reallocation unwinds; in a + // normal build the allocator can't intercept it and `clone_into` just succeeds. + let res = catch_unwind(AssertUnwindSafe(|| src.as_c_str().clone_into(&mut target))); + ARMED.store(false, Ordering::SeqCst); + + if cfg!(miri) { + assert!(res.is_err(), "clone_into should have unwound on the alloc failure"); + } + // Either way `target` must still end in its nul terminator. Before the fix the Miri + // unwind left it empty (also caught as a bad write in `CString`'s destructor). + assert_eq!(target.as_bytes_with_nul().last(), Some(&0)); +} diff --git a/library/alloctests/tests/heap.rs b/library/alloctests/tests/heap.rs index 246b341eeb387..8eb562622c0a4 100644 --- a/library/alloctests/tests/heap.rs +++ b/library/alloctests/tests/heap.rs @@ -25,7 +25,7 @@ fn check_overalign_requests(allocator: T) { .collect(); for &ptr in &pointers { assert_eq!( - (ptr.as_non_null_ptr().as_ptr() as usize) % align, + ptr.as_non_null_ptr().as_ptr().addr() % align, 0, "Got a pointer less aligned than requested" ) diff --git a/library/std/src/io/buffered/tests.rs b/library/alloctests/tests/io/buffered.rs similarity index 84% rename from library/std/src/io/buffered/tests.rs rename to library/alloctests/tests/io/buffered.rs index 6ad4158b92904..0abaa63870e15 100644 --- a/library/std/src/io/buffered/tests.rs +++ b/library/alloctests/tests/io/buffered.rs @@ -1,10 +1,14 @@ -use crate::io::prelude::*; -use crate::io::{ - self, BorrowedBuf, BufReader, BufWriter, ErrorKind, IoSlice, LineWriter, SeekFrom, +//! Tests for buffering wrappers for I/O traits + +use alloc::io::{ + self, BorrowedBuf, BufRead, BufReader, BufWriter, ErrorKind, IoSlice, LineWriter, Read, Seek, + SeekFrom, Write, }; -use crate::mem::MaybeUninit; -use crate::sync::atomic::{AtomicUsize, Ordering}; -use crate::{panic, thread}; +use core::mem::MaybeUninit; +use core::sync::atomic::{AtomicUsize, Ordering}; +use std::{panic, thread}; + +extern crate test; /// A dummy reader intended at testing short-reads propagation. pub struct ShortReader { @@ -63,7 +67,7 @@ fn test_buffered_reader_read_buf() { let mut reader = BufReader::with_capacity(2, inner); let buf: &mut [_] = &mut [MaybeUninit::uninit(); 3]; - let mut buf: BorrowedBuf<'_> = buf.into(); + let mut buf: BorrowedBuf<'_, u8> = buf.into(); reader.read_buf(buf.unfilled()).unwrap(); @@ -71,7 +75,7 @@ fn test_buffered_reader_read_buf() { assert_eq!(reader.buffer(), []); let buf: &mut [_] = &mut [MaybeUninit::uninit(); 2]; - let mut buf: BorrowedBuf<'_> = buf.into(); + let mut buf: BorrowedBuf<'_, u8> = buf.into(); reader.read_buf(buf.unfilled()).unwrap(); @@ -79,7 +83,7 @@ fn test_buffered_reader_read_buf() { assert_eq!(reader.buffer(), []); let buf: &mut [_] = &mut [MaybeUninit::uninit(); 1]; - let mut buf: BorrowedBuf<'_> = buf.into(); + let mut buf: BorrowedBuf<'_, u8> = buf.into(); reader.read_buf(buf.unfilled()).unwrap(); @@ -87,7 +91,7 @@ fn test_buffered_reader_read_buf() { assert_eq!(reader.buffer(), [3]); let buf: &mut [_] = &mut [MaybeUninit::uninit(); 3]; - let mut buf: BorrowedBuf<'_> = buf.into(); + let mut buf: BorrowedBuf<'_, u8> = buf.into(); reader.read_buf(buf.unfilled()).unwrap(); @@ -391,16 +395,16 @@ fn test_read_until() { let mut v = Vec::new(); reader.read_until(0, &mut v).unwrap(); assert_eq!(v, [0]); - v.truncate(0); + v.clear(); reader.read_until(2, &mut v).unwrap(); assert_eq!(v, [1, 2]); - v.truncate(0); + v.clear(); reader.read_until(1, &mut v).unwrap(); assert_eq!(v, [1]); - v.truncate(0); + v.clear(); reader.read_until(8, &mut v).unwrap(); assert_eq!(v, [0]); - v.truncate(0); + v.clear(); reader.read_until(9, &mut v).unwrap(); assert_eq!(v, []); } @@ -429,13 +433,13 @@ fn test_read_line() { let mut s = String::new(); reader.read_line(&mut s).unwrap(); assert_eq!(s, "a\n"); - s.truncate(0); + s.clear(); reader.read_line(&mut s).unwrap(); assert_eq!(s, "b\n"); - s.truncate(0); + s.clear(); reader.read_line(&mut s).unwrap(); assert_eq!(s, "c"); - s.truncate(0); + s.clear(); reader.read_line(&mut s).unwrap(); assert_eq!(s, ""); } @@ -488,7 +492,7 @@ fn dont_panic_in_drop_on_panicked_flush() { } #[test] -#[cfg_attr(any(target_os = "emscripten", target_os = "wasi"), ignore)] // no threads +#[cfg_attr(not(panic = "unwind"), ignore = "test requires unwinding support")] fn panic_in_write_doesnt_flush_in_drop() { static WRITES: AtomicUsize = AtomicUsize::new(0); @@ -504,12 +508,11 @@ fn panic_in_write_doesnt_flush_in_drop() { } } - thread::spawn(|| { + panic::catch_unwind(panic::AssertUnwindSafe(|| { let mut writer = BufWriter::new(PanicWriter); let _ = writer.write(b"hello world"); let _ = writer.flush(); - }) - .join() + })) .unwrap_err(); assert_eq!(WRITES.load(Ordering::SeqCst), 1); @@ -681,7 +684,7 @@ fn line_vectored() { #[test] fn line_vectored_partial_and_errors() { - use crate::collections::VecDeque; + use alloc::collections::VecDeque; enum Call { Write { inputs: Vec<&'static [u8]>, output: io::Result }, @@ -752,6 +755,133 @@ fn line_vectored_partial_and_errors() { } } +/// Regression test for the quadratic scan in `LineWriterShim::write_vectored`. +/// +/// When given a long list of newline-free buffers and a sink that only +/// retires a few slices per call, the previous implementation rescanned all +/// remaining buffers on every iteration of `write_all_vectored`, producing +/// O(N^2) work. The fix caps the scan to a constant prefix; this test +/// verifies that bytes still come out in order when the only newline lives +/// past that cap. +#[test] +fn line_vectored_long_input_past_scan_cap() { + /// Vectored sink that retires at most one non-empty slice per call, + /// mimicking a writev() bounded by IOV_MAX. + #[derive(Default)] + struct OneSliceSink { + buffer: Vec, + } + + impl Write for OneSliceSink { + fn write(&mut self, buf: &[u8]) -> io::Result { + self.buffer.extend_from_slice(buf); + Ok(buf.len()) + } + fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { + for b in bufs { + if !b.is_empty() { + self.buffer.extend_from_slice(b); + return Ok(b.len()); + } + } + Ok(0) + } + fn flush(&mut self) -> io::Result<()> { + Ok(()) + } + fn is_write_vectored(&self) -> bool { + true + } + } + + // Place the only newline well past the 1024-slice scan cap. + const N: usize = 1500; + const NEWLINE_AT: usize = 1400; + let bytes: Vec = (0..N).map(|i| if i == NEWLINE_AT { b'\n' } else { b'a' }).collect(); + let mut io_slices: Vec> = bytes.chunks(1).map(IoSlice::new).collect(); + + let mut writer = LineWriter::new(OneSliceSink::default()); + writer.write_all_vectored(&mut io_slices).unwrap(); + + // The newline past the scan cap must still trigger a flush through + // the inner writer; only the tail after the newline may remain buffered. + assert_eq!(writer.get_ref().buffer, bytes[..=NEWLINE_AT]); + + writer.flush().unwrap(); + assert_eq!(writer.get_ref().buffer, bytes); +} + +/// Regression test for newlines buried past the `write_vectored` scan cap. +/// +/// `LineWriterShim::write_vectored` only scans a bounded prefix of the slice +/// list for newlines. An earlier version computed the head/tail split against +/// the *full* list, so when more than the cap's worth of slices were passed in +/// a single call and one of the unscanned slices held a newline, that newline +/// was silently copied into the inner `BufWriter` instead of being flushed -- +/// leaving a completed line stuck in the buffer. +/// +/// The invariant this checks is the core line-buffering guarantee: once all +/// input has been written, everything up to and including the *last* newline +/// must have reached the inner writer, and only the trailing partial line may +/// remain buffered. It holds regardless of the exact scan-cap value, and it is +/// driven through the public `write_all_vectored` entry point so the cap +/// boundary is crossed naturally. +#[test] +fn line_vectored_flushes_newline_past_scan_cap() { + /// Vectored sink that accepts every slice in full, so any data that fails + /// to reach it must have been (incorrectly) left in the LineWriter buffer. + #[derive(Default)] + struct FullSink { + buffer: Vec, + } + + impl Write for FullSink { + fn write(&mut self, buf: &[u8]) -> io::Result { + self.buffer.extend_from_slice(buf); + Ok(buf.len()) + } + fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { + let mut written = 0; + for b in bufs { + self.buffer.extend_from_slice(b); + written += b.len(); + } + Ok(written) + } + fn flush(&mut self) -> io::Result<()> { + Ok(()) + } + fn is_write_vectored(&self) -> bool { + true + } + } + + // Two newlines: one comfortably inside the scan cap and one well past it, + // so a single `write_vectored` call sees the first but not the second. + const N: usize = 1100; + const FIRST_NEWLINE: usize = 5; + const LAST_NEWLINE: usize = 1050; + let bytes: Vec = (0..N) + .map(|i| if i == FIRST_NEWLINE || i == LAST_NEWLINE { b'\n' } else { b'a' }) + .collect(); + let mut io_slices: Vec> = bytes.chunks(1).map(IoSlice::new).collect(); + + // The buffer has to be large enough to hold the whole tail past the first + // newline; otherwise it fills up before the buggy split would even reach + // the second newline, masking the bug. + let mut writer = LineWriter::with_capacity(4096, FullSink::default()); + writer.write_all_vectored(&mut io_slices).unwrap(); + + // Everything up to and including the last newline must have been flushed; + // only the trailing partial line is allowed to remain buffered. The buggy + // version left the last newline buried in the buffer, so the sink only saw + // up to the first newline. + assert_eq!(writer.get_ref().buffer, bytes[..=LAST_NEWLINE]); + + writer.flush().unwrap(); + assert_eq!(writer.get_ref().buffer, bytes); +} + /// Test that, in cases where vectored writing is not enabled, the /// LineWriter uses the normal `write` call, which more-correctly handles /// partial lines @@ -1023,7 +1153,7 @@ struct WriteRecorder { impl Write for WriteRecorder { fn write(&mut self, buf: &[u8]) -> io::Result { - use crate::str::from_utf8; + use core::str::from_utf8; self.events.push(RecordedEvent::Write(from_utf8(buf).unwrap().to_string())); Ok(buf.len()) @@ -1056,7 +1186,7 @@ fn single_formatted_write() { fn bufreader_full_initialize() { struct OneByteReader; impl Read for OneByteReader { - fn read(&mut self, buf: &mut [u8]) -> crate::io::Result { + fn read(&mut self, buf: &mut [u8]) -> alloc::io::Result { if buf.len() > 0 { buf[0] = 0; Ok(1) @@ -1067,19 +1197,19 @@ fn bufreader_full_initialize() { } let mut reader = BufReader::new(OneByteReader); // Nothing is initialized yet. - assert_eq!(reader.initialized(), 0); + assert!(!reader.initialized()); let buf = reader.fill_buf().unwrap(); // We read one byte... assert_eq!(buf.len(), 1); // But we initialized the whole buffer! - assert_eq!(reader.initialized(), reader.capacity()); + assert!(reader.initialized()); } /// This is a regression test for https://github.com/rust-lang/rust/issues/127584. #[test] fn bufwriter_aliasing() { - use crate::io::{BufWriter, Cursor}; + use alloc::io::{BufWriter, Cursor}; let mut v = vec![0; 1024]; let c = Cursor::new(&mut v); let w = BufWriter::new(Box::new(c)); diff --git a/library/std/src/io/copy/tests.rs b/library/alloctests/tests/io/copy.rs similarity index 68% rename from library/std/src/io/copy/tests.rs rename to library/alloctests/tests/io/copy.rs index 25b1ece2745b9..485deeaea80e7 100644 --- a/library/std/src/io/copy/tests.rs +++ b/library/alloctests/tests/io/copy.rs @@ -1,7 +1,6 @@ -use crate::cmp::{max, min}; -use crate::collections::VecDeque; -use crate::io; -use crate::io::*; +use alloc::collections::VecDeque; +use alloc::io::{self, *}; +use core::cmp::{max, min}; #[test] fn copy_copies() { @@ -65,7 +64,7 @@ fn copy_specializes_bufreader() { let mut buffered = BufReader::with_capacity(256 * 1024, Cursor::new(&mut source)); let mut sink = Vec::new(); - assert_eq!(crate::io::copy(&mut buffered, &mut sink).unwrap(), source.len() as u64); + assert_eq!(io::copy(&mut buffered, &mut sink).unwrap(), source.len() as u64); assert_eq!(source.as_slice(), sink.as_slice()); let buf_sz = 71 * 1024; @@ -73,7 +72,7 @@ fn copy_specializes_bufreader() { let mut buffered = BufReader::with_capacity(buf_sz, Cursor::new(&mut source)); let mut sink = WriteObserver { observed_buffer: 0 }; - assert_eq!(crate::io::copy(&mut buffered, &mut sink).unwrap(), source.len() as u64); + assert_eq!(io::copy(&mut buffered, &mut sink).unwrap(), source.len() as u64); assert_eq!( sink.observed_buffer, buf_sz, "expected a large buffer to be provided to the writer" @@ -97,16 +96,17 @@ fn copy_specializes_to_vec() { #[test] fn copy_specializes_from_vecdeque() { - let mut source = VecDeque::with_capacity(100 * 1024); - for _ in 0..20 * 1024 { + let num: usize = if cfg!(miri) { 512 } else { 20 * 1024 }; + let mut source = VecDeque::with_capacity(4 * num); + for _ in 0..num { source.push_front(0); } - for _ in 0..20 * 1024 { + for _ in 0..num { source.push_back(0); } let mut sink = WriteObserver { observed_buffer: 0 }; - assert_eq!(40 * 1024u64, io::copy(&mut source, &mut sink).unwrap()); - assert_eq!(20 * 1024, sink.observed_buffer); + assert_eq!(2 * num as u64, io::copy(&mut source, &mut sink).unwrap()); + assert_eq!(num, sink.observed_buffer); } #[test] @@ -116,32 +116,3 @@ fn copy_specializes_from_slice() { assert_eq!(60 * 1024u64, io::copy(&mut source, &mut sink).unwrap()); assert_eq!(60 * 1024, sink.observed_buffer); } - -#[cfg(unix)] -mod io_benches { - use test::Bencher; - - use crate::fs::{File, OpenOptions}; - use crate::io::BufReader; - use crate::io::prelude::*; - - #[bench] - #[cfg_attr(target_os = "emscripten", ignore)] // no /dev - fn bench_copy_buf_reader(b: &mut Bencher) { - let mut file_in = File::open("/dev/zero").expect("opening /dev/zero failed"); - // use dyn to avoid specializations unrelated to readbuf - let dyn_in = &mut file_in as &mut dyn Read; - let mut reader = BufReader::with_capacity(256 * 1024, dyn_in.take(0)); - let mut writer = - OpenOptions::new().write(true).open("/dev/null").expect("opening /dev/null failed"); - - const BYTES: u64 = 1024 * 1024; - - b.bytes = BYTES; - - b.iter(|| { - reader.get_mut().set_limit(BYTES); - crate::io::copy(&mut reader, &mut writer).unwrap() - }); - } -} diff --git a/library/std/src/io/cursor/tests.rs b/library/alloctests/tests/io/cursor.rs similarity index 99% rename from library/std/src/io/cursor/tests.rs rename to library/alloctests/tests/io/cursor.rs index d7c203c297fe6..5e863f29af53c 100644 --- a/library/std/src/io/cursor/tests.rs +++ b/library/alloctests/tests/io/cursor.rs @@ -1,5 +1,6 @@ -use crate::io::prelude::*; -use crate::io::{Cursor, IoSlice, IoSliceMut, SeekFrom}; +use alloc::io::{Cursor, IoSlice, IoSliceMut, Read, Seek, SeekFrom, Write}; + +extern crate test; #[test] fn test_vec_writer() { diff --git a/library/std/src/io/tests.rs b/library/alloctests/tests/io/mod.rs similarity index 88% rename from library/std/src/io/tests.rs rename to library/alloctests/tests/io/mod.rs index b22988d4a8a9d..712e322d79f1c 100644 --- a/library/std/src/io/tests.rs +++ b/library/alloctests/tests/io/mod.rs @@ -1,10 +1,16 @@ -use super::{BorrowedBuf, Cursor, SeekFrom, repeat}; -use crate::cmp::{self, min}; -use crate::io::{ - self, BufRead, BufReader, DEFAULT_BUF_SIZE, IoSlice, IoSliceMut, Read, Seek, Write, +mod buffered; +mod copy; +mod cursor; +mod util; + +use alloc::io::{ + self, BorrowedBuf, BufRead, BufReader, Cursor, DEFAULT_BUF_SIZE, IoSlice, Read, Seek, SeekFrom, + Write, repeat, }; -use crate::mem::MaybeUninit; -use crate::ops::Deref; +use core::cmp::{self, min}; +use core::mem::MaybeUninit; + +extern crate test; #[test] fn read_until() { @@ -17,10 +23,10 @@ fn read_until() { let mut v = Vec::new(); assert_eq!(buf.read_until(b'3', &mut v).unwrap(), 3); assert_eq!(v, b"123"); - v.truncate(0); + v.clear(); assert_eq!(buf.read_until(b'3', &mut v).unwrap(), 1); assert_eq!(v, b"3"); - v.truncate(0); + v.clear(); assert_eq!(buf.read_until(b'3', &mut v).unwrap(), 0); assert_eq!(v, []); } @@ -80,10 +86,10 @@ fn read_line() { let mut v = String::new(); assert_eq!(buf.read_line(&mut v).unwrap(), 3); assert_eq!(v, "12\n"); - v.truncate(0); + v.clear(); assert_eq!(buf.read_line(&mut v).unwrap(), 1); assert_eq!(v, "\n"); - v.truncate(0); + v.clear(); assert_eq!(buf.read_line(&mut v).unwrap(), 0); assert_eq!(v, ""); } @@ -190,7 +196,7 @@ fn read_exact_slice() { #[test] fn read_buf_exact() { let buf: &mut [_] = &mut [0; 4]; - let mut buf: BorrowedBuf<'_> = buf.into(); + let mut buf: BorrowedBuf<'_, u8> = buf.into(); let mut c = Cursor::new(&b""[..]); assert_eq!(c.read_buf_exact(buf.unfilled()).unwrap_err().kind(), io::ErrorKind::UnexpectedEof); @@ -214,8 +220,8 @@ fn read_buf_exact() { fn borrowed_cursor_advance_overflow() { let mut buf = [0; 512]; let mut buf = BorrowedBuf::from(&mut buf[..]); - buf.unfilled().advance(1); - buf.unfilled().advance(usize::MAX); + buf.unfilled().advance_checked(1); + buf.unfilled().advance_checked(usize::MAX); } #[test] @@ -273,7 +279,7 @@ fn chain_bufread() { #[test] fn chain_splitted_char() { let chain = b"\xc3".chain(b"\xa9".as_slice()); - assert_eq!(crate::io::read_to_string(chain).unwrap(), "é"); + assert_eq!(alloc::io::read_to_string(chain).unwrap(), "é"); let mut chain = b"\xc3".chain(b"\xa9\n".as_slice()); let mut buf = String::new(); @@ -363,7 +369,7 @@ fn bench_read_to_end(b: &mut test::Bencher) { b.iter(|| { let mut lr = repeat(1).take(10000000); let mut vec = Vec::with_capacity(1024); - super::default_read_to_end(&mut lr, &mut vec, None) + alloc::io::default_read_to_end(&mut lr, &mut vec, None) }); } @@ -565,104 +571,6 @@ fn test_read_to_end_capacity() -> io::Result<()> { Ok(()) } -#[test] -fn io_slice_mut_advance_slices() { - let mut buf1 = [1; 8]; - let mut buf2 = [2; 16]; - let mut buf3 = [3; 8]; - let mut bufs = &mut [ - IoSliceMut::new(&mut buf1), - IoSliceMut::new(&mut buf2), - IoSliceMut::new(&mut buf3), - ][..]; - - // Only in a single buffer.. - IoSliceMut::advance_slices(&mut bufs, 1); - assert_eq!(bufs[0].deref(), [1; 7].as_ref()); - assert_eq!(bufs[1].deref(), [2; 16].as_ref()); - assert_eq!(bufs[2].deref(), [3; 8].as_ref()); - - // Removing a buffer, leaving others as is. - IoSliceMut::advance_slices(&mut bufs, 7); - assert_eq!(bufs[0].deref(), [2; 16].as_ref()); - assert_eq!(bufs[1].deref(), [3; 8].as_ref()); - - // Removing a buffer and removing from the next buffer. - IoSliceMut::advance_slices(&mut bufs, 18); - assert_eq!(bufs[0].deref(), [3; 6].as_ref()); -} - -#[test] -#[should_panic] -fn io_slice_mut_advance_slices_empty_slice() { - let mut empty_bufs = &mut [][..]; - IoSliceMut::advance_slices(&mut empty_bufs, 1); -} - -#[test] -#[should_panic] -fn io_slice_mut_advance_slices_beyond_total_length() { - let mut buf1 = [1; 8]; - let mut bufs = &mut [IoSliceMut::new(&mut buf1)][..]; - - IoSliceMut::advance_slices(&mut bufs, 9); - assert!(bufs.is_empty()); -} - -#[test] -fn io_slice_advance_slices() { - let buf1 = [1; 8]; - let buf2 = [2; 16]; - let buf3 = [3; 8]; - let mut bufs = &mut [IoSlice::new(&buf1), IoSlice::new(&buf2), IoSlice::new(&buf3)][..]; - - // Only in a single buffer.. - IoSlice::advance_slices(&mut bufs, 1); - assert_eq!(bufs[0].deref(), [1; 7].as_ref()); - assert_eq!(bufs[1].deref(), [2; 16].as_ref()); - assert_eq!(bufs[2].deref(), [3; 8].as_ref()); - - // Removing a buffer, leaving others as is. - IoSlice::advance_slices(&mut bufs, 7); - assert_eq!(bufs[0].deref(), [2; 16].as_ref()); - assert_eq!(bufs[1].deref(), [3; 8].as_ref()); - - // Removing a buffer and removing from the next buffer. - IoSlice::advance_slices(&mut bufs, 18); - assert_eq!(bufs[0].deref(), [3; 6].as_ref()); -} - -#[test] -#[should_panic] -fn io_slice_advance_slices_empty_slice() { - let mut empty_bufs = &mut [][..]; - IoSlice::advance_slices(&mut empty_bufs, 1); -} - -#[test] -#[should_panic] -fn io_slice_advance_slices_beyond_total_length() { - let buf1 = [1; 8]; - let mut bufs = &mut [IoSlice::new(&buf1)][..]; - - IoSlice::advance_slices(&mut bufs, 9); - assert!(bufs.is_empty()); -} - -#[test] -fn io_slice_as_slice() { - let buf = [1; 8]; - let slice = IoSlice::new(&buf).as_slice(); - assert_eq!(slice, buf); -} - -#[test] -fn io_slice_into_slice() { - let mut buf = [1; 8]; - let slice = IoSliceMut::new(&mut buf).into_slice(); - assert_eq!(slice, [1; 8]); -} - /// Creates a new writer that reads from at most `n_bufs` and reads /// `per_call` bytes (in total) per call to write. fn test_writer(n_bufs: usize, per_call: usize) -> TestWriter { @@ -832,7 +740,7 @@ fn bench_take_read_buf(b: &mut test::Bencher) { b.iter(|| { let buf: &mut [_] = &mut [MaybeUninit::uninit(); 64]; - let mut buf: BorrowedBuf<'_> = buf.into(); + let mut buf: BorrowedBuf<'_, u8> = buf.into(); [255; 128].take(64).read_buf(buf.unfilled()).unwrap(); }); @@ -874,7 +782,7 @@ impl Read for DataAndErrorReader { panic!("We want tests to use `read_buf`") } - fn read_buf(&mut self, buf: io::BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, buf: io::BorrowedCursor<'_, u8>) -> io::Result<()> { self.0.read_buf(buf).unwrap(); Err(io::Error::other("error")) } diff --git a/library/std/src/io/util/tests.rs b/library/alloctests/tests/io/util.rs similarity index 86% rename from library/std/src/io/util/tests.rs rename to library/alloctests/tests/io/util.rs index d0f106d7af416..52e0c3013dde7 100644 --- a/library/std/src/io/util/tests.rs +++ b/library/alloctests/tests/io/util.rs @@ -1,9 +1,9 @@ -use crate::fmt; -use crate::io::prelude::*; -use crate::io::{ - BorrowedBuf, Empty, ErrorKind, IoSlice, IoSliceMut, Repeat, SeekFrom, Sink, empty, repeat, sink, +use alloc::io::{ + BorrowedBuf, Empty, ErrorKind, IoSlice, IoSliceMut, Read, Repeat, Seek, SeekFrom, Sink, Write, + empty, repeat, sink, }; -use crate::mem::MaybeUninit; +use core::fmt; +use core::mem::MaybeUninit; struct ErrorDisplay; @@ -72,55 +72,55 @@ fn empty_reads() { assert_eq!(e.read_vectored(bufs).unwrap(), 0); let buf: &mut [MaybeUninit<_>] = &mut []; - let mut buf: BorrowedBuf<'_> = buf.into(); + let mut buf: BorrowedBuf<'_, u8> = buf.into(); e.read_buf(buf.unfilled()).unwrap(); assert_eq!(buf.len(), 0); - assert_eq!(buf.init_len(), 0); + assert!(!buf.is_init()); let buf: &mut [_] = &mut [MaybeUninit::uninit()]; - let mut buf: BorrowedBuf<'_> = buf.into(); + let mut buf: BorrowedBuf<'_, u8> = buf.into(); e.read_buf(buf.unfilled()).unwrap(); assert_eq!(buf.len(), 0); - assert_eq!(buf.init_len(), 0); + assert!(!buf.is_init()); let buf: &mut [_] = &mut [MaybeUninit::uninit(); 1024]; - let mut buf: BorrowedBuf<'_> = buf.into(); + let mut buf: BorrowedBuf<'_, u8> = buf.into(); e.read_buf(buf.unfilled()).unwrap(); assert_eq!(buf.len(), 0); - assert_eq!(buf.init_len(), 0); + assert!(!buf.is_init()); let buf: &mut [_] = &mut [MaybeUninit::uninit(); 1024]; - let mut buf: BorrowedBuf<'_> = buf.into(); + let mut buf: BorrowedBuf<'_, u8> = buf.into(); Read::by_ref(&mut e).read_buf(buf.unfilled()).unwrap(); assert_eq!(buf.len(), 0); - assert_eq!(buf.init_len(), 0); + assert!(!buf.is_init()); let buf: &mut [MaybeUninit<_>] = &mut []; - let mut buf: BorrowedBuf<'_> = buf.into(); + let mut buf: BorrowedBuf<'_, u8> = buf.into(); e.read_buf_exact(buf.unfilled()).unwrap(); assert_eq!(buf.len(), 0); - assert_eq!(buf.init_len(), 0); + assert!(!buf.is_init()); let buf: &mut [_] = &mut [MaybeUninit::uninit()]; - let mut buf: BorrowedBuf<'_> = buf.into(); + let mut buf: BorrowedBuf<'_, u8> = buf.into(); assert_eq!(e.read_buf_exact(buf.unfilled()).unwrap_err().kind(), ErrorKind::UnexpectedEof); assert_eq!(buf.len(), 0); - assert_eq!(buf.init_len(), 0); + assert!(!buf.is_init()); let buf: &mut [_] = &mut [MaybeUninit::uninit(); 1024]; - let mut buf: BorrowedBuf<'_> = buf.into(); + let mut buf: BorrowedBuf<'_, u8> = buf.into(); assert_eq!(e.read_buf_exact(buf.unfilled()).unwrap_err().kind(), ErrorKind::UnexpectedEof); assert_eq!(buf.len(), 0); - assert_eq!(buf.init_len(), 0); + assert!(!buf.is_init()); let buf: &mut [_] = &mut [MaybeUninit::uninit(); 1024]; - let mut buf: BorrowedBuf<'_> = buf.into(); + let mut buf: BorrowedBuf<'_, u8> = buf.into(); assert_eq!( Read::by_ref(&mut e).read_buf_exact(buf.unfilled()).unwrap_err().kind(), ErrorKind::UnexpectedEof, ); assert_eq!(buf.len(), 0); - assert_eq!(buf.init_len(), 0); + assert!(!buf.is_init()); let mut buf = Vec::new(); assert_eq!(e.read_to_end(&mut buf).unwrap(), 0); diff --git a/library/alloctests/tests/lib.rs b/library/alloctests/tests/lib.rs index e15c86496cf1b..b2a3e8f8f8e2a 100644 --- a/library/alloctests/tests/lib.rs +++ b/library/alloctests/tests/lib.rs @@ -1,53 +1,68 @@ +// tidy-alphabetical-start +#![allow(internal_features)] +#![deny(implicit_provenance_casts)] +#![deny(unsafe_op_in_unsafe_fn)] +#![feature(alloc_io)] #![feature(allocator_api)] +#![feature(binary_heap_drain_sorted)] +#![feature(binary_heap_into_iter_sorted)] #![feature(binary_heap_pop_if)] +#![feature(borrowed_buf_init)] +#![feature(bstr)] +#![feature(bstr_to_string)] +#![feature(buf_read_has_data_left)] +#![feature(can_vector)] +#![feature(casefold)] +#![feature(const_btree_len)] +#![feature(const_cmp)] #![feature(const_heap)] -#![feature(deque_extend_front)] -#![feature(iter_array_chunks)] -#![feature(assert_matches)] -#![feature(wtf8_internals)] -#![feature(cow_is_borrowed)] +#![feature(const_trait_impl)] #![feature(core_intrinsics)] +#![feature(core_io_borrowed_buf)] +#![feature(core_io_internals)] +#![feature(cow_is_borrowed)] +#![feature(cursor_split)] +#![feature(deque_extend_front)] #![feature(downcast_unchecked)] +#![feature(drain_keep_rest)] #![feature(exact_size_is_empty)] #![feature(hashmap_internals)] -#![feature(int_format_into)] +#![feature(inplace_iteration)] +#![feature(io_const_error)] +#![feature(iter_advance_by)] +#![feature(iter_array_chunks)] +#![feature(iter_next_chunk)] #![feature(linked_list_cursors)] +#![feature(local_waker)] +#![feature(macro_metavar_expr_concat)] #![feature(map_try_insert)] #![feature(pattern)] -#![feature(trusted_len)] -#![feature(try_reserve_kind)] -#![feature(try_with_capacity)] -#![feature(unboxed_closures)] -#![feature(binary_heap_into_iter_sorted)] -#![feature(binary_heap_drain_sorted)] -#![feature(slice_ptr_get)] -#![feature(slice_range)] +#![feature(ptr_cast_slice)] +#![feature(read_buf)] +#![feature(seek_io_take_position)] +#![feature(seek_stream_len)] #![feature(slice_partial_sort_unstable)] -#![feature(inplace_iteration)] -#![feature(iter_advance_by)] -#![feature(iter_next_chunk)] #![feature(slice_partition_dedup)] -#![feature(string_from_utf8_lossy_owned)] -#![feature(string_remove_matches)] -#![feature(const_btree_len)] -#![feature(const_trait_impl)] -#![feature(panic_update_hook)] -#![feature(pointer_is_aligned_to)] -#![feature(test)] -#![feature(thin_box)] -#![feature(drain_keep_rest)] -#![feature(local_waker)] +#![feature(slice_ptr_get)] +#![feature(slice_range)] #![feature(str_as_str)] +#![feature(str_copy_from_str)] #![feature(strict_provenance_lints)] +#![feature(string_remove_matches)] #![feature(string_replace_in_place)] -#![feature(vec_deque_truncate_front)] +#![feature(test)] +#![feature(thin_box)] +#![feature(titlecase)] +#![feature(trusted_len)] +#![feature(try_reserve_kind)] +#![feature(try_with_capacity)] +#![feature(unboxed_closures)] #![feature(unique_rc_arc)] -#![feature(macro_metavar_expr_concat)] +#![feature(vec_deque_retain_range)] #![feature(vec_peek_mut)] #![feature(vec_try_remove)] -#![allow(internal_features)] -#![deny(fuzzy_provenance_casts)] -#![deny(unsafe_op_in_unsafe_fn)] +#![feature(write_all_vectored)] +// tidy-alphabetical-end extern crate alloc; @@ -58,6 +73,7 @@ mod arc; mod autotraits; mod borrow; mod boxed; +mod bstr; mod btree_set_hash; mod c_str; mod c_str2; @@ -66,6 +82,7 @@ mod const_fns; mod cow_str; mod fmt; mod heap; +mod io; mod linked_list; mod misc_tests; mod num; diff --git a/library/alloctests/tests/rc.rs b/library/alloctests/tests/rc.rs index bb68eb4ac9e3d..0009d6fbc7058 100644 --- a/library/alloctests/tests/rc.rs +++ b/library/alloctests/tests/rc.rs @@ -87,6 +87,34 @@ fn eq() { assert_eq!(*x.0.borrow(), 0); } +#[test] +fn eq_unsized() { + #[derive(Eq)] + struct TestEq(RefCell, T); + impl PartialEq for TestEq { + fn eq(&self, other: &TestEq) -> bool { + *self.0.borrow_mut() += 1; + *other.0.borrow_mut() += 1; + true + } + } + let x = Rc::>::new(TestEq(RefCell::new(0), [0, 1, 2])) as Rc>; + assert!(x == x); + assert!(!(x != x)); + assert_eq!(*x.0.borrow(), 0); +} + +#[test] +fn eq_unsized_slice() { + let a: Rc<[()]> = Rc::new([(); 3]); + let ptr: *const () = Rc::into_raw(a.clone()).cast(); + let b: Rc<[()]> = unsafe { Rc::from_raw(ptr.cast_slice(42)) }; + assert!(a == a); + assert!(!(a != a)); + assert!(a != b); + assert!(!(a == b)); +} + const SHARED_ITER_MAX: u16 = 100; fn assert_trusted_len(_: &I) {} @@ -922,3 +950,28 @@ fn test_unique_rc_unsizing_coercion() { let rc: Rc<[u8]> = UniqueRc::into_rc(rc); assert_eq!(*rc, [123, 0, 0]); } + +/// Test that `Rc::make_mut` does not forget an allocator when it steals the data. +#[test] +fn issue_158875_make_mut_dont_leak_allocator() { + use std::alloc::Global; + + let alloc = Rc::new(Global); + + { + let mut arc = Rc::new_in(123, alloc.clone()); + let weak = Rc::downgrade(&arc); // create a weak so make_mut steals the data + _ = Rc::make_mut(&mut arc); + assert_eq!(weak.upgrade(), None); + } + + assert_eq!(Rc::strong_count(&alloc), 1); // if this is >1, we have a memory leak! +} + +#[test] +#[should_panic = "capacity overflow"] +fn new_uninit_slice_capacity_overflow() { + // header + payload layout exceeds isize::MAX -> "capacity overflow", not + // an unwrapped LayoutError. Regression test for #136797. + let _ = Rc::<[u8]>::new_uninit_slice(isize::MAX as usize); +} diff --git a/library/alloctests/tests/slice.rs b/library/alloctests/tests/slice.rs index 1e15d54d979a2..1194e48f38cfa 100644 --- a/library/alloctests/tests/slice.rs +++ b/library/alloctests/tests/slice.rs @@ -909,7 +909,8 @@ fn test_split_iterators_size_hint() { // become maximally long, so the size_hint upper bounds are tight ((|_| true) as fn(&_) -> _, Bounds::Upper), ] { - use {assert_tight_size_hints as a, format_args as f}; + use assert_tight_size_hints as a; + use format_args as f; a(v.split(p), b, "split"); a(v.split_mut(p), b, "split_mut"); diff --git a/library/alloctests/tests/sort/tests.rs b/library/alloctests/tests/sort/tests.rs index 09b76773d6b24..ec4c4fa619ddf 100644 --- a/library/alloctests/tests/sort/tests.rs +++ b/library/alloctests/tests/sort/tests.rs @@ -746,7 +746,7 @@ fn self_cmp( pattern_fn(len).into_iter().map(|val| type_into_fn(val)).collect::>(); let comparison_fn = |a: &T, b: &T| { - assert_ne!(a as *const T as usize, b as *const T as usize); + assert_ne!(a as *const T, b as *const T); a.cmp(b) }; diff --git a/library/alloctests/tests/str.rs b/library/alloctests/tests/str.rs index fcc4aaaa1dcd1..830f6972f5af5 100644 --- a/library/alloctests/tests/str.rs +++ b/library/alloctests/tests/str.rs @@ -164,7 +164,7 @@ fn test_join_for_different_lengths_with_long_separator() { } #[test] -fn test_join_issue_80335() { +fn test_join_inconsistent_borrow_shrink() { use core::borrow::Borrow; use core::cell::Cell; @@ -191,7 +191,26 @@ fn test_join_issue_80335() { } let arr: [WeirdBorrow; 3] = Default::default(); - test_join!("0-0-0", arr, "-"); + test_join!("123456-0-0", arr, "-"); +} + +#[test] +#[should_panic(expected = "mid > len")] +fn test_join_inconsistent_borrow_grow() { + use std::borrow::Borrow; + use std::cell::Cell; + + struct E(Cell); + + impl Borrow for E { + fn borrow(&self) -> &str { + let count = self.0.get(); + self.0.set(count + 1); + if count == 0 { "" } else { "longer string" } + } + } + + let _s = [E(Cell::new(0)), E(Cell::new(0))].join(""); } #[test] @@ -612,14 +631,14 @@ mod slice_index { data: "abcdef"; good: data[4..4] == ""; bad: data[4..3]; - message: "begin <= end (4 <= 3)"; + message: "byte range starts at 4 but ends at 3"; } in mod rangeinclusive_neg_width { data: "abcdef"; good: data[4..=3] == ""; bad: data[4..=2]; - message: "begin <= end (4 <= 3)"; + message: "byte range starts at 4 but ends at 3"; } } @@ -630,13 +649,13 @@ mod slice_index { // note: using 0 specifically ensures that the result of overflowing is 0..0, // so that `get` doesn't simply return None for the wrong reason. bad: data[0..=usize::MAX]; - message: "maximum usize"; + message: "out of bounds"; } in mod rangetoinclusive { data: "hello"; bad: data[..=usize::MAX]; - message: "maximum usize"; + message: "out of bounds"; } } } @@ -659,49 +678,49 @@ mod slice_index { data: super::DATA; bad: data[super::BAD_START..super::GOOD_END]; message: - "byte index 4 is not a char boundary; it is inside 'α' (bytes 3..5) of"; + "start byte index 4 is not a char boundary; it is inside 'α' (bytes 3..5 of string)"; } in mod range_2 { data: super::DATA; bad: data[super::GOOD_START..super::BAD_END]; message: - "byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7) of"; + "end byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7 of string)"; } in mod rangefrom { data: super::DATA; bad: data[super::BAD_START..]; message: - "byte index 4 is not a char boundary; it is inside 'α' (bytes 3..5) of"; + "start byte index 4 is not a char boundary; it is inside 'α' (bytes 3..5 of string)"; } in mod rangeto { data: super::DATA; bad: data[..super::BAD_END]; message: - "byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7) of"; + "end byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7 of string)"; } in mod rangeinclusive_1 { data: super::DATA; bad: data[super::BAD_START..=super::GOOD_END_INCL]; message: - "byte index 4 is not a char boundary; it is inside 'α' (bytes 3..5) of"; + "start byte index 4 is not a char boundary; it is inside 'α' (bytes 3..5 of string)"; } in mod rangeinclusive_2 { data: super::DATA; bad: data[super::GOOD_START..=super::BAD_END_INCL]; message: - "byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7) of"; + "end byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7 of string)"; } in mod rangetoinclusive { data: super::DATA; bad: data[..=super::BAD_END_INCL]; message: - "byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7) of"; + "end byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7 of string)"; } } } @@ -716,16 +735,10 @@ mod slice_index { // check the panic includes the prefix of the sliced string #[test] - #[should_panic(expected = "byte index 1024 is out of bounds of `Lorem ipsum dolor sit amet")] + #[should_panic(expected = "end byte index 1024 is out of bounds for string of length 416")] fn test_slice_fail_truncated_1() { let _ = &LOREM_PARAGRAPH[..1024]; } - // check the truncation in the panic message - #[test] - #[should_panic(expected = "luctus, im`[...]")] - fn test_slice_fail_truncated_2() { - let _ = &LOREM_PARAGRAPH[..1024]; - } } #[test] @@ -1095,6 +1108,21 @@ fn test_split_at_boundscheck() { let _ = s.split_at(1); } +#[test] +fn test_copy_from_str() { + let src = "Saludos"; + let mut dst = "Grüße, Jürgen".to_string(); + dst[..7].copy_from_str(src); + assert_eq!(dst, "Saludos, Jürgen"); +} + +#[test] +#[should_panic] +fn test_copy_from_str_unequal_len() { + let mut dst = "hello".to_string(); + dst.copy_from_str("hi"); +} + #[test] fn test_escape_unicode() { assert_eq!("abc".escape_unicode().to_string(), "\\u{61}\\u{62}\\u{63}"); @@ -1772,6 +1800,21 @@ fn test_utf16_size_hint() { assert_eq!(hint_vec("\u{101234}a"), [(2, Some(5)), (2, Some(2)), (1, Some(1)), (0, Some(0))]); } +#[test] +fn test_utf16_count() { + assert_eq!("".encode_utf16().count(), 0); + assert_eq!("a".encode_utf16().count(), 1); + assert_eq!("é".encode_utf16().count(), 1); + assert_eq!("字".encode_utf16().count(), 1); + assert_eq!("\u{1F4A9}".encode_utf16().count(), 2); + let mut iter = "\u{1F4A9}字éa".encode_utf16(); + assert_eq!(iter.clone().count(), 5); + iter.next(); + assert_eq!(iter.clone().count(), 4); // counting half of the surrogate pair + iter.next(); + assert_eq!(iter.count(), 3); +} + #[test] fn starts_with_in_unicode() { assert!(!"├── Cargo.toml".starts_with("# ")); @@ -1873,7 +1916,63 @@ fn to_lowercase() { #[test] fn to_uppercase() { assert_eq!("".to_uppercase(), ""); - assert_eq!("aéDžßfiᾀ".to_uppercase(), "AÉDŽSSFIἈΙ"); + assert_eq!("aéDžßẞfiᾀ".to_uppercase(), "AÉDŽSSẞFIἈΙ"); +} + +#[test] +fn word_to_titlecase() { + // ASCII fast path: first cased letter is upper-cased, the rest lower-cased. + assert_eq!("hello WORLD".word_to_titlecase(), "Hello world"); + assert_eq!("HELLO".word_to_titlecase(), "Hello"); + + // Leading uncased characters pass through, then the first cased letter is title-cased. + assert_eq!("'twas".word_to_titlecase(), "'Twas"); + assert_eq!("123 abc".word_to_titlecase(), "123 Abc"); + + // Empty and no-cased-character inputs are unchanged. + assert_eq!("".word_to_titlecase(), ""); + assert_eq!("农历新年".word_to_titlecase(), "农历新年"); + assert_eq!("123 456".word_to_titlecase(), "123 456"); + + // Final-sigma handling: Σ maps to ς at the end of a word, σ elsewhere. + assert_eq!("ὈΔΥΣΣΕΎΣ".word_to_titlecase(), "Ὀδυσσεύς"); + assert_eq!("ΑΣ".word_to_titlecase(), "Ας"); + assert_eq!("ΑΣΑ".word_to_titlecase(), "Ασα"); + + // Mixed ASCII prefix followed by a non-ASCII tail exercises the boundary index math, + // including around the chunk size used by the ASCII prefix optimization. + assert_eq!("HELLO ὈΔΥΣΣΕΎΣ".word_to_titlecase(), "Hello ὀδυσσεύς"); + assert_eq!("ABCDEFGHIJKLMNOΣ".word_to_titlecase(), "Abcdefghijklmnoς"); + assert_eq!("ABCDEFGHIJKLMNOPΣ".word_to_titlecase(), "Abcdefghijklmnopς"); + assert_eq!("ABCDEFGHIJKLMNOPQΣ".word_to_titlecase(), "Abcdefghijklmnopqς"); + + // A long ASCII-only string exercises the auto-vectorized fast path. + assert_eq!(str::repeat("A", 511).word_to_titlecase(), { + let mut expected = String::from("A"); + expected.push_str(&str::repeat("a", 510)); + expected + }); + + // LJ ligatures and title-case characters. + // Lj is already a title-case letter, so it stays as the first char. + assert_eq!("Ljj".word_to_titlecase(), "Ljj"); + assert_eq!("LjJ".word_to_titlecase(), "Ljj"); + // l is the first cased char (uppercases to L), Lj lowercases to lj. + assert_eq!("lLjfi".word_to_titlecase(), "Lljfi"); + assert_eq!("LLjfi".word_to_titlecase(), "Lljfi"); + + // LJ ligatures: lower=lj (U+01C9), upper=LJ (U+01C7), title=Lj (U+01C8). + // ß decomposes to "Ss" in title case (first char) but stays ß elsewhere. + assert_eq!("ßljLJLj".word_to_titlecase(), "Ssljljlj"); + assert_eq!("ljLJLjß".word_to_titlecase(), "Ljljljß"); + assert_eq!("LJLjßlj".word_to_titlecase(), "Ljljßlj"); + assert_eq!("LjßljLJ".word_to_titlecase(), "Ljßljlj"); +} + +#[test] +fn to_casefold_unnormalized() { + assert_eq!("".to_casefold_unnormalized(), ""); + assert_eq!("ꮿfiῲὼ\u{0345}ßẞΣς".to_casefold_unnormalized(), "Ꮿfiὼιὼιssssσσ"); } #[test] @@ -2335,6 +2434,7 @@ fn utf8_char_counts() { .flat_map(|n| n - spread..=n + spread) .collect::>(); if cfg!(not(miri)) { + // Miri is too slow reps.extend([1024, 1 << 16].iter().copied().flat_map(|n| n - spread..=n + spread)); } let counts = if cfg!(miri) { 0..1 } else { 0..8 }; @@ -2411,6 +2511,16 @@ fn floor_char_boundary() { check_many("🇯🇵", 0..4, 0); check_many("🇯🇵", 4..8, 4); check_many("🇯🇵", 8..10, 8); + + // anticipate length- and index-based specializations + let s = "jpĵƥ日本🇯🇵jpĵƥ日本🇯🇵"; + let expected = [ + 0, 1, 2, 2, 4, 4, 6, 6, 6, 9, 9, 9, 12, 12, 12, 12, 16, 16, 16, 16, 20, 21, 22, 22, 24, 24, + 26, 26, 26, 29, 29, 29, 32, 32, 32, 32, 36, 36, 36, 36, 40, 40, 40, 40, + ]; + for (idx, &ret) in expected.iter().enumerate() { + check_many(s, [idx], ret); + } } #[test] @@ -2457,4 +2567,14 @@ fn ceil_char_boundary() { // above len check_many("hello", 5..=10, 5); + + // anticipate length- and index-based specializations + let s = "jpĵƥ日本🇯🇵jpĵƥ日本🇯🇵"; + let expected = [ + 0, 1, 2, 4, 4, 6, 6, 9, 9, 9, 12, 12, 12, 16, 16, 16, 16, 20, 20, 20, 20, 21, 22, 24, 24, + 26, 26, 29, 29, 29, 32, 32, 32, 36, 36, 36, 36, 40, 40, 40, 40, 40, 40, 40, + ]; + for (idx, &ret) in expected.iter().enumerate() { + check_many(s, [idx], ret); + } } diff --git a/library/alloctests/tests/sync.rs b/library/alloctests/tests/sync.rs index 6d3ab1b1d11e1..5742855768c70 100644 --- a/library/alloctests/tests/sync.rs +++ b/library/alloctests/tests/sync.rs @@ -469,8 +469,6 @@ fn test_weak_count_locked() { while !a2.load(SeqCst) { let n = Arc::weak_count(&a2); assert!(n < 2, "bad weak count: {}", n); - #[cfg(miri)] // Miri's scheduler does not guarantee liveness, and thus needs this hint. - std::hint::spin_loop(); } t.join().unwrap(); } diff --git a/library/alloctests/tests/vec.rs b/library/alloctests/tests/vec.rs index 5ab305f7a5048..077005afd5d38 100644 --- a/library/alloctests/tests/vec.rs +++ b/library/alloctests/tests/vec.rs @@ -1027,6 +1027,15 @@ fn test_into_iter_next_chunk() { assert_eq!(iter.next_chunk::<4>().unwrap_err().as_slice(), &[]); // N is explicitly 4 } +#[test] +fn test_into_iter_next_chunk_back() { + let mut iter = b"lorem".to_vec().into_iter(); + + assert_eq!(iter.next_chunk_back().unwrap(), [b'e', b'm']); // N is inferred as 2 + assert_eq!(iter.next_chunk_back().unwrap(), [b'l', b'o', b'r']); // N is inferred as 3 + assert_eq!(iter.next_chunk_back::<4>().unwrap_err().as_slice(), &[]); // N is explicitly 4 +} + #[test] fn test_into_iter_clone() { fn iter_equal>(it: I, slice: &[i32]) { @@ -1110,7 +1119,7 @@ fn test_into_iter_zst() { struct AlignedZstWithDrop([u64; 0]); impl Drop for AlignedZstWithDrop { fn drop(&mut self) { - let addr = self as *mut _ as usize; + let addr = (self as *mut Self).addr(); assert!(hint::black_box(addr) % align_of::() == 0); } } @@ -1131,6 +1140,14 @@ fn test_into_iter_zst() { let mut it = vec![C, C].into_iter(); it.next_chunk::<4>().unwrap_err(); drop(it); + + let mut it = vec![C, C].into_iter(); + it.next_chunk_back::<1>().unwrap(); + drop(it); + + let mut it = vec![C, C].into_iter(); + it.next_chunk_back::<4>().unwrap_err(); + drop(it); } #[test] @@ -1356,10 +1373,10 @@ fn overaligned_allocations() { for i in 0..0x1000 { v.reserve_exact(i); assert!(v[0].0 == 273); - assert!(v.as_ptr() as usize & 0xff == 0); + assert!(v.as_ptr().addr() & 0xff == 0); v.shrink_to_fit(); assert!(v[0].0 == 273); - assert!(v.as_ptr() as usize & 0xff == 0); + assert!(v.as_ptr().addr() & 0xff == 0); } } @@ -1651,13 +1668,17 @@ fn extract_if_unconsumed() { #[test] fn extract_if_debug() { - let mut vec = vec![1, 2]; - let mut drain = vec.extract_if(.., |&mut x| x % 2 != 0); - assert!(format!("{drain:?}").contains("Some(1)")); - drain.next(); - assert!(format!("{drain:?}").contains("Some(2)")); - drain.next(); - assert!(format!("{drain:?}").contains("None")); + let mut vec = vec![1, 2, 3, 4, 5, 6, 7, 8]; + let mut drain = vec.extract_if(1..5, |&mut x| x % 2 != 0); + assert_eq!( + format!("{drain:?}"), + "ExtractIf { retained: [1], remainder: [2, 3, 4, 5], skipped_tail: [6, 7, 8], .. }" + ); + drain.next().unwrap(); + assert_eq!( + format!("{drain:?}"), + "ExtractIf { retained: [1, 2], remainder: [4, 5], skipped_tail: [6, 7, 8], .. }" + ); } #[test] @@ -2537,7 +2558,7 @@ fn test_extend_from_within_panicking_clone() { } #[test] -#[should_panic = "vec len overflow"] +#[should_panic = "the product of vec len and N shouldn't overflow"] fn test_into_flattened_size_overflow() { let v = vec![[(); usize::MAX]; 2]; let _ = v.into_flattened(); @@ -2565,12 +2586,12 @@ fn test_box_zero_allocator() { } else { unsafe { std::alloc::alloc(layout) } }; - Ok(NonNull::slice_from_raw_parts(NonNull::new(ptr).ok_or(AllocError)?, layout.size())) + Ok(NonNull::new(ptr).ok_or(AllocError)?.cast_slice(layout.size())) } unsafe fn deallocate(&self, ptr: NonNull, layout: Layout) { if layout.size() == 0 { - let addr = ptr.as_ptr() as usize; + let addr = ptr.as_ptr().addr(); let mut state = self.state.borrow_mut(); std::println!("freeing {addr}"); assert!(state.0.remove(&addr), "ZST free that wasn't allocated"); @@ -2764,3 +2785,48 @@ fn const_heap() { assert_eq!([1, 2, 4, 8, 16, 32], X); } + +// regression test for issue #153158. `const_make_global` previously assumed `Vec`'s buf +// always has a heap allocation, which lead to compilation errors. +#[test] +fn const_make_global_empty_or_zst_regression() { + const EMPTY_SLICE: &'static [i32] = { + let empty_vec: Vec = Vec::new(); + empty_vec.const_make_global() + }; + + assert_eq!(EMPTY_SLICE, &[]); + + const ZST_SLICE: &'static [()] = { + let mut zst_vec: Vec<()> = Vec::new(); + zst_vec.push(()); + zst_vec.push(()); + zst_vec.push(()); + zst_vec.const_make_global() + }; + + assert_eq!(ZST_SLICE, &[(), (), ()]); +} + +#[test] +fn const_heap_vec_macro() { + const X: &'static [u32] = { + let x: Vec = vec![]; + assert!(x == []); + x.const_make_global() + }; + + const Y: &'static [u32] = { + let y: Vec = vec![1, 2, 3]; + assert!(y == [1, 2, 3]); + y.const_make_global() + }; + + // This arm isn't const yet. + // const Z: &'static [u32] = { + // vec![4; 2].const_make_global() + // }; + + assert_eq!(X, []); + assert_eq!(Y, [1, 2, 3]); +} diff --git a/library/alloctests/tests/vec_deque.rs b/library/alloctests/tests/vec_deque.rs index 92853fe00fd63..15cc156d6988f 100644 --- a/library/alloctests/tests/vec_deque.rs +++ b/library/alloctests/tests/vec_deque.rs @@ -7,6 +7,7 @@ use std::collections::vec_deque::Drain; use std::fmt::Debug; use std::ops::Bound::*; use std::panic::{AssertUnwindSafe, catch_unwind}; +use std::sync::atomic::{AtomicUsize, Ordering}; use Taggy::*; use Taggypar::*; @@ -1635,7 +1636,7 @@ fn truncate_leak() { #[test] #[cfg_attr(not(panic = "unwind"), ignore = "test requires unwinding support")] -fn truncate_front_leak() { +fn retain_back_leak() { struct_with_counted_drop!(D(bool), DROPS => |this: &D| if this.0 { panic!("panic in `drop`"); } ); let mut q = VecDeque::new(); @@ -1648,7 +1649,7 @@ fn truncate_front_leak() { q.push_front(D(false)); q.push_front(D(false)); - catch_unwind(AssertUnwindSafe(|| q.truncate_front(1))).ok(); + catch_unwind(AssertUnwindSafe(|| q.retain_back(1))).ok(); assert_eq!(DROPS.get(), 7); } @@ -1817,20 +1818,20 @@ fn test_collect_from_into_iter_keeps_allocation() { } #[test] -fn test_truncate_front() { +fn test_retain_back() { let mut v = VecDeque::with_capacity(13); v.extend(0..7); assert_eq!(v.as_slices(), ([0, 1, 2, 3, 4, 5, 6].as_slice(), [].as_slice())); - v.truncate_front(10); + v.retain_back(10); assert_eq!(v.len(), 7); assert_eq!(v.as_slices(), ([0, 1, 2, 3, 4, 5, 6].as_slice(), [].as_slice())); - v.truncate_front(7); + v.retain_back(7); assert_eq!(v.len(), 7); assert_eq!(v.as_slices(), ([0, 1, 2, 3, 4, 5, 6].as_slice(), [].as_slice())); - v.truncate_front(3); + v.retain_back(3); assert_eq!(v.as_slices(), ([4, 5, 6].as_slice(), [].as_slice())); assert_eq!(v.len(), 3); - v.truncate_front(0); + v.retain_back(0); assert_eq!(v.as_slices(), ([].as_slice(), [].as_slice())); assert_eq!(v.len(), 0); @@ -1841,13 +1842,13 @@ fn test_truncate_front() { v.push_front(8); v.push_front(7); assert_eq!(v.as_slices(), ([7, 8, 9].as_slice(), [0, 1, 2, 3, 4, 5, 6].as_slice())); - v.truncate_front(12); + v.retain_back(12); assert_eq!(v.as_slices(), ([7, 8, 9].as_slice(), [0, 1, 2, 3, 4, 5, 6].as_slice())); - v.truncate_front(10); + v.retain_back(10); assert_eq!(v.as_slices(), ([7, 8, 9].as_slice(), [0, 1, 2, 3, 4, 5, 6].as_slice())); - v.truncate_front(8); + v.retain_back(8); assert_eq!(v.as_slices(), ([9].as_slice(), [0, 1, 2, 3, 4, 5, 6].as_slice())); - v.truncate_front(5); + v.retain_back(5); assert_eq!(v.as_slices(), ([2, 3, 4, 5, 6].as_slice(), [].as_slice())); } @@ -1855,7 +1856,7 @@ fn test_truncate_front() { fn test_extend_from_within() { let mut v = VecDeque::with_capacity(8); v.extend(0..6); - v.truncate_front(4); + v.retain_back(4); assert_eq!(v, [2, 3, 4, 5]); v.extend_from_within(1..4); assert_eq!(v, [2, 3, 4, 5, 3, 4, 5]); @@ -1915,7 +1916,7 @@ fn test_extend_from_within_clone() { panic: false, })); // remove the dummy elements - v.truncate_front(4); + v.retain_back(4); assert_eq!(v.iter().map(|tr| tr.id).collect::>(), [0, 1, 2, 3]); v.extend_from_within(2..); @@ -1947,7 +1948,7 @@ fn test_extend_from_within_clone_panic() { panic: false, })); // remove the dummy elements - v.truncate_front(4); + v.retain_back(4); assert_eq!(v.iter().map(|tr| tr.id).collect::>(), [0, 1, 2, 3]); // panic after wrapping @@ -1963,7 +1964,7 @@ fn test_extend_from_within_clone_panic() { // nothing should have been dropped assert_eq!(drop_count.get(), 0); - v.truncate_front(2); + v.retain_back(2); assert_eq!(drop_count.get(), 4); assert_eq!(v.iter().map(|tr| tr.id).collect::>(), [0, 1]); @@ -1985,7 +1986,7 @@ fn test_extend_from_within_clone_panic() { fn test_prepend_from_within() { let mut v = VecDeque::with_capacity(8); v.extend(0..6); - v.truncate_front(4); + v.retain_back(4); v.prepend_from_within(..=0); assert_eq!(v.as_slices(), ([2, 2, 3, 4, 5].as_slice(), [].as_slice())); v.prepend_from_within(2..); @@ -2007,7 +2008,7 @@ fn test_prepend_from_within_clone() { panic: false, })); // remove the dummy elements - v.truncate_front(4); + v.retain_back(4); assert_eq!(v.iter().map(|tr| tr.id).collect::>(), [0, 1, 2, 3]); v.prepend_from_within(..2); @@ -2034,7 +2035,7 @@ fn test_prepend_from_within_clone_panic() { panic: false, })); // remove the dummy elements - v.truncate_front(4); + v.retain_back(4); assert_eq!(v.iter().map(|tr| tr.id).collect::>(), [0, 1, 2, 3]); // panic after wrapping @@ -2050,7 +2051,7 @@ fn test_prepend_from_within_clone_panic() { // nothing should have been dropped assert_eq!(drop_count.get(), 0); - v.truncate_front(2); + v.retain_back(2); assert_eq!(drop_count.get(), 4); assert_eq!(v.iter().map(|tr| tr.id).collect::>(), [2, 3]); @@ -2071,7 +2072,7 @@ fn test_prepend_from_within_clone_panic() { #[test] fn test_extend_and_prepend_from_within() { let mut v = ('0'..='9').map(String::from).collect::>(); - v.truncate_front(5); + v.retain_back(5); v.extend_from_within(4..); v.prepend_from_within(..2); assert_eq!(v.iter().map(|s| &**s).collect::(), "56567899"); @@ -2095,7 +2096,7 @@ fn test_extend_front() { let mut v = VecDeque::with_capacity(8); let cap = v.capacity(); v.extend(0..4); - v.truncate_front(2); + v.retain_back(2); v.extend_front(4..8); assert_eq!(v.as_slices(), ([7, 6].as_slice(), [5, 4, 2, 3].as_slice())); assert_eq!(v.capacity(), cap); @@ -2347,3 +2348,150 @@ fn test_splice_wrapping() { assert_eq!(Vec::from(vec), [7, 8, 9]); } + +#[test] +fn test_splice_wrapping_and_resize() { + let mut vec = VecDeque::new(); + + for i in [1; 6] { + vec.push_front(i); + } + + vec.splice(1..1, [2, 3, 4]); + + assert_eq!(Vec::from(vec), [1, 2, 3, 4, 1, 1, 1, 1, 1]) +} + +#[test] +fn truncate_to_range_basic() { + // no-op + let mut v: VecDeque<_> = (0..6).collect(); + v.truncate_to_range(..); + assert_eq!(v, [0, 1, 2, 3, 4, 5]); + + // clear + let mut v: VecDeque<_> = (0..6).collect(); + v.truncate_to_range(3..3); + assert_eq!(v, [] as [i32; 0]); + + // truncate + let mut v: VecDeque<_> = (0..6).collect(); + v.truncate_to_range(..3); + assert_eq!(v, [0, 1, 2]); + + // truncate front + let mut v: VecDeque<_> = (0..6).collect(); + v.truncate_to_range(2..); + assert_eq!(v, [2, 3, 4, 5]); + + let mut v: VecDeque<_> = (0..6).collect(); + v.truncate_to_range(2..5); + assert_eq!(v, [2, 3, 4]); + + let mut v: VecDeque<_> = (0..6).collect(); + v.truncate_to_range(3..=5); + assert_eq!(v, [3, 4, 5]); + + let mut v: VecDeque<_> = (0..6).collect(); + v.truncate_to_range(..=3); + assert_eq!(v, [0, 1, 2, 3]); +} + +fn make_wrapped() -> VecDeque { + let mut v = VecDeque::new(); + v.extend(0..5); + v.push_front(-1); + v.push_front(-2); + v.push_front(-3); + assert_eq!(v.as_slices(), ([-3, -2, -1].as_slice(), [0, 1, 2, 3, 4].as_slice())); + v +} + +#[test] +fn truncate_to_range_kept_in_front() { + let mut v = make_wrapped(); + v.truncate_to_range(1..3); + assert_eq!(v, [-2, -1]); +} + +#[test] +fn truncate_to_range_kept_in_back() { + let mut v = make_wrapped(); + v.truncate_to_range(4..7); + assert_eq!(v, [1, 2, 3]); +} + +#[test] +fn truncate_to_range_kept_straddles() { + let mut v = make_wrapped(); + v.truncate_to_range(1..6); + assert_eq!(v, [-2, -1, 0, 1, 2]); +} + +#[test] +#[cfg_attr(not(panic = "unwind"), ignore = "test requires unwinding support")] +fn truncate_to_range_leak() { + struct_with_counted_drop!(D(bool), DROPS => |this: &D| if this.0 { panic!("panic in `drop`"); } ); + + let mut q = VecDeque::new(); + q.push_back(D(true)); + q.push_back(D(false)); + q.push_back(D(false)); + q.push_back(D(false)); + q.push_back(D(false)); + q.push_front(D(false)); + q.push_front(D(false)); + q.push_front(D(false)); + + catch_unwind(AssertUnwindSafe(|| q.truncate_to_range(4..7))).ok(); + + assert_eq!(DROPS.get(), 5); +} + +#[test] +fn truncate_to_range_calls_drop() { + static DROPPED: AtomicUsize = AtomicUsize::new(0); + + #[derive(Debug)] + struct Foo(u8); + + impl Drop for Foo { + fn drop(&mut self) { + DROPPED.fetch_add(1, Ordering::Relaxed); + } + } + + let mut deque: VecDeque<_> = (0..12).map(Foo).collect(); + deque.truncate_to_range(1..5); + assert!(deque.iter().map(|x| x.0).eq([1, 2, 3, 4])); + assert_eq!(8, DROPPED.load(Ordering::Relaxed)); +} + +#[test] +#[should_panic] +fn truncate_to_range_start_greater_than_end() { + let mut v: VecDeque<_> = (0..6).collect(); + #[allow(clippy::reversed_empty_ranges)] + v.truncate_to_range(4..2); +} + +#[test] +#[should_panic] +fn truncate_to_range_end_past_len() { + let mut v: VecDeque<_> = (0..6).collect(); + v.truncate_to_range(2..7); +} + +#[test] +#[should_panic] +fn truncate_to_range_start_past_len() { + let mut v: VecDeque<_> = (0..6).collect(); + v.truncate_to_range(7..8); +} + +#[test] +#[should_panic] +fn truncate_to_range_inclusive_end_overflow() { + let mut v: VecDeque<_> = (0..6).collect(); + v.truncate_to_range(0..=usize::MAX); +} diff --git a/library/backtrace b/library/backtrace index 28ec93b503bf0..d902726a1dcdc 160000 --- a/library/backtrace +++ b/library/backtrace @@ -1 +1 @@ -Subproject commit 28ec93b503bf0410745bc3d571bf3dc1caac3019 +Subproject commit d902726a1dcdc1e1c66f73d1162181b5423c645b diff --git a/library/compiler-builtins/.editorconfig b/library/compiler-builtins/.editorconfig index f0735cedfbd6b..23a4d23f28200 100644 --- a/library/compiler-builtins/.editorconfig +++ b/library/compiler-builtins/.editorconfig @@ -1,5 +1,3 @@ -# EditorConfig helps developers define and maintain consistent -# coding styles between different editors and IDEs # editorconfig.org root = true @@ -12,5 +10,5 @@ insert_final_newline = true indent_style = space indent_size = 4 -[*.yml] +[*.{yaml,yml}] indent_size = 2 diff --git a/library/compiler-builtins/.github/renovate.json5 b/library/compiler-builtins/.github/renovate.json5 new file mode 100644 index 0000000000000..7d18fd573d6d8 --- /dev/null +++ b/library/compiler-builtins/.github/renovate.json5 @@ -0,0 +1,37 @@ +{ + $schema: "https://docs.renovatebot.com/renovate-schema.json", + extends: [ + "config:recommended", + ":maintainLockFilesMonthly", + "helpers:pinGitHubActionDigestsToSemver" + ], + packageRules: [ + { + matchCategories: [ + "rust" + ], + matchJsonata: [ + "isBreaking != true" + ], + // Disable non-breaking change updates because they + // are updated periodically with lockfile maintainance. + enabled: false, + }, + { + matchManagers: [ + "github-actions" + ], + // Every month + schedule: "* 0 1 * *", + groupName: "Github Actions", + } + ], + // Receive any update that fixes security vulnerabilities. + // We need this because we disabled "patch" updates for Rust. + // Note: You need to enable "Dependabot alerts" in "Code security" GitHub + // Settings to receive security updates. + // See https://docs.renovatebot.com/configuration-options/#vulnerabilityalerts + vulnerabilityAlerts: { + enabled: true, + }, +} diff --git a/library/compiler-builtins/.github/workflows/main.yaml b/library/compiler-builtins/.github/workflows/main.yaml index 699a9c417ddef..2ded0f6177d7b 100644 --- a/library/compiler-builtins/.github/workflows/main.yaml +++ b/library/compiler-builtins/.github/workflows/main.yaml @@ -1,4 +1,5 @@ name: CI +permissions: {} on: push: { branches: [main] } pull_request: @@ -10,16 +11,23 @@ concurrency: env: CARGO_TERM_COLOR: always + LIBM_BUILD_VERBOSE: true RUSTDOCFLAGS: -Dwarnings RUSTFLAGS: -Dwarnings RUST_BACKTRACE: full - BENCHMARK_RUSTC: nightly-2025-12-01 # Pin the toolchain for reproducable results + BENCHMARK_RUSTC: nightly-2026-08-05 # Pin the toolchain for reproducable results + +defaults: + run: + # Add `-ux` to the default template specified at + # https://docs.github.com/en/actions/reference/workflows-and-actions/workflow-syntax#defaultsrunshell + shell: bash --noprofile --norc -euxo pipefail {0} jobs: # Determine which tests should be run based on changed files. calculate_vars: name: Calculate workflow variables - runs-on: ubuntu-24.04 + runs-on: ubuntu-26.04 timeout-minutes: 10 env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} @@ -28,8 +36,9 @@ jobs: extensive_matrix: ${{ steps.script.outputs.extensive_matrix }} may_skip_libm_ci: ${{ steps.script.outputs.may_skip_libm_ci }} steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@3d3c42e5aac5ba805825da76410c181273ba90b1 # v7.0.1 with: + persist-credentials: false fetch-depth: 500 - name: Fetch pull request ref run: git fetch origin "$GITHUB_REF:$GITHUB_REF" @@ -42,213 +51,262 @@ jobs: test: name: Build and test timeout-minutes: 60 + # NOTE: self-hosted riscv64 runners are experimental and may be flaky. + # Do not block CI on failures from this platform for now. + continue-on-error: ${{ contains(matrix.os, 'self-hosted') }} strategy: fail-fast: false matrix: include: - target: aarch64-apple-darwin - os: macos-15 + os: macos-26 - target: aarch64-unknown-linux-gnu - os: ubuntu-24.04-arm + os: ubuntu-26.04-arm - target: aarch64-pc-windows-msvc - os: windows-11-arm + os: windows-11-vs2026-arm - target: arm-unknown-linux-gnueabi - os: ubuntu-24.04 + os: ubuntu-26.04 - target: arm-unknown-linux-gnueabihf - os: ubuntu-24.04 + os: ubuntu-26.04 - target: armv7-unknown-linux-gnueabihf - os: ubuntu-24.04 + os: ubuntu-26.04 - target: i586-unknown-linux-gnu - os: ubuntu-24.04 + os: ubuntu-26.04 - target: i686-unknown-linux-gnu - os: ubuntu-24.04 + os: ubuntu-26.04 - target: loongarch64-unknown-linux-gnu - os: ubuntu-24.04 + os: ubuntu-26.04 - target: powerpc-unknown-linux-gnu - os: ubuntu-24.04 + os: ubuntu-26.04 - target: powerpc64-unknown-linux-gnu - os: ubuntu-24.04 + os: ubuntu-26.04 + - target: powerpc64-unknown-linux-musl + os: ["self-hosted", "linux", "powerpc64", "musl"] - target: powerpc64le-unknown-linux-gnu - os: ubuntu-24.04 + os: ubuntu-26.04 - target: powerpc64le-unknown-linux-gnu os: ubuntu-24.04-ppc64le + # FIXME(ci): re-enable these once more capacity is avialable + # - target: riscv64gc-unknown-linux-gnu + # os: ["self-hosted", "linux", "riscv64"] - target: riscv64gc-unknown-linux-gnu - os: ubuntu-24.04 + os: ubuntu-26.04 - target: s390x-unknown-linux-gnu os: ubuntu-24.04-s390x - target: thumbv6m-none-eabi - os: ubuntu-24.04 + os: ubuntu-26.04 - target: thumbv7em-none-eabi - os: ubuntu-24.04 + os: ubuntu-26.04 - target: thumbv7em-none-eabihf - os: ubuntu-24.04 + os: ubuntu-26.04 - target: thumbv7m-none-eabi - os: ubuntu-24.04 + os: ubuntu-26.04 - target: wasm32-unknown-unknown - os: ubuntu-24.04 + os: ubuntu-26.04 - target: x86_64-unknown-linux-gnu - os: ubuntu-24.04 + os: ubuntu-26.04 - target: x86_64-apple-darwin - os: macos-15-intel + os: macos-26-intel - target: i686-pc-windows-msvc - os: windows-2025 + os: windows-2025-vs2026 - target: x86_64-pc-windows-msvc - os: windows-2025 + os: windows-2025-vs2026 - target: i686-pc-windows-gnu - os: windows-2025 + os: windows-2025-vs2026 channel: nightly-i686-gnu - target: x86_64-pc-windows-gnu - os: windows-2025 + os: windows-2025-vs2026 channel: nightly-x86_64-gnu runs-on: ${{ matrix.os }} needs: [calculate_vars] env: BUILD_ONLY: ${{ matrix.build_only }} + JOB_TARGET: ${{ matrix.target }} + JOB_CHANNEL: ${{ matrix.channel }} MAY_SKIP_LIBM_CI: ${{ needs.calculate_vars.outputs.may_skip_libm_ci }} + RUN_IN_DOCKER: ${{ matrix.os == 'ubuntu-26.04' }} steps: - - name: Print $HOME - shell: bash + - name: Print runner information run: | - set -x - echo "${HOME:-not found}" + uname -a + lscpu || (sysctl -a | grep cpu) || true + echo "home: ${HOME:-not found}" pwd - printenv - - name: Print runner information - run: uname -a # Native ppc and s390x runners don't have rustup by default - name: Install rustup - if: matrix.os == 'ubuntu-24.04-ppc64le' || matrix.os == 'ubuntu-24.04-s390x' + if: matrix.os == 'ubuntu-26.04-ppc64le' || matrix.os == 'ubuntu-26.04-s390x' run: sudo apt-get update && sudo apt-get install -y rustup - - uses: actions/checkout@v4 + - uses: actions/checkout@3d3c42e5aac5ba805825da76410c181273ba90b1 # v7.0.1 + with: { persist-credentials: false } - name: Install Rust (rustup) - shell: bash run: | channel="nightly" # Account for channels that have required components (MinGW) - [ -n "${{ matrix.channel }}" ] && channel="${{ matrix.channel }}" + [ -n "$JOB_CHANNEL" ] && channel="$JOB_CHANNEL" rustup update "$channel" --no-self-update rustup default "$channel" - rustup target add "${{ matrix.target }}" + rustup target add "$JOB_TARGET" - - uses: taiki-e/install-action@nextest + - uses: taiki-e/install-action@7f4eb899022d8fe70b20c4f3de697aa85c309026 # v2.85.11 + with: + tool: nextest@0.9.131 - - uses: Swatinem/rust-cache@v2 + - uses: Swatinem/rust-cache@6323deb102c322ba6fcbdcafc7e3dddab59af2b6 # v2.9.2 with: key: ${{ matrix.target }} - name: Cache Docker layers - uses: actions/cache@v4 - if: matrix.os == 'ubuntu-24.04' + uses: actions/cache@55cc8345863c7cc4c66a329aec7e433d2d1c52a9 # v6.1.0 + if: ${{ env.RUN_IN_DOCKER == 'true' }} with: path: /tmp/.buildx-cache key: ${{ matrix.target }}-buildx-${{ github.sha }} restore-keys: ${{ matrix.target }}-buildx- # Configure buildx to use Docker layer caching - - uses: docker/setup-buildx-action@v3 - if: matrix.os == 'ubuntu-24.04' + - uses: docker/setup-buildx-action@bb05f3f5519dd87d3ba754cc423b652a5edd6d2c # v4.2.0 + if: ${{ env.RUN_IN_DOCKER == 'true' }} - name: Cache compiler-rt id: cache-compiler-rt - uses: actions/cache@v4 + uses: actions/cache@55cc8345863c7cc4c66a329aec7e433d2d1c52a9 # v6.1.0 with: path: compiler-rt - key: ${{ runner.os }}-compiler-rt-${{ hashFiles('ci/download-compiler-rt.sh') }} + key: ${{ runner.os }}-compiler-rt-${{ hashFiles('ci/download-compiler-rt.sh', 'ci/compiler-rt-patches') }} - name: Download compiler-rt reference sources if: steps.cache-compiler-rt.outputs.cache-hit != 'true' run: ./ci/download-compiler-rt.sh - shell: bash - run: echo "RUST_COMPILER_RT_ROOT=$(realpath ./compiler-rt)" >> "$GITHUB_ENV" - shell: bash - name: Download musl source run: ./ci/update-musl.sh - shell: bash - name: Verify API list - if: matrix.os == 'ubuntu-24.04' - run: python3 etc/update-api-list.py --check + if: matrix.os == 'ubuntu-26.04' || contains(matrix.os, 'self-hosted') + run: | + # Must be run on the host (not in Docker) because git and fs access is required. + python3 etc/update-api-list.py --check + cargo test -p update-api-list # Non-linux tests just use our raw script - name: Run locally - if: matrix.os != 'ubuntu-24.04' - shell: bash - run: ./ci/run.sh ${{ matrix.target }} + if: ${{ env.RUN_IN_DOCKER != 'true' }} + run: ./ci/run.sh "$JOB_TARGET" # Otherwise we use our docker containers to run builds - name: Run in Docker - if: matrix.os == 'ubuntu-24.04' - run: ./ci/run-docker.sh ${{ matrix.target }} + if: ${{ env.RUN_IN_DOCKER == 'true' }} + run: ./ci/run-docker.sh "$JOB_TARGET" - name: Print test logs if available if: always() run: if [ -f "target/test-log.txt" ]; then cat target/test-log.txt; fi - shell: bash # Workaround to keep Docker cache smaller # https://github.com/docker/build-push-action/issues/252 # https://github.com/moby/buildkit/issues/1896 - name: Move Docker cache - if: matrix.os == 'ubuntu-24.04' + if: ${{ env.RUN_IN_DOCKER == 'true' }} run: | rm -rf /tmp/.buildx-cache mv /tmp/.buildx-cache-new /tmp/.buildx-cache clippy: name: Clippy - runs-on: ubuntu-24.04 + runs-on: ubuntu-26.04 timeout-minutes: 10 steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@3d3c42e5aac5ba805825da76410c181273ba90b1 # v7.0.1 + with: { persist-credentials: false } # Unlike rustfmt, stable clippy does not work on code with nightly features. - name: Install nightly `clippy` run: | rustup update nightly --no-self-update rustup default nightly rustup component add clippy - - uses: Swatinem/rust-cache@v2 + - uses: Swatinem/rust-cache@6323deb102c322ba6fcbdcafc7e3dddab59af2b6 # v2.9.2 - name: Download musl source run: ./ci/update-musl.sh - run: cargo clippy --workspace --all-targets + zizmor: + name: Zizmor (Static analysis for GitHub Actions) + runs-on: ubuntu-26.04 + permissions: + security-events: write + timeout-minutes: 10 + steps: + - uses: actions/checkout@3d3c42e5aac5ba805825da76410c181273ba90b1 # v7.0.1 + with: { persist-credentials: false } + - uses: zizmorcore/zizmor-action@3dc1ecc9bcb9e94e9b2c709687979e1298497054 # v0.6.2 + build-custom: name: Build custom target - runs-on: ubuntu-24.04 + runs-on: ubuntu-26.04 timeout-minutes: 10 steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@3d3c42e5aac5ba805825da76410c181273ba90b1 # v7.0.1 + with: { persist-credentials: false } - name: Install Rust run: | rustup update nightly --no-self-update rustup default nightly rustup component add rust-src - - uses: Swatinem/rust-cache@v2 + - uses: Swatinem/rust-cache@6323deb102c322ba6fcbdcafc7e3dddab59af2b6 # v2.9.2 - run: | # Ensure we can build with custom target.json files (these can interact # poorly with build scripts) cargo build -p compiler_builtins -p libm \ --target etc/thumbv7em-none-eabi-renamed.json \ - -Zbuild-std=core + -Zbuild-std=core \ + -Zjson-target-spec + + # FIXME: move this target to test job once https://github.com/rust-lang/rust/pull/150138 merged. + build-thumbv6k: + name: Build thumbv6k + runs-on: ubuntu-26.04 + timeout-minutes: 10 + steps: + - uses: actions/checkout@3d3c42e5aac5ba805825da76410c181273ba90b1 # v7.0.1 + with: { persist-credentials: false } + - name: Install Rust + run: | + rustup update nightly --no-self-update + rustup default nightly + rustup component add rust-src + - uses: Swatinem/rust-cache@6323deb102c322ba6fcbdcafc7e3dddab59af2b6 # v2.9.2 + - run: | + cargo build -p compiler_builtins -p libm \ + --target etc/thumbv6-none-eabi.json \ + -Zbuild-std=core \ + -Zjson-target-spec benchmarks: name: Benchmarks - timeout-minutes: 20 + timeout-minutes: 30 strategy: fail-fast: false matrix: include: - - target: x86_64-unknown-linux-gnu - os: ubuntu-24.04 - target: aarch64-unknown-linux-gnu - os: ubuntu-24.04-arm + os: ubuntu-26.04-arm + - target: i686-unknown-linux-gnu + os: ubuntu-26.04 + - target: x86_64-unknown-linux-gnu + os: ubuntu-26.04 runs-on: ${{ matrix.os }} + env: + JOB_TARGET: ${{ matrix.target }} steps: - - uses: actions/checkout@master - - uses: taiki-e/install-action@cargo-binstall + - uses: actions/checkout@3d3c42e5aac5ba805825da76410c181273ba90b1 # v7.0.1 + with: { persist-credentials: false } + - uses: taiki-e/install-action@7f4eb899022d8fe70b20c4f3de697aa85c309026 # v2.85.11 + with: + tool: cargo-binstall@1.17.7 - name: Set up dependencies - run: ./ci/install-bench-deps.sh - - uses: Swatinem/rust-cache@v2 + run: ./ci/install-bench-deps.sh "$JOB_TARGET" + - uses: Swatinem/rust-cache@6323deb102c322ba6fcbdcafc7e3dddab59af2b6 # v2.9.2 with: key: ${{ matrix.target }} - name: Download musl source @@ -258,50 +316,47 @@ jobs: env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} PR_NUMBER: ${{ github.event.pull_request.number }} - run: ./ci/bench-icount.sh ${{ matrix.target }} + run: ./ci/bench-icount.sh "$JOB_TARGET" - name: Upload the benchmark baseline - uses: actions/upload-artifact@v4 + uses: actions/upload-artifact@043fb46d1a93c77aae656e7c1c64a875d1fc6a0a # v7.0.1 with: name: ${{ env.BASELINE_NAME }} path: ${{ env.BASELINE_NAME }}.tar.xz - - name: Run wall time benchmarks - run: ./ci/bench-runtime.sh - - name: Print test logs if available if: always() run: if [ -f "target/test-log.txt" ]; then cat target/test-log.txt; fi - shell: bash miri: name: Miri - runs-on: ubuntu-24.04 + runs-on: ubuntu-26.04 timeout-minutes: 10 steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@3d3c42e5aac5ba805825da76410c181273ba90b1 # v7.0.1 + with: { persist-credentials: false } - name: Install Rust (rustup) run: rustup update nightly --no-self-update && rustup default nightly - shell: bash - run: rustup component add miri - run: cargo miri setup - - uses: Swatinem/rust-cache@v2 + - uses: Swatinem/rust-cache@6323deb102c322ba6fcbdcafc7e3dddab59af2b6 # v2.9.2 - run: ./ci/miri.sh msrv: name: Check libm MSRV - runs-on: ubuntu-24.04 + runs-on: ubuntu-26.04 timeout-minutes: 10 env: RUSTFLAGS: # No need to check warnings on old MSRV, unset `-Dwarnings` steps: - - uses: actions/checkout@master + - uses: actions/checkout@3d3c42e5aac5ba805825da76410c181273ba90b1 # v7.0.1 + with: { persist-credentials: false } - name: Install Rust run: | msrv="$(perl -ne 'print if s/rust-version\s*=\s*"(.*)"/\1/g' libm/Cargo.toml)" echo "MSRV: $msrv" rustup update "$msrv" --no-self-update && rustup default "$msrv" - - uses: Swatinem/rust-cache@v2 + - uses: Swatinem/rust-cache@6323deb102c322ba6fcbdcafc7e3dddab59af2b6 # v2.9.2 - run: | # FIXME(msrv): Remove the workspace Cargo.toml so 1.63 cargo doesn't see # `edition = "2024"` and get spooked. @@ -310,10 +365,11 @@ jobs: rustfmt: name: Rustfmt - runs-on: ubuntu-24.04 + runs-on: ubuntu-26.04 timeout-minutes: 10 steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@3d3c42e5aac5ba805825da76410c181273ba90b1 # v7.0.1 + with: { persist-credentials: false } - name: Install nightly `rustfmt` run: rustup set profile minimal && rustup default nightly && rustup component add rustfmt - run: cargo fmt -- --check @@ -324,7 +380,7 @@ jobs: # Wait on `clippy` so we have some confidence that the crate will build - clippy - calculate_vars - runs-on: ubuntu-24.04 + runs-on: ubuntu-26.04 timeout-minutes: 240 # 4 hours strategy: matrix: @@ -336,37 +392,41 @@ jobs: env: TO_TEST: ${{ matrix.to_test }} steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@3d3c42e5aac5ba805825da76410c181273ba90b1 # v7.0.1 + with: { persist-credentials: false } - name: Install Rust run: | rustup update nightly --no-self-update rustup default nightly - - uses: Swatinem/rust-cache@v2 + - uses: Swatinem/rust-cache@6323deb102c322ba6fcbdcafc7e3dddab59af2b6 # v2.9.2 - name: download musl source run: ./ci/update-musl.sh - name: Run extensive tests run: ./ci/run-extensive.sh - name: Print test logs if available run: if [ -f "target/test-log.txt" ]; then cat target/test-log.txt; fi - shell: bash success: needs: - benchmarks - build-custom + - build-thumbv6k - clippy - extensive - miri - msrv - rustfmt - test - runs-on: ubuntu-24.04 + - zizmor + runs-on: ubuntu-26.04 timeout-minutes: 10 # GitHub branch protection is exceedingly silly and treats "jobs skipped because a dependency # failed" as success. So we have to do some contortions to ensure the job fails if any of its # dependencies fails. if: always() # make sure this is never "skipped" + env: + NEEDS: ${{ toJson(needs) }} steps: # Manually check the status of all dependencies. `if: failure()` does not work. - name: check if any dependency failed - run: jq --exit-status 'all(.result == "success")' <<< '${{ toJson(needs) }}' + run: jq --exit-status 'all(.result == "success")' <<< "$NEEDS" diff --git a/library/compiler-builtins/.github/workflows/publish.yaml b/library/compiler-builtins/.github/workflows/publish.yaml index d6f1dc398e8ec..02ddf0babdf40 100644 --- a/library/compiler-builtins/.github/workflows/publish.yaml +++ b/library/compiler-builtins/.github/workflows/publish.yaml @@ -11,15 +11,15 @@ jobs: release-plz: name: Release-plz runs-on: ubuntu-24.04 + environment: publish steps: - - name: Checkout repository - uses: actions/checkout@v4 + - uses: actions/checkout@3d3c42e5aac5ba805825da76410c181273ba90b1 # v7.0.1 with: + persist-credentials: false fetch-depth: 0 - name: Install Rust (rustup) run: rustup update nightly --no-self-update && rustup default nightly - name: Run release-plz - uses: MarcoIeni/release-plz-action@v0.5 + uses: release-plz/action@2eb1d8bcb770b4c48ccfaad919734b38b51958c9 # v0.5 env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} - CARGO_REGISTRY_TOKEN: ${{ secrets.CARGO_REGISTRY_TOKEN }} diff --git a/library/compiler-builtins/.github/workflows/rustc-pull.yml b/library/compiler-builtins/.github/workflows/rustc-pull.yml index 617db14f46eea..34e78e445677c 100644 --- a/library/compiler-builtins/.github/workflows/rustc-pull.yml +++ b/library/compiler-builtins/.github/workflows/rustc-pull.yml @@ -5,20 +5,27 @@ on: workflow_dispatch: schedule: # Run at 04:00 UTC every Monday and Thursday - - cron: '0 4 * * 1,4' + - cron: "0 4 * * 1,4" + +env: + JOSH_SYNC_VERBOSE: true jobs: pull: if: github.repository == 'rust-lang/compiler-builtins' - uses: rust-lang/josh-sync/.github/workflows/rustc-pull.yml@main + uses: rust-lang/josh-sync/.github/workflows/rustc-pull.yml@00d007cf377c524bc2968b40a61ef1d2ce20e283 # main with: github-app-id: ${{ vars.APP_CLIENT_ID }} + pr-author: "workflows-compiler-builtins[bot]" # https://rust-lang.zulipchat.com/#narrow/channel/219381-t-libs/topic/compiler-builtins.20subtree.20sync.20automation/with/528482375 zulip-stream-id: 219381 - zulip-topic: 'compiler-builtins subtree sync automation' + zulip-topic: "compiler-builtins subtree sync automation" zulip-bot-email: "compiler-builtins-ci-bot@rust-lang.zulipchat.com" pr-base-branch: main branch-name: rustc-pull secrets: zulip-api-token: ${{ secrets.ZULIP_API_TOKEN }} github-app-secret: ${{ secrets.APP_PRIVATE_KEY }} + permissions: + contents: write + pull-requests: write diff --git a/library/compiler-builtins/.gitignore b/library/compiler-builtins/.gitignore index abe346659d4c7..ec7130db73802 100644 --- a/library/compiler-builtins/.gitignore +++ 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enabled, which is the opposite of what is needed for # other tests, so it makes sense to keep it out of the workspace. "builtins-test-intrinsics", # We test via the `builtins-shim` crate, so exclude the `compiler-builtins` @@ -31,6 +34,43 @@ exclude = [ "compiler-builtins", ] +[workspace.dependencies] +anyhow = "1.0.101" +api-list-common = { path = "crates/api-list-common" } +assert_cmd = "2.1.2" +cc = "1.2.56" +compiler_builtins = { path = "builtins-shim", default-features = false } +criterion = { version = "0.8.2", default-features = false, features = ["cargo_bench_support"] } +getopts = "0.2.24" +getrandom = "0.4.1" +glob = "0.3.3" +gmp-mpfr-sys = { version = "1.6.8", default-features = false } +gungraun = "0.19.0" +heck = "0.5.0" +indicatif = { version = "0.18.3", default-features = false } +libm = { path = "libm", default-features = false } +libm-macros = { path = "crates/libm-macros" } +libm-test = { path = "libm-test", default-features = false } +libtest-mimic = "0.8.1" +musl-math-sys = { path = "crates/musl-math-sys" } +no-panic = "0.1.36" +object = { version = "0.40.0", features = ["wasm"] } +panic-handler = { path = "crates/panic-handler" } +paste = "1.0.15" +pretty_assertions = "1.4.1" +proc-macro2 = "1.0.106" +quote = "1.0.44" +rand = "0.10.0" +rand_chacha = "0.10.0" +rand_xoshiro = "0.8" +rayon = "1.11.0" +regex = "1.12.3" +rug = { version = "1.28.1", default-features = false, features = ["float", "integer", "std"] } +rustc_apfloat = "0.2.3" +serde_json = "1.0.149" +syn = "3.0.3" +tempfile = "3.25.0" + [profile.release] panic = "abort" @@ -51,6 +91,7 @@ codegen-units = 1 lto = "fat" [profile.bench] +codegen-units = 1 # Required for gungraun debug = true strip = false diff --git a/library/compiler-builtins/builtins-shim/Cargo.toml b/library/compiler-builtins/builtins-shim/Cargo.toml index 746d5b21dc3f1..c940723a1ba5f 100644 --- a/library/compiler-builtins/builtins-shim/Cargo.toml +++ b/library/compiler-builtins/builtins-shim/Cargo.toml @@ -7,6 +7,9 @@ # manifest that is identical except for the `core` dependency and forwards # to the same sources, which acts as the `compiler-builtins` Cargo entrypoint # for out of tree testing +# +# Ideally we can eventually replace this with a patch in the workspace +# manifest . [package] name = "compiler_builtins" @@ -33,32 +36,31 @@ doctest = false test = false [build-dependencies] -cc = { optional = true, version = "1.2" } +cc = { version = "1.2", optional = true } [features] -default = ["compiler-builtins"] +default = ["arch"] + +# Enable architecture-specific features such as SIMD or assembly routines. If +# disabled, the generic version can be tested on any platform. +arch = [] # Enable compilation of C code in compiler-rt, filling in some more optimized # implementations and also filling in unimplemented intrinsics c = ["dep:cc"] -# For implementations where there is both a generic version and a platform- -# specific version, use the generic version. This is meant to enable testing -# the generic versions on all platforms. -no-asm = [] +# Flag this library as the unstable compiler-builtins lib. This must be enabled +# when using as `std`'s dependency.' +compiler-builtins = ["unmangled-names"] -# Flag this library as the unstable compiler-builtins lib -compiler-builtins = [] - -# Generate memory-related intrinsics like memcpy +# Enable `no_mangle` symbols for memory-related intrinsics like memcpy. The +# mangled versions are always available. mem = [] -# Mangle all names so this can be linked in with other versions or other -# compiler-rt implementations. Also used for testing -mangled-names = [] - -# Only used in the compiler's build system -rustc-dep-of-std = ["compiler-builtins"] +# Enable `no_mangle` symbols so this crate gets used as the runtime intrinsic +# implementation. Leave this disabled for testing to avoid conflicting with +# the system intrinsics. +unmangled-names = [] # This makes certain traits and function specializations public that # are not normally public but are required by the `builtins-test` diff --git a/library/compiler-builtins/builtins-test-intrinsics/Cargo.lock b/library/compiler-builtins/builtins-test-intrinsics/Cargo.lock new file mode 100644 index 0000000000000..5f3754a2de305 --- /dev/null +++ b/library/compiler-builtins/builtins-test-intrinsics/Cargo.lock @@ -0,0 +1,71 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. +version = 4 + +[[package]] +name = "builtins-test-intrinsics" +version = "0.1.0" +dependencies = [ + "compiler_builtins", + "panic-handler", + "test", + "utest-cortex-m-qemu", + "utest-macros", +] + +[[package]] +name = "cc" +version = "1.4.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5d262e149917187838d5b42777c8253bcb64500067342904e7d429499a6f277e" +dependencies = [ + "find-msvc-tools", + "shlex", +] + +[[package]] +name = "compiler_builtins" +version = "0.1.160" +dependencies = [ + "cc", +] + +[[package]] +name = "find-msvc-tools" +version = "0.1.10" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "26b73573e6edcd2af0cdf47bd6cb58f0b3839491263c314eaad1ccf24430e1de" + +[[package]] +name = "panic-handler" +version = "0.1.0" + +[[package]] +name = "sc" +version = "0.2.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "010e18bd3bfd1d45a7e666b236c78720df0d9a7698ebaa9c1c559961eb60a38b" + +[[package]] +name = "shlex" +version = "2.0.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f8fadd59c855ef2080decdef8ff161eb6661b86933c9d82e5ba29dc602a55aba" + +[[package]] +name = "test" +version = "0.1.0" +source = "git+https://github.com/japaric/utest#e32073e2b078e3bee46001c13ae4c1acf368d762" + +[[package]] +name = "utest-cortex-m-qemu" +version = "0.1.0" +source = "git+https://github.com/japaric/utest#e32073e2b078e3bee46001c13ae4c1acf368d762" +dependencies = [ + "sc", +] + +[[package]] +name = "utest-macros" +version = "0.1.0" +source = "git+https://github.com/japaric/utest#e32073e2b078e3bee46001c13ae4c1acf368d762" diff --git a/library/compiler-builtins/builtins-test-intrinsics/Cargo.toml b/library/compiler-builtins/builtins-test-intrinsics/Cargo.toml index e73a1f7b17e5b..fed2ac39fb321 100644 --- a/library/compiler-builtins/builtins-test-intrinsics/Cargo.toml +++ b/library/compiler-builtins/builtins-test-intrinsics/Cargo.toml @@ -6,9 +6,15 @@ publish = false license = "MIT OR Apache-2.0" [dependencies] -compiler_builtins = { path = "../builtins-shim", features = ["compiler-builtins"] } +# FIXME: `aeabi_mem*` tests will require the "mem" feature to be enabled here. +compiler_builtins = { path = "../builtins-shim", features = ["compiler-builtins", "unmangled-names"] } panic-handler = { path = "../crates/panic-handler" } +[target.'cfg(all(target_arch = "arm", not(any(target_env = "gnu", target_env = "musl")), target_os = "linux"))'.dev-dependencies] +test = { git = "https://github.com/japaric/utest" } +utest-cortex-m-qemu = { default-features = false, git = "https://github.com/japaric/utest" } +utest-macros = { git = "https://github.com/japaric/utest" } + [features] c = ["compiler_builtins/c"] diff --git a/library/compiler-builtins/builtins-test-intrinsics/build.rs b/library/compiler-builtins/builtins-test-intrinsics/build.rs index b82581262f7b0..c1ab650a6e82a 100644 --- a/library/compiler-builtins/builtins-test-intrinsics/build.rs +++ b/library/compiler-builtins/builtins-test-intrinsics/build.rs @@ -1,10 +1,10 @@ -mod builtins_configure { - include!("../compiler-builtins/configure.rs"); -} +#[path = "../libm/configure.rs"] +mod configure; -fn main() { - println!("cargo::rerun-if-changed=../configure.rs"); +use configure::{Config, Library}; - let target = builtins_configure::Target::from_env(); - builtins_configure::configure_aliases(&target); +fn main() { + println!("cargo::rerun-if-changed=../libm/configure.rs"); + let cfg = Config::from_env(Library::BuiltinsTestIntrinsics); + configure::emit(&cfg); } diff --git a/library/compiler-builtins/builtins-test-intrinsics/src/main.rs b/library/compiler-builtins/builtins-test-intrinsics/src/main.rs index b9d19ea77256e..e390590946f4c 100644 --- a/library/compiler-builtins/builtins-test-intrinsics/src/main.rs +++ b/library/compiler-builtins/builtins-test-intrinsics/src/main.rs @@ -1,12 +1,12 @@ -// By compiling this file we check that all the intrinsics we care about continue to be provided by -// the `compiler_builtins` crate regardless of the changes we make to it. If we, by mistake, stop -// compiling a C implementation and forget to implement that intrinsic in Rust, this file will fail -// to link due to the missing intrinsic (symbol). - -#![allow(unused_features)] -#![allow(internal_features)] +//! Tests that require unmangled symbols from `compiler-builtins`. +//! +//! By compiling this file we check that all the intrinsics we care about continue to be provided by +//! the `compiler_builtins` crate regardless of the changes we make to it. If we, by mistake, stop +//! compiling a C implementation and forget to implement that intrinsic in Rust, this file will fail +//! to link due to the missing intrinsic (symbol). + +#![allow(internal_features, unused_features)] #![deny(dead_code)] -#![feature(allocator_api)] #![feature(f128)] #![feature(f16)] #![feature(lang_items)] diff --git a/library/compiler-builtins/builtins-test/tests/aeabi_memclr.rs b/library/compiler-builtins/builtins-test-intrinsics/tests/aeabi_memclr.rs similarity index 98% rename from library/compiler-builtins/builtins-test/tests/aeabi_memclr.rs rename to library/compiler-builtins/builtins-test-intrinsics/tests/aeabi_memclr.rs index 0761feaffd9e2..df0e6a6d52997 100644 --- a/library/compiler-builtins/builtins-test/tests/aeabi_memclr.rs +++ b/library/compiler-builtins/builtins-test-intrinsics/tests/aeabi_memclr.rs @@ -2,7 +2,6 @@ target_arch = "arm", not(any(target_env = "gnu", target_env = "musl")), target_os = "linux", - feature = "mem" ))] #![feature(compiler_builtins_lib)] #![no_std] diff --git a/library/compiler-builtins/builtins-test/tests/aeabi_memcpy.rs b/library/compiler-builtins/builtins-test-intrinsics/tests/aeabi_memcpy.rs similarity index 98% rename from library/compiler-builtins/builtins-test/tests/aeabi_memcpy.rs rename to library/compiler-builtins/builtins-test-intrinsics/tests/aeabi_memcpy.rs index e76e712a246f1..acd12eef64ba5 100644 --- a/library/compiler-builtins/builtins-test/tests/aeabi_memcpy.rs +++ b/library/compiler-builtins/builtins-test-intrinsics/tests/aeabi_memcpy.rs @@ -2,7 +2,6 @@ target_arch = "arm", not(any(target_env = "gnu", target_env = "musl")), target_os = "linux", - feature = "mem" ))] #![feature(compiler_builtins_lib)] #![no_std] diff --git a/library/compiler-builtins/builtins-test/tests/aeabi_memset.rs b/library/compiler-builtins/builtins-test-intrinsics/tests/aeabi_memset.rs similarity index 99% rename from library/compiler-builtins/builtins-test/tests/aeabi_memset.rs rename to library/compiler-builtins/builtins-test-intrinsics/tests/aeabi_memset.rs index 8f9f80f969ccb..98d2c6852d14f 100644 --- a/library/compiler-builtins/builtins-test/tests/aeabi_memset.rs +++ b/library/compiler-builtins/builtins-test-intrinsics/tests/aeabi_memset.rs @@ -2,7 +2,6 @@ target_arch = "arm", not(any(target_env = "gnu", target_env = "musl")), target_os = "linux", - feature = "mem" ))] #![feature(compiler_builtins_lib)] #![no_std] diff --git a/library/compiler-builtins/builtins-test/Cargo.toml b/library/compiler-builtins/builtins-test/Cargo.toml index 550f736a76dbb..f1a5be415675d 100644 --- a/library/compiler-builtins/builtins-test/Cargo.toml +++ b/library/compiler-builtins/builtins-test/Cargo.toml @@ -6,90 +6,81 @@ publish = false license = "MIT AND Apache-2.0 WITH LLVM-exception AND (MIT OR Apache-2.0)" [dependencies] +compiler_builtins = { workspace = true, default-features = false, features = ["unstable-public-internals"] } + # For fuzzing tests we want a deterministic seedable RNG. We also eliminate potential # problems with system RNGs on the variety of platforms this crate is tested on. # `xoshiro128**` is used for its quality, size, and speed at generating `u32` shift amounts. -rand_xoshiro = "0.7" +rand_xoshiro.workspace = true + # To compare float builtins against -rustc_apfloat = "0.2.3" -# Really a dev dependency, but dev dependencies can't be optional -gungraun = { version = "0.17.0", optional = true } +rustc_apfloat.workspace = true -[dependencies.compiler_builtins] -path = "../builtins-shim" -default-features = false -features = ["unstable-public-internals"] +# Really dev dependencies, but those can't be optional +criterion = { workspace = true, optional = true } +gungraun = { workspace = true, optional = true } [dev-dependencies] -criterion = { version = "0.6.0", default-features = false, features = ["cargo_bench_support"] } -paste = "1.0.15" - -[target.'cfg(all(target_arch = "arm", not(any(target_env = "gnu", target_env = "musl")), target_os = "linux"))'.dev-dependencies] -test = { git = "https://github.com/japaric/utest" } -utest-cortex-m-qemu = { default-features = false, git = "https://github.com/japaric/utest" } -utest-macros = { git = "https://github.com/japaric/utest" } +paste.workspace = true [features] -default = ["mangled-names"] +# Defaults should match the defaults in compiler-builtins since we have that +# dependency with `default-features=false`. +default = ["compiler_builtins/arch"] c = ["compiler_builtins/c"] -no-asm = ["compiler_builtins/no-asm"] -mem = ["compiler_builtins/mem"] -mangled-names = ["compiler_builtins/mangled-names"] -# Skip tests that rely on f128 symbols being available on the system -no-sys-f128 = ["no-sys-f128-int-convert", "no-sys-f16-f128-convert"] -# Some platforms have some f128 functions but everything except integer conversions -no-sys-f128-int-convert = [] -no-sys-f16-f128-convert = [] -no-sys-f16-f64-convert = [] -# Skip tests that rely on f16 symbols being available on the system -no-sys-f16 = ["no-sys-f16-f64-convert"] # Enable icount benchmarks (requires gungraun-runner and valgrind locally) icount = ["dep:gungraun"] -# Enable report generation without bringing in more dependencies by default -benchmarking-reports = ["criterion/plotters", "criterion/html_reports"] - -# NOTE: benchmarks must be run with `--no-default-features` or with -# `-p builtins-test`, otherwise the default `compiler-builtins` feature -# of the `compiler_builtins` crate gets activated, resulting in linker -# errors. +# Config for wall time benchmarks. Plotters and html_reports bring in extra +# deps so are off by default for CI. +benchmarking-reports = ["walltime", "criterion/plotters", "criterion/html_reports"] +walltime = ["dep:criterion"] [[bench]] name = "float_add" harness = false +required-features = ["walltime"] [[bench]] name = "float_sub" harness = false +required-features = ["walltime"] [[bench]] name = "float_mul" harness = false +required-features = ["walltime"] [[bench]] name = "float_div" harness = false +required-features = ["walltime"] [[bench]] name = "float_cmp" harness = false +required-features = ["walltime"] [[bench]] name = "float_conv" harness = false +required-features = ["walltime"] [[bench]] name = "float_extend" harness = false +required-features = ["walltime"] [[bench]] name = "float_trunc" harness = false +required-features = ["walltime"] [[bench]] name = "float_pow" harness = false +required-features = ["walltime"] [[bench]] name = "mem_icount" diff --git a/library/compiler-builtins/builtins-test/benches/float_add.rs b/library/compiler-builtins/builtins-test/benches/float_add.rs index 197f90b319da4..2c1d2d9f15520 100644 --- a/library/compiler-builtins/builtins-test/benches/float_add.rs +++ b/library/compiler-builtins/builtins-test/benches/float_add.rs @@ -74,7 +74,7 @@ float_bench! { crate_fn_ppc: add::__addkf3, sys_fn: __addtf3, sys_fn_ppc: __addkf3, - sys_available: not(feature = "no-sys-f128"), + sys_available: not(no_sys_f128), asm: [] } diff --git a/library/compiler-builtins/builtins-test/benches/float_cmp.rs b/library/compiler-builtins/builtins-test/benches/float_cmp.rs index da29b5d313263..cb13ce18fe4c6 100644 --- a/library/compiler-builtins/builtins-test/benches/float_cmp.rs +++ b/library/compiler-builtins/builtins-test/benches/float_cmp.rs @@ -185,7 +185,7 @@ float_bench! { crate_fn_ppc: cmp::__gtkf2, sys_fn: __gttf2, sys_fn_ppc: __gtkf2, - sys_available: not(feature = "no-sys-f128"), + sys_available: not(no_sys_f128), output_eq: gt_res_eq, asm: [] } @@ -198,7 +198,7 @@ float_bench! { crate_fn_ppc: cmp::__unordkf2, sys_fn: __unordtf2, sys_fn_ppc: __unordkf2, - sys_available: not(feature = "no-sys-f128"), + sys_available: not(no_sys_f128), asm: [] } diff --git a/library/compiler-builtins/builtins-test/benches/float_conv.rs b/library/compiler-builtins/builtins-test/benches/float_conv.rs index 40c13d270ac8e..35255645b2464 100644 --- a/library/compiler-builtins/builtins-test/benches/float_conv.rs +++ b/library/compiler-builtins/builtins-test/benches/float_conv.rs @@ -84,7 +84,7 @@ float_bench! { crate_fn_ppc: conv::__floatunsikf, sys_fn: __floatunsitf, sys_fn_ppc: __floatunsikf, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } @@ -138,7 +138,7 @@ float_bench! { crate_fn_ppc: conv::__floatundikf, sys_fn: __floatunditf, sys_fn_ppc: __floatundikf, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } @@ -168,7 +168,7 @@ float_bench! { crate_fn_ppc: conv::__floatuntikf, sys_fn: __floatuntitf, sys_fn_ppc: __floatuntikf, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } @@ -249,7 +249,7 @@ float_bench! { crate_fn_ppc: conv::__floatsikf, sys_fn: __floatsitf, sys_fn_ppc: __floatsikf, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } @@ -328,7 +328,7 @@ float_bench! { crate_fn_ppc: conv::__floatdikf, sys_fn: __floatditf, sys_fn_ppc: __floatdikf, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } @@ -358,7 +358,7 @@ float_bench! { crate_fn_ppc: conv::__floattikf, sys_fn: __floattitf, sys_fn_ppc: __floattikf, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } @@ -473,7 +473,7 @@ float_bench! { crate_fn: conv::__fixunstfsi, crate_fn_ppc: conv::__fixunskfsi, sys_fn: __fixunstfsi, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } @@ -484,7 +484,7 @@ float_bench! { crate_fn: conv::__fixunstfdi, crate_fn_ppc: conv::__fixunskfdi, sys_fn: __fixunstfdi, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } @@ -495,7 +495,7 @@ float_bench! { crate_fn: conv::__fixunstfti, crate_fn_ppc: conv::__fixunskfti, sys_fn: __fixunstfti, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } @@ -610,7 +610,7 @@ float_bench! { crate_fn: conv::__fixtfsi, crate_fn_ppc: conv::__fixkfsi, sys_fn: __fixtfsi, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } @@ -621,7 +621,7 @@ float_bench! { crate_fn: conv::__fixtfdi, crate_fn_ppc: conv::__fixkfdi, sys_fn: __fixtfdi, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } @@ -632,7 +632,7 @@ float_bench! { crate_fn: conv::__fixtfti, crate_fn_ppc: conv::__fixkfti, sys_fn: __fixtfti, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } diff --git a/library/compiler-builtins/builtins-test/benches/float_div.rs b/library/compiler-builtins/builtins-test/benches/float_div.rs index d5b0ad0fd402b..dd2b2c1f940e2 100644 --- a/library/compiler-builtins/builtins-test/benches/float_div.rs +++ b/library/compiler-builtins/builtins-test/benches/float_div.rs @@ -74,7 +74,7 @@ float_bench! { crate_fn_ppc: div::__divkf3, sys_fn: __divtf3, sys_fn_ppc: __divkf3, - sys_available: not(feature = "no-sys-f128"), + sys_available: not(no_sys_f128), asm: [] } diff --git a/library/compiler-builtins/builtins-test/benches/float_extend.rs b/library/compiler-builtins/builtins-test/benches/float_extend.rs index 939dc60f95f4a..7896d10c8d1aa 100644 --- a/library/compiler-builtins/builtins-test/benches/float_extend.rs +++ b/library/compiler-builtins/builtins-test/benches/float_extend.rs @@ -12,7 +12,7 @@ float_bench! { sig: (a: f16) -> f32, crate_fn: extend::__extendhfsf2, sys_fn: __extendhfsf2, - sys_available: not(feature = "no-sys-f16"), + sys_available: not(no_sys_f16), asm: [ #[cfg(target_arch = "aarch64")] { let ret: f32; @@ -34,7 +34,7 @@ float_bench! { sig: (a: f16) -> f64, crate_fn: extend::__extendhfdf2, sys_fn: __extendhfdf2, - sys_available: not(feature = "no-sys-f16-f64-convert"), + sys_available: not(no_sys_f16_f64_convert), asm: [ #[cfg(target_arch = "aarch64")] { let ret: f64; @@ -58,7 +58,7 @@ float_bench! { crate_fn_ppc: extend::__extendhfkf2, sys_fn: __extendhftf2, sys_fn_ppc: __extendhfkf2, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [], } @@ -91,7 +91,7 @@ float_bench! { crate_fn_ppc: extend::__extendsfkf2, sys_fn: __extendsftf2, sys_fn_ppc: __extendsfkf2, - sys_available: not(feature = "no-sys-f128"), + sys_available: not(no_sys_f128), asm: [], } @@ -103,7 +103,7 @@ float_bench! { crate_fn_ppc: extend::__extenddfkf2, sys_fn: __extenddftf2, sys_fn_ppc: __extenddfkf2, - sys_available: not(feature = "no-sys-f128"), + sys_available: not(no_sys_f128), asm: [], } diff --git a/library/compiler-builtins/builtins-test/benches/float_mul.rs b/library/compiler-builtins/builtins-test/benches/float_mul.rs index a7a2d34aa0489..54fc6daa9b2a6 100644 --- a/library/compiler-builtins/builtins-test/benches/float_mul.rs +++ b/library/compiler-builtins/builtins-test/benches/float_mul.rs @@ -74,7 +74,7 @@ float_bench! { crate_fn_ppc: mul::__mulkf3, sys_fn: __multf3, sys_fn_ppc: __mulkf3, - sys_available: not(feature = "no-sys-f128"), + sys_available: not(no_sys_f128), asm: [] } diff --git a/library/compiler-builtins/builtins-test/benches/float_pow.rs b/library/compiler-builtins/builtins-test/benches/float_pow.rs index 64e37dd32416e..d749ae47ddafb 100644 --- a/library/compiler-builtins/builtins-test/benches/float_pow.rs +++ b/library/compiler-builtins/builtins-test/benches/float_pow.rs @@ -24,7 +24,7 @@ float_bench! { // FIXME(f16_f128): can be changed to only `f128_enabled` once `__multf3` and `__divtf3` are // distributed by nightly. -#[cfg(all(f128_enabled, not(feature = "no-sys-f128")))] +#[cfg(all(f128_enabled, not(no_sys_f128)))] float_bench! { name: powi_f128, sig: (a: f128, b: i32) -> f128, @@ -32,7 +32,7 @@ float_bench! { crate_fn_ppc: pow::__powikf2, sys_fn: __powitf2, sys_fn_ppc: __powikf2, - sys_available: not(feature = "no-sys-f128"), + sys_available: not(no_sys_f128), asm: [] } @@ -42,7 +42,7 @@ pub fn float_pow() { powi_f32(&mut criterion); powi_f64(&mut criterion); - #[cfg(all(f128_enabled, not(feature = "no-sys-f128")))] + #[cfg(all(f128_enabled, not(no_sys_f128)))] powi_f128(&mut criterion); } diff --git a/library/compiler-builtins/builtins-test/benches/float_sub.rs b/library/compiler-builtins/builtins-test/benches/float_sub.rs index 8bae294cd56b1..a8b73d7c7719e 100644 --- a/library/compiler-builtins/builtins-test/benches/float_sub.rs +++ b/library/compiler-builtins/builtins-test/benches/float_sub.rs @@ -74,7 +74,7 @@ float_bench! { crate_fn_ppc: sub::__subkf3, sys_fn: __subtf3, sys_fn_ppc: __subkf3, - sys_available: not(feature = "no-sys-f128"), + sys_available: not(no_sys_f128), asm: [] } diff --git a/library/compiler-builtins/builtins-test/benches/float_trunc.rs b/library/compiler-builtins/builtins-test/benches/float_trunc.rs index 9373f945bb2b8..fdf96fd3d34a4 100644 --- a/library/compiler-builtins/builtins-test/benches/float_trunc.rs +++ b/library/compiler-builtins/builtins-test/benches/float_trunc.rs @@ -11,7 +11,7 @@ float_bench! { sig: (a: f32) -> f16, crate_fn: trunc::__truncsfhf2, sys_fn: __truncsfhf2, - sys_available: not(feature = "no-sys-f16"), + sys_available: not(no_sys_f16), asm: [ #[cfg(target_arch = "aarch64")] { let ret: f16; @@ -33,7 +33,7 @@ float_bench! { sig: (a: f64) -> f16, crate_fn: trunc::__truncdfhf2, sys_fn: __truncdfhf2, - sys_available: not(feature = "no-sys-f16-f64-convert"), + sys_available: not(no_sys_f16_f64_convert), asm: [ #[cfg(target_arch = "aarch64")] { let ret: f16; @@ -90,7 +90,7 @@ float_bench! { crate_fn_ppc: trunc::__trunckfhf2, sys_fn: __trunctfhf2, sys_fn_ppc: __trunckfhf2, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [], } @@ -102,7 +102,7 @@ float_bench! { crate_fn_ppc: trunc::__trunckfsf2, sys_fn: __trunctfsf2, sys_fn_ppc: __trunckfsf2, - sys_available: not(feature = "no-sys-f128"), + sys_available: not(no_sys_f128), asm: [], } @@ -114,7 +114,7 @@ float_bench! { crate_fn_ppc: trunc::__trunckfdf2, sys_fn: __trunctfdf2, sys_fn_ppc: __trunckfdf2, - sys_available: not(feature = "no-sys-f128"), + sys_available: not(no_sys_f128), asm: [], } diff --git a/library/compiler-builtins/builtins-test/benches/mem_icount.rs b/library/compiler-builtins/builtins-test/benches/mem_icount.rs index 37595e8258436..7a3cad09b4044 100644 --- a/library/compiler-builtins/builtins-test/benches/mem_icount.rs +++ b/library/compiler-builtins/builtins-test/benches/mem_icount.rs @@ -118,7 +118,7 @@ mod mcpy { } } - library_benchmark_group!(name = memcpy; benchmarks = bench_cpy); + library_benchmark_group!(name = memcpy, benchmarks = [bench_cpy]); } mod mset { @@ -167,7 +167,7 @@ mod mset { } } - library_benchmark_group!(name = memset; benchmarks = bench_set); + library_benchmark_group!(name = memset, benchmarks = [bench_set]); } mod mcmp { @@ -235,7 +235,7 @@ mod mcmp { } } - library_benchmark_group!(name = memcmp; benchmarks = bench_cmp); + library_benchmark_group!(name = memcmp, benchmarks = [bench_cmp]); } mod mmove { @@ -489,7 +489,7 @@ mod mmove { } } - library_benchmark_group!(name = memmove; benchmarks = forward_move, backward_move); + library_benchmark_group!(name = memmove, benchmarks = [forward_move, backward_move]); } use mcmp::memcmp; @@ -497,4 +497,4 @@ use mcpy::memcpy; use mmove::memmove; use mset::memset; -main!(library_benchmark_groups = memcpy, memset, memcmp, memmove); +main!(library_benchmark_groups = [memcpy, memset, memcmp, memmove]); diff --git a/library/compiler-builtins/builtins-test/build.rs b/library/compiler-builtins/builtins-test/build.rs index 5b2dcd12ef86f..133186bc7f57d 100644 --- a/library/compiler-builtins/builtins-test/build.rs +++ b/library/compiler-builtins/builtins-test/build.rs @@ -1,12 +1,13 @@ +#[path = "../libm/configure.rs"] +mod configure; + use std::collections::HashSet; -mod builtins_configure { - include!("../compiler-builtins/configure.rs"); -} +use configure::{Config, Library, set_cfg}; /// Features to enable #[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)] -enum Feature { +enum SetCfg { NoSysF128, NoSysF128IntConvert, NoSysF16, @@ -14,7 +15,15 @@ enum Feature { NoSysF16F128Convert, } -impl Feature { +impl SetCfg { + const ALL: &[Self] = &[ + Self::NoSysF128, + Self::NoSysF128IntConvert, + Self::NoSysF16, + Self::NoSysF16F64Convert, + Self::NoSysF16F128Convert, + ]; + fn implies(self) -> &'static [Self] { match self { Self::NoSysF128 => [Self::NoSysF128IntConvert, Self::NoSysF16F128Convert].as_slice(), @@ -24,96 +33,89 @@ impl Feature { Self::NoSysF16F128Convert => [].as_slice(), } } + + fn name(self) -> &'static str { + match self { + Self::NoSysF128 => "no_sys_f128", + Self::NoSysF128IntConvert => "no_sys_f128_int_convert", + Self::NoSysF16F64Convert => "no_sys_f16_f64_convert", + Self::NoSysF16F128Convert => "no_sys_f16_f128_convert", + Self::NoSysF16 => "no_sys_f16", + } + } } fn main() { - println!("cargo::rerun-if-changed=../configure.rs"); + println!("cargo::rerun-if-changed=../libm/configure.rs"); - let target = builtins_configure::Target::from_env(); - let mut features = HashSet::new(); + let cfg = Config::from_env(Library::BuiltinsTest); + configure::emit(&cfg); + + let mut to_set = HashSet::new(); // These platforms do not have f128 symbols available in their system libraries, so // skip related tests. - if target.arch == "arm" - || target.vendor == "apple" - || target.env == "msvc" + if cfg.target_arch == "arm" + || cfg.target_vendor == "apple" + || cfg.target_env == "msvc" // GCC and LLVM disagree on the ABI of `f16` and `f128` with MinGW. See // . - || (target.os == "windows" && target.env == "gnu") + || (cfg.target_os == "windows" && cfg.target_env == "gnu") // FIXME(llvm): There is an ABI incompatibility between GCC and Clang on 32-bit x86. // See . - || target.arch == "x86" + || cfg.target_arch == "x86" // 32-bit PowerPC and 64-bit LE gets code generated that Qemu cannot handle. See // . - || target.arch == "powerpc" - || target.arch == "powerpc64le" + || cfg.target_arch == "powerpc" + || cfg.target_arch == "powerpc64le" // FIXME: We get different results from the builtin functions. See // . - || target.arch == "powerpc64" + || cfg.target_arch == "powerpc64" { - features.insert(Feature::NoSysF128); + to_set.insert(SetCfg::NoSysF128); } - if target.arch == "x86" { + if cfg.target_arch == "x86" { // 32-bit x86 does not have `__fixunstfti`/`__fixtfti` but does have everything else - features.insert(Feature::NoSysF128IntConvert); + to_set.insert(SetCfg::NoSysF128IntConvert); // FIXME: 32-bit x86 has a bug in `f128 -> f16` system libraries - features.insert(Feature::NoSysF16F128Convert); + to_set.insert(SetCfg::NoSysF16F128Convert); } // These platforms do not have f16 symbols available in their system libraries, so // skip related tests. Most of these are missing `f16 <-> f32` conversion routines. - if (target.arch == "aarch64" && target.os == "linux") - || target.arch.starts_with("arm") - || target.arch == "powerpc" - || target.arch == "powerpc64" - || target.arch == "powerpc64le" - || target.arch == "loongarch64" - || (target.arch == "x86" && !target.has_feature("sse")) - || target.os == "windows" + if (cfg.target_arch == "aarch64" && cfg.target_os == "linux") + || cfg.target_arch.starts_with("arm") + || cfg.target_arch == "powerpc" + || cfg.target_arch == "powerpc64" + || cfg.target_arch == "powerpc64le" + || cfg.target_arch == "loongarch64" + || (cfg.target_arch == "x86" && !cfg.has_target_feature("sse")) + || cfg.target_os == "windows" // Linking says "error: function signature mismatch: __extendhfsf2" and seems to // think the signature is either `(i32) -> f32` or `(f32) -> f32`. See // . - || target.arch == "wasm32" - || target.arch == "wasm64" + || cfg.target_arch == "wasm32" + || cfg.target_arch == "wasm64" { - features.insert(Feature::NoSysF16); + to_set.insert(SetCfg::NoSysF16); } // These platforms are missing either `__extendhfdf2` or `__truncdfhf2`. - if target.vendor == "apple" || target.os == "windows" { - features.insert(Feature::NoSysF16F64Convert); + if cfg.target_vendor == "apple" || cfg.target_os == "windows" { + to_set.insert(SetCfg::NoSysF16F64Convert); } // Add implied features. Collection is required for borrows. - features.extend( - features + to_set.extend( + to_set .iter() .flat_map(|x| x.implies()) .copied() .collect::>(), ); - for feature in features { - let (name, warning) = match feature { - Feature::NoSysF128 => ("no-sys-f128", "using apfloat fallback for f128"), - Feature::NoSysF128IntConvert => ( - "no-sys-f128-int-convert", - "using apfloat fallback for f128 <-> int conversions", - ), - Feature::NoSysF16F64Convert => ( - "no-sys-f16-f64-convert", - "using apfloat fallback for f16 <-> f64 conversions", - ), - Feature::NoSysF16F128Convert => ( - "no-sys-f16-f128-convert", - "using apfloat fallback for f16 <-> f128 conversions", - ), - Feature::NoSysF16 => ("no-sys-f16", "using apfloat fallback for f16"), - }; - println!("cargo:warning={warning}"); - println!("cargo:rustc-cfg=feature=\"{name}\""); + for cfg in SetCfg::ALL { + set_cfg(cfg.name(), to_set.contains(cfg)); } - - builtins_configure::configure_aliases(&target); } diff --git a/library/compiler-builtins/builtins-test/src/bench.rs b/library/compiler-builtins/builtins-test/src/bench.rs index 4bdcf482cd619..dd03579285cbc 100644 --- a/library/compiler-builtins/builtins-test/src/bench.rs +++ b/library/compiler-builtins/builtins-test/src/bench.rs @@ -1,7 +1,7 @@ use alloc::vec::Vec; use core::cell::RefCell; -use compiler_builtins::float::Float; +use compiler_builtins::support::Float; /// Fuzz with these many items to ensure equal functions pub const CHECK_ITER_ITEMS: u32 = 10_000; @@ -43,7 +43,7 @@ pub fn skip_sys_checks(test_name: &str) -> bool { return true; } - if cfg!(x86_no_sse) && X86_NO_SSE_SKIPPED.contains(&test_name) { + if cfg!(x86_no_sse2) && X86_NO_SSE_SKIPPED.contains(&test_name) { return true; } diff --git a/library/compiler-builtins/builtins-test/src/lib.rs b/library/compiler-builtins/builtins-test/src/lib.rs index f1673133be27d..56c04e551df9d 100644 --- a/library/compiler-builtins/builtins-test/src/lib.rs +++ b/library/compiler-builtins/builtins-test/src/lib.rs @@ -1,6 +1,6 @@ //! This crate is for integration testing and fuzz testing of functions in `compiler-builtins`. This //! includes publicly documented intrinsics and some internal alternative implementation functions -//! such as `usize_leading_zeros_riscv` (which are tested because they are configured for +//! such as `usize_leading_zeros_condset` (which are tested because they are configured for //! architectures not tested by the CI). //! //! The general idea is to use a combination of edge case testing and randomized fuzz testing. The @@ -19,10 +19,9 @@ pub mod bench; extern crate alloc; -use compiler_builtins::float::Float; -use compiler_builtins::int::{Int, MinInt}; +use compiler_builtins::support::{Float, Int, MinInt}; use rand_xoshiro::Xoshiro128StarStar; -use rand_xoshiro::rand_core::{RngCore, SeedableRng}; +use rand_xoshiro::rand_core::{Rng, SeedableRng}; /// Sets the number of fuzz iterations run for most tests. In practice, the vast majority of bugs /// are caught by the edge case testers. Most of the remaining bugs triggered by more complex @@ -245,18 +244,18 @@ fn fuzz_float_step(rng: &mut Xoshiro128StarStar, f: &mut F) { let sign = (rng32 & 1) != 0; // exponent fuzzing. Only 4 bits for the selector needed. - let ones = (F::Int::ONE << F::EXP_BITS) - F::Int::ONE; + let ones = F::EXP_SAT; let r0 = (rng32 >> 1) % F::EXP_BITS; let r1 = (rng32 >> 5) % F::EXP_BITS; // custom rotate shift. Note that `F::Int` is unsigned, so we can shift right without smearing // the sign bit. let mask = if r1 == 0 { - ones.wrapping_shr(r0) + ones >> r0 } else { - let tmp = ones.wrapping_shr(r0); - (tmp.wrapping_shl(r1) | tmp.wrapping_shr(F::EXP_BITS - r1)) & ones + let tmp = ones >> r0; + ((tmp << r1) | (tmp >> (F::EXP_BITS - r1))) & ones }; - let mut exp = (f.to_bits() & F::EXP_MASK) >> F::SIG_BITS; + let mut exp = f.ex(); match (rng32 >> 9) % 4 { 0 => exp |= mask, 1 => exp &= mask, @@ -274,13 +273,13 @@ fn fuzz_float_step(rng: &mut Xoshiro128StarStar, f: &mut F) { macro_rules! float_edge_cases { ($F:ident, $case:ident, $inner:block) => { for exponent in [ - F::Int::ZERO, - F::Int::ONE, - F::Int::ONE << (F::EXP_BITS / 2), - (F::Int::ONE << (F::EXP_BITS - 1)) - F::Int::ONE, - F::Int::ONE << (F::EXP_BITS - 1), - (F::Int::ONE << (F::EXP_BITS - 1)) + F::Int::ONE, - (F::Int::ONE << F::EXP_BITS) - F::Int::ONE, + 0, + 1, + 1 << (F::EXP_BITS / 2), + (1 << (F::EXP_BITS - 1)) - 1, + 1 << (F::EXP_BITS - 1), + (1 << (F::EXP_BITS - 1)) + 1, + (1 << F::EXP_BITS) - 1, ] .iter() { diff --git a/library/compiler-builtins/builtins-test/tests/addsub.rs b/library/compiler-builtins/builtins-test/tests/addsub.rs index f3334bd0e2d3a..859de3e425538 100644 --- a/library/compiler-builtins/builtins-test/tests/addsub.rs +++ b/library/compiler-builtins/builtins-test/tests/addsub.rs @@ -1,4 +1,4 @@ -#![allow(unused_macros)] +#![allow(unused_macros, unused_features)] #![cfg_attr(f16_enabled, feature(f16))] #![cfg_attr(f128_enabled, feature(f128))] @@ -87,7 +87,8 @@ macro_rules! float_sum { #[test] fn $fn_add() { use core::ops::{Add, Sub}; - use compiler_builtins::float::{{add::$fn_add, sub::$fn_sub}, Float}; + use compiler_builtins::float::{add::$fn_add, sub::$fn_sub}; + use compiler_builtins::support::Float; fuzz_float_2(N, |x: $f, y: $f| { let add0 = apfloat_fallback!($f, $apfloat_ty, $sys_available, Add::add, x, y); @@ -112,7 +113,7 @@ macro_rules! float_sum { } } -#[cfg(not(x86_no_sse))] +#[cfg(not(x86_no_sse2))] mod float_addsub { use super::*; @@ -127,15 +128,15 @@ mod float_addsub { } #[cfg(f128_enabled)] - #[cfg(not(x86_no_sse))] + #[cfg(not(x86_no_sse2))] #[cfg(not(any(target_arch = "powerpc", target_arch = "powerpc64")))] float_sum! { - f128, __addtf3, __subtf3, Quad, not(feature = "no-sys-f128"); + f128, __addtf3, __subtf3, Quad, not(no_sys_f128); } #[cfg(f128_enabled)] #[cfg(any(target_arch = "powerpc", target_arch = "powerpc64"))] float_sum! { - f128, __addkf3, __subkf3, Quad, not(feature = "no-sys-f128"); + f128, __addkf3, __subkf3, Quad, not(no_sys_f128); } } diff --git a/library/compiler-builtins/builtins-test/tests/big.rs b/library/compiler-builtins/builtins-test/tests/big.rs deleted file mode 100644 index d1ae88bd16485..0000000000000 --- a/library/compiler-builtins/builtins-test/tests/big.rs +++ /dev/null @@ -1,134 +0,0 @@ -use compiler_builtins::int::{HInt, MinInt, i256, u256}; - -const LOHI_SPLIT: u128 = 0xaaaaaaaaaaaaaaaaffffffffffffffff; - -/// Print a `u256` as hex since we can't add format implementations -fn hexu(v: u256) -> String { - format!( - "0x{:016x}{:016x}{:016x}{:016x}", - v.0[3], v.0[2], v.0[1], v.0[0] - ) -} - -#[test] -fn widen_u128() { - assert_eq!(u128::MAX.widen(), u256([u64::MAX, u64::MAX, 0, 0])); - assert_eq!( - LOHI_SPLIT.widen(), - u256([u64::MAX, 0xaaaaaaaaaaaaaaaa, 0, 0]) - ); -} - -#[test] -fn widen_i128() { - assert_eq!((-1i128).widen(), u256::MAX.signed()); - assert_eq!( - (LOHI_SPLIT as i128).widen(), - i256([u64::MAX, 0xaaaaaaaaaaaaaaaa, u64::MAX, u64::MAX]) - ); - assert_eq!((-1i128).zero_widen().unsigned(), (u128::MAX).widen()); -} - -#[test] -fn widen_mul_u128() { - let tests = [ - (u128::MAX / 2, 2_u128, u256([u64::MAX - 1, u64::MAX, 0, 0])), - (u128::MAX, 2_u128, u256([u64::MAX - 1, u64::MAX, 1, 0])), - (u128::MAX, u128::MAX, u256([1, 0, u64::MAX - 1, u64::MAX])), - (u128::MIN, u128::MIN, u256::ZERO), - (1234, 0, u256::ZERO), - (0, 1234, u256::ZERO), - ]; - - let mut errors = Vec::new(); - for (i, (a, b, exp)) in tests.iter().copied().enumerate() { - let res = a.widen_mul(b); - let res_z = a.zero_widen_mul(b); - assert_eq!(res, res_z); - if res != exp { - errors.push((i, a, b, exp, res)); - } - } - - for (i, a, b, exp, res) in &errors { - eprintln!( - "FAILURE ({i}): {a:#034x} * {b:#034x} = {} got {}", - hexu(*exp), - hexu(*res) - ); - } - assert!(errors.is_empty()); -} - -#[test] -fn not_u128() { - assert_eq!(!u256::ZERO, u256::MAX); -} - -#[test] -fn shr_u128() { - let only_low = [ - 1, - u16::MAX.into(), - u32::MAX.into(), - u64::MAX.into(), - u128::MAX, - ]; - - let mut errors = Vec::new(); - - for a in only_low { - for perturb in 0..10 { - let a = a.saturating_add(perturb); - for shift in 0..128 { - let res = a.widen() >> shift; - let expected = (a >> shift).widen(); - if res != expected { - errors.push((a.widen(), shift, res, expected)); - } - } - } - } - - let check = [ - ( - u256::MAX, - 1, - u256([u64::MAX, u64::MAX, u64::MAX, u64::MAX >> 1]), - ), - ( - u256::MAX, - 5, - u256([u64::MAX, u64::MAX, u64::MAX, u64::MAX >> 5]), - ), - (u256::MAX, 63, u256([u64::MAX, u64::MAX, u64::MAX, 1])), - (u256::MAX, 64, u256([u64::MAX, u64::MAX, u64::MAX, 0])), - (u256::MAX, 65, u256([u64::MAX, u64::MAX, u64::MAX >> 1, 0])), - (u256::MAX, 127, u256([u64::MAX, u64::MAX, 1, 0])), - (u256::MAX, 128, u256([u64::MAX, u64::MAX, 0, 0])), - (u256::MAX, 129, u256([u64::MAX, u64::MAX >> 1, 0, 0])), - (u256::MAX, 191, u256([u64::MAX, 1, 0, 0])), - (u256::MAX, 192, u256([u64::MAX, 0, 0, 0])), - (u256::MAX, 193, u256([u64::MAX >> 1, 0, 0, 0])), - (u256::MAX, 191, u256([u64::MAX, 1, 0, 0])), - (u256::MAX, 254, u256([0b11, 0, 0, 0])), - (u256::MAX, 255, u256([1, 0, 0, 0])), - ]; - - for (input, shift, expected) in check { - let res = input >> shift; - if res != expected { - errors.push((input, shift, res, expected)); - } - } - - for (a, b, res, expected) in &errors { - eprintln!( - "FAILURE: {} >> {b} = {} got {}", - hexu(*a), - hexu(*expected), - hexu(*res), - ); - } - assert!(errors.is_empty()); -} diff --git a/library/compiler-builtins/builtins-test/tests/cmp.rs b/library/compiler-builtins/builtins-test/tests/cmp.rs index 4b01b6ca1c7d7..d9360027a9643 100644 --- a/library/compiler-builtins/builtins-test/tests/cmp.rs +++ b/library/compiler-builtins/builtins-test/tests/cmp.rs @@ -125,19 +125,19 @@ mod float_comparisons { fuzz_float_2(N, |x: f128, y: f128| { let x_is_nan = apfloat_fallback!( - f128, Quad, not(feature = "no-sys-f128"), + f128, Quad, not(no_sys_f128), |x: FloatTy| x.is_nan() => no_convert, x ); let y_is_nan = apfloat_fallback!( - f128, Quad, not(feature = "no-sys-f128"), + f128, Quad, not(no_sys_f128), |x: FloatTy| x.is_nan() => no_convert, y ); assert_eq!(__unordtf2(x, y) != 0, x_is_nan || y_is_nan); - cmp!(f128, x, y, Quad, not(feature = "no-sys-f128"), + cmp!(f128, x, y, Quad, not(no_sys_f128), 1, __lttf2; 1, __letf2; 1, __eqtf2; diff --git a/library/compiler-builtins/builtins-test/tests/conv.rs b/library/compiler-builtins/builtins-test/tests/conv.rs index 9b04295d2efe8..e01eb259ac869 100644 --- a/library/compiler-builtins/builtins-test/tests/conv.rs +++ b/library/compiler-builtins/builtins-test/tests/conv.rs @@ -1,11 +1,12 @@ #![cfg_attr(f128_enabled, feature(f128))] #![cfg_attr(f16_enabled, feature(f16))] // makes configuration easier -#![allow(unused_macros)] +#![allow(unused_features)] #![allow(unused_imports)] +#![allow(unused_macros)] use builtins_test::*; -use compiler_builtins::float::Float; +use compiler_builtins::support::Float; use rustc_apfloat::{Float as _, FloatConvert as _}; mod i_to_f { @@ -17,7 +18,7 @@ mod i_to_f { #[test] fn $fn() { use compiler_builtins::float::conv::$fn; - use compiler_builtins::int::Int; + use compiler_builtins::support::Int; fuzz(N, |x: $i_ty| { let f0 = apfloat_fallback!( @@ -26,7 +27,7 @@ mod i_to_f { // When the builtin is not available, we need to use a different conversion // method (since apfloat doesn't support `as` casting). |x: $i_ty| { - use compiler_builtins::int::MinInt; + use compiler_builtins::support::MinInt; let apf = if <$i_ty>::SIGNED { FloatTy::from_i128(x.try_into().unwrap()).value @@ -116,7 +117,7 @@ mod i_to_f { #[cfg(f128_enabled)] #[cfg(not(any(target_arch = "powerpc", target_arch = "powerpc64")))] - i_to_f! { f128, Quad, not(feature = "no-sys-f128-int-convert"), + i_to_f! { f128, Quad, not(no_sys_f128_int_convert), u32, __floatunsitf; i32, __floatsitf; u64, __floatunditf; @@ -127,7 +128,7 @@ mod i_to_f { #[cfg(f128_enabled)] #[cfg(any(target_arch = "powerpc", target_arch = "powerpc64"))] - i_to_f! { f128, Quad, not(feature = "no-sys-f128-int-convert"), + i_to_f! { f128, Quad, not(no_sys_f128_int_convert), u32, __floatunsikf; i32, __floatsikf; u64, __floatundikf; @@ -154,7 +155,7 @@ mod f_to_i { // When the builtin is not available, we need to use a different conversion // method (since apfloat doesn't support `as` casting). |x: $f_ty| { - use compiler_builtins::int::MinInt; + use compiler_builtins::support::MinInt; let apf = FloatTy::from_bits(x.to_bits().into()); let bits: usize = <$i_ty>::BITS.try_into().unwrap(); @@ -235,7 +236,7 @@ mod f_to_i { x, f128, Quad, - not(feature = "no-sys-f128-int-convert"), + not(no_sys_f128_int_convert), u32, __fixunstfsi; u64, __fixunstfdi; u128, __fixunstfti; @@ -258,7 +259,8 @@ macro_rules! f_to_f { ) => {$( #[test] fn $fn() { - use compiler_builtins::float::{$mod::$fn, Float}; + use compiler_builtins::float::$mod::$fn; + use compiler_builtins::support::Float; use rustc_apfloat::ieee::{$from_ap_ty, $to_ap_ty}; fuzz_float(N, |x: $from_ty| { @@ -307,12 +309,12 @@ mod extend { )))] f_to_f! { extend, - f16 => f32, Half => Single, __extendhfsf2, not(feature = "no-sys-f16"); - f16 => f32, Half => Single, __gnu_h2f_ieee, not(feature = "no-sys-f16"); - f16 => f64, Half => Double, __extendhfdf2, not(feature = "no-sys-f16-f64-convert"); - f16 => f128, Half => Quad, __extendhftf2, not(feature = "no-sys-f16-f128-convert"); - f32 => f128, Single => Quad, __extendsftf2, not(feature = "no-sys-f128"); - f64 => f128, Double => Quad, __extenddftf2, not(feature = "no-sys-f128"); + f16 => f32, Half => Single, __extendhfsf2, not(no_sys_f16); + f16 => f32, Half => Single, __gnu_h2f_ieee, not(no_sys_f16); + f16 => f64, Half => Double, __extendhfdf2, not(no_sys_f16_f64_convert); + f16 => f128, Half => Quad, __extendhftf2, not(no_sys_f16_f128_convert); + f32 => f128, Single => Quad, __extendsftf2, not(no_sys_f128); + f64 => f128, Double => Quad, __extenddftf2, not(no_sys_f128); } #[cfg(f128_enabled)] @@ -320,8 +322,8 @@ mod extend { f_to_f! { extend, // FIXME(#655): `f16` tests disabled until we can bootstrap symbols - f32 => f128, Single => Quad, __extendsfkf2, not(feature = "no-sys-f128"); - f64 => f128, Double => Quad, __extenddfkf2, not(feature = "no-sys-f128"); + f32 => f128, Single => Quad, __extendsfkf2, not(no_sys_f128); + f64 => f128, Double => Quad, __extenddfkf2, not(no_sys_f128); } } @@ -341,12 +343,12 @@ mod trunc { )))] f_to_f! { trunc, - f32 => f16, Single => Half, __truncsfhf2, not(feature = "no-sys-f16"); - f32 => f16, Single => Half, __gnu_f2h_ieee, not(feature = "no-sys-f16"); - f64 => f16, Double => Half, __truncdfhf2, not(feature = "no-sys-f16-f64-convert"); - f128 => f16, Quad => Half, __trunctfhf2, not(feature = "no-sys-f16-f128-convert"); - f128 => f32, Quad => Single, __trunctfsf2, not(feature = "no-sys-f128"); - f128 => f64, Quad => Double, __trunctfdf2, not(feature = "no-sys-f128"); + f32 => f16, Single => Half, __truncsfhf2, not(no_sys_f16); + f32 => f16, Single => Half, __gnu_f2h_ieee, not(no_sys_f16); + f64 => f16, Double => Half, __truncdfhf2, not(no_sys_f16_f64_convert); + f128 => f16, Quad => Half, __trunctfhf2, not(no_sys_f16_f128_convert); + f128 => f32, Quad => Single, __trunctfsf2, not(no_sys_f128); + f128 => f64, Quad => Double, __trunctfdf2, not(no_sys_f128); } #[cfg(f128_enabled)] @@ -354,7 +356,7 @@ mod trunc { f_to_f! { trunc, // FIXME(#655): `f16` tests disabled until we can bootstrap symbols - f128 => f32, Quad => Single, __trunckfsf2, not(feature = "no-sys-f128"); - f128 => f64, Quad => Double, __trunckfdf2, not(feature = "no-sys-f128"); + f128 => f32, Quad => Single, __trunckfsf2, not(no_sys_f128); + f128 => f64, Quad => Double, __trunckfdf2, not(no_sys_f128); } } diff --git a/library/compiler-builtins/builtins-test/tests/div_rem.rs b/library/compiler-builtins/builtins-test/tests/div_rem.rs index caee4166c9958..5d04fe9c0a9b1 100644 --- a/library/compiler-builtins/builtins-test/tests/div_rem.rs +++ b/library/compiler-builtins/builtins-test/tests/div_rem.rs @@ -1,5 +1,5 @@ #![feature(f128)] -#![allow(unused_macros)] +#![allow(unused_macros, unused_features)] use builtins_test::*; use compiler_builtins::int::sdiv::{__divmoddi4, __divmodsi4, __divmodti4}; @@ -109,7 +109,8 @@ macro_rules! float { $( #[test] fn $fn() { - use compiler_builtins::float::{div::$fn, Float}; + use compiler_builtins::float::div::$fn; + use compiler_builtins::support::Float; use core::ops::Div; fuzz_float_2(N, |x: $f, y: $f| { @@ -138,7 +139,7 @@ macro_rules! float { }; } -#[cfg(not(x86_no_sse))] +#[cfg(not(x86_no_sse2))] mod float_div { use super::*; @@ -153,12 +154,12 @@ mod float_div { f128, __divtf3, Quad, // FIXME(llvm): there is a bug in LLVM rt. // See . - not(any(feature = "no-sys-f128", all(target_arch = "aarch64", target_os = "linux"))); + not(any(no_sys_f128, all(target_arch = "aarch64", target_os = "linux"))); } #[cfg(f128_enabled)] #[cfg(any(target_arch = "powerpc", target_arch = "powerpc64"))] float! { - f128, __divkf3, Quad, not(feature = "no-sys-f128"); + f128, __divkf3, Quad, not(no_sys_f128); } } diff --git a/library/compiler-builtins/builtins-test/tests/float_pow.rs b/library/compiler-builtins/builtins-test/tests/float_pow.rs index a17dff27c105a..c808b9efae65f 100644 --- a/library/compiler-builtins/builtins-test/tests/float_pow.rs +++ b/library/compiler-builtins/builtins-test/tests/float_pow.rs @@ -1,7 +1,7 @@ -#![allow(unused_macros)] +#![allow(unused_macros, unused_features)] #![cfg_attr(f128_enabled, feature(f128))] -#[cfg_attr(x86_no_sse, allow(unused))] +#[cfg_attr(x86_no_sse2, allow(unused))] use builtins_test::*; // This is approximate because of issues related to @@ -16,7 +16,8 @@ macro_rules! pow { #[cfg($sys_available)] fn $fn() { use compiler_builtins::float::pow::$fn; - use compiler_builtins::float::Float; + use compiler_builtins::support::Float; + fuzz_float_2(N, |x: $f, y: $f| { if !(Float::is_subnormal(x) || Float::is_subnormal(y) || x.is_nan()) { let n = y.to_bits() & !<$f as Float>::SIG_MASK; @@ -52,7 +53,7 @@ macro_rules! pow { }; } -#[cfg(not(x86_no_sse))] // FIXME(i586): failure for powidf2 +#[cfg(not(x86_no_sse2))] // FIXME(i586): failure for powidf2 pow! { f32, 1e-4, __powisf2, all(); f64, 1e-12, __powidf2, all(); @@ -61,11 +62,11 @@ pow! { #[cfg(f128_enabled)] #[cfg(not(any(target_arch = "powerpc", target_arch = "powerpc64")))] pow! { - f128, 1e-36, __powitf2, not(feature = "no-sys-f128"); + f128, 1e-36, __powitf2, not(no_sys_f128); } #[cfg(f128_enabled)] #[cfg(any(target_arch = "powerpc", target_arch = "powerpc64"))] pow! { - f128, 1e-36, __powikf2, not(feature = "no-sys-f128"); + f128, 1e-36, __powikf2, not(no_sys_f128); } diff --git a/library/compiler-builtins/builtins-test/tests/lse.rs b/library/compiler-builtins/builtins-test/tests/lse.rs index 56891be8a8ac1..20d4d19a328a1 100644 --- a/library/compiler-builtins/builtins-test/tests/lse.rs +++ b/library/compiler-builtins/builtins-test/tests/lse.rs @@ -1,30 +1,71 @@ +#![allow(unused_features)] #![feature(decl_macro)] // so we can use pub(super) #![feature(macro_metavar_expr_concat)] -#![cfg(all(target_arch = "aarch64", target_os = "linux"))] +#![cfg(target_arch = "aarch64")] + +use std::sync::Mutex; + +use compiler_builtins::aarch64_outline_atomics::{get_have_lse_atomics, set_have_lse_atomics}; +use compiler_builtins::support::{Int, MinInt}; +use compiler_builtins::{foreach_bytes, foreach_ordering}; + +#[track_caller] +fn with_maybe_lse_atomics(use_lse: bool, f: impl FnOnce()) { + // Ensure tests run in parallel don't interleave global settings + static LOCK: Mutex<()> = Mutex::new(()); + let _g = LOCK.lock().unwrap(); + let old = get_have_lse_atomics(); + // safety: as the caller of the unsafe fn `set_have_lse_atomics`, we + // have to ensure the CPU supports LSE. This is why we make this assertion. + if use_lse || old { + assert!(std::arch::is_aarch64_feature_detected!("lse")); + } + unsafe { set_have_lse_atomics(use_lse) }; + f(); + unsafe { set_have_lse_atomics(old) }; +} + +pub fn run_fuzz_tests_with_lse_variants(n: u32, f: F) +where + ::Unsigned: Int, +{ + // We use `fuzz_2` because our subject function `f` requires two inputs + let test_fn = || { + builtins_test::fuzz_2(n, f); + }; + // Always run without LSE + with_maybe_lse_atomics(false, test_fn); + + // Conditionally run with LSE + if std::arch::is_aarch64_feature_detected!("lse") { + with_maybe_lse_atomics(true, test_fn); + } +} /// Translate a byte size to a Rust type. macro int_ty { - (1) => { i8 }, - (2) => { i16 }, - (4) => { i32 }, - (8) => { i64 }, - (16) => { i128 } + (1) => { u8 }, + (2) => { u16 }, + (4) => { u32 }, + (8) => { u64 }, + (16) => { u128 } } mod cas { pub(super) macro test($_ordering:ident, $bytes:tt, $name:ident) { #[test] fn $name() { - builtins_test::fuzz_2(10000, |expected: super::int_ty!($bytes), new| { + crate::run_fuzz_tests_with_lse_variants(10000, |expected: super::int_ty!($bytes), new| { let mut target = expected.wrapping_add(10); + let ret: super::int_ty!($bytes) = unsafe { + compiler_builtins::aarch64_outline_atomics::$name::$name( + expected, + new, + &mut target, + ) + }; assert_eq!( - unsafe { - compiler_builtins::aarch64_outline_atomics::$name::$name( - expected, - new, - &mut target, - ) - }, + ret, expected.wrapping_add(10), "return value should always be the previous value", ); @@ -35,15 +76,17 @@ mod cas { ); target = expected; + let ret: super::int_ty!($bytes) = unsafe { + compiler_builtins::aarch64_outline_atomics::$name::$name( + expected, + new, + &mut target, + ) + }; assert_eq!( - unsafe { - compiler_builtins::aarch64_outline_atomics::$name::$name( - expected, - new, - &mut target, - ) - }, - expected + ret, + expected, + "the new return value should always be the previous value (i.e. the first parameter passed to the function)", ); assert_eq!(target, new, "should have updated target"); }); @@ -59,16 +102,21 @@ mod swap { pub(super) macro test($_ordering:ident, $bytes:tt, $name:ident) { #[test] fn $name() { - builtins_test::fuzz_2(10000, |left: super::int_ty!($bytes), mut right| { - let orig_right = right; - assert_eq!( - unsafe { - compiler_builtins::aarch64_outline_atomics::$name::$name(left, &mut right) - }, - orig_right - ); - assert_eq!(left, right); - }); + crate::run_fuzz_tests_with_lse_variants( + 10000, + |left: super::int_ty!($bytes), mut right| { + let orig_right = right; + assert_eq!( + unsafe { + compiler_builtins::aarch64_outline_atomics::$name::$name( + left, &mut right, + ) + }, + orig_right + ); + assert_eq!(left, right); + }, + ); } } } @@ -80,7 +128,7 @@ macro_rules! test_op { ($_ordering:ident, $bytes:tt, $name:ident) => { #[test] fn $name() { - builtins_test::fuzz_2(10000, |old, val| { + crate::run_fuzz_tests_with_lse_variants(10000, |old, val| { let mut target = old; let op: fn(super::int_ty!($bytes), super::int_ty!($bytes)) -> _ = $($op)*; let expected = op(old, val); @@ -98,7 +146,6 @@ test_op!(add, |left, right| left.wrapping_add(right)); test_op!(clr, |left, right| left & !right); test_op!(xor, std::ops::BitXor::bitxor); test_op!(or, std::ops::BitOr::bitor); -use compiler_builtins::{foreach_bytes, foreach_ordering}; compiler_builtins::foreach_cas!(cas::test); compiler_builtins::foreach_cas16!(test_cas16); compiler_builtins::foreach_swp!(swap::test); diff --git a/library/compiler-builtins/builtins-test/tests/misc.rs b/library/compiler-builtins/builtins-test/tests/misc.rs index 64a9d56f36b33..a637cb71189e5 100644 --- a/library/compiler-builtins/builtins-test/tests/misc.rs +++ b/library/compiler-builtins/builtins-test/tests/misc.rs @@ -65,7 +65,7 @@ fn fuzz_values() { #[test] fn leading_zeros() { - use compiler_builtins::int::leading_zeros::{leading_zeros_default, leading_zeros_riscv}; + use compiler_builtins::int::leading_zeros::{leading_zeros_condset, leading_zeros_default}; { use compiler_builtins::int::leading_zeros::__clzsi2; fuzz(N, |x: u32| { @@ -75,7 +75,7 @@ fn leading_zeros() { let lz = x.leading_zeros() as usize; let lz0 = __clzsi2(x); let lz1 = leading_zeros_default(x); - let lz2 = leading_zeros_riscv(x); + let lz2 = leading_zeros_condset(x); if lz0 != lz { panic!("__clzsi2({x}): std: {lz}, builtins: {lz0}"); } @@ -83,7 +83,7 @@ fn leading_zeros() { panic!("leading_zeros_default({x}): std: {lz}, builtins: {lz1}"); } if lz2 != lz { - panic!("leading_zeros_riscv({x}): std: {lz}, builtins: {lz2}"); + panic!("leading_zeros_condset({x}): std: {lz}, builtins: {lz2}"); } }); } @@ -97,7 +97,7 @@ fn leading_zeros() { let lz = x.leading_zeros() as usize; let lz0 = __clzdi2(x); let lz1 = leading_zeros_default(x); - let lz2 = leading_zeros_riscv(x); + let lz2 = leading_zeros_condset(x); if lz0 != lz { panic!("__clzdi2({x}): std: {lz}, builtins: {lz0}"); } @@ -105,7 +105,7 @@ fn leading_zeros() { panic!("leading_zeros_default({x}): std: {lz}, builtins: {lz1}"); } if lz2 != lz { - panic!("leading_zeros_riscv({x}): std: {lz}, builtins: {lz2}"); + panic!("leading_zeros_condset({x}): std: {lz}, builtins: {lz2}"); } }); } diff --git a/library/compiler-builtins/builtins-test/tests/mul.rs b/library/compiler-builtins/builtins-test/tests/mul.rs index bbf1157db42f9..b16d729be1dd5 100644 --- a/library/compiler-builtins/builtins-test/tests/mul.rs +++ b/library/compiler-builtins/builtins-test/tests/mul.rs @@ -1,6 +1,6 @@ #![cfg_attr(f16_enabled, feature(f16))] #![cfg_attr(f128_enabled, feature(f128))] -#![allow(unused_macros)] +#![allow(unused_macros, unused_features)] use builtins_test::*; @@ -96,7 +96,8 @@ macro_rules! float_mul { $( #[test] fn $fn() { - use compiler_builtins::float::{mul::$fn, Float}; + use compiler_builtins::float::mul::$fn; + use compiler_builtins::support::Float; use core::ops::Mul; fuzz_float_2(N, |x: $f, y: $f| { @@ -114,7 +115,7 @@ macro_rules! float_mul { }; } -#[cfg(not(x86_no_sse))] +#[cfg(not(x86_no_sse2))] mod float_mul { use super::*; @@ -132,7 +133,7 @@ mod float_mul { } #[cfg(f128_enabled)] -#[cfg(not(x86_no_sse))] +#[cfg(not(x86_no_sse2))] #[cfg(not(any(target_arch = "powerpc", target_arch = "powerpc64")))] mod float_mul_f128 { use super::*; @@ -141,7 +142,7 @@ mod float_mul_f128 { f128, __multf3, Quad, // FIXME(llvm): there is a bug in LLVM rt. // See . - not(any(feature = "no-sys-f128", all(target_arch = "aarch64", target_os = "linux"))); + not(any(no_sys_f128, all(target_arch = "aarch64", target_os = "linux"))); } } @@ -151,6 +152,6 @@ mod float_mul_f128_ppc { use super::*; float_mul! { - f128, __mulkf3, Quad, not(feature = "no-sys-f128"); + f128, __mulkf3, Quad, not(no_sys_f128); } } diff --git a/library/compiler-builtins/ci/bench-icount.sh b/library/compiler-builtins/ci/bench-icount.sh index 6d92b50a6dae7..ac86453bceb18 100755 --- a/library/compiler-builtins/ci/bench-icount.sh +++ b/library/compiler-builtins/ci/bench-icount.sh @@ -13,6 +13,7 @@ fi # Print machine information uname -a lscpu || true +rustc -Vv gungraun_home="gungraun-home" @@ -26,12 +27,20 @@ tag="$(echo "$target" | cut -d'-' -f1)" # after the first run with gungraun. [ -d "iai-home" ] && mv "iai-home" "$gungraun_home" +failed="0" + # Run benchmarks once function run_icount_benchmarks() { cargo_args=( + "--target" "$target" "--bench" "*icount*" "--no-default-features" - "--features" "unstable,unstable-float,icount" + "--features" "unstable unstable-float icount" + # Enable unmangled-names so our compiler-builtins gets used for + # intrinsics. This makes performance impacts of c-b changes show up + # in libm benchmarks and gives us a better idea of what will happen + # in std (e.g. speedups in __addtf3 will show up in fmaf128). + "--features" "compiler_builtins/unmangled-names" ) gungraun_args=( @@ -65,13 +74,18 @@ function run_icount_benchmarks() { # Disregard regressions after merge echo "Benchmarks completed with regressions; ignoring (not in a PR)" else - ./ci/ci-util.py handle-bench-regressions "$PR_NUMBER" + ./ci/ci-util.py handle-bench-regressions "$PR_NUMBER" || failed="1" fi } # Run once with softfloats, once with arch instructions enabled -run_icount_benchmarks --features force-soft-floats -- --save-baseline=softfloat -run_icount_benchmarks -- --save-baseline=hardfloat +run_icount_benchmarks -- --save-baseline=arch_disabled +run_icount_benchmarks --features arch -- --save-baseline=arch_enabled + +if [ "$failed" != "0" ]; then + echo "One or more benchmarks failed" + exit 1 +fi # Name and tar the new baseline name="baseline-icount-$tag-$(date -u +'%Y%m%d%H%M')-${GITHUB_SHA:0:12}" diff --git a/library/compiler-builtins/ci/bench-runtime.sh b/library/compiler-builtins/ci/bench-walltime.sh similarity index 79% rename from library/compiler-builtins/ci/bench-runtime.sh rename to library/compiler-builtins/ci/bench-walltime.sh index d272cf33463ed..5d564c97beb35 100755 --- a/library/compiler-builtins/ci/bench-runtime.sh +++ b/library/compiler-builtins/ci/bench-walltime.sh @@ -6,4 +6,4 @@ export LIBM_SEED=benchesbenchesbenchesbencheswoo! cargo bench --package libm-test \ --no-default-features \ - --features short-benchmarks,build-musl,libm/force-soft-floats + --features walltime,short-benchmarks,build-musl diff --git a/library/compiler-builtins/ci/ci-util.py b/library/compiler-builtins/ci/ci-util.py index ef9ce455178ec..97f563dbd6230 100755 --- a/library/compiler-builtins/ci/ci-util.py +++ b/library/compiler-builtins/ci/ci-util.py @@ -11,7 +11,7 @@ import re import subprocess as sp import sys -from dataclasses import dataclass +from dataclasses import dataclass, field from functools import cache from glob import glob from inspect import cleandoc @@ -19,8 +19,7 @@ from pathlib import Path from typing import TypedDict, Self -USAGE = cleandoc( - """ +USAGE = cleandoc(""" usage: ./ci/ci-util.py [flags] @@ -44,8 +43,7 @@ Exit with success if the pull request contains a line starting with `ci: allow-regressions`, indicating that regressions in benchmarks should be accepted. Otherwise, exit 1. - """ -) + """) REPO_ROOT = Path(__file__).parent.parent GIT = ["git", "-C", REPO_ROOT] @@ -73,17 +71,21 @@ def eprint(*args, **kwargs): print(*args, file=sys.stderr, **kwargs) -@dataclass(init=False) +@dataclass(kw_only=True) class PrCfg: """Directives that we allow in the commit body to control test behavior. These are of the form `ci: foo`, at the start of a line. """ + # The PR body + body: str # Skip regression checks (must be at the start of a line). allow_regressions: bool = False # Don't run extensive tests skip_extensive: bool = False + # Add these extensive tests to the list + extra_extensive: list[str] = field(default_factory=list, init=False) # Allow running a large number of extensive tests. If not set, this script # will error out if a threshold is exceeded in order to avoid accidentally @@ -101,11 +103,17 @@ class PrCfg: DIR_SKIP_EXTENSIVE: str = "skip-extensive" DIR_ALLOW_MANY_EXTENSIVE: str = "allow-many-extensive" DIR_TEST_LIBM: str = "test-libm" + DIR_EXTRA_EXTENSIVE: str = "extra-extensive" - def __init__(self, body: str): - directives = re.finditer(r"^\s*ci:\s*(?P\S*)", body, re.MULTILINE) + def __post_init__(self): + directives = re.finditer( + r"^\s*ci:\s*(?P[^\s=]*)(?:\s*=\s*(?P.*))?", + self.body, + re.MULTILINE, + ) for dir in directives: name = dir.group("dir_name") + args = dir.group("args") if name == self.DIR_ALLOW_REGRESSIONS: self.allow_regressions = True elif name == self.DIR_SKIP_EXTENSIVE: @@ -114,11 +122,18 @@ def __init__(self, body: str): self.allow_many_extensive = True elif name == self.DIR_TEST_LIBM: self.always_test_libm = True + elif name == self.DIR_EXTRA_EXTENSIVE: + self.extra_extensive = [x.strip() for x in args.split(",")] + args = None else: eprint(f"Found unexpected directive `{name}`") exit(1) - pprint.pp(self) + if args is not None: + eprint("Found arguments where not expected") + exit(1) + + eprint(pprint.pformat(self)) @dataclass @@ -158,7 +173,7 @@ def from_pr(cls, pr_number: int | str) -> Self: ) pr_json = json.loads(pr_info) eprint("PR info:", json.dumps(pr_json, indent=4)) - return cls(**json.loads(pr_info), cfg=PrCfg(pr_json["body"])) + return cls(**pr_json, cfg=PrCfg(body=pr_json["body"])) class FunctionDef(TypedDict): @@ -214,12 +229,21 @@ def _init_change_list(self): assert len(parents) == 2, f"expected two-parent merge but got:\n{parents}" base = parents[0].strip() incoming = parents[1].strip() - eprint(f"base: {base}, incoming: {incoming}") + + merge_base = sp.check_output( + GIT + ["merge-base", base, incoming], text=True + ).strip() + eprint(f"merge base: {merge_base}") + textlist = sp.check_output( - GIT + ["diff", base, incoming, "--name-only"], text=True + GIT + ["diff", merge_base, incoming, "--name-only"], text=True ) self.changed = [Path(p) for p in textlist.splitlines()] + eprint("all changed: [") + for f in self.changed: + eprint(f" {f},") + eprint("]") def is_pr(self) -> bool: """Check if we are looking at a PR rather than a push.""" @@ -276,29 +300,35 @@ def emit_workflow_output(self): skip_tests = False error_on_many_tests = False + extra_tests = {} pr = PrInfo.from_env() if pr is not None: skip_tests = pr.cfg.skip_extensive error_on_many_tests = not pr.cfg.allow_many_extensive + for fn_name in pr.cfg.extra_extensive: + extra_tests.setdefault(base_name(fn_name)[1], []).append(fn_name) if skip_tests: eprint("Skipping all extensive tests") changed = self.changed_routines() + eprint(f"changed routines: {changed}") + matrix = [] total_to_test = 0 # Figure out which extensive tests need to run for ty in TYPES: ty_changed = changed.get(ty, []) - ty_to_test = [] if skip_tests else ty_changed + ty_to_test = [] if skip_tests else ty_changed.copy() + ty_to_test.extend(extra_tests.get(ty, [])) total_to_test += len(ty_to_test) item = { "ty": ty, - "changed": ",".join(ty_changed), - "to_test": ",".join(ty_to_test), + "changed": ",".join(sorted(set(ty_changed))), + "to_test": ",".join(sorted(set(ty_to_test))), } matrix.append(item) @@ -319,6 +349,37 @@ def emit_workflow_output(self): exit(1) +def base_name(name: str) -> tuple[str, str]: + """Return the basename and type from a full function name. Keep in sync with Rust's + `fn base_name`. + """ + known_mappings = [ + ("erff", ("erf", "f32")), + ("erf", ("erf", "f64")), + ("modff", ("modf", "f32")), + ("modf", ("modf", "f64")), + ("lgammaf_r", ("lgamma_r", "f32")), + ("lgamma_r", ("lgamma_r", "f64")), + ] + + found = next((base for (full, base) in known_mappings if full == name), None) + if found is not None: + return found + + if name.endswith("f"): + return (name.rstrip("f"), "f32") + elif name.endswith("f16"): + return (name.rstrip("f16"), "f16") + elif name.endswith("f32"): + return (name.rstrip("f32"), "f32") + elif name.endswith("f64"): + return (name.rstrip("f64"), "f64") + elif name.endswith("f128"): + return (name.rstrip("f128"), "f128") + + return (name, "f64") + + def locate_baseline(flags: list[str]) -> None: """Find the most recent baseline from CI, download it if specified. diff --git a/library/compiler-builtins/ci/compiler-rt-patches/0001-compiler-rt-Disable-executable-stack-on-aeabi_u-read.patch b/library/compiler-builtins/ci/compiler-rt-patches/0001-compiler-rt-Disable-executable-stack-on-aeabi_u-read.patch new file mode 100644 index 0000000000000..13f4bc31d08f7 --- /dev/null +++ b/library/compiler-builtins/ci/compiler-rt-patches/0001-compiler-rt-Disable-executable-stack-on-aeabi_u-read.patch @@ -0,0 +1,95 @@ +From 849c51e082b0958524246a0a880f46d468a55147 Mon Sep 17 00:00:00 2001 +From: Trevor Gross +Date: Thu, 6 Aug 2026 09:08:27 -0400 +Subject: [PATCH] [compiler-rt] Disable executable stack on + `aeabi_u{read,write}*.S` (#214465) + +These were missing `NO_EXEC_STACK_DIRECTIVE` to add `.note.GNU-stack`; +without it, a binary including any of these files will have the stack +marked executable. Add the directive here, matching other similar files. + +Symtab diff before: + +$ clang compiler-rt/lib/builtins/arm/aeabi_uread4.S +--target=arm-unknown-linux-gnueabi -c + $ llvm-readelf aeabi_uread4.o -S + There are 5 section headers, starting at offset 0xe4: + + Section Headers: +[Nr] Name Type Address Off Size ES Flg Lk Inf Al +[ 0] NULL 00000000 000000 000000 00 0 0 0 +[ 1] .strtab STRTAB 00000000 0000a8 000039 00 0 0 1 +[ 2] .text PROGBITS 00000000 000034 000020 00 AX 0 0 4 +[ 3] .ARM.attributes ARM_ATTRIBUTES 00000000 000054 000022 00 0 0 1 +[ 4] .symtab SYMTAB 00000000 000078 000030 10 1 2 4 + +After: + +$ clang compiler-rt/lib/builtins/arm/aeabi_uread4.S +--target=arm-unknown-linux-gnueabi -c + $ llvm-readelf aeabi_uread4.o -S + There are 6 section headers, starting at offset 0xf4: + + Section Headers: +[Nr] Name Type Address Off Size ES Flg Lk Inf Al +[ 0] NULL 00000000 000000 000000 00 0 0 0 +[ 1] .strtab STRTAB 00000000 0000a8 000049 00 0 0 1 +[ 2] .text PROGBITS 00000000 000034 000020 00 AX 0 0 4 +[ 3] .note.GNU-stack PROGBITS 00000000 000054 000000 00 0 0 1 +[ 4] .ARM.attributes ARM_ATTRIBUTES 00000000 000054 000022 00 0 0 1 +[ 5] .symtab SYMTAB 00000000 000078 000030 10 1 2 4 + +Fixes: 39413af931a7 ("[Compiler-rt] Implement AEABI Unaligned Read/Write + Helpers in compiler-rt (#167913)") +--- + +Add this patch to avoid a symcheck failure until the LLVM update can work +through. + + compiler-rt/lib/builtins/arm/aeabi_uread4.S | 1 + + compiler-rt/lib/builtins/arm/aeabi_uread8.S | 2 ++ + compiler-rt/lib/builtins/arm/aeabi_uwrite4.S | 2 ++ + compiler-rt/lib/builtins/arm/aeabi_uwrite8.S | 2 ++ + 4 files changed, 7 insertions(+) + +diff --git a/compiler-rt/lib/builtins/arm/aeabi_uread4.S b/compiler-rt/lib/builtins/arm/aeabi_uread4.S +index 4a54890fdf83..05e476a17905 100644 +--- a/compiler-rt/lib/builtins/arm/aeabi_uread4.S ++++ b/compiler-rt/lib/builtins/arm/aeabi_uread4.S +@@ -61,3 +61,4 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_uread4) + #endif + END_COMPILERRT_FUNCTION(__aeabi_uread4) + ++NO_EXEC_STACK_DIRECTIVE +diff --git a/compiler-rt/lib/builtins/arm/aeabi_uread8.S b/compiler-rt/lib/builtins/arm/aeabi_uread8.S +index 32844b8b3c7e..0b12c48ae46f 100644 +--- a/compiler-rt/lib/builtins/arm/aeabi_uread8.S ++++ b/compiler-rt/lib/builtins/arm/aeabi_uread8.S +@@ -98,3 +98,5 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_uread8) + #endif + + END_COMPILERRT_FUNCTION(__aeabi_uread8) ++ ++NO_EXEC_STACK_DIRECTIVE +diff --git a/compiler-rt/lib/builtins/arm/aeabi_uwrite4.S b/compiler-rt/lib/builtins/arm/aeabi_uwrite4.S +index 9f749695910b..7e9a0337b781 100644 +--- a/compiler-rt/lib/builtins/arm/aeabi_uwrite4.S ++++ b/compiler-rt/lib/builtins/arm/aeabi_uwrite4.S +@@ -33,3 +33,5 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_uwrite4) + #endif + bx lr + END_COMPILERRT_FUNCTION(__aeabi_uwrite4) ++ ++NO_EXEC_STACK_DIRECTIVE +diff --git a/compiler-rt/lib/builtins/arm/aeabi_uwrite8.S b/compiler-rt/lib/builtins/arm/aeabi_uwrite8.S +index 8188032fc3bd..763f42ff7ed0 100644 +--- a/compiler-rt/lib/builtins/arm/aeabi_uwrite8.S ++++ b/compiler-rt/lib/builtins/arm/aeabi_uwrite8.S +@@ -49,3 +49,5 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_uwrite8) + #endif + bx lr + END_COMPILERRT_FUNCTION(__aeabi_uwrite8) ++ ++NO_EXEC_STACK_DIRECTIVE +-- +2.50.1 (Apple Git-155) diff --git a/library/compiler-builtins/ci/docker/aarch64-unknown-linux-gnu/Dockerfile b/library/compiler-builtins/ci/docker/aarch64-unknown-linux-gnu/Dockerfile index 69b99f5b6b328..30a13fc5de910 100644 --- a/library/compiler-builtins/ci/docker/aarch64-unknown-linux-gnu/Dockerfile +++ b/library/compiler-builtins/ci/docker/aarch64-unknown-linux-gnu/Dockerfile @@ -1,15 +1,15 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ gcc libc6-dev ca-certificates \ gcc-aarch64-linux-gnu m4 make libc6-dev-arm64-cross \ - qemu-user-static + qemu-user ENV TOOLCHAIN_PREFIX=aarch64-linux-gnu- ENV CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_RUNNER=qemu-aarch64-static \ + CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_RUNNER=qemu-aarch64 \ AR_aarch64_unknown_linux_gnu="$TOOLCHAIN_PREFIX"ar \ CC_aarch64_unknown_linux_gnu="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/aarch64-linux-gnu \ diff --git a/library/compiler-builtins/ci/docker/arm-unknown-linux-gnueabi/Dockerfile b/library/compiler-builtins/ci/docker/arm-unknown-linux-gnueabi/Dockerfile index 2fa6f85205206..41ff36a49e3bb 100644 --- a/library/compiler-builtins/ci/docker/arm-unknown-linux-gnueabi/Dockerfile +++ b/library/compiler-builtins/ci/docker/arm-unknown-linux-gnueabi/Dockerfile @@ -1,14 +1,14 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ gcc libc6-dev ca-certificates \ - gcc-arm-linux-gnueabi libc6-dev-armel-cross qemu-user-static + gcc-arm-linux-gnueabi libc6-dev-armel-cross qemu-user ENV TOOLCHAIN_PREFIX=arm-linux-gnueabi- ENV CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABI_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABI_RUNNER=qemu-arm-static \ + CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABI_RUNNER=qemu-arm \ AR_arm_unknown_linux_gnueabi="$TOOLCHAIN_PREFIX"ar \ CC_arm_unknown_linux_gnueabi="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/arm-linux-gnueabi \ diff --git a/library/compiler-builtins/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile b/library/compiler-builtins/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile index 85f7335f5a85b..1fad72c470f03 100644 --- a/library/compiler-builtins/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile +++ b/library/compiler-builtins/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile @@ -1,14 +1,14 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ gcc libc6-dev ca-certificates \ - gcc-arm-linux-gnueabihf libc6-dev-armhf-cross qemu-user-static + gcc-arm-linux-gnueabihf libc6-dev-armhf-cross qemu-user ENV TOOLCHAIN_PREFIX=arm-linux-gnueabihf- ENV CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABIHF_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABIHF_RUNNER=qemu-arm-static \ + CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABIHF_RUNNER=qemu-arm \ AR_arm_unknown_linux_gnueabihf="$TOOLCHAIN_PREFIX"ar \ CC_arm_unknown_linux_gnueabihf="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/arm-linux-gnueabihf \ diff --git a/library/compiler-builtins/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile b/library/compiler-builtins/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile index 42511479f36ff..039ccd5745256 100644 --- a/library/compiler-builtins/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile +++ b/library/compiler-builtins/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile @@ -1,14 +1,14 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ gcc libc6-dev ca-certificates \ - gcc-arm-linux-gnueabihf libc6-dev-armhf-cross qemu-user-static + gcc-arm-linux-gnueabihf libc6-dev-armhf-cross qemu-user ENV TOOLCHAIN_PREFIX=arm-linux-gnueabihf- ENV CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_RUNNER=qemu-arm-static \ + CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_RUNNER=qemu-arm \ AR_armv7_unknown_linux_gnueabihf="$TOOLCHAIN_PREFIX"ar \ CC_armv7_unknown_linux_gnueabihf="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/arm-linux-gnueabihf \ diff --git a/library/compiler-builtins/ci/docker/i586-unknown-linux-gnu/Dockerfile b/library/compiler-builtins/ci/docker/i586-unknown-linux-gnu/Dockerfile index 35488c4774933..9319e73dd03f0 100644 --- a/library/compiler-builtins/ci/docker/i586-unknown-linux-gnu/Dockerfile +++ b/library/compiler-builtins/ci/docker/i586-unknown-linux-gnu/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/library/compiler-builtins/ci/docker/i686-unknown-linux-gnu/Dockerfile b/library/compiler-builtins/ci/docker/i686-unknown-linux-gnu/Dockerfile index 35488c4774933..9319e73dd03f0 100644 --- a/library/compiler-builtins/ci/docker/i686-unknown-linux-gnu/Dockerfile +++ b/library/compiler-builtins/ci/docker/i686-unknown-linux-gnu/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/library/compiler-builtins/ci/docker/loongarch64-unknown-linux-gnu/Dockerfile b/library/compiler-builtins/ci/docker/loongarch64-unknown-linux-gnu/Dockerfile index e95a1b9163ff9..442a13164880c 100644 --- a/library/compiler-builtins/ci/docker/loongarch64-unknown-linux-gnu/Dockerfile +++ b/library/compiler-builtins/ci/docker/loongarch64-unknown-linux-gnu/Dockerfile @@ -1,13 +1,13 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ - gcc libc6-dev qemu-user-static ca-certificates \ + gcc libc6-dev qemu-user ca-certificates \ gcc-14-loongarch64-linux-gnu libc6-dev-loong64-cross ENV CARGO_TARGET_LOONGARCH64_UNKNOWN_LINUX_GNU_LINKER=loongarch64-linux-gnu-gcc-14 \ - CARGO_TARGET_LOONGARCH64_UNKNOWN_LINUX_GNU_RUNNER=qemu-loongarch64-static \ + CARGO_TARGET_LOONGARCH64_UNKNOWN_LINUX_GNU_RUNNER=qemu-loongarch64 \ AR_loongarch64_unknown_linux_gnu=loongarch64-linux-gnu-ar \ CC_loongarch64_unknown_linux_gnu=loongarch64-linux-gnu-gcc-14 \ QEMU_LD_PREFIX=/usr/loongarch64-linux-gnu \ diff --git a/library/compiler-builtins/ci/docker/mips-unknown-linux-gnu/Dockerfile b/library/compiler-builtins/ci/docker/mips-unknown-linux-gnu/Dockerfile index fd1877603100a..9941a8c2736c0 100644 --- a/library/compiler-builtins/ci/docker/mips-unknown-linux-gnu/Dockerfile +++ b/library/compiler-builtins/ci/docker/mips-unknown-linux-gnu/Dockerfile @@ -1,15 +1,15 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ gcc libc6-dev ca-certificates \ gcc-mips-linux-gnu libc6-dev-mips-cross \ - binfmt-support qemu-user-static qemu-system-mips + binfmt-support qemu-user qemu-system-mips ENV TOOLCHAIN_PREFIX=mips-linux-gnu- ENV CARGO_TARGET_MIPS_UNKNOWN_LINUX_GNU_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_MIPS_UNKNOWN_LINUX_GNU_RUNNER=qemu-mips-static \ + CARGO_TARGET_MIPS_UNKNOWN_LINUX_GNU_RUNNER=qemu-mips \ AR_mips_unknown_linux_gnu="$TOOLCHAIN_PREFIX"ar \ CC_mips_unknown_linux_gnu="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/mips-linux-gnu \ diff --git a/library/compiler-builtins/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile b/library/compiler-builtins/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile index 4e542ce6858c3..c20d0a77b81c3 100644 --- a/library/compiler-builtins/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile +++ b/library/compiler-builtins/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ @@ -8,12 +8,12 @@ RUN apt-get update && \ gcc-mips64-linux-gnuabi64 \ libc6-dev \ libc6-dev-mips64-cross \ - qemu-user-static \ + qemu-user \ qemu-system-mips ENV TOOLCHAIN_PREFIX=mips64-linux-gnuabi64- ENV CARGO_TARGET_MIPS64_UNKNOWN_LINUX_GNUABI64_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_MIPS64_UNKNOWN_LINUX_GNUABI64_RUNNER=qemu-mips64-static \ + CARGO_TARGET_MIPS64_UNKNOWN_LINUX_GNUABI64_RUNNER=qemu-mips64 \ AR_mips64_unknown_linux_gnuabi64="$TOOLCHAIN_PREFIX"ar \ CC_mips64_unknown_linux_gnuabi64="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/mips64-linux-gnuabi64 \ diff --git a/library/compiler-builtins/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile b/library/compiler-builtins/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile index 528dfd8940d5e..584f7ffff45a5 100644 --- a/library/compiler-builtins/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile +++ b/library/compiler-builtins/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ @@ -8,11 +8,11 @@ RUN apt-get update && \ gcc-mips64el-linux-gnuabi64 \ libc6-dev \ libc6-dev-mips64el-cross \ - qemu-user-static + qemu-user ENV TOOLCHAIN_PREFIX=mips64el-linux-gnuabi64- ENV CARGO_TARGET_MIPS64EL_UNKNOWN_LINUX_GNUABI64_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_MIPS64EL_UNKNOWN_LINUX_GNUABI64_RUNNER=qemu-mips64el-static \ + CARGO_TARGET_MIPS64EL_UNKNOWN_LINUX_GNUABI64_RUNNER=qemu-mips64el \ AR_mips64el_unknown_linux_gnuabi64="$TOOLCHAIN_PREFIX"ar \ CC_mips64el_unknown_linux_gnuabi64="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/mips64el-linux-gnuabi64 \ diff --git a/library/compiler-builtins/ci/docker/mipsel-unknown-linux-gnu/Dockerfile b/library/compiler-builtins/ci/docker/mipsel-unknown-linux-gnu/Dockerfile index 2572180238e23..ead99bb9c1132 100644 --- a/library/compiler-builtins/ci/docker/mipsel-unknown-linux-gnu/Dockerfile +++ b/library/compiler-builtins/ci/docker/mipsel-unknown-linux-gnu/Dockerfile @@ -1,15 +1,15 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ gcc libc6-dev ca-certificates \ gcc-mipsel-linux-gnu libc6-dev-mipsel-cross \ - binfmt-support qemu-user-static + binfmt-support qemu-user ENV TOOLCHAIN_PREFIX=mipsel-linux-gnu- ENV CARGO_TARGET_MIPSEL_UNKNOWN_LINUX_GNU_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_MIPSEL_UNKNOWN_LINUX_GNU_RUNNER=qemu-mipsel-static \ + CARGO_TARGET_MIPSEL_UNKNOWN_LINUX_GNU_RUNNER=qemu-mipsel \ AR_mipsel_unknown_linux_gnu="$TOOLCHAIN_PREFIX"ar \ CC_mipsel_unknown_linux_gnu="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/mipsel-linux-gnu \ diff --git a/library/compiler-builtins/ci/docker/powerpc-unknown-linux-gnu/Dockerfile b/library/compiler-builtins/ci/docker/powerpc-unknown-linux-gnu/Dockerfile index cac1f23610aa9..74071874ed7cf 100644 --- a/library/compiler-builtins/ci/docker/powerpc-unknown-linux-gnu/Dockerfile +++ b/library/compiler-builtins/ci/docker/powerpc-unknown-linux-gnu/Dockerfile @@ -1,15 +1,15 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ - gcc libc6-dev qemu-user-static ca-certificates \ + gcc libc6-dev qemu-user ca-certificates \ gcc-powerpc-linux-gnu libc6-dev-powerpc-cross \ qemu-system-ppc ENV TOOLCHAIN_PREFIX=powerpc-linux-gnu- ENV CARGO_TARGET_POWERPC_UNKNOWN_LINUX_GNU_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_POWERPC_UNKNOWN_LINUX_GNU_RUNNER=qemu-ppc-static \ + CARGO_TARGET_POWERPC_UNKNOWN_LINUX_GNU_RUNNER=qemu-ppc \ AR_powerpc_unknown_linux_gnu="$TOOLCHAIN_PREFIX"ar \ CC_powerpc_unknown_linux_gnu="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/powerpc-linux-gnu \ diff --git a/library/compiler-builtins/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile b/library/compiler-builtins/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile index 76127b7dbb8c1..ba4fec7160b64 100644 --- a/library/compiler-builtins/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile +++ b/library/compiler-builtins/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile @@ -1,15 +1,15 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ gcc libc6-dev ca-certificates \ gcc-powerpc64-linux-gnu libc6-dev-ppc64-cross \ - binfmt-support qemu-user-static qemu-system-ppc + binfmt-support qemu-user qemu-system-ppc ENV TOOLCHAIN_PREFIX=powerpc64-linux-gnu- ENV CARGO_TARGET_POWERPC64_UNKNOWN_LINUX_GNU_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_POWERPC64_UNKNOWN_LINUX_GNU_RUNNER=qemu-ppc64-static \ + CARGO_TARGET_POWERPC64_UNKNOWN_LINUX_GNU_RUNNER=qemu-ppc64 \ AR_powerpc64_unknown_linux_gnu="$TOOLCHAIN_PREFIX"ar \ CC_powerpc64_unknown_linux_gnu="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/powerpc64-linux-gnu \ diff --git a/library/compiler-builtins/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile b/library/compiler-builtins/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile index da1d56ca66f27..e90d4c8812042 100644 --- a/library/compiler-builtins/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile +++ b/library/compiler-builtins/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile @@ -1,15 +1,15 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ - gcc libc6-dev qemu-user-static ca-certificates \ + gcc libc6-dev qemu-user ca-certificates \ gcc-powerpc64le-linux-gnu libc6-dev-ppc64el-cross \ qemu-system-ppc ENV TOOLCHAIN_PREFIX=powerpc64le-linux-gnu- ENV CARGO_TARGET_POWERPC64LE_UNKNOWN_LINUX_GNU_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_POWERPC64LE_UNKNOWN_LINUX_GNU_RUNNER=qemu-ppc64le-static \ + CARGO_TARGET_POWERPC64LE_UNKNOWN_LINUX_GNU_RUNNER=qemu-ppc64le \ AR_powerpc64le_unknown_linux_gnu="$TOOLCHAIN_PREFIX"ar \ CC_powerpc64le_unknown_linux_gnu="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/powerpc64le-linux-gnu \ diff --git a/library/compiler-builtins/ci/docker/riscv64gc-unknown-linux-gnu/Dockerfile b/library/compiler-builtins/ci/docker/riscv64gc-unknown-linux-gnu/Dockerfile index 513efacd6d968..96442121bcd9e 100644 --- a/library/compiler-builtins/ci/docker/riscv64gc-unknown-linux-gnu/Dockerfile +++ b/library/compiler-builtins/ci/docker/riscv64gc-unknown-linux-gnu/Dockerfile @@ -1,15 +1,15 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ - gcc libc6-dev qemu-user-static ca-certificates \ + gcc libc6-dev qemu-user ca-certificates \ gcc-riscv64-linux-gnu libc6-dev-riscv64-cross \ - qemu-system-riscv64 + qemu-system-riscv ENV TOOLCHAIN_PREFIX=riscv64-linux-gnu- ENV CARGO_TARGET_RISCV64GC_UNKNOWN_LINUX_GNU_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_RISCV64GC_UNKNOWN_LINUX_GNU_RUNNER=qemu-riscv64-static \ + CARGO_TARGET_RISCV64GC_UNKNOWN_LINUX_GNU_RUNNER=qemu-riscv64 \ AR_riscv64gc_unknown_linux_gnu="$TOOLCHAIN_PREFIX"ar \ CC_riscv64gc_unknown_linux_gnu="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/riscv64-linux-gnu \ diff --git a/library/compiler-builtins/ci/docker/thumbv6m-none-eabi/Dockerfile b/library/compiler-builtins/ci/docker/thumbv6m-none-eabi/Dockerfile index a9a172a21137d..463cce94e5540 100644 --- a/library/compiler-builtins/ci/docker/thumbv6m-none-eabi/Dockerfile +++ b/library/compiler-builtins/ci/docker/thumbv6m-none-eabi/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/library/compiler-builtins/ci/docker/thumbv7em-none-eabi/Dockerfile b/library/compiler-builtins/ci/docker/thumbv7em-none-eabi/Dockerfile index a9a172a21137d..463cce94e5540 100644 --- a/library/compiler-builtins/ci/docker/thumbv7em-none-eabi/Dockerfile +++ b/library/compiler-builtins/ci/docker/thumbv7em-none-eabi/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/library/compiler-builtins/ci/docker/thumbv7em-none-eabihf/Dockerfile b/library/compiler-builtins/ci/docker/thumbv7em-none-eabihf/Dockerfile index a9a172a21137d..463cce94e5540 100644 --- a/library/compiler-builtins/ci/docker/thumbv7em-none-eabihf/Dockerfile +++ b/library/compiler-builtins/ci/docker/thumbv7em-none-eabihf/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/library/compiler-builtins/ci/docker/thumbv7m-none-eabi/Dockerfile b/library/compiler-builtins/ci/docker/thumbv7m-none-eabi/Dockerfile index a9a172a21137d..463cce94e5540 100644 --- a/library/compiler-builtins/ci/docker/thumbv7m-none-eabi/Dockerfile +++ b/library/compiler-builtins/ci/docker/thumbv7m-none-eabi/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/library/compiler-builtins/ci/docker/wasm32-unknown-unknown/Dockerfile b/library/compiler-builtins/ci/docker/wasm32-unknown-unknown/Dockerfile index 2813d318670ea..09f35c3b128d0 100644 --- a/library/compiler-builtins/ci/docker/wasm32-unknown-unknown/Dockerfile +++ b/library/compiler-builtins/ci/docker/wasm32-unknown-unknown/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:20.04 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/library/compiler-builtins/ci/docker/x86_64-unknown-linux-gnu/Dockerfile b/library/compiler-builtins/ci/docker/x86_64-unknown-linux-gnu/Dockerfile index 2ef800129d675..103c395ee8496 100644 --- a/library/compiler-builtins/ci/docker/x86_64-unknown-linux-gnu/Dockerfile +++ b/library/compiler-builtins/ci/docker/x86_64-unknown-linux-gnu/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/library/compiler-builtins/ci/download-compiler-rt.sh b/library/compiler-builtins/ci/download-compiler-rt.sh index bf7f8c2489643..55498c61d54b4 100755 --- a/library/compiler-builtins/ci/download-compiler-rt.sh +++ b/library/compiler-builtins/ci/download-compiler-rt.sh @@ -4,7 +4,13 @@ set -eux -rust_llvm_version=20.1-2025-02-13 +rust_llvm_version=23.1-2026-07-22 -curl -L -o code.tar.gz "https://github.com/rust-lang/llvm-project/archive/rustc/${rust_llvm_version}.tar.gz" +curl -L --retry 3 -o code.tar.gz "https://github.com/rust-lang/llvm-project/archive/rustc/${rust_llvm_version}.tar.gz" tar xzf code.tar.gz --strip-components 1 llvm-project-rustc-${rust_llvm_version}/compiler-rt + +cd compiler-rt + +for p in ../ci/compiler-rt-patches/*; do + cat "$p" | patch -p 2 +done diff --git a/library/compiler-builtins/ci/install-bench-deps.sh b/library/compiler-builtins/ci/install-bench-deps.sh index 61f4723c0358d..7d73ed0d32f55 100755 --- a/library/compiler-builtins/ci/install-bench-deps.sh +++ b/library/compiler-builtins/ci/install-bench-deps.sh @@ -1,10 +1,22 @@ -#!/bin/sh +#!/bin/bash # Install needed dependencies for gungraun. +set -eux + +target="${1:-}" + +# Needed for gungraun +deps=(valgrind gdb libc6-dbg) + +[[ "$target" = *"i686"* ]] && deps+=(gcc-multilib) + sudo apt-get update -sudo apt-get install -y valgrind gdb libc6-dbg # Needed for gungraun +sudo apt-get install -y "${deps[@]}" + rustup update "$BENCHMARK_RUSTC" --no-self-update rustup default "$BENCHMARK_RUSTC" +[ -n "$target" ] && rustup target add "$target" + # Install the version of gungraun-runner that is specified in Cargo.toml gungraun_version="$(cargo metadata --format-version=1 --features icount | jq -r '.packages[] | select(.name == "gungraun").version')" diff --git a/library/compiler-builtins/ci/miri.sh b/library/compiler-builtins/ci/miri.sh index 7b0ea44c690f3..498bbe3c47f00 100755 --- a/library/compiler-builtins/ci/miri.sh +++ b/library/compiler-builtins/ci/miri.sh @@ -1,11 +1,13 @@ #!/bin/bash set -eux +# We need to disable the randomness that Miri intentionally introduces when +# performing floating-point operations # We need Tree Borrows as some of our raw pointer patterns are not # compatible with Stacked Borrows. -export MIRIFLAGS="-Zmiri-tree-borrows" +export MIRIFLAGS="-Zmiri-deterministic-floats -Zmiri-tree-borrows" -# One target that sets `mem-unaligned` and one that does not, +# One target that sets `mem_unaligned` and one that does not, # and a big-endian target. targets=( x86_64-unknown-linux-gnu @@ -13,6 +15,17 @@ targets=( s390x-unknown-linux-gnu ) for target in "${targets[@]}"; do - # Only run the `mem` tests to avoid this taking too long. - cargo miri test --manifest-path builtins-test/Cargo.toml --features no-asm --target "$target" -- mem + # Only run the `mem` tests to avoid this taking too long. Disable default + # features to turn off `arch` and avoid inline assembly. + cargo miri test \ + --manifest-path builtins-test/Cargo.toml \ + --no-default-features \ + --target "$target" \ + -- mem + + # Run the `libm` tests as well, but not `libm-test` to avoid this taking + # too long. + cargo miri test \ + --manifest-path libm/Cargo.toml \ + --target "$target" done diff --git a/library/compiler-builtins/ci/run-docker.sh b/library/compiler-builtins/ci/run-docker.sh index 4c1fe0fe26445..08f20b934acd5 100755 --- a/library/compiler-builtins/ci/run-docker.sh +++ b/library/compiler-builtins/ci/run-docker.sh @@ -11,8 +11,6 @@ host_arch="$(uname -m | sed 's/arm64/aarch64/')" # calling docker, otherwise docker will create them but they will be owned # by root. mkdir -p target -cargo generate-lockfile -cargo generate-lockfile --manifest-path builtins-test-intrinsics/Cargo.toml run() { local target="$1" @@ -78,6 +76,7 @@ run() { -e CI \ -e CARGO_TARGET_DIR=/builtins-target \ -e CARGO_TERM_COLOR \ + -e LIBM_BUILD_VERBOSE \ -e MAY_SKIP_LIBM_CI \ -e RUSTFLAGS \ -e RUST_BACKTRACE \ @@ -97,7 +96,7 @@ if [ "${1:-}" = "--help" ] || [ "$#" -gt 1 ]; then usage: ./ci/run-docker.sh [target] you can also set DOCKER_BASE_IMAGE to use something other than the default - ubuntu:25.04 (or rustlang/rust:nightly). + ubuntu:26.04 (or rustlang/rust:nightly). " exit fi diff --git a/library/compiler-builtins/ci/run-extensive.sh b/library/compiler-builtins/ci/run-extensive.sh index 4ba41a026fab6..9bdf8bcfbadcc 100755 --- a/library/compiler-builtins/ci/run-extensive.sh +++ b/library/compiler-builtins/ci/run-extensive.sh @@ -14,7 +14,15 @@ set -x test_cmd=( cargo test --package libm-test - --features "build-mpfr,libm/unstable,libm/force-soft-floats" + --no-default-features + # Don't enable `arch` for extensive tests. Usually anything in asm is + # only a single instruction or a small sequence, and we rely on the + # vendors to test that for us. + # + # libm/unstable enables libm/unstable-intrinsics, which means we usually + # get the single-instruction ops anyway when we aren't specifically + # testing for them. + --features "libm-test/build-mpfr libm-test/unstable-float libm/unstable" --profile release-checked ) diff --git a/library/compiler-builtins/ci/run.sh b/library/compiler-builtins/ci/run.sh index 0c07b32c74b93..359bf3d945b9b 100755 --- a/library/compiler-builtins/ci/run.sh +++ b/library/compiler-builtins/ci/run.sh @@ -13,10 +13,11 @@ if [ -z "$target" ]; then target="$host_target" fi -if [[ "$target" = *"wasm"* ]]; then - # Enable the random backend - export RUSTFLAGS="${RUSTFLAGS:-} --cfg getrandom_backend=\"wasm_js\"" -fi +# Print machine information +uname -a +lscpu || true +rustc -Vv +cc -v || true if [ "${USING_CONTAINER_RUSTC:-}" = 1 ]; then # Install nonstandard components if we have control of the environment @@ -25,19 +26,45 @@ if [ "${USING_CONTAINER_RUSTC:-}" = 1 ]; then rustup target add "$target" fi +# If nextest is available, use that +command -v cargo-nextest && nextest=1 || nextest=0 +if [ "$nextest" = "1" ]; then + test_runner=(cargo nextest run --max-fail=20) + profile_flag="--cargo-profile" + + # Workaround for https://github.com/nextest-rs/nextest/issues/2066 + if [ -n "${CARGO_TARGET_DIR:-}" ]; then + cfg_file="/tmp/nextest-config.toml" + echo "[store]" >> "$cfg_file" + echo "dir = \"$CARGO_TARGET_DIR/nextest\"" >> "$cfg_file" + test_runner+=(--config-file "$cfg_file") + fi + + # Not all configurations have tests to run on wasm + [[ "$target" = *"wasm"* ]] && test_runner+=(--no-tests=warn) +else + test_runner=(cargo test --no-fail-fast) + profile_flag="--profile" +fi + # Test our implementation if [ "${BUILD_ONLY:-}" = "1" ]; then echo "no tests to run for build-only targets" else - test_builtins=(cargo test --package builtins-test --no-fail-fast --target "$target") + test_builtins=( + "${test_runner[@]}" + --package builtins-test + --target "$target" + ) + "${test_builtins[@]}" "${test_builtins[@]}" --release "${test_builtins[@]}" --features c "${test_builtins[@]}" --features c --release - "${test_builtins[@]}" --features no-asm - "${test_builtins[@]}" --features no-asm --release "${test_builtins[@]}" --benches "${test_builtins[@]}" --benches --release + "${test_builtins[@]}" --no-default-features + "${test_builtins[@]}" --no-default-features --release # Validate that having a verbatim path for the target directory works # (trivial to regress using `/` in paths to build artifacts rather than @@ -51,23 +78,28 @@ fi # Ensure there are no duplicate symbols or references to `core` when # `compiler-builtins` is built with various features. Symcheck invokes Cargo to # build with the arguments we provide it, then validates the built artifacts. -symcheck=(cargo run -p symbol-check --release) -[[ "$target" = "wasm"* ]] && symcheck+=(--features wasm) -symcheck+=(-- build-and-check) - -"${symcheck[@]}" "$target" -- -p compiler_builtins -"${symcheck[@]}" "$target" -- -p compiler_builtins --release -"${symcheck[@]}" "$target" -- -p compiler_builtins --features c -"${symcheck[@]}" "$target" -- -p compiler_builtins --features c --release -"${symcheck[@]}" "$target" -- -p compiler_builtins --features no-asm -"${symcheck[@]}" "$target" -- -p compiler_builtins --features no-asm --release +SYMCHECK_TEST_TARGET="$target" cargo test -p symcheck --release +symcheck=(cargo run -p symcheck --release) +symcheck+=(-- --build-and-check --target "$target") + +# Executable section checks are meaningless on no-std targets +[[ "$target" == *"-none"* ]] && symcheck+=(--no-os) + +# We only need to check the configurations std may use +symcheck_cb_args=(-- --package compiler_builtins --features compiler-builtins) +"${symcheck[@]}" "${symcheck_cb_args[@]}" +"${symcheck[@]}" "${symcheck_cb_args[@]}" --release +"${symcheck[@]}" "${symcheck_cb_args[@]}" --features c +"${symcheck[@]}" "${symcheck_cb_args[@]}" --features c --release +"${symcheck[@]}" "${symcheck_cb_args[@]}" --no-default-features +"${symcheck[@]}" "${symcheck_cb_args[@]}" --no-default-features --release run_intrinsics_test() { build_args=(--verbose --manifest-path builtins-test-intrinsics/Cargo.toml) build_args+=("$@") # symcheck also checks the results of builtins-test-intrinsics - "${symcheck[@]}" "$target" -- "${build_args[@]}" + "${symcheck[@]}" -- "${build_args[@]}" # FIXME: we get access violations on Windows, our entrypoint may need to # be tweaked. @@ -102,13 +134,13 @@ mflags=() # We enumerate features manually. mflags+=(--no-default-features) -# Enable arch-specific routines when available. -mflags+=(--features arch) - # Always enable `unstable-float` since it expands available API but does not # change any implementations. mflags+=(--features unstable-float) +# This is a host program that may not run in containers. +mflags+=(--exclude update-api-list) + # We need to specifically skip tests for musl-math-sys on systems that can't # build musl since otherwise `--all` will activate it. case "$target" in @@ -119,10 +151,6 @@ case "$target" in # We can build musl on MinGW but running tests gets a stack overflow *windows-gnu*) ;; - # FIXME(#309): LE PPC crashes calling the musl version of some functions. It - # seems like a qemu bug but should be investigated further at some point. - # See . - *powerpc64le*) ;; # Everything else gets musl enabled *) mflags+=(--features libm-test/build-musl) ;; @@ -157,29 +185,9 @@ if [ "${BUILD_ONLY:-}" = "1" ]; then echo "can't run tests on $target; skipping" else - mflags+=(--workspace --target "$target") - cmd=(cargo test "${mflags[@]}") - profile_flag="--profile" - - # If nextest is available, use that - command -v cargo-nextest && nextest=1 || nextest=0 - if [ "$nextest" = "1" ]; then - cmd=(cargo nextest run --max-fail=10) - - # Workaround for https://github.com/nextest-rs/nextest/issues/2066 - if [ -f /.dockerenv ]; then - cfg_file="/tmp/nextest-config.toml" - echo "[store]" >> "$cfg_file" - echo "dir = \"$CARGO_TARGET_DIR/nextest\"" >> "$cfg_file" - cmd+=(--config-file "$cfg_file") - fi - - # Not all configurations have tests to run on wasm - [[ "$target" = *"wasm"* ]] && cmd+=(--no-tests=warn) - - cmd+=("${mflags[@]}") - profile_flag="--cargo-profile" - fi + # symcheck tests need specific env setup, and is already tested above + mflags+=(--workspace --exclude symcheck --target "$target") + cmd=("${test_runner[@]}" "${mflags[@]}") # Test once without intrinsics "${cmd[@]}" @@ -192,15 +200,15 @@ else cmd+=(--exclude util --exclude libm-macros) # Test once with intrinsics enabled - "${cmd[@]}" --features unstable-intrinsics - "${cmd[@]}" --features unstable-intrinsics --benches + "${cmd[@]}" --features arch,unstable-intrinsics + "${cmd[@]}" --features arch,unstable-intrinsics --benches # Test the same in release mode, which also increases coverage. Also ensure # the soft float routines are checked. "${cmd[@]}" "$profile_flag" release-checked - "${cmd[@]}" "$profile_flag" release-checked --features force-soft-floats - "${cmd[@]}" "$profile_flag" release-checked --features unstable-intrinsics - "${cmd[@]}" "$profile_flag" release-checked --features unstable-intrinsics --benches + "${cmd[@]}" "$profile_flag" release-checked --features arch + "${cmd[@]}" "$profile_flag" release-checked --features arch,unstable-intrinsics + "${cmd[@]}" "$profile_flag" release-checked --features arch,unstable-intrinsics --benches # Ensure that the routines do not panic. # diff --git a/library/compiler-builtins/compiler-builtins/Cargo.toml b/library/compiler-builtins/compiler-builtins/Cargo.toml index 496dde2d4cf25..b2f1443f2eb09 100644 --- a/library/compiler-builtins/compiler-builtins/Cargo.toml +++ b/library/compiler-builtins/compiler-builtins/Cargo.toml @@ -31,32 +31,31 @@ doc = false core = { path = "../../core", optional = true } [build-dependencies] -cc = { optional = true, version = "1.2" } +cc = { version = "1.2", optional = true } [features] -default = ["compiler-builtins"] +default = ["arch"] + +# Enable architecture-specific features such as SIMD or assembly routines. If +# disabled, the generic version can be tested on any platform. +arch = [] # Enable compilation of C code in compiler-rt, filling in some more optimized # implementations and also filling in unimplemented intrinsics c = ["dep:cc"] -# For implementations where there is both a generic version and a platform- -# specific version, use the generic version. This is meant to enable testing -# the generic versions on all platforms. -no-asm = [] - -# Flag this library as the unstable compiler-builtins lib -compiler-builtins = [] +# Flag this library as the unstable compiler-builtins lib. This must be enabled +# when using as `std`'s dependency.' +compiler-builtins = ["dep:core", "unmangled-names"] -# Generate memory-related intrinsics like memcpy +# Enable `no_mangle` symbols for memory-related intrinsics like memcpy. The +# mangled versions are always available. mem = [] -# Mangle all names so this can be linked in with other versions or other -# compiler-rt implementations. Also used for testing -mangled-names = [] - -# Only used in the compiler's build system -rustc-dep-of-std = ["compiler-builtins", "dep:core"] +# Enable `no_mangle` symbols so this crate gets used as the runtime intrinsic +# implementation. Leave this disabled for testing to avoid conflicting with +# the system intrinsics. +unmangled-names = [] # This makes certain traits and function specializations public that # are not normally public but are required by the `builtins-test` diff --git a/library/compiler-builtins/compiler-builtins/README.md b/library/compiler-builtins/compiler-builtins/README.md index a12bd2ee73499..63cbf33d2aea2 100644 --- a/library/compiler-builtins/compiler-builtins/README.md +++ b/library/compiler-builtins/compiler-builtins/README.md @@ -22,7 +22,7 @@ See `build.rs` for details. ## Contributing -See [CONTRIBUTING.md](CONTRIBUTING.md). +See [CONTRIBUTING.md](../CONTRIBUTING.md). ## Progress diff --git a/library/compiler-builtins/compiler-builtins/build.rs b/library/compiler-builtins/compiler-builtins/build.rs index 6e1d230e3cd26..8869add9f5ee4 100644 --- a/library/compiler-builtins/compiler-builtins/build.rs +++ b/library/compiler-builtins/compiler-builtins/build.rs @@ -1,120 +1,88 @@ +#[path = "../libm/configure.rs"] mod configure; use std::env; -use configure::{Target, configure_aliases}; +use configure::{Config, Library, set_cfg}; fn main() { - println!("cargo::rerun-if-changed=build.rs"); - println!("cargo::rerun-if-changed=configure.rs"); + let cfg = Config::from_env(Library::CompilerBuiltins); + let llvm_target = &cfg.target_triple_split; + + // Work around building as part of `builtins-shim`: if only `build.rs` is used, Cargo always + // considers the build dirty because `builtins-shim/build.rs` does not exist. If only + // `../c-b/build.rs` is used, the same may happen if not built in the workspace. + // Note: this may be `None` if CARGO_MANIFEST_DIR doesn't end in a directory name (e.g. ".") + if let Some(dir) = cfg.manifest_dir.file_name() + && dir == "builtins-shim" + { + println!("cargo::rerun-if-changed=../compiler-builtins/build.rs"); + } else { + println!("cargo::rerun-if-changed=build.rs"); + } - let target = Target::from_env(); - let cwd = env::current_dir().unwrap(); + println!("cargo::rerun-if-changed=../libm/configure.rs"); + configure::emit(&cfg); configure_check_cfg(); - configure_aliases(&target); - - configure_libm(&target); + let cwd = env::current_dir().unwrap(); println!("cargo:compiler-rt={}", cwd.join("compiler-rt").display()); - println!("cargo::rustc-check-cfg=cfg(kernel_user_helpers)"); - println!("cargo::rustc-check-cfg=cfg(feature, values(\"mem-unaligned\"))"); - - // Emscripten's runtime includes all the builtins - if target.os == "emscripten" { - return; - } - - // OpenBSD provides compiler_rt by default, use it instead of rebuilding it from source - if target.os == "openbsd" { - println!("cargo:rustc-link-search=native=/usr/lib"); - println!("cargo:rustc-link-lib=compiler_rt"); - return; - } - // Forcibly enable memory intrinsics on wasm & SGX as we don't have a libc to // provide them. - if (target.triple.contains("wasm") && !target.triple.contains("wasi")) - || (target.triple.contains("sgx") && target.triple.contains("fortanix")) - || target.triple.contains("-none") - || target.triple.contains("nvptx") - || target.triple.contains("uefi") - || target.triple.contains("xous") + if (cfg.target_triple.contains("wasm") && !cfg.target_triple.contains("wasi")) + || (cfg.target_triple.contains("sgx") && cfg.target_triple.contains("fortanix")) + || cfg.target_triple.contains("-none") + || cfg.target_triple.contains("nvptx") + || cfg.target_triple.contains("uefi") + || cfg.target_triple.contains("xous") { println!("cargo:rustc-cfg=feature=\"mem\""); } // These targets have hardware unaligned access support. - if target.arch.contains("x86_64") - || target.arch.contains("x86") - || target.arch.contains("aarch64") - || target.arch.contains("bpf") - { - println!("cargo:rustc-cfg=feature=\"mem-unaligned\""); - } - - // NOTE we are going to assume that llvm-target, what determines our codegen option, matches the - // target triple. This is usually correct for our built-in targets but can break in presence of - // custom targets, which can have arbitrary names. - let llvm_target = target.triple.split('-').collect::>(); - - // Build missing intrinsics from compiler-rt C source code. If we're - // mangling names though we assume that we're also in test mode so we don't - // build anything and we rely on the upstream implementation of compiler-rt - // functions - if !cfg!(feature = "mangled-names") && cfg!(feature = "c") { - // Don't use a C compiler for these targets: - // - // * nvptx - everything is bitcode, not compatible with mixed C/Rust - if !target.arch.contains("nvptx") { - #[cfg(feature = "c")] - c::compile(&llvm_target, &target); - } - } + let mem_unaligned = cfg.target_arch.contains("x86_64") + || cfg.target_arch.contains("x86") + || cfg.target_arch.contains("aarch64") + || cfg.target_arch.contains("bpf"); + set_cfg("mem_unaligned", mem_unaligned); // Only emit the ARM Linux atomic emulation on pre-ARMv6 architectures. This // includes the old androideabi. It is deprecated but it is available as a // rustc target (arm-linux-androideabi). - if llvm_target[0] == "armv4t" + let kernel_user_helpers = llvm_target[0] == "armv4t" || llvm_target[0] == "armv5te" - || target.triple == "arm-linux-androideabi" - { - println!("cargo:rustc-cfg=kernel_user_helpers") - } -} + || cfg.target_triple == "arm-linux-androideabi"; + set_cfg("kernel_user_helpers", kernel_user_helpers); -/// Run configuration for `libm` since it is included directly. -/// -/// Much of this is copied from `libm/configure.rs`. -fn configure_libm(target: &Target) { - println!("cargo:rustc-check-cfg=cfg(intrinsics_enabled)"); - println!("cargo:rustc-check-cfg=cfg(arch_enabled)"); - println!("cargo:rustc-check-cfg=cfg(optimizations_enabled)"); - println!("cargo:rustc-check-cfg=cfg(feature, values(\"unstable-public-internals\"))"); - - // Always use intrinsics - println!("cargo:rustc-cfg=intrinsics_enabled"); - - // The arch module may contain assembly. - if !cfg!(feature = "no-asm") { - println!("cargo:rustc-cfg=arch_enabled"); + let mut maybe_build_c = true; + + // Emscripten's runtime includes all the builtins + if cfg.target_os == "emscripten" { + maybe_build_c = false; } - println!("cargo:rustc-check-cfg=cfg(optimizations_enabled)"); - if !matches!(target.opt_level.as_str(), "0" | "1") { - println!("cargo:rustc-cfg=optimizations_enabled"); + // OpenBSD provides compiler_rt by default, use it instead of rebuilding it from source + if cfg.target_os == "openbsd" { + println!("cargo:rustc-link-search=native=/usr/lib"); + println!("cargo:rustc-link-lib=compiler_rt"); + maybe_build_c = false; } - println!( - "cargo:rustc-env=CFG_CARGO_FEATURES={:?}", - target.cargo_features - ); - println!("cargo:rustc-env=CFG_OPT_LEVEL={}", target.opt_level); - println!("cargo:rustc-env=CFG_TARGET_FEATURES={:?}", target.features); + // Everything is LLVM bitcode, not compatible with mixed C/Rust + if cfg.target_arch.contains("nvptx") { + maybe_build_c = false; + } - // Activate libm's unstable features to make full use of Nightly. - println!("cargo:rustc-cfg=feature=\"unstable-intrinsics\""); + // Build missing intrinsics from compiler-rt C source code. If we're + // mangling names though we assume that we're also in test mode so we don't + // build anything and we rely on the upstream implementation of compiler-rt + // functions + if cfg!(feature = "unmangled-names") && cfg!(feature = "c") && maybe_build_c { + #[cfg(feature = "c")] + c::compile(&cfg); + } } /// Emit directives for features we expect to support that aren't in `Cargo.toml`. @@ -176,10 +144,6 @@ fn configure_check_cfg() { // Rustc is unaware of sparc target features, but this does show up from // `rustc --print target-features --target sparc64-unknown-linux-gnu`. println!("cargo::rustc-check-cfg=cfg(target_feature, values(\"vis3\"))"); - - // FIXME: these come from libm and should be changed there - println!("cargo::rustc-check-cfg=cfg(feature, values(\"checked\"))"); - println!("cargo::rustc-check-cfg=cfg(assert_no_panic)"); } #[cfg(feature = "c")] @@ -190,7 +154,7 @@ mod c { use std::io::Write; use std::path::{Path, PathBuf}; - use super::Target; + use super::Config; struct Sources { // SYMBOL -> PATH TO SOURCE @@ -232,17 +196,18 @@ mod c { } /// Compile intrinsics from the compiler-rt C source code - pub fn compile(llvm_target: &[&str], target: &Target) { + pub fn compile(cfg: &Config) { + let llvm_target = &cfg.target_triple_split; let mut consider_float_intrinsics = true; - let cfg = &mut cc::Build::new(); + let build = &mut cc::Build::new(); // AArch64 GCCs exit with an error condition when they encounter any kind of floating point // code if the `nofp` and/or `nosimd` compiler flags have been set. // // Therefore, evaluate if those flags are present and set a boolean that causes any // compiler-rt intrinsics that contain floating point source to be excluded for this target. - if target.arch == "aarch64" { - let cflags_key = String::from("CFLAGS_") + &(target.triple.replace("-", "_")); + if cfg.target_arch == "aarch64" { + let cflags_key = String::from("CFLAGS_") + &(cfg.target_triple.replace("-", "_")); if let Ok(cflags_value) = env::var(cflags_key) { if cflags_value.contains("+nofp") || cflags_value.contains("+nosimd") { consider_float_intrinsics = false; @@ -256,22 +221,22 @@ mod c { // support `_Float16` on all targets (whereas Rust does). However, define the macro // anyway to prevent issues like rust#118813 and rust#123885 silently reoccuring if more // `f16` intrinsics get accidentally added here in the future. - cfg.define("COMPILER_RT_HAS_FLOAT16", None); + build.define("COMPILER_RT_HAS_FLOAT16", None); - cfg.warnings(false); + build.warnings(false); - if target.env == "msvc" { + if cfg.target_env == "msvc" { // Don't pull in extra libraries on MSVC - cfg.flag("/Zl"); + build.flag("/Zl"); // Emulate C99 and C++11's __func__ for MSVC prior to 2013 CTP - cfg.define("__func__", Some("__FUNCTION__")); + build.define("__func__", Some("__FUNCTION__")); } else { // Turn off various features of gcc and such, mostly copying // compiler-rt's build system already - cfg.flag("-fno-builtin"); - cfg.flag("-fvisibility=hidden"); - cfg.flag("-ffreestanding"); + build.flag("-fno-builtin"); + build.flag("-fvisibility=hidden"); + build.flag("-ffreestanding"); // Avoid the following warning appearing once **per file**: // clang: warning: optimization flag '-fomit-frame-pointer' is not supported for target 'armv7' [-Wignored-optimization-argument] // @@ -280,17 +245,17 @@ mod c { // `check_cxx_compiler_flag(-fomit-frame-pointer COMPILER_RT_HAS_FOMIT_FRAME_POINTER_FLAG)` // // in https://github.com/rust-lang/compiler-rt/blob/c8fbcb3/cmake/config-ix.cmake#L19. - cfg.flag_if_supported("-fomit-frame-pointer"); - cfg.define("VISIBILITY_HIDDEN", None); + build.flag_if_supported("-fomit-frame-pointer"); + build.define("VISIBILITY_HIDDEN", None); - if let "aarch64" | "arm64ec" = target.arch.as_str() { + if let "aarch64" | "arm64ec" = cfg.target_arch.as_str() { // FIXME(llvm20): Older GCCs on A64 fail to build with // -Werror=implicit-function-declaration due to a compiler-rt bug. // With a newer LLVM we should be able to enable the flag everywhere. // https://github.com/llvm/llvm-project/commit/8aa9d6206ce55bdaaf422839c351fbd63f033b89 } else { // Avoid implicitly creating references to undefined functions - cfg.flag("-Werror=implicit-function-declaration"); + build.flag("-Werror=implicit-function-declaration"); } } @@ -299,14 +264,14 @@ mod c { // at odds with compiling with `-ffreestanding`, as the header // may be incompatible or not present. Create a minimal stub // header to use instead. - if target.os == "uefi" { + if cfg.target_os == "uefi" { let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap()); let include_dir = out_dir.join("include"); if !include_dir.exists() { fs::create_dir(&include_dir).unwrap(); } fs::write(include_dir.join("stdlib.h"), "#include ").unwrap(); - cfg.flag(&format!("-I{}", include_dir.to_str().unwrap())); + build.flag(&format!("-I{}", include_dir.to_str().unwrap())); } let mut sources = Sources::new(); @@ -344,7 +309,7 @@ mod c { // On iOS and 32-bit OSX these are all just empty intrinsics, no need to // include them. - if target.vendor != "apple" || target.arch != "x86" { + if cfg.target_vendor != "apple" || cfg.target_arch != "x86" { sources.extend(&[ ("__absvti2", "absvti2.c"), ("__addvti3", "addvti3.c"), @@ -363,7 +328,7 @@ mod c { } } - if target.vendor == "apple" { + if cfg.target_vendor == "apple" { sources.extend(&[ ("atomic_flag_clear", "atomic_flag_clear.c"), ("atomic_flag_clear_explicit", "atomic_flag_clear_explicit.c"), @@ -377,8 +342,8 @@ mod c { ]); } - if target.env != "msvc" { - if target.arch == "x86" { + if cfg.target_env != "msvc" { + if cfg.target_arch == "x86" { sources.extend(&[ ("__ashldi3", "i386/ashldi3.S"), ("__ashrdi3", "i386/ashrdi3.S"), @@ -392,11 +357,15 @@ mod c { } } - if target.arch == "arm" && target.vendor != "apple" && target.env != "msvc" { + if cfg.target_arch == "arm" && cfg.target_vendor != "apple" && cfg.target_env != "msvc" { sources.extend(&[ ("__aeabi_div0", "arm/aeabi_div0.c"), ("__aeabi_drsub", "arm/aeabi_drsub.c"), ("__aeabi_frsub", "arm/aeabi_frsub.c"), + ("__aeabi_uread4", "arm/aeabi_uread4.S"), + ("__aeabi_uread8", "arm/aeabi_uread8.S"), + ("__aeabi_uwrite4", "arm/aeabi_uwrite4.S"), + ("__aeabi_uwrite8", "arm/aeabi_uwrite8.S"), ("__bswapdi2", "arm/bswapdi2.S"), ("__bswapsi2", "arm/bswapsi2.S"), ("__divmodsi4", "arm/divmodsi4.S"), @@ -412,7 +381,7 @@ mod c { ("__umodsi3", "arm/umodsi3.S"), ]); - if target.os == "freebsd" { + if cfg.target_os == "freebsd" { sources.extend(&[("__clear_cache", "clear_cache.c")]); } @@ -484,31 +453,36 @@ mod c { ]); } - if (target.arch == "aarch64" || target.arch == "arm64ec") && consider_float_intrinsics { + if (cfg.target_arch == "aarch64" || cfg.target_arch == "arm64ec") + && consider_float_intrinsics + { sources.extend(&[ ("__fe_getround", "fp_mode.c"), ("__fe_raise_inexact", "fp_mode.c"), ]); - if target.os != "windows" && target.os != "cygwin" { + if cfg.target_os != "windows" && cfg.target_os != "cygwin" { sources.extend(&[("__multc3", "multc3.c")]); } } - if target.arch == "mips" || target.arch == "riscv32" || target.arch == "riscv64" { + if cfg.target_arch == "mips" || cfg.target_arch == "riscv32" || cfg.target_arch == "riscv64" + { sources.extend(&[("__bswapsi2", "bswapsi2.c")]); } - if target.arch == "mips64" { + if cfg.target_arch == "mips64" { sources.extend(&[("__fe_getround", "fp_mode.c")]); } - if target.arch == "loongarch64" { + if cfg.target_arch == "loongarch64" { sources.extend(&[("__fe_getround", "fp_mode.c")]); } // Remove the assembly implementations that won't compile for the target - if llvm_target[0] == "thumbv6m" || llvm_target[0] == "thumbv8m.base" || target.os == "uefi" + if llvm_target[0] == "thumbv6m" + || llvm_target[0] == "thumbv8m.base" + || cfg.target_os == "uefi" { let mut to_remove = Vec::new(); for (k, v) in sources.map.iter() { @@ -524,19 +498,19 @@ mod c { } // Android and Cygwin uses emulated TLS so we need a runtime support function. - if target.os == "android" || target.os == "cygwin" { + if cfg.target_os == "android" || cfg.target_os == "cygwin" { sources.extend(&[("__emutls_get_address", "emutls.c")]); } // Work around a bug in the NDK headers (fixed in // https://r.android.com/2038949 which will be released in a future // NDK version) by providing a definition of LONG_BIT. - if target.os == "android" { - cfg.define("LONG_BIT", "(8 * sizeof(long))"); + if cfg.target_os == "android" { + build.define("LONG_BIT", "(8 * sizeof(long))"); } // OpenHarmony also uses emulated TLS. - if target.env == "ohos" { + if cfg.target_env == "ohos" { sources.extend(&[("__emutls_get_address", "emutls.c")]); } @@ -568,16 +542,16 @@ mod c { // Support deterministic builds by remapping the __FILE__ prefix if the // compiler supports it. This fixes the nondeterminism caused by the // use of that macro in lib/builtins/int_util.h in compiler-rt. - cfg.flag_if_supported(&format!("-ffile-prefix-map={}=.", root.display())); + build.flag_if_supported(&format!("-ffile-prefix-map={}=.", root.display())); // Include out-of-line atomics for aarch64, which are all generated by supplying different // sets of flags to the same source file. // Note: Out-of-line aarch64 atomics are not supported by the msvc toolchain (#430) and // on uefi. let src_dir = root.join("lib/builtins"); - if target.arch == "aarch64" && target.env != "msvc" && target.os != "uefi" { + if cfg.target_arch == "aarch64" && cfg.target_env != "msvc" && cfg.target_os != "uefi" { // See below for why we're building these as separate libraries. - build_aarch64_out_of_line_atomics_libraries(&src_dir, cfg, link_against_prebuilt_rt); + build_aarch64_out_of_line_atomics_libraries(&src_dir, build, link_against_prebuilt_rt); // Some run-time CPU feature detection is necessary, as well. let cpu_model_src = if src_dir.join("cpu_model.c").exists() { @@ -592,7 +566,7 @@ mod c { for (sym, src) in sources.map.iter() { let src = src_dir.join(src); if !link_against_prebuilt_rt && added_sources.insert(src.clone()) { - cfg.file(&src); + build.file(&src); println!("cargo:rerun-if-changed={}", src.display()); } println!("cargo:rustc-cfg={}=\"optimized-c\"", sym); @@ -616,7 +590,7 @@ mod c { ); } } else { - cfg.compile("libcompiler-rt.a"); + build.compile("libcompiler-rt.a"); } } diff --git a/library/compiler-builtins/compiler-builtins/configure.rs b/library/compiler-builtins/compiler-builtins/configure.rs deleted file mode 100644 index f16da6b58f812..0000000000000 --- a/library/compiler-builtins/compiler-builtins/configure.rs +++ /dev/null @@ -1,107 +0,0 @@ -// Configuration that is shared between `compiler_builtins` and `builtins_test`. - -use std::{env, str}; - -#[derive(Debug)] -#[allow(dead_code)] -pub struct Target { - pub triple: String, - pub triple_split: Vec, - pub opt_level: String, - pub cargo_features: Vec, - pub os: String, - pub arch: String, - pub vendor: String, - pub env: String, - pub pointer_width: u8, - pub little_endian: bool, - pub features: Vec, - pub reliable_f128: bool, - pub reliable_f16: bool, -} - -impl Target { - pub fn from_env() -> Self { - let triple = env::var("TARGET").unwrap(); - let triple_split = triple.split('-').map(ToOwned::to_owned).collect(); - let little_endian = match env::var("CARGO_CFG_TARGET_ENDIAN").unwrap().as_str() { - "little" => true, - "big" => false, - x => panic!("unknown endian {x}"), - }; - let cargo_features = env::vars() - .filter_map(|(name, _value)| name.strip_prefix("CARGO_FEATURE_").map(ToOwned::to_owned)) - .map(|s| s.to_lowercase().replace("_", "-")) - .collect(); - - Self { - triple, - triple_split, - os: env::var("CARGO_CFG_TARGET_OS").unwrap(), - opt_level: env::var("OPT_LEVEL").unwrap(), - cargo_features, - arch: env::var("CARGO_CFG_TARGET_ARCH").unwrap(), - vendor: env::var("CARGO_CFG_TARGET_VENDOR").unwrap(), - env: env::var("CARGO_CFG_TARGET_ENV").unwrap(), - pointer_width: env::var("CARGO_CFG_TARGET_POINTER_WIDTH") - .unwrap() - .parse() - .unwrap(), - little_endian, - features: env::var("CARGO_CFG_TARGET_FEATURE") - .unwrap_or_default() - .split(",") - .map(ToOwned::to_owned) - .collect(), - // Note that these are unstable options, so only show up with the nightly compiler or - // with `RUSTC_BOOTSTRAP=1` (which is required to use the types anyway). - reliable_f128: env::var_os("CARGO_CFG_TARGET_HAS_RELIABLE_F128").is_some(), - reliable_f16: env::var_os("CARGO_CFG_TARGET_HAS_RELIABLE_F16").is_some(), - } - } - - #[allow(dead_code)] - pub fn has_feature(&self, feature: &str) -> bool { - self.features.iter().any(|f| f == feature) - } -} - -pub fn configure_aliases(target: &Target) { - // To compile builtins-test-intrinsics for thumb targets, where there is no libc - println!("cargo::rustc-check-cfg=cfg(thumb)"); - if target.triple_split[0].starts_with("thumb") { - println!("cargo:rustc-cfg=thumb") - } - - // compiler-rt `cfg`s away some intrinsics for thumbv6m and thumbv8m.base because - // these targets do not have full Thumb-2 support but only original Thumb-1. - // We have to cfg our code accordingly. - println!("cargo::rustc-check-cfg=cfg(thumb_1)"); - if target.triple_split[0] == "thumbv6m" || target.triple_split[0] == "thumbv8m.base" { - println!("cargo:rustc-cfg=thumb_1") - } - - // Config shorthands - println!("cargo:rustc-check-cfg=cfg(x86_no_sse)"); - if target.arch == "x86" && !target.features.iter().any(|f| f == "sse") { - // Shorthand to detect i586 targets - println!("cargo:rustc-cfg=x86_no_sse"); - } - - /* Not all backends support `f16` and `f128` to the same level on all architectures, so we - * need to disable things if the compiler may crash. See configuration at: - * * https://github.com/rust-lang/rust/blob/c65dccabacdfd6c8a7f7439eba13422fdd89b91e/compiler/rustc_codegen_llvm/src/llvm_util.rs#L367-L432 - * * https://github.com/rust-lang/rustc_codegen_gcc/blob/4b5c44b14166083eef8d71f15f5ea1f53fc976a0/src/lib.rs#L496-L507 - * * https://github.com/rust-lang/rustc_codegen_cranelift/blob/c713ffab3c6e28ab4b4dd4e392330f786ea657ad/src/lib.rs#L196-L226 - */ - - println!("cargo::rustc-check-cfg=cfg(f16_enabled)"); - if target.reliable_f16 { - println!("cargo::rustc-cfg=f16_enabled"); - } - - println!("cargo::rustc-check-cfg=cfg(f128_enabled)"); - if target.reliable_f128 { - println!("cargo::rustc-cfg=f128_enabled"); - } -} diff --git a/library/compiler-builtins/compiler-builtins/src/aarch64.rs b/library/compiler-builtins/compiler-builtins/src/aarch64.rs index 1b230a214eefe..2c12cb7f3095b 100644 --- a/library/compiler-builtins/compiler-builtins/src/aarch64.rs +++ b/library/compiler-builtins/compiler-builtins/src/aarch64.rs @@ -1,7 +1,3 @@ -#![allow(unused_imports)] - -use core::intrinsics; - intrinsics! { #[unsafe(naked)] #[cfg(any(all(windows, target_env = "gnu"), target_os = "uefi"))] diff --git a/library/compiler-builtins/compiler-builtins/src/aarch64_outline_atomics.rs b/library/compiler-builtins/compiler-builtins/src/aarch64_outline_atomics.rs index df0cf76502223..367768ecb60d6 100644 --- a/library/compiler-builtins/compiler-builtins/src/aarch64_outline_atomics.rs +++ b/library/compiler-builtins/compiler-builtins/src/aarch64_outline_atomics.rs @@ -34,14 +34,27 @@ intrinsics! { } } +/// Function to enable/disable LSE. To be used only for testing purposes. +#[cfg(feature = "unstable-public-internals")] +pub unsafe fn set_have_lse_atomics(has_lse: bool) { + let lse_flag = if has_lse { 1 } else { 0 }; + HAVE_LSE_ATOMICS.store(lse_flag, Ordering::Relaxed); +} + +/// Function to obtain whether LSE is enabled or not. To be used only for testing purposes. +#[cfg(feature = "unstable-public-internals")] +pub fn get_have_lse_atomics() -> bool { + HAVE_LSE_ATOMICS.load(Ordering::Relaxed) != 0 +} + /// Translate a byte size to a Rust type. #[rustfmt::skip] macro_rules! int_ty { - (1) => { i8 }; - (2) => { i16 }; - (4) => { i32 }; - (8) => { i64 }; - (16) => { i128 }; + (1) => { u8 }; + (2) => { u16 }; + (4) => { u32 }; + (8) => { u64 }; + (16) => { u128 }; } /// Given a byte size and a register number, return a register of the appropriate size. @@ -135,18 +148,73 @@ macro_rules! stxp { }; } +// The AArch64 assembly syntax for relocation specifiers +// when accessing symbols changes depending on the target executable format. +// In ELF (used in Linux), we have a prefix notation surrounded by colons (:specifier:sym), +// while in Mach-O object files (used in MacOS), a postfix notation is used (sym@specifier). + +/// AArch64 ELF position-independent addressing: +/// +/// adrp xN, symbol +/// add xN, xN, :lo12:symbol +/// +/// The :lo12: modifier selects the low 12 bits of the symbol address +/// and emits an ELF relocation such as R_AARCH64_ADD_ABS_LO12_NC. +/// +/// Defined by the AArch64 ELF psABI. +/// See: . +#[cfg(not(target_vendor = "apple"))] +macro_rules! sym { + ($sym:literal) => { + $sym + }; +} + +#[cfg(not(target_vendor = "apple"))] +macro_rules! sym_off { + ($sym:literal) => { + concat!(":lo12:", $sym) + }; +} + +/// Mach-O ARM64 relocation types: +/// ARM64_RELOC_PAGE21 +/// ARM64_RELOC_PAGEOFF12 +/// +/// These relocations implement the @PAGE / @PAGEOFF split used by +/// adrp + add sequences on Apple platforms. +/// +/// adrp xN, symbol@PAGE -> ARM64_RELOC_PAGE21 +/// add xN, xN, symbol@PAGEOFF -> ARM64_RELOC_PAGEOFF12 +/// +/// Relocation types defined by Apple in XNU: . +/// See: . +#[cfg(target_vendor = "apple")] +macro_rules! sym { + ($sym:literal) => { + concat!($sym, "@PAGE") + }; +} + +#[cfg(target_vendor = "apple")] +macro_rules! sym_off { + ($sym:literal) => { + concat!($sym, "@PAGEOFF") + }; +} + // If supported, perform the requested LSE op and return, or fallthrough. macro_rules! try_lse_op { ($op: literal, $ordering:ident, $bytes:tt, $($reg:literal,)* [ $mem:ident ] ) => { concat!( - ".arch_extension lse; ", - "adrp x16, {have_lse}; ", - "ldrb w16, [x16, :lo12:{have_lse}]; ", - "cbz w16, 8f; ", + ".arch_extension lse\n", + concat!("adrp x16, ", sym!("{have_lse}"), "\n"), + concat!("ldrb w16, [x16, ", sym_off!("{have_lse}"), "]\n"), + "cbz w16, 8f\n", // LSE_OP s(reg),* [$mem] - concat!(lse!($op, $ordering, $bytes), $( " ", reg!($bytes, $reg), ", " ,)* "[", stringify!($mem), "]; ",), - "ret; ", - "8:" + concat!(lse!($op, $ordering, $bytes), $( " ", reg!($bytes, $reg), ", " ,)* "[", stringify!($mem), "]\n",), + "ret + 8:" ) }; } @@ -203,15 +271,15 @@ macro_rules! compare_and_swap { }; } -// i128 uses a completely different impl, so it has its own macro. -macro_rules! compare_and_swap_i128 { +// u128 uses a completely different impl, so it has its own macro. +macro_rules! compare_and_swap_u128 { ($ordering:ident, $name:ident) => { intrinsics! { #[maybe_use_optimized_c_shim] #[unsafe(naked)] pub unsafe extern "C" fn $name ( - expected: i128, desired: i128, ptr: *mut i128 - ) -> i128 { + expected: u128, desired: u128, ptr: *mut u128 + ) -> u128 { core::arch::naked_asm! { // CASP x0, x1, x2, x3, [x4]; if LSE supported. try_lse_op!("cas", $ordering, 16, 0, 1, 2, 3, [x4]), @@ -391,7 +459,7 @@ macro_rules! foreach_ldset { } foreach_cas!(compare_and_swap); -foreach_cas16!(compare_and_swap_i128); +foreach_cas16!(compare_and_swap_u128); foreach_swp!(swap); foreach_ldadd!(add); foreach_ldclr!(and); diff --git a/library/compiler-builtins/compiler-builtins/src/float/add.rs b/library/compiler-builtins/compiler-builtins/src/float/add.rs index acdcd2ebe3133..69de07372f16e 100644 --- a/library/compiler-builtins/compiler-builtins/src/float/add.rs +++ b/library/compiler-builtins/compiler-builtins/src/float/add.rs @@ -1,5 +1,4 @@ -use crate::float::Float; -use crate::int::{CastFrom, CastInto, Int, MinInt}; +use crate::support::{CastFrom, CastInto, Float, Int, MinInt}; /// Returns `a + b` fn add(a: F, b: F) -> F diff --git a/library/compiler-builtins/compiler-builtins/src/float/cmp.rs b/library/compiler-builtins/compiler-builtins/src/float/cmp.rs index 8ab39c2b5914d..243c9c767f61b 100644 --- a/library/compiler-builtins/compiler-builtins/src/float/cmp.rs +++ b/library/compiler-builtins/compiler-builtins/src/float/cmp.rs @@ -1,21 +1,30 @@ #![allow(unreachable_code)] -use crate::float::Float; -use crate::int::MinInt; -use crate::support::cfg_if; - -// Taken from LLVM config: -// https://github.com/llvm/llvm-project/blob/0cf3c437c18ed27d9663d87804a9a15ff6874af2/compiler-rt/lib/builtins/fp_compare_impl.inc#L11-L27 -cfg_if! { - if #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] { +use crate::support::{Float, MinInt, cfg_select_nofmt}; + +// These definitions should be consistent with LLVM's definition from `getCmpLibcallReturnType`, +// compiler-rt's definitions [1], GCC's `CMPtype` [2], and `libgcc`. To find the definitions +// in GCC, there are a few things to grep for: +// +// * `default_libgcc_cmp_return_mode` for the default (word sized) +// * `TARGET_LIBGCC_CMP_RETURN_MODE` for the target hook to override the default +// * `# *define *CMPtype` as a last resort, for overrides that don't use the hook (AVR) +// +// [1]: https://github.com/llvm/llvm-project/blob/0cf3c437c18ed27d9663d87804a9a15ff6874af2/compiler-rt/lib/builtins/fp_compare_impl.inc#L11-L27 +// [2]: https://gcc.gnu.org/onlinedocs/gccint/Soft-float-library-routines.html#Comparison-functions-1 +cfg_select_nofmt! { + any(target_arch = "aarch64", target_arch = "arm64ec", target_family = "wasm") => { // Aarch64 uses `int` rather than a pointer-sized value. + // `getCmpLibcallReturnType` for WASM is always set to i32. pub type CmpResult = i32; - } else if #[cfg(target_arch = "avr")] { + } + target_arch = "avr" => { // AVR uses a single byte. pub type CmpResult = i8; - } else { - // In compiler-rt, LLP64 ABIs use `long long` and everything else uses `long`. In effect, - // this means the return value is always pointer-sized. + } + _ => { + // The default is word-sized. In LLVM's compiler-rt, this is done by using `long long` on + // LLP64 ABIs and `long` on everything else. pub type CmpResult = isize; } } @@ -28,8 +37,18 @@ enum Result { Unordered, } +/// Conversions to match GCC intrinsics [1]. +/// +/// * `unord`: nonzero if either NaN, 0 otherwise +/// * `eq`, `ne`: 0 if a == b and both YaN, nonzero otherwise +/// * `ge`, `gt`, `lt`, `le`: return an int result that provides the same comparison to 0 if both +/// YaN and the comparison matches. E.g. if a >= b, `ge` returns an `x >= 0`. +/// +/// The separate map functions are only needed to handle the unordered case. +/// +/// [1]: https://gcc.gnu.org/onlinedocs/gccint/Soft-float-library-routines.html#Comparison-functions-1 impl Result { - fn to_le_abi(self) -> CmpResult { + fn to_default_cmp_result(self) -> CmpResult { match self { Result::Less => -1, Result::Equal => 0, @@ -38,7 +57,7 @@ impl Result { } } - fn to_ge_abi(self) -> CmpResult { + fn to_gt_ge_cmp_result(self) -> CmpResult { match self { Result::Less => -1, Result::Equal => 0, @@ -118,11 +137,11 @@ fn unord(a: F, b: F) -> bool { #[cfg(f16_enabled)] intrinsics! { pub extern "C" fn __lehf2(a: f16, b: f16) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __gehf2(a: f16, b: f16) -> crate::float::cmp::CmpResult { - cmp(a, b).to_ge_abi() + cmp(a, b).to_gt_ge_cmp_result() } pub extern "C" fn __unordhf2(a: f16, b: f16) -> crate::float::cmp::CmpResult { @@ -130,29 +149,29 @@ intrinsics! { } pub extern "C" fn __eqhf2(a: f16, b: f16) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __lthf2(a: f16, b: f16) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __nehf2(a: f16, b: f16) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __gthf2(a: f16, b: f16) -> crate::float::cmp::CmpResult { - cmp(a, b).to_ge_abi() + cmp(a, b).to_gt_ge_cmp_result() } } intrinsics! { pub extern "C" fn __lesf2(a: f32, b: f32) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __gesf2(a: f32, b: f32) -> crate::float::cmp::CmpResult { - cmp(a, b).to_ge_abi() + cmp(a, b).to_gt_ge_cmp_result() } #[arm_aeabi_alias = __aeabi_fcmpun] @@ -161,27 +180,27 @@ intrinsics! { } pub extern "C" fn __eqsf2(a: f32, b: f32) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __ltsf2(a: f32, b: f32) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __nesf2(a: f32, b: f32) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __gtsf2(a: f32, b: f32) -> crate::float::cmp::CmpResult { - cmp(a, b).to_ge_abi() + cmp(a, b).to_gt_ge_cmp_result() } pub extern "C" fn __ledf2(a: f64, b: f64) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __gedf2(a: f64, b: f64) -> crate::float::cmp::CmpResult { - cmp(a, b).to_ge_abi() + cmp(a, b).to_gt_ge_cmp_result() } #[arm_aeabi_alias = __aeabi_dcmpun] @@ -190,19 +209,19 @@ intrinsics! { } pub extern "C" fn __eqdf2(a: f64, b: f64) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __ltdf2(a: f64, b: f64) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __nedf2(a: f64, b: f64) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __gtdf2(a: f64, b: f64) -> crate::float::cmp::CmpResult { - cmp(a, b).to_ge_abi() + cmp(a, b).to_gt_ge_cmp_result() } } @@ -210,12 +229,12 @@ intrinsics! { intrinsics! { #[ppc_alias = __lekf2] pub extern "C" fn __letf2(a: f128, b: f128) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } #[ppc_alias = __gekf2] pub extern "C" fn __getf2(a: f128, b: f128) -> crate::float::cmp::CmpResult { - cmp(a, b).to_ge_abi() + cmp(a, b).to_gt_ge_cmp_result() } #[ppc_alias = __unordkf2] @@ -225,22 +244,22 @@ intrinsics! { #[ppc_alias = __eqkf2] pub extern "C" fn __eqtf2(a: f128, b: f128) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } #[ppc_alias = __ltkf2] pub extern "C" fn __lttf2(a: f128, b: f128) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } #[ppc_alias = __nekf2] pub extern "C" fn __netf2(a: f128, b: f128) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } #[ppc_alias = __gtkf2] pub extern "C" fn __gttf2(a: f128, b: f128) -> crate::float::cmp::CmpResult { - cmp(a, b).to_ge_abi() + cmp(a, b).to_gt_ge_cmp_result() } } diff --git a/library/compiler-builtins/compiler-builtins/src/float/conv.rs b/library/compiler-builtins/compiler-builtins/src/float/conv.rs index 75ea7ce02424a..6193aa416e222 100644 --- a/library/compiler-builtins/compiler-builtins/src/float/conv.rs +++ b/library/compiler-builtins/compiler-builtins/src/float/conv.rs @@ -1,7 +1,6 @@ use core::ops::Neg; -use super::Float; -use crate::int::{CastFrom, CastInto, Int, MinInt}; +use crate::support::{CastFrom, CastInto, Float, Int, MinInt}; /// Conversions from integers to floats. /// @@ -229,16 +228,26 @@ intrinsics! { f64::from_bits(int_to_float::u64_to_f64_bits(i)) } - #[cfg_attr(target_os = "uefi", unadjusted_on_win64)] + #[cfg(not(all(target_os = "uefi", target_arch = "x86_64")))] pub extern "C" fn __floatuntisf(i: u128) -> f32 { f32::from_bits(int_to_float::u128_to_f32_bits(i)) } - #[cfg_attr(target_os = "uefi", unadjusted_on_win64)] + #[cfg(all(target_os = "uefi", target_arch = "x86_64"))] + pub extern "C" fn __floatuntisf(lo: u64, hi: u64) -> f32 { + f32::from_bits(int_to_float::u128_to_f32_bits((u128::from(hi) << 64) | u128::from(lo))) + } + + #[cfg(not(all(target_os = "uefi", target_arch = "x86_64")))] pub extern "C" fn __floatuntidf(i: u128) -> f64 { f64::from_bits(int_to_float::u128_to_f64_bits(i)) } + #[cfg(all(target_os = "uefi", target_arch = "x86_64"))] + pub extern "C" fn __floatuntidf(lo: u64, hi: u64) -> f64 { + f64::from_bits(int_to_float::u128_to_f64_bits((u128::from(hi) << 64) | u128::from(lo))) + } + #[ppc_alias = __floatunsikf] #[cfg(f128_enabled)] pub extern "C" fn __floatunsitf(i: u32) -> f128 { @@ -280,16 +289,26 @@ intrinsics! { int_to_float::signed(i, int_to_float::u64_to_f64_bits) } - #[cfg_attr(target_os = "uefi", unadjusted_on_win64)] + #[cfg(not(all(target_os = "uefi", target_arch = "x86_64")))] pub extern "C" fn __floattisf(i: i128) -> f32 { int_to_float::signed(i, int_to_float::u128_to_f32_bits) } - #[cfg_attr(target_os = "uefi", unadjusted_on_win64)] + #[cfg(all(target_os = "uefi", target_arch = "x86_64"))] + pub extern "C" fn __floattisf(lo: u64, hi: u64) -> f32 { + int_to_float::signed((i128::from(hi) << 64) | i128::from(lo), int_to_float::u128_to_f32_bits) + } + + #[cfg(not(all(target_os = "uefi", target_arch = "x86_64")))] pub extern "C" fn __floattidf(i: i128) -> f64 { int_to_float::signed(i, int_to_float::u128_to_f64_bits) } + #[cfg(all(target_os = "uefi", target_arch = "x86_64"))] + pub extern "C" fn __floattidf(lo: u64, hi: u64) -> f64 { + int_to_float::signed((i128::from(hi) << 64) | i128::from(lo), int_to_float::u128_to_f64_bits) + } + #[ppc_alias = __floatsikf] #[cfg(f128_enabled)] pub extern "C" fn __floatsitf(i: i32) -> f128 { diff --git a/library/compiler-builtins/compiler-builtins/src/float/div.rs b/library/compiler-builtins/compiler-builtins/src/float/div.rs index fc1fc085105a7..419d8ad5e7061 100644 --- a/library/compiler-builtins/compiler-builtins/src/float/div.rs +++ b/library/compiler-builtins/compiler-builtins/src/float/div.rs @@ -82,9 +82,7 @@ use core::mem::size_of; use core::ops; -use super::HalfRep; -use crate::float::Float; -use crate::int::{CastFrom, CastInto, DInt, HInt, Int, MinInt}; +use crate::support::{CastFrom, CastInto, DInt, Float, HInt, HalfRep, Int, MinInt}; fn div(a: F, b: F) -> F where diff --git a/library/compiler-builtins/compiler-builtins/src/float/extend.rs b/library/compiler-builtins/compiler-builtins/src/float/extend.rs index c4f1fe30e0ea8..58038ce57f834 100644 --- a/library/compiler-builtins/compiler-builtins/src/float/extend.rs +++ b/library/compiler-builtins/compiler-builtins/src/float/extend.rs @@ -1,5 +1,4 @@ -use crate::float::Float; -use crate::int::{CastInto, Int, MinInt}; +use crate::support::{CastInto, Float, Int, MinInt}; /// Generic conversion from a narrower to a wider IEEE-754 floating-point type fn extend(a: F) -> R diff --git a/library/compiler-builtins/compiler-builtins/src/float/mod.rs b/library/compiler-builtins/compiler-builtins/src/float/mod.rs index 4a379d0d3575b..15318c4928804 100644 --- a/library/compiler-builtins/compiler-builtins/src/float/mod.rs +++ b/library/compiler-builtins/compiler-builtins/src/float/mod.rs @@ -6,10 +6,4 @@ pub mod extend; pub mod mul; pub mod pow; pub mod sub; -pub(crate) mod traits; pub mod trunc; - -#[cfg(not(feature = "unstable-public-internals"))] -pub(crate) use traits::{Float, HalfRep}; -#[cfg(feature = "unstable-public-internals")] -pub use traits::{Float, HalfRep}; diff --git a/library/compiler-builtins/compiler-builtins/src/float/mul.rs b/library/compiler-builtins/compiler-builtins/src/float/mul.rs index 49a2414eb5c69..ffba2dc41f8a0 100644 --- a/library/compiler-builtins/compiler-builtins/src/float/mul.rs +++ b/library/compiler-builtins/compiler-builtins/src/float/mul.rs @@ -1,5 +1,4 @@ -use crate::float::Float; -use crate::int::{CastInto, DInt, HInt, Int, MinInt}; +use crate::support::{CastInto, DInt, Float, HInt, Int, MinInt}; fn mul(a: F, b: F) -> F where diff --git a/library/compiler-builtins/compiler-builtins/src/float/pow.rs b/library/compiler-builtins/compiler-builtins/src/float/pow.rs index 6997a9c213c59..2c92971d31397 100644 --- a/library/compiler-builtins/compiler-builtins/src/float/pow.rs +++ b/library/compiler-builtins/compiler-builtins/src/float/pow.rs @@ -1,5 +1,4 @@ -use crate::float::Float; -use crate::int::Int; +use crate::support::{Float, Int}; /// Returns `a` raised to the power `b` fn pow(a: F, b: i32) -> F { diff --git a/library/compiler-builtins/compiler-builtins/src/float/sub.rs b/library/compiler-builtins/compiler-builtins/src/float/sub.rs index 48ef33b0b826f..11dd3b77d5d1c 100644 --- a/library/compiler-builtins/compiler-builtins/src/float/sub.rs +++ b/library/compiler-builtins/compiler-builtins/src/float/sub.rs @@ -1,4 +1,4 @@ -use crate::float::Float; +use crate::support::Float; intrinsics! { #[cfg(f16_enabled)] diff --git a/library/compiler-builtins/compiler-builtins/src/float/traits.rs b/library/compiler-builtins/compiler-builtins/src/float/traits.rs deleted file mode 100644 index a30d20900b1c4..0000000000000 --- a/library/compiler-builtins/compiler-builtins/src/float/traits.rs +++ /dev/null @@ -1,189 +0,0 @@ -use core::ops; - -use crate::int::{DInt, Int, MinInt}; - -/// Wrapper to extract the integer type half of the float's size -pub type HalfRep = <::Int as DInt>::H; - -/// Trait for some basic operations on floats -#[allow(dead_code)] -pub trait Float: - Copy - + core::fmt::Debug - + PartialEq - + PartialOrd - + ops::AddAssign - + ops::MulAssign - + ops::Add - + ops::Sub - + ops::Div - + ops::Rem -{ - /// A uint of the same width as the float - type Int: Int; - - /// A int of the same width as the float - type SignedInt: Int + MinInt; - - /// An int capable of containing the exponent bits plus a sign bit. This is signed. - type ExpInt: Int; - - const ZERO: Self; - const ONE: Self; - - /// The bitwidth of the float type. - const BITS: u32; - - /// The bitwidth of the significand. - const SIG_BITS: u32; - - /// The bitwidth of the exponent. - const EXP_BITS: u32 = Self::BITS - Self::SIG_BITS - 1; - - /// The saturated (maximum bitpattern) value of the exponent, i.e. the infinite - /// representation. - /// - /// This is in the rightmost position, use `EXP_MASK` for the shifted value. - const EXP_SAT: u32 = (1 << Self::EXP_BITS) - 1; - - /// The exponent bias value. - const EXP_BIAS: u32 = Self::EXP_SAT >> 1; - - /// A mask for the sign bit. - const SIGN_MASK: Self::Int; - - /// A mask for the significand. - const SIG_MASK: Self::Int; - - /// The implicit bit of the float format. - const IMPLICIT_BIT: Self::Int; - - /// A mask for the exponent. - const EXP_MASK: Self::Int; - - /// Returns `self` transmuted to `Self::Int` - fn to_bits(self) -> Self::Int; - - /// Returns `self` transmuted to `Self::SignedInt` - fn to_bits_signed(self) -> Self::SignedInt; - - /// Checks if two floats have the same bit representation. *Except* for NaNs! NaN can be - /// represented in multiple different ways. This method returns `true` if two NaNs are - /// compared. - fn eq_repr(self, rhs: Self) -> bool; - - /// Returns true if the sign is negative - fn is_sign_negative(self) -> bool; - - /// Returns the exponent, not adjusting for bias. - fn exp(self) -> Self::ExpInt; - - /// Returns the significand with no implicit bit (or the "fractional" part) - fn frac(self) -> Self::Int; - - /// Returns the significand with implicit bit - fn imp_frac(self) -> Self::Int; - - /// Returns a `Self::Int` transmuted back to `Self` - fn from_bits(a: Self::Int) -> Self; - - /// Constructs a `Self` from its parts. Inputs are treated as bits and shifted into position. - fn from_parts(negative: bool, exponent: Self::Int, significand: Self::Int) -> Self; - - fn abs(self) -> Self { - let abs_mask = !Self::SIGN_MASK; - Self::from_bits(self.to_bits() & abs_mask) - } - - /// Returns (normalized exponent, normalized significand) - fn normalize(significand: Self::Int) -> (i32, Self::Int); - - /// Returns if `self` is subnormal - fn is_subnormal(self) -> bool; -} - -macro_rules! float_impl { - ($ty:ident, $ity:ident, $sity:ident, $expty:ident, $bits:expr, $significand_bits:expr) => { - impl Float for $ty { - type Int = $ity; - type SignedInt = $sity; - type ExpInt = $expty; - - const ZERO: Self = 0.0; - const ONE: Self = 1.0; - - const BITS: u32 = $bits; - const SIG_BITS: u32 = $significand_bits; - - const SIGN_MASK: Self::Int = 1 << (Self::BITS - 1); - const SIG_MASK: Self::Int = (1 << Self::SIG_BITS) - 1; - const IMPLICIT_BIT: Self::Int = 1 << Self::SIG_BITS; - const EXP_MASK: Self::Int = !(Self::SIGN_MASK | Self::SIG_MASK); - - fn to_bits(self) -> Self::Int { - self.to_bits() - } - fn to_bits_signed(self) -> Self::SignedInt { - self.to_bits() as Self::SignedInt - } - fn eq_repr(self, rhs: Self) -> bool { - #[cfg(feature = "mangled-names")] - fn is_nan(x: $ty) -> bool { - // When using mangled-names, the "real" compiler-builtins might not have the - // necessary builtin (__unordtf2) to test whether `f128` is NaN. - // FIXME(f16_f128): Remove once the nightly toolchain has the __unordtf2 builtin - // x is NaN if all the bits of the exponent are set and the significand is non-0 - x.to_bits() & $ty::EXP_MASK == $ty::EXP_MASK && x.to_bits() & $ty::SIG_MASK != 0 - } - #[cfg(not(feature = "mangled-names"))] - fn is_nan(x: $ty) -> bool { - x.is_nan() - } - if is_nan(self) && is_nan(rhs) { - true - } else { - self.to_bits() == rhs.to_bits() - } - } - fn is_sign_negative(self) -> bool { - self.is_sign_negative() - } - fn exp(self) -> Self::ExpInt { - ((self.to_bits() & Self::EXP_MASK) >> Self::SIG_BITS) as Self::ExpInt - } - fn frac(self) -> Self::Int { - self.to_bits() & Self::SIG_MASK - } - fn imp_frac(self) -> Self::Int { - self.frac() | Self::IMPLICIT_BIT - } - fn from_bits(a: Self::Int) -> Self { - Self::from_bits(a) - } - fn from_parts(negative: bool, exponent: Self::Int, significand: Self::Int) -> Self { - Self::from_bits( - ((negative as Self::Int) << (Self::BITS - 1)) - | ((exponent << Self::SIG_BITS) & Self::EXP_MASK) - | (significand & Self::SIG_MASK), - ) - } - fn normalize(significand: Self::Int) -> (i32, Self::Int) { - let shift = significand.leading_zeros().wrapping_sub(Self::EXP_BITS); - ( - 1i32.wrapping_sub(shift as i32), - significand << shift as Self::Int, - ) - } - fn is_subnormal(self) -> bool { - (self.to_bits() & Self::EXP_MASK) == Self::Int::ZERO - } - } - }; -} - -#[cfg(f16_enabled)] -float_impl!(f16, u16, i16, i8, 16, 10); -float_impl!(f32, u32, i32, i16, 32, 23); -float_impl!(f64, u64, i64, i16, 64, 52); -#[cfg(f128_enabled)] -float_impl!(f128, u128, i128, i16, 128, 112); diff --git a/library/compiler-builtins/compiler-builtins/src/float/trunc.rs b/library/compiler-builtins/compiler-builtins/src/float/trunc.rs index 93db5d8bbdeb1..1a88b0649fda3 100644 --- a/library/compiler-builtins/compiler-builtins/src/float/trunc.rs +++ b/library/compiler-builtins/compiler-builtins/src/float/trunc.rs @@ -1,5 +1,4 @@ -use crate::float::Float; -use crate::int::{CastInto, Int, MinInt}; +use crate::support::{CastInto, Float, Int, MinInt}; fn trunc(a: F) -> R where diff --git a/library/compiler-builtins/compiler-builtins/src/hexagon.rs b/library/compiler-builtins/compiler-builtins/src/hexagon.rs index a5c7b4dfdda91..551186b1db861 100644 --- a/library/compiler-builtins/compiler-builtins/src/hexagon.rs +++ b/library/compiler-builtins/compiler-builtins/src/hexagon.rs @@ -1,53 +1,77 @@ use core::arch::global_asm; -global_asm!(include_str!("hexagon/func_macro.s"), options(raw)); - -global_asm!(include_str!("hexagon/dfaddsub.s"), options(raw)); - -global_asm!(include_str!("hexagon/dfdiv.s"), options(raw)); - -global_asm!(include_str!("hexagon/dffma.s"), options(raw)); - -global_asm!(include_str!("hexagon/dfminmax.s"), options(raw)); - -global_asm!(include_str!("hexagon/dfmul.s"), options(raw)); - -global_asm!(include_str!("hexagon/dfsqrt.s"), options(raw)); - -global_asm!(include_str!("hexagon/divdi3.s"), options(raw)); - -global_asm!(include_str!("hexagon/divsi3.s"), options(raw)); - -global_asm!(include_str!("hexagon/fastmath2_dlib_asm.s"), options(raw)); - -global_asm!(include_str!("hexagon/fastmath2_ldlib_asm.s"), options(raw)); - +// Hexagon L1 cache line size in bytes (Hexagon PRM sections 5.10.3-5.10.4). +const CACHE_LINE_SIZE: usize = 32; + +intrinsics! { + pub unsafe extern "C" fn __clear_cache(start: *mut u8, end: *mut u8) { + // Hexagon has separate instruction and data caches. + let mask = !(CACHE_LINE_SIZE - 1); + let start_line = start.addr() & mask; + let end_addr = end.addr(); + + // Clean and invalidate data cache to push new code to memory and + // invalidate stale lines in the L2 cache. + let mut addr = start_line; + while addr < end_addr { + unsafe { + core::arch::asm!( + "dccleaninva({addr})", + addr = in(reg) addr, + options(nostack, preserves_flags), + ); + } + addr += CACHE_LINE_SIZE; + } + + // Invalidate instruction cache so it re-fetches from memory. + addr = start_line; + while addr < end_addr { + unsafe { + core::arch::asm!( + "icinva({addr})", + addr = in(reg) addr, + options(nostack, preserves_flags), + ); + } + addr += CACHE_LINE_SIZE; + } + + // Instruction sync barrier ensures subsequent fetches see the new code. + unsafe { + core::arch::asm!("isync", options(nostack, preserves_flags)); + } + } +} + +// All hexagon assembly must live in ONE `global_asm!` invocation, and +// `func_macro.s` must come first. global_asm!( + include_str!("hexagon/func_macro.s"), + include_str!("hexagon/common_entry_exit_abi1.s"), + include_str!("hexagon/common_entry_exit_abi2.s"), + include_str!("hexagon/common_entry_exit_legacy.s"), + include_str!("hexagon/dfaddsub.s"), + include_str!("hexagon/dfdiv.s"), + include_str!("hexagon/dffma.s"), + include_str!("hexagon/dfminmax.s"), + include_str!("hexagon/dfmul.s"), + include_str!("hexagon/dfsqrt.s"), + include_str!("hexagon/divdi3.s"), + include_str!("hexagon/divsi3.s"), + include_str!("hexagon/fastmath2_dlib_asm.s"), + include_str!("hexagon/fastmath2_ldlib_asm.s"), include_str!("hexagon/memcpy_forward_vp4cp4n2.s"), - options(raw) -); - -global_asm!( include_str!("hexagon/memcpy_likely_aligned.s"), + include_str!("hexagon/moddi3.s"), + include_str!("hexagon/modsi3.s"), + include_str!("hexagon/sfdiv_opt.s"), + include_str!("hexagon/sfsqrt_opt.s"), + include_str!("hexagon/udivdi3.s"), + include_str!("hexagon/udivmoddi4.s"), + include_str!("hexagon/udivmodsi4.s"), + include_str!("hexagon/udivsi3.s"), + include_str!("hexagon/umoddi3.s"), + include_str!("hexagon/umodsi3.s"), options(raw) ); - -global_asm!(include_str!("hexagon/moddi3.s"), options(raw)); - -global_asm!(include_str!("hexagon/modsi3.s"), options(raw)); - -global_asm!(include_str!("hexagon/sfdiv_opt.s"), options(raw)); - -global_asm!(include_str!("hexagon/sfsqrt_opt.s"), options(raw)); - -global_asm!(include_str!("hexagon/udivdi3.s"), options(raw)); - -global_asm!(include_str!("hexagon/udivmoddi4.s"), options(raw)); - -global_asm!(include_str!("hexagon/udivmodsi4.s"), options(raw)); - -global_asm!(include_str!("hexagon/udivsi3.s"), options(raw)); - -global_asm!(include_str!("hexagon/umoddi3.s"), options(raw)); - -global_asm!(include_str!("hexagon/umodsi3.s"), options(raw)); diff --git a/library/compiler-builtins/compiler-builtins/src/hexagon/common_entry_exit_abi1.s b/library/compiler-builtins/compiler-builtins/src/hexagon/common_entry_exit_abi1.s new file mode 100644 index 0000000000000..61425abaad5ae --- /dev/null +++ b/library/compiler-builtins/compiler-builtins/src/hexagon/common_entry_exit_abi1.s @@ -0,0 +1,42 @@ + +FUNCTION_BEGIN __save_r24_through_r27 + memd(fp+#-16) = r27:26 +FALLTHROUGH_TAIL_CALL __save_r24_through_r27 __save_r24_through_r25 + { + memd(fp+#-8) = r25:24 + jumpr lr + } +FUNCTION_END __save_r24_through_r25 + + +FUNCTION_BEGIN __restore_r24_through_r27_and_deallocframe_before_tailcall + r27:26 = memd(fp+#-16) +FALLTHROUGH_TAIL_CALL __restore_r24_through_r27_and_deallocframe_before_tailcall __restore_r24_through_r25_and_deallocframe_before_tailcall + { + r25:24 = memd(fp+#-8) + deallocframe + jumpr lr + } +FUNCTION_END __restore_r24_through_r25_and_deallocframe_before_tailcall + + +FUNCTION_BEGIN __restore_r24_through_r27_and_deallocframe + { + lr = memw(fp+#4) + r27:26 = memd(fp+#-16) + } + { + r25:24 = memd(fp+#-8) + deallocframe + jumpr lr + } +FUNCTION_END __restore_r24_through_r27_and_deallocframe + + +FUNCTION_BEGIN __restore_r24_through_r25_and_deallocframe + { + r25:24 = memd(fp+#-8) + deallocframe + } + jumpr lr +FUNCTION_END __restore_r24_through_r25_and_deallocframe diff --git a/library/compiler-builtins/compiler-builtins/src/hexagon/common_entry_exit_abi2.s b/library/compiler-builtins/compiler-builtins/src/hexagon/common_entry_exit_abi2.s new file mode 100644 index 0000000000000..8734310fc3758 --- /dev/null +++ b/library/compiler-builtins/compiler-builtins/src/hexagon/common_entry_exit_abi2.s @@ -0,0 +1,237 @@ + + .macro ABI2_FUNCTION_BEGIN name + .p2align 2 + .section .text.\name,"ax",@progbits + .globl \name + .type \name, @function +\name: + .endm + + .macro ABI2_FUNCTION_END name + .size \name, . - \name + .endm + + +ABI2_FUNCTION_BEGIN __save_r16_through_r27 + { + memd(fp+#-48) = r27:26 + memd(fp+#-40) = r25:24 + } + { + memd(fp+#-32) = r23:22 + memd(fp+#-24) = r21:20 + } + { + memd(fp+#-16) = r19:18 + memd(fp+#-8) = r17:16 + jumpr lr + } +ABI2_FUNCTION_END __save_r16_through_r27 + +ABI2_FUNCTION_BEGIN __save_r16_through_r25 + { + memd(fp+#-40) = r25:24 + memd(fp+#-32) = r23:22 + } + { + memd(fp+#-24) = r21:20 + memd(fp+#-16) = r19:18 + } + { + memd(fp+#-8) = r17:16 + jumpr lr + } +ABI2_FUNCTION_END __save_r16_through_r25 + +ABI2_FUNCTION_BEGIN __save_r16_through_r23 + { + memd(fp+#-32) = r23:22 + memd(fp+#-24) = r21:20 + } + { + memd(fp+#-16) = r19:18 + memd(fp+#-8) = r17:16 + jumpr lr + } +ABI2_FUNCTION_END __save_r16_through_r23 + +ABI2_FUNCTION_BEGIN __save_r16_through_r21 + { + memd(fp+#-24) = r21:20 + memd(fp+#-16) = r19:18 + } + { + memd(fp+#-8) = r17:16 + jumpr lr + } +ABI2_FUNCTION_END __save_r16_through_r21 + +ABI2_FUNCTION_BEGIN __save_r16_through_r19 + { + memd(fp+#-16) = r19:18 + memd(fp+#-8) = r17:16 + jumpr lr + } +ABI2_FUNCTION_END __save_r16_through_r19 + +ABI2_FUNCTION_BEGIN __save_r16_through_r17 + { + memd(fp+#-8) = r17:16 + jumpr lr + } +ABI2_FUNCTION_END __save_r16_through_r17 + + +ABI2_FUNCTION_BEGIN __restore_r16_through_r27_and_deallocframe_before_tailcall + r27:26 = memd(fp+#-48) + { + r25:24 = memd(fp+#-40) + r23:22 = memd(fp+#-32) + } + { + r21:20 = memd(fp+#-24) + r19:18 = memd(fp+#-16) + } + { + r17:16 = memd(fp+#-8) + deallocframe + jumpr lr + } +ABI2_FUNCTION_END __restore_r16_through_r27_and_deallocframe_before_tailcall + +ABI2_FUNCTION_BEGIN __restore_r16_through_r25_and_deallocframe_before_tailcall + { + r25:24 = memd(fp+#-40) + r23:22 = memd(fp+#-32) + } + { + r21:20 = memd(fp+#-24) + r19:18 = memd(fp+#-16) + } + { + r17:16 = memd(fp+#-8) + deallocframe + jumpr lr + } +ABI2_FUNCTION_END __restore_r16_through_r25_and_deallocframe_before_tailcall + +ABI2_FUNCTION_BEGIN __restore_r16_through_r23_and_deallocframe_before_tailcall + { + r23:22 = memd(fp+#-32) + r21:20 = memd(fp+#-24) + } + r19:18 = memd(fp+#-16) + { + r17:16 = memd(fp+#-8) + deallocframe + jumpr lr + } +ABI2_FUNCTION_END __restore_r16_through_r23_and_deallocframe_before_tailcall + + +ABI2_FUNCTION_BEGIN __restore_r16_through_r21_and_deallocframe_before_tailcall + { + r21:20 = memd(fp+#-24) + r19:18 = memd(fp+#-16) + } + { + r17:16 = memd(fp+#-8) + deallocframe + jumpr lr + } +ABI2_FUNCTION_END __restore_r16_through_r21_and_deallocframe_before_tailcall + +ABI2_FUNCTION_BEGIN __restore_r16_through_r19_and_deallocframe_before_tailcall + r19:18 = memd(fp+#-16) + { + r17:16 = memd(fp+#-8) + deallocframe + jumpr lr + } +ABI2_FUNCTION_END __restore_r16_through_r19_and_deallocframe_before_tailcall + +ABI2_FUNCTION_BEGIN __restore_r16_through_r17_and_deallocframe_before_tailcall + { + r17:16 = memd(fp+#-8) + deallocframe + jumpr lr + } +ABI2_FUNCTION_END __restore_r16_through_r17_and_deallocframe_before_tailcall + + +ABI2_FUNCTION_BEGIN __restore_r16_through_r27_and_deallocframe + r27:26 = memd(fp+#-48) + { + r25:24 = memd(fp+#-40) + r23:22 = memd(fp+#-32) + } + { + r21:20 = memd(fp+#-24) + r19:18 = memd(fp+#-16) + } + { + r17:16 = memd(fp+#-8) + dealloc_return + } +ABI2_FUNCTION_END __restore_r16_through_r27_and_deallocframe + +ABI2_FUNCTION_BEGIN __restore_r16_through_r25_and_deallocframe + { + r25:24 = memd(fp+#-40) + r23:22 = memd(fp+#-32) + } + { + r21:20 = memd(fp+#-24) + r19:18 = memd(fp+#-16) + } + { + r17:16 = memd(fp+#-8) + dealloc_return + } +ABI2_FUNCTION_END __restore_r16_through_r25_and_deallocframe + +ABI2_FUNCTION_BEGIN __restore_r16_through_r23_and_deallocframe + { + r23:22 = memd(fp+#-32) + } + { + r21:20 = memd(fp+#-24) + r19:18 = memd(fp+#-16) + } + { + r17:16 = memd(fp+#-8) + dealloc_return + } +ABI2_FUNCTION_END __restore_r16_through_r23_and_deallocframe + +ABI2_FUNCTION_BEGIN __restore_r16_through_r21_and_deallocframe + { + r21:20 = memd(fp+#-24) + r19:18 = memd(fp+#-16) + } + { + r17:16 = memd(fp+#-8) + dealloc_return + } +ABI2_FUNCTION_END __restore_r16_through_r21_and_deallocframe + +ABI2_FUNCTION_BEGIN __restore_r16_through_r19_and_deallocframe + { + r19:18 = memd(fp+#-16) + r17:16 = memd(fp+#-8) + } + { + dealloc_return + } +ABI2_FUNCTION_END __restore_r16_through_r19_and_deallocframe + +ABI2_FUNCTION_BEGIN __restore_r16_through_r17_and_deallocframe + { + r17:16 = memd(fp+#-8) + dealloc_return + } +ABI2_FUNCTION_END __restore_r16_through_r17_and_deallocframe + +ABI2_FUNCTION_BEGIN __deallocframe + dealloc_return +ABI2_FUNCTION_END __deallocframe diff --git a/library/compiler-builtins/compiler-builtins/src/hexagon/common_entry_exit_legacy.s b/library/compiler-builtins/compiler-builtins/src/hexagon/common_entry_exit_legacy.s new file mode 100644 index 0000000000000..4c539ea91f4af --- /dev/null +++ b/library/compiler-builtins/compiler-builtins/src/hexagon/common_entry_exit_legacy.s @@ -0,0 +1,92 @@ + +FUNCTION_BEGIN __save_r27_through_r16 + memd(fp+#-48) = r17:16 +FALLTHROUGH_TAIL_CALL __save_r27_through_r16 __save_r27_through_r18 + memd(fp+#-40) = r19:18 +FALLTHROUGH_TAIL_CALL __save_r27_through_r18 __save_r27_through_r20 + memd(fp+#-32) = r21:20 +FALLTHROUGH_TAIL_CALL __save_r27_through_r20 __save_r27_through_r22 + memd(fp+#-24) = r23:22 +FALLTHROUGH_TAIL_CALL __save_r27_through_r22 __save_r27_through_r24 + memd(fp+#-16) = r25:24 + { + memd(fp+#-8) = r27:26 + jumpr lr + } +FUNCTION_END __save_r27_through_r24 + + +FUNCTION_BEGIN __restore_r27_through_r20_and_deallocframe_before_sibcall + { + r21:20 = memd(fp+#-32) + r23:22 = memd(fp+#-24) + } +FALLTHROUGH_TAIL_CALL __restore_r27_through_r20_and_deallocframe_before_sibcall __restore_r27_through_r24_and_deallocframe_before_sibcall + { + r25:24 = memd(fp+#-16) + jump __restore_r27_through_r26_and_deallocframe_before_sibcall + } +FUNCTION_END __restore_r27_through_r24_and_deallocframe_before_sibcall + + +FUNCTION_BEGIN __restore_r27_through_r16_and_deallocframe_before_sibcall + r17:16 = memd(fp+#-48) +FALLTHROUGH_TAIL_CALL __restore_r27_through_r16_and_deallocframe_before_sibcall __restore_r27_through_r18_and_deallocframe_before_sibcall + { + r19:18 = memd(fp+#-40) + r21:20 = memd(fp+#-32) + } +FALLTHROUGH_TAIL_CALL __restore_r27_through_r18_and_deallocframe_before_sibcall __restore_r27_through_r22_and_deallocframe_before_sibcall + { + r23:22 = memd(fp+#-24) + r25:24 = memd(fp+#-16) + } +FALLTHROUGH_TAIL_CALL __restore_r27_through_r22_and_deallocframe_before_sibcall __restore_r27_through_r26_and_deallocframe_before_sibcall + { + r27:26 = memd(fp+#-8) + deallocframe + jumpr lr + } +FUNCTION_END __restore_r27_through_r26_and_deallocframe_before_sibcall + + +FUNCTION_BEGIN __restore_r27_through_r16_and_deallocframe + { + r17:16 = memd(fp+#-48) + r19:18 = memd(fp+#-40) + } +FALLTHROUGH_TAIL_CALL __restore_r27_through_r16_and_deallocframe __restore_r27_through_r20_and_deallocframe + { + r21:20 = memd(fp+#-32) + r23:22 = memd(fp+#-24) + } +FALLTHROUGH_TAIL_CALL __restore_r27_through_r20_and_deallocframe __restore_r27_through_r24_and_deallocframe + { + lr = memw(fp+#4) + r25:24 = memd(fp+#-16) + } + { + r27:26 = memd(fp+#-8) + deallocframe + jumpr lr + } +FUNCTION_END __restore_r27_through_r24_and_deallocframe + + +FUNCTION_BEGIN __restore_r27_through_r18_and_deallocframe + { + r19:18 = memd(fp+#-40) + r21:20 = memd(fp+#-32) + } +FALLTHROUGH_TAIL_CALL __restore_r27_through_r18_and_deallocframe __restore_r27_through_r22_and_deallocframe + { + r23:22 = memd(fp+#-24) + r25:24 = memd(fp+#-16) + } +FALLTHROUGH_TAIL_CALL __restore_r27_through_r22_and_deallocframe __restore_r27_through_r26_and_deallocframe + { + r27:26 = memd(fp+#-8) + deallocframe + } + jumpr lr +FUNCTION_END __restore_r27_through_r26_and_deallocframe diff --git a/library/compiler-builtins/compiler-builtins/src/hexagon/dffma.s b/library/compiler-builtins/compiler-builtins/src/hexagon/dffma.s index 97d05eb1839ee..b57ed17dc1fd2 100644 --- a/library/compiler-builtins/compiler-builtins/src/hexagon/dffma.s +++ b/library/compiler-builtins/compiler-builtins/src/hexagon/dffma.s @@ -7,7 +7,7 @@ .p2align 5 __hexagon_fmadf4: __hexagon_fmadf5: -fma: +.Lfma: { p0 = dfclass(r1:0,#2) p0 = dfclass(r3:2,#2) @@ -338,10 +338,8 @@ fma: { p0 = !cmp.eq(r2,#1) p0 = !cmp.eq(r3,#2) - } - { - p0 = dfcmp.eq(r9:8,r9:8) if (p0.new) r11:10 = r9:8 + p0 = dfcmp.eq(r9:8,r9:8) } { r1:0 = insert(r11:10,#63,#0) @@ -400,7 +398,7 @@ fma: r3:2 = insert(r11:10,#63,#0) r1 -= asl(r28,#20) } - jump fma + jump .Lfma .Lfma_ab_tiny: r9:8 = combine(##0x00100000,#0) @@ -408,7 +406,7 @@ fma: r1:0 = insert(r9:8,#63,#0) r3:2 = insert(r9:8,#63,#0) } - jump fma + jump .Lfma .Lab_inf: { @@ -531,4 +529,3 @@ fma: r5 = insert(r28,#11,#20) jump .Lfma_abnormal_c_restart } -.size fma,.-fma diff --git a/library/compiler-builtins/compiler-builtins/src/hexagon/func_macro.s b/library/compiler-builtins/compiler-builtins/src/hexagon/func_macro.s index 9a1e11aebcb50..f5514cb7f057b 100644 --- a/library/compiler-builtins/compiler-builtins/src/hexagon/func_macro.s +++ b/library/compiler-builtins/compiler-builtins/src/hexagon/func_macro.s @@ -10,3 +10,11 @@ .size \name, . - \name .endm + .macro FALLTHROUGH_TAIL_CALL name0 name1 + .size \name0, . - \name0 + .globl \name1 + .type \name1, @function + .falign +\name1: + .endm + diff --git a/library/compiler-builtins/compiler-builtins/src/hexagon/memcpy_likely_aligned.s b/library/compiler-builtins/compiler-builtins/src/hexagon/memcpy_likely_aligned.s index 7e9b62f6a791c..416675833192e 100644 --- a/library/compiler-builtins/compiler-builtins/src/hexagon/memcpy_likely_aligned.s +++ b/library/compiler-builtins/compiler-builtins/src/hexagon/memcpy_likely_aligned.s @@ -31,6 +31,35 @@ FUNCTION_BEGIN __hexagon_memcpy_likely_aligned_min32bytes_mult8bytes } FUNCTION_END __hexagon_memcpy_likely_aligned_min32bytes_mult8bytes +FUNCTION_BEGIN __hexagon_memcpy_dwloop + { + r5:4 = memd(r1) + r3 = #-3 + } + { + memd(r0++#8) = r5:4 + r5:4 = memd(r1+#8) + r3 += lsr(r2,#3) + } + { + memd(r0++#8) = r5:4 + r5:4 = memd(r1+#16) + r1 = add(r1,#24) + loop0(1f,r3) + } + .falign +1: + { + memd(r0++#8) = r5:4 + r5:4 = memd(r1++#8) + }:endloop0 + { + memd(r0) = r5:4 + r0 -= add(r2,#-8) + jumpr r31 + } +FUNCTION_END __hexagon_memcpy_dwloop + .Lmemcpy_call: jump memcpy@PLT diff --git a/library/compiler-builtins/compiler-builtins/src/int/addsub.rs b/library/compiler-builtins/compiler-builtins/src/int/addsub.rs index b2b21fc2c4401..ab5e8e1b5d873 100644 --- a/library/compiler-builtins/compiler-builtins/src/int/addsub.rs +++ b/library/compiler-builtins/compiler-builtins/src/int/addsub.rs @@ -1,4 +1,4 @@ -use crate::int::{DInt, Int, MinInt}; +use crate::support::{DInt, Int, MinInt}; trait UAddSub: DInt + Int { fn uadd(self, other: Self) -> Self { diff --git a/library/compiler-builtins/compiler-builtins/src/int/big.rs b/library/compiler-builtins/compiler-builtins/src/int/big.rs deleted file mode 100644 index 8e06009090c09..0000000000000 --- a/library/compiler-builtins/compiler-builtins/src/int/big.rs +++ /dev/null @@ -1,295 +0,0 @@ -//! Integers used for wide operations, larger than `u128`. - -#![allow(unused)] - -use core::{fmt, ops}; - -use crate::int::{DInt, HInt, Int, MinInt}; - -const WORD_LO_MASK: u64 = 0x00000000ffffffff; -const WORD_HI_MASK: u64 = 0xffffffff00000000; -const WORD_FULL_MASK: u64 = 0xffffffffffffffff; -const U128_LO_MASK: u128 = u64::MAX as u128; -const U128_HI_MASK: u128 = (u64::MAX as u128) << 64; - -/// A 256-bit unsigned integer represented as 4 64-bit limbs. -/// -/// Each limb is a native-endian number, but the array is little-limb-endian. -#[allow(non_camel_case_types)] -#[derive(Clone, Copy, Debug, PartialEq, PartialOrd)] -pub struct u256(pub [u64; 4]); - -impl u256 { - pub const MAX: Self = Self([u64::MAX, u64::MAX, u64::MAX, u64::MAX]); - - /// Reinterpret as a signed integer - pub fn signed(self) -> i256 { - i256(self.0) - } -} - -/// A 256-bit signed integer represented as 4 64-bit limbs. -/// -/// Each limb is a native-endian number, but the array is little-limb-endian. -#[allow(non_camel_case_types)] -#[derive(Clone, Copy, Debug, PartialEq, PartialOrd)] -pub struct i256(pub [u64; 4]); - -impl i256 { - /// Reinterpret as an unsigned integer - pub fn unsigned(self) -> u256 { - u256(self.0) - } -} - -impl MinInt for u256 { - type OtherSign = i256; - - type Unsigned = u256; - - const SIGNED: bool = false; - const BITS: u32 = 256; - const ZERO: Self = Self([0u64; 4]); - const ONE: Self = Self([1, 0, 0, 0]); - const MIN: Self = Self([0u64; 4]); - const MAX: Self = Self([u64::MAX; 4]); -} - -impl MinInt for i256 { - type OtherSign = u256; - - type Unsigned = u256; - - const SIGNED: bool = false; - const BITS: u32 = 256; - const ZERO: Self = Self([0u64; 4]); - const ONE: Self = Self([1, 0, 0, 0]); - const MIN: Self = Self([0, 0, 0, 1 << 63]); - const MAX: Self = Self([u64::MAX, u64::MAX, u64::MAX, u64::MAX >> 1]); -} - -macro_rules! impl_common { - ($ty:ty) => { - impl ops::BitOr for $ty { - type Output = Self; - - fn bitor(mut self, rhs: Self) -> Self::Output { - self.0[0] |= rhs.0[0]; - self.0[1] |= rhs.0[1]; - self.0[2] |= rhs.0[2]; - self.0[3] |= rhs.0[3]; - self - } - } - - impl ops::Not for $ty { - type Output = Self; - - fn not(self) -> Self::Output { - Self([!self.0[0], !self.0[1], !self.0[2], !self.0[3]]) - } - } - - impl ops::Shl for $ty { - type Output = Self; - - fn shl(self, rhs: u32) -> Self::Output { - unimplemented!("only used to meet trait bounds") - } - } - }; -} - -impl_common!(i256); -impl_common!(u256); - -impl ops::Shr for u256 { - type Output = Self; - - fn shr(self, rhs: u32) -> Self::Output { - assert!(rhs < Self::BITS, "attempted to shift right with overflow"); - - if rhs == 0 { - return self; - } - - let mut ret = self; - let byte_shift = rhs / 64; - let bit_shift = rhs % 64; - - for idx in 0..4 { - let base_idx = idx + byte_shift as usize; - - let Some(base) = ret.0.get(base_idx) else { - ret.0[idx] = 0; - continue; - }; - - let mut new_val = base >> bit_shift; - - if let Some(new) = ret.0.get(base_idx + 1) { - new_val |= new.overflowing_shl(64 - bit_shift).0; - } - - ret.0[idx] = new_val; - } - - ret - } -} - -macro_rules! word { - (1, $val:expr) => { - (($val >> (32 * 3)) & Self::from(WORD_LO_MASK)) as u64 - }; - (2, $val:expr) => { - (($val >> (32 * 2)) & Self::from(WORD_LO_MASK)) as u64 - }; - (3, $val:expr) => { - (($val >> (32 * 1)) & Self::from(WORD_LO_MASK)) as u64 - }; - (4, $val:expr) => { - (($val >> (32 * 0)) & Self::from(WORD_LO_MASK)) as u64 - }; -} - -impl HInt for u128 { - type D = u256; - - fn widen(self) -> Self::D { - let w0 = self & u128::from(u64::MAX); - let w1 = (self >> u64::BITS) & u128::from(u64::MAX); - u256([w0 as u64, w1 as u64, 0, 0]) - } - - fn zero_widen(self) -> Self::D { - self.widen() - } - - fn zero_widen_mul(self, rhs: Self) -> Self::D { - let product11: u64 = word!(1, self) * word!(1, rhs); - let product12: u64 = word!(1, self) * word!(2, rhs); - let product13: u64 = word!(1, self) * word!(3, rhs); - let product14: u64 = word!(1, self) * word!(4, rhs); - let product21: u64 = word!(2, self) * word!(1, rhs); - let product22: u64 = word!(2, self) * word!(2, rhs); - let product23: u64 = word!(2, self) * word!(3, rhs); - let product24: u64 = word!(2, self) * word!(4, rhs); - let product31: u64 = word!(3, self) * word!(1, rhs); - let product32: u64 = word!(3, self) * word!(2, rhs); - let product33: u64 = word!(3, self) * word!(3, rhs); - let product34: u64 = word!(3, self) * word!(4, rhs); - let product41: u64 = word!(4, self) * word!(1, rhs); - let product42: u64 = word!(4, self) * word!(2, rhs); - let product43: u64 = word!(4, self) * word!(3, rhs); - let product44: u64 = word!(4, self) * word!(4, rhs); - - let sum0: u128 = u128::from(product44); - let sum1: u128 = u128::from(product34) + u128::from(product43); - let sum2: u128 = u128::from(product24) + u128::from(product33) + u128::from(product42); - let sum3: u128 = u128::from(product14) - + u128::from(product23) - + u128::from(product32) - + u128::from(product41); - let sum4: u128 = u128::from(product13) + u128::from(product22) + u128::from(product31); - let sum5: u128 = u128::from(product12) + u128::from(product21); - let sum6: u128 = u128::from(product11); - - let r0: u128 = - (sum0 & u128::from(WORD_FULL_MASK)) + ((sum1 & u128::from(WORD_LO_MASK)) << 32); - let r1: u128 = (sum0 >> 64) - + ((sum1 >> 32) & u128::from(WORD_FULL_MASK)) - + (sum2 & u128::from(WORD_FULL_MASK)) - + ((sum3 << 32) & u128::from(WORD_HI_MASK)); - - let (lo, carry) = r0.overflowing_add(r1 << 64); - let hi = (r1 >> 64) - + (sum1 >> 96) - + (sum2 >> 64) - + (sum3 >> 32) - + sum4 - + (sum5 << 32) - + (sum6 << 64) - + u128::from(carry); - - u256([ - (lo & U128_LO_MASK) as u64, - ((lo >> 64) & U128_LO_MASK) as u64, - (hi & U128_LO_MASK) as u64, - ((hi >> 64) & U128_LO_MASK) as u64, - ]) - } - - fn widen_mul(self, rhs: Self) -> Self::D { - self.zero_widen_mul(rhs) - } - - fn widen_hi(self) -> Self::D { - self.widen() << ::BITS - } -} - -impl HInt for i128 { - type D = i256; - - fn widen(self) -> Self::D { - let mut ret = self.unsigned().zero_widen().signed(); - if self.is_negative() { - ret.0[2] = u64::MAX; - ret.0[3] = u64::MAX; - } - ret - } - - fn zero_widen(self) -> Self::D { - self.unsigned().zero_widen().signed() - } - - fn zero_widen_mul(self, rhs: Self) -> Self::D { - self.unsigned().zero_widen_mul(rhs.unsigned()).signed() - } - - fn widen_mul(self, rhs: Self) -> Self::D { - unimplemented!("signed i128 widening multiply is not used") - } - - fn widen_hi(self) -> Self::D { - self.widen() << ::BITS - } -} - -impl DInt for u256 { - type H = u128; - - fn lo(self) -> Self::H { - let mut tmp = [0u8; 16]; - tmp[..8].copy_from_slice(&self.0[0].to_le_bytes()); - tmp[8..].copy_from_slice(&self.0[1].to_le_bytes()); - u128::from_le_bytes(tmp) - } - - fn hi(self) -> Self::H { - let mut tmp = [0u8; 16]; - tmp[..8].copy_from_slice(&self.0[2].to_le_bytes()); - tmp[8..].copy_from_slice(&self.0[3].to_le_bytes()); - u128::from_le_bytes(tmp) - } -} - -impl DInt for i256 { - type H = i128; - - fn lo(self) -> Self::H { - let mut tmp = [0u8; 16]; - tmp[..8].copy_from_slice(&self.0[0].to_le_bytes()); - tmp[8..].copy_from_slice(&self.0[1].to_le_bytes()); - i128::from_le_bytes(tmp) - } - - fn hi(self) -> Self::H { - let mut tmp = [0u8; 16]; - tmp[..8].copy_from_slice(&self.0[2].to_le_bytes()); - tmp[8..].copy_from_slice(&self.0[3].to_le_bytes()); - i128::from_le_bytes(tmp) - } -} diff --git a/library/compiler-builtins/compiler-builtins/src/int/leading_zeros.rs b/library/compiler-builtins/compiler-builtins/src/int/leading_zeros.rs index aa5cb39935ad8..c4d2569b3ab4e 100644 --- a/library/compiler-builtins/compiler-builtins/src/int/leading_zeros.rs +++ b/library/compiler-builtins/compiler-builtins/src/int/leading_zeros.rs @@ -4,12 +4,12 @@ // Compilers will insert the check for zero in cases where it is needed. #[cfg(feature = "unstable-public-internals")] -pub use implementation::{leading_zeros_default, leading_zeros_riscv}; +pub use implementation::{leading_zeros_condset, leading_zeros_default}; #[cfg(not(feature = "unstable-public-internals"))] -pub(crate) use implementation::{leading_zeros_default, leading_zeros_riscv}; +pub(crate) use implementation::{leading_zeros_condset, leading_zeros_default}; mod implementation { - use crate::int::{CastFrom, Int}; + use crate::support::{CastFrom, Int}; /// Returns the number of leading binary zeros in `x`. #[allow(dead_code)] @@ -82,14 +82,15 @@ mod implementation { // execution effects. Changing to using a LUT and branching is risky for smaller cores. } - // The above method does not compile well on RISC-V (because of the lack of predicated - // instructions), producing code with many branches or using an excessively long - // branchless solution. This method takes advantage of the set-if-less-than instruction on - // RISC-V that allows `(x >= power-of-two) as usize` to be branchless. + // The above method does not compile well on RISC-V and LoongArch (because of the lack + // of predicated instructions), producing code with many branches or using an + // excessively long branchless solution. This method takes advantage of the + // set-if-less-than instruction on RISC-V and LoongArch that allows + // `(x >= power-of-two) as usize` to be branchless. /// Returns the number of leading binary zeros in `x`. #[allow(dead_code)] - pub fn leading_zeros_riscv(x: I) -> usize + pub fn leading_zeros_condset(x: I) -> usize where usize: CastFrom, { @@ -99,7 +100,7 @@ mod implementation { // a temporary let mut t: u32; - // RISC-V does not have a set-if-greater-than-or-equal instruction and + // RISC-V and LoongArch do not have a set-if-greater-than-or-equal instruction and // `(x >= power-of-two) as usize` will get compiled into two instructions, but this is // still the most optimal method. A conditional set can only be turned into a single // immediate instruction if `x` is compared with an immediate `imm` (that can fit into @@ -146,8 +147,9 @@ mod implementation { intrinsics! { /// Returns the number of leading binary zeros in `x` pub extern "C" fn __clzsi2(x: u32) -> usize { - if cfg!(any(target_arch = "riscv32", target_arch = "riscv64")) { - leading_zeros_riscv(x) + if cfg!(any(target_arch = "loongarch32", target_arch = "loongarch64", + target_arch = "riscv32", target_arch = "riscv64")) { + leading_zeros_condset(x) } else { leading_zeros_default(x) } @@ -155,8 +157,9 @@ intrinsics! { /// Returns the number of leading binary zeros in `x` pub extern "C" fn __clzdi2(x: u64) -> usize { - if cfg!(any(target_arch = "riscv32", target_arch = "riscv64")) { - leading_zeros_riscv(x) + if cfg!(any(target_arch = "loongarch32", target_arch = "loongarch64", + target_arch = "riscv32", target_arch = "riscv64")) { + leading_zeros_condset(x) } else { leading_zeros_default(x) } diff --git a/library/compiler-builtins/compiler-builtins/src/int/mod.rs b/library/compiler-builtins/compiler-builtins/src/int/mod.rs index 518ccb23f8009..cd4011a933815 100644 --- a/library/compiler-builtins/compiler-builtins/src/int/mod.rs +++ b/library/compiler-builtins/compiler-builtins/src/int/mod.rs @@ -1,18 +1,10 @@ mod specialized_div_rem; pub mod addsub; -mod big; pub mod bswap; pub mod leading_zeros; pub mod mul; pub mod sdiv; pub mod shift; pub mod trailing_zeros; -mod traits; pub mod udiv; - -pub use big::{i256, u256}; -#[cfg(not(feature = "unstable-public-internals"))] -pub(crate) use traits::{CastFrom, CastInto, DInt, HInt, Int, MinInt}; -#[cfg(feature = "unstable-public-internals")] -pub use traits::{CastFrom, CastInto, DInt, HInt, Int, MinInt}; diff --git a/library/compiler-builtins/compiler-builtins/src/int/mul.rs b/library/compiler-builtins/compiler-builtins/src/int/mul.rs index 040c69342d148..9acfa091d195b 100644 --- a/library/compiler-builtins/compiler-builtins/src/int/mul.rs +++ b/library/compiler-builtins/compiler-builtins/src/int/mul.rs @@ -1,4 +1,4 @@ -use crate::int::{DInt, HInt, Int}; +use crate::support::{DInt, HInt, Int}; trait Mul: DInt + Int where @@ -98,11 +98,63 @@ impl_signed_mulo!(i64_overflowing_mul, i64, u64); impl_signed_mulo!(i128_overflowing_mul, i128, u128); intrinsics! { + // Ancient Egyptian/Ethiopian/Russian multiplication method + // see https://en.wikipedia.org/wiki/Ancient_Egyptian_multiplication + // + // This is a long-available stock algorithm; e.g. it is documented in + // Knuth's "The Art of Computer Programming" volume 2 (under the section + // "Evaluation of Powers") since at least the 2nd edition (1981). + // + // The main attraction of this method is that it implements (software) + // multiplication atop four simple operations: doubling, halving, checking + // if a value is even/odd, and addition. This is *not* considered to be the + // fastest multiplication method, but it may be amongst the simplest (and + // smallest with respect to code size). + // + // for reference, see also implementation from gcc + // https://raw.githubusercontent.com/gcc-mirror/gcc/master/libgcc/config/epiphany/mulsi3.c + // + // and from LLVM (in relatively readable RISC-V assembly): + // https://github.com/llvm/llvm-project/blob/main/compiler-rt/lib/builtins/riscv/int_mul_impl.inc + #[cfg(any(target_arch = "riscv32", target_arch = "riscv64", target_arch = "m68k"))] + pub extern "C" fn __mulsi3(a: u32, b: u32) -> u32 { + let (mut a, mut b) = (a, b); + let mut r: u32 = 0; + + while a > 0 { + if a & 1 > 0 { + r = r.wrapping_add(b); + } + a >>= 1; + b <<= 1; + } + + r + } + #[maybe_use_optimized_c_shim] #[arm_aeabi_alias = __aeabi_lmul] - #[cfg(any(not(any(target_arch = "riscv32", target_arch = "riscv64")), target_feature = "m"))] pub extern "C" fn __muldi3(a: u64, b: u64) -> u64 { - a.mul(b) + #[cfg(all(any(target_arch = "riscv32", target_arch = "riscv64"), not(target_feature = "m")))] + { + let (mut a, mut b) = (a, b); + let mut r: u64 = 0; + + while a > 0 { + if a & 1 > 0 { + r = r.wrapping_add(b); + } + a >>= 1; + b <<= 1; + } + + r + } + + #[cfg(not(all(any(target_arch = "riscv32", target_arch = "riscv64"), not(target_feature = "m"))))] + { + a.mul(b) + } } pub extern "C" fn __multi3(a: i128, b: i128) -> i128 { @@ -121,13 +173,24 @@ intrinsics! { mul } - #[unadjusted_on_win64] + #[cfg(not(all(target_os = "uefi", target_arch = "x86_64")))] + pub extern "C" fn __muloti4(a: i128, b: i128, oflow: &mut i32) -> i128 { let (mul, o) = i128_overflowing_mul(a, b); *oflow = o as i32; mul } + #[cfg(all(target_os = "uefi", target_arch = "x86_64"))] + pub extern "C" fn __muloti4(a_lo: u64, a_hi: u64, b_lo: u64, b_hi: u64, oflow: &mut i32) -> i128 { + let (mul, o) = i128_overflowing_mul( + (i128::from(a_hi) << 64) | i128::from(a_lo), + (i128::from(b_hi) << 64) | i128::from(b_lo), + ); + *oflow = o as i32; + mul + } + pub extern "C" fn __rust_i128_mulo(a: i128, b: i128, oflow: &mut i32) -> i128 { let (mul, o) = i128_overflowing_mul(a, b); *oflow = o.into(); @@ -139,4 +202,5 @@ intrinsics! { *oflow = o.into(); mul } + } diff --git a/library/compiler-builtins/compiler-builtins/src/int/shift.rs b/library/compiler-builtins/compiler-builtins/src/int/shift.rs index a85c1b33d6714..f5cac9ad4e367 100644 --- a/library/compiler-builtins/compiler-builtins/src/int/shift.rs +++ b/library/compiler-builtins/compiler-builtins/src/int/shift.rs @@ -1,4 +1,4 @@ -use crate::int::{DInt, HInt, Int, MinInt}; +use crate::support::{DInt, HInt, Int, MinInt}; trait Ashl: DInt { /// Returns `a << b`, requires `b < Self::BITS` diff --git a/library/compiler-builtins/compiler-builtins/src/int/specialized_div_rem/mod.rs b/library/compiler-builtins/compiler-builtins/src/int/specialized_div_rem/mod.rs index 5ffe1f59b4db6..e5324cdbd941e 100644 --- a/library/compiler-builtins/compiler-builtins/src/int/specialized_div_rem/mod.rs +++ b/library/compiler-builtins/compiler-builtins/src/int/specialized_div_rem/mod.rs @@ -97,6 +97,13 @@ const USE_LZ: bool = { // The 'Zbb' Basic Bit-Manipulation extension on RISC-V // determines if a CLZ assembly instruction exists cfg!(target_feature = "zbb") + } else if cfg!(any( + target_arch = "loongarch32", + target_arch = "loongarch64" + )) { + // The '32s' 32-bit standard feature on LoongArch + // determines if a CLZ assembly instruction exists + cfg!(target_feature = "32s") } else { // All other common targets Rust supports should have CLZ instructions true @@ -144,7 +151,7 @@ fn u64_by_u64_div_rem(duo: u64, div: u64) -> (u64, u64) { target_family = "wasm", not(any(target_pointer_width = "16", target_pointer_width = "32")), ), - not(all(not(feature = "no-asm"), target_arch = "x86_64")), + not(all(feature = "arch", target_arch = "x86_64")), not(any(target_arch = "sparc", target_arch = "sparc64")) ))] impl_trifecta!( @@ -165,7 +172,7 @@ impl_trifecta!( target_family = "wasm", not(any(target_pointer_width = "16", target_pointer_width = "32")), )), - not(all(not(feature = "no-asm"), target_arch = "x86_64")), + not(all(feature = "arch", target_arch = "x86_64")), not(any(target_arch = "sparc", target_arch = "sparc64")) ))] impl_delegate!( @@ -186,7 +193,7 @@ impl_delegate!( /// /// If the quotient does not fit in a `u64`, a floating point exception occurs. /// If `div == 0`, then a division by zero exception occurs. -#[cfg(all(not(feature = "no-asm"), target_arch = "x86_64"))] +#[cfg(all(feature = "arch", target_arch = "x86_64"))] #[inline] unsafe fn u128_by_u64_div_rem(duo: u128, div: u64) -> (u64, u64) { let duo_lo = duo as u64; @@ -208,7 +215,7 @@ unsafe fn u128_by_u64_div_rem(duo: u128, div: u64) -> (u64, u64) { } // use `asymmetric` instead of `trifecta` on x86_64 -#[cfg(all(not(feature = "no-asm"), target_arch = "x86_64"))] +#[cfg(all(feature = "arch", target_arch = "x86_64"))] impl_asymmetric!( u128_div_rem, zero_div_fn, @@ -237,7 +244,7 @@ fn u32_by_u32_div_rem(duo: u32, div: u32) -> (u32, u32) { // When not on x86 and the pointer width is not 64, use `delegate` since the division size is larger // than register size. #[cfg(all( - not(all(not(feature = "no-asm"), target_arch = "x86")), + not(all(feature = "arch", target_arch = "x86")), not(target_pointer_width = "64") ))] impl_delegate!( @@ -254,7 +261,7 @@ impl_delegate!( // When not on x86 and the pointer width is 64, use `binary_long`. #[cfg(all( - not(all(not(feature = "no-asm"), target_arch = "x86")), + not(all(feature = "arch", target_arch = "x86")), target_pointer_width = "64" ))] impl_binary_long!( @@ -272,7 +279,7 @@ impl_binary_long!( /// /// If the quotient does not fit in a `u32`, a floating point exception occurs. /// If `div == 0`, then a division by zero exception occurs. -#[cfg(all(not(feature = "no-asm"), target_arch = "x86"))] +#[cfg(all(feature = "arch", target_arch = "x86"))] #[inline] unsafe fn u64_by_u32_div_rem(duo: u64, div: u32) -> (u32, u32) { let duo_lo = duo as u32; @@ -294,7 +301,7 @@ unsafe fn u64_by_u32_div_rem(duo: u64, div: u32) -> (u32, u32) { } // use `asymmetric` instead of `delegate` on x86 -#[cfg(all(not(feature = "no-asm"), target_arch = "x86"))] +#[cfg(all(feature = "arch", target_arch = "x86"))] impl_asymmetric!( u64_div_rem, zero_div_fn, diff --git a/library/compiler-builtins/compiler-builtins/src/int/trailing_zeros.rs b/library/compiler-builtins/compiler-builtins/src/int/trailing_zeros.rs index 1b0ae5b73ad24..f42e9926dbb11 100644 --- a/library/compiler-builtins/compiler-builtins/src/int/trailing_zeros.rs +++ b/library/compiler-builtins/compiler-builtins/src/int/trailing_zeros.rs @@ -4,7 +4,7 @@ pub use implementation::trailing_zeros; pub(crate) use implementation::trailing_zeros; mod implementation { - use crate::int::{CastFrom, Int}; + use crate::support::{CastFrom, Int}; /// Returns number of trailing binary zeros in `x`. #[allow(dead_code)] diff --git a/library/compiler-builtins/compiler-builtins/src/int/traits.rs b/library/compiler-builtins/compiler-builtins/src/int/traits.rs deleted file mode 100644 index 25b9718ad53fb..0000000000000 --- a/library/compiler-builtins/compiler-builtins/src/int/traits.rs +++ /dev/null @@ -1,99 +0,0 @@ -pub use crate::support::{CastFrom, CastInto, Int, MinInt}; - -/// Trait for integers twice the bit width of another integer. This is implemented for all -/// primitives except for `u8`, because there is not a smaller primitive. -pub trait DInt: MinInt { - /// Integer that is half the bit width of the integer this trait is implemented for - type H: HInt; - - /// Returns the low half of `self` - fn lo(self) -> Self::H; - /// Returns the high half of `self` - fn hi(self) -> Self::H; - /// Returns the low and high halves of `self` as a tuple - fn lo_hi(self) -> (Self::H, Self::H) { - (self.lo(), self.hi()) - } - /// Constructs an integer using lower and higher half parts - fn from_lo_hi(lo: Self::H, hi: Self::H) -> Self { - lo.zero_widen() | hi.widen_hi() - } -} - -/// Trait for integers half the bit width of another integer. This is implemented for all -/// primitives except for `u128`, because it there is not a larger primitive. -pub trait HInt: Int { - /// Integer that is double the bit width of the integer this trait is implemented for - type D: DInt + MinInt; - - // NB: some of the below methods could have default implementations (e.g. `widen_hi`), but for - // unknown reasons this can cause infinite recursion when optimizations are disabled. See - // for context. - - /// Widens (using default extension) the integer to have double bit width - fn widen(self) -> Self::D; - /// Widens (zero extension only) the integer to have double bit width. This is needed to get - /// around problems with associated type bounds (such as `Int`) being unstable - fn zero_widen(self) -> Self::D; - /// Widens the integer to have double bit width and shifts the integer into the higher bits - fn widen_hi(self) -> Self::D; - /// Widening multiplication with zero widening. This cannot overflow. - fn zero_widen_mul(self, rhs: Self) -> Self::D; - /// Widening multiplication. This cannot overflow. - fn widen_mul(self, rhs: Self) -> Self::D; -} - -macro_rules! impl_d_int { - ($($X:ident $D:ident),*) => { - $( - impl DInt for $D { - type H = $X; - - fn lo(self) -> Self::H { - self as $X - } - fn hi(self) -> Self::H { - (self >> <$X as MinInt>::BITS) as $X - } - } - )* - }; -} - -macro_rules! impl_h_int { - ($($H:ident $uH:ident $X:ident),*) => { - $( - impl HInt for $H { - type D = $X; - - fn widen(self) -> Self::D { - self as $X - } - fn zero_widen(self) -> Self::D { - (self as $uH) as $X - } - fn zero_widen_mul(self, rhs: Self) -> Self::D { - self.zero_widen().wrapping_mul(rhs.zero_widen()) - } - fn widen_mul(self, rhs: Self) -> Self::D { - self.widen().wrapping_mul(rhs.widen()) - } - fn widen_hi(self) -> Self::D { - (self as $X) << ::BITS - } - } - )* - }; -} - -impl_d_int!(u8 u16, u16 u32, u32 u64, u64 u128, i8 i16, i16 i32, i32 i64, i64 i128); -impl_h_int!( - u8 u8 u16, - u16 u16 u32, - u32 u32 u64, - u64 u64 u128, - i8 u8 i16, - i16 u16 i32, - i32 u32 i64, - i64 u64 i128 -); diff --git a/library/compiler-builtins/compiler-builtins/src/lib.rs b/library/compiler-builtins/compiler-builtins/src/lib.rs index 342427aca9c7d..829475dcd42e2 100644 --- a/library/compiler-builtins/compiler-builtins/src/lib.rs +++ b/library/compiler-builtins/compiler-builtins/src/lib.rs @@ -1,5 +1,7 @@ #![cfg_attr(feature = "compiler-builtins", compiler_builtins)] -#![cfg_attr(all(target_family = "wasm"), feature(wasm_numeric_instr))] +#![no_builtins] +#![no_std] +// #![feature(abi_custom)] #![feature(abi_unadjusted)] #![feature(asm_experimental_arch)] @@ -7,24 +9,20 @@ #![feature(compiler_builtins)] #![feature(core_intrinsics)] #![feature(linkage)] -#![feature(naked_functions)] #![feature(repr_simd)] #![feature(macro_metavar_expr_concat)] #![feature(rustc_attrs)] -#![feature(float_bits_const)] #![cfg_attr(f16_enabled, feature(f16))] #![cfg_attr(f128_enabled, feature(f128))] -#![no_builtins] -#![no_std] +#![cfg_attr(all(target_family = "wasm"), feature(wasm_numeric_instr))] +// +#![allow(unstable_name_collisions)] // FIXME(float_bits_const): remove when stable #![allow(unused_features)] #![allow(internal_features)] // `mem::swap` cannot be used because it may generate references to memcpy in unoptimized code. #![allow(clippy::manual_swap)] // Support compiling on both stage0 and stage1 which may differ in supported stable features. #![allow(stable_features)] -// By default, disallow this as it is forbidden in edition 2024. There is a lot of unsafe code to -// be migrated, however, so exceptions exist. -#![warn(unsafe_op_in_unsafe_fn)] // We disable #[no_mangle] for tests so that we can verify the test results // against the native compiler-rt implementations of the builtins. @@ -46,8 +44,12 @@ pub mod float; pub mod int; pub mod math; pub mod mem; +pub mod sync; // `libm` expects its `support` module to be available in the crate root. +#[cfg(feature = "unstable-public-internals")] +pub use math::libm_math::support; +#[cfg(not(feature = "unstable-public-internals"))] use math::libm_math::support; #[cfg(target_arch = "arm")] @@ -56,15 +58,16 @@ pub mod arm; #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] pub mod aarch64; -#[cfg(all(target_arch = "aarch64", target_feature = "outline-atomics"))] -pub mod aarch64_outline_atomics; - +// Note that we enable the module on "mangled-names" because that is the default feature +// in the builtins-test tests. So this is a way of enabling the module during testing. #[cfg(all( - kernel_user_helpers, - any(target_os = "linux", target_os = "android"), - target_arch = "arm" + target_arch = "aarch64", + any( + target_feature = "outline-atomics", + feature = "unstable-public-internals" + ) ))] -pub mod arm_linux; +pub mod aarch64_outline_atomics; #[cfg(target_arch = "avr")] pub mod avr; @@ -72,9 +75,6 @@ pub mod avr; #[cfg(target_arch = "hexagon")] pub mod hexagon; -#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] -pub mod riscv; - #[cfg(target_arch = "x86")] pub mod x86; diff --git a/library/compiler-builtins/compiler-builtins/src/macros.rs b/library/compiler-builtins/compiler-builtins/src/macros.rs index 203cd0949ac52..25bdbcf3f975e 100644 --- a/library/compiler-builtins/compiler-builtins/src/macros.rs +++ b/library/compiler-builtins/compiler-builtins/src/macros.rs @@ -108,6 +108,25 @@ macro_rules! intrinsics { intrinsics!($($rest)*); ); + // Support cfg: + ( + #[cfg($e:meta)] + $(#[$($attrs:tt)*])* + pub extern $abi:tt fn $name:ident( $($argname:ident: $ty:ty),* ) $(-> $ret:ty)? { + $($body:tt)* + } + $($rest:tt)* + ) => ( + #[cfg($e)] + intrinsics! { + $(#[$($attrs)*])* + pub extern $abi fn $name($($argname: $ty),*) $(-> $ret)? { + $($body)* + } + } + + intrinsics!($($rest)*); + ); // Right now there's a bunch of architecture-optimized intrinsics in the // stock compiler-rt implementation. Not all of these have been ported over @@ -182,36 +201,6 @@ macro_rules! intrinsics { intrinsics!($($rest)*); ); - // Like aapcs above we recognize an attribute for the "unadjusted" abi on - // win64 for some methods. - ( - #[unadjusted_on_win64] - $(#[$($attr:tt)*])* - pub extern $abi:tt fn $name:ident( $($argname:ident: $ty:ty),* ) $(-> $ret:ty)? { - $($body:tt)* - } - - $($rest:tt)* - ) => ( - #[cfg(all(any(windows, target_os = "cygwin", all(target_os = "uefi", target_arch = "x86_64")), target_pointer_width = "64"))] - intrinsics! { - $(#[$($attr)*])* - pub extern "unadjusted" fn $name( $($argname: $ty),* ) $(-> $ret)? { - $($body)* - } - } - - #[cfg(not(all(any(windows, target_os = "cygwin", all(target_os = "uefi", target_arch = "x86_64")), target_pointer_width = "64")))] - intrinsics! { - $(#[$($attr)*])* - pub extern $abi fn $name( $($argname: $ty),* ) $(-> $ret)? { - $($body)* - } - } - - intrinsics!($($rest)*); - ); - // `arm_aeabi_alias` would conflict with `f16_apple_{arg,ret}_abi` not handled here. Avoid macro ambiguity by combining in a // single `#[]`. ( @@ -254,7 +243,7 @@ macro_rules! intrinsics { $($body)* } - #[cfg(all(target_vendor = "apple", any(target_arch = "x86", target_arch = "x86_64"), not(feature = "mangled-names")))] + #[cfg(all(target_vendor = "apple", any(target_arch = "x86", target_arch = "x86_64"), feature = "unmangled-names"))] mod $name { #[unsafe(no_mangle)] #[cfg_attr(not(any(all(windows, target_env = "gnu"), target_os = "cygwin")), linkage = "weak")] @@ -290,7 +279,7 @@ macro_rules! intrinsics { $($body)* } - #[cfg(all(target_vendor = "apple", any(target_arch = "x86", target_arch = "x86_64"), not(feature = "mangled-names")))] + #[cfg(all(target_vendor = "apple", any(target_arch = "x86", target_arch = "x86_64"), feature = "unmangled-names"))] mod $name { #[unsafe(no_mangle)] #[cfg_attr(not(any(all(windows, target_env = "gnu"), target_os = "cygwin")), linkage = "weak")] @@ -331,7 +320,7 @@ macro_rules! intrinsics { $($body)* } - #[cfg(all(target_arch = "arm", not(feature = "mangled-names")))] + #[cfg(all(target_arch = "arm", feature = "unmangled-names"))] mod $name { #[unsafe(no_mangle)] #[cfg_attr(not(any(all(windows, target_env = "gnu"), target_os = "cygwin")), linkage = "weak")] @@ -341,7 +330,7 @@ macro_rules! intrinsics { } } - #[cfg(all(target_arch = "arm", not(feature = "mangled-names")))] + #[cfg(all(target_arch = "arm", feature = "unmangled-names"))] mod $alias { #[unsafe(no_mangle)] #[cfg_attr(not(any(all(windows, target_env = "gnu"), target_os = "cygwin")), linkage = "weak")] @@ -392,7 +381,7 @@ macro_rules! intrinsics { intrinsics!($($rest)*); ); - // C mem* functions are only generated when the "mem" feature is enabled. + // C mem* functions are only exposed via `no_mangle` when the "mem" feature is enabled. ( #[mem_builtin] $(#[$($attr:tt)*])* @@ -407,7 +396,7 @@ macro_rules! intrinsics { $($body)* } - #[cfg(all(feature = "mem", not(feature = "mangled-names")))] + #[cfg(all(feature = "mem", feature = "unmangled-names"))] mod $name { $(#[$($attr)*])* #[unsafe(no_mangle)] @@ -435,7 +424,7 @@ macro_rules! intrinsics { pub mod $name { #[unsafe(naked)] $(#[$($attr)*])* - #[cfg_attr(not(feature = "mangled-names"), unsafe(no_mangle))] + #[cfg_attr(feature = "unmangled-names", unsafe(no_mangle))] #[cfg_attr(not(any(all(windows, target_env = "gnu"), target_os = "cygwin")), linkage = "weak")] pub unsafe extern $abi fn $name( $($argname: $ty),* ) $(-> $ret)? { $($body)* @@ -470,7 +459,7 @@ macro_rules! intrinsics { $($body)* } - #[cfg(not(feature = "mangled-names"))] + #[cfg(feature = "unmangled-names")] mod $name { $(#[$($attr)*])* #[unsafe(no_mangle)] diff --git a/library/compiler-builtins/compiler-builtins/src/math/mod.rs b/library/compiler-builtins/compiler-builtins/src/math/mod.rs index 62d7296741057..3dfa3863bb770 100644 --- a/library/compiler-builtins/compiler-builtins/src/math/mod.rs +++ b/library/compiler-builtins/compiler-builtins/src/math/mod.rs @@ -28,8 +28,10 @@ pub mod full_availability { fn fdimf16(x: f16, y: f16) -> f16; fn floorf16(x: f16) -> f16; fn fmaxf16(x: f16, y: f16) -> f16; + fn fmaximum_numf16(x: f16, y: f16) -> f16; fn fmaximumf16(x: f16, y: f16) -> f16; fn fminf16(x: f16, y: f16) -> f16; + fn fminimum_numf16(x: f16, y: f16) -> f16; fn fminimumf16(x: f16, y: f16) -> f16; fn fmodf16(x: f16, y: f16) -> f16; fn rintf16(x: f16) -> f16; @@ -81,8 +83,12 @@ pub mod full_availability { // however, so we still provide a fallback. libm_intrinsics! { fn fmaximum(x: f64, y: f64) -> f64; + fn fmaximum_num(x: f64, y: f64) -> f64; + fn fmaximum_numf(x: f32, y: f32) -> f32; fn fmaximumf(x: f32, y: f32) -> f32; fn fminimum(x: f64, y: f64) -> f64; + fn fminimum_num(x: f64, y: f64) -> f64; + fn fminimum_numf(x: f32, y: f32) -> f32; fn fminimumf(x: f32, y: f32) -> f32; fn roundeven(x: f64) -> f64; fn roundevenf(x: f32) -> f32; @@ -97,8 +103,10 @@ pub mod full_availability { fn floorf128(x: f128) -> f128; fn fmaf128(x: f128, y: f128, z: f128) -> f128; fn fmaxf128(x: f128, y: f128) -> f128; + fn fmaximum_numf128(x: f128, y: f128) -> f128; fn fmaximumf128(x: f128, y: f128) -> f128; fn fminf128(x: f128, y: f128) -> f128; + fn fminimum_numf128(x: f128, y: f128) -> f128; fn fminimumf128(x: f128, y: f128) -> f128; fn fmodf128(x: f128, y: f128) -> f128; fn rintf128(x: f128) -> f128; @@ -136,8 +144,12 @@ pub mod partial_availability { libm_intrinsics! { fn acos(x: f64) -> f64; fn acosf(n: f32) -> f32; + fn acosh(x: f64) -> f64; + fn acoshf(x: f32) -> f32; fn asin(x: f64) -> f64; fn asinf(n: f32) -> f32; + fn asinh(x: f64) -> f64; + fn asinhf(x: f32) -> f32; fn atan(x: f64) -> f64; fn atan2(x: f64, y: f64) -> f64; fn atan2f(a: f32, b: f32) -> f32; diff --git a/library/compiler-builtins/compiler-builtins/src/mem/impls.rs b/library/compiler-builtins/compiler-builtins/src/mem/impls.rs index da16dee25ce54..c7cfa6fb4618e 100644 --- a/library/compiler-builtins/compiler-builtins/src/mem/impls.rs +++ b/library/compiler-builtins/compiler-builtins/src/mem/impls.rs @@ -9,14 +9,15 @@ // ptr::add in these loops will wrap. And if compiler-builtins is compiled with cfg(ub_checks), // this will fail a UB check at runtime. // -// Since this scenario is UB, we are within our rights hit this check and halt execution... +// Since this scenario is UB, we are within our rights to hit this check and halt execution... // But we are also within our rights to try to make it work. // We use wrapping_add/wrapping_sub for pointer arithmetic in this module in an attempt to support // this use. Of course this is not a guarantee that such use will work, it just means that this // crate doing wrapping pointer arithmetic with a method that must not wrap won't be the problem if // something does go wrong at runtime. use core::ffi::c_int; -use core::intrinsics::likely; + +use crate::support::cold_path; const WORD_SIZE: usize = core::mem::size_of::(); const WORD_MASK: usize = WORD_SIZE - 1; @@ -34,7 +35,7 @@ const WORD_COPY_THRESHOLD: usize = if 2 * WORD_SIZE > 16 { 16 }; -#[cfg(feature = "mem-unaligned")] +#[cfg(mem_unaligned)] unsafe fn read_usize_unaligned(x: *const usize) -> usize { // Do not use `core::ptr::read_unaligned` here, since it calls `copy_nonoverlapping` which // is translated to memcpy in LLVM. @@ -45,7 +46,7 @@ unsafe fn read_usize_unaligned(x: *const usize) -> usize { /// Loads a `T`-sized chunk from `src` into `dst` at offset `offset`, if that does not exceed /// `load_sz`. The offset pointers must both be `T`-aligned. Returns the new offset, advanced by the /// chunk size if a load happened. -#[cfg(not(feature = "mem-unaligned"))] +#[cfg(not(mem_unaligned))] #[inline(always)] unsafe fn load_chunk_aligned( src: *const usize, @@ -65,7 +66,7 @@ unsafe fn load_chunk_aligned( /// Load `load_sz` many bytes from `src`, which must be usize-aligned. Acts as if we did a `usize` /// read with the out-of-bounds part filled with 0s. /// `load_sz` be strictly less than `WORD_SIZE`. -#[cfg(not(feature = "mem-unaligned"))] +#[cfg(not(mem_unaligned))] #[inline(always)] unsafe fn load_aligned_partial(src: *const usize, load_sz: usize) -> usize { debug_assert!(load_sz < WORD_SIZE); @@ -87,7 +88,7 @@ unsafe fn load_aligned_partial(src: *const usize, load_sz: usize) -> usize { /// `usize`-aligned. The bytes are returned as the *last* bytes of the return value, i.e., this acts /// as if we had done a `usize` read from `src`, with the out-of-bounds part filled with 0s. /// `load_sz` be strictly less than `WORD_SIZE`. -#[cfg(not(feature = "mem-unaligned"))] +#[cfg(not(mem_unaligned))] #[inline(always)] unsafe fn load_aligned_end_partial(src: *const usize, load_sz: usize) -> usize { debug_assert!(load_sz < WORD_SIZE); @@ -135,7 +136,7 @@ pub unsafe fn copy_forward(mut dest: *mut u8, mut src: *const u8, mut n: usize) /// `n` is in units of bytes, but must be a multiple of the word size and must not be 0. /// `src` *must not* be `usize`-aligned. - #[cfg(not(feature = "mem-unaligned"))] + #[cfg(not(mem_unaligned))] #[inline(always)] unsafe fn copy_forward_misaligned_words(dest: *mut u8, src: *const u8, n: usize) { debug_assert!(n > 0 && n % WORD_SIZE == 0); @@ -184,7 +185,7 @@ pub unsafe fn copy_forward(mut dest: *mut u8, mut src: *const u8, mut n: usize) /// `n` is in units of bytes, but must be a multiple of the word size and must not be 0. /// `src` *must not* be `usize`-aligned. - #[cfg(feature = "mem-unaligned")] + #[cfg(mem_unaligned)] #[inline(always)] unsafe fn copy_forward_misaligned_words(dest: *mut u8, src: *const u8, n: usize) { let mut dest_usize = dest as *mut usize; @@ -209,9 +210,10 @@ pub unsafe fn copy_forward(mut dest: *mut u8, mut src: *const u8, mut n: usize) let n_words = n & !WORD_MASK; let src_misalignment = src as usize & WORD_MASK; - if likely(src_misalignment == 0) { + if src_misalignment == 0 { copy_forward_aligned_words(dest, src, n_words); } else { + cold_path(); copy_forward_misaligned_words(dest, src, n_words); } dest = dest.wrapping_add(n_words); @@ -250,7 +252,7 @@ pub unsafe fn copy_backward(dest: *mut u8, src: *const u8, mut n: usize) { /// `n` is in units of bytes, but must be a multiple of the word size and must not be 0. /// `src` *must not* be `usize`-aligned. - #[cfg(not(feature = "mem-unaligned"))] + #[cfg(not(mem_unaligned))] #[inline(always)] unsafe fn copy_backward_misaligned_words(dest: *mut u8, src: *const u8, n: usize) { debug_assert!(n > 0 && n % WORD_SIZE == 0); @@ -299,7 +301,7 @@ pub unsafe fn copy_backward(dest: *mut u8, src: *const u8, mut n: usize) { /// `n` is in units of bytes, but must be a multiple of the word size and must not be 0. /// `src` *must not* be `usize`-aligned. - #[cfg(feature = "mem-unaligned")] + #[cfg(mem_unaligned)] #[inline(always)] unsafe fn copy_backward_misaligned_words(dest: *mut u8, src: *const u8, n: usize) { let mut dest_usize = dest as *mut usize; @@ -327,9 +329,10 @@ pub unsafe fn copy_backward(dest: *mut u8, src: *const u8, mut n: usize) { let n_words = n & !WORD_MASK; let src_misalignment = src as usize & WORD_MASK; - if likely(src_misalignment == 0) { + if src_misalignment == 0 { copy_backward_aligned_words(dest, src, n_words); } else { + cold_path(); copy_backward_misaligned_words(dest, src, n_words); } dest = dest.wrapping_sub(n_words); @@ -368,7 +371,7 @@ pub unsafe fn set_bytes(mut s: *mut u8, c: u8, mut n: usize) { } } - if likely(n >= WORD_COPY_THRESHOLD) { + if n >= WORD_COPY_THRESHOLD { // Align s // Because of n >= 2 * WORD_SIZE, dst_misalignment < n let misalignment = (s as usize).wrapping_neg() & WORD_MASK; @@ -380,6 +383,8 @@ pub unsafe fn set_bytes(mut s: *mut u8, c: u8, mut n: usize) { set_bytes_words(s, c, n_words); s = s.wrapping_add(n_words); n -= n_words; + } else { + cold_path(); } set_bytes_bytes(s, c, n); } diff --git a/library/compiler-builtins/compiler-builtins/src/mem/mod.rs b/library/compiler-builtins/compiler-builtins/src/mem/mod.rs index a227f60a2949b..e3c701892b671 100644 --- a/library/compiler-builtins/compiler-builtins/src/mem/mod.rs +++ b/library/compiler-builtins/compiler-builtins/src/mem/mod.rs @@ -2,22 +2,23 @@ #![allow(clippy::style)] // FIXME(e2024): this eventually needs to be removed. #![allow(unsafe_op_in_unsafe_fn)] +// FIXME(bench): remove when the benchmark rustc version is updated +#![allow(unknown_lints)] // memcpy/memmove/memset have optimized implementations on some architectures -#[cfg_attr( - all(not(feature = "no-asm"), target_arch = "x86_64"), - path = "x86_64.rs" -)] +#[cfg_attr(all(feature = "arch", target_arch = "x86_64"), path = "x86_64.rs")] mod impls; intrinsics! { #[mem_builtin] + #[allow(suspicious_runtime_symbol_definitions)] pub unsafe extern "C" fn memcpy(dest: *mut u8, src: *const u8, n: usize) -> *mut u8 { impls::copy_forward(dest, src, n); dest } #[mem_builtin] + #[allow(suspicious_runtime_symbol_definitions)] pub unsafe extern "C" fn memmove(dest: *mut u8, src: *const u8, n: usize) -> *mut u8 { let delta = (dest as usize).wrapping_sub(src as usize); if delta >= n { @@ -31,17 +32,20 @@ intrinsics! { } #[mem_builtin] + #[allow(suspicious_runtime_symbol_definitions)] pub unsafe extern "C" fn memset(s: *mut u8, c: core::ffi::c_int, n: usize) -> *mut u8 { impls::set_bytes(s, c as u8, n); s } #[mem_builtin] + #[allow(suspicious_runtime_symbol_definitions)] pub unsafe extern "C" fn memcmp(s1: *const u8, s2: *const u8, n: usize) -> core::ffi::c_int { impls::compare_bytes(s1, s2, n) } #[mem_builtin] + #[allow(suspicious_runtime_symbol_definitions)] pub unsafe extern "C" fn bcmp(s1: *const u8, s2: *const u8, n: usize) -> core::ffi::c_int { memcmp(s1, s2, n) } diff --git a/library/compiler-builtins/compiler-builtins/src/mem/x86_64.rs b/library/compiler-builtins/compiler-builtins/src/mem/x86_64.rs index bf36a286ac951..3b32f71cd138a 100644 --- a/library/compiler-builtins/compiler-builtins/src/mem/x86_64.rs +++ b/library/compiler-builtins/compiler-builtins/src/mem/x86_64.rs @@ -168,7 +168,7 @@ pub unsafe fn compare_bytes(a: *const u8, b: *const u8, n: usize) -> i32 { c16(a.cast(), b.cast(), n) } -// In order to process more than on byte simultaneously when executing strlen, +// In order to process more than one byte simultaneously when executing strlen, // two things must be considered: // * An n byte read with an n-byte aligned address will never cross // a page boundary and will always succeed. Any smaller alignment @@ -198,8 +198,8 @@ pub unsafe fn c_string_length(mut s: *const core::ffi::c_char) -> usize { s = s.add(1); } - // Shave of the least significand bits to align the address to a 16 - // byte boundary. The shaved of bits are used to correct the first iteration. + // Shave off the least significant bits to align the address to a 16 + // byte boundary. The shaved off bits are used to correct the first iteration. let align = s as usize & 15; let mut s = ((s as usize) - align) as *const __m128i; diff --git a/library/compiler-builtins/compiler-builtins/src/probestack.rs b/library/compiler-builtins/compiler-builtins/src/probestack.rs index 1cab64ea113c5..c4a2eeb0e0178 100644 --- a/library/compiler-builtins/compiler-builtins/src/probestack.rs +++ b/library/compiler-builtins/compiler-builtins/src/probestack.rs @@ -41,7 +41,7 @@ //! probes on any other architecture like ARM or PowerPC64. LLVM I'm sure would //! be more than welcome to accept such a change! -#![cfg(not(feature = "mangled-names"))] +#![cfg(feature = "unmangled-names")] // Windows and Cygwin already has builtins to do this. #![cfg(not(any(windows, target_os = "cygwin")))] // We only define stack probing for these architectures today. diff --git a/library/compiler-builtins/compiler-builtins/src/riscv.rs b/library/compiler-builtins/compiler-builtins/src/riscv.rs deleted file mode 100644 index bf31255334193..0000000000000 --- a/library/compiler-builtins/compiler-builtins/src/riscv.rs +++ /dev/null @@ -1,50 +0,0 @@ -intrinsics! { - // Ancient Egyptian/Ethiopian/Russian multiplication method - // see https://en.wikipedia.org/wiki/Ancient_Egyptian_multiplication - // - // This is a long-available stock algorithm; e.g. it is documented in - // Knuth's "The Art of Computer Programming" volume 2 (under the section - // "Evaluation of Powers") since at least the 2nd edition (1981). - // - // The main attraction of this method is that it implements (software) - // multiplication atop four simple operations: doubling, halving, checking - // if a value is even/odd, and addition. This is *not* considered to be the - // fastest multiplication method, but it may be amongst the simplest (and - // smallest with respect to code size). - // - // for reference, see also implementation from gcc - // https://raw.githubusercontent.com/gcc-mirror/gcc/master/libgcc/config/epiphany/mulsi3.c - // - // and from LLVM (in relatively readable RISC-V assembly): - // https://github.com/llvm/llvm-project/blob/main/compiler-rt/lib/builtins/riscv/int_mul_impl.inc - pub extern "C" fn __mulsi3(a: u32, b: u32) -> u32 { - let (mut a, mut b) = (a, b); - let mut r: u32 = 0; - - while a > 0 { - if a & 1 > 0 { - r = r.wrapping_add(b); - } - a >>= 1; - b <<= 1; - } - - r - } - - #[cfg(not(target_feature = "m"))] - pub extern "C" fn __muldi3(a: u64, b: u64) -> u64 { - let (mut a, mut b) = (a, b); - let mut r: u64 = 0; - - while a > 0 { - if a & 1 > 0 { - r = r.wrapping_add(b); - } - a >>= 1; - b <<= 1; - } - - r - } -} diff --git a/library/compiler-builtins/compiler-builtins/src/arm_linux.rs b/library/compiler-builtins/compiler-builtins/src/sync/arm_linux.rs similarity index 59% rename from library/compiler-builtins/compiler-builtins/src/arm_linux.rs rename to library/compiler-builtins/compiler-builtins/src/sync/arm_linux.rs index ab9f868073908..7edd76c0b8b7c 100644 --- a/library/compiler-builtins/compiler-builtins/src/arm_linux.rs +++ b/library/compiler-builtins/compiler-builtins/src/sync/arm_linux.rs @@ -125,14 +125,16 @@ unsafe fn atomic_cmpxchg(ptr: *mut T, oldval: u32, newval: u32) -> u32 { let (shift, mask) = get_shift_mask(ptr); loop { - // FIXME(safety): preconditions review needed + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. let curval_aligned = unsafe { atomic_load_aligned::(aligned_ptr) }; let curval = extract_aligned(curval_aligned, shift, mask); if curval != oldval { return curval; } let newval_aligned = insert_aligned(curval_aligned, newval, shift, mask); - // FIXME(safety): preconditions review needed + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. if unsafe { __kuser_cmpxchg(curval_aligned, newval_aligned, aligned_ptr) } { return oldval; } @@ -143,7 +145,8 @@ macro_rules! atomic_rmw { ($name:ident, $ty:ty, $op:expr, $fetch:expr) => { intrinsics! { pub unsafe extern "C" fn $name(ptr: *mut $ty, val: $ty) -> $ty { - // FIXME(safety): preconditions review needed + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. unsafe { atomic_rmw( ptr, @@ -167,140 +170,15 @@ macro_rules! atomic_cmpxchg { ($name:ident, $ty:ty) => { intrinsics! { pub unsafe extern "C" fn $name(ptr: *mut $ty, oldval: $ty, newval: $ty) -> $ty { - // FIXME(safety): preconditions review needed + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. unsafe { atomic_cmpxchg(ptr, oldval as u32, newval as u32) as $ty } } } }; } -atomic_rmw!(@old __sync_fetch_and_add_1, u8, |a: u8, b: u8| a.wrapping_add(b)); -atomic_rmw!(@old __sync_fetch_and_add_2, u16, |a: u16, b: u16| a - .wrapping_add(b)); -atomic_rmw!(@old __sync_fetch_and_add_4, u32, |a: u32, b: u32| a - .wrapping_add(b)); - -atomic_rmw!(@new __sync_add_and_fetch_1, u8, |a: u8, b: u8| a.wrapping_add(b)); -atomic_rmw!(@new __sync_add_and_fetch_2, u16, |a: u16, b: u16| a - .wrapping_add(b)); -atomic_rmw!(@new __sync_add_and_fetch_4, u32, |a: u32, b: u32| a - .wrapping_add(b)); - -atomic_rmw!(@old __sync_fetch_and_sub_1, u8, |a: u8, b: u8| a.wrapping_sub(b)); -atomic_rmw!(@old __sync_fetch_and_sub_2, u16, |a: u16, b: u16| a - .wrapping_sub(b)); -atomic_rmw!(@old __sync_fetch_and_sub_4, u32, |a: u32, b: u32| a - .wrapping_sub(b)); - -atomic_rmw!(@new __sync_sub_and_fetch_1, u8, |a: u8, b: u8| a.wrapping_sub(b)); -atomic_rmw!(@new __sync_sub_and_fetch_2, u16, |a: u16, b: u16| a - .wrapping_sub(b)); -atomic_rmw!(@new __sync_sub_and_fetch_4, u32, |a: u32, b: u32| a - .wrapping_sub(b)); - -atomic_rmw!(@old __sync_fetch_and_and_1, u8, |a: u8, b: u8| a & b); -atomic_rmw!(@old __sync_fetch_and_and_2, u16, |a: u16, b: u16| a & b); -atomic_rmw!(@old __sync_fetch_and_and_4, u32, |a: u32, b: u32| a & b); - -atomic_rmw!(@new __sync_and_and_fetch_1, u8, |a: u8, b: u8| a & b); -atomic_rmw!(@new __sync_and_and_fetch_2, u16, |a: u16, b: u16| a & b); -atomic_rmw!(@new __sync_and_and_fetch_4, u32, |a: u32, b: u32| a & b); - -atomic_rmw!(@old __sync_fetch_and_or_1, u8, |a: u8, b: u8| a | b); -atomic_rmw!(@old __sync_fetch_and_or_2, u16, |a: u16, b: u16| a | b); -atomic_rmw!(@old __sync_fetch_and_or_4, u32, |a: u32, b: u32| a | b); - -atomic_rmw!(@new __sync_or_and_fetch_1, u8, |a: u8, b: u8| a | b); -atomic_rmw!(@new __sync_or_and_fetch_2, u16, |a: u16, b: u16| a | b); -atomic_rmw!(@new __sync_or_and_fetch_4, u32, |a: u32, b: u32| a | b); - -atomic_rmw!(@old __sync_fetch_and_xor_1, u8, |a: u8, b: u8| a ^ b); -atomic_rmw!(@old __sync_fetch_and_xor_2, u16, |a: u16, b: u16| a ^ b); -atomic_rmw!(@old __sync_fetch_and_xor_4, u32, |a: u32, b: u32| a ^ b); - -atomic_rmw!(@new __sync_xor_and_fetch_1, u8, |a: u8, b: u8| a ^ b); -atomic_rmw!(@new __sync_xor_and_fetch_2, u16, |a: u16, b: u16| a ^ b); -atomic_rmw!(@new __sync_xor_and_fetch_4, u32, |a: u32, b: u32| a ^ b); - -atomic_rmw!(@old __sync_fetch_and_nand_1, u8, |a: u8, b: u8| !(a & b)); -atomic_rmw!(@old __sync_fetch_and_nand_2, u16, |a: u16, b: u16| !(a & b)); -atomic_rmw!(@old __sync_fetch_and_nand_4, u32, |a: u32, b: u32| !(a & b)); - -atomic_rmw!(@new __sync_nand_and_fetch_1, u8, |a: u8, b: u8| !(a & b)); -atomic_rmw!(@new __sync_nand_and_fetch_2, u16, |a: u16, b: u16| !(a & b)); -atomic_rmw!(@new __sync_nand_and_fetch_4, u32, |a: u32, b: u32| !(a & b)); - -atomic_rmw!(@old __sync_fetch_and_max_1, i8, |a: i8, b: i8| if a > b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_max_2, i16, |a: i16, b: i16| if a > b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_max_4, i32, |a: i32, b: i32| if a > b { - a -} else { - b -}); - -atomic_rmw!(@old __sync_fetch_and_umax_1, u8, |a: u8, b: u8| if a > b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_umax_2, u16, |a: u16, b: u16| if a > b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_umax_4, u32, |a: u32, b: u32| if a > b { - a -} else { - b -}); - -atomic_rmw!(@old __sync_fetch_and_min_1, i8, |a: i8, b: i8| if a < b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_min_2, i16, |a: i16, b: i16| if a < b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_min_4, i32, |a: i32, b: i32| if a < b { - a -} else { - b -}); - -atomic_rmw!(@old __sync_fetch_and_umin_1, u8, |a: u8, b: u8| if a < b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_umin_2, u16, |a: u16, b: u16| if a < b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_umin_4, u32, |a: u32, b: u32| if a < b { - a -} else { - b -}); - -atomic_rmw!(@old __sync_lock_test_and_set_1, u8, |_: u8, b: u8| b); -atomic_rmw!(@old __sync_lock_test_and_set_2, u16, |_: u16, b: u16| b); -atomic_rmw!(@old __sync_lock_test_and_set_4, u32, |_: u32, b: u32| b); - -atomic_cmpxchg!(__sync_val_compare_and_swap_1, u8); -atomic_cmpxchg!(__sync_val_compare_and_swap_2, u16); -atomic_cmpxchg!(__sync_val_compare_and_swap_4, u32); +include!("arm_thumb_shared.rs"); intrinsics! { pub unsafe extern "C" fn __sync_synchronize() { diff --git a/library/compiler-builtins/compiler-builtins/src/sync/arm_thumb_shared.rs b/library/compiler-builtins/compiler-builtins/src/sync/arm_thumb_shared.rs new file mode 100644 index 0000000000000..812989c7bc85a --- /dev/null +++ b/library/compiler-builtins/compiler-builtins/src/sync/arm_thumb_shared.rs @@ -0,0 +1,134 @@ +// Used by both arm_linux.rs and thumbv6k.rs. + +// References: +// - https://llvm.org/docs/Atomics.html#libcalls-sync +// - https://gcc.gnu.org/onlinedocs/gcc/_005f_005fsync-Builtins.html +// - https://refspecs.linuxfoundation.org/elf/IA64-SysV-psABI.pdf#page=58 + +atomic_rmw!(@old __sync_fetch_and_add_1, u8, |a: u8, b: u8| a.wrapping_add(b)); +atomic_rmw!(@old __sync_fetch_and_add_2, u16, |a: u16, b: u16| a + .wrapping_add(b)); +atomic_rmw!(@old __sync_fetch_and_add_4, u32, |a: u32, b: u32| a + .wrapping_add(b)); + +atomic_rmw!(@new __sync_add_and_fetch_1, u8, |a: u8, b: u8| a.wrapping_add(b)); +atomic_rmw!(@new __sync_add_and_fetch_2, u16, |a: u16, b: u16| a + .wrapping_add(b)); +atomic_rmw!(@new __sync_add_and_fetch_4, u32, |a: u32, b: u32| a + .wrapping_add(b)); + +atomic_rmw!(@old __sync_fetch_and_sub_1, u8, |a: u8, b: u8| a.wrapping_sub(b)); +atomic_rmw!(@old __sync_fetch_and_sub_2, u16, |a: u16, b: u16| a + .wrapping_sub(b)); +atomic_rmw!(@old __sync_fetch_and_sub_4, u32, |a: u32, b: u32| a + .wrapping_sub(b)); + +atomic_rmw!(@new __sync_sub_and_fetch_1, u8, |a: u8, b: u8| a.wrapping_sub(b)); +atomic_rmw!(@new __sync_sub_and_fetch_2, u16, |a: u16, b: u16| a + .wrapping_sub(b)); +atomic_rmw!(@new __sync_sub_and_fetch_4, u32, |a: u32, b: u32| a + .wrapping_sub(b)); + +atomic_rmw!(@old __sync_fetch_and_and_1, u8, |a: u8, b: u8| a & b); +atomic_rmw!(@old __sync_fetch_and_and_2, u16, |a: u16, b: u16| a & b); +atomic_rmw!(@old __sync_fetch_and_and_4, u32, |a: u32, b: u32| a & b); + +atomic_rmw!(@new __sync_and_and_fetch_1, u8, |a: u8, b: u8| a & b); +atomic_rmw!(@new __sync_and_and_fetch_2, u16, |a: u16, b: u16| a & b); +atomic_rmw!(@new __sync_and_and_fetch_4, u32, |a: u32, b: u32| a & b); + +atomic_rmw!(@old __sync_fetch_and_or_1, u8, |a: u8, b: u8| a | b); +atomic_rmw!(@old __sync_fetch_and_or_2, u16, |a: u16, b: u16| a | b); +atomic_rmw!(@old __sync_fetch_and_or_4, u32, |a: u32, b: u32| a | b); + +atomic_rmw!(@new __sync_or_and_fetch_1, u8, |a: u8, b: u8| a | b); +atomic_rmw!(@new __sync_or_and_fetch_2, u16, |a: u16, b: u16| a | b); +atomic_rmw!(@new __sync_or_and_fetch_4, u32, |a: u32, b: u32| a | b); + +atomic_rmw!(@old __sync_fetch_and_xor_1, u8, |a: u8, b: u8| a ^ b); +atomic_rmw!(@old __sync_fetch_and_xor_2, u16, |a: u16, b: u16| a ^ b); +atomic_rmw!(@old __sync_fetch_and_xor_4, u32, |a: u32, b: u32| a ^ b); + +atomic_rmw!(@new __sync_xor_and_fetch_1, u8, |a: u8, b: u8| a ^ b); +atomic_rmw!(@new __sync_xor_and_fetch_2, u16, |a: u16, b: u16| a ^ b); +atomic_rmw!(@new __sync_xor_and_fetch_4, u32, |a: u32, b: u32| a ^ b); + +atomic_rmw!(@old __sync_fetch_and_nand_1, u8, |a: u8, b: u8| !(a & b)); +atomic_rmw!(@old __sync_fetch_and_nand_2, u16, |a: u16, b: u16| !(a & b)); +atomic_rmw!(@old __sync_fetch_and_nand_4, u32, |a: u32, b: u32| !(a & b)); + +atomic_rmw!(@new __sync_nand_and_fetch_1, u8, |a: u8, b: u8| !(a & b)); +atomic_rmw!(@new __sync_nand_and_fetch_2, u16, |a: u16, b: u16| !(a & b)); +atomic_rmw!(@new __sync_nand_and_fetch_4, u32, |a: u32, b: u32| !(a & b)); + +atomic_rmw!(@old __sync_fetch_and_max_1, i8, |a: i8, b: i8| if a > b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_max_2, i16, |a: i16, b: i16| if a > b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_max_4, i32, |a: i32, b: i32| if a > b { + a +} else { + b +}); + +atomic_rmw!(@old __sync_fetch_and_umax_1, u8, |a: u8, b: u8| if a > b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_umax_2, u16, |a: u16, b: u16| if a > b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_umax_4, u32, |a: u32, b: u32| if a > b { + a +} else { + b +}); + +atomic_rmw!(@old __sync_fetch_and_min_1, i8, |a: i8, b: i8| if a < b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_min_2, i16, |a: i16, b: i16| if a < b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_min_4, i32, |a: i32, b: i32| if a < b { + a +} else { + b +}); + +atomic_rmw!(@old __sync_fetch_and_umin_1, u8, |a: u8, b: u8| if a < b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_umin_2, u16, |a: u16, b: u16| if a < b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_umin_4, u32, |a: u32, b: u32| if a < b { + a +} else { + b +}); + +atomic_rmw!(@old __sync_lock_test_and_set_1, u8, |_: u8, b: u8| b); +atomic_rmw!(@old __sync_lock_test_and_set_2, u16, |_: u16, b: u16| b); +atomic_rmw!(@old __sync_lock_test_and_set_4, u32, |_: u32, b: u32| b); + +atomic_cmpxchg!(__sync_val_compare_and_swap_1, u8); +atomic_cmpxchg!(__sync_val_compare_and_swap_2, u16); +atomic_cmpxchg!(__sync_val_compare_and_swap_4, u32); diff --git a/library/compiler-builtins/compiler-builtins/src/sync/mod.rs b/library/compiler-builtins/compiler-builtins/src/sync/mod.rs new file mode 100644 index 0000000000000..590db14bb23b3 --- /dev/null +++ b/library/compiler-builtins/compiler-builtins/src/sync/mod.rs @@ -0,0 +1,20 @@ +#[cfg(all( + kernel_user_helpers, + any(target_os = "linux", target_os = "android"), + target_arch = "arm" +))] +pub mod arm_linux; + +// Armv6k supports atomic instructions, but they are unavailable in Thumb mode +// unless Thumb-2 instructions available (v6t2). +// Using Thumb interworking allows us to use these instructions even from Thumb mode +// without Thumb-2 instructions, but LLVM does not implement that processing (as of LLVM 21), +// so we implement it here at this time. +// (`not(target_feature = "mclass")` is unneeded because v6k is not set on thumbv6m.) +#[cfg(all( + target_arch = "arm", + target_feature = "thumb-mode", + target_feature = "v6k", + not(target_feature = "v6t2"), +))] +pub mod thumbv6k; diff --git a/library/compiler-builtins/compiler-builtins/src/sync/thumbv6k.rs b/library/compiler-builtins/compiler-builtins/src/sync/thumbv6k.rs new file mode 100644 index 0000000000000..c47b4c2ec6b00 --- /dev/null +++ b/library/compiler-builtins/compiler-builtins/src/sync/thumbv6k.rs @@ -0,0 +1,213 @@ +// Armv6k supports atomic instructions, but they are unavailable in Thumb mode +// unless Thumb-2 instructions available (v6t2). +// Using Thumb interworking allows us to use these instructions even from Thumb mode +// without Thumb-2 instructions, but LLVM does not implement that processing (as of LLVM 21), +// so we implement it here at this time. + +use core::arch::asm; +use core::mem; + +// Data Memory Barrier (DMB) operation. +// +// Armv6 does not support DMB instruction, so use use special instruction equivalent to it. +// +// Refs: https://developer.arm.com/documentation/ddi0360/f/control-coprocessor-cp15/register-descriptions/c7--cache-operations-register +macro_rules! cp15_barrier { + () => { + "mcr p15, #0, {zero}, c7, c10, #5" + }; +} + +#[instruction_set(arm::a32)] +unsafe fn fence() { + unsafe { + asm!( + cp15_barrier!(), + // cp15_barrier! calls `mcr p15, 0, {zero}, c7, c10, 5`, and + // the value in the {zero} register should be zero (SBZ). + zero = inout(reg) 0_u32 => _, + options(nostack, preserves_flags), + ); + } +} + +trait Atomic: Copy + Eq { + unsafe fn load_relaxed(src: *const Self) -> Self; + unsafe fn cmpxchg(dst: *mut Self, current: Self, new: Self) -> Self; +} + +macro_rules! atomic { + ($ty:ident, $suffix:tt) => { + impl Atomic for $ty { + // #[instruction_set(arm::a32)] is unneeded for ldr. + #[inline] + unsafe fn load_relaxed( + src: *const Self, + ) -> Self { + let out: Self; + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. + unsafe { + asm!( + concat!("ldr", $suffix, " {out}, [{src}]"), // atomic { out = *src } + src = in(reg) src, + out = lateout(reg) out, + options(nostack, preserves_flags), + ); + } + out + } + #[inline] + #[instruction_set(arm::a32)] + unsafe fn cmpxchg( + dst: *mut Self, + old: Self, + new: Self, + ) -> Self { + let mut out: Self; + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. + // + // Instead of the common `fence; ll/sc loop; fence` form, we use the form used by + // LLVM, which omits the preceding fence if no write operation is performed. + unsafe { + asm!( + concat!("ldrex", $suffix, " {out}, [{dst}]"), // atomic { out = *dst; EXCLUSIVE = dst } + "cmp {out}, {old}", // if out == old { Z = 1 } else { Z = 0 } + "bne 3f", // if Z == 0 { jump 'cmp-fail } + cp15_barrier!(), // fence + "2:", // 'retry: + concat!("strex", $suffix, " {r}, {new}, [{dst}]"), // atomic { if EXCLUSIVE == dst { *dst = new; r = 0 } else { r = 1 }; EXCLUSIVE = None } + "cmp {r}, #0", // if r == 0 { Z = 1 } else { Z = 0 } + "beq 3f", // if Z == 1 { jump 'success } + concat!("ldrex", $suffix, " {out}, [{dst}]"), // atomic { out = *dst; EXCLUSIVE = dst } + "cmp {out}, {old}", // if out == old { Z = 1 } else { Z = 0 } + "beq 2b", // if Z == 1 { jump 'retry } + "3:", // 'cmp-fail | 'success: + cp15_barrier!(), // fence + dst = in(reg) dst, + // Note: this cast must be a zero-extend since loaded value + // which compared to it is zero-extended. + old = in(reg) u32::from(old), + new = in(reg) new, + out = out(reg) out, + r = out(reg) _, + // cp15_barrier! calls `mcr p15, 0, {zero}, c7, c10, 5`, and + // the value in the {zero} register should be zero (SBZ). + zero = inout(reg) 0_u32 => _, + // Do not use `preserves_flags` because CMP modifies the condition flags. + options(nostack), + ); + out + } + } + } + }; +} +atomic!(u8, "b"); +atomic!(u16, "h"); +atomic!(u32, ""); + +// To avoid the annoyance of sign extension, we implement signed CAS using +// unsigned CAS. (See note in cmpxchg impl in atomic! macro) +macro_rules! delegate_signed { + ($ty:ident, $base:ident) => { + const _: () = { + assert!(mem::size_of::<$ty>() == mem::size_of::<$base>()); + assert!(mem::align_of::<$ty>() == mem::align_of::<$base>()); + }; + impl Atomic for $ty { + #[inline] + unsafe fn load_relaxed(src: *const Self) -> Self { + // SAFETY: the caller must uphold the safety contract. + // casts are okay because $ty and $base implement the same layout. + unsafe { <$base as Atomic>::load_relaxed(src.cast::<$base>()).cast_signed() } + } + #[inline] + unsafe fn cmpxchg(dst: *mut Self, old: Self, new: Self) -> Self { + // SAFETY: the caller must uphold the safety contract. + // casts are okay because $ty and $base implement the same layout. + unsafe { + <$base as Atomic>::cmpxchg( + dst.cast::<$base>(), + old.cast_unsigned(), + new.cast_unsigned(), + ) + .cast_signed() + } + } + } + }; +} +delegate_signed!(i8, u8); +delegate_signed!(i16, u16); +delegate_signed!(i32, u32); + +// Generic atomic read-modify-write operation +// +// We could implement RMW more efficiently as an assembly LL/SC loop per operation, +// but we won't do that for now because it would make the implementation more complex. +// +// We also do not implement LL and SC as separate functions. This is because it +// is theoretically possible for the compiler to insert operations that might +// clear the reservation between LL and SC. See https://github.com/taiki-e/portable-atomic/blob/58ef7f27c9e20da4cc1ef0abf8b8ce9ac5219ec3/src/imp/atomic128/aarch64.rs#L44-L55 +// for more details. +unsafe fn atomic_rmw T, G: Fn(T, T) -> T>(ptr: *mut T, f: F, g: G) -> T { + loop { + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. + let curval = unsafe { T::load_relaxed(ptr) }; + let newval = f(curval); + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. + if unsafe { T::cmpxchg(ptr, curval, newval) } == curval { + return g(curval, newval); + } + } +} + +macro_rules! atomic_rmw { + ($name:ident, $ty:ty, $op:expr, $fetch:expr) => { + intrinsics! { + pub unsafe extern "C" fn $name(ptr: *mut $ty, val: $ty) -> $ty { + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. + unsafe { + atomic_rmw( + ptr, + |x| $op(x as $ty, val), + |old, new| $fetch(old, new) + ) as $ty + } + } + } + }; + + (@old $name:ident, $ty:ty, $op:expr) => { + atomic_rmw!($name, $ty, $op, |old, _| old); + }; + + (@new $name:ident, $ty:ty, $op:expr) => { + atomic_rmw!($name, $ty, $op, |_, new| new); + }; +} +macro_rules! atomic_cmpxchg { + ($name:ident, $ty:ty) => { + intrinsics! { + pub unsafe extern "C" fn $name(ptr: *mut $ty, oldval: $ty, newval: $ty) -> $ty { + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. + unsafe { <$ty as Atomic>::cmpxchg(ptr, oldval, newval) } + } + } + }; +} + +include!("arm_thumb_shared.rs"); + +intrinsics! { + pub unsafe extern "C" fn __sync_synchronize() { + // SAFETY: preconditions are the same as the calling function. + unsafe { fence() }; + } +} diff --git a/library/compiler-builtins/compiler-builtins/src/x86.rs b/library/compiler-builtins/compiler-builtins/src/x86.rs index 1a3c418609451..45f4ba207e6e0 100644 --- a/library/compiler-builtins/compiler-builtins/src/x86.rs +++ b/library/compiler-builtins/compiler-builtins/src/x86.rs @@ -1,7 +1,3 @@ -#![allow(unused_imports)] - -use core::intrinsics; - // NOTE These functions are implemented using assembly because they use a custom // calling convention which can't be implemented using a normal Rust function diff --git a/library/compiler-builtins/compiler-builtins/src/x86_64.rs b/library/compiler-builtins/compiler-builtins/src/x86_64.rs index 99a527ee9ac5e..a3a5c8f7e10f9 100644 --- a/library/compiler-builtins/compiler-builtins/src/x86_64.rs +++ b/library/compiler-builtins/compiler-builtins/src/x86_64.rs @@ -1,7 +1,3 @@ -#![allow(unused_imports)] - -use core::intrinsics; - // NOTE These functions are implemented using assembly because they use a custom // calling convention which can't be implemented using a normal Rust function diff --git a/library/compiler-builtins/crates/api-list-common/Cargo.toml b/library/compiler-builtins/crates/api-list-common/Cargo.toml new file mode 100644 index 0000000000000..bf9262eb828ff --- /dev/null +++ b/library/compiler-builtins/crates/api-list-common/Cargo.toml @@ -0,0 +1,6 @@ +[package] +name = "api-list-common" +version = "0.1.0" +edition = "2024" +publish = false +license = "MIT OR Apache-2.0" diff --git a/library/compiler-builtins/crates/api-list-common/src/lib.rs b/library/compiler-builtins/crates/api-list-common/src/lib.rs new file mode 100644 index 0000000000000..f6e5516a76fa6 --- /dev/null +++ b/library/compiler-builtins/crates/api-list-common/src/lib.rs @@ -0,0 +1,1567 @@ +//! A list of API we have available, shared among various test crates. + +use std::fmt; +use std::sync::LazyLock; + +/// Convenient structure for defining items, gets expanded into a flat structure. +struct NestedOp { + rust_sig: Signature, + c_sig: Option, + fn_list: &'static [&'static str], + scope: OpScope, +} + +/// Indicate where a function is defined and whether it is public or private. +#[derive(Clone, Copy, Debug)] +pub enum OpScope { + /// Part of `libm`'s public API. + LibmPublic, + /// Functions internal to `libm`, e.g. `rem_pio2`. + LibmPrivate, + /// Functions part of the public API for `compiler-builtins`. + BuiltinsPublic, +} + +impl OpScope { + /// Where we should look for functions of this scope. + pub const fn path_root(self) -> &'static str { + match self { + OpScope::LibmPublic => "libm", + OpScope::LibmPrivate => todo!(), + OpScope::BuiltinsPublic => "crate::builtins_wrapper", + } + } + + pub fn defined_in_compiler_builtins(self) -> bool { + match self { + OpScope::LibmPublic | OpScope::LibmPrivate => false, + OpScope::BuiltinsPublic => true, + } + } +} + +/// We need a flat list to work with most of the time, but define things as a more convenient +/// nested list. +const ALL_OPERATIONS_NESTED: &[NestedOp] = &[ + /******************************** + * compiler-builtins operations * + ********************************/ + NestedOp { + rust_sig: Signature { + args: &[Ty::F16, Ty::F16], + returns: &[Ty::F16], + }, + c_sig: None, + fn_list: &["addf16", "mulf16", "subf16"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32, Ty::F32], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["addf32", "divf32", "mulf32", "subf32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64, Ty::F64], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["addf64", "divf64", "mulf64", "subf64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128, Ty::F128], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["addf128", "divf128", "mulf128", "subf128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32, Ty::I32], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["powif32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64, Ty::I32], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["powif64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128, Ty::I32], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["powif128"], + scope: OpScope::BuiltinsPublic, + }, + /* Comparison */ + NestedOp { + rust_sig: Signature { + args: &[Ty::F16, Ty::F16], + returns: &[Ty::Bool], + }, + c_sig: None, + fn_list: &[ + "eqf16", "gef16", "gtf16", "lef16", "ltf16", "nef16", "unordf16", + ], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32, Ty::F32], + returns: &[Ty::Bool], + }, + c_sig: None, + fn_list: &[ + "eqf32", "gef32", "gtf32", "lef32", "ltf32", "nef32", "unordf32", + ], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64, Ty::F64], + returns: &[Ty::Bool], + }, + c_sig: None, + fn_list: &[ + "eqf64", "gef64", "gtf64", "lef64", "ltf64", "nef64", "unordf64", + ], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128, Ty::F128], + returns: &[Ty::Bool], + }, + c_sig: None, + fn_list: &[ + "eqf128", + "gef128", + "gtf128", + "lef128", + "ltf128", + "nef128", + "unordf128", + ], + scope: OpScope::BuiltinsPublic, + }, + /* conversion */ + NestedOp { + rust_sig: Signature { + args: &[Ty::F16], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["extend_f16_f32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F16], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["extend_f16_f64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F16], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["extend_f16_f128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["extend_f32_f64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["extend_f32_f128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["extend_f64_f128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::F16], + }, + c_sig: None, + fn_list: &["narrow_f32_f16"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::F16], + }, + c_sig: None, + fn_list: &["narrow_f64_f16"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::F16], + }, + c_sig: None, + fn_list: &["narrow_f128_f16"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["narrow_f64_f32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["narrow_f128_f32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["narrow_f128_f64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::I32], + }, + c_sig: None, + fn_list: &["ftoi_f32_i32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::I64], + }, + c_sig: None, + fn_list: &["ftoi_f32_i64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::I128], + }, + c_sig: None, + fn_list: &["ftoi_f32_i128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::I32], + }, + c_sig: None, + fn_list: &["ftoi_f64_i32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::I64], + }, + c_sig: None, + fn_list: &["ftoi_f64_i64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::I128], + }, + c_sig: None, + fn_list: &["ftoi_f64_i128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::I32], + }, + c_sig: None, + fn_list: &["ftoi_f128_i32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::I64], + }, + c_sig: None, + fn_list: &["ftoi_f128_i64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::I128], + }, + c_sig: None, + fn_list: &["ftoi_f128_i128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::U32], + }, + c_sig: None, + fn_list: &["ftoi_f32_u32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::U64], + }, + c_sig: None, + fn_list: &["ftoi_f32_u64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::U128], + }, + c_sig: None, + fn_list: &["ftoi_f32_u128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::U32], + }, + c_sig: None, + fn_list: &["ftoi_f64_u32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::U64], + }, + c_sig: None, + fn_list: &["ftoi_f64_u64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::U128], + }, + c_sig: None, + fn_list: &["ftoi_f64_u128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::U32], + }, + c_sig: None, + fn_list: &["ftoi_f128_u32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::U64], + }, + c_sig: None, + fn_list: &["ftoi_f128_u64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::U128], + }, + c_sig: None, + fn_list: &["ftoi_f128_u128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I32], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["itof_i32_f32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I64], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["itof_i64_f32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I128], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["itof_i128_f32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I32], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["itof_i32_f64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I64], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["itof_i64_f64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I128], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["itof_i128_f64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I32], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["itof_i32_f128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I64], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["itof_i64_f128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I128], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["itof_i128_f128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U32], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["itof_u32_f32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U64], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["itof_u64_f32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U128], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["itof_u128_f32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U32], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["itof_u32_f64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U64], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["itof_u64_f64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U128], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["itof_u128_f64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U32], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["itof_u32_f128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U64], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["itof_u64_f128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U128], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["itof_u128_f128"], + scope: OpScope::BuiltinsPublic, + }, + /* int arithmetic */ + NestedOp { + rust_sig: Signature { + args: &[Ty::I32, Ty::I32], + returns: &[Ty::I32], + }, + c_sig: None, + fn_list: &["idiv_i32", "imod_i32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I32, Ty::I32], + returns: &[Ty::I32, Ty::I32], + }, + c_sig: None, + fn_list: &["idivmod_i32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I32, Ty::I32], + returns: &[Ty::I32, Ty::Bool], + }, + c_sig: None, + fn_list: &["imulo_i32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U32, Ty::U32], + returns: &[Ty::U32], + }, + c_sig: None, + fn_list: &["idiv_u32", "imod_u32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U32, Ty::U32], + returns: &[Ty::U32, Ty::U32], + }, + c_sig: None, + fn_list: &["idivmod_u32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I64, Ty::I64], + returns: &[Ty::I64], + }, + c_sig: None, + fn_list: &["idiv_i64", "imod_i64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I64, Ty::I64], + returns: &[Ty::I64, Ty::I64], + }, + c_sig: None, + fn_list: &["idivmod_i64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U64, Ty::U64], + returns: &[Ty::U64], + }, + c_sig: None, + fn_list: &["idiv_u64", "imod_u64", "imul_u64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U64, Ty::U64], + returns: &[Ty::U64, Ty::U64], + }, + c_sig: None, + fn_list: &["idivmod_u64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I64, Ty::I64], + returns: &[Ty::I64, Ty::Bool], + }, + c_sig: None, + fn_list: &["imulo_i64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I128, Ty::I128], + returns: &[Ty::I128], + }, + c_sig: None, + fn_list: &[ + "iadd_i128", + "idiv_i128", + "imod_i128", + "imul_i128", + "isub_i128", + ], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I128, Ty::I128], + returns: &[Ty::I128, Ty::I128], + }, + c_sig: None, + fn_list: &["idivmod_i128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I128, Ty::I128], + returns: &[Ty::I128, Ty::Bool], + }, + c_sig: None, + fn_list: &["iaddo_i128", "imulo_i128", "isubo_i128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U128, Ty::U128], + returns: &[Ty::U128], + }, + c_sig: None, + fn_list: &["iadd_u128", "idiv_u128", "imod_u128", "isub_u128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U128, Ty::U128], + returns: &[Ty::U128, Ty::U128], + }, + c_sig: None, + fn_list: &["idivmod_u128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U128, Ty::U128], + returns: &[Ty::U128, Ty::Bool], + }, + c_sig: None, + fn_list: &["iaddo_u128", "imulo_u128", "isubo_u128"], + scope: OpScope::BuiltinsPublic, + }, + /* int shifts */ + NestedOp { + rust_sig: Signature { + args: &[Ty::U32, Ty::U32], + returns: &[Ty::U32], + }, + c_sig: None, + fn_list: &["ashl_u32", "lshr_u32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U64, Ty::U32], + returns: &[Ty::U64], + }, + c_sig: None, + fn_list: &["ashl_u64", "lshr_u64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U128, Ty::U32], + returns: &[Ty::U128], + }, + c_sig: None, + fn_list: &["ashl_u128", "lshr_u128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I32, Ty::U32], + returns: &[Ty::I32], + }, + c_sig: None, + fn_list: &["ashr_i32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I64, Ty::U32], + returns: &[Ty::I64], + }, + c_sig: None, + fn_list: &["ashr_i64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I128, Ty::U32], + returns: &[Ty::I128], + }, + c_sig: None, + fn_list: &["ashr_i128"], + scope: OpScope::BuiltinsPublic, + }, + /* int bitwise ops */ + NestedOp { + rust_sig: Signature { + args: &[Ty::U32], + returns: &[Ty::USize], + }, + c_sig: None, + fn_list: &["leading_zeros_u32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U64], + returns: &[Ty::USize], + }, + c_sig: None, + fn_list: &["leading_zeros_u64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U128], + returns: &[Ty::USize], + }, + c_sig: None, + fn_list: &["leading_zeros_u128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U32], + returns: &[Ty::USize], + }, + c_sig: None, + fn_list: &["trailing_zeros_u32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U64], + returns: &[Ty::USize], + }, + c_sig: None, + fn_list: &["trailing_zeros_u64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U128], + returns: &[Ty::USize], + }, + c_sig: None, + fn_list: &["trailing_zeros_u128"], + scope: OpScope::BuiltinsPublic, + }, + /******************* + * libm operations * + *******************/ + NestedOp { + // `fn(f16) -> f16` + rust_sig: Signature { + args: &[Ty::F16], + returns: &[Ty::F16], + }, + c_sig: None, + fn_list: &[ + "ceilf16", + "fabsf16", + "floorf16", + "rintf16", + "roundevenf16", + "roundf16", + "sqrtf16", + "truncf16", + ], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `fn(f32) -> f32` + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &[ + "acosf", + "acoshf", + "asinf", + "asinhf", + "atanf", + "atanhf", + "cbrtf", + "ceilf", + "cosf", + "coshf", + "erfcf", + "erff", + "exp10f", + "exp2f", + "expf", + "expm1f", + "fabsf", + "floorf", + "j0f", + "j1f", + "lgammaf", + "log10f", + "log1pf", + "log2f", + "logf", + "rintf", + "roundevenf", + "roundf", + "sinf", + "sinhf", + "sqrtf", + "tanf", + "tanhf", + "tgammaf", + "truncf", + "y0f", + "y1f", + ], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f64) -> f64` + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &[ + "acos", + "acosh", + "asin", + "asinh", + "atan", + "atanh", + "cbrt", + "ceil", + "cos", + "cosh", + "erf", + "erfc", + "exp", + "exp10", + "exp2", + "expm1", + "fabs", + "floor", + "j0", + "j1", + "lgamma", + "log", + "log10", + "log1p", + "log2", + "rint", + "round", + "roundeven", + "sin", + "sinh", + "sqrt", + "tan", + "tanh", + "tgamma", + "trunc", + "y0", + "y1", + ], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `fn(f128) -> f128` + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &[ + "ceilf128", + "fabsf128", + "floorf128", + "rintf128", + "roundevenf128", + "roundf128", + "sqrtf128", + "truncf128", + ], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f16, f16) -> f16` + rust_sig: Signature { + args: &[Ty::F16, Ty::F16], + returns: &[Ty::F16], + }, + c_sig: None, + fn_list: &[ + "copysignf16", + "fdimf16", + "fmaxf16", + "fmaximum_numf16", + "fmaximumf16", + "fminf16", + "fminimum_numf16", + "fminimumf16", + "fmodf16", + ], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f32, f32) -> f32` + rust_sig: Signature { + args: &[Ty::F32, Ty::F32], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &[ + "atan2f", + "copysignf", + "fdimf", + "fmaxf", + "fmaximum_numf", + "fmaximumf", + "fminf", + "fminimum_numf", + "fminimumf", + "fmodf", + "hypotf", + "nextafterf", + "powf", + "remainderf", + ], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f64, f64) -> f64` + rust_sig: Signature { + args: &[Ty::F64, Ty::F64], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &[ + "atan2", + "copysign", + "fdim", + "fmax", + "fmaximum", + "fmaximum_num", + "fmin", + "fminimum", + "fminimum_num", + "fmod", + "hypot", + "nextafter", + "pow", + "remainder", + ], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f128, f128) -> f128` + rust_sig: Signature { + args: &[Ty::F128, Ty::F128], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &[ + "copysignf128", + "fdimf128", + "fmaxf128", + "fmaximum_numf128", + "fmaximumf128", + "fminf128", + "fminimum_numf128", + "fminimumf128", + "fmodf128", + ], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f16, f16, f16) -> f16` + rust_sig: Signature { + args: &[Ty::F16, Ty::F16, Ty::F16], + returns: &[Ty::F16], + }, + c_sig: None, + fn_list: &["fmaf16"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f32, f32, f32) -> f32` + rust_sig: Signature { + args: &[Ty::F32, Ty::F32, Ty::F32], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["fmaf"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f64, f64, f64) -> f64` + rust_sig: Signature { + args: &[Ty::F64, Ty::F64, Ty::F64], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["fma"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f128, f128, f128) -> f128` + rust_sig: Signature { + args: &[Ty::F128, Ty::F128, Ty::F128], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["fmaf128"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f16) -> i32` + rust_sig: Signature { + args: &[Ty::F16], + returns: &[Ty::I32], + }, + c_sig: None, + fn_list: &["ilogbf16"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f32) -> i32` + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::I32], + }, + c_sig: None, + fn_list: &["ilogbf"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f64) -> i32` + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::I32], + }, + c_sig: None, + fn_list: &["ilogb"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f128) -> i32` + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::I32], + }, + c_sig: None, + fn_list: &["ilogbf128"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(i32, f32) -> f32` + rust_sig: Signature { + args: &[Ty::I32, Ty::F32], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["jnf", "ynf"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(i32, f64) -> f64` + rust_sig: Signature { + args: &[Ty::I32, Ty::F64], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["jn", "yn"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f16, i32) -> f16` + rust_sig: Signature { + args: &[Ty::F16, Ty::I32], + returns: &[Ty::F16], + }, + c_sig: None, + fn_list: &["ldexpf16", "scalbnf16"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f32, i32) -> f32` + rust_sig: Signature { + args: &[Ty::F32, Ty::I32], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["ldexpf", "scalbnf"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f64, i64) -> f64` + rust_sig: Signature { + args: &[Ty::F64, Ty::I32], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["ldexp", "scalbn"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f128, i32) -> f128` + rust_sig: Signature { + args: &[Ty::F128, Ty::I32], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["ldexpf128", "scalbnf128"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f32, &mut f32) -> f32` as `(f32) -> (f32, f32)` + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::F32, Ty::F32], + }, + c_sig: Some(Signature { + args: &[Ty::F32, Ty::MutF32], + returns: &[Ty::F32], + }), + fn_list: &["modff"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f64, &mut f64) -> f64` as `(f64) -> (f64, f64)` + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::F64, Ty::F64], + }, + c_sig: Some(Signature { + args: &[Ty::F64, Ty::MutF64], + returns: &[Ty::F64], + }), + fn_list: &["modf"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f16, &mut c_int) -> f16` as `(f16) -> (f16, i32)` + rust_sig: Signature { + args: &[Ty::F16], + returns: &[Ty::F16, Ty::I32], + }, + c_sig: Some(Signature { + args: &[Ty::F16, Ty::MutCInt], + returns: &[Ty::F16], + }), + fn_list: &["frexpf16"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f32, &mut c_int) -> f32` as `(f32) -> (f32, i32)` + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::F32, Ty::I32], + }, + c_sig: Some(Signature { + args: &[Ty::F32, Ty::MutCInt], + returns: &[Ty::F32], + }), + fn_list: &["frexpf", "lgammaf_r"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f64, &mut c_int) -> f64` as `(f64) -> (f64, i32)` + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::F64, Ty::I32], + }, + c_sig: Some(Signature { + args: &[Ty::F64, Ty::MutCInt], + returns: &[Ty::F64], + }), + fn_list: &["frexp", "lgamma_r"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f128, &mut c_int) -> f128` as `(f128) -> (f128, i32)` + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::F128, Ty::I32], + }, + c_sig: Some(Signature { + args: &[Ty::F128, Ty::MutCInt], + returns: &[Ty::F128], + }), + fn_list: &["frexpf128"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f32, f32, &mut c_int) -> f32` as `(f32, f32) -> (f32, i32)` + rust_sig: Signature { + args: &[Ty::F32, Ty::F32], + returns: &[Ty::F32, Ty::I32], + }, + c_sig: Some(Signature { + args: &[Ty::F32, Ty::F32, Ty::MutCInt], + returns: &[Ty::F32], + }), + fn_list: &["remquof"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f64, f64, &mut c_int) -> f64` as `(f64, f64) -> (f64, i32)` + rust_sig: Signature { + args: &[Ty::F64, Ty::F64], + returns: &[Ty::F64, Ty::I32], + }, + c_sig: Some(Signature { + args: &[Ty::F64, Ty::F64, Ty::MutCInt], + returns: &[Ty::F64], + }), + fn_list: &["remquo"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f32, &mut f32, &mut f32)` as `(f32) -> (f32, f32)` + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::F32, Ty::F32], + }, + c_sig: Some(Signature { + args: &[Ty::F32, Ty::MutF32, Ty::MutF32], + returns: &[], + }), + fn_list: &["sincosf"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f64, &mut f64, &mut f64)` as `(f64) -> (f64, f64)` + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::F64, Ty::F64], + }, + c_sig: Some(Signature { + args: &[Ty::F64, Ty::MutF64, Ty::MutF64], + returns: &[], + }), + fn_list: &["sincos"], + scope: OpScope::LibmPublic, + }, +]; + +/// A type used in a function signature. +#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)] +pub enum Ty { + F16, + F32, + F64, + F128, + I32, + I64, + I128, + U32, + U64, + U128, + USize, + Bool, + CInt, + MutF16, + MutF32, + MutF64, + MutF128, + MutI32, + MutCInt, +} + +impl Ty { + /// The number of bits needed to represent this type's possible values. That is, + /// `log2(variant_count)`. + pub fn effective_bits(self) -> u32 { + match self { + Ty::Bool => 1, + Ty::F16 | Ty::MutF16 => 16, + Ty::F32 | Ty::I32 | Ty::U32 | Ty::MutF32 | Ty::MutI32 => 32, + Ty::F64 | Ty::I64 | Ty::U64 | Ty::MutF64 => 64, + Ty::F128 | Ty::I128 | Ty::U128 | Ty::MutF128 => 128, + Ty::USize => usize::BITS, + // Assume we're not testing on a 16-bit system + Ty::CInt | Ty::MutCInt => 32, + } + } + + /// How to group functions that mostly have this kind of input. + fn group(self) -> Group { + match self { + Ty::F16 | Ty::MutF16 => Group::F16, + Ty::F32 | Ty::MutF32 => Group::F32, + Ty::F64 | Ty::MutF64 => Group::F64, + Ty::F128 | Ty::MutF128 => Group::F128, + Ty::I32 + | Ty::I64 + | Ty::I128 + | Ty::U32 + | Ty::U64 + | Ty::U128 + | Ty::USize + | Ty::Bool + | Ty::CInt + | Ty::MutI32 + | Ty::MutCInt => Group::Integer, + } + } + + fn is_float(self) -> bool { + match self { + Ty::F16 + | Ty::F32 + | Ty::F64 + | Ty::F128 + | Ty::MutF16 + | Ty::MutF32 + | Ty::MutF64 + | Ty::MutF128 => true, + Ty::I32 + | Ty::I64 + | Ty::I128 + | Ty::U32 + | Ty::U64 + | Ty::U128 + | Ty::USize + | Ty::Bool + | Ty::CInt + | Ty::MutI32 + | Ty::MutCInt => false, + } + } +} + +/// How a function should get grouped for things like extensive tests. +#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)] +pub enum Group { + F16, + F32, + F64, + F128, + Integer, +} + +impl fmt::Display for Ty { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let s = match self { + Ty::F16 => "f16", + Ty::F32 => "f32", + Ty::F64 => "f64", + Ty::F128 => "f128", + Ty::I32 => "i32", + Ty::I64 => "i64", + Ty::I128 => "i128", + Ty::U32 => "u32", + Ty::U64 => "u64", + Ty::U128 => "u128", + Ty::USize => "usize", + Ty::Bool => "bool", + Ty::CInt => "::core::ffi::c_int", + Ty::MutF16 => "&mut f16", + Ty::MutF32 => "&mut f32", + Ty::MutF64 => "&mut f64", + Ty::MutF128 => "&mut f128", + Ty::MutI32 => "&mut i32", + Ty::MutCInt => "&mut ::core::ffi::c_int", + }; + f.write_str(s) + } +} + +/// Representation of e.g. `(f32, f32) -> f32` +#[derive(Debug, Clone)] +pub struct Signature { + pub args: &'static [Ty], + pub returns: &'static [Ty], +} + +/// Combined information about a function implementation. +#[derive(Debug, Clone)] +pub struct MathOpInfo { + pub name: &'static str, + /// How this function should be grouped when needed. Based on the first float argument. + pub group: Group, + /// Function signature for C implementations + pub c_sig: Signature, + /// Function signature for Rust implementations + pub rust_sig: Signature, + /// Indicate what crate this function is defined in and whether it is public or private. + pub scope: OpScope, + /// The path to this function, including crate but excluding the function itself. + pub path: String, +} + +/// A flat representation of `ALL_FUNCTIONS`. +pub static ALL_OPERATIONS: LazyLock> = LazyLock::new(|| { + let mut ret = Vec::new(); + + for op in ALL_OPERATIONS_NESTED { + let fn_names = op.fn_list; + for name in fn_names { + // Locate the first float argument or return value, fall back to whatever the first + // argument is if there are no floats. + let group_ty = op + .rust_sig + .args + .iter() + .chain(op.rust_sig.returns.iter()) + .find(|arg| arg.is_float()) + .unwrap_or(&op.rust_sig.args[0]); + let group = group_ty.group(); + + let api = MathOpInfo { + name, + group, + rust_sig: op.rust_sig.clone(), + c_sig: op.c_sig.clone().unwrap_or_else(|| op.rust_sig.clone()), + scope: op.scope, + path: format!("{}::{name}", op.scope.path_root()), + }; + ret.push(api); + } + } + + ret.sort_by_key(|item| item.name); + ret +}); + +#[cfg(test)] +mod tests { + use std::collections::HashSet; + + pub use super::*; + + #[test] + fn sorted_fn_list() { + for op in ALL_OPERATIONS_NESTED { + if !op.fn_list.is_sorted() { + let mut sorted = (*op.fn_list).to_owned(); + sorted.sort_unstable(); + panic!( + "names list is not sorted: {:?}\nExpected: {sorted:?}", + op.fn_list + ); + } + } + } + + #[test] + fn no_duplicates_in_list() { + let mut names = HashSet::new(); + let mut paths = HashSet::new(); + for item in &*ALL_OPERATIONS { + let new_name = names.insert(item.name); + assert!(new_name, "duplicate name `{item:?}`"); + let new_path = paths.insert(&item.path); + assert!(new_path, "duplicate path`{item:?}`"); + } + } +} diff --git a/library/compiler-builtins/crates/libm-macros/Cargo.toml b/library/compiler-builtins/crates/libm-macros/Cargo.toml index 100a8d0ec30e4..920cc32104943 100644 --- a/library/compiler-builtins/crates/libm-macros/Cargo.toml +++ b/library/compiler-builtins/crates/libm-macros/Cargo.toml @@ -9,10 +9,11 @@ license = "MIT OR Apache-2.0" proc-macro = true [dependencies] -heck = "0.5.0" -proc-macro2 = "1.0.95" -quote = "1.0.40" -syn = { version = "2.0.104", features = ["full", "extra-traits", "visit-mut"] } +api-list-common.workspace = true +heck.workspace = true +proc-macro2.workspace = true +quote.workspace = true +syn = { workspace = true, features = ["full", "extra-traits", "visit-mut"] } [lints.rust] # Values used during testing diff --git a/library/compiler-builtins/crates/libm-macros/src/enums.rs b/library/compiler-builtins/crates/libm-macros/src/enums.rs index b4646f984d471..f15bdaa63821a 100644 --- a/library/compiler-builtins/crates/libm-macros/src/enums.rs +++ b/library/compiler-builtins/crates/libm-macros/src/enums.rs @@ -93,11 +93,6 @@ pub fn function_enum( #( #base_arms, )* } } - - /// Return information about this operation. - pub fn math_op(self) -> &'static crate::op::MathOpInfo { - crate::op::ALL_OPERATIONS.iter().find(|op| op.name == self.as_str()).unwrap() - } } }; diff --git a/library/compiler-builtins/crates/libm-macros/src/lib.rs b/library/compiler-builtins/crates/libm-macros/src/lib.rs index 7efa1488f570e..7bafd0ce8e1d4 100644 --- a/library/compiler-builtins/crates/libm-macros/src/lib.rs +++ b/library/compiler-builtins/crates/libm-macros/src/lib.rs @@ -1,18 +1,17 @@ mod enums; mod parse; -mod shared; +use api_list_common::{ALL_OPERATIONS, Group, MathOpInfo, Ty}; use parse::{Invocation, StructuredInput}; use proc_macro as pm; use proc_macro2::{self as pm2, Span}; use quote::{ToTokens, quote}; -pub(crate) use shared::{ALL_OPERATIONS, FloatTy, MathOpInfo, Ty}; use syn::spanned::Spanned; use syn::visit_mut::VisitMut; -use syn::{Ident, ItemEnum}; +use syn::{Ident, ItemEnum, PathArguments, PathSegment}; const KNOWN_TYPES: &[&str] = &[ - "FTy", "CFn", "CArgs", "CRet", "RustFn", "RustArgs", "RustRet", "public", + "CFn", "CArgs", "CRet", "RustFn", "RustArgs", "RustRet", "path", ]; /// Populate an enum with a variant representing function. Names are in upper camel case. @@ -66,8 +65,6 @@ pub fn base_name_enum(attributes: pm::TokenStream, tokens: pm::TokenStream) -> p /// ( /// // Name of that function /// fn_name: $fn_name:ident, -/// // The basic float type for this function (e.g. `f32`, `f64`) -/// FTy: $FTy:ty, /// // Function signature of the C version (e.g. `fn(f32, &mut f32) -> f32`) /// CFn: $CFn:ty, /// // A tuple representing the C version's arguments (e.g. `(f32, &mut f32)`) @@ -80,8 +77,8 @@ pub fn base_name_enum(attributes: pm::TokenStream, tokens: pm::TokenStream) -> p /// RustArgs: $RustArgs:ty, /// // The Rust version's return type (e.g. `(f32, f32)`) /// RustRet: $RustRet:ty, -/// // True if this is part of `libm`'s public API -/// public: $public:expr, +/// // Path to the function, e.g. `libm::fma` or `crate::builtins_wrapper::addf32`. +/// path: $path:path, /// // Attributes for the current function, if any /// attrs: [$($attr:meta),*], /// // Extra tokens passed directly (if any) @@ -143,11 +140,12 @@ pub fn for_each_function(tokens: pm::TokenStream) -> pm::TokenStream { fn validate(input: &mut StructuredInput) -> syn::Result> { // Replace magic mappers with a list of relevant functions. if let Some(map) = &mut input.fn_extra { - for (name, ty) in [ - ("ALL_F16", FloatTy::F16), - ("ALL_F32", FloatTy::F32), - ("ALL_F64", FloatTy::F64), - ("ALL_F128", FloatTy::F128), + for (name, group) in [ + ("ALL_F16", Group::F16), + ("ALL_F32", Group::F32), + ("ALL_F64", Group::F64), + ("ALL_F128", Group::F128), + ("ALL_INT", Group::Integer), ] { let Some(k) = map.keys().find(|key| *key == name) else { continue; @@ -156,7 +154,19 @@ fn validate(input: &mut StructuredInput) -> syn::Result let key = k.clone(); let val = map.remove(&key).unwrap(); - for op in ALL_OPERATIONS.iter().filter(|op| op.float_ty == ty) { + for op in ALL_OPERATIONS.iter().filter(|op| op.group == group) { + map.insert(Ident::new(op.name, key.span()), val.clone()); + } + } + + if let Some(k) = map.keys().find(|key| *key == "ALL_BUILTINS") { + let key = k.clone(); + let val = map.remove(&key).unwrap(); + + for op in ALL_OPERATIONS + .iter() + .filter(|op| op.scope.defined_in_compiler_builtins()) + { map.insert(Ident::new(op.name, key.span()), val.clone()); } } @@ -220,8 +230,23 @@ fn validate(input: &mut StructuredInput) -> syn::Result } // Omit f16 and f128 functions if requested - if input.skip_f16_f128 && (func.float_ty == FloatTy::F16 || func.float_ty == FloatTy::F128) - { + if input.skip_f16_f128 { + if matches!(func.group, Group::F16 | Group::F128) { + continue; + } + + if func + .rust_sig + .args + .iter() + .chain(func.rust_sig.returns.iter()) + .any(|ty| matches!(ty, Ty::F16 | Ty::F128)) + { + continue; + } + } + + if input.skip_builtins && func.scope.defined_in_compiler_builtins() { continue; } @@ -356,25 +381,33 @@ fn expand(input: StructuredInput, fn_list: &[&MathOpInfo]) -> syn::Result pm2::TokenStream::new(), }; - let base_fty = func.float_ty; - let c_args = &func.c_sig.args; - let c_ret = &func.c_sig.returns; - let rust_args = &func.rust_sig.args; - let rust_ret = &func.rust_sig.returns; - let public = func.public; + let path = syn::Path { + leading_colon: None, + segments: func + .path + .split("::") + .map(|pseg| PathSegment { + ident: Ident::new(pseg, Span::call_site()), + arguments: PathArguments::None, + }) + .collect(), + }; let mut ty_fields = Vec::new(); for ty in &input.emit_types { + let c_args = func.c_sig.args.iter().copied().map(ty_to_tokens); + let c_ret = func.c_sig.returns.iter().copied().map(ty_to_tokens); + let rust_args = func.rust_sig.args.iter().copied().map(ty_to_tokens); + let rust_ret = func.rust_sig.returns.iter().copied().map(ty_to_tokens); let field = match ty.to_string().as_str() { - "FTy" => quote! { FTy: #base_fty, }, "CFn" => quote! { CFn: fn( #(#c_args),* ,) -> ( #(#c_ret),* ), }, "CArgs" => quote! { CArgs: ( #(#c_args),* ,), }, "CRet" => quote! { CRet: ( #(#c_ret),* ), }, "RustFn" => quote! { RustFn: fn( #(#rust_args),* ,) -> ( #(#rust_ret),* ), }, "RustArgs" => quote! { RustArgs: ( #(#rust_args),* ,), }, "RustRet" => quote! { RustRet: ( #(#rust_ret),* ), }, - "public" => quote! { public: #public, }, - _ => unreachable!("checked in validation"), + "path" => quote! { path: #path, }, + _ => unreachable!("fields should be checked in validation"), }; ty_fields.push(field); } @@ -450,7 +483,7 @@ impl VisitMut for MacroReplace { /// Return the unsuffixed version of a function name; e.g. `abs` and `absf` both return `abs`, /// `lgamma_r` and `lgammaf_r` both return `lgamma_r`. fn base_name(name: &str) -> &str { - let known_mappings = &[ + let known_mappings = [ ("erff", "erf"), ("erf", "erf"), ("lgammaf_r", "lgamma_r"), @@ -458,45 +491,55 @@ fn base_name(name: &str) -> &str { ("modf", "modf"), ]; - match known_mappings.iter().find(|known| known.0 == name) { - Some(found) => found.1, - None => name - .strip_suffix("f") - .or_else(|| name.strip_suffix("f16")) - .or_else(|| name.strip_suffix("f128")) - .unwrap_or(name), + if let Some(found) = known_mappings.iter().find(|known| known.0 == name) { + return found.1; } -} -impl ToTokens for Ty { - fn to_tokens(&self, tokens: &mut pm2::TokenStream) { - let ts = match self { - Ty::F16 => quote! { f16 }, - Ty::F32 => quote! { f32 }, - Ty::F64 => quote! { f64 }, - Ty::F128 => quote! { f128 }, - Ty::I32 => quote! { i32 }, - Ty::CInt => quote! { ::core::ffi::c_int }, - Ty::MutF16 => quote! { &'a mut f16 }, - Ty::MutF32 => quote! { &'a mut f32 }, - Ty::MutF64 => quote! { &'a mut f64 }, - Ty::MutF128 => quote! { &'a mut f128 }, - Ty::MutI32 => quote! { &'a mut i32 }, - Ty::MutCInt => quote! { &'a mut core::ffi::c_int }, - }; + // Attempt to strip unambiguous suffixes first. This is repeated so e.g. + // `extend_f32_f64` turns into `extend`. + let strip = [ + "_f16", "_f32", "_f64", "_f128", "_i32", "_i64", "_i128", "_u32", "_u64", "_u128", "f16", + "f32", "f64", "f128", + ]; - tokens.extend(ts); + let mut any_found = false; + let mut ret = name; + + for sfx in strip { + if let Some(stripped) = ret.strip_suffix(sfx) { + ret = stripped; + any_found = true; + } + } + + // Only if no suffix was stripped, try stripping the C-style float suffix. + if !any_found && let Some(stripped) = ret.strip_suffix("f") { + ret = stripped; } + + ret } -impl ToTokens for FloatTy { - fn to_tokens(&self, tokens: &mut pm2::TokenStream) { - let ts = match self { - FloatTy::F16 => quote! { f16 }, - FloatTy::F32 => quote! { f32 }, - FloatTy::F64 => quote! { f64 }, - FloatTy::F128 => quote! { f128 }, - }; - tokens.extend(ts); +fn ty_to_tokens(ty: Ty) -> pm2::TokenStream { + match ty { + Ty::F16 => quote! { f16 }, + Ty::F32 => quote! { f32 }, + Ty::F64 => quote! { f64 }, + Ty::F128 => quote! { f128 }, + Ty::I32 => quote! { i32 }, + Ty::I64 => quote! { i64 }, + Ty::I128 => quote! { i128 }, + Ty::U32 => quote! { u32 }, + Ty::U64 => quote! { u64 }, + Ty::U128 => quote! { u128 }, + Ty::USize => quote! { usize }, + Ty::Bool => quote! { bool }, + Ty::CInt => quote! { ::core::ffi::c_int }, + Ty::MutF16 => quote! { &'a mut f16 }, + Ty::MutF32 => quote! { &'a mut f32 }, + Ty::MutF64 => quote! { &'a mut f64 }, + Ty::MutF128 => quote! { &'a mut f128 }, + Ty::MutI32 => quote! { &'a mut i32 }, + Ty::MutCInt => quote! { &'a mut core::ffi::c_int }, } } diff --git a/library/compiler-builtins/crates/libm-macros/src/parse.rs b/library/compiler-builtins/crates/libm-macros/src/parse.rs index 4876f3ef7263a..87add92996ccc 100644 --- a/library/compiler-builtins/crates/libm-macros/src/parse.rs +++ b/library/compiler-builtins/crates/libm-macros/src/parse.rs @@ -50,9 +50,13 @@ pub struct StructuredInput { pub emit_types: Vec, /// Skip these functions pub skip: Vec, - /// If true, omit f16 and f128 functions that aren't present in other libraries. + /// If true, omit f16 and f128 functions that may not be present in libraries we test + /// against (e.g. musl). pub skip_f16_f128: bool, - /// Invoke only for these functions + /// If true, omit functions that are defined in `compiler-builtins` and are not present + /// in libraries we test against (e.g. musl). + pub skip_builtins: bool, + /// Invoke only for the functions listed here. pub only: Option>, /// Attributes that get applied to specific functions pub attributes: Option>, @@ -73,6 +77,7 @@ impl StructuredInput { let emit_types_expr = expect_field(&mut map, "emit_types").ok(); let skip_expr = expect_field(&mut map, "skip").ok(); let skip_f16_f128 = expect_field(&mut map, "skip_f16_f128").ok(); + let skip_builtins = expect_field(&mut map, "skip_builtins").ok(); let only_expr = expect_field(&mut map, "only").ok(); let attr_expr = expect_field(&mut map, "attributes").ok(); let extra = expect_field(&mut map, "extra").ok(); @@ -101,6 +106,11 @@ impl StructuredInput { None => false, }; + let skip_builtins = match skip_builtins { + Some(expr) => expect_litbool(expr)?.value, + None => false, + }; + let only_span = only_expr.as_ref().map(|expr| expr.span()); let only = match only_expr { Some(expr) => Some(Parser::parse2(parse_ident_array, expr.into_token_stream())?), @@ -131,6 +141,7 @@ impl StructuredInput { emit_types, skip, skip_f16_f128, + skip_builtins, only, only_span, attributes, @@ -170,7 +181,6 @@ fn extract_fn_extra_field(expr: Expr) -> syn::Result> { let Arm { attrs, pat, - guard, fat_arrow_token: _, body, comma: _, @@ -179,15 +189,15 @@ fn extract_fn_extra_field(expr: Expr) -> syn::Result> { expect_empty_attrs(&attrs)?; let keys = match pat { + syn::Pat::Ident(id) => Parser::parse2(parse_ident_pat, id.into_token_stream())?, + syn::Pat::Or(or) => Parser::parse2(parse_ident_pat, or.into_token_stream())?, syn::Pat::Wild(w) => vec![Ident::new("_", w.span())], - _ => Parser::parse2(parse_ident_pat, pat.into_token_stream())?, + _ => { + let e = syn::Error::new(pat.span(), "unsupported pattern type"); + return Err(e); + } }; - if let Some(guard) = guard { - let e = syn::Error::new(guard.0.span(), "no guards allowed in this position"); - return Err(e); - } - for key in keys { let inserted = res.insert(key.clone(), *body.clone()); if inserted.is_some() { diff --git a/library/compiler-builtins/crates/libm-macros/src/shared.rs b/library/compiler-builtins/crates/libm-macros/src/shared.rs deleted file mode 100644 index 1cefe4e8c7ed4..0000000000000 --- a/library/compiler-builtins/crates/libm-macros/src/shared.rs +++ /dev/null @@ -1,590 +0,0 @@ -/* List of all functions that is shared between `libm-macros` and `libm-test`. */ - -use std::fmt; -use std::sync::LazyLock; - -struct NestedOp { - float_ty: FloatTy, - rust_sig: Signature, - c_sig: Option, - fn_list: &'static [&'static str], - public: bool, -} - -/// We need a flat list to work with most of the time, but define things as a more convenient -/// nested list. -const ALL_OPERATIONS_NESTED: &[NestedOp] = &[ - NestedOp { - // `fn(f16) -> f16` - float_ty: FloatTy::F16, - rust_sig: Signature { - args: &[Ty::F16], - returns: &[Ty::F16], - }, - c_sig: None, - fn_list: &[ - "ceilf16", - "fabsf16", - "floorf16", - "rintf16", - "roundevenf16", - "roundf16", - "sqrtf16", - "truncf16", - ], - public: true, - }, - NestedOp { - // `fn(f32) -> f32` - float_ty: FloatTy::F32, - rust_sig: Signature { - args: &[Ty::F32], - returns: &[Ty::F32], - }, - c_sig: None, - fn_list: &[ - "acosf", - "acoshf", - "asinf", - "asinhf", - "atanf", - "atanhf", - "cbrtf", - "ceilf", - "cosf", - "coshf", - "erfcf", - "erff", - "exp10f", - "exp2f", - "expf", - "expm1f", - "fabsf", - "floorf", - "j0f", - "j1f", - "lgammaf", - "log10f", - "log1pf", - "log2f", - "logf", - "rintf", - "roundevenf", - "roundf", - "sinf", - "sinhf", - "sqrtf", - "tanf", - "tanhf", - "tgammaf", - "truncf", - "y0f", - "y1f", - ], - public: true, - }, - NestedOp { - // `(f64) -> f64` - float_ty: FloatTy::F64, - rust_sig: Signature { - args: &[Ty::F64], - returns: &[Ty::F64], - }, - c_sig: None, - fn_list: &[ - "acos", - "acosh", - "asin", - "asinh", - "atan", - "atanh", - "cbrt", - "ceil", - "cos", - "cosh", - "erf", - "erfc", - "exp", - "exp10", - "exp2", - "expm1", - "fabs", - "floor", - "j0", - "j1", - "lgamma", - "log", - "log10", - "log1p", - "log2", - "rint", - "round", - "roundeven", - "sin", - "sinh", - "sqrt", - "tan", - "tanh", - "tgamma", - "trunc", - "y0", - "y1", - ], - public: true, - }, - NestedOp { - // `fn(f128) -> f128` - float_ty: FloatTy::F128, - rust_sig: Signature { - args: &[Ty::F128], - returns: &[Ty::F128], - }, - c_sig: None, - fn_list: &[ - "ceilf128", - "fabsf128", - "floorf128", - "rintf128", - "roundevenf128", - "roundf128", - "sqrtf128", - "truncf128", - ], - public: true, - }, - NestedOp { - // `(f16, f16) -> f16` - float_ty: FloatTy::F16, - rust_sig: Signature { - args: &[Ty::F16, Ty::F16], - returns: &[Ty::F16], - }, - c_sig: None, - fn_list: &[ - "copysignf16", - "fdimf16", - "fmaxf16", - "fmaximum_numf16", - "fmaximumf16", - "fminf16", - "fminimum_numf16", - "fminimumf16", - "fmodf16", - ], - public: true, - }, - NestedOp { - // `(f32, f32) -> f32` - float_ty: FloatTy::F32, - rust_sig: Signature { - args: &[Ty::F32, Ty::F32], - returns: &[Ty::F32], - }, - c_sig: None, - fn_list: &[ - "atan2f", - "copysignf", - "fdimf", - "fmaxf", - "fmaximum_numf", - "fmaximumf", - "fminf", - "fminimum_numf", - "fminimumf", - "fmodf", - "hypotf", - "nextafterf", - "powf", - "remainderf", - ], - public: true, - }, - NestedOp { - // `(f64, f64) -> f64` - float_ty: FloatTy::F64, - rust_sig: Signature { - args: &[Ty::F64, Ty::F64], - returns: &[Ty::F64], - }, - c_sig: None, - fn_list: &[ - "atan2", - "copysign", - "fdim", - "fmax", - "fmaximum", - "fmaximum_num", - "fmin", - "fminimum", - "fminimum_num", - "fmod", - "hypot", - "nextafter", - "pow", - "remainder", - ], - public: true, - }, - NestedOp { - // `(f128, f128) -> f128` - float_ty: FloatTy::F128, - rust_sig: Signature { - args: &[Ty::F128, Ty::F128], - returns: &[Ty::F128], - }, - c_sig: None, - fn_list: &[ - "copysignf128", - "fdimf128", - "fmaxf128", - "fmaximum_numf128", - "fmaximumf128", - "fminf128", - "fminimum_numf128", - "fminimumf128", - "fmodf128", - ], - public: true, - }, - NestedOp { - // `(f32, f32, f32) -> f32` - float_ty: FloatTy::F32, - rust_sig: Signature { - args: &[Ty::F32, Ty::F32, Ty::F32], - returns: &[Ty::F32], - }, - c_sig: None, - fn_list: &["fmaf"], - public: true, - }, - NestedOp { - // `(f64, f64, f64) -> f64` - float_ty: FloatTy::F64, - rust_sig: Signature { - args: &[Ty::F64, Ty::F64, Ty::F64], - returns: &[Ty::F64], - }, - c_sig: None, - fn_list: &["fma"], - public: true, - }, - NestedOp { - // `(f128, f128, f128) -> f128` - float_ty: FloatTy::F128, - rust_sig: Signature { - args: &[Ty::F128, Ty::F128, Ty::F128], - returns: &[Ty::F128], - }, - c_sig: None, - fn_list: &["fmaf128"], - public: true, - }, - NestedOp { - // `(f32) -> i32` - float_ty: FloatTy::F32, - rust_sig: Signature { - args: &[Ty::F32], - returns: &[Ty::I32], - }, - c_sig: None, - fn_list: &["ilogbf"], - public: true, - }, - NestedOp { - // `(f64) -> i32` - float_ty: FloatTy::F64, - rust_sig: Signature { - args: &[Ty::F64], - returns: &[Ty::I32], - }, - c_sig: None, - fn_list: &["ilogb"], - public: true, - }, - NestedOp { - // `(i32, f32) -> f32` - float_ty: FloatTy::F32, - rust_sig: Signature { - args: &[Ty::I32, Ty::F32], - returns: &[Ty::F32], - }, - c_sig: None, - fn_list: &["jnf", "ynf"], - public: true, - }, - NestedOp { - // `(i32, f64) -> f64` - float_ty: FloatTy::F64, - rust_sig: Signature { - args: &[Ty::I32, Ty::F64], - returns: &[Ty::F64], - }, - c_sig: None, - fn_list: &["jn", "yn"], - public: true, - }, - NestedOp { - // `(f16, i32) -> f16` - float_ty: FloatTy::F16, - rust_sig: Signature { - args: &[Ty::F16, Ty::I32], - returns: &[Ty::F16], - }, - c_sig: None, - fn_list: &["ldexpf16", "scalbnf16"], - public: true, - }, - NestedOp { - // `(f32, i32) -> f32` - float_ty: FloatTy::F32, - rust_sig: Signature { - args: &[Ty::F32, Ty::I32], - returns: &[Ty::F32], - }, - c_sig: None, - fn_list: &["ldexpf", "scalbnf"], - public: true, - }, - NestedOp { - // `(f64, i64) -> f64` - float_ty: FloatTy::F64, - rust_sig: Signature { - args: &[Ty::F64, Ty::I32], - returns: &[Ty::F64], - }, - c_sig: None, - fn_list: &["ldexp", "scalbn"], - public: true, - }, - NestedOp { - // `(f128, i32) -> f128` - float_ty: FloatTy::F128, - rust_sig: Signature { - args: &[Ty::F128, Ty::I32], - returns: &[Ty::F128], - }, - c_sig: None, - fn_list: &["ldexpf128", "scalbnf128"], - public: true, - }, - NestedOp { - // `(f32, &mut f32) -> f32` as `(f32) -> (f32, f32)` - float_ty: FloatTy::F32, - rust_sig: Signature { - args: &[Ty::F32], - returns: &[Ty::F32, Ty::F32], - }, - c_sig: Some(Signature { - args: &[Ty::F32, Ty::MutF32], - returns: &[Ty::F32], - }), - fn_list: &["modff"], - public: true, - }, - NestedOp { - // `(f64, &mut f64) -> f64` as `(f64) -> (f64, f64)` - float_ty: FloatTy::F64, - rust_sig: Signature { - args: &[Ty::F64], - returns: &[Ty::F64, Ty::F64], - }, - c_sig: Some(Signature { - args: &[Ty::F64, Ty::MutF64], - returns: &[Ty::F64], - }), - fn_list: &["modf"], - public: true, - }, - NestedOp { - // `(f32, &mut c_int) -> f32` as `(f32) -> (f32, i32)` - float_ty: FloatTy::F32, - rust_sig: Signature { - args: &[Ty::F32], - returns: &[Ty::F32, Ty::I32], - }, - c_sig: Some(Signature { - args: &[Ty::F32, Ty::MutCInt], - returns: &[Ty::F32], - }), - fn_list: &["frexpf", "lgammaf_r"], - public: true, - }, - NestedOp { - // `(f64, &mut c_int) -> f64` as `(f64) -> (f64, i32)` - float_ty: FloatTy::F64, - rust_sig: Signature { - args: &[Ty::F64], - returns: &[Ty::F64, Ty::I32], - }, - c_sig: Some(Signature { - args: &[Ty::F64, Ty::MutCInt], - returns: &[Ty::F64], - }), - fn_list: &["frexp", "lgamma_r"], - public: true, - }, - NestedOp { - // `(f32, f32, &mut c_int) -> f32` as `(f32, f32) -> (f32, i32)` - float_ty: FloatTy::F32, - rust_sig: Signature { - args: &[Ty::F32, Ty::F32], - returns: &[Ty::F32, Ty::I32], - }, - c_sig: Some(Signature { - args: &[Ty::F32, Ty::F32, Ty::MutCInt], - returns: &[Ty::F32], - }), - fn_list: &["remquof"], - public: true, - }, - NestedOp { - // `(f64, f64, &mut c_int) -> f64` as `(f64, f64) -> (f64, i32)` - float_ty: FloatTy::F64, - rust_sig: Signature { - args: &[Ty::F64, Ty::F64], - returns: &[Ty::F64, Ty::I32], - }, - c_sig: Some(Signature { - args: &[Ty::F64, Ty::F64, Ty::MutCInt], - returns: &[Ty::F64], - }), - fn_list: &["remquo"], - public: true, - }, - NestedOp { - // `(f32, &mut f32, &mut f32)` as `(f32) -> (f32, f32)` - float_ty: FloatTy::F32, - rust_sig: Signature { - args: &[Ty::F32], - returns: &[Ty::F32, Ty::F32], - }, - c_sig: Some(Signature { - args: &[Ty::F32, Ty::MutF32, Ty::MutF32], - returns: &[], - }), - fn_list: &["sincosf"], - public: true, - }, - NestedOp { - // `(f64, &mut f64, &mut f64)` as `(f64) -> (f64, f64)` - float_ty: FloatTy::F64, - rust_sig: Signature { - args: &[Ty::F64], - returns: &[Ty::F64, Ty::F64], - }, - c_sig: Some(Signature { - args: &[Ty::F64, Ty::MutF64, Ty::MutF64], - returns: &[], - }), - fn_list: &["sincos"], - public: true, - }, -]; - -/// A type used in a function signature. -#[allow(dead_code)] -#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)] -pub enum Ty { - F16, - F32, - F64, - F128, - I32, - CInt, - MutF16, - MutF32, - MutF64, - MutF128, - MutI32, - MutCInt, -} - -/// A subset of [`Ty`] representing only floats. -#[allow(dead_code)] -#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)] -pub enum FloatTy { - F16, - F32, - F64, - F128, -} - -impl fmt::Display for Ty { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let s = match self { - Ty::F16 => "f16", - Ty::F32 => "f32", - Ty::F64 => "f64", - Ty::F128 => "f128", - Ty::I32 => "i32", - Ty::CInt => "::core::ffi::c_int", - Ty::MutF16 => "&mut f16", - Ty::MutF32 => "&mut f32", - Ty::MutF64 => "&mut f64", - Ty::MutF128 => "&mut f128", - Ty::MutI32 => "&mut i32", - Ty::MutCInt => "&mut ::core::ffi::c_int", - }; - f.write_str(s) - } -} - -impl fmt::Display for FloatTy { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let s = match self { - FloatTy::F16 => "f16", - FloatTy::F32 => "f32", - FloatTy::F64 => "f64", - FloatTy::F128 => "f128", - }; - f.write_str(s) - } -} - -/// Representation of e.g. `(f32, f32) -> f32` -#[derive(Debug, Clone)] -pub struct Signature { - pub args: &'static [Ty], - pub returns: &'static [Ty], -} - -/// Combined information about a function implementation. -#[derive(Debug, Clone)] -pub struct MathOpInfo { - pub name: &'static str, - pub float_ty: FloatTy, - /// Function signature for C implementations - pub c_sig: Signature, - /// Function signature for Rust implementations - pub rust_sig: Signature, - /// True if part of libm's public API - pub public: bool, -} - -/// A flat representation of `ALL_FUNCTIONS`. -pub static ALL_OPERATIONS: LazyLock> = LazyLock::new(|| { - let mut ret = Vec::new(); - - for op in ALL_OPERATIONS_NESTED { - let fn_names = op.fn_list; - for name in fn_names { - let api = MathOpInfo { - name, - float_ty: op.float_ty, - rust_sig: op.rust_sig.clone(), - c_sig: op.c_sig.clone().unwrap_or_else(|| op.rust_sig.clone()), - public: op.public, - }; - ret.push(api); - } - - if !fn_names.is_sorted() { - let mut sorted = (*fn_names).to_owned(); - sorted.sort_unstable(); - panic!("names list is not sorted: {fn_names:?}\nExpected: {sorted:?}"); - } - } - - ret.sort_by_key(|item| item.name); - ret -}); diff --git a/library/compiler-builtins/crates/libm-macros/tests/basic.rs b/library/compiler-builtins/crates/libm-macros/tests/basic.rs index b4276262229fe..668127c298e47 100644 --- a/library/compiler-builtins/crates/libm-macros/tests/basic.rs +++ b/library/compiler-builtins/crates/libm-macros/tests/basic.rs @@ -1,3 +1,4 @@ +#![allow(unused_features)] #![feature(f16)] #![feature(f128)] // `STATUS_DLL_NOT_FOUND` on i686 MinGW, not worth looking into. @@ -6,14 +7,13 @@ macro_rules! basic { ( fn_name: $fn_name:ident, - FTy: $FTy:ty, CFn: $CFn:ty, CArgs: $CArgs:ty, CRet: $CRet:ty, RustFn: $RustFn:ty, RustArgs: $RustArgs:ty, RustRet: $RustRet:ty, - public: $public:expr, + path: $path:path, attrs: [$($attr:meta),*], extra: [$($extra_tt:tt)*], fn_extra: $fn_extra:expr, @@ -21,12 +21,11 @@ macro_rules! basic { $(#[$attr])* #[allow(dead_code)] pub mod $fn_name { - type FTy= $FTy; type CFnTy<'a> = $CFn; type RustFnTy = $RustFn; type RustArgsTy = $RustArgs; type RustRetTy = $RustRet; - const PUBLIC: bool = $public; + const PATH: &str = stringify!($path); const A: &[&str] = &[$($extra_tt)*]; fn foo(a: f32) -> f32 { $fn_extra(a) @@ -146,6 +145,7 @@ fn test_fn_extra_expansion() { let mut vf32 = Vec::new(); let mut vf64 = Vec::new(); let mut vf128 = Vec::new(); + let mut vbuiltins = Vec::new(); // Test with no extra, no skip, and no attributes libm_macros::for_each_function! { @@ -155,6 +155,7 @@ fn test_fn_extra_expansion() { ALL_F32 => vf32, ALL_F64 => vf64, ALL_F128 => vf128, + ALL_BUILTINS => vbuiltins, } } @@ -170,8 +171,11 @@ fn test_fn_extra_expansion() { for name in vf32 { assert!(name.ends_with("f"), "{name}"); } - let _ = vf64; for name in vf128 { assert!(name.ends_with("f128"), "{name}"); } + + // Nothing to assert here + let _ = vf64; + let _ = vbuiltins; } diff --git a/library/compiler-builtins/crates/libm-macros/tests/enum.rs b/library/compiler-builtins/crates/libm-macros/tests/enum.rs index 93e209a0dcc90..f012e0a9ef0ad 100644 --- a/library/compiler-builtins/crates/libm-macros/tests/enum.rs +++ b/library/compiler-builtins/crates/libm-macros/tests/enum.rs @@ -23,16 +23,3 @@ fn basename() { assert_eq!(Identifier::Sin.base_name(), BaseName::Sin); assert_eq!(Identifier::Sinf.base_name(), BaseName::Sin); } - -#[test] -fn math_op() { - assert_eq!(Identifier::Sin.math_op().float_ty, FloatTy::F64); - assert_eq!(Identifier::Sinf.math_op().float_ty, FloatTy::F32); -} - -// Replicate the structure that we have in `libm-test` -mod op { - include!("../../libm-macros/src/shared.rs"); -} - -use op::FloatTy; diff --git a/library/compiler-builtins/crates/musl-math-sys/Cargo.toml b/library/compiler-builtins/crates/musl-math-sys/Cargo.toml index 39f6fa9065bd9..eb97ffbc86693 100644 --- a/library/compiler-builtins/crates/musl-math-sys/Cargo.toml +++ b/library/compiler-builtins/crates/musl-math-sys/Cargo.toml @@ -5,10 +5,8 @@ edition = "2024" publish = false license = "MIT OR Apache-2.0" -[dependencies] - [dev-dependencies] -libm = { path = "../../libm" } +libm.workspace = true [build-dependencies] -cc = "1.2.29" +cc.workspace = true diff --git a/library/compiler-builtins/crates/musl-math-sys/build.rs b/library/compiler-builtins/crates/musl-math-sys/build.rs index 3bab5f2eb112a..7f7080daa9943 100644 --- a/library/compiler-builtins/crates/musl-math-sys/build.rs +++ b/library/compiler-builtins/crates/musl-math-sys/build.rs @@ -52,7 +52,7 @@ fn main() { println!( "cargo::warning=Musl doesn't compile with the current \ target {}; skipping build", - &cfg.target_string + cfg.target_string ); return; } diff --git a/library/compiler-builtins/crates/symbol-check/Cargo.toml b/library/compiler-builtins/crates/symbol-check/Cargo.toml deleted file mode 100644 index e2218b4917200..0000000000000 --- a/library/compiler-builtins/crates/symbol-check/Cargo.toml +++ /dev/null @@ -1,12 +0,0 @@ -[package] -name = "symbol-check" -version = "0.1.0" -edition = "2024" -publish = false - -[dependencies] -object = "0.37.1" -serde_json = "1.0.140" - -[features] -wasm = ["object/wasm"] diff --git a/library/compiler-builtins/crates/symbol-check/src/main.rs b/library/compiler-builtins/crates/symbol-check/src/main.rs deleted file mode 100644 index 7d0b7e90addb5..0000000000000 --- a/library/compiler-builtins/crates/symbol-check/src/main.rs +++ /dev/null @@ -1,362 +0,0 @@ -//! Tool used by CI to inspect compiler-builtins archives and help ensure we won't run into any -//! linking errors. - -use std::collections::{BTreeMap, BTreeSet}; -use std::fs; -use std::io::{BufRead, BufReader}; -use std::path::{Path, PathBuf}; -use std::process::{Command, Stdio}; - -use object::read::archive::ArchiveFile; -use object::{ - File as ObjFile, Object, ObjectSection, ObjectSymbol, Result as ObjResult, Symbol, SymbolKind, - SymbolScope, -}; -use serde_json::Value; - -const CHECK_LIBRARIES: &[&str] = &["compiler_builtins", "builtins_test_intrinsics"]; -const CHECK_EXTENSIONS: &[Option<&str>] = &[Some("rlib"), Some("a"), Some("exe"), None]; - -const USAGE: &str = "Usage: - - symbol-check build-and-check [TARGET] -- CARGO_BUILD_ARGS ... - -Cargo will get invoked with `CARGO_ARGS` and the specified target. All output -`compiler_builtins*.rlib` files will be checked. - -If TARGET is not specified, the host target is used. - - check PATHS ... - -Run the same checks on the given set of paths, without invoking Cargo. Paths -may be either archives or object files. -"; - -fn main() { - // Create a `&str` vec so we can match on it. - let args = std::env::args().collect::>(); - let args_ref = args.iter().map(String::as_str).collect::>(); - - match &args_ref[1..] { - ["build-and-check", target, "--", args @ ..] if !args.is_empty() => { - run_build_and_check(target, args); - } - ["build-and-check", "--", args @ ..] if !args.is_empty() => { - let target = &host_target(); - run_build_and_check(target, args); - } - ["check", paths @ ..] if !paths.is_empty() => { - check_paths(paths); - } - _ => { - println!("{USAGE}"); - std::process::exit(1); - } - } -} - -fn run_build_and_check(target: &str, args: &[&str]) { - // Make sure `--target` isn't passed to avoid confusion (since it should be - // proivded only once, positionally). - for arg in args { - assert!( - !arg.contains("--target"), - "target must be passed positionally. {USAGE}" - ); - } - - let paths = exec_cargo_with_args(target, args); - check_paths(&paths); -} - -fn check_paths>(paths: &[P]) { - for path in paths { - let path = path.as_ref(); - println!("Checking {}", path.display()); - let archive = BinFile::from_path(path); - - verify_no_duplicates(&archive); - verify_core_symbols(&archive); - } -} - -fn host_target() -> String { - let out = Command::new("rustc") - .arg("--version") - .arg("--verbose") - .output() - .unwrap(); - assert!(out.status.success()); - let out = String::from_utf8(out.stdout).unwrap(); - out.lines() - .find_map(|s| s.strip_prefix("host: ")) - .unwrap() - .to_owned() -} - -/// Run `cargo build` with the provided additional arguments, collecting the list of created -/// libraries. -fn exec_cargo_with_args(target: &str, args: &[&str]) -> Vec { - let mut cmd = Command::new("cargo"); - cmd.args([ - "build", - "--target", - target, - "--message-format=json-diagnostic-rendered-ansi", - ]) - .args(args) - .stdout(Stdio::piped()); - - println!("running: {cmd:?}"); - let mut child = cmd.spawn().expect("failed to launch Cargo"); - - let stdout = child.stdout.take().unwrap(); - let reader = BufReader::new(stdout); - let mut check_files = Vec::new(); - - for line in reader.lines() { - let line = line.expect("failed to read line"); - let j: Value = serde_json::from_str(&line).expect("failed to deserialize"); - let reason = &j["reason"]; - - // Forward output that is meant to be user-facing - if reason == "compiler-message" { - println!("{}", j["message"]["rendered"].as_str().unwrap()); - } else if reason == "build-finished" { - println!("build finshed. success: {}", j["success"]); - } else if reason == "build-script-executed" { - let pretty = serde_json::to_string_pretty(&j).unwrap(); - println!("build script output: {pretty}",); - } - - // Only interested in the artifact list now - if reason != "compiler-artifact" { - continue; - } - - // Find rlibs in the created file list that match our expected library names and - // extensions. - for fpath in j["filenames"].as_array().expect("filenames not an array") { - let path = fpath.as_str().expect("file name not a string"); - let path = PathBuf::from(path); - - if CHECK_EXTENSIONS.contains(&path.extension().map(|ex| ex.to_str().unwrap())) { - let fname = path.file_name().unwrap().to_str().unwrap(); - - if CHECK_LIBRARIES.iter().any(|lib| fname.contains(lib)) { - check_files.push(path); - } - } - } - } - - assert!(child.wait().expect("failed to wait on Cargo").success()); - - assert!(!check_files.is_empty(), "no compiler_builtins rlibs found"); - println!("Collected the following rlibs to check: {check_files:#?}"); - - check_files -} - -/// Information collected from `object`, for convenience. -#[expect(unused)] // only for printing -#[derive(Clone, Debug)] -struct SymInfo { - name: String, - kind: SymbolKind, - scope: SymbolScope, - section: String, - is_undefined: bool, - is_global: bool, - is_local: bool, - is_weak: bool, - is_common: bool, - address: u64, - object: String, -} - -impl SymInfo { - fn new(sym: &Symbol, obj: &ObjFile, obj_path: &str) -> Self { - // Include the section name if possible. Fall back to the `Section` debug impl if not. - let section = sym.section(); - let section_name = sym - .section() - .index() - .and_then(|idx| obj.section_by_index(idx).ok()) - .and_then(|sec| sec.name().ok()) - .map(ToString::to_string) - .unwrap_or_else(|| format!("{section:?}")); - - Self { - name: sym.name().expect("missing name").to_owned(), - kind: sym.kind(), - scope: sym.scope(), - section: section_name, - is_undefined: sym.is_undefined(), - is_global: sym.is_global(), - is_local: sym.is_local(), - is_weak: sym.is_weak(), - is_common: sym.is_common(), - address: sym.address(), - object: obj_path.to_owned(), - } - } -} - -/// Ensure that the same global symbol isn't defined in multiple object files within an archive. -/// -/// Note that this will also locate cases where a symbol is weakly defined in more than one place. -/// Technically there are no linker errors that will come from this, but it keeps our binary more -/// straightforward and saves some distribution size. -fn verify_no_duplicates(archive: &BinFile) { - let mut syms = BTreeMap::::new(); - let mut dups = Vec::new(); - let mut found_any = false; - - archive.for_each_symbol(|symbol, obj, member| { - // Only check defined globals - if !symbol.is_global() || symbol.is_undefined() { - return; - } - - let sym = SymInfo::new(&symbol, obj, member); - - // x86-32 includes multiple copies of thunk symbols - if sym.name.starts_with("__x86.get_pc_thunk") { - return; - } - - // GDB pretty printing symbols may show up more than once but are weak. - if sym.section == ".debug_gdb_scripts" && sym.is_weak { - return; - } - - // Windows has symbols for literal numeric constants, string literals, and MinGW pseudo- - // relocations. These are allowed to have repeated definitions. - let win_allowed_dup_pfx = ["__real@", "__xmm@", "__ymm@", "??_C@_", ".refptr"]; - if win_allowed_dup_pfx - .iter() - .any(|pfx| sym.name.starts_with(pfx)) - { - return; - } - - match syms.get(&sym.name) { - Some(existing) => { - dups.push(sym); - dups.push(existing.clone()); - } - None => { - syms.insert(sym.name.clone(), sym); - } - } - - found_any = true; - }); - - assert!(found_any, "no symbols found"); - - if !dups.is_empty() { - dups.sort_unstable_by(|a, b| a.name.cmp(&b.name)); - panic!("found duplicate symbols: {dups:#?}"); - } - - println!(" success: no duplicate symbols found"); -} - -/// Ensure that there are no references to symbols from `core` that aren't also (somehow) defined. -fn verify_core_symbols(archive: &BinFile) { - let mut defined = BTreeSet::new(); - let mut undefined = Vec::new(); - let mut has_symbols = false; - - archive.for_each_symbol(|symbol, obj, member| { - has_symbols = true; - - // Find only symbols from `core` - if !symbol.name().unwrap().contains("_ZN4core") { - return; - } - - let sym = SymInfo::new(&symbol, obj, member); - if sym.is_undefined { - undefined.push(sym); - } else { - defined.insert(sym.name); - } - }); - - assert!(has_symbols, "no symbols found"); - - // Discard any symbols that are defined somewhere in the archive - undefined.retain(|sym| !defined.contains(&sym.name)); - - if !undefined.is_empty() { - undefined.sort_unstable_by(|a, b| a.name.cmp(&b.name)); - panic!("found undefined symbols from core: {undefined:#?}"); - } - - println!(" success: no undefined references to core found"); -} - -/// Thin wrapper for owning data used by `object`. -struct BinFile { - path: PathBuf, - data: Vec, -} - -impl BinFile { - fn from_path(path: &Path) -> Self { - Self { - path: path.to_owned(), - data: fs::read(path).expect("reading file failed"), - } - } - - fn as_archive_file(&self) -> ObjResult> { - ArchiveFile::parse(self.data.as_slice()) - } - - fn as_obj_file(&self) -> ObjResult> { - ObjFile::parse(self.data.as_slice()) - } - - /// For a given archive, do something with each object file. For an object file, do - /// something once. - fn for_each_object(&self, mut f: impl FnMut(ObjFile, &str)) { - // Try as an archive first. - let as_archive = self.as_archive_file(); - if let Ok(archive) = as_archive { - for member in archive.members() { - let member = member.expect("failed to access member"); - let obj_data = member - .data(self.data.as_slice()) - .expect("failed to access object"); - let obj = ObjFile::parse(obj_data).expect("failed to parse object"); - f(obj, &String::from_utf8_lossy(member.name())); - } - - return; - } - - // Fall back to parsing as an object file. - let as_obj = self.as_obj_file(); - if let Ok(obj) = as_obj { - f(obj, &self.path.to_string_lossy()); - return; - } - - panic!( - "failed to parse as either archive or object file: {:?}, {:?}", - as_archive.unwrap_err(), - as_obj.unwrap_err(), - ); - } - - /// D something with each symbol in an archive or object file. - fn for_each_symbol(&self, mut f: impl FnMut(Symbol, &ObjFile, &str)) { - self.for_each_object(|obj, obj_path| { - obj.symbols().for_each(|sym| f(sym, &obj, obj_path)); - }); - } -} diff --git a/library/compiler-builtins/crates/symcheck/Cargo.toml b/library/compiler-builtins/crates/symcheck/Cargo.toml new file mode 100644 index 0000000000000..470cb61413c38 --- /dev/null +++ b/library/compiler-builtins/crates/symcheck/Cargo.toml @@ -0,0 +1,16 @@ +[package] +name = "symcheck" +version = "0.1.0" +edition = "2024" +publish = false + +[dependencies] +getopts.workspace = true +object.workspace = true +regex.workspace = true +serde_json.workspace = true + +[dev-dependencies] +assert_cmd.workspace = true +cc.workspace = true +tempfile.workspace = true diff --git a/library/compiler-builtins/crates/symcheck/build.rs b/library/compiler-builtins/crates/symcheck/build.rs new file mode 100644 index 0000000000000..b3e53c38b0bd4 --- /dev/null +++ b/library/compiler-builtins/crates/symcheck/build.rs @@ -0,0 +1,6 @@ +use std::env; + +fn main() { + println!("cargo::rustc-env=HOST={}", env::var("HOST").unwrap()); + println!("cargo::rustc-env=TARGET={}", env::var("TARGET").unwrap()); +} diff --git a/library/compiler-builtins/crates/symcheck/src/main.rs b/library/compiler-builtins/crates/symcheck/src/main.rs new file mode 100644 index 0000000000000..a88aeed40fb0d --- /dev/null +++ b/library/compiler-builtins/crates/symcheck/src/main.rs @@ -0,0 +1,985 @@ +//! Tool used by CI to inspect compiler-builtins archives and help ensure we won't run into any +//! linking errors. +//! +//! Note that symcheck is a "hostprog", i.e. is built and run on the host target even when the +//! actual target is cross compiled. + +#![allow(clippy::enum_variant_names)] + +use std::collections::{BTreeMap, BTreeSet, HashSet}; +use std::io::{BufRead, BufReader}; +use std::path::{Path, PathBuf}; +use std::process::{Command, Stdio, exit}; +use std::sync::LazyLock; +use std::{env, fmt, fs}; + +use object::elf::{ProgramFlags, ProgramType}; +use object::read::archive::ArchiveFile; +use object::read::pe::ImageOptionalHeader; +use object::{ + Architecture, BinaryFormat, Endianness, File as ObjFile, FileFlags, Object, ObjectSection, + ObjectSymbol, Result as ObjResult, SectionFlags, SubArchitecture, Symbol, SymbolKind, + SymbolScope, U32, elf, macho, pe, read, +}; +use regex::Regex; +use serde_json::Value; + +const CHECK_LIBRARIES: &[&str] = &["compiler_builtins", "builtins_test_intrinsics"]; +const CHECK_EXTENSIONS: &[Option<&str>] = &[Some("rlib"), Some("a"), Some("exe"), None]; +const GNU_STACK: &str = ".note.GNU-stack"; + +const USAGE: &str = "Usage: + + symcheck --build-and-check [--target TARGET] [--no-os] -- CARGO_BUILD_ARGS ... + symcheck --check [--target TARGET] PATHS ...\ +"; + +fn main() { + let mut opts = getopts::Options::new(); + + // Ideally these would be subcommands but that isn't supported. + opts.optflag("h", "help", "Print this help message"); + opts.optflag( + "", + "build-and-check", + "Cargo will get invoked with `CARGO_BUILD_ARGS` and the specified target. All output \ + `compiler_builtins*.rlib` files will be checked.", + ); + opts.optopt( + "", + "target", + // We could add a `--no-target-checks` flag to skip checks that need a target specified, + // if that winds up being useful at some point. + "Set the target when building, and the expected target for tests. Falls back to the host \ + target if not specified.", + "TARGET", + ); + opts.optflag( + "", + "check", + "Run checks on the given set of paths, without invoking Cargo. Paths \ + may be either archives or object files.", + ); + opts.optflag( + "", + "no-os", + "The binaries will not be checked for executable stacks. Used for embedded targets which \ + don't set `.note.GNU-stack` since there is no protection.", + ); + opts.optflag("", "no-visibility", "Don't check visibility."); + + let print_usage_and_exit = |code: i32| -> ! { + eprintln!("{}", opts.usage(USAGE)); + exit(code); + }; + + let m = opts.parse(std::env::args().skip(1)).unwrap_or_else(|e| { + eprintln!("{e}"); + print_usage_and_exit(1); + }); + + if m.opt_present("help") { + print_usage_and_exit(0); + } + + let no_os_target = m.opt_present("no-os"); + let check_visibility = !m.opt_present("no-visibility"); + let free_args = m.free.iter().map(String::as_str).collect::>(); + for arg in &free_args { + assert!( + !arg.contains("--target"), + "target must be passed to symcheck" + ); + } + + let target = m.opt_str("target").unwrap_or(env!("HOST").to_string()); + let target = Target::from_rustc(&target); + + if m.opt_present("build-and-check") { + let paths = exec_cargo_with_args(&target.name, &free_args); + check_paths(&target, &paths, no_os_target, check_visibility); + } else if m.opt_present("check") { + if free_args.is_empty() { + print_usage_and_exit(1); + } + check_paths(&target, &free_args, no_os_target, check_visibility); + } else { + print_usage_and_exit(1); + } +} + +fn check_paths>( + target: &Target, + paths: &[P], + no_os_target: bool, + check_visibility: bool, +) { + for path in paths { + let path = path.as_ref(); + println!("Checking {}", path.display()); + let archive = BinFile::from_path(path); + + verify_no_duplicates(&archive); + verify_core_symbols(&archive); + verify_expected_target(target, &archive); + verify_no_exec_stack(&archive, no_os_target); + if check_visibility { + verify_hidden_visibility(&archive); + } + } +} + +#[derive(Debug)] +struct Target { + name: String, + arch: Architecture, + subarch: Option, + endian: Endianness, + pointer_width: PointerWidth, + os: Os, + env: Option, + abi: Option, + families: Vec, + vendors: Vec, +} + +impl Target { + /// Use `rustc` to query target information rather than parsing it ourselves. + fn from_rustc(target: &str) -> Self { + let mut cmd = Command::new("rustc"); + cmd.args(["--target", target, "--print=cfg"]) + .stdout(Stdio::piped()); + println!("running: {cmd:?}"); + let out = cmd.output().expect("failed to launch rustc"); + + let check_empty = |s: &str| { + if s.is_empty() { + None + } else { + Some(s.to_string()) + } + }; + + let mut t = Target { + name: target.to_string(), + arch: Architecture::Unknown, + subarch: None, + endian: Endianness::Little, + pointer_width: PointerWidth::P64, + os: Os::Unknown, + env: None, + abi: None, + families: Vec::new(), + vendors: Vec::new(), + }; + + for line in out.stdout.lines() { + let line = line.expect("failed to read line"); + let Some((k, v)) = line.split_once('=') else { + continue; + }; + let v = v.trim_matches('"'); + + match k { + "target_os" => { + t.os = match v { + "aix" => Os::Aix, + "amdhsa" => Os::Amdhsa, + "android" => Os::Android, + "cuda" => Os::Cuda, + "cygwin" => Os::Cygwin, + "dragonfly" => Os::Dragonfly, + "emscripten" => Os::Emscripten, + "espidf" => Os::EspIdf, + "freebsd" => Os::FreeBsd, + "fuchsia" => Os::Fuchsia, + "haiku" => Os::Haiku, + "helenos" => Os::HelenOs, + "hermit" => Os::Hermit, + "horizon" => Os::Horizon, + "hurd" => Os::Hurd, + "illumos" => Os::Illumos, + "ios" => Os::IOs, + "l4re" => Os::L4re, + "linux" => Os::Linux, + "lynxos178" => Os::LynxOs178, + "macos" => Os::MacOs, + "managarm" => Os::Managarm, + "motor" => Os::Motor, + "netbsd" => Os::NetBsd, + "nto" => Os::Nto, + "nuttx" => Os::Nuttx, + "openbsd" => Os::OpenBsd, + "psp" => Os::Psp, + "psx" => Os::Psx, + "qurt" => Os::Qurt, + "redox" => Os::Redox, + "rtems" => Os::Rtems, + "solaris" => Os::Solaris, + "solid_asp3" => Os::SolidAsp3, + "teeos" => Os::Teeos, + "trusty" => Os::Trusty, + "tvos" => Os::TvOs, + "uefi" => Os::Uefi, + "vexos" => Os::Vexos, + "visionos" => Os::VisionOs, + "vita" => Os::Vita, + "vxworks" => Os::VxXorks, + "wasi" => Os::Wasi, + "watchos" => Os::WatchOs, + "windows" => Os::Windows, + "xous" => Os::Xous, + "zkvm" => Os::Zkvm, + "unknown" | "none" => Os::Unknown, + _ => panic!("unrecognized OS `{v}`"), + } + } + "target_arch" => { + t.arch = match v { + "aarch64" => Architecture::Aarch64, + "arm64ec" => { + t.subarch = Some(SubArchitecture::Arm64EC); + Architecture::Aarch64 + } + "arm" => Architecture::Arm, + "avr" => Architecture::Avr, + "bpf" => Architecture::Bpf, + "csky" => Architecture::Csky, + "hexagon" => Architecture::Hexagon, + "loongarch32" => Architecture::LoongArch32, + "loongarch64" => Architecture::LoongArch64, + "m68k" => Architecture::M68k, + "mips" | "mips32r6" => Architecture::Mips, + "mips64" | "mips64r6" => Architecture::Mips64, + "msp430" => Architecture::Msp430, + "powerpc" => Architecture::PowerPc, + "powerpc64" => Architecture::PowerPc64, + "riscv32" => Architecture::Riscv32, + "riscv64" => Architecture::Riscv64, + "s390x" => Architecture::S390x, + "sparc" => Architecture::Sparc, + "sparc64" => Architecture::Sparc64, + "wasm32" => Architecture::Wasm32, + "wasm64" => Architecture::Wasm64, + "x86" => Architecture::I386, + "x86_64" => Architecture::X86_64, + "xtensa" => Architecture::Xtensa, + _ => panic!("unrecognized arch {v}"), + } + } + "target_abi" => t.abi = check_empty(v), + "target_env" => t.env = check_empty(v), + "target_family" if let Some(fam) = check_empty(v) => t.families.push(fam), + "target_vendor" if let Some(ven) = check_empty(v) => t.vendors.push(ven), + "target_endian" => { + t.endian = match v { + "little" => Endianness::Little, + "big" => Endianness::Big, + _ => panic!("unknown endian {v}"), + } + } + "target_pointer_width" => { + t.pointer_width = match v { + "16" => PointerWidth::P16, + "32" => PointerWidth::P32, + "64" => PointerWidth::P64, + _ => panic!("unknown pointer width {v}"), + } + } + _ => (), + } + } + + assert_ne!(t.arch, Architecture::Unknown, "arch not found"); + t + } +} + +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +enum Os { + Aix, + Amdhsa, + Android, + Cuda, + Cygwin, + Dragonfly, + Emscripten, + EspIdf, + FreeBsd, + Fuchsia, + Haiku, + HelenOs, + Hermit, + Horizon, + Hurd, + Illumos, + IOs, + L4re, + Linux, + LynxOs178, + MacOs, + Managarm, + Motor, + NetBsd, + Nto, + Nuttx, + OpenBsd, + Psp, + Psx, + Qurt, + Redox, + Rtems, + Solaris, + SolidAsp3, + Teeos, + Trusty, + TvOs, + Uefi, + Unknown, + Vexos, + VisionOs, + Vita, + VxXorks, + Wasi, + WatchOs, + Windows, + Xous, + Zkvm, +} + +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +enum PointerWidth { + P16, + P32, + P64, +} + +/// Run `cargo build` with the provided additional arguments, collecting the list of created +/// libraries. +fn exec_cargo_with_args(target: &str, args: &[&str]) -> Vec { + let mut cmd = Command::new("cargo"); + cmd.args([ + "build", + "--target", + target, + "--message-format=json-diagnostic-rendered-ansi", + ]) + .args(args) + .stdout(Stdio::piped()); + + println!("running: {cmd:?}"); + let mut child = cmd.spawn().expect("failed to launch Cargo"); + + let stdout = child.stdout.take().unwrap(); + let reader = BufReader::new(stdout); + let mut check_files = Vec::new(); + + for line in reader.lines() { + let line = line.expect("failed to read line"); + let j: Value = serde_json::from_str(&line).expect("failed to deserialize"); + let reason = &j["reason"]; + + // Forward output that is meant to be user-facing + if reason == "compiler-message" { + println!("{}", j["message"]["rendered"].as_str().unwrap()); + } else if reason == "build-finished" { + println!("build finshed. success: {}", j["success"]); + } else if reason == "build-script-executed" { + let pretty = serde_json::to_string_pretty(&j).unwrap(); + println!("build script output: {pretty}",); + } + + // Only interested in the artifact list now + if reason != "compiler-artifact" { + continue; + } + + // Find rlibs in the created file list that match our expected library names and + // extensions. + for fpath in j["filenames"].as_array().expect("filenames not an array") { + let path = fpath.as_str().expect("file name not a string"); + let path = PathBuf::from(path); + + if CHECK_EXTENSIONS.contains(&path.extension().map(|ex| ex.to_str().unwrap())) { + let fname = path.file_name().unwrap().to_str().unwrap(); + + if CHECK_LIBRARIES.iter().any(|lib| fname.contains(lib)) { + check_files.push(path); + } + } + } + } + + assert!(child.wait().expect("failed to wait on Cargo").success()); + + assert!(!check_files.is_empty(), "no compiler_builtins rlibs found"); + println!("Collected the following rlibs to check: {check_files:#?}"); + + check_files +} + +/// Information collected from `object`, for convenience. +#[expect(unused)] // only for printing +#[derive(Clone, Debug)] +struct SymInfo { + name: String, + kind: SymbolKind, + scope: SymbolScope, + section: String, + is_undefined: bool, + is_global: bool, + is_local: bool, + is_weak: bool, + is_common: bool, + address: u64, + object: String, +} + +impl SymInfo { + fn new(sym: &Symbol, obj: &ObjFile, obj_path: &str) -> Self { + // Include the section name if possible. Fall back to the `Section` debug impl if not. + let section = sym.section(); + let section_name = sym + .section() + .index() + .and_then(|idx| obj.section_by_index(idx).ok()) + .and_then(|sec| sec.name().ok()) + .map(ToString::to_string) + .unwrap_or_else(|| format!("{section:?}")); + + Self { + name: sym.name().expect("missing name").to_owned(), + kind: sym.kind(), + scope: sym.scope(), + section: section_name, + is_undefined: sym.is_undefined(), + is_global: sym.is_global(), + is_local: sym.is_local(), + is_weak: sym.is_weak(), + is_common: sym.is_common(), + address: sym.address(), + object: obj_path.to_owned(), + } + } +} + +/// Ensure that the same global symbol isn't defined in multiple object files within an archive. +/// +/// Note that this will also locate cases where a symbol is weakly defined in more than one place. +/// Technically there are no linker errors that will come from this, but it keeps our binary more +/// straightforward and saves some distribution size. +fn verify_no_duplicates(archive: &BinFile) { + let mut syms = BTreeMap::::new(); + let mut dups = Vec::new(); + let mut found_any = false; + + archive.for_each_symbol(|symbol, obj, member| { + // Only check defined globals + if !symbol.is_global() || symbol.is_undefined() { + return; + } + + let sym = SymInfo::new(&symbol, obj, member); + + // x86-32 includes multiple copies of thunk symbols + if sym.name.starts_with("__x86.get_pc_thunk") { + return; + } + + // GDB pretty printing symbols may show up more than once but are weak. + if sym.section == ".debug_gdb_scripts" && sym.is_weak { + return; + } + + // Windows has symbols for literal numeric constants, string literals, and MinGW pseudo- + // relocations. These are allowed to have repeated definitions. + let win_allowed_dup_pfx = ["__real@", "__xmm@", "__ymm@", "??_C@_", ".refptr"]; + if win_allowed_dup_pfx + .iter() + .any(|pfx| sym.name.starts_with(pfx)) + { + return; + } + + match syms.get(&sym.name) { + Some(existing) => { + dups.push(sym); + dups.push(existing.clone()); + } + None => { + syms.insert(sym.name.clone(), sym); + } + } + + found_any = true; + }); + + if archive.has_symbol_tables() { + assert!(found_any, "no symbols found"); + } + + if !dups.is_empty() { + let count = dups.iter().map(|x| &x.name).collect::>().len(); + dups.sort_unstable_by(|a, b| a.name.cmp(&b.name)); + panic!("found {count} duplicate symbols: {dups:#?}"); + } + + println!(" success: no duplicate symbols found"); +} + +/// Ensure that there are no references to symbols from `core` that aren't also (somehow) defined. +fn verify_core_symbols(archive: &BinFile) { + // Match both mangling styles: + // + // * `_ZN4core3str8converts9from_utf817hd4454ac14cbbb790E` (old) + // * `_RNvNtNtCscK9O3IwVk7N_4core3str8converts9from_utf8` (v0) + // + // Also account for the Apple leading `_`. + static RE: LazyLock = LazyLock::new(|| Regex::new(r"^_?_[RZ].*4core").unwrap()); + + let mut defined = BTreeSet::new(); + let mut undefined = Vec::new(); + let mut has_symbols = false; + + archive.for_each_symbol(|symbol, obj, member| { + has_symbols = true; + + // Find only symbols from `core` + if !RE.is_match(symbol.name().unwrap()) { + return; + } + + let sym = SymInfo::new(&symbol, obj, member); + if sym.is_undefined { + undefined.push(sym); + } else { + defined.insert(sym.name); + } + }); + + if archive.has_symbol_tables() { + assert!(has_symbols, "no symbols found"); + } + + // Discard any symbols that are defined somewhere in the archive + undefined.retain(|sym| !defined.contains(&sym.name)); + + if !undefined.is_empty() { + undefined.sort_unstable_by(|a, b| a.name.cmp(&b.name)); + panic!( + "found {} undefined symbols from core: {undefined:#?}", + undefined.len() + ); + } + + println!(" success: no undefined references to core found"); +} + +/// Check for symbols with default visibility. +fn verify_hidden_visibility(archive: &BinFile) { + let mut visible = Vec::new(); + let mut found_any = false; + + archive.for_each_symbol(|symbol, obj, member| { + // Only check defined globals. + if !symbol.is_global() || symbol.is_undefined() { + return; + } + + let sym = SymInfo::new(&symbol, obj, member); + if sym.scope == SymbolScope::Dynamic { + visible.push(sym); + } + + found_any = true + }); + + if archive.has_symbol_tables() { + assert!(found_any, "no symbols found"); + } + + if !visible.is_empty() { + visible.sort_unstable_by(|a, b| a.name.cmp(&b.name)); + let num = visible.len(); + panic!("found {num:#?} visible symbols: {visible:#?}"); + } + + println!(" success: no visible symbols found"); +} + +/// Check that all object files are actually for the target architecture and, if provided, +/// for the target operating system. +fn verify_expected_target(target: &Target, archive: &BinFile) { + let mut mismatched = Vec::new(); + + archive.for_each_object(|obj, obj_path| { + let mut mismatch = |field: &str, a: &dyn fmt::Debug, b: &dyn fmt::Debug| { + let msg = format!("mismatched {field} {a:?} != {b:?}"); + mismatched.push((obj_path.to_owned(), msg)); + }; + + if obj.architecture() != target.arch { + mismatch("arch", &obj.architecture(), &target.arch); + } + if obj.sub_architecture() != target.subarch { + mismatch("subarch", &obj.sub_architecture(), &target.subarch); + } + if obj.endianness() != target.endian { + mismatch("endian", &obj.sub_architecture(), &target.endian); + } + + let obj_os = match &obj { + ObjFile::Elf32(f) => elf_os(f), + ObjFile::Elf64(f) => elf_os(f), + + ObjFile::MachO32(f) => mach_os(f), + ObjFile::MachO64(f) => mach_os(f), + + // The non-executable header doesn't store OS + ObjFile::Coff(_) => Os::Windows, + ObjFile::CoffBig(_) => Os::Windows, + ObjFile::Pe32(f) => pe_os(f), + ObjFile::Pe64(f) => pe_os(f), + + // Wasm files don't seem to have metadata (at least in `object`) + ObjFile::Wasm(_) => Os::Unknown, + + // Out of supported platforms, this is only used by AIX + ObjFile::Xcoff32(_) => Os::Aix, + ObjFile::Xcoff64(_) => Os::Aix, + + _ => { + unimplemented!( + "os check for binary format {:?} is not yet supported", + obj.format() + ) + } + }; + + if !(obj_os == target.os + || obj_os == Os::Unknown + // Cygwin and Windows object files look the same + || (obj_os == Os::Windows && target.os == Os::Cygwin)) + { + mismatch("OS", &obj_os, &target.os); + } + }); + + for (file, msg) in &mismatched { + eprintln!("in `{file}`: {msg}"); + } + + assert!( + mismatched.is_empty(), + "some object files do not match the intended target" + ); + println!(" success: object files match target"); +} + +/* Note that we only match OS tags that have been tested. There are others for other platforms + * that Rust supports but aren't as easy to test, they can be added as needed. */ + +/// Get the OS from an elf file, or `Unknown` if not specified. +fn elf_os(f: &read::elf::ElfFile) -> Os { + let os_abi = f.elf_header().e_ident().os_abi; + match os_abi { + elf::ELFOSABI_NONE => Os::Unknown, + elf::ELFOSABI_FREEBSD => Os::FreeBsd, + elf::ELFOSABI_SOLARIS => Os::Solaris, + // In practice, these seem not to be specified and instead match ELFOSABI_NONE. + elf::ELFOSABI_HURD => Os::Hurd, + elf::ELFOSABI_LINUX => Os::Linux, + elf::ELFOSABI_NETBSD => Os::NetBsd, + elf::ELFOSABI_OPENBSD => Os::OpenBsd, + _ => panic!("unrecognized ELF os_abi {os_abi}"), + } +} + +/// Get the OS from a mach file, or `Unknown` if not specified. +fn mach_os(f: &read::macho::MachOFile) -> Os { + // Note that this only returns something on `.rmeta` objects, not `.o`s. + let Ok(Some((build_cmd, build_tool))) = f.build_version() else { + return Os::Unknown; + }; + let platform = build_cmd.platform.get(f.endian()); + + match platform { + macho::PLATFORM_UNKNOWN => Os::Unknown, + macho::PLATFORM_MACOS => Os::MacOs, + macho::PLATFORM_IOS | macho::PLATFORM_IOSSIMULATOR | macho::PLATFORM_MACCATALYST => Os::IOs, + macho::PLATFORM_TVOS | macho::PLATFORM_TVOSSIMULATOR => Os::TvOs, + macho::PLATFORM_VISIONOS | macho::PLATFORM_VISIONOSSIMULATOR => Os::VisionOs, + macho::PLATFORM_WATCHOS | macho::PLATFORM_WATCHOSSIMULATOR => Os::WatchOs, + _ => panic!("unrecognized Mach-O platform {platform} ({build_cmd:?} {build_tool:?})"), + } +} + +/// Get the OS from a PE file, or `Unknown` if not specified. +fn pe_os(f: &read::pe::PeFile) -> Os { + let opt_hdr = f.nt_headers().optional_header(); + let sub = opt_hdr.subsystem(); + match sub { + pe::IMAGE_SUBSYSTEM_WINDOWS_CUI | pe::IMAGE_SUBSYSTEM_WINDOWS_GUI => Os::Windows, + _ => panic!("unrecognized PE subsystem {sub}, {opt_hdr:?}"), + } +} + +/// Reasons a binary is considered to have an executable stack. +enum ExeStack { + MissingGnuStackSec, + ExeGnuStackSec, + ExePtGnuStack, +} + +/// Ensure that the object/archive will not require an executable stack. +fn verify_no_exec_stack(archive: &BinFile, no_os_target: bool) { + if no_os_target { + // We don't really have a good way of knowing whether or not an elf file is for a + // no-os environment so we rely on a CLI arg (note.GNU-stack doesn't get emitted if + // there is no OS to protect the stack). + println!(" skipping check for writeable+executable stack on no-os target"); + return; + } + + let mut problem_objfiles = Vec::new(); + + archive.for_each_object(|obj, obj_path| match check_obj_exe_stack(&obj) { + Ok(()) => (), + Err(exe) => problem_objfiles.push((obj_path.to_owned(), exe)), + }); + + if problem_objfiles.is_empty() { + println!(" success: no writeable+executable stack indicators found"); + return; + } + + eprintln!("the following object files require an executable stack:"); + + for (obj, exe) in problem_objfiles { + let reason = match exe { + ExeStack::MissingGnuStackSec => "no .note.GNU-stack section", + ExeStack::ExeGnuStackSec => ".note.GNU-stack section marked SHF_EXECINSTR", + ExeStack::ExePtGnuStack => "PT_GNU_STACK program header marked PF_X", + }; + eprintln!(" {obj} ({reason})"); + } + + exit(1); +} + +/// `Err` if the section/flag combination indicates that the object file should be linked with an +/// executable stack. +fn check_obj_exe_stack(obj: &ObjFile) -> Result<(), ExeStack> { + match obj.format() { + BinaryFormat::Elf => check_elf_exe_stack(obj), + // Technically has the `MH_ALLOW_STACK_EXECUTION` flag but I can't get the compiler to + // emit it (`-allow_stack_execute` doesn't seem to work in recent versions). + BinaryFormat::MachO => Ok(()), + // Can't find much information about Windows stack executability. + BinaryFormat::Coff | BinaryFormat::Pe => Ok(()), + // Also not sure about wasm. + BinaryFormat::Wasm => Ok(()), + BinaryFormat::Xcoff | _ => { + unimplemented!("binary format {:?} is not supported", obj.format()) + } + } +} + +/// Check for an executable stack in elf binaries. +/// +/// If the `PT_GNU_STACK` header on a binary is present and marked executable, the binary will +/// have an executable stack (RWE rather than the desired RW). If any object file has the right +/// `.note.GNU-stack` logic, the final binary will get `PT_GNU_STACK`. +/// +/// Individual object file logic is as follows, paraphrased from [1]: +/// +/// - A `.note.GNU-stack` section with the exe flag means this needs an executable stack +/// - A `.note.GNU-stack` section without the exe flag means there is no executable stack needed +/// - Without the section, behavior is target-specific. Historically it usually means an executable +/// stack is required. +/// +/// Per [2], it is now deprecated behavior for a missing `.note.GNU-stack` section to imply an +/// executable stack. However, we shouldn't assume that tooling has caught up to this. +/// +/// [1]: https://www.man7.org/linux/man-pages/man1/ld.1.html +/// [2]: https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=0d38576a34ec64a1b4500c9277a8e9d0f07e6774> +fn check_elf_exe_stack(obj: &ObjFile) -> Result<(), ExeStack> { + let end = obj.endianness(); + + // Check for PT_GNU_STACK marked executable + let mut is_obj_exe = false; + let mut found_gnu_stack = false; + let mut check_ph = |p_type: U32, + p_flags: U32| { + let ty = p_type.get(end); + let flags = p_flags.get(end); + + // Presence of PT_INTERP indicates that this is an executable rather than a standalone + // object file. + if ty == elf::PT_INTERP { + is_obj_exe = true; + } + + if ty == elf::PT_GNU_STACK { + assert!(!found_gnu_stack, "multiple PT_GNU_STACK sections"); + found_gnu_stack = true; + if flags.contains(elf::PF_X) { + return Err(ExeStack::ExePtGnuStack); + } + } + + Ok(()) + }; + + match obj { + ObjFile::Elf32(f) => { + for ph in f.elf_program_headers() { + check_ph(ph.p_type, ph.p_flags)?; + } + } + ObjFile::Elf64(f) => { + for ph in f.elf_program_headers() { + check_ph(ph.p_type, ph.p_flags)?; + } + } + _ => panic!("should only be called with elf objects"), + } + + if is_obj_exe { + return Ok(()); + } + + // The remaining are checks for individual object files, which wind up controlling PT_GNU_STACK + // in the final binary. + let mut gnu_stack_exe = None; + let mut has_exe_sections = false; + for sec in obj.sections() { + let SectionFlags::Elf { + sh_type: _, + sh_flags, + } = sec.flags() + else { + unreachable!("only elf files are being checked"); + }; + + let is_sec_exe = sh_flags.contains(elf::SHF_EXECINSTR); + + // If the magic section is present, its exe bit tells us whether or not the object + // file requires an executable stack. + if sec.name().unwrap_or_default() == GNU_STACK { + assert!(gnu_stack_exe.is_none(), "multiple {GNU_STACK} sections"); + if is_sec_exe { + gnu_stack_exe = Some(Err(ExeStack::ExeGnuStackSec)); + } else { + gnu_stack_exe = Some(Ok(())); + } + } + + // Otherwise, just keep track of whether or not we have exeuctable sections + has_exe_sections |= is_sec_exe; + } + + // GNU_STACK sets the executability if specified. + if let Some(exe) = gnu_stack_exe { + return exe; + } + + // Ignore object files that have no executable sections, like rmeta. + if !has_exe_sections { + return Ok(()); + } + + let FileFlags::Elf { e_flags, .. } = obj.flags() else { + unreachable!("only elf files are being checked"); + }; + + // If there is no `.note.GNU-stack` and no executable sections, behavior differs by platform. + match obj.architecture() { + // PPC64 doesn't set `.note.GNU-stack` since GNU nested functions don't need a trampoline, + // . This only applies to ELFv1. + Architecture::PowerPc64 if e_flags.0 & elf::EF_PPC64_ABI != 2 => Ok(()), + + _ => Err(ExeStack::MissingGnuStackSec), + } +} + +/// Thin wrapper for owning data used by `object`. +struct BinFile { + path: PathBuf, + data: Vec, +} + +impl BinFile { + fn from_path(path: &Path) -> Self { + Self { + path: path.to_owned(), + data: fs::read(path).expect("reading file failed"), + } + } + + fn as_archive_file(&self) -> ObjResult> { + ArchiveFile::parse(self.data.as_slice()) + } + + fn as_obj_file(&self) -> ObjResult> { + ObjFile::parse(self.data.as_slice()) + } + + /// For a given archive, do something with each object file. For an object file, do + /// something once. + fn for_each_object(&self, mut f: impl FnMut(ObjFile, &str)) { + // Try as an archive first. + let as_archive = self.as_archive_file(); + if let Ok(archive) = as_archive { + for member in archive.members() { + let member = member.expect("failed to access member"); + let obj_data = member + .data(self.data.as_slice()) + .expect("failed to access object"); + let obj = ObjFile::parse(obj_data).expect("failed to parse object"); + f(obj, &String::from_utf8_lossy(member.name())); + } + + return; + } + + // Fall back to parsing as an object file. + let as_obj = self.as_obj_file(); + if let Ok(obj) = as_obj { + f(obj, &self.path.to_string_lossy()); + return; + } + + panic!( + "failed to parse as either archive or object file: {:?}, {:?}", + as_archive.unwrap_err(), + as_obj.unwrap_err(), + ); + } + + /// D something with each symbol in an archive or object file. + fn for_each_symbol(&self, mut f: impl FnMut(Symbol, &ObjFile, &str)) { + self.for_each_object(|obj, obj_path| { + obj.symbols().for_each(|sym| f(sym, &obj, obj_path)); + }); + } + + /// PE executable files don't have the same kind of symbol tables. This isn't a perfectly + /// accurate check, but at least tells us whether we can skip erroring if we don't find any + /// symbols. + fn has_symbol_tables(&self) -> bool { + let mut empty = true; + let mut ret = false; + + self.for_each_object(|obj, _obj_path| { + if !matches!(obj.format(), BinaryFormat::Pe) { + // Any non-PE objects should have symbol tables. + ret = true; + } + empty = false; + }); + + // If empty, assume there should be tables. + empty || ret + } +} diff --git a/library/compiler-builtins/crates/symcheck/tests/all.rs b/library/compiler-builtins/crates/symcheck/tests/all.rs new file mode 100644 index 0000000000000..ce7d09798dc65 --- /dev/null +++ b/library/compiler-builtins/crates/symcheck/tests/all.rs @@ -0,0 +1,389 @@ +use std::ffi::OsString; +use std::path::{Path, PathBuf}; +use std::process::{Command, Stdio}; +use std::{env, str}; + +use assert_cmd::assert::Assert; +use assert_cmd::cargo::cargo_bin_cmd; +use object::BinaryFormat; +use tempfile::tempdir; + +trait AssertExt { + fn stderr_contains(self, s: &str) -> Self; +} + +impl AssertExt for Assert { + #[track_caller] + fn stderr_contains(self, s: &str) -> Self { + let out = String::from_utf8_lossy(&self.get_output().stderr); + assert!(out.contains(s), "looking for: `{s}`\nout:\n```\n{out}\n```"); + self + } +} + +#[test] +fn test_duplicates() { + let t = TestTarget::from_env(); + let dir = tempdir().unwrap(); + let dup_out = dir.path().join("dup.o"); + let lib_out = dir.path().join("libfoo.rlib"); + + // For the "bad" file, we need duplicate symbols from different object files in the archive. Do + // this reliably by building an archive and a separate object file then merging them. + t.rustc_build(&input_dir().join("duplicates.rs"), &lib_out, |cmd| cmd); + t.rustc_build(&input_dir().join("duplicates.rs"), &dup_out, |cmd| { + cmd.arg("--emit=obj") + }); + + let mut ar = t.cc_build().get_archiver(); + + if ar.get_program().to_string_lossy().contains("lib.exe") { + let mut out_arg = OsString::from("-out:"); + out_arg.push(&lib_out); + ar.arg(&out_arg); + // Repeating the same file as the first arg makes lib.exe append (taken from the + // `cc` implementation). + ar.arg(&lib_out); + } else { + ar.arg("rs") + // Eat an `libfoo.rlib(lib.rmeta) has no symbols` info message on MacOS + .stderr(Stdio::null()) + .arg(&lib_out); + } + + run(ar.arg(&dup_out)); + + let assert = t.symcheck_exe().arg(&lib_out).assert(); + assert + .failure() + .stderr_contains("duplicate symbols") + .stderr_contains("FDUP") + .stderr_contains("IDUP") + .stderr_contains("fndup"); +} + +#[test] +fn test_core_symbols() { + let t = TestTarget::from_env(); + let dir = tempdir().unwrap(); + let lib_out = dir.path().join("libfoo.rlib"); + t.rustc_build(&input_dir().join("core_symbols.rs"), &lib_out, |cmd| cmd); + let assert = t.symcheck_exe().arg(&lib_out).assert(); + assert + .failure() + .stderr_contains("found 1 undefined symbols from core") + .stderr_contains("from_utf8"); +} + +#[test] +fn test_visible_symbols() { + let t = TestTarget::from_env(); + if t.is_windows() { + eprintln!("windows does not have visibility, skipping"); + return; + } + let dir = tempdir().unwrap(); + let lib_out = dir.path().join("libfoo.rlib"); + t.rustc_build(&input_dir().join("good_lib.rs"), &lib_out, |cmd| cmd); + let assert = t.symcheck_exe().arg(&lib_out).assert(); + assert.failure().stderr_contains("found 1 visible symbols"); // good is visible. +} + +#[test] +fn test_target_mismatch() { + // Build with the target we know we have a toolchain for, but check against something else. + let t_build = TestTarget::from_env(); + let t_check = if t_build.triple.starts_with("x86_64") { + TestTarget { + triple: "aarch64-unknown-linux-gnu".to_string(), + } + } else { + TestTarget { + triple: "x86_64-unknown-linux-gnu".to_string(), + } + }; + + let dir = tempdir().unwrap(); + let lib_out = dir.path().join("libfoo.rlib"); + t_build.rustc_build(&input_dir().join("good_lib.rs"), &lib_out, |cmd| cmd); + + let assert = t_check.symcheck_exe().arg(&lib_out).assert(); + assert + .failure() + .stderr_contains("some object files do not match the intended target"); + + // Try with C as well since some checks rely on rmeta archive members (Mach-O `build_version`). + let objs = t_build + .cc_build() + .file(input_dir().join("good_lib.c")) + .out_dir(&dir) + .compile_intermediates(); + let [c_obj] = objs.as_slice() else { panic!() }; + + let assert = t_check.symcheck_exe().arg(c_obj).assert(); + assert + .failure() + .stderr_contains("some object files do not match the intended target"); +} + +mod exe_stack { + use super::*; + + /// Check with an object that has no `.note.GNU-stack` section, indicating platform-default stack + /// writeability (usually enabled). + #[test] + fn test_missing_gnu_stack_section() { + let t = TestTarget::from_env(); + if t.is_msvc() { + // Can't easily build asm via cc with cl.exe / masm.exe + eprintln!("assembly on windows, skipping"); + return; + } + + let dir = tempdir().unwrap(); + let src = input_dir().join("missing_gnu_stack_section.S"); + + let objs = t.cc_build().file(src).out_dir(&dir).compile_intermediates(); + let [obj] = objs.as_slice() else { panic!() }; + + let assert = t.symcheck_exe().arg(obj).arg("--no-visibility").assert(); + + if t.is_ppc64_elfv1() || t.no_os() || t.binary_obj_format() != BinaryFormat::Elf { + // Ppc64be ELFv1 doesn't emit `.note.GNU-stack`, not relevant without an OS, and non-elf + // targets don't use `.note.GNU-stack`. + assert.success(); + return; + } + + assert + .failure() + .stderr_contains("the following object files require an executable stack") + .stderr_contains("missing_gnu_stack_section.o (no .note.GNU-stack section)"); + } + + /// Check with an object that has a `.note.GNU-stack` section with the executable flag set. + #[test] + fn test_exe_gnu_stack_section() { + let t = TestTarget::from_env(); + let mut build = t.cc_build(); + if !build.get_compiler().is_like_gnu() || t.is_windows() { + eprintln!("unsupported compiler for nested functions, skipping"); + return; + } + + let dir = tempdir().unwrap(); + let objs = build + .file(input_dir().join("has_exe_gnu_stack_section.c")) + .out_dir(&dir) + .compile_intermediates(); + let [obj] = objs.as_slice() else { panic!() }; + + let assert = t.symcheck_exe().arg(obj).arg("--no-visibility").assert(); + + if t.is_ppc64_elfv1() || t.no_os() { + // Ppc64be ELFv1 doesn't emit `.note.GNU-stack`, not relevant without an OS. + assert.success(); + return; + } + + assert + .failure() + .stderr_contains("the following object files require an executable stack") + .stderr_contains( + "has_exe_gnu_stack_section.o (.note.GNU-stack section marked SHF_EXECINSTR)", + ); + } + + /// Check a final binary with `PT_GNU_STACK`. + #[test] + fn test_execstack_bin() { + let t = TestTarget::from_env(); + if t.binary_obj_format() != BinaryFormat::Elf || !t.supports_executables() { + // Mac's Clang rejects `-z execstack`. `-allow_stack_execute` should work per the ld + // manpage, at least on x86, but it doesn't seem to., not relevant without an OS. + eprintln!("non-elf or no-executable target, skipping"); + return; + } + + let dir = tempdir().unwrap(); + let out = dir.path().join("execstack.out"); + + let mut cmd = t.cc_build().get_compiler().to_command(); + t.set_bin_out_path(&mut cmd, &out); + + run(cmd + .arg("-z") + .arg("execstack") + .arg(input_dir().join("good_bin.c"))); + + let assert = t.symcheck_exe().arg(&out).assert(); + assert + .failure() + .stderr_contains("the following object files require an executable stack") + .stderr_contains("execstack.out (PT_GNU_STACK program header marked PF_X)"); + } +} + +#[test] +fn test_good_lib() { + let t = TestTarget::from_env(); + let dir = tempdir().unwrap(); + let lib_out = dir.path().join("libfoo.rlib"); + t.rustc_build(&input_dir().join("good_lib.rs"), &lib_out, |cmd| cmd); + let assert = t + .symcheck_exe() + .arg(&lib_out) + .arg("--no-visibility") + .assert(); + assert.success(); +} + +#[test] +fn test_good_bin() { + let t = TestTarget::from_env(); + // Nothing to test if we can't build a binary. + if !t.supports_executables() { + eprintln!("no-exe target, skipping"); + return; + } + + let dir = tempdir().unwrap(); + let out = dir.path().join("good_bin.out"); + + let mut cmd = t.cc_build().get_compiler().to_command(); + t.set_bin_out_path(&mut cmd, &out); + run(cmd.arg(input_dir().join("good_bin.c"))); + + let assert = t.symcheck_exe().arg(&out).arg("--no-visibility").assert(); + assert.success(); +} + +/// Since symcheck is a hostprog, the target we want to build and test symcheck for may not be the +/// same as the host target. +struct TestTarget { + triple: String, +} + +impl TestTarget { + fn from_env() -> Self { + let triple = match env::var("SYMCHECK_TEST_TARGET") { + Ok(t) => t, + // Require on CI so we don't accidentally always test the native target + _ if env::var("CI").is_ok() => panic!("SYMCHECK_TEST_TARGET must be set in CI"), + // Fall back to native for local convenience. + Err(_) => env!("HOST").to_string(), + }; + + println!("using target {triple}"); + Self { triple } + } + + /// Build i -> o with optional additional configuration. + fn rustc_build(&self, i: &Path, o: &Path, mut f: impl FnMut(&mut Command) -> &mut Command) { + let mut cmd = Command::new("rustc"); + cmd.arg(i) + .arg("--target") + .arg(&self.triple) + .arg("--crate-type=lib") + .arg("-o") + .arg(o); + f(&mut cmd); + run(&mut cmd); + } + + /// Configure `cc` with the host and target. + fn cc_build(&self) -> cc::Build { + let mut b = cc::Build::new(); + b.host(env!("HOST")) + .target(&self.triple) + .opt_level(0) + .cargo_debug(true) + .cargo_metadata(false); + b + } + + fn symcheck_exe(&self) -> assert_cmd::Command { + let mut cmd = cargo_bin_cmd!(); + cmd.arg("--check").arg("--target").arg(&self.triple); + if self.no_os() { + cmd.arg("--no-os"); + } + cmd + } + + /// MSVC requires different flags for setting output path, account for that here. + fn set_bin_out_path<'a>(&self, cmd: &'a mut Command, out: &Path) -> &'a mut Command { + if self.cc_build().get_compiler().is_like_msvc() { + let mut exe_arg = OsString::from("/Fe"); + let mut obj_arg = OsString::from("/Fo"); + exe_arg.push(out); + obj_arg.push(out.with_extension("o")); + cmd.arg(exe_arg).arg(obj_arg) + } else { + cmd.arg("-o").arg(out) + } + } + + /// Based on `rustc_target`. + fn binary_obj_format(&self) -> BinaryFormat { + let t = &self.triple; + if t.contains("-windows-") || t.contains("-cygwin") { + // Coff for libraries, PE for executables. + BinaryFormat::Coff + } else if t.starts_with("wasm") { + BinaryFormat::Wasm + } else if t.contains("-aix") { + BinaryFormat::Xcoff + } else if t.contains("-apple-") { + BinaryFormat::MachO + } else { + BinaryFormat::Elf + } + } + + fn is_windows(&self) -> bool { + self.triple.contains("-windows-") + } + + fn is_msvc(&self) -> bool { + self.triple.contains("-windows-msvc") + } + + fn is_ppc64_elfv1(&self) -> bool { + let output = Command::new("rustc") + .arg("--target") + .arg(&self.triple) + .arg("--print=cfg") + .output() + .unwrap(); + assert!(output.status.success()); + let stdout = str::from_utf8(&output.stdout).unwrap(); + self.triple.starts_with("powerpc64") && stdout.contains(r#"target_abi="elfv1""#) + } + + /// True if the target needs `--no-os` passed to symcheck. + fn no_os(&self) -> bool { + self.triple.contains("-none") + } + + /// True if the target supports (easily) building to a final executable. + fn supports_executables(&self) -> bool { + // Technically i686-pc-windows-gnu should work but it has nontrivial setup in CI. + !(self.no_os() + || self.triple == "wasm32-unknown-unknown" + || self.triple == "i686-pc-windows-gnu") + } +} + +fn input_dir() -> PathBuf { + Path::new(env!("CARGO_MANIFEST_DIR")).join("tests/input") +} + +#[track_caller] +fn run(cmd: &mut Command) { + eprintln!("+ {cmd:?}"); + let out = cmd.output().unwrap(); + println!("{}", String::from_utf8_lossy(&out.stdout)); + eprintln!("{}", String::from_utf8_lossy(&out.stderr)); + assert!(out.status.success(), "{:?}", out.status); +} diff --git a/library/compiler-builtins/crates/symcheck/tests/input/core_symbols.rs b/library/compiler-builtins/crates/symcheck/tests/input/core_symbols.rs new file mode 100644 index 0000000000000..cf74f97796612 --- /dev/null +++ b/library/compiler-builtins/crates/symcheck/tests/input/core_symbols.rs @@ -0,0 +1,11 @@ +//! Ensure we catch calls to `core`. + +#![no_std] + +#[unsafe(no_mangle)] +pub fn call_from_core(s: &[u8]) -> &str { + match core::str::from_utf8(&s) { + Ok(s) => s, + Err(_) => "", + } +} diff --git a/library/compiler-builtins/crates/symcheck/tests/input/duplicates.rs b/library/compiler-builtins/crates/symcheck/tests/input/duplicates.rs new file mode 100644 index 0000000000000..92623a0b2e1a5 --- /dev/null +++ b/library/compiler-builtins/crates/symcheck/tests/input/duplicates.rs @@ -0,0 +1,12 @@ +//! Ensure we catch duplicate symbols (the duplicates are in the aux file). Gets built twice +//! as separate object files. + +#![no_std] + +#[unsafe(no_mangle)] +static IDUP: i32 = 0; +#[unsafe(no_mangle)] +static FDUP: f32 = 0.0; + +#[unsafe(no_mangle)] +pub fn fndup() {} diff --git a/library/compiler-builtins/crates/symcheck/tests/input/good_bin.c b/library/compiler-builtins/crates/symcheck/tests/input/good_bin.c new file mode 100644 index 0000000000000..dba75b58af1a1 --- /dev/null +++ b/library/compiler-builtins/crates/symcheck/tests/input/good_bin.c @@ -0,0 +1,3 @@ +/* empty main used to test binaries with compiler options */ + +int main() {} diff --git a/library/compiler-builtins/crates/symcheck/tests/input/good_lib.c b/library/compiler-builtins/crates/symcheck/tests/input/good_lib.c new file mode 100644 index 0000000000000..0b7e431cb90f2 --- /dev/null +++ b/library/compiler-builtins/crates/symcheck/tests/input/good_lib.c @@ -0,0 +1 @@ +void good() {} diff --git a/library/compiler-builtins/crates/symcheck/tests/input/good_lib.rs b/library/compiler-builtins/crates/symcheck/tests/input/good_lib.rs new file mode 100644 index 0000000000000..6679ee1dd30cf --- /dev/null +++ b/library/compiler-builtins/crates/symcheck/tests/input/good_lib.rs @@ -0,0 +1,4 @@ +#![no_std] + +#[unsafe(no_mangle)] +pub fn good() {} diff --git a/library/compiler-builtins/crates/symcheck/tests/input/has_exe_gnu_stack_section.c b/library/compiler-builtins/crates/symcheck/tests/input/has_exe_gnu_stack_section.c new file mode 100644 index 0000000000000..d4be217b5a06c --- /dev/null +++ b/library/compiler-builtins/crates/symcheck/tests/input/has_exe_gnu_stack_section.c @@ -0,0 +1,16 @@ +/* A file that requires an executable stack and thus will have a + * `.note.GNU-stack` section with the executable bit set. + * + * GNU nested functions are the only way I could find to force an explicitly + * executable stack. Supported by GCC only, not Clang. + */ + +void intermediate(void (*)(int, int), int); + +void hack(int *array, int size) { + void store (int index, int value) { + array[index] = value; + } + + intermediate(store, size); +} diff --git a/library/compiler-builtins/crates/symcheck/tests/input/missing_gnu_stack_section.S b/library/compiler-builtins/crates/symcheck/tests/input/missing_gnu_stack_section.S new file mode 100644 index 0000000000000..99ac3ba51c47d --- /dev/null +++ b/library/compiler-builtins/crates/symcheck/tests/input/missing_gnu_stack_section.S @@ -0,0 +1,25 @@ +/* Create an object file with no `.note.GNU-stack` section. + * + * Assembly files do not get that section, meaning platform-default stack + * executability is implied (usually yes on Linux). + */ + +/* Unless we set the ABI version, we have no way to differentiate between + big-endian ppc64 ELFv1 or ELFv2 since e_flags is otherwise unspecified */ +#if defined(__powerpc64__) && _CALL_ELF == 2 +.abiversion 2 +#endif + +.global func + +#ifdef __wasm__ +.functype func () -> () +.type func, @function +#endif + +func: + nop + +#ifdef __wasm__ + end_function +#endif diff --git a/library/compiler-builtins/crates/update-api-list/Cargo.toml b/library/compiler-builtins/crates/update-api-list/Cargo.toml new file mode 100644 index 0000000000000..7a14a0e9770f5 --- /dev/null +++ b/library/compiler-builtins/crates/update-api-list/Cargo.toml @@ -0,0 +1,13 @@ +[package] +name = "update-api-list" +version = "0.1.0" +edition = "2024" +publish = false +license = "MIT OR Apache-2.0" + +[dependencies] +api-list-common.workspace = true +getopts.workspace = true +glob.workspace = true +pretty_assertions.workspace = true +regex.workspace = true diff --git a/library/compiler-builtins/crates/update-api-list/src/lib.rs b/library/compiler-builtins/crates/update-api-list/src/lib.rs new file mode 100644 index 0000000000000..a07ae3411ee37 --- /dev/null +++ b/library/compiler-builtins/crates/update-api-list/src/lib.rs @@ -0,0 +1,11 @@ +use std::path::{Path, PathBuf}; +use std::sync::LazyLock; + +pub static WORKSPACE_ROOT: LazyLock = LazyLock::new(|| { + Path::new(env!("CARGO_MANIFEST_DIR")) + .parent() + .unwrap() + .parent() + .unwrap() + .to_owned() +}); diff --git a/library/compiler-builtins/crates/update-api-list/tests/all.rs b/library/compiler-builtins/crates/update-api-list/tests/all.rs new file mode 100644 index 0000000000000..814c7cc3fa0ca --- /dev/null +++ b/library/compiler-builtins/crates/update-api-list/tests/all.rs @@ -0,0 +1,128 @@ +use std::fs; +use std::path::Path; +use std::process::Command; +use std::sync::LazyLock; + +use pretty_assertions::assert_str_eq; +use regex::Regex; +use update_api_list::WORKSPACE_ROOT; + +static PUBLIC_FUNCTIONS: LazyLock> = LazyLock::new(|| { + fs::read_to_string(WORKSPACE_ROOT.join("etc/function-list.txt")) + .unwrap() + .lines() + .map(|line| line.trim()) + .filter(|line| !(line.starts_with("#") || line.is_empty())) + .map(|line| line.to_owned()) + .collect() +}); + +/// In each file, check annotations indicating that blocks of code should be sorted or should +/// include an exhaustive list of all public API. +#[test] +fn tidy_lists() { + let out = Command::new("git") + .arg("ls-files") + .current_dir(&*WORKSPACE_ROOT) + .output() + .unwrap(); + assert!(out.status.success()); + + let file_list = str::from_utf8(&out.stdout).unwrap(); + + for path in file_list.lines() { + let relpath = Path::new(path); + let abspath = WORKSPACE_ROOT.join(relpath); + if abspath.is_dir() || relpath == file!() { + continue; + } + + let src = fs::read_to_string(&abspath).unwrap(); + let lines: Vec<_> = src.lines().collect(); + + validate_delimited_block( + relpath, + &lines, + "verify-sorted-start", + "verify-sorted-end", + ensure_sorted, + ); + + validate_delimited_block( + relpath, + &lines, + "verify-apilist-start", + "verify-apilist-end", + ensure_contains_api, + ); + } +} + +/// Identify blocks of code wrapped within `start` and `end`, collect their contents to a list of +/// strings, and call `validate` for each of those lists. +fn validate_delimited_block( + relpath: &Path, + lines: &[&str], + start: &str, + end: &str, + validate: impl Fn(&Path, usize, &[&str]), +) { + let mut block_lines = Vec::new(); + let mut block_start_line = None; + for (mut line_num, line) in lines.iter().enumerate() { + line_num += 1; + + if line.contains(start) { + block_start_line = Some(line_num); + continue; + } + + // End of a block, validate its contents + if line.contains(end) { + let Some(start_line) = block_start_line else { + panic!("`{end}` without `{start}` at {relpath:?}:{line_num}"); + }; + + validate(relpath, start_line, &block_lines); + block_lines.clear(); + block_start_line = None; + continue; + } + + if block_start_line.is_some() { + block_lines.push(*line); + } + } + + if let Some(start_line) = block_start_line { + panic!("`{start}` without `{end}` at {relpath:?}:{start_line}"); + } +} + +/// Given a list of strings, ensure that each public function we have is named somewhere. +fn ensure_contains_api(relpath: &Path, block_start_line: usize, lines: &[&str]) { + let mut not_found = Vec::new(); + + for func in &*PUBLIC_FUNCTIONS { + // The function name may be on its own or somewhere in a snake case string. + let re = Regex::new(&format!(r"(\b|_){func}(\b|_)")).unwrap(); + if !lines.iter().any(|line| re.is_match(line)) { + not_found.push(func); + } + } + + if not_found.is_empty() { + return; + } + + panic!("functions not found at {relpath:?}:{block_start_line}: {not_found:?}"); +} + +fn ensure_sorted(relpath: &Path, block_start_line: usize, lines: &[&str]) { + let mut sorted = lines.to_owned(); + sorted.sort_unstable(); + let a = lines.join("\n"); + let b = sorted.join("\n"); + + assert_str_eq!(a, b, "sorted block at {relpath:?}:{block_start_line}"); +} diff --git a/library/compiler-builtins/crates/util/Cargo.toml b/library/compiler-builtins/crates/util/Cargo.toml index 614c54bd83557..c56e2cc12ea58 100644 --- a/library/compiler-builtins/crates/util/Cargo.toml +++ b/library/compiler-builtins/crates/util/Cargo.toml @@ -5,15 +5,15 @@ edition = "2024" publish = false license = "MIT OR Apache-2.0" +[dependencies] +libm.workspace = true +libm-macros.workspace = true +libm-test.workspace = true +musl-math-sys = { workspace = true, optional = true } +rug = { workspace = true, optional = true } + [features] default = ["build-musl", "build-mpfr", "unstable-float"] build-musl = ["libm-test/build-musl", "dep:musl-math-sys"] build-mpfr = ["libm-test/build-mpfr", "dep:rug"] unstable-float = ["libm/unstable-float", "libm-test/unstable-float", "rug?/nightly-float"] - -[dependencies] -libm = { path = "../../libm", default-features = false } -libm-macros = { path = "../libm-macros" } -libm-test = { path = "../../libm-test", default-features = false } -musl-math-sys = { path = "../musl-math-sys", optional = true } -rug = { version = "1.27.0", optional = true, default-features = false, features = ["float", "std"] } diff --git a/library/compiler-builtins/crates/util/build.rs b/library/compiler-builtins/crates/util/build.rs index a1be4127527ae..f7ed72addee10 100644 --- a/library/compiler-builtins/crates/util/build.rs +++ b/library/compiler-builtins/crates/util/build.rs @@ -1,10 +1,10 @@ -#![allow(unexpected_cfgs)] - #[path = "../../libm/configure.rs"] mod configure; +use configure::{Config, Library}; + fn main() { println!("cargo:rerun-if-changed=../../libm/configure.rs"); - let cfg = configure::Config::from_env(); - configure::emit_libm_config(&cfg); + let cfg = Config::from_env(Library::Util); + configure::emit(&cfg); } diff --git a/library/compiler-builtins/crates/util/src/main.rs b/library/compiler-builtins/crates/util/src/main.rs index 5972181531b26..aa79354a57159 100644 --- a/library/compiler-builtins/crates/util/src/main.rs +++ b/library/compiler-builtins/crates/util/src/main.rs @@ -8,10 +8,10 @@ use std::env; use std::num::ParseIntError; use std::str::FromStr; -use libm::support::{Hexf, hf32, hf64}; +use libm::support::{Float, Hex, hf32, hf64}; #[cfg(feature = "build-mpfr")] use libm_test::mpfloat::MpOp; -use libm_test::{MathOp, TupleCall}; +use libm_test::{MathOp, TupleCall, builtins_wrapper}; #[cfg(feature = "build-mpfr")] use rug::az::{self, Az}; @@ -22,18 +22,32 @@ cargo run -p util -- SUBCOMMAND: eval inputs... + x inputs... Evaulate the expression with a given basis. This can be useful for running routines with a debugger, or quickly checking input. Examples: * eval musl sinf 1.234 # print the results of musl sinf(1.234f32) * eval mpfr pow 1.234 2.432 # print the results of mpfr pow(1.234, 2.432) + + print inputs... + p inputs... + For each input, print it in different formats with various floating + point properties (normal, infinite, etc). "; fn main() { let args = env::args().collect::>(); - let str_args = args.iter().map(|s| s.as_str()).collect::>(); + let str_args = args + .iter() + .map(|s| { + // Allow pasting from comma-separated arguments + let s = s.as_str(); + s.strip_suffix(",").unwrap_or(s) + }) + .collect::>(); match &str_args.as_slice()[1..] { - ["eval", basis, op, inputs @ ..] => do_eval(basis, op, inputs), + ["eval" | "x", basis, op, inputs @ ..] => do_eval(basis, op, inputs), + ["print" | "p", inputs @ ..] => do_classify(inputs), _ => { println!("{USAGE}\nunrecognized input `{str_args:?}`"); std::process::exit(1); @@ -47,6 +61,7 @@ macro_rules! handle_call { CFn: $CFn:ty, RustFn: $RustFn:ty, RustArgs: $RustArgs:ty, + path: $path:path, attrs: [$($attr:meta),*], extra: ($basis:ident, $op:ident, $inputs:ident), fn_extra: $musl_fn:expr, @@ -56,7 +71,7 @@ macro_rules! handle_call { type Op = libm_test::op::$fn_name::Routine; let input = <$RustArgs>::parse($inputs); - let libm_fn: ::RustFn = libm::$fn_name; + let libm_fn: ::RustFn = $path; let output = match $basis { "libm" => input.call_intercept_panics(libm_fn), @@ -73,7 +88,7 @@ macro_rules! handle_call { } _ => panic!("unrecognized or disabled basis '{}'", $basis), }; - println!("{output:?} {:x}", Hexf(output)); + println!("{output:?} {:x}", Hex(output)); return; } }; @@ -83,7 +98,7 @@ macro_rules! handle_call { fn do_eval(basis: &str, op: &str, inputs: &[&str]) { libm_macros::for_each_function! { callback: handle_call, - emit_types: [CFn, RustFn, RustArgs], + emit_types: [CFn, RustFn, RustArgs, path], extra: (basis, op, inputs), fn_extra: match MACRO_FN_NAME { // Not provided by musl @@ -98,7 +113,8 @@ fn do_eval(basis: &str, op: &str, inputs: &[&str]) { | roundeven | roundevenf | ALL_F16 - | ALL_F128 => None, + | ALL_F128 + | ALL_BUILTINS => None, _ => Some(musl_math_sys::MACRO_FN_NAME) } } @@ -106,6 +122,69 @@ fn do_eval(basis: &str, op: &str, inputs: &[&str]) { panic!("no operation matching {op}"); } +/// Print basic float information to stdout. +fn do_classify(inputs: &[&str]) { + for s in inputs { + if let Some(s) = s.strip_suffix("f16") { + cfg_select! { + f16_enabled => { + let s = s.trim_end_matches("_"); + let x: f16 = parse(&[s], 0); + classify_print(x); + continue; + } + _ => { + panic!("parsing this type requires f16 support: `{s}`"); + } + } + }; + if let Some(s) = s.strip_suffix("f32") { + let s = s.trim_end_matches("_"); + let x: f32 = parse(&[s], 0); + classify_print(x); + continue; + } else if let Some(s) = s.strip_suffix("f64") { + let s = s.trim_end_matches("_"); + let x: f64 = parse(&[s], 0); + classify_print(x); + continue; + } + if let Some(s) = s.strip_suffix("f128") { + cfg_select! { + all(f128_enabled, feature = "build-mpfr") => { + let s = s.trim_end_matches("_"); + let x: f128 = parse_rug(&[s], 0); + classify_print(x); + continue; + } + _ => { + panic!( + "parsing this type requires f128 support and \ + the `build-mpfr` feature: `{s}`" + ); + } + } + }; + panic!("float type must be specified with a `f*` suffix: `{s}`"); + } +} + +fn classify_print(x: F) +where + F: Float, +{ + println!("{x:?}"); + println!(" hex: {}", Hex(x)); + println!(" bits: {}", Hex(x.to_bits())); + println!(" nan: {}", x.is_nan()); + println!(" inf: {}", x.is_infinite()); + println!(" normal: {}", !x.is_subnormal()); + println!(" pos: {}", x.is_sign_positive()); + println!(" exp: {} {}", x.ex(), Hex(x.ex())); + println!(" exp unbiased: {}", x.exp_unbiased()); + println!(" frac: {} {}", x.frac(), Hex(x.frac())); +} + /// Parse a tuple from a space-delimited string. trait ParseTuple { fn parse(input: &[&str]) -> Self; @@ -232,14 +311,56 @@ macro_rules! impl_parse_tuple_via_rug { }; } +#[cfg(f16_enabled)] +impl_parse_tuple!(f16); impl_parse_tuple!(f32); impl_parse_tuple!(f64); -#[cfg(f16_enabled)] -impl_parse_tuple_via_rug!(f16); #[cfg(f128_enabled)] impl_parse_tuple_via_rug!(f128); +macro_rules! impl_parse_tuple_int { + (@skip_u32 $ty:ty) => { + impl ParseTuple for ($ty,) { + fn parse(input: &[&str]) -> Self { + assert_eq!(input.len(), 1, "expected a single argument, got {input:?}"); + (parse(input, 0),) + } + } + + impl ParseTuple for ($ty, $ty) { + fn parse(input: &[&str]) -> Self { + assert_eq!(input.len(), 2, "expected two arguments, got {input:?}"); + (parse(input, 0), parse(input, 1)) + } + } + + impl FromStrRadix for $ty { + fn from_str_radix(s: &str, radix: u32) -> Result { + let s = strip_radix_prefix(s, radix); + <$ty>::from_str_radix(s, radix) + } + } + }; + ($ty:ty) => { + impl_parse_tuple_int!(@skip_u32 $ty); + + impl ParseTuple for ($ty, u32) { + fn parse(input: &[&str]) -> Self { + assert_eq!(input.len(), 2, "expected two arguments, got {input:?}"); + (parse(input, 0), parse(input, 1)) + } + } + }; +} + +impl_parse_tuple_int!(i32); +impl_parse_tuple_int!(i64); +impl_parse_tuple_int!(i128); +impl_parse_tuple_int!(@skip_u32 u32); +impl_parse_tuple_int!(u64); +impl_parse_tuple_int!(u128); + /// Try to parse the number, printing a nice message on failure. fn parse(input: &[&str], idx: usize) -> T { let s = input[idx]; @@ -286,13 +407,6 @@ trait FromStrRadix: Sized { fn from_str_radix(s: &str, radix: u32) -> Result; } -impl FromStrRadix for i32 { - fn from_str_radix(s: &str, radix: u32) -> Result { - let s = strip_radix_prefix(s, radix); - i32::from_str_radix(s, radix) - } -} - #[cfg(f16_enabled)] impl FromStrRadix for f16 { fn from_str_radix(s: &str, radix: u32) -> Result { diff --git a/library/compiler-builtins/etc/function-definitions.json b/library/compiler-builtins/etc/function-definitions.json index 4f796905b7543..88070abf0ce09 100644 --- a/library/compiler-builtins/etc/function-definitions.json +++ b/library/compiler-builtins/etc/function-definitions.json @@ -98,8 +98,8 @@ }, "ceil": { "sources": [ - "libm/src/math/arch/i586.rs", - "libm/src/math/arch/wasm32.rs", + "libm/src/math/arch/i586/rounding.rs", + "libm/src/math/arch/wasm32/rounding.rs", "libm/src/math/ceil.rs", "libm/src/math/generic/ceil.rs" ], @@ -107,7 +107,7 @@ }, "ceilf": { "sources": [ - "libm/src/math/arch/wasm32.rs", + "libm/src/math/arch/wasm32/rounding.rs", "libm/src/math/ceil.rs", "libm/src/math/generic/ceil.rs" ], @@ -253,7 +253,7 @@ }, "fabs": { "sources": [ - "libm/src/math/arch/wasm32.rs", + "libm/src/math/arch/wasm32/fabs.rs", "libm/src/math/fabs.rs", "libm/src/math/generic/fabs.rs" ], @@ -261,7 +261,7 @@ }, "fabsf": { "sources": [ - "libm/src/math/arch/wasm32.rs", + "libm/src/math/arch/wasm32/fabs.rs", "libm/src/math/fabs.rs", "libm/src/math/generic/fabs.rs" ], @@ -311,8 +311,8 @@ }, "floor": { "sources": [ - "libm/src/math/arch/i586.rs", - "libm/src/math/arch/wasm32.rs", + "libm/src/math/arch/i586/rounding.rs", + "libm/src/math/arch/wasm32/rounding.rs", "libm/src/math/floor.rs", "libm/src/math/generic/floor.rs" ], @@ -320,7 +320,7 @@ }, "floorf": { "sources": [ - "libm/src/math/arch/wasm32.rs", + "libm/src/math/arch/wasm32/rounding.rs", "libm/src/math/floor.rs", "libm/src/math/generic/floor.rs" ], @@ -342,26 +342,38 @@ }, "fma": { "sources": [ - "libm/src/math/arch/aarch64.rs", + "libm/src/math/arch/aarch64/fma.rs", + "libm/src/math/arch/loongarch/fma.rs", "libm/src/math/arch/x86/fma.rs", - "libm/src/math/fma.rs" + "libm/src/math/fma.rs", + "libm/src/math/generic/fma.rs" ], "type": "f64" }, "fmaf": { "sources": [ - "libm/src/math/arch/aarch64.rs", + "libm/src/math/arch/aarch64/fma.rs", + "libm/src/math/arch/loongarch/fma.rs", "libm/src/math/arch/x86/fma.rs", - "libm/src/math/fma.rs" + "libm/src/math/fma.rs", + "libm/src/math/generic/fma.rs" ], "type": "f32" }, "fmaf128": { "sources": [ - "libm/src/math/fma.rs" + "libm/src/math/fma.rs", + "libm/src/math/generic/fma.rs" ], "type": "f128" }, + "fmaf16": { + "sources": [ + "libm/src/math/fmaf16.rs", + "libm/src/math/generic/fma.rs" + ], + "type": "f16" + }, "fmax": { "sources": [ "libm/src/math/fmin_fmax.rs", @@ -560,16 +572,32 @@ }, "frexp": { "sources": [ - "libm/src/math/frexp.rs" + "libm/src/math/frexp.rs", + "libm/src/math/generic/frexp.rs" ], "type": "f64" }, "frexpf": { "sources": [ - "libm/src/math/frexpf.rs" + "libm/src/math/frexp.rs", + "libm/src/math/generic/frexp.rs" ], "type": "f32" }, + "frexpf128": { + "sources": [ + "libm/src/math/frexp.rs", + "libm/src/math/generic/frexp.rs" + ], + "type": "f128" + }, + "frexpf16": { + "sources": [ + "libm/src/math/frexp.rs", + "libm/src/math/generic/frexp.rs" + ], + "type": "f16" + }, "hypot": { "sources": [ "libm/src/math/hypot.rs" @@ -584,16 +612,32 @@ }, "ilogb": { "sources": [ + "libm/src/math/generic/ilogb.rs", "libm/src/math/ilogb.rs" ], "type": "f64" }, "ilogbf": { "sources": [ - "libm/src/math/ilogbf.rs" + "libm/src/math/generic/ilogb.rs", + "libm/src/math/ilogb.rs" ], "type": "f32" }, + "ilogbf128": { + "sources": [ + "libm/src/math/generic/ilogb.rs", + "libm/src/math/ilogb.rs" + ], + "type": "f128" + }, + "ilogbf16": { + "sources": [ + "libm/src/math/generic/ilogb.rs", + "libm/src/math/ilogb.rs" + ], + "type": "f16" + }, "j0": { "sources": [ "libm/src/math/j0.rs" @@ -788,29 +832,36 @@ }, "rint": { "sources": [ - "libm/src/math/arch/aarch64.rs", - "libm/src/math/arch/wasm32.rs", + "libm/src/math/arch/aarch64/rounding.rs", + "libm/src/math/arch/i586/rounding.rs", + "libm/src/math/arch/loongarch/rounding.rs", + "libm/src/math/arch/wasm32/rounding.rs", + "libm/src/math/generic/rint.rs", "libm/src/math/rint.rs" ], "type": "f64" }, "rintf": { "sources": [ - "libm/src/math/arch/aarch64.rs", - "libm/src/math/arch/wasm32.rs", + "libm/src/math/arch/aarch64/rounding.rs", + "libm/src/math/arch/loongarch/rounding.rs", + "libm/src/math/arch/wasm32/rounding.rs", + "libm/src/math/generic/rint.rs", "libm/src/math/rint.rs" ], "type": "f32" }, "rintf128": { "sources": [ + "libm/src/math/generic/rint.rs", "libm/src/math/rint.rs" ], "type": "f128" }, "rintf16": { "sources": [ - "libm/src/math/arch/aarch64.rs", + "libm/src/math/arch/aarch64/rounding.rs", + "libm/src/math/generic/rint.rs", "libm/src/math/rint.rs" ], "type": "f16" @@ -933,9 +984,10 @@ }, "sqrt": { "sources": [ - "libm/src/math/arch/aarch64.rs", - "libm/src/math/arch/wasm32.rs", - "libm/src/math/arch/x86.rs", + "libm/src/math/arch/aarch64/sqrt.rs", + "libm/src/math/arch/loongarch/sqrt.rs", + "libm/src/math/arch/wasm32/sqrt.rs", + "libm/src/math/arch/x86/sqrt.rs", "libm/src/math/generic/sqrt.rs", "libm/src/math/sqrt.rs" ], @@ -943,9 +995,10 @@ }, "sqrtf": { "sources": [ - "libm/src/math/arch/aarch64.rs", - "libm/src/math/arch/wasm32.rs", - "libm/src/math/arch/x86.rs", + "libm/src/math/arch/aarch64/sqrt.rs", + "libm/src/math/arch/loongarch/sqrt.rs", + "libm/src/math/arch/wasm32/sqrt.rs", + "libm/src/math/arch/x86/sqrt.rs", "libm/src/math/generic/sqrt.rs", "libm/src/math/sqrt.rs" ], @@ -960,7 +1013,7 @@ }, "sqrtf16": { "sources": [ - "libm/src/math/arch/aarch64.rs", + "libm/src/math/arch/aarch64/sqrt.rs", "libm/src/math/generic/sqrt.rs", "libm/src/math/sqrt.rs" ], @@ -1004,7 +1057,7 @@ }, "trunc": { "sources": [ - "libm/src/math/arch/wasm32.rs", + "libm/src/math/arch/wasm32/rounding.rs", "libm/src/math/generic/trunc.rs", "libm/src/math/trunc.rs" ], @@ -1012,7 +1065,7 @@ }, "truncf": { "sources": [ - "libm/src/math/arch/wasm32.rs", + "libm/src/math/arch/wasm32/rounding.rs", "libm/src/math/generic/trunc.rs", "libm/src/math/trunc.rs" ], diff --git a/library/compiler-builtins/etc/function-list.txt b/library/compiler-builtins/etc/function-list.txt index 1f226c8c0ff3b..14f75a2c5783b 100644 --- a/library/compiler-builtins/etc/function-list.txt +++ b/library/compiler-builtins/etc/function-list.txt @@ -54,6 +54,7 @@ floorf16 fma fmaf fmaf128 +fmaf16 fmax fmaxf fmaxf128 @@ -84,10 +85,14 @@ fmodf128 fmodf16 frexp frexpf +frexpf128 +frexpf16 hypot hypotf ilogb ilogbf +ilogbf128 +ilogbf16 j0 j0f j1 diff --git a/library/compiler-builtins/etc/thumbv6-none-eabi.json b/library/compiler-builtins/etc/thumbv6-none-eabi.json new file mode 100644 index 0000000000000..4c1f760ac3e03 --- /dev/null +++ b/library/compiler-builtins/etc/thumbv6-none-eabi.json @@ -0,0 +1,20 @@ +{ + "abi": "eabi", + "arch": "arm", + "asm-args": ["-mthumb-interwork", "-march=armv6", "-mlittle-endian"], + "c-enum-min-bits": 8, + "crt-objects-fallback": "false", + "data-layout": "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64", + "emit-debug-gdb-scripts": false, + "features": "+soft-float,+strict-align,+v6k", + "frame-pointer": "always", + "has-thumb-interworking": true, + "linker": "rust-lld", + "linker-flavor": "gnu-lld", + "llvm-floatabi": "soft", + "llvm-target": "thumbv6-none-eabi", + "max-atomic-width": 32, + "panic-strategy": "abort", + "relocation-model": "static", + "target-pointer-width": 32 +} diff --git a/library/compiler-builtins/etc/update-api-list.py b/library/compiler-builtins/etc/update-api-list.py index 76c75cbf4dccb..2d8ad2903646d 100755 --- a/library/compiler-builtins/etc/update-api-list.py +++ b/library/compiler-builtins/etc/update-api-list.py @@ -6,6 +6,8 @@ needed, or that lists are sorted. """ +# FIXME: this needs to be updated to work with compiler-builtins sources + import difflib import json import re @@ -14,7 +16,7 @@ from dataclasses import dataclass from glob import glob from pathlib import Path -from typing import Any, Callable, TypeAlias +from typing import Any, TypeAlias SELF_PATH = Path(__file__) ETC_DIR = SELF_PATH.parent @@ -116,10 +118,20 @@ def _init_function_list(self, index: IndexTy) -> None: def _init_defs(self, index: IndexTy) -> None: defs = {name: set() for name in self.public_functions} - funcs = (i for i in index.values() if "function" in i["inner"]) - funcs = (f for f in funcs if f["name"] in self.public_functions) - for func in funcs: - defs[func["name"]].add(func["span"]["filename"]) + all_funcs = (i for i in index.values() if "function" in i["inner"]) + + for func_def in all_funcs: + func_def_name = func_def["name"] + for pub_func_name in self.public_functions: + needles = [ + pub_func_name, + f"{pub_func_name}_round", + f"{pub_func_name}_status", + ] + if not any(needle == func_def_name for needle in needles): + continue + + defs[pub_func_name].add(func_def["span"]["filename"]) # A lot of the `arch` module is often configured out so doesn't show up in docs. Use # string matching as a fallback. @@ -134,6 +146,8 @@ def _init_defs(self, index: IndexTy) -> None: for name, sources in defs.items(): base_sources = defs[base_name(name)[0]] + + # Also add any functions in `generic` that use this function's base name for src in (s for s in base_sources if "generic" in s): sources.add(src) @@ -187,36 +201,6 @@ def write_function_defs(self, check: bool) -> None: with open(out_file, "w") as f: f.write(output) - def tidy_lists(self) -> None: - """In each file, check annotations indicating blocks of code should be sorted or should - include all public API. - """ - - flist = sp.check_output(["git", "ls-files"], cwd=ROOT_DIR, text=True) - - for path in flist.splitlines(): - fpath = ROOT_DIR.joinpath(path) - if fpath.is_dir() or fpath == SELF_PATH: - continue - - lines = fpath.read_text().splitlines() - - validate_delimited_block( - fpath, - lines, - "verify-sorted-start", - "verify-sorted-end", - ensure_sorted, - ) - - validate_delimited_block( - fpath, - lines, - "verify-apilist-start", - "verify-apilist-end", - lambda p, n, lines: self.ensure_contains_api(p, n, lines), - ) - def ensure_contains_api(self, fpath: Path, line_num: int, lines: list[str]): """Given a list of strings, ensure that each public function we have is named somewhere. @@ -238,54 +222,6 @@ def ensure_contains_api(self, fpath: Path, line_num: int, lines: list[str]): exit(1) -def validate_delimited_block( - fpath: Path, - lines: list[str], - start: str, - end: str, - validate: Callable[[Path, int, list[str]], None], -) -> None: - """Identify blocks of code wrapped within `start` and `end`, collect their contents - to a list of strings, and call `validate` for each of those lists. - """ - relpath = fpath.relative_to(ROOT_DIR) - block_lines = [] - block_start_line: None | int = None - for line_num, line in enumerate(lines): - line_num += 1 - - if start in line: - block_start_line = line_num - continue - - if end in line: - if block_start_line is None: - eprint(f"`{end}` without `{start}` at {relpath}:{line_num}") - exit(1) - - validate(fpath, block_start_line, block_lines) - block_lines = [] - block_start_line = None - continue - - if block_start_line is not None: - block_lines.append(line) - - if block_start_line is not None: - eprint(f"`{start}` without `{end}` at {relpath}:{block_start_line}") - exit(1) - - -def ensure_sorted(fpath: Path, block_start_line: int, lines: list[str]) -> None: - """Ensure that a list of lines is sorted, otherwise print a diff and exit.""" - relpath = fpath.relative_to(ROOT_DIR) - diff_and_exit( - "\n".join(lines), - "\n".join(sorted(lines)), - f"sorted block at {relpath}:{block_start_line}", - ) - - def diff_and_exit(actual: str, expected: str, name: str): """If the two strings are different, print a diff between them and then exit with an error. @@ -322,11 +258,13 @@ def base_name(name: str) -> tuple[str, str]: if name.endswith("f"): return (name.rstrip("f"), "f32") - - if name.endswith("f16"): + elif name.endswith("f16"): return (name.rstrip("f16"), "f16") - - if name.endswith("f128"): + elif name.endswith("f32"): + return (name.rstrip("f32"), "f32") + elif name.endswith("f64"): + return (name.rstrip("f64"), "f64") + elif name.endswith("f128"): return (name.rstrip("f128"), "f128") return (name, "f64") @@ -340,8 +278,6 @@ def ensure_updated_list(check: bool) -> None: crate.write_function_list(check) crate.write_function_defs(check) - crate.tidy_lists() - def main(): """By default overwrite the file. If `--check` is passed, print a diff instead and diff --git a/library/compiler-builtins/libm-test/Cargo.toml b/library/compiler-builtins/libm-test/Cargo.toml index adecfc1af6b87..5014fb0008611 100644 --- a/library/compiler-builtins/libm-test/Cargo.toml +++ b/library/compiler-builtins/libm-test/Cargo.toml @@ -5,8 +5,40 @@ edition = "2024" publish = false license = "MIT OR Apache-2.0" +[dependencies] +anyhow.workspace = true +api-list-common.workspace = true +compiler_builtins = { workspace = true, default-features = false, features = ["unstable-public-internals"] } +# This is not directly used but is required so we can enable `gmp-mpfr-sys/force-cross`. +gmp-mpfr-sys = { workspace = true, optional = true } +indicatif.workspace = true +libm = { workspace = true, default-features = false, features = ["unstable-public-internals"] } +libm-macros.workspace = true +musl-math-sys = { workspace = true, optional = true } +paste.workspace = true +rand.workspace = true +rand_chacha.workspace = true +rayon.workspace = true +rug = { workspace = true, optional = true } + +# Really dev dependencies, but those can't be optional +criterion = { workspace = true, optional = true } +gungraun = { workspace = true, optional = true } + +[target.'cfg(target_family = "wasm")'.dependencies] +getrandom = { workspace = true, features = ["wasm_js"] } +indicatif = { workspace = true, features = ["wasmbind"] } + +[build-dependencies] +rand = { workspace = true, optional = true } + +[dev-dependencies] +libtest-mimic.workspace = true + [features] -default = ["build-mpfr", "unstable-float"] +# Defaults should match the defaults in compiler-builtins since we have that +# dependency with `default-features=false`. +default = ["build-mpfr", "unstable-float", "compiler_builtins/arch"] # Propagated from libm because this affects which functions we test. unstable-float = ["libm/unstable-float", "rug?/nightly-float"] @@ -18,8 +50,10 @@ build-mpfr = ["dep:rug", "dep:gmp-mpfr-sys"] # Build our own musl for testing and benchmarks build-musl = ["dep:musl-math-sys"] -# Enable report generation without bringing in more dependencies by default -benchmarking-reports = ["criterion/plotters", "criterion/html_reports"] +# Config for wall time benchmarks. Plotters and html_reports bring in extra +# deps so are off by default for CI. +benchmarking-reports = ["walltime", "criterion/plotters", "criterion/html_reports"] +walltime = ["dep:criterion"] # Enable icount benchmarks (requires gungraun-runner and valgrind locally) icount = ["dep:gungraun"] @@ -27,31 +61,6 @@ icount = ["dep:gungraun"] # Run with a reduced set of benchmarks, such as for CI short-benchmarks = [] -[dependencies] -anyhow = "1.0.98" -# This is not directly used but is required so we can enable `gmp-mpfr-sys/force-cross`. -gmp-mpfr-sys = { version = "1.6.5", optional = true, default-features = false } -gungraun = { version = "0.17.0", optional = true } -indicatif = { version = "0.18.0", default-features = false } -libm = { path = "../libm", features = ["unstable-public-internals"] } -libm-macros = { path = "../crates/libm-macros" } -musl-math-sys = { path = "../crates/musl-math-sys", optional = true } -paste = "1.0.15" -rand = "0.9.1" -rand_chacha = "0.9.0" -rayon = "1.10.0" -rug = { version = "1.27.0", optional = true, default-features = false, features = ["float", "integer", "std"] } - -[target.'cfg(target_family = "wasm")'.dependencies] -getrandom = { version = "0.3.3", features = ["wasm_js"] } - -[build-dependencies] -rand = { version = "0.9.1", optional = true } - -[dev-dependencies] -criterion = { version = "0.6.0", default-features = false, features = ["cargo_bench_support"] } -libtest-mimic = "0.8.1" - [[bench]] name = "icount" harness = false @@ -60,15 +69,10 @@ required-features = ["icount"] [[bench]] name = "random" harness = false +required-features = ["walltime"] [[test]] # No harness so that we can skip tests at runtime based on env. Prefixed with # `z` so these tests get run last. name = "z_extensive" harness = false - -[lints.rust] -# Values from the chared config.rs used by `libm` but not the test crate -unexpected_cfgs = { level = "warn", check-cfg = [ - 'cfg(feature, values("arch", "force-soft-floats", "unstable-intrinsics"))', -] } diff --git a/library/compiler-builtins/libm-test/benches/icount.rs b/library/compiler-builtins/libm-test/benches/icount.rs index fb856d9be4517..8e067f2da5e6d 100644 --- a/library/compiler-builtins/libm-test/benches/icount.rs +++ b/library/compiler-builtins/libm-test/benches/icount.rs @@ -5,7 +5,7 @@ use std::hint::black_box; use gungraun::{library_benchmark, library_benchmark_group, main}; -use libm::support::{HInt, Hexf, hf16, hf32, hf64, hf128, u256}; +use libm::support::{HInt, Hex, hf16, hf32, hf64, hf128, i256, u256}; use libm_test::generate::spaced; use libm_test::{CheckBasis, CheckCtx, GeneratorKind, MathOp, OpRustArgs, TupleCall, op}; @@ -41,11 +41,6 @@ macro_rules! icount_benches { input.call(f); } } - - library_benchmark_group!( - name = [< icount_bench_ $fn_name _group >]; - benchmarks = [< icount_bench_ $fn_name >] - ); } }; } @@ -54,6 +49,325 @@ libm_macros::for_each_function! { callback: icount_benches, } +library_benchmark_group!( + name = icount_bench_math_group, + benchmarks = [ + // verify-apilist-start + // verify-sorted-start + icount_bench_acos, + icount_bench_acosf, + icount_bench_acosh, + icount_bench_acoshf, + icount_bench_addf128, + icount_bench_addf16, + icount_bench_addf32, + icount_bench_addf64, + icount_bench_ashl_u128, + icount_bench_ashl_u32, + icount_bench_ashl_u64, + icount_bench_ashr_i128, + icount_bench_ashr_i32, + icount_bench_ashr_i64, + icount_bench_asin, + icount_bench_asinf, + icount_bench_asinh, + icount_bench_asinhf, + icount_bench_atan, + icount_bench_atan2, + icount_bench_atan2f, + icount_bench_atanf, + icount_bench_atanh, + icount_bench_atanhf, + icount_bench_cbrt, + icount_bench_cbrtf, + icount_bench_ceil, + icount_bench_ceilf, + icount_bench_ceilf128, + icount_bench_ceilf16, + icount_bench_copysign, + icount_bench_copysignf, + icount_bench_copysignf128, + icount_bench_copysignf16, + icount_bench_cos, + icount_bench_cosf, + icount_bench_cosh, + icount_bench_coshf, + icount_bench_divf128, + icount_bench_divf32, + icount_bench_divf64, + icount_bench_eqf128, + icount_bench_eqf16, + icount_bench_eqf32, + icount_bench_eqf64, + icount_bench_erf, + icount_bench_erfc, + icount_bench_erfcf, + icount_bench_erff, + icount_bench_exp, + icount_bench_exp10, + icount_bench_exp10f, + icount_bench_exp2, + icount_bench_exp2f, + icount_bench_expf, + icount_bench_expm1, + icount_bench_expm1f, + icount_bench_extend_f16_f128, + icount_bench_extend_f16_f32, + icount_bench_extend_f16_f64, + icount_bench_extend_f32_f128, + icount_bench_extend_f32_f64, + icount_bench_extend_f64_f128, + icount_bench_fabs, + icount_bench_fabsf, + icount_bench_fabsf128, + icount_bench_fabsf16, + icount_bench_fdim, + icount_bench_fdimf, + icount_bench_fdimf128, + icount_bench_fdimf16, + icount_bench_floor, + icount_bench_floorf, + icount_bench_floorf128, + icount_bench_floorf16, + icount_bench_fma, + icount_bench_fmaf, + icount_bench_fmaf128, + icount_bench_fmaf16, + icount_bench_fmax, + icount_bench_fmaxf, + icount_bench_fmaxf128, + icount_bench_fmaxf16, + icount_bench_fmaximum, + icount_bench_fmaximum_num, + icount_bench_fmaximum_numf, + icount_bench_fmaximum_numf128, + icount_bench_fmaximum_numf16, + icount_bench_fmaximumf, + icount_bench_fmaximumf128, + icount_bench_fmaximumf16, + icount_bench_fmin, + icount_bench_fminf, + icount_bench_fminf128, + icount_bench_fminf16, + icount_bench_fminimum, + icount_bench_fminimum_num, + icount_bench_fminimum_numf, + icount_bench_fminimum_numf128, + icount_bench_fminimum_numf16, + icount_bench_fminimumf, + icount_bench_fminimumf128, + icount_bench_fminimumf16, + icount_bench_fmod, + icount_bench_fmodf, + icount_bench_fmodf128, + icount_bench_fmodf16, + icount_bench_frexp, + icount_bench_frexpf, + icount_bench_frexpf128, + icount_bench_frexpf16, + icount_bench_ftoi_f128_i128, + icount_bench_ftoi_f128_i32, + icount_bench_ftoi_f128_i64, + icount_bench_ftoi_f128_u128, + icount_bench_ftoi_f128_u32, + icount_bench_ftoi_f128_u64, + icount_bench_ftoi_f32_i128, + icount_bench_ftoi_f32_i32, + icount_bench_ftoi_f32_i64, + icount_bench_ftoi_f32_u128, + icount_bench_ftoi_f32_u32, + icount_bench_ftoi_f32_u64, + icount_bench_ftoi_f64_i128, + icount_bench_ftoi_f64_i32, + icount_bench_ftoi_f64_i64, + icount_bench_ftoi_f64_u128, + icount_bench_ftoi_f64_u32, + icount_bench_ftoi_f64_u64, + icount_bench_gef128, + icount_bench_gef16, + icount_bench_gef32, + icount_bench_gef64, + icount_bench_gtf128, + icount_bench_gtf16, + icount_bench_gtf32, + icount_bench_gtf64, + icount_bench_hypot, + icount_bench_hypotf, + icount_bench_iadd_i128, + icount_bench_iadd_u128, + icount_bench_iaddo_i128, + icount_bench_iaddo_u128, + icount_bench_idiv_i128, + icount_bench_idiv_i32, + icount_bench_idiv_i64, + icount_bench_idiv_u128, + icount_bench_idiv_u32, + icount_bench_idiv_u64, + icount_bench_idivmod_i128, + icount_bench_idivmod_i32, + icount_bench_idivmod_i64, + icount_bench_idivmod_u128, + icount_bench_idivmod_u32, + icount_bench_idivmod_u64, + icount_bench_ilogb, + icount_bench_ilogbf, + icount_bench_ilogbf128, + icount_bench_ilogbf16, + icount_bench_imod_i128, + icount_bench_imod_i32, + icount_bench_imod_i64, + icount_bench_imod_u128, + icount_bench_imod_u32, + icount_bench_imod_u64, + icount_bench_imul_i128, + icount_bench_imul_u64, + icount_bench_imulo_i128, + icount_bench_imulo_i32, + icount_bench_imulo_i64, + icount_bench_imulo_u128, + icount_bench_isub_i128, + icount_bench_isub_u128, + icount_bench_isubo_i128, + icount_bench_isubo_u128, + icount_bench_itof_i128_f128, + icount_bench_itof_i128_f32, + icount_bench_itof_i128_f64, + icount_bench_itof_i32_f128, + icount_bench_itof_i32_f32, + icount_bench_itof_i32_f64, + icount_bench_itof_i64_f128, + icount_bench_itof_i64_f32, + icount_bench_itof_i64_f64, + icount_bench_itof_u128_f128, + icount_bench_itof_u128_f32, + icount_bench_itof_u128_f64, + icount_bench_itof_u32_f128, + icount_bench_itof_u32_f32, + icount_bench_itof_u32_f64, + icount_bench_itof_u64_f128, + icount_bench_itof_u64_f32, + icount_bench_itof_u64_f64, + icount_bench_j0, + icount_bench_j0f, + icount_bench_j1, + icount_bench_j1f, + icount_bench_jn, + icount_bench_jnf, + icount_bench_ldexp, + icount_bench_ldexpf, + icount_bench_ldexpf128, + icount_bench_ldexpf16, + icount_bench_leading_zeros_u128, + icount_bench_leading_zeros_u32, + icount_bench_leading_zeros_u64, + icount_bench_lef128, + icount_bench_lef16, + icount_bench_lef32, + icount_bench_lef64, + icount_bench_lgamma, + icount_bench_lgamma_r, + icount_bench_lgammaf, + icount_bench_lgammaf_r, + icount_bench_log, + icount_bench_log10, + icount_bench_log10f, + icount_bench_log1p, + icount_bench_log1pf, + icount_bench_log2, + icount_bench_log2f, + icount_bench_logf, + icount_bench_lshr_u128, + icount_bench_lshr_u32, + icount_bench_lshr_u64, + icount_bench_ltf128, + icount_bench_ltf16, + icount_bench_ltf32, + icount_bench_ltf64, + icount_bench_modf, + icount_bench_modff, + icount_bench_mulf128, + icount_bench_mulf16, + icount_bench_mulf32, + icount_bench_mulf64, + icount_bench_narrow_f128_f16, + icount_bench_narrow_f128_f32, + icount_bench_narrow_f128_f64, + icount_bench_narrow_f32_f16, + icount_bench_narrow_f64_f16, + icount_bench_narrow_f64_f32, + icount_bench_nef128, + icount_bench_nef16, + icount_bench_nef32, + icount_bench_nef64, + icount_bench_nextafter, + icount_bench_nextafterf, + icount_bench_pow, + icount_bench_powf, + icount_bench_powif128, + icount_bench_powif32, + icount_bench_powif64, + icount_bench_remainder, + icount_bench_remainderf, + icount_bench_remquo, + icount_bench_remquof, + icount_bench_rint, + icount_bench_rintf, + icount_bench_rintf128, + icount_bench_rintf16, + icount_bench_round, + icount_bench_roundeven, + icount_bench_roundevenf, + icount_bench_roundevenf128, + icount_bench_roundevenf16, + icount_bench_roundf, + icount_bench_roundf128, + icount_bench_roundf16, + icount_bench_scalbn, + icount_bench_scalbnf, + icount_bench_scalbnf128, + icount_bench_scalbnf16, + icount_bench_sin, + icount_bench_sincos, + icount_bench_sincosf, + icount_bench_sinf, + icount_bench_sinh, + icount_bench_sinhf, + icount_bench_sqrt, + icount_bench_sqrtf, + icount_bench_sqrtf128, + icount_bench_sqrtf16, + icount_bench_subf128, + icount_bench_subf16, + icount_bench_subf32, + icount_bench_subf64, + icount_bench_tan, + icount_bench_tanf, + icount_bench_tanh, + icount_bench_tanhf, + icount_bench_tgamma, + icount_bench_tgammaf, + icount_bench_trailing_zeros_u128, + icount_bench_trailing_zeros_u32, + icount_bench_trailing_zeros_u64, + icount_bench_trunc, + icount_bench_truncf, + icount_bench_truncf128, + icount_bench_truncf16, + icount_bench_unordf128, + icount_bench_unordf16, + icount_bench_unordf32, + icount_bench_unordf64, + icount_bench_y0, + icount_bench_y0f, + icount_bench_y1, + icount_bench_y1f, + icount_bench_yn, + icount_bench_ynf, + // verify-sorted-end + // verify-apilist-end + ] +); + fn setup_u128_mul() -> Vec<(u128, u128)> { let step = u128::MAX / 300; let mut x = 0u128; @@ -103,6 +417,13 @@ fn setup_u256_shift() -> Vec<(u256, u32)> { v } +fn setup_i256_shift() -> Vec<(i256, u32)> { + setup_u256_shift() + .into_iter() + .map(|(x, i)| (x.signed(), i)) + .collect() +} + #[library_benchmark] #[bench::linspace(setup_u128_mul())] fn icount_bench_u128_widen_mul(cases: Vec<(u128, u128)>) { @@ -154,15 +475,25 @@ fn icount_bench_u256_shr(cases: Vec<(u256, u32)>) { } } +#[library_benchmark] +#[bench::linspace(setup_i256_shift())] +fn icount_bench_i256_shr(cases: Vec<(i256, u32)>) { + for (x, y) in cases.iter().copied() { + black_box(black_box(x) >> black_box(y)); + } +} + library_benchmark_group!( - name = icount_bench_u128_group; - benchmarks = - icount_bench_u128_widen_mul, - icount_bench_u256_narrowing_div, - icount_bench_u256_add, - icount_bench_u256_sub, - icount_bench_u256_shl, - icount_bench_u256_shr + name = icount_bench_u128_group, + benchmarks = [ + icount_bench_u128_widen_mul, + icount_bench_u256_narrowing_div, + icount_bench_u256_add, + icount_bench_u256_sub, + icount_bench_u256_shl, + icount_bench_u256_shr, + icount_bench_i256_shr, + ] ); #[library_benchmark] @@ -194,222 +525,59 @@ fn icount_bench_hf128(s: &str) -> f128 { } library_benchmark_group!( - name = icount_bench_hf_parse_group; - benchmarks = - icount_bench_hf16, - icount_bench_hf32, - icount_bench_hf64, - icount_bench_hf128 + name = icount_bench_hf_parse_group, + benchmarks = [ + icount_bench_hf16, + icount_bench_hf32, + icount_bench_hf64, + icount_bench_hf128, + ] ); #[library_benchmark] #[bench::short(1.015625)] #[bench::max(f16::MAX)] fn icount_bench_print_hf16(x: f16) -> String { - black_box(Hexf(x).to_string()) + black_box(Hex(x).to_string()) } #[library_benchmark] #[bench::short(1.015625)] #[bench::max(f32::MAX)] fn icount_bench_print_hf32(x: f32) -> String { - black_box(Hexf(x).to_string()) + black_box(Hex(x).to_string()) } #[library_benchmark] #[bench::short(1.015625)] #[bench::max(f64::MAX)] fn icount_bench_print_hf64(x: f64) -> String { - black_box(Hexf(x).to_string()) + black_box(Hex(x).to_string()) } #[library_benchmark] #[bench::short(1.015625)] #[bench::max(f128::MAX)] fn icount_bench_print_hf128(x: f128) -> String { - black_box(Hexf(x).to_string()) + black_box(Hex(x).to_string()) } library_benchmark_group!( - name = icount_bench_hf_print_group; - benchmarks = - icount_bench_print_hf16, - icount_bench_print_hf32, - icount_bench_print_hf64, - icount_bench_print_hf128 + name = icount_bench_hf_print_group, + benchmarks = [ + icount_bench_print_hf16, + icount_bench_print_hf32, + icount_bench_print_hf64, + icount_bench_print_hf128, + ] ); main!( - library_benchmark_groups = - // Benchmarks not related to public libm math - icount_bench_u128_group, - icount_bench_hf_parse_group, - icount_bench_hf_print_group, - // verify-apilist-start - // verify-sorted-start - icount_bench_acos_group, - icount_bench_acosf_group, - icount_bench_acosh_group, - icount_bench_acoshf_group, - icount_bench_asin_group, - icount_bench_asinf_group, - icount_bench_asinh_group, - icount_bench_asinhf_group, - icount_bench_atan2_group, - icount_bench_atan2f_group, - icount_bench_atan_group, - icount_bench_atanf_group, - icount_bench_atanh_group, - icount_bench_atanhf_group, - icount_bench_cbrt_group, - icount_bench_cbrtf_group, - icount_bench_ceil_group, - icount_bench_ceilf128_group, - icount_bench_ceilf16_group, - icount_bench_ceilf_group, - icount_bench_copysign_group, - icount_bench_copysignf128_group, - icount_bench_copysignf16_group, - icount_bench_copysignf_group, - icount_bench_cos_group, - icount_bench_cosf_group, - icount_bench_cosh_group, - icount_bench_coshf_group, - icount_bench_erf_group, - icount_bench_erfc_group, - icount_bench_erfcf_group, - icount_bench_erff_group, - icount_bench_exp10_group, - icount_bench_exp10f_group, - icount_bench_exp2_group, - icount_bench_exp2f_group, - icount_bench_exp_group, - icount_bench_expf_group, - icount_bench_expm1_group, - icount_bench_expm1f_group, - icount_bench_fabs_group, - icount_bench_fabsf128_group, - icount_bench_fabsf16_group, - icount_bench_fabsf_group, - icount_bench_fdim_group, - icount_bench_fdimf128_group, - icount_bench_fdimf16_group, - icount_bench_fdimf_group, - icount_bench_floor_group, - icount_bench_floorf128_group, - icount_bench_floorf16_group, - icount_bench_floorf_group, - icount_bench_fma_group, - icount_bench_fmaf128_group, - icount_bench_fmaf_group, - icount_bench_fmax_group, - icount_bench_fmaxf128_group, - icount_bench_fmaxf16_group, - icount_bench_fmaxf_group, - icount_bench_fmaximum_group, - icount_bench_fmaximum_num_group, - icount_bench_fmaximum_numf128_group, - icount_bench_fmaximum_numf16_group, - icount_bench_fmaximum_numf_group, - icount_bench_fmaximumf128_group, - icount_bench_fmaximumf16_group, - icount_bench_fmaximumf_group, - icount_bench_fmin_group, - icount_bench_fminf128_group, - icount_bench_fminf16_group, - icount_bench_fminf_group, - icount_bench_fminimum_group, - icount_bench_fminimum_num_group, - icount_bench_fminimum_numf128_group, - icount_bench_fminimum_numf16_group, - icount_bench_fminimum_numf_group, - icount_bench_fminimumf128_group, - icount_bench_fminimumf16_group, - icount_bench_fminimumf_group, - icount_bench_fmod_group, - icount_bench_fmodf128_group, - icount_bench_fmodf16_group, - icount_bench_fmodf_group, - icount_bench_frexp_group, - icount_bench_frexpf_group, - icount_bench_hypot_group, - icount_bench_hypotf_group, - icount_bench_ilogb_group, - icount_bench_ilogbf_group, - icount_bench_j0_group, - icount_bench_j0f_group, - icount_bench_j1_group, - icount_bench_j1f_group, - icount_bench_jn_group, - icount_bench_jnf_group, - icount_bench_ldexp_group, - icount_bench_ldexpf128_group, - icount_bench_ldexpf16_group, - icount_bench_ldexpf_group, - icount_bench_lgamma_group, - icount_bench_lgamma_r_group, - icount_bench_lgammaf_group, - icount_bench_lgammaf_r_group, - icount_bench_log10_group, - icount_bench_log10f_group, - icount_bench_log1p_group, - icount_bench_log1pf_group, - icount_bench_log2_group, - icount_bench_log2f_group, - icount_bench_log_group, - icount_bench_logf_group, - icount_bench_modf_group, - icount_bench_modff_group, - icount_bench_nextafter_group, - icount_bench_nextafterf_group, - icount_bench_pow_group, - icount_bench_powf_group, - icount_bench_remainder_group, - icount_bench_remainderf_group, - icount_bench_remquo_group, - icount_bench_remquof_group, - icount_bench_rint_group, - icount_bench_rintf128_group, - icount_bench_rintf16_group, - icount_bench_rintf_group, - icount_bench_round_group, - icount_bench_roundeven_group, - icount_bench_roundevenf128_group, - icount_bench_roundevenf16_group, - icount_bench_roundevenf_group, - icount_bench_roundf128_group, - icount_bench_roundf16_group, - icount_bench_roundf_group, - icount_bench_scalbn_group, - icount_bench_scalbnf128_group, - icount_bench_scalbnf16_group, - icount_bench_scalbnf_group, - icount_bench_sin_group, - icount_bench_sincos_group, - icount_bench_sincosf_group, - icount_bench_sinf_group, - icount_bench_sinh_group, - icount_bench_sinhf_group, - icount_bench_sqrt_group, - icount_bench_sqrtf128_group, - icount_bench_sqrtf16_group, - icount_bench_sqrtf_group, - icount_bench_tan_group, - icount_bench_tanf_group, - icount_bench_tanh_group, - icount_bench_tanhf_group, - icount_bench_tgamma_group, - icount_bench_tgammaf_group, - icount_bench_trunc_group, - icount_bench_truncf128_group, - icount_bench_truncf16_group, - icount_bench_truncf_group, - icount_bench_y0_group, - icount_bench_y0f_group, - icount_bench_y1_group, - icount_bench_y1f_group, - icount_bench_yn_group, - icount_bench_ynf_group, - // verify-sorted-end - // verify-apilist-end + library_benchmark_groups = [ + // Benchmarks not related to public libm math + icount_bench_u128_group, + icount_bench_hf_parse_group, + icount_bench_hf_print_group, + icount_bench_math_group, + ] ); diff --git a/library/compiler-builtins/libm-test/benches/random.rs b/library/compiler-builtins/libm-test/benches/random.rs index 1b17f049ecac2..ae4c2f51bdec5 100644 --- a/library/compiler-builtins/libm-test/benches/random.rs +++ b/library/compiler-builtins/libm-test/benches/random.rs @@ -69,7 +69,7 @@ where use anyhow::Context; use libm_test::CheckOutput; - if cfg!(x86_no_sse) && musl_extra.skip_on_i586 { + if cfg!(x86_no_sse2) && musl_extra.skip_on_i586 { break; } @@ -137,7 +137,8 @@ libm_macros::for_each_function! { | roundeven | roundevenf | ALL_F16 - | ALL_F128 => (false, None), + | ALL_F128 + | ALL_BUILTINS => (false, None), // By default we never skip (false) and always have a musl function available _ => (false, Some(musl_math_sys::MACRO_FN_NAME)) diff --git a/library/compiler-builtins/libm-test/build.rs b/library/compiler-builtins/libm-test/build.rs index 510ba842f10ab..fa7db8ed63e3e 100644 --- a/library/compiler-builtins/libm-test/build.rs +++ b/library/compiler-builtins/libm-test/build.rs @@ -1,9 +1,10 @@ #[path = "../libm/configure.rs"] mod configure; -use configure::Config; + +use configure::{Config, Library}; fn main() { println!("cargo:rerun-if-changed=../libm/configure.rs"); - let cfg = Config::from_env(); - configure::emit_test_config(&cfg); + let cfg = Config::from_env(Library::LibmTest); + configure::emit(&cfg); } diff --git a/library/compiler-builtins/libm-test/examples/plot_domains.rs b/library/compiler-builtins/libm-test/examples/plot_domains.rs index 7331d454f2111..b2fd1979ad550 100644 --- a/library/compiler-builtins/libm-test/examples/plot_domains.rs +++ b/library/compiler-builtins/libm-test/examples/plot_domains.rs @@ -52,7 +52,7 @@ fn main() { /// Run multiple generators for a single operator. fn plot_one_operator(out_dir: &Path, config: &mut String) where - Op: MathOp, + Op: MathOp, Op::RustArgs: SpacedInput, { let mut ctx = CheckCtx::new(Op::IDENTIFIER, CheckBasis::Mpfr, GeneratorKind::Spaced); diff --git a/library/compiler-builtins/libm-test/src/builtins_wrapper.rs b/library/compiler-builtins/libm-test/src/builtins_wrapper.rs new file mode 100644 index 0000000000000..ce517148b9ca3 --- /dev/null +++ b/library/compiler-builtins/libm-test/src/builtins_wrapper.rs @@ -0,0 +1,310 @@ +//! Wrappers around compiler-builtins functions. +//! +//! Functions from compiler-builtins have a different naming scheme from libm and often a different +//! ABI (doesn't work with libm-test traits because that changes the type signature). Wrap these +//! to make them a bit more similar to the rest of the libm functions. + +macro_rules! cb_op { + // Fully generic version + ($mod:ident, $cb_name:ident, $new_name:ident, ($($arg:ident: $ArgTy:ty),*) -> $RetTy:ty) => { + pub fn $new_name($($arg: $ArgTy),*) -> $RetTy { + compiler_builtins::float::$mod::$cb_name($($arg),*) + } + }; + (@int $mod:ident, $cb_name:ident, $new_name:ident, ($($arg:ident: $ArgTy:ty),*) -> $RetTy:ty) => { + pub fn $new_name($($arg: $ArgTy),*) -> $RetTy { + compiler_builtins::int::$mod::$cb_name($($arg),*) + } + }; + + // Common signatures + (@binop $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + cb_op!($mod, $cb_name, $new_name, (a: $ty, b: $ty) -> $ty); + }; + + // Cmp signatures. See the documentation in cmp.rs regarding the result. + (@cmp_eq $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + pub fn $new_name(a: $ty, b: $ty) -> bool { + compiler_builtins::float::$mod::$cb_name(a, b) == 0 + } + }; + (@cmp_ne $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + pub fn $new_name(a: $ty, b: $ty) -> bool { + compiler_builtins::float::$mod::$cb_name(a, b) != 0 + } + }; + (@cmp_unord $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + pub fn $new_name(a: $ty, b: $ty) -> bool { + compiler_builtins::float::$mod::$cb_name(a, b) != 0 + } + }; + (@cmp_lt $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + pub fn $new_name(a: $ty, b: $ty) -> bool { + compiler_builtins::float::$mod::$cb_name(a, b) < 0 + } + }; + (@cmp_le $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + pub fn $new_name(a: $ty, b: $ty) -> bool { + compiler_builtins::float::$mod::$cb_name(a, b) <= 0 + } + }; + (@cmp_gt $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + pub fn $new_name(a: $ty, b: $ty) -> bool { + compiler_builtins::float::$mod::$cb_name(a, b) > 0 + } + }; + (@cmp_ge $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + pub fn $new_name(a: $ty, b: $ty) -> bool { + compiler_builtins::float::$mod::$cb_name(a, b) >= 0 + } + }; + (@int_binop_oflow $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + pub fn $new_name(a: $ty, b: $ty) -> ($ty, bool) { + let mut oflow = 0; + let res = compiler_builtins::int::$mod::$cb_name(a, b, &mut oflow); + (res, oflow != 0) + } + }; + + // Make division by 0 well-defined so testing is easier. + (@int_div $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + pub fn $new_name(a: $ty, b: $ty) -> $ty { + if b == 0 { + return <$ty>::MIN; + } + compiler_builtins::int::$mod::$cb_name(a, b) + } + }; + (@int_divmod $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + pub fn $new_name(a: $ty, b: $ty) -> ($ty, $ty) { + if b == 0 { + return (<$ty>::MIN, <$ty>::MIN); + } + let mut rem = 0; + let div = compiler_builtins::int::$mod::$cb_name(a, b, &mut rem); + (div, rem) + } + }; + (@int_udivmod $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + pub fn $new_name(a: $ty, b: $ty) -> ($ty, $ty) { + if b == 0 { + return (<$ty>::MIN, <$ty>::MIN); + } + let mut rem = 0; + let div = compiler_builtins::int::$mod::$cb_name(a, b, Some(&mut rem)); + (div, rem) + } + }; +} + +#[cfg(f16_enabled)] +cb_op!(@binop f16, add, __addhf3, addf16); +cb_op!(@binop f32, add, __addsf3, addf32); +cb_op!(@binop f64, add, __adddf3, addf64); +#[cfg(f128_enabled)] +cb_op!(@binop f128, add, __addtf3, addf128); + +#[cfg(f16_enabled)] +cb_op!(@binop f16, sub, __subhf3, subf16); +cb_op!(@binop f32, sub, __subsf3, subf32); +cb_op!(@binop f64, sub, __subdf3, subf64); +#[cfg(f128_enabled)] +cb_op!(@binop f128, sub, __subtf3, subf128); + +#[cfg(f16_enabled)] +cb_op!(@binop f16, mul, __mulhf3, mulf16); +cb_op!(@binop f32, mul, __mulsf3, mulf32); +cb_op!(@binop f64, mul, __muldf3, mulf64); +#[cfg(f128_enabled)] +cb_op!(@binop f128, mul, __multf3, mulf128); + +cb_op!(@binop f32, div, __divsf3, divf32); +cb_op!(@binop f64, div, __divdf3, divf64); +#[cfg(f128_enabled)] +cb_op!(@binop f128, div, __divtf3, divf128); + +cb_op!(pow, __powisf2, powif32, (a: f32, b: i32) -> f32); +cb_op!(pow, __powidf2, powif64, (a: f64, b: i32) -> f64); +#[cfg(f128_enabled)] +cb_op!(pow, __powitf2, powif128, (a: f128, b: i32) -> f128); + +#[cfg(f16_enabled)] +cb_op!(@cmp_eq f16, cmp, __eqhf2, eqf16); +cb_op!(@cmp_eq f32, cmp, __eqsf2, eqf32); +cb_op!(@cmp_eq f64, cmp, __eqdf2, eqf64); +#[cfg(f128_enabled)] +cb_op!(@cmp_eq f128, cmp, __eqtf2, eqf128); + +#[cfg(f16_enabled)] +cb_op!(@cmp_gt f16, cmp, __gthf2, gtf16); +cb_op!(@cmp_gt f32, cmp, __gtsf2, gtf32); +cb_op!(@cmp_gt f64, cmp, __gtdf2, gtf64); +#[cfg(f128_enabled)] +cb_op!(@cmp_gt f128, cmp, __gttf2, gtf128); + +#[cfg(f16_enabled)] +cb_op!(@cmp_ge f16, cmp, __gehf2, gef16); +cb_op!(@cmp_ge f32, cmp, __gesf2, gef32); +cb_op!(@cmp_ge f64, cmp, __gedf2, gef64); +#[cfg(f128_enabled)] +cb_op!(@cmp_ge f128, cmp, __getf2, gef128); + +#[cfg(f16_enabled)] +cb_op!(@cmp_lt f16, cmp, __lthf2, ltf16); +cb_op!(@cmp_lt f32, cmp, __ltsf2, ltf32); +cb_op!(@cmp_lt f64, cmp, __ltdf2, ltf64); +#[cfg(f128_enabled)] +cb_op!(@cmp_lt f128, cmp, __lttf2, ltf128); + +#[cfg(f16_enabled)] +cb_op!(@cmp_le f16, cmp, __lehf2, lef16); +cb_op!(@cmp_le f32, cmp, __lesf2, lef32); +cb_op!(@cmp_le f64, cmp, __ledf2, lef64); +#[cfg(f128_enabled)] +cb_op!(@cmp_le f128, cmp, __letf2, lef128); + +#[cfg(f16_enabled)] +cb_op!(@cmp_ne f16, cmp, __nehf2, nef16); +cb_op!(@cmp_ne f32, cmp, __nesf2, nef32); +cb_op!(@cmp_ne f64, cmp, __nedf2, nef64); +#[cfg(f128_enabled)] +cb_op!(@cmp_ne f128, cmp, __netf2, nef128); + +#[cfg(f16_enabled)] +cb_op!(@cmp_unord f16, cmp, __unordhf2, unordf16); +cb_op!(@cmp_unord f32, cmp, __unordsf2, unordf32); +cb_op!(@cmp_unord f64, cmp, __unorddf2, unordf64); +#[cfg(f128_enabled)] +cb_op!(@cmp_unord f128, cmp, __unordtf2, unordf128); + +#[cfg(f16_enabled)] +cb_op!(extend, __extendhfsf2, extend_f16_f32, (a: f16) -> f32); +#[cfg(f16_enabled)] +cb_op!(extend, __extendhfdf2, extend_f16_f64, (a: f16) -> f64); +#[cfg(f16_enabled)] +#[cfg(f128_enabled)] +cb_op!(extend, __extendhftf2, extend_f16_f128, (a: f16) -> f128); +cb_op!(extend, __extendsfdf2, extend_f32_f64, (a: f32) -> f64); +#[cfg(f128_enabled)] +cb_op!(extend, __extendsftf2, extend_f32_f128, (a: f32) -> f128); +#[cfg(f128_enabled)] +cb_op!(extend, __extenddftf2, extend_f64_f128, (a: f64) -> f128); + +// Note that these are renamed from trunc to narrow to avoid collision with libm `trunc`. +#[cfg(f16_enabled)] +cb_op!(trunc, __truncsfhf2, narrow_f32_f16, (a: f32) -> f16); +#[cfg(f16_enabled)] +cb_op!(trunc, __truncdfhf2, narrow_f64_f16, (a: f64) -> f16); +cb_op!(trunc, __truncdfsf2, narrow_f64_f32, (a: f64) -> f32); +#[cfg(f16_enabled)] +#[cfg(f128_enabled)] +cb_op!(trunc, __trunctfhf2, narrow_f128_f16, (a: f128) -> f16); +#[cfg(f128_enabled)] +cb_op!(trunc, __trunctfsf2, narrow_f128_f32, (a: f128) -> f32); +#[cfg(f128_enabled)] +cb_op!(trunc, __trunctfdf2, narrow_f128_f64, (a: f128) -> f64); + +cb_op!(conv, __fixsfsi, ftoi_f32_i32, (a: f32) -> i32); +cb_op!(conv, __fixsfdi, ftoi_f32_i64, (a: f32) -> i64); +cb_op!(conv, __fixsfti, ftoi_f32_i128, (a: f32) -> i128); +cb_op!(conv, __fixdfsi, ftoi_f64_i32, (a: f64) -> i32); +cb_op!(conv, __fixdfdi, ftoi_f64_i64, (a: f64) -> i64); +cb_op!(conv, __fixdfti, ftoi_f64_i128, (a: f64) -> i128); +#[cfg(f128_enabled)] +cb_op!(conv, __fixtfsi, ftoi_f128_i32, (a: f128) -> i32); +#[cfg(f128_enabled)] +cb_op!(conv, __fixtfdi, ftoi_f128_i64, (a: f128) -> i64); +#[cfg(f128_enabled)] +cb_op!(conv, __fixtfti, ftoi_f128_i128, (a: f128) -> i128); +cb_op!(conv, __fixunssfsi, ftoi_f32_u32, (a: f32) -> u32); +cb_op!(conv, __fixunssfdi, ftoi_f32_u64, (a: f32) -> u64); +cb_op!(conv, __fixunssfti, ftoi_f32_u128, (a: f32) -> u128); +cb_op!(conv, __fixunsdfsi, ftoi_f64_u32, (a: f64) -> u32); +cb_op!(conv, __fixunsdfdi, ftoi_f64_u64, (a: f64) -> u64); +cb_op!(conv, __fixunsdfti, ftoi_f64_u128, (a: f64) -> u128); +#[cfg(f128_enabled)] +cb_op!(conv, __fixunstfsi, ftoi_f128_u32, (a: f128) -> u32); +#[cfg(f128_enabled)] +cb_op!(conv, __fixunstfdi, ftoi_f128_u64, (a: f128) -> u64); +#[cfg(f128_enabled)] +cb_op!(conv, __fixunstfti, ftoi_f128_u128, (a: f128) -> u128); + +cb_op!(conv, __floatsisf, itof_i32_f32, (a: i32) -> f32); +cb_op!(conv, __floatdisf, itof_i64_f32, (a: i64) -> f32); +cb_op!(conv, __floattisf, itof_i128_f32, (a: i128) -> f32); +cb_op!(conv, __floatsidf, itof_i32_f64, (a: i32) -> f64); +cb_op!(conv, __floatdidf, itof_i64_f64, (a: i64) -> f64); +cb_op!(conv, __floattidf, itof_i128_f64, (a: i128) -> f64); +#[cfg(f128_enabled)] +cb_op!(conv, __floatsitf, itof_i32_f128, (a: i32) -> f128); +#[cfg(f128_enabled)] +cb_op!(conv, __floatditf, itof_i64_f128, (a: i64) -> f128); +#[cfg(f128_enabled)] +cb_op!(conv, __floattitf, itof_i128_f128, (a: i128) -> f128); +cb_op!(conv, __floatunsisf, itof_u32_f32, (a: u32) -> f32); +cb_op!(conv, __floatundisf, itof_u64_f32, (a: u64) -> f32); +cb_op!(conv, __floatuntisf, itof_u128_f32, (a: u128) -> f32); +cb_op!(conv, __floatunsidf, itof_u32_f64, (a: u32) -> f64); +cb_op!(conv, __floatundidf, itof_u64_f64, (a: u64) -> f64); +cb_op!(conv, __floatuntidf, itof_u128_f64, (a: u128) -> f64); +#[cfg(f128_enabled)] +cb_op!(conv, __floatunsitf, itof_u32_f128, (a: u32) -> f128); +#[cfg(f128_enabled)] +cb_op!(conv, __floatunditf, itof_u64_f128, (a: u64) -> f128); +#[cfg(f128_enabled)] +cb_op!(conv, __floatuntitf, itof_u128_f128, (a: u128) -> f128); + +/* int ops */ + +cb_op!(@int addsub, __rust_i128_add, iadd_i128, (a: i128, b: i128) -> i128); +cb_op!(@int addsub, __rust_i128_sub, isub_i128, (a: i128, b: i128) -> i128); +cb_op!(@int addsub, __rust_u128_add, iadd_u128, (a: u128, b: u128) -> u128); +cb_op!(@int addsub, __rust_u128_sub, isub_u128, (a: u128, b: u128) -> u128); +cb_op!(@int_binop_oflow i128, addsub, __rust_i128_addo, iaddo_i128); +cb_op!(@int_binop_oflow i128, addsub, __rust_i128_subo, isubo_i128); +cb_op!(@int_binop_oflow u128, addsub, __rust_u128_addo, iaddo_u128); +cb_op!(@int_binop_oflow u128, addsub, __rust_u128_subo, isubo_u128); + +cb_op!(@int mul, __muldi3, imul_u64, (a: u64, b: u64) -> u64); +cb_op!(@int mul, __multi3, imul_i128, (a: i128, b: i128) -> i128); +cb_op!(@int_binop_oflow i32, mul, __mulosi4, imulo_i32); +cb_op!(@int_binop_oflow i64, mul, __mulodi4, imulo_i64); +cb_op!(@int_binop_oflow i128, mul, __muloti4, imulo_i128); +cb_op!(@int_binop_oflow u128, mul, __rust_u128_mulo, imulo_u128); + +cb_op!(@int_div i32, sdiv, __divsi3, idiv_i32); +cb_op!(@int_div i64, sdiv, __divdi3, idiv_i64); +cb_op!(@int_div i128, sdiv, __divti3, idiv_i128); +cb_op!(@int_div i32, sdiv, __modsi3, imod_i32); +cb_op!(@int_div i64, sdiv, __moddi3, imod_i64); +cb_op!(@int_div i128, sdiv, __modti3, imod_i128); +cb_op!(@int_divmod i32, sdiv, __divmodsi4, idivmod_i32); +cb_op!(@int_divmod i64, sdiv, __divmoddi4, idivmod_i64); +cb_op!(@int_divmod i128, sdiv, __divmodti4, idivmod_i128); + +cb_op!(@int_div u32, udiv, __udivsi3, idiv_u32); +cb_op!(@int_div u64, udiv, __udivdi3, idiv_u64); +cb_op!(@int_div u128, udiv, __udivti3, idiv_u128); +cb_op!(@int_div u32, udiv, __umodsi3, imod_u32); +cb_op!(@int_div u64, udiv, __umoddi3, imod_u64); +cb_op!(@int_div u128, udiv, __umodti3, imod_u128); +cb_op!(@int_udivmod u32, udiv, __udivmodsi4, idivmod_u32); +cb_op!(@int_udivmod u64, udiv, __udivmoddi4, idivmod_u64); +cb_op!(@int_udivmod u128, udiv, __udivmodti4, idivmod_u128); + +cb_op!(@int shift, __ashlsi3, ashl_u32, (a: u32, b: u32) -> u32); +cb_op!(@int shift, __ashldi3, ashl_u64, (a: u64, b: u32) -> u64); +cb_op!(@int shift, __ashlti3, ashl_u128, (a: u128, b: u32) -> u128); +cb_op!(@int shift, __ashrsi3, ashr_i32, (a: i32, b: u32) -> i32); +cb_op!(@int shift, __ashrdi3, ashr_i64, (a: i64, b: u32) -> i64); +cb_op!(@int shift, __ashrti3, ashr_i128, (a: i128, b: u32) -> i128); +cb_op!(@int shift, __lshrsi3, lshr_u32, (a: u32, b: u32) -> u32); +cb_op!(@int shift, __lshrdi3, lshr_u64, (a: u64, b: u32) -> u64); +cb_op!(@int shift, __lshrti3, lshr_u128, (a: u128, b: u32) -> u128); + +cb_op!(@int leading_zeros, __clzsi2, leading_zeros_u32, (a: u32) -> usize); +cb_op!(@int leading_zeros, __clzdi2, leading_zeros_u64, (a: u64) -> usize); +cb_op!(@int leading_zeros, __clzti2, leading_zeros_u128, (a: u128) -> usize); +cb_op!(@int trailing_zeros, __ctzsi2, trailing_zeros_u32, (a: u32) -> usize); +cb_op!(@int trailing_zeros, __ctzdi2, trailing_zeros_u64, (a: u64) -> usize); +cb_op!(@int trailing_zeros, __ctzti2, trailing_zeros_u128, (a: u128) -> usize); diff --git a/library/compiler-builtins/libm-test/src/domain.rs b/library/compiler-builtins/libm-test/src/domain.rs index 94641be9b5483..0ae105f4a02d2 100644 --- a/library/compiler-builtins/libm-test/src/domain.rs +++ b/library/compiler-builtins/libm-test/src/domain.rs @@ -207,7 +207,7 @@ impl EitherPrim, Domain> { .into_prim_float()]; /// Domain for `loggamma` - const LGAMMA: [Self; 1] = Self::STRICTLY_POSITIVE; + const LGAMMA: [Self; 1] = Self::UNBOUNDED1; /// Domain for `jn` and `yn`. // FIXME: the domain should provide some sort of "reasonable range" so we don't actually test @@ -224,6 +224,47 @@ pub fn get_domain( argnum: usize, ) -> EitherPrim, Domain> { let x = match id.base_name() { + // Basic arithmetic + BaseName::Add => &EitherPrim::UNBOUNDED2[..], + BaseName::Sub => &EitherPrim::UNBOUNDED2[..], + BaseName::Mul => &EitherPrim::UNBOUNDED2[..], + BaseName::Div => &EitherPrim::UNBOUNDED2[..], + BaseName::Powi => &EitherPrim::UNBOUNDED2[..], + + // Comparison + BaseName::Eq => &EitherPrim::UNBOUNDED2[..], + BaseName::Ne => &EitherPrim::UNBOUNDED2[..], + BaseName::Gt => &EitherPrim::UNBOUNDED2[..], + BaseName::Ge => &EitherPrim::UNBOUNDED2[..], + BaseName::Lt => &EitherPrim::UNBOUNDED2[..], + BaseName::Le => &EitherPrim::UNBOUNDED2[..], + BaseName::Unord => &EitherPrim::UNBOUNDED2[..], + + // Conversions + BaseName::Extend => &EitherPrim::UNBOUNDED1[..], + BaseName::Narrow => &EitherPrim::UNBOUNDED1[..], + BaseName::Ftoi => &EitherPrim::UNBOUNDED1[..], + BaseName::Itof => &EitherPrim::UNBOUNDED1[..], + + // Integer ops + BaseName::Iadd => &EitherPrim::UNBOUNDED2[..], + BaseName::Iaddo => &EitherPrim::UNBOUNDED2[..], + BaseName::Isub => &EitherPrim::UNBOUNDED2[..], + BaseName::Isubo => &EitherPrim::UNBOUNDED2[..], + BaseName::Imul => &EitherPrim::UNBOUNDED2[..], + BaseName::Imulo => &EitherPrim::UNBOUNDED2[..], + BaseName::Idiv => &EitherPrim::UNBOUNDED2[..], + BaseName::Imod => &EitherPrim::UNBOUNDED2[..], + BaseName::Idivmod => &EitherPrim::UNBOUNDED2[..], + // Shifts technically aren't unbounded, but its range is restricted elsewhere in + // our test generators. + BaseName::Ashl => &EitherPrim::UNBOUNDED2[..], + BaseName::Ashr => &EitherPrim::UNBOUNDED2[..], + BaseName::Lshr => &EitherPrim::UNBOUNDED2[..], + BaseName::LeadingZeros => &EitherPrim::UNBOUNDED1[..], + BaseName::TrailingZeros => &EitherPrim::UNBOUNDED1[..], + + // Math functions BaseName::Acos => &EitherPrim::INVERSE_TRIG_PERIODIC[..], BaseName::Acosh => &EitherPrim::ACOSH[..], BaseName::Asin => &EitherPrim::INVERSE_TRIG_PERIODIC[..], diff --git a/library/compiler-builtins/libm-test/src/f8_impl.rs b/library/compiler-builtins/libm-test/src/f8_impl.rs index 905c7d7fde92a..fb95e279eedd6 100644 --- a/library/compiler-builtins/libm-test/src/f8_impl.rs +++ b/library/compiler-builtins/libm-test/src/f8_impl.rs @@ -25,13 +25,18 @@ impl Float for f8 { const NEG_ZERO: Self = Self(0b1_0000_000); const ONE: Self = Self(0b0_0111_000); const NEG_ONE: Self = Self(0b1_0111_000); - const MAX: Self = Self(0b0_1110_111); - const MIN: Self = Self(0b1_1110_111); const INFINITY: Self = Self(0b0_1111_000); const NEG_INFINITY: Self = Self(0b1_1111_000); + const MAX: Self = Self(0b0_1110_111); + const MIN: Self = Self(0b1_1110_111); + const NAN: Self = Self(0b0_1111_100); + const SNAN: Self = Self(0b0_1111_001); const NEG_NAN: Self = Self(0b1_1111_100); + const NEG_SNAN: Self = Self(0b1_1111_001); + const MIN_POSITIVE_NORMAL: Self = Self(1 << Self::SIG_BITS); + const MIN_POSITIVE_SUBNORMAL: Self = Self(1); // FIXME: incorrect values const EPSILON: Self = Self::ZERO; const PI: Self = Self::ZERO; @@ -44,6 +49,7 @@ impl Float for f8 { const SIG_MASK: Self::Int = 0b0_0000_111; const EXP_MASK: Self::Int = 0b0_1111_000; const IMPLICIT_BIT: Self::Int = 0b0_0001_000; + const SIG_TOP_BIT: Self::Int = Self::IMPLICIT_BIT >> 1; fn to_bits(self) -> Self::Int { self.0 @@ -53,6 +59,14 @@ impl Float for f8 { self.0 as i8 } + fn eq_repr(self, rhs: Self) -> bool { + if self.is_nan() && rhs.is_nan() { + true + } else { + self.to_bits() == rhs.to_bits() + } + } + fn is_nan(self) -> bool { self.0 & Self::EXP_MASK == Self::EXP_MASK && self.0 & Self::SIG_MASK != 0 } diff --git a/library/compiler-builtins/libm-test/src/generate.rs b/library/compiler-builtins/libm-test/src/generate.rs index da080d23fa79c..29c2b9f92236b 100644 --- a/library/compiler-builtins/libm-test/src/generate.rs +++ b/library/compiler-builtins/libm-test/src/generate.rs @@ -1,5 +1,6 @@ //! Different generators that can create random or systematic bit patterns. +pub mod bitpattern; pub mod case_list; pub mod edge_cases; pub mod random; @@ -48,3 +49,28 @@ impl Iterator for KnownSize { } impl ExactSizeIterator for KnownSize {} + +/// Yield `(a0, b0), ..., (a0, bn), ..., (an, bn)` for iterators `[a0, ..., an]` and +/// `[b0, ..., bn]`. +fn product2(i0: I0, i1: I1) -> impl Iterator +where + I0: Iterator, + I1: Iterator + Clone, +{ + i0.flat_map(move |first| i1.clone().map(move |second| (first, second))) +} + +/// Yield `(a0, b0, c0), ..., (a0, b0, cn), ..., (a0, bn, cn), ..., (an, bn, cn)` for iterators +/// `[a0, ..., an]`, `[b0, ..., bn]` and `[c0, ..., cn]`. +fn product3( + i0: I0, + i1: I1, + i2: I2, +) -> impl Iterator +where + I0: Iterator, + I1: Iterator + Clone, + I2: Iterator + Clone, +{ + product2(product2(i0, i1), i2).map(|((first, second), third)| (first, second, third)) +} diff --git a/library/compiler-builtins/libm-test/src/generate/bitpattern.rs b/library/compiler-builtins/libm-test/src/generate/bitpattern.rs new file mode 100644 index 0000000000000..45b2ff0b21acb --- /dev/null +++ b/library/compiler-builtins/libm-test/src/generate/bitpattern.rs @@ -0,0 +1,371 @@ +use libm::support::{Float, Int, MinInt}; + +/// Iterate all the bitwise subsets of the given mask. +/// +/// Produces the same sequence as `(0..=uN::MAX).filter(|x| x & !mask == 0)`, +/// but each item is generated in O(1) time. +/// +/// # Panics +/// +/// Panics if the mask has all bits set. +/// +/// # Example +/// +/// ```ignore +/// assert!(bitwise_subsets(0b1001).eq([0b0000, 0b0001, 0b1000, 0b1001])); +/// ``` +fn bitwise_subsets(mask: I) -> impl Iterator + Clone +where + I: Int, +{ + assert!( + mask != I::MAX, + "to optimize the implementation, varying every bit is not supported" + ); + let fixed = !mask; + let mut counter = fixed - I::ONE; + + // `(counter + 1) & !fixed` is initially 0, and increases after each item returned + std::iter::from_fn(move || { + counter = counter.checked_add(I::ONE)? | fixed; + Some(counter ^ fixed) + }) +} + +/// Create a bitmask with `count` ones. The ones are filled in this order: +/// +/// 1. Sign bit +/// 2. Significand low bits +/// 3. Significand high bits, exponent low bits, exponent high bits (increment together) +fn most_wanted_bitmask(count: u32) -> F::Int { + if count == 0 { + return F::Int::ZERO; + } + let mut mask = F::SIGN_MASK; + let n = (count - 1) / 4; + mask |= low_mask_bits(n, F::EXP_MASK); + mask |= high_mask_bits(n, F::EXP_MASK); + mask |= high_mask_bits(n, F::SIG_MASK); + // spend most of the remaining budget on the least significant bits, then use up remainders + mask |= low_mask_bits(count - mask.count_ones(), F::SIG_MASK); + mask |= high_mask_bits(n + count - mask.count_ones(), F::SIG_MASK); + mask |= high_mask_bits(n + count - mask.count_ones(), F::EXP_MASK); + mask |= low_mask_bits(n + count - mask.count_ones(), F::EXP_MASK); + mask +} + +/// Similar to `most_wanted_bitmask` but adds bits around the middle of the int rather than at +/// a sign/exponent/significand boundary. +fn most_wanted_int_bitmask>(count: u32) -> I { + if count == 0 { + return I::ZERO; + } + let mut mask = I::ZERO; + let n = count / 4; + + let low_mask = I::MAX >> (I::BITS / 2); + let high_mask = low_mask << (I::BITS / 2); + + mask |= low_mask_bits(n, high_mask); + mask |= high_mask_bits(n, high_mask); + mask |= high_mask_bits(n, low_mask); + // spend most of the remaining budget on the least significant bits, then use up remainders + mask |= low_mask_bits(count - mask.count_ones(), low_mask); + mask |= high_mask_bits(n + count - mask.count_ones(), low_mask); + mask |= high_mask_bits(n + count - mask.count_ones(), high_mask); + mask |= low_mask_bits(n + count - mask.count_ones(), high_mask); + mask +} + +/// Set `count` bits in the LSB of `mask`. +fn low_mask_bits(count: u32, mask: I) -> I { + mask & (mask >> (mask.count_ones().saturating_sub(count))) +} + +/// Set `count` bits in the MSB of `mask`. +fn high_mask_bits(count: u32, mask: I) -> I { + mask & (mask << (mask.count_ones().saturating_sub(count))) +} + +/// Biased generator for floats. +/// +/// Starts with the first value of `fillers`, then toggles `bits_to_vary` bits exhaustively. Once +/// that has completed, move on to the next filler. +/// +/// The returned iterator will produce `fillers.len() << bits_to_vary` items. +#[cfg_attr(not(test), expect(dead_code))] +fn float_gen( + bits_to_vary: u32, + fillers: impl IntoIterator, +) -> impl Iterator +where + F: Float, + F::Int: Int, +{ + let varying = most_wanted_bitmask::(bits_to_vary); + let patterns = bitwise_subsets(varying); + + fillers + .into_iter() + .flat_map(move |preset| patterns.clone().map(move |x| x ^ preset)) + .map(F::from_bits) +} + +/// See [`float_gen`] docs for details. +#[cfg_attr(not(test), expect(dead_code))] +fn int_gen(bits_to_vary: u32, fillers: impl IntoIterator) -> impl Iterator +where + I: Int, +{ + let varying = most_wanted_int_bitmask::(bits_to_vary); + let patterns = bitwise_subsets(varying); + + fillers + .into_iter() + .flat_map(move |preset| patterns.clone().map(move |x| x ^ preset)) +} + +#[cfg(test)] +mod test { + use super::*; + use crate::f8; + + #[test] + fn equivalence() { + // with a small integer type, we can easily verify that behaviour matches for all arguments + for mask in 0..u8::MAX { + let expect = (0..=u8::MAX).filter(|x| x & !mask == 0); + assert!(bitwise_subsets(mask).eq(expect)); + } + } + + #[test] + fn most_wanted() { + let expected8 = [ + 0b0_0000_000, + // + 0b1_0000_000, + 0b1_0000_001, + 0b1_0000_011, + 0b1_0000_111, + // + 0b1_1001_101, + 0b1_1001_111, + 0b1_1101_111, + 0b1_1111_111, + ]; + let expected32 = [ + 0b0_00000000_00000000000000000000000, + // + 0b1_00000000_00000000000000000000000, + 0b1_00000000_00000000000000000000001, + 0b1_00000000_00000000000000000000011, + 0b1_00000000_00000000000000000000111, + // + 0b1_10000001_10000000000000000000001, + 0b1_10000001_10000000000000000000011, + 0b1_10000001_10000000000000000000111, + 0b1_10000001_10000000000000000001111, + // + 0b1_11000011_11000000000000000000011, + 0b1_11000011_11000000000000000000111, + 0b1_11000011_11000000000000000001111, + 0b1_11000011_11000000000000000011111, + // + 0b1_11100111_11100000000000000000111, + 0b1_11100111_11100000000000000001111, + 0b1_11100111_11100000000000000011111, + 0b1_11100111_11100000000000000111111, + // + 0b1_11111111_11110000000000000001111, + 0b1_11111111_11110000000000000011111, + 0b1_11111111_11110000000000000111111, + 0b1_11111111_11110000000000001111111, + // + 0b1_11111111_11111000000000001111111, + 0b1_11111111_11111000000000011111111, + 0b1_11111111_11111000000000111111111, + 0b1_11111111_11111000000001111111111, + // + 0b1_11111111_11111100000001111111111, + 0b1_11111111_11111100000011111111111, + 0b1_11111111_11111100000111111111111, + 0b1_11111111_11111100001111111111111, + // + 0b1_11111111_11111110001111111111111, + 0b1_11111111_11111110011111111111111, + 0b1_11111111_11111110111111111111111, + 0b1_11111111_11111111111111111111111, + ]; + for k in 0..=8 { + let mask = most_wanted_bitmask::(k); + assert_eq!(mask, expected8[k as usize], "{k}"); + assert_eq!(mask.count_ones(), k); + } + for k in 0..=32 { + let mask = most_wanted_bitmask::(k); + assert_eq!(mask, expected32[k as usize], "{k}"); + assert_eq!(mask.count_ones(), k); + } + } + + #[test] + fn most_wanted_int() { + let expected = [ + 0b0000_0000_0000_0000, + 0b0000_0000_0000_0001, + 0b0000_0000_0000_0011, + 0b0000_0000_0000_0111, + // + 0b1000_0001_1000_0001, + 0b1000_0001_1000_0011, + 0b1000_0001_1000_0111, + 0b1000_0001_1000_1111, + // + 0b1100_0011_1100_0011, + 0b1100_0011_1100_0111, + 0b1100_0011_1100_1111, + 0b1100_0011_1101_1111, + // + 0b1110_0111_1110_0111, + 0b1110_0111_1110_1111, + 0b1110_0111_1111_1111, + 0b1111_0111_1111_1111, + // + 0b1111_1111_1111_1111, + ]; + let mut x = vec![]; + for k in 0..=16 { + let mask = most_wanted_int_bitmask::(k); + x.push(mask); + assert_eq!(mask, expected[k as usize], "{k}"); + assert_eq!(mask.count_ones(), k); + } + } + + #[test] + #[cfg(f16_enabled)] + fn gen_with_fillers() { + let expected = [ + // Filler: zeros + 0b0_00000_0000000000, + 0b0_00000_0000000001, + 0b0_00000_0000000010, + 0b0_00000_0000000011, + 0b1_00000_0000000000, + 0b1_00000_0000000001, + 0b1_00000_0000000010, + 0b1_00000_0000000011, + // Filler: ones + 0b1_11111_1111111111, + 0b1_11111_1111111110, + 0b1_11111_1111111101, + 0b1_11111_1111111100, + 0b0_11111_1111111111, + 0b0_11111_1111111110, + 0b0_11111_1111111101, + 0b0_11111_1111111100, + // Filler: pattern + 0b1_00110_1000101011, + 0b1_00110_1000101010, + 0b1_00110_1000101001, + 0b1_00110_1000101000, + 0b0_00110_1000101011, + 0b0_00110_1000101010, + 0b0_00110_1000101001, + 0b0_00110_1000101000, + ]; + let v = float_gen::(3, [0, u16::MAX, 0b1_00110_1000101011]) + .map(|x| x.to_bits()) + .collect::>(); + assert_eq!(expected.as_slice(), v); + } + + #[test] + fn gen_int_with_fillers() { + let expected = [ + // Filler: zeros + 0b0000_0000_0000_0000, + 0b0000_0000_0000_0001, + 0b0000_0000_0000_0010, + 0b0000_0000_0000_0011, + 0b0000_0000_0000_0100, + 0b0000_0000_0000_0101, + 0b0000_0000_0000_0110, + 0b0000_0000_0000_0111, + // Filler: ones + 0b1111_1111_1111_1111, + 0b1111_1111_1111_1110, + 0b1111_1111_1111_1101, + 0b1111_1111_1111_1100, + 0b1111_1111_1111_1011, + 0b1111_1111_1111_1010, + 0b1111_1111_1111_1001, + 0b1111_1111_1111_1000, + // Filler: pattern + 0b1001_1010_0010_1011, + 0b1001_1010_0010_1010, + 0b1001_1010_0010_1001, + 0b1001_1010_0010_1000, + 0b1001_1010_0010_1111, + 0b1001_1010_0010_1110, + 0b1001_1010_0010_1101, + 0b1001_1010_0010_1100, + ]; + let v = int_gen::(3, [0, u16::MAX, 0b1001_1010_0010_1011]).collect::>(); + assert_eq!(expected.as_slice(), v); + } + + #[test] + fn gen_includes_specials() { + let v: Vec<_> = float_gen(5, vec![0, 0x7fffff, !0x7fffff, !0]) + .map(f32::to_bits) + .collect(); + for x in &[ + 0.0, + f32::from_bits(1), + f32::MIN_POSITIVE, + f32::MAX, + f32::INFINITY, + f32::NAN, + ] { + assert!(v.contains(&x.to_bits()), "{x} not found"); + assert!(v.contains(&(-x).to_bits()), "-{x} not found"); + } + } + + #[test] + fn count() { + for k in 0..10 { + assert!(float_gen::(k, vec![0]).count() == 1 << k); + assert!(float_gen::(k, vec![0, !0]).count() == 2 << k); + assert!(float_gen::(k, vec![0, 1, 2]).count() == 3 << k); + } + } + + #[test] + fn specific() { + let iter = float_gen::(1, vec![0]).map(f32::to_bits); + assert!(iter.eq([0.0_f32.to_bits(), (-0.0_f32).to_bits()])); + let iter = float_gen::(1, vec![0]).map(f64::to_bits); + assert!(iter.eq([0.0_f64.to_bits(), (-0.0_f64).to_bits()])); + + let mut v: Vec<_> = float_gen::(5, vec![0]).map(f32::to_bits).collect(); + assert!(v.len() == 32); + assert!(v.is_sorted()); + v.dedup(); + assert!(v.len() == 32); + for bits in v { + assert!(bits & 0xc0c0_0001 == bits); + } + + let mut v: Vec<_> = float_gen::(5, vec![0]).map(f64::to_bits).collect(); + assert!(v.len() == 32); + assert!(v.is_sorted()); + v.dedup(); + assert!(v.len() == 32); + for bits in v { + assert!(bits & 0xc018_0000_0000_0001 == bits); + } + } +} diff --git a/library/compiler-builtins/libm-test/src/generate/case_list.rs b/library/compiler-builtins/libm-test/src/generate/case_list.rs index 43b28722f2dd2..2275787307d95 100644 --- a/library/compiler-builtins/libm-test/src/generate/case_list.rs +++ b/library/compiler-builtins/libm-test/src/generate/case_list.rs @@ -6,9 +6,11 @@ //! //! This is useful for adding regression tests or expected failures. -use libm::hf64; +#[cfg(f16_enabled)] +use libm::hf16; #[cfg(f128_enabled)] use libm::hf128; +use libm::{hf32, hf64}; use crate::{CheckBasis, CheckCtx, GeneratorKind, MathOp, op}; @@ -18,814 +20,1625 @@ pub struct TestCase { } impl TestCase { - #[expect(dead_code)] - fn append_inputs(v: &mut Vec, l: &[Op::RustArgs]) { - v.extend(l.iter().copied().map(|input| Self { - input, - output: None, - })); - } - - fn append_pairs(v: &mut Vec, l: &[(Op::RustArgs, Option)]) + /// Turn into a different operation with the same types. + fn cast(self) -> TestCase where - Op::RustRet: Copy, + Op2::RustArgs: From, + Op2::RustRet: From, { - v.extend( - l.iter() - .copied() - .map(|(input, output)| Self { input, output }), - ); + TestCase { + input: self.input.into(), + output: self.output.map(Into::into), + } } } +macro_rules! cases { + ( + $( + $(#[$($meta:tt)*])* + ($($tt:tt)*) + ),* $(,)? + ) => {{ + Vec::from_iter([ + $( + $(#[$($meta)*])* + cases!(@single $($tt)*), + )* + ]) + }}; + + // Variant without a result, which will check against MPFR. + (@single ($($arg:expr),* $(,)?), None $(,)?) => { + TestCase{ + input: ($($arg,)*), + output: None, + } + }; + + // Variant for when the result is specified. + (@single ($($arg:expr),* $(,)?), $res:expr $(,)?) => { + TestCase{ + input: ($($arg,)*), + output: Some($res), + } + }; +} + +/******************************** + * compiler-builtins test cases * + ********************************/ + +#[cfg(f16_enabled)] +fn addf16_cases() -> Vec> { + cases![] +} + +fn addf32_cases() -> Vec> { + cases![] +} + +fn addf64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn addf128_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +fn subf16_cases() -> Vec> { + cases![] +} + +fn subf32_cases() -> Vec> { + cases![] +} + +fn subf64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn subf128_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +fn mulf16_cases() -> Vec> { + cases![] +} + +fn mulf32_cases() -> Vec> { + cases![] +} + +fn mulf64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn mulf128_cases() -> Vec> { + cases![] +} + +fn divf32_cases() -> Vec> { + cases![] +} + +fn divf64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn divf128_cases() -> Vec> { + cases![] +} + +fn powif32_cases() -> Vec> { + cases![] +} + +fn powif64_cases() -> Vec> { + cases![ + // High error + ((0.9999497584118668, -5858518), 6.823250355352412e127), + ] +} + +#[cfg(f128_enabled)] +fn powif128_cases() -> Vec> { + cases![] +} + +/* comparison */ + +#[cfg(f16_enabled)] +fn eqf16_cases() -> Vec> { + cases![] +} + +fn eqf32_cases() -> Vec> { + cases![] +} + +fn eqf64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn eqf128_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +fn gtf16_cases() -> Vec> { + cases![] +} + +fn gtf32_cases() -> Vec> { + cases![] +} + +fn gtf64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn gtf128_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +fn gef16_cases() -> Vec> { + cases![] +} + +fn gef32_cases() -> Vec> { + cases![] +} + +fn gef64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn gef128_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +fn ltf16_cases() -> Vec> { + cases![] +} + +fn ltf32_cases() -> Vec> { + cases![] +} + +fn ltf64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn ltf128_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +fn lef16_cases() -> Vec> { + cases![] +} + +fn lef32_cases() -> Vec> { + cases![] +} + +fn lef64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn lef128_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +fn nef16_cases() -> Vec> { + cases![] +} + +fn nef32_cases() -> Vec> { + cases![] +} + +fn nef64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn nef128_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +fn unordf16_cases() -> Vec> { + cases![] +} + +fn unordf32_cases() -> Vec> { + cases![] +} + +fn unordf64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn unordf128_cases() -> Vec> { + cases![] +} + +/* conversion */ + +#[cfg(f16_enabled)] +fn extend_f16_f32_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +fn extend_f16_f64_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +#[cfg(f128_enabled)] +fn extend_f16_f128_cases() -> Vec> { + cases![] +} + +fn extend_f32_f64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn extend_f32_f128_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn extend_f64_f128_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +fn narrow_f32_f16_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +fn narrow_f64_f16_cases() -> Vec> { + cases![] +} + +fn narrow_f64_f32_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +#[cfg(f128_enabled)] +fn narrow_f128_f16_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn narrow_f128_f32_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn narrow_f128_f64_cases() -> Vec> { + cases![] +} + +fn ftoi_f32_i32_cases() -> Vec> { + cases![] +} + +fn ftoi_f32_i64_cases() -> Vec> { + cases![] +} + +fn ftoi_f32_i128_cases() -> Vec> { + cases![] +} + +fn ftoi_f64_i32_cases() -> Vec> { + cases![] +} + +fn ftoi_f64_i64_cases() -> Vec> { + cases![] +} + +fn ftoi_f64_i128_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn ftoi_f128_i32_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn ftoi_f128_i64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn ftoi_f128_i128_cases() -> Vec> { + cases![] +} + +fn ftoi_f32_u32_cases() -> Vec> { + cases![] +} + +fn ftoi_f32_u64_cases() -> Vec> { + cases![] +} + +fn ftoi_f32_u128_cases() -> Vec> { + cases![] +} + +fn ftoi_f64_u32_cases() -> Vec> { + cases![] +} + +fn ftoi_f64_u64_cases() -> Vec> { + cases![] +} + +fn ftoi_f64_u128_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn ftoi_f128_u32_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn ftoi_f128_u64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn ftoi_f128_u128_cases() -> Vec> { + cases![] +} + +fn itof_i32_f32_cases() -> Vec> { + cases![] +} + +fn itof_i64_f32_cases() -> Vec> { + cases![] +} + +fn itof_i128_f32_cases() -> Vec> { + cases![] +} + +fn itof_i32_f64_cases() -> Vec> { + cases![] +} + +fn itof_i64_f64_cases() -> Vec> { + cases![] +} + +fn itof_i128_f64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn itof_i32_f128_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn itof_i64_f128_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn itof_i128_f128_cases() -> Vec> { + cases![] +} + +fn itof_u32_f32_cases() -> Vec> { + cases![] +} + +fn itof_u64_f32_cases() -> Vec> { + cases![] +} + +fn itof_u128_f32_cases() -> Vec> { + cases![] +} + +fn itof_u32_f64_cases() -> Vec> { + cases![] +} + +fn itof_u64_f64_cases() -> Vec> { + cases![] +} + +fn itof_u128_f64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn itof_u32_f128_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn itof_u64_f128_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn itof_u128_f128_cases() -> Vec> { + cases![] +} + +/* int arithmetic */ + +fn iadd_i128_cases() -> Vec> { + cases![] +} + +fn iadd_u128_cases() -> Vec> { + cases![] +} + +fn iaddo_i128_cases() -> Vec> { + cases![] +} + +fn iaddo_u128_cases() -> Vec> { + cases![] +} + +fn isub_i128_cases() -> Vec> { + cases![] +} + +fn isub_u128_cases() -> Vec> { + cases![] +} + +fn isubo_i128_cases() -> Vec> { + cases![] +} + +fn isubo_u128_cases() -> Vec> { + cases![] +} + +fn idiv_i128_cases() -> Vec> { + cases![] +} + +fn idiv_i32_cases() -> Vec> { + cases![] +} + +fn idiv_i64_cases() -> Vec> { + cases![] +} + +fn idiv_u128_cases() -> Vec> { + cases![] +} + +fn idiv_u32_cases() -> Vec> { + cases![] +} + +fn idiv_u64_cases() -> Vec> { + cases![] +} + +fn idivmod_i128_cases() -> Vec> { + cases![] +} + +fn idivmod_i32_cases() -> Vec> { + cases![] +} + +fn idivmod_i64_cases() -> Vec> { + cases![] +} + +fn idivmod_u128_cases() -> Vec> { + cases![] +} + +fn idivmod_u32_cases() -> Vec> { + cases![] +} + +fn idivmod_u64_cases() -> Vec> { + cases![] +} + +fn imod_i128_cases() -> Vec> { + cases![] +} + +fn imod_i32_cases() -> Vec> { + cases![] +} + +fn imod_i64_cases() -> Vec> { + cases![] +} + +fn imod_u128_cases() -> Vec> { + cases![] +} + +fn imod_u32_cases() -> Vec> { + cases![] +} + +fn imod_u64_cases() -> Vec> { + cases![] +} + +fn imul_i128_cases() -> Vec> { + cases![] +} + +fn imul_u64_cases() -> Vec> { + cases![] +} + +fn imulo_i128_cases() -> Vec> { + cases![] +} + +fn imulo_i32_cases() -> Vec> { + cases![] +} + +fn imulo_i64_cases() -> Vec> { + cases![] +} + +fn imulo_u128_cases() -> Vec> { + cases![] +} + +/* int shifts */ + +fn ashl_u32_cases() -> Vec> { + cases![] +} + +fn ashl_u64_cases() -> Vec> { + cases![] +} + +fn ashl_u128_cases() -> Vec> { + cases![] +} + +fn ashr_i32_cases() -> Vec> { + cases![] +} + +fn ashr_i64_cases() -> Vec> { + cases![] +} + +fn ashr_i128_cases() -> Vec> { + cases![] +} + +fn lshr_u32_cases() -> Vec> { + cases![] +} + +fn lshr_u64_cases() -> Vec> { + cases![] +} + +fn lshr_u128_cases() -> Vec> { + cases![] +} + +/* int bitwise ops */ + +fn leading_zeros_u32_cases() -> Vec> { + cases![] +} + +fn leading_zeros_u64_cases() -> Vec> { + cases![] +} + +fn leading_zeros_u128_cases() -> Vec> { + cases![] +} + +fn trailing_zeros_u32_cases() -> Vec> { + cases![] +} + +fn trailing_zeros_u64_cases() -> Vec> { + cases![] +} + +fn trailing_zeros_u128_cases() -> Vec> { + cases![] +} + +/******************* + * libm test cases * + *******************/ + fn acos_cases() -> Vec> { - vec![] + cases![] } fn acosf_cases() -> Vec> { - vec![] + cases![] } fn acosh_cases() -> Vec> { - vec![] + cases![] } fn acoshf_cases() -> Vec> { - vec![] + cases![] } fn asin_cases() -> Vec> { - vec![] + cases![] } fn asinf_cases() -> Vec> { - vec![] + cases![] } -fn asinh_cases() -> Vec> { - vec![] +fn asinhf_cases() -> Vec> { + cases![ + // Failure on i586 + ((-0.37330312), -0.3651353), + ((-0.421092), -0.40954682), + ] } -fn asinhf_cases() -> Vec> { - vec![] +fn asinh_cases() -> Vec> { + cases![] } fn atan_cases() -> Vec> { - vec![] + cases![] } fn atan2_cases() -> Vec> { - vec![] + cases![] } fn atan2f_cases() -> Vec> { - vec![] + cases![] } fn atanf_cases() -> Vec> { - vec![] + cases![] } fn atanh_cases() -> Vec> { - vec![] + cases![] } fn atanhf_cases() -> Vec> { - vec![] + cases![] } fn cbrt_cases() -> Vec> { - vec![] + cases![] } fn cbrtf_cases() -> Vec> { - vec![] + cases![] } fn ceil_cases() -> Vec> { - vec![] + cases![] } fn ceilf_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn ceilf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn ceilf16_cases() -> Vec> { - vec![] + cases![] } fn copysign_cases() -> Vec> { - vec![] + cases![] } fn copysignf_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn copysignf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn copysignf16_cases() -> Vec> { - vec![] + cases![] } fn cos_cases() -> Vec> { - vec![] + cases![] } fn cosf_cases() -> Vec> { - vec![] + cases![] } fn cosh_cases() -> Vec> { - vec![] + cases![] } fn coshf_cases() -> Vec> { - vec![] + cases![] } fn erf_cases() -> Vec> { - vec![] + cases![] } fn erfc_cases() -> Vec> { - vec![] + cases![] } fn erfcf_cases() -> Vec> { - vec![] + cases![] } fn erff_cases() -> Vec> { - vec![] + cases![] } fn exp_cases() -> Vec> { - vec![] + cases![] } fn exp10_cases() -> Vec> { - vec![] + cases![] } fn exp10f_cases() -> Vec> { - vec![] + cases![] } fn exp2_cases() -> Vec> { - vec![] + cases![] } fn exp2f_cases() -> Vec> { - vec![] + cases![] } fn expf_cases() -> Vec> { - vec![] + cases![ + ((hf32!("-0x1.2d245ap-8")), hf32!("0x1.fda718p-1")), + ((hf32!("0x1.db1b7ap-7")), hf32!("0x1.03bd22p+0")), + ((hf32!("-0x1.dc15fcp+5")), hf32!("0x1.1ae6e6p-86")), + ] } fn expm1_cases() -> Vec> { - vec![] + cases![] } fn expm1f_cases() -> Vec> { - vec![] + cases![] } fn fabs_cases() -> Vec> { - vec![] + cases![] } fn fabsf_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn fabsf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn fabsf16_cases() -> Vec> { - vec![] + cases![] } fn fdim_cases() -> Vec> { - vec![] + cases![ + // Failures on i586 + ( + ( + hf64!("0x1.10d2f8a8dffd1p+355"), + hf64!("-0x1.5203b17e54a8cp+373") + ), + hf64!("0x1.5203f5b312d2fp+373") + ), + ( + ( + hf64!("0x1.9ffdf64f0d2f8p+294"), + hf64!("-0x1.71addd21280b5p+344") + ), + hf64!("0x1.71addd21280bbp+344") + ), + ( + ( + hf64!("0x1.f3600eb4ad0e0p-953"), + hf64!("-0x1.0c29b2b40023dp-976") + ), + hf64!("0x1.f36010cd00737p-953") + ), + ] } fn fdimf_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn fdimf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn fdimf16_cases() -> Vec> { - vec![] + cases![] } fn floor_cases() -> Vec> { - vec![] + cases![] } fn floorf_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn floorf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn floorf16_cases() -> Vec> { - vec![] + cases![] } -fn fma_cases() -> Vec> { - let mut v = vec![]; - TestCase::append_pairs( - &mut v, - &[ - // Previous failure with incorrect sign - ((5e-324, -5e-324, 0.0), Some(-0.0)), - ], - ); - v +#[cfg(f16_enabled)] +fn fmaf16_cases() -> Vec> { + cases![ + // Subnormal result + ((hf16!("0x1p-11"), hf16!("0x1p-11"), 0.0), None,), + ((hf16!("0x1p-24"), hf16!("0x1p-24"), 0.0), None,), + // Failed during extensive tests + ( + ( + hf16!("-0x1.c4p-12"), + hf16!("0x1.22p-14"), + hf16!("-0x1.f4p-15"), + ), + hf16!("-0x1.f48p-15") + ), + // Examples from https://github.com/llvm/llvm-project/issues/128450 + ( + ( + hf16!("0x1.400p+8"), + hf16!("0x1.008p+7"), + hf16!("0x1.000p-24"), + ), + hf16!("0x1.40cp+15") + ), + ( + (hf16!("0x1.eb8p-12"), hf16!("0x1.9p-11"), hf16!("-0x1p-11"),), + None + ), + // Previous failures during testing + ((-569.0, -4.89, 65470.0), None), + ((-998.0, 0.02596, -998.0), None), + ((6e-8, 6e-8, -6.104e-5), None), + ((6e-8, 65300.0, 9.5e-7), None), + ((-569.0, -4.89, -0.0417), None), + ((6444.0, 0.003443, 0.003443), None), + ((6e-8, 6e-8, 6e-8), None), + ((6e-8, -1.0, 6e-8), None), + ((1.001, 65500.0, 6e-8), None), + ((1.001, 65500.0, 65500.0), None), + ((1.002, 65470.0, 0.0), None), + ((1.002, 65470.0, 65500.0), None), + ((0.0002216, -8.464e-5, 4.4e-5), None), + ((-56700.0, -2.082, -61120.0), None), + ((-475.3, -475.3, 60450.0), None), + ((-61120.0, -3.969, 20320.0), None), + ((6e-8, -6e-8, 0.0), None), + ] } fn fmaf_cases() -> Vec> { - let mut v = vec![]; - TestCase::append_pairs( - &mut v, - &[ - // Known rounding error for some implementations (notably MinGW) + cases![ + // Known rounding error for some implementations (notably MinGW) + ((-1.9369631e13f32, 2.1513551e-7, -1.7354427e-24), -4167095.8), + // Failure on i586 + ( ( - (-1.9369631e13f32, 2.1513551e-7, -1.7354427e-24), - Some(-4167095.8), + hf32!("-0x1.c92494p+109"), + hf32!("-0x0.000018p-126"), + hf32!("-0x1.6db6f0p-91"), ), - ], - ); - v + hf32!("0x1.56db6ep-36") + ), + ] +} + +fn fma_cases() -> Vec> { + cases![ + // Previous failure with incorrect sign + ((5e-324, -5e-324, 0.0), -0.0), + // Failure on i586 + ( + (0.999999999999999, 1.0000000000000013, 0.0), + 1.0000000000000002 + ), + // Failure on musl i686/i586 + ( + ( + hf64!("0x0.0000000100001p-1022"), + hf64!("0x1.ffffffffffffbp+1023"), + hf64!("0x0p+0") + ), + hf64!("0x1.00000fffffffdp-30") + ) + ] } #[cfg(f128_enabled)] fn fmaf128_cases() -> Vec> { - let mut v = vec![]; - TestCase::append_pairs( - &mut v, - &[ + cases![ + ( + // Tricky rounding case that previously failed in extensive tests ( - // Tricky rounding case that previously failed in extensive tests - ( - hf128!("-0x1.1966cc01966cc01966cc01966f06p-25"), - hf128!("-0x1.669933fe69933fe69933fe6997c9p-16358"), - hf128!("-0x0.000000000000000000000000048ap-16382"), - ), - Some(hf128!("0x0.c5171470a3ff5e0f68d751491b18p-16382")), + hf128!("-0x1.1966cc01966cc01966cc01966f06p-25"), + hf128!("-0x1.669933fe69933fe69933fe6997c9p-16358"), + hf128!("-0x0.000000000000000000000000048ap-16382"), ), + hf128!("0x0.c5171470a3ff5e0f68d751491b18p-16382") + ), + ( + // Subnormal edge case that caused a failure ( - // Subnormal edge case that caused a failure - ( - hf128!("0x0.7ffffffffffffffffffffffffff7p-16382"), - hf128!("0x1.ffffffffffffffffffffffffffffp-1"), - hf128!("0x0.8000000000000000000000000009p-16382"), - ), - Some(hf128!("0x1.0000000000000000000000000000p-16382")), + hf128!("0x0.7ffffffffffffffffffffffffff7p-16382"), + hf128!("0x1.ffffffffffffffffffffffffffffp-1"), + hf128!("0x0.8000000000000000000000000009p-16382"), ), - ], - ); - v + hf128!("0x1.0000000000000000000000000000p-16382") + ), + ] } #[cfg(f16_enabled)] fn fmaxf16_cases() -> Vec> { - vec![] + cases![] } fn fmaxf_cases() -> Vec> { - vec![] + cases![] } fn fmax_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn fmaxf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn fmaximumf16_cases() -> Vec> { - vec![] + cases![] } fn fmaximumf_cases() -> Vec> { - vec![] + cases![] } fn fmaximum_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn fmaximumf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn fmaximum_numf16_cases() -> Vec> { - vec![] + cases![] } fn fmaximum_numf_cases() -> Vec> { - vec![] + cases![] } fn fmaximum_num_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn fmaximum_numf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn fminf16_cases() -> Vec> { - vec![] + cases![] } fn fminf_cases() -> Vec> { - vec![] + cases![] } fn fmin_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn fminf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn fminimumf16_cases() -> Vec> { - vec![] + cases![] } fn fminimumf_cases() -> Vec> { - vec![] + cases![] } fn fminimum_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn fminimumf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn fminimum_numf16_cases() -> Vec> { - vec![] + cases![] } fn fminimum_numf_cases() -> Vec> { - vec![] + cases![] } fn fminimum_num_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn fminimum_numf128_cases() -> Vec> { - vec![] + cases![] } fn fmod_cases() -> Vec> { - let mut v = vec![]; - TestCase::append_pairs( - &mut v, - &[ - // Previous failure with incorrect loop iteration - // - ((2.1, 3.123e-320), Some(2.0696e-320)), - ((2.1, 2.253547e-318), Some(1.772535e-318)), - ], - ); - v + cases![ + // Previous failure with incorrect loop iteration + // + ((2.1, 3.123e-320), 2.0696e-320), + ((2.1, 2.253547e-318), 1.772535e-318), + ] } fn fmodf_cases() -> Vec> { - let mut v = vec![]; - TestCase::append_pairs( - &mut v, - &[ - // Previous failure with incorrect loop iteration - // - ((2.1, 8.858e-42), Some(8.085e-42)), - ((2.1, 6.39164e-40), Some(6.1636e-40)), - ((5.5, 6.39164e-40), Some(4.77036e-40)), - ((-151.189, 6.39164e-40), Some(-5.64734e-40)), - ], - ); - v + cases![ + // Previous failure with incorrect loop iteration + // + ((2.1, 8.858e-42), 8.085e-42), + ((2.1, 6.39164e-40), 6.1636e-40), + ((5.5, 6.39164e-40), 4.77036e-40), + ((-151.189, 6.39164e-40), -5.64734e-40), + ] } #[cfg(f128_enabled)] fn fmodf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn fmodf16_cases() -> Vec> { - vec![] + cases![] } -fn frexp_cases() -> Vec> { - vec![] +#[cfg(f16_enabled)] +fn frexpf16_cases() -> Vec> { + cases![] } fn frexpf_cases() -> Vec> { - vec![] + cases![] } -fn hypot_cases() -> Vec> { - vec![] +fn frexp_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn frexpf128_cases() -> Vec> { + cases![] } fn hypotf_cases() -> Vec> { - vec![] + cases![] } -fn ilogb_cases() -> Vec> { - vec![] +fn hypot_cases() -> Vec> { + cases![ + // Cases that can overflow exponent if wrapping arithmetic is not used + ( + ( + hf64!("-0x1.800f800f80100p+1023"), + hf64!("0x1.8354835473720p+996"), + ), + None + ), + ( + (hf64!("0x1.201b201b201c0p+0"), hf64!("0x1.b028b028b02a0p-1")), + None + ), + ( + ( + hf64!("-0x1.e538e538e564p+980"), + hf64!("-0x1.c4dfc4dfc508p+983"), + ), + None + ), + ( + ( + hf64!("-0x1.2f22e4f77aa58p+983"), + hf64!("-0x1.44c9f5524c8ccp+980"), + ), + None + ), + ] +} + +#[cfg(f16_enabled)] +fn ilogbf16_cases() -> Vec> { + cases![] } fn ilogbf_cases() -> Vec> { - vec![] + cases![] +} + +fn ilogb_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn ilogbf128_cases() -> Vec> { + cases![] } fn j0_cases() -> Vec> { - vec![] + cases![] } fn j0f_cases() -> Vec> { - vec![] + cases![] } fn j1_cases() -> Vec> { - vec![] + cases![] } fn j1f_cases() -> Vec> { - vec![] + cases![] } -fn jn_cases() -> Vec> { - vec![] +fn jnf_cases() -> Vec> { + cases![] } -fn jnf_cases() -> Vec> { - vec![] +fn jn_cases() -> Vec> { + cases![ + // Inputs that produce high errors + ((190, 1005.366268038242), 7.328620335959289e-10), + ((238, -311.0349), 7.270196433535006e-8), + ] } fn ldexp_cases() -> Vec> { - vec![] + cases![] } fn ldexpf_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn ldexpf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn ldexpf16_cases() -> Vec> { - vec![] + cases![] } fn lgamma_cases() -> Vec> { - vec![] + cases![] } -fn lgamma_r_cases() -> Vec> { - vec![] +fn lgammaf_cases() -> Vec> { + cases![ + // High error + ((-4.933393,), -1.9580022), + ] } -fn lgammaf_cases() -> Vec> { - vec![] +fn lgamma_r_cases() -> Vec> { + cases![] } fn lgammaf_r_cases() -> Vec> { - vec![] + cases![] } fn log_cases() -> Vec> { - vec![] + cases![] } fn log10_cases() -> Vec> { - vec![] + cases![] } fn log10f_cases() -> Vec> { - vec![] + cases![] } -fn log1p_cases() -> Vec> { - vec![] +fn log1pf_cases() -> Vec> { + cases![ + // Musl failures on i586 + ((hf32!("-0x1.8292f6p-2")), hf32!("-0x1.e56918p-2")), + ((hf32!("0x1.12d15ep-1")), hf32!("0x1.b7fbf8p-2")), + ((hf32!("-0x1.904ebep-2")), hf32!("-0x1.fbb6cap-2")), + ] } -fn log1pf_cases() -> Vec> { - vec![] +fn log1p_cases() -> Vec> { + cases![ + // Musl failure on i586 + ( + (hf64!("-0x1.9094dbf7f2e85p-2"),), + hf64!("-0x1.fc29f046c88a1p-2") + ), + ] } fn log2_cases() -> Vec> { - vec![] + cases![] } fn log2f_cases() -> Vec> { - vec![] + cases![] } fn logf_cases() -> Vec> { - vec![] + cases![] } fn modf_cases() -> Vec> { - vec![] + cases![] } fn modff_cases() -> Vec> { - vec![] + cases![] } fn nextafter_cases() -> Vec> { - vec![] + cases![] } fn nextafterf_cases() -> Vec> { - vec![] + cases![] } fn pow_cases() -> Vec> { - vec![] + cases![] } fn powf_cases() -> Vec> { - vec![] + cases![] } fn remainder_cases() -> Vec> { - vec![] + cases![] } fn remainderf_cases() -> Vec> { - vec![] + cases![] } fn remquo_cases() -> Vec> { - vec![] + cases![] } fn remquof_cases() -> Vec> { - vec![] + cases![] } -fn rint_cases() -> Vec> { - let mut v = vec![]; - TestCase::append_pairs( - &mut v, - &[ - // Known failure on i586 - #[cfg(not(x86_no_sse))] - ( - (hf64!("-0x1.e3f13ff995ffcp+38"),), - Some(hf64!("-0x1.e3f13ff994000p+38")), - ), - #[cfg(x86_no_sse)] - ( - (hf64!("-0x1.e3f13ff995ffcp+38"),), - Some(hf64!("-0x1.e3f13ff998000p+38")), - ), - ], - ); - v +#[cfg(f16_enabled)] +fn rintf16_cases() -> Vec> { + // Out rint doesn't respect rounding modes so it is the same as roundeven + roundevenf16_cases() + .into_iter() + .map(TestCase::cast) + .collect() } fn rintf_cases() -> Vec> { - vec![] + // Out rint doesn't respect rounding modes so it is the same as roundeven + roundevenf_cases().into_iter().map(TestCase::cast).collect() } -#[cfg(f128_enabled)] -fn rintf128_cases() -> Vec> { - vec![] +fn rint_cases() -> Vec> { + // Out rint doesn't respect rounding modes so it is the same as roundeven + roundeven_cases().into_iter().map(TestCase::cast).collect() } -#[cfg(f16_enabled)] -fn rintf16_cases() -> Vec> { - vec![] +#[cfg(f128_enabled)] +fn rintf128_cases() -> Vec> { + // Out rint doesn't respect rounding modes so it is the same as roundeven + roundevenf128_cases() + .into_iter() + .map(TestCase::cast) + .collect() } #[cfg(f16_enabled)] fn roundf16_cases() -> Vec> { - vec![] + cases![] } fn round_cases() -> Vec> { - vec![] + cases![ + // Failure on i586 + ( + (hf64!("0x1.9efc6a203d4a9p+52"),), + hf64!("0x1.9efc6a203d4a9p+52") + ) + ] } fn roundf_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn roundf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn roundevenf16_cases() -> Vec> { - vec![] + cases![] } -fn roundeven_cases() -> Vec> { - let mut v = vec![]; - TestCase::append_pairs( - &mut v, - &[ - // Known failure on i586 - #[cfg(not(x86_no_sse))] - ( - (hf64!("-0x1.e3f13ff995ffcp+38"),), - Some(hf64!("-0x1.e3f13ff994000p+38")), - ), - #[cfg(x86_no_sse)] - ( - (hf64!("-0x1.e3f13ff995ffcp+38"),), - Some(hf64!("-0x1.e3f13ff998000p+38")), - ), - ], - ); - v +fn roundevenf_cases() -> Vec> { + cases![] } -fn roundevenf_cases() -> Vec> { - vec![] +fn roundeven_cases() -> Vec> { + cases![ + // Failure on i586 + ((-519629176421.49976,), -519629176421.0), + // Failures with a previous algorithm + ((-849751480.5001163,), -849751481.0), + ((-12493089.499809155,), -12493089.0), + ((-1308.5000830345912,), -1309.0), + ] } #[cfg(f128_enabled)] fn roundevenf128_cases() -> Vec> { - vec![] + cases![] } fn scalbn_cases() -> Vec> { - vec![] + cases![] } fn scalbnf_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn scalbnf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn scalbnf16_cases() -> Vec> { - vec![] + cases![] } fn sin_cases() -> Vec> { - vec![] + cases![] } fn sincos_cases() -> Vec> { - vec![] + cases![] } fn sincosf_cases() -> Vec> { - vec![] + cases![] } fn sinf_cases() -> Vec> { - vec![] + cases![] } fn sinh_cases() -> Vec> { - vec![] + cases![] } fn sinhf_cases() -> Vec> { - vec![] + cases![] } fn sqrt_cases() -> Vec> { - vec![] + cases![] } fn sqrtf_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn sqrtf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn sqrtf16_cases() -> Vec> { - vec![] + cases![] } -fn tan_cases() -> Vec> { - vec![] +fn tanf_cases() -> Vec> { + cases![] } -fn tanf_cases() -> Vec> { - vec![] +fn tan_cases() -> Vec> { + cases![ + // Musl failures on i586 + ( + (hf64!("0x1.fffffffffffafp+1023"),), + hf64!("0x1.c573c6dd8c00ap+0") + ), + ( + (hf64!("0x1.fffffffffffafp+1023"),), + hf64!("0x1.c573c6dd8c00ap+0") + ), + ( + (hf64!("-0x1.0b10f6eaf2ca0p+883"),), + hf64!("0x1.cefbd167e2402p+0") + ), + ] } fn tanh_cases() -> Vec> { - vec![] + cases![( + (hf64!("0x1.fbfdb8b31b9b4p-3"),), + hf64!("0x1.f1d2bcb4e1b45p-3") + )] } fn tanhf_cases() -> Vec> { - vec![] + cases![ + // Inaccuracy in musl + ((0.24503659,), 0.24024734), + ((0.19125812,), 0.18895969), + ] } fn tgamma_cases() -> Vec> { - vec![] + cases![] } fn tgammaf_cases() -> Vec> { - vec![] + cases![] } fn trunc_cases() -> Vec> { - vec![] + cases![] } fn truncf_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn truncf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn truncf16_cases() -> Vec> { - vec![] + cases![] } fn y0_cases() -> Vec> { - vec![] + cases![] } fn y0f_cases() -> Vec> { - vec![] + cases![] } fn y1_cases() -> Vec> { - vec![] + cases![] } fn y1f_cases() -> Vec> { - vec![] + cases![] } -fn yn_cases() -> Vec> { - vec![] +fn ynf_cases() -> Vec> { + cases![] } -fn ynf_cases() -> Vec> { - vec![] +fn yn_cases() -> Vec> { + cases![ + // Inputs that should be finite but tend to round to infinity + ((228, 120.75621), -3.3293829e38), + ((148, 61.379253), -3.2585946e38), + ((184, 87.26689), -3.2943882e38), + ] } pub trait CaseListInput: MathOp + Sized { diff --git a/library/compiler-builtins/libm-test/src/generate/edge_cases.rs b/library/compiler-builtins/libm-test/src/generate/edge_cases.rs index 4e4a782a16988..9ada6d5c95b2d 100644 --- a/library/compiler-builtins/libm-test/src/generate/edge_cases.rs +++ b/library/compiler-builtins/libm-test/src/generate/edge_cases.rs @@ -3,10 +3,9 @@ use libm::support::{CastInto, Float, Int, MinInt}; use crate::domain::get_domain; -use crate::generate::KnownSize; -use crate::op::OpITy; +use crate::generate::{KnownSize, product2, product3}; use crate::run_cfg::{check_near_count, check_point_count}; -use crate::{BaseName, CheckCtx, FloatExt, FloatTy, MathOp, test_log}; +use crate::{Arg0, Arg1, Arg2, BaseName, CheckCtx, FloatExt, MathOp, Ty, test_log}; /// Generate a sequence of edge cases, e.g. numbers near zeroes and infiniteis. pub trait EdgeCaseInput { @@ -14,15 +13,12 @@ pub trait EdgeCaseInput { } /// Create a list of values around interesting points (infinities, zeroes, NaNs). -fn float_edge_cases( +fn float_edge_cases( ctx: &CheckCtx, argnum: usize, -) -> (impl Iterator + Clone, u64) -where - Op: MathOp, -{ +) -> (impl Iterator + Clone, u64) { let mut ret = Vec::new(); - let one = OpITy::::ONE; + let one = F::Int::ONE; let values = &mut ret; let domain = get_domain::<_, i8>(ctx.fn_ident, argnum).unwrap_float(); let domain_start = domain.range_start(); @@ -32,17 +28,17 @@ where let near_points = check_near_count(ctx); // Check near some notable constants - count_up(Op::FTy::ONE, near_points, values); - count_up(Op::FTy::ZERO, near_points, values); - count_up(Op::FTy::NEG_ONE, near_points, values); - count_down(Op::FTy::ONE, near_points, values); - count_down(Op::FTy::ZERO, near_points, values); - count_down(Op::FTy::NEG_ONE, near_points, values); - values.push(Op::FTy::NEG_ZERO); + count_up(F::ONE, near_points, values); + count_up(F::ZERO, near_points, values); + count_up(F::NEG_ONE, near_points, values); + count_down(F::ONE, near_points, values); + count_down(F::ZERO, near_points, values); + count_down(F::NEG_ONE, near_points, values); + values.push(F::NEG_ZERO); // Check values near the extremes - count_up(Op::FTy::NEG_INFINITY, near_points, values); - count_down(Op::FTy::INFINITY, near_points, values); + count_up(F::NEG_INFINITY, near_points, values); + count_down(F::INFINITY, near_points, values); count_down(domain_end, near_points, values); count_up(domain_start, near_points, values); count_down(domain_start, near_points, values); @@ -50,20 +46,20 @@ where count_down(domain_end, near_points, values); // Check some special values that aren't included in the above ranges - values.push(Op::FTy::NAN); - values.push(Op::FTy::NEG_NAN); - values.extend(Op::FTy::consts().iter()); + values.push(F::NAN); + values.push(F::NEG_NAN); + values.extend(F::consts().iter()); // Check around the maximum subnormal value - let sub_max = Op::FTy::from_bits(Op::FTy::SIG_MASK); + let sub_max = F::from_bits(F::SIG_MASK); count_up(sub_max, near_points, values); count_down(sub_max, near_points, values); count_up(-sub_max, near_points, values); count_down(-sub_max, near_points, values); // Check a few values around the subnormal range - for shift in (0..Op::FTy::SIG_BITS).step_by(Op::FTy::SIG_BITS as usize / 5) { - let v = Op::FTy::from_bits(one << shift); + for shift in (0..F::SIG_BITS).step_by(F::SIG_BITS as usize / 5) { + let v = F::from_bits(one << shift); count_up(v, 2, values); count_down(v, 2, values); count_up(-v, 2, values); @@ -142,21 +138,22 @@ where if matches!(ctx.base_name, BaseName::Scalbn | BaseName::Ldexp) { assert_eq!(argnum, 1, "scalbn integer argument should be arg1"); - let (emax, emin, emin_sn) = match ctx.fn_ident.math_op().float_ty { - FloatTy::F16 => { + let (emax, emin, emin_sn) = match ctx.fn_ident.math_op().rust_sig.args[0] { + Ty::F16 => { #[cfg(not(f16_enabled))] unreachable!(); #[cfg(f16_enabled)] (f16::EXP_MAX, f16::EXP_MIN, f16::EXP_MIN_SUBNORM) } - FloatTy::F32 => (f32::EXP_MAX, f32::EXP_MIN, f32::EXP_MIN_SUBNORM), - FloatTy::F64 => (f64::EXP_MAX, f64::EXP_MIN, f64::EXP_MIN_SUBNORM), - FloatTy::F128 => { + Ty::F32 => (f32::EXP_MAX, f32::EXP_MIN, f32::EXP_MIN_SUBNORM), + Ty::F64 => (f64::EXP_MAX, f64::EXP_MIN, f64::EXP_MIN_SUBNORM), + Ty::F128 => { #[cfg(not(f128_enabled))] unreachable!(); #[cfg(f128_enabled)] (f128::EXP_MAX, f128::EXP_MIN, f128::EXP_MIN_SUBNORM) } + ty => unreachable!("expected a float first argument, got {ty}"), }; // `scalbn`/`ldexp` have their trickiest behavior around exponent limits @@ -172,6 +169,22 @@ where int_count_around((emin_sn - emax).cast(), near_points, &mut values); } + if matches!( + ctx.base_name, + BaseName::Ashl | BaseName::Ashr | BaseName::Lshr + ) { + // Don't test shift values that are allowed to invoke UB. + let max = match ctx.fn_ident.math_op().rust_sig.args[0] { + Ty::U32 | Ty::I32 => 31, + Ty::U64 | Ty::I64 => 63, + Ty::U128 | Ty::I128 => 127, + ty => panic!("unexpected type {ty}"), + }; + let max: I = max.cast(); + int_count_around(max, near_points, &mut values); + values.retain(|v| *v <= max); + } + values.sort(); values.dedup(); let count = values.len().try_into().unwrap(); @@ -213,10 +226,10 @@ macro_rules! impl_edge_case_input { ($fty:ty) => { impl EdgeCaseInput for ($fty,) where - Op: MathOp, + Op: MathOp, { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { - let (iter0, steps0) = float_edge_cases::(ctx, 0); + let (iter0, steps0) = float_edge_cases::>(ctx, 0); let iter0 = iter0.map(|v| (v,)); (iter0, steps0) } @@ -224,37 +237,28 @@ macro_rules! impl_edge_case_input { impl EdgeCaseInput for ($fty, $fty) where - Op: MathOp, + Op: MathOp, { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { - let (iter0, steps0) = float_edge_cases::(ctx, 0); - let (iter1, steps1) = float_edge_cases::(ctx, 1); - let iter = - iter0.flat_map(move |first| iter1.clone().map(move |second| (first, second))); - let count = steps0.checked_mul(steps1).unwrap(); + let (iter0, steps0) = float_edge_cases::>(ctx, 0); + let (iter1, steps1) = float_edge_cases::>(ctx, 1); + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); (iter, count) } } impl EdgeCaseInput for ($fty, $fty, $fty) where - Op: MathOp, + Op: MathOp, { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { - let (iter0, steps0) = float_edge_cases::(ctx, 0); - let (iter1, steps1) = float_edge_cases::(ctx, 1); - let (iter2, steps2) = float_edge_cases::(ctx, 2); - - let iter = iter0 - .flat_map(move |first| iter1.clone().map(move |second| (first, second))) - .flat_map(move |(first, second)| { - iter2.clone().map(move |third| (first, second, third)) - }); - let count = steps0 - .checked_mul(steps1) - .unwrap() - .checked_mul(steps2) - .unwrap(); + let (iter0, steps0) = float_edge_cases::>(ctx, 0); + let (iter1, steps1) = float_edge_cases::>(ctx, 1); + let (iter2, steps2) = float_edge_cases::>(ctx, 2); + + let iter = product3(iter0, iter1, iter2); + let count = steps0.strict_mul(steps1).strict_mul(steps2); (iter, count) } @@ -262,15 +266,14 @@ macro_rules! impl_edge_case_input { impl EdgeCaseInput for (i32, $fty) where - Op: MathOp, + Op: MathOp, { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { let (iter0, steps0) = int_edge_cases(ctx, 0); - let (iter1, steps1) = float_edge_cases::(ctx, 1); + let (iter1, steps1) = float_edge_cases::>(ctx, 1); - let iter = - iter0.flat_map(move |first| iter1.clone().map(move |second| (first, second))); - let count = steps0.checked_mul(steps1).unwrap(); + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); (iter, count) } @@ -278,15 +281,14 @@ macro_rules! impl_edge_case_input { impl EdgeCaseInput for ($fty, i32) where - Op: MathOp, + Op: MathOp, { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { - let (iter0, steps0) = float_edge_cases::(ctx, 0); + let (iter0, steps0) = float_edge_cases::>(ctx, 0); let (iter1, steps1) = int_edge_cases(ctx, 1); - let iter = - iter0.flat_map(move |first| iter1.clone().map(move |second| (first, second))); - let count = steps0.checked_mul(steps1).unwrap(); + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); (iter, count) } @@ -301,6 +303,57 @@ impl_edge_case_input!(f64); #[cfg(f128_enabled)] impl_edge_case_input!(f128); +macro_rules! impl_edge_case_input_int { + (@skip_u32 $ity:ty) => { + impl EdgeCaseInput for ($ity,) + where + Op: MathOp, + { + fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { + let (iter0, steps0) = int_edge_cases(ctx, 0); + let iter0 = iter0.map(|v| (v,)); + (iter0, steps0) + } + } + + impl EdgeCaseInput for ($ity, $ity) + where + Op: MathOp, + { + fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { + let (iter0, steps0) = int_edge_cases(ctx, 0); + let (iter1, steps1) = int_edge_cases(ctx, 1); + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); + (iter, count) + } + } + }; + ($ity:ty) => { + impl_edge_case_input_int!(@skip_u32 $ity); + + impl EdgeCaseInput for ($ity, u32) + where + Op: MathOp, + { + fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { + let (iter0, steps0) = int_edge_cases(ctx, 0); + let (iter1, steps1) = int_edge_cases(ctx, 1); + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); + (iter, count) + } + } + }; +} + +impl_edge_case_input_int!(i32); +impl_edge_case_input_int!(i64); +impl_edge_case_input_int!(i128); +impl_edge_case_input_int!(@skip_u32 u32); +impl_edge_case_input_int!(u64); +impl_edge_case_input_int!(u128); + pub fn get_test_cases( ctx: &CheckCtx, ) -> (impl Iterator + Send + use<'_, Op>, u64) diff --git a/library/compiler-builtins/libm-test/src/generate/random.rs b/library/compiler-builtins/libm-test/src/generate/random.rs index 4ee88946d8eaf..b6cd315ef34c1 100644 --- a/library/compiler-builtins/libm-test/src/generate/random.rs +++ b/library/compiler-builtins/libm-test/src/generate/random.rs @@ -2,15 +2,17 @@ use std::env; use std::ops::RangeInclusive; use std::sync::LazyLock; -use libm::support::Float; +use libm::support::{Float, Int}; +use rand::distr::uniform::SampleUniform; use rand::distr::{Alphanumeric, StandardUniform}; use rand::prelude::Distribution; -use rand::{Rng, SeedableRng}; +use rand::{RngExt, SeedableRng}; use rand_chacha::ChaCha8Rng; -use super::KnownSize; use crate::CheckCtx; -use crate::run_cfg::{int_range, iteration_count}; +use crate::generate::{KnownSize, product2, product3}; +use crate::num::full_range; +use crate::run_cfg::{arg_max_iterations, int_range}; pub(crate) const SEED_ENV: &str = "LIBM_SEED"; @@ -31,7 +33,7 @@ pub trait RandomInput: Sized { } /// Generate a sequence of deterministically random floats. -fn random_floats(count: u64) -> impl Iterator +fn random_floats(count: u64) -> impl Iterator + Clone where StandardUniform: Distribution, { @@ -43,16 +45,19 @@ where } /// Generate a sequence of deterministically random `i32`s within a specified range. -fn random_ints(count: u64, range: RangeInclusive) -> impl Iterator { +fn random_ints(count: u64, range: RangeInclusive) -> impl Iterator + Clone +where + I: Int + SampleUniform, +{ let mut rng = ChaCha8Rng::from_seed(*SEED); - (0..count).map(move |_| rng.random_range::(range.clone())) + (0..count).map(move |_| rng.random_range::(range.clone())) } macro_rules! impl_random_input { ($fty:ty) => { impl RandomInput for ($fty,) { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { - let count = iteration_count(ctx, 0); + let count = arg_max_iterations(ctx, 0); let iter = random_floats(count).map(|f: $fty| (f,)); (iter, count) } @@ -60,48 +65,53 @@ macro_rules! impl_random_input { impl RandomInput for ($fty, $fty) { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { - let count0 = iteration_count(ctx, 0); - let count1 = iteration_count(ctx, 1); - let iter = random_floats(count0) - .flat_map(move |f1: $fty| random_floats(count1).map(move |f2: $fty| (f1, f2))); - (iter, count0 * count1) + let count0 = arg_max_iterations(ctx, 0); + let count1 = arg_max_iterations(ctx, 1); + let iter0 = random_floats(count0); + let iter1 = random_floats(count1); + let iter = product2(iter0, iter1); + let count = count0.strict_mul(count1); + (iter, count) } } impl RandomInput for ($fty, $fty, $fty) { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { - let count0 = iteration_count(ctx, 0); - let count1 = iteration_count(ctx, 1); - let count2 = iteration_count(ctx, 2); - let iter = random_floats(count0).flat_map(move |f1: $fty| { - random_floats(count1).flat_map(move |f2: $fty| { - random_floats(count2).map(move |f3: $fty| (f1, f2, f3)) - }) - }); - (iter, count0 * count1 * count2) + let count0 = arg_max_iterations(ctx, 0); + let count1 = arg_max_iterations(ctx, 1); + let count2 = arg_max_iterations(ctx, 2); + let iter0 = random_floats(count0); + let iter1 = random_floats(count1); + let iter2 = random_floats(count2); + let iter = product3(iter0, iter1, iter2); + let count = count0.strict_mul(count1).strict_mul(count2); + (iter, count) } } impl RandomInput for (i32, $fty) { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { - let count0 = iteration_count(ctx, 0); - let count1 = iteration_count(ctx, 1); - let range0 = int_range(ctx, 0); - let iter = random_ints(count0, range0) - .flat_map(move |f1: i32| random_floats(count1).map(move |f2: $fty| (f1, f2))); - (iter, count0 * count1) + let count0 = arg_max_iterations(ctx, 0); + let count1 = arg_max_iterations(ctx, 1); + let range0 = int_range::(ctx, 0).unwrap_or(full_range()); + let iter0 = random_ints(count0, range0); + let iter1 = random_floats(count1); + let iter = product2(iter0, iter1); + let count = count0.strict_mul(count1); + (iter, count) } } impl RandomInput for ($fty, i32) { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { - let count0 = iteration_count(ctx, 0); - let count1 = iteration_count(ctx, 1); - let range1 = int_range(ctx, 1); - let iter = random_floats(count0).flat_map(move |f1: $fty| { - random_ints(count1, range1.clone()).map(move |f2: i32| (f1, f2)) - }); - (iter, count0 * count1) + let count0 = arg_max_iterations(ctx, 0); + let count1 = arg_max_iterations(ctx, 1); + let range1 = int_range::(ctx, 1).unwrap_or(full_range()); + let iter0 = random_floats(count0); + let iter1 = random_ints(count1, range1.clone()); + let iter = product2(iter0, iter1); + let count = count0.strict_mul(count1); + (iter, count) } } }; @@ -114,6 +124,55 @@ impl_random_input!(f64); #[cfg(f128_enabled)] impl_random_input!(f128); +macro_rules! impl_random_input_int { + (@skip_u32 $ity:ty) => { + impl RandomInput for ($ity,) { + fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { + let count = arg_max_iterations(ctx, 0); + let range = int_range::<$ity>(ctx, 0).unwrap_or(full_range()); + let iter = random_ints(count, range).map(|f: $ity| (f,)); + (iter, count) + } + } + + impl RandomInput for ($ity, $ity) { + fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { + let count0 = arg_max_iterations(ctx, 0); + let count1 = arg_max_iterations(ctx, 1); + let range0 = int_range::<$ity>(ctx, 0).unwrap_or(full_range()); + let range1 = int_range::<$ity>(ctx, 1).unwrap_or(full_range()); + let iter0 = random_ints(count0, range0); + let iter1 = random_ints(count1, range1.clone()); + let iter = product2(iter0, iter1); + (iter, count0 * count1) + } + } + }; + ($ity:ty) => { + impl_random_input_int!(@skip_u32 $ity); + + impl RandomInput for ($ity, u32) { + fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { + let count0 = arg_max_iterations(ctx, 0); + let count1 = arg_max_iterations(ctx, 1); + let range0 = int_range::<$ity>(ctx, 0).unwrap_or(full_range()); + let range1 = int_range::(ctx, 1).unwrap_or(full_range()); + let iter0 = random_ints(count0, range0); + let iter1 = random_ints(count1, range1.clone()); + let iter = product2(iter0, iter1); + (iter, count0 * count1) + } + } + }; +} + +impl_random_input_int!(i32); +impl_random_input_int!(i64); +impl_random_input_int!(i128); +impl_random_input_int!(@skip_u32 u32); +impl_random_input_int!(u64); +impl_random_input_int!(u128); + /// Create a test case iterator. pub fn get_test_cases( ctx: &CheckCtx, diff --git a/library/compiler-builtins/libm-test/src/generate/spaced.rs b/library/compiler-builtins/libm-test/src/generate/spaced.rs index 8e6b376ebd1e9..051dd2687d8cb 100644 --- a/library/compiler-builtins/libm-test/src/generate/spaced.rs +++ b/library/compiler-builtins/libm-test/src/generate/spaced.rs @@ -1,12 +1,13 @@ use std::fmt; use std::ops::RangeInclusive; -use libm::support::{Float, MinInt}; +use libm::support::{Float, Int, MinInt}; use crate::domain::get_domain; -use crate::op::OpITy; -use crate::run_cfg::{int_range, iteration_count}; -use crate::{CheckCtx, MathOp, linear_ints, logspace}; +use crate::generate::{product2, product3}; +use crate::num::full_range; +use crate::run_cfg::{arg_max_iterations, int_range}; +use crate::{Arg0, Arg1, Arg2, CheckCtx, MathOp, linear_ints, logspace}; /// Generate a sequence of inputs that eiher cover the domain in completeness (for smaller float /// types and single argument functions) or provide evenly spaced inputs across the domain with @@ -17,23 +18,23 @@ pub trait SpacedInput { /// Construct an iterator from `logspace` and also calculate the total number of steps expected /// for that iterator. -fn logspace_steps( +fn logspace_steps( ctx: &CheckCtx, argnum: usize, max_steps: u64, -) -> (impl Iterator + Clone, u64) +) -> (impl Iterator + Clone, u64) where - Op: MathOp, - OpITy: TryFrom, - u64: TryFrom, Error: fmt::Debug>, - RangeInclusive>: Iterator, + F: Float, + F::Int: TryFrom, + u64: TryFrom, + RangeInclusive: Iterator, { // i8 is a dummy type here, it can be any integer. - let domain = get_domain::(ctx.fn_ident, argnum).unwrap_float(); + let domain = get_domain::(ctx.fn_ident, argnum).unwrap_float(); let start = domain.range_start(); let end = domain.range_end(); - let max_steps = OpITy::::try_from(max_steps).unwrap_or(OpITy::::MAX); + let max_steps = F::Int::try_from(max_steps).unwrap_or(F::Int::MAX); let (iter, steps) = logspace(start, end, max_steps); // `steps` will be <= the original `max_steps`, which is a `u64`. @@ -66,174 +67,194 @@ impl, B: Iterator> Iterator for EitherIter() -> Option +fn total_value_count() -> Option where u64: TryFrom, { - u64::try_from(F::Int::MAX) + total_value_count_int::() +} + +fn total_value_count_int() -> Option +where + u64: TryFrom, +{ + u64::try_from(I::MAX.abs_diff(I::MIN)) .ok() .and_then(|max| max.checked_add(1)) } /// Returns an iterator of every possible value of type `F`. -fn all_values() -> impl Iterator +fn exhaustive_float() -> (impl Iterator + Clone, u64) where + u64: TryFrom, RangeInclusive: Iterator, { - (F::Int::MIN..=F::Int::MAX).map(|bits| F::from_bits(bits)) + let count = total_value_count::().expect("tried exhaustive with > u64::MAX items"); + let iter = (F::Int::MIN..=F::Int::MAX).map(|bits| F::from_bits(bits)); + (iter, count) } macro_rules! impl_spaced_input { ($fty:ty) => { impl SpacedInput for ($fty,) where - Op: MathOp, + Op: MathOp, { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { - let max_steps0 = iteration_count(ctx, 0); - // `f16` and `f32` can have exhaustive tests. - match value_count::() { - Some(steps0) if steps0 <= max_steps0 => { - let iter0 = all_values(); - let iter0 = iter0.map(|v| (v,)); - (EitherIter::A(iter0), steps0) - } - _ => { - let (iter0, steps0) = logspace_steps::(ctx, 0, max_steps0); - let iter0 = iter0.map(|v| (v,)); - (EitherIter::B(iter0), steps0) - } + let max_steps0 = arg_max_iterations(ctx, 0); + + // Unary tests: `f16` and `f32` may be exhaustive. + if let Some(exhaustive_steps0) = total_value_count::>() + && exhaustive_steps0 <= max_steps0 + { + let (iter0, steps0) = exhaustive_float(); + let iter0 = iter0.map(|v| (v,)); + + return (EitherIter::A(iter0), steps0); } + + // Non-exhaustive, sweep a subset of inputs. + let (iter0, steps0) = logspace_steps::>(ctx, 0, max_steps0); + let iter0 = iter0.map(|v| (v,)); + (EitherIter::B(iter0), steps0) } } impl SpacedInput for ($fty, $fty) where - Op: MathOp, + Op: MathOp, { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { - let max_steps0 = iteration_count(ctx, 0); - let max_steps1 = iteration_count(ctx, 1); - // `f16` can have exhaustive tests. - match value_count::() { - Some(count) if count <= max_steps0 && count <= max_steps1 => { - let iter = all_values() - .flat_map(|first| all_values().map(move |second| (first, second))); - (EitherIter::A(iter), count.checked_mul(count).unwrap()) - } - _ => { - let (iter0, steps0) = logspace_steps::(ctx, 0, max_steps0); - let (iter1, steps1) = logspace_steps::(ctx, 1, max_steps1); - let iter = iter0.flat_map(move |first| { - iter1.clone().map(move |second| (first, second)) - }); - let count = steps0.checked_mul(steps1).unwrap(); - (EitherIter::B(iter), count) - } + let max_steps0 = arg_max_iterations(ctx, 0); + let max_steps1 = arg_max_iterations(ctx, 1); + + // Binary test: `f16` may be exhaustive. + if let Some(exhaustive_steps0) = total_value_count::>() + && exhaustive_steps0 <= max_steps0 + && let Some(exhaustive_steps1) = total_value_count::>() + && exhaustive_steps1 <= max_steps1 + { + let (iter0, steps0) = exhaustive_float(); + let (iter1, steps1) = exhaustive_float(); + + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); + + return (EitherIter::A(iter), count); } + + // Non-exhaustive, sweep a subset of inputs. + let (iter0, steps0) = logspace_steps::>(ctx, 0, max_steps0); + let (iter1, steps1) = logspace_steps::>(ctx, 1, max_steps1); + + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); + + (EitherIter::B(iter), count) } } impl SpacedInput for ($fty, $fty, $fty) where - Op: MathOp, + Op: MathOp, { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { - let max_steps0 = iteration_count(ctx, 0); - let max_steps1 = iteration_count(ctx, 1); - let max_steps2 = iteration_count(ctx, 2); - // `f16` can be exhaustive tested if `LIBM_EXTENSIVE_TESTS` is incresed. - match value_count::() { - Some(count) - if count <= max_steps0 && count <= max_steps1 && count <= max_steps2 => - { - let iter = all_values().flat_map(|first| { - all_values().flat_map(move |second| { - all_values().map(move |third| (first, second, third)) - }) - }); - (EitherIter::A(iter), count.checked_pow(3).unwrap()) - } - _ => { - let (iter0, steps0) = logspace_steps::(ctx, 0, max_steps0); - let (iter1, steps1) = logspace_steps::(ctx, 1, max_steps1); - let (iter2, steps2) = logspace_steps::(ctx, 2, max_steps2); - - let iter = iter0 - .flat_map(move |first| iter1.clone().map(move |second| (first, second))) - .flat_map(move |(first, second)| { - iter2.clone().map(move |third| (first, second, third)) - }); - let count = steps0 - .checked_mul(steps1) - .unwrap() - .checked_mul(steps2) - .unwrap(); - - (EitherIter::B(iter), count) - } + let max_steps0 = arg_max_iterations(ctx, 0); + let max_steps1 = arg_max_iterations(ctx, 1); + let max_steps2 = arg_max_iterations(ctx, 2); + + // Ternary test: `f16` may be exhaustive tested if `LIBM_EXTENSIVE_TESTS` + // is incresed. + if let Some(exhaustive_steps0) = total_value_count::>() + && exhaustive_steps0 <= max_steps0 + && let Some(exhaustive_steps1) = total_value_count::>() + && exhaustive_steps1 <= max_steps1 + && let Some(exhaustive_steps2) = total_value_count::>() + && exhaustive_steps2 <= max_steps2 + { + let (iter0, steps0) = exhaustive_float(); + let (iter1, steps1) = exhaustive_float(); + let (iter2, steps2) = exhaustive_float(); + + let iter = product3(iter0, iter1, iter2); + let count = steps0.strict_mul(steps1).strict_mul(steps2); + + return (EitherIter::A(iter), count); } + + // Non-exhaustive, sweep a subset of inputs. + let (iter0, steps0) = logspace_steps::>(ctx, 0, max_steps0); + let (iter1, steps1) = logspace_steps::>(ctx, 1, max_steps1); + let (iter2, steps2) = logspace_steps::>(ctx, 2, max_steps2); + + let iter = product3(iter0, iter1, iter2); + let count = steps0.strict_mul(steps1).strict_mul(steps2); + + (EitherIter::B(iter), count) } } impl SpacedInput for (i32, $fty) where - Op: MathOp, + Op: MathOp, { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { - let range0 = int_range(ctx, 0); - let max_steps0 = iteration_count(ctx, 0); - let max_steps1 = iteration_count(ctx, 1); - match value_count::() { - Some(count1) if count1 <= max_steps1 => { - let (iter0, steps0) = linear_ints(range0, max_steps0); - let iter = iter0 - .flat_map(move |first| all_values().map(move |second| (first, second))); - (EitherIter::A(iter), steps0.checked_mul(count1).unwrap()) - } - _ => { - let (iter0, steps0) = linear_ints(range0, max_steps0); - let (iter1, steps1) = logspace_steps::(ctx, 1, max_steps1); - - let iter = iter0.flat_map(move |first| { - iter1.clone().map(move |second| (first, second)) - }); - let count = steps0.checked_mul(steps1).unwrap(); - - (EitherIter::B(iter), count) - } + let range0 = int_range(ctx, 0).unwrap_or(full_range()); + let max_steps0 = arg_max_iterations(ctx, 0); + let max_steps1 = arg_max_iterations(ctx, 1); + + if let Some(exhaustive_steps0) = total_value_count_int::>() + && exhaustive_steps0 <= max_steps0 + && let Some(exhaustive_steps1) = total_value_count::>() + && exhaustive_steps1 <= max_steps1 + { + let (iter0, steps0) = linear_ints(range0, max_steps0); + let (iter1, steps1) = exhaustive_float(); + + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); + + return (EitherIter::A(iter), count); } + + let (iter0, steps0) = linear_ints(range0, max_steps0); + let (iter1, steps1) = logspace_steps::>(ctx, 1, max_steps1); + + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); + + (EitherIter::B(iter), count) } } impl SpacedInput for ($fty, i32) where - Op: MathOp, + Op: MathOp, { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { - let max_steps0 = iteration_count(ctx, 0); - let range1 = int_range(ctx, 1); - let max_steps1 = iteration_count(ctx, 1); - match value_count::() { - Some(count0) if count0 <= max_steps0 => { - let (iter1, steps1) = linear_ints(range1, max_steps1); - let iter = all_values().flat_map(move |first| { - iter1.clone().map(move |second| (first, second)) - }); - (EitherIter::A(iter), count0.checked_mul(steps1).unwrap()) - } - _ => { - let (iter0, steps0) = logspace_steps::(ctx, 0, max_steps0); - let (iter1, steps1) = linear_ints(range1, max_steps1); - - let iter = iter0.flat_map(move |first| { - iter1.clone().map(move |second| (first, second)) - }); - let count = steps0.checked_mul(steps1).unwrap(); - - (EitherIter::B(iter), count) - } + let max_steps0 = arg_max_iterations(ctx, 0); + let range1 = int_range(ctx, 1).unwrap_or(full_range()); + let max_steps1 = arg_max_iterations(ctx, 1); + + if let Some(exhaustive_steps0) = total_value_count::>() + && exhaustive_steps0 <= max_steps0 + { + let (iter0, steps0) = exhaustive_float(); + let (iter1, steps1) = linear_ints(range1, max_steps1); + + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); + + return (EitherIter::A(iter), count); } + + let (iter0, steps0) = logspace_steps::>(ctx, 0, max_steps0); + let (iter1, steps1) = linear_ints(range1, max_steps1); + + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); + + (EitherIter::B(iter), count) } } }; @@ -246,6 +267,102 @@ impl_spaced_input!(f64); #[cfg(f128_enabled)] impl_spaced_input!(f128); +macro_rules! impl_spaced_input_int { + (@skip_u32 $ity:ty) => { + impl SpacedInput for ($ity,) + where + Op: MathOp, + { + fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { + let range = int_range(ctx, 0).unwrap_or(full_range()); + let max_steps0 = arg_max_iterations(ctx, 0); + + if let Some(steps0) = total_value_count_int::>() + && steps0 <= max_steps0 + { + let iter0 = range.map(|v| (v,)); + return (EitherIter::A(iter0), steps0); + } + + let (iter0, steps0) = linear_ints::>(range, max_steps0); + let iter0 = iter0.map(|v| (v,)); + (EitherIter::B(iter0), steps0) + } + } + + impl SpacedInput for ($ity, $ity) + where + Op: MathOp, + { + fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { + let range0 = int_range(ctx, 0).unwrap_or(full_range()); + let range1 = int_range(ctx, 1).unwrap_or(full_range()); + let max_steps0 = arg_max_iterations(ctx, 0); + let max_steps1 = arg_max_iterations(ctx, 0); + + if let Some(steps0) = total_value_count_int::>() + && steps0 <= max_steps0 + && let Some(steps1) = total_value_count_int::>() + && steps1 <= max_steps1 + { + let iter = product2(range0, range1); + let count = steps0.strict_mul(steps1); + + return (EitherIter::A(iter), count); + } + + let (iter0, steps0) = linear_ints::>(range0, max_steps0); + let (iter1, steps1) = linear_ints::>(range1, max_steps1); + + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); + + (EitherIter::B(iter), count) + } + } + }; + ($ity:ty) => { + impl_spaced_input_int!(@skip_u32 $ity); + + impl SpacedInput for ($ity, u32) + where + Op: MathOp, + { + fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { + let range0 = int_range(ctx, 0).unwrap_or(full_range()); + let range1 = int_range(ctx, 1).unwrap_or(full_range()); + let max_steps0 = arg_max_iterations(ctx, 0); + let max_steps1 = arg_max_iterations(ctx, 0); + + if let Some(steps0) = total_value_count_int::>() + && steps0 <= max_steps0 + && let Some(steps1) = total_value_count_int::>() + && steps1 <= max_steps1 + { + let iter = product2(range0, range1); + let count = steps0.strict_mul(steps1); + + return (EitherIter::A(iter), count); + } + + let (iter0, steps0) = linear_ints::>(range0, max_steps0); + let (iter1, steps1) = linear_ints::>(range1, max_steps1); + + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); + (EitherIter::B(iter), count) + } + } + }; +} + +impl_spaced_input_int!(i32); +impl_spaced_input_int!(i64); +impl_spaced_input_int!(i128); +impl_spaced_input_int!(@skip_u32 u32); +impl_spaced_input_int!(u64); +impl_spaced_input_int!(u128); + /// Create a test case iterator for extensive inputs. Also returns the total test case count. pub fn get_test_cases( ctx: &CheckCtx, diff --git a/library/compiler-builtins/libm-test/src/lib.rs b/library/compiler-builtins/libm-test/src/lib.rs index accb39654d15a..f2ee03252139e 100644 --- a/library/compiler-builtins/libm-test/src/lib.rs +++ b/library/compiler-builtins/libm-test/src/lib.rs @@ -1,7 +1,9 @@ #![cfg_attr(f16_enabled, feature(f16))] #![cfg_attr(f128_enabled, feature(f128))] #![allow(clippy::unusual_byte_groupings)] // sometimes we group by sign_exp_sig +#![allow(unstable_name_collisions)] // FIXME(float_bits_const): remove when stable +pub mod builtins_wrapper; pub mod domain; mod f8_impl; pub mod generate; @@ -24,8 +26,8 @@ pub use f8_impl::{f8, hf8}; pub use libm::support::{Float, Int, IntTy, MinInt}; pub use num::{FloatExt, linear_ints, logspace}; pub use op::{ - BaseName, FloatTy, Identifier, MathOp, OpCFn, OpCRet, OpFTy, OpRustArgs, OpRustFn, OpRustRet, - Ty, + Arg0, Arg1, Arg2, BaseName, Group, Identifier, MathOp, OpCFn, OpCRet, OpRustArgs, OpRustFn, + OpRustRet, Ret0, Ret1, Ty, }; pub use precision::{MaybeOverride, SpecialCase, default_ulp}; use run_cfg::extensive_max_iterations; @@ -33,7 +35,7 @@ pub use run_cfg::{ CheckBasis, CheckCtx, EXTENSIVE_ENV, GeneratorKind, bigint_fuzz_iteration_count, skip_extensive_test, }; -pub use test_traits::{CheckOutput, Hex, TupleCall}; +pub use test_traits::{CheckOutput, Tuple, TupleCall}; /// Result type for tests is usually from `anyhow`. Most times there is no success value to /// propagate. diff --git a/library/compiler-builtins/libm-test/src/mpfloat.rs b/library/compiler-builtins/libm-test/src/mpfloat.rs index 9b51dc6051d03..69c6590d3763b 100644 --- a/library/compiler-builtins/libm-test/src/mpfloat.rs +++ b/library/compiler-builtins/libm-test/src/mpfloat.rs @@ -6,12 +6,14 @@ use std::cmp::Ordering; use rug::Assign; -pub use rug::Float as MpFloat; -use rug::az::{self, Az}; +use rug::az::{self, Az, CheckedCast, OverflowingCast, WrappingAs}; use rug::float::Round::Nearest; -use rug::ops::{PowAssignRound, RemAssignRound}; +use rug::ops::{ + AddAssignRound, DivAssignRound, MulAssignRound, PowAssignRound, RemAssignRound, SubAssignRound, +}; +pub use rug::{Float as MpFloat, Integer as MpInt}; -use crate::{Float, MathOp}; +use crate::{Arg0, Arg1, Arg2, Float, MathOp, Ret0, Ret1}; /// Create a multiple-precision float with the correct number of bits for a concrete float type. fn new_mpfloat() -> MpFloat { @@ -19,7 +21,7 @@ fn new_mpfloat() -> MpFloat { } /// Set subnormal emulation and convert to a concrete float type. -fn prep_retval(mp: &mut MpFloat, ord: Ordering) -> F +fn prep_retval(mp: &mut MpFloat, ord: Ordering) -> F where for<'a> &'a MpFloat: az::Cast, { @@ -59,7 +61,7 @@ macro_rules! impl_mp_op { type MpTy = MpFloat; fn new_mp() -> Self::MpTy { - new_mpfloat::() + new_mpfloat::>() } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { @@ -83,7 +85,7 @@ macro_rules! impl_mp_op { type MpTy = (MpFloat, MpFloat); fn new_mp() -> Self::MpTy { - (new_mpfloat::(), new_mpfloat::()) + (new_mpfloat::>(), new_mpfloat::>()) } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { @@ -109,9 +111,9 @@ macro_rules! impl_mp_op { fn new_mp() -> Self::MpTy { ( - new_mpfloat::(), - new_mpfloat::(), - new_mpfloat::(), + new_mpfloat::>(), + new_mpfloat::>(), + new_mpfloat::>(), ) } @@ -133,6 +135,16 @@ libm_macros::for_each_function! { skip: [ // Most of these need a manual implementation // verify-sorted-start + addf128, + addf16, + addf32, + addf64, + ashl_u128, + ashl_u32, + ashl_u64, + ashr_i128, + ashr_i32, + ashr_i64, ceil, ceilf, ceilf128, @@ -141,6 +153,19 @@ libm_macros::for_each_function! { copysignf, copysignf128, copysignf16, + divf128, + divf32, + divf64, + eqf128, + eqf16, + eqf32, + eqf64, + extend_f16_f128, + extend_f16_f32, + extend_f16_f64, + extend_f32_f128, + extend_f32_f64, + extend_f64_f128, fabs, fabsf, fabsf128, @@ -162,22 +187,135 @@ libm_macros::for_each_function! { fmodf16, frexp, frexpf, + frexpf128, + frexpf16, + ftoi_f128_i128, + ftoi_f128_i32, + ftoi_f128_i64, + ftoi_f128_u128, + ftoi_f128_u32, + ftoi_f128_u64, + ftoi_f32_i128, + ftoi_f32_i32, + ftoi_f32_i64, + ftoi_f32_u128, + ftoi_f32_u32, + ftoi_f32_u64, + ftoi_f64_i128, + ftoi_f64_i32, + ftoi_f64_i64, + ftoi_f64_u128, + ftoi_f64_u32, + ftoi_f64_u64, + gef128, + gef16, + gef32, + gef64, + gtf128, + gtf16, + gtf32, + gtf64, + iadd_i128, + iadd_u128, + iaddo_i128, + iaddo_u128, + idiv_i128, + idiv_i32, + idiv_i64, + idiv_u128, + idiv_u32, + idiv_u64, + idivmod_i128, + idivmod_i32, + idivmod_i64, + idivmod_u128, + idivmod_u32, + idivmod_u64, ilogb, ilogbf, + ilogbf128, + ilogbf16, + imod_i128, + imod_i32, + imod_i64, + imod_u128, + imod_u32, + imod_u64, + imul_i128, + imul_u64, + imulo_i128, + imulo_i32, + imulo_i64, + imulo_u128, + isub_i128, + isub_u128, + isubo_i128, + isubo_u128, + itof_i128_f128, + itof_i128_f32, + itof_i128_f64, + itof_i32_f128, + itof_i32_f32, + itof_i32_f64, + itof_i64_f128, + itof_i64_f32, + itof_i64_f64, + itof_u128_f128, + itof_u128_f32, + itof_u128_f64, + itof_u32_f128, + itof_u32_f32, + itof_u32_f64, + itof_u64_f128, + itof_u64_f32, + itof_u64_f64, jn, jnf, ldexp, ldexpf, ldexpf128, ldexpf16, + leading_zeros_u128, + leading_zeros_u32, + leading_zeros_u64, + lef128, + lef16, + lef32, + lef64, + lgamma, lgamma_r, + lgammaf, lgammaf_r, + lshr_u128, + lshr_u32, + lshr_u64, + ltf128, + ltf16, + ltf32, + ltf64, modf, modff, + mulf128, + mulf16, + mulf32, + mulf64, + narrow_f128_f16, + narrow_f128_f32, + narrow_f128_f64, + narrow_f32_f16, + narrow_f64_f16, + narrow_f64_f32, + nef128, + nef16, + nef32, + nef64, nextafter, nextafterf, pow, powf,remquo, + powif128, + powif32, + powif64, remquof, rint, rintf, @@ -196,10 +334,21 @@ libm_macros::for_each_function! { scalbnf128, scalbnf16, sincos,sincosf, + subf128, + subf16, + subf32, + subf64, + trailing_zeros_u128, + trailing_zeros_u32, + trailing_zeros_u64, trunc, truncf, truncf128, truncf16,yn, + unordf128, + unordf16, + unordf32, + unordf64, ynf, // verify-sorted-end ], @@ -208,12 +357,11 @@ libm_macros::for_each_function! { expm1 | expm1f => exp_m1, fabs | fabsf => abs, fdim | fdimf | fdimf16 | fdimf128 => positive_diff, - fma | fmaf | fmaf128 => mul_add, + fmaf16 | fma | fmaf | fmaf128 => mul_add, fmax | fmaxf | fmaxf16 | fmaxf128 | fmaximum_num | fmaximum_numf | fmaximum_numf16 | fmaximum_numf128 => max, fmin | fminf | fminf16 | fminf128 | fminimum_num | fminimum_numf | fminimum_numf16 | fminimum_numf128 => min, - lgamma | lgammaf => ln_gamma, log | logf => ln, log1p | log1pf => ln_1p, tgamma | tgammaf => gamma, @@ -235,7 +383,7 @@ macro_rules! impl_no_round { type MpTy = MpFloat; fn new_mp() -> Self::MpTy { - new_mpfloat::() + new_mpfloat::>() } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { @@ -294,7 +442,7 @@ macro_rules! impl_op_for_ty { type MpTy = (MpFloat, MpFloat); fn new_mp() -> Self::MpTy { - (new_mpfloat::(), new_mpfloat::()) + (new_mpfloat::>(), new_mpfloat::>()) } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { @@ -302,8 +450,8 @@ macro_rules! impl_op_for_ty { this.1.assign(&this.0); let (ord0, ord1) = this.0.trunc_fract_round(&mut this.1, Nearest); ( - prep_retval::(&mut this.1, ord0), - prep_retval::(&mut this.0, ord1), + prep_retval::>(&mut this.1, ord0), + prep_retval::>(&mut this.0, ord1), ) } } @@ -312,7 +460,7 @@ macro_rules! impl_op_for_ty { type MpTy = (MpFloat, MpFloat); fn new_mp() -> Self::MpTy { - (new_mpfloat::(), new_mpfloat::()) + (new_mpfloat::>(), new_mpfloat::>()) } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { @@ -323,55 +471,18 @@ macro_rules! impl_op_for_ty { } } - impl MpOp for crate::op::[]::Routine { - type MpTy = MpFloat; - - fn new_mp() -> Self::MpTy { - new_mpfloat::() - } - - fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { - this.assign(input.0); - let exp = this.frexp_mut(); - (prep_retval::(this, Ordering::Equal), exp) - } - } - - impl MpOp for crate::op::[]::Routine { - type MpTy = MpFloat; - - fn new_mp() -> Self::MpTy { - new_mpfloat::() - } - - fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { - this.assign(input.0); - - // `get_exp` follows `frexp` for `0.5 <= |m| < 1.0`. Adjust the exponent by - // one to scale the significand to `1.0 <= |m| < 2.0`. - this.get_exp().map(|v| v - 1).unwrap_or_else(|| { - if this.is_infinite() { - i32::MAX - } else { - // Zero or NaN - i32::MIN - } - }) - } - } - impl MpOp for crate::op::[]::Routine { type MpTy = MpFloat; fn new_mp() -> Self::MpTy { - new_mpfloat::() + new_mpfloat::>() } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { let (n, x) = input; this.assign(x); let ord = this.jn_round(n, Nearest); - prep_retval::(this, ord) + prep_retval::(this, ord) } } @@ -379,7 +490,7 @@ macro_rules! impl_op_for_ty { type MpTy = (MpFloat, MpFloat); fn new_mp() -> Self::MpTy { - (new_mpfloat::(), new_mpfloat::()) + (new_mpfloat::>(), new_mpfloat::>()) } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { @@ -387,8 +498,8 @@ macro_rules! impl_op_for_ty { this.1.assign(0.0); let (sord, cord) = this.0.sin_cos_round(&mut this.1, Nearest); ( - prep_retval::(&mut this.0, sord), - prep_retval::(&mut this.1, cord) + prep_retval::>(&mut this.0, sord), + prep_retval::>(&mut this.1, cord) ) } } @@ -398,8 +509,8 @@ macro_rules! impl_op_for_ty { fn new_mp() -> Self::MpTy { ( - new_mpfloat::(), - new_mpfloat::(), + new_mpfloat::>(), + new_mpfloat::>(), ) } @@ -407,7 +518,7 @@ macro_rules! impl_op_for_ty { this.0.assign(input.0); this.1.assign(input.1); let (ord, q) = this.0.remainder_quo31_round(&this.1, Nearest); - (prep_retval::(&mut this.0, ord), q) + (prep_retval::>(&mut this.0, ord), q) } } @@ -415,14 +526,14 @@ macro_rules! impl_op_for_ty { type MpTy = MpFloat; fn new_mp() -> Self::MpTy { - new_mpfloat::() + new_mpfloat::>() } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { let (n, x) = input; this.assign(x); let ord = this.yn_round(n, Nearest); - prep_retval::(this, ord) + prep_retval::(this, ord) } } } @@ -433,11 +544,154 @@ macro_rules! impl_op_for_ty { macro_rules! impl_op_for_ty_all { ($fty:ty, $suffix:literal) => { paste::paste! { + impl MpOp for crate::op::[]::Routine { + type MpTy = (MpFloat, MpFloat); + + fn new_mp() -> Self::MpTy { + (new_mpfloat::>(), new_mpfloat::>()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.0.assign(input.0); + this.1.assign(input.1); + let ord = this.0.add_assign_round(&this.1, Nearest); + prep_retval::(&mut this.0, ord) + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = (MpFloat, MpFloat); + + fn new_mp() -> Self::MpTy { + (new_mpfloat::>(), new_mpfloat::>()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.0.assign(input.0); + this.1.assign(input.1); + let ord = this.0.sub_assign_round(&this.1, Nearest); + prep_retval::(&mut this.0, ord) + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = (MpFloat, MpFloat); + + fn new_mp() -> Self::MpTy { + (new_mpfloat::>(), new_mpfloat::>()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.0.assign(input.0); + this.1.assign(input.1); + let ord = this.0.mul_assign_round(&this.1, Nearest); + prep_retval::(&mut this.0, ord) + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = (MpFloat, MpFloat); + + fn new_mp() -> Self::MpTy { + (new_mpfloat::>(), new_mpfloat::>()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.0.assign(input.0); + this.1.assign(input.1); + this.0 == this.1 + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = (MpFloat, MpFloat); + + fn new_mp() -> Self::MpTy { + (new_mpfloat::>(), new_mpfloat::>()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.0.assign(input.0); + this.1.assign(input.1); + this.0 > this.1 + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = (MpFloat, MpFloat); + + fn new_mp() -> Self::MpTy { + (new_mpfloat::>(), new_mpfloat::>()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.0.assign(input.0); + this.1.assign(input.1); + this.0 >= this.1 + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = (MpFloat, MpFloat); + + fn new_mp() -> Self::MpTy { + (new_mpfloat::>(), new_mpfloat::>()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.0.assign(input.0); + this.1.assign(input.1); + this.0 < this.1 + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = (MpFloat, MpFloat); + + fn new_mp() -> Self::MpTy { + (new_mpfloat::>(), new_mpfloat::>()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.0.assign(input.0); + this.1.assign(input.1); + this.0 <= this.1 + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = (MpFloat, MpFloat); + + fn new_mp() -> Self::MpTy { + (new_mpfloat::>(), new_mpfloat::>()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.0.assign(input.0); + this.1.assign(input.1); + this.0 != this.1 + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = (MpFloat, MpFloat); + + fn new_mp() -> Self::MpTy { + (new_mpfloat::>(), new_mpfloat::>()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.0.assign(input.0); + this.1.assign(input.1); + this.0.is_nan() || this.1.is_nan() + } + } + impl MpOp for crate::op::[]::Routine { type MpTy = (MpFloat, MpFloat); fn new_mp() -> Self::MpTy { - (new_mpfloat::(), new_mpfloat::()) + (new_mpfloat::>(), new_mpfloat::>()) } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { @@ -452,7 +706,7 @@ macro_rules! impl_op_for_ty_all { type MpTy = (MpFloat, MpFloat); fn new_mp() -> Self::MpTy { - (new_mpfloat::(), new_mpfloat::()) + (new_mpfloat::>(), new_mpfloat::>()) } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { @@ -468,7 +722,7 @@ macro_rules! impl_op_for_ty_all { type MpTy = (MpFloat, MpFloat); fn new_mp() -> Self::MpTy { - (new_mpfloat::(), new_mpfloat::()) + (new_mpfloat::>(), new_mpfloat::>()) } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { @@ -488,7 +742,7 @@ macro_rules! impl_op_for_ty_all { type MpTy = (MpFloat, MpFloat); fn new_mp() -> Self::MpTy { - (new_mpfloat::(), new_mpfloat::()) + (new_mpfloat::>(), new_mpfloat::>()) } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { @@ -504,6 +758,43 @@ macro_rules! impl_op_for_ty_all { } } + impl MpOp for crate::op::[]::Routine { + type MpTy = MpFloat; + + fn new_mp() -> Self::MpTy { + new_mpfloat::>() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + let exp = this.frexp_mut(); + (prep_retval::>(this, Ordering::Equal), exp) + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpFloat; + + fn new_mp() -> Self::MpTy { + new_mpfloat::>() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + + // `get_exp` follows `frexp` for `0.5 <= |m| < 1.0`. Adjust the exponent by + // one to scale the significand to `1.0 <= |m| < 2.0`. + this.get_exp().map(|v| v - 1).unwrap_or_else(|| { + if this.is_infinite() { + i32::MAX + } else { + // Zero or NaN + i32::MIN + } + }) + } + } + // `ldexp` and `scalbn` are the same for binary floating point, so just forward all // methods. impl MpOp for crate::op::[]::Routine { @@ -522,13 +813,122 @@ macro_rules! impl_op_for_ty_all { type MpTy = MpFloat; fn new_mp() -> Self::MpTy { - new_mpfloat::() + new_mpfloat::>() } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { this.assign(input.0); *this <<= input.1; - prep_retval::(this, Ordering::Equal) + prep_retval::(this, Ordering::Equal) + } + } + } + }; +} + +macro_rules! impl_op_for_ty_no_f16 { + ($fty:ty, $suffix:literal) => { + paste::paste! { + impl MpOp for crate::op::[
]::Routine { + type MpTy = (MpFloat, MpFloat); + + fn new_mp() -> Self::MpTy { + (new_mpfloat::>(), new_mpfloat::>()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.0.assign(input.0); + this.1.assign(input.1); + let ord = this.0.div_assign_round(&this.1, Nearest); + prep_retval::(&mut this.0, ord) + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpFloat; + + fn new_mp() -> Self::MpTy { + new_mpfloat::>() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + let ord = this.pow_assign_round(input.1, Nearest); + prep_retval::(this, ord) + } + } + } + }; +} + +macro_rules! impl_extend_trunc { + ($narrow:ty, $wide:ty) => { + paste::paste! { + impl MpOp for crate::op::[]::Routine { + type MpTy = MpFloat; + + fn new_mp() -> Self::MpTy { + new_mpfloat::>() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + prep_retval::(this, Ordering::Equal) + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpFloat; + + fn new_mp() -> Self::MpTy { + new_mpfloat::>() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + prep_retval::(this, Ordering::Equal) + } + } + } + }; +} + +macro_rules! impl_ftoi_itof { + ($fty:ty, $ity:ty) => { + paste::paste! { + impl MpOp for crate::op::[]::Routine { + type MpTy = MpFloat; + + fn new_mp() -> Self::MpTy { + new_mpfloat::>() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + this.trunc_mut(); + this.subnormalize_ieee_round(Ordering::Equal, Nearest); + (&*this).checked_cast().unwrap_or_else(|| { + if this.is_nan() { + 0 + } else if this.is_sign_negative() { + Self::RustRet::MIN + } else { + Self::RustRet::MAX + } + }) + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpFloat; + + fn new_mp() -> Self::MpTy { + new_mpfloat::() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + prep_retval::(this, Ordering::Equal) } } } @@ -538,6 +938,11 @@ macro_rules! impl_op_for_ty_all { impl_op_for_ty!(f32, "f"); impl_op_for_ty!(f64, ""); +impl_op_for_ty_no_f16!(f32, "f"); +impl_op_for_ty_no_f16!(f64, ""); +#[cfg(f128_enabled)] +impl_op_for_ty_no_f16!(f128, "f128"); + #[cfg(f16_enabled)] impl_op_for_ty_all!(f16, "f16"); impl_op_for_ty_all!(f32, "f"); @@ -545,18 +950,56 @@ impl_op_for_ty_all!(f64, ""); #[cfg(f128_enabled)] impl_op_for_ty_all!(f128, "f128"); +#[cfg(f16_enabled)] +impl_extend_trunc!(f16, f32); +#[cfg(f16_enabled)] +impl_extend_trunc!(f16, f64); +#[cfg(f16_enabled)] +#[cfg(f128_enabled)] +impl_extend_trunc!(f16, f128); +impl_extend_trunc!(f32, f64); +#[cfg(f128_enabled)] +impl_extend_trunc!(f32, f128); +#[cfg(f128_enabled)] +impl_extend_trunc!(f64, f128); + +impl_ftoi_itof!(f32, i32); +impl_ftoi_itof!(f32, i64); +impl_ftoi_itof!(f32, i128); +impl_ftoi_itof!(f32, u32); +impl_ftoi_itof!(f32, u64); +impl_ftoi_itof!(f32, u128); +impl_ftoi_itof!(f64, i32); +impl_ftoi_itof!(f64, i64); +impl_ftoi_itof!(f64, i128); +impl_ftoi_itof!(f64, u32); +impl_ftoi_itof!(f64, u64); +impl_ftoi_itof!(f64, u128); +#[cfg(f128_enabled)] +impl_ftoi_itof!(f128, i32); +#[cfg(f128_enabled)] +impl_ftoi_itof!(f128, i64); +#[cfg(f128_enabled)] +impl_ftoi_itof!(f128, i128); +#[cfg(f128_enabled)] +impl_ftoi_itof!(f128, u32); +#[cfg(f128_enabled)] +impl_ftoi_itof!(f128, u64); +#[cfg(f128_enabled)] +impl_ftoi_itof!(f128, u128); + // `lgamma_r` is not a simple suffix so we can't use the above macro. impl MpOp for crate::op::lgamma_r::Routine { type MpTy = MpFloat; fn new_mp() -> Self::MpTy { - new_mpfloat::() + new_mpfloat::>() } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { this.assign(input.0); let (sign, ord) = this.ln_abs_gamma_round(Nearest); - let ret = prep_retval::(this, ord); + let ret = prep_retval::>(this, ord); (ret, sign as i32) } } @@ -565,17 +1008,41 @@ impl MpOp for crate::op::lgammaf_r::Routine { type MpTy = MpFloat; fn new_mp() -> Self::MpTy { - new_mpfloat::() + new_mpfloat::>() } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { this.assign(input.0); let (sign, ord) = this.ln_abs_gamma_round(Nearest); - let ret = prep_retval::(this, ord); + let ret = prep_retval::>(this, ord); (ret, sign as i32) } } +impl MpOp for crate::op::lgamma::Routine { + type MpTy = MpFloat; + + fn new_mp() -> Self::MpTy { + new_mpfloat::>() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + ::run(this, input).0 + } +} + +impl MpOp for crate::op::lgammaf::Routine { + type MpTy = MpFloat; + + fn new_mp() -> Self::MpTy { + new_mpfloat::>() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + ::run(this, input).0 + } +} + /* stub implementations so we don't need to special case them */ impl MpOp for crate::op::nextafter::Routine { @@ -601,3 +1068,286 @@ impl MpOp for crate::op::nextafterf::Routine { unimplemented!("nextafter does not yet have a MPFR operation"); } } + +macro_rules! impl_int_ops { + ($ity:ty) => { + paste::paste! { + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + if input.1 == 0 { + // Make divide by 0 well-defined to match our wrappers. + return <$ity>::MIN; + } + this.assign(input.0); + *this /= input.1; + (&*this).wrapping_as::() + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + if input.1 == 0 { + // Make divide by 0 well-defined to match our wrappers. + return <$ity>::MIN; + } + this.assign(input.0); + *this %= input.1; + (&*this).wrapping_as::() + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = (MpInt, MpInt); + + fn new_mp() -> Self::MpTy { + (MpInt::new(), MpInt::new()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + if input.1 == 0 { + // Make divide by 0 well-defined to match our wrappers. + return (<$ity>::MIN, <$ity>::MIN); + } + this.0.assign(input.0); + this.1.assign(input.1); + this.0.div_rem_mut(&mut this.1); + ( + (&this.0).wrapping_as::>(), + (&this.1).wrapping_as::>(), + ) + } + } + } + }; +} + +impl_int_ops!(i32); +impl_int_ops!(i64); +impl_int_ops!(i128); +impl_int_ops!(u32); +impl_int_ops!(u64); +impl_int_ops!(u128); + +macro_rules! impl_unsigned_int_ops { + ($ity:ty) => { + paste::paste! { + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + assert!(input.1 < Arg0::::BITS, "got UB shift {}", input.1); + this.assign(input.0); + *this <<= input.1; + (&*this).wrapping_as::>() + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + assert!(input.1 < Arg0::::BITS, "got UB shift {}", input.1); + this.assign(input.0); + *this >>= input.1; + (&*this).wrapping_as::>() + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + (Arg0::::BITS - this.significant_bits()).try_into().unwrap() + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + this.find_one(0).unwrap_or(Arg0::::BITS).try_into().unwrap() + } + } + } + }; +} + +impl_unsigned_int_ops!(u32); +impl_unsigned_int_ops!(u64); +impl_unsigned_int_ops!(u128); + +macro_rules! impl_signed_int_ops { + ($ity:ty) => { + paste::paste! { + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + assert!(input.1 < Arg0::::BITS, "got UB shift {}", input.1); + this.assign(input.0); + *this >>= input.1; + (&*this).wrapping_as::() + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + *this *= input.1; + (&*this).overflowing_cast() + } + } + } + }; +} + +impl_signed_int_ops!(i32); +impl_signed_int_ops!(i64); +impl_signed_int_ops!(i128); + +macro_rules! impl_u128_i128_int_ops { + ($ity:ty) => { + paste::paste! { + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + *this += input.1; + (&*this).wrapping_as::() + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + *this -= input.1; + (&*this).wrapping_as::() + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + *this += input.1; + (&*this).overflowing_cast() + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + *this -= input.1; + (&*this).overflowing_cast() + } + } + } + }; +} + +impl_u128_i128_int_ops!(i128); +impl_u128_i128_int_ops!(u128); + +impl MpOp for crate::op::imul_u64::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + *this *= input.1; + (&*this).wrapping_as() + } +} + +impl MpOp for crate::op::imul_i128::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + *this *= input.1; + (&*this).wrapping_as() + } +} + +impl MpOp for crate::op::imulo_u128::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + *this *= input.1; + (&*this).overflowing_cast() + } +} diff --git a/library/compiler-builtins/libm-test/src/num.rs b/library/compiler-builtins/libm-test/src/num.rs index 3237c85039d57..efa87d6351597 100644 --- a/library/compiler-builtins/libm-test/src/num.rs +++ b/library/compiler-builtins/libm-test/src/num.rs @@ -1,6 +1,7 @@ //! Helpful numeric operations. use std::cmp::min; +use std::fmt; use std::ops::RangeInclusive; use libm::support::Float; @@ -257,15 +258,20 @@ where } /// Returns an iterator of up to `steps` integers evenly distributed. -pub fn linear_ints( - range: RangeInclusive, +pub fn linear_ints( + range: RangeInclusive, steps: u64, -) -> (impl Iterator + Clone, u64) { - let steps = steps.checked_sub(1).unwrap(); - let between = u64::from(range.start().abs_diff(*range.end())); - let spacing = i32::try_from((between / steps).max(1)).unwrap(); - let steps = steps.min(between); - let mut x: i32 = *range.start(); +) -> (impl Iterator + Clone, u64) +where + I: Int + TryFrom, + u128: TryFrom, +{ + let spaces: u128 = steps.checked_sub(1).unwrap().into(); + let between = u128::try_from(range.start().abs_diff(*range.end())).expect("out of u128 range"); + let spacing = I::try_from((between / spaces).max(1)).unwrap(); + let steps = spaces.min(between); + let steps = u64::try_from(steps).expect("> u64::MAX steps"); + let mut x: I = *range.start(); ( (0..=steps).map(move |_| { let res = x; @@ -278,6 +284,11 @@ pub fn linear_ints( ) } +/// `..` as a `RangeInclusive`. +pub fn full_range() -> RangeInclusive { + I::MIN..=I::MAX +} + #[cfg(test)] mod tests { use std::cmp::max; diff --git a/library/compiler-builtins/libm-test/src/op.rs b/library/compiler-builtins/libm-test/src/op.rs index afd445ff9c5ae..809d518755262 100644 --- a/library/compiler-builtins/libm-test/src/op.rs +++ b/library/compiler-builtins/libm-test/src/op.rs @@ -16,19 +16,25 @@ use std::fmt; use std::panic::{RefUnwindSafe, UnwindSafe}; -pub use shared::{ALL_OPERATIONS, FloatTy, MathOpInfo, Ty}; +pub use api_list_common::{ALL_OPERATIONS, Group, MathOpInfo, Ty}; -use crate::{CheckOutput, Float, TupleCall}; - -mod shared { - include!("../../crates/libm-macros/src/shared.rs"); -} +use crate::{CheckOutput, Tuple, TupleCall}; /// An enum representing each possible symbol name (`sin`, `sinf`, `sinl`, etc). #[libm_macros::function_enum(BaseName)] #[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)] pub enum Identifier {} +impl Identifier { + /// Return information about this operation. + pub fn math_op(self) -> &'static MathOpInfo { + ALL_OPERATIONS + .iter() + .find(|op| op.name == self.as_str()) + .unwrap() + } +} + impl fmt::Display for Identifier { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { f.write_str(self.as_str()) @@ -49,9 +55,6 @@ impl fmt::Display for BaseName { /// Attributes ascribed to a `libm` routine including signature, type information, /// and naming. pub trait MathOp { - /// The float type used for this operation. - type FTy: Float; - /// The function type representing the signature in a C library. type CFn: Copy; @@ -72,6 +75,7 @@ pub trait MathOp { /// The required `TupleCall` bounds ensure this type can be passed either to the C function or /// to the Rust function. type RustArgs: Copy + + Tuple + TupleCall + TupleCall + RefUnwindSafe; @@ -90,38 +94,44 @@ pub trait MathOp { /// The function in `libm` which can be called. const ROUTINE: Self::RustFn; - - /// Whether or not the function is part of libm public API. - const PUBLIC: bool; } -/// Access the associated `FTy` type from an op (helper to avoid ambiguous associated types). -pub type OpFTy = ::FTy; -/// Access the associated `FTy::Int` type from an op (helper to avoid ambiguous associated types). -pub type OpITy = <::FTy as Float>::Int; -/// Access the associated `CFn` type from an op (helper to avoid ambiguous associated types). +/* Most of these are workarounds for */ + +/// Access the associated `CFn` type from an op. pub type OpCFn = ::CFn; -/// Access the associated `CRet` type from an op (helper to avoid ambiguous associated types). +/// Access the associated `CRet` type from an op. pub type OpCRet = ::CRet; -/// Access the associated `RustFn` type from an op (helper to avoid ambiguous associated types). +/// Access the associated `RustFn` type from an op. pub type OpRustFn = ::RustFn; -/// Access the associated `RustArgs` type from an op (helper to avoid ambiguous associated types). +/// Access the associated `RustArgs` type from an op. pub type OpRustArgs = ::RustArgs; -/// Access the associated `RustRet` type from an op (helper to avoid ambiguous associated types). +/// Access the associated `RustRet` type from an op. pub type OpRustRet = ::RustRet; +/// Get the type of the first Rust argument. +pub type Arg0 = as Tuple>::T0; +/// Get the type of the second Rust argument. +pub type Arg1 = as Tuple>::T1; +/// Get the type of the third Rust argument. +pub type Arg2 = as Tuple>::T2; + +/// If the Rust return type is a tuple, get the first type. +pub type Ret0 = as Tuple>::T0; +/// If the Rust return type is a tuple, get the second type. +pub type Ret1 = as Tuple>::T1; + macro_rules! create_op_modules { // Matcher for unary functions ( fn_name: $fn_name:ident, - FTy: $FTy:ty, CFn: $CFn:ty, CArgs: $CArgs:ty, CRet: $CRet:ty, RustFn: $RustFn:ty, RustArgs: $RustArgs:ty, RustRet: $RustRet:ty, - public: $public:expr, + path: $path:path, attrs: [$($attr:meta),*], ) => { paste::paste! { @@ -131,7 +141,6 @@ macro_rules! create_op_modules { pub struct Routine; impl MathOp for Routine { - type FTy = $FTy; type CFn = for<'a> $CFn; type CArgs<'a> = $CArgs where Self: 'a; type CRet = $CRet; @@ -140,8 +149,7 @@ macro_rules! create_op_modules { type RustRet = $RustRet; const IDENTIFIER: Identifier = Identifier::[< $fn_name:camel >]; - const ROUTINE: Self::RustFn = libm::$fn_name; - const PUBLIC: bool = $public; + const ROUTINE: Self::RustFn = $path; } } diff --git a/library/compiler-builtins/libm-test/src/precision.rs b/library/compiler-builtins/libm-test/src/precision.rs index 7887c032394b8..967274caa9644 100644 --- a/library/compiler-builtins/libm-test/src/precision.rs +++ b/library/compiler-builtins/libm-test/src/precision.rs @@ -1,9 +1,10 @@ //! Configuration for skipping or changing the result for individual test cases (inputs) rather //! than ignoring entire tests. +use BaseName as Bn; use CheckBasis::{Mpfr, Musl}; +use Identifier as Id; use libm::support::CastFrom; -use {BaseName as Bn, Identifier as Id}; use crate::{BaseName, CheckBasis, CheckCtx, Float, Identifier, Int, TestResult}; @@ -12,9 +13,38 @@ pub struct SpecialCase; /// ULP allowed to differ from the results returned by a test basis. #[allow(clippy::single_match)] -pub fn default_ulp(ctx: &CheckCtx) -> u32 { +pub fn default_ulp(ctx: &CheckCtx) -> Option { // ULP compared to the infinite (MPFR) result. let mut ulp = match ctx.base_name { + // Basic arithmetic needs to always be precise. + Bn::Add | Bn::Sub | Bn::Mul | Bn::Div => 0, + // FIXME(correctness): we need a better powi implementation (though this is no worse + // than C). + Bn::Powi if ctx.fn_ident == Id::Powif64 => 500_000, + Bn::Powi => 1000, + + // Operations that only return non-float results + Bn::Eq | Bn::Ne | Bn::Gt | Bn::Ge | Bn::Lt | Bn::Le | Bn::Unord | Bn::Ilogb => return None, + + // Integer ops + Bn::Ashl + | Bn::Ashr + | Bn::Lshr + | Bn::LeadingZeros + | Bn::TrailingZeros + | Bn::Iadd + | Bn::Iaddo + | Bn::Isub + | Bn::Isubo + | Bn::Imul + | Bn::Imulo + | Bn::Idiv + | Bn::Imod + | Bn::Idivmod => return None, + + // Convrsion operations must be precise. + Bn::Extend | Bn::Narrow | Bn::Ftoi | Bn::Itof => 0, + // Operations that require exact results. This list should correlate with what we // have documented at . Bn::Ceil @@ -31,7 +61,6 @@ pub fn default_ulp(ctx: &CheckCtx) -> u32 { | Bn::FminimumNum | Bn::Fmod | Bn::Frexp - | Bn::Ilogb | Bn::Ldexp | Bn::Modf | Bn::Nextafter @@ -46,6 +75,7 @@ pub fn default_ulp(ctx: &CheckCtx) -> u32 { // Operations that aren't required to be exact, but our implementations are. Bn::Cbrt => 0, + Bn::Hypot if ctx.fn_ident == Id::Hypot => 0, // Bessel functions have large inaccuracies. Bn::J0 | Bn::J1 | Bn::Y0 | Bn::Y1 | Bn::Jn | Bn::Yn => 8_000_000, @@ -67,7 +97,7 @@ pub fn default_ulp(ctx: &CheckCtx) -> u32 { Bn::Exp2 => 1, Bn::Expm1 => 1, Bn::Hypot => 1, - Bn::Lgamma | Bn::LgammaR => 16, + Bn::Lgamma | Bn::LgammaR => 4, Bn::Log => 1, Bn::Log10 => 1, Bn::Log1p => 1, @@ -83,8 +113,10 @@ pub fn default_ulp(ctx: &CheckCtx) -> u32 { Bn::Tgamma => 20, }; - // These have a separate implementation on i586 - if cfg!(x86_no_sse) { + let mut orig_ulp = ulp; + + // These have a separate implementation on i586 which is more accurate. + if cfg!(x86_no_sse2) { match ctx.fn_ident { Id::Exp => ulp = 1, Id::Exp2 => ulp = 1, @@ -94,44 +126,17 @@ pub fn default_ulp(ctx: &CheckCtx) -> u32 { Id::Exp10f => ulp = 0, _ => (), } - } - // There are some cases where musl's approximation is less accurate than ours. For these - // cases, increase the ULP. - if ctx.basis == Musl { - match ctx.base_name { - Bn::Cosh => ulp = 2, - Bn::Exp10 if usize::BITS < 64 => ulp = 4, - Bn::Lgamma | Bn::LgammaR => ulp = 400, - Bn::Tanh => ulp = 4, - _ => (), - } - - match ctx.fn_ident { - Id::Cbrt => ulp = 2, - // FIXME(#401): musl has an incorrect result here. - Id::Fdim => ulp = 2, - Id::Exp2f => ulp = 1, - Id::Expf => ulp = 1, - Id::Sincosf => ulp = 500, - Id::Tgamma => ulp = 20, - _ => (), - } - } + assert!(ulp <= orig_ulp, "pattern can be deleted {ctx:?}"); + orig_ulp = ulp; - if cfg!(target_arch = "x86") { + // Due to rust-lang/rust#114479 (unsound floating point behavior on x86 without SSE), the + // following operations have worse precision. match ctx.fn_ident { - // Input `fma(0.999999999999999, 1.0000000000000013, 0.0) = 1.0000000000000002` is - // incorrect on i586 and i686. + // FIXME: these need to be correctly rounded but are not, likely due to LLVM bugs + // around precision without SSE float ops. It may be worth looking into an assembly + // implementation. Id::Fma => ulp = 1, - _ => (), - } - } - - // In some cases, our implementation is less accurate than musl on i586. - if cfg!(x86_no_sse) { - match ctx.fn_ident { - // FIXME(#401): these need to be correctly rounded but are not. Id::Fmaf => ulp = 1, Id::Fdim => ulp = 1, Id::Round => ulp = 1, @@ -139,13 +144,44 @@ pub fn default_ulp(ctx: &CheckCtx) -> u32 { Id::Asinh => ulp = 3, Id::Asinhf => ulp = 3, Id::Cbrt => ulp = 1, - Id::Log1p | Id::Log1pf => ulp = 2, + Id::Hypot => ulp = 1, + Id::Log1p => ulp = 2, + Id::Log1pf => ulp = 2, Id::Tan => ulp = 2, _ => (), } + + assert!(ulp >= orig_ulp, "pattern can be deleted {ctx:?}"); + orig_ulp = ulp; } - ulp + // There are some cases where musl's approximation is less accurate than ours, either due to + // the implementation itself or because of x87 inaccuracy problems. For these cases, increase + // the allowed ULP. + if ctx.basis == Musl { + match ctx.fn_ident { + // Musl probably runs into issues with the x87 ABI here which we don't have. + Id::Fma if cfg!(target_arch = "x86") => ulp = 1, + Id::Fdim => ulp = 2, + + Id::Asinhf => ulp = 3, + Id::Cbrt => ulp = 2, + Id::Cosh => ulp = 2, + Id::Coshf => ulp = 2, + Id::Exp10 if cfg!(x86_no_sse2) => ulp = 4, + Id::Exp10f if cfg!(x86_no_sse2) => ulp = 4, + Id::Exp2f => ulp = 1, + Id::Expf => ulp = 1, + Id::Hypot => ulp = 1, + Id::Tanh => ulp = 4, + Id::Tanhf => ulp = 4, + _ => (), + } + + assert!(ulp >= orig_ulp, "pattern can be deleted {ctx:?}"); + } + + Some(ulp) } /// Result of checking for possible overrides. @@ -218,17 +254,26 @@ impl MaybeOverride<(f16,)> for SpecialCase {} impl MaybeOverride<(f32,)> for SpecialCase { fn check_float(input: (f32,), actual: F, expected: F, ctx: &CheckCtx) -> CheckAction { - if (ctx.base_name == BaseName::Lgamma || ctx.base_name == BaseName::LgammaR) - && input.0 > 4e36 + if ctx.base_name == BaseName::J0 && input.0 < -1e34 { + // Errors get huge close to -inf + return XFAIL_NOCHECK; + } + + // the testing infrastructure doesn't account for allowed ulp in the case of overflow + if matches!(ctx.base_name, BaseName::Lgamma | BaseName::LgammaR) + && input.0 == 4.0850034e36 && expected.is_infinite() - && !actual.is_infinite() + && actual == F::MAX { - // This result should saturate but we return a finite value. return XFAIL_NOCHECK; } - if ctx.base_name == BaseName::J0 && input.0 < -1e34 { - // Errors get huge close to -inf + // FIXME(correctness): lgammaf has high relative inaccuracy near its zeroes + if matches!(ctx.base_name, BaseName::Lgamma | BaseName::LgammaR) + && input.0 > -13.0625 + && input.0 < -2.0 + && (expected.abs() < F::ONE || (input.0 - input.0.round()).abs() < 0.02) + { return XFAIL_NOCHECK; } @@ -252,17 +297,26 @@ impl MaybeOverride<(f32,)> for SpecialCase { impl MaybeOverride<(f64,)> for SpecialCase { fn check_float(input: (f64,), actual: F, expected: F, ctx: &CheckCtx) -> CheckAction { - if cfg!(x86_no_sse) - && (ctx.base_name == BaseName::Rint || ctx.base_name == BaseName::Roundeven) - && (expected - actual).abs() <= F::ONE - && (expected - actual).abs() > F::ZERO + if ctx.base_name == BaseName::J0 && input.0 < -1e300 { + // Errors get huge close to -inf + return XFAIL_NOCHECK; + } + + if ctx.base_name == BaseName::Acosh + && input.0 < 1.0 + && actual.is_nan() + && ctx.basis == CheckBasis::Musl { - // Our rounding mode is incorrect. - return XFAIL("i586 rint rounding mode"); + // Musl sometimes evaluates acosh(negative) to a numeric value + return XFAIL_NOCHECK; } - if ctx.base_name == BaseName::J0 && input.0 < -1e300 { - // Errors get huge close to -inf + // FIXME(correctness): lgamma has high relative inaccuracy near its zeroes + if matches!(ctx.base_name, BaseName::Lgamma | BaseName::LgammaR) + && input.0 > -32.0 + && input.0 < -2.0 + && (expected.abs() < F::ONE || (input.0 - input.0.round()).abs() < 0.02) + { return XFAIL_NOCHECK; } @@ -295,27 +349,6 @@ fn unop_common( expected: F2, ctx: &CheckCtx, ) -> CheckAction { - if ctx.base_name == BaseName::Acosh - && input.0 < F1::NEG_ONE - && !(expected.is_nan() && actual.is_nan()) - { - // acoshf is undefined for x <= 1.0, but we return a random result at lower values. - - if ctx.basis == CheckBasis::Musl { - return XFAIL_NOCHECK; - } - - return XFAIL("acoshf undefined"); - } - - if (ctx.base_name == BaseName::Lgamma || ctx.base_name == BaseName::LgammaR) - && input.0 < F1::ZERO - && !input.0.is_infinite() - { - // loggamma should not be defined for x < 0, yet we both return results - return XFAIL_NOCHECK; - } - // fabs and copysign must leave NaNs untouched. if ctx.base_name == BaseName::Fabs && input.0.is_nan() { // LLVM currently uses x87 instructions which quieten signalling NaNs to handle the i686 @@ -401,14 +434,6 @@ fn binop_common( return SKIP; } - // FIXME(#939): this should not be skipped, there is a bug in our implementationi. - if ctx.base_name == BaseName::FmaximumNum - && ctx.basis == CheckBasis::Mpfr - && ((input.0.is_nan() && actual.is_nan() && expected.is_nan()) || input.1.is_nan()) - { - return XFAIL_NOCHECK; - } - /* FIXME(#439): our fmin and fmax do not compare signed zeros */ if ctx.base_name == BaseName::Fmin @@ -501,18 +526,19 @@ fn int_float_common( } // Our bessel functions blow up with large N values - if ctx.basis == Musl && (ctx.base_name == BaseName::Jn || ctx.base_name == BaseName::Yn) { - if cfg!(x86_no_sse) { + if ctx.base_name == BaseName::Jn || ctx.base_name == BaseName::Yn { + if cfg!(x86_no_sse2) { // Precision is especially bad on i586, not worth checking. return XFAIL_NOCHECK; } - if input.0 > 4000 { + if input.0 > 140 { return XFAIL_NOCHECK; - } else if input.0 > 100 { - return CheckAction::AssertWithUlp(1_000_000); + } else if input.0 > 80 { + return CheckAction::AssertWithUlp(10_000_000); } } + DEFAULT } @@ -523,7 +549,29 @@ impl MaybeOverride<(f64, i32)> for SpecialCase {} #[cfg(f128_enabled)] impl MaybeOverride<(f128, i32)> for SpecialCase {} +#[cfg(f16_enabled)] +impl MaybeOverride<(f16, f16, f16)> for SpecialCase {} impl MaybeOverride<(f32, f32, f32)> for SpecialCase {} impl MaybeOverride<(f64, f64, f64)> for SpecialCase {} #[cfg(f128_enabled)] impl MaybeOverride<(f128, f128, f128)> for SpecialCase {} + +impl MaybeOverride<(i32,)> for SpecialCase {} +impl MaybeOverride<(i64,)> for SpecialCase {} +impl MaybeOverride<(i128,)> for SpecialCase {} +impl MaybeOverride<(u32,)> for SpecialCase {} +impl MaybeOverride<(u64,)> for SpecialCase {} +impl MaybeOverride<(u128,)> for SpecialCase {} + +impl MaybeOverride<(i32, i32)> for SpecialCase {} +impl MaybeOverride<(i64, i64)> for SpecialCase {} +impl MaybeOverride<(i128, i128)> for SpecialCase {} +impl MaybeOverride<(u32, u32)> for SpecialCase {} +impl MaybeOverride<(u64, u64)> for SpecialCase {} +impl MaybeOverride<(u128, u128)> for SpecialCase {} + +impl MaybeOverride<(i32, u32)> for SpecialCase {} +impl MaybeOverride<(i64, u32)> for SpecialCase {} +impl MaybeOverride<(i128, u32)> for SpecialCase {} +impl MaybeOverride<(u64, u32)> for SpecialCase {} +impl MaybeOverride<(u128, u32)> for SpecialCase {} diff --git a/library/compiler-builtins/libm-test/src/run_cfg.rs b/library/compiler-builtins/libm-test/src/run_cfg.rs index 90f81195c8560..234eb914e6d2b 100644 --- a/library/compiler-builtins/libm-test/src/run_cfg.rs +++ b/library/compiler-builtins/libm-test/src/run_cfg.rs @@ -2,10 +2,10 @@ use std::ops::RangeInclusive; use std::sync::LazyLock; -use std::{env, str}; +use std::{env, fmt, str}; use crate::generate::random::{SEED, SEED_ENV}; -use crate::{BaseName, FloatTy, Identifier, test_log}; +use crate::{BaseName, Group, Identifier, Ty, test_log}; /// The environment variable indicating which extensive tests should be run. pub const EXTENSIVE_ENV: &str = "LIBM_EXTENSIVE_TESTS"; @@ -15,9 +15,12 @@ pub const EXTENSIVE_ITER_ENV: &str = "LIBM_EXTENSIVE_ITERATIONS"; /// The override value, if set by the above environment. static EXTENSIVE_ITER_OVERRIDE: LazyLock> = LazyLock::new(|| { - env::var(EXTENSIVE_ITER_ENV) - .map(|v| v.parse().expect("failed to parse iteration count")) - .ok() + let s = env::var(EXTENSIVE_ITER_ENV).ok()?; + let r = match s.as_str() { + "unlimited" | "max" => u64::MAX, + _ => s.parse().expect("failed to parse iteration count"), + }; + Some(r) }); /// Specific tests that need to have a reduced amount of iterations to complete in a reasonable @@ -69,7 +72,7 @@ pub fn extensive_max_iterations() -> u64 { #[derive(Clone, Debug, PartialEq, Eq)] pub struct CheckCtx { /// Allowed ULP deviation - pub ulp: u32, + pub ulp: Option, pub fn_ident: Identifier, pub base_name: BaseName, /// Function name. @@ -88,7 +91,7 @@ impl CheckCtx { /// Create a new check context, using the default ULP for the function. pub fn new(fn_ident: Identifier, basis: CheckBasis, gen_kind: GeneratorKind) -> Self { let mut ret = Self { - ulp: 0, + ulp: None, fn_ident, fn_name: fn_ident.as_str(), base_name: fn_ident.base_name(), @@ -152,10 +155,10 @@ static EXTENSIVE: LazyLock> = LazyLock::new(|| { let list = var.split(",").filter(|s| !s.is_empty()).collect::>(); let mut ret = Vec::new(); - let append_ty_ops = |ret: &mut Vec<_>, fty: FloatTy| { + let append_ty_ops = |ret: &mut Vec<_>, group: Group| { let iter = Identifier::ALL .iter() - .filter(move |id| id.math_op().float_ty == fty) + .filter(move |id| id.math_op().group == group) .copied(); ret.extend(iter); }; @@ -163,10 +166,11 @@ static EXTENSIVE: LazyLock> = LazyLock::new(|| { for item in list { match item { "all" => ret = Identifier::ALL.to_owned(), - "all_f16" => append_ty_ops(&mut ret, FloatTy::F16), - "all_f32" => append_ty_ops(&mut ret, FloatTy::F32), - "all_f64" => append_ty_ops(&mut ret, FloatTy::F64), - "all_f128" => append_ty_ops(&mut ret, FloatTy::F128), + "all_f16" => append_ty_ops(&mut ret, Group::F16), + "all_f32" => append_ty_ops(&mut ret, Group::F32), + "all_f64" => append_ty_ops(&mut ret, Group::F64), + "all_f128" => append_ty_ops(&mut ret, Group::F128), + "all_int" => append_ty_ops(&mut ret, Group::Integer), s => { let id = Identifier::from_str(s) .unwrap_or_else(|| panic!("unrecognized test name `{s}`")); @@ -178,13 +182,18 @@ static EXTENSIVE: LazyLock> = LazyLock::new(|| { ret }); +/// Most ops are somewhere on the order or 10^7 iterations per second when running exhaustive +/// tests. Assuming about four hours to run, this is log2 of the max number of inputs that coul +/// be tested. +const MAX_REASONABLE_EXHAUSTIVE_BITS: u32 = 36; + /// Information about the function to be tested. #[derive(Debug)] struct TestEnv { /// Tests should be reduced because the platform is slow. E.g. 32-bit or emulated. slow_platform: bool, - /// The float cannot be tested exhaustively, `f64` or `f128`. - large_float_ty: bool, + /// How many bits of input there are for this function. + total_input_bits: u32, /// Env indicates that an extensive test should be run. should_run_extensive: bool, /// Multiprecision tests will be run. @@ -199,10 +208,11 @@ impl TestEnv { let op = id.math_op(); let will_run_mp = cfg!(feature = "build-mpfr"); - let large_float_ty = match op.float_ty { - FloatTy::F16 | FloatTy::F32 => false, - FloatTy::F64 | FloatTy::F128 => true, - }; + + let mut total_input_bits = 0; + for ty in op.rust_sig.args { + total_input_bits += ty.effective_bits(); + } let will_run_extensive = EXTENSIVE.contains(&id); @@ -210,7 +220,7 @@ impl TestEnv { Self { slow_platform: slow_platform(), - large_float_ty, + total_input_bits, should_run_extensive: will_run_extensive, mp_tests_enabled: will_run_mp, input_count, @@ -229,8 +239,9 @@ fn slow_platform() -> bool { slow_on_ci && crate::ci() } -/// The number of iterations to run for a given test. -pub fn iteration_count(ctx: &CheckCtx, argnum: usize) -> u64 { +/// The maximum number of iterations to run for a given argument in a given test. This may be +/// greater than the number of representable values. +pub fn arg_max_iterations(ctx: &CheckCtx, argnum: usize) -> u64 { let t_env = TestEnv::from_env(ctx); // Ideally run 5M tests @@ -251,51 +262,58 @@ pub fn iteration_count(ctx: &CheckCtx, argnum: usize) -> u64 { // Run fewer random tests than domain tests. let random_iter_count = domain_iter_count / 100; + let mut should_adjust = true; let mut total_iterations = match ctx.gen_kind { - GeneratorKind::Spaced if ctx.extensive => extensive_max_iterations(), + GeneratorKind::Spaced if ctx.extensive => { + // If an exact number is provided, no need to adjust + should_adjust = EXTENSIVE_ITER_OVERRIDE.is_none(); + extensive_max_iterations() + } GeneratorKind::Spaced => domain_iter_count, GeneratorKind::Random => random_iter_count, GeneratorKind::EdgeCases | GeneratorKind::List => { - unimplemented!("shoudn't need `iteration_count` for {:?}", ctx.gen_kind) + unimplemented!("shoudn't need `arg_max_iterations` for {:?}", ctx.gen_kind) } }; - // Larger float types get more iterations. - if t_env.large_float_ty { - if ctx.extensive { - // Extensive already has a pretty high test count. - total_iterations *= 2; - } else { - total_iterations *= 4; + // Apply some adjustments so tests with more possible inputs (argument count or larger float + // types) get more tests. + if should_adjust { + // This signature has too many possible inputs to test exhaustively, so increase input count + // on all other kinds of tests to get better coverage. + if t_env.total_input_bits > MAX_REASONABLE_EXHAUSTIVE_BITS { + if ctx.extensive { + // Extensive already has a pretty high test count. + total_iterations *= 2; + } else { + total_iterations *= 4; + } } - } - // Functions with more arguments get more iterations. - let arg_multiplier = 1 << (t_env.input_count - 1); - total_iterations *= arg_multiplier; + // Functions with more arguments get more iterations. + let arg_multiplier = 1 << (t_env.input_count - 1); + total_iterations *= arg_multiplier; - // FMA has a huge domain but is reasonably fast to run, so increase another 1.5x. - if ctx.base_name == BaseName::Fma { - total_iterations = 3 * total_iterations / 2; - } + // FMA has a huge domain but is reasonably fast to run, so increase another 1.5x. + if ctx.base_name == BaseName::Fma { + total_iterations = 3 * total_iterations / 2; + } - // Some tests are significantly slower than others and need to be further reduced. - if let Some(slow) = EXTREMELY_SLOW_TESTS - .iter() - .find(|slow| slow.matches_ctx(ctx)) - { - // However, do not override if the extensive iteration count has been manually set. - if !(ctx.extensive && EXTENSIVE_ITER_OVERRIDE.is_some()) { + // Some tests are significantly slower than others and need to be further reduced. + if let Some(slow) = EXTREMELY_SLOW_TESTS + .iter() + .find(|slow| slow.matches_ctx(ctx)) + { total_iterations /= slow.reduce_factor; } - } - if cfg!(optimizations_enabled) { - // Always run at least 10,000 tests. - total_iterations = total_iterations.max(10_000); - } else { - // Without optimizations, just run a quick check regardless of other parameters. - total_iterations = 800; + if cfg!(optimizations_enabled) { + // Always run at least 10,000 tests. + total_iterations = total_iterations.max(10_000); + } else { + // Without optimizations, just run a quick check regardless of other parameters. + total_iterations = 800; + } } let mut overridden = false; @@ -304,7 +322,7 @@ pub fn iteration_count(ctx: &CheckCtx, argnum: usize) -> u64 { overridden = true; } - // Adjust for the number of inputs + // Distribute available iterations among inputs. let ntests = match t_env.input_count { 1 => total_iterations, 2 => (total_iterations as f64).sqrt().ceil() as u64, @@ -312,7 +330,7 @@ pub fn iteration_count(ctx: &CheckCtx, argnum: usize) -> u64 { _ => panic!("test has more than three arguments"), }; - let total = ntests.pow(t_env.input_count.try_into().unwrap()); + let total = ntests.saturating_pow(t_env.input_count.try_into().unwrap()); let seed_msg = match ctx.gen_kind { GeneratorKind::Spaced => String::new(), @@ -339,12 +357,39 @@ pub fn iteration_count(ctx: &CheckCtx, argnum: usize) -> u64 { ntests } -/// Some tests require that an integer be kept within reasonable limits; generate that here. -pub fn int_range(ctx: &CheckCtx, argnum: usize) -> RangeInclusive { +/// Some tests require that an integer be kept within reasonable limits; if that is needed, retun +/// a limited range. +pub fn int_range(ctx: &CheckCtx, argnum: usize) -> Option> +where + I: TryFrom, +{ let t_env = TestEnv::from_env(ctx); + let argcount = ctx.fn_ident.math_op().rust_sig.args.len(); + assert!( + argnum < argcount, + "requested argnum {argnum} of only {argcount} args" + ); + + // Shift operations can have UB if the shift value exceeds their range + if matches!( + ctx.base_name, + BaseName::Ashl | BaseName::Ashr | BaseName::Lshr + ) && argnum == 1 + { + let max = match ctx.fn_ident.math_op().rust_sig.args[0] { + Ty::U32 | Ty::I32 => 31, + Ty::U64 | Ty::I64 => 63, + Ty::U128 | Ty::I128 => 127, + ty => panic!("unexpected type {ty}"), + }; + + return Some(map_range(0..=max)); + } + + // Use the whole range for most functions. if !matches!(ctx.base_name, BaseName::Jn | BaseName::Yn) { - return i32::MIN..=i32::MAX; + return None; } assert_eq!( @@ -362,12 +407,21 @@ pub fn int_range(ctx: &CheckCtx, argnum: usize) -> RangeInclusive { let extensive_range = (-0xfff)..=0xfffff; - match ctx.gen_kind { + let ret = match ctx.gen_kind { _ if ctx.extensive => extensive_range, GeneratorKind::Spaced | GeneratorKind::Random => non_extensive_range, GeneratorKind::EdgeCases => extensive_range, GeneratorKind::List => unimplemented!("shoudn't need range for {:?}", ctx.gen_kind), - } + }; + + Some(map_range(ret)) +} + +fn map_range(r: RangeInclusive) -> RangeInclusive +where + I: TryFrom, +{ + I::try_from(*r.start()).unwrap()..=I::try_from(*r.end()).unwrap() } /// For domain tests, limit how many asymptotes or specified check points we test. diff --git a/library/compiler-builtins/libm-test/src/test_traits.rs b/library/compiler-builtins/libm-test/src/test_traits.rs index 278274d917b35..a1b48224bfd47 100644 --- a/library/compiler-builtins/libm-test/src/test_traits.rs +++ b/library/compiler-builtins/libm-test/src/test_traits.rs @@ -1,7 +1,8 @@ //! Traits related to testing. //! -//! There are two main traits in this module: +//! There are three main traits in this module: //! +//! - `Tuple`: Implemented on tuples to help extract types. //! - `TupleCall`: implemented on tuples to allow calling them as function arguments. //! - `CheckOutput`: implemented on anything that is an output type for validation against an //! expected value. @@ -10,7 +11,7 @@ use std::panic::{RefUnwindSafe, UnwindSafe}; use std::{fmt, panic}; use anyhow::{Context, anyhow, bail, ensure}; -use libm::support::Hexf; +use libm::support::{DisplayHex, Hex}; use crate::precision::CheckAction; use crate::{ @@ -23,6 +24,7 @@ use crate::{ /// tuple for multiple signatures). pub trait TupleCall: fmt::Debug { type Output; + fn call(self, f: Func) -> Self::Output; /// Intercept panics and print the input to stderr before continuing. @@ -42,6 +44,16 @@ pub trait TupleCall: fmt::Debug { } } +/// Helper to allow extracting types from a tuple. +pub trait Tuple { + type T0; + type T1; + type T2; +} + +/// If a tuple contains fewer types than provided in `Tuple`, they use this struct. +pub enum Unused {} + /// A trait to implement on any output type so we can verify it in a generic way. pub trait CheckOutput: Sized { /// Validate `self` (actual) and `expected` are the same. @@ -50,15 +62,24 @@ pub trait CheckOutput: Sized { fn validate(self, expected: Self, input: Input, ctx: &CheckCtx) -> TestResult; } -/// A helper trait to print something as hex with the correct number of nibbles, e.g. a `u32` -/// will always print with `0x` followed by 8 digits. -/// -/// This is only used for printing errors so allocating is okay. -pub trait Hex: Copy { - /// Hex integer syntax. - fn hex(self) -> String; - /// Hex float syntax. - fn hexf(self) -> String; +/* implement Tuple */ + +impl Tuple for (T0,) { + type T0 = T0; + type T1 = Unused; + type T2 = Unused; +} + +impl Tuple for (T0, T1) { + type T0 = T0; + type T1 = T1; + type T2 = Unused; +} + +impl Tuple for (T0, T1, T2) { + type T0 = T0; + type T1 = T1; + type T2 = T2; } /* implement `TupleCall` */ @@ -142,47 +163,25 @@ where } } -/* implement `Hex` */ - -impl Hex for (T1,) -where - T1: Hex, -{ - fn hex(self) -> String { - format!("({},)", self.0.hex()) - } - - fn hexf(self) -> String { - format!("({},)", self.0.hexf()) - } -} - -impl Hex for (T1, T2) -where - T1: Hex, - T2: Hex, -{ - fn hex(self) -> String { - format!("({}, {})", self.0.hex(), self.1.hex()) - } - - fn hexf(self) -> String { - format!("({}, {})", self.0.hexf(), self.1.hexf()) - } -} +/* trait implementations for bool */ -impl Hex for (T1, T2, T3) +impl CheckOutput for bool where - T1: Hex, - T2: Hex, - T3: Hex, + Input: Copy + DisplayHex + fmt::Debug, + SpecialCase: MaybeOverride, { - fn hex(self) -> String { - format!("({}, {}, {})", self.0.hex(), self.1.hex(), self.2.hex()) - } + fn validate<'a>(self, expected: Self, input: Input, _ctx: &CheckCtx) -> TestResult { + anyhow::ensure!( + self == expected, + "\ + \n input: {input:?} {ibits}\ + \n expected: {expected}\ + \n actual: {self}\ + ", + ibits = Hex(input), + ); - fn hexf(self) -> String { - format!("({}, {}, {})", self.0.hexf(), self.1.hexf(), self.2.hexf()) + Ok(()) } } @@ -191,19 +190,9 @@ where macro_rules! impl_int { ($($ty:ty),*) => { $( - impl Hex for $ty { - fn hex(self) -> String { - format!("{self:#0width$x}", width = ((Self::BITS / 4) + 2) as usize) - } - - fn hexf(self) -> String { - String::new() - } - } - impl $crate::CheckOutput for $ty where - Input: Hex + fmt::Debug, + Input: Copy + DisplayHex + fmt::Debug, SpecialCase: MaybeOverride, { fn validate<'a>( @@ -221,8 +210,8 @@ macro_rules! impl_int { fn validate_int(actual: I, expected: I, input: Input, ctx: &CheckCtx) -> TestResult where - I: Int + Hex, - Input: Hex + fmt::Debug, + I: Int, + Input: Copy + DisplayHex + fmt::Debug, SpecialCase: MaybeOverride, { let (result, xfail_msg) = match SpecialCase::check_int(input, actual, expected, ctx) { @@ -243,47 +232,29 @@ where None => String::new(), }; - anyhow::ensure!( - result, - "\ - \n input: {input:?} {ibits}\ - \n expected: {expected:<22?} {expbits}\ - \n actual: {actual:<22?} {actbits}\ - \n {msg}\ - ", - actbits = actual.hex(), - expbits = expected.hex(), - ibits = input.hex(), - msg = make_xfail_msg() - ); + if !result { + bail!(make_error_message( + input, + expected, + actual, + "", + &make_xfail_msg() + )); + } Ok(()) } -impl_int!(u32, i32, u64, i64); +impl_int!(u16, i16, u32, i32, u64, i64, u128, i128, usize); /* trait implementations for floats */ macro_rules! impl_float { ($($ty:ty),*) => { $( - impl Hex for $ty { - fn hex(self) -> String { - format!( - "{:#0width$x}", - self.to_bits(), - width = ((Self::BITS / 4) + 2) as usize - ) - } - - fn hexf(self) -> String { - format!("{}", Hexf(self)) - } - } - impl $crate::CheckOutput for $ty where - Input: Hex + fmt::Debug, + Input: Copy + DisplayHex + fmt::Debug, SpecialCase: MaybeOverride, { fn validate<'a>( @@ -301,8 +272,8 @@ macro_rules! impl_float { fn validate_float(actual: F, expected: F, input: Input, ctx: &CheckCtx) -> TestResult where - F: Float + Hex, - Input: Hex + fmt::Debug, + F: Float, + Input: Copy + DisplayHex + fmt::Debug, u32: TryFrom, SpecialCase: MaybeOverride, { @@ -310,11 +281,11 @@ where // Create a wrapper function so we only need to `.with_context` once. let mut inner = || -> TestResult { - let mut allowed_ulp = ctx.ulp; + let mut allowed_ulp = ctx + .ulp + .expect("functions returning floats should have a default ulp set"); match SpecialCase::check_float(input, actual, expected, ctx) { - // Forbid overrides if the items came from an explicit list - _ if ctx.gen_kind == GeneratorKind::List => (), CheckAction::AssertSuccess => (), CheckAction::AssertFailure(msg) => assert_failure_msg = Some(msg), CheckAction::Custom(res) => return res, @@ -385,23 +356,7 @@ where } } - res.with_context(|| { - format!( - "\ - \n input: {input:?}\ - \n as hex: {ihex}\ - \n as bits: {ibits}\ - \n expected: {expected:<22?} {exphex} {expbits}\ - \n actual: {actual:<22?} {acthex} {actbits}\ - ", - ihex = input.hexf(), - ibits = input.hex(), - exphex = expected.hexf(), - expbits = expected.hex(), - actbits = actual.hex(), - acthex = actual.hexf(), - ) - }) + res.with_context(|| make_error_message(input, expected, actual, "", "")) } impl_float!(f32, f64); @@ -420,30 +375,27 @@ macro_rules! impl_tuples { $( impl CheckOutput for ($a, $b) where - Input: Hex + fmt::Debug, + Input: Copy + DisplayHex + fmt::Debug, SpecialCase: MaybeOverride, - { + { fn validate<'a>( self, expected: Self, input: Input, ctx: &CheckCtx, ) -> TestResult { - self.0.validate(expected.0, input, ctx) + self.0 + .validate(expected.0, input, ctx) .and_then(|()| self.1.validate(expected.1, input, ctx)) - .with_context(|| format!( - "full context:\ - \n input: {input:?} {ibits}\ - \n as hex: {ihex}\ - \n as bits: {ibits}\ - \n expected: {expected:?} {expbits}\ - \n actual: {self:?} {actbits}\ - ", - ihex = input.hexf(), - ibits = input.hex(), - expbits = expected.hex(), - actbits = self.hex(), - )) + .with_context(|| { + make_error_message( + input, + expected, + self, + "full context:", + "", + ) + }) } } )* @@ -451,8 +403,66 @@ macro_rules! impl_tuples { } impl_tuples!( + (i32, i32); + (i64, i64); + (i128, i128); + + (u32, u32); + (u64, u64); + (u128, u128); + + (i32, bool); + (i64, bool); + (i128, bool); + + (u32, bool); + (u64, bool); + (u128, bool); + (f32, i32); (f64, i32); (f32, f32); (f64, f64); ); + +#[cfg(f16_enabled)] +impl_tuples!( + (f16, i32); + (f16, f16); +); + +#[cfg(f128_enabled)] +impl_tuples!( + (f128, i32); + (f128, f128); +); + +fn make_error_message( + input: I, + expected: E, + actual: A, + pre_msg: &str, + post_msg: &str, +) -> String +where + I: Copy + fmt::Debug + DisplayHex, + E: Copy + fmt::Debug + DisplayHex, + A: Copy + fmt::Debug + DisplayHex, +{ + let pre_pad = if pre_msg.is_empty() { "" } else { "\n " }; + let post_pad = if post_msg.is_empty() { "" } else { "\n " }; + format!( + "\ + {pre_pad}{pre_msg}\ + \n input: {input:?}\ + \n as hex: {ihex}\ + \n as bits: {ihex:-}\ + \n expected: {expected:<16?} {exphex} {exphex:-}\ + \n actual: {actual:<16?} {acthex} {acthex:-}\ + {post_pad}{post_msg}\ + ", + ihex = Hex(input), + exphex = Hex(expected), + acthex = Hex(actual), + ) +} diff --git a/library/compiler-builtins/libm-test/tests/check_coverage.rs b/library/compiler-builtins/libm-test/tests/check_coverage.rs index 3b445a3de9da1..384fef19daf8c 100644 --- a/library/compiler-builtins/libm-test/tests/check_coverage.rs +++ b/library/compiler-builtins/libm-test/tests/check_coverage.rs @@ -39,7 +39,14 @@ fn test_for_each_function_all_included() { `ALL_OPERATIONS` (in `libm-macros`)." ); } - assert_eq!(all_functions, tested); + + // FIXME: This needs to be updated to interact with compiler-builtins + // assert_eq!( + // all_functions, + // tested, + // "difference: {:?}", + // tested.difference(&all_functions) + // ); } #[test] diff --git a/library/compiler-builtins/libm-test/tests/compare_built_musl.rs b/library/compiler-builtins/libm-test/tests/compare_built_musl.rs index 86f3b8b711ea7..5e9ead0473c2e 100644 --- a/library/compiler-builtins/libm-test/tests/compare_built_musl.rs +++ b/library/compiler-builtins/libm-test/tests/compare_built_musl.rs @@ -78,6 +78,7 @@ libm_macros::for_each_function! { attributes: [], // Not provided by musl skip_f16_f128: true, + skip_builtins: true, skip: [ // TODO integer inputs jn, diff --git a/library/compiler-builtins/libm-test/tests/u256.rs b/library/compiler-builtins/libm-test/tests/u256.rs index d1c5cfbcc586d..a17e16f8f429b 100644 --- a/library/compiler-builtins/libm-test/tests/u256.rs +++ b/library/compiler-builtins/libm-test/tests/u256.rs @@ -2,15 +2,16 @@ //! routines, so this only does a few million fuzz iterations against GMP. #![cfg(feature = "build-mpfr")] +#![allow(unstable_name_collisions)] // for the integer_widen_truncate feature use std::sync::LazyLock; -use libm::support::{HInt, u256}; +use libm::support::{HInt, i256, u256}; type BigInt = rug::Integer; -use libm_test::bigint_fuzz_iteration_count; use libm_test::generate::random::SEED; -use rand::{Rng, SeedableRng}; +use libm_test::{MinInt, bigint_fuzz_iteration_count}; +use rand::{RngExt, SeedableRng}; use rand_chacha::ChaCha8Rng; use rug::Assign; use rug::integer::Order; @@ -19,56 +20,162 @@ use rug::ops::NotAssign; static BIGINT_U256_MAX: LazyLock = LazyLock::new(|| BigInt::from_digits(&[u128::MAX, u128::MAX], Order::Lsf)); -/// Copied from the test module. -fn hexu(v: u256) -> String { - format!("0x{:032x}{:032x}", v.hi, v.lo) -} - fn random_u256(rng: &mut ChaCha8Rng) -> u256 { let lo: u128 = rng.random(); let hi: u128 = rng.random(); u256 { lo, hi } } -fn assign_bigint(bx: &mut BigInt, x: u256) { - bx.assign_digits(&[x.lo, x.hi], Order::Lsf); +fn random_i256(rng: &mut ChaCha8Rng) -> i256 { + random_u256(rng).signed() +} + +fn assign_bigint_u256(bx: &mut BigInt, x: u256) { + bx.assign(x.hi); + *bx <<= 128; + *bx += x.lo; } -fn from_bigint(bx: &mut BigInt) -> u256 { +fn assign_bigint_i256(bx: &mut BigInt, x: i256) { + bx.assign(x.hi); + *bx <<= 128; + *bx += x.lo; +} + +/// Note that this destroys the result in `bx`. +fn from_bigint_u256(bx: &mut BigInt) -> u256 { // Truncate so the result fits into `[u128; 2]`. This makes all ops overflowing. *bx &= &*BIGINT_U256_MAX; let mut bres = [0u128, 0]; bx.write_digits(&mut bres, Order::Lsf); - bx.assign(0); + bx.assign(0); // prevent accidental reuse u256 { lo: bres[0], hi: bres[1], } } -fn check_one( - x: impl FnOnce() -> String, - y: impl FnOnce() -> Option, - actual: u256, - expected: &mut BigInt, -) { - let expected = from_bigint(expected); +/// Note that this destroys the result in `bx`. +fn from_bigint_i256(bx: &mut BigInt) -> i256 { + // Truncate so the result fits into `[u128; 2]`. This makes all ops overflowing. + *bx &= &*BIGINT_U256_MAX; + let lo = bx.to_u128_wrapping(); + *bx >>= 128; + let hi = bx.to_i128_wrapping(); + bx.assign(0); // prevent accidental reuse + i256 { hi, lo } +} + +#[track_caller] +fn assert_same_u256(msg: impl Fn() -> String, actual: u256, expected_big: &mut BigInt) { + let expected = from_bigint_u256(expected_big); + if actual != expected { + let mut act_big = BigInt::new(); + assign_bigint_u256(&mut act_big, actual); + panic!( + "Test failure: {}\n\ + actual: {act_big}\n\ + expected: {expected_big}\n\ + actual: {actual:#x}\n\ + expected: {expected:#x}\ + ", + msg() + ) + } +} + +#[track_caller] +fn assert_same_i256(msg: impl Fn() -> String, actual: i256, expected_big: &mut BigInt) { + let expected = from_bigint_i256(expected_big); if actual != expected { - let xmsg = x(); - let ymsg = y().map(|y| format!("y: {y}\n")).unwrap_or_default(); + let mut act_big = BigInt::new(); + assign_bigint_i256(&mut act_big, actual); panic!( - "Results do not match\n\ - input: {xmsg}\n\ - {ymsg}\ - actual: {}\n\ - expected: {}\ + "Test failure: {}\n\ + actual: {act_big}\n\ + expected: {expected_big}\n\ + actual: {actual:#x}\n\ + expected: {expected:#x}\ ", - hexu(actual), - hexu(expected), + msg() ) } } +/// Verify the test setup. +#[test] +fn mp_u256_roundtrip() { + let mut rng = ChaCha8Rng::from_seed(*SEED); + let mut bx = BigInt::new(); + + for _ in 0..bigint_fuzz_iteration_count() { + let x = random_u256(&mut rng); + assign_bigint_u256(&mut bx, x); + assert_eq!(from_bigint_u256(&mut bx), x); + } + + // Check wraparound + assign_bigint_u256(&mut bx, u256::MAX); + bx += 1; + assert_eq!(from_bigint_u256(&mut bx), u256::MIN); + assign_bigint_u256(&mut bx, u256::MIN); + bx -= 1; + assert_eq!(from_bigint_u256(&mut bx), u256::MAX); +} + +/// Verify the test setup. +#[test] +fn mp_i256_roundtrip() { + let mut rng = ChaCha8Rng::from_seed(*SEED); + let mut bx = BigInt::new(); + + for _ in 0..bigint_fuzz_iteration_count() { + let x = random_i256(&mut rng); + assign_bigint_i256(&mut bx, x); + assert_eq!(from_bigint_i256(&mut bx), x); + } + + // Check wraparound + assign_bigint_i256(&mut bx, i256::MAX); + bx += 1; + assert_eq!(from_bigint_i256(&mut bx), i256::MIN); + assign_bigint_i256(&mut bx, i256::MIN); + bx -= 1; + assert_eq!(from_bigint_i256(&mut bx), i256::MAX); +} + +#[test] +fn mp_u256_ord() { + let mut rng = ChaCha8Rng::from_seed(*SEED); + let mut bx = BigInt::new(); + let mut by = BigInt::new(); + + for _ in 0..bigint_fuzz_iteration_count() { + let x = random_u256(&mut rng); + let y = random_u256(&mut rng); + assign_bigint_u256(&mut bx, x); + assign_bigint_u256(&mut by, y); + + assert_eq!(x.cmp(&y), bx.cmp(&by), "cmp({x:#x}, {y:#x})"); + } +} + +#[test] +fn mp_i256_ord() { + let mut rng = ChaCha8Rng::from_seed(*SEED); + let mut bx = BigInt::new(); + let mut by = BigInt::new(); + + for _ in 0..bigint_fuzz_iteration_count() { + let x = random_i256(&mut rng); + let y = random_i256(&mut rng); + assign_bigint_i256(&mut bx, x); + assign_bigint_i256(&mut by, y); + + assert_eq!(x.cmp(&y), bx.cmp(&by), "cmp({x:#x}, {y:#x})"); + } +} + #[test] fn mp_u256_bitor() { let mut rng = ChaCha8Rng::from_seed(*SEED); @@ -78,11 +185,28 @@ fn mp_u256_bitor() { for _ in 0..bigint_fuzz_iteration_count() { let x = random_u256(&mut rng); let y = random_u256(&mut rng); - assign_bigint(&mut bx, x); - assign_bigint(&mut by, y); + assign_bigint_u256(&mut bx, x); + assign_bigint_u256(&mut by, y); + let actual = x | y; + bx |= &by; + assert_same_u256(|| format!("{x:#x} ^ {y:#x}"), actual, &mut bx); + } +} + +#[test] +fn mp_i256_bitor() { + let mut rng = ChaCha8Rng::from_seed(*SEED); + let mut bx = BigInt::new(); + let mut by = BigInt::new(); + + for _ in 0..bigint_fuzz_iteration_count() { + let x = random_i256(&mut rng); + let y = random_i256(&mut rng); + assign_bigint_i256(&mut bx, x); + assign_bigint_i256(&mut by, y); let actual = x | y; bx |= &by; - check_one(|| hexu(x), || Some(hexu(y)), actual, &mut bx); + assert_same_i256(|| format!("{x:#x} ^ {y:#x}"), actual, &mut bx); } } @@ -93,10 +217,24 @@ fn mp_u256_not() { for _ in 0..bigint_fuzz_iteration_count() { let x = random_u256(&mut rng); - assign_bigint(&mut bx, x); + assign_bigint_u256(&mut bx, x); + let actual = !x; + bx.not_assign(); + assert_same_u256(|| format!("!{x:#x}"), actual, &mut bx); + } +} + +#[test] +fn mp_i256_not() { + let mut rng = ChaCha8Rng::from_seed(*SEED); + let mut bx = BigInt::new(); + + for _ in 0..bigint_fuzz_iteration_count() { + let x = random_i256(&mut rng); + assign_bigint_i256(&mut bx, x); let actual = !x; bx.not_assign(); - check_one(|| hexu(x), || None, actual, &mut bx); + assert_same_i256(|| format!("!{x:#x}"), actual, &mut bx); } } @@ -109,8 +247,9 @@ fn mp_u256_add() { for _ in 0..bigint_fuzz_iteration_count() { let x = random_u256(&mut rng); let y = random_u256(&mut rng); - assign_bigint(&mut bx, x); - assign_bigint(&mut by, y); + assign_bigint_u256(&mut bx, x); + assign_bigint_u256(&mut by, y); + // Emulate wrapping semantics with panicking ops let actual = if u256::MAX - x >= y { x + y } else { @@ -119,7 +258,35 @@ fn mp_u256_add() { y - (u256::MAX - x) - 1_u128.widen() }; bx += &by; - check_one(|| hexu(x), || Some(hexu(y)), actual, &mut bx); + assert_same_u256(|| format!("{x:#x} + {y:#x}"), actual, &mut bx); + } +} + +#[test] +fn mp_i256_add() { + let mut rng = ChaCha8Rng::from_seed(*SEED); + let mut bx = BigInt::new(); + let mut by = BigInt::new(); + + for _ in 0..bigint_fuzz_iteration_count() { + let x = random_i256(&mut rng); + let y = random_i256(&mut rng); + assign_bigint_i256(&mut bx, x); + assign_bigint_i256(&mut by, y); + + // Emulate wrapping semantics with panicking ops + let actual = if x > i256::ZERO && y > i256::MAX - x { + // Overflow condition + (x + i256::MIN) + (y + i256::MIN) + } else if x < i256::ZERO && y < i256::MIN - x { + // Underflow condition + (x - i256::MIN) + (y - i256::MIN) + } else { + // Otherwise there is no overflow + x + y + }; + bx += &by; + assert_same_i256(|| format!("{x:#x} + {y:#x}"), actual, &mut bx); } } @@ -132,15 +299,41 @@ fn mp_u256_sub() { for _ in 0..bigint_fuzz_iteration_count() { let x = random_u256(&mut rng); let y = random_u256(&mut rng); - assign_bigint(&mut bx, x); - assign_bigint(&mut by, y); + assign_bigint_u256(&mut bx, x); + assign_bigint_u256(&mut by, y); // since the operators (may) panic on overflow, // we should test something that doesn't let actual = if x >= y { x - y } else { y - x }; bx -= &by; bx.abs_mut(); - check_one(|| hexu(x), || Some(hexu(y)), actual, &mut bx); + assert_same_u256(|| format!("{x:#x} - {y:#x}"), actual, &mut bx); + } +} + +#[test] +fn mp_i256_sub() { + let mut rng = ChaCha8Rng::from_seed(*SEED); + let mut bx = BigInt::new(); + let mut by = BigInt::new(); + + for _ in 0..bigint_fuzz_iteration_count() { + let x = random_i256(&mut rng); + let y = random_i256(&mut rng); + assign_bigint_i256(&mut bx, x); + assign_bigint_i256(&mut by, y); + dbg!(&bx, &by); + + // Emulate wrapping semantics with panicking ops + let actual = if y > i256::ZERO && x < i256::MIN + y { + (x - i256::MIN) - (y + i256::MIN) + } else if y < i256::ZERO && x > i256::MAX + y { + (x + i256::MIN) - (y - i256::MIN) + } else { + x - y + }; + bx -= &by; + assert_same_i256(|| format!("{x:#x} - {y:#x}"), actual, &mut bx); } } @@ -152,10 +345,25 @@ fn mp_u256_shl() { for _ in 0..bigint_fuzz_iteration_count() { let x = random_u256(&mut rng); let shift: u32 = rng.random_range(0..256); - assign_bigint(&mut bx, x); + assign_bigint_u256(&mut bx, x); + let actual = x << shift; + bx <<= shift; + assert_same_u256(|| format!("{x:#x} << {shift}"), actual, &mut bx); + } +} + +#[test] +fn mp_i256_shl() { + let mut rng = ChaCha8Rng::from_seed(*SEED); + let mut bx = BigInt::new(); + + for _ in 0..bigint_fuzz_iteration_count() { + let x = random_i256(&mut rng); + let shift: u32 = rng.random_range(0..256); + assign_bigint_i256(&mut bx, x); let actual = x << shift; bx <<= shift; - check_one(|| hexu(x), || Some(shift.to_string()), actual, &mut bx); + assert_same_i256(|| format!("{x:#x} << {shift}"), actual, &mut bx); } } @@ -167,15 +375,30 @@ fn mp_u256_shr() { for _ in 0..bigint_fuzz_iteration_count() { let x = random_u256(&mut rng); let shift: u32 = rng.random_range(0..256); - assign_bigint(&mut bx, x); + assign_bigint_u256(&mut bx, x); + let actual = x >> shift; + bx >>= shift; + assert_same_u256(|| format!("{x:#x} >> {shift}"), actual, &mut bx); + } +} + +#[test] +fn mp_i256_shr() { + let mut rng = ChaCha8Rng::from_seed(*SEED); + let mut bx = BigInt::new(); + + for _ in 0..bigint_fuzz_iteration_count() { + let x = random_i256(&mut rng); + let shift: u32 = rng.random_range(0..256); + assign_bigint_i256(&mut bx, x); let actual = x >> shift; bx >>= shift; - check_one(|| hexu(x), || Some(shift.to_string()), actual, &mut bx); + assert_same_i256(|| format!("{x:#x} >> {shift}"), actual, &mut bx); } } #[test] -fn mp_u256_widen_mul() { +fn mp_u256_u128_widen_mul() { let mut rng = ChaCha8Rng::from_seed(*SEED); let mut bx = BigInt::new(); let mut by = BigInt::new(); @@ -187,9 +410,8 @@ fn mp_u256_widen_mul() { by.assign(y); let actual = x.widen_mul(y); bx *= &by; - check_one( - || format!("{x:#034x}"), - || Some(format!("{y:#034x}")), + assert_same_u256( + || format!("{x:#034x}.widen_mul({y:#034x})"), actual, &mut bx, ); diff --git a/library/compiler-builtins/libm/CHANGELOG.md b/library/compiler-builtins/libm/CHANGELOG.md index 33fec06aa2379..037f79ef3ef1c 100644 --- a/library/compiler-builtins/libm/CHANGELOG.md +++ b/library/compiler-builtins/libm/CHANGELOG.md @@ -8,6 +8,22 @@ and this project adheres to ## [Unreleased] +## [0.2.16](https://github.com/rust-lang/compiler-builtins/compare/libm-v0.2.15...libm-v0.2.16) - 2025-12-07 + +### Fixed + +- Fix an incorrect result for `fminimum` and `fmaximum` with the input (-0, NaN) +- Fix a typo in `libm::Libm::roundeven` +- Fix the `expm1f` overflow threshold +- Change `CmpResult` to use a pointer-sized return type +- Compare against `CARGO_CFG_TARGET_FAMILY` in a multi-valued fashion +- Implement `exp` and its variants for i586 with inline assembly +- Implement `floor` and `ceil` in assembly on `i586` + +### Other + +- Significantly optimize `fmod` worst case performance ([#1002](https://github.com/rust-lang/compiler-builtins/pull/1002)) + ## [0.2.15](https://github.com/rust-lang/compiler-builtins/compare/libm-v0.2.14...libm-v0.2.15) - 2025-05-06 ### Other diff --git a/library/compiler-builtins/libm/Cargo.toml b/library/compiler-builtins/libm/Cargo.toml index 5b5ca34fd2c9e..f9dbd29ffc3ea 100644 --- a/library/compiler-builtins/libm/Cargo.toml +++ b/library/compiler-builtins/libm/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "libm" -version = "0.2.15" +version = "0.2.16" authors = [ "Alex Crichton ", "Amanieu d'Antras ", @@ -13,7 +13,11 @@ keywords = ["libm", "math"] repository = "https://github.com/rust-lang/compiler-builtins" license = "MIT" edition = "2021" -rust-version = "1.63" +rust-version = "1.67" + +[dev-dependencies] +# FIXME(msrv>=1.85): switch to `no-panic.workspace` +no-panic = "0.1.36" [features] default = ["arch"] @@ -34,19 +38,17 @@ unstable-public-internals = [] # Enable the nightly-only `f16` and `f128`. unstable-float = [] -# Used to prevent using any intrinsics or arch-specific code. -# -# HACK: this is a negative feature which is generally a bad idea in Cargo, but -# we need it to be able to forbid other features when this crate is used in -# Rust dependencies. Setting this overrides all features that may enable -# hard float operations. +# DEPRECATED: This feature is kept around for compatibility reasons but +# does not do anything. +# FIXME(1.0): remove this feature. force-soft-floats = [] -[dev-dependencies] -no-panic = "0.1.35" - [lints.rust] unexpected_cfgs = { level = "warn", check-cfg = [ - # compiler-builtins sets this feature, but we use it in `libm` + # compiler-builtins sets these features, but we use them in `libm` 'cfg(feature, values("compiler-builtins"))', + 'cfg(feature, values("unmangled-names"))', ] } + +[package.metadata.docs.rs] +features = ["unstable-float"] diff --git a/library/compiler-builtins/libm/build.rs b/library/compiler-builtins/libm/build.rs index 07d08ed4364db..584e6a25da270 100644 --- a/library/compiler-builtins/libm/build.rs +++ b/library/compiler-builtins/libm/build.rs @@ -1,18 +1,11 @@ -use std::env; - mod configure; -fn main() { - let cfg = configure::Config::from_env(); +use configure::{Config, Library}; +fn main() { println!("cargo:rerun-if-changed=build.rs"); println!("cargo:rerun-if-changed=configure.rs"); - println!("cargo:rustc-check-cfg=cfg(assert_no_panic)"); - - // If set, enable `no-panic`. Requires LTO (`release-opt` profile). - if env::var("ENSURE_NO_PANIC").is_ok() { - println!("cargo:rustc-cfg=assert_no_panic"); - } - configure::emit_libm_config(&cfg); + let cfg = Config::from_env(Library::Libm); + configure::emit(&cfg); } diff --git a/library/compiler-builtins/libm/configure.rs b/library/compiler-builtins/libm/configure.rs index ee65a3a8d6243..ec4e46c391042 100644 --- a/library/compiler-builtins/libm/configure.rs +++ b/library/compiler-builtins/libm/configure.rs @@ -1,16 +1,23 @@ -// Configuration shared with both libm and libm-test +//! Common configuration shared by multiple crates in the workspace. -use std::env; +use std::env::{self, VarError}; use std::path::PathBuf; +use std::sync::atomic::AtomicBool; +use std::sync::atomic::Ordering::Relaxed; + +/// Read from env, print more debug output via `cargo:warning` if set. +static VERBOSE_BUILD: AtomicBool = AtomicBool::new(false); #[derive(Debug)] #[allow(dead_code)] pub struct Config { + pub library: Library, pub manifest_dir: PathBuf, pub out_dir: PathBuf, pub opt_level: String, pub cargo_features: Vec, pub target_triple: String, + pub target_triple_split: Vec, pub target_arch: String, pub target_env: String, pub target_families: Vec, @@ -23,8 +30,14 @@ pub struct Config { } impl Config { - pub fn from_env() -> Self { + pub fn from_env(library: Library) -> Self { + println!("cargo:rerun-if-env-changed=LIBM_BUILD_VERBOSE"); + if env_flag("LIBM_BUILD_VERBOSE") { + VERBOSE_BUILD.store(true, Relaxed); + } + let target_triple = env::var("TARGET").unwrap(); + let target_triple_split = target_triple.split('-').map(ToOwned::to_owned).collect(); let target_families = env::var("CARGO_CFG_TARGET_FAMILY") .map(|feats| feats.split(',').map(ToOwned::to_owned).collect()) .unwrap_or_default(); @@ -35,9 +48,16 @@ impl Config { .filter_map(|(name, _value)| name.strip_prefix("CARGO_FEATURE_").map(ToOwned::to_owned)) .map(|s| s.to_lowercase().replace("_", "-")) .collect(); + if VERBOSE_BUILD.load(Relaxed) { + for feature in &cargo_features { + println!("cargo:warning=feature `{feature}` enabled"); + } + } Self { + library, target_triple, + target_triple_split, manifest_dir: PathBuf::from(env::var("CARGO_MANIFEST_DIR").unwrap()), out_dir: PathBuf::from(env::var("OUT_DIR").unwrap()), opt_level: env::var("OPT_LEVEL").unwrap(), @@ -55,70 +75,98 @@ impl Config { reliable_f16: env::var_os("CARGO_CFG_TARGET_HAS_RELIABLE_F16").is_some(), } } -} -/// Libm gets most config options made available. -#[allow(dead_code)] -pub fn emit_libm_config(cfg: &Config) { - emit_intrinsics_cfg(); - emit_arch_cfg(); - emit_optimization_cfg(cfg); - emit_cfg_shorthands(cfg); - emit_cfg_env(cfg); - emit_f16_f128_cfg(cfg); + #[allow(dead_code)] + pub fn has_target_feature(&self, feature: &str) -> bool { + self.target_features.iter().any(|f| f == feature) + } } -/// Tests don't need most feature-related config. +/// The library that is setting this configuration #[allow(dead_code)] -pub fn emit_test_config(cfg: &Config) { - emit_optimization_cfg(cfg); - emit_cfg_shorthands(cfg); - emit_cfg_env(cfg); - emit_f16_f128_cfg(cfg); +#[derive(Debug)] +pub enum Library { + BuiltinsTest, + BuiltinsTestIntrinsics, + CompilerBuiltins, + Libm, + LibmTest, + Util, } -/// Simplify the feature logic for enabling intrinsics so code only needs to use -/// `cfg(intrinsics_enabled)`. -fn emit_intrinsics_cfg() { - println!("cargo:rustc-check-cfg=cfg(intrinsics_enabled)"); +#[allow(unexpected_cfgs)] // Not all crates use all these features +pub fn emit(cfg: &Config) { + let split = &cfg.target_triple_split; - // Disabled by default; `unstable-intrinsics` enables again; `force-soft-floats` overrides - // to disable. - if cfg!(feature = "unstable-intrinsics") && !cfg!(feature = "force-soft-floats") { - println!("cargo:rustc-cfg=intrinsics_enabled"); - } -} + let unstable_float = cfg!(feature = "unstable-float"); -/// Simplify the feature logic for enabling arch-specific features so code only needs to use -/// `cfg(arch_enabled)`. -fn emit_arch_cfg() { - println!("cargo:rustc-check-cfg=cfg(arch_enabled)"); + // Intrinsics may include `core::arch` use, so also gate it under `arch`. + let intrinsics_enabled = cfg!(feature = "unstable-intrinsics") && cfg!(feature = "arch"); - // Enabled by default via the "arch" feature, `force-soft-floats` overrides to disable. - if cfg!(feature = "arch") && !cfg!(feature = "force-soft-floats") { - println!("cargo:rustc-cfg=arch_enabled"); - } -} + // Some tests are extremely slow. Emit a config option based on optimization level. + let opt = !matches!(cfg.opt_level.as_str(), "0" | "1"); -/// Some tests are extremely slow. Emit a config option based on optimization level. -fn emit_optimization_cfg(cfg: &Config) { - println!("cargo:rustc-check-cfg=cfg(optimizations_enabled)"); + // To compile builtins-test-intrinsics for thumb targets, where there is no libc + let thumb = split[0].starts_with("thumb"); - if !matches!(cfg.opt_level.as_str(), "0" | "1") { - println!("cargo:rustc-cfg=optimizations_enabled"); - } -} + // compiler-rt `cfg`s away some intrinsics for thumbv6m and thumbv8m.base because + // these targets do not have full Thumb-2 support but only original Thumb-1. + // We have to cfg our code accordingly. + let thumb_1 = split[0] == "thumbv6m" || split[0] == "thumbv8m.base"; + + // Shorthand to detect i586 targets + let x86_no_sse2 = cfg.target_arch == "x86" && !cfg.target_features.iter().any(|f| f == "sse2"); -/// Provide an alias for common longer config combinations. -fn emit_cfg_shorthands(cfg: &Config) { - println!("cargo:rustc-check-cfg=cfg(x86_no_sse)"); - if cfg.target_arch == "x86" && !cfg.target_features.iter().any(|f| f == "sse") { - // Shorthand to detect i586 targets - println!("cargo:rustc-cfg=x86_no_sse"); + // If set, enable `no-panic` for `libm`. Requires LTO (`release-opt` profile). + let assert_no_panic = env_flag("ENSURE_NO_PANIC"); + + // Arch shorthand config is used in most crates. + set_cfg("thumb", thumb); + set_cfg("thumb_1", thumb_1); + set_cfg("x86_no_sse2", x86_no_sse2); + + match cfg.library { + Library::CompilerBuiltins => { + // libm config. Intrinsics are always enabled when a part of c-b. + set_cfg("assert_no_panic", assert_no_panic); + set_cfg("intrinsics_enabled", true); + set_cfg("optimizations_enabled", opt); + + // Not all backends support `f16` and `f128` to the same level on all architectures, + // so we need to disable things if the compiler may crash. See configuration at: + // * https://github.com/rust-lang/rust/blob/c65dccabacdfd6c8a7f7439eba13422fdd89b91e/compiler/rustc_codegen_llvm/src/llvm_util.rs#L367-L432 + // * https://github.com/rust-lang/rustc_codegen_gcc/blob/4b5c44b14166083eef8d71f15f5ea1f53fc976a0/src/lib.rs#L496-L507 + // * https://github.com/rust-lang/rustc_codegen_cranelift/blob/c713ffab3c6e28ab4b4dd4e392330f786ea657ad/src/lib.rs#L196-L226 + set_cfg("f16_enabled", cfg.reliable_f16); + set_cfg("f128_enabled", cfg.reliable_f128); + } + Library::BuiltinsTest => { + set_cfg("f16_enabled", cfg.reliable_f16); + set_cfg("f128_enabled", cfg.reliable_f128); + } + Library::BuiltinsTestIntrinsics => { + set_cfg("f16_enabled", cfg.reliable_f16); + set_cfg("f128_enabled", cfg.reliable_f128); + } + Library::Libm | Library::Util => { + set_cfg("assert_no_panic", assert_no_panic); + set_cfg("intrinsics_enabled", intrinsics_enabled); + set_cfg("optimizations_enabled", opt); + + set_cfg("f16_enabled", unstable_float && cfg.reliable_f16); + set_cfg("f128_enabled", unstable_float && cfg.reliable_f128); + } + Library::LibmTest => { + set_cfg("optimizations_enabled", opt); + emit_cfg_env(cfg); + + set_cfg("f16_enabled", unstable_float && cfg.reliable_f16); + set_cfg("f128_enabled", unstable_float && cfg.reliable_f128); + } } } -/// Reemit config that we make use of for test logging. +/// Re-emit config that we make use of for test logging. fn emit_cfg_env(cfg: &Config) { println!( "cargo:rustc-env=CFG_CARGO_FEATURES={:?}", @@ -131,25 +179,24 @@ fn emit_cfg_env(cfg: &Config) { ); } -/// Configure whether or not `f16` and `f128` support should be enabled. -fn emit_f16_f128_cfg(cfg: &Config) { - println!("cargo:rustc-check-cfg=cfg(f16_enabled)"); - println!("cargo:rustc-check-cfg=cfg(f128_enabled)"); - - // `unstable-float` enables these features. - if !cfg!(feature = "unstable-float") { +/// Emit a check-cfg directive and enable the cfg if `set` is `true`. +pub fn set_cfg(name: &str, set: bool) { + println!("cargo:rustc-check-cfg=cfg({name})"); + if !set { return; } - - /* See the compiler-builtins configure file for info about the meaning of these options */ - - println!("cargo:rustc-check-cfg=cfg(f16_enabled)"); - if cfg.reliable_f16 { - println!("cargo:rustc-cfg=f16_enabled"); + if VERBOSE_BUILD.load(Relaxed) { + println!("cargo:warning=setting config `{name}`"); } + println!("cargo:rustc-cfg={name}"); +} - println!("cargo:rustc-check-cfg=cfg(f128_enabled)"); - if cfg.reliable_f128 { - println!("cargo:rustc-cfg=f128_enabled"); +/// Return true if the env is set to a value other than `0`. +pub fn env_flag(key: &str) -> bool { + match env::var(key) { + Ok(x) if x == "0" => false, + Err(VarError::NotPresent) => false, + Err(VarError::NotUnicode(_)) => panic!("non-unicode var for `{key}`"), + Ok(_) => true, } } diff --git a/library/compiler-builtins/libm/src/lib.rs b/library/compiler-builtins/libm/src/lib.rs index 31b12235314cd..9c323347a04dd 100644 --- a/library/compiler-builtins/libm/src/lib.rs +++ b/library/compiler-builtins/libm/src/lib.rs @@ -1,5 +1,6 @@ //! libm in pure Rust #![no_std] +// #![cfg_attr(intrinsics_enabled, allow(internal_features))] #![cfg_attr(intrinsics_enabled, feature(core_intrinsics))] #![cfg_attr( @@ -8,20 +9,26 @@ )] #![cfg_attr(f128_enabled, feature(f128))] #![cfg_attr(f16_enabled, feature(f16))] +// +// The edition is 2021 but we follow 2024 idioms. +#![deny(rust_2024_compatibility)] +#![allow(edition_2024_expr_fragment_specifier)] +// +// FIXME(float_bits_const): remove when stable +#![allow(unstable_name_collisions)] +// Allow idioms that come from ported C or may be more clear #![allow(clippy::assign_op_pattern)] -#![allow(clippy::deprecated_cfg_attr)] -#![allow(clippy::eq_op)] -#![allow(clippy::excessive_precision)] -#![allow(clippy::float_cmp)] #![allow(clippy::int_plus_one)] -#![allow(clippy::just_underscores_and_digits)] -#![allow(clippy::many_single_char_names)] -#![allow(clippy::mixed_case_hex_literals)] #![allow(clippy::needless_late_init)] #![allow(clippy::needless_return)] -#![allow(clippy::unreadable_literal)] +// Literals are usually intentional +#![allow(clippy::excessive_precision)] +// Allow needed patterns like `(z - z) / (z - z)` and `0.0 / 0.0` that we need for exceptions +// and rounding. +#![allow(clippy::eq_op)] #![allow(clippy::zero_divided_by_zero)] -#![forbid(unsafe_op_in_unsafe_fn)] +// In generic code we use bits like `let _0 = F::ZERO` +#![allow(clippy::just_underscores_and_digits)] mod libm_helper; mod math; diff --git a/library/compiler-builtins/libm/src/libm_helper.rs b/library/compiler-builtins/libm/src/libm_helper.rs index 0bb669398657e..f2c4daed561ec 100644 --- a/library/compiler-builtins/libm/src/libm_helper.rs +++ b/library/compiler-builtins/libm/src/libm_helper.rs @@ -195,6 +195,7 @@ libm_helper! { (fn fabs(x: f16) -> (f16); => fabsf16); (fn fdim(x: f16, y: f16) -> (f16); => fdimf16); (fn floor(x: f16) -> (f16); => floorf16); + (fn fma(x: f16, y: f16, z: f16) -> (f16); => fmaf16); (fn fmax(x: f16, y: f16) -> (f16); => fmaxf16); (fn fmaximum_num(x: f16, y: f16) -> (f16); => fmaximum_numf16); (fn fmaximumf16(x: f16, y: f16) -> (f16); => fmaximumf16); @@ -202,6 +203,8 @@ libm_helper! { (fn fminimum(x: f16, y: f16) -> (f16); => fminimumf16); (fn fminimum_num(x: f16, y: f16) -> (f16); => fminimum_numf16); (fn fmod(x: f16, y: f16) -> (f16); => fmodf16); + (fn frexp(x: f16) -> (f16, i32); => frexpf16); + (fn ilogb(x: f16) -> (i32); => ilogbf16); (fn ldexp(x: f16, n: i32) -> (f16); => ldexpf16); (fn rint(x: f16) -> (f16); => rintf16); (fn round(x: f16) -> (f16); => roundf16); @@ -231,6 +234,8 @@ libm_helper! { (fn fminimum(x: f128, y: f128) -> (f128); => fminimumf128); (fn fminimum_num(x: f128, y: f128) -> (f128); => fminimum_numf128); (fn fmod(x: f128, y: f128) -> (f128); => fmodf128); + (fn frexp(x: f128) -> (f128, i32); => frexpf128); + (fn ilogb(x: f128) -> (i32); => ilogbf128); (fn ldexp(x: f128, n: i32) -> (f128); => ldexpf128); (fn rint(x: f128) -> (f128); => rintf128); (fn round(x: f128) -> (f128); => roundf128); diff --git a/library/compiler-builtins/libm/src/math/acosh.rs b/library/compiler-builtins/libm/src/math/acosh.rs index 8737bad012c84..2904fc0ed5201 100644 --- a/library/compiler-builtins/libm/src/math/acosh.rs +++ b/library/compiler-builtins/libm/src/math/acosh.rs @@ -1,4 +1,4 @@ -use super::{log, log1p, sqrt}; +use super::{Float, log, log1p, sqrt}; const LN2: f64 = 0.693147180559945309417232121458176568; /* 0x3fe62e42, 0xfefa39ef*/ @@ -9,19 +9,19 @@ const LN2: f64 = 0.693147180559945309417232121458176568; /* 0x3fe62e42, 0xfefa3 /// `x` must be a number greater than or equal to 1. #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn acosh(x: f64) -> f64 { - let u = x.to_bits(); - let e = ((u >> 52) as usize) & 0x7ff; + let ux = x.to_bits(); /* x < 1 domain error is handled in the called functions */ - - if e < 0x3ff + 1 { - /* |x| < 2, up to 2ulp error in [1,1.125] */ - return log1p(x - 1.0 + sqrt((x - 1.0) * (x - 1.0) + 2.0 * (x - 1.0))); - } - if e < 0x3ff + 26 { - /* |x| < 0x1p26 */ - return log(2.0 * x - 1.0 / (x + sqrt(x * x - 1.0))); + if (ux & !f64::SIGN_MASK) < 2_f64.to_bits() { + /* |x| < 2, invalid if x < 1 */ + /* up to 2ulp error in [1,1.125] */ + let x_1 = x - 1.0; + log1p(x_1 + sqrt(x_1 * x_1 + 2.0 * x_1)) + } else if ux < ((1 << 26) as f64).to_bits() { + /* 2 <= x < 0x1p26 */ + log(2.0 * x - 1.0 / (x + sqrt(x * x - 1.0))) + } else { + /* x >= 0x1p26 or x <= -2 or nan */ + log(x) + LN2 } - /* |x| >= 0x1p26 or nan */ - return log(x) + LN2; } diff --git a/library/compiler-builtins/libm/src/math/acoshf.rs b/library/compiler-builtins/libm/src/math/acoshf.rs index 432fa03f11635..d9aafaabdef43 100644 --- a/library/compiler-builtins/libm/src/math/acoshf.rs +++ b/library/compiler-builtins/libm/src/math/acoshf.rs @@ -1,4 +1,4 @@ -use super::{log1pf, logf, sqrtf}; +use super::{Float, log1pf, logf, sqrtf}; const LN2: f32 = 0.693147180559945309417232121458176568; @@ -9,18 +9,19 @@ const LN2: f32 = 0.693147180559945309417232121458176568; /// `x` must be a number greater than or equal to 1. #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn acoshf(x: f32) -> f32 { - let u = x.to_bits(); - let a = u & 0x7fffffff; + let ux = x.to_bits(); - if a < 0x3f800000 + (1 << 23) { - /* |x| < 2, invalid if x < 1 or nan */ + /* x < 1 domain error is handled in the called functions */ + if (ux & !f32::SIGN_MASK) < 2_f32.to_bits() { + /* |x| < 2, invalid if x < 1 */ /* up to 2ulp error in [1,1.125] */ - return log1pf(x - 1.0 + sqrtf((x - 1.0) * (x - 1.0) + 2.0 * (x - 1.0))); + let x_1 = x - 1.0; + log1pf(x_1 + sqrtf(x_1 * x_1 + 2.0 * x_1)) + } else if ux < ((1 << 12) as f32).to_bits() { + /* 2 <= x < 0x1p12 */ + logf(2.0 * x - 1.0 / (x + sqrtf(x * x - 1.0))) + } else { + /* x >= 0x1p12 or x <= -2 or nan */ + logf(x) + LN2 } - if a < 0x3f800000 + (12 << 23) { - /* |x| < 0x1p12 */ - return logf(2.0 * x - 1.0 / (x + sqrtf(x * x - 1.0))); - } - /* x >= 0x1p12 */ - return logf(x) + LN2; } diff --git a/library/compiler-builtins/libm/src/math/arch/aarch64.rs b/library/compiler-builtins/libm/src/math/arch/aarch64.rs deleted file mode 100644 index 8896804b50403..0000000000000 --- a/library/compiler-builtins/libm/src/math/arch/aarch64.rs +++ /dev/null @@ -1,121 +0,0 @@ -//! Architecture-specific support for aarch64 with neon. - -use core::arch::asm; - -pub fn fma(mut x: f64, y: f64, z: f64) -> f64 { - // SAFETY: `fmadd` is available with neon and has no side effects. - unsafe { - asm!( - "fmadd {x:d}, {x:d}, {y:d}, {z:d}", - x = inout(vreg) x, - y = in(vreg) y, - z = in(vreg) z, - options(nomem, nostack, pure) - ); - } - x -} - -pub fn fmaf(mut x: f32, y: f32, z: f32) -> f32 { - // SAFETY: `fmadd` is available with neon and has no side effects. - unsafe { - asm!( - "fmadd {x:s}, {x:s}, {y:s}, {z:s}", - x = inout(vreg) x, - y = in(vreg) y, - z = in(vreg) z, - options(nomem, nostack, pure) - ); - } - x -} - -// NB: `frintx` is technically the correct instruction for C's `rint`. However, in Rust (and LLVM -// by default), `rint` is identical to `roundeven` (no fpenv interaction) so we use the -// side-effect-free `frintn`. -// -// In general, C code that calls Rust's libm should assume that fpenv is ignored. - -pub fn rint(mut x: f64) -> f64 { - // SAFETY: `frintn` is available with neon and has no side effects. - // - // `frintn` is always round-to-nearest which does not match the C specification, but Rust does - // not support rounding modes. - unsafe { - asm!( - "frintn {x:d}, {x:d}", - x = inout(vreg) x, - options(nomem, nostack, pure) - ); - } - x -} - -pub fn rintf(mut x: f32) -> f32 { - // SAFETY: `frintn` is available with neon and has no side effects. - // - // `frintn` is always round-to-nearest which does not match the C specification, but Rust does - // not support rounding modes. - unsafe { - asm!( - "frintn {x:s}, {x:s}", - x = inout(vreg) x, - options(nomem, nostack, pure) - ); - } - x -} - -#[cfg(all(f16_enabled, target_feature = "fp16"))] -pub fn rintf16(mut x: f16) -> f16 { - // SAFETY: `frintn` is available for `f16` with `fp16` (implies `neon`) and has no side effects. - // - // `frintn` is always round-to-nearest which does not match the C specification, but Rust does - // not support rounding modes. - unsafe { - asm!( - "frintn {x:h}, {x:h}", - x = inout(vreg) x, - options(nomem, nostack, pure) - ); - } - x -} - -pub fn sqrt(mut x: f64) -> f64 { - // SAFETY: `fsqrt` is available with neon and has no side effects. - unsafe { - asm!( - "fsqrt {x:d}, {x:d}", - x = inout(vreg) x, - options(nomem, nostack, pure) - ); - } - x -} - -pub fn sqrtf(mut x: f32) -> f32 { - // SAFETY: `fsqrt` is available with neon and has no side effects. - unsafe { - asm!( - "fsqrt {x:s}, {x:s}", - x = inout(vreg) x, - options(nomem, nostack, pure) - ); - } - x -} - -#[cfg(all(f16_enabled, target_feature = "fp16"))] -pub fn sqrtf16(mut x: f16) -> f16 { - // SAFETY: `fsqrt` is available for `f16` with `fp16` (implies `neon`) and has no - // side effects. - unsafe { - asm!( - "fsqrt {x:h}, {x:h}", - x = inout(vreg) x, - options(nomem, nostack, pure) - ); - } - x -} diff --git a/library/compiler-builtins/libm/src/math/arch/aarch64/fma.rs b/library/compiler-builtins/libm/src/math/arch/aarch64/fma.rs new file mode 100644 index 0000000000000..9fd574fad37d2 --- /dev/null +++ b/library/compiler-builtins/libm/src/math/arch/aarch64/fma.rs @@ -0,0 +1,29 @@ +use core::arch::asm; + +pub fn fmaf(mut x: f32, y: f32, z: f32) -> f32 { + // SAFETY: `fmadd` is available with neon and has no side effects. + unsafe { + asm!( + "fmadd {x:s}, {x:s}, {y:s}, {z:s}", + x = inout(vreg) x, + y = in(vreg) y, + z = in(vreg) z, + options(nomem, nostack, pure) + ); + } + x +} + +pub fn fma(mut x: f64, y: f64, z: f64) -> f64 { + // SAFETY: `fmadd` is available with neon and has no side effects. + unsafe { + asm!( + "fmadd {x:d}, {x:d}, {y:d}, {z:d}", + x = inout(vreg) x, + y = in(vreg) y, + z = in(vreg) z, + options(nomem, nostack, pure) + ); + } + x +} diff --git a/library/compiler-builtins/libm/src/math/arch/aarch64/mod.rs b/library/compiler-builtins/libm/src/math/arch/aarch64/mod.rs new file mode 100644 index 0000000000000..0192a3d442aec --- /dev/null +++ b/library/compiler-builtins/libm/src/math/arch/aarch64/mod.rs @@ -0,0 +1,13 @@ +//! Architecture-specific support for aarch64 with neon. + +mod fma; +mod rounding; +mod sqrt; + +pub use fma::{fma, fmaf}; +#[cfg(all(f16_enabled, target_feature = "fp16"))] +pub use rounding::rintf16; +pub use rounding::{rint, rintf}; +#[cfg(all(f16_enabled, target_feature = "fp16"))] +pub use sqrt::sqrtf16; +pub use sqrt::{sqrt, sqrtf}; diff --git a/library/compiler-builtins/libm/src/math/arch/aarch64/rounding.rs b/library/compiler-builtins/libm/src/math/arch/aarch64/rounding.rs new file mode 100644 index 0000000000000..255e8e85b2f0b --- /dev/null +++ b/library/compiler-builtins/libm/src/math/arch/aarch64/rounding.rs @@ -0,0 +1,53 @@ +//! NB: `frintx` is technically the correct instruction for C's `rint`. However, in Rust (and LLVM +//! by default), `rint` is identical to `roundeven` (no fpenv interaction) so we use the +//! side-effect-free `frintn`. +//! +//! In general, C code that calls Rust's libm should assume that fpenv is ignored. + +use core::arch::asm; + +#[cfg(all(f16_enabled, target_feature = "fp16"))] +pub fn rintf16(mut x: f16) -> f16 { + // SAFETY: `frintn` is available for `f16` with `fp16` (implies `neon`) and has no side effects. + // + // `frintn` is always round-to-nearest which does not match the C specification, but Rust does + // not support rounding modes. + unsafe { + asm!( + "frintn {x:h}, {x:h}", + x = inout(vreg) x, + options(nomem, nostack, pure) + ); + } + x +} + +pub fn rintf(mut x: f32) -> f32 { + // SAFETY: `frintn` is available with neon and has no side effects. + // + // `frintn` is always round-to-nearest which does not match the C specification, but Rust does + // not support rounding modes. + unsafe { + asm!( + "frintn {x:s}, {x:s}", + x = inout(vreg) x, + options(nomem, nostack, pure) + ); + } + x +} + +pub fn rint(mut x: f64) -> f64 { + // SAFETY: `frintn` is available with neon and has no side effects. + // + // `frintn` is always round-to-nearest which does not match the C specification, but Rust does + // not support rounding modes. + unsafe { + asm!( + "frintn {x:d}, {x:d}", + x = inout(vreg) x, + options(nomem, nostack, pure) + ); + } + x +} diff --git a/library/compiler-builtins/libm/src/math/arch/aarch64/sqrt.rs b/library/compiler-builtins/libm/src/math/arch/aarch64/sqrt.rs new file mode 100644 index 0000000000000..e3743dfd558aa --- /dev/null +++ b/library/compiler-builtins/libm/src/math/arch/aarch64/sqrt.rs @@ -0,0 +1,39 @@ +use core::arch::asm; + +#[cfg(all(f16_enabled, target_feature = "fp16"))] +pub fn sqrtf16(mut x: f16) -> f16 { + // SAFETY: `fsqrt` is available for `f16` with `fp16` (implies `neon`) and has no + // side effects. + unsafe { + asm!( + "fsqrt {x:h}, {x:h}", + x = inout(vreg) x, + options(nomem, nostack, pure) + ); + } + x +} + +pub fn sqrtf(mut x: f32) -> f32 { + // SAFETY: `fsqrt` is available with neon and has no side effects. + unsafe { + asm!( + "fsqrt {x:s}, {x:s}", + x = inout(vreg) x, + options(nomem, nostack, pure) + ); + } + x +} + +pub fn sqrt(mut x: f64) -> f64 { + // SAFETY: `fsqrt` is available with neon and has no side effects. + unsafe { + asm!( + "fsqrt {x:d}, {x:d}", + x = inout(vreg) x, + options(nomem, nostack, pure) + ); + } + x +} diff --git a/library/compiler-builtins/libm/src/math/arch/i586.rs b/library/compiler-builtins/libm/src/math/arch/i586/exp_all.rs similarity index 53% rename from library/compiler-builtins/libm/src/math/arch/i586.rs rename to library/compiler-builtins/libm/src/math/arch/i586/exp_all.rs index d9bb93fbf5852..020b5c057daaf 100644 --- a/library/compiler-builtins/libm/src/math/arch/i586.rs +++ b/library/compiler-builtins/libm/src/math/arch/i586/exp_all.rs @@ -1,65 +1,3 @@ -//! Architecture-specific support for x86-32 without SSE2 -//! -//! We use an alternative implementation on x86, because the -//! main implementation fails with the x87 FPU used by -//! debian i386, probably due to excess precision issues. -//! -//! See https://github.com/rust-lang/compiler-builtins/pull/976 for discussion on why these -//! functions are implemented in this way. - -pub fn ceil(mut x: f64) -> f64 { - unsafe { - core::arch::asm!( - "fld qword ptr [{x}]", - // Save the FPU control word, using `x` as scratch space. - "fstcw [{x}]", - // Set rounding control to 0b10 (+∞). - "mov word ptr [{x} + 2], 0x0b7f", - "fldcw [{x} + 2]", - // Round. - "frndint", - // Restore FPU control word. - "fldcw [{x}]", - // Save rounded value to memory. - "fstp qword ptr [{x}]", - x = in(reg) &mut x, - // All the x87 FPU stack is used, all registers must be clobbered - out("st(0)") _, out("st(1)") _, - out("st(2)") _, out("st(3)") _, - out("st(4)") _, out("st(5)") _, - out("st(6)") _, out("st(7)") _, - options(nostack), - ); - } - x -} - -pub fn floor(mut x: f64) -> f64 { - unsafe { - core::arch::asm!( - "fld qword ptr [{x}]", - // Save the FPU control word, using `x` as scratch space. - "fstcw [{x}]", - // Set rounding control to 0b01 (-∞). - "mov word ptr [{x} + 2], 0x077f", - "fldcw [{x} + 2]", - // Round. - "frndint", - // Restore FPU control word. - "fldcw [{x}]", - // Save rounded value to memory. - "fstp qword ptr [{x}]", - x = in(reg) &mut x, - // All the x87 FPU stack is used, all registers must be clobbered - out("st(0)") _, out("st(1)") _, - out("st(2)") _, out("st(3)") _, - out("st(4)") _, out("st(5)") _, - out("st(6)") _, out("st(7)") _, - options(nostack), - ); - } - x -} /// Implements the exponential functions with `x87` assembly. /// /// This relies on the instruction `f2xm1`, which computes `2^x - 1` (for diff --git a/library/compiler-builtins/libm/src/math/arch/i586/mod.rs b/library/compiler-builtins/libm/src/math/arch/i586/mod.rs new file mode 100644 index 0000000000000..f80be49fc4b3f --- /dev/null +++ b/library/compiler-builtins/libm/src/math/arch/i586/mod.rs @@ -0,0 +1,14 @@ +//! Architecture-specific support for x86-32 without SSE2 +//! +//! We use an alternative implementation on x86, because the +//! main implementation fails with the x87 FPU used by +//! debian i386, probably due to excess precision issues. +//! +//! See https://github.com/rust-lang/compiler-builtins/pull/976 for discussion on why these +//! functions are implemented in this way. + +mod exp_all; +mod rounding; + +pub use exp_all::{x87_exp, x87_exp2, x87_exp2f, x87_exp10, x87_exp10f, x87_expf}; +pub use rounding::{ceil, floor, rint}; diff --git a/library/compiler-builtins/libm/src/math/arch/i586/rounding.rs b/library/compiler-builtins/libm/src/math/arch/i586/rounding.rs new file mode 100644 index 0000000000000..45bf0adafd304 --- /dev/null +++ b/library/compiler-builtins/libm/src/math/arch/i586/rounding.rs @@ -0,0 +1,103 @@ +pub fn ceil(mut x: f64) -> f64 { + unsafe { + core::arch::asm!( + "fld qword ptr [{x}]", + // Save the FPU control word, using `x` as scratch space. + "fstcw [{x}]", + // Set rounding control to 0b10 (+∞). + "mov word ptr [{x} + 2], 0x0b7f", + "fldcw [{x} + 2]", + // Round. + "frndint", + // Restore FPU control word. + "fldcw [{x}]", + // Save rounded value to memory. + "fstp qword ptr [{x}]", + x = in(reg) &mut x, + // All the x87 FPU stack is used, all registers must be clobbered + out("st(0)") _, out("st(1)") _, + out("st(2)") _, out("st(3)") _, + out("st(4)") _, out("st(5)") _, + out("st(6)") _, out("st(7)") _, + options(nostack), + ); + } + x +} + +pub fn floor(mut x: f64) -> f64 { + unsafe { + core::arch::asm!( + "fld qword ptr [{x}]", + // Save the FPU control word, using `x` as scratch space. + "fstcw [{x}]", + // Set rounding control to 0b01 (-∞). + "mov word ptr [{x} + 2], 0x077f", + "fldcw [{x} + 2]", + // Round. + "frndint", + // Restore FPU control word. + "fldcw [{x}]", + // Save rounded value to memory. + "fstp qword ptr [{x}]", + x = in(reg) &mut x, + // All the x87 FPU stack is used, all registers must be clobbered + out("st(0)") _, out("st(1)") _, + out("st(2)") _, out("st(3)") _, + out("st(4)") _, out("st(5)") _, + out("st(6)") _, out("st(7)") _, + options(nostack), + ); + } + x +} + +/// Note that this respects rounding mode. Because it is UB to have a non-default rounding +/// mode in Rust, this acts as roundeven. +pub fn rint(mut x: f64) -> f64 { + unsafe { + core::arch::asm!( + "fld qword ptr [{x}]", + "frndint", + "fstp qword ptr [{x}]", + x = in(reg) &mut x, + // All the x87 FPU stack is used, all registers must be clobbered + out("st(0)") _, out("st(1)") _, + out("st(2)") _, out("st(3)") _, + out("st(4)") _, out("st(5)") _, + out("st(6)") _, out("st(7)") _, + options(nostack), + ); + } + x +} + +/* FIXME(msrv): after 1.82, the below can be used to compute control words using `asm_const`: + +#[derive(Clone, Copy, Debug, PartialEq)] +enum Precision { + Single, + Double, + Extended, +} + +/// See: Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 1: +/// Basic Architecture, section 8.1.5 x87 FPU Control Word. +const fn make_fpcw(round: Round, prec: Precision) -> u16 { + let exceptions = 0b111111; // Disable all 6 exceptions + let misc = 0b1000000; // reserved field usually set by default + let pc = match prec { + Precision::Single => 0b00, + Precision::Double => 0b10, + Precision::Extended => 0b11, + }; + let rc = match round { + Round::Nearest => 0b00, + Round::Negative => 0b01, + Round::Positive => 0b10, + Round::Zero => 0b11, + }; + (rc << 10) | (pc << 8) | misc | exceptions +} + +*/ diff --git a/library/compiler-builtins/libm/src/math/arch/loongarch/fma.rs b/library/compiler-builtins/libm/src/math/arch/loongarch/fma.rs new file mode 100644 index 0000000000000..8ea24ea6954ff --- /dev/null +++ b/library/compiler-builtins/libm/src/math/arch/loongarch/fma.rs @@ -0,0 +1,31 @@ +use core::arch::asm; + +#[cfg(target_feature = "d")] +pub fn fma(mut x: f64, y: f64, z: f64) -> f64 { + // SAFETY: `fmadd.d` is available with `d and has no side effects. + unsafe { + asm!( + "fmadd.d {x}, {x}, {y}, {z}", + x = inout(freg) x, + y = in(freg) y, + z = in(freg) z, + options(nomem, nostack, pure) + ); + } + x +} + +#[cfg(target_feature = "f")] +pub fn fmaf(mut x: f32, y: f32, z: f32) -> f32 { + // SAFETY: `fmadd.s` is available with `f` and has no side effects. + unsafe { + asm!( + "fmadd.s {x}, {x}, {y}, {z}", + x = inout(freg) x, + y = in(freg) y, + z = in(freg) z, + options(nomem, nostack, pure) + ); + } + x +} diff --git a/library/compiler-builtins/libm/src/math/arch/loongarch/mod.rs b/library/compiler-builtins/libm/src/math/arch/loongarch/mod.rs new file mode 100644 index 0000000000000..90c61e30ec067 --- /dev/null +++ b/library/compiler-builtins/libm/src/math/arch/loongarch/mod.rs @@ -0,0 +1,16 @@ +//! Architecture-specific support for LoongArch with FPU + +mod fma; +mod rounding; +mod sqrt; + +#[cfg(target_feature = "d")] +pub use fma::fma; +#[cfg(target_feature = "f")] +pub use fma::fmaf; +#[cfg(target_feature = "lsx")] +pub use rounding::{rint, rintf}; +#[cfg(target_feature = "d")] +pub use sqrt::sqrt; +#[cfg(target_feature = "f")] +pub use sqrt::sqrtf; diff --git a/library/compiler-builtins/libm/src/math/arch/loongarch/rounding.rs b/library/compiler-builtins/libm/src/math/arch/loongarch/rounding.rs new file mode 100644 index 0000000000000..ebbef09fea127 --- /dev/null +++ b/library/compiler-builtins/libm/src/math/arch/loongarch/rounding.rs @@ -0,0 +1,39 @@ +//! NB: `frint.{s.d}` is technically the correct instruction for C's `rint`. +//! However, in Rust (and LLVM by default), `rint` is identical to `roundeven` +//! (no fpenv interaction) so we use the side-effect-free `vfrintrne.{s,d}`. +//! +//! In general, C code that calls Rust's libm should assume that fpenv is ignored. + +use core::arch::asm; + +#[cfg(target_feature = "lsx")] +pub fn rint(mut x: f64) -> f64 { + // SAFETY: `vfrintrne.d` is available with `lsx` and has no side effects. + // + // `vfrintrne.d` is always round-to-nearest which does not match the + // C specification, but Rust does not support rounding modes. + unsafe { + asm!( + "vfrintrne.d {x:w}, {x:w}", + x = inout(freg) x, + options(nomem, nostack, pure) + ); + } + x +} + +#[cfg(target_feature = "lsx")] +pub fn rintf(mut x: f32) -> f32 { + // SAFETY: `vfrintrne.s` is available with `lsx` and has no side effects. + // + // `vfrintrne.s` is always round-to-nearest which does not match the + // C specification, but Rust does not support rounding modes. + unsafe { + asm!( + "vfrintrne.s {x:w}, {x:w}", + x = inout(freg) x, + options(nomem, nostack, pure) + ); + } + x +} diff --git a/library/compiler-builtins/libm/src/math/arch/loongarch/sqrt.rs b/library/compiler-builtins/libm/src/math/arch/loongarch/sqrt.rs new file mode 100644 index 0000000000000..e23d3facc0375 --- /dev/null +++ b/library/compiler-builtins/libm/src/math/arch/loongarch/sqrt.rs @@ -0,0 +1,27 @@ +use core::arch::asm; + +#[cfg(target_feature = "d")] +pub fn sqrt(mut x: f64) -> f64 { + // SAFETY: `fsqrt.d` is available with `d` and has no side effects. + unsafe { + asm!( + "fsqrt.d {x}, {x}", + x = inout(freg) x, + options(nomem, nostack, pure) + ); + } + x +} + +#[cfg(target_feature = "f")] +pub fn sqrtf(mut x: f32) -> f32 { + // SAFETY: `fsqrt.s` is available with `f` and has no side effects. + unsafe { + asm!( + "fsqrt.s {x}, {x}", + x = inout(freg) x, + options(nomem, nostack, pure) + ); + } + x +} diff --git a/library/compiler-builtins/libm/src/math/arch/mod.rs b/library/compiler-builtins/libm/src/math/arch/mod.rs index ba859c679d0db..ab2c4a17760b4 100644 --- a/library/compiler-builtins/libm/src/math/arch/mod.rs +++ b/library/compiler-builtins/libm/src/math/arch/mod.rs @@ -6,21 +6,24 @@ //! well as improving things when these routines are called as part of other implementations. // Most implementations should be defined here, to ensure they are not made available when -// soft floats are required. -#[cfg(arch_enabled)] -cfg_if! { - if #[cfg(all(target_arch = "wasm32", intrinsics_enabled))] { +// soft floats are required. Primarily gated on the `arch` feature, Miri does not support inline +// assembly. +#[cfg(all(feature = "arch", not(miri)))] +cfg_select_nofmt! { + all(target_arch = "wasm32", intrinsics_enabled) => { mod wasm32; pub use wasm32::{ ceil, ceilf, fabs, fabsf, floor, floorf, rint, rintf, sqrt, sqrtf, trunc, truncf, }; - } else if #[cfg(target_feature = "sse2")] { + } + target_feature = "sse2" => { mod x86; pub use x86::{sqrt, sqrtf, fma, fmaf}; - } else if #[cfg(all( + } + all( any(target_arch = "aarch64", target_arch = "arm64ec"), target_feature = "neon" - ))] { + ) => { mod aarch64; pub use aarch64::{ @@ -38,18 +41,39 @@ cfg_if! { sqrtf16, }; } + any(target_arch = "loongarch32", target_arch = "loongarch64") => { + mod loongarch; + + #[cfg(target_feature = "d")] + pub use loongarch::fma; + #[cfg(target_feature = "f")] + pub use loongarch::fmaf; + #[cfg(target_feature = "lsx")] + pub use loongarch::{rint, rintf}; + #[cfg(target_feature = "d")] + pub use loongarch::sqrt; + #[cfg(target_feature = "f")] + pub use loongarch::sqrtf; + } + _ => {} } // There are certain architecture-specific implementations that are needed for correctness -// even with `force-soft-float`. These are configured here. -cfg_if! { - if #[cfg(all(target_arch = "x86", not(target_feature = "sse2")))] { +// even with `arch` disabled. These are configured here. +cfg_select_nofmt! { + x86_no_sse2 => { mod i586; - pub use i586::{ceil, floor}; - } -} -cfg_if! { - if #[cfg(x86_no_sse)] { - pub use i586::{x87_exp10f, x87_exp10, x87_expf, x87_exp, x87_exp2f, x87_exp2}; + pub use i586::{ + ceil, + floor, + rint, + x87_exp, + x87_exp10, + x87_exp10f, + x87_exp2, + x87_exp2f, + x87_expf, + }; } + _ => {} } diff --git a/library/compiler-builtins/libm/src/math/arch/wasm32/fabs.rs b/library/compiler-builtins/libm/src/math/arch/wasm32/fabs.rs new file mode 100644 index 0000000000000..1f5ff3f28131b --- /dev/null +++ b/library/compiler-builtins/libm/src/math/arch/wasm32/fabs.rs @@ -0,0 +1,7 @@ +pub fn fabsf(x: f32) -> f32 { + x.abs() +} + +pub fn fabs(x: f64) -> f64 { + x.abs() +} diff --git a/library/compiler-builtins/libm/src/math/arch/wasm32/mod.rs b/library/compiler-builtins/libm/src/math/arch/wasm32/mod.rs new file mode 100644 index 0000000000000..b262e0108155e --- /dev/null +++ b/library/compiler-builtins/libm/src/math/arch/wasm32/mod.rs @@ -0,0 +1,10 @@ +//! Wasm has builtins for simple float operations. Use the unstable `core::arch` intrinsics which +//! are significantly faster than soft float operations. + +mod fabs; +mod rounding; +mod sqrt; + +pub use fabs::{fabs, fabsf}; +pub use rounding::{ceil, ceilf, floor, floorf, rint, rintf, trunc, truncf}; +pub use sqrt::{sqrt, sqrtf}; diff --git a/library/compiler-builtins/libm/src/math/arch/wasm32.rs b/library/compiler-builtins/libm/src/math/arch/wasm32/rounding.rs similarity index 76% rename from library/compiler-builtins/libm/src/math/arch/wasm32.rs rename to library/compiler-builtins/libm/src/math/arch/wasm32/rounding.rs index de80c8a581726..1c8914e4561c1 100644 --- a/library/compiler-builtins/libm/src/math/arch/wasm32.rs +++ b/library/compiler-builtins/libm/src/math/arch/wasm32/rounding.rs @@ -1,50 +1,34 @@ //! Wasm has builtins for simple float operations. Use the unstable `core::arch` intrinsics which //! are significantly faster than soft float operations. -pub fn ceil(x: f64) -> f64 { - core::arch::wasm32::f64_ceil(x) -} - pub fn ceilf(x: f32) -> f32 { core::arch::wasm32::f32_ceil(x) } -pub fn fabs(x: f64) -> f64 { - x.abs() -} - -pub fn fabsf(x: f32) -> f32 { - x.abs() -} - -pub fn floor(x: f64) -> f64 { - core::arch::wasm32::f64_floor(x) +pub fn ceil(x: f64) -> f64 { + core::arch::wasm32::f64_ceil(x) } pub fn floorf(x: f32) -> f32 { core::arch::wasm32::f32_floor(x) } -pub fn rint(x: f64) -> f64 { - core::arch::wasm32::f64_nearest(x) +pub fn floor(x: f64) -> f64 { + core::arch::wasm32::f64_floor(x) } pub fn rintf(x: f32) -> f32 { core::arch::wasm32::f32_nearest(x) } -pub fn sqrt(x: f64) -> f64 { - core::arch::wasm32::f64_sqrt(x) +pub fn rint(x: f64) -> f64 { + core::arch::wasm32::f64_nearest(x) } -pub fn sqrtf(x: f32) -> f32 { - core::arch::wasm32::f32_sqrt(x) +pub fn truncf(x: f32) -> f32 { + core::arch::wasm32::f32_trunc(x) } pub fn trunc(x: f64) -> f64 { core::arch::wasm32::f64_trunc(x) } - -pub fn truncf(x: f32) -> f32 { - core::arch::wasm32::f32_trunc(x) -} diff --git a/library/compiler-builtins/libm/src/math/arch/wasm32/sqrt.rs b/library/compiler-builtins/libm/src/math/arch/wasm32/sqrt.rs new file mode 100644 index 0000000000000..1d73e4ddcfe96 --- /dev/null +++ b/library/compiler-builtins/libm/src/math/arch/wasm32/sqrt.rs @@ -0,0 +1,7 @@ +pub fn sqrtf(x: f32) -> f32 { + core::arch::wasm32::f32_sqrt(x) +} + +pub fn sqrt(x: f64) -> f64 { + core::arch::wasm32::f64_sqrt(x) +} diff --git a/library/compiler-builtins/libm/src/math/arch/x86/detect.rs b/library/compiler-builtins/libm/src/math/arch/x86/detect.rs index ca785470b806d..983818b5b5e47 100644 --- a/library/compiler-builtins/libm/src/math/arch/x86/detect.rs +++ b/library/compiler-builtins/libm/src/math/arch/x86/detect.rs @@ -1,5 +1,5 @@ -// Using runtime feature detection requires atomics. Currently there are no x86 targets -// that support sse but not `AtomicPtr`. +//! Using runtime feature detection requires atomics. Currently there are no x86 targets +//! that support sse but not `AtomicPtr`. #[cfg(target_arch = "x86")] use core::arch::x86::{__cpuid, __cpuid_count, _xgetbv, CpuidResult}; diff --git a/library/compiler-builtins/libm/src/math/arch/x86/mod.rs b/library/compiler-builtins/libm/src/math/arch/x86/mod.rs new file mode 100644 index 0000000000000..279bf35b9c9e0 --- /dev/null +++ b/library/compiler-builtins/libm/src/math/arch/x86/mod.rs @@ -0,0 +1,8 @@ +//! Architecture-specific support for x86-32 with SSE2 (i686) and x86-64. + +mod detect; +mod fma; +mod sqrt; + +pub use fma::{fma, fmaf}; +pub use sqrt::{sqrt, sqrtf}; diff --git a/library/compiler-builtins/libm/src/math/arch/x86.rs b/library/compiler-builtins/libm/src/math/arch/x86/sqrt.rs similarity index 85% rename from library/compiler-builtins/libm/src/math/arch/x86.rs rename to library/compiler-builtins/libm/src/math/arch/x86/sqrt.rs index 454aa285074d6..d172e1239f1a9 100644 --- a/library/compiler-builtins/libm/src/math/arch/x86.rs +++ b/library/compiler-builtins/libm/src/math/arch/x86/sqrt.rs @@ -1,10 +1,3 @@ -//! Architecture-specific support for x86-32 and x86-64 with SSE2 - -mod detect; -mod fma; - -pub use fma::{fma, fmaf}; - pub fn sqrtf(mut x: f32) -> f32 { // SAFETY: `sqrtss` is part of `sse2`, which this module is gated behind. It has no memory // access or side effects. diff --git a/library/compiler-builtins/libm/src/math/atan2.rs b/library/compiler-builtins/libm/src/math/atan2.rs index 51456e409b8cc..19be7584bbf07 100644 --- a/library/compiler-builtins/libm/src/math/atan2.rs +++ b/library/compiler-builtins/libm/src/math/atan2.rs @@ -119,7 +119,7 @@ mod tests { use super::*; #[test] - #[cfg_attr(x86_no_sse, ignore = "FIXME(i586): possible incorrect rounding")] + #[cfg_attr(x86_no_sse2, ignore = "FIXME(i586): possible incorrect rounding")] fn sanity_check() { assert_eq!(atan2(0.0, 1.0), 0.0); assert_eq!(atan2(0.0, -1.0), PI); diff --git a/library/compiler-builtins/libm/src/math/cbrt.rs b/library/compiler-builtins/libm/src/math/cbrt.rs index e905e15f13fbe..b6d24c807eb00 100644 --- a/library/compiler-builtins/libm/src/math/cbrt.rs +++ b/library/compiler-builtins/libm/src/math/cbrt.rs @@ -208,7 +208,7 @@ mod tests { #[test] fn spot_checks() { - if !cfg!(x86_no_sse) { + if !cfg!(x86_no_sse2) { // Exposes a rounding mode problem. Ignored on i586 because of inaccurate FMA. assert_biteq!( cbrt(f64::from_bits(0xf7f792b28f600000)), diff --git a/library/compiler-builtins/libm/src/math/ceil.rs b/library/compiler-builtins/libm/src/math/ceil.rs index 2cac49f29ba97..c8fb17e7ddca1 100644 --- a/library/compiler-builtins/libm/src/math/ceil.rs +++ b/library/compiler-builtins/libm/src/math/ceil.rs @@ -1,10 +1,12 @@ +use super::generic; + /// Ceil (f16) /// /// Finds the nearest integer greater than or equal to `x`. #[cfg(f16_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn ceilf16(x: f16) -> f16 { - super::generic::ceil(x) + generic::ceil_status(x).val } /// Ceil (f32) @@ -18,7 +20,7 @@ pub fn ceilf(x: f32) -> f32 { args: x, } - super::generic::ceil(x) + generic::ceil_status(x).val } /// Ceil (f64) @@ -29,11 +31,11 @@ pub fn ceil(x: f64) -> f64 { select_implementation! { name: ceil, use_arch: all(target_arch = "wasm32", intrinsics_enabled), - use_arch_required: all(target_arch = "x86", not(target_feature = "sse2")), + use_arch_required: x86_no_sse2, args: x, } - super::generic::ceil(x) + generic::ceil_status(x).val } /// Ceil (f128) @@ -42,5 +44,105 @@ pub fn ceil(x: f64) -> f64 { #[cfg(f128_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn ceilf128(x: f128) -> f128 { - super::generic::ceil(x) + generic::ceil_status(x).val +} + +#[cfg(test)] +mod tests { + use super::*; + use crate::support::{Float, FpResult, Hex, Status}; + + macro_rules! cases { + ($f:ty) => { + [ + // roundtrip + (0.0, 0.0, Status::OK), + (-0.0, -0.0, Status::OK), + (1.0, 1.0, Status::OK), + (-1.0, -1.0, Status::OK), + (<$f>::INFINITY, <$f>::INFINITY, Status::OK), + (<$f>::NEG_INFINITY, <$f>::NEG_INFINITY, Status::OK), + // with rounding + (0.1, 1.0, Status::INEXACT), + (-0.1, -0.0, Status::INEXACT), + (0.5, 1.0, Status::INEXACT), + (-0.5, -0.0, Status::INEXACT), + (0.9, 1.0, Status::INEXACT), + (-0.9, -0.0, Status::INEXACT), + (1.1, 2.0, Status::INEXACT), + (-1.1, -1.0, Status::INEXACT), + (1.5, 2.0, Status::INEXACT), + (-1.5, -1.0, Status::INEXACT), + (1.9, 2.0, Status::INEXACT), + (-1.9, -1.0, Status::INEXACT), + ] + }; + } + + #[track_caller] + fn check(f: fn(F) -> F, cases: &[(F, F, Status)]) { + for &(x, exp_res, exp_stat) in cases { + let FpResult { val, status } = generic::ceil_status(x); + assert_biteq!(val, exp_res, "generic::ceil_status({x:?}) ({})", Hex(x)); + assert_eq!( + status, + exp_stat, + "{x:?} {} -> {exp_res:?} {}", + Hex(x), + Hex(exp_res) + ); + let val = f(x); + assert_biteq!(val, exp_res, "ceil({x:?}) ({})", Hex(x)); + } + } + + #[test] + #[cfg(f16_enabled)] + fn check_f16() { + check::(ceilf16, &cases!(f16)); + check::( + ceilf16, + &[ + (hf16!("0x1p10"), hf16!("0x1p10"), Status::OK), + (hf16!("-0x1p10"), hf16!("-0x1p10"), Status::OK), + ], + ); + } + + #[test] + fn check_f32() { + check::(ceilf, &cases!(f32)); + check::( + ceilf, + &[ + (hf32!("0x1p23"), hf32!("0x1p23"), Status::OK), + (hf32!("-0x1p23"), hf32!("-0x1p23"), Status::OK), + ], + ); + } + + #[test] + fn check_f64() { + check::(ceil, &cases!(f64)); + check::( + ceil, + &[ + (hf64!("0x1p52"), hf64!("0x1p52"), Status::OK), + (hf64!("-0x1p52"), hf64!("-0x1p52"), Status::OK), + ], + ); + } + + #[test] + #[cfg(f128_enabled)] + fn check_f128() { + check::(ceilf128, &cases!(f128)); + check::( + ceilf128, + &[ + (hf128!("0x1p112"), hf128!("0x1p112"), Status::OK), + (hf128!("-0x1p112"), hf128!("-0x1p112"), Status::OK), + ], + ); + } } diff --git a/library/compiler-builtins/libm/src/math/exp.rs b/library/compiler-builtins/libm/src/math/exp.rs index cb939ad5d8bf2..05203985bf313 100644 --- a/library/compiler-builtins/libm/src/math/exp.rs +++ b/library/compiler-builtins/libm/src/math/exp.rs @@ -85,7 +85,7 @@ const P5: f64 = 4.13813679705723846039e-08; /* 0x3E663769, 0x72BEA4D0 */ pub fn exp(mut x: f64) -> f64 { select_implementation! { name: x87_exp, - use_arch_required: x86_no_sse, + use_arch_required: x86_no_sse2, args: x, } diff --git a/library/compiler-builtins/libm/src/math/exp10.rs b/library/compiler-builtins/libm/src/math/exp10.rs index e0af1945b922a..452b29a2c3d14 100644 --- a/library/compiler-builtins/libm/src/math/exp10.rs +++ b/library/compiler-builtins/libm/src/math/exp10.rs @@ -11,7 +11,7 @@ const P10: &[f64] = &[ pub fn exp10(x: f64) -> f64 { select_implementation! { name: x87_exp10, - use_arch_required: x86_no_sse, + use_arch_required: x86_no_sse2, args: x, } diff --git a/library/compiler-builtins/libm/src/math/exp10f.rs b/library/compiler-builtins/libm/src/math/exp10f.rs index f0a311c2d1915..4b9e949fbbe97 100644 --- a/library/compiler-builtins/libm/src/math/exp10f.rs +++ b/library/compiler-builtins/libm/src/math/exp10f.rs @@ -11,7 +11,7 @@ const P10: &[f32] = &[ pub fn exp10f(x: f32) -> f32 { select_implementation! { name: x87_exp10f, - use_arch_required: x86_no_sse, + use_arch_required: x86_no_sse2, args: x, } diff --git a/library/compiler-builtins/libm/src/math/exp2.rs b/library/compiler-builtins/libm/src/math/exp2.rs index 08b71587f6de5..cc2aa434c4e9d 100644 --- a/library/compiler-builtins/libm/src/math/exp2.rs +++ b/library/compiler-builtins/libm/src/math/exp2.rs @@ -326,7 +326,7 @@ static TBL: [u64; TBLSIZE * 2] = [ pub fn exp2(mut x: f64) -> f64 { select_implementation! { name: x87_exp2, - use_arch_required: x86_no_sse, + use_arch_required: x86_no_sse2, args: x, } @@ -380,7 +380,7 @@ pub fn exp2(mut x: f64) -> f64 { let mut i0 = ui as u32; i0 = i0.wrapping_add(TBLSIZE as u32 / 2); let ku = i0 / TBLSIZE as u32 * TBLSIZE as u32; - let ki = div!(ku as i32, TBLSIZE as i32); + let ki = (ku as i32) / TBLSIZE as i32; i0 %= TBLSIZE as u32; let uf = f64::from_bits(ui) - redux; let mut z = x - uf; diff --git a/library/compiler-builtins/libm/src/math/exp2f.rs b/library/compiler-builtins/libm/src/math/exp2f.rs index ceff6822c5969..44872d74b0ca8 100644 --- a/library/compiler-builtins/libm/src/math/exp2f.rs +++ b/library/compiler-builtins/libm/src/math/exp2f.rs @@ -77,7 +77,7 @@ static EXP2FT: [u64; TBLSIZE] = [ pub fn exp2f(mut x: f32) -> f32 { select_implementation! { name: x87_exp2f, - use_arch_required: x86_no_sse, + use_arch_required: x86_no_sse2, args: x, } diff --git a/library/compiler-builtins/libm/src/math/expf.rs b/library/compiler-builtins/libm/src/math/expf.rs index 5541ab79a9c14..d1185ff2c4621 100644 --- a/library/compiler-builtins/libm/src/math/expf.rs +++ b/library/compiler-builtins/libm/src/math/expf.rs @@ -34,7 +34,7 @@ const P2: f32 = -2.7667332906e-3; /* -0xb55215.0p-32 */ pub fn expf(mut x: f32) -> f32 { select_implementation! { name: x87_expf, - use_arch_required: x86_no_sse, + use_arch_required: x86_no_sse2, args: x, } diff --git a/library/compiler-builtins/libm/src/math/fdim.rs b/library/compiler-builtins/libm/src/math/fdim.rs index dac409e86b135..b61630847f808 100644 --- a/library/compiler-builtins/libm/src/math/fdim.rs +++ b/library/compiler-builtins/libm/src/math/fdim.rs @@ -2,8 +2,8 @@ /// /// Determines the positive difference between arguments, returning: /// * x - y if x > y, or -/// * +0 if x <= y, or -/// * NAN if either argument is NAN. +/// * +0 if x <= y, or +/// * NAN if either argument is NAN. /// /// A range error may occur. #[cfg(f16_enabled)] @@ -16,8 +16,8 @@ pub fn fdimf16(x: f16, y: f16) -> f16 { /// /// Determines the positive difference between arguments, returning: /// * x - y if x > y, or -/// * +0 if x <= y, or -/// * NAN if either argument is NAN. +/// * +0 if x <= y, or +/// * NAN if either argument is NAN. /// /// A range error may occur. #[cfg_attr(assert_no_panic, no_panic::no_panic)] @@ -29,8 +29,8 @@ pub fn fdimf(x: f32, y: f32) -> f32 { /// /// Determines the positive difference between arguments, returning: /// * x - y if x > y, or -/// * +0 if x <= y, or -/// * NAN if either argument is NAN. +/// * +0 if x <= y, or +/// * NAN if either argument is NAN. /// /// A range error may occur. #[cfg_attr(assert_no_panic, no_panic::no_panic)] @@ -42,8 +42,8 @@ pub fn fdim(x: f64, y: f64) -> f64 { /// /// Determines the positive difference between arguments, returning: /// * x - y if x > y, or -/// * +0 if x <= y, or -/// * NAN if either argument is NAN. +/// * +0 if x <= y, or +/// * NAN if either argument is NAN. /// /// A range error may occur. #[cfg(f128_enabled)] @@ -51,3 +51,101 @@ pub fn fdim(x: f64, y: f64) -> f64 { pub fn fdimf128(x: f128, y: f128) -> f128 { super::generic::fdim(x, y) } + +#[cfg(test)] +mod tests { + use crate::support::{Float, Hex}; + + macro_rules! cases { + ($f:ty) => { + [ + // x = -inf + (<$f>::NEG_INFINITY, <$f>::NEG_INFINITY, 0.0), + (<$f>::NEG_INFINITY, -1.0, 0.0), + (<$f>::NEG_INFINITY, -0.0, 0.0), + (<$f>::NEG_INFINITY, 0.0, 0.0), + (<$f>::NEG_INFINITY, 1.0, 0.0), + (<$f>::NEG_INFINITY, <$f>::INFINITY, 0.0), + (<$f>::NEG_INFINITY, <$f>::NAN, <$f>::NAN), + // x = -1.0 + (-1.0, <$f>::NEG_INFINITY, <$f>::INFINITY), + (-1.0, -1.0, 0.0), + (-1.0, -0.0, 0.0), + (-1.0, 0.0, 0.0), + (-1.0, 1.0, 0.0), + (-1.0, <$f>::INFINITY, 0.0), + (-1.0, <$f>::NAN, <$f>::NAN), + // x = -0.0 + (-0.0, <$f>::NEG_INFINITY, <$f>::INFINITY), + (-0.0, -1.0, 1.0), + (-0.0, -0.0, 0.0), + (-0.0, 0.0, 0.0), + (-0.0, 1.0, 0.0), + (-0.0, <$f>::INFINITY, 0.0), + (-0.0, <$f>::NAN, <$f>::NAN), + // x = 0.0 + (0.0, <$f>::NEG_INFINITY, <$f>::INFINITY), + (0.0, -1.0, 1.0), + (0.0, -0.0, 0.0), + (0.0, 0.0, 0.0), + (0.0, 1.0, 0.0), + (0.0, <$f>::INFINITY, 0.0), + (0.0, <$f>::NAN, <$f>::NAN), + // x = 1.0 + (1.0, <$f>::NEG_INFINITY, <$f>::INFINITY), + (1.0, -1.0, 2.0), + (1.0, -0.0, 1.0), + (1.0, 0.0, 1.0), + (1.0, 1.0, 0.0), + (1.0, <$f>::INFINITY, 0.0), + (1.0, <$f>::NAN, <$f>::NAN), + // x = inf + (<$f>::INFINITY, <$f>::NEG_INFINITY, <$f>::INFINITY), + (<$f>::INFINITY, -1.0, <$f>::INFINITY), + (<$f>::INFINITY, -0.0, <$f>::INFINITY), + (<$f>::INFINITY, 0.0, <$f>::INFINITY), + (<$f>::INFINITY, 1.0, <$f>::INFINITY), + (<$f>::INFINITY, <$f>::INFINITY, 0.0), + (<$f>::INFINITY, <$f>::NAN, <$f>::NAN), + // x = nan + (<$f>::NAN, <$f>::NEG_INFINITY, <$f>::NAN), + (<$f>::NAN, -1.0, <$f>::NAN), + (<$f>::NAN, -0.0, <$f>::NAN), + (<$f>::NAN, 0.0, <$f>::NAN), + (<$f>::NAN, 1.0, <$f>::NAN), + (<$f>::NAN, <$f>::INFINITY, <$f>::NAN), + (<$f>::NAN, <$f>::NAN, <$f>::NAN), + ] + }; + } + + #[track_caller] + fn check(f: fn(F, F) -> F, cases: &[(F, F, F)]) { + for &(x, y, exp_res) in cases { + let val = f(x, y); + assert_biteq!(val, exp_res, "fdim({x:?}, {y:?}) ({} {})", Hex(x), Hex(y)); + } + } + + #[test] + #[cfg(f16_enabled)] + fn check_f16() { + check::(super::super::fdimf16, &cases!(f16)); + } + + #[test] + fn check_f32() { + check::(super::super::fdimf, &cases!(f32)); + } + + #[test] + fn check_f64() { + check::(super::super::fdim, &cases!(f64)); + } + + #[test] + #[cfg(f128_enabled)] + fn check_f128() { + check::(super::super::fdimf128, &cases!(f128)); + } +} diff --git a/library/compiler-builtins/libm/src/math/floor.rs b/library/compiler-builtins/libm/src/math/floor.rs index 7241c427f6463..2b1e31c0564b0 100644 --- a/library/compiler-builtins/libm/src/math/floor.rs +++ b/library/compiler-builtins/libm/src/math/floor.rs @@ -1,10 +1,12 @@ +use super::generic; + /// Floor (f16) /// /// Finds the nearest integer less than or equal to `x`. #[cfg(f16_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn floorf16(x: f16) -> f16 { - return super::generic::floor(x); + return generic::floor_status(x).val; } /// Floor (f64) @@ -15,11 +17,11 @@ pub fn floor(x: f64) -> f64 { select_implementation! { name: floor, use_arch: all(target_arch = "wasm32", intrinsics_enabled), - use_arch_required: all(target_arch = "x86", not(target_feature = "sse2")), + use_arch_required: x86_no_sse2, args: x, } - return super::generic::floor(x); + return generic::floor_status(x).val; } /// Floor (f32) @@ -33,7 +35,7 @@ pub fn floorf(x: f32) -> f32 { args: x, } - return super::generic::floor(x); + return generic::floor_status(x).val; } /// Floor (f128) @@ -42,5 +44,105 @@ pub fn floorf(x: f32) -> f32 { #[cfg(f128_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn floorf128(x: f128) -> f128 { - return super::generic::floor(x); + return generic::floor_status(x).val; +} + +#[cfg(test)] +mod tests { + use super::*; + use crate::support::{Float, FpResult, Hex, Status}; + + macro_rules! cases { + ($f:ty) => { + [ + // roundtrip + (0.0, 0.0, Status::OK), + (-0.0, -0.0, Status::OK), + (1.0, 1.0, Status::OK), + (-1.0, -1.0, Status::OK), + (<$f>::INFINITY, <$f>::INFINITY, Status::OK), + (<$f>::NEG_INFINITY, <$f>::NEG_INFINITY, Status::OK), + // with rounding + (0.1, 0.0, Status::INEXACT), + (-0.1, -1.0, Status::INEXACT), + (0.5, 0.0, Status::INEXACT), + (-0.5, -1.0, Status::INEXACT), + (0.9, 0.0, Status::INEXACT), + (-0.9, -1.0, Status::INEXACT), + (1.1, 1.0, Status::INEXACT), + (-1.1, -2.0, Status::INEXACT), + (1.5, 1.0, Status::INEXACT), + (-1.5, -2.0, Status::INEXACT), + (1.9, 1.0, Status::INEXACT), + (-1.9, -2.0, Status::INEXACT), + ] + }; + } + + #[track_caller] + fn check(f: fn(F) -> F, cases: &[(F, F, Status)]) { + for &(x, exp_res, exp_stat) in cases { + let FpResult { val, status } = generic::floor_status(x); + assert_biteq!(val, exp_res, "generic::floor_status({x:?}) ({})", Hex(x)); + assert_eq!( + status, + exp_stat, + "{x:?} {} -> {exp_res:?} {}", + Hex(x), + Hex(exp_res) + ); + let val = f(x); + assert_biteq!(val, exp_res, "floor({x:?}) ({})", Hex(x)); + } + } + + #[test] + #[cfg(f16_enabled)] + fn check_f16() { + check::(floorf16, &cases!(f16)); + check::( + floorf16, + &[ + (hf16!("0x1p10"), hf16!("0x1p10"), Status::OK), + (hf16!("-0x1p10"), hf16!("-0x1p10"), Status::OK), + ], + ); + } + + #[test] + fn check_f32() { + check::(floorf, &cases!(f32)); + check::( + floorf, + &[ + (hf32!("0x1p23"), hf32!("0x1p23"), Status::OK), + (hf32!("-0x1p23"), hf32!("-0x1p23"), Status::OK), + ], + ); + } + + #[test] + fn check_f64() { + check::(floor, &cases!(f64)); + check::( + floor, + &[ + (hf64!("0x1p52"), hf64!("0x1p52"), Status::OK), + (hf64!("-0x1p52"), hf64!("-0x1p52"), Status::OK), + ], + ); + } + + #[test] + #[cfg(f128_enabled)] + fn check_f128() { + check::(floorf128, &cases!(f128)); + check::( + floorf128, + &[ + (hf128!("0x1p112"), hf128!("0x1p112"), Status::OK), + (hf128!("-0x1p112"), hf128!("-0x1p112"), Status::OK), + ], + ); + } } diff --git a/library/compiler-builtins/libm/src/math/fma.rs b/library/compiler-builtins/libm/src/math/fma.rs index 70e6de768fab0..e6b9e8fa1b60b 100644 --- a/library/compiler-builtins/libm/src/math/fma.rs +++ b/library/compiler-builtins/libm/src/math/fma.rs @@ -1,16 +1,7 @@ -/* SPDX-License-Identifier: MIT */ -/* origin: musl src/math/fma.c, fmaf.c Ported to generic Rust algorithm in 2025, TG. */ - use super::generic; use crate::support::Round; -// Placeholder so we can have `fmaf16` in the `Float` trait. -#[allow(unused)] -#[cfg(f16_enabled)] -#[cfg_attr(assert_no_panic, no_panic::no_panic)] -pub(crate) fn fmaf16(_x: f16, _y: f16, _z: f16) -> f16 { - unimplemented!() -} +/* See `fmaf16.rs` for that implementation */ /// Floating multiply add (f32) /// @@ -21,6 +12,7 @@ pub fn fmaf(x: f32, y: f32, z: f32) -> f32 { name: fmaf, use_arch: any( all(target_arch = "aarch64", target_feature = "neon"), + all(any(target_arch = "loongarch32", target_arch = "loongarch64"), target_feature = "f"), target_feature = "sse2", ), args: x, y, z, @@ -38,6 +30,7 @@ pub fn fma(x: f64, y: f64, z: f64) -> f64 { name: fma, use_arch: any( all(target_arch = "aarch64", target_feature = "neon"), + all(any(target_arch = "loongarch32", target_arch = "loongarch64"), target_feature = "d"), target_feature = "sse2", ), args: x, y, z, @@ -58,42 +51,83 @@ pub fn fmaf128(x: f128, y: f128, z: f128) -> f128 { #[cfg(test)] mod tests { use super::*; - use crate::support::{CastFrom, CastInto, Float, FpResult, HInt, MinInt, Round, Status}; - - /// Test the generic `fma_round` algorithm for a given float. - fn spec_test(f: impl Fn(F, F, F) -> F) - where - F: Float, - F: CastFrom, - F: CastFrom, - F::Int: HInt, - u32: CastInto, - { - let x = F::from_bits(F::Int::ONE); - let y = F::from_bits(F::Int::ONE); - let z = F::ZERO; - - // 754-2020 says "When the exact result of (a × b) + c is non-zero yet the result of - // fusedMultiplyAdd is zero because of rounding, the zero result takes the sign of the - // exact result" - assert_biteq!(f(x, y, z), F::ZERO); - assert_biteq!(f(x, -y, z), F::NEG_ZERO); - assert_biteq!(f(-x, y, z), F::NEG_ZERO); - assert_biteq!(f(-x, -y, z), F::ZERO); + use crate::support::{Float, FpResult, Hex, Round, Status}; + + macro_rules! cases { + ($f:ty) => { + [ + // Simple + (0.0, 0.0, 0.0, 0.0), + (1.0, 1.0, 0.0, 1.0), + (1.0, 0.0, 1.0, 1.0), + // Sign checks + (1.0, 1.0, 1.0, 2.0), + (1.0, 1.0, -1.0, 0.0), + (1.0, -1.0, 1.0, 0.0), + (1.0, -1.0, -1.0, -2.0), + (-1.0, 1.0, 1.0, 0.0), + (-1.0, 1.0, -1.0, -2.0), + (-1.0, -1.0, 1.0, 2.0), + (-1.0, -1.0, -1.0, 0.0), + + // Roundtrip + (<$f>::MAX, 1.0, 0.0, <$f>::MAX), + (<$f>::MAX, <$f>::MAX, 1.0, <$f>::INFINITY), + (<$f>::MAX, 1.0, -<$f>::MAX, 0.0), + (-<$f>::MAX, 1.0, <$f>::MAX, 0.0), + (<$f>::MIN_POSITIVE_NORMAL, 1.0, -<$f>::MIN_POSITIVE_NORMAL, 0.0), + (-<$f>::MIN_POSITIVE_NORMAL, 1.0, <$f>::MIN_POSITIVE_NORMAL, 0.0), + (<$f>::MIN_POSITIVE_SUBNORMAL, 1.0, -<$f>::MIN_POSITIVE_SUBNORMAL, 0.0), + (-<$f>::MIN_POSITIVE_SUBNORMAL, 1.0, <$f>::MIN_POSITIVE_SUBNORMAL, 0.0), + (<$f>::MAX, 1.0, -<$f>::MAX, 0.0), + + // 754-2020 says "When the exact result of (a × b) + c is non-zero yet the result of + // fusedMultiplyAdd is zero because of rounding, the zero result takes the sign of the + // exact result" + (<$f>::MIN_POSITIVE_SUBNORMAL, <$f>::MIN_POSITIVE_SUBNORMAL, 0.0, 0.0), + (<$f>::MIN_POSITIVE_SUBNORMAL, -<$f>::MIN_POSITIVE_SUBNORMAL, 0.0, -0.0), + (-<$f>::MIN_POSITIVE_SUBNORMAL, <$f>::MIN_POSITIVE_SUBNORMAL, 0.0, -0.0), + (-<$f>::MIN_POSITIVE_SUBNORMAL, -<$f>::MIN_POSITIVE_SUBNORMAL, 0.0, 0.0), + ] + }; + } + + #[track_caller] + fn check(f: fn(F, F, F) -> F, cases: &[(F, F, F, F)]) { + for &(x, y, z, exp_res) in cases { + let val = f(x, y, z); + assert_biteq!( + val, + exp_res, + "fma({x:?}, {y:?}, {z:?}) ({} {} {})", + Hex(x), + Hex(y), + Hex(z) + ); + } } #[test] - fn spec_test_f32() { - spec_test::(fmaf); + #[cfg(f16_enabled)] + fn check_f16() { + check::(super::super::fmaf16, &cases!(f16)); + } + + #[test] + fn check_f32() { + check::(fmaf, &cases!(f32)); // Also do a small check that the non-widening version works for f32 (this should ideally // get tested some more). - spec_test::(|x, y, z| generic::fma_round(x, y, z, Round::Nearest).val); + check::( + |x, y, z| generic::fma_round(x, y, z, Round::Nearest).val, + &cases!(f32), + ); } #[test] - fn spec_test_f64() { - spec_test::(fma); + fn check_f64() { + check::(fma, &cases!(f64)); let expect_underflow = [ ( @@ -121,8 +155,8 @@ mod tests { #[test] #[cfg(f128_enabled)] - fn spec_test_f128() { - spec_test::(fmaf128); + fn check_f128() { + check::(fmaf128, &cases!(f128)); } #[test] @@ -148,7 +182,7 @@ mod tests { let result = fma(-0.992, -0.992, -0.992); //force rounding to storage format on x87 to prevent superious errors. - #[cfg(all(target_arch = "x86", not(target_feature = "sse2")))] + #[cfg(x86_no_sse2)] let result = force_eval!(result); assert_eq!(result, -0.007936000000000007,); } diff --git a/library/compiler-builtins/libm/src/math/fmaf16.rs b/library/compiler-builtins/libm/src/math/fmaf16.rs new file mode 100644 index 0000000000000..8d1c5bccf8527 --- /dev/null +++ b/library/compiler-builtins/libm/src/math/fmaf16.rs @@ -0,0 +1,258 @@ +/* SPDX-License-Identifier: MIT OR Apache-2.0 + * origin: original implementation, 2026 (TG) */ + +use crate::support::{CastFrom, Float, Int, unbounded_shr_u64}; + +/// We use a a U21.43 fixed-point representation when needed. +const FIXED_FRAC_BITS: u32 = 43; + +/// Floating multiply add (f16) +/// +/// Computes `(x*y)+z`, rounded as one ternary operation (i.e. calculated with infinite precision). +#[cfg_attr(assert_no_panic, no_panic::no_panic)] +pub fn fmaf16(x: f16, y: f16, z: f16) -> f16 { + let ix = x.to_bits() & !f16::SIGN_MASK; + let iy = y.to_bits() & !f16::SIGN_MASK; + let iz = z.to_bits() & !f16::SIGN_MASK; + + let xneg = x.is_sign_negative(); + let yneg = y.is_sign_negative(); + let zneg = z.is_sign_negative(); + + let mneg = xneg ^ yneg; + + if ix == 0 || ix >= f16::EXP_MASK || iy == 0 || iy >= f16::EXP_MASK { + // Value will overflow, defer to non-fused operations. + return x * y + z; + } + + if iz == 0 { + // Empty add component means we only need to multiply. + return x * y; + } + + if iz >= f16::EXP_MASK { + // `z` is NaN or infinity, which sets the result. + return z; + } + + let mut xexp = x.ex(); + let mut yexp = y.ex(); + let mut zexp = z.ex(); + + let mut xsig = ix & f16::SIG_MASK; + let mut ysig = iy & f16::SIG_MASK; + let mut zsig = iz & f16::SIG_MASK; + + // If not subnormal, set the implicit bit + if xexp != 0 { + xsig |= f16::IMPLICIT_BIT; + } + if yexp != 0 { + ysig |= f16::IMPLICIT_BIT; + } + if zexp != 0 { + zsig |= f16::IMPLICIT_BIT; + } + + // A biased exponent of 1 (min normal) and 0 (subnormal) have the same real exponent, so + // adjust for this. Bias is now 14 rather than 15. + xexp = xexp.saturating_sub(1); + yexp = yexp.saturating_sub(1); + zexp = zexp.saturating_sub(1); + let adjbias = f16::EXP_BIAS - 1; + + // Exponent after multiplication. Bias doubles to 28. + let mexp = xexp + yexp; + let mbias = adjbias * 2; + + // Exit now if we know the result will overflow. We need to keep one beyond the infinite + // exponent in case the addition rounds down to a finite number. + // + // Note that `EXP_MAX` (i.e. max finite) represents infinity here because our values are + // acting with a bias of 14. + let inf_exp = mbias + f16::EXP_MAX.unsigned(); + if mexp > inf_exp + 1 { + if mneg { + return f16::NEG_INFINITY; + } else { + return f16::INFINITY; + } + } + + // Multiplication moves the explicit 1 from the 11th bit to the 22nd bit. + let m = u32::from(xsig) * u32::from(ysig); + let mut m64 = u64::from(m); + + // The entire dynamic range of an `f16` fits into a `u64`. Shift based on the exponent to + // create a U21.43 fixed-point value. At the maximum exponent, there are five zeros before + // the explicit leading 1 (intentional so this truncates to the final repr). + if let Some(mshift) = mexp.checked_sub(5) { + debug_assert_eq!( + unbounded_shr_u64(m64, 64 - mshift), + 0, + "data shifted out {m} {mshift}" + ); + m64 <<= mshift; + } else { + // The lower few bits here would be on the order of 2^-43, which is too small to show up + // in a result significand. Just squash them to a sticky bit. + let sticky = m64 & 0b11111 != 0; + m64 >>= 5 - mexp; + m64 |= u64::from(sticky); + } + + // Shift z to U21.43 as well. + let zshift = zexp + FIXED_FRAC_BITS - f16::SIG_BITS - adjbias; + let z64 = u64::from(zsig) << zshift; + + let sub = mneg ^ zneg; + + let rneg; + let r64 = if sub { + if m64 > z64 { + rneg = mneg; + m64.wrapping_sub(z64) + } else if m64 == z64 { + rneg = false; + m64.wrapping_sub(z64) + } else { + rneg = zneg; + z64.wrapping_sub(m64) + } + } else { + rneg = mneg; + m64 + z64 + }; + + let sign = if rneg { -1.0 } else { 1.0 }; + f16_from_u21_43(r64).copysign(sign) +} + +/// Turn a U21.43 value into an f16 with positive sign. +fn f16_from_u21_43(mut r64: u64) -> f16 { + let extra_bits = 64 - 16; + let max_finite_lz = 64 - f16::SIG_BITS - extra_bits - 1; // 5 + + // Check for overflow to infinity after addition, return before checking lz. + if r64 & (u64::MAX << (64 - max_finite_lz)) != 0 { + return f16::INFINITY; + } + + // Shift the fixed point to floating point. There are 5 leading zeros before the largest + // finite value's explicit one. + // + // We want `rexp` as one less than the actual value to be stored because it gets added to + // a value with the leading one set. This value and the shift are clamped so subnormals + // don't become normalized. + let exp_max_biased_m1 = f16::EXP_MAX.unsigned() + f16::EXP_BIAS - 1; // 29 + let lz = r64.leading_zeros(); + let rexp = (exp_max_biased_m1 + max_finite_lz).saturating_sub(lz); + let shift = exp_max_biased_m1 - rexp; + r64 <<= shift; + + // Round up if the round bit (one past significand end) is set and any trailing bit is set, + // or if the preceding bit is set. + let round_bit = 1u64 << (extra_bits - 1); + let up_mask = ((1u64 << (extra_bits + 1)) - 1) & !round_bit; + let round_up = r64 & round_bit != 0 && r64 & up_mask != 0; + let round_up = u16::from(round_up); + + // Truncate then round. Automatically accounts for subnormals with the unset explicit decimal + // bit, since `rexp` is one less than the actual biased value. + let mut r = (r64 >> extra_bits) as u16; + r += u16::cast_from(rexp) << f16::SIG_BITS; + r += round_up; + + f16::from_bits(r) +} + +#[cfg(test)] +mod tests { + use super::*; + + #[test] + fn test_from_fixed() { + // Move 1.xx... floating point to 1.xx... fixed point + let shift_to_one = |x: u16| u64::from(x) << (FIXED_FRAC_BITS - f16::SIG_BITS); + let top_sig = f16::IMPLICIT_BIT; + let max_sig = f16::IMPLICIT_BIT | f16::SIG_MASK; + + // Basic values + let one = shift_to_one(top_sig); + let max = shift_to_one(max_sig) << 15; + let inf = shift_to_one(max_sig + 1) << 15; + let min_norm = one >> 14; + let max_sub = shift_to_one(f16::SIG_MASK) >> 14; + let min_sub = shift_to_one(1) >> 14; + + assert_biteq!(f16_from_u21_43(0), 0.0f16); + assert_biteq!(f16_from_u21_43(one), 1.0f16); + assert_biteq!(f16_from_u21_43(max), f16::MAX); + assert_biteq!(f16_from_u21_43(inf), f16::INFINITY); + assert_biteq!(f16_from_u21_43(min_norm), f16::MIN_POSITIVE_NORMAL); + assert_biteq!(f16_from_u21_43(max_sub), f16::from_bits(f16::SIG_MASK)); + assert_biteq!(f16_from_u21_43(min_sub), f16::MIN_POSITIVE_SUBNORMAL); + + // Masks centered around 1 to add a rounding + let mask_r = shift_to_one(0b1) >> 1; // round bit + let mask_rg = shift_to_one(0b11) >> 2; // round + guard + let mask_rgs = shift_to_one(0b111) >> 3; // round + guard + sticky + let mask_rs = shift_to_one(0b101) >> 3; // round + sticky + let mask_rs2 = shift_to_one(0b1000_0001) >> 8; // round + part of sticky + + let signed_shift = |val: u64, shift: i32| { + if shift >= 0 { + val << shift + } else { + val >> -shift + } + }; + + let check_round = |fixed: u64, shift: i32, lsb_set: bool, down: f16, up: f16| { + // Masks that will cause rounding down + let mdown = if lsb_set { &[0][..] } else { &[0, mask_r][..] }; + // Masks that will cause rounding up + let mup = if lsb_set { + &[mask_r, mask_rg, mask_rgs, mask_rs, mask_rs2][..] + } else { + &[mask_rg, mask_rgs, mask_rs, mask_rs2][..] + }; + + for (i, mask) in mdown.iter().enumerate() { + let bits = fixed | signed_shift(*mask, shift); + assert_biteq!(f16_from_u21_43(bits), down, "{bits:#066b} {i}"); + } + + for (i, mask) in mup.iter().enumerate() { + let bits = fixed | signed_shift(*mask, shift); + assert_biteq!(f16_from_u21_43(bits), up, "{bits:#066b} {i}"); + } + }; + + check_round(one, 0, false, 1.0, 1.0f16.next_up()); + check_round(max, 15, true, f16::MAX, f16::INFINITY); + check_round( + min_norm, + -14, + false, + f16::MIN_POSITIVE_NORMAL, + f16::MIN_POSITIVE_NORMAL.next_up(), + ); + check_round( + max_sub, + -14, + true, + f16::MIN_POSITIVE_NORMAL.next_down(), + f16::MIN_POSITIVE_NORMAL, + ); + check_round( + min_sub, + -14, + true, + f16::MIN_POSITIVE_SUBNORMAL, + f16::MIN_POSITIVE_SUBNORMAL.next_up(), + ); + check_round(0, -14, false, 0.0, f16::MIN_POSITIVE_SUBNORMAL); + } +} diff --git a/library/compiler-builtins/libm/src/math/fmin_fmax.rs b/library/compiler-builtins/libm/src/math/fmin_fmax.rs index c4c1b0435dd29..64ad79928f7a0 100644 --- a/library/compiler-builtins/libm/src/math/fmin_fmax.rs +++ b/library/compiler-builtins/libm/src/math/fmin_fmax.rs @@ -77,9 +77,11 @@ pub fn fmaxf128(x: f128, y: f128) -> f128 { #[cfg(test)] mod tests { use super::*; - use crate::support::{Float, Hexf}; + use crate::support::{Float, Hex}; fn fmin_spec_test(f: impl Fn(F, F) -> F) { + // Note that (YaN, sNaN) and (sNaN, YaN) results differ from 754-2008. This is intentional, + // see comments in the generic implementations. let cases = [ (F::ZERO, F::ZERO, F::ZERO), (F::ZERO, F::ONE, F::ZERO), @@ -88,6 +90,8 @@ mod tests { (F::ZERO, F::NEG_INFINITY, F::NEG_INFINITY), (F::ZERO, F::NAN, F::ZERO), (F::ZERO, F::NEG_NAN, F::ZERO), + (F::ZERO, F::SNAN, F::ZERO), + (F::ZERO, F::NEG_SNAN, F::ZERO), (F::NEG_ZERO, F::NEG_ZERO, F::NEG_ZERO), (F::NEG_ZERO, F::ONE, F::NEG_ZERO), (F::NEG_ZERO, F::NEG_ONE, F::NEG_ONE), @@ -95,6 +99,8 @@ mod tests { (F::NEG_ZERO, F::NEG_INFINITY, F::NEG_INFINITY), (F::NEG_ZERO, F::NAN, F::NEG_ZERO), (F::NEG_ZERO, F::NEG_NAN, F::NEG_ZERO), + (F::NEG_ZERO, F::SNAN, F::NEG_ZERO), + (F::NEG_ZERO, F::NEG_SNAN, F::NEG_ZERO), (F::ONE, F::ZERO, F::ZERO), (F::ONE, F::NEG_ZERO, F::NEG_ZERO), (F::ONE, F::ONE, F::ONE), @@ -103,6 +109,8 @@ mod tests { (F::ONE, F::NEG_INFINITY, F::NEG_INFINITY), (F::ONE, F::NAN, F::ONE), (F::ONE, F::NEG_NAN, F::ONE), + (F::ONE, F::SNAN, F::ONE), + (F::ONE, F::NEG_SNAN, F::ONE), (F::NEG_ONE, F::ZERO, F::NEG_ONE), (F::NEG_ONE, F::NEG_ZERO, F::NEG_ONE), (F::NEG_ONE, F::ONE, F::NEG_ONE), @@ -111,6 +119,8 @@ mod tests { (F::NEG_ONE, F::NEG_INFINITY, F::NEG_INFINITY), (F::NEG_ONE, F::NAN, F::NEG_ONE), (F::NEG_ONE, F::NEG_NAN, F::NEG_ONE), + (F::NEG_ONE, F::SNAN, F::NEG_ONE), + (F::NEG_ONE, F::NEG_SNAN, F::NEG_ONE), (F::INFINITY, F::ZERO, F::ZERO), (F::INFINITY, F::NEG_ZERO, F::NEG_ZERO), (F::INFINITY, F::ONE, F::ONE), @@ -119,6 +129,8 @@ mod tests { (F::INFINITY, F::NEG_INFINITY, F::NEG_INFINITY), (F::INFINITY, F::NAN, F::INFINITY), (F::INFINITY, F::NEG_NAN, F::INFINITY), + (F::INFINITY, F::SNAN, F::INFINITY), + (F::INFINITY, F::NEG_SNAN, F::INFINITY), (F::NEG_INFINITY, F::ZERO, F::NEG_INFINITY), (F::NEG_INFINITY, F::NEG_ZERO, F::NEG_INFINITY), (F::NEG_INFINITY, F::ONE, F::NEG_INFINITY), @@ -127,6 +139,8 @@ mod tests { (F::NEG_INFINITY, F::NEG_INFINITY, F::NEG_INFINITY), (F::NEG_INFINITY, F::NAN, F::NEG_INFINITY), (F::NEG_INFINITY, F::NEG_NAN, F::NEG_INFINITY), + (F::NEG_INFINITY, F::SNAN, F::NEG_INFINITY), + (F::NEG_INFINITY, F::NEG_SNAN, F::NEG_INFINITY), (F::NAN, F::ZERO, F::ZERO), (F::NAN, F::NEG_ZERO, F::NEG_ZERO), (F::NAN, F::ONE, F::ONE), @@ -140,19 +154,48 @@ mod tests { (F::NEG_NAN, F::NEG_ONE, F::NEG_ONE), (F::NEG_NAN, F::INFINITY, F::INFINITY), (F::NEG_NAN, F::NEG_INFINITY, F::NEG_INFINITY), + (F::SNAN, F::ZERO, F::ZERO), + (F::SNAN, F::NEG_ZERO, F::NEG_ZERO), + (F::SNAN, F::ONE, F::ONE), + (F::SNAN, F::NEG_ONE, F::NEG_ONE), + (F::SNAN, F::INFINITY, F::INFINITY), + (F::SNAN, F::NEG_INFINITY, F::NEG_INFINITY), + (F::NEG_SNAN, F::ZERO, F::ZERO), + (F::NEG_SNAN, F::NEG_ZERO, F::NEG_ZERO), + (F::NEG_SNAN, F::ONE, F::ONE), + (F::NEG_SNAN, F::NEG_ONE, F::NEG_ONE), + (F::NEG_SNAN, F::INFINITY, F::INFINITY), + (F::NEG_SNAN, F::NEG_INFINITY, F::NEG_INFINITY), ]; for (x, y, res) in cases { let val = f(x, y); - assert_biteq!(val, res, "fmin({}, {})", Hexf(x), Hexf(y)); + assert_biteq!(val, res, "fmin({}, {})", Hex(x), Hex(y)); } - // Ordering between zeros and NaNs does not matter + // Ordering between zeros does not matter assert_eq!(f(F::ZERO, F::NEG_ZERO), F::ZERO); assert_eq!(f(F::NEG_ZERO, F::ZERO), F::ZERO); - assert!(f(F::NAN, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_NAN, F::NAN).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_NAN).is_nan()); + + // Selection between NaNs does not matter, it just must be quiet + assert!(f(F::NAN, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_NAN).is_qnan()); + + // These operations should technically return a qnan, but LLVM optimizes out our + // `* 1.0` canonicalization. + assert!(f(F::NAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NAN, F::SNAN).is_nan()); + assert!(f(F::NEG_NAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NEG_NAN, F::SNAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_NAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NEG_SNAN, F::SNAN).is_nan()); + assert!(f(F::SNAN, F::NAN).is_nan()); + assert!(f(F::SNAN, F::NAN).is_nan()); + assert!(f(F::SNAN, F::NEG_NAN).is_nan()); + assert!(f(F::SNAN, F::NEG_SNAN).is_nan()); } #[test] @@ -186,6 +229,8 @@ mod tests { (F::ZERO, F::NEG_INFINITY, F::ZERO), (F::ZERO, F::NAN, F::ZERO), (F::ZERO, F::NEG_NAN, F::ZERO), + (F::ZERO, F::SNAN, F::ZERO), + (F::ZERO, F::NEG_SNAN, F::ZERO), (F::NEG_ZERO, F::NEG_ZERO, F::NEG_ZERO), (F::NEG_ZERO, F::ONE, F::ONE), (F::NEG_ZERO, F::NEG_ONE, F::NEG_ZERO), @@ -193,6 +238,8 @@ mod tests { (F::NEG_ZERO, F::NEG_INFINITY, F::NEG_ZERO), (F::NEG_ZERO, F::NAN, F::NEG_ZERO), (F::NEG_ZERO, F::NEG_NAN, F::NEG_ZERO), + (F::NEG_ZERO, F::SNAN, F::NEG_ZERO), + (F::NEG_ZERO, F::NEG_SNAN, F::NEG_ZERO), (F::ONE, F::ZERO, F::ONE), (F::ONE, F::NEG_ZERO, F::ONE), (F::ONE, F::ONE, F::ONE), @@ -201,6 +248,8 @@ mod tests { (F::ONE, F::NEG_INFINITY, F::ONE), (F::ONE, F::NAN, F::ONE), (F::ONE, F::NEG_NAN, F::ONE), + (F::ONE, F::SNAN, F::ONE), + (F::ONE, F::NEG_SNAN, F::ONE), (F::NEG_ONE, F::ZERO, F::ZERO), (F::NEG_ONE, F::NEG_ZERO, F::NEG_ZERO), (F::NEG_ONE, F::ONE, F::ONE), @@ -209,6 +258,8 @@ mod tests { (F::NEG_ONE, F::NEG_INFINITY, F::NEG_ONE), (F::NEG_ONE, F::NAN, F::NEG_ONE), (F::NEG_ONE, F::NEG_NAN, F::NEG_ONE), + (F::NEG_ONE, F::SNAN, F::NEG_ONE), + (F::NEG_ONE, F::NEG_SNAN, F::NEG_ONE), (F::INFINITY, F::ZERO, F::INFINITY), (F::INFINITY, F::NEG_ZERO, F::INFINITY), (F::INFINITY, F::ONE, F::INFINITY), @@ -217,6 +268,8 @@ mod tests { (F::INFINITY, F::NEG_INFINITY, F::INFINITY), (F::INFINITY, F::NAN, F::INFINITY), (F::INFINITY, F::NEG_NAN, F::INFINITY), + (F::INFINITY, F::SNAN, F::INFINITY), + (F::INFINITY, F::NEG_SNAN, F::INFINITY), (F::NEG_INFINITY, F::ZERO, F::ZERO), (F::NEG_INFINITY, F::NEG_ZERO, F::NEG_ZERO), (F::NEG_INFINITY, F::ONE, F::ONE), @@ -225,6 +278,8 @@ mod tests { (F::NEG_INFINITY, F::NEG_INFINITY, F::NEG_INFINITY), (F::NEG_INFINITY, F::NAN, F::NEG_INFINITY), (F::NEG_INFINITY, F::NEG_NAN, F::NEG_INFINITY), + (F::NEG_INFINITY, F::SNAN, F::NEG_INFINITY), + (F::NEG_INFINITY, F::NEG_SNAN, F::NEG_INFINITY), (F::NAN, F::ZERO, F::ZERO), (F::NAN, F::NEG_ZERO, F::NEG_ZERO), (F::NAN, F::ONE, F::ONE), @@ -238,19 +293,54 @@ mod tests { (F::NEG_NAN, F::NEG_ONE, F::NEG_ONE), (F::NEG_NAN, F::INFINITY, F::INFINITY), (F::NEG_NAN, F::NEG_INFINITY, F::NEG_INFINITY), + (F::SNAN, F::ZERO, F::ZERO), + (F::SNAN, F::NEG_ZERO, F::NEG_ZERO), + (F::SNAN, F::ONE, F::ONE), + (F::SNAN, F::NEG_ONE, F::NEG_ONE), + (F::SNAN, F::INFINITY, F::INFINITY), + (F::SNAN, F::NEG_INFINITY, F::NEG_INFINITY), + (F::NEG_SNAN, F::ZERO, F::ZERO), + (F::NEG_SNAN, F::NEG_ZERO, F::NEG_ZERO), + (F::NEG_SNAN, F::ONE, F::ONE), + (F::NEG_SNAN, F::NEG_ONE, F::NEG_ONE), + (F::NEG_SNAN, F::INFINITY, F::INFINITY), + (F::NEG_SNAN, F::NEG_INFINITY, F::NEG_INFINITY), ]; for (x, y, res) in cases { let val = f(x, y); - assert_biteq!(val, res, "fmax({}, {})", Hexf(x), Hexf(y)); + assert_biteq!( + val, + res, + "fmax({}, {}) ({}, {})", + Hex(x), + Hex(y), + Hex(x.to_bits()), + Hex(y.to_bits()), + ); } - // Ordering between zeros and NaNs does not matter + // Ordering between zeros assert_eq!(f(F::ZERO, F::NEG_ZERO), F::ZERO); assert_eq!(f(F::NEG_ZERO, F::ZERO), F::ZERO); - assert!(f(F::NAN, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_NAN, F::NAN).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_NAN).is_nan()); + + // Selection between NaNs does not matter, it just must be quiet + assert!(f(F::NAN, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_NAN).is_qnan()); + + assert!(f(F::NAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NAN, F::SNAN).is_nan()); + assert!(f(F::NEG_NAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NEG_NAN, F::SNAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_NAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NEG_SNAN, F::SNAN).is_nan()); + assert!(f(F::SNAN, F::NAN).is_nan()); + assert!(f(F::SNAN, F::NEG_NAN).is_nan()); + assert!(f(F::SNAN, F::NEG_SNAN).is_nan()); + assert!(f(F::SNAN, F::SNAN).is_nan()); } #[test] diff --git a/library/compiler-builtins/libm/src/math/fminimum_fmaximum.rs b/library/compiler-builtins/libm/src/math/fminimum_fmaximum.rs index a3c9c9c3991b7..59d9af317674f 100644 --- a/library/compiler-builtins/libm/src/math/fminimum_fmaximum.rs +++ b/library/compiler-builtins/libm/src/math/fminimum_fmaximum.rs @@ -69,7 +69,7 @@ pub fn fmaximumf128(x: f128, y: f128) -> f128 { #[cfg(test)] mod tests { use super::*; - use crate::support::{Float, Hexf}; + use crate::support::{Float, Hex}; fn fminimum_spec_test(f: impl Fn(F, F) -> F) { let cases = [ @@ -122,29 +122,63 @@ mod tests { (F::NAN, F::INFINITY, F::NAN), (F::NAN, F::NEG_INFINITY, F::NAN), (F::NAN, F::NAN, F::NAN), + (F::NAN, F::SNAN, F::NAN), ]; for (x, y, res) in cases { let val = f(x, y); - assert_biteq!(val, res, "fminimum({}, {})", Hexf(x), Hexf(y)); + assert_biteq!( + val, + res, + "fminimum({}, {}) ({}, {})", + Hex(x), + Hex(y), + Hex(x.to_bits()), + Hex(y.to_bits()), + ); } - // Ordering between NaNs does not matter - assert!(f(F::NAN, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_NAN, F::NAN).is_nan()); - assert!(f(F::ZERO, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_ZERO, F::NEG_NAN).is_nan()); - assert!(f(F::ONE, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_ONE, F::NEG_NAN).is_nan()); - assert!(f(F::INFINITY, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_INFINITY, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_NAN, F::ZERO).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_ZERO).is_nan()); - assert!(f(F::NEG_NAN, F::ONE).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_ONE).is_nan()); - assert!(f(F::NEG_NAN, F::INFINITY).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_INFINITY).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_NAN).is_nan()); + // On platforms where operations only return a single canonical NaN (e.g. RISC-V), the + // result may not exactly match one of the inputs which is fine. + assert!(f(F::NAN, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::NAN).is_qnan()); + assert!(f(F::ZERO, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_ZERO, F::NEG_NAN).is_qnan()); + assert!(f(F::ONE, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_ONE, F::NEG_NAN).is_qnan()); + assert!(f(F::INFINITY, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_INFINITY, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::ZERO).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_ZERO).is_qnan()); + assert!(f(F::NEG_NAN, F::ONE).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_ONE).is_qnan()); + assert!(f(F::NEG_NAN, F::INFINITY).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_INFINITY).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_NAN).is_qnan()); + + // These operations should technically return a qnan, but LLVM optimizes out our + // `* 1.0` canonicalization. + assert!(f(F::INFINITY, F::SNAN,).is_nan()); + assert!(f(F::NEG_INFINITY, F::SNAN,).is_nan()); + assert!(f(F::NEG_ONE, F::SNAN,).is_nan()); + assert!(f(F::NEG_SNAN, F::INFINITY).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_INFINITY).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_NAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_ONE).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_ZERO).is_nan()); + assert!(f(F::NEG_SNAN, F::ONE).is_nan()); + assert!(f(F::NEG_SNAN, F::ZERO).is_nan()); + assert!(f(F::NEG_ZERO, F::SNAN,).is_nan()); + assert!(f(F::ONE, F::SNAN,).is_nan()); + assert!(f(F::SNAN, F::INFINITY,).is_nan()); + assert!(f(F::SNAN, F::NEG_INFINITY,).is_nan()); + assert!(f(F::SNAN, F::NEG_ONE,).is_nan()); + assert!(f(F::SNAN, F::NEG_SNAN,).is_nan()); + assert!(f(F::SNAN, F::NEG_ZERO,).is_nan()); + assert!(f(F::SNAN, F::ONE,).is_nan()); + assert!(f(F::SNAN, F::SNAN,).is_nan()); + assert!(f(F::SNAN, F::ZERO,).is_nan()); + assert!(f(F::ZERO, F::SNAN,).is_nan()); } #[test] @@ -220,29 +254,63 @@ mod tests { (F::NAN, F::INFINITY, F::NAN), (F::NAN, F::NEG_INFINITY, F::NAN), (F::NAN, F::NAN, F::NAN), + (F::NAN, F::SNAN, F::NAN), ]; for (x, y, res) in cases { let val = f(x, y); - assert_biteq!(val, res, "fmaximum({}, {})", Hexf(x), Hexf(y)); + assert_biteq!( + val, + res, + "fmaximum({}, {}) ({}, {})", + Hex(x), + Hex(y), + Hex(x.to_bits()), + Hex(y.to_bits()), + ); } - // Ordering between NaNs does not matter - assert!(f(F::NAN, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_NAN, F::NAN).is_nan()); - assert!(f(F::ZERO, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_ZERO, F::NEG_NAN).is_nan()); - assert!(f(F::ONE, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_ONE, F::NEG_NAN).is_nan()); - assert!(f(F::INFINITY, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_INFINITY, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_NAN, F::ZERO).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_ZERO).is_nan()); - assert!(f(F::NEG_NAN, F::ONE).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_ONE).is_nan()); - assert!(f(F::NEG_NAN, F::INFINITY).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_INFINITY).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_NAN).is_nan()); + // On platforms where operations only return a single canonical NaN (e.g. RISC-V), the + // result may not exactly match one of the inputs which is fine. + assert!(f(F::NAN, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::NAN).is_qnan()); + assert!(f(F::ZERO, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_ZERO, F::NEG_NAN).is_qnan()); + assert!(f(F::ONE, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_ONE, F::NEG_NAN).is_qnan()); + assert!(f(F::INFINITY, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_INFINITY, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::ZERO).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_ZERO).is_qnan()); + assert!(f(F::NEG_NAN, F::ONE).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_ONE).is_qnan()); + assert!(f(F::NEG_NAN, F::INFINITY).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_INFINITY).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_NAN).is_qnan()); + + // These operations should technically return a qnan, but LLVM optimizes out our + // `* 1.0` canonicalization. + assert!(f(F::INFINITY, F::SNAN,).is_nan()); + assert!(f(F::NEG_INFINITY, F::SNAN,).is_nan()); + assert!(f(F::NEG_ONE, F::SNAN,).is_nan()); + assert!(f(F::NEG_SNAN, F::INFINITY).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_INFINITY).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_NAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_ONE).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_ZERO).is_nan()); + assert!(f(F::NEG_SNAN, F::ONE).is_nan()); + assert!(f(F::NEG_SNAN, F::ZERO).is_nan()); + assert!(f(F::NEG_ZERO, F::SNAN,).is_nan()); + assert!(f(F::ONE, F::SNAN,).is_nan()); + assert!(f(F::SNAN, F::INFINITY,).is_nan()); + assert!(f(F::SNAN, F::NEG_INFINITY,).is_nan()); + assert!(f(F::SNAN, F::NEG_ONE,).is_nan()); + assert!(f(F::SNAN, F::NEG_SNAN,).is_nan()); + assert!(f(F::SNAN, F::NEG_ZERO,).is_nan()); + assert!(f(F::SNAN, F::ONE,).is_nan()); + assert!(f(F::SNAN, F::SNAN,).is_nan()); + assert!(f(F::SNAN, F::ZERO,).is_nan()); + assert!(f(F::ZERO, F::SNAN,).is_nan()); } #[test] diff --git a/library/compiler-builtins/libm/src/math/fminimum_fmaximum_num.rs b/library/compiler-builtins/libm/src/math/fminimum_fmaximum_num.rs index 612cefe756e30..51b20b736d2ca 100644 --- a/library/compiler-builtins/libm/src/math/fminimum_fmaximum_num.rs +++ b/library/compiler-builtins/libm/src/math/fminimum_fmaximum_num.rs @@ -69,7 +69,7 @@ pub fn fmaximum_numf128(x: f128, y: f128) -> f128 { #[cfg(test)] mod tests { use super::*; - use crate::support::{Float, Hexf}; + use crate::support::{Float, Hex}; fn fminimum_num_spec_test(f: impl Fn(F, F) -> F) { let cases = [ @@ -81,6 +81,8 @@ mod tests { (F::ZERO, F::NEG_INFINITY, F::NEG_INFINITY), (F::ZERO, F::NAN, F::ZERO), (F::ZERO, F::NEG_NAN, F::ZERO), + (F::ZERO, F::SNAN, F::ZERO), + (F::ZERO, F::NEG_SNAN, F::ZERO), (F::NEG_ZERO, F::ZERO, F::NEG_ZERO), (F::NEG_ZERO, F::NEG_ZERO, F::NEG_ZERO), (F::NEG_ZERO, F::ONE, F::NEG_ZERO), @@ -89,6 +91,8 @@ mod tests { (F::NEG_ZERO, F::NEG_INFINITY, F::NEG_INFINITY), (F::NEG_ZERO, F::NAN, F::NEG_ZERO), (F::NEG_ZERO, F::NEG_NAN, F::NEG_ZERO), + (F::NEG_ZERO, F::SNAN, F::NEG_ZERO), + (F::NEG_ZERO, F::NEG_SNAN, F::NEG_ZERO), (F::ONE, F::ZERO, F::ZERO), (F::ONE, F::NEG_ZERO, F::NEG_ZERO), (F::ONE, F::ONE, F::ONE), @@ -97,6 +101,8 @@ mod tests { (F::ONE, F::NEG_INFINITY, F::NEG_INFINITY), (F::ONE, F::NAN, F::ONE), (F::ONE, F::NEG_NAN, F::ONE), + (F::ONE, F::SNAN, F::ONE), + (F::ONE, F::NEG_SNAN, F::ONE), (F::NEG_ONE, F::ZERO, F::NEG_ONE), (F::NEG_ONE, F::NEG_ZERO, F::NEG_ONE), (F::NEG_ONE, F::ONE, F::NEG_ONE), @@ -105,6 +111,8 @@ mod tests { (F::NEG_ONE, F::NEG_INFINITY, F::NEG_INFINITY), (F::NEG_ONE, F::NAN, F::NEG_ONE), (F::NEG_ONE, F::NEG_NAN, F::NEG_ONE), + (F::NEG_ONE, F::SNAN, F::NEG_ONE), + (F::NEG_ONE, F::NEG_SNAN, F::NEG_ONE), (F::INFINITY, F::ZERO, F::ZERO), (F::INFINITY, F::NEG_ZERO, F::NEG_ZERO), (F::INFINITY, F::ONE, F::ONE), @@ -113,6 +121,8 @@ mod tests { (F::INFINITY, F::NEG_INFINITY, F::NEG_INFINITY), (F::INFINITY, F::NAN, F::INFINITY), (F::INFINITY, F::NEG_NAN, F::INFINITY), + (F::INFINITY, F::SNAN, F::INFINITY), + (F::INFINITY, F::NEG_SNAN, F::INFINITY), (F::NEG_INFINITY, F::ZERO, F::NEG_INFINITY), (F::NEG_INFINITY, F::NEG_ZERO, F::NEG_INFINITY), (F::NEG_INFINITY, F::ONE, F::NEG_INFINITY), @@ -121,6 +131,8 @@ mod tests { (F::NEG_INFINITY, F::NEG_INFINITY, F::NEG_INFINITY), (F::NEG_INFINITY, F::NAN, F::NEG_INFINITY), (F::NEG_INFINITY, F::NEG_NAN, F::NEG_INFINITY), + (F::NEG_INFINITY, F::SNAN, F::NEG_INFINITY), + (F::NEG_INFINITY, F::NEG_SNAN, F::NEG_INFINITY), (F::NAN, F::ZERO, F::ZERO), (F::NAN, F::NEG_ZERO, F::NEG_ZERO), (F::NAN, F::ONE, F::ONE), @@ -134,17 +146,52 @@ mod tests { (F::NEG_NAN, F::NEG_ONE, F::NEG_ONE), (F::NEG_NAN, F::INFINITY, F::INFINITY), (F::NEG_NAN, F::NEG_INFINITY, F::NEG_INFINITY), + (F::SNAN, F::ZERO, F::ZERO), + (F::SNAN, F::NEG_ZERO, F::NEG_ZERO), + (F::SNAN, F::ONE, F::ONE), + (F::SNAN, F::NEG_ONE, F::NEG_ONE), + (F::SNAN, F::INFINITY, F::INFINITY), + (F::SNAN, F::NEG_INFINITY, F::NEG_INFINITY), + (F::NEG_SNAN, F::ZERO, F::ZERO), + (F::NEG_SNAN, F::NEG_ZERO, F::NEG_ZERO), + (F::NEG_SNAN, F::ONE, F::ONE), + (F::NEG_SNAN, F::NEG_ONE, F::NEG_ONE), + (F::NEG_SNAN, F::INFINITY, F::INFINITY), + (F::NEG_SNAN, F::NEG_INFINITY, F::NEG_INFINITY), ]; for (x, y, expected) in cases { let actual = f(x, y); - assert_biteq!(actual, expected, "fminimum_num({}, {})", Hexf(x), Hexf(y)); + assert_biteq!( + actual, + expected, + "fminimum_num({}, {}) ({}, {})", + Hex(x), + Hex(y), + Hex(x.to_bits()), + Hex(y.to_bits()), + ); } - // Ordering between NaNs does not matter - assert!(f(F::NAN, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_NAN, F::NAN).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_NAN).is_nan()); + // Selection between NaNs does not matter, it just must be quiet + assert!(f(F::NAN, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_NAN).is_qnan()); + + // These operations should technically return a qnan, but LLVM optimizes out our + // `* 1.0` canonicalization. + assert!(f(F::NAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NAN, F::SNAN).is_nan()); + assert!(f(F::NEG_NAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NEG_NAN, F::SNAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_NAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NEG_SNAN, F::SNAN).is_nan()); + assert!(f(F::SNAN, F::NAN).is_nan()); + assert!(f(F::SNAN, F::NEG_NAN).is_nan()); + assert!(f(F::SNAN, F::NEG_SNAN).is_nan()); + assert!(f(F::SNAN, F::SNAN).is_nan()); } #[test] @@ -179,6 +226,8 @@ mod tests { (F::ZERO, F::NEG_INFINITY, F::ZERO), (F::ZERO, F::NAN, F::ZERO), (F::ZERO, F::NEG_NAN, F::ZERO), + (F::ZERO, F::SNAN, F::ZERO), + (F::ZERO, F::NEG_SNAN, F::ZERO), (F::NEG_ZERO, F::ZERO, F::ZERO), (F::NEG_ZERO, F::NEG_ZERO, F::NEG_ZERO), (F::NEG_ZERO, F::ONE, F::ONE), @@ -187,6 +236,8 @@ mod tests { (F::NEG_ZERO, F::NEG_INFINITY, F::NEG_ZERO), (F::NEG_ZERO, F::NAN, F::NEG_ZERO), (F::NEG_ZERO, F::NEG_NAN, F::NEG_ZERO), + (F::NEG_ZERO, F::SNAN, F::NEG_ZERO), + (F::NEG_ZERO, F::NEG_SNAN, F::NEG_ZERO), (F::ONE, F::ZERO, F::ONE), (F::ONE, F::NEG_ZERO, F::ONE), (F::ONE, F::ONE, F::ONE), @@ -195,6 +246,8 @@ mod tests { (F::ONE, F::NEG_INFINITY, F::ONE), (F::ONE, F::NAN, F::ONE), (F::ONE, F::NEG_NAN, F::ONE), + (F::ONE, F::SNAN, F::ONE), + (F::ONE, F::NEG_SNAN, F::ONE), (F::NEG_ONE, F::ZERO, F::ZERO), (F::NEG_ONE, F::NEG_ZERO, F::NEG_ZERO), (F::NEG_ONE, F::ONE, F::ONE), @@ -203,6 +256,8 @@ mod tests { (F::NEG_ONE, F::NEG_INFINITY, F::NEG_ONE), (F::NEG_ONE, F::NAN, F::NEG_ONE), (F::NEG_ONE, F::NEG_NAN, F::NEG_ONE), + (F::NEG_ONE, F::SNAN, F::NEG_ONE), + (F::NEG_ONE, F::NEG_SNAN, F::NEG_ONE), (F::INFINITY, F::ZERO, F::INFINITY), (F::INFINITY, F::NEG_ZERO, F::INFINITY), (F::INFINITY, F::ONE, F::INFINITY), @@ -211,6 +266,8 @@ mod tests { (F::INFINITY, F::NEG_INFINITY, F::INFINITY), (F::INFINITY, F::NAN, F::INFINITY), (F::INFINITY, F::NEG_NAN, F::INFINITY), + (F::INFINITY, F::SNAN, F::INFINITY), + (F::INFINITY, F::NEG_SNAN, F::INFINITY), (F::NEG_INFINITY, F::ZERO, F::ZERO), (F::NEG_INFINITY, F::NEG_ZERO, F::NEG_ZERO), (F::NEG_INFINITY, F::ONE, F::ONE), @@ -219,6 +276,8 @@ mod tests { (F::NEG_INFINITY, F::NEG_INFINITY, F::NEG_INFINITY), (F::NEG_INFINITY, F::NAN, F::NEG_INFINITY), (F::NEG_INFINITY, F::NEG_NAN, F::NEG_INFINITY), + (F::NEG_INFINITY, F::SNAN, F::NEG_INFINITY), + (F::NEG_INFINITY, F::NEG_SNAN, F::NEG_INFINITY), (F::NAN, F::ZERO, F::ZERO), (F::NAN, F::NEG_ZERO, F::NEG_ZERO), (F::NAN, F::ONE, F::ONE), @@ -232,17 +291,52 @@ mod tests { (F::NEG_NAN, F::NEG_ONE, F::NEG_ONE), (F::NEG_NAN, F::INFINITY, F::INFINITY), (F::NEG_NAN, F::NEG_INFINITY, F::NEG_INFINITY), + (F::SNAN, F::ZERO, F::ZERO), + (F::SNAN, F::NEG_ZERO, F::NEG_ZERO), + (F::SNAN, F::ONE, F::ONE), + (F::SNAN, F::NEG_ONE, F::NEG_ONE), + (F::SNAN, F::INFINITY, F::INFINITY), + (F::SNAN, F::NEG_INFINITY, F::NEG_INFINITY), + (F::NEG_SNAN, F::ZERO, F::ZERO), + (F::NEG_SNAN, F::NEG_ZERO, F::NEG_ZERO), + (F::NEG_SNAN, F::ONE, F::ONE), + (F::NEG_SNAN, F::NEG_ONE, F::NEG_ONE), + (F::NEG_SNAN, F::INFINITY, F::INFINITY), + (F::NEG_SNAN, F::NEG_INFINITY, F::NEG_INFINITY), ]; for (x, y, expected) in cases { let actual = f(x, y); - assert_biteq!(actual, expected, "fmaximum_num({}, {})", Hexf(x), Hexf(y)); + assert_biteq!( + actual, + expected, + "fmaximum_num({}, {}) ({}, {})", + Hex(x), + Hex(y), + Hex(x.to_bits()), + Hex(y.to_bits()), + ); } - // Ordering between NaNs does not matter - assert!(f(F::NAN, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_NAN, F::NAN).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_NAN).is_nan()); + // Selection between NaNs does not matter, it just must be quiet + assert!(f(F::NAN, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_NAN).is_qnan()); + + // These operations should technically return a qnan, but LLVM optimizes out our + // `* 1.0` canonicalization. + assert!(f(F::NAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NAN, F::SNAN).is_nan()); + assert!(f(F::NEG_NAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NEG_NAN, F::SNAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_NAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NEG_SNAN, F::SNAN).is_nan()); + assert!(f(F::SNAN, F::NAN).is_nan()); + assert!(f(F::SNAN, F::NEG_NAN).is_nan()); + assert!(f(F::SNAN, F::NEG_SNAN).is_nan()); + assert!(f(F::SNAN, F::SNAN).is_nan()); } #[test] diff --git a/library/compiler-builtins/libm/src/math/frexp.rs b/library/compiler-builtins/libm/src/math/frexp.rs index 932111eebc955..af38915a3ac69 100644 --- a/library/compiler-builtins/libm/src/math/frexp.rs +++ b/library/compiler-builtins/libm/src/math/frexp.rs @@ -1,21 +1,34 @@ +/// Decompose a float into a normalized value within the range `[0.5, 1)`, and a power of 2. +/// +/// That is, `x * 2^p` will represent the input value. +// Placeholder so we can have `frexpf16` in the `Float` trait. +#[cfg(f16_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] -pub fn frexp(x: f64) -> (f64, i32) { - let mut y = x.to_bits(); - let ee = ((y >> 52) & 0x7ff) as i32; +pub fn frexpf16(x: f16) -> (f16, i32) { + super::generic::frexp(x) +} - if ee == 0 { - if x != 0.0 { - let x1p64 = f64::from_bits(0x43f0000000000000); - let (x, e) = frexp(x * x1p64); - return (x, e - 64); - } - return (x, 0); - } else if ee == 0x7ff { - return (x, 0); - } +/// Decompose a float into a normalized value within the range `[0.5, 1)`, and a power of 2. +/// +/// That is, `x * 2^p` will represent the input value. +#[cfg_attr(assert_no_panic, no_panic::no_panic)] +pub fn frexpf(x: f32) -> (f32, i32) { + super::generic::frexp(x) +} - let e = ee - 0x3fe; - y &= 0x800fffffffffffff; - y |= 0x3fe0000000000000; - return (f64::from_bits(y), e); +/// Decompose a float into a normalized value within the range `[0.5, 1)`, and a power of 2. +/// +/// That is, `x * 2^p` will represent the input value. +#[cfg_attr(assert_no_panic, no_panic::no_panic)] +pub fn frexp(x: f64) -> (f64, i32) { + super::generic::frexp(x) +} + +/// Decompose a float into a normalized value within the range `[0.5, 1)`, and a power of 2. +/// +/// That is, `x * 2^p` will represent the input value. +#[cfg(f128_enabled)] +#[cfg_attr(assert_no_panic, no_panic::no_panic)] +pub fn frexpf128(x: f128) -> (f128, i32) { + super::generic::frexp(x) } diff --git a/library/compiler-builtins/libm/src/math/frexpf.rs b/library/compiler-builtins/libm/src/math/frexpf.rs deleted file mode 100644 index 904bf14f7b8ea..0000000000000 --- a/library/compiler-builtins/libm/src/math/frexpf.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[cfg_attr(assert_no_panic, no_panic::no_panic)] -pub fn frexpf(x: f32) -> (f32, i32) { - let mut y = x.to_bits(); - let ee: i32 = ((y >> 23) & 0xff) as i32; - - if ee == 0 { - if x != 0.0 { - let x1p64 = f32::from_bits(0x5f800000); - let (x, e) = frexpf(x * x1p64); - return (x, e - 64); - } else { - return (x, 0); - } - } else if ee == 0xff { - return (x, 0); - } - - let e = ee - 0x7e; - y &= 0x807fffff; - y |= 0x3f000000; - (f32::from_bits(y), e) -} diff --git a/library/compiler-builtins/libm/src/math/generic/ceil.rs b/library/compiler-builtins/libm/src/math/generic/ceil.rs index 1072ba7c29b63..944cb4d4c7259 100644 --- a/library/compiler-builtins/libm/src/math/generic/ceil.rs +++ b/library/compiler-builtins/libm/src/math/generic/ceil.rs @@ -9,11 +9,6 @@ use crate::support::{Float, FpResult, Int, IntTy, MinInt, Status}; -#[inline] -pub fn ceil(x: F) -> F { - ceil_status(x).val -} - #[inline] pub fn ceil_status(x: F) -> FpResult { let zero = IntTy::::ZERO; @@ -46,7 +41,7 @@ pub fn ceil_status(x: F) -> FpResult { F::from_bits(ix) } else { // |x| < 1.0, raise an inexact exception since truncation will happen (unless x == 0). - if ix & F::SIG_MASK == F::Int::ZERO { + if ix & !F::SIGN_MASK == F::Int::ZERO { status = Status::OK; } else { status = Status::INEXACT; @@ -66,109 +61,3 @@ pub fn ceil_status(x: F) -> FpResult { FpResult::new(res, status) } - -#[cfg(test)] -mod tests { - use super::*; - use crate::support::Hexf; - - /// Test against https://en.cppreference.com/w/cpp/numeric/math/ceil - fn spec_test(cases: &[(F, F, Status)]) { - let roundtrip = [ - F::ZERO, - F::ONE, - F::NEG_ONE, - F::NEG_ZERO, - F::INFINITY, - F::NEG_INFINITY, - ]; - - for x in roundtrip { - let FpResult { val, status } = ceil_status(x); - assert_biteq!(val, x, "{}", Hexf(x)); - assert_eq!(status, Status::OK, "{}", Hexf(x)); - } - - for &(x, res, res_stat) in cases { - let FpResult { val, status } = ceil_status(x); - assert_biteq!(val, res, "{}", Hexf(x)); - assert_eq!(status, res_stat, "{}", Hexf(x)); - } - } - - /* Skipping f16 / f128 "sanity_check"s due to rejected literal lexing at MSRV */ - - #[test] - #[cfg(f16_enabled)] - fn spec_tests_f16() { - let cases = [ - (0.1, 1.0, Status::INEXACT), - (-0.1, -0.0, Status::INEXACT), - (0.9, 1.0, Status::INEXACT), - (-0.9, -0.0, Status::INEXACT), - (1.1, 2.0, Status::INEXACT), - (-1.1, -1.0, Status::INEXACT), - (1.9, 2.0, Status::INEXACT), - (-1.9, -1.0, Status::INEXACT), - ]; - spec_test::(&cases); - } - - #[test] - fn sanity_check_f32() { - assert_eq!(ceil(1.1f32), 2.0); - assert_eq!(ceil(2.9f32), 3.0); - } - - #[test] - fn spec_tests_f32() { - let cases = [ - (0.1, 1.0, Status::INEXACT), - (-0.1, -0.0, Status::INEXACT), - (0.9, 1.0, Status::INEXACT), - (-0.9, -0.0, Status::INEXACT), - (1.1, 2.0, Status::INEXACT), - (-1.1, -1.0, Status::INEXACT), - (1.9, 2.0, Status::INEXACT), - (-1.9, -1.0, Status::INEXACT), - ]; - spec_test::(&cases); - } - - #[test] - fn sanity_check_f64() { - assert_eq!(ceil(1.1f64), 2.0); - assert_eq!(ceil(2.9f64), 3.0); - } - - #[test] - fn spec_tests_f64() { - let cases = [ - (0.1, 1.0, Status::INEXACT), - (-0.1, -0.0, Status::INEXACT), - (0.9, 1.0, Status::INEXACT), - (-0.9, -0.0, Status::INEXACT), - (1.1, 2.0, Status::INEXACT), - (-1.1, -1.0, Status::INEXACT), - (1.9, 2.0, Status::INEXACT), - (-1.9, -1.0, Status::INEXACT), - ]; - spec_test::(&cases); - } - - #[test] - #[cfg(f128_enabled)] - fn spec_tests_f128() { - let cases = [ - (0.1, 1.0, Status::INEXACT), - (-0.1, -0.0, Status::INEXACT), - (0.9, 1.0, Status::INEXACT), - (-0.9, -0.0, Status::INEXACT), - (1.1, 2.0, Status::INEXACT), - (-1.1, -1.0, Status::INEXACT), - (1.9, 2.0, Status::INEXACT), - (-1.9, -1.0, Status::INEXACT), - ]; - spec_test::(&cases); - } -} diff --git a/library/compiler-builtins/libm/src/math/generic/floor.rs b/library/compiler-builtins/libm/src/math/generic/floor.rs index e6dfd8866a425..a99d192831e3c 100644 --- a/library/compiler-builtins/libm/src/math/generic/floor.rs +++ b/library/compiler-builtins/libm/src/math/generic/floor.rs @@ -9,11 +9,6 @@ use crate::support::{Float, FpResult, Int, IntTy, MinInt, Status}; -#[inline] -pub fn floor(x: F) -> F { - floor_status(x).val -} - #[inline] pub fn floor_status(x: F) -> FpResult { let zero = IntTy::::ZERO; @@ -26,7 +21,6 @@ pub fn floor_status(x: F) -> FpResult { return FpResult::ok(x); } - let status; let res = if e >= 0 { // |x| >= 1.0 let m = F::SIG_MASK >> e.unsigned(); @@ -35,9 +29,6 @@ pub fn floor_status(x: F) -> FpResult { return FpResult::ok(x); } - // Otherwise, raise an inexact exception. - status = Status::INEXACT; - if x.is_sign_negative() { ix += m; } @@ -45,113 +36,20 @@ pub fn floor_status(x: F) -> FpResult { ix &= !m; F::from_bits(ix) } else { - // |x| < 1.0, raise an inexact exception since truncation will happen. - if ix & F::SIG_MASK == F::Int::ZERO { - status = Status::OK; - } else { - status = Status::INEXACT; + // |x| < 1.0, zero or inexact with truncation + + if (ix & !F::SIGN_MASK) == F::Int::ZERO { + return FpResult::ok(x); } if x.is_sign_positive() { // 0.0 <= x < 1.0; rounding down goes toward +0.0. F::ZERO - } else if ix << 1 != zero { + } else { // -1.0 < x < 0.0; rounding down goes toward -1.0. F::NEG_ONE - } else { - // -0.0 remains unchanged - x } }; - FpResult::new(res, status) -} - -#[cfg(test)] -mod tests { - use super::*; - use crate::support::Hexf; - - /// Test against https://en.cppreference.com/w/cpp/numeric/math/floor - fn spec_test(cases: &[(F, F, Status)]) { - let roundtrip = [ - F::ZERO, - F::ONE, - F::NEG_ONE, - F::NEG_ZERO, - F::INFINITY, - F::NEG_INFINITY, - ]; - - for x in roundtrip { - let FpResult { val, status } = floor_status(x); - assert_biteq!(val, x, "{}", Hexf(x)); - assert_eq!(status, Status::OK, "{}", Hexf(x)); - } - - for &(x, res, res_stat) in cases { - let FpResult { val, status } = floor_status(x); - assert_biteq!(val, res, "{}", Hexf(x)); - assert_eq!(status, res_stat, "{}", Hexf(x)); - } - } - - /* Skipping f16 / f128 "sanity_check"s and spec cases due to rejected literal lexing at MSRV */ - - #[test] - #[cfg(f16_enabled)] - fn spec_tests_f16() { - let cases = []; - spec_test::(&cases); - } - - #[test] - fn sanity_check_f32() { - assert_eq!(floor(0.5f32), 0.0); - assert_eq!(floor(1.1f32), 1.0); - assert_eq!(floor(2.9f32), 2.0); - } - - #[test] - fn spec_tests_f32() { - let cases = [ - (0.1, 0.0, Status::INEXACT), - (-0.1, -1.0, Status::INEXACT), - (0.9, 0.0, Status::INEXACT), - (-0.9, -1.0, Status::INEXACT), - (1.1, 1.0, Status::INEXACT), - (-1.1, -2.0, Status::INEXACT), - (1.9, 1.0, Status::INEXACT), - (-1.9, -2.0, Status::INEXACT), - ]; - spec_test::(&cases); - } - - #[test] - fn sanity_check_f64() { - assert_eq!(floor(1.1f64), 1.0); - assert_eq!(floor(2.9f64), 2.0); - } - - #[test] - fn spec_tests_f64() { - let cases = [ - (0.1, 0.0, Status::INEXACT), - (-0.1, -1.0, Status::INEXACT), - (0.9, 0.0, Status::INEXACT), - (-0.9, -1.0, Status::INEXACT), - (1.1, 1.0, Status::INEXACT), - (-1.1, -2.0, Status::INEXACT), - (1.9, 1.0, Status::INEXACT), - (-1.9, -2.0, Status::INEXACT), - ]; - spec_test::(&cases); - } - - #[test] - #[cfg(f128_enabled)] - fn spec_tests_f128() { - let cases = []; - spec_test::(&cases); - } + FpResult::new(res, Status::INEXACT) } diff --git a/library/compiler-builtins/libm/src/math/generic/fma_wide.rs b/library/compiler-builtins/libm/src/math/generic/fma_wide.rs index a2ef59d3e3d6f..e7d540694135d 100644 --- a/library/compiler-builtins/libm/src/math/generic/fma_wide.rs +++ b/library/compiler-builtins/libm/src/math/generic/fma_wide.rs @@ -1,5 +1,8 @@ +/* SPDX-License-Identifier: MIT */ +/* origin: musl src/math/fmaf.c Ported to generic Rust algorithm in 2025, TG. */ + use crate::support::{ - CastFrom, CastInto, DFloat, Float, FpResult, HFloat, IntTy, MinInt, Round, Status, + CastFrom, CastInto, Float, FpResult, IntTy, MinInt, NarrowFloat, Round, Status, WideFloat, }; /// Fma implementation when a hardware-backed larger float type is available. For `f32` and `f64`, @@ -7,8 +10,8 @@ use crate::support::{ #[inline] pub fn fma_wide_round(x: F, y: F, z: F, round: Round) -> FpResult where - F: Float + HFloat, - B: Float + DFloat, + F: Float + NarrowFloat, + B: Float + WideFloat, B::Int: CastInto, i32: CastFrom, { diff --git a/library/compiler-builtins/libm/src/math/generic/fmax.rs b/library/compiler-builtins/libm/src/math/generic/fmax.rs index b05804704d03e..bdd46cc38a818 100644 --- a/library/compiler-builtins/libm/src/math/generic/fmax.rs +++ b/library/compiler-builtins/libm/src/math/generic/fmax.rs @@ -8,11 +8,15 @@ //! - Otherwise, either `x` or `y`, canonicalized //! - -0.0 and +0.0 may be disregarded (unlike newer operations) //! -//! Excluded from our implementation is sNaN handling. +//! We do not treat sNaN and qNaN differently; even though IEEE technically requires this, (a call +//! with sNaN should return qNaN rather than the other result), it breaks associativity so isn't +//! desired behavior. C23 does not differentiate between sNaN and qNaN, so we do not either. More +//! on the problems with `minNum` [here][minnum-removal]. //! -//! More on the differences: [link]. +//! IEEE also specifies that a sNaN in either argument should signal invalid, but we do not +//! implement this. //! -//! [link]: https://grouper.ieee.org/groups/msc/ANSI_IEEE-Std-754-2019/background/minNum_maxNum_Removal_Demotion_v3.pdf +//! [minnum-removal]: https://grouper.ieee.org/groups/msc/ANSI_IEEE-Std-754-2019/background/minNum_maxNum_Removal_Demotion_v3.pdf use crate::support::Float; diff --git a/library/compiler-builtins/libm/src/math/generic/fmaximum.rs b/library/compiler-builtins/libm/src/math/generic/fmaximum.rs index 55a031e18ee8d..1fa48f964804e 100644 --- a/library/compiler-builtins/libm/src/math/generic/fmaximum.rs +++ b/library/compiler-builtins/libm/src/math/generic/fmaximum.rs @@ -7,7 +7,8 @@ //! - +0.0 if x and y are zero with opposite signs //! - qNaN if either operation is NaN //! -//! Excluded from our implementation is sNaN handling. +//! Note that the IEEE 754-2019 specifies that a sNaN in either argument should signal invalid, +//! but we do not implement this. use crate::support::Float; diff --git a/library/compiler-builtins/libm/src/math/generic/fmaximum_num.rs b/library/compiler-builtins/libm/src/math/generic/fmaximum_num.rs index 2dc60b2d237f5..c7ca50a89dc8d 100644 --- a/library/compiler-builtins/libm/src/math/generic/fmaximum_num.rs +++ b/library/compiler-builtins/libm/src/math/generic/fmaximum_num.rs @@ -9,7 +9,8 @@ //! - Non-NaN if one operand is NaN //! - qNaN if both operands are NaNx //! -//! Excluded from our implementation is sNaN handling. +//! Note that the IEEE 754-2019 specifies that a sNaN in either argument should signal invalid, +//! but we do not implement this. use crate::support::Float; diff --git a/library/compiler-builtins/libm/src/math/generic/fmin.rs b/library/compiler-builtins/libm/src/math/generic/fmin.rs index e2245bf9e137b..e7755e82345c6 100644 --- a/library/compiler-builtins/libm/src/math/generic/fmin.rs +++ b/library/compiler-builtins/libm/src/math/generic/fmin.rs @@ -8,11 +8,15 @@ //! - Otherwise, either `x` or `y`, canonicalized //! - -0.0 and +0.0 may be disregarded (unlike newer operations) //! -//! Excluded from our implementation is sNaN handling. +//! We do not treat sNaN and qNaN differently; even though IEEE technically requires this, (a call +//! with sNaN should return qNaN rather than the other result), it breaks associativity so isn't +//! desired behavior. C23 does not differentiate between sNaN and qNaN, so we do not either. More +//! on the problems with `minNum` [here][minnum-removal]. //! -//! More on the differences: [link]. +//! IEEE also specifies that a sNaN in either argument should signal invalid, but we do not +//! implement this. //! -//! [link]: https://grouper.ieee.org/groups/msc/ANSI_IEEE-Std-754-2019/background/minNum_maxNum_Removal_Demotion_v3.pdf +//! [minnum-removal]: https://grouper.ieee.org/groups/msc/ANSI_IEEE-Std-754-2019/background/minNum_maxNum_Removal_Demotion_v3.pdf use crate::support::Float; diff --git a/library/compiler-builtins/libm/src/math/generic/fminimum.rs b/library/compiler-builtins/libm/src/math/generic/fminimum.rs index aa68b1291d42b..82e72d6440649 100644 --- a/library/compiler-builtins/libm/src/math/generic/fminimum.rs +++ b/library/compiler-builtins/libm/src/math/generic/fminimum.rs @@ -7,7 +7,8 @@ //! - -0.0 if x and y are zero with opposite signs //! - qNaN if either operation is NaN //! -//! Excluded from our implementation is sNaN handling. +//! Note that the IEEE 754-2019 specifies that a sNaN in either argument should signal invalid, +//! but we do not implement this. use crate::support::Float; diff --git a/library/compiler-builtins/libm/src/math/generic/fminimum_num.rs b/library/compiler-builtins/libm/src/math/generic/fminimum_num.rs index 265bd4605ce39..5b5271b123bad 100644 --- a/library/compiler-builtins/libm/src/math/generic/fminimum_num.rs +++ b/library/compiler-builtins/libm/src/math/generic/fminimum_num.rs @@ -9,7 +9,8 @@ //! - Non-NaN if one operand is NaN //! - qNaN if both operands are NaNx //! -//! Excluded from our implementation is sNaN handling. +//! Note that the IEEE 754-2019 specifies that a sNaN in either argument should signal invalid, +//! but we do not implement this. use crate::support::Float; diff --git a/library/compiler-builtins/libm/src/math/generic/frexp.rs b/library/compiler-builtins/libm/src/math/generic/frexp.rs new file mode 100644 index 0000000000000..cbf5b100ba0f8 --- /dev/null +++ b/library/compiler-builtins/libm/src/math/generic/frexp.rs @@ -0,0 +1,26 @@ +use super::super::{CastFrom, Float}; + +#[inline] +pub fn frexp(x: F) -> (F, i32) { + let mut ix = x.to_bits(); + let mut ee = x.ex() as i32; + + if ee == 0 { + if x == F::ZERO { + return (x, 0); + } + + // Subnormals, needs to be normalized first + ix &= F::SIG_MASK; + (ee, ix) = F::normalize(ix); + ix |= x.to_bits() & F::SIGN_MASK; + } else if ee == F::EXP_SAT as i32 { + // inf or NaN + return (x, 0); + } + + let e = ee - (F::EXP_BIAS as i32 - 1); + ix &= F::SIGN_MASK | F::SIG_MASK; + ix |= F::Int::cast_from(F::EXP_BIAS - 1) << F::SIG_BITS; + (F::from_bits(ix), e) +} diff --git a/library/compiler-builtins/libm/src/math/generic/ilogb.rs b/library/compiler-builtins/libm/src/math/generic/ilogb.rs new file mode 100644 index 0000000000000..02a7d6b30b103 --- /dev/null +++ b/library/compiler-builtins/libm/src/math/generic/ilogb.rs @@ -0,0 +1,35 @@ +use super::super::{Float, MinInt}; + +const FP_ILOGBNAN: i32 = i32::MIN; +const FP_ILOGB0: i32 = FP_ILOGBNAN; + +#[inline] +pub fn ilogb(x: F) -> i32 { + let zero = F::Int::ZERO; + let mut i = x.to_bits(); + let e = x.ex() as i32; + + if e == 0 { + i <<= F::EXP_BITS + 1; + if i == F::Int::ZERO { + force_eval!(0.0 / 0.0); + return FP_ILOGB0; + } + /* subnormal x */ + let mut e = -(F::EXP_BIAS as i32); + while i >> (F::BITS - 1) == zero { + e -= 1; + i <<= 1; + } + e + } else if e == F::EXP_SAT as i32 { + force_eval!(0.0 / 0.0); + if i << (F::EXP_BITS + 1) != zero { + FP_ILOGBNAN + } else { + i32::MAX + } + } else { + e - F::EXP_BIAS as i32 + } +} diff --git a/library/compiler-builtins/libm/src/math/generic/mod.rs b/library/compiler-builtins/libm/src/math/generic/mod.rs index 9d497a03f5447..7a26295e39077 100644 --- a/library/compiler-builtins/libm/src/math/generic/mod.rs +++ b/library/compiler-builtins/libm/src/math/generic/mod.rs @@ -1,5 +1,11 @@ -// Note: generic functions are marked `#[inline]` because, even though generic functions are -// typically inlined, this does not seem to always be the case. +//! Generic implementations that are shared by multiple types. +//! +//! Implementation and usage notes: +//! +//! * Generic functions are marked `#[inline]` because, even though generic functions are +//! typically inlined, we seem to occasionally run into exceptions. +//! * Tests usually live wherever the functions are consumed (e.g. `src/ceil`) so they can be +//! reused to test arch-specific implementations. mod ceil; mod copysign; @@ -15,17 +21,19 @@ mod fmin; mod fminimum; mod fminimum_num; mod fmod; +mod frexp; +mod ilogb; mod rint; mod round; mod scalbn; mod sqrt; mod trunc; -pub use ceil::ceil; +pub use ceil::ceil_status; pub use copysign::copysign; pub use fabs::fabs; pub use fdim::fdim; -pub use floor::floor; +pub use floor::floor_status; pub use fma::fma_round; pub use fma_wide::fma_wide_round; pub use fmax::fmax; @@ -35,8 +43,12 @@ pub use fmin::fmin; pub use fminimum::fminimum; pub use fminimum_num::fminimum_num; pub use fmod::fmod; -pub use rint::rint_round; +pub use frexp::frexp; +pub use ilogb::ilogb; +pub use rint::rint_status; pub use round::round; pub use scalbn::scalbn; -pub use sqrt::sqrt; -pub use trunc::trunc; +#[cfg(test)] +pub use sqrt::SqrtHelper; +pub use sqrt::sqrt_round; +pub use trunc::trunc_status; diff --git a/library/compiler-builtins/libm/src/math/generic/rint.rs b/library/compiler-builtins/libm/src/math/generic/rint.rs index c5bc27d3de6bc..aa3d94e9a30d8 100644 --- a/library/compiler-builtins/libm/src/math/generic/rint.rs +++ b/library/compiler-builtins/libm/src/math/generic/rint.rs @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: MIT */ /* origin: musl src/math/rint.c */ -use crate::support::{Float, FpResult, Round}; +use crate::support::{Float, FpResult, Status}; /// IEEE 754-2019 `roundToIntegralExact`, which respects rounding mode and raises inexact if /// applicable. #[inline] -pub fn rint_round(x: F, _round: Round) -> FpResult { +pub fn rint_status(x: F) -> FpResult { let toint = F::ONE / F::EPSILON; let e = x.ex(); let positive = x.is_sign_positive(); @@ -14,7 +14,7 @@ pub fn rint_round(x: F, _round: Round) -> FpResult { // On i386 `force_eval!` must be used to force rounding via storage to memory. Otherwise, // the excess precission from x87 would cause an incorrect final result. let force = |x| { - if cfg!(x86_no_sse) && (F::BITS == 32 || F::BITS == 64) { + if cfg!(x86_no_sse2) && (F::BITS == 32 || F::BITS == 64) { force_eval!(x) } else { x @@ -41,90 +41,10 @@ pub fn rint_round(x: F, _round: Round) -> FpResult { } }; - FpResult::ok(res) -} - -#[cfg(test)] -mod tests { - use super::*; - use crate::support::{Hexf, Status}; - - fn spec_test(cases: &[(F, F, Status)]) { - let roundtrip = [ - F::ZERO, - F::ONE, - F::NEG_ONE, - F::NEG_ZERO, - F::INFINITY, - F::NEG_INFINITY, - ]; - - for x in roundtrip { - let FpResult { val, status } = rint_round(x, Round::Nearest); - assert_biteq!(val, x, "rint_round({})", Hexf(x)); - assert_eq!(status, Status::OK, "{}", Hexf(x)); - } - - for &(x, res, res_stat) in cases { - let FpResult { val, status } = rint_round(x, Round::Nearest); - assert_biteq!(val, res, "rint_round({})", Hexf(x)); - assert_eq!(status, res_stat, "{}", Hexf(x)); - } - } - - #[test] - #[cfg(f16_enabled)] - fn spec_tests_f16() { - let cases = []; - spec_test::(&cases); - } - - #[test] - fn spec_tests_f32() { - let cases = [ - (0.1, 0.0, Status::OK), - (-0.1, -0.0, Status::OK), - (0.5, 0.0, Status::OK), - (-0.5, -0.0, Status::OK), - (0.9, 1.0, Status::OK), - (-0.9, -1.0, Status::OK), - (1.1, 1.0, Status::OK), - (-1.1, -1.0, Status::OK), - (1.5, 2.0, Status::OK), - (-1.5, -2.0, Status::OK), - (1.9, 2.0, Status::OK), - (-1.9, -2.0, Status::OK), - (2.8, 3.0, Status::OK), - (-2.8, -3.0, Status::OK), - ]; - spec_test::(&cases); - } - - #[test] - fn spec_tests_f64() { - let cases = [ - (0.1, 0.0, Status::OK), - (-0.1, -0.0, Status::OK), - (0.5, 0.0, Status::OK), - (-0.5, -0.0, Status::OK), - (0.9, 1.0, Status::OK), - (-0.9, -1.0, Status::OK), - (1.1, 1.0, Status::OK), - (-1.1, -1.0, Status::OK), - (1.5, 2.0, Status::OK), - (-1.5, -2.0, Status::OK), - (1.9, 2.0, Status::OK), - (-1.9, -2.0, Status::OK), - (2.8, 3.0, Status::OK), - (-2.8, -3.0, Status::OK), - ]; - spec_test::(&cases); - } - - #[test] - #[cfg(f128_enabled)] - fn spec_tests_f128() { - let cases = []; - spec_test::(&cases); - } + let status = if res == x { + Status::OK + } else { + Status::INEXACT + }; + FpResult::new(res, status) } diff --git a/library/compiler-builtins/libm/src/math/generic/round.rs b/library/compiler-builtins/libm/src/math/generic/round.rs index 16739f01d8775..9cab1e22c2c6c 100644 --- a/library/compiler-builtins/libm/src/math/generic/round.rs +++ b/library/compiler-builtins/libm/src/math/generic/round.rs @@ -1,4 +1,4 @@ -use super::{copysign, trunc}; +use super::{copysign, trunc_status}; use crate::support::{Float, MinInt}; #[inline] @@ -6,78 +6,5 @@ pub fn round(x: F) -> F { let f0p5 = F::from_parts(false, F::EXP_BIAS - 1, F::Int::ZERO); // 0.5 let f0p25 = F::from_parts(false, F::EXP_BIAS - 2, F::Int::ZERO); // 0.25 - trunc(x + copysign(f0p5 - f0p25 * F::EPSILON, x)) -} - -#[cfg(test)] -mod tests { - use super::*; - - #[test] - #[cfg(f16_enabled)] - fn zeroes_f16() { - assert_biteq!(round(0.0_f16), 0.0_f16); - assert_biteq!(round(-0.0_f16), -0.0_f16); - } - - #[test] - #[cfg(f16_enabled)] - fn sanity_check_f16() { - assert_eq!(round(-1.0_f16), -1.0); - assert_eq!(round(2.8_f16), 3.0); - assert_eq!(round(-0.5_f16), -1.0); - assert_eq!(round(0.5_f16), 1.0); - assert_eq!(round(-1.5_f16), -2.0); - assert_eq!(round(1.5_f16), 2.0); - } - - #[test] - fn zeroes_f32() { - assert_biteq!(round(0.0_f32), 0.0_f32); - assert_biteq!(round(-0.0_f32), -0.0_f32); - } - - #[test] - fn sanity_check_f32() { - assert_eq!(round(-1.0_f32), -1.0); - assert_eq!(round(2.8_f32), 3.0); - assert_eq!(round(-0.5_f32), -1.0); - assert_eq!(round(0.5_f32), 1.0); - assert_eq!(round(-1.5_f32), -2.0); - assert_eq!(round(1.5_f32), 2.0); - } - - #[test] - fn zeroes_f64() { - assert_biteq!(round(0.0_f64), 0.0_f64); - assert_biteq!(round(-0.0_f64), -0.0_f64); - } - - #[test] - fn sanity_check_f64() { - assert_eq!(round(-1.0_f64), -1.0); - assert_eq!(round(2.8_f64), 3.0); - assert_eq!(round(-0.5_f64), -1.0); - assert_eq!(round(0.5_f64), 1.0); - assert_eq!(round(-1.5_f64), -2.0); - assert_eq!(round(1.5_f64), 2.0); - } - - #[test] - #[cfg(f128_enabled)] - fn zeroes_f128() { - assert_biteq!(round(0.0_f128), 0.0_f128); - assert_biteq!(round(-0.0_f128), -0.0_f128); - } - - #[test] - #[cfg(f128_enabled)] - fn sanity_check_f128() { - assert_eq!(round(-1.0_f128), -1.0); - assert_eq!(round(2.8_f128), 3.0); - assert_eq!(round(-0.5_f128), -1.0); - assert_eq!(round(0.5_f128), 1.0); - assert_eq!(round(-1.5_f128), -2.0); - assert_eq!(round(1.5_f128), 2.0); - } + trunc_status(x + copysign(f0p5 - f0p25 * F::EPSILON, x)).val } diff --git a/library/compiler-builtins/libm/src/math/generic/sqrt.rs b/library/compiler-builtins/libm/src/math/generic/sqrt.rs index 9481c4cdb7bbe..013f6c097487f 100644 --- a/library/compiler-builtins/libm/src/math/generic/sqrt.rs +++ b/library/compiler-builtins/libm/src/math/generic/sqrt.rs @@ -45,20 +45,6 @@ use crate::support::{ CastFrom, CastInto, DInt, Float, FpResult, HInt, Int, IntTy, MinInt, Round, Status, cold_path, }; -#[inline] -pub fn sqrt(x: F) -> F -where - F: Float + SqrtHelper, - F::Int: HInt, - F::Int: From, - F::Int: From, - F::Int: CastInto, - F::Int: CastInto, - u32: CastInto, -{ - sqrt_round(x, Round::Nearest).val -} - #[inline] pub fn sqrt_round(x: F, _round: Round) -> FpResult where @@ -164,17 +150,17 @@ where let s1_u2: F::ISet1 = ((m_u2) >> (F::BITS - F::ISet1::BITS)).cast(); // Perform iterations, if any, at quarter width (used for `f128`). - let (r1_u0, _s1_u2) = goldschmidt::(r1_u0, s1_u2, F::SET1_ROUNDS, false); + let (r1_u0, _s1_u2) = goldschmidt::(r1_u0, s1_u2, F::SET1_ROUNDS, false); // Widen values and perform iterations at half width (used for `f64` and `f128`). let r2_u0: F::ISet2 = F::ISet2::from(r1_u0) << (F::ISet2::BITS - F::ISet1::BITS); let s2_u2: F::ISet2 = ((m_u2) >> (F::BITS - F::ISet2::BITS)).cast(); - let (r2_u0, _s2_u2) = goldschmidt::(r2_u0, s2_u2, F::SET2_ROUNDS, false); + let (r2_u0, _s2_u2) = goldschmidt::(r2_u0, s2_u2, F::SET2_ROUNDS, false); // Perform final iterations at full width (used for all float types). let r_u0: F::Int = F::Int::from(r2_u0) << (F::BITS - F::ISet2::BITS); let s_u2: F::Int = m_u2; - let (_r_u0, s_u2) = goldschmidt::(r_u0, s_u2, F::FINAL_ROUNDS, true); + let (_r_u0, s_u2) = goldschmidt::(r_u0, s_u2, F::FINAL_ROUNDS, true); // Shift back to mantissa position. let mut m = s_u2 >> (F::EXP_BITS - 2); @@ -250,9 +236,8 @@ fn wmulh(a: I, b: I) -> I { /// Note that performance relies on the optimizer being able to unroll these loops (reasonably /// trivial, `count` is a constant when called). #[inline] -fn goldschmidt(mut r_u0: I, mut s_u2: I, count: u32, final_set: bool) -> (I, I) +fn goldschmidt(mut r_u0: I, mut s_u2: I, count: u32, final_set: bool) -> (I, I) where - F: SqrtHelper, I: HInt + From, { let three_u2 = I::from(0b11u8) << (I::BITS - 2); @@ -365,177 +350,3 @@ static RSQRT_TAB: [u16; 128] = [ 0xc116, 0xc03c, 0xbf65, 0xbe90, 0xbdbe, 0xbcef, 0xbc23, 0xbb59, 0xba91, 0xb9cc, 0xb90a, 0xb84a, 0xb78c, 0xb6d0, 0xb617, 0xb560, ]; - -#[cfg(test)] -mod tests { - use super::*; - - /// Test behavior specified in IEEE 754 `squareRoot`. - fn spec_test() - where - F: Float + SqrtHelper, - F::Int: HInt, - F::Int: From, - F::Int: From, - F::Int: CastInto, - F::Int: CastInto, - u32: CastInto, - { - // Values that should return a NaN and raise invalid - let nan = [F::NEG_INFINITY, F::NEG_ONE, F::NAN, F::MIN]; - - // Values that return unaltered - let roundtrip = [F::ZERO, F::NEG_ZERO, F::INFINITY]; - - for x in nan { - let FpResult { val, status } = sqrt_round(x, Round::Nearest); - assert!(val.is_nan()); - assert!(status == Status::INVALID); - } - - for x in roundtrip { - let FpResult { val, status } = sqrt_round(x, Round::Nearest); - assert_biteq!(val, x); - assert!(status == Status::OK); - } - } - - #[test] - #[cfg(f16_enabled)] - fn sanity_check_f16() { - assert_biteq!(sqrt(100.0f16), 10.0); - assert_biteq!(sqrt(4.0f16), 2.0); - } - - #[test] - #[cfg(f16_enabled)] - fn spec_tests_f16() { - spec_test::(); - } - - #[test] - #[cfg(f16_enabled)] - #[allow(clippy::approx_constant)] - fn conformance_tests_f16() { - let cases = [ - (f16::PI, 0x3f17_u16), - // 10_000.0, using a hex literal for MSRV hack (Rust < 1.67 checks literal widths as - // part of the AST, so the `cfg` is irrelevant here). - (f16::from_bits(0x70e2), 0x5640_u16), - (f16::from_bits(0x0000000f), 0x13bf_u16), - (f16::INFINITY, f16::INFINITY.to_bits()), - ]; - - for (input, output) in cases { - assert_biteq!( - sqrt(input), - f16::from_bits(output), - "input: {input:?} ({:#018x})", - input.to_bits() - ); - } - } - - #[test] - fn sanity_check_f32() { - assert_biteq!(sqrt(100.0f32), 10.0); - assert_biteq!(sqrt(4.0f32), 2.0); - } - - #[test] - fn spec_tests_f32() { - spec_test::(); - } - - #[test] - #[allow(clippy::approx_constant)] - fn conformance_tests_f32() { - let cases = [ - (f32::PI, 0x3fe2dfc5_u32), - (10000.0f32, 0x42c80000_u32), - (f32::from_bits(0x0000000f), 0x1b2f456f_u32), - (f32::INFINITY, f32::INFINITY.to_bits()), - ]; - - for (input, output) in cases { - assert_biteq!( - sqrt(input), - f32::from_bits(output), - "input: {input:?} ({:#018x})", - input.to_bits() - ); - } - } - - #[test] - fn sanity_check_f64() { - assert_biteq!(sqrt(100.0f64), 10.0); - assert_biteq!(sqrt(4.0f64), 2.0); - } - - #[test] - fn spec_tests_f64() { - spec_test::(); - } - - #[test] - #[allow(clippy::approx_constant)] - fn conformance_tests_f64() { - let cases = [ - (f64::PI, 0x3ffc5bf891b4ef6a_u64), - (10000.0, 0x4059000000000000_u64), - (f64::from_bits(0x0000000f), 0x1e7efbdeb14f4eda_u64), - (f64::INFINITY, f64::INFINITY.to_bits()), - ]; - - for (input, output) in cases { - assert_biteq!( - sqrt(input), - f64::from_bits(output), - "input: {input:?} ({:#018x})", - input.to_bits() - ); - } - } - - #[test] - #[cfg(f128_enabled)] - fn sanity_check_f128() { - assert_biteq!(sqrt(100.0f128), 10.0); - assert_biteq!(sqrt(4.0f128), 2.0); - } - - #[test] - #[cfg(f128_enabled)] - fn spec_tests_f128() { - spec_test::(); - } - - #[test] - #[cfg(f128_enabled)] - #[allow(clippy::approx_constant)] - fn conformance_tests_f128() { - let cases = [ - (f128::PI, 0x3fffc5bf891b4ef6aa79c3b0520d5db9_u128), - // 10_000.0, see `f16` for reasoning. - ( - f128::from_bits(0x400c3880000000000000000000000000), - 0x40059000000000000000000000000000_u128, - ), - ( - f128::from_bits(0x0000000f), - 0x1fc9efbdeb14f4ed9b17ae807907e1e9_u128, - ), - (f128::INFINITY, f128::INFINITY.to_bits()), - ]; - - for (input, output) in cases { - assert_biteq!( - sqrt(input), - f128::from_bits(output), - "input: {input:?} ({:#018x})", - input.to_bits() - ); - } - } -} diff --git a/library/compiler-builtins/libm/src/math/generic/trunc.rs b/library/compiler-builtins/libm/src/math/generic/trunc.rs index d5b444d15dfc0..0b252fab94ae1 100644 --- a/library/compiler-builtins/libm/src/math/generic/trunc.rs +++ b/library/compiler-builtins/libm/src/math/generic/trunc.rs @@ -3,146 +3,34 @@ use crate::support::{Float, FpResult, Int, IntTy, MinInt, Status}; -#[inline] -pub fn trunc(x: F) -> F { - trunc_status(x).val -} - #[inline] pub fn trunc_status(x: F) -> FpResult { - let mut xi: F::Int = x.to_bits(); + let xi: F::Int = x.to_bits(); let e: i32 = x.exp_unbiased(); - // C1: The represented value has no fractional part, so no truncation is needed + // The represented value has no fractional part, so no truncation is needed if e >= F::SIG_BITS as i32 { return FpResult::ok(x); } - let mask = if e < 0 { - // C2: If the exponent is negative, the result will be zero so we mask out everything + let clear_mask = if e < 0 { + // If the exponent is negative, the result will be zero so we clear everything // except the sign. - F::SIGN_MASK + !F::SIGN_MASK } else { - // C3: Otherwise, we mask out the last `e` bits of the significand. - !(F::SIG_MASK >> e.unsigned()) + // Otherwise, we keep `e` fractional bits and clear the rest. + F::SIG_MASK >> e.unsigned() }; - // C4: If the to-be-masked-out portion is already zero, we have an exact result - if (xi & !mask) == IntTy::::ZERO { - return FpResult::ok(x); - } - - // C5: Otherwise the result is inexact and we will truncate. Raise `FE_INEXACT`, mask the - // result, and return. - - let status = if xi & F::SIG_MASK == F::Int::ZERO { + let cleared = xi & clear_mask; + let status = if cleared == IntTy::::ZERO { + // If the to-be-zeroed portion is already zero, we have an exact result. Status::OK } else { + // Otherwise the result is inexact and we will truncate, so indicate `FE_INEXACT`. Status::INEXACT }; - xi &= mask; - FpResult::new(F::from_bits(xi), status) -} - -#[cfg(test)] -mod tests { - use super::*; - use crate::support::Hexf; - - fn spec_test(cases: &[(F, F, Status)]) { - let roundtrip = [ - F::ZERO, - F::ONE, - F::NEG_ONE, - F::NEG_ZERO, - F::INFINITY, - F::NEG_INFINITY, - ]; - - for x in roundtrip { - let FpResult { val, status } = trunc_status(x); - assert_biteq!(val, x, "{}", Hexf(x)); - assert_eq!(status, Status::OK, "{}", Hexf(x)); - } - - for &(x, res, res_stat) in cases { - let FpResult { val, status } = trunc_status(x); - assert_biteq!(val, res, "{}", Hexf(x)); - assert_eq!(status, res_stat, "{}", Hexf(x)); - } - } - - /* Skipping f16 / f128 "sanity_check"s and spec cases due to rejected literal lexing at MSRV */ - #[test] - #[cfg(f16_enabled)] - fn spec_tests_f16() { - let cases = []; - spec_test::(&cases); - } - - #[test] - fn sanity_check_f32() { - assert_eq!(trunc(0.5f32), 0.0); - assert_eq!(trunc(1.1f32), 1.0); - assert_eq!(trunc(2.9f32), 2.0); - } - - #[test] - fn spec_tests_f32() { - let cases = [ - (0.1, 0.0, Status::INEXACT), - (-0.1, -0.0, Status::INEXACT), - (0.9, 0.0, Status::INEXACT), - (-0.9, -0.0, Status::INEXACT), - (1.1, 1.0, Status::INEXACT), - (-1.1, -1.0, Status::INEXACT), - (1.9, 1.0, Status::INEXACT), - (-1.9, -1.0, Status::INEXACT), - ]; - spec_test::(&cases); - - assert_biteq!(trunc(1.1f32), 1.0); - assert_biteq!(trunc(1.1f64), 1.0); - - // C1 - assert_biteq!(trunc(hf32!("0x1p23")), hf32!("0x1p23")); - assert_biteq!(trunc(hf64!("0x1p52")), hf64!("0x1p52")); - assert_biteq!(trunc(hf32!("-0x1p23")), hf32!("-0x1p23")); - assert_biteq!(trunc(hf64!("-0x1p52")), hf64!("-0x1p52")); - - // C2 - assert_biteq!(trunc(hf32!("0x1p-1")), 0.0); - assert_biteq!(trunc(hf64!("0x1p-1")), 0.0); - assert_biteq!(trunc(hf32!("-0x1p-1")), -0.0); - assert_biteq!(trunc(hf64!("-0x1p-1")), -0.0); - } - - #[test] - fn sanity_check_f64() { - assert_eq!(trunc(1.1f64), 1.0); - assert_eq!(trunc(2.9f64), 2.0); - } - - #[test] - fn spec_tests_f64() { - let cases = [ - (0.1, 0.0, Status::INEXACT), - (-0.1, -0.0, Status::INEXACT), - (0.9, 0.0, Status::INEXACT), - (-0.9, -0.0, Status::INEXACT), - (1.1, 1.0, Status::INEXACT), - (-1.1, -1.0, Status::INEXACT), - (1.9, 1.0, Status::INEXACT), - (-1.9, -1.0, Status::INEXACT), - ]; - spec_test::(&cases); - } - - #[test] - #[cfg(f128_enabled)] - fn spec_tests_f128() { - let cases = []; - spec_test::(&cases); - } + // Now zero the bits we need to truncate and return. + FpResult::new(F::from_bits(xi ^ cleared), status) } diff --git a/library/compiler-builtins/libm/src/math/hypot.rs b/library/compiler-builtins/libm/src/math/hypot.rs index c0b2a19370cd7..e8bd44ca975d5 100644 --- a/library/compiler-builtins/libm/src/math/hypot.rs +++ b/library/compiler-builtins/libm/src/math/hypot.rs @@ -1,72 +1,301 @@ +/* SPDX-License-Identifier: MIT */ +/* origin: core-math/src/binary64/hypot/hypot.c + * Copyright (c) 2022 Alexei Sibidanov. + * Ported to Rust in 2025, TG + * Approximate CORE-MATH commit: 8ea8ea35c518 + */ + +//! Euclidian distance via the pythagorean theorem (`√(x2 + y2)`). +//! +//! Per IEEE 754-2019: +//! +//! - Domain: `[−∞, +∞] × [−∞, +∞]` +//! - `hypot(±0, ±0)` is +0 +//! - `hypot(±∞, qNaN)` is +∞ +//! - `hypot(qNaN, ±∞)` is +∞. +//! - May raise overflow or underflow + use super::sqrt; +#[allow(unused_imports)] // msrv compat +use super::support::Float; +use super::support::cold_path; + +#[cfg_attr(assert_no_panic, no_panic::no_panic)] +pub fn hypot(x: f64, y: f64) -> f64 { + return cr_hypot(x, y); +} + +fn cr_hypot(mut x: f64, mut y: f64) -> f64 { + let flag = get_flags(); + + let xi = x.to_bits(); + let yi = y.to_bits(); + + let emsk: u64 = 0x7ffu64 << 52; + let mut ex: u64 = xi & emsk; + let mut ey: u64 = yi & emsk; + /* emsk corresponds to the upper bits of NaN and Inf (apart the sign bit) */ + x = x.abs(); + y = y.abs(); + if ex == emsk || ey == emsk { + cold_path(); + + /* Either x or y is NaN or Inf */ + let wx: u64 = xi << 1; + let wy: u64 = yi << 1; + let wm: u64 = emsk << 1; + + let one_inf = (wx == wm) ^ (wy == wm); + let one_nan = x.is_nan() ^ y.is_nan(); + + // let nqnn: i32 = (((wx >> 52) == 0xfff) ^ ((wy >> 52) == 0xfff)) as i32; + // /* ninf is 1 when only one of x and y is +/-Inf + // nqnn is 1 when only one of x and y is qNaN + // IEEE 754 says that hypot(+/-Inf,qNaN)=hypot(qNaN,+/-Inf)=+Inf. */ + if one_inf && one_nan { + return f64::INFINITY; + } + return x + y; /* inf, sNaN */ + } + + let u: f64 = x.max(y); + let v: f64 = x.min(y); + let mut xd: u64 = u.to_bits(); + let mut yd: u64 = v.to_bits(); + ey = yd; -const SPLIT: f64 = 134217728. + 1.; // 0x1p27 + 1 === (2 ^ 27) + 1 + if ey >> 52 == 0 { + cold_path(); -fn sq(x: f64) -> (f64, f64) { - let xh: f64; - let xl: f64; - let xc: f64; + if yd == 0 { + return f64::from_bits(xd); + } - xc = x * SPLIT; - xh = x - xc + xc; - xl = x - xh; - let hi = x * x; - let lo = xh * xh - hi + 2. * xh * xl + xl * xl; - (hi, lo) + ex = xd; + + if ex >> 52 == 0 { + cold_path(); + + if ex == 0 { + return 0.0; + } + + return as_hypot_denorm(ex, ey); + } + + let nz: u32 = ey.leading_zeros(); + ey <<= nz - 11; + ey &= u64::MAX >> 12; + ey = ey.wrapping_sub(((nz as i64 - 12i64) << 52) as u64); + let t = ey; // why did they do this? + yd = t; + } + + let de: u64 = xd.wrapping_sub(yd); + if de > (27_u64 << 52) { + cold_path(); + return hf64!("0x1p-27").fma(v, u); + } + + let off: i64 = (0x3ff_i64 << 52) - (xd & emsk) as i64; + xd = xd.wrapping_add(off as u64); + yd = yd.wrapping_add(off as u64); + x = f64::from_bits(xd); + y = f64::from_bits(yd); + let x2: f64 = x * x; + let dx2: f64 = x.fma(x, -x2); + let y2: f64 = y * y; + let dy2: f64 = y.fma(y, -y2); + let r2: f64 = x2 + y2; + let ir2: f64 = 0.5 / r2; + let dr2: f64 = ((x2 - r2) + y2) + (dx2 + dy2); + let mut th: f64 = sqrt(r2); + let rsqrt: f64 = th * ir2; + let dz: f64 = dr2 - th.fma(th, -r2); + let mut tl: f64 = rsqrt * dz; + th = fasttwosum(th, tl, &mut tl); + let mut thd: u64 = th.to_bits(); + let tld = tl.abs().to_bits(); + ex = thd; + ey = tld; + ex &= 0x7ff_u64 << 52; + let aidr: u64 = ey.wrapping_add(0x3fe_u64 << 52).wrapping_sub(ex); + let mid: u64 = (aidr.wrapping_sub(0x3c90000000000000).wrapping_add(16)) >> 5; + if mid == 0 || !(0x39b0000000000000_u64..=0x3c9fffffffffff80_u64).contains(&aidr) { + cold_path(); + thd = as_hypot_hard(x, y, flag).to_bits(); + } + thd = thd.wrapping_sub(off as u64); + if thd >= (0x7ff_u64 << 52) { + cold_path(); + return as_hypot_overflow(); + } + + f64::from_bits(thd) } -#[cfg_attr(assert_no_panic, no_panic::no_panic)] -pub fn hypot(mut x: f64, mut y: f64) -> f64 { - let x1p700 = f64::from_bits(0x6bb0000000000000); // 0x1p700 === 2 ^ 700 - let x1p_700 = f64::from_bits(0x1430000000000000); // 0x1p-700 === 2 ^ -700 - - let mut uxi = x.to_bits(); - let mut uyi = y.to_bits(); - let uti; - let ex: i64; - let ey: i64; - let mut z: f64; - - /* arrange |x| >= |y| */ - uxi &= -1i64 as u64 >> 1; - uyi &= -1i64 as u64 >> 1; - if uxi < uyi { - uti = uxi; - uxi = uyi; - uyi = uti; +fn fasttwosum(x: f64, y: f64, e: &mut f64) -> f64 { + let s: f64 = x + y; + let z: f64 = s - x; + *e = y - z; + s +} + +fn as_hypot_overflow() -> f64 { + let z: f64 = hf64!("0x1.fffffffffffffp1023"); + let f = z + z; + if f > z { + // errno = ERANGE + } + f +} + +/// Here the square root is refined by Newton iterations: x^2+y^2 is exact +/// and fits in a 128-bit integer, so the approximation is squared (which +/// also fits in a 128-bit integer), compared and adjusted if necessary using +/// the exact value of x^2+y^2. +fn as_hypot_hard(x: f64, y: f64, flag: FExcept) -> f64 { + let op: f64 = 1.0 + hf64!("0x1p-54"); + let om: f64 = 1.0 - hf64!("0x1p-54"); + let mut xi: u64 = x.to_bits(); + let yi: u64 = y.to_bits(); + let mut bm: u64 = (xi & (u64::MAX >> 12)) | 1u64 << 52; + let mut lm: u64 = (yi & (u64::MAX >> 12)) | 1u64 << 52; + let be: i32 = (xi >> 52) as i32; + let le: i32 = (yi >> 52) as i32; + let ri: u64 = sqrt(x * x + y * y).to_bits(); + let bs: i32 = 2; + let mut rm: u64 = ri & (u64::MAX >> 12); + let mut re: i32 = (ri >> 52) as i32 - 0x3ff; + rm |= 1u64 << 52; + + for _ in 0..3 { + if rm == 1u64 << 52 { + rm = u64::MAX >> 11; + re -= 1; + } else { + cold_path(); + rm -= 1; + } + } + + bm <<= bs; + let mut m2: u64 = bm.wrapping_mul(bm); + let de: i32 = be - le; + let mut ls: i32 = bs - de; + + if ls >= 0 { + lm <<= ls; + m2 = m2.wrapping_add(lm.wrapping_mul(lm)); + } else { + cold_path(); + let lm2: u128 = (lm as u128) * (lm as u128); + ls *= 2; + m2 = m2.wrapping_add((lm2 >> -ls) as u64); + m2 |= ((lm2 << (128 + ls)) != 0) as u64; + } + + let k: i32 = bs + re; + let mut d: i64; + + loop { + rm += 1 + (rm >= (1u64 << 53)) as u64; + let tm: u64 = rm << k; + let rm2: u64 = tm.wrapping_mul(tm); + d = m2 as i64 - rm2 as i64; + + if d <= 0 { + break; + } } - /* special cases */ - ex = (uxi >> 52) as i64; - ey = (uyi >> 52) as i64; - x = f64::from_bits(uxi); - y = f64::from_bits(uyi); - /* note: hypot(inf,nan) == inf */ - if ey == 0x7ff { - return y; + if d == 0 { + set_flags(flag); + } else if op == om { + let tm: u64 = (rm << k) - (1 << (k - (rm <= (1u64 << 53)) as i32)); + d = m2 as i64 - (tm.wrapping_mul(tm)) as i64; + + if d == 0 { + cold_path(); + rm -= rm & 1; + } else { + rm = rm.wrapping_add((d >> 63) as u64); + } + } else { + cold_path(); + rm -= ((op == 1.0) as u64) << (rm > (1u64 << 53)) as u32; } - if ex == 0x7ff || uyi == 0 { - return x; + + if rm >= (1u64 << 53) { + rm >>= 1; + re += 1; } - /* note: hypot(x,y) ~= x + y*y/x/2 with inexact for small y/x */ - /* 64 difference is enough for ld80 double_t */ - if ex - ey > 64 { - return x + y; + + let e: u64 = (be - 1 + re) as u64; + xi = (e << 52) + rm; + + f64::from_bits(xi) +} + +fn as_hypot_denorm(mut a: u64, mut b: u64) -> f64 { + let op: f64 = 1.0 + hf64!("0x1p-54"); + let om: f64 = 1.0 - hf64!("0x1p-54"); + let af: f64 = a as i64 as f64; + let bf: f64 = b as i64 as f64; + a <<= 1; + b <<= 1; + // Is this casting right? + let mut rm: u64 = sqrt(af * af + bf * bf) as u64; + let tm: u64 = rm << 1; + let mut d: i64 = (a.wrapping_mul(a) as i64) + .wrapping_sub(tm.wrapping_mul(tm) as i64) + .wrapping_add(b.wrapping_mul(b) as i64); + let sd: i64 = d >> 63; + let um: i64 = ((rm as i64) ^ sd) - sd; + let mut drm: i64 = sd + 1; + let mut dd: i64 = (um << 3) + 4; + let mut p_d: i64; + rm -= drm as u64; + drm += sd; + loop { + p_d = d; + rm = rm.wrapping_add(drm as u64); + d = d.wrapping_sub(dd); + dd = dd.wrapping_add(8); + if (d ^ p_d) <= 0 { + cold_path(); + break; + } } + p_d = (sd & d) + (!sd & p_d); + if p_d != 0 { + if op == om { + let sum: i64 = p_d + .wrapping_sub(4u64.wrapping_mul(rm) as i64) + .wrapping_sub(1); - /* precise sqrt argument in nearest rounding mode without overflow */ - /* xh*xh must not overflow and xl*xl must not underflow in sq */ - z = 1.; - if ex > 0x3ff + 510 { - z = x1p700; - x *= x1p_700; - y *= x1p_700; - } else if ey < 0x3ff - 450 { - z = x1p_700; - x *= x1p700; - y *= x1p700; + if sum != 0 { + rm = rm.wrapping_add((sum >> 63).wrapping_add(1) as u64); + } else { + cold_path(); + rm += rm & 1; + } + } else { + cold_path(); + rm += (op > 1.0) as u64; + } + } else { + cold_path(); } - let (hx, lx) = sq(x); - let (hy, ly) = sq(y); - z * sqrt(ly + lx + hy + hx) + + let xi: u64 = rm; + f64::from_bits(xi) +} + +type FExcept = u32; + +fn set_flags(_flag: FExcept) {} + +fn get_flags() -> FExcept { + 0 } diff --git a/library/compiler-builtins/libm/src/math/ilogb.rs b/library/compiler-builtins/libm/src/math/ilogb.rs index ef774f6ad3a65..4c3f0a6aa0452 100644 --- a/library/compiler-builtins/libm/src/math/ilogb.rs +++ b/library/compiler-builtins/libm/src/math/ilogb.rs @@ -1,32 +1,25 @@ -const FP_ILOGBNAN: i32 = -1 - 0x7fffffff; -const FP_ILOGB0: i32 = FP_ILOGBNAN; +/// Extract the binary exponent of `x`. +#[cfg(f16_enabled)] +#[cfg_attr(assert_no_panic, no_panic::no_panic)] +pub fn ilogbf16(x: f16) -> i32 { + super::generic::ilogb(x) +} +/// Extract the binary exponent of `x`. +#[cfg_attr(assert_no_panic, no_panic::no_panic)] +pub fn ilogbf(x: f32) -> i32 { + super::generic::ilogb(x) +} + +/// Extract the binary exponent of `x`. #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn ilogb(x: f64) -> i32 { - let mut i: u64 = x.to_bits(); - let e = ((i >> 52) & 0x7ff) as i32; + super::generic::ilogb(x) +} - if e == 0 { - i <<= 12; - if i == 0 { - force_eval!(0.0 / 0.0); - return FP_ILOGB0; - } - /* subnormal x */ - let mut e = -0x3ff; - while (i >> 63) == 0 { - e -= 1; - i <<= 1; - } - e - } else if e == 0x7ff { - force_eval!(0.0 / 0.0); - if (i << 12) != 0 { - FP_ILOGBNAN - } else { - i32::MAX - } - } else { - e - 0x3ff - } +/// Extract the binary exponent of `x`. +#[cfg(f128_enabled)] +#[cfg_attr(assert_no_panic, no_panic::no_panic)] +pub fn ilogbf128(x: f128) -> i32 { + super::generic::ilogb(x) } diff --git a/library/compiler-builtins/libm/src/math/ilogbf.rs b/library/compiler-builtins/libm/src/math/ilogbf.rs deleted file mode 100644 index 5b0cb46ec558b..0000000000000 --- a/library/compiler-builtins/libm/src/math/ilogbf.rs +++ /dev/null @@ -1,28 +0,0 @@ -const FP_ILOGBNAN: i32 = -1 - 0x7fffffff; -const FP_ILOGB0: i32 = FP_ILOGBNAN; - -#[cfg_attr(assert_no_panic, no_panic::no_panic)] -pub fn ilogbf(x: f32) -> i32 { - let mut i = x.to_bits(); - let e = ((i >> 23) & 0xff) as i32; - - if e == 0 { - i <<= 9; - if i == 0 { - force_eval!(0.0 / 0.0); - return FP_ILOGB0; - } - /* subnormal x */ - let mut e = -0x7f; - while (i >> 31) == 0 { - e -= 1; - i <<= 1; - } - e - } else if e == 0xff { - force_eval!(0.0 / 0.0); - if (i << 9) != 0 { FP_ILOGBNAN } else { i32::MAX } - } else { - e - 0x7f - } -} diff --git a/library/compiler-builtins/libm/src/math/j1f.rs b/library/compiler-builtins/libm/src/math/j1f.rs index cd829c1aa1213..d545a8635b127 100644 --- a/library/compiler-builtins/libm/src/math/j1f.rs +++ b/library/compiler-builtins/libm/src/math/j1f.rs @@ -374,8 +374,7 @@ mod tests { fn test_y1f_2002() { //allow slightly different result on x87 let res = y1f(2.0000002_f32); - if cfg!(all(target_arch = "x86", not(target_feature = "sse2"))) && (res == -0.10703231_f32) - { + if cfg!(x86_no_sse2) && (res == -0.10703231_f32) { return; } assert_eq!(res, -0.10703229_f32); diff --git a/library/compiler-builtins/libm/src/math/lgamma_r.rs b/library/compiler-builtins/libm/src/math/lgamma_r.rs index 38eb270f68390..f3c6fef1464d8 100644 --- a/library/compiler-builtins/libm/src/math/lgamma_r.rs +++ b/library/compiler-builtins/libm/src/math/lgamma_r.rs @@ -79,6 +79,7 @@ */ use super::{floor, k_cos, k_sin, log}; +use crate::support::unchecked_div_i32; const PI: f64 = 3.14159265358979311600e+00; /* 0x400921FB, 0x54442D18 */ const A0: f64 = 7.72156649015328655494e-02; /* 0x3FB3C467, 0xE37DB0C8 */ @@ -152,7 +153,8 @@ fn sin_pi(mut x: f64) -> f64 { x = 2.0 * (x * 0.5 - floor(x * 0.5)); /* x mod 2.0 */ n = (x * 4.0) as i32; - n = div!(n + 1, 2); + // SAFETY: nonzero divisor, nonnegative dividend (`n < 8`). + n = unsafe { unchecked_div_i32(n + 1, 2) }; x -= (n as f64) * 0.5; x *= PI; diff --git a/library/compiler-builtins/libm/src/math/lgammaf_r.rs b/library/compiler-builtins/libm/src/math/lgammaf_r.rs index a0b6a678a6709..9e60bb267cb77 100644 --- a/library/compiler-builtins/libm/src/math/lgammaf_r.rs +++ b/library/compiler-builtins/libm/src/math/lgammaf_r.rs @@ -14,6 +14,7 @@ */ use super::{floorf, k_cosf, k_sinf, logf}; +use crate::support::unchecked_div_isize; const PI: f32 = 3.1415927410e+00; /* 0x40490fdb */ const A0: f32 = 7.7215664089e-02; /* 0x3d9e233f */ @@ -88,7 +89,8 @@ fn sin_pi(mut x: f32) -> f32 { x = 2.0 * (x * 0.5 - floorf(x * 0.5)); /* x mod 2.0 */ n = (x * 4.0) as isize; - n = div!(n + 1, 2); + // SAFETY: nonzero divisor, nonnegative dividend (`n < 8`). + n = unsafe { unchecked_div_isize(n + 1, 2) }; y = (x as f64) - (n as f64) * 0.5; y *= 3.14159265358979323846; match n { @@ -176,7 +178,7 @@ pub fn lgammaf_r(mut x: f32) -> (f32, i32) { /* [1.7316,2] */ y = 2.0 - x; i = 0; - } else if ix >= 0x3F9da620 { + } else if ix >= 0x3f9da620 { /* [1.23,1.73] */ y = x - TC; i = 1; diff --git a/library/compiler-builtins/libm/src/math/mod.rs b/library/compiler-builtins/libm/src/math/mod.rs index 8eecfe5667d1f..50b42e0c07972 100644 --- a/library/compiler-builtins/libm/src/math/mod.rs +++ b/library/compiler-builtins/libm/src/math/mod.rs @@ -58,24 +58,6 @@ macro_rules! i { }; } -// Temporary macro to avoid panic codegen for division (in debug mode too). At -// the time of this writing this is only used in a few places, and once -// rust-lang/rust#72751 is fixed then this macro will no longer be necessary and -// the native `/` operator can be used and panics won't be codegen'd. -#[cfg(any(debug_assertions, not(intrinsics_enabled)))] -macro_rules! div { - ($a:expr, $b:expr) => { - $a / $b - }; -} - -#[cfg(all(not(debug_assertions), intrinsics_enabled))] -macro_rules! div { - ($a:expr, $b:expr) => { - unsafe { core::intrinsics::unchecked_div($a, $b) } - }; -} - // `support` may be public for testing #[macro_use] #[cfg(feature = "unstable-public-internals")] @@ -85,14 +67,17 @@ pub mod support; #[cfg(not(feature = "unstable-public-internals"))] pub(crate) mod support; -cfg_if! { - if #[cfg(feature = "unstable-public-internals")] { +cfg_select_nofmt! { + feature = "unstable-public-internals" => { pub mod generic; - } else { + } + _ => { mod generic; } } +pub mod relaxed; + // Private modules mod arch; mod expo2; @@ -122,7 +107,9 @@ use self::rem_pio2::rem_pio2; use self::rem_pio2_large::rem_pio2_large; use self::rem_pio2f::rem_pio2f; #[allow(unused_imports)] -use self::support::{CastFrom, CastInto, DFloat, DInt, Float, HFloat, HInt, Int, IntTy, MinInt}; +use self::support::{ + CastFrom, CastInto, DInt, Float, HInt, Int, IntTy, MinInt, NarrowFloat, WideFloat, +}; // Public modules mod acos; @@ -166,11 +153,9 @@ mod fminimum_fmaximum; mod fminimum_fmaximum_num; mod fmod; mod frexp; -mod frexpf; mod hypot; mod hypotf; mod ilogb; -mod ilogbf; mod j0; mod j0f; mod j1; @@ -260,12 +245,10 @@ pub use self::fmin_fmax::{fmax, fmaxf, fmin, fminf}; pub use self::fminimum_fmaximum::{fmaximum, fmaximumf, fminimum, fminimumf}; pub use self::fminimum_fmaximum_num::{fmaximum_num, fmaximum_numf, fminimum_num, fminimum_numf}; pub use self::fmod::{fmod, fmodf}; -pub use self::frexp::frexp; -pub use self::frexpf::frexpf; +pub use self::frexp::{frexp, frexpf}; pub use self::hypot::hypot; pub use self::hypotf::hypotf; -pub use self::ilogb::ilogb; -pub use self::ilogbf::ilogbf; +pub use self::ilogb::{ilogb, ilogbf}; pub use self::j0::{j0, y0}; pub use self::j0f::{j0f, y0f}; pub use self::j1::{j1, y1}; @@ -314,18 +297,23 @@ pub use self::tgamma::tgamma; pub use self::tgammaf::tgammaf; pub use self::trunc::{trunc, truncf}; -cfg_if! { - if #[cfg(f16_enabled)] { +cfg_select_nofmt! { + f16_enabled => { + mod fmaf16; + // verify-sorted-start pub use self::ceil::ceilf16; pub use self::copysign::copysignf16; pub use self::fabs::fabsf16; pub use self::fdim::fdimf16; pub use self::floor::floorf16; + pub use self::fmaf16::fmaf16; pub use self::fmin_fmax::{fmaxf16, fminf16}; pub use self::fminimum_fmaximum::{fmaximumf16, fminimumf16}; pub use self::fminimum_fmaximum_num::{fmaximum_numf16, fminimum_numf16}; pub use self::fmod::fmodf16; + pub use self::frexp::frexpf16; + pub use self::ilogb::ilogbf16; pub use self::ldexp::ldexpf16; pub use self::rint::rintf16; pub use self::round::roundf16; @@ -334,14 +322,12 @@ cfg_if! { pub use self::sqrt::sqrtf16; pub use self::trunc::truncf16; // verify-sorted-end - - #[allow(unused_imports)] - pub(crate) use self::fma::fmaf16; } + _ => {} } -cfg_if! { - if #[cfg(f128_enabled)] { +cfg_select_nofmt! { + f128_enabled => { // verify-sorted-start pub use self::ceil::ceilf128; pub use self::copysign::copysignf128; @@ -353,6 +339,8 @@ cfg_if! { pub use self::fminimum_fmaximum::{fmaximumf128, fminimumf128}; pub use self::fminimum_fmaximum_num::{fmaximum_numf128, fminimum_numf128}; pub use self::fmod::fmodf128; + pub use self::frexp::frexpf128; + pub use self::ilogb::ilogbf128; pub use self::ldexp::ldexpf128; pub use self::rint::rintf128; pub use self::round::roundf128; @@ -362,6 +350,7 @@ cfg_if! { pub use self::trunc::truncf128; // verify-sorted-end } + _ => {} } #[inline] diff --git a/library/compiler-builtins/libm/src/math/pow.rs b/library/compiler-builtins/libm/src/math/pow.rs index 914d68cfce1a2..87eaab3c7c727 100644 --- a/library/compiler-builtins/libm/src/math/pow.rs +++ b/library/compiler-builtins/libm/src/math/pow.rs @@ -472,9 +472,9 @@ mod tests { let exp = expected(*val); let res = computed(*val); - #[cfg(all(target_arch = "x86", not(target_feature = "sse2")))] + #[cfg(x86_no_sse2)] let exp = force_eval!(exp); - #[cfg(all(target_arch = "x86", not(target_feature = "sse2")))] + #[cfg(x86_no_sse2)] let res = force_eval!(res); assert!( if exp.is_nan() { diff --git a/library/compiler-builtins/libm/src/math/relaxed/cbrtf64.rs b/library/compiler-builtins/libm/src/math/relaxed/cbrtf64.rs new file mode 100644 index 0000000000000..7b371feb96b6d --- /dev/null +++ b/library/compiler-builtins/libm/src/math/relaxed/cbrtf64.rs @@ -0,0 +1,113 @@ +/* origin: FreeBSD /usr/src/lib/msun/src/s_cbrt.c */ +/* + * ==================================================== + * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. + * + * Developed at SunPro, a Sun Microsystems, Inc. business. + * Permission to use, copy, modify, and distribute this + * software is freely granted, provided that this notice + * is preserved. + * ==================================================== + * + * Optimized by Bruce D. Evans. + */ +/* cbrt(x) + * Return cube root of x + */ + +use core::f64; + +const B1: u32 = 715094163; /* B1 = (1023-1023/3-0.03306235651)*2**20 */ +const B2: u32 = 696219795; /* B2 = (1023-1023/3-54/3-0.03306235651)*2**20 */ + +/* |1/cbrt(x) - p(x)| < 2**-23.5 (~[-7.93e-8, 7.929e-8]). */ +const P0: f64 = 1.87595182427177009643; /* 0x3ffe03e6, 0x0f61e692 */ +const P1: f64 = -1.88497979543377169875; /* 0xbffe28e0, 0x92f02420 */ +const P2: f64 = 1.621429720105354466140; /* 0x3ff9f160, 0x4a49d6c2 */ +const P3: f64 = -0.758397934778766047437; /* 0xbfe844cb, 0xbee751d9 */ +const P4: f64 = 0.145996192886612446982; /* 0x3fc2b000, 0xd4e4edd7 */ + +/// Cube root (f64) +/// +/// Computes the cube root of the argument. +#[cfg_attr(assert_no_panic, no_panic::no_panic)] +pub fn cbrtf64(x: f64) -> f64 { + let x1p54 = f64::from_bits(0x4350000000000000); // 0x1p54 === 2 ^ 54 + + let mut ui: u64 = x.to_bits(); + let mut r: f64; + let s: f64; + let mut t: f64; + let w: f64; + let mut hx: u32 = (ui >> 32) as u32 & 0x7fffffff; + + if hx >= 0x7ff00000 { + /* cbrt(NaN,INF) is itself */ + return x + x; + } + + /* + * Rough cbrt to 5 bits: + * cbrt(2**e*(1+m) ~= 2**(e/3)*(1+(e%3+m)/3) + * where e is integral and >= 0, m is real and in [0, 1), and "/" and + * "%" are integer division and modulus with rounding towards minus + * infinity. The RHS is always >= the LHS and has a maximum relative + * error of about 1 in 16. Adding a bias of -0.03306235651 to the + * (e%3+m)/3 term reduces the error to about 1 in 32. With the IEEE + * floating point representation, for finite positive normal values, + * ordinary integer divison of the value in bits magically gives + * almost exactly the RHS of the above provided we first subtract the + * exponent bias (1023 for doubles) and later add it back. We do the + * subtraction virtually to keep e >= 0 so that ordinary integer + * division rounds towards minus infinity; this is also efficient. + */ + if hx < 0x00100000 { + /* zero or subnormal? */ + ui = (x * x1p54).to_bits(); + hx = (ui >> 32) as u32 & 0x7fffffff; + if hx == 0 { + return x; /* cbrt(0) is itself */ + } + hx = hx / 3 + B2; + } else { + hx = hx / 3 + B1; + } + ui &= 1 << 63; + ui |= (hx as u64) << 32; + t = f64::from_bits(ui); + + /* + * New cbrt to 23 bits: + * cbrt(x) = t*cbrt(x/t**3) ~= t*P(t**3/x) + * where P(r) is a polynomial of degree 4 that approximates 1/cbrt(r) + * to within 2**-23.5 when |r - 1| < 1/10. The rough approximation + * has produced t such than |t/cbrt(x) - 1| ~< 1/32, and cubing this + * gives us bounds for r = t**3/x. + * + * Try to optimize for parallel evaluation as in __tanf.c. + */ + r = (t * t) * (t / x); + t = t * ((P0 + r * (P1 + r * P2)) + ((r * r) * r) * (P3 + r * P4)); + + /* + * Round t away from zero to 23 bits (sloppily except for ensuring that + * the result is larger in magnitude than cbrt(x) but not much more than + * 2 23-bit ulps larger). With rounding towards zero, the error bound + * would be ~5/6 instead of ~4/6. With a maximum error of 2 23-bit ulps + * in the rounded t, the infinite-precision error in the Newton + * approximation barely affects third digit in the final error + * 0.667; the error in the rounded t can be up to about 3 23-bit ulps + * before the final error is larger than 0.667 ulps. + */ + ui = t.to_bits(); + ui = (ui + 0x80000000) & 0xffffffffc0000000; + t = f64::from_bits(ui); + + /* one step Newton iteration to 53 bits with error < 0.667 ulps */ + s = t * t; /* t*t is exact */ + r = x / s; /* error <= 0.5 ulps; |r| < |t| */ + w = t + t; /* t+t is exact */ + r = (r - t) / (w + r); /* r-t is exact; w+r ~= 3*t */ + t = t + t * r; /* error <= 0.5 + 0.5/3 + epsilon */ + t +} diff --git a/library/compiler-builtins/libm/src/math/relaxed/hypotf64.rs b/library/compiler-builtins/libm/src/math/relaxed/hypotf64.rs new file mode 100644 index 0000000000000..ae4196aefff03 --- /dev/null +++ b/library/compiler-builtins/libm/src/math/relaxed/hypotf64.rs @@ -0,0 +1,72 @@ +use super::super::sqrt; + +const SPLIT: f64 = 134217728. + 1.; // 0x1p27 + 1 === (2 ^ 27) + 1 + +fn sq(x: f64) -> (f64, f64) { + let xh: f64; + let xl: f64; + let xc: f64; + + xc = x * SPLIT; + xh = x - xc + xc; + xl = x - xh; + let hi = x * x; + let lo = xh * xh - hi + 2. * xh * xl + xl * xl; + (hi, lo) +} + +#[cfg_attr(assert_no_panic, no_panic::no_panic)] +pub fn hypotf64(mut x: f64, mut y: f64) -> f64 { + let x1p700 = f64::from_bits(0x6bb0000000000000); // 0x1p700 === 2 ^ 700 + let x1p_700 = f64::from_bits(0x1430000000000000); // 0x1p-700 === 2 ^ -700 + + let mut uxi = x.to_bits(); + let mut uyi = y.to_bits(); + let uti; + let ex: i64; + let ey: i64; + let mut z: f64; + + /* arrange |x| >= |y| */ + uxi &= -1i64 as u64 >> 1; + uyi &= -1i64 as u64 >> 1; + if uxi < uyi { + uti = uxi; + uxi = uyi; + uyi = uti; + } + + /* special cases */ + ex = (uxi >> 52) as i64; + ey = (uyi >> 52) as i64; + x = f64::from_bits(uxi); + y = f64::from_bits(uyi); + /* note: hypot(inf,nan) == inf */ + if ey == 0x7ff { + return y; + } + if ex == 0x7ff || uyi == 0 { + return x; + } + /* note: hypot(x,y) ~= x + y*y/x/2 with inexact for small y/x */ + /* 64 difference is enough for ld80 double_t */ + if ex - ey > 64 { + return x + y; + } + + /* precise sqrt argument in nearest rounding mode without overflow */ + /* xh*xh must not overflow and xl*xl must not underflow in sq */ + z = 1.; + if ex > 0x3ff + 510 { + z = x1p700; + x *= x1p_700; + y *= x1p_700; + } else if ey < 0x3ff - 450 { + z = x1p_700; + x *= x1p700; + y *= x1p700; + } + let (hx, lx) = sq(x); + let (hy, ly) = sq(y); + z * sqrt(ly + lx + hy + hx) +} diff --git a/library/compiler-builtins/libm/src/math/relaxed/mod.rs b/library/compiler-builtins/libm/src/math/relaxed/mod.rs new file mode 100644 index 0000000000000..ed3b4146249fb --- /dev/null +++ b/library/compiler-builtins/libm/src/math/relaxed/mod.rs @@ -0,0 +1,10 @@ +//! Relaxed precision implementations. +//! +//! These functions may be smaller or faster than those in the main `math` module, but will +//! not be as accurate. + +mod cbrtf64; +mod hypotf64; + +pub use cbrtf64::cbrtf64; +pub use hypotf64::hypotf64; diff --git a/library/compiler-builtins/libm/src/math/rem_pio2.rs b/library/compiler-builtins/libm/src/math/rem_pio2.rs index 61b1030275a22..d2be3957358ae 100644 --- a/library/compiler-builtins/libm/src/math/rem_pio2.rs +++ b/library/compiler-builtins/libm/src/math/rem_pio2.rs @@ -53,7 +53,7 @@ pub(crate) fn rem_pio2(x: f64) -> (i32, f64, f64) { let tmp = x * INV_PIO2 + TO_INT; // force rounding of tmp to it's storage format on x87 to avoid // excess precision issues. - #[cfg(all(target_arch = "x86", not(target_feature = "sse2")))] + #[cfg(x86_no_sse2)] let tmp = force_eval!(tmp); let f_n = tmp - TO_INT; let n = f_n as i32; @@ -195,7 +195,7 @@ mod tests { #[test] // FIXME(correctness): inaccurate results on i586 - #[cfg_attr(x86_no_sse, ignore)] + #[cfg_attr(x86_no_sse2, ignore)] fn test_near_pi() { let arg = 3.141592025756836; let arg = force_eval!(arg); diff --git a/library/compiler-builtins/libm/src/math/rem_pio2_large.rs b/library/compiler-builtins/libm/src/math/rem_pio2_large.rs index bb2c532916b2a..8212c1a0a9f42 100644 --- a/library/compiler-builtins/libm/src/math/rem_pio2_large.rs +++ b/library/compiler-builtins/libm/src/math/rem_pio2_large.rs @@ -1,4 +1,6 @@ #![allow(unused_unsafe)] +// FIXME(clippy): the suggested fix is bad but the code as-written could be better +#![allow(clippy::explicit_counter_loop)] /* origin: FreeBSD /usr/src/lib/msun/src/k_rem_pio2.c */ /* * ==================================================== @@ -226,7 +228,7 @@ pub(crate) fn rem_pio2_large(x: &[f64], y: &mut [f64], e0: i32, prec: usize) -> // FIXME(rust-lang/rust#144518): Inline assembly would cause `no_panic` to fail // on the callers of this function. As a workaround, avoid inlining `floor` here // when implemented with assembly. - #[cfg_attr(x86_no_sse, inline(never))] + #[cfg_attr(x86_no_sse2, inline(never))] extern "C" fn floor(x: f64) -> f64 { super::floor(x) } @@ -255,7 +257,7 @@ pub(crate) fn rem_pio2_large(x: &[f64], y: &mut [f64], e0: i32, prec: usize) -> /* determine jx,jv,q0, note that 3>q0 */ let jx = nx - 1; - let mut jv = div!(e0 - 3, 24); + let mut jv = (e0 - 3) / 24; if jv < 0 { jv = 0; } diff --git a/library/compiler-builtins/libm/src/math/rem_pio2f.rs b/library/compiler-builtins/libm/src/math/rem_pio2f.rs index 481f7ee830bbb..bbf8042752137 100644 --- a/library/compiler-builtins/libm/src/math/rem_pio2f.rs +++ b/library/compiler-builtins/libm/src/math/rem_pio2f.rs @@ -44,7 +44,7 @@ pub(crate) fn rem_pio2f(x: f32) -> (i32, f64) { let tmp = x64 * INV_PIO2 + TOINT; // force rounding of tmp to it's storage format on x87 to avoid // excess precision issues. - #[cfg(all(target_arch = "x86", not(target_feature = "sse2")))] + #[cfg(x86_no_sse2)] let tmp = force_eval!(tmp); let f_n = tmp - TOINT; return (f_n as i32, x64 - f_n * PIO2_1 - f_n * PIO2_1T); diff --git a/library/compiler-builtins/libm/src/math/rint.rs b/library/compiler-builtins/libm/src/math/rint.rs index 011a7ae3d60ad..ca3864b1582c9 100644 --- a/library/compiler-builtins/libm/src/math/rint.rs +++ b/library/compiler-builtins/libm/src/math/rint.rs @@ -1,4 +1,4 @@ -use super::support::Round; +use super::generic; /// Round `x` to the nearest integer, breaking ties toward even. #[cfg(f16_enabled)] @@ -10,7 +10,7 @@ pub fn rintf16(x: f16) -> f16 { args: x, } - super::generic::rint_round(x, Round::Nearest).val + generic::rint_status(x).val } /// Round `x` to the nearest integer, breaking ties toward even. @@ -20,12 +20,13 @@ pub fn rintf(x: f32) -> f32 { name: rintf, use_arch: any( all(target_arch = "aarch64", target_feature = "neon"), + all(any(target_arch = "loongarch32", target_arch = "loongarch64"), target_feature = "lsx"), all(target_arch = "wasm32", intrinsics_enabled), ), args: x, } - super::generic::rint_round(x, Round::Nearest).val + generic::rint_status(x).val } /// Round `x` to the nearest integer, breaking ties toward even. @@ -35,17 +36,123 @@ pub fn rint(x: f64) -> f64 { name: rint, use_arch: any( all(target_arch = "aarch64", target_feature = "neon"), + all(any(target_arch = "loongarch32", target_arch = "loongarch64"), target_feature = "lsx"), all(target_arch = "wasm32", intrinsics_enabled), ), + use_arch_required: x86_no_sse2, args: x, } - super::generic::rint_round(x, Round::Nearest).val + generic::rint_status(x).val } /// Round `x` to the nearest integer, breaking ties toward even. #[cfg(f128_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn rintf128(x: f128) -> f128 { - super::generic::rint_round(x, Round::Nearest).val + generic::rint_status(x).val +} + +#[cfg(test)] +mod tests { + use super::*; + use crate::support::{Float, FpResult, Hex, Status}; + + macro_rules! cases { + ($f:ty) => { + [ + // roundtrip + (0.0, 0.0, Status::OK), + (-0.0, -0.0, Status::OK), + (1.0, 1.0, Status::OK), + (-1.0, -1.0, Status::OK), + (<$f>::INFINITY, <$f>::INFINITY, Status::OK), + (<$f>::NEG_INFINITY, <$f>::NEG_INFINITY, Status::OK), + // with rounding + (0.1, 0.0, Status::INEXACT), + (-0.1, -0.0, Status::INEXACT), + (0.5, 0.0, Status::INEXACT), + (-0.5, -0.0, Status::INEXACT), + (0.9, 1.0, Status::INEXACT), + (-0.9, -1.0, Status::INEXACT), + (1.1, 1.0, Status::INEXACT), + (-1.1, -1.0, Status::INEXACT), + (1.5, 2.0, Status::INEXACT), + (-1.5, -2.0, Status::INEXACT), + (1.9, 2.0, Status::INEXACT), + (-1.9, -2.0, Status::INEXACT), + (2.5, 2.0, Status::INEXACT), + (-2.5, -2.0, Status::INEXACT), + (3.5, 4.0, Status::INEXACT), + (-3.5, -4.0, Status::INEXACT), + ] + }; + } + + #[track_caller] + fn check(f: fn(F) -> F, cases: &[(F, F, Status)]) { + for &(x, exp_res, exp_stat) in cases { + let FpResult { val, status } = generic::rint_status(x); + assert_biteq!(val, exp_res, "generic::rint_status({x:?}) ({})", Hex(x)); + assert_eq!( + status, + exp_stat, + "{x:?} {} -> {exp_res:?} {}", + Hex(x), + Hex(exp_res) + ); + let val = f(x); + assert_biteq!(val, exp_res, "rint({x:?}) ({})", Hex(x)); + } + } + + #[test] + #[cfg(f16_enabled)] + fn check_f16() { + check::(rintf16, &cases!(f16)); + check::( + rintf16, + &[ + (hf16!("0x1p10"), hf16!("0x1p10"), Status::OK), + (hf16!("-0x1p10"), hf16!("-0x1p10"), Status::OK), + ], + ); + } + + #[test] + fn check_f32() { + check::(rintf, &cases!(f32)); + check::( + rintf, + &[ + (hf32!("0x1p23"), hf32!("0x1p23"), Status::OK), + (hf32!("-0x1p23"), hf32!("-0x1p23"), Status::OK), + ], + ); + } + + #[test] + fn check_f64() { + check::(rint, &cases!(f64)); + check::( + rint, + &[ + (hf64!("0x1p52"), hf64!("0x1p52"), Status::OK), + (hf64!("-0x1p52"), hf64!("-0x1p52"), Status::OK), + ], + ); + } + + #[test] + #[cfg(f128_enabled)] + fn check_f128() { + check::(rintf128, &cases!(f128)); + check::( + rintf128, + &[ + (hf128!("0x1p112"), hf128!("0x1p112"), Status::OK), + (hf128!("-0x1p112"), hf128!("-0x1p112"), Status::OK), + ], + ); + } } diff --git a/library/compiler-builtins/libm/src/math/round.rs b/library/compiler-builtins/libm/src/math/round.rs index 256197e6ccbee..091cd801ad6b4 100644 --- a/library/compiler-builtins/libm/src/math/round.rs +++ b/library/compiler-builtins/libm/src/math/round.rs @@ -1,25 +1,120 @@ +use super::generic; + /// Round `x` to the nearest integer, breaking ties away from zero. #[cfg(f16_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn roundf16(x: f16) -> f16 { - super::generic::round(x) + generic::round(x) } /// Round `x` to the nearest integer, breaking ties away from zero. #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn roundf(x: f32) -> f32 { - super::generic::round(x) + generic::round(x) } /// Round `x` to the nearest integer, breaking ties away from zero. #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn round(x: f64) -> f64 { - super::generic::round(x) + generic::round(x) } /// Round `x` to the nearest integer, breaking ties away from zero. #[cfg(f128_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn roundf128(x: f128) -> f128 { - super::generic::round(x) + generic::round(x) +} + +#[cfg(test)] +mod tests { + use super::*; + use crate::support::{Float, Hex}; + + macro_rules! cases { + ($f:ty) => { + [ + // roundtrip + (0.0, 0.0), + (-0.0, -0.0), + (1.0, 1.0), + (-1.0, -1.0), + (<$f>::INFINITY, <$f>::INFINITY), + (<$f>::NEG_INFINITY, <$f>::NEG_INFINITY), + // with rounding + (0.1, 0.0), + (-0.1, -0.0), + (0.5, 1.0), + (-0.5, -1.0), + (0.9, 1.0), + (-0.9, -1.0), + (1.1, 1.0), + (-1.1, -1.0), + (1.5, 2.0), + (-1.5, -2.0), + (1.9, 2.0), + (-1.9, -2.0), + ] + }; + } + + #[track_caller] + fn check(f: fn(F) -> F, cases: &[(F, F)]) { + for &(x, exp_res) in cases { + let val = generic::round(x); + assert_biteq!(val, exp_res, "generic::round_status({x:?}) {}", Hex(x)); + let val = f(x); + assert_biteq!(val, exp_res, "round({x:?}) {}", Hex(x)); + } + } + + #[test] + #[cfg(f16_enabled)] + fn check_f16() { + check::(roundf16, &cases!(f16)); + check::( + roundf16, + &[ + (hf16!("0x1p10"), hf16!("0x1p10")), + (hf16!("-0x1p10"), hf16!("-0x1p10")), + ], + ); + } + + #[test] + fn check_f32() { + check::(roundf, &cases!(f32)); + check::( + roundf, + &[ + (hf32!("0x1p23"), hf32!("0x1p23")), + (hf32!("-0x1p23"), hf32!("-0x1p23")), + ], + ); + } + + #[test] + fn check_f64() { + check::(round, &cases!(f64)); + check::( + round, + &[ + (hf64!("0x1p52"), hf64!("0x1p52")), + (hf64!("-0x1p52"), hf64!("-0x1p52")), + ], + ); + } + + #[test] + #[cfg(f128_enabled)] + fn check_f128() { + check::(roundf128, &cases!(f128)); + check::( + roundf128, + &[ + (hf128!("0x1p112"), hf128!("0x1p112")), + (hf128!("-0x1p112"), hf128!("-0x1p112")), + ], + ); + } } diff --git a/library/compiler-builtins/libm/src/math/roundeven.rs b/library/compiler-builtins/libm/src/math/roundeven.rs index f0d67d41076ec..4cedd0c16b82d 100644 --- a/library/compiler-builtins/libm/src/math/roundeven.rs +++ b/library/compiler-builtins/libm/src/math/roundeven.rs @@ -1,25 +1,28 @@ -use super::support::{Float, Round}; +//! Note that we can use `rint` for these implementations since Rust expects the rounding +//! mode is always ties-to-even. `roundeven` also does not raise `FE_INEXACT`. +//! +//! Tested in the `rint` module. /// Round `x` to the nearest integer, breaking ties toward even. This is IEEE 754 /// `roundToIntegralTiesToEven`. #[cfg(f16_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn roundevenf16(x: f16) -> f16 { - roundeven_impl(x) + super::rintf16(x) } /// Round `x` to the nearest integer, breaking ties toward even. This is IEEE 754 /// `roundToIntegralTiesToEven`. #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn roundevenf(x: f32) -> f32 { - roundeven_impl(x) + super::rintf(x) } /// Round `x` to the nearest integer, breaking ties toward even. This is IEEE 754 /// `roundToIntegralTiesToEven`. #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn roundeven(x: f64) -> f64 { - roundeven_impl(x) + super::rint(x) } /// Round `x` to the nearest integer, breaking ties toward even. This is IEEE 754 @@ -27,10 +30,5 @@ pub fn roundeven(x: f64) -> f64 { #[cfg(f128_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn roundevenf128(x: f128) -> f128 { - roundeven_impl(x) -} - -#[inline] -pub fn roundeven_impl(x: F) -> F { - super::generic::rint_round(x, Round::Nearest).val + super::rintf128(x) } diff --git a/library/compiler-builtins/libm/src/math/sin.rs b/library/compiler-builtins/libm/src/math/sin.rs index 5378a7bc3874a..ded0df85ad237 100644 --- a/library/compiler-builtins/libm/src/math/sin.rs +++ b/library/compiler-builtins/libm/src/math/sin.rs @@ -86,9 +86,9 @@ mod tests { use super::*; #[test] - #[cfg_attr(x86_no_sse, ignore = "FIXME(i586): possible incorrect rounding")] + #[cfg_attr(x86_no_sse2, ignore = "FIXME(i586): possible incorrect rounding")] fn test_near_pi() { - let x = f64::from_bits(0x400921fb000FD5DD); // 3.141592026217707 + let x = f64::from_bits(0x400921fb000fd5dd); // 3.141592026217707 let sx = f64::from_bits(0x3ea50d15ced1a4a2); // 6.273720864039205e-7 assert_eq!(sin(x), sx); } diff --git a/library/compiler-builtins/libm/src/math/sincosf.rs b/library/compiler-builtins/libm/src/math/sincosf.rs index c4beb5267f280..1d15abe543067 100644 --- a/library/compiler-builtins/libm/src/math/sincosf.rs +++ b/library/compiler-builtins/libm/src/math/sincosf.rs @@ -122,8 +122,6 @@ pub fn sincosf(x: f32) -> (f32, f32) { } } -// PowerPC tests are failing on LLVM 13: https://github.com/rust-lang/rust/issues/88520 -#[cfg(not(target_arch = "powerpc64"))] #[cfg(test)] mod tests { use super::sincosf; diff --git a/library/compiler-builtins/libm/src/math/sqrt.rs b/library/compiler-builtins/libm/src/math/sqrt.rs index 7ba1bc9b32b23..a8e2a387661cf 100644 --- a/library/compiler-builtins/libm/src/math/sqrt.rs +++ b/library/compiler-builtins/libm/src/math/sqrt.rs @@ -1,3 +1,6 @@ +use super::generic; +use crate::support::Round; + /// The square root of `x` (f16). #[cfg(f16_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] @@ -8,7 +11,7 @@ pub fn sqrtf16(x: f16) -> f16 { args: x, } - return super::generic::sqrt(x); + return generic::sqrt_round(x, Round::Nearest).val; } /// The square root of `x` (f32). @@ -19,12 +22,13 @@ pub fn sqrtf(x: f32) -> f32 { use_arch: any( all(target_arch = "aarch64", target_feature = "neon"), all(target_arch = "wasm32", intrinsics_enabled), + all(any(target_arch = "loongarch32", target_arch = "loongarch64"), target_feature = "f"), target_feature = "sse2" ), args: x, } - super::generic::sqrt(x) + generic::sqrt_round(x, Round::Nearest).val } /// The square root of `x` (f64). @@ -35,17 +39,193 @@ pub fn sqrt(x: f64) -> f64 { use_arch: any( all(target_arch = "aarch64", target_feature = "neon"), all(target_arch = "wasm32", intrinsics_enabled), + all(any(target_arch = "loongarch32", target_arch = "loongarch64"), target_feature = "d"), target_feature = "sse2" ), args: x, } - super::generic::sqrt(x) + generic::sqrt_round(x, Round::Nearest).val } /// The square root of `x` (f128). #[cfg(f128_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn sqrtf128(x: f128) -> f128 { - return super::generic::sqrt(x); + return generic::sqrt_round(x, Round::Nearest).val; +} + +#[cfg(test)] +mod tests { + use generic::SqrtHelper; + + use super::*; + use crate::support::{CastInto, Float, FpResult, HInt, Status}; + + /// Test behavior specified in IEEE 754 `squareRoot`. + fn spec_test() + where + F: Float + SqrtHelper, + F::Int: HInt, + F::Int: From, + F::Int: From, + F::Int: CastInto, + F::Int: CastInto, + u32: CastInto, + { + // Values that should return a NaN and raise invalid + let nan = [F::NEG_INFINITY, F::NEG_ONE, F::NAN, F::MIN]; + + // Values that return unaltered + let roundtrip = [F::ZERO, F::NEG_ZERO, F::INFINITY]; + + for x in nan { + let FpResult { val, status } = generic::sqrt_round(x, Round::Nearest); + assert!(val.is_nan()); + assert!(status == Status::INVALID); + } + + for x in roundtrip { + let FpResult { val, status } = generic::sqrt_round(x, Round::Nearest); + assert_biteq!(val, x); + assert!(status == Status::OK); + } + } + + #[test] + #[cfg(f16_enabled)] + fn sanity_check_f16() { + assert_biteq!(sqrtf16(100.0f16), 10.0); + assert_biteq!(sqrtf16(4.0f16), 2.0); + } + + #[test] + #[cfg(f16_enabled)] + fn spec_tests_f16() { + spec_test::(); + } + + #[test] + #[cfg(f16_enabled)] + #[allow(clippy::approx_constant)] + fn conformance_tests_f16() { + let cases = [ + (f16::PI, 0x3f17_u16), + (10000.0_f16, 0x5640_u16), + (f16::from_bits(0x0000000f), 0x13bf_u16), + (f16::INFINITY, f16::INFINITY.to_bits()), + ]; + + for (input, output) in cases { + assert_biteq!( + sqrtf16(input), + f16::from_bits(output), + "input: {input:?} ({:#018x})", + input.to_bits() + ); + } + } + + #[test] + fn sanity_check_f32() { + assert_biteq!(sqrtf(100.0f32), 10.0); + assert_biteq!(sqrtf(4.0f32), 2.0); + } + + #[test] + fn spec_tests_f32() { + spec_test::(); + } + + #[test] + #[allow(clippy::approx_constant)] + fn conformance_tests_f32() { + let cases = [ + (f32::PI, 0x3fe2dfc5_u32), + (10000.0f32, 0x42c80000_u32), + (f32::from_bits(0x0000000f), 0x1b2f456f_u32), + (f32::INFINITY, f32::INFINITY.to_bits()), + ]; + + for (input, output) in cases { + assert_biteq!( + sqrtf(input), + f32::from_bits(output), + "input: {input:?} ({:#018x})", + input.to_bits() + ); + } + } + + #[test] + fn sanity_check_f64() { + assert_biteq!(sqrt(100.0f64), 10.0); + assert_biteq!(sqrt(4.0f64), 2.0); + } + + #[test] + fn spec_tests_f64() { + spec_test::(); + } + + #[test] + #[allow(clippy::approx_constant)] + fn conformance_tests_f64() { + let cases = [ + (f64::PI, 0x3ffc5bf891b4ef6a_u64), + (10000.0, 0x4059000000000000_u64), + (f64::from_bits(0x0000000f), 0x1e7efbdeb14f4eda_u64), + (f64::INFINITY, f64::INFINITY.to_bits()), + ]; + + for (input, output) in cases { + assert_biteq!( + sqrt(input), + f64::from_bits(output), + "input: {input:?} ({:#018x})", + input.to_bits() + ); + } + } + + #[test] + #[cfg(f128_enabled)] + fn sanity_check_f128() { + assert_biteq!(sqrtf128(100.0f128), 10.0); + assert_biteq!(sqrtf128(4.0f128), 2.0); + } + + #[test] + #[cfg(f128_enabled)] + fn spec_tests_f128() { + spec_test::(); + } + + #[test] + #[cfg(f128_enabled)] + #[allow(clippy::approx_constant)] + fn conformance_tests_f128() { + let cases = [ + (f128::PI, 0x3fffc5bf891b4ef6aa79c3b0520d5db9_u128), + // 10_000.0, see `f16` for reasoning. + ( + f128::from_bits(0x400c3880000000000000000000000000), + 0x40059000000000000000000000000000_u128, + ), + ( + f128::from_bits(0x0000000f), + 0x1fc9efbdeb14f4ed9b17ae807907e1e9_u128, + ), + (f128::INFINITY, f128::INFINITY.to_bits()), + ]; + + for (input, output) in cases { + assert_biteq!( + sqrtf128(input), + f128::from_bits(output), + "input: {input:?} ({:#018x})", + input.to_bits() + ); + } + } } diff --git a/library/compiler-builtins/libm/src/math/support/big.rs b/library/compiler-builtins/libm/src/math/support/big.rs index b7f1285424956..9b8728c987cfd 100644 --- a/library/compiler-builtins/libm/src/math/support/big.rs +++ b/library/compiler-builtins/libm/src/math/support/big.rs @@ -3,7 +3,7 @@ #[cfg(test)] mod tests; -use core::ops; +use core::{fmt, ops}; use super::{DInt, HInt, Int, MinInt}; @@ -11,18 +11,18 @@ const U128_LO_MASK: u128 = u64::MAX as u128; /// A 256-bit unsigned integer represented as two 128-bit native-endian limbs. #[allow(non_camel_case_types)] -#[derive(Clone, Copy, Debug, PartialEq, PartialOrd, Eq, Ord)] +#[derive(Clone, Copy, PartialEq, PartialOrd, Eq, Ord)] pub struct u256 { pub hi: u128, pub lo: u128, } impl u256 { - #[cfg(any(test, feature = "unstable-public-internals"))] pub const MAX: Self = Self { lo: u128::MAX, hi: u128::MAX, }; + pub const MIN: Self = Self { lo: 0, hi: 0 }; /// Reinterpret as a signed integer pub fn signed(self) -> i256 { @@ -35,15 +35,23 @@ impl u256 { /// A 256-bit signed integer represented as two 128-bit native-endian limbs. #[allow(non_camel_case_types)] -#[derive(Clone, Copy, Debug, PartialEq, PartialOrd, Eq, Ord)] +#[derive(Clone, Copy, PartialEq, PartialOrd, Eq, Ord)] pub struct i256 { pub hi: i128, pub lo: u128, } impl i256 { + pub const MAX: Self = Self { + lo: u128::MAX, + hi: i128::MAX, + }; + pub const MIN: Self = Self { + lo: u128::MIN, + hi: i128::MIN, + }; + /// Reinterpret as an unsigned integer - #[cfg(any(test, feature = "unstable-public-internals"))] pub fn unsigned(self) -> u256 { u256 { lo: self.lo, @@ -61,11 +69,8 @@ impl MinInt for u256 { const BITS: u32 = 256; const ZERO: Self = Self { lo: 0, hi: 0 }; const ONE: Self = Self { lo: 1, hi: 0 }; - const MIN: Self = Self { lo: 0, hi: 0 }; - const MAX: Self = Self { - lo: u128::MAX, - hi: u128::MAX, - }; + const MIN: Self = Self::MIN; + const MAX: Self = Self::MAX; } impl MinInt for i256 { @@ -77,14 +82,8 @@ impl MinInt for i256 { const BITS: u32 = 256; const ZERO: Self = Self { lo: 0, hi: 0 }; const ONE: Self = Self { lo: 1, hi: 0 }; - const MIN: Self = Self { - lo: u128::MIN, - hi: i128::MIN, - }; - const MAX: Self = Self { - lo: u128::MAX, - hi: i128::MAX, - }; + const MIN: Self = Self::MIN; + const MAX: Self = Self::MAX; } macro_rules! impl_common { @@ -280,3 +279,36 @@ impl DInt for i256 { self.hi } } + +impl fmt::Debug for u256 { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + fmt::LowerHex::fmt(self, f) + } +} + +impl fmt::Debug for i256 { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + fmt::LowerHex::fmt(&self.unsigned(), f) + } +} + +impl fmt::LowerHex for u256 { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + cfg_select_nofmt! { + feature = "compiler-builtins" => { + let _ = f; + unimplemented!() + } + _ => { + let pfx= if f.alternate() { "0x"} else {""}; + write!(f, "{pfx}{:032x}{:032x}", self.hi, self.lo) + } + } + } +} + +impl fmt::LowerHex for i256 { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + fmt::LowerHex::fmt(&self.unsigned(), f) + } +} diff --git a/library/compiler-builtins/libm/src/math/support/big/tests.rs b/library/compiler-builtins/libm/src/math/support/big/tests.rs index 0c32f445c1368..2f0ba7ebc3182 100644 --- a/library/compiler-builtins/libm/src/math/support/big/tests.rs +++ b/library/compiler-builtins/libm/src/math/support/big/tests.rs @@ -1,17 +1,11 @@ extern crate std; -use std::string::String; -use std::{eprintln, format}; +use std::eprintln; -use super::{HInt, MinInt, i256, u256}; +use super::{DInt, HInt, MinInt, i256, u256}; use crate::support::{Int as _, NarrowingDiv}; const LOHI_SPLIT: u128 = 0xaaaaaaaaaaaaaaaaffffffffffffffff; -/// Print a `u256` as hex since we can't add format implementations -fn hexu(v: u256) -> String { - format!("0x{:032x}{:032x}", v.hi, v.lo) -} - #[test] fn widen_u128() { assert_eq!( @@ -81,11 +75,9 @@ fn widen_mul_u128() { eprintln!( "\ FAILURE ({i}): {a:#034x} * {b:#034x}\n\ - expected: {}\n\ - got: {}\ + expected: {expected:#x}\n\ + actual: {actual:#x}\ ", - hexu(expected), - hexu(actual) ); }; @@ -106,6 +98,169 @@ fn not_u256() { assert_eq!(!u256::ZERO, u256::MAX); } +#[test] +fn shl_u256() { + let only_high = [ + 1, + u16::MAX.into(), + u32::MAX.into(), + u64::MAX.into(), + u128::MAX, + ]; + let mut has_errors = false; + + let mut add_error = |a, b, expected, actual| { + has_errors = true; + eprintln!( + "\ + FAILURE: {a:#x} << {b}\n\ + expected: {expected:#x}\n\ + actual: {actual:#x}\ + ", + ); + }; + + for a in only_high { + for perturb in 0..10 { + let a = a.saturating_add(perturb); + for shift in 0..128 { + let res = u256::from_lo_hi(0, a) << shift; + let expected = u256::from_lo_hi(0, a << shift); + if res != expected { + add_error(a.widen(), shift, expected, res); + } + } + } + } + + let check = [ + ( + u256::MAX, + 1, + u256 { + lo: u128::MAX << 1, + hi: u128::MAX, + }, + ), + ( + u256::MAX, + 5, + u256 { + lo: u128::MAX << 5, + hi: u128::MAX, + }, + ), + ( + u256::MAX, + 63, + u256 { + lo: u128::MAX << 63, + hi: u128::MAX, + }, + ), + ( + u256::MAX, + 64, + u256 { + lo: (u64::MAX as u128) << 64, + hi: u128::MAX, + }, + ), + ( + u256::MAX, + 65, + u256 { + lo: (u64::MAX as u128) << 65, + hi: u128::MAX, + }, + ), + ( + u256::MAX, + 127, + u256 { + lo: 1 << 127, + hi: u128::MAX, + }, + ), + ( + u256::MAX, + 128, + u256 { + lo: 0, + hi: u128::MAX, + }, + ), + ( + u256::MAX, + 129, + u256 { + lo: 0, + hi: u128::MAX << 1, + }, + ), + ( + u256::MAX, + 191, + u256 { + lo: 0, + hi: u128::MAX << 63, + }, + ), + ( + u256::MAX, + 192, + u256 { + lo: 0, + hi: u128::MAX << 64, + }, + ), + ( + u256::MAX, + 193, + u256 { + lo: 0, + hi: u128::MAX << 65, + }, + ), + ( + u256::MAX, + 254, + u256 { + lo: 0, + hi: 0b11 << 126, + }, + ), + ( + u256::MAX, + 255, + u256 { + lo: 0, + hi: 1 << 127, + }, + ), + ( + u256 { + hi: 0, + lo: LOHI_SPLIT, + }, + 64, + u256 { + lo: 0xffffffffffffffff0000000000000000, + hi: 0xaaaaaaaaaaaaaaaa, + }, + ), + ]; + + for (input, shift, expected) in check { + let res = input << shift; + if res != expected { + add_error(input, shift, expected, res); + } + } + + assert!(!has_errors); +} + #[test] fn shr_u256() { let only_low = [ @@ -121,13 +276,10 @@ fn shr_u256() { has_errors = true; eprintln!( "\ - FAILURE: {} >> {b}\n\ - expected: {}\n\ - actual: {}\ + FAILURE: {a:#x} >> {b}\n\ + expected: {expected:#x}\n\ + actual: {actual:#x}\ ", - hexu(a), - hexu(expected), - hexu(actual), ); }; @@ -261,8 +413,6 @@ fn shr_u256() { #[test] #[should_panic] #[cfg(debug_assertions)] -// FIXME(ppc): ppc64le seems to have issues with `should_panic` tests. -#[cfg(not(all(target_arch = "powerpc64", target_endian = "little")))] fn shr_u256_overflow() { // Like regular shr, panic on overflow with debug assertions let _ = u256::MAX >> 256; @@ -271,10 +421,10 @@ fn shr_u256_overflow() { #[test] #[cfg(not(debug_assertions))] fn shr_u256_overflow() { - // No panic without debug assertions - assert_eq!(u256::MAX >> 256, u256::ZERO); - assert_eq!(u256::MAX >> 257, u256::ZERO); - assert_eq!(u256::MAX >> u32::MAX, u256::ZERO); + // Without debug assertions, the shift amount is wrapped + assert_eq!(u256::MAX >> 256, u256::MAX); + assert_eq!(u256::MAX >> 257, u256::MAX >> 1); + assert_eq!(u256::MAX >> u32::MAX, u256::ONE); } #[test] @@ -338,6 +488,7 @@ fn i256_shifts() { } } #[test] +#[cfg_attr(miri, ignore)] // This test is very slow when using Miri fn div_u256_by_u128() { for j in i8::MIN..=i8::MAX { let y: u128 = (j as i128).rotate_right(4).unsigned(); diff --git a/library/compiler-builtins/libm/src/math/support/env.rs b/library/compiler-builtins/libm/src/math/support/env.rs index 53ae32f658dbe..0f89799ed9189 100644 --- a/library/compiler-builtins/libm/src/math/support/env.rs +++ b/library/compiler-builtins/libm/src/math/support/env.rs @@ -49,10 +49,14 @@ pub enum Round { } /// IEEE 754 exception status flags. -#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[derive(Clone, Copy, PartialEq, Eq)] pub struct Status(u8); impl Status { + /* Note that if we ever store/load this to/from floating point control status registers, it + * may be worth making these values platform-dependent to line up with register layout + * to avoid bit swapping. For the time being, this isn't a concern. */ + /// Default status indicating no errors. pub const OK: Self = Self(0); @@ -74,7 +78,7 @@ impl Status { /// result is -inf. /// `x / y` when `x != 0.0` and `y == 0.0`, #[cfg_attr(not(feature = "unstable-public-internals"), allow(dead_code))] - pub const DIVIDE_BY_ZERO: Self = Self(1 << 2); + pub const DIVIDE_BY_ZERO: Self = Self(1 << 1); /// The result exceeds the maximum finite value. /// @@ -82,14 +86,14 @@ impl Status { /// on the intermediate result. `Zero` rounds to the signed maximum finite. `Positive` and /// `Negative` round to signed maximum finite in one direction, signed infinity in the other. #[cfg_attr(not(feature = "unstable-public-internals"), allow(dead_code))] - pub const OVERFLOW: Self = Self(1 << 3); + pub const OVERFLOW: Self = Self(1 << 2); /// The result is subnormal and lost precision. - pub const UNDERFLOW: Self = Self(1 << 4); + pub const UNDERFLOW: Self = Self(1 << 3); /// The finite-precision result does not match that of infinite precision, and the reason /// is not represented by one of the other flags. - pub const INEXACT: Self = Self(1 << 5); + pub const INEXACT: Self = Self(1 << 4); /// True if `UNDERFLOW` is set. #[cfg_attr(not(feature = "unstable-public-internals"), allow(dead_code))] @@ -128,3 +132,38 @@ impl Status { Self(self.0 | rhs.0) } } + +#[cfg(any(test, feature = "unstable-public-internals"))] +impl core::fmt::Debug for Status { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + // shift -> flag map + let names = &[ + "INVALID", + "DIVIDE_BY_ZERO", + "OVERFLOW", + "UNDERFLOW", + "INEXACT", + ]; + + write!(f, "Status(")?; + let mut any = false; + for shift in 0..u8::BITS { + if self.0 & (1 << shift) != 0 { + if any { + write!(f, " | ")?; + } + match names.get(shift as usize) { + Some(name) => write!(f, "{name}")?, + None => write!(f, "UNKNOWN(1 << {shift})")?, + } + any = true; + } + } + + if !any { + write!(f, "OK")?; + } + write!(f, ")")?; + Ok(()) + } +} diff --git a/library/compiler-builtins/libm/src/math/support/float_traits.rs b/library/compiler-builtins/libm/src/math/support/float_traits.rs index 4e5011f62e0f6..f802f4be6c2d7 100644 --- a/library/compiler-builtins/libm/src/math/support/float_traits.rs +++ b/library/compiler-builtins/libm/src/math/support/float_traits.rs @@ -1,8 +1,17 @@ -#![allow(unknown_lints)] // FIXME(msrv) we shouldn't need this - use core::{fmt, mem, ops}; use super::int_traits::{CastFrom, Int, MinInt}; +use crate::support::{DInt, DisplayHex}; + +/// Wrapper to extract the integer type half of the float's size +#[allow(unused)] // only used in c-b +pub type HalfRep = <::Int as DInt>::H; + +/// Whether MIPS sNaN/qNaNs should be used. +/// +/// Note that MIPS is doing some general migration here, though this is only available on (rare) +/// modern MIPS hardware per discussion at . +const MIPS_NAN: bool = cfg!(target_arch = "mips") || cfg!(target_arch = "mips64"); /// Trait for some basic operations on floats // #[allow(dead_code)] @@ -10,6 +19,7 @@ use super::int_traits::{CastFrom, Int, MinInt}; pub trait Float: Copy + fmt::Debug + + DisplayHex + PartialEq + PartialOrd + ops::AddAssign @@ -36,24 +46,31 @@ pub trait Float: const NEG_ONE: Self; const INFINITY: Self; const NEG_INFINITY: Self; - const NAN: Self; - const NEG_NAN: Self; const MAX: Self; const MIN: Self; + + /// Quiet NaN. + const NAN: Self; + /// Signaling NaN. + const SNAN: Self; + const NEG_NAN: Self; + const NEG_SNAN: Self; + const EPSILON: Self; const PI: Self; const NEG_PI: Self; const FRAC_PI_2: Self; const MIN_POSITIVE_NORMAL: Self; + const MIN_POSITIVE_SUBNORMAL: Self; - /// The bitwidth of the float type + /// The bitwidth of the float type. const BITS: u32; - /// The bitwidth of the significand + /// The bitwidth of the significand (does not include the implicit bit). const SIG_BITS: u32; - /// The bitwidth of the exponent + /// The bitwidth of the exponent. const EXP_BITS: u32 = Self::BITS - Self::SIG_BITS - 1; /// The saturated (maximum bitpattern) value of the exponent, i.e. the infinite @@ -62,7 +79,7 @@ pub trait Float: /// This shifted fully right, use `EXP_MASK` for the shifted value. const EXP_SAT: u32 = (1 << Self::EXP_BITS) - 1; - /// The exponent bias value + /// The exponent bias value. const EXP_BIAS: u32 = Self::EXP_SAT >> 1; /// Maximum unbiased exponent value. @@ -86,6 +103,9 @@ pub trait Float: /// The implicit bit of the float format const IMPLICIT_BIT: Self::Int; + /// A mask for the top bit of the significand, useful for NaN ops. + const SIG_TOP_BIT: Self::Int; + /// Returns `self` transmuted to `Self::Int` fn to_bits(self) -> Self::Int; @@ -107,16 +127,28 @@ pub trait Float: /// This method returns `true` if two NaNs are compared. Use [`biteq`](Self::biteq) instead /// if `NaN` should not be treated separately. #[allow(dead_code)] - fn eq_repr(self, rhs: Self) -> bool { - if self.is_nan() && rhs.is_nan() { - true + fn eq_repr(self, rhs: Self) -> bool; + + /// Returns true if the value is NaN. + fn is_nan(self) -> bool; + + fn is_qnan(self) -> bool { + if !self.is_nan() { + return false; + } + + let top = self.to_bits() & Self::SIG_TOP_BIT; + + if MIPS_NAN { + top == Self::Int::ZERO } else { - self.biteq(rhs) + top != Self::Int::ZERO } } - /// Returns true if the value is NaN. - fn is_nan(self) -> bool; + fn is_snan(self) -> bool { + self.is_nan() && !self.is_qnan() + } /// Returns true if the value is +inf or -inf. fn is_infinite(self) -> bool; @@ -178,7 +210,6 @@ pub trait Float: fn fma(self, y: Self, z: Self) -> Self; /// Returns (normalized exponent, normalized significand) - #[allow(dead_code)] fn normalize(significand: Self::Int) -> (i32, Self::Int); /// Returns a number that represents the sign of self. @@ -226,18 +257,36 @@ macro_rules! float_impl { const NEG_ONE: Self = -1.0; const INFINITY: Self = Self::INFINITY; const NEG_INFINITY: Self = Self::NEG_INFINITY; - const NAN: Self = Self::NAN; - // NAN isn't guaranteed to be positive but it usually is. We only use this for - // tests. - const NEG_NAN: Self = $from_bits($to_bits(Self::NAN) | Self::SIGN_MASK); const MAX: Self = -Self::MIN; // Sign bit set, saturated mantissa, saturated exponent with last bit zeroed const MIN: Self = $from_bits(Self::Int::MAX & !(1 << Self::SIG_BITS)); + + // The default NaN seems to set one of the top two significand bits on most + // platforms (sNaN vs. qNaN). For mips, the significand is all 1s (with the + // exception of the signaling bit). + const NAN: Self = $from_bits(if MIPS_NAN { + Self::EXP_MASK | (Self::SIG_TOP_BIT - 1) + } else { + Self::EXP_MASK | Self::SIG_TOP_BIT + }); + const SNAN: Self = $from_bits(if MIPS_NAN { + Self::EXP_MASK | Self::SIG_MASK + } else { + Self::EXP_MASK | (Self::SIG_TOP_BIT >> 1) + }); + // NAN isn't guaranteed to be positive but it usually is. We only use these for + // tests. + const NEG_NAN: Self = $from_bits($to_bits(Self::NAN) | Self::SIGN_MASK); + const NEG_SNAN: Self = $from_bits($to_bits(Self::SNAN) | Self::SIGN_MASK); + const EPSILON: Self = <$ty>::EPSILON; // Exponent is a 1 in the LSB const MIN_POSITIVE_NORMAL: Self = $from_bits(1 << Self::SIG_BITS); + // Single 1 in the LSB + const MIN_POSITIVE_SUBNORMAL: Self = $from_bits(1); + const PI: Self = core::$ty::consts::PI; const NEG_PI: Self = -Self::PI; const FRAC_PI_2: Self = core::$ty::consts::FRAC_PI_2; @@ -249,10 +298,32 @@ macro_rules! float_impl { const SIG_MASK: Self::Int = (1 << Self::SIG_BITS) - 1; const EXP_MASK: Self::Int = !(Self::SIGN_MASK | Self::SIG_MASK); const IMPLICIT_BIT: Self::Int = 1 << Self::SIG_BITS; + const SIG_TOP_BIT: Self::Int = Self::IMPLICIT_BIT >> 1; fn to_bits(self) -> Self::Int { self.to_bits() } + + fn eq_repr(self, rhs: Self) -> bool { + #[cfg(not(feature = "unmangled-names"))] + fn is_nan(x: $ty) -> bool { + // When not using unmangled-names, the "real" compiler-builtins might not have + // the necessary builtin (__unordtf2) to test whether `f128` is NaN. + // FIXME(f128): Remove once the nightly toolchain has the __unordtf2 builtin + // x is NaN if all the bits of the exponent are set and the significand is non-0 + x.to_bits() & $ty::EXP_MASK == $ty::EXP_MASK && x.to_bits() & $ty::SIG_MASK != 0 + } + #[cfg(feature = "unmangled-names")] + fn is_nan(x: $ty) -> bool { + x.is_nan() + } + if is_nan(self) && is_nan(rhs) { + true + } else { + self.to_bits() == rhs.to_bits() + } + } + fn is_nan(self) -> bool { self.is_nan() } @@ -266,44 +337,41 @@ macro_rules! float_impl { Self::from_bits(a) } fn abs(self) -> Self { - cfg_if! { + cfg_select_nofmt! { // FIXME(msrv): `abs` is available in `core` starting with 1.85. - if #[cfg(intrinsics_enabled)] { + intrinsics_enabled => { self.abs() - } else { + } + _ => { super::super::generic::fabs(self) } } } fn copysign(self, other: Self) -> Self { - cfg_if! { + cfg_select_nofmt! { // FIXME(msrv): `copysign` is available in `core` starting with 1.85. - if #[cfg(intrinsics_enabled)] { + intrinsics_enabled => { self.copysign(other) - } else { + } + _ => { super::super::generic::copysign(self, other) } } } fn fma(self, y: Self, z: Self) -> Self { - cfg_if! { + cfg_select_nofmt! { // fma is not yet available in `core` - if #[cfg(intrinsics_enabled)] { - // FIXME(msrv,bench): once our benchmark rustc version is above the - // 2022-09-23 nightly, this can be removed. - #[allow(unused_unsafe)] - unsafe { core::intrinsics::$fma_intrinsic(self, y, z) } - } else { + intrinsics_enabled => { + core::intrinsics::$fma_intrinsic(self, y, z) + } + _ => { super::super::$fma_fn(self, y, z) } } } fn normalize(significand: Self::Int) -> (i32, Self::Int) { let shift = significand.leading_zeros().wrapping_sub(Self::EXP_BITS); - ( - 1i32.wrapping_sub(shift as i32), - significand << shift as Self::Int, - ) + (1i32.wrapping_sub(shift as i32), significand << shift) } } }; @@ -388,28 +456,28 @@ pub const fn f64_to_bits(x: f64) -> u64 { unsafe { mem::transmute::(x) } } -/// Trait for floats twice the bit width of another integer. -pub trait DFloat: Float { +/// Trait for floats that are wider than a `NFloat` type. +pub trait WideFloat: Float { /// Float that is half the bit width of the floatthis trait is implemented for. - type H: HFloat; + type H: NarrowFloat; /// Narrow the float type. fn narrow(self) -> Self::H; } -/// Trait for floats half the bit width of another float. -pub trait HFloat: Float { +/// Trait for floats narrower than a `WFloat` type. +pub trait NarrowFloat: Float { /// Float that is double the bit width of the float this trait is implemented for. - type D: DFloat; + type D: WideFloat; /// Widen the float type. fn widen(self) -> Self::D; } -macro_rules! impl_d_float { +macro_rules! impl_wide_float { ($($X:ident $D:ident),*) => { $( - impl DFloat for $D { + impl WideFloat for $D { type H = $X; fn narrow(self) -> Self::H { @@ -420,10 +488,10 @@ macro_rules! impl_d_float { }; } -macro_rules! impl_h_float { +macro_rules! impl_narrow_float { ($($H:ident $X:ident),*) => { $( - impl HFloat for $H { + impl NarrowFloat for $H { type D = $X; fn widen(self) -> Self::D { @@ -434,17 +502,17 @@ macro_rules! impl_h_float { }; } -impl_d_float!(f32 f64); +impl_wide_float!(f32 f64); #[cfg(f16_enabled)] -impl_d_float!(f16 f32); +impl_wide_float!(f16 f32); #[cfg(f128_enabled)] -impl_d_float!(f64 f128); +impl_wide_float!(f64 f128); -impl_h_float!(f32 f64); +impl_narrow_float!(f32 f64); #[cfg(f16_enabled)] -impl_h_float!(f16 f32); +impl_narrow_float!(f16 f32); #[cfg(f128_enabled)] -impl_h_float!(f64 f128); +impl_narrow_float!(f64 f128); #[cfg(test)] mod tests { @@ -459,6 +527,17 @@ mod tests { assert_eq!(f16::EXP_MAX, 15); assert_eq!(f16::EXP_MIN, -14); assert_eq!(f16::EXP_MIN_SUBNORM, -24); + assert_biteq!(f16::NAN, ::NAN); + // Value of NAN and FLT16_SNAN in C. We don't strictly need to match up, but it is good to + // be aware if there are platforms where we don't. + if MIPS_NAN { + assert_biteq!(f16::NAN, f16::from_bits(0x7fbf)); + assert_biteq!(f16::SNAN, f16::from_bits(0x7fff)); + } else { + assert_biteq!(f16::NAN, f16::from_bits(0x7e00)); + assert_biteq!(f16::SNAN, f16::from_bits(0x7d00)); + } + assert!(f16::NAN.is_qnan()); // `exp_unbiased` assert_eq!(f16::FRAC_PI_2.exp_unbiased(), 0); @@ -485,6 +564,21 @@ mod tests { assert_eq!(f32::EXP_MAX, 127); assert_eq!(f32::EXP_MIN, -126); assert_eq!(f32::EXP_MIN_SUBNORM, -149); + assert_biteq!(f32::NAN, ::NAN); + // Value of NAN and FLT_SNAN in C. We don't strictly need to match up, but it is good to + // be aware if there are platforms where we don't. + if MIPS_NAN { + assert_biteq!(f32::NAN, f32::from_bits(0x7fbfffff)); + assert_biteq!(f32::SNAN, f32::from_bits(0x7fffffff)); + } else { + assert_biteq!(f32::NAN, f32::from_bits(0x7fc00000)); + assert_biteq!(f32::SNAN, f32::from_bits(0x7fa00000)); + } + assert!(f32::NAN.is_qnan()); + // FIXME(rust-lang/rust#115567): x87 use in `is_snan` quiets the sNaN + if !cfg!(x86_no_sse2) { + assert!(f32::SNAN.is_snan()); + } // `exp_unbiased` assert_eq!(f32::FRAC_PI_2.exp_unbiased(), 0); @@ -515,6 +609,21 @@ mod tests { assert_eq!(f64::EXP_MAX, 1023); assert_eq!(f64::EXP_MIN, -1022); assert_eq!(f64::EXP_MIN_SUBNORM, -1074); + assert_biteq!(f64::NAN, ::NAN); + // Value of NAN and DBL_SNAN in C. We don't strictly need to match up, but it is good to + // be aware if there are platforms where we don't. + if MIPS_NAN { + assert_biteq!(f64::NAN, f64::from_bits(0x7ff7ffffffffffff)); + assert_biteq!(f64::SNAN, f64::from_bits(0x7fffffffffffffff)); + } else { + assert_biteq!(f64::NAN, f64::from_bits(0x7ff8000000000000)); + assert_biteq!(f64::SNAN, f64::from_bits(0x7ff4000000000000)); + } + assert!(f64::NAN.is_qnan()); + // FIXME(rust-lang/rust#115567): x87 use in `is_snan` quiets the sNaN + if !cfg!(x86_no_sse2) { + assert!(f64::SNAN.is_snan()); + } // `exp_unbiased` assert_eq!(f64::FRAC_PI_2.exp_unbiased(), 0); @@ -546,6 +655,30 @@ mod tests { assert_eq!(f128::EXP_MAX, 16383); assert_eq!(f128::EXP_MIN, -16382); assert_eq!(f128::EXP_MIN_SUBNORM, -16494); + assert_biteq!(f128::NAN, ::NAN); + // Value of NAN and FLT128_SNAN in C. We don't strictly need to match up, but it is good to + // be aware if there are platforms where we don't. + if MIPS_NAN { + assert_biteq!( + f128::NAN, + f128::from_bits(0x7fff7fffffffffffffffffffffffffff) + ); + assert_biteq!( + f128::SNAN, + f128::from_bits(0x7fffffffffffffffffffffffffffffff) + ); + } else { + assert_biteq!( + f128::NAN, + f128::from_bits(0x7fff8000000000000000000000000000) + ); + assert_biteq!( + f128::SNAN, + f128::from_bits(0x7fff4000000000000000000000000000) + ); + } + assert!(f128::NAN.is_qnan()); + assert!(f128::SNAN.is_snan()); // `exp_unbiased` assert_eq!(f128::FRAC_PI_2.exp_unbiased(), 0); diff --git a/library/compiler-builtins/libm/src/math/support/hex_float.rs b/library/compiler-builtins/libm/src/math/support/hex_float.rs index c8558b90053d1..607ba7964023b 100644 --- a/library/compiler-builtins/libm/src/math/support/hex_float.rs +++ b/library/compiler-builtins/libm/src/math/support/hex_float.rs @@ -1,5 +1,7 @@ //! Utilities for working with hex float formats. +pub use hex_fmt::{DisplayHex, Hex}; + use super::{Round, Status, f32_from_bits, f64_from_bits}; /// Construct a 16-bit float from hex float representation (C-style) @@ -121,7 +123,7 @@ const fn parse_finite( Ok(Parsed { sig, exp }) => (sig, exp), }; - let mut round_bits = u128_ilog2(sig) as i32 - sig_bits as i32; + let mut round_bits = sig.ilog2() as i32 - sig_bits as i32; // Round at least up to min_lsb if exp < min_lsb - round_bits { @@ -299,29 +301,11 @@ const fn parse_hex(mut b: &[u8]) -> Result { )); }; - { - let e; - if negate_exp { - e = (exp as i64) - (pexp as i64); - } else { - e = (exp as i64) + (pexp as i64); - }; - - exp = if e < i32::MIN as i64 { - i32::MIN - } else if e > i32::MAX as i64 { - i32::MAX - } else { - e as i32 - }; - } - /* FIXME(msrv): once MSRV >= 1.66, replace the above workaround block with: if negate_exp { exp = exp.saturating_sub_unsigned(pexp); } else { exp = exp.saturating_add_unsigned(pexp); }; - */ Ok(Parsed { sig, exp }) } @@ -342,33 +326,32 @@ const fn hex_digit(c: u8) -> Option { } } -/* FIXME(msrv): vendor some things that are not const stable at our MSRV */ - -/// `u128::ilog2` -const fn u128_ilog2(v: u128) -> u32 { - assert!(v != 0); - u128::BITS - 1 - v.leading_zeros() -} - -#[cfg(any(test, feature = "unstable-public-internals"))] mod hex_fmt { use core::fmt; - use crate::support::Float; - - /// Format a floating point number as its IEEE hex (`%a`) representation. - pub struct Hexf(pub F); + use crate::support::{Float, div_ceil_u32}; // Adapted from https://github.com/ericseppanen/hexfloat2/blob/a5c27932f0ff/src/format.rs - #[cfg(not(feature = "compiler-builtins"))] pub(super) fn fmt_any_hex(x: &F, f: &mut fmt::Formatter<'_>) -> fmt::Result { if x.is_sign_negative() { write!(f, "-")?; + } else { + write!(f, "+")?; } if x.is_nan() { - return write!(f, "NaN"); - } else if x.is_infinite() { + if x.is_snan() { + write!(f, "sNaN")?; + } else if x.is_nan() { + write!(f, "qNaN")?; + } + let payload = x.frac() & !F::SIG_TOP_BIT; + let width = div_ceil_u32(F::SIG_BITS, 4) as usize + 2; + write!(f, "({payload:#0width$x})")?; + return Ok(()); + } + + if x.is_infinite() { return write!(f, "inf"); } else if *x == F::ZERO { return write!(f, "0x0p+0"); @@ -394,102 +377,137 @@ mod hex_fmt { write!(f, "0x{leading}{sig:0mwidth$x}p{exponent:+}") } - #[cfg(feature = "compiler-builtins")] - pub(super) fn fmt_any_hex(_x: &F, _f: &mut fmt::Formatter<'_>) -> fmt::Result { - unimplemented!() + /// Types that can be formatted as hex via `Hex`. For ints we always print with a fixed + /// number of leading zeros. For floats we use the IEEE hex (`%a`) representation. The `-` + /// format modifier is used to print the integer hex representation rather than hex float. + pub trait DisplayHex { + #[allow(unused)] // Only used for tests and public test internals + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result; } - impl fmt::LowerHex for Hexf { + /// A wrapper implementing formatting traits via `DisplayHex`. + #[allow(unused)] // Only used for tests and public test internals + pub struct Hex(pub T); + + impl fmt::Debug for Hex { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - cfg_if! { - if #[cfg(feature = "compiler-builtins")] { - let _ = f; - unimplemented!() - } else { - fmt_any_hex(&self.0, f) - } - } + self.0.fmt(f) } } - impl fmt::LowerHex for Hexf<(F, F)> { + impl fmt::Display for Hex { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - cfg_if! { - if #[cfg(feature = "compiler-builtins")] { - let _ = f; - unimplemented!() - } else { - write!(f, "({:x}, {:x})", Hexf(self.0.0), Hexf(self.0.1)) - } - } + self.0.fmt(f) } } - impl fmt::LowerHex for Hexf<(F, i32)> { + impl fmt::LowerHex for Hex { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - cfg_if! { - if #[cfg(feature = "compiler-builtins")] { - let _ = f; - unimplemented!() - } else { - write!(f, "({:x}, {:x})", Hexf(self.0.0), Hexf(self.0.1)) - } + self.0.fmt(f) + } + } + + impl DisplayHex for F { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + if f.sign_minus() { + self.to_bits().fmt(f) + } else { + fmt_any_hex(self, f) } } } - impl fmt::LowerHex for Hexf { + macro_rules! impl_int { + ($ity:ty) => { + impl DisplayHex for $ity { + #[inline] + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + write!( + f, + "{self:#0width$x}", + width = ((<$ity>::BITS / 4) + 2) as usize, + ) + } + } + }; + } + + impl_int!(i8); + impl_int!(i16); + impl_int!(i32); + impl_int!(i64); + impl_int!(i128); + impl_int!(isize); + impl_int!(u8); + impl_int!(u16); + impl_int!(u32); + impl_int!(u64); + impl_int!(u128); + impl_int!(usize); + + // Not really a meaningful impl, but makes some generics easier. + impl DisplayHex for bool { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - cfg_if! { - if #[cfg(feature = "compiler-builtins")] { + cfg_select_nofmt! { + feature = "compiler-builtins" => { let _ = f; unimplemented!() - } else { - fmt::LowerHex::fmt(&self.0, f) + } + _ => { + write!(f, "{self}") } } } } - impl fmt::Debug for Hexf + impl DisplayHex for (T1,) where - Hexf: fmt::LowerHex, + T1: Copy + DisplayHex, { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - cfg_if! { - if #[cfg(feature = "compiler-builtins")] { - let _ = f; - unimplemented!() - } else { - fmt::LowerHex::fmt(self, f) - } - } + write!(f, "(")?; + self.0.fmt(f)?; + write!(f, ",)") } } - impl fmt::Display for Hexf + impl DisplayHex for (T1, T2) where - Hexf: fmt::LowerHex, + T1: Copy + DisplayHex, + T2: Copy + DisplayHex, { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - cfg_if! { - if #[cfg(feature = "compiler-builtins")] { - let _ = f; - unimplemented!() - } else { - fmt::LowerHex::fmt(self, f) - } - } + write!(f, "(")?; + self.0.fmt(f)?; + write!(f, ", ")?; + self.1.fmt(f)?; + write!(f, ")") } } -} -#[cfg(any(test, feature = "unstable-public-internals"))] -pub use hex_fmt::*; + impl DisplayHex for (T1, T2, T3) + where + T1: Copy + DisplayHex, + T2: Copy + DisplayHex, + T3: Copy + DisplayHex, + { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + write!(f, "(")?; + self.0.fmt(f)?; + write!(f, ", ")?; + self.1.fmt(f)?; + write!(f, ", ")?; + self.2.fmt(f)?; + write!(f, ")") + } + } +} #[cfg(test)] mod parse_tests { extern crate std; + + use std::string::{String, ToString}; use std::{format, println}; use super::*; @@ -538,18 +556,37 @@ mod parse_tests { } Ok(()) } + + /// Strip the qNaN/sNaN and payload since we don't parse that. + #[cfg_attr(not(f16_enabled), expect(unused))] + pub fn canonicalize_snan_str(mut s: String) -> String { + if s.contains("sNaN") || s.contains("qNaN") { + s = s.replace("sNaN", "NaN").replace("qNaN", "NaN"); + if let Some((nan, payload)) = s.split_once("(") { + assert!(payload.ends_with(")")); + s = nan.to_string(); + } + } + s + } + #[test] #[cfg(f16_enabled)] fn test_rounding() { let n = 1_i32 << 14; for i in -n..n { let u = i.rotate_right(11) as u32; - let s = format!("{}", Hexf(f32::from_bits(u))); - assert!(rounding_properties(&s).is_ok()); + let s = format!("{}", Hex(f32::from_bits(u))); + let s = canonicalize_snan_str(s); + match rounding_properties(&s) { + Ok(()) => (), + Err(e) => panic!("failed rounding properties for `{s}`: {e:?}"), + } } } #[test] + #[cfg_attr(miri, ignore)] // This test is very slow when using Miri fn test_parse_any() { for k in -149..=127 { let s = format!("0x1p{k}"); @@ -615,7 +652,7 @@ mod parse_tests { #[cfg(f128_enabled)] fn rounding() { let pi = std::f128::consts::PI; - let s = format!("{}", Hexf(pi)); + let s = format!("{}", Hex(pi)); for k in 0..=111 { let (bits, status) = parse_any(&s, 128 - k, 112 - k, Round::Nearest).unwrap(); @@ -641,6 +678,7 @@ mod parse_tests { } } #[test] + #[cfg_attr(miri, ignore)] // This test is very slow when using Miri fn long_tail() { for k in 1..1000 { let s = format!("0x1.{}p0", "0".repeat(k)); @@ -872,68 +910,63 @@ mod parse_tests { } #[cfg(test)] -// FIXME(ppc): something with `should_panic` tests cause a SIGILL with ppc64le -#[cfg(not(all(target_arch = "powerpc64", target_endian = "little")))] mod tests_panicking { extern crate std; use super::*; - // HACK(msrv): 1.63 rejects unknown width float literals at an AST level, so use a macro to - // hide them from the AST. + #[test] #[cfg(f16_enabled)] - macro_rules! f16_tests { - () => { - #[test] - fn test_f16_almost_extra_precision() { - // Exact maximum precision allowed - hf16("0x1.ffcp+0"); - } - - #[test] - #[should_panic(expected = "the value is too precise")] - fn test_f16_extra_precision() { - // One bit more than the above. - hf16("0x1.ffdp+0"); - } + fn test_f16_almost_extra_precision() { + // Exact maximum precision allowed + hf16("0x1.ffcp+0"); + } - #[test] - #[should_panic(expected = "the value is too huge")] - fn test_f16_overflow() { - // One bit more than the above. - hf16("0x1p+16"); - } + #[test] + #[cfg(f16_enabled)] + #[should_panic(expected = "the value is too precise")] + fn test_f16_extra_precision() { + // One bit more than the above. + hf16("0x1.ffdp+0"); + } - #[test] - fn test_f16_tiniest() { - let x = hf16("0x1.p-24"); - let y = hf16("0x0.001p-12"); - let z = hf16("0x0.8p-23"); - assert_eq!(x, y); - assert_eq!(x, z); - } + #[test] + #[cfg(f16_enabled)] + #[should_panic(expected = "the value is too huge")] + fn test_f16_overflow() { + // One bit more than the above. + hf16("0x1p+16"); + } - #[test] - #[should_panic(expected = "the value is too tiny")] - fn test_f16_too_tiny() { - hf16("0x1.p-25"); - } + #[test] + #[cfg(f16_enabled)] + fn test_f16_tiniest() { + let x = hf16("0x1.p-24"); + let y = hf16("0x0.001p-12"); + let z = hf16("0x0.8p-23"); + assert_eq!(x, y); + assert_eq!(x, z); + } - #[test] - #[should_panic(expected = "the value is too tiny")] - fn test_f16_also_too_tiny() { - hf16("0x0.8p-24"); - } + #[test] + #[cfg(f16_enabled)] + #[should_panic(expected = "the value is too tiny")] + fn test_f16_too_tiny() { + hf16("0x1.p-25"); + } - #[test] - #[should_panic(expected = "the value is too tiny")] - fn test_f16_again_too_tiny() { - hf16("0x0.001p-13"); - } - }; + #[test] + #[cfg(f16_enabled)] + #[should_panic(expected = "the value is too tiny")] + fn test_f16_also_too_tiny() { + hf16("0x0.8p-24"); } + #[test] #[cfg(f16_enabled)] - f16_tests!(); + #[should_panic(expected = "the value is too tiny")] + fn test_f16_again_too_tiny() { + hf16("0x0.001p-13"); + } #[test] fn test_f32_almost_extra_precision() { @@ -1002,68 +1035,66 @@ mod tests_panicking { hf64("0x1.abcdabcdabcdf8p+0"); } - // HACK(msrv): 1.63 rejects unknown width float literals at an AST level, so use a macro to - // hide them from the AST. + #[test] #[cfg(f128_enabled)] - macro_rules! f128_tests { - () => { - #[test] - fn test_f128_almost_extra_precision() { - // Exact maximum precision allowed - hf128("0x1.ffffffffffffffffffffffffffffp+16383"); - } - - #[test] - #[should_panic(expected = "the value is too precise")] - fn test_f128_extra_precision() { - // Just below the maximum finite. - hf128("0x1.fffffffffffffffffffffffffffe8p+16383"); - } - #[test] - #[should_panic(expected = "the value is too huge")] - fn test_f128_extra_precision_overflow() { - // One bit more than the above. Should overflow. - hf128("0x1.ffffffffffffffffffffffffffff8p+16383"); - } + fn test_f128_almost_extra_precision() { + // Exact maximum precision allowed + hf128("0x1.ffffffffffffffffffffffffffffp+16383"); + } - #[test] - #[should_panic(expected = "the value is too huge")] - fn test_f128_overflow() { - // One bit more than the above. - hf128("0x1p+16384"); - } + #[test] + #[cfg(f128_enabled)] + #[should_panic(expected = "the value is too precise")] + fn test_f128_extra_precision() { + // Just below the maximum finite. + hf128("0x1.fffffffffffffffffffffffffffe8p+16383"); + } + #[test] + #[cfg(f128_enabled)] + #[should_panic(expected = "the value is too huge")] + fn test_f128_extra_precision_overflow() { + // One bit more than the above. Should overflow. + hf128("0x1.ffffffffffffffffffffffffffff8p+16383"); + } - #[test] - fn test_f128_tiniest() { - let x = hf128("0x1.p-16494"); - let y = hf128("0x0.0000000000000001p-16430"); - let z = hf128("0x0.8p-16493"); - assert_eq!(x, y); - assert_eq!(x, z); - } + #[test] + #[cfg(f128_enabled)] + #[should_panic(expected = "the value is too huge")] + fn test_f128_overflow() { + // One bit more than the above. + hf128("0x1p+16384"); + } - #[test] - #[should_panic(expected = "the value is too tiny")] - fn test_f128_too_tiny() { - hf128("0x1.p-16495"); - } + #[test] + #[cfg(f128_enabled)] + fn test_f128_tiniest() { + let x = hf128("0x1.p-16494"); + let y = hf128("0x0.0000000000000001p-16430"); + let z = hf128("0x0.8p-16493"); + assert_eq!(x, y); + assert_eq!(x, z); + } - #[test] - #[should_panic(expected = "the value is too tiny")] - fn test_f128_again_too_tiny() { - hf128("0x0.0000000000000001p-16431"); - } + #[test] + #[cfg(f128_enabled)] + #[should_panic(expected = "the value is too tiny")] + fn test_f128_too_tiny() { + hf128("0x1.p-16495"); + } - #[test] - #[should_panic(expected = "the value is too tiny")] - fn test_f128_also_too_tiny() { - hf128("0x0.8p-16494"); - } - }; + #[test] + #[cfg(f128_enabled)] + #[should_panic(expected = "the value is too tiny")] + fn test_f128_again_too_tiny() { + hf128("0x0.0000000000000001p-16431"); } + #[test] #[cfg(f128_enabled)] - f128_tests!(); + #[should_panic(expected = "the value is too tiny")] + fn test_f128_also_too_tiny() { + hf128("0x0.8p-16494"); + } } #[cfg(test)] @@ -1080,8 +1111,11 @@ mod print_tests { use std::format; // Exhaustively check that `f16` roundtrips. for x in 0..=u16::MAX { + use super::parse_tests::canonicalize_snan_str; + let f = f16::from_bits(x); - let s = format!("{}", Hexf(f)); + let s = format!("{}", Hex(f)); + let s = canonicalize_snan_str(s); let from_s = hf16(&s); if f.is_nan() && from_s.is_nan() { @@ -1100,6 +1134,8 @@ mod print_tests { #[cfg(f16_enabled)] fn test_f16_to_f32() { use std::format; + + use super::parse_tests::canonicalize_snan_str; // Exhaustively check that these are equivalent for all `f16`: // - `f16 -> f32` // - `f16 -> str -> f32` @@ -1107,9 +1143,11 @@ mod print_tests { // - `f16 -> f32 -> str -> f16 -> f32` for x in 0..=u16::MAX { let f16 = f16::from_bits(x); - let s16 = format!("{}", Hexf(f16)); + let s16 = format!("{}", Hex(f16)); + let s16 = canonicalize_snan_str(s16); let f32 = f16 as f32; - let s32 = format!("{}", Hexf(f32)); + let s32 = format!("{}", Hex(f32)); + let s32 = canonicalize_snan_str(s32); let a = hf32(&s16); let b = hf32(&s32); @@ -1138,53 +1176,94 @@ mod print_tests { } #[test] fn spot_checks() { - assert_eq!(Hexf(f32::MAX).to_string(), "0x1.fffffep+127"); - assert_eq!(Hexf(f64::MAX).to_string(), "0x1.fffffffffffffp+1023"); - - assert_eq!(Hexf(f32::MIN).to_string(), "-0x1.fffffep+127"); - assert_eq!(Hexf(f64::MIN).to_string(), "-0x1.fffffffffffffp+1023"); - - assert_eq!(Hexf(f32::ZERO).to_string(), "0x0p+0"); - assert_eq!(Hexf(f64::ZERO).to_string(), "0x0p+0"); - - assert_eq!(Hexf(f32::NEG_ZERO).to_string(), "-0x0p+0"); - assert_eq!(Hexf(f64::NEG_ZERO).to_string(), "-0x0p+0"); - - assert_eq!(Hexf(f32::NAN).to_string(), "NaN"); - assert_eq!(Hexf(f64::NAN).to_string(), "NaN"); + assert_eq!(Hex(f32::MAX).to_string(), "+0x1.fffffep+127"); + assert_eq!(Hex(f64::MAX).to_string(), "+0x1.fffffffffffffp+1023"); + + assert_eq!(Hex(f32::MIN).to_string(), "-0x1.fffffep+127"); + assert_eq!(Hex(f64::MIN).to_string(), "-0x1.fffffffffffffp+1023"); + + assert_eq!(Hex(f32::ZERO).to_string(), "+0x0p+0"); + assert_eq!(Hex(f64::ZERO).to_string(), "+0x0p+0"); + + assert_eq!(Hex(f32::NEG_ZERO).to_string(), "-0x0p+0"); + assert_eq!(Hex(f64::NEG_ZERO).to_string(), "-0x0p+0"); + + assert_eq!(Hex(f32::NAN).to_string(), "+qNaN(0x000000)"); + assert_eq!(Hex(f64::NAN).to_string(), "+qNaN(0x0000000000000)"); + assert_eq!(Hex(f32::NEG_NAN).to_string(), "-qNaN(0x000000)"); + assert_eq!(Hex(f64::NEG_NAN).to_string(), "-qNaN(0x0000000000000)"); + if !cfg!(x86_no_sse2) { + // FIXME(rust-lang/rust#115567): calls quiet the sNaN + assert_eq!(Hex(f32::SNAN).to_string(), "+sNaN(0x200000)"); + assert_eq!(Hex(f64::SNAN).to_string(), "+sNaN(0x4000000000000)"); + assert_eq!(Hex(f32::NEG_SNAN).to_string(), "-sNaN(0x200000)"); + assert_eq!(Hex(f64::NEG_SNAN).to_string(), "-sNaN(0x4000000000000)"); + assert_eq!(Hex(f32::from_bits(u32::MAX)).to_string(), "-qNaN(0x3fffff)"); + assert_eq!( + Hex(f64::from_bits(u64::MAX)).to_string(), + "-qNaN(0x7ffffffffffff)" + ); + } - assert_eq!(Hexf(f32::INFINITY).to_string(), "inf"); - assert_eq!(Hexf(f64::INFINITY).to_string(), "inf"); + assert_eq!(Hex(f32::INFINITY).to_string(), "+inf"); + assert_eq!(Hex(f64::INFINITY).to_string(), "+inf"); - assert_eq!(Hexf(f32::NEG_INFINITY).to_string(), "-inf"); - assert_eq!(Hexf(f64::NEG_INFINITY).to_string(), "-inf"); + assert_eq!(Hex(f32::NEG_INFINITY).to_string(), "-inf"); + assert_eq!(Hex(f64::NEG_INFINITY).to_string(), "-inf"); #[cfg(f16_enabled)] { - assert_eq!(Hexf(f16::MAX).to_string(), "0x1.ffcp+15"); - assert_eq!(Hexf(f16::MIN).to_string(), "-0x1.ffcp+15"); - assert_eq!(Hexf(f16::ZERO).to_string(), "0x0p+0"); - assert_eq!(Hexf(f16::NEG_ZERO).to_string(), "-0x0p+0"); - assert_eq!(Hexf(f16::NAN).to_string(), "NaN"); - assert_eq!(Hexf(f16::INFINITY).to_string(), "inf"); - assert_eq!(Hexf(f16::NEG_INFINITY).to_string(), "-inf"); + assert_eq!(Hex(f16::MAX).to_string(), "+0x1.ffcp+15"); + assert_eq!(Hex(f16::MIN).to_string(), "-0x1.ffcp+15"); + assert_eq!(Hex(f16::ZERO).to_string(), "+0x0p+0"); + assert_eq!(Hex(f16::NEG_ZERO).to_string(), "-0x0p+0"); + + assert_eq!(Hex(f16::NAN).to_string(), "+qNaN(0x000)"); + assert_eq!(Hex(f16::SNAN).to_string(), "+sNaN(0x100)"); + assert_eq!(Hex(f16::NEG_NAN).to_string(), "-qNaN(0x000)"); + assert_eq!(Hex(f16::NEG_SNAN).to_string(), "-sNaN(0x100)"); + assert_eq!(Hex(f16::from_bits(u16::MAX)).to_string(), "-qNaN(0x1ff)"); + + assert_eq!(Hex(f16::INFINITY).to_string(), "+inf"); + assert_eq!(Hex(f16::NEG_INFINITY).to_string(), "-inf"); } #[cfg(f128_enabled)] { assert_eq!( - Hexf(f128::MAX).to_string(), - "0x1.ffffffffffffffffffffffffffffp+16383" + Hex(f128::MAX).to_string(), + "+0x1.ffffffffffffffffffffffffffffp+16383" ); assert_eq!( - Hexf(f128::MIN).to_string(), + Hex(f128::MIN).to_string(), "-0x1.ffffffffffffffffffffffffffffp+16383" ); - assert_eq!(Hexf(f128::ZERO).to_string(), "0x0p+0"); - assert_eq!(Hexf(f128::NEG_ZERO).to_string(), "-0x0p+0"); - assert_eq!(Hexf(f128::NAN).to_string(), "NaN"); - assert_eq!(Hexf(f128::INFINITY).to_string(), "inf"); - assert_eq!(Hexf(f128::NEG_INFINITY).to_string(), "-inf"); + assert_eq!(Hex(f128::ZERO).to_string(), "+0x0p+0"); + assert_eq!(Hex(f128::NEG_ZERO).to_string(), "-0x0p+0"); + + assert_eq!( + Hex(f128::NAN).to_string(), + "+qNaN(0x0000000000000000000000000000)" + ); + assert_eq!( + Hex(f128::SNAN).to_string(), + "+sNaN(0x4000000000000000000000000000)" + ); + assert_eq!( + Hex(f128::NEG_NAN).to_string(), + "-qNaN(0x0000000000000000000000000000)" + ); + assert_eq!( + Hex(f128::NEG_SNAN).to_string(), + "-sNaN(0x4000000000000000000000000000)" + ); + assert_eq!( + Hex(f128::from_bits(u128::MAX)).to_string(), + "-qNaN(0x7fffffffffffffffffffffffffff)" + ); + + assert_eq!(Hex(f128::INFINITY).to_string(), "+inf"); + assert_eq!(Hex(f128::NEG_INFINITY).to_string(), "-inf"); } } } diff --git a/library/compiler-builtins/libm/src/math/support/int_traits.rs b/library/compiler-builtins/libm/src/math/support/int_traits.rs index 55b609affd2e6..48c0e0438bc1d 100644 --- a/library/compiler-builtins/libm/src/math/support/int_traits.rs +++ b/library/compiler-builtins/libm/src/math/support/int_traits.rs @@ -3,6 +3,8 @@ use core::{cmp, fmt, ops}; mod narrowing_div; pub use narrowing_div::NarrowingDiv; +use crate::support::DisplayHex; + /// Minimal integer implementations needed on all integer types, including wide integers. #[allow(dead_code)] // Some constants are only used with tests pub trait MinInt: @@ -40,6 +42,7 @@ pub trait Int: + fmt::Display + fmt::Binary + fmt::LowerHex + + DisplayHex + ops::AddAssign + ops::SubAssign + ops::MulAssign @@ -107,6 +110,7 @@ pub trait Int: fn borrowing_sub(self, other: Self, borrow: bool) -> (Self, bool); fn leading_zeros(self) -> u32; fn trailing_zeros(self) -> u32; + fn count_ones(self) -> u32; fn ilog2(self) -> u32; } @@ -176,6 +180,10 @@ macro_rules! int_impl_common { ::trailing_zeros(self) } + fn count_ones(self) -> u32 { + ::count_ones(self) + } + fn ilog2(self) -> u32 { // On our older MSRV, this resolves to the trait method. Which won't actually work, // but this is only called behind other gates. diff --git a/library/compiler-builtins/libm/src/math/support/int_traits/narrowing_div.rs b/library/compiler-builtins/libm/src/math/support/int_traits/narrowing_div.rs index e76fc5ae9f4ca..942cd5ed2acc0 100644 --- a/library/compiler-builtins/libm/src/math/support/int_traits/narrowing_div.rs +++ b/library/compiler-builtins/libm/src/math/support/int_traits/narrowing_div.rs @@ -153,6 +153,7 @@ mod test { use super::{HInt, NarrowingDiv}; #[test] + #[cfg_attr(miri, ignore)] // This test is very slow when using Miri fn inverse_mul() { for x in 0..=u8::MAX { for y in 1..=u8::MAX { diff --git a/library/compiler-builtins/libm/src/math/support/macros.rs b/library/compiler-builtins/libm/src/math/support/macros.rs index 550d2e92eb7c5..767f15a1c14a3 100644 --- a/library/compiler-builtins/libm/src/math/support/macros.rs +++ b/library/compiler-builtins/libm/src/math/support/macros.rs @@ -1,42 +1,28 @@ -/// `libm` cannot have dependencies, so this is vendored directly from the `cfg-if` crate -/// (with some comments stripped for compactness). -macro_rules! cfg_if { - // match if/else chains with a final `else` - ($( - if #[cfg($meta:meta)] { $($tokens:tt)* } - ) else * else { - $($tokens2:tt)* - }) => { - cfg_if! { @__items () ; $( ( ($meta) ($($tokens)*) ), )* ( () ($($tokens2)*) ), } +// Because `cfg_select` requires rust verion 1.95 and we support older versions, +// we use the following replacement until that is no longer true. +// +// Doesn't support the syntax that rustfmt changes to, hence not calling it just +// `cfg_seelect`. +// +// FIXME(msrv) +macro_rules! cfg_select_nofmt { + ({ $($tt:tt)* }) => {{ + $crate::cfg_select_nofmt! { $($tt)* } + }}; + (_ => { $($output:tt)* }) => { + $($output)* }; - - // match if/else chains lacking a final `else` ( - if #[cfg($i_met:meta)] { $($i_tokens:tt)* } - $( else if #[cfg($e_met:meta)] { $($e_tokens:tt)* } )* + $cfg:meta => $output:tt + $($( $rest:tt )+)? ) => { - cfg_if! { - @__items - () ; - ( ($i_met) ($($i_tokens)*) ), - $( ( ($e_met) ($($e_tokens)*) ), )* - ( () () ), - } - }; - - // Internal and recursive macro to emit all the items - // - // Collects all the negated cfgs in a list at the beginning and after the - // semicolon is all the remaining items - (@__items ($($not:meta,)*) ; ) => {}; - (@__items ($($not:meta,)*) ; ( ($($m:meta),*) ($($tokens:tt)*) ), $($rest:tt)*) => { - #[cfg(all($($m,)* not(any($($not),*))))] cfg_if! { @__identity $($tokens)* } - cfg_if! { @__items ($($not,)* $($m,)*) ; $($rest)* } - }; - - // Internal macro to make __apply work out right for different match types, - // because of how macros matching/expand stuff. - (@__identity $($tokens:tt)*) => { $($tokens)* }; + #[cfg($cfg)] + cfg_select_nofmt! { _ => $output } + $( + #[cfg(not($cfg))] + cfg_select_nofmt! { $($rest)+ } + )? + } } /// Choose between using an arch-specific implementation and the function body. Returns directly @@ -46,7 +32,7 @@ macro_rules! cfg_if { /// These live in the `math::arch::some_target_arch` module. /// /// Specify a `use_arch_required` meta field if something architecture-specific must be used -/// regardless of feature configuration (`force-soft-floats`). +/// regardless of feature configuration (`arch`). /// /// The passed meta options do not need to account for the `arch` target feature. macro_rules! select_implementation { @@ -71,8 +57,9 @@ macro_rules! select_implementation { } } - // By default, never use arch-specific implementations if we have force-soft-floats - #[cfg(arch_enabled)] + // By default, never use arch-specific implementations if `arch` is disabled or with Miri + // (no inline assembly support). + #[cfg(all(feature = "arch", not(miri)))] select_implementation! { @cfg $($use_arch)?; // Wrap in `if true` to avoid unused warnings @@ -146,9 +133,9 @@ macro_rules! assert_biteq { "{}\nl: {l:?} ({lb:#0width$x} {lh})\nr: {r:?} ({rb:#0width$x} {rh})", format_args!($($tt)*), lb = l.to_bits(), - lh = $crate::support::Hexf(l), + lh = $crate::support::Hex(l), rb = r.to_bits(), - rh = $crate::support::Hexf(r), + rh = $crate::support::Hex(r), width = ((bits / 4) + 2) as usize, ); diff --git a/library/compiler-builtins/libm/src/math/support/mod.rs b/library/compiler-builtins/libm/src/math/support/mod.rs index 15ab010dc8d5f..260c37080c981 100644 --- a/library/compiler-builtins/libm/src/math/support/mod.rs +++ b/library/compiler-builtins/libm/src/math/support/mod.rs @@ -14,13 +14,11 @@ mod modular; pub use big::{i256, u256}; // Clippy seems to have a false positive #[allow(unused_imports, clippy::single_component_path_imports)] -pub(crate) use cfg_if; +pub(crate) use cfg_select_nofmt; pub use env::{FpResult, Round, Status}; #[allow(unused_imports)] -pub use float_traits::{DFloat, Float, HFloat, IntTy}; +pub use float_traits::{Float, HalfRep, IntTy, NarrowFloat, WideFloat}; pub(crate) use float_traits::{f32_from_bits, f64_from_bits}; -#[cfg(any(test, feature = "unstable-public-internals"))] -pub use hex_float::Hexf; #[cfg(f16_enabled)] #[allow(unused_imports)] pub use hex_float::hf16; @@ -28,12 +26,60 @@ pub use hex_float::hf16; #[allow(unused_imports)] pub use hex_float::hf128; #[allow(unused_imports)] -pub use hex_float::{hf32, hf64}; +pub use hex_float::{DisplayHex, Hex, hf32, hf64}; pub use int_traits::{CastFrom, CastInto, DInt, HInt, Int, MinInt, NarrowingDiv}; pub use modular::linear_mul_reduction; /// Hint to the compiler that the current path is cold. pub fn cold_path() { #[cfg(intrinsics_enabled)] - core::intrinsics::cold_path(); + core::hint::cold_path(); +} + +/// # Safety +/// +/// `y` must not be zero and the result must not overflow (`x > i32::MIN`). +pub unsafe fn unchecked_div_i32(x: i32, y: i32) -> i32 { + cfg_select_nofmt! { + all(not(debug_assertions), intrinsics_enabled) => { + // Temporary macro to avoid panic codegen for division (in debug mode too). At + // the time of this writing this is only used in a few places, and once + // rust-lang/rust#72751 is fixed then this macro will no longer be necessary and + // the native `/` operator can be used and panics won't be codegen'd. + // + // Note: I am not sure whether the above comment is still up to date, we need + // to double check whether panics are elided where we use this. + unsafe { core::intrinsics::unchecked_div(x, y) } + } + _ => { + x / y + } + } +} + +/// # Safety +/// +/// `y` must not be zero and the result must not overflow (`x > isize::MIN`). +pub unsafe fn unchecked_div_isize(x: isize, y: isize) -> isize { + cfg_select_nofmt! { + all(not(debug_assertions), intrinsics_enabled) => { + unsafe { core::intrinsics::unchecked_div(x, y) } + } + _ => { + x / y + } + } +} + +// FIXME(msrv): `div_ceil` is stable in 1.73. +pub fn div_ceil_u32(a: u32, b: u32) -> u32 { + let d = a / b; + let r = a % b; + if r > 0 { d + 1 } else { d } +} + +// FIXME(msrv): unbounded shifts are stable in 1.87 +#[allow(unused)] +pub fn unbounded_shr_u64(x: u64, shift: u32) -> u64 { + x.checked_shr(shift).unwrap_or(0) } diff --git a/library/compiler-builtins/libm/src/math/support/modular.rs b/library/compiler-builtins/libm/src/math/support/modular.rs index cc0edf2f2bc04..026c599c1bba4 100644 --- a/library/compiler-builtins/libm/src/math/support/modular.rs +++ b/library/compiler-builtins/libm/src/math/support/modular.rs @@ -231,6 +231,7 @@ mod test { use crate::support::modular::Reducer; #[test] + #[cfg_attr(miri, ignore)] // This test is very slow when using Miri fn reducer_ops() { for n in 33..=63_u8 { for x in 0..2 * n { @@ -259,6 +260,7 @@ mod test { } } #[test] + #[cfg_attr(miri, ignore)] // This test is very slow when using Miri fn reduction_u8() { for y in 1..64u8 { for x in 0..2 * y { diff --git a/library/compiler-builtins/libm/src/math/tgamma.rs b/library/compiler-builtins/libm/src/math/tgamma.rs index 41415d9d12589..c526842470c85 100644 --- a/library/compiler-builtins/libm/src/math/tgamma.rs +++ b/library/compiler-builtins/libm/src/math/tgamma.rs @@ -23,6 +23,7 @@ Gamma(x)*Gamma(-x) = -pi/(x sin(pi x)) most ideas and constants are from boost and python */ use super::{exp, floor, k_cos, k_sin, pow}; +use crate::support::unchecked_div_isize; const PI: f64 = 3.141592653589793238462643383279502884; @@ -37,7 +38,8 @@ fn sinpi(mut x: f64) -> f64 { /* reduce x into [-.25,.25] */ n = (4.0 * x) as isize; - n = div!(n + 1, 2); + // SAFETY: nonzero divisor, nonnegative dividend (`n < 8`). + n = unsafe { unchecked_div_isize(n + 1, 2) }; x -= (n as f64) * 0.5; x *= PI; diff --git a/library/compiler-builtins/libm/src/math/trunc.rs b/library/compiler-builtins/libm/src/math/trunc.rs index 20d52a111a120..9eb902ea578f8 100644 --- a/library/compiler-builtins/libm/src/math/trunc.rs +++ b/library/compiler-builtins/libm/src/math/trunc.rs @@ -1,10 +1,12 @@ +use super::generic; + /// Rounds the number toward 0 to the closest integral value (f16). /// /// This effectively removes the decimal part of the number, leaving the integral part. #[cfg(f16_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn truncf16(x: f16) -> f16 { - super::generic::trunc(x) + generic::trunc_status(x).val } /// Rounds the number toward 0 to the closest integral value (f32). @@ -18,7 +20,7 @@ pub fn truncf(x: f32) -> f32 { args: x, } - super::generic::trunc(x) + generic::trunc_status(x).val } /// Rounds the number toward 0 to the closest integral value (f64). @@ -32,7 +34,7 @@ pub fn trunc(x: f64) -> f64 { args: x, } - super::generic::trunc(x) + generic::trunc_status(x).val } /// Rounds the number toward 0 to the closest integral value (f128). @@ -41,13 +43,105 @@ pub fn trunc(x: f64) -> f64 { #[cfg(f128_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn truncf128(x: f128) -> f128 { - super::generic::trunc(x) + generic::trunc_status(x).val } #[cfg(test)] mod tests { + use super::*; + use crate::support::{Float, FpResult, Hex, Status}; + + macro_rules! cases { + ($f:ty) => { + [ + // roundtrip + (0.0, 0.0, Status::OK), + (-0.0, -0.0, Status::OK), + (1.0, 1.0, Status::OK), + (-1.0, -1.0, Status::OK), + (<$f>::INFINITY, <$f>::INFINITY, Status::OK), + (<$f>::NEG_INFINITY, <$f>::NEG_INFINITY, Status::OK), + // with rounding + (0.1, 0.0, Status::INEXACT), + (-0.1, -0.0, Status::INEXACT), + (0.5, 0.0, Status::INEXACT), + (-0.5, -0.0, Status::INEXACT), + (0.9, 0.0, Status::INEXACT), + (-0.9, -0.0, Status::INEXACT), + (1.1, 1.0, Status::INEXACT), + (-1.1, -1.0, Status::INEXACT), + (1.5, 1.0, Status::INEXACT), + (-1.5, -1.0, Status::INEXACT), + (1.9, 1.0, Status::INEXACT), + (-1.9, -1.0, Status::INEXACT), + ] + }; + } + + #[track_caller] + fn check(f: fn(F) -> F, cases: &[(F, F, Status)]) { + for &(x, exp_res, exp_stat) in cases { + let FpResult { val, status } = generic::trunc_status(x); + assert_biteq!(val, exp_res, "generic::trunc_status({x:?}) ({})", Hex(x)); + assert_eq!( + status, + exp_stat, + "{x:?} {} -> {exp_res:?} {}", + Hex(x), + Hex(exp_res) + ); + let val = f(x); + assert_biteq!(val, exp_res, "trunc({x:?}) ({})", Hex(x)); + } + } + + #[test] + #[cfg(f16_enabled)] + fn check_f16() { + check::(truncf16, &cases!(f16)); + check::( + truncf16, + &[ + (hf16!("0x1p10"), hf16!("0x1p10"), Status::OK), + (hf16!("-0x1p10"), hf16!("-0x1p10"), Status::OK), + ], + ); + } + + #[test] + fn check_f32() { + check::(truncf, &cases!(f32)); + check::( + truncf, + &[ + (hf32!("0x1p23"), hf32!("0x1p23"), Status::OK), + (hf32!("-0x1p23"), hf32!("-0x1p23"), Status::OK), + ], + ); + } + + #[test] + fn check_f64() { + check::(trunc, &cases!(f64)); + check::( + trunc, + &[ + (hf64!("0x1p52"), hf64!("0x1p52"), Status::OK), + (hf64!("-0x1p52"), hf64!("-0x1p52"), Status::OK), + ], + ); + } + #[test] - fn sanity_check() { - assert_eq!(super::truncf(1.1), 1.0); + #[cfg(f128_enabled)] + fn check_f128() { + check::(truncf128, &cases!(f128)); + check::( + truncf128, + &[ + (hf128!("0x1p112"), hf128!("0x1p112"), Status::OK), + (hf128!("-0x1p112"), hf128!("-0x1p112"), Status::OK), + ], + ); } } diff --git a/library/compiler-builtins/rust-version b/library/compiler-builtins/rust-version index 6a2835bc2d9eb..2f175e966812d 100644 --- a/library/compiler-builtins/rust-version +++ b/library/compiler-builtins/rust-version @@ -1 +1 @@ -23d01cd2412583491621ab1ca4f1b01e37d11e39 +2c39ff499469be916d4e45506d1afed69bbaddb7 diff --git a/library/compiler-builtins/triagebot.toml b/library/compiler-builtins/triagebot.toml index b210a5fb52563..d0cdb497edbad 100644 --- a/library/compiler-builtins/triagebot.toml +++ b/library/compiler-builtins/triagebot.toml @@ -10,7 +10,7 @@ exclude_titles = ["Rustc pull update"] # when commits are included in subtrees, as well as warning links in commits. # Documentation at: https://forge.rust-lang.org/triagebot/issue-links.html [issue-links] -check-commits = false +check-commits = "uncanonicalized" # Enable issue transfers within the org # Documentation at: https://forge.rust-lang.org/triagebot/transfer.html diff --git a/library/core/Cargo.toml b/library/core/Cargo.toml index 66452e569f778..1ad634c91554c 100644 --- a/library/core/Cargo.toml +++ b/library/core/Cargo.toml @@ -26,7 +26,6 @@ optimize_for_size = [] # Make `RefCell` store additional debugging information, which is printed out when # a borrow error occurs debug_refcell = [] -llvm_enzyme = [] [lints.rust.unexpected_cfgs] level = "warn" @@ -46,6 +45,9 @@ check-cfg = [ 'cfg(kani)', 'cfg(flux)', 'cfg(rapx)', + # Prevents use of a static variable for providing platform specific RawOsError + # functionality + 'cfg(no_io_statics)', ] [package.metadata.flux] diff --git a/library/core/src/alloc/global.rs b/library/core/src/alloc/global.rs index 9b80e3b70fa2f..e1e08ab7a2cb9 100644 --- a/library/core/src/alloc/global.rs +++ b/library/core/src/alloc/global.rs @@ -1,4 +1,7 @@ +use super::{AllocError, GlobalAllocator}; use crate::alloc::Layout; +use crate::hint::assert_unchecked; +use crate::ptr::NonNull; use crate::{cmp, ptr}; /// A memory allocator that can be registered as the standard library’s default @@ -16,10 +19,9 @@ use crate::{cmp, ptr}; /// method such as `dealloc` or by being /// passed to a reallocation method that returns a non-null pointer. /// -/// /// # Example /// -/// ``` +/// ```standalone_crate /// use std::alloc::{GlobalAlloc, Layout}; /// use std::cell::UnsafeCell; /// use std::ptr::null_mut; @@ -57,7 +59,7 @@ use crate::{cmp, ptr}; /// let mut allocated = 0; /// if self /// .remaining -/// .fetch_update(Relaxed, Relaxed, |mut remaining| { +/// .try_update(Relaxed, Relaxed, |mut remaining| { /// if size > remaining { /// return None; /// } @@ -82,39 +84,83 @@ use crate::{cmp, ptr}; /// } /// ``` /// +/// # The `#[global_allocator]` attribute +/// +/// As the example above demonstrates, the `#[global_allocator]` attribute can be used to register a +/// concrete `static` of a type that implements this trait to become *the* global allocator +/// for the current program. That global allocator can be invoked via the functions [`alloc`], +/// [`alloc_zeroed`], [`dealloc`], [`realloc`]). Note, however, that invoking those functions is +/// *not* equivalent to directly invoking the underlying methods on the declared global allocator! +/// Users of the global allocator cannot assume anything about what the allocator does (even if they know which allocator is being used), +/// and implementors of the allocator cannot assume anything about what the program does (even if they know how the allocator is being used). +/// Both can only assume the documented requirements for the respective other party of this contract. +/// This means: +/// +/// - Allocation functions may non-deterministically entirely skip the underlying allocator, e.g. if the +/// compiler can show that this allocation can be replaced by a stack variable. The compiler may +/// also merge multiple allocation operations into one, as long as it can also adjust all +/// corresponding deallocation operations accordingly. +/// - An allocation created by invoking [`alloc`], [`alloc_zeroed`], or [`realloc`] has exactly the +/// size and minimum alignment defined by `layout`, even if the underlying allocator makes +/// stronger promises. +/// - An allocation created by invoking [`alloc`], [`alloc_zeroed`], or [`realloc`] can only be +/// freed by invoking [`dealloc`] or [`realloc`]. In particular, passing a pointer to such an +/// allocation directly to the underlying method on [`GlobalAlloc`] is not permitted. Until one of +/// those functions is called, it is undefined behavior to access the memory that backs this +/// allocation with any pointer not derived from the return value of this function (e.g., with +/// internal pointers the allocator might keep around). +/// - The pointer passed to [`dealloc`] or [`realloc`] must have been obtained by invoking [`alloc`], +/// [`alloc_zeroed`], or [`realloc`]. In particular, passing a pointer returned by the underlying +/// methods on [`GlobalAlloc`] is not permitted. +/// - [`alloc`] de-initializes the contents of the allocation before handing it to the user. So even +/// if you control the underlying allocator and know that it explicitly initialized this memory, +/// you cannot rely on it being initialized. For a [`realloc`] that grows an allocation, this +/// applies to the newly allocated part. +/// - [`dealloc`] de-initializes the contents of the allocation before handing it to the allocator. +/// So even if you know that the program previously initialized that memory, the allocator cannot +/// rely on it being initialized. For a [`realloc`] that shrinks an allocation, this applies to +/// the part being removed. +/// +/// [`alloc`]: ../../std/alloc/fn.alloc.html +/// [`alloc_zeroed`]: ../../std/alloc/fn.alloc_zeroed.html +/// [`dealloc`]: ../../std/alloc/fn.dealloc.html +/// [`realloc`]: ../../std/alloc/fn.realloc.html +/// +/// The first point means that you cannot rely on global allocations actually happening, even if +/// there are explicit global allocations in the source. The optimizer may detect unused global +/// allocations that it can either eliminate entirely or move to the stack and thus never invoke the +/// global allocator. The optimizer may further assume that allocation is infallible, so code that +/// used to fail due to allocator failures may now suddenly work because the optimizer worked around +/// the need for an allocation. More concretely, the following code example is unsound, irrespective +/// of whether your custom allocator allows counting how many allocations have happened. +/// +/// ```rust,ignore (unsound and has placeholders) +/// drop(Box::new(42)); +/// let number_of_heap_allocs = /* call private allocator API */; +/// unsafe { std::hint::assert_unchecked(number_of_heap_allocs > 0); } +/// ``` +/// +/// Note that the optimizations mentioned above are not the only +/// optimization that can be applied. You may generally not rely on global allocations +/// happening if they can be removed without changing program behavior. +/// Whether allocations happen or not is not part of the program behavior, even if it +/// could be detected via an allocator that tracks allocations by printing or otherwise +/// having side effects. +/// /// # Safety /// /// The `GlobalAlloc` trait is an `unsafe` trait for a number of reasons, and /// implementors must ensure that they adhere to these contracts: /// +/// * It is undefined behavior for the allocator to read, write, or deallocate any memory that +/// is *currently allocated*. This memory is owned by the user, the allocator must not touch it. +/// /// * It's undefined behavior if global allocators unwind. This restriction may /// be lifted in the future, but currently a panic from any of these /// functions may lead to memory unsafety. /// -/// * `Layout` queries and calculations in general must be correct. Callers of -/// this trait are allowed to rely on the contracts defined on each method, -/// and implementors must ensure such contracts remain true. -/// -/// * You must not rely on allocations actually happening, even if there are explicit -/// heap allocations in the source. The optimizer may detect unused allocations that it can either -/// eliminate entirely or move to the stack and thus never invoke the allocator. The -/// optimizer may further assume that allocation is infallible, so code that used to fail due -/// to allocator failures may now suddenly work because the optimizer worked around the -/// need for an allocation. More concretely, the following code example is unsound, irrespective -/// of whether your custom allocator allows counting how many allocations have happened. -/// -/// ```rust,ignore (unsound and has placeholders) -/// drop(Box::new(42)); -/// let number_of_heap_allocs = /* call private allocator API */; -/// unsafe { std::hint::assert_unchecked(number_of_heap_allocs > 0); } -/// ``` -/// -/// Note that the optimizations mentioned above are not the only -/// optimization that can be applied. You may generally not rely on heap allocations -/// happening if they can be removed without changing program behavior. -/// Whether allocations happen or not is not part of the program behavior, even if it -/// could be detected via an allocator that tracks allocations by printing or otherwise -/// having side effects. +/// * Callers of this trait are allowed to rely on the contracts defined on each method, and +/// implementors must ensure such contracts remain true. /// /// # Re-entrance /// @@ -130,7 +176,7 @@ use crate::{cmp, ptr}; /// - [`std::thread_local`], /// - [`std::thread::current`], /// - [`std::thread::park`] and [`std::thread::Thread`]'s [`unpark`] method and -/// [`Clone`] implementation. +/// [`Clone`] implementation. /// /// [`std`]: ../../std/index.html /// [`std::sync::Mutex`]: ../../std/sync/struct.Mutex.html @@ -139,7 +185,6 @@ use crate::{cmp, ptr}; /// [`std::thread::park`]: ../../std/thread/fn.park.html /// [`std::thread::Thread`]: ../../std/thread/struct.Thread.html /// [`unpark`]: ../../std/thread/struct.Thread.html#method.unpark - #[stable(feature = "global_alloc", since = "1.28.0")] pub unsafe trait GlobalAlloc { /// Allocates memory as described by the given `layout`. @@ -171,7 +216,7 @@ pub unsafe trait GlobalAlloc { /// /// Clients wishing to abort computation in response to an /// allocation error are encouraged to call the [`handle_alloc_error`] function, - /// rather than directly invoking `panic!` or similar. + /// rather than directly invoking `panic!` or similar (but note that both may unwind). /// /// [`handle_alloc_error`]: ../../alloc/alloc/fn.handle_alloc_error.html #[stable(feature = "global_alloc", since = "1.28.0")] @@ -284,9 +329,10 @@ pub unsafe trait GlobalAlloc { /// [`handle_alloc_error`]: ../../alloc/alloc/fn.handle_alloc_error.html #[stable(feature = "global_alloc", since = "1.28.0")] unsafe fn realloc(&self, ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { - // SAFETY: the caller must ensure that the `new_size` does not overflow. - // `layout.align()` comes from a `Layout` and is thus guaranteed to be valid. - let new_layout = unsafe { Layout::from_size_align_unchecked(new_size, layout.align()) }; + let alignment = layout.alignment(); + // SAFETY: the caller must ensure that the `new_size` does not overflow + // when rounded up to the next multiple of `alignment`. + let new_layout = unsafe { Layout::from_size_alignment_unchecked(new_size, alignment) }; // SAFETY: the caller must ensure that `new_layout` is greater than zero. let new_ptr = unsafe { self.alloc(new_layout) }; if !new_ptr.is_null() { @@ -300,3 +346,72 @@ pub unsafe trait GlobalAlloc { new_ptr } } + +/// Allows all [`GlobalAllocator`]s to be used with the legacy [`GlobalAlloc`] interface. +#[stable(feature = "global_alloc", since = "1.28.0")] +unsafe impl GlobalAlloc for A +where + A: GlobalAllocator + ?Sized, +{ + unsafe fn alloc(&self, layout: Layout) -> *mut u8 { + // SAFETY: guaranteed by the caller. + // This might lead to the removal of zero-size checks inside the + // `Allocator` implementation. + unsafe { assert_unchecked(layout.size() != 0) }; + match self.allocate(layout) { + Ok(ptr) => ptr.cast().as_ptr(), + Err(AllocError) => ptr::null_mut(), + } + } + + unsafe fn dealloc(&self, ptr: *mut u8, layout: Layout) { + // SAFETY: guaranteed by the caller. + unsafe { assert_unchecked(layout.size() != 0) }; + // SAFETY: only non-null pointers can be currently allocated. + let ptr = unsafe { NonNull::new_unchecked(ptr) }; + // SAFETY: guaranteed by caller. + unsafe { self.deallocate(ptr, layout) }; + } + + unsafe fn alloc_zeroed(&self, layout: Layout) -> *mut u8 { + // SAFETY: guaranteed by the caller. + unsafe { assert_unchecked(layout.size() != 0) }; + match self.allocate_zeroed(layout) { + Ok(ptr) => ptr.cast().as_ptr(), + Err(AllocError) => ptr::null_mut(), + } + } + + unsafe fn realloc(&self, ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { + // SAFETY: guaranteed by the caller. + unsafe { assert_unchecked(layout.size() != 0) }; + // SAFETY: guaranteed by the caller. + unsafe { assert_unchecked(new_size != 0) }; + + // SAFETY: only non-null pointers can be currently allocated. + let ptr = unsafe { NonNull::new_unchecked(ptr) }; + let alignment = layout.alignment(); + // SAFETY: the caller must ensure that the `new_size` does not overflow + // when rounded up to the next multiple of `alignment`. + let new_layout = unsafe { Layout::from_size_alignment_unchecked(new_size, alignment) }; + + // SAFETY: + // Two preconditions are guaranteed by the caller: + // * `ptr` is currently allocated with this allocator. + // * `layout` fits the block of memory. + // The size precondition is upheld by selecting between `grow` and `shrink` + // based on the size. + let ptr = unsafe { + if new_size >= layout.size() { + self.grow(ptr, layout, new_layout) + } else { + self.shrink(ptr, layout, new_layout) + } + }; + + match ptr { + Ok(ptr) => ptr.cast().as_ptr(), + Err(AllocError) => ptr::null_mut(), + } + } +} diff --git a/library/core/src/alloc/layout.rs b/library/core/src/alloc/layout.rs index 67f917345894c..de592466ce467 100644 --- a/library/core/src/alloc/layout.rs +++ b/library/core/src/alloc/layout.rs @@ -12,8 +12,8 @@ use crate::error::Error; use crate::intrinsics::{unchecked_add, unchecked_mul, unchecked_sub}; #[cfg(kani)] use crate::kani; -use crate::mem::SizedTypeProperties; -use crate::ptr::{Alignment, NonNull}; +use crate::mem::{Alignment, SizedTypeProperties}; +use crate::ptr::NonNull; // Used only for contract verification. #[allow(unused_imports)] use crate::ub_checks::Invariant; @@ -249,37 +249,43 @@ impl Layout { /// /// # Safety /// - /// This function is only safe to call if the following conditions hold: + /// This function is safe to call if the pointer is safe to reborrow as `&T` + /// (in which case you could also call [`for_value`][Self::for_value]). + /// Otherwise, the following conditions must hold: /// /// - If `T` is `Sized`, this function is always safe to call. /// - If the unsized tail of `T` is: - /// - a [slice], then the length of the slice tail must be an initialized - /// integer, and the size of the *entire value* + /// - a [slice] `[U]`, `str`, or a [trait object] `dyn Trait`, then the size of the *entire value* /// (dynamic tail length + statically sized prefix) must fit in `isize`. /// For the special case where the dynamic tail length is 0, this function /// is safe to call. - /// - a [trait object], then the vtable part of the pointer must point - /// to a valid vtable for the type `T` acquired by an unsizing coercion, - /// and the size of the *entire value* - /// (dynamic tail length + statically sized prefix) must fit in `isize`. - /// - an (unstable) [extern type], then this function is always safe to - /// call, but may panic or otherwise return the wrong value, as the - /// extern type's layout is not known. This is the same behavior as - /// [`Layout::for_value`] on a reference to an extern type tail. - /// - otherwise, it is conservatively not allowed to call this function. + // NOTE: the reason this is safe is that if an overflow were to occur already with size 0, + // then we would stop compilation as even the "statically known" part of the type would + // already be too big (or the call may be in dead code and optimized away, but then it + // doesn't matter). + /// - No other kind of unsized tail currently exists that satisfies the trait bounds for this + /// function. If more kinds of unsized tails get introduced in the future, the documentation + /// of this function will have to be extended before it can be used for such types. + /// + /// Here, *unsized tail* refers to the type obtained by recursively descending through the last + /// field of a tuple or struct until we arrived at a built-in unsized type. + /// + /// As a consequence of these rules, it is the case that whenever it is allowed to convert `val` + /// into a shared reference, then it is also allowed to invoke this function. /// /// [trait object]: ../../book/ch17-02-trait-objects.html /// [extern type]: ../../unstable-book/language-features/extern-types.html - #[unstable(feature = "layout_for_ptr", issue = "69835")] + #[stable(feature = "layout_for_ptr", since = "1.99.0")] + #[rustc_const_stable(feature = "layout_for_ptr", since = "1.99.0")] #[must_use] #[inline] // TODO: we should try to capture the above constraints on T in a `requires` clause, and the // metadata helpers from https://github.com/model-checking/verify-rust-std/pull/37 may be able // to accomplish this. #[ensures(|result| result.align().is_power_of_two())] - pub const unsafe fn for_value_raw(t: *const T) -> Self { + pub const unsafe fn for_value_raw(val: *const T) -> Self { // SAFETY: we pass along the prerequisites of these functions to the caller - let (size, alignment) = unsafe { (mem::size_of_val_raw(t), Alignment::of_val_raw(t)) }; + let (size, alignment) = unsafe { (mem::size_of_val_raw(val), Alignment::of_val_raw(val)) }; // SAFETY: see rationale in `new` for why this is using the unsafe variant unsafe { Layout::from_size_alignment_unchecked(size, alignment) } } @@ -290,13 +296,13 @@ impl Layout { /// be that of a valid pointer, which means this must not be used /// as a "not yet initialized" sentinel value. /// Types that lazily allocate must track initialization by some other means. - #[stable(feature = "alloc_layout_extra", since = "CURRENT_RUSTC_VERSION")] - #[rustc_const_stable(feature = "alloc_layout_extra", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "alloc_layout_extra", since = "1.95.0")] + #[rustc_const_stable(feature = "alloc_layout_extra", since = "1.95.0")] #[must_use] #[inline] #[ensures(|result| result.is_aligned())] pub const fn dangling_ptr(&self) -> NonNull { - NonNull::without_provenance(self.align.as_nonzero()) + NonNull::without_provenance(self.align.as_nonzero_usize()) } /// Creates a layout describing the record that can hold a value @@ -458,8 +464,8 @@ impl Layout { /// let repeated = padding_needed.repeat(0).unwrap(); /// assert_eq!(repeated, (Layout::from_size_align(0, 4).unwrap(), 8)); /// ``` - #[stable(feature = "alloc_layout_extra", since = "CURRENT_RUSTC_VERSION")] - #[rustc_const_stable(feature = "alloc_layout_extra", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "alloc_layout_extra", since = "1.95.0")] + #[rustc_const_stable(feature = "alloc_layout_extra", since = "1.95.0")] #[inline] // Since rust-lang/rust#148769, the result does not include padding after the trailing // element, i.e., on success the resulting size is (n - 1) * stride + self.size() for n > 0 @@ -575,8 +581,8 @@ impl Layout { /// aligned. /// /// On arithmetic overflow, returns `LayoutError`. - #[stable(feature = "alloc_layout_extra", since = "CURRENT_RUSTC_VERSION")] - #[rustc_const_stable(feature = "alloc_layout_extra", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "alloc_layout_extra", since = "1.95.0")] + #[rustc_const_stable(feature = "alloc_layout_extra", since = "1.95.0")] #[inline] // for Kani (v0.54.0), the below multiplication is too costly to prove (running into the // 6-hours timeout on GitHub); we use a weaker postcondition instead @@ -600,8 +606,8 @@ impl Layout { /// and is not incorporated *at all* into the resulting layout. /// /// On arithmetic overflow, returns `LayoutError`. - #[stable(feature = "alloc_layout_extra", since = "CURRENT_RUSTC_VERSION")] - #[rustc_const_stable(feature = "alloc_layout_extra", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "alloc_layout_extra", since = "1.95.0")] + #[rustc_const_stable(feature = "alloc_layout_extra", since = "1.95.0")] #[inline] #[ensures(|result| result.is_err() || result.as_ref().unwrap().size() == self.size() + next.size())] #[ensures(|result| result.is_err() || result.as_ref().unwrap().align() == self.align())] diff --git a/library/core/src/alloc/mod.rs b/library/core/src/alloc/mod.rs index 959407b753487..6069c468f96e4 100644 --- a/library/core/src/alloc/mod.rs +++ b/library/core/src/alloc/mod.rs @@ -49,80 +49,181 @@ impl fmt::Display for AllocError { /// An implementation of `Allocator` can allocate, grow, shrink, and deallocate arbitrary blocks of /// data described via [`Layout`][]. /// -/// `Allocator` is designed to be implemented on ZSTs, references, or smart pointers. -/// An allocator for `MyAlloc([u8; N])` cannot be moved, without updating the pointers to the -/// allocated memory. +/// `Allocator` is mostly designed to be implemented on ZSTs, references, or smart pointers, +/// but can also be implemented directly on the underlying memory-owning type so long as it +/// upholds the necessary guarantees. In general, an allocator of the type `MyAlloc([u8; N])` +/// cannot be soundly created without being pinned or otherwise immovable in order to be +/// correct. /// /// In contrast to [`GlobalAlloc`][], `Allocator` allows zero-sized allocations. If an underlying /// allocator does not support this (like jemalloc) or responds by returning a null pointer /// (such as `libc::malloc`), this must be caught by the implementation. /// +/// In order to be usable in a flexible manner while still being sound, implementors of the trait +/// must uphold very detailed semantics as explained below; the following terms are thus provided +/// as vocabulary for allocator safety and implementation requirements: +/// +/// ### Equivalent allocators +/// +/// Multiple allocator values can sometimes be interchangeable with each other. +/// When this is the case, we refer to those allocators as being *equivalent* to +/// each other. +/// +/// Users of allocators may assume the following are true of equivalent allocators, +/// and implementors must ensure these rules are upheld: +/// * An allocator is equivalent to itself. (Equivalence is reflexive.) +/// * If an allocator is equivalent to a second allocator, then +/// the second allocator is also equivalent to the first. (Equivalence is symmetric.) +/// * If an allocator is equivalent to a second allocator, and +/// the second allocator is equivalent to a third allocator, then +/// the first allocator is also equivalent to the third allocator. +/// (Equivalence is transitive.) +/// * Moving, subtyping, unsize-coercing, or trait-upcasting an allocator does not change +/// what the allocator is equivalent to. +/// * Copying or cloning an allocator creates an equivalent one, should the +/// [`AllocatorClone`] trait be implemented. +/// +/// Additionally, implementors of `Allocator` may specify additional equivalences +/// between allocators. It is the responsibility of such implementors to make sure +/// that equivalent allocators have "compatible" `Allocator` implementations. +/// In particular, the standard library specifies the following equivalences: +/// * A reference to an allocator (either `&` or `&mut`) is equivalent to +/// the allocator being referenced. +/// * A `Box`, `Rc`, or `Arc` containing an allocator is equivalent to +/// the allocator inside. +/// * All `Global` allocator instances are equivalent with each other. +/// * All `System` allocator instances are equivalent with each other. +/// /// ### Currently allocated memory /// -/// Some of the methods require that a memory block is *currently allocated* by an allocator. +/// Some of the methods require that a memory block is *currently allocated* by some specific allocator. /// This means that: -/// * the starting address for that memory block was previously -/// returned by [`allocate`], [`grow`], or [`shrink`], and -/// * the memory block has not subsequently been deallocated. +/// * the starting address for that memory block was previously returned by +/// the [`allocate`], [`allocate_zeroed`], [`grow`], [`grow_zeroed`], or [`shrink`] methods, +/// called on an allocator that's equivalent to this specific allocator; and +/// * the memory block has not subsequently been [*invalidated*]. +/// +/// ### Invalidating memory blocks +/// +/// A memory block that is currently allocated becomes *invalidated* when one +/// of the following happens: +/// * The memory block is deallocated. This occurs when the memory block +/// is passed as an argument to a [`deallocate`] call, or when it is passed +/// as an argument to a [`grow`], [`grow_zeroed`] or [`shrink`] call that returns `Ok`. +/// * For all (equivalent) allocators that this memory block is currently allocated by, at +/// least one of the following has occurred: +/// * The allocator's destructor runs. +/// * The allocator is mutated through a public or otherwise untrusted API taking `&mut` access. +/// * One of the borrow-checker lifetimes in the allocator's type expires. /// -/// A memory block is deallocated by a call to [`deallocate`], -/// or by a call to [`grow`] or [`shrink`] that returns `Ok`. -/// A call to `grow` or `shrink` that returns `Err`, -/// does not deallocate the memory block passed to it. +/// Note that these conditions imply that a collection may ensure that +/// any specific currently allocated memory block won't be invalidated by: +/// * not deallocating that memory block, +/// * owning an allocator that memory block is allocated with, and +/// * not publicly exposing `&mut` access to that allocator. +/// +/// Also note that safe public API of an allocator with `&` access is not +/// allowed to invalidate its memory blocks. Furthermore, unsafe public API +/// of an allocator with `&` access must document that they invalidate +/// memory blocks (e.g., by calling `deallocate`) if they do. Therefore, +/// a collection may safely expose `&` access to its allocator. +/// +/// Also note that, even in cases where there are other "alive" allocators known +/// to be equivalent to a given collection's allocator, most collections still should +/// not publicly expose `&mut` access to their allocators. The fact that there are +/// other "alive" allocators would prevent this `&mut` access from invalidating +/// the collection's memory block, but public `&mut` access is still likely to +/// be unsound, since a user could replace the collection's allocator with +/// a non-equivalent allocator, causing the collection to deallocate its memory +/// with the wrong allocator. /// /// [`allocate`]: Allocator::allocate +/// [`allocate_zeroed`]: Allocator::allocate_zeroed /// [`grow`]: Allocator::grow +/// [`grow_zeroed`]: Allocator::grow_zeroed /// [`shrink`]: Allocator::shrink /// [`deallocate`]: Allocator::deallocate /// /// ### Memory fitting /// -/// Some of the methods require that a `layout` *fit* a memory block or vice versa. This means that the -/// following conditions must hold: +/// Some of the methods require that a `layout` *fits* a memory block or vice versa. This means +/// that the following conditions must hold: /// * the memory block must be *currently allocated* with alignment of [`layout.align()`], and /// * [`layout.size()`] must fall in the range `min ..= max`, where: /// - `min` is the size of the layout used to allocate the block, and -/// - `max` is the actual size returned from [`allocate`], [`grow`], or [`shrink`]. +/// - `max` is the actual size returned from [`allocate`], [`allocate_zeroed`], +/// [`grow`], [`grow_zeroed`], or [`shrink`]. /// /// [`layout.align()`]: Layout::align /// [`layout.size()`]: Layout::size /// /// # Safety /// -/// Memory blocks that are [*currently allocated*] by an allocator, -/// must point to valid memory, and retain their validity until either: -/// - the memory block is deallocated, or -/// - the allocator is dropped. +/// Implementors of `Allocator` must ensure that a memory block that +/// is [*currently allocated*] by the allocator points to valid memory +/// until that memory block is [*invalidated*]. The implementor must also +/// not violate this invariant of `Allocator` via allocator equivalences +/// that are in the implementor's control. +/// +/// Additionally, any memory block returned by the allocator must +/// satisfy the allocation invariants described in `core::ptr`. +/// In particular, if a block has base address `p` and size `n`, +/// then `p as usize + n <= usize::MAX` must hold. These blocks must also +/// be wholly disjoint. /// -/// Copying, cloning, or moving the allocator must not invalidate memory blocks returned from it. -/// A copied or cloned allocator must behave like the original allocator. +/// This ensures that pointer arithmetic within the allocation +/// (for example, `ptr.add(len)`) cannot overflow the address space, and +/// that it is possible to perform nonoverlapping copies between allocations. /// -/// A memory block which is [*currently allocated*] may be passed to -/// any method of the allocator that accepts such an argument. +/// None of the allocating or deallocating methods may unwind. This restriction +/// may be lifted in the future by ensuring unwinding out of an allocating function always +/// aborts. If an implementor of `Allocator` also has drop glue or directly implements `Drop`, +/// dropping the allocator must not result in an unwind. +/// +/// It is undefined behavior for the allocator to read, write, or deallocate any memory that +/// is currently allocated. This memory is owned by the user; the allocator must not touch it. +/// +/// Lastly, the methods on this trait must be *correct*; in particular, the layout requested +/// must be respected, calls must zero out memory if the documentation so requires, +/// returning an `AllocError` from a reallocating method must indeed ensure that +/// the old pointer was not invalidated, and de/reallocating calls must accept layouts +/// in the ranges defined by their documentation. /// /// [*currently allocated*]: #currently-allocated-memory +/// [*invalidated*]: #invalidating-memory-blocks +// NOTE: the above bound on allocating methods not unwinding, alongside the similar +// bound on `AllocatorClone`, are currently load-bearing in std! see the below issues +// and make sure they cannot be triggered before relaxing this: +// https://rust.tf/156490 +// https://rust.tf/159982 #[unstable(feature = "allocator_api", issue = "32838")] #[rustc_const_unstable(feature = "const_heap", issue = "79597")] pub const unsafe trait Allocator { /// Attempts to allocate a block of memory. /// - /// On success, returns a [`NonNull<[u8]>`][NonNull] meeting the size and alignment guarantees of `layout`. + /// On success, returns a [`NonNull<[u8]>`][NonNull] meeting the size and alignment + /// guarantees of `layout`. The returned block may have a larger size than specified + /// by `layout.size()`, and may or may not have its contents initialized. /// - /// The returned block may have a larger size than specified by `layout.size()`, and may or may - /// not have its contents initialized. + /// It is recommended that overallocating as per the above is only performed if doing so + /// is cheap; there is no guarantee that the caller is able to take advantage of the + /// returned excess. Implementors are free to e.g. provide an alternate method to query + /// available excess if doing so is expensive and should be left to the caller. /// - /// The returned block of memory remains valid as long as it is [*currently allocated*] and the shorter of: - /// - the borrow-checker lifetime of the allocator type itself. - /// - as long as the allocator and all its clones have not been dropped. + /// Note that the returned block of memory is considered [*currently allocated*] + /// with this allocator (and equivalent allocators). + /// Therefore, it is the responsibility of implementors of `Allocator` to make sure that + /// this block of memory remains valid until it is [*invalidated*]. /// /// [*currently allocated*]: #currently-allocated-memory + /// [*invalidated*]: #invalidating-memory-blocks /// /// # Errors /// /// Returning `Err` indicates that either memory is exhausted or `layout` does not meet /// allocator's size or alignment constraints. /// - /// Implementations are encouraged to return `Err` on memory exhaustion rather than panicking or + /// Implementations are encouraged to return `Err` on memory exhaustion rather than /// aborting, but this is not a strict requirement. (Specifically: it is *legal* to implement /// this trait atop an underlying native allocation library that aborts on memory exhaustion.) /// @@ -139,7 +240,7 @@ pub const unsafe trait Allocator { /// Returning `Err` indicates that either memory is exhausted or `layout` does not meet /// allocator's size or alignment constraints. /// - /// Implementations are encouraged to return `Err` on memory exhaustion rather than panicking or + /// Implementations are encouraged to return `Err` on memory exhaustion rather than /// aborting, but this is not a strict requirement. (Specifically: it is *legal* to implement /// this trait atop an underlying native allocation library that aborts on memory exhaustion.) /// @@ -161,6 +262,13 @@ pub const unsafe trait Allocator { /// * `ptr` must denote a block of memory [*currently allocated*] via this allocator, and /// * `layout` must [*fit*] that block of memory. /// + /// Note that it is *immediate* language UB for a deallocation or reallocation to + /// invalidate any outstanding references, smart pointers, etc.; thus, notably, an + /// allocator that has been moved into its own [*currently allocated*] memory may + /// not have its backing memory be freed, even if the allocator is never used again + /// afterwards. This is due to the fact that such a deallocation would invalidate the + /// `&self` reference passed to this method. + /// /// [*currently allocated*]: #currently-allocated-memory /// [*fit*]: #memory-fitting unsafe fn deallocate(&self, ptr: NonNull, layout: Layout); @@ -171,13 +279,13 @@ pub const unsafe trait Allocator { /// memory. The pointer is suitable for holding data described by `new_layout`. To accomplish /// this, the allocator may extend the allocation referenced by `ptr` to fit the new layout. /// - /// If this returns `Ok`, then ownership of the memory block referenced by `ptr` has been - /// transferred to this allocator. Any access to the old `ptr` is Undefined Behavior, even if the - /// allocation was grown in-place. The newly returned pointer is the only valid pointer - /// for accessing this memory now. + /// If this returns `Ok`, then the memory block referenced by `ptr` has been [*invalidated*]. + /// The old `ptr` must not be used to access the memory, even if the allocation was grown in-place. + /// The newly returned pointer is the only valid pointer for accessing this memory now. + /// All bytes past `old_layout.size()` should be assumed to be uninitialised. /// - /// If this method returns `Err`, then ownership of the memory block has not been transferred to - /// this allocator, and the contents of the memory block are unaltered. + /// If this method returns `Err`, then the memory block has not been *invalidated*, + /// and the contents of the memory block are unaltered. /// /// # Safety /// @@ -189,13 +297,14 @@ pub const unsafe trait Allocator { /// /// [*currently allocated*]: #currently-allocated-memory /// [*fit*]: #memory-fitting + /// [*invalidated*]: #invalidating-memory-blocks /// /// # Errors /// /// Returns `Err` if the new layout does not meet the allocator's size and alignment /// constraints of the allocator, or if growing otherwise fails. /// - /// Implementations are encouraged to return `Err` on memory exhaustion rather than panicking or + /// Implementations are encouraged to return `Err` on memory exhaustion rather than /// aborting, but this is not a strict requirement. (Specifically: it is *legal* to implement /// this trait atop an underlying native allocation library that aborts on memory exhaustion.) /// @@ -235,12 +344,9 @@ pub const unsafe trait Allocator { /// The memory block will contain the following contents after a successful call to /// `grow_zeroed`: /// * Bytes `0..old_layout.size()` are preserved from the original allocation. - /// * Bytes `old_layout.size()..old_size` will either be preserved or zeroed, depending on - /// the allocator implementation. `old_size` refers to the size of the memory block prior - /// to the `grow_zeroed` call, which may be larger than the size that was originally - /// requested when it was allocated. - /// * Bytes `old_size..new_size` are zeroed. `new_size` refers to the size of the memory - /// block returned by the `grow_zeroed` call. + /// * Bytes `old_layout.size()..new_size` are zeroed. `new_size` refers to the size + /// of the memory block returned by the `grow_zeroed` call, which may be larger than + /// `new_layout.size()`. /// /// # Safety /// @@ -258,7 +364,7 @@ pub const unsafe trait Allocator { /// Returns `Err` if the new layout does not meet the allocator's size and alignment /// constraints of the allocator, or if growing otherwise fails. /// - /// Implementations are encouraged to return `Err` on memory exhaustion rather than panicking or + /// Implementations are encouraged to return `Err` on memory exhaustion rather than /// aborting, but this is not a strict requirement. (Specifically: it is *legal* to implement /// this trait atop an underlying native allocation library that aborts on memory exhaustion.) /// @@ -298,13 +404,14 @@ pub const unsafe trait Allocator { /// memory. The pointer is suitable for holding data described by `new_layout`. To accomplish /// this, the allocator may shrink the allocation referenced by `ptr` to fit the new layout. /// - /// If this returns `Ok`, then ownership of the memory block referenced by `ptr` has been - /// transferred to this allocator. Any access to the old `ptr` is Undefined Behavior, even if the - /// allocation was shrunk in-place. The newly returned pointer is the only valid pointer - /// for accessing this memory now. /// - /// If this method returns `Err`, then ownership of the memory block has not been transferred to - /// this allocator, and the contents of the memory block are unaltered. + /// If this returns `Ok`, then the memory block referenced by `ptr` has been [*invalidated*]. + /// The old `ptr` must not be used to access the memory, even if the allocation was shrunk in-place. + /// The newly returned pointer is the only valid pointer for accessing this memory now. + /// All bytes past `new_layout.size()` should be assumed to be uninitialised. + /// + /// If this method returns `Err`, then the memory block has not been *invalidated*, + /// and the contents of the memory block are unaltered. /// /// # Safety /// @@ -316,13 +423,14 @@ pub const unsafe trait Allocator { /// /// [*currently allocated*]: #currently-allocated-memory /// [*fit*]: #memory-fitting + /// [*invalidated*]: #invalidating-memory-blocks /// /// # Errors /// /// Returns `Err` if the new layout does not meet the allocator's size and alignment /// constraints of the allocator, or if shrinking otherwise fails. /// - /// Implementations are encouraged to return `Err` on memory exhaustion rather than panicking or + /// Implementations are encouraged to return `Err` on memory exhaustion rather than /// aborting, but this is not a strict requirement. (Specifically: it is *legal* to implement /// this trait atop an underlying native allocation library that aborts on memory exhaustion.) /// @@ -355,22 +463,117 @@ pub const unsafe trait Allocator { Ok(new_ptr) } - - /// Creates a "by reference" adapter for this instance of `Allocator`. - /// - /// The returned adapter also implements `Allocator` and will simply borrow this. - #[inline(always)] - fn by_ref(&self) -> &Self - where - Self: Sized, - { - self - } } +/// An [`Allocator`] that can be registered as the standard library’s default +/// through the `#[global_allocator]` attribute. +/// +/// Types implementing this trait can be used as the default allocator for +/// memory allocations through `Box`, `Vec` and the collection types. For +/// instance, the `System` allocator implements this trait, and thus can be +/// explicitly set as the default like so: +/// ``` +/// use std::alloc::System; +/// +/// #[global_allocator] +/// static ALLOCATOR: System = System; +/// ``` +/// +/// The `Global` allocator forwards all memory allocation requests to the +/// `static` annotated with `#[global_allocator]`. Hence, `Global` does not +/// implement `GlobalAllocator` itself, as that would lead to infinite recursion. +/// +/// # Note to implementors +/// +/// This trait is used to prevent the infinite recursion that would occur if the +/// default allocator were to attempt to allocate memory through `Global` (and +/// thus from itself). +/// +/// When to implement this trait: +/// * for custom global allocators that only use system memory allocation +/// services. +/// * for allocators that wrap another allocator that implements `GlobalAllocator`. +/// +/// When **not** to implement this trait: +/// * for wrappers of arbitrary allocators (which might end up being `Global`, +/// leading to infinite recursion). +/// +/// # Safety +/// +/// When implementing a global allocator, one has to be careful not to create an infinitely +/// recursive implementation by accident, as many constructs in the Rust standard library may +/// allocate in their implementation. For example, on some platforms, [`std::sync::Mutex`] may +/// allocate, so using it is highly problematic in a global allocator. +/// +/// For this reason, one should generally stick to library features available through +/// [`core`], and avoid using [`std`] in a global allocator. A few features from [`std`] are +/// guaranteed to not use `#[global_allocator]` to allocate: +/// +/// - [`std::thread_local`], +/// - [`std::thread::current`], +/// - [`std::thread::park`] and [`std::thread::Thread`]'s [`unpark`] method and +/// [`Clone`] implementation. +/// +/// [`std`]: ../../std/index.html +/// [`std::sync::Mutex`]: ../../std/sync/struct.Mutex.html +/// [`std::thread_local`]: ../../std/macro.thread_local.html +/// [`std::thread::current`]: ../../std/thread/fn.current.html +/// [`std::thread::park`]: ../../std/thread/fn.park.html +/// [`std::thread::Thread`]: ../../std/thread/struct.Thread.html +/// [`unpark`]: ../../std/thread/struct.Thread.html#method.unpark +#[unstable(feature = "allocator_api", issue = "32838")] +#[expect(multiple_supertrait_upcastable)] +pub unsafe trait GlobalAllocator: StaticAllocator + Sync + 'static {} + +/// Marks a type's [`Clone`] implementation as sound with regard to [`Allocator`] equivalence. +/// Implementors must ensure that, upon cloning, the two allocators are equivalent +/// (i.e. it is possible to free memory with one that was allocated with the other). +/// Further, mutable accesses such as moving or dropping the allocator must not invalidate +/// its currently allocated blocks at least so long as clones exist. +/// +/// Additionally, the bound that allocators do not unwind when (de)allocating also applies +/// to guaranteeing allocators will not unwind when cloned. +/// +/// It must also be the case that types which are `AllocatorClone` are either explicitly not +/// copyable (such as by containing a `!Copy` field) or that copying them also respects allocator +/// equivalence as if it had been a clone. +#[unstable(feature = "allocator_api", issue = "32838")] +pub unsafe trait AllocatorClone: Allocator + Clone {} + +/// Marks that an allocator and its supertypes will never invalidate currently allocated +/// memory unless explicitly deallocated via a call to a deallocating method, even if +/// dropped or if the allocator's lifetime expires. +/// +/// This is a necessity in conjunction with [`Pin`], as only allocators that promise +/// memory is never reused without a destructor running may be used to back a pinned pointer. +/// +/// # Safety +/// +/// Implementors must ensure that memory blocks are *only, ever* invalidated by a +/// call to a de/reallocating method on `Allocator`, and that this holds true for all +/// possible instances of all subtypes of the implementor as well. +/// +/// These requirements trivially apply to allocators that always maintain global state, such as +/// `System` or `Global`. However, due to subtype coercion, it is *not* sound to implement +/// for an arbitrary `Allocator + 'static` due to [edge-case interactions][unsound] with e.g. +/// `Pin::clone`. Namely, an impl of `StaticAllocator for MyAllocator + 'long` guarantees that any +/// value of `MyAllocator + 'short` also fulfills the requirements of `StaticAllocator`. +/// +/// The following must thus be guaranteed: +/// - the `Drop` impl of the allocator does not invalidate any allocations; +/// - the allocator does not expose a safe API surface that allows invalidating +/// its allocations; +/// - the allocator's lifetime expiring does not invalidate any allocations; +/// - the above also hold for all equivalent allocators (see [`Allocator`] docs). +/// +/// [`Pin`]: ../../core/pin/struct.Pin.html +/// [unsound]: https://github.com/rust-lang/rust/issues/157089 +#[unstable(feature = "allocator_api", issue = "32838")] +pub unsafe trait StaticAllocator: Allocator {} + #[unstable(feature = "allocator_api", issue = "32838")] #[rustc_const_unstable(feature = "const_heap", issue = "79597")] -unsafe impl const Allocator for &A +const unsafe impl Allocator for &A where A: [const] Allocator + ?Sized, { @@ -425,9 +628,10 @@ where } #[unstable(feature = "allocator_api", issue = "32838")] -unsafe impl Allocator for &mut A +#[rustc_const_unstable(feature = "const_heap", issue = "79597")] +const unsafe impl Allocator for &mut A where - A: Allocator + ?Sized, + A: [const] Allocator + ?Sized, { #[inline] fn allocate(&self, layout: Layout) -> Result, AllocError> { @@ -478,3 +682,14 @@ where unsafe { (**self).shrink(ptr, old_layout, new_layout) } } } + +#[unstable(feature = "allocator_api", issue = "32838")] +unsafe impl AllocatorClone for &A {} + +// If an allocator is `StaticAllocator` all equivalent allocators must also uphold +// its semantics, and references are equivalent to the allocator they reference. +#[unstable(feature = "allocator_api", issue = "32838")] +unsafe impl StaticAllocator for &A {} + +#[unstable(feature = "allocator_api", issue = "32838")] +unsafe impl StaticAllocator for &mut A {} diff --git a/library/core/src/any.rs b/library/core/src/any.rs index 42f332f7d8ba8..85ff2fe1dd6ee 100644 --- a/library/core/src/any.rs +++ b/library/core/src/any.rs @@ -86,7 +86,10 @@ #![stable(feature = "rust1", since = "1.0.0")] -use crate::{fmt, hash, intrinsics, ptr}; +use crate::intrinsics::{self, type_id, type_id_vtable}; +use crate::mem::transmute; +use crate::mem::type_info::{TraitImpl, TypeKind}; +use crate::{fmt, hash, ptr}; /////////////////////////////////////////////////////////////////////////////// // Any trait @@ -663,7 +666,7 @@ impl dyn Any + Send + Sync { /// /// The following is an example program that tries to use `TypeId::of` to /// implement a generic type `Unique` that guarantees unique instances for each `Unique`, -/// that is, and for each type `T` there can be at most one value of type `Unique` at any time. +/// that is, for each type `T` there can be at most one value of type `Unique` at any time. /// /// ``` /// mod unique { @@ -736,33 +739,10 @@ unsafe impl Sync for TypeId {} #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq for TypeId { +const impl PartialEq for TypeId { #[inline] fn eq(&self, other: &Self) -> bool { - #[cfg(miri)] - return crate::intrinsics::type_id_eq(*self, *other); - #[cfg(not(miri))] - { - let this = self; - crate::intrinsics::const_eval_select!( - @capture { this: &TypeId, other: &TypeId } -> bool: - if const { - crate::intrinsics::type_id_eq(*this, *other) - } else { - // Ideally we would just invoke `type_id_eq` unconditionally here, - // but since we do not MIR inline intrinsics, because backends - // may want to override them (and miri does!), MIR opts do not - // clean up this call sufficiently for LLVM to turn repeated calls - // of `TypeId` comparisons against one specific `TypeId` into - // a lookup table. - // SAFETY: We know that at runtime none of the bits have provenance and all bits - // are initialized. So we can just convert the whole thing to a `u128` and compare that. - unsafe { - crate::mem::transmute::<_, u128>(*this) == crate::mem::transmute::<_, u128>(*other) - } - } - ) - } + crate::intrinsics::type_id_eq(*self, *other) } } @@ -788,7 +768,66 @@ impl TypeId { const { intrinsics::type_id::() } } - fn as_u128(self) -> u128 { + /// Checks if the [TypeId] implements the trait. If it does it returns [TraitImpl] which can be used to build a fat pointer. + /// It can only be called at compile time. `self` must be the [TypeId] of a sized type or None will be returned. + /// + /// # Examples + /// + /// ``` + /// #![feature(type_info)] + /// use std::any::{TypeId}; + /// + /// pub trait Blah {} + /// impl Blah for u8 {} + /// + /// assert!(const { TypeId::of::().trait_info_of::() }.is_some()); + /// assert!(const { TypeId::of::().trait_info_of::() }.is_none()); + /// ``` + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + #[rustc_comptime] + pub fn trait_info_of<'a, T: TryAsDynCompatible<'a> + ?Sized>(self) -> Option> { + // SAFETY: The vtable was obtained for `T`, so it is guaranteed to be `DynMetadata`. + // The intrinsic can't infer this because it is designed to work with arbitrary TypeIds. + unsafe { transmute(self.trait_info_of_trait_type_id(const { type_id::() })) } + } + + /// Checks if the [TypeId] implements the trait of `trait_represented_by_type_id`. If it does it returns [TraitImpl] which can be used to build a fat pointer. + /// It can only be called at compile time. `self` must be the [TypeId] of a sized type or None will be returned. + /// + /// # Examples + /// + /// ``` + /// #![feature(type_info)] + /// use std::any::{TypeId}; + /// + /// pub trait Blah {} + /// impl Blah for u8 {} + /// + /// assert!(const { TypeId::of::().trait_info_of_trait_type_id(TypeId::of::()) }.is_some()); + /// assert!(const { TypeId::of::().trait_info_of_trait_type_id(TypeId::of::()) }.is_none()); + /// ``` + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + #[rustc_comptime] + pub fn trait_info_of_trait_type_id( + self, + trait_represented_by_type_id: TypeId, + ) -> Option> { + if self.size().is_none() { + return None; + } + + if matches!(trait_represented_by_type_id.info().kind, TypeKind::DynTrait(_)) + && let Some(vtable) = type_id_vtable(self, trait_represented_by_type_id) + { + Some(TraitImpl { vtable }) + } else { + None + } + } + + pub(crate) fn as_u128(self) -> u128 { let mut bytes = [0; 16]; // This is a provenance-stripping memcpy. @@ -907,12 +946,72 @@ pub const fn type_name_of_val(_val: &T) -> &'static str { type_name::() } -/// Returns `Some(&U)` if `T` can be coerced to the trait object type `U`. Otherwise, it returns `None`. +/// Trait that is automatically implemented for all `dyn Trait<'b, C> + 'a` without assoc type bounds. +/// The lifetime parameter should be the same that is used to constrain generic type parameters +/// that are turned into the dyn trait constrained by `TryAsDynCompatible`. +/// +/// This is required for `try_as_dyn` to be able to soundly convert non-static +/// types to `dyn Trait`. +/// +/// Note: these requirements are sufficient for soundness, but it is unclear +/// if they are all necessary. We may be able to lift some requirements in favor +/// of more precise ones. +/// +#[unstable(feature = "try_as_dyn", issue = "144361")] +#[lang = "try_as_dyn"] +#[rustc_deny_explicit_impl] +pub trait TryAsDynCompatible<'a>: ptr::Pointee> {} + +/// Returns `Some(&U)` if `T` can be coerced to the dyn trait type `U`. Otherwise, it returns `None`. +/// +/// # Run-time failures +/// +/// There are multiple ways to get a `None`, and you need to manually analyze which one it is, as the +/// compiler does not provide any help here. +/// +/// * `T` does not implement `Trait` at all, +/// * `T`'s impl for `Trait` is not fully generic, +/// * `T`'s impl for `Trait` is a builtin impl (e.g. `dyn Debug` implements `Debug`) +/// +/// There is some detailed documentation about this feature at +/// +/// But the gist is summarized below: +/// +/// ## Lifetime-independent impls +/// +/// `try_as_dyn` does not have access to lifetime information, thus it cannot differentiate between +/// `'static`, other lifetimes, and can't reason about outlives bounds on impls. Thus we can only accept +/// impls that do not have `'static` lifetimes, or outlives bounds of any kind. You can have simple +/// trait bounds, and the compiler will transitively only use impls of those simple trait bounds that satisfy +/// the same rules as the main trait you're converting to. +/// +/// An example of a legal impl is: +/// +/// ```rust +/// # trait Trait<'a, T> {} +/// # struct Type<'b, U>(&'b U); +/// # use std::fmt::{Debug, Display}; +/// impl<'a, 'b, T: Debug, U: Display> Trait<'a, T> for Type<'b, U> {} +/// ``` +/// +/// Impls without generic parameters at all are also legal, as long as they contain no `'static` lifetimes. +/// +/// ## Builtin impls +/// +/// Builtin impls (like `impl Debug for dyn Debug`) have various obscure rules and often are not fully generic. +/// To simplify reasoning about what is allowed and what not, all builtin impls are rejected and will neither +/// directly nor indirectly contribute to a `Some` result. /// /// # Compile-time failures -/// Determining whether `T` can be coerced to the trait object type `U` requires compiler trait resolution. +/// Determining whether `T` can be coerced to the dyn trait type `U` requires compiler trait resolution. /// In some cases, that resolution can exceed the recursion limit, /// and compilation will fail instead of this function returning `None`. +/// +/// The input type `T` must outlive the lifetime `'a` on the `dyn Trait + 'a`. +/// This is basically the same rule that forbids `let x: &dyn Trait + 'static = &&some_local_variable;` +/// So if you see borrow check errors around `try_as_dyn`, think about whether a normal unsizing +/// coercion would be possible at all if you were using concrete types or had bounds on the input type. +/// /// # Examples /// /// ```rust @@ -942,18 +1041,21 @@ pub const fn type_name_of_val(_val: &T) -> &'static str { /// ``` #[must_use] #[unstable(feature = "try_as_dyn", issue = "144361")] -pub const fn try_as_dyn< - T: Any + 'static, - U: ptr::Pointee> + ?Sized + 'static, ->( +pub const fn try_as_dyn<'a, T: ?Sized + 'a, U: TryAsDynCompatible<'a> + ?Sized>( t: &T, ) -> Option<&U> { - let vtable: Option> = const { intrinsics::vtable_for::() }; + // For unsized `T`, `trait_info_of` always returns `None` (vtable lookup is + // only supported for sized types). The function therefore unconditionally + // returns `None` in that case. + let vtable: Option> = + const { type_id::().trait_info_of::().as_ref().map(TraitImpl::get_vtable) }; match vtable { Some(dyn_metadata) => { - let pointer = ptr::from_raw_parts(t, dyn_metadata); + let pointer = ptr::from_raw_parts(t as *const T as *const (), dyn_metadata); // SAFETY: `t` is a reference to a type, so we know it is valid. // `dyn_metadata` is a vtable for T, implementing the trait of `U`. + // `T` is sized here because `trait_info_of` only returns `Some` for sized types, + // so the thin data pointer fully describes the value. Some(unsafe { &*pointer }) } None => None, @@ -962,51 +1064,24 @@ pub const fn try_as_dyn< /// Returns `Some(&mut U)` if `T` can be coerced to the trait object type `U`. Otherwise, it returns `None`. /// -/// # Compile-time failures -/// Determining whether `T` can be coerced to the trait object type `U` requires compiler trait resolution. -/// In some cases, that resolution can exceed the recursion limit, -/// and compilation will fail instead of this function returning `None`. -/// # Examples -/// -/// ```rust -/// #![feature(try_as_dyn)] -/// -/// use core::any::try_as_dyn_mut; -/// -/// trait Animal { -/// fn speak(&self) -> &'static str; -/// } -/// -/// struct Dog; -/// impl Animal for Dog { -/// fn speak(&self) -> &'static str { "woof" } -/// } -/// -/// struct Rock; // does not implement Animal -/// -/// let mut dog = Dog; -/// let mut rock = Rock; -/// -/// let as_animal: Option<&mut dyn Animal> = try_as_dyn_mut::(&mut dog); -/// assert_eq!(as_animal.unwrap().speak(), "woof"); -/// -/// let not_an_animal: Option<&mut dyn Animal> = try_as_dyn_mut::(&mut rock); -/// assert!(not_an_animal.is_none()); -/// ``` +/// See documentation of [try_as_dyn] for details about the behaviour and limitations. #[must_use] #[unstable(feature = "try_as_dyn", issue = "144361")] -pub const fn try_as_dyn_mut< - T: Any + 'static, - U: ptr::Pointee> + ?Sized + 'static, ->( +pub const fn try_as_dyn_mut<'a, T: ?Sized + 'a, U: TryAsDynCompatible<'a> + ?Sized>( t: &mut T, ) -> Option<&mut U> { - let vtable: Option> = const { intrinsics::vtable_for::() }; + // For unsized `T`, `trait_info_of` always returns `None` (vtable lookup is + // only supported for sized types). The function therefore unconditionally + // returns `None` in that case. + let vtable: Option> = + const { type_id::().trait_info_of::().as_ref().map(TraitImpl::get_vtable) }; match vtable { Some(dyn_metadata) => { - let pointer = ptr::from_raw_parts_mut(t, dyn_metadata); + let pointer = ptr::from_raw_parts_mut(t as *mut T as *mut (), dyn_metadata); // SAFETY: `t` is a reference to a type, so we know it is valid. // `dyn_metadata` is a vtable for T, implementing the trait of `U`. + // `T` is sized here because `trait_info_of` only returns `Some` for sized types, + // so the thin data pointer fully describes the value. Some(unsafe { &mut *pointer }) } None => None, diff --git a/library/core/src/arch.rs b/library/core/src/arch.rs index e5078a45c6d9c..737a643ef8659 100644 --- a/library/core/src/arch.rs +++ b/library/core/src/arch.rs @@ -76,3 +76,33 @@ pub macro global_asm("assembly template", $(operands,)* $(options($(option),*))? pub fn breakpoint() { core::intrinsics::breakpoint(); } + +/// The `core::arch::return_address!()` macro returns a pointer with an address that corresponds to the caller of the function that invoked the `return_address!()` macro. +/// The pointer has no provenance, as if created by `core::ptr::without_provenance`. It cannot be used to read memory (other than ZSTs). +/// +/// The value returned by the macro depends highly on the architecture and compiler (including any options set). +/// In particular, it is allowed to be wrong (particularly if inlining is involved), or even contain a nonsense value. +/// The result of this macro must not be relied upon for soundness or correctness, only for debugging purposes. +/// +/// As a best effort, if a useful value cannot be determined (for example, due to limitations on the current codegen), +/// this macro tries to return a null pointer instead of nonsense (this cannot be relied upon for correctness, however). +/// +/// Formally, this function returns a pointer with a non-deterministic address and no provenance. +/// +/// This is equivalent to the gcc `__builtin_return_address(0)` intrinsic (other forms of the intrinsic are not supported). +/// Because the operation can be always performed by the compiler without crashing or causing undefined behaviour, invoking the macro is a safe operation. +/// +/// ## Example +/// ``` +/// #![feature(return_address)] +/// +/// # fn run_test() { +/// let addr = core::arch::return_address!(); +/// println!("Caller is {addr:p}"); +/// # } +/// # #[cfg(not(miri))] // FIXME: Figure out how to make miri work before stabilizing this macro +/// # run_test() +/// ``` +#[unstable(feature = "return_address", issue = "154966")] +#[allow_internal_unstable(core_intrinsics)] +pub macro return_address() {{ core::intrinsics::return_address() }} diff --git a/library/core/src/array/drain.rs b/library/core/src/array/drain.rs index 0a497d3943ea6..96a5a3178c11e 100644 --- a/library/core/src/array/drain.rs +++ b/library/core/src/array/drain.rs @@ -1,27 +1,23 @@ -use safety::requires; - -use crate::iter::{TrustedLen, UncheckedIterator}; -#[cfg(kani)] -use crate::kani; use crate::marker::{Destruct, PhantomData}; -use crate::mem::{ManuallyDrop, SizedTypeProperties, conjure_zst}; -use crate::ptr::{NonNull, drop_in_place, from_raw_parts_mut, null_mut}; +use crate::mem::{ManuallyDrop, SizedTypeProperties, conjure_zst, transmute}; +use crate::ptr::{NonNull, drop_in_place, from_raw_parts_mut, without_provenance_mut}; -impl<'l, 'f, T, U, const N: usize, F: FnMut(T) -> U> Drain<'l, 'f, T, N, F> { +impl<'l, 'f, T, U, F: FnMut(T) -> U> Drain<'l, 'f, T, F> { /// This function returns a function that lets you index the given array in const. /// As implemented it can optimize better than iterators, and can be constified. /// It acts like a sort of guard (owns the array) and iterator combined, which can be implemented - /// as it is a struct that implements const fn; - /// in that regard it is somewhat similar to an array::Iter implementing `UncheckedIterator`. + /// as it is a struct that implements const fn. /// The only method you're really allowed to call is `next()`, /// anything else is more or less UB, hence this function being unsafe. /// Moved elements will not be dropped. /// This will also not actually store the array. /// /// SAFETY: must only be called `N` times. Thou shalt not drop the array either. - // FIXME(const-hack): this is a hack for `let guard = Guard(array); |i| f(guard[i])`. #[rustc_const_unstable(feature = "array_try_map", issue = "79711")] - pub(super) const unsafe fn new(array: &'l mut ManuallyDrop<[T; N]>, f: &'f mut F) -> Self { + pub(super) const unsafe fn new( + array: &'l mut ManuallyDrop<[T; N]>, + f: &'f mut F, + ) -> Self { // dont drop the array, transfers "ownership" to Self let ptr: NonNull = NonNull::from_mut(array).cast(); // SAFETY: @@ -29,17 +25,17 @@ impl<'l, 'f, T, U, const N: usize, F: FnMut(T) -> U> Drain<'l, 'f, T, N, F> { // at the end of `slice`. `end` will never be dereferenced, only checked // for direct pointer equality with `ptr` to check if the drainer is done. unsafe { - let end = if T::IS_ZST { null_mut() } else { ptr.as_ptr().add(N) }; - Self { ptr, end, f, l: PhantomData } + let end_or_len = + if T::IS_ZST { without_provenance_mut(N) } else { ptr.as_ptr().add(N) }; + Self { ptr, end_or_len, f, l: PhantomData } } } } /// See [`Drain::new`]; this is our fake iterator. -#[rustc_const_unstable(feature = "array_try_map", issue = "79711")] #[unstable(feature = "array_try_map", issue = "79711")] -pub(super) struct Drain<'l, 'f, T, const N: usize, F> { - // FIXME(const-hack): This is essentially a slice::IterMut<'static>, replace when possible. +pub(super) struct Drain<'l, 'f, T, F> { + // FIXME(const-hack): This is a slice::IterMut<'l>, replace when possible. /// The pointer to the next element to return, or the past-the-end location /// if the drainer is empty. /// @@ -47,16 +43,16 @@ pub(super) struct Drain<'l, 'f, T, const N: usize, F> { /// As we "own" this array, we dont need to store any lifetime. ptr: NonNull, /// For non-ZSTs, the non-null pointer to the past-the-end element. - /// For ZSTs, this is null. - end: *mut T, + /// For ZSTs, this is the number of unprocessed items. + end_or_len: *mut T, f: &'f mut F, - l: PhantomData<&'l mut [T; N]>, + l: PhantomData<&'l mut [T]>, } #[rustc_const_unstable(feature = "array_try_map", issue = "79711")] #[unstable(feature = "array_try_map", issue = "79711")] -impl const FnOnce<(usize,)> for &mut Drain<'_, '_, T, N, F> +const impl FnOnce<(usize,)> for &mut Drain<'_, '_, T, F> where F: [const] FnMut(T) -> U, { @@ -69,7 +65,7 @@ where } #[rustc_const_unstable(feature = "array_try_map", issue = "79711")] #[unstable(feature = "array_try_map", issue = "79711")] -impl const FnMut<(usize,)> for &mut Drain<'_, '_, T, N, F> +const impl FnMut<(usize,)> for &mut Drain<'_, '_, T, F> where F: [const] FnMut(T) -> U, { @@ -79,6 +75,16 @@ where (_ /* ignore argument */,): (usize,), ) -> Self::Output { if T::IS_ZST { + #[expect(ptr_to_integer_transmute_in_consts)] + // SAFETY: + // This is equivalent to `self.end_or_len.addr`, but that's not + // available in `const`. `self.end_or_len` doesn't have provenance, + // so transmuting is fine. + let len = unsafe { transmute::<*mut T, usize>(self.end_or_len) }; + // SAFETY: + // The caller guarantees that this is never called more than N times + // (see `Drain::new`), hence this cannot underflow. + self.end_or_len = without_provenance_mut(unsafe { len.unchecked_sub(1) }); // its UB to call this more than N times, so returning more ZSTs is valid. // SAFETY: its a ZST? we conjur. (self.f)(unsafe { conjure_zst::() }) @@ -94,20 +100,32 @@ where } #[rustc_const_unstable(feature = "array_try_map", issue = "79711")] #[unstable(feature = "array_try_map", issue = "79711")] -impl const Drop for Drain<'_, '_, T, N, F> { +const impl Drop for Drain<'_, '_, T, F> { fn drop(&mut self) { - if !T::IS_ZST { + let slice = if T::IS_ZST { + from_raw_parts_mut::<[T]>( + self.ptr.as_ptr(), + #[expect(ptr_to_integer_transmute_in_consts)] + // SAFETY: + // This is equivalent to `self.end_or_len.addr`, but that's not + // available in `const`. `self.end_or_len` doesn't have provenance, + // so transmuting is fine. + unsafe { + transmute::<*mut T, usize>(self.end_or_len) + }, + ) + } else { // SAFETY: we cant read more than N elements - let slice = unsafe { + unsafe { from_raw_parts_mut::<[T]>( self.ptr.as_ptr(), // SAFETY: `start <= end` - self.end.offset_from_unsigned(self.ptr.as_ptr()), + self.end_or_len.offset_from_unsigned(self.ptr.as_ptr()), ) - }; + } + }; - // SAFETY: By the type invariant, we're allowed to drop all these. (we own it, after all) - unsafe { drop_in_place(slice) } - } + // SAFETY: By the type invariant, we're allowed to drop all these. (we own it, after all) + unsafe { drop_in_place(slice) } } } diff --git a/library/core/src/array/equality.rs b/library/core/src/array/equality.rs index ec79a657e58e2..d4692ca478388 100644 --- a/library/core/src/array/equality.rs +++ b/library/core/src/array/equality.rs @@ -2,7 +2,7 @@ use crate::cmp::BytewiseEq; #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq<[U; N]> for [T; N] +const impl PartialEq<[U; N]> for [T; N] where T: [const] PartialEq, { @@ -18,7 +18,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq<[U]> for [T; N] +const impl PartialEq<[U]> for [T; N] where T: [const] PartialEq, { @@ -40,7 +40,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq<[U; N]> for [T] +const impl PartialEq<[U; N]> for [T] where T: [const] PartialEq, { @@ -62,7 +62,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq<&[U]> for [T; N] +const impl PartialEq<&[U]> for [T; N] where T: [const] PartialEq, { @@ -78,7 +78,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq<[U; N]> for &[T] +const impl PartialEq<[U; N]> for &[T] where T: [const] PartialEq, { @@ -94,7 +94,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq<&mut [U]> for [T; N] +const impl PartialEq<&mut [U]> for [T; N] where T: [const] PartialEq, { @@ -110,7 +110,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq<[U; N]> for &mut [T] +const impl PartialEq<[U; N]> for &mut [T] where T: [const] PartialEq, { @@ -130,7 +130,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const Eq for [T; N] {} +const impl Eq for [T; N] {} #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] const trait SpecArrayEq: Sized { @@ -139,7 +139,7 @@ const trait SpecArrayEq: Sized { } #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl, Other, const N: usize> const SpecArrayEq for T { +const impl, Other, const N: usize> SpecArrayEq for T { default fn spec_eq(a: &[Self; N], b: &[Other; N]) -> bool { a[..] == b[..] } @@ -149,7 +149,7 @@ impl, Other, const N: usize> const SpecArrayEq, U, const N: usize> const SpecArrayEq for T { +const impl, U, const N: usize> SpecArrayEq for T { fn spec_eq(a: &[T; N], b: &[U; N]) -> bool { // SAFETY: Arrays are compared element-wise, and don't add any padding // between elements, so when the elements are `BytewiseEq`, we can diff --git a/library/core/src/array/iter.rs b/library/core/src/array/iter.rs index 575c6673e1565..7663e98cac8c2 100644 --- a/library/core/src/array/iter.rs +++ b/library/core/src/array/iter.rs @@ -27,15 +27,20 @@ pub struct IntoIter { impl IntoIter { #[inline] - fn unsize(&self) -> &InnerUnsized { + #[rustc_const_unstable(feature = "const_iter", issue = "92476")] + const fn unsize(&self) -> &InnerUnsized { self.inner.deref() } #[inline] - fn unsize_mut(&mut self) -> &mut InnerUnsized { + #[rustc_const_unstable(feature = "const_iter", issue = "92476")] + const fn unsize_mut(&mut self) -> &mut InnerUnsized { self.inner.deref_mut() } } +#[stable(feature = "boxed_array_value_iter", since = "1.99.0")] +impl !Iterator for [T; N] {} + // Note: the `#[rustc_skip_during_method_dispatch(array)]` on `trait IntoIterator` // hides this implementation from explicit `.into_iter()` calls on editions < 2021, // so those calls will still resolve to the slice implementation, by reference. @@ -225,7 +230,8 @@ impl IntoIter { /// Returns a mutable slice of all elements that have not been yielded yet. #[stable(feature = "array_value_iter", since = "1.51.0")] #[inline] - pub fn as_mut_slice(&mut self) -> &mut [T] { + #[rustc_const_unstable(feature = "const_iter", issue = "92476")] + pub const fn as_mut_slice(&mut self) -> &mut [T] { self.unsize_mut().as_mut_slice() } } @@ -369,8 +375,8 @@ unsafe impl TrustedLen for IntoIter {} #[doc(hidden)] #[unstable(issue = "none", feature = "std_internals")] -#[rustc_unsafe_specialization_marker] -pub trait NonDrop {} +#[unsafe(rustc_allow_lifetime_dependent_specialization)] +trait NonDrop {} // T: Copy as approximation for !Drop since get_unchecked does not advance self.alive // and thus we can't implement drop-handling diff --git a/library/core/src/array/iter/iter_inner.rs b/library/core/src/array/iter/iter_inner.rs index 3c2343591f8cf..d93cbf32c0162 100644 --- a/library/core/src/array/iter/iter_inner.rs +++ b/library/core/src/array/iter/iter_inner.rs @@ -1,9 +1,10 @@ //! Defines the `IntoIter` owned iterator for arrays. +use crate::clone::TrivialClone; use crate::mem::MaybeUninit; use crate::num::NonZero; use crate::ops::{IndexRange, NeverShortCircuit, Try}; -use crate::{fmt, iter}; +use crate::{fmt, iter, ptr}; #[allow(private_bounds)] trait PartialDrop { @@ -99,9 +100,26 @@ impl PolymorphicIter<[MaybeUninit; N]> { impl Clone for PolymorphicIter<[MaybeUninit; N]> { #[inline] fn clone(&self) -> Self { + SpecPolymorphicIterClone::::spec_clone(self) + } +} + +trait SpecPolymorphicIterClone { + fn spec_clone( + this: &PolymorphicIter<[MaybeUninit; N]>, + ) -> PolymorphicIter<[MaybeUninit; N]> + where + Self: Sized; +} + +impl SpecPolymorphicIterClone for T { + #[inline] + default fn spec_clone( + this: &PolymorphicIter<[MaybeUninit; N]>, + ) -> PolymorphicIter<[MaybeUninit; N]> { // Note, we don't really need to match the exact same alive range, so // we can just clone into offset 0 regardless of where `self` is. - let mut new = Self::empty(); + let mut new = PolymorphicIter::<[MaybeUninit; N]>::empty(); fn clone_into_new( source: &PolymorphicIter<[MaybeUninit]>, @@ -118,7 +136,33 @@ impl Clone for PolymorphicIter<[MaybeUninit; N]> { } } - clone_into_new(self, &mut new); + clone_into_new(this, &mut new); + new + } +} + +impl SpecPolymorphicIterClone for T { + #[inline] + fn spec_clone( + this: &PolymorphicIter<[MaybeUninit; N]>, + ) -> PolymorphicIter<[MaybeUninit; N]> { + // Note, we don't really need to match the exact same alive range, so + // we can just clone into offset 0 regardless of where `self` is. + let mut new = PolymorphicIter::<[MaybeUninit; N]>::empty(); + + let len = this.alive.len(); + + // SAFETY: These two allocations can not overlap since `new` is allocated + // on the stack of this function. + unsafe { + ptr::copy_nonoverlapping( + this.data.as_ptr().add(this.alive.start()), + new.data.as_mut_ptr(), + len, + ); + new.alive = IndexRange::zero_to(len); + } + new } } @@ -134,7 +178,8 @@ impl PolymorphicIter<[MaybeUninit]> { } #[inline] - pub(super) fn as_mut_slice(&mut self) -> &mut [T] { + #[rustc_const_unstable(feature = "const_iter", issue = "92476")] + pub(super) const fn as_mut_slice(&mut self) -> &mut [T] { // SAFETY: We know that all elements within `alive` are properly initialized. unsafe { let slice = self.data.get_unchecked_mut(self.alive.clone()); diff --git a/library/core/src/array/mod.rs b/library/core/src/array/mod.rs index 6cca2e6358b63..30af6450d19a9 100644 --- a/library/core/src/array/mod.rs +++ b/library/core/src/array/mod.rs @@ -11,7 +11,7 @@ use crate::convert::Infallible; use crate::error::Error; use crate::hash::{self, Hash}; use crate::intrinsics::transmute_unchecked; -use crate::iter::{UncheckedIterator, repeat_n}; +use crate::iter::{TrustedLen, repeat_n}; use crate::marker::Destruct; use crate::mem::{self, ManuallyDrop, MaybeUninit}; use crate::ops::{ @@ -52,7 +52,10 @@ pub use iter::IntoIter; #[must_use = "cloning is often expensive and is not expected to have side effects"] #[stable(feature = "array_repeat", since = "1.91.0")] pub fn repeat(val: T) -> [T; N] { - from_trusted_iterator(repeat_n(val, N)) + let mut iter = repeat_n(val, N); + // SAFETY: Unless a panic occurs, from_fn will call the closure N times, + // and repeat_n's next() will return Some for N times. + from_fn(move |_| unsafe { iter.next().unwrap_unchecked() }) } /// Creates an array where each element is produced by calling `f` with @@ -90,10 +93,8 @@ pub fn repeat(val: T) -> [T; N] { /// You can also capture things, for example to create an array full of clones /// where you can't just use `[item; N]` because it's not `Copy`: /// ``` -/// # // TBH `array::repeat` would be better for this, but it's not stable yet. -/// let my_string = String::from("Hello"); -/// let clones: [String; 42] = std::array::from_fn(|_| my_string.clone()); -/// assert!(clones.iter().all(|x| *x == my_string)); +/// let my_string: [String; 2] = std::array::from_fn(|i| format!("Hello {i}")); +/// assert_eq!(my_string, ["Hello 0", "Hello 1"]); /// ``` /// /// The array is generated in ascending index order, starting from the front @@ -194,7 +195,7 @@ impl Error for TryFromSliceError {} #[stable(feature = "try_from_slice_error", since = "1.36.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for TryFromSliceError { +const impl From for TryFromSliceError { fn from(x: Infallible) -> TryFromSliceError { match x {} } @@ -202,7 +203,7 @@ impl const From for TryFromSliceError { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef<[T]> for [T; N] { +const impl AsRef<[T]> for [T; N] { #[inline] fn as_ref(&self) -> &[T] { &self[..] @@ -211,7 +212,7 @@ impl const AsRef<[T]> for [T; N] { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsMut<[T]> for [T; N] { +const impl AsMut<[T]> for [T; N] { #[inline] fn as_mut(&mut self) -> &mut [T] { &mut self[..] @@ -220,7 +221,7 @@ impl const AsMut<[T]> for [T; N] { #[stable(feature = "array_borrow", since = "1.4.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Borrow<[T]> for [T; N] { +const impl Borrow<[T]> for [T; N] { fn borrow(&self) -> &[T] { self } @@ -228,7 +229,7 @@ impl const Borrow<[T]> for [T; N] { #[stable(feature = "array_borrow", since = "1.4.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const BorrowMut<[T]> for [T; N] { +const impl BorrowMut<[T]> for [T; N] { fn borrow_mut(&mut self) -> &mut [T] { self } @@ -248,7 +249,7 @@ impl const BorrowMut<[T]> for [T; N] { /// ``` #[stable(feature = "try_from", since = "1.34.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const TryFrom<&[T]> for [T; N] +const impl TryFrom<&[T]> for [T; N] where T: Copy, { @@ -274,7 +275,7 @@ where /// ``` #[stable(feature = "try_from_mut_slice_to_array", since = "1.59.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const TryFrom<&mut [T]> for [T; N] +const impl TryFrom<&mut [T]> for [T; N] where T: Copy, { @@ -300,7 +301,7 @@ where /// ``` #[stable(feature = "try_from", since = "1.34.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl<'a, T, const N: usize> const TryFrom<&'a [T]> for &'a [T; N] { +const impl<'a, T, const N: usize> TryFrom<&'a [T]> for &'a [T; N] { type Error = TryFromSliceError; #[inline] @@ -323,7 +324,7 @@ impl<'a, T, const N: usize> const TryFrom<&'a [T]> for &'a [T; N] { /// ``` #[stable(feature = "try_from", since = "1.34.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl<'a, T, const N: usize> const TryFrom<&'a mut [T]> for &'a mut [T; N] { +const impl<'a, T, const N: usize> TryFrom<&'a mut [T]> for &'a mut [T; N] { type Error = TryFromSliceError; #[inline] @@ -379,7 +380,7 @@ impl<'a, T, const N: usize> IntoIterator for &'a mut [T; N] { #[stable(feature = "index_trait_on_arrays", since = "1.50.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -impl const Index for [T; N] +const impl Index for [T; N] where [T]: [const] Index, { @@ -393,7 +394,7 @@ where #[stable(feature = "index_trait_on_arrays", since = "1.50.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -impl const IndexMut for [T; N] +const impl IndexMut for [T; N] where [T]: [const] IndexMut, { @@ -405,32 +406,52 @@ where /// Implements comparison of arrays [lexicographically](Ord#lexicographical-comparison). #[stable(feature = "rust1", since = "1.0.0")] -impl PartialOrd for [T; N] { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +const impl PartialOrd for [T; N] { #[inline] fn partial_cmp(&self, other: &[T; N]) -> Option { - PartialOrd::partial_cmp(&&self[..], &&other[..]) + <[T] as PartialOrd>::partial_cmp(self, other) } + #[inline] fn lt(&self, other: &[T; N]) -> bool { - PartialOrd::lt(&&self[..], &&other[..]) + <[T] as PartialOrd>::lt(self, other) } #[inline] fn le(&self, other: &[T; N]) -> bool { - PartialOrd::le(&&self[..], &&other[..]) + <[T] as PartialOrd>::le(self, other) } #[inline] fn ge(&self, other: &[T; N]) -> bool { - PartialOrd::ge(&&self[..], &&other[..]) + <[T] as PartialOrd>::ge(self, other) } #[inline] fn gt(&self, other: &[T; N]) -> bool { - PartialOrd::gt(&&self[..], &&other[..]) + <[T] as PartialOrd>::gt(self, other) + } + + #[inline] + fn __chaining_lt(&self, other: &[T; N]) -> ControlFlow { + <[T] as PartialOrd>::__chaining_lt(self, other) + } + #[inline] + fn __chaining_le(&self, other: &[T; N]) -> ControlFlow { + <[T] as PartialOrd>::__chaining_le(self, other) + } + #[inline] + fn __chaining_ge(&self, other: &[T; N]) -> ControlFlow { + <[T] as PartialOrd>::__chaining_ge(self, other) + } + #[inline] + fn __chaining_gt(&self, other: &[T; N]) -> ControlFlow { + <[T] as PartialOrd>::__chaining_gt(self, other) } } /// Implements comparison of arrays [lexicographically](Ord#lexicographical-comparison). #[stable(feature = "rust1", since = "1.0.0")] -impl Ord for [T; N] { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +const impl Ord for [T; N] { #[inline] fn cmp(&self, other: &[T; N]) -> Ordering { Ord::cmp(&&self[..], &&other[..]) @@ -464,7 +485,15 @@ trait SpecArrayClone: Clone { impl SpecArrayClone for T { #[inline] default fn clone(array: &[T; N]) -> [T; N] { - from_trusted_iterator(array.iter().cloned()) + let mut ptr: *const T = array.as_ptr(); + // SAFETY: Unless a panic occurs, from_fn will call the closure N times, + // so our pointer arithmetic will be in bounds for the N-element array. + // This works even for ZSTs, since in that case, add() is a no-op. + from_fn(move |_| unsafe { + let old = ptr; + ptr = ptr.add(1); + (&*old).clone() + }) } } @@ -516,20 +545,47 @@ impl [T; N] { /// /// # Note on performance and stack usage /// - /// Unfortunately, usages of this method are currently not always optimized - /// as well as they could be. This mainly concerns large arrays, as mapping - /// over small arrays seem to be optimized just fine. Also note that in - /// debug mode (i.e. without any optimizations), this method can use a lot - /// of stack space (a few times the size of the array or more). + /// Note that this method is *eager*. It evaluates `f` all `N` times before + /// returning the new array. + /// + /// That means that `arr.map(f).map(g)` is, in general, *not* equivalent to + /// `array.map(|x| g(f(x)))`, as the former calls `f` 4 times then `g` 4 times, + /// whereas the latter interleaves the calls (`fgfgfgfg`). + /// + /// A consequence of this is that it can have fairly-high stack usage, especially + /// in debug mode or for long arrays. The backend may be able to optimize it + /// away, but especially for complicated mappings it might not be able to. + /// + /// If you're doing a one-step `map` and really want an array as the result, + /// then absolutely use this method. Its implementation uses a bunch of tricks + /// to help the optimizer handle it well. Particularly for simple arrays, + /// like `[u8; 3]` or `[f32; 4]`, there's nothing to be concerned about. + /// + /// However, if you don't actually need an *array* of the results specifically, + /// just to process them, then you likely want [`Iterator::map`] instead. + /// + /// For example, rather than doing an array-to-array map of all the elements + /// in the array up-front and only iterating after that completes, + /// + /// ``` + /// # let my_array = [1, 2, 3]; + /// # let f = |x: i32| x + 1; + /// for x in my_array.map(f) { + /// // ... + /// } + /// ``` + /// + /// It's often better to use an iterator along the lines of /// - /// Therefore, in performance-critical code, try to avoid using this method - /// on large arrays or check the emitted code. Also try to avoid chained - /// maps (e.g. `arr.map(...).map(...)`). + /// ``` + /// # let my_array = [1, 2, 3]; + /// # let f = |x: i32| x + 1; + /// for x in my_array.into_iter().map(f) { + /// // ... + /// } + /// ``` /// - /// In many cases, you can instead use [`Iterator::map`] by calling `.iter()` - /// or `.into_iter()` on your array. `[T; N]::map` is only necessary if you - /// really need a new array of the same size as the result. Rust's lazy - /// iterators tend to get optimized very well. + /// as that's more likely to avoid large temporaries. /// /// /// # Examples @@ -850,39 +906,6 @@ impl [T; N] { } } -/// Populate an array from the first `N` elements of `iter` -/// -/// # Panics -/// -/// If the iterator doesn't actually have enough items. -/// -/// By depending on `TrustedLen`, however, we can do that check up-front (where -/// it easily optimizes away) so it doesn't impact the loop that fills the array. -#[inline] -fn from_trusted_iterator(iter: impl UncheckedIterator) -> [T; N] { - try_from_trusted_iterator(iter.map(NeverShortCircuit)).0 -} - -#[inline] -fn try_from_trusted_iterator( - iter: impl UncheckedIterator, -) -> ChangeOutputType -where - R: Try, - R::Residual: Residual<[T; N]>, -{ - assert!(iter.size_hint().0 >= N); - fn next(mut iter: impl UncheckedIterator) -> impl FnMut(usize) -> T { - move |_| { - // SAFETY: We know that `from_fn` will call this at most N times, - // and we checked to ensure that we have at least that many items. - unsafe { iter.next_unchecked() } - } - } - - try_from_fn(next(iter)) -} - /// Version of [`try_from_fn`] using a passed-in slice in order to avoid /// needing to monomorphize for every array length. /// @@ -953,7 +976,7 @@ impl Guard<'_, T> { } #[rustc_const_unstable(feature = "array_try_from_fn", issue = "89379")] -impl const Drop for Guard<'_, T> { +const impl Drop for Guard<'_, T> { #[inline] fn drop(&mut self) { debug_assert!(self.initialized <= self.array_mut.len()); @@ -964,6 +987,54 @@ impl const Drop for Guard<'_, T> { } } +/// Panic guard for incremental initialization of arrays from the back. +/// +/// Elements of the array are populated starting from the end towards the beginning. +/// Disarm the guard with `mem::forget` once the array has been fully initialized. +/// +/// # Safety +/// +/// All write accesses to this structure are unsafe and must maintain a correct +/// count of `initialized` elements. +struct GuardBack<'a, T> { + /// The array to be initialized (will be filled from the end). + pub array_mut: &'a mut [MaybeUninit], + /// The number of items that have been initialized so far. + pub initialized: usize, +} + +impl GuardBack<'_, T> { + /// Adds an item to the array and updates the initialized item counter. + /// + /// # Safety + /// + /// No more than N elements must be initialized. + #[inline] + pub(crate) unsafe fn push_unchecked(&mut self, item: T) { + // SAFETY: If `initialized` was correct before and the caller does not + // invoke this method more than N times, then writes will be in-bounds + // and slots will not be initialized more than once. + unsafe { + let offset = self.initialized.unchecked_add(1); + let index = self.array_mut.len().unchecked_sub(offset); + self.array_mut.get_unchecked_mut(index).write(item); + self.initialized = offset; + } + } +} + +impl Drop for GuardBack<'_, T> { + #[inline] + fn drop(&mut self) { + debug_assert!(self.initialized <= self.array_mut.len()); + let len = self.array_mut.len(); + // SAFETY: this slice will contain only initialized objects. + unsafe { + self.array_mut.get_unchecked_mut(len - self.initialized..len).assume_init_drop(); + } + } +} + /// Pulls `N` items from `iter` and returns them as an array. If the iterator /// yields fewer than `N` items, `Err` is returned containing an iterator over /// the already yielded items. @@ -976,33 +1047,82 @@ impl const Drop for Guard<'_, T> { /// dropped. /// /// Used for [`Iterator::next_chunk`]. +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] #[inline] -pub(crate) fn iter_next_chunk( - iter: &mut impl Iterator, +pub(crate) const fn iter_next_chunk( + iter: &mut impl [const] Iterator, ) -> Result<[T; N], IntoIter> { - let mut array = [const { MaybeUninit::uninit() }; N]; - let r = iter_next_chunk_erased(&mut array, iter); - match r { - Ok(()) => { - // SAFETY: All elements of `array` were populated. - Ok(unsafe { MaybeUninit::array_assume_init(array) }) + iter.spec_next_chunk() +} + +pub(crate) const trait SpecNextChunk: Iterator { + fn spec_next_chunk(&mut self) -> Result<[T; N], IntoIter>; +} +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] +const impl, T, const N: usize> SpecNextChunk for I { + #[inline] + default fn spec_next_chunk(&mut self) -> Result<[T; N], IntoIter> { + let mut array = [const { MaybeUninit::uninit() }; N]; + let r = iter_next_chunk_erased(&mut array, self); + match r { + Ok(()) => { + // SAFETY: All elements of `array` were populated. + Ok(unsafe { MaybeUninit::array_assume_init(array) }) + } + Err(initialized) => { + // SAFETY: Only the first `initialized` elements were populated + Err(unsafe { IntoIter::new_unchecked(array, 0..initialized) }) + } } - Err(initialized) => { - // SAFETY: Only the first `initialized` elements were populated - Err(unsafe { IntoIter::new_unchecked(array, 0..initialized) }) + } +} +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] +const impl + TrustedLen, T, const N: usize> SpecNextChunk + for I +{ + fn spec_next_chunk(&mut self) -> Result<[T; N], IntoIter> { + let len = (*self).size_hint().0; + let mut array = [const { MaybeUninit::uninit() }; N]; + if len < N { + // SAFETY: `TrustedLen`, an unsafe trait, requires that i can get len items out of it. + unsafe { write(&mut array, self, len) }; + // SAFETY: Only the first `len` elements were populated + Err(unsafe { IntoIter::new_unchecked(array, 0..len) }) + } else { + // SAFETY: `TrustedLen`, an unsafe trait, requires that i can get N items out of it. + unsafe { write(&mut array, self, N) }; + // SAFETY: All N items were populated + Ok(unsafe { MaybeUninit::array_assume_init(array) }) } } } +// SAFETY: `from` must have len items, and len items must be < N. +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] +const unsafe fn write( + to: &mut [MaybeUninit; N], + from: &mut impl [const] Iterator, + len: usize, +) { + let mut guard = Guard { array_mut: to, initialized: 0 }; + while guard.initialized < len { + // SAFETY: caller has guaranteed, from has len items. + let item = unsafe { from.next().unwrap_unchecked() }; + // SAFETY: guard.initialized < len < N + unsafe { guard.push_unchecked(item) }; + } + crate::mem::forget(guard); +} /// Version of [`iter_next_chunk`] using a passed-in slice in order to avoid /// needing to monomorphize for every array length. /// /// Unfortunately this loop has two exit conditions, the buffer filling up /// or the iterator running out of items, making it tend to optimize poorly. +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] #[inline] -fn iter_next_chunk_erased( +const fn iter_next_chunk_erased( buffer: &mut [MaybeUninit], - iter: &mut impl Iterator, + iter: &mut impl [const] Iterator, ) -> Result<(), usize> { // if `Iterator::next` panics, this guard will drop already initialized items let mut guard = Guard { array_mut: buffer, initialized: 0 }; @@ -1022,3 +1142,109 @@ fn iter_next_chunk_erased( mem::forget(guard); Ok(()) } + +/// Pulls `N` items from the back of `iter` and returns them as an array. +/// If the iterator yields fewer than `N` items, `Err` is returned containing +/// an iterator over the already yielded items. +/// +/// Since the iterator is passed as a mutable reference and this function calls +/// `next_back` at most `N` times, the iterator can still be used afterwards to +/// retrieve the remaining items. +/// +/// If `iter.next_back()` panics, all items already yielded by the iterator are +/// dropped. +/// +/// Used for [`DoubleEndedIterator::next_chunk_back`]. +#[inline] +pub(crate) fn iter_next_chunk_back( + iter: &mut impl DoubleEndedIterator, +) -> Result<[T; N], IntoIter> { + iter.spec_next_chunk_back() +} + +pub(crate) trait SpecNextChunkBack: + DoubleEndedIterator +{ + fn spec_next_chunk_back(&mut self) -> Result<[T; N], IntoIter>; +} + +impl, T, const N: usize> SpecNextChunkBack for I { + #[inline] + default fn spec_next_chunk_back(&mut self) -> Result<[T; N], IntoIter> { + let mut array = [const { MaybeUninit::uninit() }; N]; + let r = iter_next_chunk_back_erased(&mut array, self); + match r { + Ok(()) => { + // SAFETY: All elements of `array` were populated. + Ok(unsafe { MaybeUninit::array_assume_init(array) }) + } + Err(initialized) => { + // SAFETY: Only the last `initialized` elements were populated + Err(unsafe { IntoIter::new_unchecked(array, N - initialized..N) }) + } + } + } +} + +impl + TrustedLen, T, const N: usize> SpecNextChunkBack + for I +{ + fn spec_next_chunk_back(&mut self) -> Result<[T; N], IntoIter> { + let len = (*self).size_hint().0; + let mut array = [const { MaybeUninit::uninit() }; N]; + if len < N { + // SAFETY: `TrustedLen`, an unsafe trait, requires that i can get len items out of it. + unsafe { write_back(&mut array, self, len) }; + // SAFETY: Only the last `len` elements were populated + Err(unsafe { IntoIter::new_unchecked(array, N - len..N) }) + } else { + // SAFETY: `TrustedLen`, an unsafe trait, requires that i can get N items out of it. + unsafe { write_back(&mut array, self, N) }; + // SAFETY: All N items were populated + Ok(unsafe { MaybeUninit::array_assume_init(array) }) + } + } +} + +// SAFETY: `from` must have len items, and len items must be < N. +unsafe fn write_back( + to: &mut [MaybeUninit; N], + from: &mut impl DoubleEndedIterator, + len: usize, +) { + let mut guard = GuardBack { array_mut: to, initialized: 0 }; + while guard.initialized < len { + // SAFETY: caller has guaranteed, from has len items. + let item = unsafe { from.next_back().unwrap_unchecked() }; + // SAFETY: guard.initialized < len < N + unsafe { guard.push_unchecked(item) }; + } + crate::mem::forget(guard); +} + +/// Version of [`iter_next_chunk_back`] using a passed-in slice +/// in order to avoid needing to monomorphize for every array length. +/// +/// Unfortunately this loop has two exit conditions, the buffer filling up +/// or the iterator running out of items, making it tend to optimize poorly. +#[inline] +fn iter_next_chunk_back_erased( + buffer: &mut [MaybeUninit], + iter: &mut impl DoubleEndedIterator, +) -> Result<(), usize> { + // if `Iterator::next_back` panics, this guard will drop already initialized items + let mut guard = GuardBack { array_mut: buffer, initialized: 0 }; + while guard.initialized < guard.array_mut.len() { + let Some(item) = iter.next_back() else { + let initialized = guard.initialized; + mem::forget(guard); + return Err(initialized); + }; + + // SAFETY: The loop condition ensures we have space to push the item + unsafe { guard.push_unchecked(item) }; + } + + mem::forget(guard); + Ok(()) +} diff --git a/library/core/src/ascii/ascii_char.rs b/library/core/src/ascii/ascii_char.rs index f11e50d628975..9fd64c8ad723f 100644 --- a/library/core/src/ascii/ascii_char.rs +++ b/library/core/src/ascii/ascii_char.rs @@ -484,6 +484,11 @@ impl AsciiChar { #[requires(b <= 127)] #[ensures(|result| *result as u8 == b)] pub const unsafe fn from_u8_unchecked(b: u8) -> Self { + assert_unsafe_precondition!( + check_library_ub, + "`ascii::Char::from_u8_unchecked` input cannot exceed 127.", + (b: u8 = b) => b <= 127, + ); // SAFETY: Our safety precondition is that `b` is in-range. unsafe { transmute(b) } } @@ -891,7 +896,7 @@ impl AsciiChar { /// # Examples /// /// ``` - /// #![feature(ascii_char, ascii_char_variants, is_ascii_octdigit)] + /// #![feature(ascii_char, ascii_char_variants)] /// /// use std::ascii; /// @@ -962,7 +967,8 @@ impl AsciiChar { self.to_u8().is_ascii_hexdigit() } - /// Checks if the value is a punctuation character: + /// Checks if the value is a punctuation or symbol character + /// (i.e. not alphanumeric, whitespace, or control): /// /// - 0x21 ..= 0x2F `! " # $ % & ' ( ) * + , - . /`, or /// - 0x3A ..= 0x40 `: ; < = > ? @`, or @@ -1002,7 +1008,8 @@ impl AsciiChar { self.to_u8().is_ascii_punctuation() } - /// Checks if the value is a graphic character: + /// Checks if the value is a graphic character + /// (i.e. not whitespace or control): /// 0x21 '!' ..= 0x7E '~'. /// /// # Examples @@ -1055,8 +1062,8 @@ impl AsciiChar { /// before using this function. /// /// [infra-aw]: https://infra.spec.whatwg.org/#ascii-whitespace - /// [pct]: https://pubs.opengroup.org/onlinepubs/9699919799/basedefs/V1_chap07.html#tag_07_03_01 - /// [bfs]: https://pubs.opengroup.org/onlinepubs/9699919799/utilities/V3_chap02.html#tag_18_06_05 + /// [pct]: https://pubs.opengroup.org/onlinepubs/9799919799/basedefs/V1_chap07.html#tag_07_03_01 + /// [bfs]: https://pubs.opengroup.org/onlinepubs/9799919799/utilities/V3_chap02.html#tag_19_06_05 /// /// # Examples /// @@ -1171,7 +1178,7 @@ macro_rules! into_int_impl { $( #[unstable(feature = "ascii_char", issue = "110998")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] - impl const From for $ty { + const impl From for $ty { #[inline] fn from(chr: AsciiChar) -> $ty { chr as u8 as $ty diff --git a/library/core/src/async_iter/async_iter.rs b/library/core/src/async_iter/async_iter.rs index c21c08320bef6..b9e1065e48807 100644 --- a/library/core/src/async_iter/async_iter.rs +++ b/library/core/src/async_iter/async_iter.rs @@ -141,6 +141,7 @@ impl Poll> { /// Converts something into an async iterator #[unstable(feature = "async_iterator", issue = "79024")] +#[rustc_diagnostic_item = "IntoAsyncIterator"] pub trait IntoAsyncIterator { /// The type of the item yielded by the iterator type Item; diff --git a/library/core/src/attribute_docs.rs b/library/core/src/attribute_docs.rs new file mode 100644 index 0000000000000..584e1583c9bdb --- /dev/null +++ b/library/core/src/attribute_docs.rs @@ -0,0 +1,635 @@ +#[doc(attribute = "must_use")] +// +/// Warn when a value is ignored. +/// +/// The `must_use` attribute applies to values where simply creating or returning them is +/// often not enough. If a value marked with `#[must_use]` is produced and then ignored, the +/// compiler warns through the [`unused_must_use`] lint. +/// +/// This is most common on types that represent an important state or outcome. For example, +/// [`Result`] is marked `#[must_use]` because ignoring an error value can hide a failed operation. +/// In the following example, the returned [`Result`] is the only sign that writing the message +/// might have failed: +/// +/// ``` +/// # #![allow(unused_must_use)] +/// fn write_message() -> std::io::Result<()> { +/// // Write the message... +/// Ok(()) +/// } +/// +/// write_message(); +/// ``` +/// +/// Ignoring that [`Result`] triggers this warning: +/// +/// ```text +/// warning: unused `Result` that must be used +/// = note: this `Result` may be an `Err` variant, which should be handled +/// = note: `#[warn(unused_must_use)]` (part of `#[warn(unused)]`) on by default +/// help: use `let _ = ...` to ignore the resulting value +/// ``` +/// +/// Future values are also `#[must_use]`: creating a future does not run it, so ignoring one often +/// means the intended asynchronous work never happens. +/// +/// You can also place `#[must_use]` on a function, method, or trait declaration. On a function or +/// method, the warning is tied to ignoring that call's return value: +/// +/// ``` +/// # #![allow(unused_must_use)] +/// #[must_use] +/// fn make_token() -> String { +/// String::from("token") +/// } +/// +/// // Ignoring this call's return value triggers `unused_must_use`. +/// make_token(); +/// ``` +/// +/// On a trait, the warning applies when a function returns an opaque type (`impl Trait`) or trait +/// object (`dyn Trait`) whose bounds include that trait. This is how futures warn if you create one +/// but never poll or await it, since an `async fn` returns an opaque type implementing [`Future`]. +/// +/// The attribute can include a message explaining what the caller should do with the value: +/// +/// ``` +/// # #![allow(dead_code)] +/// #[must_use = "call `.finish()` to complete the operation"] +/// fn start_operation() -> Operation { +/// Operation +/// } +/// +/// struct Operation; +/// ``` +/// +/// If intentionally ignoring the value is correct, bind it to `_` or call [`drop`]: +/// +/// ``` +/// # #[must_use] +/// # fn make_token() -> String { +/// # String::from("token") +/// # } +/// let _ = make_token(); +/// drop(make_token()); +/// ``` +/// +/// The attribute is a warning tool, not a type-system rule. Code can still explicitly discard a +/// `#[must_use]` value, and the compiler does not require callers to inspect or otherwise act on +/// the value. +/// +/// For more information, see the Reference on [the `must_use` attribute]. +/// +/// [`unused_must_use`]: ../rustc/lints/listing/warn-by-default.html#unused-must-use +/// [the `must_use` attribute]: ../reference/attributes/diagnostics.html#the-must_use-attribute +const _: () = (); + +#[doc(attribute = "allow")] +// +/// The `allow` attribute suppresses lint diagnostics that would otherwise produce +/// warnings or errors. It can be used on any lint or lint group (except those +/// set to [`forbid`]). +/// +/// ``` +/// #[allow(dead_code)] +/// fn unused_function() { +/// // ... +/// } +/// +/// fn main() { +/// // `unused_function` does not generate a compiler warning. +/// } +/// ``` +/// +/// Without `#[allow(dead_code)]`, the example above would emit: +/// +/// ```text +/// warning: function `unused_function` is never used +/// --> main.rs:1:4 +/// | +/// 1 | fn unused_function() { +/// | ^^^^^^^^^^^^^^^ +/// | +/// = note: `#[warn(dead_code)]` (part of `#[warn(unused)]`) on by default +/// +/// warning: 1 warning emitted +/// ``` +/// +/// Multiple lints can be set to `allow` at once with commas: +/// +/// ``` +/// #[allow(unused_variables, unused_mut)] +/// fn main() { +/// let mut x: u32 = 42; +/// } +/// ``` +/// +/// This is mostly used to prevent lint warnings or errors while still under development. +/// +/// It cannot override a lint that has been set to [`forbid`]. +/// +/// It's also important to consider that overusing `allow` could make code harder to maintain +/// and possibly hide issues. To mitigate this issue, using the `expect` attribute is preferred. +/// +/// `allow` can be overridden by [`warn`], [`deny`], and [`forbid`]. +/// +/// The lint checks supported by rustc can be found via `rustc -W help`, +/// along with their default settings and are documented in [the `rustc` book]. +/// +/// [the `rustc` book]: ../rustc/lints/listing/index.html +/// +/// For more information, see the Reference on [the `allow` attribute]. +/// +/// [the `allow` attribute]: ../reference/attributes/diagnostics.html#lint-check-attributes +/// [`forbid`]: ./attribute.forbid.html +/// [`warn`]: ./attribute.warn.html +/// [`deny`]: ./attribute.deny.html +const _: () = (); + +#[doc(attribute = "cfg")] +// +/// Used for conditional compilation. +/// +/// The `cfg` attribute allows compiling an item under specific conditions, otherwise it +/// will be ignored. +/// +/// ``` +/// // Only compiles this function for Linux. +/// #[cfg(target_os = "linux")] +/// fn platform_specific() { +/// println!("Running on Linux"); +/// } +/// +/// // Only compiles this function if not for Linux. +/// #[cfg(not(target_os = "linux"))] +/// fn platform_specific() { +/// println!("Running on something else"); +/// } +/// ``` +/// +/// Depending on the platform you're targeting, only one of these two functions will be considered +/// during the compilation. +/// +/// Conditions can also be combined with `all(...)`, `any(...)`, and `not(...)`: +/// +/// * `all`: True if all given predicates are true. +/// * `any`: True if at least one of the given predicates is true. +/// * `not`: True if the predicate is false and false if the predicate is true. +/// +/// ``` +/// #[cfg(all(unix, target_pointer_width = "64"))] +/// fn unix_64bit() { +/// // ... +/// } +/// ``` +/// +/// If you want to use this mechanism in an [`if`] condition in your code, you +/// can use the [`cfg!`] macro. To conditionally apply an attribute, +/// see [`cfg_attr`]. +/// +/// For more information, see the Reference on [the `cfg` attribute]. +/// +/// [`cfg_attr`]: ../reference/conditional-compilation.html#the-cfg_attr-attribute +/// [the `cfg` attribute]: ../reference/conditional-compilation.html#the-cfg-attribute +/// [`if`]: ./keyword.if.html +const _: () = (); + +#[doc(attribute = "deny")] +// +/// Emits an error, preventing the compilation from finishing, when a lint check has failed. +/// This is useful for enforcing rules or preventing certain patterns: +/// +/// ```compile_fail +/// #[deny(unused)] +/// fn foo() { +/// let x = 42; // Emits an error because x is unused. +/// } +/// ``` +/// +/// `deny` can be overridden by [`allow`], [`warn`], and [`forbid`]: +/// +/// ``` +/// #![deny(unused)] +/// +/// #[allow(unused)] // We override the `deny` for this function. +/// fn foo() { +/// let x = 42; // No lint emitted even though `x` is unused. +/// } +/// ``` +/// +/// Multiple lints can also be set to `deny` at once: +/// +/// ```compile_fail +/// #![deny(unused_imports, unused_variables)] +/// use std::collections::*; +/// +/// fn main() { +/// let mut x = 10; +/// } +/// ``` +/// +/// The lint checks supported by rustc can be found via `rustc -W help`, +/// along with their default settings and are documented in [the `rustc` book]. +/// +/// [the `rustc` book]: ../rustc/lints/listing/index.html +/// +/// For more information, see the Reference on [the `deny` attribute]. +/// +/// [the `deny` attribute]: ../reference/attributes/diagnostics.html#lint-check-attributes +/// [`forbid`]: ./attribute.forbid.html +/// [`allow`]: ./attribute.allow.html +/// [`warn`]: ./attribute.warn.html +/// [`deny`]: ./attribute.deny.html +const _: () = (); + +#[doc(attribute = "forbid")] +// +/// Emits an error, preventing the compilation from finishing, when a lint check has failed. +/// +/// A lint set to `forbid` cannot be overridden by [`allow`] or [`warn`]. +/// Attempting either will result in a compilation error. Writing `#[deny(...)]` on the same lint inside a +/// `forbid` scope is permitted, but has no effect; the lint remains at the `forbid` level. +/// +/// This is useful for enforcing strict policies that should not be relaxed +/// anywhere in the codebase. Example: +/// +/// ``` +/// #![forbid(unsafe_code)] +/// +/// // This would cause a compilation error if uncommented: +/// // #[allow(unsafe_code)] // error: cannot override `forbid` +/// ``` +/// +/// Multiple lints can be set to `forbid` at once: +/// +/// ``` +/// #![forbid(unsafe_code, unused)] +/// ``` +/// +/// The lint checks supported by rustc can be found via `rustc -W help`, +/// along with their default settings and are documented in [the `rustc` book]. +/// +/// [the `rustc` book]: ../rustc/lints/listing/index.html +/// +/// For more information, see the Reference on [the `forbid` attribute]. +/// +/// [the `forbid` attribute]: ../reference/attributes/diagnostics.html#lint-check-attributes +/// [`allow`]: ./attribute.allow.html +/// [`warn`]: ./attribute.warn.html +const _: () = (); + +#[doc(attribute = "deprecated")] +// +/// Emits a warning during compilation when an item with this attribute is used. +/// `since` and `note` are optional fields giving more detail about why the item is deprecated. +/// +/// * `since`: the version since when the item is deprecated. +/// * `note`: the reason why an item is deprecated. +/// +/// Example: +/// +/// ``` +/// #[deprecated(since = "1.0.0", note = "Use bar instead")] +/// struct Foo; +/// struct Bar; +/// ``` +/// +/// The `deprecated` attribute helps developers transition away from old code by providing warnings +/// when deprecated items are used. Note that during `Cargo` builds, warnings on dependencies get +/// silenced by default, so you may not see a deprecation warning unless you build that dependency +/// directly. +/// +/// For more information, see the Reference on [the `deprecated` attribute]. +/// +/// [the `deprecated` attribute]: ../reference/attributes/diagnostics.html#the-deprecated-attribute +const _: () = (); + +#[doc(attribute = "warn")] +// +/// Emits a warning during compilation when a lint check failed. +/// +/// Unlike [`deny`] or [`forbid`], `warn` does not produce a hard error: the compilation +/// continues, but the compiler emits a warning message. `warn` can be overridden by [`allow`], +/// [`deny`], and [`forbid`]. +/// +/// Example: +/// +/// ```compile_fail +/// #![allow(unused)] +/// +/// #[warn(unused)] // We override the allowed `unused` lint. +/// fn foo() { +/// // This lint warns by default even without #[warn(unused)] being explicitly set +/// let x = 42; // warning: unused variable `x` +/// } +/// ``` +/// +/// +/// Many lints, including `unused`, are already set to `warn` by default so this attribute is +/// mainly useful for lints that are normally [`allow`] by default. +/// +/// Multiple lints can be set to `warn` at once: +/// +/// ```compile_fail +/// #[warn(unused_mut, unused_variables)] +/// fn main() { +/// let mut x = 42; +/// } +/// ``` +/// +/// The lint checks supported by rustc can be found via `rustc -W help`, +/// along with their default settings and are documented in [the `rustc` book]. +/// +/// [the `rustc` book]: ../rustc/lints/listing/index.html +/// +/// For more information, see the Reference on [the `warn` attribute]. +/// +/// [the `warn` attribute]: ../reference/attributes/diagnostics.html#lint-check-attributes +/// [`allow`]: ./attribute.allow.html +/// [`deny`]: ./attribute.deny.html +/// [`forbid`]: ./attribute.forbid.html +const _: () = (); + +#[doc(attribute = "no_std")] +// +/// Prevents automatically linking the standard library. +/// +/// Written as an inner attribute at the top of the crate root, the `no_std` attribute stops +/// the compiler from linking [`std`] into the crate, and only links [`core`]. +/// +/// The attribute also swaps which prelude gets inserted, with the [`core`] prelude replacing +/// the [`std`] prelude. Items like [`Option`], [`Result`], and the primitive types remain +/// available from [`core`] without any imports needed: +/// +/// ```rust,ignore (no_std) +/// #![no_std] +/// +/// fn halve(x: u32) -> Option { +/// if x % 2 == 0 { Some(x / 2) } else { None } +/// } +/// ``` +/// +/// Anything that requires heap memory allocations is not part of [`core`]. Linking the [`alloc`] +/// crate explicitly can be used to include these types: +/// +/// ```rust,ignore (no_std + needs a global allocator to link) +/// #![no_std] +/// +/// extern crate alloc; +/// +/// use alloc::vec::Vec; +/// ``` +/// +/// A `no_std` binary also removes the startup routine and default panic handler `std` +/// normally provides. It must define its own `#[panic_handler]`, and typically its own +/// entry point by additionally using `#![no_main]`: +/// +/// ```rust,ignore (no_std + needs more than no_main alone to link) +/// #![no_std] +/// #![no_main] +/// +/// use core::panic::PanicInfo; +/// +/// #[panic_handler] +/// fn on_panic(_info: &PanicInfo) -> ! { +/// loop {} +/// } +/// ``` +/// +/// For more information, see the Reference on [the `no_std` attribute]. +/// +/// [`std`]: ../std/index.html +/// [`core`]: ../core/index.html +/// [`alloc`]: ../alloc/index.html +/// [`Option`]: option::Option +/// [`Result`]: result::Result +/// [the `no_std` attribute]: ../reference/names/preludes.html#the-no_std-attribute +const _: () = (); + +#[doc(attribute = "inline")] +// +/// Suggest that the compiler inline a function at its call sites. +/// +/// Inlining replaces a call with a copy of the called function's body, which can remove the +/// overhead of the call. The `inline` attribute is only a hint: the compiler may ignore it, and +/// it already inlines functions on its own when that looks worthwhile. Poor choices about what to +/// inline can make a program larger or slower. +/// +/// Where it does matter is inlining across crate boundaries. A non-generic function is not +/// normally inlined into another crate, since the calling crate compiles against only its +/// signature. Marking it `#[inline]` makes the body available to other crates so they can inline +/// it too: +/// +/// ```rust +/// # #![allow(dead_code)] +/// #[inline] +/// pub fn square(x: i32) -> i32 { +/// x * x +/// } +/// ``` +/// +/// Generic functions do not need this. They are instantiated in each crate that uses them, so +/// their bodies are already available to inline. +/// +/// The attribute applies to functions and has three forms: +/// +/// - `#[inline]` suggests inlining the function. +/// - `#[inline(always)]` suggests inlining it at every call site. +/// - `#[inline(never)]` suggests never inlining it. +/// +/// You should almost never need `#[inline(always)]`: prefer to let the compiler decide unless +/// profiling shows a small, hot function that benefits from it. `#[inline(never)]` is useful to +/// keep a rarely used path, such as a function that only reports an error, out of its caller. +/// +/// For more information, see the Reference on [the `inline` attribute]. +/// +/// [the `inline` attribute]: ../reference/attributes/codegen.html#the-inline-attribute +const _: () = (); + +#[doc(attribute = "cold")] +// +/// Hint to the compiler that a function is unlikely to be called. +/// +/// Marking a function `#[cold]` tells the compiler that calls to it are rare, so it can +/// optimize for the common case where the function is not called. It is only a hint: the +/// compiler may ignore it, and it does not change the function's behavior. +/// +/// It is typically used on functions that handle uncommon cases, such as error or panic paths: +/// +/// ```rust +/// # #![allow(dead_code)] +/// fn check(value: i32) { +/// if value < 0 { +/// report_error("value must be non-negative"); +/// } +/// // ... the common case continues here ... +/// } +/// +/// #[cold] +/// fn report_error(message: &str) { +/// eprintln!("error: {message}"); +/// } +/// ``` +/// +/// For more information, see the Reference on [the `cold` attribute]. +/// +/// [the `cold` attribute]: ../reference/attributes/codegen.html#the-cold-attribute +const _: () = (); + +#[doc(attribute = "track_caller")] +// +/// Make a function report the location of its caller instead of its own. +/// +/// When a function panics, the panic message normally points at the line inside that function +/// where the panic happened. `#[track_caller]` changes that: it lets the function see the +/// [`Location`] it was called from, so the panic (and any direct use of [`Location::caller`]) +/// points at the call site instead. The standard library uses this on methods like +/// [`Option::unwrap`], so a failed `unwrap` blames the line that called it rather than a line +/// inside the standard library. +/// +/// ```rust,should_panic +/// #[track_caller] +/// fn assert_even(n: i32) { +/// assert!(n % 2 == 0, "{n} is not even"); +/// } +/// +/// // The panic blames this line, not the `assert!` inside `assert_even`. +/// assert_even(3); +/// ``` +/// +/// The attribute applies to functions with the default `"Rust"` ABI, other than `fn main`. +/// +/// For more information, see the Reference on [the `track_caller` attribute]. +/// +/// [`Location`]: panic::Location +/// [`Location::caller`]: panic::Location::caller +/// [`Option::unwrap`]: Option::unwrap +/// [the `track_caller` attribute]: ../reference/attributes/codegen.html#the-track_caller-attribute +const _: () = (); + +#[doc(attribute = "proc_macro")] +// +/// Defines a function-like procedural macro. +/// +/// Applied to a `pub` function at the root of a proc-macro crate, `proc_macro` makes that function usable as a macro invoked as +/// `foo!(...)` in other crates. The function receives the tokens written inside the invocation as a [`TokenStream`] and returns +/// the [`TokenStream`] that replaces the invocation: +/// +/// ```rust, ignore (requires depending on the proc-macro crate) +/// # extern crate proc_macro; +/// use proc_macro::TokenStream; +/// +/// #[proc_macro] +/// pub fn foo(input: TokenStream) -> TokenStream { +/// "fn answer() -> u32 { 67 }".parse().unwrap() +/// } +/// ``` +/// +/// The macro can only be invoked from other crates, not from the crate where it is defined: +/// +/// ```rust,ignore (requires depending on the proc-macro crate) +/// use my_macro_crate::foo; +/// +/// // Expands to `fn answer() -> u32 { 67 }`. +/// foo!(); +/// +/// fn main() { +/// println!("{}", answer()); // Prints 67 +/// } +/// ``` +/// +/// The attribute is only usable with crates of the `proc-macro` crate type, which is set in the crate's `Cargo.toml` +/// with `proc-macro = true` in the `[lib]` section. Using it anywhere else is a compilation error: +/// +/// ```text +///error: the `#[proc_macro]` attribute is only usable with crates of the `proc-macro` crate type +/// --> src/lib.rs:4:1 +/// | +/// 4| #[proc_macro] +/// | ^^^^^^^^^^^^ +/// ``` +/// +/// For more information, see the Reference on [function-like procedural macros] and the [`proc_macro`] crate documentation. +/// +/// [`TokenStream`]: ../proc_macro/struct.TokenStream.html +/// [function-like procedural macros]: ../reference/procedural-macros.html#the-proc_macro-attribute +/// [`proc_macro`]: ../proc_macro/index.html +const _: () = (); + +#[doc(attribute = "link_section")] +// +/// Places a function or static in a specific object-file section. +/// +/// The `link_section` attribute specifies the section of the generated object file where a +/// function or static is placed. Section names and their meaning are target-specific. +/// +/// ```rust,no_run +/// # #[cfg(target_os = "linux")] { +/// #[unsafe(link_section = ".example_section")] +/// pub static VALUE: u32 = 42; +/// # } +/// ``` +/// +/// Incorrectly placing code or data in a section can violate requirements imposed by the target, +/// linker, or runtime. For example, placing mutable data in a read-only section may result in +/// undefined behavior. For this reason, `link_section` is an unsafe attribute. +/// +/// Starting with the 2024 edition, the attribute must be written using the `unsafe(...)` syntax. +/// Earlier editions also permit `#[link_section = "..."]`. +/// +/// For more information, see the Reference on [the `link_section` attribute]. +/// +/// [the `link_section` attribute]: ../reference/abi.html#the-link_section-attribute +const _: () = (); + +#[doc(attribute = "non_exhaustive")] +// +/// Indicates that a type might have more fields or variants added in the future. +/// +/// Placing `#[non_exhaustive]` on a struct or enum tells code in other crates not to assume +/// the definition is complete. This lets a library add new fields or variants without breaking +/// existing code. +/// +/// On an enum, code outside the defining crate must include a wildcard arm when matching: +/// +/// ```rust,ignore (cross-crate effect only) +/// // in crate `errors`: +/// #[non_exhaustive] +/// pub enum ConnectionError { +/// Refused, +/// Timeout, +/// } +/// +/// // in another crate: +/// use errors::ConnectionError; +/// +/// match error { +/// ConnectionError::Refused => println!("connection refused"), +/// ConnectionError::Timeout => println!("timed out"), +/// _ => println!("other error"), // required because of #[non_exhaustive] +/// } +/// ``` +/// +/// On a struct, code outside the defining crate cannot construct instances using struct literal +/// syntax: +/// +/// ```rust,ignore (cross-crate effect only) +/// // in crate `config`: +/// #[non_exhaustive] +/// pub struct Config { +/// pub width: u32, +/// pub height: u32, +/// } +/// +/// // in another crate: +/// use config::Config; +/// +/// let c = Config { width: 800, height: 600 }; // ERROR: cannot construct +/// ``` +/// +/// Inside the defining crate, exhaustive matching and direct construction are still allowed. +/// +/// For more information, see the Reference on [the `non_exhaustive` attribute]. +/// +/// [the `non_exhaustive` attribute]: ../reference/attributes/type_system.html#the-non_exhaustive-attribute +const _: () = (); diff --git a/library/core/src/autodiff.md b/library/core/src/autodiff.md new file mode 100644 index 0000000000000..847ed8b3ef324 --- /dev/null +++ b/library/core/src/autodiff.md @@ -0,0 +1,157 @@ +This module provides support for automatic differentiation. For precise information on +differences between the `autodiff_forward` and `autodiff_reverse` macros and how to +use them, see their respective documentation. + +## General usage + +Autodiff macros can be applied to almost all function definitions, see below for examples. +They can be applied to functions accepting structs, arrays, slices, vectors, tuples, and more. + +It is possible to apply multiple autodiff macros to the same function. As an example, this can +be helpful to compute the partial derivatives with respect to `x` and `y` independently: +```rust,ignore (optional component) +#[autodiff_forward(dsquare1, Dual, Const, Dual)] +#[autodiff_forward(dsquare2, Const, Dual, Dual)] +#[autodiff_forward(dsquare3, Active, Active, Active)] +fn square(x: f64, y: f64) -> f64 { + x * x + 2.0 * y +} +``` + +We also support autodiff on functions with generic parameters: +```rust,ignore (optional component) +#[autodiff_forward(generic_derivative, Duplicated, Active)] +fn generic_f + Copy>(x: &T) -> T { + x * x +} +``` + +or applying autodiff to nested functions: +```rust,ignore (optional component) +fn outer(x: f64) -> f64 { + #[autodiff_forward(inner_derivative, Dual, Const)] + fn inner(y: f64) -> f64 { + y * y + } + inner_derivative(x, 1.0) +} + +fn main() { + assert_eq!(outer(3.14), 6.28); +} +``` +The generated function will be available in the same scope as the function differentiated, and +have the same private/pub usability. + +## Traits and impls +Autodiff macros can be used in multiple ways in combination with traits: +```rust,ignore (optional component) +struct Foo { + a: f64, +} + +trait MyTrait { + #[autodiff_reverse(df, Const, Active, Active)] + fn f(&self, x: f64) -> f64; +} + +impl MyTrait for Foo { + fn f(&self, x: f64) -> f64 { + x.sin() + } +} + +fn main() { + let foo = Foo { a: 3.0f64 }; + assert_eq!(foo.f(2.0), 2.0_f64.sin()); + assert_eq!(foo.df(2.0, 1.0).1, 2.0_f64.cos()); +} +``` +In this case `df` will be the default implementation provided by the library who provided the +trait. A user implementing `MyTrait` could then decide to use the default implementation of +`df`, or overwrite it with a custom implementation as a form of "custom derivatives". + +On the other hand, a function generated by either autodiff macro can also be used to implement a +trait: +```rust,ignore (optional component) +struct Foo { + a: f64, +} + +trait MyTrait { + fn f(&self, x: f64) -> f64; + fn df(&self, x: f64, seed: f64) -> (f64, f64); +} + +impl MyTrait for Foo { + #[autodiff_reverse(df, Const, Active, Active)] + fn f(&self, x: f64) -> f64 { + self.a * 0.25 * (x * x - 1.0 - 2.0 * x.ln()) + } +} +``` + +Simple `impl` blocks without traits are also supported. Differentiating with respect to the +implemented struct will then require the use of a "shadow struct" to hold the derivatives of the +struct fields: + +```rust,ignore (optional component) +struct OptProblem { + a: f64, + b: f64, +} + +impl OptProblem { + #[autodiff_reverse(d_objective, Duplicated, Duplicated, Duplicated)] + fn objective(&self, x: &[f64], out: &mut f64) { + *out = self.a + x[0].sqrt() * self.b + } +} +fn main() { + let p = OptProblem { a: 1., b: 2. }; + let mut p_shadow = OptProblem { a: 0., b: 0. }; + let mut dx = [0.0]; + let mut out = 0.0; + let mut dout = 1.0; + + p.d_objective(&mut p_shadow, &x, &mut dx, &mut out, &mut dout); +} +``` + +## Higher-order derivatives +Finally, it is possible to generate higher-order derivatives (e.g. Hessian) by applying an +autodiff macro to a function that is already generated by an autodiff macro, via a thin wrapper. +The following example uses Forward mode over Reverse mode + +```rust,ignore (optional component) +#[autodiff_reverse(df, Duplicated, Duplicated)] +fn f(x: &[f64;2], y: &mut f64) { + *y = x[0] * x[0] + x[1] * x[0] +} + +#[autodiff_forward(h, Dual, Dual, Dual, Dual)] +fn wrapper(x: &[f64;2], dx: &mut [f64;2], y: &mut f64, dy: &mut f64) { + df(x, dx, y, dy); +} + +fn main() { + let mut y = 0.0; + let x = [2.0, 2.0]; + + let mut dy = 0.0; + let mut dx = [1.0, 0.0]; + + let mut bx = [0.0, 0.0]; + let mut by = 1.0; + let mut dbx = [0.0, 0.0]; + let mut dby = 0.0; + h(&x, &mut dx, &mut bx, &mut dbx, &mut y, &mut dy, &mut by, &mut dby); + assert_eq!(&dbx, [2.0, 1.0]); +} +``` + +## Current limitations: + +- Differentiating a function which accepts a `dyn Trait` is currently not supported. +- Builds without `lto="fat"` are not yet supported. +- Builds in debug mode are currently more likely to fail compilation. diff --git a/library/core/src/bool.rs b/library/core/src/bool.rs index 9b9d2f02550bd..7a2823baaae0f 100644 --- a/library/core/src/bool.rs +++ b/library/core/src/bool.rs @@ -78,15 +78,11 @@ impl bool { /// # Examples /// /// ``` - /// #![feature(bool_to_result)] - /// /// assert_eq!(false.ok_or(0), Err(0)); /// assert_eq!(true.ok_or(0), Ok(())); /// ``` /// /// ``` - /// #![feature(bool_to_result)] - /// /// let mut a = 0; /// let mut function_with_side_effects = || { a += 1; }; /// @@ -97,7 +93,7 @@ impl bool { /// // evaluated eagerly. /// assert_eq!(a, 2); /// ``` - #[unstable(feature = "bool_to_result", issue = "142748")] + #[stable(feature = "bool_to_result", since = "1.98.0")] #[rustc_const_unstable(feature = "const_bool", issue = "151531")] #[inline] pub const fn ok_or(self, err: E) -> Result<(), E> { @@ -110,15 +106,11 @@ impl bool { /// # Examples /// /// ``` - /// #![feature(bool_to_result)] - /// /// assert_eq!(false.ok_or_else(|| 0), Err(0)); /// assert_eq!(true.ok_or_else(|| 0), Ok(())); /// ``` /// /// ``` - /// #![feature(bool_to_result)] - /// /// let mut a = 0; /// /// assert!(true.ok_or_else(|| { a += 1; }).is_ok()); @@ -128,7 +120,7 @@ impl bool { /// // `ok_or_else`. /// assert_eq!(a, 1); /// ``` - #[unstable(feature = "bool_to_result", issue = "142748")] + #[stable(feature = "bool_to_result", since = "1.98.0")] #[rustc_const_unstable(feature = "const_bool", issue = "151531")] #[inline] pub const fn ok_or_else E + [const] Destruct>( @@ -137,4 +129,32 @@ impl bool { ) -> Result<(), E> { if self { Ok(()) } else { Err(f()) } } + + /// Toggles `self` in-place. + /// + /// - If `self` is [`true`], sets `self` to [`false`]. + /// - If `self` is [`false`], sets `self` to [`true`]. + /// + /// Equivalent to `value = !value`. + /// + /// # Examples + /// + /// ``` + /// #![feature(bool_toggle)] + /// let mut boolean = false; + /// + /// boolean.toggle(); + /// assert_eq!(boolean, true); + /// + /// boolean.toggle(); + /// assert_eq!(boolean, false); + /// ``` + /// + /// [`true`]: ../std/keyword.true.html + /// [`false`]: ../std/keyword.false.html + #[unstable(feature = "bool_toggle", issue = "159298")] + #[inline] + pub const fn toggle(&mut self) { + *self = !*self; + } } diff --git a/library/core/src/borrow.rs b/library/core/src/borrow.rs index eb4562bda4ce3..fe844e32c7e0f 100644 --- a/library/core/src/borrow.rs +++ b/library/core/src/borrow.rs @@ -209,7 +209,7 @@ pub const trait BorrowMut: [const] Borrow { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Borrow for T { +const impl Borrow for T { #[rustc_diagnostic_item = "noop_method_borrow"] fn borrow(&self) -> &T { self @@ -218,7 +218,7 @@ impl const Borrow for T { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const BorrowMut for T { +const impl BorrowMut for T { fn borrow_mut(&mut self) -> &mut T { self } @@ -226,7 +226,7 @@ impl const BorrowMut for T { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Borrow for &T { +const impl Borrow for &T { fn borrow(&self) -> &T { self } @@ -234,7 +234,7 @@ impl const Borrow for &T { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Borrow for &mut T { +const impl Borrow for &mut T { fn borrow(&self) -> &T { self } @@ -242,7 +242,7 @@ impl const Borrow for &mut T { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const BorrowMut for &mut T { +const impl BorrowMut for &mut T { fn borrow_mut(&mut self) -> &mut T { self } diff --git a/library/core/src/bstr/mod.rs b/library/core/src/bstr/mod.rs index 34e1ea66c99ad..0530ddc292a99 100644 --- a/library/core/src/bstr/mod.rs +++ b/library/core/src/bstr/mod.rs @@ -6,7 +6,7 @@ mod traits; pub use traits::{impl_partial_eq, impl_partial_eq_n, impl_partial_eq_ord}; use crate::borrow::{Borrow, BorrowMut}; -use crate::fmt; +use crate::fmt::{self, Alignment}; use crate::ops::{Deref, DerefMut, DerefPure}; /// A wrapper for `&[u8]` representing a human-readable string that's conventionally, but not @@ -38,6 +38,7 @@ use crate::ops::{Deref, DerefMut, DerefPure}; /// The `Display` implementation behaves as if the `ByteStr` were first lossily converted to a /// `str`, with invalid UTF-8 presented as the Unicode replacement character (�). #[unstable(feature = "bstr", issue = "134915")] +#[rustc_has_incoherent_inherent_impls] #[repr(transparent)] #[doc(alias = "BStr")] pub struct ByteStr(pub [u8]); @@ -131,7 +132,7 @@ impl ByteStr { #[unstable(feature = "bstr", issue = "134915")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Deref for ByteStr { +const impl Deref for ByteStr { type Target = [u8]; #[inline] @@ -142,7 +143,7 @@ impl const Deref for ByteStr { #[unstable(feature = "bstr", issue = "134915")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const DerefMut for ByteStr { +const impl DerefMut for ByteStr { #[inline] fn deref_mut(&mut self) -> &mut [u8] { &mut self.0 @@ -171,53 +172,94 @@ impl fmt::Debug for ByteStr { } } -#[unstable(feature = "bstr", issue = "134915")] +#[unstable(feature = "bstr_to_string", issue = "134915")] impl fmt::Display for ByteStr { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - fn fmt_nopad(this: &ByteStr, f: &mut fmt::Formatter<'_>) -> fmt::Result { - for chunk in this.utf8_chunks() { + fn emit(byte_str: &ByteStr, f: &mut fmt::Formatter<'_>) -> fmt::Result { + for chunk in byte_str.utf8_chunks() { f.write_str(chunk.valid())?; if !chunk.invalid().is_empty() { f.write_str("\u{FFFD}")?; } } + Ok(()) } - let Some(align) = f.align() else { - return fmt_nopad(self, f); - }; - let nchars: usize = self - .utf8_chunks() - .map(|chunk| { - chunk.valid().chars().count() + if chunk.invalid().is_empty() { 0 } else { 1 } - }) - .sum(); - let padding = f.width().unwrap_or(0).saturating_sub(nchars); - let fill = f.fill(); - let (lpad, rpad) = match align { - fmt::Alignment::Left => (0, padding), - fmt::Alignment::Right => (padding, 0), - fmt::Alignment::Center => { - let half = padding / 2; - (half, half + padding % 2) + let requested_width = f.width().unwrap_or(0); + if requested_width == 0 && f.precision().is_none() { + // Avoid counting the characters if no truncation or padding was + // requested. + return emit(self, f); + } + + let (truncated, actual_width) = match f.precision() { + // The entire string is truncated away. Weird, but ok. + Some(0) => (ByteStr::new(&[]), 0), + // Advance through string until we run out of space. + Some(precision) => { + let mut remaining_width = precision; + let mut chunks = self.utf8_chunks(); + let mut current_width = 0; + let mut offset = 0; + loop { + let Some(chunk) = chunks.next() else { + // We reached the end of the string without running out + // of space, so print the entire string. + break (self, current_width); + }; + + let mut chars = chunk.valid().char_indices(); + let Err(remaining) = chars.advance_by(remaining_width) else { + // We've counted off `precision` characters, so truncate + // the string at the current offset. + break (&self[..offset + chars.offset()], precision); + }; + + offset += chunk.valid().len(); + current_width += remaining_width - remaining.get(); + remaining_width = remaining.get(); + + // `remaining_width` cannot be zero, there is still space + // remaining. So next, count the � character emitted for + // the invalid chunk (if it exists). + if !chunk.invalid().is_empty() { + offset += chunk.invalid().len(); + current_width += 1; + remaining_width -= 1; + + if remaining_width == 0 { + break (&self[..offset], precision); + } + } + } + } + // The string shouldn't be truncated at all, so just count the number + // of characters to calculate the padding. + None => { + let actual_width = self + .utf8_chunks() + .map(|chunk| { + chunk.valid().chars().count() + + if chunk.invalid().is_empty() { 0 } else { 1 } + }) + .sum(); + (self, actual_width) } }; - for _ in 0..lpad { - write!(f, "{fill}")?; - } - fmt_nopad(self, f)?; - for _ in 0..rpad { - write!(f, "{fill}")?; - } - Ok(()) + // The width is originally stored as a 16-bit number, so this cannot fail. + let padding = u16::try_from(requested_width.saturating_sub(actual_width)).unwrap(); + + let post_padding = f.padding(padding, Alignment::Left)?; + emit(truncated, f)?; + post_padding.write(f) } } #[unstable(feature = "bstr", issue = "134915")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef<[u8]> for ByteStr { +const impl AsRef<[u8]> for ByteStr { #[inline] fn as_ref(&self) -> &[u8] { &self.0 @@ -226,7 +268,7 @@ impl const AsRef<[u8]> for ByteStr { #[unstable(feature = "bstr", issue = "134915")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef for ByteStr { +const impl AsRef for ByteStr { #[inline] fn as_ref(&self) -> &ByteStr { self @@ -237,7 +279,7 @@ impl const AsRef for ByteStr { #[unstable(feature = "bstr", issue = "134915")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef for str { +const impl AsRef for str { #[inline] fn as_ref(&self) -> &ByteStr { ByteStr::new(self) @@ -246,7 +288,7 @@ impl const AsRef for str { #[unstable(feature = "bstr", issue = "134915")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsMut<[u8]> for ByteStr { +const impl AsMut<[u8]> for ByteStr { #[inline] fn as_mut(&mut self) -> &mut [u8] { &mut self.0 @@ -261,7 +303,7 @@ impl const AsMut<[u8]> for ByteStr { #[unstable(feature = "bstr", issue = "134915")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Borrow<[u8]> for ByteStr { +const impl Borrow<[u8]> for ByteStr { #[inline] fn borrow(&self) -> &[u8] { &self.0 @@ -272,7 +314,7 @@ impl const Borrow<[u8]> for ByteStr { #[unstable(feature = "bstr", issue = "134915")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const BorrowMut<[u8]> for ByteStr { +const impl BorrowMut<[u8]> for ByteStr { #[inline] fn borrow_mut(&mut self) -> &mut [u8] { &mut self.0 @@ -341,7 +383,7 @@ impl<'a> Default for &'a mut ByteStr { #[unstable(feature = "bstr", issue = "134915")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl<'a> const TryFrom<&'a ByteStr> for &'a str { +const impl<'a> TryFrom<&'a ByteStr> for &'a str { type Error = crate::str::Utf8Error; #[inline] @@ -352,7 +394,7 @@ impl<'a> const TryFrom<&'a ByteStr> for &'a str { #[unstable(feature = "bstr", issue = "134915")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl<'a> const TryFrom<&'a mut ByteStr> for &'a mut str { +const impl<'a> TryFrom<&'a mut ByteStr> for &'a mut str { type Error = crate::str::Utf8Error; #[inline] diff --git a/library/core/src/bstr/traits.rs b/library/core/src/bstr/traits.rs index ff46bb13ba4eb..1d8d0e29e9a5a 100644 --- a/library/core/src/bstr/traits.rs +++ b/library/core/src/bstr/traits.rs @@ -25,7 +25,7 @@ impl PartialOrd for ByteStr { impl PartialEq for ByteStr { #[inline] fn eq(&self, other: &ByteStr) -> bool { - &self.0 == &other.0 + self.0 == other.0 } } @@ -45,8 +45,7 @@ impl hash::Hash for ByteStr { #[unstable(feature = "bstr_internals", issue = "none")] macro_rules! impl_partial_eq { ($lhs:ty, $rhs:ty) => { - #[allow(unused_lifetimes)] - impl<'a> PartialEq<$rhs> for $lhs { + impl PartialEq<$rhs> for $lhs { #[inline] fn eq(&self, other: &$rhs) -> bool { let other: &[u8] = other.as_ref(); @@ -54,8 +53,7 @@ macro_rules! impl_partial_eq { } } - #[allow(unused_lifetimes)] - impl<'a> PartialEq<$lhs> for $rhs { + impl PartialEq<$lhs> for $rhs { #[inline] fn eq(&self, other: &$lhs) -> bool { let this: &[u8] = self.as_ref(); @@ -76,9 +74,8 @@ macro_rules! impl_partial_eq_ord { ($lhs:ty, $rhs:ty) => { $crate::bstr::impl_partial_eq!($lhs, $rhs); - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] - impl<'a> PartialOrd<$rhs> for $lhs { + impl PartialOrd<$rhs> for $lhs { #[inline] fn partial_cmp(&self, other: &$rhs) -> Option { let other: &[u8] = other.as_ref(); @@ -86,9 +83,8 @@ macro_rules! impl_partial_eq_ord { } } - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] - impl<'a> PartialOrd<$lhs> for $rhs { + impl PartialOrd<$lhs> for $rhs { #[inline] fn partial_cmp(&self, other: &$lhs) -> Option { let this: &[u8] = self.as_ref(); @@ -107,7 +103,6 @@ pub use impl_partial_eq_ord; #[unstable(feature = "bstr_internals", issue = "none")] macro_rules! impl_partial_eq_n { ($lhs:ty, $rhs:ty) => { - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] impl PartialEq<$rhs> for $lhs { #[inline] @@ -117,7 +112,6 @@ macro_rules! impl_partial_eq_n { } } - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] impl PartialEq<$lhs> for $rhs { #[inline] @@ -274,4 +268,5 @@ impl_slice_index!(range::RangeFrom); impl_slice_index!(ops::RangeInclusive); impl_slice_index!(range::RangeInclusive); impl_slice_index!(ops::RangeToInclusive); +impl_slice_index!(range::RangeToInclusive); impl_slice_index!((ops::Bound, ops::Bound)); diff --git a/library/core/src/cell.rs b/library/core/src/cell.rs index 661ea4ab6a27f..e8cd3a500084a 100644 --- a/library/core/src/cell.rs +++ b/library/core/src/cell.rs @@ -68,7 +68,7 @@ //! [`OnceCell`] is somewhat of a hybrid of `Cell` and `RefCell` that works for values that //! typically only need to be set once. This means that a reference `&T` can be obtained without //! moving or copying the inner value (unlike `Cell`) but also without runtime checks (unlike -//! `RefCell`). However, its value can also not be updated once set unless you have a mutable +//! `RefCell`). However, once set, its value cannot be updated unless you have a mutable //! reference to the `OnceCell`. //! //! `OnceCell` provides the following methods: @@ -255,13 +255,16 @@ use crate::marker::{Destruct, PhantomData, Unsize}; use crate::mem::{self, ManuallyDrop}; use crate::ops::{self, CoerceUnsized, Deref, DerefMut, DerefPure, DispatchFromDyn}; use crate::panic::const_panic; -use crate::pin::PinCoerceUnsized; +use crate::pin::PinSafePointer; use crate::ptr::{self, NonNull}; use crate::range; +mod covariant_unsafe_cell; mod lazy; mod once; +#[unstable(feature = "covariant_unsafe_cell", issue = "159735")] +pub use covariant_unsafe_cell::CovariantUnsafeCell; #[stable(feature = "lazy_cell", since = "1.80.0")] pub use lazy::LazyCell; #[stable(feature = "once_cell", since = "1.70.0")] @@ -334,7 +337,7 @@ impl Clone for Cell { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for Cell { +const impl Default for Cell { /// Creates a `Cell`, with the `Default` value for T. #[inline] fn default() -> Cell { @@ -391,7 +394,7 @@ impl Ord for Cell { #[stable(feature = "cell_from", since = "1.12.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for Cell { +const impl From for Cell { /// Creates a new `Cell` containing the given value. fn from(t: T) -> Cell { Cell::new(t) @@ -689,6 +692,30 @@ impl, U> CoerceUnsized> for Cell {} #[unstable(feature = "dispatch_from_dyn", issue = "none")] impl, U> DispatchFromDyn> for Cell {} +#[stable(feature = "more_conversion_trait_impls", since = "1.95.0")] +impl AsRef<[Cell; N]> for Cell<[T; N]> { + #[inline] + fn as_ref(&self) -> &[Cell; N] { + self.as_array_of_cells() + } +} + +#[stable(feature = "more_conversion_trait_impls", since = "1.95.0")] +impl AsRef<[Cell]> for Cell<[T; N]> { + #[inline] + fn as_ref(&self) -> &[Cell] { + self.as_array_of_cells() + } +} + +#[stable(feature = "more_conversion_trait_impls", since = "1.95.0")] +impl AsRef<[Cell]> for Cell<[T]> { + #[inline] + fn as_ref(&self) -> &[Cell] { + self.as_slice_of_cells() + } +} + impl Cell<[T]> { /// Returns a `&[Cell]` from a `&Cell<[T]>` /// @@ -750,7 +777,6 @@ impl Cell<[T; N]> { /// following is unsound: /// /// ```rust -/// #![feature(cell_get_cloned)] /// # use std::cell::Cell; /// /// #[derive(Copy, Debug)] @@ -1438,7 +1464,7 @@ impl Clone for RefCell { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for RefCell { +const impl Default for RefCell { /// Creates a `RefCell`, with the `Default` value for T. #[inline] fn default() -> RefCell { @@ -1516,7 +1542,7 @@ impl Ord for RefCell { #[stable(feature = "cell_from", since = "1.12.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for RefCell { +const impl From for RefCell { /// Creates a new `RefCell` containing the given value. fn from(t: T) -> RefCell { RefCell::new(t) @@ -1556,7 +1582,7 @@ impl<'b> BorrowRef<'b> { } #[rustc_const_unstable(feature = "const_ref_cell", issue = "137844")] -impl const Drop for BorrowRef<'_> { +const impl Drop for BorrowRef<'_> { #[inline] fn drop(&mut self) { let borrow = self.borrow.get(); @@ -1566,7 +1592,7 @@ impl const Drop for BorrowRef<'_> { } #[rustc_const_unstable(feature = "const_ref_cell", issue = "137844")] -impl const Clone for BorrowRef<'_> { +const impl Clone for BorrowRef<'_> { #[inline] fn clone(&self) -> Self { // Since this Ref exists, we know the borrow flag @@ -1598,7 +1624,7 @@ pub struct Ref<'b, T: ?Sized + 'b> { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Deref for Ref<'_, T> { +const impl Deref for Ref<'_, T> { type Target = T; #[inline] @@ -2024,7 +2050,7 @@ struct BorrowRefMut<'b> { } #[rustc_const_unstable(feature = "const_ref_cell", issue = "137844")] -impl const Drop for BorrowRefMut<'_> { +const impl Drop for BorrowRefMut<'_> { #[inline] fn drop(&mut self) { let borrow = self.borrow.get(); @@ -2082,7 +2108,7 @@ pub struct RefMut<'b, T: ?Sized + 'b> { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Deref for RefMut<'_, T> { +const impl Deref for RefMut<'_, T> { type Target = T; #[inline] @@ -2094,7 +2120,7 @@ impl const Deref for RefMut<'_, T> { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const DerefMut for RefMut<'_, T> { +const impl DerefMut for RefMut<'_, T> { #[inline] fn deref_mut(&mut self) -> &mut T { // SAFETY: the value is accessible as long as we hold our borrow. @@ -2127,8 +2153,9 @@ impl fmt::Display for RefMut<'_, T> { /// use `UnsafeCell` to wrap their data. /// /// Note that only the immutability guarantee for shared references is affected by `UnsafeCell`. The -/// uniqueness guarantee for mutable references is unaffected. There is *no* legal way to obtain -/// aliasing `&mut`, not even with `UnsafeCell`. +/// uniqueness guarantee for mutable references is unaffected. As explained below, for the duration +/// of the lifetime of an `&mut`, no other reference may exist and no pointer may be used to access +/// that memory; this applies even with `UnsafeCell`. /// /// `UnsafeCell` does nothing to avoid data races; they are still undefined behavior. If multiple /// threads have access to the same `UnsafeCell`, they must follow the usual rules of the @@ -2148,17 +2175,19 @@ impl fmt::Display for RefMut<'_, T> { /// /// - If you create a safe reference with lifetime `'a` (either a `&T` or `&mut T` reference), then /// you must not access the data in any way that contradicts that reference for the remainder of -/// `'a`. For example, this means that if you take the `*mut T` from an `UnsafeCell` and cast it -/// to an `&T`, then the data in `T` must remain immutable (modulo any `UnsafeCell` data found -/// within `T`, of course) until that reference's lifetime expires. Similarly, if you create a -/// `&mut T` reference that is released to safe code, then you must not access the data within the -/// `UnsafeCell` until that reference expires. +/// `'a`, and you must not create any contradicting references. For example, this means that if +/// you take the `*mut T` from an `UnsafeCell` and cast it to a `&T`, then the data in `T` must +/// remain immutable (modulo any `UnsafeCell` data found within `T`, of course) until that +/// reference's lifetime expires, and no `&mut` reference to this data may be created. Similarly, +/// if you create a `&mut T` reference, then you must not access the data within the `UnsafeCell` +/// with any other pointer/reference until that reference expires, and no reference of any kind +/// may be created. /// /// - For both `&T` without `UnsafeCell<_>` and `&mut T`, you must also not deallocate the data -/// until the reference expires. As a special exception, given an `&T`, any part of it that is +/// until the reference expires. As a special exception, given a `&T`, any part of it that is /// inside an `UnsafeCell<_>` may be deallocated during the lifetime of the reference, after the /// last time the reference is used (dereferenced or reborrowed). Since you cannot deallocate a part -/// of what a reference points to, this means the memory an `&T` points to can be deallocated only if +/// of what a reference points to, this means the memory a `&T` points to can be deallocated only if /// *every part of it* (including padding) is inside an `UnsafeCell`. /// /// However, whenever a `&UnsafeCell` is constructed or dereferenced, it must still point to @@ -2174,10 +2203,10 @@ impl fmt::Display for RefMut<'_, T> { /// 2. A `&mut T` reference may be released to safe code provided neither other `&mut T` nor `&T` /// co-exist with it. A `&mut T` must always be unique. /// -/// Note that whilst mutating the contents of an `&UnsafeCell` (even while other +/// Note that whilst mutating the contents of a `&UnsafeCell` (even while other /// `&UnsafeCell` references alias the cell) is /// ok (provided you enforce the above invariants some other way), it is still undefined behavior -/// to have multiple `&mut UnsafeCell` aliases. That is, `UnsafeCell` is a wrapper +/// to have aliasing `&mut UnsafeCell` (or aliasing `&mut` of *any* type). That is, `UnsafeCell` is a wrapper /// designed to have a special interaction with _shared_ accesses (_i.e._, through an /// `&UnsafeCell<_>` reference); there is no magic whatsoever when dealing with _exclusive_ /// accesses (_e.g._, through a `&mut UnsafeCell<_>`): neither the cell nor the wrapped value @@ -2200,36 +2229,19 @@ impl fmt::Display for RefMut<'_, T> { /// order to avoid its interior mutability property from spreading from `T` into the `Outer` type, /// thus this can cause distortions in the type size in these cases. /// -/// Note that the only valid way to obtain a `*mut T` pointer to the contents of a -/// _shared_ `UnsafeCell` is through [`.get()`] or [`.raw_get()`]. A `&mut T` reference -/// can be obtained by either dereferencing this pointer or by calling [`.get_mut()`] -/// on an _exclusive_ `UnsafeCell`. Even though `T` and `UnsafeCell` have the -/// same memory layout, the following is not allowed and undefined behavior: +/// The following examples make use of this guarantee: /// -/// ```rust,compile_fail +/// ```rust /// # use std::cell::UnsafeCell; -/// unsafe fn not_allowed(ptr: &UnsafeCell) -> &mut T { +/// /// # Safety +/// /// The caller must not call `get_mut_unchecked` again (on any alias of `ptr`) for the duration +/// /// of the lifetime of the returned reference. +/// unsafe fn get_mut_unchecked(ptr: &UnsafeCell) -> &mut T { /// let t = ptr as *const UnsafeCell as *mut T; -/// // This is undefined behavior, because the `*mut T` pointer -/// // was not obtained through `.get()` nor `.raw_get()`: /// unsafe { &mut *t } /// } /// ``` /// -/// Instead, do this: -/// -/// ```rust -/// # use std::cell::UnsafeCell; -/// // Safety: the caller must ensure that there are no references that -/// // point to the *contents* of the `UnsafeCell`. -/// unsafe fn get_mut(ptr: &UnsafeCell) -> &mut T { -/// unsafe { &mut *ptr.get() } -/// } -/// ``` -/// -/// Converting in the other direction from a `&mut T` -/// to an `&UnsafeCell` is allowed: -/// /// ```rust /// # use std::cell::UnsafeCell; /// fn get_shared(ptr: &mut T) -> &UnsafeCell { @@ -2240,7 +2252,6 @@ impl fmt::Display for RefMut<'_, T> { /// ``` /// /// [niche]: https://rust-lang.github.io/unsafe-code-guidelines/glossary.html#niche -/// [`.raw_get()`]: `UnsafeCell::raw_get` /// /// # Examples /// @@ -2398,9 +2409,12 @@ impl UnsafeCell { /// Gets a mutable pointer to the wrapped value. /// - /// This can be cast to a pointer of any kind. When creating references, you must uphold the - /// aliasing rules; see [the type-level docs][UnsafeCell#aliasing-rules] for more discussion and - /// caveats. + /// This can be cast to a pointer of any kind. When creating (shared or mutable) references, you + /// must uphold the aliasing rules; see [the type-level docs][UnsafeCell#aliasing-rules] for + /// more discussion and caveats. + /// + /// This is equivalent to casting `self` to a raw pointer and then casting that raw + /// pointer to `*mut T`. /// /// # Examples /// @@ -2419,8 +2433,7 @@ impl UnsafeCell { #[rustc_should_not_be_called_on_const_items] pub const fn get(&self) -> *mut T { // We can just cast the pointer from `UnsafeCell` to `T` because of - // #[repr(transparent)]. This exploits std's special status, there is - // no guarantee for user code that this will work in future versions of the compiler! + // #[repr(transparent)]. self as *const UnsafeCell as *const T as *mut T } @@ -2450,9 +2463,11 @@ impl UnsafeCell { /// The difference from [`get`] is that this function accepts a raw pointer, /// which is useful to avoid the creation of temporary references. /// - /// This can be cast to a pointer of any kind. When creating references, you must uphold the - /// aliasing rules; see [the type-level docs][UnsafeCell#aliasing-rules] for more discussion and - /// caveats. + /// This can be cast to a pointer of any kind. When creating (shared or mutable) references, you + /// must uphold the aliasing rules; see [the type-level docs][UnsafeCell#aliasing-rules] for + /// more discussion and caveats. + /// + /// This is equivalent to casting `this` to `*mut T`. /// /// [`get`]: UnsafeCell::get() /// @@ -2544,7 +2559,7 @@ impl UnsafeCell { #[stable(feature = "unsafe_cell_default", since = "1.10.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for UnsafeCell { +const impl Default for UnsafeCell { /// Creates an `UnsafeCell`, with the `Default` value for T. fn default() -> UnsafeCell { UnsafeCell::new(Default::default()) @@ -2553,7 +2568,7 @@ impl const Default for UnsafeCell { #[stable(feature = "cell_from", since = "1.12.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for UnsafeCell { +const impl From for UnsafeCell { /// Creates a new `UnsafeCell` containing the given value. fn from(t: T) -> UnsafeCell { UnsafeCell::new(t) @@ -2651,7 +2666,7 @@ impl SyncUnsafeCell { #[unstable(feature = "sync_unsafe_cell", issue = "95439")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for SyncUnsafeCell { +const impl Default for SyncUnsafeCell { /// Creates an `SyncUnsafeCell`, with the `Default` value for T. fn default() -> SyncUnsafeCell { SyncUnsafeCell::new(Default::default()) @@ -2660,7 +2675,7 @@ impl const Default for SyncUnsafeCell { #[unstable(feature = "sync_unsafe_cell", issue = "95439")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for SyncUnsafeCell { +const impl From for SyncUnsafeCell { /// Creates a new `SyncUnsafeCell` containing the given value. fn from(t: T) -> SyncUnsafeCell { SyncUnsafeCell::new(t) @@ -2695,20 +2710,14 @@ fn assert_coerce_unsized( let _: RefCell<&dyn Send> = d; } +// The implementations of Deref/DerefMut are not malicious, so we can allow the +// user to perform unsizing coercions with `Pin>` pointers if they +// can manage to create one. #[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -unsafe impl PinCoerceUnsized for UnsafeCell {} - -#[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -unsafe impl PinCoerceUnsized for SyncUnsafeCell {} - -#[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -unsafe impl PinCoerceUnsized for Cell {} - -#[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -unsafe impl PinCoerceUnsized for RefCell {} - -#[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -unsafe impl<'b, T: ?Sized> PinCoerceUnsized for Ref<'b, T> {} +unsafe impl<'b, T: ?Sized> PinSafePointer for Ref<'b, T> {} +// The implementations of Deref/DerefMut are not malicious, so we can allow the +// user to perform unsizing coercions with `Pin>` pointers if they +// can manage to create one. #[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -unsafe impl<'b, T: ?Sized> PinCoerceUnsized for RefMut<'b, T> {} +unsafe impl<'b, T: ?Sized> PinSafePointer for RefMut<'b, T> {} diff --git a/library/core/src/cell/covariant_unsafe_cell.rs b/library/core/src/cell/covariant_unsafe_cell.rs new file mode 100644 index 0000000000000..3876cc404cd2e --- /dev/null +++ b/library/core/src/cell/covariant_unsafe_cell.rs @@ -0,0 +1,183 @@ +use crate::cell::UnsafeCell; +use crate::fmt; +use crate::ops::CoerceUnsized; +use crate::ptr::{self, NonNull}; + +/// **Co**variant version of [`UnsafeCell`]. +#[unstable(feature = "covariant_unsafe_cell", issue = "159735")] +#[repr(transparent)] +#[rustc_pub_transparent] +// Implementation note: +// +// We could make `CovariantUnsafeCell` be the canonical lang item and make `UnsafeCell` a wrapper +// over it, with `PhantomData<*mut T>`. That would however be a huge compiler change, without clear +// benefit. +// +// As such, `CovariantUnsafeCell` is wrapping `UnsafeCell` instead. It is a lang-item only to +// hardcode its variance to be **co**variant in `T`, even though it is wrapping `UnsafeCell` which +// is **in**variant in `T`. +#[lang = "covariant_unsafe_cell"] +pub struct CovariantUnsafeCell(UnsafeCell); + +#[unstable(feature = "covariant_unsafe_cell", issue = "159735")] +impl !Sync for CovariantUnsafeCell {} + +impl CovariantUnsafeCell { + /// Constructs a new instance of `CovariantUnsafeCell` which will wrap the specified value. + /// + /// All access to the inner value through `&CovariantUnsafeCell` requires `unsafe` code. + /// + /// # Examples + /// + /// ``` + /// #![feature(covariant_unsafe_cell)] + /// use std::cell::CovariantUnsafeCell; + /// + /// let uc = CovariantUnsafeCell::new(5); + /// ``` + #[unstable(feature = "covariant_unsafe_cell", issue = "159735")] + #[rustc_const_unstable(feature = "covariant_unsafe_cell", issue = "159735")] + #[inline(always)] + pub const fn new(value: T) -> CovariantUnsafeCell { + CovariantUnsafeCell(UnsafeCell::new(value)) + } + + /// Unwraps the value, consuming the cell. + /// + /// # Examples + /// + /// ``` + /// #![feature(covariant_unsafe_cell)] + /// use std::cell::CovariantUnsafeCell; + /// + /// let uc = CovariantUnsafeCell::new(5); + /// + /// let five = uc.into_inner(); + /// ``` + #[inline(always)] + #[unstable(feature = "covariant_unsafe_cell", issue = "159735")] + #[rustc_const_unstable(feature = "covariant_unsafe_cell", issue = "159735")] + pub const fn into_inner(self) -> T { + self.0.into_inner() + } +} + +impl CovariantUnsafeCell { + /// Gets a mutable non-null pointer to the wrapped value. + /// + /// This can be cast to a pointer of any kind. When creating (shared or mutable) references, you + /// must uphold the aliasing rules; see [the `UnsafeCell` type-level docs] for more discussion + /// and caveats. + /// + /// [the `UnsafeCell` type-level docs]: super::UnsafeCell#aliasing-rules + /// + /// # Examples + /// + /// ``` + /// #![feature(covariant_unsafe_cell)] + /// use std::cell::CovariantUnsafeCell; + /// use std::ptr::NonNull; + /// + /// let uc = CovariantUnsafeCell::new(5); + /// + /// let ptr: NonNull = uc.get(); + /// ``` + #[inline(always)] + #[rustc_as_ptr] + #[rustc_should_not_be_called_on_const_items] + #[unstable(feature = "covariant_unsafe_cell", issue = "159735")] + #[rustc_const_unstable(feature = "covariant_unsafe_cell", issue = "159735")] + pub const fn get(&self) -> NonNull { + // We can just cast the pointer from `CovariantUnsafeCell` to `T` because of + // #[repr(transparent)]. + // + // Note that this is also known to be allowed for user code as per + // `#[rustc_pub_transparent]`. + // SAFETY: the pointer is not null, as it comes from a reference + unsafe { NonNull::new_unchecked(ptr::from_ref(self).cast_mut() as *mut T) } + } + + /// Returns a mutable reference to the underlying data. + /// + /// This call borrows the `CovariantUnsafeCell` mutably (at compile-time) which guarantees that + /// we possess the only reference. + /// + /// # Examples + /// + /// ``` + /// #![feature(covariant_unsafe_cell)] + /// use std::cell::CovariantUnsafeCell; + /// + /// let mut c = CovariantUnsafeCell::new(5); + /// *c.get_mut() += 1; + /// + /// assert_eq!(*c.get_mut(), 6); + /// ``` + #[inline(always)] + #[unstable(feature = "covariant_unsafe_cell", issue = "159735")] + #[rustc_const_unstable(feature = "covariant_unsafe_cell", issue = "159735")] + pub const fn get_mut(&mut self) -> &mut T { + self.0.get_mut() + } + + /// Gets a mutable pointer to the wrapped value. + /// The difference from [`get`] is that this function accepts a raw pointer, + /// which is useful to avoid the creation of temporary references. + /// + /// This can be cast to a pointer of any kind. When creating (shared or mutable) references, you + /// must uphold the aliasing rules; see [the `UnsafeCell` type-level docs] for more discussion + /// and caveats. + /// + /// [`get`]: CovariantUnsafeCell::get() + /// + /// # Examples + /// + /// Gradual initialization of an `CovariantUnsafeCell` requires `raw_get`, as + /// calling `get` would require creating a reference to uninitialized data: + /// + /// ``` + /// #![feature(covariant_unsafe_cell)] + /// use std::cell::CovariantUnsafeCell; + /// use std::mem::MaybeUninit; + /// + /// let m = MaybeUninit::>::uninit(); + /// unsafe { CovariantUnsafeCell::raw_get(m.as_ptr()).write(5); } + /// // avoid below which references to uninitialized data + /// // unsafe { CovariantUnsafeCell::get(&*m.as_ptr()).write(5); } + /// let uc = unsafe { m.assume_init() }; + /// + /// assert_eq!(uc.into_inner(), 5); + /// ``` + #[inline(always)] + #[unstable(feature = "covariant_unsafe_cell", issue = "159735")] + #[rustc_const_unstable(feature = "covariant_unsafe_cell", issue = "159735")] + pub const fn raw_get(this: *const Self) -> *mut T { + // We can just cast the pointer from `UnsafeCell` to `T` because of + // #[repr(transparent)]. + // + // Note that this is also known to be allowed for user code as per + // `#[rustc_pub_transparent]`. + this as *const T as *mut T + } +} + +#[unstable(feature = "coerce_unsized", issue = "18598")] +impl, U> CoerceUnsized> for CovariantUnsafeCell {} + +#[unstable(feature = "covariant_unsafe_cell", issue = "159735")] +impl fmt::Debug for CovariantUnsafeCell { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("CovariantUnsafeCell").finish_non_exhaustive() + } +} + +#[cfg(test)] +mod tests { + use super::*; + + fn _covarience<'short, 'long: 'short>( + x: CovariantUnsafeCell<&'long ()>, + ) -> CovariantUnsafeCell<&'short ()> { + x + } +} diff --git a/library/core/src/cell/lazy.rs b/library/core/src/cell/lazy.rs index 28a76569c1d03..ba32fff2284fd 100644 --- a/library/core/src/cell/lazy.rs +++ b/library/core/src/cell/lazy.rs @@ -346,7 +346,8 @@ impl T> DerefMut for LazyCell { } #[stable(feature = "lazy_cell", since = "1.80.0")] -impl Default for LazyCell { +#[rustc_const_unstable(feature = "const_default", issue = "143894")] +const impl Default for LazyCell { /// Creates a new lazy value using `Default` as the initializing function. #[inline] fn default() -> LazyCell { @@ -366,6 +367,16 @@ impl fmt::Debug for LazyCell { } } +#[stable(feature = "from_wrapper_impls", since = "1.96.0")] +impl From for LazyCell { + /// Constructs a `LazyCell` that starts already initialized + /// with the provided value. + #[inline] + fn from(value: T) -> Self { + Self { state: UnsafeCell::new(State::Init(value)) } + } +} + #[cold] #[inline(never)] const fn panic_poisoned() -> ! { diff --git a/library/core/src/cell/once.rs b/library/core/src/cell/once.rs index af4469fad2cc6..01ba604e67949 100644 --- a/library/core/src/cell/once.rs +++ b/library/core/src/cell/once.rs @@ -47,6 +47,31 @@ impl OnceCell { OnceCell { inner: UnsafeCell::new(None) } } + /// Creates a new initialized cell. + /// + /// This is equivalent to `OnceCell::from(value)`, but can be used in + /// const contexts, unlike the `From` implementation. + /// + /// # Examples + /// + /// ``` + /// #![feature(once_cell_new_init)] + /// use std::cell::OnceCell; + /// + /// const CELL: OnceCell = OnceCell::new_init(1); + /// assert_eq!(CELL.get(), Some(&1)); + /// + /// let cell = OnceCell::new_init(String::from("kitty")); + /// assert_eq!(cell.set(String::from("puppy")), Err(String::from("puppy"))); + /// assert_eq!(cell.get(), Some(&"kitty".to_string())); + /// ``` + #[inline] + #[must_use] + #[unstable(feature = "once_cell_new_init", issue = "159859")] + pub const fn new_init(init_value: T) -> OnceCell { + OnceCell { inner: UnsafeCell::new(Some(init_value)) } + } + /// Gets the reference to the underlying value. /// /// Returns `None` if the cell is uninitialized. @@ -354,7 +379,7 @@ impl OnceCell { #[stable(feature = "once_cell", since = "1.70.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for OnceCell { +const impl Default for OnceCell { #[inline] fn default() -> Self { Self::new() @@ -397,7 +422,7 @@ impl Eq for OnceCell {} #[stable(feature = "once_cell", since = "1.70.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for OnceCell { +const impl From for OnceCell { /// Creates a new `OnceCell` which already contains the given `value`. #[inline] fn from(value: T) -> Self { diff --git a/library/core/src/char/convert.rs b/library/core/src/char/convert.rs index da80568a3c6d1..447c30520f3e4 100644 --- a/library/core/src/char/convert.rs +++ b/library/core/src/char/convert.rs @@ -43,7 +43,7 @@ pub(super) const unsafe fn from_u32_unchecked(i: u32) -> char { #[stable(feature = "char_convert", since = "1.13.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for u32 { +const impl From for u32 { /// Converts a [`char`] into a [`u32`]. /// /// # Examples @@ -62,7 +62,7 @@ impl const From for u32 { #[stable(feature = "more_char_conversions", since = "1.51.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for u64 { +const impl From for u64 { /// Converts a [`char`] into a [`u64`]. /// /// # Examples @@ -83,7 +83,7 @@ impl const From for u64 { #[stable(feature = "more_char_conversions", since = "1.51.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for u128 { +const impl From for u128 { /// Converts a [`char`] into a [`u128`]. /// /// # Examples @@ -108,7 +108,7 @@ impl const From for u128 { /// See [`impl From for char`](char#impl-From-for-char) for details on the encoding. #[stable(feature = "u8_from_char", since = "1.59.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const TryFrom for u8 { +const impl TryFrom for u8 { type Error = TryFromCharError; /// Tries to convert a [`char`] into a [`u8`]. @@ -138,7 +138,7 @@ impl const TryFrom for u8 { /// This corresponds to the UCS-2 encoding, as specified in ISO/IEC 10646:2003. #[stable(feature = "u16_from_char", since = "1.74.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const TryFrom for u16 { +const impl TryFrom for u16 { type Error = TryFromCharError; /// Tries to convert a [`char`] into a [`u16`]. @@ -170,7 +170,7 @@ impl const TryFrom for u16 { /// UTF-32 code point to the extent representable by pointer addresses. #[stable(feature = "usize_try_from_char", since = "1.94.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const TryFrom for usize { +const impl TryFrom for usize { type Error = TryFromCharError; /// Tries to convert a [`char`] into a [`usize`]. @@ -220,7 +220,7 @@ impl const TryFrom for usize { /// C0 and C1 control codes. #[stable(feature = "char_convert", since = "1.13.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for char { +const impl From for char { /// Converts a [`u8`] into a [`char`]. /// /// # Examples @@ -306,7 +306,7 @@ const fn char_try_from_u32(i: u32) -> Result { #[stable(feature = "try_from", since = "1.34.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const TryFrom for char { +const impl TryFrom for char { type Error = CharTryFromError; #[inline] diff --git a/library/core/src/char/methods.rs b/library/core/src/char/methods.rs index 8424fd709db56..044a19c72b96b 100644 --- a/library/core/src/char/methods.rs +++ b/library/core/src/char/methods.rs @@ -7,7 +7,6 @@ use crate::panic::const_panic; use crate::slice; use crate::str::from_utf8_unchecked_mut; use crate::ub_checks::assert_unsafe_precondition; -use crate::unicode::printable::is_printable; use crate::unicode::{self, conversions}; impl char { @@ -95,13 +94,18 @@ impl char { /// The version of [Unicode](https://www.unicode.org/) that the Unicode parts of /// `char` and `str` methods are based on. /// - /// New versions of Unicode are released regularly and subsequently all methods - /// in the standard library depending on Unicode are updated. Therefore the - /// behavior of some `char` and `str` methods and the value of this constant - /// changes over time. This is *not* considered to be a breaking change. + /// New versions of Unicode are released regularly, and subsequently all methods + /// in the standard library depending on Unicode are updated. Therefore, the + /// behavior of some `char` and `str` methods, and the value of this constant, + /// change over time (within the boundaries of Unicode's [stability policies]). + /// This is *not* considered to be a breaking change. + /// + /// [stability policies]: https://www.unicode.org/policies/stability_policy.html /// /// The version numbering scheme is explained in - /// [Unicode 11.0 or later, Section 3.1 Versions of the Unicode Standard](https://www.unicode.org/versions/Unicode11.0.0/ch03.pdf#page=4). + /// [Section 3.1 (Version Numbering)] of the Unicode Standard. + /// + /// [Section 3.1 (Version Numbering)]: https://www.unicode.org/versions/latest/core-spec/chapter-3/#G49512 #[stable(feature = "assoc_char_consts", since = "1.52.0")] pub const UNICODE_VERSION: (u8, u8, u8) = crate::unicode::UNICODE_VERSION; @@ -475,18 +479,33 @@ impl char { #[inline] pub(crate) fn escape_debug_ext(self, args: EscapeDebugExtArgs) -> EscapeDebug { match self { - '\0' => EscapeDebug::backslash(ascii::Char::Digit0), - '\t' => EscapeDebug::backslash(ascii::Char::SmallT), - '\r' => EscapeDebug::backslash(ascii::Char::SmallR), - '\n' => EscapeDebug::backslash(ascii::Char::SmallN), - '\\' => EscapeDebug::backslash(ascii::Char::ReverseSolidus), + // Special escapes '\"' if args.escape_double_quote => EscapeDebug::backslash(ascii::Char::QuotationMark), '\'' if args.escape_single_quote => EscapeDebug::backslash(ascii::Char::Apostrophe), - _ if args.escape_grapheme_extended && self.is_grapheme_extended() => { + '\\' => EscapeDebug::backslash(ascii::Char::ReverseSolidus), + '\n' => EscapeDebug::backslash(ascii::Char::SmallN), + '\t' => EscapeDebug::backslash(ascii::Char::SmallT), + '\r' => EscapeDebug::backslash(ascii::Char::SmallR), + '\0' => EscapeDebug::backslash(ascii::Char::Digit0), + + // ASCII fast path, + // plus U+FF9E HALFWIDTH KATAKANA VOICED SOUND MARK + // and U+FF9F HALFWIDTH KATAKANA SEMI-VOICED SOUND MARK + // which should not be escaped despite being grapheme extenders. + '\x20'..='\x7E' | '\u{FF9E}' | '\u{FF9F}' => EscapeDebug::printable(self), + + _ if self.is_control() + || self.is_private_use() + || self.is_whitespace() + || args.escape_grapheme_extender && self.is_grapheme_extender() + || self.is_default_ignorable() + || self.is_format_control() + || !self.is_assigned() => + { EscapeDebug::unicode(self) } - _ if is_printable(self) => EscapeDebug::printable(self), - _ => EscapeDebug::unicode(self), + + _ => EscapeDebug::printable(self), } } @@ -755,11 +774,11 @@ impl char { /// Returns `true` if this `char` has the `Alphabetic` property. /// - /// `Alphabetic` is described in Chapter 4 (Character Properties) of the [Unicode Standard] and - /// specified in the [Unicode Character Database][ucd] [`DerivedCoreProperties.txt`]. + /// `Alphabetic` is [described] in Chapter 4 (Character Properties) of the Unicode Standard, and + /// [specified] in the Unicode Character Database [`DerivedCoreProperties.txt`]. /// - /// [Unicode Standard]: https://www.unicode.org/versions/latest/ - /// [ucd]: https://www.unicode.org/reports/tr44/ + /// [described]: https://www.unicode.org/versions/latest/core-spec/chapter-4/#G32524 + /// [specified]: https://www.unicode.org/reports/tr44/#Alphabetic /// [`DerivedCoreProperties.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/DerivedCoreProperties.txt /// /// # Examples @@ -780,17 +799,82 @@ impl char { pub fn is_alphabetic(self) -> bool { match self { 'a'..='z' | 'A'..='Z' => true, - c => c > '\x7f' && unicode::Alphabetic(c), + '\0'..='\u{A9}' => false, + _ => unicode::Alphabetic(self), + } + } + + /// Returns `true` if this `char` has the `Cased` property. + /// A character is cased if and only if it is uppercase, lowercase, or titlecase. + /// + /// `Cased` is [described] in Chapter 3 (Character Properties) of the Unicode Standard and + /// [specified] in the Unicode Character Database [`DerivedCoreProperties.txt`]. + /// + /// [described]: https://www.unicode.org/versions/latest/core-spec/chapter-3/#G44595 + /// [specified]: https://www.unicode.org/reports/tr44/#Cased + /// [`DerivedCoreProperties.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/DerivedCoreProperties.txt + /// + /// # Examples + /// + /// Basic usage: + /// + /// ``` + /// #![feature(titlecase)] + /// assert!('A'.is_cased()); + /// assert!('a'.is_cased()); + /// assert!(!'京'.is_cased()); + /// ``` + #[must_use] + #[unstable(feature = "titlecase", issue = "153892")] + #[inline] + pub fn is_cased(self) -> bool { + match self { + 'a'..='z' | 'A'..='Z' => true, + '\0'..='\u{A9}' => false, + _ => unicode::Lowercase(self) || unicode::Uppercase(self) || unicode::Lt(self), + } + } + + /// Returns the case of this character: + /// [`Some(CharCase::Upper)`][`CharCase::Upper`] if [`self.is_uppercase()`][`char::is_uppercase`], + /// [`Some(CharCase::Lower)`][`CharCase::Lower`] if [`self.is_lowercase()`][`char::is_lowercase`], + /// [`Some(CharCase::Title)`][`CharCase::Title`] if [`self.is_titlecase()`][`char::is_titlecase`], and + /// `None` if [`!self.is_cased()`][`char::is_cased`]. + /// + /// # Examples + /// + /// ``` + /// #![feature(titlecase)] + /// use core::char::CharCase; + /// assert_eq!('a'.case(), Some(CharCase::Lower)); + /// assert_eq!('δ'.case(), Some(CharCase::Lower)); + /// assert_eq!('A'.case(), Some(CharCase::Upper)); + /// assert_eq!('Δ'.case(), Some(CharCase::Upper)); + /// assert_eq!('Dž'.case(), Some(CharCase::Title)); + /// assert_eq!('中'.case(), None); + /// ``` + #[must_use] + #[unstable(feature = "titlecase", issue = "153892")] + #[inline] + pub fn case(self) -> Option { + match self { + 'a'..='z' => Some(CharCase::Lower), + 'A'..='Z' => Some(CharCase::Upper), + '\0'..='\u{A9}' => None, + _ if unicode::Lowercase(self) => Some(CharCase::Lower), + _ if unicode::Uppercase(self) => Some(CharCase::Upper), + _ if unicode::Lt(self) => Some(CharCase::Title), + _ => None, } } /// Returns `true` if this `char` has the `Lowercase` property. /// - /// `Lowercase` is described in Chapter 4 (Character Properties) of the [Unicode Standard] and - /// specified in the [Unicode Character Database][ucd] [`DerivedCoreProperties.txt`]. + /// `Lowercase` is [described] in Chapter 4 (Character Properties) of the Unicode Standard, and + /// [specified] in the Unicode Character Database [`DerivedCoreProperties.txt`]. /// - /// [Unicode Standard]: https://www.unicode.org/versions/latest/ - /// [ucd]: https://www.unicode.org/reports/tr44/ + /// [described]: https://www.unicode.org/versions/latest/core-spec/chapter-4/#G136255 + /// [specified]: https://www.unicode.org/reports/tr44/#Lowercase /// [`DerivedCoreProperties.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/DerivedCoreProperties.txt /// /// # Examples @@ -821,17 +905,52 @@ impl char { pub const fn is_lowercase(self) -> bool { match self { 'a'..='z' => true, - c => c > '\x7f' && unicode::Lowercase(c), + '\0'..='\u{A9}' => false, + _ => unicode::Lowercase(self), + } + } + + /// Returns `true` if this `char` is in the general category for titlecase letters. + /// Conceptually, these characters consist of an uppercase portion followed by a lowercase portion. + /// + /// Titlecase letters (code points with the general category of `Lt`) are [described] in Chapter 4 + /// (Character Properties) of the Unicode Standard, and [specified] in the Unicode Character + /// Database [`UnicodeData.txt`]. + /// + /// [described]: https://www.unicode.org/versions/latest/core-spec/chapter-4/#G124722 + /// [specified]: https://www.unicode.org/reports/tr44/#GC_Values_Table + /// [`UnicodeData.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/UnicodeData.txt + /// + /// # Examples + /// + /// Basic usage: + /// + /// ``` + /// #![feature(titlecase)] + /// assert!('Dž'.is_titlecase()); + /// assert!('ῼ'.is_titlecase()); + /// assert!(!'D'.is_titlecase()); + /// assert!(!'z'.is_titlecase()); + /// assert!(!'中'.is_titlecase()); + /// assert!(!' '.is_titlecase()); + /// ``` + #[must_use] + #[unstable(feature = "titlecase", issue = "153892")] + #[inline] + pub fn is_titlecase(self) -> bool { + match self { + '\0'..='\u{01C4}' => false, + _ => unicode::Lt(self), } } /// Returns `true` if this `char` has the `Uppercase` property. /// - /// `Uppercase` is described in Chapter 4 (Character Properties) of the [Unicode Standard] and - /// specified in the [Unicode Character Database][ucd] [`DerivedCoreProperties.txt`]. + /// `Uppercase` is [described] in Chapter 4 (Character Properties) of the Unicode Standard, and + /// [specified] in the Unicode Character Database [`DerivedCoreProperties.txt`]. /// - /// [Unicode Standard]: https://www.unicode.org/versions/latest/ - /// [ucd]: https://www.unicode.org/reports/tr44/ + /// [described]: https://www.unicode.org/versions/latest/core-spec/chapter-4/#G136255 + /// [specified]: https://www.unicode.org/reports/tr44/#Uppercase /// [`DerivedCoreProperties.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/DerivedCoreProperties.txt /// /// # Examples @@ -862,47 +981,59 @@ impl char { pub const fn is_uppercase(self) -> bool { match self { 'A'..='Z' => true, - c => c > '\x7f' && unicode::Uppercase(c), + '\0'..='\u{BF}' => false, + _ => unicode::Uppercase(self), } } - /// Returns `true` if this `char` has the `White_Space` property. + /// Returns `true` if this `char` has one of the general categories for numbers. /// - /// `White_Space` is specified in the [Unicode Character Database][ucd] [`PropList.txt`]. + /// The general categories for numbers (`Nd` for decimal digits, `Nl` for letter-like numeric + /// characters, and `No` for other numeric characters) are [specified] in the Unicode Character + /// Database [`UnicodeData.txt`]. /// - /// [ucd]: https://www.unicode.org/reports/tr44/ - /// [`PropList.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/PropList.txt + /// This method doesn't cover everything that could be considered a number, e.g. ideographic numbers like '三'. + /// If you want everything including characters with overlapping purposes, then you might want to use + /// a Unicode or language-processing library that exposes the appropriate character properties + /// (e.g. [`Numeric_Type`]) instead of looking at the Unicode categories. + /// + /// If you want to parse ASCII decimal digits (0-9) or ASCII base-N, use + /// `is_ascii_digit` or `is_digit` instead. + /// + /// [specified]: https://www.unicode.org/reports/tr44/#GC_Values_Table + /// [`UnicodeData.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/UnicodeData.txt + /// [`Numeric_Type`]: https://www.unicode.org/reports/tr44/#Numeric_Type /// /// # Examples /// /// Basic usage: /// /// ``` - /// assert!(' '.is_whitespace()); - /// - /// // line break - /// assert!('\n'.is_whitespace()); - /// - /// // a non-breaking space - /// assert!('\u{A0}'.is_whitespace()); - /// - /// assert!(!'越'.is_whitespace()); + /// assert!('٣'.is_numeric()); + /// assert!('7'.is_numeric()); + /// assert!('৬'.is_numeric()); + /// assert!('¾'.is_numeric()); + /// assert!('①'.is_numeric()); + /// assert!(!'K'.is_numeric()); + /// assert!(!'و'.is_numeric()); + /// assert!(!'藏'.is_numeric()); + /// assert!(!'三'.is_numeric()); /// ``` #[must_use] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_const_stable(feature = "const_char_classify", since = "1.87.0")] #[inline] - pub const fn is_whitespace(self) -> bool { + pub fn is_numeric(self) -> bool { match self { - ' ' | '\x09'..='\x0d' => true, - c => c > '\x7f' && unicode::White_Space(c), + '0'..='9' => true, + '\0'..='\u{B1}' => false, + _ => unicode::N(self), } } /// Returns `true` if this `char` satisfies either [`is_alphabetic()`] or [`is_numeric()`]. /// - /// [`is_alphabetic()`]: #method.is_alphabetic - /// [`is_numeric()`]: #method.is_numeric + /// [`is_alphabetic()`]: Self::is_alphabetic + /// [`is_numeric()`]: Self::is_numeric /// /// # Examples /// @@ -922,21 +1053,56 @@ impl char { #[stable(feature = "rust1", since = "1.0.0")] #[inline] pub fn is_alphanumeric(self) -> bool { - if self.is_ascii() { - self.is_ascii_alphanumeric() - } else { - unicode::Alphabetic(self) || unicode::N(self) + match self { + 'a'..='z' | 'A'..='Z' | '0'..='9' => true, + '\0'..='\u{A9}' => false, + _ => unicode::Alphabetic(self) || unicode::N(self), + } + } + + /// Returns `true` if this `char` has the `White_Space` property. + /// + /// `White_Space` is [specified] in the Unicode Character Database [`PropList.txt`]. + /// + /// [specified]: https://www.unicode.org/reports/tr44/#White_Space + /// [`PropList.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/PropList.txt + /// + /// # Examples + /// + /// Basic usage: + /// + /// ``` + /// assert!(' '.is_whitespace()); + /// + /// // line break + /// assert!('\n'.is_whitespace()); + /// + /// // a non-breaking space + /// assert!('\u{A0}'.is_whitespace()); + /// + /// assert!(!'越'.is_whitespace()); + /// ``` + #[must_use] + #[stable(feature = "rust1", since = "1.0.0")] + #[rustc_const_stable(feature = "const_char_classify", since = "1.87.0")] + #[inline] + pub const fn is_whitespace(self) -> bool { + match self { + ' ' | '\x09'..='\x0d' => true, + '\0'..='\u{84}' => false, + _ => unicode::White_Space(self), } } /// Returns `true` if this `char` has the general category for control codes. /// - /// Control codes (code points with the general category of `Cc`) are described in Chapter 4 - /// (Character Properties) of the [Unicode Standard] and specified in the [Unicode Character - /// Database][ucd] [`UnicodeData.txt`]. + /// Control codes (code points with the general category of `Cc`) are [described] in Chapter 23 + /// (Special Areas and Format Characters) of the Unicode Standard, and [specified] in the Unicode Character + /// Database [`UnicodeData.txt`]. The full set of Unicode control codes is + /// `'\0'..='\x1f' | '\x7f'..='\u{9f}'`, and will never change. /// - /// [Unicode Standard]: https://www.unicode.org/versions/latest/ - /// [ucd]: https://www.unicode.org/reports/tr44/ + /// [described]: https://www.unicode.org/versions/latest/core-spec/chapter-23/#G20365 + /// [specified]: https://www.unicode.org/reports/tr44/#GC_Values_Table /// [`UnicodeData.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/UnicodeData.txt /// /// # Examples @@ -944,14 +1110,16 @@ impl char { /// Basic usage: /// /// ``` - /// // U+009C, STRING TERMINATOR - /// assert!('œ'.is_control()); + /// assert!('\t'.is_control()); + /// assert!('\n'.is_control()); + /// assert!('\u{9C}'.is_control()); // STRING TERMINATOR /// assert!(!'q'.is_control()); /// ``` #[must_use] #[stable(feature = "rust1", since = "1.0.0")] + #[rustc_const_stable(feature = "const_is_control", since = "1.97.0")] #[inline] - pub fn is_control(self) -> bool { + pub const fn is_control(self) -> bool { // According to // https://www.unicode.org/policies/stability_policy.html#Property_Value, // the set of codepoints in `Cc` will never change. @@ -959,97 +1127,182 @@ impl char { matches!(self, '\0'..='\x1f' | '\x7f'..='\u{9f}') } - /// Returns `true` if this `char` has the `Grapheme_Extend` property. + /// Returns `true` if this `char` has the general category for [private-use characters]. + /// These characters do not have an interpretation specified by Unicode; individual programs + /// and users are free to assign them whatever meaning they like. /// - /// `Grapheme_Extend` is described in [Unicode Standard Annex #29 (Unicode Text - /// Segmentation)][uax29] and specified in the [Unicode Character Database][ucd] - /// [`DerivedCoreProperties.txt`]. + /// [private-use characters]: https://www.unicode.org/faq/private_use#private_use + /// + /// Private-use characters (code points with the general category of `Co`) are [described] in Chapter 23 + /// (Special Areas and Format Characters) of the Unicode Standard, and [specified] in the + /// Unicode Character Database [`UnicodeData.txt`]. The full set of private-use characters is + /// `'\u{E000}'..='\u{F8FF}' | '\u{F0000}'..='\u{FFFFD}' | '\u{100000}'..='\u{10FFFD}'`, + /// and will never change. + /// + /// [described]: https://www.unicode.org/versions/latest/core-spec/chapter-23/#G19184 + /// [specified]: https://www.unicode.org/reports/tr44/#GC_Values_Table + /// [`UnicodeData.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/UnicodeData.txt /// - /// [uax29]: https://www.unicode.org/reports/tr29/ - /// [ucd]: https://www.unicode.org/reports/tr44/ - /// [`DerivedCoreProperties.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/DerivedCoreProperties.txt #[must_use] + #[unstable(feature = "char_unassigned_private_use", issue = "158322")] #[inline] - pub(crate) fn is_grapheme_extended(self) -> bool { - !self.is_ascii() && unicode::Grapheme_Extend(self) + pub const fn is_private_use(self) -> bool { + // According to + // https://www.unicode.org/policies/stability_policy.html#Property_Value, + // the set of codepoints in `Co` will never change. + // So we can just hard-code the patterns to match against instead of using a table. + matches!(self, '\u{E000}'..='\u{F8FF}' | '\u{F0000}'..='\u{FFFFD}' | '\u{100000}'..='\u{10FFFD}') } - /// Returns `true` if this `char` has the `Cased` property. + /// Returns `true` if this `char` has the general category for format control characters. /// - /// `Cased` is described in Chapter 4 (Character Properties) of the [Unicode Standard] and - /// specified in the [Unicode Character Database][ucd] [`DerivedCoreProperties.txt`]. + /// Format controls (code points with the general category of `Cf`) are [described] in Chapter 4 + /// (Character Properties) of the Unicode Standard, and [specified] in the Unicode Character + /// Database [`UnicodeData.txt`]. /// - /// [Unicode Standard]: https://www.unicode.org/versions/latest/ - /// [ucd]: https://www.unicode.org/reports/tr44/ - /// [`DerivedCoreProperties.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/DerivedCoreProperties.txt + /// [described]: https://www.unicode.org/versions/latest/core-spec/chapter-4/#G134153 + /// [specified]: https://www.unicode.org/reports/tr44/#GC_Values_Table + /// [`UnicodeData.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/UnicodeData.txt + /// + /// # Examples + /// + /// Basic usage: + /// + /// ```ignore(private) + /// assert!('\u{AD}'.is_format_control()); // SOFT HYPHEN + /// assert!('\u{200B}'.is_format_control()); // ZERO WIDTH SPACE + /// assert!('\u{E0041}'.is_format_control()); // TAG LATIN CAPITAL LETTER A + /// assert!('۝'.is_format_control()); // ARABIC END OF AYAH + /// assert!('𓐲'.is_format_control()); // EGYPTIAN HIEROGLYPH INSERT AT TOP START + /// assert!(!'q'.is_format_control()); + /// ``` #[must_use] #[inline] - #[doc(hidden)] - #[unstable(feature = "char_internals", reason = "exposed only for libstd", issue = "none")] - pub fn is_cased(self) -> bool { - if self.is_ascii() { self.is_ascii_alphabetic() } else { unicode::Cased(self) } + fn is_format_control(self) -> bool { + self > '\u{AC}' && unicode::Cf(self) } - /// Returns `true` if this `char` has the `Case_Ignorable` property. + /// Returns `true` if this `char` has been assigned a meaning by Unicode, as of + /// [`UNICODE_VERSION`]. /// - /// `Case_Ignorable` is described in Chapter 4 (Character Properties) of the [Unicode Standard] and - /// specified in the [Unicode Character Database][ucd] [`DerivedCoreProperties.txt`]. + /// [`UNICODE_VERSION`]: Self::UNICODE_VERSION /// - /// [Unicode Standard]: https://www.unicode.org/versions/latest/ - /// [ucd]: https://www.unicode.org/reports/tr44/ - /// [`DerivedCoreProperties.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/DerivedCoreProperties.txt + /// Many of Unicode's [stability policies] apply only to assigned characters. + /// + /// [stability policies]: https://www.unicode.org/policies/stability_policy.html + /// + /// Currently unassigned characters (characters for which this method returns `false`) + /// may have a meaning assigned in a future version of Unicode, + /// except for the 66 [noncharacters] which will never be assigned a meaning. + /// + /// [noncharacters]: https://www.unicode.org/faq/private_use.html#noncharacters + /// + /// A character is considered assigned if it is present in [`UnicodeData.txt`]. + /// Unassigned characters have general category `Cn`, as [described] in Chapter 4 + /// (Character Properties) of the Unicode Standard. + /// + /// [`UnicodeData.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/UnicodeData.txt + /// [described]: https://www.unicode.org/versions/latest/core-spec/chapter-4/#G134153 + /// + /// # Examples + /// + /// Basic usage: + /// + /// ``` + /// #![feature(char_unassigned_private_use)] + /// assert!('γ'.is_assigned()); // once a character is assigned, it stays assigned forever + /// assert!(!'\u{FFFE}'.is_assigned()); // noncharacter, will never be assigned + /// + /// // Not currently assigned, but may be in the future, + /// // so we shouldn't rely on the current status + /// /* assert!(!'\u{7AAAA}'.is_assigned()); */ + /// ``` #[must_use] + #[unstable(feature = "char_unassigned_private_use", issue = "158322")] #[inline] - #[doc(hidden)] - #[unstable(feature = "char_internals", reason = "exposed only for libstd", issue = "none")] - pub fn is_case_ignorable(self) -> bool { - if self.is_ascii() { - matches!(self, '\'' | '.' | ':' | '^' | '`') - } else { - unicode::Case_Ignorable(self) + pub fn is_assigned(self) -> bool { + match self { + '\0'..='\u{377}' => true, + '\u{378}'..='\u{3FFFD}' => !unicode::Cn_planes_0_3(self), + // Assigned character ranges in planes 4 and above. + // `src/tools/unicode-table-generator/src/main.rs` asserts that this is correct + '\u{E0001}' + | '\u{E0020}'..='\u{E007F}' + | '\u{E0100}'..='\u{E01EF}' + | '\u{F0000}'..='\u{FFFFD}' + | '\u{100000}'..='\u{10FFFD}' => true, + _ => false, } } - /// Returns `true` if this `char` has one of the general categories for numbers. - /// - /// The general categories for numbers (`Nd` for decimal digits, `Nl` for letter-like numeric - /// characters, and `No` for other numeric characters) are specified in the [Unicode Character - /// Database][ucd] [`UnicodeData.txt`]. + /// Returns `true` if this `char` has the `Default_Ignorable_Code_Point` property. + /// These characters [should be displayed as invisible in fallback rendering](https://www.unicode.org/faq/unsup_char#3). /// - /// This method doesn't cover everything that could be considered a number, e.g. ideographic numbers like '三'. - /// If you want everything including characters with overlapping purposes then you might want to use - /// a unicode or language-processing library that exposes the appropriate character properties instead - /// of looking at the unicode categories. - /// - /// If you want to parse ASCII decimal digits (0-9) or ASCII base-N, use - /// `is_ascii_digit` or `is_digit` instead. + /// `Default_Ignorable_Code_Point` is [described] in Chapter 5 (Implementation Guidelines) of the Unicode Standard, + /// and [specified] in the Unicode Character Database [`DerivedCoreProperties.txt`]. /// - /// [Unicode Standard]: https://www.unicode.org/versions/latest/ - /// [ucd]: https://www.unicode.org/reports/tr44/ - /// [`UnicodeData.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/UnicodeData.txt + /// [described]: https://www.unicode.org/versions/latest/core-spec/chapter-5/#G40120 + /// [specified]: https://www.unicode.org/reports/tr44/#Default_Ignorable_Code_Point + /// [`DerivedCoreProperties.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/DerivedCoreProperties.txt /// /// # Examples /// /// Basic usage: /// /// ``` - /// assert!('٣'.is_numeric()); - /// assert!('7'.is_numeric()); - /// assert!('৬'.is_numeric()); - /// assert!('¾'.is_numeric()); - /// assert!('①'.is_numeric()); - /// assert!(!'K'.is_numeric()); - /// assert!(!'و'.is_numeric()); - /// assert!(!'藏'.is_numeric()); - /// assert!(!'三'.is_numeric()); + /// #![feature(default_ignorable)] + /// assert!('\u{AD}'.is_default_ignorable()); // SOFT HYPHEN + /// assert!('\u{115F}'.is_default_ignorable()); // HANGUL CHOSEONG FILLER + /// assert!('\u{200B}'.is_default_ignorable()); // ZERO WIDTH SPACE + /// assert!('\u{E0041}'.is_default_ignorable()); // TAG LATIN CAPITAL LETTER A + /// assert!(!'۝'.is_default_ignorable()); // ARABIC END OF AYAH + /// assert!(!'𓐲'.is_default_ignorable()); // EGYPTIAN HIEROGLYPH INSERT AT TOP START + /// assert!(!' '.is_default_ignorable()); + /// assert!(!'\n'.is_default_ignorable()); + /// assert!(!'\0'.is_default_ignorable()); + /// assert!(!'q'.is_default_ignorable()); /// ``` #[must_use] - #[stable(feature = "rust1", since = "1.0.0")] + #[unstable(feature = "default_ignorable", issue = "160583")] #[inline] - pub fn is_numeric(self) -> bool { - match self { - '0'..='9' => true, - c => c > '\x7f' && unicode::N(c), + pub fn is_default_ignorable(self) -> bool { + self > '\u{AC}' && unicode::Default_Ignorable_Code_Point(self) + } + + /// Returns `true` if this `char` has the `Grapheme_Extend` property. + /// + /// `Grapheme_Extend` is [described] in Chapter 3 (Conformance) of the Unicode Standard, + /// and [specified] in the Unicode Character Database [`DerivedCoreProperties.txt`]. + /// + /// [described]: https://www.unicode.org/versions/latest/core-spec/chapter-3/#G41165 + /// [specified]: https://www.unicode.org/reports/tr44/#Grapheme_Extend + /// [`DerivedCoreProperties.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/DerivedCoreProperties.txt + #[must_use] + #[inline] + fn is_grapheme_extender(self) -> bool { + self > '\u{02FF}' && unicode::Grapheme_Extend(self) + } + + /// Returns `true` if this `char` has the `Case_Ignorable` property. This narrow-use property + /// is used to implement context-dependent casing for the Greek letter sigma (uppercase 'Σ'), + /// which has two lowercase forms. + /// + /// `Case_Ignorable` is [described] in Chapter 3 (Conformance) of the Unicode Core Specification, + /// and [specified] in the Unicode Character Database [`DerivedCoreProperties.txt`]. + /// See those resources, as well as [`to_lowercase()`]'s documentation, for more information. + /// + /// [described]: https://www.unicode.org/versions/latest/core-spec/chapter-3/#G63116 + /// [specified]: https://www.unicode.org/reports/tr44/#Case_Ignorable + /// [`DerivedCoreProperties.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/DerivedCoreProperties.txt + /// [`to_lowercase()`]: Self::to_lowercase() + #[must_use] + #[inline] + #[unstable(feature = "case_ignorable", issue = "154848")] + pub fn is_case_ignorable(self) -> bool { + if self.is_ascii() { + matches!(self, '\'' | '.' | ':' | '^' | '`') + } else { + unicode::Case_Ignorable(self) } } @@ -1064,13 +1317,12 @@ impl char { /// [ucd]: https://www.unicode.org/reports/tr44/ /// [`UnicodeData.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/UnicodeData.txt /// - /// If this `char` requires special considerations (e.g. multiple `char`s) the iterator yields - /// the `char`(s) given by [`SpecialCasing.txt`]. - /// - /// [`SpecialCasing.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/SpecialCasing.txt + /// If this `char` expands to multiple `char`s, the iterator yields the `char`s given by + /// [`SpecialCasing.txt`]. The maximum number of `char`s in a case mapping is 3. /// /// This operation performs an unconditional mapping without tailoring. That is, the conversion - /// is independent of context and language. + /// is independent of context and language. See [below](#notes-on-context-and-locale) + /// for more information. /// /// In the [Unicode Standard], Chapter 4 (Character Properties) discusses case mapping in /// general and Chapter 3 (Conformance) discusses the default algorithm for case conversion. @@ -1112,7 +1364,62 @@ impl char { /// // convert into themselves. /// assert_eq!('山'.to_lowercase().to_string(), "山"); /// ``` - #[must_use = "this returns the lowercase character as a new iterator, \ + /// # Notes on context and locale + /// + /// As stated earlier, this method does not take into account language or context. + /// Below is a non-exhaustive list of situations where this can be relevant. + /// If you need to handle locale-depedendent casing in your code, consider using + /// an external crate, like [`icu_casemap`](https://crates.io/crates/icu_casemap) + /// which is developed by Unicode. + /// + /// ## Greek sigma + /// + /// In Greek, the letter simga (uppercase 'Σ') has two lowercase forms: + /// 'σ' which is used in most situations, and 'ς' which appears only + /// at the end of a word. [`char::to_lowercase()`] always uses the first form: + /// + /// ``` + /// assert_eq!('Σ'.to_lowercase().to_string(), "σ"); + /// ``` + /// + /// `str::to_lowercase()` (only available with the `alloc` crate) + /// *does* properly handle this contextual mapping, + /// so prefer using that method if you can. Alternatively, you can use + /// [`is_cased()`] and [`is_case_ignorable()`] to implement it yourself. + /// See `Final_Sigma` in [Table 3.17] of the Unicode Standard, + /// along with [`SpecialCasing.txt`], for more details. + /// + /// [`is_cased()`]: Self::is_cased() + /// [`is_case_ignorable()`]: Self::is_case_ignorable() + /// [Table 3.17]: https://www.unicode.org/versions/latest/core-spec/chapter-3/#G54277 + /// + /// ## Turkish and Azeri I/ı/İ/i + /// + /// In Turkish and Azeri, the equivalent of 'i' in Latin has five forms instead of two: + /// + /// * 'Dotless': I / ı, sometimes written ï + /// * 'Dotted': İ / i + /// + /// Note that the uppercase undotted 'I' is the same codepoint as the Latin. Therefore: + /// + /// ``` + /// let lower_i = 'I'.to_lowercase().to_string(); + /// ``` + /// + /// `'I'`'s correct lowercase relies on the language of the text: if we're + /// in `en-US`, it should be `"i"`, but if we're in `tr-TR` or `az-AZ`, it should + /// be `"ı"`. `to_lowercase()` does not take this into account, and so: + /// + /// ``` + /// let lower_i = 'I'.to_lowercase().to_string(); + /// + /// assert_eq!(lower_i, "i"); + /// ``` + /// + /// holds across languages. + /// + /// [`SpecialCasing.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/SpecialCasing.txt + #[must_use = "this returns the lowercased character as a new iterator, \ without modifying the original"] #[stable(feature = "rust1", since = "1.0.0")] #[inline] @@ -1120,9 +1427,192 @@ impl char { ToLowercase(CaseMappingIter::new(conversions::to_lower(self))) } + /// Returns an iterator that yields the titlecase mapping of this `char` as one or more + /// `char`s. + /// + /// This is usually, but not always, equivalent to the uppercase mapping + /// returned by [`to_uppercase()`]. Prefer this method when seeking to capitalize + /// Only The First Letter of a word, but use [`to_uppercase()`] for ALL CAPS. + /// See [below](#difference-from-uppercase) for a thorough explanation + /// of the difference between the two methods. + /// + /// If this `char` does not have a titlecase mapping, the iterator yields the same `char`. + /// + /// If this `char` has a one-to-one titlecase mapping given by the [Unicode Character + /// Database][ucd] [`UnicodeData.txt`], the iterator yields that `char`. + /// + /// [ucd]: https://www.unicode.org/reports/tr44/ + /// [`UnicodeData.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/UnicodeData.txt + /// + /// If this `char` expands to multiple `char`s, the iterator yields the `char`s given by + /// [`SpecialCasing.txt`]. The maximum number of `char`s in a case mapping is 3. + /// + /// [`SpecialCasing.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/SpecialCasing.txt + /// + /// This operation performs an unconditional mapping without tailoring. That is, the conversion + /// is independent of context and language. See [below](#note-on-locale) + /// for more information. + /// + /// In the [Unicode Standard], Chapter 4 (Character Properties) discusses case mapping in + /// general and Chapter 3 (Conformance) discusses the default algorithm for case conversion. + /// + /// [Unicode Standard]: https://www.unicode.org/versions/latest/ + /// + /// # Examples + /// + /// As an iterator: + /// + /// ``` + /// #![feature(titlecase)] + /// for c in 'ß'.to_titlecase() { + /// print!("{c}"); + /// } + /// println!(); + /// ``` + /// + /// Using `println!` directly: + /// + /// ``` + /// #![feature(titlecase)] + /// println!("{}", 'ß'.to_titlecase()); + /// ``` + /// + /// Both are equivalent to: + /// + /// ``` + /// println!("Ss"); + /// ``` + /// + /// Using [`to_string`](../std/string/trait.ToString.html#tymethod.to_string): + /// + /// ``` + /// #![feature(titlecase)] + /// assert_eq!('c'.to_titlecase().to_string(), "C"); + /// assert_eq!('ა'.to_titlecase().to_string(), "ა"); + /// assert_eq!('dž'.to_titlecase().to_string(), "Dž"); + /// assert_eq!('ᾨ'.to_titlecase().to_string(), "ᾨ"); + /// + /// // Sometimes the result is more than one character: + /// assert_eq!('ß'.to_titlecase().to_string(), "Ss"); + /// + /// // Characters that do not have separate cased forms + /// // convert into themselves. + /// assert_eq!('山'.to_titlecase().to_string(), "山"); + /// ``` + /// + /// # Difference from uppercase + /// + /// Currently, there are three classes of characters where [`to_uppercase()`] + /// and `to_titlecase()` give different results: + /// + /// ## Georgian script + /// + /// Each letter in the modern Georgian alphabet can be written in one of two forms: + /// the typical lowercase-like "mkhedruli" form, and a variant uppercase-like "mtavruli" + /// form. However, unlike uppercase in most cased scripts, mtavruli is not typically used + /// to start sentences, denote proper nouns, or for any other purpose + /// in running text. It is instead confined to titles and headings, which are written entirely + /// in mtavruli. For this reason, [`to_uppercase()`] applied to a Georgian letter + /// will return the mtavruli form, but `to_titlecase()` will return the mkhedruli form. + /// + /// ``` + /// #![feature(titlecase)] + /// let ani = 'ა'; // First letter of the Georgian alphabet, in mkhedruli form + /// + /// // Titlecasing mkhedruli maps it to itself... + /// assert_eq!(ani.to_titlecase().to_string(), ani.to_string()); + /// + /// // but uppercasing it maps it to mtavruli + /// assert_eq!(ani.to_uppercase().to_string(), "Ა"); + /// ``` + /// + /// ## Compatibility digraphs for Latin-alphabet Serbo-Croatian + /// + /// The standard Latin alphabet for the Serbo-Croatian language + /// (Bosnian, Croatian, Montenegrin, and Serbian) contains + /// three digraphs: Dž, Lj, and Nj. These are usually represented as + /// two characters. However, for compatibility with older character sets, + /// Unicode includes single-character versions of these digraphs. + /// Each has a uppercase, titlecase, and lowercase version: + /// + /// - `'DŽ'`, `'Dž'`, `'dž'` + /// - `'LJ'`, `'Lj'`, `'lj'` + /// - `'NJ'`, `'Nj'`, `'nj'` + /// + /// Unicode additionally encodes a casing triad for the Dz digraph + /// without the caron: `'DZ'`, `'Dz'`, `'dz'`. + /// + /// ## Iota-subscritped Greek vowels + /// + /// In ancient Greek, the long vowels alpha (α), eta (η), and omega (ω) + /// were sometimes followed by an iota (ι), forming a diphthong. Over time, + /// the diphthong pronunciation was slowly lost, with the iota becoming mute. + /// Eventually, the ι disappeared from the spelling as well. + /// However, there remains a need to represent ancient texts faithfully. + /// + /// Modern editions of ancient Greek texts commonly use a reduced-sized + /// ι symbol to denote mute iotas, while distinguishing them from ιs + /// which continued to affect pronunciation. The exact standard differs + /// between different publications. Some render the mute ι below its associated + /// vowel (subscript), while others place it to the right of said vowel (adscript). + /// The interaction of mute ι symbols with casing also varies. + /// + /// The Unicode Standard, for its default casing rules, chose to make lowercase + /// Greek vowels with iota subscipt (e.g. `'ᾠ'`) titlecase to the uppercase vowel + /// with iota subscript (`'ᾨ'`) but uppercase to the uppercase vowel followed by + /// full-size uppercase iota (`"ὨΙ"`). This is just one convention among many + /// in common use, but it is the one Unicode settled on, + /// so it is what this method does also. + /// + /// # Note on locale + /// + /// As stated above, this method is locale-insensitive. + /// If you need locale support, consider using an external crate, + /// like [`icu_casemap`](https://crates.io/crates/icu_casemap) + /// which is developed by Unicode. A description of one common + /// locale-dependent casing issue follows (there are others): + /// + /// In Turkish and Azeri, the equivalent of 'i' in Latin has five forms instead of two: + /// + /// * 'Dotless': I / ı, sometimes written ï + /// * 'Dotted': İ / i + /// + /// Note that the lowercase dotted 'i' is the same codepoint as the Latin. Therefore: + /// + /// ``` + /// #![feature(titlecase)] + /// let upper_i = 'i'.to_titlecase().to_string(); + /// ``` + /// + /// `'i'`'s correct titlecase relies on the language of the text: if we're + /// in `en-US`, it should be `"I"`, but if we're in `tr-TR` or `az-AZ`, it should + /// be `"İ"`. `to_titlecase()` does not take this into account, and so: + /// + /// ``` + /// #![feature(titlecase)] + /// let upper_i = 'i'.to_titlecase().to_string(); + /// + /// assert_eq!(upper_i, "I"); + /// ``` + /// + /// holds across languages. + /// + /// [`to_uppercase()`]: Self::to_uppercase() + #[must_use = "this returns the titlecased character as a new iterator, \ + without modifying the original"] + #[unstable(feature = "titlecase", issue = "153892")] + #[inline] + pub fn to_titlecase(self) -> ToTitlecase { + ToTitlecase(CaseMappingIter::new(conversions::to_title(self))) + } + /// Returns an iterator that yields the uppercase mapping of this `char` as one or more /// `char`s. /// + /// Prefer this method when converting a word into ALL CAPS, but consider [`to_titlecase()`] + /// instead if you seek to capitalize Only The First Letter. See that method's documentation + /// for more information on the difference between the two. + /// /// If this `char` does not have an uppercase mapping, the iterator yields the same `char`. /// /// If this `char` has a one-to-one uppercase mapping given by the [Unicode Character @@ -1131,13 +1621,14 @@ impl char { /// [ucd]: https://www.unicode.org/reports/tr44/ /// [`UnicodeData.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/UnicodeData.txt /// - /// If this `char` requires special considerations (e.g. multiple `char`s) the iterator yields - /// the `char`(s) given by [`SpecialCasing.txt`]. + /// If this `char` expands to multiple `char`s, the iterator yields the `char`s given by + /// [`SpecialCasing.txt`]. The maximum number of `char`s in a case mapping is 3. /// /// [`SpecialCasing.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/SpecialCasing.txt /// /// This operation performs an unconditional mapping without tailoring. That is, the conversion - /// is independent of context and language. + /// is independent of context and language. See [below](#note-on-locale) + /// for more information. /// /// In the [Unicode Standard], Chapter 4 (Character Properties) discusses case mapping in /// general and Chapter 3 (Conformance) discusses the default algorithm for case conversion. @@ -1145,6 +1636,7 @@ impl char { /// [Unicode Standard]: https://www.unicode.org/versions/latest/ /// /// # Examples + /// /// `'ſt'` (U+FB05) is a single Unicode code point (a ligature) that maps to "ST" in uppercase. /// /// As an iterator: @@ -1172,9 +1664,12 @@ impl char { /// /// ``` /// assert_eq!('c'.to_uppercase().to_string(), "C"); + /// assert_eq!('ა'.to_uppercase().to_string(), "Ა"); + /// assert_eq!('dž'.to_uppercase().to_string(), "DŽ"); /// /// // Sometimes the result is more than one character: /// assert_eq!('ſt'.to_uppercase().to_string(), "ST"); + /// assert_eq!('ᾨ'.to_uppercase().to_string(), "ὨΙ"); /// /// // Characters that do not have both uppercase and lowercase /// // convert into themselves. @@ -1183,19 +1678,25 @@ impl char { /// /// # Note on locale /// - /// In Turkish, the equivalent of 'i' in Latin has five forms instead of two: + /// As stated above, this method is locale-insensitive. + /// If you need locale support, consider using an external crate, + /// like [`icu_casemap`](https://crates.io/crates/icu_casemap) + /// which is developed by Unicode. A description of one common + /// locale-dependent casing issue follows (there are others): + /// + /// In Turkish and Azeri, the equivalent of 'i' in Latin has five forms instead of two: /// /// * 'Dotless': I / ı, sometimes written ï /// * 'Dotted': İ / i /// - /// Note that the lowercase dotted 'i' is the same as the Latin. Therefore: + /// Note that the lowercase dotted 'i' is the same codepoint as the Latin. Therefore: /// /// ``` /// let upper_i = 'i'.to_uppercase().to_string(); /// ``` /// - /// The value of `upper_i` here relies on the language of the text: if we're - /// in `en-US`, it should be `"I"`, but if we're in `tr_TR`, it should + /// `'i'`'s correct uppercase relies on the language of the text: if we're + /// in `en-US`, it should be `"I"`, but if we're in `tr-TR` or `az-AZ`, it should /// be `"İ"`. `to_uppercase()` does not take this into account, and so: /// /// ``` @@ -1205,7 +1706,9 @@ impl char { /// ``` /// /// holds across languages. - #[must_use = "this returns the uppercase character as a new iterator, \ + /// + /// [`to_titlecase()`]: Self::to_titlecase() + #[must_use = "this returns the uppercased character as a new iterator, \ without modifying the original"] #[stable(feature = "rust1", since = "1.0.0")] #[inline] @@ -1213,6 +1716,132 @@ impl char { ToUppercase(CaseMappingIter::new(conversions::to_upper(self))) } + /// Returns an iterator that yields the case folding of this `char` as one or more + /// `char`s. + /// + /// Case folding is meant to be used when performing case-insensitive string comparisons. + /// Case-folded strings should not usually be exposed directly to users. For most, + /// but not all, characters, the casefold mapping is identical to the lowercase one. + /// + /// This iterator yields the `char`(s) in the common or full case folding for this `char`, + /// as given by the [Unicode Character Database][ucd] [`CaseFolding.txt`]. + /// The maximum number of `char`s in a case folding is 3. + /// + /// [ucd]: https://www.unicode.org/reports/tr44/ + /// [`CaseFolding.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/CaseFolding.txt + /// + /// + /// No [normalization] (e.g. NFC) is performed, so visually and semantically identical characters + /// might still casefold differently. For example, `'ά'` (U+03AC GREEK SMALL LETTER ALPHA WITH TONOS) + /// is considered distinct from `'ά'` (U+1F71 GREEK SMALL LETTER ALPHA WITH OXIA), + /// even though Unicode considers them canonically equivalent. + /// + /// In addition, this method is independent of language/locale, + /// so the special behavior of I/ı/İ/i in Turkish and Azeri is not handled. + /// + /// In the [Unicode Standard], Chapter 4 (Character Properties) discusses case folding in + /// general and Chapter 3 (Conformance) discusses the default algorithm for case folding. + /// + /// [Unicode Standard]: https://www.unicode.org/versions/latest/ + /// + /// # Examples + /// + /// The German sharp S `'ß'` (U+DF) is a single Unicode code point + /// that casefolds to `"ss"`. Its uppercase variant '`ẞ`' (U+1E9E) + /// has the same case-folding. + /// + /// As an iterator: + /// + /// ``` + /// #![feature(casefold)] + /// assert!('ß'.to_casefold_unnormalized().eq(['s', 's'])); + /// assert!('ẞ'.to_casefold_unnormalized().eq(['s', 's'])); + /// ``` + /// + /// Using [`to_string`](../std/string/trait.ToString.html#tymethod.to_string): + /// + /// ``` + /// #![feature(casefold)] + /// assert_eq!('ß'.to_casefold_unnormalized().to_string(), "ss"); + /// assert_eq!('ẞ'.to_casefold_unnormalized().to_string(), "ss"); + /// ``` + /// + /// No [normalization] is performed: + /// + /// ```rust + /// #![feature(casefold)] + /// // These two characters are visually and semantically identical; + /// // Unicode considers them to be canonically equivalent. + /// let alpha_tonos = 'ά'; + /// let alpha_oxia = 'ά'; + /// + /// // However, they are different codepoints: + /// assert_eq!(alpha_tonos, '\u{03AC}'); + /// assert_eq!(alpha_oxia, '\u{1F71}'); + /// + /// // Their case-foldings are likewise unequal: + /// assert!(alpha_tonos.to_casefold_unnormalized().eq(['\u{03AC}'])); + /// assert!(alpha_oxia.to_casefold_unnormalized().eq(['\u{1F71}'])); + /// ``` + /// + /// # Note on locale + /// + /// In Turkish and Azeri, the equivalent of 'i' in Latin has five forms instead of two: + /// + /// * 'Dotless': I / ı, sometimes written ï + /// * 'Dotted': İ / i + /// + /// Note that the uppercase undotted 'I' is the same codepoint as the Latin. Therefore: + /// + /// ``` + /// #![feature(casefold)] + /// let casefold_i = 'I'.to_casefold_unnormalized().to_string(); + /// ``` + /// + /// `'I'`'s correct case folding relies on the language of the text: if we're + /// in `en-US`, it should be `"i"`, but if we're in `tr-TR` or `az-AZ`, it should + /// be `"ı"`. `to_casefold_unnormalized()` does not take this into account, and so: + /// + /// ``` + /// #![feature(casefold)] + /// let casefold_i = 'I'.to_casefold_unnormalized().to_string(); + /// + /// assert_eq!(casefold_i, "i"); + /// ``` + /// + /// holds across languages. + /// + /// [normalization]: https://www.unicode.org/faq/normalization.html + #[must_use = "this returns the case-folded character as a new iterator, \ + without modifying the original"] + #[unstable(feature = "casefold", issue = "157000")] + #[inline] + pub fn to_casefold_unnormalized(self) -> ToCasefold { + ToCasefold(CaseMappingIter::new(conversions::to_casefold(self))) + } + + /// Returns the code point value as a `u32`. + /// + /// # Examples + /// + /// ``` + /// #![feature(char_to_u32)] + /// + /// let ascii = 'a'; + /// let heart = '❤'; + /// + /// assert_eq!(ascii.to_u32(), 97_u32); + /// assert_eq!(heart.to_u32(), 0x2764_u32); + /// ``` + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[unstable(feature = "char_to_u32", issue = "158938")] + #[rustc_const_unstable(feature = "char_to_u32", issue = "158938")] + #[inline(always)] + pub const fn to_u32(self) -> u32 { + self as u32 + } + /// Checks if the value is within the ASCII range. /// /// # Examples @@ -1448,7 +2077,7 @@ impl char { #[rustc_const_stable(feature = "const_ascii_ctype_on_intrinsics", since = "1.47.0")] #[inline] pub const fn is_ascii_alphabetic(&self) -> bool { - matches!(*self, 'A'..='Z' | 'a'..='z') + matches!(*self, 'a'..='z' | 'A'..='Z') } /// Checks if the value is an ASCII uppercase character: @@ -1658,7 +2287,8 @@ impl char { matches!(*self, '0'..='9') | matches!(*self, 'A'..='F') | matches!(*self, 'a'..='f') } - /// Checks if the value is an ASCII punctuation character: + /// Checks if the value is an ASCII punctuation or symbol character + /// (i.e. not alphanumeric, whitespace, or control): /// /// - U+0021 ..= U+002F `! " # $ % & ' ( ) * + , - . /`, or /// - U+003A ..= U+0040 `: ; < = > ? @`, or @@ -1699,7 +2329,8 @@ impl char { | matches!(*self, '{'..='~') } - /// Checks if the value is an ASCII graphic character: + /// Checks if the value is an ASCII graphic character + /// (i.e. not whitespace or control): /// U+0021 '!' ..= U+007E '~'. /// /// # Examples @@ -1737,6 +2368,9 @@ impl char { /// U+0020 SPACE, U+0009 HORIZONTAL TAB, U+000A LINE FEED, /// U+000C FORM FEED, or U+000D CARRIAGE RETURN. /// + /// **Warning:** Because the list above excludes U+000B VERTICAL TAB, + /// `c.is_ascii_whitespace()` is **not** equivalent to `c.is_ascii() && c.is_whitespace()`. + /// /// Rust uses the WhatWG Infra Standard's [definition of ASCII /// whitespace][infra-aw]. There are several other definitions in /// wide use. For instance, [the POSIX locale][pct] includes @@ -1750,8 +2384,8 @@ impl char { /// before using this function. /// /// [infra-aw]: https://infra.spec.whatwg.org/#ascii-whitespace - /// [pct]: https://pubs.opengroup.org/onlinepubs/9699919799/basedefs/V1_chap07.html#tag_07_03_01 - /// [bfs]: https://pubs.opengroup.org/onlinepubs/9699919799/utilities/V3_chap02.html#tag_18_06_05 + /// [pct]: https://pubs.opengroup.org/onlinepubs/9799919799/basedefs/V1_chap07.html#tag_07_03_01 + /// [bfs]: https://pubs.opengroup.org/onlinepubs/9799919799/utilities/V3_chap02.html#tag_19_06_05 /// /// # Examples /// @@ -1822,8 +2456,15 @@ impl char { } pub(crate) struct EscapeDebugExtArgs { - /// Escape Extended Grapheme codepoints? - pub(crate) escape_grapheme_extended: bool, + /// Escape Grapheme Extender codepoints? + /// + /// Note that this excludes + /// U+FF9E HALFWIDTH KATAKANA VOICED SOUND MARK + /// and U+FF9F HALFWIDTH KATAKANA SEMI-VOICED SOUND MARK, + /// which are never escaped, as graphically + /// they are not combining. See + /// for background on these characters. + pub(crate) escape_grapheme_extender: bool, /// Escape single quotes? pub(crate) escape_single_quote: bool, @@ -1834,7 +2475,7 @@ pub(crate) struct EscapeDebugExtArgs { impl EscapeDebugExtArgs { pub(crate) const ESCAPE_ALL: Self = Self { - escape_grapheme_extended: true, + escape_grapheme_extender: true, escape_single_quote: true, escape_double_quote: true, }; diff --git a/library/core/src/char/mod.rs b/library/core/src/char/mod.rs index eed3514716838..e3d5069f3aadb 100644 --- a/library/core/src/char/mod.rs +++ b/library/core/src/char/mod.rs @@ -97,31 +97,31 @@ const MAX_THREE_B: u32 = 0x10000; /// The highest valid code point a `char` can have, `'\u{10FFFF}'`. Use [`char::MAX`] instead. #[stable(feature = "rust1", since = "1.0.0")] +#[deprecated(since = "TBD", note = "replaced by the `MAX` associated constant on `char`")] pub const MAX: char = char::MAX; -/// The maximum number of bytes required to [encode](char::encode_utf8) a `char` to -/// UTF-8 encoding. -#[unstable(feature = "char_max_len", issue = "121714")] -pub const MAX_LEN_UTF8: usize = char::MAX_LEN_UTF8; - -/// The maximum number of two-byte units required to [encode](char::encode_utf16) a `char` -/// to UTF-16 encoding. -#[unstable(feature = "char_max_len", issue = "121714")] -pub const MAX_LEN_UTF16: usize = char::MAX_LEN_UTF16; - /// `U+FFFD REPLACEMENT CHARACTER` (�) is used in Unicode to represent a /// decoding error. Use [`char::REPLACEMENT_CHARACTER`] instead. #[stable(feature = "decode_utf16", since = "1.9.0")] +#[deprecated( + since = "TBD", + note = "replaced by the `REPLACEMENT_CHARACTER` associated constant on `char`" +)] pub const REPLACEMENT_CHARACTER: char = char::REPLACEMENT_CHARACTER; /// The version of [Unicode](https://www.unicode.org/) that the Unicode parts of /// `char` and `str` methods are based on. Use [`char::UNICODE_VERSION`] instead. #[stable(feature = "unicode_version", since = "1.45.0")] +#[deprecated( + since = "TBD", + note = "replaced by the `UNICODE_VERSION` associated constant on `char`" +)] pub const UNICODE_VERSION: (u8, u8, u8) = char::UNICODE_VERSION; /// Creates an iterator over the UTF-16 encoded code points in `iter`, returning /// unpaired surrogates as `Err`s. Use [`char::decode_utf16`] instead. #[stable(feature = "decode_utf16", since = "1.9.0")] +#[deprecated(since = "TBD", note = "replaced by the `decode_utf16` method on `char`")] #[inline] pub fn decode_utf16>(iter: I) -> DecodeUtf16 { self::decode::decode_utf16(iter) @@ -130,6 +130,7 @@ pub fn decode_utf16>(iter: I) -> DecodeUtf16 Option { @@ -140,6 +141,7 @@ pub const fn from_u32(i: u32) -> Option { /// instead. #[stable(feature = "char_from_unchecked", since = "1.5.0")] #[rustc_const_stable(feature = "const_char_from_u32_unchecked", since = "1.81.0")] +#[deprecated(since = "TBD", note = "replaced by the `from_u32_unchecked` method on `char`")] #[must_use] #[inline] #[requires(i <= 0x10FFFF && (i < 0xD800 || i > 0xDFFF))] @@ -151,6 +153,7 @@ pub const unsafe fn from_u32_unchecked(i: u32) -> char { /// Converts a digit in the given radix to a `char`. Use [`char::from_digit`] instead. #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_stable(feature = "const_char_convert", since = "1.67.0")] +#[deprecated(since = "TBD", note = "replaced by the `from_digit` method on `char`")] #[must_use] #[inline] pub const fn from_digit(num: u32, radix: u32) -> Option { @@ -368,13 +371,21 @@ impl fmt::Display for EscapeDebug { } macro_rules! casemappingiter_impls { - ($(#[$attr:meta])* $ITER_NAME:ident) => { + ( + #[$stab:meta] + #[$dendstab:meta] + #[$fusedstab:meta] + #[$exactstab:meta] + #[$displaystab:meta] + $(#[$attr:meta])* + $ITER_NAME:ident + ) => { $(#[$attr])* - #[stable(feature = "rust1", since = "1.0.0")] + #[$stab] #[derive(Debug, Clone)] pub struct $ITER_NAME(CaseMappingIter); - #[stable(feature = "rust1", since = "1.0.0")] + #[$stab] impl Iterator for $ITER_NAME { type Item = char; fn next(&mut self) -> Option { @@ -411,7 +422,7 @@ macro_rules! casemappingiter_impls { } } - #[stable(feature = "case_mapping_double_ended", since = "1.59.0")] + #[$dendstab] impl DoubleEndedIterator for $ITER_NAME { fn next_back(&mut self) -> Option { self.0.next_back() @@ -429,10 +440,10 @@ macro_rules! casemappingiter_impls { } } - #[stable(feature = "fused", since = "1.26.0")] + #[$fusedstab] impl FusedIterator for $ITER_NAME {} - #[stable(feature = "exact_size_case_mapping_iter", since = "1.35.0")] + #[$exactstab] impl ExactSizeIterator for $ITER_NAME { fn len(&self) -> usize { self.0.len() @@ -459,7 +470,7 @@ macro_rules! casemappingiter_impls { #[unstable(feature = "std_internals", issue = "none")] unsafe impl TrustedRandomAccess for $ITER_NAME {} - #[stable(feature = "char_struct_display", since = "1.16.0")] + #[$displaystab] impl fmt::Display for $ITER_NAME { #[inline] fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { @@ -470,6 +481,41 @@ macro_rules! casemappingiter_impls { } casemappingiter_impls! { + #[stable(feature = "rust1", since = "1.0.0")] + #[stable(feature = "case_mapping_double_ended", since = "1.59.0")] + #[stable(feature = "fused", since = "1.26.0")] + #[stable(feature = "exact_size_case_mapping_iter", since = "1.35.0")] + #[stable(feature = "char_struct_display", since = "1.16.0")] + /// Returns an iterator that yields the uppercase equivalent of a `char`. + /// + /// This `struct` is created by the [`to_uppercase`] method on [`char`]. See + /// its documentation for more. + /// + /// [`to_uppercase`]: char::to_uppercase + ToUppercase +} + +casemappingiter_impls! { + #[unstable(feature = "titlecase", issue = "153892")] + #[unstable(feature = "titlecase", issue = "153892")] + #[unstable(feature = "titlecase", issue = "153892")] + #[unstable(feature = "titlecase", issue = "153892")] + #[unstable(feature = "titlecase", issue = "153892")] + /// Returns an iterator that yields the titlecase equivalent of a `char`. + /// + /// This `struct` is created by the [`to_titlecase`] method on [`char`]. See + /// its documentation for more. + /// + /// [`to_titlecase`]: char::to_titlecase + ToTitlecase +} + +casemappingiter_impls! { + #[stable(feature = "rust1", since = "1.0.0")] + #[stable(feature = "case_mapping_double_ended", since = "1.59.0")] + #[stable(feature = "fused", since = "1.26.0")] + #[stable(feature = "exact_size_case_mapping_iter", since = "1.35.0")] + #[stable(feature = "char_struct_display", since = "1.16.0")] /// Returns an iterator that yields the lowercase equivalent of a `char`. /// /// This `struct` is created by the [`to_lowercase`] method on [`char`]. See @@ -480,13 +526,18 @@ casemappingiter_impls! { } casemappingiter_impls! { - /// Returns an iterator that yields the uppercase equivalent of a `char`. + #[unstable(feature = "casefold", issue = "157000")] + #[unstable(feature = "casefold", issue = "157000")] + #[unstable(feature = "casefold", issue = "157000")] + #[unstable(feature = "casefold", issue = "157000")] + #[unstable(feature = "casefold", issue = "157000")] + /// Returns an iterator that yields the case-folded equivalent of a `char`. /// - /// This `struct` is created by the [`to_uppercase`] method on [`char`]. See + /// This `struct` is created by the [`to_casefold_unnormalized`] method on [`char`]. See /// its documentation for more. /// - /// [`to_uppercase`]: char::to_uppercase - ToUppercase + /// [`to_casefold_unnormalized`]: char::to_casefold_unnormalized + ToCasefold } #[derive(Debug, Clone)] @@ -611,3 +662,23 @@ impl fmt::Display for TryFromCharError { #[stable(feature = "u8_from_char", since = "1.59.0")] impl Error for TryFromCharError {} + +/// The case of a cased character, +/// as returned by [`char::case`]. +/// +/// Titlecase characters conceptually are composed of an uppercase portion +/// followed by a lowercase portion. +/// The variant discriminants represent this: +/// the most significant bit represents whether the case +/// conceptually starts as uppercase, while the least significant bit +/// represents whether it conceptually ends as uppercase. +#[unstable(feature = "titlecase", issue = "153892")] +#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash, PartialOrd, Ord)] +pub enum CharCase { + /// Lowercase. Corresponds to the `Lowercase` Unicode property. + Lower = 0b00, + /// Titlecase. Corresponds to the `Titlecase_Letter` Unicode general category. + Title = 0b10, + /// Uppercase. Corresponds to the `Uppercase` Unicode property. + Upper = 0b11, +} diff --git a/library/core/src/clone.rs b/library/core/src/clone.rs index 85b09ee06f1fd..f124b8bceaded 100644 --- a/library/core/src/clone.rs +++ b/library/core/src/clone.rs @@ -275,7 +275,7 @@ pub const trait Clone: Sized { // lifetime-dependent. Therefore, if `TrivialClone` is implemented for any lifetime, // its invariant holds whenever `Clone` is implemented, even if the actual // `TrivialClone` bound would not be satisfied because of lifetime bounds. -#[rustc_unsafe_specialization_marker] +#[unsafe(rustc_allow_lifetime_dependent_specialization)] // If `#[derive(Clone, Clone, Copy)]` is written, there will be multiple // implementations of `TrivialClone`. To keep it from appearing in error // messages, make it a `#[marker]` trait. @@ -290,6 +290,107 @@ pub macro Clone($item:item) { /* compiler built-in */ } +/// A trait for types whose [`Clone`] operation creates another alias to the same +/// logical resource or shared state. +/// +/// `Share` refines the meaning of [`Clone`] for types where cloning a value +/// creates another handle, reference, or alias to the same logical resource or +/// shared state, rather than an independent owned value. The distinction is +/// semantic, not operational: `Share` does not mean merely that cloning is +/// cheap, constant-time, allocation-free, or convenient. +/// +/// `Share` is a third way to think about creating another usable value: +/// +/// * [`Copy`] may duplicate a value implicitly. +/// * [`Clone`] explicitly creates another value. +/// * `Share` explicitly creates another value that aliases the same underlying +/// logical resource or shared state. +/// +/// `Share` is not a replacement for either [`Copy`] or [`Clone`], and neither +/// trait implies it. For example, integers are [`Copy`] but not `Share`, because +/// copying an integer creates an independent value. Likewise, not every cheap +/// [`Clone`] implementation is `Share`. +/// +/// Shared references, `Rc`, `Arc`, `Sender`, and `SyncSender` are +/// examples of types that can be shared this way. Types such as `Vec`, +/// `String`, `Box`, owned collections, and similar owned values are not +/// `Share`, even though they implement [`Clone`], because cloning them creates +/// independent owned storage or value ownership. Mutable references (`&mut T`) +/// are neither `Clone` nor `Share`, because you cannot have two active at once. +/// +/// Calling [`share`](Share::share) is equivalent to calling [`clone`](Clone::clone) +/// for implementors, but communicates that the resulting value aliases the same +/// underlying resource. The `share` method is final, so implementors should +/// define the operation through [`Clone::clone`] and implement `Share` only when +/// those cloning semantics are clone-as-alias semantics. +/// +/// # Examples +/// +/// ``` +/// #![feature(share_trait)] +/// +/// use std::cell::Cell; +/// use std::clone::Share; +/// use std::rc::Rc; +/// use std::sync::{ +/// Arc, +/// atomic::{AtomicUsize, Ordering}, +/// }; +/// +/// let value = 1; +/// let reference = &value; +/// assert!(std::ptr::eq(reference, reference.share())); +/// +/// let rc = Rc::new(Cell::new(2)); +/// let shared_rc = rc.share(); +/// assert!(Rc::ptr_eq(&rc, &shared_rc)); +/// shared_rc.set(3); +/// assert_eq!(rc.get(), 3); +/// +/// let arc = Arc::new(AtomicUsize::new(4)); +/// let shared_arc = arc.share(); +/// assert!(Arc::ptr_eq(&arc, &shared_arc)); +/// shared_arc.store(5, Ordering::Relaxed); +/// assert_eq!(arc.load(Ordering::Relaxed), 5); +/// ``` +/// +/// ``` +/// #![feature(share_trait)] +/// +/// use std::clone::Share; +/// use std::sync::mpsc::{channel, sync_channel}; +/// +/// let (sender, receiver) = channel(); +/// let shared_sender = sender.share(); +/// sender.send(1).unwrap(); +/// shared_sender.send(2).unwrap(); +/// +/// let mut received = [receiver.recv().unwrap(), receiver.recv().unwrap()]; +/// received.sort(); +/// assert_eq!(received, [1, 2]); +/// +/// let (sync_sender, sync_receiver) = sync_channel(2); +/// let shared_sync_sender = sync_sender.share(); +/// sync_sender.send(3).unwrap(); +/// shared_sync_sender.send(4).unwrap(); +/// +/// let mut received = [sync_receiver.recv().unwrap(), sync_receiver.recv().unwrap()]; +/// received.sort(); +/// assert_eq!(received, [3, 4]); +/// ``` +#[unstable(feature = "share_trait", issue = "156756")] +pub trait Share: Clone { + /// Creates another alias to the same underlying resource or shared state. + /// + /// This is equivalent to calling [`Clone::clone`]. Use `share` at call + /// sites to make aliasing intent explicit; implementors define this + /// operation through [`Clone::clone`], not by overriding this method. + #[unstable(feature = "share_trait", issue = "156756")] + final fn share(&self) -> Self { + Clone::clone(self) + } +} + /// Trait for objects whose [`Clone`] impl is lightweight (e.g. reference-counted) /// /// Cloning an object implementing this trait should in general: @@ -601,7 +702,7 @@ unsafe impl CloneToUninit for crate::bstr::ByteStr { /// are implemented in `traits::SelectionContext::copy_clone_conditions()` /// in `rustc_trait_selection`. mod impls { - use super::TrivialClone; + use super::{Share, TrivialClone}; use crate::marker::PointeeSized; macro_rules! impl_clone { @@ -609,7 +710,7 @@ mod impls { $( #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] - impl const Clone for $t { + const impl Clone for $t { #[inline(always)] fn clone(&self) -> Self { *self @@ -619,7 +720,7 @@ mod impls { #[doc(hidden)] #[unstable(feature = "trivial_clone", issue = "none")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] - unsafe impl const TrivialClone for $t {} + const unsafe impl TrivialClone for $t {} )* } } @@ -633,7 +734,7 @@ mod impls { #[unstable(feature = "never_type", issue = "35121")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] - impl const Clone for ! { + const impl Clone for ! { #[inline] fn clone(&self) -> Self { *self @@ -643,11 +744,11 @@ mod impls { #[doc(hidden)] #[unstable(feature = "trivial_clone", issue = "none")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] - unsafe impl const TrivialClone for ! {} + const unsafe impl TrivialClone for ! {} #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] - impl const Clone for *const T { + const impl Clone for *const T { #[inline(always)] fn clone(&self) -> Self { *self @@ -657,11 +758,11 @@ mod impls { #[doc(hidden)] #[unstable(feature = "trivial_clone", issue = "none")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] - unsafe impl const TrivialClone for *const T {} + const unsafe impl TrivialClone for *const T {} #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] - impl const Clone for *mut T { + const impl Clone for *mut T { #[inline(always)] fn clone(&self) -> Self { *self @@ -671,12 +772,12 @@ mod impls { #[doc(hidden)] #[unstable(feature = "trivial_clone", issue = "none")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] - unsafe impl const TrivialClone for *mut T {} + const unsafe impl TrivialClone for *mut T {} /// Shared references can be cloned, but mutable references *cannot*! #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] - impl const Clone for &T { + const impl Clone for &T { #[inline(always)] #[rustc_diagnostic_item = "noop_method_clone"] fn clone(&self) -> Self { @@ -687,7 +788,10 @@ mod impls { #[doc(hidden)] #[unstable(feature = "trivial_clone", issue = "none")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] - unsafe impl const TrivialClone for &T {} + const unsafe impl TrivialClone for &T {} + + #[unstable(feature = "share_trait", issue = "156756")] + impl Share for &T {} /// Shared references can be cloned, but mutable references *cannot*! #[stable(feature = "rust1", since = "1.0.0")] diff --git a/library/core/src/cmp.rs b/library/core/src/cmp.rs index 78ea1f1113258..43128302dfef4 100644 --- a/library/core/src/cmp.rs +++ b/library/core/src/cmp.rs @@ -241,22 +241,33 @@ use crate::ops::ControlFlow; #[stable(feature = "rust1", since = "1.0.0")] #[doc(alias = "==")] #[doc(alias = "!=")] -#[rustc_on_unimplemented( +#[diagnostic::on_unimplemented( message = "can't compare `{Self}` with `{Rhs}`", - label = "no implementation for `{Self} == {Rhs}`", - append_const_msg + label = "no implementation for `{Self} == {Rhs}`" )] #[rustc_diagnostic_item = "PartialEq"] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] pub const trait PartialEq: PointeeSized { - /// Tests for `self` and `other` values to be equal, and is used by `==`. + /// Equality operator `==`. + /// + /// Implementation of the "is equal to" operator `==`: + /// tests whether its arguments are equal. #[must_use] #[stable(feature = "rust1", since = "1.0.0")] #[rustc_diagnostic_item = "cmp_partialeq_eq"] fn eq(&self, other: &Rhs) -> bool; - /// Tests for `!=`. The default implementation is almost always sufficient, - /// and should not be overridden without very good reason. + /// Inequality operator `!=`. + /// + /// Implementation of the "is not equal to" or "is different from" operator `!=`: + /// tests whether its arguments are different. + /// + /// # Default implementation + /// The default implementation of the inequality operator simply calls + /// the implementation of the equality operator and negates the result. + /// + /// This default shouldn't be overridden without good reason, + /// such as when forwarding to another PartialEq implementation. #[inline] #[must_use] #[stable(feature = "rust1", since = "1.0.0")] @@ -281,8 +292,9 @@ pub macro PartialEq($item:item) { /// The primary difference to [`PartialEq`] is the additional requirement for reflexivity. A type /// that implements [`PartialEq`] guarantees that for all `a`, `b` and `c`: /// -/// - symmetric: `a == b` implies `b == a` and `a != b` implies `!(a == b)` +/// - symmetric: `a == b` implies `b == a` /// - transitive: `a == b` and `b == c` implies `a == c` +/// - consistent: `a != b` if and only if `!(a == b)` /// /// `Eq`, which builds on top of [`PartialEq`] also implies: /// @@ -336,19 +348,28 @@ pub macro PartialEq($item:item) { #[rustc_diagnostic_item = "Eq"] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] pub const trait Eq: [const] PartialEq + PointeeSized { - // this method is used solely by `impl Eq or #[derive(Eq)]` to assert that every component of a - // type implements `Eq` itself. The current deriving infrastructure means doing this assertion - // without using a method on this trait is nearly impossible. + // This method was used solely by `#[derive(Eq)]` to assert that every component of a + // type implements `Eq` itself. // // This should never be implemented by hand. #[doc(hidden)] #[coverage(off)] #[inline] #[stable(feature = "rust1", since = "1.0.0")] + #[rustc_diagnostic_item = "assert_receiver_is_total_eq"] + #[deprecated(since = "1.95.0", note = "implementation detail of `#[derive(Eq)]`")] fn assert_receiver_is_total_eq(&self) {} + + // FIXME (#152504): this method is used solely by `#[derive(Eq)]` to assert that + // every component of a type implements `Eq` itself. It will be removed again soon. + #[doc(hidden)] + #[coverage(off)] + #[unstable(feature = "derive_eq_internals", issue = "none")] + fn assert_fields_are_eq(&self) {} } /// Derive macro generating an impl of the trait [`Eq`]. +/// The behavior of this macro is described in detail [here](Eq#derivable). #[rustc_builtin_macro] #[stable(feature = "builtin_macro_prelude", since = "1.38.0")] #[allow_internal_unstable(core_intrinsics, derive_eq_internals, structural_match)] @@ -676,7 +697,7 @@ pub struct Reverse(#[stable(feature = "reverse_cmp_key", since = "1.19.0")] p #[stable(feature = "reverse_cmp_key", since = "1.19.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialOrd for Reverse { +const impl PartialOrd for Reverse { #[inline] fn partial_cmp(&self, other: &Reverse) -> Option { other.0.partial_cmp(&self.0) @@ -702,7 +723,7 @@ impl const PartialOrd for Reverse { #[stable(feature = "reverse_cmp_key", since = "1.19.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const Ord for Reverse { +const impl Ord for Reverse { #[inline] fn cmp(&self, other: &Reverse) -> Ordering { other.0.cmp(&self.0) @@ -722,6 +743,54 @@ impl Clone for Reverse { } } +/// A pair where ordering and equality work on only the `key`, ignoring the `value`. +/// +/// Used to implement `Iterator::min_by_key` as `map`+`min`, for example. +#[derive(Debug, Copy, Clone)] +pub(crate) struct KeyAndValue { + pub key: K, + pub value: V, +} +impl PartialEq for KeyAndValue { + #[inline] + fn eq(&self, other: &Self) -> bool { + self.key == other.key + } + #[inline] + fn ne(&self, other: &Self) -> bool { + self.key != other.key + } +} +impl Eq for KeyAndValue {} +impl PartialOrd for KeyAndValue { + #[inline] + fn partial_cmp(&self, other: &Self) -> Option { + PartialOrd::partial_cmp(&self.key, &other.key) + } + #[inline] + fn lt(&self, other: &Self) -> bool { + self.key < other.key + } + #[inline] + fn le(&self, other: &Self) -> bool { + self.key <= other.key + } + #[inline] + fn gt(&self, other: &Self) -> bool { + self.key > other.key + } + #[inline] + fn ge(&self, other: &Self) -> bool { + self.key >= other.key + } +} +impl Ord for KeyAndValue { + #[inline] + fn cmp(&self, other: &Self) -> Ordering { + Ord::cmp(&self.key, &other.key) + } +} + /// Trait for types that form a [total order](https://en.wikipedia.org/wiki/Total_order). /// /// Implementations must be consistent with the [`PartialOrd`] implementation, and ensure `max`, @@ -1347,10 +1416,9 @@ pub macro Ord($item:item) { #[doc(alias = "<")] #[doc(alias = "<=")] #[doc(alias = ">=")] -#[rustc_on_unimplemented( +#[diagnostic::on_unimplemented( message = "can't compare `{Self}` with `{Rhs}`", - label = "no implementation for `{Self} < {Rhs}` and `{Self} > {Rhs}`", - append_const_msg + label = "no implementation for `{Self} < {Rhs}` and `{Self} > {Rhs}`" )] #[rustc_diagnostic_item = "PartialOrd"] #[allow(multiple_supertrait_upcastable)] // FIXME(sized_hierarchy): remove this @@ -1853,6 +1921,214 @@ where if f(&v2) < f(&v1) { [v2, v1] } else { [v1, v2] } } +/// Calls `mac` on lists of arguments from size `0` to `1 + count($y)`. +macro impl_for_tuples_up_to($mac:ident! { $($x:ident, $($y:ident,)*)? }) { + $(impl_for_tuples_up_to! { + $mac! { $($y,)* } + })? + $mac! { $($x, $($y,)*)? } +} + +/// Calls each `mac` on lists of arguments from size zero to twelve. +macro impl_tuples($($mac:ident,)+) { + $(impl_for_tuples_up_to! { $mac! { x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, } })+ +} + +/// Implementation detail for [`smallest`] and [`largest`]. +/// Marker indicating that `Self` is a tuple where all members are of the same type. +#[diagnostic::on_unimplemented(message = "`{Self}` is not a homogeneous tuple")] +#[unstable(feature = "cmp_splat_internals", issue = "160728")] +#[rustc_const_unstable(feature = "cmp_splat_internals", issue = "160728")] +const trait HomogeneousTuple: crate::marker::Tuple { + /// The type of each item in this tuple. + type Item; +} + +/// Implements [`HomogeneousTuple`] for a provided tuple. +macro impl_homogeneous_tuple($($($x:ident,)+)?) { + $( + #[unstable(feature = "cmp_splat_internals", issue = "160728")] + #[rustc_const_unstable(feature = "cmp_splat_internals", issue = "160728")] + const impl HomogeneousTuple for ($(${ignore($x)}T,)+) { + type Item = T; + } + )? +} + +impl_tuples! { + impl_homogeneous_tuple, +} + +/// Compares and returns the minimum of the provided values. +/// +/// Returns the first argument if the comparison determines them to be equal. +/// +/// Internally uses [`Ord::min`]. +/// +/// # Examples +/// +/// ``` +/// #![feature(cmp_splat)] +/// use std::cmp; +/// +/// assert_eq!(cmp::smallest(1), 1); +/// assert_eq!(cmp::smallest(1, 2), 1); +/// assert_eq!(cmp::smallest(3, 2, 1), 1); +/// assert_eq!(cmp::smallest(1, 2, 3, 4), 1); +/// ``` +/// ``` +/// #![feature(cmp_splat)] +/// use std::cmp::{self, Ordering}; +/// +/// #[derive(Eq)] +/// struct Equal(&'static str); +/// +/// impl PartialEq for Equal { +/// fn eq(&self, other: &Self) -> bool { true } +/// } +/// impl PartialOrd for Equal { +/// fn partial_cmp(&self, other: &Self) -> Option { Some(Ordering::Equal) } +/// } +/// impl Ord for Equal { +/// fn cmp(&self, other: &Self) -> Ordering { Ordering::Equal } +/// } +/// +/// assert_eq!(cmp::smallest(Equal("v1"), Equal("v2")).0, "v1"); +/// ``` +/// +/// # Stability +/// +/// This function is added in its current form as an experiment in variadic functions. +/// In a future iteration of the feature, this function may be removed in favour of +/// making [`min`] itself variadic instead. +#[inline] +#[must_use] +#[unstable(feature = "cmp_splat", issue = "160728")] +#[rustc_const_unstable(feature = "cmp_splat", issue = "160728")] +#[expect(private_bounds, reason = "`SmallestArgs` is an internal implementation detail")] +#[cfg(not(test))] // FIXME: splat interacts poorly with the double linking of `core` in tests +pub const fn smallest( + #[rustc_splat] args: impl [const] SmallestArgs, +) -> T { + SmallestArgs::smallest(args) +} + +/// Implementation detail for [`smallest`]. +#[diagnostic::on_unimplemented(message = "`{Self}` is not a valid set of arguments for `smallest`")] +#[unstable(feature = "cmp_splat_internals", issue = "160728")] +#[rustc_const_unstable(feature = "cmp_splat_internals", issue = "160728")] +const trait SmallestArgs: HomogeneousTuple { + /// Reduces all elements of a homogeneous tuple to its smallest value. + fn smallest(self) -> Self::Item; +} + +/// Implements [`SmallestArgs`] for a provided tuple if applicable. +macro impl_smallest_args($($x:ident, $($($y:ident,)+)?)?) { + $( + #[unstable(feature = "cmp_splat_internals", issue = "160728")] + #[rustc_const_unstable(feature = "cmp_splat_internals", issue = "160728")] + const impl SmallestArgs for (T, $($(${ignore($y)}T,)+)?) + $(where T: [const] Destruct + [const] Ord, $(${ignore($y)})+)? + { + #[inline] + fn smallest(self) -> Self::Item { + let ($x, $($($y,)+)?) = self; + $($(let $x = $x.min($y);)+)? + $x + } + } + )? +} + +impl_tuples! { + impl_smallest_args, +} + +/// Compares and returns the maximum of the provided values. +/// +/// Returns the last argument if the comparison determines them to be equal. +/// +/// Internally uses [`Ord::max`]. +/// +/// # Examples +/// +/// ``` +/// #![feature(cmp_splat)] +/// use std::cmp; +/// +/// assert_eq!(cmp::largest(1), 1); +/// assert_eq!(cmp::largest(1, 2), 2); +/// assert_eq!(cmp::largest(3, 2, 1), 3); +/// assert_eq!(cmp::largest(1, 2, 3, 4), 4); +/// ``` +/// ``` +/// #![feature(cmp_splat)] +/// use std::cmp::{self, Ordering}; +/// +/// #[derive(Eq)] +/// struct Equal(&'static str); +/// +/// impl PartialEq for Equal { +/// fn eq(&self, other: &Self) -> bool { true } +/// } +/// impl PartialOrd for Equal { +/// fn partial_cmp(&self, other: &Self) -> Option { Some(Ordering::Equal) } +/// } +/// impl Ord for Equal { +/// fn cmp(&self, other: &Self) -> Ordering { Ordering::Equal } +/// } +/// +/// assert_eq!(cmp::largest(Equal("v1"), Equal("v2")).0, "v2"); +/// ``` +/// +/// # Stability +/// +/// This function is added in its current form as an experiment in variadic functions. +/// In a future iteration of the feature, this function may be removed in favour of +/// making [`max`] itself variadic instead. +#[inline] +#[must_use] +#[unstable(feature = "cmp_splat", issue = "160728")] +#[rustc_const_unstable(feature = "cmp_splat", issue = "160728")] +#[expect(private_bounds, reason = "`LargestArgs` is an internal implementation detail")] +#[cfg(not(test))] // FIXME: splat interacts poorly with the double linking of `core` in tests +pub const fn largest( + #[rustc_splat] args: impl [const] LargestArgs, +) -> T { + LargestArgs::largest(args) +} + +/// Implementation detail for [`largest`]. +#[diagnostic::on_unimplemented(message = "`{Self}` is not a valid set of arguments for `largest`")] +#[unstable(feature = "cmp_splat_internals", issue = "160728")] +#[rustc_const_unstable(feature = "cmp_splat_internals", issue = "160728")] +const trait LargestArgs: HomogeneousTuple { + /// Reduces all elements of a homogeneous tuple to its largest value. + fn largest(self) -> Self::Item; +} + +/// Implements [`LargestArgs`] for a provided tuple if applicable. +macro impl_largest_args($($x:ident, $($($y:ident,)+)?)?) { + $( + #[unstable(feature = "cmp_splat_internals", issue = "160728")] + #[rustc_const_unstable(feature = "cmp_splat_internals", issue = "160728")] + const impl LargestArgs for (T, $($(${ignore($y)}T,)+)?) + $(where T: [const] Destruct + [const] Ord, $(${ignore($y)})+)? + { + #[inline] + fn largest(self) -> Self::Item { + let ($x, $($($y,)+)?) = self; + $($(let $x = $x.max($y);)+)? + $x + } + } + )? +} + +impl_tuples! { + impl_largest_args, +} + // Implementation of PartialEq, Eq, PartialOrd and Ord for primitive types mod impls { use crate::cmp::Ordering::{self, Equal, Greater, Less}; @@ -1861,22 +2137,34 @@ mod impls { use crate::ops::ControlFlow::{self, Break, Continue}; use crate::panic::const_assert; - macro_rules! partial_eq_impl { + /// Implements `PartialEq` for primitive types. + /// + /// Primitive types have a compiler-defined primitive implementation of `==` and `!=`. + /// This implements the `PartialEq` trait in terms of those primitive implementations. + /// + /// NOTE: Calling this on a non-primitive type (such as `()`) + /// leads to an infinitely-looping self-recursive implementation. + macro_rules! impl_partial_eq_for_primitive { ($($t:ty)*) => ($( #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialEq for $t { + const impl PartialEq for $t { #[inline] fn eq(&self, other: &Self) -> bool { *self == *other } + // Override the default to use the primitive implementation for `!=`. #[inline] fn ne(&self, other: &Self) -> bool { *self != *other } } )*) } + impl_partial_eq_for_primitive! { + bool char usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 f16 f32 f64 f128 + } + #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialEq for () { + const impl PartialEq for () { #[inline] fn eq(&self, _other: &()) -> bool { true @@ -1887,15 +2175,11 @@ mod impls { } } - partial_eq_impl! { - bool char usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 f16 f32 f64 f128 - } - macro_rules! eq_impl { ($($t:ty)*) => ($( #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const Eq for $t {} + const impl Eq for $t {} )*) } @@ -1944,7 +2228,7 @@ mod impls { ($($t:ty)*) => ($( #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialOrd for $t { + const impl PartialOrd for $t { #[inline] fn partial_cmp(&self, other: &Self) -> Option { match (*self <= *other, *self >= *other) { @@ -1962,7 +2246,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialOrd for () { + const impl PartialOrd for () { #[inline] fn partial_cmp(&self, _: &()) -> Option { Some(Equal) @@ -1971,7 +2255,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialOrd for bool { + const impl PartialOrd for bool { #[inline] fn partial_cmp(&self, other: &bool) -> Option { Some(self.cmp(other)) @@ -1986,7 +2270,7 @@ mod impls { ($($t:ty)*) => ($( #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialOrd for $t { + const impl PartialOrd for $t { #[inline] fn partial_cmp(&self, other: &Self) -> Option { Some(crate::intrinsics::three_way_compare(*self, *other)) @@ -1997,7 +2281,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const Ord for $t { + const impl Ord for $t { #[inline] fn cmp(&self, other: &Self) -> Ordering { crate::intrinsics::three_way_compare(*self, *other) @@ -2028,7 +2312,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const Ord for () { + const impl Ord for () { #[inline] fn cmp(&self, _other: &()) -> Ordering { Equal @@ -2037,7 +2321,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const Ord for bool { + const impl Ord for bool { #[inline] fn cmp(&self, other: &bool) -> Ordering { // Casting to i8's and converting the difference to an Ordering generates @@ -2073,7 +2357,7 @@ mod impls { #[unstable(feature = "never_type", issue = "35121")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialEq for ! { + const impl PartialEq for ! { #[inline] fn eq(&self, _: &!) -> bool { *self @@ -2082,11 +2366,11 @@ mod impls { #[unstable(feature = "never_type", issue = "35121")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const Eq for ! {} + const impl Eq for ! {} #[unstable(feature = "never_type", issue = "35121")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialOrd for ! { + const impl PartialOrd for ! { #[inline] fn partial_cmp(&self, _: &!) -> Option { *self @@ -2095,7 +2379,7 @@ mod impls { #[unstable(feature = "never_type", issue = "35121")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const Ord for ! { + const impl Ord for ! { #[inline] fn cmp(&self, _: &!) -> Ordering { *self @@ -2106,7 +2390,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialEq<&B> for &A + const impl PartialEq<&B> for &A where A: [const] PartialEq, { @@ -2121,7 +2405,7 @@ mod impls { } #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialOrd<&B> for &A + const impl PartialOrd<&B> for &A where A: [const] PartialOrd, { @@ -2164,7 +2448,7 @@ mod impls { } #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const Ord for &A + const impl Ord for &A where A: [const] Ord, { @@ -2175,13 +2459,13 @@ mod impls { } #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const Eq for &A where A: [const] Eq {} + const impl Eq for &A where A: [const] Eq {} // &mut pointers #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialEq<&mut B> for &mut A + const impl PartialEq<&mut B> for &mut A where A: [const] PartialEq, { @@ -2196,7 +2480,7 @@ mod impls { } #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialOrd<&mut B> for &mut A + const impl PartialOrd<&mut B> for &mut A where A: [const] PartialOrd, { @@ -2239,7 +2523,7 @@ mod impls { } #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const Ord for &mut A + const impl Ord for &mut A where A: [const] Ord, { @@ -2250,11 +2534,11 @@ mod impls { } #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const Eq for &mut A where A: [const] Eq {} + const impl Eq for &mut A where A: [const] Eq {} #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialEq<&mut B> for &A + const impl PartialEq<&mut B> for &A where A: [const] PartialEq, { @@ -2270,7 +2554,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialEq<&B> for &mut A + const impl PartialEq<&B> for &mut A where A: [const] PartialEq, { diff --git a/library/core/src/cmp/bytewise.rs b/library/core/src/cmp/bytewise.rs index f0f5f656405a9..07e24441cf51d 100644 --- a/library/core/src/cmp/bytewise.rs +++ b/library/core/src/cmp/bytewise.rs @@ -24,7 +24,7 @@ pub(crate) const unsafe trait BytewiseEq: macro_rules! is_bytewise_comparable { ($($t:ty),+ $(,)?) => {$( - unsafe impl const BytewiseEq for $t {} + const unsafe impl BytewiseEq for $t {} )+}; } @@ -33,7 +33,7 @@ is_bytewise_comparable!(u8, u16, u32, u64, u128, usize, i8, i16, i32, i64, i128, // SAFETY: These have *niches*, but no *padding* and no *provenance*, // so we can compare them directly. -is_bytewise_comparable!(bool, char, super::Ordering); +is_bytewise_comparable!(bool, char, super::Ordering, crate::ascii::Char); // SAFETY: Similarly, the `NonZero` type has a niche, but no undef and no pointers, // and they compare like their underlying numeric type. diff --git a/library/core/src/convert/mod.rs b/library/core/src/convert/mod.rs index ef4ab15f93c0b..912623b73050e 100644 --- a/library/core/src/convert/mod.rs +++ b/library/core/src/convert/mod.rs @@ -5,22 +5,21 @@ //! //! - Implement the [`AsRef`] trait for cheap reference-to-reference conversions //! - Implement the [`AsMut`] trait for cheap mutable-to-mutable conversions -//! - Implement the [`From`] trait for consuming value-to-value conversions -//! - Implement the [`Into`] trait for consuming value-to-value conversions to types -//! outside the current crate -//! - The [`TryFrom`] and [`TryInto`] traits behave like [`From`] and [`Into`], -//! but should be implemented when the conversion can fail. +//! - Implement the [`From`] trait for consuming value-to-value conversions that cannot fail. This +//! automatically provides an implementation of [`Into`] +//! - Implement the [`TryFrom`] trait for consuming value-to-value conversions that can fail. This +//! automatically provides an implementation of [`TryInto`] //! -//! The traits in this module are often used as trait bounds for generic functions such that to +//! The traits in this module are often used as trait bounds for generic functions such that //! arguments of multiple types are supported. See the documentation of each trait for examples. //! //! As a library author, you should always prefer implementing [`From`][`From`] or //! [`TryFrom`][`TryFrom`] rather than [`Into`][`Into`] or [`TryInto`][`TryInto`], //! as [`From`] and [`TryFrom`] provide greater flexibility and offer //! equivalent [`Into`] or [`TryInto`] implementations for free, thanks to a -//! blanket implementation in the standard library. When targeting a version prior to Rust 1.41, it -//! may be necessary to implement [`Into`] or [`TryInto`] directly when converting to a type -//! outside the current crate. +//! blanket implementation in the standard library. In versions of Rust prior to Rust 1.41, +//! it was sometimes necessary to implement [`Into`] or [`TryInto`] directly when converting to a +//! type outside the current crate. //! //! # Generic Implementations //! @@ -44,6 +43,8 @@ mod num; #[unstable(feature = "convert_float_to_int", issue = "67057")] pub use num::FloatToInt; +#[unstable(feature = "integer_casts", issue = "157388")] +pub use num::{BoundedCastFromInt, CheckedCastFromInt}; /// The identity function. /// @@ -577,6 +578,7 @@ pub const trait Into: Sized { /// [`from`]: From::from /// [book]: ../../book/ch09-00-error-handling.html #[rustc_diagnostic_item = "From"] +#[lang = "From"] #[stable(feature = "rust1", since = "1.0.0")] #[rustc_on_unimplemented(on( all(Self = "&str", T = "alloc::string::String"), @@ -589,6 +591,7 @@ pub const trait From: Sized { #[rustc_diagnostic_item = "from_fn"] #[must_use] #[stable(feature = "rust1", since = "1.0.0")] + #[lang = "from"] fn from(value: T) -> Self; } @@ -709,7 +712,7 @@ pub const trait TryFrom: Sized { // As lifts over & #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef for &T +const impl AsRef for &T where T: [const] AsRef, { @@ -722,7 +725,7 @@ where // As lifts over &mut #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef for &mut T +const impl AsRef for &mut T where T: [const] AsRef, { @@ -743,7 +746,7 @@ where // AsMut lifts over &mut #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsMut for &mut T +const impl AsMut for &mut T where T: [const] AsMut, { @@ -764,7 +767,7 @@ where // From implies Into #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Into for T +const impl Into for T where U: [const] From, { @@ -782,7 +785,7 @@ where // From (and thus Into) is reflexive #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for T { +const impl From for T { /// Returns the argument unchanged. #[inline(always)] fn from(t: T) -> T { @@ -799,7 +802,7 @@ impl const From for T { #[rustc_reservation_impl = "permitting this impl would forbid us from adding \ `impl From for T` later; see rust-lang/rust#64715 for details"] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for T { +const impl From for T { fn from(t: !) -> T { t } @@ -808,7 +811,7 @@ impl const From for T { // TryFrom implies TryInto #[stable(feature = "try_from", since = "1.34.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const TryInto for T +const impl TryInto for T where U: [const] TryFrom, { @@ -824,7 +827,7 @@ where // with an uninhabited error type. #[stable(feature = "try_from", since = "1.34.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const TryFrom for T +const impl TryFrom for T where U: [const] Into, { @@ -842,7 +845,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef<[T]> for [T] { +const impl AsRef<[T]> for [T] { #[inline(always)] fn as_ref(&self) -> &[T] { self @@ -851,7 +854,7 @@ impl const AsRef<[T]> for [T] { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsMut<[T]> for [T] { +const impl AsMut<[T]> for [T] { #[inline(always)] fn as_mut(&mut self) -> &mut [T] { self @@ -860,7 +863,7 @@ impl const AsMut<[T]> for [T] { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef for str { +const impl AsRef for str { #[inline(always)] fn as_ref(&self) -> &str { self @@ -869,7 +872,7 @@ impl const AsRef for str { #[stable(feature = "as_mut_str_for_str", since = "1.51.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsMut for str { +const impl AsMut for str { #[inline(always)] fn as_mut(&mut self) -> &mut str { self @@ -931,7 +934,7 @@ pub enum Infallible {} #[stable(feature = "convert_infallible", since = "1.34.0")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] -impl const Clone for Infallible { +const impl Clone for Infallible { fn clone(&self) -> Infallible { match *self {} } @@ -956,7 +959,7 @@ impl Error for Infallible {} #[stable(feature = "convert_infallible", since = "1.34.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq for Infallible { +const impl PartialEq for Infallible { fn eq(&self, _: &Infallible) -> bool { match *self {} } @@ -964,11 +967,11 @@ impl const PartialEq for Infallible { #[stable(feature = "convert_infallible", since = "1.34.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const Eq for Infallible {} +const impl Eq for Infallible {} #[stable(feature = "convert_infallible", since = "1.34.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialOrd for Infallible { +const impl PartialOrd for Infallible { fn partial_cmp(&self, _other: &Self) -> Option { match *self {} } @@ -976,7 +979,7 @@ impl const PartialOrd for Infallible { #[stable(feature = "convert_infallible", since = "1.34.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const Ord for Infallible { +const impl Ord for Infallible { fn cmp(&self, _other: &Self) -> crate::cmp::Ordering { match *self {} } @@ -984,7 +987,7 @@ impl const Ord for Infallible { #[stable(feature = "convert_infallible", since = "1.34.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for Infallible { +const impl From for Infallible { #[inline] fn from(x: !) -> Self { x diff --git a/library/core/src/convert/num.rs b/library/core/src/convert/num.rs index 3625234b301dc..f5eea9a49b2cd 100644 --- a/library/core/src/convert/num.rs +++ b/library/core/src/convert/num.rs @@ -2,22 +2,14 @@ use safety::requires; #[cfg(kani)] use crate::kani; -use crate::num::TryFromIntError; +use crate::num::{IntErrorKind, TryFromIntError}; #[allow(unused_imports)] use crate::ub_checks::float_to_int_in_range; -mod private { - /// This trait being unreachable from outside the crate - /// prevents other implementations of the `FloatToInt` trait, - /// which allows potentially adding more trait methods after the trait is `#[stable]`. - #[unstable(feature = "convert_float_to_int", issue = "67057")] - pub trait Sealed {} -} - /// Supporting trait for inherent methods of `f32` and `f64` such as `to_int_unchecked`. /// Typically doesn’t need to be used directly. #[unstable(feature = "convert_float_to_int", issue = "67057")] -pub trait FloatToInt: private::Sealed + Sized { +pub impl(self) trait FloatToInt: Sized { #[unstable(feature = "convert_float_to_int", issue = "67057")] #[doc(hidden)] unsafe fn to_int_unchecked(self) -> Int; @@ -25,8 +17,6 @@ pub trait FloatToInt: private::Sealed + Sized { macro_rules! impl_float_to_int { ($Float:ty => $($Int:ty),+) => { - #[unstable(feature = "convert_float_to_int", issue = "67057")] - impl private::Sealed for $Float {} $( #[unstable(feature = "convert_float_to_int", issue = "67057")] impl FloatToInt<$Int> for $Float { @@ -53,7 +43,7 @@ macro_rules! impl_from_bool { ($($int:ty)*) => {$( #[stable(feature = "from_bool", since = "1.28.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] - impl const From for $int { + const impl From for $int { /// Converts from [`bool`] to #[doc = concat!("[`", stringify!($int), "`]")] /// , by turning `false` into `0` and `true` into `1`. @@ -80,10 +70,10 @@ impl_from_bool!(i8 i16 i32 i64 i128 isize); /// Implement `From<$small>` for `$large` macro_rules! impl_from { - ($small:ty => $large:ty, #[$attr:meta]) => { - #[$attr] + ($small:ty => $large:ty, $(#[$attrs:meta]),+) => { + $(#[$attrs])+ #[rustc_const_unstable(feature = "const_convert", issue = "143773")] - impl const From<$small> for $large { + const impl From<$small> for $large { #[doc = concat!("Converts from [`", stringify!($small), "`] to [`", stringify!($large), "`] losslessly.")] #[cfg_attr(flux, flux::spec(fn(small: $small) -> $large[cast(small)]))] #[inline(always)] @@ -159,61 +149,67 @@ impl_from!(i16 => isize, #[stable(feature = "lossless_iusize_conv", since = "1.2 // of the `f16`/`f128` impls can be used on stable as the `f16` and `f128` types are unstable). // signed integer -> float -impl_from!(i8 => f16, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); +impl_from!(i8 => f16, #[unstable(feature = "f16", issue = "116909")], #[unstable_feature_bound(f16)]); impl_from!(i8 => f32, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); impl_from!(i8 => f64, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); -impl_from!(i8 => f128, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); +impl_from!(i8 => f128, #[unstable(feature = "f128", issue = "116909")], #[unstable_feature_bound(f128)]); impl_from!(i16 => f32, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); impl_from!(i16 => f64, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); -impl_from!(i16 => f128, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); +impl_from!(i16 => f128, #[unstable(feature = "f128", issue = "116909")], #[unstable_feature_bound(f128)]); impl_from!(i32 => f64, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); -impl_from!(i32 => f128, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); -// FIXME(f128): This impl would allow using `f128` on stable before it is stabilised. -// impl_from!(i64 => f128, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); +impl_from!(i32 => f128, #[unstable(feature = "f128", issue = "116909")], #[unstable_feature_bound(f128)]); +impl_from!(i64 => f128, #[unstable(feature = "f128", issue = "116909")], #[unstable_feature_bound(f128)]); // unsigned integer -> float -impl_from!(u8 => f16, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); +impl_from!(u8 => f16, #[unstable(feature = "f16", issue = "116909")], #[unstable_feature_bound(f16)]); impl_from!(u8 => f32, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); impl_from!(u8 => f64, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); -impl_from!(u8 => f128, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); +impl_from!(u8 => f128, #[unstable(feature = "f128", issue = "116909")], #[unstable_feature_bound(f128)]); impl_from!(u16 => f32, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); impl_from!(u16 => f64, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); -impl_from!(u16 => f128, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); +impl_from!(u16 => f128, #[unstable(feature = "f128", issue = "116909")], #[unstable_feature_bound(f128)]); impl_from!(u32 => f64, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); -impl_from!(u32 => f128, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); -// FIXME(f128): This impl would allow using `f128` on stable before it is stabilised. -// impl_from!(u64 => f128, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); +impl_from!(u32 => f128, #[unstable(feature = "f128", issue = "116909")], #[unstable_feature_bound(f128)]); +impl_from!(u64 => f128, #[unstable(feature = "f128", issue = "116909")], #[unstable_feature_bound(f128)]); // float -> float -// FIXME(f16,f128): adding additional `From<{float}>` impls to `f32` breaks inference. See -// -impl_from!(f16 => f64, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); -impl_from!(f16 => f128, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); + +// FIXME(f16): adding the additional `From<{float}>` impl to `f32` would break inference in cases +// like `f32::from(1.0)`. The type checker has a custom workaround to keep that and similar code +// compiling even with the second `From<16> for f32` instance. We keep this instance unstable for +// now so that we can later remove the workaround. +// +// See also . +impl_from!(f16 => f32, #[unstable(feature = "f32_from_f16", issue = "154005")], #[unstable_feature_bound(f32_from_f16)]); +impl_from!(f16 => f64, #[unstable(feature = "f16", issue = "116909")], #[unstable_feature_bound(f16)]); +// Also #[unstable(feature = "f16", issue = "116909")]: +impl_from!(f16 => f128, #[unstable(feature = "f128", issue = "116909")], #[unstable_feature_bound(f16, f128)]); impl_from!(f32 => f64, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); -impl_from!(f32 => f128, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); -impl_from!(f64 => f128, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); +impl_from!(f32 => f128, #[unstable(feature = "f128", issue = "116909")], #[unstable_feature_bound(f128)]); +impl_from!(f64 => f128, #[unstable(feature = "f128", issue = "116909")], #[unstable_feature_bound(f128)]); macro_rules! impl_float_from_bool { ( + $(#[$attr:meta])* $float:ty $(; doctest_prefix: $(#[doc = $doctest_prefix:literal])* doctest_suffix: $(#[doc = $doctest_suffix:literal])* )? ) => { - #[stable(feature = "float_from_bool", since = "1.68.0")] + $(#[$attr])* #[rustc_const_unstable(feature = "const_convert", issue = "143773")] - impl const From for $float { + const impl From for $float { #[doc = concat!("Converts a [`bool`] to [`", stringify!($float),"`] losslessly.")] /// The resulting value is positive `0.0` for `false` and `1.0` for `true` values. /// /// # Examples /// ``` $($(#[doc = $doctest_prefix])*)? - #[doc = concat!("let x: ", stringify!($float)," = false.into();")] + #[doc = concat!("let x = ", stringify!($float), "::from(false);")] /// assert_eq!(x, 0.0); /// assert!(x.is_sign_positive()); /// - #[doc = concat!("let y: ", stringify!($float)," = true.into();")] + #[doc = concat!("let y = ", stringify!($float), "::from(true);")] /// assert_eq!(y, 1.0); $($(#[doc = $doctest_suffix])*)? /// ``` @@ -227,20 +223,32 @@ macro_rules! impl_float_from_bool { // boolean -> float impl_float_from_bool!( + #[unstable(feature = "f16", issue = "116909")] + #[unstable_feature_bound(f16)] f16; doctest_prefix: // rustdoc doesn't remove the conventional space after the `///` + ///# #![allow(unused_features)] ///#![feature(f16)] ///# #[cfg(all(target_arch = "x86_64", target_os = "linux"))] { /// doctest_suffix: ///# } ); -impl_float_from_bool!(f32); -impl_float_from_bool!(f64); impl_float_from_bool!( + #[stable(feature = "float_from_bool", since = "1.68.0")] + f32 +); +impl_float_from_bool!( + #[stable(feature = "float_from_bool", since = "1.68.0")] + f64 +); +impl_float_from_bool!( + #[unstable(feature = "f128", issue = "116909")] + #[unstable_feature_bound(f128)] f128; doctest_prefix: + ///# #![allow(unused_features)] ///#![feature(f128)] ///# #[cfg(all(target_arch = "x86_64", target_os = "linux"))] { /// @@ -253,7 +261,7 @@ macro_rules! impl_try_from_unbounded { ($source:ty => $($target:ty),+) => {$( #[stable(feature = "try_from", since = "1.34.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] - impl const TryFrom<$source> for $target { + const impl TryFrom<$source> for $target { type Error = TryFromIntError; /// Tries to create the target number type from a source @@ -272,7 +280,7 @@ macro_rules! impl_try_from_lower_bounded { ($source:ty => $($target:ty),+) => {$( #[stable(feature = "try_from", since = "1.34.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] - impl const TryFrom<$source> for $target { + const impl TryFrom<$source> for $target { type Error = TryFromIntError; /// Tries to create the target number type from a source @@ -283,7 +291,7 @@ macro_rules! impl_try_from_lower_bounded { if u >= 0 { Ok(u as Self) } else { - Err(TryFromIntError(())) + Err(TryFromIntError(IntErrorKind::NegOverflow)) } } } @@ -295,7 +303,7 @@ macro_rules! impl_try_from_upper_bounded { ($source:ty => $($target:ty),+) => {$( #[stable(feature = "try_from", since = "1.34.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] - impl const TryFrom<$source> for $target { + const impl TryFrom<$source> for $target { type Error = TryFromIntError; /// Tries to create the target number type from a source @@ -304,7 +312,7 @@ macro_rules! impl_try_from_upper_bounded { #[inline] fn try_from(u: $source) -> Result { if u > (Self::MAX as $source) { - Err(TryFromIntError(())) + Err(TryFromIntError(IntErrorKind::PosOverflow)) } else { Ok(u as Self) } @@ -318,7 +326,7 @@ macro_rules! impl_try_from_both_bounded { ($source:ty => $($target:ty),+) => {$( #[stable(feature = "try_from", since = "1.34.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] - impl const TryFrom<$source> for $target { + const impl TryFrom<$source> for $target { type Error = TryFromIntError; /// Tries to create the target number type from a source @@ -328,8 +336,10 @@ macro_rules! impl_try_from_both_bounded { fn try_from(u: $source) -> Result { let min = Self::MIN as $source; let max = Self::MAX as $source; - if u < min || u > max { - Err(TryFromIntError(())) + if u < min { + Err(TryFromIntError(IntErrorKind::NegOverflow)) + } else if u > max { + Err(TryFromIntError(IntErrorKind::PosOverflow)) } else { Ok(u as Self) } @@ -340,10 +350,10 @@ macro_rules! impl_try_from_both_bounded { /// Implement `TryFrom` for `bool` macro_rules! impl_try_from_integer_for_bool { - ($($int:ty)+) => {$( - #[stable(feature = "try_from", since = "1.34.0")] + ($signedness:ident $($int:ty)+) => {$( + #[stable(feature = "bool_try_from_int", since = "1.95.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] - impl const TryFrom<$int> for bool { + const impl TryFrom<$int> for bool { type Error = TryFromIntError; /// Tries to create a bool from an integer type. @@ -352,18 +362,31 @@ macro_rules! impl_try_from_integer_for_bool { /// # Examples /// /// ``` - #[doc = concat!("assert_eq!(0_", stringify!($int), ".try_into(), Ok(false));")] + #[doc = concat!("assert_eq!(bool::try_from(0_", stringify!($int), "), Ok(false));")] /// - #[doc = concat!("assert_eq!(1_", stringify!($int), ".try_into(), Ok(true));")] + #[doc = concat!("assert_eq!(bool::try_from(1_", stringify!($int), "), Ok(true));")] /// - #[doc = concat!("assert!(<", stringify!($int), " as TryInto>::try_into(2).is_err());")] + #[doc = concat!("assert!(bool::try_from(2_", stringify!($int), ").is_err());")] /// ``` #[inline] fn try_from(i: $int) -> Result { - match i { - 0 => Ok(false), - 1 => Ok(true), - _ => Err(TryFromIntError(())), + sign_dependent_expr!{ + $signedness ? + if signed { + match i { + 0 => Ok(false), + 1 => Ok(true), + ..0 => Err(TryFromIntError(IntErrorKind::NegOverflow)), + 2.. => Err(TryFromIntError(IntErrorKind::PosOverflow)), + } + } + if unsigned { + match i { + 0 => Ok(false), + 1 => Ok(true), + 2.. => Err(TryFromIntError(IntErrorKind::PosOverflow)), + } + } } } } @@ -377,8 +400,8 @@ macro_rules! rev { } // integer -> bool -impl_try_from_integer_for_bool!(u128 u64 u32 u16 u8); -impl_try_from_integer_for_bool!(i128 i64 i32 i16 i8); +impl_try_from_integer_for_bool!(unsigned u128 u64 u32 u16 u8); +impl_try_from_integer_for_bool!(signed i128 i64 i32 i16 i8); // unsigned integer -> unsigned integer impl_try_from_upper_bounded!(u16 => u8); @@ -416,7 +439,7 @@ impl_try_from_lower_bounded!(isize => usize); #[cfg(target_pointer_width = "16")] mod ptr_try_from_impls { - use super::TryFromIntError; + use super::{IntErrorKind, TryFromIntError}; impl_try_from_upper_bounded!(usize => u8); impl_try_from_unbounded!(usize => u16, u32, u64, u128); @@ -438,7 +461,7 @@ mod ptr_try_from_impls { #[cfg(target_pointer_width = "32")] mod ptr_try_from_impls { - use super::TryFromIntError; + use super::{IntErrorKind, TryFromIntError}; impl_try_from_upper_bounded!(usize => u8, u16); impl_try_from_unbounded!(usize => u32, u64, u128); @@ -463,7 +486,7 @@ mod ptr_try_from_impls { #[cfg(target_pointer_width = "64")] mod ptr_try_from_impls { - use super::TryFromIntError; + use super::{IntErrorKind, TryFromIntError}; impl_try_from_upper_bounded!(usize => u8, u16, u32); impl_try_from_unbounded!(usize => u64, u128); @@ -493,7 +516,7 @@ macro_rules! impl_nonzero_int_from_nonzero_int { ($Small:ty => $Large:ty) => { #[stable(feature = "nz_int_conv", since = "1.41.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] - impl const From> for NonZero<$Large> { + const impl From> for NonZero<$Large> { // Rustdocs on the impl block show a "[+] show undocumented items" toggle. // Rustdocs on functions do not. #[doc = concat!("Converts [NonZero]\\<[", stringify!($Small), "]> ")] @@ -552,7 +575,7 @@ macro_rules! impl_nonzero_int_try_from_int { ($Int:ty) => { #[stable(feature = "nzint_try_from_int_conv", since = "1.46.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] - impl const TryFrom<$Int> for NonZero<$Int> { + const impl TryFrom<$Int> for NonZero<$Int> { type Error = TryFromIntError; // Rustdocs on the impl block show a "[+] show undocumented items" toggle. @@ -561,7 +584,7 @@ macro_rules! impl_nonzero_int_try_from_int { #[doc = concat!("to [NonZero]\\<[", stringify!($Int), "]>.")] #[inline] fn try_from(value: $Int) -> Result { - Self::new(value).ok_or(TryFromIntError(())) + Self::new(value).ok_or(TryFromIntError(IntErrorKind::Zero)) } } }; @@ -585,7 +608,7 @@ macro_rules! impl_nonzero_int_try_from_nonzero_int { ($source:ty => $($target:ty),+) => {$( #[stable(feature = "nzint_try_from_nzint_conv", since = "1.49.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] - impl const TryFrom> for NonZero<$target> { + const impl TryFrom> for NonZero<$target> { type Error = TryFromIntError; // Rustdocs on the impl block show a "[+] show undocumented items" toggle. @@ -890,3 +913,98 @@ mod verify { (f128 => u8, u16, u32, u64, u128, usize, i8, i16, i32, i64, i128, isize), ); } + +/// Conversion between integers, wrapping around or saturating at the target type's boundaries. +#[unstable(feature = "integer_casts", issue = "157388")] +#[rustc_const_unstable(feature = "integer_casts", issue = "157388")] +pub impl(self) const trait BoundedCastFromInt: Sized { + /// Converts `value` to this type, wrapping around at the boundary of the type. + #[unstable(feature = "integer_casts", issue = "157388")] + fn wrapping_cast_from(value: T) -> Self; + + /// Converts `value` to this type, saturating at the numeric bounds instead of overflowing. + #[unstable(feature = "integer_casts", issue = "157388")] + fn saturating_cast_from(value: T) -> Self; +} + +/// Fallible conversion between integers. +#[unstable(feature = "integer_casts", issue = "157388")] +#[rustc_const_unstable(feature = "integer_casts", issue = "157388")] +pub impl(self) const trait CheckedCastFromInt: Sized { + /// Converts `value` to this type, returning `None` if overflow would have occurred. + #[unstable(feature = "integer_casts", issue = "157388")] + fn checked_cast_from(value: T) -> Option; + + /// Converts `value` to this type, assuming overflow cannot occur. + /// + /// # Safety + /// + /// This results in undefined behavior when `value` will overflow when + /// converted to this type. + #[unstable(feature = "integer_casts", issue = "157388")] + unsafe fn unchecked_cast_from(value: T) -> Self; + + /// Converts `value` to this type, panicking on overflow. + /// + /// # Panics + /// + /// This function will always panic on overflow, regardless of whether overflow checks are enabled. + #[unstable(feature = "integer_casts", issue = "157388")] + fn strict_cast_from(value: T) -> Self; +} + +macro_rules! impl_int_cast { + ($Src:ty as [$($Dst:ty),*]) => {$( + #[unstable(feature = "integer_casts", issue = "157388")] + #[rustc_const_unstable(feature = "integer_casts", issue = "157388")] + const impl CheckedCastFromInt<$Src> for $Dst { + #[inline] + fn checked_cast_from(value: $Src) -> Option { + value.try_into().ok() + } + + #[inline(always)] + unsafe fn unchecked_cast_from(value: $Src) -> Self { + // SAFETY: the safety contract must be upheld by the caller. + unsafe { value.try_into().unwrap_unchecked() } + } + + #[inline] + #[track_caller] + fn strict_cast_from(value: $Src) -> Self { + match value.try_into() { + Ok(x) => x, + Err(_) => core::num::imp::overflow_panic::cast_integer() + } + } + } + + #[unstable(feature = "integer_casts", issue = "157388")] + #[rustc_const_unstable(feature = "integer_casts", issue = "157388")] + const impl BoundedCastFromInt<$Src> for $Dst { + #[inline(always)] + fn wrapping_cast_from(value: $Src) -> Self { + value as Self + } + + #[inline] + #[allow(unused_comparisons)] + #[allow(irrefutable_let_patterns)] + fn saturating_cast_from(value: $Src) -> Self { + if let Ok(x) = value.try_into() { + return x; + } + + if value < 0 { <$Dst>::MIN } else { <$Dst>::MAX } + } + } + )*}; +} + +macro_rules! impl_all_int_casts { + ([$($Src:ty),*]) => {$( + impl_int_cast!($Src as [u8, u16, u32, u64, u128, usize, i8, i16, i32, i64, i128, isize]); + )*}; +} + +impl_all_int_casts!([u8, u16, u32, u64, u128, usize, i8, i16, i32, i64, i128, isize]); diff --git a/library/core/src/default.rs b/library/core/src/default.rs index 1cc4fb6e8fdd3..359ef29bb7331 100644 --- a/library/core/src/default.rs +++ b/library/core/src/default.rs @@ -151,7 +151,7 @@ macro_rules! default_impl { ($t:ty, $v:expr, $doc:tt) => { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] - impl const Default for $t { + const impl Default for $t { #[inline(always)] #[doc = $doc] fn default() -> $t { diff --git a/library/core/src/error.md b/library/core/src/error.md index 4b62391cafc37..12027a05bab3c 100644 --- a/library/core/src/error.md +++ b/library/core/src/error.md @@ -34,7 +34,7 @@ responsibilities they cover: ## Converting Errors into Panics -The panic and error systems are not entirely distinct. Often times errors +The panic and error systems are not entirely distinct. Oftentimes errors that are anticipated runtime failures in an API might instead represent bugs to a caller. For these situations the standard library provides APIs for constructing panics with an `Error` as its source. diff --git a/library/core/src/error.rs b/library/core/src/error.rs index 011d6ac4a1c78..0f01c09c8d91c 100644 --- a/library/core/src/error.rs +++ b/library/core/src/error.rs @@ -494,7 +494,7 @@ where /// `Request` supports generic, type-driven access to data. Its use is currently restricted to the /// standard library in cases where trait authors wish to allow trait implementors to share generic /// information across trait boundaries. The motivating and prototypical use case is -/// `core::error::Error` which would otherwise require a method per concrete type (eg. +/// `core::error::Error` which would otherwise require a method per concrete type (e.g. /// `std::backtrace::Backtrace` instance that implementors want to expose to users). /// /// # Data flow @@ -502,29 +502,29 @@ where /// To describe the intended data flow for Request objects, let's consider two conceptual users /// separated by API boundaries: /// -/// * Consumer - the consumer requests objects using a Request instance; eg a crate that offers +/// * Consumer - the consumer requests objects using a Request instance; e.g. a crate that offers /// fancy `Error`/`Result` reporting to users wants to request a Backtrace from a given `dyn Error`. /// -/// * Producer - the producer provides objects when requested via Request; eg. a library with an +/// * Producer - the producer provides objects when requested via Request; e.g. a library with an /// an `Error` implementation that automatically captures backtraces at the time instances are /// created. /// -/// The consumer only needs to know where to submit their request and are expected to handle the +/// The consumer only needs to know where to submit their request and is expected to handle the /// request not being fulfilled by the use of `Option` in the responses offered by the producer. /// /// * A Producer initializes the value of one of its fields of a specific type. (or is otherwise -/// prepared to generate a value requested). eg, `backtrace::Backtrace` or -/// `std::backtrace::Backtrace` +/// prepared to generate a value requested). e.g., `backtrace::Backtrace` or +/// `std::backtrace::Backtrace`. /// * A Consumer requests an object of a specific type (say `std::backtrace::Backtrace`). In the /// case of a `dyn Error` trait object (the Producer), there are functions called `request_ref` and /// `request_value` to simplify obtaining an `Option` for a given type. /// * The Producer, when requested, populates the given Request object which is given as a mutable /// reference. /// * The Consumer extracts a value or reference to the requested type from the `Request` object -/// wrapped in an `Option`; in the case of `dyn Error` the aforementioned `request_ref` and ` -/// request_value` methods mean that `dyn Error` users don't have to deal with the `Request` type at +/// wrapped in an `Option`; in the case of `dyn Error` the aforementioned `request_ref` and +/// `request_value` methods mean that `dyn Error` users don't have to deal with the `Request` type at /// all (but `Error` implementors do). The `None` case of the `Option` suggests only that the -/// Producer cannot currently offer an instance of the requested type, not it can't or never will. +/// Producer cannot currently offer an instance of the requested type, not that it can't or never will. /// /// # Examples /// diff --git a/library/core/src/escape.rs b/library/core/src/escape.rs index f459c58270818..940daeee7184c 100644 --- a/library/core/src/escape.rs +++ b/library/core/src/escape.rs @@ -167,13 +167,11 @@ union MaybeEscapedCharacter { /// Marker type to indicate that the character is always escaped, /// used to optimize the iterator implementation. #[derive(Clone, Copy)] -#[non_exhaustive] pub(crate) struct AlwaysEscaped; /// Marker type to indicate that the character may be escaped, /// used to optimize the iterator implementation. #[derive(Clone, Copy)] -#[non_exhaustive] pub(crate) struct MaybeEscaped; /// An iterator over a possibly escaped character. diff --git a/library/core/src/ffi/c_double.md b/library/core/src/ffi/c_double.md index d49e29b6e6e7f..8586dec909d92 100644 --- a/library/core/src/ffi/c_double.md +++ b/library/core/src/ffi/c_double.md @@ -1,6 +1,6 @@ Equivalent to C's `double` type. -This type will almost always be [`f64`], which is guaranteed to be an [IEEE 754 double-precision float] in Rust. That said, the standard technically only guarantees that it be a floating-point number with at least the precision of a [`float`], and it may be `f32` or something entirely different from the IEEE-754 standard. +This type will almost always be [`f64`], which is guaranteed to be an [IEEE 754 double-precision float] in Rust. That said, the standard technically only guarantees that it be a floating-point number with at least the precision of a [`float`]; some 16-bit systems use [`f32`], for example. Esoteric systems could use something entirely different from the IEEE-754 standard. [IEEE 754 double-precision float]: https://en.wikipedia.org/wiki/IEEE_754 [`float`]: c_float diff --git a/library/core/src/ffi/c_short.md b/library/core/src/ffi/c_short.md index 3d1e53d1325f3..29415129b50a7 100644 --- a/library/core/src/ffi/c_short.md +++ b/library/core/src/ffi/c_short.md @@ -1,5 +1,3 @@ Equivalent to C's `signed short` (`short`) type. This type will almost always be [`i16`], but may differ on some esoteric systems. The C standard technically only requires that this type be a signed integer with at least 16 bits; some systems may define it as `i32`, for example. - -[`char`]: c_char diff --git a/library/core/src/ffi/c_str.rs b/library/core/src/ffi/c_str.rs index cbfbed73fb1ed..f3c4072009ee4 100644 --- a/library/core/src/ffi/c_str.rs +++ b/library/core/src/ffi/c_str.rs @@ -15,7 +15,7 @@ use crate::slice::memchr; use crate::ub_checks::Invariant; #[allow(unused_imports)] use crate::ub_checks::can_dereference; -use crate::{fmt, ops, slice, str}; +use crate::{fmt, ops, range, slice, str}; // FIXME: because this is doc(inline)d, we *have* to use intra-doc links because the actual link // depends on where the item is being documented. however, since this is libcore, we can't @@ -162,7 +162,7 @@ impl Error for FromBytesWithNulError {} /// within the slice. /// /// This error is created by the [`CStr::from_bytes_until_nul`] method. -#[derive(Clone, PartialEq, Eq, Debug)] +#[derive(Clone, Copy, PartialEq, Eq, Debug)] #[stable(feature = "cstr_from_bytes_until_nul", since = "1.69.0")] pub struct FromBytesUntilNulError(()); @@ -183,7 +183,8 @@ impl fmt::Debug for CStr { } #[stable(feature = "cstr_default", since = "1.10.0")] -impl Default for &CStr { +#[rustc_const_unstable(feature = "const_default", issue = "143894")] +const impl Default for &CStr { #[inline] fn default() -> Self { c"" @@ -629,7 +630,12 @@ impl CStr { pub const fn to_bytes_with_nul(&self) -> &[u8] { // SAFETY: Transmuting a slice of `c_char`s to a slice of `u8`s // is safe on all supported targets. - unsafe { &*((&raw const self.inner) as *const [u8]) } + let bytes = unsafe { &*((&raw const self.inner) as *const [u8]) }; + + // SAFETY: A valid `CStr` always contains at least its trailing nul byte. + unsafe { crate::hint::assert_unchecked(!bytes.is_empty()) }; + + bytes } /// Iterates over the bytes in this C string. @@ -729,7 +735,7 @@ impl PartialEq<&Self> for CStr { impl PartialOrd for CStr { #[inline] fn partial_cmp(&self, other: &CStr) -> Option { - self.to_bytes().partial_cmp(&other.to_bytes()) + self.to_bytes().partial_cmp(other.to_bytes()) } } @@ -737,7 +743,7 @@ impl PartialOrd for CStr { impl Ord for CStr { #[inline] fn cmp(&self, other: &CStr) -> Ordering { - self.to_bytes().cmp(&other.to_bytes()) + self.to_bytes().cmp(other.to_bytes()) } } @@ -764,9 +770,19 @@ impl ops::Index> for CStr { } } +#[stable(feature = "new_range_from_api", since = "1.96.0")] +impl ops::Index> for CStr { + type Output = CStr; + + #[inline] + fn index(&self, index: range::RangeFrom) -> &CStr { + ops::Index::index(self, ops::RangeFrom::from(index)) + } +} + #[stable(feature = "cstring_asref", since = "1.7.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef for CStr { +const impl AsRef for CStr { #[inline] fn as_ref(&self) -> &CStr { self diff --git a/library/core/src/ffi/c_ulong.md b/library/core/src/ffi/c_ulong.md index 4ab304e657773..e311231911ba8 100644 --- a/library/core/src/ffi/c_ulong.md +++ b/library/core/src/ffi/c_ulong.md @@ -1,5 +1,5 @@ Equivalent to C's `unsigned long` type. -This type will always be [`u32`] or [`u64`]. Most notably, many Linux-based systems assume an `u64`, but Windows assumes `u32`. The C standard technically only requires that this type be an unsigned integer with the size of a [`long`], although in practice, no system would have a `ulong` that is neither a `u32` nor `u64`. +This type will always be [`u32`] or [`u64`]. Most notably, many Linux-based systems assume a `u64`, but Windows assumes `u32`. The C standard technically only requires that this type be an unsigned integer with the size of a [`long`], although in practice, no system would have a `ulong` that is neither a `u32` nor `u64`. [`long`]: c_long diff --git a/library/core/src/ffi/c_void.md b/library/core/src/ffi/c_void.md index ee7403aa04099..1c3ae6333d827 100644 --- a/library/core/src/ffi/c_void.md +++ b/library/core/src/ffi/c_void.md @@ -9,7 +9,7 @@ stabilized, it is recommended to use a newtype wrapper around an empty byte array. See the [Nomicon] for details. One could use `std::os::raw::c_void` if they want to support old Rust -compiler down to 1.1.0. After Rust 1.30.0, it was re-exported by +compilers down to 1.1.0. After Rust 1.30.0, it was re-exported by this definition. For more information, please read [RFC 2521]. [Nomicon]: https://doc.rust-lang.org/nomicon/ffi.html#representing-opaque-structs diff --git a/library/core/src/ffi/mod.rs b/library/core/src/ffi/mod.rs index f1b928da7ef3c..4e82203930d3c 100644 --- a/library/core/src/ffi/mod.rs +++ b/library/core/src/ffi/mod.rs @@ -23,20 +23,10 @@ use crate::fmt; #[stable(feature = "c_str_module", since = "1.88.0")] pub mod c_str; -#[unstable( - feature = "c_variadic", - issue = "44930", - reason = "the `c_variadic` feature has not been properly tested on all supported platforms" -)] +mod va_list; +#[stable(feature = "c_variadic", since = "1.99.0")] pub use self::va_list::{VaArgSafe, VaList}; -#[unstable( - feature = "c_variadic", - issue = "44930", - reason = "the `c_variadic` feature has not been properly tested on all supported platforms" -)] -pub mod va_list; - mod primitives; #[stable(feature = "core_ffi_c", since = "1.64.0")] pub use self::primitives::{ @@ -91,3 +81,30 @@ impl fmt::Debug for c_void { )] #[link(name = "/defaultlib:libcmt", modifiers = "+verbatim", cfg(target_feature = "crt-static"))] unsafe extern "C" {} + +// Used by rustc for checking the definitions of other function with the same symbol names +// +// See the `invalid_runtime_symbols_definitions` lint. +mod runtime_symbols { + use crate::ffi::{c_char, c_int, c_void}; + + unsafe extern "C" { + #[rustc_canonical_symbol] + fn memcpy(dest: *mut c_void, src: *const c_void, n: usize) -> *mut c_void; + + #[rustc_canonical_symbol] + fn memmove(dest: *mut c_void, src: *const c_void, n: usize) -> *mut c_void; + + #[rustc_canonical_symbol] + fn memset(s: *mut c_void, c: c_int, n: usize) -> *mut c_void; + + #[rustc_canonical_symbol] + fn memcmp(s1: *const c_void, s2: *const c_void, n: usize) -> c_int; + + #[rustc_canonical_symbol] + fn bcmp(s1: *const c_void, s2: *const c_void, n: usize) -> c_int; + + #[rustc_canonical_symbol] + fn strlen(s: *const c_char) -> usize; + } +} diff --git a/library/core/src/ffi/primitives.rs b/library/core/src/ffi/primitives.rs index fa23cf33af431..11dad9a65470c 100644 --- a/library/core/src/ffi/primitives.rs +++ b/library/core/src/ffi/primitives.rs @@ -15,24 +15,27 @@ macro_rules! type_alias { } } -type_alias! { "c_char.md", c_char = c_char_definition::c_char; #[doc(cfg(all()))] } +// `#[doc(cfg(true))]` is used to prevent rustdoc from displaying a "Available on ..." box. +// The implementation of these constants is target-specific, but every target does define them. + +type_alias! { "c_char.md", c_char = c_char_definition::c_char; #[doc(cfg(true))] } type_alias! { "c_schar.md", c_schar = i8; } type_alias! { "c_uchar.md", c_uchar = u8; } type_alias! { "c_short.md", c_short = i16; } type_alias! { "c_ushort.md", c_ushort = u16; } -type_alias! { "c_int.md", c_int = c_int_definition::c_int; #[doc(cfg(all()))] } -type_alias! { "c_uint.md", c_uint = c_int_definition::c_uint; #[doc(cfg(all()))] } +type_alias! { "c_int.md", c_int = c_int_definition::c_int; #[doc(cfg(true))] } +type_alias! { "c_uint.md", c_uint = c_int_definition::c_uint; #[doc(cfg(true))] } -type_alias! { "c_long.md", c_long = c_long_definition::c_long; #[doc(cfg(all()))] } -type_alias! { "c_ulong.md", c_ulong = c_long_definition::c_ulong; #[doc(cfg(all()))] } +type_alias! { "c_long.md", c_long = c_long_definition::c_long; #[doc(cfg(true))] } +type_alias! { "c_ulong.md", c_ulong = c_long_definition::c_ulong; #[doc(cfg(true))] } type_alias! { "c_longlong.md", c_longlong = i64; } type_alias! { "c_ulonglong.md", c_ulonglong = u64; } type_alias! { "c_float.md", c_float = f32; } -type_alias! { "c_double.md", c_double = f64; } +type_alias! { "c_double.md", c_double= c_double_definition::c_double; #[doc(cfg(true))] } mod c_char_definition { crate::cfg_select! { @@ -183,3 +186,18 @@ mod c_int_definition { } } } + +mod c_double_definition { + crate::cfg_select! { + target_arch = "avr" => { + // avr: + // Per https://gcc.gnu.org/wiki/avr-gcc#Type_Layout. The table says `4,8` because + // in C the width of `double` can be changed with the `-mdouble=32/64` setting. But + // 32-bits is the default for the rust avr target. + pub(super) type c_double = f32; + } + _ => { + pub(super) type c_double = f64; + } + } +} diff --git a/library/core/src/ffi/va_list.rs b/library/core/src/ffi/va_list.rs index d0f155316a109..63942003c568b 100644 --- a/library/core/src/ffi/va_list.rs +++ b/library/core/src/ffi/va_list.rs @@ -39,12 +39,8 @@ use crate::marker::PhantomCovariantLifetime; // derive `Copy`. However, in the future we might want to support a target where `va_copy` // allocates, or otherwise violates the requirements of `Copy`. Therefore `VaList` is only `Clone`. crate::cfg_select! { - all( - target_arch = "aarch64", - not(target_vendor = "apple"), - not(target_os = "uefi"), - not(windows), - ) => { + all(target_arch = "aarch64", not(target_vendor = "apple"), not(target_os = "uefi"), not(windows)) => + { /// AArch64 ABI implementation of a `va_list`. /// /// See the [AArch64 Procedure Call Standard] for more details. @@ -183,14 +179,52 @@ crate::cfg_select! { } } -/// A variable argument list, equivalent to `va_list` in C. +/// A variable argument list, ABI-compatible with `va_list` in C. +/// +/// This type is created in c-variadic functions when `...` is desugared. A `VaList` +/// is automatically initialized (equivalent to calling `va_start` in C). +/// +/// ``` +/// use std::ffi::VaList; +/// +/// /// # Safety +/// /// Must be passed at least `count` arguments of type `i32`. +/// unsafe extern "C" fn my_func(count: u32, ap: ...) -> i32 { +/// unsafe { vmy_func(count, ap) } +/// } +/// +/// /// # Safety +/// /// Must be passed at least `count` arguments of type `i32`. +/// unsafe fn vmy_func(count: u32, mut ap: VaList<'_>) -> i32 { +/// let mut sum = 0; +/// for _ in 0..count { +/// sum += unsafe { ap.next_arg::() }; +/// } +/// sum +/// } +/// +/// assert_eq!(unsafe { my_func(1, 42i32) }, 42); +/// assert_eq!(unsafe { my_func(3, 42i32, -7i32, 20i32) }, 55); +/// ``` +/// +/// The [`VaList::next_arg`] method reads the next argument from the variable argument list, +/// and is equivalent to C `va_arg`. +/// +/// Cloning a `VaList` performs the equivalent of C `va_copy`, producing an independent cursor +/// that arguments can be read from without affecting the original. Dropping a `VaList` performs +/// the equivalent of C `va_end`. +/// +/// A `VaList` can be used across an FFI boundary, and fully matches the platform's `va_list` in +/// terms of layout and ABI. #[repr(transparent)] #[lang = "va_list"] +#[stable(feature = "c_variadic", since = "1.99.0")] pub struct VaList<'a> { inner: VaListInner, _marker: PhantomCovariantLifetime<'a>, } +#[stable(feature = "c_variadic", since = "1.99.0")] impl fmt::Debug for VaList<'_> { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { // No need to include `_marker` in debug output. @@ -200,12 +234,17 @@ impl fmt::Debug for VaList<'_> { impl VaList<'_> { // Helper used in the implementation of the `va_copy` intrinsic. - pub(crate) fn duplicate(&self) -> Self { - Self { inner: self.inner.clone(), _marker: self._marker } + pub(crate) const fn duplicate(&self) -> Self { + Self { inner: self.inner, _marker: self._marker } } } -impl Clone for VaList<'_> { +#[stable(feature = "c_variadic", since = "1.99.0")] +#[rustc_const_unstable(feature = "const_c_variadic", issue = "151787")] +const impl<'f> Clone for VaList<'f> { + /// Clone the [`VaList`], producing a second independent cursor into the variable argument list. + /// + /// Corresponds to `va_copy` in C. #[inline] fn clone(&self) -> Self { // We only implement Clone and not Copy because some future target might not be able to @@ -216,82 +255,223 @@ impl Clone for VaList<'_> { } } -impl<'f> Drop for VaList<'f> { +#[stable(feature = "c_variadic", since = "1.99.0")] +#[rustc_const_unstable(feature = "const_c_variadic", issue = "151787")] +const impl<'f> Drop for VaList<'f> { + /// Drop the [`VaList`]. + /// + /// Corresponds to `va_end` in C. + #[inline] fn drop(&mut self) { + // Call the rust `va_end` intrinsic, which is a no-op and does not map to LLVM `va_end`. + // The rust intrinsic exists as a hook for Miri to check for UB. + // // SAFETY: this variable argument list is being dropped, so won't be read from again. unsafe { va_end(self) } } } -mod sealed { - pub trait Sealed {} - - impl Sealed for i32 {} - impl Sealed for i64 {} - impl Sealed for isize {} - - impl Sealed for u32 {} - impl Sealed for u64 {} - impl Sealed for usize {} - - impl Sealed for f64 {} - - impl Sealed for *mut T {} - impl Sealed for *const T {} -} - -/// Types that are valid to read using [`VaList::arg`]. +/// Types that are valid to read using [`VaList::next_arg`]. +/// +/// This trait is implemented for primitive types that have a variable argument application-binary +/// interface (ABI) on the current platform. It is always implemented for: +/// +/// - [`c_int`], [`c_long`] and [`c_longlong`] +/// - [`c_uint`], [`c_ulong`] and [`c_ulonglong`] +/// - [`c_double`] +/// - `*const T` and `*mut T` +/// +/// Implementations for e.g. `i32` or `usize` shouldn't be relied upon directly, +/// because they may not be available on all platforms. /// /// # Safety /// -/// The standard library implements this trait for primitive types that are -/// expected to have a variable argument application-binary interface (ABI) on all -/// platforms. +/// When C passes variable arguments, signed integers smaller than [`c_int`] are promoted +/// to [`c_int`], unsigned integers smaller than [`c_uint`] are promoted to [`c_uint`], +/// and [`c_float`] is promoted to [`c_double`]. Implementing this trait for types that are +/// subject to this promotion rule is invalid. /// -/// When C passes variable arguments, integers smaller than [`c_int`] and floats smaller -/// than [`c_double`] are implicitly promoted to [`c_int`] and [`c_double`] respectively. -/// Implementing this trait for types that are subject to this promotion rule is invalid. +/// This trait is only implemented for 128-bit integers when the platform defines the `__int128` +/// type. /// /// [`c_int`]: core::ffi::c_int +/// [`c_long`]: core::ffi::c_long +/// [`c_longlong`]: core::ffi::c_longlong +/// +/// [`c_uint`]: core::ffi::c_uint +/// [`c_ulong`]: core::ffi::c_ulong +/// [`c_ulonglong`]: core::ffi::c_ulonglong +/// +/// [`c_float`]: core::ffi::c_float /// [`c_double`]: core::ffi::c_double // We may unseal this trait in the future, but currently our `va_arg` implementations don't support -// types with an alignment larger than 8, or with a non-scalar layout. Inline assembly can be used -// to accept unsupported types in the meantime. -pub unsafe trait VaArgSafe: sealed::Sealed {} +// types with a non-scalar layout. Inline assembly can be used to accept unsupported types in the +// meantime. +#[lang = "va_arg_safe"] +#[stable(feature = "c_variadic", since = "1.99.0")] +pub impl(self) unsafe trait VaArgSafe {} + +crate::cfg_select! { + any(target_arch = "avr", target_arch = "msp430") => { + // c_int/c_uint are i16/u16 on these targets. + // + // - i8 is implicitly promoted to c_int in C, and cannot implement `VaArgSafe`. + // - u8 is implicitly promoted to c_uint in C, and cannot implement `VaArgSafe`. + #[stable(feature = "c_variadic", since = "1.99.0")] + unsafe impl VaArgSafe for i16 {} + #[stable(feature = "c_variadic", since = "1.99.0")] + unsafe impl VaArgSafe for u16 {} + } + _ => { + // c_int/c_uint are i32/u32 on this target. + // + // - i8 and i16 are implicitly promoted to c_int in C, and cannot implement `VaArgSafe`. + // - u8 and u16 are implicitly promoted to c_uint in C, and cannot implement `VaArgSafe`. + } +} -// i8 and i16 are implicitly promoted to c_int in C, and cannot implement `VaArgSafe`. +crate::cfg_select! { + target_arch = "avr" => { + // c_double is f32 on this target. + #[stable(feature = "c_variadic", since = "1.99.0")] + unsafe impl VaArgSafe for f32 {} + } + _ => { + // c_double is f64 on this target. + // + // - f32 is implicitly promoted to c_double in C, and cannot implement `VaArgSafe`. + } +} + +#[stable(feature = "c_variadic", since = "1.99.0")] unsafe impl VaArgSafe for i32 {} +#[stable(feature = "c_variadic", since = "1.99.0")] unsafe impl VaArgSafe for i64 {} +#[stable(feature = "c_variadic", since = "1.99.0")] unsafe impl VaArgSafe for isize {} -// u8 and u16 are implicitly promoted to c_int in C, and cannot implement `VaArgSafe`. +#[stable(feature = "c_variadic", since = "1.99.0")] unsafe impl VaArgSafe for u32 {} +#[stable(feature = "c_variadic", since = "1.99.0")] unsafe impl VaArgSafe for u64 {} +#[stable(feature = "c_variadic", since = "1.99.0")] unsafe impl VaArgSafe for usize {} -// f32 is implicitly promoted to c_double in C, and cannot implement `VaArgSafe`. +// Implement `VaArgSafe` for 128-bit integers on targets where clang provides `__int128`. +// +// GCC does not implement `__int128` for any 16-bit/32-bit target: +// +// https://gcc.gnu.org/onlinedocs/gcc-15.2.0/gcc/_005f_005fint128.html +// +// > There is no support in GCC for expressing an integer constant of type __int128 for targets +// > with long long integer less than 128 bits wide. +// +// Per https://learn.microsoft.com/en-us/cpp/cpp/data-type-ranges?view=msvc-170, MSVC does not +// define `__int128`. +// +// Clang is slightly more permissive: it defines `__int128` on wasm32 (a 32-bit target) and also +// does provide `__int128` on 64-bit `*-pc-windows-msvc`, and we follow suit. +cfg_select! { + any( + target_arch = "wasm32", + all(target_arch = "x86_64", target_abi = "x32"), + all( + target_pointer_width = "64", + any( + target_arch = "aarch64", + target_arch = "amdgpu", + target_arch = "arm64ec", + target_arch = "bpf", + target_arch = "loongarch64", + target_arch = "mips64", + target_arch = "mips64r6", + target_arch = "nvptx64", + target_arch = "powerpc64", + target_arch = "riscv64", + target_arch = "s390x", + target_arch = "sparc64", + target_arch = "wasm64", + target_arch = "x86_64", + ), + ), + ) => { + #[unstable_feature_bound(c_variadic_int128)] + #[unstable(feature = "c_variadic_int128", issue = "155752")] + unsafe impl VaArgSafe for i128 {} + #[unstable_feature_bound(c_variadic_int128)] + #[unstable(feature = "c_variadic_int128", issue = "155752")] + unsafe impl VaArgSafe for u128 {} + } + _ => { + #[repr(transparent)] + #[derive(Clone, Copy)] + // When there are no actual implementations on i128, declare the c_variadic_int128 feature + // on a private type so that the feature is defined on all targets. + #[unstable(feature = "c_variadic_int128", issue = "155752")] + struct S(i32); + } +} + +#[stable(feature = "c_variadic", since = "1.99.0")] unsafe impl VaArgSafe for f64 {} +#[stable(feature = "c_variadic", since = "1.99.0")] unsafe impl VaArgSafe for *mut T {} +#[stable(feature = "c_variadic", since = "1.99.0")] unsafe impl VaArgSafe for *const T {} +// Check that relevant `core::ffi` types implement `VaArgSafe`. +const _: () = { + const fn va_arg_safe_check() {} + + va_arg_safe_check::(); + va_arg_safe_check::(); + va_arg_safe_check::(); + + va_arg_safe_check::(); + va_arg_safe_check::(); + va_arg_safe_check::(); + + va_arg_safe_check::(); + + va_arg_safe_check::<*const crate::ffi::c_void>(); + va_arg_safe_check::<*mut crate::ffi::c_void>(); + + va_arg_safe_check::<*const crate::ffi::c_char>(); + va_arg_safe_check::<*mut crate::ffi::c_char>(); +}; + impl<'f> VaList<'f> { - /// Advance to and read the next variable argument. + /// Read the next argument from the variable argument list. + /// + /// Only types that implement [`VaArgSafe`] can be read from a variable argument list. /// /// # Safety /// - /// This function is only sound to call when: + /// This function is safe to call only if all of the following conditions are satisfied: /// - /// - there is a next variable argument available. - /// - the next argument's type must be ABI-compatible with the type `T`. - /// - the next argument must have a properly initialized value of type `T`. + /// - There is another c-variadic argument to read. + /// - The actual type of the argument `U` is compatible with `T` (as defined below). + /// - If `U` and `T` are both integer types, then the value passed by the caller must be + /// representable in both types. + /// - If `T` is not [`Copy`], then it must not have already been read using `next_arg` + /// on a [`clone`][VaList::clone]d copy of this `VaList`. + /// (Currently, all types implementing [`VaArgSafe`] also implement [`Copy`], + /// but this may change in the future.) /// - /// Calling this function with an incompatible type, an invalid value, or when there - /// are no more variable arguments, is unsound. + /// Types `T` and `U` are compatible when: /// - /// [valid]: https://doc.rust-lang.org/nightly/nomicon/what-unsafe-does.html - #[inline] - pub unsafe fn arg(&mut self) -> T { + /// - `T` and `U` are the same type. + /// - `T` and `U` are integer types of the same size. + /// - `T` and `U` are both pointers, and their target types are compatible. + /// - `T` is a pointer to [`c_void`] and `U` is a pointer to [`i8`] or [`u8`], or vice versa. + /// + /// [`c_void`]: core::ffi::c_void + #[inline] // Avoid codegen when not used to help backends that don't support VaList. + #[stable(feature = "c_variadic", since = "1.99.0")] + #[rustc_const_unstable(feature = "const_c_variadic", issue = "151787")] + #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces + pub const unsafe fn next_arg(&mut self) -> T { // SAFETY: the caller must uphold the safety contract for `va_arg`. unsafe { va_arg(self) } } diff --git a/library/core/src/field.rs b/library/core/src/field.rs new file mode 100644 index 0000000000000..915a4c07b9e23 --- /dev/null +++ b/library/core/src/field.rs @@ -0,0 +1,170 @@ +//! Field Reflection + +use crate::fmt; +use crate::hash::{Hash, Hasher}; +use crate::marker::PhantomData; + +/// Field Representing Type +#[unstable(feature = "field_representing_type_raw", issue = "none")] +#[lang = "field_representing_type"] +#[fundamental] +pub struct FieldRepresentingType { + // We want this type to be invariant over `T`, because otherwise `field_of!(Struct<'short>, + // field)` is a subtype of `field_of!(Struct<'long>, field)`. This subtype relationship does not + // have an immediately obvious meaning and we want to prevent people from relying on it. + _phantom: PhantomData T>, +} + +impl fmt::Debug + for FieldRepresentingType +{ + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + enum Member { + Name(&'static str), + Index(u32), + } + impl fmt::Display for Member { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self { + Self::Name(name) => fmt::Display::fmt(name, f), + Self::Index(idx) => fmt::Display::fmt(idx, f), + } + } + } + let (variant, field) = const { + use crate::mem::type_info::{self, Type, TypeKind}; + let type_id = type_info::of::(); + match Type::of::().kind { + TypeKind::Struct => (None, Member::Name(type_id.field(0, FIELD as usize).name())), + TypeKind::Tuple => (None, Member::Index(FIELD)), + TypeKind::Enum => { + let variant_name = type_id.variant(VARIANT as usize).name(); + let field_name = type_id.field(VARIANT as usize, FIELD as usize).name(); + (Some(variant_name), Member::Name(field_name)) + } + TypeKind::Union => (None, Member::Name(type_id.field(0, FIELD as usize).name())), + _ => unreachable!(), + } + }; + let type_name = const { crate::any::type_name::() }; + match variant { + Some(variant) => write!(f, "field_of!({type_name}, {variant}.{field})"), + None => write!(f, "field_of!({type_name}, {field})"), + } + // NOTE: if there are changes in the reflection work and the above no + // longer compiles, then the following debug impl could also work in + // the meantime: + // ```rust + // let type_name = const { type_name::() }; + // write!(f, "field_of!({type_name}, {VARIANT}.{FIELD})") + // ``` + } +} + +impl Copy + for FieldRepresentingType +{ +} + +impl Clone + for FieldRepresentingType +{ + fn clone(&self) -> Self { + *self + } +} + +impl Default + for FieldRepresentingType +{ + fn default() -> Self { + Self { _phantom: PhantomData::default() } + } +} + +impl Hash + for FieldRepresentingType +{ + fn hash(&self, state: &mut H) { + self._phantom.hash(state); + } +} + +impl PartialEq + for FieldRepresentingType +{ + fn eq(&self, other: &Self) -> bool { + self._phantom == other._phantom + } +} + +impl Eq + for FieldRepresentingType +{ +} + +impl PartialOrd + for FieldRepresentingType +{ + fn partial_cmp(&self, other: &Self) -> Option { + self._phantom.partial_cmp(&other._phantom) + } +} + +impl Ord + for FieldRepresentingType +{ + fn cmp(&self, other: &Self) -> crate::cmp::Ordering { + self._phantom.cmp(&other._phantom) + } +} + +/// Expands to the field representing type of the given field. +/// +/// The container type may be a tuple, `struct`, `union` or `enum`. In the case of an enum, the +/// variant must also be specified. Only a single field is supported. +#[unstable(feature = "field_projections", issue = "145383")] +#[allow_internal_unstable(field_representing_type_raw, builtin_syntax)] +#[diagnostic::on_unmatched_args( + note = "this macro expects a container type and a field path, like `field_of!(Type, field)` or `field_of!(Enum, Variant.field)`" +)] +#[diagnostic::opaque] +// NOTE: when stabilizing this macro, we can never add new trait impls for `FieldRepresentingType`, +// since it is `#[fundamental]` and thus could break users of this macro, since the compiler expands +// it to `FieldRepresentingType<...>`. Thus stabilizing this requires careful thought about the +// completeness of the trait impls for `FieldRepresentingType`. +pub macro field_of($Container:ty, $($fields:expr)+ $(,)?) { + builtin # field_of($Container, $($fields)+) +} + +/// Type representing a field of a `struct`, `union`, `enum` variant or tuple. +/// +/// # Safety +/// +/// Given a valid value of type `Self::Base`, there exists a valid value of type `Self::Type` at +/// byte offset `OFFSET` +#[lang = "field"] +#[unstable(feature = "field_projections", issue = "145383")] +#[rustc_deny_explicit_impl] +#[rustc_dyn_incompatible_trait] +// NOTE: the compiler provides the impl of `Field` for `FieldRepresentingType` when it can guarantee +// the safety requirements of this trait. It also has to manually add the correct trait bounds on +// associated types (and the `Self` type). Thus any changes to the bounds here must be reflected in +// the old and new trait solver: +// - `fn assemble_candidates_for_field_trait` in +// `compiler/rustc_trait_selection/src/traits/select/candidate_assembly.rs`, and +// - `fn consider_builtin_field_candidate` in +// `compiler/rustc_next_trait_solver/src/solve/trait_goals.rs`. +pub unsafe trait Field: Send + Sync + Copy { + /// The type of the base where this field exists in. + #[lang = "field_base"] + type Base; + + /// The type of the field. + #[lang = "field_type"] + type Type; + + /// The offset of the field in bytes. + #[lang = "field_offset"] + const OFFSET: usize = crate::intrinsics::field_offset::(); +} diff --git a/library/core/src/fmt/builders.rs b/library/core/src/fmt/builders.rs index 7550dac45cd02..ceec98c8659fb 100644 --- a/library/core/src/fmt/builders.rs +++ b/library/core/src/fmt/builders.rs @@ -1,5 +1,6 @@ #![allow(unused_imports)] +use crate::cell::Cell; use crate::fmt::{self, Debug, Formatter}; struct PadAdapter<'buf, 'state> { @@ -50,6 +51,29 @@ impl fmt::Write for PadAdapter<'_, '_> { } } +/// Wraps an `FnOnce` formatting closure in a type that implements [`fmt::Debug`] by calling the +/// closure, allowing the `*_with` builder methods to forward to their `&dyn fmt::Debug` +/// counterparts. +/// +/// By doing this, the builder logic is monomorphized only once and not for every closure type +/// (see #149745). +/// +/// Formatting a `DebugOnce` consumes the closure, so attempting to format it more than once +/// panics. This never happens because the debug builders format each value exactly once. +struct DebugOnce(Cell>); + +impl fmt::Debug for DebugOnce +where + F: FnOnce(&mut fmt::Formatter<'_>) -> fmt::Result, +{ + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self.0.take() { + Some(value_fmt) => value_fmt(f), + None => panic!("formatting closure called more than once"), + } + } +} + /// A struct to help with [`fmt::Debug`](Debug) implementations. /// /// This is useful when you wish to output a formatted struct as a part of your @@ -130,18 +154,6 @@ impl<'a, 'b: 'a> DebugStruct<'a, 'b> { /// ``` #[stable(feature = "debug_builders", since = "1.2.0")] pub fn field(&mut self, name: &str, value: &dyn fmt::Debug) -> &mut Self { - self.field_with(name, |f| value.fmt(f)) - } - - /// Adds a new field to the generated struct output. - /// - /// This method is equivalent to [`DebugStruct::field`], but formats the - /// value using a provided closure rather than by calling [`Debug::fmt`]. - #[unstable(feature = "debug_closure_helpers", issue = "117729")] - pub fn field_with(&mut self, name: &str, value_fmt: F) -> &mut Self - where - F: FnOnce(&mut fmt::Formatter<'_>) -> fmt::Result, - { self.result = self.result.and_then(|_| { if self.is_pretty() { if !self.has_fields { @@ -152,14 +164,14 @@ impl<'a, 'b: 'a> DebugStruct<'a, 'b> { let mut writer = PadAdapter::wrap(self.fmt, &mut slot, &mut state); writer.write_str(name)?; writer.write_str(": ")?; - value_fmt(&mut writer)?; + value.fmt(&mut writer)?; writer.write_str(",\n") } else { let prefix = if self.has_fields { ", " } else { " { " }; self.fmt.write_str(prefix)?; self.fmt.write_str(name)?; self.fmt.write_str(": ")?; - value_fmt(self.fmt) + value.fmt(self.fmt) } }); @@ -167,6 +179,18 @@ impl<'a, 'b: 'a> DebugStruct<'a, 'b> { self } + /// Adds a new field to the generated struct output. + /// + /// This method is equivalent to [`DebugStruct::field`], but formats the + /// value using a provided closure rather than by calling [`Debug::fmt`]. + #[unstable(feature = "debug_closure_helpers", issue = "117729")] + pub fn field_with(&mut self, name: &str, value_fmt: F) -> &mut Self + where + F: FnOnce(&mut fmt::Formatter<'_>) -> fmt::Result, + { + self.field(name, &DebugOnce(Cell::new(Some(value_fmt)))) + } + /// Marks the struct as non-exhaustive, indicating to the reader that there are some other /// fields that are not shown in the debug representation. /// @@ -327,18 +351,6 @@ impl<'a, 'b: 'a> DebugTuple<'a, 'b> { /// ``` #[stable(feature = "debug_builders", since = "1.2.0")] pub fn field(&mut self, value: &dyn fmt::Debug) -> &mut Self { - self.field_with(|f| value.fmt(f)) - } - - /// Adds a new field to the generated tuple struct output. - /// - /// This method is equivalent to [`DebugTuple::field`], but formats the - /// value using a provided closure rather than by calling [`Debug::fmt`]. - #[unstable(feature = "debug_closure_helpers", issue = "117729")] - pub fn field_with(&mut self, value_fmt: F) -> &mut Self - where - F: FnOnce(&mut fmt::Formatter<'_>) -> fmt::Result, - { self.result = self.result.and_then(|_| { if self.is_pretty() { if self.fields == 0 { @@ -347,12 +359,12 @@ impl<'a, 'b: 'a> DebugTuple<'a, 'b> { let mut slot = None; let mut state = Default::default(); let mut writer = PadAdapter::wrap(self.fmt, &mut slot, &mut state); - value_fmt(&mut writer)?; + value.fmt(&mut writer)?; writer.write_str(",\n") } else { let prefix = if self.fields == 0 { "(" } else { ", " }; self.fmt.write_str(prefix)?; - value_fmt(self.fmt) + value.fmt(self.fmt) } }); @@ -360,6 +372,18 @@ impl<'a, 'b: 'a> DebugTuple<'a, 'b> { self } + /// Adds a new field to the generated tuple struct output. + /// + /// This method is equivalent to [`DebugTuple::field`], but formats the + /// value using a provided closure rather than by calling [`Debug::fmt`]. + #[unstable(feature = "debug_closure_helpers", issue = "117729")] + pub fn field_with(&mut self, value_fmt: F) -> &mut Self + where + F: FnOnce(&mut fmt::Formatter<'_>) -> fmt::Result, + { + self.field(&DebugOnce(Cell::new(Some(value_fmt)))) + } + /// Marks the tuple struct as non-exhaustive, indicating to the reader that there are some /// other fields that are not shown in the debug representation. /// @@ -453,10 +477,7 @@ struct DebugInner<'a, 'b: 'a> { } impl<'a, 'b: 'a> DebugInner<'a, 'b> { - fn entry_with(&mut self, entry_fmt: F) - where - F: FnOnce(&mut fmt::Formatter<'_>) -> fmt::Result, - { + fn entry(&mut self, entry: &dyn fmt::Debug) { self.result = self.result.and_then(|_| { if self.is_pretty() { if !self.has_fields { @@ -465,19 +486,26 @@ impl<'a, 'b: 'a> DebugInner<'a, 'b> { let mut slot = None; let mut state = Default::default(); let mut writer = PadAdapter::wrap(self.fmt, &mut slot, &mut state); - entry_fmt(&mut writer)?; + entry.fmt(&mut writer)?; writer.write_str(",\n") } else { if self.has_fields { self.fmt.write_str(", ")? } - entry_fmt(self.fmt) + entry.fmt(self.fmt) } }); self.has_fields = true; } + fn entry_with(&mut self, entry_fmt: F) + where + F: FnOnce(&mut fmt::Formatter<'_>) -> fmt::Result, + { + self.entry(&DebugOnce(Cell::new(Some(entry_fmt)))); + } + fn is_pretty(&self) -> bool { self.fmt.alternate() } @@ -546,7 +574,7 @@ impl<'a, 'b: 'a> DebugSet<'a, 'b> { /// ``` #[stable(feature = "debug_builders", since = "1.2.0")] pub fn entry(&mut self, entry: &dyn fmt::Debug) -> &mut Self { - self.inner.entry_with(|f| entry.fmt(f)); + self.inner.entry(entry); self } @@ -738,7 +766,7 @@ impl<'a, 'b: 'a> DebugList<'a, 'b> { /// ``` #[stable(feature = "debug_builders", since = "1.2.0")] pub fn entry(&mut self, entry: &dyn fmt::Debug) -> &mut Self { - self.inner.entry_with(|f| entry.fmt(f)); + self.inner.entry(entry); self } @@ -969,18 +997,6 @@ impl<'a, 'b: 'a> DebugMap<'a, 'b> { /// ``` #[stable(feature = "debug_map_key_value", since = "1.42.0")] pub fn key(&mut self, key: &dyn fmt::Debug) -> &mut Self { - self.key_with(|f| key.fmt(f)) - } - - /// Adds the key part of a new entry to the map output. - /// - /// This method is equivalent to [`DebugMap::key`], but formats the - /// key using a provided closure rather than by calling [`Debug::fmt`]. - #[unstable(feature = "debug_closure_helpers", issue = "117729")] - pub fn key_with(&mut self, key_fmt: F) -> &mut Self - where - F: FnOnce(&mut fmt::Formatter<'_>) -> fmt::Result, - { self.result = self.result.and_then(|_| { assert!( !self.has_key, @@ -995,13 +1011,13 @@ impl<'a, 'b: 'a> DebugMap<'a, 'b> { let mut slot = None; self.state = Default::default(); let mut writer = PadAdapter::wrap(self.fmt, &mut slot, &mut self.state); - key_fmt(&mut writer)?; + key.fmt(&mut writer)?; writer.write_str(": ")?; } else { if self.has_fields { self.fmt.write_str(", ")? } - key_fmt(self.fmt)?; + key.fmt(self.fmt)?; self.fmt.write_str(": ")?; } @@ -1012,6 +1028,18 @@ impl<'a, 'b: 'a> DebugMap<'a, 'b> { self } + /// Adds the key part of a new entry to the map output. + /// + /// This method is equivalent to [`DebugMap::key`], but formats the + /// key using a provided closure rather than by calling [`Debug::fmt`]. + #[unstable(feature = "debug_closure_helpers", issue = "117729")] + pub fn key_with(&mut self, key_fmt: F) -> &mut Self + where + F: FnOnce(&mut fmt::Formatter<'_>) -> fmt::Result, + { + self.key(&DebugOnce(Cell::new(Some(key_fmt)))) + } + /// Adds the value part of a new entry to the map output. /// /// This method, together with `key`, is an alternative to `entry` that @@ -1045,28 +1073,16 @@ impl<'a, 'b: 'a> DebugMap<'a, 'b> { /// ``` #[stable(feature = "debug_map_key_value", since = "1.42.0")] pub fn value(&mut self, value: &dyn fmt::Debug) -> &mut Self { - self.value_with(|f| value.fmt(f)) - } - - /// Adds the value part of a new entry to the map output. - /// - /// This method is equivalent to [`DebugMap::value`], but formats the - /// value using a provided closure rather than by calling [`Debug::fmt`]. - #[unstable(feature = "debug_closure_helpers", issue = "117729")] - pub fn value_with(&mut self, value_fmt: F) -> &mut Self - where - F: FnOnce(&mut fmt::Formatter<'_>) -> fmt::Result, - { self.result = self.result.and_then(|_| { assert!(self.has_key, "attempted to format a map value before its key"); if self.is_pretty() { let mut slot = None; let mut writer = PadAdapter::wrap(self.fmt, &mut slot, &mut self.state); - value_fmt(&mut writer)?; + value.fmt(&mut writer)?; writer.write_str(",\n")?; } else { - value_fmt(self.fmt)?; + value.fmt(self.fmt)?; } self.has_key = false; @@ -1077,6 +1093,18 @@ impl<'a, 'b: 'a> DebugMap<'a, 'b> { self } + /// Adds the value part of a new entry to the map output. + /// + /// This method is equivalent to [`DebugMap::value`], but formats the + /// value using a provided closure rather than by calling [`Debug::fmt`]. + #[unstable(feature = "debug_closure_helpers", issue = "117729")] + pub fn value_with(&mut self, value_fmt: F) -> &mut Self + where + F: FnOnce(&mut fmt::Formatter<'_>) -> fmt::Result, + { + self.value(&DebugOnce(Cell::new(Some(value_fmt)))) + } + /// Adds the contents of an iterator of entries to the map output. /// /// # Examples @@ -1227,7 +1255,7 @@ impl<'a, 'b: 'a> DebugMap<'a, 'b> { /// assert_eq!(format!("{:?}", wrapped), "'a'"); /// ``` #[stable(feature = "fmt_from_fn", since = "1.93.0")] -#[rustc_const_stable(feature = "const_fmt_from_fn", since = "CURRENT_RUSTC_VERSION")] +#[rustc_const_stable(feature = "const_fmt_from_fn", since = "1.95.0")] #[must_use = "returns a type implementing Debug and Display, which do not have any effects unless they are used"] pub const fn from_fn) -> fmt::Result>(f: F) -> FromFn { FromFn(f) diff --git a/library/core/src/fmt/float.rs b/library/core/src/fmt/float.rs index 6a458436726cf..bb70e59f960ed 100644 --- a/library/core/src/fmt/float.rs +++ b/library/core/src/fmt/float.rs @@ -1,6 +1,6 @@ use crate::fmt::{Debug, Display, Formatter, LowerExp, Result, UpperExp}; use crate::mem::MaybeUninit; -use crate::num::{flt2dec, fmt as numfmt}; +use crate::num::imp::{flt2dec, fmt as numfmt}; #[doc(hidden)] trait GeneralFormat: PartialOrd { @@ -171,8 +171,7 @@ where }; if let Some(precision) = fmt.options.get_precision() { - // 1 integral digit + `precision` fractional digits = `precision + 1` total digits - float_to_exponential_common_exact(fmt, num, sign, precision + 1, upper) + float_to_exponential_common_exact(fmt, num, sign, precision, upper) } else { float_to_exponential_common_shortest(fmt, num, sign, upper) } diff --git a/library/core/src/fmt/mod.rs b/library/core/src/fmt/mod.rs index e20109c3cc9a8..6a4c58afc16f3 100644 --- a/library/core/src/fmt/mod.rs +++ b/library/core/src/fmt/mod.rs @@ -6,7 +6,7 @@ use crate::cell::{Cell, Ref, RefCell, RefMut, SyncUnsafeCell, UnsafeCell}; use crate::char::EscapeDebugExtArgs; use crate::hint::assert_unchecked; use crate::marker::{PhantomData, PointeeSized}; -use crate::num::fmt as numfmt; +use crate::num::imp::fmt as numfmt; use crate::ops::Deref; use crate::ptr::NonNull; use crate::{iter, mem, result, str}; @@ -36,8 +36,10 @@ pub enum Alignment { Center, } -#[unstable(feature = "int_format_into", issue = "138215")] -pub use num_buffer::{NumBuffer, NumBufferTrait}; +#[stable(feature = "int_format_into", since = "1.98.0")] +pub use num_buffer::NumBuffer; +#[unstable(feature = "fmt_internals", issue = "none")] +pub use num_buffer::NumBufferTrait; #[stable(feature = "debug_builders", since = "1.2.0")] pub use self::builders::{DebugList, DebugMap, DebugSet, DebugStruct, DebugTuple}; @@ -330,9 +332,7 @@ mod flags { } impl FormattingOptions { - /// Construct a new `FormatterBuilder` with the supplied `Write` trait - /// object for output that is equivalent to the `{}` formatting - /// specifier: + /// Construct a new `FormattingOptions` representing the plain `{}` formatting specifier: /// /// - no flags, /// - filled with spaces, @@ -516,7 +516,7 @@ impl FormattingOptions { pub const fn get_precision(&self) -> Option { if self.flags & flags::PRECISION_FLAG != 0 { Some(self.precision) } else { None } } - /// Returns the current precision. + /// Returns the current `x?` or `X?` flag. #[unstable(feature = "formatting_options", issue = "118117")] pub const fn get_debug_as_hex(&self) -> Option { if self.flags & flags::DEBUG_LOWER_HEX_FLAG != 0 { @@ -1037,9 +1037,10 @@ impl Display for Arguments<'_> { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_on_unimplemented( on( - crate_local, + all(crate_local, not(Self = "{union}")), note = "add `#[derive(Debug)]` to `{Self}` or manually `impl {This} for {Self}`" ), + on(all(crate_local, Self = "{union}"), note = "manually `impl {This} for {Self}`"), on( from_desugaring = "FormatLiteral", label = "`{Self}` cannot be formatted using `{{:?}}` because it doesn't implement `{This}`" @@ -1175,7 +1176,7 @@ pub use macros::Debug; ), on( from_desugaring = "FormatLiteral", - note = "in format strings you may be able to use `{{:?}}` (or {{:#?}} for pretty-print) instead", + note = "in format strings you may be able to use `{{:?}}` (or `{{:#?}}` for pretty-print) instead", label = "`{Self}` cannot be formatted with the default formatter", ), message = "`{Self}` doesn't implement `{This}`" @@ -1610,7 +1611,7 @@ pub trait UpperExp: PointeeSized { /// /// let mut output = String::new(); /// fmt::write(&mut output, format_args!("Hello {}!", "world")) -/// .expect("Error occurred while trying to write in String"); +/// .expect("Writing to a `String` should not fail"); /// assert_eq!(output, "Hello world!"); /// ``` /// @@ -1621,7 +1622,7 @@ pub trait UpperExp: PointeeSized { /// /// let mut output = String::new(); /// write!(&mut output, "Hello {}!", "world") -/// .expect("Error occurred while trying to write in String"); +/// .expect("Writing to a `String` should not fail"); /// assert_eq!(output, "Hello world!"); /// ``` /// @@ -2006,7 +2007,13 @@ impl<'a> Formatter<'a> { // SAFETY: Per the precondition. unsafe { self.write_formatted_parts(&formatted) } } else { - let post_padding = self.padding(width - len as u16, Alignment::Right)?; + // Padding widths are capped at `u16`, so reaching this branch means + // the formatted output is also shorter than `u16::MAX`. + let len = match u16::try_from(len) { + Ok(len) => len, + Err(_) => unreachable!(), + }; + let post_padding = self.padding(width - len, Alignment::Right)?; // SAFETY: Per the precondition. unsafe { self.write_formatted_parts(&formatted)?; @@ -2570,6 +2577,21 @@ impl<'a> Formatter<'a> { builder.finish() } + /// Shrinks `derive(Debug)` code, for faster compilation and smaller binaries. + /// For C-like enums with concatenated variant name strings. + #[doc(hidden)] + #[unstable(feature = "fmt_helpers_for_derive", issue = "none")] + pub fn debug_c_like_enum_write_str<'b>( + &'b mut self, + names: &str, + offset: &[usize], + discr: usize, + ) -> Result { + let start = offset[discr]; + let end = offset[discr + 1]; + self.write_str(&names[start..end]) + } + /// Creates a `DebugTuple` builder designed to assist with creation of /// `fmt::Debug` implementations for tuple structs. /// @@ -2920,7 +2942,7 @@ impl Debug for str { // the loop here first skips over runs of printable ASCII as a fast path. // other chars (unicode, or ASCII that needs escaping) are then handled per-`char`. let mut rest = self; - while rest.len() > 0 { + while !rest.is_empty() { let Some(non_printable_start) = rest.as_bytes().iter().position(|&b| needs_escape(b)) else { printable_range.end += rest.len(); @@ -2934,7 +2956,7 @@ impl Debug for str { let mut chars = rest.chars(); if let Some(c) = chars.next() { let esc = c.escape_debug_ext(EscapeDebugExtArgs { - escape_grapheme_extended: true, + escape_grapheme_extender: true, escape_single_quote: false, escape_double_quote: true, }); @@ -2966,7 +2988,7 @@ impl Debug for char { fn fmt(&self, f: &mut Formatter<'_>) -> Result { f.write_char('\'')?; let esc = self.escape_debug_ext(EscapeDebugExtArgs { - escape_grapheme_extended: true, + escape_grapheme_extender: true, escape_single_quote: true, escape_double_quote: false, }); @@ -2989,20 +3011,19 @@ impl Display for char { #[stable(feature = "rust1", since = "1.0.0")] impl Pointer for *const T { fn fmt(&self, f: &mut Formatter<'_>) -> Result { - if <::Metadata as core::unit::IsUnit>::is_unit() { - pointer_fmt_inner(self.expose_provenance(), f) + // Since the formatting will be identical for all pointer types, erase the pointee type and + // metadata type to reduce the amount of codegen work needed for each distinct type. + let ptr: *const T = *self; + let ptr_addr = ptr.expose_provenance(); + if <::Metadata as core::unit::IsUnit>::IS_UNIT { + pointer_fmt_inner(ptr_addr, f) } else { - f.debug_struct("Pointer") - .field_with("addr", |f| pointer_fmt_inner(self.expose_provenance(), f)) - .field("metadata", &core::ptr::metadata(*self)) - .finish() + wide_pointer_fmt_inner(ptr_addr, &core::ptr::metadata(ptr), f) } } } -/// Since the formatting will be identical for all pointer types, uses a -/// non-monomorphized implementation for the actual formatting to reduce the -/// amount of codegen work needed. +/// Formats an address in `fmt::Pointer` style. /// /// This uses `ptr_addr: usize` and not `ptr: *const ()` to be able to use this for /// `fn(...) -> ...` without using [problematic] "Oxford Casts". @@ -3031,6 +3052,14 @@ pub(crate) fn pointer_fmt_inner(ptr_addr: usize, f: &mut Formatter<'_>) -> Resul ret } +/// Formats a wide pointer (address and type-erased metadata) in `fmt::Pointer` style. +fn wide_pointer_fmt_inner(ptr_addr: usize, metadata: &dyn Debug, f: &mut Formatter<'_>) -> Result { + f.debug_struct("Pointer") + .field_with("addr", move |f| pointer_fmt_inner(ptr_addr, f)) + .field("metadata", metadata) + .finish() +} + #[stable(feature = "rust1", since = "1.0.0")] impl Pointer for *mut T { fn fmt(&self, f: &mut Formatter<'_>) -> Result { @@ -3160,7 +3189,7 @@ impl Debug for Ref<'_, T> { #[stable(feature = "rust1", since = "1.0.0")] impl Debug for RefMut<'_, T> { fn fmt(&self, f: &mut Formatter<'_>) -> Result { - Debug::fmt(&*(self.deref()), f) + Debug::fmt(self.deref(), f) } } diff --git a/library/core/src/fmt/num.rs b/library/core/src/fmt/num.rs index 253a7b7587e49..b1e627f6df9e0 100644 --- a/library/core/src/fmt/num.rs +++ b/library/core/src/fmt/num.rs @@ -2,7 +2,7 @@ use crate::fmt::NumBuffer; use crate::mem::MaybeUninit; -use crate::num::fmt as numfmt; +use crate::num::imp::fmt as numfmt; use crate::{fmt, str}; /// Formatting of integers with a non-decimal radix. @@ -260,7 +260,6 @@ macro_rules! impl_Display { /// # Examples /// /// ``` - /// #![feature(int_format_into)] /// use core::fmt::NumBuffer; /// #[doc = concat!("let n = 0", stringify!($Signed), ";")] @@ -273,7 +272,7 @@ macro_rules! impl_Display { #[doc = concat!("let n2 = ", stringify!($Signed::MAX), ";")] #[doc = concat!("assert_eq!(n2.format_into(&mut buf), ", stringify!($Signed::MAX), ".to_string());")] /// ``` - #[unstable(feature = "int_format_into", issue = "138215")] + #[stable(feature = "int_format_into", since = "1.98.0")] pub fn format_into(self, buf: &mut NumBuffer) -> &str { let mut offset; @@ -299,13 +298,12 @@ macro_rules! impl_Display { } impl $Unsigned { - /// Allows users to write an integer (in signed decimal format) into a variable `buf` of - /// type [`NumBuffer`] that is passed by the caller by mutable reference. + /// Allows users to write an integer (in unsigned decimal format) into a variable `buf` + /// of type [`NumBuffer`] that is passed by the caller by mutable reference. /// /// # Examples /// /// ``` - /// #![feature(int_format_into)] /// use core::fmt::NumBuffer; /// #[doc = concat!("let n = 0", stringify!($Unsigned), ";")] @@ -318,7 +316,7 @@ macro_rules! impl_Display { #[doc = concat!("let n2 = ", stringify!($Unsigned::MAX), ";")] #[doc = concat!("assert_eq!(n2.format_into(&mut buf), ", stringify!($Unsigned::MAX), ".to_string());")] /// ``` - #[unstable(feature = "int_format_into", issue = "138215")] + #[stable(feature = "int_format_into", since = "1.98.0")] pub fn format_into(self, buf: &mut NumBuffer) -> &str { let offset; @@ -363,7 +361,7 @@ macro_rules! impl_Display { #[cfg(feature = "optimize_for_size")] fn ${concat($fmt_fn, _small)}(n: $T, is_nonnegative: bool, f: &mut fmt::Formatter<'_>) -> fmt::Result { - const MAX_DEC_N: usize = $T::MAX.ilog(10) as usize + 1; + const MAX_DEC_N: usize = $T::MAX.ilog10() as usize + 1; let mut buf = [MaybeUninit::::uninit(); MAX_DEC_N]; let offset = ${concat($fmt_fn, _in_buf_small)}(n, &mut buf); @@ -594,6 +592,7 @@ impl_Debug! { // Include wasm32 in here since it doesn't reflect the native pointer size, and // often cares strongly about getting a smaller code size. #[cfg(any(target_pointer_width = "64", target_arch = "wasm32"))] +#[doc(auto_cfg = false)] mod imp { use super::*; impl_Display!(i8, u8, i16, u16, i32, u32, i64, u64, isize, usize; as u64 into display_u64); @@ -601,6 +600,7 @@ mod imp { } #[cfg(not(any(target_pointer_width = "64", target_arch = "wasm32")))] +#[doc(auto_cfg = false)] mod imp { use super::*; impl_Display!(i8, u8, i16, u16, i32, u32, isize, usize; as u32 into display_u32); @@ -666,7 +666,9 @@ impl u128 { (mod_1e16, U128_MAX_DEC_N) } else { // Write digits at buf[23..39]. - enc_16lsd::<{ U128_MAX_DEC_N - 16 }>(buf, mod_1e16); + // + // SAFETY: `mod_1e16 < 1e16` (remainder), and `U128_MAX_DEC_N - 16 + 16 == buf.len()`. + unsafe { enc_16lsd::<{ U128_MAX_DEC_N - 16 }>(buf, mod_1e16) }; // Take another 16 decimals. let (quot2, mod2) = div_rem_1e16(quot_1e16); @@ -674,7 +676,10 @@ impl u128 { (mod2, U128_MAX_DEC_N - 16) } else { // Write digits at buf[7..23]. - enc_16lsd::<{ U128_MAX_DEC_N - 32 }>(buf, mod2); + // + // SAFETY: `mod2 < 1e16` (remainder), and `U128_MAX_DEC_N - 32 + 16 <= buf.len()`. + unsafe { enc_16lsd::<{ U128_MAX_DEC_N - 32 }>(buf, mod2) }; + // Quot2 has at most 7 decimals remaining after two 1e16 divisions. (quot2 as u64, U128_MAX_DEC_N - 32) } @@ -690,15 +695,14 @@ impl u128 { unsafe { core::hint::assert_unchecked(offset <= buf.len()) } offset -= 4; - // pull two pairs let quad = remain % 1_00_00; remain /= 1_00_00; - let pair1 = (quad / 100) as usize; - let pair2 = (quad % 100) as usize; - buf[offset + 0].write(DECIMAL_PAIRS[pair1 * 2 + 0]); - buf[offset + 1].write(DECIMAL_PAIRS[pair1 * 2 + 1]); - buf[offset + 2].write(DECIMAL_PAIRS[pair2 * 2 + 0]); - buf[offset + 3].write(DECIMAL_PAIRS[pair2 * 2 + 1]); + + // SAFETY: quad is a remainder modulo 10_000. The offset checks + // above reserve exactly four bytes in buf. + unsafe { + write_quad(buf.get_unchecked_mut(offset..offset + 4), quad); + } } // Format per two digits from the lookup table. @@ -736,13 +740,12 @@ impl u128 { offset } - /// Allows users to write an integer (in signed decimal format) into a variable `buf` of + /// Allows users to write an integer (in unsigned decimal format) into a variable `buf` of /// type [`NumBuffer`] that is passed by the caller by mutable reference. /// /// # Examples /// /// ``` - /// #![feature(int_format_into)] /// use core::fmt::NumBuffer; /// /// let n = 0u128; @@ -757,9 +760,9 @@ impl u128 { /// let mut buf2 = NumBuffer::new(); /// assert_eq!(n2.format_into(&mut buf2), u128::MAX.to_string()); /// ``` - #[unstable(feature = "int_format_into", issue = "138215")] + #[stable(feature = "int_format_into", since = "1.98.0")] pub fn format_into(self, buf: &mut NumBuffer) -> &str { - let diff = buf.capacity() - U128_MAX_DEC_N; + let diff = buf.buf.len() - U128_MAX_DEC_N; // FIXME: Once const generics are better, use `NumberBufferTrait::BUF_SIZE` as generic const // for `fmt_u128_inner`. // @@ -777,7 +780,6 @@ impl i128 { /// # Examples /// /// ``` - /// #![feature(int_format_into)] /// use core::fmt::NumBuffer; /// /// let n = 0i128; @@ -790,9 +792,9 @@ impl i128 { /// let n2 = i128::MAX; /// assert_eq!(n2.format_into(&mut buf), i128::MAX.to_string()); /// ``` - #[unstable(feature = "int_format_into", issue = "138215")] + #[stable(feature = "int_format_into", since = "1.98.0")] pub fn format_into(self, buf: &mut NumBuffer) -> &str { - let diff = buf.capacity() - U128_MAX_DEC_N; + let diff = buf.buf.len() - U128_MAX_DEC_N; // FIXME: Once const generics are better, use `NumberBufferTrait::BUF_SIZE` as generic const // for `fmt_u128_inner`. // @@ -816,23 +818,69 @@ impl i128 { } } +/// Writes `quad` as exactly four digits (for example: `42` becomes `"0042"`). +/// +/// # Safety +/// +/// `quad` must be below 10_000 and `buf` must contain exactly four bytes. +#[inline(always)] +unsafe fn write_quad(buf: &mut [MaybeUninit], quad: u64) { + // SAFETY: These are this function's caller-provided invariants. + unsafe { + core::hint::assert_unchecked(quad < 10_000); + core::hint::assert_unchecked(buf.len() == 4); + } + + let quad = quad as u32; + + // Note: this is equivalent to `quad / 100`, but contains no division instructions. + let high = (quad * const { (1 << 19) / 100 + 1 }) >> 19; + let low = quad - high * 100; + let high = high as usize; + let low = low as usize; + + // SAFETY: `high` and `low` are below 100 because `quad` is below 10_000. + unsafe { core::hint::assert_unchecked(high < 100 && low < 100) } + + buf[0..2].write_copy_of_slice(&DECIMAL_PAIRS[high * 2..high * 2 + 2]); + buf[2..4].write_copy_of_slice(&DECIMAL_PAIRS[low * 2..low * 2 + 2]); +} + /// Encodes the 16 least-significant decimals of n into `buf[OFFSET .. OFFSET + /// 16 ]`. -fn enc_16lsd(buf: &mut [MaybeUninit], n: u64) { - // Consume the least-significant decimals from a working copy. +/// +/// # Safety +/// +/// `n` must be below 1e16, and `buf` must be at least `OFFSET + 16` bytes long. +unsafe fn enc_16lsd(buf: &mut [MaybeUninit], n: u64) { + // SAFETY: Every caller passes a remainder produced by division by 10^16, + // and every used `OFFSET` specialization reserves sixteen bytes in `buf`. + unsafe { + core::hint::assert_unchecked(n < 10_000_000_000_000_000); + core::hint::assert_unchecked(OFFSET + 16 <= buf.len()); + } + + // Peel four digits at a time from right to left (12345678 -> 1234 | 5678). + // Since 10_000 is constant, LLVM replaces each division with multiply or shift. let mut remain = n; - // Format per four digits from the lookup table. - for quad_index in (0..4).rev() { - // pull two pairs + for quad_index in (1..4).rev() { let quad = remain % 1_00_00; remain /= 1_00_00; - let pair1 = (quad / 100) as usize; - let pair2 = (quad % 100) as usize; - buf[quad_index * 4 + OFFSET + 0].write(DECIMAL_PAIRS[pair1 * 2 + 0]); - buf[quad_index * 4 + OFFSET + 1].write(DECIMAL_PAIRS[pair1 * 2 + 1]); - buf[quad_index * 4 + OFFSET + 2].write(DECIMAL_PAIRS[pair2 * 2 + 0]); - buf[quad_index * 4 + OFFSET + 3].write(DECIMAL_PAIRS[pair2 * 2 + 1]); + + // SAFETY: `OFFSET + quad_index * 4` starts one of the four + // non-overlapping four-byte regions proven in bounds above. + unsafe { + write_quad( + buf.get_unchecked_mut(OFFSET + quad_index * 4..OFFSET + (quad_index + 1) * 4), + quad, + ); + } + } + + // SAFETY: OFFSET starts the first four-byte region proven in bounds above. + unsafe { + write_quad(buf.get_unchecked_mut(OFFSET..OFFSET + 4), remain); } } @@ -858,7 +906,7 @@ fn div_rem_1e16(n: u128) -> (u128, u64) { const M_HIGH: u128 = 76624777043294442917917351357515459181; const SH_POST: u8 = 51; - let quot = n.widening_mul(M_HIGH).1 >> SH_POST; + let quot = n.carrying_mul(M_HIGH, 0).1 >> SH_POST; let rem = n - quot * D; (quot, rem as u64) } diff --git a/library/core/src/fmt/num_buffer.rs b/library/core/src/fmt/num_buffer.rs index 474a8d20ef6c5..7d42091b05086 100644 --- a/library/core/src/fmt/num_buffer.rs +++ b/library/core/src/fmt/num_buffer.rs @@ -1,23 +1,29 @@ use crate::mem::MaybeUninit; /// Trait used to describe the maximum number of digits in decimal base of the implemented integer. -#[unstable(feature = "int_format_into", issue = "138215")] +#[unstable(feature = "fmt_internals", issue = "none")] pub trait NumBufferTrait { - /// Maximum number of digits in decimal base of the implemented integer. - const BUF_SIZE: usize; + /// Used for initializing the `NumberBuffer` value. + #[unstable(feature = "fmt_internals", issue = "none")] + const DEFAULT: Self::Buf; + /// The actual underlying type. + #[unstable(feature = "fmt_internals", issue = "none")] + type Buf: AsRef<[MaybeUninit]> + AsMut<[MaybeUninit]>; } macro_rules! impl_NumBufferTrait { ($($signed:ident, $unsigned:ident,)*) => { $( - #[unstable(feature = "int_format_into", issue = "138215")] + #[stable(feature = "int_format_into", since = "1.98.0")] impl NumBufferTrait for $signed { // `+ 2` and not `+ 1` to include the `-` character. - const BUF_SIZE: usize = $signed::MAX.ilog(10) as usize + 2; + const DEFAULT: Self::Buf = [MaybeUninit::::uninit(); $signed::MAX.ilog10() as usize + 2]; + type Buf = [MaybeUninit; $signed::MAX.ilog10() as usize + 2]; } - #[unstable(feature = "int_format_into", issue = "138215")] + #[stable(feature = "int_format_into", since = "1.98.0")] impl NumBufferTrait for $unsigned { - const BUF_SIZE: usize = $unsigned::MAX.ilog(10) as usize + 1; + const DEFAULT: Self::Buf = [MaybeUninit::::uninit(); $unsigned::MAX.ilog10() as usize + 1]; + type Buf = [MaybeUninit; $unsigned::MAX.ilog10() as usize + 1]; } )* } @@ -34,27 +40,40 @@ impl_NumBufferTrait! { /// A buffer wrapper of which the internal size is based on the maximum /// number of digits the associated integer can have. -#[unstable(feature = "int_format_into", issue = "138215")] -#[derive(Debug)] +/// +/// # Examples +/// +/// ``` +/// use core::fmt::NumBuffer; +/// +/// let mut buf = NumBuffer::new(); +/// let n1 = 1972u32; +/// assert_eq!(n1.format_into(&mut buf), "1972"); +/// +/// // Formatting a negative integer includes the sign. +/// let mut buf = NumBuffer::new(); +/// let n2 = -1972i32; +/// assert_eq!(n2.format_into(&mut buf), "-1972"); +/// ``` +#[stable(feature = "int_format_into", since = "1.98.0")] pub struct NumBuffer { - // FIXME: Once const generics feature is working, use `T::BUF_SIZE` instead of 40. - pub(crate) buf: [MaybeUninit; 40], - // FIXME: Remove this field once we can actually use `T`. + pub(crate) buf: T::Buf, phantom: core::marker::PhantomData, } -#[unstable(feature = "int_format_into", issue = "138215")] +#[stable(feature = "int_format_into", since = "1.98.0")] +impl core::fmt::Debug for NumBuffer { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + f.debug_struct("NumBuffer").finish() + } +} + +#[stable(feature = "int_format_into", since = "1.98.0")] impl NumBuffer { /// Initializes internal buffer. - #[unstable(feature = "int_format_into", issue = "138215")] + #[stable(feature = "int_format_into", since = "1.98.0")] + #[rustc_const_stable(feature = "int_format_into", since = "1.98.0")] pub const fn new() -> Self { - // FIXME: Once const generics feature is working, use `T::BUF_SIZE` instead of 40. - NumBuffer { buf: [MaybeUninit::::uninit(); 40], phantom: core::marker::PhantomData } - } - - /// Returns the length of the internal buffer. - #[unstable(feature = "int_format_into", issue = "138215")] - pub const fn capacity(&self) -> usize { - self.buf.len() + NumBuffer { buf: T::DEFAULT, phantom: core::marker::PhantomData } } } diff --git a/library/core/src/future/async_drop.rs b/library/core/src/future/async_drop.rs index c48c3f2ba281e..2f067531f18a4 100644 --- a/library/core/src/future/async_drop.rs +++ b/library/core/src/future/async_drop.rs @@ -41,9 +41,18 @@ pub trait AsyncDrop { } /// Async drop. +/// +/// # Safety +/// +/// The pointer `_to_drop` must be valid for both reads and writes, +/// not only for the duration of this function call, +/// but also until the returned future has completed. +/// See [ptr::drop_in_place] for additional safety concerns. +/// +/// [ptr::drop_in_place]: crate::ptr::drop_in_place() #[unstable(feature = "async_drop", issue = "126482")] #[lang = "async_drop_in_place"] -pub async unsafe fn async_drop_in_place(_to_drop: *mut T) { +pub async unsafe fn async_drop_in_place(_to_drop: &mut T) { // Code here does not matter - this is replaced by the // real implementation by the compiler. } diff --git a/library/core/src/hash/mod.rs b/library/core/src/hash/mod.rs index eea6118571204..c7c8d57e1010d 100644 --- a/library/core/src/hash/mod.rs +++ b/library/core/src/hash/mod.rs @@ -784,7 +784,7 @@ impl Clone for BuildHasherDefault { #[stable(since = "1.7.0", feature = "build_hasher")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for BuildHasherDefault { +const impl Default for BuildHasherDefault { fn default() -> BuildHasherDefault { Self::new() } diff --git a/library/core/src/hash/sip.rs b/library/core/src/hash/sip.rs index eed1044bd2a92..bc74bd0e085ff 100644 --- a/library/core/src/hash/sip.rs +++ b/library/core/src/hash/sip.rs @@ -340,7 +340,7 @@ impl Clone for Hasher { } #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for Hasher { +const impl Default for Hasher { /// Creates a `Hasher` with the two initial keys set to 0. #[inline] fn default() -> Hasher { diff --git a/library/core/src/hint.rs b/library/core/src/hint.rs index fe59166363b9c..8d7c2a16899e1 100644 --- a/library/core/src/hint.rs +++ b/library/core/src/hint.rs @@ -520,7 +520,7 @@ pub const fn black_box(dummy: T) -> T { /// macro_rules! make_error { /// ($($args:expr),*) => { /// core::hint::must_use({ -/// let error = $crate::make_error(core::format_args!($($args),*)); +/// let error = make_error(core::format_args!($($args),*)); /// error /// }) /// }; @@ -730,7 +730,6 @@ pub const fn unlikely(b: bool) -> bool { /// # Examples /// /// ``` -/// #![feature(cold_path)] /// use core::hint::cold_path; /// /// fn foo(x: &[i32]) { @@ -756,7 +755,6 @@ pub const fn unlikely(b: bool) -> bool { /// than the branch: /// /// ``` -/// #![feature(cold_path)] /// use core::hint::cold_path; /// /// #[inline(always)] @@ -783,8 +781,12 @@ pub const fn unlikely(b: bool) -> bool { /// } /// } /// ``` -#[unstable(feature = "cold_path", issue = "136873")] +#[stable(feature = "cold_path", since = "1.95.0")] +#[rustc_const_stable(feature = "cold_path", since = "1.95.0")] #[inline(always)] +// Even if for some reason the cold_path intrinsic is not visible to codegen, the coldness will +// ensure that branches this is in are still known to be cold. +#[cold] pub const fn cold_path() { crate::intrinsics::cold_path() } diff --git a/library/core/src/index.rs b/library/core/src/index.rs index 3baefdf10cecb..70372163c6e17 100644 --- a/library/core/src/index.rs +++ b/library/core/src/index.rs @@ -315,7 +315,7 @@ unsafe impl SliceIndex<[T]> for Clamp> { } #[unstable(feature = "sliceindex_wrappers", issue = "146179")] -unsafe impl SliceIndex<[T]> for Clamp> { +unsafe impl SliceIndex<[T]> for Clamp> { type Output = [T]; fn get(self, slice: &[T]) -> Option<&Self::Output> { @@ -408,7 +408,7 @@ unsafe impl SliceIndex<[T]> for Clamp> { } #[unstable(feature = "sliceindex_wrappers", issue = "146179")] -unsafe impl SliceIndex<[T]> for Clamp { +unsafe impl SliceIndex<[T]> for Clamp { type Output = [T]; fn get(self, slice: &[T]) -> Option<&Self::Output> { diff --git a/library/core/src/internal_macros.rs b/library/core/src/internal_macros.rs index f90818c7969c9..0d0ff23fe2946 100644 --- a/library/core/src/internal_macros.rs +++ b/library/core/src/internal_macros.rs @@ -3,7 +3,7 @@ macro_rules! forward_ref_unop { (impl $imp:ident, $method:ident for $t:ty, $(#[$attr:meta])+) => { $(#[$attr])+ - impl const $imp for &$t { + const impl $imp for &$t { type Output = <$t as $imp>::Output; #[inline] @@ -19,7 +19,7 @@ macro_rules! forward_ref_unop { macro_rules! forward_ref_binop { (impl $imp:ident, $method:ident for $t:ty, $u:ty, $(#[$attr:meta])+) => { $(#[$attr])+ - impl const $imp<$u> for &$t { + const impl $imp<$u> for &$t { type Output = <$t as $imp<$u>>::Output; #[inline] @@ -30,7 +30,7 @@ macro_rules! forward_ref_binop { } $(#[$attr])+ - impl const $imp<&$u> for $t { + const impl $imp<&$u> for $t { type Output = <$t as $imp<$u>>::Output; #[inline] @@ -41,7 +41,7 @@ macro_rules! forward_ref_binop { } $(#[$attr])+ - impl const $imp<&$u> for &$t { + const impl $imp<&$u> for &$t { type Output = <$t as $imp<$u>>::Output; #[inline] @@ -58,7 +58,7 @@ macro_rules! forward_ref_binop { macro_rules! forward_ref_op_assign { (impl $imp:ident, $method:ident for $t:ty, $u:ty, $(#[$attr:meta])+) => { $(#[$attr])+ - impl const $imp<&$u> for $t { + const impl $imp<&$u> for $t { #[inline] #[track_caller] fn $method(&mut self, other: &$u) { diff --git a/library/core/src/intrinsics/bounds.rs b/library/core/src/intrinsics/bounds.rs index 353908598d40b..377465aeb10fd 100644 --- a/library/core/src/intrinsics/bounds.rs +++ b/library/core/src/intrinsics/bounds.rs @@ -39,3 +39,73 @@ impl ChangePointee for *mut T { impl ChangePointee for *const T { type Output = *const U; } + +/// Built-in float types (f16, f32, f64 and f128). +/// +/// # Safety +/// Must actually *be* such a type. +#[rustc_const_unstable(feature = "core_intrinsics", issue = "none")] +pub const unsafe trait FloatPrimitive: Sized + Copy { + type UInt: const core::ops::BitOr + + const core::ops::BitAnd + + const core::ops::Not; + const SIGN_MASK: Self::UInt; + fn to_bits(self) -> Self::UInt; + fn from_bits(bits: Self::UInt) -> Self; +} + +#[rustc_const_unstable(feature = "core_intrinsics", issue = "none")] +const unsafe impl FloatPrimitive for f16 { + type UInt = u16; + const SIGN_MASK: Self::UInt = f16::SIGN_MASK; + #[inline] + fn to_bits(self) -> Self::UInt { + f16::to_bits(self) + } + #[inline] + fn from_bits(bits: Self::UInt) -> Self { + f16::from_bits(bits) + } +} + +#[rustc_const_unstable(feature = "core_intrinsics", issue = "none")] +const unsafe impl FloatPrimitive for f32 { + type UInt = u32; + const SIGN_MASK: Self::UInt = f32::SIGN_MASK; + #[inline] + fn to_bits(self) -> Self::UInt { + f32::to_bits(self) + } + #[inline] + fn from_bits(bits: Self::UInt) -> Self { + f32::from_bits(bits) + } +} + +#[rustc_const_unstable(feature = "core_intrinsics", issue = "none")] +const unsafe impl FloatPrimitive for f64 { + type UInt = u64; + const SIGN_MASK: Self::UInt = f64::SIGN_MASK; + #[inline] + fn to_bits(self) -> Self::UInt { + f64::to_bits(self) + } + #[inline] + fn from_bits(bits: Self::UInt) -> Self { + f64::from_bits(bits) + } +} + +#[rustc_const_unstable(feature = "core_intrinsics", issue = "none")] +const unsafe impl FloatPrimitive for f128 { + type UInt = u128; + const SIGN_MASK: Self::UInt = f128::SIGN_MASK; + #[inline] + fn to_bits(self) -> Self::UInt { + f128::to_bits(self) + } + #[inline] + fn from_bits(bits: Self::UInt) -> Self { + f128::from_bits(bits) + } +} diff --git a/library/core/src/intrinsics/fallback.rs b/library/core/src/intrinsics/fallback.rs index 7b3c49cf3a56f..544e42b3c8c63 100644 --- a/library/core/src/intrinsics/fallback.rs +++ b/library/core/src/intrinsics/fallback.rs @@ -26,7 +26,7 @@ pub const trait CarryingMulAdd: Copy + 'static { macro_rules! impl_carrying_mul_add_by_widening { ($($t:ident $u:ident $w:ident,)+) => {$( #[rustc_const_unstable(feature = "core_intrinsics_fallbacks", issue = "none")] - impl const CarryingMulAdd for $t { + const impl CarryingMulAdd for $t { type Unsigned = $u; #[inline] fn carrying_mul_add(self, a: Self, b: Self, c: Self) -> ($u, $t) { @@ -85,7 +85,7 @@ const fn wide_mul_u128(a: u128, b: u128) -> (u128, u128) { } #[rustc_const_unstable(feature = "core_intrinsics_fallbacks", issue = "none")] -impl const CarryingMulAdd for u128 { +const impl CarryingMulAdd for u128 { type Unsigned = u128; #[inline] fn carrying_mul_add(self, b: u128, c: u128, d: u128) -> (u128, u128) { @@ -99,7 +99,7 @@ impl const CarryingMulAdd for u128 { } #[rustc_const_unstable(feature = "core_intrinsics_fallbacks", issue = "none")] -impl const CarryingMulAdd for i128 { +const impl CarryingMulAdd for i128 { type Unsigned = u128; #[inline] fn carrying_mul_add(self, b: i128, c: i128, d: i128) -> (u128, i128) { @@ -132,7 +132,7 @@ macro_rules! zero { macro_rules! impl_disjoint_bitor { ($($t:ident,)+) => {$( #[rustc_const_unstable(feature = "core_intrinsics_fallbacks", issue = "none")] - impl const DisjointBitOr for $t { + const impl DisjointBitOr for $t { #[cfg_attr(miri, track_caller)] #[inline] #[requires((self & other) == zero!($t))] @@ -157,20 +157,20 @@ impl_disjoint_bitor! { pub const trait FunnelShift: Copy + 'static { /// See [`super::unchecked_funnel_shl`]; we just need the trait indirection to handle /// different types since calling intrinsics with generics doesn't work. - unsafe fn unchecked_funnel_shl(self, rhs: Self, shift: u32) -> Self; + unsafe fn unchecked_funnel_shl(self, right: Self, shift: u32) -> Self; /// See [`super::unchecked_funnel_shr`]; we just need the trait indirection to handle /// different types since calling intrinsics with generics doesn't work. - unsafe fn unchecked_funnel_shr(self, rhs: Self, shift: u32) -> Self; + unsafe fn unchecked_funnel_shr(self, right: Self, shift: u32) -> Self; } macro_rules! impl_funnel_shifts { ($($type:ident),*) => {$( #[rustc_const_unstable(feature = "core_intrinsics_fallbacks", issue = "none")] - impl const FunnelShift for $type { + const impl FunnelShift for $type { #[cfg_attr(miri, track_caller)] #[inline] - unsafe fn unchecked_funnel_shl(self, rhs: Self, shift: u32) -> Self { + unsafe fn unchecked_funnel_shl(self, right: Self, shift: u32) -> Self { // This implementation is also used by Miri so we have to check the precondition. // SAFETY: this is guaranteed by the caller unsafe { super::assume(shift < $type::BITS) }; @@ -187,7 +187,7 @@ macro_rules! impl_funnel_shifts { unsafe { super::disjoint_bitor( super::unchecked_shl(self, shift), - super::unchecked_shr(rhs, $type::BITS - shift), + super::unchecked_shr(right, $type::BITS - shift), ) } } @@ -195,12 +195,12 @@ macro_rules! impl_funnel_shifts { #[cfg_attr(miri, track_caller)] #[inline] - unsafe fn unchecked_funnel_shr(self, rhs: Self, shift: u32) -> Self { + unsafe fn unchecked_funnel_shr(self, right: Self, shift: u32) -> Self { // This implementation is also used by Miri so we have to check the precondition. // SAFETY: this is guaranteed by the caller unsafe { super::assume(shift < $type::BITS) }; if shift == 0 { - rhs + right } else { // SAFETY: // - `shift < T::BITS`, which satisfies `unchecked_shr` @@ -212,7 +212,7 @@ macro_rules! impl_funnel_shifts { unsafe { super::disjoint_bitor( super::unchecked_shl(self, $type::BITS - shift), - super::unchecked_shr(rhs, shift), + super::unchecked_shr(right, shift), ) } } @@ -224,3 +224,38 @@ macro_rules! impl_funnel_shifts { impl_funnel_shifts! { u8, u16, u32, u64, u128, usize } + +#[rustc_const_unstable(feature = "core_intrinsics_fallbacks", issue = "none")] +pub const trait CarrylessMul: Copy + 'static { + /// See [`super::carryless_mul`]; we just need the trait indirection to handle + /// different types since calling intrinsics with generics doesn't work. + fn carryless_mul(self, rhs: Self) -> Self; +} + +macro_rules! impl_carryless_mul{ + ($($type:ident),*) => {$( + #[rustc_const_unstable(feature = "core_intrinsics_fallbacks", issue = "none")] + const impl CarrylessMul for $type { + #[inline] + fn carryless_mul(self, rhs: Self) -> Self { + let mut result = 0; + let mut i = 0; + + while i < $type::BITS { + // If the i-th bit in rhs is set. + if (rhs >> i) & 1 != 0 { + // Then xor the result with `self` shifted to the left by i positions. + result ^= self << i; + } + i += 1; + } + + result + } + } + )*}; +} + +impl_carryless_mul! { + u8, u16, u32, u64, u128, usize +} diff --git a/library/core/src/intrinsics/gpu.rs b/library/core/src/intrinsics/gpu.rs index 9e7624841d0c6..8ea894b3955d4 100644 --- a/library/core/src/intrinsics/gpu.rs +++ b/library/core/src/intrinsics/gpu.rs @@ -5,6 +5,51 @@ #![unstable(feature = "gpu_intrinsics", issue = "none")] +/// Returns the pointer to workgroup memory allocated at launch-time on GPUs. +/// +/// Workgroup memory is a memory region that is shared between all threads in +/// the same workgroup. It is faster to access than other memory but pointers do not +/// work outside the workgroup where they were obtained. +/// Workgroup memory can be allocated statically or after compilation, when +/// launching a gpu-kernel. `gpu_launch_sized_workgroup_mem` returns the pointer to +/// the memory that is allocated at launch-time. +/// The size of this memory can differ between launches of a gpu-kernel, depending on +/// what is specified at launch-time. +/// However, the alignment is fixed by the kernel itself, at compile-time. +/// +/// The returned pointer is the start of the workgroup memory region that is +/// allocated at launch-time. +/// All calls to `gpu_launch_sized_workgroup_mem` in a workgroup, independent of the +/// generic type, return the same address, so alias the same memory. +/// The returned pointer is aligned by at least the alignment of `T`. +/// +/// If `gpu_launch_sized_workgroup_mem` is invoked multiple times with different +/// types that have different alignment, then you may only rely on the resulting +/// pointer having the alignment of `T` after a call to `gpu_launch_sized_workgroup_mem::` +/// has occurred in the current program execution. +/// +/// # Safety +/// +/// The pointer is safe to dereference from the start (the returned pointer) up to the +/// size of workgroup memory that was specified when launching the current gpu-kernel. +/// This allocated size is not related in any way to `T`. +/// +/// The user must take care of synchronizing access to workgroup memory between +/// threads in a workgroup. The usual data race requirements apply. +/// +/// # Other APIs +/// +/// CUDA and HIP call this dynamic shared memory, shared between threads in a block. +/// OpenCL and SYCL call this local memory, shared between threads in a work-group. +/// GLSL calls this shared memory, shared between invocations in a work group. +/// DirectX calls this groupshared memory, shared between threads in a thread-group. +#[must_use = "returns a pointer that does nothing unless used"] +#[rustc_intrinsic] +#[rustc_nounwind] +#[unstable(feature = "gpu_launch_sized_workgroup_mem", issue = "135513")] +#[cfg(any(doc, target_arch = "amdgpu", target_arch = "nvptx64"))] +pub fn gpu_launch_sized_workgroup_mem() -> *mut T; + /// Returns a pointer to the HSA kernel dispatch packet. /// /// A `gpu-kernel` on amdgpu is always launched through a kernel dispatch packet. @@ -18,6 +63,6 @@ /// [hsa.h]: https://github.com/ROCm/rocm-systems/blob/rocm-7.1.0/projects/rocr-runtime/runtime/hsa-runtime/inc/hsa.h#L2959 #[rustc_nounwind] #[rustc_intrinsic] -#[cfg(target_arch = "amdgpu")] +#[cfg(any(doc, target_arch = "amdgpu"))] #[must_use = "returns a pointer that does nothing unless used"] pub fn amdgpu_dispatch_ptr() -> *const (); diff --git a/library/core/src/intrinsics/mir.rs b/library/core/src/intrinsics/mir.rs index 939298268c934..dce7bf681a7af 100644 --- a/library/core/src/intrinsics/mir.rs +++ b/library/core/src/intrinsics/mir.rs @@ -4,7 +4,7 @@ //! this feature, turn back. This is *exceptionally* unstable. There is no attempt at all to make //! anything work besides those things which the rustc test suite happened to need. If you make a //! typo you'll probably ICE. Really, this is not the solution to your problems. Consider instead -//! supporting the [stable MIR project group](https://github.com/rust-lang/project-stable-mir). +//! supporting the [rustc public project group](https://github.com/rust-lang/rustc_public). //! //! The documentation for this module describes how to use this feature. If you are interested in //! hacking on the implementation, most of that documentation lives at @@ -62,7 +62,9 @@ //! //! # Examples //! -//! ```rust +#![cfg_attr(panic = "unwind", doc = "```rust")] +// This test can't support panic=abort because it generates an UnwindContinue MIR terminator. +#![cfg_attr(panic = "abort", doc = "```ignore")] //! #![feature(core_intrinsics, custom_mir)] //! #![allow(internal_features)] //! #![allow(unused_assignments)] @@ -227,7 +229,7 @@ //! //! #### Statements //! - Assign statements work via normal Rust assignment. -//! - [`Retag`], [`StorageLive`], [`StorageDead`] statements have an associated function. +//! - [`StorageLive`], [`StorageDead`] statements have an associated function. //! //! #### Rvalues //! @@ -405,7 +407,6 @@ define!( "mir_ptr_metadata", fn PtrMetadata(place: *const P) ->

(&mut self, predicate: P) -> Option where Self: Sized, diff --git a/library/core/src/iter/traits/iterator.rs b/library/core/src/iter/traits/iterator.rs index 13202e6cb5888..1a3a8f59f43c0 100644 --- a/library/core/src/iter/traits/iterator.rs +++ b/library/core/src/iter/traits/iterator.rs @@ -8,9 +8,10 @@ use super::super::{ }; use super::TrustedLen; use crate::array; -use crate::cmp::{self, Ordering}; +use crate::cmp::{self, KeyAndValue, Ordering}; #[cfg(kani)] use crate::kani; +use crate::marker::Destruct; use crate::num::NonZero; use crate::ops::{ChangeOutputType, ControlFlow, FromResidual, Residual, Try}; @@ -112,7 +113,6 @@ pub const trait Iterator { /// ``` #[inline] #[unstable(feature = "iter_next_chunk", issue = "98326")] - #[rustc_non_const_trait_method] fn next_chunk( &mut self, ) -> Result<[Self::Item; N], array::IntoIter> @@ -225,15 +225,15 @@ pub const trait Iterator { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn count(self) -> usize where - Self: Sized, + Self: Sized + [const] Destruct, + Self::Item: [const] Destruct, { self.fold( 0, #[rustc_inherit_overflow_checks] - |count, _| count + 1, + const |accum, _elem| accum + 1, ) } @@ -258,13 +258,17 @@ pub const trait Iterator { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn last(self) -> Option where - Self: Sized, + Self: Sized + [const] Destruct, + Self::Item: [const] Destruct, { #[inline] - fn some(_: Option, x: T) -> Option { + #[rustc_const_unstable(feature = "const_destruct", issue = "133214")] + const fn some(_: Option, x: T) -> Option + where + T: [const] Destruct, + { Some(x) } @@ -507,11 +511,10 @@ pub const trait Iterator { /// [`OsStr`]: ../../std/ffi/struct.OsStr.html #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn chain(self, other: U) -> Chain where Self: Sized, - U: IntoIterator, + U: [const] IntoIterator, { Chain::new(self, other.into_iter()) } @@ -635,8 +638,28 @@ pub const trait Iterator { Zip::new(self, other.into_iter()) } - /// Creates a new iterator which places a copy of `separator` between adjacent - /// items of the original iterator. + /// Creates a new iterator which places a copy of `separator` between items + /// of the original iterator. + /// + /// Specifically on fused iterators, it is guaranteed that the new iterator + /// places a copy of `separator` between *adjacent* `Some(_)` items. For non-fused iterators, + /// it is guaranteed that [`intersperse`] will create a new iterator that places a copy + /// of `separator` between `Some(_)` items, particularly just right before the subsequent + /// `Some(_)` item. + /// + /// For example, consider the following non-fused iterator: + /// + /// ```text + /// Some(1) -> Some(2) -> None -> Some(3) -> Some(4) -> ... + /// ``` + /// + /// If this non-fused iterator were to be interspersed with `0`, + /// then the interspersed iterator will produce: + /// + /// ```text + /// Some(1) -> Some(0) -> Some(2) -> None -> Some(0) -> Some(3) -> Some(0) -> + /// Some(4) -> ... + /// ``` /// /// In case `separator` does not implement [`Clone`] or needs to be /// computed every time, use [`intersperse_with`]. @@ -667,10 +690,10 @@ pub const trait Iterator { /// ``` /// /// [`Clone`]: crate::clone::Clone + /// [`intersperse`]: Iterator::intersperse /// [`intersperse_with`]: Iterator::intersperse_with #[inline] #[unstable(feature = "iter_intersperse", issue = "79524")] - #[rustc_non_const_trait_method] fn intersperse(self, separator: Self::Item) -> Intersperse where Self: Sized, @@ -680,12 +703,32 @@ pub const trait Iterator { } /// Creates a new iterator which places an item generated by `separator` - /// between adjacent items of the original iterator. + /// between items of the original iterator. + /// + /// Specifically on fused iterators, it is guaranteed that the new iterator + /// places an item generated by `separator` between adjacent `Some(_)` items. + /// For non-fused iterators, it is guaranteed that [`intersperse_with`] will + /// create a new iterator that places an item generated by `separator` between `Some(_)` + /// items, particularly just right before the subsequent `Some(_)` item. /// - /// The closure will be called exactly once each time an item is placed - /// between two adjacent items from the underlying iterator; specifically, - /// the closure is not called if the underlying iterator yields less than - /// two items and after the last item is yielded. + /// For example, consider the following non-fused iterator: + /// + /// ```text + /// Some(1) -> Some(2) -> None -> Some(3) -> Some(4) -> ... + /// ``` + /// + /// If this non-fused iterator were to be interspersed with a `separator` closure + /// that returns `0` repeatedly, the interspersed iterator will produce: + /// + /// ```text + /// Some(1) -> Some(0) -> Some(2) -> None -> Some(0) -> Some(3) -> Some(0) -> + /// Some(4) -> ... + /// ``` + /// + /// The `separator` closure will be called exactly once each time an item + /// is placed between two adjacent items from the underlying iterator; + /// specifically, the closure is not called if the underlying iterator yields + /// less than two items and after the last item is yielded. /// /// If the iterator's item implements [`Clone`], it may be easier to use /// [`intersperse`]. @@ -727,9 +770,9 @@ pub const trait Iterator { /// ``` /// [`Clone`]: crate::clone::Clone /// [`intersperse`]: Iterator::intersperse + /// [`intersperse_with`]: Iterator::intersperse_with #[inline] #[unstable(feature = "iter_intersperse", issue = "79524")] - #[rustc_non_const_trait_method] fn intersperse_with(self, separator: G) -> IntersperseWith where Self: Sized, @@ -789,7 +832,6 @@ pub const trait Iterator { #[rustc_diagnostic_item = "IteratorMap"] #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn map(self, f: F) -> Map where Self: Sized, @@ -911,7 +953,6 @@ pub const trait Iterator { #[inline] #[stable(feature = "rust1", since = "1.0.0")] #[rustc_diagnostic_item = "iter_filter"] - #[rustc_non_const_trait_method] fn filter

(self, predicate: P) -> Filter where Self: Sized, @@ -957,7 +998,6 @@ pub const trait Iterator { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn filter_map(self, f: F) -> FilterMap where Self: Sized, @@ -1005,7 +1045,6 @@ pub const trait Iterator { #[inline] #[stable(feature = "rust1", since = "1.0.0")] #[rustc_diagnostic_item = "enumerate_method"] - #[rustc_non_const_trait_method] fn enumerate(self) -> Enumerate where Self: Sized, @@ -1077,7 +1116,6 @@ pub const trait Iterator { /// [`next`]: Iterator::next #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn peekable(self) -> Peekable where Self: Sized, @@ -1143,7 +1181,6 @@ pub const trait Iterator { #[inline] #[doc(alias = "drop_while")] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn skip_while

(self, predicate: P) -> SkipWhile where Self: Sized, @@ -1222,7 +1259,6 @@ pub const trait Iterator { /// the iteration should stop, but wasn't placed back into the iterator. #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn take_while

(self, predicate: P) -> TakeWhile where Self: Sized, @@ -1311,7 +1347,6 @@ pub const trait Iterator { /// [`fuse`]: Iterator::fuse #[inline] #[stable(feature = "iter_map_while", since = "1.57.0")] - #[rustc_non_const_trait_method] fn map_while(self, predicate: P) -> MapWhile where Self: Sized, @@ -1341,7 +1376,6 @@ pub const trait Iterator { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn skip(self, n: usize) -> Skip where Self: Sized, @@ -1414,7 +1448,6 @@ pub const trait Iterator { #[doc(alias = "limit")] #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn take(self, n: usize) -> Take where Self: Sized, @@ -1462,7 +1495,6 @@ pub const trait Iterator { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn scan(self, initial_state: St, f: F) -> Scan where Self: Sized, @@ -1586,7 +1618,6 @@ pub const trait Iterator { /// [`flat_map()`]: Iterator::flat_map #[inline] #[stable(feature = "iterator_flatten", since = "1.29.0")] - #[rustc_non_const_trait_method] fn flatten(self) -> Flatten where Self: Sized, @@ -1619,24 +1650,12 @@ pub const trait Iterator { /// items yielded by `self`). If 𝑘 is less than `N`, this method yields an /// empty iterator. /// - /// The returned iterator implements [`FusedIterator`], because once `self` - /// returns `None`, even if it returns a `Some(T)` again in the next iterations, - /// we cannot put it into a contiguous array buffer, and thus the returned iterator - /// should be fused. - /// /// [`slice::windows()`]: slice::windows /// [`FusedIterator`]: crate::iter::FusedIterator /// /// # Panics /// - /// Panics if `N` is zero. This check will most probably get changed to a - /// compile time error before this method gets stabilized. - /// - /// ```should_panic - /// #![feature(iter_map_windows)] - /// - /// let iter = std::iter::repeat(0).map_windows(|&[]| ()); - /// ``` + /// Panics if `N` is zero. /// /// # Examples /// @@ -1684,7 +1703,7 @@ pub const trait Iterator { /// assert_eq!(it.next(), None); /// ``` /// - /// For non-fused iterators, they are fused after `map_windows`. + /// For non-fused iterators, the window is reset after `None` is yielded. /// /// ``` /// #![feature(iter_map_windows)] @@ -1701,11 +1720,11 @@ pub const trait Iterator { /// let val = self.state; /// self.state = self.state + 1; /// - /// // yields `0..5` first, then only even numbers since `6..`. - /// if val < 5 || val % 2 == 0 { - /// Some(val) - /// } else { + /// // Skip every 5th number + /// if (val + 1) % 5 == 0 { /// None + /// } else { + /// Some(val) /// } /// } /// } @@ -1713,39 +1732,45 @@ pub const trait Iterator { /// /// let mut iter = NonFusedIterator::default(); /// - /// // yields 0..5 first. /// assert_eq!(iter.next(), Some(0)); /// assert_eq!(iter.next(), Some(1)); /// assert_eq!(iter.next(), Some(2)); /// assert_eq!(iter.next(), Some(3)); - /// assert_eq!(iter.next(), Some(4)); - /// // then we can see our iterator going back and forth /// assert_eq!(iter.next(), None); + /// assert_eq!(iter.next(), Some(5)); /// assert_eq!(iter.next(), Some(6)); - /// assert_eq!(iter.next(), None); + /// assert_eq!(iter.next(), Some(7)); /// assert_eq!(iter.next(), Some(8)); /// assert_eq!(iter.next(), None); + /// assert_eq!(iter.next(), Some(10)); + /// assert_eq!(iter.next(), Some(11)); /// - /// // however, with `.map_windows()`, it is fused. /// let mut iter = NonFusedIterator::default() /// .map_windows(|arr: &[_; 2]| *arr); /// /// assert_eq!(iter.next(), Some([0, 1])); /// assert_eq!(iter.next(), Some([1, 2])); /// assert_eq!(iter.next(), Some([2, 3])); - /// assert_eq!(iter.next(), Some([3, 4])); /// assert_eq!(iter.next(), None); /// - /// // it will always return `None` after the first time. - /// assert_eq!(iter.next(), None); + /// assert_eq!(iter.next(), Some([5, 6])); + /// assert_eq!(iter.next(), Some([6, 7])); + /// assert_eq!(iter.next(), Some([7, 8])); /// assert_eq!(iter.next(), None); + /// + /// assert_eq!(iter.next(), Some([10, 11])); + /// assert_eq!(iter.next(), Some([11, 12])); + /// assert_eq!(iter.next(), Some([12, 13])); /// assert_eq!(iter.next(), None); /// ``` #[inline] #[unstable(feature = "iter_map_windows", issue = "87155")] #[rustc_non_const_trait_method] #[requires(N > 0)] - fn map_windows(self, f: F) -> MapWindows + fn map_windows( + self, + f: F, + ) -> MapWindows where Self: Sized, F: FnMut(&[Self::Item; N]) -> R, @@ -1807,7 +1832,6 @@ pub const trait Iterator { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn fuse(self) -> Fuse where Self: Sized, @@ -1892,7 +1916,6 @@ pub const trait Iterator { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn inspect(self, f: F) -> Inspect where Self: Sized, @@ -1913,7 +1936,7 @@ pub const trait Iterator { /// without giving up ownership of the original iterator, /// so you can use the original iterator afterwards. /// - /// Uses [`impl Iterator for &mut I { type Item = I::Item; ...}`](https://doc.rust-lang.org/nightly/std/iter/trait.Iterator.html#impl-Iterator-for-%26mut+I). + /// Uses [`impl Iterator for &mut I { type Item = I::Item; ...}`](Iterator#impl-Iterator-for-%26mut+I). /// /// # Examples /// @@ -2462,12 +2485,11 @@ pub const trait Iterator { /// ``` #[inline] #[stable(feature = "iterator_try_fold", since = "1.27.0")] - #[rustc_non_const_trait_method] fn try_fold(&mut self, init: B, mut f: F) -> R where Self: Sized, - F: FnMut(B, Self::Item) -> R, - R: Try, + F: [const] FnMut(B, Self::Item) -> R + [const] Destruct, + R: [const] Try, { let mut accum = init; while let Some(x) = self.next() { @@ -2641,11 +2663,10 @@ pub const trait Iterator { #[doc(alias = "inject", alias = "foldl")] #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn fold(mut self, init: B, mut f: F) -> B where - Self: Sized, - F: FnMut(B, Self::Item) -> B, + Self: Sized + [const] Destruct, + F: [const] FnMut(B, Self::Item) -> B + [const] Destruct, { let mut accum = init; while let Some(x) = self.next() { @@ -2679,11 +2700,10 @@ pub const trait Iterator { /// ``` #[inline] #[stable(feature = "iterator_fold_self", since = "1.51.0")] - #[rustc_non_const_trait_method] fn reduce(mut self, f: F) -> Option where - Self: Sized, - F: FnMut(Self::Item, Self::Item) -> Self::Item, + Self: Sized + [const] Destruct, + F: [const] FnMut(Self::Item, Self::Item) -> Self::Item + [const] Destruct, { let first = self.next()?; Some(self.fold(first, f)) @@ -2751,14 +2771,13 @@ pub const trait Iterator { /// ``` #[inline] #[unstable(feature = "iterator_try_reduce", issue = "87053")] - #[rustc_non_const_trait_method] fn try_reduce( &mut self, - f: impl FnMut(Self::Item, Self::Item) -> R, + f: impl [const] FnMut(Self::Item, Self::Item) -> R + [const] Destruct, ) -> ChangeOutputType> where Self: Sized, - R: Try>>, + R: [const] Try>>, { let first = match self.next() { Some(i) => i, @@ -3235,7 +3254,7 @@ pub const trait Iterator { Self: Sized, Self::Item: Ord, { - self.max_by(Ord::cmp) + self.reduce(Ord::max) } /// Returns the minimum element of an iterator. @@ -3272,7 +3291,7 @@ pub const trait Iterator { Self: Sized, Self::Item: Ord, { - self.min_by(Ord::cmp) + self.reduce(Ord::min) } /// Returns the element that gives the maximum value from the @@ -3295,18 +3314,17 @@ pub const trait Iterator { Self: Sized, F: FnMut(&Self::Item) -> B, { - #[inline] - fn key(mut f: impl FnMut(&T) -> B) -> impl FnMut(T) -> (B, T) { - move |x| (f(&x), x) - } + // If we implemented this via `max_by` that would force it to use `B::cmp`. + // By using `max` over `KeyAndValue`, it instead ends up calling `B::lt` + // (via `KeyAndValue::max`), which is often overridden more efficiently. #[inline] - fn compare((x_p, _): &(B, T), (y_p, _): &(B, T)) -> Ordering { - x_p.cmp(y_p) + fn key(mut f: impl FnMut(&T) -> B) -> impl FnMut(T) -> KeyAndValue { + move |value| KeyAndValue { key: f(&value), value } } - let (_, x) = self.map(key(f)).max_by(compare)?; - Some(x) + let KeyAndValue { value, .. } = self.map(key(f)).max()?; + Some(value) } /// Returns the element that gives the maximum value with respect to the @@ -3357,18 +3375,17 @@ pub const trait Iterator { Self: Sized, F: FnMut(&Self::Item) -> B, { - #[inline] - fn key(mut f: impl FnMut(&T) -> B) -> impl FnMut(T) -> (B, T) { - move |x| (f(&x), x) - } + // If we implemented this via `min_by` that would force it to use `B::cmp`. + // By using `min` over `KeyAndValue`, it instead ends up calling `B::lt` + // (via `KeyAndValue::min`), which is often overridden more efficiently. #[inline] - fn compare((x_p, _): &(B, T), (y_p, _): &(B, T)) -> Ordering { - x_p.cmp(y_p) + fn key(mut f: impl FnMut(&T) -> B) -> impl FnMut(T) -> KeyAndValue { + move |value| KeyAndValue { key: f(&value), value } } - let (_, x) = self.map(key(f)).min_by(compare)?; - Some(x) + let KeyAndValue { value, .. } = self.map(key(f)).min()?; + Some(value) } /// Returns the element that gives the minimum value with respect to the @@ -3423,7 +3440,6 @@ pub const trait Iterator { #[inline] #[doc(alias = "reverse")] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn rev(self) -> Rev where Self: Sized + DoubleEndedIterator, @@ -3492,7 +3508,6 @@ pub const trait Iterator { /// ``` #[stable(feature = "iter_copied", since = "1.36.0")] #[rustc_diagnostic_item = "iter_copied"] - #[rustc_non_const_trait_method] fn copied<'a, T>(self) -> Copied where T: Copy + 'a, @@ -3541,7 +3556,6 @@ pub const trait Iterator { /// ``` #[stable(feature = "rust1", since = "1.0.0")] #[rustc_diagnostic_item = "iter_cloned"] - #[rustc_non_const_trait_method] fn cloned<'a, T>(self) -> Cloned where T: Clone + 'a, @@ -3573,10 +3587,9 @@ pub const trait Iterator { /// ``` #[stable(feature = "rust1", since = "1.0.0")] #[inline] - #[rustc_non_const_trait_method] fn cycle(self) -> Cycle where - Self: Sized + Clone, + Self: Sized + [const] Clone, { Cycle::new(self) } @@ -3617,8 +3630,7 @@ pub const trait Iterator { /// ``` #[track_caller] #[unstable(feature = "iter_array_chunks", issue = "100450")] - #[rustc_non_const_trait_method] - fn array_chunks(self) -> ArrayChunks + fn array_chunks<#[rustc_panics_when_zero] const N: usize>(self) -> ArrayChunks where Self: Sized, { @@ -3654,16 +3666,15 @@ pub const trait Iterator { /// assert_eq!(sum, -0.0_f32); /// ``` #[stable(feature = "iter_arith", since = "1.11.0")] - #[rustc_non_const_trait_method] fn sum(self) -> S where Self: Sized, - S: Sum, + S: [const] Sum, { Sum::sum(self) } - /// Iterates over the entire iterator, multiplying all the elements + /// Iterates over the entire iterator, multiplying all the elements. /// /// An empty iterator returns the one value of the type. /// @@ -3687,11 +3698,10 @@ pub const trait Iterator { /// assert_eq!(factorial(5), 120); /// ``` #[stable(feature = "iter_arith", since = "1.11.0")] - #[rustc_non_const_trait_method] fn product

(self) -> P where Self: Sized, - P: Product, + P: [const] Product, { Product::product(self) } @@ -4076,7 +4086,7 @@ pub const trait Iterator { mut compare: impl FnMut(&T, &T) -> bool + 'a, ) -> impl FnMut(T) -> bool + 'a { move |curr| { - if !compare(&last, &curr) { + if !compare(last, &curr) { return false; } *last = curr; diff --git a/library/core/src/iter/traits/marker.rs b/library/core/src/iter/traits/marker.rs index 2e756a6dd67c4..1e6704fe524a9 100644 --- a/library/core/src/iter/traits/marker.rs +++ b/library/core/src/iter/traits/marker.rs @@ -25,7 +25,7 @@ pub unsafe trait TrustedFused {} /// /// [`Fuse`]: crate::iter::Fuse #[stable(feature = "fused", since = "1.26.0")] -#[rustc_unsafe_specialization_marker] +#[unsafe(rustc_allow_lifetime_dependent_specialization)] // FIXME: this should be a #[marker] and have another blanket impl for T: TrustedFused // but that ICEs iter::Fuse specializations. #[lang = "fused_iterator"] @@ -62,10 +62,12 @@ impl FusedIterator for &mut I {} /// This trait must only be implemented when the contract is upheld. Consumers /// of this trait must inspect [`Iterator::size_hint()`]’s upper bound. #[unstable(feature = "trusted_len", issue = "37572")] -#[rustc_unsafe_specialization_marker] -pub unsafe trait TrustedLen: Iterator {} +#[unsafe(rustc_allow_lifetime_dependent_specialization)] +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] +pub const unsafe trait TrustedLen: [const] Iterator {} #[unstable(feature = "trusted_len", issue = "37572")] +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] unsafe impl TrustedLen for &mut I {} /// An iterator that when yielding an item will have taken at least one element diff --git a/library/core/src/iter/traits/mod.rs b/library/core/src/iter/traits/mod.rs index b330e9ffe21ac..7639704d5799c 100644 --- a/library/core/src/iter/traits/mod.rs +++ b/library/core/src/iter/traits/mod.rs @@ -4,7 +4,6 @@ mod double_ended; mod exact_size; mod iterator; mod marker; -mod unchecked_iterator; #[unstable(issue = "none", feature = "inplace_iteration")] pub use self::marker::InPlaceIterable; @@ -12,7 +11,6 @@ pub use self::marker::InPlaceIterable; pub use self::marker::TrustedFused; #[unstable(feature = "trusted_step", issue = "85731")] pub use self::marker::TrustedStep; -pub(crate) use self::unchecked_iterator::UncheckedIterator; #[stable(feature = "rust1", since = "1.0.0")] pub use self::{ accum::{Product, Sum}, diff --git a/library/std/src/keyword_docs.rs b/library/core/src/keyword_docs.rs similarity index 96% rename from library/std/src/keyword_docs.rs rename to library/core/src/keyword_docs.rs index dc0d11b07a9f3..3d914556fc65c 100644 --- a/library/std/src/keyword_docs.rs +++ b/library/core/src/keyword_docs.rs @@ -73,7 +73,7 @@ /// [`use`]: keyword.use.html /// [const-cast]: pointer::cast /// [mut-cast]: primitive.pointer.html#method.cast-1 -mod as_keyword {} +const _: () = (); #[doc(keyword = "break")] // @@ -171,7 +171,7 @@ mod as_keyword {} /// [Reference on "break expression"]: ../reference/expressions/loop-expr.html#break-expressions /// [Reference on "break and loop values"]: /// ../reference/expressions/loop-expr.html#break-and-loop-values -mod break_keyword {} +const _: () = (); #[doc(keyword = "const")] // @@ -195,7 +195,7 @@ mod break_keyword {} /// to be most things that would be reasonable to have in a constant (barring `const fn`s). For /// example, you can't have a [`File`] as a `const`. /// -/// [`File`]: crate::fs::File +/// [`File`]: ../std/fs/struct.File.html /// /// The only lifetime allowed in a constant is `'static`, which is the lifetime that encompasses /// all others in a Rust program. For example, if you wanted to define a constant string, it would @@ -238,7 +238,7 @@ mod break_keyword {} /// /// Turning a `fn` into a `const fn` has no effect on run-time uses of that function. /// -/// ## Other uses of `const` +/// ## raw pointers /// /// The `const` keyword is also used in raw pointers in combination with `mut`, as seen in `*const /// T` and `*mut T`. More about `const` as used in raw pointers can be read at the Rust docs for the [pointer primitive]. @@ -248,7 +248,7 @@ mod break_keyword {} /// [Reference]: ../reference/items/constant-items.html /// [const-blocks]: ../reference/expressions/block-expr.html#const-blocks /// [const-eval]: ../reference/const_eval.html -mod const_keyword {} +const _: () = (); #[doc(keyword = "continue")] // @@ -288,7 +288,7 @@ mod const_keyword {} /// See [continue expressions] from the reference for more details. /// /// [continue expressions]: ../reference/expressions/loop-expr.html#continue-expressions -mod continue_keyword {} +const _: () = (); #[doc(keyword = "crate")] // @@ -325,7 +325,7 @@ mod continue_keyword {} /// module `foo`, from anywhere else in the same crate. /// /// [Reference]: ../reference/items/extern-crates.html -mod crate_keyword {} +const _: () = (); #[doc(keyword = "else")] // @@ -378,7 +378,7 @@ mod crate_keyword {} /// [`match`]: keyword.match.html /// [`false`]: keyword.false.html /// [`if`]: keyword.if.html -mod else_keyword {} +const _: () = (); #[doc(keyword = "enum")] // @@ -418,7 +418,7 @@ mod else_keyword {} /// The first enum shown is the usual kind of enum you'd find in a C-style language. The second /// shows off a hypothetical example of something storing location data, with `Coord` being any /// other type that's needed, for example a struct. The third example demonstrates the kind of -/// data a variant can store, ranging from nothing, to a tuple, to an anonymous struct. +/// data a variant can store, ranging from nothing, to a tuple, to a struct-like variant. /// /// Instantiating enum variants involves explicitly using the enum's name as its namespace, /// followed by one of its variants. `SimpleEnum::SecondVariant` would be an example from above. @@ -433,7 +433,7 @@ mod else_keyword {} /// [ADT]: https://en.wikipedia.org/wiki/Algebraic_data_type /// [Rust Book]: ../book/ch06-01-defining-an-enum.html /// [Reference]: ../reference/items/enumerations.html -mod enum_keyword {} +const _: () = (); #[doc(keyword = "extern")] // @@ -480,18 +480,18 @@ mod enum_keyword {} /// ../book/ch19-01-unsafe-rust.html#using-extern-functions-to-call-external-code /// [Reference]: ../reference/items/external-blocks.html /// [`crate`]: keyword.crate.html -mod extern_keyword {} +const _: () = (); #[doc(keyword = "false")] // -/// A value of type [`bool`] representing logical **false**. +/// A value of type [`prim@bool`] representing logical **false**. /// /// `false` is the logical opposite of [`true`]. /// /// See the documentation for [`true`] for more information. /// /// [`true`]: keyword.true.html -mod false_keyword {} +const _: () = (); #[doc(keyword = "fn")] // @@ -558,7 +558,7 @@ mod false_keyword {} /// [`extern`]: keyword.extern.html /// [Rust book]: ../book/ch03-03-how-functions-work.html /// [Reference]: ../reference/items/functions.html -mod fn_keyword {} +const _: () = (); #[doc(keyword = "for")] // @@ -640,7 +640,7 @@ mod fn_keyword {} /// [Rust book]: /// ../book/ch03-05-control-flow.html#looping-through-a-collection-with-for /// [Reference]: ../reference/expressions/loop-expr.html#iterator-loops -mod for_keyword {} +const _: () = (); #[doc(keyword = "if")] // @@ -714,7 +714,7 @@ mod for_keyword {} /// /// [Rust book]: ../book/ch03-05-control-flow.html#if-expressions /// [Reference]: ../reference/expressions/if-expr.html -mod if_keyword {} +const _: () = (); #[doc(keyword = "impl")] // @@ -804,7 +804,7 @@ mod if_keyword {} /// [book1]: ../book/ch05-03-method-syntax.html /// [Reference]: ../reference/items/implementations.html /// [book2]: ../book/ch10-02-traits.html#returning-types-that-implement-traits -mod impl_keyword {} +const _: () = (); #[doc(keyword = "in")] // @@ -836,7 +836,7 @@ mod impl_keyword {} /// For more information, see the [Reference]. /// /// [Reference]: ../reference/visibility-and-privacy.html#pubin-path-pubcrate-pubsuper-and-pubself -mod in_keyword {} +const _: () = (); #[doc(keyword = "let")] // @@ -899,7 +899,7 @@ mod in_keyword {} /// [`if`]: keyword.if.html /// [book2]: ../book/ch18-01-all-the-places-for-patterns.html#let-statements /// [Reference]: ../reference/statements.html#let-statements -mod let_keyword {} +const _: () = (); #[doc(keyword = "loop")] // @@ -949,7 +949,7 @@ mod let_keyword {} /// [`for`]: keyword.for.html /// [`while`]: keyword.while.html /// [Reference]: ../reference/expressions/loop-expr.html -mod loop_keyword {} +const _: () = (); #[doc(keyword = "match")] // @@ -961,14 +961,14 @@ mod loop_keyword {} /// returned. /// /// ```rust -/// let opt = Option::None::; +/// let opt: Option = None; /// let x = match opt { /// Some(int) => int, /// None => 10, /// }; /// assert_eq!(x, 10); /// -/// let a_number = Option::Some(10); +/// let a_number = Some(10); /// match a_number { /// Some(x) if x <= 5 => println!("0 to 5 num = {x}"), /// Some(x @ 6..=10) => println!("6 to 10 num = {x}"), @@ -999,7 +999,7 @@ mod loop_keyword {} /// For more information on `match` and matching in general, see the [Reference]. /// /// [Reference]: ../reference/expressions/match-expr.html -mod match_keyword {} +const _: () = (); #[doc(keyword = "mod")] // @@ -1027,7 +1027,7 @@ mod match_keyword {} /// [`pub`]: keyword.pub.html /// [`struct`]: keyword.struct.html /// [modules]: ../reference/items/modules.html -mod mod_keyword {} +const _: () = (); #[doc(keyword = "move")] // @@ -1060,7 +1060,8 @@ mod mod_keyword {} /// /// `move` is often used when [threads] are involved. /// -/// ```rust +#[cfg_attr(target_os = "wasi", doc = "```rust,ignore (thread::spawn not supported)")] +#[cfg_attr(not(target_os = "wasi"), doc = "```rust")] /// let data = vec![1, 2, 3]; /// /// std::thread::spawn(move || { @@ -1084,7 +1085,7 @@ mod mod_keyword {} /// /// [closure]: ../book/ch13-01-closures.html /// [threads]: ../book/ch16-01-threads.html#using-move-closures-with-threads -mod move_keyword {} +const _: () = (); #[doc(keyword = "mut")] // @@ -1142,7 +1143,7 @@ mod move_keyword {} /// More information on mutable references and pointers can be found in the [Reference]. /// /// [Reference]: ../reference/types/pointer.html#mutable-references-mut -mod mut_keyword {} +const _: () = (); #[doc(keyword = "pub")] // @@ -1157,7 +1158,7 @@ mod mut_keyword {} /// /// [reference]:../reference/visibility-and-privacy.html?highlight=pub#visibility-and-privacy /// [Rust by Example]:../rust-by-example/mod/visibility.html -mod pub_keyword {} +const _: () = (); #[doc(keyword = "ref")] // @@ -1207,7 +1208,7 @@ mod pub_keyword {} /// /// [`match`]: keyword.match.html /// [Reference]: ../reference/patterns.html#identifier-patterns -mod ref_keyword {} +const _: () = (); #[doc(keyword = "return")] // @@ -1235,31 +1236,18 @@ mod ref_keyword {} /// `return` returns from the function immediately (an "early return"): /// /// ```no_run -/// use std::fs::File; -/// use std::io::{Error, ErrorKind, Read, Result}; -/// -/// fn main() -> Result<()> { -/// let mut file = match File::open("foo.txt") { -/// Ok(f) => f, -/// Err(e) => return Err(e), -/// }; +/// fn main() -> Result<(), &'static str> { +/// let contents = "Hello, world!"; /// -/// let mut contents = String::new(); -/// let size = match file.read_to_string(&mut contents) { -/// Ok(s) => s, -/// Err(e) => return Err(e), -/// }; +/// if contents.contains("impossible!") { +/// return Err("oh no!"); +/// } /// -/// if contents.contains("impossible!") { -/// return Err(Error::new(ErrorKind::Other, "oh no!")); -/// } -/// -/// if size > 9000 { -/// return Err(Error::new(ErrorKind::Other, "over 9000!")); -/// } +/// if contents.len() > 9000 { +/// return Err("over 9000!"); +/// } /// -/// assert_eq!(contents, "Hello, world!"); -/// Ok(()) +/// Ok(()) /// } /// ``` /// @@ -1284,7 +1272,7 @@ mod ref_keyword {} /// /// [closures]: ../book/ch13-01-closures.html /// [`async`]: ../std/keyword.async.html -mod return_keyword {} +const _: () = (); #[doc(keyword = "become")] // @@ -1306,7 +1294,8 @@ mod return_keyword {} /// manner to computed goto). /// /// Example of using `become` to implement functional-style `fold`: -/// ``` +/// +/// ```ignore-wasm (tail-call target feature not enabled by default on wasm) /// #![feature(explicit_tail_calls)] /// #![expect(incomplete_features)] /// @@ -1360,7 +1349,8 @@ mod return_keyword {} /// (unless it's coerced to a function pointer) /// /// It is possible to tail-call a function pointer: -/// ``` +/// +/// ```ignore-wasm (tail-call target feature not enabled by default on wasm) /// #![feature(explicit_tail_calls)] /// #![expect(incomplete_features)] /// @@ -1386,7 +1376,7 @@ mod return_keyword {} /// let program = &[Inst::Inc, Inst::Inc, Inst::Dec, Inst::Inc]; /// assert_eq!(dispatch(program, 0), 2); /// ``` -mod become_keyword {} +const _: () = (); #[doc(keyword = "self")] // @@ -1479,7 +1469,7 @@ mod become_keyword {} /// /// [`use`]: keyword.use.html /// [Reference]: ../reference/items/associated-items.html#methods -mod self_keyword {} +const _: () = (); // FIXME: Once rustdoc can handle URL conflicts on case insensitive file systems, we can replace // these two lines with `#[doc(keyword = "Self")]` and update `is_doc_keyword` in @@ -1550,7 +1540,7 @@ mod self_keyword {} /// /// [`impl`]: keyword.impl.html /// [`trait`]: keyword.trait.html -mod self_upper_keyword {} +const _: () = (); #[doc(keyword = "static")] // @@ -1631,12 +1621,12 @@ mod self_upper_keyword {} /// [`extern`]: keyword.extern.html /// [`mut`]: keyword.mut.html /// [`unsafe`]: keyword.unsafe.html -/// [`Mutex`]: sync::Mutex -/// [`OnceLock`]: sync::OnceLock +/// [`Mutex`]: ../std/sync/struct.Mutex.html +/// [`OnceLock`]: ../std/sync/struct.OnceLock.html /// [`RefCell`]: cell::RefCell /// [atomic]: sync::atomic /// [Reference]: ../reference/items/static-items.html -mod static_keyword {} +const _: () = (); #[doc(keyword = "struct")] // @@ -1744,7 +1734,7 @@ mod static_keyword {} /// [`PhantomData`]: marker::PhantomData /// [book]: ../book/ch05-01-defining-structs.html /// [reference]: ../reference/items/structs.html -mod struct_keyword {} +const _: () = (); #[doc(keyword = "super")] // @@ -1770,7 +1760,7 @@ mod struct_keyword {} /// /// [module]: ../reference/items/modules.html /// [Reference]: ../reference/paths.html#super -mod super_keyword {} +const _: () = (); #[doc(keyword = "trait")] // @@ -1955,11 +1945,11 @@ mod super_keyword {} /// [`unsafe`]: keyword.unsafe.html /// [Ref-Traits]: ../reference/items/traits.html /// [Ref-Trait-Objects]: ../reference/types/trait-object.html -mod trait_keyword {} +const _: () = (); #[doc(keyword = "true")] // -/// A value of type [`bool`] representing logical **true**. +/// A value of type [`prim@bool`] representing logical **true**. /// /// Logically `true` is not equal to [`false`]. /// @@ -1982,7 +1972,7 @@ mod trait_keyword {} /// [`while`]: keyword.while.html /// [`match`]: ../reference/expressions/match-expr.html#match-guards /// [`false`]: keyword.false.html -mod true_keyword {} +const _: () = (); #[doc(keyword = "type")] // @@ -2034,7 +2024,7 @@ mod true_keyword {} /// [`trait`]: keyword.trait.html /// [associated type]: ../reference/items/associated-items.html#associated-types /// [alias]: ../reference/items/type-aliases.html -mod type_keyword {} +const _: () = (); #[doc(keyword = "unsafe")] // @@ -2042,10 +2032,19 @@ mod type_keyword {} /// system. /// /// The `unsafe` keyword has two uses: -/// - to declare the existence of contracts the compiler can't check (`unsafe fn` and `unsafe -/// trait`), -/// - and to declare that a programmer has checked that these contracts have been upheld (`unsafe -/// {}` and `unsafe impl`, but also `unsafe fn` -- see below). +/// - to declare the existence of contracts the compiler can't check, +/// - and to declare that a programmer has checked that these contracts have been upheld. +/// +/// Typically, each `unsafe` is either of the first or second kind: `unsafe fn` and `unsafe trait` +/// declare the existence of an unsafe contract; `unsafe {}` and `unsafe impl` declare that an +/// unsafe contract (which must have been declared elsewhere) is being upheld. +/// +/// However, historically, these two are not mutually exclusive: the body of an `unsafe fn` is, on +/// old editions, treated like an unsafe block, which means that this use of `unsafe` both declares +/// the existence of a contract to call the current function, and declares that the contracts of the +/// unsafe operations inside this function are being upheld. The `unsafe_op_in_unsafe_fn` lint can +/// be enabled to change that and make `unsafe fn` only play the former role. That lint is enabled +/// by default since edition 2024. /// /// # Unsafe abilities /// @@ -2088,6 +2087,13 @@ mod type_keyword {} /// - `unsafe impl`: the contract necessary to implement the trait has been /// checked by the programmer and is guaranteed to be respected. /// +/// On old editions, `unsafe fn` also acts like an `unsafe {}` block around the code inside the +/// function. This means it is not just a signal to the caller, but also promises that the +/// preconditions for the operations inside the function are upheld. Mixing these two meanings can +/// be confusing, so the `unsafe_op_in_unsafe_fn` lint has been introduced and enabled by default +/// since edition 2024 to warn against that and require explicit unsafe blocks even inside `unsafe +/// fn`. +/// /// See the [Rustonomicon] and the [Reference] for more information. /// /// # Examples @@ -2296,6 +2302,7 @@ mod type_keyword {} /// [`static`]: keyword.static.html /// [`union`]: keyword.union.html /// [`impl`]: keyword.impl.html +/// [`Vec::set_len`]: ../std/vec/struct.Vec.html#method.set_len /// [raw pointers]: ../reference/types/pointer.html /// [memory safety]: ../book/ch19-01-unsafe-rust.html /// [Rustonomicon]: ../nomicon/index.html @@ -2303,7 +2310,7 @@ mod type_keyword {} /// [soundness]: https://rust-lang.github.io/unsafe-code-guidelines/glossary.html#soundness-of-code--of-a-library /// [Reference]: ../reference/unsafety.html /// [discussion on Rust Internals]: https://internals.rust-lang.org/t/what-does-unsafe-mean/6696 -mod unsafe_keyword {} +const _: () = (); #[doc(keyword = "use")] // @@ -2401,7 +2408,7 @@ mod unsafe_keyword {} /// [`super`]: keyword.super.html /// [ref-use-decls]: ../reference/items/use-declarations.html /// [ref-impl-trait]: ../reference/types/impl-trait.html -mod use_keyword {} +const _: () = (); #[doc(keyword = "where")] // @@ -2486,7 +2493,7 @@ mod use_keyword {} /// ``` /// /// `where` is available anywhere generic and lifetime parameters are available, -/// as can be seen with the [`Cow`](crate::borrow::Cow) type from the standard +/// as can be seen with the [`Cow`](../std/borrow/enum.Cow.html) type from the standard /// library: /// /// ```rust @@ -2501,7 +2508,7 @@ mod use_keyword {} /// ``` /// /// [RFC]: https://github.com/rust-lang/rfcs/blob/master/text/0135-where.md -mod where_keyword {} +const _: () = (); #[doc(keyword = "while")] // @@ -2559,7 +2566,7 @@ mod where_keyword {} /// [`for`]: keyword.for.html /// [`loop`]: keyword.loop.html /// [reference]: ../reference/expressions/loop-expr.html#predicate-loops -mod while_keyword {} +const _: () = (); // 2018 Edition keywords @@ -2621,7 +2628,7 @@ mod while_keyword {} /// [never type]: ../reference/types/never.html /// [`Result`]: result::Result /// [async book blocks]: https://rust-lang.github.io/async-book/part-guide/more-async-await.html#async-blocks -mod async_keyword {} +const _: () = (); #[doc(keyword = "await")] // @@ -2641,7 +2648,7 @@ mod async_keyword {} /// [`Future`]: future::Future /// [async book]: https://rust-lang.github.io/async-book/ /// [`async`]: ../std/keyword.async.html -mod await_keyword {} +const _: () = (); #[doc(keyword = "dyn")] // @@ -2677,7 +2684,7 @@ mod await_keyword {} /// [ref-dyn-compat]: ../reference/items/traits.html#dyn-compatibility /// [erased]: https://en.wikipedia.org/wiki/Type_erasure /// [^1]: Formerly known as *object safe*. -mod dyn_keyword {} +const _: () = (); #[doc(keyword = "union")] // @@ -2751,4 +2758,4 @@ mod dyn_keyword {} /// /// [`struct`]: keyword.struct.html /// [union]: ../reference/items/unions.html -mod union_keyword {} +const _: () = (); diff --git a/library/core/src/lib.rs b/library/core/src/lib.rs index 57864d80376c4..164ac9daa9573 100644 --- a/library/core/src/lib.rs +++ b/library/core/src/lib.rs @@ -48,30 +48,19 @@ html_playground_url = "https://play.rust-lang.org/", issue_tracker_base_url = "https://github.com/rust-lang/rust/issues/", test(no_crate_inject, attr(deny(warnings))), - test(attr(allow(dead_code, deprecated, unused_variables, unused_mut))) + test(attr(allow(dead_code, deprecated, unused_variables, unused_mut, duplicate_features))) )] #![doc(rust_logo)] -#![doc(auto_cfg(hide( - no_fp_fmt_parse, - target_pointer_width = "16", - target_pointer_width = "32", - target_pointer_width = "64", - target_has_atomic = "8", - target_has_atomic = "16", - target_has_atomic = "32", - target_has_atomic = "64", - target_has_atomic = "ptr", - target_has_atomic_equal_alignment = "8", - target_has_atomic_equal_alignment = "16", - target_has_atomic_equal_alignment = "32", - target_has_atomic_equal_alignment = "64", - target_has_atomic_equal_alignment = "ptr", - target_has_atomic_load_store = "8", - target_has_atomic_load_store = "16", - target_has_atomic_load_store = "32", - target_has_atomic_load_store = "64", - target_has_atomic_load_store = "ptr", -)))] +#![doc(auto_cfg( + hide(no_fp_fmt_parse), + hide(target_pointer_width, values("16", "32", "64")), + hide( + target_has_atomic, + target_has_atomic_primitive_alignment, + target_has_atomic_load_store, + values("8", "16", "32", "64", "ptr"), + ), +))] #![no_core] #![rustc_coherence_is_core] #![rustc_preserve_ub_checks] @@ -79,7 +68,7 @@ // Lints: #![deny(rust_2021_incompatible_or_patterns)] #![deny(unsafe_op_in_unsafe_fn)] -#![deny(fuzzy_provenance_casts)] +#![deny(implicit_provenance_casts)] #![warn(deprecated_in_future)] #![warn(missing_debug_implementations)] #![warn(missing_docs)] @@ -87,6 +76,7 @@ #![allow(incomplete_features)] #![warn(multiple_supertrait_upcastable)] #![allow(internal_features)] +#![allow(unused_features)] #![deny(ffi_unwind_calls)] #![warn(unreachable_pub)] // Do not check link redundancy on bootstrapping phase @@ -95,42 +85,22 @@ // // Library features: // tidy-alphabetical-start -#![feature(array_ptr_get)] #![feature(asm_experimental_arch)] -#![feature(bstr)] #![feature(bstr_internals)] -#![feature(cfg_select)] #![feature(cfg_target_has_reliable_f16_f128)] #![feature(const_carrying_mul_add)] #![feature(const_cmp)] #![feature(const_destruct)] #![feature(const_eval_select)] #![feature(const_select_unpredictable)] -#![feature(const_unsigned_bigint_helpers)] #![feature(core_intrinsics)] #![feature(coverage_attribute)] #![feature(disjoint_bitor)] -#![feature(internal_impls_macro)] -#![feature(ip)] -#![feature(is_ascii_octdigit)] -#![feature(link_cfg)] +#![feature(io_const_error)] #![feature(offset_of_enum)] #![feature(panic_internals)] #![feature(pattern_type_macro)] -#![feature(ptr_alignment_type)] -#![feature(ptr_metadata)] -#![feature(set_ptr_value)] -#![feature(signed_bigint_helpers)] -#![feature(slice_ptr_get)] -#![feature(str_internals)] -#![feature(str_split_inclusive_remainder)] -#![feature(str_split_remainder)] -#![feature(type_info)] #![feature(ub_checks)] -#![feature(unsafe_pinned)] -#![feature(utf16_extra)] -#![feature(variant_count)] -#![feature(widening_mul)] // tidy-alphabetical-end // // Language features: @@ -142,26 +112,31 @@ #![feature(auto_traits)] #![feature(cfg_sanitize)] #![feature(cfg_target_has_atomic)] -#![feature(cfg_target_has_atomic_equal_alignment)] #![feature(cfg_ub_checks)] +#![feature(const_closures)] #![feature(const_precise_live_drops)] #![feature(const_trait_impl)] #![feature(decl_macro)] #![feature(deprecated_suggestion)] #![feature(derive_const)] #![feature(diagnostic_on_const)] +#![feature(diagnostic_on_unmatched_args)] +#![feature(diagnostic_opaque)] #![feature(doc_cfg)] #![feature(doc_notable_trait)] #![feature(extern_types)] #![feature(f16)] #![feature(f128)] +#![feature(field_projections)] +#![feature(final_associated_functions)] #![feature(freeze_impls)] #![feature(fundamental)] #![feature(funnel_shifts)] -#![feature(if_let_guard)] +#![feature(impl_restriction)] #![feature(intra_doc_pointers)] #![feature(intrinsics)] #![feature(lang_items)] +#![feature(link_cfg)] #![feature(link_llvm_intrinsics)] #![feature(macro_metavar_expr)] #![feature(macro_metavar_expr_concat)] @@ -174,20 +149,20 @@ #![feature(no_core)] #![feature(optimize_attribute)] #![feature(pattern_types)] +#![feature(pin_macro_internals)] #![feature(prelude_import)] -#![feature(reborrow)] #![feature(repr_simd)] -#![feature(rustc_allow_const_fn_unstable)] #![feature(rustc_attrs)] #![feature(rustdoc_internals)] #![feature(simd_ffi)] +#![feature(splat)] #![feature(staged_api)] #![feature(stmt_expr_attributes)] #![feature(strict_provenance_lints)] -#![feature(target_feature_inline_always)] #![feature(trait_alias)] #![feature(transparent_unions)] #![feature(try_blocks)] +#![feature(uint_carryless_mul)] #![feature(unboxed_closures)] #![feature(unsized_fn_params)] #![feature(with_negative_coherence)] @@ -200,9 +175,11 @@ #![feature(aarch64_unstable_target_feature)] #![feature(arm_target_feature)] #![feature(avx10_target_feature)] +#![feature(clflushopt_target_feature)] #![feature(hexagon_target_feature)] #![feature(loongarch_target_feature)] #![feature(mips_target_feature)] +#![feature(movrs_target_feature)] #![feature(nvptx_target_feature)] #![feature(powerpc_target_feature)] #![feature(riscv_target_feature)] @@ -227,7 +204,7 @@ use prelude::rust_2024::*; #[macro_use] mod macros; -#[unstable(feature = "assert_matches", issue = "82775")] +#[stable(feature = "assert_matches", since = "1.96.0")] pub use crate::macros::{assert_matches, debug_assert_matches}; #[unstable(feature = "derive_from", issue = "144889")] @@ -239,16 +216,22 @@ pub mod from { // We don't export this through #[macro_export] for now, to avoid breakage. #[unstable(feature = "autodiff", issue = "124509")] -/// Unstable module containing the unstable `autodiff` macro. +#[doc = include_str!("../../core/src/autodiff.md")] pub mod autodiff { #[unstable(feature = "autodiff", issue = "124509")] pub use crate::macros::builtin::{autodiff_forward, autodiff_reverse}; } +#[unstable(feature = "gpu_offload", issue = "131513")] +#[doc = include_str!("../../core/src/offload.md")] +pub mod offload; + #[unstable(feature = "contracts", issue = "128044")] pub mod contracts; -#[unstable(feature = "cfg_select", issue = "115585")] +#[unstable(feature = "derive_macro_global_path", issue = "154645")] +pub use crate::macros::builtin::derive; +#[stable(feature = "cfg_select", since = "1.95.0")] pub use crate::macros::cfg_select; #[macro_use] @@ -257,12 +240,10 @@ mod internal_macros; #[path = "num/shells/legacy_int_modules.rs"] mod legacy_int_modules; #[stable(feature = "rust1", since = "1.0.0")] -#[allow(clippy::useless_attribute)] // FIXME false positive (https://github.com/rust-lang/rust-clippy/issues/15636) -#[allow(deprecated_in_future)] +#[allow(deprecated, clippy::legacy_numeric_constants)] pub use legacy_int_modules::{i8, i16, i32, i64, isize, u8, u16, u32, u64, usize}; #[stable(feature = "i128", since = "1.26.0")] -#[allow(clippy::useless_attribute)] // FIXME false positive (https://github.com/rust-lang/rust-clippy/issues/15636) -#[allow(deprecated_in_future)] +#[allow(deprecated, clippy::legacy_numeric_constants)] pub use legacy_int_modules::{i128, u128}; #[path = "num/f128.rs"] @@ -296,6 +277,8 @@ pub mod cmp; pub mod convert; pub mod default; pub mod error; +#[unstable(feature = "field_projections", issue = "145383")] +pub mod field; pub mod index; pub mod marker; pub mod ops; @@ -313,7 +296,7 @@ pub mod bstr; pub mod cell; pub mod char; pub mod ffi; -#[unstable(feature = "core_io_borrowed_buf", issue = "117693")] +#[unstable(feature = "core_io", issue = "154046")] pub mod io; pub mod iter; pub mod net; @@ -324,9 +307,11 @@ pub mod panicking; #[unstable(feature = "pattern_type_macro", issue = "123646")] pub mod pat; pub mod pin; +#[unstable(feature = "abort_immediate", issue = "154601")] +pub mod process; #[unstable(feature = "random", issue = "130703")] pub mod random; -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] pub mod range; pub mod result; pub mod sync; @@ -356,6 +341,8 @@ mod bool; mod escape; mod tuple; mod unit; +#[unstable(feature = "view_type_macro", issue = "155938")] +pub mod view; #[stable(feature = "core_primitive", since = "1.43.0")] pub mod primitive; @@ -406,6 +393,19 @@ pub mod simd { pub use crate::core_simd::simd::*; } +// Include private modules that exist solely to provide rustdoc +// documentation for built-in attributes. Using `include!` because rustdoc +// only looks for these modules at the crate level. +include!("attribute_docs.rs"); + +// Include a number of private modules that exist solely to provide +// the rustdoc documentation for the existing keywords. Using `include!` +// because rustdoc only looks for these modules at the crate level. +include!("keyword_docs.rs"); + +// Include a number of private modules that exist solely to provide +// the rustdoc documentation for primitive types. Using `include!` +// because rustdoc only looks for these modules at the crate level. include!("primitive_docs.rs"); #[cfg(flux)] diff --git a/library/core/src/macros/mod.rs b/library/core/src/macros/mod.rs index 3176f3c067092..ab8fc47009186 100644 --- a/library/core/src/macros/mod.rs +++ b/library/core/src/macros/mod.rs @@ -39,8 +39,9 @@ macro_rules! panic { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_diagnostic_item = "assert_eq_macro"] #[allow_internal_unstable(panic_internals)] +#[rustc_diagnostic_opaque] macro_rules! assert_eq { - ($left:expr, $right:expr $(,)?) => { + ($left:expr, $right:expr $(,)?) => {{ match (&$left, &$right) { (left_val, right_val) => { if !(*left_val == *right_val) { @@ -52,8 +53,8 @@ macro_rules! assert_eq { } } } - }; - ($left:expr, $right:expr, $($arg:tt)+) => { + }}; + ($left:expr, $right:expr, $($arg:tt)+) => {{ match (&$left, &$right) { (left_val, right_val) => { if !(*left_val == *right_val) { @@ -65,7 +66,7 @@ macro_rules! assert_eq { } } } - }; + }}; } /// Asserts that two expressions are not equal to each other (using [`PartialEq`]). @@ -95,8 +96,9 @@ macro_rules! assert_eq { #[stable(feature = "assert_ne", since = "1.13.0")] #[rustc_diagnostic_item = "assert_ne_macro"] #[allow_internal_unstable(panic_internals)] +#[rustc_diagnostic_opaque] macro_rules! assert_ne { - ($left:expr, $right:expr $(,)?) => { + ($left:expr, $right:expr $(,)?) => {{ match (&$left, &$right) { (left_val, right_val) => { if *left_val == *right_val { @@ -108,8 +110,8 @@ macro_rules! assert_ne { } } } - }; - ($left:expr, $right:expr, $($arg:tt)+) => { + }}; + ($left:expr, $right:expr, $($arg:tt)+) => {{ match (&($left), &($right)) { (left_val, right_val) => { if *left_val == *right_val { @@ -121,11 +123,9 @@ macro_rules! assert_ne { } } } - }; + }}; } -// FIXME add back debug_assert_matches doc link after bootstrap. - /// Asserts that an expression matches the provided pattern. /// /// This macro is generally preferable to `assert!(matches!(value, pattern))`, because it can print @@ -137,9 +137,11 @@ macro_rules! assert_ne { /// otherwise this macro will panic. /// /// Assertions are always checked in both debug and release builds, and cannot -/// be disabled. See `debug_assert_matches!` for assertions that are disabled in +/// be disabled. See [`debug_assert_matches!`] for assertions that are disabled in /// release builds by default. /// +/// [`debug_assert_matches!`]: crate::debug_assert_matches +/// /// On panic, this macro will print the value of the expression with its debug representation. /// /// Like [`assert!`], this macro has a second form, where a custom panic message can be provided. @@ -147,8 +149,6 @@ macro_rules! assert_ne { /// # Examples /// /// ``` -/// #![feature(assert_matches)] -/// /// use std::assert_matches; /// /// let a = Some(345); @@ -166,11 +166,11 @@ macro_rules! assert_ne { /// assert_matches!(a, Some(x) if x > 100); /// // assert_matches!(a, Some(x) if x < 100); // panics /// ``` -#[unstable(feature = "assert_matches", issue = "82775")] +#[stable(feature = "assert_matches", since = "1.96.0")] #[allow_internal_unstable(panic_internals)] #[rustc_macro_transparency = "semiopaque"] pub macro assert_matches { - ($left:expr, $(|)? $( $pattern:pat_param )|+ $( if $guard: expr )? $(,)?) => { + ($left:expr, $(|)? $( $pattern:pat_param )|+ $( if $guard: expr )? $(,)?) => {{ match $left { $( $pattern )|+ $( if $guard )? => {} ref left_val => { @@ -181,8 +181,8 @@ pub macro assert_matches { ); } } - }, - ($left:expr, $(|)? $( $pattern:pat_param )|+ $( if $guard: expr )?, $($arg:tt)+) => { + }}, + ($left:expr, $(|)? $( $pattern:pat_param )|+ $( if $guard: expr )?, $($arg:tt)+) => {{ match $left { $( $pattern )|+ $( if $guard )? => {} ref left_val => { @@ -193,7 +193,7 @@ pub macro assert_matches { ); } } - }, + }}, } /// Selects code at compile-time based on `cfg` predicates. @@ -208,8 +208,6 @@ pub macro assert_matches { /// # Example /// /// ``` -/// #![feature(cfg_select)] -/// /// cfg_select! { /// unix => { /// fn foo() { /* unix specific functionality */ } @@ -227,14 +225,13 @@ pub macro assert_matches { /// right-hand side: /// /// ``` -/// #![feature(cfg_select)] -/// /// let _some_string = cfg_select! { /// unix => "With great power comes great electricity bills", /// _ => { "Behind every successful diet is an unwatched pizza" } /// }; /// ``` -#[unstable(feature = "cfg_select", issue = "115585")] +#[stable(feature = "cfg_select", since = "1.95.0")] +#[doc(alias = "cfg_if", alias = "cfg-if")] #[rustc_diagnostic_item = "cfg_select"] #[rustc_builtin_macro] pub macro cfg_select($($tt:tt)*) { @@ -289,6 +286,7 @@ pub macro cfg_select($($tt:tt)*) { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_diagnostic_item = "debug_assert_macro"] #[allow_internal_unstable(edition_panic)] +#[rustc_diagnostic_opaque] macro_rules! debug_assert { ($($arg:tt)*) => { if $crate::cfg!(debug_assertions) { @@ -380,8 +378,6 @@ macro_rules! debug_assert_ne { /// # Examples /// /// ``` -/// #![feature(assert_matches)] -/// /// use std::debug_assert_matches; /// /// let a = Some(345); @@ -399,7 +395,7 @@ macro_rules! debug_assert_ne { /// debug_assert_matches!(a, Some(x) if x > 100); /// // debug_assert_matches!(a, Some(x) if x < 100); // panics /// ``` -#[unstable(feature = "assert_matches", issue = "82775")] +#[stable(feature = "assert_matches", since = "1.96.0")] #[allow_internal_unstable(assert_matches)] #[rustc_macro_transparency = "semiopaque"] pub macro debug_assert_matches($($arg:tt)*) { @@ -431,6 +427,7 @@ pub macro debug_assert_matches($($arg:tt)*) { #[stable(feature = "matches_macro", since = "1.42.0")] #[rustc_diagnostic_item = "matches_macro"] #[allow_internal_unstable(non_exhaustive_omitted_patterns_lint, stmt_expr_attributes)] +#[rustc_diagnostic_opaque] macro_rules! matches { ($expression:expr, $pattern:pat $(if $guard:expr)? $(,)?) => { #[allow(non_exhaustive_omitted_patterns)] @@ -449,7 +446,7 @@ macro_rules! matches { /// [raw-identifier syntax][ris]: `r#try`. /// /// [propagating-errors]: https://doc.rust-lang.org/book/ch09-02-recoverable-errors-with-result.html#a-shortcut-for-propagating-errors-the--operator -/// [ris]: https://doc.rust-lang.org/nightly/rust-by-example/compatibility/raw_identifiers.html +/// [ris]: ../rust-by-example/compatibility/raw_identifiers.html /// /// `try!` matches the given [`Result`]. In case of the `Ok` variant, the /// expression has the value of the wrapped value. @@ -602,15 +599,19 @@ macro_rules! r#try { /// } /// /// let mut m = Example{}; -/// write!(&mut m, "Hello World").expect("Not written"); +/// write!(&mut m, "Hello World").expect("Writing to `Example` should succeed"); /// ``` #[macro_export] #[stable(feature = "rust1", since = "1.0.0")] #[rustc_diagnostic_item = "write_macro"] +#[rustc_diagnostic_opaque] macro_rules! write { ($dst:expr, $($arg:tt)*) => { $dst.write_fmt($crate::format_args!($($arg)*)) }; + ($($arg:tt)*) => { + compile_error!("requires a destination and format arguments, like `write!(dest, \"format string\", args...)`") + }; } /// Writes formatted data into a buffer, with a newline appended. @@ -642,6 +643,7 @@ macro_rules! write { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_diagnostic_item = "writeln_macro"] #[allow_internal_unstable(format_args_nl)] +#[rustc_diagnostic_opaque] macro_rules! writeln { ($dst:expr $(,)?) => { $crate::write!($dst, "\n") @@ -649,6 +651,9 @@ macro_rules! writeln { ($dst:expr, $($arg:tt)*) => { $dst.write_fmt($crate::format_args_nl!($($arg)*)) }; + ($($arg:tt)*) => { + compile_error!("requires a destination and format arguments, like `writeln!(dest, \"format string\", args...)`") + }; } /// Indicates unreachable code. @@ -794,6 +799,7 @@ macro_rules! unreachable { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_diagnostic_item = "unimplemented_macro"] #[allow_internal_unstable(panic_internals)] +#[rustc_diagnostic_opaque] macro_rules! unimplemented { () => { $crate::panicking::panic("not implemented") @@ -874,6 +880,7 @@ macro_rules! unimplemented { #[stable(feature = "todo_macro", since = "1.40.0")] #[rustc_diagnostic_item = "todo_macro"] #[allow_internal_unstable(panic_internals)] +#[rustc_diagnostic_opaque] macro_rules! todo { () => { $crate::panicking::panic("not yet implemented") @@ -1629,6 +1636,48 @@ pub(crate) mod builtin { /* compiler built-in */ } + /// The `offload_kernel` macro is applied to a function to generate two separate + /// definitions: a host-side wrapper for dispatch and a device-side kernel. + /// + /// The macro does not perform the offload itself. It generates the necessary + /// code required by the compiler's offloading infrastructure. + /// + /// ### Usage example: + /// + /// ```rust,ignore (offload requires a -Z flag) + /// #[offload_kernel] + /// fn foo(a: &[f32], b: &[f32], c: *mut f32) { + /// *c = a[0] + b[0]; + /// } + /// ``` + /// + /// This expands to the host-side function: + /// + /// ```rust,ignore (offload requires a -Z flag) + /// #[unsafe(no_mangle)] + /// #[inline(never)] + /// fn foo(_: &[f32], _: &[f32], _: *mut f32) { + /// ::core::panicking::panic("not implemented") + /// } + /// ``` + /// + /// And the device-side kernel: + /// + /// ```rust,ignore (offload requires a -Z flag) + /// #[rustc_offload_kernel] + /// #[unsafe(no_mangle)] + /// unsafe extern "gpu-kernel" fn foo(a: &[f32], b: &[f32], c: *mut f32) { + /// *c = a[0] + b[0]; + /// } + /// ``` + #[unstable(feature = "gpu_offload", issue = "131513")] + #[allow_internal_unstable(rustc_attrs)] + #[allow_internal_unstable(core_intrinsics)] + #[rustc_builtin_macro] + pub macro offload_kernel($item:item) { + /* compiler built-in */ + } + /// Asserts that a boolean expression is `true` at runtime. /// /// This will invoke the [`panic!`] macro if the provided expression cannot be @@ -1722,7 +1771,7 @@ pub(crate) mod builtin { /// /// See [the reference] for more info. /// - /// [the reference]: ../../../reference/attributes/derive.html + /// [the reference]: ../reference/attributes/derive.html #[stable(feature = "rust1", since = "1.0.0")] #[rustc_builtin_macro] pub macro derive($item:item) { @@ -1781,7 +1830,7 @@ pub(crate) mod builtin { /// /// See also [`std::alloc::GlobalAlloc`](../../../std/alloc/trait.GlobalAlloc.html). #[stable(feature = "global_allocator", since = "1.28.0")] - #[allow_internal_unstable(rustc_attrs)] + #[allow_internal_unstable(rustc_attrs, ptr_alignment_type)] #[rustc_builtin_macro] pub macro global_allocator($item:item) { /* compiler built-in */ @@ -1864,7 +1913,7 @@ pub(crate) mod builtin { issue = "23416", reason = "placeholder syntax for type ascription" )] - #[rustfmt::skip] + #[diagnostic::opaque] pub macro type_ascribe($expr:expr, $ty:ty) { builtin # type_ascribe($expr, $ty) } @@ -1876,6 +1925,7 @@ pub(crate) mod builtin { issue = "87121", reason = "placeholder syntax for deref patterns" )] + #[diagnostic::opaque] pub macro deref($pat:pat) { builtin # deref($pat) } diff --git a/library/core/src/macros/panic.md b/library/core/src/macros/panic.md index 6bd23b3072ed9..1a436c7564e0f 100644 --- a/library/core/src/macros/panic.md +++ b/library/core/src/macros/panic.md @@ -19,7 +19,7 @@ call. You can override the panic hook using [`std::panic::set_hook()`]. Inside the hook a panic can be accessed as a `&dyn Any + Send`, which contains either a `&str` or `String` for regular `panic!()` invocations. (Whether a particular invocation contains the payload at type `&str` or `String` is unspecified and can change.) -To panic with a value of another other type, [`panic_any`] can be used. +To panic with a value of another type, [`panic_any`] can be used. See also the macro [`compile_error!`], for raising errors during compilation. diff --git a/library/core/src/marker.rs b/library/core/src/marker.rs index 718ca6340c8ef..8dbe6efe97218 100644 --- a/library/core/src/marker.rs +++ b/library/core/src/marker.rs @@ -46,15 +46,12 @@ use crate::pin::UnsafePinned; /// marker_impls! { /// MarkerTrait for /// u8, i8, -/// {T: ?Sized} *const T, -/// {T: ?Sized} *mut T, +/// {T: PointeeSized} *const T, +/// {T: PointeeSized} *mut T, /// {T: MarkerTrait} PhantomData, /// u32, /// } /// ``` -#[unstable(feature = "internal_impls_macro", issue = "none")] -// Allow implementations of `UnsizedConstParamTy` even though std cannot use that feature. -#[allow_internal_unstable(unsized_const_params)] macro marker_impls { ( $(#[$($meta:tt)*])* $Trait:ident for $({$($bounds:tt)*})? $T:ty $(, $($rest:tt)*)? ) => { $(#[$($meta)*])* impl< $($($bounds)*)? > $Trait for $T {} @@ -851,7 +848,7 @@ impl Copy for PhantomData {} #[stable(feature = "rust1", since = "1.0.0")] impl Clone for PhantomData { fn clone(&self) -> Self { - Self + *self } } @@ -861,7 +858,7 @@ unsafe impl TrivialClone for PhantomData {} #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for PhantomData { +const impl Default for PhantomData { fn default() -> Self { Self } @@ -929,14 +926,22 @@ marker_impls! { /// This is part of [RFC 3467](https://rust-lang.github.io/rfcs/3467-unsafe-pinned.html), and is /// tracked by [#125735](https://github.com/rust-lang/rust/issues/125735). #[lang = "unsafe_unpin"] -pub(crate) unsafe auto trait UnsafeUnpin {} +#[unstable(feature = "unsafe_unpin", issue = "125735")] +pub unsafe auto trait UnsafeUnpin {} -impl !UnsafeUnpin for UnsafePinned {} -unsafe impl UnsafeUnpin for PhantomData {} -unsafe impl UnsafeUnpin for *const T {} -unsafe impl UnsafeUnpin for *mut T {} -unsafe impl UnsafeUnpin for &T {} -unsafe impl UnsafeUnpin for &mut T {} +#[unstable(feature = "unsafe_unpin", issue = "125735")] +impl !UnsafeUnpin for UnsafePinned {} +marker_impls! { +#[unstable(feature = "unsafe_unpin", issue = "125735")] + unsafe UnsafeUnpin for + {T: PointeeSized} PhantomData, + {T: PointeeSized} *const T, + {T: PointeeSized} *mut T, + {T: PointeeSized} &T, + {T: PointeeSized} &mut T, + {T: PointeeSized} pattern_type!(*const T is !null), + {T: PointeeSized} pattern_type!(*mut T is !null), +} /// Types that do not require any pinning guarantees. /// @@ -1020,6 +1025,7 @@ pub auto trait Unpin {} // will likely eventually be deprecated, and all new code should be using `UnsafePinned` instead. #[stable(feature = "pin", since = "1.33.0")] #[derive(Debug, Default, Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash)] +#[rustc_diagnostic_item = "PhantomPinned"] pub struct PhantomPinned; #[stable(feature = "pin", since = "1.33.0")] @@ -1029,6 +1035,7 @@ impl !Unpin for PhantomPinned {} // continue working. Ideally PhantomPinned could just wrap an `UnsafePinned<()>` to get the same // effect, but we can't add a new field to an already stable unit struct -- that would be a breaking // change. +#[unstable(feature = "unsafe_unpin", issue = "125735")] impl !UnsafeUnpin for PhantomPinned {} marker_impls! { @@ -1052,7 +1059,7 @@ marker_impls! { #[unstable(feature = "const_destruct", issue = "133214")] #[rustc_const_unstable(feature = "const_destruct", issue = "133214")] #[lang = "destruct"] -#[rustc_on_unimplemented(message = "can't drop `{Self}`", append_const_msg)] +#[diagnostic::on_unimplemented(message = "can't drop `{Self}`")] #[rustc_deny_explicit_impl] #[rustc_dyn_incompatible_trait] pub const trait Destruct: PointeeSized {} @@ -1061,13 +1068,28 @@ pub const trait Destruct: PointeeSized {} /// /// The implementation of this trait is built-in and cannot be implemented /// for any user type. -#[unstable(feature = "tuple_trait", issue = "none")] +#[unstable(feature = "tuple_trait", issue = "157987")] #[lang = "tuple_trait"] #[diagnostic::on_unimplemented(message = "`{Self}` is not a tuple")] +#[fundamental] #[rustc_deny_explicit_impl] #[rustc_dyn_incompatible_trait] pub trait Tuple {} +/// Creates a new style directly represented const argument. +/// ```ignore (cannot test this from within core yet) +/// type const BAR: usize = N; +/// type const FOO: usize = direct!(BAR::); +/// ``` +#[rustc_builtin_macro(direct_const_arg)] +#[unstable(feature = "min_generic_const_args", issue = "132980")] +#[macro_export] +macro_rules! direct_const_arg { + ($($arg:tt)*) => { + /* compiler built-in */ + }; +} + /// A marker for types which can be used as types of `const` generic parameters. /// /// These types must have a proper equivalence relation (`Eq`) and it must be automatically @@ -1075,7 +1097,7 @@ pub trait Tuple {} /// that all fields are also `ConstParamTy`, which implies that recursively, all fields /// are `StructuralPartialEq`. #[lang = "const_param_ty"] -#[unstable(feature = "unsized_const_params", issue = "95174")] +#[unstable(feature = "const_param_ty_trait", issue = "95174", implied_by = "unsized_const_params")] #[diagnostic::on_unimplemented(message = "`{Self}` can't be used as a const parameter type")] #[allow(multiple_supertrait_upcastable)] // We name this differently than the derive macro so that the `adt_const_params` can @@ -1085,15 +1107,19 @@ pub trait ConstParamTy_: StructuralPartialEq + Eq {} /// Derive macro generating an impl of the trait `ConstParamTy`. #[rustc_builtin_macro] -#[allow_internal_unstable(unsized_const_params)] -#[unstable(feature = "adt_const_params", issue = "95174")] +#[allow_internal_unstable(const_param_ty_trait)] +#[unstable(feature = "min_adt_const_params", issue = "154042", implied_by = "adt_const_params")] pub macro ConstParamTy($item:item) { /* compiler built-in */ } +// For `adt_const_params` to be recognized as a feature +#[unstable(feature = "adt_const_params", issue = "95174")] +const _: () = (); + // FIXME(adt_const_params): handle `ty::FnDef`/`ty::Closure` marker_impls! { - #[unstable(feature = "adt_const_params", issue = "95174")] + #[unstable(feature = "min_adt_const_params", issue = "154042")] ConstParamTy_ for usize, u8, u16, u32, u64, u128, isize, i8, i16, i32, i64, i128, @@ -1112,24 +1138,6 @@ marker_impls! { {T: ConstParamTy_ + ?Sized} &T, } -/// A common trait implemented by all function pointers. -// -// Note that while the trait is internal and unstable it is nevertheless -// exposed as a public bound of the stable `core::ptr::fn_addr_eq` function. -#[unstable( - feature = "fn_ptr_trait", - issue = "none", - reason = "internal trait for implementing various traits for all function pointers" -)] -#[lang = "fn_ptr_trait"] -#[rustc_deny_explicit_impl] -#[rustc_dyn_incompatible_trait] -pub trait FnPtr: Copy + Clone { - /// Returns the address of the function pointer. - #[lang = "fn_ptr_addr"] - fn addr(self) -> *const (); -} - /// Derive macro that makes a smart pointer usable with trait objects. /// /// # What this macro does @@ -1339,3 +1347,37 @@ pub macro CoercePointee($item:item) { pub trait CoercePointeeValidated { /* compiler built-in */ } + +/// Allows value to be reborrowed as exclusive, creating a copy of the value +/// that disables the source for reads and writes for the lifetime of the copy. +#[lang = "reborrow"] +#[unstable(feature = "reborrow", issue = "145612")] +pub trait Reborrow { + /* compiler built-in */ +} + +/// Derive macro generating an impl of the trait `Reborrow`. +#[rustc_builtin_macro(Reborrow)] +#[allow_internal_unstable(reborrow)] +#[unstable(feature = "reborrow", issue = "145612")] +pub macro Reborrow($item:item) { + /* compiler built-in */ +} + +/// Allows reborrowable value to be reborrowed as shared, creating a copy +/// that disables the source for writes for the lifetime of the copy. +#[lang = "coerce_shared"] +#[unstable(feature = "reborrow", issue = "145612")] +pub trait CoerceShared: Reborrow { + /* compiler built-in */ +} + +/// Derive macro generating an impl of the trait `CoerceShared`. +/// +/// The shared target type must be specified with `#[coerce_shared(Target)]`. +#[rustc_builtin_macro(CoerceShared, attributes(coerce_shared))] +#[allow_internal_unstable(reborrow)] +#[unstable(feature = "reborrow", issue = "145612")] +pub macro CoerceShared($item:item) { + /* compiler built-in */ +} diff --git a/library/core/src/marker/variance.rs b/library/core/src/marker/variance.rs index 5fc62a5ad7ac2..9e135e89c451e 100644 --- a/library/core/src/marker/variance.rs +++ b/library/core/src/marker/variance.rs @@ -30,7 +30,7 @@ macro_rules! phantom_type { } } - impl self::sealed::Sealed for $name where T: ?Sized { + impl self::private_items::PrivateItems for $name where T: ?Sized { const VALUE: Self = Self::new(); } impl Variance for $name where T: ?Sized {} @@ -114,7 +114,7 @@ macro_rules! phantom_lifetime { } } - impl self::sealed::Sealed for $name<'_> { + impl self::private_items::PrivateItems for $name<'_> { const VALUE: Self = Self::new(); } impl Variance for $name<'_> {} @@ -233,14 +233,15 @@ phantom_type! { pub struct PhantomInvariant(PhantomData T>); } -mod sealed { - pub trait Sealed { +mod private_items { + #[unstable(feature = "std_internals", issue = "none")] + pub trait PrivateItems { const VALUE: Self; } } /// A marker trait for phantom variance types. -pub trait Variance: sealed::Sealed + Default {} +pub trait Variance: private_items::PrivateItems + Default {} /// Construct a variance marker; equivalent to [`Default::default`]. /// diff --git a/library/core/src/ptr/alignment.rs b/library/core/src/mem/alignment.rs similarity index 80% rename from library/core/src/ptr/alignment.rs rename to library/core/src/mem/alignment.rs index b14277428b557..4fb584327acd4 100644 --- a/library/core/src/ptr/alignment.rs +++ b/library/core/src/mem/alignment.rs @@ -17,7 +17,8 @@ use crate::{cmp, fmt, hash, mem, num}; /// Note that particularly large alignments, while representable in this type, /// are likely not to be supported by actual allocators and linkers. #[unstable(feature = "ptr_alignment_type", issue = "102070")] -#[derive(Copy, Clone, PartialEq, Eq)] +#[derive(Copy)] +#[derive_const(Clone, PartialEq, Eq)] #[repr(transparent)] // uses the field directly instead of .as_usize() to permit proving as_usize so that its proof // does not itself use as_usize @@ -46,7 +47,7 @@ impl Alignment { /// /// ``` /// #![feature(ptr_alignment_type)] - /// use std::ptr::Alignment; + /// use std::mem::Alignment; /// /// assert_eq!(Alignment::MIN.as_usize(), 1); /// ``` @@ -63,13 +64,18 @@ impl Alignment { #[requires(mem::align_of::().is_power_of_two())] #[ensures(|result| result.as_usize().is_power_of_two())] pub const fn of() -> Self { - // This can't actually panic since type alignment is always a power of two. - const { Alignment::new(align_of::()).unwrap() } + ::ALIGNMENT } /// Returns the [ABI]-required minimum alignment of the type of the value that `val` points to. /// - /// Every reference to a value of the type `T` must be a multiple of this number. + /// This function is identical to [`Alignment::of::()`][Self::of] whenever + /// T: [Sized], + /// but also supports determining the alignment required by a `dyn Trait` value, which is the + /// alignment of the underlying concrete type. + /// + /// This provides the same numerical value as [`align_of_val`], + /// but in an `Alignment` instead of a `usize`. /// /// [ABI]: https://en.wikipedia.org/wiki/Application_binary_interface /// @@ -77,10 +83,29 @@ impl Alignment { /// /// ``` /// #![feature(ptr_alignment_type)] - /// use std::ptr::Alignment; + /// use std::mem::Alignment; /// /// assert_eq!(Alignment::of_val(&5i32).as_usize(), 4); /// ``` + /// + /// (Caution: [it is not guaranteed][type-layout] that the alignment of `i32` is `4`; + /// that is, the above assertion does not pass on all platforms.) + /// + /// `dyn` types may have different alignments for different values; + /// `Alignment::of_val()` can be used to learn those alignments: + /// + /// ``` + /// #![feature(ptr_alignment_type)] + /// use std::mem::Alignment; + /// + /// let a: &dyn ToString = &1234u16; + /// let b: &dyn ToString = &String::from("abcd"); + /// + /// assert_eq!(Alignment::of_val(a), Alignment::of::()); + /// assert_eq!(Alignment::of_val(b), Alignment::of::()); + /// ``` + /// + /// [type-layout]: ../../reference/type-layout.html#r-layout.primitive #[inline] #[must_use] #[unstable(feature = "ptr_alignment_type", issue = "102070")] @@ -92,13 +117,17 @@ impl Alignment { /// Returns the [ABI]-required minimum alignment of the type of the value that `val` points to. /// - /// Every reference to a value of the type `T` must be a multiple of this number. + /// This function is identical to [`Alignment::of_val()`], except that it can be used with raw + /// pointers in situations where it would be unsound or undesirable to convert them to + /// [`&` references][primitive@reference] and impose the aliasing rules that come with that. /// /// [ABI]: https://en.wikipedia.org/wiki/Application_binary_interface /// /// # Safety /// - /// This function is only safe to call if the following conditions hold: + /// This function is safe to call if the pointer is safe to reborrow as `&T` + /// (in which case you could also call [`of_val`][Self::of_val]). + /// Otherwise, the following conditions must hold: /// /// - If `T` is `Sized`, this function is always safe to call. /// - If the unsized tail of `T` is: @@ -124,15 +153,18 @@ impl Alignment { /// /// ``` /// #![feature(ptr_alignment_type)] - /// #![feature(layout_for_ptr)] - /// use std::ptr::Alignment; + /// use std::mem::Alignment; /// /// assert_eq!(unsafe { Alignment::of_val_raw(&5i32) }.as_usize(), 4); /// ``` + /// + /// (Caution: [it is not guaranteed][type-layout] that the alignment of `i32` is `4`; + /// that is, the above assertion does not pass on all platforms.) + /// + /// [type-layout]: ../../reference/type-layout.html#r-layout.primitive #[inline] #[must_use] #[unstable(feature = "ptr_alignment_type", issue = "102070")] - // #[unstable(feature = "layout_for_ptr", issue = "69835")] pub const unsafe fn of_val_raw(val: *const T) -> Self { // SAFETY: precondition propagated to the caller let align = unsafe { mem::align_of_val_raw(val) }; @@ -188,20 +220,32 @@ impl Alignment { #[inline] #[ensures(|result| result.is_power_of_two())] pub const fn as_usize(self) -> usize { - // Going through `as_nonzero` helps this be more clearly the inverse of + // Going through `as_nonzero_usize` helps this be more clearly the inverse of // `new_unchecked`, letting MIR optimizations fold it away. - self.as_nonzero().get() + self.as_nonzero_usize().get() + } + + /// Returns the alignment as a [NonZero]<[usize]>. + #[unstable(feature = "ptr_alignment_type", issue = "102070")] + #[deprecated( + since = "1.96.0", + note = "renamed to `as_nonzero_usize`", + suggestion = "as_nonzero_usize" + )] + #[inline] + pub const fn as_nonzero(self) -> NonZero { + self.as_nonzero_usize() } /// Returns the alignment as a [NonZero]<[usize]>. #[unstable(feature = "ptr_alignment_type", issue = "102070")] #[inline] #[ensures(|result| result.get().is_power_of_two())] - // uses the field directly instead of self.as_usize(): as_usize's body calls as_nonzero, so - // referencing it here would make the contract instrumentation infinitely recursive + // uses the field directly instead of self.as_usize(): as_usize's body calls as_nonzero_usize, + // so referencing it here would make the contract instrumentation infinitely recursive #[ensures(|result| result.get() == self._inner_repr_trick as usize)] - pub const fn as_nonzero(self) -> NonZero { + pub const fn as_nonzero_usize(self) -> NonZero { // This transmutes directly to avoid the UbCheck in `NonZero::new_unchecked` // since there's no way for the user to trip that check anyway -- the // validity invariant of the type would have to have been broken earlier -- @@ -230,7 +274,7 @@ impl Alignment { #[ensures(|result| (*result as usize) < mem::size_of::() * 8)] #[ensures(|result| 1usize << *result == self.as_usize())] pub const fn log2(self) -> u32 { - self.as_nonzero().trailing_zeros() + self.as_nonzero_usize().trailing_zeros() } /// Returns a bit mask that can be used to match this alignment. @@ -240,9 +284,10 @@ impl Alignment { /// # Examples /// /// ``` - /// #![feature(ptr_alignment_type)] /// #![feature(ptr_mask)] - /// use std::ptr::{Alignment, NonNull}; + /// #![feature(ptr_alignment_type)] + /// use std::mem::Alignment; + /// use std::ptr::NonNull; /// /// #[repr(align(1))] struct Align1(u8); /// #[repr(align(2))] struct Align2(u16); @@ -275,13 +320,13 @@ impl Alignment { #[unstable(feature = "ptr_alignment_type", issue = "102070")] impl fmt::Debug for Alignment { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - write!(f, "{:?} (1 << {:?})", self.as_nonzero(), self.log2()) + write!(f, "{:?} (1 << {:?})", self.as_nonzero_usize(), self.log2()) } } #[unstable(feature = "ptr_alignment_type", issue = "102070")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const TryFrom> for Alignment { +const impl TryFrom> for Alignment { type Error = num::TryFromIntError; #[inline] @@ -292,27 +337,27 @@ impl const TryFrom> for Alignment { #[unstable(feature = "ptr_alignment_type", issue = "102070")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const TryFrom for Alignment { +const impl TryFrom for Alignment { type Error = num::TryFromIntError; #[inline] fn try_from(align: usize) -> Result { - Self::new(align).ok_or(num::TryFromIntError(())) + Self::new(align).ok_or(num::TryFromIntError(num::IntErrorKind::NotAPowerOfTwo)) } } #[unstable(feature = "ptr_alignment_type", issue = "102070")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for NonZero { +const impl From for NonZero { #[inline] fn from(align: Alignment) -> NonZero { - align.as_nonzero() + align.as_nonzero_usize() } } #[unstable(feature = "ptr_alignment_type", issue = "102070")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for usize { +const impl From for usize { #[inline] fn from(align: Alignment) -> usize { align.as_usize() @@ -320,15 +365,17 @@ impl const From for usize { } #[unstable(feature = "ptr_alignment_type", issue = "102070")] -impl cmp::Ord for Alignment { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +const impl cmp::Ord for Alignment { #[inline] fn cmp(&self, other: &Self) -> cmp::Ordering { - self.as_nonzero().get().cmp(&other.as_nonzero().get()) + self.as_nonzero_usize().cmp(&other.as_nonzero_usize()) } } #[unstable(feature = "ptr_alignment_type", issue = "102070")] -impl cmp::PartialOrd for Alignment { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +const impl cmp::PartialOrd for Alignment { #[inline] fn partial_cmp(&self, other: &Self) -> Option { Some(self.cmp(other)) @@ -339,21 +386,22 @@ impl cmp::PartialOrd for Alignment { impl hash::Hash for Alignment { #[inline] fn hash(&self, state: &mut H) { - self.as_nonzero().hash(state) + self.as_nonzero_usize().hash(state) } } /// Returns [`Alignment::MIN`], which is valid for any type. #[unstable(feature = "ptr_alignment_type", issue = "102070")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for Alignment { +const impl Default for Alignment { fn default() -> Alignment { Alignment::MIN } } #[cfg(target_pointer_width = "16")] -#[derive(Copy, Clone, PartialEq, Eq)] +#[derive(Copy)] +#[derive_const(Clone, PartialEq, Eq)] #[repr(usize)] #[cfg_attr(kani, derive(kani::Arbitrary))] enum AlignmentEnum { @@ -376,7 +424,8 @@ enum AlignmentEnum { } #[cfg(target_pointer_width = "32")] -#[derive(Copy, Clone, PartialEq, Eq)] +#[derive(Copy)] +#[derive_const(Clone, PartialEq, Eq)] #[repr(usize)] #[cfg_attr(kani, derive(kani::Arbitrary))] enum AlignmentEnum { @@ -415,7 +464,8 @@ enum AlignmentEnum { } #[cfg(target_pointer_width = "64")] -#[derive(Copy, Clone, PartialEq, Eq)] +#[derive(Copy)] +#[derive_const(Clone, PartialEq, Eq)] #[repr(usize)] #[cfg_attr(kani, derive(kani::Arbitrary))] enum AlignmentEnum { diff --git a/library/core/src/mem/drop_guard.rs b/library/core/src/mem/drop_guard.rs index 74bf353907455..8e6655f785466 100644 --- a/library/core/src/mem/drop_guard.rs +++ b/library/core/src/mem/drop_guard.rs @@ -109,31 +109,31 @@ where #[unstable(feature = "drop_guard", issue = "144426")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Deref for DropGuard +const impl Deref for DropGuard where F: FnOnce(T), { type Target = T; fn deref(&self) -> &T { - &*self.inner + &self.inner } } #[unstable(feature = "drop_guard", issue = "144426")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const DerefMut for DropGuard +const impl DerefMut for DropGuard where F: FnOnce(T), { fn deref_mut(&mut self) -> &mut T { - &mut *self.inner + &mut self.inner } } #[unstable(feature = "drop_guard", issue = "144426")] #[rustc_const_unstable(feature = "const_drop_guard", issue = "none")] -impl const Drop for DropGuard +const impl Drop for DropGuard where F: [const] FnOnce(T), { diff --git a/library/core/src/mem/manually_drop.rs b/library/core/src/mem/manually_drop.rs index ca008a82ee6f0..6c2f77a373393 100644 --- a/library/core/src/mem/manually_drop.rs +++ b/library/core/src/mem/manually_drop.rs @@ -43,13 +43,63 @@ use crate::ptr; /// } /// ``` /// -/// # Interaction with `Box` +/// # Safety hazards when storing `ManuallyDrop` in a struct or an enum. +/// +/// Special care is needed when all of the conditions below are met: +/// * A struct or enum contains a `ManuallyDrop`. +/// * The `ManuallyDrop` is not inside a `union`. +/// * The struct or enum is part of public API, or is stored in a struct or an +/// enum that is part of public API. +/// * There is a _safe_ function that drops the contents of the `ManuallyDrop` +/// field, and it can be called outside the struct or enum's `Drop` implementation. +/// +/// In particular, deriving `Debug`, `Clone`, `PartialEq`, `PartialOrd`, `Ord`, +/// or `Hash` on the struct or enum could be unsound, since the derived +/// implementations of these traits would access the `ManuallyDrop` field. +/// +/// For example, in the following code, `derive(Debug)` is unsound in combination +/// with the `ManuallyDrop::drop` call in `Foo::new`: +/// +/// ```no_run +/// # use std::mem::ManuallyDrop; +/// #[derive(Debug)] +/// pub struct Foo { +/// /// Invariant: this value may have been dropped! +/// value: ManuallyDrop, +/// } +/// impl Foo { +/// pub fn new() -> Self { +/// let mut temp = Self { +/// value: ManuallyDrop::new(String::from("Unsafe rust is hard.")) +/// }; +/// unsafe { +/// // SAFETY: `value` hasn't been dropped yet. +/// ManuallyDrop::drop(&mut temp.value); +/// } +/// temp +/// } +/// } +/// ``` +/// +/// As one could use the `Debug` implementation to access an already dropped +/// field: +/// +/// ```rust,ignore (uses-type-from-separate-snippet) +/// let foo = Foo::new(); +/// println!("{foo:?}"); // Undefined behavior! +/// ``` /// -/// Currently, if you have a `ManuallyDrop`, where the type `T` is a `Box` or -/// contains a `Box` inside, then dropping the `T` followed by moving the -/// `ManuallyDrop` is [considered to be undefined +/// Note that similar unsoundness can arise without `derive`. The cause of the +/// unsoundness are public APIs which allow to access an already dropped value +/// inside `ManuallyDrop`. +/// +/// # Pre-`1.96` Interaction with `Box` +/// +/// Before Rust `1.96.0`, if you had a `ManuallyDrop`, where the type `T` +/// was a `Box` or contained a `Box` inside, then dropping the `T` followed by +/// moving the `ManuallyDrop` was [considered to be undefined /// behavior](https://github.com/rust-lang/unsafe-code-guidelines/issues/245). -/// That is, the following code causes undefined behavior: +/// That is, the following code caused undefined behavior: /// /// ```no_run /// use std::mem::ManuallyDrop; @@ -58,31 +108,12 @@ use crate::ptr; /// unsafe { /// ManuallyDrop::drop(&mut x); /// } -/// let y = x; // Undefined behavior! +/// let y = x; // Undefined behavior! (pre 1.96.0) /// ``` /// -/// This is [likely to change in the -/// future](https://rust-lang.github.io/rfcs/3336-maybe-dangling.html). In the -/// meantime, consider using [`MaybeUninit`] instead. -/// -/// # Safety hazards when storing `ManuallyDrop` in a struct or an enum. -/// -/// Special care is needed when all of the conditions below are met: -/// * A struct or enum contains a `ManuallyDrop`. -/// * The `ManuallyDrop` is not inside a `union`. -/// * The struct or enum is part of public API, or is stored in a struct or an -/// enum that is part of public API. -/// * There is code that drops the contents of the `ManuallyDrop` field, and -/// this code is outside the struct or enum's `Drop` implementation. -/// -/// In particular, the following hazards may occur: -/// -/// #### Storing generic types -/// -/// If the `ManuallyDrop` contains a client-supplied generic type, the client -/// might provide a `Box` as that type. This would cause undefined behavior when -/// the struct or enum is later moved, as mentioned in the previous section. For -/// example, the following code causes undefined behavior: +/// Note that this could also have happen with a generic type where the user of +/// the library providing it could substitute the generic for a `Box<_>` and +/// then move the library type: /// /// ```no_run /// use std::mem::ManuallyDrop; @@ -101,7 +132,7 @@ use crate::ptr; /// self.is_some = false; /// unsafe { /// // SAFETY: `value` hasn't been dropped yet, as per the invariant -/// // (This is actually unsound!) +/// // (This is actually unsound pre rust 1.96.0!) /// ManuallyDrop::drop(&mut self.value); /// } /// } @@ -112,41 +143,7 @@ use crate::ptr; /// /// let mut option = BadOption::new(Box::new(42)); /// option.change_to_none(); -/// let option2 = option; // Undefined behavior! -/// ``` -/// -/// #### Deriving traits -/// -/// Deriving `Debug`, `Clone`, `PartialEq`, `PartialOrd`, `Ord`, or `Hash` on -/// the struct or enum could be unsound, since the derived implementations of -/// these traits would access the `ManuallyDrop` field. For example, the -/// following code causes undefined behavior: -/// -/// ```no_run -/// use std::mem::ManuallyDrop; -/// -/// // This derive is unsound in combination with the `ManuallyDrop::drop` call. -/// #[derive(Debug)] -/// pub struct Foo { -/// value: ManuallyDrop, -/// } -/// impl Foo { -/// pub fn new() -> Self { -/// let mut temp = Self { -/// value: ManuallyDrop::new(String::from("Unsafe rust is hard.")) -/// }; -/// unsafe { -/// // SAFETY: `value` hasn't been dropped yet. -/// ManuallyDrop::drop(&mut temp.value); -/// } -/// temp -/// } -/// } -/// -/// // In another crate: -/// -/// let foo = Foo::new(); -/// println!("{:?}", foo); // Undefined behavior! +/// let option2 = option; // Undefined behavior! (pre 1.96) /// ``` /// /// [drop order]: https://doc.rust-lang.org/reference/destructors.html @@ -181,6 +178,7 @@ impl ManuallyDrop { #[stable(feature = "manually_drop", since = "1.20.0")] #[rustc_const_stable(feature = "const_manually_drop", since = "1.32.0")] #[inline(always)] + #[rustc_no_writable] pub const fn new(value: T) -> ManuallyDrop { ManuallyDrop { value: MaybeDangling::new(value) } } @@ -270,7 +268,7 @@ impl ManuallyDrop { #[stable(feature = "manually_drop", since = "1.20.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Deref for ManuallyDrop { +const impl Deref for ManuallyDrop { type Target = T; #[inline(always)] fn deref(&self) -> &T { @@ -280,7 +278,7 @@ impl const Deref for ManuallyDrop { #[stable(feature = "manually_drop", since = "1.20.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const DerefMut for ManuallyDrop { +const impl DerefMut for ManuallyDrop { #[inline(always)] fn deref_mut(&mut self) -> &mut T { self.value.as_mut() diff --git a/library/core/src/mem/maybe_dangling.rs b/library/core/src/mem/maybe_dangling.rs index a5f77e667f975..46e5228a2da3f 100644 --- a/library/core/src/mem/maybe_dangling.rs +++ b/library/core/src/mem/maybe_dangling.rs @@ -1,13 +1,10 @@ #![unstable(feature = "maybe_dangling", issue = "118166")] +use crate::marker::StructuralPartialEq; use crate::{mem, ptr}; /// Allows wrapped [references] and [boxes] to dangle. /// -///

-/// This type is not properly implemented yet, and the documentation below is thus not accurate. -///
-/// /// That is, if a reference (or a `Box`) is wrapped in `MaybeDangling` (including when in a /// (nested) field of a compound type wrapped in `MaybeDangling`), it does not have to follow /// pointer aliasing rules or be dereferenceable. @@ -16,7 +13,6 @@ use crate::{mem, ptr}; /// executing (particularly in concurrent code). As a somewhat absurd example, consider this code: /// /// ```rust,no_run -/// #![feature(box_as_ptr)] /// # use std::alloc::{dealloc, Layout}; /// # use std::mem; /// @@ -38,7 +34,7 @@ use crate::{mem, ptr}; /// // FIXME: remove `no_run` once the semantics are actually implemented /// ```rust,no_run -/// #![feature(maybe_dangling, box_as_ptr)] +/// #![feature(maybe_dangling)] /// # use std::alloc::{dealloc, Layout}; /// # use std::mem::{self, MaybeDangling}; /// @@ -73,10 +69,12 @@ use crate::{mem, ptr}; #[repr(transparent)] #[rustc_pub_transparent] #[derive(Debug, Copy, Clone, Default)] +#[lang = "maybe_dangling"] pub struct MaybeDangling(P); impl MaybeDangling

{ /// Wraps a value in a `MaybeDangling`, allowing it to dangle. + #[rustc_no_writable] pub const fn new(x: P) -> Self where P: Sized, @@ -112,3 +110,5 @@ impl MaybeDangling

{ x } } + +impl StructuralPartialEq for MaybeDangling {} diff --git a/library/core/src/mem/maybe_uninit.rs b/library/core/src/mem/maybe_uninit.rs index 320eb97f83a43..94703940baa1f 100644 --- a/library/core/src/mem/maybe_uninit.rs +++ b/library/core/src/mem/maybe_uninit.rs @@ -1,18 +1,18 @@ use crate::any::type_name; use crate::clone::TrivialClone; use crate::marker::Destruct; -use crate::mem::ManuallyDrop; +use crate::mem::{ManuallyDrop, transmute_neo}; use crate::{fmt, intrinsics, ptr, slice}; /// A wrapper type to construct uninitialized instances of `T`. /// /// # Initialization invariant /// -/// The compiler, in general, assumes that a variable is properly initialized +/// The compiler, in general, assumes that a variable is [properly initialized or "valid"][validity] /// according to the requirements of the variable's type. For example, a variable of /// reference type must be aligned and non-null. This is an invariant that must /// *always* be upheld, even in unsafe code. As a consequence, zero-initializing a -/// variable of reference type causes instantaneous [undefined behavior][ub], +/// variable of reference type causes instantaneous undefined behavior, /// no matter whether that reference ever gets used to access memory: /// /// ```rust,no_run @@ -53,6 +53,11 @@ use crate::{fmt, intrinsics, ptr, slice}; /// // The equivalent code with `MaybeUninit`: /// let x: i32 = unsafe { MaybeUninit::uninit().assume_init() }; // undefined behavior! ⚠️ /// ``` +/// +/// Conversely, sometimes it is okay to not initialize *all* bytes of a `MaybeUninit` +/// before calling `assume_init`. For instance, padding bytes do not have to be initialized. +/// See the field-by-field struct initialization example below for a case of that. +/// /// On top of that, remember that most types have additional invariants beyond merely /// being considered initialized at the type level. For example, a `1`-initialized [`Vec`] /// is considered initialized (under the current implementation; this does not constitute @@ -197,7 +202,12 @@ use crate::{fmt, intrinsics, ptr, slice}; /// ); /// ``` /// [`&raw mut`]: https://doc.rust-lang.org/reference/types/pointer.html#r-type.pointer.raw.constructor -/// [ub]: ../../reference/behavior-considered-undefined.html +/// [validity]: ../../reference/behavior-considered-undefined.html#r-undefined.validity +/// +/// Note that we have not initialized the padding, but that's fine -- it does not have to be +/// initialized. In fact, even if we had initialized the padding in `uninit`, those bytes would be +/// lost when copying the result: no matter the contents of the padding bytes in `uninit`, they will +/// always be uninitialized in `foo`. /// /// # Layout /// @@ -427,7 +437,8 @@ impl MaybeUninit { /// be null. /// /// Note that if `T` has padding bytes, those bytes are *not* preserved when the - /// `MaybeUninit` value is returned from this function, so those bytes will *not* be zeroed. + /// `MaybeUninit` value is returned from this function, so those bytes are not + /// guaranteed to be zeroed. /// /// Note that dropping a `MaybeUninit` will never call `T`'s drop code. /// It is your responsibility to make sure `T` gets dropped if it got initialized. @@ -657,11 +668,18 @@ impl MaybeUninit { /// # Safety /// /// It is up to the caller to guarantee that the `MaybeUninit` really is in an initialized - /// state. Calling this when the content is not yet fully initialized causes immediate undefined - /// behavior. The [type-level documentation][inv] contains more information about - /// this initialization invariant. + /// state, i.e., a state that is considered ["valid" for type `T`][validity]. Calling this when + /// the content is not yet fully initialized causes immediate undefined behavior. The + /// [type-level documentation][inv] contains more information about this initialization + /// invariant. + /// + /// It is a common mistake to assume that this function is safe to call on integers because they + /// can hold all bit patterns. It is also a common mistake to think that calling this function + /// is UB if any byte is uninitialized. Both of these assumptions are wrong. If that is + /// surprising to you, please read the [type-level documentation][inv]. /// /// [inv]: #initialization-invariant + /// [validity]: ../../reference/behavior-considered-undefined.html#r-undefined.validity /// /// On top of that, remember that most types have additional invariants beyond merely /// being considered initialized at the type level. For example, a `1`-initialized [`Vec`] @@ -689,12 +707,13 @@ impl MaybeUninit { /// *Incorrect* usage of this method: /// /// ```rust,no_run + /// # #![allow(invalid_value)] /// use std::mem::MaybeUninit; /// - /// let x = MaybeUninit::>::uninit(); - /// let x_init = unsafe { x.assume_init() }; - /// // `x` had not been initialized yet, so this last line caused undefined behavior. ⚠️ + /// let x: i32 = unsafe { MaybeUninit::uninit().assume_init() }; // undefined behavior! ⚠️ /// ``` + /// + /// See the [type-level documentation][#examples] for more examples. #[stable(feature = "maybe_uninit", since = "1.36.0")] #[rustc_const_stable(feature = "const_maybe_uninit_assume_init_by_value", since = "1.59.0")] #[inline(always)] @@ -705,9 +724,9 @@ impl MaybeUninit { // This also means that `self` must be a `value` variant. unsafe { intrinsics::assert_inhabited::(); - // We do this via a raw ptr read instead of `ManuallyDrop::into_inner` so that there's + // We do this via a transmute instead of `ManuallyDrop::into_inner` so that there's // no trace of `ManuallyDrop` in Miri's error messages here. - (&raw const self.value).cast::().read() + transmute_neo(self) } } @@ -1267,8 +1286,8 @@ impl [MaybeUninit] { /// Fills a slice with elements returned by calling a closure for each index. /// /// This method uses a closure to create new values. If you'd rather `Clone` a given value, use - /// [slice::write_filled]. If you want to use the `Default` trait to generate values, you can - /// pass [`|_| Default::default()`][Default::default] as the argument. + /// [`slice::write_filled`]. If you want to use the `Default` trait to generate values, use + /// [`slice::write_default`]. /// /// # Panics /// @@ -1305,6 +1324,73 @@ impl [MaybeUninit] { unsafe { self.assume_init_mut() } } + /// Fills a slice with elements returned by calling [`Default::default`] for each index. + /// + /// # Panics + /// + /// This function will panic if any call to [`Default::default`] panics. + /// + /// If such a panic occurs, any elements previously initialized during this operation will be + /// dropped. + /// + /// # Examples + /// + /// ``` + /// #![feature(maybe_uninit_fill)] + /// use std::mem::MaybeUninit; + /// + /// let mut buf = [const { MaybeUninit::::uninit() }; 5]; + /// let initialized = buf.write_default(); + /// assert_eq!(initialized, &mut [0, 0, 0, 0, 0]); + /// ``` + #[unstable(feature = "maybe_uninit_fill", issue = "117428")] + pub fn write_default(&mut self) -> &mut [T] + where + T: Default, + { + trait DefaultSpec: Default { + fn write_default(buf: &mut [MaybeUninit]) -> &mut [Self]; + } + + impl DefaultSpec for T { + default fn write_default(buf: &mut [MaybeUninit]) -> &mut [Self] { + buf.write_with(|_| T::default()) + } + } + + macro_rules! spec_default_zero { + ($ty:ty) => { + impl DefaultSpec for $ty { + fn write_default(buf: &mut [MaybeUninit]) -> &mut [Self] { + // SAFETY: + // `Default::default` is equivalent to zero-initialization + // for all these types, and this initializes the entire + // slice. + unsafe { + buf.as_mut_ptr().write_bytes(0, buf.len()); + buf.assume_init_mut() + } + } + } + }; + } + + spec_default_zero!(i8); + spec_default_zero!(u8); + spec_default_zero!(i16); + spec_default_zero!(u16); + spec_default_zero!(i32); + spec_default_zero!(u32); + spec_default_zero!(i64); + spec_default_zero!(u64); + spec_default_zero!(i128); + spec_default_zero!(u128); + spec_default_zero!(isize); + spec_default_zero!(usize); + + T::write_default(self) + } + /// Fills a slice with elements yielded by an iterator until either all elements have been /// initialized or the iterator is empty. /// @@ -1532,6 +1618,56 @@ impl MaybeUninit<[T; N]> { } } +#[stable(feature = "more_conversion_trait_impls", since = "1.95.0")] +impl From<[MaybeUninit; N]> for MaybeUninit<[T; N]> { + #[inline] + fn from(arr: [MaybeUninit; N]) -> Self { + arr.transpose() + } +} + +#[stable(feature = "more_conversion_trait_impls", since = "1.95.0")] +impl AsRef<[MaybeUninit; N]> for MaybeUninit<[T; N]> { + #[inline] + fn as_ref(&self) -> &[MaybeUninit; N] { + // SAFETY: T and MaybeUninit have the same layout + unsafe { &*ptr::from_ref(self).cast() } + } +} + +#[stable(feature = "more_conversion_trait_impls", since = "1.95.0")] +impl AsRef<[MaybeUninit]> for MaybeUninit<[T; N]> { + #[inline] + fn as_ref(&self) -> &[MaybeUninit] { + AsRef::<[MaybeUninit; N]>::as_ref(self) + } +} + +#[stable(feature = "more_conversion_trait_impls", since = "1.95.0")] +impl AsMut<[MaybeUninit; N]> for MaybeUninit<[T; N]> { + #[inline] + fn as_mut(&mut self) -> &mut [MaybeUninit; N] { + // SAFETY: T and MaybeUninit have the same layout + unsafe { &mut *ptr::from_mut(self).cast() } + } +} + +#[stable(feature = "more_conversion_trait_impls", since = "1.95.0")] +impl AsMut<[MaybeUninit]> for MaybeUninit<[T; N]> { + #[inline] + fn as_mut(&mut self) -> &mut [MaybeUninit] { + &mut *AsMut::<[MaybeUninit; N]>::as_mut(self) + } +} + +#[stable(feature = "more_conversion_trait_impls", since = "1.95.0")] +impl From> for [MaybeUninit; N] { + #[inline] + fn from(arr: MaybeUninit<[T; N]>) -> Self { + arr.transpose() + } +} + impl [MaybeUninit; N] { /// Transposes a `[MaybeUninit; N]` into a `MaybeUninit<[T; N]>`. /// diff --git a/library/core/src/mem/mod.rs b/library/core/src/mem/mod.rs index d38b51da02829..8ec99013d25fe 100644 --- a/library/core/src/mem/mod.rs +++ b/library/core/src/mem/mod.rs @@ -1,19 +1,49 @@ -//! Basic functions for dealing with memory. +//! Basic functions for dealing with memory, values, and types. //! -//! This module contains functions for querying the size and alignment of -//! types, initializing and manipulating memory. +//! The contents of this module can be seen as belonging to a few families: +//! +//! * [`drop`], [`replace`], [`swap`], and [`take`] +//! are safe functions for moving values in particular ways. +//! They are useful in everyday Rust code. +//! +//! * [`size_of`], [`size_of_val`], [`align_of`], [`align_of_val`], and [`offset_of`] +//! give information about the representation of values in memory. +//! +//! * [`discriminant`] +//! allows comparing the variants of [`enum`] values while ignoring their fields. +//! +//! * [`forget`] and [`ManuallyDrop`] +//! prevent destructors from running, which is used in certain kinds of ownership transfer. +//! [`needs_drop`] +//! tells you whether a type’s destructor even does anything. +//! +//! * [`transmute`], [`transmute_copy`], and [`MaybeUninit`] +//! convert and construct values in [`unsafe`] ways. +//! +//! See also the [`alloc`] and [`ptr`] modules for more primitive operations on memory. +//! +// core::alloc exists but doesn’t contain all the items we want to discuss +//! [`alloc`]: ../../std/alloc/index.html +//! [`enum`]: ../../std/keyword.enum.html +//! [`ptr`]: crate::ptr +//! [`unsafe`]: ../../std/keyword.unsafe.html #![stable(feature = "rust1", since = "1.0.0")] use crate::alloc::Layout; use crate::clone::TrivialClone; +use crate::cmp::Ordering; #[cfg(kani)] use crate::kani; use crate::marker::{Destruct, DiscriminantKind}; use crate::panic::const_assert; -use crate::ptr::Alignment; +use crate::ub_checks::assert_unsafe_precondition; use crate::{clone, cmp, fmt, hash, intrinsics, ptr}; +mod alignment; +#[unstable(feature = "ptr_alignment_type", issue = "102070")] +pub use alignment::Alignment; + mod manually_drop; #[stable(feature = "manually_drop", since = "1.20.0")] pub use manually_drop::ManuallyDrop; @@ -159,6 +189,7 @@ pub mod type_info; #[rustc_const_stable(feature = "const_forget", since = "1.46.0")] #[stable(feature = "rust1", since = "1.0.0")] #[rustc_diagnostic_item = "mem_forget"] +#[rustc_no_writable] pub const fn forget(t: T) { let _ = ManuallyDrop::new(t); } @@ -344,6 +375,13 @@ pub fn forget_unsized(t: T) { #[rustc_const_stable(feature = "const_mem_size_of", since = "1.24.0")] #[rustc_diagnostic_item = "mem_size_of"] pub const fn size_of() -> usize { + // By making this a constant, we also guarantee that the constant can be successfully evaluated + // in any program execution that actually executes `size_of`. Which is relevant because the + // constant can fail to evaluate if the type is too big. Someone might do something cursed where + // soundness relies on a certain type not being too big, and they check that by just invoking + // size_of on the type to ensure it exists, so if we fully DCE'd size_of calls that would be + // considered unsound... but by making this a constant, it participates in the usual "required + // consts" system, and we are safe. ::SIZE } @@ -384,12 +422,13 @@ pub const fn size_of_val(val: &T) -> usize { /// /// # Safety /// -/// This function is only safe to call if the following conditions hold: +/// This function is safe to call if the pointer is safe to reborrow as `&T` +/// (in which case you could also call [`size_of_val`]). +/// Otherwise, the following conditions must hold: /// /// - If `T` is `Sized`, this function is always safe to call. -/// - If the unsized tail of `T` is: -/// - a [slice], then the length of the slice tail must be an initialized -/// integer, and the size of the *entire value* +/// - If the *unsized tail* of `T` is: +/// - a [slice] `[U]`, `str`, or a [trait object] `dyn Trait`, then the size of the *entire value* /// (dynamic tail length + statically sized prefix) must fit in `isize`. /// For the special case where the dynamic tail length is 0, this function /// is safe to call. @@ -397,15 +436,15 @@ pub const fn size_of_val(val: &T) -> usize { // then we would stop compilation as even the "statically known" part of the type would // already be too big (or the call may be in dead code and optimized away, but then it // doesn't matter). -/// - a [trait object], then the vtable part of the pointer must point -/// to a valid vtable acquired by an unsizing coercion, and the size -/// of the *entire value* (dynamic tail length + statically sized prefix) -/// must fit in `isize`. -/// - an (unstable) [extern type], then this function is always safe to -/// call, but may panic or otherwise return the wrong value, as the -/// extern type's layout is not known. This is the same behavior as -/// [`size_of_val`] on a reference to a type with an extern type tail. -/// - otherwise, it is conservatively not allowed to call this function. +/// - No other kind of unsized tail currently exists that satisfies the trait bounds for this +/// function. If more kinds of unsized tails get introduced in the future, the documentation +/// of this function will have to be extended before it can be used for such types. +/// +/// Here, *unsized tail* refers to the type obtained by recursively descending through the last +/// field of a tuple or struct until we arrived at a built-in unsized type. +/// +/// As a consequence of these rules, it is the case that whenever it is allowed to convert `val` +/// into a shared reference, then it is also allowed to invoke this function. /// /// [`size_of::()`]: size_of /// [trait object]: ../../book/ch17-02-trait-objects.html @@ -414,7 +453,6 @@ pub const fn size_of_val(val: &T) -> usize { /// # Examples /// /// ``` -/// #![feature(layout_for_ptr)] /// use std::mem; /// /// assert_eq!(4, size_of_val(&5i32)); @@ -425,7 +463,8 @@ pub const fn size_of_val(val: &T) -> usize { /// ``` #[inline] #[must_use] -#[unstable(feature = "layout_for_ptr", issue = "69835")] +#[stable(feature = "layout_for_ptr", since = "1.99.0")] +#[rustc_const_stable(feature = "layout_for_ptr", since = "1.99.0")] pub const unsafe fn size_of_val_raw(val: *const T) -> usize { // SAFETY: the caller must provide a valid raw pointer unsafe { intrinsics::size_of_val(val) } @@ -479,7 +518,7 @@ pub fn min_align_of_val(val: &T) -> usize { unsafe { intrinsics::align_of_val(val) } } -/// Returns the [ABI]-required minimum alignment of a type in bytes. +/// Returns the [ABI]-required minimum alignment of a type, in bytes. /// /// Every reference to a value of the type `T` must be a multiple of this number. /// @@ -492,6 +531,11 @@ pub fn min_align_of_val(val: &T) -> usize { /// ``` /// assert_eq!(4, align_of::()); /// ``` +/// +/// (Caution: [it is not guaranteed][type-layout] that the alignment of `i32` is `4`; +/// that is, the above assertion does not pass on all platforms.) +/// +/// [type-layout]: ../../reference/type-layout.html#r-layout.primitive #[inline(always)] #[must_use] #[stable(feature = "rust1", since = "1.0.0")] @@ -502,10 +546,12 @@ pub const fn align_of() -> usize { ::ALIGN } -/// Returns the [ABI]-required minimum alignment of the type of the value that `val` points to in +/// Returns the [ABI]-required minimum alignment of the type of the value that `val` points to, in /// bytes. /// -/// Every reference to a value of the type `T` must be a multiple of this number. +/// This function is identical to [`align_of::()`][align_of] whenever T: [Sized], +/// but also supports determining the alignment required by a `dyn Trait` value, which is the +/// alignment of the underlying concrete type. /// /// [ABI]: https://en.wikipedia.org/wiki/Application_binary_interface /// @@ -514,6 +560,22 @@ pub const fn align_of() -> usize { /// ``` /// assert_eq!(4, align_of_val(&5i32)); /// ``` +/// +/// (Caution: [it is not guaranteed][type-layout] that the alignment of `i32` is `4`; +/// that is, this example assertion does not pass on all platforms.) +/// +/// `dyn` types may have different alignments for different values; +/// `align_of_val` can be used to learn those alignments: +/// +/// ``` +/// let a: &dyn ToString = &1234u16; +/// let b: &dyn ToString = &String::from("abcd"); +/// +/// assert_eq!(align_of_val(a), align_of::()); +/// assert_eq!(align_of_val(b), align_of::()); +/// ``` +/// +/// [type-layout]: ../../reference/type-layout.html#r-layout.primitive #[inline] #[must_use] #[stable(feature = "rust1", since = "1.0.0")] @@ -523,33 +585,40 @@ pub const fn align_of_val(val: &T) -> usize { unsafe { intrinsics::align_of_val(val) } } -/// Returns the [ABI]-required minimum alignment of the type of the value that `val` points to in +/// Returns the [ABI]-required minimum alignment of the type of the value that `val` points to, in /// bytes. /// -/// Every reference to a value of the type `T` must be a multiple of this number. +/// This function is identical to [`align_of_val()`], except that it can be used with raw pointers +/// in situations where it would be unsound or undesirable to convert them to +/// [`&` references][primitive@reference] and impose the aliasing rules that come with that. /// /// [ABI]: https://en.wikipedia.org/wiki/Application_binary_interface /// /// # Safety /// -/// This function is only safe to call if the following conditions hold: +/// This function is safe to call if the pointer is safe to reborrow as `&T` +/// (in which case you could also call [`align_of_val`]). +/// Otherwise, the following conditions must hold: /// /// - If `T` is `Sized`, this function is always safe to call. /// - If the unsized tail of `T` is: -/// - a [slice], then the length of the slice tail must be an initialized -/// integer, and the size of the *entire value* +/// - a [slice] `[U]`, `str`, or a [trait object] `dyn Trait`, then the size of the *entire value* /// (dynamic tail length + statically sized prefix) must fit in `isize`. /// For the special case where the dynamic tail length is 0, this function /// is safe to call. -/// - a [trait object], then the vtable part of the pointer must point -/// to a valid vtable acquired by an unsizing coercion, and the size -/// of the *entire value* (dynamic tail length + statically sized prefix) -/// must fit in `isize`. -/// - an (unstable) [extern type], then this function is always safe to -/// call, but may panic or otherwise return the wrong value, as the -/// extern type's layout is not known. This is the same behavior as -/// [`align_of_val`] on a reference to a type with an extern type tail. -/// - otherwise, it is conservatively not allowed to call this function. +// NOTE: the reason this is safe is that if an overflow were to occur already with size 0, +// then we would stop compilation as even the "statically known" part of the type would +// already be too big (or the call may be in dead code and optimized away, but then it +// doesn't matter). +/// - No other kind of unsized tail currently exists that satisfies the trait bounds for this +/// function. If more kinds of unsized tails get introduced in the future, the documentation +/// of this function will have to be extended before it can be used for such types. +/// +/// Here, *unsized tail* refers to the type obtained by recursively descending through the last +/// field of a tuple or struct until we arrived at a built-in unsized type. +/// +/// As a consequence of these rules, it is the case that whenever it is allowed to convert `val` +/// into a shared reference, then it is also allowed to invoke this function. /// /// [trait object]: ../../book/ch17-02-trait-objects.html /// [extern type]: ../../unstable-book/language-features/extern-types.html @@ -557,14 +626,19 @@ pub const fn align_of_val(val: &T) -> usize { /// # Examples /// /// ``` -/// #![feature(layout_for_ptr)] /// use std::mem; /// /// assert_eq!(4, unsafe { mem::align_of_val_raw(&5i32) }); /// ``` +/// +/// (Caution: [it is not guaranteed][type-layout] that the alignment of `i32` is `4`; +/// that is, the above assertion does not pass on all platforms.) +/// +/// [type-layout]: ../../reference/type-layout.html#r-layout.primitive #[inline] #[must_use] -#[unstable(feature = "layout_for_ptr", issue = "69835")] +#[stable(feature = "layout_for_ptr", since = "1.99.0")] +#[rustc_const_stable(feature = "layout_for_ptr", since = "1.99.0")] pub const unsafe fn align_of_val_raw(val: *const T) -> usize { // SAFETY: the caller must provide a valid raw pointer unsafe { intrinsics::align_of_val(val) } @@ -1015,6 +1089,27 @@ pub const fn copy(x: &T) -> T { /// /// [ub]: ../../reference/behavior-considered-undefined.html /// +/// If you have a raw pointer instead of a reference, you might be looking for +/// `src.cast::().`[`read_unaligned()`](pointer#method.read_unaligned) instead. +/// +/// # Safety +/// +/// - Requires `size_of_val::(src) >= size_of::()` +/// - The first `size_of::()` bytes behind `src` must be *readable* +/// - The first `size_of::()` bytes behind `src` must be *[valid]* +/// when interpreted as a `Dst`. +/// +/// On top of that, remember that most types have additional invariants beyond merely +/// being considered initialized at the type level. For example, a `1`-initialized [`Vec`] +/// is considered initialized (under the current implementation; this does not constitute +/// a stable guarantee) because the only requirement the compiler knows about it +/// is that the data pointer must be non-null. Creating such a `Vec` does not cause +/// *immediate* undefined behavior, but will cause undefined behavior with most +/// safe operations (including dropping it). +/// +/// [valid]: ../../reference/behavior-considered-undefined.html#r-undefined.validity +/// [`Vec`]: ../../std/vec/struct.Vec.html +/// /// # Examples /// /// ``` @@ -1039,20 +1134,32 @@ pub const fn copy(x: &T) -> T { /// /// // The contents of 'foo_array' should not have changed /// assert_eq!(foo_array, [10]); +/// +/// let bytes: &[u8] = &[1, 2, 3, 4, 5, 6, 7]; +/// assert_eq!( +/// unsafe { mem::transmute_copy::<[u8], u32>(bytes) }, +/// u32::from_ne_bytes(*bytes.first_chunk().unwrap()), +/// ); /// ``` #[inline] #[must_use] #[track_caller] #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_stable(feature = "const_transmute_copy", since = "1.74.0")] -pub const unsafe fn transmute_copy(src: &Src) -> Dst { - assert!( - size_of::() >= size_of::(), - "cannot transmute_copy if Dst is larger than Src" +pub const unsafe fn transmute_copy(src: &Src) -> Dst { + // library UB because it's possible for the `Src` to be only a subset of the allocation + // and thus for a failure to not be immediate language UB + assert_unsafe_precondition!( + check_library_ub, + "cannot transmute_copy if Dst is larger than Src", + ( + src_size: usize = size_of_val::(src), + dst_size: usize = Dst::SIZE, + ) => src_size >= dst_size ); // If Dst has a higher alignment requirement, src might not be suitably aligned. - if align_of::() > align_of::() { + if align_of::() > align_of_val::(src) { // SAFETY: `src` is a reference which is guaranteed to be valid for reads. // The caller must guarantee that the actual transmutation is safe. unsafe { ptr::read_unaligned(src as *const Src as *const Dst) } @@ -1064,6 +1171,109 @@ pub const unsafe fn transmute_copy(src: &Src) -> Dst { } } +/// Like [`transmute`], but only initializes the "common prefix" of the first +/// `min(size_of::(), size_of::())` bytes of the destination from the +/// corresponding bytes of the source. +/// +/// This is equivalent to a "union cast" through a `union` with `#[repr(C)]`. +/// +/// That means some size mismatches are not UB, like `[T; 2]` to `[T; 1]`. +/// Increasing size is usually UB from being insufficiently initialized -- like +/// `u8` to `u32` -- but isn't always. For example, going from `u8` to +/// `#[repr(C, align(4))] AlignedU8(u8);` is sound. +/// +/// Prefer normal `transmute` where possible, for the extra checking, since +/// both do exactly the same thing at runtime, if they both compile. +/// +/// # Safety +/// +/// If `size_of::() >= size_of::()`, the first `size_of::()` bytes +/// of `src` must be be *valid* when interpreted as a `Dst`. (In this case, the +/// preconditions are the same as for `transmute_copy(&ManuallyDrop::new(src))`.) +/// +/// If `size_of::() <= size_of::()`, the bytes of `src` padded with +/// uninitialized bytes afterwards up to a total size of `size_of::()` +/// must be *valid* when interpreted as a `Dst`. +/// +/// In both cases, any safety preconditions of the `Dst` type must also be upheld. +/// +/// # Examples +/// +/// ``` +/// #![feature(transmute_prefix)] +/// use std::mem::transmute_prefix; +/// +/// assert_eq!(unsafe { transmute_prefix::<[i32; 4], [i32; 2]>([1, 2, 3, 4]) }, [1, 2]); +/// +/// let expected = if cfg!(target_endian = "little") { 0x34 } else { 0x12 }; +/// assert_eq!(unsafe { transmute_prefix::(0x1234) }, expected); +/// +/// // Would be UB because the destination is incompletely initialized. +/// // transmute_prefix::(123) +/// +/// // OK because the destination is allowed to be partially initialized. +/// let _: std::mem::MaybeUninit = unsafe { transmute_prefix(123_u8) }; +/// ``` +#[unstable(feature = "transmute_prefix", issue = "155079")] +#[rustc_no_writable] +pub const unsafe fn transmute_prefix(src: Src) -> Dst { + #[repr(C)] + union Transmute { + a: ManuallyDrop, + b: ManuallyDrop, + } + + match const { Ord::cmp(&Src::SIZE, &Dst::SIZE) } { + // SAFETY: When Dst is bigger, the union is the size of Dst + Ordering::Less => unsafe { + let a = transmute_neo(src); + intrinsics::transmute_unchecked(Transmute:: { a }) + }, + // SAFETY: When they're the same size, we can use the MIR primitive + Ordering::Equal => unsafe { intrinsics::transmute_unchecked::(src) }, + // SAFETY: When Src is bigger, the union is the size of Src + Ordering::Greater => unsafe { + let u: Transmute = intrinsics::transmute_unchecked(src); + transmute_neo(u.b) + }, + } +} + +/// New version of `transmute`, exposed under this name so it can be iterated upon +/// without risking breakage to uses of "real" transmute. +/// +/// Uses a `const`-`assert` to check the sizes instead of typeck hacks, +/// but is semantially identical to `transmute` otherwise. +/// +/// It will not be stabilized under this name. +/// +/// # Examples +/// +/// ``` +/// #![feature(transmute_neo)] +/// use std::mem::transmute_neo; +/// +/// assert_eq!(unsafe { transmute_neo::(0.0) }, 0); +/// ``` +/// +/// ```compile_fail,E0080 +/// #![feature(transmute_neo)] +/// use std::mem::transmute_neo; +/// +/// unsafe { transmute_neo::(123) }; +/// ``` +#[unstable(feature = "transmute_neo", issue = "155079")] +#[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces +#[inline] +#[rustc_no_writable] +pub const unsafe fn transmute_neo(src: Src) -> Dst { + const { assert!(Src::SIZE == Dst::SIZE) }; + + // SAFETY: the const-assert just checked that they're the same size, + // and any other safety invariants need to be upheld by the caller. + unsafe { intrinsics::transmute_unchecked(src) } +} + /// Opaque type representing the discriminant of an enum. /// /// See the [`discriminant`] function in this module for more information. @@ -1264,7 +1474,10 @@ pub trait SizedTypeProperties: Sized { #[doc(hidden)] #[unstable(feature = "ptr_alignment_type", issue = "102070")] - const ALIGNMENT: Alignment = Alignment::of::(); + const ALIGNMENT: Alignment = { + // This can't panic since type alignment is always a power of two. + Alignment::new(Self::ALIGN).unwrap() + }; /// `true` if this type requires no storage. /// `false` if its [size](size_of) is greater than zero. @@ -1443,10 +1656,14 @@ impl SizedTypeProperties for T {} /// [`offset_of_enum`]: https://doc.rust-lang.org/nightly/unstable-book/language-features/offset-of-enum.html /// [`offset_of_slice`]: https://doc.rust-lang.org/nightly/unstable-book/language-features/offset-of-slice.html #[stable(feature = "offset_of", since = "1.77.0")] +#[diagnostic::on_unmatched_args( + note = "this macro expects a container type and a (nested) field path, like `offset_of!(Type, field)`" +)] +#[doc(alias = "memoffset")] #[allow_internal_unstable(builtin_syntax, core_intrinsics)] +#[diagnostic::opaque] pub macro offset_of($Container:ty, $($fields:expr)+ $(,)?) { - // The `{}` is for better error messages - const {builtin # offset_of($Container, $($fields)+)} + const { builtin # offset_of($Container, $($fields)+) } } /// Create a fresh instance of the inhabited ZST type `T`. @@ -1489,12 +1706,13 @@ pub macro offset_of($Container:ty, $($fields:expr)+ $(,)?) { /// /// [inhabited]: https://doc.rust-lang.org/reference/glossary.html#inhabited #[unstable(feature = "mem_conjure_zst", issue = "95383")] +#[rustc_const_unstable(feature = "mem_conjure_zst", issue = "95383")] pub const unsafe fn conjure_zst() -> T { const_assert!( - size_of::() == 0, - "mem::conjure_zst invoked on a nonzero-sized type", - "mem::conjure_zst invoked on type {t}, which is not zero-sized", - t: &str = stringify!(T) + T::IS_ZST, + "mem::conjure_zst invoked on a non-zero-sized type", + "mem::conjure_zst invoked on type {name}, which is not zero-sized", + name: &str = crate::any::type_name::() ); // SAFETY: because the caller must guarantee that it's inhabited and zero-sized, diff --git a/library/core/src/mem/type_info.rs b/library/core/src/mem/type_info.rs index 8b30803c97c98..2f38f9b77faf4 100644 --- a/library/core/src/mem/type_info.rs +++ b/library/core/src/mem/type_info.rs @@ -2,7 +2,10 @@ //! runtime or const-eval processable way. use crate::any::TypeId; -use crate::intrinsics::type_of; +use crate::fmt; +use crate::intrinsics::{self, type_id, type_of}; +use crate::marker::PointeeSized; +use crate::ptr::DynMetadata; /// Compile-time type information. #[derive(Debug)] @@ -12,8 +15,20 @@ use crate::intrinsics::type_of; pub struct Type { /// Per-type information pub kind: TypeKind, - /// Size of the type. `None` if it is unsized - pub size: Option, +} + +/// Info of a trait implementation, you can retrieve the vtable with [Self::get_vtable] +#[derive(Debug, PartialEq, Eq)] +#[unstable(feature = "type_info", issue = "146922")] +pub struct TraitImpl { + pub(crate) vtable: DynMetadata, +} + +impl TraitImpl { + /// Gets the raw vtable for type reflection mapping + pub const fn get_vtable(&self) -> DynMetadata { + self.vtable + } } impl TypeId { @@ -21,34 +36,59 @@ impl TypeId { /// It can only be called at compile time. #[unstable(feature = "type_info", issue = "146922")] #[rustc_const_unstable(feature = "type_info", issue = "146922")] - pub const fn info(self) -> Type { + #[rustc_comptime] + pub fn info(self) -> Type { type_of(self) } } impl Type { /// Returns the type information of the generic type parameter. + /// + /// Note: Unlike `TypeId`s obtained via `TypeId::of`, the `Type` + /// struct and its fields contain `TypeId`s that are not necessarily + /// derived from types that outlive `'static`. This means that using + /// the `TypeId`s (transitively) obtained from this function will + /// be able to break invariants that other `TypeId` consuming crates + /// may have assumed to hold. #[unstable(feature = "type_info", issue = "146922")] #[rustc_const_unstable(feature = "type_info", issue = "146922")] - // FIXME(reflection): don't require the 'static bound - pub const fn of() -> Self { - const { TypeId::of::().info() } + pub const fn of() -> Self { + const { type_id::().info() } } } +// FIXME(reflection): get rid of the static lifetime bound on TypeId and remove this function. +/// Returns the [TypeId] of the generic type parameter. +/// +/// This is identical to [TypeId::of] but without the static lifetime bound. It will be removed +/// in the future. +#[must_use] +#[unstable(feature = "type_info", issue = "146922")] +#[rustc_const_unstable(feature = "type_info", issue = "146922")] +pub const fn of() -> TypeId { + const { intrinsics::type_id::() } +} + /// Compile-time type information. #[derive(Debug)] #[non_exhaustive] #[unstable(feature = "type_info", issue = "146922")] pub enum TypeKind { /// Tuples. - Tuple(Tuple), + Tuple, /// Arrays. Array(Array), /// Slices. Slice(Slice), /// Dynamic Traits. DynTrait(DynTrait), + /// Structs. + Struct, + /// Enums. + Enum, + /// Unions. + Union, /// Primitive boolean type. Bool(Bool), /// Primitive character type. @@ -63,30 +103,12 @@ pub enum TypeKind { Reference(Reference), /// Pointers. Pointer(Pointer), + /// Function pointers. + FnPtr(FnPtr), /// FIXME(#146922): add all the common types Other, } -/// Compile-time type information about tuples. -#[derive(Debug)] -#[non_exhaustive] -#[unstable(feature = "type_info", issue = "146922")] -pub struct Tuple { - /// All fields of a tuple. - pub fields: &'static [Field], -} - -/// Compile-time type information about fields of tuples, structs and enum variants. -#[derive(Debug)] -#[non_exhaustive] -#[unstable(feature = "type_info", issue = "146922")] -pub struct Field { - /// The field's type. - pub ty: TypeId, - /// Offset in bytes from the parent type - pub offset: usize, -} - /// Compile-time type information about arrays. #[derive(Debug)] #[non_exhaustive] @@ -137,6 +159,46 @@ pub struct Trait { pub is_auto: bool, } +/// Compile-time type information about instantiated generics of structs, enum and union variants. +#[derive(Debug)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +#[lang = "type_info_generic"] +pub enum Generic { + /// Lifetimes. + Lifetime(Lifetime), + /// Types. + Type(GenericType), + /// Const parameters. + Const(Const), +} + +/// Compile-time type information about generic lifetimes. +#[derive(Debug)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +pub struct Lifetime { + // No additional information to provide for now. +} + +/// Compile-time type information about instantiated generic types. +#[derive(Debug)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +pub struct GenericType { + /// The type itself. + pub ty: TypeId, +} + +/// Compile-time type information about generic const parameters. +#[derive(Debug)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +pub struct Const { + /// The const's type. + pub ty: TypeId, +} + /// Compile-time type information about `bool`. #[derive(Debug)] #[non_exhaustive] @@ -202,3 +264,475 @@ pub struct Pointer { /// Whether this pointer is mutable or not. pub mutable: bool, } + +#[derive(Debug)] +#[unstable(feature = "type_info", issue = "146922")] +/// Function pointer, e.g. fn(u8), +pub struct FnPtr { + /// Unsafety, true is unsafe + pub unsafety: bool, + + /// Abi, e.g. extern "C" + pub abi: Abi, + + /// Function inputs + pub inputs: &'static [TypeId], + + /// Function return type, default is TypeId::of::<()> + pub output: TypeId, + + /// Vardiadic function, e.g. extern "C" fn add(n: usize, mut args: ...); + pub variadic: bool, + + // FIXME(splat): should these fields be private, or merged into an Option? + /// Is any function argument splatted? + pub is_splatted: bool, + + /// The index of the splatted function argument in `inputs`, only valid if `is_splatted` is true. + /// e.g. in `fn overload(a: u8, #[rustc_splat] b: (f32, usize))` the index is 1, and it can be called + /// as `overload(a, 1.0, 2)`. + pub splatted_index: u8, +} + +impl FnPtr { + /// Returns the splatted function argument index, or `None` if no argument is splatted. + pub const fn splatted(&self) -> Option { + if self.is_splatted { Some(self.splatted_index) } else { None } + } +} + +#[derive(Debug, Default)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +/// Abi of [FnPtr] +pub enum Abi { + /// Named abi, e.g. extern "custom", "stdcall" etc. + Named(&'static str), + + /// Default + #[default] + ExternRust, + + /// C-calling convention + ExternC, +} + +impl TypeId { + /// Returns `true` if the type represented by this `TypeId` is an signed integer. + /// + /// For everything else this returns false. + /// + /// # Examples + /// + /// ``` + /// #![feature(type_info)] + /// use std::any::TypeId; + /// + /// assert_eq!(const { TypeId::of::().is_signed() }, true); + /// assert_eq!(const { TypeId::of::().is_signed() }, false); + /// assert_eq!(const { TypeId::of::().is_signed() }, false); + /// ``` + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + #[rustc_comptime] + pub fn is_signed(self) -> bool { + intrinsics::type_id_is_signed(self) + } + + /// Returns the size of the type represented by this `TypeId`. `None` if it is unsized. + /// + /// # Examples + /// + /// ``` + /// #![feature(type_info)] + /// use std::any::TypeId; + /// + /// assert_eq!(const { TypeId::of::().size() }, Some(4)); + /// assert_eq!(const { TypeId::of::<[u8; 16]>().size() }, Some(16)); + /// ``` + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + #[rustc_comptime] + pub fn size(self) -> Option { + intrinsics::size_of_type_id(self) + } + + /// Returns the number of variants of the type represented by this `TypeId`. + /// + /// For enums, this is the number of variants. For structs and unions, this is always 1. + /// + /// ``` + /// #![feature(type_info)] + /// use std::any::TypeId; + /// + /// assert_eq!(const { TypeId::of::>().variants() }, 2); + /// + /// struct Unit; + /// struct Point { + /// x: u32, + /// y: u32, + /// } + /// assert_eq!(const { TypeId::of::().variants() }, 1); + /// assert_eq!(const { TypeId::of::().variants() }, 1); + /// assert_eq!(const { TypeId::of::<(f32, f32)>().variants() }, 1); + /// ``` + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + #[rustc_comptime] + pub fn variants(self) -> usize { + intrinsics::type_id_variants(self) + } + + // FIXME(reflection): make the errors nicer. This is a wider problem, + // TypeId::fields has nice errors in the docs but those are not the ones shown + // by rustc. + /// Returns the variant representing type at the given index of the type represented by this `TypeId`. Use it to + /// get the name of an enum variant or check whether it is non_exhaustive. + /// + /// ``` + /// #![feature(type_info)] + /// use std::any::TypeId; + /// + /// enum Enum { + /// Unit, + /// Tuple(u32, u64), + /// #[non_exhaustive] + /// Struct { x: u32, y: u32, z: String }, + /// } + /// assert_eq!(const { TypeId::of::().variant(1).name() }, "Tuple"); + /// assert_eq!(const { TypeId::of::().variant(2).name() }, "Struct"); + /// + /// assert_eq!(const { TypeId::of::().variant(1).non_exhaustive() }, false); + /// assert_eq!(const { TypeId::of::().variant(2).non_exhaustive() }, true); + /// ``` + /// + /// The variant index refer to the source order index of a variant in a type. + /// + /// Variant indexes are always `0..variant_count`, regardless of any custom discriminants that may have been defined. + /// + /// ``` + /// enum Enum { + /// Foo, // variant index == 0 + /// Bar, // variant index == 1 + /// } + /// ``` + /// + /// Calling variant on the TypeId for a struct will be treated as a compile-time error. The same + /// is true for out-of-bounds indexing on an enum. + /// + /// ```compile_fail,E0080 + /// # #![feature(type_info)] + /// # use std::any::TypeId; + /// # + /// # struct Point { + /// # x: u32, + /// # y: u32, + /// # } + /// # enum Enum { + /// # Unit, + /// # Tuple(u32, u64), + /// # Struct { x: u32, y: u32, z: String }, + /// # } + /// const { + /// _ = TypeId::of::().variant(0); // error: cannot get the variant of a struct + /// _ = TypeId::of::().variant(10); // error: indexing out of bounds: the len is 3 but the index is 10 + /// } + /// ``` + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + #[rustc_comptime] + pub fn variant(self, variant_index: usize) -> VariantId { + intrinsics::type_id_fields(self, variant_index); + VariantId { base: self, variant: variant_index } + } + + /// Returns the number of fields at the given `variant_index` of the type represented by this `TypeId`. + /// + /// ``` + /// #![feature(type_info)] + /// use std::any::TypeId; + /// + /// assert_eq!(const { TypeId::of::().fields(0) }, 0); + /// + /// struct Point { + /// x: u32, + /// y: u32, + /// } + /// assert_eq!(const { TypeId::of::().fields(0) }, 2); + /// + /// enum Enum { + /// Unit, + /// Tuple(u32, u64), + /// Struct { x: u32, y: u32, z: String }, + /// } + /// assert_eq!(const { TypeId::of::().fields(0) }, 0); + /// assert_eq!(const { TypeId::of::().fields(1) }, 2); + /// assert_eq!(const { TypeId::of::().fields(2) }, 3); + /// ``` + /// + /// The variant index refers to the source order index of a variant in a type. + /// + /// For enums, these are always `0..variant_count`, regardless of any custom discriminants that may have been defined. + /// `struct`s, `tuples`, and `unions`s are considered to have a single variant with variant index zero. + /// + /// ``` + /// enum Number { + /// Seven = 7, // variant index == 0 + /// Six = 6, // variant index == 1 + /// } + /// ``` + /// + /// Out-of-bounds indexing will be treated as a compile-time error. + /// + /// ```compile_fail,E0080 + /// # #![feature(type_info)] + /// # use std::any::TypeId; + /// # + /// # struct Point { + /// # x: u32, + /// # y: u32, + /// # } + /// # enum Enum { + /// # Unit, + /// # Tuple(u32, u64), + /// # Struct { x: u32, y: u32, z: String }, + /// # } + /// const { + /// _ = TypeId::of::().fields(10); // error: indexing out of bounds: the len is 2 but the index is 10 + /// _ = TypeId::of::().fields(10); // error: indexing out of bounds: the len is 3 but the index is 10 + /// } + /// ``` + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + #[rustc_comptime] + // FIXME(type_info): Add enum variant pattern types and use them to represent individual variants + // Then add a `variant` method to get a wrapper around such a pattern type (similar to the FRT + // type we have) and add methods on that. It's the only way to really sensibly represent + // things like `non_exhaustive` which can be applied to variants as well. + pub fn fields(self, variant_index: usize) -> usize { + intrinsics::type_id_fields(self, variant_index) + } + + /// Returns the field representing type at the given index of the type represented by this `TypeId`. + /// + /// ``` + /// #![feature(type_info)] + /// use std::any::TypeId; + /// + /// struct Point { + /// x: u32, + /// y: u32, + /// } + /// assert_eq!(const { TypeId::of::().field(0, 0).type_id() }, TypeId::of::()); + /// assert_eq!(const { TypeId::of::().field(0, 1).type_id() }, TypeId::of::()); + /// + /// enum Enum { + /// Unit, + /// Tuple(u32, u64), + /// Struct { x: u32, y: u32, z: String }, + /// } + /// assert_eq!(const { TypeId::of::().field(1, 0).type_id() }, TypeId::of::()); + /// assert_eq!(const { TypeId::of::().field(2, 2).type_id() }, TypeId::of::()); + /// ``` + /// + /// The variant index and field index refer to the source order index of a variant in a type and + /// the source order index of a field in a variant, respectively. + /// + /// For enums, variant indexes are always `0..variant_count`, regardless of any custom discriminants that may have been defined. + /// `struct`s, `tuples`, and `unions`s are considered to have a single variant with variant index zero. + /// + /// As for field indexes, they may not be the same as the layout order for `repr(Rust)` types, but they are for `repr(C)` types. + /// + /// ``` + /// enum Enum { + /// Foo, // variant index == 0 + /// Bar { // variant index == 1 + /// a: (), // field index == 0 in `Bar` + /// b: (), // field index == 1 in `Bar` + /// } + /// } + /// ``` + /// + /// Out-of-bounds indexing will be treated as a compile-time error. + /// + /// ```compile_fail,E0080 + /// # #![feature(type_info)] + /// # use std::any::TypeId; + /// # + /// # struct Point { + /// # x: u32, + /// # y: u32, + /// # } + /// # enum Enum { + /// # Unit, + /// # Tuple(u32, u64), + /// # Struct { x: u32, y: u32, z: String }, + /// # } + /// const { + /// _ = TypeId::of::().field(0, 10); // error: indexing out of bounds: the len is 2 but the index is 10 + /// _ = TypeId::of::().field(2, 10); // error: indexing out of bounds: the len is 3 but the index is 10 + /// } + /// ``` + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + #[rustc_comptime] + pub fn field(self, variant_index: usize, field_index: usize) -> FieldId { + FieldId { + frt_type_id: intrinsics::type_id_field_representing_type( + self, + variant_index, + field_index, + ), + } + } + + /// Returns whether a type is marked with `#[non_exhaustive]`. + /// Returns `false` for everything but adts. + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + #[rustc_comptime] + pub fn non_exhaustive(self) -> bool { + intrinsics::non_exhaustive(self) + } + + /// Returns a list of generic parameters of the type. + /// Returns an empty slice for everything that doesn't have generics. + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + #[rustc_comptime] + pub fn generics(self) -> &'static [Generic] { + intrinsics::type_id_generics(self) + } +} + +/// Variant representing type ID. Representing a variant of an enum. +#[derive(Copy, PartialOrd, Ord, Hash)] +#[derive_const(Clone, PartialEq, Eq)] +#[unstable(feature = "type_info", issue = "146922")] +pub struct VariantId { + base: TypeId, + variant: usize, +} + +#[unstable(feature = "type_info", issue = "146922")] +impl fmt::Debug for VariantId { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + write!(f, "Variant({:#034x}-{})", self.base.as_u128(), self.variant) + } +} + +impl VariantId { + /// Returns the name of the variant. + /// + /// ``` + /// #![feature(type_info)] + /// use std::any::TypeId; + /// + /// enum Enum { + /// Unit, + /// Tuple(bool), + /// Struct { a: bool }, + /// } + /// assert_eq!( + /// const { TypeId::of::().variant(1).name() }, + /// "Tuple", + /// ); + /// ``` + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + #[rustc_comptime] + pub fn name(self) -> &'static str { + intrinsics::variant_name(self.base, self.variant) + } + + /// Returns whether this variant is marked with `#[non_exhaustive]`. + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + #[rustc_comptime] + pub fn non_exhaustive(self) -> bool { + intrinsics::variant_non_exhaustive(self.base, self.variant) + } +} + +/// Field representing type ID. Representing a field of a struct, tuple or enum variant. +#[derive(Copy, PartialOrd, Ord, Hash)] +#[derive_const(Clone, PartialEq, Eq)] +#[unstable(feature = "type_info", issue = "146922")] +pub struct FieldId { + frt_type_id: TypeId, +} + +#[unstable(feature = "type_info", issue = "146922")] +impl fmt::Debug for FieldId { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + write!(f, "FieldId({:#034x})", self.frt_type_id.as_u128()) + } +} + +impl FieldId { + /// Returns the `TypeId` of the actual field type. + /// + /// ``` + /// #![feature(type_info)] + /// use std::any::TypeId; + /// + /// struct Point { + /// x: u32, + /// y: u32, + /// } + /// assert_eq!( + /// const { TypeId::of::().field(0, 0).type_id() }, + /// TypeId::of::() + /// ); + /// ``` + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + #[rustc_comptime] + pub fn type_id(self) -> TypeId { + intrinsics::field_representing_type_actual_type_id(self.frt_type_id) + } + + /// Returns the name of the field. + /// + /// ``` + /// #![feature(type_info)] + /// use std::any::TypeId; + /// + /// struct Point { + /// x: u32, + /// y: u32, + /// } + /// assert_eq!( + /// const { TypeId::of::().field(0, 0).name() }, + /// "x", + /// ); + /// ``` + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + #[rustc_comptime] + pub fn name(self) -> &'static str { + intrinsics::field_representing_type_name(self.frt_type_id) + } + /// Returns the offset of the field wrt to its containing type. + /// + /// ``` + /// #![feature(type_info)] + /// use std::any::TypeId; + /// + /// #[repr(C)] + /// struct Point { + /// x: u32, + /// y: u32, + /// } + /// assert_eq!( + /// const { TypeId::of::().field(0, 1).offset() }, + /// 4, + /// ); + /// ``` + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + #[rustc_comptime] + pub fn offset(self) -> usize { + intrinsics::field_representing_type_offset(self.frt_type_id) + } +} diff --git a/library/core/src/net/display_buffer.rs b/library/core/src/net/display_buffer.rs index 625ad5401f5c0..1b60d722784da 100644 --- a/library/core/src/net/display_buffer.rs +++ b/library/core/src/net/display_buffer.rs @@ -2,15 +2,20 @@ use crate::mem::MaybeUninit; use crate::{fmt, str}; /// Used for slow path in `Display` implementations when alignment is required. -pub(super) struct DisplayBuffer { - buf: [MaybeUninit; SIZE], +pub(super) struct DisplayBuffer<'a> { + buf: &'a mut [MaybeUninit], len: usize, } -impl DisplayBuffer { +impl<'a> DisplayBuffer<'a> { #[inline] - pub(super) const fn new() -> Self { - Self { buf: [MaybeUninit::uninit(); SIZE], len: 0 } + pub(super) const fn new(buf: &'a mut [MaybeUninit]) -> Self { + Self { buf, len: 0 } + } + + #[inline] + pub(super) const fn buffer() -> [MaybeUninit; SIZE] { + [MaybeUninit::uninit(); SIZE] } #[inline] @@ -24,7 +29,7 @@ impl DisplayBuffer { } } -impl fmt::Write for DisplayBuffer { +impl fmt::Write for DisplayBuffer<'_> { fn write_str(&mut self, s: &str) -> fmt::Result { let bytes = s.as_bytes(); diff --git a/library/core/src/net/ip_addr.rs b/library/core/src/net/ip_addr.rs index a1bfd774710d5..f09410b18651e 100644 --- a/library/core/src/net/ip_addr.rs +++ b/library/core/src/net/ip_addr.rs @@ -68,7 +68,8 @@ pub enum IpAddr { /// assert!("0xcb.0x0.0x71.0x00".parse::().is_err()); // all octets are in hex /// ``` #[rustc_diagnostic_item = "Ipv4Addr"] -#[derive(Copy, Clone, PartialEq, Eq)] +#[derive(Copy)] +#[derive_const(Clone, PartialEq, Eq)] #[stable(feature = "rust1", since = "1.0.0")] pub struct Ipv4Addr { octets: [u8; 4], @@ -161,7 +162,8 @@ impl Hash for Ipv4Addr { /// assert_eq!(localhost.is_loopback(), true); /// ``` #[rustc_diagnostic_item = "Ipv6Addr"] -#[derive(Copy, Clone, PartialEq, Eq)] +#[derive(Copy)] +#[derive_const(Clone, PartialEq, Eq)] #[stable(feature = "rust1", since = "1.0.0")] pub struct Ipv6Addr { octets: [u8; 16], @@ -177,15 +179,17 @@ impl Hash for Ipv6Addr { } } -/// Scope of an [IPv6 multicast address] as defined in [IETF RFC 7346 section 2]. +/// Scope of an [IPv6 multicast address] as defined in [IETF RFC 7346 section 2], +/// which updates [IETF RFC 4291 section 2.7]. /// /// # Stability Guarantees /// -/// Not all possible values for a multicast scope have been assigned. -/// Future RFCs may introduce new scopes, which will be added as variants to this enum; -/// because of this the enum is marked as `#[non_exhaustive]`. +/// Scopes 0 and F are currently reserved by IETF, and may be assigned in the future. +/// For this reason, the enum variants for those two scopes are not currently nameable. +/// You can still check for them in your code using `as` casts. /// /// # Examples +/// /// ``` /// #![feature(ip)] /// @@ -204,32 +208,76 @@ impl Hash for Ipv6Addr { /// Some(SiteLocal) => println!("Site-Local scope"), /// Some(OrganizationLocal) => println!("Organization-Local scope"), /// Some(Global) => println!("Global scope"), -/// Some(_) => println!("Unknown scope"), +/// Some(s) => { +/// let snum = s as u8; +/// if matches!(0x0 | 0xF, snum) { +/// println!("Reserved scope {snum:X}") +/// } else { +/// println!("Unassigned scope {snum:X}") +/// } +/// } /// None => println!("Not a multicast address!") /// } -/// /// ``` /// /// [IPv6 multicast address]: Ipv6Addr /// [IETF RFC 7346 section 2]: https://tools.ietf.org/html/rfc7346#section-2 -#[derive(Copy, PartialEq, Eq, Clone, Hash, Debug)] +/// [IETF RFC 4291 section 2.7]: https://datatracker.ietf.org/doc/html/rfc4291#section-2.7 +#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)] #[unstable(feature = "ip", issue = "27709")] -#[non_exhaustive] pub enum Ipv6MulticastScope { + /// Reserved by IETF. + #[doc(hidden)] + #[unstable( + feature = "ip_multicast_reserved", + reason = "not yet assigned by IETF", + issue = "none" + )] + Reserved0 = 0x0, /// Interface-Local scope. - InterfaceLocal, + InterfaceLocal = 0x1, /// Link-Local scope. - LinkLocal, + LinkLocal = 0x2, /// Realm-Local scope. - RealmLocal, + RealmLocal = 0x3, /// Admin-Local scope. - AdminLocal, + AdminLocal = 0x4, /// Site-Local scope. - SiteLocal, + SiteLocal = 0x5, + + /// Scope 6. Unassigned, available for administrators + /// to define additional multicast regions. + Unassigned6 = 0x6, + /// Scope 7. Unassigned, available for administrators + /// to define additional multicast regions. + Unassigned7 = 0x7, /// Organization-Local scope. - OrganizationLocal, + OrganizationLocal = 0x8, + /// Scope 9. Unassigned, available for administrators + /// to define additional multicast regions. + Unassigned9 = 0x9, + /// Scope A. Unassigned, available for administrators + /// to define additional multicast regions. + UnassignedA = 0xA, + /// Scope B. Unassigned, available for administrators + /// to define additional multicast regions. + UnassignedB = 0xB, + /// Scope C. Unassigned, available for administrators + /// to define additional multicast regions. + UnassignedC = 0xC, + /// Scope D. Unassigned, available for administrators + /// to define additional multicast regions. + UnassignedD = 0xD, /// Global scope. - Global, + Global = 0xE, + /// Reserved by IETF. + #[doc(hidden)] + #[unstable( + feature = "ip_multicast_reserved", + reason = "not yet assigned by IETF", + issue = "none" + )] + ReservedF = 0xF, } impl IpAddr { @@ -257,6 +305,35 @@ impl IpAddr { } } + /// Returns the unspecified IP address for the same IP version. + /// + /// Returns `0.0.0.0` for IPv4 and `::` for IPv6. + /// + /// Use this method when you must bind a socket to an unspecified local + /// address that uses the same IP version as a remote address. + /// + /// # Examples + /// + /// ``` + /// #![feature(addr_unspecified_from)] + /// use std::net::{IpAddr, Ipv4Addr, Ipv6Addr}; + /// + /// let ipv4 = IpAddr::V4(Ipv4Addr::new(127, 0, 0, 1)); + /// assert_eq!(IpAddr::unspecified_from(ipv4), IpAddr::V4(Ipv4Addr::UNSPECIFIED)); + /// + /// let ipv6 = IpAddr::V6(Ipv6Addr::new(0x2001, 0xdb8, 0, 0, 0, 0, 0, 1)); + /// assert_eq!(IpAddr::unspecified_from(ipv6), IpAddr::V6(Ipv6Addr::UNSPECIFIED)); + /// ``` + #[inline] + #[must_use] + #[unstable(feature = "addr_unspecified_from", issue = "158975")] + pub const fn unspecified_from(this: Self) -> Self { + match this { + Self::V4(_) => Self::V4(Ipv4Addr::UNSPECIFIED), + Self::V6(_) => Self::V6(Ipv6Addr::UNSPECIFIED), + } + } + /// Returns [`true`] if this is a loopback address. /// /// See the documentation for [`Ipv4Addr::is_loopback()`] and @@ -1088,7 +1165,7 @@ impl fmt::Debug for IpAddr { #[stable(feature = "ip_from_ip", since = "1.16.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for IpAddr { +const impl From for IpAddr { /// Copies this address to a new `IpAddr::V4`. /// /// # Examples @@ -1111,7 +1188,7 @@ impl const From for IpAddr { #[stable(feature = "ip_from_ip", since = "1.16.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for IpAddr { +const impl From for IpAddr { /// Copies this address to a new `IpAddr::V6`. /// /// # Examples @@ -1144,7 +1221,8 @@ impl fmt::Display for Ipv4Addr { } else { const LONGEST_IPV4_ADDR: &str = "255.255.255.255"; - let mut buf = DisplayBuffer::<{ LONGEST_IPV4_ADDR.len() }>::new(); + let mut buf = DisplayBuffer::buffer::<{ LONGEST_IPV4_ADDR.len() }>(); + let mut buf = DisplayBuffer::new(&mut buf); // Buffer is long enough for the longest possible IPv4 address, so this should never fail. write!(buf, "{}.{}.{}.{}", octets[0], octets[1], octets[2], octets[3]).unwrap(); @@ -1183,7 +1261,8 @@ impl PartialEq for Ipv4Addr { } #[stable(feature = "rust1", since = "1.0.0")] -impl PartialOrd for Ipv4Addr { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +const impl PartialOrd for Ipv4Addr { #[inline] fn partial_cmp(&self, other: &Ipv4Addr) -> Option { Some(self.cmp(other)) @@ -1213,7 +1292,8 @@ impl PartialOrd for Ipv4Addr { } #[stable(feature = "rust1", since = "1.0.0")] -impl Ord for Ipv4Addr { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +const impl Ord for Ipv4Addr { #[inline] fn cmp(&self, other: &Ipv4Addr) -> Ordering { self.octets.cmp(&other.octets) @@ -1222,7 +1302,7 @@ impl Ord for Ipv4Addr { #[stable(feature = "ip_u32", since = "1.1.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for u32 { +const impl From for u32 { /// Uses [`Ipv4Addr::to_bits`] to convert an IPv4 address to a host byte order `u32`. #[inline] fn from(ip: Ipv4Addr) -> u32 { @@ -1232,7 +1312,7 @@ impl const From for u32 { #[stable(feature = "ip_u32", since = "1.1.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for Ipv4Addr { +const impl From for Ipv4Addr { /// Uses [`Ipv4Addr::from_bits`] to convert a host byte order `u32` into an IPv4 address. #[inline] fn from(ip: u32) -> Ipv4Addr { @@ -1242,7 +1322,7 @@ impl const From for Ipv4Addr { #[stable(feature = "from_slice_v4", since = "1.9.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From<[u8; 4]> for Ipv4Addr { +const impl From<[u8; 4]> for Ipv4Addr { /// Creates an `Ipv4Addr` from a four element byte array. /// /// # Examples @@ -1261,7 +1341,7 @@ impl const From<[u8; 4]> for Ipv4Addr { #[stable(feature = "ip_from_slice", since = "1.17.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From<[u8; 4]> for IpAddr { +const impl From<[u8; 4]> for IpAddr { /// Creates an `IpAddr::V4` from a four element byte array. /// /// # Examples @@ -1848,14 +1928,23 @@ impl Ipv6Addr { pub const fn multicast_scope(&self) -> Option { if self.is_multicast() { match self.segments()[0] & 0x000f { - 1 => Some(Ipv6MulticastScope::InterfaceLocal), - 2 => Some(Ipv6MulticastScope::LinkLocal), - 3 => Some(Ipv6MulticastScope::RealmLocal), - 4 => Some(Ipv6MulticastScope::AdminLocal), - 5 => Some(Ipv6MulticastScope::SiteLocal), - 8 => Some(Ipv6MulticastScope::OrganizationLocal), - 14 => Some(Ipv6MulticastScope::Global), - _ => None, + 0x0 => Some(Ipv6MulticastScope::Reserved0), + 0x1 => Some(Ipv6MulticastScope::InterfaceLocal), + 0x2 => Some(Ipv6MulticastScope::LinkLocal), + 0x3 => Some(Ipv6MulticastScope::RealmLocal), + 0x4 => Some(Ipv6MulticastScope::AdminLocal), + 0x5 => Some(Ipv6MulticastScope::SiteLocal), + 0x6 => Some(Ipv6MulticastScope::Unassigned6), + 0x7 => Some(Ipv6MulticastScope::Unassigned7), + 0x8 => Some(Ipv6MulticastScope::OrganizationLocal), + 0x9 => Some(Ipv6MulticastScope::Unassigned9), + 0xA => Some(Ipv6MulticastScope::UnassignedA), + 0xB => Some(Ipv6MulticastScope::UnassignedB), + 0xC => Some(Ipv6MulticastScope::UnassignedC), + 0xD => Some(Ipv6MulticastScope::UnassignedD), + 0xE => Some(Ipv6MulticastScope::Global), + 0xF => Some(Ipv6MulticastScope::ReservedF), + _ => unreachable!(), } } else { None @@ -2138,7 +2227,8 @@ impl fmt::Display for Ipv6Addr { } else { const LONGEST_IPV6_ADDR: &str = "ffff:ffff:ffff:ffff:ffff:ffff:ffff:ffff"; - let mut buf = DisplayBuffer::<{ LONGEST_IPV6_ADDR.len() }>::new(); + let mut buf = DisplayBuffer::buffer::<{ LONGEST_IPV6_ADDR.len() }>(); + let mut buf = DisplayBuffer::new(&mut buf); // Buffer is long enough for the longest possible IPv6 address, so this should never fail. write!(buf, "{}", self).unwrap(); @@ -2177,7 +2267,8 @@ impl PartialEq for IpAddr { } #[stable(feature = "rust1", since = "1.0.0")] -impl PartialOrd for Ipv6Addr { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +const impl PartialOrd for Ipv6Addr { #[inline] fn partial_cmp(&self, other: &Ipv6Addr) -> Option { Some(self.cmp(other)) @@ -2207,7 +2298,8 @@ impl PartialOrd for Ipv6Addr { } #[stable(feature = "rust1", since = "1.0.0")] -impl Ord for Ipv6Addr { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +const impl Ord for Ipv6Addr { #[inline] fn cmp(&self, other: &Ipv6Addr) -> Ordering { self.segments().cmp(&other.segments()) @@ -2216,7 +2308,7 @@ impl Ord for Ipv6Addr { #[stable(feature = "i128", since = "1.26.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for u128 { +const impl From for u128 { /// Uses [`Ipv6Addr::to_bits`] to convert an IPv6 address to a host byte order `u128`. #[inline] fn from(ip: Ipv6Addr) -> u128 { @@ -2225,7 +2317,7 @@ impl const From for u128 { } #[stable(feature = "i128", since = "1.26.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for Ipv6Addr { +const impl From for Ipv6Addr { /// Uses [`Ipv6Addr::from_bits`] to convert a host byte order `u128` to an IPv6 address. #[inline] fn from(ip: u128) -> Ipv6Addr { @@ -2235,7 +2327,7 @@ impl const From for Ipv6Addr { #[stable(feature = "ipv6_from_octets", since = "1.9.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From<[u8; 16]> for Ipv6Addr { +const impl From<[u8; 16]> for Ipv6Addr { /// Creates an `Ipv6Addr` from a sixteen element byte array. /// /// # Examples @@ -2263,7 +2355,7 @@ impl const From<[u8; 16]> for Ipv6Addr { #[stable(feature = "ipv6_from_segments", since = "1.16.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From<[u16; 8]> for Ipv6Addr { +const impl From<[u16; 8]> for Ipv6Addr { /// Creates an `Ipv6Addr` from an eight element 16-bit array. /// /// # Examples @@ -2292,7 +2384,7 @@ impl const From<[u16; 8]> for Ipv6Addr { #[stable(feature = "ip_from_slice", since = "1.17.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From<[u8; 16]> for IpAddr { +const impl From<[u8; 16]> for IpAddr { /// Creates an `IpAddr::V6` from a sixteen element byte array. /// /// # Examples @@ -2320,7 +2412,7 @@ impl const From<[u8; 16]> for IpAddr { #[stable(feature = "ip_from_slice", since = "1.17.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From<[u16; 8]> for IpAddr { +const impl From<[u16; 8]> for IpAddr { /// Creates an `IpAddr::V6` from an eight element 16-bit array. /// /// # Examples @@ -2348,7 +2440,7 @@ impl const From<[u16; 8]> for IpAddr { #[stable(feature = "ip_bitops", since = "1.75.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const Not for Ipv4Addr { +const impl Not for Ipv4Addr { type Output = Ipv4Addr; #[inline] @@ -2364,7 +2456,7 @@ impl const Not for Ipv4Addr { #[stable(feature = "ip_bitops", since = "1.75.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const Not for &'_ Ipv4Addr { +const impl Not for &'_ Ipv4Addr { type Output = Ipv4Addr; #[inline] @@ -2375,7 +2467,7 @@ impl const Not for &'_ Ipv4Addr { #[stable(feature = "ip_bitops", since = "1.75.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const Not for Ipv6Addr { +const impl Not for Ipv6Addr { type Output = Ipv6Addr; #[inline] @@ -2391,7 +2483,7 @@ impl const Not for Ipv6Addr { #[stable(feature = "ip_bitops", since = "1.75.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const Not for &'_ Ipv6Addr { +const impl Not for &'_ Ipv6Addr { type Output = Ipv6Addr; #[inline] @@ -2407,7 +2499,7 @@ macro_rules! bitop_impls { )*) => { $( $(#[$attr])* - impl const $BitOpAssign for $ty { + const impl $BitOpAssign for $ty { fn $bitop_assign(&mut self, rhs: $ty) { let mut idx = 0; while idx < self.octets.len() { @@ -2418,14 +2510,14 @@ macro_rules! bitop_impls { } $(#[$attr])* - impl const $BitOpAssign<&'_ $ty> for $ty { + const impl $BitOpAssign<&'_ $ty> for $ty { fn $bitop_assign(&mut self, rhs: &'_ $ty) { self.$bitop_assign(*rhs); } } $(#[$attr])* - impl const $BitOp for $ty { + const impl $BitOp for $ty { type Output = $ty; #[inline] @@ -2436,7 +2528,7 @@ macro_rules! bitop_impls { } $(#[$attr])* - impl const $BitOp<&'_ $ty> for $ty { + const impl $BitOp<&'_ $ty> for $ty { type Output = $ty; #[inline] @@ -2447,7 +2539,7 @@ macro_rules! bitop_impls { } $(#[$attr])* - impl const $BitOp<$ty> for &'_ $ty { + const impl $BitOp<$ty> for &'_ $ty { type Output = $ty; #[inline] @@ -2459,7 +2551,7 @@ macro_rules! bitop_impls { } $(#[$attr])* - impl const $BitOp<&'_ $ty> for &'_ $ty { + const impl $BitOp<&'_ $ty> for &'_ $ty { type Output = $ty; #[inline] diff --git a/library/core/src/net/parser.rs b/library/core/src/net/parser.rs index 3aab24a90d817..8e56fd323b0d7 100644 --- a/library/core/src/net/parser.rs +++ b/library/core/src/net/parser.rs @@ -63,11 +63,6 @@ impl<'a> Parser<'a> { if self.state.is_empty() { result } else { None }.ok_or(AddrParseError(kind)) } - /// Peek the next character from the input - fn peek_char(&self) -> Option { - self.state.first().map(|&b| char::from(b)) - } - /// Reads the next character from the input fn read_char(&mut self) -> Option { self.state.split_first().map(|(&b, tail)| { @@ -100,60 +95,56 @@ impl<'a> Parser<'a> { }) } - // Read a number off the front of the input in the given radix, stopping - // at the first non-digit character or eof. Fails if the number has more - // digits than max_digits or if there is no number. - // - // INVARIANT: `max_digits` must be less than the number of digits that `u32` - // can represent. - fn read_number>( + /// Reads a number off the front of the input in the given radix, stopping at the first + /// non-digit character or eof. Fails if the number has more digits than `max_digits`, if there + /// is no number, if the number overflows `T`, or if there are leading zeros but + /// `allow_zero_prefix` is false. + /// + /// `max_digits` must be in 1..=6. + fn read_radix_max_digits>( &mut self, radix: u32, - max_digits: Option, + max_digits: u32, allow_zero_prefix: bool, ) -> Option { - self.read_atomically(move |p| { - let mut digit_count = 0; - let has_leading_zero = p.peek_char() == Some('0'); - - // If max_digits.is_some(), then we are parsing a `u8` or `u16` and - // don't need to use checked arithmetic since it fits within a `u32`. - let result = if let Some(max_digits) = max_digits { - // u32::MAX = 4_294_967_295u32, which is 10 digits long. - // `max_digits` must be less than 10 to not overflow a `u32`. - debug_assert!(max_digits < 10); - - let mut result = 0_u32; - while let Some(digit) = p.read_atomically(|p| p.read_char()?.to_digit(radix)) { - result *= radix; - result += digit; - digit_count += 1; - - if digit_count > max_digits { - return None; - } - } - - result.try_into().ok() - } else { - let mut result = T::ZERO; + debug_assert!(1 <= max_digits); + debug_assert!(max_digits <= 6); // Works for any radix in u32 + self.read_atomically(|p| { + let first = p.read_char()?.to_digit(radix)?; + let mut result = first; + let mut digit_count = 1; - while let Some(digit) = p.read_atomically(|p| p.read_char()?.to_digit(radix)) { - result = result.checked_mul(radix)?; - result = result.checked_add(digit)?; - digit_count += 1; + while let Some(digit) = p.read_atomically(|p| p.read_char()?.to_digit(radix)) { + if digit_count >= max_digits { + return None; } + result *= radix; + result += digit; + digit_count += 1; + } - Some(result) - }; - - if digit_count == 0 { - None - } else if !allow_zero_prefix && has_leading_zero && digit_count > 1 { + if !allow_zero_prefix && first == 0 && digit_count > 1 { None } else { - result + result.try_into().ok() + } + }) + } + + /// Reads a decimal number off the front of the input, stopping at the first non-digit character + /// or eof. Fails if there is no number, or if the number overflows `T`. Allows an arbitrary + /// amount of leading zeros. + fn read_decimal(&mut self) -> Option { + self.read_atomically(|p| { + let first = p.read_char()?.to_digit(10)?; + let mut result = T::ZERO.checked_add(first)?; + + while let Some(digit) = p.read_atomically(|p| p.read_char()?.to_digit(10)) { + result = result.checked_mul(10)?; + result = result.checked_add(digit)?; } + + Some(result) }) } @@ -166,7 +157,7 @@ impl<'a> Parser<'a> { *slot = p.read_separator('.', i, |p| { // Disallow octal number in IP string. // https://tools.ietf.org/html/rfc6943#section-3.1.1 - p.read_number(10, Some(3), false) + p.read_radix_max_digits(10, 3, false) })?; } @@ -198,7 +189,7 @@ impl<'a> Parser<'a> { } } - let group = p.read_separator(':', i, |p| p.read_number(16, Some(4), true)); + let group = p.read_separator(':', i, |p| p.read_radix_max_digits(16, 4, true)); match group { Some(g) => *slot = g, @@ -250,7 +241,7 @@ impl<'a> Parser<'a> { fn read_port(&mut self) -> Option { self.read_atomically(|p| { p.read_given_char(':')?; - p.read_number(10, None, true) + p.read_decimal() }) } @@ -258,7 +249,7 @@ impl<'a> Parser<'a> { fn read_scope_id(&mut self) -> Option { self.read_atomically(|p| { p.read_given_char('%')?; - p.read_number(10, None, true) + p.read_decimal() }) } @@ -489,7 +480,7 @@ enum AddrKind { /// use std::net::SocketAddr; /// /// // No problem, the `panic!` message has disappeared. -/// let _foo: SocketAddr = "127.0.0.1:8080".parse().expect("unreachable panic"); +/// let _foo: SocketAddr = "127.0.0.1:8080".parse().expect("`parse` should succeed"); /// ``` #[stable(feature = "rust1", since = "1.0.0")] #[derive(Debug, Clone, PartialEq, Eq)] diff --git a/library/core/src/net/socket_addr.rs b/library/core/src/net/socket_addr.rs index ccc53c156d3a1..b461736bb74bd 100644 --- a/library/core/src/net/socket_addr.rs +++ b/library/core/src/net/socket_addr.rs @@ -307,6 +307,54 @@ impl SocketAddr { pub const fn is_ipv6(&self) -> bool { matches!(*self, SocketAddr::V6(_)) } + + /// Returns the unspecified socket address for the same IP version. + /// + /// Returns `0.0.0.0:0` for IPv4 and `[::]:0` for IPv6. For IPv6, this + /// method preserves the flow information and scope ID. + /// + /// Use this method when you must bind a socket to an unspecified local + /// address that uses the same IP version as a remote address. + /// + /// # Examples + /// ``` + /// #![feature(addr_unspecified_from)] + /// use std::net::{SocketAddr, SocketAddrV4, SocketAddrV6, Ipv4Addr, Ipv6Addr}; + /// + /// let addr = SocketAddr::V4(SocketAddrV4::new(Ipv4Addr::new(127, 0, 0, 1), 3000)); + /// assert_eq!( + /// SocketAddr::unspecified_from(addr), + /// SocketAddr::V4(SocketAddrV4::new(Ipv4Addr::UNSPECIFIED, 0)) + /// ); + /// + /// let addr = SocketAddr::V6(SocketAddrV6::new( + /// Ipv6Addr::new(0x2001, 0xdb8, 0, 0, 0, 0, 0, 1), + /// 443, + /// 0x1234, + /// 5, + /// )); + /// + /// let unspecified = SocketAddr::unspecified_from(addr); + /// assert_eq!(unspecified.ip(), Ipv6Addr::UNSPECIFIED); + /// if let SocketAddr::V6(v6) = unspecified { + /// assert_eq!(v6.flowinfo(), 0x1234); + /// assert_eq!(v6.scope_id(), 5); + /// } + /// ``` + #[inline] + #[must_use] + #[unstable(feature = "addr_unspecified_from", issue = "158975")] + pub const fn unspecified_from(this: Self) -> Self { + match this { + Self::V4(_) => Self::V4(SocketAddrV4::new(Ipv4Addr::UNSPECIFIED, 0)), + Self::V6(addr) => Self::V6(SocketAddrV6::new( + Ipv6Addr::UNSPECIFIED, + 0, + addr.flowinfo(), + addr.scope_id(), + )), + } + } } impl SocketAddrV4 { @@ -593,7 +641,7 @@ impl SocketAddrV6 { #[stable(feature = "ip_from_ip", since = "1.16.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for SocketAddr { +const impl From for SocketAddr { /// Converts a [`SocketAddrV4`] into a [`SocketAddr::V4`]. #[inline] fn from(sock4: SocketAddrV4) -> SocketAddr { @@ -603,7 +651,7 @@ impl const From for SocketAddr { #[stable(feature = "ip_from_ip", since = "1.16.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for SocketAddr { +const impl From for SocketAddr { /// Converts a [`SocketAddrV6`] into a [`SocketAddr::V6`]. #[inline] fn from(sock6: SocketAddrV6) -> SocketAddr { @@ -613,7 +661,7 @@ impl const From for SocketAddr { #[stable(feature = "addr_from_into_ip", since = "1.17.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl> const From<(I, u16)> for SocketAddr { +const impl> From<(I, u16)> for SocketAddr { /// Converts a tuple struct (Into<[`IpAddr`]>, `u16`) into a [`SocketAddr`]. /// /// This conversion creates a [`SocketAddr::V4`] for an [`IpAddr::V4`] @@ -652,7 +700,8 @@ impl fmt::Display for SocketAddrV4 { } else { const LONGEST_IPV4_SOCKET_ADDR: &str = "255.255.255.255:65535"; - let mut buf = DisplayBuffer::<{ LONGEST_IPV4_SOCKET_ADDR.len() }>::new(); + let mut buf = DisplayBuffer::buffer::<{ LONGEST_IPV4_SOCKET_ADDR.len() }>(); + let mut buf = DisplayBuffer::new(&mut buf); // Buffer is long enough for the longest possible IPv4 socket address, so this should never fail. write!(buf, "{}:{}", self.ip(), self.port()).unwrap(); @@ -682,7 +731,8 @@ impl fmt::Display for SocketAddrV6 { const LONGEST_IPV6_SOCKET_ADDR: &str = "[ffff:ffff:ffff:ffff:ffff:ffff:ffff:ffff%4294967295]:65535"; - let mut buf = DisplayBuffer::<{ LONGEST_IPV6_SOCKET_ADDR.len() }>::new(); + let mut buf = DisplayBuffer::buffer::<{ LONGEST_IPV6_SOCKET_ADDR.len() }>(); + let mut buf = DisplayBuffer::new(&mut buf); match self.scope_id() { 0 => write!(buf, "[{}]:{}", self.ip(), self.port()), scope_id => write!(buf, "[{}%{}]:{}", self.ip(), scope_id, self.port()), diff --git a/library/core/src/num/complex.rs b/library/core/src/num/complex.rs new file mode 100644 index 0000000000000..9321718899cdd --- /dev/null +++ b/library/core/src/num/complex.rs @@ -0,0 +1,20 @@ +/// A complex number. +#[derive(Clone, Copy, Debug, PartialEq)] +#[unstable(feature = "complex_numbers", issue = "154023")] +#[repr(C)] +#[lang = "complex"] +pub struct Complex { + /// The real component. + pub re: T, + /// The imaginary component. + pub im: T, +} + +#[unstable(feature = "complex_numbers", issue = "154023")] +impl Complex { + /// Create a new complex number from a real and imaginary component. + #[must_use] + pub fn new(re: T, im: T) -> Complex { + Complex { re, im } + } +} diff --git a/library/core/src/num/error.rs b/library/core/src/num/error.rs index 8a353dc0fbe99..ccf50a2c81a1b 100644 --- a/library/core/src/num/error.rs +++ b/library/core/src/num/error.rs @@ -7,12 +7,28 @@ use crate::fmt; /// The error type returned when a checked integral type conversion fails. #[stable(feature = "try_from", since = "1.34.0")] #[derive(Debug, Copy, Clone, PartialEq, Eq)] -pub struct TryFromIntError(pub(crate) ()); +pub struct TryFromIntError(pub(crate) IntErrorKind); + +impl TryFromIntError { + /// Outputs the detailed cause of converting an integer failing. + #[must_use] + #[unstable(feature = "try_from_int_error_kind", issue = "153978")] + pub const fn kind(&self) -> &IntErrorKind { + &self.0 + } +} #[stable(feature = "try_from", since = "1.34.0")] impl fmt::Display for TryFromIntError { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - "out of range integral type conversion attempted".fmt(f) + match self.0 { + IntErrorKind::Empty | IntErrorKind::InvalidDigit => unreachable!(), + IntErrorKind::PosOverflow => "number too large to fit in target type", + IntErrorKind::NegOverflow => "number too small to fit in target type", + IntErrorKind::Zero => "number would be zero for non-zero type", + IntErrorKind::NotAPowerOfTwo => "number is not a power of two", + } + .fmt(f) } } @@ -21,7 +37,7 @@ impl Error for TryFromIntError {} #[stable(feature = "try_from", since = "1.34.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for TryFromIntError { +const impl From for TryFromIntError { fn from(x: Infallible) -> TryFromIntError { match x {} } @@ -29,7 +45,7 @@ impl const From for TryFromIntError { #[unstable(feature = "never_type", issue = "35121")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for TryFromIntError { +const impl From for TryFromIntError { #[inline] fn from(never: !) -> TryFromIntError { // Match rather than coerce to make sure that code like @@ -66,7 +82,8 @@ pub struct ParseIntError { pub(super) kind: IntErrorKind, } -/// Enum to store the various types of errors that can cause parsing an integer to fail. +/// Enum to store the various types of errors that can cause parsing or converting an +/// integer to fail. /// /// # Example /// @@ -103,10 +120,19 @@ pub enum IntErrorKind { NegOverflow, /// Value was Zero /// - /// This variant will be emitted when the parsing string has a value of zero, which - /// would be illegal for non-zero types. + /// This variant will be emitted when the parsing string or the converting integer + /// has a value of zero, which would be illegal for non-zero types. #[stable(feature = "int_error_matching", since = "1.55.0")] Zero, + /// Value is not a power of two. + /// + /// This variant will be emitted when converting an integer that is not a power of + /// two. This is required in some cases such as constructing an [`Alignment`]. + /// + /// [`Alignment`]: core::mem::Alignment "mem::Alignment" + #[unstable(feature = "try_from_int_error_kind", issue = "153978")] + // Also, #[unstable(feature = "ptr_alignment_type", issue = "102070")] + NotAPowerOfTwo, } impl ParseIntError { @@ -128,6 +154,7 @@ impl fmt::Display for ParseIntError { IntErrorKind::PosOverflow => "number too large to fit in target type", IntErrorKind::NegOverflow => "number too small to fit in target type", IntErrorKind::Zero => "number would be zero for non-zero type", + IntErrorKind::NotAPowerOfTwo => "number is not a power of two", } .fmt(f) } diff --git a/library/core/src/num/f128.rs b/library/core/src/num/f128.rs index 72df42c4de89f..c0b4a6b7de958 100644 --- a/library/core/src/num/f128.rs +++ b/library/core/src/num/f128.rs @@ -39,6 +39,7 @@ pub mod consts { pub const TAU: f128 = 6.28318530717958647692528676655900576839433879875021164194989_f128; /// The golden ratio (φ) + #[doc(alias = "phi")] #[unstable(feature = "f128", issue = "116909")] pub const GOLDEN_RATIO: f128 = 1.61803398874989484820458683436563811772030917980576286213545_f128; @@ -154,7 +155,10 @@ pub mod consts { pub const LN_10: f128 = 2.30258509299404568401799145468436420760110148862877297603333_f128; } -#[doc(test(attr(feature(cfg_target_has_reliable_f16_f128), allow(internal_features))))] +#[doc(test(attr( + feature(cfg_target_has_reliable_f16_f128), + allow(internal_features, unused_features) +)))] impl f128 { /// The radix or base of the internal representation of `f128`. #[unstable(feature = "f128", issue = "116909")] @@ -278,14 +282,142 @@ impl f128 { #[unstable(feature = "f128", issue = "116909")] pub const NEG_INFINITY: f128 = -1.0_f128 / 0.0_f128; - /// Sign bit - pub(crate) const SIGN_MASK: u128 = 0x8000_0000_0000_0000_0000_0000_0000_0000; + /// Maximum integer that can be represented exactly in an [`f128`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i128`] and [`f128`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f128`] and back to + /// [`i128`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f128`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// [`MAX_EXACT_INTEGER`]: f128::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f128::MIN_EXACT_INTEGER + /// ``` + /// #![feature(f128)] + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// # #[cfg(target_has_reliable_f128)] { + /// let max_exact_int = f128::MAX_EXACT_INTEGER; + /// assert_eq!(max_exact_int, max_exact_int as f128 as i128); + /// assert_eq!(max_exact_int + 1, (max_exact_int + 1) as f128 as i128); + /// assert_ne!(max_exact_int + 2, (max_exact_int + 2) as f128 as i128); + /// + /// // Beyond `f128::MAX_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((max_exact_int + 1) as f128, (max_exact_int + 2) as f128); + /// # }} + /// ``` + // #[unstable(feature = "f128", issue = "116909")] + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MAX_EXACT_INTEGER: i128 = (1 << Self::MANTISSA_DIGITS) - 1; - /// Exponent mask - pub(crate) const EXP_MASK: u128 = 0x7fff_0000_0000_0000_0000_0000_0000_0000; + /// Minimum integer that can be represented exactly in an [`f128`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i128`] and [`f128`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f128`] and back to + /// [`i128`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f128`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// This constant is equivalent to `-MAX_EXACT_INTEGER`. + /// + /// [`MAX_EXACT_INTEGER`]: f128::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f128::MIN_EXACT_INTEGER + /// ``` + /// #![feature(f128)] + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// # #[cfg(target_has_reliable_f128)] { + /// let min_exact_int = f128::MIN_EXACT_INTEGER; + /// assert_eq!(min_exact_int, min_exact_int as f128 as i128); + /// assert_eq!(min_exact_int - 1, (min_exact_int - 1) as f128 as i128); + /// assert_ne!(min_exact_int - 2, (min_exact_int - 2) as f128 as i128); + /// + /// // Below `f128::MIN_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((min_exact_int - 1) as f128, (min_exact_int - 2) as f128); + /// # }} + /// ``` + // #[unstable(feature = "f128", issue = "116909")] + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MIN_EXACT_INTEGER: i128 = -Self::MAX_EXACT_INTEGER; - /// Mantissa mask - pub(crate) const MAN_MASK: u128 = 0x0000_ffff_ffff_ffff_ffff_ffff_ffff_ffff; + /// The mask of the bit used to encode the sign of an [`f128`]. + /// + /// This bit is set when the sign is negative and unset when the sign is + /// positive. + /// If you only need to check whether a value is positive or negative, + /// [`is_sign_positive`] or [`is_sign_negative`] can be used. + /// + /// [`is_sign_positive`]: f128::is_sign_positive + /// [`is_sign_negative`]: f128::is_sign_negative + /// ```rust + /// #![feature(float_masks)] + /// #![feature(f128)] + /// # #[cfg(target_has_reliable_f128)] { + /// let sign_mask = f128::SIGN_MASK; + /// let a = 1.6552f128; + /// let a_bits = a.to_bits(); + /// + /// assert_eq!(a_bits & sign_mask, 0x0); + /// assert_eq!(f128::from_bits(a_bits ^ sign_mask), -a); + /// assert_eq!(sign_mask, (-0.0f128).to_bits()); + /// # } + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const SIGN_MASK: u128 = 0x8000_0000_0000_0000_0000_0000_0000_0000; + + /// The mask of the bits used to encode the exponent of an [`f128`]. + /// + /// Note that the exponent is stored as a biased value, with a bias of 16383 for `f128`. + /// + /// ```rust + /// #![feature(float_masks)] + /// #![feature(f128)] + /// # #[cfg(target_has_reliable_f128)] { + /// fn get_exp(a: f128) -> i128 { + /// let bias = 16383; + /// let biased = a.to_bits() & f128::EXPONENT_MASK; + /// (biased >> (f128::MANTISSA_DIGITS - 1)).cast_signed() - bias + /// } + /// + /// assert_eq!(get_exp(0.5), -1); + /// assert_eq!(get_exp(1.0), 0); + /// assert_eq!(get_exp(2.0), 1); + /// assert_eq!(get_exp(4.0), 2); + /// # } + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const EXPONENT_MASK: u128 = 0x7fff_0000_0000_0000_0000_0000_0000_0000; + + /// The mask of the bits used to encode the mantissa of an [`f128`]. + /// + /// ```rust + /// #![feature(float_masks)] + /// #![feature(f128)] + /// # #[cfg(target_has_reliable_f128)] { + /// let mantissa_mask = f128::MANTISSA_MASK; + /// + /// assert_eq!(0f128.to_bits() & mantissa_mask, 0x0); + /// assert_eq!(1f128.to_bits() & mantissa_mask, 0x0); + /// + /// // multiplying a finite value by a power of 2 doesn't change its mantissa + /// // unless the result or initial value is not normal. + /// let a = 1.6552f128; + /// let b = 4.0 * a; + /// assert_eq!(a.to_bits() & mantissa_mask, b.to_bits() & mantissa_mask); + /// + /// // The maximum and minimum values have a saturated significand + /// assert_eq!(f128::MAX.to_bits() & f128::MANTISSA_MASK, f128::MANTISSA_MASK); + /// assert_eq!(f128::MIN.to_bits() & f128::MANTISSA_MASK, f128::MANTISSA_MASK); + /// # } + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const MANTISSA_MASK: u128 = 0x0000_ffff_ffff_ffff_ffff_ffff_ffff_ffff; /// Minimum representable positive value (min subnormal) const TINY_BITS: u128 = 0x1; @@ -447,11 +579,12 @@ impl f128 { /// ``` #[inline] #[unstable(feature = "f128", issue = "116909")] + #[must_use] pub const fn classify(self) -> FpCategory { let bits = self.to_bits(); - match (bits & Self::MAN_MASK, bits & Self::EXP_MASK) { - (0, Self::EXP_MASK) => FpCategory::Infinite, - (_, Self::EXP_MASK) => FpCategory::Nan, + match (bits & Self::MANTISSA_MASK, bits & Self::EXPONENT_MASK) { + (0, Self::EXPONENT_MASK) => FpCategory::Infinite, + (_, Self::EXPONENT_MASK) => FpCategory::Nan, (0, 0) => FpCategory::Zero, (_, 0) => FpCategory::Subnormal, _ => FpCategory::Normal, @@ -547,6 +680,7 @@ impl f128 { #[inline] #[doc(alias = "nextUp")] #[unstable(feature = "f128", issue = "116909")] + #[must_use = "method returns a new number and does not mutate the original value"] pub const fn next_up(self) -> Self { // Some targets violate Rust's assumption of IEEE semantics, e.g. by flushing // denormals to zero. This is in general unsound and unsupported, but here @@ -601,6 +735,7 @@ impl f128 { #[inline] #[doc(alias = "nextDown")] #[unstable(feature = "f128", issue = "116909")] + #[must_use = "method returns a new number and does not mutate the original value"] pub const fn next_down(self) -> Self { // Some targets violate Rust's assumption of IEEE semantics, e.g. by flushing // denormals to zero. This is in general unsound and unsupported, but here @@ -715,7 +850,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let x = 1.0f128; /// let y = 2.0f128; @@ -729,7 +864,7 @@ impl f128 { #[rustc_const_unstable(feature = "f128", issue = "116909")] #[must_use = "this returns the result of the comparison, without modifying either input"] pub const fn max(self, other: f128) -> f128 { - intrinsics::maxnumf128(self, other) + intrinsics::maximum_number_nsz_f128(self, other) } /// Returns the minimum of the two numbers, ignoring NaN. @@ -746,7 +881,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let x = 1.0f128; /// let y = 2.0f128; @@ -760,7 +895,7 @@ impl f128 { #[rustc_const_unstable(feature = "f128", issue = "116909")] #[must_use = "this returns the result of the comparison, without modifying either input"] pub const fn min(self, other: f128) -> f128 { - intrinsics::minnumf128(self, other) + intrinsics::minimum_number_nsz_f128(self, other) } /// Returns the maximum of the two numbers, propagating NaN. @@ -778,7 +913,7 @@ impl f128 { /// ``` /// #![feature(f128)] /// #![feature(float_minimum_maximum)] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let x = 1.0f128; /// let y = 2.0f128; @@ -810,7 +945,7 @@ impl f128 { /// ``` /// #![feature(f128)] /// #![feature(float_minimum_maximum)] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let x = 1.0f128; /// let y = 2.0f128; @@ -846,8 +981,10 @@ impl f128 { #[doc(alias = "average")] #[unstable(feature = "f128", issue = "116909")] #[rustc_const_unstable(feature = "f128", issue = "116909")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] pub const fn midpoint(self, other: f128) -> f128 { - const HI: f128 = f128::MAX / 2.; + const HI: f128 = f128::MAX * 0.5; let (a, b) = (self, other); let abs_a = a.abs(); @@ -855,9 +992,9 @@ impl f128 { if abs_a <= HI && abs_b <= HI { // Overflow is impossible - (a + b) / 2. + (a + b) * 0.5 } else { - (a / 2.) + (b / 2.) + (a * 0.5) + (b * 0.5) } } @@ -1350,7 +1487,7 @@ impl f128 { #[rustc_const_unstable(feature = "f128", issue = "116909")] #[must_use = "method returns a new number and does not mutate the original value"] pub const fn abs(self) -> Self { - intrinsics::fabsf128(self) + intrinsics::fabs(self) } /// Returns a number that represents the sign of `self`. @@ -1423,8 +1560,8 @@ impl f128 { /// /// See [algebraic operators](primitive@f32#algebraic-operators) for more info. #[must_use = "method returns a new number and does not mutate the original value"] - #[unstable(feature = "float_algebraic", issue = "136469")] - #[rustc_const_unstable(feature = "float_algebraic", issue = "136469")] + #[unstable(feature = "f128", issue = "116909")] + #[rustc_const_unstable(feature = "f128", issue = "116909")] #[inline] pub const fn algebraic_add(self, rhs: f128) -> f128 { intrinsics::fadd_algebraic(self, rhs) @@ -1434,8 +1571,8 @@ impl f128 { /// /// See [algebraic operators](primitive@f32#algebraic-operators) for more info. #[must_use = "method returns a new number and does not mutate the original value"] - #[unstable(feature = "float_algebraic", issue = "136469")] - #[rustc_const_unstable(feature = "float_algebraic", issue = "136469")] + #[unstable(feature = "f128", issue = "116909")] + #[rustc_const_unstable(feature = "f128", issue = "116909")] #[inline] pub const fn algebraic_sub(self, rhs: f128) -> f128 { intrinsics::fsub_algebraic(self, rhs) @@ -1445,8 +1582,8 @@ impl f128 { /// /// See [algebraic operators](primitive@f32#algebraic-operators) for more info. #[must_use = "method returns a new number and does not mutate the original value"] - #[unstable(feature = "float_algebraic", issue = "136469")] - #[rustc_const_unstable(feature = "float_algebraic", issue = "136469")] + #[unstable(feature = "f128", issue = "116909")] + #[rustc_const_unstable(feature = "f128", issue = "116909")] #[inline] pub const fn algebraic_mul(self, rhs: f128) -> f128 { intrinsics::fmul_algebraic(self, rhs) @@ -1456,8 +1593,8 @@ impl f128 { /// /// See [algebraic operators](primitive@f32#algebraic-operators) for more info. #[must_use = "method returns a new number and does not mutate the original value"] - #[unstable(feature = "float_algebraic", issue = "136469")] - #[rustc_const_unstable(feature = "float_algebraic", issue = "136469")] + #[unstable(feature = "f128", issue = "116909")] + #[rustc_const_unstable(feature = "f128", issue = "116909")] #[inline] pub const fn algebraic_div(self, rhs: f128) -> f128 { intrinsics::fdiv_algebraic(self, rhs) @@ -1467,18 +1604,49 @@ impl f128 { /// /// See [algebraic operators](primitive@f32#algebraic-operators) for more info. #[must_use = "method returns a new number and does not mutate the original value"] - #[unstable(feature = "float_algebraic", issue = "136469")] - #[rustc_const_unstable(feature = "float_algebraic", issue = "136469")] + #[unstable(feature = "f128", issue = "116909")] + #[rustc_const_unstable(feature = "f128", issue = "116909")] #[inline] pub const fn algebraic_rem(self, rhs: f128) -> f128 { intrinsics::frem_algebraic(self, rhs) } + + /// Returns `self` if the value is not NaN, otherwise returns `replacement` + /// if `self` is NaN. + /// + /// # Examples + /// + /// ``` + /// #![feature(f128)] + /// #![feature(float_nan_to)] + /// # #[cfg(target_has_reliable_f128)] { + /// + /// let n = f128::NAN; + /// let x = 2.0f128; + /// let y = f128::INFINITY; + /// + /// assert_eq!(n.nan_to(0.0f128), 0.0f128); + /// assert_eq!(x.nan_to(0.0f128), 2.0f128); + /// assert_eq!(y.nan_to(0.0f128), f128::INFINITY); + /// # } + /// ``` + #[must_use = "method returns a new float and does not mutate the original value"] + #[unstable(feature = "float_nan_to", issue = "161248")] + #[rustc_const_unstable(feature = "float_nan_to", issue = "161248")] + #[inline] + pub const fn nan_to(self, replacement: f128) -> f128 { + if self.is_nan() { replacement } else { self } + } } // Functions in this module fall into `core_float_math` // #[unstable(feature = "core_float_math", issue = "137578")] #[cfg(not(test))] -#[doc(test(attr(feature(cfg_target_has_reliable_f16_f128), expect(internal_features))))] +#[doc(test(attr( + feature(cfg_target_has_reliable_f16_f128), + expect(internal_features), + allow(unused_features) +)))] impl f128 { /// Returns the largest integer less than or equal to `self`. /// @@ -1488,8 +1656,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let f = 3.7_f128; /// let g = 3.0_f128; @@ -1517,8 +1684,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let f = 3.01_f128; /// let g = 4.0_f128; @@ -1546,8 +1712,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let f = 3.3_f128; /// let g = -3.3_f128; @@ -1580,8 +1745,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let f = 3.3_f128; /// let g = -3.3_f128; @@ -1612,8 +1776,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let f = 3.7_f128; /// let g = 3.0_f128; @@ -1642,8 +1805,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let x = 3.6_f128; /// let y = -3.6_f128; @@ -1681,8 +1843,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let m = 10.0_f128; /// let x = 4.0_f128; @@ -1726,8 +1887,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let a: f128 = 7.0; /// let b = 4.0; @@ -1770,8 +1930,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let a: f128 = 7.0; /// let b = 4.0; @@ -1813,12 +1972,11 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = 2.0_f128; /// let abs_difference = (x.powi(2) - (x * x)).abs(); - /// assert!(abs_difference <= f128::EPSILON); + /// assert!(abs_difference <= 1e-9); /// /// assert_eq!(f128::powi(f128::NAN, 0), 1.0); /// assert_eq!(f128::powi(0.0, 0), 1.0); @@ -1846,8 +2004,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let positive = 4.0_f128; /// let negative = -4.0_f128; diff --git a/library/core/src/num/f16.rs b/library/core/src/num/f16.rs index 7d05c3592ea2a..170a34e8610a3 100644 --- a/library/core/src/num/f16.rs +++ b/library/core/src/num/f16.rs @@ -18,7 +18,7 @@ use crate::convert::FloatToInt; use crate::kani; use crate::num::FpCategory; #[cfg(not(test))] -use crate::num::libm; +use crate::num::imp::libm; use crate::panic::const_assert; #[allow(unused_imports)] use crate::ub_checks::float_to_int_in_range; @@ -41,6 +41,7 @@ pub mod consts { pub const TAU: f16 = 6.28318530717958647692528676655900577_f16; /// The golden ratio (φ) + #[doc(alias = "phi")] #[unstable(feature = "f16", issue = "116909")] pub const GOLDEN_RATIO: f16 = 1.618033988749894848204586834365638118_f16; @@ -148,7 +149,10 @@ pub mod consts { pub const LN_10: f16 = 2.30258509299404568401799145468436421_f16; } -#[doc(test(attr(feature(cfg_target_has_reliable_f16_f128), allow(internal_features))))] +#[doc(test(attr( + feature(cfg_target_has_reliable_f16_f128), + allow(internal_features, unused_features) +)))] impl f16 { /// The radix or base of the internal representation of `f16`. #[unstable(feature = "f16", issue = "116909")] @@ -272,14 +276,144 @@ impl f16 { #[unstable(feature = "f16", issue = "116909")] pub const NEG_INFINITY: f16 = -1.0_f16 / 0.0_f16; - /// Sign bit - pub(crate) const SIGN_MASK: u16 = 0x8000; + /// Maximum integer that can be represented exactly in an [`f16`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i16`] and [`f16`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f16`] and back to + /// [`i16`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f16`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// [`MAX_EXACT_INTEGER`]: f16::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f16::MIN_EXACT_INTEGER + /// ``` + /// #![feature(f16)] + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// # #[cfg(target_has_reliable_f16)] { + /// let max_exact_int = f16::MAX_EXACT_INTEGER; + /// assert_eq!(max_exact_int, max_exact_int as f16 as i16); + /// assert_eq!(max_exact_int + 1, (max_exact_int + 1) as f16 as i16); + /// assert_ne!(max_exact_int + 2, (max_exact_int + 2) as f16 as i16); + /// + /// // Beyond `f16::MAX_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((max_exact_int + 1) as f16, (max_exact_int + 2) as f16); + /// # }} + /// ``` + // #[unstable(feature = "f16", issue = "116909")] + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MAX_EXACT_INTEGER: i16 = (1 << Self::MANTISSA_DIGITS) - 1; + + /// Minimum integer that can be represented exactly in an [`f16`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i16`] and [`f16`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f16`] and back to + /// [`i16`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f16`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// This constant is equivalent to `-MAX_EXACT_INTEGER`. + /// + /// [`MAX_EXACT_INTEGER`]: f16::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f16::MIN_EXACT_INTEGER + /// ``` + /// #![feature(f16)] + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// # #[cfg(target_has_reliable_f16)] { + /// let min_exact_int = f16::MIN_EXACT_INTEGER; + /// assert_eq!(min_exact_int, min_exact_int as f16 as i16); + /// assert_eq!(min_exact_int - 1, (min_exact_int - 1) as f16 as i16); + /// assert_ne!(min_exact_int - 2, (min_exact_int - 2) as f16 as i16); + /// + /// // Below `f16::MIN_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((min_exact_int - 1) as f16, (min_exact_int - 2) as f16); + /// # }} + /// ``` + // #[unstable(feature = "f16", issue = "116909")] + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MIN_EXACT_INTEGER: i16 = -Self::MAX_EXACT_INTEGER; - /// Exponent mask - pub(crate) const EXP_MASK: u16 = 0x7c00; + /// The mask of the bit used to encode the sign of an [`f16`]. + /// + /// This bit is set when the sign is negative and unset when the sign is + /// positive. + /// If you only need to check whether a value is positive or negative, + /// [`is_sign_positive`] or [`is_sign_negative`] can be used. + /// + /// [`is_sign_positive`]: f16::is_sign_positive + /// [`is_sign_negative`]: f16::is_sign_negative + /// ```rust + /// #![feature(float_masks)] + /// #![feature(f16)] + /// # #[cfg(target_has_reliable_f16)] { + /// let sign_mask = f16::SIGN_MASK; + /// let a = 1.6552f16; + /// let a_bits = a.to_bits(); + /// + /// assert_eq!(a_bits & sign_mask, 0x0); + /// assert_eq!(f16::from_bits(a_bits ^ sign_mask), -a); + /// assert_eq!(sign_mask, (-0.0f16).to_bits()); + /// # } + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const SIGN_MASK: u16 = 0x8000; - /// Mantissa mask - pub(crate) const MAN_MASK: u16 = 0x03ff; + /// The mask of the bits used to encode the exponent of an [`f16`]. + /// + /// Note that the exponent is stored as a biased value, with a bias of 15 for `f16`. + /// + /// ```rust + /// #![feature(float_masks)] + /// #![feature(f16)] + /// # #[cfg(target_has_reliable_f16)] { + /// let exponent_mask = f16::EXPONENT_MASK; + /// + /// fn get_exp(a: f16) -> i16 { + /// let bias = 15; + /// let biased = a.to_bits() & f16::EXPONENT_MASK; + /// (biased >> (f16::MANTISSA_DIGITS - 1)).cast_signed() - bias + /// } + /// + /// assert_eq!(get_exp(0.5), -1); + /// assert_eq!(get_exp(1.0), 0); + /// assert_eq!(get_exp(2.0), 1); + /// assert_eq!(get_exp(4.0), 2); + /// # } + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const EXPONENT_MASK: u16 = 0x7c00; + + /// The mask of the bits used to encode the mantissa of an [`f16`]. + /// + /// ```rust + /// #![feature(float_masks)] + /// #![feature(f16)] + /// # #[cfg(target_has_reliable_f16)] { + /// let mantissa_mask = f16::MANTISSA_MASK; + /// + /// assert_eq!(0f16.to_bits() & mantissa_mask, 0x0); + /// assert_eq!(1f16.to_bits() & mantissa_mask, 0x0); + /// + /// // multiplying a finite value by a power of 2 doesn't change its mantissa + /// // unless the result or initial value is not normal. + /// let a = 1.6552f16; + /// let b = 4.0 * a; + /// assert_eq!(a.to_bits() & mantissa_mask, b.to_bits() & mantissa_mask); + /// + /// // The maximum and minimum values have a saturated significand + /// assert_eq!(f16::MAX.to_bits() & f16::MANTISSA_MASK, f16::MANTISSA_MASK); + /// assert_eq!(f16::MIN.to_bits() & f16::MANTISSA_MASK, f16::MANTISSA_MASK); + /// # } + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const MANTISSA_MASK: u16 = 0x03ff; /// Minimum representable positive value (min subnormal) const TINY_BITS: u16 = 0x1; @@ -439,11 +573,12 @@ impl f16 { /// ``` #[inline] #[unstable(feature = "f16", issue = "116909")] + #[must_use] pub const fn classify(self) -> FpCategory { let b = self.to_bits(); - match (b & Self::MAN_MASK, b & Self::EXP_MASK) { - (0, Self::EXP_MASK) => FpCategory::Infinite, - (_, Self::EXP_MASK) => FpCategory::Nan, + match (b & Self::MANTISSA_MASK, b & Self::EXPONENT_MASK) { + (0, Self::EXPONENT_MASK) => FpCategory::Infinite, + (_, Self::EXPONENT_MASK) => FpCategory::Nan, (0, 0) => FpCategory::Zero, (_, 0) => FpCategory::Subnormal, _ => FpCategory::Normal, @@ -543,6 +678,7 @@ impl f16 { #[inline] #[doc(alias = "nextUp")] #[unstable(feature = "f16", issue = "116909")] + #[must_use = "method returns a new number and does not mutate the original value"] pub const fn next_up(self) -> Self { // Some targets violate Rust's assumption of IEEE semantics, e.g. by flushing // denormals to zero. This is in general unsound and unsupported, but here @@ -597,6 +733,7 @@ impl f16 { #[inline] #[doc(alias = "nextDown")] #[unstable(feature = "f16", issue = "116909")] + #[must_use = "method returns a new number and does not mutate the original value"] pub const fn next_down(self) -> Self { // Some targets violate Rust's assumption of IEEE semantics, e.g. by flushing // denormals to zero. This is in general unsound and unsupported, but here @@ -723,7 +860,7 @@ impl f16 { #[rustc_const_unstable(feature = "f16", issue = "116909")] #[must_use = "this returns the result of the comparison, without modifying either input"] pub const fn max(self, other: f16) -> f16 { - intrinsics::maxnumf16(self, other) + intrinsics::maximum_number_nsz_f16(self, other) } /// Returns the minimum of the two numbers, ignoring NaN. @@ -754,7 +891,7 @@ impl f16 { #[rustc_const_unstable(feature = "f16", issue = "116909")] #[must_use = "this returns the result of the comparison, without modifying either input"] pub const fn min(self, other: f16) -> f16 { - intrinsics::minnumf16(self, other) + intrinsics::minimum_number_nsz_f16(self, other) } /// Returns the maximum of the two numbers, propagating NaN. @@ -840,8 +977,10 @@ impl f16 { #[doc(alias = "average")] #[unstable(feature = "f16", issue = "116909")] #[rustc_const_unstable(feature = "f16", issue = "116909")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] pub const fn midpoint(self, other: f16) -> f16 { - const HI: f16 = f16::MAX / 2.; + const HI: f16 = f16::MAX * 0.5; let (a, b) = (self, other); let abs_a = a.abs(); @@ -849,9 +988,9 @@ impl f16 { if abs_a <= HI && abs_b <= HI { // Overflow is impossible - (a + b) / 2. + (a + b) * 0.5 } else { - (a / 2.) + (b / 2.) + (a * 0.5) + (b * 0.5) } } @@ -1317,7 +1456,7 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(target_has_reliable_f16_math)] { + /// # #[cfg(target_has_reliable_f16)] { /// /// let x = 3.5_f16; /// let y = -3.5_f16; @@ -1333,7 +1472,7 @@ impl f16 { #[rustc_const_unstable(feature = "f16", issue = "116909")] #[must_use = "method returns a new number and does not mutate the original value"] pub const fn abs(self) -> Self { - intrinsics::fabsf16(self) + intrinsics::fabs(self) } /// Returns a number that represents the sign of `self`. @@ -1382,7 +1521,7 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(target_has_reliable_f16_math)] { + /// # #[cfg(target_has_reliable_f16)] { /// /// let f = 3.5_f16; /// @@ -1406,8 +1545,8 @@ impl f16 { /// /// See [algebraic operators](primitive@f32#algebraic-operators) for more info. #[must_use = "method returns a new number and does not mutate the original value"] - #[unstable(feature = "float_algebraic", issue = "136469")] - #[rustc_const_unstable(feature = "float_algebraic", issue = "136469")] + #[unstable(feature = "f16", issue = "116909")] + #[rustc_const_unstable(feature = "f16", issue = "116909")] #[inline] pub const fn algebraic_add(self, rhs: f16) -> f16 { intrinsics::fadd_algebraic(self, rhs) @@ -1417,8 +1556,8 @@ impl f16 { /// /// See [algebraic operators](primitive@f32#algebraic-operators) for more info. #[must_use = "method returns a new number and does not mutate the original value"] - #[unstable(feature = "float_algebraic", issue = "136469")] - #[rustc_const_unstable(feature = "float_algebraic", issue = "136469")] + #[unstable(feature = "f16", issue = "116909")] + #[rustc_const_unstable(feature = "f16", issue = "116909")] #[inline] pub const fn algebraic_sub(self, rhs: f16) -> f16 { intrinsics::fsub_algebraic(self, rhs) @@ -1428,8 +1567,8 @@ impl f16 { /// /// See [algebraic operators](primitive@f32#algebraic-operators) for more info. #[must_use = "method returns a new number and does not mutate the original value"] - #[unstable(feature = "float_algebraic", issue = "136469")] - #[rustc_const_unstable(feature = "float_algebraic", issue = "136469")] + #[unstable(feature = "f16", issue = "116909")] + #[rustc_const_unstable(feature = "f16", issue = "116909")] #[inline] pub const fn algebraic_mul(self, rhs: f16) -> f16 { intrinsics::fmul_algebraic(self, rhs) @@ -1439,8 +1578,8 @@ impl f16 { /// /// See [algebraic operators](primitive@f32#algebraic-operators) for more info. #[must_use = "method returns a new number and does not mutate the original value"] - #[unstable(feature = "float_algebraic", issue = "136469")] - #[rustc_const_unstable(feature = "float_algebraic", issue = "136469")] + #[unstable(feature = "f16", issue = "116909")] + #[rustc_const_unstable(feature = "f16", issue = "116909")] #[inline] pub const fn algebraic_div(self, rhs: f16) -> f16 { intrinsics::fdiv_algebraic(self, rhs) @@ -1450,18 +1589,49 @@ impl f16 { /// /// See [algebraic operators](primitive@f32#algebraic-operators) for more info. #[must_use = "method returns a new number and does not mutate the original value"] - #[unstable(feature = "float_algebraic", issue = "136469")] - #[rustc_const_unstable(feature = "float_algebraic", issue = "136469")] + #[unstable(feature = "f16", issue = "116909")] + #[rustc_const_unstable(feature = "f16", issue = "116909")] #[inline] pub const fn algebraic_rem(self, rhs: f16) -> f16 { intrinsics::frem_algebraic(self, rhs) } + + /// Returns `self` if the value is not NaN, otherwise returns `replacement` + /// if `self` is NaN. + /// + /// # Examples + /// + /// ``` + /// #![feature(f16)] + /// #![feature(float_nan_to)] + /// # #[cfg(target_has_reliable_f16)] { + /// + /// let n = f16::NAN; + /// let x = 2.0f16; + /// let y = f16::INFINITY; + /// + /// assert_eq!(n.nan_to(0.0f16), 0.0f16); + /// assert_eq!(x.nan_to(0.0f16), 2.0f16); + /// assert_eq!(y.nan_to(0.0f16), f16::INFINITY); + /// # } + /// ``` + #[must_use = "method returns a new float and does not mutate the original value"] + #[unstable(feature = "float_nan_to", issue = "161248")] + #[rustc_const_unstable(feature = "float_nan_to", issue = "161248")] + #[inline] + pub const fn nan_to(self, replacement: f16) -> f16 { + if self.is_nan() { replacement } else { self } + } } // Functions in this module fall into `core_float_math` // #[unstable(feature = "core_float_math", issue = "137578")] #[cfg(not(test))] -#[doc(test(attr(feature(cfg_target_has_reliable_f16_f128), expect(internal_features))))] +#[doc(test(attr( + feature(cfg_target_has_reliable_f16_f128), + expect(internal_features), + allow(unused_features) +)))] impl f16 { /// Returns the largest integer less than or equal to `self`. /// @@ -1471,7 +1641,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16)] { /// /// let f = 3.7_f16; @@ -1500,7 +1669,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16)] { /// /// let f = 3.01_f16; @@ -1529,7 +1697,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16)] { /// /// let f = 3.3_f16; @@ -1563,7 +1730,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16)] { /// /// let f = 3.3_f16; @@ -1595,7 +1761,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16)] { /// /// let f = 3.7_f16; @@ -1625,7 +1790,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16)] { /// /// let x = 3.6_f16; @@ -1664,7 +1828,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16)] { /// /// let m = 10.0_f16; @@ -1709,7 +1872,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16)] { /// /// let a: f16 = 7.0; @@ -1753,7 +1915,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16)] { /// /// let a: f16 = 7.0; @@ -1796,12 +1957,11 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] - /// # #[cfg(target_has_reliable_f16)] { + /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = 2.0_f16; /// let abs_difference = (x.powi(2) - (x * x)).abs(); - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 0.1); /// /// assert_eq!(f16::powi(f16::NAN, 0), 1.0); /// assert_eq!(f16::powi(0.0, 0), 1.0); @@ -1829,7 +1989,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16)] { /// /// let positive = 4.0_f16; @@ -1864,7 +2023,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16)] { /// /// let x = 8.0f16; diff --git a/library/core/src/num/f32.rs b/library/core/src/num/f32.rs index 9fbe4a3795649..ea6d1ca471cc3 100644 --- a/library/core/src/num/f32.rs +++ b/library/core/src/num/f32.rs @@ -29,14 +29,14 @@ use crate::{cfg_select, intrinsics, mem}; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let r = std::f32::RADIX; /// /// // intended way /// let r = f32::RADIX; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `RADIX` associated constant on `f32`")] +#[deprecated(since = "1.99.0", note = "replaced by the `RADIX` associated constant on `f32`")] #[rustc_diagnostic_item = "f32_legacy_const_radix"] pub const RADIX: u32 = f32::RADIX; @@ -47,7 +47,7 @@ pub const RADIX: u32 = f32::RADIX; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let d = std::f32::MANTISSA_DIGITS; /// /// // intended way @@ -55,7 +55,7 @@ pub const RADIX: u32 = f32::RADIX; /// ``` #[stable(feature = "rust1", since = "1.0.0")] #[deprecated( - since = "TBD", + since = "1.99.0", note = "replaced by the `MANTISSA_DIGITS` associated constant on `f32`" )] #[rustc_diagnostic_item = "f32_legacy_const_mantissa_dig"] @@ -68,14 +68,14 @@ pub const MANTISSA_DIGITS: u32 = f32::MANTISSA_DIGITS; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let d = std::f32::DIGITS; /// /// // intended way /// let d = f32::DIGITS; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `DIGITS` associated constant on `f32`")] +#[deprecated(since = "1.99.0", note = "replaced by the `DIGITS` associated constant on `f32`")] #[rustc_diagnostic_item = "f32_legacy_const_digits"] pub const DIGITS: u32 = f32::DIGITS; @@ -90,14 +90,14 @@ pub const DIGITS: u32 = f32::DIGITS; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let e = std::f32::EPSILON; /// /// // intended way /// let e = f32::EPSILON; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `EPSILON` associated constant on `f32`")] +#[deprecated(since = "1.99.0", note = "replaced by the `EPSILON` associated constant on `f32`")] #[rustc_diagnostic_item = "f32_legacy_const_epsilon"] pub const EPSILON: f32 = f32::EPSILON; @@ -108,14 +108,14 @@ pub const EPSILON: f32 = f32::EPSILON; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let min = std::f32::MIN; /// /// // intended way /// let min = f32::MIN; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `MIN` associated constant on `f32`")] +#[deprecated(since = "1.99.0", note = "replaced by the `MIN` associated constant on `f32`")] #[rustc_diagnostic_item = "f32_legacy_const_min"] pub const MIN: f32 = f32::MIN; @@ -126,14 +126,17 @@ pub const MIN: f32 = f32::MIN; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let min = std::f32::MIN_POSITIVE; /// /// // intended way /// let min = f32::MIN_POSITIVE; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `MIN_POSITIVE` associated constant on `f32`")] +#[deprecated( + since = "1.99.0", + note = "replaced by the `MIN_POSITIVE` associated constant on `f32`" +)] #[rustc_diagnostic_item = "f32_legacy_const_min_positive"] pub const MIN_POSITIVE: f32 = f32::MIN_POSITIVE; @@ -144,14 +147,14 @@ pub const MIN_POSITIVE: f32 = f32::MIN_POSITIVE; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let max = std::f32::MAX; /// /// // intended way /// let max = f32::MAX; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `MAX` associated constant on `f32`")] +#[deprecated(since = "1.99.0", note = "replaced by the `MAX` associated constant on `f32`")] #[rustc_diagnostic_item = "f32_legacy_const_max"] pub const MAX: f32 = f32::MAX; @@ -162,14 +165,14 @@ pub const MAX: f32 = f32::MAX; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let min = std::f32::MIN_EXP; /// /// // intended way /// let min = f32::MIN_EXP; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `MIN_EXP` associated constant on `f32`")] +#[deprecated(since = "1.99.0", note = "replaced by the `MIN_EXP` associated constant on `f32`")] #[rustc_diagnostic_item = "f32_legacy_const_min_exp"] pub const MIN_EXP: i32 = f32::MIN_EXP; @@ -180,14 +183,14 @@ pub const MIN_EXP: i32 = f32::MIN_EXP; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let max = std::f32::MAX_EXP; /// /// // intended way /// let max = f32::MAX_EXP; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `MAX_EXP` associated constant on `f32`")] +#[deprecated(since = "1.99.0", note = "replaced by the `MAX_EXP` associated constant on `f32`")] #[rustc_diagnostic_item = "f32_legacy_const_max_exp"] pub const MAX_EXP: i32 = f32::MAX_EXP; @@ -198,14 +201,14 @@ pub const MAX_EXP: i32 = f32::MAX_EXP; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let min = std::f32::MIN_10_EXP; /// /// // intended way /// let min = f32::MIN_10_EXP; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `MIN_10_EXP` associated constant on `f32`")] +#[deprecated(since = "1.99.0", note = "replaced by the `MIN_10_EXP` associated constant on `f32`")] #[rustc_diagnostic_item = "f32_legacy_const_min_10_exp"] pub const MIN_10_EXP: i32 = f32::MIN_10_EXP; @@ -216,14 +219,14 @@ pub const MIN_10_EXP: i32 = f32::MIN_10_EXP; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let max = std::f32::MAX_10_EXP; /// /// // intended way /// let max = f32::MAX_10_EXP; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `MAX_10_EXP` associated constant on `f32`")] +#[deprecated(since = "1.99.0", note = "replaced by the `MAX_10_EXP` associated constant on `f32`")] #[rustc_diagnostic_item = "f32_legacy_const_max_10_exp"] pub const MAX_10_EXP: i32 = f32::MAX_10_EXP; @@ -234,14 +237,14 @@ pub const MAX_10_EXP: i32 = f32::MAX_10_EXP; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let nan = std::f32::NAN; /// /// // intended way /// let nan = f32::NAN; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `NAN` associated constant on `f32`")] +#[deprecated(since = "1.99.0", note = "replaced by the `NAN` associated constant on `f32`")] #[rustc_diagnostic_item = "f32_legacy_const_nan"] pub const NAN: f32 = f32::NAN; @@ -252,14 +255,14 @@ pub const NAN: f32 = f32::NAN; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let inf = std::f32::INFINITY; /// /// // intended way /// let inf = f32::INFINITY; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `INFINITY` associated constant on `f32`")] +#[deprecated(since = "1.99.0", note = "replaced by the `INFINITY` associated constant on `f32`")] #[rustc_diagnostic_item = "f32_legacy_const_infinity"] pub const INFINITY: f32 = f32::INFINITY; @@ -270,14 +273,17 @@ pub const INFINITY: f32 = f32::INFINITY; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let ninf = std::f32::NEG_INFINITY; /// /// // intended way /// let ninf = f32::NEG_INFINITY; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `NEG_INFINITY` associated constant on `f32`")] +#[deprecated( + since = "1.99.0", + note = "replaced by the `NEG_INFINITY` associated constant on `f32`" +)] #[rustc_diagnostic_item = "f32_legacy_const_neg_infinity"] pub const NEG_INFINITY: f32 = f32::NEG_INFINITY; @@ -298,6 +304,7 @@ pub mod consts { pub const TAU: f32 = 6.28318530717958647692528676655900577_f32; /// The golden ratio (φ) + #[doc(alias = "phi")] #[stable(feature = "euler_gamma_golden_ratio", since = "1.94.0")] pub const GOLDEN_RATIO: f32 = 1.618033988749894848204586834365638118_f32; @@ -399,6 +406,7 @@ pub mod consts { pub const LN_10: f32 = 2.30258509299404568401799145468436421_f32; } +#[doc(test(attr(allow(unused_features))))] impl f32 { /// The radix or base of the internal representation of `f32`. #[stable(feature = "assoc_int_consts", since = "1.43.0")] @@ -510,7 +518,7 @@ impl f32 { /// The concrete bit pattern may change across Rust versions and target platforms. #[stable(feature = "assoc_int_consts", since = "1.43.0")] #[rustc_diagnostic_item = "f32_nan"] - #[allow(clippy::eq_op)] + #[allow(clippy::eq_op, clippy::zero_divided_by_zero)] pub const NAN: f32 = 0.0_f32 / 0.0_f32; /// Infinity (∞). #[stable(feature = "assoc_int_consts", since = "1.43.0")] @@ -519,14 +527,127 @@ impl f32 { #[stable(feature = "assoc_int_consts", since = "1.43.0")] pub const NEG_INFINITY: f32 = -1.0_f32 / 0.0_f32; - /// Sign bit - pub(crate) const SIGN_MASK: u32 = 0x8000_0000; + /// Maximum integer that can be represented exactly in an [`f32`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i32`] and [`f32`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f32`] and back to + /// [`i32`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f32`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// [`MAX_EXACT_INTEGER`]: f32::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f32::MIN_EXACT_INTEGER + /// ``` + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// let max_exact_int = f32::MAX_EXACT_INTEGER; + /// assert_eq!(max_exact_int, max_exact_int as f32 as i32); + /// assert_eq!(max_exact_int + 1, (max_exact_int + 1) as f32 as i32); + /// assert_ne!(max_exact_int + 2, (max_exact_int + 2) as f32 as i32); + /// + /// // Beyond `f32::MAX_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((max_exact_int + 1) as f32, (max_exact_int + 2) as f32); + /// # } + /// ``` + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MAX_EXACT_INTEGER: i32 = (1 << Self::MANTISSA_DIGITS) - 1; + + /// Minimum integer that can be represented exactly in an [`f32`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i32`] and [`f32`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f32`] and back to + /// [`i32`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f32`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// This constant is equivalent to `-MAX_EXACT_INTEGER`. + /// + /// [`MAX_EXACT_INTEGER`]: f32::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f32::MIN_EXACT_INTEGER + /// ``` + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// let min_exact_int = f32::MIN_EXACT_INTEGER; + /// assert_eq!(min_exact_int, min_exact_int as f32 as i32); + /// assert_eq!(min_exact_int - 1, (min_exact_int - 1) as f32 as i32); + /// assert_ne!(min_exact_int - 2, (min_exact_int - 2) as f32 as i32); + /// + /// // Below `f32::MIN_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((min_exact_int - 1) as f32, (min_exact_int - 2) as f32); + /// # } + /// ``` + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MIN_EXACT_INTEGER: i32 = -Self::MAX_EXACT_INTEGER; + + /// The mask of the bit used to encode the sign of an [`f32`]. + /// + /// This bit is set when the sign is negative and unset when the sign is + /// positive. + /// If you only need to check whether a value is positive or negative, + /// [`is_sign_positive`] or [`is_sign_negative`] can be used. + /// + /// [`is_sign_positive`]: f32::is_sign_positive + /// [`is_sign_negative`]: f32::is_sign_negative + /// ```rust + /// #![feature(float_masks)] + /// let sign_mask = f32::SIGN_MASK; + /// let a = 1.6552f32; + /// let a_bits = a.to_bits(); + /// + /// assert_eq!(a_bits & sign_mask, 0x0); + /// assert_eq!(f32::from_bits(a_bits ^ sign_mask), -a); + /// assert_eq!(sign_mask, (-0.0f32).to_bits()); + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const SIGN_MASK: u32 = 0x8000_0000; - /// Exponent mask - pub(crate) const EXP_MASK: u32 = 0x7f80_0000; + /// The mask of the bits used to encode the exponent of an [`f32`]. + /// + /// Note that the exponent is stored as a biased value, with a bias of 127 for `f32`. + /// + /// ```rust + /// #![feature(float_masks)] + /// fn get_exp(a: f32) -> i32 { + /// let bias = 127; + /// let biased = a.to_bits() & f32::EXPONENT_MASK; + /// (biased >> (f32::MANTISSA_DIGITS - 1)).cast_signed() - bias + /// } + /// + /// assert_eq!(get_exp(0.5), -1); + /// assert_eq!(get_exp(1.0), 0); + /// assert_eq!(get_exp(2.0), 1); + /// assert_eq!(get_exp(4.0), 2); + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const EXPONENT_MASK: u32 = 0x7f80_0000; - /// Mantissa mask - pub(crate) const MAN_MASK: u32 = 0x007f_ffff; + /// The mask of the bits used to encode the mantissa of an [`f32`]. + /// + /// ```rust + /// #![feature(float_masks)] + /// let mantissa_mask = f32::MANTISSA_MASK; + /// + /// assert_eq!(0f32.to_bits() & mantissa_mask, 0x0); + /// assert_eq!(1f32.to_bits() & mantissa_mask, 0x0); + /// + /// // multiplying a finite value by a power of 2 doesn't change its mantissa + /// // unless the result or initial value is not normal. + /// let a = 1.6552f32; + /// let b = 4.0 * a; + /// assert_eq!(a.to_bits() & mantissa_mask, b.to_bits() & mantissa_mask); + /// + /// // The maximum and minimum values have a saturated significand + /// assert_eq!(f32::MAX.to_bits() & f32::MANTISSA_MASK, f32::MANTISSA_MASK); + /// assert_eq!(f32::MIN.to_bits() & f32::MANTISSA_MASK, f32::MANTISSA_MASK); + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const MANTISSA_MASK: u32 = 0x007f_ffff; /// Minimum representable positive value (min subnormal) const TINY_BITS: u32 = 0x1; @@ -670,6 +791,7 @@ impl f32 { /// ``` #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_stable(feature = "const_float_classify", since = "1.83.0")] + #[must_use] pub const fn classify(self) -> FpCategory { // We used to have complicated logic here that avoids the simple bit-based tests to work // around buggy codegen for x87 targets (see @@ -677,9 +799,9 @@ impl f32 { // of our tests is able to find any difference between the complicated and the naive // version, so now we are back to the naive version. let b = self.to_bits(); - match (b & Self::MAN_MASK, b & Self::EXP_MASK) { - (0, Self::EXP_MASK) => FpCategory::Infinite, - (_, Self::EXP_MASK) => FpCategory::Nan, + match (b & Self::MANTISSA_MASK, b & Self::EXPONENT_MASK) { + (0, Self::EXPONENT_MASK) => FpCategory::Infinite, + (_, Self::EXPONENT_MASK) => FpCategory::Nan, (0, 0) => FpCategory::Zero, (_, 0) => FpCategory::Subnormal, _ => FpCategory::Normal, @@ -769,6 +891,7 @@ impl f32 { #[doc(alias = "nextUp")] #[stable(feature = "float_next_up_down", since = "1.86.0")] #[rustc_const_stable(feature = "float_next_up_down", since = "1.86.0")] + #[must_use = "method returns a new number and does not mutate the original value"] pub const fn next_up(self) -> Self { // Some targets violate Rust's assumption of IEEE semantics, e.g. by flushing // denormals to zero. This is in general unsound and unsupported, but here @@ -820,6 +943,7 @@ impl f32 { #[doc(alias = "nextDown")] #[stable(feature = "float_next_up_down", since = "1.86.0")] #[rustc_const_stable(feature = "float_next_up_down", since = "1.86.0")] + #[must_use = "method returns a new number and does not mutate the original value"] pub const fn next_down(self) -> Self { // Some targets violate Rust's assumption of IEEE semantics, e.g. by flushing // denormals to zero. This is in general unsound and unsupported, but here @@ -937,7 +1061,7 @@ impl f32 { #[rustc_const_stable(feature = "const_float_methods", since = "1.85.0")] #[inline] pub const fn max(self, other: f32) -> f32 { - intrinsics::maxnumf32(self, other) + intrinsics::maximum_number_nsz_f32(self, other) } /// Returns the minimum of the two numbers, ignoring NaN. @@ -964,7 +1088,7 @@ impl f32 { #[rustc_const_stable(feature = "const_float_methods", since = "1.85.0")] #[inline] pub const fn min(self, other: f32) -> f32 { - intrinsics::minnumf32(self, other) + intrinsics::minimum_number_nsz_f32(self, other) } /// Returns the maximum of the two numbers, propagating NaN. @@ -1036,6 +1160,8 @@ impl f32 { #[doc(alias = "average")] #[stable(feature = "num_midpoint", since = "1.85.0")] #[rustc_const_stable(feature = "num_midpoint", since = "1.85.0")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] pub const fn midpoint(self, other: f32) -> f32 { cfg_select! { // Allow faster implementation that have known good 64-bit float @@ -1050,11 +1176,9 @@ impl f32 { all(target_arch = "arm", target_feature = "vfp2"), target_arch = "wasm32", target_arch = "wasm64", - ) => { - ((self as f64 + other as f64) / 2.0) as f32 - } + ) => ((self as f64 + other as f64) * 0.5) as f32, _ => { - const HI: f32 = f32::MAX / 2.; + const HI: f32 = f32::MAX * 0.5; let (a, b) = (self, other); let abs_a = a.abs(); @@ -1062,9 +1186,9 @@ impl f32 { if abs_a <= HI && abs_b <= HI { // Overflow is impossible - (a + b) / 2. + (a + b) * 0.5 } else { - (a / 2.) + (b / 2.) + (a * 0.5) + (b * 0.5) } } } @@ -1517,7 +1641,7 @@ impl f32 { #[rustc_const_stable(feature = "const_float_methods", since = "1.85.0")] #[inline] pub const fn abs(self) -> f32 { - intrinsics::fabsf32(self) + intrinsics::fabs(self) } /// Returns a number that represents the sign of `self`. @@ -1582,8 +1706,8 @@ impl f32 { /// /// See [algebraic operators](primitive@f32#algebraic-operators) for more info. #[must_use = "method returns a new number and does not mutate the original value"] - #[unstable(feature = "float_algebraic", issue = "136469")] - #[rustc_const_unstable(feature = "float_algebraic", issue = "136469")] + #[stable(feature = "float_algebraic", since = "1.98.0")] + #[rustc_const_stable(feature = "float_algebraic", since = "1.98.0")] #[inline] pub const fn algebraic_add(self, rhs: f32) -> f32 { intrinsics::fadd_algebraic(self, rhs) @@ -1593,8 +1717,8 @@ impl f32 { /// /// See [algebraic operators](primitive@f32#algebraic-operators) for more info. #[must_use = "method returns a new number and does not mutate the original value"] - #[unstable(feature = "float_algebraic", issue = "136469")] - #[rustc_const_unstable(feature = "float_algebraic", issue = "136469")] + #[stable(feature = "float_algebraic", since = "1.98.0")] + #[rustc_const_stable(feature = "float_algebraic", since = "1.98.0")] #[inline] pub const fn algebraic_sub(self, rhs: f32) -> f32 { intrinsics::fsub_algebraic(self, rhs) @@ -1604,8 +1728,8 @@ impl f32 { /// /// See [algebraic operators](primitive@f32#algebraic-operators) for more info. #[must_use = "method returns a new number and does not mutate the original value"] - #[unstable(feature = "float_algebraic", issue = "136469")] - #[rustc_const_unstable(feature = "float_algebraic", issue = "136469")] + #[stable(feature = "float_algebraic", since = "1.98.0")] + #[rustc_const_stable(feature = "float_algebraic", since = "1.98.0")] #[inline] pub const fn algebraic_mul(self, rhs: f32) -> f32 { intrinsics::fmul_algebraic(self, rhs) @@ -1615,8 +1739,8 @@ impl f32 { /// /// See [algebraic operators](primitive@f32#algebraic-operators) for more info. #[must_use = "method returns a new number and does not mutate the original value"] - #[unstable(feature = "float_algebraic", issue = "136469")] - #[rustc_const_unstable(feature = "float_algebraic", issue = "136469")] + #[stable(feature = "float_algebraic", since = "1.98.0")] + #[rustc_const_stable(feature = "float_algebraic", since = "1.98.0")] #[inline] pub const fn algebraic_div(self, rhs: f32) -> f32 { intrinsics::fdiv_algebraic(self, rhs) @@ -1626,12 +1750,36 @@ impl f32 { /// /// See [algebraic operators](primitive@f32#algebraic-operators) for more info. #[must_use = "method returns a new number and does not mutate the original value"] - #[unstable(feature = "float_algebraic", issue = "136469")] - #[rustc_const_unstable(feature = "float_algebraic", issue = "136469")] + #[stable(feature = "float_algebraic", since = "1.98.0")] + #[rustc_const_stable(feature = "float_algebraic", since = "1.98.0")] #[inline] pub const fn algebraic_rem(self, rhs: f32) -> f32 { intrinsics::frem_algebraic(self, rhs) } + + /// Returns `self` if the value is not NaN, otherwise returns `replacement` + /// if `self` is NaN. + /// + /// # Examples + /// + /// ``` + /// #![feature(float_nan_to)] + /// + /// let n = f32::NAN; + /// let x = 2.0f32; + /// let y = f32::INFINITY; + /// + /// assert_eq!(n.nan_to(0.0f32), 0.0f32); + /// assert_eq!(x.nan_to(0.0f32), 2.0f32); + /// assert_eq!(y.nan_to(0.0f32), f32::INFINITY); + /// ``` + #[must_use = "method returns a new float and does not mutate the original value"] + #[unstable(feature = "float_nan_to", issue = "161248")] + #[rustc_const_unstable(feature = "float_nan_to", issue = "161248")] + #[inline] + pub const fn nan_to(self, replacement: f32) -> f32 { + if self.is_nan() { replacement } else { self } + } } /// Experimental implementations of floating point functions in `core`. @@ -1641,7 +1789,7 @@ impl f32 { #[unstable(feature = "core_float_math", issue = "137578")] pub mod math { use crate::intrinsics; - use crate::num::libm; + use crate::num::imp::libm; /// Experimental version of `floor` in `core`. See [`f32::floor`] for details. /// @@ -1829,6 +1977,7 @@ pub mod math { /// # Examples /// /// ``` + /// # #![allow(unused_features)] /// #![feature(core_float_math)] /// /// # // FIXME(#140515): mingw has an incorrect fma diff --git a/library/core/src/num/f64.rs b/library/core/src/num/f64.rs index fac845b8be317..56653dc4d2420 100644 --- a/library/core/src/num/f64.rs +++ b/library/core/src/num/f64.rs @@ -29,14 +29,14 @@ use crate::{intrinsics, mem}; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let r = std::f64::RADIX; /// /// // intended way /// let r = f64::RADIX; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `RADIX` associated constant on `f64`")] +#[deprecated(since = "1.99.0", note = "replaced by the `RADIX` associated constant on `f64`")] #[rustc_diagnostic_item = "f64_legacy_const_radix"] pub const RADIX: u32 = f64::RADIX; @@ -47,7 +47,7 @@ pub const RADIX: u32 = f64::RADIX; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let d = std::f64::MANTISSA_DIGITS; /// /// // intended way @@ -55,7 +55,7 @@ pub const RADIX: u32 = f64::RADIX; /// ``` #[stable(feature = "rust1", since = "1.0.0")] #[deprecated( - since = "TBD", + since = "1.99.0", note = "replaced by the `MANTISSA_DIGITS` associated constant on `f64`" )] #[rustc_diagnostic_item = "f64_legacy_const_mantissa_dig"] @@ -68,14 +68,14 @@ pub const MANTISSA_DIGITS: u32 = f64::MANTISSA_DIGITS; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let d = std::f64::DIGITS; /// /// // intended way /// let d = f64::DIGITS; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `DIGITS` associated constant on `f64`")] +#[deprecated(since = "1.99.0", note = "replaced by the `DIGITS` associated constant on `f64`")] #[rustc_diagnostic_item = "f64_legacy_const_digits"] pub const DIGITS: u32 = f64::DIGITS; @@ -90,14 +90,14 @@ pub const DIGITS: u32 = f64::DIGITS; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let e = std::f64::EPSILON; /// /// // intended way /// let e = f64::EPSILON; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `EPSILON` associated constant on `f64`")] +#[deprecated(since = "1.99.0", note = "replaced by the `EPSILON` associated constant on `f64`")] #[rustc_diagnostic_item = "f64_legacy_const_epsilon"] pub const EPSILON: f64 = f64::EPSILON; @@ -108,14 +108,14 @@ pub const EPSILON: f64 = f64::EPSILON; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let min = std::f64::MIN; /// /// // intended way /// let min = f64::MIN; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `MIN` associated constant on `f64`")] +#[deprecated(since = "1.99.0", note = "replaced by the `MIN` associated constant on `f64`")] #[rustc_diagnostic_item = "f64_legacy_const_min"] pub const MIN: f64 = f64::MIN; @@ -126,14 +126,17 @@ pub const MIN: f64 = f64::MIN; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let min = std::f64::MIN_POSITIVE; /// /// // intended way /// let min = f64::MIN_POSITIVE; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `MIN_POSITIVE` associated constant on `f64`")] +#[deprecated( + since = "1.99.0", + note = "replaced by the `MIN_POSITIVE` associated constant on `f64`" +)] #[rustc_diagnostic_item = "f64_legacy_const_min_positive"] pub const MIN_POSITIVE: f64 = f64::MIN_POSITIVE; @@ -144,14 +147,14 @@ pub const MIN_POSITIVE: f64 = f64::MIN_POSITIVE; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let max = std::f64::MAX; /// /// // intended way /// let max = f64::MAX; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `MAX` associated constant on `f64`")] +#[deprecated(since = "1.99.0", note = "replaced by the `MAX` associated constant on `f64`")] #[rustc_diagnostic_item = "f64_legacy_const_max"] pub const MAX: f64 = f64::MAX; @@ -162,14 +165,14 @@ pub const MAX: f64 = f64::MAX; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let min = std::f64::MIN_EXP; /// /// // intended way /// let min = f64::MIN_EXP; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `MIN_EXP` associated constant on `f64`")] +#[deprecated(since = "1.99.0", note = "replaced by the `MIN_EXP` associated constant on `f64`")] #[rustc_diagnostic_item = "f64_legacy_const_min_exp"] pub const MIN_EXP: i32 = f64::MIN_EXP; @@ -180,14 +183,14 @@ pub const MIN_EXP: i32 = f64::MIN_EXP; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let max = std::f64::MAX_EXP; /// /// // intended way /// let max = f64::MAX_EXP; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `MAX_EXP` associated constant on `f64`")] +#[deprecated(since = "1.99.0", note = "replaced by the `MAX_EXP` associated constant on `f64`")] #[rustc_diagnostic_item = "f64_legacy_const_max_exp"] pub const MAX_EXP: i32 = f64::MAX_EXP; @@ -198,14 +201,14 @@ pub const MAX_EXP: i32 = f64::MAX_EXP; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let min = std::f64::MIN_10_EXP; /// /// // intended way /// let min = f64::MIN_10_EXP; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `MIN_10_EXP` associated constant on `f64`")] +#[deprecated(since = "1.99.0", note = "replaced by the `MIN_10_EXP` associated constant on `f64`")] #[rustc_diagnostic_item = "f64_legacy_const_min_10_exp"] pub const MIN_10_EXP: i32 = f64::MIN_10_EXP; @@ -216,14 +219,14 @@ pub const MIN_10_EXP: i32 = f64::MIN_10_EXP; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let max = std::f64::MAX_10_EXP; /// /// // intended way /// let max = f64::MAX_10_EXP; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `MAX_10_EXP` associated constant on `f64`")] +#[deprecated(since = "1.99.0", note = "replaced by the `MAX_10_EXP` associated constant on `f64`")] #[rustc_diagnostic_item = "f64_legacy_const_max_10_exp"] pub const MAX_10_EXP: i32 = f64::MAX_10_EXP; @@ -234,14 +237,14 @@ pub const MAX_10_EXP: i32 = f64::MAX_10_EXP; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let nan = std::f64::NAN; /// /// // intended way /// let nan = f64::NAN; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `NAN` associated constant on `f64`")] +#[deprecated(since = "1.99.0", note = "replaced by the `NAN` associated constant on `f64`")] #[rustc_diagnostic_item = "f64_legacy_const_nan"] pub const NAN: f64 = f64::NAN; @@ -252,14 +255,14 @@ pub const NAN: f64 = f64::NAN; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let inf = std::f64::INFINITY; /// /// // intended way /// let inf = f64::INFINITY; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `INFINITY` associated constant on `f64`")] +#[deprecated(since = "1.99.0", note = "replaced by the `INFINITY` associated constant on `f64`")] #[rustc_diagnostic_item = "f64_legacy_const_infinity"] pub const INFINITY: f64 = f64::INFINITY; @@ -270,14 +273,17 @@ pub const INFINITY: f64 = f64::INFINITY; /// /// ```rust /// // deprecated way -/// # #[allow(deprecated, deprecated_in_future)] +/// # #[allow(deprecated)] /// let ninf = std::f64::NEG_INFINITY; /// /// // intended way /// let ninf = f64::NEG_INFINITY; /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[deprecated(since = "TBD", note = "replaced by the `NEG_INFINITY` associated constant on `f64`")] +#[deprecated( + since = "1.99.0", + note = "replaced by the `NEG_INFINITY` associated constant on `f64`" +)] #[rustc_diagnostic_item = "f64_legacy_const_neg_infinity"] pub const NEG_INFINITY: f64 = f64::NEG_INFINITY; @@ -298,6 +304,7 @@ pub mod consts { pub const TAU: f64 = 6.28318530717958647692528676655900577_f64; /// The golden ratio (φ) + #[doc(alias = "phi")] #[stable(feature = "euler_gamma_golden_ratio", since = "1.94.0")] pub const GOLDEN_RATIO: f64 = 1.618033988749894848204586834365638118_f64; @@ -399,6 +406,7 @@ pub mod consts { pub const LN_10: f64 = 2.30258509299404568401799145468436421_f64; } +#[doc(test(attr(allow(unused_features))))] impl f64 { /// The radix or base of the internal representation of `f64`. #[stable(feature = "assoc_int_consts", since = "1.43.0")] @@ -509,7 +517,7 @@ impl f64 { /// The concrete bit pattern may change across Rust versions and target platforms. #[rustc_diagnostic_item = "f64_nan"] #[stable(feature = "assoc_int_consts", since = "1.43.0")] - #[allow(clippy::eq_op)] + #[allow(clippy::eq_op, clippy::zero_divided_by_zero)] pub const NAN: f64 = 0.0_f64 / 0.0_f64; /// Infinity (∞). #[stable(feature = "assoc_int_consts", since = "1.43.0")] @@ -518,14 +526,127 @@ impl f64 { #[stable(feature = "assoc_int_consts", since = "1.43.0")] pub const NEG_INFINITY: f64 = -1.0_f64 / 0.0_f64; - /// Sign bit - pub(crate) const SIGN_MASK: u64 = 0x8000_0000_0000_0000; + /// Maximum integer that can be represented exactly in an [`f64`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i64`] and [`f64`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f64`] and back to + /// [`i64`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f64`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// [`MAX_EXACT_INTEGER`]: f64::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f64::MIN_EXACT_INTEGER + /// ``` + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// let max_exact_int = f64::MAX_EXACT_INTEGER; + /// assert_eq!(max_exact_int, max_exact_int as f64 as i64); + /// assert_eq!(max_exact_int + 1, (max_exact_int + 1) as f64 as i64); + /// assert_ne!(max_exact_int + 2, (max_exact_int + 2) as f64 as i64); + /// + /// // Beyond `f64::MAX_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((max_exact_int + 1) as f64, (max_exact_int + 2) as f64); + /// # } + /// ``` + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MAX_EXACT_INTEGER: i64 = (1 << Self::MANTISSA_DIGITS) - 1; - /// Exponent mask - pub(crate) const EXP_MASK: u64 = 0x7ff0_0000_0000_0000; + /// Minimum integer that can be represented exactly in an [`f64`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i64`] and [`f64`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f64`] and back to + /// [`i64`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f64`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// This constant is equivalent to `-MAX_EXACT_INTEGER`. + /// + /// [`MAX_EXACT_INTEGER`]: f64::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f64::MIN_EXACT_INTEGER + /// ``` + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// let min_exact_int = f64::MIN_EXACT_INTEGER; + /// assert_eq!(min_exact_int, min_exact_int as f64 as i64); + /// assert_eq!(min_exact_int - 1, (min_exact_int - 1) as f64 as i64); + /// assert_ne!(min_exact_int - 2, (min_exact_int - 2) as f64 as i64); + /// + /// // Below `f64::MIN_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((min_exact_int - 1) as f64, (min_exact_int - 2) as f64); + /// # } + /// ``` + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MIN_EXACT_INTEGER: i64 = -Self::MAX_EXACT_INTEGER; - /// Mantissa mask - pub(crate) const MAN_MASK: u64 = 0x000f_ffff_ffff_ffff; + /// The mask of the bit used to encode the sign of an [`f64`]. + /// + /// This bit is set when the sign is negative and unset when the sign is + /// positive. + /// If you only need to check whether a value is positive or negative, + /// [`is_sign_positive`] or [`is_sign_negative`] can be used. + /// + /// [`is_sign_positive`]: f64::is_sign_positive + /// [`is_sign_negative`]: f64::is_sign_negative + /// ```rust + /// #![feature(float_masks)] + /// let sign_mask = f64::SIGN_MASK; + /// let a = 1.6552f64; + /// let a_bits = a.to_bits(); + /// + /// assert_eq!(a_bits & sign_mask, 0x0); + /// assert_eq!(f64::from_bits(a_bits ^ sign_mask), -a); + /// assert_eq!(sign_mask, (-0.0f64).to_bits()); + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const SIGN_MASK: u64 = 0x8000_0000_0000_0000; + + /// The mask of the bits used to encode the exponent of an [`f64`]. + /// + /// Note that the exponent is stored as a biased value, with a bias of 1024 for `f64`. + /// + /// ```rust + /// #![feature(float_masks)] + /// fn get_exp(a: f64) -> i64 { + /// let bias = 1023; + /// let biased = a.to_bits() & f64::EXPONENT_MASK; + /// (biased >> (f64::MANTISSA_DIGITS - 1)).cast_signed() - bias + /// } + /// + /// assert_eq!(get_exp(0.5), -1); + /// assert_eq!(get_exp(1.0), 0); + /// assert_eq!(get_exp(2.0), 1); + /// assert_eq!(get_exp(4.0), 2); + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const EXPONENT_MASK: u64 = 0x7ff0_0000_0000_0000; + + /// The mask of the bits used to encode the mantissa of an [`f64`]. + /// + /// ```rust + /// #![feature(float_masks)] + /// let mantissa_mask = f64::MANTISSA_MASK; + /// + /// assert_eq!(0f64.to_bits() & mantissa_mask, 0x0); + /// assert_eq!(1f64.to_bits() & mantissa_mask, 0x0); + /// + /// // multiplying a finite value by a power of 2 doesn't change its mantissa + /// // unless the result or initial value is not normal. + /// let a = 1.6552f64; + /// let b = 4.0 * a; + /// assert_eq!(a.to_bits() & mantissa_mask, b.to_bits() & mantissa_mask); + /// + /// // The maximum and minimum values have a saturated significand + /// assert_eq!(f64::MAX.to_bits() & f64::MANTISSA_MASK, f64::MANTISSA_MASK); + /// assert_eq!(f64::MIN.to_bits() & f64::MANTISSA_MASK, f64::MANTISSA_MASK); + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const MANTISSA_MASK: u64 = 0x000f_ffff_ffff_ffff; /// Minimum representable positive value (min subnormal) const TINY_BITS: u64 = 0x1; @@ -669,6 +790,7 @@ impl f64 { /// ``` #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_stable(feature = "const_float_classify", since = "1.83.0")] + #[must_use] pub const fn classify(self) -> FpCategory { // We used to have complicated logic here that avoids the simple bit-based tests to work // around buggy codegen for x87 targets (see @@ -676,9 +798,9 @@ impl f64 { // of our tests is able to find any difference between the complicated and the naive // version, so now we are back to the naive version. let b = self.to_bits(); - match (b & Self::MAN_MASK, b & Self::EXP_MASK) { - (0, Self::EXP_MASK) => FpCategory::Infinite, - (_, Self::EXP_MASK) => FpCategory::Nan, + match (b & Self::MANTISSA_MASK, b & Self::EXPONENT_MASK) { + (0, Self::EXPONENT_MASK) => FpCategory::Infinite, + (_, Self::EXPONENT_MASK) => FpCategory::Nan, (0, 0) => FpCategory::Zero, (_, 0) => FpCategory::Subnormal, _ => FpCategory::Normal, @@ -710,15 +832,6 @@ impl f64 { !self.is_sign_negative() } - #[must_use] - #[stable(feature = "rust1", since = "1.0.0")] - #[deprecated(since = "1.0.0", note = "renamed to is_sign_positive")] - #[inline] - #[doc(hidden)] - pub fn is_positive(self) -> bool { - self.is_sign_positive() - } - /// Returns `true` if `self` has a negative sign, including `-0.0`, NaNs with /// negative sign bit and negative infinity. /// @@ -746,15 +859,6 @@ impl f64 { self.to_bits() & Self::SIGN_MASK != 0 } - #[must_use] - #[stable(feature = "rust1", since = "1.0.0")] - #[deprecated(since = "1.0.0", note = "renamed to is_sign_negative")] - #[inline] - #[doc(hidden)] - pub fn is_negative(self) -> bool { - self.is_sign_negative() - } - /// Returns the least number greater than `self`. /// /// Let `TINY` be the smallest representable positive `f64`. Then, @@ -786,6 +890,7 @@ impl f64 { #[doc(alias = "nextUp")] #[stable(feature = "float_next_up_down", since = "1.86.0")] #[rustc_const_stable(feature = "float_next_up_down", since = "1.86.0")] + #[must_use = "method returns a new number and does not mutate the original value"] pub const fn next_up(self) -> Self { // Some targets violate Rust's assumption of IEEE semantics, e.g. by flushing // denormals to zero. This is in general unsound and unsupported, but here @@ -837,6 +942,7 @@ impl f64 { #[doc(alias = "nextDown")] #[stable(feature = "float_next_up_down", since = "1.86.0")] #[rustc_const_stable(feature = "float_next_up_down", since = "1.86.0")] + #[must_use = "method returns a new number and does not mutate the original value"] pub const fn next_down(self) -> Self { // Some targets violate Rust's assumption of IEEE semantics, e.g. by flushing // denormals to zero. This is in general unsound and unsupported, but here @@ -955,7 +1061,7 @@ impl f64 { #[rustc_const_stable(feature = "const_float_methods", since = "1.85.0")] #[inline] pub const fn max(self, other: f64) -> f64 { - intrinsics::maxnumf64(self, other) + intrinsics::maximum_number_nsz_f64(self, other) } /// Returns the minimum of the two numbers, ignoring NaN. @@ -982,7 +1088,7 @@ impl f64 { #[rustc_const_stable(feature = "const_float_methods", since = "1.85.0")] #[inline] pub const fn min(self, other: f64) -> f64 { - intrinsics::minnumf64(self, other) + intrinsics::minimum_number_nsz_f64(self, other) } /// Returns the maximum of the two numbers, propagating NaN. @@ -1054,8 +1160,10 @@ impl f64 { #[doc(alias = "average")] #[stable(feature = "num_midpoint", since = "1.85.0")] #[rustc_const_stable(feature = "num_midpoint", since = "1.85.0")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] pub const fn midpoint(self, other: f64) -> f64 { - const HI: f64 = f64::MAX / 2.; + const HI: f64 = f64::MAX * 0.5; let (a, b) = (self, other); let abs_a = a.abs(); @@ -1063,9 +1171,9 @@ impl f64 { if abs_a <= HI && abs_b <= HI { // Overflow is impossible - (a + b) / 2. + (a + b) * 0.5 } else { - (a / 2.) + (b / 2.) + (a * 0.5) + (b * 0.5) } } @@ -1515,7 +1623,7 @@ impl f64 { #[rustc_const_stable(feature = "const_float_methods", since = "1.85.0")] #[inline] pub const fn abs(self) -> f64 { - intrinsics::fabsf64(self) + intrinsics::fabs(self) } /// Returns a number that represents the sign of `self`. @@ -1580,8 +1688,8 @@ impl f64 { /// /// See [algebraic operators](primitive@f32#algebraic-operators) for more info. #[must_use = "method returns a new number and does not mutate the original value"] - #[unstable(feature = "float_algebraic", issue = "136469")] - #[rustc_const_unstable(feature = "float_algebraic", issue = "136469")] + #[stable(feature = "float_algebraic", since = "1.98.0")] + #[rustc_const_stable(feature = "float_algebraic", since = "1.98.0")] #[inline] pub const fn algebraic_add(self, rhs: f64) -> f64 { intrinsics::fadd_algebraic(self, rhs) @@ -1591,8 +1699,8 @@ impl f64 { /// /// See [algebraic operators](primitive@f32#algebraic-operators) for more info. #[must_use = "method returns a new number and does not mutate the original value"] - #[unstable(feature = "float_algebraic", issue = "136469")] - #[rustc_const_unstable(feature = "float_algebraic", issue = "136469")] + #[stable(feature = "float_algebraic", since = "1.98.0")] + #[rustc_const_stable(feature = "float_algebraic", since = "1.98.0")] #[inline] pub const fn algebraic_sub(self, rhs: f64) -> f64 { intrinsics::fsub_algebraic(self, rhs) @@ -1602,8 +1710,8 @@ impl f64 { /// /// See [algebraic operators](primitive@f32#algebraic-operators) for more info. #[must_use = "method returns a new number and does not mutate the original value"] - #[unstable(feature = "float_algebraic", issue = "136469")] - #[rustc_const_unstable(feature = "float_algebraic", issue = "136469")] + #[stable(feature = "float_algebraic", since = "1.98.0")] + #[rustc_const_stable(feature = "float_algebraic", since = "1.98.0")] #[inline] pub const fn algebraic_mul(self, rhs: f64) -> f64 { intrinsics::fmul_algebraic(self, rhs) @@ -1613,8 +1721,8 @@ impl f64 { /// /// See [algebraic operators](primitive@f32#algebraic-operators) for more info. #[must_use = "method returns a new number and does not mutate the original value"] - #[unstable(feature = "float_algebraic", issue = "136469")] - #[rustc_const_unstable(feature = "float_algebraic", issue = "136469")] + #[stable(feature = "float_algebraic", since = "1.98.0")] + #[rustc_const_stable(feature = "float_algebraic", since = "1.98.0")] #[inline] pub const fn algebraic_div(self, rhs: f64) -> f64 { intrinsics::fdiv_algebraic(self, rhs) @@ -1624,12 +1732,36 @@ impl f64 { /// /// See [algebraic operators](primitive@f32#algebraic-operators) for more info. #[must_use = "method returns a new number and does not mutate the original value"] - #[unstable(feature = "float_algebraic", issue = "136469")] - #[rustc_const_unstable(feature = "float_algebraic", issue = "136469")] + #[stable(feature = "float_algebraic", since = "1.98.0")] + #[rustc_const_stable(feature = "float_algebraic", since = "1.98.0")] #[inline] pub const fn algebraic_rem(self, rhs: f64) -> f64 { intrinsics::frem_algebraic(self, rhs) } + + /// Returns `self` if the value is not NaN, otherwise returns `replacement` + /// if `self` is NaN. + /// + /// # Examples + /// + /// ``` + /// #![feature(float_nan_to)] + /// + /// let n = f64::NAN; + /// let x = 2.0f64; + /// let y = f64::INFINITY; + /// + /// assert_eq!(n.nan_to(0.0f64), 0.0f64); + /// assert_eq!(x.nan_to(0.0f64), 2.0f64); + /// assert_eq!(y.nan_to(0.0f64), f64::INFINITY); + /// ``` + #[must_use = "method returns a new float and does not mutate the original value"] + #[unstable(feature = "float_nan_to", issue = "161248")] + #[rustc_const_unstable(feature = "float_nan_to", issue = "161248")] + #[inline] + pub const fn nan_to(self, replacement: f64) -> f64 { + if self.is_nan() { replacement } else { self } + } } #[unstable(feature = "core_float_math", issue = "137578")] @@ -1639,7 +1771,7 @@ impl f64 { /// They will be stabilized as inherent methods._ pub mod math { use crate::intrinsics; - use crate::num::libm; + use crate::num::imp::libm; /// Experimental version of `floor` in `core`. See [`f64::floor`] for details. /// @@ -1827,6 +1959,7 @@ pub mod math { /// # Examples /// /// ``` + /// # #![allow(unused_features)] /// #![feature(core_float_math)] /// /// # // FIXME(#140515): mingw has an incorrect fma diff --git a/library/core/src/num/float_parse.rs b/library/core/src/num/float_parse.rs new file mode 100644 index 0000000000000..d8846a0cc0a8e --- /dev/null +++ b/library/core/src/num/float_parse.rs @@ -0,0 +1,133 @@ +//! User-facing API for float parsing. + +use crate::error::Error; +use crate::fmt; +use crate::num::imp::dec2flt; +use crate::str::FromStr; + +macro_rules! from_str_float_impl { + ($t:ty) => { + #[stable(feature = "rust1", since = "1.0.0")] + impl FromStr for $t { + type Err = ParseFloatError; + + /// Converts a string in base 10 to a float. + /// Accepts an optional decimal exponent. + /// + /// This function accepts strings such as + /// + /// * '3.14' + /// * '-3.14' + /// * '2.5E10', or equivalently, '2.5e10' + /// * '2.5E-10' + /// * '5.' + /// * '.5', or, equivalently, '0.5' + /// * '7' + /// * '007' + /// * 'inf', '-inf', '+infinity', 'NaN' + /// + /// Note that alphabetical characters are not case-sensitive. + /// + /// Leading and trailing whitespace represent an error. + /// + /// # Grammar + /// + /// All strings that adhere to the following [EBNF] grammar when + /// lowercased will result in an [`Ok`] being returned: + /// + /// ```txt + /// Float ::= Sign? ( 'inf' | 'infinity' | 'nan' | Number ) + /// Number ::= ( Digit+ | + /// Digit+ '.' Digit* | + /// Digit* '.' Digit+ ) Exp? + /// Exp ::= 'e' Sign? Digit+ + /// Sign ::= [+-] + /// Digit ::= [0-9] + /// ``` + /// + /// [EBNF]: https://www.w3.org/TR/REC-xml/#sec-notation + /// + /// # Arguments + /// + /// * src - A string + /// + /// # Return value + /// + /// `Err(ParseFloatError)` if the string did not represent a valid + /// number. Otherwise, `Ok(n)` where `n` is the closest + /// representable floating-point number to the number represented + /// by `src` (following the same rules for rounding as for the + /// results of primitive operations). + // We add the `#[inline(never)]` attribute, since its content will + // be filled with that of `dec2flt`, which has #[inline(always)]. + // Since `dec2flt` is generic, a normal inline attribute on this function + // with `dec2flt` having no attributes results in heavily repeated + // generation of `dec2flt`, despite the fact only a maximum of 2 + // possible instances can ever exist. Adding #[inline(never)] avoids this. + #[inline(never)] + fn from_str(src: &str) -> Result { + dec2flt::dec2flt(src) + } + } + }; +} + +#[cfg(target_has_reliable_f16)] +from_str_float_impl!(f16); +from_str_float_impl!(f32); +from_str_float_impl!(f64); + +// FIXME(f16): A fallback is used when the backend+target does not support f16 well, in order +// to avoid ICEs. + +#[cfg(not(target_has_reliable_f16))] +#[expect(ineffective_unstable_trait_impl, reason = "stable trait on unstable type")] +#[unstable(feature = "f16", issue = "116909")] +impl FromStr for f16 { + type Err = ParseFloatError; + + #[inline] + fn from_str(_src: &str) -> Result { + unimplemented!("requires target_has_reliable_f16") + } +} + +/// An error which can be returned when parsing a float. +/// +/// This error is used as the error type for the [`FromStr`] implementation +/// for [`f32`] and [`f64`]. +/// +/// # Example +/// +/// ``` +/// use std::str::FromStr; +/// +/// if let Err(e) = f64::from_str("a.12") { +/// println!("Failed conversion to f64: {e}"); +/// } +/// ``` +#[derive(Debug, Clone, PartialEq, Eq)] +#[stable(feature = "rust1", since = "1.0.0")] +pub struct ParseFloatError { + pub(super) kind: FloatErrorKind, +} + +#[derive(Debug, Clone, PartialEq, Eq)] +pub(super) enum FloatErrorKind { + Empty, + Invalid, +} + +#[stable(feature = "rust1", since = "1.0.0")] +impl Error for ParseFloatError {} + +#[stable(feature = "rust1", since = "1.0.0")] +impl fmt::Display for ParseFloatError { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self.kind { + FloatErrorKind::Empty => "cannot parse float from empty string", + FloatErrorKind::Invalid => "invalid float literal", + } + .fmt(f) + } +} diff --git a/library/core/src/num/bignum.rs b/library/core/src/num/imp/bignum.rs similarity index 98% rename from library/core/src/num/bignum.rs rename to library/core/src/num/imp/bignum.rs index 95b49a38ded06..9e930ed15a234 100644 --- a/library/core/src/num/bignum.rs +++ b/library/core/src/num/imp/bignum.rs @@ -251,7 +251,7 @@ macro_rules! define_bignum { /// Multiplies itself by `5^e` and returns its own mutable reference. pub fn mul_pow5(&mut self, mut e: usize) -> &mut $name { - use crate::num::bignum::SMALL_POW5; + use crate::num::imp::bignum::SMALL_POW5; // There are exactly n trailing zeros on 2^n, and the only relevant digit sizes // are consecutive powers of two, so this is well suited index for the table. @@ -281,7 +281,7 @@ macro_rules! define_bignum { pub fn mul_digits<'a>(&'a mut self, other: &[$ty]) -> &'a mut $name { // the internal routine. works best when aa.len() <= bb.len(). fn mul_inner(ret: &mut [$ty; $n], aa: &[$ty], bb: &[$ty]) -> usize { - use crate::num::bignum::FullOps; + use crate::num::imp::bignum::FullOps; let mut retsz = 0; for (i, &a) in aa.iter().enumerate() { @@ -320,7 +320,7 @@ macro_rules! define_bignum { /// Divides itself by a digit-sized `other` and returns its own /// mutable reference *and* the remainder. pub fn div_rem_small(&mut self, other: $ty) -> (&mut $name, $ty) { - use crate::num::bignum::FullOps; + use crate::num::imp::bignum::FullOps; assert!(other > 0); diff --git a/library/core/src/num/dec2flt/common.rs b/library/core/src/num/imp/dec2flt/common.rs similarity index 100% rename from library/core/src/num/dec2flt/common.rs rename to library/core/src/num/imp/dec2flt/common.rs diff --git a/library/core/src/num/dec2flt/decimal.rs b/library/core/src/num/imp/dec2flt/decimal.rs similarity index 93% rename from library/core/src/num/dec2flt/decimal.rs rename to library/core/src/num/imp/dec2flt/decimal.rs index db7176c124318..c9b0cc531b386 100644 --- a/library/core/src/num/dec2flt/decimal.rs +++ b/library/core/src/num/imp/dec2flt/decimal.rs @@ -1,7 +1,9 @@ //! Representation of a float as the significant digits and exponent. -use crate::num::dec2flt::float::RawFloat; -use crate::num::dec2flt::fpu::set_precision; +use dec2flt::Lemire; +use dec2flt::fpu::set_precision; + +use crate::num::imp::dec2flt; const INT_POW10: [u64; 16] = [ 1, @@ -34,7 +36,7 @@ pub struct Decimal { impl Decimal { /// Detect if the float can be accurately reconstructed from native floats. #[inline] - fn can_use_fast_path(&self) -> bool { + fn can_use_fast_path(&self) -> bool { F::MIN_EXPONENT_FAST_PATH <= self.exponent && self.exponent <= F::MAX_EXPONENT_DISGUISED_FAST_PATH && self.mantissa <= F::MAX_MANTISSA_FAST_PATH @@ -51,7 +53,7 @@ impl Decimal { /// /// There is an exception: disguised fast-path cases, where we can shift /// powers-of-10 from the exponent to the significant digits. - pub fn try_fast_path(&self) -> Option { + pub fn try_fast_path(&self) -> Option { // Here we need to work around . // The fast path crucially depends on arithmetic being rounded to the correct number of bits // without any intermediate rounding. On x86 (without SSE or SSE2) this requires the precision diff --git a/library/core/src/num/dec2flt/decimal_seq.rs b/library/core/src/num/imp/dec2flt/decimal_seq.rs similarity index 99% rename from library/core/src/num/dec2flt/decimal_seq.rs rename to library/core/src/num/imp/dec2flt/decimal_seq.rs index e66c63faa11cc..8ecdf3959a9e1 100644 --- a/library/core/src/num/dec2flt/decimal_seq.rs +++ b/library/core/src/num/imp/dec2flt/decimal_seq.rs @@ -9,13 +9,14 @@ //! algorithm can be found in "ParseNumberF64 by Simple Decimal Conversion", //! available online: . +use dec2flt::common::{ByteSlice, is_8digits}; use safety::ensures; #[cfg(kani)] use crate::forall; #[cfg(kani)] use crate::kani; -use crate::num::dec2flt::common::{ByteSlice, is_8digits}; +use crate::num::imp::dec2flt; /// A decimal floating-point number, represented as a sequence of decimal digits. #[derive(Clone, Debug, PartialEq)] diff --git a/library/core/src/num/dec2flt/fpu.rs b/library/core/src/num/imp/dec2flt/fpu.rs similarity index 100% rename from library/core/src/num/dec2flt/fpu.rs rename to library/core/src/num/imp/dec2flt/fpu.rs diff --git a/library/core/src/num/dec2flt/lemire.rs b/library/core/src/num/imp/dec2flt/lemire.rs similarity index 96% rename from library/core/src/num/dec2flt/lemire.rs rename to library/core/src/num/imp/dec2flt/lemire.rs index f84929a03c172..f89d16c843477 100644 --- a/library/core/src/num/dec2flt/lemire.rs +++ b/library/core/src/num/imp/dec2flt/lemire.rs @@ -1,10 +1,9 @@ //! Implementation of the Eisel-Lemire algorithm. -use crate::num::dec2flt::common::BiasedFp; -use crate::num::dec2flt::float::RawFloat; -use crate::num::dec2flt::table::{ - LARGEST_POWER_OF_FIVE, POWER_OF_FIVE_128, SMALLEST_POWER_OF_FIVE, -}; +use dec2flt::common::BiasedFp; +use dec2flt::table::{LARGEST_POWER_OF_FIVE, POWER_OF_FIVE_128, SMALLEST_POWER_OF_FIVE}; + +use crate::num::imp::{Float, dec2flt}; /// Compute w * 10^q using an extended-precision float representation. /// @@ -24,7 +23,7 @@ use crate::num::dec2flt::table::{ /// at a Gigabyte per Second" in section 5, "Fast Algorithm", and /// section 6, "Exact Numbers And Ties", available online: /// . -pub fn compute_float(q: i64, mut w: u64) -> BiasedFp { +pub fn compute_float(q: i64, mut w: u64) -> BiasedFp { let fp_zero = BiasedFp::zero_pow2(0); let fp_inf = BiasedFp::zero_pow2(F::INFINITE_POWER); let fp_error = BiasedFp::zero_pow2(-1); diff --git a/library/core/src/num/dec2flt/mod.rs b/library/core/src/num/imp/dec2flt/mod.rs similarity index 61% rename from library/core/src/num/dec2flt/mod.rs rename to library/core/src/num/imp/dec2flt/mod.rs index 66e30e1c5f7f1..76b8d416ee0f1 100644 --- a/library/core/src/num/dec2flt/mod.rs +++ b/library/core/src/num/imp/dec2flt/mod.rs @@ -87,148 +87,103 @@ issue = "none" )] -use self::common::BiasedFp; -use self::float::RawFloat; -use self::lemire::compute_float; -use self::parse::{parse_inf_nan, parse_number}; -use self::slow::parse_long_mantissa; -use crate::error::Error; -use crate::fmt; -use crate::str::FromStr; +use common::BiasedFp; +use lemire::compute_float; +use parse::{parse_inf_nan, parse_number}; +use slow::parse_long_mantissa; + +use crate::f64; +use crate::num::ParseFloatError; +use crate::num::float_parse::FloatErrorKind; +use crate::num::imp::FloatExt; mod common; pub mod decimal; pub mod decimal_seq; mod fpu; -mod slow; -mod table; -// float is used in flt2dec, and all are used in unit tests. -pub mod float; pub mod lemire; pub mod parse; +mod slow; +mod table; -macro_rules! from_str_float_impl { - ($t:ty) => { - #[stable(feature = "rust1", since = "1.0.0")] - impl FromStr for $t { - type Err = ParseFloatError; - - /// Converts a string in base 10 to a float. - /// Accepts an optional decimal exponent. - /// - /// This function accepts strings such as - /// - /// * '3.14' - /// * '-3.14' - /// * '2.5E10', or equivalently, '2.5e10' - /// * '2.5E-10' - /// * '5.' - /// * '.5', or, equivalently, '0.5' - /// * '7' - /// * '007' - /// * 'inf', '-inf', '+infinity', 'NaN' - /// - /// Note that alphabetical characters are not case-sensitive. - /// - /// Leading and trailing whitespace represent an error. - /// - /// # Grammar - /// - /// All strings that adhere to the following [EBNF] grammar when - /// lowercased will result in an [`Ok`] being returned: - /// - /// ```txt - /// Float ::= Sign? ( 'inf' | 'infinity' | 'nan' | Number ) - /// Number ::= ( Digit+ | - /// Digit+ '.' Digit* | - /// Digit* '.' Digit+ ) Exp? - /// Exp ::= 'e' Sign? Digit+ - /// Sign ::= [+-] - /// Digit ::= [0-9] - /// ``` - /// - /// [EBNF]: https://www.w3.org/TR/REC-xml/#sec-notation - /// - /// # Arguments - /// - /// * src - A string - /// - /// # Return value - /// - /// `Err(ParseFloatError)` if the string did not represent a valid - /// number. Otherwise, `Ok(n)` where `n` is the closest - /// representable floating-point number to the number represented - /// by `src` (following the same rules for rounding as for the - /// results of primitive operations). - // We add the `#[inline(never)]` attribute, since its content will - // be filled with that of `dec2flt`, which has #[inline(always)]. - // Since `dec2flt` is generic, a normal inline attribute on this function - // with `dec2flt` having no attributes results in heavily repeated - // generation of `dec2flt`, despite the fact only a maximum of 2 - // possible instances can ever exist. Adding #[inline(never)] avoids this. - #[inline(never)] - fn from_str(src: &str) -> Result { - dec2flt(src) - } - } +/// Extension to `Float` that are necessary for parsing using the Lemire method. +/// +/// See the parent module's doc comment for why this is necessary. +/// +/// Not intended for use outside of the `dec2flt` module. +#[doc(hidden)] +pub trait Lemire: FloatExt { + /// Maximum exponent for a fast path case, or `⌊(SIG_BITS+1)/log2(5)⌋` + // assuming FLT_EVAL_METHOD = 0 + const MAX_EXPONENT_FAST_PATH: i64 = { + let log2_5 = f64::consts::LOG2_10 - 1.0; + (Self::SIG_TOTAL_BITS as f64 / log2_5) as i64 }; -} -#[cfg(target_has_reliable_f16)] -from_str_float_impl!(f16); -from_str_float_impl!(f32); -from_str_float_impl!(f64); + /// Minimum exponent for a fast path case, or `-⌊(SIG_BITS+1)/log2(5)⌋` + const MIN_EXPONENT_FAST_PATH: i64 = -Self::MAX_EXPONENT_FAST_PATH; + + /// Maximum exponent that can be represented for a disguised-fast path case. + /// This is `MAX_EXPONENT_FAST_PATH + ⌊(SIG_BITS+1)/log2(10)⌋` + const MAX_EXPONENT_DISGUISED_FAST_PATH: i64 = + Self::MAX_EXPONENT_FAST_PATH + (Self::SIG_TOTAL_BITS as f64 / f64::consts::LOG2_10) as i64; + + /// Maximum mantissa for the fast-path (`1 << 53` for f64). + const MAX_MANTISSA_FAST_PATH: u64 = 1 << Self::SIG_TOTAL_BITS; + + /// Gets a small power-of-ten for fast-path multiplication. + fn pow10_fast_path(exponent: usize) -> Self; -// FIXME(f16): A fallback is used when the backend+target does not support f16 well, in order -// to avoid ICEs. + /// Converts integer into float through an as cast. + /// This is only called in the fast-path algorithm, and therefore + /// will not lose precision, since the value will always have + /// only if the value is <= Self::MAX_MANTISSA_FAST_PATH. + fn from_u64(v: u64) -> Self; +} -#[cfg(not(target_has_reliable_f16))] -impl FromStr for f16 { - type Err = ParseFloatError; +#[cfg(target_has_reliable_f16)] +impl Lemire for f16 { + fn pow10_fast_path(exponent: usize) -> Self { + #[allow(clippy::use_self)] + const TABLE: [f16; 8] = [1e0, 1e1, 1e2, 1e3, 1e4, 0.0, 0.0, 0.]; + TABLE[exponent & 7] + } #[inline] - fn from_str(_src: &str) -> Result { - unimplemented!("requires target_has_reliable_f16") + fn from_u64(v: u64) -> Self { + debug_assert!(v <= Self::MAX_MANTISSA_FAST_PATH); + v as _ } } -/// An error which can be returned when parsing a float. -/// -/// This error is used as the error type for the [`FromStr`] implementation -/// for [`f32`] and [`f64`]. -/// -/// # Example -/// -/// ``` -/// use std::str::FromStr; -/// -/// if let Err(e) = f64::from_str("a.12") { -/// println!("Failed conversion to f64: {e}"); -/// } -/// ``` -#[derive(Debug, Clone, PartialEq, Eq)] -#[stable(feature = "rust1", since = "1.0.0")] -pub struct ParseFloatError { - kind: FloatErrorKind, -} +impl Lemire for f32 { + fn pow10_fast_path(exponent: usize) -> Self { + #[allow(clippy::use_self)] + const TABLE: [f32; 16] = + [1e0, 1e1, 1e2, 1e3, 1e4, 1e5, 1e6, 1e7, 1e8, 1e9, 1e10, 0., 0., 0., 0., 0.]; + TABLE[exponent & 15] + } -#[derive(Debug, Clone, PartialEq, Eq)] -enum FloatErrorKind { - Empty, - Invalid, + #[inline] + fn from_u64(v: u64) -> Self { + debug_assert!(v <= Self::MAX_MANTISSA_FAST_PATH); + v as _ + } } -#[stable(feature = "rust1", since = "1.0.0")] -impl Error for ParseFloatError {} +impl Lemire for f64 { + fn pow10_fast_path(exponent: usize) -> Self { + const TABLE: [f64; 32] = [ + 1e0, 1e1, 1e2, 1e3, 1e4, 1e5, 1e6, 1e7, 1e8, 1e9, 1e10, 1e11, 1e12, 1e13, 1e14, 1e15, + 1e16, 1e17, 1e18, 1e19, 1e20, 1e21, 1e22, 0., 0., 0., 0., 0., 0., 0., 0., 0., + ]; + TABLE[exponent & 31] + } -#[stable(feature = "rust1", since = "1.0.0")] -impl fmt::Display for ParseFloatError { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - match self.kind { - FloatErrorKind::Empty => "cannot parse float from empty string", - FloatErrorKind::Invalid => "invalid float literal", - } - .fmt(f) + #[inline] + fn from_u64(v: u64) -> Self { + debug_assert!(v <= Self::MAX_MANTISSA_FAST_PATH); + v as _ } } @@ -245,7 +200,7 @@ pub fn pfe_invalid() -> ParseFloatError { } /// Converts a `BiasedFp` to the closest machine float type. -fn biased_fp_to_float(x: BiasedFp) -> F { +fn biased_fp_to_float(x: BiasedFp) -> F { let mut word = x.m; word |= (x.p_biased as u64) << F::SIG_BITS; F::from_u64_bits(word) @@ -253,7 +208,7 @@ fn biased_fp_to_float(x: BiasedFp) -> F { /// Converts a decimal string into a floating point number. #[inline(always)] // Will be inlined into a function with `#[inline(never)]`, see above -pub fn dec2flt(s: &str) -> Result { +pub fn dec2flt(s: &str) -> Result { let mut s = s.as_bytes(); let Some(&c) = s.first() else { return Err(pfe_empty()) }; let negative = c == b'-'; diff --git a/library/core/src/num/dec2flt/parse.rs b/library/core/src/num/imp/dec2flt/parse.rs similarity index 96% rename from library/core/src/num/dec2flt/parse.rs rename to library/core/src/num/imp/dec2flt/parse.rs index e38fedc58bec0..ee55eadbc7b9e 100644 --- a/library/core/src/num/dec2flt/parse.rs +++ b/library/core/src/num/imp/dec2flt/parse.rs @@ -1,8 +1,9 @@ //! Functions to parse floating-point numbers. -use crate::num::dec2flt::common::{ByteSlice, is_8digits}; -use crate::num::dec2flt::decimal::Decimal; -use crate::num::dec2flt::float::RawFloat; +use dec2flt::common::{ByteSlice, is_8digits}; +use dec2flt::decimal::Decimal; + +use crate::num::imp::{Float, dec2flt}; const MIN_19DIGIT_INT: u64 = 100_0000_0000_0000_0000; @@ -195,7 +196,7 @@ pub fn parse_number(s: &[u8]) -> Option { } /// Try to parse a special, non-finite float. -pub(crate) fn parse_inf_nan(s: &[u8], negative: bool) -> Option { +pub(crate) fn parse_inf_nan(s: &[u8], negative: bool) -> Option { // Since a valid string has at most the length 8, we can load // all relevant characters into a u64 and work from there. // This also generates much better code. diff --git a/library/core/src/num/dec2flt/slow.rs b/library/core/src/num/imp/dec2flt/slow.rs similarity index 94% rename from library/core/src/num/dec2flt/slow.rs rename to library/core/src/num/imp/dec2flt/slow.rs index 3baed42652393..f1b2525cf38e6 100644 --- a/library/core/src/num/dec2flt/slow.rs +++ b/library/core/src/num/imp/dec2flt/slow.rs @@ -1,8 +1,9 @@ //! Slow, fallback algorithm for cases the Eisel-Lemire algorithm cannot round. -use crate::num::dec2flt::common::BiasedFp; -use crate::num::dec2flt::decimal_seq::{DecimalSeq, parse_decimal_seq}; -use crate::num::dec2flt::float::RawFloat; +use dec2flt::common::BiasedFp; +use dec2flt::decimal_seq::{DecimalSeq, parse_decimal_seq}; + +use crate::num::imp::{Float, dec2flt}; /// Parse the significant digits and biased, binary exponent of a float. /// @@ -23,7 +24,7 @@ use crate::num::dec2flt::float::RawFloat; /// /// The algorithms described here are based on "Processing Long Numbers Quickly", /// available here: . -pub(crate) fn parse_long_mantissa(s: &[u8]) -> BiasedFp { +pub(crate) fn parse_long_mantissa(s: &[u8]) -> BiasedFp { const MAX_SHIFT: usize = 60; const NUM_POWERS: usize = 19; const POWERS: [u8; 19] = diff --git a/library/core/src/num/dec2flt/table.rs b/library/core/src/num/imp/dec2flt/table.rs similarity index 100% rename from library/core/src/num/dec2flt/table.rs rename to library/core/src/num/imp/dec2flt/table.rs diff --git a/library/core/src/num/diy_float.rs b/library/core/src/num/imp/diy_float.rs similarity index 96% rename from library/core/src/num/diy_float.rs rename to library/core/src/num/imp/diy_float.rs index e054e7f3f10a7..439b74b31a78b 100644 --- a/library/core/src/num/diy_float.rs +++ b/library/core/src/num/imp/diy_float.rs @@ -22,7 +22,7 @@ pub struct Fp { impl Fp { /// Returns a correctly rounded product of itself and `other`. pub fn mul(self, other: Self) -> Self { - let (lo, hi) = self.f.widening_mul(other.f); + let (lo, hi) = self.f.carrying_mul(other.f, 0); let f = hi + (lo >> 63) /* round */; let e = self.e + other.e + 64; Self { f, e } diff --git a/library/core/src/num/flt2dec/decoder.rs b/library/core/src/num/imp/flt2dec/decoder.rs similarity index 97% rename from library/core/src/num/flt2dec/decoder.rs rename to library/core/src/num/imp/flt2dec/decoder.rs index bd6e2cdbafec8..5ccc91f4c9faf 100644 --- a/library/core/src/num/flt2dec/decoder.rs +++ b/library/core/src/num/imp/flt2dec/decoder.rs @@ -1,7 +1,7 @@ //! Decodes a floating-point value into individual parts and error ranges. use crate::num::FpCategory; -use crate::num::dec2flt::float::RawFloat; +use crate::num::imp::FloatExt; /// Decoded unsigned finite value, such that: /// @@ -40,7 +40,7 @@ pub enum FullDecoded { } /// A floating point type which can be `decode`d. -pub trait DecodableFloat: RawFloat + Copy { +pub trait DecodableFloat: FloatExt + Copy { /// The minimum positive normalized value. fn min_pos_norm_value() -> Self; } diff --git a/library/core/src/num/flt2dec/estimator.rs b/library/core/src/num/imp/flt2dec/estimator.rs similarity index 100% rename from library/core/src/num/flt2dec/estimator.rs rename to library/core/src/num/imp/flt2dec/estimator.rs diff --git a/library/core/src/num/flt2dec/mod.rs b/library/core/src/num/imp/flt2dec/mod.rs similarity index 92% rename from library/core/src/num/flt2dec/mod.rs rename to library/core/src/num/imp/flt2dec/mod.rs index e79a00a865969..cf895b3e89e66 100644 --- a/library/core/src/num/flt2dec/mod.rs +++ b/library/core/src/num/imp/flt2dec/mod.rs @@ -244,18 +244,21 @@ fn digits_to_dec_str<'a>( } /// Formats the given decimal digits `0.<...buf...> * 10^exp` into the exponential -/// form with at least the given number of significant digits. When `upper` is `true`, +/// form with at least the given number of fractional digits. When `upper` is `true`, /// the exponent will be prefixed by `E`; otherwise that's `e`. The result is /// stored to the supplied parts array and a slice of written parts is returned. /// -/// `min_digits` can be less than the number of actual significant digits in `buf`; +/// `frac_digits` can be less than the number of actual fractional digits in `buf`; /// it will be ignored and full digits will be printed. It is only used to print -/// additional zeroes after rendered digits. Thus, `min_digits == 0` means that +/// additional zeroes after rendered digits. Thus, `frac_digits == 0` means that /// it will only print the given digits and nothing else. +/// +/// For example, `buf = b"123", exp = 3, frac_digits = 4` yields the parts for +/// `1.2300e2`. fn digits_to_exp_str<'a>( buf: &'a [u8], exp: i16, - min_ndigits: usize, + frac_digits: usize, upper: bool, parts: &'a mut [MaybeUninit>], ) -> &'a [Part<'a>] { @@ -268,12 +271,22 @@ fn digits_to_exp_str<'a>( parts[n] = MaybeUninit::new(Part::Copy(&buf[..1])); n += 1; - if buf.len() > 1 || min_ndigits > 1 { + // The first generated digit becomes the integral digit, anything after that is already part of + // the fractional portion we can emit verbatim. + let actual_frac_digits = buf.len() - 1; + if actual_frac_digits > 0 || frac_digits > 0 { + // Emit a decimal point either when we already have fractional digits or when the requested + // precision needs trailing zeroes after the radix point. parts[n] = MaybeUninit::new(Part::Copy(b".")); - parts[n + 1] = MaybeUninit::new(Part::Copy(&buf[1..])); - n += 2; - if min_ndigits > buf.len() { - parts[n] = MaybeUninit::new(Part::Zero(min_ndigits - buf.len())); + n += 1; + if actual_frac_digits > 0 { + parts[n] = MaybeUninit::new(Part::Copy(&buf[1..])); + n += 1; + } + if frac_digits > actual_frac_digits { + // format_exact exhausted the meaningful digits, so extend the fractional part with + // zeroes up to the requested precision. + parts[n] = MaybeUninit::new(Part::Zero(frac_digits - actual_frac_digits)); n += 1; } } @@ -492,7 +505,7 @@ fn estimate_max_buf_len(exp: i16) -> usize { } /// Formats given floating point number into the exponential form with -/// exactly given number of significant digits. The result is stored to +/// exactly given number of fractional digits. The result is stored to /// the supplied parts array while utilizing given byte buffer as a scratch. /// `upper` is used to determine the case of the exponent prefix (`e` or `E`). /// The first part to be rendered is always a `Part::Sign` (which can be @@ -502,8 +515,10 @@ fn estimate_max_buf_len(exp: i16) -> usize { /// It should return the part of the buffer that it initialized. /// You probably would want `strategy::grisu::format_exact` for this. /// -/// The byte buffer should be at least `ndigits` bytes long unless `ndigits` is -/// so large that only the fixed number of digits will be ever written. +/// The returned format is `[sign][digit][.fraction?][zero padding?][e|E][exponent]`. +/// +/// The byte buffer should be at least `frac_digits + 1` bytes long unless +/// `frac_digits` is so large that only the fixed number of digits will be ever written. /// (The tipping point for `f64` is about 800, so 1000 bytes should be enough.) /// There should be at least 6 parts available, due to the worst case like /// `[+][1][.][2345][e][-][6]`. @@ -511,7 +526,7 @@ pub fn to_exact_exp_str<'a, T, F>( mut format_exact: F, v: T, sign: Sign, - ndigits: usize, + frac_digits: usize, upper: bool, buf: &'a mut [MaybeUninit], parts: &'a mut [MaybeUninit>], @@ -521,7 +536,6 @@ where F: FnMut(&Decoded, &'a mut [MaybeUninit], i16) -> (&'a [u8], i16), { assert!(parts.len() >= 6); - assert!(ndigits > 0); let (negative, full_decoded) = decode(v); let sign = determine_sign(sign, &full_decoded, negative); @@ -537,10 +551,10 @@ where Formatted { sign, parts: unsafe { parts[..1].assume_init_ref() } } } FullDecoded::Zero => { - if ndigits > 1 { + if frac_digits > 0 { // [0.][0000][e0] parts[0] = MaybeUninit::new(Part::Copy(b"0.")); - parts[1] = MaybeUninit::new(Part::Zero(ndigits - 1)); + parts[1] = MaybeUninit::new(Part::Zero(frac_digits)); parts[2] = MaybeUninit::new(Part::Copy(if upper { b"E0" } else { b"e0" })); Formatted { sign, @@ -558,11 +572,14 @@ where } FullDecoded::Finite(ref decoded) => { let maxlen = estimate_max_buf_len(decoded.exp); - assert!(buf.len() >= ndigits || buf.len() >= maxlen); - - let trunc = if ndigits < maxlen { ndigits } else { maxlen }; - let (buf, exp) = format_exact(decoded, &mut buf[..trunc], i16::MIN); - Formatted { sign, parts: digits_to_exp_str(buf, exp, ndigits, upper, parts) } + // Scratch space is only needed for the significant digits that `format_exact` can + // actually generate. Any remaining requested fractional precision becomes a trailing + // `Part::Zero`. + let sig_digits = if frac_digits < maxlen { frac_digits + 1 } else { maxlen }; + assert!(buf.len() >= sig_digits); + + let (buf, exp) = format_exact(decoded, &mut buf[..sig_digits], i16::MIN); + Formatted { sign, parts: digits_to_exp_str(buf, exp, frac_digits, upper, parts) } } } } diff --git a/library/core/src/num/flt2dec/strategy/dragon.rs b/library/core/src/num/imp/flt2dec/strategy/dragon.rs similarity index 98% rename from library/core/src/num/flt2dec/strategy/dragon.rs rename to library/core/src/num/imp/flt2dec/strategy/dragon.rs index dd73e4b4846d5..de19ca6bb664d 100644 --- a/library/core/src/num/flt2dec/strategy/dragon.rs +++ b/library/core/src/num/imp/flt2dec/strategy/dragon.rs @@ -4,11 +4,13 @@ //! [^1]: Burger, R. G. and Dybvig, R. K. 1996. Printing floating-point numbers //! quickly and accurately. SIGPLAN Not. 31, 5 (May. 1996), 108-116. +use flt2dec::estimator::estimate_scaling_factor; +use flt2dec::{Decoded, MAX_SIG_DIGITS, round_up}; + use crate::cmp::Ordering; use crate::mem::MaybeUninit; -use crate::num::bignum::{Big32x40 as Big, Digit32 as Digit}; -use crate::num::flt2dec::estimator::estimate_scaling_factor; -use crate::num::flt2dec::{Decoded, MAX_SIG_DIGITS, round_up}; +use crate::num::imp::bignum::{Big32x40 as Big, Digit32 as Digit}; +use crate::num::imp::flt2dec; static POW10: [Digit; 10] = [1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000, 1000000000]; diff --git a/library/core/src/num/flt2dec/strategy/grisu.rs b/library/core/src/num/imp/flt2dec/strategy/grisu.rs similarity index 99% rename from library/core/src/num/flt2dec/strategy/grisu.rs rename to library/core/src/num/imp/flt2dec/strategy/grisu.rs index d3bbb0934e0ff..f7ee465829340 100644 --- a/library/core/src/num/flt2dec/strategy/grisu.rs +++ b/library/core/src/num/imp/flt2dec/strategy/grisu.rs @@ -5,9 +5,11 @@ //! [^1]: Florian Loitsch. 2010. Printing floating-point numbers quickly and //! accurately with integers. SIGPLAN Not. 45, 6 (June 2010), 233-243. +use flt2dec::{Decoded, MAX_SIG_DIGITS, round_up}; + use crate::mem::MaybeUninit; -use crate::num::diy_float::Fp; -use crate::num::flt2dec::{Decoded, MAX_SIG_DIGITS, round_up}; +use crate::num::imp::diy_float::Fp; +use crate::num::imp::flt2dec; // see the comments in `format_shortest_opt` for the rationale. #[doc(hidden)] @@ -455,7 +457,7 @@ pub fn format_shortest<'a>( d: &Decoded, buf: &'a mut [MaybeUninit], ) -> (/*digits*/ &'a [u8], /*exp*/ i16) { - use crate::num::flt2dec::strategy::dragon::format_shortest as fallback; + use flt2dec::strategy::dragon::format_shortest as fallback; // SAFETY: The borrow checker is not smart enough to let us use `buf` // in the second branch, so we launder the lifetime here. But we only re-use // `buf` if `format_shortest_opt` returned `None` so this is okay. @@ -765,7 +767,7 @@ pub fn format_exact<'a>( buf: &'a mut [MaybeUninit], limit: i16, ) -> (/*digits*/ &'a [u8], /*exp*/ i16) { - use crate::num::flt2dec::strategy::dragon::format_exact as fallback; + use flt2dec::strategy::dragon::format_exact as fallback; // SAFETY: The borrow checker is not smart enough to let us use `buf` // in the second branch, so we launder the lifetime here. But we only re-use // `buf` if `format_exact_opt` returned `None` so this is okay. diff --git a/library/core/src/num/fmt.rs b/library/core/src/num/imp/fmt.rs similarity index 87% rename from library/core/src/num/fmt.rs rename to library/core/src/num/imp/fmt.rs index 0e4b2844d8192..db5dfb37ed423 100644 --- a/library/core/src/num/fmt.rs +++ b/library/core/src/num/imp/fmt.rs @@ -68,9 +68,14 @@ pub struct Formatted<'a> { } impl<'a> Formatted<'a> { - /// Returns the exact byte length of combined formatted result. + /// Returns the byte length of combined formatted result. + /// + /// Saturates at `usize::MAX` if the actual length is larger. + /// + /// This matters on 16-bit targets, where exponential formatting can exceed + /// `usize::MAX` by emitting `u16::MAX` trailing zeroes plus `"1."` / `"e0"`. pub fn len(&self) -> usize { - self.sign.len() + self.parts.iter().map(|part| part.len()).sum::() + self.parts.iter().fold(self.sign.len(), |len, part| len.saturating_add(part.len())) } /// Writes all formatted parts into the supplied buffer. diff --git a/library/core/src/num/int_bits.rs b/library/core/src/num/imp/int_bits.rs similarity index 97% rename from library/core/src/num/int_bits.rs rename to library/core/src/num/imp/int_bits.rs index 7e54591922358..2bc95e66e7ef6 100644 --- a/library/core/src/num/int_bits.rs +++ b/library/core/src/num/imp/int_bits.rs @@ -64,7 +64,7 @@ macro_rules! uint_impl { ($U:ident) => { - pub(super) mod $U { + pub(in crate::num) mod $U { const STAGES: usize = $U::BITS.ilog2() as usize; #[inline] const fn prepare(sparse: $U) -> [$U; STAGES] { @@ -100,7 +100,7 @@ macro_rules! uint_impl { } #[inline(always)] - pub(in super::super) const fn extract_impl(mut x: $U, sparse: $U) -> $U { + pub(in crate::num) const fn extract_impl(mut x: $U, sparse: $U) -> $U { let masks = prepare(sparse); x &= sparse; let mut stage = 0; @@ -131,7 +131,7 @@ macro_rules! uint_impl { x } #[inline(always)] - pub(in super::super) const fn deposit_impl(mut x: $U, sparse: $U) -> $U { + pub(in crate::num) const fn deposit_impl(mut x: $U, sparse: $U) -> $U { let masks = prepare(sparse); let mut stage = STAGES; while stage > 0 { diff --git a/library/core/src/num/int_log10.rs b/library/core/src/num/imp/int_log10.rs similarity index 94% rename from library/core/src/num/int_log10.rs rename to library/core/src/num/imp/int_log10.rs index af8e1f90968d6..1da029c6a21c4 100644 --- a/library/core/src/num/int_log10.rs +++ b/library/core/src/num/imp/int_log10.rs @@ -96,7 +96,7 @@ const fn u128_impl(mut val: u128) -> u32 { macro_rules! define_unsigned_ilog10 { ($($ty:ident => $impl_fn:ident,)*) => {$( #[inline] - pub(super) const fn $ty(val: NonZero<$ty>) -> u32 { + pub(in crate::num) const fn $ty(val: NonZero<$ty>) -> u32 { let result = $impl_fn(val.get()); // SAFETY: Integer logarithm is monotonic non-decreasing, so the computed `result` cannot @@ -117,7 +117,7 @@ define_unsigned_ilog10! { } #[inline] -pub(super) const fn usize(val: NonZero) -> u32 { +pub(in crate::num) const fn usize(val: NonZero) -> u32 { #[cfg(target_pointer_width = "16")] let impl_fn = u16; @@ -136,7 +136,7 @@ macro_rules! define_signed_ilog10 { ($($ty:ident => $impl_fn:ident,)*) => {$( // 0 < val <= $ty::MAX #[inline] - pub(super) const fn $ty(val: $ty) -> Option { + pub(in crate::num) const fn $ty(val: $ty) -> Option { if val > 0 { let result = $impl_fn(val.cast_unsigned()); @@ -166,6 +166,6 @@ define_signed_ilog10! { /// on every single primitive type. #[cold] #[track_caller] -pub(super) const fn panic_for_nonpositive_argument() -> ! { +pub(in crate::num) const fn panic_for_nonpositive_argument() -> ! { panic!("argument of integer logarithm must be positive") } diff --git a/library/core/src/num/int_sqrt.rs b/library/core/src/num/imp/int_sqrt.rs similarity index 89% rename from library/core/src/num/int_sqrt.rs rename to library/core/src/num/imp/int_sqrt.rs index c7a322c08c139..c2bb4bf6078f4 100644 --- a/library/core/src/num/int_sqrt.rs +++ b/library/core/src/num/imp/int_sqrt.rs @@ -37,40 +37,10 @@ const U8_ISQRT_WITH_REMAINDER: [(u8, u8); 256] = { #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline] -pub(super) const fn u8(n: u8) -> u8 { +pub(in crate::num) const fn u8(n: u8) -> u8 { U8_ISQRT_WITH_REMAINDER[n as usize].0 } -/// Generates an `i*` function that returns the [integer square root]( -/// https://en.wikipedia.org/wiki/Integer_square_root) of any **nonnegative** -/// input of a specific signed integer type. -macro_rules! signed_fn { - ($SignedT:ident, $UnsignedT:ident) => { - /// Returns the [integer square root]( - /// https://en.wikipedia.org/wiki/Integer_square_root) of any - /// **nonnegative** - #[doc = concat!("[`", stringify!($SignedT), "`](prim@", stringify!($SignedT), ")")] - /// input. - /// - /// # Safety - /// - /// This results in undefined behavior when the input is negative. - #[must_use = "this returns the result of the operation, \ - without modifying the original"] - #[inline] - pub(super) const unsafe fn $SignedT(n: $SignedT) -> $SignedT { - debug_assert!(n >= 0, "Negative input inside `isqrt`."); - $UnsignedT(n as $UnsignedT) as $SignedT - } - }; -} - -signed_fn!(i8, u8); -signed_fn!(i16, u16); -signed_fn!(i32, u32); -signed_fn!(i64, u64); -signed_fn!(i128, u128); - /// Generates a `u*` function that returns the [integer square root]( /// https://en.wikipedia.org/wiki/Integer_square_root) of any input of /// a specific unsigned integer type. @@ -83,7 +53,7 @@ macro_rules! unsigned_fn { #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline] - pub(super) const fn $UnsignedT(mut n: $UnsignedT) -> $UnsignedT { + pub(in crate::num) const fn $UnsignedT(mut n: $UnsignedT) -> $UnsignedT { if n <= <$HalfBitsT>::MAX as $UnsignedT { $HalfBitsT(n as $HalfBitsT) as $UnsignedT } else { @@ -311,6 +281,6 @@ unsigned_fn!(u128, u64, u128_stages); /// on every single primitive type. #[cold] #[track_caller] -pub(super) const fn panic_for_negative_argument() -> ! { +pub(in crate::num) const fn panic_for_negative_argument() -> ! { panic!("argument of integer square root cannot be negative") } diff --git a/library/core/src/num/imp/libm.rs b/library/core/src/num/imp/libm.rs new file mode 100644 index 0000000000000..388f1479b2461 --- /dev/null +++ b/library/core/src/num/imp/libm.rs @@ -0,0 +1,168 @@ +//! Bindings to math functions provided by the system `libm` or by the `libm` crate, exposed +//! via `compiler-builtins`. +//! +//! The functions in the root of this module are "guaranteed" to be available; see the +//! `full_availability` module in compiler-builtins for details. + +// SAFETY: These symbols have standard interfaces in C and are defined by `libm`, or are +// provided by `compiler-builtins` on unsupported platforms. +#[allow(dead_code)] // This list reflects what is available rather than what is consumed. +unsafe extern "C" { + pub(crate) safe fn cbrt(x: f64) -> f64; + pub(crate) safe fn cbrtf(n: f32) -> f32; + pub(crate) safe fn ceil(x: f64) -> f64; + pub(crate) safe fn ceilf(x: f32) -> f32; + pub(crate) safe fn ceilf128(x: f128) -> f128; + pub(crate) safe fn ceilf16(x: f16) -> f16; + pub(crate) safe fn copysign(x: f64, y: f64) -> f64; + pub(crate) safe fn copysignf(x: f32, y: f32) -> f32; + pub(crate) safe fn copysignf128(x: f128, y: f128) -> f128; + pub(crate) safe fn copysignf16(x: f16, y: f16) -> f16; + pub(crate) safe fn fabs(x: f64) -> f64; + pub(crate) safe fn fabsf(x: f32) -> f32; + pub(crate) safe fn fabsf128(x: f128) -> f128; + pub(crate) safe fn fabsf16(x: f16) -> f16; + pub(crate) safe fn fdim(a: f64, b: f64) -> f64; + pub(crate) safe fn fdimf(a: f32, b: f32) -> f32; + pub(crate) safe fn fdimf128(x: f128, y: f128) -> f128; + pub(crate) safe fn fdimf16(x: f16, y: f16) -> f16; + pub(crate) safe fn floor(x: f64) -> f64; + pub(crate) safe fn floorf(x: f32) -> f32; + pub(crate) safe fn floorf128(x: f128) -> f128; + pub(crate) safe fn floorf16(x: f16) -> f16; + pub(crate) safe fn fma(x: f64, y: f64, z: f64) -> f64; + pub(crate) safe fn fmaf(x: f32, y: f32, z: f32) -> f32; + pub(crate) safe fn fmaf128(x: f128, y: f128, z: f128) -> f128; + pub(crate) safe fn fmax(x: f64, y: f64) -> f64; + pub(crate) safe fn fmaxf(x: f32, y: f32) -> f32; + pub(crate) safe fn fmaxf128(x: f128, y: f128) -> f128; + pub(crate) safe fn fmaxf16(x: f16, y: f16) -> f16; + pub(crate) safe fn fmaximum(x: f64, y: f64) -> f64; + pub(crate) safe fn fmaximumf(x: f32, y: f32) -> f32; + pub(crate) safe fn fmaximumf128(x: f128, y: f128) -> f128; + pub(crate) safe fn fmaximumf16(x: f16, y: f16) -> f16; + pub(crate) safe fn fmin(x: f64, y: f64) -> f64; + pub(crate) safe fn fminf(x: f32, y: f32) -> f32; + pub(crate) safe fn fminf128(x: f128, y: f128) -> f128; + pub(crate) safe fn fminf16(x: f16, y: f16) -> f16; + pub(crate) safe fn fminimum(x: f64, y: f64) -> f64; + pub(crate) safe fn fminimumf(x: f32, y: f32) -> f32; + pub(crate) safe fn fminimumf128(x: f128, y: f128) -> f128; + pub(crate) safe fn fminimumf16(x: f16, y: f16) -> f16; + pub(crate) safe fn fmod(x: f64, y: f64) -> f64; + pub(crate) safe fn fmodf(x: f32, y: f32) -> f32; + pub(crate) safe fn fmodf128(x: f128, y: f128) -> f128; + pub(crate) safe fn fmodf16(x: f16, y: f16) -> f16; + pub(crate) safe fn rint(x: f64) -> f64; + pub(crate) safe fn rintf(x: f32) -> f32; + pub(crate) safe fn rintf128(x: f128) -> f128; + pub(crate) safe fn rintf16(x: f16) -> f16; + pub(crate) safe fn round(x: f64) -> f64; + pub(crate) safe fn roundeven(x: f64) -> f64; + pub(crate) safe fn roundevenf(x: f32) -> f32; + pub(crate) safe fn roundevenf128(x: f128) -> f128; + pub(crate) safe fn roundevenf16(x: f16) -> f16; + pub(crate) safe fn roundf(x: f32) -> f32; + pub(crate) safe fn roundf128(x: f128) -> f128; + pub(crate) safe fn roundf16(x: f16) -> f16; + pub(crate) safe fn sqrt(x: f64) -> f64; + pub(crate) safe fn sqrtf(x: f32) -> f32; + pub(crate) safe fn sqrtf128(x: f128) -> f128; + pub(crate) safe fn sqrtf16(x: f16) -> f16; + pub(crate) safe fn trunc(x: f64) -> f64; + pub(crate) safe fn truncf(x: f32) -> f32; + pub(crate) safe fn truncf128(x: f128) -> f128; + pub(crate) safe fn truncf16(x: f16) -> f16; +} + +/// These symbols will be available when `std` is available, and on many no-std platforms. However, +/// since this isn't a guarantee, we cannot rely on them for stable implementations. +pub(crate) mod likely_available { + cfg_select! { + all(target_env = "msvc", target_arch = "x86") => { + /* these symbols are not available on x86 msvc */ + } + _ => { + #[allow(dead_code)] + unsafe extern "C" { + pub(crate) safe fn acosf(n: f32) -> f32; + pub(crate) safe fn asinf(n: f32) -> f32; + pub(crate) safe fn atan2f(a: f32, b: f32) -> f32; + pub(crate) safe fn atanf(n: f32) -> f32; + pub(crate) safe fn cosf(x: f32) -> f32; + pub(crate) safe fn coshf(n: f32) -> f32; + pub(crate) safe fn erfcf(x: f32) -> f32; + pub(crate) safe fn erff(x: f32) -> f32; + pub(crate) safe fn exp2f(x: f32) -> f32; + pub(crate) safe fn expf(x: f32) -> f32; + pub(crate) safe fn expm1f(n: f32) -> f32; + pub(crate) safe fn hypotf(x: f32, y: f32) -> f32; + pub(crate) safe fn ldexpf(f: f32, n: i32) -> f32; + pub(crate) safe fn log10f(x: f32) -> f32; + pub(crate) safe fn log1pf(n: f32) -> f32; + pub(crate) safe fn log2f(x: f32) -> f32; + pub(crate) safe fn logf(x: f32) -> f32; + pub(crate) safe fn powf(x: f32, y: f32) -> f32; + pub(crate) safe fn sinf(x: f32) -> f32; + pub(crate) safe fn sinhf(n: f32) -> f32; + pub(crate) safe fn tanf(n: f32) -> f32; + pub(crate) safe fn tanhf(n: f32) -> f32; + pub(crate) safe fn tgammaf(x: f32) -> f32; + } + } + } + + #[allow(dead_code)] + unsafe extern "C" { + pub(crate) safe fn acos(x: f64) -> f64; + pub(crate) safe fn asin(x: f64) -> f64; + pub(crate) safe fn atan(x: f64) -> f64; + pub(crate) safe fn atan2(x: f64, y: f64) -> f64; + pub(crate) safe fn cos(x: f64) -> f64; + pub(crate) safe fn cosh(x: f64) -> f64; + pub(crate) safe fn erf(x: f64) -> f64; + pub(crate) safe fn erfc(x: f64) -> f64; + pub(crate) safe fn exp(x: f64) -> f64; + pub(crate) safe fn exp2(x: f64) -> f64; + pub(crate) safe fn expm1(x: f64) -> f64; + pub(crate) safe fn hypot(x: f64, y: f64) -> f64; + pub(crate) safe fn ldexp(f: f64, n: i32) -> f64; + pub(crate) safe fn log(x: f64) -> f64; + pub(crate) safe fn log10(x: f64) -> f64; + pub(crate) safe fn log1p(x: f64) -> f64; + pub(crate) safe fn log2(x: f64) -> f64; + pub(crate) safe fn pow(x: f64, y: f64) -> f64; + pub(crate) safe fn sin(x: f64) -> f64; + pub(crate) safe fn sinh(x: f64) -> f64; + pub(crate) safe fn tan(x: f64) -> f64; + pub(crate) safe fn tanh(x: f64) -> f64; + pub(crate) safe fn tgamma(x: f64) -> f64; + } +} + +/// These symbols exist on some platforms but do not have a compiler-builtins fallback. +pub(crate) mod maybe_available { + #[allow(dead_code)] + unsafe extern "C" { + pub(crate) safe fn acosf128(x: f128) -> f128; + pub(crate) safe fn asinf128(x: f128) -> f128; + pub(crate) safe fn atanf128(x: f128) -> f128; + pub(crate) safe fn cbrtf128(x: f128) -> f128; + pub(crate) safe fn cosf128(x: f128) -> f128; + pub(crate) safe fn erff128(x: f128) -> f128; + pub(crate) safe fn expf128(x: f128) -> f128; + pub(crate) safe fn exp2f128(x: f128) -> f128; + pub(crate) safe fn expm1f128(x: f128) -> f128; + pub(crate) safe fn hypotf128(x: f128, y: f128) -> f128; + pub(crate) safe fn ldexpf128(f: f128, n: i32) -> f128; + pub(crate) safe fn log10f128(x: f128) -> f128; + pub(crate) safe fn log1pf128(x: f128) -> f128; + pub(crate) safe fn log2f128(x: f128) -> f128; + pub(crate) safe fn logf128(x: f128) -> f128; + pub(crate) safe fn powf128(x: f128, y: f128) -> f128; + pub(crate) safe fn sinf128(x: f128) -> f128; + pub(crate) safe fn tanf128(x: f128) -> f128; + pub(crate) safe fn tanhf128(x: f128) -> f128; + pub(crate) safe fn tgammaf128(x: f128) -> f128; + } +} diff --git a/library/core/src/num/imp/mod.rs b/library/core/src/num/imp/mod.rs new file mode 100644 index 0000000000000..6fccfd1c238ed --- /dev/null +++ b/library/core/src/num/imp/mod.rs @@ -0,0 +1,21 @@ +//! Numeric routines, separate from API. + +// These modules are public only for testing. +#[cfg(not(no_fp_fmt_parse))] +pub mod bignum; +#[cfg(not(no_fp_fmt_parse))] +pub mod dec2flt; +#[cfg(not(no_fp_fmt_parse))] +pub mod diy_float; +#[cfg(not(no_fp_fmt_parse))] +pub mod flt2dec; +pub mod fmt; + +pub(crate) mod int_bits; +pub(crate) mod int_log10; +pub(crate) mod int_sqrt; +pub(crate) mod libm; +pub(crate) mod overflow_panic; +mod traits; + +pub use traits::{Float, FloatExt, Int}; diff --git a/library/core/src/num/overflow_panic.rs b/library/core/src/num/imp/overflow_panic.rs similarity index 57% rename from library/core/src/num/overflow_panic.rs rename to library/core/src/num/imp/overflow_panic.rs index e30573dd3f392..fd5b88ad324c6 100644 --- a/library/core/src/num/overflow_panic.rs +++ b/library/core/src/num/imp/overflow_panic.rs @@ -4,48 +4,54 @@ #[cold] #[track_caller] -pub(super) const fn add() -> ! { +pub(in crate::num) const fn add() -> ! { panic!("attempt to add with overflow") } #[cold] #[track_caller] -pub(super) const fn sub() -> ! { +pub(in crate::num) const fn sub() -> ! { panic!("attempt to subtract with overflow") } #[cold] #[track_caller] -pub(super) const fn mul() -> ! { +pub(in crate::num) const fn mul() -> ! { panic!("attempt to multiply with overflow") } #[cold] #[track_caller] -pub(super) const fn div() -> ! { - panic!("attempt to divide with overflow") -} - -#[cold] -#[track_caller] -pub(super) const fn rem() -> ! { +pub(in crate::num) const fn rem() -> ! { panic!("attempt to calculate the remainder with overflow") } #[cold] #[track_caller] -pub(super) const fn neg() -> ! { +pub(in crate::num) const fn neg() -> ! { panic!("attempt to negate with overflow") } #[cold] #[track_caller] -pub(super) const fn shr() -> ! { +pub(in crate::num) const fn shr() -> ! { panic!("attempt to shift right with overflow") } #[cold] #[track_caller] -pub(super) const fn shl() -> ! { +pub(in crate::num) const fn shl() -> ! { panic!("attempt to shift left with overflow") } + +#[cold] +#[track_caller] +pub(in crate::num) const fn pow() -> ! { + panic!("attempt to exponentiate with overflow") +} + +#[cold] +#[track_caller] +pub(crate) const fn cast_integer() -> ! { + panic!("attempt to cast integer with overflow") +} diff --git a/library/core/src/num/dec2flt/float.rs b/library/core/src/num/imp/traits.rs similarity index 70% rename from library/core/src/num/dec2flt/float.rs rename to library/core/src/num/imp/traits.rs index 21aabdc8addb4..3a7ea23f73f31 100644 --- a/library/core/src/num/dec2flt/float.rs +++ b/library/core/src/num/imp/traits.rs @@ -1,10 +1,14 @@ -//! Helper trait for generic float types. +//! Numeric traits used for internal implementations. -use core::f64; +#![doc(hidden)] +#![unstable( + feature = "num_internals", + reason = "internal routines only exposed for testing", + issue = "none" +)] -use crate::fmt::{Debug, LowerExp}; use crate::num::FpCategory; -use crate::ops::{self, Add, Div, Mul, Neg}; +use crate::{f64, fmt, ops}; /// Lossy `as` casting between two types. pub trait CastInto: Copy { @@ -12,11 +16,11 @@ pub trait CastInto: Copy { } /// Collection of traits that allow us to be generic over integer size. -pub trait Integer: +pub trait Int: Sized + Clone + Copy - + Debug + + fmt::Debug + ops::Shr + ops::Shl + ops::BitAnd @@ -37,7 +41,7 @@ macro_rules! int { } } - impl Integer for $ty { + impl Int for $ty { const ZERO: Self = 0; const ONE: Self = 1; } @@ -48,27 +52,22 @@ macro_rules! int { int!(u16, u32, u64); /// A helper trait to avoid duplicating basically all the conversion code for IEEE floats. -/// -/// See the parent module's doc comment for why this is necessary. -/// -/// Should **never ever** be implemented for other types or be used outside the `dec2flt` module. #[doc(hidden)] -pub trait RawFloat: +pub trait Float: Sized - + Div - + Neg - + Mul - + Add - + LowerExp + + ops::Div + + ops::Neg + + ops::Mul + + ops::Add + + fmt::Debug + PartialEq + PartialOrd + Default + Clone + Copy - + Debug { /// The unsigned integer with the same size as the float - type Int: Integer + Into; + type Int: Int + Into; /* general constants */ @@ -128,8 +127,6 @@ pub trait RawFloat: const MIN_EXPONENT_ROUND_TO_EVEN: i32; const MAX_EXPONENT_ROUND_TO_EVEN: i32; - /* limits related to Fast pathing */ - /// Largest decimal exponent for a non-infinite value. /// /// This is the max exponent in binary converted to the max exponent in decimal. Allows fast @@ -151,41 +148,19 @@ pub trait RawFloat: /// compile time since intermediates exceed the range of an `f64`. const SMALLEST_POWER_OF_TEN: i32; - /// Maximum exponent for a fast path case, or `⌊(SIG_BITS+1)/log2(5)⌋` - // assuming FLT_EVAL_METHOD = 0 - const MAX_EXPONENT_FAST_PATH: i64 = { - let log2_5 = f64::consts::LOG2_10 - 1.0; - (Self::SIG_TOTAL_BITS as f64 / log2_5) as i64 - }; - - /// Minimum exponent for a fast path case, or `-⌊(SIG_BITS+1)/log2(5)⌋` - const MIN_EXPONENT_FAST_PATH: i64 = -Self::MAX_EXPONENT_FAST_PATH; - - /// Maximum exponent that can be represented for a disguised-fast path case. - /// This is `MAX_EXPONENT_FAST_PATH + ⌊(SIG_BITS+1)/log2(10)⌋` - const MAX_EXPONENT_DISGUISED_FAST_PATH: i64 = - Self::MAX_EXPONENT_FAST_PATH + (Self::SIG_TOTAL_BITS as f64 / f64::consts::LOG2_10) as i64; - - /// Maximum mantissa for the fast-path (`1 << 53` for f64). - const MAX_MANTISSA_FAST_PATH: u64 = 1 << Self::SIG_TOTAL_BITS; - - /// Converts integer into float through an as cast. - /// This is only called in the fast-path algorithm, and therefore - /// will not lose precision, since the value will always have - /// only if the value is <= Self::MAX_MANTISSA_FAST_PATH. - fn from_u64(v: u64) -> Self; - - /// Performs a raw transmutation from an integer. - fn from_u64_bits(v: u64) -> Self; - - /// Gets a small power-of-ten for fast-path multiplication. - fn pow10_fast_path(exponent: usize) -> Self; - /// Returns the category that this number falls into. fn classify(self) -> FpCategory; /// Transmute to the integer representation fn to_bits(self) -> Self::Int; +} + +/// Items that ideally would be on `Float`, but don't apply to all float types because they +/// rely on the mantissa fitting into a `u64` (which isn't true for `f128`). +#[doc(hidden)] +pub trait FloatExt: Float { + /// Performs a raw transmutation from an integer. + fn from_u64_bits(v: u64) -> Self; /// Returns the mantissa, exponent and sign as integers. /// @@ -219,7 +194,7 @@ const fn pow2_to_pow10(a: i64) -> i64 { } #[cfg(target_has_reliable_f16)] -impl RawFloat for f16 { +impl Float for f16 { type Int = u16; const INFINITY: Self = Self::INFINITY; @@ -229,30 +204,13 @@ impl RawFloat for f16 { const BITS: u32 = 16; const SIG_TOTAL_BITS: u32 = Self::MANTISSA_DIGITS; - const EXP_MASK: Self::Int = Self::EXP_MASK; - const SIG_MASK: Self::Int = Self::MAN_MASK; + const EXP_MASK: Self::Int = Self::EXPONENT_MASK; + const SIG_MASK: Self::Int = Self::MANTISSA_MASK; const MIN_EXPONENT_ROUND_TO_EVEN: i32 = -22; const MAX_EXPONENT_ROUND_TO_EVEN: i32 = 5; const SMALLEST_POWER_OF_TEN: i32 = -27; - #[inline] - fn from_u64(v: u64) -> Self { - debug_assert!(v <= Self::MAX_MANTISSA_FAST_PATH); - v as _ - } - - #[inline] - fn from_u64_bits(v: u64) -> Self { - Self::from_bits((v & 0xFFFF) as u16) - } - - fn pow10_fast_path(exponent: usize) -> Self { - #[allow(clippy::use_self)] - const TABLE: [f16; 8] = [1e0, 1e1, 1e2, 1e3, 1e4, 0.0, 0.0, 0.]; - TABLE[exponent & 7] - } - fn to_bits(self) -> Self::Int { self.to_bits() } @@ -262,7 +220,15 @@ impl RawFloat for f16 { } } -impl RawFloat for f32 { +#[cfg(target_has_reliable_f16)] +impl FloatExt for f16 { + #[inline] + fn from_u64_bits(v: u64) -> Self { + Self::from_bits((v & 0xFFFF) as u16) + } +} + +impl Float for f32 { type Int = u32; const INFINITY: Self = f32::INFINITY; @@ -272,31 +238,13 @@ impl RawFloat for f32 { const BITS: u32 = 32; const SIG_TOTAL_BITS: u32 = Self::MANTISSA_DIGITS; - const EXP_MASK: Self::Int = Self::EXP_MASK; - const SIG_MASK: Self::Int = Self::MAN_MASK; + const EXP_MASK: Self::Int = Self::EXPONENT_MASK; + const SIG_MASK: Self::Int = Self::MANTISSA_MASK; const MIN_EXPONENT_ROUND_TO_EVEN: i32 = -17; const MAX_EXPONENT_ROUND_TO_EVEN: i32 = 10; const SMALLEST_POWER_OF_TEN: i32 = -65; - #[inline] - fn from_u64(v: u64) -> Self { - debug_assert!(v <= Self::MAX_MANTISSA_FAST_PATH); - v as _ - } - - #[inline] - fn from_u64_bits(v: u64) -> Self { - f32::from_bits((v & 0xFFFFFFFF) as u32) - } - - fn pow10_fast_path(exponent: usize) -> Self { - #[allow(clippy::use_self)] - const TABLE: [f32; 16] = - [1e0, 1e1, 1e2, 1e3, 1e4, 1e5, 1e6, 1e7, 1e8, 1e9, 1e10, 0., 0., 0., 0., 0.]; - TABLE[exponent & 15] - } - fn to_bits(self) -> Self::Int { self.to_bits() } @@ -306,7 +254,14 @@ impl RawFloat for f32 { } } -impl RawFloat for f64 { +impl FloatExt for f32 { + #[inline] + fn from_u64_bits(v: u64) -> Self { + f32::from_bits((v & 0xFFFFFFFF) as u32) + } +} + +impl Float for f64 { type Int = u64; const INFINITY: Self = Self::INFINITY; @@ -316,32 +271,13 @@ impl RawFloat for f64 { const BITS: u32 = 64; const SIG_TOTAL_BITS: u32 = Self::MANTISSA_DIGITS; - const EXP_MASK: Self::Int = Self::EXP_MASK; - const SIG_MASK: Self::Int = Self::MAN_MASK; + const EXP_MASK: Self::Int = Self::EXPONENT_MASK; + const SIG_MASK: Self::Int = Self::MANTISSA_MASK; const MIN_EXPONENT_ROUND_TO_EVEN: i32 = -4; const MAX_EXPONENT_ROUND_TO_EVEN: i32 = 23; const SMALLEST_POWER_OF_TEN: i32 = -342; - #[inline] - fn from_u64(v: u64) -> Self { - debug_assert!(v <= Self::MAX_MANTISSA_FAST_PATH); - v as _ - } - - #[inline] - fn from_u64_bits(v: u64) -> Self { - f64::from_bits(v) - } - - fn pow10_fast_path(exponent: usize) -> Self { - const TABLE: [f64; 32] = [ - 1e0, 1e1, 1e2, 1e3, 1e4, 1e5, 1e6, 1e7, 1e8, 1e9, 1e10, 1e11, 1e12, 1e13, 1e14, 1e15, - 1e16, 1e17, 1e18, 1e19, 1e20, 1e21, 1e22, 0., 0., 0., 0., 0., 0., 0., 0., 0., - ]; - TABLE[exponent & 31] - } - fn to_bits(self) -> Self::Int { self.to_bits() } @@ -350,3 +286,10 @@ impl RawFloat for f64 { self.classify() } } + +impl FloatExt for f64 { + #[inline] + fn from_u64_bits(v: u64) -> Self { + f64::from_bits(v) + } +} diff --git a/library/core/src/num/int_macros.rs b/library/core/src/num/int_macros.rs index 3341fdb24b291..115ca0b717af4 100644 --- a/library/core/src/num/int_macros.rs +++ b/library/core/src/num/int_macros.rs @@ -173,14 +173,13 @@ macro_rules! int_impl { /// # Examples /// /// ``` - /// #![feature(isolate_most_least_significant_one)] - /// #[doc = concat!("let n: ", stringify!($SelfT), " = 0b_01100100;")] /// /// assert_eq!(n.isolate_highest_one(), 0b_01000000); #[doc = concat!("assert_eq!(0_", stringify!($SelfT), ".isolate_highest_one(), 0);")] /// ``` - #[unstable(feature = "isolate_most_least_significant_one", issue = "136909")] + #[stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] + #[rustc_const_stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -194,14 +193,13 @@ macro_rules! int_impl { /// # Examples /// /// ``` - /// #![feature(isolate_most_least_significant_one)] - /// #[doc = concat!("let n: ", stringify!($SelfT), " = 0b_01100100;")] /// /// assert_eq!(n.isolate_lowest_one(), 0b_00000100); #[doc = concat!("assert_eq!(0_", stringify!($SelfT), ".isolate_lowest_one(), 0);")] /// ``` - #[unstable(feature = "isolate_most_least_significant_one", issue = "136909")] + #[stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] + #[rustc_const_stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -212,17 +210,19 @@ macro_rules! int_impl { /// Returns the index of the highest bit set to one in `self`, or `None` /// if `self` is `0`. /// + /// Note that for non-negative numbers, this is equivalent to + /// [`checked_ilog2`](Self::checked_ilog2). + /// /// # Examples /// /// ``` - /// #![feature(int_lowest_highest_one)] - /// #[doc = concat!("assert_eq!(0b0_", stringify!($SelfT), ".highest_one(), None);")] #[doc = concat!("assert_eq!(0b1_", stringify!($SelfT), ".highest_one(), Some(0));")] #[doc = concat!("assert_eq!(0b1_0000_", stringify!($SelfT), ".highest_one(), Some(4));")] #[doc = concat!("assert_eq!(0b1_1111_", stringify!($SelfT), ".highest_one(), Some(4));")] /// ``` - #[unstable(feature = "int_lowest_highest_one", issue = "145203")] + #[stable(feature = "int_lowest_highest_one", since = "1.97.0")] + #[rustc_const_stable(feature = "int_lowest_highest_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -236,14 +236,13 @@ macro_rules! int_impl { /// # Examples /// /// ``` - /// #![feature(int_lowest_highest_one)] - /// #[doc = concat!("assert_eq!(0b0_", stringify!($SelfT), ".lowest_one(), None);")] #[doc = concat!("assert_eq!(0b1_", stringify!($SelfT), ".lowest_one(), Some(0));")] #[doc = concat!("assert_eq!(0b1_0000_", stringify!($SelfT), ".lowest_one(), Some(4));")] #[doc = concat!("assert_eq!(0b1_1111_", stringify!($SelfT), ".lowest_one(), Some(0));")] /// ``` - #[unstable(feature = "int_lowest_highest_one", issue = "145203")] + #[stable(feature = "int_lowest_highest_one", since = "1.97.0")] + #[rustc_const_stable(feature = "int_lowest_highest_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -272,6 +271,94 @@ macro_rules! int_impl { self as $UnsignedT } + /// Saturating conversion of `self` to an unsigned integer of the same size. + /// + /// Negative values are clamped to `0`. + /// + /// For other kinds of unsigned integer casts, see + /// [`cast_unsigned`](Self::cast_unsigned), + /// [`checked_cast_unsigned`](Self::checked_cast_unsigned), + /// or [`strict_cast_unsigned`](Self::strict_cast_unsigned). + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_cast_extras)] + #[doc = concat!("let n = ", stringify!($SelfT), "::MIN;")] + /// + #[doc = concat!("assert_eq!(n.saturating_cast_unsigned(), 0", stringify!($UnsignedT), ");")] + #[doc = concat!("assert_eq!(64", stringify!($SelfT), ".saturating_cast_unsigned(), 64", stringify!($UnsignedT), ");")] + /// ``` + #[rustc_const_unstable(feature = "integer_cast_extras", issue = "154650")] + #[unstable(feature = "integer_cast_extras", issue = "154650")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline(always)] + pub const fn saturating_cast_unsigned(self) -> $UnsignedT { + if self >= 0 { + self.cast_unsigned() + } else { + 0 + } + } + + /// Checked conversion of `self` to an unsigned integer of the same size, + /// returning `None` if `self` is negative. + /// + /// For other kinds of unsigned integer casts, see + /// [`cast_unsigned`](Self::cast_unsigned), + /// [`saturating_cast_unsigned`](Self::saturating_cast_unsigned), + /// or [`strict_cast_unsigned`](Self::strict_cast_unsigned). + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_cast_extras)] + #[doc = concat!("let n = ", stringify!($SelfT), "::MIN;")] + /// + #[doc = concat!("assert_eq!(n.checked_cast_unsigned(), None);")] + #[doc = concat!("assert_eq!(64", stringify!($SelfT), ".checked_cast_unsigned(), Some(64", stringify!($UnsignedT), "));")] + /// ``` + #[rustc_const_unstable(feature = "integer_cast_extras", issue = "154650")] + #[unstable(feature = "integer_cast_extras", issue = "154650")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline(always)] + pub const fn checked_cast_unsigned(self) -> Option<$UnsignedT> { + if self >= 0 { + Some(self.cast_unsigned()) + } else { + None + } + } + + /// Strict conversion of `self` to an unsigned integer of the same size, + /// which panics if `self` is negative. + /// + /// For other kinds of unsigned integer casts, see + /// [`cast_unsigned`](Self::cast_unsigned), + /// [`checked_cast_unsigned`](Self::checked_cast_unsigned), + /// or [`saturating_cast_unsigned`](Self::saturating_cast_unsigned). + /// + /// # Examples + /// + /// ```should_panic + /// #![feature(integer_cast_extras)] + #[doc = concat!("let _ = ", stringify!($SelfT), "::MIN.strict_cast_unsigned();")] + /// ``` + #[rustc_const_unstable(feature = "integer_cast_extras", issue = "154650")] + #[unstable(feature = "integer_cast_extras", issue = "154650")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline] + #[track_caller] + pub const fn strict_cast_unsigned(self) -> $UnsignedT { + match self.checked_cast_unsigned() { + Some(n) => n, + None => imp::overflow_panic::cast_integer(), + } + } + /// Shifts the bits to the left by a specified amount, `n`, /// wrapping the truncated bits to the end of the resulting integer. /// @@ -390,13 +477,9 @@ macro_rules! int_impl { #[must_use] #[inline] pub const fn from_be(x: Self) -> Self { - #[cfg(target_endian = "big")] - { - x - } - #[cfg(not(target_endian = "big"))] - { - x.swap_bytes() + cfg_select! { + target_endian = "big" => x, + _ => x.swap_bytes(), } } @@ -422,13 +505,9 @@ macro_rules! int_impl { #[must_use] #[inline] pub const fn from_le(x: Self) -> Self { - #[cfg(target_endian = "little")] - { - x - } - #[cfg(not(target_endian = "little"))] - { - x.swap_bytes() + cfg_select! { + target_endian = "little" => x, + _ => x.swap_bytes(), } } @@ -459,13 +538,9 @@ macro_rules! int_impl { without modifying the original"] #[inline] pub const fn to_be(self) -> Self { // or not to be? - #[cfg(target_endian = "big")] - { - self - } - #[cfg(not(target_endian = "big"))] - { - self.swap_bytes() + cfg_select! { + target_endian = "big" => self, + _ => self.swap_bytes(), } } @@ -496,13 +571,9 @@ macro_rules! int_impl { without modifying the original"] #[inline] pub const fn to_le(self) -> Self { - #[cfg(target_endian = "little")] - { - self - } - #[cfg(not(target_endian = "little"))] - { - self.swap_bytes() + cfg_select! { + target_endian = "little" => self, + _ => self.swap_bytes(), } } @@ -553,7 +624,7 @@ macro_rules! int_impl { #[track_caller] pub const fn strict_add(self, rhs: Self) -> Self { let (a, b) = self.overflowing_add(rhs); - if b { overflow_panic::add() } else { a } + if b { imp::overflow_panic::add() } else { a } } /// Unchecked integer addition. Computes `self + rhs`, assuming overflow @@ -644,7 +715,7 @@ macro_rules! int_impl { #[track_caller] pub const fn strict_add_unsigned(self, rhs: $UnsignedT) -> Self { let (a, b) = self.overflowing_add_unsigned(rhs); - if b { overflow_panic::add() } else { a } + if b { imp::overflow_panic::add() } else { a } } /// Checked integer subtraction. Computes `self - rhs`, returning `None` if @@ -694,7 +765,7 @@ macro_rules! int_impl { #[track_caller] pub const fn strict_sub(self, rhs: Self) -> Self { let (a, b) = self.overflowing_sub(rhs); - if b { overflow_panic::sub() } else { a } + if b { imp::overflow_panic::sub() } else { a } } /// Unchecked integer subtraction. Computes `self - rhs`, assuming overflow @@ -785,7 +856,7 @@ macro_rules! int_impl { #[track_caller] pub const fn strict_sub_unsigned(self, rhs: $UnsignedT) -> Self { let (a, b) = self.overflowing_sub_unsigned(rhs); - if b { overflow_panic::sub() } else { a } + if b { imp::overflow_panic::sub() } else { a } } /// Checked integer multiplication. Computes `self * rhs`, returning `None` if @@ -835,7 +906,7 @@ macro_rules! int_impl { #[track_caller] pub const fn strict_mul(self, rhs: Self) -> Self { let (a, b) = self.overflowing_mul(rhs); - if b { overflow_panic::mul() } else { a } + if b { imp::overflow_panic::mul() } else { a } } /// Unchecked integer multiplication. Computes `self * rhs`, assuming overflow @@ -915,9 +986,12 @@ macro_rules! int_impl { /// This function will always panic on overflow, regardless of whether overflow checks are enabled. /// /// The only case where such an overflow can occur is when one divides `MIN / -1` on a signed type (where - /// `MIN` is the negative minimal value for the type); this is equivalent to `-MIN`, a positive value + /// [`MIN`](Self::MIN) is the negative minimal value for the type); the result of this is `-MIN`, a positive value /// that is too large to represent in the type. /// + /// Note that this is equivalent to normal division: `MIN / -1` will also panic both in + /// debug and release builds. + /// /// # Examples /// /// ``` @@ -942,8 +1016,8 @@ macro_rules! int_impl { #[inline] #[track_caller] pub const fn strict_div(self, rhs: Self) -> Self { - let (a, b) = self.overflowing_div(rhs); - if b { overflow_panic::div() } else { a } + // Normal division already checks for "div-by-minus-1". + self / rhs } /// Checked Euclidean division. Computes `self.div_euclid(rhs)`, @@ -982,9 +1056,12 @@ macro_rules! int_impl { /// This function will always panic on overflow, regardless of whether overflow checks are enabled. /// /// The only case where such an overflow can occur is when one divides `MIN / -1` on a signed type (where - /// `MIN` is the negative minimal value for the type); this is equivalent to `-MIN`, a positive value + /// [`MIN`](Self::MIN) is the negative minimal value for the type); the result of this is `-MIN`, a positive value /// that is too large to represent in the type. /// + /// Note that this is equivalent to `div_euclid`: `MIN.div_euclid(-1)` will also panic both + /// in debug and release builds. + /// /// # Examples /// /// ``` @@ -1009,8 +1086,8 @@ macro_rules! int_impl { #[inline] #[track_caller] pub const fn strict_div_euclid(self, rhs: Self) -> Self { - let (a, b) = self.overflowing_div_euclid(rhs); - if b { overflow_panic::div() } else { a } + // Normal `div_euclid` already checks for "div-by-minus-1". + self.div_euclid(rhs) } /// Checked integer division without remainder. Computes `self / rhs`, @@ -1113,7 +1190,7 @@ macro_rules! int_impl { ( lhs: $SelfT = self, rhs: $SelfT = rhs, - ) => rhs > 0 && lhs % rhs == 0 && (lhs != <$SelfT>::MIN || rhs != -1), + ) => rhs != 0 && lhs % rhs == 0 && (lhs != <$SelfT>::MIN || rhs != -1), ); // SAFETY: Same precondition unsafe { intrinsics::exact_div(self, rhs) } @@ -1155,7 +1232,7 @@ macro_rules! int_impl { /// This function will always panic on overflow, regardless of whether overflow checks are enabled. /// /// The only case where such an overflow can occur is `x % y` for `MIN / -1` on a - /// signed type (where `MIN` is the negative minimal value), which is invalid due to implementation artifacts. + /// signed type (where [`MIN`](Self::MIN) is the negative minimal value), which is invalid due to implementation artifacts. /// /// # Examples /// @@ -1182,7 +1259,7 @@ macro_rules! int_impl { #[track_caller] pub const fn strict_rem(self, rhs: Self) -> Self { let (a, b) = self.overflowing_rem(rhs); - if b { overflow_panic::rem() } else { a } + if b { imp::overflow_panic::rem() } else { a } } /// Checked Euclidean remainder. Computes `self.rem_euclid(rhs)`, returning `None` @@ -1221,7 +1298,7 @@ macro_rules! int_impl { /// This function will always panic on overflow, regardless of whether overflow checks are enabled. /// /// The only case where such an overflow can occur is `x % y` for `MIN / -1` on a - /// signed type (where `MIN` is the negative minimal value), which is invalid due to implementation artifacts. + /// signed type (where [`MIN`](Self::MIN) is the negative minimal value), which is invalid due to implementation artifacts. /// /// # Examples /// @@ -1248,7 +1325,7 @@ macro_rules! int_impl { #[track_caller] pub const fn strict_rem_euclid(self, rhs: Self) -> Self { let (a, b) = self.overflowing_rem_euclid(rhs); - if b { overflow_panic::rem() } else { a } + if b { imp::overflow_panic::rem() } else { a } } /// Checked negation. Computes `-self`, returning `None` if `self == MIN`. @@ -1328,7 +1405,7 @@ macro_rules! int_impl { #[track_caller] pub const fn strict_neg(self) -> Self { let (a, b) = self.overflowing_neg(); - if b { overflow_panic::neg() } else { a } + if b { imp::overflow_panic::neg() } else { a } } /// Checked shift left. Computes `self << rhs`, returning `None` if `rhs` is larger @@ -1384,7 +1461,7 @@ macro_rules! int_impl { #[track_caller] pub const fn strict_shl(self, rhs: u32) -> Self { let (a, b) = self.overflowing_shl(rhs); - if b { overflow_panic::shl() } else { a } + if b { imp::overflow_panic::shl() } else { a } } /// Unchecked shift left. Computes `self << rhs`, assuming that @@ -1565,7 +1642,7 @@ macro_rules! int_impl { #[track_caller] pub const fn strict_shr(self, rhs: u32) -> Self { let (a, b) = self.overflowing_shr(rhs); - if b { overflow_panic::shr() } else { a } + if b { imp::overflow_panic::shr() } else { a } } /// Unchecked shift right. Computes `self >> rhs`, assuming that @@ -1770,11 +1847,38 @@ macro_rules! int_impl { without modifying the original"] #[inline] pub const fn checked_pow(self, mut exp: u32) -> Option { + let mut base = self; + let mut acc: Self = 1; + + if intrinsics::is_val_statically_known(base) && base.unsigned_abs().is_power_of_two() { + let k = base.unsigned_abs().ilog2(); + let shift = try_opt!(k.checked_mul(exp)); + return if base < 0 && (exp % 2) == 1 { + (-1 as Self).shl_exact(shift) + } else { + (1 as Self).shl_exact(shift) + } + } + if exp == 0 { return Some(1); } - let mut base = self; - let mut acc: Self = 1; + + if intrinsics::is_val_statically_known(exp) { + while exp > 1 { + if (exp & 1) == 1 { + acc = try_opt!(acc.checked_mul(base)); + } + exp /= 2; + base = try_opt!(base.checked_mul(base)); + } + + // since exp!=0, finally the exp must be 1. + // Deal with the final bit of the exponent separately, since + // squaring the base afterwards is not necessary and may cause a + // needless overflow. + return acc.checked_mul(base); + } // Inductive (`acc` starts at 1; `try_opt!` bails on overflow, so // nonzero × nonzero stays nonzero); discharges the nonzero @@ -1821,27 +1925,18 @@ macro_rules! int_impl { without modifying the original"] #[inline] #[track_caller] - pub const fn strict_pow(self, mut exp: u32) -> Self { - if exp == 0 { - return 1; - } - let mut base = self; - let mut acc: Self = 1; - - loop { - if (exp & 1) == 1 { - acc = acc.strict_mul(base); - // since exp!=0, finally the exp must be 1. - if exp == 1 { - return acc; - } - } - exp /= 2; - base = base.strict_mul(base); + pub const fn strict_pow(self, exp: u32) -> Self { + match self.checked_pow(exp) { + Some(x) => x, + None => imp::overflow_panic::pow(), } } - /// Returns the square root of the number, rounded down. + /// Returns the integer square root of the number, rounded down. + /// + /// This function returns the **principal (non-negative) square root**. + /// For a given number `n`, although both `x` and `-x` satisfy x2 = n, + /// this function always returns the non-negative value. /// /// Returns `None` if `self` is negative. /// @@ -1859,10 +1954,9 @@ macro_rules! int_impl { if self < 0 { None } else { - // SAFETY: Input is nonnegative in this `else` branch. - let result = unsafe { - crate::num::int_sqrt::$ActualT(self as $ActualT) as $SelfT - }; + // The upper bound of `$UnsignedT::MAX.isqrt()` told to the compiler + // in the unsigned function also tells it that `result >= 0` + let result = self.cast_unsigned().isqrt().cast_signed(); // Inform the optimizer what the range of outputs is. If // testing `core` crashes with no panic message and a @@ -1876,15 +1970,9 @@ macro_rules! int_impl { // `[0, <$ActualT>::MAX]`, sqrt(n) will be bounded by // `[sqrt(0), sqrt(<$ActualT>::MAX)]`. unsafe { - // SAFETY: `<$ActualT>::MAX` is nonnegative. - const MAX_RESULT: $SelfT = unsafe { - crate::num::int_sqrt::$ActualT(<$ActualT>::MAX) as $SelfT - }; - - crate::hint::assert_unchecked(result >= 0); + const MAX_RESULT: $SelfT = <$SelfT>::MAX.cast_unsigned().isqrt().cast_signed(); crate::hint::assert_unchecked(result <= MAX_RESULT); } - Some(result) } } @@ -2191,8 +2279,8 @@ macro_rules! int_impl { /// boundary of the type. /// /// The only case where such wrapping can occur is when one divides `MIN / -1` on a signed type (where - /// `MIN` is the negative minimal value for the type); this is equivalent to `-MIN`, a positive value - /// that is too large to represent in the type. In such a case, this function returns `MIN` itself. + /// [`MIN`](Self::MIN) is the negative minimal value for the type); this is equivalent to `-MIN`, a positive value + /// that is too large to represent in the type. In such a case, this function returns [`MIN`](Self::MIN) itself. /// /// # Panics /// @@ -2216,9 +2304,9 @@ macro_rules! int_impl { /// Wrapping Euclidean division. Computes `self.div_euclid(rhs)`, /// wrapping around at the boundary of the type. /// - /// Wrapping will only occur in `MIN / -1` on a signed type (where `MIN` is the negative minimal value + /// Wrapping will only occur in `MIN / -1` on a signed type (where [`MIN`](Self::MIN) is the negative minimal value /// for the type). This is equivalent to `-MIN`, a positive value that is too large to represent in the - /// type. In this case, this method returns `MIN` itself. + /// type. In this case, this method returns [`MIN`](Self::MIN) itself. /// /// # Panics /// @@ -2243,7 +2331,7 @@ macro_rules! int_impl { /// boundary of the type. /// /// Such wrap-around never actually occurs mathematically; implementation artifacts make `x % y` - /// invalid for `MIN / -1` on a signed type (where `MIN` is the negative minimal value). In such a case, + /// invalid for `MIN / -1` on a signed type (where [`MIN`](Self::MIN) is the negative minimal value). In such a case, /// this function returns `0`. /// /// # Panics @@ -2268,8 +2356,8 @@ macro_rules! int_impl { /// Wrapping Euclidean remainder. Computes `self.rem_euclid(rhs)`, wrapping around /// at the boundary of the type. /// - /// Wrapping will only occur in `MIN % -1` on a signed type (where `MIN` is the negative minimal value - /// for the type). In this case, this method returns 0. + /// Wrapping will only occur in `MIN % -1` on a signed type (where [`MIN`](Self::MIN) is + /// the negative minimal value for the type). In this case, this method returns 0. /// /// # Panics /// @@ -2293,9 +2381,9 @@ macro_rules! int_impl { /// Wrapping (modular) negation. Computes `-self`, wrapping around at the boundary /// of the type. /// - /// The only case where such wrapping can occur is when one negates `MIN` on a signed type (where `MIN` + /// The only case where such wrapping can occur is when one negates [`MIN`](Self::MIN) on a signed type (where [`MIN`](Self::MIN) /// is the negative minimal value for the type); this is a positive value that is too large to represent - /// in the type. In such a case, this function returns `MIN` itself. + /// in the type. In such a case, this function returns [`MIN`](Self::MIN) itself. /// /// # Examples /// @@ -2318,7 +2406,7 @@ macro_rules! int_impl { /// /// Beware that, unlike most other `wrapping_*` methods on integers, this /// does *not* give the same result as doing the shift in infinite precision - /// then truncating as needed. The behaviour matches what shift instructions + /// then truncating as needed. Instead, the behaviour of this method matches what shift instructions /// do on many processors, and is what the `<<` operator does when overflow /// checks are disabled, but numerically it's weird. Consider, instead, /// using [`Self::unbounded_shl`] which has nicer behaviour. @@ -2356,7 +2444,7 @@ macro_rules! int_impl { /// /// Beware that, unlike most other `wrapping_*` methods on integers, this /// does *not* give the same result as doing the shift in infinite precision - /// then truncating as needed. The behaviour matches what shift instructions + /// then truncating as needed. Instead, the behaviour of this method matches what shift instructions /// do on many processors, and is what the `>>` operator does when overflow /// checks are disabled, but numerically it's weird. Consider, instead, /// using [`Self::unbounded_shr`] which has nicer behaviour. @@ -2394,7 +2482,7 @@ macro_rules! int_impl { /// /// The only case where such wrapping can occur is when one takes the absolute value of the negative /// minimal value for the type; this is a positive value that is too large to represent in the type. In - /// such a case, this function returns `MIN` itself. + /// such a case, this function returns [`MIN`](Self::MIN) itself. /// /// # Examples /// @@ -2454,52 +2542,17 @@ macro_rules! int_impl { #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline] - pub const fn wrapping_pow(self, mut exp: u32) -> Self { - if exp == 0 { - return 1; - } - let mut base = self; - let mut acc: Self = 1; - - if intrinsics::is_val_statically_known(exp) { - #[safety::loop_invariant(exp>=1)] - while exp > 1 { - if (exp & 1) == 1 { - acc = acc.wrapping_mul(base); - } - exp /= 2; - base = base.wrapping_mul(base); - } - - // since exp!=0, finally the exp must be 1. - // Deal with the final bit of the exponent separately, since - // squaring the base afterwards is not necessary. - acc.wrapping_mul(base) - } else { - // This is faster than the above when the exponent is not known - // at compile time. We can't use the same code for the constant - // exponent case because LLVM is currently unable to unroll - // this loop. - #[safety::loop_invariant(true)] - loop { - if (exp & 1) == 1 { - acc = acc.wrapping_mul(base); - // since exp!=0, finally the exp must be 1. - if exp == 1 { - return acc; - } - } - exp /= 2; - base = base.wrapping_mul(base); - } - } + pub const fn wrapping_pow(self, exp: u32) -> Self { + let (a, _) = self.overflowing_pow(exp); + a } /// Calculates `self` + `rhs`. /// /// Returns a tuple of the addition along with a boolean indicating /// whether an arithmetic overflow would occur. If an overflow would have - /// occurred then the wrapped value is returned. + /// occurred then the wrapped value is returned (negative if overflowed + /// above [`MAX`](Self::MAX), non-negative if below [`MIN`](Self::MIN)). /// /// # Examples /// @@ -2534,6 +2587,9 @@ macro_rules! int_impl { /// The output boolean returned by this method is *not* a carry flag, /// and should *not* be added to a more significant word. /// + /// If overflow occurred, the wrapped value is returned (negative if overflowed + /// above [`MAX`](Self::MAX), non-negative if below [`MIN`](Self::MIN)). + /// /// If the input carry is false, this method is equivalent to /// [`overflowing_add`](Self::overflowing_add). /// @@ -2601,7 +2657,8 @@ macro_rules! int_impl { /// Calculates `self` - `rhs`. /// /// Returns a tuple of the subtraction along with a boolean indicating whether an arithmetic overflow - /// would occur. If an overflow would have occurred then the wrapped value is returned. + /// would occur. If an overflow would have occurred then the wrapped value is returned + /// (negative if overflowed above [`MAX`](Self::MAX), non-negative if below [`MIN`](Self::MIN)). /// /// # Examples /// @@ -2637,6 +2694,9 @@ macro_rules! int_impl { /// The output boolean returned by this method is *not* a borrow flag, /// and should *not* be subtracted from a more significant word. /// + /// If overflow occurred, the wrapped value is returned (negative if overflowed + /// above [`MAX`](Self::MAX), non-negative if below [`MIN`](Self::MIN)). + /// /// If the input borrow is false, this method is equivalent to /// [`overflowing_sub`](Self::overflowing_sub). /// @@ -2722,32 +2782,6 @@ macro_rules! int_impl { (a as Self, b) } - /// Calculates the complete product `self * rhs` without the possibility to overflow. - /// - /// This returns the low-order (wrapping) bits and the high-order (overflow) bits - /// of the result as two separate values, in that order. - /// - /// If you also need to add a carry to the wide result, then you want - /// [`Self::carrying_mul`] instead. - /// - /// # Examples - /// - /// Please note that this example is shared among integer types, which is why `i32` is used. - /// - /// ``` - /// #![feature(widening_mul)] - /// assert_eq!(5i32.widening_mul(-2), (4294967286, -1)); - /// assert_eq!(1_000_000_000i32.widening_mul(-10), (2884901888, -3)); - /// ``` - #[unstable(feature = "widening_mul", issue = "152016")] - #[rustc_const_unstable(feature = "widening_mul", issue = "152016")] - #[must_use = "this returns the result of the operation, \ - without modifying the original"] - #[inline] - pub const fn widening_mul(self, rhs: Self) -> ($UnsignedT, Self) { - Self::carrying_mul_add(self, rhs, 0, 0) - } - /// Calculates the "full multiplication" `self * rhs + carry` /// without the possibility to overflow. /// @@ -2758,11 +2792,9 @@ macro_rules! int_impl { /// additional amount of overflow. This allows for chaining together multiple /// multiplications to create "big integers" which represent larger values. /// - /// If you don't need the `carry`, then you can use [`Self::widening_mul`] instead. - /// /// # Examples /// - /// Please note that this example is shared among integer types, which is why `i32` is used. + /// Please note that this example is shared among integer types, which is why [`i32`] is used. /// /// ``` /// #![feature(signed_bigint_helpers)] @@ -2794,8 +2826,7 @@ macro_rules! int_impl { /// additional amount of overflow. This allows for chaining together multiple /// multiplications to create "big integers" which represent larger values. /// - /// If you don't need either `carry`, then you can use [`Self::widening_mul`] instead, - /// and if you only need one `carry`, then you can use [`Self::carrying_mul`] instead. + /// If you only need one `carry`, then you can use [`Self::carrying_mul`] instead. /// /// # Examples /// @@ -2941,7 +2972,7 @@ macro_rules! int_impl { /// Negates self, overflowing if this is equal to the minimum value. /// /// Returns a tuple of the negated version of self along with a boolean indicating whether an overflow - /// happened. If `self` is the minimum value (e.g., `i32::MIN` for values of type `i32`), then the + /// happened. If `self` is the minimum value (e.g., [`i32::MIN`] for values of type [`i32`]), then the /// minimum value will be returned again and `true` will be returned for an overflow happening. /// /// # Examples @@ -3011,7 +3042,7 @@ macro_rules! int_impl { /// /// Returns a tuple of the absolute version of self along with a boolean indicating whether an overflow /// happened. If self is the minimum value - #[doc = concat!("(e.g., ", stringify!($SelfT), "::MIN for values of type ", stringify!($SelfT), "),")] + #[doc = concat!("(e.g., [`", stringify!($SelfT), "::MIN`] for values of type [`", stringify!($SelfT), "`]),")] /// then the minimum value will be returned again and true will be returned /// for an overflow happening. /// @@ -3049,30 +3080,56 @@ macro_rules! int_impl { without modifying the original"] #[inline] pub const fn overflowing_pow(self, mut exp: u32) -> (Self, bool) { - if exp == 0 { - return (1,false); - } let mut base = self; let mut acc: Self = 1; - let mut overflown = false; - // Scratch space for storing results of overflowing_mul. - let mut r; + let mut overflow = false; + let mut tmp_overflow; + + if intrinsics::is_val_statically_known(base) && base.unsigned_abs().is_power_of_two() { + let k = base.unsigned_abs().ilog2(); + let Some(shift) = k.checked_mul(exp) else { + return (0, true) + }; + let base: Self = if base < 0 && (exp % 2) != 0 { -1 } else { 1 }; + return (base.unbounded_shl(shift), base.shl_exact(shift).is_none()); + } + + if exp == 0 { + return (1, false); + } + + if intrinsics::is_val_statically_known(exp) { + while exp > 1 { + if (exp & 1) == 1 { + (acc, tmp_overflow) = acc.overflowing_mul(base); + overflow |= tmp_overflow; + } + exp /= 2; + (base, tmp_overflow) = base.overflowing_mul(base); + overflow |= tmp_overflow; + } + + // since exp!=0, finally the exp must be 1. + // Deal with the final bit of the exponent separately, since + // squaring the base afterwards is not necessary and may cause a + // needless overflow. + (acc, tmp_overflow) = acc.overflowing_mul(base); + overflow |= tmp_overflow; + return (acc, overflow); + } loop { if (exp & 1) == 1 { - r = acc.overflowing_mul(base); + (acc, tmp_overflow) = acc.overflowing_mul(base); + overflow |= tmp_overflow; // since exp!=0, finally the exp must be 1. if exp == 1 { - r.1 |= overflown; - return r; + return (acc, overflow); } - acc = r.0; - overflown |= r.1; } exp /= 2; - r = base.overflowing_mul(base); - base = r.0; - overflown |= r.1; + (base, tmp_overflow) = base.overflowing_mul(base); + overflow |= tmp_overflow; } } @@ -3092,47 +3149,19 @@ macro_rules! int_impl { without modifying the original"] #[inline] #[rustc_inherit_overflow_checks] - pub const fn pow(self, mut exp: u32) -> Self { - if exp == 0 { - return 1; - } - let mut base = self; - let mut acc = 1; - - if intrinsics::is_val_statically_known(exp) { - while exp > 1 { - if (exp & 1) == 1 { - acc = acc * base; - } - exp /= 2; - base = base * base; - } - - // since exp!=0, finally the exp must be 1. - // Deal with the final bit of the exponent separately, since - // squaring the base afterwards is not necessary and may cause a - // needless overflow. - acc * base + pub const fn pow(self, exp: u32) -> Self { + if intrinsics::overflow_checks() { + self.strict_pow(exp) } else { - // This is faster than the above when the exponent is not known - // at compile time. We can't use the same code for the constant - // exponent case because LLVM is currently unable to unroll - // this loop. - loop { - if (exp & 1) == 1 { - acc = acc * base; - // since exp!=0, finally the exp must be 1. - if exp == 1 { - return acc; - } - } - exp /= 2; - base = base * base; - } + self.wrapping_pow(exp) } } - /// Returns the square root of the number, rounded down. + /// Returns the integer square root of the number, rounded down. + /// + /// This function returns the **principal (non-negative) square root**. + /// For a given number `n`, although both `x` and `-x` satisfy x2 = n, + /// this function always returns the non-negative value. /// /// # Panics /// @@ -3152,7 +3181,7 @@ macro_rules! int_impl { pub const fn isqrt(self) -> Self { match self.checked_isqrt() { Some(sqrt) => sqrt, - None => crate::num::int_sqrt::panic_for_negative_argument(), + None => imp::int_sqrt::panic_for_negative_argument(), } } @@ -3170,7 +3199,7 @@ macro_rules! int_impl { /// /// # Panics /// - /// This function will panic if `rhs` is zero or if `self` is `Self::MIN` + /// This function will panic if `rhs` is zero or if `self` is [`Self::MIN`] /// and `rhs` is -1. This behavior is not affected by the `overflow-checks` flag. /// /// # Examples @@ -3208,7 +3237,7 @@ macro_rules! int_impl { /// /// # Panics /// - /// This function will panic if `rhs` is zero or if `self` is `Self::MIN` and + /// This function will panic if `rhs` is zero or if `self` is [`Self::MIN`] and /// `rhs` is -1. This behavior is not affected by the `overflow-checks` flag. /// /// # Examples @@ -3255,7 +3284,7 @@ macro_rules! int_impl { /// /// # Panics /// - /// This function will panic if `rhs` is zero or if `self` is `Self::MIN` + /// This function will panic if `rhs` is zero or if `self` is [`Self::MIN`] /// and `rhs` is -1. This behavior is not affected by the `overflow-checks` flag. /// /// # Examples @@ -3297,7 +3326,7 @@ macro_rules! int_impl { /// /// # Panics /// - /// This function will panic if `rhs` is zero or if `self` is `Self::MIN` + /// This function will panic if `rhs` is zero or if `self` is [`Self::MIN`] /// and `rhs` is -1. This behavior is not affected by the `overflow-checks` flag. /// /// # Examples @@ -3434,8 +3463,8 @@ macro_rules! int_impl { /// rounded down. /// /// This method might not be optimized owing to implementation details; - /// `ilog2` can produce results more efficiently for base 2, and `ilog10` - /// can produce results more efficiently for base 10. + /// [`ilog2`][Self::ilog2] can produce results more efficiently for base 2, + /// and [`ilog10`](Self::ilog10) can produce results more efficiently for base 10. /// /// # Panics /// @@ -3458,7 +3487,7 @@ macro_rules! int_impl { if let Some(log) = self.checked_ilog(base) { log } else { - int_log10::panic_for_nonpositive_argument() + imp::int_log10::panic_for_nonpositive_argument() } } @@ -3483,7 +3512,7 @@ macro_rules! int_impl { if let Some(log) = self.checked_ilog2() { log } else { - int_log10::panic_for_nonpositive_argument() + imp::int_log10::panic_for_nonpositive_argument() } } @@ -3508,7 +3537,7 @@ macro_rules! int_impl { if let Some(log) = self.checked_ilog10() { log } else { - int_log10::panic_for_nonpositive_argument() + imp::int_log10::panic_for_nonpositive_argument() } } @@ -3545,6 +3574,9 @@ macro_rules! int_impl { /// /// Returns `None` if the number is negative or zero. /// + /// Note that for non-negative numbers, this is equivalent to + /// [`highest_one`](Self::highest_one). + /// /// # Examples /// /// ``` @@ -3580,7 +3612,7 @@ macro_rules! int_impl { without modifying the original"] #[inline] pub const fn checked_ilog10(self) -> Option { - int_log10::$ActualT(self as $ActualT) + imp::int_log10::$ActualT(self as $ActualT) } /// Computes the absolute value of `self`. @@ -3908,7 +3940,7 @@ macro_rules! int_impl { #[inline(always)] #[rustc_promotable] #[rustc_const_stable(feature = "const_min_value", since = "1.32.0")] - #[deprecated(since = "TBD", note = "replaced by the `MIN` associated constant on this type")] + #[deprecated(since = "1.99.0", note = "replaced by the `MIN` associated constant on this type")] #[rustc_diagnostic_item = concat!(stringify!($SelfT), "_legacy_fn_min_value")] pub const fn min_value() -> Self { Self::MIN @@ -3922,7 +3954,7 @@ macro_rules! int_impl { #[inline(always)] #[rustc_promotable] #[rustc_const_stable(feature = "const_max_value", since = "1.32.0")] - #[deprecated(since = "TBD", note = "replaced by the `MAX` associated constant on this type")] + #[deprecated(since = "1.99.0", note = "replaced by the `MAX` associated constant on this type")] #[rustc_diagnostic_item = concat!(stringify!($SelfT), "_legacy_fn_max_value")] pub const fn max_value() -> Self { Self::MAX @@ -3954,5 +3986,207 @@ macro_rules! int_impl { self } } + + /// Truncate an integer to an integer of the same size or smaller, preserving the least + /// significant bits. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_widen_truncate)] + #[doc = concat!("assert_eq!(120i8, 120", stringify!($SelfT), ".truncate());")] + #[doc = concat!("assert_eq!(-120i8, (-120", stringify!($SelfT), ").truncate());")] + /// assert_eq!(120i8, 376i32.truncate()); + /// ``` + #[must_use = "this returns the truncated value and does not modify the original"] + #[unstable(feature = "integer_widen_truncate", issue = "154330")] + #[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] + #[inline] + pub const fn truncate(self) -> Target + where Self: [const] traits::TruncateTarget + { + traits::TruncateTarget::internal_truncate(self) + } + + /// Truncate an integer to an integer of the same size or smaller, saturating at numeric bounds + /// instead of truncating. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_widen_truncate)] + #[doc = concat!("assert_eq!(120i8, 120", stringify!($SelfT), ".saturating_truncate());")] + #[doc = concat!("assert_eq!(-120i8, (-120", stringify!($SelfT), ").saturating_truncate());")] + /// assert_eq!(127i8, 376i32.saturating_truncate()); + /// assert_eq!(-128i8, (-1000i32).saturating_truncate()); + /// ``` + #[must_use = "this returns the truncated value and does not modify the original"] + #[unstable(feature = "integer_widen_truncate", issue = "154330")] + #[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] + #[inline] + pub const fn saturating_truncate(self) -> Target + where Self: [const] traits::TruncateTarget + { + traits::TruncateTarget::internal_saturating_truncate(self) + } + + /// Truncate an integer to an integer of the same size or smaller, returning `None` if the value + /// is outside the bounds of the smaller type. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_widen_truncate)] + #[doc = concat!("assert_eq!(Some(120i8), 120", stringify!($SelfT), ".checked_truncate());")] + #[doc = concat!("assert_eq!(Some(-120i8), (-120", stringify!($SelfT), ").checked_truncate());")] + /// assert_eq!(None, 376i32.checked_truncate::()); + /// assert_eq!(None, (-1000i32).checked_truncate::()); + /// ``` + #[must_use = "this returns the truncated value and does not modify the original"] + #[unstable(feature = "integer_widen_truncate", issue = "154330")] + #[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] + #[inline] + pub const fn checked_truncate(self) -> Option + where Self: [const] traits::TruncateTarget + { + traits::TruncateTarget::internal_checked_truncate(self) + } + + /// Widen to an integer of the same size or larger, preserving its value. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_widen_truncate)] + #[doc = concat!("assert_eq!(120i128, 120i8.widen());")] + #[doc = concat!("assert_eq!(-120i128, (-120i8).widen());")] + /// ``` + #[must_use = "this returns the widened value and does not modify the original"] + #[unstable(feature = "integer_widen_truncate", issue = "154330")] + #[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] + #[inline] + pub const fn widen(self) -> Target + where Self: [const] traits::WidenTarget + { + traits::WidenTarget::internal_widen(self) + } + + + /// Converts `self` to the target integer type, saturating at the numeric + /// bounds instead of overflowing. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_casts)] + #[doc = concat!("assert_eq!(i8::MAX, ", stringify!($SelfT), "::MAX.saturating_cast());")] + #[doc = concat!("assert_eq!(i8::MIN, ", stringify!($SelfT), "::MIN.saturating_cast());")] + #[doc = concat!("assert_eq!(42u8, 42", stringify!($SelfT), ".saturating_cast());")] + #[doc = concat!("assert_eq!(0u8, (-42", stringify!($SelfT), ").saturating_cast());")] + /// ``` + #[must_use = "this returns the cast result and does not modify the original"] + #[unstable(feature = "integer_casts", issue = "157388")] + #[rustc_const_unstable(feature = "integer_casts", issue = "157388")] + #[inline(always)] + pub const fn saturating_cast>(self) -> T { + T::saturating_cast_from(self) + } + + /// Converts `self` to the target integer type, wrapping around at the + /// boundary of the target type. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_casts)] + #[doc = concat!("assert_eq!(", stringify!($SelfT), "::MAX as i8, ", stringify!($SelfT), "::MAX.wrapping_cast());")] + #[doc = concat!("assert_eq!(", stringify!($SelfT), "::MIN as i8, ", stringify!($SelfT), "::MIN.wrapping_cast());")] + #[doc = concat!("assert_eq!(42u8, 42", stringify!($SelfT), ".wrapping_cast());")] + #[doc = concat!("assert_eq!(u8::MAX - 41, (-42", stringify!($SelfT), ").wrapping_cast());")] + /// ``` + #[must_use = "this returns the cast result and does not modify the original"] + #[unstable(feature = "integer_casts", issue = "157388")] + #[rustc_const_unstable(feature = "integer_casts", issue = "157388")] + #[inline(always)] + pub const fn wrapping_cast>(self) -> T { + T::wrapping_cast_from(self) + } + + /// Converts `self` to the target integer type, returning `None` if the value + /// is not representable by the target type. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_casts)] + #[doc = concat!("assert_eq!(Some(42u8), 42", stringify!($SelfT), ".checked_cast());")] + #[doc = concat!("assert_eq!((-42", stringify!($SelfT), ").checked_cast::(), None);")] + /// ``` + #[must_use = "this returns the cast result and does not modify the original"] + #[unstable(feature = "integer_casts", issue = "157388")] + #[rustc_const_unstable(feature = "integer_casts", issue = "157388")] + #[inline(always)] + pub const fn checked_cast>(self) -> Option { + T::checked_cast_from(self) + } + + /// Converts `self` to the target integer type, panicking if the value + /// is not representable by the target type. + /// + /// # Panics + /// + /// This function will panic if the value is not representable by the target type. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_casts)] + #[doc = concat!("assert_eq!(42u8, 42", stringify!($SelfT), ".strict_cast());")] + /// ``` + /// + /// The following will panic: + /// + /// ```should_panic + /// #![feature(integer_casts)] + #[doc = concat!("let _ = (-42", stringify!($SelfT), ").strict_cast::();")] + /// ``` + #[must_use = "this returns the cast result and does not modify the original"] + #[unstable(feature = "integer_casts", issue = "157388")] + #[rustc_const_unstable(feature = "integer_casts", issue = "157388")] + #[inline(always)] + #[track_caller] + pub const fn strict_cast>(self) -> T { + T::strict_cast_from(self) + } + + /// Converts `self` to the target integer type, assuming the value is + /// representable by the target type. + /// + /// # Safety + /// + /// This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, + /// or smaller than `T::MIN`, where `T` is the target type. + #[must_use = "this returns the cast result and does not modify the original"] + #[unstable(feature = "integer_casts", issue = "157388")] + #[rustc_const_unstable(feature = "integer_casts", issue = "157388")] + #[inline(always)] + pub const unsafe fn unchecked_cast>(self) -> T { + assert_unsafe_precondition!( + check_language_ub, + concat!(stringify!($SelfT), "::unchecked_cast must fit in the target type"), + ( + // Check has to be performed up-front because it depends on generic T. + in_bounds: bool = { + let cast_val = self.checked_cast::(); + let ret = cast_val.is_some(); + core::mem::forget(cast_val); // We don't have const Drop, but we know it's an int. + ret + }, + ) => in_bounds, + ); + + // SAFETY: this is guaranteed to be safe by the caller. + unsafe { T::unchecked_cast_from(self) } + } } } diff --git a/library/core/src/num/libm.rs b/library/core/src/num/libm.rs deleted file mode 100644 index aeabb08723095..0000000000000 --- a/library/core/src/num/libm.rs +++ /dev/null @@ -1,11 +0,0 @@ -//! Bindings to math functions provided by the system `libm` or by the `libm` crate, exposed -//! via `compiler-builtins`. - -// SAFETY: These symbols have standard interfaces in C and are defined by `libm`, or are -// provided by `compiler-builtins` on unsupported platforms. -unsafe extern "C" { - pub(crate) safe fn cbrt(n: f64) -> f64; - pub(crate) safe fn cbrtf(n: f32) -> f32; - pub(crate) safe fn fdim(a: f64, b: f64) -> f64; - pub(crate) safe fn fdimf(a: f32, b: f32) -> f32; -} diff --git a/library/core/src/num/mod.rs b/library/core/src/num/mod.rs index a44f8138c8d42..c96defe9056a5 100644 --- a/library/core/src/num/mod.rs +++ b/library/core/src/num/mod.rs @@ -4,6 +4,7 @@ use safety::{ensures, requires}; +use crate::convert::{BoundedCastFromInt, CheckedCastFromInt}; #[cfg(kani)] use crate::kani; use crate::panic::const_panic; @@ -31,45 +32,44 @@ macro_rules! sign_dependent_expr { }; } -// All these modules are technically private and only exposed for coretests: -#[cfg(not(no_fp_fmt_parse))] -pub mod bignum; -#[cfg(not(no_fp_fmt_parse))] -pub mod dec2flt; -#[cfg(not(no_fp_fmt_parse))] -pub mod diy_float; -#[cfg(not(no_fp_fmt_parse))] -pub mod flt2dec; -pub mod fmt; +// These modules are public only for testing. +#[doc(hidden)] +#[unstable( + feature = "num_internals", + reason = "internal routines only exposed for testing", + issue = "none" +)] +pub mod imp; #[macro_use] mod int_macros; // import int_impl! #[macro_use] mod uint_macros; // import uint_impl! +mod complex; mod error; -mod int_bits; -mod int_log10; -mod int_sqrt; -pub(crate) mod libm; +#[cfg(not(no_fp_fmt_parse))] +mod float_parse; mod nonzero; -mod overflow_panic; mod saturating; +mod traits; mod wrapping; /// 100% perma-unstable #[doc(hidden)] pub mod niche_types; -#[stable(feature = "rust1", since = "1.0.0")] -#[cfg(not(no_fp_fmt_parse))] -pub use dec2flt::ParseFloatError; +#[unstable(feature = "complex_numbers", issue = "154023")] +pub use complex::Complex; #[stable(feature = "int_error_matching", since = "1.55.0")] pub use error::IntErrorKind; #[stable(feature = "rust1", since = "1.0.0")] pub use error::ParseIntError; #[stable(feature = "try_from", since = "1.34.0")] pub use error::TryFromIntError; +#[stable(feature = "rust1", since = "1.0.0")] +#[cfg(not(no_fp_fmt_parse))] +pub use float_parse::ParseFloatError; #[stable(feature = "generic_nonzero", since = "1.79.0")] pub use nonzero::NonZero; #[unstable( @@ -248,6 +248,137 @@ macro_rules! midpoint_impl { }; } +macro_rules! widening_mul_impl { + ($SelfT:ty, $WideT:ty) => { + /// Widening multiplication. Computes `self * rhs`, widening to a larger integer. + /// + /// The returned value is always exact and can never overflow. + /// + /// Note that this method is semantically equivalent to [`carrying_mul`] with a + /// carry of zero, with the latter instead returning a tuple denoting the low and + /// high parts of the result. Consider using it instead if you need + /// interoperability with other big int helper functions, or if this method isn't + /// available for a given type. + /// + /// [`carrying_mul`]: Self::carrying_mul + /// + /// # Examples + /// + /// ``` + /// #![feature(widening_mul)] + /// + #[doc = concat!("assert_eq!(", stringify!($SelfT), "::MAX.widening_mul(0_", stringify!($SelfT), "), 0);")] + #[doc = concat!("assert_eq!(", stringify!($SelfT), "::MAX.widening_mul(", stringify!($SelfT), "::MAX), ", stringify!($SelfT), "::MAX as ", stringify!($WideT), " * ", stringify!($SelfT), "::MAX as ", stringify!($WideT), ");")] + /// ``` + #[unstable(feature = "widening_mul", issue = "152016")] + #[rustc_const_unstable(feature = "widening_mul", issue = "152016")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline] + pub const fn widening_mul(self, rhs: Self) -> $WideT { + self as $WideT * rhs as $WideT + } + } +} + +macro_rules! widening_carryless_mul_impl { + ($SelfT:ty, $WideT:ty) => { + /// Performs a widening carry-less multiplication. + /// + /// # Examples + /// + /// ``` + /// #![feature(uint_carryless_mul)] + /// + #[doc = concat!("assert_eq!(", stringify!($SelfT), "::MAX.widening_carryless_mul(", + stringify!($SelfT), "::MAX), ", stringify!($WideT), "::MAX / 3);")] + /// ``` + #[rustc_const_unstable(feature = "uint_carryless_mul", issue = "152080")] + #[doc(alias = "clmul")] + #[unstable(feature = "uint_carryless_mul", issue = "152080")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline] + pub const fn widening_carryless_mul(self, rhs: $SelfT) -> $WideT { + (self as $WideT).carryless_mul(rhs as $WideT) + } + } +} + +macro_rules! carrying_carryless_mul_impl { + (u128, u256) => { + carrying_carryless_mul_impl! { @internal u128 => + pub const fn carrying_carryless_mul(self, rhs: Self, carry: Self) -> (Self, Self) { + let x0 = self as u64; + let x1 = (self >> 64) as u64; + let y0 = rhs as u64; + let y1 = (rhs >> 64) as u64; + + let z0 = u64::widening_carryless_mul(x0, y0); + let z2 = u64::widening_carryless_mul(x1, y1); + + // The grade school algorithm would compute: + // z1 = x0y1 ^ x1y0 + + // Instead, Karatsuba first computes: + let z3 = u64::widening_carryless_mul(x0 ^ x1, y0 ^ y1); + // Since it distributes over XOR, + // z3 == x0y0 ^ x0y1 ^ x1y0 ^ x1y1 + // |--| |---------| |--| + // == z0 ^ z1 ^ z2 + // so we can compute z1 as + let z1 = z3 ^ z0 ^ z2; + + let lo = z0 ^ (z1 << 64); + let hi = z2 ^ (z1 >> 64); + + (lo ^ carry, hi) + } + } + }; + ($SelfT:ty, $WideT:ty) => { + carrying_carryless_mul_impl! { @internal $SelfT => + pub const fn carrying_carryless_mul(self, rhs: Self, carry: Self) -> (Self, Self) { + // Can't use widening_carryless_mul because it's not implemented for usize. + let p = (self as $WideT).carryless_mul(rhs as $WideT); + + let lo = (p as $SelfT); + let hi = (p >> Self::BITS) as $SelfT; + + (lo ^ carry, hi) + } + } + }; + (@internal $SelfT:ty => $($fn:tt)*) => { + /// Calculates the "full carryless multiplication" without the possibility to overflow. + /// + /// This returns the low-order (wrapping) bits and the high-order (overflow) bits + /// of the result as two separate values, in that order. + /// + /// # Examples + /// + /// Please note that this example is shared among integer types, which is why `u8` is used. + /// + /// ``` + /// #![feature(uint_carryless_mul)] + /// + /// assert_eq!(0b1000_0000u8.carrying_carryless_mul(0b1000_0000, 0b0000), (0, 0b0100_0000)); + /// assert_eq!(0b1000_0000u8.carrying_carryless_mul(0b1000_0000, 0b1111), (0b1111, 0b0100_0000)); + #[doc = concat!("assert_eq!(", + stringify!($SelfT), "::MAX.carrying_carryless_mul(", stringify!($SelfT), "::MAX, ", stringify!($SelfT), "::MAX), ", + "(!(", stringify!($SelfT), "::MAX / 3), ", stringify!($SelfT), "::MAX / 3));" + )] + /// ``` + #[rustc_const_unstable(feature = "uint_carryless_mul", issue = "152080")] + #[doc(alias = "clmul")] + #[unstable(feature = "uint_carryless_mul", issue = "152080")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline] + $($fn)* + } +} + impl i8 { int_impl! { Self = i8, @@ -258,11 +389,11 @@ impl i8 { Min = -128, Max = 127, rot = 2, - rot_op = "-0x7e", - rot_result = "0xa", - swap_op = "0x12", - swapped = "0x12", - reversed = "0x48", + rot_op = "-0x7e", + rot_result = "0x0a", + swap_op = "0x12", + swapped = "0x12", + reversed = "0x48", le_bytes = "[0x12]", be_bytes = "[0x12]", to_xe_bytes_doc = i8_xe_bytes_doc!(), @@ -270,6 +401,7 @@ impl i8 { bound_condition = "", } midpoint_impl! { i8, i16, signed } + widening_mul_impl! { i8, i16 } } impl i16 { @@ -282,11 +414,11 @@ impl i16 { Min = -32768, Max = 32767, rot = 4, - rot_op = "-0x5ffd", - rot_result = "0x3a", - swap_op = "0x1234", - swapped = "0x3412", - reversed = "0x2c48", + rot_op = "-0x5ffd", + rot_result = "0x003a", + swap_op = "0x1234", + swapped = "0x3412", + reversed = "0x2c48", le_bytes = "[0x34, 0x12]", be_bytes = "[0x12, 0x34]", to_xe_bytes_doc = "", @@ -294,6 +426,7 @@ impl i16 { bound_condition = "", } midpoint_impl! { i16, i32, signed } + widening_mul_impl! { i16, i32 } } impl i32 { @@ -306,11 +439,11 @@ impl i32 { Min = -2147483648, Max = 2147483647, rot = 8, - rot_op = "0x10000b3", - rot_result = "0xb301", - swap_op = "0x12345678", - swapped = "0x78563412", - reversed = "0x1e6a2c48", + rot_op = "0x010000b3", + rot_result = "0x0000b301", + swap_op = "0x12345678", + swapped = "0x78563412", + reversed = "0x1e6a2c48", le_bytes = "[0x78, 0x56, 0x34, 0x12]", be_bytes = "[0x12, 0x34, 0x56, 0x78]", to_xe_bytes_doc = "", @@ -318,6 +451,7 @@ impl i32 { bound_condition = "", } midpoint_impl! { i32, i64, signed } + widening_mul_impl! { i32, i64 } } impl i64 { @@ -330,11 +464,11 @@ impl i64 { Min = -9223372036854775808, Max = 9223372036854775807, rot = 12, - rot_op = "0xaa00000000006e1", - rot_result = "0x6e10aa", - swap_op = "0x1234567890123456", - swapped = "0x5634129078563412", - reversed = "0x6a2c48091e6a2c48", + rot_op = "0x0aa00000000006e1", + rot_result = "0x00000000006e10aa", + swap_op = "0x1234567890123456", + swapped = "0x5634129078563412", + reversed = "0x6a2c48091e6a2c48", le_bytes = "[0x56, 0x34, 0x12, 0x90, 0x78, 0x56, 0x34, 0x12]", be_bytes = "[0x12, 0x34, 0x56, 0x78, 0x90, 0x12, 0x34, 0x56]", to_xe_bytes_doc = "", @@ -342,6 +476,7 @@ impl i64 { bound_condition = "", } midpoint_impl! { i64, signed } + widening_mul_impl! { i64, i128 } } impl i128 { @@ -354,11 +489,11 @@ impl i128 { Min = -170141183460469231731687303715884105728, Max = 170141183460469231731687303715884105727, rot = 16, - rot_op = "0x13f40000000000000000000000004f76", - rot_result = "0x4f7613f4", - swap_op = "0x12345678901234567890123456789012", - swapped = "0x12907856341290785634129078563412", - reversed = "0x48091e6a2c48091e6a2c48091e6a2c48", + rot_op = "0x13f40000000000000000000000004f76", + rot_result = "0x0000000000000000000000004f7613f4", + swap_op = "0x12345678901234567890123456789012", + swapped = "0x12907856341290785634129078563412", + reversed = "0x48091e6a2c48091e6a2c48091e6a2c48", le_bytes = "[0x12, 0x90, 0x78, 0x56, 0x34, 0x12, 0x90, 0x78, \ 0x56, 0x34, 0x12, 0x90, 0x78, 0x56, 0x34, 0x12]", be_bytes = "[0x12, 0x34, 0x56, 0x78, 0x90, 0x12, 0x34, 0x56, \ @@ -370,6 +505,7 @@ impl i128 { midpoint_impl! { i128, signed } } +#[doc(auto_cfg = false)] #[cfg(target_pointer_width = "16")] impl isize { int_impl! { @@ -381,11 +517,11 @@ impl isize { Min = -32768, Max = 32767, rot = 4, - rot_op = "-0x5ffd", - rot_result = "0x3a", - swap_op = "0x1234", - swapped = "0x3412", - reversed = "0x2c48", + rot_op = "-0x5ffd", + rot_result = "0x003a", + swap_op = "0x1234", + swapped = "0x3412", + reversed = "0x2c48", le_bytes = "[0x34, 0x12]", be_bytes = "[0x12, 0x34]", to_xe_bytes_doc = usize_isize_to_xe_bytes_doc!(), @@ -395,6 +531,7 @@ impl isize { midpoint_impl! { isize, i32, signed } } +#[doc(auto_cfg = false)] #[cfg(target_pointer_width = "32")] impl isize { int_impl! { @@ -406,11 +543,11 @@ impl isize { Min = -2147483648, Max = 2147483647, rot = 8, - rot_op = "0x10000b3", - rot_result = "0xb301", - swap_op = "0x12345678", - swapped = "0x78563412", - reversed = "0x1e6a2c48", + rot_op = "0x010000b3", + rot_result = "0x0000b301", + swap_op = "0x12345678", + swapped = "0x78563412", + reversed = "0x1e6a2c48", le_bytes = "[0x78, 0x56, 0x34, 0x12]", be_bytes = "[0x12, 0x34, 0x56, 0x78]", to_xe_bytes_doc = usize_isize_to_xe_bytes_doc!(), @@ -420,6 +557,7 @@ impl isize { midpoint_impl! { isize, i64, signed } } +#[doc(auto_cfg = false)] #[cfg(target_pointer_width = "64")] impl isize { int_impl! { @@ -431,11 +569,11 @@ impl isize { Min = -9223372036854775808, Max = 9223372036854775807, rot = 12, - rot_op = "0xaa00000000006e1", - rot_result = "0x6e10aa", - swap_op = "0x1234567890123456", - swapped = "0x5634129078563412", - reversed = "0x6a2c48091e6a2c48", + rot_op = "0x0aa00000000006e1", + rot_result = "0x00000000006e10aa", + swap_op = "0x1234567890123456", + swapped = "0x5634129078563412", + reversed = "0x6a2c48091e6a2c48", le_bytes = "[0x56, 0x34, 0x12, 0x90, 0x78, 0x56, 0x34, 0x12]", be_bytes = "[0x12, 0x34, 0x56, 0x78, 0x90, 0x12, 0x34, 0x56]", to_xe_bytes_doc = usize_isize_to_xe_bytes_doc!(), @@ -457,14 +595,17 @@ impl u8 { BITS_MINUS_ONE = 7, MAX = 255, rot = 2, - rot_op = "0x82", - rot_result = "0xa", - fsh_op = "0x36", - fshl_result = "0x8", - fshr_result = "0x8d", - swap_op = "0x12", - swapped = "0x12", - reversed = "0x48", + rot_op = "0x82", + rot_result = "0x0a", + fsh_op = "0x36", + fshl_result = "0x08", + fshr_result = "0x8d", + clmul_lhs = "0x12", + clmul_rhs = "0x34", + clmul_result = "0x28", + swap_op = "0x12", + swapped = "0x12", + reversed = "0x48", le_bytes = "[0x12]", be_bytes = "[0x12]", to_xe_bytes_doc = u8_xe_bytes_doc!(), @@ -472,6 +613,9 @@ impl u8 { bound_condition = "", } midpoint_impl! { u8, u16, unsigned } + widening_mul_impl! { u8, u16 } + widening_carryless_mul_impl! { u8, u16 } + carrying_carryless_mul_impl! { u8, u16 } /// Checks if the value is within the ASCII range. /// @@ -896,7 +1040,8 @@ impl u8 { matches!(*self, b'0'..=b'9') | matches!(*self, b'A'..=b'F') | matches!(*self, b'a'..=b'f') } - /// Checks if the value is an ASCII punctuation character: + /// Checks if the value is an ASCII punctuation or symbol character + /// (i.e. not alphanumeric, whitespace, or control): /// /// - U+0021 ..= U+002F `! " # $ % & ' ( ) * + , - . /`, or /// - U+003A ..= U+0040 `: ; < = > ? @`, or @@ -937,7 +1082,8 @@ impl u8 { | matches!(*self, b'{'..=b'~') } - /// Checks if the value is an ASCII graphic character: + /// Checks if the value is an ASCII graphic character + /// (i.e. not whitespace or control): /// U+0021 '!' ..= U+007E '~'. /// /// # Examples @@ -975,6 +1121,9 @@ impl u8 { /// U+0020 SPACE, U+0009 HORIZONTAL TAB, U+000A LINE FEED, /// U+000C FORM FEED, or U+000D CARRIAGE RETURN. /// + /// **Warning:** Because the list above excludes U+000B VERTICAL TAB, + /// `b.is_ascii_whitespace()` is **not** equivalent to `char::from(b).is_whitespace()`. + /// /// Rust uses the WhatWG Infra Standard's [definition of ASCII /// whitespace][infra-aw]. There are several other definitions in /// wide use. For instance, [the POSIX locale][pct] includes @@ -988,8 +1137,8 @@ impl u8 { /// before using this function. /// /// [infra-aw]: https://infra.spec.whatwg.org/#ascii-whitespace - /// [pct]: https://pubs.opengroup.org/onlinepubs/9699919799/basedefs/V1_chap07.html#tag_07_03_01 - /// [bfs]: https://pubs.opengroup.org/onlinepubs/9699919799/utilities/V3_chap02.html#tag_18_06_05 + /// [pct]: https://pubs.opengroup.org/onlinepubs/9799919799/basedefs/V1_chap07.html#tag_07_03_01 + /// [bfs]: https://pubs.opengroup.org/onlinepubs/9799919799/utilities/V3_chap02.html#tag_19_06_05 /// /// # Examples /// @@ -1099,14 +1248,17 @@ impl u16 { BITS_MINUS_ONE = 15, MAX = 65535, rot = 4, - rot_op = "0xa003", - rot_result = "0x3a", - fsh_op = "0x2de", - fshl_result = "0x30", - fshr_result = "0x302d", - swap_op = "0x1234", - swapped = "0x3412", - reversed = "0x2c48", + rot_op = "0xa003", + rot_result = "0x003a", + fsh_op = "0x02de", + fshl_result = "0x0030", + fshr_result = "0x302d", + clmul_lhs = "0x9012", + clmul_rhs = "0xcd34", + clmul_result = "0x0928", + swap_op = "0x1234", + swapped = "0x3412", + reversed = "0x2c48", le_bytes = "[0x34, 0x12]", be_bytes = "[0x12, 0x34]", to_xe_bytes_doc = "", @@ -1114,6 +1266,9 @@ impl u16 { bound_condition = "", } midpoint_impl! { u16, u32, unsigned } + widening_mul_impl! { u16, u32 } + widening_carryless_mul_impl! { u16, u32 } + carrying_carryless_mul_impl! { u16, u32 } /// Checks if the value is a Unicode surrogate code point, which are disallowed values for [`char`]. /// @@ -1149,14 +1304,17 @@ impl u32 { BITS_MINUS_ONE = 31, MAX = 4294967295, rot = 8, - rot_op = "0x10000b3", - rot_result = "0xb301", - fsh_op = "0x2fe78e45", - fshl_result = "0xb32f", - fshr_result = "0xb32fe78e", - swap_op = "0x12345678", - swapped = "0x78563412", - reversed = "0x1e6a2c48", + rot_op = "0x010000b3", + rot_result = "0x0000b301", + fsh_op = "0x2fe78e45", + fshl_result = "0x0000b32f", + fshr_result = "0xb32fe78e", + clmul_lhs = "0x56789012", + clmul_rhs = "0xf52ecd34", + clmul_result = "0x9b980928", + swap_op = "0x12345678", + swapped = "0x78563412", + reversed = "0x1e6a2c48", le_bytes = "[0x78, 0x56, 0x34, 0x12]", be_bytes = "[0x12, 0x34, 0x56, 0x78]", to_xe_bytes_doc = "", @@ -1164,6 +1322,9 @@ impl u32 { bound_condition = "", } midpoint_impl! { u32, u64, unsigned } + widening_mul_impl! { u32, u64 } + widening_carryless_mul_impl! { u32, u64 } + carrying_carryless_mul_impl! { u32, u64 } } impl u64 { @@ -1175,14 +1336,17 @@ impl u64 { BITS_MINUS_ONE = 63, MAX = 18446744073709551615, rot = 12, - rot_op = "0xaa00000000006e1", - rot_result = "0x6e10aa", - fsh_op = "0x2fe78e45983acd98", - fshl_result = "0x6e12fe", - fshr_result = "0x6e12fe78e45983ac", - swap_op = "0x1234567890123456", - swapped = "0x5634129078563412", - reversed = "0x6a2c48091e6a2c48", + rot_op = "0x0aa00000000006e1", + rot_result = "0x00000000006e10aa", + fsh_op = "0x2fe78e45983acd98", + fshl_result = "0x00000000006e12fe", + fshr_result = "0x6e12fe78e45983ac", + clmul_lhs = "0x7890123456789012", + clmul_rhs = "0xdd358416f52ecd34", + clmul_result = "0x0a6299579b980928", + swap_op = "0x1234567890123456", + swapped = "0x5634129078563412", + reversed = "0x6a2c48091e6a2c48", le_bytes = "[0x56, 0x34, 0x12, 0x90, 0x78, 0x56, 0x34, 0x12]", be_bytes = "[0x12, 0x34, 0x56, 0x78, 0x90, 0x12, 0x34, 0x56]", to_xe_bytes_doc = "", @@ -1190,6 +1354,9 @@ impl u64 { bound_condition = "", } midpoint_impl! { u64, u128, unsigned } + widening_mul_impl! { u64, u128 } + widening_carryless_mul_impl! { u64, u128 } + carrying_carryless_mul_impl! { u64, u128 } } impl u128 { @@ -1201,14 +1368,17 @@ impl u128 { BITS_MINUS_ONE = 127, MAX = 340282366920938463463374607431768211455, rot = 16, - rot_op = "0x13f40000000000000000000000004f76", - rot_result = "0x4f7613f4", - fsh_op = "0x2fe78e45983acd98039000008736273", - fshl_result = "0x4f7602fe", - fshr_result = "0x4f7602fe78e45983acd9803900000873", - swap_op = "0x12345678901234567890123456789012", - swapped = "0x12907856341290785634129078563412", - reversed = "0x48091e6a2c48091e6a2c48091e6a2c48", + rot_op = "0x13f40000000000000000000000004f76", + rot_result = "0x0000000000000000000000004f7613f4", + fsh_op = "0x02fe78e45983acd98039000008736273", + fshl_result = "0x0000000000000000000000004f7602fe", + fshr_result = "0x4f7602fe78e45983acd9803900000873", + clmul_lhs = "0x12345678901234567890123456789012", + clmul_rhs = "0x4317e40ab4ddcf05dd358416f52ecd34", + clmul_result = "0xb9cf660de35d0c170a6299579b980928", + swap_op = "0x12345678901234567890123456789012", + swapped = "0x12907856341290785634129078563412", + reversed = "0x48091e6a2c48091e6a2c48091e6a2c48", le_bytes = "[0x12, 0x90, 0x78, 0x56, 0x34, 0x12, 0x90, 0x78, \ 0x56, 0x34, 0x12, 0x90, 0x78, 0x56, 0x34, 0x12]", be_bytes = "[0x12, 0x34, 0x56, 0x78, 0x90, 0x12, 0x34, 0x56, \ @@ -1218,8 +1388,10 @@ impl u128 { bound_condition = "", } midpoint_impl! { u128, unsigned } + carrying_carryless_mul_impl! { u128, u256 } } +#[doc(auto_cfg = false)] #[cfg(target_pointer_width = "16")] impl usize { uint_impl! { @@ -1230,14 +1402,17 @@ impl usize { BITS_MINUS_ONE = 15, MAX = 65535, rot = 4, - rot_op = "0xa003", - rot_result = "0x3a", - fsh_op = "0x2fe78e45983acd98039000008736273", - fshl_result = "0x4f7602fe", - fshr_result = "0x4f7602fe78e45983acd9803900000873", - swap_op = "0x1234", - swapped = "0x3412", - reversed = "0x2c48", + rot_op = "0xa003", + rot_result = "0x003a", + fsh_op = "0x02de", + fshl_result = "0x0030", + fshr_result = "0x302d", + clmul_lhs = "0x9012", + clmul_rhs = "0xcd34", + clmul_result = "0x0928", + swap_op = "0x1234", + swapped = "0x3412", + reversed = "0x2c48", le_bytes = "[0x34, 0x12]", be_bytes = "[0x12, 0x34]", to_xe_bytes_doc = usize_isize_to_xe_bytes_doc!(), @@ -1245,8 +1420,10 @@ impl usize { bound_condition = " on 16-bit targets", } midpoint_impl! { usize, u32, unsigned } + carrying_carryless_mul_impl! { usize, u32 } } +#[doc(auto_cfg = false)] #[cfg(target_pointer_width = "32")] impl usize { uint_impl! { @@ -1257,14 +1434,17 @@ impl usize { BITS_MINUS_ONE = 31, MAX = 4294967295, rot = 8, - rot_op = "0x10000b3", - rot_result = "0xb301", - fsh_op = "0x2fe78e45", - fshl_result = "0xb32f", - fshr_result = "0xb32fe78e", - swap_op = "0x12345678", - swapped = "0x78563412", - reversed = "0x1e6a2c48", + rot_op = "0x010000b3", + rot_result = "0x0000b301", + fsh_op = "0x2fe78e45", + fshl_result = "0x0000b32f", + fshr_result = "0xb32fe78e", + clmul_lhs = "0x56789012", + clmul_rhs = "0xf52ecd34", + clmul_result = "0x9b980928", + swap_op = "0x12345678", + swapped = "0x78563412", + reversed = "0x1e6a2c48", le_bytes = "[0x78, 0x56, 0x34, 0x12]", be_bytes = "[0x12, 0x34, 0x56, 0x78]", to_xe_bytes_doc = usize_isize_to_xe_bytes_doc!(), @@ -1272,8 +1452,10 @@ impl usize { bound_condition = " on 32-bit targets", } midpoint_impl! { usize, u64, unsigned } + carrying_carryless_mul_impl! { usize, u64 } } +#[doc(auto_cfg = false)] #[cfg(target_pointer_width = "64")] impl usize { uint_impl! { @@ -1284,14 +1466,17 @@ impl usize { BITS_MINUS_ONE = 63, MAX = 18446744073709551615, rot = 12, - rot_op = "0xaa00000000006e1", - rot_result = "0x6e10aa", - fsh_op = "0x2fe78e45983acd98", - fshl_result = "0x6e12fe", - fshr_result = "0x6e12fe78e45983ac", - swap_op = "0x1234567890123456", - swapped = "0x5634129078563412", - reversed = "0x6a2c48091e6a2c48", + rot_op = "0x0aa00000000006e1", + rot_result = "0x00000000006e10aa", + fsh_op = "0x2fe78e45983acd98", + fshl_result = "0x00000000006e12fe", + fshr_result = "0x6e12fe78e45983ac", + clmul_lhs = "0x7890123456789012", + clmul_rhs = "0xdd358416f52ecd34", + clmul_result = "0xa6299579b980928", + swap_op = "0x1234567890123456", + swapped = "0x5634129078563412", + reversed = "0x6a2c48091e6a2c48", le_bytes = "[0x56, 0x34, 0x12, 0x90, 0x78, 0x56, 0x34, 0x12]", be_bytes = "[0x12, 0x34, 0x56, 0x78, 0x90, 0x12, 0x34, 0x56]", to_xe_bytes_doc = usize_isize_to_xe_bytes_doc!(), @@ -1299,6 +1484,7 @@ impl usize { bound_condition = " on 64-bit targets", } midpoint_impl! { usize, u128, unsigned } + carrying_carryless_mul_impl! { usize, u128 } } impl usize { @@ -1401,10 +1587,10 @@ pub const fn can_not_overflow(radix: u32, is_signed_ty: bool, digits: &[u8]) #[cfg_attr(panic = "immediate-abort", inline)] #[cold] #[track_caller] -const fn from_ascii_radix_panic(radix: u32) -> ! { +const fn from_ascii_bytes_radix_panic(radix: u32) -> ! { const_panic!( - "from_ascii_radix: radix must lie in the range `[2, 36]`", - "from_ascii_radix: radix must lie in the range `[2, 36]` - found {radix}", + "from_ascii_bytes_radix: radix must lie in the range `[2, 36]`", + "from_ascii_bytes_radix: radix must lie in the range `[2, 36]` - found {radix}", radix: u32 = radix, ) } @@ -1413,7 +1599,7 @@ macro_rules! from_str_int_impl { ($signedness:ident $($int_ty:ty)+) => {$( #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] - impl const FromStr for $int_ty { + const impl FromStr for $int_ty { type Err = ParseIntError; /// Parses an integer from a string slice with decimal digits. @@ -1502,7 +1688,7 @@ macro_rules! from_str_int_impl { #[rustc_const_stable(feature = "const_int_from_str", since = "1.82.0")] #[inline] pub const fn from_str_radix(src: &str, radix: u32) -> Result<$int_ty, ParseIntError> { - <$int_ty>::from_ascii_radix(src.as_bytes(), radix) + <$int_ty>::from_ascii_bytes_radix_impl(src.as_bytes(), radix) } /// Parses an integer from an ASCII-byte slice with decimal digits. @@ -1526,18 +1712,22 @@ macro_rules! from_str_int_impl { /// ``` /// #![feature(int_from_ascii)] /// - #[doc = concat!("assert_eq!(", stringify!($int_ty), "::from_ascii(b\"+10\"), Ok(10));")] + #[doc = concat!("assert_eq!(", stringify!($int_ty), "::from_ascii_bytes(b\"+10\"), Ok(10));")] /// ``` /// Trailing space returns error: /// ``` /// # #![feature(int_from_ascii)] /// # - #[doc = concat!("assert!(", stringify!($int_ty), "::from_ascii(b\"1 \").is_err());")] + #[doc = concat!("assert!(", stringify!($int_ty), "::from_ascii_bytes(b\"1 \").is_err());")] /// ``` #[unstable(feature = "int_from_ascii", issue = "134821")] + #[rustc_const_unstable(feature = "const_convert", issue = "143773")] #[inline] - pub const fn from_ascii(src: &[u8]) -> Result<$int_ty, ParseIntError> { - <$int_ty>::from_ascii_radix(src, 10) + pub const fn from_ascii_bytes(src: T) -> Result<$int_ty, ParseIntError> + where + T: [const] AsRef<[u8]> + [const] crate::marker::Destruct + { + <$int_ty>::from_ascii_bytes_radix(src.as_ref(), 10) } /// Parses an integer from an ASCII-byte slice with digits in a given base. @@ -1570,22 +1760,31 @@ macro_rules! from_str_int_impl { /// ``` /// #![feature(int_from_ascii)] /// - #[doc = concat!("assert_eq!(", stringify!($int_ty), "::from_ascii_radix(b\"A\", 16), Ok(10));")] + #[doc = concat!("assert_eq!(", stringify!($int_ty), "::from_ascii_bytes_radix(b\"A\", 16), Ok(10));")] /// ``` /// Trailing space returns error: /// ``` /// # #![feature(int_from_ascii)] /// # - #[doc = concat!("assert!(", stringify!($int_ty), "::from_ascii_radix(b\"1 \", 10).is_err());")] + #[doc = concat!("assert!(", stringify!($int_ty), "::from_ascii_bytes_radix(b\"1 \", 10).is_err());")] /// ``` #[unstable(feature = "int_from_ascii", issue = "134821")] + #[rustc_const_unstable(feature = "const_convert", issue = "143773")] #[inline] - pub const fn from_ascii_radix(src: &[u8], radix: u32) -> Result<$int_ty, ParseIntError> { + pub const fn from_ascii_bytes_radix(src: T, radix: u32) -> Result<$int_ty, ParseIntError> + where + T: [const] AsRef<[u8]> + [const] crate::marker::Destruct + { + <$int_ty>::from_ascii_bytes_radix_impl(src.as_ref(), radix) + } + + #[inline] + pub(super) const fn from_ascii_bytes_radix_impl(src: &[u8], radix: u32) -> Result<$int_ty, ParseIntError> { use self::IntErrorKind::*; use self::ParseIntError as PIE; if 2 > radix || radix > 36 { - from_ascii_radix_panic(radix); + from_ascii_bytes_radix_panic(radix); } if src.is_empty() { @@ -1778,16 +1977,12 @@ mod verify { kani::assume(lhs >= $min && lhs <= $max); kani::assume(rhs >= $min && rhs <= $max); - let (result_low, result_high) = lhs.widening_mul(rhs); + let result = lhs.widening_mul(rhs); // Compute expected result using wider type let expected = (lhs as $wide_type) * (rhs as $wide_type); - let expected_low = expected as $type; - let expected_high = (expected >> <$type>::BITS) as $type; - - assert_eq!(result_low, expected_low); - assert_eq!(result_high, expected_high); + assert_eq!(result, expected); } )+ } diff --git a/library/core/src/num/niche_types.rs b/library/core/src/num/niche_types.rs index 3b39622490620..ca37f3cedfd09 100644 --- a/library/core/src/num/niche_types.rs +++ b/library/core/src/num/niche_types.rs @@ -5,49 +5,37 @@ )] use crate::cmp::Ordering; -use crate::fmt; use crate::hash::{Hash, Hasher}; use crate::marker::StructuralPartialEq; +use crate::{fmt, pattern_type}; macro_rules! define_valid_range_type { ($( $(#[$m:meta])* - $vis:vis struct $name:ident($int:ident as $uint:ident in $low:literal..=$high:literal); + $vis:vis struct $name:ident($int:ident is $pat:pat); )+) => {$( #[cfg_attr(flux, flux::opaque)] #[cfg_attr(flux, flux::refined_by(val: int))] #[cfg_attr(flux, flux::invariant($low <= cast(val) && cast(val) <= $high))] - #[derive(Clone, Copy, Eq)] + #[derive(Clone, Copy)] #[repr(transparent)] - #[rustc_layout_scalar_valid_range_start($low)] - #[rustc_layout_scalar_valid_range_end($high)] $(#[$m])* - $vis struct $name($int); - - const _: () = { - // With the `valid_range` attributes, it's always specified as unsigned - assert!(<$uint>::MIN == 0); - let ulow: $uint = $low; - let uhigh: $uint = $high; - assert!(ulow <= uhigh); - - assert!(size_of::<$int>() == size_of::<$uint>()); - }; - + $vis struct $name(pattern_type!($int is $pat)); impl $name { #[inline] #[cfg_attr(flux, flux::spec(fn (val: $int) -> Option))] pub const fn new(val: $int) -> Option { - if (val as $uint) >= ($low as $uint) && (val as $uint) <= ($high as $uint) { - // SAFETY: just checked the inclusive range - Some(unsafe { $name(val) }) + #[allow(non_contiguous_range_endpoints)] + if let $pat = val { + // SAFETY: just checked that the value matches the pattern + Some(unsafe { $name(crate::mem::transmute(val)) }) } else { None } } /// Constructs an instance of this type from the underlying integer - /// primitive without checking whether its zero. + /// primitive without checking whether its valid. /// /// # Safety /// Immediate language UB if `val` is not within the valid range for this @@ -56,14 +44,14 @@ macro_rules! define_valid_range_type { #[cfg_attr(flux, flux::spec(fn (val: $int{ $low <= cast(val) && cast(val) <= $high }) -> Self[{val:cast(val)}]))] pub const unsafe fn new_unchecked(val: $int) -> Self { // SAFETY: Caller promised that `val` is within the valid range. - unsafe { $name(val) } + unsafe { crate::mem::transmute(val) } } #[inline] #[cfg_attr(flux, flux::spec(fn (self: Self) -> $int[cast(self.val)] ensures $low <= cast(self.val) && cast(self.val) <= $high))] pub const fn as_inner(self) -> $int { - // SAFETY: This is a transparent wrapper, so unwrapping it is sound - // (Not using `.0` due to MCP#807.) + // SAFETY: pattern types are always legal values of their base type + // (Not using `.0` because that has perf regressions.) unsafe { crate::mem::transmute(self) } } } @@ -73,6 +61,8 @@ macro_rules! define_valid_range_type { // by . impl StructuralPartialEq for $name {} + impl Eq for $name {} + impl PartialEq for $name { #[inline] fn eq(&self, other: &Self) -> bool { @@ -110,7 +100,7 @@ macro_rules! define_valid_range_type { } define_valid_range_type! { - pub struct Nanoseconds(u32 as u32 in 0..=999_999_999); + pub struct Nanoseconds(u32 is 0..=999_999_999); } impl Nanoseconds { @@ -119,54 +109,39 @@ impl Nanoseconds { } #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for Nanoseconds { +const impl Default for Nanoseconds { #[inline] fn default() -> Self { Self::ZERO } } -define_valid_range_type! { - pub struct NonZeroU8Inner(u8 as u8 in 1..=0xff); - pub struct NonZeroU16Inner(u16 as u16 in 1..=0xff_ff); - pub struct NonZeroU32Inner(u32 as u32 in 1..=0xffff_ffff); - pub struct NonZeroU64Inner(u64 as u64 in 1..=0xffffffff_ffffffff); - pub struct NonZeroU128Inner(u128 as u128 in 1..=0xffffffffffffffff_ffffffffffffffff); - - pub struct NonZeroI8Inner(i8 as u8 in 1..=0xff); - pub struct NonZeroI16Inner(i16 as u16 in 1..=0xff_ff); - pub struct NonZeroI32Inner(i32 as u32 in 1..=0xffff_ffff); - pub struct NonZeroI64Inner(i64 as u64 in 1..=0xffffffff_ffffffff); - pub struct NonZeroI128Inner(i128 as u128 in 1..=0xffffffffffffffff_ffffffffffffffff); - - pub struct NonZeroCharInner(char as u32 in 1..=0x10ffff); -} +const HALF_USIZE: usize = usize::MAX >> 1; -#[cfg(target_pointer_width = "16")] -define_valid_range_type! { - pub struct UsizeNoHighBit(usize as usize in 0..=0x7fff); - pub struct NonZeroUsizeInner(usize as usize in 1..=0xffff); - pub struct NonZeroIsizeInner(isize as usize in 1..=0xffff); -} -#[cfg(target_pointer_width = "32")] define_valid_range_type! { - pub struct UsizeNoHighBit(usize as usize in 0..=0x7fff_ffff); - pub struct NonZeroUsizeInner(usize as usize in 1..=0xffff_ffff); - pub struct NonZeroIsizeInner(isize as usize in 1..=0xffff_ffff); -} -#[cfg(target_pointer_width = "64")] -define_valid_range_type! { - pub struct UsizeNoHighBit(usize as usize in 0..=0x7fff_ffff_ffff_ffff); - pub struct NonZeroUsizeInner(usize as usize in 1..=0xffff_ffff_ffff_ffff); - pub struct NonZeroIsizeInner(isize as usize in 1..=0xffff_ffff_ffff_ffff); -} + pub struct NonZeroU8Inner(u8 is 1..); + pub struct NonZeroU16Inner(u16 is 1..); + pub struct NonZeroU32Inner(u32 is 1..); + pub struct NonZeroU64Inner(u64 is 1..); + pub struct NonZeroU128Inner(u128 is 1..); -define_valid_range_type! { - pub struct U32NotAllOnes(u32 as u32 in 0..=0xffff_fffe); - pub struct I32NotAllOnes(i32 as u32 in 0..=0xffff_fffe); + pub struct NonZeroI8Inner(i8 is ..0 | 1..); + pub struct NonZeroI16Inner(i16 is ..0 | 1..); + pub struct NonZeroI32Inner(i32 is ..0 | 1..); + pub struct NonZeroI64Inner(i64 is ..0 | 1..); + pub struct NonZeroI128Inner(i128 is ..0 | 1..); + + pub struct UsizeNoHighBit(usize is 0..=HALF_USIZE); + pub struct NonZeroUsizeInner(usize is 1..); + pub struct NonZeroIsizeInner(isize is ..0 | 1..); + + pub struct U32NotAllOnes(u32 is 0..u32::MAX); + pub struct I32NotAllOnes(i32 is ..-1 | 0..); + + pub struct U64NotAllOnes(u64 is 0..u64::MAX); + pub struct I64NotAllOnes(i64 is ..-1 | 0..); - pub struct U64NotAllOnes(u64 as u64 in 0..=0xffff_ffff_ffff_fffe); - pub struct I64NotAllOnes(i64 as u64 in 0..=0xffff_ffff_ffff_fffe); + pub struct NonZeroCharInner(char is '\u{1}' ..= '\u{10ffff}'); } pub trait NotAllOnesHelper { @@ -187,7 +162,7 @@ impl NotAllOnesHelper for i64 { } define_valid_range_type! { - pub struct CodePointInner(u32 as u32 in 0..=0x10ffff); + pub struct CodePointInner(u32 is 0..=0x10ffff); } impl CodePointInner { diff --git a/library/core/src/num/nonzero.rs b/library/core/src/num/nonzero.rs index c6d64117fe510..605cab8d951d9 100644 --- a/library/core/src/num/nonzero.rs +++ b/library/core/src/num/nonzero.rs @@ -9,6 +9,7 @@ use crate::hash::{Hash, Hasher}; #[cfg(kani)] use crate::kani; use crate::marker::{Destruct, Freeze, StructuralPartialEq}; +use crate::num::imp; use crate::ops::{BitOr, BitOrAssign, Div, DivAssign, Neg, Rem, RemAssign}; use crate::panic::{RefUnwindSafe, UnwindSafe}; use crate::str::FromStr; @@ -34,30 +35,14 @@ use crate::{fmt, intrinsics, ptr, ub_checks}; reason = "implementation detail which may disappear or be replaced at any time", issue = "none" )] -pub unsafe trait ZeroablePrimitive: Sized + Copy + private::Sealed { - #[doc(hidden)] +pub impl(self) unsafe trait ZeroablePrimitive: Sized + Copy { + /// A type like `Self` but with a niche that includes zero. type NonZeroInner: Sized + Copy; } macro_rules! impl_zeroable_primitive { ($($NonZeroInner:ident ( $primitive:ty )),+ $(,)?) => { - mod private { - #[unstable( - feature = "nonzero_internals", - reason = "implementation detail which may disappear or be replaced at any time", - issue = "none" - )] - pub trait Sealed {} - } - $( - #[unstable( - feature = "nonzero_internals", - reason = "implementation detail which may disappear or be replaced at any time", - issue = "none" - )] - impl private::Sealed for $primitive {} - #[unstable( feature = "nonzero_internals", reason = "implementation detail which may disappear or be replaced at any time", @@ -101,7 +86,7 @@ impl_zeroable_primitive!( /// /// `NonZero` is guaranteed to have the same layout and bit validity as `T` /// with the exception that the all-zero bit pattern is invalid. -/// `Option>` is guaranteed to be compatible with `T`, including in +/// `Option>` is guaranteed to be ABI-compatible with `T`, including in /// FFI. /// /// Thanks to the [null pointer optimization], `NonZero` and @@ -187,7 +172,8 @@ impl_nonzero_auto_trait!(Unpin); impl_nonzero_auto_trait!(UnwindSafe); #[stable(feature = "nonzero", since = "1.28.0")] -impl Clone for NonZero +#[rustc_const_unstable(feature = "const_clone", issue = "142757")] +const impl Clone for NonZero where T: ZeroablePrimitive, { @@ -205,11 +191,12 @@ impl Copy for NonZero where T: ZeroablePrimitive {} #[doc(hidden)] #[unstable(feature = "trivial_clone", issue = "none")] -unsafe impl TrivialClone for NonZero where T: ZeroablePrimitive {} +#[rustc_const_unstable(feature = "const_clone", issue = "142757")] +const unsafe impl TrivialClone for NonZero where T: ZeroablePrimitive {} #[stable(feature = "nonzero", since = "1.28.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq for NonZero +const impl PartialEq for NonZero where T: ZeroablePrimitive + [const] PartialEq, { @@ -229,11 +216,11 @@ impl StructuralPartialEq for NonZero where T: ZeroablePrimitive + Structur #[stable(feature = "nonzero", since = "1.28.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const Eq for NonZero where T: ZeroablePrimitive + [const] Eq {} +const impl Eq for NonZero where T: ZeroablePrimitive + [const] Eq {} #[stable(feature = "nonzero", since = "1.28.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialOrd for NonZero +const impl PartialOrd for NonZero where T: ZeroablePrimitive + [const] PartialOrd, { @@ -265,7 +252,7 @@ where #[stable(feature = "nonzero", since = "1.28.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const Ord for NonZero +const impl Ord for NonZero where // FIXME(const_hack): the T: ~const Destruct should be inferred from the Self: ~const Destruct. // See https://github.com/rust-lang/rust/issues/144207 @@ -311,7 +298,7 @@ where #[stable(feature = "from_nonzero", since = "1.31.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From> for T +const impl From> for T where T: ZeroablePrimitive, { @@ -324,7 +311,7 @@ where #[stable(feature = "nonzero_bitor", since = "1.45.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const BitOr for NonZero +const impl BitOr for NonZero where T: ZeroablePrimitive + [const] BitOr, { @@ -339,7 +326,7 @@ where #[stable(feature = "nonzero_bitor", since = "1.45.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const BitOr for NonZero +const impl BitOr for NonZero where T: ZeroablePrimitive + [const] BitOr, { @@ -354,7 +341,7 @@ where #[stable(feature = "nonzero_bitor", since = "1.45.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const BitOr> for T +const impl BitOr> for T where T: ZeroablePrimitive + [const] BitOr, { @@ -369,7 +356,7 @@ where #[stable(feature = "nonzero_bitor", since = "1.45.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const BitOrAssign for NonZero +const impl BitOrAssign for NonZero where T: ZeroablePrimitive, Self: [const] BitOr, @@ -382,7 +369,7 @@ where #[stable(feature = "nonzero_bitor", since = "1.45.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const BitOrAssign for NonZero +const impl BitOrAssign for NonZero where T: ZeroablePrimitive, Self: [const] BitOr, @@ -578,7 +565,7 @@ macro_rules! nonzero_integer { /// #[doc = concat!("`", stringify!($Ty), "` is guaranteed to have the same layout and bit validity as `", stringify!($Int), "`")] /// with the exception that `0` is not a valid instance. - #[doc = concat!("`Option<", stringify!($Ty), ">` is guaranteed to be compatible with `", stringify!($Int), "`,")] + #[doc = concat!("`Option<", stringify!($Ty), ">` is guaranteed to be ABI-compatible with `", stringify!($Int), "`,")] /// including in FFI. /// /// Thanks to the [null pointer optimization], @@ -687,8 +674,6 @@ macro_rules! nonzero_integer { /// # Example /// /// ``` - /// #![feature(isolate_most_least_significant_one)] - /// /// # use core::num::NonZero; /// # fn main() { test().unwrap(); } /// # fn test() -> Option<()> { @@ -699,7 +684,8 @@ macro_rules! nonzero_integer { /// # Some(()) /// # } /// ``` - #[unstable(feature = "isolate_most_least_significant_one", issue = "136909")] + #[stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] + #[rustc_const_stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -720,8 +706,6 @@ macro_rules! nonzero_integer { /// # Example /// /// ``` - /// #![feature(isolate_most_least_significant_one)] - /// /// # use core::num::NonZero; /// # fn main() { test().unwrap(); } /// # fn test() -> Option<()> { @@ -732,7 +716,8 @@ macro_rules! nonzero_integer { /// # Some(()) /// # } /// ``` - #[unstable(feature = "isolate_most_least_significant_one", issue = "136909")] + #[stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] + #[rustc_const_stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -747,11 +732,19 @@ macro_rules! nonzero_integer { /// Returns the index of the highest bit set to one in `self`. /// + #[doc = sign_dependent_expr!{ + $signedness ? + if signed { + "" + } + if unsigned { + "Note that this is equivalent to [`ilog2`](Self::ilog2)." + } + }] + /// /// # Examples /// /// ``` - /// #![feature(int_lowest_highest_one)] - /// /// # use core::num::NonZero; /// # fn main() { test().unwrap(); } /// # fn test() -> Option<()> { @@ -761,7 +754,8 @@ macro_rules! nonzero_integer { /// # Some(()) /// # } /// ``` - #[unstable(feature = "int_lowest_highest_one", issue = "145203")] + #[stable(feature = "int_lowest_highest_one", since = "1.97.0")] + #[rustc_const_stable(feature = "int_lowest_highest_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -774,8 +768,6 @@ macro_rules! nonzero_integer { /// # Examples /// /// ``` - /// #![feature(int_lowest_highest_one)] - /// /// # use core::num::NonZero; /// # fn main() { test().unwrap(); } /// # fn test() -> Option<()> { @@ -785,7 +777,8 @@ macro_rules! nonzero_integer { /// # Some(()) /// # } /// ``` - #[unstable(feature = "int_lowest_highest_one", issue = "145203")] + #[stable(feature = "int_lowest_highest_one", since = "1.97.0")] + #[rustc_const_stable(feature = "int_lowest_highest_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -1190,7 +1183,10 @@ macro_rules! nonzero_integer { /// assuming overflow cannot occur. /// Overflow is unchecked, and it is undefined behavior to overflow /// *even if the result would wrap to a non-zero value*. - /// The behavior is undefined as soon as + /// + /// # Safety + /// + /// This results in undefined behavior when #[doc = sign_dependent_expr!{ $signedness ? if signed { @@ -1337,16 +1333,186 @@ macro_rules! nonzero_integer { // So the result cannot be zero. unsafe { Self::new_unchecked(self.get().saturating_pow(other)) } } + + /// Parses a non-zero integer from an ASCII-byte slice with decimal digits. + /// + /// The characters are expected to be an optional + #[doc = sign_dependent_expr!{ + $signedness ? + if signed { + " `+` or `-` " + } + if unsigned { + " `+` " + } + }] + /// sign followed by only digits. Leading and trailing non-digit characters (including + /// whitespace) represent an error. Underscores (which are accepted in Rust literals) + /// also represent an error. + /// + /// # Examples + /// + /// ``` + /// #![feature(int_from_ascii)] + /// + /// # use std::num::NonZero; + /// # + /// # fn main() { test().unwrap(); } + /// # fn test() -> Option<()> { + #[doc = concat!("assert_eq!(NonZero::<", stringify!($Int), ">::from_ascii_bytes(b\"+10\"), Ok(NonZero::new(10)?));")] + /// # Some(()) + /// # } + /// ``` + /// + /// Trailing space returns error: + /// + /// ``` + /// #![feature(int_from_ascii)] + /// + /// # use std::num::NonZero; + /// # + #[doc = concat!("assert!(NonZero::<", stringify!($Int), ">::from_ascii_bytes(b\"1 \").is_err());")] + /// ``` + #[unstable(feature = "int_from_ascii", issue = "134821")] + #[rustc_const_unstable(feature = "const_convert", issue = "143773")] + #[inline] + pub const fn from_ascii_bytes(src: T) -> Result + where + T: [const] AsRef<[u8]> + [const] crate::marker::Destruct + { + Self::from_ascii_bytes_radix_impl(src.as_ref(), 10) + } + + /// Parses a non-zero integer from an ASCII-byte slice with digits in a given base. + /// + /// The characters are expected to be an optional + #[doc = sign_dependent_expr!{ + $signedness ? + if signed { + " `+` or `-` " + } + if unsigned { + " `+` " + } + }] + /// sign followed by only digits. Leading and trailing non-digit characters (including + /// whitespace) represent an error. Underscores (which are accepted in Rust literals) + /// also represent an error. + /// + /// Digits are a subset of these characters, depending on `radix`: + /// + /// - `0-9` + /// - `a-z` + /// - `A-Z` + /// + /// # Panics + /// + /// This method panics if `radix` is not in the range from 2 to 36. + /// + /// # Examples + /// + /// ``` + /// #![feature(int_from_ascii)] + /// + /// # use std::num::NonZero; + /// # + /// # fn main() { test().unwrap(); } + /// # fn test() -> Option<()> { + #[doc = concat!("assert_eq!(NonZero::<", stringify!($Int), ">::from_ascii_bytes_radix(b\"A\", 16), Ok(NonZero::new(10)?));")] + /// # Some(()) + /// # } + /// ``` + /// + /// Trailing space returns error: + /// + /// ``` + /// #![feature(int_from_ascii)] + /// + /// # use std::num::NonZero; + /// # + #[doc = concat!("assert!(NonZero::<", stringify!($Int), ">::from_ascii_bytes_radix(b\"1 \", 10).is_err());")] + /// ``` + #[unstable(feature = "int_from_ascii", issue = "134821")] + #[rustc_const_unstable(feature = "const_convert", issue = "143773")] + #[inline] + pub const fn from_ascii_bytes_radix(src: T, radix: u32) -> Result + where + T: [const] AsRef<[u8]> + [const] crate::marker::Destruct + { + Self::from_ascii_bytes_radix_impl(src.as_ref(), radix) + } + + #[inline] + const fn from_ascii_bytes_radix_impl(src: &[u8], radix: u32) -> Result { + let n = match <$Int>::from_ascii_bytes_radix_impl(src, radix) { + Ok(n) => n, + Err(err) => return Err(err), + }; + if let Some(n) = Self::new(n) { + Ok(n) + } else { + Err(ParseIntError { kind: IntErrorKind::Zero }) + } + } + + /// Parses a non-zero integer from a string slice with digits in a given base. + /// + /// The string is expected to be an optional + #[doc = sign_dependent_expr!{ + $signedness ? + if signed { + " `+` or `-` " + } + if unsigned { + " `+` " + } + }] + /// sign followed by only digits. Leading and trailing non-digit characters (including + /// whitespace) represent an error. Underscores (which are accepted in Rust literals) + /// also represent an error. + /// + /// Digits are a subset of these characters, depending on `radix`: + /// + /// - `0-9` + /// - `a-z` + /// - `A-Z` + /// + /// # Panics + /// + /// This method panics if `radix` is not in the range from 2 to 36. + /// + /// # Examples + /// + /// ``` + /// # use std::num::NonZero; + /// # + /// # fn main() { test().unwrap(); } + /// # fn test() -> Option<()> { + #[doc = concat!("assert_eq!(NonZero::<", stringify!($Int), ">::from_str_radix(\"A\", 16), Ok(NonZero::new(10)?));")] + /// # Some(()) + /// # } + /// ``` + /// + /// Trailing space returns error: + /// + /// ``` + /// # use std::num::NonZero; + /// # + #[doc = concat!("assert!(NonZero::<", stringify!($Int), ">::from_str_radix(\"1 \", 10).is_err());")] + /// ``` + #[stable(feature = "nonzero_from_str_radix", since = "1.98.0")] + #[rustc_const_stable(feature = "nonzero_from_str_radix", since = "1.98.0")] + #[inline] + pub const fn from_str_radix(src: &str, radix: u32) -> Result { + Self::from_ascii_bytes_radix_impl(src.as_bytes(), radix) + } } #[stable(feature = "nonzero_parse", since = "1.35.0")] impl FromStr for NonZero<$Int> { type Err = ParseIntError; fn from_str(src: &str) -> Result { - Self::new(<$Int>::from_str_radix(src, 10)?) - .ok_or(ParseIntError { - kind: IntErrorKind::Zero - }) + Self::from_str_radix(src, 10) } } @@ -1414,7 +1580,7 @@ macro_rules! nonzero_integer_signedness_dependent_impls { (unsigned $Int:ty) => { #[stable(feature = "nonzero_div", since = "1.51.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Div> for $Int { + const impl Div> for $Int { type Output = $Int; /// Same as `self / other.get()`, but because `other` is a `NonZero<_>`, @@ -1433,7 +1599,7 @@ macro_rules! nonzero_integer_signedness_dependent_impls { #[stable(feature = "nonzero_div_assign", since = "1.79.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const DivAssign> for $Int { + const impl DivAssign> for $Int { /// Same as `self /= other.get()`, but because `other` is a `NonZero<_>`, /// there's never a runtime check for division-by-zero. /// @@ -1447,7 +1613,7 @@ macro_rules! nonzero_integer_signedness_dependent_impls { #[stable(feature = "nonzero_div", since = "1.51.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Rem> for $Int { + const impl Rem> for $Int { type Output = $Int; /// This operation satisfies `n % d == n - (n / d) * d`, and cannot panic. @@ -1461,7 +1627,7 @@ macro_rules! nonzero_integer_signedness_dependent_impls { #[stable(feature = "nonzero_div_assign", since = "1.79.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const RemAssign> for $Int { + const impl RemAssign> for $Int { /// This operation satisfies `n % d == n - (n / d) * d`, and cannot panic. #[inline] fn rem_assign(&mut self, other: NonZero<$Int>) { @@ -1502,7 +1668,7 @@ macro_rules! nonzero_integer_signedness_dependent_impls { (signed $Int:ty) => { #[stable(feature = "signed_nonzero_neg", since = "1.71.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Neg for NonZero<$Int> { + const impl Neg for NonZero<$Int> { type Output = Self; #[inline] @@ -1647,7 +1813,10 @@ macro_rules! nonzero_integer_signedness_dependent_methods { /// assuming overflow cannot occur. /// Overflow is unchecked, and it is undefined behavior to overflow /// *even if the result would wrap to a non-zero value*. - /// The behavior is undefined as soon as + /// + /// # Safety + /// + /// This results in undefined behavior when #[doc = concat!("`self + rhs > ", stringify!($Int), "::MAX`.")] /// /// # Examples @@ -1735,6 +1904,8 @@ macro_rules! nonzero_integer_signedness_dependent_methods { /// except that it has no failure cases to worry about /// since this value can never be zero. /// + /// Note that this is equivalent to [`highest_one`](Self::highest_one). + /// /// # Examples /// /// ``` @@ -1783,7 +1954,7 @@ macro_rules! nonzero_integer_signedness_dependent_methods { without modifying the original"] #[inline] pub const fn ilog10(self) -> u32 { - super::int_log10::$Int(self) + imp::int_log10::$Int(self) } /// Calculates the midpoint (average) between `self` and `rhs`. @@ -1925,19 +2096,18 @@ macro_rules! nonzero_integer_signedness_dependent_methods { /// # Examples /// /// ``` - /// #![feature(uint_bit_width)] - /// /// # use core::num::NonZero; /// # /// # fn main() { test().unwrap(); } /// # fn test() -> Option<()> { - #[doc = concat!("assert_eq!(NonZero::<", stringify!($Int), ">::MIN.bit_width(), NonZero::new(1)?);")] + #[doc = concat!("assert_eq!(NonZero::<", stringify!($Int), ">::new(0b1)?.bit_width(), NonZero::new(1)?);")] #[doc = concat!("assert_eq!(NonZero::<", stringify!($Int), ">::new(0b111)?.bit_width(), NonZero::new(3)?);")] #[doc = concat!("assert_eq!(NonZero::<", stringify!($Int), ">::new(0b1110)?.bit_width(), NonZero::new(4)?);")] /// # Some(()) /// # } /// ``` - #[unstable(feature = "uint_bit_width", issue = "142326")] + #[stable(feature = "uint_bit_width", since = "1.97.0")] + #[rustc_const_stable(feature = "uint_bit_width", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] diff --git a/library/core/src/num/saturating.rs b/library/core/src/num/saturating.rs index 42396a7d4faba..459ed533d7420 100644 --- a/library/core/src/num/saturating.rs +++ b/library/core/src/num/saturating.rs @@ -224,7 +224,7 @@ macro_rules! saturating_impl { ($($t:ty)*) => ($( #[stable(feature = "saturating_int_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Add for Saturating<$t> { + const impl Add for Saturating<$t> { type Output = Saturating<$t>; #[inline] @@ -238,7 +238,7 @@ macro_rules! saturating_impl { #[stable(feature = "saturating_int_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const AddAssign for Saturating<$t> { + const impl AddAssign for Saturating<$t> { #[inline] fn add_assign(&mut self, other: Saturating<$t>) { *self = *self + other; @@ -250,7 +250,7 @@ macro_rules! saturating_impl { #[stable(feature = "saturating_int_assign_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const AddAssign<$t> for Saturating<$t> { + const impl AddAssign<$t> for Saturating<$t> { #[inline] fn add_assign(&mut self, other: $t) { *self = *self + Saturating(other); @@ -262,7 +262,7 @@ macro_rules! saturating_impl { #[stable(feature = "saturating_int_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Sub for Saturating<$t> { + const impl Sub for Saturating<$t> { type Output = Saturating<$t>; #[inline] @@ -276,7 +276,7 @@ macro_rules! saturating_impl { #[stable(feature = "saturating_int_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const SubAssign for Saturating<$t> { + const impl SubAssign for Saturating<$t> { #[inline] fn sub_assign(&mut self, other: Saturating<$t>) { *self = *self - other; @@ -288,7 +288,7 @@ macro_rules! saturating_impl { #[stable(feature = "saturating_int_assign_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const SubAssign<$t> for Saturating<$t> { + const impl SubAssign<$t> for Saturating<$t> { #[inline] fn sub_assign(&mut self, other: $t) { *self = *self - Saturating(other); @@ -300,7 +300,7 @@ macro_rules! saturating_impl { #[stable(feature = "saturating_int_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Mul for Saturating<$t> { + const impl Mul for Saturating<$t> { type Output = Saturating<$t>; #[inline] @@ -314,7 +314,7 @@ macro_rules! saturating_impl { #[stable(feature = "saturating_int_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const MulAssign for Saturating<$t> { + const impl MulAssign for Saturating<$t> { #[inline] fn mul_assign(&mut self, other: Saturating<$t>) { *self = *self * other; @@ -326,7 +326,7 @@ macro_rules! saturating_impl { #[stable(feature = "saturating_int_assign_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const MulAssign<$t> for Saturating<$t> { + const impl MulAssign<$t> for Saturating<$t> { #[inline] fn mul_assign(&mut self, other: $t) { *self = *self * Saturating(other); @@ -353,7 +353,7 @@ macro_rules! saturating_impl { /// ``` #[stable(feature = "saturating_int_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Div for Saturating<$t> { + const impl Div for Saturating<$t> { type Output = Saturating<$t>; #[inline] @@ -367,7 +367,7 @@ macro_rules! saturating_impl { #[stable(feature = "saturating_int_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const DivAssign for Saturating<$t> { + const impl DivAssign for Saturating<$t> { #[inline] fn div_assign(&mut self, other: Saturating<$t>) { *self = *self / other; @@ -379,7 +379,7 @@ macro_rules! saturating_impl { #[stable(feature = "saturating_int_assign_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const DivAssign<$t> for Saturating<$t> { + const impl DivAssign<$t> for Saturating<$t> { #[inline] fn div_assign(&mut self, other: $t) { *self = *self / Saturating(other); @@ -391,7 +391,7 @@ macro_rules! saturating_impl { #[stable(feature = "saturating_int_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Rem for Saturating<$t> { + const impl Rem for Saturating<$t> { type Output = Saturating<$t>; #[inline] @@ -405,7 +405,7 @@ macro_rules! saturating_impl { #[stable(feature = "saturating_int_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const RemAssign for Saturating<$t> { + const impl RemAssign for Saturating<$t> { #[inline] fn rem_assign(&mut self, other: Saturating<$t>) { *self = *self % other; @@ -417,7 +417,7 @@ macro_rules! saturating_impl { #[stable(feature = "saturating_int_assign_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const RemAssign<$t> for Saturating<$t> { + const impl RemAssign<$t> for Saturating<$t> { #[inline] fn rem_assign(&mut self, other: $t) { *self = *self % Saturating(other); @@ -429,7 +429,7 @@ macro_rules! saturating_impl { #[stable(feature = "saturating_int_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Not for Saturating<$t> { + const impl Not for Saturating<$t> { type Output = Saturating<$t>; #[inline] @@ -443,7 +443,7 @@ macro_rules! saturating_impl { #[stable(feature = "saturating_int_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitXor for Saturating<$t> { + const impl BitXor for Saturating<$t> { type Output = Saturating<$t>; #[inline] @@ -457,7 +457,7 @@ macro_rules! saturating_impl { #[stable(feature = "saturating_int_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitXorAssign for Saturating<$t> { + const impl BitXorAssign for Saturating<$t> { #[inline] fn bitxor_assign(&mut self, other: Saturating<$t>) { *self = *self ^ other; @@ -469,7 +469,7 @@ macro_rules! saturating_impl { #[stable(feature = "saturating_int_assign_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitXorAssign<$t> for Saturating<$t> { + const impl BitXorAssign<$t> for Saturating<$t> { #[inline] fn bitxor_assign(&mut self, other: $t) { *self = *self ^ Saturating(other); @@ -481,7 +481,7 @@ macro_rules! saturating_impl { #[stable(feature = "saturating_int_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitOr for Saturating<$t> { + const impl BitOr for Saturating<$t> { type Output = Saturating<$t>; #[inline] @@ -495,7 +495,7 @@ macro_rules! saturating_impl { #[stable(feature = "saturating_int_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitOrAssign for Saturating<$t> { + const impl BitOrAssign for Saturating<$t> { #[inline] fn bitor_assign(&mut self, other: Saturating<$t>) { *self = *self | other; @@ -507,7 +507,7 @@ macro_rules! saturating_impl { #[stable(feature = "saturating_int_assign_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitOrAssign<$t> for Saturating<$t> { + const impl BitOrAssign<$t> for Saturating<$t> { #[inline] fn bitor_assign(&mut self, other: $t) { *self = *self | Saturating(other); @@ -519,7 +519,7 @@ macro_rules! saturating_impl { #[stable(feature = "saturating_int_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitAnd for Saturating<$t> { + const impl BitAnd for Saturating<$t> { type Output = Saturating<$t>; #[inline] @@ -533,7 +533,7 @@ macro_rules! saturating_impl { #[stable(feature = "saturating_int_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitAndAssign for Saturating<$t> { + const impl BitAndAssign for Saturating<$t> { #[inline] fn bitand_assign(&mut self, other: Saturating<$t>) { *self = *self & other; @@ -545,7 +545,7 @@ macro_rules! saturating_impl { #[stable(feature = "saturating_int_assign_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitAndAssign<$t> for Saturating<$t> { + const impl BitAndAssign<$t> for Saturating<$t> { #[inline] fn bitand_assign(&mut self, other: $t) { *self = *self & Saturating(other); @@ -1011,7 +1011,7 @@ macro_rules! saturating_int_impl_signed { #[stable(feature = "saturating_int_impl", since = "1.74.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Neg for Saturating<$t> { + const impl Neg for Saturating<$t> { type Output = Self; #[inline] fn neg(self) -> Self { diff --git a/library/core/src/num/shells/legacy_int_modules.rs b/library/core/src/num/shells/legacy_int_modules.rs index 6b4f253911157..cf624ab50afe5 100644 --- a/library/core/src/num/shells/legacy_int_modules.rs +++ b/library/core/src/num/shells/legacy_int_modules.rs @@ -5,8 +5,8 @@ macro_rules! legacy_int_module { ($T:ident, #[$attr:meta]) => ( #[$attr] #[deprecated( - since = "TBD", - note = "all constants in this module replaced by associated constants on the type" + since = "1.99.0", + note = "all constants in this module replaced by associated constants on the type", )] #[rustc_diagnostic_item = concat!(stringify!($T), "_legacy_mod")] pub mod $T { @@ -30,7 +30,7 @@ macro_rules! legacy_int_module { /// ``` /// #[$attr] - #[deprecated(since = "TBD", note = "replaced by the `MIN` associated constant on this type")] + #[deprecated(since = "1.99.0", note = "replaced by the `MIN` associated constant on this type")] #[rustc_diagnostic_item = concat!(stringify!($T), "_legacy_const_min")] pub const MIN: $T = $T::MIN; @@ -50,7 +50,7 @@ macro_rules! legacy_int_module { /// ``` /// #[$attr] - #[deprecated(since = "TBD", note = "replaced by the `MAX` associated constant on this type")] + #[deprecated(since = "1.99.0", note = "replaced by the `MAX` associated constant on this type")] #[rustc_diagnostic_item = concat!(stringify!($T), "_legacy_const_max")] pub const MAX: $T = $T::MAX; } diff --git a/library/core/src/num/traits.rs b/library/core/src/num/traits.rs new file mode 100644 index 0000000000000..8f5daf2345df9 --- /dev/null +++ b/library/core/src/num/traits.rs @@ -0,0 +1,129 @@ +/// Definitions of traits for numeric types +// Implementation based on `num_conv` by jhpratt, under (MIT OR Apache-2.0). + +/// Trait for types that this type can be truncated to +#[unstable(feature = "num_internals", reason = "internal implementation detail", issue = "none")] +#[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] +pub impl(self) const trait TruncateTarget { + #[doc(hidden)] + fn internal_truncate(self) -> Target; + + #[doc(hidden)] + fn internal_saturating_truncate(self) -> Target; + + #[doc(hidden)] + fn internal_checked_truncate(self) -> Option; +} + +/// Trait for types that this type can be widened to +#[unstable(feature = "num_internals", reason = "internal implementation detail", issue = "none")] +#[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] +pub impl(self) const trait WidenTarget { + #[doc(hidden)] + fn internal_widen(self) -> Target; +} + +macro_rules! impl_truncate { + ($($from:ty => $($to:ty),+;)*) => {$($( + const _: () = assert!( + size_of::<$from>() >= size_of::<$to>(), + concat!( + "cannot truncate ", + stringify!($from), + " to ", + stringify!($to), + " because ", + stringify!($from), + " is smaller than ", + stringify!($to) + ) + ); + + #[unstable(feature = "num_internals", reason = "internal implementation detail", issue = "none")] + #[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] + const impl TruncateTarget<$to> for $from { + #[inline] + fn internal_truncate(self) -> $to { + self as _ + } + + #[inline] + fn internal_saturating_truncate(self) -> $to { + if self > <$to>::MAX as Self { + <$to>::MAX + } else if self < <$to>::MIN as Self { + <$to>::MIN + } else { + self as _ + } + } + + #[inline] + fn internal_checked_truncate(self) -> Option<$to> { + if self > <$to>::MAX as Self || self < <$to>::MIN as Self { + None + } else { + Some(self as _) + } + } + } + )+)*}; +} + +macro_rules! impl_widen { + ($($from:ty => $($to:ty),+;)*) => {$($( + const _: () = assert!( + size_of::<$from>() <= size_of::<$to>(), + concat!( + "cannot widen ", + stringify!($from), + " to ", + stringify!($to), + " because ", + stringify!($from), + " is larger than ", + stringify!($to) + ) + ); + + #[unstable(feature = "num_internals", reason = "internal implementation detail", issue = "none")] + #[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] + const impl WidenTarget<$to> for $from { + fn internal_widen(self) -> $to { + self as _ + } + } + )+)*}; +} + +impl_truncate! { + u8 => u8; + u16 => u16, u8; + u32 => u32, u16, u8; + u64 => u64, u32, u16, u8; + u128 => u128, u64, u32, u16, u8; + usize => usize, u16, u8; + + i8 => i8; + i16 => i16, i8; + i32 => i32, i16, i8; + i64 => i64, i32, i16, i8; + i128 => i128, i64, i32, i16, i8; + isize => isize, i16, i8; +} + +impl_widen! { + u8 => u8, u16, u32, u64, u128, usize; + u16 => u16, u32, u64, u128, usize; + u32 => u32, u64, u128; + u64 => u64, u128; + u128 => u128; + usize => usize; + + i8 => i8, i16, i32, i64, i128, isize; + i16 => i16, i32, i64, i128, isize; + i32 => i32, i64, i128; + i64 => i64, i128; + i128 => i128; + isize => isize; +} diff --git a/library/core/src/num/uint_macros.rs b/library/core/src/num/uint_macros.rs index 0ab22d96c7095..ded277c0dbd5f 100644 --- a/library/core/src/num/uint_macros.rs +++ b/library/core/src/num/uint_macros.rs @@ -17,6 +17,9 @@ macro_rules! uint_impl { fsh_op = $fsh_op:literal, fshl_result = $fshl_result:literal, fshr_result = $fshr_result:literal, + clmul_lhs = $clmul_lhs:literal, + clmul_rhs = $clmul_rhs:literal, + clmul_result = $clmul_result:literal, swap_op = $swap_op:literal, swapped = $swapped:literal, reversed = $reversed:literal, @@ -229,14 +232,13 @@ macro_rules! uint_impl { /// # Examples /// /// ``` - /// #![feature(uint_bit_width)] - /// #[doc = concat!("assert_eq!(0_", stringify!($SelfT), ".bit_width(), 0);")] #[doc = concat!("assert_eq!(0b111_", stringify!($SelfT), ".bit_width(), 3);")] #[doc = concat!("assert_eq!(0b1110_", stringify!($SelfT), ".bit_width(), 4);")] #[doc = concat!("assert_eq!(", stringify!($SelfT), "::MAX.bit_width(), ", stringify!($BITS), ");")] /// ``` - #[unstable(feature = "uint_bit_width", issue = "142326")] + #[stable(feature = "uint_bit_width", since = "1.97.0")] + #[rustc_const_stable(feature = "uint_bit_width", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -250,14 +252,13 @@ macro_rules! uint_impl { /// # Examples /// /// ``` - /// #![feature(isolate_most_least_significant_one)] - /// #[doc = concat!("let n: ", stringify!($SelfT), " = 0b_01100100;")] /// /// assert_eq!(n.isolate_highest_one(), 0b_01000000); #[doc = concat!("assert_eq!(0_", stringify!($SelfT), ".isolate_highest_one(), 0);")] /// ``` - #[unstable(feature = "isolate_most_least_significant_one", issue = "136909")] + #[stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] + #[rustc_const_stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -271,14 +272,13 @@ macro_rules! uint_impl { /// # Examples /// /// ``` - /// #![feature(isolate_most_least_significant_one)] - /// #[doc = concat!("let n: ", stringify!($SelfT), " = 0b_01100100;")] /// /// assert_eq!(n.isolate_lowest_one(), 0b_00000100); #[doc = concat!("assert_eq!(0_", stringify!($SelfT), ".isolate_lowest_one(), 0);")] /// ``` - #[unstable(feature = "isolate_most_least_significant_one", issue = "136909")] + #[stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] + #[rustc_const_stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -289,17 +289,18 @@ macro_rules! uint_impl { /// Returns the index of the highest bit set to one in `self`, or `None` /// if `self` is `0`. /// + /// Note that this is equivalent to [`checked_ilog2`](Self::checked_ilog2). + /// /// # Examples /// /// ``` - /// #![feature(int_lowest_highest_one)] - /// #[doc = concat!("assert_eq!(0b0_", stringify!($SelfT), ".highest_one(), None);")] #[doc = concat!("assert_eq!(0b1_", stringify!($SelfT), ".highest_one(), Some(0));")] #[doc = concat!("assert_eq!(0b1_0000_", stringify!($SelfT), ".highest_one(), Some(4));")] #[doc = concat!("assert_eq!(0b1_1111_", stringify!($SelfT), ".highest_one(), Some(4));")] /// ``` - #[unstable(feature = "int_lowest_highest_one", issue = "145203")] + #[stable(feature = "int_lowest_highest_one", since = "1.97.0")] + #[rustc_const_stable(feature = "int_lowest_highest_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -316,14 +317,13 @@ macro_rules! uint_impl { /// # Examples /// /// ``` - /// #![feature(int_lowest_highest_one)] - /// #[doc = concat!("assert_eq!(0b0_", stringify!($SelfT), ".lowest_one(), None);")] #[doc = concat!("assert_eq!(0b1_", stringify!($SelfT), ".lowest_one(), Some(0));")] #[doc = concat!("assert_eq!(0b1_0000_", stringify!($SelfT), ".lowest_one(), Some(4));")] #[doc = concat!("assert_eq!(0b1_1111_", stringify!($SelfT), ".lowest_one(), Some(0));")] /// ``` - #[unstable(feature = "int_lowest_highest_one", issue = "145203")] + #[stable(feature = "int_lowest_highest_one", since = "1.97.0")] + #[rustc_const_stable(feature = "int_lowest_highest_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -355,6 +355,98 @@ macro_rules! uint_impl { self as $SignedT } + /// Saturating conversion of `self` to a signed integer of the same size. + /// + /// The signed integer's maximum value is returned if `self` is larger + /// than the maximum positive value representable by the signed integer. + /// + /// For other kinds of signed integer casts, see + /// [`cast_signed`](Self::cast_signed), + /// [`checked_cast_signed`](Self::checked_cast_signed), + /// or [`strict_cast_signed`](Self::strict_cast_signed). + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_cast_extras)] + #[doc = concat!("let n = ", stringify!($SelfT), "::MAX;")] + /// + #[doc = concat!("assert_eq!(n.saturating_cast_signed(), ", stringify!($SignedT), "::MAX);")] + #[doc = concat!("assert_eq!(64", stringify!($SelfT), ".saturating_cast_signed(), 64", stringify!($SignedT), ");")] + /// ``` + #[rustc_const_unstable(feature = "integer_cast_extras", issue = "154650")] + #[unstable(feature = "integer_cast_extras", issue = "154650")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline(always)] + pub const fn saturating_cast_signed(self) -> $SignedT { + // Clamp to the signed integer max size, which is ActualT::MAX >> 1. + if self <= <$SignedT>::MAX.cast_unsigned() { + self.cast_signed() + } else { + <$SignedT>::MAX + } + } + + /// Checked conversion of `self` to a signed integer of the same size, + /// returning `None` if `self` is larger than the signed integer's + /// maximum value. + /// + /// For other kinds of signed integer casts, see + /// [`cast_signed`](Self::cast_signed), + /// [`saturating_cast_signed`](Self::saturating_cast_signed), + /// or [`strict_cast_signed`](Self::strict_cast_signed). + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_cast_extras)] + #[doc = concat!("let n = ", stringify!($SelfT), "::MAX;")] + /// + #[doc = concat!("assert_eq!(n.checked_cast_signed(), None);")] + #[doc = concat!("assert_eq!(64", stringify!($SelfT), ".checked_cast_signed(), Some(64", stringify!($SignedT), "));")] + /// ``` + #[rustc_const_unstable(feature = "integer_cast_extras", issue = "154650")] + #[unstable(feature = "integer_cast_extras", issue = "154650")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline(always)] + pub const fn checked_cast_signed(self) -> Option<$SignedT> { + if self <= <$SignedT>::MAX.cast_unsigned() { + Some(self.cast_signed()) + } else { + None + } + } + + /// Strict conversion of `self` to a signed integer of the same size, + /// which panics if `self` is larger than the signed integer's maximum + /// value. + /// + /// For other kinds of signed integer casts, see + /// [`cast_signed`](Self::cast_signed), + /// [`checked_cast_signed`](Self::checked_cast_signed), + /// or [`saturating_cast_signed`](Self::saturating_cast_signed). + /// + /// # Examples + /// + /// ```should_panic + /// #![feature(integer_cast_extras)] + #[doc = concat!("let _ = ", stringify!($SelfT), "::MAX.strict_cast_signed();")] + /// ``` + #[rustc_const_unstable(feature = "integer_cast_extras", issue = "154650")] + #[unstable(feature = "integer_cast_extras", issue = "154650")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline] + #[track_caller] + pub const fn strict_cast_signed(self) -> $SignedT { + match self.checked_cast_signed() { + Some(n) => n, + None => imp::overflow_panic::cast_integer(), + } + } + /// Shifts the bits to the left by a specified amount, `n`, /// wrapping the truncated bits to the end of the resulting integer. /// @@ -412,74 +504,224 @@ macro_rules! uint_impl { return intrinsics::rotate_right(self, n); } - /// Performs a left funnel shift (concatenates `self` with `rhs`, with `self` - /// making up the most significant half, then shifts the combined value left - /// by `n`, and most significant half is extracted to produce the result). + /// Performs a left funnel shift. + /// + /// This operation can be thought of as concatenating `self` and `right` into an + /// integer twice the size of + #[doc = concat!("`", stringify!($SelfT) , "`,")] + /// performing a left shift by `n`, and returning the **left half** of the result. /// - /// Please note this isn't the same operation as the `<<` shifting operator or - /// [`rotate_left`](Self::rotate_left), although `a.funnel_shl(a, n)` is *equivalent* - /// to `a.rotate_left(n)`. + /// The name comes from "funneling" a wider integer to a narrower integer. /// /// # Panics /// - /// If `n` is greater than or equal to the number of bits in `self` + /// This function will panic if `n` is greater than or equal to the number of + /// bits in `self`. /// /// # Examples /// - /// Basic usage: + /// ``` + /// #![feature(funnel_shifts)] + /// + #[doc = concat!("let a = ", $rot_op, "_", stringify!($SelfT), ";")] + #[doc = concat!("let b = ", $fsh_op, "_", stringify!($SelfT), ";")] + /// + #[doc = concat!("assert_eq!(a.funnel_shl(b, ", $rot, "), ", $fshl_result, ");")] + /// + /// // Using zeros as the right operand acts as a normal shift left + #[doc = concat!("assert_eq!(a.funnel_shl(0, ", $rot, "), a << ", $rot, ");")] /// + /// // Shifting by 0 returns `self` unchanged + #[doc = concat!("assert_eq!(a.funnel_shl(b, 0), a);")] + /// + /// // Using the same value as the right operand acts as a rotate + #[doc = concat!("assert_eq!(a.funnel_shl(a, ", $rot, "), a.rotate_left(", $rot, "));")] /// ``` + /// + /// Note that while `funnel_shl` can act as a rotate, it does not allow for + /// rotating by an unbounded amount like [`rotate_left`](Self::rotate_left) does: + /// + /// ```should_panic /// #![feature(funnel_shifts)] - #[doc = concat!("let a = ", $rot_op, stringify!($SelfT), ";")] - #[doc = concat!("let b = ", $fsh_op, stringify!($SelfT), ";")] - #[doc = concat!("let m = ", $fshl_result, ";")] /// - #[doc = concat!("assert_eq!(a.funnel_shl(b, ", $rot, "), m);")] + #[doc = concat!("let a = ", stringify!($SelfT), "::MAX;")] + /// // Okay + #[doc = concat!("let _ = a.rotate_left(", stringify!($SelfT), "::BITS);")] + /// // Panics + #[doc = concat!("let _ = a.funnel_shl(a, ", stringify!($SelfT), "::BITS);")] /// ``` #[rustc_const_unstable(feature = "funnel_shifts", issue = "145686")] #[unstable(feature = "funnel_shifts", issue = "145686")] - #[must_use = "this returns the result of the operation, \ - without modifying the original"] + #[must_use = "this returns the result of the operation, without modifying the original"] #[inline(always)] - pub const fn funnel_shl(self, rhs: Self, n: u32) -> Self { + pub const fn funnel_shl(self, right: Self, n: u32) -> Self { assert!(n < Self::BITS, "attempt to funnel shift left with overflow"); // SAFETY: just checked that `shift` is in-range - unsafe { intrinsics::unchecked_funnel_shl(self, rhs, n) } + unsafe { self.unchecked_funnel_shl(right, n) } } - /// Performs a right funnel shift (concatenates `self` and `rhs`, with `self` - /// making up the most significant half, then shifts the combined value right - /// by `n`, and least significant half is extracted to produce the result). + /// Performs a right funnel shift. /// - /// Please note this isn't the same operation as the `>>` shifting operator or - /// [`rotate_right`](Self::rotate_right), although `a.funnel_shr(a, n)` is *equivalent* - /// to `a.rotate_right(n)`. + /// This operation can be thought of as concatenating `self` and `right` into an + /// integer twice the size of + #[doc = concat!("`", stringify!($SelfT) , "`,")] + /// performing a right shift by `n`, and returning the **right half** of the result. + /// + /// The name comes from "funneling" a wider integer to a narrower integer. /// /// # Panics /// - /// If `n` is greater than or equal to the number of bits in `self` + /// This function will panic if `n` is greater than or equal to the number of + /// bits in `self`. /// /// # Examples /// - /// Basic usage: + /// ``` + /// #![feature(funnel_shifts)] + /// + #[doc = concat!("let a = ", $rot_op, "_", stringify!($SelfT), ";")] + #[doc = concat!("let b = ", $fsh_op, "_", stringify!($SelfT), ";")] + /// + #[doc = concat!("assert_eq!(a.funnel_shr(b, ", $rot, "), ", $fshr_result, ");")] /// + /// // Using zeros as the left operand acts as a normal shift right + #[doc = concat!("assert_eq!(0_", stringify!($SelfT), ".funnel_shr(a, ", $rot, "), a >> ", $rot, ");")] + /// + /// // Shifting by 0 returns `right` unchanged + #[doc = concat!("assert_eq!(b.funnel_shr(a, 0), a);")] + /// + /// // Using the same value as the right operand acts as a rotate + #[doc = concat!("assert_eq!(a.funnel_shr(a, ", $rot, "), a.rotate_right(", $rot, "));")] /// ``` + /// + /// Note that while `funnel_shr` can act as a rotate, it does not allow for + /// rotating by an unbounded amount like [`rotate_right`](Self::rotate_right) does: + /// + /// ```should_panic /// #![feature(funnel_shifts)] - #[doc = concat!("let a = ", $rot_op, stringify!($SelfT), ";")] - #[doc = concat!("let b = ", $fsh_op, stringify!($SelfT), ";")] - #[doc = concat!("let m = ", $fshr_result, ";")] /// - #[doc = concat!("assert_eq!(a.funnel_shr(b, ", $rot, "), m);")] + #[doc = concat!("let a = ", stringify!($SelfT), "::MAX;")] + /// // Okay + #[doc = concat!("let _ = a.rotate_right(", stringify!($SelfT), "::BITS);")] + /// // Panics + #[doc = concat!("let _ = a.funnel_shr(a, ", stringify!($SelfT), "::BITS);")] /// ``` #[rustc_const_unstable(feature = "funnel_shifts", issue = "145686")] #[unstable(feature = "funnel_shifts", issue = "145686")] - #[must_use = "this returns the result of the operation, \ - without modifying the original"] + #[must_use = "this returns the result of the operation, without modifying the original"] #[inline(always)] - pub const fn funnel_shr(self, rhs: Self, n: u32) -> Self { + pub const fn funnel_shr(self, right: Self, n: u32) -> Self { assert!(n < Self::BITS, "attempt to funnel shift right with overflow"); // SAFETY: just checked that `shift` is in-range - unsafe { intrinsics::unchecked_funnel_shr(self, rhs, n) } + unsafe { self.unchecked_funnel_shr(right, n) } + } + + /// Unchecked funnel shift left. + /// + /// # Safety + /// + /// This results in undefined behavior if `n` is greater than or equal to + #[doc = concat!("`", stringify!($SelfT) , "::BITS`,")] + /// i.e. when [`funnel_shl`](Self::funnel_shl) would panic. + /// + #[rustc_const_unstable(feature = "funnel_shifts", issue = "145686")] + #[unstable(feature = "funnel_shifts", issue = "145686")] + #[must_use = "this returns the result of the operation, without modifying the original"] + #[inline(always)] + #[track_caller] + pub const unsafe fn unchecked_funnel_shl(self, right: Self, n: u32) -> Self { + assert_unsafe_precondition!( + check_language_ub, + concat!(stringify!($SelfT), "::unchecked_funnel_shl cannot overflow"), + (n: u32 = n) => n < <$ActualT>::BITS, + ); + + // SAFETY: this is guaranteed to be safe by the caller. + unsafe { + intrinsics::unchecked_funnel_shl(self, right, n) + } + } + + /// Unchecked funnel shift right. + /// + /// # Safety + /// + /// This results in undefined behavior if `n` is greater than or equal to + #[doc = concat!("`", stringify!($SelfT) , "::BITS`,")] + /// i.e. when [`funnel_shr`](Self::funnel_shr) would panic. + /// + #[rustc_const_unstable(feature = "funnel_shifts", issue = "145686")] + #[unstable(feature = "funnel_shifts", issue = "145686")] + #[must_use = "this returns the result of the operation, without modifying the original"] + #[inline(always)] + #[track_caller] + pub const unsafe fn unchecked_funnel_shr(self, right: Self, n: u32) -> Self { + assert_unsafe_precondition!( + check_language_ub, + concat!(stringify!($SelfT), "::unchecked_funnel_shr cannot overflow"), + (n: u32 = n) => n < <$ActualT>::BITS, + ); + + // SAFETY: this is guaranteed to be safe by the caller. + unsafe { + intrinsics::unchecked_funnel_shr(self, right, n) + } + } + + /// Performs a carry-less multiplication, returning the lower bits. + /// + /// This operation is similar to long multiplication in base 2, except that exclusive or is + /// used instead of addition. The implementation is equivalent to: + /// + /// ```no_run + #[doc = concat!("pub fn carryless_mul(lhs: ", stringify!($SelfT), ", rhs: ", stringify!($SelfT), ") -> ", stringify!($SelfT), "{")] + /// let mut retval = 0; + #[doc = concat!(" for i in 0..", stringify!($SelfT), "::BITS {")] + /// if (rhs >> i) & 1 != 0 { + /// // long multiplication would use += + /// retval ^= lhs << i; + /// } + /// } + /// retval + /// } + /// ``` + /// + /// The actual implementation is more efficient, and on some platforms lowers directly to a + /// dedicated instruction. + /// + /// # Uses + /// + /// Carryless multiplication can be used to turn a bitmask of quote characters into a + /// bit mask of characters surrounded by quotes: + /// + /// ```no_run + /// r#"abc xxx "foobar" zzz "a"!"#; // input string + /// 0b0000000010000001000001010; // quote_mask + /// 0b0000000001111110000000100; // quote_mask.carryless_mul(!0) & !quote_mask + /// ``` + /// + /// Another use is in cryptography, where carryless multiplication allows for efficient + /// implementations of polynomial multiplication in `GF(2)[X]`, the polynomial ring + /// over `GF(2)`. + /// + /// # Examples + /// + /// ``` + /// #![feature(uint_carryless_mul)] + /// + #[doc = concat!("let a = ", $clmul_lhs, stringify!($SelfT), ";")] + #[doc = concat!("let b = ", $clmul_rhs, stringify!($SelfT), ";")] + /// + #[doc = concat!("assert_eq!(a.carryless_mul(b), ", $clmul_result, ");")] + /// ``` + #[rustc_const_unstable(feature = "uint_carryless_mul", issue = "152080")] + #[doc(alias = "clmul")] + #[unstable(feature = "uint_carryless_mul", issue = "152080")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline(always)] + pub const fn carryless_mul(self, rhs: Self) -> Self { + intrinsics::carryless_mul(self, rhs) } /// Reverses the byte order of the integer. @@ -510,12 +752,13 @@ macro_rules! uint_impl { /// assert_eq!(n.extract_bits(0b0010_0100), 0b0000_0011); /// assert_eq!(n.extract_bits(0xF0), 0b0000_1011); /// ``` + #[doc(alias = "pext")] #[unstable(feature = "uint_gather_scatter_bits", issue = "149069")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline] pub const fn extract_bits(self, mask: Self) -> Self { - crate::num::int_bits::$ActualT::extract_impl(self as $ActualT, mask as $ActualT) as $SelfT + imp::int_bits::$ActualT::extract_impl(self as $ActualT, mask as $ActualT) as $SelfT } /// Returns an integer with the least significant bits of `self` @@ -527,12 +770,13 @@ macro_rules! uint_impl { /// assert_eq!(n.deposit_bits(0b0101_0101), 0b0101_0001); /// assert_eq!(n.deposit_bits(0xF0), 0b1101_0000); /// ``` + #[doc(alias = "pdep")] #[unstable(feature = "uint_gather_scatter_bits", issue = "149069")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline] pub const fn deposit_bits(self, mask: Self) -> Self { - crate::num::int_bits::$ActualT::deposit_impl(self as $ActualT, mask as $ActualT) as $SelfT + imp::int_bits::$ActualT::deposit_impl(self as $ActualT, mask as $ActualT) as $SelfT } /// Reverses the order of bits in the integer. The least significant bit becomes the most significant bit, @@ -577,13 +821,9 @@ macro_rules! uint_impl { #[must_use] #[inline(always)] pub const fn from_be(x: Self) -> Self { - #[cfg(target_endian = "big")] - { - x - } - #[cfg(not(target_endian = "big"))] - { - x.swap_bytes() + cfg_select! { + target_endian = "big" => x, + _ => x.swap_bytes(), } } @@ -608,13 +848,9 @@ macro_rules! uint_impl { #[must_use] #[inline(always)] pub const fn from_le(x: Self) -> Self { - #[cfg(target_endian = "little")] - { - x - } - #[cfg(not(target_endian = "little"))] - { - x.swap_bytes() + cfg_select! { + target_endian = "little" => x, + _ => x.swap_bytes(), } } @@ -640,13 +876,9 @@ macro_rules! uint_impl { without modifying the original"] #[inline(always)] pub const fn to_be(self) -> Self { // or not to be? - #[cfg(target_endian = "big")] - { - self - } - #[cfg(not(target_endian = "big"))] - { - self.swap_bytes() + cfg_select! { + target_endian = "big" => self, + _ => self.swap_bytes(), } } @@ -672,13 +904,9 @@ macro_rules! uint_impl { without modifying the original"] #[inline(always)] pub const fn to_le(self) -> Self { - #[cfg(target_endian = "little")] - { - self - } - #[cfg(not(target_endian = "little"))] - { - self.swap_bytes() + cfg_select! { + target_endian = "little" => self, + _ => self.swap_bytes(), } } @@ -743,7 +971,7 @@ macro_rules! uint_impl { #[track_caller] pub const fn strict_add(self, rhs: Self) -> Self { let (a, b) = self.overflowing_add(rhs); - if b { overflow_panic::add() } else { a } + if b { imp::overflow_panic::add() } else { a } } /// Unchecked integer addition. Computes `self + rhs`, assuming overflow @@ -758,7 +986,7 @@ macro_rules! uint_impl { /// # Safety /// /// This results in undefined behavior when - #[doc = concat!("`self + rhs > ", stringify!($SelfT), "::MAX` or `self + rhs < ", stringify!($SelfT), "::MIN`,")] + #[doc = concat!("`self + rhs > ", stringify!($SelfT), "::MAX`,")] /// i.e. when [`checked_add`] would return `None`. /// /// [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked @@ -840,7 +1068,7 @@ macro_rules! uint_impl { #[track_caller] pub const fn strict_add_signed(self, rhs: $SignedT) -> Self { let (a, b) = self.overflowing_add_signed(rhs); - if b { overflow_panic::add() } else { a } + if b { imp::overflow_panic::add() } else { a } } /// Checked integer subtraction. Computes `self - rhs`, returning @@ -899,7 +1127,7 @@ macro_rules! uint_impl { #[track_caller] pub const fn strict_sub(self, rhs: Self) -> Self { let (a, b) = self.overflowing_sub(rhs); - if b { overflow_panic::sub() } else { a } + if b { imp::overflow_panic::sub() } else { a } } /// Unchecked integer subtraction. Computes `self - rhs`, assuming overflow @@ -939,7 +1167,7 @@ macro_rules! uint_impl { /// # Safety /// /// This results in undefined behavior when - #[doc = concat!("`self - rhs > ", stringify!($SelfT), "::MAX` or `self - rhs < ", stringify!($SelfT), "::MIN`,")] + #[doc = concat!("`self - rhs < ", stringify!($SelfT), "::MIN`,")] /// i.e. when [`checked_sub`] would return `None`. /// /// [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked @@ -1025,7 +1253,7 @@ macro_rules! uint_impl { #[track_caller] pub const fn strict_sub_signed(self, rhs: $SignedT) -> Self { let (a, b) = self.overflowing_sub_signed(rhs); - if b { overflow_panic::sub() } else { a } + if b { imp::overflow_panic::sub() } else { a } } #[doc = concat!( @@ -1134,7 +1362,7 @@ macro_rules! uint_impl { #[track_caller] pub const fn strict_mul(self, rhs: Self) -> Self { let (a, b) = self.overflowing_mul(rhs); - if b { overflow_panic::mul() } else { a } + if b { imp::overflow_panic::mul() } else { a } } /// Unchecked integer multiplication. Computes `self * rhs`, assuming overflow @@ -1149,7 +1377,7 @@ macro_rules! uint_impl { /// # Safety /// /// This results in undefined behavior when - #[doc = concat!("`self * rhs > ", stringify!($SelfT), "::MAX` or `self * rhs < ", stringify!($SelfT), "::MIN`,")] + #[doc = concat!("`self * rhs > ", stringify!($SelfT), "::MAX`,")] /// i.e. when [`checked_mul`] would return `None`. /// /// [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked @@ -1538,8 +1766,8 @@ macro_rules! uint_impl { /// rounded down. /// /// This method might not be optimized owing to implementation details; - /// `ilog2` can produce results more efficiently for base 2, and `ilog10` - /// can produce results more efficiently for base 10. + /// [`ilog2`](Self::ilog2) can produce results more efficiently for base 2, + /// and [`ilog10`](Self::ilog10) can produce results more efficiently for base 10. /// /// # Panics /// @@ -1561,7 +1789,7 @@ macro_rules! uint_impl { if let Some(log) = self.checked_ilog(base) { log } else { - int_log10::panic_for_nonpositive_argument() + imp::int_log10::panic_for_nonpositive_argument() } } @@ -1586,7 +1814,7 @@ macro_rules! uint_impl { if let Some(log) = self.checked_ilog2() { log } else { - int_log10::panic_for_nonpositive_argument() + imp::int_log10::panic_for_nonpositive_argument() } } @@ -1611,7 +1839,7 @@ macro_rules! uint_impl { if let Some(log) = self.checked_ilog10() { log } else { - int_log10::panic_for_nonpositive_argument() + imp::int_log10::panic_for_nonpositive_argument() } } @@ -1628,6 +1856,10 @@ macro_rules! uint_impl { /// /// ``` #[doc = concat!("assert_eq!(5", stringify!($SelfT), ".checked_ilog(5), Some(1));")] + #[doc = concat!("assert_eq!(4", stringify!($SelfT), ".checked_ilog(5), Some(0));")] + #[doc = concat!("assert_eq!(5", stringify!($SelfT), ".checked_ilog(0), None);")] + #[doc = concat!("assert_eq!(5", stringify!($SelfT), ".checked_ilog(1), None);")] + #[doc = concat!("assert_eq!(0", stringify!($SelfT), ".checked_ilog(1), None);")] /// ``` #[stable(feature = "int_log", since = "1.67.0")] #[rustc_const_stable(feature = "int_log", since = "1.67.0")] @@ -1642,9 +1874,14 @@ macro_rules! uint_impl { // applied by the compiler. If you want those specific bases, // use `.checked_ilog2()` or `.checked_ilog10()` directly. if core::intrinsics::is_val_statically_known(base) { - if base == 2 { - return self.checked_ilog2(); - } else if base == 10 { + // change of base: + // if base == 2 ** k, then + // log(base, n) == log(2, n) / k + if base.is_power_of_two() && base > 1 { + let k = base.ilog2(); + return Some(try_opt!(self.checked_ilog2()) / k); + } + if base == 10 { return self.checked_ilog10(); } } @@ -1684,6 +1921,8 @@ macro_rules! uint_impl { /// /// Returns `None` if the number is zero. /// + /// Note that this is equivalent to [`highest_one`](Self::highest_one). + /// /// # Examples /// /// ``` @@ -1773,7 +2012,7 @@ macro_rules! uint_impl { #[track_caller] pub const fn strict_neg(self) -> Self { let (a, b) = self.overflowing_neg(); - if b { overflow_panic::neg() } else { a } + if b { imp::overflow_panic::neg() } else { a } } /// Checked shift left. Computes `self << rhs`, returning `None` @@ -1829,7 +2068,7 @@ macro_rules! uint_impl { #[track_caller] pub const fn strict_shl(self, rhs: u32) -> Self { let (a, b) = self.overflowing_shl(rhs); - if b { overflow_panic::shl() } else { a } + if b { imp::overflow_panic::shl() } else { a } } /// Unchecked shift left. Computes `self << rhs`, assuming that @@ -2016,7 +2255,7 @@ macro_rules! uint_impl { #[track_caller] pub const fn strict_shr(self, rhs: u32) -> Self { let (a, b) = self.overflowing_shr(rhs); - if b { overflow_panic::shr() } else { a } + if b { imp::overflow_panic::shr() } else { a } } /// Unchecked shift right. Computes `self >> rhs`, assuming that @@ -2167,11 +2406,39 @@ macro_rules! uint_impl { without modifying the original"] #[inline] pub const fn checked_pow(self, mut exp: u32) -> Option { + let mut base = self; + let mut acc: Self = 1; + + if intrinsics::is_val_statically_known(base) && base.is_power_of_two() { + // change of base: + // if base == 2 ** k, then + // (2 ** k) ** n + // == 2 ** (k * n) + // == 1 << (k * n) + let k = base.ilog2(); + let shift = try_opt!(k.checked_mul(exp)); + return (1 as Self).checked_shl(shift); + } + if exp == 0 { return Some(1); } - let mut base = self; - let mut acc: Self = 1; + + if intrinsics::is_val_statically_known(exp) { + while exp > 1 { + if (exp & 1) == 1 { + acc = try_opt!(acc.checked_mul(base)); + } + exp /= 2; + base = try_opt!(base.checked_mul(base)); + } + + // since exp!=0, finally the exp must be 1. + // Deal with the final bit of the exponent separately, since + // squaring the base afterwards is not necessary and may cause a + // needless overflow. + return acc.checked_mul(base); + } // Inductive (`acc` starts at 1; `try_opt!` bails on overflow, so // positive × positive stays positive); discharges the nonzero @@ -2218,23 +2485,10 @@ macro_rules! uint_impl { without modifying the original"] #[inline] #[track_caller] - pub const fn strict_pow(self, mut exp: u32) -> Self { - if exp == 0 { - return 1; - } - let mut base = self; - let mut acc: Self = 1; - - loop { - if (exp & 1) == 1 { - acc = acc.strict_mul(base); - // since exp!=0, finally the exp must be 1. - if exp == 1 { - return acc; - } - } - exp /= 2; - base = base.strict_mul(base); + pub const fn strict_pow(self, exp: u32) -> Self { + match self.checked_pow(exp) { + None => imp::overflow_panic::pow(), + Some(a) => a, } } @@ -2627,7 +2881,7 @@ macro_rules! uint_impl { /// /// Beware that, unlike most other `wrapping_*` methods on integers, this /// does *not* give the same result as doing the shift in infinite precision - /// then truncating as needed. The behaviour matches what shift instructions + /// then truncating as needed. Instead, the behaviour of this method matches what shift instructions /// do on many processors, and is what the `<<` operator does when overflow /// checks are disabled, but numerically it's weird. Consider, instead, /// using [`Self::unbounded_shl`] which has nicer behaviour. @@ -2672,7 +2926,7 @@ macro_rules! uint_impl { /// /// Beware that, unlike most other `wrapping_*` methods on integers, this /// does *not* give the same result as doing the shift in infinite precision - /// then truncating as needed. The behaviour matches what shift instructions + /// then truncating as needed. Instead, the behaviour of this method matches what shift instructions /// do on many processors, and is what the `>>` operator does when overflow /// checks are disabled, but numerically it's weird. Consider, instead, /// using [`Self::unbounded_shr`] which has nicer behaviour. @@ -2726,45 +2980,9 @@ macro_rules! uint_impl { #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline] - pub const fn wrapping_pow(self, mut exp: u32) -> Self { - if exp == 0 { - return 1; - } - let mut base = self; - let mut acc: Self = 1; - - if intrinsics::is_val_statically_known(exp) { - #[safety::loop_invariant(exp>=1)] - while exp > 1 { - if (exp & 1) == 1 { - acc = acc.wrapping_mul(base); - } - exp /= 2; - base = base.wrapping_mul(base); - } - - // since exp!=0, finally the exp must be 1. - // Deal with the final bit of the exponent separately, since - // squaring the base afterwards is not necessary. - acc.wrapping_mul(base) - } else { - // This is faster than the above when the exponent is not known - // at compile time. We can't use the same code for the constant - // exponent case because LLVM is currently unable to unroll - // this loop. - #[safety::loop_invariant(true)] - loop { - if (exp & 1) == 1 { - acc = acc.wrapping_mul(base); - // since exp!=0, finally the exp must be 1. - if exp == 1 { - return acc; - } - } - exp /= 2; - base = base.wrapping_mul(base); - } - } + pub const fn wrapping_pow(self, exp: u32) -> Self { + let (a, _) = self.overflowing_pow(exp); + a } /// Calculates `self` + `rhs`. @@ -3011,54 +3229,6 @@ macro_rules! uint_impl { (a as Self, b) } - /// Calculates the complete double-width product `self * rhs`. - /// - /// This returns the low-order (wrapping) bits and the high-order (overflow) bits - /// of the result as two separate values, in that order. As such, - /// `a.widening_mul(b).0` produces the same result as `a.wrapping_mul(b)`. - /// - /// If you also need to add a value and carry to the wide result, then you want - /// [`Self::carrying_mul_add`] instead. - /// - /// If you also need to add a carry to the wide result, then you want - /// [`Self::carrying_mul`] instead. - /// - /// If you just want to know *whether* the multiplication overflowed, then you - /// want [`Self::overflowing_mul`] instead. - /// - /// # Examples - /// - /// ``` - /// #![feature(widening_mul)] - #[doc = concat!("assert_eq!(5_", stringify!($SelfT), ".widening_mul(7), (35, 0));")] - #[doc = concat!("assert_eq!(", stringify!($SelfT), "::MAX.widening_mul(", stringify!($SelfT), "::MAX), (1, ", stringify!($SelfT), "::MAX - 1));")] - /// ``` - /// - /// Compared to other `*_mul` methods: - /// ``` - /// #![feature(widening_mul)] - #[doc = concat!("assert_eq!(", stringify!($SelfT), "::widening_mul(1 << ", stringify!($BITS_MINUS_ONE), ", 6), (0, 3));")] - #[doc = concat!("assert_eq!(", stringify!($SelfT), "::overflowing_mul(1 << ", stringify!($BITS_MINUS_ONE), ", 6), (0, true));")] - #[doc = concat!("assert_eq!(", stringify!($SelfT), "::wrapping_mul(1 << ", stringify!($BITS_MINUS_ONE), ", 6), 0);")] - #[doc = concat!("assert_eq!(", stringify!($SelfT), "::checked_mul(1 << ", stringify!($BITS_MINUS_ONE), ", 6), None);")] - /// ``` - /// - /// Please note that this example is shared among integer types, which is why `u32` is used. - /// - /// ``` - /// #![feature(widening_mul)] - /// assert_eq!(5u32.widening_mul(2), (10, 0)); - /// assert_eq!(1_000_000_000u32.widening_mul(10), (1410065408, 2)); - /// ``` - #[unstable(feature = "widening_mul", issue = "152016")] - #[rustc_const_unstable(feature = "widening_mul", issue = "152016")] - #[must_use = "this returns the result of the operation, \ - without modifying the original"] - #[inline] - pub const fn widening_mul(self, rhs: Self) -> (Self, Self) { - Self::carrying_mul_add(self, rhs, 0, 0) - } - /// Calculates the "full multiplication" `self * rhs + carry` /// without the possibility to overflow. /// @@ -3090,7 +3260,6 @@ macro_rules! uint_impl { /// implementing it for wider-than-native types. /// /// ``` - /// #![feature(const_unsigned_bigint_helpers)] /// fn scalar_mul_eq(little_endian_digits: &mut Vec, multiplicand: u16) { /// let mut carry = 0; /// for d in little_endian_digits.iter_mut() { @@ -3115,6 +3284,7 @@ macro_rules! uint_impl { /// except that it gives the value of the overflow instead of just whether one happened: /// /// ``` + /// # #![allow(unused_features)] /// #![feature(const_unsigned_bigint_helpers)] /// let r = u8::carrying_mul(7, 13, 0); /// assert_eq!((r.0, r.1 != 0), u8::overflowing_mul(7, 13)); @@ -3127,6 +3297,7 @@ macro_rules! uint_impl { /// [`wrapping_add`](Self::wrapping_add) methods: /// /// ``` + /// # #![allow(unused_features)] /// #![feature(const_unsigned_bigint_helpers)] /// assert_eq!( /// 789_u16.carrying_mul(456, 123).0, @@ -3405,31 +3576,61 @@ macro_rules! uint_impl { without modifying the original"] #[inline] pub const fn overflowing_pow(self, mut exp: u32) -> (Self, bool) { - if exp == 0{ - return (1,false); - } let mut base = self; let mut acc: Self = 1; - let mut overflown = false; - // Scratch space for storing results of overflowing_mul. - let mut r; + let mut overflow = false; + let mut tmp_overflow; + + if intrinsics::is_val_statically_known(base) && base.is_power_of_two() { + // change of base: + // if base == 2 ** k, then + // (2 ** k) ** n + // == 2 ** (k * n) + // == 1 << (k * n) + let k = base.ilog2(); + let Some(shift) = k.checked_mul(exp) else { + return (0, true) + }; + return ((1 as Self).unbounded_shl(shift), shift >= Self::BITS) + } + + if exp == 0 { + return (1, false); + } + + if intrinsics::is_val_statically_known(exp) { + while exp > 1 { + if (exp & 1) == 1 { + (acc, tmp_overflow) = acc.overflowing_mul(base); + overflow |= tmp_overflow; + } + exp /= 2; + (base, tmp_overflow) = base.overflowing_mul(base); + overflow |= tmp_overflow; + } + + // since exp!=0, finally the exp must be 1. + // Deal with the final bit of the exponent separately, since + // squaring the base afterwards is not necessary and may cause a + // needless overflow. + (acc, tmp_overflow) = acc.overflowing_mul(base); + overflow |= tmp_overflow; + return (acc, overflow); + } #[safety::loop_invariant(true)] loop { if (exp & 1) == 1 { - r = acc.overflowing_mul(base); + (acc, tmp_overflow) = acc.overflowing_mul(base); + overflow |= tmp_overflow; // since exp!=0, finally the exp must be 1. if exp == 1 { - r.1 |= overflown; - return r; + return (acc, overflow); } - acc = r.0; - overflown |= r.1; } exp /= 2; - r = base.overflowing_mul(base); - base = r.0; - overflown |= r.1; + (base, tmp_overflow) = base.overflowing_mul(base); + overflow |= tmp_overflow; } } @@ -3447,43 +3648,11 @@ macro_rules! uint_impl { without modifying the original"] #[inline] #[rustc_inherit_overflow_checks] - pub const fn pow(self, mut exp: u32) -> Self { - if exp == 0 { - return 1; - } - let mut base = self; - let mut acc = 1; - - if intrinsics::is_val_statically_known(exp) { - while exp > 1 { - if (exp & 1) == 1 { - acc = acc * base; - } - exp /= 2; - base = base * base; - } - - // since exp!=0, finally the exp must be 1. - // Deal with the final bit of the exponent separately, since - // squaring the base afterwards is not necessary and may cause a - // needless overflow. - acc * base + pub const fn pow(self, exp: u32) -> Self { + if intrinsics::overflow_checks() { + self.strict_pow(exp) } else { - // This is faster than the above when the exponent is not known - // at compile time. We can't use the same code for the constant - // exponent case because LLVM is currently unable to unroll - // this loop. - loop { - if (exp & 1) == 1 { - acc = acc * base; - // since exp!=0, finally the exp must be 1. - if exp == 1 { - return acc; - } - } - exp /= 2; - base = base * base; - } + self.wrapping_pow(exp) } } @@ -3500,7 +3669,7 @@ macro_rules! uint_impl { without modifying the original"] #[inline] pub const fn isqrt(self) -> Self { - let result = crate::num::int_sqrt::$ActualT(self as $ActualT) as $SelfT; + let result = imp::int_sqrt::$ActualT(self as $ActualT) as Self; // Inform the optimizer what the range of outputs is. If testing // `core` crashes with no panic message and a `num::int_sqrt::u*` @@ -3511,10 +3680,29 @@ macro_rules! uint_impl { // function, which means that increasing the input will never // cause the output to decrease. Thus, since the input for unsigned // integers is bounded by `[0, <$ActualT>::MAX]`, sqrt(n) will be - // bounded by `[sqrt(0), sqrt(<$ActualT>::MAX)]`. + // bounded by `[sqrt(0), sqrt(<$ActualT>::MAX)]` and bounding the + // input by `[1, <$ActualT>::MAX]` bounds sqrt(n) by + // `[sqrt(1), sqrt(<$ActualT>::MAX)]`. unsafe { - const MAX_RESULT: $SelfT = crate::num::int_sqrt::$ActualT(<$ActualT>::MAX) as $SelfT; - crate::hint::assert_unchecked(result <= MAX_RESULT); + const MAX_RESULT: $SelfT = imp::int_sqrt::$ActualT(<$ActualT>::MAX) as $SelfT; + crate::hint::assert_unchecked(result <= MAX_RESULT) + } + + if self >= 1 { + // SAFETY: The above statements about monotonicity also apply here. + // Since the input in this branch is bounded by `[1, <$ActualT>::MAX]`, + // sqrt(n) is bounded by `[sqrt(1), sqrt(<$ActualT>::MAX)]`, and + // `sqrt(1) == 1`. + unsafe { crate::hint::assert_unchecked(result >= 1) } + } + + // SAFETY: the isqrt implementation returns the square root and rounds down, + // meaning `result * result <= self`. This implies `result <= self`. + // The compiler needs both to optimize for both. + // `result * result <= self` implies the multiplication will not overflow. + unsafe { + crate::hint::assert_unchecked(result.unchecked_mul(result) <= self); + crate::hint::assert_unchecked(result <= self); } result @@ -3997,7 +4185,7 @@ macro_rules! uint_impl { #[rustc_promotable] #[inline(always)] #[rustc_const_stable(feature = "const_max_value", since = "1.32.0")] - #[deprecated(since = "TBD", note = "replaced by the `MIN` associated constant on this type")] + #[deprecated(since = "1.99.0", note = "replaced by the `MIN` associated constant on this type")] #[rustc_diagnostic_item = concat!(stringify!($SelfT), "_legacy_fn_min_value")] pub const fn min_value() -> Self { Self::MIN } @@ -4009,8 +4197,201 @@ macro_rules! uint_impl { #[rustc_promotable] #[inline(always)] #[rustc_const_stable(feature = "const_max_value", since = "1.32.0")] - #[deprecated(since = "TBD", note = "replaced by the `MAX` associated constant on this type")] + #[deprecated(since = "1.99.0", note = "replaced by the `MAX` associated constant on this type")] #[rustc_diagnostic_item = concat!(stringify!($SelfT), "_legacy_fn_max_value")] pub const fn max_value() -> Self { Self::MAX } + + /// Truncate an integer to an integer of the same size or smaller, preserving the least + /// significant bits. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_widen_truncate)] + #[doc = concat!("assert_eq!(120u8, 120", stringify!($SelfT), ".truncate());")] + /// assert_eq!(120u8, 376u32.truncate()); + /// ``` + #[must_use = "this returns the truncated value and does not modify the original"] + #[unstable(feature = "integer_widen_truncate", issue = "154330")] + #[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] + #[inline] + pub const fn truncate(self) -> Target + where Self: [const] traits::TruncateTarget + { + traits::TruncateTarget::internal_truncate(self) + } + + /// Truncate an integer to an integer of the same size or smaller, saturating at numeric bounds + /// instead of truncating. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_widen_truncate)] + #[doc = concat!("assert_eq!(120u8, 120", stringify!($SelfT), ".saturating_truncate());")] + /// assert_eq!(255u8, 376u32.saturating_truncate()); + /// ``` + #[must_use = "this returns the truncated value and does not modify the original"] + #[unstable(feature = "integer_widen_truncate", issue = "154330")] + #[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] + #[inline] + pub const fn saturating_truncate(self) -> Target + where Self: [const] traits::TruncateTarget + { + traits::TruncateTarget::internal_saturating_truncate(self) + } + + /// Truncate an integer to an integer of the same size or smaller, returning `None` if the value + /// is outside the bounds of the smaller type. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_widen_truncate)] + #[doc = concat!("assert_eq!(Some(120u8), 120", stringify!($SelfT), ".checked_truncate());")] + /// assert_eq!(None, 376u32.checked_truncate::()); + /// ``` + #[must_use = "this returns the truncated value and does not modify the original"] + #[unstable(feature = "integer_widen_truncate", issue = "154330")] + #[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] + #[inline] + pub const fn checked_truncate(self) -> Option + where Self: [const] traits::TruncateTarget + { + traits::TruncateTarget::internal_checked_truncate(self) + } + + /// Widen to an integer of the same size or larger, preserving its value. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_widen_truncate)] + #[doc = concat!("assert_eq!(120u128, 120u8.widen());")] + /// ``` + #[must_use = "this returns the widened value and does not modify the original"] + #[unstable(feature = "integer_widen_truncate", issue = "154330")] + #[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] + #[inline] + pub const fn widen(self) -> Target + where Self: [const] traits::WidenTarget + { + traits::WidenTarget::internal_widen(self) + } + + /// Converts `self` to the target integer type, saturating at the numeric + /// bounds instead of overflowing. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_casts)] + #[doc = concat!("assert_eq!(255u8, ", stringify!($SelfT), "::MAX.saturating_cast());")] + #[doc = concat!("assert_eq!(127i8, ", stringify!($SelfT), "::MAX.saturating_cast());")] + #[doc = concat!("assert_eq!(42i8, 42", stringify!($SelfT), ".saturating_cast());")] + /// ``` + #[must_use = "this returns the cast result and does not modify the original"] + #[unstable(feature = "integer_casts", issue = "157388")] + #[rustc_const_unstable(feature = "integer_casts", issue = "157388")] + #[inline(always)] + pub const fn saturating_cast>(self) -> T { + T::saturating_cast_from(self) + } + + /// Converts `self` to the target integer type, wrapping around at the + /// boundary of the target type. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_casts)] + #[doc = concat!("assert_eq!(255u8, ", stringify!($SelfT), "::MAX.wrapping_cast());")] + #[doc = concat!("assert_eq!(42i8, 42", stringify!($SelfT), ".wrapping_cast());")] + #[doc = concat!("assert_eq!(", stringify!($SelfT), "::MAX as i8, ", stringify!($SelfT), "::MAX.wrapping_cast());")] + /// ``` + #[must_use = "this returns the cast result and does not modify the original"] + #[unstable(feature = "integer_casts", issue = "157388")] + #[rustc_const_unstable(feature = "integer_casts", issue = "157388")] + #[inline(always)] + pub const fn wrapping_cast>(self) -> T { + T::wrapping_cast_from(self) + } + + /// Converts `self` to the target integer type, returning `None` if the value + /// is not representable by the target type. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_casts)] + #[doc = concat!("assert_eq!(Some(42u8), 42", stringify!($SelfT), ".checked_cast());")] + #[doc = concat!("assert_eq!(128", stringify!($SelfT), ".checked_cast::(), None);")] + /// ``` + #[must_use = "this returns the cast result and does not modify the original"] + #[unstable(feature = "integer_casts", issue = "157388")] + #[rustc_const_unstable(feature = "integer_casts", issue = "157388")] + #[inline(always)] + pub const fn checked_cast>(self) -> Option { + T::checked_cast_from(self) + } + + /// Converts `self` to the target integer type, panicking if the value + /// is not representable by the target type. + /// + /// # Panics + /// + /// This function will panic if the value is not representable by the target type. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_casts)] + #[doc = concat!("assert_eq!(42u8, 42", stringify!($SelfT), ".strict_cast());")] + /// ``` + /// + /// The following will panic: + /// + /// ```should_panic + /// #![feature(integer_casts)] + #[doc = concat!("let _ = 128", stringify!($SelfT), ".strict_cast::();")] + /// ``` + #[must_use = "this returns the cast result and does not modify the original"] + #[unstable(feature = "integer_casts", issue = "157388")] + #[rustc_const_unstable(feature = "integer_casts", issue = "157388")] + #[inline(always)] + #[track_caller] + pub const fn strict_cast>(self) -> T { + T::strict_cast_from(self) + } + + /// Converts `self` to the target integer type, assuming the value is + /// representable by the target type. + /// + /// # Safety + /// + /// This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, + /// or smaller than `T::MIN`, where `T` is the target type. + #[must_use = "this returns the cast result and does not modify the original"] + #[unstable(feature = "integer_casts", issue = "157388")] + #[rustc_const_unstable(feature = "integer_casts", issue = "157388")] + #[inline(always)] + pub const unsafe fn unchecked_cast>(self) -> T { + assert_unsafe_precondition!( + check_language_ub, + concat!(stringify!($SelfT), "::unchecked_cast must fit in the target type"), + ( + // Check has to be performed up-front because it depends on generic T. + in_bounds: bool = { + let cast_val = self.checked_cast::(); + let ret = cast_val.is_some(); + core::mem::forget(cast_val); // We don't have const Drop, but we know it's an int. + ret + }, + ) => in_bounds, + ); + + // SAFETY: this is guaranteed to be safe by the caller. + unsafe { T::unchecked_cast_from(self) } + } } } diff --git a/library/core/src/num/wrapping.rs b/library/core/src/num/wrapping.rs index 669785dac2cda..20bb9ad7785b6 100644 --- a/library/core/src/num/wrapping.rs +++ b/library/core/src/num/wrapping.rs @@ -99,7 +99,7 @@ macro_rules! sh_impl_signed { ($t:ident, $f:ident) => { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Shl<$f> for Wrapping<$t> { + const impl Shl<$f> for Wrapping<$t> { type Output = Wrapping<$t>; #[inline] @@ -117,7 +117,7 @@ macro_rules! sh_impl_signed { #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const ShlAssign<$f> for Wrapping<$t> { + const impl ShlAssign<$f> for Wrapping<$t> { #[inline] fn shl_assign(&mut self, other: $f) { *self = *self << other; @@ -129,7 +129,7 @@ macro_rules! sh_impl_signed { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Shr<$f> for Wrapping<$t> { + const impl Shr<$f> for Wrapping<$t> { type Output = Wrapping<$t>; #[inline] @@ -147,7 +147,7 @@ macro_rules! sh_impl_signed { #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const ShrAssign<$f> for Wrapping<$t> { + const impl ShrAssign<$f> for Wrapping<$t> { #[inline] fn shr_assign(&mut self, other: $f) { *self = *self >> other; @@ -163,7 +163,7 @@ macro_rules! sh_impl_unsigned { ($t:ident, $f:ident) => { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Shl<$f> for Wrapping<$t> { + const impl Shl<$f> for Wrapping<$t> { type Output = Wrapping<$t>; #[inline] @@ -177,7 +177,7 @@ macro_rules! sh_impl_unsigned { #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const ShlAssign<$f> for Wrapping<$t> { + const impl ShlAssign<$f> for Wrapping<$t> { #[inline] fn shl_assign(&mut self, other: $f) { *self = *self << other; @@ -189,7 +189,7 @@ macro_rules! sh_impl_unsigned { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Shr<$f> for Wrapping<$t> { + const impl Shr<$f> for Wrapping<$t> { type Output = Wrapping<$t>; #[inline] @@ -203,7 +203,7 @@ macro_rules! sh_impl_unsigned { #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const ShrAssign<$f> for Wrapping<$t> { + const impl ShrAssign<$f> for Wrapping<$t> { #[inline] fn shr_assign(&mut self, other: $f) { *self = *self >> other; @@ -241,7 +241,7 @@ macro_rules! wrapping_impl { ($($t:ty)*) => ($( #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Add for Wrapping<$t> { + const impl Add for Wrapping<$t> { type Output = Wrapping<$t>; #[inline] @@ -255,7 +255,7 @@ macro_rules! wrapping_impl { #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const AddAssign for Wrapping<$t> { + const impl AddAssign for Wrapping<$t> { #[inline] fn add_assign(&mut self, other: Wrapping<$t>) { *self = *self + other; @@ -267,7 +267,7 @@ macro_rules! wrapping_impl { #[stable(feature = "wrapping_int_assign_impl", since = "1.60.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const AddAssign<$t> for Wrapping<$t> { + const impl AddAssign<$t> for Wrapping<$t> { #[inline] fn add_assign(&mut self, other: $t) { *self = *self + Wrapping(other); @@ -279,7 +279,7 @@ macro_rules! wrapping_impl { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Sub for Wrapping<$t> { + const impl Sub for Wrapping<$t> { type Output = Wrapping<$t>; #[inline] @@ -293,7 +293,7 @@ macro_rules! wrapping_impl { #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const SubAssign for Wrapping<$t> { + const impl SubAssign for Wrapping<$t> { #[inline] fn sub_assign(&mut self, other: Wrapping<$t>) { *self = *self - other; @@ -305,7 +305,7 @@ macro_rules! wrapping_impl { #[stable(feature = "wrapping_int_assign_impl", since = "1.60.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const SubAssign<$t> for Wrapping<$t> { + const impl SubAssign<$t> for Wrapping<$t> { #[inline] fn sub_assign(&mut self, other: $t) { *self = *self - Wrapping(other); @@ -317,7 +317,7 @@ macro_rules! wrapping_impl { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Mul for Wrapping<$t> { + const impl Mul for Wrapping<$t> { type Output = Wrapping<$t>; #[inline] @@ -331,7 +331,7 @@ macro_rules! wrapping_impl { #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const MulAssign for Wrapping<$t> { + const impl MulAssign for Wrapping<$t> { #[inline] fn mul_assign(&mut self, other: Wrapping<$t>) { *self = *self * other; @@ -343,7 +343,7 @@ macro_rules! wrapping_impl { #[stable(feature = "wrapping_int_assign_impl", since = "1.60.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const MulAssign<$t> for Wrapping<$t> { + const impl MulAssign<$t> for Wrapping<$t> { #[inline] fn mul_assign(&mut self, other: $t) { *self = *self * Wrapping(other); @@ -355,7 +355,7 @@ macro_rules! wrapping_impl { #[stable(feature = "wrapping_div", since = "1.3.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Div for Wrapping<$t> { + const impl Div for Wrapping<$t> { type Output = Wrapping<$t>; #[inline] @@ -369,7 +369,7 @@ macro_rules! wrapping_impl { #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const DivAssign for Wrapping<$t> { + const impl DivAssign for Wrapping<$t> { #[inline] fn div_assign(&mut self, other: Wrapping<$t>) { *self = *self / other; @@ -381,7 +381,7 @@ macro_rules! wrapping_impl { #[stable(feature = "wrapping_int_assign_impl", since = "1.60.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const DivAssign<$t> for Wrapping<$t> { + const impl DivAssign<$t> for Wrapping<$t> { #[inline] fn div_assign(&mut self, other: $t) { *self = *self / Wrapping(other); @@ -393,7 +393,7 @@ macro_rules! wrapping_impl { #[stable(feature = "wrapping_impls", since = "1.7.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Rem for Wrapping<$t> { + const impl Rem for Wrapping<$t> { type Output = Wrapping<$t>; #[inline] @@ -407,7 +407,7 @@ macro_rules! wrapping_impl { #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const RemAssign for Wrapping<$t> { + const impl RemAssign for Wrapping<$t> { #[inline] fn rem_assign(&mut self, other: Wrapping<$t>) { *self = *self % other; @@ -419,7 +419,7 @@ macro_rules! wrapping_impl { #[stable(feature = "wrapping_int_assign_impl", since = "1.60.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const RemAssign<$t> for Wrapping<$t> { + const impl RemAssign<$t> for Wrapping<$t> { #[inline] fn rem_assign(&mut self, other: $t) { *self = *self % Wrapping(other); @@ -431,7 +431,7 @@ macro_rules! wrapping_impl { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Not for Wrapping<$t> { + const impl Not for Wrapping<$t> { type Output = Wrapping<$t>; #[inline] @@ -445,7 +445,7 @@ macro_rules! wrapping_impl { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitXor for Wrapping<$t> { + const impl BitXor for Wrapping<$t> { type Output = Wrapping<$t>; #[inline] @@ -459,7 +459,7 @@ macro_rules! wrapping_impl { #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitXorAssign for Wrapping<$t> { + const impl BitXorAssign for Wrapping<$t> { #[inline] fn bitxor_assign(&mut self, other: Wrapping<$t>) { *self = *self ^ other; @@ -471,7 +471,7 @@ macro_rules! wrapping_impl { #[stable(feature = "wrapping_int_assign_impl", since = "1.60.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitXorAssign<$t> for Wrapping<$t> { + const impl BitXorAssign<$t> for Wrapping<$t> { #[inline] fn bitxor_assign(&mut self, other: $t) { *self = *self ^ Wrapping(other); @@ -483,7 +483,7 @@ macro_rules! wrapping_impl { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitOr for Wrapping<$t> { + const impl BitOr for Wrapping<$t> { type Output = Wrapping<$t>; #[inline] @@ -497,7 +497,7 @@ macro_rules! wrapping_impl { #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitOrAssign for Wrapping<$t> { + const impl BitOrAssign for Wrapping<$t> { #[inline] fn bitor_assign(&mut self, other: Wrapping<$t>) { *self = *self | other; @@ -509,7 +509,7 @@ macro_rules! wrapping_impl { #[stable(feature = "wrapping_int_assign_impl", since = "1.60.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitOrAssign<$t> for Wrapping<$t> { + const impl BitOrAssign<$t> for Wrapping<$t> { #[inline] fn bitor_assign(&mut self, other: $t) { *self = *self | Wrapping(other); @@ -521,7 +521,7 @@ macro_rules! wrapping_impl { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitAnd for Wrapping<$t> { + const impl BitAnd for Wrapping<$t> { type Output = Wrapping<$t>; #[inline] @@ -535,7 +535,7 @@ macro_rules! wrapping_impl { #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitAndAssign for Wrapping<$t> { + const impl BitAndAssign for Wrapping<$t> { #[inline] fn bitand_assign(&mut self, other: Wrapping<$t>) { *self = *self & other; @@ -547,7 +547,7 @@ macro_rules! wrapping_impl { #[stable(feature = "wrapping_int_assign_impl", since = "1.60.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitAndAssign<$t> for Wrapping<$t> { + const impl BitAndAssign<$t> for Wrapping<$t> { #[inline] fn bitand_assign(&mut self, other: $t) { *self = *self & Wrapping(other); @@ -559,7 +559,7 @@ macro_rules! wrapping_impl { #[stable(feature = "wrapping_neg", since = "1.10.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Neg for Wrapping<$t> { + const impl Neg for Wrapping<$t> { type Output = Self; #[inline] fn neg(self) -> Self { diff --git a/library/core/src/offload.md b/library/core/src/offload.md new file mode 100644 index 0000000000000..985a93a4294fa --- /dev/null +++ b/library/core/src/offload.md @@ -0,0 +1,40 @@ +This module provides support for gpu offloading. For technical details regarding the `offload_kernel` +and `offload!` macros, see their respective documentation. + +## General usage +The `offload_kernel` macro can be applied to a function to generate the necessary code to launch a +kernel on the target device. + +```rust,ignore (optional component) +#[offload_kernel] +fn kernel(x: *mut [f64; 256]) { + // SAFETY: + // calling our `arch` functions and dereferencing a raw pointer is unsafe + unsafe { + let n = (*x).len(); + let i = (thread_idx_x() + block_idx_x() * block_dim_x()) as usize; + if i < n { + (*x)[i] = i as f64; + } + } +} +``` + +To launch an offloaded kernel, use the `offload!` macro. It lets you specify the kernel, the +workgroup and thread dimensions, and the arguments to forward to the device. + +```rust,ignore (optional component) +let mut x = [0.0f64; 256]; +core::offload::offload! { + kernel = kernel, + workgroup_dim = [256, 1, 1], + args = (&mut x as *mut [f64; 256],), +} +``` + +For precise information on the underlying `offload` intrinsic, see its respective documentation. + +## Current limitations: + +- Usage is restricted to types supported by the current device-mapping implementation. +- Functions accepting dyn Trait are not supported. diff --git a/library/core/src/offload/mod.rs b/library/core/src/offload/mod.rs new file mode 100644 index 0000000000000..17ff74f0bbfbb --- /dev/null +++ b/library/core/src/offload/mod.rs @@ -0,0 +1,103 @@ +// offload module +#[unstable(feature = "gpu_offload", issue = "131513")] +pub use crate::macros::builtin::offload_kernel; +#[unstable(feature = "gpu_offload", issue = "131513")] +pub use crate::offload; + +/// Launches a kernel on an offload device (e.g., a GPU). +/// +/// This macro is an interface over the `offload` intrinsic. The kernel itself must be defined +/// using the [`offload_kernel`] macro. +/// +/// The following named arguments are accepted: +/// +/// - `kernel`: The kernel function to offload. Must be a function item. (required) +/// - `args`: A tuple of arguments forwarded to `kernel`. (required) +/// - `workgroup_dim`: A 3D size specifying the number of workgroups to launch. +/// Defaults to `[1, 1, 1]`. +/// - `thread_dim`: A 3D size specifying the number of threads per workgroup. +/// Defaults to `[1, 1, 1]`. +/// - `dyn_cache`: The amount of dynamic shared memory, in bytes, to allocate for the kernel. +/// Defaults to `0`. +/// +/// Each argument may only be specified once. +/// +/// # Examples +/// +/// ```rust,ignore (offload requires a -Z flag) +/// let mut x = [0.0f64; 256]; +/// core::offload::offload! { +/// kernel = kernel, +/// workgroup_dim = [256, 1, 1], +/// args = (&mut x as *mut [f64; 256],), +/// } +/// ``` +#[macro_export] +#[unstable(feature = "gpu_offload", issue = "131513")] +#[allow_internal_unstable(core_intrinsics)] +macro_rules! offload { + ( $($field:ident = $val:expr),* $(,)? ) => { + $crate::offload!(@munch + [ $($field = $val),* ]; + kernel = NONE; + workgroup_dim = ([1, 1, 1]); + thread_dim = ([1, 1, 1]); + dyn_cache = (0); + args = NONE + ) + }; + + (@munch [kernel = $val:expr $(, $rest_f:ident = $rest_v:expr)*]; kernel = NONE; workgroup_dim = $w:tt; thread_dim = $t:tt; dyn_cache = $d:tt; args = $a:tt) => { + $crate::offload!(@munch [$($rest_f = $rest_v),*]; kernel = (SOME $val); workgroup_dim = $w; thread_dim = $t; dyn_cache = $d; args = $a) + }; + (@munch [kernel = $val:expr $(, $rest_f:ident = $rest_v:expr)*]; kernel = (SOME $old:expr); workgroup_dim = $w:tt; thread_dim = $t:tt; dyn_cache = $d:tt; args = $a:tt) => { + compile_error!("duplicate field `kernel`") + }; + (@munch [workgroup_dim = $val:expr $(, $rest_f:ident = $rest_v:expr)*]; kernel = $k:tt; workgroup_dim = ([1, 1, 1]); thread_dim = $t:tt; dyn_cache = $d:tt; args = $a:tt) => { + $crate::offload!(@munch [$($rest_f = $rest_v),*]; kernel = $k; workgroup_dim = (SOME $val); thread_dim = $t; dyn_cache = $d; args = $a) + }; + (@munch [workgroup_dim = $val:expr $(, $rest_f:ident = $rest_v:expr)*]; kernel = $k:tt; workgroup_dim = (SOME $old:expr); thread_dim = $t:tt; dyn_cache = $d:tt; args = $a:tt) => { + compile_error!("duplicate field `workgroup_dim`") + }; + (@munch [thread_dim = $val:expr $(, $rest_f:ident = $rest_v:expr)*]; kernel = $k:tt; workgroup_dim = $w:tt; thread_dim = ([1, 1, 1]); dyn_cache = $d:tt; args = $a:tt) => { + $crate::offload!(@munch [$($rest_f = $rest_v),*]; kernel = $k; workgroup_dim = $w; thread_dim = (SOME $val); dyn_cache = $d; args = $a) + }; + (@munch [thread_dim = $val:expr $(, $rest_f:ident = $rest_v:expr)*]; kernel = $k:tt; workgroup_dim = $w:tt; thread_dim = (SOME $old:expr); dyn_cache = $d:tt; args = $a:tt) => { + compile_error!("duplicate field `thread_dim`") + }; + (@munch [dyn_cache = $val:expr $(, $rest_f:ident = $rest_v:expr)*]; kernel = $k:tt; workgroup_dim = $w:tt; thread_dim = $t:tt; dyn_cache = (0); args = $a:tt) => { + $crate::offload!(@munch [$($rest_f = $rest_v),*]; kernel = $k; workgroup_dim = $w; thread_dim = $t; dyn_cache = (SOME $val); args = $a) + }; + (@munch [dyn_cache = $val:expr $(, $rest_f:ident = $rest_v:expr)*]; kernel = $k:tt; workgroup_dim = $w:tt; thread_dim = $t:tt; dyn_cache = (SOME $old:expr); args = $a:tt) => { + compile_error!("duplicate field `dyn_cache`") + }; + (@munch [args = $val:expr $(, $rest_f:ident = $rest_v:expr)*]; kernel = $k:tt; workgroup_dim = $w:tt; thread_dim = $t:tt; dyn_cache = $d:tt; args = NONE) => { + $crate::offload!(@munch [$($rest_f = $rest_v),*]; kernel = $k; workgroup_dim = $w; thread_dim = $t; dyn_cache = $d; args = (SOME $val)) + }; + (@munch [args = $val:expr $(, $rest_f:ident = $rest_v:expr)*]; kernel = $k:tt; workgroup_dim = $w:tt; thread_dim = $t:tt; dyn_cache = $d:tt; args = (SOME $old:expr)) => { + compile_error!("duplicate field `args`") + }; + + (@munch [$invalid:ident = $val:expr $(, $rest_f:ident = $rest_v:expr)*]; kernel = $k:tt; workgroup_dim = $w:tt; thread_dim = $t:tt; dyn_cache = $d:tt; args = $a:tt) => { + compile_error!(concat!("unknown field `", stringify!($invalid), "`")) + }; + + (@munch []; kernel = NONE; workgroup_dim = $w:tt; thread_dim = $t:tt; dyn_cache = $d:tt; args = $a:tt) => { + compile_error!("missing `kernel`") + }; + (@munch []; kernel = $k:tt; workgroup_dim = $w:tt; thread_dim = $t:tt; dyn_cache = $d:tt; args = NONE) => { + compile_error!("missing `args`") + }; + (@munch []; kernel = (SOME $kernel:expr); workgroup_dim = $w:tt; thread_dim = $t:tt; dyn_cache = $d:tt; args = (SOME $args:expr)) => { + $crate::intrinsics::offload::<_, _, ()>( + $kernel, + $crate::offload!(@value $w), + $crate::offload!(@value $t), + $crate::offload!(@value $d), + $args, + ) + }; + + (@value (SOME $val:expr)) => { $val }; + (@value ($val:expr)) => { $val }; +} diff --git a/library/core/src/ops/arith.rs b/library/core/src/ops/arith.rs index 6c6479c998459..34af7d97acb5a 100644 --- a/library/core/src/ops/arith.rs +++ b/library/core/src/ops/arith.rs @@ -70,8 +70,7 @@ on(all(Self = "{integer}", Rhs = "{float}"), message = "cannot add a float to an integer",), on(all(Self = "{float}", Rhs = "{integer}"), message = "cannot add an integer to a float",), message = "cannot add `{Rhs}` to `{Self}`", - label = "no implementation for `{Self} + {Rhs}`", - append_const_msg + label = "no implementation for `{Self} + {Rhs}`" )] #[doc(alias = "+")] pub const trait Add { @@ -96,7 +95,7 @@ macro_rules! add_impl { ($($t:ty)*) => ($( #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Add for $t { + const impl Add for $t { type Output = $t; #[inline] @@ -181,10 +180,9 @@ add_impl! { usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 f16 f32 f64 f128 #[lang = "sub"] #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -#[rustc_on_unimplemented( +#[diagnostic::on_unimplemented( message = "cannot subtract `{Rhs}` from `{Self}`", - label = "no implementation for `{Self} - {Rhs}`", - append_const_msg + label = "no implementation for `{Self} - {Rhs}`" )] #[doc(alias = "-")] pub const trait Sub { @@ -209,7 +207,7 @@ macro_rules! sub_impl { ($($t:ty)*) => ($( #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Sub for $t { + const impl Sub for $t { type Output = $t; #[inline] @@ -343,7 +341,7 @@ macro_rules! mul_impl { ($($t:ty)*) => ($( #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Mul for $t { + const impl Mul for $t { type Output = $t; #[inline] @@ -487,7 +485,7 @@ macro_rules! div_impl_integer { #[doc = $panic] #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Div for $t { + const impl Div for $t { type Output = $t; #[inline] @@ -510,7 +508,7 @@ macro_rules! div_impl_float { ($($t:ty)*) => ($( #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Div for $t { + const impl Div for $t { type Output = $t; #[inline] @@ -596,7 +594,7 @@ macro_rules! rem_impl_integer { #[doc = $panic] #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Rem for $t { + const impl Rem for $t { type Output = $t; #[inline] @@ -634,7 +632,7 @@ macro_rules! rem_impl_float { /// ``` #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Rem for $t { + const impl Rem for $t { type Output = $t; #[inline] @@ -712,10 +710,11 @@ macro_rules! neg_impl { ($($t:ty)*) => ($( #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Neg for $t { + const impl Neg for $t { type Output = $t; #[inline] + #[track_caller] #[rustc_inherit_overflow_checks] fn neg(self) -> $t { -self } } @@ -784,7 +783,7 @@ macro_rules! add_assign_impl { ($($t:ty)+) => ($( #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const AddAssign for $t { + const impl AddAssign for $t { #[inline] #[track_caller] #[rustc_inherit_overflow_checks] @@ -855,7 +854,7 @@ macro_rules! sub_assign_impl { ($($t:ty)+) => ($( #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const SubAssign for $t { + const impl SubAssign for $t { #[inline] #[track_caller] #[rustc_inherit_overflow_checks] @@ -917,7 +916,7 @@ macro_rules! mul_assign_impl { ($($t:ty)+) => ($( #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const MulAssign for $t { + const impl MulAssign for $t { #[inline] #[track_caller] #[rustc_inherit_overflow_checks] @@ -979,7 +978,7 @@ macro_rules! div_assign_impl { ($($t:ty)+) => ($( #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const DivAssign for $t { + const impl DivAssign for $t { #[inline] #[track_caller] fn div_assign(&mut self, other: $t) { *self /= other } @@ -1044,7 +1043,7 @@ macro_rules! rem_assign_impl { ($($t:ty)+) => ($( #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const RemAssign for $t { + const impl RemAssign for $t { #[inline] #[track_caller] fn rem_assign(&mut self, other: $t) { *self %= other } diff --git a/library/core/src/ops/bit.rs b/library/core/src/ops/bit.rs index 0cd61b0737381..7c008531c1f5a 100644 --- a/library/core/src/ops/bit.rs +++ b/library/core/src/ops/bit.rs @@ -56,7 +56,7 @@ macro_rules! not_impl { ($($t:ty)*) => ($( #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Not for $t { + const impl Not for $t { type Output = $t; #[inline] @@ -73,7 +73,7 @@ not_impl! { bool usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 } #[stable(feature = "not_never", since = "1.60.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const Not for ! { +const impl Not for ! { type Output = !; #[inline] @@ -171,7 +171,7 @@ macro_rules! bitand_impl { ($($t:ty)*) => ($( #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitAnd for $t { + const impl BitAnd for $t { type Output = $t; #[inline] @@ -275,7 +275,7 @@ macro_rules! bitor_impl { ($($t:ty)*) => ($( #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitOr for $t { + const impl BitOr for $t { type Output = $t; #[inline] @@ -379,7 +379,7 @@ macro_rules! bitxor_impl { ($($t:ty)*) => ($( #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitXor for $t { + const impl BitXor for $t { type Output = $t; #[inline] @@ -480,10 +480,11 @@ macro_rules! shl_impl { ($t:ty, $f:ty) => { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Shl<$f> for $t { + const impl Shl<$f> for $t { type Output = $t; #[inline] + #[track_caller] #[rustc_inherit_overflow_checks] fn shl(self, other: $f) -> $t { self << other @@ -602,10 +603,11 @@ macro_rules! shr_impl { ($t:ty, $f:ty) => { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Shr<$f> for $t { + const impl Shr<$f> for $t { type Output = $t; #[inline] + #[track_caller] #[rustc_inherit_overflow_checks] fn shr(self, other: $f) -> $t { self >> other @@ -741,7 +743,7 @@ macro_rules! bitand_assign_impl { ($($t:ty)+) => ($( #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitAndAssign for $t { + const impl BitAndAssign for $t { #[inline] fn bitand_assign(&mut self, other: $t) { *self &= other } } @@ -816,7 +818,7 @@ macro_rules! bitor_assign_impl { ($($t:ty)+) => ($( #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitOrAssign for $t { + const impl BitOrAssign for $t { #[inline] fn bitor_assign(&mut self, other: $t) { *self |= other } } @@ -891,7 +893,7 @@ macro_rules! bitxor_assign_impl { ($($t:ty)+) => ($( #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const BitXorAssign for $t { + const impl BitXorAssign for $t { #[inline] fn bitxor_assign(&mut self, other: $t) { *self ^= other } } @@ -956,8 +958,9 @@ macro_rules! shl_assign_impl { ($t:ty, $f:ty) => { #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const ShlAssign<$f> for $t { + const impl ShlAssign<$f> for $t { #[inline] + #[track_caller] #[rustc_inherit_overflow_checks] fn shl_assign(&mut self, other: $f) { *self <<= other @@ -1042,8 +1045,9 @@ macro_rules! shr_assign_impl { ($t:ty, $f:ty) => { #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const ShrAssign<$f> for $t { + const impl ShrAssign<$f> for $t { #[inline] + #[track_caller] #[rustc_inherit_overflow_checks] fn shr_assign(&mut self, other: $f) { *self >>= other diff --git a/library/core/src/ops/control_flow.rs b/library/core/src/ops/control_flow.rs index 3cc184f0ab75c..227c9c43bea66 100644 --- a/library/core/src/ops/control_flow.rs +++ b/library/core/src/ops/control_flow.rs @@ -102,7 +102,7 @@ pub enum ControlFlow { #[unstable(feature = "try_trait_v2", issue = "84277", old_name = "try_trait")] #[rustc_const_unstable(feature = "const_try", issue = "74935")] -impl const ops::Try for ControlFlow { +const impl ops::Try for ControlFlow { type Output = C; type Residual = ControlFlow; @@ -124,7 +124,7 @@ impl const ops::Try for ControlFlow { #[rustc_const_unstable(feature = "const_try", issue = "74935")] // Note: manually specifying the residual type instead of using the default to work around // https://github.com/rust-lang/rust/issues/99940 -impl const ops::FromResidual> for ControlFlow { +const impl ops::FromResidual> for ControlFlow { #[inline] fn from_residual(residual: ControlFlow) -> Self { match residual { @@ -134,7 +134,8 @@ impl const ops::FromResidual> for Cont } #[unstable(feature = "try_trait_v2_residual", issue = "91285")] -impl ops::Residual for ControlFlow { +#[rustc_const_unstable(feature = "const_try_residual", issue = "91285")] +const impl ops::Residual for ControlFlow { type TryType = ControlFlow; } @@ -151,7 +152,7 @@ impl ControlFlow { /// ``` #[inline] #[stable(feature = "control_flow_enum_is", since = "1.59.0")] - #[rustc_const_unstable(feature = "min_const_control_flow", issue = "148738")] + #[rustc_const_stable(feature = "min_const_control_flow", since = "1.95.0")] pub const fn is_break(&self) -> bool { matches!(*self, ControlFlow::Break(_)) } @@ -168,7 +169,7 @@ impl ControlFlow { /// ``` #[inline] #[stable(feature = "control_flow_enum_is", since = "1.59.0")] - #[rustc_const_unstable(feature = "min_const_control_flow", issue = "148738")] + #[rustc_const_stable(feature = "min_const_control_flow", since = "1.95.0")] pub const fn is_continue(&self) -> bool { matches!(*self, ControlFlow::Continue(_)) } @@ -197,14 +198,12 @@ impl ControlFlow { } } - /// Converts the `ControlFlow` into an `Result` which is `Ok` if the + /// Converts the `ControlFlow` into a `Result` which is `Ok` if the /// `ControlFlow` was `Break` and `Err` if otherwise. /// /// # Examples /// /// ``` - /// #![feature(control_flow_ok)] - /// /// use std::ops::ControlFlow; /// /// struct TreeNode { @@ -263,8 +262,9 @@ impl ControlFlow { /// assert_eq!(res, Ok(&5)); /// ``` #[inline] - #[unstable(feature = "control_flow_ok", issue = "140266")] - #[rustc_const_unstable(feature = "min_const_control_flow", issue = "148738")] + #[stable(feature = "control_flow_ok", since = "1.96.0")] + #[rustc_const_stable(feature = "control_flow_ok", since = "1.96.0")] + #[rustc_allow_const_fn_unstable(const_precise_live_drops)] pub const fn break_ok(self) -> Result { match self { ControlFlow::Continue(c) => Err(c), @@ -311,14 +311,12 @@ impl ControlFlow { } } - /// Converts the `ControlFlow` into an `Result` which is `Ok` if the + /// Converts the `ControlFlow` into a `Result` which is `Ok` if the /// `ControlFlow` was `Continue` and `Err` if otherwise. /// /// # Examples /// /// ``` - /// #![feature(control_flow_ok)] - /// /// use std::ops::ControlFlow; /// /// struct TreeNode { @@ -376,8 +374,9 @@ impl ControlFlow { /// assert_eq!(res, Err("too big value detected")); /// ``` #[inline] - #[unstable(feature = "control_flow_ok", issue = "140266")] - #[rustc_const_unstable(feature = "min_const_control_flow", issue = "148738")] + #[stable(feature = "control_flow_ok", since = "1.96.0")] + #[rustc_const_stable(feature = "control_flow_ok", since = "1.96.0")] + #[rustc_allow_const_fn_unstable(const_precise_live_drops)] pub const fn continue_ok(self) -> Result { match self { ControlFlow::Continue(c) => Ok(c), @@ -422,13 +421,17 @@ impl ControlFlow { } } -/// These are used only as part of implementing the iterator adapters. -/// They have mediocre names and non-obvious semantics, so aren't -/// currently on a path to potential stabilization. +// These are used only as part of implementing the iterator adapters. +// They have mediocre names and non-obvious semantics, so aren't +// currently on a path to potential stabilization. impl ControlFlow { /// Creates a `ControlFlow` from any type implementing `Try`. #[inline] - pub(crate) fn from_try(r: R) -> Self { + #[rustc_const_unstable(feature = "const_control_flow", issue = "148739")] + pub(crate) const fn from_try(r: R) -> Self + where + R: [const] ops::Try, + { match R::branch(r) { ControlFlow::Continue(v) => ControlFlow::Continue(v), ControlFlow::Break(v) => ControlFlow::Break(R::from_residual(v)), @@ -437,7 +440,11 @@ impl ControlFlow { /// Converts a `ControlFlow` into any type implementing `Try`. #[inline] - pub(crate) fn into_try(self) -> R { + #[rustc_const_unstable(feature = "const_control_flow", issue = "148739")] + pub(crate) const fn into_try(self) -> R + where + R: [const] ops::Try, + { match self { ControlFlow::Continue(v) => R::from_output(v), ControlFlow::Break(v) => v, diff --git a/library/core/src/ops/deref.rs b/library/core/src/ops/deref.rs index 305861ea7b698..58bf0e2d73b97 100644 --- a/library/core/src/ops/deref.rs +++ b/library/core/src/ops/deref.rs @@ -152,7 +152,7 @@ pub const trait Deref: PointeeSized { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Deref for &T { +const impl Deref for &T { type Target = T; #[rustc_diagnostic_item = "noop_method_deref"] @@ -166,7 +166,7 @@ impl !DerefMut for &T {} #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Deref for &mut T { +const impl Deref for &mut T { type Target = T; fn deref(&self) -> &T { @@ -276,7 +276,7 @@ pub const trait DerefMut: [const] Deref + PointeeSized { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const DerefMut for &mut T { +const impl DerefMut for &mut T { fn deref_mut(&mut self) -> &mut T { self } @@ -293,6 +293,7 @@ impl const DerefMut for &mut T { /// unchanged. #[unstable(feature = "deref_pure_trait", issue = "87121")] #[lang = "deref_pure"] +#[rustc_dyn_incompatible_trait] pub unsafe trait DerefPure: PointeeSized {} #[unstable(feature = "deref_pure_trait", issue = "87121")] diff --git a/library/core/src/ops/drop.rs b/library/core/src/ops/drop.rs index 7125bf54701bb..138460d54cf99 100644 --- a/library/core/src/ops/drop.rs +++ b/library/core/src/ops/drop.rs @@ -1,3 +1,5 @@ +use crate::pin::Pin; + /// Custom code within the destructor. /// /// When a value is no longer needed, Rust will run a "destructor" on that value. @@ -237,5 +239,30 @@ pub const trait Drop { /// [`mem::drop`]: drop /// [`ptr::drop_in_place`]: crate::ptr::drop_in_place #[stable(feature = "rust1", since = "1.0.0")] - fn drop(&mut self); + #[rustc_default_body_unstable(feature = "pin_ergonomics", issue = "130494")] + fn drop(&mut self) { + // SAFETY: `self` is pinned till after dropped. + unsafe { Drop::pin_drop(Pin::new_unchecked(self)) } + } + + /// Execute the destructor for this type, but different to [`Drop::drop`], it requires `self` + /// to be pinned. + /// + /// By implementing this method instead of [`Drop::drop`], the receiver type [`Pin<&mut Self>`] + /// makes sure that the value is pinned until it is deallocated (See [`std::pin` module docs] for + /// more details), which enables us to support field projections of `Self` type safely. + /// + /// For types that support pin-projection (i.e., marked with `#[pin_v2]`), this method must be used. + /// + /// For any type, at least and at most one of [`Drop::drop`] and [`Drop::pin_drop`] should be + /// implemented. + /// + /// See also [`Drop::drop`] for more details. + /// + /// [`Drop::drop`]: crate::ops::Drop::drop + /// [`Drop::pin_drop`]: crate::ops::Drop::pin_drop + /// [`Pin<&mut Self>`]: crate::pin::Pin + /// [`std::pin` module docs]: crate::pin + #[unstable(feature = "pin_ergonomics", issue = "130494")] + fn pin_drop(self: Pin<&mut Self>) {} } diff --git a/library/core/src/ops/function.rs b/library/core/src/ops/function.rs index efe5c0871fb8b..d40603e15bb1b 100644 --- a/library/core/src/ops/function.rs +++ b/library/core/src/ops/function.rs @@ -1,5 +1,5 @@ use crate::marker::Tuple; - +use crate::ptr::NonNull; /// The version of the call operator that takes an immutable receiver. /// /// Instances of `Fn` can be called repeatedly without mutating state. @@ -67,8 +67,8 @@ use crate::marker::Tuple; // SAFETY: tidy is not smart enough to tell that the below unsafe block is a string label = "call the function in a closure: `|| unsafe {{ /* code */ }}`" ), - message = "expected a `{Trait}` closure, found `{Self}`", - label = "expected an `{Trait}` closure, found `{Self}`" + message = "expected an `{This:resolved}` closure, found `{Self}`", + label = "expected an `{This:resolved}` closure, found `{Self}`" )] #[fundamental] // so that regex can rely that `&str: !FnMut` #[must_use = "closures are lazy and do nothing unless called"] @@ -154,8 +154,8 @@ pub const trait Fn: [const] FnMut { // SAFETY: tidy is not smart enough to tell that the below unsafe block is a string label = "call the function in a closure: `|| unsafe {{ /* code */ }}`" ), - message = "expected a `{Trait}` closure, found `{Self}`", - label = "expected an `{Trait}` closure, found `{Self}`" + message = "expected an `{This:resolved}` closure, found `{Self}`", + label = "expected an `{This:resolved}` closure, found `{Self}`" )] #[fundamental] // so that regex can rely that `&str: !FnMut` #[must_use = "closures are lazy and do nothing unless called"] @@ -233,8 +233,8 @@ pub const trait FnMut: FnOnce { // SAFETY: tidy is not smart enough to tell that the below unsafe block is a string label = "call the function in a closure: `|| unsafe {{ /* code */ }}`" ), - message = "expected a `{Trait}` closure, found `{Self}`", - label = "expected an `{Trait}` closure, found `{Self}`" + message = "expected an `{This:resolved}` closure, found `{Self}`", + label = "expected an `{This:resolved}` closure, found `{Self}`" )] #[fundamental] // so that regex can rely that `&str: !FnMut` #[must_use = "closures are lazy and do nothing unless called"] @@ -255,7 +255,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_trait_impl", issue = "143874")] - impl const Fn for &F + const impl Fn for &F where F: [const] Fn, { @@ -266,7 +266,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_trait_impl", issue = "143874")] - impl const FnMut for &F + const impl FnMut for &F where F: [const] Fn, { @@ -277,7 +277,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_trait_impl", issue = "143874")] - impl const FnOnce for &F + const impl FnOnce for &F where F: [const] Fn, { @@ -290,7 +290,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_trait_impl", issue = "143874")] - impl const FnMut for &mut F + const impl FnMut for &mut F where F: [const] FnMut, { @@ -301,7 +301,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_trait_impl", issue = "143874")] - impl const FnOnce for &mut F + const impl FnOnce for &mut F where F: [const] FnMut, { @@ -311,3 +311,40 @@ mod impls { } } } + +unsafe extern "C" { + /// A type representing a pointer to a function pointer. + #[unstable(feature = "fn_static", issue = "148768")] + #[lang = "code"] + pub type Code; +} + +/// A common trait implemented by all function pointers. +#[unstable(feature = "fn_static", issue = "148768")] +#[lang = "fn_ptr_trait"] +#[fundamental] +#[rustc_deny_explicit_impl] +#[rustc_dyn_incompatible_trait] +pub trait FnPtr: Copy { + /// Returns the address of the function pointer. + #[unstable(feature = "fn_static", issue = "148768")] + fn addr(self) -> usize { + self.as_ptr().addr().get() + } + + /// Returns the function pointer as a [`NonNull`]. + #[unstable(feature = "fn_static", issue = "148768")] + #[lang = "fn_ptr_as_ptr"] + fn as_ptr(self) -> NonNull; + + /// Constructs a function pointer from a `NonNull` pointer. + /// + /// # Safety + /// + /// The function pointer must have been obtained + /// from an [`FnPtr::as_ptr`] call from a function + /// pointer type that is ABI compatible. + #[unstable(feature = "fn_static", issue = "148768")] + #[lang = "fn_ptr_from_ptr"] + unsafe fn from_ptr(ptr: NonNull) -> Self; +} diff --git a/library/core/src/ops/mod.rs b/library/core/src/ops/mod.rs index ab1ad407ee282..6fa96c242fa76 100644 --- a/library/core/src/ops/mod.rs +++ b/library/core/src/ops/mod.rs @@ -149,7 +149,6 @@ mod function; mod index; mod index_range; mod range; -mod reborrow; mod try_trait; mod unsize; @@ -177,6 +176,8 @@ pub use self::deref::Receiver; pub use self::deref::{Deref, DerefMut}; #[stable(feature = "rust1", since = "1.0.0")] pub use self::drop::Drop; +#[unstable(feature = "fn_static", issue = "148768")] +pub use self::function::{Code, FnPtr}; #[stable(feature = "rust1", since = "1.0.0")] pub use self::function::{Fn, FnMut, FnOnce}; #[stable(feature = "rust1", since = "1.0.0")] @@ -190,8 +191,6 @@ pub use self::range::{Bound, RangeBounds, RangeInclusive, RangeToInclusive}; pub use self::range::{OneSidedRange, OneSidedRangeBound}; #[stable(feature = "rust1", since = "1.0.0")] pub use self::range::{Range, RangeFrom, RangeFull, RangeTo}; -#[unstable(feature = "reborrow", issue = "145612")] -pub use self::reborrow::{CoerceShared, Reborrow}; #[unstable(feature = "try_trait_v2_residual", issue = "91285")] pub use self::try_trait::Residual; #[unstable(feature = "try_trait_v2_yeet", issue = "96374")] diff --git a/library/core/src/ops/range.rs b/library/core/src/ops/range.rs index c15c8f20c16be..ebb6c3ddb938c 100644 --- a/library/core/src/ops/range.rs +++ b/library/core/src/ops/range.rs @@ -363,10 +363,15 @@ pub struct RangeInclusive { pub(crate) start: Idx, pub(crate) end: Idx, - // This field is: + // This field represents an overflow flag for either bound (start or end): // - `false` upon construction - // - `false` when iteration has yielded an element and the iterator is not exhausted - // - `true` when iteration has been used to exhaust the iterator + // - `false` when iteration has yielded an element and + // neither bound has overflowed the valid range of `Idx` + // - `true` when iteration has caused either bound to + // overflow the valid range of `Idx` + // + // When this is true, `start` or `end` may be left in an unspecified state, + // often wrapping (modular arithmetic) around at the boundary of `Idx`. // // This is required to support PartialEq and Hash without a PartialOrd bound or specialization. pub(crate) exhausted: bool, @@ -464,6 +469,13 @@ impl RangeInclusive { /// The caller is responsible for dealing with `end == usize::MAX`. #[inline] pub(crate) const fn into_slice_range(self) -> Range { + // Typically users should not be indexing with exhausted instances, + // but this heuristic should apply to most cases. This doesn't + // handle reverse iteration well (`next_back` and `nth_back` can + // cause `end` to wrap around to values at or near `usize::MAX`), + // but using an exhausted `RangeInclusive` after reverse iteration + // is an exceedingly rare case. + // If we're not exhausted, we want to simply slice `start..end + 1`. // If we are exhausted, then slicing with `end + 1..end + 1` gives us an // empty range that is still subject to bounds-checks for that endpoint. @@ -1045,7 +1057,7 @@ use self::Bound::{Excluded, Included, Unbounded}; #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeFull { +const impl RangeBounds for RangeFull { fn start_bound(&self) -> Bound<&T> { Unbounded } @@ -1056,7 +1068,7 @@ impl const RangeBounds for RangeFull { #[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const IntoBounds for RangeFull { +const impl IntoBounds for RangeFull { fn into_bounds(self) -> (Bound, Bound) { (Unbounded, Unbounded) } @@ -1064,7 +1076,7 @@ impl const IntoBounds for RangeFull { #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeFrom { +const impl RangeBounds for RangeFrom { fn start_bound(&self) -> Bound<&T> { Included(&self.start) } @@ -1075,7 +1087,7 @@ impl const RangeBounds for RangeFrom { #[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const IntoBounds for RangeFrom { +const impl IntoBounds for RangeFrom { fn into_bounds(self) -> (Bound, Bound) { (Included(self.start), Unbounded) } @@ -1083,7 +1095,7 @@ impl const IntoBounds for RangeFrom { #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeTo { +const impl RangeBounds for RangeTo { fn start_bound(&self) -> Bound<&T> { Unbounded } @@ -1094,7 +1106,7 @@ impl const RangeBounds for RangeTo { #[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const IntoBounds for RangeTo { +const impl IntoBounds for RangeTo { fn into_bounds(self) -> (Bound, Bound) { (Unbounded, Excluded(self.end)) } @@ -1102,7 +1114,7 @@ impl const IntoBounds for RangeTo { #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for Range { +const impl RangeBounds for Range { fn start_bound(&self) -> Bound<&T> { Included(&self.start) } @@ -1113,7 +1125,7 @@ impl const RangeBounds for Range { #[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const IntoBounds for Range { +const impl IntoBounds for Range { fn into_bounds(self) -> (Bound, Bound) { (Included(self.start), Excluded(self.end)) } @@ -1121,15 +1133,17 @@ impl const IntoBounds for Range { #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeInclusive { +const impl RangeBounds for RangeInclusive { fn start_bound(&self) -> Bound<&T> { Included(&self.start) } fn end_bound(&self) -> Bound<&T> { if self.exhausted { - // When the iterator is exhausted, we usually have start == end, + // When the iterator is exhausted, it might have overflowed, // but we want the range to appear empty, containing nothing. - Excluded(&self.end) + // So in that case, we return bounds which are always empty: + // Included(start)..Excluded(start) + Excluded(&self.start) } else { Included(&self.end) } @@ -1138,24 +1152,20 @@ impl const RangeBounds for RangeInclusive { #[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const IntoBounds for RangeInclusive { +const impl IntoBounds for RangeInclusive { fn into_bounds(self) -> (Bound, Bound) { - ( - Included(self.start), - if self.exhausted { - // When the iterator is exhausted, we usually have start == end, - // but we want the range to appear empty, containing nothing. - Excluded(self.end) - } else { - Included(self.end) - }, - ) + assert!( + !self.exhausted, + "attempted to convert from an exhausted `RangeInclusive` (unspecified behavior)" + ); + + (Included(self.start), Included(self.end)) } } #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeToInclusive { +const impl RangeBounds for RangeToInclusive { fn start_bound(&self) -> Bound<&T> { Unbounded } @@ -1166,7 +1176,7 @@ impl const RangeBounds for RangeToInclusive { #[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const IntoBounds for RangeToInclusive { +const impl IntoBounds for RangeToInclusive { fn into_bounds(self) -> (Bound, Bound) { (Unbounded, Included(self.end)) } @@ -1174,7 +1184,7 @@ impl const IntoBounds for RangeToInclusive { #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for (Bound, Bound) { +const impl RangeBounds for (Bound, Bound) { fn start_bound(&self) -> Bound<&T> { match *self { (Included(ref start), _) => Included(start), @@ -1194,7 +1204,7 @@ impl const RangeBounds for (Bound, Bound) { #[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const IntoBounds for (Bound, Bound) { +const impl IntoBounds for (Bound, Bound) { fn into_bounds(self) -> (Bound, Bound) { self } @@ -1202,7 +1212,7 @@ impl const IntoBounds for (Bound, Bound) { #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl<'a, T: ?Sized + 'a> const RangeBounds for (Bound<&'a T>, Bound<&'a T>) { +const impl<'a, T: ?Sized + 'a> RangeBounds for (Bound<&'a T>, Bound<&'a T>) { fn start_bound(&self) -> Bound<&T> { self.0 } @@ -1220,7 +1230,7 @@ impl<'a, T: ?Sized + 'a> const RangeBounds for (Bound<&'a T>, Bound<&'a T>) { /// i.e. replace `start..` with `(Bound::Included(start), Bound::Unbounded)`. #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeFrom<&T> { +const impl RangeBounds for RangeFrom<&T> { fn start_bound(&self) -> Bound<&T> { Included(self.start) } @@ -1237,7 +1247,7 @@ impl const RangeBounds for RangeFrom<&T> { /// i.e. replace `..end` with `(Bound::Unbounded, Bound::Excluded(end))`. #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeTo<&T> { +const impl RangeBounds for RangeTo<&T> { fn start_bound(&self) -> Bound<&T> { Unbounded } @@ -1254,7 +1264,7 @@ impl const RangeBounds for RangeTo<&T> { /// i.e. replace `start..end` with `(Bound::Included(start), Bound::Excluded(end))`. #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for Range<&T> { +const impl RangeBounds for Range<&T> { fn start_bound(&self) -> Bound<&T> { Included(self.start) } @@ -1271,7 +1281,7 @@ impl const RangeBounds for Range<&T> { /// i.e. replace `start..=end` with `(Bound::Included(start), Bound::Included(end))`. #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeInclusive<&T> { +const impl RangeBounds for RangeInclusive<&T> { fn start_bound(&self) -> Bound<&T> { Included(self.start) } @@ -1288,7 +1298,7 @@ impl const RangeBounds for RangeInclusive<&T> { /// i.e. replace `..=end` with `(Bound::Unbounded, Bound::Included(end))`. #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeToInclusive<&T> { +const impl RangeBounds for RangeToInclusive<&T> { fn start_bound(&self) -> Bound<&T> { Unbounded } @@ -1326,7 +1336,7 @@ pub const trait OneSidedRange: RangeBounds { #[unstable(feature = "one_sided_range", issue = "69780")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const OneSidedRange for RangeTo +const impl OneSidedRange for RangeTo where Self: RangeBounds, { @@ -1337,7 +1347,7 @@ where #[unstable(feature = "one_sided_range", issue = "69780")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const OneSidedRange for RangeFrom +const impl OneSidedRange for RangeFrom where Self: RangeBounds, { @@ -1348,7 +1358,7 @@ where #[unstable(feature = "one_sided_range", issue = "69780")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const OneSidedRange for RangeToInclusive +const impl OneSidedRange for RangeToInclusive where Self: RangeBounds, { diff --git a/library/core/src/ops/reborrow.rs b/library/core/src/ops/reborrow.rs deleted file mode 100644 index f83f4233a4de5..0000000000000 --- a/library/core/src/ops/reborrow.rs +++ /dev/null @@ -1,16 +0,0 @@ -/// Allows value to be reborrowed as exclusive, creating a copy of the value -/// that disables the source for reads and writes for the lifetime of the copy. -#[lang = "reborrow"] -#[unstable(feature = "reborrow", issue = "145612")] -pub trait Reborrow { - // Empty. -} - -/// Allows reborrowable value to be reborrowed as shared, creating a copy -/// that disables the source for writes for the lifetime of the copy. -#[lang = "coerce_shared"] -#[unstable(feature = "reborrow", issue = "145612")] -pub trait CoerceShared: Reborrow { - /// The type of this value when reborrowed as shared. - type Target: Copy; -} diff --git a/library/core/src/ops/try_trait.rs b/library/core/src/ops/try_trait.rs index 34000f6d6b218..f7486cddaae5d 100644 --- a/library/core/src/ops/try_trait.rs +++ b/library/core/src/ops/try_trait.rs @@ -1,4 +1,4 @@ -use crate::marker::{Destruct, PhantomData}; +use crate::marker::Destruct; use crate::ops::ControlFlow; /// The `?` operator and `try {}` blocks. @@ -157,7 +157,7 @@ pub const trait Try: [const] FromResidual { /// type: that type will have a "hole" in the correct place, and will maintain the /// "foo-ness" of the residual so other types need to opt-in to interconversion. #[unstable(feature = "try_trait_v2", issue = "84277", old_name = "try_trait")] - type Residual; + type Residual: Residual; /// Constructs the type from its `Output` type. /// @@ -398,25 +398,6 @@ pub(crate) type ChangeOutputType>, V> = /// Not currently planned to be exposed publicly, so just `pub(crate)`. #[repr(transparent)] pub(crate) struct NeverShortCircuit(pub T); -// FIXME(const-hack): replace with `|a| NeverShortCircuit(f(a))` when const closures added. -pub(crate) struct Wrapped T> { - f: F, - p: PhantomData<(T, A)>, -} -#[rustc_const_unstable(feature = "const_never_short_circuit", issue = "none")] -impl T + [const] Destruct> const FnOnce<(A,)> for Wrapped { - type Output = NeverShortCircuit; - - extern "rust-call" fn call_once(mut self, args: (A,)) -> Self::Output { - self.call_mut(args) - } -} -#[rustc_const_unstable(feature = "const_never_short_circuit", issue = "none")] -impl T> const FnMut<(A,)> for Wrapped { - extern "rust-call" fn call_mut(&mut self, (args,): (A,)) -> Self::Output { - NeverShortCircuit((self.f)(args)) - } -} impl NeverShortCircuit { /// Wraps a unary function to produce one that wraps the output into a `NeverShortCircuit`. @@ -424,23 +405,32 @@ impl NeverShortCircuit { /// This is useful for implementing infallible functions in terms of the `try_` ones, /// without accidentally capturing extra generic parameters in a closure. #[inline] - pub(crate) const fn wrap_mut_1(f: F) -> Wrapped + #[rustc_const_unstable(feature = "const_array", issue = "147606")] + pub(crate) const fn wrap_mut_1( + mut f: F, + ) -> impl [const] FnMut(A) -> Self + [const] Destruct where - F: [const] FnMut(A) -> T, + F: [const] FnMut(A) -> T + [const] Destruct, { - Wrapped { f, p: PhantomData } + const move |a| NeverShortCircuit(f(a)) } #[inline] - pub(crate) fn wrap_mut_2(mut f: impl FnMut(A, B) -> T) -> impl FnMut(A, B) -> Self { - move |a, b| NeverShortCircuit(f(a, b)) + #[rustc_const_unstable(feature = "const_array", issue = "147606")] + pub(crate) const fn wrap_mut_2( + mut f: F, + ) -> impl [const] FnMut(A, B) -> Self + [const] Destruct + where + F: [const] FnMut(A, B) -> T + [const] Destruct, + { + const move |a, b| NeverShortCircuit(f(a, b)) } } pub(crate) enum NeverShortCircuitResidual {} #[rustc_const_unstable(feature = "const_never_short_circuit", issue = "none")] -impl const Try for NeverShortCircuit { +const impl Try for NeverShortCircuit { type Output = T; type Residual = NeverShortCircuitResidual; @@ -455,14 +445,14 @@ impl const Try for NeverShortCircuit { } } #[rustc_const_unstable(feature = "const_never_short_circuit", issue = "none")] -impl const FromResidual for NeverShortCircuit { +const impl FromResidual for NeverShortCircuit { #[inline] fn from_residual(never: NeverShortCircuitResidual) -> Self { match never {} } } #[rustc_const_unstable(feature = "const_never_short_circuit", issue = "none")] -impl const Residual for NeverShortCircuitResidual { +const impl Residual for NeverShortCircuitResidual { type TryType = NeverShortCircuit; } diff --git a/library/core/src/ops/unsize.rs b/library/core/src/ops/unsize.rs index f0781ee01fd53..aade68df2b6ce 100644 --- a/library/core/src/ops/unsize.rs +++ b/library/core/src/ops/unsize.rs @@ -33,13 +33,16 @@ use crate::marker::{PointeeSized, Unsize}; /// [nomicon-coerce]: ../../nomicon/coercions.html #[unstable(feature = "coerce_unsized", issue = "18598")] #[lang = "coerce_unsized"] -pub trait CoerceUnsized { +pub trait CoerceUnsized: Sized { // Empty. } // &mut T -> &mut U #[unstable(feature = "coerce_unsized", issue = "18598")] -impl<'a, T: PointeeSized + Unsize, U: PointeeSized> CoerceUnsized<&'a mut U> for &'a mut T {} +impl<'a, 'b: 'a, T: PointeeSized + Unsize, U: PointeeSized> CoerceUnsized<&'a mut U> + for &'b mut T +{ +} // &mut T -> &U #[unstable(feature = "coerce_unsized", issue = "18598")] impl<'a, 'b: 'a, T: PointeeSized + Unsize, U: PointeeSized> CoerceUnsized<&'a U> for &'b mut T {} @@ -116,7 +119,7 @@ impl, U: PointeeSized> CoerceUnsized<*const U> for * /// [^1]: Formerly known as *object safety*. #[unstable(feature = "dispatch_from_dyn", issue = "none")] #[lang = "dispatch_from_dyn"] -pub trait DispatchFromDyn { +pub trait DispatchFromDyn: Sized { // Empty. } diff --git a/library/core/src/option.rs b/library/core/src/option.rs index 6c898c38b99e2..1bcd727316c0a 100644 --- a/library/core/src/option.rs +++ b/library/core/src/option.rs @@ -40,9 +40,6 @@ //! } //! ``` //! -// -// FIXME: Show how `Option` is used in practice, with lots of methods -// //! # Options and pointers ("nullable" pointers) //! //! Rust's pointer types must always point to a valid location; there are @@ -584,6 +581,7 @@ use crate::clone::TrivialClone; use crate::iter::{self, FusedIterator, TrustedLen}; use crate::marker::Destruct; +use crate::num::NonZero; use crate::ops::{self, ControlFlow, Deref, DerefMut, Residual, Try}; use crate::panicking::{panic, panic_display}; use crate::pin::Pin; @@ -1286,8 +1284,6 @@ impl Option { /// # Examples /// /// ``` - /// #![feature(result_option_map_or_default)] - /// /// let x: Option<&str> = Some("hi"); /// let y: Option<&str> = None; /// @@ -1297,7 +1293,7 @@ impl Option { /// /// [default value]: Default::default #[inline] - #[unstable(feature = "result_option_map_or_default", issue = "138099")] + #[stable(feature = "result_option_map_or_default", since = "1.98.0")] #[rustc_const_unstable(feature = "const_option_ops", issue = "143956")] pub const fn map_or_default(self, f: F) -> U where @@ -1751,8 +1747,12 @@ impl Option { /// ``` #[inline] #[stable(feature = "option_entry", since = "1.20.0")] - pub fn get_or_insert(&mut self, value: T) -> &mut T { - self.get_or_insert_with(|| value) + #[rustc_const_unstable(feature = "const_option_ops", issue = "143956")] + pub const fn get_or_insert(&mut self, value: T) -> &mut T + where + T: [const] Destruct, + { + self.get_or_insert_with(const || value) } /// Inserts the default value into the option if it is [`None`], then @@ -1777,7 +1777,7 @@ impl Option { #[rustc_const_unstable(feature = "const_option_ops", issue = "143956")] pub const fn get_or_insert_default(&mut self) -> &mut T where - T: [const] Default + [const] Destruct, + T: [const] Default, { self.get_or_insert_with(T::default) } @@ -1805,10 +1805,25 @@ impl Option { pub const fn get_or_insert_with(&mut self, f: F) -> &mut T where F: [const] FnOnce() -> T + [const] Destruct, - T: [const] Destruct, { if let None = self { - *self = Some(f()); + // The effect of the following statement is identical to + // *self = Some(f()); + // except that it does not drop the old value of `*self`. This is not a leak, because + // we just checked that the old value is `None`, which contains no fields to drop. + // This implementation strategy + // + // * avoids needing a `T: [const] Destruct` bound, to the benefit of `const` callers, + // * and avoids possibly compiling needless drop code (as would sometimes happen in the + // previous implementation), to the benefit of non-`const` callers. + // + // FIXME(const-hack): It would be nice if this weird trick were made obsolete + // (though that is likely to be hard/wontfix). + // + // It could also be expressed as `unsafe { core::ptr::write(self, Some(f())) }`, but + // no reason is currently known to use additional unsafe code here. + + mem::forget(mem::replace(self, Some(f()))); } // SAFETY: a `None` variant for `self` would have been replaced by a `Some` @@ -1944,7 +1959,7 @@ impl Option { mem::replace(self, Some(value)) } - /// Zips `self` with another `Option`. + /// Makes a tuple of the value in `self` and the value in another `Option`. /// /// If `self` is `Some(s)` and `other` is `Some(o)`, this method returns `Some((s, o))`. /// Otherwise, `None` is returned. @@ -1972,7 +1987,7 @@ impl Option { } } - /// Zips `self` and another `Option` with function `f`. + /// Combines the value in `self` with the value in another `Option`, using the function `f`. /// /// If `self` is `Some(s)` and `other` is `Some(o)`, this method returns `Some(f(s, o))`. /// Otherwise, `None` is returned. @@ -2067,10 +2082,7 @@ impl Option { /// assert_eq!(o2.into_flat_iter().collect::>(), Vec::<&usize>::new()); /// ``` #[unstable(feature = "option_into_flat_iter", issue = "148441")] - pub fn into_flat_iter(self) -> OptionFlatten - where - T: IntoIterator, - { + pub fn into_flat_iter(self) -> OptionFlatten { OptionFlatten { iter: self.map(IntoIterator::into_iter) } } } @@ -2251,7 +2263,7 @@ const fn expect_failed(msg: &str) -> ! { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] -impl const Clone for Option +const impl Clone for Option where // FIXME(const_hack): the T: [const] Destruct should be inferred from the Self: [const] Destruct in clone_from. // See https://github.com/rust-lang/rust/issues/144207 @@ -2280,11 +2292,11 @@ impl crate::clone::UseCloned for Option where T: crate::clone::UseCloned { #[doc(hidden)] #[unstable(feature = "trivial_clone", issue = "none")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] -unsafe impl const TrivialClone for Option where T: [const] TrivialClone + [const] Destruct {} +const unsafe impl TrivialClone for Option where T: [const] TrivialClone + [const] Destruct {} #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for Option { +const impl Default for Option { /// Returns [`None`][Option::None]. /// /// # Examples @@ -2301,7 +2313,7 @@ impl const Default for Option { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_iter", issue = "92476")] -impl const IntoIterator for Option { +const impl IntoIterator for Option { type Item = T; type IntoIter = IntoIter; @@ -2346,7 +2358,7 @@ impl<'a, T> IntoIterator for &'a mut Option { #[stable(since = "1.12.0", feature = "option_from")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for Option { +const impl From for Option { /// Moves `val` into a new [`Some`]. /// /// # Examples @@ -2363,7 +2375,7 @@ impl const From for Option { #[stable(feature = "option_ref_from_ref_option", since = "1.30.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl<'a, T> const From<&'a Option> for Option<&'a T> { +const impl<'a, T> From<&'a Option> for Option<&'a T> { /// Converts from `&Option` to `Option<&T>`. /// /// # Examples @@ -2391,7 +2403,7 @@ impl<'a, T> const From<&'a Option> for Option<&'a T> { #[stable(feature = "option_ref_from_ref_option", since = "1.30.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl<'a, T> const From<&'a mut Option> for Option<&'a mut T> { +const impl<'a, T> From<&'a mut Option> for Option<&'a mut T> { /// Converts from `&mut Option` to `Option<&mut T>` /// /// # Examples @@ -2419,7 +2431,7 @@ impl<'a, T> const From<&'a mut Option> for Option<&'a mut T> { impl crate::marker::StructuralPartialEq for Option {} #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq for Option { +const impl PartialEq for Option { #[inline] fn eq(&self, other: &Self) -> bool { // Spelling out the cases explicitly optimizes better than @@ -2438,7 +2450,7 @@ impl const PartialEq for Option { // not optimal. #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialOrd for Option { +const impl PartialOrd for Option { #[inline] fn partial_cmp(&self, other: &Self) -> Option { match (self, other) { @@ -2452,7 +2464,7 @@ impl const PartialOrd for Option { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const Ord for Option { +const impl Ord for Option { #[inline] fn cmp(&self, other: &Self) -> cmp::Ordering { match (self, other) { @@ -2474,7 +2486,7 @@ struct Item { } #[rustc_const_unstable(feature = "const_iter", issue = "92476")] -impl const Iterator for Item { +const impl Iterator for Item { type Item = A; #[inline] @@ -2609,7 +2621,7 @@ pub struct IntoIter { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_iter", issue = "92476")] -impl const Iterator for IntoIter { +const impl Iterator for IntoIter { type Item = A; #[inline] @@ -2637,7 +2649,8 @@ impl ExactSizeIterator for IntoIter {} impl FusedIterator for IntoIter {} #[unstable(feature = "trusted_len", issue = "37572")] -unsafe impl TrustedLen for IntoIter {} +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] +const unsafe impl TrustedLen for IntoIter {} /// The iterator produced by [`Option::into_flat_iter`]. See its documentation for more. #[derive(Clone, Debug)] @@ -2651,18 +2664,111 @@ impl Iterator for OptionFlatten { type Item = A::Item; fn next(&mut self) -> Option { - self.iter.as_mut()?.next() + match &mut self.iter { + Some(iter) => iter.next(), + None => None, + } } fn size_hint(&self) -> (usize, Option) { - self.iter.as_ref().map(|i| i.size_hint()).unwrap_or((0, Some(0))) + match &self.iter { + Some(iter) => iter.size_hint(), + None => (0, Some(0)), + } + } + + fn advance_by(&mut self, n: usize) -> Result<(), NonZero> { + match &mut self.iter { + Some(iter) => iter.advance_by(n), + None => NonZero::new(n).map_or(Ok(()), Err), + } + } + + fn nth(&mut self, n: usize) -> Option { + match &mut self.iter { + Some(iter) => iter.nth(n), + None => None, + } + } + + fn fold(self, init: Acc, fold: Fold) -> Acc + where + Fold: FnMut(Acc, Self::Item) -> Acc, + { + match self.iter { + Some(iter) => iter.fold(init, fold), + None => init, + } + } + + fn try_fold(&mut self, init: Acc, fold: Fold) -> R + where + Fold: FnMut(Acc, Self::Item) -> R, + R: Try, + { + match &mut self.iter { + Some(iter) => iter.try_fold(init, fold), + None => try { init }, + } + } + + fn count(self) -> usize { + match self.iter { + Some(iter) => iter.count(), + None => 0, + } + } + + fn last(self) -> Option { + match self.iter { + Some(iter) => iter.last(), + None => None, + } } } #[unstable(feature = "option_into_flat_iter", issue = "148441")] impl DoubleEndedIterator for OptionFlatten { fn next_back(&mut self) -> Option { - self.iter.as_mut()?.next_back() + match &mut self.iter { + Some(iter) => iter.next_back(), + None => None, + } + } + + fn advance_back_by(&mut self, n: usize) -> Result<(), NonZero> { + match &mut self.iter { + Some(iter) => iter.advance_back_by(n), + None => NonZero::new(n).map_or(Ok(()), Err), + } + } + + fn nth_back(&mut self, n: usize) -> Option { + match &mut self.iter { + Some(iter) => iter.nth_back(n), + None => None, + } + } + + fn rfold(self, init: Acc, fold: Fold) -> Acc + where + Fold: FnMut(Acc, Self::Item) -> Acc, + { + match self.iter { + Some(iter) => iter.rfold(init, fold), + None => init, + } + } + + fn try_rfold(&mut self, init: Acc, fold: Fold) -> R + where + Fold: FnMut(Acc, Self::Item) -> R, + R: Try, + { + match &mut self.iter { + Some(iter) => iter.try_rfold(init, fold), + None => try { init }, + } } } @@ -2743,16 +2849,13 @@ impl> FromIterator> for Option { /// so the final value of `shared` is 6 (= `3 + 2 + 1`), not 16. #[inline] fn from_iter>>(iter: I) -> Option { - // FIXME(#11084): This could be replaced with Iterator::scan when this - // performance bug is closed. - iter::try_process(iter.into_iter(), |i| i.collect()) } } #[unstable(feature = "try_trait_v2", issue = "84277", old_name = "try_trait")] #[rustc_const_unstable(feature = "const_try", issue = "74935")] -impl const ops::Try for Option { +const impl ops::Try for Option { type Output = T; type Residual = Option; @@ -2774,7 +2877,7 @@ impl const ops::Try for Option { #[rustc_const_unstable(feature = "const_try", issue = "74935")] // Note: manually specifying the residual type instead of using the default to work around // https://github.com/rust-lang/rust/issues/99940 -impl const ops::FromResidual> for Option { +const impl ops::FromResidual> for Option { #[inline] fn from_residual(residual: Option) -> Self { match residual { @@ -2786,7 +2889,7 @@ impl const ops::FromResidual> for Option { #[diagnostic::do_not_recommend] #[unstable(feature = "try_trait_v2_yeet", issue = "96374")] #[rustc_const_unstable(feature = "const_try", issue = "74935")] -impl const ops::FromResidual> for Option { +const impl ops::FromResidual> for Option { #[inline] fn from_residual(ops::Yeet(()): ops::Yeet<()>) -> Self { None @@ -2795,7 +2898,7 @@ impl const ops::FromResidual> for Option { #[unstable(feature = "try_trait_v2_residual", issue = "91285")] #[rustc_const_unstable(feature = "const_try", issue = "74935")] -impl const ops::Residual for Option { +const impl ops::Residual for Option { type TryType = Option; } diff --git a/library/core/src/os/darwin/objc.rs b/library/core/src/os/darwin/objc.rs index df3aab867e83d..7be07891085a3 100644 --- a/library/core/src/os/darwin/objc.rs +++ b/library/core/src/os/darwin/objc.rs @@ -67,7 +67,8 @@ pub type SEL = *mut objc_selector; /// /// # Example /// -/// ```no_run +#[cfg_attr(target_os = "macos", doc = "```no_run")] +#[cfg_attr(not(target_os = "macos"), doc = "```ignore (needs macos)")] /// #![feature(darwin_objc)] /// use core::os::darwin::objc; /// @@ -93,7 +94,8 @@ pub macro class($classname:expr) {{ /// /// # Examples /// -/// ```no_run +#[cfg_attr(target_os = "macos", doc = "```no_run")] +#[cfg_attr(not(target_os = "macos"), doc = "```ignore (needs macos)")] /// #![feature(darwin_objc)] /// use core::os::darwin::objc; /// diff --git a/library/core/src/panic.rs b/library/core/src/panic.rs index cf07504466808..4332e7d28c58b 100644 --- a/library/core/src/panic.rs +++ b/library/core/src/panic.rs @@ -1,4 +1,4 @@ -//! Panic support in the standard library. +//! Panic support in core. #![stable(feature = "core_panic_info", since = "1.41.0")] @@ -116,7 +116,7 @@ pub macro unreachable_2021 { /// convert unwinds to aborts, so using this function isn't necessary for FFI. #[unstable(feature = "abort_unwind", issue = "130338")] #[rustc_nounwind] -pub fn abort_unwind R, R>(f: F) -> R { +pub fn abort_on_unwind R, R>(f: F) -> R { f() } diff --git a/library/core/src/panic/panic_info.rs b/library/core/src/panic/panic_info.rs index 9d53567a26fd9..ee22521cb014c 100644 --- a/library/core/src/panic/panic_info.rs +++ b/library/core/src/panic/panic_info.rs @@ -13,7 +13,7 @@ use crate::panic::Location; #[derive(Debug)] pub struct PanicInfo<'a> { message: &'a fmt::Arguments<'a>, - location: &'a Location<'a>, + location: &'static Location<'static>, can_unwind: bool, force_no_backtrace: bool, } @@ -33,7 +33,7 @@ impl<'a> PanicInfo<'a> { #[inline] pub(crate) fn new( message: &'a fmt::Arguments<'a>, - location: &'a Location<'a>, + location: &'static Location<'static>, can_unwind: bool, force_no_backtrace: bool, ) -> Self { @@ -88,10 +88,10 @@ impl<'a> PanicInfo<'a> { /// ``` #[must_use] #[stable(feature = "panic_hooks", since = "1.10.0")] - pub fn location(&self) -> Option<&Location<'_>> { + pub fn location(&self) -> Option<&'static Location<'static>> { // NOTE: If this is changed to sometimes return None, // deal with that case in std::panicking::default_hook and core::panicking::panic_fmt. - Some(&self.location) + Some(self.location) } /// Returns the payload associated with the panic. diff --git a/library/core/src/panic/unwind_safe.rs b/library/core/src/panic/unwind_safe.rs index 21dbd09f49606..bf2e61dc541c6 100644 --- a/library/core/src/panic/unwind_safe.rs +++ b/library/core/src/panic/unwind_safe.rs @@ -2,6 +2,7 @@ use crate::async_iter::AsyncIterator; use crate::cell::UnsafeCell; use crate::fmt; use crate::future::Future; +use crate::marker::PointeeSized; use crate::ops::{Deref, DerefMut}; use crate::pin::Pin; use crate::ptr::{NonNull, Unique}; @@ -178,17 +179,17 @@ pub struct AssertUnwindSafe(#[stable(feature = "catch_unwind", since = "1.9.0 // * Our custom AssertUnwindSafe wrapper is indeed unwind safe #[stable(feature = "catch_unwind", since = "1.9.0")] -impl !UnwindSafe for &mut T {} +impl !UnwindSafe for &mut T {} #[stable(feature = "catch_unwind", since = "1.9.0")] -impl UnwindSafe for &T {} +impl UnwindSafe for &T {} #[stable(feature = "catch_unwind", since = "1.9.0")] -impl UnwindSafe for *const T {} +impl UnwindSafe for *const T {} #[stable(feature = "catch_unwind", since = "1.9.0")] -impl UnwindSafe for *mut T {} +impl UnwindSafe for *mut T {} #[unstable(feature = "ptr_internals", issue = "none")] -impl UnwindSafe for Unique {} +impl UnwindSafe for Unique {} #[stable(feature = "nonnull", since = "1.25.0")] -impl UnwindSafe for NonNull {} +impl UnwindSafe for NonNull {} #[stable(feature = "catch_unwind", since = "1.9.0")] impl UnwindSafe for AssertUnwindSafe {} @@ -249,7 +250,7 @@ impl RefUnwindSafe for crate::sync::atomic::AtomicPtr {} #[stable(feature = "catch_unwind", since = "1.9.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Deref for AssertUnwindSafe { +const impl Deref for AssertUnwindSafe { type Target = T; fn deref(&self) -> &T { @@ -259,7 +260,7 @@ impl const Deref for AssertUnwindSafe { #[stable(feature = "catch_unwind", since = "1.9.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const DerefMut for AssertUnwindSafe { +const impl DerefMut for AssertUnwindSafe { fn deref_mut(&mut self) -> &mut T { &mut self.0 } @@ -313,3 +314,16 @@ impl AsyncIterator for AssertUnwindSafe { self.0.size_hint() } } + +/// If a value's type is already `UnwindSafe`, +/// wrapping it in `AssertUnwindSafe` is never incorrect. +#[stable(feature = "from_wrapper_impls", since = "1.96.0")] +impl From for AssertUnwindSafe +where + T: UnwindSafe, +{ + #[inline(always)] + fn from(value: T) -> Self { + Self(value) + } +} diff --git a/library/core/src/panicking.rs b/library/core/src/panicking.rs index 3609dd1fe2e02..46790b620127b 100644 --- a/library/core/src/panicking.rs +++ b/library/core/src/panicking.rs @@ -305,6 +305,19 @@ fn panic_null_pointer_dereference() -> ! { ) } +#[cfg_attr(not(panic = "immediate-abort"), inline(never), cold, optimize(size))] +#[cfg_attr(panic = "immediate-abort", inline)] +#[track_caller] +#[lang = "panic_null_reference_constructed"] // needed by codegen for panic on null reference formation +#[rustc_nounwind] // `CheckNull` MIR pass requires this function to never unwind +fn panic_null_reference_constructed() -> ! { + if cfg!(panic = "immediate-abort") { + super::intrinsics::abort() + } + + panic_nounwind_fmt(format_args!("null reference produced"), /* force_no_backtrace */ false) +} + #[cfg_attr(not(panic = "immediate-abort"), inline(never), cold, optimize(size))] #[cfg_attr(panic = "immediate-abort", inline)] #[track_caller] diff --git a/library/core/src/pat.rs b/library/core/src/pat.rs index 50beb2ceb4b8a..d8ed9b5d50307 100644 --- a/library/core/src/pat.rs +++ b/library/core/src/pat.rs @@ -58,7 +58,7 @@ macro_rules! impl_range_pat { ($($ty:ty,)*) => { $( #[rustc_const_unstable(feature = "pattern_type_range_trait", issue = "123646")] - impl const RangePattern for $ty { + const impl RangePattern for $ty { const MIN: $ty = <$ty>::MIN; const MAX: $ty = <$ty>::MAX; fn sub_one(self) -> Self { @@ -81,7 +81,7 @@ impl_range_pat! { // verify that the `self as u32 -1` in the impl does not underflow. #[cfg_attr(flux, flux::assoc(fn sub_ok(self: char) -> bool { 0 < char_to_int(self)}))] #[rustc_const_unstable(feature = "pattern_type_range_trait", issue = "123646")] -impl const RangePattern for char { +const impl RangePattern for char { const MIN: Self = char::MIN; const MAX: Self = char::MAX; diff --git a/library/core/src/pin.rs b/library/core/src/pin.rs index c4981facc04c3..58e63ff04af15 100644 --- a/library/core/src/pin.rs +++ b/library/core/src/pin.rs @@ -474,9 +474,9 @@ //! //! In an intrusive doubly-linked list, the collection itself does not own the memory in which //! each of its elements is stored. Instead, each client is free to allocate space for elements it -//! adds to the list in whichever manner it likes, including on the stack! Elements can live on a -//! stack frame that lives shorter than the collection does provided the elements that live in a -//! given stack frame are removed from the list before going out of scope. +//! adds to the list in whichever manner it likes, including on the stack! Elements can be stored +//! in a stack frame shorter-lived than the collection, provided they are removed from the list +//! before that frame goes out of scope. //! //! To make such an intrusive data structure work, every element stores pointers to its predecessor //! and successor within its own data, rather than having the list structure itself managing those @@ -600,7 +600,7 @@ //! automatically called [`Pin::get_unchecked_mut`]. //! //! This can never cause a problem in purely safe code because creating a pinning pointer to -//! a type which has an address-sensitive (thus does not implement `Unpin`) requires `unsafe`, +//! a type which has address-sensitive states (and thus does not implement `Unpin`) requires `unsafe`, //! but it is important to note that choosing to take advantage of pinning-related guarantees //! to justify validity in the implementation of your type has consequences for that type's //! [`Drop`][Drop] implementation as well: if an element of your type could have been pinned, @@ -740,7 +740,7 @@ //! //! While counter-intuitive, it's often the easier choice: if you do not expose a //! [Pin]<[&mut] Field>, you do not need to be careful about other code -//! moving out of that field, you just have to ensure is that you never create pinning +//! moving out of that field, you just have to ensure that you never create a pinning //! reference to that field. This does of course also mean that if you decide a field does not //! have structural pinning, you must not write [`unsafe`] code that assumes (invalidly) that the //! field *is* structurally pinned! @@ -1080,9 +1080,8 @@ pub use self::unsafe_pinned::UnsafePinned; /// [subtle-details]: self#subtle-details-and-the-drop-guarantee "pin subtle details" /// [`unsafe`]: ../../std/keyword.unsafe.html "keyword unsafe" // -// Note: the `Clone` derive below causes unsoundness as it's possible to implement -// `Clone` for mutable references. -// See for more details. +// Note: the `Clone` derive below is sound because either `Ptr: PinSafePointer` +// or the pointee is `Unpin`. #[stable(feature = "pin", since = "1.33.0")] #[lang = "pin"] #[fundamental] @@ -1097,7 +1096,8 @@ pub struct Pin { // issues. `&self.pointer` should not be accessible to untrusted trait // implementations. // -// See for more details. +// See and the +// `PinSafePointer` trait for more details. #[stable(feature = "pin_trait_impls", since = "1.41.0")] impl PartialEq> for Pin @@ -1230,11 +1230,15 @@ impl Pin { /// points to is pinned, that is a violation of the API contract and may lead to undefined /// behavior in later (even safe) operations. /// - /// By using this method, you are also making a promise about the [`Deref`], - /// [`DerefMut`], and [`Drop`] implementations of `Ptr`, if they exist. Most importantly, they - /// must not move out of their `self` arguments: `Pin::as_mut` and `Pin::as_ref` - /// will call `DerefMut::deref_mut` and `Deref::deref` *on the pointer type `Ptr`* - /// and expect these methods to uphold the pinning invariants. + /// By using this method, you are also making a promise about several trait + /// implementations of `Ptr` itself, if they exist. Most importantly, they + /// must not move out of their `self` arguments: `Pin::as_mut` and + /// `Pin::as_ref` will call `DerefMut::deref_mut` and `Deref::deref` *on the + /// pointer type `Ptr`* and expect these methods to uphold the pinning + /// invariants. These requirements are specified in more detail on the + /// [`PinSafePointer`] trait, and `Ptr` must abide by the safety + /// requirements of that trait. + /// /// Moreover, by calling this method you promise that the reference `Ptr` /// dereferences to will not be moved out of again; in particular, it /// must not be possible to obtain a `&mut Ptr::Target` and then @@ -1536,7 +1540,7 @@ impl<'a, T: ?Sized> Pin<&'a T> { U: ?Sized, F: FnOnce(&T) -> &U, { - let pointer = &*self.pointer; + let pointer = self.pointer; let new_pointer = func(pointer); // SAFETY: the safety contract for `new_unchecked` must be @@ -1680,7 +1684,7 @@ impl Pin<&'static mut T> { #[stable(feature = "pin", since = "1.33.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Deref for Pin { +const impl Deref for Pin { type Target = Ptr::Target; fn deref(&self) -> &Ptr::Target { Pin::get_ref(Pin::as_ref(self)) @@ -1690,7 +1694,7 @@ impl const Deref for Pin { mod helper { /// Helper that prevents downstream crates from implementing `DerefMut` for `Pin`. /// - /// The `Pin` type implements the unsafe trait `PinCoerceUnsized`, which essentially requires + /// The `Pin` type implements the unsafe trait `PinSafePointer`, which essentially requires /// that the type does not have a malicious `Deref` or `DerefMut` impl. However, without this /// helper module, downstream crates are able to write `impl DerefMut for Pin` as /// long as it does not overlap with the impl provided by stdlib. This is because `Pin` is @@ -1723,7 +1727,7 @@ mod helper { #[unstable(feature = "pin_derefmut_internals", issue = "none")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] - impl const PinDerefMutHelper for PinHelper + const impl PinDerefMutHelper for PinHelper where Ptr::Target: crate::marker::Unpin, { @@ -1739,7 +1743,7 @@ mod helper { #[stable(feature = "pin", since = "1.33.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] #[cfg(not(doc))] -impl const DerefMut for Pin +const impl DerefMut for Pin where Ptr: [const] Deref, helper::PinHelper: [const] helper::PinDerefMutHelper, @@ -1765,7 +1769,7 @@ where #[stable(feature = "pin", since = "1.33.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] #[cfg(doc)] -impl const DerefMut for Pin +const impl DerefMut for Pin where Ptr: [const] DerefMut, ::Target: Unpin, @@ -1781,6 +1785,10 @@ unsafe impl DerefPure for Pin {} #[unstable(feature = "legacy_receiver_trait", issue = "none")] impl LegacyReceiver for Pin {} +// The following implementations allow untrusted trait implementations to access +// `&self.pointer`, which is only sound because these traits are mentioned in +// the safety requirements of `PinSafePointer`. + #[stable(feature = "pin", since = "1.33.0")] impl fmt::Debug for Pin { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { @@ -1810,54 +1818,157 @@ impl fmt::Pointer for Pin { #[stable(feature = "pin", since = "1.33.0")] impl CoerceUnsized> for Pin where - Ptr: CoerceUnsized + PinCoerceUnsized, - U: PinCoerceUnsized, + Ptr: CoerceUnsized + PinSafePointer, + U: PinSafePointer, { } #[stable(feature = "pin", since = "1.33.0")] impl DispatchFromDyn> for Pin where - Ptr: DispatchFromDyn + PinCoerceUnsized, - U: PinCoerceUnsized, + Ptr: DispatchFromDyn + PinSafePointer, + U: PinSafePointer, { } #[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -/// Trait that indicates that this is a pointer or a wrapper for one, where -/// unsizing can be performed on the pointee when it is pinned. +/// Trait that indicates that this is a pointer that does not misbehave when +/// combined with [`Pin`]. +/// +/// Note that for backwards compatibility reasons, it is possible to create a +/// [`Pin

`] for pointer types `P` that do not implement this trait. However, +/// this can only be done safely if `

::Target` implements `Unpin`, +/// which means that pinning has no effect. /// /// # Safety /// -/// If this type implements `Deref`, then the concrete type returned by `deref` -/// and `deref_mut` must not change without a modification. The following -/// operations are not considered modifications: +/// Types that implement this trait must not provide "malicious" implementations +/// of any safe traits used by [`Pin`]. /// -/// * Moving the pointer. -/// * Performing unsizing coercions on the pointer. -/// * Performing dynamic dispatch with the pointer. -/// * Calling `deref` or `deref_mut` on the pointer. +/// ## The pointer must always reference the same object /// -/// The concrete type of a trait object is the type that the vtable corresponds -/// to. The concrete type of a slice is an array of the same element type and -/// the length specified in the metadata. The concrete type of a sized type -/// is the type itself. -pub unsafe trait PinCoerceUnsized {} - -#[stable(feature = "pin", since = "1.33.0")] -unsafe impl<'a, T: ?Sized> PinCoerceUnsized for &'a T {} - -#[stable(feature = "pin", since = "1.33.0")] -unsafe impl<'a, T: ?Sized> PinCoerceUnsized for &'a mut T {} +/// Calls to [`deref`]/[`deref_mut`] on the same `Pin

` instance must always +/// refer to the same object. That is, the address returned by these methods +/// must not change. This applies even if the pointer type is moved. +/// +/// These coercions must also not change the underlying concrete type. Here, the +/// concrete type of a trait object is the type that the vtable corresponds to. +/// The concrete type of a slice is an array of the same element type and the +/// length specified in the metadata. The concrete type of a sized type is the +/// type itself. +/// +/// As an example, after unsizing coercing a pinned pointer, `deref_mut` must +/// not return a `#[repr(transparent)]` wrapper around the value it referenced +/// before being unsized, even if the address is unchanged. +/// +/// ## The pointer must not move its pointee +/// +/// The [`deref_mut`] method and the pointer type's destructor are called with a +/// `&mut self` receiver, but they must behave as-if it was a `self: Pin<&mut +/// Self>` receiver. That is, they must not move out of the underlying value. +/// +/// As an example, `deref_mut` must not invoke `swap` on the inner value. +/// +/// ## Shared access to the pointer +/// +/// If this pointer type uses `&P` references as evidence that this value is not +/// pinned, then it must not treat the `&self` argument passed to [`Clone`] or +/// the formatting traits ([`fmt::Debug`], [`fmt::Display`], [`fmt::Pointer`]) +/// as such evidence. +/// +/// As an example, given a `Pin>` there is no way to obtain an `&Arc` +/// (note that `Deref` just gives a `&T`). Because of this, the [`Arc`] type can +/// assume that an `&Arc` value can only exist if the `T` is not pinned, +/// which justifies the soundness of the [`Arc::get_mut`] method. +/// +/// ## Cloning pinned pointers +/// +/// When a [`Pin

`] is cloned, the `P` pointer value returned by `clone` is +/// passed to [`Pin::new_unchecked`]. The implementation of [`Clone`] must +/// return a value such that this is sound. +/// +/// For example, when a `Pin<&T>` is cloned, the resulting `&T` points at the +/// same value. The value is known to be pinned since a `Pin<&T>` to it exists, +/// so it is safe to wrap the `&T` returned by `clone` in `Pin`. +/// +/// [`deref`]: Deref::deref +/// [`deref_mut`]: DerefMut::deref_mut +/// [`clone`]: Clone::clone +/// [`Arc`]: ../../std/sync/struct.Arc.html "Arc" +/// [`Arc::get_mut`]: ../../std/sync/struct.Arc.html#method.get_mut "Arc::get_mut" +pub unsafe trait PinSafePointer: Deref + Sized {} +// A pointer can only be pin safe if it does not implement certain safe traits +// maliciously. Since `&T` is fundamental, downstream crates may be able to +// implement those traits for `&LocalType`, so we must carefully check that +// this is not a problem for each trait. +// +// The `&T` type always implements [`Deref`] and [`Clone`], so despite being +// fundamental, downstream crates cannot implement these traits for +// `&LocalType`. +// +// The `&T` type has a negative blanket implementations for [`DerefMut`], so +// downstream crates cannot implement `DerefMut` for `&LocalType`. +// +// Conversely, downstream crates are able to implement `Debug` and `Display` for +// `&LocalType` as long as `LocalType` does not implement said trait. However, +// the existence of an `&&T` cannot be treated as evidence that the `T` is not +// pinned, so this is not problematic. #[stable(feature = "pin", since = "1.33.0")] -unsafe impl PinCoerceUnsized for Pin {} +unsafe impl<'a, T: ?Sized> PinSafePointer for &'a T {} +// A pointer can only be pin safe if it does not implement certain safe traits +// maliciously. Since `&mut T` is fundamental, downstream crates may be able to +// implement those traits for `&mut LocalType`, so we must carefully check that +// this is not a problem for each trait. +// +// The `&mut T` type always implements [`Deref`] and [`DerefMut`], so despite +// being fundamental, downstream crates cannot implement these traits for `&mut +// LocalType`. +// +// The `&mut T` type has a negative blanket implementations for [`Clone`], so +// downstream crates cannot implement `Clone` for `&mut LocalType`. +// +// Conversely, downstream crates are able to implement `Debug` and `Display` +// for `&mut LocalType` as long as `LocalType` does not implement said trait. +// However, the existence of an `&&mut T` cannot be treated as evidence that the +// `T` is not pinned, so this is not problematic. #[stable(feature = "pin", since = "1.33.0")] -unsafe impl PinCoerceUnsized for *const T {} +unsafe impl<'a, T: ?Sized> PinSafePointer for &'a mut T {} +// A pointer can only be pin safe if it does not implement certain safe traits +// maliciously. `Pin` implements these traits by forwarding to `P`, which also +// asserts that these implementations are not malicious, so the implementations +// provided by `core` are ok. However, since `Pin` is fundamental, +// downstream crates may be able to implement those traits for `Pin` +// directly, so we must carefully check that if a downstream crate can +// implement these traits for `Pin`, then this does not lead to any +// problems for the `Pin>` type. +// +// The `Pin

` type only implements `Deref` when `P: Deref`, so downstream +// crates can implement `Deref` for `Pin` in cases where `LocalType: +// !Deref`. However, as `Deref` is a super-trait for `PinSafePointer`, we do +// not assert that `Pin

` is pin safe in that scenario. +// +// The `Pin

` type only implements `DerefMut` when `P: DerefMut` and +// `P::Target: Unpin`, so normally downstream crates would be able to provide +// an implementation of `DerefMut` for `Pin` when `LocalType` does +// not satisfy those conditions. However, a special hack is used to prevent +// such downstream implementations, so this is not a problem. See +// [#145608](https://github.com/rust-lang/rust/pull/145608) for details. +// +// Conversely, downstream crates are able to implement `Clone`, `Debug` and +// `Display` for `Pin` as long as `LocalType` does not implement +// said trait. However, the existence of an `&Pin

` cannot be treated as +// evidence that the value is not pinned, so this is not problematic. +// +// Furthermore, in the case of `Clone`, cloning a `Pin>` will utilize +// `Pin::new_unchecked` to convert from `Pin

` to `Pin>`. However, +// given that the implementation of `Clone` returned a `Pin

`, we know that +// the target value is pinned, so this conversion is okay even if `Clone` was +// implemented for `Pin

` by a downstream crate. #[stable(feature = "pin", since = "1.33.0")] -unsafe impl PinCoerceUnsized for *mut T {} +unsafe impl PinSafePointer for Pin

{} /// Constructs a [Pin]<[&mut] T>, by pinning a `value: T` locally. /// @@ -2026,14 +2137,82 @@ unsafe impl PinCoerceUnsized for *mut T {} /// [`Box::pin`]: ../../std/boxed/struct.Box.html#method.pin #[stable(feature = "pin_macro", since = "1.68.0")] #[rustc_macro_transparency = "semiopaque"] -#[allow_internal_unstable(super_let)] +#[allow_internal_unstable(pin_macro_internals, super_let)] #[rustc_diagnostic_item = "pin_macro"] // `super` gets removed by rustfmt #[rustfmt::skip] +#[diagnostic::opaque] pub macro pin($value:expr $(,)?) { { - super let mut pinned = $value; + super let mut pinned: $crate::pin::PinMacroHelper<_> = $crate::pin::PinMacroHelper { value: $value }; + // SAFETY: The value is pinned: it is the local above which cannot be named outside this macro. - unsafe { $crate::pin::Pin::new_unchecked(&mut pinned) } + // + // In order to make sure that the above local is passed to the below function call + // without any coercions in between, we wrap the user-provided value in the + // `PinMacroHelper` type, which we know doesn't implement `DerefMut`. Without such + // a wrapper, a user might cause a deref coercion on `&mut pinned`, causing the + // `Pin::new_unchecked` call to pin the wrong thing, which is unsound. + // See . + // + // To verify that there are no problematic coercions in the below line, we enumerate + // the list of all possible kinds of coercions that currently exist in the language, + // and verify that they can't be used to coerce a `&mut PinMacroHelper` into a + // `&mut PinMacroHelper` (as enforced by the above type annotation on `pinned`, + // and the type signature of `pin_new_unchecked_in_helper`), where `T` and `U` are + // different types: + // + // * Subtype coercions: `&mut` is invariant over the type being referenced, so subtype + // coercion can only change the lifetime of the `&mut` reference itself, which poses + // no problems. + // * Coercions that change the kind of references/pointers: We have the following kinds + // of coercions, none of which can produce a `&mut`: `&mut`-to-`&`, `*mut`-to-`*const`, + // `&`-to-`*const`, `&mut`-to-`*mut`. + // * Deref coercions: Does not apply here, since `PinMacroHelper` does not implement + // `Deref` or `DerefMut`. And since `PinMacroHelper` is not a fundamental type, users + // cannot add any such implementations to the type. + // * Unsize coercions: Does not apply here, since unsize coercions can only produce a + // reference/pointer to an unsized type, and `PinMacroHelper` is always `Sized`. + // * Coercions from function items or non-capturing closures to function pointers: + // Does not apply here. `&mut _` is not a function item or closure. + // * Never-to-any coercions: If this coercion applies, then we're in unreachable code, + // so whatever we do can't possibly cause unsoundness. + // + // Furthermore, if we ever add more kinds of coercions to the language, it seems + // extremely unlikely that user code would be allowed to define new coercions + // on a stdlib-defined type such as `PinMacroHelper`. + // + // I have not verified whether it is possible to cause a coercion in the `let` + // statement above, before assigning to the `pinned` variable. However, even if + // such a coercion were possible, it would not affect the soundness of the macro, + // since the soundness argument only relies on the type of `pinned` being + // `PinMacroHelper<_>`, which is enforced by the type annotation. + unsafe { $crate::pin::pin_new_unchecked_in_helper(&mut pinned) } } } + +/// Helper for `pin!` to enforce its type signature. +/// See . +#[unstable(feature = "pin_macro_internals", issue = "none")] +#[doc(hidden)] +#[expect(missing_debug_implementations, reason = "this type is only used by the `pin!` macro")] +#[rustc_diagnostic_item = "PinMacroHelper"] +pub struct PinMacroHelper { + pub value: T, +} + +/// Helper for `pin!` to enforce its type signature. +/// See . +/// +/// # Safety +/// Calling this function has the same safety requirements as calling +/// `Pin::new_unchecked` on `&mut pinned.value` +#[unstable(feature = "pin_macro_internals", issue = "none")] +#[doc(hidden)] +#[inline] +pub const unsafe fn pin_new_unchecked_in_helper<'a, T>( + pinned: &'a mut PinMacroHelper, +) -> Pin<&'a mut T> { + // SAFETY: Ensured by the caller. + unsafe { Pin::new_unchecked(&mut pinned.value) } +} diff --git a/library/core/src/pin/unsafe_pinned.rs b/library/core/src/pin/unsafe_pinned.rs index ae03809b4581f..83d9e9acedbf7 100644 --- a/library/core/src/pin/unsafe_pinned.rs +++ b/library/core/src/pin/unsafe_pinned.rs @@ -149,7 +149,7 @@ impl Default for UnsafePinned { #[unstable(feature = "unsafe_pinned", issue = "125735")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for UnsafePinned { +const impl From for UnsafePinned { /// Creates a new `UnsafePinned` containing the given value. fn from(value: T) -> Self { UnsafePinned::new(value) @@ -178,5 +178,3 @@ impl, U> CoerceUnsized> for UnsafePinned #[unstable(feature = "dispatch_from_dyn", issue = "none")] // #[unstable(feature = "unsafe_pinned", issue = "125735")] impl, U> DispatchFromDyn> for UnsafePinned {} - -// FIXME(unsafe_pinned): impl PinCoerceUnsized for UnsafePinned? diff --git a/library/core/src/prelude/v1.rs b/library/core/src/prelude/v1.rs index 354be271ff131..6122ab12ec351 100644 --- a/library/core/src/prelude/v1.rs +++ b/library/core/src/prelude/v1.rs @@ -80,7 +80,7 @@ mod ambiguous_macros_only { #[doc(no_inline)] pub use self::ambiguous_macros_only::{env, panic}; -#[unstable(feature = "cfg_select", issue = "115585")] +#[stable(feature = "cfg_select", since = "1.95.0")] #[doc(no_inline)] pub use crate::cfg_select; @@ -120,9 +120,13 @@ pub use crate::trace_macros; // (no public module for them to be re-exported from). #[stable(feature = "builtin_macro_prelude", since = "1.38.0")] pub use crate::macros::builtin::{ - alloc_error_handler, bench, derive, global_allocator, test, test_case, + alloc_error_handler, bench, global_allocator, test, test_case, }; +#[stable(feature = "builtin_macro_prelude", since = "1.38.0")] +#[doc(no_inline)] +pub use crate::macros::builtin::derive; + #[unstable(feature = "derive_const", issue = "118304")] pub use crate::macros::builtin::derive_const; diff --git a/library/core/src/primitive_docs.rs b/library/core/src/primitive_docs.rs index 3a4e1e657a3da..3e1596689e9d1 100644 --- a/library/core/src/primitive_docs.rs +++ b/library/core/src/primitive_docs.rs @@ -58,7 +58,7 @@ /// assert_eq!(false as i32, 0); /// ``` #[stable(feature = "rust1", since = "1.0.0")] -mod prim_bool {} +const _: () = (); #[rustc_doc_primitive = "never"] #[doc(alias = "!")] @@ -146,7 +146,7 @@ mod prim_bool {} /// /// ```ignore (hypothetical-example) /// loop { -/// let (client, request) = get_request().expect("disconnected"); +/// let (client, request) = get_request().expect("server should stay connected"); /// let response = request.process(); /// response.send(client); /// } @@ -312,7 +312,7 @@ mod prim_bool {} /// [2024 edition]: /// #[unstable(feature = "never_type", issue = "35121")] -mod prim_never {} +const _: () = (); // Required to make auto trait impls render. // See src/librustdoc/passes/collect_trait_impls.rs:collect_trait_impls @@ -448,7 +448,7 @@ impl ! {} /// assert_eq!(32, size_of_val(&v[..])); /// ``` #[stable(feature = "rust1", since = "1.0.0")] -mod prim_char {} +const _: () = (); #[rustc_doc_primitive = "unit"] #[doc(alias = "(")] @@ -489,7 +489,7 @@ mod prim_char {} /// ``` /// #[stable(feature = "rust1", since = "1.0.0")] -mod prim_unit {} +const _: () = (); // Required to make auto trait impls render. // See src/librustdoc/passes/collect_trait_impls.rs:collect_trait_impls @@ -616,7 +616,7 @@ impl () {} /// [`write`]: ptr::write /// [valid]: ptr#safety #[stable(feature = "rust1", since = "1.0.0")] -mod prim_pointer {} +const _: () = (); #[rustc_doc_primitive = "array"] #[doc(alias = "[]")] @@ -828,7 +828,7 @@ mod prim_pointer {} /// [slice pattern]: ../reference/patterns.html#slice-patterns /// [`From`]: convert::From #[stable(feature = "rust1", since = "1.0.0")] -mod prim_array {} +const _: () = (); #[rustc_doc_primitive = "slice"] #[doc(alias = "[")] @@ -942,7 +942,7 @@ mod prim_array {} /// [`.chunks`]: slice::chunks /// [`.windows`]: slice::windows #[stable(feature = "rust1", since = "1.0.0")] -mod prim_slice {} +const _: () = (); #[rustc_doc_primitive = "str"] /// String slices. @@ -1015,7 +1015,7 @@ mod prim_slice {} /// called on a string slice may assume that it is valid UTF-8, which means that a non-UTF-8 string /// slice can lead to undefined behavior down the road. #[stable(feature = "rust1", since = "1.0.0")] -mod prim_str {} +const _: () = (); #[rustc_doc_primitive = "tuple"] #[doc(alias = "(")] @@ -1142,7 +1142,7 @@ mod prim_str {} /// ``` /// #[stable(feature = "rust1", since = "1.0.0")] -mod prim_tuple {} +const _: () = (); // Required to make auto trait impls render. // See src/librustdoc/passes/collect_trait_impls.rs:collect_trait_impls @@ -1167,7 +1167,7 @@ impl (T,) {} /// /// [wikipedia]: https://en.wikipedia.org/wiki/Half-precision_floating-point_format #[unstable(feature = "f16", issue = "116909")] -mod prim_f16 {} +const _: () = (); #[rustc_doc_primitive = "f32"] #[doc(alias = "single")] @@ -1333,15 +1333,16 @@ mod prim_f16 {} /// such as NaN, +/-Inf, or -0.0 may behave in unexpected ways, but these operations /// will never cause undefined behavior. /// -/// Because of the unpredictable nature of compiler optimizations, the same inputs may produce -/// different results even within a single program run. **Unsafe code must not rely on any property -/// of the return value for soundness.** However, implementations will generally do their best to -/// pick a reasonable tradeoff between performance and accuracy of the result. +/// Algebraic operations are non-deterministic. This means that two invocations of such an operation +/// with the same inputs may produce different results even within a single program run. No +/// guarantees are made about the results of individual operations, except that they produce *some* +/// valid floating-point value. **Unsafe code must not rely on any property of the return value for +/// soundness.** However, implementations will generally do their best to pick a reasonable tradeoff +/// between performance and accuracy of the result. /// /// For example: /// /// ``` -/// # #![feature(float_algebraic)] /// # #![allow(unused_assignments)] /// # let mut x: f32 = 0.0; /// # let a: f32 = 1.0; @@ -1360,11 +1361,26 @@ mod prim_f16 {} /// # let b: f32 = 2.0; /// # let c: f32 = 3.0; /// # let d: f32 = 4.0; -/// x = a + b + c + d; // As written +/// x = ((a + b) + c) + d; // As written /// x = (a + c) + (b + d); // Reordered to shorten critical path and enable vectorization /// ``` +/// +/// The following example demonstrates the non-determinism: +/// +/// ``` +/// # #![allow(unused_assignments)] +/// # let a: f32 = 1.0; +/// # let b: f32 = 2.0; +/// let x1 = a.algebraic_add(b); +/// let x2 = a.algebraic_add(b); +/// assert_eq!(x1.to_bits(), x1.to_bits()); // this is guaranteed +/// # if false { +/// assert_eq!(x1.to_bits(), x2.to_bits()); // but this may fail +/// assert!(!x2.is_nan()); // this may also fail, even if there was no NaN input +/// # } +/// ``` #[stable(feature = "rust1", since = "1.0.0")] -mod prim_f32 {} +const _: () = (); #[rustc_doc_primitive = "f64"] #[doc(alias = "double")] @@ -1378,7 +1394,7 @@ mod prim_f32 {} /// /// [wikipedia]: https://en.wikipedia.org/wiki/Double-precision_floating-point_format #[stable(feature = "rust1", since = "1.0.0")] -mod prim_f64 {} +const _: () = (); #[rustc_doc_primitive = "f128"] #[doc(alias = "quad")] @@ -1401,31 +1417,31 @@ mod prim_f64 {} /// /// [wikipedia]: https://en.wikipedia.org/wiki/Quadruple-precision_floating-point_format #[unstable(feature = "f128", issue = "116909")] -mod prim_f128 {} +const _: () = (); #[rustc_doc_primitive = "i8"] // /// The 8-bit signed integer type. #[stable(feature = "rust1", since = "1.0.0")] -mod prim_i8 {} +const _: () = (); #[rustc_doc_primitive = "i16"] // /// The 16-bit signed integer type. #[stable(feature = "rust1", since = "1.0.0")] -mod prim_i16 {} +const _: () = (); #[rustc_doc_primitive = "i32"] // /// The 32-bit signed integer type. #[stable(feature = "rust1", since = "1.0.0")] -mod prim_i32 {} +const _: () = (); #[rustc_doc_primitive = "i64"] // /// The 64-bit signed integer type. #[stable(feature = "rust1", since = "1.0.0")] -mod prim_i64 {} +const _: () = (); #[rustc_doc_primitive = "i128"] // @@ -1443,31 +1459,31 @@ mod prim_i64 {} /// do not use the same alignment. `i128` is intended to always match `__int128` and does not /// attempt to match `_BitInt(128)` on platforms without `__int128`. #[stable(feature = "i128", since = "1.26.0")] -mod prim_i128 {} +const _: () = (); #[rustc_doc_primitive = "u8"] // /// The 8-bit unsigned integer type. #[stable(feature = "rust1", since = "1.0.0")] -mod prim_u8 {} +const _: () = (); #[rustc_doc_primitive = "u16"] // /// The 16-bit unsigned integer type. #[stable(feature = "rust1", since = "1.0.0")] -mod prim_u16 {} +const _: () = (); #[rustc_doc_primitive = "u32"] // /// The 32-bit unsigned integer type. #[stable(feature = "rust1", since = "1.0.0")] -mod prim_u32 {} +const _: () = (); #[rustc_doc_primitive = "u64"] // /// The 64-bit unsigned integer type. #[stable(feature = "rust1", since = "1.0.0")] -mod prim_u64 {} +const _: () = (); #[rustc_doc_primitive = "u128"] // @@ -1475,7 +1491,7 @@ mod prim_u64 {} /// /// Please see [the documentation for `i128`](prim@i128) for information on ABI compatibility. #[stable(feature = "i128", since = "1.26.0")] -mod prim_u128 {} +const _: () = (); #[rustc_doc_primitive = "isize"] // @@ -1485,7 +1501,7 @@ mod prim_u128 {} /// location in memory. For example, on a 32 bit target, this is 4 bytes /// and on a 64 bit target, this is 8 bytes. #[stable(feature = "rust1", since = "1.0.0")] -mod prim_isize {} +const _: () = (); #[rustc_doc_primitive = "usize"] // @@ -1495,7 +1511,7 @@ mod prim_isize {} /// location in memory. For example, on a 32 bit target, this is 4 bytes /// and on a 64 bit target, this is 8 bytes. #[stable(feature = "rust1", since = "1.0.0")] -mod prim_usize {} +const _: () = (); #[rustc_doc_primitive = "reference"] #[doc(alias = "&")] @@ -1656,7 +1672,7 @@ mod prim_usize {} /// /// [allocation]: ptr#allocation #[stable(feature = "rust1", since = "1.0.0")] -mod prim_ref {} +const _: () = (); #[rustc_doc_primitive = "fn"] // @@ -1777,7 +1793,7 @@ mod prim_ref {} /// However, a direct cast back is not possible. You need to use `transmute`: /// /// ```rust -/// # #[cfg(not(miri))] { // FIXME: use strict provenance APIs once they are stable, then remove this `cfg` +/// # #[cfg(not(miri))] { // disabled because it fails with -Zmiri-strict-provenance /// # let fnptr: fn(i32) -> i32 = |x| x+2; /// # let fnptr_addr = fnptr as usize; /// let fnptr = fnptr_addr as *const (); @@ -1794,6 +1810,7 @@ mod prim_ref {} /// have different sizes. /// /// ### ABI compatibility +/// [ABI compatibility]: #abi-compatibility /// /// Generally, when a function is declared with one signature and called via a function pointer with /// a different signature, the two signatures must be *ABI-compatible* or else calling the function @@ -1831,7 +1848,7 @@ mod prim_ref {} /// - `*const T`, `*mut T`, `&T`, `&mut T`, `Box` (specifically, only `Box`), and /// `NonNull` are all ABI-compatible with each other for all `T`. They are also ABI-compatible /// with each other for _different_ `T` if they have the same metadata type (`::Metadata`). +/// Pointee>::Metadata`). However, see the [Control Flow Integrity][cfi-docs] docs for caveats. /// - `usize` is ABI-compatible with the `uN` integer type of the same size, and likewise `isize` is /// ABI-compatible with the `iN` integer type of the same size. /// - `char` is ABI-compatible with `u32`. @@ -1890,6 +1907,8 @@ mod prim_ref {} /// Behavior since transmuting `None::>` to `NonZero` violates the non-zero /// requirement. /// +/// [cfi-docs]: https://doc.rust-lang.org/beta/unstable-book/compiler-flags/sanitizer.html#controlflowintegrity +/// /// ### Trait implementations /// /// In this documentation the shorthand `fn(T₁, T₂, …, Tₙ)` is used to represent non-variadic @@ -1928,7 +1947,7 @@ mod prim_ref {} /// In addition, all *safe* function pointers implement [`Fn`], [`FnMut`], and [`FnOnce`], because /// these traits are specially known to the compiler. #[stable(feature = "rust1", since = "1.0.0")] -mod prim_fn {} +const _: () = (); // Required to make auto trait impls render. // See src/librustdoc/passes/collect_trait_impls.rs:collect_trait_impls diff --git a/library/core/src/process.rs b/library/core/src/process.rs new file mode 100644 index 0000000000000..81481b2cba26e --- /dev/null +++ b/library/core/src/process.rs @@ -0,0 +1,43 @@ +//! A module for working with processes. +//! +//! Most process-related functionality requires std, but [`abort_immediate`] +//! is available on all targets. + +/// Terminates the process in a violent fashion. +/// +/// The function will never return and will immediately terminate the current +/// process in a platform specific "abnormal" manner. As a consequence, +/// no destructors on the current stack or any other thread's stack +/// will be run, Rust IO buffers (eg, from `BufWriter`) will not be flushed, +/// and C stdio buffers will not be flushed. +/// +/// Unlike [`abort`](../../std/process/fn.abort.html), `abort_immediate` does +/// not attempt to match C `abort()` or otherwise perform a "clean" abort. +/// Instead, it emits code that will crash the process with as little overhead +/// as possible, such as a "halt and catch fire" style instruction. You should +/// generally prefer using `abort` instead except where the absolute minimum +/// overhead is required. +/// +/// # Platform-specific behavior +/// +/// `abort_immediate` lowers to a trap instruction on *most* architectures; on +/// some architectures it simply lowers to call the unmangled `abort` function. +/// The exact behavior is architecture and system dependent. +/// +/// On bare-metal (no OS) systems the trap instruction usually causes a +/// *hardware* exception to be raised in a *synchronous* fashion; hardware +/// exceptions have nothing to do with C++ exceptions and are closer in +/// semantics to POSIX signals. +/// +/// On hosted applications (applications running under an OS), the trap +/// instruction *usually* terminates the whole process with an exit code that +/// corresponds to `SIGILL` or equivalent, *unless* this signal is handled. +/// Other signals such as `SIGABRT`, `SIGTRAP`, `SIGSEGV`, and `SIGBUS` may be +/// produced instead, depending on specifics. This is not an exhaustive list. +#[unstable(feature = "abort_immediate", issue = "154601")] +#[cold] +#[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces +#[doc(alias = "halt")] +pub fn abort_immediate() -> ! { + crate::intrinsics::abort() +} diff --git a/library/core/src/ptr/const_ptr.rs b/library/core/src/ptr/const_ptr.rs index a51e1a4fc2981..2e79ed7d696fa 100644 --- a/library/core/src/ptr/const_ptr.rs +++ b/library/core/src/ptr/const_ptr.rs @@ -187,6 +187,7 @@ impl *const T { /// [`with_exposed_provenance`]: with_exposed_provenance #[inline(always)] #[stable(feature = "exposed_provenance", since = "1.84.0")] + #[expect(implicit_provenance_casts, reason = "this *is* the replacement")] pub fn expose_provenance(self) -> usize { self.cast::<()>() as usize } @@ -294,8 +295,8 @@ impl *const T { /// assert_eq!(ptr.as_ref_unchecked(), &10); /// } /// ``` - #[stable(feature = "ptr_as_ref_unchecked", since = "CURRENT_RUSTC_VERSION")] - #[rustc_const_stable(feature = "ptr_as_ref_unchecked", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "ptr_as_ref_unchecked", since = "1.95.0")] + #[rustc_const_stable(feature = "ptr_as_ref_unchecked", since = "1.95.0")] #[inline] #[must_use] pub const unsafe fn as_ref_unchecked<'a>(self) -> &'a T { @@ -334,6 +335,10 @@ impl *const T { #[doc = include_str!("./docs/offset.md")] /// + /// Consider using [`wrapping_offset`](#method.wrapping_offset) instead if these constraints are + /// difficult to satisfy. The only advantage of this method is that it + /// enables more aggressive compiler optimizations. + /// /// # Examples /// /// ``` @@ -589,9 +594,8 @@ impl *const T { /// needed for `const`-compatibility: the distance between pointers into *different* allocated /// objects is not known at compile-time. However, the requirement also exists at /// runtime and may be exploited by optimizations. If you wish to compute the difference between - /// pointers that are not guaranteed to be from the same allocation, use `(self as isize - - /// origin as isize) / size_of::()`. - // FIXME: recommend `addr()` instead of `as usize` once that is stable. + /// pointers that are not guaranteed to be from the same allocation, use + /// `(self.addr() as isize - origin.addr() as isize) / size_of::()`. /// /// [`add`]: #method.add /// [allocation]: crate::ptr#allocation @@ -634,7 +638,7 @@ impl *const T { /// ``` #[stable(feature = "ptr_offset_from", since = "1.47.0")] #[rustc_const_stable(feature = "const_ptr_offset_from", since = "1.65.0")] - #[inline] + #[inline(always)] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[requires( // Ensures subtracting `origin` from `self` doesn't overflow @@ -857,6 +861,10 @@ impl *const T { #[doc = include_str!("./docs/add.md")] /// + /// Consider using [`wrapping_add`](#method.wrapping_add) instead if these constraints are + /// difficult to satisfy. The only advantage of this method is that it + /// enables more aggressive compiler optimizations. + /// /// # Examples /// /// ``` @@ -962,39 +970,12 @@ impl *const T { unsafe { self.cast::().add(count).with_metadata_of(self) } } - /// Subtracts an unsigned offset from a pointer. - /// - /// This can only move the pointer backward (or not move it). If you need to move forward or - /// backward depending on the value, then you might want [`offset`](#method.offset) instead - /// which takes a signed offset. - /// - /// `count` is in units of T; e.g., a `count` of 3 represents a pointer - /// offset of `3 * size_of::()` bytes. - /// - /// # Safety - /// - /// If any of the following conditions are violated, the result is Undefined Behavior: - /// - /// * The offset in bytes, `count * size_of::()`, computed on mathematical integers (without - /// "wrapping around"), must fit in an `isize`. + #[doc = include_str!("./docs/sub.md")] /// - /// * If the computed offset is non-zero, then `self` must be [derived from][crate::ptr#provenance] a pointer to some - /// [allocation], and the entire memory range between `self` and the result must be in - /// bounds of that allocation. In particular, this range must not "wrap around" the edge - /// of the address space. - /// - /// Allocations can never be larger than `isize::MAX` bytes, so if the computed offset - /// stays in bounds of the allocation, it is guaranteed to satisfy the first requirement. - /// This implies, for instance, that `vec.as_ptr().add(vec.len())` (for `vec: Vec`) is always - /// safe. - /// - /// Consider using [`wrapping_sub`] instead if these constraints are + /// Consider using [`wrapping_sub`](#method.wrapping_sub) instead if these constraints are /// difficult to satisfy. The only advantage of this method is that it /// enables more aggressive compiler optimizations. /// - /// [`wrapping_sub`]: #method.wrapping_sub - /// [allocation]: crate::ptr#allocation - /// /// # Examples /// /// ``` @@ -1160,6 +1141,7 @@ impl *const T { #[stable(feature = "pointer_methods", since = "1.26.0")] #[must_use = "returns a new pointer rather than modifying its argument"] #[rustc_const_stable(feature = "const_ptr_offset", since = "1.61.0")] + #[allow(clippy::ptr_offset_with_cast)] #[inline(always)] pub const fn wrapping_add(self, count: usize) -> Self where @@ -1272,7 +1254,7 @@ impl *const T { /// [`ptr::read`]: crate::ptr::read() #[stable(feature = "pointer_methods", since = "1.26.0")] #[rustc_const_stable(feature = "const_ptr_read", since = "1.71.0")] - #[inline] + #[inline(always)] #[track_caller] pub const unsafe fn read(self) -> T where @@ -1293,9 +1275,10 @@ impl *const T { /// /// [`ptr::read_volatile`]: crate::ptr::read_volatile() #[stable(feature = "pointer_methods", since = "1.26.0")] - #[inline] + #[rustc_const_unstable(feature = "const_volatile", issue = "159094")] + #[inline(always)] #[track_caller] - pub unsafe fn read_volatile(self) -> T + pub const unsafe fn read_volatile(self) -> T where T: Sized, { @@ -1313,7 +1296,7 @@ impl *const T { /// [`ptr::read_unaligned`]: crate::ptr::read_unaligned() #[stable(feature = "pointer_methods", since = "1.26.0")] #[rustc_const_stable(feature = "const_ptr_read", since = "1.71.0")] - #[inline] + #[inline(always)] #[track_caller] pub const unsafe fn read_unaligned(self) -> T where @@ -1333,7 +1316,7 @@ impl *const T { /// [`ptr::copy`]: crate::ptr::copy() #[rustc_const_stable(feature = "const_intrinsic_copy", since = "1.83.0")] #[stable(feature = "pointer_methods", since = "1.26.0")] - #[inline] + #[inline(always)] #[track_caller] pub const unsafe fn copy_to(self, dest: *mut T, count: usize) where @@ -1353,7 +1336,7 @@ impl *const T { /// [`ptr::copy_nonoverlapping`]: crate::ptr::copy_nonoverlapping() #[rustc_const_stable(feature = "const_intrinsic_copy", since = "1.83.0")] #[stable(feature = "pointer_methods", since = "1.26.0")] - #[inline] + #[inline(always)] #[track_caller] pub const unsafe fn copy_to_nonoverlapping(self, dest: *mut T, count: usize) where @@ -1511,11 +1494,11 @@ impl *const T { /// /// ```rust /// #![feature(ptr_cast_slice)] + /// /// // create a slice pointer when starting out with a pointer to the first element /// let x = [5, 6, 7]; - /// let raw_pointer = x.as_ptr(); - /// let slice = raw_pointer.cast_slice(3); - /// assert_eq!(unsafe { &*slice }[2], 7); + /// let raw_slice = x.as_ptr().cast_slice(3); + /// assert_eq!(unsafe { &*raw_slice }[2], 7); /// ``` /// /// You must ensure that the pointer is valid and not null before dereferencing @@ -1564,7 +1547,7 @@ impl *const [T] { /// let slice: *const [i8] = ptr::slice_from_raw_parts(ptr::null(), 3); /// assert_eq!(slice.len(), 3); /// ``` - #[inline] + #[inline(always)] #[stable(feature = "slice_ptr_len", since = "1.79.0")] #[rustc_const_stable(feature = "const_slice_ptr_len", since = "1.79.0")] pub const fn len(self) -> usize { @@ -1601,7 +1584,7 @@ impl *const [T] { /// let slice: *const [i8] = ptr::slice_from_raw_parts(ptr::null(), 3); /// assert_eq!(slice.as_ptr(), ptr::null()); /// ``` - #[inline] + #[inline(always)] #[unstable(feature = "slice_ptr_get", issue = "74265")] pub const fn as_ptr(self) -> *const T { self as *const T @@ -1626,9 +1609,10 @@ impl *const [T] { /// Returns a raw pointer to an element or subslice, without doing bounds /// checking. /// - /// Calling this method with an out-of-bounds index or when `self` is not dereferenceable + /// Calling this method with an [out-of-bounds index] or when `self` is not dereferenceable /// is *[undefined behavior]* even if the resulting pointer is not used. /// + /// [out-of-bounds index]: #method.add /// [undefined behavior]: https://doc.rust-lang.org/reference/behavior-considered-undefined.html /// /// # Examples @@ -1644,7 +1628,7 @@ impl *const [T] { /// ``` #[unstable(feature = "slice_ptr_get", issue = "74265")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] - #[inline] + #[inline(always)] pub const unsafe fn get_unchecked(self, index: I) -> *const I::Output where I: [const] SliceIndex<[T]>, @@ -1689,7 +1673,7 @@ impl *const [T; N] { /// let arr: *const [i8; 3] = ptr::null(); /// assert_eq!(arr.as_ptr(), ptr::null()); /// ``` - #[inline] + #[inline(always)] #[unstable(feature = "array_ptr_get", issue = "119834")] pub const fn as_ptr(self) -> *const T { self as *const T @@ -1720,7 +1704,7 @@ impl *const [T; N] { note = "see issue #53020 for more information" )] impl PartialEq for *const T { - #[inline] + #[inline(always)] #[allow(ambiguous_wide_pointer_comparisons)] fn eq(&self, other: &*const T) -> bool { *self == *other @@ -1762,31 +1746,31 @@ impl Ord for *const T { note = "see issue #53020 for more information" )] impl PartialOrd for *const T { - #[inline] + #[inline(always)] #[allow(ambiguous_wide_pointer_comparisons)] fn partial_cmp(&self, other: &*const T) -> Option { Some(self.cmp(other)) } - #[inline] + #[inline(always)] #[allow(ambiguous_wide_pointer_comparisons)] fn lt(&self, other: &*const T) -> bool { *self < *other } - #[inline] + #[inline(always)] #[allow(ambiguous_wide_pointer_comparisons)] fn le(&self, other: &*const T) -> bool { *self <= *other } - #[inline] + #[inline(always)] #[allow(ambiguous_wide_pointer_comparisons)] fn gt(&self, other: &*const T) -> bool { *self > *other } - #[inline] + #[inline(always)] #[allow(ambiguous_wide_pointer_comparisons)] fn ge(&self, other: &*const T) -> bool { *self >= *other diff --git a/library/core/src/ptr/docs/add.md b/library/core/src/ptr/docs/add.md index 6e2e87f5f811b..807ebee6db1c8 100644 --- a/library/core/src/ptr/docs/add.md +++ b/library/core/src/ptr/docs/add.md @@ -14,19 +14,15 @@ If any of the following conditions are violated, the result is Undefined Behavio * The offset in bytes, `count * size_of::()`, computed on mathematical integers (without "wrapping around"), must fit in an `isize`. -* If the computed offset is non-zero, then `self` must be [derived from][crate::ptr#provenance] a pointer to some -[allocation], and the entire memory range between `self` and the result must be in -bounds of that allocation. In particular, this range must not "wrap around" the edge -of the address space. +* Let `result` be `self.addr() + count * size_of::()`, computed on mathematical integers. +This must fit in a `usize`. -Allocations can never be larger than `isize::MAX` bytes, so if the computed offset -stays in bounds of the allocation, it is guaranteed to satisfy the first requirement. -This implies, for instance, that `vec.as_ptr().add(vec.len())` (for `vec: Vec`) is always -safe. +* If the computed offset is non-zero, then `self` must be [derived from][crate::ptr#provenance] a pointer to some +[allocation], and the entire memory range between `self` and `result` +(i.e., `self.addr()..result`) must be in bounds of that allocation. -Consider using [`wrapping_add`] instead if these constraints are -difficult to satisfy. The only advantage of this method is that it -enables more aggressive compiler optimizations. +Allocations can never be larger than `isize::MAX` bytes and they can only contain addresses +representable by `usize`, so technically the last condition implies the first two. This implies, for +instance, that `vec.as_ptr().add(vec.len())` (for `vec: Vec`) is always safe. -[`wrapping_add`]: #method.wrapping_add [allocation]: crate::ptr#allocation diff --git a/library/core/src/ptr/docs/as_ref.md b/library/core/src/ptr/docs/as_ref.md index 2c7d6e149b76a..4b41031198236 100644 --- a/library/core/src/ptr/docs/as_ref.md +++ b/library/core/src/ptr/docs/as_ref.md @@ -16,4 +16,4 @@ determined to be null or not. See [`is_null`] for more information. # Null-unchecked version If you are sure the pointer can never be null, you can use `as_ref_unchecked` which returns -`&mut T` instead of `Option<&mut T>`. +`&T` instead of `Option<&T>`. diff --git a/library/core/src/ptr/docs/as_uninit_slice.md b/library/core/src/ptr/docs/as_uninit_slice.md index 1113f4748c2df..a2402b020468f 100644 --- a/library/core/src/ptr/docs/as_uninit_slice.md +++ b/library/core/src/ptr/docs/as_uninit_slice.md @@ -7,7 +7,7 @@ that the value has to be initialized. # Safety When calling this method, you have to ensure that *either* the pointer is null *or* -all of the following is true: +all of the following are true: * The pointer must be [valid] for reads for `ptr.len() * size_of::()` many bytes, and it must be properly aligned. This means in particular: diff --git a/library/core/src/ptr/docs/offset.md b/library/core/src/ptr/docs/offset.md index f04f5606ab297..b1add36d37735 100644 --- a/library/core/src/ptr/docs/offset.md +++ b/library/core/src/ptr/docs/offset.md @@ -10,20 +10,16 @@ If any of the following conditions are violated, the result is Undefined Behavio * The offset in bytes, `count * size_of::()`, computed on mathematical integers (without "wrapping around"), must fit in an `isize`. -* If the computed offset is non-zero, then `self` must be [derived from][crate::ptr#provenance] a pointer to some -[allocation], and the entire memory range between `self` and the result must be in -bounds of that allocation. In particular, this range must not "wrap around" the edge -of the address space. Note that "range" here refers to a half-open range as usual in Rust, -i.e., `self..result` for non-negative offsets and `result..self` for negative offsets. +* Let `result` be `self.addr() + count * size_of::()`, computed on mathematical integers. +This must fit in a `usize`. -Allocations can never be larger than `isize::MAX` bytes, so if the computed offset -stays in bounds of the allocation, it is guaranteed to satisfy the first requirement. -This implies, for instance, that `vec.as_ptr().add(vec.len())` (for `vec: Vec`) is always -safe. +* If the computed offset is non-zero, then `self` must be [derived from][crate::ptr#provenance] a pointer to some +[allocation], and the entire memory range between `self` and `result` +(i.e., `min(self.addr(), result)..max(self.addr(), result)`) +must be in bounds of that allocation. -Consider using [`wrapping_offset`] instead if these constraints are -difficult to satisfy. The only advantage of this method is that it -enables more aggressive compiler optimizations. +Allocations can never be larger than `isize::MAX` bytes and they can only contain addresses +representable by `usize`, so technically the last condition implies the first two. This implies, for +instance, that `vec.as_ptr().offset(vec.len() as isize)` (for `vec: Vec`) is always safe. -[`wrapping_offset`]: #method.wrapping_offset [allocation]: crate::ptr#allocation diff --git a/library/core/src/ptr/docs/sub.md b/library/core/src/ptr/docs/sub.md new file mode 100644 index 0000000000000..b8873b0cf3631 --- /dev/null +++ b/library/core/src/ptr/docs/sub.md @@ -0,0 +1,27 @@ +Subtracts an unsigned offset from a pointer. + +This can only move the pointer backward (or not move it). If you need to move forward or +backward depending on the value, then you might want [`offset`](#method.offset) instead +which takes a signed offset. + +`count` is in units of T; e.g., a `count` of 3 represents a pointer +offset of `3 * size_of::()` bytes. + +# Safety + +If any of the following conditions are violated, the result is Undefined Behavior: + +* The offset in bytes, `count * size_of::()`, computed on mathematical integers (without + "wrapping around"), must fit in an `isize`. + +* Let `result` be `self.addr() - count * size_of::()`, computed on mathematical integers. +This must fit in a `usize`. + +* If the computed offset is non-zero, then `self` must be [derived from][crate::ptr#provenance] a pointer to some +[allocation], and the entire memory range between `self` and `result` +(i.e., `result..self.addr()`) must be in bounds of that allocation. + +Allocations can never be larger than `isize::MAX` bytes and they can only contain addresses +representable by `usize`, so technically the last condition implies the first two. + +[allocation]: crate::ptr#allocation diff --git a/library/core/src/ptr/mod.rs b/library/core/src/ptr/mod.rs index 50d2396728ee4..73e779bac1171 100644 --- a/library/core/src/ptr/mod.rs +++ b/library/core/src/ptr/mod.rs @@ -15,22 +15,19 @@ //! The precise rules for validity are not determined yet. The guarantees that are //! provided at this point are very minimal: //! -//! * For memory accesses of [size zero][zst], *every* pointer is valid, including the [null] -//! pointer. The following points are only concerned with non-zero-sized accesses. -//! * A [null] pointer is *never* valid. -//! * For a pointer to be valid, it is necessary, but not always sufficient, that the pointer be -//! *dereferenceable*. The [provenance] of the pointer is used to determine which [allocation] -//! it is derived from; a pointer is dereferenceable if the memory range of the given size -//! starting at the pointer is entirely contained within the bounds of that allocation. Note +//! * A [null] pointer is *never* valid for reads/writes. +//! * For memory accesses of [size zero][zst], *every* non-null pointer is valid for reads/writes. +//! The following points are only concerned with non-zero-sized accesses. +//! * For a pointer to be valid for reads/writes, it is necessary, but not always sufficient, that +//! the pointer be *dereferenceable*. The [provenance] of the pointer is used to determine which +//! [allocation] it is derived from; a pointer is dereferenceable if the memory range of the given +//! size starting at the pointer is entirely contained within the bounds of that allocation. Note //! that in Rust, every (stack-allocated) variable is considered a separate allocation. //! * All accesses performed by functions in this module are *non-atomic* in the sense //! of [atomic operations] used to synchronize between threads. This means it is //! undefined behavior to perform two concurrent accesses to the same location from different -//! threads unless both accesses only read from memory. Notice that this explicitly -//! includes [`read_volatile`] and [`write_volatile`]: Volatile accesses cannot -//! be used for inter-thread synchronization, regardless of whether they are acting on -//! Rust memory or not. -//! * The result of casting a reference to a pointer is valid for as long as the +//! threads unless both accesses only read from memory. +//! * The result of casting a reference to a pointer is valid for reads/writes for as long as the //! underlying allocation is live and no reference (just raw pointers) is used to //! access the same memory. That is, reference and pointer accesses cannot be //! interleaved. @@ -41,6 +38,13 @@ //! information, see the [book] as well as the section in the reference devoted //! to [undefined behavior][ub]. //! +//! Note that some operations such as [`read`] and [`write`][`write()`] do allow null pointers if +//! the total size of the access is zero. However, other operations internally convert pointers into +//! references. Therefore, the general notion of "valid for reads/writes" excludes null pointers, +//! and the specific operations that permit null pointers mention that as an exception. Furthermore, +//! [`read_volatile`] and [`write_volatile`] can be used in even more situations; see their +//! documentation for details. +//! //! We say that a pointer is "dangling" if it is not valid for any non-zero-sized accesses. This //! means out-of-bounds pointers, pointers to freed memory, null pointers, and pointers created with //! [`NonNull::dangling`] are all dangling. @@ -115,9 +119,26 @@ //! fully contiguous (i.e., has no "holes"), there is no guarantee that this //! will not change in the future. //! +//! An allocation can be either mutable (the common case) or *read-only*. +//! Read-only allocations are implicitly introduced by the compiler for `static` items without +//! interior mutability and for `const` items. Writing or creating a mutable reference to a +//! read-only allocation is undefined behavior, and most atomic operations are not supported +//! for read-only allocations either (see [here][atomic-ro] for exceptions). +//! Additionally, some target-specific intrinsics are not supported on read-only +//! allocations even if their memory write is masked off, such as [`_mm_maskmoveu_si128`]. +//! +//! [atomic-ro]: crate::sync::atomic#atomic-accesses-to-read-only-memory +//! [`_mm_maskmoveu_si128`]: ../../core/arch/x86/fn._mm_maskmoveu_si128.html +//! //! Allocations must behave like "normal" memory: in particular, reads must not have //! side-effects, and writes must become visible to other threads using the usual synchronization //! primitives. +//! Allocations must support all atomic operations that are available for the target (as +//! determined by the `target_has_atomic*` set of cfg flags). +//! Read-only allocations only have to support the operations [permitted there][atomic-ro]. +//! The precise instructions used for atomic operations are generally not guaranteed, so portable +//! software should place all Rust allocations in memory regions that support all atomic +//! instructions. //! //! For any allocation with `base` address, `size`, and a set of //! `addresses`, the following are guaranteed: @@ -136,6 +157,13 @@ //! the allocation), `base + o` will not wrap around the address space (in //! other words, will not overflow `usize`) //! +//! Allocations typically have a fixed size that cannot change. However, allocations created by +//! directly invoking page table operations of the operating system, e.g. via `mmap`, are allowed to +//! grow by adding more pages to them at the end. Unmapping parts of an allocation (i.e., shrinking +//! it or punching holes into it) is currently not supported. Allocations created via +//! "compiler-recognized" operations, such as `std::alloc` methods or `libc::malloc`, can never +//! change their size, even if they use `mmap` under the hood. +//! //! [`null()`]: null //! //! # Provenance @@ -258,16 +286,15 @@ //! [`with_addr`] method: //! //! ```text -//! /// Creates a new pointer with the given address. -//! /// -//! /// This performs the same operation as an `addr as ptr` cast, but copies -//! /// the *provenance* of `self` to the new pointer. -//! /// This allows us to dynamically preserve and propagate this important -//! /// information in a way that is otherwise impossible with a unary cast. -//! /// -//! /// This is equivalent to using `wrapping_offset` to offset `self` to the -//! /// given address, and therefore has all the same capabilities and restrictions. -//! pub fn with_addr(self, addr: usize) -> Self; +//! /// Creates a new pointer with the given address and the provenance of `self`. +//! /// +//! /// This is similar to a `addr as *const T` cast, +//! /// but copies the provenance of `self` to the new pointer. +//! /// This avoids the inherent ambiguity of the unary cast. +//! /// +//! /// This is equivalent to using `wrapping_offset` to offset `self` to the given address, +//! /// and therefore has all the same capabilities and restrictions. +//! pub fn with_addr(self, addr: usize) -> Self; //! ``` //! //! So you're still able to drop down to the address representation and do whatever @@ -297,27 +324,25 @@ //! represent the tagged pointer as an actual pointer and not a `usize`*. For instance: //! //! ``` -//! unsafe { -//! // A flag we want to pack into our pointer -//! static HAS_DATA: usize = 0x1; -//! static FLAG_MASK: usize = !HAS_DATA; -//! -//! // Our value, which must have enough alignment to have spare least-significant-bits. -//! let my_precious_data: u32 = 17; -//! assert!(align_of::() > 1); -//! -//! // Create a tagged pointer -//! let ptr = &my_precious_data as *const u32; -//! let tagged = ptr.map_addr(|addr| addr | HAS_DATA); -//! -//! // Check the flag: -//! if tagged.addr() & HAS_DATA != 0 { -//! // Untag and read the pointer -//! let data = *tagged.map_addr(|addr| addr & FLAG_MASK); -//! assert_eq!(data, 17); -//! } else { -//! unreachable!() -//! } +//! // A flag we want to pack into our pointer +//! static HAS_DATA: usize = 0x1; +//! static FLAG_MASK: usize = !HAS_DATA; +//! +//! // Our value, which must have enough alignment to have spare least-significant-bits. +//! let my_precious_data: u32 = 17; +//! assert!(align_of::() > 1); +//! +//! // Create a tagged pointer +//! let ptr = &my_precious_data as *const u32; +//! let tagged = ptr.map_addr(|addr| addr | HAS_DATA); +//! +//! // Check the flag: +//! if tagged.addr() & HAS_DATA != 0 { +//! // Untag and read the pointer +//! let data = unsafe { *tagged.map_addr(|addr| addr & FLAG_MASK) }; +//! assert_eq!(data, 17); +//! } else { +//! unreachable!() //! } //! ``` //! @@ -405,14 +430,16 @@ use crate::cmp::Ordering; use crate::intrinsics::const_eval_select; #[cfg(kani)] use crate::kani; -use crate::marker::{Destruct, FnPtr, PointeeSized}; +use crate::marker::{Destruct, PointeeSized}; use crate::mem::{self, MaybeUninit, SizedTypeProperties}; use crate::num::NonZero; +use crate::ops::FnPtr; use crate::{fmt, hash, intrinsics, ub_checks}; -mod alignment; #[unstable(feature = "ptr_alignment_type", issue = "102070")] -pub use alignment::Alignment; +#[deprecated(since = "1.96.0", note = "moved from `ptr` to `mem`")] +/// Deprecated re-export of [mem::Alignment]. +pub type Alignment = mem::Alignment; mod metadata; #[unstable(feature = "ptr_metadata", issue = "81513")] @@ -452,9 +479,9 @@ mod mut_ptr; /// /// Behavior is undefined if any of the following conditions are violated: /// -/// * `src` must be [valid] for reads of `count * size_of::()` bytes. +/// * `src` must be [valid] for reads of `count * size_of::()` bytes or that number must be 0. /// -/// * `dst` must be [valid] for writes of `count * size_of::()` bytes. +/// * `dst` must be [valid] for writes of `count * size_of::()` bytes or that number must be 0. /// /// * Both `src` and `dst` must be properly aligned. /// @@ -576,11 +603,11 @@ pub const unsafe fn copy_nonoverlapping(src: *const T, dst: *mut T, count: us /// /// Behavior is undefined if any of the following conditions are violated: /// -/// * `src` must be [valid] for reads of `count * size_of::()` bytes. +/// * `src` must be [valid] for reads of `count * size_of::()` bytes or that number must be 0. /// -/// * `dst` must be [valid] for writes of `count * size_of::()` bytes, and must remain valid even -/// when `src` is read for `count * size_of::()` bytes. (This means if the memory ranges -/// overlap, the `dst` pointer must not be invalidated by `src` reads.) +/// * `dst` must be [valid] for writes of `count * size_of::()` bytes or that number must be 0, +/// and `dst` must remain valid even when `src` is read for `count * size_of::()` bytes. (This +/// means if the memory ranges overlap, the `dst` pointer must not be invalidated by `src` reads.) /// /// * Both `src` and `dst` must be properly aligned. /// @@ -809,20 +836,33 @@ pub const unsafe fn write_bytes(dst: *mut T, val: u8, count: usize) { /// // Ensure that the last item was dropped. /// assert!(weak.upgrade().is_none()); /// ``` +#[inline(always)] #[stable(feature = "drop_in_place", since = "1.8.0")] -#[lang = "drop_in_place"] -#[allow(unconditional_recursion)] #[rustc_diagnostic_item = "ptr_drop_in_place"] #[rustc_const_unstable(feature = "const_drop_in_place", issue = "109342")] pub const unsafe fn drop_in_place(to_drop: *mut T) +where + T: [const] Destruct, +{ + // Due to historic reasons, `drop_in_place` takes a pointer rather than a reference, + // which results in worse codegen since we don't apply noalias/dereferenceable llvm + // attributes to pointer arguments. To workaround this without breaking public + // interface, `drop_in_place` calls the lang item, rather than being one directly. + + // SAFETY: + // - compiler glue has the same safety requirements as this function + // - the pointer must be valid as per the safety requirement of this function + unsafe { drop_glue(&mut *to_drop) } +} + +/// Helper function for `drop_in_place`. The compiler replaces this by the actual drop glue. +#[lang = "drop_glue"] +pub(crate) const unsafe fn drop_glue(_: &mut T) where T: [const] Destruct, { // Code here does not matter - this is replaced by the // real drop glue by the compiler. - - // SAFETY: see comment above - unsafe { drop_in_place(to_drop) } } /// Creates a null raw pointer. @@ -995,7 +1035,7 @@ pub const fn dangling_mut() -> *mut T { #[stable(feature = "exposed_provenance", since = "1.84.0")] #[rustc_const_stable(feature = "const_exposed_provenance", since = "1.91.0")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces -#[allow(fuzzy_provenance_casts)] // this *is* the explicit provenance API one should use instead +#[allow(implicit_provenance_casts)] // this *is* the explicit provenance API one should use instead pub const fn with_exposed_provenance(addr: usize) -> *const T { addr as *const T } @@ -1036,7 +1076,7 @@ pub const fn with_exposed_provenance(addr: usize) -> *const T { #[stable(feature = "exposed_provenance", since = "1.84.0")] #[rustc_const_stable(feature = "const_exposed_provenance", since = "1.91.0")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces -#[allow(fuzzy_provenance_casts)] // this *is* the explicit provenance API one should use instead +#[allow(implicit_provenance_casts)] // this *is* the explicit provenance API one should use instead pub const fn with_exposed_provenance_mut(addr: usize) -> *mut T { addr as *mut T } @@ -1304,7 +1344,7 @@ pub const fn slice_from_raw_parts_mut(data: *mut T, len: usize) -> *mut [T] { /// assert_eq!([1, 0, 1, 2], array); /// } /// ``` -#[inline] +#[inline(always)] #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_stable(feature = "const_swap", since = "1.85.0")] #[rustc_diagnostic_item = "ptr_swap"] @@ -1523,7 +1563,7 @@ unsafe fn swap_nonoverlapping_bytes(x: *mut u8, y: *mut u8, bytes: NonZero(dst: *mut T, src: T) -> T { // SAFETY: the caller must guarantee that `dst` is valid to be // cast to a mutable reference (valid for writes, aligned, initialized), // and cannot overlap `src` since `dst` must point to a distinct - // allocation. + // allocation. We are excluding null (with a ZST check) before creating a reference. unsafe { ub_checks::assert_unsafe_precondition!( check_language_ub, @@ -1569,6 +1609,12 @@ pub const unsafe fn replace(dst: *mut T, src: T) -> T { is_zst: bool = T::IS_ZST, ) => ub_checks::maybe_is_aligned_and_not_null(addr, align, is_zst) ); + if T::IS_ZST { + // If `T` is a ZST, `dst` is allowed to be null. However, we also don't have to actually + // do anything since there isn't actually any data to be copied anyway. All values of + // type `T` are bit-identical, so we can just return `src` here. + return src; + } mem::replace(&mut *dst, src) } } @@ -1580,7 +1626,7 @@ pub const unsafe fn replace(dst: *mut T, src: T) -> T { /// /// Behavior is undefined if any of the following conditions are violated: /// -/// * `src` must be [valid] for reads. +/// * `src` must be [valid] for reads or `T` must be a ZST. /// /// * `src` must be properly aligned. Use [`read_unaligned`] if this is not the /// case. @@ -1678,7 +1724,7 @@ pub const unsafe fn replace(dst: *mut T, src: T) -> T { /// ``` /// /// [valid]: self#safety -#[inline] +#[inline(always)] #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_stable(feature = "const_ptr_read", since = "1.71.0")] #[track_caller] @@ -1796,22 +1842,30 @@ pub const unsafe fn read(src: *const T) -> T { /// unsafe { ptr.read_unaligned() } /// } /// ``` -#[inline] +#[inline(always)] #[stable(feature = "ptr_unaligned", since = "1.17.0")] #[rustc_const_stable(feature = "const_ptr_read", since = "1.71.0")] #[track_caller] #[rustc_diagnostic_item = "ptr_read_unaligned"] pub const unsafe fn read_unaligned(src: *const T) -> T { - let mut tmp = MaybeUninit::::uninit(); + // Always true thanks to the repr, but to demonstrate + const { + assert!(mem::offset_of!(Unaligned::, 0) == 0); + assert!(size_of::() == size_of::>()); + } + + let src = src.cast::>(); // SAFETY: the caller must guarantee that `src` is valid for reads. - // `src` cannot overlap `tmp` because `tmp` was just allocated on - // the stack as a separate allocation. + // Reading it as `Unaligned` instead of `T` reads those same bytes because + // it's the same size (thus zero offset), but with alignment 1 instead. // - // Also, since we just wrote a valid value into `tmp`, it is guaranteed - // to be properly initialized. + // Similarly, because it's the same bytes it's sound to transmute from the + // `Unaligned` to `T`. Transmute is a value-based (not a place-based) + // operation that doesn't care about alignment. unsafe { - copy_nonoverlapping(src as *const u8, tmp.as_mut_ptr() as *mut u8, size_of::()); - tmp.assume_init() + let unaligned = read(src); + // Can't just destructure because that's not allowed in const fn + mem::transmute_neo(unaligned) } } @@ -1832,7 +1886,7 @@ pub const unsafe fn read_unaligned(src: *const T) -> T { /// /// Behavior is undefined if any of the following conditions are violated: /// -/// * `dst` must be [valid] for writes. +/// * `dst` must be [valid] for writes or `T` must be a ZST. /// /// * `dst` must be properly aligned. Use [`write_unaligned`] if this is not the /// case. @@ -1894,7 +1948,7 @@ pub const unsafe fn read_unaligned(src: *const T) -> T { /// assert_eq!(foo, "bar"); /// assert_eq!(bar, "foo"); /// ``` -#[inline] +#[inline(always)] #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_stable(feature = "const_ptr_write", since = "1.83.0")] #[rustc_diagnostic_item = "ptr_write"] @@ -1998,20 +2052,24 @@ pub const unsafe fn write(dst: *mut T, src: T) { /// unsafe { ptr.write_unaligned(val) } /// } /// ``` -#[inline] +#[inline(always)] #[stable(feature = "ptr_unaligned", since = "1.17.0")] #[rustc_const_stable(feature = "const_ptr_write", since = "1.83.0")] #[rustc_diagnostic_item = "ptr_write_unaligned"] #[track_caller] pub const unsafe fn write_unaligned(dst: *mut T, src: T) { - // SAFETY: the caller must guarantee that `dst` is valid for writes. - // `dst` cannot overlap `src` because the caller has mutable access - // to `dst` while `src` is owned by this function. - unsafe { - copy_nonoverlapping((&raw const src) as *const u8, dst as *mut u8, size_of::()); - // We are calling the intrinsic directly to avoid function calls in the generated code. - intrinsics::forget(src); + // Always true thanks to the repr, but to demonstrate + const { + assert!(mem::offset_of!(Unaligned::, 0) == 0); + assert!(size_of::() == size_of::>()); } + + let dst = dst.cast::>(); + let src = Unaligned(src); + // SAFETY: the caller must guarantee that `dst` is valid for writes. + // Writing it as `Unaligned` instead of `T` writes those same bytes because + // it's the same size (thus zero offset), but with alignment 1 instead. + unsafe { write(dst, src) } } /// Performs a volatile read of the value from `src` without moving it. @@ -2043,9 +2101,27 @@ pub const unsafe fn write_unaligned(dst: *mut T, src: T) { /// /// Note that volatile memory operations where T is a zero-sized type are noops and may be ignored. /// +/// When invoked during const evaluation, this behaves like a regular read. In particular, such +/// reads must always follow the first of the two cases above. +/// /// [allocation]: crate::ptr#allocated-object /// [atomic]: crate::sync::atomic#memory-model-for-atomic-accesses /// +/// # Load splitting +/// +/// Exactly which hardware loads are performed by this function is, in general, highly target-dependent. +/// +/// For a simple scalar, such as when `T` is a thin pointer, this will typically be one load assuming +/// your target supports a load of exactly that size and alignment. +/// +/// For anything else, it will be split into multiple loads in some unspecified way. +/// This can happen even for scalars: notably, on many targets loading a `u128` will still need to be split, +/// despite being "one" scalar. On many targets loading anything larger than a pointer will need to be split. +/// On all current targets a load larger than 64 bytes will need to be split. +/// Any load whose size is not a power of two will also almost certainly need to be split. +/// +/// There is no stability guarantee on how that splitting happens. It may change at any point. +/// /// # Safety /// /// Like [`read`], `read_volatile` creates a bitwise copy of `T`, regardless of whether `T` is @@ -2055,8 +2131,8 @@ pub const unsafe fn write_unaligned(dst: *mut T, src: T) { /// /// Behavior is undefined if any of the following conditions are violated: /// -/// * `src` must be either [valid] for reads, or it must point to memory outside of all Rust -/// allocations and reading from that memory must: +/// * `src` must be either [valid] for reads, or `T` must be a ZST, or `src` must point to memory +/// outside of all Rust allocations and reading from that memory must: /// - not trap, and /// - not cause any memory inside a Rust allocation to be modified. /// @@ -2081,12 +2157,13 @@ pub const unsafe fn write_unaligned(dst: *mut T, src: T) { /// assert_eq!(std::ptr::read_volatile(y), 12); /// } /// ``` -#[inline] +#[inline(always)] #[stable(feature = "volatile", since = "1.9.0")] +#[rustc_const_unstable(feature = "const_volatile", issue = "159094")] #[track_caller] #[rustc_diagnostic_item = "ptr_read_volatile"] #[safety::requires(ub_checks::can_dereference(src))] -pub unsafe fn read_volatile(src: *const T) -> T { +pub const unsafe fn read_volatile(src: *const T) -> T { // SAFETY: the caller must uphold the safety contract for `volatile_load`. unsafe { ub_checks::assert_unsafe_precondition!( @@ -2137,15 +2214,33 @@ pub unsafe fn read_volatile(src: *const T) -> T { /// dropped when operating on Rust memory. Additionally, it does not drop `src`. Semantically, `src` /// is moved into the location pointed to by `dst`. /// +/// When invoked during const evaluation, this behaves like a regular write. In particular, such +/// reads must always follow the first of the two cases above. +/// /// [allocation]: crate::ptr#allocated-object /// [atomic]: crate::sync::atomic#memory-model-for-atomic-accesses /// +/// # Store splitting +/// +/// Exactly which hardware stores are performed by this function is, in general, highly target-dependent. +/// +/// For a simple scalar, such as when `T` is a thin pointer, this will typically be one store assuming +/// your target supports a store of exactly that size and alignment. +/// +/// For anything else, it will be split into multiple stores in some unspecified way. +/// This can happen even for scalars: notably, on many targets storing a `u128` will still need to be split, +/// despite being "one" scalar. On many targets storing anything larger than a pointer will need to be split. +/// On all current targets a store larger than 64 bytes will need to be split. +/// Any store whose size is not a power of two will also almost certainly need to be split. +/// +/// There is no stability guarantee on how that splitting happens. It may change at any point. +/// /// # Safety /// /// Behavior is undefined if any of the following conditions are violated: /// -/// * `dst` must be either [valid] for writes, or it must point to memory outside of all Rust -/// allocations and writing to that memory must: +/// * `dst` must be either [valid] for writes, or `T` must be a ZST, or `dst` must point to memory +/// outside of all Rust allocations and writing to that memory must: /// - not trap, and /// - not cause any memory inside a Rust allocation to be modified. /// @@ -2169,12 +2264,13 @@ pub unsafe fn read_volatile(src: *const T) -> T { /// assert_eq!(std::ptr::read_volatile(y), 12); /// } /// ``` -#[inline] +#[inline(always)] #[stable(feature = "volatile", since = "1.9.0")] +#[rustc_const_unstable(feature = "const_volatile", issue = "159094")] #[rustc_diagnostic_item = "ptr_write_volatile"] #[track_caller] #[safety::requires(ub_checks::can_write(dst))] -pub unsafe fn write_volatile(dst: *mut T, src: T) { +pub const unsafe fn write_volatile(dst: *mut T, src: T) { // SAFETY: the caller must uphold the safety contract for `volatile_store`. unsafe { ub_checks::assert_unsafe_precondition!( @@ -2624,21 +2720,21 @@ impl Ord for F { #[stable(feature = "fnptr_impls", since = "1.4.0")] impl hash::Hash for F { fn hash(&self, state: &mut HH) { - state.write_usize(self.addr() as _) + state.write_usize(self.addr()) } } #[stable(feature = "fnptr_impls", since = "1.4.0")] impl fmt::Pointer for F { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - fmt::pointer_fmt_inner(self.addr() as _, f) + fmt::pointer_fmt_inner(self.addr(), f) } } #[stable(feature = "fnptr_impls", since = "1.4.0")] impl fmt::Debug for F { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - fmt::pointer_fmt_inner(self.addr() as _, f) + fmt::pointer_fmt_inner(self.addr(), f) } } @@ -2816,6 +2912,11 @@ pub macro addr_of_mut($place:expr) { &raw mut $place } +/// Used in [`read_unaligned`] and [`write_unaligned`] to load and store `T` +/// with alignment 1 rather than its usual `align_of::()` alignment. +#[repr(Rust, packed)] +struct Unaligned(T); + #[cfg(kani)] #[unstable(feature = "kani", issue = "none")] mod verify { diff --git a/library/core/src/ptr/mut_ptr.rs b/library/core/src/ptr/mut_ptr.rs index 6e6e72eb03fbf..c78bab7663a51 100644 --- a/library/core/src/ptr/mut_ptr.rs +++ b/library/core/src/ptr/mut_ptr.rs @@ -178,6 +178,7 @@ impl *mut T { /// [`with_exposed_provenance_mut`]: with_exposed_provenance_mut #[inline(always)] #[stable(feature = "exposed_provenance", since = "1.84.0")] + #[expect(implicit_provenance_casts, reason = "this *is* the replacement")] pub fn expose_provenance(self) -> usize { self.cast::<()>() as usize } @@ -259,7 +260,6 @@ impl *mut T { /// [`as_uninit_ref`]: #method.as_uninit_ref-1 /// [`as_ref_unchecked`]: #method.as_ref_unchecked-1 /// [`as_mut`]: #method.as_mut - #[stable(feature = "ptr_as_ref", since = "1.9.0")] #[rustc_const_stable(feature = "const_ptr_is_null", since = "1.84.0")] #[inline] @@ -292,8 +292,8 @@ impl *mut T { /// println!("We got back the value: {}!", ptr.as_ref_unchecked()); /// } /// ``` - #[stable(feature = "ptr_as_ref_unchecked", since = "CURRENT_RUSTC_VERSION")] - #[rustc_const_stable(feature = "ptr_as_ref_unchecked", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "ptr_as_ref_unchecked", since = "1.95.0")] + #[rustc_const_stable(feature = "ptr_as_ref_unchecked", since = "1.95.0")] #[inline] #[must_use] pub const unsafe fn as_ref_unchecked<'a>(self) -> &'a T { @@ -337,6 +337,10 @@ impl *mut T { #[doc = include_str!("./docs/offset.md")] /// + /// Consider using [`wrapping_offset`](#method.wrapping_offset) instead if these constraints are + /// difficult to satisfy. The only advantage of this method is that it + /// enables more aggressive compiler optimizations. + /// /// # Examples /// /// ``` @@ -625,7 +629,7 @@ impl *mut T { /// /// [`as_mut`]: #method.as_mut /// [`as_uninit_mut`]: #method.as_uninit_mut - /// [`as_ref_unchecked`]: #method.as_mut_unchecked + /// [`as_ref_unchecked`]: #method.as_ref_unchecked /// /// # Safety /// @@ -642,8 +646,8 @@ impl *mut T { /// # assert_eq!(s, [4, 2, 3]); /// println!("{s:?}"); // It'll print: "[4, 2, 3]". /// ``` - #[stable(feature = "ptr_as_ref_unchecked", since = "CURRENT_RUSTC_VERSION")] - #[rustc_const_stable(feature = "ptr_as_ref_unchecked", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "ptr_as_ref_unchecked", since = "1.95.0")] + #[rustc_const_stable(feature = "ptr_as_ref_unchecked", since = "1.95.0")] #[inline] #[must_use] pub const unsafe fn as_mut_unchecked<'a>(self) -> &'a mut T { @@ -664,6 +668,8 @@ impl *mut T { /// /// When calling this method, you have to ensure that *either* the pointer is null *or* /// the pointer is [convertible to a reference](crate::ptr#pointer-to-reference-conversion). + /// Note that because the created reference is to `MaybeUninit`, the + /// source pointer can point to uninitialized memory. /// /// # Panics during const evaluation /// @@ -774,9 +780,8 @@ impl *mut T { /// needed for `const`-compatibility: the distance between pointers into *different* allocated /// objects is not known at compile-time. However, the requirement also exists at /// runtime and may be exploited by optimizations. If you wish to compute the difference between - /// pointers that are not guaranteed to be from the same allocation, use `(self as isize - - /// origin as isize) / size_of::()`. - // FIXME: recommend `addr()` instead of `as usize` once that is stable. + /// pointers that are not guaranteed to be from the same allocation, use + /// `(self.addr() as isize - origin.addr() as isize) / size_of::()`. /// /// [`add`]: #method.add /// [allocation]: crate::ptr#allocation @@ -959,6 +964,10 @@ impl *mut T { #[doc = include_str!("./docs/add.md")] /// + /// Consider using [`wrapping_add`](#method.wrapping_add) instead if these constraints are + /// difficult to satisfy. The only advantage of this method is that it + /// enables more aggressive compiler optimizations. + /// /// # Examples /// /// ``` @@ -1066,39 +1075,12 @@ impl *mut T { unsafe { self.cast::().add(count).with_metadata_of(self) } } - /// Subtracts an unsigned offset from a pointer. - /// - /// This can only move the pointer backward (or not move it). If you need to move forward or - /// backward depending on the value, then you might want [`offset`](#method.offset) instead - /// which takes a signed offset. - /// - /// `count` is in units of T; e.g., a `count` of 3 represents a pointer - /// offset of `3 * size_of::()` bytes. + #[doc = include_str!("./docs/sub.md")] /// - /// # Safety - /// - /// If any of the following conditions are violated, the result is Undefined Behavior: - /// - /// * The offset in bytes, `count * size_of::()`, computed on mathematical integers (without - /// "wrapping around"), must fit in an `isize`. - /// - /// * If the computed offset is non-zero, then `self` must be [derived from][crate::ptr#provenance] a pointer to some - /// [allocation], and the entire memory range between `self` and the result must be in - /// bounds of that allocation. In particular, this range must not "wrap around" the edge - /// of the address space. - /// - /// Allocations can never be larger than `isize::MAX` bytes, so if the computed offset - /// stays in bounds of the allocation, it is guaranteed to satisfy the first requirement. - /// This implies, for instance, that `vec.as_ptr().add(vec.len())` (for `vec: Vec`) is always - /// safe. - /// - /// Consider using [`wrapping_sub`] instead if these constraints are + /// Consider using [`wrapping_sub`](#method.wrapping_sub) instead if these constraints are /// difficult to satisfy. The only advantage of this method is that it /// enables more aggressive compiler optimizations. /// - /// [`wrapping_sub`]: #method.wrapping_sub - /// [allocation]: crate::ptr#allocation - /// /// # Examples /// /// ``` @@ -1263,6 +1245,7 @@ impl *mut T { #[stable(feature = "pointer_methods", since = "1.26.0")] #[must_use = "returns a new pointer rather than modifying its argument"] #[rustc_const_stable(feature = "const_ptr_offset", since = "1.61.0")] + #[allow(clippy::ptr_offset_with_cast)] #[inline(always)] pub const fn wrapping_add(self, count: usize) -> Self where @@ -1393,9 +1376,10 @@ impl *mut T { /// /// [`ptr::read_volatile`]: crate::ptr::read_volatile() #[stable(feature = "pointer_methods", since = "1.26.0")] + #[rustc_const_unstable(feature = "const_volatile", issue = "159094")] #[inline(always)] #[track_caller] - pub unsafe fn read_volatile(self) -> T + pub const unsafe fn read_volatile(self) -> T where T: Sized, { @@ -1567,9 +1551,10 @@ impl *mut T { /// /// [`ptr::write_volatile`]: crate::ptr::write_volatile() #[stable(feature = "pointer_methods", since = "1.26.0")] + #[rustc_const_unstable(feature = "const_volatile", issue = "159094")] #[inline(always)] #[track_caller] - pub unsafe fn write_volatile(self, val: T) + pub const unsafe fn write_volatile(self, val: T) where T: Sized, { @@ -1794,13 +1779,13 @@ impl *mut T { /// #![feature(ptr_cast_slice)] /// /// let x = &mut [5, 6, 7]; - /// let slice = x.as_mut_ptr().cast_slice(3); + /// let raw_mut_slice = x.as_mut_ptr().cast_slice(3); /// /// unsafe { - /// (*slice)[2] = 99; // assign a value at an index in the slice + /// (*raw_mut_slice)[2] = 99; // assign a value at an index in the slice /// }; /// - /// assert_eq!(unsafe { &*slice }[2], 99); + /// assert_eq!(unsafe { &*raw_mut_slice }[2], 99); /// ``` /// /// You must ensure that the pointer is valid and not null before dereferencing @@ -1820,6 +1805,7 @@ impl *mut T { slice_from_raw_parts_mut(self, len) } } + impl *mut MaybeUninit { /// Casts from a maybe-uninitialized type to its initialized version. /// @@ -1919,7 +1905,6 @@ impl *mut [T] { /// /// ``` /// #![feature(raw_slice_split)] - /// #![feature(slice_ptr_get)] /// /// let mut v = [1, 0, 3, 0, 5, 6]; /// let ptr = &mut v as *mut [_]; diff --git a/library/core/src/ptr/non_null.rs b/library/core/src/ptr/non_null.rs index 96db651df1896..d707386afcdd1 100644 --- a/library/core/src/ptr/non_null.rs +++ b/library/core/src/ptr/non_null.rs @@ -5,10 +5,9 @@ use crate::cmp::Ordering; #[cfg(kani)] use crate::kani; use crate::marker::{Destruct, PointeeSized, Unsize}; -use crate::mem::{MaybeUninit, SizedTypeProperties}; +use crate::mem::{MaybeUninit, SizedTypeProperties, transmute}; use crate::num::NonZero; use crate::ops::{CoerceUnsized, DispatchFromDyn}; -use crate::pin::PinCoerceUnsized; use crate::ptr::Unique; use crate::slice::{self, SliceIndex}; #[cfg(kani)] @@ -54,7 +53,12 @@ use crate::{fmt, hash, intrinsics, mem, ptr}; /// it is your responsibility to ensure that `as_mut` is never called, and `as_ptr` /// is never used for mutation. /// -/// # Representation +/// # Layout +/// +/// `NonNull` is guaranteed to have the same layout and bit validity as `*mut T` +/// with the exception that a null pointer is invalid. +/// `Option>` is guaranteed to be ABI-compatible with `*mut T`, including in +/// FFI. /// /// Thanks to the [null pointer optimization], /// `NonNull` and `Option>` @@ -76,13 +80,10 @@ use crate::{fmt, hash, intrinsics, mem, ptr}; /// [null pointer optimization]: crate::option#representation #[stable(feature = "nonnull", since = "1.25.0")] #[repr(transparent)] -#[rustc_layout_scalar_valid_range_start(1)] #[rustc_nonnull_optimization_guaranteed] -#[rustc_diagnostic_item = "NonNull"] +#[lang = "non_null"] pub struct NonNull { - // Remember to use `.as_ptr()` instead of `.pointer`, as field projecting to - // this is banned by . - pointer: *const T, + pointer: crate::pattern_type!(*const T is !null), } /// `NonNull` pointers are not `Send` because the data they reference may be aliased. @@ -106,9 +107,8 @@ impl NonNull { #[must_use] #[inline] pub const fn without_provenance(addr: NonZero) -> Self { - let pointer = crate::ptr::without_provenance(addr.get()); - // SAFETY: we know `addr` is non-zero. - unsafe { NonNull { pointer } } + // SAFETY: we know `addr` is non-zero and all nonzero integers are valid raw pointers. + unsafe { transmute(addr) } } /// Creates a new `NonNull` that is dangling, but well-aligned. @@ -134,10 +134,10 @@ impl NonNull { #[rustc_const_stable(feature = "const_nonnull_dangling", since = "1.36.0")] #[must_use] #[inline] - #[ensures(|result| !result.pointer.is_null() && result.pointer.is_aligned())] + #[ensures(|result| !result.as_ptr().is_null() && result.as_ptr().is_aligned())] pub const fn dangling() -> Self { - let align = crate::ptr::Alignment::of::(); - NonNull::without_provenance(align.as_nonzero()) + let align = crate::mem::Alignment::of::(); + NonNull::without_provenance(align.as_nonzero_usize()) } /// Converts an address back to a mutable pointer, picking up some previously 'exposed' @@ -147,8 +147,9 @@ impl NonNull { /// /// This is an [Exposed Provenance][crate::ptr#exposed-provenance] API. #[stable(feature = "nonnull_provenance", since = "1.89.0")] + #[rustc_const_unstable(feature = "const_nonnull_with_exposed_provenance", issue = "154215")] #[inline] - pub fn with_exposed_provenance(addr: NonZero) -> Self { + pub const fn with_exposed_provenance(addr: NonZero) -> Self { // SAFETY: we know `addr` is non-zero. unsafe { let ptr = crate::ptr::with_exposed_provenance_mut(addr.get()); @@ -217,6 +218,10 @@ impl NonNull { impl NonNull { /// Creates a new `NonNull`. /// + /// Note that if you have an `&mut`, you can use the safe [`from_mut`] instead. + /// + /// [`from_mut`]: NonNull::from_mut + /// /// # Safety /// /// `ptr` must be non-null. @@ -252,12 +257,16 @@ impl NonNull { "NonNull::new_unchecked requires that the pointer is non-null", (ptr: *mut () = ptr as *mut ()) => !ptr.is_null() ); - NonNull { pointer: ptr as _ } + transmute(ptr) } } /// Creates a new `NonNull` if `ptr` is non-null. /// + /// Note that if you have an `&mut`, you can use [`from_mut`] instead to avoid the `Option`. + /// + /// [`from_mut`]: NonNull::from_mut + /// /// # Panics during const evaluation /// /// This method will panic during const evaluation if the pointer cannot be @@ -271,7 +280,7 @@ impl NonNull { /// use std::ptr::NonNull; /// /// let mut x = 0u32; - /// let ptr = NonNull::::new(&mut x as *mut _).expect("ptr is null!"); + /// let ptr = NonNull::::new(&mut x as *mut _).expect("pointer should not be null"); /// /// if let Some(ptr) = NonNull::::new(std::ptr::null_mut()) { /// unreachable!(); @@ -297,7 +306,7 @@ impl NonNull { #[inline] pub const fn from_ref(r: &T) -> Self { // SAFETY: A reference cannot be null. - unsafe { NonNull { pointer: r as *const T } } + unsafe { transmute(r as *const T) } } /// Converts a mutable reference to a `NonNull` pointer. @@ -306,7 +315,7 @@ impl NonNull { #[inline] pub const fn from_mut(r: &mut T) -> Self { // SAFETY: A mutable reference cannot be null. - unsafe { NonNull { pointer: r as *mut T } } + unsafe { transmute(r as *mut T) } } /// Performs the same functionality as [`std::ptr::from_raw_parts`], except that a @@ -317,7 +326,7 @@ impl NonNull { /// [`std::ptr::from_raw_parts`]: crate::ptr::from_raw_parts #[unstable(feature = "ptr_metadata", issue = "81513")] #[inline] - #[ensures(|result| !result.pointer.is_null())] + #[ensures(|result| !result.as_ptr().is_null())] pub const fn from_raw_parts( data_pointer: NonNull, metadata: ::Metadata, @@ -406,7 +415,7 @@ impl NonNull { /// use std::ptr::NonNull; /// /// let mut x = 0u32; - /// let ptr = NonNull::new(&mut x).expect("ptr is null!"); + /// let ptr = NonNull::new(&mut x).expect("pointer should not be null"); /// /// let x_value = unsafe { *ptr.as_ptr() }; /// assert_eq!(x_value, 0); @@ -421,7 +430,7 @@ impl NonNull { #[must_use] #[inline(always)] //Ensures address of resulting pointer is same as original - #[ensures(|result: &*mut T| *result == self.pointer as *mut T)] + #[ensures(|result: &*mut T| *result == unsafe { mem::transmute::(self) })] pub const fn as_ptr(self) -> *mut T { // This is a transmute for the same reasons as `NonZero::get`. @@ -450,7 +459,7 @@ impl NonNull { /// use std::ptr::NonNull; /// /// let mut x = 0u32; - /// let ptr = NonNull::new(&mut x as *mut _).expect("ptr is null!"); + /// let ptr = NonNull::new(&mut x as *mut _).expect("pointer should not be null"); /// /// let ref_x = unsafe { ptr.as_ref() }; /// println!("{ref_x}"); @@ -488,7 +497,7 @@ impl NonNull { /// use std::ptr::NonNull; /// /// let mut x = 0u32; - /// let mut ptr = NonNull::new(&mut x).expect("null pointer"); + /// let mut ptr = NonNull::new(&mut x).expect("pointer should not be null"); /// /// let x_ref = unsafe { ptr.as_mut() }; /// assert_eq!(*x_ref, 0); @@ -518,7 +527,7 @@ impl NonNull { /// use std::ptr::NonNull; /// /// let mut x = 0u32; - /// let ptr = NonNull::new(&mut x as *mut _).expect("null pointer"); + /// let ptr = NonNull::new(&mut x as *mut _).expect("pointer should not be null"); /// /// let casted_ptr = ptr.cast::(); /// let raw_ptr: *mut i8 = casted_ptr.as_ptr(); @@ -532,7 +541,7 @@ impl NonNull { #[ensures(|result: &NonNull| result.as_ptr().addr() == self.as_ptr().addr())] pub const fn cast(self) -> NonNull { // SAFETY: `self` is a `NonNull` pointer which is necessarily non-null - unsafe { NonNull { pointer: self.as_ptr() as *mut U } } + unsafe { transmute(self.as_ptr() as *mut U) } } /// Try to cast to a pointer of another type by checking alignment. @@ -562,28 +571,7 @@ impl NonNull { if self.is_aligned_to(align_of::()) { Some(self.cast()) } else { None } } - /// Adds an offset to a pointer. - /// - /// `count` is in units of T; e.g., a `count` of 3 represents a pointer - /// offset of `3 * size_of::()` bytes. - /// - /// # Safety - /// - /// If any of the following conditions are violated, the result is Undefined Behavior: - /// - /// * The computed offset, `count * size_of::()` bytes, must not overflow `isize`. - /// - /// * If the computed offset is non-zero, then `self` must be derived from a pointer to some - /// [allocation], and the entire memory range between `self` and the result must be in - /// bounds of that allocation. In particular, this range must not "wrap around" the edge - /// of the address space. - /// - /// Allocations can never be larger than `isize::MAX` bytes, so if the computed offset - /// stays in bounds of the allocation, it is guaranteed to satisfy the first requirement. - /// This implies, for instance, that `vec.as_ptr().add(vec.len())` (for `vec: Vec`) is always - /// safe. - /// - /// [allocation]: crate::ptr#allocation + #[doc = include_str!("./docs/offset.md")] /// /// # Examples /// @@ -617,7 +605,7 @@ impl NonNull { // Additionally safety contract of `offset` guarantees that the resulting pointer is // pointing to an allocation, there can't be an allocation at null, thus it's safe to // construct `NonNull`. - unsafe { NonNull { pointer: intrinsics::offset(self.as_ptr(), count) } } + unsafe { transmute(intrinsics::offset(self.as_ptr(), count)) } } /// Calculates the offset from a pointer in bytes. @@ -646,31 +634,10 @@ impl NonNull { // Additionally safety contract of `offset` guarantees that the resulting pointer is // pointing to an allocation, there can't be an allocation at null, thus it's safe to // construct `NonNull`. - unsafe { NonNull { pointer: self.as_ptr().byte_offset(count) } } + unsafe { transmute(self.as_ptr().byte_offset(count)) } } - /// Adds an offset to a pointer (convenience for `.offset(count as isize)`). - /// - /// `count` is in units of T; e.g., a `count` of 3 represents a pointer - /// offset of `3 * size_of::()` bytes. - /// - /// # Safety - /// - /// If any of the following conditions are violated, the result is Undefined Behavior: - /// - /// * The computed offset, `count * size_of::()` bytes, must not overflow `isize`. - /// - /// * If the computed offset is non-zero, then `self` must be derived from a pointer to some - /// [allocation], and the entire memory range between `self` and the result must be in - /// bounds of that allocation. In particular, this range must not "wrap around" the edge - /// of the address space. - /// - /// Allocations can never be larger than `isize::MAX` bytes, so if the computed offset - /// stays in bounds of the allocation, it is guaranteed to satisfy the first requirement. - /// This implies, for instance, that `vec.as_ptr().add(vec.len())` (for `vec: Vec`) is always - /// safe. - /// - /// [allocation]: crate::ptr#allocation + #[doc = include_str!("./docs/add.md")] /// /// # Examples /// @@ -692,11 +659,11 @@ impl NonNull { #[rustc_const_stable(feature = "non_null_convenience", since = "1.80.0")] #[requires(count.checked_mul(core::mem::size_of::()).is_some() && count * core::mem::size_of::() <= isize::MAX as usize - && (self.pointer as isize).checked_add(count as isize * core::mem::size_of::() as isize).is_some() // check wrapping add + && (self.as_ptr() as isize).checked_add(count as isize * core::mem::size_of::() as isize).is_some() // check wrapping add // Zero-sized offsets (`count * size_of::() == 0`) are always // permitted, including on dangling pointers, per the documentation. && (count == 0 || core::mem::size_of::() == 0 - || core::ub_checks::same_allocation(self.pointer, self.pointer.wrapping_offset(count as isize))))] + || core::ub_checks::same_allocation(self.as_ptr(), self.as_ptr().wrapping_offset(count as isize))))] #[ensures(|result: &NonNull| result.as_ptr() == self.as_ptr().offset(count as isize))] pub const unsafe fn add(self, count: usize) -> Self where @@ -706,7 +673,7 @@ impl NonNull { // Additionally safety contract of `offset` guarantees that the resulting pointer is // pointing to an allocation, there can't be an allocation at null, thus it's safe to // construct `NonNull`. - unsafe { NonNull { pointer: intrinsics::offset(self.as_ptr(), count) } } + unsafe { transmute(intrinsics::offset(self.as_ptr(), count)) } } /// Calculates the offset from a pointer in bytes (convenience for `.byte_offset(count as isize)`). @@ -739,32 +706,10 @@ impl NonNull { // Additionally safety contract of `add` guarantees that the resulting pointer is pointing // to an allocation, there can't be an allocation at null, thus it's safe to construct // `NonNull`. - unsafe { NonNull { pointer: self.as_ptr().byte_add(count) } } + unsafe { transmute(self.as_ptr().byte_add(count)) } } - /// Subtracts an offset from a pointer (convenience for - /// `.offset((count as isize).wrapping_neg())`). - /// - /// `count` is in units of T; e.g., a `count` of 3 represents a pointer - /// offset of `3 * size_of::()` bytes. - /// - /// # Safety - /// - /// If any of the following conditions are violated, the result is Undefined Behavior: - /// - /// * The computed offset, `count * size_of::()` bytes, must not overflow `isize`. - /// - /// * If the computed offset is non-zero, then `self` must be derived from a pointer to some - /// [allocation], and the entire memory range between `self` and the result must be in - /// bounds of that allocation. In particular, this range must not "wrap around" the edge - /// of the address space. - /// - /// Allocations can never be larger than `isize::MAX` bytes, so if the computed offset - /// stays in bounds of the allocation, it is guaranteed to satisfy the first requirement. - /// This implies, for instance, that `vec.as_ptr().add(vec.len())` (for `vec: Vec`) is always - /// safe. - /// - /// [allocation]: crate::ptr#allocation + #[doc = include_str!("./docs/sub.md")] /// /// # Examples /// @@ -839,7 +784,7 @@ impl NonNull { // Additionally safety contract of `sub` guarantees that the resulting pointer is pointing // to an allocation, there can't be an allocation at null, thus it's safe to construct // `NonNull`. - unsafe { NonNull { pointer: self.as_ptr().byte_sub(count) } } + unsafe { transmute(self.as_ptr().byte_sub(count)) } } /// Calculates the distance between two pointers within the same allocation. The returned value is in @@ -880,9 +825,8 @@ impl NonNull { /// needed for `const`-compatibility: the distance between pointers into *different* allocated /// objects is not known at compile-time. However, the requirement also exists at /// runtime and may be exploited by optimizations. If you wish to compute the difference between - /// pointers that are not guaranteed to be from the same allocation, use `(self as isize - - /// origin as isize) / size_of::()`. - // FIXME: recommend `addr()` instead of `as usize` once that is stable. + /// pointers that are not guaranteed to be from the same allocation, use + /// `(self.addr() as isize - origin.addr() as isize) / size_of::()`. /// /// [`add`]: #method.add /// [allocation]: crate::ptr#allocation @@ -1084,7 +1028,7 @@ impl NonNull { #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[stable(feature = "non_null_convenience", since = "1.80.0")] #[rustc_const_stable(feature = "non_null_convenience", since = "1.80.0")] - #[requires(ub_checks::can_dereference(self.pointer))] + #[requires(ub_checks::can_dereference(self.as_ptr()))] pub const unsafe fn read(self) -> T where T: Sized, @@ -1106,7 +1050,7 @@ impl NonNull { #[inline] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[stable(feature = "non_null_convenience", since = "1.80.0")] - #[requires(ub_checks::can_dereference(self.pointer))] + #[requires(ub_checks::can_dereference(self.as_ptr()))] pub unsafe fn read_volatile(self) -> T where T: Sized, @@ -1127,7 +1071,7 @@ impl NonNull { #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[stable(feature = "non_null_convenience", since = "1.80.0")] #[rustc_const_stable(feature = "non_null_convenience", since = "1.80.0")] - #[requires(ub_checks::can_read_unaligned(self.pointer))] + #[requires(ub_checks::can_read_unaligned(self.as_ptr()))] pub const unsafe fn read_unaligned(self) -> T where T: Sized, @@ -1252,12 +1196,12 @@ impl NonNull { #[rustc_const_unstable(feature = "const_drop_in_place", issue = "109342")] #[requires(ub_checks::can_dereference(self.as_ptr() as *const()))] // Ensure self is aligned, initialized, and valid for read #[requires(ub_checks::can_write(self.as_ptr() as *mut()))] // Ensure self is valid for write - pub const unsafe fn drop_in_place(self) + pub const unsafe fn drop_in_place(mut self) where T: [const] Destruct, { // SAFETY: the caller must uphold the safety contract for `drop_in_place`. - unsafe { ptr::drop_in_place(self.as_ptr()) } + unsafe { ptr::drop_glue(self.as_mut()) } } /// Overwrites a memory location with the given value without reading or @@ -1446,14 +1390,14 @@ impl NonNull { let stride = crate::mem::size_of::(); // ZSTs if stride == 0 { - if self.pointer.addr() % align == 0 { + if self.as_ptr().addr() % align == 0 { return *result == 0; } else { return *result == usize::MAX; } } // In this case, the pointer cannot be aligned - if (align % stride == 0) && (self.pointer.addr() % stride != 0) { + if (align % stride == 0) && (self.as_ptr().addr() % stride != 0) { return *result == usize::MAX; } // Checking if the answer should indeed be usize::MAX when a % stride != 0 requires @@ -1463,11 +1407,11 @@ impl NonNull { return true; } // If we reach this case, either: - // - align % stride == 0 and self.pointer.addr() % stride == 0, so it is definitely possible to align the pointer + // - align % stride == 0 and self.as_ptr().addr() % stride == 0, so it is definitely possible to align the pointer // - align % stride != 0 and result != usize::MAX, so align_offset is claiming that it's possible to align the pointer // Check that applying the returned result does indeed produce an aligned address let product = usize::wrapping_mul(*result, stride); - let new_addr = usize::wrapping_add(product, self.pointer.addr()); + let new_addr = usize::wrapping_add(product, self.as_ptr().addr()); *result != usize::MAX && new_addr % align == 0 })] pub fn align_offset(self, align: usize) -> usize @@ -1634,12 +1578,12 @@ impl NonNull<[T]> { // validity requirements on `data`, so the postcondition must not // dereference the resulting pointer (`unsafe { result.as_ref() }.len()`, // as used previously, is UB for dangling or misaligned `data`). - #[ensures(|result| !result.pointer.is_null() - && result.pointer as *const T == data.pointer + #[ensures(|result| !result.as_ptr().is_null() + && result.as_ptr() as *const T == data.as_ptr() as *const T && result.len() == len)] pub const fn slice_from_raw_parts(data: NonNull, len: usize) -> Self { // SAFETY: `data` is a `NonNull` pointer which is necessarily non-null - unsafe { Self::new_unchecked(super::slice_from_raw_parts_mut(data.as_ptr(), len)) } + unsafe { Self::new_unchecked(data.as_ptr().cast_slice(len)) } } /// Returns the length of a non-null raw slice. @@ -1719,7 +1663,7 @@ impl NonNull<[T]> { #[unstable(feature = "slice_ptr_get", issue = "74265")] #[rustc_never_returns_null_ptr] // Address preservation - #[ensures(|result: &*mut T| *result == self.pointer as *mut T)] + #[ensures(|result: &*mut T| *result == self.as_ptr() as *mut T)] pub const fn as_mut_ptr(self) -> *mut T { self.as_non_null_ptr().as_ptr() } @@ -1854,9 +1798,10 @@ impl NonNull<[T]> { /// Returns a raw pointer to an element or subslice, without doing bounds /// checking. /// - /// Calling this method with an out-of-bounds index or when `self` is not dereferenceable + /// Calling this method with an [out-of-bounds index] or when `self` is not dereferenceable /// is *[undefined behavior]* even if the resulting pointer is not used. /// + /// [out-of-bounds index]: #method.add /// [undefined behavior]: https://doc.rust-lang.org/reference/behavior-considered-undefined.html /// /// # Examples @@ -1907,9 +1852,6 @@ impl CoerceUnsized> for NonNull #[unstable(feature = "dispatch_from_dyn", issue = "none")] impl DispatchFromDyn> for NonNull where T: Unsize {} -#[stable(feature = "pin", since = "1.33.0")] -unsafe impl PinCoerceUnsized for NonNull {} - #[stable(feature = "nonnull", since = "1.25.0")] impl fmt::Debug for NonNull { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { @@ -1964,7 +1906,7 @@ impl hash::Hash for NonNull { #[unstable(feature = "ptr_internals", issue = "none")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From> for NonNull { +const impl From> for NonNull { #[inline] fn from(unique: Unique) -> Self { unique.as_non_null_ptr() @@ -1973,7 +1915,7 @@ impl const From> for NonNull { #[stable(feature = "nonnull", since = "1.25.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From<&mut T> for NonNull { +const impl From<&mut T> for NonNull { /// Converts a `&mut T` to a `NonNull`. /// /// This conversion is safe and infallible since references cannot be null. @@ -1985,7 +1927,7 @@ impl const From<&mut T> for NonNull { #[stable(feature = "nonnull", since = "1.25.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From<&T> for NonNull { +const impl From<&T> for NonNull { /// Converts a `&T` to a `NonNull`. /// /// This conversion is safe and infallible since references cannot be null. diff --git a/library/core/src/ptr/unique.rs b/library/core/src/ptr/unique.rs index 0422d3d595067..2a95348bf0551 100644 --- a/library/core/src/ptr/unique.rs +++ b/library/core/src/ptr/unique.rs @@ -6,7 +6,6 @@ use crate::fmt; use crate::kani; use crate::marker::{PhantomData, PointeeSized, Unsize}; use crate::ops::{CoerceUnsized, DispatchFromDyn}; -use crate::pin::PinCoerceUnsized; use crate::ptr::NonNull; /// A wrapper around a raw non-null `*mut T` that indicates that the possessor @@ -186,9 +185,6 @@ impl CoerceUnsized> for Unique wh #[unstable(feature = "ptr_internals", issue = "none")] impl DispatchFromDyn> for Unique where T: Unsize {} -#[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -unsafe impl PinCoerceUnsized for Unique {} - #[unstable(feature = "ptr_internals", issue = "none")] impl fmt::Debug for Unique { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { @@ -205,7 +201,7 @@ impl fmt::Pointer for Unique { #[unstable(feature = "ptr_internals", issue = "none")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From<&mut T> for Unique { +const impl From<&mut T> for Unique { /// Converts a `&mut T` to a `Unique`. /// /// This conversion is infallible since references cannot be null. @@ -217,7 +213,7 @@ impl const From<&mut T> for Unique { #[unstable(feature = "ptr_internals", issue = "none")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From> for Unique { +const impl From> for Unique { /// Converts a `NonNull` to a `Unique`. /// /// This conversion is infallible since `NonNull` cannot be null. diff --git a/library/core/src/random.rs b/library/core/src/random.rs index 8a51fb289d8f3..d609d25cff51f 100644 --- a/library/core/src/random.rs +++ b/library/core/src/random.rs @@ -1,60 +1,262 @@ //! Random value generation. -use crate::range::RangeFull; +use crate::range::{RangeFull, RangeInclusive}; /// A source of randomness. #[unstable(feature = "random", issue = "130703")] -pub trait RandomSource { +pub trait Rng { /// Fills `bytes` with random bytes. /// /// Note that calling `fill_bytes` multiple times is not equivalent to calling `fill_bytes` once - /// with a larger buffer. A `RandomSource` is allowed to return different bytes for those two - /// cases. For instance, this allows a `RandomSource` to generate a word at a time and throw - /// part of it away if not needed. + /// with a larger buffer. An `Rng` is allowed to return different bytes for those two cases. For + /// instance, this allows an `Rng` to generate a word at a time and throw part of it away if not + /// needed. fn fill_bytes(&mut self, bytes: &mut [u8]); } +/// Implements `Rng` for mutable references to random number generators by +/// forwarding all methods to the referenced generator. +#[unstable(feature = "random", issue = "130703")] +impl<'a, R: Rng + ?Sized> Rng for &'a mut R { + fn fill_bytes(&mut self, bytes: &mut [u8]) { + R::fill_bytes(self, bytes); + } +} + /// A trait representing a distribution of random values for a type. #[unstable(feature = "random", issue = "130703")] pub trait Distribution { /// Samples a random value from the distribution, using the specified random source. - fn sample(&self, source: &mut (impl RandomSource + ?Sized)) -> T; + fn sample(&self, source: &mut (impl Rng + ?Sized)) -> T; } impl> Distribution for &DT { - fn sample(&self, source: &mut (impl RandomSource + ?Sized)) -> T { + fn sample(&self, source: &mut (impl Rng + ?Sized)) -> T { (*self).sample(source) } } impl Distribution for RangeFull { - fn sample(&self, source: &mut (impl RandomSource + ?Sized)) -> bool { + fn sample(&self, source: &mut (impl Rng + ?Sized)) -> bool { let byte: u8 = RangeFull.sample(source); byte & 1 == 1 } } -macro_rules! impl_primitive { +macro_rules! impl_full { ($t:ty) => { impl Distribution<$t> for RangeFull { - fn sample(&self, source: &mut (impl RandomSource + ?Sized)) -> $t { + fn sample(&self, source: &mut (impl Rng + ?Sized)) -> $t { let mut bytes = (0 as $t).to_ne_bytes(); source.fill_bytes(&mut bytes); - <$t>::from_ne_bytes(bytes) + // Always use little-endian for reproducibility. Since the vast majority of code is + // mainly or exclusively tested on LE targets, giving different PRNG results for the + // same seed on BE targets is a serious portability hazard. + <$t>::from_le_bytes(bytes) } } }; } -impl_primitive!(u8); -impl_primitive!(i8); -impl_primitive!(u16); -impl_primitive!(i16); -impl_primitive!(u32); -impl_primitive!(i32); -impl_primitive!(u64); -impl_primitive!(i64); -impl_primitive!(u128); -impl_primitive!(i128); -impl_primitive!(usize); -impl_primitive!(isize); +impl_full!(u8); +impl_full!(i8); +impl_full!(u16); +impl_full!(i16); +impl_full!(u32); +impl_full!(i32); +impl_full!(u64); +impl_full!(i64); +impl_full!(u128); +impl_full!(i128); +impl_full!(usize); +impl_full!(isize); + +#[cold] +fn empty_range() -> ! { + panic!("cannot sample from an empty distribution") +} + +macro_rules! lemire_sample { + ($name:ident($ty:ty)) => { + // Unbiased uniform sampling of a number within the range [0, bound). + // + // By performing some clever modular arithmetic, this algorithm manages + // to both reduce divisions and minimize the chance of sample rejections. + // + // Algorithm from: + // spellchecker:off + // Daniel Lemire. 2019. Fast Random Integer Generation in an Interval. + // ACM Trans. Model. Comput. Simul. 29, 1, Article 3 (January 2019), 12 pages. + // https://doi.org/10.1145/3230636 + // spellchecker:on + fn $name(bound: $ty, source: &mut (impl Rng + ?Sized)) -> $ty { + debug_assert_ne!(bound, 0); + + let sample: $ty = (..).sample(source); + + let (mut l, mut res) = sample.carrying_mul(bound, 0); + if l < bound { + let t = bound.wrapping_neg() % bound; + while l < t { + let sample: $ty = (..).sample(source); + (l, res) = sample.carrying_mul(bound, 0); + } + } + + debug_assert!(res < bound); + res + } + }; +} + +lemire_sample!(bounded32(u32)); +lemire_sample!(bounded64(u64)); +lemire_sample!(bounded128(u128)); + +macro_rules! impl_range { + ($unsigned:ty, $signed:ty as $base:ty => $bounded:ident) => { + impl Distribution<$unsigned> for RangeInclusive<$unsigned> { + /// Chooses a random number within the range. + /// + /// Every possible result value is equally likely. In other words, + /// this operation uses unbiased uniform sampling. + /// + /// # Panics + /// + /// Panics if the range is empty. + /// + /// # Side-channels + /// + /// This implementation does not claim to be resistant against side- + /// channel attacks. In particular, the execution time of this operation + /// may leak information about the returned value, and not just the + /// values of the range bounds. While this implementation tries to + /// avoid operations with particularly data-dependent timing (such + /// as divisions), Rust as a language has no facilities for ensuring + /// data-independent timing, voiding all promises about side-channel- + /// freedom. + /// + /// # Examples + /// + /// A D20 dice roll: + /// ``` + /// #![feature(random)] + /// + /// use std::random::{Distribution, SystemRng}; + /// use std::range::RangeInclusive; + /// + /// let roll = RangeInclusive::from(1..=20).sample(&mut SystemRng); + /// assert!(1 <= roll && roll <= 20); + /// if roll == 20 { + /// println!("Wow! You achieve writing a sound linked list."); + /// } else { + /// println!("Miri attacks!"); + /// } + /// ``` + #[inline] + fn sample(&self, source: &mut (impl Rng + ?Sized)) -> $unsigned { + if self.start > self.last { + empty_range(); + } + + if self.start == self.last { + return self.start; + } + + let Some(bound) = (self.last - self.start).checked_add(1) else { + // Overflow can only occur for Self::MIN..=Self::MAX, meaning + // the range is effectively unbounded. + return RangeFull.sample(source); + }; + + let offset = if bound.is_power_of_two() { + let sample: $unsigned = RangeFull.sample(source); + sample & (bound - 1) + } else { + $bounded(bound as $base, source) as $unsigned + }; + + self.start + offset + } + } + + impl Distribution<$signed> for RangeInclusive<$signed> { + /// Chooses a random number within the range. + /// + /// Every possible result value is equally likely. In other words, + /// this operation uses unbiased uniform sampling. + /// + /// # Panics + /// + /// Panics if the range is empty. + /// + /// # Side-channels + /// + /// This implementation does not claim to be resistant against side- + /// channel attacks. In particular, the execution time of this operation + /// may leak information about the returned value, and not just the + /// values of the range bounds. While this implementation tries to + /// avoid operations with particularly data-dependent timing (such + /// as divisions), Rust as a language has no facilities for ensuring + /// data-independent timing, voiding all promises about side-channel- + /// freedom. + /// + /// # Examples + /// + /// A D20 dice roll: + /// ``` + /// #![feature(random)] + /// + /// use std::random::{Distribution, SystemRng}; + /// use std::range::RangeInclusive; + /// + /// let roll = RangeInclusive::from(1..=20).sample(&mut SystemRng); + /// assert!(1 <= roll && roll <= 20); + /// if roll == 20 { + /// println!("Wow! You achieve writing a sound linked list."); + /// } else { + /// println!("Miri attacks!"); + /// } + /// ``` + #[inline] + fn sample(&self, source: &mut (impl Rng + ?Sized)) -> $signed { + if self.start > self.last { + empty_range(); + } + + if self.start == self.last { + return self.start; + } + + let Some(bound) = self.last.wrapping_sub(self.start).cast_unsigned().checked_add(1) + else { + // Overflow can only occur for Self::MIN..=Self::MAX, meaning + // the range is effectively unbounded. + return RangeFull.sample(source); + }; + + let offset = if bound.is_power_of_two() { + let sample: $unsigned = RangeFull.sample(source); + sample & (bound - 1) + } else { + $bounded(bound as $base, source) as $unsigned + }; + + self.start.wrapping_add_unsigned(offset) + } + } + }; +} + +// Use 32-bit integers for small integers since it reduces the likelihood of +// sample rejections. +impl_range!(u8, i8 as u32 => bounded32); +impl_range!(u16, i16 as u32 => bounded32); + +impl_range!(u32, i32 as u32 => bounded32); +impl_range!(u64, i64 as u64 => bounded64); +impl_range!(u128, i128 as u128 => bounded128); +#[cfg(any(target_pointer_width = "16", target_pointer_width = "32",))] +impl_range!(usize, isize as u32 => bounded32); +#[cfg(target_pointer_width = "64")] +impl_range!(usize, isize as u64 => bounded64); diff --git a/library/core/src/range.rs b/library/core/src/range.rs index 4b87d426bda76..557587b4e9a88 100644 --- a/library/core/src/range.rs +++ b/library/core/src/range.rs @@ -1,19 +1,18 @@ -//! # Experimental replacement range types +//! # Replacement range types //! -//! The types within this module are meant to replace the existing -//! `Range`, `RangeInclusive`, and `RangeFrom` types in a future edition. +//! The types within this module are meant to replace the legacy `Range`, +//! `RangeInclusive`, `RangeToInclusive` and `RangeFrom` types in a future edition. //! //! ``` -//! #![feature(new_range_api)] -//! use core::range::{Range, RangeFrom, RangeInclusive}; +//! use core::range::{Range, RangeFrom, RangeInclusive, RangeToInclusive}; //! //! let arr = [0, 1, 2, 3, 4]; -//! assert_eq!(arr[ .. ], [0, 1, 2, 3, 4]); -//! assert_eq!(arr[ .. 3 ], [0, 1, 2 ]); -//! assert_eq!(arr[ ..=3 ], [0, 1, 2, 3 ]); -//! assert_eq!(arr[ RangeFrom::from(1.. )], [ 1, 2, 3, 4]); -//! assert_eq!(arr[ Range::from(1..3 )], [ 1, 2 ]); -//! assert_eq!(arr[RangeInclusive::from(1..=3)], [ 1, 2, 3 ]); +//! assert_eq!(arr[ .. ], [0, 1, 2, 3, 4]); +//! assert_eq!(arr[ .. 3 ], [0, 1, 2 ]); +//! assert_eq!(arr[RangeToInclusive::from( ..=3)], [0, 1, 2, 3 ]); +//! assert_eq!(arr[ RangeFrom::from(1.. )], [ 1, 2, 3, 4]); +//! assert_eq!(arr[ Range::from(1..3 )], [ 1, 2 ]); +//! assert_eq!(arr[ RangeInclusive::from(1..=3)], [ 1, 2, 3 ]); //! ``` use crate::fmt; @@ -21,47 +20,61 @@ use crate::hash::Hash; mod iter; -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api_legacy", since = "1.98.0")] pub mod legacy; -use Bound::{Excluded, Included, Unbounded}; -#[doc(inline)] -pub use iter::{RangeFromIter, RangeInclusiveIter, RangeIter}; +use core::ops::Bound::{self, Excluded, Included, Unbounded}; #[doc(inline)] -pub use crate::iter::Step; +#[stable(feature = "new_range_from_api", since = "1.96.0")] +pub use iter::RangeFromIter; +#[doc(inline)] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] +pub use iter::RangeInclusiveIter; +#[doc(inline)] +#[stable(feature = "new_range_api", since = "1.96.0")] +pub use iter::RangeIter; + +use crate::iter::Step; +// FIXME(one_sided_range): These types should move into this module. +// FIXME(range_into_bounds): Ditto. Also consider re-exporting `RangeBounds` and related. +use crate::ops::{IntoBounds, OneSidedRange, OneSidedRangeBound, RangeBounds}; #[doc(inline)] -pub use crate::ops::{Bound, IntoBounds, OneSidedRange, RangeBounds, RangeFull, RangeTo}; +#[stable(feature = "new_range_api_exports", since = "1.98.0")] +pub use crate::ops::{RangeFull, RangeTo}; -/// A (half-open) range bounded inclusively below and exclusively above -/// (`start..end` in a future edition). +/// A (half-open) range bounded inclusively below and exclusively above. /// -/// The range `start..end` contains all values with `start <= x < end`. +/// The `Range` contains all values with `start <= x < end`. /// It is empty if `start >= end`. /// /// # Examples /// /// ``` -/// #![feature(new_range_api)] /// use core::range::Range; /// /// assert_eq!(Range::from(3..5), Range { start: 3, end: 5 }); /// assert_eq!(3 + 4 + 5, Range::from(3..6).into_iter().sum()); /// ``` +/// +/// # Edition notes +/// +/// It is planned that the syntax `start..end` will construct this +/// type in a future edition, but it does not do so today. #[lang = "RangeCopy"] #[derive(Copy, Hash)] #[derive_const(Clone, Default, PartialEq, Eq)] -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "1.96.0")] pub struct Range { /// The lower bound of the range (inclusive). - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_api", since = "1.96.0")] pub start: Idx, /// The upper bound of the range (exclusive). - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_api", since = "1.96.0")] pub end: Idx, } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "1.96.0")] impl fmt::Debug for Range { fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { self.start.fmt(fmt)?; @@ -79,7 +92,6 @@ impl Range { /// # Examples /// /// ``` - /// #![feature(new_range_api)] /// use core::range::Range; /// /// let mut i = Range::from(3..9).iter().map(|n| n*n); @@ -87,7 +99,7 @@ impl Range { /// assert_eq!(i.next(), Some(16)); /// assert_eq!(i.next(), Some(25)); /// ``` - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_api", since = "1.96.0")] #[inline] pub fn iter(&self) -> RangeIter { self.clone().into_iter() @@ -100,7 +112,6 @@ impl> Range { /// # Examples /// /// ``` - /// #![feature(new_range_api)] /// use core::range::Range; /// /// assert!(!Range::from(3..5).contains(&2)); @@ -117,7 +128,7 @@ impl> Range { /// assert!(!Range::from(f32::NAN..1.0).contains(&0.5)); /// ``` #[inline] - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] pub const fn contains(&self, item: &U) -> bool where @@ -132,7 +143,6 @@ impl> Range { /// # Examples /// /// ``` - /// #![feature(new_range_api)] /// use core::range::Range; /// /// assert!(!Range::from(3..5).is_empty()); @@ -143,7 +153,6 @@ impl> Range { /// The range is empty if either side is incomparable: /// /// ``` - /// #![feature(new_range_api)] /// use core::range::Range; /// /// assert!(!Range::from(3.0..5.0).is_empty()); @@ -151,7 +160,7 @@ impl> Range { /// assert!( Range::from(f32::NAN..5.0).is_empty()); /// ``` #[inline] - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] pub const fn is_empty(&self) -> bool where @@ -161,9 +170,9 @@ impl> Range { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for Range { +const impl RangeBounds for Range { fn start_bound(&self) -> Bound<&T> { Included(&self.start) } @@ -178,9 +187,9 @@ impl const RangeBounds for Range { /// If you need to use this implementation where `T` is unsized, /// consider using the `RangeBounds` impl for a 2-tuple of [`Bound<&T>`][Bound], /// i.e. replace `start..end` with `(Bound::Included(start), Bound::Excluded(end))`. -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for Range<&T> { +const impl RangeBounds for Range<&T> { fn start_bound(&self) -> Bound<&T> { Included(self.start) } @@ -189,62 +198,62 @@ impl const RangeBounds for Range<&T> { } } -// #[unstable(feature = "range_into_bounds", issue = "136903")] -#[unstable(feature = "new_range_api", issue = "125687")] +#[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const IntoBounds for Range { +const impl IntoBounds for Range { fn into_bounds(self) -> (Bound, Bound) { (Included(self.start), Excluded(self.end)) } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From> for legacy::Range { +const impl From> for legacy::Range { #[inline] fn from(value: Range) -> Self { Self { start: value.start, end: value.end } } } - -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From> for Range { +const impl From> for Range { #[inline] fn from(value: legacy::Range) -> Self { Self { start: value.start, end: value.end } } } -/// A range bounded inclusively below and above (`start..=last`). +/// A range bounded inclusively below and above. /// -/// The `RangeInclusive` `start..=last` contains all values with `x >= start` +/// The `RangeInclusive` contains all values with `x >= start` /// and `x <= last`. It is empty unless `start <= last`. /// /// # Examples /// -/// The `start..=last` syntax is a `RangeInclusive`: -/// /// ``` -/// #![feature(new_range_api)] /// use core::range::RangeInclusive; /// /// assert_eq!(RangeInclusive::from(3..=5), RangeInclusive { start: 3, last: 5 }); /// assert_eq!(3 + 4 + 5, RangeInclusive::from(3..=5).into_iter().sum()); /// ``` +/// +/// # Edition notes +/// +/// It is planned that the syntax `start..=last` will construct this +/// type in a future edition, but it does not do so today. #[lang = "RangeInclusiveCopy"] #[derive(Clone, Copy, PartialEq, Eq, Hash)] -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] pub struct RangeInclusive { /// The lower bound of the range (inclusive). - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] pub start: Idx, /// The upper bound of the range (inclusive). - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] pub last: Idx, } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] impl fmt::Debug for RangeInclusive { fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { self.start.fmt(fmt)?; @@ -260,7 +269,6 @@ impl> RangeInclusive { /// # Examples /// /// ``` - /// #![feature(new_range_api)] /// use core::range::RangeInclusive; /// /// assert!(!RangeInclusive::from(3..=5).contains(&2)); @@ -278,7 +286,7 @@ impl> RangeInclusive { /// assert!(!RangeInclusive::from(f32::NAN..=1.0).contains(&1.0)); /// ``` #[inline] - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] pub const fn contains(&self, item: &U) -> bool where @@ -293,7 +301,6 @@ impl> RangeInclusive { /// # Examples /// /// ``` - /// #![feature(new_range_api)] /// use core::range::RangeInclusive; /// /// assert!(!RangeInclusive::from(3..=5).is_empty()); @@ -304,14 +311,13 @@ impl> RangeInclusive { /// The range is empty if either side is incomparable: /// /// ``` - /// #![feature(new_range_api)] /// use core::range::RangeInclusive; /// /// assert!(!RangeInclusive::from(3.0..=5.0).is_empty()); /// assert!( RangeInclusive::from(3.0..=f32::NAN).is_empty()); /// assert!( RangeInclusive::from(f32::NAN..=5.0).is_empty()); /// ``` - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[inline] #[rustc_const_unstable(feature = "const_range", issue = "none")] pub const fn is_empty(&self) -> bool @@ -330,7 +336,6 @@ impl RangeInclusive { /// # Examples /// /// ``` - /// #![feature(new_range_api)] /// use core::range::RangeInclusive; /// /// let mut i = RangeInclusive::from(3..=8).iter().map(|n| n*n); @@ -338,25 +343,16 @@ impl RangeInclusive { /// assert_eq!(i.next(), Some(16)); /// assert_eq!(i.next(), Some(25)); /// ``` - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[inline] pub fn iter(&self) -> RangeInclusiveIter { self.clone().into_iter() } } -impl RangeInclusive { - /// Converts to an exclusive `Range` for `SliceIndex` implementations. - /// The caller is responsible for dealing with `last == usize::MAX`. - #[inline] - pub(crate) const fn into_slice_range(self) -> Range { - Range { start: self.start, end: self.last + 1 } - } -} - -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeInclusive { +const impl RangeBounds for RangeInclusive { fn start_bound(&self) -> Bound<&T> { Included(&self.start) } @@ -371,9 +367,9 @@ impl const RangeBounds for RangeInclusive { /// If you need to use this implementation where `T` is unsized, /// consider using the `RangeBounds` impl for a 2-tuple of [`Bound<&T>`][Bound], /// i.e. replace `start..=end` with `(Bound::Included(start), Bound::Included(end))`. -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeInclusive<&T> { +const impl RangeBounds for RangeInclusive<&T> { fn start_bound(&self) -> Bound<&T> { Included(self.start) } @@ -382,31 +378,71 @@ impl const RangeBounds for RangeInclusive<&T> { } } -// #[unstable(feature = "range_into_bounds", issue = "136903")] -#[unstable(feature = "new_range_api", issue = "125687")] +// #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] +#[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const IntoBounds for RangeInclusive { +const impl IntoBounds for RangeInclusive { fn into_bounds(self) -> (Bound, Bound) { (Included(self.start), Included(self.last)) } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From> for legacy::RangeInclusive { +const impl From> for legacy::RangeInclusive { #[inline] fn from(value: RangeInclusive) -> Self { Self::new(value.start, value.last) } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From> for RangeInclusive { +const impl From> for RangeInclusive { + /// Converts from a legacy range to a non-legacy range, potentially panicking. + /// + /// # Panics + /// + /// If the legacy range iterator has been exhausted, + /// this function will either panic or return an empty range. + /// + /// # Examples + /// + /// ``` + /// use core::range::legacy; + /// use core::range::RangeInclusive; + /// + /// let single: legacy::RangeInclusive = 0..=1; + /// let single = RangeInclusive::from(single); + /// assert_eq!((single.start, single.last), (0, 1)); + /// + /// let empty: legacy::RangeInclusive = 0..=0; + /// let empty = RangeInclusive::from(empty); + /// assert_eq!((empty.start, empty.last), (0, 0)); + /// ``` + /// + /// ``` + /// # // This test requires unwinding to work. + /// # // Disable it when unwinding isn't available. + /// # #[cfg(panic = "unwind")] + /// # fn main() { + /// use core::range::legacy; + /// use core::range::RangeInclusive; + /// use std::panic::catch_unwind; + /// + /// let mut exhausted: legacy::RangeInclusive = 0..=0; + /// exhausted.next(); + /// let result = catch_unwind(|| RangeInclusive::from(exhausted)); + /// // The `from` call either panicked or returned an empty range. + /// assert!(result.is_err() || result.is_ok_and(|range| range.is_empty())); + /// # } + /// # #[cfg(not(panic = "unwind"))] + /// # fn main() {} + /// ``` #[inline] fn from(value: legacy::RangeInclusive) -> Self { assert!( !value.exhausted, - "attempted to convert from an exhausted `legacy::RangeInclusive` (unspecified behavior)" + "attempted to convert from an exhausted `legacy::RangeInclusive`" ); let (start, last) = value.into_inner(); @@ -414,43 +450,44 @@ impl const From> for RangeInclusive { } } -/// A range only bounded inclusively below (`start..`). +/// A range only bounded inclusively below. /// -/// The `RangeFrom` `start..` contains all values with `x >= start`. +/// The `RangeFrom` contains all values with `x >= start`. /// -/// *Note*: Overflow in the [`Iterator`] implementation (when the contained +/// *Note*: Overflow in the [`IntoIterator`] implementation (when the contained /// data type reaches its numerical limit) is allowed to panic, wrap, or /// saturate. This behavior is defined by the implementation of the [`Step`] /// trait. For primitive integers, this follows the normal rules, and respects -/// the overflow checks profile (panic in debug, wrap in release). Note also -/// that overflow happens earlier than you might assume: the overflow happens -/// in the call to `next` that yields the maximum value, as the range must be -/// set to a state to yield the next value. +/// the overflow checks profile (panic in debug, wrap in release). Unlike +/// its legacy counterpart, the iterator will only panic after yielding the +/// maximum value when overflow checks are enabled. /// /// [`Step`]: crate::iter::Step /// /// # Examples /// -/// The `start..` syntax is a `RangeFrom`: -/// /// ``` -/// #![feature(new_range_api)] /// use core::range::RangeFrom; /// /// assert_eq!(RangeFrom::from(2..), core::range::RangeFrom { start: 2 }); /// assert_eq!(2 + 3 + 4, RangeFrom::from(2..).into_iter().take(3).sum()); /// ``` +/// +/// # Edition notes +/// +/// It is planned that the syntax `start..` will construct this +/// type in a future edition, but it does not do so today. #[lang = "RangeFromCopy"] #[derive(Copy, Hash)] #[derive_const(Clone, PartialEq, Eq)] -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] pub struct RangeFrom { /// The lower bound of the range (inclusive). - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_from_api", since = "1.96.0")] pub start: Idx, } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] impl fmt::Debug for RangeFrom { fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { self.start.fmt(fmt)?; @@ -467,7 +504,6 @@ impl RangeFrom { /// # Examples /// /// ``` - /// #![feature(new_range_api)] /// use core::range::RangeFrom; /// /// let mut i = RangeFrom::from(3..).iter().map(|n| n*n); @@ -475,7 +511,7 @@ impl RangeFrom { /// assert_eq!(i.next(), Some(16)); /// assert_eq!(i.next(), Some(25)); /// ``` - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_from_api", since = "1.96.0")] #[inline] pub fn iter(&self) -> RangeFromIter { self.clone().into_iter() @@ -488,7 +524,6 @@ impl> RangeFrom { /// # Examples /// /// ``` - /// #![feature(new_range_api)] /// use core::range::RangeFrom; /// /// assert!(!RangeFrom::from(3..).contains(&2)); @@ -500,7 +535,7 @@ impl> RangeFrom { /// assert!(!RangeFrom::from(f32::NAN..).contains(&0.5)); /// ``` #[inline] - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_from_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] pub const fn contains(&self, item: &U) -> bool where @@ -511,9 +546,9 @@ impl> RangeFrom { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeFrom { +const impl RangeBounds for RangeFrom { fn start_bound(&self) -> Bound<&T> { Included(&self.start) } @@ -528,9 +563,9 @@ impl const RangeBounds for RangeFrom { /// If you need to use this implementation where `T` is unsized, /// consider using the `RangeBounds` impl for a 2-tuple of [`Bound<&T>`][Bound], /// i.e. replace `start..` with `(Bound::Included(start), Bound::Unbounded)`. -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeFrom<&T> { +const impl RangeBounds for RangeFrom<&T> { fn start_bound(&self) -> Bound<&T> { Included(self.start) } @@ -539,45 +574,52 @@ impl const RangeBounds for RangeFrom<&T> { } } -// #[unstable(feature = "range_into_bounds", issue = "136903")] -#[unstable(feature = "new_range_api", issue = "125687")] +#[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const IntoBounds for RangeFrom { +const impl IntoBounds for RangeFrom { fn into_bounds(self) -> (Bound, Bound) { (Included(self.start), Unbounded) } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[unstable(feature = "one_sided_range", issue = "69780")] +#[rustc_const_unstable(feature = "const_range", issue = "none")] +const impl OneSidedRange for RangeFrom +where + Self: RangeBounds, +{ + fn bound(self) -> (OneSidedRangeBound, T) { + (OneSidedRangeBound::StartInclusive, self.start) + } +} + +#[stable(feature = "new_range_from_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -impl const From> for legacy::RangeFrom { +const impl From> for legacy::RangeFrom { #[inline] fn from(value: RangeFrom) -> Self { Self { start: value.start } } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -impl const From> for RangeFrom { +const impl From> for RangeFrom { #[inline] fn from(value: legacy::RangeFrom) -> Self { Self { start: value.start } } } -/// A range only bounded inclusively above (`..=last`). +/// A range only bounded inclusively above. /// -/// The `RangeToInclusive` `..=last` contains all values with `x <= last`. +/// The `RangeToInclusive` contains all values with `x <= last`. /// It cannot serve as an [`Iterator`] because it doesn't have a starting point. /// /// # Examples /// -/// The `..=last` syntax is a `RangeToInclusive`: -/// -/// ``` -/// #![feature(new_range_api)] +/// ```standalone_crate /// #![feature(new_range)] -/// assert_eq!((..=5), std::range::RangeToInclusive{ last: 5 }); +/// assert_eq!((..=5), std::range::RangeToInclusive { last: 5 }); /// ``` /// /// It does not have an [`IntoIterator`] implementation, so you can't use it in a @@ -605,17 +647,22 @@ impl const From> for RangeFrom { /// ``` /// /// [slicing index]: crate::slice::SliceIndex +/// +/// # Edition notes +/// +/// It is planned that the syntax `..=last` will construct this +/// type in a future edition, but it does not do so today. #[lang = "RangeToInclusiveCopy"] #[doc(alias = "..=")] #[derive(Copy, Clone, PartialEq, Eq, Hash)] -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] pub struct RangeToInclusive { /// The upper bound of the range (inclusive) - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] pub last: Idx, } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] impl fmt::Debug for RangeToInclusive { fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { write!(fmt, "..=")?; @@ -639,7 +686,7 @@ impl> RangeToInclusive { /// assert!(!(..=f32::NAN).contains(&0.5)); /// ``` #[inline] - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] pub const fn contains(&self, item: &U) -> bool where @@ -650,12 +697,13 @@ impl> RangeToInclusive { } } +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] impl From> for RangeToInclusive { fn from(value: legacy::RangeToInclusive) -> Self { Self { last: value.end } } } - +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] impl From> for legacy::RangeToInclusive { fn from(value: RangeToInclusive) -> Self { Self { end: value.last } @@ -665,9 +713,9 @@ impl From> for legacy::RangeToInclusive { // RangeToInclusive cannot impl From> // because underflow would be possible with (..0).into() -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeToInclusive { +const impl RangeBounds for RangeToInclusive { fn start_bound(&self) -> Bound<&T> { Unbounded } @@ -676,10 +724,32 @@ impl const RangeBounds for RangeToInclusive { } } +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] +#[rustc_const_unstable(feature = "const_range", issue = "none")] +const impl RangeBounds for RangeToInclusive<&T> { + fn start_bound(&self) -> Bound<&T> { + Unbounded + } + fn end_bound(&self) -> Bound<&T> { + Included(self.last) + } +} + #[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const IntoBounds for RangeToInclusive { +const impl IntoBounds for RangeToInclusive { fn into_bounds(self) -> (Bound, Bound) { (Unbounded, Included(self.last)) } } + +#[unstable(feature = "one_sided_range", issue = "69780")] +#[rustc_const_unstable(feature = "const_range", issue = "none")] +const impl OneSidedRange for RangeToInclusive +where + Self: RangeBounds, +{ + fn bound(self) -> (OneSidedRangeBound, T) { + (OneSidedRangeBound::EndInclusive, self.last) + } +} diff --git a/library/core/src/range/iter.rs b/library/core/src/range/iter.rs index 6631fb2ce583c..fe29ae7449c27 100644 --- a/library/core/src/range/iter.rs +++ b/library/core/src/range/iter.rs @@ -10,12 +10,27 @@ use crate::range::{Range, RangeFrom, RangeInclusive, legacy}; use crate::{intrinsics, mem}; /// By-value [`Range`] iterator. -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "1.96.0")] #[derive(Debug, Clone)] -pub struct RangeIter(legacy::Range); +pub struct RangeIter(pub(crate) legacy::Range); impl RangeIter { + #[unstable(feature = "new_range_remainder", issue = "154458")] /// Returns the remainder of the range being iterated over. + /// + /// # Examples + /// + /// ``` + /// #![feature(new_range_remainder)] + /// + /// let range = core::range::Range::from(3..11); + /// let mut iter = range.into_iter(); + /// assert_eq!(iter.clone().remainder(), range); + /// iter.next(); + /// assert_eq!(iter.clone().remainder(), core::range::Range::from(4..11)); + /// iter.by_ref().for_each(drop); + /// assert!(iter.remainder().is_empty()); + /// ``` pub fn remainder(self) -> Range { Range { start: self.0.start, end: self.0.end } } @@ -53,7 +68,7 @@ unsafe_range_trusted_random_access_impl! { u64 i64 } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "1.96.0")] impl Iterator for RangeIter { type Item = A; @@ -123,7 +138,7 @@ impl Iterator for RangeIter { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "1.96.0")] impl DoubleEndedIterator for RangeIter { #[inline] fn next_back(&mut self) -> Option { @@ -144,10 +159,10 @@ impl DoubleEndedIterator for RangeIter { #[unstable(feature = "trusted_len", issue = "37572")] unsafe impl TrustedLen for RangeIter {} -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "1.96.0")] impl FusedIterator for RangeIter {} -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "1.96.0")] impl IntoIterator for Range { type Item = A; type IntoIter = RangeIter; @@ -158,7 +173,7 @@ impl IntoIterator for Range { } /// By-value [`RangeInclusive`] iterator. -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[derive(Debug, Clone)] pub struct RangeInclusiveIter(legacy::RangeInclusive); @@ -166,6 +181,21 @@ impl RangeInclusiveIter { /// Returns the remainder of the range being iterated over. /// /// If the iterator is exhausted or empty, returns `None`. + /// + /// # Examples + /// + /// ``` + /// #![feature(new_range_remainder)] + /// + /// let range = core::range::RangeInclusive::from(3..=11); + /// let mut iter = range.into_iter(); + /// assert_eq!(iter.clone().remainder().unwrap(), range); + /// iter.next(); + /// assert_eq!(iter.clone().remainder().unwrap(), core::range::RangeInclusive::from(4..=11)); + /// iter.by_ref().for_each(drop); + /// assert!(iter.remainder().is_none()); + /// ``` + #[unstable(feature = "new_range_remainder", issue = "154458")] pub fn remainder(self) -> Option> { if self.0.is_empty() { return None; @@ -175,7 +205,7 @@ impl RangeInclusiveIter { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] impl Iterator for RangeInclusiveIter { type Item = A; @@ -231,7 +261,7 @@ impl Iterator for RangeInclusiveIter { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] impl DoubleEndedIterator for RangeInclusiveIter { #[inline] fn next_back(&mut self) -> Option { @@ -252,10 +282,10 @@ impl DoubleEndedIterator for RangeInclusiveIter { #[unstable(feature = "trusted_len", issue = "37572")] unsafe impl TrustedLen for RangeInclusiveIter {} -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] impl FusedIterator for RangeInclusiveIter {} -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] impl IntoIterator for RangeInclusive { type Item = A; type IntoIter = RangeInclusiveIter; @@ -275,14 +305,14 @@ impl IntoIterator for RangeInclusive { // since e.g. `(0..=u64::MAX).len()` would be `u64::MAX + 1`. macro_rules! range_exact_iter_impl { ($($t:ty)*) => ($( - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_api", since = "1.96.0")] impl ExactSizeIterator for RangeIter<$t> { } )*) } macro_rules! range_incl_exact_iter_impl { ($($t:ty)*) => ($( - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] impl ExactSizeIterator for RangeInclusiveIter<$t> { } )*) } @@ -298,45 +328,75 @@ range_incl_exact_iter_impl! { } /// By-value [`RangeFrom`] iterator. -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] #[derive(Debug, Clone)] pub struct RangeFromIter { start: A, - /// Whether the first element of the iterator has yielded. + /// Whether the maximum value of the iterator has yielded. /// Only used when overflow checks are enabled. - first: bool, + exhausted: bool, } impl RangeFromIter { /// Returns the remainder of the range being iterated over. + /// + /// # Examples + /// + /// ``` + /// #![feature(new_range_remainder)] + /// + /// let range = core::range::RangeFrom::from(3..); + /// let mut iter = range.into_iter(); + /// assert_eq!(iter.clone().remainder(), range); + /// iter.next(); + /// assert_eq!(iter.remainder(), core::range::RangeFrom::from(4..)); + /// ``` #[inline] #[rustc_inherit_overflow_checks] + #[unstable(feature = "new_range_remainder", issue = "154458")] pub fn remainder(self) -> RangeFrom { - if intrinsics::overflow_checks() { - if !self.first { - return RangeFrom { start: Step::forward(self.start, 1) }; - } + // Need to handle this case even if overflow-checks are disabled, + // because a `RangeFromIter` could be exhausted in a crate with + // overflow-checks enabled, but then passed to a crate with them + // disabled before this is called. + if self.exhausted { + return RangeFrom { start: Step::forward(self.start, 1) }; } RangeFrom { start: self.start } } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] impl Iterator for RangeFromIter { type Item = A; #[inline] #[rustc_inherit_overflow_checks] fn next(&mut self) -> Option { + if self.exhausted { + // This should panic if overflow checks are enabled, since + // `forward_checked` returned `None` in prior iteration. + self.start = Step::forward(self.start.clone(), 1); + + // If we get here, if means this iterator was exhausted by a crate + // with overflow-checks enabled, but now we're iterating in a crate with + // overflow-checks disabled. Since we successfully incremented `self.start` + // above (in many cases this will wrap around to MIN), we now unset + // the flag so we don't repeat this process in the next iteration. + // + // This could also happen if `forward_checked` returned None but + // (for whatever reason, not applicable to any std implementors) + // `forward` doesn't panic when overflow-checks are enabled. In that + // case, this is also the correct behavior. + self.exhausted = false; + } if intrinsics::overflow_checks() { - if self.first { - self.first = false; + let Some(n) = Step::forward_checked(self.start.clone(), 1) else { + self.exhausted = true; return Some(self.start.clone()); - } - - self.start = Step::forward(self.start.clone(), 1); - return Some(self.start.clone()); + }; + return Some(mem::replace(&mut self.start, n)); } let n = Step::forward(self.start.clone(), 1); @@ -351,18 +411,22 @@ impl Iterator for RangeFromIter { #[inline] #[rustc_inherit_overflow_checks] fn nth(&mut self, n: usize) -> Option { + // Typically `forward` will cause an overflow-check panic here, + // but unset the exhausted flag to handle the uncommon cases. + // See the comments in `next` for more details. + if self.exhausted { + self.start = Step::forward(self.start.clone(), 1); + self.exhausted = false; + } if intrinsics::overflow_checks() { - if self.first { - self.first = false; - - let plus_n = Step::forward(self.start.clone(), n); + let plus_n = Step::forward(self.start.clone(), n); + if let Some(plus_n1) = Step::forward_checked(plus_n.clone(), 1) { + self.start = plus_n1; + } else { self.start = plus_n.clone(); - return Some(plus_n); + self.exhausted = true; } - - let plus_n = Step::forward(self.start.clone(), n); - self.start = Step::forward(plus_n.clone(), 1); - return Some(self.start.clone()); + return Some(plus_n); } let plus_n = Step::forward(self.start.clone(), n); @@ -374,15 +438,15 @@ impl Iterator for RangeFromIter { #[unstable(feature = "trusted_len", issue = "37572")] unsafe impl TrustedLen for RangeFromIter {} -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] impl FusedIterator for RangeFromIter {} -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] impl IntoIterator for RangeFrom { type Item = A; type IntoIter = RangeFromIter; fn into_iter(self) -> Self::IntoIter { - RangeFromIter { start: self.start, first: true } + RangeFromIter { start: self.start, exhausted: false } } } diff --git a/library/core/src/range/legacy.rs b/library/core/src/range/legacy.rs index aa11331382dd0..c1bac705f80b3 100644 --- a/library/core/src/range/legacy.rs +++ b/library/core/src/range/legacy.rs @@ -7,4 +7,5 @@ //! The types here are equivalent to those in [`core::ops`]. #[doc(inline)] +#[stable(feature = "new_range_api_legacy", since = "1.98.0")] pub use crate::ops::{Range, RangeFrom, RangeInclusive, RangeToInclusive}; diff --git a/library/core/src/result.rs b/library/core/src/result.rs index 5f438d72ac13c..b257cd8c82a0e 100644 --- a/library/core/src/result.rs +++ b/library/core/src/result.rs @@ -114,14 +114,15 @@ //! //! You might instead, if you don't want to handle the error, simply //! assert success with [`expect`]. This will panic if the -//! write fails, providing a marginally useful message indicating why: +//! write fails, providing a message explaining why the write was expected +//! to succeed: //! //! ```no_run //! use std::fs::File; //! use std::io::prelude::*; //! //! let mut file = File::create("valuable_data.txt").unwrap(); -//! file.write_all(b"important message").expect("failed to write message"); +//! file.write_all(b"important message").expect("writing to the file should succeed"); //! ``` //! //! You might also simply assert success: @@ -912,8 +913,6 @@ impl Result { /// # Examples /// /// ``` - /// #![feature(result_option_map_or_default)] - /// /// let x: Result<_, &str> = Ok("foo"); /// let y: Result<&str, _> = Err("bar"); /// @@ -923,7 +922,7 @@ impl Result { /// /// [default value]: Default::default #[inline] - #[unstable(feature = "result_option_map_or_default", issue = "138099")] + #[stable(feature = "result_option_map_or_default", since = "1.98.0")] #[rustc_const_unstable(feature = "const_result_trait_fn", issue = "144211")] pub const fn map_or_default(self, f: F) -> U where @@ -980,7 +979,7 @@ impl Result { /// .parse::() /// .inspect(|x| println!("original: {x}")) /// .map(|x| x.pow(3)) - /// .expect("failed to parse number"); + /// .expect("literal `4` should parse as a `u8`"); /// ``` #[inline] #[stable(feature = "result_option_inspect", since = "1.76.0")] @@ -1682,7 +1681,12 @@ impl Result { #[inline] #[track_caller] #[stable(feature = "option_result_unwrap_unchecked", since = "1.58.0")] - pub unsafe fn unwrap_err_unchecked(self) -> E { + #[rustc_const_unstable(feature = "const_result_unwrap_unchecked", issue = "148714")] + pub const unsafe fn unwrap_err_unchecked(self) -> E + where + T: [const] Destruct, + E: [const] Destruct, + { match self { // SAFETY: the safety contract must be upheld by the caller. Ok(_) => unsafe { hint::unreachable_unchecked() }, @@ -2159,7 +2163,7 @@ impl> FromIterator> for Result { #[unstable(feature = "try_trait_v2", issue = "84277", old_name = "try_trait")] #[rustc_const_unstable(feature = "const_try", issue = "74935")] -impl const ops::Try for Result { +const impl ops::Try for Result { type Output = T; type Residual = Result; @@ -2179,7 +2183,7 @@ impl const ops::Try for Result { #[unstable(feature = "try_trait_v2", issue = "84277", old_name = "try_trait")] #[rustc_const_unstable(feature = "const_try", issue = "74935")] -impl> const ops::FromResidual> +const impl> ops::FromResidual> for Result { #[inline] @@ -2193,7 +2197,7 @@ impl> const ops::FromResidual> const ops::FromResidual> for Result { +const impl> ops::FromResidual> for Result { #[inline] fn from_residual(ops::Yeet(e): ops::Yeet) -> Self { Err(From::from(e)) @@ -2202,6 +2206,6 @@ impl> const ops::FromResidual> for Result< #[unstable(feature = "try_trait_v2_residual", issue = "91285")] #[rustc_const_unstable(feature = "const_try", issue = "74935")] -impl const ops::Residual for Result { +const impl ops::Residual for Result { type TryType = Result; } diff --git a/library/core/src/slice/ascii.rs b/library/core/src/slice/ascii.rs index 82c45a04e3dd7..6d2f297076c18 100644 --- a/library/core/src/slice/ascii.rs +++ b/library/core/src/slice/ascii.rs @@ -64,7 +64,10 @@ impl [u8] { return false; } - #[cfg(all(target_arch = "x86_64", target_feature = "sse2"))] + #[cfg(any( + all(target_arch = "x86_64", target_feature = "sse2"), + all(target_arch = "aarch64", target_feature = "neon") + ))] { const CHUNK_SIZE: usize = 16; // The following function has two invariants: @@ -90,7 +93,7 @@ impl [u8] { let mut b = other; while let ([first_a, rest_a @ ..], [first_b, rest_b @ ..]) = (a, b) { - if first_a.eq_ignore_ascii_case(&first_b) { + if first_a.eq_ignore_ascii_case(first_b) { a = rest_a; b = rest_b; } else { @@ -110,7 +113,10 @@ impl [u8] { /// /// The caller must guarantee that the slices are equal in length, and the /// slice lengths are greater than or equal to `N` bytes. - #[cfg(all(target_arch = "x86_64", target_feature = "sse2"))] + #[cfg(any( + all(target_arch = "x86_64", target_feature = "sse2"), + all(target_arch = "aarch64", target_feature = "neon") + ))] #[inline] const fn eq_ignore_ascii_case_chunks(&self, other: &[u8]) -> bool { // FIXME(const-hack): The while-loops that follow should be replaced by @@ -224,7 +230,11 @@ impl [u8] { /// Returns a byte slice with leading ASCII whitespace bytes removed. /// /// 'Whitespace' refers to the definition used by - /// [`u8::is_ascii_whitespace`]. + /// [`u8::is_ascii_whitespace`]. Importantly, this definition excludes + /// the `\0x0B` byte even though it has the Unicode [`White_Space`] property + /// and is removed by [`str::trim_start`]. + /// + /// [`White_Space`]: https://www.unicode.org/reports/tr44/#White_Space /// /// # Examples /// @@ -253,7 +263,11 @@ impl [u8] { /// Returns a byte slice with trailing ASCII whitespace bytes removed. /// /// 'Whitespace' refers to the definition used by - /// [`u8::is_ascii_whitespace`]. + /// [`u8::is_ascii_whitespace`]. Importantly, this definition excludes + /// the `\0x0B` byte even though it has the Unicode [`White_Space`] property + /// and is removed by [`str::trim_end`]. + /// + /// [`White_Space`]: https://www.unicode.org/reports/tr44/#White_Space /// /// # Examples /// @@ -283,7 +297,11 @@ impl [u8] { /// removed. /// /// 'Whitespace' refers to the definition used by - /// [`u8::is_ascii_whitespace`]. + /// [`u8::is_ascii_whitespace`]. Importantly, this definition excludes + /// the `\0x0B` byte even though it has the Unicode [`White_Space`] property + /// and is removed by [`str::trim`]. + /// + /// [`White_Space`]: https://www.unicode.org/reports/tr44/#White_Space /// /// # Examples /// @@ -376,7 +394,7 @@ impl<'a> fmt::Display for EscapeAscii<'a> { b > 0x7E || b < 0x20 || b == b'\\' || b == b'\'' || b == b'"' } - while bytes.len() > 0 { + while !bytes.is_empty() { // fast path for the printable, non-escaped subset of ascii let prefix = bytes.iter().take_while(|&&b| !needs_escape(b)).count(); // SAFETY: prefix length was derived by counting bytes in the same splice, so it's in-bounds @@ -441,7 +459,8 @@ pub const fn is_ascii_simple(mut bytes: &[u8]) -> bool { /// (above) returns true, then we know the answer is false. #[cfg(not(any( all(target_arch = "x86_64", target_feature = "sse2"), - all(target_arch = "loongarch64", target_feature = "lsx") + all(target_arch = "loongarch64", target_feature = "lsx"), + all(target_arch = "aarch64", target_feature = "neon") )))] #[inline] #[rustc_allow_const_fn_unstable(const_eval_select)] // fallback impl has same behavior @@ -578,24 +597,81 @@ fn is_ascii_sse2(bytes: &[u8]) -> bool { rest.iter().all(|b| b.is_ascii()) } -/// ASCII test optimized to use the `pmovmskb` instruction on `x86-64`. -/// -/// Uses explicit SSE2 intrinsics to prevent LLVM from auto-vectorizing with -/// broken AVX-512 code that extracts mask bits one-by-one. -#[cfg(all(target_arch = "x86_64", target_feature = "sse2"))] +/// Chunk size for NEON vectorized ASCII checking (4x 16-byte loads). +#[cfg(all(target_arch = "aarch64", target_feature = "neon"))] +const NEON_CHUNK_SIZE: usize = 64; + +/// Width of a single NEON vector, used to vectorize the tail left over by the +/// unrolled `NEON_CHUNK_SIZE` loop. +#[cfg(all(target_arch = "aarch64", target_feature = "neon"))] +const NEON_VECTOR_SIZE: usize = 16; + +#[cfg(all(target_arch = "aarch64", target_feature = "neon"))] +#[inline] +fn is_ascii_neon(bytes: &[u8]) -> bool { + use crate::arch::aarch64::{vld1q_u8, vmaxvq_u8, vorrq_u8}; + + let (chunks, rest) = bytes.as_chunks::(); + + for chunk in chunks { + let ptr = chunk.as_ptr(); + // SAFETY: chunk is 64 bytes, and `vld1q_u8` has no alignment requirement. + let max = unsafe { + let a1 = vld1q_u8(ptr); + let a2 = vld1q_u8(ptr.add(16)); + let b1 = vld1q_u8(ptr.add(32)); + let b2 = vld1q_u8(ptr.add(48)); + // OR all chunks - if any byte has high bit set, combined will too. + let combined = vorrq_u8(vorrq_u8(a1, a2), vorrq_u8(b1, b2)); + // `vmaxvq_u8` is a horizontal reduction with a longer latency than + // `vorrq_u8`, so it runs once per 64 bytes rather than once per load. + vmaxvq_u8(combined) + }; + if max >= 128 { + return false; + } + } + + // The unrolled loop above leaves up to 63 bytes, so sweep those a vector at + // a time before falling back to a byte-at-a-time check. + let (vectors, rest) = rest.as_chunks::(); + + for vector in vectors { + // SAFETY: vector is 16 bytes, and `vld1q_u8` has no alignment requirement. + let max = unsafe { vmaxvq_u8(vld1q_u8(vector.as_ptr())) }; + if max >= 128 { + return false; + } + } + + // Handle remaining bytes + rest.iter().all(|b| b.is_ascii()) +} + +/// Uses explicit SIMD intrinsics to prevent LLVM from auto-vectorizing with +/// broken code (e.g., AVX-512 on x86-64 that extracts mask bits one-by-one). +#[cfg(any( + all(target_arch = "x86_64", target_feature = "sse2"), + all(target_arch = "aarch64", target_feature = "neon") +))] #[inline] #[rustc_allow_const_fn_unstable(const_eval_select)] const fn is_ascii(bytes: &[u8]) -> bool { const USIZE_SIZE: usize = size_of::(); const NONASCII_MASK: usize = usize::MAX / 255 * 0x80; + #[cfg(all(target_arch = "x86_64", target_feature = "sse2"))] + const SIMD_MIN_LEN: usize = SSE2_CHUNK_SIZE; + #[cfg(all(target_arch = "aarch64", target_feature = "neon"))] + const SIMD_MIN_LEN: usize = NEON_CHUNK_SIZE; + const_eval_select!( @capture { bytes: &[u8] } -> bool: if const { is_ascii_simple(bytes) } else { // For small inputs, use usize-at-a-time processing to avoid SSE2 call overhead. - if bytes.len() < SSE2_CHUNK_SIZE { + if bytes.len() < SIMD_MIN_LEN { let chunks = bytes.chunks_exact(USIZE_SIZE); let remainder = chunks.remainder(); for chunk in chunks { @@ -607,7 +683,10 @@ const fn is_ascii(bytes: &[u8]) -> bool { return remainder.iter().all(|b| b.is_ascii()); } - is_ascii_sse2(bytes) + #[cfg(all(target_arch = "x86_64", target_feature = "sse2"))] + { is_ascii_sse2(bytes) } + #[cfg(all(target_arch = "aarch64", target_feature = "neon"))] + { is_ascii_neon(bytes) } } ) } diff --git a/library/core/src/slice/cmp.rs b/library/core/src/slice/cmp.rs index 2390ca74a8e09..70d2392dfb3c6 100644 --- a/library/core/src/slice/cmp.rs +++ b/library/core/src/slice/cmp.rs @@ -4,13 +4,14 @@ use super::{from_raw_parts, memchr}; use crate::ascii; use crate::cmp::{self, BytewiseEq, Ordering}; use crate::intrinsics::compare_bytes; -use crate::mem::SizedTypeProperties; +use crate::marker::Destruct; +use crate::mem::{SizedTypeProperties, transmute_copy}; use crate::num::NonZero; use crate::ops::ControlFlow; #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq<[U]> for [T] +const impl PartialEq<[U]> for [T] where T: [const] PartialEq, { @@ -29,11 +30,12 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const Eq for [T] {} +const impl Eq for [T] {} /// Implements comparison of slices [lexicographically](Ord#lexicographical-comparison). #[stable(feature = "rust1", since = "1.0.0")] -impl Ord for [T] { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +const impl Ord for [T] { fn cmp(&self, other: &[T]) -> Ordering { SliceOrd::compare(self, other) } @@ -52,7 +54,8 @@ const fn as_underlying(x: ControlFlow) -> u8 { /// Implements comparison of slices [lexicographically](Ord#lexicographical-comparison). #[stable(feature = "rust1", since = "1.0.0")] -impl PartialOrd for [T] { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +const impl PartialOrd for [T] { #[inline] fn partial_cmp(&self, other: &[T]) -> Option { SlicePartialOrd::partial_compare(self, other) @@ -110,7 +113,7 @@ const trait SlicePartialEq { // Generic slice equality #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const SlicePartialEq for A +const impl SlicePartialEq for A where A: [const] PartialEq, { @@ -140,7 +143,7 @@ where // When each element can be compared byte-wise, we can compare all the bytes // from the whole size in one call to the intrinsics. #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const SlicePartialEq for A +const impl SlicePartialEq for A where A: [const] BytewiseEq, { @@ -175,19 +178,23 @@ const trait SliceChain: Sized { type AlwaysBreak = ControlFlow; -impl SlicePartialOrd for A { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +const impl SlicePartialOrd for A { default fn partial_compare(left: &[A], right: &[A]) -> Option { - let elem_chain = |a, b| match PartialOrd::partial_cmp(a, b) { + let elem_chain = const |a, b| match PartialOrd::partial_cmp(a, b) { Some(Ordering::Equal) => ControlFlow::Continue(()), non_eq => ControlFlow::Break(non_eq), }; - let len_chain = |a: &_, b: &_| ControlFlow::Break(usize::partial_cmp(a, b)); + + let len_chain = const |a: &_, b: &_| ControlFlow::Break(usize::partial_cmp(a, b)); + let AlwaysBreak::Break(b) = chaining_impl(left, right, elem_chain, len_chain); b } } -impl SliceChain for A { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +const impl SliceChain for A { default fn chaining_lt(left: &[Self], right: &[Self]) -> ControlFlow { chaining_impl(left, right, PartialOrd::__chaining_lt, usize::__chaining_lt) } @@ -202,12 +209,13 @@ impl SliceChain for A { } } +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] #[inline] -fn chaining_impl<'l, 'r, A: PartialOrd, B, C>( +const fn chaining_impl<'l, 'r, A: PartialOrd, B, C>( left: &'l [A], right: &'r [A], - elem_chain: impl Fn(&'l A, &'r A) -> ControlFlow, - len_chain: impl for<'a> FnOnce(&'a usize, &'a usize) -> ControlFlow, + elem_chain: impl [const] Fn(&'l A, &'r A) -> ControlFlow + [const] Destruct, + len_chain: impl for<'a> [const] FnOnce(&'a usize, &'a usize) -> ControlFlow + [const] Destruct, ) -> ControlFlow { let l = cmp::min(left.len(), right.len()); @@ -216,8 +224,11 @@ fn chaining_impl<'l, 'r, A: PartialOrd, B, C>( let lhs = &left[..l]; let rhs = &right[..l]; - for i in 0..l { + // FIXME(const-hack): revert this to `for i in 0..l` once `impl const Iterator for Range` + let mut i: usize = 0; + while i < l { elem_chain(&lhs[i], &rhs[i])?; + i += 1; } len_chain(&left.len(), &right.len()) @@ -237,7 +248,7 @@ where */ #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const SlicePartialOrd for A { +const impl SlicePartialOrd for A { fn partial_compare(left: &[A], right: &[A]) -> Option { Some(SliceOrd::compare(left, right)) } @@ -270,13 +281,16 @@ const trait SliceOrd: Sized { fn compare(left: &[Self], right: &[Self]) -> Ordering; } -impl SliceOrd for A { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +const impl SliceOrd for A { default fn compare(left: &[Self], right: &[Self]) -> Ordering { - let elem_chain = |a, b| match Ord::cmp(a, b) { + let elem_chain = const |a, b| match Ord::cmp(a, b) { Ordering::Equal => ControlFlow::Continue(()), non_eq => ControlFlow::Break(non_eq), }; - let len_chain = |a: &_, b: &_| ControlFlow::Break(usize::cmp(a, b)); + + let len_chain = const |a: &_, b: &_| ControlFlow::Break(usize::cmp(a, b)); + let AlwaysBreak::Break(b) = chaining_impl(left, right, elem_chain, len_chain); b } @@ -293,20 +307,20 @@ impl SliceOrd for A { const unsafe trait UnsignedBytewiseOrd: [const] Ord {} #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -unsafe impl const UnsignedBytewiseOrd for bool {} +const unsafe impl UnsignedBytewiseOrd for bool {} #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -unsafe impl const UnsignedBytewiseOrd for u8 {} +const unsafe impl UnsignedBytewiseOrd for u8 {} #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -unsafe impl const UnsignedBytewiseOrd for NonZero {} +const unsafe impl UnsignedBytewiseOrd for NonZero {} #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -unsafe impl const UnsignedBytewiseOrd for Option> {} +const unsafe impl UnsignedBytewiseOrd for Option> {} #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -unsafe impl const UnsignedBytewiseOrd for ascii::Char {} +const unsafe impl UnsignedBytewiseOrd for ascii::Char {} // `compare_bytes` compares a sequence of unsigned bytes lexicographically, so // use it if the requirements for `UnsignedBytewiseOrd` are fulfilled. #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const SliceOrd for A { +const impl SliceOrd for A { #[inline] fn compare(left: &[Self], right: &[Self]) -> Ordering { // Since the length of a slice is always less than or equal to @@ -333,7 +347,7 @@ impl const SliceOrd for A { // Don't generate our own chaining loops for `memcmp`-able things either. #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const SliceChain for A { +const impl SliceChain for A { #[inline] fn chaining_lt(left: &[Self], right: &[Self]) -> ControlFlow { match SliceOrd::compare(left, right) { @@ -377,23 +391,20 @@ where } } -impl SliceContains for u8 { - #[inline] - fn slice_contains(&self, x: &[Self]) -> bool { - memchr::memchr(*self, x).is_some() - } -} - -impl SliceContains for i8 { +impl SliceContains for T { #[inline] - fn slice_contains(&self, x: &[Self]) -> bool { - let byte = *self as u8; - // SAFETY: `i8` and `u8` have the same memory layout, thus casting `x.as_ptr()` - // as `*const u8` is safe. The `x.as_ptr()` comes from a reference and is thus guaranteed - // to be valid for reads for the length of the slice `x.len()`, which cannot be larger - // than `isize::MAX`. The returned slice is never mutated. - let bytes: &[u8] = unsafe { from_raw_parts(x.as_ptr() as *const u8, x.len()) }; - memchr::memchr(byte, bytes).is_some() + default fn slice_contains(&self, x: &[Self]) -> bool { + if size_of::() == 1 { + // SAFETY: `BytewiseEq` guarantees that values have no padding or provenance and + // compare like their underlying bytes. Since `T` is one byte, both the value and + // slice can be read as `u8`s. + let (byte, bytes) = unsafe { + (transmute_copy::(self), from_raw_parts(x.as_ptr().cast::(), x.len())) + }; + memchr::memchr(byte, bytes).is_some() + } else { + x.iter().any(|y| *y == *self) + } } } diff --git a/library/core/src/slice/index.rs b/library/core/src/slice/index.rs index 59802989c18fb..b82d79232becc 100644 --- a/library/core/src/slice/index.rs +++ b/library/core/src/slice/index.rs @@ -8,7 +8,7 @@ use crate::{ops, range}; #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -impl const ops::Index for [T] +const impl ops::Index for [T] where I: [const] SliceIndex<[T]>, { @@ -22,11 +22,12 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -impl const ops::IndexMut for [T] +const impl ops::IndexMut for [T] where I: [const] SliceIndex<[T]>, { #[inline(always)] + #[rustc_no_writable] fn index_mut(&mut self, index: I) -> &mut I::Output { index.index_mut(self) } @@ -102,46 +103,6 @@ const unsafe fn get_offset_len_mut_noubcheck( crate::intrinsics::aggregate_raw_ptr(ptr, len) } -mod private_slice_index { - use super::{ops, range}; - - #[stable(feature = "slice_get_slice", since = "1.28.0")] - pub trait Sealed {} - - #[stable(feature = "slice_get_slice", since = "1.28.0")] - impl Sealed for usize {} - #[stable(feature = "slice_get_slice", since = "1.28.0")] - impl Sealed for ops::Range {} - #[stable(feature = "slice_get_slice", since = "1.28.0")] - impl Sealed for ops::RangeTo {} - #[stable(feature = "slice_get_slice", since = "1.28.0")] - impl Sealed for ops::RangeFrom {} - #[stable(feature = "slice_get_slice", since = "1.28.0")] - impl Sealed for ops::RangeFull {} - #[stable(feature = "slice_get_slice", since = "1.28.0")] - impl Sealed for ops::RangeInclusive {} - #[stable(feature = "slice_get_slice", since = "1.28.0")] - impl Sealed for ops::RangeToInclusive {} - #[stable(feature = "slice_index_with_ops_bound_pair", since = "1.53.0")] - impl Sealed for (ops::Bound, ops::Bound) {} - - #[unstable(feature = "new_range_api", issue = "125687")] - impl Sealed for range::Range {} - #[unstable(feature = "new_range_api", issue = "125687")] - impl Sealed for range::RangeInclusive {} - #[unstable(feature = "new_range_api", issue = "125687")] - impl Sealed for range::RangeToInclusive {} - #[unstable(feature = "new_range_api", issue = "125687")] - impl Sealed for range::RangeFrom {} - - impl Sealed for ops::IndexRange {} - - #[unstable(feature = "sliceindex_wrappers", issue = "146179")] - impl Sealed for crate::index::Last {} - #[unstable(feature = "sliceindex_wrappers", issue = "146179")] - impl Sealed for crate::index::Clamp where T: Sealed {} -} - /// A helper trait used for indexing operations. /// /// Implementations of this trait have to promise that if the argument @@ -160,7 +121,7 @@ mod private_slice_index { label = "slice indices are of type `usize` or ranges of `usize`" )] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -pub const unsafe trait SliceIndex: private_slice_index::Sealed { +pub impl(crate) const unsafe trait SliceIndex { /// The output type returned by methods. #[stable(feature = "slice_get_slice", since = "1.28.0")] type Output: ?Sized; @@ -178,6 +139,8 @@ pub const unsafe trait SliceIndex: private_slice_index::Sealed { /// Returns a pointer to the output at this location, without /// performing any bounds checking. /// + /// # Safety + /// /// Calling this method with an out-of-bounds index or a dangling `slice` pointer /// is *[undefined behavior]* even if the resulting pointer is not used. /// @@ -188,6 +151,8 @@ pub const unsafe trait SliceIndex: private_slice_index::Sealed { /// Returns a mutable pointer to the output at this location, without /// performing any bounds checking. /// + /// # Safety + /// /// Calling this method with an out-of-bounds index or a dangling `slice` pointer /// is *[undefined behavior]* even if the resulting pointer is not used. /// @@ -211,7 +176,7 @@ pub const unsafe trait SliceIndex: private_slice_index::Sealed { /// The methods `index` and `index_mut` panic if the index is out of bounds. #[stable(feature = "slice_get_slice_impls", since = "1.15.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for usize { +const unsafe impl SliceIndex<[T]> for usize { type Output = T; #[inline] @@ -225,6 +190,7 @@ unsafe impl const SliceIndex<[T]> for usize { } #[inline] + #[rustc_no_writable] fn get_mut(self, slice: &mut [T]) -> Option<&mut T> { if self < slice.len() { // SAFETY: `self` is checked to be in bounds. @@ -273,6 +239,7 @@ unsafe impl const SliceIndex<[T]> for usize { } #[inline] + #[rustc_no_writable] fn index_mut(self, slice: &mut [T]) -> &mut T { // N.B., use intrinsic indexing &mut (*slice)[self] @@ -282,7 +249,7 @@ unsafe impl const SliceIndex<[T]> for usize { /// Because `IndexRange` guarantees `start <= end`, fewer checks are needed here /// than there are for a general `Range` (which might be `100..3`). #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for ops::IndexRange { +const unsafe impl SliceIndex<[T]> for ops::IndexRange { type Output = [T]; #[inline] @@ -296,6 +263,7 @@ unsafe impl const SliceIndex<[T]> for ops::IndexRange { } #[inline] + #[rustc_no_writable] fn get_mut(self, slice: &mut [T]) -> Option<&mut [T]> { if self.end() <= slice.len() { // SAFETY: `self` is checked to be valid and in bounds above. @@ -344,6 +312,7 @@ unsafe impl const SliceIndex<[T]> for ops::IndexRange { } #[inline] + #[rustc_no_writable] fn index_mut(self, slice: &mut [T]) -> &mut [T] { if self.end() <= slice.len() { // SAFETY: `self` is checked to be valid and in bounds above. @@ -359,7 +328,7 @@ unsafe impl const SliceIndex<[T]> for ops::IndexRange { /// - the end of the range is out of bounds. #[stable(feature = "slice_get_slice_impls", since = "1.15.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for ops::Range { +const unsafe impl SliceIndex<[T]> for ops::Range { type Output = [T]; #[inline] @@ -376,6 +345,7 @@ unsafe impl const SliceIndex<[T]> for ops::Range { } #[inline] + #[rustc_no_writable] fn get_mut(self, slice: &mut [T]) -> Option<&mut [T]> { if let Some(new_len) = usize::checked_sub(self.end, self.start) && self.end <= slice.len() @@ -445,6 +415,7 @@ unsafe impl const SliceIndex<[T]> for ops::Range { } #[inline] + #[rustc_no_writable] fn index_mut(self, slice: &mut [T]) -> &mut [T] { // Using checked_sub is a safe way to get `SubUnchecked` in MIR if let Some(new_len) = usize::checked_sub(self.end, self.start) @@ -458,9 +429,9 @@ unsafe impl const SliceIndex<[T]> for ops::Range { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for range::Range { +const unsafe impl SliceIndex<[T]> for range::Range { type Output = [T]; #[inline] @@ -469,6 +440,7 @@ unsafe impl const SliceIndex<[T]> for range::Range { } #[inline] + #[rustc_no_writable] fn get_mut(self, slice: &mut [T]) -> Option<&mut [T]> { ops::Range::from(self).get_mut(slice) } @@ -491,6 +463,7 @@ unsafe impl const SliceIndex<[T]> for range::Range { } #[inline] + #[rustc_no_writable] fn index_mut(self, slice: &mut [T]) -> &mut [T] { ops::Range::from(self).index_mut(slice) } @@ -499,7 +472,7 @@ unsafe impl const SliceIndex<[T]> for range::Range { /// The methods `index` and `index_mut` panic if the end of the range is out of bounds. #[stable(feature = "slice_get_slice_impls", since = "1.15.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for ops::RangeTo { +const unsafe impl SliceIndex<[T]> for ops::RangeTo { type Output = [T]; #[inline] @@ -508,6 +481,7 @@ unsafe impl const SliceIndex<[T]> for ops::RangeTo { } #[inline] + #[rustc_no_writable] fn get_mut(self, slice: &mut [T]) -> Option<&mut [T]> { (0..self.end).get_mut(slice) } @@ -530,6 +504,7 @@ unsafe impl const SliceIndex<[T]> for ops::RangeTo { } #[inline] + #[rustc_no_writable] fn index_mut(self, slice: &mut [T]) -> &mut [T] { (0..self.end).index_mut(slice) } @@ -538,7 +513,7 @@ unsafe impl const SliceIndex<[T]> for ops::RangeTo { /// The methods `index` and `index_mut` panic if the start of the range is out of bounds. #[stable(feature = "slice_get_slice_impls", since = "1.15.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for ops::RangeFrom { +const unsafe impl SliceIndex<[T]> for ops::RangeFrom { type Output = [T]; #[inline] @@ -547,6 +522,7 @@ unsafe impl const SliceIndex<[T]> for ops::RangeFrom { } #[inline] + #[rustc_no_writable] fn get_mut(self, slice: &mut [T]) -> Option<&mut [T]> { (self.start..slice.len()).get_mut(slice) } @@ -576,6 +552,7 @@ unsafe impl const SliceIndex<[T]> for ops::RangeFrom { } #[inline] + #[rustc_no_writable] fn index_mut(self, slice: &mut [T]) -> &mut [T] { if self.start > slice.len() { slice_index_fail(self.start, slice.len(), slice.len()) @@ -588,9 +565,9 @@ unsafe impl const SliceIndex<[T]> for ops::RangeFrom { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for range::RangeFrom { +const unsafe impl SliceIndex<[T]> for range::RangeFrom { type Output = [T]; #[inline] @@ -599,6 +576,7 @@ unsafe impl const SliceIndex<[T]> for range::RangeFrom { } #[inline] + #[rustc_no_writable] fn get_mut(self, slice: &mut [T]) -> Option<&mut [T]> { ops::RangeFrom::from(self).get_mut(slice) } @@ -621,6 +599,7 @@ unsafe impl const SliceIndex<[T]> for range::RangeFrom { } #[inline] + #[rustc_no_writable] fn index_mut(self, slice: &mut [T]) -> &mut [T] { ops::RangeFrom::from(self).index_mut(slice) } @@ -628,7 +607,7 @@ unsafe impl const SliceIndex<[T]> for range::RangeFrom { #[stable(feature = "slice_get_slice_impls", since = "1.15.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for ops::RangeFull { +const unsafe impl SliceIndex<[T]> for ops::RangeFull { type Output = [T]; #[inline] @@ -637,6 +616,7 @@ unsafe impl const SliceIndex<[T]> for ops::RangeFull { } #[inline] + #[rustc_no_writable] fn get_mut(self, slice: &mut [T]) -> Option<&mut [T]> { Some(slice) } @@ -657,28 +637,29 @@ unsafe impl const SliceIndex<[T]> for ops::RangeFull { } #[inline] + #[rustc_no_writable] fn index_mut(self, slice: &mut [T]) -> &mut [T] { slice } } /// The methods `index` and `index_mut` panic if: -/// - the end of the range is `usize::MAX` or /// - the start of the range is greater than the end of the range or /// - the end of the range is out of bounds. #[stable(feature = "inclusive_range", since = "1.26.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for ops::RangeInclusive { +const unsafe impl SliceIndex<[T]> for ops::RangeInclusive { type Output = [T]; #[inline] fn get(self, slice: &[T]) -> Option<&[T]> { - if *self.end() == usize::MAX { None } else { self.into_slice_range().get(slice) } + if *self.end() >= slice.len() { None } else { self.into_slice_range().get(slice) } } #[inline] + #[rustc_no_writable] fn get_mut(self, slice: &mut [T]) -> Option<&mut [T]> { - if *self.end() == usize::MAX { None } else { self.into_slice_range().get_mut(slice) } + if *self.end() >= slice.len() { None } else { self.into_slice_range().get_mut(slice) } } #[inline] @@ -709,6 +690,7 @@ unsafe impl const SliceIndex<[T]> for ops::RangeInclusive { } #[inline] + #[rustc_no_writable] fn index_mut(self, slice: &mut [T]) -> &mut [T] { let Self { mut start, mut end, exhausted } = self; let len = slice.len(); @@ -724,9 +706,9 @@ unsafe impl const SliceIndex<[T]> for ops::RangeInclusive { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for range::RangeInclusive { +const unsafe impl SliceIndex<[T]> for range::RangeInclusive { type Output = [T]; #[inline] @@ -735,6 +717,7 @@ unsafe impl const SliceIndex<[T]> for range::RangeInclusive { } #[inline] + #[rustc_no_writable] fn get_mut(self, slice: &mut [T]) -> Option<&mut [T]> { ops::RangeInclusive::from(self).get_mut(slice) } @@ -757,6 +740,7 @@ unsafe impl const SliceIndex<[T]> for range::RangeInclusive { } #[inline] + #[rustc_no_writable] fn index_mut(self, slice: &mut [T]) -> &mut [T] { ops::RangeInclusive::from(self).index_mut(slice) } @@ -765,7 +749,7 @@ unsafe impl const SliceIndex<[T]> for range::RangeInclusive { /// The methods `index` and `index_mut` panic if the end of the range is out of bounds. #[stable(feature = "inclusive_range", since = "1.26.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for ops::RangeToInclusive { +const unsafe impl SliceIndex<[T]> for ops::RangeToInclusive { type Output = [T]; #[inline] @@ -774,6 +758,7 @@ unsafe impl const SliceIndex<[T]> for ops::RangeToInclusive { } #[inline] + #[rustc_no_writable] fn get_mut(self, slice: &mut [T]) -> Option<&mut [T]> { (0..=self.end).get_mut(slice) } @@ -796,15 +781,16 @@ unsafe impl const SliceIndex<[T]> for ops::RangeToInclusive { } #[inline] + #[rustc_no_writable] fn index_mut(self, slice: &mut [T]) -> &mut [T] { (0..=self.end).index_mut(slice) } } /// The methods `index` and `index_mut` panic if the end of the range is out of bounds. -#[stable(feature = "inclusive_range", since = "1.26.0")] +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for range::RangeToInclusive { +const unsafe impl SliceIndex<[T]> for range::RangeToInclusive { type Output = [T]; #[inline] @@ -813,6 +799,7 @@ unsafe impl const SliceIndex<[T]> for range::RangeToInclusive { } #[inline] + #[rustc_no_writable] fn get_mut(self, slice: &mut [T]) -> Option<&mut [T]> { (0..=self.last).get_mut(slice) } @@ -835,6 +822,7 @@ unsafe impl const SliceIndex<[T]> for range::RangeToInclusive { } #[inline] + #[rustc_no_writable] fn index_mut(self, slice: &mut [T]) -> &mut [T] { (0..=self.last).index_mut(slice) } @@ -950,8 +938,7 @@ where R: ops::RangeBounds, { let len = bounds.end; - let r = into_range(len, (range.start_bound().copied(), range.end_bound().copied()))?; - if r.start > r.end || r.end > len { None } else { Some(r) } + try_into_slice_range(len, (range.start_bound().copied(), range.end_bound().copied())) } /// Converts a pair of `ops::Bound`s into `ops::Range` without performing any @@ -978,25 +965,31 @@ pub(crate) const fn into_range_unchecked( /// Returns `None` on overflowing indices. #[rustc_const_unstable(feature = "const_range", issue = "none")] #[inline] -pub(crate) const fn into_range( +pub(crate) const fn try_into_slice_range( len: usize, (start, end): (ops::Bound, ops::Bound), ) -> Option> { - use ops::Bound; - let start = match start { - Bound::Included(start) => start, - Bound::Excluded(start) => start.checked_add(1)?, - Bound::Unbounded => 0, - }; - let end = match end { - Bound::Included(end) => end.checked_add(1)?, - Bound::Excluded(end) => end, - Bound::Unbounded => len, + ops::Bound::Included(end) if end >= len => return None, + // Cannot overflow because `end < len` implies `end < usize::MAX`. + ops::Bound::Included(end) => end + 1, + + ops::Bound::Excluded(end) if end > len => return None, + ops::Bound::Excluded(end) => end, + + ops::Bound::Unbounded => len, }; - // Don't bother with checking `start < end` and `end <= len` - // since these checks are handled by `Range` impls + let start = match start { + ops::Bound::Excluded(start) if start >= end => return None, + // Cannot overflow because `start < end` implies `start < usize::MAX`. + ops::Bound::Excluded(start) => start + 1, + + ops::Bound::Included(start) if start > end => return None, + ops::Bound::Included(start) => start, + + ops::Bound::Unbounded => 0, + }; Some(start..end) } @@ -1039,12 +1032,13 @@ unsafe impl SliceIndex<[T]> for (ops::Bound, ops::Bound) { #[inline] fn get(self, slice: &[T]) -> Option<&Self::Output> { - into_range(slice.len(), self)?.get(slice) + try_into_slice_range(slice.len(), self)?.get(slice) } #[inline] + #[rustc_no_writable] fn get_mut(self, slice: &mut [T]) -> Option<&mut Self::Output> { - into_range(slice.len(), self)?.get_mut(slice) + try_into_slice_range(slice.len(), self)?.get_mut(slice) } #[inline] @@ -1065,6 +1059,7 @@ unsafe impl SliceIndex<[T]> for (ops::Bound, ops::Bound) { } #[inline] + #[rustc_no_writable] fn index_mut(self, slice: &mut [T]) -> &mut Self::Output { into_slice_range(slice.len(), self).index_mut(slice) } diff --git a/library/core/src/slice/iter.rs b/library/core/src/slice/iter.rs index 44c85a50c8b00..5950f9eb7071e 100644 --- a/library/core/src/slice/iter.rs +++ b/library/core/src/slice/iter.rs @@ -7,9 +7,7 @@ use safety::requires; use super::{from_raw_parts, from_raw_parts_mut}; use crate::hint::assert_unchecked; -use crate::iter::{ - FusedIterator, TrustedLen, TrustedRandomAccess, TrustedRandomAccessNoCoerce, UncheckedIterator, -}; +use crate::iter::{FusedIterator, TrustedLen, TrustedRandomAccess, TrustedRandomAccessNoCoerce}; #[cfg(kani)] use crate::kani; use crate::marker::PhantomData; @@ -182,14 +180,14 @@ impl Invariant for Iter<'_, T> { fn is_safe(&self) -> bool { let ty_size = crate::mem::size_of::(); // Use `abs_diff` since `end_or_len` may be smaller than `ptr` if `T` is a ZST. - let distance = self.ptr.addr().get().abs_diff(self.end_or_len as usize); + let distance = self.ptr.addr().get().abs_diff(self.end_or_len.addr()); if ty_size == 0 || distance == 0 { self.ptr.is_aligned() } else { let slice_ptr: *const [T] = crate::ptr::from_raw_parts(self.ptr.as_ptr(), distance / ty_size); crate::ub_checks::same_allocation(self.ptr.as_ptr(), self.end_or_len) - && self.ptr.addr().get() <= self.end_or_len as usize + && self.ptr.addr().get() <= self.end_or_len.addr() && distance % ty_size == 0 && crate::ub_checks::can_dereference(slice_ptr) } @@ -243,14 +241,14 @@ impl Invariant for IterMut<'_, T> { /// and `self.end_or_len`. fn is_safe(&self) -> bool { let ty_size = crate::mem::size_of::(); - let distance = self.ptr.addr().get().abs_diff(self.end_or_len as usize); + let distance = self.ptr.addr().get().abs_diff(self.end_or_len.addr()); if ty_size == 0 || distance == 0 { self.ptr.is_aligned() } else { let slice_ptr: *mut [T] = crate::ptr::from_raw_parts_mut(self.ptr.as_ptr(), distance / ty_size); crate::ub_checks::same_allocation(self.ptr.as_ptr(), self.end_or_len) - && self.ptr.addr().get() <= self.end_or_len as usize + && self.ptr.addr().get() <= self.end_or_len.addr() && distance % ty_size == 0 && crate::ub_checks::can_dereference(slice_ptr) && crate::ub_checks::can_write(slice_ptr) @@ -480,7 +478,7 @@ impl<'a, T: 'a, P: FnMut(&T) -> bool> Split<'a, T, P> { /// ``` #[unstable(feature = "split_as_slice", issue = "96137")] pub fn as_slice(&self) -> &'a [T] { - if self.finished { &[] } else { &self.v } + if self.finished { &[] } else { self.v } } } @@ -2234,7 +2232,7 @@ unsafe impl Sync for ChunksExactMut<'_, T> where T: Sync {} /// /// [`array_windows`]: slice::array_windows /// [slices]: slice -#[derive(Debug, Clone, Copy)] +#[derive(Debug)] #[stable(feature = "array_windows", since = "1.94.0")] #[must_use = "iterators are lazy and do nothing unless consumed"] pub struct ArrayWindows<'a, T: 'a, const N: usize> { @@ -2248,6 +2246,14 @@ impl<'a, T: 'a, const N: usize> ArrayWindows<'a, T, N> { } } +// FIXME(#26925) Remove in favor of `#[derive(Clone)]` +#[stable(feature = "array_windows", since = "1.94.0")] +impl Clone for ArrayWindows<'_, T, N> { + fn clone(&self) -> Self { + Self { v: self.v } + } +} + #[stable(feature = "array_windows", since = "1.94.0")] impl<'a, T, const N: usize> Iterator for ArrayWindows<'a, T, N> { type Item = &'a [T; N]; @@ -2283,6 +2289,14 @@ impl<'a, T, const N: usize> Iterator for ArrayWindows<'a, T, N> { fn last(self) -> Option { self.v.last_chunk() } + + unsafe fn __iterator_get_unchecked(&mut self, idx: usize) -> Self::Item { + // SAFETY: since the caller guarantees that `idx` is in bounds, + // which means that `idx` cannot overflow an `isize`, and the + // "slice" created by `cast_array` is a subslice of `self.v` + // thus is guaranteed to be valid for the lifetime `'a` of `self.v`. + unsafe { &*self.v.as_ptr().add(idx).cast_array() } + } } #[stable(feature = "array_windows", since = "1.94.0")] @@ -2311,6 +2325,22 @@ impl ExactSizeIterator for ArrayWindows<'_, T, N> { } } +#[unstable(feature = "trusted_len", issue = "37572")] +unsafe impl TrustedLen for ArrayWindows<'_, T, N> {} + +#[stable(feature = "array_windows", since = "1.94.0")] +impl FusedIterator for ArrayWindows<'_, T, N> {} + +#[doc(hidden)] +#[unstable(feature = "trusted_random_access", issue = "none")] +unsafe impl TrustedRandomAccess for ArrayWindows<'_, T, N> {} + +#[doc(hidden)] +#[unstable(feature = "trusted_random_access", issue = "none")] +unsafe impl TrustedRandomAccessNoCoerce for ArrayWindows<'_, T, N> { + const MAY_HAVE_SIDE_EFFECT: bool = false; +} + /// An iterator over a slice in (non-overlapping) chunks (`chunk_size` elements at a /// time), starting at the end of the slice. /// @@ -3083,6 +3113,20 @@ where if self.slice.is_empty() { (0, Some(0)) } else { (1, Some(self.slice.len())) } } + #[inline] + fn count(mut self) -> usize { + let Some((mut previous, rest)) = self.slice.split_first() else { + return 0; + }; + + let mut count = 1; + for current in rest { + count += usize::from(!(self.predicate)(previous, current)); + previous = current; + } + count + } + #[inline] fn last(mut self) -> Option { self.next_back() diff --git a/library/core/src/slice/iter/macros.rs b/library/core/src/slice/iter/macros.rs index 967b2ae960e0e..d173aba074dce 100644 --- a/library/core/src/slice/iter/macros.rs +++ b/library/core/src/slice/iter/macros.rs @@ -201,25 +201,20 @@ macro_rules! iterator { } fn next_chunk(&mut self) -> Result<[$elem; N], crate::array::IntoIter<$elem, N>> { - if T::IS_ZST { + if T::IS_ZST || len!(self) < N { return crate::array::iter_next_chunk(self); } - let len = len!(self); - if len >= N { - // SAFETY: we are just getting an array of [T; N] and moving the pointer over a little - let r = unsafe { self.post_inc_start(N).cast_array().$into_ref() } - .$array_ref(); // must convert &[T; N] to [&T; N] + + // SAFETY: the check above ensures len >= N + unsafe { + let r = self + .post_inc_start(N) + .cast_array() // NonNull -> NonNull<[T; N]> + // SAFETY: post_inc_start(N) insures we don't return overlapping `&mut`s + .$into_ref() // NonNull<[T; N]> -> &{mut} [T; N] + .$array_ref(); // must convert &{mut} [T; N] to [&{mut} T; N] + Ok(r) - } else { - // cant use $array_ref because theres no builtin for &mut [MU; N] -> [&mut MU; N] - // cant use copy_nonoverlapping as the $elem is of type &{mut} T instead of T - let mut a = [const { crate::mem::MaybeUninit::<$elem>::uninit() }; N]; - for into in (&mut a).into_iter().take(len) { - // SAFETY: take(n) limits to remainder (slice produces worse codegen) - into.write(unsafe { self.post_inc_start(1).$into_ref() }); - } - // SAFETY: we just initialized elements 0..len - unsafe { Err(crate::array::IntoIter::new_unchecked(a, 0..len)) } } } @@ -247,7 +242,7 @@ macro_rules! iterator { // SAFETY: We are in bounds. `post_inc_start` does the right thing even for ZSTs. unsafe { self.post_inc_start(n); - Some(self.next_unchecked()) + Some(self.post_inc_start(1).$into_ref()) } } @@ -491,17 +486,6 @@ macro_rules! iterator { #[unstable(feature = "trusted_len", issue = "37572")] unsafe impl TrustedLen for $name<'_, T> {} - impl<'a, T> UncheckedIterator for $name<'a, T> { - #[inline] - #[safety::requires(!is_empty!(self))] - unsafe fn next_unchecked(&mut self) -> $elem { - // SAFETY: The caller promised there's at least one more item. - unsafe { - self.post_inc_start(1).$into_ref() - } - } - } - #[stable(feature = "default_iters", since = "1.70.0")] impl Default for $name<'_, T> { /// Creates an empty slice iterator. diff --git a/library/core/src/slice/memchr.rs b/library/core/src/slice/memchr.rs index 602e22afb573e..d59a20fd25d5d 100644 --- a/library/core/src/slice/memchr.rs +++ b/library/core/src/slice/memchr.rs @@ -35,11 +35,16 @@ pub const fn memchr(x: u8, text: &[u8]) -> Option { #[cfg(not(kani))] { // Fast path for small slices. - if text.len() < 2 * USIZE_BYTES { - return memchr_naive(x, text); + let result = if text.len() < 2 * USIZE_BYTES { + memchr_naive(x, text) + } else { + memchr_aligned(x, text) + }; + if let Some(index) = result { + // SAFETY: Both implementations only return an index from within `text`. + unsafe { crate::hint::assert_unchecked(index < text.len()) }; } - - memchr_aligned(x, text) + result } } @@ -119,8 +124,18 @@ const fn memchr_aligned(x: u8, text: &[u8]) -> Option { } /// Returns the last index matching the byte `x` in `text`. +#[inline] #[must_use] pub fn memrchr(x: u8, text: &[u8]) -> Option { + let result = memrchr_aligned(x, text); + if let Some(index) = result { + // SAFETY: `memrchr_aligned` only returns the index of a matching byte in `text`. + unsafe { crate::hint::assert_unchecked(index < text.len()) }; + } + result +} + +fn memrchr_aligned(x: u8, text: &[u8]) -> Option { // Scan for a single byte value by reading two `usize` words at a time. // // Split `text` in three parts: diff --git a/library/core/src/slice/mod.rs b/library/core/src/slice/mod.rs index 78f9c6e78d8c7..41137231c3461 100644 --- a/library/core/src/slice/mod.rs +++ b/library/core/src/slice/mod.rs @@ -608,6 +608,7 @@ impl [T] { #[inline] #[must_use] #[rustc_const_unstable(feature = "const_index", issue = "143775")] + #[rustc_no_writable] pub const fn get_mut(&mut self, index: I) -> Option<&mut I::Output> where I: [const] SliceIndex, @@ -697,6 +698,7 @@ impl [T] { #[rustc_const_unstable(feature = "const_index", issue = "143775")] #[cfg_attr(rapx, rapx::verify)] #[cfg_attr(rapx, rapx::requires(InBound(index_access(self, index))))] + #[rustc_no_writable] pub const unsafe fn get_unchecked_mut(&mut self, index: I) -> &mut I::Output where I: [const] SliceIndex, @@ -770,6 +772,7 @@ impl [T] { #[rustc_as_ptr] #[inline(always)] #[must_use] + #[rustc_no_writable] pub const fn as_mut_ptr(&mut self) -> *mut T { self as *mut [T] as *mut T } @@ -919,16 +922,12 @@ impl [T] { #[inline] #[track_caller] pub const fn swap(&mut self, a: usize, b: usize) { - // FIXME: use swap_unchecked here (https://github.com/rust-lang/rust/pull/88540#issuecomment-944344343) - // Can't take two mutable loans from one vector, so instead use raw pointers. - let pa = &raw mut self[a]; - let pb = &raw mut self[b]; - // SAFETY: `pa` and `pb` have been created from safe mutable references and refer - // to elements in the slice and therefore are guaranteed to be valid and aligned. - // Note that accessing the elements behind `a` and `b` is checked and will - // panic when out of bounds. + // Bounds checks that panic exactly like indexing would. + let _ = &self[a]; + let _ = &self[b]; + // SAFETY: `a` and `b` were checked to be in bounds above. unsafe { - ptr::swap(pa, pb); + self.swap_unchecked(a, b); } } @@ -1365,7 +1364,9 @@ impl [T] { #[cfg_attr(rapx, rapx::verify)] #[cfg_attr(rapx, rapx::requires(ValidNum(N, "[1,)")))] #[cfg_attr(rapx, rapx::requires(ValidNum(len(self) % N == 0)))] - pub const unsafe fn as_chunks_unchecked(&self) -> &[[T; N]] { + pub const unsafe fn as_chunks_unchecked<#[rustc_panics_when_zero] const N: usize>( + &self, + ) -> &[[T; N]] { assert_unsafe_precondition!( check_language_ub, "slice::as_chunks_unchecked requires `N != 0` and the slice to split exactly into `N`-element chunks", @@ -1424,7 +1425,7 @@ impl [T] { #[track_caller] #[must_use] #[cfg_attr(rapx, rapx::verify)] - pub const fn as_chunks(&self) -> (&[[T; N]], &[T]) { + pub const fn as_chunks<#[rustc_panics_when_zero] const N: usize>(&self) -> (&[[T; N]], &[T]) { assert!(N != 0, "chunk size must be non-zero"); let len_rounded_down = self.len() / N * N; // SAFETY: The rounded-down value is always the same or smaller than the @@ -1472,7 +1473,7 @@ impl [T] { #[track_caller] #[must_use] #[cfg_attr(rapx, rapx::verify)] - pub const fn as_rchunks(&self) -> (&[T], &[[T; N]]) { + pub const fn as_rchunks<#[rustc_panics_when_zero] const N: usize>(&self) -> (&[T], &[[T; N]]) { assert!(N != 0, "chunk size must be non-zero"); let len = self.len() / N; let (remainder, multiple_of_n) = self.split_at(self.len() - len * N); @@ -1530,7 +1531,9 @@ impl [T] { #[cfg_attr(rapx, rapx::verify)] #[cfg_attr(rapx, rapx::requires(ValidNum(N, "[1,)")))] #[cfg_attr(rapx, rapx::requires(ValidNum(len(self) % N == 0)))] - pub const unsafe fn as_chunks_unchecked_mut(&mut self) -> &mut [[T; N]] { + pub const unsafe fn as_chunks_unchecked_mut<#[rustc_panics_when_zero] const N: usize>( + &mut self, + ) -> &mut [[T; N]] { assert_unsafe_precondition!( check_language_ub, "slice::as_chunks_unchecked requires `N != 0` and the slice to split exactly into `N`-element chunks", @@ -1585,7 +1588,9 @@ impl [T] { #[track_caller] #[must_use] #[cfg_attr(rapx, rapx::verify)] - pub const fn as_chunks_mut(&mut self) -> (&mut [[T; N]], &mut [T]) { + pub const fn as_chunks_mut<#[rustc_panics_when_zero] const N: usize>( + &mut self, + ) -> (&mut [[T; N]], &mut [T]) { assert!(N != 0, "chunk size must be non-zero"); let len_rounded_down = self.len() / N * N; // SAFETY: The rounded-down value is always the same or smaller than the @@ -1638,7 +1643,9 @@ impl [T] { #[inline] #[track_caller] #[must_use] - pub const fn as_rchunks_mut(&mut self) -> (&mut [T], &mut [[T; N]]) { + pub const fn as_rchunks_mut<#[rustc_panics_when_zero] const N: usize>( + &mut self, + ) -> (&mut [T], &mut [[T; N]]) { assert!(N != 0, "chunk size must be non-zero"); let len = self.len() / N; let (remainder, multiple_of_n) = self.split_at_mut(self.len() - len * N); @@ -1679,7 +1686,9 @@ impl [T] { #[rustc_const_unstable(feature = "const_slice_make_iter", issue = "137737")] #[inline] #[track_caller] - pub const fn array_windows(&self) -> ArrayWindows<'_, T, N> { + pub const fn array_windows<#[rustc_panics_when_zero] const N: usize>( + &self, + ) -> ArrayWindows<'_, T, N> { assert!(N != 0, "window size must be non-zero"); ArrayWindows::new(self) } @@ -2569,6 +2578,7 @@ impl [T] { F: FnMut(&T) -> bool, { let index = self.iter().position(pred)?; + // Slice bounds checks optimized are away (as of June 2026) Some((&self[..index], &self[index + 1..])) } @@ -2597,6 +2607,7 @@ impl [T] { F: FnMut(&T) -> bool, { let index = self.iter().rposition(pred)?; + // Slice bounds checks optimized are away (as of June 2026) Some((&self[..index], &self[index + 1..])) } @@ -2775,16 +2786,16 @@ impl [T] { /// Returns a subslice with the prefix and suffix removed. /// - /// If the slice starts with `prefix` and ends with `suffix`, returns the subslice after the - /// prefix and before the suffix, wrapped in `Some`. + /// If the slice starts with `prefix`, ends with `suffix`, and + /// the prefix and suffix don't overlap, returns the subslice after + /// the prefix and before the suffix, wrapped in `Some`. /// - /// If the slice does not start with `prefix` or does not end with `suffix`, returns `None`. + /// If the slice does not start with `prefix`, does not end with `suffix`, + /// or the prefix and suffix overlap in the slice, returns `None`. /// /// # Examples /// /// ``` - /// #![feature(strip_circumfix)] - /// /// let v = &[10, 50, 40, 30]; /// assert_eq!(v.strip_circumfix(&[10], &[30]), Some(&[50, 40][..])); /// assert_eq!(v.strip_circumfix(&[10], &[40, 30]), Some(&[50][..])); @@ -2793,9 +2804,10 @@ impl [T] { /// assert_eq!(v.strip_circumfix(&[10], &[40]), None); /// assert_eq!(v.strip_circumfix(&[], &[40, 30]), Some(&[10, 50][..])); /// assert_eq!(v.strip_circumfix(&[10, 50], &[]), Some(&[40, 30][..])); + /// assert_eq!(v.strip_circumfix(&[10, 50, 40], &[50, 40, 30]), None); /// ``` #[must_use = "returns the subslice without modifying the original"] - #[unstable(feature = "strip_circumfix", issue = "147946")] + #[stable(feature = "strip_circumfix", since = "1.98.0")] pub fn strip_circumfix(&self, prefix: &P, suffix: &S) -> Option<&[T]> where T: PartialEq, @@ -2957,12 +2969,13 @@ impl [T] { /// s.insert(idx, num); /// assert_eq!(s, [0, 1, 1, 1, 1, 2, 3, 5, 8, 13, 21, 34, 42, 55]); /// ``` + #[rustc_const_unstable(feature = "const_binary_search", issue = "159532")] #[stable(feature = "rust1", since = "1.0.0")] - pub fn binary_search(&self, x: &T) -> Result + pub const fn binary_search(&self, x: &T) -> Result where - T: Ord, + T: [const] Ord, { - self.binary_search_by(|p| p.cmp(x)) + self.binary_search_by(const |p| p.cmp(x)) } /// Binary searches this slice with a comparator function. @@ -3007,12 +3020,13 @@ impl [T] { /// let r = s.binary_search_by(|probe| probe.cmp(&seek)); /// assert!(match r { Ok(1..=4) => true, _ => false, }); /// ``` + #[rustc_const_unstable(feature = "const_binary_search", issue = "159532")] #[stable(feature = "rust1", since = "1.0.0")] #[inline] #[cfg_attr(rapx, rapx::verify)] - pub fn binary_search_by<'a, F>(&'a self, mut f: F) -> Result + pub const fn binary_search_by<'a, F>(&'a self, mut f: F) -> Result where - F: FnMut(&'a T) -> Ordering, + F: [const] FnMut(&'a T) -> Ordering + [const] Destruct, { let mut size = self.len(); if size == 0 { @@ -3109,14 +3123,15 @@ impl [T] { // This breaks links when slice is displayed in core, but changing it to use relative links // would break when the item is re-exported. So allow the core links to be broken for now. #[allow(rustdoc::broken_intra_doc_links)] + #[rustc_const_unstable(feature = "const_binary_search", issue = "159532")] #[stable(feature = "slice_binary_search_by_key", since = "1.10.0")] #[inline] - pub fn binary_search_by_key<'a, B, F>(&'a self, b: &B, mut f: F) -> Result + pub const fn binary_search_by_key<'a, B, F>(&'a self, b: &B, mut f: F) -> Result where - F: FnMut(&'a T) -> B, - B: Ord, + F: [const] FnMut(&'a T) -> B + [const] Destruct, + B: [const] Ord + [const] Destruct, { - self.binary_search_by(|k| f(k).cmp(b)) + self.binary_search_by(const |k| f(k).cmp(b)) } /// Sorts the slice in ascending order **without** preserving the initial order of equal elements. @@ -3729,18 +3744,22 @@ impl [T] { self.partition_dedup_by(|a, b| a == b) } - /// Moves all but the first of consecutive elements to the end of the slice satisfying - /// a given equality relation. + /// Moves all but the first of consecutive elements to the end of the slice that are + /// "equal" according to the given predicate function. /// /// Returns two slices. The first contains no consecutive repeated elements. /// The second contains all the duplicates in no specified order. /// - /// The `same_bucket` function is passed references to two elements from the slice and - /// must determine if the elements compare equal. The elements are passed in opposite order - /// from their order in the slice, so if `same_bucket(a, b)` returns `true`, `a` is moved - /// at the end of the slice. + /// The predicate `same_bucket(x, p)` is passed references to two elements from + /// the slice and must determine if the elements compare equal. The element `p` occurs + /// *before* `x` in the slice (`[.., p, .., x, ..]`), so `same_bucket(x, p)` + /// is receiving them in reversed order. /// - /// If the slice is sorted, the first returned slice contains no duplicates. + /// If the slice is sorted, the first returned slice contains no duplicates. For more + /// complicated predicates however, the order (ascending vs. descending) can matter. + /// + /// Both references passed to `same_bucket` are mutable. + /// This allows merged elements in the first slice by mutating `p` and returning `true`. /// /// # Examples /// @@ -3749,7 +3768,7 @@ impl [T] { /// /// let mut slice = ["foo", "Foo", "BAZ", "Bar", "bar", "baz", "BAZ"]; /// - /// let (dedup, duplicates) = slice.partition_dedup_by(|a, b| a.eq_ignore_ascii_case(b)); + /// let (dedup, duplicates) = slice.partition_dedup_by(|x, p| x.eq_ignore_ascii_case(p)); /// /// assert_eq!(dedup, ["foo", "BAZ", "Bar", "baz"]); /// assert_eq!(duplicates, ["bar", "Foo", "BAZ"]); @@ -3831,7 +3850,7 @@ impl [T] { // are less than `len`, thus are inside `self`. `prev_ptr_write` points to // one element before `ptr_write`, but `next_write` starts at 1, so // `prev_ptr_write` is never less than 0 and is inside the slice. - // This fulfils the requirements for dereferencing `ptr_read`, `prev_ptr_write` + // This fulfills the requirements for dereferencing `ptr_read`, `prev_ptr_write` // and `ptr_write`, and for using `ptr.add(next_read)`, `ptr.add(next_write - 1)` // and `prev_ptr_write.offset(1)`. // @@ -4396,6 +4415,7 @@ impl [T] { /// /// assert_eq!(&bytes, b"Hello, Wello!"); /// ``` + #[inline] #[stable(feature = "copy_within", since = "1.37.0")] #[track_caller] #[cfg_attr(rapx, rapx::verify)] @@ -4970,13 +4990,15 @@ impl [T] { /// s.insert(idx, num); /// assert_eq!(s, [0, 1, 1, 1, 1, 2, 3, 5, 8, 13, 21, 34, 42, 55]); /// ``` + #[rustc_const_unstable(feature = "const_binary_search", issue = "159532")] #[stable(feature = "partition_point", since = "1.52.0")] #[must_use] - pub fn partition_point

(&self, mut pred: P) -> usize + pub const fn partition_point

(&self, mut pred: P) -> usize where - P: FnMut(&T) -> bool, + P: [const] FnMut(&T) -> bool + [const] Destruct, { - self.binary_search_by(|x| if pred(x) { Less } else { Greater }).unwrap_or_else(|i| i) + self.binary_search_by(const |x| if pred(x) { Less } else { Greater }) + .unwrap_or_else(const |i| i) } /// Removes the subslice corresponding to the given range @@ -5421,7 +5443,7 @@ impl [T] { /// # Examples /// Basic usage: /// ``` - /// #![feature(substr_range)] + /// use core::range::Range; /// /// let nums = &[0, 5, 10, 0, 0, 5]; /// @@ -5429,14 +5451,14 @@ impl [T] { /// .split(|t| *t == 0) /// .map(|n| nums.subslice_range(n).unwrap()); /// - /// assert_eq!(iter.next(), Some(0..0)); - /// assert_eq!(iter.next(), Some(1..3)); - /// assert_eq!(iter.next(), Some(4..4)); - /// assert_eq!(iter.next(), Some(5..6)); + /// assert_eq!(iter.next(), Some(Range { start: 0, end: 0 })); + /// assert_eq!(iter.next(), Some(Range { start: 1, end: 3 })); + /// assert_eq!(iter.next(), Some(Range { start: 4, end: 4 })); + /// assert_eq!(iter.next(), Some(Range { start: 5, end: 6 })); /// ``` #[must_use] - #[unstable(feature = "substr_range", issue = "126769")] - pub fn subslice_range(&self, subslice: &[T]) -> Option> { + #[stable(feature = "substr_range", since = "1.98.0")] + pub fn subslice_range(&self, subslice: &[T]) -> Option> { if T::IS_ZST { panic!("elements are zero-sized"); } @@ -5453,7 +5475,11 @@ impl [T] { let start = byte_start / size_of::(); let end = start.wrapping_add(subslice.len()); - if start <= self.len() && end <= self.len() { Some(start..end) } else { None } + if start <= self.len() && end <= self.len() { + Some(core::range::Range { start, end }) + } else { + None + } } /// Returns the same slice `&[T]`. @@ -5719,7 +5745,7 @@ const trait CloneFromSpec { } #[rustc_const_unstable(feature = "const_clone", issue = "142757")] -impl const CloneFromSpec for [T] +const impl CloneFromSpec for [T] where T: [const] Clone + [const] Destruct, { @@ -5741,7 +5767,7 @@ where } #[rustc_const_unstable(feature = "const_clone", issue = "142757")] -impl const CloneFromSpec for [T] +const impl CloneFromSpec for [T] where T: [const] TrivialClone + [const] Destruct, { @@ -5756,7 +5782,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for &[T] { +const impl Default for &[T] { /// Creates an empty slice. fn default() -> Self { &[] @@ -5765,7 +5791,7 @@ impl const Default for &[T] { #[stable(feature = "mut_slice_default", since = "1.5.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for &mut [T] { +const impl Default for &mut [T] { /// Creates a mutable empty slice. fn default() -> Self { &mut [] @@ -5865,24 +5891,6 @@ impl fmt::Display for GetDisjointMutError { } } -mod private_get_disjoint_mut_index { - use super::{Range, RangeInclusive, range}; - - #[unstable(feature = "get_disjoint_mut_helpers", issue = "none")] - pub trait Sealed {} - - #[unstable(feature = "get_disjoint_mut_helpers", issue = "none")] - impl Sealed for usize {} - #[unstable(feature = "get_disjoint_mut_helpers", issue = "none")] - impl Sealed for Range {} - #[unstable(feature = "get_disjoint_mut_helpers", issue = "none")] - impl Sealed for RangeInclusive {} - #[unstable(feature = "get_disjoint_mut_helpers", issue = "none")] - impl Sealed for range::Range {} - #[unstable(feature = "get_disjoint_mut_helpers", issue = "none")] - impl Sealed for range::RangeInclusive {} -} - /// A helper trait for `<[T]>::get_disjoint_mut()`. /// /// # Safety @@ -5890,9 +5898,7 @@ mod private_get_disjoint_mut_index { /// If `is_in_bounds()` returns `true` and `is_overlapping()` returns `false`, /// it must be safe to index the slice with the indices. #[unstable(feature = "get_disjoint_mut_helpers", issue = "none")] -pub unsafe trait GetDisjointMutIndex: - Clone + private_get_disjoint_mut_index::Sealed -{ +pub impl(self) unsafe trait GetDisjointMutIndex: Clone { /// Returns `true` if `self` is in bounds for `len` slice elements. #[unstable(feature = "get_disjoint_mut_helpers", issue = "none")] fn is_in_bounds(&self, len: usize) -> bool; diff --git a/library/core/src/slice/sort/shared/mod.rs b/library/core/src/slice/sort/shared/mod.rs index e2cdcb3dd511d..e1977d79f3207 100644 --- a/library/core/src/slice/sort/shared/mod.rs +++ b/library/core/src/slice/sort/shared/mod.rs @@ -7,7 +7,7 @@ pub(crate) mod smallsort; /// SAFETY: this is safety relevant, how does this interact with the soundness holes in /// specialization? -#[rustc_unsafe_specialization_marker] +#[unsafe(rustc_allow_lifetime_dependent_specialization)] pub(crate) trait FreezeMarker {} impl FreezeMarker for T {} diff --git a/library/core/src/slice/sort/shared/smallsort.rs b/library/core/src/slice/sort/shared/smallsort.rs index e555fce440872..40939f922bcb6 100644 --- a/library/core/src/slice/sort/shared/smallsort.rs +++ b/library/core/src/slice/sort/shared/smallsort.rs @@ -134,7 +134,7 @@ impl UnstableSmallSortFreezeTypeImpl for T { } /// SAFETY: Only used for run-time optimization heuristic. -#[rustc_unsafe_specialization_marker] +#[unsafe(rustc_allow_lifetime_dependent_specialization)] trait CopyMarker {} impl CopyMarker for T {} @@ -284,7 +284,7 @@ fn small_sort_general_with_scratch bool>( // permutation of the input through drop_guard. This technique is similar // to ping-pong merging. bidirectional_merge( - &*ptr::slice_from_raw_parts(drop_guard.src, drop_guard.len), + slice::from_raw_parts(drop_guard.src, drop_guard.len), drop_guard.dst, is_less, ); @@ -332,7 +332,7 @@ where let v_base = v.as_mut_ptr(); let initial_region_len = if no_merge { len } else { len_div_2 }; // SAFETY: Both possible values of `initial_region_len` are in-bounds. - let mut region = unsafe { &mut *ptr::slice_from_raw_parts_mut(v_base, initial_region_len) }; + let mut region = unsafe { slice::from_raw_parts_mut(v_base, initial_region_len) }; // Avoid compiler unrolling, we *really* don't want that to happen here for binary-size reasons. loop { @@ -357,9 +357,7 @@ where } // SAFETY: The right side of `v` based on `len_div_2` is guaranteed in-bounds. - unsafe { - region = &mut *ptr::slice_from_raw_parts_mut(v_base.add(len_div_2), len - len_div_2) - }; + unsafe { region = slice::from_raw_parts_mut(v_base.add(len_div_2), len - len_div_2) }; } // SAFETY: We checked that T is Freeze and thus observation safe. @@ -367,11 +365,7 @@ where // scratch and v must not alias and scratch has v.len() space. unsafe { let scratch_base = stack_array.as_mut_ptr() as *mut T; - bidirectional_merge( - &mut *ptr::slice_from_raw_parts_mut(v_base, len), - scratch_base, - is_less, - ); + bidirectional_merge(slice::from_raw_parts_mut(v_base, len), scratch_base, is_less); ptr::copy_nonoverlapping(scratch_base, v_base, len); } } @@ -675,7 +669,7 @@ unsafe fn sort8_stable bool>( // SAFETY: scratch_base[0..8] is now initialized, allowing us to merge back // into dst. unsafe { - bidirectional_merge(&*ptr::slice_from_raw_parts(scratch_base, 8), dst, is_less); + bidirectional_merge(slice::from_raw_parts(scratch_base, 8), dst, is_less); } } diff --git a/library/core/src/slice/sort/unstable/quicksort.rs b/library/core/src/slice/sort/unstable/quicksort.rs index bdf56a8080305..5f2991ee722d2 100644 --- a/library/core/src/slice/sort/unstable/quicksort.rs +++ b/library/core/src/slice/sort/unstable/quicksort.rs @@ -142,12 +142,8 @@ const fn inst_partition bool>() -> fn(&mut [T], &T, &mut // Specialize for types that are relatively cheap to copy, where branchless optimizations // have large leverage e.g. `u64` and `String`. cfg_select! { - feature = "optimize_for_size" => { - partition_lomuto_branchless_simple:: - } - _ => { - partition_lomuto_branchless_cyclic:: - } + feature = "optimize_for_size" => partition_lomuto_branchless_simple::, + _ => partition_lomuto_branchless_cyclic::, } } else { partition_hoare_branchy_cyclic:: diff --git a/library/core/src/str/iter.rs b/library/core/src/str/iter.rs index 34e2ab79b9d34..b93003cda7efe 100644 --- a/library/core/src/str/iter.rs +++ b/library/core/src/str/iter.rs @@ -103,9 +103,6 @@ impl<'a> Iterator for Chars<'a> { #[inline] fn size_hint(&self) -> (usize, Option) { let len = self.iter.len(); - // `(len + 3)` can't overflow, because we know that the `slice::Iter` - // belongs to a slice in memory which has a maximum length of - // `isize::MAX` (that's well below `usize::MAX`). (len.div_ceil(4), Some(len)) } @@ -1418,7 +1415,7 @@ impl<'a> SplitAsciiWhitespace<'a> { } // SAFETY: Slice is created from str. - Some(unsafe { crate::str::from_utf8_unchecked(&self.inner.iter.iter.v) }) + Some(unsafe { crate::str::from_utf8_unchecked(self.inner.iter.iter.v) }) } } @@ -1533,9 +1530,6 @@ impl<'a> Iterator for EncodeUtf16<'a> { // is therefore determined by assuming the remaining bytes contain as // many 3-byte sequences as possible. The highest bytes:code units // ratio is for 1-byte sequences, so use this for the upper bound. - // `(len + 2)` can't overflow, because we know that the `slice::Iter` - // belongs to a slice in memory which has a maximum length of - // `isize::MAX` (that's well below `usize::MAX`) if self.extra == 0 { (len.div_ceil(3), Some(len)) } else { @@ -1544,6 +1538,43 @@ impl<'a> Iterator for EncodeUtf16<'a> { (len.div_ceil(3) + 1, Some(len + 1)) } } + + #[inline] + fn count(self) -> usize { + let extra = if self.extra == 0 { 0 } else { 1 }; + // Find UTF-8 non-continuation bytes and map: + // + // len_utf8() | len_utf16() + // -----------|------------ + // 1 | 1 + // 2 | 1 + // 3 | 1 + // 4 | 2 + // + // Because we never map to larger values the result is never larger than + // `self.chars.as_str().len()` so the sum can never overflow + self.chars.as_str().as_bytes().iter().fold(extra, |acc, &byte| { + acc.wrapping_add({ + if byte < 0b1000_0000 { + // 0b0xxx_xxxx: ASCII-compatible U+0000 to U+007F + 1 + } else if byte < 0b1100_0000 { + // 0b10xx_xxxx: UTF-8 continuation byte, skip + 0 + } else if byte < 0b1111_0000 { + // 0b110x_xxxx: start of a 2-byte UTF-8 sequence for U+0080 to U+07FF + // 0b1110_xxxx: start of a 3-byte UTF-8 sequence for U+0800 to U+FFFF + 1 + } else { + // 0b1111_0xxx: start of a 4-byte UTF-8 sequence for U+010000 to U+10FFFF + // This is exactly the range encoded as a surrogate pair in UTF-16 + // + // 0b1111_1xxx: would fall here but never occurs in valid UTF-8 + 2 + } + }) + }) + } } #[stable(feature = "fused", since = "1.26.0")] diff --git a/library/core/src/str/lossy.rs b/library/core/src/str/lossy.rs index 93bbf4573e4c9..eed1dbd95a962 100644 --- a/library/core/src/str/lossy.rs +++ b/library/core/src/str/lossy.rs @@ -125,7 +125,7 @@ impl fmt::Debug for Debug<'_> { let mut from = 0; for (i, c) in valid.char_indices() { let esc = c.escape_debug_ext(EscapeDebugExtArgs { - escape_grapheme_extended: true, + escape_grapheme_extender: true, escape_single_quote: false, escape_double_quote: true, }); diff --git a/library/core/src/str/mod.rs b/library/core/src/str/mod.rs index ab7389a1300c5..b3b4658645b9f 100644 --- a/library/core/src/str/mod.rs +++ b/library/core/src/str/mod.rs @@ -15,7 +15,8 @@ mod validations; use self::pattern::{DoubleEndedSearcher, Pattern, ReverseSearcher, Searcher}; use crate::char::{self, EscapeDebugExtArgs}; -use crate::ops::Range; +use crate::hint::assert_unchecked; +use crate::range::Range; use crate::slice::{self, SliceIndex}; use crate::ub_checks::assert_unsafe_precondition; use crate::{ascii, mem}; @@ -81,38 +82,50 @@ const fn slice_error_fail_ct(_: &str, _: usize, _: usize) -> ! { #[track_caller] fn slice_error_fail_rt(s: &str, begin: usize, end: usize) -> ! { - const MAX_DISPLAY_LENGTH: usize = 256; - let trunc_len = s.floor_char_boundary(MAX_DISPLAY_LENGTH); - let s_trunc = &s[..trunc_len]; - let ellipsis = if trunc_len < s.len() { "[...]" } else { "" }; - - // 1. out of bounds - if begin > s.len() || end > s.len() { - let oob_index = if begin > s.len() { begin } else { end }; - panic!("byte index {oob_index} is out of bounds of `{s_trunc}`{ellipsis}"); - } - - // 2. begin <= end - assert!( - begin <= end, - "begin <= end ({} <= {}) when slicing `{}`{}", - begin, - end, - s_trunc, - ellipsis - ); - - // 3. character boundary - let index = if !s.is_char_boundary(begin) { begin } else { end }; - // find the character - let char_start = s.floor_char_boundary(index); - // `char_start` must be less than len and a char boundary - let ch = s[char_start..].chars().next().unwrap(); - let char_range = char_start..char_start + ch.len_utf8(); - panic!( - "byte index {} is not a char boundary; it is inside {:?} (bytes {:?}) of `{}`{}", - index, ch, char_range, s_trunc, ellipsis - ); + let len = s.len(); + + // 1. begin is OOB. + if begin > len { + panic!("start byte index {begin} is out of bounds for string of length {len}"); + } + + // 2. end is OOB. + if end > len { + panic!("end byte index {end} is out of bounds for string of length {len}"); + } + + // 3. range is backwards. + if begin > end { + panic!("byte range starts at {begin} but ends at {end}"); + } + + // 4. begin is inside a character. + if !s.is_char_boundary(begin) { + let floor = s.floor_char_boundary(begin); + let ceil = s.ceil_char_boundary(begin); + let range = floor..ceil; + let ch = s[floor..ceil].chars().next().unwrap(); + panic!( + "start byte index {begin} is not a char boundary; it is inside {ch:?} (bytes {range:?} of string)" + ) + } + + // 5. end is inside a character. + if !s.is_char_boundary(end) { + let floor = s.floor_char_boundary(end); + let ceil = s.ceil_char_boundary(end); + let range = floor..ceil; + let ch = s[floor..ceil].chars().next().unwrap(); + panic!( + "end byte index {end} is not a char boundary; it is inside {ch:?} (bytes {range:?} of string)" + ) + } + + // 6. end is OOB and range is inclusive (end == len). + // This test cannot be combined with 2. above because for cases like + // `"abcαβγ"[4..9]` the error is that 4 is inside 'α', not that 9 is OOB. + debug_assert_eq!(end, len); + panic!("end byte index {end} is out of bounds for string of length {len}"); } impl str { @@ -138,6 +151,7 @@ impl str { #[rustc_no_implicit_autorefs] #[must_use] #[inline] + #[allow(clippy::needless_as_bytes)] pub const fn len(&self) -> usize { self.as_bytes().len() } @@ -409,21 +423,35 @@ impl str { #[inline] pub const fn floor_char_boundary(&self, index: usize) -> usize { if index >= self.len() { - self.len() - } else { - let mut i = index; - while i > 0 { - if self.as_bytes()[i].is_utf8_char_boundary() { - break; - } - i -= 1; - } + return self.len(); + } + if self.as_bytes()[index].is_utf8_char_boundary() { + return index; + } + // Unlike `ceil_char_boundary`, the loop is unrolled manually to prevent the compiler from + // generating excessive unrolled loop bodies when `index` is statically known. - // The character boundary will be within four bytes of the index - debug_assert!(i >= index.saturating_sub(3)); + // The first byte of `&str` must always be a char boundary, so we can assume `i > 0` below + // for any `i` where `self.as_bytes()[i]` is not a char boundary. + debug_assert!(self.as_bytes()[0].is_utf8_char_boundary()); - i + // SAFETY: `self.as_bytes()[0]` is always a char boundary with valid `&str` + unsafe { assert_unchecked(index >= 1) }; + if self.as_bytes()[index - 1].is_utf8_char_boundary() { + return index - 1; + } + + // SAFETY: `self.as_bytes()[0]` is always a char boundary with valid `&str` + unsafe { assert_unchecked(index >= 2) }; + if self.as_bytes()[index - 2].is_utf8_char_boundary() { + return index - 2; } + + // `self.as_bytes()[0]` is always a char boundary with valid `&str` + debug_assert!(index >= 3); + // The character boundary will be within four bytes of the index + debug_assert!(self.as_bytes()[index - 3].is_utf8_char_boundary()); + index - 3 } /// Finds the closest `x` not below `index` where [`is_char_boundary(x)`] is `true`. @@ -455,14 +483,14 @@ impl str { self.len() } else { let mut i = index; - while i < self.len() { - if self.as_bytes()[i].is_utf8_char_boundary() { + while !self.as_bytes()[i].is_utf8_char_boundary() { + i += 1; + if i >= self.len() { break; } - i += 1; } - // The character boundary will be within four bytes of the index + // The character boundary will be within four bytes of the index debug_assert!(i <= index + 3); i @@ -577,6 +605,7 @@ impl str { #[rustc_as_ptr] #[must_use] #[inline(always)] + #[rustc_no_writable] pub const fn as_mut_ptr(&mut self) -> *mut u8 { self as *mut str as *mut u8 } @@ -1190,6 +1219,9 @@ impl str { /// /// This uses the same definition as [`char::is_ascii_whitespace`]. /// To split by Unicode `Whitespace` instead, use [`split_whitespace`]. + /// Note that because of this difference in definition, even if `s.is_ascii()` + /// is `true`, `s.split_ascii_whitespace()` behavior will differ from `s.split_whitespace()` + /// if `s` contains U+000B VERTICAL TAB. /// /// [`split_whitespace`]: str::split_whitespace /// @@ -2461,12 +2493,14 @@ impl str { /// Returns a string slice with the prefix and suffix removed. /// - /// If the string starts with the pattern `prefix` and ends with the pattern `suffix`, returns + /// If the string starts with the pattern `prefix` and ends with + /// the pattern `suffix`, and the prefix and suffix don't overlap, returns /// the substring after the prefix and before the suffix, wrapped in `Some`. /// Unlike [`trim_start_matches`] and [`trim_end_matches`], this method removes both the prefix /// and suffix exactly once. /// - /// If the string does not start with `prefix` or does not end with `suffix`, returns `None`. + /// If the string does not start with `prefix`, does not end with `suffix`, + /// or the prefix and suffix overlap in the string, returns `None`. /// /// Each [pattern] can be a `&str`, [`char`], a slice of [`char`]s, or a /// function or closure that determines if a character matches. @@ -2479,15 +2513,14 @@ impl str { /// # Examples /// /// ``` - /// #![feature(strip_circumfix)] - /// /// assert_eq!("bar:hello:foo".strip_circumfix("bar:", ":foo"), Some("hello")); /// assert_eq!("bar:foo".strip_circumfix("foo", "foo"), None); /// assert_eq!("foo:bar;".strip_circumfix("foo:", ';'), Some("bar")); + /// assert_eq!("foo:bar:baz".strip_circumfix("foo:bar:", ":bar:baz"), None); /// ``` #[must_use = "this returns the remaining substring as a new slice, \ without modifying the original"] - #[unstable(feature = "strip_circumfix", issue = "147946")] + #[stable(feature = "strip_circumfix", since = "1.98.0")] pub fn strip_circumfix(&self, prefix: P, suffix: S) -> Option<&str> where for<'a> S::Searcher<'a>: ReverseSearcher<'a>, @@ -2810,6 +2843,9 @@ impl str { /// Same as `to_ascii_lowercase(a) == to_ascii_lowercase(b)`, /// but without allocating and copying temporaries. /// + /// For Unicode-aware case-insensitive matching, consider + /// [`str::eq_ignore_case_unnormalized`]. + /// /// # Examples /// /// ``` @@ -2825,6 +2861,59 @@ impl str { self.as_bytes().eq_ignore_ascii_case(other.as_bytes()) } + /// Checks that two strings are a caseless match, according to + /// [Definition 144] in Chapter 3 of the Unicode Standard. + /// + /// [Definition 144]: https://www.unicode.org/versions/latest/core-spec/chapter-3/#G53513 + /// + /// Same as `a.to_casefold_unnormalized() == b.to_casefold_unnormalized()`, + /// but without allocating. See that method's documentation, + /// as well as [`char::to_casefold_unnormalized()`], + /// for more information about case folding. + /// + /// No [normalization] (e.g. NFC) is performed, so visually and semantically identical strings + /// might still compare unequal. For example, `"Å"` (U+00C5 LATIN CAPITAL LETTER A WITH RING ABOVE) + /// is considered distinct from `"Å"` (A followed by U+030A COMBINING RING ABOVE), + /// even though Unicode considers them canonically equivalent. + /// + /// In addition, this method is independent of language/locale, + /// so the special behavior of I/ı/İ/i in Turkish and Azeri is not handled. + /// + /// # Examples + /// + /// ``` + /// #![feature(casefold)] + /// assert!("Ferris".eq_ignore_case_unnormalized("FERRIS")); + /// assert!("Ferrös".eq_ignore_case_unnormalized("FERRÖS")); + /// assert!("ẞ".eq_ignore_case_unnormalized("ss")); + /// ``` + /// + /// No NFC [normalization] is performed: + /// + /// ```rust + /// #![feature(casefold)] + /// // These two strings are visually and semantically identical... + /// let comp = "Å"; + /// let decomp = "Å"; + /// + /// // ... but not codepoint-for-codepoint equal. + /// assert_eq!(comp, "\u{C5}"); + /// assert_eq!(decomp, "A\u{030A}"); + /// + /// // Their case-foldings are likewise unequal: + /// assert!(!comp.eq_ignore_case_unnormalized(decomp)); + /// ``` + /// + /// [normalization]: https://www.unicode.org/faq/normalization.html + #[unstable(feature = "casefold", issue = "157000")] + #[must_use] + #[inline] + pub fn eq_ignore_case_unnormalized(&self, other: &str) -> bool { + self.chars() + .flat_map(char::to_casefold_unnormalized) + .eq(other.chars().flat_map(char::to_casefold_unnormalized)) + } + /// Converts this string to its ASCII upper case equivalent in-place. /// /// ASCII letters 'a' to 'z' are mapped to 'A' to 'Z', @@ -2881,12 +2970,78 @@ impl str { me.make_ascii_lowercase() } + /// Copies the string from `src` into `self`, using a memcpy. + /// + /// The length of `src` must be the same as `self`. + /// + /// # Panics + /// + /// This function will panic if the two strings have different lengths. + /// + /// # Examples + /// + /// ``` + /// #![feature(str_copy_from_str)] + /// let src = "Saludos"; + /// let mut dst = String::from("Grüße, Jürgen"); + /// + /// // Because the strings have to be the same length, + /// // we slice the destination slice from sixteen bytes + /// // to seven. It will panic if we don't do this. + /// dst[..7].copy_from_str(src); + /// + /// assert_eq!(src, "Saludos"); + /// assert_eq!(dst, "Saludos, Jürgen"); + /// ``` + /// + /// Rust enforces that there can only be one mutable reference with no + /// immutable references to a particular piece of data in a particular + /// scope. Because of this, attempting to use `copy_from_str` on a + /// single string will result in a compile failure: + /// + /// ```compile_fail + /// #![feature(str_copy_from_str)] + /// let mut string = String::from("Abcde"); + /// + /// string[..2].copy_from_str(&string[3..]); // compile fail! + /// ``` + /// + /// To work around this, we can use [`split_at_mut`] to create two distinct + /// sub-slices from a string: + /// + /// ``` + /// #![feature(str_copy_from_str)] + /// let mut string = String::from("Abcde"); + /// + /// { + /// let (left, right) = string.split_at_mut(2); + /// left.copy_from_str(&right[1..]); + /// } + /// + /// assert_eq!(string, "decde"); + /// ``` + /// + /// [`split_at_mut`]: str::split_at_mut + #[doc(alias = "memcpy")] + #[inline] + #[unstable(feature = "str_copy_from_str", issue = "159841")] + #[track_caller] + pub fn copy_from_str(&mut self, src: &str) { + // SAFETY: `copy_from_slice` panics unless the lengths are equal, and copying same-length + // UTF-8 into a `str` keeps it valid UTF-8. + let me = unsafe { self.as_bytes_mut() }; + me.copy_from_slice(src.as_bytes()); + } + /// Returns a string slice with leading ASCII whitespace removed. /// /// 'Whitespace' refers to the definition used by - /// [`u8::is_ascii_whitespace`]. + /// [`u8::is_ascii_whitespace`]. Importantly, this definition excludes + /// the U+000B code point even though it has the Unicode [`White_Space`] property + /// and is removed by [`str::trim_start`]. /// /// [`u8::is_ascii_whitespace`]: u8::is_ascii_whitespace + /// [`White_Space`]: https://www.unicode.org/reports/tr44/#White_Space /// /// # Examples /// @@ -2909,9 +3064,12 @@ impl str { /// Returns a string slice with trailing ASCII whitespace removed. /// /// 'Whitespace' refers to the definition used by - /// [`u8::is_ascii_whitespace`]. + /// [`u8::is_ascii_whitespace`]. Importantly, this definition excludes + /// the U+000B code point even though it has the Unicode [`White_Space`] property + /// and is removed by [`str::trim_end`]. /// /// [`u8::is_ascii_whitespace`]: u8::is_ascii_whitespace + /// [`White_Space`]: https://www.unicode.org/reports/tr44/#White_Space /// /// # Examples /// @@ -2935,9 +3093,12 @@ impl str { /// removed. /// /// 'Whitespace' refers to the definition used by - /// [`u8::is_ascii_whitespace`]. + /// [`u8::is_ascii_whitespace`]. Importantly, this definition excludes + /// the U+000B code point even though it has the Unicode [`White_Space`] property + /// and is removed by [`str::trim`]. /// /// [`u8::is_ascii_whitespace`]: u8::is_ascii_whitespace + /// [`White_Space`]: https://www.unicode.org/reports/tr44/#White_Space /// /// # Examples /// @@ -3099,18 +3260,18 @@ impl str { /// /// # Examples /// ``` - /// #![feature(substr_range)] + /// use core::range::Range; /// /// let data = "a, b, b, a"; /// let mut iter = data.split(", ").map(|s| data.substr_range(s).unwrap()); /// - /// assert_eq!(iter.next(), Some(0..1)); - /// assert_eq!(iter.next(), Some(3..4)); - /// assert_eq!(iter.next(), Some(6..7)); - /// assert_eq!(iter.next(), Some(9..10)); + /// assert_eq!(iter.next(), Some(Range { start: 0, end: 1 })); + /// assert_eq!(iter.next(), Some(Range { start: 3, end: 4 })); + /// assert_eq!(iter.next(), Some(Range { start: 6, end: 7 })); + /// assert_eq!(iter.next(), Some(Range { start: 9, end: 10 })); /// ``` #[must_use] - #[unstable(feature = "substr_range", issue = "126769")] + #[stable(feature = "substr_range", since = "1.98.0")] pub fn substr_range(&self, substr: &str) -> Option> { self.as_bytes().subslice_range(substr.as_bytes()) } @@ -3129,7 +3290,7 @@ impl str { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef<[u8]> for str { +const impl AsRef<[u8]> for str { #[inline] fn as_ref(&self) -> &[u8] { self.as_bytes() @@ -3138,7 +3299,7 @@ impl const AsRef<[u8]> for str { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for &str { +const impl Default for &str { /// Creates an empty str #[inline] fn default() -> Self { @@ -3148,7 +3309,7 @@ impl const Default for &str { #[stable(feature = "default_mut_str", since = "1.28.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for &mut str { +const impl Default for &mut str { /// Creates an empty mutable str #[inline] fn default() -> Self { @@ -3169,7 +3330,7 @@ impl_fn_for_zst! { #[derive(Clone)] struct CharEscapeDebugContinue impl Fn = |c: char| -> char::EscapeDebug { c.escape_debug_ext(EscapeDebugExtArgs { - escape_grapheme_extended: false, + escape_grapheme_extender: false, escape_single_quote: true, escape_double_quote: true }) diff --git a/library/core/src/str/pattern.rs b/library/core/src/str/pattern.rs index ae234e95a491b..ad38126b6b7f5 100644 --- a/library/core/src/str/pattern.rs +++ b/library/core/src/str/pattern.rs @@ -166,7 +166,7 @@ pub trait Pattern: Sized { } } - /// Returns the pattern as utf-8 bytes if possible. + /// Returns the pattern as UTF-8 if possible. fn as_utf8_pattern(&self) -> Option> { None } @@ -177,7 +177,9 @@ pub trait Pattern: Sized { #[derive(Copy, Clone, Eq, PartialEq, Debug)] pub enum Utf8Pattern<'a> { /// Type returned by String and str types. - StringPattern(&'a [u8]), + /// This stores `str` rather than bytes so callers cannot describe + /// non-UTF-8 string patterns through this API. + StringPattern(&'a str), /// Type returned by char types. CharPattern(char), } @@ -990,7 +992,7 @@ impl<'b> Pattern for &'b str { /// Checks whether the pattern matches anywhere in the haystack #[inline] fn is_contained_in(self, haystack: &str) -> bool { - if self.len() == 0 { + if self.is_empty() { return true; } @@ -1002,7 +1004,8 @@ impl<'b> Pattern for &'b str { #[cfg(any( all(target_arch = "x86_64", target_feature = "sse2"), - all(target_arch = "loongarch64", target_feature = "lsx") + all(target_arch = "loongarch64", target_feature = "lsx"), + all(target_arch = "aarch64", target_feature = "neon") ))] if self.len() <= 32 { if let Some(result) = simd_contains(self, haystack) { @@ -1021,7 +1024,7 @@ impl<'b> Pattern for &'b str { fn strip_prefix_of(self, haystack: &str) -> Option<&str> { if self.is_prefix_of(haystack) { // SAFETY: prefix was just verified to exist. - unsafe { Some(haystack.get_unchecked(self.as_bytes().len()..)) } + unsafe { Some(haystack.get_unchecked(self.len()..)) } } else { None } @@ -1043,7 +1046,7 @@ impl<'b> Pattern for &'b str { Self::Searcher<'a>: ReverseSearcher<'a>, { if self.is_suffix_of(haystack) { - let i = haystack.len() - self.as_bytes().len(); + let i = haystack.len() - self.len(); // SAFETY: suffix was just verified to exist. unsafe { Some(haystack.get_unchecked(..i)) } } else { @@ -1053,7 +1056,7 @@ impl<'b> Pattern for &'b str { #[inline] fn as_utf8_pattern(&self) -> Option> { - Some(Utf8Pattern::StringPattern(self.as_bytes())) + Some(Utf8Pattern::StringPattern(self)) } } @@ -1073,6 +1076,7 @@ pub struct StrSearcher<'a, 'b> { #[derive(Clone, Debug)] enum StrSearcherImpl { Empty(EmptyNeedle), + Byte(ByteNeedle), TwoWay(TwoWaySearcher), } @@ -1086,6 +1090,16 @@ struct EmptyNeedle { is_finished: bool, } +/// Fast searcher for a single-byte needle using `memchr`/`memrchr`. +#[derive(Clone, Debug)] +struct ByteNeedle { + b: u8, + /// Forward cursor: `haystack[..position]` has already been reported. + position: usize, + /// Backward cursor: `haystack[end..]` has already been reported. + end: usize, +} + impl<'a, 'b> StrSearcher<'a, 'b> { fn new(haystack: &'a str, needle: &'b str) -> StrSearcher<'a, 'b> { if needle.is_empty() { @@ -1100,6 +1114,12 @@ impl<'a, 'b> StrSearcher<'a, 'b> { is_finished: false, }), } + } else if let &[b] = needle.as_bytes() { + StrSearcher { + haystack, + needle, + searcher: StrSearcherImpl::Byte(ByteNeedle { b, position: 0, end: haystack.len() }), + } } else { StrSearcher { haystack, @@ -1142,6 +1162,23 @@ unsafe impl<'a, 'b> Searcher<'a> for StrSearcher<'a, 'b> { } } } + StrSearcherImpl::Byte(ref mut searcher) => { + let bytes = self.haystack.as_bytes(); + let pos = searcher.position; + if pos >= bytes.len() { + return SearchStep::Done; + } + if bytes[pos] == searcher.b { + searcher.position = pos + 1; + SearchStep::Match(pos, pos + 1) + } else { + // `pos` is always on a char boundary, so this rejects + // exactly the char starting at `pos`. + let end = self.haystack.ceil_char_boundary(pos + 1); + searcher.position = end; + SearchStep::Reject(pos, end) + } + } StrSearcherImpl::TwoWay(ref mut searcher) => { // TwoWaySearcher produces valid *Match* indices that split at char boundaries // as long as it does correct matching and that haystack and needle are @@ -1157,11 +1194,9 @@ unsafe impl<'a, 'b> Searcher<'a> for StrSearcher<'a, 'b> { self.needle.as_bytes(), is_long, ) { - SearchStep::Reject(a, mut b) => { + SearchStep::Reject(a, b) => { // skip to next char boundary - while !self.haystack.is_char_boundary(b) { - b += 1; - } + let b = self.haystack.ceil_char_boundary(b); searcher.position = cmp::max(b, searcher.position); SearchStep::Reject(a, b) } @@ -1181,6 +1216,23 @@ unsafe impl<'a, 'b> Searcher<'a> for StrSearcher<'a, 'b> { SearchStep::Reject(..) => {} } }, + StrSearcherImpl::Byte(ref mut searcher) => { + let bytes = self.haystack.as_bytes(); + if searcher.position >= bytes.len() { + return None; + } + match memchr::memchr(searcher.b, &bytes[searcher.position..]) { + Some(i) => { + let pos = searcher.position + i; + searcher.position = pos + 1; + Some((pos, pos + 1)) + } + None => { + searcher.position = bytes.len(); + None + } + } + } StrSearcherImpl::TwoWay(ref mut searcher) => { let is_long = searcher.memory == usize::MAX; // write out `true` and `false` cases to encourage the compiler @@ -1226,6 +1278,21 @@ unsafe impl<'a, 'b> ReverseSearcher<'a> for StrSearcher<'a, 'b> { } } } + StrSearcherImpl::Byte(ref mut searcher) => { + let end = searcher.end; + if end == 0 { + return SearchStep::Done; + } + let bytes = self.haystack.as_bytes(); + if bytes[end - 1] == searcher.b { + searcher.end = end - 1; + SearchStep::Match(end - 1, end) + } else { + let start = self.haystack.floor_char_boundary(end - 1); + searcher.end = start; + SearchStep::Reject(start, end) + } + } StrSearcherImpl::TwoWay(ref mut searcher) => { if searcher.end == 0 { return SearchStep::Done; @@ -1236,11 +1303,9 @@ unsafe impl<'a, 'b> ReverseSearcher<'a> for StrSearcher<'a, 'b> { self.needle.as_bytes(), is_long, ) { - SearchStep::Reject(mut a, b) => { - // skip to next char boundary - while !self.haystack.is_char_boundary(a) { - a -= 1; - } + SearchStep::Reject(a, b) => { + // skip to previous char boundary + let a = self.haystack.floor_char_boundary(a); searcher.end = cmp::min(a, searcher.end); SearchStep::Reject(a, b) } @@ -1260,6 +1325,22 @@ unsafe impl<'a, 'b> ReverseSearcher<'a> for StrSearcher<'a, 'b> { SearchStep::Reject(..) => {} } }, + StrSearcherImpl::Byte(ref mut searcher) => { + if searcher.end == 0 { + return None; + } + let bytes = self.haystack.as_bytes(); + match memchr::memrchr(searcher.b, &bytes[..searcher.end]) { + Some(i) => { + searcher.end = i; + Some((i, i + 1)) + } + None => { + searcher.end = 0; + None + } + } + } StrSearcherImpl::TwoWay(ref mut searcher) => { let is_long = searcher.memory == usize::MAX; // write out `true` and `false`, like `next_match` @@ -1498,7 +1579,13 @@ impl TwoWaySearcher { let start = if long_period { self.crit_pos } else { cmp::max(self.crit_pos, self.memory) }; for i in start..needle.len() { - if needle[i] != haystack[self.position + i] { + // SAFETY: on every iteration of `'search`, the `haystack.get(self.position + needle_last)` + // check returned `Some`, so `self.position + needle_last < haystack.len()`. + // Since `i < needle.len()` implies `i <= needle_last`, we have + // `self.position + i < haystack.len()`. + // Every path that mutates `self.position` below either returns or re-enters `'search`, + // which re-runs the check before reaching the loop again. + if needle[i] != unsafe { *haystack.get_unchecked(self.position + i) } { self.position += i - self.crit_pos + 1; if !long_period { self.memory = 0; @@ -1510,7 +1597,13 @@ impl TwoWaySearcher { // See if the left part of the needle matches let start = if long_period { 0 } else { self.memory }; for i in (start..self.crit_pos).rev() { - if needle[i] != haystack[self.position + i] { + // SAFETY: on every iteration of `'search`, the `haystack.get(self.position + needle_last)` + // check returned `Some`, so `self.position + needle_last < haystack.len()`. + // Since `i < self.crit_pos <= needle.len()`, we have `i <= needle_last`, and thus + // `self.position + i <= self.position + needle_last < haystack.len()`. + // Every path that mutates `self.position` below either returns or re-enters `'search`, + // which re-runs the check before reaching the loop again. + if needle[i] != unsafe { *haystack.get_unchecked(self.position + i) } { self.position += self.period; if !long_period { self.memory = needle.len() - self.period; @@ -1585,7 +1678,14 @@ impl TwoWaySearcher { cmp::min(self.crit_pos_back, self.memory_back) }; for i in (0..crit).rev() { - if needle[i] != haystack[self.end - needle.len() + i] { + // SAFETY: On every iteration of `'search`, `haystack.get(self.end.wrapping_sub(needle.len()))` + // returned `Some`, so `self.end >= needle.len()` and `self.end - needle.len() < haystack.len()`. + // Since `self.end <= haystack.len()` and `i < needle.len()`, we have + // `self.end - needle.len() + i < self.end <= haystack.len()`, so + // `haystack.get_unchecked(self.end - needle.len() + i)` is safe. + // - The path that mutates `self.end` either re-enters `'search`, which re-runs the checks + // before reaching this loop again, or returns on match, so the invariant holds. + if needle[i] != unsafe { *haystack.get_unchecked(self.end - needle.len() + i) } { self.end -= self.crit_pos_back - i; if !long_period { self.memory_back = needle.len(); @@ -1597,7 +1697,12 @@ impl TwoWaySearcher { // See if the right part of the needle matches let needle_end = if long_period { needle.len() } else { self.memory_back }; for i in self.crit_pos_back..needle_end { - if needle[i] != haystack[self.end - needle.len() + i] { + // SAFETY: The same `self.end - needle.len() + i < haystack.len()` argument as the + // left-part loop applies: the `haystack.get(self.end.wrapping_sub(needle.len()))` + // check at the top of `'search` established the bound for this iteration, and + // every mutation of `self.end` is followed by `continue 'search` (which re-runs + // the check) or a `return` (which exits before any further unsafe access). + if needle[i] != unsafe { *haystack.get_unchecked(self.end - needle.len() + i) } { self.end -= self.period; if !long_period { self.memory_back = self.period; @@ -1787,7 +1892,8 @@ impl TwoWayStrategy for RejectAndMatch { /// [0]: http://0x80.pl/articles/simd-strfind.html#sse-avx2 #[cfg(any( all(target_arch = "x86_64", target_feature = "sse2"), - all(target_arch = "loongarch64", target_feature = "lsx") + all(target_arch = "loongarch64", target_feature = "lsx"), + all(target_arch = "aarch64", target_feature = "neon") ))] #[inline] fn simd_contains(needle: &str, haystack: &str) -> Option { @@ -1868,9 +1974,7 @@ fn simd_contains(needle: &str, haystack: &str) -> Option { let eq_first: Mask = a.simd_eq(first_probe); let eq_last: Mask = b.simd_eq(second_probe); let both = eq_first.bitand(eq_last); - let mask = both.to_bitmask() as u16; - - mask + both.to_bitmask() as u16 }; let mut i = 0; @@ -1922,7 +2026,8 @@ fn simd_contains(needle: &str, haystack: &str) -> Option { /// Both slices must have the same length. #[cfg(any( all(target_arch = "x86_64", any(kani, target_feature = "sse2")), - all(target_arch = "loongarch64", target_feature = "lsx") + all(target_arch = "loongarch64", target_feature = "lsx"), + all(target_arch = "aarch64", target_feature = "neon") ))] #[inline] #[requires(x.len() == y.len())] diff --git a/library/core/src/str/traits.rs b/library/core/src/str/traits.rs index a7cc943994c53..e4bf752ad2ae6 100644 --- a/library/core/src/str/traits.rs +++ b/library/core/src/str/traits.rs @@ -5,7 +5,7 @@ use crate::cmp::Ordering; use crate::intrinsics::unchecked_sub; use crate::slice::SliceIndex; use crate::ub_checks::assert_unsafe_precondition; -use crate::{ops, ptr, range}; +use crate::{ops, range}; /// Implements ordering of strings. /// @@ -24,7 +24,7 @@ impl Ord for str { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq for str { +const impl PartialEq for str { #[inline] fn eq(&self, other: &str) -> bool { self.as_bytes() == other.as_bytes() @@ -33,7 +33,7 @@ impl const PartialEq for str { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const Eq for str {} +const impl Eq for str {} /// Implements comparison operations on strings. /// @@ -52,7 +52,7 @@ impl PartialOrd for str { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -impl const ops::Index for str +const impl ops::Index for str where I: [const] SliceIndex, { @@ -66,7 +66,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -impl const ops::IndexMut for str +const impl ops::IndexMut for str where I: [const] SliceIndex, { @@ -76,13 +76,6 @@ where } } -#[inline(never)] -#[cold] -#[track_caller] -const fn str_index_overflow_fail() -> ! { - panic!("attempted to index str up to maximum usize"); -} - /// Implements substring slicing with syntax `&self[..]` or `&mut self[..]`. /// /// Returns a slice of the whole string, i.e., returns `&self` or `&mut @@ -97,7 +90,7 @@ const fn str_index_overflow_fail() -> ! { /// Equivalent to `&self[0 .. len]` or `&mut self[0 .. len]`. #[stable(feature = "str_checked_slicing", since = "1.20.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex for ops::RangeFull { +const unsafe impl SliceIndex for ops::RangeFull { type Output = str; #[inline] fn get(self, slice: &str) -> Option<&Self::Output> { @@ -125,6 +118,35 @@ unsafe impl const SliceIndex for ops::RangeFull { } } +/// Check that a range is in bounds for slicing a string. +/// If this returns true, it is safe to call `slice.get_unchecked(range)` or +/// `slice.get_unchecked_mut(range)`. +#[inline(always)] +const fn check_range(slice: &str, range: crate::range::Range) -> bool { + let crate::range::Range { start, end } = range; + let bytes = slice.as_bytes(); + + if start > end || end > slice.len() { + return false; + } + + if start == slice.len() { + // If `start == slice.len()`, then `end == slice.len()` must also be true. + return true; + } + + // SAFETY: + // `start > end || end > slice.len()` is false, so `start <= end <= slice.len()` is true. + // `start == slice.len()` is false, so `start < slice.len()` is also true. + // + // No need to check for `end == 0`, because if `end == 0` is true then `start == slice.len()` + // would also be true, which is already handled above. + unsafe { + (start == 0 || bytes.as_ptr().add(start).read().is_utf8_char_boundary()) + && (end == slice.len() || bytes.as_ptr().add(end).read().is_utf8_char_boundary()) + } +} + /// Implements substring slicing with syntax `&self[begin .. end]` or `&mut /// self[begin .. end]`. /// @@ -162,34 +184,15 @@ unsafe impl const SliceIndex for ops::RangeFull { /// ``` #[stable(feature = "str_checked_slicing", since = "1.20.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex for ops::Range { +const unsafe impl SliceIndex for ops::Range { type Output = str; #[inline] fn get(self, slice: &str) -> Option<&Self::Output> { - if self.start <= self.end - && slice.is_char_boundary(self.start) - && slice.is_char_boundary(self.end) - { - // SAFETY: just checked that `start` and `end` are on a char boundary, - // and we are passing in a safe reference, so the return value will also be one. - // We also checked char boundaries, so this is valid UTF-8. - Some(unsafe { &*self.get_unchecked(slice) }) - } else { - None - } + range::Range::from(self).get(slice) } #[inline] fn get_mut(self, slice: &mut str) -> Option<&mut Self::Output> { - if self.start <= self.end - && slice.is_char_boundary(self.start) - && slice.is_char_boundary(self.end) - { - // SAFETY: just checked that `start` and `end` are on a char boundary. - // We know the pointer is unique because we got it from `slice`. - Some(unsafe { &mut *self.get_unchecked_mut(slice) }) - } else { - None - } + range::Range::from(self).get_mut(slice) } #[inline] #[track_caller] @@ -216,7 +219,7 @@ unsafe impl const SliceIndex for ops::Range { // which satisfies all the conditions for `add`. unsafe { let new_len = unchecked_sub(self.end, self.start); - ptr::slice_from_raw_parts(slice.as_ptr().add(self.start), new_len) as *const str + slice.as_ptr().add(self.start).cast_slice(new_len) as *const str } } #[inline] @@ -237,45 +240,27 @@ unsafe impl const SliceIndex for ops::Range { // SAFETY: see comments for `get_unchecked`. unsafe { let new_len = unchecked_sub(self.end, self.start); - ptr::slice_from_raw_parts_mut(slice.as_mut_ptr().add(self.start), new_len) as *mut str + slice.as_mut_ptr().add(self.start).cast_slice(new_len) as *mut str } } #[inline] fn index(self, slice: &str) -> &Self::Output { - let (start, end) = (self.start, self.end); - match self.get(slice) { - Some(s) => s, - None => super::slice_error_fail(slice, start, end), - } + range::Range::from(self).index(slice) } #[inline] fn index_mut(self, slice: &mut str) -> &mut Self::Output { - // is_char_boundary checks that the index is in [0, .len()] - // cannot reuse `get` as above, because of NLL trouble - if self.start <= self.end - && slice.is_char_boundary(self.start) - && slice.is_char_boundary(self.end) - { - // SAFETY: just checked that `start` and `end` are on a char boundary, - // and we are passing in a safe reference, so the return value will also be one. - unsafe { &mut *self.get_unchecked_mut(slice) } - } else { - super::slice_error_fail(slice, self.start, self.end) - } + range::Range::from(self).index_mut(slice) } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex for range::Range { +const unsafe impl SliceIndex for range::Range { type Output = str; #[inline] fn get(self, slice: &str) -> Option<&Self::Output> { - if self.start <= self.end - && slice.is_char_boundary(self.start) - && slice.is_char_boundary(self.end) - { - // SAFETY: just checked that `start` and `end` are on a char boundary, + if check_range(slice, self) { + // SAFETY: just checked that `self` is in bounds, // and we are passing in a safe reference, so the return value will also be one. // We also checked char boundaries, so this is valid UTF-8. Some(unsafe { &*self.get_unchecked(slice) }) @@ -285,11 +270,8 @@ unsafe impl const SliceIndex for range::Range { } #[inline] fn get_mut(self, slice: &mut str) -> Option<&mut Self::Output> { - if self.start <= self.end - && slice.is_char_boundary(self.start) - && slice.is_char_boundary(self.end) - { - // SAFETY: just checked that `start` and `end` are on a char boundary. + if check_range(slice, self) { + // SAFETY: just checked that `self` is in bounds. // We know the pointer is unique because we got it from `slice`. Some(unsafe { &mut *self.get_unchecked_mut(slice) }) } else { @@ -321,7 +303,7 @@ unsafe impl const SliceIndex for range::Range { // which satisfies all the conditions for `add`. unsafe { let new_len = unchecked_sub(self.end, self.start); - ptr::slice_from_raw_parts(slice.as_ptr().add(self.start), new_len) as *const str + slice.as_ptr().add(self.start).cast_slice(new_len) as *const str } } #[inline] @@ -342,7 +324,7 @@ unsafe impl const SliceIndex for range::Range { // SAFETY: see comments for `get_unchecked`. unsafe { let new_len = unchecked_sub(self.end, self.start); - ptr::slice_from_raw_parts_mut(slice.as_mut_ptr().add(self.start), new_len) as *mut str + slice.as_mut_ptr().add(self.start).cast_slice(new_len) as *mut str } } #[inline] @@ -355,13 +337,9 @@ unsafe impl const SliceIndex for range::Range { } #[inline] fn index_mut(self, slice: &mut str) -> &mut Self::Output { - // is_char_boundary checks that the index is in [0, .len()] // cannot reuse `get` as above, because of NLL trouble - if self.start <= self.end - && slice.is_char_boundary(self.start) - && slice.is_char_boundary(self.end) - { - // SAFETY: just checked that `start` and `end` are on a char boundary, + if check_range(slice, self) { + // SAFETY: just checked that `self` is in bounds, // and we are passing in a safe reference, so the return value will also be one. unsafe { &mut *self.get_unchecked_mut(slice) } } else { @@ -389,12 +367,12 @@ unsafe impl SliceIndex for (ops::Bound, ops::Bound) { #[inline] fn get(self, slice: &str) -> Option<&str> { - crate::slice::index::into_range(slice.len(), self)?.get(slice) + crate::slice::index::try_into_slice_range(slice.len(), self)?.get(slice) } #[inline] fn get_mut(self, slice: &mut str) -> Option<&mut str> { - crate::slice::index::into_range(slice.len(), self)?.get_mut(slice) + crate::slice::index::try_into_slice_range(slice.len(), self)?.get_mut(slice) } #[inline] @@ -439,7 +417,7 @@ unsafe impl SliceIndex for (ops::Bound, ops::Bound) { /// character (as defined by `is_char_boundary`), or if `end > len`. #[stable(feature = "str_checked_slicing", since = "1.20.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex for ops::RangeTo { +const unsafe impl SliceIndex for ops::RangeTo { type Output = str; #[inline] fn get(self, slice: &str) -> Option<&Self::Output> { @@ -508,7 +486,7 @@ unsafe impl const SliceIndex for ops::RangeTo { /// a character (as defined by `is_char_boundary`), or if `begin > len`. #[stable(feature = "str_checked_slicing", since = "1.20.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex for ops::RangeFrom { +const unsafe impl SliceIndex for ops::RangeFrom { type Output = str; #[inline] fn get(self, slice: &str) -> Option<&Self::Output> { @@ -562,9 +540,9 @@ unsafe impl const SliceIndex for ops::RangeFrom { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex for range::RangeFrom { +const unsafe impl SliceIndex for range::RangeFrom { type Output = str; #[inline] fn get(self, slice: &str) -> Option<&Self::Output> { @@ -636,15 +614,15 @@ unsafe impl const SliceIndex for range::RangeFrom { /// byte offset or equal to `len`), if `begin > end`, or if `end >= len`. #[stable(feature = "inclusive_range", since = "1.26.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex for ops::RangeInclusive { +const unsafe impl SliceIndex for ops::RangeInclusive { type Output = str; #[inline] fn get(self, slice: &str) -> Option<&Self::Output> { - if *self.end() == usize::MAX { None } else { self.into_slice_range().get(slice) } + if *self.end() >= slice.len() { None } else { self.into_slice_range().get(slice) } } #[inline] fn get_mut(self, slice: &mut str) -> Option<&mut Self::Output> { - if *self.end() == usize::MAX { None } else { self.into_slice_range().get_mut(slice) } + if *self.end() >= slice.len() { None } else { self.into_slice_range().get_mut(slice) } } #[inline] unsafe fn get_unchecked(self, slice: *const str) -> *const Self::Output { @@ -658,55 +636,69 @@ unsafe impl const SliceIndex for ops::RangeInclusive { } #[inline] fn index(self, slice: &str) -> &Self::Output { - if *self.end() == usize::MAX { - str_index_overflow_fail(); + let Self { mut start, mut end, exhausted } = self; + let len = slice.len(); + if end < len { + end = end + 1; + start = if exhausted { end } else { start }; + if start <= end && slice.is_char_boundary(start) && slice.is_char_boundary(end) { + // SAFETY: just checked that `start` and `end` are on a char boundary, + // and we are passing in a safe reference, so the return value will also be one. + // We also checked char boundaries, so this is valid UTF-8. + unsafe { return &*(start..end).get_unchecked(slice) } + } } - self.into_slice_range().index(slice) + + super::slice_error_fail(slice, start, end) } #[inline] fn index_mut(self, slice: &mut str) -> &mut Self::Output { - if *self.end() == usize::MAX { - str_index_overflow_fail(); + let Self { mut start, mut end, exhausted } = self; + let len = slice.len(); + if end < len { + end = end + 1; + start = if exhausted { end } else { start }; + if start <= end && slice.is_char_boundary(start) && slice.is_char_boundary(end) { + // SAFETY: just checked that `start` and `end` are on a char boundary, + // and we are passing in a safe reference, so the return value will also be one. + // We also checked char boundaries, so this is valid UTF-8. + unsafe { return &mut *(start..end).get_unchecked_mut(slice) } + } } - self.into_slice_range().index_mut(slice) + + super::slice_error_fail(slice, start, end) } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex for range::RangeInclusive { +const unsafe impl SliceIndex for range::RangeInclusive { type Output = str; #[inline] fn get(self, slice: &str) -> Option<&Self::Output> { - if self.last == usize::MAX { None } else { self.into_slice_range().get(slice) } + ops::RangeInclusive::from(self).get(slice) } #[inline] fn get_mut(self, slice: &mut str) -> Option<&mut Self::Output> { - if self.last == usize::MAX { None } else { self.into_slice_range().get_mut(slice) } + ops::RangeInclusive::from(self).get_mut(slice) } #[inline] unsafe fn get_unchecked(self, slice: *const str) -> *const Self::Output { // SAFETY: the caller must uphold the safety contract for `get_unchecked`. - unsafe { self.into_slice_range().get_unchecked(slice) } + unsafe { ops::RangeInclusive::from(self).get_unchecked(slice) } } #[inline] unsafe fn get_unchecked_mut(self, slice: *mut str) -> *mut Self::Output { // SAFETY: the caller must uphold the safety contract for `get_unchecked_mut`. - unsafe { self.into_slice_range().get_unchecked_mut(slice) } + unsafe { ops::RangeInclusive::from(self).get_unchecked_mut(slice) } } #[inline] fn index(self, slice: &str) -> &Self::Output { - if self.last == usize::MAX { - str_index_overflow_fail(); - } - self.into_slice_range().index(slice) + ops::RangeInclusive::from(self).index(slice) } #[inline] fn index_mut(self, slice: &mut str) -> &mut Self::Output { - if self.last == usize::MAX { - str_index_overflow_fail(); - } - self.into_slice_range().index_mut(slice) + ops::RangeInclusive::from(self).index_mut(slice) } } @@ -726,7 +718,7 @@ unsafe impl const SliceIndex for range::RangeInclusive { /// `is_char_boundary`, or equal to `len`), or if `end >= len`. #[stable(feature = "inclusive_range", since = "1.26.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex for ops::RangeToInclusive { +const unsafe impl SliceIndex for ops::RangeToInclusive { type Output = str; #[inline] fn get(self, slice: &str) -> Option<&Self::Output> { @@ -756,6 +748,52 @@ unsafe impl const SliceIndex for ops::RangeToInclusive { } } +/// Implements substring slicing with syntax `&self[..= last]` or `&mut +/// self[..= last]`. +/// +/// Returns a slice of the given string from the byte range \[0, `last`\]. +/// Equivalent to `&self [0 .. last + 1]`, except if `last` has the maximum +/// value for `usize`. +/// +/// This operation is *O*(1). +/// +/// # Panics +/// +/// Panics if `last` does not point to the ending byte offset of a character +/// (`last + 1` is either a starting byte offset as defined by +/// `is_char_boundary`, or equal to `len`), or if `last >= len`. +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] +#[rustc_const_unstable(feature = "const_index", issue = "143775")] +const unsafe impl SliceIndex for range::RangeToInclusive { + type Output = str; + #[inline] + fn get(self, slice: &str) -> Option<&Self::Output> { + (0..=self.last).get(slice) + } + #[inline] + fn get_mut(self, slice: &mut str) -> Option<&mut Self::Output> { + (0..=self.last).get_mut(slice) + } + #[inline] + unsafe fn get_unchecked(self, slice: *const str) -> *const Self::Output { + // SAFETY: the caller must uphold the safety contract for `get_unchecked`. + unsafe { (0..=self.last).get_unchecked(slice) } + } + #[inline] + unsafe fn get_unchecked_mut(self, slice: *mut str) -> *mut Self::Output { + // SAFETY: the caller must uphold the safety contract for `get_unchecked_mut`. + unsafe { (0..=self.last).get_unchecked_mut(slice) } + } + #[inline] + fn index(self, slice: &str) -> &Self::Output { + (0..=self.last).index(slice) + } + #[inline] + fn index_mut(self, slice: &mut str) -> &mut Self::Output { + (0..=self.last).index_mut(slice) + } +} + /// Parse a value from a string /// /// `FromStr`'s [`from_str`] method is often used implicitly, through diff --git a/library/core/src/sync/atomic.rs b/library/core/src/sync/atomic.rs index 22f46ec385ced..e676a3851112d 100644 --- a/library/core/src/sync/atomic.rs +++ b/library/core/src/sync/atomic.rs @@ -238,7 +238,6 @@ #![stable(feature = "rust1", since = "1.0.0")] #![cfg_attr(not(target_has_atomic_load_store = "8"), allow(dead_code))] #![cfg_attr(not(target_has_atomic_load_store = "8"), allow(unused_imports))] -#![rustc_diagnostic_item = "atomic_mod"] // Clippy complains about the pattern of "safe function calling unsafe function taking pointers". // This happens with AtomicPtr intrinsics but is fine, as the pointers clippy is concerned about // are just normal values that get loaded/stored, but not dereferenced. @@ -248,84 +247,123 @@ use self::Ordering::*; use crate::cell::UnsafeCell; use crate::hint::spin_loop; use crate::intrinsics::AtomicOrdering as AO; +use crate::mem::transmute; use crate::{fmt, intrinsics}; -trait Sealed {} +#[unstable( + feature = "atomic_internals", + reason = "implementation detail which may disappear or be replaced at any time", + issue = "none" +)] +#[expect(missing_debug_implementations)] +mod private { + #[cfg(target_has_atomic_load_store = "8")] + #[repr(C, align(1))] + pub struct Align1(T); + #[cfg(target_has_atomic_load_store = "16")] + #[repr(C, align(2))] + pub struct Align2(T); + #[cfg(target_has_atomic_load_store = "32")] + #[repr(C, align(4))] + pub struct Align4(T); + #[cfg(target_has_atomic_load_store = "64")] + #[repr(C, align(8))] + pub struct Align8(T); + #[cfg(any(target_has_atomic_load_store = "128", doc))] + #[repr(C, align(16))] + pub struct Align16(T); +} /// A marker trait for primitive types which can be modified atomically. /// /// This is an implementation detail for [Atomic]\ which may disappear or be replaced at any time. -/// -/// # Safety -/// -/// Types implementing this trait must be primitives that can be modified atomically. -/// -/// The associated `Self::AtomicInner` type must have the same size and bit validity as `Self`, -/// but may have a higher alignment requirement, so the following `transmute`s are sound: -/// -/// - `&mut Self::AtomicInner` as `&mut Self` -/// - `Self` as `Self::AtomicInner` or the reverse +// +// # Safety +// +// Types implementing this trait must be primitives that can be modified atomically. +// +// The associated `Self::Storage` type must have the same size, but may have fewer validity +// invariants or a higher alignment requirement than `Self`. #[unstable( feature = "atomic_internals", reason = "implementation detail which may disappear or be replaced at any time", issue = "none" )] -#[expect(private_bounds)] -pub unsafe trait AtomicPrimitive: Sized + Copy + Sealed { +pub impl(self) unsafe trait AtomicPrimitive: Sized + Copy { /// Temporary implementation detail. - type AtomicInner: Sized; + type Storage: Sized; } -macro impl_atomic_primitive( - $Atom:ident $(<$T:ident>)? ($Primitive:ty), - size($size:literal), - align($align:literal) $(,)? -) { - impl $(<$T>)? Sealed for $Primitive {} - - #[unstable( - feature = "atomic_internals", - reason = "implementation detail which may disappear or be replaced at any time", - issue = "none" - )] - #[cfg(target_has_atomic_load_store = $size)] - unsafe impl $(<$T>)? AtomicPrimitive for $Primitive { - type AtomicInner = $Atom $(<$T>)?; - } +macro impl_atomic_primitive { + ( + @impl [$($T:ident)?] $Primitive:ty as $Storage:ident<$Operand:ty>, + $cfg:meta + ) => { + #[unstable( + feature = "atomic_internals", + reason = "implementation detail which may disappear or be replaced at any time", + issue = "none" + )] + #[cfg($cfg)] + unsafe impl $(<$T>)? AtomicPrimitive for $Primitive { + type Storage = private::$Storage<$Operand>; + } + }, + + ( + [$($T:ident)?] $Primitive:ty as $Storage:ident<$Operand:ty>, + size($size:literal) + ) => { + impl_atomic_primitive!( + @impl [$($T)?] $Primitive as $Storage<$Operand>, + target_has_atomic_load_store = $size + ); + }, + + ( + [$($T:ident)?] $Primitive:ty as $Storage:ident<$Operand:ty>, + size($size:literal), + doc + ) => { + impl_atomic_primitive!( + @impl [$($T)?] $Primitive as $Storage<$Operand>, + any(target_has_atomic_load_store = $size, doc) + ); + }, } -impl_atomic_primitive!(AtomicBool(bool), size("8"), align(1)); -impl_atomic_primitive!(AtomicI8(i8), size("8"), align(1)); -impl_atomic_primitive!(AtomicU8(u8), size("8"), align(1)); -impl_atomic_primitive!(AtomicI16(i16), size("16"), align(2)); -impl_atomic_primitive!(AtomicU16(u16), size("16"), align(2)); -impl_atomic_primitive!(AtomicI32(i32), size("32"), align(4)); -impl_atomic_primitive!(AtomicU32(u32), size("32"), align(4)); -impl_atomic_primitive!(AtomicI64(i64), size("64"), align(8)); -impl_atomic_primitive!(AtomicU64(u64), size("64"), align(8)); -impl_atomic_primitive!(AtomicI128(i128), size("128"), align(16)); -impl_atomic_primitive!(AtomicU128(u128), size("128"), align(16)); +impl_atomic_primitive!([] bool as Align1, size("8")); +impl_atomic_primitive!([] i8 as Align1, size("8")); +impl_atomic_primitive!([] u8 as Align1, size("8")); +impl_atomic_primitive!([] i16 as Align2, size("16")); +impl_atomic_primitive!([] u16 as Align2, size("16")); +impl_atomic_primitive!([] i32 as Align4, size("32")); +impl_atomic_primitive!([] u32 as Align4, size("32")); +impl_atomic_primitive!([] i64 as Align8, size("64")); +impl_atomic_primitive!([] u64 as Align8, size("64")); +impl_atomic_primitive!([] i128 as Align16, size("128"), doc); +impl_atomic_primitive!([] u128 as Align16, size("128"), doc); #[cfg(target_pointer_width = "16")] -impl_atomic_primitive!(AtomicIsize(isize), size("ptr"), align(2)); +impl_atomic_primitive!([] isize as Align2, size("ptr")); #[cfg(target_pointer_width = "32")] -impl_atomic_primitive!(AtomicIsize(isize), size("ptr"), align(4)); +impl_atomic_primitive!([] isize as Align4, size("ptr")); #[cfg(target_pointer_width = "64")] -impl_atomic_primitive!(AtomicIsize(isize), size("ptr"), align(8)); +impl_atomic_primitive!([] isize as Align8, size("ptr")); #[cfg(target_pointer_width = "16")] -impl_atomic_primitive!(AtomicUsize(usize), size("ptr"), align(2)); +impl_atomic_primitive!([] usize as Align2, size("ptr")); #[cfg(target_pointer_width = "32")] -impl_atomic_primitive!(AtomicUsize(usize), size("ptr"), align(4)); +impl_atomic_primitive!([] usize as Align4, size("ptr")); #[cfg(target_pointer_width = "64")] -impl_atomic_primitive!(AtomicUsize(usize), size("ptr"), align(8)); +impl_atomic_primitive!([] usize as Align8, size("ptr")); #[cfg(target_pointer_width = "16")] -impl_atomic_primitive!(AtomicPtr(*mut T), size("ptr"), align(2)); +impl_atomic_primitive!([T] *mut T as Align2<*mut T>, size("ptr")); #[cfg(target_pointer_width = "32")] -impl_atomic_primitive!(AtomicPtr(*mut T), size("ptr"), align(4)); +impl_atomic_primitive!([T] *mut T as Align4<*mut T>, size("ptr")); #[cfg(target_pointer_width = "64")] -impl_atomic_primitive!(AtomicPtr(*mut T), size("ptr"), align(8)); +impl_atomic_primitive!([T] *mut T as Align8<*mut T>, size("ptr")); /// A memory location which can be safely modified from multiple threads. /// @@ -342,7 +380,16 @@ impl_atomic_primitive!(AtomicPtr(*mut T), size("ptr"), align(8)); /// /// [module-level documentation]: crate::sync::atomic #[unstable(feature = "generic_atomic", issue = "130539")] -pub type Atomic = ::AtomicInner; +#[repr(C)] +#[rustc_diagnostic_item = "Atomic"] +pub struct Atomic { + v: UnsafeCell, +} + +#[stable(feature = "rust1", since = "1.0.0")] +unsafe impl Send for Atomic {} +#[stable(feature = "rust1", since = "1.0.0")] +unsafe impl Sync for Atomic {} // Some architectures don't have byte-sized atomics, which results in LLVM // emulating them using a LL/SC loop. However for AtomicBool we can take @@ -367,11 +414,7 @@ const EMULATE_ATOMIC_BOOL: bool = cfg!(any( /// loads and stores of `u8`. #[cfg(target_has_atomic_load_store = "8")] #[stable(feature = "rust1", since = "1.0.0")] -#[rustc_diagnostic_item = "AtomicBool"] -#[repr(C, align(1))] -pub struct AtomicBool { - v: UnsafeCell, -} +pub type AtomicBool = Atomic; #[cfg(target_has_atomic_load_store = "8")] #[stable(feature = "rust1", since = "1.0.0")] @@ -383,11 +426,6 @@ impl Default for AtomicBool { } } -// Send is implicitly implemented for AtomicBool. -#[cfg(target_has_atomic_load_store = "8")] -#[stable(feature = "rust1", since = "1.0.0")] -unsafe impl Sync for AtomicBool {} - /// A raw pointer type which can be safely shared between threads. /// /// This type has the same size and bit validity as a `*mut T`. @@ -396,13 +434,7 @@ unsafe impl Sync for AtomicBool {} /// loads and stores of pointers. Its size depends on the target pointer's size. #[cfg(target_has_atomic_load_store = "ptr")] #[stable(feature = "rust1", since = "1.0.0")] -#[rustc_diagnostic_item = "AtomicPtr"] -#[cfg_attr(target_pointer_width = "16", repr(C, align(2)))] -#[cfg_attr(target_pointer_width = "32", repr(C, align(4)))] -#[cfg_attr(target_pointer_width = "64", repr(C, align(8)))] -pub struct AtomicPtr { - p: UnsafeCell<*mut T>, -} +pub type AtomicPtr = Atomic<*mut T>; #[cfg(target_has_atomic_load_store = "ptr")] #[stable(feature = "rust1", since = "1.0.0")] @@ -413,13 +445,6 @@ impl Default for AtomicPtr { } } -#[cfg(target_has_atomic_load_store = "ptr")] -#[stable(feature = "rust1", since = "1.0.0")] -unsafe impl Send for AtomicPtr {} -#[cfg(target_has_atomic_load_store = "ptr")] -#[stable(feature = "rust1", since = "1.0.0")] -unsafe impl Sync for AtomicPtr {} - /// Atomic memory orderings /// /// Memory orderings specify the way atomic operations synchronize memory. @@ -528,7 +553,9 @@ impl AtomicBool { #[rustc_const_stable(feature = "const_atomic_new", since = "1.24.0")] #[must_use] pub const fn new(v: bool) -> AtomicBool { - AtomicBool { v: UnsafeCell::new(v as u8) } + // SAFETY: + // `Atomic` is essentially a transparent wrapper around `T`. + unsafe { transmute(v) } } /// Creates a new `AtomicBool` from a pointer. @@ -595,9 +622,10 @@ impl AtomicBool { /// ``` #[inline] #[stable(feature = "atomic_access", since = "1.15.0")] - pub fn get_mut(&mut self) -> &mut bool { + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] + pub const fn get_mut(&mut self) -> &mut bool { // SAFETY: the mutable reference guarantees unique ownership. - unsafe { &mut *(self.v.get() as *mut bool) } + unsafe { &mut *self.as_ptr() } } /// Gets atomic access to a `&mut bool`. @@ -605,7 +633,6 @@ impl AtomicBool { /// # Examples /// /// ``` - /// #![feature(atomic_from_mut)] /// use std::sync::atomic::{AtomicBool, Ordering}; /// /// let mut some_bool = true; @@ -614,9 +641,10 @@ impl AtomicBool { /// assert_eq!(some_bool, false); /// ``` #[inline] - #[cfg(target_has_atomic_equal_alignment = "8")] - #[unstable(feature = "atomic_from_mut", issue = "76314")] - pub fn from_mut(v: &mut bool) -> &mut Self { + #[cfg(target_has_atomic_primitive_alignment = "8")] + #[stable(feature = "atomic_from_mut", since = "1.98.0")] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] + pub const fn from_mut(v: &mut bool) -> &mut Self { // SAFETY: the mutable reference guarantees unique ownership, and // alignment of both `bool` and `Self` is 1. unsafe { &mut *(v as *mut bool as *mut Self) } @@ -630,7 +658,6 @@ impl AtomicBool { /// # Examples /// /// ```ignore-wasm - /// #![feature(atomic_from_mut)] /// use std::sync::atomic::{AtomicBool, Ordering}; /// /// let mut some_bools = [const { AtomicBool::new(false) }; 10]; @@ -650,8 +677,9 @@ impl AtomicBool { /// }); /// ``` #[inline] - #[unstable(feature = "atomic_from_mut", issue = "76314")] - pub fn get_mut_slice(this: &mut [Self]) -> &mut [bool] { + #[stable(feature = "atomic_from_mut", since = "1.98.0")] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] + pub const fn get_mut_slice(this: &mut [Self]) -> &mut [bool] { // SAFETY: the mutable reference guarantees unique ownership. unsafe { &mut *(this as *mut [Self] as *mut [bool]) } } @@ -661,7 +689,6 @@ impl AtomicBool { /// # Examples /// /// ```rust,ignore-wasm - /// #![feature(atomic_from_mut)] /// use std::sync::atomic::{AtomicBool, Ordering}; /// /// let mut some_bools = [false; 10]; @@ -674,9 +701,10 @@ impl AtomicBool { /// assert_eq!(some_bools, [true; 10]); /// ``` #[inline] - #[cfg(target_has_atomic_equal_alignment = "8")] - #[unstable(feature = "atomic_from_mut", issue = "76314")] - pub fn from_mut_slice(v: &mut [bool]) -> &mut [Self] { + #[cfg(target_has_atomic_primitive_alignment = "8")] + #[stable(feature = "atomic_from_mut", since = "1.98.0")] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] + pub const fn from_mut_slice(v: &mut [bool]) -> &mut [Self] { // SAFETY: the mutable reference guarantees unique ownership, and // alignment of both `bool` and `Self` is 1. unsafe { &mut *(v as *mut [bool] as *mut [Self]) } @@ -699,7 +727,11 @@ impl AtomicBool { #[stable(feature = "atomic_access", since = "1.15.0")] #[rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0")] pub const fn into_inner(self) -> bool { - self.v.into_inner() != 0 + // SAFETY: + // * `Atomic` is essentially a transparent wrapper around `T`. + // * all operations on `Atomic` ensure that `T::Storage` remains + // a valid `bool`. + unsafe { transmute(self) } } /// Loads a value from the bool. @@ -722,11 +754,14 @@ impl AtomicBool { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces - pub fn load(&self, order: Ordering) -> bool { + pub const fn load(&self, order: Ordering) -> bool { // SAFETY: any data races are prevented by atomic intrinsics and the raw // pointer passed in is valid because we got it from a reference. - unsafe { atomic_load(self.v.get(), order) != 0 } + unsafe { + atomic_load::<_, /* VOLATILE */ false>(self.v.get().cast::(), order) != 0 + } } /// Stores a value into the bool. @@ -750,13 +785,14 @@ impl AtomicBool { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn store(&self, val: bool, order: Ordering) { + pub const fn store(&self, val: bool, order: Ordering) { // SAFETY: any data races are prevented by atomic intrinsics and the raw // pointer passed in is valid because we got it from a reference. unsafe { - atomic_store(self.v.get(), val as u8, order); + atomic_store::<_, /* VOLATILE */ false>(self.v.get().cast::(), val as u8, order); } } @@ -782,15 +818,16 @@ impl AtomicBool { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] #[cfg(target_has_atomic = "8")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn swap(&self, val: bool, order: Ordering) -> bool { + pub const fn swap(&self, val: bool, order: Ordering) -> bool { if EMULATE_ATOMIC_BOOL { if val { self.fetch_or(true, order) } else { self.fetch_and(false, order) } } else { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_swap(self.v.get(), val as u8, order) != 0 } + unsafe { atomic_swap(self.v.get().cast::(), val as u8, order) != 0 } } } @@ -846,6 +883,7 @@ impl AtomicBool { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] #[deprecated( since = "1.50.0", note = "Use `compare_exchange` or `compare_exchange_weak` instead" @@ -853,7 +891,7 @@ impl AtomicBool { #[cfg(target_has_atomic = "8")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn compare_and_swap(&self, current: bool, new: bool, order: Ordering) -> bool { + pub const fn compare_and_swap(&self, current: bool, new: bool, order: Ordering) -> bool { match self.compare_exchange(current, new, order, strongest_failure_ordering(order)) { Ok(x) => x, Err(x) => x, @@ -911,11 +949,12 @@ impl AtomicBool { /// [compare-and-swap operation]: https://en.wikipedia.org/wiki/Compare-and-swap #[inline] #[stable(feature = "extended_compare_and_swap", since = "1.10.0")] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] #[doc(alias = "compare_and_swap")] #[cfg(target_has_atomic = "8")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn compare_exchange( + pub const fn compare_exchange( &self, current: bool, new: bool, @@ -950,7 +989,13 @@ impl AtomicBool { } else { // SAFETY: data races are prevented by atomic intrinsics. match unsafe { - atomic_compare_exchange(self.v.get(), current as u8, new as u8, success, failure) + atomic_compare_exchange( + self.v.get().cast::(), + current as u8, + new as u8, + success, + failure, + ) } { Ok(x) => Ok(x != 0), Err(x) => Err(x != 0), @@ -1007,11 +1052,12 @@ impl AtomicBool { /// [compare-and-swap operation]: https://en.wikipedia.org/wiki/Compare-and-swap #[inline] #[stable(feature = "extended_compare_and_swap", since = "1.10.0")] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] #[doc(alias = "compare_and_swap")] #[cfg(target_has_atomic = "8")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn compare_exchange_weak( + pub const fn compare_exchange_weak( &self, current: bool, new: bool, @@ -1024,7 +1070,13 @@ impl AtomicBool { // SAFETY: data races are prevented by atomic intrinsics. match unsafe { - atomic_compare_exchange_weak(self.v.get(), current as u8, new as u8, success, failure) + atomic_compare_exchange_weak( + self.v.get().cast::(), + current as u8, + new as u8, + success, + failure, + ) } { Ok(x) => Ok(x != 0), Err(x) => Err(x != 0), @@ -1065,12 +1117,13 @@ impl AtomicBool { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] #[cfg(target_has_atomic = "8")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn fetch_and(&self, val: bool, order: Ordering) -> bool { + pub const fn fetch_and(&self, val: bool, order: Ordering) -> bool { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_and(self.v.get(), val as u8, order) != 0 } + unsafe { atomic_and(self.v.get().cast::(), val as u8, order) != 0 } } /// Logical "nand" with a boolean value. @@ -1108,10 +1161,11 @@ impl AtomicBool { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] #[cfg(target_has_atomic = "8")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn fetch_nand(&self, val: bool, order: Ordering) -> bool { + pub const fn fetch_nand(&self, val: bool, order: Ordering) -> bool { // We can't use atomic_nand here because it can result in a bool with // an invalid value. This happens because the atomic operation is done // with an 8-bit integer internally, which would set the upper 7 bits. @@ -1161,12 +1215,13 @@ impl AtomicBool { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] #[cfg(target_has_atomic = "8")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn fetch_or(&self, val: bool, order: Ordering) -> bool { + pub const fn fetch_or(&self, val: bool, order: Ordering) -> bool { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_or(self.v.get(), val as u8, order) != 0 } + unsafe { atomic_or(self.v.get().cast::(), val as u8, order) != 0 } } /// Logical "xor" with a boolean value. @@ -1203,12 +1258,13 @@ impl AtomicBool { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] #[cfg(target_has_atomic = "8")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn fetch_xor(&self, val: bool, order: Ordering) -> bool { + pub const fn fetch_xor(&self, val: bool, order: Ordering) -> bool { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_xor(self.v.get(), val as u8, order) != 0 } + unsafe { atomic_xor(self.v.get().cast::(), val as u8, order) != 0 } } /// Logical "not" with a boolean value. @@ -1241,10 +1297,11 @@ impl AtomicBool { /// ``` #[inline] #[stable(feature = "atomic_bool_fetch_not", since = "1.81.0")] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] #[cfg(target_has_atomic = "8")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn fetch_not(&self, order: Ordering) -> bool { + pub const fn fetch_not(&self, order: Ordering) -> bool { self.fetch_xor(true, order) } @@ -1287,73 +1344,27 @@ impl AtomicBool { self.v.get().cast() } - /// Fetches the value, and applies a function to it that returns an optional - /// new value. Returns a `Result` of `Ok(previous_value)` if the function - /// returned `Some(_)`, else `Err(previous_value)`. - /// - /// Note: This may call the function multiple times if the value has been - /// changed from other threads in the meantime, as long as the function - /// returns `Some(_)`, but the function will have been applied only once to - /// the stored value. - /// - /// `fetch_update` takes two [`Ordering`] arguments to describe the memory - /// ordering of this operation. The first describes the required ordering for - /// when the operation finally succeeds while the second describes the - /// required ordering for loads. These correspond to the success and failure - /// orderings of [`AtomicBool::compare_exchange`] respectively. - /// - /// Using [`Acquire`] as success ordering makes the store part of this - /// operation [`Relaxed`], and using [`Release`] makes the final successful - /// load [`Relaxed`]. The (failed) load ordering can only be [`SeqCst`], - /// [`Acquire`] or [`Relaxed`]. - /// - /// **Note:** This method is only available on platforms that support atomic - /// operations on `u8`. - /// - /// # Considerations - /// - /// This method is not magic; it is not provided by the hardware, and does not act like a - /// critical section or mutex. - /// - /// It is implemented on top of an atomic [compare-and-swap operation], and thus is subject to - /// the usual drawbacks of CAS operations. In particular, be careful of the [ABA problem]. - /// - /// [ABA Problem]: https://en.wikipedia.org/wiki/ABA_problem - /// [compare-and-swap operation]: https://en.wikipedia.org/wiki/Compare-and-swap - /// - /// # Examples - /// - /// ```rust - /// use std::sync::atomic::{AtomicBool, Ordering}; - /// - /// let x = AtomicBool::new(false); - /// assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |_| None), Err(false)); - /// assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |x| Some(!x)), Ok(false)); - /// assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |x| Some(!x)), Ok(true)); - /// assert_eq!(x.load(Ordering::SeqCst), false); - /// ``` + /// An alias for [`AtomicBool::try_update`]. #[inline] #[stable(feature = "atomic_fetch_update", since = "1.53.0")] #[cfg(target_has_atomic = "8")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] + #[deprecated( + since = "1.99.0", + note = "renamed to `try_update` for consistency", + suggestion = "try_update" + )] pub fn fetch_update( &self, set_order: Ordering, fetch_order: Ordering, - mut f: F, + f: F, ) -> Result where F: FnMut(bool) -> Option, { - let mut prev = self.load(fetch_order); - while let Some(next) = f(prev) { - match self.compare_exchange_weak(prev, next, set_order, fetch_order) { - x @ Ok(_) => return x, - Err(next_prev) => prev = next_prev, - } - } - Err(prev) + self.try_update(set_order, fetch_order, f) } /// Fetches the value, and applies a function to it that returns an optional @@ -1395,7 +1406,6 @@ impl AtomicBool { /// # Examples /// /// ```rust - /// #![feature(atomic_try_update)] /// use std::sync::atomic::{AtomicBool, Ordering}; /// /// let x = AtomicBool::new(false); @@ -1405,7 +1415,7 @@ impl AtomicBool { /// assert_eq!(x.load(Ordering::SeqCst), false); /// ``` #[inline] - #[unstable(feature = "atomic_try_update", issue = "135894")] + #[stable(feature = "atomic_try_update", since = "1.95.0")] #[cfg(target_has_atomic = "8")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] @@ -1413,11 +1423,16 @@ impl AtomicBool { &self, set_order: Ordering, fetch_order: Ordering, - f: impl FnMut(bool) -> Option, + mut f: impl FnMut(bool) -> Option, ) -> Result { - // FIXME(atomic_try_update): this is currently an unstable alias to `fetch_update`; - // when stabilizing, turn `fetch_update` into a deprecated alias to `try_update`. - self.fetch_update(set_order, fetch_order, f) + let mut prev = self.load(fetch_order); + while let Some(next) = f(prev) { + match self.compare_exchange_weak(prev, next, set_order, fetch_order) { + x @ Ok(_) => return x, + Err(next_prev) => prev = next_prev, + } + } + Err(prev) } /// Fetches the value, applies a function to it that it return a new value. @@ -1454,7 +1469,6 @@ impl AtomicBool { /// # Examples /// /// ```rust - /// #![feature(atomic_try_update)] /// /// use std::sync::atomic::{AtomicBool, Ordering}; /// @@ -1464,7 +1478,7 @@ impl AtomicBool { /// assert_eq!(x.load(Ordering::SeqCst), false); /// ``` #[inline] - #[unstable(feature = "atomic_try_update", issue = "135894")] + #[stable(feature = "atomic_try_update", since = "1.95.0")] #[cfg(target_has_atomic = "8")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] @@ -1500,7 +1514,9 @@ impl AtomicPtr { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_stable(feature = "const_atomic_new", since = "1.24.0")] pub const fn new(p: *mut T) -> AtomicPtr { - AtomicPtr { p: UnsafeCell::new(p) } + // SAFETY: + // `Atomic` is essentially a transparent wrapper around `T`. + unsafe { transmute(p) } } /// Creates a new `AtomicPtr` from a pointer. @@ -1586,8 +1602,11 @@ impl AtomicPtr { /// ``` #[inline] #[stable(feature = "atomic_access", since = "1.15.0")] - pub fn get_mut(&mut self) -> &mut *mut T { - self.p.get_mut() + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] + pub const fn get_mut(&mut self) -> &mut *mut T { + // SAFETY: + // `Atomic` is essentially a transparent wrapper around `T`. + unsafe { &mut *self.as_ptr() } } /// Gets atomic access to a pointer. @@ -1597,7 +1616,6 @@ impl AtomicPtr { /// # Examples /// /// ``` - /// #![feature(atomic_from_mut)] /// use std::sync::atomic::{AtomicPtr, Ordering}; /// /// let mut data = 123; @@ -1608,9 +1626,10 @@ impl AtomicPtr { /// assert_eq!(unsafe { *some_ptr }, 456); /// ``` #[inline] - #[cfg(target_has_atomic_equal_alignment = "ptr")] - #[unstable(feature = "atomic_from_mut", issue = "76314")] - pub fn from_mut(v: &mut *mut T) -> &mut Self { + #[cfg(target_has_atomic_primitive_alignment = "ptr")] + #[stable(feature = "atomic_from_mut", since = "1.98.0")] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] + pub const fn from_mut(v: &mut *mut T) -> &mut Self { let [] = [(); align_of::>() - align_of::<*mut ()>()]; // SAFETY: // - the mutable reference guarantees unique ownership. @@ -1627,7 +1646,6 @@ impl AtomicPtr { /// # Examples /// /// ```ignore-wasm - /// #![feature(atomic_from_mut)] /// use std::ptr::null_mut; /// use std::sync::atomic::{AtomicPtr, Ordering}; /// @@ -1653,8 +1671,9 @@ impl AtomicPtr { /// }); /// ``` #[inline] - #[unstable(feature = "atomic_from_mut", issue = "76314")] - pub fn get_mut_slice(this: &mut [Self]) -> &mut [*mut T] { + #[stable(feature = "atomic_from_mut", since = "1.98.0")] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] + pub const fn get_mut_slice(this: &mut [Self]) -> &mut [*mut T] { // SAFETY: the mutable reference guarantees unique ownership. unsafe { &mut *(this as *mut [Self] as *mut [*mut T]) } } @@ -1666,7 +1685,6 @@ impl AtomicPtr { /// # Examples /// /// ```ignore-wasm - /// #![feature(atomic_from_mut)] /// use std::ptr::null_mut; /// use std::sync::atomic::{AtomicPtr, Ordering}; /// @@ -1687,9 +1705,10 @@ impl AtomicPtr { /// } /// ``` #[inline] - #[cfg(target_has_atomic_equal_alignment = "ptr")] - #[unstable(feature = "atomic_from_mut", issue = "76314")] - pub fn from_mut_slice(v: &mut [*mut T]) -> &mut [Self] { + #[cfg(target_has_atomic_primitive_alignment = "ptr")] + #[stable(feature = "atomic_from_mut", since = "1.98.0")] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] + pub const fn from_mut_slice(v: &mut [*mut T]) -> &mut [Self] { // SAFETY: // - the mutable reference guarantees unique ownership. // - the alignment of `*mut T` and `Self` is the same on all platforms @@ -1715,7 +1734,9 @@ impl AtomicPtr { #[stable(feature = "atomic_access", since = "1.15.0")] #[rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0")] pub const fn into_inner(self) -> *mut T { - self.p.into_inner() + // SAFETY: + // `Atomic` is essentially a transparent wrapper around `T`. + unsafe { transmute(self) } } /// Loads a value from the pointer. @@ -1739,10 +1760,13 @@ impl AtomicPtr { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces - pub fn load(&self, order: Ordering) -> *mut T { + pub const fn load(&self, order: Ordering) -> *mut T { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_load(self.p.get(), order) } + unsafe { + atomic_load::<_, /* VOLATILE */ false>(self.as_ptr(), order) + } } /// Stores a value into the pointer. @@ -1768,12 +1792,13 @@ impl AtomicPtr { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn store(&self, ptr: *mut T, order: Ordering) { + pub const fn store(&self, ptr: *mut T, order: Ordering) { // SAFETY: data races are prevented by atomic intrinsics. unsafe { - atomic_store(self.p.get(), ptr, order); + atomic_store::<_, /* VOLATILE */ false>(self.as_ptr(), ptr, order); } } @@ -1801,12 +1826,13 @@ impl AtomicPtr { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] #[cfg(target_has_atomic = "ptr")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn swap(&self, ptr: *mut T, order: Ordering) -> *mut T { + pub const fn swap(&self, ptr: *mut T, order: Ordering) -> *mut T { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_swap(self.p.get(), ptr, order) } + unsafe { atomic_swap(self.as_ptr(), ptr, order) } } /// Stores a value into the pointer if the current value is the same as the `current` value. @@ -1930,7 +1956,7 @@ impl AtomicPtr { failure: Ordering, ) -> Result<*mut T, *mut T> { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_compare_exchange(self.p.get(), current, new, success, failure) } + unsafe { atomic_compare_exchange(self.as_ptr(), current, new, success, failure) } } /// Stores a value into the pointer if the current value is the same as the `current` value. @@ -1997,86 +2023,30 @@ impl AtomicPtr { // but we know for sure that the pointer is valid (we just got it from // an `UnsafeCell` that we have by reference) and the atomic operation // itself allows us to safely mutate the `UnsafeCell` contents. - unsafe { atomic_compare_exchange_weak(self.p.get(), current, new, success, failure) } + unsafe { atomic_compare_exchange_weak(self.as_ptr(), current, new, success, failure) } } - /// Fetches the value, and applies a function to it that returns an optional - /// new value. Returns a `Result` of `Ok(previous_value)` if the function - /// returned `Some(_)`, else `Err(previous_value)`. - /// - /// Note: This may call the function multiple times if the value has been - /// changed from other threads in the meantime, as long as the function - /// returns `Some(_)`, but the function will have been applied only once to - /// the stored value. - /// - /// `fetch_update` takes two [`Ordering`] arguments to describe the memory - /// ordering of this operation. The first describes the required ordering for - /// when the operation finally succeeds while the second describes the - /// required ordering for loads. These correspond to the success and failure - /// orderings of [`AtomicPtr::compare_exchange`] respectively. - /// - /// Using [`Acquire`] as success ordering makes the store part of this - /// operation [`Relaxed`], and using [`Release`] makes the final successful - /// load [`Relaxed`]. The (failed) load ordering can only be [`SeqCst`], - /// [`Acquire`] or [`Relaxed`]. - /// - /// **Note:** This method is only available on platforms that support atomic - /// operations on pointers. - /// - /// # Considerations - /// - /// This method is not magic; it is not provided by the hardware, and does not act like a - /// critical section or mutex. - /// - /// It is implemented on top of an atomic [compare-and-swap operation], and thus is subject to - /// the usual drawbacks of CAS operations. In particular, be careful of the [ABA problem], - /// which is a particularly common pitfall for pointers! - /// - /// [ABA Problem]: https://en.wikipedia.org/wiki/ABA_problem - /// [compare-and-swap operation]: https://en.wikipedia.org/wiki/Compare-and-swap - /// - /// # Examples - /// - /// ```rust - /// use std::sync::atomic::{AtomicPtr, Ordering}; - /// - /// let ptr: *mut _ = &mut 5; - /// let some_ptr = AtomicPtr::new(ptr); - /// - /// let new: *mut _ = &mut 10; - /// assert_eq!(some_ptr.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |_| None), Err(ptr)); - /// let result = some_ptr.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |x| { - /// if x == ptr { - /// Some(new) - /// } else { - /// None - /// } - /// }); - /// assert_eq!(result, Ok(ptr)); - /// assert_eq!(some_ptr.load(Ordering::SeqCst), new); - /// ``` + /// An alias for [`AtomicPtr::try_update`]. #[inline] #[stable(feature = "atomic_fetch_update", since = "1.53.0")] #[cfg(target_has_atomic = "ptr")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] + #[deprecated( + since = "1.99.0", + note = "renamed to `try_update` for consistency", + suggestion = "try_update" + )] pub fn fetch_update( &self, set_order: Ordering, fetch_order: Ordering, - mut f: F, + f: F, ) -> Result<*mut T, *mut T> where F: FnMut(*mut T) -> Option<*mut T>, { - let mut prev = self.load(fetch_order); - while let Some(next) = f(prev) { - match self.compare_exchange_weak(prev, next, set_order, fetch_order) { - x @ Ok(_) => return x, - Err(next_prev) => prev = next_prev, - } - } - Err(prev) + self.try_update(set_order, fetch_order, f) } /// Fetches the value, and applies a function to it that returns an optional /// new value. Returns a `Result` of `Ok(previous_value)` if the function @@ -2118,7 +2088,6 @@ impl AtomicPtr { /// # Examples /// /// ```rust - /// #![feature(atomic_try_update)] /// use std::sync::atomic::{AtomicPtr, Ordering}; /// /// let ptr: *mut _ = &mut 5; @@ -2137,7 +2106,7 @@ impl AtomicPtr { /// assert_eq!(some_ptr.load(Ordering::SeqCst), new); /// ``` #[inline] - #[unstable(feature = "atomic_try_update", issue = "135894")] + #[stable(feature = "atomic_try_update", since = "1.95.0")] #[cfg(target_has_atomic = "ptr")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] @@ -2145,11 +2114,16 @@ impl AtomicPtr { &self, set_order: Ordering, fetch_order: Ordering, - f: impl FnMut(*mut T) -> Option<*mut T>, + mut f: impl FnMut(*mut T) -> Option<*mut T>, ) -> Result<*mut T, *mut T> { - // FIXME(atomic_try_update): this is currently an unstable alias to `fetch_update`; - // when stabilizing, turn `fetch_update` into a deprecated alias to `try_update`. - self.fetch_update(set_order, fetch_order, f) + let mut prev = self.load(fetch_order); + while let Some(next) = f(prev) { + match self.compare_exchange_weak(prev, next, set_order, fetch_order) { + x @ Ok(_) => return x, + Err(next_prev) => prev = next_prev, + } + } + Err(prev) } /// Fetches the value, applies a function to it that it return a new value. @@ -2188,7 +2162,6 @@ impl AtomicPtr { /// # Examples /// /// ```rust - /// #![feature(atomic_try_update)] /// /// use std::sync::atomic::{AtomicPtr, Ordering}; /// @@ -2201,8 +2174,8 @@ impl AtomicPtr { /// assert_eq!(some_ptr.load(Ordering::SeqCst), new); /// ``` #[inline] - #[unstable(feature = "atomic_try_update", issue = "135894")] - #[cfg(target_has_atomic = "8")] + #[stable(feature = "atomic_try_update", since = "1.95.0")] + #[cfg(target_has_atomic = "ptr")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] pub fn update( @@ -2339,7 +2312,7 @@ impl AtomicPtr { #[rustc_should_not_be_called_on_const_items] pub fn fetch_byte_add(&self, val: usize, order: Ordering) -> *mut T { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_add(self.p.get(), val, order).cast() } + unsafe { atomic_add(self.as_ptr(), val, order).cast() } } /// Offsets the pointer's address by subtracting `val` *bytes*, returning the @@ -2375,7 +2348,7 @@ impl AtomicPtr { #[rustc_should_not_be_called_on_const_items] pub fn fetch_byte_sub(&self, val: usize, order: Ordering) -> *mut T { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_sub(self.p.get(), val, order).cast() } + unsafe { atomic_sub(self.as_ptr(), val, order).cast() } } /// Performs a bitwise "or" operation on the address of the current pointer, @@ -2426,7 +2399,7 @@ impl AtomicPtr { #[rustc_should_not_be_called_on_const_items] pub fn fetch_or(&self, val: usize, order: Ordering) -> *mut T { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_or(self.p.get(), val, order).cast() } + unsafe { atomic_or(self.as_ptr(), val, order).cast() } } /// Performs a bitwise "and" operation on the address of the current @@ -2476,7 +2449,7 @@ impl AtomicPtr { #[rustc_should_not_be_called_on_const_items] pub fn fetch_and(&self, val: usize, order: Ordering) -> *mut T { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_and(self.p.get(), val, order).cast() } + unsafe { atomic_and(self.as_ptr(), val, order).cast() } } /// Performs a bitwise "xor" operation on the address of the current @@ -2524,7 +2497,7 @@ impl AtomicPtr { #[rustc_should_not_be_called_on_const_items] pub fn fetch_xor(&self, val: usize, order: Ordering) -> *mut T { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_xor(self.p.get(), val, order).cast() } + unsafe { atomic_xor(self.as_ptr(), val, order).cast() } } /// Returns a mutable pointer to the underlying pointer. @@ -2563,14 +2536,14 @@ impl AtomicPtr { #[rustc_const_stable(feature = "atomic_as_ptr", since = "1.70.0")] #[rustc_never_returns_null_ptr] pub const fn as_ptr(&self) -> *mut *mut T { - self.p.get() + self.v.get().cast() } } #[cfg(target_has_atomic_load_store = "8")] #[stable(feature = "atomic_bool_from", since = "1.24.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for AtomicBool { +const impl From for AtomicBool { /// Converts a `bool` into an `AtomicBool`. /// /// # Examples @@ -2589,7 +2562,7 @@ impl const From for AtomicBool { #[cfg(target_has_atomic_load_store = "ptr")] #[stable(feature = "atomic_from", since = "1.23.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From<*mut T> for AtomicPtr { +const impl From<*mut T> for AtomicPtr { /// Converts a `*mut T` into an `AtomicPtr`. #[inline] fn from(p: *mut T) -> Self { @@ -2606,7 +2579,8 @@ macro_rules! if_8_bit { #[cfg(target_has_atomic_load_store)] macro_rules! atomic_int { - ($cfg_cas:meta, + ($cfg_base:meta, + $cfg_cas:meta, $cfg_align:meta, $stable:meta, $stable_cxchg:meta, @@ -2616,7 +2590,6 @@ macro_rules! atomic_int { $stable_nand:meta, $const_stable_new:meta, $const_stable_into_inner:meta, - $diagnostic_item:meta, $s_int_type:literal, $extra_feature:expr, $min_fn:ident, $max_fn:ident, @@ -2653,11 +2626,7 @@ macro_rules! atomic_int { /// /// [module-level documentation]: crate::sync::atomic #[$stable] - #[$diagnostic_item] - #[repr(C, align($align))] - pub struct $atomic_type { - v: UnsafeCell<$int_type>, - } + pub type $atomic_type = Atomic<$int_type>; #[$stable] impl Default for $atomic_type { @@ -2669,7 +2638,7 @@ macro_rules! atomic_int { #[$stable_from] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] - impl const From<$int_type> for $atomic_type { + const impl From<$int_type> for $atomic_type { #[doc = concat!("Converts an `", stringify!($int_type), "` into an `", stringify!($atomic_type), "`.")] #[inline] fn from(v: $int_type) -> Self { Self::new(v) } @@ -2682,16 +2651,13 @@ macro_rules! atomic_int { } } - // Send is implicitly implemented. - #[$stable] - unsafe impl Sync for $atomic_type {} - impl $atomic_type { /// Creates a new atomic integer. /// /// # Examples /// - /// ``` + #[cfg_attr($cfg_base, doc = "```")] + #[cfg_attr(not($cfg_base), doc = "```compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::", stringify!($atomic_type), ";")] /// #[doc = concat!("let atomic_forty_two = ", stringify!($atomic_type), "::new(42);")] @@ -2701,14 +2667,17 @@ macro_rules! atomic_int { #[$const_stable_new] #[must_use] pub const fn new(v: $int_type) -> Self { - Self {v: UnsafeCell::new(v)} + // SAFETY: + // `Atomic` is essentially a transparent wrapper around `T`. + unsafe { transmute(v) } } /// Creates a new reference to an atomic integer from a pointer. /// /// # Examples /// - /// ``` + #[cfg_attr($cfg_base, doc = "```rust")] + #[cfg_attr(not($cfg_base), doc = "```rust,compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::{self, ", stringify!($atomic_type), "};")] /// /// // Get a pointer to an allocated value @@ -2763,7 +2732,6 @@ macro_rules! atomic_int { unsafe { &*ptr.cast() } } - /// Returns a mutable reference to the underlying integer. /// /// This is safe because the mutable reference guarantees that no other threads are @@ -2771,7 +2739,8 @@ macro_rules! atomic_int { /// /// # Examples /// - /// ``` + #[cfg_attr($cfg_base, doc = "```")] + #[cfg_attr(not($cfg_base), doc = "```compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let mut some_var = ", stringify!($atomic_type), "::new(10);")] @@ -2781,8 +2750,11 @@ macro_rules! atomic_int { /// ``` #[inline] #[$stable_access] - pub fn get_mut(&mut self) -> &mut $int_type { - self.v.get_mut() + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] + pub const fn get_mut(&mut self) -> &mut $int_type { + // SAFETY: + // `Atomic` is essentially a transparent wrapper around `T`. + unsafe { &mut *self.as_ptr() } } #[doc = concat!("Get atomic access to a `&mut ", stringify!($int_type), "`.")] @@ -2797,8 +2769,8 @@ macro_rules! atomic_int { /// /// # Examples /// - /// ``` - /// #![feature(atomic_from_mut)] + #[cfg_attr($cfg_align, doc = "```rust")] + #[cfg_attr(not($cfg_align), doc = "```rust,compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// /// let mut some_int = 123; @@ -2808,9 +2780,10 @@ macro_rules! atomic_int { /// ``` /// #[inline] - #[$cfg_align] - #[unstable(feature = "atomic_from_mut", issue = "76314")] - pub fn from_mut(v: &mut $int_type) -> &mut Self { + #[cfg(any($cfg_align, doc))] + #[stable(feature = "atomic_from_mut", since = "1.98.0")] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] + pub const fn from_mut(v: &mut $int_type) -> &mut Self { let [] = [(); align_of::() - align_of::<$int_type>()]; // SAFETY: // - the mutable reference guarantees unique ownership. @@ -2826,8 +2799,8 @@ macro_rules! atomic_int { /// /// # Examples /// - /// ```ignore-wasm - /// #![feature(atomic_from_mut)] + #[cfg_attr($cfg_base, doc = "```ignore-wasm")] + #[cfg_attr(not($cfg_base), doc = "```ignore-wasm,compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let mut some_ints = [const { ", stringify!($atomic_type), "::new(0) }; 10];")] @@ -2849,8 +2822,9 @@ macro_rules! atomic_int { /// }); /// ``` #[inline] - #[unstable(feature = "atomic_from_mut", issue = "76314")] - pub fn get_mut_slice(this: &mut [Self]) -> &mut [$int_type] { + #[stable(feature = "atomic_from_mut", since = "1.98.0")] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] + pub const fn get_mut_slice(this: &mut [Self]) -> &mut [$int_type] { // SAFETY: the mutable reference guarantees unique ownership. unsafe { &mut *(this as *mut [Self] as *mut [$int_type]) } } @@ -2867,8 +2841,8 @@ macro_rules! atomic_int { /// /// # Examples /// - /// ```ignore-wasm - /// #![feature(atomic_from_mut)] + #[cfg_attr($cfg_align, doc = "```ignore-wasm")] + #[cfg_attr(not($cfg_align), doc = "```ignore-wasm,compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// /// let mut some_ints = [0; 10]; @@ -2883,9 +2857,10 @@ macro_rules! atomic_int { /// } /// ``` #[inline] - #[$cfg_align] - #[unstable(feature = "atomic_from_mut", issue = "76314")] - pub fn from_mut_slice(v: &mut [$int_type]) -> &mut [Self] { + #[cfg(any($cfg_align, doc))] + #[stable(feature = "atomic_from_mut", since = "1.98.0")] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] + pub const fn from_mut_slice(v: &mut [$int_type]) -> &mut [Self] { let [] = [(); align_of::() - align_of::<$int_type>()]; // SAFETY: // - the mutable reference guarantees unique ownership. @@ -2901,7 +2876,8 @@ macro_rules! atomic_int { /// /// # Examples /// - /// ``` + #[cfg_attr($cfg_base, doc = "```")] + #[cfg_attr(not($cfg_base), doc = "```compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::", stringify!($atomic_type), ";")] /// #[doc = concat!("let some_var = ", stringify!($atomic_type), "::new(5);")] @@ -2911,7 +2887,9 @@ macro_rules! atomic_int { #[$stable_access] #[$const_stable_into_inner] pub const fn into_inner(self) -> $int_type { - self.v.into_inner() + // SAFETY: + // `Atomic` is essentially a transparent wrapper around `T`. + unsafe { transmute(self) } } /// Loads a value from the atomic integer. @@ -2925,7 +2903,8 @@ macro_rules! atomic_int { /// /// # Examples /// - /// ``` + #[cfg_attr($cfg_base, doc = "```")] + #[cfg_attr(not($cfg_base), doc = "```compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let some_var = ", stringify!($atomic_type), "::new(5);")] @@ -2934,10 +2913,11 @@ macro_rules! atomic_int { /// ``` #[inline] #[$stable] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces - pub fn load(&self, order: Ordering) -> $int_type { + pub const fn load(&self, order: Ordering) -> $int_type { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_load(self.v.get(), order) } + unsafe { atomic_load::<_, /* VOLATILE */ false>(self.as_ptr(), order) } } /// Stores a value into the atomic integer. @@ -2951,7 +2931,8 @@ macro_rules! atomic_int { /// /// # Examples /// - /// ``` + #[cfg_attr($cfg_base, doc = "```")] + #[cfg_attr(not($cfg_base), doc = "```compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let some_var = ", stringify!($atomic_type), "::new(5);")] @@ -2961,11 +2942,12 @@ macro_rules! atomic_int { /// ``` #[inline] #[$stable] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn store(&self, val: $int_type, order: Ordering) { + pub const fn store(&self, val: $int_type, order: Ordering) { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_store(self.v.get(), val, order); } + unsafe { atomic_store::<_, /* VOLATILE */ false>(self.as_ptr(), val, order); } } /// Stores a value into the atomic integer, returning the previous value. @@ -2980,7 +2962,8 @@ macro_rules! atomic_int { /// /// # Examples /// - /// ``` + #[cfg_attr($cfg_cas, doc = "```")] + #[cfg_attr(not($cfg_cas), doc = "```compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let some_var = ", stringify!($atomic_type), "::new(5);")] @@ -2989,12 +2972,13 @@ macro_rules! atomic_int { /// ``` #[inline] #[$stable] - #[$cfg_cas] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] + #[cfg(any($cfg_cas, doc))] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn swap(&self, val: $int_type, order: Ordering) -> $int_type { + pub const fn swap(&self, val: $int_type, order: Ordering) -> $int_type { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_swap(self.v.get(), val, order) } + unsafe { atomic_swap(self.as_ptr(), val, order) } } /// Stores a value into the atomic integer if the current value is the same as @@ -3037,7 +3021,8 @@ macro_rules! atomic_int { /// /// # Examples /// - /// ``` + #[cfg_attr($cfg_cas, doc = "```")] + #[cfg_attr(not($cfg_cas), doc = "```compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let some_var = ", stringify!($atomic_type), "::new(5);")] @@ -3050,14 +3035,15 @@ macro_rules! atomic_int { /// ``` #[inline] #[$stable] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] #[deprecated( since = "1.50.0", note = "Use `compare_exchange` or `compare_exchange_weak` instead") ] - #[$cfg_cas] + #[cfg(any($cfg_cas, doc))] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn compare_and_swap(&self, + pub const fn compare_and_swap(&self, current: $int_type, new: $int_type, order: Ordering) -> $int_type { @@ -3090,7 +3076,8 @@ macro_rules! atomic_int { /// /// # Examples /// - /// ``` + #[cfg_attr($cfg_cas, doc = "```")] + #[cfg_attr(not($cfg_cas), doc = "```compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let some_var = ", stringify!($atomic_type), "::new(5);")] @@ -3123,16 +3110,17 @@ macro_rules! atomic_int { /// [compare-and-swap operation]: https://en.wikipedia.org/wiki/Compare-and-swap #[inline] #[$stable_cxchg] - #[$cfg_cas] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] + #[cfg(any($cfg_cas, doc))] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn compare_exchange(&self, + pub const fn compare_exchange(&self, current: $int_type, new: $int_type, success: Ordering, failure: Ordering) -> Result<$int_type, $int_type> { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_compare_exchange(self.v.get(), current, new, success, failure) } + unsafe { atomic_compare_exchange(self.as_ptr(), current, new, success, failure) } } /// Stores a value into the atomic integer if the current value is the same as @@ -3157,7 +3145,8 @@ macro_rules! atomic_int { /// /// # Examples /// - /// ``` + #[cfg_attr($cfg_cas, doc = "```")] + #[cfg_attr(not($cfg_cas), doc = "```compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let val = ", stringify!($atomic_type), "::new(4);")] @@ -3187,17 +3176,18 @@ macro_rules! atomic_int { /// [compare-and-swap operation]: https://en.wikipedia.org/wiki/Compare-and-swap #[inline] #[$stable_cxchg] - #[$cfg_cas] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] + #[cfg(any($cfg_cas, doc))] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn compare_exchange_weak(&self, + pub const fn compare_exchange_weak(&self, current: $int_type, new: $int_type, success: Ordering, failure: Ordering) -> Result<$int_type, $int_type> { // SAFETY: data races are prevented by atomic intrinsics. unsafe { - atomic_compare_exchange_weak(self.v.get(), current, new, success, failure) + atomic_compare_exchange_weak(self.as_ptr(), current, new, success, failure) } } @@ -3215,7 +3205,8 @@ macro_rules! atomic_int { /// /// # Examples /// - /// ``` + #[cfg_attr($cfg_cas, doc = "```")] + #[cfg_attr(not($cfg_cas), doc = "```compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let foo = ", stringify!($atomic_type), "::new(0);")] @@ -3224,12 +3215,13 @@ macro_rules! atomic_int { /// ``` #[inline] #[$stable] - #[$cfg_cas] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] + #[cfg(any($cfg_cas, doc))] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn fetch_add(&self, val: $int_type, order: Ordering) -> $int_type { + pub const fn fetch_add(&self, val: $int_type, order: Ordering) -> $int_type { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_add(self.v.get(), val, order) } + unsafe { atomic_add(self.as_ptr(), val, order) } } /// Subtracts from the current value, returning the previous value. @@ -3246,7 +3238,8 @@ macro_rules! atomic_int { /// /// # Examples /// - /// ``` + #[cfg_attr($cfg_cas, doc = "```")] + #[cfg_attr(not($cfg_cas), doc = "```compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let foo = ", stringify!($atomic_type), "::new(20);")] @@ -3255,12 +3248,13 @@ macro_rules! atomic_int { /// ``` #[inline] #[$stable] - #[$cfg_cas] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] + #[cfg(any($cfg_cas, doc))] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn fetch_sub(&self, val: $int_type, order: Ordering) -> $int_type { + pub const fn fetch_sub(&self, val: $int_type, order: Ordering) -> $int_type { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_sub(self.v.get(), val, order) } + unsafe { atomic_sub(self.as_ptr(), val, order) } } /// Bitwise "and" with the current value. @@ -3280,7 +3274,8 @@ macro_rules! atomic_int { /// /// # Examples /// - /// ``` + #[cfg_attr($cfg_cas, doc = "```")] + #[cfg_attr(not($cfg_cas), doc = "```compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let foo = ", stringify!($atomic_type), "::new(0b101101);")] @@ -3289,12 +3284,13 @@ macro_rules! atomic_int { /// ``` #[inline] #[$stable] - #[$cfg_cas] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] + #[cfg(any($cfg_cas, doc))] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn fetch_and(&self, val: $int_type, order: Ordering) -> $int_type { + pub const fn fetch_and(&self, val: $int_type, order: Ordering) -> $int_type { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_and(self.v.get(), val, order) } + unsafe { atomic_and(self.as_ptr(), val, order) } } /// Bitwise "nand" with the current value. @@ -3314,7 +3310,8 @@ macro_rules! atomic_int { /// /// # Examples /// - /// ``` + #[cfg_attr($cfg_cas, doc = "```")] + #[cfg_attr(not($cfg_cas), doc = "```compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let foo = ", stringify!($atomic_type), "::new(0x13);")] @@ -3323,12 +3320,13 @@ macro_rules! atomic_int { /// ``` #[inline] #[$stable_nand] - #[$cfg_cas] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] + #[cfg(any($cfg_cas, doc))] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn fetch_nand(&self, val: $int_type, order: Ordering) -> $int_type { + pub const fn fetch_nand(&self, val: $int_type, order: Ordering) -> $int_type { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_nand(self.v.get(), val, order) } + unsafe { atomic_nand(self.as_ptr(), val, order) } } /// Bitwise "or" with the current value. @@ -3348,7 +3346,8 @@ macro_rules! atomic_int { /// /// # Examples /// - /// ``` + #[cfg_attr($cfg_cas, doc = "```")] + #[cfg_attr(not($cfg_cas), doc = "```compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let foo = ", stringify!($atomic_type), "::new(0b101101);")] @@ -3357,12 +3356,13 @@ macro_rules! atomic_int { /// ``` #[inline] #[$stable] - #[$cfg_cas] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] + #[cfg(any($cfg_cas, doc))] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn fetch_or(&self, val: $int_type, order: Ordering) -> $int_type { + pub const fn fetch_or(&self, val: $int_type, order: Ordering) -> $int_type { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_or(self.v.get(), val, order) } + unsafe { atomic_or(self.as_ptr(), val, order) } } /// Bitwise "xor" with the current value. @@ -3382,7 +3382,8 @@ macro_rules! atomic_int { /// /// # Examples /// - /// ``` + #[cfg_attr($cfg_cas, doc = "```")] + #[cfg_attr(not($cfg_cas), doc = "```compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let foo = ", stringify!($atomic_type), "::new(0b101101);")] @@ -3391,77 +3392,34 @@ macro_rules! atomic_int { /// ``` #[inline] #[$stable] - #[$cfg_cas] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] + #[cfg(any($cfg_cas, doc))] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn fetch_xor(&self, val: $int_type, order: Ordering) -> $int_type { + pub const fn fetch_xor(&self, val: $int_type, order: Ordering) -> $int_type { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_xor(self.v.get(), val, order) } + unsafe { atomic_xor(self.as_ptr(), val, order) } } - /// Fetches the value, and applies a function to it that returns an optional - /// new value. Returns a `Result` of `Ok(previous_value)` if the function returned `Some(_)`, else - /// `Err(previous_value)`. - /// - /// Note: This may call the function multiple times if the value has been changed from other threads in - /// the meantime, as long as the function returns `Some(_)`, but the function will have been applied - /// only once to the stored value. - /// - /// `fetch_update` takes two [`Ordering`] arguments to describe the memory ordering of this operation. - /// The first describes the required ordering for when the operation finally succeeds while the second - /// describes the required ordering for loads. These correspond to the success and failure orderings of - #[doc = concat!("[`", stringify!($atomic_type), "::compare_exchange`]")] - /// respectively. - /// - /// Using [`Acquire`] as success ordering makes the store part - /// of this operation [`Relaxed`], and using [`Release`] makes the final successful load - /// [`Relaxed`]. The (failed) load ordering can only be [`SeqCst`], [`Acquire`] or [`Relaxed`]. - /// - /// **Note**: This method is only available on platforms that support atomic operations on - #[doc = concat!("[`", $s_int_type, "`].")] - /// - /// # Considerations - /// - /// This method is not magic; it is not provided by the hardware, and does not act like a - /// critical section or mutex. - /// - /// It is implemented on top of an atomic [compare-and-swap operation], and thus is subject to - /// the usual drawbacks of CAS operations. In particular, be careful of the [ABA problem] - /// if this atomic integer is an index or more generally if knowledge of only the *bitwise value* - /// of the atomic is not in and of itself sufficient to ensure any required preconditions. - /// - /// [ABA Problem]: https://en.wikipedia.org/wiki/ABA_problem - /// [compare-and-swap operation]: https://en.wikipedia.org/wiki/Compare-and-swap - /// - /// # Examples - /// - /// ```rust - #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] - /// - #[doc = concat!("let x = ", stringify!($atomic_type), "::new(7);")] - /// assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |_| None), Err(7)); - /// assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |x| Some(x + 1)), Ok(7)); - /// assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |x| Some(x + 1)), Ok(8)); - /// assert_eq!(x.load(Ordering::SeqCst), 9); - /// ``` + /// An alias for + #[doc = concat!("[`", stringify!($atomic_type), "::try_update`]")] + /// . #[inline] #[stable(feature = "no_more_cas", since = "1.45.0")] - #[$cfg_cas] + #[cfg(any($cfg_cas, doc))] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] + #[deprecated( + since = "1.99.0", + note = "renamed to `try_update` for consistency", + suggestion = "try_update" + )] pub fn fetch_update(&self, set_order: Ordering, fetch_order: Ordering, - mut f: F) -> Result<$int_type, $int_type> + f: F) -> Result<$int_type, $int_type> where F: FnMut($int_type) -> Option<$int_type> { - let mut prev = self.load(fetch_order); - while let Some(next) = f(prev) { - match self.compare_exchange_weak(prev, next, set_order, fetch_order) { - x @ Ok(_) => return x, - Err(next_prev) => prev = next_prev - } - } - Err(prev) + self.try_update(set_order, fetch_order, f) } /// Fetches the value, and applies a function to it that returns an optional @@ -3502,8 +3460,8 @@ macro_rules! atomic_int { /// /// # Examples /// - /// ```rust - /// #![feature(atomic_try_update)] + #[cfg_attr($cfg_cas, doc = "```rust")] + #[cfg_attr(not($cfg_cas), doc = "```rust,compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let x = ", stringify!($atomic_type), "::new(7);")] @@ -3513,19 +3471,24 @@ macro_rules! atomic_int { /// assert_eq!(x.load(Ordering::SeqCst), 9); /// ``` #[inline] - #[unstable(feature = "atomic_try_update", issue = "135894")] - #[$cfg_cas] + #[stable(feature = "atomic_try_update", since = "1.95.0")] + #[cfg(any($cfg_cas, doc))] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] pub fn try_update( &self, set_order: Ordering, fetch_order: Ordering, - f: impl FnMut($int_type) -> Option<$int_type>, + mut f: impl FnMut($int_type) -> Option<$int_type>, ) -> Result<$int_type, $int_type> { - // FIXME(atomic_try_update): this is currently an unstable alias to `fetch_update`; - // when stabilizing, turn `fetch_update` into a deprecated alias to `try_update`. - self.fetch_update(set_order, fetch_order, f) + let mut prev = self.load(fetch_order); + while let Some(next) = f(prev) { + match self.compare_exchange_weak(prev, next, set_order, fetch_order) { + x @ Ok(_) => return x, + Err(next_prev) => prev = next_prev + } + } + Err(prev) } /// Fetches the value, applies a function to it that it return a new value. @@ -3565,8 +3528,8 @@ macro_rules! atomic_int { /// /// # Examples /// - /// ```rust - /// #![feature(atomic_try_update)] + #[cfg_attr($cfg_cas, doc = "```rust")] + #[cfg_attr(not($cfg_cas), doc = "```rust,compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let x = ", stringify!($atomic_type), "::new(7);")] @@ -3575,8 +3538,8 @@ macro_rules! atomic_int { /// assert_eq!(x.load(Ordering::SeqCst), 9); /// ``` #[inline] - #[unstable(feature = "atomic_try_update", issue = "135894")] - #[$cfg_cas] + #[stable(feature = "atomic_try_update", since = "1.95.0")] + #[cfg(any($cfg_cas, doc))] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] pub fn update( @@ -3611,7 +3574,8 @@ macro_rules! atomic_int { /// /// # Examples /// - /// ``` + #[cfg_attr($cfg_cas, doc = "```")] + #[cfg_attr(not($cfg_cas), doc = "```compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let foo = ", stringify!($atomic_type), "::new(23);")] @@ -3621,7 +3585,8 @@ macro_rules! atomic_int { /// /// If you want to obtain the maximum value in one step, you can use the following: /// - /// ``` + #[cfg_attr($cfg_cas, doc = "```")] + #[cfg_attr(not($cfg_cas), doc = "```compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let foo = ", stringify!($atomic_type), "::new(23);")] @@ -3631,12 +3596,13 @@ macro_rules! atomic_int { /// ``` #[inline] #[stable(feature = "atomic_min_max", since = "1.45.0")] - #[$cfg_cas] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] + #[cfg(any($cfg_cas, doc))] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn fetch_max(&self, val: $int_type, order: Ordering) -> $int_type { + pub const fn fetch_max(&self, val: $int_type, order: Ordering) -> $int_type { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { $max_fn(self.v.get(), val, order) } + unsafe { $max_fn(self.as_ptr(), val, order) } } /// Minimum with the current value. @@ -3656,7 +3622,8 @@ macro_rules! atomic_int { /// /// # Examples /// - /// ``` + #[cfg_attr($cfg_cas, doc = "```")] + #[cfg_attr(not($cfg_cas), doc = "```compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let foo = ", stringify!($atomic_type), "::new(23);")] @@ -3668,7 +3635,8 @@ macro_rules! atomic_int { /// /// If you want to obtain the minimum value in one step, you can use the following: /// - /// ``` + #[cfg_attr($cfg_cas, doc = "```")] + #[cfg_attr(not($cfg_cas), doc = "```compile_fail")] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let foo = ", stringify!($atomic_type), "::new(23);")] @@ -3678,12 +3646,13 @@ macro_rules! atomic_int { /// ``` #[inline] #[stable(feature = "atomic_min_max", since = "1.45.0")] - #[$cfg_cas] + #[rustc_const_unstable(feature = "const_atomic", issue = "160078")] + #[cfg(any($cfg_cas, doc))] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] - pub fn fetch_min(&self, val: $int_type, order: Ordering) -> $int_type { + pub const fn fetch_min(&self, val: $int_type, order: Ordering) -> $int_type { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { $min_fn(self.v.get(), val, order) } + unsafe { $min_fn(self.as_ptr(), val, order) } } /// Returns a mutable pointer to the underlying integer. @@ -3723,7 +3692,7 @@ macro_rules! atomic_int { #[rustc_const_stable(feature = "atomic_as_ptr", since = "1.70.0")] #[rustc_never_returns_null_ptr] pub const fn as_ptr(&self) -> *mut $int_type { - self.v.get() + self.v.get().cast() } } } @@ -3731,8 +3700,9 @@ macro_rules! atomic_int { #[cfg(target_has_atomic_load_store = "8")] atomic_int! { - cfg(target_has_atomic = "8"), - cfg(target_has_atomic_equal_alignment = "8"), + target_has_atomic_load_store = "8", + target_has_atomic = "8", + target_has_atomic_primitive_alignment = "8", stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), @@ -3741,7 +3711,6 @@ atomic_int! { stable(feature = "integer_atomics_stable", since = "1.34.0"), rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"), rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0"), - rustc_diagnostic_item = "AtomicI8", "i8", "", atomic_min, atomic_max, @@ -3750,8 +3719,9 @@ atomic_int! { } #[cfg(target_has_atomic_load_store = "8")] atomic_int! { - cfg(target_has_atomic = "8"), - cfg(target_has_atomic_equal_alignment = "8"), + target_has_atomic_load_store = "8", + target_has_atomic = "8", + target_has_atomic_primitive_alignment = "8", stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), @@ -3760,7 +3730,6 @@ atomic_int! { stable(feature = "integer_atomics_stable", since = "1.34.0"), rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"), rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0"), - rustc_diagnostic_item = "AtomicU8", "u8", "", atomic_umin, atomic_umax, @@ -3769,8 +3738,9 @@ atomic_int! { } #[cfg(target_has_atomic_load_store = "16")] atomic_int! { - cfg(target_has_atomic = "16"), - cfg(target_has_atomic_equal_alignment = "16"), + target_has_atomic_load_store = "16", + target_has_atomic = "16", + target_has_atomic_primitive_alignment = "16", stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), @@ -3779,7 +3749,6 @@ atomic_int! { stable(feature = "integer_atomics_stable", since = "1.34.0"), rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"), rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0"), - rustc_diagnostic_item = "AtomicI16", "i16", "", atomic_min, atomic_max, @@ -3788,8 +3757,9 @@ atomic_int! { } #[cfg(target_has_atomic_load_store = "16")] atomic_int! { - cfg(target_has_atomic = "16"), - cfg(target_has_atomic_equal_alignment = "16"), + target_has_atomic_load_store = "16", + target_has_atomic = "16", + target_has_atomic_primitive_alignment = "16", stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), @@ -3798,7 +3768,6 @@ atomic_int! { stable(feature = "integer_atomics_stable", since = "1.34.0"), rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"), rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0"), - rustc_diagnostic_item = "AtomicU16", "u16", "", atomic_umin, atomic_umax, @@ -3807,8 +3776,9 @@ atomic_int! { } #[cfg(target_has_atomic_load_store = "32")] atomic_int! { - cfg(target_has_atomic = "32"), - cfg(target_has_atomic_equal_alignment = "32"), + target_has_atomic_load_store = "32", + target_has_atomic = "32", + target_has_atomic_primitive_alignment = "32", stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), @@ -3817,7 +3787,6 @@ atomic_int! { stable(feature = "integer_atomics_stable", since = "1.34.0"), rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"), rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0"), - rustc_diagnostic_item = "AtomicI32", "i32", "", atomic_min, atomic_max, @@ -3826,8 +3795,9 @@ atomic_int! { } #[cfg(target_has_atomic_load_store = "32")] atomic_int! { - cfg(target_has_atomic = "32"), - cfg(target_has_atomic_equal_alignment = "32"), + target_has_atomic_load_store = "32", + target_has_atomic = "32", + target_has_atomic_primitive_alignment = "32", stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), @@ -3836,7 +3806,6 @@ atomic_int! { stable(feature = "integer_atomics_stable", since = "1.34.0"), rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"), rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0"), - rustc_diagnostic_item = "AtomicU32", "u32", "", atomic_umin, atomic_umax, @@ -3845,8 +3814,9 @@ atomic_int! { } #[cfg(target_has_atomic_load_store = "64")] atomic_int! { - cfg(target_has_atomic = "64"), - cfg(target_has_atomic_equal_alignment = "64"), + target_has_atomic_load_store = "64", + target_has_atomic = "64", + target_has_atomic_primitive_alignment = "64", stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), @@ -3855,7 +3825,6 @@ atomic_int! { stable(feature = "integer_atomics_stable", since = "1.34.0"), rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"), rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0"), - rustc_diagnostic_item = "AtomicI64", "i64", "", atomic_min, atomic_max, @@ -3864,8 +3833,9 @@ atomic_int! { } #[cfg(target_has_atomic_load_store = "64")] atomic_int! { - cfg(target_has_atomic = "64"), - cfg(target_has_atomic_equal_alignment = "64"), + target_has_atomic_load_store = "64", + target_has_atomic = "64", + target_has_atomic_primitive_alignment = "64", stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), @@ -3874,17 +3844,17 @@ atomic_int! { stable(feature = "integer_atomics_stable", since = "1.34.0"), rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"), rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0"), - rustc_diagnostic_item = "AtomicU64", "u64", "", atomic_umin, atomic_umax, 8, u64 AtomicU64 } -#[cfg(target_has_atomic_load_store = "128")] +#[cfg(any(target_has_atomic_load_store = "128", doc))] atomic_int! { - cfg(target_has_atomic = "128"), - cfg(target_has_atomic_equal_alignment = "128"), + target_has_atomic_load_store = "128", + target_has_atomic = "128", + target_has_atomic_primitive_alignment = "128", unstable(feature = "integer_atomics", issue = "99069"), unstable(feature = "integer_atomics", issue = "99069"), unstable(feature = "integer_atomics", issue = "99069"), @@ -3893,17 +3863,17 @@ atomic_int! { unstable(feature = "integer_atomics", issue = "99069"), rustc_const_unstable(feature = "integer_atomics", issue = "99069"), rustc_const_unstable(feature = "integer_atomics", issue = "99069"), - rustc_diagnostic_item = "AtomicI128", "i128", "#![feature(integer_atomics)]\n\n", atomic_min, atomic_max, 16, i128 AtomicI128 } -#[cfg(target_has_atomic_load_store = "128")] +#[cfg(any(target_has_atomic_load_store = "128", doc))] atomic_int! { - cfg(target_has_atomic = "128"), - cfg(target_has_atomic_equal_alignment = "128"), + target_has_atomic_load_store = "128", + target_has_atomic = "128", + target_has_atomic_primitive_alignment = "128", unstable(feature = "integer_atomics", issue = "99069"), unstable(feature = "integer_atomics", issue = "99069"), unstable(feature = "integer_atomics", issue = "99069"), @@ -3912,7 +3882,6 @@ atomic_int! { unstable(feature = "integer_atomics", issue = "99069"), rustc_const_unstable(feature = "integer_atomics", issue = "99069"), rustc_const_unstable(feature = "integer_atomics", issue = "99069"), - rustc_diagnostic_item = "AtomicU128", "u128", "#![feature(integer_atomics)]\n\n", atomic_umin, atomic_umax, @@ -3925,8 +3894,9 @@ macro_rules! atomic_int_ptr_sized { ( $($target_pointer_width:literal $align:literal)* ) => { $( #[cfg(target_pointer_width = $target_pointer_width)] atomic_int! { - cfg(target_has_atomic = "ptr"), - cfg(target_has_atomic_equal_alignment = "ptr"), + target_has_atomic_load_store = "ptr", + target_has_atomic = "ptr", + target_has_atomic_primitive_alignment = "ptr", stable(feature = "rust1", since = "1.0.0"), stable(feature = "extended_compare_and_swap", since = "1.10.0"), stable(feature = "atomic_debug", since = "1.3.0"), @@ -3935,7 +3905,6 @@ macro_rules! atomic_int_ptr_sized { stable(feature = "atomic_nand", since = "1.27.0"), rustc_const_stable(feature = "const_ptr_sized_atomics", since = "1.24.0"), rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0"), - rustc_diagnostic_item = "AtomicIsize", "isize", "", atomic_min, atomic_max, @@ -3944,8 +3913,9 @@ macro_rules! atomic_int_ptr_sized { } #[cfg(target_pointer_width = $target_pointer_width)] atomic_int! { - cfg(target_has_atomic = "ptr"), - cfg(target_has_atomic_equal_alignment = "ptr"), + target_has_atomic_load_store = "ptr", + target_has_atomic = "ptr", + target_has_atomic_primitive_alignment = "ptr", stable(feature = "rust1", since = "1.0.0"), stable(feature = "extended_compare_and_swap", since = "1.10.0"), stable(feature = "atomic_debug", since = "1.3.0"), @@ -3954,7 +3924,6 @@ macro_rules! atomic_int_ptr_sized { stable(feature = "atomic_nand", since = "1.27.0"), rustc_const_stable(feature = "const_ptr_sized_atomics", since = "1.24.0"), rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0"), - rustc_diagnostic_item = "AtomicUsize", "usize", "", atomic_umin, atomic_umax, @@ -3993,7 +3962,7 @@ atomic_int_ptr_sized! { #[inline] #[cfg(target_has_atomic)] -fn strongest_failure_ordering(order: Ordering) -> Ordering { +const fn strongest_failure_ordering(order: Ordering) -> Ordering { match order { Release => Relaxed, Relaxed => Relaxed, @@ -4005,13 +3974,14 @@ fn strongest_failure_ordering(order: Ordering) -> Ordering { #[inline] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces -unsafe fn atomic_store(dst: *mut T, val: T, order: Ordering) { +#[rustc_const_unstable(feature = "const_atomic", issue = "160078")] +const unsafe fn atomic_store(dst: *mut T, val: T, order: Ordering) { // SAFETY: the caller must uphold the safety contract for `atomic_store`. unsafe { match order { - Relaxed => intrinsics::atomic_store::(dst, val), - Release => intrinsics::atomic_store::(dst, val), - SeqCst => intrinsics::atomic_store::(dst, val), + Relaxed => intrinsics::atomic_store::(dst, val), + Release => intrinsics::atomic_store::(dst, val), + SeqCst => intrinsics::atomic_store::(dst, val), Acquire => panic!("there is no such thing as an acquire store"), AcqRel => panic!("there is no such thing as an acquire-release store"), } @@ -4020,13 +3990,14 @@ unsafe fn atomic_store(dst: *mut T, val: T, order: Ordering) { #[inline] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces -unsafe fn atomic_load(dst: *const T, order: Ordering) -> T { +#[rustc_const_unstable(feature = "const_atomic", issue = "160078")] +const unsafe fn atomic_load(dst: *const T, order: Ordering) -> T { // SAFETY: the caller must uphold the safety contract for `atomic_load`. unsafe { match order { - Relaxed => intrinsics::atomic_load::(dst), - Acquire => intrinsics::atomic_load::(dst), - SeqCst => intrinsics::atomic_load::(dst), + Relaxed => intrinsics::atomic_load::(dst), + Acquire => intrinsics::atomic_load::(dst), + SeqCst => intrinsics::atomic_load::(dst), Release => panic!("there is no such thing as a release load"), AcqRel => panic!("there is no such thing as an acquire-release load"), } @@ -4036,7 +4007,8 @@ unsafe fn atomic_load(dst: *const T, order: Ordering) -> T { #[inline] #[cfg(target_has_atomic)] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces -unsafe fn atomic_swap(dst: *mut T, val: T, order: Ordering) -> T { +#[rustc_const_unstable(feature = "const_atomic", issue = "160078")] +const unsafe fn atomic_swap(dst: *mut T, val: T, order: Ordering) -> T { // SAFETY: the caller must uphold the safety contract for `atomic_swap`. unsafe { match order { @@ -4053,7 +4025,8 @@ unsafe fn atomic_swap(dst: *mut T, val: T, order: Ordering) -> T { #[inline] #[cfg(target_has_atomic)] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces -unsafe fn atomic_add(dst: *mut T, val: U, order: Ordering) -> T { +#[rustc_const_unstable(feature = "const_atomic", issue = "160078")] +const unsafe fn atomic_add(dst: *mut T, val: U, order: Ordering) -> T { // SAFETY: the caller must uphold the safety contract for `atomic_add`. unsafe { match order { @@ -4070,7 +4043,8 @@ unsafe fn atomic_add(dst: *mut T, val: U, order: Ordering) -> #[inline] #[cfg(target_has_atomic)] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces -unsafe fn atomic_sub(dst: *mut T, val: U, order: Ordering) -> T { +#[rustc_const_unstable(feature = "const_atomic", issue = "160078")] +const unsafe fn atomic_sub(dst: *mut T, val: U, order: Ordering) -> T { // SAFETY: the caller must uphold the safety contract for `atomic_sub`. unsafe { match order { @@ -4089,7 +4063,8 @@ unsafe fn atomic_sub(dst: *mut T, val: U, order: Ordering) -> #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[unstable(feature = "core_intrinsics", issue = "none")] #[doc(hidden)] -pub unsafe fn atomic_compare_exchange( +#[rustc_const_unstable(feature = "const_atomic", issue = "160078")] +pub const unsafe fn atomic_compare_exchange( dst: *mut T, old: T, new: T, @@ -4154,7 +4129,8 @@ pub unsafe fn atomic_compare_exchange( #[inline] #[cfg(target_has_atomic)] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces -unsafe fn atomic_compare_exchange_weak( +#[rustc_const_unstable(feature = "const_atomic", issue = "160078")] +const unsafe fn atomic_compare_exchange_weak( dst: *mut T, old: T, new: T, @@ -4219,7 +4195,8 @@ unsafe fn atomic_compare_exchange_weak( #[inline] #[cfg(target_has_atomic)] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces -unsafe fn atomic_and(dst: *mut T, val: U, order: Ordering) -> T { +#[rustc_const_unstable(feature = "const_atomic", issue = "160078")] +const unsafe fn atomic_and(dst: *mut T, val: U, order: Ordering) -> T { // SAFETY: the caller must uphold the safety contract for `atomic_and` unsafe { match order { @@ -4235,7 +4212,8 @@ unsafe fn atomic_and(dst: *mut T, val: U, order: Ordering) -> #[inline] #[cfg(target_has_atomic)] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces -unsafe fn atomic_nand(dst: *mut T, val: U, order: Ordering) -> T { +#[rustc_const_unstable(feature = "const_atomic", issue = "160078")] +const unsafe fn atomic_nand(dst: *mut T, val: U, order: Ordering) -> T { // SAFETY: the caller must uphold the safety contract for `atomic_nand` unsafe { match order { @@ -4251,7 +4229,8 @@ unsafe fn atomic_nand(dst: *mut T, val: U, order: Ordering) -> #[inline] #[cfg(target_has_atomic)] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces -unsafe fn atomic_or(dst: *mut T, val: U, order: Ordering) -> T { +#[rustc_const_unstable(feature = "const_atomic", issue = "160078")] +const unsafe fn atomic_or(dst: *mut T, val: U, order: Ordering) -> T { // SAFETY: the caller must uphold the safety contract for `atomic_or` unsafe { match order { @@ -4267,7 +4246,8 @@ unsafe fn atomic_or(dst: *mut T, val: U, order: Ordering) -> T #[inline] #[cfg(target_has_atomic)] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces -unsafe fn atomic_xor(dst: *mut T, val: U, order: Ordering) -> T { +#[rustc_const_unstable(feature = "const_atomic", issue = "160078")] +const unsafe fn atomic_xor(dst: *mut T, val: U, order: Ordering) -> T { // SAFETY: the caller must uphold the safety contract for `atomic_xor` unsafe { match order { @@ -4284,7 +4264,8 @@ unsafe fn atomic_xor(dst: *mut T, val: U, order: Ordering) -> #[inline] #[cfg(target_has_atomic)] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces -unsafe fn atomic_max(dst: *mut T, val: T, order: Ordering) -> T { +#[rustc_const_unstable(feature = "const_atomic", issue = "160078")] +const unsafe fn atomic_max(dst: *mut T, val: T, order: Ordering) -> T { // SAFETY: the caller must uphold the safety contract for `atomic_max` unsafe { match order { @@ -4301,7 +4282,8 @@ unsafe fn atomic_max(dst: *mut T, val: T, order: Ordering) -> T { #[inline] #[cfg(target_has_atomic)] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces -unsafe fn atomic_min(dst: *mut T, val: T, order: Ordering) -> T { +#[rustc_const_unstable(feature = "const_atomic", issue = "160078")] +const unsafe fn atomic_min(dst: *mut T, val: T, order: Ordering) -> T { // SAFETY: the caller must uphold the safety contract for `atomic_min` unsafe { match order { @@ -4318,7 +4300,8 @@ unsafe fn atomic_min(dst: *mut T, val: T, order: Ordering) -> T { #[inline] #[cfg(target_has_atomic)] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces -unsafe fn atomic_umax(dst: *mut T, val: T, order: Ordering) -> T { +#[rustc_const_unstable(feature = "const_atomic", issue = "160078")] +const unsafe fn atomic_umax(dst: *mut T, val: T, order: Ordering) -> T { // SAFETY: the caller must uphold the safety contract for `atomic_umax` unsafe { match order { @@ -4335,7 +4318,8 @@ unsafe fn atomic_umax(dst: *mut T, val: T, order: Ordering) -> T { #[inline] #[cfg(target_has_atomic)] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces -unsafe fn atomic_umin(dst: *mut T, val: T, order: Ordering) -> T { +#[rustc_const_unstable(feature = "const_atomic", issue = "160078")] +const unsafe fn atomic_umin(dst: *mut T, val: T, order: Ordering) -> T { // SAFETY: the caller must uphold the safety contract for `atomic_umin` unsafe { match order { @@ -4351,8 +4335,9 @@ unsafe fn atomic_umin(dst: *mut T, val: T, order: Ordering) -> T { /// An atomic fence. /// /// Fences create synchronization between themselves and atomic operations or fences in other -/// threads. To achieve this, a fence prevents the compiler and CPU from reordering certain types of -/// memory operations around it. +/// threads. It can be helpful to think of a fence as preventing the compiler and CPU from +/// reordering certain types of memory operations around it, but that is a simplified model which +/// fails to capture some of the nuances. /// /// There are 3 different ways to use an atomic fence: /// @@ -4501,9 +4486,11 @@ unsafe fn atomic_umin(dst: *mut T, val: T, order: Ordering) -> T { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] +#[rustc_const_unstable(feature = "const_atomic", issue = "160078")] #[rustc_diagnostic_item = "fence"] +#[doc(alias = "atomic_thread_fence")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces -pub fn fence(order: Ordering) { +pub const fn fence(order: Ordering) { // SAFETY: using an atomic fence is safe. unsafe { match order { @@ -4516,15 +4503,15 @@ pub fn fence(order: Ordering) { } } -/// A "compiler-only" atomic fence. +/// An atomic fence for synchronization within a single thread. /// /// Like [`fence`], this function establishes synchronization with other atomic operations and /// fences. However, unlike [`fence`], `compiler_fence` only establishes synchronization with /// operations *in the same thread*. This may at first sound rather useless, since code within a /// thread is typically already totally ordered and does not need any further synchronization. -/// However, there are cases where code can run on the same thread without being ordered: +/// However, there are cases where code can run on the same thread without being synchronized: /// - The most common case is that of a *signal handler*: a signal handler runs in the same thread -/// as the code it interrupted, but it is not ordered with respect to that code. `compiler_fence` +/// as the code it interrupted, but it is not synchronized with that code. `compiler_fence` /// can be used to establish synchronization between a thread and its signal handler, the same way /// that `fence` can be used to establish synchronization across threads. /// - Similar situations can arise in embedded programming with interrupt handlers, or in custom @@ -4535,9 +4522,14 @@ pub fn fence(order: Ordering) { /// [`fence`], synchronization still requires atomic operations to be used in both threads -- it is /// not possible to perform synchronization entirely with fences and non-atomic operations. /// -/// `compiler_fence` does not emit any machine code, but restricts the kinds of memory re-ordering -/// the compiler is allowed to do. `compiler_fence` corresponds to [`atomic_signal_fence`] in C and -/// C++. +/// `compiler_fence` does not emit any machine code. However, note that `compiler_fence` is also +/// *not* a "compiler barrier". It can be helpful to think of a `compiler_fence` as preventing the +/// compiler from reordering certain types of memory operations around it, but that is a simplified +/// model which fails to capture some of the nuances. The only actual guarantee made by +/// `compiler_fence` is establishing synchronization with signal handlers and similar kinds of code, +/// under the rules described in the [`fence`] documentation. +/// +/// `compiler_fence` corresponds to [`atomic_signal_fence`] in C and C++. /// /// [`atomic_signal_fence`]: https://en.cppreference.com/w/cpp/atomic/atomic_signal_fence /// @@ -4579,9 +4571,11 @@ pub fn fence(order: Ordering) { /// ``` #[inline] #[stable(feature = "compiler_fences", since = "1.21.0")] +#[rustc_const_unstable(feature = "const_atomic", issue = "160078")] #[rustc_diagnostic_item = "compiler_fence"] +#[doc(alias = "atomic_signal_fence")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces -pub fn compiler_fence(order: Ordering) { +pub const fn compiler_fence(order: Ordering) { // SAFETY: using an atomic fence is safe. unsafe { match order { diff --git a/library/core/src/sync/exclusive.rs b/library/core/src/sync/exclusive.rs deleted file mode 100644 index 35b8120995187..0000000000000 --- a/library/core/src/sync/exclusive.rs +++ /dev/null @@ -1,322 +0,0 @@ -//! Defines [`Exclusive`]. - -use core::clone::TrivialClone; -use core::cmp::Ordering; -use core::fmt; -use core::future::Future; -use core::hash::{Hash, Hasher}; -use core::marker::{StructuralPartialEq, Tuple}; -use core::ops::{Coroutine, CoroutineState}; -use core::pin::Pin; -use core::task::{Context, Poll}; - -/// `Exclusive` provides _mutable_ access, also referred to as _exclusive_ -/// access to the underlying value. However, it only permits _immutable_, or _shared_ -/// access to the underlying value when that value is [`Sync`]. -/// -/// While this may seem not very useful, it allows `Exclusive` to _unconditionally_ -/// implement `Sync`. Indeed, the safety requirements of `Sync` state that for `Exclusive` -/// to be `Sync`, it must be sound to _share_ across threads, that is, it must be sound -/// for `&Exclusive` to cross thread boundaries. By design, a `&Exclusive` for non-`Sync` T -/// has no API whatsoever, making it useless, thus harmless, thus memory safe. -/// -/// Certain constructs like [`Future`]s can only be used with _exclusive_ access, -/// and are often `Send` but not `Sync`, so `Exclusive` can be used as hint to the -/// Rust compiler that something is `Sync` in practice. -/// -/// ## Examples -/// -/// Using a non-`Sync` future prevents the wrapping struct from being `Sync`: -/// -/// ```compile_fail -/// use core::cell::Cell; -/// -/// async fn other() {} -/// fn assert_sync(t: T) {} -/// struct State { -/// future: F -/// } -/// -/// assert_sync(State { -/// future: async { -/// let cell = Cell::new(1); -/// let cell_ref = &cell; -/// other().await; -/// let value = cell_ref.get(); -/// } -/// }); -/// ``` -/// -/// `Exclusive` ensures the struct is `Sync` without stripping the future of its -/// functionality: -/// -/// ``` -/// #![feature(exclusive_wrapper)] -/// use core::cell::Cell; -/// use core::sync::Exclusive; -/// -/// async fn other() {} -/// fn assert_sync(t: T) {} -/// struct State { -/// future: Exclusive -/// } -/// -/// assert_sync(State { -/// future: Exclusive::new(async { -/// let cell = Cell::new(1); -/// let cell_ref = &cell; -/// other().await; -/// let value = cell_ref.get(); -/// }) -/// }); -/// ``` -/// -/// ## Parallels with a mutex -/// -/// In some sense, `Exclusive` can be thought of as a _compile-time_ version of -/// a mutex, as the borrow-checker guarantees that only one `&mut` can exist -/// for any value. This is a parallel with the fact that -/// `&` and `&mut` references together can be thought of as a _compile-time_ -/// version of a read-write lock. -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -#[doc(alias = "SyncWrapper")] -#[doc(alias = "SyncCell")] -#[doc(alias = "Unique")] -// `Exclusive` can't have derived `PartialOrd`, `Clone`, etc. impls as they would -// use `&` access to the inner value, violating the `Sync` impl's safety -// requirements. -#[derive(Default)] -#[repr(transparent)] -pub struct Exclusive { - inner: T, -} - -// See `Exclusive`'s docs for justification. -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -unsafe impl Sync for Exclusive {} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl fmt::Debug for Exclusive { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> Result<(), fmt::Error> { - f.debug_struct("Exclusive").finish_non_exhaustive() - } -} - -impl Exclusive { - /// Wrap a value in an `Exclusive` - #[unstable(feature = "exclusive_wrapper", issue = "98407")] - #[must_use] - #[inline] - pub const fn new(t: T) -> Self { - Self { inner: t } - } - - /// Unwrap the value contained in the `Exclusive` - #[unstable(feature = "exclusive_wrapper", issue = "98407")] - #[rustc_const_unstable(feature = "exclusive_wrapper", issue = "98407")] - #[must_use] - #[inline] - pub const fn into_inner(self) -> T { - self.inner - } -} - -impl Exclusive { - /// Gets exclusive access to the underlying value. - #[unstable(feature = "exclusive_wrapper", issue = "98407")] - #[must_use] - #[inline] - pub const fn get_mut(&mut self) -> &mut T { - &mut self.inner - } - - /// Gets pinned exclusive access to the underlying value. - /// - /// `Exclusive` is considered to _structurally pin_ the underlying - /// value, which means _unpinned_ `Exclusive`s can produce _unpinned_ - /// access to the underlying value, but _pinned_ `Exclusive`s only - /// produce _pinned_ access to the underlying value. - #[unstable(feature = "exclusive_wrapper", issue = "98407")] - #[must_use] - #[inline] - pub const fn get_pin_mut(self: Pin<&mut Self>) -> Pin<&mut T> { - // SAFETY: `Exclusive` can only produce `&mut T` if itself is unpinned - // `Pin::map_unchecked_mut` is not const, so we do this conversion manually - unsafe { Pin::new_unchecked(&mut self.get_unchecked_mut().inner) } - } - - /// Build a _mutable_ reference to an `Exclusive` from - /// a _mutable_ reference to a `T`. This allows you to skip - /// building an `Exclusive` with [`Exclusive::new`]. - #[unstable(feature = "exclusive_wrapper", issue = "98407")] - #[must_use] - #[inline] - pub const fn from_mut(r: &'_ mut T) -> &'_ mut Exclusive { - // SAFETY: repr is ≥ C, so refs have the same layout; and `Exclusive` properties are `&mut`-agnostic - unsafe { &mut *(r as *mut T as *mut Exclusive) } - } - - /// Build a _pinned mutable_ reference to an `Exclusive` from - /// a _pinned mutable_ reference to a `T`. This allows you to skip - /// building an `Exclusive` with [`Exclusive::new`]. - #[unstable(feature = "exclusive_wrapper", issue = "98407")] - #[must_use] - #[inline] - pub const fn from_pin_mut(r: Pin<&'_ mut T>) -> Pin<&'_ mut Exclusive> { - // SAFETY: `Exclusive` can only produce `&mut T` if itself is unpinned - // `Pin::map_unchecked_mut` is not const, so we do this conversion manually - unsafe { Pin::new_unchecked(Self::from_mut(r.get_unchecked_mut())) } - } -} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -#[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for Exclusive { - #[inline] - fn from(t: T) -> Self { - Self::new(t) - } -} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl FnOnce for Exclusive -where - F: FnOnce, - Args: Tuple, -{ - type Output = F::Output; - - extern "rust-call" fn call_once(self, args: Args) -> Self::Output { - self.into_inner().call_once(args) - } -} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl FnMut for Exclusive -where - F: FnMut, - Args: Tuple, -{ - extern "rust-call" fn call_mut(&mut self, args: Args) -> Self::Output { - self.get_mut().call_mut(args) - } -} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl Fn for Exclusive -where - F: Sync + Fn, - Args: Tuple, -{ - extern "rust-call" fn call(&self, args: Args) -> Self::Output { - self.as_ref().call(args) - } -} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl Future for Exclusive -where - T: Future + ?Sized, -{ - type Output = T::Output; - - #[inline] - fn poll(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll { - self.get_pin_mut().poll(cx) - } -} - -#[unstable(feature = "coroutine_trait", issue = "43122")] // also #98407 -impl Coroutine for Exclusive -where - G: Coroutine + ?Sized, -{ - type Yield = G::Yield; - type Return = G::Return; - - #[inline] - fn resume(self: Pin<&mut Self>, arg: R) -> CoroutineState { - G::resume(self.get_pin_mut(), arg) - } -} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl AsRef for Exclusive -where - T: Sync + ?Sized, -{ - #[inline] - fn as_ref(&self) -> &T { - &self.inner - } -} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl Clone for Exclusive -where - T: Sync + Clone, -{ - #[inline] - fn clone(&self) -> Self { - Self { inner: self.inner.clone() } - } -} - -#[doc(hidden)] -#[unstable(feature = "trivial_clone", issue = "none")] -unsafe impl TrivialClone for Exclusive where T: Sync + TrivialClone {} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl Copy for Exclusive where T: Sync + Copy {} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl PartialEq> for Exclusive -where - T: Sync + PartialEq + ?Sized, - U: Sync + ?Sized, -{ - #[inline] - fn eq(&self, other: &Exclusive) -> bool { - self.inner == other.inner - } -} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl StructuralPartialEq for Exclusive where T: Sync + StructuralPartialEq + ?Sized {} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl Eq for Exclusive where T: Sync + Eq + ?Sized {} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl Hash for Exclusive -where - T: Sync + Hash + ?Sized, -{ - #[inline] - fn hash(&self, state: &mut H) { - Hash::hash(&self.inner, state) - } -} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl PartialOrd> for Exclusive -where - T: Sync + PartialOrd + ?Sized, - U: Sync + ?Sized, -{ - #[inline] - fn partial_cmp(&self, other: &Exclusive) -> Option { - self.inner.partial_cmp(&other.inner) - } -} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl Ord for Exclusive -where - T: Sync + Ord + ?Sized, -{ - #[inline] - fn cmp(&self, other: &Self) -> Ordering { - self.inner.cmp(&other.inner) - } -} diff --git a/library/core/src/sync/mod.rs b/library/core/src/sync/mod.rs index 4365e4cb250ca..6c2660263a705 100644 --- a/library/core/src/sync/mod.rs +++ b/library/core/src/sync/mod.rs @@ -3,6 +3,6 @@ #![stable(feature = "rust1", since = "1.0.0")] pub mod atomic; -mod exclusive; +mod sync_view; #[unstable(feature = "exclusive_wrapper", issue = "98407")] -pub use exclusive::Exclusive; +pub use sync_view::SyncView; diff --git a/library/core/src/sync/sync_view.rs b/library/core/src/sync/sync_view.rs new file mode 100644 index 0000000000000..63e157bf90f23 --- /dev/null +++ b/library/core/src/sync/sync_view.rs @@ -0,0 +1,414 @@ +//! Defines [`SyncView`]. + +use core::clone::TrivialClone; +use core::cmp::Ordering; +use core::fmt; +use core::future::Future; +use core::hash::{Hash, Hasher}; +use core::marker::{StructuralPartialEq, Tuple}; +use core::ops::{Coroutine, CoroutineState}; +use core::pin::Pin; +use core::task::{Context, Poll}; + +/// `SyncView` provides _mutable_ access, also referred to as _exclusive_ +/// access to the underlying value. However, it only permits _immutable_, or _shared_ +/// access to the underlying value when that value is [`Sync`]. +/// +/// While this may seem not very useful, it allows `SyncView` to _unconditionally_ +/// implement `Sync`. Indeed, the safety requirements of `Sync` state that for `SyncView` +/// to be `Sync`, it must be sound to _share_ across threads, that is, it must be sound +/// for `&SyncView` to cross thread boundaries. By design, a `&SyncView` for non-`Sync` +/// `T` has no API whatsoever, making it useless, thus harmless, thus memory safe. +/// +/// Certain constructs like [`Future`]s can only be used with _exclusive_ access, +/// and are often [`Send`] but not `Sync`, so `SyncView` can be used as hint to the +/// Rust compiler that something is `Sync` in practice. +/// +/// ## Examples +/// +/// Using a non-`Sync` future prevents the wrapping struct from being `Sync`: +/// +/// ```compile_fail +/// use core::cell::Cell; +/// +/// async fn other() {} +/// fn assert_sync(t: T) {} +/// struct State { +/// future: F +/// } +/// +/// assert_sync(State { +/// future: async { +/// let cell = Cell::new(1); +/// let cell_ref = &cell; +/// other().await; +/// let value = cell_ref.get(); +/// } +/// }); +/// ``` +/// +/// `SyncView` ensures the struct is `Sync` without stripping the future of its +/// functionality: +/// +/// ``` +/// #![feature(exclusive_wrapper)] +/// use core::cell::Cell; +/// use core::sync::SyncView; +/// +/// async fn other() {} +/// fn assert_sync(t: T) {} +/// struct State { +/// future: SyncView +/// } +/// +/// assert_sync(State { +/// future: SyncView::new(async { +/// let cell = Cell::new(1); +/// let cell_ref = &cell; +/// other().await; +/// let value = cell_ref.get(); +/// }) +/// }); +/// ``` +/// +/// ## Parallels with a mutex +/// +/// In some sense, `SyncView` can be thought of as a _compile-time_ version of +/// a mutex, as the borrow-checker guarantees that only one `&mut` can exist +/// for any value. This is a parallel with the fact that +/// `&` and `&mut` references together can be thought of as a _compile-time_ +/// version of a read-write lock. +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[doc(alias = "SyncWrapper")] +#[doc(alias = "SyncCell")] +#[doc(alias = "Unique")] +#[doc(alias = "Exclusive")] +// `SyncView` can't have derived `PartialOrd`, `Clone`, etc. impls as they would +// use `&` access to the inner value, violating the `Sync` impl's safety +// requirements. +#[repr(transparent)] +pub struct SyncView { + inner: T, +} + +// See `SyncView`'s docs for justification. +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +unsafe impl Sync for SyncView {} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_default", issue = "143894")] +const impl Default for SyncView +where + T: [const] Default, +{ + #[inline] + fn default() -> Self { + Self { inner: Default::default() } + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +impl fmt::Debug for SyncView { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> Result<(), fmt::Error> { + f.debug_struct("SyncView").finish_non_exhaustive() + } +} + +impl SyncView { + /// Wrap a value in an `SyncView` + #[unstable(feature = "exclusive_wrapper", issue = "98407")] + #[rustc_const_unstable(feature = "exclusive_wrapper", issue = "98407")] + #[must_use] + #[inline] + pub const fn new(t: T) -> Self { + Self { inner: t } + } + + /// Unwrap the value contained in the `SyncView` + #[unstable(feature = "exclusive_wrapper", issue = "98407")] + #[rustc_const_unstable(feature = "exclusive_wrapper", issue = "98407")] + #[must_use] + #[inline] + pub const fn into_inner(self) -> T { + self.inner + } +} + +impl SyncView { + /// Gets pinned exclusive access to the underlying value. + /// + /// `SyncView` is considered to _structurally pin_ the underlying + /// value, which means _unpinned_ `SyncView`s can produce _unpinned_ + /// access to the underlying value, but _pinned_ `SyncView`s only + /// produce _pinned_ access to the underlying value. + #[unstable(feature = "exclusive_wrapper", issue = "98407")] + #[rustc_const_unstable(feature = "exclusive_wrapper", issue = "98407")] + #[must_use] + #[inline] + pub const fn as_pin_mut(self: Pin<&mut Self>) -> Pin<&mut T> { + // SAFETY: `SyncView` can only produce `&mut T` if itself is unpinned + // `Pin::map_unchecked_mut` is not const, so we do this conversion manually + unsafe { Pin::new_unchecked(&mut self.get_unchecked_mut().inner) } + } + + /// Build a _mutable_ reference to an `SyncView` from + /// a _mutable_ reference to a `T`. This allows you to skip + /// building an `SyncView` with [`SyncView::new`]. + #[unstable(feature = "exclusive_wrapper", issue = "98407")] + #[rustc_const_unstable(feature = "exclusive_wrapper", issue = "98407")] + #[must_use] + #[inline] + pub const fn from_mut(r: &'_ mut T) -> &'_ mut SyncView { + // SAFETY: repr is ≥ C, so refs have the same layout; and `SyncView` properties are `&mut`-agnostic + unsafe { &mut *(r as *mut T as *mut SyncView) } + } + + /// Build a _pinned mutable_ reference to an `SyncView` from + /// a _pinned mutable_ reference to a `T`. This allows you to skip + /// building an `SyncView` with [`SyncView::new`]. + #[unstable(feature = "exclusive_wrapper", issue = "98407")] + #[rustc_const_unstable(feature = "exclusive_wrapper", issue = "98407")] + #[must_use] + #[inline] + pub const fn from_pin_mut(r: Pin<&'_ mut T>) -> Pin<&'_ mut SyncView> { + // SAFETY: `SyncView` can only produce `&mut T` if itself is unpinned + // `Pin::map_unchecked_mut` is not const, so we do this conversion manually + unsafe { Pin::new_unchecked(Self::from_mut(r.get_unchecked_mut())) } + } +} + +impl SyncView { + /// Gets pinned shared access to the underlying value. + /// + /// `SyncView` is considered to _structurally pin_ the underlying + /// value, which means _unpinned_ `SyncView`s can produce _unpinned_ + /// access to the underlying value, but _pinned_ `SyncView`s only + /// produce _pinned_ access to the underlying value. + #[unstable(feature = "exclusive_wrapper", issue = "98407")] + #[rustc_const_unstable(feature = "exclusive_wrapper", issue = "98407")] + #[must_use] + #[inline] + pub const fn as_pin_ref(self: Pin<&Self>) -> Pin<&T> { + // SAFETY: `SyncView` can only produce `&T` if itself is unpinned + // `Pin::map_unchecked` is not const, so we do this conversion manually + unsafe { Pin::new_unchecked(&self.get_ref().inner) } + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_convert", issue = "143773")] +const impl From for SyncView { + #[inline] + fn from(t: T) -> Self { + Self::new(t) + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_trait_impl", issue = "143874")] +const impl FnOnce for SyncView +where + F: [const] FnOnce, + Args: Tuple, +{ + type Output = F::Output; + + extern "rust-call" fn call_once(self, args: Args) -> Self::Output { + self.into_inner().call_once(args) + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_trait_impl", issue = "143874")] +const impl FnMut for SyncView +where + F: [const] FnMut, + Args: Tuple, +{ + extern "rust-call" fn call_mut(&mut self, args: Args) -> Self::Output { + self.as_mut().call_mut(args) + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_trait_impl", issue = "143874")] +const impl Fn for SyncView +where + F: Sync + [const] Fn, + Args: Tuple, +{ + extern "rust-call" fn call(&self, args: Args) -> Self::Output { + self.as_ref().call(args) + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +impl AsyncFnOnce for SyncView +where + F: AsyncFnOnce, + Args: Tuple, +{ + type CallOnceFuture = F::CallOnceFuture; + + type Output = F::Output; + + extern "rust-call" fn async_call_once(self, args: Args) -> Self::CallOnceFuture { + self.into_inner().async_call_once(args) + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +impl AsyncFnMut for SyncView +where + F: AsyncFnMut, + Args: Tuple, +{ + type CallRefFuture<'a> + = F::CallRefFuture<'a> + where + F: 'a; + + extern "rust-call" fn async_call_mut(&mut self, args: Args) -> Self::CallRefFuture<'_> { + self.as_mut().async_call_mut(args) + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +impl AsyncFn for SyncView +where + F: Sync + AsyncFn, + Args: Tuple, +{ + extern "rust-call" fn async_call(&self, args: Args) -> Self::CallRefFuture<'_> { + self.as_ref().async_call(args) + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +impl Future for SyncView +where + T: Future + ?Sized, +{ + type Output = T::Output; + + #[inline] + fn poll(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll { + self.as_pin_mut().poll(cx) + } +} + +#[unstable(feature = "coroutine_trait", issue = "43122")] // also #98407 +impl Coroutine for SyncView +where + G: Coroutine + ?Sized, +{ + type Yield = G::Yield; + type Return = G::Return; + + #[inline] + fn resume(self: Pin<&mut Self>, arg: R) -> CoroutineState { + G::resume(self.as_pin_mut(), arg) + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_convert", issue = "143773")] +const impl AsRef for SyncView +where + T: Sync + ?Sized, +{ + /// Gets shared access to the underlying value. + #[inline] + fn as_ref(&self) -> &T { + &self.inner + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_convert", issue = "143773")] +const impl AsMut for SyncView +where + T: ?Sized, +{ + /// Gets exclusive access to the underlying value. + #[inline] + fn as_mut(&mut self) -> &mut T { + &mut self.inner + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_clone", issue = "142757")] +const impl Clone for SyncView +where + T: Sync + [const] Clone, +{ + #[inline] + fn clone(&self) -> Self { + Self { inner: self.inner.clone() } + } +} + +#[doc(hidden)] +#[unstable(feature = "trivial_clone", issue = "none")] +#[rustc_const_unstable(feature = "const_clone", issue = "142757")] +const unsafe impl TrivialClone for SyncView where T: Sync + [const] TrivialClone {} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +impl Copy for SyncView where T: Sync + Copy {} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +const impl PartialEq> for SyncView +where + T: Sync + [const] PartialEq + ?Sized, + U: Sync + ?Sized, +{ + #[inline] + fn eq(&self, other: &SyncView) -> bool { + self.inner == other.inner + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +impl StructuralPartialEq for SyncView where T: Sync + StructuralPartialEq + ?Sized {} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +const impl Eq for SyncView where T: Sync + [const] Eq + ?Sized {} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +impl Hash for SyncView +where + T: Sync + Hash + ?Sized, +{ + #[inline] + fn hash(&self, state: &mut H) { + Hash::hash(&self.inner, state) + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +const impl PartialOrd> for SyncView +where + T: Sync + [const] PartialOrd + ?Sized, + U: Sync + ?Sized, +{ + #[inline] + fn partial_cmp(&self, other: &SyncView) -> Option { + self.inner.partial_cmp(&other.inner) + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +const impl Ord for SyncView +where + T: Sync + [const] Ord + ?Sized, +{ + #[inline] + fn cmp(&self, other: &Self) -> Ordering { + self.inner.cmp(&other.inner) + } +} diff --git a/library/core/src/task/poll.rs b/library/core/src/task/poll.rs index 380abac0ae95f..87f8830a6b176 100644 --- a/library/core/src/task/poll.rs +++ b/library/core/src/task/poll.rs @@ -216,7 +216,7 @@ impl Poll>> { #[stable(feature = "futures_api", since = "1.36.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for Poll { +const impl From for Poll { /// Moves the value into a [`Poll::Ready`] to make a `Poll`. /// /// # Example diff --git a/library/core/src/task/wake.rs b/library/core/src/task/wake.rs index c22a9da0385b5..473b185d24652 100644 --- a/library/core/src/task/wake.rs +++ b/library/core/src/task/wake.rs @@ -245,14 +245,14 @@ impl<'a> Context<'a> { #[stable(feature = "futures_api", since = "1.36.0")] #[rustc_const_stable(feature = "const_waker", since = "1.82.0")] pub const fn waker(&self) -> &'a Waker { - &self.waker + self.waker } /// Returns a reference to the [`LocalWaker`] for the current task. #[inline] #[unstable(feature = "local_waker", issue = "118959")] pub const fn local_waker(&self) -> &'a LocalWaker { - &self.local_waker + self.local_waker } /// Returns a reference to the extension data for the current task. @@ -418,15 +418,16 @@ unsafe impl Sync for Waker {} impl Waker { /// Wakes up the task associated with this `Waker`. /// - /// As long as the executor keeps running and the task is not finished, it is - /// guaranteed that each invocation of [`wake()`](Self::wake) (or + /// As long as the executor keeps running and the task is not finished, + /// it is guaranteed that each invocation of [`wake()`](Self::wake) (or /// [`wake_by_ref()`](Self::wake_by_ref)) will be followed by at least one - /// [`poll()`] of the task to which this `Waker` belongs. This makes - /// it possible to temporarily yield to other tasks while running potentially - /// unbounded processing loops. + /// [`poll()`] of the task to which this `Waker` belongs, such that the call to + /// [`wake()`](Self::wake) (or [`wake_by_ref()`](Self::wake_by_ref)) _happens-before_ + /// the beginning of the invocation of [`poll()`]. This makes it possible to temporarily + /// yield to other tasks while running potentially unbounded processing loops. /// /// Note that the above implies that multiple wake-ups may be coalesced into a - /// single [`poll()`] invocation by the runtime. + /// single [`poll()`] invocation by the executor. /// /// Also note that yielding to competing tasks is not guaranteed: it is the /// executor’s choice which task to run and the executor may choose to run the @@ -946,7 +947,7 @@ impl Clone for LocalWaker { #[unstable(feature = "local_waker", issue = "118959")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef for Waker { +const impl AsRef for Waker { fn as_ref(&self) -> &LocalWaker { // SAFETY: LocalWaker is just Waker without thread safety unsafe { transmute(self) } diff --git a/library/core/src/time.rs b/library/core/src/time.rs index 2277794723dfc..daf9ace23ba64 100644 --- a/library/core/src/time.rs +++ b/library/core/src/time.rs @@ -716,7 +716,6 @@ impl Duration { /// # Examples /// /// ``` - /// #![feature(duration_constants)] /// use std::time::Duration; /// /// assert_eq!(Duration::new(0, 0).saturating_add(Duration::new(0, 1)), Duration::new(0, 1)); @@ -829,7 +828,6 @@ impl Duration { /// # Examples /// /// ``` - /// #![feature(duration_constants)] /// use std::time::Duration; /// /// assert_eq!(Duration::new(0, 500_000_001).saturating_mul(2), Duration::new(1, 2)); @@ -1038,6 +1036,7 @@ impl Duration { /// This method will panic if result is negative, overflows `Duration` or not finite. /// /// # Examples + /// /// ``` /// use std::time::Duration; /// @@ -1045,6 +1044,37 @@ impl Duration { /// assert_eq!(dur.mul_f64(3.14), Duration::new(8, 478_000_000)); /// assert_eq!(dur.mul_f64(3.14e5), Duration::new(847_800, 0)); /// ``` + /// + /// Note that `f64` does not have enough bits ([`f64::MANTISSA_DIGITS`]) to represent the full + /// range of possible `Duration` with nanosecond precision, so rounding may occur even for + /// trivial operations like multiplying by 1. + /// + /// ``` + /// # #![feature(float_exact_integer_constants)] + /// use std::time::Duration; + /// + /// // This is about 14.9 weeks, remaining precise to the nanosecond: + /// let weeks = Duration::from_nanos(f64::MAX_EXACT_INTEGER as u64); + /// assert_eq!(weeks, weeks.mul_f64(1.0)); + /// + /// // A larger value incurs rounding in the floating-point operation: + /// let weeks = Duration::from_nanos(u64::MAX); + /// assert_ne!(weeks, weeks.mul_f64(1.0)); + /// + /// // This is over 285 million years, remaining precise to the second: + /// let years = Duration::from_secs(f64::MAX_EXACT_INTEGER as u64); + /// assert_eq!(years, years.mul_f64(1.0)); + /// + /// // And again larger values incur rounding: + /// let years = Duration::from_secs(u64::MAX / 2); + /// assert_ne!(years, years.mul_f64(1.0)); + /// ``` + /// + /// ```should_panic + /// # use std::time::Duration; + /// // In the extreme, rounding can even overflow `Duration`, which panics. + /// let _ = Duration::from_secs(u64::MAX).mul_f64(1.0); + /// ``` #[stable(feature = "duration_float", since = "1.38.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] @@ -1055,6 +1085,10 @@ impl Duration { /// Multiplies `Duration` by `f32`. /// + /// Since the significand of `f32` is quite limited compared to the range of `Duration` + /// -- only about 16.8ms of exact nanosecond precision -- this method currently forwards + /// to [`mul_f64`][Self::mul_f64] for greater accuracy. + /// /// # Panics /// This method will panic if result is negative, overflows `Duration` or not finite. /// @@ -1063,7 +1097,10 @@ impl Duration { /// use std::time::Duration; /// /// let dur = Duration::new(2, 700_000_000); - /// assert_eq!(dur.mul_f32(3.14), Duration::new(8, 478_000_641)); + /// // Note that this `3.14_f32` argument already has more floating-point + /// // representation error than a direct `3.14_f64` would, so the result + /// // is slightly different from the ideal 8.478s. + /// assert_eq!(dur.mul_f32(3.14), Duration::new(8, 478_000_283)); /// assert_eq!(dur.mul_f32(3.14e5), Duration::new(847_800, 0)); /// ``` #[stable(feature = "duration_float", since = "1.38.0")] @@ -1071,7 +1108,7 @@ impl Duration { without modifying the original"] #[inline] pub fn mul_f32(self, rhs: f32) -> Duration { - Duration::from_secs_f32(rhs * self.as_secs_f32()) + self.mul_f64(rhs.into()) } /// Divides `Duration` by `f64`. @@ -1080,6 +1117,7 @@ impl Duration { /// This method will panic if result is negative, overflows `Duration` or not finite. /// /// # Examples + /// /// ``` /// use std::time::Duration; /// @@ -1087,6 +1125,37 @@ impl Duration { /// assert_eq!(dur.div_f64(3.14), Duration::new(0, 859_872_611)); /// assert_eq!(dur.div_f64(3.14e5), Duration::new(0, 8_599)); /// ``` + /// + /// Note that `f64` does not have enough bits ([`f64::MANTISSA_DIGITS`]) to represent the full + /// range of possible `Duration` with nanosecond precision, so rounding may occur even for + /// trivial operations like dividing by 1. + /// + /// ``` + /// # #![feature(float_exact_integer_constants)] + /// use std::time::Duration; + /// + /// // This is about 14.9 weeks, remaining precise to the nanosecond: + /// let weeks = Duration::from_nanos(f64::MAX_EXACT_INTEGER as u64); + /// assert_eq!(weeks, weeks.div_f64(1.0)); + /// + /// // A larger value incurs rounding in the floating-point operation: + /// let weeks = Duration::from_nanos(u64::MAX); + /// assert_ne!(weeks, weeks.div_f64(1.0)); + /// + /// // This is over 285 million years, remaining precise to the second: + /// let years = Duration::from_secs(f64::MAX_EXACT_INTEGER as u64); + /// assert_eq!(years, years.div_f64(1.0)); + /// + /// // And again larger values incur rounding: + /// let years = Duration::from_secs(u64::MAX / 2); + /// assert_ne!(years, years.div_f64(1.0)); + /// ``` + /// + /// ```should_panic + /// # use std::time::Duration; + /// // In the extreme, rounding can even overflow `Duration`, which panics. + /// let _ = Duration::from_secs(u64::MAX).div_f64(1.0); + /// ``` #[stable(feature = "duration_float", since = "1.38.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] @@ -1097,6 +1166,10 @@ impl Duration { /// Divides `Duration` by `f32`. /// + /// Since the significand of `f32` is quite limited compared to the range of `Duration` + /// -- only about 16.8ms of exact nanosecond precision -- this method currently forwards + /// to [`div_f64`][Self::div_f64] for greater accuracy. + /// /// # Panics /// This method will panic if result is negative, overflows `Duration` or not finite. /// @@ -1105,9 +1178,10 @@ impl Duration { /// use std::time::Duration; /// /// let dur = Duration::new(2, 700_000_000); - /// // note that due to rounding errors result is slightly - /// // different from 0.859_872_611 - /// assert_eq!(dur.div_f32(3.14), Duration::new(0, 859_872_580)); + /// // Note that this `3.14_f32` argument already has more floating-point + /// // representation error than a direct `3.14_f64` would, so the result + /// // is slightly different from the ideally rounded 0.859_872_611. + /// assert_eq!(dur.div_f32(3.14), Duration::new(0, 859_872_583)); /// assert_eq!(dur.div_f32(3.14e5), Duration::new(0, 8_599)); /// ``` #[stable(feature = "duration_float", since = "1.38.0")] @@ -1115,7 +1189,7 @@ impl Duration { without modifying the original"] #[inline] pub fn div_f32(self, rhs: f32) -> Duration { - Duration::from_secs_f32(self.as_secs_f32() / rhs) + self.div_f64(rhs.into()) } /// Divides `Duration` by `Duration` and returns `f64`. @@ -1205,7 +1279,7 @@ impl Duration { #[stable(feature = "duration", since = "1.3.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const Add for Duration { +const impl Add for Duration { type Output = Duration; #[inline] @@ -1216,7 +1290,7 @@ impl const Add for Duration { #[stable(feature = "time_augmented_assignment", since = "1.9.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const AddAssign for Duration { +const impl AddAssign for Duration { #[inline] fn add_assign(&mut self, rhs: Duration) { *self = *self + rhs; @@ -1225,7 +1299,7 @@ impl const AddAssign for Duration { #[stable(feature = "duration", since = "1.3.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const Sub for Duration { +const impl Sub for Duration { type Output = Duration; #[inline] @@ -1236,7 +1310,7 @@ impl const Sub for Duration { #[stable(feature = "time_augmented_assignment", since = "1.9.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const SubAssign for Duration { +const impl SubAssign for Duration { #[inline] fn sub_assign(&mut self, rhs: Duration) { *self = *self - rhs; @@ -1245,7 +1319,7 @@ impl const SubAssign for Duration { #[stable(feature = "duration", since = "1.3.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const Mul for Duration { +const impl Mul for Duration { type Output = Duration; #[inline] @@ -1256,7 +1330,7 @@ impl const Mul for Duration { #[stable(feature = "symmetric_u32_duration_mul", since = "1.31.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const Mul for u32 { +const impl Mul for u32 { type Output = Duration; #[inline] @@ -1267,7 +1341,7 @@ impl const Mul for u32 { #[stable(feature = "time_augmented_assignment", since = "1.9.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const MulAssign for Duration { +const impl MulAssign for Duration { #[inline] fn mul_assign(&mut self, rhs: u32) { *self = *self * rhs; @@ -1276,7 +1350,7 @@ impl const MulAssign for Duration { #[stable(feature = "duration", since = "1.3.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const Div for Duration { +const impl Div for Duration { type Output = Duration; #[inline] @@ -1288,7 +1362,7 @@ impl const Div for Duration { #[stable(feature = "time_augmented_assignment", since = "1.9.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const DivAssign for Duration { +const impl DivAssign for Duration { #[inline] #[track_caller] fn div_assign(&mut self, rhs: u32) { diff --git a/library/core/src/tuple.rs b/library/core/src/tuple.rs index 58f81372aff75..6dd26d3ed762d 100644 --- a/library/core/src/tuple.rs +++ b/library/core/src/tuple.rs @@ -25,7 +25,7 @@ macro_rules! tuple_impls { $($T)+ @ #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl<$($T: [const] PartialEq),+> const PartialEq for ($($T,)+) { + const impl<$($T: [const] PartialEq),+> PartialEq for ($($T,)+) { #[inline] fn eq(&self, other: &($($T,)+)) -> bool { $( ${ignore($T)} self.${index()} == other.${index()} )&&+ @@ -41,14 +41,13 @@ macro_rules! tuple_impls { $($T)+ @ #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl<$($T: [const] Eq),+> const Eq for ($($T,)+) + const impl<$($T: [const] Eq),+> Eq for ($($T,)+) {} } maybe_tuple_doc! { $($T)+ @ - #[unstable(feature = "adt_const_params", issue = "95174")] - #[unstable_feature_bound(unsized_const_params)] + #[unstable(feature = "min_adt_const_params", issue = "154042")] impl<$($T: ConstParamTy_),+> ConstParamTy_ for ($($T,)+) {} } @@ -64,7 +63,7 @@ macro_rules! tuple_impls { $($T)+ @ #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl<$($T: [const] PartialOrd),+> const PartialOrd for ($($T,)+) + const impl<$($T: [const] PartialOrd),+> PartialOrd for ($($T,)+) { #[inline] fn partial_cmp(&self, other: &($($T,)+)) -> Option { @@ -109,7 +108,7 @@ macro_rules! tuple_impls { $($T)+ @ #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl<$($T: [const] Ord),+> const Ord for ($($T,)+) + const impl<$($T: [const] Ord),+> Ord for ($($T,)+) { #[inline] fn cmp(&self, other: &($($T,)+)) -> Ordering { @@ -121,7 +120,8 @@ macro_rules! tuple_impls { maybe_tuple_doc! { $($T)+ @ #[stable(feature = "rust1", since = "1.0.0")] - impl<$($T: Default),+> Default for ($($T,)+) { + #[rustc_const_unstable(feature = "const_default", issue = "143894")] + const impl<$($T: [const] Default),+> Default for ($($T,)+) { #[inline] fn default() -> ($($T,)+) { ($({ let x: $T = Default::default(); x},)+) diff --git a/library/core/src/unicode/mod.rs b/library/core/src/unicode/mod.rs index c71fa754e68fb..1648795facd40 100644 --- a/library/core/src/unicode/mod.rs +++ b/library/core/src/unicode/mod.rs @@ -4,22 +4,23 @@ // for use in alloc, not re-exported in std. #[rustfmt::skip] -pub use unicode_data::case_ignorable::lookup as Case_Ignorable; -pub use unicode_data::cased::lookup as Cased; pub use unicode_data::conversions; #[rustfmt::skip] pub(crate) use unicode_data::alphabetic::lookup as Alphabetic; +pub(crate) use unicode_data::case_ignorable::lookup as Case_Ignorable; +pub(crate) use unicode_data::cf::lookup as Cf; +pub(crate) use unicode_data::cn_planes_0_3::lookup as Cn_planes_0_3; +pub(crate) use unicode_data::default_ignorable_code_point::lookup as Default_Ignorable_Code_Point; pub(crate) use unicode_data::grapheme_extend::lookup as Grapheme_Extend; pub(crate) use unicode_data::lowercase::lookup as Lowercase; +pub(crate) use unicode_data::lt::lookup as Lt; pub(crate) use unicode_data::n::lookup as N; pub(crate) use unicode_data::uppercase::lookup as Uppercase; pub(crate) use unicode_data::white_space::lookup as White_Space; -pub(crate) mod printable; - #[allow(unreachable_pub)] -mod unicode_data; +pub mod unicode_data; /// The version of [Unicode](https://www.unicode.org/) that the Unicode parts of /// `char` and `str` methods are based on. @@ -27,8 +28,13 @@ mod unicode_data; /// New versions of Unicode are released regularly and subsequently all methods /// in the standard library depending on Unicode are updated. Therefore the /// behavior of some `char` and `str` methods and the value of this constant -/// changes over time. This is *not* considered to be a breaking change. +/// changes over time, within the boundaries of Unicode's [stability policies]. +/// This is *not* considered to be a breaking change. +/// +/// [stability policies]: https://www.unicode.org/policies/stability_policy.html /// /// The version numbering scheme is explained in -/// [Unicode 11.0 or later, Section 3.1 Versions of the Unicode Standard](https://www.unicode.org/versions/Unicode11.0.0/ch03.pdf#page=4). +/// [Section 3.1 (Version Numbering)] of the Unicode Standard. +/// +/// [Section 3.1 (Version Numbering)]: https://www.unicode.org/versions/latest/core-spec/chapter-3/#G49512 pub const UNICODE_VERSION: (u8, u8, u8) = unicode_data::UNICODE_VERSION; diff --git a/library/core/src/unicode/printable.py b/library/core/src/unicode/printable.py deleted file mode 100755 index 260fa9f9e6ad2..0000000000000 --- a/library/core/src/unicode/printable.py +++ /dev/null @@ -1,258 +0,0 @@ -#!/usr/bin/env python - -# This script uses the following Unicode tables: -# - UnicodeData.txt - - -from collections import namedtuple -import csv -import os -import subprocess - -NUM_CODEPOINTS = 0x110000 - - -def to_ranges(iter): - current = None - for i in iter: - if current is None or i != current[1] or i in (0x10000, 0x20000): - if current is not None: - yield tuple(current) - current = [i, i + 1] - else: - current[1] += 1 - if current is not None: - yield tuple(current) - - -def get_escaped(codepoints): - for c in codepoints: - if (c.class_ or "Cn") in "Cc Cf Cs Co Cn Zl Zp Zs".split() and c.value != ord( - " " - ): - yield c.value - - -def get_file(f): - try: - return open(os.path.basename(f)) - except FileNotFoundError: - subprocess.run(["curl", "-O", f], check=True) - return open(os.path.basename(f)) - - -Codepoint = namedtuple("Codepoint", "value class_") - - -def get_codepoints(f): - r = csv.reader(f, delimiter=";") - prev_codepoint = 0 - class_first = None - for row in r: - codepoint = int(row[0], 16) - name = row[1] - class_ = row[2] - - if class_first is not None: - if not name.endswith("Last>"): - raise ValueError("Missing Last after First") - - for c in range(prev_codepoint + 1, codepoint): - yield Codepoint(c, class_first) - - class_first = None - if name.endswith("First>"): - class_first = class_ - - yield Codepoint(codepoint, class_) - prev_codepoint = codepoint - - if class_first is not None: - raise ValueError("Missing Last after First") - - for c in range(prev_codepoint + 1, NUM_CODEPOINTS): - yield Codepoint(c, None) - - -def compress_singletons(singletons): - uppers = [] # (upper, # items in lowers) - lowers = [] - - for i in singletons: - upper = i >> 8 - lower = i & 0xFF - if len(uppers) == 0 or uppers[-1][0] != upper: - uppers.append((upper, 1)) - else: - upper, count = uppers[-1] - uppers[-1] = upper, count + 1 - lowers.append(lower) - - return uppers, lowers - - -def compress_normal(normal): - # lengths 0x00..0x7f are encoded as 00, 01, ..., 7e, 7f - # lengths 0x80..0x7fff are encoded as 80 80, 80 81, ..., ff fe, ff ff - compressed = [] # [truelen, (truelenaux), falselen, (falselenaux)] - - prev_start = 0 - for start, count in normal: - truelen = start - prev_start - falselen = count - prev_start = start + count - - assert truelen < 0x8000 and falselen < 0x8000 - entry = [] - if truelen > 0x7F: - entry.append(0x80 | (truelen >> 8)) - entry.append(truelen & 0xFF) - else: - entry.append(truelen & 0x7F) - if falselen > 0x7F: - entry.append(0x80 | (falselen >> 8)) - entry.append(falselen & 0xFF) - else: - entry.append(falselen & 0x7F) - - compressed.append(entry) - - return compressed - - -def print_singletons(uppers, lowers, uppersname, lowersname): - print("#[rustfmt::skip]") - print("const {}: &[(u8, u8)] = &[".format(uppersname)) - for u, c in uppers: - print(" ({:#04x}, {}),".format(u, c)) - print("];") - print("#[rustfmt::skip]") - print("const {}: &[u8] = &[".format(lowersname)) - for i in range(0, len(lowers), 8): - print( - " {}".format(" ".join("{:#04x},".format(x) for x in lowers[i : i + 8])) - ) - print("];") - - -def print_normal(normal, normalname): - print("#[rustfmt::skip]") - print("const {}: &[u8] = &[".format(normalname)) - for v in normal: - print(" {}".format(" ".join("{:#04x},".format(i) for i in v))) - print("];") - - -def main(): - file = get_file("https://www.unicode.org/Public/UNIDATA/UnicodeData.txt") - - codepoints = get_codepoints(file) - - CUTOFF = 0x10000 - singletons0 = [] - singletons1 = [] - normal0 = [] - normal1 = [] - extra = [] - - for a, b in to_ranges(get_escaped(codepoints)): - if a > 2 * CUTOFF: - extra.append((a, b - a)) - elif a == b - 1: - if a & CUTOFF: - singletons1.append(a & ~CUTOFF) - else: - singletons0.append(a) - elif a == b - 2: - if a & CUTOFF: - singletons1.append(a & ~CUTOFF) - singletons1.append((a + 1) & ~CUTOFF) - else: - singletons0.append(a) - singletons0.append(a + 1) - else: - if a >= 2 * CUTOFF: - extra.append((a, b - a)) - elif a & CUTOFF: - normal1.append((a & ~CUTOFF, b - a)) - else: - normal0.append((a, b - a)) - - singletons0u, singletons0l = compress_singletons(singletons0) - singletons1u, singletons1l = compress_singletons(singletons1) - normal0 = compress_normal(normal0) - normal1 = compress_normal(normal1) - - print("""\ -// NOTE: The following code was generated by "library/core/src/unicode/printable.py", -// do not edit directly! - -fn check(x: u16, singletonuppers: &[(u8, u8)], singletonlowers: &[u8], normal: &[u8]) -> bool { - let xupper = (x >> 8) as u8; - let mut lowerstart = 0; - for &(upper, lowercount) in singletonuppers { - let lowerend = lowerstart + lowercount as usize; - if xupper == upper { - for &lower in &singletonlowers[lowerstart..lowerend] { - if lower == x as u8 { - return false; - } - } - } else if xupper < upper { - break; - } - lowerstart = lowerend; - } - - let mut x = x as i32; - let mut normal = normal.iter().cloned(); - let mut current = true; - while let Some(v) = normal.next() { - let len = if v & 0x80 != 0 { - ((v & 0x7f) as i32) << 8 | normal.next().unwrap() as i32 - } else { - v as i32 - }; - x -= len; - if x < 0 { - break; - } - current = !current; - } - current -} - -pub(crate) fn is_printable(x: char) -> bool { - let x = x as u32; - let lower = x as u16; - - if x < 32 { - // ASCII fast path - false - } else if x < 127 { - // ASCII fast path - true - } else if x < 0x10000 { - check(lower, SINGLETONS0U, SINGLETONS0L, NORMAL0) - } else if x < 0x20000 { - check(lower, SINGLETONS1U, SINGLETONS1L, NORMAL1) - } else {\ -""") - for a, b in extra: - print(" if 0x{:x} <= x && x < 0x{:x} {{".format(a, a + b)) - print(" return false;") - print(" }") - print("""\ - true - } -}\ -""") - print() - print_singletons(singletons0u, singletons0l, "SINGLETONS0U", "SINGLETONS0L") - print_singletons(singletons1u, singletons1l, "SINGLETONS1U", "SINGLETONS1L") - print_normal(normal0, "NORMAL0") - print_normal(normal1, "NORMAL1") - - -if __name__ == "__main__": - main() diff --git a/library/core/src/unicode/printable.rs b/library/core/src/unicode/printable.rs deleted file mode 100644 index 68e1c8ae31c06..0000000000000 --- a/library/core/src/unicode/printable.rs +++ /dev/null @@ -1,608 +0,0 @@ -// NOTE: The following code was generated by "library/core/src/unicode/printable.py", -// do not edit directly! - -fn check(x: u16, singletonuppers: &[(u8, u8)], singletonlowers: &[u8], normal: &[u8]) -> bool { - let xupper = (x >> 8) as u8; - let mut lowerstart = 0; - for &(upper, lowercount) in singletonuppers { - let lowerend = lowerstart + lowercount as usize; - if xupper == upper { - for &lower in &singletonlowers[lowerstart..lowerend] { - if lower == x as u8 { - return false; - } - } - } else if xupper < upper { - break; - } - lowerstart = lowerend; - } - - let mut x = x as i32; - let mut normal = normal.iter().cloned(); - let mut current = true; - while let Some(v) = normal.next() { - let len = if v & 0x80 != 0 { - ((v & 0x7f) as i32) << 8 | normal.next().unwrap() as i32 - } else { - v as i32 - }; - x -= len; - if x < 0 { - break; - } - current = !current; - } - current -} - -pub(crate) fn is_printable(x: char) -> bool { - let x = x as u32; - let lower = x as u16; - - if x < 32 { - // ASCII fast path - false - } else if x < 127 { - // ASCII fast path - true - } else if x < 0x10000 { - check(lower, SINGLETONS0U, SINGLETONS0L, NORMAL0) - } else if x < 0x20000 { - check(lower, SINGLETONS1U, SINGLETONS1L, NORMAL1) - } else { - if 0x2a6e0 <= x && x < 0x2a700 { - return false; - } - if 0x2b81e <= x && x < 0x2b820 { - return false; - } - if 0x2ceae <= x && x < 0x2ceb0 { - return false; - } - if 0x2ebe1 <= x && x < 0x2ebf0 { - return false; - } - if 0x2ee5e <= x && x < 0x2f800 { - return false; - } - if 0x2fa1e <= x && x < 0x30000 { - return false; - } - if 0x3134b <= x && x < 0x31350 { - return false; - } - if 0x3347a <= x && x < 0xe0100 { - return false; - } - if 0xe01f0 <= x && x < 0x110000 { - return false; - } - true - } -} - -#[rustfmt::skip] -const SINGLETONS0U: &[(u8, u8)] = &[ - (0x00, 1), - (0x03, 5), - (0x05, 6), - (0x06, 2), - (0x07, 6), - (0x08, 7), - (0x09, 17), - (0x0a, 28), - (0x0b, 25), - (0x0c, 25), - (0x0d, 16), - (0x0e, 12), - (0x0f, 4), - (0x10, 3), - (0x12, 18), - (0x13, 9), - (0x16, 1), - (0x17, 4), - (0x18, 1), - (0x19, 3), - (0x1a, 9), - (0x1b, 1), - (0x1c, 2), - (0x1f, 22), - (0x20, 3), - (0x2b, 2), - (0x2d, 11), - (0x2e, 1), - (0x30, 4), - (0x31, 2), - (0x32, 1), - (0xa9, 2), - (0xaa, 4), - (0xab, 8), - (0xfa, 2), - (0xfb, 5), - (0xfe, 3), - (0xff, 9), -]; -#[rustfmt::skip] -const SINGLETONS0L: &[u8] = &[ - 0xad, 0x78, 0x79, 0x8b, 0x8d, 0xa2, 0x30, 0x57, - 0x58, 0x8b, 0x8c, 0x90, 0x1c, 0xdd, 0x0e, 0x0f, - 0x4b, 0x4c, 0xfb, 0xfc, 0x2e, 0x2f, 0x3f, 0x5c, - 0x5d, 0x5f, 0xe2, 0x84, 0x8d, 0x8e, 0x91, 0x92, - 0xa9, 0xb1, 0xba, 0xbb, 0xc5, 0xc6, 0xc9, 0xca, - 0xde, 0xe4, 0xe5, 0xff, 0x00, 0x04, 0x11, 0x12, - 0x29, 0x31, 0x34, 0x37, 0x3a, 0x3b, 0x3d, 0x49, - 0x4a, 0x5d, 0x84, 0x8e, 0x92, 0xa9, 0xb1, 0xb4, - 0xba, 0xbb, 0xc6, 0xca, 0xce, 0xcf, 0xe4, 0xe5, - 0x00, 0x04, 0x0d, 0x0e, 0x11, 0x12, 0x29, 0x31, - 0x34, 0x3a, 0x3b, 0x45, 0x46, 0x49, 0x4a, 0x5e, - 0x64, 0x65, 0x84, 0x91, 0x9b, 0x9d, 0xc9, 0xce, - 0xcf, 0x0d, 0x11, 0x29, 0x3a, 0x3b, 0x45, 0x49, - 0x57, 0x5b, 0x5e, 0x5f, 0x64, 0x65, 0x8d, 0x91, - 0xa9, 0xb4, 0xba, 0xbb, 0xc5, 0xc9, 0xdf, 0xe4, - 0xe5, 0xf0, 0x0d, 0x11, 0x45, 0x49, 0x64, 0x65, - 0x80, 0x84, 0xb2, 0xbc, 0xbe, 0xbf, 0xd5, 0xd7, - 0xf0, 0xf1, 0x83, 0x85, 0x8b, 0xa4, 0xa6, 0xbe, - 0xbf, 0xc5, 0xc7, 0xcf, 0xda, 0xdb, 0x48, 0x98, - 0xbd, 0xcd, 0xc6, 0xce, 0xcf, 0x49, 0x4e, 0x4f, - 0x57, 0x59, 0x5e, 0x5f, 0x89, 0x8e, 0x8f, 0xb1, - 0xb6, 0xb7, 0xbf, 0xc1, 0xc6, 0xc7, 0xd7, 0x11, - 0x16, 0x17, 0x5b, 0x5c, 0xf6, 0xf7, 0xfe, 0xff, - 0x80, 0x6d, 0x71, 0xde, 0xdf, 0x0e, 0x1f, 0x6e, - 0x6f, 0x1c, 0x1d, 0x5f, 0x7d, 0x7e, 0xae, 0xaf, - 0xde, 0xdf, 0x4d, 0xbb, 0xbc, 0x16, 0x17, 0x1e, - 0x1f, 0x46, 0x47, 0x4e, 0x4f, 0x58, 0x5a, 0x5c, - 0x5e, 0x7e, 0x7f, 0xb5, 0xc5, 0xd4, 0xd5, 0xdc, - 0xf0, 0xf1, 0xf5, 0x72, 0x73, 0x8f, 0x74, 0x75, - 0x26, 0x2e, 0x2f, 0xa7, 0xaf, 0xb7, 0xbf, 0xc7, - 0xcf, 0xd7, 0xdf, 0x9a, 0x00, 0x40, 0x97, 0x98, - 0x30, 0x8f, 0x1f, 0xce, 0xff, 0x4e, 0x4f, 0x5a, - 0x5b, 0x07, 0x08, 0x0f, 0x10, 0x27, 0x2f, 0xee, - 0xef, 0x6e, 0x6f, 0x37, 0x3d, 0x3f, 0x42, 0x45, - 0x53, 0x67, 0x75, 0xc8, 0xc9, 0xd0, 0xd1, 0xd8, - 0xd9, 0xe7, 0xfe, 0xff, -]; -#[rustfmt::skip] -const SINGLETONS1U: &[(u8, u8)] = &[ - (0x00, 6), - (0x01, 1), - (0x03, 1), - (0x04, 2), - (0x05, 7), - (0x07, 2), - (0x08, 8), - (0x09, 2), - (0x0a, 5), - (0x0b, 2), - (0x0e, 4), - (0x10, 1), - (0x11, 2), - (0x12, 5), - (0x13, 28), - (0x14, 1), - (0x15, 2), - (0x17, 2), - (0x19, 13), - (0x1c, 5), - (0x1d, 8), - (0x1f, 1), - (0x24, 1), - (0x6a, 4), - (0x6b, 2), - (0x6e, 2), - (0xaf, 3), - (0xb1, 2), - (0xbc, 2), - (0xcf, 2), - (0xd1, 2), - (0xd4, 12), - (0xd5, 9), - (0xd6, 2), - (0xd7, 2), - (0xda, 1), - (0xe0, 5), - (0xe1, 2), - (0xe6, 1), - (0xe7, 4), - (0xe8, 2), - (0xee, 32), - (0xf0, 4), - (0xf8, 2), - (0xfa, 5), - (0xfb, 1), -]; -#[rustfmt::skip] -const SINGLETONS1L: &[u8] = &[ - 0x0c, 0x27, 0x3b, 0x3e, 0x4e, 0x4f, 0x8f, 0x9e, - 0x9e, 0x9f, 0x7b, 0x8b, 0x93, 0x96, 0xa2, 0xb2, - 0xba, 0x86, 0xb1, 0x06, 0x07, 0x09, 0x36, 0x3d, - 0x3e, 0x56, 0xf3, 0xd0, 0xd1, 0x04, 0x14, 0x18, - 0x36, 0x37, 0x56, 0x57, 0x7f, 0xaa, 0xae, 0xaf, - 0xbd, 0x35, 0xe0, 0x12, 0x87, 0x89, 0x8e, 0x9e, - 0x04, 0x0d, 0x0e, 0x11, 0x12, 0x29, 0x31, 0x34, - 0x3a, 0x45, 0x46, 0x49, 0x4a, 0x4e, 0x4f, 0x64, - 0x65, 0x8a, 0x8c, 0x8d, 0x8f, 0xb6, 0xc1, 0xc3, - 0xc4, 0xc6, 0xcb, 0xd6, 0x5c, 0xb6, 0xb7, 0x1b, - 0x1c, 0x07, 0x08, 0x0a, 0x0b, 0x14, 0x17, 0x36, - 0x39, 0x3a, 0xa8, 0xa9, 0xd8, 0xd9, 0x09, 0x37, - 0x90, 0x91, 0xa8, 0x07, 0x0a, 0x3b, 0x3e, 0x66, - 0x69, 0x8f, 0x92, 0x11, 0x6f, 0x5f, 0xbf, 0xee, - 0xef, 0x5a, 0x62, 0xb9, 0xba, 0xf4, 0xfc, 0xff, - 0x53, 0x54, 0x9a, 0x9b, 0x2e, 0x2f, 0x27, 0x28, - 0x55, 0x9d, 0xa0, 0xa1, 0xa3, 0xa4, 0xa7, 0xa8, - 0xad, 0xba, 0xbc, 0xc4, 0x06, 0x0b, 0x0c, 0x15, - 0x1d, 0x3a, 0x3f, 0x45, 0x51, 0xa6, 0xa7, 0xcc, - 0xcd, 0xa0, 0x07, 0x19, 0x1a, 0x22, 0x25, 0x3e, - 0x3f, 0xdf, 0xe7, 0xec, 0xef, 0xff, 0xc5, 0xc6, - 0x04, 0x20, 0x23, 0x25, 0x26, 0x28, 0x33, 0x38, - 0x3a, 0x48, 0x4a, 0x4c, 0x50, 0x53, 0x55, 0x56, - 0x58, 0x5a, 0x5c, 0x5e, 0x60, 0x63, 0x65, 0x66, - 0x6b, 0x73, 0x78, 0x7d, 0x7f, 0x8a, 0xa4, 0xaa, - 0xaf, 0xb0, 0xc0, 0xd0, 0xae, 0xaf, 0x6e, 0x6f, - 0xc7, 0xdd, 0xde, 0x93, -]; -#[rustfmt::skip] -const NORMAL0: &[u8] = &[ - 0x00, 0x20, - 0x5f, 0x22, - 0x82, 0xdf, 0x04, - 0x82, 0x44, 0x08, - 0x1b, 0x04, - 0x06, 0x11, - 0x81, 0xac, 0x0e, - 0x80, 0xab, 0x05, - 0x20, 0x07, - 0x81, 0x1c, 0x03, - 0x19, 0x08, - 0x01, 0x04, - 0x2f, 0x04, - 0x34, 0x04, - 0x07, 0x03, - 0x01, 0x07, - 0x06, 0x07, - 0x11, 0x0a, - 0x50, 0x0f, - 0x12, 0x07, - 0x55, 0x07, - 0x03, 0x04, - 0x1c, 0x0a, - 0x09, 0x03, - 0x08, 0x03, - 0x07, 0x03, - 0x02, 0x03, - 0x03, 0x03, - 0x0c, 0x04, - 0x05, 0x03, - 0x0b, 0x06, - 0x01, 0x0e, - 0x15, 0x05, - 0x4e, 0x07, - 0x1b, 0x07, - 0x57, 0x07, - 0x02, 0x05, - 0x18, 0x0c, - 0x50, 0x04, - 0x43, 0x03, - 0x2d, 0x03, - 0x01, 0x04, - 0x11, 0x06, - 0x0f, 0x0c, - 0x3a, 0x04, - 0x1d, 0x25, - 0x5f, 0x20, - 0x6d, 0x04, - 0x6a, 0x25, - 0x80, 0xc8, 0x05, - 0x82, 0xb0, 0x03, - 0x1a, 0x06, - 0x82, 0xfd, 0x03, - 0x59, 0x07, - 0x16, 0x09, - 0x18, 0x09, - 0x14, 0x0c, - 0x14, 0x0c, - 0x6a, 0x06, - 0x0a, 0x06, - 0x1a, 0x06, - 0x59, 0x07, - 0x2b, 0x05, - 0x46, 0x0a, - 0x2c, 0x04, - 0x0c, 0x04, - 0x01, 0x03, - 0x31, 0x0b, - 0x2c, 0x04, - 0x1a, 0x06, - 0x0b, 0x03, - 0x80, 0xac, 0x06, - 0x0a, 0x06, - 0x4c, 0x14, - 0x80, 0xf4, 0x08, - 0x3c, 0x03, - 0x0f, 0x03, - 0x3e, 0x05, - 0x38, 0x08, - 0x2b, 0x05, - 0x82, 0xff, 0x11, - 0x18, 0x08, - 0x2f, 0x11, - 0x2d, 0x03, - 0x22, 0x0e, - 0x21, 0x0f, - 0x80, 0x8c, 0x04, - 0x82, 0x9a, 0x16, - 0x0b, 0x15, - 0x88, 0x94, 0x05, - 0x2f, 0x05, - 0x3b, 0x07, - 0x02, 0x0e, - 0x18, 0x09, - 0x80, 0xbe, 0x22, - 0x74, 0x0c, - 0x80, 0xd6, 0x1a, - 0x81, 0x10, 0x05, - 0x80, 0xe1, 0x09, - 0xf2, 0x9e, 0x03, - 0x37, 0x09, - 0x81, 0x5c, 0x14, - 0x80, 0xb8, 0x08, - 0x80, 0xdd, 0x14, - 0x3c, 0x03, - 0x0a, 0x06, - 0x38, 0x08, - 0x46, 0x08, - 0x0c, 0x06, - 0x74, 0x0b, - 0x1e, 0x03, - 0x5a, 0x04, - 0x59, 0x09, - 0x80, 0x83, 0x18, - 0x1c, 0x0a, - 0x16, 0x09, - 0x4c, 0x04, - 0x80, 0x8a, 0x06, - 0xab, 0xa4, 0x0c, - 0x17, 0x04, - 0x31, 0xa1, 0x04, - 0x81, 0xda, 0x26, - 0x07, 0x0c, - 0x05, 0x05, - 0x82, 0xb3, 0x20, - 0x2a, 0x06, - 0x4c, 0x04, - 0x80, 0x8d, 0x04, - 0x80, 0xbe, 0x03, - 0x1b, 0x03, - 0x0f, 0x0d, -]; -#[rustfmt::skip] -const NORMAL1: &[u8] = &[ - 0x5e, 0x22, - 0x7b, 0x05, - 0x03, 0x04, - 0x2d, 0x03, - 0x66, 0x03, - 0x01, 0x2f, - 0x2e, 0x80, 0x82, - 0x1d, 0x03, - 0x31, 0x0f, - 0x1c, 0x04, - 0x24, 0x09, - 0x1e, 0x05, - 0x2b, 0x05, - 0x44, 0x04, - 0x0e, 0x2a, - 0x80, 0xaa, 0x06, - 0x24, 0x04, - 0x24, 0x04, - 0x28, 0x08, - 0x34, 0x0b, - 0x4e, 0x03, - 0x34, 0x0c, - 0x81, 0x37, 0x09, - 0x16, 0x0a, - 0x08, 0x18, - 0x3b, 0x45, - 0x39, 0x03, - 0x63, 0x08, - 0x09, 0x30, - 0x16, 0x05, - 0x21, 0x03, - 0x1b, 0x05, - 0x1b, 0x26, - 0x38, 0x04, - 0x4b, 0x05, - 0x2f, 0x04, - 0x0a, 0x07, - 0x09, 0x07, - 0x40, 0x20, - 0x27, 0x04, - 0x0c, 0x09, - 0x36, 0x03, - 0x3a, 0x05, - 0x1a, 0x07, - 0x04, 0x0c, - 0x07, 0x50, - 0x49, 0x37, - 0x33, 0x0d, - 0x33, 0x07, - 0x2e, 0x08, - 0x0a, 0x06, - 0x26, 0x03, - 0x1d, 0x08, - 0x02, 0x80, 0xd0, - 0x52, 0x10, - 0x06, 0x08, - 0x09, 0x21, - 0x2e, 0x08, - 0x2a, 0x16, - 0x1a, 0x26, - 0x1c, 0x14, - 0x17, 0x09, - 0x4e, 0x04, - 0x24, 0x09, - 0x44, 0x0d, - 0x19, 0x07, - 0x0a, 0x06, - 0x48, 0x08, - 0x27, 0x09, - 0x75, 0x0b, - 0x42, 0x3e, - 0x2a, 0x06, - 0x3b, 0x05, - 0x0a, 0x06, - 0x51, 0x06, - 0x01, 0x05, - 0x10, 0x03, - 0x05, 0x0b, - 0x59, 0x08, - 0x02, 0x1d, - 0x62, 0x1e, - 0x48, 0x08, - 0x0a, 0x80, 0xa6, - 0x5e, 0x22, - 0x45, 0x0b, - 0x0a, 0x06, - 0x0d, 0x13, - 0x3a, 0x06, - 0x0a, 0x06, - 0x14, 0x1c, - 0x2c, 0x04, - 0x17, 0x80, 0xb9, - 0x3c, 0x64, - 0x53, 0x0c, - 0x48, 0x09, - 0x0a, 0x46, - 0x45, 0x1b, - 0x48, 0x08, - 0x53, 0x0d, - 0x49, 0x07, - 0x0a, 0x56, - 0x08, 0x58, - 0x22, 0x0e, - 0x0a, 0x06, - 0x46, 0x0a, - 0x1d, 0x03, - 0x47, 0x49, - 0x37, 0x03, - 0x0e, 0x08, - 0x0a, 0x06, - 0x39, 0x07, - 0x0a, 0x06, - 0x2c, 0x04, - 0x0a, 0x80, 0xf6, - 0x19, 0x07, - 0x3b, 0x03, - 0x1d, 0x55, - 0x01, 0x0f, - 0x32, 0x0d, - 0x83, 0x9b, 0x66, - 0x75, 0x0b, - 0x80, 0xc4, 0x8a, 0x4c, - 0x63, 0x0d, - 0x84, 0x30, 0x10, - 0x16, 0x0a, - 0x8f, 0x9b, 0x05, - 0x82, 0x47, 0x9a, 0xb9, - 0x3a, 0x86, 0xc6, - 0x82, 0x39, 0x07, - 0x2a, 0x04, - 0x5c, 0x06, - 0x26, 0x0a, - 0x46, 0x0a, - 0x28, 0x05, - 0x13, 0x81, 0xb0, - 0x3a, 0x80, 0xc6, - 0x5b, 0x05, - 0x34, 0x2c, - 0x4b, 0x04, - 0x39, 0x07, - 0x11, 0x40, - 0x05, 0x0b, - 0x07, 0x09, - 0x9c, 0xd6, 0x29, - 0x20, 0x61, - 0x73, 0xa1, 0xfd, - 0x81, 0x33, 0x0f, - 0x01, 0x1d, - 0x06, 0x0e, - 0x04, 0x08, - 0x81, 0x8c, 0x89, 0x04, - 0x6b, 0x05, - 0x0d, 0x03, - 0x09, 0x07, - 0x10, 0x8f, 0x60, - 0x80, 0xfd, 0x03, - 0x81, 0xb4, 0x06, - 0x17, 0x0f, - 0x11, 0x0f, - 0x47, 0x09, - 0x74, 0x3c, - 0x80, 0xf6, 0x0a, - 0x73, 0x08, - 0x70, 0x15, - 0x46, 0x7a, - 0x14, 0x0c, - 0x14, 0x0c, - 0x57, 0x09, - 0x19, 0x80, 0x87, - 0x81, 0x47, 0x03, - 0x85, 0x42, 0x0f, - 0x15, 0x84, 0x50, - 0x1f, 0x06, - 0x06, 0x80, 0xd5, - 0x2b, 0x05, - 0x3e, 0x21, - 0x01, 0x70, - 0x2d, 0x03, - 0x1a, 0x04, - 0x02, 0x81, 0x40, - 0x1f, 0x11, - 0x3a, 0x05, - 0x01, 0x81, 0xd0, - 0x2a, 0x80, 0xd6, - 0x2b, 0x04, - 0x01, 0x80, 0xc0, - 0x36, 0x08, - 0x02, 0x80, 0xe0, - 0x80, 0xf7, 0x29, - 0x4c, 0x04, - 0x0a, 0x04, - 0x02, 0x83, 0x11, - 0x44, 0x4c, - 0x3d, 0x80, 0xc2, - 0x3c, 0x06, - 0x01, 0x04, - 0x55, 0x05, - 0x1b, 0x34, - 0x02, 0x81, 0x0e, - 0x2c, 0x04, - 0x64, 0x0c, - 0x56, 0x0a, - 0x80, 0xae, 0x38, - 0x1d, 0x0d, - 0x2c, 0x04, - 0x09, 0x07, - 0x02, 0x0e, - 0x06, 0x80, 0x9a, - 0x83, 0xd9, 0x03, - 0x11, 0x03, - 0x0d, 0x03, - 0x80, 0xda, 0x06, - 0x0c, 0x04, - 0x01, 0x0f, - 0x0c, 0x04, - 0x38, 0x08, - 0x0a, 0x06, - 0x28, 0x08, - 0x2c, 0x04, - 0x02, 0x0e, - 0x09, 0x27, - 0x81, 0x58, 0x08, - 0x1d, 0x03, - 0x0b, 0x03, - 0x3b, 0x04, - 0x1e, 0x04, - 0x0a, 0x07, - 0x80, 0xfb, 0x84, 0x05, -]; diff --git a/library/core/src/unicode/unicode_data.rs b/library/core/src/unicode/unicode_data.rs index 429b60a68f439..ca3a276b89d90 100644 --- a/library/core/src/unicode/unicode_data.rs +++ b/library/core/src/unicode/unicode_data.rs @@ -1,15 +1,20 @@ //! This file is generated by `./x run src/tools/unicode-table-generator`; do not edit manually! -// Alphabetic : 1723 bytes, 147369 codepoints in 759 ranges (U+0000AA - U+03347A) using skiplist -// Case_Ignorable : 1063 bytes, 2789 codepoints in 459 ranges (U+0000A8 - U+0E01F0) using skiplist -// Cased : 401 bytes, 4580 codepoints in 156 ranges (U+0000AA - U+01F18A) using skiplist -// Grapheme_Extend : 899 bytes, 2232 codepoints in 383 ranges (U+000300 - U+0E01F0) using skiplist -// Lowercase : 943 bytes, 2569 codepoints in 676 ranges (U+0000AA - U+01E944) using bitset -// N : 463 bytes, 1914 codepoints in 145 ranges (U+0000B2 - U+01FBFA) using skiplist -// Uppercase : 799 bytes, 1980 codepoints in 659 ranges (U+0000C0 - U+01F18A) using bitset -// White_Space : 256 bytes, 19 codepoints in 8 ranges (U+000085 - U+003001) using cascading -// to_lower : 11708 bytes -// to_upper : 13656 bytes -// Total : 31911 bytes +// Alphabetic : 1723 bytes, 147369 codepoints in 759 ranges (U+0000AA - U+03347A) using skiplist +// Case_Ignorable : 1063 bytes, 2789 codepoints in 459 ranges (U+0000A8 - U+0E01F0) using skiplist +// Cf : 87 bytes, 170 codepoints in 21 ranges (U+0000AD - U+0E0080) using skiplist +// Cn_Planes_0_3 : 1677 bytes, 94165 codepoints in 730 ranges (U+000378 - U+03FFFE) using skiplist +// Default_Ignorable_Code_Point: 83 bytes, 4174 codepoints in 17 ranges (U+0000AD - U+0E1000) using skiplist +// Grapheme_Extend : 899 bytes, 2232 codepoints in 383 ranges (U+000300 - U+0E01F0) using skiplist +// Lowercase : 943 bytes, 2569 codepoints in 676 ranges (U+0000AA - U+01E944) using bitset +// Lt : 33 bytes, 31 codepoints in 10 ranges (U+0001C5 - U+001FFD) using skiplist +// N : 463 bytes, 1914 codepoints in 145 ranges (U+0000B2 - U+01FBFA) using skiplist +// Uppercase : 799 bytes, 1980 codepoints in 659 ranges (U+0000C0 - U+01F18A) using bitset +// White_Space : 256 bytes, 19 codepoints in 8 ranges (U+000085 - U+003001) using cascading +// to_lower : 1112 bytes, 1462 codepoints in 185 ranges (U+0000C0 - U+01E921) using 2-level LUT +// to_upper : 1998 bytes, 1554 codepoints in 299 ranges (U+0000B5 - U+01E943) using 2-level LUT +// to_title : 340 bytes, 135 codepoints in 49 ranges (U+0000DF - U+00FB17) using 2-level LUT +// to_casefold : 32 bytes, 174 codepoints in 5 ranges (U+000131 - U+00ABBF) using 2-level LUT +// Total : 11508 bytes #[inline(always)] const fn bitset_search< @@ -337,40 +342,174 @@ pub mod case_ignorable { } #[rustfmt::skip] -pub mod cased { +pub mod cf { use super::ShortOffsetRunHeader; - static SHORT_OFFSET_RUNS: [ShortOffsetRunHeader; 22] = [ - ShortOffsetRunHeader::new(0, 4256), ShortOffsetRunHeader::new(51, 5024), - ShortOffsetRunHeader::new(61, 7296), ShortOffsetRunHeader::new(65, 7958), - ShortOffsetRunHeader::new(74, 9398), ShortOffsetRunHeader::new(149, 11264), - ShortOffsetRunHeader::new(151, 42560), ShortOffsetRunHeader::new(163, 43824), - ShortOffsetRunHeader::new(177, 64256), ShortOffsetRunHeader::new(183, 65313), - ShortOffsetRunHeader::new(187, 66560), ShortOffsetRunHeader::new(191, 67456), - ShortOffsetRunHeader::new(213, 68736), ShortOffsetRunHeader::new(221, 71840), - ShortOffsetRunHeader::new(229, 93760), ShortOffsetRunHeader::new(231, 119808), - ShortOffsetRunHeader::new(237, 120486), ShortOffsetRunHeader::new(274, 122624), - ShortOffsetRunHeader::new(297, 122928), ShortOffsetRunHeader::new(303, 125184), - ShortOffsetRunHeader::new(305, 127280), ShortOffsetRunHeader::new(307, 1241482), + static SHORT_OFFSET_RUNS: [ShortOffsetRunHeader; 11] = [ + ShortOffsetRunHeader::new(0, 1536), ShortOffsetRunHeader::new(3, 2192), + ShortOffsetRunHeader::new(11, 6158), ShortOffsetRunHeader::new(15, 8203), + ShortOffsetRunHeader::new(17, 65279), ShortOffsetRunHeader::new(25, 69821), + ShortOffsetRunHeader::new(29, 78896), ShortOffsetRunHeader::new(33, 113824), + ShortOffsetRunHeader::new(35, 119155), ShortOffsetRunHeader::new(37, 917505), + ShortOffsetRunHeader::new(39, 2031744), ]; - static OFFSETS: [u8; 313] = [ - 170, 1, 10, 1, 4, 1, 5, 23, 1, 31, 1, 195, 1, 4, 4, 208, 2, 35, 7, 2, 30, 5, 96, 1, 42, 4, - 2, 2, 2, 4, 1, 1, 6, 1, 1, 3, 1, 1, 1, 20, 1, 83, 1, 139, 8, 166, 1, 38, 9, 41, 0, 38, 1, 1, - 5, 1, 2, 43, 1, 4, 0, 86, 2, 6, 0, 11, 5, 43, 2, 3, 64, 192, 64, 0, 2, 6, 2, 38, 2, 6, 2, 8, - 1, 1, 1, 1, 1, 1, 1, 31, 2, 53, 1, 7, 1, 1, 3, 3, 1, 7, 3, 4, 2, 6, 4, 13, 5, 3, 1, 7, 116, - 1, 13, 1, 16, 13, 101, 1, 4, 1, 2, 10, 1, 1, 3, 5, 6, 1, 1, 1, 1, 1, 1, 4, 1, 6, 4, 1, 2, 4, - 5, 5, 4, 1, 17, 32, 3, 2, 0, 52, 0, 229, 6, 4, 3, 2, 12, 38, 1, 1, 5, 1, 0, 46, 18, 30, 132, - 102, 3, 4, 1, 77, 20, 6, 1, 3, 0, 43, 1, 14, 6, 80, 0, 7, 12, 5, 0, 26, 6, 26, 0, 80, 96, - 36, 4, 36, 116, 11, 1, 15, 1, 7, 1, 2, 1, 11, 1, 15, 1, 7, 1, 2, 0, 1, 2, 3, 1, 42, 1, 9, 0, - 51, 13, 51, 93, 22, 10, 22, 0, 64, 0, 64, 32, 25, 2, 25, 0, 85, 1, 71, 1, 2, 2, 1, 2, 2, 2, - 4, 1, 12, 1, 1, 1, 7, 1, 65, 1, 4, 2, 8, 1, 7, 1, 28, 1, 4, 1, 5, 1, 1, 3, 7, 1, 0, 2, 25, - 1, 25, 1, 31, 1, 25, 1, 31, 1, 25, 1, 31, 1, 25, 1, 31, 1, 25, 1, 8, 0, 10, 1, 20, 6, 6, 0, - 62, 0, 68, 0, 26, 6, 26, 6, 26, 0, + static OFFSETS: [u8; 43] = [ + 173, 1, 0, 6, 22, 1, 192, 1, 49, 1, 0, 2, 80, 1, 0, 1, 0, 5, 26, 5, 49, 5, 1, 10, 0, 1, + 249, 3, 0, 1, 15, 1, 0, 16, 0, 4, 0, 8, 0, 1, 30, 96, 0, ]; #[inline] pub fn lookup(c: char) -> bool { debug_assert!(!c.is_ascii()); - (c as u32) >= 0xaa && lookup_slow(c) + (c as u32) >= 0xad && lookup_slow(c) + } + + #[inline(never)] + fn lookup_slow(c: char) -> bool { + const { + assert!(SHORT_OFFSET_RUNS.last().unwrap().0 > char::MAX as u32); + let mut i = 0; + while i < SHORT_OFFSET_RUNS.len() { + assert!(SHORT_OFFSET_RUNS[i].start_index() < OFFSETS.len()); + i += 1; + } + } + // SAFETY: We just ensured the last element of `SHORT_OFFSET_RUNS` is greater than `std::char::MAX` + // and the start indices of all elements in `SHORT_OFFSET_RUNS` are smaller than `OFFSETS.len()`. + unsafe { super::skip_search(c, &SHORT_OFFSET_RUNS, &OFFSETS) } + } +} + +#[rustfmt::skip] +pub mod cn_planes_0_3 { + use super::ShortOffsetRunHeader; + + static SHORT_OFFSET_RUNS: [ShortOffsetRunHeader; 54] = [ + ShortOffsetRunHeader::new(0, 888), ShortOffsetRunHeader::new(1, 1328), + ShortOffsetRunHeader::new(11, 1806), ShortOffsetRunHeader::new(25, 4681), + ShortOffsetRunHeader::new(325, 5789), ShortOffsetRunHeader::new(365, 7958), + ShortOffsetRunHeader::new(445, 9258), ShortOffsetRunHeader::new(491, 11124), + ShortOffsetRunHeader::new(495, 11508), ShortOffsetRunHeader::new(497, 42125), + ShortOffsetRunHeader::new(549, 42540), ShortOffsetRunHeader::new(553, 55204), + ShortOffsetRunHeader::new(605, 64110), ShortOffsetRunHeader::new(611, 64976), + ShortOffsetRunHeader::new(629, 67383), ShortOffsetRunHeader::new(735, 74650), + ShortOffsetRunHeader::new(1067, 77712), ShortOffsetRunHeader::new(1074, 78934), + ShortOffsetRunHeader::new(1077, 82939), ShortOffsetRunHeader::new(1079, 83527), + ShortOffsetRunHeader::new(1081, 90368), ShortOffsetRunHeader::new(1082, 92160), + ShortOffsetRunHeader::new(1084, 92729), ShortOffsetRunHeader::new(1085, 93504), + ShortOffsetRunHeader::new(1108, 101590), ShortOffsetRunHeader::new(1127, 110576), + ShortOffsetRunHeader::new(1132, 110883), ShortOffsetRunHeader::new(1139, 111356), + ShortOffsetRunHeader::new(1149, 113664), ShortOffsetRunHeader::new(1150, 117760), + ShortOffsetRunHeader::new(1160, 118452), ShortOffsetRunHeader::new(1163, 120486), + ShortOffsetRunHeader::new(1227, 120780), ShortOffsetRunHeader::new(1229, 121484), + ShortOffsetRunHeader::new(1231, 122624), ShortOffsetRunHeader::new(1236, 123536), + ShortOffsetRunHeader::new(1262, 124112), ShortOffsetRunHeader::new(1268, 126065), + ShortOffsetRunHeader::new(1298, 126976), ShortOffsetRunHeader::new(1370, 128729), + ShortOffsetRunHeader::new(1395, 129624), ShortOffsetRunHeader::new(1423, 131072), + ShortOffsetRunHeader::new(1444, 173792), ShortOffsetRunHeader::new(1445, 178206), + ShortOffsetRunHeader::new(1447, 183982), ShortOffsetRunHeader::new(1449, 191457), + ShortOffsetRunHeader::new(1451, 192094), ShortOffsetRunHeader::new(1453, 194560), + ShortOffsetRunHeader::new(1454, 195102), ShortOffsetRunHeader::new(1455, 196608), + ShortOffsetRunHeader::new(1456, 201547), ShortOffsetRunHeader::new(1457, 210042), + ShortOffsetRunHeader::new(1459, 262142), ShortOffsetRunHeader::new(1460, 1376254), + ]; + static OFFSETS: [u8; 1461] = [ + 0, 2, 6, 4, 7, 1, 1, 1, 20, 1, 0, 1, 38, 2, 50, 2, 3, 1, 55, 8, 27, 4, 6, 11, 0, 1, 60, 2, + 101, 14, 59, 2, 49, 2, 15, 1, 28, 2, 1, 1, 11, 5, 34, 5, 237, 1, 8, 2, 2, 2, 22, 1, 7, 1, 1, + 3, 4, 2, 9, 2, 2, 2, 4, 8, 1, 4, 2, 1, 5, 2, 25, 2, 3, 1, 6, 4, 2, 2, 22, 1, 7, 1, 2, 1, 2, + 1, 2, 2, 1, 1, 5, 4, 2, 2, 3, 3, 1, 7, 4, 1, 1, 7, 17, 10, 3, 1, 9, 1, 3, 1, 22, 1, 7, 1, 2, + 1, 5, 2, 10, 1, 3, 1, 3, 2, 1, 15, 4, 2, 12, 7, 7, 1, 3, 1, 8, 2, 2, 2, 22, 1, 7, 1, 2, 1, + 5, 2, 9, 2, 2, 2, 3, 7, 3, 4, 2, 1, 5, 2, 18, 10, 2, 1, 6, 3, 3, 1, 4, 3, 2, 1, 1, 1, 2, 3, + 2, 3, 3, 3, 12, 4, 5, 3, 3, 1, 4, 2, 1, 6, 1, 14, 21, 5, 13, 1, 3, 1, 23, 1, 16, 2, 9, 1, 3, + 1, 4, 7, 2, 1, 3, 1, 2, 2, 4, 2, 10, 7, 22, 1, 3, 1, 23, 1, 10, 1, 5, 2, 9, 1, 3, 1, 4, 7, + 2, 5, 3, 1, 4, 2, 10, 1, 3, 12, 13, 1, 3, 1, 51, 1, 3, 1, 6, 4, 16, 2, 26, 1, 3, 1, 18, 3, + 24, 1, 9, 1, 1, 2, 7, 3, 1, 4, 6, 1, 1, 1, 8, 6, 10, 2, 3, 12, 58, 4, 29, 37, 2, 1, 1, 1, 5, + 1, 24, 1, 1, 1, 23, 2, 5, 1, 1, 1, 7, 1, 10, 2, 4, 32, 72, 1, 36, 4, 39, 1, 36, 1, 15, 1, + 13, 37, 198, 1, 1, 5, 1, 2, 0, 1, 4, 2, 7, 1, 1, 1, 4, 2, 41, 1, 4, 2, 33, 1, 4, 2, 7, 1, 1, + 1, 4, 2, 15, 1, 57, 1, 4, 2, 67, 2, 32, 3, 26, 6, 86, 2, 6, 2, 0, 3, 89, 7, 22, 9, 24, 9, + 20, 12, 13, 1, 3, 1, 2, 12, 94, 2, 10, 6, 10, 6, 26, 6, 89, 7, 43, 5, 70, 10, 31, 1, 12, 4, + 12, 4, 1, 3, 42, 2, 5, 11, 44, 4, 26, 6, 11, 3, 62, 2, 65, 1, 29, 2, 11, 6, 10, 6, 14, 2, + 46, 2, 12, 20, 77, 1, 166, 8, 60, 3, 15, 3, 62, 5, 43, 2, 11, 8, 43, 5, 0, 2, 6, 2, 38, 2, + 6, 2, 8, 1, 1, 1, 1, 1, 1, 1, 31, 2, 53, 1, 15, 1, 14, 2, 6, 1, 19, 2, 3, 1, 9, 1, 101, 1, + 12, 2, 27, 1, 13, 3, 34, 14, 33, 15, 140, 4, 0, 22, 11, 21, 0, 2, 0, 5, 45, 1, 1, 5, 1, 2, + 56, 7, 2, 14, 24, 9, 7, 1, 7, 1, 7, 1, 7, 1, 7, 1, 7, 1, 7, 1, 7, 1, 126, 34, 26, 1, 89, 12, + 214, 26, 80, 1, 86, 2, 103, 5, 43, 1, 94, 1, 86, 9, 48, 1, 0, 3, 55, 9, 0, 20, 184, 8, 221, + 20, 60, 3, 10, 6, 56, 8, 70, 8, 12, 6, 116, 11, 30, 3, 78, 1, 11, 4, 33, 1, 55, 9, 14, 2, + 10, 2, 103, 24, 28, 10, 6, 2, 6, 2, 6, 9, 7, 1, 7, 1, 60, 4, 126, 2, 10, 6, 0, 12, 23, 4, + 49, 4, 0, 2, 106, 38, 7, 12, 5, 5, 26, 1, 5, 1, 1, 1, 2, 1, 2, 1, 0, 32, 42, 6, 51, 1, 19, + 1, 4, 4, 5, 1, 135, 2, 1, 1, 190, 3, 6, 2, 6, 2, 6, 2, 3, 3, 7, 1, 7, 10, 5, 2, 12, 1, 26, + 1, 19, 1, 2, 1, 15, 2, 14, 34, 123, 5, 3, 4, 45, 3, 88, 1, 13, 3, 1, 47, 46, 130, 29, 3, 49, + 15, 28, 4, 36, 9, 30, 5, 43, 5, 30, 1, 37, 4, 14, 42, 158, 2, 10, 6, 36, 4, 36, 4, 40, 8, + 52, 11, 12, 1, 15, 1, 7, 1, 2, 1, 11, 1, 15, 1, 7, 1, 2, 3, 52, 12, 0, 9, 22, 10, 8, 24, 6, + 1, 42, 1, 9, 69, 6, 2, 1, 1, 44, 1, 2, 3, 1, 2, 23, 1, 72, 8, 9, 48, 19, 1, 2, 5, 33, 3, 27, + 5, 27, 38, 56, 4, 20, 2, 50, 1, 2, 5, 8, 1, 3, 1, 29, 2, 3, 4, 10, 7, 9, 7, 64, 32, 39, 4, + 12, 9, 54, 3, 29, 2, 27, 5, 26, 7, 4, 12, 7, 80, 73, 55, 51, 13, 51, 7, 46, 8, 10, 6, 38, 3, + 29, 8, 2, 208, 31, 1, 42, 1, 3, 2, 2, 16, 6, 8, 9, 33, 46, 8, 42, 22, 26, 38, 28, 20, 23, 9, + 78, 4, 36, 9, 68, 10, 1, 2, 25, 7, 10, 6, 53, 1, 18, 8, 39, 9, 96, 1, 20, 11, 18, 1, 47, 62, + 7, 1, 1, 1, 4, 1, 15, 1, 11, 6, 59, 5, 10, 6, 4, 1, 8, 2, 2, 2, 22, 1, 7, 1, 2, 1, 5, 1, 10, + 2, 2, 2, 3, 2, 1, 6, 1, 5, 7, 2, 7, 3, 5, 11, 10, 1, 1, 2, 1, 1, 38, 1, 10, 1, 1, 2, 1, 1, + 4, 1, 10, 1, 2, 8, 2, 29, 92, 1, 5, 30, 72, 8, 10, 166, 54, 2, 38, 34, 69, 11, 10, 6, 13, + 19, 58, 6, 10, 6, 20, 28, 27, 2, 15, 4, 23, 185, 60, 100, 83, 12, 8, 2, 1, 2, 8, 1, 2, 1, + 30, 1, 2, 2, 12, 9, 10, 70, 8, 2, 46, 2, 11, 27, 72, 8, 83, 13, 73, 7, 10, 86, 8, 88, 34, + 14, 10, 6, 9, 1, 45, 1, 14, 10, 29, 3, 32, 2, 22, 1, 14, 73, 7, 1, 2, 1, 44, 3, 1, 1, 2, 1, + 9, 8, 10, 6, 6, 1, 2, 1, 37, 1, 2, 1, 6, 7, 10, 6, 44, 4, 10, 246, 25, 7, 17, 1, 41, 3, 29, + 85, 1, 15, 50, 13, 0, 102, 111, 1, 5, 11, 196, 0, 99, 13, 0, 10, 0, 5, 0, 0, 58, 0, 0, 7, + 31, 1, 10, 4, 81, 1, 10, 6, 30, 2, 6, 10, 70, 10, 10, 1, 7, 1, 21, 5, 19, 0, 58, 198, 91, 5, + 25, 2, 25, 44, 75, 4, 57, 7, 17, 64, 5, 11, 7, 9, 0, 41, 32, 97, 115, 0, 4, 1, 7, 1, 2, 1, + 0, 15, 1, 29, 3, 2, 1, 14, 4, 8, 0, 0, 107, 5, 13, 3, 9, 7, 10, 2, 8, 0, 253, 3, 0, 6, 23, + 15, 17, 15, 46, 2, 23, 9, 116, 60, 246, 10, 39, 2, 194, 21, 70, 122, 20, 12, 20, 12, 87, 9, + 25, 135, 85, 1, 71, 1, 2, 2, 1, 2, 2, 2, 4, 1, 12, 1, 1, 1, 7, 1, 65, 1, 4, 2, 8, 1, 7, 1, + 28, 1, 4, 1, 5, 1, 1, 3, 7, 1, 0, 2, 0, 2, 0, 15, 5, 1, 15, 0, 31, 6, 6, 213, 7, 1, 17, 2, + 7, 1, 2, 1, 5, 5, 62, 33, 1, 112, 45, 3, 14, 2, 10, 4, 2, 0, 31, 17, 58, 5, 1, 0, 42, 214, + 43, 4, 1, 192, 31, 1, 22, 8, 2, 224, 7, 1, 4, 1, 2, 1, 15, 1, 197, 2, 16, 41, 76, 4, 10, 4, + 2, 0, 68, 76, 61, 194, 4, 1, 27, 1, 2, 1, 1, 2, 1, 1, 10, 1, 4, 1, 1, 1, 1, 6, 1, 4, 1, 1, + 1, 1, 1, 1, 3, 1, 2, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 1, 1, 2, 4, 1, 7, 1, 4, 1, 4, + 1, 1, 1, 10, 1, 17, 5, 3, 1, 5, 1, 17, 52, 2, 0, 44, 4, 100, 12, 15, 2, 15, 1, 15, 1, 37, + 10, 174, 56, 29, 13, 44, 4, 9, 7, 2, 14, 6, 154, 0, 3, 17, 3, 13, 3, 218, 6, 12, 4, 1, 15, + 12, 4, 56, 8, 10, 6, 40, 8, 30, 2, 12, 4, 2, 14, 9, 39, 0, 8, 14, 2, 13, 3, 11, 3, 57, 1, 1, + 4, 16, 2, 12, 4, 10, 7, 147, 1, 103, 0, 0, 32, 0, 2, 0, 2, 0, 15, 0, 0, 0, 0, 0, 5, 0, 0, 0, + ]; + #[inline] + pub fn lookup(c: char) -> bool { + debug_assert!(!c.is_ascii()); + (c as u32) >= 0x378 && lookup_slow(c) + } + + #[inline(never)] + fn lookup_slow(c: char) -> bool { + const { + assert!(SHORT_OFFSET_RUNS.last().unwrap().0 > char::MAX as u32); + let mut i = 0; + while i < SHORT_OFFSET_RUNS.len() { + assert!(SHORT_OFFSET_RUNS[i].start_index() < OFFSETS.len()); + i += 1; + } + } + // SAFETY: We just ensured the last element of `SHORT_OFFSET_RUNS` is greater than `std::char::MAX` + // and the start indices of all elements in `SHORT_OFFSET_RUNS` are smaller than `OFFSETS.len()`. + unsafe { super::skip_search(c, &SHORT_OFFSET_RUNS, &OFFSETS) } + } +} + +#[rustfmt::skip] +pub mod default_ignorable_code_point { + use super::ShortOffsetRunHeader; + + static SHORT_OFFSET_RUNS: [ShortOffsetRunHeader; 12] = [ + ShortOffsetRunHeader::new(0, 847), ShortOffsetRunHeader::new(3, 1564), + ShortOffsetRunHeader::new(5, 4447), ShortOffsetRunHeader::new(7, 6068), + ShortOffsetRunHeader::new(9, 8203), ShortOffsetRunHeader::new(13, 12644), + ShortOffsetRunHeader::new(19, 65024), ShortOffsetRunHeader::new(21, 113824), + ShortOffsetRunHeader::new(29, 119155), ShortOffsetRunHeader::new(31, 917504), + ShortOffsetRunHeader::new(33, 921600), ShortOffsetRunHeader::new(34, 2035712), + ]; + static OFFSETS: [u8; 35] = [ + 173, 1, 0, 1, 0, 1, 0, 2, 0, 2, 85, 5, 0, 5, 26, 5, 49, 16, 0, 1, 0, 16, 239, 1, 160, 1, + 79, 9, 0, 4, 0, 8, 0, 0, 0, + ]; + #[inline] + pub fn lookup(c: char) -> bool { + debug_assert!(!c.is_ascii()); + (c as u32) >= 0xad && lookup_slow(c) } #[inline(never)] @@ -573,6 +712,39 @@ pub mod lowercase { } } +#[rustfmt::skip] +pub mod lt { + use super::ShortOffsetRunHeader; + + static SHORT_OFFSET_RUNS: [ShortOffsetRunHeader; 3] = [ + ShortOffsetRunHeader::new(0, 453), ShortOffsetRunHeader::new(1, 8072), + ShortOffsetRunHeader::new(9, 1122301), + ]; + static OFFSETS: [u8; 21] = [ + 0, 1, 2, 1, 2, 1, 38, 1, 0, 8, 8, 8, 8, 8, 12, 1, 15, 1, 47, 1, 0, + ]; + #[inline] + pub fn lookup(c: char) -> bool { + debug_assert!(!c.is_ascii()); + (c as u32) >= 0x1c5 && lookup_slow(c) + } + + #[inline(never)] + fn lookup_slow(c: char) -> bool { + const { + assert!(SHORT_OFFSET_RUNS.last().unwrap().0 > char::MAX as u32); + let mut i = 0; + while i < SHORT_OFFSET_RUNS.len() { + assert!(SHORT_OFFSET_RUNS[i].start_index() < OFFSETS.len()); + i += 1; + } + } + // SAFETY: We just ensured the last element of `SHORT_OFFSET_RUNS` is greater than `std::char::MAX` + // and the start indices of all elements in `SHORT_OFFSET_RUNS` are smaller than `OFFSETS.len()`. + unsafe { super::skip_search(c, &SHORT_OFFSET_RUNS, &OFFSETS) } + } +} + #[rustfmt::skip] pub mod n { use super::ShortOffsetRunHeader; @@ -758,833 +930,555 @@ pub mod white_space { #[rustfmt::skip] pub mod conversions { - const INDEX_MASK: u32 = 0x400000; + + + use crate::ops::RangeInclusive; + + struct L1Lut { + l2_luts: [L2Lut; 2], + } + + struct L2Lut { + singles: &'static [(Range, i16)], + multis: &'static [(u16, [u16; 3])], + } + + #[derive(Copy, Clone)] + struct Range { + start: u16, + len: u8, + parity: bool, + } + + impl Range { + const fn new(range: RangeInclusive, parity: bool) -> Self { + let start = *range.start(); + let end = *range.end(); + assert!(start <= end); + + let len = end - start; + assert!(len <= 255); + + Self { start, len: len as u8, parity } + } + + const fn singleton(start: u16) -> Self { + Self::new(start..=start, false) + } + + const fn step_by_1(range: RangeInclusive) -> Self { + Self::new(range, false) + } + + const fn step_by_2(range: RangeInclusive) -> Self { + Self::new(range, true) + } + + const fn start(&self) -> u16 { + self.start + } + + const fn end(&self) -> u16 { + self.start + self.len as u16 + } + } + + fn deconstruct(c: char) -> (u16, u16) { + let c = c as u32; + let plane = (c >> 16) as u16; + let low = c as u16; + (plane, low) + } + + unsafe fn reconstruct(plane: u16, low: u16) -> char { + // SAFETY: The caller must ensure that the result is a valid `char`. + unsafe { char::from_u32_unchecked(((plane as u32) << 16) | (low as u32)) } + } + + fn lookup(input: char, l1_lut: &L1Lut) -> Option<[char; 3]> { + let (input_high, input_low) = deconstruct(input); + let Some(l2_lut) = l1_lut.l2_luts.get(input_high as usize) else { + return None; + }; + + let idx = l2_lut.singles.binary_search_by(|(range, _)| { + use crate::cmp::Ordering; + + if input_low < range.start() { + Ordering::Greater + } else if input_low > range.end() { + Ordering::Less + } else { + Ordering::Equal + } + }); + + if let Ok(idx) = idx { + // SAFETY: binary search guarantees that the index is in bounds. + let &(range, output_delta) = unsafe { l2_lut.singles.get_unchecked(idx) }; + let mask = range.parity as u16; + if input_low & mask == range.start() & mask { + let output_low = input_low.wrapping_add_signed(output_delta); + // SAFETY: Table data are guaranteed to be valid Unicode. + let output = unsafe { reconstruct(input_high, output_low) }; + return Some([output, '\0', '\0']); + } + }; + + if let Ok(idx) = l2_lut.multis.binary_search_by_key(&input_low, |&(p, _)| p) { + // SAFETY: binary search guarantees that the index is in bounds. + let &(_, output_lows) = unsafe { l2_lut.multis.get_unchecked(idx) }; + // SAFETY: Table data are guaranteed to be valid Unicode. + let output = output_lows.map(|output_low| unsafe { reconstruct(input_high, output_low) }); + return Some(output); + }; + + None + } pub fn to_lower(c: char) -> [char; 3] { - if c.is_ascii() { - [(c as u8).to_ascii_lowercase() as char, '\0', '\0'] - } else { - LOWERCASE_TABLE - .binary_search_by(|&(key, _)| key.cmp(&c)) - .map(|i| { - // SAFETY: i is the result of the binary search - let u = unsafe { LOWERCASE_TABLE.get_unchecked(i) }.1; - char::from_u32(u).map(|c| [c, '\0', '\0']).unwrap_or_else(|| { - // SAFETY: Index comes from statically generated table - unsafe { *LOWERCASE_TABLE_MULTI.get_unchecked((u & (INDEX_MASK - 1)) as usize) } - }) - }) - .unwrap_or([c, '\0', '\0']) + // https://util.unicode.org/UnicodeJsps/list-unicodeset.jsp?a=[:Changes_When_Lowercased:]-[:ASCII:]&abb=on + if c < '\u{C0}' { + return [c.to_ascii_lowercase(), '\0', '\0']; } + + lookup(c, &LOWERCASE_LUT).unwrap_or([c, '\0', '\0']) } pub fn to_upper(c: char) -> [char; 3] { - if c.is_ascii() { - [(c as u8).to_ascii_uppercase() as char, '\0', '\0'] - } else { - UPPERCASE_TABLE - .binary_search_by(|&(key, _)| key.cmp(&c)) - .map(|i| { - // SAFETY: i is the result of the binary search - let u = unsafe { UPPERCASE_TABLE.get_unchecked(i) }.1; - char::from_u32(u).map(|c| [c, '\0', '\0']).unwrap_or_else(|| { - // SAFETY: Index comes from statically generated table - unsafe { *UPPERCASE_TABLE_MULTI.get_unchecked((u & (INDEX_MASK - 1)) as usize) } - }) - }) - .unwrap_or([c, '\0', '\0']) + // https://util.unicode.org/UnicodeJsps/list-unicodeset.jsp?a=[:Changes_When_Uppercased:]-[:ASCII:]&abb=on + if c < '\u{B5}' { + return [c.to_ascii_uppercase(), '\0', '\0']; } + + lookup(c, &UPPERCASE_LUT).unwrap_or([c, '\0', '\0']) } - static LOWERCASE_TABLE: &[(char, u32); 1462] = &[ - ('\u{c0}', 224), ('\u{c1}', 225), ('\u{c2}', 226), ('\u{c3}', 227), ('\u{c4}', 228), - ('\u{c5}', 229), ('\u{c6}', 230), ('\u{c7}', 231), ('\u{c8}', 232), ('\u{c9}', 233), - ('\u{ca}', 234), ('\u{cb}', 235), ('\u{cc}', 236), ('\u{cd}', 237), ('\u{ce}', 238), - ('\u{cf}', 239), ('\u{d0}', 240), ('\u{d1}', 241), ('\u{d2}', 242), ('\u{d3}', 243), - ('\u{d4}', 244), ('\u{d5}', 245), ('\u{d6}', 246), ('\u{d8}', 248), ('\u{d9}', 249), - ('\u{da}', 250), ('\u{db}', 251), ('\u{dc}', 252), ('\u{dd}', 253), ('\u{de}', 254), - ('\u{100}', 257), ('\u{102}', 259), ('\u{104}', 261), ('\u{106}', 263), ('\u{108}', 265), - ('\u{10a}', 267), ('\u{10c}', 269), ('\u{10e}', 271), ('\u{110}', 273), ('\u{112}', 275), - ('\u{114}', 277), ('\u{116}', 279), ('\u{118}', 281), ('\u{11a}', 283), ('\u{11c}', 285), - ('\u{11e}', 287), ('\u{120}', 289), ('\u{122}', 291), ('\u{124}', 293), ('\u{126}', 295), - ('\u{128}', 297), ('\u{12a}', 299), ('\u{12c}', 301), ('\u{12e}', 303), - ('\u{130}', 4194304), ('\u{132}', 307), ('\u{134}', 309), ('\u{136}', 311), - ('\u{139}', 314), ('\u{13b}', 316), ('\u{13d}', 318), ('\u{13f}', 320), ('\u{141}', 322), - ('\u{143}', 324), ('\u{145}', 326), ('\u{147}', 328), ('\u{14a}', 331), ('\u{14c}', 333), - ('\u{14e}', 335), ('\u{150}', 337), ('\u{152}', 339), ('\u{154}', 341), ('\u{156}', 343), - ('\u{158}', 345), ('\u{15a}', 347), ('\u{15c}', 349), ('\u{15e}', 351), ('\u{160}', 353), - ('\u{162}', 355), ('\u{164}', 357), ('\u{166}', 359), ('\u{168}', 361), ('\u{16a}', 363), - ('\u{16c}', 365), ('\u{16e}', 367), ('\u{170}', 369), ('\u{172}', 371), ('\u{174}', 373), - ('\u{176}', 375), ('\u{178}', 255), ('\u{179}', 378), ('\u{17b}', 380), ('\u{17d}', 382), - ('\u{181}', 595), ('\u{182}', 387), ('\u{184}', 389), ('\u{186}', 596), ('\u{187}', 392), - ('\u{189}', 598), ('\u{18a}', 599), ('\u{18b}', 396), ('\u{18e}', 477), ('\u{18f}', 601), - ('\u{190}', 603), ('\u{191}', 402), ('\u{193}', 608), ('\u{194}', 611), ('\u{196}', 617), - ('\u{197}', 616), ('\u{198}', 409), ('\u{19c}', 623), ('\u{19d}', 626), ('\u{19f}', 629), - ('\u{1a0}', 417), ('\u{1a2}', 419), ('\u{1a4}', 421), ('\u{1a6}', 640), ('\u{1a7}', 424), - ('\u{1a9}', 643), ('\u{1ac}', 429), ('\u{1ae}', 648), ('\u{1af}', 432), ('\u{1b1}', 650), - ('\u{1b2}', 651), ('\u{1b3}', 436), ('\u{1b5}', 438), ('\u{1b7}', 658), ('\u{1b8}', 441), - ('\u{1bc}', 445), ('\u{1c4}', 454), ('\u{1c5}', 454), ('\u{1c7}', 457), ('\u{1c8}', 457), - ('\u{1ca}', 460), ('\u{1cb}', 460), ('\u{1cd}', 462), ('\u{1cf}', 464), ('\u{1d1}', 466), - ('\u{1d3}', 468), ('\u{1d5}', 470), ('\u{1d7}', 472), ('\u{1d9}', 474), ('\u{1db}', 476), - ('\u{1de}', 479), ('\u{1e0}', 481), ('\u{1e2}', 483), ('\u{1e4}', 485), ('\u{1e6}', 487), - ('\u{1e8}', 489), ('\u{1ea}', 491), ('\u{1ec}', 493), ('\u{1ee}', 495), ('\u{1f1}', 499), - ('\u{1f2}', 499), ('\u{1f4}', 501), ('\u{1f6}', 405), ('\u{1f7}', 447), ('\u{1f8}', 505), - ('\u{1fa}', 507), ('\u{1fc}', 509), ('\u{1fe}', 511), ('\u{200}', 513), ('\u{202}', 515), - ('\u{204}', 517), ('\u{206}', 519), ('\u{208}', 521), ('\u{20a}', 523), ('\u{20c}', 525), - ('\u{20e}', 527), ('\u{210}', 529), ('\u{212}', 531), ('\u{214}', 533), ('\u{216}', 535), - ('\u{218}', 537), ('\u{21a}', 539), ('\u{21c}', 541), ('\u{21e}', 543), ('\u{220}', 414), - ('\u{222}', 547), ('\u{224}', 549), ('\u{226}', 551), ('\u{228}', 553), ('\u{22a}', 555), - ('\u{22c}', 557), ('\u{22e}', 559), ('\u{230}', 561), ('\u{232}', 563), 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('\u{16e46}', 93798), ('\u{16e47}', 93799), ('\u{16e48}', 93800), ('\u{16e49}', 93801), - ('\u{16e4a}', 93802), ('\u{16e4b}', 93803), ('\u{16e4c}', 93804), ('\u{16e4d}', 93805), - ('\u{16e4e}', 93806), ('\u{16e4f}', 93807), ('\u{16e50}', 93808), ('\u{16e51}', 93809), - ('\u{16e52}', 93810), ('\u{16e53}', 93811), ('\u{16e54}', 93812), ('\u{16e55}', 93813), - ('\u{16e56}', 93814), ('\u{16e57}', 93815), ('\u{16e58}', 93816), ('\u{16e59}', 93817), - ('\u{16e5a}', 93818), ('\u{16e5b}', 93819), ('\u{16e5c}', 93820), ('\u{16e5d}', 93821), - ('\u{16e5e}', 93822), ('\u{16e5f}', 93823), ('\u{16ea0}', 93883), ('\u{16ea1}', 93884), - ('\u{16ea2}', 93885), ('\u{16ea3}', 93886), ('\u{16ea4}', 93887), ('\u{16ea5}', 93888), - ('\u{16ea6}', 93889), ('\u{16ea7}', 93890), ('\u{16ea8}', 93891), ('\u{16ea9}', 93892), - ('\u{16eaa}', 93893), ('\u{16eab}', 93894), ('\u{16eac}', 93895), ('\u{16ead}', 93896), - ('\u{16eae}', 93897), ('\u{16eaf}', 93898), ('\u{16eb0}', 93899), ('\u{16eb1}', 93900), - ('\u{16eb2}', 93901), ('\u{16eb3}', 93902), ('\u{16eb4}', 93903), ('\u{16eb5}', 93904), - ('\u{16eb6}', 93905), ('\u{16eb7}', 93906), ('\u{16eb8}', 93907), ('\u{1e900}', 125218), - ('\u{1e901}', 125219), ('\u{1e902}', 125220), ('\u{1e903}', 125221), ('\u{1e904}', 125222), - ('\u{1e905}', 125223), ('\u{1e906}', 125224), ('\u{1e907}', 125225), ('\u{1e908}', 125226), - ('\u{1e909}', 125227), ('\u{1e90a}', 125228), ('\u{1e90b}', 125229), ('\u{1e90c}', 125230), - ('\u{1e90d}', 125231), ('\u{1e90e}', 125232), ('\u{1e90f}', 125233), ('\u{1e910}', 125234), - ('\u{1e911}', 125235), ('\u{1e912}', 125236), ('\u{1e913}', 125237), ('\u{1e914}', 125238), - ('\u{1e915}', 125239), ('\u{1e916}', 125240), ('\u{1e917}', 125241), ('\u{1e918}', 125242), - ('\u{1e919}', 125243), ('\u{1e91a}', 125244), ('\u{1e91b}', 125245), ('\u{1e91c}', 125246), - ('\u{1e91d}', 125247), ('\u{1e91e}', 125248), ('\u{1e91f}', 125249), ('\u{1e920}', 125250), - ('\u{1e921}', 125251), - ]; + pub fn to_title(c: char) -> [char; 3] { + // https://util.unicode.org/UnicodeJsps/list-unicodeset.jsp?a=[:Changes_When_Titlecased:]-[:ASCII:]&abb=on + if c < '\u{B5}' { + return [c.to_ascii_uppercase(), '\0', '\0']; + } - static LOWERCASE_TABLE_MULTI: &[[char; 3]; 1] = &[ - ['i', '\u{307}', '\u{0}'], - ]; + lookup(c, &TITLECASE_LUT).or_else(|| lookup(c, &UPPERCASE_LUT)).unwrap_or([c, '\0', '\0']) + } - static UPPERCASE_TABLE: &[(char, u32); 1554] = &[ - ('\u{b5}', 924), ('\u{df}', 4194304), ('\u{e0}', 192), ('\u{e1}', 193), ('\u{e2}', 194), - ('\u{e3}', 195), ('\u{e4}', 196), ('\u{e5}', 197), ('\u{e6}', 198), ('\u{e7}', 199), - ('\u{e8}', 200), ('\u{e9}', 201), ('\u{ea}', 202), ('\u{eb}', 203), ('\u{ec}', 204), - ('\u{ed}', 205), ('\u{ee}', 206), ('\u{ef}', 207), ('\u{f0}', 208), ('\u{f1}', 209), - ('\u{f2}', 210), ('\u{f3}', 211), ('\u{f4}', 212), ('\u{f5}', 213), ('\u{f6}', 214), - ('\u{f8}', 216), ('\u{f9}', 217), ('\u{fa}', 218), ('\u{fb}', 219), ('\u{fc}', 220), - ('\u{fd}', 221), ('\u{fe}', 222), ('\u{ff}', 376), ('\u{101}', 256), ('\u{103}', 258), - ('\u{105}', 260), ('\u{107}', 262), ('\u{109}', 264), ('\u{10b}', 266), ('\u{10d}', 268), - ('\u{10f}', 270), ('\u{111}', 272), ('\u{113}', 274), ('\u{115}', 276), ('\u{117}', 278), - ('\u{119}', 280), ('\u{11b}', 282), ('\u{11d}', 284), ('\u{11f}', 286), ('\u{121}', 288), - ('\u{123}', 290), ('\u{125}', 292), ('\u{127}', 294), ('\u{129}', 296), ('\u{12b}', 298), - ('\u{12d}', 300), ('\u{12f}', 302), ('\u{131}', 73), ('\u{133}', 306), ('\u{135}', 308), - ('\u{137}', 310), ('\u{13a}', 313), ('\u{13c}', 315), ('\u{13e}', 317), ('\u{140}', 319), - ('\u{142}', 321), ('\u{144}', 323), ('\u{146}', 325), ('\u{148}', 327), - ('\u{149}', 4194305), ('\u{14b}', 330), ('\u{14d}', 332), ('\u{14f}', 334), - ('\u{151}', 336), ('\u{153}', 338), ('\u{155}', 340), ('\u{157}', 342), ('\u{159}', 344), - ('\u{15b}', 346), ('\u{15d}', 348), ('\u{15f}', 350), ('\u{161}', 352), ('\u{163}', 354), - ('\u{165}', 356), ('\u{167}', 358), ('\u{169}', 360), ('\u{16b}', 362), ('\u{16d}', 364), - ('\u{16f}', 366), ('\u{171}', 368), ('\u{173}', 370), ('\u{175}', 372), ('\u{177}', 374), - ('\u{17a}', 377), ('\u{17c}', 379), ('\u{17e}', 381), ('\u{17f}', 83), ('\u{180}', 579), - ('\u{183}', 386), ('\u{185}', 388), ('\u{188}', 391), ('\u{18c}', 395), ('\u{192}', 401), - ('\u{195}', 502), ('\u{199}', 408), ('\u{19a}', 573), ('\u{19b}', 42972), ('\u{19e}', 544), - ('\u{1a1}', 416), ('\u{1a3}', 418), ('\u{1a5}', 420), ('\u{1a8}', 423), ('\u{1ad}', 428), - ('\u{1b0}', 431), ('\u{1b4}', 435), ('\u{1b6}', 437), ('\u{1b9}', 440), ('\u{1bd}', 444), - ('\u{1bf}', 503), ('\u{1c5}', 452), ('\u{1c6}', 452), ('\u{1c8}', 455), ('\u{1c9}', 455), - ('\u{1cb}', 458), ('\u{1cc}', 458), ('\u{1ce}', 461), ('\u{1d0}', 463), ('\u{1d2}', 465), - ('\u{1d4}', 467), ('\u{1d6}', 469), ('\u{1d8}', 471), ('\u{1da}', 473), ('\u{1dc}', 475), - ('\u{1dd}', 398), ('\u{1df}', 478), ('\u{1e1}', 480), ('\u{1e3}', 482), ('\u{1e5}', 484), - ('\u{1e7}', 486), ('\u{1e9}', 488), ('\u{1eb}', 490), ('\u{1ed}', 492), ('\u{1ef}', 494), - ('\u{1f0}', 4194306), ('\u{1f2}', 497), ('\u{1f3}', 497), ('\u{1f5}', 500), - ('\u{1f9}', 504), ('\u{1fb}', 506), ('\u{1fd}', 508), ('\u{1ff}', 510), ('\u{201}', 512), - ('\u{203}', 514), ('\u{205}', 516), ('\u{207}', 518), ('\u{209}', 520), ('\u{20b}', 522), - ('\u{20d}', 524), ('\u{20f}', 526), ('\u{211}', 528), ('\u{213}', 530), ('\u{215}', 532), - ('\u{217}', 534), ('\u{219}', 536), ('\u{21b}', 538), ('\u{21d}', 540), ('\u{21f}', 542), - ('\u{223}', 546), ('\u{225}', 548), ('\u{227}', 550), ('\u{229}', 552), ('\u{22b}', 554), - ('\u{22d}', 556), ('\u{22f}', 558), ('\u{231}', 560), ('\u{233}', 562), ('\u{23c}', 571), - ('\u{23f}', 11390), ('\u{240}', 11391), ('\u{242}', 577), ('\u{247}', 582), - ('\u{249}', 584), ('\u{24b}', 586), ('\u{24d}', 588), ('\u{24f}', 590), ('\u{250}', 11375), - ('\u{251}', 11373), ('\u{252}', 11376), ('\u{253}', 385), ('\u{254}', 390), - ('\u{256}', 393), ('\u{257}', 394), ('\u{259}', 399), ('\u{25b}', 400), ('\u{25c}', 42923), - ('\u{260}', 403), ('\u{261}', 42924), ('\u{263}', 404), ('\u{264}', 42955), - ('\u{265}', 42893), ('\u{266}', 42922), ('\u{268}', 407), ('\u{269}', 406), - ('\u{26a}', 42926), ('\u{26b}', 11362), ('\u{26c}', 42925), ('\u{26f}', 412), - ('\u{271}', 11374), ('\u{272}', 413), ('\u{275}', 415), ('\u{27d}', 11364), - ('\u{280}', 422), ('\u{282}', 42949), ('\u{283}', 425), ('\u{287}', 42929), - ('\u{288}', 430), ('\u{289}', 580), ('\u{28a}', 433), ('\u{28b}', 434), ('\u{28c}', 581), - ('\u{292}', 439), ('\u{29d}', 42930), ('\u{29e}', 42928), ('\u{345}', 921), - ('\u{371}', 880), ('\u{373}', 882), ('\u{377}', 886), ('\u{37b}', 1021), ('\u{37c}', 1022), - ('\u{37d}', 1023), ('\u{390}', 4194307), ('\u{3ac}', 902), ('\u{3ad}', 904), - ('\u{3ae}', 905), ('\u{3af}', 906), ('\u{3b0}', 4194308), ('\u{3b1}', 913), - ('\u{3b2}', 914), ('\u{3b3}', 915), ('\u{3b4}', 916), ('\u{3b5}', 917), ('\u{3b6}', 918), - ('\u{3b7}', 919), ('\u{3b8}', 920), ('\u{3b9}', 921), ('\u{3ba}', 922), ('\u{3bb}', 923), - ('\u{3bc}', 924), ('\u{3bd}', 925), ('\u{3be}', 926), ('\u{3bf}', 927), ('\u{3c0}', 928), - ('\u{3c1}', 929), ('\u{3c2}', 931), ('\u{3c3}', 931), ('\u{3c4}', 932), ('\u{3c5}', 933), - ('\u{3c6}', 934), ('\u{3c7}', 935), ('\u{3c8}', 936), ('\u{3c9}', 937), ('\u{3ca}', 938), - ('\u{3cb}', 939), ('\u{3cc}', 908), ('\u{3cd}', 910), ('\u{3ce}', 911), ('\u{3d0}', 914), - ('\u{3d1}', 920), ('\u{3d5}', 934), ('\u{3d6}', 928), ('\u{3d7}', 975), ('\u{3d9}', 984), - ('\u{3db}', 986), ('\u{3dd}', 988), ('\u{3df}', 990), ('\u{3e1}', 992), ('\u{3e3}', 994), - ('\u{3e5}', 996), ('\u{3e7}', 998), ('\u{3e9}', 1000), ('\u{3eb}', 1002), ('\u{3ed}', 1004), - ('\u{3ef}', 1006), ('\u{3f0}', 922), ('\u{3f1}', 929), ('\u{3f2}', 1017), ('\u{3f3}', 895), - ('\u{3f5}', 917), ('\u{3f8}', 1015), ('\u{3fb}', 1018), ('\u{430}', 1040), - ('\u{431}', 1041), ('\u{432}', 1042), ('\u{433}', 1043), ('\u{434}', 1044), - ('\u{435}', 1045), ('\u{436}', 1046), ('\u{437}', 1047), ('\u{438}', 1048), - ('\u{439}', 1049), ('\u{43a}', 1050), ('\u{43b}', 1051), ('\u{43c}', 1052), - ('\u{43d}', 1053), ('\u{43e}', 1054), ('\u{43f}', 1055), ('\u{440}', 1056), - ('\u{441}', 1057), ('\u{442}', 1058), ('\u{443}', 1059), ('\u{444}', 1060), - ('\u{445}', 1061), ('\u{446}', 1062), ('\u{447}', 1063), ('\u{448}', 1064), - ('\u{449}', 1065), ('\u{44a}', 1066), ('\u{44b}', 1067), ('\u{44c}', 1068), - ('\u{44d}', 1069), ('\u{44e}', 1070), ('\u{44f}', 1071), ('\u{450}', 1024), - ('\u{451}', 1025), ('\u{452}', 1026), ('\u{453}', 1027), ('\u{454}', 1028), - ('\u{455}', 1029), ('\u{456}', 1030), ('\u{457}', 1031), ('\u{458}', 1032), - ('\u{459}', 1033), ('\u{45a}', 1034), ('\u{45b}', 1035), ('\u{45c}', 1036), - ('\u{45d}', 1037), ('\u{45e}', 1038), ('\u{45f}', 1039), ('\u{461}', 1120), - ('\u{463}', 1122), ('\u{465}', 1124), ('\u{467}', 1126), ('\u{469}', 1128), - ('\u{46b}', 1130), ('\u{46d}', 1132), ('\u{46f}', 1134), ('\u{471}', 1136), - ('\u{473}', 1138), ('\u{475}', 1140), ('\u{477}', 1142), ('\u{479}', 1144), - ('\u{47b}', 1146), ('\u{47d}', 1148), ('\u{47f}', 1150), ('\u{481}', 1152), - ('\u{48b}', 1162), ('\u{48d}', 1164), ('\u{48f}', 1166), ('\u{491}', 1168), - ('\u{493}', 1170), ('\u{495}', 1172), ('\u{497}', 1174), ('\u{499}', 1176), - ('\u{49b}', 1178), ('\u{49d}', 1180), ('\u{49f}', 1182), ('\u{4a1}', 1184), - ('\u{4a3}', 1186), ('\u{4a5}', 1188), ('\u{4a7}', 1190), ('\u{4a9}', 1192), - ('\u{4ab}', 1194), ('\u{4ad}', 1196), ('\u{4af}', 1198), ('\u{4b1}', 1200), - ('\u{4b3}', 1202), ('\u{4b5}', 1204), ('\u{4b7}', 1206), ('\u{4b9}', 1208), - ('\u{4bb}', 1210), ('\u{4bd}', 1212), ('\u{4bf}', 1214), ('\u{4c2}', 1217), - ('\u{4c4}', 1219), ('\u{4c6}', 1221), ('\u{4c8}', 1223), ('\u{4ca}', 1225), - ('\u{4cc}', 1227), ('\u{4ce}', 1229), ('\u{4cf}', 1216), ('\u{4d1}', 1232), - ('\u{4d3}', 1234), ('\u{4d5}', 1236), ('\u{4d7}', 1238), ('\u{4d9}', 1240), - ('\u{4db}', 1242), ('\u{4dd}', 1244), ('\u{4df}', 1246), ('\u{4e1}', 1248), - ('\u{4e3}', 1250), ('\u{4e5}', 1252), ('\u{4e7}', 1254), ('\u{4e9}', 1256), - ('\u{4eb}', 1258), ('\u{4ed}', 1260), ('\u{4ef}', 1262), ('\u{4f1}', 1264), - ('\u{4f3}', 1266), ('\u{4f5}', 1268), ('\u{4f7}', 1270), ('\u{4f9}', 1272), - ('\u{4fb}', 1274), ('\u{4fd}', 1276), ('\u{4ff}', 1278), ('\u{501}', 1280), - ('\u{503}', 1282), ('\u{505}', 1284), ('\u{507}', 1286), ('\u{509}', 1288), - ('\u{50b}', 1290), ('\u{50d}', 1292), ('\u{50f}', 1294), ('\u{511}', 1296), - ('\u{513}', 1298), ('\u{515}', 1300), ('\u{517}', 1302), ('\u{519}', 1304), - ('\u{51b}', 1306), ('\u{51d}', 1308), ('\u{51f}', 1310), ('\u{521}', 1312), - ('\u{523}', 1314), ('\u{525}', 1316), ('\u{527}', 1318), ('\u{529}', 1320), - ('\u{52b}', 1322), ('\u{52d}', 1324), ('\u{52f}', 1326), ('\u{561}', 1329), - ('\u{562}', 1330), ('\u{563}', 1331), ('\u{564}', 1332), ('\u{565}', 1333), - ('\u{566}', 1334), ('\u{567}', 1335), ('\u{568}', 1336), ('\u{569}', 1337), - ('\u{56a}', 1338), ('\u{56b}', 1339), ('\u{56c}', 1340), ('\u{56d}', 1341), - ('\u{56e}', 1342), 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42934), - ('\u{a7b9}', 42936), ('\u{a7bb}', 42938), ('\u{a7bd}', 42940), ('\u{a7bf}', 42942), - ('\u{a7c1}', 42944), ('\u{a7c3}', 42946), ('\u{a7c8}', 42951), ('\u{a7ca}', 42953), - ('\u{a7cd}', 42956), ('\u{a7cf}', 42958), ('\u{a7d1}', 42960), ('\u{a7d3}', 42962), - ('\u{a7d5}', 42964), ('\u{a7d7}', 42966), ('\u{a7d9}', 42968), ('\u{a7db}', 42970), - ('\u{a7f6}', 42997), ('\u{ab53}', 42931), ('\u{ab70}', 5024), ('\u{ab71}', 5025), - ('\u{ab72}', 5026), ('\u{ab73}', 5027), ('\u{ab74}', 5028), ('\u{ab75}', 5029), - ('\u{ab76}', 5030), ('\u{ab77}', 5031), ('\u{ab78}', 5032), ('\u{ab79}', 5033), - ('\u{ab7a}', 5034), ('\u{ab7b}', 5035), ('\u{ab7c}', 5036), ('\u{ab7d}', 5037), - ('\u{ab7e}', 5038), ('\u{ab7f}', 5039), ('\u{ab80}', 5040), ('\u{ab81}', 5041), - ('\u{ab82}', 5042), ('\u{ab83}', 5043), ('\u{ab84}', 5044), ('\u{ab85}', 5045), - ('\u{ab86}', 5046), ('\u{ab87}', 5047), ('\u{ab88}', 5048), ('\u{ab89}', 5049), - ('\u{ab8a}', 5050), ('\u{ab8b}', 5051), ('\u{ab8c}', 5052), ('\u{ab8d}', 5053), - ('\u{ab8e}', 5054), ('\u{ab8f}', 5055), ('\u{ab90}', 5056), ('\u{ab91}', 5057), - ('\u{ab92}', 5058), ('\u{ab93}', 5059), ('\u{ab94}', 5060), ('\u{ab95}', 5061), - ('\u{ab96}', 5062), ('\u{ab97}', 5063), ('\u{ab98}', 5064), ('\u{ab99}', 5065), - ('\u{ab9a}', 5066), ('\u{ab9b}', 5067), ('\u{ab9c}', 5068), ('\u{ab9d}', 5069), - ('\u{ab9e}', 5070), ('\u{ab9f}', 5071), ('\u{aba0}', 5072), ('\u{aba1}', 5073), - ('\u{aba2}', 5074), ('\u{aba3}', 5075), ('\u{aba4}', 5076), ('\u{aba5}', 5077), - ('\u{aba6}', 5078), ('\u{aba7}', 5079), ('\u{aba8}', 5080), ('\u{aba9}', 5081), - ('\u{abaa}', 5082), ('\u{abab}', 5083), ('\u{abac}', 5084), ('\u{abad}', 5085), - ('\u{abae}', 5086), ('\u{abaf}', 5087), ('\u{abb0}', 5088), ('\u{abb1}', 5089), - ('\u{abb2}', 5090), ('\u{abb3}', 5091), ('\u{abb4}', 5092), ('\u{abb5}', 5093), - ('\u{abb6}', 5094), ('\u{abb7}', 5095), ('\u{abb8}', 5096), ('\u{abb9}', 5097), - ('\u{abba}', 5098), ('\u{abbb}', 5099), ('\u{abbc}', 5100), ('\u{abbd}', 5101), - ('\u{abbe}', 5102), ('\u{abbf}', 5103), ('\u{fb00}', 4194394), ('\u{fb01}', 4194395), - ('\u{fb02}', 4194396), ('\u{fb03}', 4194397), ('\u{fb04}', 4194398), ('\u{fb05}', 4194399), - ('\u{fb06}', 4194400), ('\u{fb13}', 4194401), ('\u{fb14}', 4194402), ('\u{fb15}', 4194403), - ('\u{fb16}', 4194404), ('\u{fb17}', 4194405), ('\u{ff41}', 65313), ('\u{ff42}', 65314), - ('\u{ff43}', 65315), ('\u{ff44}', 65316), ('\u{ff45}', 65317), ('\u{ff46}', 65318), - ('\u{ff47}', 65319), ('\u{ff48}', 65320), ('\u{ff49}', 65321), ('\u{ff4a}', 65322), - ('\u{ff4b}', 65323), ('\u{ff4c}', 65324), ('\u{ff4d}', 65325), ('\u{ff4e}', 65326), - ('\u{ff4f}', 65327), ('\u{ff50}', 65328), ('\u{ff51}', 65329), ('\u{ff52}', 65330), - ('\u{ff53}', 65331), ('\u{ff54}', 65332), ('\u{ff55}', 65333), ('\u{ff56}', 65334), - ('\u{ff57}', 65335), ('\u{ff58}', 65336), ('\u{ff59}', 65337), ('\u{ff5a}', 65338), - ('\u{10428}', 66560), ('\u{10429}', 66561), ('\u{1042a}', 66562), ('\u{1042b}', 66563), - ('\u{1042c}', 66564), ('\u{1042d}', 66565), ('\u{1042e}', 66566), ('\u{1042f}', 66567), - ('\u{10430}', 66568), ('\u{10431}', 66569), ('\u{10432}', 66570), ('\u{10433}', 66571), - ('\u{10434}', 66572), ('\u{10435}', 66573), ('\u{10436}', 66574), ('\u{10437}', 66575), - ('\u{10438}', 66576), ('\u{10439}', 66577), ('\u{1043a}', 66578), ('\u{1043b}', 66579), - ('\u{1043c}', 66580), ('\u{1043d}', 66581), ('\u{1043e}', 66582), ('\u{1043f}', 66583), - ('\u{10440}', 66584), ('\u{10441}', 66585), ('\u{10442}', 66586), ('\u{10443}', 66587), - ('\u{10444}', 66588), ('\u{10445}', 66589), ('\u{10446}', 66590), ('\u{10447}', 66591), - ('\u{10448}', 66592), ('\u{10449}', 66593), ('\u{1044a}', 66594), ('\u{1044b}', 66595), - ('\u{1044c}', 66596), ('\u{1044d}', 66597), ('\u{1044e}', 66598), ('\u{1044f}', 66599), - ('\u{104d8}', 66736), ('\u{104d9}', 66737), ('\u{104da}', 66738), ('\u{104db}', 66739), - ('\u{104dc}', 66740), ('\u{104dd}', 66741), ('\u{104de}', 66742), ('\u{104df}', 66743), - ('\u{104e0}', 66744), ('\u{104e1}', 66745), ('\u{104e2}', 66746), ('\u{104e3}', 66747), - ('\u{104e4}', 66748), ('\u{104e5}', 66749), ('\u{104e6}', 66750), ('\u{104e7}', 66751), - ('\u{104e8}', 66752), ('\u{104e9}', 66753), ('\u{104ea}', 66754), ('\u{104eb}', 66755), - ('\u{104ec}', 66756), ('\u{104ed}', 66757), ('\u{104ee}', 66758), ('\u{104ef}', 66759), - ('\u{104f0}', 66760), ('\u{104f1}', 66761), ('\u{104f2}', 66762), ('\u{104f3}', 66763), - ('\u{104f4}', 66764), ('\u{104f5}', 66765), ('\u{104f6}', 66766), ('\u{104f7}', 66767), - ('\u{104f8}', 66768), ('\u{104f9}', 66769), ('\u{104fa}', 66770), ('\u{104fb}', 66771), - ('\u{10597}', 66928), ('\u{10598}', 66929), ('\u{10599}', 66930), ('\u{1059a}', 66931), - ('\u{1059b}', 66932), ('\u{1059c}', 66933), ('\u{1059d}', 66934), ('\u{1059e}', 66935), - ('\u{1059f}', 66936), ('\u{105a0}', 66937), ('\u{105a1}', 66938), ('\u{105a3}', 66940), - ('\u{105a4}', 66941), ('\u{105a5}', 66942), ('\u{105a6}', 66943), ('\u{105a7}', 66944), - ('\u{105a8}', 66945), ('\u{105a9}', 66946), ('\u{105aa}', 66947), ('\u{105ab}', 66948), - ('\u{105ac}', 66949), ('\u{105ad}', 66950), ('\u{105ae}', 66951), ('\u{105af}', 66952), - ('\u{105b0}', 66953), ('\u{105b1}', 66954), ('\u{105b3}', 66956), ('\u{105b4}', 66957), - ('\u{105b5}', 66958), ('\u{105b6}', 66959), ('\u{105b7}', 66960), ('\u{105b8}', 66961), - ('\u{105b9}', 66962), ('\u{105bb}', 66964), ('\u{105bc}', 66965), ('\u{10cc0}', 68736), - ('\u{10cc1}', 68737), ('\u{10cc2}', 68738), ('\u{10cc3}', 68739), ('\u{10cc4}', 68740), - ('\u{10cc5}', 68741), ('\u{10cc6}', 68742), ('\u{10cc7}', 68743), ('\u{10cc8}', 68744), - ('\u{10cc9}', 68745), ('\u{10cca}', 68746), ('\u{10ccb}', 68747), ('\u{10ccc}', 68748), - ('\u{10ccd}', 68749), ('\u{10cce}', 68750), ('\u{10ccf}', 68751), ('\u{10cd0}', 68752), - ('\u{10cd1}', 68753), ('\u{10cd2}', 68754), ('\u{10cd3}', 68755), ('\u{10cd4}', 68756), - ('\u{10cd5}', 68757), ('\u{10cd6}', 68758), ('\u{10cd7}', 68759), ('\u{10cd8}', 68760), - ('\u{10cd9}', 68761), ('\u{10cda}', 68762), ('\u{10cdb}', 68763), ('\u{10cdc}', 68764), - ('\u{10cdd}', 68765), ('\u{10cde}', 68766), ('\u{10cdf}', 68767), ('\u{10ce0}', 68768), - ('\u{10ce1}', 68769), ('\u{10ce2}', 68770), ('\u{10ce3}', 68771), ('\u{10ce4}', 68772), - ('\u{10ce5}', 68773), ('\u{10ce6}', 68774), ('\u{10ce7}', 68775), ('\u{10ce8}', 68776), - ('\u{10ce9}', 68777), ('\u{10cea}', 68778), ('\u{10ceb}', 68779), ('\u{10cec}', 68780), - ('\u{10ced}', 68781), ('\u{10cee}', 68782), ('\u{10cef}', 68783), ('\u{10cf0}', 68784), - ('\u{10cf1}', 68785), ('\u{10cf2}', 68786), ('\u{10d70}', 68944), ('\u{10d71}', 68945), - ('\u{10d72}', 68946), ('\u{10d73}', 68947), ('\u{10d74}', 68948), ('\u{10d75}', 68949), - ('\u{10d76}', 68950), ('\u{10d77}', 68951), ('\u{10d78}', 68952), ('\u{10d79}', 68953), - ('\u{10d7a}', 68954), ('\u{10d7b}', 68955), ('\u{10d7c}', 68956), ('\u{10d7d}', 68957), - ('\u{10d7e}', 68958), ('\u{10d7f}', 68959), ('\u{10d80}', 68960), ('\u{10d81}', 68961), - ('\u{10d82}', 68962), ('\u{10d83}', 68963), ('\u{10d84}', 68964), ('\u{10d85}', 68965), - ('\u{118c0}', 71840), ('\u{118c1}', 71841), ('\u{118c2}', 71842), ('\u{118c3}', 71843), - ('\u{118c4}', 71844), ('\u{118c5}', 71845), ('\u{118c6}', 71846), ('\u{118c7}', 71847), - ('\u{118c8}', 71848), ('\u{118c9}', 71849), ('\u{118ca}', 71850), ('\u{118cb}', 71851), - ('\u{118cc}', 71852), ('\u{118cd}', 71853), ('\u{118ce}', 71854), ('\u{118cf}', 71855), - ('\u{118d0}', 71856), ('\u{118d1}', 71857), ('\u{118d2}', 71858), ('\u{118d3}', 71859), - ('\u{118d4}', 71860), ('\u{118d5}', 71861), ('\u{118d6}', 71862), ('\u{118d7}', 71863), - ('\u{118d8}', 71864), ('\u{118d9}', 71865), ('\u{118da}', 71866), ('\u{118db}', 71867), - ('\u{118dc}', 71868), ('\u{118dd}', 71869), ('\u{118de}', 71870), ('\u{118df}', 71871), - ('\u{16e60}', 93760), ('\u{16e61}', 93761), ('\u{16e62}', 93762), ('\u{16e63}', 93763), - ('\u{16e64}', 93764), ('\u{16e65}', 93765), ('\u{16e66}', 93766), ('\u{16e67}', 93767), - ('\u{16e68}', 93768), ('\u{16e69}', 93769), ('\u{16e6a}', 93770), ('\u{16e6b}', 93771), - ('\u{16e6c}', 93772), ('\u{16e6d}', 93773), ('\u{16e6e}', 93774), ('\u{16e6f}', 93775), - ('\u{16e70}', 93776), ('\u{16e71}', 93777), ('\u{16e72}', 93778), ('\u{16e73}', 93779), - ('\u{16e74}', 93780), ('\u{16e75}', 93781), ('\u{16e76}', 93782), ('\u{16e77}', 93783), - ('\u{16e78}', 93784), ('\u{16e79}', 93785), ('\u{16e7a}', 93786), ('\u{16e7b}', 93787), - ('\u{16e7c}', 93788), ('\u{16e7d}', 93789), ('\u{16e7e}', 93790), ('\u{16e7f}', 93791), - ('\u{16ebb}', 93856), ('\u{16ebc}', 93857), ('\u{16ebd}', 93858), ('\u{16ebe}', 93859), - ('\u{16ebf}', 93860), ('\u{16ec0}', 93861), ('\u{16ec1}', 93862), ('\u{16ec2}', 93863), - ('\u{16ec3}', 93864), ('\u{16ec4}', 93865), ('\u{16ec5}', 93866), ('\u{16ec6}', 93867), - ('\u{16ec7}', 93868), ('\u{16ec8}', 93869), ('\u{16ec9}', 93870), ('\u{16eca}', 93871), - ('\u{16ecb}', 93872), ('\u{16ecc}', 93873), ('\u{16ecd}', 93874), ('\u{16ece}', 93875), - ('\u{16ecf}', 93876), ('\u{16ed0}', 93877), ('\u{16ed1}', 93878), ('\u{16ed2}', 93879), - ('\u{16ed3}', 93880), ('\u{1e922}', 125184), ('\u{1e923}', 125185), ('\u{1e924}', 125186), - ('\u{1e925}', 125187), ('\u{1e926}', 125188), ('\u{1e927}', 125189), ('\u{1e928}', 125190), - ('\u{1e929}', 125191), ('\u{1e92a}', 125192), ('\u{1e92b}', 125193), ('\u{1e92c}', 125194), - ('\u{1e92d}', 125195), ('\u{1e92e}', 125196), ('\u{1e92f}', 125197), ('\u{1e930}', 125198), - ('\u{1e931}', 125199), ('\u{1e932}', 125200), ('\u{1e933}', 125201), ('\u{1e934}', 125202), - ('\u{1e935}', 125203), ('\u{1e936}', 125204), ('\u{1e937}', 125205), ('\u{1e938}', 125206), - ('\u{1e939}', 125207), ('\u{1e93a}', 125208), ('\u{1e93b}', 125209), ('\u{1e93c}', 125210), - ('\u{1e93d}', 125211), ('\u{1e93e}', 125212), ('\u{1e93f}', 125213), ('\u{1e940}', 125214), - ('\u{1e941}', 125215), ('\u{1e942}', 125216), ('\u{1e943}', 125217), - ]; + pub fn to_casefold(c: char) -> [char; 3] { + // https://util.unicode.org/UnicodeJsps/list-unicodeset.jsp?a=[:Changes_When_Casefolded:]-[:ASCII:]&abb=on + if c < '\u{B5}' { + return [c.to_ascii_lowercase(), '\0', '\0']; + } - static UPPERCASE_TABLE_MULTI: &[[char; 3]; 102] = &[ - ['S', 'S', '\u{0}'], ['\u{2bc}', 'N', '\u{0}'], ['J', '\u{30c}', '\u{0}'], - ['\u{399}', '\u{308}', '\u{301}'], ['\u{3a5}', '\u{308}', '\u{301}'], - ['\u{535}', '\u{552}', '\u{0}'], ['H', '\u{331}', '\u{0}'], ['T', '\u{308}', '\u{0}'], - ['W', '\u{30a}', '\u{0}'], ['Y', '\u{30a}', '\u{0}'], ['A', '\u{2be}', '\u{0}'], - ['\u{3a5}', '\u{313}', '\u{0}'], ['\u{3a5}', '\u{313}', '\u{300}'], - ['\u{3a5}', '\u{313}', '\u{301}'], ['\u{3a5}', '\u{313}', '\u{342}'], - ['\u{1f08}', '\u{399}', '\u{0}'], ['\u{1f09}', '\u{399}', '\u{0}'], - ['\u{1f0a}', '\u{399}', '\u{0}'], ['\u{1f0b}', '\u{399}', '\u{0}'], - ['\u{1f0c}', '\u{399}', '\u{0}'], ['\u{1f0d}', '\u{399}', '\u{0}'], - ['\u{1f0e}', '\u{399}', '\u{0}'], ['\u{1f0f}', '\u{399}', '\u{0}'], - ['\u{1f08}', '\u{399}', '\u{0}'], ['\u{1f09}', '\u{399}', '\u{0}'], - ['\u{1f0a}', '\u{399}', '\u{0}'], ['\u{1f0b}', '\u{399}', '\u{0}'], - ['\u{1f0c}', '\u{399}', '\u{0}'], ['\u{1f0d}', '\u{399}', '\u{0}'], - ['\u{1f0e}', '\u{399}', '\u{0}'], ['\u{1f0f}', '\u{399}', '\u{0}'], - ['\u{1f28}', '\u{399}', '\u{0}'], ['\u{1f29}', '\u{399}', '\u{0}'], - ['\u{1f2a}', '\u{399}', '\u{0}'], ['\u{1f2b}', '\u{399}', '\u{0}'], - ['\u{1f2c}', '\u{399}', '\u{0}'], ['\u{1f2d}', '\u{399}', '\u{0}'], - ['\u{1f2e}', '\u{399}', '\u{0}'], ['\u{1f2f}', '\u{399}', '\u{0}'], - ['\u{1f28}', '\u{399}', '\u{0}'], ['\u{1f29}', '\u{399}', '\u{0}'], - ['\u{1f2a}', '\u{399}', '\u{0}'], ['\u{1f2b}', '\u{399}', '\u{0}'], - ['\u{1f2c}', '\u{399}', '\u{0}'], ['\u{1f2d}', '\u{399}', '\u{0}'], - ['\u{1f2e}', '\u{399}', '\u{0}'], ['\u{1f2f}', '\u{399}', '\u{0}'], - ['\u{1f68}', '\u{399}', '\u{0}'], ['\u{1f69}', '\u{399}', '\u{0}'], - ['\u{1f6a}', '\u{399}', '\u{0}'], ['\u{1f6b}', '\u{399}', '\u{0}'], - ['\u{1f6c}', '\u{399}', '\u{0}'], ['\u{1f6d}', '\u{399}', '\u{0}'], - ['\u{1f6e}', '\u{399}', '\u{0}'], ['\u{1f6f}', '\u{399}', '\u{0}'], - ['\u{1f68}', '\u{399}', '\u{0}'], ['\u{1f69}', '\u{399}', '\u{0}'], - ['\u{1f6a}', '\u{399}', '\u{0}'], ['\u{1f6b}', '\u{399}', '\u{0}'], - ['\u{1f6c}', '\u{399}', '\u{0}'], ['\u{1f6d}', '\u{399}', '\u{0}'], - ['\u{1f6e}', '\u{399}', '\u{0}'], ['\u{1f6f}', '\u{399}', '\u{0}'], - ['\u{1fba}', '\u{399}', '\u{0}'], ['\u{391}', '\u{399}', '\u{0}'], - ['\u{386}', '\u{399}', '\u{0}'], ['\u{391}', '\u{342}', '\u{0}'], - ['\u{391}', '\u{342}', '\u{399}'], ['\u{391}', '\u{399}', '\u{0}'], - ['\u{1fca}', '\u{399}', '\u{0}'], ['\u{397}', '\u{399}', '\u{0}'], - ['\u{389}', '\u{399}', '\u{0}'], ['\u{397}', '\u{342}', '\u{0}'], - ['\u{397}', '\u{342}', '\u{399}'], ['\u{397}', '\u{399}', '\u{0}'], - ['\u{399}', '\u{308}', '\u{300}'], ['\u{399}', '\u{308}', '\u{301}'], - ['\u{399}', '\u{342}', '\u{0}'], ['\u{399}', '\u{308}', '\u{342}'], - ['\u{3a5}', '\u{308}', '\u{300}'], ['\u{3a5}', '\u{308}', '\u{301}'], - ['\u{3a1}', '\u{313}', '\u{0}'], ['\u{3a5}', '\u{342}', '\u{0}'], - ['\u{3a5}', '\u{308}', '\u{342}'], ['\u{1ffa}', '\u{399}', '\u{0}'], - ['\u{3a9}', '\u{399}', '\u{0}'], ['\u{38f}', '\u{399}', '\u{0}'], - ['\u{3a9}', '\u{342}', '\u{0}'], ['\u{3a9}', '\u{342}', '\u{399}'], - ['\u{3a9}', '\u{399}', '\u{0}'], ['F', 'F', '\u{0}'], ['F', 'I', '\u{0}'], - ['F', 'L', '\u{0}'], ['F', 'F', 'I'], ['F', 'F', 'L'], ['S', 'T', '\u{0}'], - ['S', 'T', '\u{0}'], ['\u{544}', '\u{546}', '\u{0}'], ['\u{544}', '\u{535}', '\u{0}'], - ['\u{544}', '\u{53b}', '\u{0}'], ['\u{54e}', '\u{546}', '\u{0}'], - ['\u{544}', '\u{53d}', '\u{0}'], - ]; + + lookup(c, &CASEFOLD_LUT).unwrap_or_else(|| { + // Fall back to lowercase of uppercase + + let uppercase = lookup(c, &UPPERCASE_LUT).unwrap_or([c, '\0', '\0']); + + // We need to take the lowercase of each character in `uppercase`, + // and then concatenate them together. + + // Lowercase the first uppercased char + let mut final_result = to_lower(uppercase[0]); + + if uppercase[1] != '\0' { + // There's a 2nd uppercase char, lowercase it as well + let lowercase_1 = to_lower(uppercase[1]); + + // The lowercase of the second uppercase character + // can't be 3 chars long; + // that would bring the total case-folding length + // above 3 characters, which would violate + // a Unicode stability guarantee. + debug_assert_eq!(lowercase_1[2], '\0'); + + // Currently, in every case where there + // are multiple uppercased characters, + // the lowercase of the first uppercase + // has length 1. However, Unicode doesn't + // guarantee this. + // If, after updating the Unicode data + // to a new Unicode version, the below + // assertion starts to fail in + // `coretests/tests/unicode.rs` `to_casefold()`, + // delete it, and uncomment the + // `if` condition and corresponding + // `else` block below it. + debug_assert_eq!(final_result[1], '\0'); + //if final_result[1] == '\0' { + + final_result[1] = lowercase_1[0]; + + if uppercase[2] != '\0' { + // There's a 3rd uppercased char, lowercase it as well. + // Because of the Unicode stability guarantee that case-folding + // does not expand a string more than 3x in length, + // we know this lowercase must be 1 char long. + + debug_assert_eq!(lowercase_1[1], '\0'); + let lowercase_2 = to_lower(uppercase[2]); + debug_assert_eq!(lowercase_2[1], '\0'); + debug_assert_eq!(lowercase_2[2], '\0'); + final_result[2] = lowercase_2[0]; + } else { + // Currently, the lowercase of + // the second uppercase character + // can't be 2 chars long either, + // but Unicode doesn't guarantee this. + // If, after updating the Unicode data + // to a new Unicode version, the below + // assertion starts to fail in + // `coretests/tests/unicode.rs` `to_casefold()`, + // delete it and uncomment the line + // below it. + debug_assert_eq!(lowercase_1[1], '\0'); + //final_result[2] = lowercase_1[1]; + } + + /*} else { + final_result[2] = lowercase_1[0]; + debug_assert_eq!(lowercase_1[1], '\0'); + debug_assert_eq!(uppercase[2], '\0') + }*/ + } + final_result + }) + } + + static LOWERCASE_LUT: L1Lut = L1Lut { + l2_luts: [ + L2Lut { + singles: &[ // 172 entries, 1032 bytes + (Range::step_by_1(0x00c0..=0x00d6), 32), (Range::step_by_1(0x00d8..=0x00de), 32), + (Range::step_by_2(0x0100..=0x012e), 1), (Range::step_by_2(0x0132..=0x0136), 1), + (Range::step_by_2(0x0139..=0x0147), 1), (Range::step_by_2(0x014a..=0x0176), 1), + (Range::singleton(0x0178), -121), (Range::step_by_2(0x0179..=0x017d), 1), + (Range::singleton(0x0181), 210), (Range::step_by_2(0x0182..=0x0184), 1), + (Range::singleton(0x0186), 206), (Range::singleton(0x0187), 1), + (Range::step_by_1(0x0189..=0x018a), 205), (Range::singleton(0x018b), 1), + (Range::singleton(0x018e), 79), (Range::singleton(0x018f), 202), + (Range::singleton(0x0190), 203), (Range::singleton(0x0191), 1), + (Range::singleton(0x0193), 205), (Range::singleton(0x0194), 207), + (Range::singleton(0x0196), 211), (Range::singleton(0x0197), 209), + (Range::singleton(0x0198), 1), (Range::singleton(0x019c), 211), + (Range::singleton(0x019d), 213), (Range::singleton(0x019f), 214), + (Range::step_by_2(0x01a0..=0x01a4), 1), (Range::singleton(0x01a6), 218), + (Range::singleton(0x01a7), 1), (Range::singleton(0x01a9), 218), + (Range::singleton(0x01ac), 1), (Range::singleton(0x01ae), 218), + (Range::singleton(0x01af), 1), (Range::step_by_1(0x01b1..=0x01b2), 217), + (Range::step_by_2(0x01b3..=0x01b5), 1), (Range::singleton(0x01b7), 219), + (Range::singleton(0x01b8), 1), (Range::singleton(0x01bc), 1), (Range::singleton(0x01c4), 2), + (Range::singleton(0x01c5), 1), (Range::singleton(0x01c7), 2), (Range::singleton(0x01c8), 1), + (Range::singleton(0x01ca), 2), (Range::step_by_2(0x01cb..=0x01db), 1), + (Range::step_by_2(0x01de..=0x01ee), 1), (Range::singleton(0x01f1), 2), + (Range::step_by_2(0x01f2..=0x01f4), 1), (Range::singleton(0x01f6), -97), + (Range::singleton(0x01f7), -56), (Range::step_by_2(0x01f8..=0x021e), 1), + (Range::singleton(0x0220), -130), (Range::step_by_2(0x0222..=0x0232), 1), + (Range::singleton(0x023a), 10795), (Range::singleton(0x023b), 1), + (Range::singleton(0x023d), -163), (Range::singleton(0x023e), 10792), + (Range::singleton(0x0241), 1), (Range::singleton(0x0243), -195), + (Range::singleton(0x0244), 69), (Range::singleton(0x0245), 71), + (Range::step_by_2(0x0246..=0x024e), 1), (Range::step_by_2(0x0370..=0x0372), 1), + (Range::singleton(0x0376), 1), (Range::singleton(0x037f), 116), + (Range::singleton(0x0386), 38), (Range::step_by_1(0x0388..=0x038a), 37), + (Range::singleton(0x038c), 64), (Range::step_by_1(0x038e..=0x038f), 63), + (Range::step_by_1(0x0391..=0x03a1), 32), (Range::step_by_1(0x03a3..=0x03ab), 32), + (Range::singleton(0x03cf), 8), (Range::step_by_2(0x03d8..=0x03ee), 1), + (Range::singleton(0x03f4), -60), (Range::singleton(0x03f7), 1), + (Range::singleton(0x03f9), -7), (Range::singleton(0x03fa), 1), + (Range::step_by_1(0x03fd..=0x03ff), -130), (Range::step_by_1(0x0400..=0x040f), 80), + (Range::step_by_1(0x0410..=0x042f), 32), (Range::step_by_2(0x0460..=0x0480), 1), + (Range::step_by_2(0x048a..=0x04be), 1), (Range::singleton(0x04c0), 15), + (Range::step_by_2(0x04c1..=0x04cd), 1), (Range::step_by_2(0x04d0..=0x052e), 1), + (Range::step_by_1(0x0531..=0x0556), 48), (Range::step_by_1(0x10a0..=0x10c5), 7264), + (Range::singleton(0x10c7), 7264), (Range::singleton(0x10cd), 7264), + (Range::step_by_1(0x13a0..=0x13ef), -26672), (Range::step_by_1(0x13f0..=0x13f5), 8), + (Range::singleton(0x1c89), 1), (Range::step_by_1(0x1c90..=0x1cba), -3008), + (Range::step_by_1(0x1cbd..=0x1cbf), -3008), (Range::step_by_2(0x1e00..=0x1e94), 1), + (Range::singleton(0x1e9e), -7615), (Range::step_by_2(0x1ea0..=0x1efe), 1), + (Range::step_by_1(0x1f08..=0x1f0f), -8), (Range::step_by_1(0x1f18..=0x1f1d), -8), + (Range::step_by_1(0x1f28..=0x1f2f), -8), (Range::step_by_1(0x1f38..=0x1f3f), -8), + (Range::step_by_1(0x1f48..=0x1f4d), -8), (Range::step_by_2(0x1f59..=0x1f5f), -8), + (Range::step_by_1(0x1f68..=0x1f6f), -8), (Range::step_by_1(0x1f88..=0x1f8f), -8), + (Range::step_by_1(0x1f98..=0x1f9f), -8), (Range::step_by_1(0x1fa8..=0x1faf), -8), + (Range::step_by_1(0x1fb8..=0x1fb9), -8), (Range::step_by_1(0x1fba..=0x1fbb), -74), + (Range::singleton(0x1fbc), -9), (Range::step_by_1(0x1fc8..=0x1fcb), -86), + (Range::singleton(0x1fcc), -9), (Range::step_by_1(0x1fd8..=0x1fd9), -8), + (Range::step_by_1(0x1fda..=0x1fdb), -100), (Range::step_by_1(0x1fe8..=0x1fe9), -8), + (Range::step_by_1(0x1fea..=0x1feb), -112), (Range::singleton(0x1fec), -7), + (Range::step_by_1(0x1ff8..=0x1ff9), -128), (Range::step_by_1(0x1ffa..=0x1ffb), -126), + (Range::singleton(0x1ffc), -9), (Range::singleton(0x2126), -7517), + (Range::singleton(0x212a), -8383), (Range::singleton(0x212b), -8262), + (Range::singleton(0x2132), 28), (Range::step_by_1(0x2160..=0x216f), 16), + (Range::singleton(0x2183), 1), (Range::step_by_1(0x24b6..=0x24cf), 26), + (Range::step_by_1(0x2c00..=0x2c2f), 48), (Range::singleton(0x2c60), 1), + (Range::singleton(0x2c62), -10743), (Range::singleton(0x2c63), -3814), + (Range::singleton(0x2c64), -10727), (Range::step_by_2(0x2c67..=0x2c6b), 1), + (Range::singleton(0x2c6d), -10780), (Range::singleton(0x2c6e), -10749), + (Range::singleton(0x2c6f), -10783), (Range::singleton(0x2c70), -10782), + (Range::singleton(0x2c72), 1), (Range::singleton(0x2c75), 1), + (Range::step_by_1(0x2c7e..=0x2c7f), -10815), (Range::step_by_2(0x2c80..=0x2ce2), 1), + (Range::step_by_2(0x2ceb..=0x2ced), 1), (Range::singleton(0x2cf2), 1), + (Range::step_by_2(0xa640..=0xa66c), 1), (Range::step_by_2(0xa680..=0xa69a), 1), + (Range::step_by_2(0xa722..=0xa72e), 1), (Range::step_by_2(0xa732..=0xa76e), 1), + (Range::step_by_2(0xa779..=0xa77b), 1), (Range::singleton(0xa77d), 30204), + (Range::step_by_2(0xa77e..=0xa786), 1), (Range::singleton(0xa78b), 1), + (Range::singleton(0xa78d), 23256), (Range::step_by_2(0xa790..=0xa792), 1), + (Range::step_by_2(0xa796..=0xa7a8), 1), (Range::singleton(0xa7aa), 23228), + (Range::singleton(0xa7ab), 23217), (Range::singleton(0xa7ac), 23221), + (Range::singleton(0xa7ad), 23231), (Range::singleton(0xa7ae), 23228), + (Range::singleton(0xa7b0), 23278), (Range::singleton(0xa7b1), 23254), + (Range::singleton(0xa7b2), 23275), (Range::singleton(0xa7b3), 928), + (Range::step_by_2(0xa7b4..=0xa7c2), 1), (Range::singleton(0xa7c4), -48), + (Range::singleton(0xa7c5), 23229), (Range::singleton(0xa7c6), 30152), + (Range::step_by_2(0xa7c7..=0xa7c9), 1), (Range::singleton(0xa7cb), 23193), + (Range::step_by_2(0xa7cc..=0xa7da), 1), (Range::singleton(0xa7dc), 22975), + (Range::singleton(0xa7f5), 1), (Range::step_by_1(0xff21..=0xff3a), 32), + ], + multis: &[ // 1 entries, 8 bytes + (0x0130, [0x0069, 0x0307, 0x0000]), + ], + }, + L2Lut { + singles: &[ // 12 entries, 72 bytes + (Range::step_by_1(0x0400..=0x0427), 40), (Range::step_by_1(0x04b0..=0x04d3), 40), + (Range::step_by_1(0x0570..=0x057a), 39), (Range::step_by_1(0x057c..=0x058a), 39), + (Range::step_by_1(0x058c..=0x0592), 39), (Range::step_by_1(0x0594..=0x0595), 39), + (Range::step_by_1(0x0c80..=0x0cb2), 64), (Range::step_by_1(0x0d50..=0x0d65), 32), + (Range::step_by_1(0x18a0..=0x18bf), 32), (Range::step_by_1(0x6e40..=0x6e5f), 32), + (Range::step_by_1(0x6ea0..=0x6eb8), 27), (Range::step_by_1(0xe900..=0xe921), 34), + ], + multis: &[ // 0 entries, 0 bytes + ], + }, + ], + }; + + static UPPERCASE_LUT: L1Lut = L1Lut { + l2_luts: [ + L2Lut { + singles: &[ // 185 entries, 1110 bytes + (Range::singleton(0x00b5), 743), (Range::step_by_1(0x00e0..=0x00f6), -32), + (Range::step_by_1(0x00f8..=0x00fe), -32), (Range::singleton(0x00ff), 121), + (Range::step_by_2(0x0101..=0x012f), -1), (Range::singleton(0x0131), -232), + (Range::step_by_2(0x0133..=0x0137), -1), (Range::step_by_2(0x013a..=0x0148), -1), + (Range::step_by_2(0x014b..=0x0177), -1), (Range::step_by_2(0x017a..=0x017e), -1), + (Range::singleton(0x017f), -300), (Range::singleton(0x0180), 195), + (Range::step_by_2(0x0183..=0x0185), -1), (Range::singleton(0x0188), -1), + (Range::singleton(0x018c), -1), (Range::singleton(0x0192), -1), + (Range::singleton(0x0195), 97), (Range::singleton(0x0199), -1), + (Range::singleton(0x019a), 163), (Range::singleton(0x019b), -22975), + (Range::singleton(0x019e), 130), (Range::step_by_2(0x01a1..=0x01a5), -1), + (Range::singleton(0x01a8), -1), (Range::singleton(0x01ad), -1), + (Range::singleton(0x01b0), -1), (Range::step_by_2(0x01b4..=0x01b6), -1), + (Range::singleton(0x01b9), -1), (Range::singleton(0x01bd), -1), + (Range::singleton(0x01bf), 56), (Range::singleton(0x01c5), -1), + (Range::singleton(0x01c6), -2), (Range::singleton(0x01c8), -1), + (Range::singleton(0x01c9), -2), (Range::singleton(0x01cb), -1), + (Range::singleton(0x01cc), -2), (Range::step_by_2(0x01ce..=0x01dc), -1), + (Range::singleton(0x01dd), -79), (Range::step_by_2(0x01df..=0x01ef), -1), + (Range::singleton(0x01f2), -1), (Range::singleton(0x01f3), -2), + (Range::singleton(0x01f5), -1), (Range::step_by_2(0x01f9..=0x021f), -1), + (Range::step_by_2(0x0223..=0x0233), -1), (Range::singleton(0x023c), -1), + (Range::step_by_1(0x023f..=0x0240), 10815), (Range::singleton(0x0242), -1), + (Range::step_by_2(0x0247..=0x024f), -1), (Range::singleton(0x0250), 10783), + (Range::singleton(0x0251), 10780), (Range::singleton(0x0252), 10782), + (Range::singleton(0x0253), -210), (Range::singleton(0x0254), -206), + (Range::step_by_1(0x0256..=0x0257), -205), (Range::singleton(0x0259), -202), + (Range::singleton(0x025b), -203), (Range::singleton(0x025c), -23217), + (Range::singleton(0x0260), -205), (Range::singleton(0x0261), -23221), + (Range::singleton(0x0263), -207), (Range::singleton(0x0264), -23193), + (Range::singleton(0x0265), -23256), (Range::singleton(0x0266), -23228), + (Range::singleton(0x0268), -209), (Range::singleton(0x0269), -211), + (Range::singleton(0x026a), -23228), (Range::singleton(0x026b), 10743), + (Range::singleton(0x026c), -23231), (Range::singleton(0x026f), -211), + (Range::singleton(0x0271), 10749), (Range::singleton(0x0272), -213), + (Range::singleton(0x0275), -214), (Range::singleton(0x027d), 10727), + (Range::singleton(0x0280), -218), (Range::singleton(0x0282), -23229), + (Range::singleton(0x0283), -218), (Range::singleton(0x0287), -23254), + (Range::singleton(0x0288), -218), (Range::singleton(0x0289), -69), + (Range::step_by_1(0x028a..=0x028b), -217), (Range::singleton(0x028c), -71), + (Range::singleton(0x0292), -219), (Range::singleton(0x029d), -23275), + (Range::singleton(0x029e), -23278), (Range::singleton(0x0345), 84), + (Range::step_by_2(0x0371..=0x0373), -1), (Range::singleton(0x0377), -1), + (Range::step_by_1(0x037b..=0x037d), 130), (Range::singleton(0x03ac), -38), + (Range::step_by_1(0x03ad..=0x03af), -37), (Range::step_by_1(0x03b1..=0x03c1), -32), + (Range::singleton(0x03c2), -31), (Range::step_by_1(0x03c3..=0x03cb), -32), + (Range::singleton(0x03cc), -64), (Range::step_by_1(0x03cd..=0x03ce), -63), + (Range::singleton(0x03d0), -62), (Range::singleton(0x03d1), -57), + (Range::singleton(0x03d5), -47), (Range::singleton(0x03d6), -54), + (Range::singleton(0x03d7), -8), (Range::step_by_2(0x03d9..=0x03ef), -1), + (Range::singleton(0x03f0), -86), (Range::singleton(0x03f1), -80), + (Range::singleton(0x03f2), 7), (Range::singleton(0x03f3), -116), + (Range::singleton(0x03f5), -96), (Range::singleton(0x03f8), -1), + (Range::singleton(0x03fb), -1), (Range::step_by_1(0x0430..=0x044f), -32), + (Range::step_by_1(0x0450..=0x045f), -80), (Range::step_by_2(0x0461..=0x0481), -1), + (Range::step_by_2(0x048b..=0x04bf), -1), (Range::step_by_2(0x04c2..=0x04ce), -1), + (Range::singleton(0x04cf), -15), (Range::step_by_2(0x04d1..=0x052f), -1), + (Range::step_by_1(0x0561..=0x0586), -48), (Range::step_by_1(0x10d0..=0x10fa), 3008), + (Range::step_by_1(0x10fd..=0x10ff), 3008), (Range::step_by_1(0x13f8..=0x13fd), -8), + (Range::singleton(0x1c80), -6254), (Range::singleton(0x1c81), -6253), + (Range::singleton(0x1c82), -6244), (Range::step_by_1(0x1c83..=0x1c84), -6242), + (Range::singleton(0x1c85), -6243), (Range::singleton(0x1c86), -6236), + (Range::singleton(0x1c87), -6181), (Range::singleton(0x1c88), -30270), + (Range::singleton(0x1c8a), -1), (Range::singleton(0x1d79), -30204), + (Range::singleton(0x1d7d), 3814), (Range::singleton(0x1d8e), -30152), + (Range::step_by_2(0x1e01..=0x1e95), -1), (Range::singleton(0x1e9b), -59), + (Range::step_by_2(0x1ea1..=0x1eff), -1), (Range::step_by_1(0x1f00..=0x1f07), 8), + (Range::step_by_1(0x1f10..=0x1f15), 8), (Range::step_by_1(0x1f20..=0x1f27), 8), + (Range::step_by_1(0x1f30..=0x1f37), 8), (Range::step_by_1(0x1f40..=0x1f45), 8), + (Range::step_by_2(0x1f51..=0x1f57), 8), (Range::step_by_1(0x1f60..=0x1f67), 8), + (Range::step_by_1(0x1f70..=0x1f71), 74), (Range::step_by_1(0x1f72..=0x1f75), 86), + (Range::step_by_1(0x1f76..=0x1f77), 100), (Range::step_by_1(0x1f78..=0x1f79), 128), + (Range::step_by_1(0x1f7a..=0x1f7b), 112), (Range::step_by_1(0x1f7c..=0x1f7d), 126), + (Range::step_by_1(0x1fb0..=0x1fb1), 8), (Range::singleton(0x1fbe), -7205), + (Range::step_by_1(0x1fd0..=0x1fd1), 8), (Range::step_by_1(0x1fe0..=0x1fe1), 8), + (Range::singleton(0x1fe5), 7), (Range::singleton(0x214e), -28), + (Range::step_by_1(0x2170..=0x217f), -16), (Range::singleton(0x2184), -1), + (Range::step_by_1(0x24d0..=0x24e9), -26), (Range::step_by_1(0x2c30..=0x2c5f), -48), + (Range::singleton(0x2c61), -1), (Range::singleton(0x2c65), -10795), + (Range::singleton(0x2c66), -10792), (Range::step_by_2(0x2c68..=0x2c6c), -1), + (Range::singleton(0x2c73), -1), (Range::singleton(0x2c76), -1), + (Range::step_by_2(0x2c81..=0x2ce3), -1), (Range::step_by_2(0x2cec..=0x2cee), -1), + (Range::singleton(0x2cf3), -1), (Range::step_by_1(0x2d00..=0x2d25), -7264), + (Range::singleton(0x2d27), -7264), (Range::singleton(0x2d2d), -7264), + (Range::step_by_2(0xa641..=0xa66d), -1), (Range::step_by_2(0xa681..=0xa69b), -1), + (Range::step_by_2(0xa723..=0xa72f), -1), (Range::step_by_2(0xa733..=0xa76f), -1), + (Range::step_by_2(0xa77a..=0xa77c), -1), (Range::step_by_2(0xa77f..=0xa787), -1), + (Range::singleton(0xa78c), -1), (Range::step_by_2(0xa791..=0xa793), -1), + (Range::singleton(0xa794), 48), (Range::step_by_2(0xa797..=0xa7a9), -1), + (Range::step_by_2(0xa7b5..=0xa7c3), -1), (Range::step_by_2(0xa7c8..=0xa7ca), -1), + (Range::step_by_2(0xa7cd..=0xa7db), -1), (Range::singleton(0xa7f6), -1), + (Range::singleton(0xab53), -928), (Range::step_by_1(0xab70..=0xabbf), 26672), + (Range::step_by_1(0xff41..=0xff5a), -32), + ], + multis: &[ // 102 entries, 816 bytes + (0x00df, [0x0053, 0x0053, 0x0000]), (0x0149, [0x02bc, 0x004e, 0x0000]), + (0x01f0, [0x004a, 0x030c, 0x0000]), (0x0390, [0x0399, 0x0308, 0x0301]), + (0x03b0, [0x03a5, 0x0308, 0x0301]), (0x0587, [0x0535, 0x0552, 0x0000]), + (0x1e96, [0x0048, 0x0331, 0x0000]), (0x1e97, [0x0054, 0x0308, 0x0000]), + (0x1e98, [0x0057, 0x030a, 0x0000]), (0x1e99, [0x0059, 0x030a, 0x0000]), + (0x1e9a, [0x0041, 0x02be, 0x0000]), (0x1f50, [0x03a5, 0x0313, 0x0000]), + (0x1f52, [0x03a5, 0x0313, 0x0300]), (0x1f54, [0x03a5, 0x0313, 0x0301]), + (0x1f56, [0x03a5, 0x0313, 0x0342]), (0x1f80, [0x1f08, 0x0399, 0x0000]), + (0x1f81, [0x1f09, 0x0399, 0x0000]), (0x1f82, [0x1f0a, 0x0399, 0x0000]), + (0x1f83, [0x1f0b, 0x0399, 0x0000]), (0x1f84, [0x1f0c, 0x0399, 0x0000]), + (0x1f85, [0x1f0d, 0x0399, 0x0000]), (0x1f86, [0x1f0e, 0x0399, 0x0000]), + (0x1f87, [0x1f0f, 0x0399, 0x0000]), (0x1f88, [0x1f08, 0x0399, 0x0000]), + (0x1f89, [0x1f09, 0x0399, 0x0000]), (0x1f8a, [0x1f0a, 0x0399, 0x0000]), + (0x1f8b, [0x1f0b, 0x0399, 0x0000]), (0x1f8c, [0x1f0c, 0x0399, 0x0000]), + (0x1f8d, [0x1f0d, 0x0399, 0x0000]), (0x1f8e, [0x1f0e, 0x0399, 0x0000]), + (0x1f8f, [0x1f0f, 0x0399, 0x0000]), (0x1f90, [0x1f28, 0x0399, 0x0000]), + (0x1f91, [0x1f29, 0x0399, 0x0000]), (0x1f92, [0x1f2a, 0x0399, 0x0000]), + (0x1f93, [0x1f2b, 0x0399, 0x0000]), (0x1f94, [0x1f2c, 0x0399, 0x0000]), + (0x1f95, [0x1f2d, 0x0399, 0x0000]), (0x1f96, [0x1f2e, 0x0399, 0x0000]), + (0x1f97, [0x1f2f, 0x0399, 0x0000]), (0x1f98, [0x1f28, 0x0399, 0x0000]), + (0x1f99, [0x1f29, 0x0399, 0x0000]), (0x1f9a, [0x1f2a, 0x0399, 0x0000]), + (0x1f9b, [0x1f2b, 0x0399, 0x0000]), (0x1f9c, [0x1f2c, 0x0399, 0x0000]), + (0x1f9d, [0x1f2d, 0x0399, 0x0000]), (0x1f9e, [0x1f2e, 0x0399, 0x0000]), + (0x1f9f, [0x1f2f, 0x0399, 0x0000]), (0x1fa0, [0x1f68, 0x0399, 0x0000]), + (0x1fa1, [0x1f69, 0x0399, 0x0000]), (0x1fa2, [0x1f6a, 0x0399, 0x0000]), + (0x1fa3, [0x1f6b, 0x0399, 0x0000]), (0x1fa4, [0x1f6c, 0x0399, 0x0000]), + (0x1fa5, [0x1f6d, 0x0399, 0x0000]), (0x1fa6, [0x1f6e, 0x0399, 0x0000]), + (0x1fa7, [0x1f6f, 0x0399, 0x0000]), (0x1fa8, [0x1f68, 0x0399, 0x0000]), + (0x1fa9, [0x1f69, 0x0399, 0x0000]), (0x1faa, [0x1f6a, 0x0399, 0x0000]), + (0x1fab, [0x1f6b, 0x0399, 0x0000]), (0x1fac, [0x1f6c, 0x0399, 0x0000]), + (0x1fad, [0x1f6d, 0x0399, 0x0000]), (0x1fae, [0x1f6e, 0x0399, 0x0000]), + (0x1faf, [0x1f6f, 0x0399, 0x0000]), (0x1fb2, [0x1fba, 0x0399, 0x0000]), + (0x1fb3, [0x0391, 0x0399, 0x0000]), (0x1fb4, [0x0386, 0x0399, 0x0000]), + (0x1fb6, [0x0391, 0x0342, 0x0000]), (0x1fb7, [0x0391, 0x0342, 0x0399]), + (0x1fbc, [0x0391, 0x0399, 0x0000]), (0x1fc2, [0x1fca, 0x0399, 0x0000]), + (0x1fc3, [0x0397, 0x0399, 0x0000]), (0x1fc4, [0x0389, 0x0399, 0x0000]), + (0x1fc6, [0x0397, 0x0342, 0x0000]), (0x1fc7, [0x0397, 0x0342, 0x0399]), + (0x1fcc, [0x0397, 0x0399, 0x0000]), (0x1fd2, [0x0399, 0x0308, 0x0300]), + (0x1fd3, [0x0399, 0x0308, 0x0301]), (0x1fd6, [0x0399, 0x0342, 0x0000]), + (0x1fd7, [0x0399, 0x0308, 0x0342]), (0x1fe2, [0x03a5, 0x0308, 0x0300]), + (0x1fe3, [0x03a5, 0x0308, 0x0301]), (0x1fe4, [0x03a1, 0x0313, 0x0000]), + (0x1fe6, [0x03a5, 0x0342, 0x0000]), (0x1fe7, [0x03a5, 0x0308, 0x0342]), + (0x1ff2, [0x1ffa, 0x0399, 0x0000]), (0x1ff3, [0x03a9, 0x0399, 0x0000]), + (0x1ff4, [0x038f, 0x0399, 0x0000]), (0x1ff6, [0x03a9, 0x0342, 0x0000]), + (0x1ff7, [0x03a9, 0x0342, 0x0399]), (0x1ffc, [0x03a9, 0x0399, 0x0000]), + (0xfb00, [0x0046, 0x0046, 0x0000]), (0xfb01, [0x0046, 0x0049, 0x0000]), + (0xfb02, [0x0046, 0x004c, 0x0000]), (0xfb03, [0x0046, 0x0046, 0x0049]), + (0xfb04, [0x0046, 0x0046, 0x004c]), (0xfb05, [0x0053, 0x0054, 0x0000]), + (0xfb06, [0x0053, 0x0054, 0x0000]), (0xfb13, [0x0544, 0x0546, 0x0000]), + (0xfb14, [0x0544, 0x0535, 0x0000]), (0xfb15, [0x0544, 0x053b, 0x0000]), + (0xfb16, [0x054e, 0x0546, 0x0000]), (0xfb17, [0x0544, 0x053d, 0x0000]), + ], + }, + L2Lut { + singles: &[ // 12 entries, 72 bytes + (Range::step_by_1(0x0428..=0x044f), -40), (Range::step_by_1(0x04d8..=0x04fb), -40), + (Range::step_by_1(0x0597..=0x05a1), -39), (Range::step_by_1(0x05a3..=0x05b1), -39), + (Range::step_by_1(0x05b3..=0x05b9), -39), (Range::step_by_1(0x05bb..=0x05bc), -39), + (Range::step_by_1(0x0cc0..=0x0cf2), -64), (Range::step_by_1(0x0d70..=0x0d85), -32), + (Range::step_by_1(0x18c0..=0x18df), -32), (Range::step_by_1(0x6e60..=0x6e7f), -32), + (Range::step_by_1(0x6ebb..=0x6ed3), -27), (Range::step_by_1(0xe922..=0xe943), -34), + ], + multis: &[ // 0 entries, 0 bytes + ], + }, + ], + }; + + static TITLECASE_LUT: L1Lut = L1Lut { + l2_luts: [ + L2Lut { + singles: &[ // 26 entries, 156 bytes + (Range::singleton(0x01c4), 1), (Range::singleton(0x01c5), 0), + (Range::singleton(0x01c6), -1), (Range::singleton(0x01c7), 1), + (Range::singleton(0x01c8), 0), (Range::singleton(0x01c9), -1), + (Range::singleton(0x01ca), 1), (Range::singleton(0x01cb), 0), + (Range::singleton(0x01cc), -1), (Range::singleton(0x01f1), 1), + (Range::singleton(0x01f2), 0), (Range::singleton(0x01f3), -1), + (Range::step_by_1(0x10d0..=0x10fa), 0), (Range::step_by_1(0x10fd..=0x10ff), 0), + (Range::step_by_1(0x1f80..=0x1f87), 8), (Range::step_by_1(0x1f88..=0x1f8f), 0), + (Range::step_by_1(0x1f90..=0x1f97), 8), (Range::step_by_1(0x1f98..=0x1f9f), 0), + (Range::step_by_1(0x1fa0..=0x1fa7), 8), (Range::step_by_1(0x1fa8..=0x1faf), 0), + (Range::singleton(0x1fb3), 9), (Range::singleton(0x1fbc), 0), (Range::singleton(0x1fc3), 9), + (Range::singleton(0x1fcc), 0), (Range::singleton(0x1ff3), 9), (Range::singleton(0x1ffc), 0), + ], + multis: &[ // 23 entries, 184 bytes + (0x00df, [0x0053, 0x0073, 0x0000]), (0x0587, [0x0535, 0x0582, 0x0000]), + (0x1fb2, [0x1fba, 0x0345, 0x0000]), (0x1fb4, [0x0386, 0x0345, 0x0000]), + (0x1fb7, [0x0391, 0x0342, 0x0345]), (0x1fc2, [0x1fca, 0x0345, 0x0000]), + (0x1fc4, [0x0389, 0x0345, 0x0000]), (0x1fc7, [0x0397, 0x0342, 0x0345]), + (0x1ff2, [0x1ffa, 0x0345, 0x0000]), (0x1ff4, [0x038f, 0x0345, 0x0000]), + (0x1ff7, [0x03a9, 0x0342, 0x0345]), (0xfb00, [0x0046, 0x0066, 0x0000]), + (0xfb01, [0x0046, 0x0069, 0x0000]), (0xfb02, [0x0046, 0x006c, 0x0000]), + (0xfb03, [0x0046, 0x0066, 0x0069]), (0xfb04, [0x0046, 0x0066, 0x006c]), + (0xfb05, [0x0053, 0x0074, 0x0000]), (0xfb06, [0x0053, 0x0074, 0x0000]), + (0xfb13, [0x0544, 0x0576, 0x0000]), (0xfb14, [0x0544, 0x0565, 0x0000]), + (0xfb15, [0x0544, 0x056b, 0x0000]), (0xfb16, [0x054e, 0x0576, 0x0000]), + (0xfb17, [0x0544, 0x056d, 0x0000]), + ], + }, + L2Lut { + singles: &[ // 0 entries, 0 bytes + ], + multis: &[ // 0 entries, 0 bytes + ], + }, + ], + }; + + static CASEFOLD_LUT: L1Lut = L1Lut { + l2_luts: [ + L2Lut { + singles: &[ // 4 entries, 24 bytes + (Range::singleton(0x0131), 0), (Range::step_by_1(0x13a0..=0x13f5), 0), + (Range::step_by_1(0x13f8..=0x13fd), -8), (Range::step_by_1(0xab70..=0xabbf), 26672), + ], + multis: &[ // 1 entries, 8 bytes + (0x1e9e, [0x0073, 0x0073, 0x0000]), + ], + }, + L2Lut { + singles: &[ // 0 entries, 0 bytes + ], + multis: &[ // 0 entries, 0 bytes + ], + }, + ], + }; } diff --git a/library/core/src/unit.rs b/library/core/src/unit.rs index d54816c444bc4..5d9c79538e371 100644 --- a/library/core/src/unit.rs +++ b/library/core/src/unit.rs @@ -1,3 +1,5 @@ +use crate::intrinsics::type_id; + /// Collapses all unit items from an iterator into one. /// /// This is more useful when combined with higher-level abstractions, like @@ -19,17 +21,10 @@ impl FromIterator<()> for () { } pub(crate) trait IsUnit { - fn is_unit() -> bool; + const IS_UNIT: bool; } impl IsUnit for T { - default fn is_unit() -> bool { - false - } -} - -impl IsUnit for () { - fn is_unit() -> bool { - true - } + // `type_id` erases lifetimes, but that's OK here because "is it ()" never depends on lifetimes + const IS_UNIT: bool = type_id::() == type_id::<()>(); } diff --git a/library/core/src/unsafe_binder.rs b/library/core/src/unsafe_binder.rs index 98f53e07d9d8d..3d2a04e95f078 100644 --- a/library/core/src/unsafe_binder.rs +++ b/library/core/src/unsafe_binder.rs @@ -3,6 +3,7 @@ /// Unwrap an unsafe binder into its underlying type. #[allow_internal_unstable(builtin_syntax)] #[unstable(feature = "unsafe_binders", issue = "130516")] +#[diagnostic::opaque] pub macro unwrap_binder { ($expr:expr) => { builtin # unwrap_binder ( $expr ) @@ -15,6 +16,7 @@ pub macro unwrap_binder { /// Wrap a type into an unsafe binder. #[allow_internal_unstable(builtin_syntax)] #[unstable(feature = "unsafe_binders", issue = "130516")] +#[diagnostic::opaque] pub macro wrap_binder { ($expr:expr) => { builtin # wrap_binder ( $expr ) diff --git a/library/core/src/view.rs b/library/core/src/view.rs new file mode 100644 index 0000000000000..68eca3f3598d2 --- /dev/null +++ b/library/core/src/view.rs @@ -0,0 +1,21 @@ +//! Helpers module for exporting the `view_types` macro. + +/// Creates a view type. +/// ``` +/// #![feature(view_types, view_type_macro)] +// +/// struct Foo { +/// bar: usize, +/// baz: u32, +/// } +/// +/// type FooBar = std::view::view_type!(Foo.{ bar }); +/// ``` +#[macro_export] +#[rustc_builtin_macro(view_type)] +#[unstable(feature = "view_type_macro", issue = "155938")] +macro_rules! view_type { + ($($arg:tt)*) => { + /* compiler built-in */ + }; +} diff --git a/library/core/src/wtf8.rs b/library/core/src/wtf8.rs index 7214918db6c39..56679ea3aa9d9 100644 --- a/library/core/src/wtf8.rs +++ b/library/core/src/wtf8.rs @@ -147,7 +147,7 @@ impl fmt::Debug for Wtf8 { use crate::fmt::Write as _; for c in s.chars().flat_map(|c| { c.escape_debug_ext(EscapeDebugExtArgs { - escape_grapheme_extended: true, + escape_grapheme_extender: true, escape_single_quote: false, escape_double_quote: true, }) @@ -454,25 +454,50 @@ impl Wtf8 { #[track_caller] #[inline] pub fn check_utf8_boundary(&self, index: usize) { + let Err(err) = self.try_check_utf8_boundary(index) else { return }; + match err { + Utf8BoundaryError::NotABoundary => { + panic!("byte index {index} is not a codepoint boundary") + } + Utf8BoundaryError::OutOfBounds => panic!("byte index {index} is out of bounds"), + Utf8BoundaryError::BetweenSurrogates => { + panic!("byte index {index} lies between surrogate codepoints") + } + } + } + + #[track_caller] + #[inline] + pub fn try_check_utf8_boundary(&self, index: usize) -> Result<(), Utf8BoundaryError> { if index == 0 { - return; + return Ok(()); } match self.bytes.get(index) { Some(0xED) => (), // Might be a surrogate - Some(&b) if (b as i8) >= -0x40 => return, - Some(_) => panic!("byte index {index} is not a codepoint boundary"), - None if index == self.len() => return, - None => panic!("byte index {index} is out of bounds"), + Some(&b) if (b as i8) >= -0x40 => return Ok(()), + Some(_) => return Err(Utf8BoundaryError::NotABoundary), + None if index == self.len() => return Ok(()), + None => return Err(Utf8BoundaryError::OutOfBounds), } if self.bytes[index + 1] >= 0xA0 { // There's a surrogate after index. Now check before index. if index >= 3 && self.bytes[index - 3] == 0xED && self.bytes[index - 2] >= 0xA0 { - panic!("byte index {index} lies between surrogate codepoints"); + return Err(Utf8BoundaryError::BetweenSurrogates); } } + Ok(()) } } +// This error type is only used temporarily to provide better panic messages +// It does not implement Error. +#[derive(Debug)] +pub enum Utf8BoundaryError { + NotABoundary, + OutOfBounds, + BetweenSurrogates, +} + /// Copied from core::str::raw::slice_unchecked #[inline] unsafe fn slice_unchecked(s: &Wtf8, begin: usize, end: usize) -> &Wtf8 { @@ -484,11 +509,22 @@ unsafe fn slice_unchecked(s: &Wtf8, begin: usize, end: usize) -> &Wtf8 { } } -/// Copied from core::str::raw::slice_error_fail #[inline(never)] fn slice_error_fail(s: &Wtf8, begin: usize, end: usize) -> ! { - assert!(begin <= end); - panic!("index {begin} and/or {end} in `{s:?}` do not lie on character boundary"); + let len = s.len(); + if begin > len { + panic!("start byte index {begin} is out of bounds for string of length {len}"); + } + if end > len { + panic!("end byte index {end} is out of bounds for string of length {len}"); + } + if begin > end { + panic!("byte range starts at {begin} but ends at {end}"); + } + if !s.is_code_point_boundary(begin) { + panic!("byte index {begin} is not a code point boundary"); + } + panic!("byte index {end} is not a code point boundary"); } /// Iterator for the code points of a WTF-8 string. diff --git a/library/coretests/benches/lib.rs b/library/coretests/benches/lib.rs index 150b9b33f4578..e8dc815a7dd0f 100644 --- a/library/coretests/benches/lib.rs +++ b/library/coretests/benches/lib.rs @@ -1,6 +1,6 @@ // wasm32 does not support benches (no time). #![cfg(not(target_arch = "wasm32"))] -// Disabling in Miri as these would take too long. +// This is marked as `test = true` and hence picked up by `./x miri`, but that would be too slow. #![cfg(not(miri))] #![feature(flt2dec)] #![feature(test)] @@ -8,7 +8,9 @@ #![feature(iter_array_chunks)] #![feature(iter_next_chunk)] #![feature(iter_advance_by)] +#![feature(num_internals)] #![feature(uint_gather_scatter_bits)] +#![allow(internal_features)] extern crate test; diff --git a/library/coretests/benches/net/addr_parser.rs b/library/coretests/benches/net/addr_parser.rs index bbf2ea3eb9796..d44ea98bfcbec 100644 --- a/library/coretests/benches/net/addr_parser.rs +++ b/library/coretests/benches/net/addr_parser.rs @@ -3,76 +3,210 @@ use core::str::FromStr; use test::{Bencher, black_box}; -const IPV4_STR: &str = "192.168.0.1"; -const IPV4_STR_PORT: &str = "192.168.0.1:8080"; - -const IPV6_STR_FULL: &str = "2001:db8:0:0:0:0:c0a8:1"; -const IPV6_STR_COMPRESS: &str = "2001:db8::c0a8:1"; -const IPV6_STR_V4: &str = "2001:db8::192.168.0.1"; -const IPV6_STR_PORT: &str = "[2001:db8::c0a8:1]:8080"; -const IPV6_STR_PORT_SCOPE_ID: &str = "[2001:db8::c0a8:1%1337]:8080"; +const IPV4: &[&str] = &[ + "192.168.0.1", + "8.8.8.8", + "127.0.0.1", + "255.255.255.255", + "0.0.0.0", + "10.0.0.1", + "203.0.113.42", + "172.16.254.1", + "100.64.0.1", + "1.2.3.4", +]; + +const IPV4_PORT: &[&str] = &[ + "192.168.0.1:8080", + "8.8.8.8:53", + "127.0.0.1:65535", + "255.255.255.255:1", + "0.0.0.0:80", + "10.0.0.1:443", + "203.0.113.42:22", + "172.16.254.1:3306", + "100.64.0.1:8443", + "1.2.3.4:0", +]; + +const IPV6_FULL: &[&str] = &[ + "2001:db8:0:0:0:0:c0a8:1", + "2001:db8:85a3:8d3:1319:8a2e:370:7348", + "fe80:0:0:0:0:0:0:1", + "ff02:0:0:0:0:0:0:101", + "2001:4860:4860:0:0:0:0:8888", + "2606:4700:4700:0:0:0:0:1111", + "fd00:0:0:0:0:0:0:1", + "fec0:0:0:0:0:0:0:abcd", + "1:2:3:4:5:6:7:8", + "abcd:ef01:2345:6789:abcd:ef01:2345:6789", +]; + +const IPV6_COMPRESS: &[&str] = &[ + "2001:db8::c0a8:1", + "::1", + "fe80::1", + "2001:db8::", + "ff02::1:2", + "64:ff9b::", + "::", + "2001:4860:4860::8888", + "2606:4700:4700::1111", + "fe80::1ff:fe23:4567:890a", +]; + +const IPV6_V4: &[&str] = &[ + "2001:db8::192.168.0.1", + "::ffff:192.168.0.1", + "64:ff9b::192.0.2.33", + "::ffff:8.8.8.8", + "::192.168.0.1", + "::ffff:255.255.255.255", + "2001:db8:0:0:0:0:192.168.0.1", + "64:ff9b::10.0.0.1", + "::ffff:1.2.3.4", + "::ffff:127.0.0.1", +]; + +const IPV6_PORT: &[&str] = &[ + "[2001:db8::c0a8:1]:8080", + "[::1]:443", + "[fe80::1]:53", + "[2001:db8:85a3:8d3:1319:8a2e:370:7348]:22", + "[::]:80", + "[2001:4860:4860::8888]:443", + "[2606:4700:4700::1111]:53", + "[fe80::1ff:fe23:4567:890a]:8080", + "[64:ff9b::192.0.2.33]:443", + "[::ffff:8.8.8.8]:53", +]; + +const IPV6_PORT_SCOPE_ID: &[&str] = &[ + "[2001:db8::c0a8:1%1337]:8080", + "[fe80::1%1]:53", + "[fe80::1%999999]:443", + "[fe80::1%0]:80", + "[fe80::1ff:fe23:4567:890a%2]:8080", + "[::1%1]:443", + "[fe80::abcd%15]:22", + "[ff02::1%42]:5353", + "[fe80::1%4294967295]:443", + "[2001:db8::1%100]:8080", +]; #[bench] fn bench_parse_ipv4(b: &mut Bencher) { - b.iter(|| Ipv4Addr::from_str(black_box(IPV4_STR))); + b.iter(|| { + for s in IPV4 { + let _ = black_box(Ipv4Addr::from_str(black_box(s))); + } + }); } #[bench] fn bench_parse_ipv6_full(b: &mut Bencher) { - b.iter(|| Ipv6Addr::from_str(black_box(IPV6_STR_FULL))); + b.iter(|| { + for s in IPV6_FULL { + let _ = black_box(Ipv6Addr::from_str(black_box(s))); + } + }); } #[bench] fn bench_parse_ipv6_compress(b: &mut Bencher) { - b.iter(|| Ipv6Addr::from_str(black_box(IPV6_STR_COMPRESS))); + b.iter(|| { + for s in IPV6_COMPRESS { + let _ = black_box(Ipv6Addr::from_str(black_box(s))); + } + }); } #[bench] fn bench_parse_ipv6_v4(b: &mut Bencher) { - b.iter(|| Ipv6Addr::from_str(black_box(IPV6_STR_V4))); + b.iter(|| { + for s in IPV6_V4 { + let _ = black_box(Ipv6Addr::from_str(black_box(s))); + } + }); } #[bench] fn bench_parse_ipaddr_v4(b: &mut Bencher) { - b.iter(|| IpAddr::from_str(black_box(IPV4_STR))); + b.iter(|| { + for s in IPV4 { + let _ = black_box(IpAddr::from_str(black_box(s))); + } + }); } #[bench] fn bench_parse_ipaddr_v6_full(b: &mut Bencher) { - b.iter(|| IpAddr::from_str(black_box(IPV6_STR_FULL))); + b.iter(|| { + for s in IPV6_FULL { + let _ = black_box(IpAddr::from_str(black_box(s))); + } + }); } #[bench] fn bench_parse_ipaddr_v6_compress(b: &mut Bencher) { - b.iter(|| IpAddr::from_str(black_box(IPV6_STR_COMPRESS))); + b.iter(|| { + for s in IPV6_COMPRESS { + let _ = black_box(IpAddr::from_str(black_box(s))); + } + }); } #[bench] fn bench_parse_ipaddr_v6_v4(b: &mut Bencher) { - b.iter(|| IpAddr::from_str(black_box(IPV6_STR_V4))); + b.iter(|| { + for s in IPV6_V4 { + let _ = black_box(IpAddr::from_str(black_box(s))); + } + }); } #[bench] fn bench_parse_socket_v4(b: &mut Bencher) { - b.iter(|| SocketAddrV4::from_str(black_box(IPV4_STR_PORT))); + b.iter(|| { + for s in IPV4_PORT { + let _ = black_box(SocketAddrV4::from_str(black_box(s))); + } + }); } #[bench] fn bench_parse_socket_v6(b: &mut Bencher) { - b.iter(|| SocketAddrV6::from_str(black_box(IPV6_STR_PORT))); + b.iter(|| { + for s in IPV6_PORT { + let _ = black_box(SocketAddrV6::from_str(black_box(s))); + } + }); } #[bench] fn bench_parse_socket_v6_scope_id(b: &mut Bencher) { - b.iter(|| SocketAddrV6::from_str(black_box(IPV6_STR_PORT_SCOPE_ID))); + b.iter(|| { + for s in IPV6_PORT_SCOPE_ID { + let _ = black_box(SocketAddrV6::from_str(black_box(s))); + } + }); } #[bench] fn bench_parse_socketaddr_v4(b: &mut Bencher) { - b.iter(|| SocketAddr::from_str(black_box(IPV4_STR_PORT))); + b.iter(|| { + for s in IPV4_PORT { + let _ = black_box(SocketAddr::from_str(black_box(s))); + } + }); } #[bench] fn bench_parse_socketaddr_v6(b: &mut Bencher) { - b.iter(|| SocketAddr::from_str(black_box(IPV6_STR_PORT))); + b.iter(|| { + for s in IPV6_PORT { + let _ = black_box(SocketAddr::from_str(black_box(s))); + } + }); } diff --git a/library/coretests/benches/num/flt2dec/mod.rs b/library/coretests/benches/num/flt2dec/mod.rs index 428d0bbbbfbfa..0cd94ec5e1cfe 100644 --- a/library/coretests/benches/num/flt2dec/mod.rs +++ b/library/coretests/benches/num/flt2dec/mod.rs @@ -3,7 +3,7 @@ mod strategy { mod grisu; } -use core::num::flt2dec::{DecodableFloat, Decoded, FullDecoded, MAX_SIG_DIGITS, decode}; +use core::num::imp::flt2dec::{DecodableFloat, Decoded, FullDecoded, MAX_SIG_DIGITS, decode}; use std::io::Write; use test::{Bencher, black_box}; diff --git a/library/coretests/benches/num/flt2dec/strategy/dragon.rs b/library/coretests/benches/num/flt2dec/strategy/dragon.rs index 4526697140365..d98b3df9b2f35 100644 --- a/library/coretests/benches/num/flt2dec/strategy/dragon.rs +++ b/library/coretests/benches/num/flt2dec/strategy/dragon.rs @@ -1,4 +1,4 @@ -use core::num::flt2dec::strategy::dragon::*; +use core::num::imp::flt2dec::strategy::dragon::*; use std::mem::MaybeUninit; use super::super::*; diff --git a/library/coretests/benches/num/flt2dec/strategy/grisu.rs b/library/coretests/benches/num/flt2dec/strategy/grisu.rs index d20f9b02f7e74..5f73fdebf5e77 100644 --- a/library/coretests/benches/num/flt2dec/strategy/grisu.rs +++ b/library/coretests/benches/num/flt2dec/strategy/grisu.rs @@ -1,4 +1,4 @@ -use core::num::flt2dec::strategy::grisu::*; +use core::num::imp::flt2dec::strategy::grisu::*; use std::mem::MaybeUninit; use super::super::*; diff --git a/library/coretests/benches/pattern.rs b/library/coretests/benches/pattern.rs index b0f8b39c22e16..c7bbf879f722d 100644 --- a/library/coretests/benches/pattern.rs +++ b/library/coretests/benches/pattern.rs @@ -39,3 +39,203 @@ fn ends_with_str(b: &mut Bencher) { } }) } + +fn make_haystack() -> String { + "Lorem ipsum dolor sit amet, consectetur adipiscing elit. Suspendisse quis lorem \ + sit amet dolor ultricies condimentum. Praesent iaculis purus elit, ac malesuada \ + quam malesuada in. Duis sed orci eros. Suspendisse sit amet magna mollis, mollis \ + nunc luctus, imperdiet mi. Integer fringilla non sem ut lacinia. Fusce varius \ + tortor a risus porttitor hendrerit. Morbi mauris dui, ultricies nec tempus vel, \ + gravida nec quam. In est dui, tincidunt sed tempus interdum, adipiscing laoreet \ + ante. Etiam tempor, tellus quis sagittis interdum, nulla purus mattis sem, quis \ + auctor erat odio ac tellus. In nec nunc sit amet diam volutpat molestie at sed \ + ipsum. Vestibulum laoreet consequat vulputate. Integer accumsan lorem ac dignissim \ + placerat. Suspendisse convallis faucibus lorem. Aliquam erat volutpat." + .repeat(50) +} + +#[bench] +fn find_str(b: &mut Bencher) { + let s = make_haystack(); + let haystack = black_box(s.as_str()); + b.bytes = haystack.len() as u64; + b.iter(|| black_box(haystack.find("the english language"))) +} + +#[bench] +fn rfind_str(b: &mut Bencher) { + let s = make_haystack(); + let haystack = black_box(s.as_str()); + b.bytes = haystack.len() as u64; + b.iter(|| black_box(haystack.rfind("the english language"))) +} + +#[bench] +fn find_str_worst_case(b: &mut Bencher) { + let near_miss = "the english languagX"; + let haystack_str = near_miss.repeat(2000); + let haystack = black_box(haystack_str.as_str()); + b.bytes = haystack.len() as u64; + b.iter(|| black_box(haystack.find("the english language"))) +} + +#[bench] +fn rfind_str_worst_case(b: &mut Bencher) { + let near_miss = "the english languagX"; + let haystack_str = near_miss.repeat(2000); + let haystack = black_box(haystack_str.as_str()); + b.bytes = haystack.len() as u64; + b.iter(|| black_box(haystack.rfind("the english language"))) +} + +/// 64 KiB of text that does not contain the needle. +fn haystack_without_needle() -> String { + "abcdefgh".repeat(8 * 1024) +} + +#[bench] +fn find_1byte_str_long_nomatch(b: &mut Bencher) { + let s = haystack_without_needle(); + let haystack = black_box(s.as_str()); + b.bytes = haystack.len() as u64; + b.iter(|| black_box(haystack.find(","))) +} + +#[bench] +fn find_char_long_nomatch(b: &mut Bencher) { + let s = haystack_without_needle(); + let haystack = black_box(s.as_str()); + b.bytes = haystack.len() as u64; + b.iter(|| black_box(haystack.find(','))) +} + +#[bench] +fn find_1byte_str_long_match_end(b: &mut Bencher) { + let mut s = haystack_without_needle(); + s.push(','); + let haystack = black_box(s.as_str()); + b.bytes = haystack.len() as u64; + b.iter(|| black_box(haystack.find(","))) +} + +#[bench] +fn find_char_long_match_end(b: &mut Bencher) { + let mut s = haystack_without_needle(); + s.push(','); + let haystack = black_box(s.as_str()); + b.bytes = haystack.len() as u64; + b.iter(|| black_box(haystack.find(','))) +} + +#[bench] +fn rfind_1byte_str_long_nomatch(b: &mut Bencher) { + let s = haystack_without_needle(); + let haystack = black_box(s.as_str()); + b.bytes = haystack.len() as u64; + b.iter(|| black_box(haystack.rfind(","))) +} + +#[bench] +fn rfind_char_long_nomatch(b: &mut Bencher) { + let s = haystack_without_needle(); + let haystack = black_box(s.as_str()); + b.bytes = haystack.len() as u64; + b.iter(|| black_box(haystack.rfind(','))) +} + +#[bench] +fn find_1byte_str_early_return(b: &mut Bencher) { + let mut s = String::from("abcdefg,"); + s.push_str(&haystack_without_needle()); + let haystack = black_box(s.as_str()); + b.iter(|| { + for _ in 0..1024 { + black_box(black_box(haystack).find(",")); + } + }) +} + +#[bench] +fn find_char_early_return(b: &mut Bencher) { + let mut s = String::from("abcdefg,"); + s.push_str(&haystack_without_needle()); + let haystack = black_box(s.as_str()); + b.iter(|| { + for _ in 0..1024 { + black_box(black_box(haystack).find(',')); + } + }) +} + +// Short haystacks measure searcher construction overhead as much as the scan. +#[bench] +fn find_1byte_str_short_haystack(b: &mut Bencher) { + let haystack = black_box("abcdefg,ijklmno"); + b.iter(|| { + for _ in 0..1024 { + black_box(black_box(haystack).find(",")); + } + }) +} + +#[bench] +fn find_char_short_haystack(b: &mut Bencher) { + let haystack = black_box("abcdefg,ijklmno"); + b.iter(|| { + for _ in 0..1024 { + black_box(black_box(haystack).find(',')); + } + }) +} + +// Match-dense input: a match every third byte, the worst case for any +// skip-ahead scheme since there is nothing to skip. +#[bench] +fn split_1byte_str_dense(b: &mut Bencher) { + let s = "ab,".repeat(8 * 1024); + let haystack = black_box(s.as_str()); + b.bytes = haystack.len() as u64; + b.iter(|| black_box(haystack.split(",").count())) +} + +#[bench] +fn split_char_dense(b: &mut Bencher) { + let s = "ab,".repeat(8 * 1024); + let haystack = black_box(s.as_str()); + b.bytes = haystack.len() as u64; + b.iter(|| black_box(haystack.split(',').count())) +} + +// A match every 65 bytes, resembling line splitting. +#[bench] +fn split_1byte_str_sparse(b: &mut Bencher) { + let s = format!("{},", "abcdefgh".repeat(8)).repeat(1000); + let haystack = black_box(s.as_str()); + b.bytes = haystack.len() as u64; + b.iter(|| black_box(haystack.split(",").count())) +} + +#[bench] +fn split_char_sparse(b: &mut Bencher) { + let s = format!("{},", "abcdefgh".repeat(8)).repeat(1000); + let haystack = black_box(s.as_str()); + b.bytes = haystack.len() as u64; + b.iter(|| black_box(haystack.split(',').count())) +} + +// Haystack dominated by multi-byte chars, ASCII needle. +#[bench] +fn split_1byte_str_multibyte_haystack(b: &mut Bencher) { + let s = "\u{251c}\u{2500}\u{2500} ".repeat(8 * 1024); + let haystack = black_box(s.as_str()); + b.bytes = haystack.len() as u64; + b.iter(|| black_box(haystack.split(" ").count())) +} + +#[bench] +fn split_char_multibyte_haystack(b: &mut Bencher) { + let s = "\u{251c}\u{2500}\u{2500} ".repeat(8 * 1024); + let haystack = black_box(s.as_str()); + b.bytes = haystack.len() as u64; + b.iter(|| black_box(haystack.split(' ').count())) +} diff --git a/library/coretests/benches/str/eq_ignore_ascii_case.rs b/library/coretests/benches/str/eq_ignore_ascii_case.rs index 29129b933bc46..db75960664106 100644 --- a/library/coretests/benches/str/eq_ignore_ascii_case.rs +++ b/library/coretests/benches/str/eq_ignore_ascii_case.rs @@ -43,3 +43,23 @@ fn bench_large_str_eq(b: &mut Bencher) { let other = black_box(en::LARGE); b.iter(|| assert!(s.eq_ignore_ascii_case(other))) } + +#[bench] +fn bench_medium_str_early_mismatch(b: &mut Bencher) { + // Differs in the first byte, exercising the early-return path of the + // chunked comparison. + let other_owned = ["_", &en::MEDIUM[1..]].concat(); + let s = black_box(en::MEDIUM); + let other = black_box(&*other_owned); + b.iter(|| assert!(!s.eq_ignore_ascii_case(other))) +} + +#[bench] +fn bench_medium_str_tail_mismatch(b: &mut Bencher) { + // Differs in the last byte, exercising the `last_chunk` tail handling of + // the chunked comparison. + let other_owned = [&en::MEDIUM[..en::MEDIUM.len() - 1], "_"].concat(); + let s = black_box(en::MEDIUM); + let other = black_box(&*other_owned); + b.iter(|| assert!(!s.eq_ignore_ascii_case(other))) +} diff --git a/library/coretests/tests/array.rs b/library/coretests/tests/array.rs index 2b4429092e98b..5b35d05d6a032 100644 --- a/library/coretests/tests/array.rs +++ b/library/coretests/tests/array.rs @@ -1,3 +1,4 @@ +use core::cell::Cell; use core::num::NonZero; use core::sync::atomic::{AtomicUsize, Ordering}; use core::{array, assert_eq}; @@ -105,6 +106,34 @@ fn iterator_clone() { assert_eq!(clone.next_back(), Some(4)); assert_eq!(it.next(), Some(2)); assert_eq!(clone.next(), Some(2)); + assert_eq!(it.next(), None); + assert_eq!(clone.next(), None); +} + +#[test] +fn iterator_clone_spec() { + #[derive(Debug, PartialEq)] + struct Foo(i32); + + impl Clone for Foo { + fn clone(&self) -> Self { + // nontrivial clone + Foo(-self.0) + } + } + + let mut it = IntoIterator::into_iter([Foo(0), Foo(2), Foo(4), Foo(6), Foo(8)]); + assert_eq!(it.next(), Some(Foo(0))); + assert_eq!(it.next_back(), Some(Foo(8))); + let mut clone = it.clone(); + assert_eq!(it.next_back(), Some(Foo(6))); + assert_eq!(clone.next_back(), Some(Foo(-6))); + assert_eq!(it.next_back(), Some(Foo(4))); + assert_eq!(clone.next_back(), Some(Foo(-4))); + assert_eq!(it.next(), Some(Foo(2))); + assert_eq!(clone.next(), Some(Foo(-2))); + assert_eq!(it.next(), None); + assert_eq!(clone.next(), None); } #[test] @@ -168,8 +197,6 @@ fn iterator_debug() { #[test] fn iterator_drops() { - use core::cell::Cell; - // This test makes sure the correct number of elements are dropped. The `R` // type is just a reference to a `Cell` that is incremented when an `R` is // dropped. @@ -337,8 +364,6 @@ fn array_map_drop_safety() { #[test] fn cell_allows_array_cycle() { - use core::cell::Cell; - #[derive(Debug)] struct B<'a> { a: [Cell>>; 2], @@ -513,7 +538,6 @@ fn array_rsplit_array_mut_out_of_bounds() { #[test] fn array_intoiter_advance_by() { - use std::cell::Cell; struct DropCounter<'a>(usize, &'a Cell); impl Drop for DropCounter<'_> { fn drop(&mut self) { @@ -566,7 +590,6 @@ fn array_intoiter_advance_by() { #[test] fn array_intoiter_advance_back_by() { - use std::cell::Cell; struct DropCounter<'a>(usize, &'a Cell); impl Drop for DropCounter<'_> { fn drop(&mut self) { @@ -646,7 +669,7 @@ fn array_mixed_equality_integers() { #[test] fn array_mixed_equality_nans() { - let array3: [f32; 3] = [1.0, std::f32::NAN, 3.0]; + let array3: [f32; 3] = [1.0, f32::NAN, 3.0]; let slice3: &[f32] = &{ array3 }; assert!(!(array3 == slice3)); @@ -718,6 +741,33 @@ fn array_map_drops_unmapped_elements_on_panic() { } } +#[cfg(not(panic = "abort"))] +#[test] +fn array_map_drops_unmapped_zst_elements_on_panic() { + use std::sync::ReentrantLock; + + static DROPPED: ReentrantLock> = ReentrantLock::new(Cell::new(0)); + + struct ZstDrop; + impl Drop for ZstDrop { + fn drop(&mut self) { + DROPPED.lock().update(|x| x + 1); + } + } + + let dropped = DROPPED.lock(); + dropped.set(0); + let array = [const { ZstDrop }; 5]; + let success = std::panic::catch_unwind(std::panic::AssertUnwindSafe(|| { + let _ = array.map(|x| { + drop(x); + assert_eq!(dropped.get(), 1); + }); + })); + assert!(success.is_err()); + assert_eq!(dropped.get(), 5); +} + // This covers the `PartialEq::<[T]>::eq` impl for `[T; N]` when it returns false. #[test] fn array_eq() { @@ -741,3 +791,18 @@ fn const_array_ops() { struct Zst; assert_eq!([(); 10].try_map(|()| Some(Zst)), Some([const { Zst }; 10])); } + +#[test] +const fn extra_const_array_ops() { + let x: [u8; 4] = + { std::array::from_fn(const |i| i + 4).map(const |x| x * 2).map(const |x| x as _) }; + let y = 4; + struct Z(u16); + const impl Drop for Z { + fn drop(&mut self) {} + } + let w = Z(2); + let _x: [u8; 4] = { + std::array::from_fn(const |_| x[0] + y).map(const |x| x * (w.0 as u8)).map(const |x| x as _) + }; +} diff --git a/library/coretests/tests/bstr.rs b/library/coretests/tests/bstr.rs index cd4d69d6b337d..dffc7e3f03494 100644 --- a/library/coretests/tests/bstr.rs +++ b/library/coretests/tests/bstr.rs @@ -49,4 +49,19 @@ fn test_display() { assert_eq!(&format!("{b2:->3}!"), "�(��!"); assert_eq!(&format!("{b2:-^3}!"), "�(��!"); assert_eq!(&format!("{b2:-^2}!"), "�(��!"); + + assert_eq!(&format!("{b1:.1}!"), &format!("{:.1}!", "abc")); + assert_eq!(&format!("{b1:.2}!"), &format!("{:.2}!", "abc")); + assert_eq!(&format!("{b1:.3}!"), &format!("{:.3}!", "abc")); + assert_eq!(&format!("{b1:-<5.2}!"), &format!("{:-<5.2}!", "abc")); + assert_eq!(&format!("{b1:-^5.2}!"), &format!("{:-^5.2}!", "abc")); + assert_eq!(&format!("{b1:->5.2}!"), &format!("{:->5.2}!", "abc")); + + assert_eq!(&format!("{b2:.1}!"), "�!"); + assert_eq!(&format!("{b2:.2}!"), "�(!"); + assert_eq!(&format!("{b2:.3}!"), "�(�!"); + assert_eq!(&format!("{b2:.4}!"), "�(��!"); + assert_eq!(&format!("{b2:-<6.3}!"), "�(�---!"); + assert_eq!(&format!("{b2:-^6.3}!"), "-�(�--!"); + assert_eq!(&format!("{b2:->6.3}!"), "---�(�!"); } diff --git a/library/coretests/tests/char.rs b/library/coretests/tests/char.rs index f0f6a24429284..4981ab0c9b809 100644 --- a/library/coretests/tests/char.rs +++ b/library/coretests/tests/char.rs @@ -1,5 +1,6 @@ +use std::char::{self, CharCase}; +use std::str; use std::str::FromStr; -use std::{char, str}; #[test] fn test_convert() { @@ -39,6 +40,30 @@ fn test_from_str() { assert!(char::from_str("abc").is_err()); } +#[test] +fn test_is_cased() { + assert!('a'.is_cased()); + assert!('ö'.is_cased()); + assert!('ß'.is_cased()); + assert!('Ü'.is_cased()); + assert!('P'.is_cased()); + assert!('ª'.is_cased()); + assert!(!'攂'.is_cased()); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn test_char_case() { + for c in '\0'..='\u{10FFFF}' { + match c.case() { + None => assert!(!c.is_cased()), + Some(CharCase::Lower) => assert!(c.is_lowercase()), + Some(CharCase::Upper) => assert!(c.is_uppercase()), + Some(CharCase::Title) => assert!(c.is_titlecase()), + } + } +} + #[test] fn test_is_lowercase() { assert!('a'.is_lowercase()); @@ -48,6 +73,17 @@ fn test_is_lowercase() { assert!(!'P'.is_lowercase()); } +#[test] +fn test_is_titlecase() { + assert!('Dž'.is_titlecase()); + assert!('ᾨ'.is_titlecase()); + assert!(!'h'.is_titlecase()); + assert!(!'ä'.is_titlecase()); + assert!(!'ß'.is_titlecase()); + assert!(!'Ö'.is_titlecase()); + assert!(!'T'.is_titlecase()); +} + #[test] fn test_is_uppercase() { assert!(!'h'.is_uppercase()); @@ -57,6 +93,27 @@ fn test_is_uppercase() { assert!('T'.is_uppercase()); } +#[test] +fn titlecase_fast_path() { + for c in '\0'..='\u{01C4}' { + assert!(!(c.is_cased() && !c.is_lowercase() && !c.is_uppercase())) + } +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn at_most_one_case() { + for c in '\0'..='\u{10FFFF}' { + assert_eq!( + !c.is_cased() as u8 + + c.is_lowercase() as u8 + + c.is_uppercase() as u8 + + c.is_titlecase() as u8, + 1 + ); + } +} + #[test] fn test_is_whitespace() { assert!(' '.is_whitespace()); @@ -155,6 +212,41 @@ fn test_to_uppercase() { assert_eq!(upper('ᾀ'), "ἈΙ"); } +#[test] +fn test_to_casefold_unnormalized() { + fn fold(c: char) -> String { + let to_casefold = c.to_casefold_unnormalized(); + assert_eq!(to_casefold.len(), to_casefold.count()); + let iter: String = c.to_casefold_unnormalized().collect(); + let disp: String = c.to_casefold_unnormalized().to_string(); + assert_eq!(iter, disp); + let iter_rev: String = c.to_casefold_unnormalized().rev().collect(); + let disp_rev: String = disp.chars().rev().collect(); + assert_eq!(iter_rev, disp_rev); + iter + } + assert_eq!(fold('A'), "a"); + assert_eq!(fold('Ö'), "ö"); + assert_eq!(fold('ß'), "ss"); + assert_eq!(fold('ẞ'), "ss"); + assert_eq!(fold('Ü'), "ü"); + assert_eq!(fold('💩'), "💩"); + assert_eq!(fold('Σ'), "σ"); + assert_eq!(fold('ς'), "σ"); + assert_eq!(fold('Τ'), "τ"); + assert_eq!(fold('Ι'), "ι"); + assert_eq!(fold('Γ'), "γ"); + assert_eq!(fold('Μ'), "μ"); + assert_eq!(fold('Α'), "α"); + assert_eq!(fold('Dž'), "dž"); + assert_eq!(fold('fi'), "fi"); + assert_eq!(fold('İ'), "i\u{307}"); + assert_eq!(fold('ꮿ'), "Ꮿ"); + assert_eq!(fold('Ꮿ'), "Ꮿ"); + assert_eq!(fold('ῲ'), "ὼι"); + assert_eq!(fold('\u{0345}'), "ι"); +} + #[test] fn test_is_control() { assert!('\u{0}'.is_control()); @@ -207,6 +299,8 @@ fn test_escape_debug() { assert_eq!(string('\u{200b}'), "\\u{200b}"); // zero width space assert_eq!(string('\u{e000}'), "\\u{e000}"); // private use 1 assert_eq!(string('\u{100000}'), "\\u{100000}"); // private use 2 + assert_eq!(string('\u{ff9e}'), "\u{ff9e}"); // halfwidth dakuten + assert_eq!(string('\u{ff9f}'), "\u{ff9f}"); // halfwidth handakuten } #[test] @@ -261,7 +355,7 @@ fn test_encode_utf8() { let mut buf = [0; char::MAX_LEN_UTF8]; let ptr = buf.as_ptr(); let s = input.encode_utf8(&mut buf); - assert_eq!(s.as_ptr() as usize, ptr as usize); + assert_eq!(s.as_ptr(), ptr); assert!(str::from_utf8(s.as_bytes()).is_ok()); assert_eq!(s.as_bytes(), expect); } @@ -278,7 +372,7 @@ fn test_encode_utf16() { let mut buf = [0; 2]; let ptr = buf.as_mut_ptr(); let b = input.encode_utf16(&mut buf); - assert_eq!(b.as_mut_ptr() as usize, ptr as usize); + assert_eq!(b.as_mut_ptr(), ptr); assert_eq!(b, expect); } diff --git a/library/coretests/tests/cmp.rs b/library/coretests/tests/cmp.rs index 55e35a4a7250e..c739f3e290378 100644 --- a/library/coretests/tests/cmp.rs +++ b/library/coretests/tests/cmp.rs @@ -1,5 +1,5 @@ +use core::cmp; use core::cmp::Ordering::{self, *}; -use core::cmp::{self}; #[test] fn test_int_totalord() { @@ -48,6 +48,40 @@ fn test_ord_min_max_by() { assert_eq!(cmp::max_by(2, -1, f), 2); } +// Regression test for #136307 / #139357: ensure compare() receives (v1, v2), not (v2, v1). +#[test] +fn min_by_compare_argument_order() { + let mut order = vec![]; + let res = cmp::min_by(1i32, 2, |a, b| { + order.push((*a, *b)); + a.cmp(b) + }); + assert_eq!(res, 1); + assert_eq!(order, [(1, 2)]); +} + +#[test] +fn max_by_compare_argument_order() { + let mut order = vec![]; + let res = cmp::max_by(1i32, 2, |a, b| { + order.push((*a, *b)); + a.cmp(b) + }); + assert_eq!(res, 2); + assert_eq!(order, [(1, 2)]); +} + +#[test] +fn minmax_by_compare_argument_order() { + let mut order = vec![]; + let res = cmp::minmax_by(1i32, 2, |a, b| { + order.push((*a, *b)); + a.cmp(b) + }); + assert_eq!(res, [1, 2]); + assert_eq!(order, [(1, 2)]); +} + #[test] fn test_ord_min_max_by_key() { let f = |x: &i32| x.abs(); @@ -220,13 +254,13 @@ mod const_cmp { struct S(i32); - impl const PartialEq for S { + const impl PartialEq for S { fn eq(&self, other: &Self) -> bool { self.0 == other.0 } } - impl const PartialOrd for S { + const impl PartialOrd for S { fn partial_cmp(&self, other: &Self) -> Option { let ret = match (self.0, other.0) { (a, b) if a > b => Ordering::Greater, @@ -246,3 +280,12 @@ mod const_cmp { const _: () = assert!(S(0) < S(1)); const _: () = assert!(S(1) > S(0)); } + +mod const_splat { + use super::*; + + const _: () = assert!(cmp::smallest(1, 2, 3, 4) == 1); + const _: () = assert!(cmp::smallest(4, 3, 2, 1) == 1); + const _: () = assert!(cmp::largest(1, 2, 3, 4) == 4); + const _: () = assert!(cmp::largest(4, 3, 2, 1) == 4); +} diff --git a/library/coretests/tests/ffi/cstr.rs b/library/coretests/tests/ffi/cstr.rs index 7d669cc1c3fff..0fb98036b2675 100644 --- a/library/coretests/tests/ffi/cstr.rs +++ b/library/coretests/tests/ffi/cstr.rs @@ -1,5 +1,11 @@ use core::ffi::CStr; +#[test] +fn const_default() { + const S: &CStr = <_>::default(); + assert_eq!(S, c""); +} + #[test] fn compares_as_u8s() { let a: &CStr = c"Hello!"; // Starts with ascii diff --git a/library/coretests/tests/fmt/float.rs b/library/coretests/tests/fmt/float.rs index 003782f34dc93..4f7357761744b 100644 --- a/library/coretests/tests/fmt/float.rs +++ b/library/coretests/tests/fmt/float.rs @@ -1,3 +1,5 @@ +use core::fmt::{self, Write}; + #[test] fn test_format_f64() { assert_eq!("1", format!("{:.0}", 1.0f64)); @@ -170,6 +172,72 @@ fn test_format_f32_rounds_ties_to_even() { assert_eq!("-1.28E2", format!("{:.2E}", -128.5f32)); } +#[test] +fn test_format_f64_max_precision_exponential() { + struct ExactExpWriter { + prefix: &'static [u8], + zeroes_remaining: u32, + suffix: &'static [u8], + prefix_pos: usize, + suffix_pos: usize, + total_len: u32, + } + + impl ExactExpWriter { + fn new(prefix: &'static str, suffix: &'static str) -> Self { + Self { + prefix: prefix.as_bytes(), + zeroes_remaining: u16::MAX.into(), + suffix: suffix.as_bytes(), + prefix_pos: 0, + suffix_pos: 0, + total_len: 0, + } + } + + fn finish(self) { + assert_eq!(self.prefix_pos, self.prefix.len()); + assert_eq!(self.zeroes_remaining, 0); + assert_eq!(self.suffix_pos, self.suffix.len()); + assert_eq!(self.total_len, u32::from(u16::MAX) + 4); + } + } + + impl Write for ExactExpWriter { + fn write_str(&mut self, s: &str) -> fmt::Result { + for byte in s.bytes() { + self.total_len += 1; + + if self.prefix_pos < self.prefix.len() { + assert_eq!(byte, self.prefix[self.prefix_pos]); + self.prefix_pos += 1; + } else if self.zeroes_remaining > 0 { + assert_eq!(byte, b'0'); + self.zeroes_remaining -= 1; + } else { + assert!(self.suffix_pos < self.suffix.len()); + assert_eq!(byte, self.suffix[self.suffix_pos]); + self.suffix_pos += 1; + } + } + + Ok(()) + } + } + + fn assert_exact_exp(args: fmt::Arguments<'_>, prefix: &'static str, suffix: &'static str) { + let mut writer = ExactExpWriter::new(prefix, suffix); + fmt::write(&mut writer, args).unwrap(); + writer.finish(); + } + + assert_exact_exp(format_args!("{:.65535e}", 0.0f64), "0.", "e0"); + assert_exact_exp(format_args!("{:.65535e}", 1.0f64), "1.", "e0"); + assert_exact_exp(format_args!("{:.65535E}", 0.0f64), "0.", "E0"); + assert_exact_exp(format_args!("{:.65535E}", 1.0f64), "1.", "E0"); + assert_exact_exp(format_args!("{:65535.65535e}", 1.0f64), "1.", "e0"); +} + fn is_exponential(s: &str) -> bool { s.contains("e") || s.contains("E") } diff --git a/library/coretests/tests/hint.rs b/library/coretests/tests/hint.rs index d15730823eb5b..8eeb86b29a65f 100644 --- a/library/coretests/tests/hint.rs +++ b/library/coretests/tests/hint.rs @@ -3,7 +3,7 @@ fn select_unpredictable_drop() { use core::cell::Cell; struct X<'a>(&'a Cell); - impl const Drop for X<'_> { + const impl Drop for X<'_> { fn drop(&mut self) { self.0.set(true); } diff --git a/library/coretests/tests/intrinsics.rs b/library/coretests/tests/intrinsics.rs index c6d841b8383a8..e562f49b0a2fc 100644 --- a/library/coretests/tests/intrinsics.rs +++ b/library/coretests/tests/intrinsics.rs @@ -1,6 +1,7 @@ use core::any::TypeId; -use core::intrinsics::{assume, vtable_for}; +use core::intrinsics::assume; use std::fmt::Debug; +use std::intrinsics::type_id_vtable; use std::option::Option; use std::ptr::DynMetadata; @@ -198,15 +199,17 @@ fn carrying_mul_add_fallback_i128() { } #[test] -fn test_vtable_for() { +fn test_type_id_vtable() { #[derive(Debug)] struct A {} struct B {} - const A_VTABLE: Option> = vtable_for::(); + const A_VTABLE: Option> = + type_id_vtable(TypeId::of::(), TypeId::of::()); assert!(A_VTABLE.is_some()); - const B_VTABLE: Option> = vtable_for::(); + const B_VTABLE: Option> = + type_id_vtable(TypeId::of::(), TypeId::of::()); assert!(B_VTABLE.is_none()); } diff --git a/library/coretests/tests/io/borrowed_buf.rs b/library/coretests/tests/io/borrowed_buf.rs index aaa98d26ff8b9..fbd44b629361d 100644 --- a/library/coretests/tests/io/borrowed_buf.rs +++ b/library/coretests/tests/io/borrowed_buf.rs @@ -5,10 +5,32 @@ use core::mem::MaybeUninit; #[test] fn new() { let buf: &mut [_] = &mut [0; 16]; - let mut rbuf: BorrowedBuf<'_> = buf.into(); + let mut rbuf: BorrowedBuf<'_, u8> = buf.into(); assert_eq!(rbuf.filled().len(), 0); - assert_eq!(rbuf.init_len(), 16); + assert!(rbuf.is_init()); + assert_eq!(rbuf.capacity(), 16); + assert_eq!(rbuf.unfilled().capacity(), 16); +} + +#[test] +fn new_u64() { + let buf: &mut [_] = &mut [0u64; 16]; + let mut rbuf = BorrowedBuf::from(buf); + + assert_eq!(rbuf.filled().len(), 0); + assert!(rbuf.is_init()); + assert_eq!(rbuf.capacity(), 16); + assert_eq!(rbuf.unfilled().capacity(), 16); +} + +#[test] +fn new_unit() { + let buf: &mut [_] = &mut [(); 16]; + let mut rbuf = BorrowedBuf::from(buf); + + assert_eq!(rbuf.filled().len(), 0); + assert!(rbuf.is_init()); assert_eq!(rbuf.capacity(), 16); assert_eq!(rbuf.unfilled().capacity(), 16); } @@ -17,10 +39,32 @@ fn new() { #[test] fn uninit() { let buf: &mut [_] = &mut [MaybeUninit::uninit(); 16]; - let mut rbuf: BorrowedBuf<'_> = buf.into(); + let mut rbuf: BorrowedBuf<'_, u8> = buf.into(); + + assert_eq!(rbuf.filled().len(), 0); + assert!(!rbuf.is_init()); + assert_eq!(rbuf.capacity(), 16); + assert_eq!(rbuf.unfilled().capacity(), 16); +} + +#[test] +fn uninit_u64() { + let buf: &mut [_] = &mut [MaybeUninit::::uninit(); 16]; + let mut rbuf = BorrowedBuf::::from(buf); + + assert_eq!(rbuf.filled().len(), 0); + assert!(!rbuf.is_init()); + assert_eq!(rbuf.capacity(), 16); + assert_eq!(rbuf.unfilled().capacity(), 16); +} + +#[test] +fn uninit_unit() { + let buf: &mut [_] = &mut [MaybeUninit::<()>::uninit(); 16]; + let mut rbuf = BorrowedBuf::<()>::from(buf); assert_eq!(rbuf.filled().len(), 0); - assert_eq!(rbuf.init_len(), 0); + assert!(!rbuf.is_init()); assert_eq!(rbuf.capacity(), 16); assert_eq!(rbuf.unfilled().capacity(), 16); } @@ -28,19 +72,41 @@ fn uninit() { #[test] fn initialize_unfilled() { let buf: &mut [_] = &mut [MaybeUninit::uninit(); 16]; - let mut rbuf: BorrowedBuf<'_> = buf.into(); + let mut rbuf: BorrowedBuf<'_, u8> = buf.into(); rbuf.unfilled().ensure_init(); - assert_eq!(rbuf.init_len(), 16); + assert!(rbuf.is_init()); } #[test] fn advance_filled() { let buf: &mut [_] = &mut [0; 16]; - let mut rbuf: BorrowedBuf<'_> = buf.into(); + let mut rbuf: BorrowedBuf<'_, u8> = buf.into(); - rbuf.unfilled().advance(1); + rbuf.unfilled().advance_checked(1); + + assert_eq!(rbuf.filled().len(), 1); + assert_eq!(rbuf.unfilled().capacity(), 15); +} + +#[test] +fn advance_filled_u64() { + let buf: &mut [_] = &mut [0u64; 16]; + let mut rbuf = BorrowedBuf::from(buf); + + rbuf.unfilled().advance_checked(1); + + assert_eq!(rbuf.filled().len(), 1); + assert_eq!(rbuf.unfilled().capacity(), 15); +} + +#[test] +fn advance_filled_unit() { + let buf: &mut [_] = &mut [(); 16]; + let mut rbuf = BorrowedBuf::from(buf); + + rbuf.unfilled().advance_checked(1); assert_eq!(rbuf.filled().len(), 1); assert_eq!(rbuf.unfilled().capacity(), 15); @@ -49,9 +115,9 @@ fn advance_filled() { #[test] fn clear() { let buf: &mut [_] = &mut [255; 16]; - let mut rbuf: BorrowedBuf<'_> = buf.into(); + let mut rbuf: BorrowedBuf<'_, u8> = buf.into(); - rbuf.unfilled().advance(16); + rbuf.unfilled().advance_checked(16); assert_eq!(rbuf.filled().len(), 16); assert_eq!(rbuf.unfilled().capacity(), 0); @@ -61,43 +127,123 @@ fn clear() { assert_eq!(rbuf.filled().len(), 0); assert_eq!(rbuf.unfilled().capacity(), 16); - assert_eq!(rbuf.unfilled().init_mut(), [255; 16]); + assert_eq!(rbuf.unfilled().ensure_init(), [255; 16]); +} + +#[test] +fn clear_u64() { + let buf: &mut [_] = &mut [255u64; 16]; + let mut rbuf = BorrowedBuf::from(buf); + + rbuf.unfilled().advance_checked(16); + + assert_eq!(rbuf.filled().len(), 16); + assert_eq!(rbuf.unfilled().capacity(), 0); + + rbuf.clear(); + + assert_eq!(rbuf.filled().len(), 0); + assert_eq!(rbuf.unfilled().capacity(), 16); + + unsafe { + rbuf.set_init(); + } + rbuf.unfilled().advance_checked(16); + assert_eq!(rbuf.filled(), [255; 16]); +} + +#[test] +fn clear_unit() { + let buf: &mut [_] = &mut [(); 16]; + let mut rbuf = BorrowedBuf::from(buf); + + rbuf.unfilled().advance_checked(16); + + assert_eq!(rbuf.filled().len(), 16); + assert_eq!(rbuf.unfilled().capacity(), 0); + + rbuf.clear(); + + assert_eq!(rbuf.filled().len(), 0); + assert_eq!(rbuf.unfilled().capacity(), 16); + + unsafe { + rbuf.set_init(); + } + rbuf.unfilled().advance_checked(16); + assert_eq!(rbuf.filled(), [(); 16]); } #[test] fn set_init() { let buf: &mut [_] = &mut [MaybeUninit::zeroed(); 16]; - let mut rbuf: BorrowedBuf<'_> = buf.into(); + let mut rbuf: BorrowedBuf<'_, u8> = buf.into(); unsafe { - rbuf.set_init(8); + rbuf.set_init(); } - assert_eq!(rbuf.init_len(), 8); + assert!(rbuf.is_init()); + rbuf.unfilled().advance_checked(16); + assert_eq!(rbuf.filled(), [0; 16]); +} - rbuf.unfilled().advance(4); +#[test] +fn set_init_u64() { + let buf: &mut [_] = &mut [MaybeUninit::::zeroed(); 16]; + let mut rbuf = BorrowedBuf::::from(buf); unsafe { - rbuf.set_init(2); + rbuf.set_init(); } - assert_eq!(rbuf.init_len(), 8); + assert!(rbuf.is_init()); + rbuf.unfilled().advance_checked(16); + assert_eq!(rbuf.filled(), [0; 16]); +} + +#[test] +fn set_init_unit() { + let buf: &mut [_] = &mut [MaybeUninit::<()>::zeroed(); 16]; + let mut rbuf = BorrowedBuf::<()>::from(buf); unsafe { - rbuf.set_init(8); + rbuf.set_init(); } - assert_eq!(rbuf.init_len(), 8); + assert!(rbuf.is_init()); + rbuf.unfilled().advance_checked(16); + assert_eq!(rbuf.filled(), [(); 16]); } #[test] fn append() { let buf: &mut [_] = &mut [MaybeUninit::new(255); 16]; - let mut rbuf: BorrowedBuf<'_> = buf.into(); + let mut rbuf: BorrowedBuf<'_, u8> = buf.into(); + + rbuf.unfilled().append(&[0; 8]); + + assert!(!rbuf.is_init()); + assert_eq!(rbuf.filled().len(), 8); + assert_eq!(rbuf.filled(), [0; 8]); + + rbuf.clear(); + + rbuf.unfilled().append(&[1; 16]); + + assert!(!rbuf.is_init()); + assert_eq!(rbuf.filled().len(), 16); + assert_eq!(rbuf.filled(), [1; 16]); +} + +#[test] +fn append_u64() { + let buf: &mut [_] = &mut [MaybeUninit::new(255u64); 16]; + let mut rbuf = BorrowedBuf::::from(buf); rbuf.unfilled().append(&[0; 8]); - assert_eq!(rbuf.init_len(), 8); + assert!(!rbuf.is_init()); assert_eq!(rbuf.filled().len(), 8); assert_eq!(rbuf.filled(), [0; 8]); @@ -105,15 +251,35 @@ fn append() { rbuf.unfilled().append(&[1; 16]); - assert_eq!(rbuf.init_len(), 16); + assert!(!rbuf.is_init()); assert_eq!(rbuf.filled().len(), 16); assert_eq!(rbuf.filled(), [1; 16]); } +#[test] +fn append_unit() { + let buf: &mut [_] = &mut [MaybeUninit::new(()); 16]; + let mut rbuf = BorrowedBuf::<()>::from(buf); + + rbuf.unfilled().append(&[(); 8]); + + assert!(!rbuf.is_init()); + assert_eq!(rbuf.filled().len(), 8); + assert_eq!(rbuf.filled(), [(); 8]); + + rbuf.clear(); + + rbuf.unfilled().append(&[(); 16]); + + assert!(!rbuf.is_init()); + assert_eq!(rbuf.filled().len(), 16); + assert_eq!(rbuf.filled(), [(); 16]); +} + #[test] fn reborrow_written() { let buf: &mut [_] = &mut [MaybeUninit::new(0); 32]; - let mut buf: BorrowedBuf<'_> = buf.into(); + let mut buf: BorrowedBuf<'_, u8> = buf.into(); let mut cursor = buf.unfilled(); cursor.append(&[1; 16]); @@ -125,41 +291,115 @@ fn reborrow_written() { assert_eq!(cursor.written(), 32); assert_eq!(buf.unfilled().written(), 32); - assert_eq!(buf.init_len(), 32); + assert!(!buf.is_init()); assert_eq!(buf.filled().len(), 32); let filled = buf.filled(); assert_eq!(&filled[..16], [1; 16]); assert_eq!(&filled[16..], [2; 16]); } +#[test] +fn reborrow_written_u64() { + let buf: &mut [_] = &mut [MaybeUninit::new(0u64); 32]; + let mut buf = BorrowedBuf::::from(buf); + + let mut cursor = buf.unfilled(); + cursor.append(&[1; 16]); + + let mut cursor2 = cursor.reborrow(); + cursor2.append(&[2; 16]); + + assert_eq!(cursor2.written(), 32); + assert_eq!(cursor.written(), 32); + + assert_eq!(buf.unfilled().written(), 32); + assert!(!buf.is_init()); + assert_eq!(buf.filled().len(), 32); + let filled = buf.filled(); + assert_eq!(&filled[..16], [1; 16]); + assert_eq!(&filled[16..], [2; 16]); +} + +#[test] +fn reborrow_written_unit() { + let buf: &mut [_] = &mut [MaybeUninit::new(()); 32]; + let mut buf = BorrowedBuf::<()>::from(buf); + + let mut cursor = buf.unfilled(); + cursor.append(&[(); 16]); + + let mut cursor2 = cursor.reborrow(); + cursor2.append(&[(); 16]); + + assert_eq!(cursor2.written(), 32); + assert_eq!(cursor.written(), 32); + + assert_eq!(buf.unfilled().written(), 32); + assert!(!buf.is_init()); + assert_eq!(buf.filled().len(), 32); + let filled = buf.filled(); + assert_eq!(&filled[..16], [(); 16]); + assert_eq!(&filled[16..], [(); 16]); +} + #[test] fn cursor_set_init() { let buf: &mut [_] = &mut [MaybeUninit::zeroed(); 16]; - let mut rbuf: BorrowedBuf<'_> = buf.into(); + let mut rbuf: BorrowedBuf<'_, u8> = buf.into(); + let mut cursor = rbuf.unfilled(); unsafe { - rbuf.unfilled().set_init(8); + cursor.set_init(); } - assert_eq!(rbuf.init_len(), 8); - assert_eq!(rbuf.unfilled().init_mut().len(), 8); - assert_eq!(unsafe { rbuf.unfilled().as_mut().len() }, 16); + assert!(cursor.is_init()); + assert_eq!(unsafe { cursor.as_mut().len() }, 16); + + cursor.advance_checked(4); + + assert_eq!(unsafe { cursor.as_mut().len() }, 12); - rbuf.unfilled().advance(4); + assert!(rbuf.is_init()); +} + +#[test] +fn cursor_set_init_u64() { + let buf: &mut [_] = &mut [MaybeUninit::::zeroed(); 16]; + let mut rbuf = BorrowedBuf::::from(buf); + let mut cursor = rbuf.unfilled(); unsafe { - rbuf.unfilled().set_init(2); + cursor.set_init(); } - assert_eq!(rbuf.init_len(), 8); + assert!(cursor.is_init()); + assert_eq!(unsafe { cursor.as_mut().len() }, 16); + + cursor.advance_checked(4); + + assert_eq!(unsafe { cursor.as_mut().len() }, 12); + + assert!(rbuf.is_init()); +} + +#[test] +fn cursor_set_init_unit() { + let buf: &mut [_] = &mut [MaybeUninit::<()>::zeroed(); 16]; + let mut rbuf = BorrowedBuf::<()>::from(buf); + let mut cursor = rbuf.unfilled(); unsafe { - rbuf.unfilled().set_init(8); + cursor.set_init(); } - assert_eq!(rbuf.init_len(), 12); - assert_eq!(rbuf.unfilled().init_mut().len(), 8); - assert_eq!(unsafe { rbuf.unfilled().as_mut().len() }, 12); + assert!(cursor.is_init()); + assert_eq!(unsafe { cursor.as_mut().len() }, 16); + + cursor.advance_checked(4); + + assert_eq!(unsafe { cursor.as_mut().len() }, 12); + + assert!(rbuf.is_init()); } #[test] @@ -173,26 +413,26 @@ fn cursor_with_unfilled_buf() { assert_eq!(buf.filled(), &[1, 2, 3]); }); - assert_eq!(cursor.init_mut().len(), 0); + assert!(!cursor.is_init()); assert_eq!(cursor.written(), 3); cursor.with_unfilled_buf(|buf| { assert_eq!(buf.capacity(), 13); - assert_eq!(buf.init_len(), 0); + assert!(!buf.is_init()); buf.unfilled().ensure_init(); - buf.unfilled().advance(4); + buf.unfilled().advance_checked(4); }); - assert_eq!(cursor.init_mut().len(), 9); + assert!(cursor.is_init()); assert_eq!(cursor.written(), 7); cursor.with_unfilled_buf(|buf| { assert_eq!(buf.capacity(), 9); - assert_eq!(buf.init_len(), 9); + assert!(buf.is_init()); }); - assert_eq!(cursor.init_mut().len(), 9); + assert!(cursor.is_init()); assert_eq!(cursor.written(), 7); assert_eq!(rbuf.filled(), &[1, 2, 3, 0, 0, 0, 0]); diff --git a/library/coretests/tests/io/error.rs b/library/coretests/tests/io/error.rs new file mode 100644 index 0000000000000..62f6f6cace8b3 --- /dev/null +++ b/library/coretests/tests/io/error.rs @@ -0,0 +1,11 @@ +use core::io::RawOsError; + +/// On all targets to date, [`RawOsError`] is equivalent to a `c_int`, with the +/// notable exception of UEFI, where it is instead defined as `usize`. +#[test] +fn raw_os_error_ffi_guarantees() { + let _: RawOsError = cfg_select! { + target_os = "uefi" => 0 as usize, + _ => 0 as core::ffi::c_int, + }; +} diff --git a/library/coretests/tests/io/io_slice.rs b/library/coretests/tests/io/io_slice.rs new file mode 100644 index 0000000000000..4639ef2c6ac41 --- /dev/null +++ b/library/coretests/tests/io/io_slice.rs @@ -0,0 +1,100 @@ +use core::io::{IoSlice, IoSliceMut}; +use core::ops::Deref; + +#[test] +fn io_slice_mut_advance_slices() { + let mut buf1 = [1; 8]; + let mut buf2 = [2; 16]; + let mut buf3 = [3; 8]; + let mut bufs = &mut [ + IoSliceMut::new(&mut buf1), + IoSliceMut::new(&mut buf2), + IoSliceMut::new(&mut buf3), + ][..]; + + // Only in a single buffer.. + IoSliceMut::advance_slices(&mut bufs, 1); + assert_eq!(bufs[0].deref(), [1; 7].as_ref()); + assert_eq!(bufs[1].deref(), [2; 16].as_ref()); + assert_eq!(bufs[2].deref(), [3; 8].as_ref()); + + // Removing a buffer, leaving others as is. + IoSliceMut::advance_slices(&mut bufs, 7); + assert_eq!(bufs[0].deref(), [2; 16].as_ref()); + assert_eq!(bufs[1].deref(), [3; 8].as_ref()); + + // Removing a buffer and removing from the next buffer. + IoSliceMut::advance_slices(&mut bufs, 18); + assert_eq!(bufs[0].deref(), [3; 6].as_ref()); +} + +#[test] +#[should_panic] +fn io_slice_mut_advance_slices_empty_slice() { + let mut empty_bufs = &mut [][..]; + IoSliceMut::advance_slices(&mut empty_bufs, 1); +} + +#[test] +#[should_panic] +fn io_slice_mut_advance_slices_beyond_total_length() { + let mut buf1 = [1; 8]; + let mut bufs = &mut [IoSliceMut::new(&mut buf1)][..]; + + IoSliceMut::advance_slices(&mut bufs, 9); + assert!(bufs.is_empty()); +} + +#[test] +fn io_slice_advance_slices() { + let buf1 = [1; 8]; + let buf2 = [2; 16]; + let buf3 = [3; 8]; + let mut bufs = &mut [IoSlice::new(&buf1), IoSlice::new(&buf2), IoSlice::new(&buf3)][..]; + + // Only in a single buffer.. + IoSlice::advance_slices(&mut bufs, 1); + assert_eq!(bufs[0].deref(), [1; 7].as_ref()); + assert_eq!(bufs[1].deref(), [2; 16].as_ref()); + assert_eq!(bufs[2].deref(), [3; 8].as_ref()); + + // Removing a buffer, leaving others as is. + IoSlice::advance_slices(&mut bufs, 7); + assert_eq!(bufs[0].deref(), [2; 16].as_ref()); + assert_eq!(bufs[1].deref(), [3; 8].as_ref()); + + // Removing a buffer and removing from the next buffer. + IoSlice::advance_slices(&mut bufs, 18); + assert_eq!(bufs[0].deref(), [3; 6].as_ref()); +} + +#[test] +#[should_panic] +fn io_slice_advance_slices_empty_slice() { + let mut empty_bufs = &mut [][..]; + IoSlice::advance_slices(&mut empty_bufs, 1); +} + +#[test] +#[should_panic] +fn io_slice_advance_slices_beyond_total_length() { + let buf1 = [1; 8]; + let mut bufs = &mut [IoSlice::new(&buf1)][..]; + + IoSlice::advance_slices(&mut bufs, 9); + assert!(bufs.is_empty()); +} + +#[test] +fn io_slice_as_slice() { + let buf = [1; 8]; + let slice = IoSlice::new(&buf).as_slice(); + assert_eq!(slice, buf); +} + +#[test] +fn io_slice_into_slice() { + let mut buf = [1; 8]; + let slice = IoSliceMut::new(&mut buf).into_slice(); + assert_eq!(slice, [1; 8]); +} diff --git a/library/coretests/tests/io/mod.rs b/library/coretests/tests/io/mod.rs index a24893a525a9d..9341f1d85550b 100644 --- a/library/coretests/tests/io/mod.rs +++ b/library/coretests/tests/io/mod.rs @@ -1 +1,3 @@ mod borrowed_buf; +mod error; +mod io_slice; diff --git a/library/coretests/tests/iter/adapters/array_chunks.rs b/library/coretests/tests/iter/adapters/array_chunks.rs index e6e279b14e626..480d3138bdb35 100644 --- a/library/coretests/tests/iter/adapters/array_chunks.rs +++ b/library/coretests/tests/iter/adapters/array_chunks.rs @@ -1,4 +1,4 @@ -use core::iter::{self}; +use core::iter; use super::*; diff --git a/library/coretests/tests/iter/adapters/filter.rs b/library/coretests/tests/iter/adapters/filter.rs index 167851e33336e..14cd3cbd58f10 100644 --- a/library/coretests/tests/iter/adapters/filter.rs +++ b/library/coretests/tests/iter/adapters/filter.rs @@ -63,3 +63,15 @@ fn test_next_chunk_does_not_leak() { assert_eq!(Rc::strong_count(w), 1); } } + +#[test] +fn test_next_chunk_back_does_not_leak() { + let drop_witness: [_; 5] = std::array::from_fn(|_| Rc::new(())); + + let v = (0..5).map(|i| drop_witness[i].clone()).collect::>(); + let _ = v.into_iter().filter(|_| false).next_chunk_back::<1>(); + + for ref w in drop_witness { + assert_eq!(Rc::strong_count(w), 1); + } +} diff --git a/library/coretests/tests/iter/adapters/intersperse.rs b/library/coretests/tests/iter/adapters/intersperse.rs index 72ae59b6b2f5f..bcb7709077cd7 100644 --- a/library/coretests/tests/iter/adapters/intersperse.rs +++ b/library/coretests/tests/iter/adapters/intersperse.rs @@ -152,3 +152,189 @@ fn test_try_fold_specialization_intersperse_err() { iter.try_for_each(|item| if item == "b" { None } else { Some(()) }); assert_eq!(iter.next(), None); } + +#[test] +fn test_non_fused_iterator_intersperse() { + #[derive(Debug)] + struct TestCounter { + counter: usize, + } + + /// Given a counter of 0, this produces: + /// `None` -> `Some(2)` -> `None` -> `Some(4)` -> `None` -> `Some(6)` + /// -> and then `None` endlessly + impl Iterator for TestCounter { + type Item = usize; + fn next(&mut self) -> Option { + if self.counter > 6 { + None + } else if self.counter % 2 == 0 { + self.counter += 1; + None + } else { + self.counter += 1; + Some(self.counter) + } + } + } + + let counter = 0; + // places a 1 between `Some(_)` items + let non_fused_iter = TestCounter { counter }; + let mut intersperse_iter = non_fused_iter.intersperse(1); + // Interspersed iter produces: + // `None` -> `Some(2)` -> `None` -> `Some(1)` -> Some(4)` -> `None` -> `Some(1)` -> + // `Some(6)` -> and then `None` endlessly + assert_eq!(intersperse_iter.next(), None); + assert_eq!(intersperse_iter.next(), Some(2)); + assert_eq!(intersperse_iter.next(), None); + assert_eq!(intersperse_iter.next(), Some(1)); + assert_eq!(intersperse_iter.next(), Some(4)); + assert_eq!(intersperse_iter.next(), None); + assert_eq!(intersperse_iter.next(), Some(1)); + assert_eq!(intersperse_iter.next(), Some(6)); + assert_eq!(intersperse_iter.next(), None); + + // Extra check to make sure it is `None` after processing all items + assert_eq!(intersperse_iter.next(), None); +} + +#[test] +fn test_non_fused_iterator_intersperse_2() { + #[derive(Debug)] + struct TestCounter { + counter: usize, + } + + // Given a counter of 0, this produces: + // `Some(1)` -> `Some(2)` -> `None` -> `Some(4)` -> `Some(5)` -> + // and then `None` endlessly + impl Iterator for TestCounter { + type Item = usize; + fn next(&mut self) -> Option { + if self.counter < 5 { + self.counter += 1; + if self.counter % 3 != 0 { + return Some(self.counter); + } else { + return None; + } + } + self.counter += 1; + None + } + } + + let counter = 0; + // places a 100 between `Some(_)` items + let non_fused_iter = TestCounter { counter }; + let mut intersperse_iter = non_fused_iter.intersperse(100); + // Interspersed iter produces: + // `Some(1)` -> `Some(100)` -> `Some(2)` -> `None` -> `Some(100)` + // -> `Some(4)` -> `Some(100)` -> `Some(5)` -> `None` endlessly + assert_eq!(intersperse_iter.next(), Some(1)); + assert_eq!(intersperse_iter.next(), Some(100)); + assert_eq!(intersperse_iter.next(), Some(2)); + assert_eq!(intersperse_iter.next(), None); + assert_eq!(intersperse_iter.next(), Some(100)); + assert_eq!(intersperse_iter.next(), Some(4)); + assert_eq!(intersperse_iter.next(), Some(100)); + assert_eq!(intersperse_iter.next(), Some(5)); + assert_eq!(intersperse_iter.next(), None); + + // Extra check to make sure it is `None` after processing 6 items + assert_eq!(intersperse_iter.next(), None); +} + +#[test] +fn test_non_fused_iterator_intersperse_with() { + #[derive(Debug)] + struct TestCounter { + counter: usize, + } + + // Given a counter of 0, this produces: + // `None` -> `Some(2)` -> `None` -> `Some(4)` -> `None` -> `Some(6)` + // -> and then `None` endlessly + impl Iterator for TestCounter { + type Item = usize; + fn next(&mut self) -> Option { + if self.counter > 6 { + None + } else if self.counter % 2 == 0 { + self.counter += 1; + None + } else { + self.counter += 1; + Some(self.counter) + } + } + } + + let counter = 0; + let non_fused_iter = TestCounter { counter }; + // places a 2 between `Some(_)` items + let mut intersperse_iter = non_fused_iter.intersperse_with(|| 1); + // Interspersed iter produces: + // `None` -> `Some(2)` -> `None` -> `Some(1)` -> Some(4)` -> `None` -> `Some(1)` -> + // `Some(6)` -> and then `None` endlessly + assert_eq!(intersperse_iter.next(), None); + assert_eq!(intersperse_iter.next(), Some(2)); + assert_eq!(intersperse_iter.next(), None); + assert_eq!(intersperse_iter.next(), Some(1)); + assert_eq!(intersperse_iter.next(), Some(4)); + assert_eq!(intersperse_iter.next(), None); + assert_eq!(intersperse_iter.next(), Some(1)); + assert_eq!(intersperse_iter.next(), Some(6)); + assert_eq!(intersperse_iter.next(), None); + + // Extra check to make sure it is `None` after processing 6 items + assert_eq!(intersperse_iter.next(), None); +} + +#[test] +fn test_non_fused_iterator_intersperse_with_2() { + #[derive(Debug)] + struct TestCounter { + counter: usize, + } + + // Given a counter of 0, this produces: + // `Some(1)` -> `Some(2)` -> `None` -> `Some(4)` -> `Some(5)` -> + // and then `None` endlessly + impl Iterator for TestCounter { + type Item = usize; + fn next(&mut self) -> Option { + if self.counter < 5 { + self.counter += 1; + if self.counter % 3 != 0 { + return Some(self.counter); + } else { + return None; + } + } + self.counter += 1; + None + } + } + + let counter = 0; + // places a 100 between `Some(_)` items + let non_fused_iter = TestCounter { counter }; + let mut intersperse_iter = non_fused_iter.intersperse_with(|| 100); + // Interspersed iter produces: + // `Some(1)` -> `Some(100)` -> `Some(2)` -> `None` -> `Some(100)` + // -> `Some(4)` -> `Some(100)` -> `Some(5)` -> `None` endlessly + assert_eq!(intersperse_iter.next(), Some(1)); + assert_eq!(intersperse_iter.next(), Some(100)); + assert_eq!(intersperse_iter.next(), Some(2)); + assert_eq!(intersperse_iter.next(), None); + assert_eq!(intersperse_iter.next(), Some(100)); + assert_eq!(intersperse_iter.next(), Some(4)); + assert_eq!(intersperse_iter.next(), Some(100)); + assert_eq!(intersperse_iter.next(), Some(5)); + assert_eq!(intersperse_iter.next(), None); + + // Extra check to make sure it is `None` after processing 6 items + assert_eq!(intersperse_iter.next(), None); +} diff --git a/library/coretests/tests/iter/adapters/map_windows.rs b/library/coretests/tests/iter/adapters/map_windows.rs index 01cebc9b27fd8..9e8068387f1e5 100644 --- a/library/coretests/tests/iter/adapters/map_windows.rs +++ b/library/coretests/tests/iter/adapters/map_windows.rs @@ -5,7 +5,7 @@ use std::sync::atomic::Ordering::SeqCst; mod drop_checks { //! These tests mainly make sure the elements are correctly dropped. - use std::sync::atomic::Ordering::SeqCst; + use std::sync::atomic::Ordering::{Relaxed, SeqCst}; use std::sync::atomic::{AtomicBool, AtomicUsize}; #[derive(Debug)] @@ -143,6 +143,51 @@ mod drop_checks { check::<5>(5, 1); check::<5>(5, 4); } + + /// Regression test for #156501 + #[test] + fn panicking_clone() { + static CLONE_COUNTER: AtomicUsize = AtomicUsize::new(0); + static DROP_COUNTER: AtomicUsize = AtomicUsize::new(0); + + struct PanickingClone(u8); + + impl Clone for PanickingClone { + fn clone(&self) -> Self { + if CLONE_COUNTER.fetch_add(1, Relaxed) == 3 { + panic!( + "⚞(· <:::> ·)⚟ aaaaaah its the turbofish monster!!! its gonna eat us all!!!1!" + ); + } + + Self(self.0) + } + } + + impl Drop for PanickingClone { + fn drop(&mut self) { + assert_eq!(self.0, 42); + + DROP_COUNTER.fetch_add(1, Relaxed); + } + } + + let array = [const { PanickingClone(42) }; 17]; + let mut iter = array.into_iter().map_windows::<_, (), 17>(|_| ()); + + // initialize the buffer + iter.next(); + + let result = std::panic::catch_unwind(|| { + // now do the clones and panic. + // this should't try to drop uninitialized memory + let _ = iter.clone(); + }); + + assert!(result.is_err()); + + assert_eq!(DROP_COUNTER.load(Relaxed), 3); + } } #[test] @@ -172,6 +217,7 @@ fn test_case_from_pr_82413_comment() { #[test] #[should_panic = "array in `Iterator::map_windows` must contain more than 0 elements"] +#[allow(unconditional_panic)] fn check_zero_window() { let _ = std::iter::repeat(0).map_windows(|_: &[_; 0]| ()); } @@ -284,3 +330,29 @@ fn test_size_hint() { check_size_hint::<5>((5, Some(5)), (1, Some(1))); check_size_hint::<5>((5, Some(10)), (1, Some(6))); } + +#[test] +fn test_unfused() { + #[derive(Default)] + struct UnfusedIter(usize); + impl Iterator for UnfusedIter { + type Item = usize; + + fn next(&mut self) -> Option { + let curr = self.0; + self.0 += 1; + if curr % 7 == 0 { None } else { Some(curr) } + } + } + + let mut iter = UnfusedIter(1).map_windows(|a: &[_; 3]| *a); + assert_eq!(iter.by_ref().collect::>(), vec![[1, 2, 3], [2, 3, 4], [3, 4, 5], [4, 5, 6]]); + assert_eq!( + iter.by_ref().collect::>(), + vec![[8, 9, 10], [9, 10, 11], [10, 11, 12], [11, 12, 13]] + ); + assert_eq!( + iter.by_ref().collect::>(), + vec![[15, 16, 17], [16, 17, 18], [17, 18, 19], [18, 19, 20]] + ); +} diff --git a/library/coretests/tests/iter/adapters/step_by.rs b/library/coretests/tests/iter/adapters/step_by.rs index 6f3300e7a8820..7580b6fb9f8af 100644 --- a/library/coretests/tests/iter/adapters/step_by.rs +++ b/library/coretests/tests/iter/adapters/step_by.rs @@ -93,6 +93,46 @@ fn test_iterator_step_by_nth_overflow() { assert_eq!(it.0, (usize::MAX as Bigger) * 1); } +#[test] +#[allow(non_local_definitions)] +fn test_iterator_step_by_nth_overflow_on_none() { + #[cfg(target_pointer_width = "16")] + type Bigger = u32; + #[cfg(target_pointer_width = "32")] + type Bigger = u64; + #[cfg(target_pointer_width = "64")] + type Bigger = u128; + + #[derive(Clone)] + struct Test(Bigger); + impl Iterator for &mut Test { + type Item = i32; + fn next(&mut self) -> Option { + None + } + fn nth(&mut self, n: usize) -> Option { + self.0 += n as Bigger + 1; + None + } + } + + // usize::MAX * usize::MAX overflow + let mut it = Test(0); + let mut step_by = (&mut it).step_by(usize::MAX); + // first next() call sets StepBy's first_take to false + assert_eq!(step_by.next(), None); + assert_eq!(step_by.nth(usize::MAX), None); + assert_eq!(it.0, usize::MAX as Bigger + 1); + + // usize::MAX * (usize::MAX - 1) overflow + let mut it = Test(0); + let mut step_by = (&mut it).step_by(usize::MAX); + // first next() call sets StepBy's first_take to false + assert_eq!(step_by.next(), None); + assert_eq!(step_by.nth(usize::MAX - 1), None); + assert_eq!(it.0, usize::MAX as Bigger + 1); +} + #[test] fn test_iterator_step_by_nth_try_fold() { let mut it = (0..).step_by(10); @@ -299,3 +339,95 @@ fn test_step_by_fold_range_specialization() { assert_eq!(r.sum::(), usize::MAX - 1); }); } + +#[test] +fn test_step_by_new_range_iter() { + use core::range::Range as NewRange; + + // forward iteration + let v: Vec = NewRange::from(0_u32..10).into_iter().step_by(3).collect(); + assert_eq!(v, [0, 3, 6, 9]); + + // size_hint + assert_eq!(NewRange::from(0_u32..10).into_iter().step_by(3).size_hint(), (4, Some(4))); + assert_eq!(NewRange::from(0_u32..9).into_iter().step_by(3).size_hint(), (3, Some(3))); + + // nth + assert_eq!(NewRange::from(0_u32..20).into_iter().step_by(5).nth(2), Some(10)); + + // empty range + assert_eq!(NewRange::from(5_u32..5).into_iter().step_by(1).next(), None); + + // step larger than range + assert_eq!(NewRange::from(0_u32..3).into_iter().step_by(10).collect::>(), [0]); + + // backward iteration (usize has ExactSizeIterator) + let mut it = NewRange::from(0_usize..11).into_iter().step_by(3); + assert_eq!(it.next_back(), Some(9)); + assert_eq!(it.next_back(), Some(6)); + assert_eq!(it.next_back(), Some(3)); + assert_eq!(it.next_back(), Some(0)); + assert_eq!(it.next_back(), None); + + // interleaved forward and backward + let mut it = NewRange::from(0_usize..16).into_iter().step_by(5); + assert_eq!(it.next(), Some(0)); + assert_eq!(it.next_back(), Some(15)); + assert_eq!(it.next(), Some(5)); + assert_eq!(it.next_back(), Some(10)); + assert_eq!(it.next(), None); +} + +#[test] +fn test_step_by_nth_non_fused() { + struct StepByNthOne { + exhausted: bool, + } + impl Iterator for StepByNthOne { + type Item = i32; + fn next(&mut self) -> Option { + if self.exhausted { + Some(0) + } else { + self.exhausted = true; + None + } + } + } + + let mut iter = StepByNthOne { exhausted: false }.step_by(1); + assert_eq!(iter.nth(1), None) +} + +#[test] +fn test_step_by_nth_non_fused_on_non_first_take() { + struct StepByOneNthMax(i32); + impl Iterator for StepByOneNthMax { + type Item = i32; + fn next(&mut self) -> Option { + let prev = self.0; + self.0 += 1; + if prev == 1 { None } else { Some(prev) } + } + } + + let mut iter = StepByOneNthMax(0).step_by(1); + // sets StepBy iterator first_take field to false + assert_eq!(iter.next(), Some(0)); + // Our underlying iterator should be pointing at a `None` item + // so we should expect `StepBy::nth` to return `None` + assert_eq!(iter.nth(usize::MAX), None) +} + +#[test] +fn test_step_by_fused() { + // `StepBy` is fused whenever the underlying iterator is fused. + fn assert_fused(_: I) {} + assert_fused((0..10).step_by(3)); + + // Once the underlying fused iterator is exhausted, `StepBy` keeps yielding `None`. + let mut it = (0..3).step_by(5); + assert_eq!(it.next(), Some(0)); + assert_eq!(it.next(), None); + assert_eq!(it.next(), None); +} diff --git a/library/coretests/tests/iter/adapters/take.rs b/library/coretests/tests/iter/adapters/take.rs index b932059afec8a..700bd3f44a1d1 100644 --- a/library/coretests/tests/iter/adapters/take.rs +++ b/library/coretests/tests/iter/adapters/take.rs @@ -260,3 +260,66 @@ fn test_reverse_on_zip() { assert_eq!((1, 0), (one, zero)); } } + +#[test] +fn test_iterator_take_count() { + let xs = [0, 1, 2, 3, 5, 13, 15, 16, 17, 19]; + + // take shorter than, equal to, and longer than the underlying iterator + assert_eq!(xs.iter().take(0).count(), 0); + assert_eq!(xs.iter().take(5).count(), 5); + assert_eq!(xs.iter().take(10).count(), 10); + assert_eq!(xs.iter().take(11).count(), 10); + assert_eq!(xs.iter().take(usize::MAX).count(), 10); + + // partially consumed + let mut it = xs.iter().take(5); + it.next(); + it.next(); + assert_eq!(it.count(), 3); + + let mut it = xs.iter().take(20); + it.next(); + assert_eq!(it.count(), 9); + + // `count` must observe the same elements `next` would have yielded: + // a side-effecting inner iterator sees exactly min(n, len) closure calls. + let mut calls = 0; + let count = (0..10) + .map(|x| { + calls += 1; + x + }) + .take(3) + .count(); + assert_eq!(count, 3); + assert_eq!(calls, 3); + + // stateful filter: count agrees with the number of elements actually yielded + let mut budget = 7; + let yielded: Vec = (1..100) + .filter(|&x| { + if x <= budget { + budget -= 1; + true + } else { + false + } + }) + .take(10) + .collect(); + + let mut budget = 7; + let counted = (1..100) + .filter(|&x| { + if x <= budget { + budget -= 1; + true + } else { + false + } + }) + .take(10) + .count(); + assert_eq!(counted, yielded.len()); +} diff --git a/library/coretests/tests/iter/range.rs b/library/coretests/tests/iter/range.rs index d5d2b8bf2b047..c9904f08c4240 100644 --- a/library/coretests/tests/iter/range.rs +++ b/library/coretests/tests/iter/range.rs @@ -93,9 +93,26 @@ fn test_range_inclusive_exhaustion() { assert_eq!(r.next(), None); assert_eq!(r.next(), None); - assert_eq!(*r.start(), 10); + assert_eq!(*r.start(), 11); assert_eq!(*r.end(), 10); - assert_ne!(r, 10..=10); + assert_eq!(r.contains(&11), false); + assert_eq!(r.contains(&10), false); + assert_eq!(r, 11..=10); + assert_eq!(r, r); + + let mut r = 255..=255_u8; + assert_eq!(r.next(), Some(255)); + assert!(r.is_empty()); + assert_eq!(r.next(), None); + assert_eq!(r.next(), None); + + assert_eq!(*r.start(), 0); + assert_eq!(*r.end(), 255); + assert_eq!(r.contains(&0), false); + assert_eq!(r.contains(&255), false); + assert_ne!(r, 255..=255); + assert_ne!(r, 0..=255); + assert_eq!(r, r); let mut r = 10..=10; assert_eq!(r.next_back(), Some(10)); @@ -103,8 +120,23 @@ fn test_range_inclusive_exhaustion() { assert_eq!(r.next_back(), None); assert_eq!(*r.start(), 10); - assert_eq!(*r.end(), 10); - assert_ne!(r, 10..=10); + assert_eq!(*r.end(), 9); + assert_eq!(r.contains(&10), false); + assert_eq!(r.contains(&9), false); + assert_eq!(r, 10..=9); + + let mut r = 0..=0_u8; + assert_eq!(r.next_back(), Some(0)); + assert!(r.is_empty()); + assert_eq!(r.next_back(), None); + + assert_eq!(*r.start(), 0); + assert_eq!(*r.end(), 255); + assert_eq!(r.contains(&0), false); + assert_eq!(r.contains(&255), false); + assert_ne!(r, 0..=0); + assert_ne!(r, 0..=255); + assert_eq!(r, r); let mut r = 10..=12; assert_eq!(r.next(), Some(10)); @@ -221,9 +253,6 @@ fn test_range_inclusive_nth() { assert_eq!((10..=15).nth(5), Some(15)); assert_eq!((10..=15).nth(6), None); - let mut exhausted_via_next = 10_u8..=20; - while exhausted_via_next.next().is_some() {} - let mut r = 10_u8..=20; assert_eq!(r.nth(2), Some(12)); assert_eq!(r, 13..=20); @@ -233,7 +262,11 @@ fn test_range_inclusive_nth() { assert_eq!(ExactSizeIterator::is_empty(&r), false); assert_eq!(r.nth(10), None); assert_eq!(r.is_empty(), true); - assert_eq!(r, exhausted_via_next); + assert_eq!(*r.start(), 27); + assert_eq!(*r.end(), 20); + assert_eq!(r.contains(&27), false); + assert_eq!(r.contains(&20), false); + assert_eq!(r, r); assert_eq!(ExactSizeIterator::is_empty(&r), true); } @@ -245,9 +278,6 @@ fn test_range_inclusive_nth_back() { assert_eq!((10..=15).nth_back(6), None); assert_eq!((-120..=80_i8).nth_back(200), Some(-120)); - let mut exhausted_via_next_back = 10_u8..=20; - while exhausted_via_next_back.next_back().is_some() {} - let mut r = 10_u8..=20; assert_eq!(r.nth_back(2), Some(18)); assert_eq!(r, 10..=17); @@ -257,7 +287,11 @@ fn test_range_inclusive_nth_back() { assert_eq!(ExactSizeIterator::is_empty(&r), false); assert_eq!(r.nth_back(10), None); assert_eq!(r.is_empty(), true); - assert_eq!(r, exhausted_via_next_back); + assert_eq!(*r.start(), 10); + assert_eq!(*r.end(), 3); + assert_eq!(r.contains(&10), false); + assert_eq!(r.contains(&3), false); + assert_eq!(r, r); assert_eq!(ExactSizeIterator::is_empty(&r), true); } @@ -502,3 +536,142 @@ fn test_double_ended_range() { panic!("unreachable"); } } + +macro_rules! nz { + (NonZero<$type:ident>($val:literal)) => { + ::core::num::NonZero::<$type>::new($val).unwrap() + }; + (NonZero<$type:ident>::MAX) => { + ::core::num::NonZero::<$type>::new($type::MAX).unwrap() + }; +} + +macro_rules! nonzero_array { + (NonZero<$type:ident>[$($val:literal),*]) => { + [$(nz!(NonZero<$type>($val))),*] + } +} + +macro_rules! nonzero_range { + (NonZero<$type:ident>($($left:literal)?..$($right:literal)?)) => { + nz!(NonZero<$type>($($left)?))..nz!(NonZero<$type>($($right)?)) + }; + (NonZero<$type:ident>($($left:literal)?..MAX)) => { + nz!(NonZero<$type>($($left)?))..nz!(NonZero<$type>::MAX) + }; + (NonZero<$type:ident>($($left:literal)?..=$right:literal)) => { + nz!(NonZero<$type>($($left)?))..=nz!(NonZero<$type>($right)) + }; + (NonZero<$type:ident>($($left:literal)?..=MAX)) => { + nz!(NonZero<$type>($($left)?))..=nz!(NonZero<$type>::MAX) + }; +} + +#[test] +fn test_nonzero_range() { + assert_eq!( + nonzero_range!(NonZero(1..=21)).step_by(5).collect::>(), + nonzero_array!(NonZero[1, 6, 11, 16, 21]) + ); + assert_eq!( + nonzero_range!(NonZero(1..=20)).step_by(5).collect::>(), + nonzero_array!(NonZero[1, 6, 11, 16]) + ); + assert_eq!( + nonzero_range!(NonZero(1..20)).step_by(5).collect::>(), + nonzero_array!(NonZero[1, 6, 11, 16]) + ); + assert_eq!( + nonzero_range!(NonZero(1..21)).rev().step_by(5).collect::>(), + nonzero_array!(NonZero[20, 15, 10, 5]) + ); + assert_eq!( + nonzero_range!(NonZero(1..21)).rev().step_by(6).collect::>(), + nonzero_array!(NonZero[20, 14, 8, 2]) + ); + assert_eq!( + nonzero_range!(NonZero(200..255)).step_by(50).collect::>(), + nonzero_array!(NonZero[200, 250]) + ); + assert_eq!( + nonzero_range!(NonZero(200..5)).step_by(1).collect::>(), + nonzero_array!(NonZero[]) + ); + assert_eq!( + nonzero_range!(NonZero(200..200)).step_by(1).collect::>(), + nonzero_array!(NonZero[]) + ); + + assert_eq!(nonzero_range!(NonZero(10..20)).step_by(1).size_hint(), (10, Some(10))); + assert_eq!(nonzero_range!(NonZero(10..20)).step_by(5).size_hint(), (2, Some(2))); + assert_eq!(nonzero_range!(NonZero(1..21)).rev().step_by(5).size_hint(), (4, Some(4))); + assert_eq!(nonzero_range!(NonZero(1..21)).rev().step_by(6).size_hint(), (4, Some(4))); + assert_eq!(nonzero_range!(NonZero(20..1)).step_by(1).size_hint(), (0, Some(0))); + assert_eq!(nonzero_range!(NonZero(20..20)).step_by(1).size_hint(), (0, Some(0))); + + // ExactSizeIterator + assert_eq!(nonzero_range!(NonZero(1..=MAX)).step_by(1).len(), usize::from(u8::MAX)); + assert_eq!(nonzero_range!(NonZero(1..=MAX)).step_by(1).len(), usize::from(u16::MAX)); + assert_eq!(nonzero_range!(NonZero(1..=MAX)).step_by(1).len(), usize::MAX); + + // Limits (next) + let mut range = nonzero_range!(NonZero(254..=MAX)); + assert_eq!(range.next(), Some(nz!(NonZero(254)))); + assert_eq!(range.next(), Some(nz!(NonZero(255)))); + assert_eq!(range.next(), None); + + let mut range = nonzero_range!(NonZero(65534..=MAX)); + assert_eq!(range.next(), Some(nz!(NonZero(65534)))); + assert_eq!(range.next(), Some(nz!(NonZero(65535)))); + assert_eq!(range.next(), None); + + // Limits (size_hint, exclusive range) + assert_eq!( + nonzero_range!(NonZero(1..MAX)).step_by(1).size_hint(), + (u8::MAX as usize - 1, Some(u8::MAX as usize - 1)) + ); + assert_eq!( + nonzero_range!(NonZero(1..MAX)).step_by(1).size_hint(), + (u16::MAX as usize - 1, Some(u16::MAX as usize - 1)) + ); + #[cfg(any(target_pointer_width = "32", target_pointer_width = "64"))] + assert_eq!( + nonzero_range!(NonZero(1..MAX)).step_by(1).size_hint(), + (u32::MAX as usize - 1, Some(u32::MAX as usize - 1)) + ); + #[cfg(target_pointer_width = "64")] + assert_eq!( + nonzero_range!(NonZero(1..MAX)).step_by(1).size_hint(), + (u64::MAX as usize - 1, Some(u64::MAX as usize - 1)) + ); + assert_eq!(nonzero_range!(NonZero(1..MAX)).step_by(1).size_hint(), (usize::MAX, None)); + assert_eq!( + nonzero_range!(NonZero(1..MAX)).step_by(1).size_hint(), + (usize::MAX - 1, Some(usize::MAX - 1)) + ); + + // Limits (size_hint, inclusive range) + assert_eq!( + nonzero_range!(NonZero(1..=MAX)).step_by(1).size_hint(), + (u8::MAX as usize, Some(u8::MAX as usize)) + ); + assert_eq!( + nonzero_range!(NonZero(1..=MAX)).step_by(1).size_hint(), + (u16::MAX as usize, Some(u16::MAX as usize)) + ); + #[cfg(any(target_pointer_width = "32", target_pointer_width = "64"))] + assert_eq!( + nonzero_range!(NonZero(1..=MAX)).step_by(1).size_hint(), + (u32::MAX as usize, Some(u32::MAX as usize)) + ); + #[cfg(target_pointer_width = "64")] + assert_eq!( + nonzero_range!(NonZero(1..=MAX)).step_by(1).size_hint(), + (u64::MAX as usize, Some(u64::MAX as usize)) + ); + assert_eq!(nonzero_range!(NonZero(1..=MAX)).step_by(1).size_hint(), (usize::MAX, None)); + assert_eq!( + nonzero_range!(NonZero(1..=MAX)).step_by(1).size_hint(), + (usize::MAX, Some(usize::MAX)) + ); +} diff --git a/library/coretests/tests/iter/sources.rs b/library/coretests/tests/iter/sources.rs index 420f3088e6ee4..c1df278b54064 100644 --- a/library/coretests/tests/iter/sources.rs +++ b/library/coretests/tests/iter/sources.rs @@ -192,3 +192,19 @@ fn test_repeat_n_soundness() { let _z = y; assert_eq!(0, *x); } + +#[test] +fn test_repeat_n_default() { + #[derive(Clone)] + pub struct PanicOnDrop; + + impl Drop for PanicOnDrop { + fn drop(&mut self) { + unreachable!() + } + } + + // The default is an empty iterator, so there's never any item to drop. + let iter = RepeatN::::default(); + assert_eq!(iter.count(), 0); +} diff --git a/library/coretests/tests/iter/traits/iterator.rs b/library/coretests/tests/iter/traits/iterator.rs index 5ef1f797ae55d..e4c3459e0bff9 100644 --- a/library/coretests/tests/iter/traits/iterator.rs +++ b/library/coretests/tests/iter/traits/iterator.rs @@ -1,4 +1,5 @@ use core::cell::RefCell; +use core::cmp::Ordering; use core::iter::zip; use core::num::NonZero; @@ -17,13 +18,13 @@ impl PartialEq for Mod3 { impl Eq for Mod3 {} impl PartialOrd for Mod3 { - fn partial_cmp(&self, other: &Self) -> Option { + fn partial_cmp(&self, other: &Self) -> Option { Some(self.cmp(other)) } } impl Ord for Mod3 { - fn cmp(&self, other: &Self) -> core::cmp::Ordering { + fn cmp(&self, other: &Self) -> Ordering { (self.0 % 3).cmp(&(other.0 % 3)) } } @@ -75,8 +76,6 @@ fn test_lt() { #[test] fn test_cmp_by() { - use core::cmp::Ordering; - let f = |x: i32, y: i32| (x * x).cmp(&y); let xs = || [1, 2, 3, 4].iter().copied(); let ys = || [1, 4, 16].iter().copied(); @@ -91,8 +90,6 @@ fn test_cmp_by() { #[test] fn test_partial_cmp_by() { - use core::cmp::Ordering; - let f = |x: i32, y: i32| (x * x).partial_cmp(&y); let xs = || [1, 2, 3, 4].iter().copied(); let ys = || [1, 4, 16].iter().copied(); @@ -619,6 +616,57 @@ fn test_next_chunk() { assert_eq!(it.next_chunk::<0>().unwrap(), []); } +#[test] +fn test_next_chunk_back() { + let mut it = 0..12; + assert_eq!(it.next_chunk_back().unwrap(), [8, 9, 10, 11]); + assert_eq!(it.next_chunk_back().unwrap(), []); + assert_eq!(it.next_chunk_back().unwrap(), [2, 3, 4, 5, 6, 7]); + assert_eq!(it.next_chunk_back::<4>().unwrap_err().as_slice(), &[0, 1]); + + let mut it = std::iter::once_with(|| panic!()); + assert_eq!(it.next_chunk_back::<0>().unwrap(), []); +} + +#[test] +fn test_next_chunk_untrusted() { + struct Untrusted(I); + impl Iterator for Untrusted { + type Item = I::Item; + + fn next(&mut self) -> Option { + self.0.next() + } + } + let mut it = Untrusted(0..12); + assert_eq!(it.next_chunk().unwrap(), [0, 1, 2, 3]); + assert_eq!(it.next_chunk().unwrap(), []); + assert_eq!(it.next_chunk().unwrap(), [4, 5, 6, 7, 8, 9]); + assert_eq!(it.next_chunk::<4>().unwrap_err().as_slice(), &[10, 11]); +} + +#[test] +fn test_next_chunk_back_untrusted() { + struct Untrusted(I); + impl Iterator for Untrusted { + type Item = I::Item; + + fn next(&mut self) -> Option { + self.0.next() + } + } + impl DoubleEndedIterator for Untrusted { + fn next_back(&mut self) -> Option { + self.0.next_back() + } + } + let mut it = Untrusted(0..12); + assert_eq!(it.next_chunk_back().unwrap(), [8, 9, 10, 11]); + assert_eq!(it.next_chunk_back().unwrap(), []); + assert_eq!(it.next_chunk_back().unwrap(), [2, 3, 4, 5, 6, 7]); + assert_eq!(it.next_chunk::<4>().unwrap_err().as_slice(), &[0, 1]); +} + #[test] fn test_collect_into_tuples() { let a = vec![(1, 2, 3), (4, 5, 6), (7, 8, 9)]; @@ -671,3 +719,62 @@ fn _empty_impl_all_auto_traits() { all_auto_traits::>(); } + +#[test] +fn test_iterator_min_max_use_ord_min_max() { + // There's no stable guarantee that the iterator methods use these, but they were added + // on `Ord` (as opposed to just the functions in `cmp`) so that they could be overridden + // when a more efficient implementation is available, so we should probably use them. + + let a = [OnlyMinMax(3), OnlyMinMax(1), OnlyMinMax(5), OnlyMinMax(9), OnlyMinMax(7)]; + assert_eq!(a.iter().copied().min(), Some(OnlyMinMax(1))); + assert_eq!(a.iter().copied().max(), Some(OnlyMinMax(9))); + + #[derive(Debug, Copy, Clone, Eq, PartialEq)] + struct OnlyMinMax(i32); + impl PartialOrd for OnlyMinMax { + fn partial_cmp(&self, _other: &Self) -> Option { + unimplemented!() + } + } + impl Ord for OnlyMinMax { + fn cmp(&self, _other: &Self) -> Ordering { + unimplemented!() + } + fn min(self, other: Self) -> Self { + Self(Ord::min(self.0, other.0)) + } + fn max(self, other: Self) -> Self { + Self(Ord::max(self.0, other.0)) + } + } +} + +#[test] +fn test_iterator_min_max_by_key_use_lt() { + // The exact method is certainly not a stable guarantee. The important part + // is that they use a simple `-> bool` method as opposed to three-way `cmp`. + // If they used `gt` instead, or something, that wouldn't be the end of the world, + // but `lt` tends to be best optimized because that's the one that C++ has + // traditionally used in standard library templates. + + let a = [3, 1, 5, 9, 7]; + assert_eq!(a.iter().copied().min_by_key(|x| OnlyLt(*x)), Some(1)); + assert_eq!(a.iter().copied().max_by_key(|x| OnlyLt(*x)), Some(9)); + + #[derive(Debug, Copy, Clone, Eq, PartialEq)] + struct OnlyLt(i32); + impl PartialOrd for OnlyLt { + fn partial_cmp(&self, _other: &Self) -> Option { + unimplemented!() + } + fn lt(&self, other: &Self) -> bool { + self.0 < other.0 + } + } + impl Ord for OnlyLt { + fn cmp(&self, _other: &Self) -> Ordering { + unimplemented!() + } + } +} diff --git a/library/coretests/tests/lib.rs b/library/coretests/tests/lib.rs index d085e4ad1a8fe..1f629f01f38dd 100644 --- a/library/coretests/tests/lib.rs +++ b/library/coretests/tests/lib.rs @@ -1,6 +1,6 @@ // tidy-alphabetical-start +#![cfg_attr(not(panic = "abort"), feature(reentrant_lock))] #![cfg_attr(target_has_atomic = "128", feature(integer_atomics))] -#![cfg_attr(test, feature(cfg_select))] #![feature(array_ptr_get)] #![feature(array_try_from_fn)] #![feature(array_try_map)] @@ -8,17 +8,19 @@ #![feature(ascii_char_variants)] #![feature(async_iter_from_iter)] #![feature(async_iterator)] -#![feature(bool_to_result)] +#![feature(borrowed_buf_init)] #![feature(bstr)] +#![feature(casefold)] #![feature(cfg_target_has_reliable_f16_f128)] #![feature(char_internals)] -#![feature(char_max_len)] -#![feature(clamp_magnitude)] #![feature(clone_to_uninit)] +#![feature(cmp_minmax)] +#![feature(cmp_splat)] #![feature(const_array)] #![feature(const_bool)] #![feature(const_cell_traits)] #![feature(const_clone)] +#![feature(const_closures)] #![feature(const_cmp)] #![feature(const_convert)] #![feature(const_default)] @@ -34,10 +36,9 @@ #![feature(const_select_unpredictable)] #![feature(const_trait_impl)] #![feature(const_unsigned_bigint_helpers)] -#![feature(control_flow_ok)] -#![feature(core_float_math)] #![feature(core_intrinsics)] #![feature(core_intrinsics_fallbacks)] +#![feature(core_io)] #![feature(core_io_borrowed_buf)] #![feature(core_private_bignum)] #![feature(core_private_diy_float)] @@ -47,14 +48,13 @@ #![feature(drop_guard)] #![feature(duration_constants)] #![feature(duration_constructors)] -#![feature(error_generic_member_access)] #![feature(exact_div)] #![feature(exact_size_is_empty)] #![feature(extend_one)] #![feature(extern_types)] #![feature(f16)] #![feature(f128)] -#![feature(float_algebraic)] +#![feature(float_exact_integer_constants)] #![feature(float_gamma)] #![feature(float_minimum_maximum)] #![feature(flt2dec)] @@ -66,11 +66,12 @@ #![feature(generic_assert_internals)] #![feature(hasher_prefixfree_extras)] #![feature(hashmap_internals)] -#![feature(int_lowest_highest_one)] +#![feature(int_from_ascii)] #![feature(int_roundings)] +#![feature(integer_casts)] +#![feature(io_slice_as_bytes)] #![feature(ip)] #![feature(is_ascii_octdigit)] -#![feature(isolate_most_least_significant_one)] #![feature(iter_advance_by)] #![feature(iter_array_chunks)] #![feature(iter_collect_into)] @@ -82,22 +83,23 @@ #![feature(iter_partition_in_place)] #![feature(iterator_try_collect)] #![feature(iterator_try_reduce)] -#![feature(layout_for_ptr)] +#![feature(macro_metavar_expr_concat)] #![feature(maybe_uninit_fill)] #![feature(maybe_uninit_uninit_array_transpose)] #![feature(min_specialization)] #![feature(never_type)] -#![feature(new_range_api)] #![feature(next_index)] #![feature(non_exhaustive_omitted_patterns_lint)] +#![feature(num_internals)] #![feature(numfmt)] #![feature(one_sided_range)] -#![feature(option_reduce)] +#![feature(panic_internals)] #![feature(pattern)] #![feature(pointer_is_aligned_to)] #![feature(portable_simd)] #![feature(ptr_metadata)] -#![feature(result_option_map_or_default)] +#![feature(raw_os_error_ty)] +#![feature(rustc_attrs)] #![feature(signed_bigint_helpers)] #![feature(slice_from_ptr_range)] #![feature(slice_index_methods)] @@ -112,21 +114,22 @@ #![feature(step_trait)] #![feature(str_internals)] #![feature(strict_provenance_lints)] -#![feature(test)] +#![feature(titlecase)] #![feature(trusted_len)] #![feature(trusted_random_access)] #![feature(try_blocks)] #![feature(try_find)] +#![feature(try_from_int_error_kind)] #![feature(try_trait_v2)] #![feature(type_info)] -#![feature(uint_bit_width)] +#![feature(uint_carryless_mul)] #![feature(uint_gather_scatter_bits)] +#![feature(unicode_internals)] #![feature(unsize)] #![feature(unwrap_infallible)] -#![feature(widening_mul)] // tidy-alphabetical-end #![allow(internal_features)] -#![deny(fuzzy_provenance_casts)] +#![deny(implicit_provenance_casts)] #![deny(unsafe_op_in_unsafe_fn)] /// Version of `assert_matches` that ignores fancy runtime printing in const context and uses structural equality. @@ -181,7 +184,6 @@ mod cmp; mod const_ptr; mod convert; mod ffi; -mod floats; mod fmt; mod future; mod hash; diff --git a/library/coretests/tests/macros.rs b/library/coretests/tests/macros.rs index 50b5eb63e43a7..a868cfcef4ce1 100644 --- a/library/coretests/tests/macros.rs +++ b/library/coretests/tests/macros.rs @@ -1,5 +1,7 @@ #![allow(unused_must_use)] +use std::{assert_matches, debug_assert_matches}; + #[allow(dead_code)] trait Trait { fn blah(&self); @@ -47,23 +49,51 @@ fn matches_leading_pipe() { #[test] fn cfg_select_basic() { cfg_select! { - target_pointer_width = "64" => { fn f0_() -> bool { true }} + target_pointer_width = "64" => { + fn f0_() -> bool { + true + } + } _ => {} } cfg_select! { - unix => { fn f1_() -> bool { true } } - _ => { fn f1_() -> bool { false }} + unix => { + fn f1_() -> bool { + true + } + } + _ => { + fn f1_() -> bool { + false + } + } } cfg_select! { - target_pointer_width = "32" => { fn f2_() -> bool { false } } - target_pointer_width = "64" => { fn f2_() -> bool { true } } + target_pointer_width = "32" => { + fn f2_() -> bool { + false + } + } + target_pointer_width = "64" => { + fn f2_() -> bool { + true + } + } } cfg_select! { - target_pointer_width = "16" => { fn f3_() -> i32 { 1 } } - _ => { fn f3_() -> i32 { 2 }} + target_pointer_width = "16" => { + fn f3_() -> i32 { + 1 + } + } + _ => { + fn f3_() -> i32 { + 2 + } + } } #[cfg(target_pointer_width = "64")] @@ -88,11 +118,11 @@ fn cfg_select_debug_assertions() { cfg_select! { debug_assertions => { assert!(cfg!(debug_assertions)); - assert_eq!(4, 2+2); + assert_eq!(4, 2 + 2); } _ => { assert!(cfg!(not(debug_assertions))); - assert_eq!(10, 5+5); + assert_eq!(10, 5 + 5); } } } @@ -119,32 +149,68 @@ fn cfg_select_options() { cfg_select! { test => { use core::option::Option as Option2; - fn works1() -> Option2 { Some(1) } + fn works1() -> Option2 { + Some(1) + } + } + _ => { + fn works1() -> Option { + None + } } - _ => { fn works1() -> Option { None } } } cfg_select! { - feature = "foo" => { fn works2() -> bool { false } } - test => { fn works2() -> bool { true } } - _ => { fn works2() -> bool { false } } + feature = "foo" => { + fn works2() -> bool { + false + } + } + test => { + fn works2() -> bool { + true + } + } + _ => { + fn works2() -> bool { + false + } + } } cfg_select! { - feature = "foo" => { fn works3() -> bool { false } } - _ => { fn works3() -> bool { true } } + feature = "foo" => { + fn works3() -> bool { + false + } + } + _ => { + fn works3() -> bool { + true + } + } } cfg_select! { test => { use core::option::Option as Option3; - fn works4() -> Option3 { Some(1) } + fn works4() -> Option3 { + Some(1) + } } } cfg_select! { - feature = "foo" => { fn works5() -> bool { false } } - test => { fn works5() -> bool { true } } + feature = "foo" => { + fn works5() -> bool { + false + } + } + test => { + fn works5() -> bool { + true + } + } } assert!(works1().is_some()); @@ -181,14 +247,14 @@ fn cfg_select_two_functions() { fn _accepts_expressions() -> i32 { cfg_select! { - unix => { 1 } - _ => { 2 } + unix => 1, + _ => 2, } } fn _accepts_only_wildcard() -> i32 { cfg_select! { - _ => { 1 } + _ => 1, } } @@ -198,19 +264,19 @@ fn _allows_stmt_expr_attributes() { let one = 1; let two = 2; cfg_select! { - unix => { one * two; } - _ => { one + two; } + unix => { + one * two; + } + _ => { + one + two; + } } } fn _expression() { let _ = cfg_select!( - windows => { - " XP" - } - _ => { - "" - } + windows => " XP", + _ => "", ); } @@ -219,3 +285,39 @@ fn _matches_does_not_trigger_non_exhaustive_omitted_patterns_lint(o: core::sync: // Ordering is a #[non_exhaustive] enum from a separate crate let _m = matches!(o, core::sync::atomic::Ordering::Relaxed); } + +struct MutRefWithDrop<'a>(&'a mut u32); + +// MutRefWithDrop needs to have a non-trivial drop to encounter potential lifetime issues if the +// macros don't introduce a temporary scope. +impl Drop for MutRefWithDrop<'_> { + fn drop(&mut self) { + *self.0 = u32::MAX; + } +} + +#[test] +fn temporary_scope_introduction() { + // Fails to compile if the macros don't introduce a temporary scope, since `&mut val` would + // create a second mutable borrow while `MutRefWithDrop` still holds a unique ref. + // See https://github.com/rust-lang/rust/issues/154406 for reference. + let mut val = 0; + + (assert_matches!(*MutRefWithDrop(&mut val).0, 0), std::mem::take(&mut val)); + (assert_matches!(*MutRefWithDrop(&mut val).0, 0, "msg"), std::mem::take(&mut val)); + (debug_assert_matches!(*MutRefWithDrop(&mut val).0, 0), std::mem::take(&mut val)); + (debug_assert_matches!(*MutRefWithDrop(&mut val).0, 0, "msg"), std::mem::take(&mut val)); + + (assert_eq!(*MutRefWithDrop(&mut val).0, 0), std::mem::take(&mut val)); + (assert_eq!(*MutRefWithDrop(&mut val).0, 0, "msg"), std::mem::take(&mut val)); + (debug_assert_eq!(*MutRefWithDrop(&mut val).0, 0), std::mem::take(&mut val)); + (debug_assert_eq!(*MutRefWithDrop(&mut val).0, 0, "msg"), std::mem::take(&mut val)); + + (assert_ne!(*MutRefWithDrop(&mut val).0, 1), std::mem::take(&mut val)); + (assert_ne!(*MutRefWithDrop(&mut val).0, 1, "msg"), std::mem::take(&mut val)); + (debug_assert_ne!(*MutRefWithDrop(&mut val).0, 1), std::mem::take(&mut val)); + (debug_assert_ne!(*MutRefWithDrop(&mut val).0, 1, "msg"), std::mem::take(&mut val)); + + (assert!(*MutRefWithDrop(&mut val).0 == 0), std::mem::take(&mut val)); + (assert!(*MutRefWithDrop(&mut val).0 == 0, "msg"), std::mem::take(&mut val)); +} diff --git a/library/coretests/tests/manually_drop.rs b/library/coretests/tests/manually_drop.rs index 1638c82b161b4..db0cb9c31e174 100644 --- a/library/coretests/tests/manually_drop.rs +++ b/library/coretests/tests/manually_drop.rs @@ -40,7 +40,7 @@ fn const_drop_in_place() { struct Test<'a>(Dropped<'a>); struct Dropped<'a>(&'a Cell); - impl const Drop for Dropped<'_> { + const impl Drop for Dropped<'_> { fn drop(&mut self) { self.0.set(self.0.get() + 1); } diff --git a/library/coretests/tests/mem.rs b/library/coretests/tests/mem.rs index 193d5416b06a7..793c9f489e47f 100644 --- a/library/coretests/tests/mem.rs +++ b/library/coretests/tests/mem.rs @@ -1,3 +1,5 @@ +mod fn_ptr; +mod trait_info_of; mod type_info; use core::mem::*; @@ -136,32 +138,6 @@ fn test_transmute_copy_unaligned() { assert_eq!(0_u64, unsafe { transmute_copy(&u.b) }); } -#[test] -#[cfg(panic = "unwind")] -fn test_transmute_copy_grow_panics() { - use std::panic; - - let err = panic::catch_unwind(panic::AssertUnwindSafe(|| unsafe { - let _unused: u64 = transmute_copy(&1_u8); - })); - - match err { - Ok(_) => unreachable!(), - Err(payload) => { - payload - .downcast::<&'static str>() - .and_then(|s| { - if *s == "cannot transmute_copy if Dst is larger than Src" { - Ok(s) - } else { - Err(s) - } - }) - .unwrap_or_else(|p| panic::resume_unwind(p)); - } - } -} - #[test] #[allow(dead_code)] fn test_discriminant_send_sync() { diff --git a/library/coretests/tests/mem/fn_ptr.rs b/library/coretests/tests/mem/fn_ptr.rs new file mode 100644 index 0000000000000..192054bcaf66b --- /dev/null +++ b/library/coretests/tests/mem/fn_ptr.rs @@ -0,0 +1,235 @@ +use std::any::TypeId; +use std::mem::type_info::{Abi, FnPtr, Type, TypeKind}; + +const STRING_TY: TypeId = const { TypeId::of::() }; +const U8_TY: TypeId = const { TypeId::of::() }; +const _U8_REF_TY: TypeId = const { TypeId::of::<&u8>() }; +const UNIT_TY: TypeId = const { TypeId::of::<()>() }; +const TUPLE_STRING_U8_TY: TypeId = const { TypeId::of::<(String, u8)>() }; + +#[test] +fn test_fn_ptrs() { + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternRust, + inputs: &[], + output, + variadic: false, + is_splatted: false, + splatted_index: _, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, UNIT_TY); +} +#[test] +fn test_ref() { + const { + // references are tricky because the lifetimes give the references different type ids + // so we check the pointees instead + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternRust, + inputs: &[ty1, ty2], + output, + variadic: false, + is_splatted: false, + splatted_index: _, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + if output != UNIT_TY { + panic!(); + } + let TypeKind::Reference(reference) = ty1.info().kind else { + panic!(); + }; + if reference.pointee != U8_TY { + panic!(); + } + let TypeKind::Reference(reference) = ty2.info().kind else { + panic!(); + }; + if reference.pointee != U8_TY { + panic!(); + } + } +} + +#[test] +fn test_unsafe() { + let TypeKind::FnPtr(FnPtr { + unsafety: true, + abi: Abi::ExternRust, + inputs: &[], + output, + variadic: false, + is_splatted: false, + splatted_index: _, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, UNIT_TY); +} +#[test] +fn test_abi() { + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternRust, + inputs: &[], + output, + variadic: false, + is_splatted: false, + splatted_index: _, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, UNIT_TY); + + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternC, + inputs: &[], + output, + variadic: false, + is_splatted: false, + splatted_index: _, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, UNIT_TY); + + let TypeKind::FnPtr(FnPtr { + unsafety: true, + abi: Abi::Named("system"), + inputs: &[], + output, + variadic: false, + is_splatted: false, + splatted_index: _, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, UNIT_TY); +} + +#[test] +fn test_inputs() { + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternRust, + inputs: &[ty1, ty2], + output, + variadic: false, + is_splatted: false, + splatted_index: _, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, UNIT_TY); + assert_eq!(ty1, STRING_TY); + assert_eq!(ty2, U8_TY); + + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternRust, + inputs: &[ty1, ty2], + output, + variadic: false, + is_splatted: false, + splatted_index: _, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, UNIT_TY); + assert_eq!(ty1, STRING_TY); + assert_eq!(ty2, U8_TY); +} + +#[test] +fn test_output() { + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternRust, + inputs: &[], + output, + variadic: false, + is_splatted: false, + splatted_index: _, + }) = (const { Type::of:: u8>().kind }) + else { + panic!(); + }; + assert_eq!(output, U8_TY); +} + +#[test] +fn test_variadic() { + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternC, + inputs: [ty1], + output, + variadic: true, + is_splatted: false, + splatted_index: _, + }) = &(const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, &UNIT_TY); + assert_eq!(*ty1, U8_TY); +} + +#[test] +fn test_splat() { + #[rustfmt::skip] + let TypeKind::FnPtr(fn_ptr_ty) = &(const { Type::of::().kind }) else { + panic!(); + }; + let FnPtr { + unsafety: false, + abi: Abi::ExternRust, + inputs: [ty1], + output, + variadic: false, + is_splatted: true, + splatted_index: 0, + } = fn_ptr_ty + else { + panic!(); + }; + assert_eq!(output, &UNIT_TY); + assert_eq!(*ty1, TUPLE_STRING_U8_TY); + assert_eq!(fn_ptr_ty.splatted(), Some(0)); +} + +#[test] +fn test_not_splat() { + let TypeKind::FnPtr(fn_ptr_ty) = &(const { Type::of::().kind }) else { + panic!(); + }; + let FnPtr { + unsafety: false, + abi: Abi::ExternRust, + inputs: [ty1], + output, + variadic: false, + is_splatted: false, + splatted_index: _, + } = fn_ptr_ty + else { + panic!(); + }; + assert_eq!(output, &UNIT_TY); + assert_eq!(*ty1, TUPLE_STRING_U8_TY); + assert_eq!(fn_ptr_ty.splatted(), None); +} diff --git a/library/coretests/tests/mem/trait_info_of.rs b/library/coretests/tests/mem/trait_info_of.rs new file mode 100644 index 0000000000000..4fd4a013693d9 --- /dev/null +++ b/library/coretests/tests/mem/trait_info_of.rs @@ -0,0 +1,71 @@ +use std::any::TypeId; +use std::ptr::DynMetadata; + +struct Garlic(i32); +trait Blah { + fn get_truth(&self) -> i32; +} +impl Blah for Garlic { + fn get_truth(&self) -> i32 { + self.0 * 21 + } +} +unsafe impl Send for Garlic {} + +#[test] +fn test_implements_trait() { + const { + assert!(TypeId::of::().trait_info_of::().is_some()); + assert!(TypeId::of::().trait_info_of::().is_some()); + assert!(TypeId::of::<*const Box>().trait_info_of::().is_none()); + assert!(TypeId::of::().trait_info_of_trait_type_id(TypeId::of::()).is_none()); + } +} + +#[test] +fn test_dyn_creation() { + let garlic = Garlic(2); + unsafe { + assert_eq!( + std::ptr::from_raw_parts::( + &raw const garlic, + const { TypeId::of::().trait_info_of::() }.unwrap().get_vtable() + ) + .as_ref() + .unwrap() + .get_truth(), + 42 + ); + } + + assert_eq!( + const { + TypeId::of::() + .trait_info_of_trait_type_id(TypeId::of::()) + .unwrap() + }.get_vtable(), + unsafe { + crate::mem::transmute::<_, DynMetadata<*const ()>>( + const { + TypeId::of::().trait_info_of::() + }.unwrap().get_vtable(), + ) + } + ); +} + +#[test] +fn test_incorrect_use() { + assert_eq!( + const { TypeId::of::().trait_info_of_trait_type_id(TypeId::of::()) }, + None + ); +} + +trait DstTrait {} +impl DstTrait for [i32] {} + +#[test] +fn dst_ice() { + assert!(const { TypeId::of::<[i32]>().trait_info_of::() }.is_none()); +} diff --git a/library/coretests/tests/mem/type_info.rs b/library/coretests/tests/mem/type_info.rs index 87f2d5dd8289c..74be53c57b46b 100644 --- a/library/coretests/tests/mem/type_info.rs +++ b/library/coretests/tests/mem/type_info.rs @@ -1,5 +1,8 @@ +#![allow(dead_code)] + use std::any::{Any, TypeId}; -use std::mem::type_info::{Type, TypeKind}; +use std::mem::offset_of; +use std::mem::type_info::{Const, Generic, GenericType, Type, TypeKind}; #[test] fn test_arrays() { @@ -32,76 +35,243 @@ fn test_slices() { #[test] fn test_tuples() { - fn assert_tuple_arity() { - match const { Type::of::() }.kind { - TypeKind::Tuple(tup) => { - assert_eq!(tup.fields.len(), N); - } - _ => unreachable!(), + const { + let ty_id = TypeId::of::<()>(); + assert!(ty_id.size() == Some(size_of::<()>())); + assert!(ty_id.variants() == 1); + assert!(ty_id.fields(0) == 0); + + let ty_id = TypeId::of::<(u8,)>(); + assert!(ty_id.size() == Some(size_of::<(u8,)>())); + assert!(ty_id.variants() == 1); + assert!(ty_id.fields(0) == 1); + assert!(ty_id.field(0, 0).type_id() == TypeId::of::()); + + let ty_id = TypeId::of::<(u8, u16)>(); + assert!(ty_id.size() == Some(size_of::<(u8, u16)>())); + assert!(ty_id.variants() == 1); + assert!(ty_id.fields(0) == 2); + assert!(ty_id.field(0, 0).type_id() == TypeId::of::()); + assert!(ty_id.field(0, 1).type_id() == TypeId::of::()); + } +} + +#[test] +fn test_structs() { + const { + struct TestStruct { + first: u8, + second: u16, + reference: &'static u16, + } + + let ty_id = TypeId::of::(); + assert!(!ty_id.non_exhaustive()); + assert!(ty_id.size() == Some(size_of::())); + assert!(ty_id.variants() == 1); + assert!(ty_id.fields(0) == 3); + assert!(ty_id.field(0, 0).type_id() == TypeId::of::()); + assert!(ty_id.field(0, 0).offset() == offset_of!(TestStruct, first)); + assert!(ty_id.field(0, 0).name() == "first"); + assert!(ty_id.field(0, 1).type_id() == TypeId::of::()); + assert!(ty_id.field(0, 1).offset() == offset_of!(TestStruct, second)); + assert!(ty_id.field(0, 1).name() == "second"); + assert!(ty_id.field(0, 2).type_id() == TypeId::of::<&u16>()); + assert!(ty_id.field(0, 2).offset() == offset_of!(TestStruct, reference)); + assert!(ty_id.field(0, 2).name() == "reference"); + } + + const { + #[non_exhaustive] + struct NonExhaustive { + a: u8, } + + assert!(TypeId::of::().non_exhaustive()); } - assert_tuple_arity::<(), 0>(); - assert_tuple_arity::<(u8,), 1>(); - assert_tuple_arity::<(u8, u8), 2>(); + const { + struct TupleStruct(u8, u16); + + let ty_id = TypeId::of::(); + assert!(ty_id.size() == Some(size_of::())); + assert!(ty_id.variants() == 1); + assert!(ty_id.fields(0) == 2); + assert!(ty_id.field(0, 0).type_id() == TypeId::of::()); + assert!(ty_id.field(0, 0).name() == "0"); + assert!(ty_id.field(0, 1).type_id() == TypeId::of::()); + assert!(ty_id.field(0, 1).name() == "1"); + } const { - match Type::of::<(i8, u8)>().kind { - TypeKind::Tuple(tup) => { - let [a, b] = tup.fields else { unreachable!() }; - - assert!(a.offset == 0); - assert!(b.offset == 1); - - match (a.ty.info().kind, b.ty.info().kind) { - (TypeKind::Int(a), TypeKind::Int(b)) => { - assert!(a.bits == 8 && a.signed); - assert!(b.bits == 8 && !b.signed); - } - _ => unreachable!(), - } - } - _ => unreachable!(), + struct Generics<'a, T, const C: u64> { + a: &'a T, } + + let ty_id = TypeId::of::>(); + assert!(ty_id.fields(0) == 1); + assert!(ty_id.generics().len() == 3); + + let Generic::Lifetime(_) = ty_id.generics()[0] else { panic!() }; + let Generic::Type(GenericType { ty: generic_ty, .. }) = ty_id.generics()[1] else { + panic!() + }; + assert!(generic_ty == TypeId::of::()); + let Generic::Const(Const { ty: const_ty, .. }) = ty_id.generics()[2] else { panic!() }; + assert!(const_ty == TypeId::of::()); } } #[test] -fn test_primitives() { - use TypeKind::*; +fn test_unions() { + const { + union TestUnion { + first: i16, + second: u16, + } + + let ty_id = TypeId::of::(); + assert!(ty_id.size() == Some(size_of::())); + assert!(ty_id.variants() == 1); + assert!(ty_id.fields(0) == 2); + assert!(ty_id.field(0, 0).name() == "first"); + assert!(ty_id.field(0, 0).type_id() == TypeId::of::()); + assert!(ty_id.field(0, 1).name() == "second"); + assert!(ty_id.field(0, 1).type_id() == TypeId::of::()); + } + + const { + union Generics<'a, T: Copy, const C: u64> { + a: T, + z: &'a (), + } + + let ty_id = TypeId::of::>(); + assert!(ty_id.fields(0) == 2); + assert!(ty_id.field(0, 1).offset() == offset_of!(Generics<'static, i32, 1_u64>, a)); + assert!(ty_id.field(0, 1).offset() == offset_of!(Generics<'static, i32, 1_u64>, z)); + + assert!(ty_id.generics().len() == 3); + let Generic::Lifetime(_) = ty_id.generics()[0] else { panic!() }; + let Generic::Type(GenericType { ty: generic_ty, .. }) = ty_id.generics()[1] else { + panic!() + }; + assert!(generic_ty == TypeId::of::()); + let Generic::Const(Const { ty: const_ty, .. }) = ty_id.generics()[2] else { panic!() }; + assert!(const_ty == TypeId::of::()); + } +} + +#[test] +fn test_enums() { + const { + enum E { + Some(u32), + None, + #[non_exhaustive] + Foomp { + a: (), + b: &'static str, + }, + } - let Type { kind: Bool(_ty), size, .. } = (const { Type::of::() }) else { panic!() }; - assert_eq!(size, Some(1)); + let ty_id = TypeId::of::(); + assert!(!ty_id.non_exhaustive()); + assert!(ty_id.size() == Some(size_of::())); + assert!(ty_id.variants() == 3); - let Type { kind: Char(_ty), size, .. } = (const { Type::of::() }) else { panic!() }; - assert_eq!(size, Some(4)); + assert!(ty_id.variant(0).name() == "Some"); + assert!(!ty_id.variant(0).non_exhaustive()); + assert!(ty_id.fields(0) == 1); + assert!(ty_id.field(0, 0).type_id() == TypeId::of::()); - let Type { kind: Int(ty), size, .. } = (const { Type::of::() }) else { panic!() }; - assert_eq!(size, Some(4)); - assert_eq!(ty.bits, 32); - assert!(ty.signed); + assert!(ty_id.variant(1).name() == "None"); + assert!(!ty_id.variant(1).non_exhaustive()); + assert!(ty_id.fields(1) == 0); - let Type { kind: Int(ty), size, .. } = (const { Type::of::() }) else { panic!() }; - assert_eq!(size, Some(size_of::())); - assert_eq!(ty.bits as usize, size_of::() * 8); - assert!(ty.signed); + assert!(ty_id.variant(2).name() == "Foomp"); + assert!(ty_id.variant(2).non_exhaustive()); + assert!(ty_id.fields(2) == 2); + assert!(ty_id.field(2, 0).type_id() == TypeId::of::<()>()); + assert!(ty_id.field(2, 1).type_id() == TypeId::of::<&str>()); + assert!(ty_id.field(2, 1).name() == "b"); - let Type { kind: Int(ty), size, .. } = (const { Type::of::() }) else { panic!() }; - assert_eq!(size, Some(4)); - assert_eq!(ty.bits, 32); - assert!(!ty.signed); + assert!(ty_id.generics().is_empty()); + } - let Type { kind: Int(ty), size, .. } = (const { Type::of::() }) else { panic!() }; - assert_eq!(size, Some(size_of::())); - assert_eq!(ty.bits as usize, size_of::() * 8); - assert!(!ty.signed); + const { + let ty_id = TypeId::of::>(); + assert!(ty_id.variants() == 2); + assert!(ty_id.generics().len() == 1); + + let Generic::Type(GenericType { ty: generic_ty, .. }) = ty_id.generics()[0] else { + panic!() + }; + assert!(generic_ty == TypeId::of::()); + + let ty_id = TypeId::of::>(); + assert!(ty_id.size() == Some(size_of::>())); + assert!(ty_id.variants() == 2); + assert!(ty_id.fields(0) == 0); + assert!(ty_id.fields(1) == 1); + assert!(ty_id.field(1, 0).type_id() == TypeId::of::()); + } +} - let Type { kind: Float(ty), size, .. } = (const { Type::of::() }) else { panic!() }; - assert_eq!(size, Some(4)); - assert_eq!(ty.bits, 32); +#[test] +fn test_primitives() { + use TypeKind::*; - let Type { kind: Str(_ty), size, .. } = (const { Type::of::() }) else { panic!() }; - assert_eq!(size, None); + const { + let Type { kind: Bool(_ty), .. } = (const { Type::of::() }) else { panic!() }; + let ty_id = TypeId::of::(); + assert!(ty_id.size() == Some(size_of::())); + assert!(ty_id.variants() == 1); + + let Type { kind: Char(_ty), .. } = (const { Type::of::() }) else { panic!() }; + let ty_id = TypeId::of::(); + assert!(ty_id.size() == Some(size_of::())); + assert!(ty_id.variants() == 1); + + let Type { kind: Int(ty), .. } = (const { Type::of::() }) else { panic!() }; + assert!(ty.bits == 32); + assert!(ty.signed); + let ty_id = TypeId::of::(); + assert!(ty_id.size() == Some(size_of::())); + assert!(ty_id.variants() == 1); + + let Type { kind: Int(ty), .. } = (const { Type::of::() }) else { panic!() }; + assert!(ty.bits as usize == size_of::() * 8); + assert!(ty.signed); + let ty_id = TypeId::of::(); + assert!(ty_id.size() == Some(size_of::())); + assert!(ty_id.variants() == 1); + + let Type { kind: Int(ty), .. } = (const { Type::of::() }) else { panic!() }; + assert!(ty.bits == 32); + assert!(!ty.signed); + let ty_id = TypeId::of::(); + assert!(ty_id.size() == Some(size_of::())); + assert!(ty_id.variants() == 1); + + let Type { kind: Int(ty), .. } = (const { Type::of::() }) else { panic!() }; + assert!(ty.bits as usize == size_of::() * 8); + assert!(!ty.signed); + let ty_id = TypeId::of::(); + assert!(ty_id.size() == Some(size_of::())); + assert!(ty_id.variants() == 1); + + let Type { kind: Float(ty), .. } = (const { Type::of::() }) else { panic!() }; + assert!(ty.bits == 32); + let ty_id = TypeId::of::(); + assert!(ty_id.size() == Some(size_of::())); + assert!(ty_id.variants() == 1); + + let Type { kind: Str(_ty), .. } = (const { Type::of::() }) else { panic!() }; + let ty_id = TypeId::of::(); + assert!(ty_id.size() == None); + assert!(ty_id.variants() == 1); + } } #[test] diff --git a/library/coretests/tests/net/ip_addr.rs b/library/coretests/tests/net/ip_addr.rs index 3fec59d67b748..ea78d7c58e9e4 100644 --- a/library/coretests/tests/net/ip_addr.rs +++ b/library/coretests/tests/net/ip_addr.rs @@ -218,18 +218,15 @@ fn ipv6_to_ipv4() { #[test] fn ip_properties() { - macro_rules! ip { - ($s:expr) => { - IpAddr::from_str($s).unwrap() - }; - } - macro_rules! check { ($s:expr) => { check!($s, 0); }; ($s:expr, $mask:expr) => {{ + let ip = IpAddr::from_str($s).unwrap(); + assert_eq!($s, ip.to_string()); + let unspec: u8 = 1 << 0; let loopback: u8 = 1 << 1; let global: u8 = 1 << 2; @@ -238,39 +235,39 @@ fn ip_properties() { let benchmarking: u8 = 1 << 5; if ($mask & unspec) == unspec { - assert!(ip!($s).is_unspecified()); + assert!(ip.is_unspecified()); } else { - assert!(!ip!($s).is_unspecified()); + assert!(!ip.is_unspecified()); } if ($mask & loopback) == loopback { - assert!(ip!($s).is_loopback()); + assert!(ip.is_loopback()); } else { - assert!(!ip!($s).is_loopback()); + assert!(!ip.is_loopback()); } if ($mask & global) == global { - assert!(ip!($s).is_global()); + assert!(ip.is_global()); } else { - assert!(!ip!($s).is_global()); + assert!(!ip.is_global()); } if ($mask & multicast) == multicast { - assert!(ip!($s).is_multicast()); + assert!(ip.is_multicast()); } else { - assert!(!ip!($s).is_multicast()); + assert!(!ip.is_multicast()); } if ($mask & doc) == doc { - assert!(ip!($s).is_documentation()); + assert!(ip.is_documentation()); } else { - assert!(!ip!($s).is_documentation()); + assert!(!ip.is_documentation()); } if ($mask & benchmarking) == benchmarking { - assert!(ip!($s).is_benchmarking()); + assert!(ip.is_benchmarking()); } else { - assert!(!ip!($s).is_benchmarking()); + assert!(!ip.is_benchmarking()); } }}; } @@ -339,18 +336,15 @@ fn ip_properties() { #[test] fn ipv4_properties() { - macro_rules! ip { - ($s:expr) => { - Ipv4Addr::from_str($s).unwrap() - }; - } - macro_rules! check { ($s:expr) => { check!($s, 0); }; ($s:expr, $mask:expr) => {{ + let ip = Ipv4Addr::from_str($s).unwrap(); + assert_eq!($s, ip.to_string()); + let unspec: u16 = 1 << 0; let loopback: u16 = 1 << 1; let private: u16 = 1 << 2; @@ -364,69 +358,69 @@ fn ipv4_properties() { let shared: u16 = 1 << 11; if ($mask & unspec) == unspec { - assert!(ip!($s).is_unspecified()); + assert!(ip.is_unspecified()); } else { - assert!(!ip!($s).is_unspecified()); + assert!(!ip.is_unspecified()); } if ($mask & loopback) == loopback { - assert!(ip!($s).is_loopback()); + assert!(ip.is_loopback()); } else { - assert!(!ip!($s).is_loopback()); + assert!(!ip.is_loopback()); } if ($mask & private) == private { - assert!(ip!($s).is_private()); + assert!(ip.is_private()); } else { - assert!(!ip!($s).is_private()); + assert!(!ip.is_private()); } if ($mask & link_local) == link_local { - assert!(ip!($s).is_link_local()); + assert!(ip.is_link_local()); } else { - assert!(!ip!($s).is_link_local()); + assert!(!ip.is_link_local()); } if ($mask & global) == global { - assert!(ip!($s).is_global()); + assert!(ip.is_global()); } else { - assert!(!ip!($s).is_global()); + assert!(!ip.is_global()); } if ($mask & multicast) == multicast { - assert!(ip!($s).is_multicast()); + assert!(ip.is_multicast()); } else { - assert!(!ip!($s).is_multicast()); + assert!(!ip.is_multicast()); } if ($mask & broadcast) == broadcast { - assert!(ip!($s).is_broadcast()); + assert!(ip.is_broadcast()); } else { - assert!(!ip!($s).is_broadcast()); + assert!(!ip.is_broadcast()); } if ($mask & documentation) == documentation { - assert!(ip!($s).is_documentation()); + assert!(ip.is_documentation()); } else { - assert!(!ip!($s).is_documentation()); + assert!(!ip.is_documentation()); } if ($mask & benchmarking) == benchmarking { - assert!(ip!($s).is_benchmarking()); + assert!(ip.is_benchmarking()); } else { - assert!(!ip!($s).is_benchmarking()); + assert!(!ip.is_benchmarking()); } if ($mask & reserved) == reserved { - assert!(ip!($s).is_reserved()); + assert!(ip.is_reserved()); } else { - assert!(!ip!($s).is_reserved()); + assert!(!ip.is_reserved()); } if ($mask & shared) == shared { - assert!(ip!($s).is_shared()); + assert!(ip.is_shared()); } else { - assert!(!ip!($s).is_shared()); + assert!(!ip.is_shared()); } }}; } @@ -479,23 +473,19 @@ fn ipv4_properties() { #[test] fn ipv6_properties() { - macro_rules! ip { - ($s:expr) => { - Ipv6Addr::from_str($s).unwrap() - }; - } - macro_rules! check { ($s:expr, &[$($octet:expr),*]) => { check!($s, &[$($octet),*], 0); }; ($s:expr, &[$($octet:expr),*], $mask:expr) => { - assert_eq!($s, ip!($s).to_string()); + let ip = Ipv6Addr::from_str($s).unwrap(); + assert_eq!($s, ip.to_string()); + let octets = &[$($octet),*]; - assert_eq!(&ip!($s).octets(), octets); - assert_eq!(Ipv6Addr::from(*octets), ip!($s)); - assert_eq!(Ipv6Addr::from_octets(*octets), ip!($s)); + assert_eq!(&ip.octets(), octets); + assert_eq!(Ipv6Addr::from(*octets), ip); + assert_eq!(Ipv6Addr::from_octets(*octets), ip); let unspecified: u32 = 1 << 0; let loopback: u32 = 1 << 1; @@ -522,84 +512,84 @@ fn ipv6_properties() { let ipv4_mapped: u32 = 1 << 17; if ($mask & unspecified) == unspecified { - assert!(ip!($s).is_unspecified()); + assert!(ip.is_unspecified()); } else { - assert!(!ip!($s).is_unspecified()); + assert!(!ip.is_unspecified()); } if ($mask & loopback) == loopback { - assert!(ip!($s).is_loopback()); + assert!(ip.is_loopback()); } else { - assert!(!ip!($s).is_loopback()); + assert!(!ip.is_loopback()); } if ($mask & unique_local) == unique_local { - assert!(ip!($s).is_unique_local()); + assert!(ip.is_unique_local()); } else { - assert!(!ip!($s).is_unique_local()); + assert!(!ip.is_unique_local()); } if ($mask & global) == global { - assert!(ip!($s).is_global()); + assert!(ip.is_global()); } else { - assert!(!ip!($s).is_global()); + assert!(!ip.is_global()); } if ($mask & unicast_link_local) == unicast_link_local { - assert!(ip!($s).is_unicast_link_local()); + assert!(ip.is_unicast_link_local()); } else { - assert!(!ip!($s).is_unicast_link_local()); + assert!(!ip.is_unicast_link_local()); } if ($mask & unicast_global) == unicast_global { - assert!(ip!($s).is_unicast_global()); + assert!(ip.is_unicast_global()); } else { - assert!(!ip!($s).is_unicast_global()); + assert!(!ip.is_unicast_global()); } if ($mask & documentation) == documentation { - assert!(ip!($s).is_documentation()); + assert!(ip.is_documentation()); } else { - assert!(!ip!($s).is_documentation()); + assert!(!ip.is_documentation()); } if ($mask & benchmarking) == benchmarking { - assert!(ip!($s).is_benchmarking()); + assert!(ip.is_benchmarking()); } else { - assert!(!ip!($s).is_benchmarking()); + assert!(!ip.is_benchmarking()); } if ($mask & multicast) != 0 { - assert!(ip!($s).multicast_scope().is_some()); - assert!(ip!($s).is_multicast()); + assert!(ip.multicast_scope().is_some()); + assert!(ip.is_multicast()); } else { - assert!(ip!($s).multicast_scope().is_none()); - assert!(!ip!($s).is_multicast()); + assert!(ip.multicast_scope().is_none()); + assert!(!ip.is_multicast()); } if ($mask & multicast_interface_local) == multicast_interface_local { - assert_eq!(ip!($s).multicast_scope().unwrap(), + assert_eq!(ip.multicast_scope().unwrap(), Ipv6MulticastScope::InterfaceLocal); } if ($mask & multicast_link_local) == multicast_link_local { - assert_eq!(ip!($s).multicast_scope().unwrap(), + assert_eq!(ip.multicast_scope().unwrap(), Ipv6MulticastScope::LinkLocal); } if ($mask & multicast_realm_local) == multicast_realm_local { - assert_eq!(ip!($s).multicast_scope().unwrap(), + assert_eq!(ip.multicast_scope().unwrap(), Ipv6MulticastScope::RealmLocal); } if ($mask & multicast_admin_local) == multicast_admin_local { - assert_eq!(ip!($s).multicast_scope().unwrap(), + assert_eq!(ip.multicast_scope().unwrap(), Ipv6MulticastScope::AdminLocal); } if ($mask & multicast_site_local) == multicast_site_local { - assert_eq!(ip!($s).multicast_scope().unwrap(), + assert_eq!(ip.multicast_scope().unwrap(), Ipv6MulticastScope::SiteLocal); } if ($mask & multicast_organization_local) == multicast_organization_local { - assert_eq!(ip!($s).multicast_scope().unwrap(), + assert_eq!(ip.multicast_scope().unwrap(), Ipv6MulticastScope::OrganizationLocal); } if ($mask & multicast_global) == multicast_global { - assert_eq!(ip!($s).multicast_scope().unwrap(), + assert_eq!(ip.multicast_scope().unwrap(), Ipv6MulticastScope::Global); } if ($mask & ipv4_mapped) == ipv4_mapped { - assert!(ip!($s).is_ipv4_mapped()); + assert!(ip.is_ipv4_mapped()); } else { - assert!(!ip!($s).is_ipv4_mapped()); + assert!(!ip.is_ipv4_mapped()); } } } diff --git a/library/coretests/tests/nonzero.rs b/library/coretests/tests/nonzero.rs index c368a2621740b..5efc09fd2d98e 100644 --- a/library/coretests/tests/nonzero.rs +++ b/library/coretests/tests/nonzero.rs @@ -124,6 +124,100 @@ fn test_from_signed_nonzero() { assert_eq!(num, 1i32); } +#[test] +fn test_from_ascii_bytes_radix() { + assert_eq!(NonZero::::from_ascii_bytes_radix(b"123", 10), Ok(NonZero::new(123).unwrap())); + assert_eq!(NonZero::::from_ascii_bytes_radix(b"1001", 2), Ok(NonZero::new(9).unwrap())); + assert_eq!(NonZero::::from_ascii_bytes_radix(b"123", 8), Ok(NonZero::new(83).unwrap())); + assert_eq!(NonZero::::from_ascii_bytes_radix(b"123", 16), Ok(NonZero::new(291).unwrap())); + assert_eq!( + NonZero::::from_ascii_bytes_radix(b"ffff", 16), + Ok(NonZero::new(65535).unwrap()) + ); + assert_eq!(NonZero::::from_ascii_bytes_radix(b"z", 36), Ok(NonZero::new(35).unwrap())); + assert_eq!( + NonZero::::from_ascii_bytes_radix(b"0", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::Zero) + ); + assert_eq!( + NonZero::::from_ascii_bytes_radix(b"-1", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::InvalidDigit) + ); + assert_eq!( + NonZero::::from_ascii_bytes_radix(b"-129", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::NegOverflow) + ); + assert_eq!( + NonZero::::from_ascii_bytes_radix(b"257", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::PosOverflow) + ); + + assert_eq!( + NonZero::::from_ascii_bytes_radix(b"Z", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::InvalidDigit) + ); + assert_eq!( + NonZero::::from_ascii_bytes_radix(b"_", 2).err().map(|e| e.kind().clone()), + Some(IntErrorKind::InvalidDigit) + ); +} + +#[test] +fn test_from_ascii_bytes() { + assert_eq!(NonZero::::from_ascii_bytes(b"123"), Ok(NonZero::new(123).unwrap())); + assert_eq!( + NonZero::::from_ascii_bytes(b"0").err().map(|e| e.kind().clone()), + Some(IntErrorKind::Zero) + ); + assert_eq!( + NonZero::::from_ascii_bytes(b"-1").err().map(|e| e.kind().clone()), + Some(IntErrorKind::InvalidDigit) + ); + assert_eq!( + NonZero::::from_ascii_bytes(b"-129").err().map(|e| e.kind().clone()), + Some(IntErrorKind::NegOverflow) + ); + assert_eq!( + NonZero::::from_ascii_bytes(b"257").err().map(|e| e.kind().clone()), + Some(IntErrorKind::PosOverflow) + ); +} + +#[test] +fn test_from_str_radix() { + assert_eq!(NonZero::::from_str_radix("123", 10), Ok(NonZero::new(123).unwrap())); + assert_eq!(NonZero::::from_str_radix("1001", 2), Ok(NonZero::new(9).unwrap())); + assert_eq!(NonZero::::from_str_radix("123", 8), Ok(NonZero::new(83).unwrap())); + assert_eq!(NonZero::::from_str_radix("123", 16), Ok(NonZero::new(291).unwrap())); + assert_eq!(NonZero::::from_str_radix("ffff", 16), Ok(NonZero::new(65535).unwrap())); + assert_eq!(NonZero::::from_str_radix("z", 36), Ok(NonZero::new(35).unwrap())); + assert_eq!( + NonZero::::from_str_radix("0", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::Zero) + ); + assert_eq!( + NonZero::::from_str_radix("-1", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::InvalidDigit) + ); + assert_eq!( + NonZero::::from_str_radix("-129", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::NegOverflow) + ); + assert_eq!( + NonZero::::from_str_radix("257", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::PosOverflow) + ); + + assert_eq!( + NonZero::::from_str_radix("Z", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::InvalidDigit) + ); + assert_eq!( + NonZero::::from_str_radix("_", 2).err().map(|e| e.kind().clone()), + Some(IntErrorKind::InvalidDigit) + ); +} + #[test] fn test_from_str() { assert_eq!("123".parse::>(), Ok(NonZero::new(123).unwrap())); @@ -191,11 +285,11 @@ fn test_nonzero_from_int_on_success() { #[test] fn test_nonzero_from_int_on_err() { - assert!(NonZero::::try_from(0).is_err()); - assert!(NonZero::::try_from(0).is_err()); + assert_eq!(NonZero::::try_from(0).unwrap_err().kind(), &IntErrorKind::Zero); + assert_eq!(NonZero::::try_from(0).unwrap_err().kind(), &IntErrorKind::Zero); - assert!(NonZero::::try_from(0).is_err()); - assert!(NonZero::::try_from(0).is_err()); + assert_eq!(NonZero::::try_from(0).unwrap_err().kind(), &IntErrorKind::Zero); + assert_eq!(NonZero::::try_from(0).unwrap_err().kind(), &IntErrorKind::Zero); } #[test] diff --git a/library/coretests/tests/num/bignum.rs b/library/coretests/tests/num/bignum.rs index 6dfa496e018bf..2b4c30cc261cb 100644 --- a/library/coretests/tests/num/bignum.rs +++ b/library/coretests/tests/num/bignum.rs @@ -1,5 +1,5 @@ -use core::num::bignum::Big32x40; -use core::num::bignum::tests::Big8x3 as Big; +use core::num::imp::bignum::Big32x40; +use core::num::imp::bignum::tests::Big8x3 as Big; #[test] #[should_panic] diff --git a/library/coretests/tests/num/carryless_mul.rs b/library/coretests/tests/num/carryless_mul.rs new file mode 100644 index 0000000000000..5d4690beaedea --- /dev/null +++ b/library/coretests/tests/num/carryless_mul.rs @@ -0,0 +1,254 @@ +//! Tests the `Unsigned::{carryless_mul, widening_carryless_mul, carrying_carryless_mul}` methods. + +#[test] +fn carryless_mul_u128() { + assert_eq_const_safe!(u128: ::carryless_mul(0, 0), 0); + assert_eq_const_safe!(u128: ::carryless_mul(1, 1), 1); + + assert_eq_const_safe!( + u128: ::carryless_mul( + 0x0123456789ABCDEF_FEDCBA9876543210, + 1u128 << 64, + ), + 0xFEDCBA9876543210_0000000000000000 + ); + + assert_eq_const_safe!( + u128: ::carryless_mul( + 0x0123456789ABCDEF_FEDCBA9876543210, + (1u128 << 64) | 1, + ), + 0xFFFFFFFFFFFFFFFF_FEDCBA9876543210 + ); + + assert_eq_const_safe!( + u128: ::carryless_mul( + 0x0123456789ABCDEF_FEDCBA9876543211, + 1u128 << 127, + ), + 0x8000000000000000_0000000000000000 + ); + + assert_eq_const_safe!( + u128: ::carryless_mul( + 0xAAAAAAAAAAAAAAAA_AAAAAAAAAAAAAAAA, + 0x5555555555555555_5555555555555555, + ), + 0x2222222222222222_2222222222222222 + ); + + assert_eq_const_safe!( + u128: ::carryless_mul( + (1 << 127) | (1 << 64) | 1, + (1 << 63) | 1 + ), + (1 << 64) | (1 << 63) | 1 + ); + + assert_eq_const_safe!( + u128: ::carryless_mul( + 0x8000000000000000_0000000000000001, + 0x7FFFFFFFFFFFFFFF_FFFFFFFFFFFFFFFF, + ), + 0xFFFFFFFFFFFFFFFF_FFFFFFFFFFFFFFFF + ); +} + +#[test] +fn carryless_mul_u64() { + assert_eq_const_safe!(u64: ::carryless_mul(0, 0), 0); + assert_eq_const_safe!(u64: ::carryless_mul(1, 1), 1); + + assert_eq_const_safe!( + u64: ::carryless_mul( + 0x0123_4567_89AB_CDEF, + 1u64 << 32, + ), + 0x89AB_CDEF_0000_0000 + ); + + assert_eq_const_safe!( + u64: ::carryless_mul( + 0x0123_4567_89AB_CDEF, + (1u64 << 32) | 1, + ), + 0x8888_8888_89AB_CDEF + ); + + assert_eq_const_safe!( + u64: ::carryless_mul( + 0x0123_4567_89AB_CDEF, + 1u64 << 63, + ), + 0x8000_0000_0000_0000 + ); + + assert_eq_const_safe!( + u64: ::carryless_mul( + 0xAAAA_AAAA_AAAA_AAAA, + 0x5555_5555_5555_5555, + ), + 0x2222_2222_2222_2222 + ); + + assert_eq_const_safe!( + u64: ::carryless_mul( + (1u64 << 63) | (1u64 << 32) | 1, + (1u64 << 31) | 1, + ), + (1u64 << 32) | (1u64 << 31) | 1 + ); + + assert_eq_const_safe!( + u64: ::carryless_mul( + 0x8000_0000_0000_0001, + 0x7FFF_FFFF_FFFF_FFFF, + ), + 0xFFFF_FFFF_FFFF_FFFF + ); +} + +#[test] +fn carryless_mul_u32() { + assert_eq_const_safe!( + u32: ::carryless_mul(0x0123_4567, 1u32 << 16), + 0x4567_0000 + ); + + assert_eq_const_safe!( + u32: ::carryless_mul(0xAAAA_AAAA, 0x5555_5555), + 0x2222_2222 + ); +} + +#[test] +fn carryless_mul_u16() { + assert_eq_const_safe!( + u16: ::carryless_mul(0x0123, 1u16 << 8), + 0x2300 + ); + + assert_eq_const_safe!( + u16: ::carryless_mul(0xAAAA, 0x5555), + 0x2222 + ); +} + +#[test] +fn carryless_mul_u8() { + assert_eq_const_safe!( + u8: ::carryless_mul(0x01, 1u8 << 4), + 0x10 + ); + + assert_eq_const_safe!( + u8: ::carryless_mul(0xAA, 0x55), + 0x22 + ); +} + +#[test] +fn widening_carryless_mul() { + assert_eq_const_safe!( + u16: ::widening_carryless_mul(0xEFu8, 1u8 << 7), + 0x7780u16 + ); + assert_eq_const_safe!( + u16: ::widening_carryless_mul(0xEFu8, (1u8 << 7) | 1), + 0x776Fu16 + ); + + assert_eq_const_safe!( + u32: ::widening_carryless_mul(0xBEEFu16, 1u16 << 15), + 0x5F77_8000u32 + ); + assert_eq_const_safe!( + u32: ::widening_carryless_mul(0xBEEFu16, (1u16 << 15) | 1), + 0x5F77_3EEFu32 + ); + + assert_eq_const_safe!( + u64: ::widening_carryless_mul(0xDEAD_BEEFu32, 1u32 << 31), + 0x6F56_DF77_8000_0000u64 + ); + assert_eq_const_safe!( + u64: ::widening_carryless_mul(0xDEAD_BEEFu32, (1u32 << 31) | 1), + 0x6F56_DF77_5EAD_BEEFu64 + ); + + assert_eq_const_safe!( + u128: ::widening_carryless_mul(0xDEAD_BEEF_FACE_FEEDu64, 1u64 << 63), + 147995377545877439359040026616086396928 + + ); + assert_eq_const_safe!( + u128: ::widening_carryless_mul(0xDEAD_BEEF_FACE_FEEDu64, (1u64 << 63) | 1), + 147995377545877439356638973527682121453 + ); +} + +#[test] +fn carrying_carryless_mul() { + assert_eq_const_safe!( + (u8, u8): ::carrying_carryless_mul(0xEFu8, 1u8 << 7, 0), + (0x80u8, 0x77u8) + ); + assert_eq_const_safe!( + (u8, u8): ::carrying_carryless_mul(0xEFu8, (1u8 << 7) | 1, 0xEF), + (0x80u8, 0x77u8) + ); + + assert_eq_const_safe!( + (u16, u16): ::carrying_carryless_mul(0xBEEFu16, 1u16 << 15, 0), + (0x8000u16, 0x5F77u16) + ); + assert_eq_const_safe!( + (u16, u16): ::carrying_carryless_mul(0xBEEFu16, (1u16 << 15) | 1, 0xBEEF), + (0x8000u16, 0x5F77u16) + ); + + assert_eq_const_safe!( + (u32, u32): ::carrying_carryless_mul(0xDEAD_BEEFu32, 1u32 << 31, 0), + (0x8000_0000u32, 0x6F56_DF77u32) + ); + assert_eq_const_safe!( + (u32, u32): ::carrying_carryless_mul(0xDEAD_BEEFu32, (1u32 << 31) | 1, 0xDEAD_BEEF), + (0x8000_0000u32, 0x6F56_DF77u32) + ); + + assert_eq_const_safe!( + (u64, u64): ::carrying_carryless_mul(0xDEAD_BEEF_FACE_FEEDu64, 1u64 << 63, 0), + (9223372036854775808, 8022845492652638070) + ); + assert_eq_const_safe!( + (u64, u64): ::carrying_carryless_mul( + 0xDEAD_BEEF_FACE_FEEDu64, + (1u64 << 63) | 1, + 0xDEAD_BEEF_FACE_FEED, + ), + (9223372036854775808, 8022845492652638070) + ); + + assert_eq_const_safe!( + (u128, u128): ::carrying_carryless_mul( + 0xDEAD_BEEF_FACE_FEED_0123_4567_89AB_CDEFu128, + 1u128 << 127, + 0, + ), + ( + 0x8000_0000_0000_0000_0000_0000_0000_0000u128, + 147995377545877439359081019380694640375, + ) + ); + assert_eq_const_safe!( + (u128, u128): ::carrying_carryless_mul( + 0xDEAD_BEEF_FACE_FEED_0123_4567_89AB_CDEFu128, + (1u128 << 127) | 1, + 0xDEAD_BEEF_FACE_FEED_0123_4567_89AB_CDEF, + ), + ( + 0x8000_0000_0000_0000_0000_0000_0000_0000u128, + 147995377545877439359081019380694640375, + ) + ); +} diff --git a/library/coretests/tests/num/cast.rs b/library/coretests/tests/num/cast.rs new file mode 100644 index 0000000000000..dddfd3a02ee64 --- /dev/null +++ b/library/coretests/tests/num/cast.rs @@ -0,0 +1,101 @@ +use std::sync::LazyLock; + +// All (negative) integers which are at or near a power of two to test +// boundary conditions. We use strings so we can convert to any type using +// parsing, while still being able to use the *position* in ORDERED_VALS for +// comparisons. +static ORDERED_VALS: LazyLock> = LazyLock::new(|| { + let mut pos_int_vals = Vec::new(); + for exp in 0..=127 { + let val = 1_u128 << exp; + pos_int_vals.push(val.saturating_sub(2)); + pos_int_vals.push(val.saturating_sub(1)); + pos_int_vals.push(val); + pos_int_vals.push(val.saturating_add(1)); + pos_int_vals.push(val.saturating_add(2)); + } + pos_int_vals.sort(); + pos_int_vals.dedup(); + + let mut pos_str_vals: Vec<_> = pos_int_vals.iter().map(|i| i.to_string()).collect(); + + // These are manual because the upper ones overflow even u128. + pos_str_vals.push("340282366920938463463374607431768211454".to_owned()); // 2**128 - 2 + pos_str_vals.push("340282366920938463463374607431768211455".to_owned()); // 2**128 - 1 + pos_str_vals.push("340282366920938463463374607431768211456".to_owned()); // 2**128 + pos_str_vals.push("340282366920938463463374607431768211457".to_owned()); // 2**128 + 1 + pos_str_vals.push("340282366920938463463374607431768211458".to_owned()); // 2**128 + 2 + + let mut out = Vec::new(); + for val in pos_str_vals[1..].iter().rev() { + out.push(format!("-{val}")); + } + out.extend(pos_str_vals); + out +}); + +macro_rules! make_checked_cast_test { + ($Src:ident as [$($Dst:ident),*]) => {$( + #[test] + #[allow(non_snake_case)] + fn ${concat(test_checked_cast_, $Src, _to_, $Dst)}() { + for val in ORDERED_VALS.iter() { + if let Some(src) = val.parse::<$Src>().ok() { + let dst: Option<$Dst> = val.parse().ok(); + assert_eq!(src.checked_cast::<$Dst>(), dst); + } + } + } + )*} +} + +macro_rules! make_bounded_cast_test { + (|$src:ident| $raw:expr, $Src:ident as [$($Dst:ident),*]) => {$( + #[test] + #[allow(non_snake_case)] + fn ${concat(test_bounded_cast_, $Src, _to_, $Dst)}() { + let ord_idx = |s| ORDERED_VALS.iter().position(|v| *v == s).unwrap(); + let dst_min_idx = ord_idx(<$Dst>::MIN.to_string()); + let dst_max_idx = ord_idx(<$Dst>::MAX.to_string()); + for (val_idx, val) in ORDERED_VALS.iter().enumerate() { + if let Some($src) = val.parse::<$Src>().ok() { + let dst: Option<$Dst> = val.parse().ok(); + + assert_eq!($src.wrapping_cast::<$Dst>(), $raw as $Dst); + + if val_idx > dst_max_idx { + assert_eq!($src.saturating_cast::<$Dst>(), <$Dst>::MAX); + } else if val_idx < dst_min_idx { + assert_eq!($src.saturating_cast::<$Dst>(), <$Dst>::MIN); + } else { + assert_eq!($src.saturating_cast::<$Dst>(), dst.unwrap()); + } + } + } + } + )*} +} + +macro_rules! make_tests_for_src { + (|$src:ident| $raw:expr, [$($Src:ident),*]) => {$( + make_checked_cast_test!( $Src as [u8, u16, u32, u64, u128, usize, i8, i16, i32, i64, i128, isize]); + make_bounded_cast_test!(|$src| $raw, $Src as [u8, u16, u32, u64, u128, usize, i8, i16, i32, i64, i128, isize]); + + // NonZero types are not (yet) implemented. + // make_checked_cast_test!($Src as [ + // NonZeroU8, NonZeroU16, NonZeroU32, NonZeroU64, NonZeroU128, NonZeroUsize, + // NonZeroI8, NonZeroI16, NonZeroI32, NonZeroI64, NonZeroI128, NonZeroIsize + // ]); + )*} +} + +make_tests_for_src!(|x| x, [u8, u16, u32, u64, u128, usize, i8, i16, i32, i64, i128, isize]); + +// NonZero types are not (yet) implemented. +// make_tests_for_src!( +// |x| x.get(), +// [ +// NonZeroU8, NonZeroU16, NonZeroU32, NonZeroU64, NonZeroU128, NonZeroUsize, +// NonZeroI8, NonZeroI16, NonZeroI32, NonZeroI64, NonZeroI128, NonZeroIsize +// ] +// ); diff --git a/library/coretests/tests/num/dec2flt/decimal.rs b/library/coretests/tests/num/dec2flt/decimal.rs index f5ecc604a99a1..8611310850be7 100644 --- a/library/coretests/tests/num/dec2flt/decimal.rs +++ b/library/coretests/tests/num/dec2flt/decimal.rs @@ -1,4 +1,4 @@ -use core::num::dec2flt::decimal::Decimal; +use core::num::imp::dec2flt::decimal::Decimal; type FPath = ((i64, u64, bool, bool), Option); diff --git a/library/coretests/tests/num/dec2flt/decimal_seq.rs b/library/coretests/tests/num/dec2flt/decimal_seq.rs index f46ba7c465a6e..f2fee3a0d8e85 100644 --- a/library/coretests/tests/num/dec2flt/decimal_seq.rs +++ b/library/coretests/tests/num/dec2flt/decimal_seq.rs @@ -1,4 +1,4 @@ -use core::num::dec2flt::decimal_seq::{DecimalSeq, parse_decimal_seq}; +use core::num::imp::dec2flt::decimal_seq::{DecimalSeq, parse_decimal_seq}; #[test] fn test_trim() { diff --git a/library/coretests/tests/num/dec2flt/float.rs b/library/coretests/tests/num/dec2flt/float.rs index 734cb7e4f7dbd..0713c5c651fb3 100644 --- a/library/coretests/tests/num/dec2flt/float.rs +++ b/library/coretests/tests/num/dec2flt/float.rs @@ -1,4 +1,5 @@ -use core::num::dec2flt::float::RawFloat; +use core::num::imp::dec2flt::Lemire; +use core::num::imp::{Float, FloatExt}; use crate::num::{ldexp_f32, ldexp_f64}; @@ -56,57 +57,60 @@ fn test_f64_integer_decode() { #[test] #[cfg(target_has_reliable_f16)] fn test_f16_consts() { - assert_eq!(::INFINITY, f16::INFINITY); - assert_eq!(::NEG_INFINITY, -f16::INFINITY); - assert_eq!(::NAN.to_bits(), f16::NAN.to_bits()); - assert_eq!(::NEG_NAN.to_bits(), (-f16::NAN).to_bits()); - assert_eq!(::SIG_BITS, 10); - assert_eq!(::MIN_EXPONENT_ROUND_TO_EVEN, -22); - assert_eq!(::MAX_EXPONENT_ROUND_TO_EVEN, 5); - assert_eq!(::MIN_EXPONENT_FAST_PATH, -4); - assert_eq!(::MAX_EXPONENT_FAST_PATH, 4); - assert_eq!(::MAX_EXPONENT_DISGUISED_FAST_PATH, 7); - assert_eq!(::EXP_MIN, -14); - assert_eq!(::EXP_SAT, 0x1f); - assert_eq!(::SMALLEST_POWER_OF_TEN, -27); - assert_eq!(::LARGEST_POWER_OF_TEN, 4); - assert_eq!(::MAX_MANTISSA_FAST_PATH, 2048); + assert_eq!(::INFINITY, f16::INFINITY); + assert_eq!(::NEG_INFINITY, -f16::INFINITY); + assert_eq!(::NAN.to_bits(), f16::NAN.to_bits()); + assert_eq!(::NEG_NAN.to_bits(), (-f16::NAN).to_bits()); + assert_eq!(::SIG_BITS, 10); + assert_eq!(::MIN_EXPONENT_ROUND_TO_EVEN, -22); + assert_eq!(::MAX_EXPONENT_ROUND_TO_EVEN, 5); + assert_eq!(::EXP_MIN, -14); + assert_eq!(::EXP_SAT, 0x1f); + assert_eq!(::SMALLEST_POWER_OF_TEN, -27); + assert_eq!(::LARGEST_POWER_OF_TEN, 4); + + assert_eq!(::MIN_EXPONENT_FAST_PATH, -4); + assert_eq!(::MAX_EXPONENT_FAST_PATH, 4); + assert_eq!(::MAX_EXPONENT_DISGUISED_FAST_PATH, 7); + assert_eq!(::MAX_MANTISSA_FAST_PATH, 2048); } #[test] fn test_f32_consts() { - assert_eq!(::INFINITY, f32::INFINITY); - assert_eq!(::NEG_INFINITY, -f32::INFINITY); - assert_eq!(::NAN.to_bits(), f32::NAN.to_bits()); - assert_eq!(::NEG_NAN.to_bits(), (-f32::NAN).to_bits()); - assert_eq!(::SIG_BITS, 23); - assert_eq!(::MIN_EXPONENT_ROUND_TO_EVEN, -17); - assert_eq!(::MAX_EXPONENT_ROUND_TO_EVEN, 10); - assert_eq!(::MIN_EXPONENT_FAST_PATH, -10); - assert_eq!(::MAX_EXPONENT_FAST_PATH, 10); - assert_eq!(::MAX_EXPONENT_DISGUISED_FAST_PATH, 17); - assert_eq!(::EXP_MIN, -126); - assert_eq!(::EXP_SAT, 0xff); - assert_eq!(::SMALLEST_POWER_OF_TEN, -65); - assert_eq!(::LARGEST_POWER_OF_TEN, 38); - assert_eq!(::MAX_MANTISSA_FAST_PATH, 16777216); + assert_eq!(::INFINITY, f32::INFINITY); + assert_eq!(::NEG_INFINITY, -f32::INFINITY); + assert_eq!(::NAN.to_bits(), f32::NAN.to_bits()); + assert_eq!(::NEG_NAN.to_bits(), (-f32::NAN).to_bits()); + assert_eq!(::SIG_BITS, 23); + assert_eq!(::MIN_EXPONENT_ROUND_TO_EVEN, -17); + assert_eq!(::MAX_EXPONENT_ROUND_TO_EVEN, 10); + assert_eq!(::EXP_MIN, -126); + assert_eq!(::EXP_SAT, 0xff); + assert_eq!(::SMALLEST_POWER_OF_TEN, -65); + assert_eq!(::LARGEST_POWER_OF_TEN, 38); + + assert_eq!(::MIN_EXPONENT_FAST_PATH, -10); + assert_eq!(::MAX_EXPONENT_FAST_PATH, 10); + assert_eq!(::MAX_EXPONENT_DISGUISED_FAST_PATH, 17); + assert_eq!(::MAX_MANTISSA_FAST_PATH, 16777216); } #[test] fn test_f64_consts() { - assert_eq!(::INFINITY, f64::INFINITY); - assert_eq!(::NEG_INFINITY, -f64::INFINITY); - assert_eq!(::NAN.to_bits(), f64::NAN.to_bits()); - assert_eq!(::NEG_NAN.to_bits(), (-f64::NAN).to_bits()); - assert_eq!(::SIG_BITS, 52); - assert_eq!(::MIN_EXPONENT_ROUND_TO_EVEN, -4); - assert_eq!(::MAX_EXPONENT_ROUND_TO_EVEN, 23); - assert_eq!(::MIN_EXPONENT_FAST_PATH, -22); - assert_eq!(::MAX_EXPONENT_FAST_PATH, 22); - assert_eq!(::MAX_EXPONENT_DISGUISED_FAST_PATH, 37); - assert_eq!(::EXP_MIN, -1022); - assert_eq!(::EXP_SAT, 0x7ff); - assert_eq!(::SMALLEST_POWER_OF_TEN, -342); - assert_eq!(::LARGEST_POWER_OF_TEN, 308); - assert_eq!(::MAX_MANTISSA_FAST_PATH, 9007199254740992); + assert_eq!(::INFINITY, f64::INFINITY); + assert_eq!(::NEG_INFINITY, -f64::INFINITY); + assert_eq!(::NAN.to_bits(), f64::NAN.to_bits()); + assert_eq!(::NEG_NAN.to_bits(), (-f64::NAN).to_bits()); + assert_eq!(::SIG_BITS, 52); + assert_eq!(::MIN_EXPONENT_ROUND_TO_EVEN, -4); + assert_eq!(::MAX_EXPONENT_ROUND_TO_EVEN, 23); + assert_eq!(::EXP_MIN, -1022); + assert_eq!(::EXP_SAT, 0x7ff); + assert_eq!(::SMALLEST_POWER_OF_TEN, -342); + assert_eq!(::LARGEST_POWER_OF_TEN, 308); + + assert_eq!(::MIN_EXPONENT_FAST_PATH, -22); + assert_eq!(::MAX_EXPONENT_FAST_PATH, 22); + assert_eq!(::MAX_EXPONENT_DISGUISED_FAST_PATH, 37); + assert_eq!(::MAX_MANTISSA_FAST_PATH, 9007199254740992); } diff --git a/library/coretests/tests/num/dec2flt/lemire.rs b/library/coretests/tests/num/dec2flt/lemire.rs index ba359a0495fef..e5a7ae346f425 100644 --- a/library/coretests/tests/num/dec2flt/lemire.rs +++ b/library/coretests/tests/num/dec2flt/lemire.rs @@ -1,5 +1,6 @@ -use core::num::dec2flt::float::RawFloat; -use core::num::dec2flt::lemire::compute_float; +use core::num::imp::{Float, dec2flt}; + +use dec2flt::lemire::compute_float; #[cfg(target_has_reliable_f16)] fn compute_float16(q: i64, w: u64) -> (i32, u64) { diff --git a/library/coretests/tests/num/dec2flt/parse.rs b/library/coretests/tests/num/dec2flt/parse.rs index 65f1289d531b3..a63cdb3873762 100644 --- a/library/coretests/tests/num/dec2flt/parse.rs +++ b/library/coretests/tests/num/dec2flt/parse.rs @@ -1,6 +1,8 @@ -use core::num::dec2flt::decimal::Decimal; -use core::num::dec2flt::parse::parse_number; -use core::num::dec2flt::{dec2flt, pfe_invalid}; +use core::num::imp::dec2flt; + +use dec2flt::decimal::Decimal; +use dec2flt::parse::parse_number; +use dec2flt::{dec2flt, pfe_invalid}; fn new_dec(e: i64, m: u64) -> Decimal { Decimal { exponent: e, mantissa: m, negative: false, many_digits: false } diff --git a/library/coretests/tests/num/float_ieee754_flt2dec_dec2flt.rs b/library/coretests/tests/num/float_ieee754_flt2dec_dec2flt.rs new file mode 100644 index 0000000000000..c0ff8175eef30 --- /dev/null +++ b/library/coretests/tests/num/float_ieee754_flt2dec_dec2flt.rs @@ -0,0 +1,166 @@ +//! IEEE 754 floating point compliance tests +//! +//! To understand IEEE 754's requirements on a programming language, one must understand that the +//! requirements of IEEE 754 rest on the total programming environment, and not entirely on any +//! one component. That means the hardware, language, and even libraries are considered part of +//! conforming floating point support in a programming environment. +//! +//! A programming language's duty, accordingly, is: +//! 1. offer access to the hardware where the hardware offers support +//! 2. provide operations that fulfill the remaining requirements of the standard +//! 3. provide the ability to write additional software that can fulfill those requirements +//! +//! This may be fulfilled in any combination that the language sees fit. However, to claim that +//! a language supports IEEE 754 is to suggest that it has fulfilled requirements 1 and 2, without +//! deferring minimum requirements to libraries. This is because support for IEEE 754 is defined +//! as complete support for at least one specified floating point type as an "arithmetic" and +//! "interchange" format, plus specified type conversions to "external character sequences" and +//! integer types. +//! +//! For our purposes, +//! "interchange format" => f16, f32, f64, f128 +//! "arithmetic format" => f16, f32, f64, f128, and any "soft floats" +//! "external character sequence" => str from any float +//! "integer format" => {i,u}{8,16,32,64,128} +//! +//! None of these tests are against Rust's own implementation. They are only tests against the +//! standard. That is why they accept wildly diverse inputs or may seem to duplicate other tests. +//! Please consider this carefully when adding, removing, or reorganizing these tests. They are +//! here so that it is clear what tests are required by the standard and what can be changed. + +use core::fmt; +use core::str::FromStr; + +use crate::num::{assert_biteq, float_test}; + +/// ToString uses the default fmt::Display impl without special concerns, and bypasses other parts +/// of the formatting infrastructure, which makes it ideal for testing here. +#[track_caller] +fn string_roundtrip(x: T) -> T +where + T: FromStr + fmt::Display, +{ + x.to_string().parse::().unwrap() +} + +// FIXME(f128): Tests are disabled while we don't have parsing / printing + +// We must preserve signs on all numbers. That includes zero. +// -0 and 0 are == normally, so test bit equality. +float_test! { + name: preserve_signed_zero, + attrs: { + const: #[cfg(false)], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(false)], + }, + test { + let neg0 = flt(-0.0); + let pos0 = flt(0.0); + assert_biteq!(neg0, string_roundtrip(neg0)); + assert_biteq!(pos0, string_roundtrip(pos0)); + assert_ne!(neg0.to_bits(), pos0.to_bits()); + } +} + +float_test! { + name: preserve_signed_infinity, + attrs: { + const: #[cfg(false)], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(false)], + }, + test { + let neg_inf = Float::NEG_INFINITY; + let pos_inf = Float::INFINITY; + assert_biteq!(neg_inf, string_roundtrip(neg_inf)); + assert_biteq!(pos_inf, string_roundtrip(pos_inf)); + assert_ne!(neg_inf.to_bits(), pos_inf.to_bits()); + } +} + +float_test! { + name: infinity_to_str, + attrs: { + const: #[cfg(false)], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(false)], + }, + test { + assert!( + match Float::INFINITY.to_string().to_lowercase().as_str() { + "+infinity" | "infinity" => true, + "+inf" | "inf" => true, + _ => false, + }, + "Infinity must write to a string as some casing of inf or infinity, with an optional +." + ); + assert!( + match Float::NEG_INFINITY.to_string().to_lowercase().as_str() { + "-infinity" | "-inf" => true, + _ => false, + }, + "Negative Infinity must write to a string as some casing of -inf or -infinity" + ); + } +} + +float_test! { + name: nan_to_str, + attrs: { + const: #[cfg(false)], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(false)], + }, + test { + assert!( + match Float::NAN.to_string().to_lowercase().as_str() { + "nan" | "+nan" | "-nan" => true, + _ => false, + }, + "NaNs must write to a string as some casing of nan." + ) + } +} + +float_test! { + name: infinity_from_str, + attrs: { + const: #[cfg(false)], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(false)], + }, + test { + // "+"?("inf"|"infinity") in any case => Infinity + assert_biteq!(Float::INFINITY, Float::from_str("infinity").unwrap()); + assert_biteq!(Float::INFINITY, Float::from_str("inf").unwrap()); + assert_biteq!(Float::INFINITY, Float::from_str("+infinity").unwrap()); + assert_biteq!(Float::INFINITY, Float::from_str("+inf").unwrap()); + // yes! this means you are weLcOmE tO mY iNfInItElY tWiStEd MiNd + assert_biteq!(Float::INFINITY, Float::from_str("+iNfInItY").unwrap()); + + // "-inf"|"-infinity" in any case => Negative Infinity + assert_biteq!(Float::NEG_INFINITY, Float::from_str("-infinity").unwrap()); + assert_biteq!(Float::NEG_INFINITY, Float::from_str("-inf").unwrap()); + assert_biteq!(Float::NEG_INFINITY, Float::from_str("-INF").unwrap()); + assert_biteq!(Float::NEG_INFINITY, Float::from_str("-INFinity").unwrap()); + + } +} + +float_test! { + name: qnan_from_str, + attrs: { + const: #[cfg(false)], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(false)], + }, + test { + // ("+"|"-"")?"s"?"nan" in any case => qNaN + assert!("nan".parse::().unwrap().is_nan()); + assert!("-nan".parse::().unwrap().is_nan()); + assert!("+nan".parse::().unwrap().is_nan()); + assert!("+NAN".parse::().unwrap().is_nan()); + assert!("-NaN".parse::().unwrap().is_nan()); + } +} diff --git a/library/coretests/tests/floats/mod.rs b/library/coretests/tests/num/floats.rs similarity index 55% rename from library/coretests/tests/floats/mod.rs rename to library/coretests/tests/num/floats.rs index 06fc3c96eafc8..cc1d1a0b673dc 100644 --- a/library/coretests/tests/floats/mod.rs +++ b/library/coretests/tests/num/floats.rs @@ -1,20 +1,42 @@ +use std::hint::black_box; use std::num::FpCategory as Fp; use std::ops::{Add, Div, Mul, Rem, Sub}; -trait TestableFloat: Sized { +/// i586 has issues with floating point precision. +const I586: bool = cfg!(target_arch = "x86") && cfg!(not(target_feature = "sse2")); + +pub(crate) trait TestableFloat: Sized { + const BITS: u32; /// Unsigned int with the same size, for converting to/from bits. type Int; + /// Signed int with the same size. + type SInt; /// Set the default tolerance for float comparison based on the type. const APPROX: Self; /// Allow looser tolerance for f32 on miri const POWI_APPROX: Self = Self::APPROX; + /// Tolerance for `powf` tests; some types need looser bounds + const POWF_APPROX: Self = Self::APPROX; /// Allow looser tolerance for f16 const _180_TO_RADIANS_APPROX: Self = Self::APPROX; /// Allow for looser tolerance for f16 const PI_TO_DEGREES_APPROX: Self = Self::APPROX; + /// Tolerance for math tests + const EXP_APPROX: Self = Self::APPROX; + const LN_APPROX: Self = Self::APPROX; + const LOG_APPROX: Self = Self::APPROX; + const LOG2_APPROX: Self = Self::APPROX; + const LOG10_APPROX: Self = Self::APPROX; + const ASINH_APPROX: Self = Self::APPROX; + const ACOSH_APPROX: Self = Self::APPROX; + const ATANH_APPROX: Self = Self::APPROX; + const GAMMA_APPROX: Self = Self::APPROX; + const GAMMA_APPROX_LOOSE: Self = Self::APPROX; + const LNGAMMA_APPROX: Self = Self::APPROX; + const LNGAMMA_APPROX_LOOSE: Self = Self::APPROX; const ZERO: Self; const ONE: Self; - const PI: Self; + const SNAN: Self; const MIN_POSITIVE_NORMAL: Self; const MAX_SUBNORMAL: Self; /// Smallest number @@ -40,16 +62,38 @@ trait TestableFloat: Sized { const NEG_MUL_ADD_RESULT: Self; /// Reciprocal of the maximum val const MAX_RECIP: Self; + const ASINH_ACOSH_MAX: Self; } impl TestableFloat for f16 { + const BITS: u32 = 16; type Int = u16; - const APPROX: Self = 1e-3; + type SInt = i16; + /// Miri adds some extra errors to float functions; make sure the tests still pass. + /// These values are purely used as a canary to test against and are thus not a stable guarantee Rust provides. + /// They serve as a way to get an idea of the real precision of floating point operations on different platforms. + const APPROX: Self = if cfg!(miri) { 1e-2 } else { 1e-3 }; + const POWF_APPROX: Self = if cfg!(miri) { 1e-0 } else { 5e-1 }; const _180_TO_RADIANS_APPROX: Self = 1e-2; const PI_TO_DEGREES_APPROX: Self = 0.125; + const EXP_APPROX: Self = if cfg!(miri) { 5e-1 } else { 1e-2 }; // for values on the order of 150, 4 ULP are more than 0.1... + const POWI_APPROX: Self = if cfg!(miri) { 1e-1 } else { Self::APPROX }; + const LN_APPROX: Self = 1e-2; + const LOG_APPROX: Self = if cfg!(miri) { 1e-1 } else { 1e-2 }; + const LOG2_APPROX: Self = 1e-2; + const LOG10_APPROX: Self = 1e-2; + const ASINH_APPROX: Self = 1e-2; + const ACOSH_APPROX: Self = 1e-2; + const ATANH_APPROX: Self = 1e-2; + const GAMMA_APPROX: Self = 1e-2; + const GAMMA_APPROX_LOOSE: Self = 1e-1; + const LNGAMMA_APPROX: Self = 1e-2; + const LNGAMMA_APPROX_LOOSE: Self = 1e-1; const ZERO: Self = 0.0; const ONE: Self = 1.0; - const PI: Self = std::f16::consts::PI; + // We rely on NAN having an all-0 payload, so the signaling bit is the least significant + // non-0 bit, and that gets toggled by the "-1". + const SNAN: Self = Self::from_bits(Self::NAN.to_bits() - 1); const MIN_POSITIVE_NORMAL: Self = Self::MIN_POSITIVE; const MAX_SUBNORMAL: Self = Self::MIN_POSITIVE.next_down(); const TINY: Self = Self::from_bits(0x1); @@ -67,18 +111,48 @@ impl TestableFloat for f16 { const MUL_ADD_RESULT: Self = 62.031; const NEG_MUL_ADD_RESULT: Self = 48.625; const MAX_RECIP: Self = 1.526624e-5; + const ASINH_ACOSH_MAX: Self = 11.781; } impl TestableFloat for f32 { + const BITS: u32 = 32; type Int = u32; + type SInt = i32; const APPROX: Self = 1e-6; /// Miri adds some extra errors to float functions; make sure the tests still pass. /// These values are purely used as a canary to test against and are thus not a stable guarantee Rust provides. /// They serve as a way to get an idea of the real precision of floating point operations on different platforms. const POWI_APPROX: Self = if cfg!(miri) { 1e-4 } else { Self::APPROX }; + const POWF_APPROX: Self = if cfg!(miri) { 1e-3 } else { 1e-4 }; + const EXP_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const LN_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const LOG_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const LOG2_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const LOG10_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const ASINH_APPROX: Self = if cfg!(miri) { + 1e-3 + } else if I586 { + 1e-5 + } else { + Self::APPROX + }; + const ACOSH_APPROX: Self = if cfg!(miri) { + 1e-3 + } else if I586 { + 1e-5 + } else { + Self::APPROX + }; + const ATANH_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const GAMMA_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const GAMMA_APPROX_LOOSE: Self = if cfg!(miri) { 1e-2 } else { 1e-4 }; + const LNGAMMA_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const LNGAMMA_APPROX_LOOSE: Self = if cfg!(miri) { 1e-2 } else { 1e-4 }; const ZERO: Self = 0.0; const ONE: Self = 1.0; - const PI: Self = std::f32::consts::PI; + // We rely on NAN having an all-0 payload, so the signaling bit is the least significant + // non-0 bit, and that gets toggled by the "-1". + const SNAN: Self = Self::from_bits(Self::NAN.to_bits() - 1); const MIN_POSITIVE_NORMAL: Self = Self::MIN_POSITIVE; const MAX_SUBNORMAL: Self = Self::MIN_POSITIVE.next_down(); const TINY: Self = Self::from_bits(0x1); @@ -96,14 +170,21 @@ impl TestableFloat for f32 { const MUL_ADD_RESULT: Self = 62.05; const NEG_MUL_ADD_RESULT: Self = 48.65; const MAX_RECIP: Self = 2.938736e-39; + const ASINH_ACOSH_MAX: Self = 89.4159851; } impl TestableFloat for f64 { + const BITS: u32 = 64; type Int = u64; + type SInt = i64; const APPROX: Self = 1e-6; + const GAMMA_APPROX_LOOSE: Self = 1e-4; + const LNGAMMA_APPROX_LOOSE: Self = 1e-4; const ZERO: Self = 0.0; const ONE: Self = 1.0; - const PI: Self = std::f64::consts::PI; + // We rely on NAN having an all-0 payload, so the signaling bit is the least significant + // non-0 bit, and that gets toggled by the "-1". + const SNAN: Self = Self::from_bits(Self::NAN.to_bits() - 1); const MIN_POSITIVE_NORMAL: Self = Self::MIN_POSITIVE; const MAX_SUBNORMAL: Self = Self::MIN_POSITIVE.next_down(); const TINY: Self = Self::from_bits(0x1); @@ -121,14 +202,31 @@ impl TestableFloat for f64 { const MUL_ADD_RESULT: Self = 62.050000000000004; const NEG_MUL_ADD_RESULT: Self = 48.650000000000006; const MAX_RECIP: Self = 5.562684646268003e-309; + const ASINH_ACOSH_MAX: Self = 710.47586007394398; } impl TestableFloat for f128 { + const BITS: u32 = 128; type Int = u128; + type SInt = i128; const APPROX: Self = 1e-9; + const EXP_APPROX: Self = 1e-12; + const LN_APPROX: Self = 1e-12; + const LOG_APPROX: Self = 1e-12; + const LOG2_APPROX: Self = 1e-12; + const LOG10_APPROX: Self = 1e-12; + const ASINH_APPROX: Self = 1e-10; + const ACOSH_APPROX: Self = 1e-10; + const ATANH_APPROX: Self = 1e-10; + const GAMMA_APPROX: Self = 1e-12; + const GAMMA_APPROX_LOOSE: Self = 1e-10; + const LNGAMMA_APPROX: Self = 1e-12; + const LNGAMMA_APPROX_LOOSE: Self = 1e-10; const ZERO: Self = 0.0; const ONE: Self = 1.0; - const PI: Self = std::f128::consts::PI; + // We rely on NAN having an all-0 payload, so the signaling bit is the least significant + // non-0 bit, and that gets toggled by the "-1". + const SNAN: Self = Self::from_bits(Self::NAN.to_bits() - 1); const MIN_POSITIVE_NORMAL: Self = Self::MIN_POSITIVE; const MAX_SUBNORMAL: Self = Self::MIN_POSITIVE.next_down(); const TINY: Self = Self::from_bits(0x1); @@ -146,41 +244,41 @@ impl TestableFloat for f128 { const MUL_ADD_RESULT: Self = 62.0500000000000000000000000000000037; const NEG_MUL_ADD_RESULT: Self = 48.6500000000000000000000000000000049; const MAX_RECIP: Self = 8.40525785778023376565669454330438228902076605e-4933; + const ASINH_ACOSH_MAX: Self = 11357.216553474703894801348310092223; } /// Determine the tolerance for values of the argument type. -const fn lim_for_ty(_x: T) -> T { +pub(crate) const fn lim_for_ty(_x: T) -> T { T::APPROX } // We have runtime ("rt") and const versions of these macros. /// Verify that floats are within a tolerance of each other. -macro_rules! assert_approx_eq_rt { - ($a:expr, $b:expr) => {{ assert_approx_eq_rt!($a, $b, $crate::floats::lim_for_ty($a)) }}; +macro_rules! assert_approx_eq { + ($a:expr, $b:expr $(,)?) => {{ + assert_approx_eq!($a, $b, $crate::num::floats::lim_for_ty($a)) + }}; ($a:expr, $b:expr, $lim:expr) => {{ let (a, b) = (&$a, &$b); let diff = (*a - *b).abs(); - assert!( + core::panic::const_assert!( diff <= $lim, + "actual value is not approximately equal to expected value", "{a:?} is not approximately equal to {b:?} (threshold {lim:?}, difference {diff:?})", - lim = $lim + // We rely on the `Float` type being brought in scope by the macros below. + a: Float = *a, + b: Float = *b, + diff: Float = diff, + lim: Float = $lim, ); }}; } -macro_rules! assert_approx_eq_const { - ($a:expr, $b:expr) => {{ assert_approx_eq_const!($a, $b, $crate::floats::lim_for_ty($a)) }}; - ($a:expr, $b:expr, $lim:expr) => {{ - let (a, b) = (&$a, &$b); - let diff = (*a - *b).abs(); - assert!(diff <= $lim); - }}; -} /// Verify that floats have the same bitwise representation. Used to avoid the default `0.0 == -0.0` /// behavior, as well as to ensure exact NaN bitpatterns. -macro_rules! assert_biteq_rt { - (@inner $left:expr, $right:expr, $msg_sep:literal, $($tt:tt)*) => {{ +macro_rules! assert_biteq { + ($left:expr, $right:expr $(,)?) => {{ let l = $left; let r = $right; @@ -190,62 +288,20 @@ macro_rules! assert_biteq_rt { // Hack to get the width from a value let bits = (l.to_bits() - l.to_bits()).leading_zeros(); - assert!( + core::panic::const_assert!( l.to_bits() == r.to_bits(), - "{msg}{nl}l: {l:?} ({lb:#0width$x})\nr: {r:?} ({rb:#0width$x})", - msg = format_args!($($tt)*), - nl = $msg_sep, - lb = l.to_bits(), - rb = r.to_bits(), - width = ((bits / 4) + 2) as usize, + "actual value and expected value are not bit-equal", + "actual value and expected value are not bit-equal\n\ + l: {l:?} ({lb:#0width$x})\nr: {r:?} ({rb:#0width$x})", + // We rely on the `Float` type being brought in scope by the macros below. + l: Float = l, + r: Float = r, + lb: ::Int = l.to_bits(), + rb: ::Int = r.to_bits(), + width: usize = ((bits / 4) + 2) as usize, ); - - if !l.is_nan() && !r.is_nan() { - // Also check that standard equality holds, since most tests use `assert_biteq` rather - // than `assert_eq`. - assert_eq!(l, r); - } }}; - ($left:expr, $right:expr , $($tt:tt)*) => { - assert_biteq_rt!(@inner $left, $right, "\n", $($tt)*) - }; - ($left:expr, $right:expr $(,)?) => { - assert_biteq_rt!(@inner $left, $right, "", "") - }; } -macro_rules! assert_biteq_const { - (@inner $left:expr, $right:expr, $msg_sep:literal, $($tt:tt)*) => {{ - let l = $left; - let r = $right; - - // Hack to coerce left and right to the same type - let mut _eq_ty = l; - _eq_ty = r; - - assert!(l.to_bits() == r.to_bits()); - - if !l.is_nan() && !r.is_nan() { - // Also check that standard equality holds, since most tests use `assert_biteq` rather - // than `assert_eq`. - assert!(l == r); - } - }}; - ($left:expr, $right:expr , $($tt:tt)*) => { - assert_biteq_const!(@inner $left, $right, "\n", $($tt)*) - }; - ($left:expr, $right:expr $(,)?) => { - assert_biteq_const!(@inner $left, $right, "", "") - }; -} - -// Use the runtime version by default. -// This way, they can be shadowed by the const versions. -pub(crate) use {assert_approx_eq_rt as assert_approx_eq, assert_biteq_rt as assert_biteq}; - -// Also make the const version available for re-exports. -#[rustfmt::skip] -pub(crate) use assert_biteq_const; -pub(crate) use assert_approx_eq_const; /// Generate float tests for all our float types, for compile-time and run-time behavior. /// @@ -279,95 +335,102 @@ macro_rules! float_test { $(f128: #[ $($f128_meta:meta),+ ] ,)? $(const f128: #[ $($f128_const_meta:meta),+ ] ,)? }, - test<$fty:ident> $test:block + test $test:block ) => { mod $name { + #[allow(unused_imports)] use super::*; #[test] $( $( #[$f16_meta] )+ )? fn test_f16() { - type $fty = f16; + #[allow(unused_imports)] + use core::f16::consts; + type Float = f16; #[allow(unused)] - const fn flt (x: $fty) -> $fty { x } + const fn flt (x: Float) -> Float { x } $test } #[test] $( $( #[$f32_meta] )+ )? fn test_f32() { - type $fty = f32; + #[allow(unused_imports)] + use core::f32::consts; + type Float = f32; #[allow(unused)] - const fn flt (x: $fty) -> $fty { x } + const fn flt (x: Float) -> Float { x } $test } #[test] $( $( #[$f64_meta] )+ )? fn test_f64() { - type $fty = f64; + #[allow(unused_imports)] + use core::f64::consts; + type Float = f64; #[allow(unused)] - const fn flt (x: $fty) -> $fty { x } + const fn flt (x: Float) -> Float { x } $test } #[test] $( $( #[$f128_meta] )+ )? fn test_f128() { - type $fty = f128; + #[allow(unused_imports)] + use core::f128::consts; + type Float = f128; #[allow(unused)] - const fn flt (x: $fty) -> $fty { x } + const fn flt (x: Float) -> Float { x } $test } $( $( #[$const_meta] )+ )? mod const_ { - #[allow(unused)] - use super::TestableFloat; - #[allow(unused)] - use std::num::FpCategory as Fp; - #[allow(unused)] - use std::ops::{Add, Div, Mul, Rem, Sub}; - // Shadow the runtime versions of the macro with const-compatible versions. - #[allow(unused)] - use $crate::floats::{ - assert_approx_eq_const as assert_approx_eq, - assert_biteq_const as assert_biteq, - }; + #[allow(unused_imports)] + use super::*; #[test] $( $( #[$f16_const_meta] )+ )? fn test_f16() { - type $fty = f16; + #[allow(unused_imports)] + use core::f16::consts; + type Float = f16; #[allow(unused)] - const fn flt (x: $fty) -> $fty { x } + const fn flt (x: Float) -> Float { x } const { $test } } #[test] $( $( #[$f32_const_meta] )+ )? fn test_f32() { - type $fty = f32; + #[allow(unused_imports)] + use core::f32::consts; + type Float = f32; #[allow(unused)] - const fn flt (x: $fty) -> $fty { x } + const fn flt (x: Float) -> Float { x } const { $test } } #[test] $( $( #[$f64_const_meta] )+ )? fn test_f64() { - type $fty = f64; + #[allow(unused_imports)] + use core::f64::consts; + type Float = f64; #[allow(unused)] - const fn flt (x: $fty) -> $fty { x } + const fn flt (x: Float) -> Float { x } const { $test } } #[test] $( $( #[$f128_const_meta] )+ )? fn test_f128() { - type $fty = f128; + #[allow(unused_imports)] + use core::f128::consts; + type Float = f128; #[allow(unused)] - const fn flt (x: $fty) -> $fty { x } + const fn flt (x: Float) -> Float { x } const { $test } } } @@ -375,13 +438,16 @@ macro_rules! float_test { }; } +pub(crate) use assert_biteq; +pub(crate) use float_test; + float_test! { name: num, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, - test { + test { let two: Float = 2.0; let ten: Float = 10.0; assert_biteq!(ten.add(two), ten + two); @@ -396,10 +462,11 @@ float_test! { float_test! { name: num_rem, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { + test { let two: Float = 2.0; let ten: Float = 10.0; assert_biteq!(ten.rem(two), ten % two); @@ -409,10 +476,10 @@ float_test! { float_test! { name: nan, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, - test { + test { let nan: Float = Float::NAN; assert!(nan.is_nan()); assert!(!nan.is_infinite()); @@ -429,10 +496,10 @@ float_test! { float_test! { name: infinity, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, - test { + test { let inf: Float = Float::INFINITY; assert!(inf.is_infinite()); assert!(!inf.is_finite()); @@ -447,10 +514,10 @@ float_test! { float_test! { name: neg_infinity, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, - test { + test { let neg_inf: Float = Float::NEG_INFINITY; assert!(neg_inf.is_infinite()); assert!(!neg_inf.is_finite()); @@ -465,10 +532,10 @@ float_test! { float_test! { name: zero, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, - test { + test { assert_biteq!(0.0, Float::ZERO); assert!(!Float::ZERO.is_infinite()); assert!(Float::ZERO.is_finite()); @@ -483,10 +550,10 @@ float_test! { float_test! { name: neg_zero, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, - test { + test { let neg_zero: Float = -0.0; assert!(0.0 == neg_zero); assert_biteq!(-0.0, neg_zero); @@ -503,10 +570,10 @@ float_test! { float_test! { name: one, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, - test { + test { assert_biteq!(1.0, Float::ONE); assert!(!Float::ONE.is_infinite()); assert!(Float::ONE.is_finite()); @@ -521,10 +588,10 @@ float_test! { float_test! { name: is_nan, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, - test { + test { let nan: Float = Float::NAN; let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; @@ -542,10 +609,10 @@ float_test! { float_test! { name: is_infinite, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, - test { + test { let nan: Float = Float::NAN; let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; @@ -563,10 +630,10 @@ float_test! { float_test! { name: is_finite, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, - test { + test { let nan: Float = Float::NAN; let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; @@ -584,10 +651,10 @@ float_test! { float_test! { name: is_normal, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, - test { + test { let nan: Float = Float::NAN; let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; @@ -606,9 +673,9 @@ float_test! { float_test! { name: classify, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], + f16: #[cfg(target_has_reliable_f16)], }, - test { + test { let nan: Float = Float::NAN; let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; @@ -627,91 +694,116 @@ float_test! { float_test! { name: min, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((0.0 as Float).min(0.0), 0.0); - assert_biteq!((-0.0 as Float).min(-0.0), -0.0); - assert_biteq!((9.0 as Float).min(9.0), 9.0); - assert_biteq!((-9.0 as Float).min(0.0), -9.0); - assert_biteq!((0.0 as Float).min(9.0), 0.0); - assert_biteq!((-0.0 as Float).min(9.0), -0.0); - assert_biteq!((-0.0 as Float).min(-9.0), -9.0); + test { + assert_biteq!(flt(0.0).min(0.0), 0.0); + assert_biteq!(flt(-0.0).min(-0.0), -0.0); + assert_biteq!(flt(9.0).min(9.0), 9.0); + assert_biteq!(flt(-9.0).min(0.0), -9.0); + assert_biteq!(flt(0.0).min(9.0), 0.0); + assert_biteq!(flt(-0.0).min(9.0), -0.0); + assert_biteq!(flt(-0.0).min(-9.0), -9.0); assert_biteq!(Float::INFINITY.min(9.0), 9.0); - assert_biteq!((9.0 as Float).min(Float::INFINITY), 9.0); + assert_biteq!(flt(9.0).min(Float::INFINITY), 9.0); assert_biteq!(Float::INFINITY.min(-9.0), -9.0); - assert_biteq!((-9.0 as Float).min(Float::INFINITY), -9.0); + assert_biteq!(flt(-9.0).min(Float::INFINITY), -9.0); assert_biteq!(Float::NEG_INFINITY.min(9.0), Float::NEG_INFINITY); - assert_biteq!((9.0 as Float).min(Float::NEG_INFINITY), Float::NEG_INFINITY); + assert_biteq!(flt(9.0).min(Float::NEG_INFINITY), Float::NEG_INFINITY); assert_biteq!(Float::NEG_INFINITY.min(-9.0), Float::NEG_INFINITY); - assert_biteq!((-9.0 as Float).min(Float::NEG_INFINITY), Float::NEG_INFINITY); - assert_biteq!(Float::NAN.min(9.0), 9.0); - assert_biteq!(Float::NAN.min(-9.0), -9.0); - assert_biteq!((9.0 as Float).min(Float::NAN), 9.0); - assert_biteq!((-9.0 as Float).min(Float::NAN), -9.0); + assert_biteq!(flt(-9.0).min(Float::NEG_INFINITY), Float::NEG_INFINITY); + // We add black_box for the NAN tests as that used to be able to trigger miscompilations. + assert_biteq!(Float::NAN.min(black_box(9.0)), 9.0); + assert_biteq!(black_box(Float::NAN).min(-9.0), -9.0); + assert_biteq!(flt(9.0).min(black_box(Float::NAN)), 9.0); + assert_biteq!(black_box(flt(-9.0)).min(Float::NAN), -9.0); assert!(Float::NAN.min(Float::NAN).is_nan()); + // FIXME(llvm21): LLVM miscompiles the fallback impl on aarch64 and likely other targets + // (https://github.com/llvm/llvm-project/issues/176624). When we require LLVM 22, + // remove the ui test `tests/ui/float/minmax.rs` and unconditionally enable the test here. + if cfg!(miri) { + assert_biteq!(Float::SNAN.min(black_box(9.0)), 9.0); + assert_biteq!(black_box(Float::SNAN).min(-9.0), -9.0); + assert_biteq!(flt(9.0).min(black_box(Float::SNAN)), 9.0); + assert_biteq!(black_box(flt(-9.0)).min(Float::SNAN), -9.0); + } + assert!(Float::SNAN.min(Float::SNAN).is_nan()); } } float_test! { name: max, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((0.0 as Float).max(0.0), 0.0); - assert_biteq!((-0.0 as Float).max(-0.0), -0.0); - assert_biteq!((9.0 as Float).max(9.0), 9.0); - assert_biteq!((-9.0 as Float).max(0.0), 0.0); - assert_biteq!((-9.0 as Float).max(-0.0), -0.0); - assert_biteq!((0.0 as Float).max(9.0), 9.0); - assert_biteq!((0.0 as Float).max(-9.0), 0.0); - assert_biteq!((-0.0 as Float).max(-9.0), -0.0); + test { + assert_biteq!(flt(0.0).max(0.0), 0.0); + assert_biteq!(flt(-0.0).max(-0.0), -0.0); + assert_biteq!(flt(9.0).max(9.0), 9.0); + assert_biteq!(flt(-9.0).max(0.0), 0.0); + assert_biteq!(flt(-9.0).max(-0.0), -0.0); + assert_biteq!(flt(0.0).max(9.0), 9.0); + assert_biteq!(flt(0.0).max(-9.0), 0.0); + assert_biteq!(flt(-0.0).max(-9.0), -0.0); assert_biteq!(Float::INFINITY.max(9.0), Float::INFINITY); - assert_biteq!((9.0 as Float).max(Float::INFINITY), Float::INFINITY); + assert_biteq!(flt(9.0).max(Float::INFINITY), Float::INFINITY); assert_biteq!(Float::INFINITY.max(-9.0), Float::INFINITY); - assert_biteq!((-9.0 as Float).max(Float::INFINITY), Float::INFINITY); + assert_biteq!(flt(-9.0).max(Float::INFINITY), Float::INFINITY); assert_biteq!(Float::NEG_INFINITY.max(9.0), 9.0); - assert_biteq!((9.0 as Float).max(Float::NEG_INFINITY), 9.0); + assert_biteq!(flt(9.0).max(Float::NEG_INFINITY), 9.0); assert_biteq!(Float::NEG_INFINITY.max(-9.0), -9.0); - assert_biteq!((-9.0 as Float).max(Float::NEG_INFINITY), -9.0); - assert_biteq!(Float::NAN.max(9.0), 9.0); - assert_biteq!(Float::NAN.max(-9.0), -9.0); - assert_biteq!((9.0 as Float).max(Float::NAN), 9.0); - assert_biteq!((-9.0 as Float).max(Float::NAN), -9.0); + assert_biteq!(flt(-9.0).max(Float::NEG_INFINITY), -9.0); + // We add black_box for the NAN tests as that used to be able to trigger miscompilations. + assert_biteq!(Float::NAN.max(black_box(9.0)), 9.0); + assert_biteq!(black_box(Float::NAN).max(-9.0), -9.0); + assert_biteq!(flt(9.0).max(black_box(Float::NAN)), 9.0); + assert_biteq!(black_box(flt(-9.0)).max(Float::NAN), -9.0); assert!(Float::NAN.max(Float::NAN).is_nan()); + // FIXME(llvm21): LLVM miscompiles the fallback impl on aarch64 and likely other targets + // (https://github.com/llvm/llvm-project/issues/176624). When we require LLVM 22, + // remove the ui test `tests/ui/float/minmax.rs` and unconditionally enable the test here. + if cfg!(miri) { + assert_biteq!(Float::SNAN.max(black_box(9.0)), 9.0); + assert_biteq!(black_box(Float::SNAN).max(-9.0), -9.0); + assert_biteq!(flt(9.0).max(black_box(Float::SNAN)), 9.0); + assert_biteq!(black_box(flt(-9.0)).max(Float::SNAN), -9.0); + } + assert!(Float::SNAN.max(Float::SNAN).is_nan()); } } float_test! { name: minimum, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((0.0 as Float).minimum(0.0), 0.0); - assert_biteq!((-0.0 as Float).minimum(0.0), -0.0); - assert_biteq!((-0.0 as Float).minimum(-0.0), -0.0); - assert_biteq!((9.0 as Float).minimum(9.0), 9.0); - assert_biteq!((-9.0 as Float).minimum(0.0), -9.0); - assert_biteq!((0.0 as Float).minimum(9.0), 0.0); - assert_biteq!((-0.0 as Float).minimum(9.0), -0.0); - assert_biteq!((-0.0 as Float).minimum(-9.0), -9.0); + test { + assert_biteq!(flt(0.0).minimum(0.0), 0.0); + assert_biteq!(flt(-0.0).minimum(0.0), -0.0); + assert_biteq!(flt(-0.0).minimum(-0.0), -0.0); + assert_biteq!(flt(9.0).minimum(9.0), 9.0); + assert_biteq!(flt(-9.0).minimum(0.0), -9.0); + assert_biteq!(flt(0.0).minimum(9.0), 0.0); + assert_biteq!(flt(-0.0).minimum(9.0), -0.0); + assert_biteq!(flt(-0.0).minimum(-9.0), -9.0); assert_biteq!(Float::INFINITY.minimum(9.0), 9.0); - assert_biteq!((9.0 as Float).minimum(Float::INFINITY), 9.0); + assert_biteq!(flt(9.0).minimum(Float::INFINITY), 9.0); assert_biteq!(Float::INFINITY.minimum(-9.0), -9.0); - assert_biteq!((-9.0 as Float).minimum(Float::INFINITY), -9.0); + assert_biteq!(flt(-9.0).minimum(Float::INFINITY), -9.0); assert_biteq!(Float::NEG_INFINITY.minimum(9.0), Float::NEG_INFINITY); - assert_biteq!((9.0 as Float).minimum(Float::NEG_INFINITY), Float::NEG_INFINITY); + assert_biteq!(flt(9.0).minimum(Float::NEG_INFINITY), Float::NEG_INFINITY); assert_biteq!(Float::NEG_INFINITY.minimum(-9.0), Float::NEG_INFINITY); - assert_biteq!((-9.0 as Float).minimum(Float::NEG_INFINITY), Float::NEG_INFINITY); + assert_biteq!(flt(-9.0).minimum(Float::NEG_INFINITY), Float::NEG_INFINITY); assert!(Float::NAN.minimum(9.0).is_nan()); assert!(Float::NAN.minimum(-9.0).is_nan()); - assert!((9.0 as Float).minimum(Float::NAN).is_nan()); - assert!((-9.0 as Float).minimum(Float::NAN).is_nan()); + assert!(flt(9.0).minimum(Float::NAN).is_nan()); + assert!(flt(-9.0).minimum(Float::NAN).is_nan()); assert!(Float::NAN.minimum(Float::NAN).is_nan()); } } @@ -719,31 +811,32 @@ float_test! { float_test! { name: maximum, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((0.0 as Float).maximum(0.0), 0.0); - assert_biteq!((-0.0 as Float).maximum(0.0), 0.0); - assert_biteq!((-0.0 as Float).maximum(-0.0), -0.0); - assert_biteq!((9.0 as Float).maximum(9.0), 9.0); - assert_biteq!((-9.0 as Float).maximum(0.0), 0.0); - assert_biteq!((-9.0 as Float).maximum(-0.0), -0.0); - assert_biteq!((0.0 as Float).maximum(9.0), 9.0); - assert_biteq!((0.0 as Float).maximum(-9.0), 0.0); - assert_biteq!((-0.0 as Float).maximum(-9.0), -0.0); + test { + assert_biteq!(flt(0.0).maximum(0.0), 0.0); + assert_biteq!(flt(-0.0).maximum(0.0), 0.0); + assert_biteq!(flt(-0.0).maximum(-0.0), -0.0); + assert_biteq!(flt(9.0).maximum(9.0), 9.0); + assert_biteq!(flt(-9.0).maximum(0.0), 0.0); + assert_biteq!(flt(-9.0).maximum(-0.0), -0.0); + assert_biteq!(flt(0.0).maximum(9.0), 9.0); + assert_biteq!(flt(0.0).maximum(-9.0), 0.0); + assert_biteq!(flt(-0.0).maximum(-9.0), -0.0); assert_biteq!(Float::INFINITY.maximum(9.0), Float::INFINITY); - assert_biteq!((9.0 as Float).maximum(Float::INFINITY), Float::INFINITY); + assert_biteq!(flt(9.0).maximum(Float::INFINITY), Float::INFINITY); assert_biteq!(Float::INFINITY.maximum(-9.0), Float::INFINITY); - assert_biteq!((-9.0 as Float).maximum(Float::INFINITY), Float::INFINITY); + assert_biteq!(flt(-9.0).maximum(Float::INFINITY), Float::INFINITY); assert_biteq!(Float::NEG_INFINITY.maximum(9.0), 9.0); - assert_biteq!((9.0 as Float).maximum(Float::NEG_INFINITY), 9.0); + assert_biteq!(flt(9.0).maximum(Float::NEG_INFINITY), 9.0); assert_biteq!(Float::NEG_INFINITY.maximum(-9.0), -9.0); - assert_biteq!((-9.0 as Float).maximum(Float::NEG_INFINITY), -9.0); + assert_biteq!(flt(-9.0).maximum(Float::NEG_INFINITY), -9.0); assert!(Float::NAN.maximum(9.0).is_nan()); assert!(Float::NAN.maximum(-9.0).is_nan()); - assert!((9.0 as Float).maximum(Float::NAN).is_nan()); - assert!((-9.0 as Float).maximum(Float::NAN).is_nan()); + assert!(flt(9.0).maximum(Float::NAN).is_nan()); + assert!(flt(-9.0).maximum(Float::NAN).is_nan()); assert!(Float::NAN.maximum(Float::NAN).is_nan()); } } @@ -751,19 +844,20 @@ float_test! { float_test! { name: midpoint, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((0.5 as Float).midpoint(0.5), 0.5); - assert_biteq!((0.5 as Float).midpoint(2.5), 1.5); - assert_biteq!((3.0 as Float).midpoint(4.0), 3.5); - assert_biteq!((-3.0 as Float).midpoint(4.0), 0.5); - assert_biteq!((3.0 as Float).midpoint(-4.0), -0.5); - assert_biteq!((-3.0 as Float).midpoint(-4.0), -3.5); - assert_biteq!((0.0 as Float).midpoint(0.0), 0.0); - assert_biteq!((-0.0 as Float).midpoint(-0.0), -0.0); - assert_biteq!((-5.0 as Float).midpoint(5.0), 0.0); + test { + assert_biteq!(flt(0.5).midpoint(0.5), 0.5); + assert_biteq!(flt(0.5).midpoint(2.5), 1.5); + assert_biteq!(flt(3.0).midpoint(4.0), 3.5); + assert_biteq!(flt(-3.0).midpoint(4.0), 0.5); + assert_biteq!(flt(3.0).midpoint(-4.0), -0.5); + assert_biteq!(flt(-3.0).midpoint(-4.0), -3.5); + assert_biteq!(flt(0.0).midpoint(0.0), 0.0); + assert_biteq!(flt(-0.0).midpoint(-0.0), -0.0); + assert_biteq!(flt(-5.0).midpoint(5.0), 0.0); assert_biteq!(Float::MAX.midpoint(Float::MIN), 0.0); assert_biteq!(Float::MIN.midpoint(Float::MAX), 0.0); assert_biteq!(Float::MAX.midpoint(Float::MIN_POSITIVE), Float::MAX / 2.); @@ -793,7 +887,7 @@ float_test! { assert!(Float::NEG_INFINITY.midpoint(Float::INFINITY).is_nan()); assert!(Float::INFINITY.midpoint(Float::NEG_INFINITY).is_nan()); assert!(Float::NAN.midpoint(1.0).is_nan()); - assert!((1.0 as Float).midpoint(Float::NAN).is_nan()); + assert!(flt(1.0).midpoint(Float::NAN).is_nan()); assert!(Float::NAN.midpoint(Float::NAN).is_nan()); } } @@ -803,11 +897,11 @@ float_test! { name: midpoint_large_magnitude, attrs: { const: #[cfg(false)], - // FIXME(f16_f128): `powi` does not work in Miri for these types - f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], - f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + // Needs powi + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], }, - test { + test { // test if large differences in magnitude are still correctly computed. // NOTE: that because of how small x and y are, x + y can never overflow // so (x + y) / 2.0 is always correct @@ -815,10 +909,10 @@ float_test! { // be safely doubled, while j is significantly smaller. for i in Float::MAX_EXP.saturating_sub(64)..Float::MAX_EXP { for j in 0..64u8 { - let large = (2.0 as Float).powi(i); + let large = flt(2.0).powi(i); // a much smaller number, such that there is no chance of overflow to test // potential double rounding in midpoint's implementation. - let small = (2.0 as Float).powi(Float::MAX_EXP - 1) + let small = flt(2.0).powi(Float::MAX_EXP - 1) * Float::EPSILON * Float::from(j); @@ -834,10 +928,11 @@ float_test! { float_test! { name: abs, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { + test { assert_biteq!(Float::INFINITY.abs(), Float::INFINITY); assert_biteq!(Float::ONE.abs(), Float::ONE); assert_biteq!(Float::ZERO.abs(), Float::ZERO); @@ -852,12 +947,13 @@ float_test! { float_test! { name: copysign, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((1.0 as Float).copysign(-2.0), -1.0); - assert_biteq!((-1.0 as Float).copysign(2.0), 1.0); + test { + assert_biteq!(flt(1.0).copysign(-2.0), -1.0); + assert_biteq!(flt(-1.0).copysign(2.0), 1.0); assert_biteq!(Float::INFINITY.copysign(-0.0), Float::NEG_INFINITY); assert_biteq!(Float::NEG_INFINITY.copysign(0.0), Float::INFINITY); } @@ -867,13 +963,14 @@ float_test! { name: rem_euclid, attrs: { const: #[cfg(false)], + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert!(Float::INFINITY.rem_euclid(42.0 as Float).is_nan()); - assert_biteq!((42.0 as Float).rem_euclid(Float::INFINITY), 42.0 as Float); - assert!((42.0 as Float).rem_euclid(Float::NAN).is_nan()); + test { + assert!(Float::INFINITY.rem_euclid(42.0).is_nan()); + assert_biteq!(flt(42.0).rem_euclid(Float::INFINITY), 42.0); + assert!(flt(42.0).rem_euclid(Float::NAN).is_nan()); assert!(Float::INFINITY.rem_euclid(Float::INFINITY).is_nan()); assert!(Float::INFINITY.rem_euclid(Float::NAN).is_nan()); assert!(Float::NAN.rem_euclid(Float::INFINITY).is_nan()); @@ -884,12 +981,13 @@ float_test! { name: div_euclid, attrs: { const: #[cfg(false)], + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((42.0 as Float).div_euclid(Float::INFINITY), 0.0); - assert!((42.0 as Float).div_euclid(Float::NAN).is_nan()); + test { + assert_biteq!(flt(42.0).div_euclid(Float::INFINITY), 0.0); + assert!(flt(42.0).div_euclid(Float::NAN).is_nan()); assert!(Float::INFINITY.div_euclid(Float::INFINITY).is_nan()); assert!(Float::INFINITY.div_euclid(Float::NAN).is_nan()); assert!(Float::NAN.div_euclid(Float::INFINITY).is_nan()); @@ -899,22 +997,23 @@ float_test! { float_test! { name: floor, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((1.0 as Float).floor(), 1.0); - assert_biteq!((1.3 as Float).floor(), 1.0); - assert_biteq!((1.5 as Float).floor(), 1.0); - assert_biteq!((1.7 as Float).floor(), 1.0); - assert_biteq!((0.5 as Float).floor(), 0.0); - assert_biteq!((0.0 as Float).floor(), 0.0); - assert_biteq!((-0.0 as Float).floor(), -0.0); - assert_biteq!((-0.5 as Float).floor(), -1.0); - assert_biteq!((-1.0 as Float).floor(), -1.0); - assert_biteq!((-1.3 as Float).floor(), -2.0); - assert_biteq!((-1.5 as Float).floor(), -2.0); - assert_biteq!((-1.7 as Float).floor(), -2.0); + test { + assert_biteq!(flt(1.0).floor(), 1.0); + assert_biteq!(flt(1.3).floor(), 1.0); + assert_biteq!(flt(1.5).floor(), 1.0); + assert_biteq!(flt(1.7).floor(), 1.0); + assert_biteq!(flt(0.5).floor(), 0.0); + assert_biteq!(flt(0.0).floor(), 0.0); + assert_biteq!(flt(-0.0).floor(), -0.0); + assert_biteq!(flt(-0.5).floor(), -1.0); + assert_biteq!(flt(-1.0).floor(), -1.0); + assert_biteq!(flt(-1.3).floor(), -2.0); + assert_biteq!(flt(-1.5).floor(), -2.0); + assert_biteq!(flt(-1.7).floor(), -2.0); assert_biteq!(Float::MAX.floor(), Float::MAX); assert_biteq!(Float::MIN.floor(), Float::MIN); assert_biteq!(Float::MIN_POSITIVE.floor(), 0.0); @@ -928,22 +1027,23 @@ float_test! { float_test! { name: ceil, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((1.0 as Float).ceil(), 1.0); - assert_biteq!((1.3 as Float).ceil(), 2.0); - assert_biteq!((1.5 as Float).ceil(), 2.0); - assert_biteq!((1.7 as Float).ceil(), 2.0); - assert_biteq!((0.5 as Float).ceil(), 1.0); - assert_biteq!((0.0 as Float).ceil(), 0.0); - assert_biteq!((-0.0 as Float).ceil(), -0.0); - assert_biteq!((-0.5 as Float).ceil(), -0.0); - assert_biteq!((-1.0 as Float).ceil(), -1.0); - assert_biteq!((-1.3 as Float).ceil(), -1.0); - assert_biteq!((-1.5 as Float).ceil(), -1.0); - assert_biteq!((-1.7 as Float).ceil(), -1.0); + test { + assert_biteq!(flt(1.0).ceil(), 1.0); + assert_biteq!(flt(1.3).ceil(), 2.0); + assert_biteq!(flt(1.5).ceil(), 2.0); + assert_biteq!(flt(1.7).ceil(), 2.0); + assert_biteq!(flt(0.5).ceil(), 1.0); + assert_biteq!(flt(0.0).ceil(), 0.0); + assert_biteq!(flt(-0.0).ceil(), -0.0); + assert_biteq!(flt(-0.5).ceil(), -0.0); + assert_biteq!(flt(-1.0).ceil(), -1.0); + assert_biteq!(flt(-1.3).ceil(), -1.0); + assert_biteq!(flt(-1.5).ceil(), -1.0); + assert_biteq!(flt(-1.7).ceil(), -1.0); assert_biteq!(Float::MAX.ceil(), Float::MAX); assert_biteq!(Float::MIN.ceil(), Float::MIN); assert_biteq!(Float::MIN_POSITIVE.ceil(), 1.0); @@ -957,23 +1057,24 @@ float_test! { float_test! { name: round, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((2.5 as Float).round(), 3.0); - assert_biteq!((1.0 as Float).round(), 1.0); - assert_biteq!((1.3 as Float).round(), 1.0); - assert_biteq!((1.5 as Float).round(), 2.0); - assert_biteq!((1.7 as Float).round(), 2.0); - assert_biteq!((0.5 as Float).round(), 1.0); - assert_biteq!((0.0 as Float).round(), 0.0); - assert_biteq!((-0.0 as Float).round(), -0.0); - assert_biteq!((-0.5 as Float).round(), -1.0); - assert_biteq!((-1.0 as Float).round(), -1.0); - assert_biteq!((-1.3 as Float).round(), -1.0); - assert_biteq!((-1.5 as Float).round(), -2.0); - assert_biteq!((-1.7 as Float).round(), -2.0); + test { + assert_biteq!(flt(2.5).round(), 3.0); + assert_biteq!(flt(1.0).round(), 1.0); + assert_biteq!(flt(1.3).round(), 1.0); + assert_biteq!(flt(1.5).round(), 2.0); + assert_biteq!(flt(1.7).round(), 2.0); + assert_biteq!(flt(0.5).round(), 1.0); + assert_biteq!(flt(0.0).round(), 0.0); + assert_biteq!(flt(-0.0).round(), -0.0); + assert_biteq!(flt(-0.5).round(), -1.0); + assert_biteq!(flt(-1.0).round(), -1.0); + assert_biteq!(flt(-1.3).round(), -1.0); + assert_biteq!(flt(-1.5).round(), -2.0); + assert_biteq!(flt(-1.7).round(), -2.0); assert_biteq!(Float::MAX.round(), Float::MAX); assert_biteq!(Float::MIN.round(), Float::MIN); assert_biteq!(Float::MIN_POSITIVE.round(), 0.0); @@ -987,23 +1088,24 @@ float_test! { float_test! { name: round_ties_even, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((2.5 as Float).round_ties_even(), 2.0); - assert_biteq!((1.0 as Float).round_ties_even(), 1.0); - assert_biteq!((1.3 as Float).round_ties_even(), 1.0); - assert_biteq!((1.5 as Float).round_ties_even(), 2.0); - assert_biteq!((1.7 as Float).round_ties_even(), 2.0); - assert_biteq!((0.5 as Float).round_ties_even(), 0.0); - assert_biteq!((0.0 as Float).round_ties_even(), 0.0); - assert_biteq!((-0.0 as Float).round_ties_even(), -0.0); - assert_biteq!((-0.5 as Float).round_ties_even(), -0.0); - assert_biteq!((-1.0 as Float).round_ties_even(), -1.0); - assert_biteq!((-1.3 as Float).round_ties_even(), -1.0); - assert_biteq!((-1.5 as Float).round_ties_even(), -2.0); - assert_biteq!((-1.7 as Float).round_ties_even(), -2.0); + test { + assert_biteq!(flt(2.5).round_ties_even(), 2.0); + assert_biteq!(flt(1.0).round_ties_even(), 1.0); + assert_biteq!(flt(1.3).round_ties_even(), 1.0); + assert_biteq!(flt(1.5).round_ties_even(), 2.0); + assert_biteq!(flt(1.7).round_ties_even(), 2.0); + assert_biteq!(flt(0.5).round_ties_even(), 0.0); + assert_biteq!(flt(0.0).round_ties_even(), 0.0); + assert_biteq!(flt(-0.0).round_ties_even(), -0.0); + assert_biteq!(flt(-0.5).round_ties_even(), -0.0); + assert_biteq!(flt(-1.0).round_ties_even(), -1.0); + assert_biteq!(flt(-1.3).round_ties_even(), -1.0); + assert_biteq!(flt(-1.5).round_ties_even(), -2.0); + assert_biteq!(flt(-1.7).round_ties_even(), -2.0); assert_biteq!(Float::MAX.round_ties_even(), Float::MAX); assert_biteq!(Float::MIN.round_ties_even(), Float::MIN); assert_biteq!(Float::MIN_POSITIVE.round_ties_even(), 0.0); @@ -1017,22 +1119,23 @@ float_test! { float_test! { name: trunc, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((1.0 as Float).trunc(), 1.0); - assert_biteq!((1.3 as Float).trunc(), 1.0); - assert_biteq!((1.5 as Float).trunc(), 1.0); - assert_biteq!((1.7 as Float).trunc(), 1.0); - assert_biteq!((0.5 as Float).trunc(), 0.0); - assert_biteq!((0.0 as Float).trunc(), 0.0); - assert_biteq!((-0.0 as Float).trunc(), -0.0); - assert_biteq!((-0.5 as Float).trunc(), -0.0); - assert_biteq!((-1.0 as Float).trunc(), -1.0); - assert_biteq!((-1.3 as Float).trunc(), -1.0); - assert_biteq!((-1.5 as Float).trunc(), -1.0); - assert_biteq!((-1.7 as Float).trunc(), -1.0); + test { + assert_biteq!(flt(1.0).trunc(), 1.0); + assert_biteq!(flt(1.3).trunc(), 1.0); + assert_biteq!(flt(1.5).trunc(), 1.0); + assert_biteq!(flt(1.7).trunc(), 1.0); + assert_biteq!(flt(0.5).trunc(), 0.0); + assert_biteq!(flt(0.0).trunc(), 0.0); + assert_biteq!(flt(-0.0).trunc(), -0.0); + assert_biteq!(flt(-0.5).trunc(), -0.0); + assert_biteq!(flt(-1.0).trunc(), -1.0); + assert_biteq!(flt(-1.3).trunc(), -1.0); + assert_biteq!(flt(-1.5).trunc(), -1.0); + assert_biteq!(flt(-1.7).trunc(), -1.0); assert_biteq!(Float::MAX.trunc(), Float::MAX); assert_biteq!(Float::MIN.trunc(), Float::MIN); assert_biteq!(Float::MIN_POSITIVE.trunc(), 0.0); @@ -1046,22 +1149,23 @@ float_test! { float_test! { name: fract, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((1.0 as Float).fract(), 0.0); - assert_approx_eq!((1.3 as Float).fract(), 0.3); // rounding differs between float types - assert_biteq!((1.5 as Float).fract(), 0.5); - assert_approx_eq!((1.7 as Float).fract(), 0.7); - assert_biteq!((0.5 as Float).fract(), 0.5); - assert_biteq!((0.0 as Float).fract(), 0.0); - assert_biteq!((-0.0 as Float).fract(), 0.0); - assert_biteq!((-0.5 as Float).fract(), -0.5); - assert_biteq!((-1.0 as Float).fract(), 0.0); - assert_approx_eq!((-1.3 as Float).fract(), -0.3); // rounding differs between float types - assert_biteq!((-1.5 as Float).fract(), -0.5); - assert_approx_eq!((-1.7 as Float).fract(), -0.7); + test { + assert_biteq!(flt(1.0).fract(), 0.0); + assert_approx_eq!(flt(1.3).fract(), 0.3); // rounding differs between float types + assert_biteq!(flt(1.5).fract(), 0.5); + assert_approx_eq!(flt(1.7).fract(), 0.7); + assert_biteq!(flt(0.5).fract(), 0.5); + assert_biteq!(flt(0.0).fract(), 0.0); + assert_biteq!(flt(-0.0).fract(), 0.0); + assert_biteq!(flt(-0.5).fract(), -0.5); + assert_biteq!(flt(-1.0).fract(), 0.0); + assert_approx_eq!(flt(-1.3).fract(), -0.3); // rounding differs between float types + assert_biteq!(flt(-1.5).fract(), -0.5); + assert_approx_eq!(flt(-1.7).fract(), -0.7); assert_biteq!(Float::MAX.fract(), 0.0); assert_biteq!(Float::MIN.fract(), 0.0); assert_biteq!(Float::MIN_POSITIVE.fract(), Float::MIN_POSITIVE); @@ -1077,10 +1181,11 @@ float_test! { float_test! { name: signum, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { + test { assert_biteq!(Float::INFINITY.signum(), Float::ONE); assert_biteq!(Float::ONE.signum(), Float::ONE); assert_biteq!(Float::ZERO.signum(), Float::ONE); @@ -1095,10 +1200,10 @@ float_test! { float_test! { name: is_sign_positive, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, - test { + test { assert!(Float::INFINITY.is_sign_positive()); assert!(Float::ONE.is_sign_positive()); assert!(Float::ZERO.is_sign_positive()); @@ -1114,10 +1219,10 @@ float_test! { float_test! { name: is_sign_negative, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, - test { + test { assert!(!Float::INFINITY.is_sign_negative()); assert!(!Float::ONE.is_sign_negative()); assert!(!Float::ZERO.is_sign_negative()); @@ -1133,10 +1238,10 @@ float_test! { float_test! { name: next_up, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, - test { + test { assert_biteq!(Float::NEG_INFINITY.next_up(), Float::MIN); assert_biteq!(Float::MIN.next_up(), -Float::MAX_DOWN); assert_biteq!((-Float::ONE - Float::EPSILON).next_up(), -Float::ONE); @@ -1164,10 +1269,10 @@ float_test! { float_test! { name: next_down, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, - test { + test { assert_biteq!(Float::NEG_INFINITY.next_down(), Float::NEG_INFINITY); assert_biteq!(Float::MIN.next_down(), Float::NEG_INFINITY); assert_biteq!((-Float::MAX_DOWN).next_down(), Float::MIN); @@ -1197,10 +1302,11 @@ float_test! { name: sqrt_domain, attrs: { const: #[cfg(false)], + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { + test { assert!(Float::NAN.sqrt().is_nan()); assert!(Float::NEG_INFINITY.sqrt().is_nan()); assert!((-Float::ONE).sqrt().is_nan()); @@ -1215,12 +1321,12 @@ float_test! { name: clamp_min_greater_than_max, attrs: { const: #[cfg(false)], - f16: #[should_panic, cfg(any(miri, target_has_reliable_f16))], + f16: #[should_panic, cfg(target_has_reliable_f16)], f32: #[should_panic], f64: #[should_panic], - f128: #[should_panic, cfg(any(miri, target_has_reliable_f128))], + f128: #[should_panic, cfg(target_has_reliable_f128)], }, - test { + test { let _ = Float::ONE.clamp(3.0, 1.0); } } @@ -1229,12 +1335,12 @@ float_test! { name: clamp_min_is_nan, attrs: { const: #[cfg(false)], - f16: #[should_panic, cfg(any(miri, target_has_reliable_f16))], + f16: #[should_panic, cfg(target_has_reliable_f16)], f32: #[should_panic], f64: #[should_panic], - f128: #[should_panic, cfg(any(miri, target_has_reliable_f128))], + f128: #[should_panic, cfg(target_has_reliable_f128)], }, - test { + test { let _ = Float::ONE.clamp(Float::NAN, 1.0); } } @@ -1243,12 +1349,12 @@ float_test! { name: clamp_max_is_nan, attrs: { const: #[cfg(false)], - f16: #[should_panic, cfg(any(miri, target_has_reliable_f16))], + f16: #[should_panic, cfg(target_has_reliable_f16)], f32: #[should_panic], f64: #[should_panic], - f128: #[should_panic, cfg(any(miri, target_has_reliable_f128))], + f128: #[should_panic, cfg(target_has_reliable_f128)], }, - test { + test { let _ = Float::ONE.clamp(3.0, Float::NAN); } } @@ -1256,10 +1362,11 @@ float_test! { float_test! { name: total_cmp, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { + test { use core::cmp::Ordering; const fn quiet_bit_mask() -> ::Int { @@ -1361,10 +1468,11 @@ float_test! { name: total_cmp_s_nan, attrs: { const: #[cfg(false)], + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { + test { use core::cmp::Ordering; fn quiet_bit_mask() -> ::Int { @@ -1417,18 +1525,19 @@ float_test! { float_test! { name: recip, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { + test { let nan: Float = Float::NAN; let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; let max: Float = Float::MAX; - assert_biteq!((1.0 as Float).recip(), 1.0); - assert_biteq!((2.0 as Float).recip(), 0.5); - assert_biteq!((-0.4 as Float).recip(), -2.5); - assert_biteq!((0.0 as Float).recip(), inf); + assert_biteq!(flt(1.0).recip(), 1.0); + assert_biteq!(flt(2.0).recip(), 0.5); + assert_biteq!(flt(-0.4).recip(), -2.5); + assert_biteq!(flt(0.0).recip(), inf); assert!(nan.recip().is_nan()); assert_biteq!(inf.recip(), 0.0); assert_biteq!(neg_inf.recip(), -0.0); @@ -1440,60 +1549,364 @@ float_test! { name: powi, attrs: { const: #[cfg(false)], - // FIXME(f16_f128): `powi` does not work in Miri for these types - f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], - f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], }, - test { + test { let nan: Float = Float::NAN; let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; assert_approx_eq!(Float::ONE.powi(1), Float::ONE); - assert_approx_eq!((-3.1 as Float).powi(2), 9.6100000000000005506706202140776519387, Float::POWI_APPROX); - assert_approx_eq!((5.9 as Float).powi(-2), 0.028727377190462507313100483690639638451); - assert_biteq!((8.3 as Float).powi(0), Float::ONE); + assert_approx_eq!(flt(-3.1).powi(2), 9.6100000000000005506706202140776519387, Float::POWI_APPROX); + assert_approx_eq!(flt(5.9).powi(-2), 0.028727377190462507313100483690639638451); + assert_biteq!(flt(8.3).powi(0), Float::ONE); assert!(nan.powi(2).is_nan()); assert_biteq!(inf.powi(3), inf); assert_biteq!(neg_inf.powi(2), inf); } } +float_test! { + name: powf, + attrs: { + const: #[cfg(false)], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], + }, + test { + let nan: Float = Float::NAN; + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + assert_biteq!(flt(1.0).powf(1.0), 1.0); + assert_approx_eq!(flt(3.4).powf(4.5), 246.40818323761892815995637964326426756, Float::POWF_APPROX); + assert_approx_eq!(flt(2.7).powf(-3.2), 0.041652009108526178281070304373500889273, Float::POWF_APPROX); + assert_approx_eq!(flt(-3.1).powf(2.0), 9.6100000000000005506706202140776519387, Float::POWF_APPROX); + assert_approx_eq!(flt(5.9).powf(-2.0), 0.028727377190462507313100483690639638451, Float::POWF_APPROX); + assert_biteq!(flt(8.3).powf(0.0), 1.0); + assert!(nan.powf(2.0).is_nan()); + assert_biteq!(inf.powf(2.0), inf); + assert_biteq!(neg_inf.powf(3.0), neg_inf); + } +} + +float_test! { + name: exp, + attrs: { + const: #[cfg(false)], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], + }, + test { + assert_biteq!(1.0, flt(0.0).exp()); + assert_approx_eq!(consts::E, flt(1.0).exp(), Float::EXP_APPROX); + assert_approx_eq!(148.41315910257660342111558004055227962348775, flt(5.0).exp(), Float::EXP_APPROX); + + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + let nan: Float = Float::NAN; + assert_biteq!(inf, inf.exp()); + assert_biteq!(0.0, neg_inf.exp()); + assert!(nan.exp().is_nan()); + } +} + +float_test! { + name: exp2, + attrs: { + const: #[cfg(false)], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], + }, + test { + assert_approx_eq!(32.0, flt(5.0).exp2(), Float::EXP_APPROX); + assert_biteq!(1.0, flt(0.0).exp2()); + + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + let nan: Float = Float::NAN; + assert_biteq!(inf, inf.exp2()); + assert_biteq!(0.0, neg_inf.exp2()); + assert!(nan.exp2().is_nan()); + } +} + +float_test! { + name: ln, + attrs: { + const: #[cfg(false)], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], + }, + test { + let nan: Float = Float::NAN; + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + assert_approx_eq!(flt(1.0).exp().ln(), 1.0, Float::LN_APPROX); + assert!(nan.ln().is_nan()); + assert_biteq!(inf.ln(), inf); + assert!(neg_inf.ln().is_nan()); + assert!(flt(-2.3).ln().is_nan()); + assert_biteq!(flt(-0.0).ln(), neg_inf); + assert_biteq!(flt(0.0).ln(), neg_inf); + assert_approx_eq!(flt(4.0).ln(), 1.3862943611198906188344642429163531366, Float::LN_APPROX); + } +} + +float_test! { + name: log, + attrs: { + const: #[cfg(false)], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], + }, + test { + let nan: Float = Float::NAN; + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + assert_approx_eq!(flt(10.0).log(10.0), 1.0, Float::LOG_APPROX); + assert_approx_eq!(flt(2.3).log(3.5), 0.66485771361478710036766645911922010272, Float::LOG_APPROX); + assert_approx_eq!(flt(1.0).exp().log(flt(1.0).exp()), 1.0, Float::LOG_APPROX); + assert!(flt(1.0).log(1.0).is_nan()); + assert!(flt(1.0).log(-13.9).is_nan()); + assert!(nan.log(2.3).is_nan()); + assert_biteq!(inf.log(10.0), inf); + assert!(neg_inf.log(8.8).is_nan()); + assert!(flt(-2.3).log(0.1).is_nan()); + assert_biteq!(flt(-0.0).log(2.0), neg_inf); + assert_biteq!(flt(0.0).log(7.0), neg_inf); + } +} + +float_test! { + name: log2, + attrs: { + const: #[cfg(false)], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], + }, + test { + let nan: Float = Float::NAN; + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + assert_approx_eq!(flt(10.0).log2(), 3.32192809488736234787031942948939017, Float::LOG2_APPROX); + assert_approx_eq!(flt(2.3).log2(), 1.2016338611696504130002982471978765921, Float::LOG2_APPROX); + assert_approx_eq!(flt(1.0).exp().log2(), 1.4426950408889634073599246810018921381, Float::LOG2_APPROX); + assert!(nan.log2().is_nan()); + assert_biteq!(inf.log2(), inf); + assert!(neg_inf.log2().is_nan()); + assert!(flt(-2.3).log2().is_nan()); + assert_biteq!(flt(-0.0).log2(), neg_inf); + assert_biteq!(flt(0.0).log2(), neg_inf); + } +} + +float_test! { + name: log10, + attrs: { + const: #[cfg(false)], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], + }, + test { + let nan: Float = Float::NAN; + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + assert_approx_eq!(flt(10.0).log10(), 1.0, Float::LOG10_APPROX); + assert_approx_eq!(flt(2.3).log10(), 0.36172783601759284532595218865859309898, Float::LOG10_APPROX); + assert_approx_eq!(flt(1.0).exp().log10(), 0.43429448190325182765112891891660508222, Float::LOG10_APPROX); + assert_biteq!(flt(1.0).log10(), 0.0); + assert!(nan.log10().is_nan()); + assert_biteq!(inf.log10(), inf); + assert!(neg_inf.log10().is_nan()); + assert!(flt(-2.3).log10().is_nan()); + assert_biteq!(flt(-0.0).log10(), neg_inf); + assert_biteq!(flt(0.0).log10(), neg_inf); + } +} + +float_test! { + name: asinh, + attrs: { + const: #[cfg(false)], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], + }, + test { + assert_biteq!(flt(0.0).asinh(), 0.0); + assert_biteq!(flt(-0.0).asinh(), -0.0); + + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + let nan: Float = Float::NAN; + assert_biteq!(inf.asinh(), inf); + assert_biteq!(neg_inf.asinh(), neg_inf); + assert!(nan.asinh().is_nan()); + assert!(flt(-0.0).asinh().is_sign_negative()); + + // issue 63271 + assert_approx_eq!(flt(2.0).asinh(), 1.443635475178810342493276740273105, Float::ASINH_APPROX); + assert_approx_eq!(flt(-2.0).asinh(), -1.443635475178810342493276740273105, Float::ASINH_APPROX); + + assert_approx_eq!(flt(-200.0).asinh(), -5.991470797049389, Float::ASINH_APPROX); + + // issue 153878: large values were rounding to infinity + assert_approx_eq!(Float::MAX.asinh(), Float::ASINH_ACOSH_MAX, Float::ASINH_APPROX); + + #[allow(overflowing_literals)] + if Float::MAX > flt(66000.0) { + // regression test for the catastrophic cancellation fixed in 72486 + assert_approx_eq!(flt(-67452098.07139316).asinh(), -18.720075426274544393985484294000831757220, Float::ASINH_APPROX); + } + } +} + +float_test! { + name: acosh, + attrs: { + const: #[cfg(false)], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], + }, + test { + assert_biteq!(flt(1.0).acosh(), 0.0); + assert!(flt(0.999).acosh().is_nan()); + + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + let nan: Float = Float::NAN; + assert_biteq!(inf.acosh(), inf); + assert!(neg_inf.acosh().is_nan()); + assert!(nan.acosh().is_nan()); + assert_approx_eq!(flt(2.0).acosh(), 1.31695789692481670862504634730796844, Float::ACOSH_APPROX); + assert_approx_eq!(flt(3.0).acosh(), 1.76274717403908605046521864995958461, Float::ACOSH_APPROX); + + // issue 153878: large values were rounding to infinity + assert_approx_eq!(Float::MAX.acosh(), Float::ASINH_ACOSH_MAX, Float::ACOSH_APPROX); + + #[allow(overflowing_literals)] + if Float::MAX > flt(66000.0) { + // test for low accuracy from issue 104548 + assert_approx_eq!(flt(60.0), flt(60.0).cosh().acosh(), Float::ACOSH_APPROX); + } + } +} + +float_test! { + name: atanh, + attrs: { + const: #[cfg(false)], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], + }, + test { + assert_biteq!(flt(0.0).atanh(), 0.0); + assert_biteq!(flt(-0.0).atanh(), -0.0); + + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + assert_biteq!(flt(1.0).atanh(), inf); + assert_biteq!(flt(-1.0).atanh(), neg_inf); + + let nan: Float = Float::NAN; + assert!(inf.atanh().is_nan()); + assert!(neg_inf.atanh().is_nan()); + assert!(nan.atanh().is_nan()); + + assert_approx_eq!(flt(0.5).atanh(), 0.54930614433405484569762261846126285, Float::ATANH_APPROX); + assert_approx_eq!(flt(-0.5).atanh(), -0.54930614433405484569762261846126285, Float::ATANH_APPROX); + } +} + +float_test! { + name: gamma, + attrs: { + const: #[cfg(false)], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], + }, + test { + assert_approx_eq!(flt(1.0).gamma(), 1.0, Float::GAMMA_APPROX); + assert_approx_eq!(flt(2.0).gamma(), 1.0, Float::GAMMA_APPROX); + assert_approx_eq!(flt(3.0).gamma(), 2.0, Float::GAMMA_APPROX); + assert_approx_eq!(flt(4.0).gamma(), 6.0, Float::GAMMA_APPROX); + assert_approx_eq!(flt(5.0).gamma(), 24.0, Float::GAMMA_APPROX_LOOSE); + assert_approx_eq!(flt(0.5).gamma(), consts::PI.sqrt(), Float::GAMMA_APPROX); + assert_approx_eq!(flt(-0.5).gamma(), flt(-2.0) * consts::PI.sqrt(), Float::GAMMA_APPROX_LOOSE); + assert_biteq!(flt(0.0).gamma(), Float::INFINITY); + assert_biteq!(flt(-0.0).gamma(), Float::NEG_INFINITY); + assert!(flt(-1.0).gamma().is_nan()); + assert!(flt(-2.0).gamma().is_nan()); + assert!(Float::NAN.gamma().is_nan()); + assert!(Float::NEG_INFINITY.gamma().is_nan()); + assert_biteq!(Float::INFINITY.gamma(), Float::INFINITY); + + // FIXME: there is a bug in the MinGW gamma implementation that causes this to + // return NaN. https://sourceforge.net/p/mingw-w64/bugs/517/ + if !cfg!(all(target_os = "windows", target_env = "gnu", not(target_abi = "llvm"))) { + assert_biteq!(flt(1760.9).gamma(), Float::INFINITY); + } + + if ::BITS <= 64 { + assert_biteq!(flt(171.71).gamma(), Float::INFINITY); + } + } +} + +float_test! { + name: ln_gamma, + attrs: { + const: #[cfg(false)], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], + }, + test { + assert_approx_eq!(flt(1.0).ln_gamma().0, 0.0, Float::LNGAMMA_APPROX); + assert_eq!(flt(1.0).ln_gamma().1, 1); + assert_approx_eq!(flt(2.0).ln_gamma().0, 0.0, Float::LNGAMMA_APPROX); + assert_eq!(flt(2.0).ln_gamma().1, 1); + assert_approx_eq!(flt(3.0).ln_gamma().0, flt(2.0).ln(), Float::LNGAMMA_APPROX); + assert_eq!(flt(3.0).ln_gamma().1, 1); + assert_approx_eq!(flt(-0.5).ln_gamma().0, (flt(2.0) * consts::PI.sqrt()).ln(), Float::LNGAMMA_APPROX_LOOSE); + assert_eq!(flt(-0.5).ln_gamma().1, -1); + } +} + float_test! { name: to_degrees, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, - test { - let pi: Float = Float::PI; + test { + let pi: Float = consts::PI; let nan: Float = Float::NAN; let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; - assert_biteq!((0.0 as Float).to_degrees(), 0.0); - assert_approx_eq!((-5.8 as Float).to_degrees(), -332.31552117587745090765431723855668471); + assert_biteq!(flt(0.0).to_degrees(), 0.0); + assert_approx_eq!(flt(-5.8).to_degrees(), -332.31552117587745090765431723855668471); assert_approx_eq!(pi.to_degrees(), 180.0, Float::PI_TO_DEGREES_APPROX); assert!(nan.to_degrees().is_nan()); assert_biteq!(inf.to_degrees(), inf); assert_biteq!(neg_inf.to_degrees(), neg_inf); - assert_biteq!((1.0 as Float).to_degrees(), 57.2957795130823208767981548141051703); + assert_biteq!(flt(1.0).to_degrees(), 57.2957795130823208767981548141051703); } } float_test! { name: to_radians, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, - test { - let pi: Float = Float::PI; + test { + let pi: Float = consts::PI; let nan: Float = Float::NAN; let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; - assert_biteq!((0.0 as Float).to_radians(), 0.0); - assert_approx_eq!((154.6 as Float).to_radians(), 2.6982790235832334267135442069489767804); - assert_approx_eq!((-332.31 as Float).to_radians(), -5.7999036373023566567593094812182763013); - assert_approx_eq!((180.0 as Float).to_radians(), pi, Float::_180_TO_RADIANS_APPROX); + assert_biteq!(flt(0.0).to_radians(), 0.0); + assert_approx_eq!(flt(154.6).to_radians(), 2.6982790235832334267135442069489767804); + assert_approx_eq!(flt(-332.31).to_radians(), -5.7999036373023566567593094812182763013); + assert_approx_eq!(flt(180.0).to_radians(), pi, Float::_180_TO_RADIANS_APPROX); assert!(nan.to_radians().is_nan()); assert_biteq!(inf.to_radians(), inf); assert_biteq!(neg_inf.to_radians(), neg_inf); @@ -1503,12 +1916,12 @@ float_test! { float_test! { name: to_algebraic, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, - test { - let a: Float = 123.0; - let b: Float = 456.0; + test { + let a: Float = flt(123.0); + let b: Float = flt(456.0); // Check that individual operations match their primitive counterparts. // @@ -1527,10 +1940,10 @@ float_test! { float_test! { name: to_bits_conv, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, - test { + test { assert_biteq!(flt(1.0), Float::RAW_1); assert_biteq!(flt(12.5), Float::RAW_12_DOT_5); assert_biteq!(flt(1337.0), Float::RAW_1337); @@ -1554,18 +1967,18 @@ float_test! { float_test! { name: mul_add, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], + f16: #[cfg(target_has_reliable_f16)], // FIXME(#140515): mingw has an incorrect fma https://sourceforge.net/p/mingw-w64/bugs/848/ f32: #[cfg_attr(all(target_os = "windows", target_env = "gnu", not(target_abi = "llvm")), ignore)], f64: #[cfg_attr(all(target_os = "windows", target_env = "gnu", not(target_abi = "llvm")), ignore)], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f128: #[cfg(target_has_reliable_f128)], }, - test { + test { let nan: Float = Float::NAN; let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; - assert_biteq!(flt(12.3).mul_add(4.5, 6.7), Float::MUL_ADD_RESULT); - assert_biteq!((flt(-12.3)).mul_add(-4.5, -6.7), Float::NEG_MUL_ADD_RESULT); + assert_biteq!(flt(12.3).mul_add(flt(4.5), flt(6.7)), Float::MUL_ADD_RESULT); + assert_biteq!((flt(-12.3)).mul_add(flt(-4.5), flt(-6.7)), Float::NEG_MUL_ADD_RESULT); assert_biteq!(flt(0.0).mul_add(8.9, 1.2), 1.2); assert_biteq!(flt(3.4).mul_add(-0.0, 5.6), 5.6); assert!(nan.mul_add(7.8, 9.0).is_nan()); @@ -1579,10 +1992,10 @@ float_test! { float_test! { name: from, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, - test { + test { assert_biteq!(Float::from(false), Float::ZERO); assert_biteq!(Float::from(true), Float::ONE); @@ -1601,9 +2014,9 @@ float_test! { attrs: { f16: #[cfg(false)], const f16: #[cfg(false)], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f128: #[cfg(target_has_reliable_f128)], }, - test { + test { assert_biteq!(Float::from(u16::MIN), Float::ZERO); assert_biteq!(Float::from(42_u16), 42.0); assert_biteq!(Float::from(u16::MAX), 65535.0); @@ -1620,9 +2033,9 @@ float_test! { const f16: #[cfg(false)], f32: #[cfg(false)], const f32: #[cfg(false)], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f128: #[cfg(target_has_reliable_f128)], }, - test { + test { assert_biteq!(Float::from(u32::MIN), Float::ZERO); assert_biteq!(Float::from(42_u32), 42.0); assert_biteq!(Float::from(u32::MAX), 4294967295.0); @@ -1632,6 +2045,93 @@ float_test! { } } +// Test the `float_exact_integer_constants` feature +float_test! { + name: max_exact_integer_constant, + attrs: { + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], + }, + test { + // The maximum integer that converts to a unique floating point + // value. + const MAX_EXACT_INTEGER: ::SInt = Float::MAX_EXACT_INTEGER; + + let max_minus_one = (MAX_EXACT_INTEGER - 1) as Float as ::SInt; + let max_plus_one = (MAX_EXACT_INTEGER + 1) as Float as ::SInt; + let max_plus_two = (MAX_EXACT_INTEGER + 2) as Float as ::SInt; + + // This does an extra round trip back to float for the second operand in + // order to print the results if there is a mismatch + assert_biteq!((MAX_EXACT_INTEGER - 1) as Float, max_minus_one as Float); + assert_biteq!(MAX_EXACT_INTEGER as Float, MAX_EXACT_INTEGER as Float as ::SInt as Float); + assert_biteq!((MAX_EXACT_INTEGER + 1) as Float, max_plus_one as Float); + // The first non-unique conversion, where `max_plus_two` roundtrips to + // `max_plus_one` + assert_biteq!((MAX_EXACT_INTEGER + 1) as Float, (MAX_EXACT_INTEGER + 2) as Float); + assert_biteq!((MAX_EXACT_INTEGER + 2) as Float, max_plus_one as Float); + assert_biteq!((MAX_EXACT_INTEGER + 2) as Float, max_plus_two as Float); + + // Lossless roundtrips, for integers + assert!(MAX_EXACT_INTEGER - 1 == max_minus_one); + assert!(MAX_EXACT_INTEGER == MAX_EXACT_INTEGER as Float as ::SInt); + assert!(MAX_EXACT_INTEGER + 1 == max_plus_one); + // The first non-unique conversion, where `max_plus_two` roundtrips to + // one less than the starting value + assert!(MAX_EXACT_INTEGER + 2 != max_plus_two); + + // max-1 | max+0 | max+1 | max+2 + // After roundtripping, +1 and +2 will equal each other + assert!(max_minus_one != MAX_EXACT_INTEGER); + assert!(MAX_EXACT_INTEGER != max_plus_one); + assert!(max_plus_one == max_plus_two); + } +} + +float_test! { + name: min_exact_integer_constant, + attrs: { + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], + }, + test { + // The minimum integer that converts to a unique floating point + // value. + const MIN_EXACT_INTEGER: ::SInt = Float::MIN_EXACT_INTEGER; + + // Same logic as the `max` test, but we work our way leftward + // across the number line from (min_exact + 1) to (min_exact - 2). + let min_plus_one = (MIN_EXACT_INTEGER + 1) as Float as ::SInt; + let min_minus_one = (MIN_EXACT_INTEGER - 1) as Float as ::SInt; + let min_minus_two = (MIN_EXACT_INTEGER - 2) as Float as ::SInt; + + // This does an extra round trip back to float for the second operand in + // order to print the results if there is a mismatch + assert_biteq!((MIN_EXACT_INTEGER + 1) as Float, min_plus_one as Float); + assert_biteq!(MIN_EXACT_INTEGER as Float, MIN_EXACT_INTEGER as Float as ::SInt as Float); + assert_biteq!((MIN_EXACT_INTEGER - 1) as Float, min_minus_one as Float); + // The first non-unique conversion, which roundtrips to one + // greater than the starting value. + assert_biteq!((MIN_EXACT_INTEGER - 1) as Float, (MIN_EXACT_INTEGER - 2) as Float); + assert_biteq!((MIN_EXACT_INTEGER - 2) as Float, min_minus_one as Float); + assert_biteq!((MIN_EXACT_INTEGER - 2) as Float, min_minus_two as Float); + + // Lossless roundtrips, for integers + assert!(MIN_EXACT_INTEGER + 1 == min_plus_one); + assert!(MIN_EXACT_INTEGER == MIN_EXACT_INTEGER as Float as ::SInt); + assert!(MIN_EXACT_INTEGER - 1 == min_minus_one); + // The first non-unique conversion, which roundtrips to one + // greater than the starting value. + assert!(MIN_EXACT_INTEGER - 2 != min_minus_two); + + // min-2 | min-1 | min | min+1 + // After roundtripping, -2 and -1 will equal each other. + assert!(min_plus_one != MIN_EXACT_INTEGER); + assert!(MIN_EXACT_INTEGER != min_minus_one); + assert!(min_minus_one == min_minus_two); + } +} + // FIXME(f128): Uncomment and adapt these tests once the From<{u64,i64}> impls are added. // float_test! { // name: from_u64_i64, @@ -1639,9 +2139,9 @@ float_test! { // f16: #[cfg(false)], // f32: #[cfg(false)], // f64: #[cfg(false)], -// f128: #[cfg(any(miri, target_has_reliable_f128))], +// f128: #[cfg(target_has_reliable_f128)], // }, -// test { +// test { // assert_biteq!(Float::from(u64::MIN), Float::ZERO); // assert_biteq!(Float::from(42_u64), 42.0); // assert_biteq!(Float::from(u64::MAX), 18446744073709551615.0); @@ -1650,3 +2150,30 @@ float_test! { // assert_biteq!(Float::from(i64::MAX), 9223372036854775807.0); // } // } + +float_test! { + name: real_consts, + attrs: { + // FIXME(f16_f128): add math tests when available + const: #[cfg(false)], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], + }, + test { + let pi: Float = consts::PI; + assert_approx_eq!(consts::FRAC_PI_2, pi / 2.0); + assert_approx_eq!(consts::FRAC_PI_3, pi / 3.0, Float::APPROX); + assert_approx_eq!(consts::FRAC_PI_4, pi / 4.0); + assert_approx_eq!(consts::FRAC_PI_6, pi / 6.0); + assert_approx_eq!(consts::FRAC_PI_8, pi / 8.0); + assert_approx_eq!(consts::FRAC_1_PI, 1.0 / pi); + assert_approx_eq!(consts::FRAC_2_PI, 2.0 / pi); + assert_approx_eq!(consts::FRAC_2_SQRT_PI, 2.0 / pi.sqrt()); + assert_approx_eq!(consts::SQRT_2, flt(2.0).sqrt()); + assert_approx_eq!(consts::FRAC_1_SQRT_2, 1.0 / flt(2.0).sqrt()); + assert_approx_eq!(consts::LOG2_E, consts::E.log2()); + assert_approx_eq!(consts::LOG10_E, consts::E.log10()); + assert_approx_eq!(consts::LN_2, flt(2.0).ln()); + assert_approx_eq!(consts::LN_10, flt(10.0).ln(), Float::APPROX); + } +} diff --git a/library/coretests/tests/num/flt2dec/estimator.rs b/library/coretests/tests/num/flt2dec/estimator.rs index f53282611f686..1e24048fa515a 100644 --- a/library/coretests/tests/num/flt2dec/estimator.rs +++ b/library/coretests/tests/num/flt2dec/estimator.rs @@ -1,4 +1,4 @@ -use core::num::flt2dec::estimator::*; +use core::num::imp::flt2dec::estimator::*; use crate::num::ldexp_f64; diff --git a/library/coretests/tests/num/flt2dec/mod.rs b/library/coretests/tests/num/flt2dec/mod.rs index be1bc6ac460ba..02a5d31553da1 100644 --- a/library/coretests/tests/num/flt2dec/mod.rs +++ b/library/coretests/tests/num/flt2dec/mod.rs @@ -1,11 +1,13 @@ -use core::num::flt2dec::{ +use core::num::imp::flt2dec::{ DecodableFloat, Decoded, FullDecoded, MAX_SIG_DIGITS, Sign, decode, round_up, to_exact_exp_str, to_exact_fixed_str, to_shortest_exp_str, to_shortest_str, }; -use core::num::fmt::{Formatted, Part}; +use core::num::imp::fmt::{Formatted, Part}; use std::mem::MaybeUninit; use std::{fmt, str}; +use Sign::{Minus, MinusPlus}; + use crate::num::{ldexp_f32, ldexp_f64}; mod estimator; @@ -562,8 +564,6 @@ pub fn to_shortest_str_test(mut f_: F) where F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit]) -> (&'a [u8], i16), { - use core::num::flt2dec::Sign::*; - fn to_string(f: &mut F, v: T, sign: Sign, frac_digits: usize) -> String where T: DecodableFloat, @@ -672,8 +672,6 @@ pub fn to_shortest_exp_str_test(mut f_: F) where F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit]) -> (&'a [u8], i16), { - use core::num::flt2dec::Sign::*; - fn to_string(f: &mut F, v: T, sign: Sign, exp_bounds: (i16, i16), upper: bool) -> String where T: DecodableFloat, @@ -789,15 +787,21 @@ pub fn to_exact_exp_str_test(mut f_: F) where F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit], i16) -> (&'a [u8], i16), { - use core::num::flt2dec::Sign::*; - fn to_string(f: &mut F, v: T, sign: Sign, ndigits: usize, upper: bool) -> String where T: DecodableFloat, F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit], i16) -> (&'a [u8], i16), { to_string_with_parts(|buf, parts| { - to_exact_exp_str(|d, b, l| f(d, b, l), v, sign, ndigits, upper, buf, parts) + to_exact_exp_str( + |d, b, l| f(d, b, l), + v, + sign, + ndigits.saturating_sub(1), + upper, + buf, + parts, + ) }) } @@ -1065,8 +1069,6 @@ pub fn to_exact_fixed_str_test(mut f_: F) where F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit], i16) -> (&'a [u8], i16), { - use core::num::flt2dec::Sign::*; - fn to_string(f: &mut F, v: T, sign: Sign, frac_digits: usize) -> String where T: DecodableFloat, diff --git a/library/coretests/tests/num/flt2dec/random.rs b/library/coretests/tests/num/flt2dec/random.rs index 7386139aaced5..e47aa6d37a804 100644 --- a/library/coretests/tests/num/flt2dec/random.rs +++ b/library/coretests/tests/num/flt2dec/random.rs @@ -1,10 +1,11 @@ #![cfg(not(target_arch = "wasm32"))] -use core::num::flt2dec::strategy::grisu::{format_exact_opt, format_shortest_opt}; -use core::num::flt2dec::{DecodableFloat, Decoded, FullDecoded, MAX_SIG_DIGITS, decode}; +use core::num::imp::flt2dec; use std::mem::MaybeUninit; use std::str; +use flt2dec::strategy::grisu::{format_exact_opt, format_shortest_opt}; +use flt2dec::{DecodableFloat, Decoded, FullDecoded, MAX_SIG_DIGITS, decode}; use rand::distr::{Distribution, Uniform}; pub fn decode_finite(v: T) -> Decoded { @@ -159,7 +160,7 @@ where #[test] fn shortest_random_equivalence_test() { - use core::num::flt2dec::strategy::dragon::format_shortest as fallback; + use flt2dec::strategy::dragon::format_shortest as fallback; // Miri is too slow let n = if cfg!(miri) { 10 } else { 10_000 }; @@ -174,7 +175,7 @@ fn shortest_random_equivalence_test() { #[cfg(target_has_reliable_f16)] fn shortest_f16_exhaustive_equivalence_test() { // see the f32 version - use core::num::flt2dec::strategy::dragon::format_shortest as fallback; + use flt2dec::strategy::dragon::format_shortest as fallback; f16_exhaustive_equivalence_test(format_shortest_opt, fallback, MAX_SIG_DIGITS); } @@ -188,7 +189,7 @@ fn shortest_f32_exhaustive_equivalence_test() { // with `--nocapture` (and plenty of time and appropriate rustc flags), this should print: // `done, ignored=17643158 passed=2121451881 failed=0`. - use core::num::flt2dec::strategy::dragon::format_shortest as fallback; + use flt2dec::strategy::dragon::format_shortest as fallback; f32_exhaustive_equivalence_test(format_shortest_opt, fallback, MAX_SIG_DIGITS); } @@ -197,14 +198,14 @@ fn shortest_f32_exhaustive_equivalence_test() { fn shortest_f64_hard_random_equivalence_test() { // this again probably has to use appropriate rustc flags. - use core::num::flt2dec::strategy::dragon::format_shortest as fallback; + use flt2dec::strategy::dragon::format_shortest as fallback; f64_random_equivalence_test(format_shortest_opt, fallback, MAX_SIG_DIGITS, 100_000_000); } #[test] #[cfg(target_has_reliable_f16)] fn exact_f16_random_equivalence_test() { - use core::num::flt2dec::strategy::dragon::format_exact as fallback; + use flt2dec::strategy::dragon::format_exact as fallback; // Miri is too slow let n = if cfg!(miri) { 3 } else { 1_000 }; @@ -220,7 +221,7 @@ fn exact_f16_random_equivalence_test() { #[test] fn exact_f32_random_equivalence_test() { - use core::num::flt2dec::strategy::dragon::format_exact as fallback; + use flt2dec::strategy::dragon::format_exact as fallback; // Miri is too slow let n = if cfg!(miri) { 3 } else { 1_000 }; @@ -236,7 +237,7 @@ fn exact_f32_random_equivalence_test() { #[test] fn exact_f64_random_equivalence_test() { - use core::num::flt2dec::strategy::dragon::format_exact as fallback; + use flt2dec::strategy::dragon::format_exact as fallback; // Miri is too slow let n = if cfg!(miri) { 2 } else { 1_000 }; diff --git a/library/coretests/tests/num/flt2dec/strategy/dragon.rs b/library/coretests/tests/num/flt2dec/strategy/dragon.rs index 43bb6024f9cee..886f50064a503 100644 --- a/library/coretests/tests/num/flt2dec/strategy/dragon.rs +++ b/library/coretests/tests/num/flt2dec/strategy/dragon.rs @@ -1,5 +1,5 @@ -use core::num::bignum::Big32x40 as Big; -use core::num::flt2dec::strategy::dragon::*; +use core::num::imp::bignum::Big32x40 as Big; +use core::num::imp::flt2dec::strategy::dragon::*; use super::super::*; diff --git a/library/coretests/tests/num/flt2dec/strategy/grisu.rs b/library/coretests/tests/num/flt2dec/strategy/grisu.rs index 117191e0c8fdb..8350480333380 100644 --- a/library/coretests/tests/num/flt2dec/strategy/grisu.rs +++ b/library/coretests/tests/num/flt2dec/strategy/grisu.rs @@ -1,4 +1,4 @@ -use core::num::flt2dec::strategy::grisu::*; +use core::num::imp::flt2dec::strategy::grisu::*; use super::super::*; diff --git a/library/coretests/tests/num/ieee754.rs b/library/coretests/tests/num/ieee754.rs deleted file mode 100644 index b0f6a7545aa93..0000000000000 --- a/library/coretests/tests/num/ieee754.rs +++ /dev/null @@ -1,158 +0,0 @@ -//! IEEE 754 floating point compliance tests -//! -//! To understand IEEE 754's requirements on a programming language, one must understand that the -//! requirements of IEEE 754 rest on the total programming environment, and not entirely on any -//! one component. That means the hardware, language, and even libraries are considered part of -//! conforming floating point support in a programming environment. -//! -//! A programming language's duty, accordingly, is: -//! 1. offer access to the hardware where the hardware offers support -//! 2. provide operations that fulfill the remaining requirements of the standard -//! 3. provide the ability to write additional software that can fulfill those requirements -//! -//! This may be fulfilled in any combination that the language sees fit. However, to claim that -//! a language supports IEEE 754 is to suggest that it has fulfilled requirements 1 and 2, without -//! deferring minimum requirements to libraries. This is because support for IEEE 754 is defined -//! as complete support for at least one specified floating point type as an "arithmetic" and -//! "interchange" format, plus specified type conversions to "external character sequences" and -//! integer types. -//! -//! For our purposes, -//! "interchange format" => f32, f64 -//! "arithmetic format" => f32, f64, and any "soft floats" -//! "external character sequence" => str from any float -//! "integer format" => {i,u}{8,16,32,64,128} -//! -//! None of these tests are against Rust's own implementation. They are only tests against the -//! standard. That is why they accept wildly diverse inputs or may seem to duplicate other tests. -//! Please consider this carefully when adding, removing, or reorganizing these tests. They are -//! here so that it is clear what tests are required by the standard and what can be changed. - -use ::core::str::FromStr; - -// IEEE 754 for many tests is applied to specific bit patterns. -// These generally are not applicable to NaN, however. -macro_rules! assert_biteq { - ($lhs:expr, $rhs:expr) => { - assert_eq!($lhs.to_bits(), $rhs.to_bits()) - }; -} - -// ToString uses the default fmt::Display impl without special concerns, and bypasses other parts -// of the formatting infrastructure, which makes it ideal for testing here. -macro_rules! roundtrip { - ($f:expr => $t:ty) => { - ($f).to_string().parse::<$t>().unwrap() - }; -} - -macro_rules! assert_floats_roundtrip { - ($f:ident) => { - assert_biteq!(f32::$f, roundtrip!(f32::$f => f32)); - assert_biteq!(f64::$f, roundtrip!(f64::$f => f64)); - }; - ($f:expr) => { - assert_biteq!($f as f32, roundtrip!($f => f32)); - assert_biteq!($f as f64, roundtrip!($f => f64)); - } -} - -macro_rules! assert_floats_bitne { - ($lhs:ident, $rhs:ident) => { - assert_ne!(f32::$lhs.to_bits(), f32::$rhs.to_bits()); - assert_ne!(f64::$lhs.to_bits(), f64::$rhs.to_bits()); - }; - ($lhs:expr, $rhs:expr) => { - assert_ne!(f32::to_bits($lhs), f32::to_bits($rhs)); - assert_ne!(f64::to_bits($lhs), f64::to_bits($rhs)); - }; -} - -// We must preserve signs on all numbers. That includes zero. -// -0 and 0 are == normally, so test bit equality. -#[test] -fn preserve_signed_zero() { - assert_floats_roundtrip!(-0.0); - assert_floats_roundtrip!(0.0); - assert_floats_bitne!(0.0, -0.0); -} - -#[test] -fn preserve_signed_infinity() { - assert_floats_roundtrip!(INFINITY); - assert_floats_roundtrip!(NEG_INFINITY); - assert_floats_bitne!(INFINITY, NEG_INFINITY); -} - -#[test] -fn infinity_to_str() { - assert!(match f32::INFINITY.to_string().to_lowercase().as_str() { - "+infinity" | "infinity" => true, - "+inf" | "inf" => true, - _ => false, - }); - assert!( - match f64::INFINITY.to_string().to_lowercase().as_str() { - "+infinity" | "infinity" => true, - "+inf" | "inf" => true, - _ => false, - }, - "Infinity must write to a string as some casing of inf or infinity, with an optional +." - ); -} - -#[test] -fn neg_infinity_to_str() { - assert!(match f32::NEG_INFINITY.to_string().to_lowercase().as_str() { - "-infinity" | "-inf" => true, - _ => false, - }); - assert!( - match f64::NEG_INFINITY.to_string().to_lowercase().as_str() { - "-infinity" | "-inf" => true, - _ => false, - }, - "Negative Infinity must write to a string as some casing of -inf or -infinity" - ) -} - -#[test] -fn nan_to_str() { - assert!( - match f32::NAN.to_string().to_lowercase().as_str() { - "nan" | "+nan" | "-nan" => true, - _ => false, - }, - "NaNs must write to a string as some casing of nan." - ) -} - -// "+"?("inf"|"infinity") in any case => Infinity -#[test] -fn infinity_from_str() { - assert_biteq!(f32::INFINITY, f32::from_str("infinity").unwrap()); - assert_biteq!(f32::INFINITY, f32::from_str("inf").unwrap()); - assert_biteq!(f32::INFINITY, f32::from_str("+infinity").unwrap()); - assert_biteq!(f32::INFINITY, f32::from_str("+inf").unwrap()); - // yes! this means you are weLcOmE tO mY iNfInItElY tWiStEd MiNd - assert_biteq!(f32::INFINITY, f32::from_str("+iNfInItY").unwrap()); -} - -// "-inf"|"-infinity" in any case => Negative Infinity -#[test] -fn neg_infinity_from_str() { - assert_biteq!(f32::NEG_INFINITY, f32::from_str("-infinity").unwrap()); - assert_biteq!(f32::NEG_INFINITY, f32::from_str("-inf").unwrap()); - assert_biteq!(f32::NEG_INFINITY, f32::from_str("-INF").unwrap()); - assert_biteq!(f32::NEG_INFINITY, f32::from_str("-INFinity").unwrap()); -} - -// ("+"|"-"")?"s"?"nan" in any case => qNaN -#[test] -fn qnan_from_str() { - assert!("nan".parse::().unwrap().is_nan()); - assert!("-nan".parse::().unwrap().is_nan()); - assert!("+nan".parse::().unwrap().is_nan()); - assert!("+NAN".parse::().unwrap().is_nan()); - assert!("-NaN".parse::().unwrap().is_nan()); -} diff --git a/library/coretests/tests/num/int_log.rs b/library/coretests/tests/num/int_log.rs index e8d35fc21ce6e..c8eebebc27515 100644 --- a/library/coretests/tests/num/int_log.rs +++ b/library/coretests/tests/num/int_log.rs @@ -3,9 +3,9 @@ /// Rounds the argument down to the next integer, except that we account for potential imprecision /// in the input, so if `f` is very close to an integer, it will round to that. fn round_down_imprecise(f: f32) -> u32 { - // Rounds up for values less than 16*EPSILON below an integer, + // Rounds up for values less than 32*EPSILON below an integer, // and rounds down for everything else. - (f + 16.0 * f32::EPSILON) as u32 + (f + 32.0 * f32::EPSILON) as u32 } #[test] @@ -50,7 +50,6 @@ fn checked_ilog() { } #[test] -#[cfg_attr(miri, ignore)] // FIXME test is broken on Miri: https://github.com/rust-lang/rust/issues/137591 fn checked_ilog2() { assert_eq!(5u32.checked_ilog2(), Some(2)); assert_eq!(0u64.checked_ilog2(), None); diff --git a/library/coretests/tests/num/int_macros.rs b/library/coretests/tests/num/int_macros.rs index 37336f49ef1b6..f391fe23cd1f5 100644 --- a/library/coretests/tests/num/int_macros.rs +++ b/library/coretests/tests/num/int_macros.rs @@ -2,7 +2,8 @@ macro_rules! int_module { ($T:ident, $U:ident) => { use core::num::ParseIntError; use core::ops::{BitAnd, BitOr, BitXor, Not, Shl, Shr}; - use core::$T::*; + const MAX: $T = $T::MAX; + const MIN: $T = $T::MIN; const UMAX: $U = $U::MAX; @@ -316,50 +317,291 @@ macro_rules! int_module { } fn test_pow() { + { + const R: $T = 0; + assert_eq_const_safe!($T: R.wrapping_pow(0), 1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(1), 0 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(2), 0 as $T); + assert_eq_const_safe!($T: R.wrapping_pow($T::BITS - 1), 0 as $T); + assert_eq_const_safe!($T: R.wrapping_pow($T::BITS), 0 as $T); + assert_eq_const_safe!($T: R.wrapping_pow($T::BITS + 1), 0 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(128), 0 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(129), 0 as $T); + + assert_eq_const_safe!(Option<$T>: R.checked_pow(0), Some(1 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(1), Some(0 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(2), Some(0 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow($T::BITS - 1), Some(0 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow($T::BITS), Some(0 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow($T::BITS + 1), Some(0 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(128), Some(0 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(129), Some(0 as $T)); + + assert_eq_const_safe!(($T, bool): R.overflowing_pow(0), (1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(1), (0 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(2), (0 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow($T::BITS - 1), (0 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow($T::BITS), (0 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow($T::BITS + 1), (0 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(128), (0 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(129), (0 as $T, false)); + + assert_eq_const_safe!($T: R.saturating_pow(0), 1 as $T); + assert_eq_const_safe!($T: R.saturating_pow(1), 0 as $T); + assert_eq_const_safe!($T: R.saturating_pow(2), 0 as $T); + assert_eq_const_safe!($T: R.saturating_pow($T::BITS - 1), 0 as $T); + assert_eq_const_safe!($T: R.saturating_pow($T::BITS), 0 as $T); + assert_eq_const_safe!($T: R.saturating_pow($T::BITS + 1), 0 as $T); + assert_eq_const_safe!($T: R.saturating_pow(128), 0 as $T); + assert_eq_const_safe!($T: R.saturating_pow(129), 0 as $T); + } + + { + const R: $T = 1; + assert_eq_const_safe!($T: R.wrapping_pow(0), 1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(1), 1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(2), 1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow($T::BITS - 1), 1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow($T::BITS), 1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow($T::BITS + 1), 1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(128), 1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(129), 1 as $T); + + assert_eq_const_safe!(Option<$T>: R.checked_pow(0), Some(1 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(1), Some(1 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(2), Some(1 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow($T::BITS - 1), Some(1 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow($T::BITS), Some(1 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow($T::BITS + 1), Some(1 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(128), Some(1 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(129), Some(1 as $T)); + + assert_eq_const_safe!(($T, bool): R.overflowing_pow(0), (1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(1), (1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(2), (1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow($T::BITS - 1), (1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow($T::BITS), (1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow($T::BITS + 1), (1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(128), (1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(129), (1 as $T, false)); + + assert_eq_const_safe!($T: R.saturating_pow(0), 1 as $T); + assert_eq_const_safe!($T: R.saturating_pow(1), 1 as $T); + assert_eq_const_safe!($T: R.saturating_pow(2), 1 as $T); + assert_eq_const_safe!($T: R.saturating_pow($T::BITS - 1), 1 as $T); + assert_eq_const_safe!($T: R.saturating_pow($T::BITS), 1 as $T); + assert_eq_const_safe!($T: R.saturating_pow($T::BITS + 1), 1 as $T); + assert_eq_const_safe!($T: R.saturating_pow(128), 1 as $T); + assert_eq_const_safe!($T: R.saturating_pow(129), 1 as $T); + } + + { + const R: $T = -1; + assert_eq_const_safe!($T: R.wrapping_pow(0), 1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(1), -1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(2), 1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow($T::BITS - 1), -1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow($T::BITS), 1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow($T::BITS + 1), -1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(128), 1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(129), -1 as $T); + + assert_eq_const_safe!(Option<$T>: R.checked_pow(0), Some(1 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(1), Some(-1 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(2), Some(1 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow($T::BITS - 1), Some(-1 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow($T::BITS), Some(1 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow($T::BITS + 1), Some(-1 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(128), Some(1 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(129), Some(-1 as $T)); + + assert_eq_const_safe!(($T, bool): R.overflowing_pow(0), (1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(1), (-1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(2), (1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow($T::BITS - 1), (-1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow($T::BITS), (1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow($T::BITS + 1), (-1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(128), (1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(129), (-1 as $T, false)); + + assert_eq_const_safe!($T: R.saturating_pow(0), 1 as $T); + assert_eq_const_safe!($T: R.saturating_pow(1), -1 as $T); + assert_eq_const_safe!($T: R.saturating_pow(2), 1 as $T); + assert_eq_const_safe!($T: R.saturating_pow($T::BITS - 1), -1 as $T); + assert_eq_const_safe!($T: R.saturating_pow($T::BITS), 1 as $T); + assert_eq_const_safe!($T: R.saturating_pow($T::BITS + 1), -1 as $T); + assert_eq_const_safe!($T: R.saturating_pow(128), 1 as $T); + assert_eq_const_safe!($T: R.saturating_pow(129), -1 as $T); + } + { const R: $T = 2; - assert_eq_const_safe!($T: R.pow(2), 4 as $T); - assert_eq_const_safe!($T: R.pow(0), 1 as $T); - assert_eq_const_safe!($T: R.wrapping_pow(2), 4 as $T); assert_eq_const_safe!($T: R.wrapping_pow(0), 1 as $T); - assert_eq_const_safe!(Option<$T>: R.checked_pow(2), Some(4 as $T)); + assert_eq_const_safe!($T: R.wrapping_pow(1), 2 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(2), 4 as $T); + assert_eq_const_safe!($T: R.wrapping_pow($T::BITS - 1), $T::MIN); + assert_eq_const_safe!($T: R.wrapping_pow($T::BITS), 0 as $T); + assert_eq_const_safe!($T: R.wrapping_pow($T::BITS + 1), 0 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(128), 0 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(129), 0 as $T); + assert_eq_const_safe!(Option<$T>: R.checked_pow(0), Some(1 as $T)); - assert_eq_const_safe!(($T, bool): R.overflowing_pow(2), (4 as $T, false)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(1), Some(2 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(2), Some(4 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow($T::BITS - 1), None); + assert_eq_const_safe!(Option<$T>: R.checked_pow($T::BITS), None); + assert_eq_const_safe!(Option<$T>: R.checked_pow($T::BITS + 1), None); + assert_eq_const_safe!(Option<$T>: R.checked_pow(128), None); + assert_eq_const_safe!(Option<$T>: R.checked_pow(129), None); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(0), (1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(1), (2 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(2), (4 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow($T::BITS - 1), ($T::MIN, true)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow($T::BITS), (0 as $T, true)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow($T::BITS + 1), (0 as $T, true)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(128), (0 as $T, true)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(129), (0 as $T, true)); + + assert_eq_const_safe!($T: R.saturating_pow(0), 1 as $T); + assert_eq_const_safe!($T: R.saturating_pow(1), 2 as $T); assert_eq_const_safe!($T: R.saturating_pow(2), 4 as $T); + assert_eq_const_safe!($T: R.saturating_pow($T::BITS - 1), $T::MAX); + assert_eq_const_safe!($T: R.saturating_pow($T::BITS), $T::MAX); + assert_eq_const_safe!($T: R.saturating_pow($T::BITS + 1), $T::MAX); + assert_eq_const_safe!($T: R.saturating_pow(128), $T::MAX); + assert_eq_const_safe!($T: R.saturating_pow(129), $T::MAX); + } + + { + const R: $T = -2; + assert_eq_const_safe!($T: R.wrapping_pow(0), 1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(1), -2 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(2), 4 as $T); + assert_eq_const_safe!($T: R.wrapping_pow($T::BITS - 1), $T::MIN); + assert_eq_const_safe!($T: R.wrapping_pow($T::BITS), 0 as $T); + assert_eq_const_safe!($T: R.wrapping_pow($T::BITS + 1), 0 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(128), 0 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(129), 0 as $T); + + assert_eq_const_safe!(Option<$T>: R.checked_pow(0), Some(1 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(1), Some(-2 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(2), Some(4 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow($T::BITS - 1), Some($T::MIN)); + assert_eq_const_safe!(Option<$T>: R.checked_pow($T::BITS), None); + assert_eq_const_safe!(Option<$T>: R.checked_pow($T::BITS + 1), None); + assert_eq_const_safe!(Option<$T>: R.checked_pow(128), None); + assert_eq_const_safe!(Option<$T>: R.checked_pow(129), None); + + assert_eq_const_safe!(($T, bool): R.overflowing_pow(0), (1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(1), (-2 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(2), (4 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow($T::BITS - 1), ($T::MIN, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow($T::BITS), (0 as $T, true)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow($T::BITS + 1), (0 as $T, true)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(128), (0 as $T, true)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(129), (0 as $T, true)); + assert_eq_const_safe!($T: R.saturating_pow(0), 1 as $T); + assert_eq_const_safe!($T: R.saturating_pow(1), -2 as $T); + assert_eq_const_safe!($T: R.saturating_pow(2), 4 as $T); + assert_eq_const_safe!($T: R.saturating_pow($T::BITS - 1), $T::MIN); + assert_eq_const_safe!($T: R.saturating_pow($T::BITS), $T::MAX); + assert_eq_const_safe!($T: R.saturating_pow($T::BITS + 1), $T::MIN); + assert_eq_const_safe!($T: R.saturating_pow(128), $T::MAX); + assert_eq_const_safe!($T: R.saturating_pow(129), $T::MIN); + } + + // Overflow in the shift caclculation should result in the final + // result being 0 rather than accidentally succeeding due to a + // shift within the word size. + // eg `4 ** 0x8000_0000` should give 0 rather than 1 << 0 + { + const R: $T = 4; + const HALF: u32 = u32::MAX / 2 + 1; + assert_eq_const_safe!($T: R.wrapping_pow(HALF), 0 as $T); + assert_eq_const_safe!(Option<$T>: R.checked_pow(HALF), None); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(HALF), (0 as $T, true)); + assert_eq_const_safe!($T: R.saturating_pow(HALF), $T::MAX); + } + + { + const R: $T = -4; + const HALF: u32 = u32::MAX / 2 + 1; + assert_eq_const_safe!($T: R.wrapping_pow(HALF), 0 as $T); + assert_eq_const_safe!(Option<$T>: R.checked_pow(HALF), None); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(HALF), (0 as $T, true)); + assert_eq_const_safe!($T: R.saturating_pow(HALF), $T::MAX); } { - const R: $T = MAX; - // use `^` to represent .pow() with no overflow. - // if itest::MAX == 2^j-1, then itest is a `j` bit int, - // so that `itest::MAX*itest::MAX == 2^(2*j)-2^(j+1)+1`, - // thussaturating_pow the overflowing result is exactly 1. + const R: $T = $T::MAX; + assert_eq_const_safe!($T: R.wrapping_pow(0), 1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(1), R as $T); assert_eq_const_safe!($T: R.wrapping_pow(2), 1 as $T); + + assert_eq_const_safe!($T: R.wrapping_pow(128), 1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(129), R as $T); + + assert_eq_const_safe!(Option<$T>: R.checked_pow(0), Some(1 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(1), Some(R as $T)); assert_eq_const_safe!(Option<$T>: R.checked_pow(2), None); + assert_eq_const_safe!(Option<$T>: R.checked_pow(128), None); + assert_eq_const_safe!(Option<$T>: R.checked_pow(129), None); + + assert_eq_const_safe!(($T, bool): R.overflowing_pow(0), (1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(1), (R as $T, false)); assert_eq_const_safe!(($T, bool): R.overflowing_pow(2), (1 as $T, true)); - assert_eq_const_safe!($T: R.saturating_pow(2), MAX); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(128), (1 as $T, true)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(129), (R as $T, true)); + + assert_eq_const_safe!($T: R.saturating_pow(0), 1 as $T); + assert_eq_const_safe!($T: R.saturating_pow(1), R as $T); + assert_eq_const_safe!($T: R.saturating_pow(2), $T::MAX); + assert_eq_const_safe!($T: R.saturating_pow($T::BITS - 1), $T::MAX); + assert_eq_const_safe!($T: R.saturating_pow($T::BITS), $T::MAX); + assert_eq_const_safe!($T: R.saturating_pow($T::BITS + 1), $T::MAX); + assert_eq_const_safe!($T: R.saturating_pow(128), $T::MAX); + assert_eq_const_safe!($T: R.saturating_pow(129), $T::MAX); } { - // test for negative exponent. - const R: $T = -2; - assert_eq_const_safe!($T: R.pow(2), 4 as $T); - assert_eq_const_safe!($T: R.pow(3), -8 as $T); - assert_eq_const_safe!($T: R.pow(0), 1 as $T); - assert_eq_const_safe!($T: R.wrapping_pow(2), 4 as $T); - assert_eq_const_safe!($T: R.wrapping_pow(3), -8 as $T); + const R: $T = $T::MIN; assert_eq_const_safe!($T: R.wrapping_pow(0), 1 as $T); - assert_eq_const_safe!(Option<$T>: R.checked_pow(2), Some(4 as $T)); - assert_eq_const_safe!(Option<$T>: R.checked_pow(3), Some(-8 as $T)); + assert_eq_const_safe!($T: R.wrapping_pow(1), R as $T); + assert_eq_const_safe!($T: R.wrapping_pow(2), 0 as $T); + assert_eq_const_safe!($T: R.wrapping_pow($T::BITS - 1), 0 as $T); + assert_eq_const_safe!($T: R.wrapping_pow($T::BITS), 0 as $T); + assert_eq_const_safe!($T: R.wrapping_pow($T::BITS + 1), 0 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(128), 0 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(129), 0 as $T); + assert_eq_const_safe!(Option<$T>: R.checked_pow(0), Some(1 as $T)); - assert_eq_const_safe!(($T, bool): R.overflowing_pow(2), (4 as $T, false)); - assert_eq_const_safe!(($T, bool): R.overflowing_pow(3), (-8 as $T, false)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(1), Some(R as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(2), None); + assert_eq_const_safe!(Option<$T>: R.checked_pow($T::BITS - 1), None); + assert_eq_const_safe!(Option<$T>: R.checked_pow($T::BITS), None); + assert_eq_const_safe!(Option<$T>: R.checked_pow($T::BITS + 1), None); + assert_eq_const_safe!(Option<$T>: R.checked_pow(128), None); + assert_eq_const_safe!(Option<$T>: R.checked_pow(129), None); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(0), (1 as $T, false)); - assert_eq_const_safe!($T: R.saturating_pow(2), 4 as $T); - assert_eq_const_safe!($T: R.saturating_pow(3), -8 as $T); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(1), (R as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(2), (0 as $T, true)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow($T::BITS - 1), (0 as $T, true)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow($T::BITS), (0 as $T, true)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow($T::BITS + 1), (0 as $T, true)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(128), (0 as $T, true)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(129), (0 as $T, true)); + assert_eq_const_safe!($T: R.saturating_pow(0), 1 as $T); + assert_eq_const_safe!($T: R.saturating_pow(1), R as $T); + assert_eq_const_safe!($T: R.saturating_pow(2), $T::MAX); + assert_eq_const_safe!($T: R.saturating_pow($T::BITS - 1), $T::MIN); + assert_eq_const_safe!($T: R.saturating_pow($T::BITS), $T::MAX); + assert_eq_const_safe!($T: R.saturating_pow($T::BITS + 1), $T::MIN); + assert_eq_const_safe!($T: R.saturating_pow(128), $T::MAX); + assert_eq_const_safe!($T: R.saturating_pow(129), $T::MIN); } } @@ -432,12 +674,6 @@ macro_rules! int_module { assert_eq_const_safe!(($T, bool): (0 as $T).borrowing_sub(MIN, true), (MAX, false)); } - fn test_widening_mul() { - assert_eq_const_safe!(($U, $T): MAX.widening_mul(MAX), (1, MAX / 2)); - assert_eq_const_safe!(($U, $T): MIN.widening_mul(MAX), (MIN as $U, MIN / 2)); - assert_eq_const_safe!(($U, $T): MIN.widening_mul(MIN), (0, MAX / 2 + 1)); - } - fn test_carrying_mul() { assert_eq_const_safe!(($U, $T): MAX.carrying_mul(MAX, 0), (1, MAX / 2)); assert_eq_const_safe!(($U, $T): diff --git a/library/coretests/tests/num/midpoint.rs b/library/coretests/tests/num/midpoint.rs index 71e980067842a..240a4e8d68aa6 100644 --- a/library/coretests/tests/num/midpoint.rs +++ b/library/coretests/tests/num/midpoint.rs @@ -4,7 +4,7 @@ //! - midpoint(-a, -b) == -midpoint(a, b) #[test] -#[cfg(not(miri))] +#[cfg(not(miri))] // Miri is too slow fn midpoint_obvious_impl_i8() { for a in i8::MIN..=i8::MAX { for b in i8::MIN..=i8::MAX { @@ -14,7 +14,7 @@ fn midpoint_obvious_impl_i8() { } #[test] -#[cfg(not(miri))] +#[cfg(not(miri))] // Miri is too slow fn midpoint_obvious_impl_u8() { for a in u8::MIN..=u8::MAX { for b in u8::MIN..=u8::MAX { @@ -24,7 +24,7 @@ fn midpoint_obvious_impl_u8() { } #[test] -#[cfg(not(miri))] +#[cfg(not(miri))] // Miri is too slow fn midpoint_order_expectation_i8() { for a in i8::MIN..=i8::MAX { for b in i8::MIN..=i8::MAX { @@ -34,7 +34,7 @@ fn midpoint_order_expectation_i8() { } #[test] -#[cfg(not(miri))] +#[cfg(not(miri))] // Miri is too slow fn midpoint_order_expectation_u8() { for a in u8::MIN..=u8::MAX { for b in u8::MIN..=u8::MAX { @@ -44,7 +44,7 @@ fn midpoint_order_expectation_u8() { } #[test] -#[cfg(not(miri))] +#[cfg(not(miri))] // Miri is too slow fn midpoint_negative_expectation() { for a in 0..=i8::MAX { for b in 0..=i8::MAX { diff --git a/library/coretests/tests/num/mod.rs b/library/coretests/tests/num/mod.rs index 913f766ec1683..ac65a3b59c66a 100644 --- a/library/coretests/tests/num/mod.rs +++ b/library/coretests/tests/num/mod.rs @@ -22,11 +22,14 @@ mod u64; mod u8; mod bignum; +mod carryless_mul; +mod cast; mod const_from; mod dec2flt; +mod float_ieee754_flt2dec_dec2flt; mod float_iter_sum_identity; +mod floats; mod flt2dec; -mod ieee754; mod int_log; mod int_sqrt; mod midpoint; @@ -35,6 +38,8 @@ mod niche_types; mod ops; mod wrapping; +use floats::{assert_biteq, float_test}; + /// Adds the attribute to all items in the block. macro_rules! cfg_block { ($(#[$attr:meta]{$($it:item)*})*) => {$($( @@ -113,7 +118,7 @@ fn from_str_issue7588() { #[test] #[should_panic = "radix must lie in the range `[2, 36]`"] -fn from_ascii_radix_panic() { +fn from_ascii_bytes_radix_panic() { let radix = 1; let _parsed = u64::from_str_radix("12345ABCD", radix); } @@ -370,6 +375,43 @@ fn test_f32f64() { assert!(nan.is_nan()); } +/// Conversions where $source can be represented as bool. +macro_rules! test_impl_try_from_integer_to_bool { + ($fn_name:ident, $source:ty) => { + #[test] + fn $fn_name() { + let max: $source = <$source>::MAX; + let min: $source = <$source>::MIN; + let zero: $source = 0; + let one: $source = 1; + let two: $source = 2; + assert_eq!(bool::try_from(max).unwrap_err().kind(), &IntErrorKind::PosOverflow); + if min != 0 { + assert_eq!(bool::try_from(min).unwrap_err().kind(), &IntErrorKind::NegOverflow); + assert_eq!( + bool::try_from(zero - 1).unwrap_err().kind(), + &IntErrorKind::NegOverflow + ); + } + assert_eq!(bool::try_from(zero).unwrap(), false); + assert_eq!(bool::try_from(one).unwrap(), true); + assert_eq!(bool::try_from(two).unwrap_err().kind(), &IntErrorKind::PosOverflow); + } + }; +} + +test_impl_try_from_integer_to_bool! { test_try_u8bool, u8 } +test_impl_try_from_integer_to_bool! { test_try_u16bool, u16 } +test_impl_try_from_integer_to_bool! { test_try_u32bool, u32 } +test_impl_try_from_integer_to_bool! { test_try_u64bool, u64 } +test_impl_try_from_integer_to_bool! { test_try_u128bool, u128 } + +test_impl_try_from_integer_to_bool! { test_try_i8bool, i8 } +test_impl_try_from_integer_to_bool! { test_try_i16bool, i16 } +test_impl_try_from_integer_to_bool! { test_try_i32bool, i32 } +test_impl_try_from_integer_to_bool! { test_try_i64bool, i64 } +test_impl_try_from_integer_to_bool! { test_try_i128bool, i128 } + /// Conversions where the full width of $source can be represented as $target macro_rules! test_impl_try_from_always_ok { ($fn_name:ident, $source:ty, $target: ty) => { @@ -493,9 +535,15 @@ macro_rules! test_impl_try_from_signed_to_unsigned_upper_ok { let zero: $source = 0; let neg_one: $source = -1; assert_eq!(<$target as TryFrom<$source>>::try_from(max).unwrap(), max as $target); - assert!(<$target as TryFrom<$source>>::try_from(min).is_err()); + assert_eq!( + <$target as TryFrom<$source>>::try_from(min).unwrap_err().kind(), + &IntErrorKind::NegOverflow + ); assert_eq!(<$target as TryFrom<$source>>::try_from(zero).unwrap(), zero as $target); - assert!(<$target as TryFrom<$source>>::try_from(neg_one).is_err()); + assert_eq!( + <$target as TryFrom<$source>>::try_from(neg_one).unwrap_err().kind(), + &IntErrorKind::NegOverflow + ); } }; } @@ -556,7 +604,10 @@ macro_rules! test_impl_try_from_unsigned_to_signed_upper_err { let max = <$source>::MAX; let min = <$source>::MIN; let zero: $source = 0; - assert!(<$target as TryFrom<$source>>::try_from(max).is_err()); + assert_eq!( + <$target as TryFrom<$source>>::try_from(max).unwrap_err().kind(), + &IntErrorKind::PosOverflow + ); assert_eq!(<$target as TryFrom<$source>>::try_from(min).unwrap(), min as $target); assert_eq!(<$target as TryFrom<$source>>::try_from(zero).unwrap(), zero as $target); } @@ -619,9 +670,15 @@ macro_rules! test_impl_try_from_same_sign_err { let zero: $source = 0; let t_max = <$target>::MAX; let t_min = <$target>::MIN; - assert!(<$target as TryFrom<$source>>::try_from(max).is_err()); + assert_eq!( + <$target as TryFrom<$source>>::try_from(max).unwrap_err().kind(), + &IntErrorKind::PosOverflow + ); if min != 0 { - assert!(<$target as TryFrom<$source>>::try_from(min).is_err()); + assert_eq!( + <$target as TryFrom<$source>>::try_from(min).unwrap_err().kind(), + &IntErrorKind::NegOverflow + ); } assert_eq!(<$target as TryFrom<$source>>::try_from(zero).unwrap(), zero as $target); assert_eq!( @@ -708,8 +765,14 @@ macro_rules! test_impl_try_from_signed_to_unsigned_err { let zero: $source = 0; let t_max = <$target>::MAX; let t_min = <$target>::MIN; - assert!(<$target as TryFrom<$source>>::try_from(max).is_err()); - assert!(<$target as TryFrom<$source>>::try_from(min).is_err()); + assert_eq!( + <$target as TryFrom<$source>>::try_from(max).unwrap_err().kind(), + &IntErrorKind::PosOverflow + ); + assert_eq!( + <$target as TryFrom<$source>>::try_from(min).unwrap_err().kind(), + &IntErrorKind::NegOverflow + ); assert_eq!(<$target as TryFrom<$source>>::try_from(zero).unwrap(), zero as $target); assert_eq!( <$target as TryFrom<$source>>::try_from(t_max as $source).unwrap(), diff --git a/library/coretests/tests/num/uint_macros.rs b/library/coretests/tests/num/uint_macros.rs index 7c4fb22599c03..8189776807915 100644 --- a/library/coretests/tests/num/uint_macros.rs +++ b/library/coretests/tests/num/uint_macros.rs @@ -2,15 +2,14 @@ macro_rules! uint_module { ($T:ident) => { use core::num::ParseIntError; use core::ops::{BitAnd, BitOr, BitXor, Not, Shl, Shr}; - use core::$T::*; use crate::num; #[test] fn test_overflows() { - assert!(MAX > 0); - assert!(MIN <= 0); - assert!((MIN + MAX).wrapping_add(1) == 0); + assert!($T::MAX > 0); + assert!($T::MIN <= 0); + assert!(($T::MIN + $T::MAX).wrapping_add(1) == 0); } #[test] @@ -25,7 +24,7 @@ macro_rules! uint_module { assert!(0b0110 as $T == (0b1100 as $T).bitxor(0b1010 as $T)); assert!(0b1110 as $T == (0b0111 as $T).shl(1)); assert!(0b0111 as $T == (0b1110 as $T).shr(1)); - assert!(MAX - (0b1011 as $T) == (0b1011 as $T).not()); + assert!($T::MAX - (0b1011 as $T) == (0b1011 as $T).not()); } const A: $T = 0b0101100; @@ -117,6 +116,13 @@ macro_rules! uint_module { assert_eq_const_safe!($T: <$T>::funnel_shr(_1, _1, 4), <$T>::rotate_right(_1, 4)); } + fn test_carryless_mul() { + assert_eq_const_safe!($T: <$T>::carryless_mul(0, 0), 0); + assert_eq_const_safe!($T: <$T>::carryless_mul(1, 1), 1); + + assert_eq_const_safe!($T: <$T>::carryless_mul(0b0100, 2), 0b1000); + } + fn test_swap_bytes() { assert_eq_const_safe!($T: A.swap_bytes().swap_bytes(), A); assert_eq_const_safe!($T: B.swap_bytes().swap_bytes(), B); @@ -331,30 +337,125 @@ macro_rules! uint_module { } fn test_pow() { + { + const R: $T = 0; + assert_eq_const_safe!($T: R.wrapping_pow(0), 1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(1), 0 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(2), 0 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(128), 0 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(129), 0 as $T); + + assert_eq_const_safe!(Option<$T>: R.checked_pow(0), Some(1 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(1), Some(0 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(2), Some(0 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(128), Some(0 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(129), Some(0 as $T)); + + assert_eq_const_safe!(($T, bool): R.overflowing_pow(0), (1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(1), (0 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(2), (0 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(128), (0 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(129), (0 as $T, false)); + + assert_eq_const_safe!($T: R.saturating_pow(0), 1 as $T); + assert_eq_const_safe!($T: R.saturating_pow(1), 0 as $T); + assert_eq_const_safe!($T: R.saturating_pow(2), 0 as $T); + assert_eq_const_safe!($T: R.saturating_pow(128), 0 as $T); + assert_eq_const_safe!($T: R.saturating_pow(129), 0 as $T); + } + + { + const R: $T = 1; + assert_eq_const_safe!($T: R.wrapping_pow(0), 1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(1), 1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(2), 1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(128), 1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(129), 1 as $T); + + assert_eq_const_safe!(Option<$T>: R.checked_pow(0), Some(1 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(1), Some(1 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(2), Some(1 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(128), Some(1 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(129), Some(1 as $T)); + + assert_eq_const_safe!(($T, bool): R.overflowing_pow(0), (1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(1), (1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(2), (1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(128), (1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(129), (1 as $T, false)); + + assert_eq_const_safe!($T: R.saturating_pow(0), 1 as $T); + assert_eq_const_safe!($T: R.saturating_pow(1), 1 as $T); + assert_eq_const_safe!($T: R.saturating_pow(2), 1 as $T); + assert_eq_const_safe!($T: R.saturating_pow(128), 1 as $T); + assert_eq_const_safe!($T: R.saturating_pow(129), 1 as $T); + } + { const R: $T = 2; - assert_eq_const_safe!($T: R.pow(2), 4 as $T); - assert_eq_const_safe!($T: R.pow(0), 1 as $T); - assert_eq_const_safe!($T: R.wrapping_pow(2), 4 as $T); assert_eq_const_safe!($T: R.wrapping_pow(0), 1 as $T); - assert_eq_const_safe!(Option<$T>: R.checked_pow(2), Some(4 as $T)); + assert_eq_const_safe!($T: R.wrapping_pow(1), 2 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(2), 4 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(128), 0 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(129), 0 as $T); + assert_eq_const_safe!(Option<$T>: R.checked_pow(0), Some(1 as $T)); - assert_eq_const_safe!(($T, bool): R.overflowing_pow(2), (4 as $T, false)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(1), Some(2 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(2), Some(4 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(128), None); + assert_eq_const_safe!(Option<$T>: R.checked_pow(129), None); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(0), (1 as $T, false)); - assert_eq_const_safe!($T: R.saturating_pow(2), 4 as $T); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(1), (2 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(2), (4 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(128), (0 as $T, true)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(129), (0 as $T, true)); + assert_eq_const_safe!($T: R.saturating_pow(0), 1 as $T); + assert_eq_const_safe!($T: R.saturating_pow(1), 2 as $T); + assert_eq_const_safe!($T: R.saturating_pow(2), 4 as $T); + assert_eq_const_safe!($T: R.saturating_pow(128), $T::MAX); + assert_eq_const_safe!($T: R.saturating_pow(129), $T::MAX); + } + + // Overflow in the shift caclculation should result in the final + // result being 0 rather than accidentally succeeding due to a + // shift within the word size. + // eg `4 ** 0x8000_0000` should give 0 rather than 1 << 0 + { + const R: $T = 4; + const HALF: u32 = u32::MAX / 2 + 1; + assert_eq_const_safe!($T: R.wrapping_pow(HALF), 0 as $T); + assert_eq_const_safe!(Option<$T>: R.checked_pow(HALF), None); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(HALF), (0 as $T, true)); + assert_eq_const_safe!($T: R.saturating_pow(HALF), $T::MAX); } { const R: $T = $T::MAX; - // use `^` to represent .pow() with no overflow. - // if itest::MAX == 2^j-1, then itest is a `j` bit int, - // so that `itest::MAX*itest::MAX == 2^(2*j)-2^(j+1)+1`, - // thussaturating_pow the overflowing result is exactly 1. + assert_eq_const_safe!($T: R.wrapping_pow(0), 1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(1), R as $T); assert_eq_const_safe!($T: R.wrapping_pow(2), 1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(128), 1 as $T); + assert_eq_const_safe!($T: R.wrapping_pow(129), R as $T); + + assert_eq_const_safe!(Option<$T>: R.checked_pow(0), Some(1 as $T)); + assert_eq_const_safe!(Option<$T>: R.checked_pow(1), Some(R as $T)); assert_eq_const_safe!(Option<$T>: R.checked_pow(2), None); + assert_eq_const_safe!(Option<$T>: R.checked_pow(128), None); + assert_eq_const_safe!(Option<$T>: R.checked_pow(129), None); + + assert_eq_const_safe!(($T, bool): R.overflowing_pow(0), (1 as $T, false)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(1), (R as $T, false)); assert_eq_const_safe!(($T, bool): R.overflowing_pow(2), (1 as $T, true)); - assert_eq_const_safe!($T: R.saturating_pow(2), MAX); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(128), (1 as $T, true)); + assert_eq_const_safe!(($T, bool): R.overflowing_pow(129), (R as $T, true)); + + assert_eq_const_safe!($T: R.saturating_pow(0), 1 as $T); + assert_eq_const_safe!($T: R.saturating_pow(1), R as $T); + assert_eq_const_safe!($T: R.saturating_pow(2), $T::MAX); + assert_eq_const_safe!($T: R.saturating_pow(128), $T::MAX); + assert_eq_const_safe!($T: R.saturating_pow(129), $T::MAX); } } @@ -461,14 +562,14 @@ macro_rules! uint_module { fn test_next_multiple_of() { assert_eq_const_safe!($T: (16 as $T).next_multiple_of(8), 16); assert_eq_const_safe!($T: (23 as $T).next_multiple_of(8), 24); - assert_eq_const_safe!($T: MAX.next_multiple_of(1), MAX); + assert_eq_const_safe!($T: $T::MAX.next_multiple_of(1), $T::MAX); } fn test_checked_next_multiple_of() { assert_eq_const_safe!(Option<$T>: (16 as $T).checked_next_multiple_of(8), Some(16)); assert_eq_const_safe!(Option<$T>: (23 as $T).checked_next_multiple_of(8), Some(24)); assert_eq_const_safe!(Option<$T>: (1 as $T).checked_next_multiple_of(0), None); - assert_eq_const_safe!(Option<$T>: MAX.checked_next_multiple_of(2), None); + assert_eq_const_safe!(Option<$T>: $T::MAX.checked_next_multiple_of(2), None); } fn test_is_next_multiple_of() { @@ -498,10 +599,6 @@ macro_rules! uint_module { assert_eq_const_safe!(($T, bool): $T::MAX.borrowing_sub($T::MAX, true), ($T::MAX, true)); } - fn test_widening_mul() { - assert_eq_const_safe!(($T, $T): $T::MAX.widening_mul($T::MAX), (1, $T::MAX - 1)); - } - fn test_carrying_mul() { assert_eq_const_safe!(($T, $T): $T::MAX.carrying_mul($T::MAX, 0), (1, $T::MAX - 1)); assert_eq_const_safe!(($T, $T): $T::MAX.carrying_mul($T::MAX, $T::MAX), (0, $T::MAX)); diff --git a/library/coretests/tests/ops.rs b/library/coretests/tests/ops.rs index 121718f2167e2..1cbc625959886 100644 --- a/library/coretests/tests/ops.rs +++ b/library/coretests/tests/ops.rs @@ -305,7 +305,12 @@ fn test_fmt() { let mut r = 1..=1; assert_eq!(format!("{:?}", r), "1..=1"); r.next().unwrap(); - assert_eq!(format!("{:?}", r), "1..=1 (exhausted)"); + assert_eq!(format!("{:?}", r), "2..=1"); + + let mut r = 255_u8..=255; + assert_eq!(format!("{:?}", r), "255..=255"); + r.next().unwrap(); + assert_eq!(format!("{:?}", r), "0..=255 (exhausted)"); assert_eq!(format!("{:?}", 1..1), "1..1"); assert_eq!(format!("{:?}", 1..), "1.."); diff --git a/library/coretests/tests/option.rs b/library/coretests/tests/option.rs index fc0f82ad6bb38..3df7afb4f3bea 100644 --- a/library/coretests/tests/option.rs +++ b/library/coretests/tests/option.rs @@ -495,6 +495,30 @@ const fn option_const_mut() { */ } +/// Test that `Option::get_or_insert_default` is usable in const contexts, including with types that +/// do not satisfy `T: const Destruct`. +#[test] +fn const_get_or_insert_default() { + const OPT_DEFAULT: Option> = { + let mut x = None; + x.get_or_insert_default(); + x + }; + assert!(OPT_DEFAULT.is_some()); +} + +/// Test that `Option::get_or_insert_with` is usable in const contexts, including with types that +/// do not satisfy `T: const Destruct`. +#[test] +fn const_get_or_insert_with() { + const OPT_WITH: Option> = { + let mut x = None; + x.get_or_insert_with(Vec::new); + x + }; + assert!(OPT_WITH.is_some()); +} + #[test] fn test_unwrap_drop() { struct Dtor<'a> { diff --git a/library/coretests/tests/pin.rs b/library/coretests/tests/pin.rs index b3fb06e710d44..37a729ae4f1c4 100644 --- a/library/coretests/tests/pin.rs +++ b/library/coretests/tests/pin.rs @@ -45,22 +45,6 @@ mod pin_coerce_unsized { pub trait MyTrait {} impl MyTrait for String {} - // These Pins should continue to compile. - // Do note that these instances of Pin types cannot be used - // meaningfully because all methods require a Deref/DerefMut - // bounds on the pointer type and Cell, RefCell and UnsafeCell - // do not implement Deref/DerefMut. - - pub fn cell(arg: Pin>>) -> Pin>> { - arg - } - pub fn ref_cell(arg: Pin>>) -> Pin>> { - arg - } - pub fn unsafe_cell(arg: Pin>>) -> Pin>> { - arg - } - // These sensible Pin coercions are possible. pub fn pin_mut_ref(arg: Pin<&mut String>) -> Pin<&mut dyn MyTrait> { arg @@ -68,15 +52,6 @@ mod pin_coerce_unsized { pub fn pin_ref(arg: Pin<&String>) -> Pin<&dyn MyTrait> { arg } - pub fn pin_ptr(arg: Pin<*const String>) -> Pin<*const dyn MyTrait> { - arg - } - pub fn pin_ptr_mut(arg: Pin<*mut String>) -> Pin<*mut dyn MyTrait> { - arg - } - pub fn pin_non_null(arg: Pin>) -> Pin> { - arg - } pub fn nesting_pins(arg: Pin>) -> Pin> { arg } diff --git a/library/coretests/tests/ptr.rs b/library/coretests/tests/ptr.rs index 93f9454d71378..9dbaf6690c81c 100644 --- a/library/coretests/tests/ptr.rs +++ b/library/coretests/tests/ptr.rs @@ -384,7 +384,7 @@ fn align_offset_stride_one() { #[test] fn align_offset_various_strides() { unsafe fn test_stride(ptr: *const T, align: usize) -> bool { - let numptr = ptr as usize; + let numptr = ptr.addr(); let mut expected = usize::MAX; // Naive but definitely correct way to find the *first* aligned element of stride::. for el in 0..align { diff --git a/library/coretests/tests/slice.rs b/library/coretests/tests/slice.rs index 2bb62f36bb0e6..9b0db0e733c57 100644 --- a/library/coretests/tests/slice.rs +++ b/library/coretests/tests/slice.rs @@ -5,6 +5,60 @@ use core::num::NonZero; use core::ops::{Range, RangeInclusive}; use core::slice; +#[test] +fn test_contains_bytewise_types() { + let mut bools = [false; 64]; + assert!(bools.contains(&false)); + assert!(!bools.contains(&true)); + bools[31] = true; + assert!(bools.contains(&true)); + + let one = NonZero::new(1_u8).unwrap(); + let two = NonZero::new(2_u8).unwrap(); + let three = NonZero::new(3_u8).unwrap(); + let mut nonzeros = [one; 64]; + nonzeros[31] = two; + assert!(nonzeros.contains(&one)); + assert!(nonzeros.contains(&two)); + assert!(!nonzeros.contains(&three)); + + let mut optional_nonzeros = [Some(one); 64]; + optional_nonzeros[31] = None; + assert!(optional_nonzeros.contains(&Some(one))); + assert!(optional_nonzeros.contains(&None)); + assert!(!optional_nonzeros.contains(&Some(two))); + + let minus_one = NonZero::new(-1_i8).unwrap(); + let signed_one = NonZero::new(1_i8).unwrap(); + let signed_two = NonZero::new(2_i8).unwrap(); + let mut signed_nonzeros = [minus_one; 64]; + signed_nonzeros[31] = signed_one; + assert!(signed_nonzeros.contains(&minus_one)); + assert!(signed_nonzeros.contains(&signed_one)); + assert!(!signed_nonzeros.contains(&signed_two)); + + let mut optional_signed_nonzeros = [Some(minus_one); 64]; + optional_signed_nonzeros[31] = None; + assert!(optional_signed_nonzeros.contains(&Some(minus_one))); + assert!(optional_signed_nonzeros.contains(&None)); + assert!(!optional_signed_nonzeros.contains(&Some(signed_one))); + + let mut orderings = [Ordering::Less; 64]; + orderings[31] = Ordering::Greater; + assert!(orderings.contains(&Ordering::Less)); + assert!(orderings.contains(&Ordering::Greater)); + assert!(!orderings.contains(&Ordering::Equal)); + + let a = core::ascii::Char::CapitalA; + let q = core::ascii::Char::CapitalQ; + let z = core::ascii::Char::CapitalZ; + let mut ascii = [a; 64]; + ascii[31] = z; + assert!(ascii.contains(&a)); + assert!(ascii.contains(&z)); + assert!(!ascii.contains(&q)); +} + #[test] fn test_position() { let b = [1, 2, 3, 5, 5]; @@ -1781,6 +1835,17 @@ pub mod memchr { assert_eq!(None, memchr(b'a', b"xyz")); } + #[test] + fn each_alignment() { + let mut data = [1u8; 64]; + let needle = 2; + let pos = 40; + data[pos] = needle; + for start in 0..16 { + assert_eq!(Some(pos - start), memchr(needle, &data[start..])); + } + } + #[test] fn matches_one_reversed() { assert_eq!(Some(0), memrchr(b'a', b"a")); @@ -1886,7 +1951,7 @@ fn test_align_to_empty_mid() { type Chunk = u32; for offset in 0..4 { let (_, mid, _) = unsafe { bytes[offset..offset + 1].align_to::() }; - assert_eq!(mid.as_ptr() as usize % align_of::(), 0); + assert_eq!(mid.as_ptr().addr() % align_of::(), 0); } } diff --git a/library/coretests/tests/time.rs b/library/coretests/tests/time.rs index ff80ff680943f..5877f662b7ddc 100644 --- a/library/coretests/tests/time.rs +++ b/library/coretests/tests/time.rs @@ -598,3 +598,100 @@ fn from_neg_zero() { assert_eq!(Duration::from_secs_f32(-0.0), Duration::ZERO); assert_eq!(Duration::from_secs_f64(-0.0), Duration::ZERO); } + +#[test] +#[should_panic(expected = "value is either too big or NaN")] +fn duration_fp_mul_nan() { + let _ = Duration::NANOSECOND.mul_f64(f64::NAN); +} + +#[test] +#[should_panic(expected = "value is either too big or NaN")] +fn duration_fp_mul_posinfinity() { + let _ = Duration::NANOSECOND.mul_f64(f64::INFINITY); +} + +#[test] +#[should_panic(expected = "value is negative")] +fn duration_fp_mul_neginfinity() { + let _ = Duration::NANOSECOND.mul_f64(f64::NEG_INFINITY); +} + +#[test] +#[should_panic(expected = "value is either too big or NaN")] +fn duration_fp_div_nan() { + let _ = Duration::NANOSECOND.div_f64(f64::NAN); +} + +#[test] +#[should_panic(expected = "value is either too big or NaN")] +fn duration_fp_div_poszero() { + let _ = Duration::NANOSECOND.div_f64(0.0); +} + +#[test] +#[should_panic(expected = "value is negative")] +fn duration_fp_div_negzero() { + let _ = Duration::NANOSECOND.div_f64(-0.0); +} + +#[test] +#[should_panic(expected = "value is negative")] +fn duration_fp_div_negative() { + let _ = Duration::NANOSECOND.div_f64(f64::MIN); +} + +const TOO_LARGE_FACTOR: f64 = Duration::MAX.as_nanos() as f64; +const TOO_LARGE_DIVISOR: f64 = (Duration::MAX.as_secs_f64() * 2e9).next_up(); +const SMALLEST_DIVISOR: f64 = (TOO_LARGE_DIVISOR.recip() * 2.0).next_up().next_up(); +const SMALLEST_FACTOR: f64 = TOO_LARGE_FACTOR.recip() / 2.0; +const SMALLEST_NEGFACTOR: f64 = (0.0f64.next_down() * 0.5e9).next_up(); + +#[test] +fn duration_fp_boundaries() { + const DURATION_BITS: u32 = Duration::MAX.as_nanos().ilog2() + 1; + const PRECISION: u32 = DURATION_BITS - f64::MANTISSA_DIGITS + 1; + + assert_eq!(Duration::MAX.mul_f64(0.0), Duration::ZERO); + assert_eq!(Duration::MAX.mul_f64(-0.0), Duration::ZERO); + + assert_eq!(Duration::MAX.mul_f64(SMALLEST_FACTOR), Duration::NANOSECOND); + assert_eq!(Duration::MAX.mul_f64(SMALLEST_FACTOR.next_down()), Duration::ZERO); + + assert_eq!(Duration::MAX.div_f64(TOO_LARGE_DIVISOR), Duration::ZERO); + assert_eq!(Duration::MAX.div_f64(TOO_LARGE_DIVISOR.next_down()), Duration::NANOSECOND); + + assert_eq!(Duration::MAX.div_f64(f64::INFINITY), Duration::ZERO); + assert_eq!(Duration::MAX.div_f64(f64::NEG_INFINITY), Duration::ZERO); + + // the following assertions pair with the subsequent (`should_panic`) tests + + assert_eq!(Duration::NANOSECOND.mul_f64(SMALLEST_NEGFACTOR), Duration::ZERO); + + assert!( + Duration::MAX - Duration::NANOSECOND.mul_f64(TOO_LARGE_FACTOR.next_down()) + < Duration::from_nanos(1 << PRECISION) + ); + assert!( + Duration::MAX - Duration::NANOSECOND.div_f64(SMALLEST_DIVISOR) + < Duration::from_nanos(1 << PRECISION) + ); +} + +#[test] +#[should_panic(expected = "value is negative")] +fn duration_fp_mul_negative() { + let _ = Duration::NANOSECOND.mul_f64(SMALLEST_NEGFACTOR.next_down()); +} + +#[test] +#[should_panic(expected = "value is either too big or NaN")] +fn duration_fp_mul_overflow() { + let _ = Duration::NANOSECOND.mul_f64(TOO_LARGE_FACTOR); +} + +#[test] +#[should_panic(expected = "value is either too big or NaN")] +fn duration_fp_div_overflow() { + let _ = Duration::NANOSECOND.div_f64(SMALLEST_DIVISOR.next_down()); +} diff --git a/library/coretests/tests/unicode.rs b/library/coretests/tests/unicode.rs index bbace0ef66ca3..548f38cb53932 100644 --- a/library/coretests/tests/unicode.rs +++ b/library/coretests/tests/unicode.rs @@ -1,5 +1,167 @@ +use core::iter::Step; +use core::unicode::unicode_data; +use std::ops::RangeInclusive; + +mod test_data; + #[test] pub fn version() { let (major, _minor, _update) = core::char::UNICODE_VERSION; assert!(major >= 10); } + +#[track_caller] +fn test_boolean_property(ranges: &[RangeInclusive], lookup: fn(char) -> bool) { + let mut start = '\u{80}'; + for range in ranges { + for c in start..*range.start() { + assert!(!lookup(c), "{c:?}"); + } + for c in range.clone() { + assert!(lookup(c), "{c:?}"); + } + start = Step::forward(*range.end(), 1); + } + for c in start..=char::MAX { + assert!(!lookup(c), "{c:?}"); + } +} + +#[track_caller] +fn test_case_mapping( + ranges: &[(char, [char; 3])], + lookup: fn(char) -> [char; 3], + fallback: fn(char) -> [char; 3], +) { + let mut start = '\u{80}'; + for &(key, val) in ranges { + for c in start..key { + assert_eq!(lookup(c), fallback(c), "{c:?}"); + } + assert_eq!(lookup(key), val, "{key:?}"); + start = char::from_u32(key as u32 + 1).unwrap(); + } + for c in start..=char::MAX { + assert_eq!(lookup(c), fallback(c), "{c:?}"); + } +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn alphabetic() { + test_boolean_property(test_data::ALPHABETIC, unicode_data::alphabetic::lookup); + test_boolean_property(test_data::ALPHABETIC, char::is_alphabetic); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn case_ignorable() { + test_boolean_property(test_data::CASE_IGNORABLE, unicode_data::case_ignorable::lookup); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn cf() { + test_boolean_property(test_data::CF, unicode_data::cf::lookup); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn cn_planes_0_3() { + test_boolean_property(test_data::CN_PLANES_0_3, unicode_data::cn_planes_0_3::lookup); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn default_ignorable_code_point() { + test_boolean_property( + test_data::DEFAULT_IGNORABLE_CODE_POINT, + unicode_data::default_ignorable_code_point::lookup, + ); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn grapheme_extend() { + test_boolean_property(test_data::GRAPHEME_EXTEND, unicode_data::grapheme_extend::lookup); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn lowercase() { + test_boolean_property(test_data::LOWERCASE, unicode_data::lowercase::lookup); + test_boolean_property(test_data::LOWERCASE, char::is_lowercase); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn lt() { + test_boolean_property(test_data::LT, unicode_data::lt::lookup); + test_boolean_property(test_data::LT, char::is_titlecase); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn n() { + test_boolean_property(test_data::N, unicode_data::n::lookup); + test_boolean_property(test_data::N, char::is_numeric); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn uppercase() { + test_boolean_property(test_data::UPPERCASE, unicode_data::uppercase::lookup); + test_boolean_property(test_data::UPPERCASE, char::is_uppercase); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn white_space() { + test_boolean_property(test_data::WHITE_SPACE, unicode_data::white_space::lookup); + test_boolean_property(test_data::WHITE_SPACE, char::is_whitespace); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn to_lowercase() { + test_case_mapping(test_data::TO_LOWER, unicode_data::conversions::to_lower, |c| { + [c, '\0', '\0'] + }); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn to_uppercase() { + test_case_mapping(test_data::TO_UPPER, unicode_data::conversions::to_upper, |c| { + [c, '\0', '\0'] + }); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn to_titlecase() { + test_case_mapping( + test_data::TO_TITLE, + unicode_data::conversions::to_title, + unicode_data::conversions::to_upper, + ); +} + +/// This test verifies some assumptions we currently make about Unicode casings +/// which might be falsified by future versions of the standard. +/// It's important that it gets run with debug assertions enabled, +/// so that the debug assertions in `core/src/unicode/unicode_data.rs` +/// `conversions::to_casefold` get run with every possible Unicode character as input. +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn to_casefold() { + test_case_mapping(test_data::TO_CASEFOLD, unicode_data::conversions::to_casefold, |c| { + let upper = unicode_data::conversions::to_upper(c); + let lower = upper.map(unicode_data::conversions::to_lower); + let mut result = ['\0'; 3]; + for (i, c) in lower.into_iter().flatten().filter(|&c| c != '\0').enumerate() { + result[i] = c; + } + result + }); +} diff --git a/library/coretests/tests/unicode/test_data.rs b/library/coretests/tests/unicode/test_data.rs new file mode 100644 index 0000000000000..02576ed9f5876 --- /dev/null +++ b/library/coretests/tests/unicode/test_data.rs @@ -0,0 +1,3280 @@ +//! This file is generated by `./x run src/tools/unicode-table-generator`; do not edit manually! +// ignore-tidy-file-filelength + +use std::ops::RangeInclusive; + +#[rustfmt::skip] +pub(super) static ALPHABETIC: &[RangeInclusive; 759] = &[ + '\u{aa}'..='\u{aa}', '\u{b5}'..='\u{b5}', '\u{ba}'..='\u{ba}', '\u{c0}'..='\u{d6}', + '\u{d8}'..='\u{f6}', '\u{f8}'..='\u{2c1}', '\u{2c6}'..='\u{2d1}', '\u{2e0}'..='\u{2e4}', + '\u{2ec}'..='\u{2ec}', '\u{2ee}'..='\u{2ee}', '\u{345}'..='\u{345}', '\u{363}'..='\u{374}', + '\u{376}'..='\u{377}', '\u{37a}'..='\u{37d}', '\u{37f}'..='\u{37f}', '\u{386}'..='\u{386}', + '\u{388}'..='\u{38a}', '\u{38c}'..='\u{38c}', '\u{38e}'..='\u{3a1}', '\u{3a3}'..='\u{3f5}', + '\u{3f7}'..='\u{481}', '\u{48a}'..='\u{52f}', '\u{531}'..='\u{556}', '\u{559}'..='\u{559}', + '\u{560}'..='\u{588}', '\u{5b0}'..='\u{5bd}', '\u{5bf}'..='\u{5bf}', '\u{5c1}'..='\u{5c2}', + '\u{5c4}'..='\u{5c5}', '\u{5c7}'..='\u{5c7}', '\u{5d0}'..='\u{5ea}', '\u{5ef}'..='\u{5f2}', + '\u{610}'..='\u{61a}', '\u{620}'..='\u{657}', '\u{659}'..='\u{65f}', '\u{66e}'..='\u{6d3}', + '\u{6d5}'..='\u{6dc}', '\u{6e1}'..='\u{6e8}', '\u{6ed}'..='\u{6ef}', '\u{6fa}'..='\u{6fc}', + '\u{6ff}'..='\u{6ff}', '\u{710}'..='\u{73f}', '\u{74d}'..='\u{7b1}', '\u{7ca}'..='\u{7ea}', + '\u{7f4}'..='\u{7f5}', '\u{7fa}'..='\u{7fa}', '\u{800}'..='\u{817}', '\u{81a}'..='\u{82c}', + '\u{840}'..='\u{858}', '\u{860}'..='\u{86a}', '\u{870}'..='\u{887}', '\u{889}'..='\u{88f}', + '\u{897}'..='\u{897}', '\u{8a0}'..='\u{8c9}', '\u{8d4}'..='\u{8df}', '\u{8e3}'..='\u{8e9}', + '\u{8f0}'..='\u{93b}', '\u{93d}'..='\u{94c}', '\u{94e}'..='\u{950}', '\u{955}'..='\u{963}', + '\u{971}'..='\u{983}', '\u{985}'..='\u{98c}', '\u{98f}'..='\u{990}', '\u{993}'..='\u{9a8}', + '\u{9aa}'..='\u{9b0}', '\u{9b2}'..='\u{9b2}', '\u{9b6}'..='\u{9b9}', '\u{9bd}'..='\u{9c4}', + '\u{9c7}'..='\u{9c8}', '\u{9cb}'..='\u{9cc}', '\u{9ce}'..='\u{9ce}', '\u{9d7}'..='\u{9d7}', + '\u{9dc}'..='\u{9dd}', '\u{9df}'..='\u{9e3}', '\u{9f0}'..='\u{9f1}', '\u{9fc}'..='\u{9fc}', + '\u{a01}'..='\u{a03}', '\u{a05}'..='\u{a0a}', '\u{a0f}'..='\u{a10}', '\u{a13}'..='\u{a28}', + '\u{a2a}'..='\u{a30}', '\u{a32}'..='\u{a33}', '\u{a35}'..='\u{a36}', '\u{a38}'..='\u{a39}', + '\u{a3e}'..='\u{a42}', '\u{a47}'..='\u{a48}', '\u{a4b}'..='\u{a4c}', '\u{a51}'..='\u{a51}', + '\u{a59}'..='\u{a5c}', '\u{a5e}'..='\u{a5e}', '\u{a70}'..='\u{a75}', '\u{a81}'..='\u{a83}', + '\u{a85}'..='\u{a8d}', '\u{a8f}'..='\u{a91}', '\u{a93}'..='\u{aa8}', '\u{aaa}'..='\u{ab0}', + '\u{ab2}'..='\u{ab3}', '\u{ab5}'..='\u{ab9}', '\u{abd}'..='\u{ac5}', '\u{ac7}'..='\u{ac9}', + '\u{acb}'..='\u{acc}', '\u{ad0}'..='\u{ad0}', '\u{ae0}'..='\u{ae3}', '\u{af9}'..='\u{afc}', + '\u{b01}'..='\u{b03}', '\u{b05}'..='\u{b0c}', '\u{b0f}'..='\u{b10}', '\u{b13}'..='\u{b28}', + '\u{b2a}'..='\u{b30}', '\u{b32}'..='\u{b33}', '\u{b35}'..='\u{b39}', '\u{b3d}'..='\u{b44}', + '\u{b47}'..='\u{b48}', '\u{b4b}'..='\u{b4c}', '\u{b56}'..='\u{b57}', '\u{b5c}'..='\u{b5d}', + '\u{b5f}'..='\u{b63}', '\u{b71}'..='\u{b71}', '\u{b82}'..='\u{b83}', '\u{b85}'..='\u{b8a}', + '\u{b8e}'..='\u{b90}', '\u{b92}'..='\u{b95}', '\u{b99}'..='\u{b9a}', '\u{b9c}'..='\u{b9c}', + '\u{b9e}'..='\u{b9f}', '\u{ba3}'..='\u{ba4}', '\u{ba8}'..='\u{baa}', '\u{bae}'..='\u{bb9}', + '\u{bbe}'..='\u{bc2}', '\u{bc6}'..='\u{bc8}', '\u{bca}'..='\u{bcc}', '\u{bd0}'..='\u{bd0}', + '\u{bd7}'..='\u{bd7}', '\u{c00}'..='\u{c0c}', '\u{c0e}'..='\u{c10}', '\u{c12}'..='\u{c28}', + '\u{c2a}'..='\u{c39}', '\u{c3d}'..='\u{c44}', '\u{c46}'..='\u{c48}', '\u{c4a}'..='\u{c4c}', + '\u{c55}'..='\u{c56}', '\u{c58}'..='\u{c5a}', '\u{c5c}'..='\u{c5d}', '\u{c60}'..='\u{c63}', + '\u{c80}'..='\u{c83}', '\u{c85}'..='\u{c8c}', '\u{c8e}'..='\u{c90}', '\u{c92}'..='\u{ca8}', + '\u{caa}'..='\u{cb3}', '\u{cb5}'..='\u{cb9}', '\u{cbd}'..='\u{cc4}', '\u{cc6}'..='\u{cc8}', + '\u{cca}'..='\u{ccc}', '\u{cd5}'..='\u{cd6}', '\u{cdc}'..='\u{cde}', '\u{ce0}'..='\u{ce3}', + '\u{cf1}'..='\u{cf3}', '\u{d00}'..='\u{d0c}', '\u{d0e}'..='\u{d10}', '\u{d12}'..='\u{d3a}', + '\u{d3d}'..='\u{d44}', '\u{d46}'..='\u{d48}', '\u{d4a}'..='\u{d4c}', '\u{d4e}'..='\u{d4e}', + '\u{d54}'..='\u{d57}', '\u{d5f}'..='\u{d63}', '\u{d7a}'..='\u{d7f}', '\u{d81}'..='\u{d83}', + '\u{d85}'..='\u{d96}', '\u{d9a}'..='\u{db1}', '\u{db3}'..='\u{dbb}', '\u{dbd}'..='\u{dbd}', + '\u{dc0}'..='\u{dc6}', '\u{dcf}'..='\u{dd4}', '\u{dd6}'..='\u{dd6}', '\u{dd8}'..='\u{ddf}', + '\u{df2}'..='\u{df3}', '\u{e01}'..='\u{e3a}', '\u{e40}'..='\u{e46}', '\u{e4d}'..='\u{e4d}', + '\u{e81}'..='\u{e82}', '\u{e84}'..='\u{e84}', '\u{e86}'..='\u{e8a}', '\u{e8c}'..='\u{ea3}', + '\u{ea5}'..='\u{ea5}', '\u{ea7}'..='\u{eb9}', '\u{ebb}'..='\u{ebd}', '\u{ec0}'..='\u{ec4}', + '\u{ec6}'..='\u{ec6}', '\u{ecd}'..='\u{ecd}', '\u{edc}'..='\u{edf}', '\u{f00}'..='\u{f00}', + '\u{f40}'..='\u{f47}', '\u{f49}'..='\u{f6c}', '\u{f71}'..='\u{f83}', '\u{f88}'..='\u{f97}', + '\u{f99}'..='\u{fbc}', '\u{1000}'..='\u{1036}', '\u{1038}'..='\u{1038}', + '\u{103b}'..='\u{103f}', '\u{1050}'..='\u{108f}', '\u{109a}'..='\u{109d}', + '\u{10a0}'..='\u{10c5}', '\u{10c7}'..='\u{10c7}', '\u{10cd}'..='\u{10cd}', + '\u{10d0}'..='\u{10fa}', '\u{10fc}'..='\u{1248}', '\u{124a}'..='\u{124d}', + '\u{1250}'..='\u{1256}', '\u{1258}'..='\u{1258}', '\u{125a}'..='\u{125d}', + '\u{1260}'..='\u{1288}', '\u{128a}'..='\u{128d}', '\u{1290}'..='\u{12b0}', + '\u{12b2}'..='\u{12b5}', '\u{12b8}'..='\u{12be}', '\u{12c0}'..='\u{12c0}', + '\u{12c2}'..='\u{12c5}', '\u{12c8}'..='\u{12d6}', '\u{12d8}'..='\u{1310}', + '\u{1312}'..='\u{1315}', '\u{1318}'..='\u{135a}', '\u{1380}'..='\u{138f}', + '\u{13a0}'..='\u{13f5}', '\u{13f8}'..='\u{13fd}', '\u{1401}'..='\u{166c}', + '\u{166f}'..='\u{167f}', '\u{1681}'..='\u{169a}', '\u{16a0}'..='\u{16ea}', + '\u{16ee}'..='\u{16f8}', '\u{1700}'..='\u{1713}', '\u{171f}'..='\u{1733}', + '\u{1740}'..='\u{1753}', '\u{1760}'..='\u{176c}', '\u{176e}'..='\u{1770}', + '\u{1772}'..='\u{1773}', '\u{1780}'..='\u{17b3}', '\u{17b6}'..='\u{17c8}', + '\u{17d7}'..='\u{17d7}', '\u{17dc}'..='\u{17dc}', '\u{1820}'..='\u{1878}', + '\u{1880}'..='\u{18aa}', '\u{18b0}'..='\u{18f5}', '\u{1900}'..='\u{191e}', + '\u{1920}'..='\u{192b}', '\u{1930}'..='\u{1938}', '\u{1950}'..='\u{196d}', + '\u{1970}'..='\u{1974}', '\u{1980}'..='\u{19ab}', '\u{19b0}'..='\u{19c9}', + '\u{1a00}'..='\u{1a1b}', '\u{1a20}'..='\u{1a5e}', '\u{1a61}'..='\u{1a74}', + '\u{1aa7}'..='\u{1aa7}', '\u{1abf}'..='\u{1ac0}', '\u{1acc}'..='\u{1ace}', + '\u{1b00}'..='\u{1b33}', '\u{1b35}'..='\u{1b43}', '\u{1b45}'..='\u{1b4c}', + '\u{1b80}'..='\u{1ba9}', '\u{1bac}'..='\u{1baf}', '\u{1bba}'..='\u{1be5}', + '\u{1be7}'..='\u{1bf1}', '\u{1c00}'..='\u{1c36}', '\u{1c4d}'..='\u{1c4f}', + '\u{1c5a}'..='\u{1c7d}', '\u{1c80}'..='\u{1c8a}', '\u{1c90}'..='\u{1cba}', + '\u{1cbd}'..='\u{1cbf}', '\u{1ce9}'..='\u{1cec}', '\u{1cee}'..='\u{1cf3}', + '\u{1cf5}'..='\u{1cf6}', '\u{1cfa}'..='\u{1cfa}', '\u{1d00}'..='\u{1dbf}', + '\u{1dd3}'..='\u{1df4}', '\u{1e00}'..='\u{1f15}', '\u{1f18}'..='\u{1f1d}', + '\u{1f20}'..='\u{1f45}', '\u{1f48}'..='\u{1f4d}', '\u{1f50}'..='\u{1f57}', + '\u{1f59}'..='\u{1f59}', '\u{1f5b}'..='\u{1f5b}', '\u{1f5d}'..='\u{1f5d}', + '\u{1f5f}'..='\u{1f7d}', '\u{1f80}'..='\u{1fb4}', '\u{1fb6}'..='\u{1fbc}', + '\u{1fbe}'..='\u{1fbe}', '\u{1fc2}'..='\u{1fc4}', '\u{1fc6}'..='\u{1fcc}', + '\u{1fd0}'..='\u{1fd3}', '\u{1fd6}'..='\u{1fdb}', '\u{1fe0}'..='\u{1fec}', + '\u{1ff2}'..='\u{1ff4}', '\u{1ff6}'..='\u{1ffc}', '\u{2071}'..='\u{2071}', + '\u{207f}'..='\u{207f}', '\u{2090}'..='\u{209c}', '\u{2102}'..='\u{2102}', + '\u{2107}'..='\u{2107}', '\u{210a}'..='\u{2113}', '\u{2115}'..='\u{2115}', + '\u{2119}'..='\u{211d}', '\u{2124}'..='\u{2124}', '\u{2126}'..='\u{2126}', + '\u{2128}'..='\u{2128}', '\u{212a}'..='\u{212d}', '\u{212f}'..='\u{2139}', + '\u{213c}'..='\u{213f}', '\u{2145}'..='\u{2149}', '\u{214e}'..='\u{214e}', + '\u{2160}'..='\u{2188}', '\u{24b6}'..='\u{24e9}', '\u{2c00}'..='\u{2ce4}', + '\u{2ceb}'..='\u{2cee}', '\u{2cf2}'..='\u{2cf3}', '\u{2d00}'..='\u{2d25}', + '\u{2d27}'..='\u{2d27}', '\u{2d2d}'..='\u{2d2d}', '\u{2d30}'..='\u{2d67}', + '\u{2d6f}'..='\u{2d6f}', '\u{2d80}'..='\u{2d96}', '\u{2da0}'..='\u{2da6}', + '\u{2da8}'..='\u{2dae}', '\u{2db0}'..='\u{2db6}', '\u{2db8}'..='\u{2dbe}', + '\u{2dc0}'..='\u{2dc6}', '\u{2dc8}'..='\u{2dce}', '\u{2dd0}'..='\u{2dd6}', + '\u{2dd8}'..='\u{2dde}', '\u{2de0}'..='\u{2dff}', '\u{2e2f}'..='\u{2e2f}', + '\u{3005}'..='\u{3007}', '\u{3021}'..='\u{3029}', '\u{3031}'..='\u{3035}', + '\u{3038}'..='\u{303c}', '\u{3041}'..='\u{3096}', '\u{309d}'..='\u{309f}', + '\u{30a1}'..='\u{30fa}', '\u{30fc}'..='\u{30ff}', '\u{3105}'..='\u{312f}', + '\u{3131}'..='\u{318e}', '\u{31a0}'..='\u{31bf}', '\u{31f0}'..='\u{31ff}', + '\u{3400}'..='\u{4dbf}', '\u{4e00}'..='\u{a48c}', '\u{a4d0}'..='\u{a4fd}', + '\u{a500}'..='\u{a60c}', '\u{a610}'..='\u{a61f}', '\u{a62a}'..='\u{a62b}', + '\u{a640}'..='\u{a66e}', '\u{a674}'..='\u{a67b}', '\u{a67f}'..='\u{a6ef}', + '\u{a717}'..='\u{a71f}', '\u{a722}'..='\u{a788}', '\u{a78b}'..='\u{a7dc}', + '\u{a7f1}'..='\u{a805}', '\u{a807}'..='\u{a827}', '\u{a840}'..='\u{a873}', + '\u{a880}'..='\u{a8c3}', '\u{a8c5}'..='\u{a8c5}', '\u{a8f2}'..='\u{a8f7}', + '\u{a8fb}'..='\u{a8fb}', '\u{a8fd}'..='\u{a8ff}', '\u{a90a}'..='\u{a92a}', + '\u{a930}'..='\u{a952}', '\u{a960}'..='\u{a97c}', '\u{a980}'..='\u{a9b2}', + '\u{a9b4}'..='\u{a9bf}', '\u{a9cf}'..='\u{a9cf}', '\u{a9e0}'..='\u{a9ef}', + '\u{a9fa}'..='\u{a9fe}', '\u{aa00}'..='\u{aa36}', '\u{aa40}'..='\u{aa4d}', + '\u{aa60}'..='\u{aa76}', '\u{aa7a}'..='\u{aabe}', '\u{aac0}'..='\u{aac0}', + '\u{aac2}'..='\u{aac2}', '\u{aadb}'..='\u{aadd}', '\u{aae0}'..='\u{aaef}', + '\u{aaf2}'..='\u{aaf5}', '\u{ab01}'..='\u{ab06}', '\u{ab09}'..='\u{ab0e}', + '\u{ab11}'..='\u{ab16}', '\u{ab20}'..='\u{ab26}', '\u{ab28}'..='\u{ab2e}', + '\u{ab30}'..='\u{ab5a}', '\u{ab5c}'..='\u{ab69}', '\u{ab70}'..='\u{abea}', + '\u{ac00}'..='\u{d7a3}', '\u{d7b0}'..='\u{d7c6}', '\u{d7cb}'..='\u{d7fb}', + '\u{f900}'..='\u{fa6d}', '\u{fa70}'..='\u{fad9}', '\u{fb00}'..='\u{fb06}', + '\u{fb13}'..='\u{fb17}', '\u{fb1d}'..='\u{fb28}', '\u{fb2a}'..='\u{fb36}', + '\u{fb38}'..='\u{fb3c}', '\u{fb3e}'..='\u{fb3e}', '\u{fb40}'..='\u{fb41}', + '\u{fb43}'..='\u{fb44}', '\u{fb46}'..='\u{fbb1}', '\u{fbd3}'..='\u{fd3d}', + '\u{fd50}'..='\u{fd8f}', '\u{fd92}'..='\u{fdc7}', '\u{fdf0}'..='\u{fdfb}', + '\u{fe70}'..='\u{fe74}', '\u{fe76}'..='\u{fefc}', '\u{ff21}'..='\u{ff3a}', + '\u{ff41}'..='\u{ff5a}', '\u{ff66}'..='\u{ffbe}', '\u{ffc2}'..='\u{ffc7}', + '\u{ffca}'..='\u{ffcf}', '\u{ffd2}'..='\u{ffd7}', '\u{ffda}'..='\u{ffdc}', + '\u{10000}'..='\u{1000b}', '\u{1000d}'..='\u{10026}', '\u{10028}'..='\u{1003a}', + '\u{1003c}'..='\u{1003d}', '\u{1003f}'..='\u{1004d}', '\u{10050}'..='\u{1005d}', + '\u{10080}'..='\u{100fa}', '\u{10140}'..='\u{10174}', '\u{10280}'..='\u{1029c}', + '\u{102a0}'..='\u{102d0}', '\u{10300}'..='\u{1031f}', '\u{1032d}'..='\u{1034a}', + '\u{10350}'..='\u{1037a}', '\u{10380}'..='\u{1039d}', '\u{103a0}'..='\u{103c3}', + '\u{103c8}'..='\u{103cf}', '\u{103d1}'..='\u{103d5}', '\u{10400}'..='\u{1049d}', + '\u{104b0}'..='\u{104d3}', '\u{104d8}'..='\u{104fb}', '\u{10500}'..='\u{10527}', + '\u{10530}'..='\u{10563}', '\u{10570}'..='\u{1057a}', '\u{1057c}'..='\u{1058a}', + '\u{1058c}'..='\u{10592}', '\u{10594}'..='\u{10595}', '\u{10597}'..='\u{105a1}', + '\u{105a3}'..='\u{105b1}', '\u{105b3}'..='\u{105b9}', '\u{105bb}'..='\u{105bc}', + '\u{105c0}'..='\u{105f3}', '\u{10600}'..='\u{10736}', '\u{10740}'..='\u{10755}', + '\u{10760}'..='\u{10767}', '\u{10780}'..='\u{10785}', '\u{10787}'..='\u{107b0}', + '\u{107b2}'..='\u{107ba}', '\u{10800}'..='\u{10805}', '\u{10808}'..='\u{10808}', + '\u{1080a}'..='\u{10835}', '\u{10837}'..='\u{10838}', '\u{1083c}'..='\u{1083c}', + '\u{1083f}'..='\u{10855}', '\u{10860}'..='\u{10876}', '\u{10880}'..='\u{1089e}', + '\u{108e0}'..='\u{108f2}', '\u{108f4}'..='\u{108f5}', '\u{10900}'..='\u{10915}', + '\u{10920}'..='\u{10939}', '\u{10940}'..='\u{10959}', '\u{10980}'..='\u{109b7}', + '\u{109be}'..='\u{109bf}', '\u{10a00}'..='\u{10a03}', '\u{10a05}'..='\u{10a06}', + '\u{10a0c}'..='\u{10a13}', '\u{10a15}'..='\u{10a17}', '\u{10a19}'..='\u{10a35}', + '\u{10a60}'..='\u{10a7c}', '\u{10a80}'..='\u{10a9c}', '\u{10ac0}'..='\u{10ac7}', + '\u{10ac9}'..='\u{10ae4}', '\u{10b00}'..='\u{10b35}', '\u{10b40}'..='\u{10b55}', + '\u{10b60}'..='\u{10b72}', '\u{10b80}'..='\u{10b91}', '\u{10c00}'..='\u{10c48}', + '\u{10c80}'..='\u{10cb2}', '\u{10cc0}'..='\u{10cf2}', '\u{10d00}'..='\u{10d27}', + '\u{10d4a}'..='\u{10d65}', '\u{10d69}'..='\u{10d69}', '\u{10d6f}'..='\u{10d85}', + '\u{10e80}'..='\u{10ea9}', '\u{10eab}'..='\u{10eac}', '\u{10eb0}'..='\u{10eb1}', + '\u{10ec2}'..='\u{10ec7}', '\u{10efa}'..='\u{10efc}', '\u{10f00}'..='\u{10f1c}', + '\u{10f27}'..='\u{10f27}', '\u{10f30}'..='\u{10f45}', '\u{10f70}'..='\u{10f81}', + '\u{10fb0}'..='\u{10fc4}', '\u{10fe0}'..='\u{10ff6}', '\u{11000}'..='\u{11045}', + '\u{11071}'..='\u{11075}', '\u{11080}'..='\u{110b8}', '\u{110c2}'..='\u{110c2}', + '\u{110d0}'..='\u{110e8}', '\u{11100}'..='\u{11132}', '\u{11144}'..='\u{11147}', + '\u{11150}'..='\u{11172}', '\u{11176}'..='\u{11176}', '\u{11180}'..='\u{111bf}', + '\u{111c1}'..='\u{111c4}', '\u{111ce}'..='\u{111cf}', '\u{111da}'..='\u{111da}', + '\u{111dc}'..='\u{111dc}', '\u{11200}'..='\u{11211}', '\u{11213}'..='\u{11234}', + '\u{11237}'..='\u{11237}', '\u{1123e}'..='\u{11241}', '\u{11280}'..='\u{11286}', + '\u{11288}'..='\u{11288}', '\u{1128a}'..='\u{1128d}', '\u{1128f}'..='\u{1129d}', + '\u{1129f}'..='\u{112a8}', '\u{112b0}'..='\u{112e8}', '\u{11300}'..='\u{11303}', + '\u{11305}'..='\u{1130c}', '\u{1130f}'..='\u{11310}', '\u{11313}'..='\u{11328}', + '\u{1132a}'..='\u{11330}', '\u{11332}'..='\u{11333}', '\u{11335}'..='\u{11339}', + '\u{1133d}'..='\u{11344}', '\u{11347}'..='\u{11348}', '\u{1134b}'..='\u{1134c}', + '\u{11350}'..='\u{11350}', '\u{11357}'..='\u{11357}', '\u{1135d}'..='\u{11363}', + '\u{11380}'..='\u{11389}', '\u{1138b}'..='\u{1138b}', '\u{1138e}'..='\u{1138e}', + '\u{11390}'..='\u{113b5}', '\u{113b7}'..='\u{113c0}', '\u{113c2}'..='\u{113c2}', + '\u{113c5}'..='\u{113c5}', '\u{113c7}'..='\u{113ca}', '\u{113cc}'..='\u{113cd}', + '\u{113d1}'..='\u{113d1}', '\u{113d3}'..='\u{113d3}', '\u{11400}'..='\u{11441}', + '\u{11443}'..='\u{11445}', '\u{11447}'..='\u{1144a}', '\u{1145f}'..='\u{11461}', + '\u{11480}'..='\u{114c1}', '\u{114c4}'..='\u{114c5}', '\u{114c7}'..='\u{114c7}', + '\u{11580}'..='\u{115b5}', '\u{115b8}'..='\u{115be}', '\u{115d8}'..='\u{115dd}', + '\u{11600}'..='\u{1163e}', '\u{11640}'..='\u{11640}', '\u{11644}'..='\u{11644}', + '\u{11680}'..='\u{116b5}', '\u{116b8}'..='\u{116b8}', '\u{11700}'..='\u{1171a}', + '\u{1171d}'..='\u{1172a}', '\u{11740}'..='\u{11746}', '\u{11800}'..='\u{11838}', + '\u{118a0}'..='\u{118df}', '\u{118ff}'..='\u{11906}', '\u{11909}'..='\u{11909}', + '\u{1190c}'..='\u{11913}', '\u{11915}'..='\u{11916}', '\u{11918}'..='\u{11935}', + '\u{11937}'..='\u{11938}', '\u{1193b}'..='\u{1193c}', '\u{1193f}'..='\u{11942}', + '\u{119a0}'..='\u{119a7}', '\u{119aa}'..='\u{119d7}', '\u{119da}'..='\u{119df}', + '\u{119e1}'..='\u{119e1}', '\u{119e3}'..='\u{119e4}', '\u{11a00}'..='\u{11a32}', + '\u{11a35}'..='\u{11a3e}', '\u{11a50}'..='\u{11a97}', '\u{11a9d}'..='\u{11a9d}', + '\u{11ab0}'..='\u{11af8}', '\u{11b60}'..='\u{11b67}', '\u{11bc0}'..='\u{11be0}', + '\u{11c00}'..='\u{11c08}', '\u{11c0a}'..='\u{11c36}', '\u{11c38}'..='\u{11c3e}', + '\u{11c40}'..='\u{11c40}', '\u{11c72}'..='\u{11c8f}', '\u{11c92}'..='\u{11ca7}', + '\u{11ca9}'..='\u{11cb6}', '\u{11d00}'..='\u{11d06}', '\u{11d08}'..='\u{11d09}', + '\u{11d0b}'..='\u{11d36}', '\u{11d3a}'..='\u{11d3a}', '\u{11d3c}'..='\u{11d3d}', + '\u{11d3f}'..='\u{11d41}', '\u{11d43}'..='\u{11d43}', '\u{11d46}'..='\u{11d47}', + '\u{11d60}'..='\u{11d65}', '\u{11d67}'..='\u{11d68}', '\u{11d6a}'..='\u{11d8e}', + '\u{11d90}'..='\u{11d91}', '\u{11d93}'..='\u{11d96}', '\u{11d98}'..='\u{11d98}', + '\u{11db0}'..='\u{11ddb}', '\u{11ee0}'..='\u{11ef6}', '\u{11f00}'..='\u{11f10}', + '\u{11f12}'..='\u{11f3a}', '\u{11f3e}'..='\u{11f40}', '\u{11fb0}'..='\u{11fb0}', + '\u{12000}'..='\u{12399}', '\u{12400}'..='\u{1246e}', '\u{12480}'..='\u{12543}', + '\u{12f90}'..='\u{12ff0}', '\u{13000}'..='\u{1342f}', '\u{13441}'..='\u{13446}', + '\u{13460}'..='\u{143fa}', '\u{14400}'..='\u{14646}', '\u{16100}'..='\u{1612e}', + '\u{16800}'..='\u{16a38}', '\u{16a40}'..='\u{16a5e}', '\u{16a70}'..='\u{16abe}', + '\u{16ad0}'..='\u{16aed}', '\u{16b00}'..='\u{16b2f}', '\u{16b40}'..='\u{16b43}', + '\u{16b63}'..='\u{16b77}', '\u{16b7d}'..='\u{16b8f}', '\u{16d40}'..='\u{16d6c}', + '\u{16e40}'..='\u{16e7f}', '\u{16ea0}'..='\u{16eb8}', '\u{16ebb}'..='\u{16ed3}', + '\u{16f00}'..='\u{16f4a}', '\u{16f4f}'..='\u{16f87}', '\u{16f8f}'..='\u{16f9f}', + '\u{16fe0}'..='\u{16fe1}', '\u{16fe3}'..='\u{16fe3}', '\u{16ff0}'..='\u{16ff6}', + '\u{17000}'..='\u{18cd5}', '\u{18cff}'..='\u{18d1e}', '\u{18d80}'..='\u{18df2}', + '\u{1aff0}'..='\u{1aff3}', '\u{1aff5}'..='\u{1affb}', '\u{1affd}'..='\u{1affe}', + '\u{1b000}'..='\u{1b122}', '\u{1b132}'..='\u{1b132}', '\u{1b150}'..='\u{1b152}', + '\u{1b155}'..='\u{1b155}', '\u{1b164}'..='\u{1b167}', '\u{1b170}'..='\u{1b2fb}', + '\u{1bc00}'..='\u{1bc6a}', '\u{1bc70}'..='\u{1bc7c}', '\u{1bc80}'..='\u{1bc88}', + '\u{1bc90}'..='\u{1bc99}', '\u{1bc9e}'..='\u{1bc9e}', '\u{1d400}'..='\u{1d454}', + '\u{1d456}'..='\u{1d49c}', '\u{1d49e}'..='\u{1d49f}', '\u{1d4a2}'..='\u{1d4a2}', + '\u{1d4a5}'..='\u{1d4a6}', '\u{1d4a9}'..='\u{1d4ac}', '\u{1d4ae}'..='\u{1d4b9}', + '\u{1d4bb}'..='\u{1d4bb}', '\u{1d4bd}'..='\u{1d4c3}', '\u{1d4c5}'..='\u{1d505}', + '\u{1d507}'..='\u{1d50a}', '\u{1d50d}'..='\u{1d514}', '\u{1d516}'..='\u{1d51c}', + '\u{1d51e}'..='\u{1d539}', '\u{1d53b}'..='\u{1d53e}', '\u{1d540}'..='\u{1d544}', + '\u{1d546}'..='\u{1d546}', '\u{1d54a}'..='\u{1d550}', '\u{1d552}'..='\u{1d6a5}', + '\u{1d6a8}'..='\u{1d6c0}', '\u{1d6c2}'..='\u{1d6da}', '\u{1d6dc}'..='\u{1d6fa}', + '\u{1d6fc}'..='\u{1d714}', '\u{1d716}'..='\u{1d734}', '\u{1d736}'..='\u{1d74e}', + '\u{1d750}'..='\u{1d76e}', '\u{1d770}'..='\u{1d788}', '\u{1d78a}'..='\u{1d7a8}', + '\u{1d7aa}'..='\u{1d7c2}', '\u{1d7c4}'..='\u{1d7cb}', '\u{1df00}'..='\u{1df1e}', + '\u{1df25}'..='\u{1df2a}', '\u{1e000}'..='\u{1e006}', '\u{1e008}'..='\u{1e018}', + '\u{1e01b}'..='\u{1e021}', '\u{1e023}'..='\u{1e024}', '\u{1e026}'..='\u{1e02a}', + '\u{1e030}'..='\u{1e06d}', '\u{1e08f}'..='\u{1e08f}', '\u{1e100}'..='\u{1e12c}', + '\u{1e137}'..='\u{1e13d}', '\u{1e14e}'..='\u{1e14e}', '\u{1e290}'..='\u{1e2ad}', + '\u{1e2c0}'..='\u{1e2eb}', '\u{1e4d0}'..='\u{1e4eb}', '\u{1e5d0}'..='\u{1e5ed}', + '\u{1e5f0}'..='\u{1e5f0}', '\u{1e6c0}'..='\u{1e6de}', '\u{1e6e0}'..='\u{1e6f5}', + '\u{1e6fe}'..='\u{1e6ff}', '\u{1e7e0}'..='\u{1e7e6}', '\u{1e7e8}'..='\u{1e7eb}', + '\u{1e7ed}'..='\u{1e7ee}', '\u{1e7f0}'..='\u{1e7fe}', '\u{1e800}'..='\u{1e8c4}', + '\u{1e900}'..='\u{1e943}', '\u{1e947}'..='\u{1e947}', '\u{1e94b}'..='\u{1e94b}', + '\u{1ee00}'..='\u{1ee03}', '\u{1ee05}'..='\u{1ee1f}', '\u{1ee21}'..='\u{1ee22}', + '\u{1ee24}'..='\u{1ee24}', '\u{1ee27}'..='\u{1ee27}', '\u{1ee29}'..='\u{1ee32}', + '\u{1ee34}'..='\u{1ee37}', '\u{1ee39}'..='\u{1ee39}', '\u{1ee3b}'..='\u{1ee3b}', + '\u{1ee42}'..='\u{1ee42}', '\u{1ee47}'..='\u{1ee47}', '\u{1ee49}'..='\u{1ee49}', + '\u{1ee4b}'..='\u{1ee4b}', '\u{1ee4d}'..='\u{1ee4f}', '\u{1ee51}'..='\u{1ee52}', + '\u{1ee54}'..='\u{1ee54}', '\u{1ee57}'..='\u{1ee57}', '\u{1ee59}'..='\u{1ee59}', + '\u{1ee5b}'..='\u{1ee5b}', '\u{1ee5d}'..='\u{1ee5d}', '\u{1ee5f}'..='\u{1ee5f}', + '\u{1ee61}'..='\u{1ee62}', '\u{1ee64}'..='\u{1ee64}', '\u{1ee67}'..='\u{1ee6a}', + '\u{1ee6c}'..='\u{1ee72}', '\u{1ee74}'..='\u{1ee77}', '\u{1ee79}'..='\u{1ee7c}', + '\u{1ee7e}'..='\u{1ee7e}', '\u{1ee80}'..='\u{1ee89}', '\u{1ee8b}'..='\u{1ee9b}', + '\u{1eea1}'..='\u{1eea3}', '\u{1eea5}'..='\u{1eea9}', '\u{1eeab}'..='\u{1eebb}', + '\u{1f130}'..='\u{1f149}', '\u{1f150}'..='\u{1f169}', '\u{1f170}'..='\u{1f189}', + '\u{20000}'..='\u{2a6df}', '\u{2a700}'..='\u{2b81d}', '\u{2b820}'..='\u{2cead}', + '\u{2ceb0}'..='\u{2ebe0}', '\u{2ebf0}'..='\u{2ee5d}', '\u{2f800}'..='\u{2fa1d}', + '\u{30000}'..='\u{3134a}', '\u{31350}'..='\u{33479}', +]; + +#[rustfmt::skip] +pub(super) static CASE_IGNORABLE: &[RangeInclusive; 459] = &[ + '\u{a8}'..='\u{a8}', '\u{ad}'..='\u{ad}', '\u{af}'..='\u{af}', '\u{b4}'..='\u{b4}', + '\u{b7}'..='\u{b8}', '\u{2b0}'..='\u{36f}', '\u{374}'..='\u{375}', '\u{37a}'..='\u{37a}', + '\u{384}'..='\u{385}', '\u{387}'..='\u{387}', '\u{483}'..='\u{489}', '\u{559}'..='\u{559}', + '\u{55f}'..='\u{55f}', '\u{591}'..='\u{5bd}', '\u{5bf}'..='\u{5bf}', '\u{5c1}'..='\u{5c2}', + '\u{5c4}'..='\u{5c5}', '\u{5c7}'..='\u{5c7}', '\u{5f4}'..='\u{5f4}', '\u{600}'..='\u{605}', + '\u{610}'..='\u{61a}', '\u{61c}'..='\u{61c}', '\u{640}'..='\u{640}', '\u{64b}'..='\u{65f}', + '\u{670}'..='\u{670}', '\u{6d6}'..='\u{6dd}', '\u{6df}'..='\u{6e8}', '\u{6ea}'..='\u{6ed}', + '\u{70f}'..='\u{70f}', '\u{711}'..='\u{711}', '\u{730}'..='\u{74a}', '\u{7a6}'..='\u{7b0}', + '\u{7eb}'..='\u{7f5}', '\u{7fa}'..='\u{7fa}', '\u{7fd}'..='\u{7fd}', '\u{816}'..='\u{82d}', + '\u{859}'..='\u{85b}', '\u{888}'..='\u{888}', '\u{890}'..='\u{891}', '\u{897}'..='\u{89f}', + '\u{8c9}'..='\u{902}', '\u{93a}'..='\u{93a}', '\u{93c}'..='\u{93c}', '\u{941}'..='\u{948}', + '\u{94d}'..='\u{94d}', '\u{951}'..='\u{957}', '\u{962}'..='\u{963}', '\u{971}'..='\u{971}', + '\u{981}'..='\u{981}', '\u{9bc}'..='\u{9bc}', '\u{9c1}'..='\u{9c4}', '\u{9cd}'..='\u{9cd}', + '\u{9e2}'..='\u{9e3}', '\u{9fe}'..='\u{9fe}', '\u{a01}'..='\u{a02}', '\u{a3c}'..='\u{a3c}', + '\u{a41}'..='\u{a42}', '\u{a47}'..='\u{a48}', '\u{a4b}'..='\u{a4d}', '\u{a51}'..='\u{a51}', + '\u{a70}'..='\u{a71}', '\u{a75}'..='\u{a75}', '\u{a81}'..='\u{a82}', '\u{abc}'..='\u{abc}', + '\u{ac1}'..='\u{ac5}', '\u{ac7}'..='\u{ac8}', '\u{acd}'..='\u{acd}', '\u{ae2}'..='\u{ae3}', + '\u{afa}'..='\u{aff}', '\u{b01}'..='\u{b01}', '\u{b3c}'..='\u{b3c}', '\u{b3f}'..='\u{b3f}', + '\u{b41}'..='\u{b44}', '\u{b4d}'..='\u{b4d}', '\u{b55}'..='\u{b56}', '\u{b62}'..='\u{b63}', + '\u{b82}'..='\u{b82}', '\u{bc0}'..='\u{bc0}', '\u{bcd}'..='\u{bcd}', '\u{c00}'..='\u{c00}', + '\u{c04}'..='\u{c04}', '\u{c3c}'..='\u{c3c}', '\u{c3e}'..='\u{c40}', '\u{c46}'..='\u{c48}', + '\u{c4a}'..='\u{c4d}', '\u{c55}'..='\u{c56}', '\u{c62}'..='\u{c63}', '\u{c81}'..='\u{c81}', + '\u{cbc}'..='\u{cbc}', '\u{cbf}'..='\u{cbf}', '\u{cc6}'..='\u{cc6}', '\u{ccc}'..='\u{ccd}', + '\u{ce2}'..='\u{ce3}', '\u{d00}'..='\u{d01}', '\u{d3b}'..='\u{d3c}', '\u{d41}'..='\u{d44}', + '\u{d4d}'..='\u{d4d}', '\u{d62}'..='\u{d63}', '\u{d81}'..='\u{d81}', '\u{dca}'..='\u{dca}', + '\u{dd2}'..='\u{dd4}', '\u{dd6}'..='\u{dd6}', '\u{e31}'..='\u{e31}', '\u{e34}'..='\u{e3a}', + '\u{e46}'..='\u{e4e}', '\u{eb1}'..='\u{eb1}', '\u{eb4}'..='\u{ebc}', '\u{ec6}'..='\u{ec6}', + '\u{ec8}'..='\u{ece}', '\u{f18}'..='\u{f19}', '\u{f35}'..='\u{f35}', '\u{f37}'..='\u{f37}', + '\u{f39}'..='\u{f39}', '\u{f71}'..='\u{f7e}', '\u{f80}'..='\u{f84}', '\u{f86}'..='\u{f87}', + '\u{f8d}'..='\u{f97}', '\u{f99}'..='\u{fbc}', '\u{fc6}'..='\u{fc6}', + '\u{102d}'..='\u{1030}', '\u{1032}'..='\u{1037}', '\u{1039}'..='\u{103a}', + '\u{103d}'..='\u{103e}', '\u{1058}'..='\u{1059}', '\u{105e}'..='\u{1060}', + '\u{1071}'..='\u{1074}', '\u{1082}'..='\u{1082}', '\u{1085}'..='\u{1086}', + '\u{108d}'..='\u{108d}', '\u{109d}'..='\u{109d}', '\u{10fc}'..='\u{10fc}', + '\u{135d}'..='\u{135f}', '\u{1712}'..='\u{1714}', '\u{1732}'..='\u{1733}', + '\u{1752}'..='\u{1753}', '\u{1772}'..='\u{1773}', '\u{17b4}'..='\u{17b5}', + '\u{17b7}'..='\u{17bd}', '\u{17c6}'..='\u{17c6}', '\u{17c9}'..='\u{17d3}', + '\u{17d7}'..='\u{17d7}', '\u{17dd}'..='\u{17dd}', '\u{180b}'..='\u{180f}', + '\u{1843}'..='\u{1843}', '\u{1885}'..='\u{1886}', '\u{18a9}'..='\u{18a9}', + '\u{1920}'..='\u{1922}', '\u{1927}'..='\u{1928}', '\u{1932}'..='\u{1932}', + '\u{1939}'..='\u{193b}', '\u{1a17}'..='\u{1a18}', '\u{1a1b}'..='\u{1a1b}', + '\u{1a56}'..='\u{1a56}', '\u{1a58}'..='\u{1a5e}', '\u{1a60}'..='\u{1a60}', + '\u{1a62}'..='\u{1a62}', '\u{1a65}'..='\u{1a6c}', '\u{1a73}'..='\u{1a7c}', + '\u{1a7f}'..='\u{1a7f}', '\u{1aa7}'..='\u{1aa7}', '\u{1ab0}'..='\u{1add}', + '\u{1ae0}'..='\u{1aeb}', '\u{1b00}'..='\u{1b03}', '\u{1b34}'..='\u{1b34}', + '\u{1b36}'..='\u{1b3a}', '\u{1b3c}'..='\u{1b3c}', '\u{1b42}'..='\u{1b42}', + '\u{1b6b}'..='\u{1b73}', '\u{1b80}'..='\u{1b81}', '\u{1ba2}'..='\u{1ba5}', + '\u{1ba8}'..='\u{1ba9}', '\u{1bab}'..='\u{1bad}', '\u{1be6}'..='\u{1be6}', + '\u{1be8}'..='\u{1be9}', '\u{1bed}'..='\u{1bed}', '\u{1bef}'..='\u{1bf1}', + '\u{1c2c}'..='\u{1c33}', '\u{1c36}'..='\u{1c37}', '\u{1c78}'..='\u{1c7d}', + '\u{1cd0}'..='\u{1cd2}', '\u{1cd4}'..='\u{1ce0}', '\u{1ce2}'..='\u{1ce8}', + '\u{1ced}'..='\u{1ced}', '\u{1cf4}'..='\u{1cf4}', '\u{1cf8}'..='\u{1cf9}', + '\u{1d2c}'..='\u{1d6a}', '\u{1d78}'..='\u{1d78}', '\u{1d9b}'..='\u{1dff}', + '\u{1fbd}'..='\u{1fbd}', '\u{1fbf}'..='\u{1fc1}', '\u{1fcd}'..='\u{1fcf}', + '\u{1fdd}'..='\u{1fdf}', '\u{1fed}'..='\u{1fef}', '\u{1ffd}'..='\u{1ffe}', + '\u{200b}'..='\u{200f}', '\u{2018}'..='\u{2019}', '\u{2024}'..='\u{2024}', + '\u{2027}'..='\u{2027}', '\u{202a}'..='\u{202e}', '\u{2060}'..='\u{2064}', + '\u{2066}'..='\u{206f}', '\u{2071}'..='\u{2071}', '\u{207f}'..='\u{207f}', + '\u{2090}'..='\u{209c}', '\u{20d0}'..='\u{20f0}', '\u{2c7c}'..='\u{2c7d}', + '\u{2cef}'..='\u{2cf1}', '\u{2d6f}'..='\u{2d6f}', '\u{2d7f}'..='\u{2d7f}', + '\u{2de0}'..='\u{2dff}', '\u{2e2f}'..='\u{2e2f}', '\u{3005}'..='\u{3005}', + '\u{302a}'..='\u{302d}', '\u{3031}'..='\u{3035}', '\u{303b}'..='\u{303b}', + '\u{3099}'..='\u{309e}', '\u{30fc}'..='\u{30fe}', '\u{a015}'..='\u{a015}', + '\u{a4f8}'..='\u{a4fd}', '\u{a60c}'..='\u{a60c}', '\u{a66f}'..='\u{a672}', + '\u{a674}'..='\u{a67d}', '\u{a67f}'..='\u{a67f}', '\u{a69c}'..='\u{a69f}', + '\u{a6f0}'..='\u{a6f1}', '\u{a700}'..='\u{a721}', '\u{a770}'..='\u{a770}', + '\u{a788}'..='\u{a78a}', '\u{a7f1}'..='\u{a7f4}', '\u{a7f8}'..='\u{a7f9}', + '\u{a802}'..='\u{a802}', '\u{a806}'..='\u{a806}', '\u{a80b}'..='\u{a80b}', + '\u{a825}'..='\u{a826}', '\u{a82c}'..='\u{a82c}', '\u{a8c4}'..='\u{a8c5}', + '\u{a8e0}'..='\u{a8f1}', '\u{a8ff}'..='\u{a8ff}', '\u{a926}'..='\u{a92d}', + '\u{a947}'..='\u{a951}', '\u{a980}'..='\u{a982}', '\u{a9b3}'..='\u{a9b3}', + '\u{a9b6}'..='\u{a9b9}', '\u{a9bc}'..='\u{a9bd}', '\u{a9cf}'..='\u{a9cf}', + '\u{a9e5}'..='\u{a9e6}', '\u{aa29}'..='\u{aa2e}', '\u{aa31}'..='\u{aa32}', + '\u{aa35}'..='\u{aa36}', '\u{aa43}'..='\u{aa43}', '\u{aa4c}'..='\u{aa4c}', + '\u{aa70}'..='\u{aa70}', '\u{aa7c}'..='\u{aa7c}', '\u{aab0}'..='\u{aab0}', + '\u{aab2}'..='\u{aab4}', '\u{aab7}'..='\u{aab8}', '\u{aabe}'..='\u{aabf}', + '\u{aac1}'..='\u{aac1}', '\u{aadd}'..='\u{aadd}', '\u{aaec}'..='\u{aaed}', + '\u{aaf3}'..='\u{aaf4}', '\u{aaf6}'..='\u{aaf6}', '\u{ab5b}'..='\u{ab5f}', + '\u{ab69}'..='\u{ab6b}', '\u{abe5}'..='\u{abe5}', '\u{abe8}'..='\u{abe8}', + '\u{abed}'..='\u{abed}', '\u{fb1e}'..='\u{fb1e}', '\u{fbb2}'..='\u{fbc2}', + '\u{fe00}'..='\u{fe0f}', '\u{fe13}'..='\u{fe13}', '\u{fe20}'..='\u{fe2f}', + '\u{fe52}'..='\u{fe52}', '\u{fe55}'..='\u{fe55}', '\u{feff}'..='\u{feff}', + '\u{ff07}'..='\u{ff07}', '\u{ff0e}'..='\u{ff0e}', '\u{ff1a}'..='\u{ff1a}', + '\u{ff3e}'..='\u{ff3e}', '\u{ff40}'..='\u{ff40}', '\u{ff70}'..='\u{ff70}', + '\u{ff9e}'..='\u{ff9f}', '\u{ffe3}'..='\u{ffe3}', '\u{fff9}'..='\u{fffb}', + '\u{101fd}'..='\u{101fd}', '\u{102e0}'..='\u{102e0}', '\u{10376}'..='\u{1037a}', + '\u{10780}'..='\u{10785}', '\u{10787}'..='\u{107b0}', '\u{107b2}'..='\u{107ba}', + '\u{10a01}'..='\u{10a03}', '\u{10a05}'..='\u{10a06}', '\u{10a0c}'..='\u{10a0f}', + '\u{10a38}'..='\u{10a3a}', '\u{10a3f}'..='\u{10a3f}', '\u{10ae5}'..='\u{10ae6}', + '\u{10d24}'..='\u{10d27}', '\u{10d4e}'..='\u{10d4e}', '\u{10d69}'..='\u{10d6d}', + '\u{10d6f}'..='\u{10d6f}', '\u{10eab}'..='\u{10eac}', '\u{10ec5}'..='\u{10ec5}', + '\u{10efa}'..='\u{10eff}', '\u{10f46}'..='\u{10f50}', '\u{10f82}'..='\u{10f85}', + '\u{11001}'..='\u{11001}', '\u{11038}'..='\u{11046}', '\u{11070}'..='\u{11070}', + '\u{11073}'..='\u{11074}', '\u{1107f}'..='\u{11081}', '\u{110b3}'..='\u{110b6}', + '\u{110b9}'..='\u{110ba}', '\u{110bd}'..='\u{110bd}', '\u{110c2}'..='\u{110c2}', + '\u{110cd}'..='\u{110cd}', '\u{11100}'..='\u{11102}', '\u{11127}'..='\u{1112b}', + '\u{1112d}'..='\u{11134}', '\u{11173}'..='\u{11173}', '\u{11180}'..='\u{11181}', + '\u{111b6}'..='\u{111be}', '\u{111c9}'..='\u{111cc}', '\u{111cf}'..='\u{111cf}', + '\u{1122f}'..='\u{11231}', '\u{11234}'..='\u{11234}', '\u{11236}'..='\u{11237}', + '\u{1123e}'..='\u{1123e}', '\u{11241}'..='\u{11241}', '\u{112df}'..='\u{112df}', + '\u{112e3}'..='\u{112ea}', '\u{11300}'..='\u{11301}', '\u{1133b}'..='\u{1133c}', + '\u{11340}'..='\u{11340}', '\u{11366}'..='\u{1136c}', '\u{11370}'..='\u{11374}', + '\u{113bb}'..='\u{113c0}', '\u{113ce}'..='\u{113ce}', '\u{113d0}'..='\u{113d0}', + '\u{113d2}'..='\u{113d2}', '\u{113e1}'..='\u{113e2}', '\u{11438}'..='\u{1143f}', + '\u{11442}'..='\u{11444}', '\u{11446}'..='\u{11446}', '\u{1145e}'..='\u{1145e}', + '\u{114b3}'..='\u{114b8}', '\u{114ba}'..='\u{114ba}', '\u{114bf}'..='\u{114c0}', + '\u{114c2}'..='\u{114c3}', '\u{115b2}'..='\u{115b5}', '\u{115bc}'..='\u{115bd}', + '\u{115bf}'..='\u{115c0}', '\u{115dc}'..='\u{115dd}', '\u{11633}'..='\u{1163a}', + '\u{1163d}'..='\u{1163d}', '\u{1163f}'..='\u{11640}', '\u{116ab}'..='\u{116ab}', + '\u{116ad}'..='\u{116ad}', '\u{116b0}'..='\u{116b5}', '\u{116b7}'..='\u{116b7}', + '\u{1171d}'..='\u{1171d}', '\u{1171f}'..='\u{1171f}', '\u{11722}'..='\u{11725}', + '\u{11727}'..='\u{1172b}', '\u{1182f}'..='\u{11837}', '\u{11839}'..='\u{1183a}', + '\u{1193b}'..='\u{1193c}', '\u{1193e}'..='\u{1193e}', '\u{11943}'..='\u{11943}', + '\u{119d4}'..='\u{119d7}', '\u{119da}'..='\u{119db}', '\u{119e0}'..='\u{119e0}', + '\u{11a01}'..='\u{11a0a}', '\u{11a33}'..='\u{11a38}', '\u{11a3b}'..='\u{11a3e}', + '\u{11a47}'..='\u{11a47}', '\u{11a51}'..='\u{11a56}', '\u{11a59}'..='\u{11a5b}', + '\u{11a8a}'..='\u{11a96}', '\u{11a98}'..='\u{11a99}', '\u{11b60}'..='\u{11b60}', + '\u{11b62}'..='\u{11b64}', '\u{11b66}'..='\u{11b66}', '\u{11c30}'..='\u{11c36}', + '\u{11c38}'..='\u{11c3d}', '\u{11c3f}'..='\u{11c3f}', '\u{11c92}'..='\u{11ca7}', + '\u{11caa}'..='\u{11cb0}', '\u{11cb2}'..='\u{11cb3}', '\u{11cb5}'..='\u{11cb6}', + '\u{11d31}'..='\u{11d36}', '\u{11d3a}'..='\u{11d3a}', '\u{11d3c}'..='\u{11d3d}', + '\u{11d3f}'..='\u{11d45}', '\u{11d47}'..='\u{11d47}', '\u{11d90}'..='\u{11d91}', + '\u{11d95}'..='\u{11d95}', '\u{11d97}'..='\u{11d97}', '\u{11dd9}'..='\u{11dd9}', + '\u{11ef3}'..='\u{11ef4}', '\u{11f00}'..='\u{11f01}', '\u{11f36}'..='\u{11f3a}', + '\u{11f40}'..='\u{11f40}', '\u{11f42}'..='\u{11f42}', '\u{11f5a}'..='\u{11f5a}', + '\u{13430}'..='\u{13440}', '\u{13447}'..='\u{13455}', '\u{1611e}'..='\u{16129}', + '\u{1612d}'..='\u{1612f}', '\u{16af0}'..='\u{16af4}', '\u{16b30}'..='\u{16b36}', + '\u{16b40}'..='\u{16b43}', '\u{16d40}'..='\u{16d42}', '\u{16d6b}'..='\u{16d6c}', + '\u{16f4f}'..='\u{16f4f}', '\u{16f8f}'..='\u{16f9f}', '\u{16fe0}'..='\u{16fe1}', + '\u{16fe3}'..='\u{16fe4}', '\u{16ff2}'..='\u{16ff3}', '\u{1aff0}'..='\u{1aff3}', + '\u{1aff5}'..='\u{1affb}', '\u{1affd}'..='\u{1affe}', '\u{1bc9d}'..='\u{1bc9e}', + '\u{1bca0}'..='\u{1bca3}', '\u{1cf00}'..='\u{1cf2d}', '\u{1cf30}'..='\u{1cf46}', + '\u{1d167}'..='\u{1d169}', '\u{1d173}'..='\u{1d182}', '\u{1d185}'..='\u{1d18b}', + '\u{1d1aa}'..='\u{1d1ad}', '\u{1d242}'..='\u{1d244}', '\u{1da00}'..='\u{1da36}', + '\u{1da3b}'..='\u{1da6c}', '\u{1da75}'..='\u{1da75}', '\u{1da84}'..='\u{1da84}', + '\u{1da9b}'..='\u{1da9f}', '\u{1daa1}'..='\u{1daaf}', '\u{1e000}'..='\u{1e006}', + '\u{1e008}'..='\u{1e018}', '\u{1e01b}'..='\u{1e021}', '\u{1e023}'..='\u{1e024}', + '\u{1e026}'..='\u{1e02a}', '\u{1e030}'..='\u{1e06d}', '\u{1e08f}'..='\u{1e08f}', + '\u{1e130}'..='\u{1e13d}', '\u{1e2ae}'..='\u{1e2ae}', '\u{1e2ec}'..='\u{1e2ef}', + '\u{1e4eb}'..='\u{1e4ef}', '\u{1e5ee}'..='\u{1e5ef}', '\u{1e6e3}'..='\u{1e6e3}', + '\u{1e6e6}'..='\u{1e6e6}', '\u{1e6ee}'..='\u{1e6ef}', '\u{1e6f5}'..='\u{1e6f5}', + '\u{1e6ff}'..='\u{1e6ff}', '\u{1e8d0}'..='\u{1e8d6}', '\u{1e944}'..='\u{1e94b}', + '\u{1f3fb}'..='\u{1f3ff}', '\u{e0001}'..='\u{e0001}', '\u{e0020}'..='\u{e007f}', + '\u{e0100}'..='\u{e01ef}', +]; + +#[rustfmt::skip] +pub(super) static CF: &[RangeInclusive; 21] = &[ + '\u{ad}'..='\u{ad}', '\u{600}'..='\u{605}', '\u{61c}'..='\u{61c}', '\u{6dd}'..='\u{6dd}', + '\u{70f}'..='\u{70f}', '\u{890}'..='\u{891}', '\u{8e2}'..='\u{8e2}', + '\u{180e}'..='\u{180e}', '\u{200b}'..='\u{200f}', '\u{202a}'..='\u{202e}', + '\u{2060}'..='\u{2064}', '\u{2066}'..='\u{206f}', '\u{feff}'..='\u{feff}', + '\u{fff9}'..='\u{fffb}', '\u{110bd}'..='\u{110bd}', '\u{110cd}'..='\u{110cd}', + '\u{13430}'..='\u{1343f}', '\u{1bca0}'..='\u{1bca3}', '\u{1d173}'..='\u{1d17a}', + '\u{e0001}'..='\u{e0001}', '\u{e0020}'..='\u{e007f}', +]; + +#[rustfmt::skip] +pub(super) static CN_PLANES_0_3: &[RangeInclusive; 730] = &[ + '\u{378}'..='\u{379}', '\u{380}'..='\u{383}', '\u{38b}'..='\u{38b}', '\u{38d}'..='\u{38d}', + '\u{3a2}'..='\u{3a2}', '\u{530}'..='\u{530}', '\u{557}'..='\u{558}', '\u{58b}'..='\u{58c}', + '\u{590}'..='\u{590}', '\u{5c8}'..='\u{5cf}', '\u{5eb}'..='\u{5ee}', '\u{5f5}'..='\u{5ff}', + '\u{70e}'..='\u{70e}', '\u{74b}'..='\u{74c}', '\u{7b2}'..='\u{7bf}', '\u{7fb}'..='\u{7fc}', + '\u{82e}'..='\u{82f}', '\u{83f}'..='\u{83f}', '\u{85c}'..='\u{85d}', '\u{85f}'..='\u{85f}', + '\u{86b}'..='\u{86f}', '\u{892}'..='\u{896}', '\u{984}'..='\u{984}', '\u{98d}'..='\u{98e}', + '\u{991}'..='\u{992}', '\u{9a9}'..='\u{9a9}', '\u{9b1}'..='\u{9b1}', '\u{9b3}'..='\u{9b5}', + '\u{9ba}'..='\u{9bb}', '\u{9c5}'..='\u{9c6}', '\u{9c9}'..='\u{9ca}', '\u{9cf}'..='\u{9d6}', + '\u{9d8}'..='\u{9db}', '\u{9de}'..='\u{9de}', '\u{9e4}'..='\u{9e5}', '\u{9ff}'..='\u{a00}', + '\u{a04}'..='\u{a04}', '\u{a0b}'..='\u{a0e}', '\u{a11}'..='\u{a12}', '\u{a29}'..='\u{a29}', + '\u{a31}'..='\u{a31}', '\u{a34}'..='\u{a34}', '\u{a37}'..='\u{a37}', '\u{a3a}'..='\u{a3b}', + '\u{a3d}'..='\u{a3d}', '\u{a43}'..='\u{a46}', '\u{a49}'..='\u{a4a}', '\u{a4e}'..='\u{a50}', + '\u{a52}'..='\u{a58}', '\u{a5d}'..='\u{a5d}', '\u{a5f}'..='\u{a65}', '\u{a77}'..='\u{a80}', + '\u{a84}'..='\u{a84}', '\u{a8e}'..='\u{a8e}', '\u{a92}'..='\u{a92}', '\u{aa9}'..='\u{aa9}', + '\u{ab1}'..='\u{ab1}', '\u{ab4}'..='\u{ab4}', '\u{aba}'..='\u{abb}', '\u{ac6}'..='\u{ac6}', + '\u{aca}'..='\u{aca}', '\u{ace}'..='\u{acf}', '\u{ad1}'..='\u{adf}', '\u{ae4}'..='\u{ae5}', + '\u{af2}'..='\u{af8}', '\u{b00}'..='\u{b00}', '\u{b04}'..='\u{b04}', '\u{b0d}'..='\u{b0e}', + '\u{b11}'..='\u{b12}', '\u{b29}'..='\u{b29}', '\u{b31}'..='\u{b31}', '\u{b34}'..='\u{b34}', + '\u{b3a}'..='\u{b3b}', '\u{b45}'..='\u{b46}', '\u{b49}'..='\u{b4a}', '\u{b4e}'..='\u{b54}', + '\u{b58}'..='\u{b5b}', '\u{b5e}'..='\u{b5e}', '\u{b64}'..='\u{b65}', '\u{b78}'..='\u{b81}', + '\u{b84}'..='\u{b84}', '\u{b8b}'..='\u{b8d}', '\u{b91}'..='\u{b91}', '\u{b96}'..='\u{b98}', + '\u{b9b}'..='\u{b9b}', '\u{b9d}'..='\u{b9d}', '\u{ba0}'..='\u{ba2}', '\u{ba5}'..='\u{ba7}', + '\u{bab}'..='\u{bad}', '\u{bba}'..='\u{bbd}', '\u{bc3}'..='\u{bc5}', '\u{bc9}'..='\u{bc9}', + '\u{bce}'..='\u{bcf}', '\u{bd1}'..='\u{bd6}', '\u{bd8}'..='\u{be5}', '\u{bfb}'..='\u{bff}', + '\u{c0d}'..='\u{c0d}', '\u{c11}'..='\u{c11}', '\u{c29}'..='\u{c29}', '\u{c3a}'..='\u{c3b}', + '\u{c45}'..='\u{c45}', '\u{c49}'..='\u{c49}', '\u{c4e}'..='\u{c54}', '\u{c57}'..='\u{c57}', + '\u{c5b}'..='\u{c5b}', '\u{c5e}'..='\u{c5f}', '\u{c64}'..='\u{c65}', '\u{c70}'..='\u{c76}', + '\u{c8d}'..='\u{c8d}', '\u{c91}'..='\u{c91}', '\u{ca9}'..='\u{ca9}', '\u{cb4}'..='\u{cb4}', + '\u{cba}'..='\u{cbb}', '\u{cc5}'..='\u{cc5}', '\u{cc9}'..='\u{cc9}', '\u{cce}'..='\u{cd4}', + '\u{cd7}'..='\u{cdb}', '\u{cdf}'..='\u{cdf}', '\u{ce4}'..='\u{ce5}', '\u{cf0}'..='\u{cf0}', + '\u{cf4}'..='\u{cff}', '\u{d0d}'..='\u{d0d}', '\u{d11}'..='\u{d11}', '\u{d45}'..='\u{d45}', + '\u{d49}'..='\u{d49}', '\u{d50}'..='\u{d53}', '\u{d64}'..='\u{d65}', '\u{d80}'..='\u{d80}', + '\u{d84}'..='\u{d84}', '\u{d97}'..='\u{d99}', '\u{db2}'..='\u{db2}', '\u{dbc}'..='\u{dbc}', + '\u{dbe}'..='\u{dbf}', '\u{dc7}'..='\u{dc9}', '\u{dcb}'..='\u{dce}', '\u{dd5}'..='\u{dd5}', + '\u{dd7}'..='\u{dd7}', '\u{de0}'..='\u{de5}', '\u{df0}'..='\u{df1}', '\u{df5}'..='\u{e00}', + '\u{e3b}'..='\u{e3e}', '\u{e5c}'..='\u{e80}', '\u{e83}'..='\u{e83}', '\u{e85}'..='\u{e85}', + '\u{e8b}'..='\u{e8b}', '\u{ea4}'..='\u{ea4}', '\u{ea6}'..='\u{ea6}', '\u{ebe}'..='\u{ebf}', + '\u{ec5}'..='\u{ec5}', '\u{ec7}'..='\u{ec7}', '\u{ecf}'..='\u{ecf}', '\u{eda}'..='\u{edb}', + '\u{ee0}'..='\u{eff}', '\u{f48}'..='\u{f48}', '\u{f6d}'..='\u{f70}', '\u{f98}'..='\u{f98}', + '\u{fbd}'..='\u{fbd}', '\u{fcd}'..='\u{fcd}', '\u{fdb}'..='\u{fff}', + '\u{10c6}'..='\u{10c6}', '\u{10c8}'..='\u{10cc}', '\u{10ce}'..='\u{10cf}', + '\u{1249}'..='\u{1249}', '\u{124e}'..='\u{124f}', '\u{1257}'..='\u{1257}', + '\u{1259}'..='\u{1259}', '\u{125e}'..='\u{125f}', '\u{1289}'..='\u{1289}', + '\u{128e}'..='\u{128f}', '\u{12b1}'..='\u{12b1}', '\u{12b6}'..='\u{12b7}', + '\u{12bf}'..='\u{12bf}', '\u{12c1}'..='\u{12c1}', '\u{12c6}'..='\u{12c7}', + '\u{12d7}'..='\u{12d7}', '\u{1311}'..='\u{1311}', '\u{1316}'..='\u{1317}', + '\u{135b}'..='\u{135c}', '\u{137d}'..='\u{137f}', '\u{139a}'..='\u{139f}', + '\u{13f6}'..='\u{13f7}', '\u{13fe}'..='\u{13ff}', '\u{169d}'..='\u{169f}', + '\u{16f9}'..='\u{16ff}', '\u{1716}'..='\u{171e}', '\u{1737}'..='\u{173f}', + '\u{1754}'..='\u{175f}', '\u{176d}'..='\u{176d}', '\u{1771}'..='\u{1771}', + '\u{1774}'..='\u{177f}', '\u{17de}'..='\u{17df}', '\u{17ea}'..='\u{17ef}', + '\u{17fa}'..='\u{17ff}', '\u{181a}'..='\u{181f}', '\u{1879}'..='\u{187f}', + '\u{18ab}'..='\u{18af}', '\u{18f6}'..='\u{18ff}', '\u{191f}'..='\u{191f}', + '\u{192c}'..='\u{192f}', '\u{193c}'..='\u{193f}', '\u{1941}'..='\u{1943}', + '\u{196e}'..='\u{196f}', '\u{1975}'..='\u{197f}', '\u{19ac}'..='\u{19af}', + '\u{19ca}'..='\u{19cf}', '\u{19db}'..='\u{19dd}', '\u{1a1c}'..='\u{1a1d}', + '\u{1a5f}'..='\u{1a5f}', '\u{1a7d}'..='\u{1a7e}', '\u{1a8a}'..='\u{1a8f}', + '\u{1a9a}'..='\u{1a9f}', '\u{1aae}'..='\u{1aaf}', '\u{1ade}'..='\u{1adf}', + '\u{1aec}'..='\u{1aff}', '\u{1b4d}'..='\u{1b4d}', '\u{1bf4}'..='\u{1bfb}', + '\u{1c38}'..='\u{1c3a}', '\u{1c4a}'..='\u{1c4c}', '\u{1c8b}'..='\u{1c8f}', + '\u{1cbb}'..='\u{1cbc}', '\u{1cc8}'..='\u{1ccf}', '\u{1cfb}'..='\u{1cff}', + '\u{1f16}'..='\u{1f17}', '\u{1f1e}'..='\u{1f1f}', '\u{1f46}'..='\u{1f47}', + '\u{1f4e}'..='\u{1f4f}', '\u{1f58}'..='\u{1f58}', '\u{1f5a}'..='\u{1f5a}', + '\u{1f5c}'..='\u{1f5c}', '\u{1f5e}'..='\u{1f5e}', '\u{1f7e}'..='\u{1f7f}', + '\u{1fb5}'..='\u{1fb5}', '\u{1fc5}'..='\u{1fc5}', '\u{1fd4}'..='\u{1fd5}', + '\u{1fdc}'..='\u{1fdc}', '\u{1ff0}'..='\u{1ff1}', '\u{1ff5}'..='\u{1ff5}', + '\u{1fff}'..='\u{1fff}', '\u{2065}'..='\u{2065}', '\u{2072}'..='\u{2073}', + '\u{208f}'..='\u{208f}', '\u{209d}'..='\u{209f}', '\u{20c2}'..='\u{20cf}', + '\u{20f1}'..='\u{20ff}', '\u{218c}'..='\u{218f}', '\u{242a}'..='\u{243f}', + '\u{244b}'..='\u{245f}', '\u{2b74}'..='\u{2b75}', '\u{2cf4}'..='\u{2cf8}', + '\u{2d26}'..='\u{2d26}', '\u{2d28}'..='\u{2d2c}', '\u{2d2e}'..='\u{2d2f}', + '\u{2d68}'..='\u{2d6e}', '\u{2d71}'..='\u{2d7e}', '\u{2d97}'..='\u{2d9f}', + '\u{2da7}'..='\u{2da7}', '\u{2daf}'..='\u{2daf}', '\u{2db7}'..='\u{2db7}', + '\u{2dbf}'..='\u{2dbf}', '\u{2dc7}'..='\u{2dc7}', '\u{2dcf}'..='\u{2dcf}', + '\u{2dd7}'..='\u{2dd7}', '\u{2ddf}'..='\u{2ddf}', '\u{2e5e}'..='\u{2e7f}', + '\u{2e9a}'..='\u{2e9a}', '\u{2ef4}'..='\u{2eff}', '\u{2fd6}'..='\u{2fef}', + '\u{3040}'..='\u{3040}', '\u{3097}'..='\u{3098}', '\u{3100}'..='\u{3104}', + '\u{3130}'..='\u{3130}', '\u{318f}'..='\u{318f}', '\u{31e6}'..='\u{31ee}', + '\u{321f}'..='\u{321f}', '\u{a48d}'..='\u{a48f}', '\u{a4c7}'..='\u{a4cf}', + '\u{a62c}'..='\u{a63f}', '\u{a6f8}'..='\u{a6ff}', '\u{a7dd}'..='\u{a7f0}', + '\u{a82d}'..='\u{a82f}', '\u{a83a}'..='\u{a83f}', '\u{a878}'..='\u{a87f}', + '\u{a8c6}'..='\u{a8cd}', '\u{a8da}'..='\u{a8df}', '\u{a954}'..='\u{a95e}', + '\u{a97d}'..='\u{a97f}', '\u{a9ce}'..='\u{a9ce}', '\u{a9da}'..='\u{a9dd}', + '\u{a9ff}'..='\u{a9ff}', '\u{aa37}'..='\u{aa3f}', '\u{aa4e}'..='\u{aa4f}', + '\u{aa5a}'..='\u{aa5b}', '\u{aac3}'..='\u{aada}', '\u{aaf7}'..='\u{ab00}', + '\u{ab07}'..='\u{ab08}', '\u{ab0f}'..='\u{ab10}', '\u{ab17}'..='\u{ab1f}', + '\u{ab27}'..='\u{ab27}', '\u{ab2f}'..='\u{ab2f}', '\u{ab6c}'..='\u{ab6f}', + '\u{abee}'..='\u{abef}', '\u{abfa}'..='\u{abff}', '\u{d7a4}'..='\u{d7af}', + '\u{d7c7}'..='\u{d7ca}', '\u{d7fc}'..='\u{d7ff}', '\u{fa6e}'..='\u{fa6f}', + '\u{fada}'..='\u{faff}', '\u{fb07}'..='\u{fb12}', '\u{fb18}'..='\u{fb1c}', + '\u{fb37}'..='\u{fb37}', '\u{fb3d}'..='\u{fb3d}', '\u{fb3f}'..='\u{fb3f}', + '\u{fb42}'..='\u{fb42}', '\u{fb45}'..='\u{fb45}', '\u{fdd0}'..='\u{fdef}', + '\u{fe1a}'..='\u{fe1f}', '\u{fe53}'..='\u{fe53}', '\u{fe67}'..='\u{fe67}', + '\u{fe6c}'..='\u{fe6f}', '\u{fe75}'..='\u{fe75}', '\u{fefd}'..='\u{fefe}', + '\u{ff00}'..='\u{ff00}', '\u{ffbf}'..='\u{ffc1}', '\u{ffc8}'..='\u{ffc9}', + '\u{ffd0}'..='\u{ffd1}', '\u{ffd8}'..='\u{ffd9}', '\u{ffdd}'..='\u{ffdf}', + '\u{ffe7}'..='\u{ffe7}', '\u{ffef}'..='\u{fff8}', '\u{fffe}'..='\u{ffff}', + '\u{1000c}'..='\u{1000c}', '\u{10027}'..='\u{10027}', '\u{1003b}'..='\u{1003b}', + '\u{1003e}'..='\u{1003e}', '\u{1004e}'..='\u{1004f}', '\u{1005e}'..='\u{1007f}', + '\u{100fb}'..='\u{100ff}', '\u{10103}'..='\u{10106}', '\u{10134}'..='\u{10136}', + '\u{1018f}'..='\u{1018f}', '\u{1019d}'..='\u{1019f}', '\u{101a1}'..='\u{101cf}', + '\u{101fe}'..='\u{1027f}', '\u{1029d}'..='\u{1029f}', '\u{102d1}'..='\u{102df}', + '\u{102fc}'..='\u{102ff}', '\u{10324}'..='\u{1032c}', '\u{1034b}'..='\u{1034f}', + '\u{1037b}'..='\u{1037f}', '\u{1039e}'..='\u{1039e}', '\u{103c4}'..='\u{103c7}', + '\u{103d6}'..='\u{103ff}', '\u{1049e}'..='\u{1049f}', '\u{104aa}'..='\u{104af}', + '\u{104d4}'..='\u{104d7}', '\u{104fc}'..='\u{104ff}', '\u{10528}'..='\u{1052f}', + '\u{10564}'..='\u{1056e}', '\u{1057b}'..='\u{1057b}', '\u{1058b}'..='\u{1058b}', + '\u{10593}'..='\u{10593}', '\u{10596}'..='\u{10596}', '\u{105a2}'..='\u{105a2}', + '\u{105b2}'..='\u{105b2}', '\u{105ba}'..='\u{105ba}', '\u{105bd}'..='\u{105bf}', + '\u{105f4}'..='\u{105ff}', '\u{10737}'..='\u{1073f}', '\u{10756}'..='\u{1075f}', + '\u{10768}'..='\u{1077f}', '\u{10786}'..='\u{10786}', '\u{107b1}'..='\u{107b1}', + '\u{107bb}'..='\u{107ff}', '\u{10806}'..='\u{10807}', '\u{10809}'..='\u{10809}', + '\u{10836}'..='\u{10836}', '\u{10839}'..='\u{1083b}', '\u{1083d}'..='\u{1083e}', + '\u{10856}'..='\u{10856}', '\u{1089f}'..='\u{108a6}', '\u{108b0}'..='\u{108df}', + '\u{108f3}'..='\u{108f3}', '\u{108f6}'..='\u{108fa}', '\u{1091c}'..='\u{1091e}', + '\u{1093a}'..='\u{1093e}', '\u{1095a}'..='\u{1097f}', '\u{109b8}'..='\u{109bb}', + '\u{109d0}'..='\u{109d1}', '\u{10a04}'..='\u{10a04}', '\u{10a07}'..='\u{10a0b}', + '\u{10a14}'..='\u{10a14}', '\u{10a18}'..='\u{10a18}', '\u{10a36}'..='\u{10a37}', + '\u{10a3b}'..='\u{10a3e}', '\u{10a49}'..='\u{10a4f}', '\u{10a59}'..='\u{10a5f}', + '\u{10aa0}'..='\u{10abf}', '\u{10ae7}'..='\u{10aea}', '\u{10af7}'..='\u{10aff}', + '\u{10b36}'..='\u{10b38}', '\u{10b56}'..='\u{10b57}', '\u{10b73}'..='\u{10b77}', + '\u{10b92}'..='\u{10b98}', '\u{10b9d}'..='\u{10ba8}', '\u{10bb0}'..='\u{10bff}', + '\u{10c49}'..='\u{10c7f}', '\u{10cb3}'..='\u{10cbf}', '\u{10cf3}'..='\u{10cf9}', + '\u{10d28}'..='\u{10d2f}', '\u{10d3a}'..='\u{10d3f}', '\u{10d66}'..='\u{10d68}', + '\u{10d86}'..='\u{10d8d}', '\u{10d90}'..='\u{10e5f}', '\u{10e7f}'..='\u{10e7f}', + '\u{10eaa}'..='\u{10eaa}', '\u{10eae}'..='\u{10eaf}', '\u{10eb2}'..='\u{10ec1}', + '\u{10ec8}'..='\u{10ecf}', '\u{10ed9}'..='\u{10ef9}', '\u{10f28}'..='\u{10f2f}', + '\u{10f5a}'..='\u{10f6f}', '\u{10f8a}'..='\u{10faf}', '\u{10fcc}'..='\u{10fdf}', + '\u{10ff7}'..='\u{10fff}', '\u{1104e}'..='\u{11051}', '\u{11076}'..='\u{1107e}', + '\u{110c3}'..='\u{110cc}', '\u{110ce}'..='\u{110cf}', '\u{110e9}'..='\u{110ef}', + '\u{110fa}'..='\u{110ff}', '\u{11135}'..='\u{11135}', '\u{11148}'..='\u{1114f}', + '\u{11177}'..='\u{1117f}', '\u{111e0}'..='\u{111e0}', '\u{111f5}'..='\u{111ff}', + '\u{11212}'..='\u{11212}', '\u{11242}'..='\u{1127f}', '\u{11287}'..='\u{11287}', + '\u{11289}'..='\u{11289}', '\u{1128e}'..='\u{1128e}', '\u{1129e}'..='\u{1129e}', + '\u{112aa}'..='\u{112af}', '\u{112eb}'..='\u{112ef}', '\u{112fa}'..='\u{112ff}', + '\u{11304}'..='\u{11304}', '\u{1130d}'..='\u{1130e}', '\u{11311}'..='\u{11312}', + '\u{11329}'..='\u{11329}', '\u{11331}'..='\u{11331}', '\u{11334}'..='\u{11334}', + '\u{1133a}'..='\u{1133a}', '\u{11345}'..='\u{11346}', '\u{11349}'..='\u{1134a}', + '\u{1134e}'..='\u{1134f}', '\u{11351}'..='\u{11356}', '\u{11358}'..='\u{1135c}', + '\u{11364}'..='\u{11365}', '\u{1136d}'..='\u{1136f}', '\u{11375}'..='\u{1137f}', + '\u{1138a}'..='\u{1138a}', '\u{1138c}'..='\u{1138d}', '\u{1138f}'..='\u{1138f}', + '\u{113b6}'..='\u{113b6}', '\u{113c1}'..='\u{113c1}', '\u{113c3}'..='\u{113c4}', + '\u{113c6}'..='\u{113c6}', '\u{113cb}'..='\u{113cb}', '\u{113d6}'..='\u{113d6}', + '\u{113d9}'..='\u{113e0}', '\u{113e3}'..='\u{113ff}', '\u{1145c}'..='\u{1145c}', + '\u{11462}'..='\u{1147f}', '\u{114c8}'..='\u{114cf}', '\u{114da}'..='\u{1157f}', + '\u{115b6}'..='\u{115b7}', '\u{115de}'..='\u{115ff}', '\u{11645}'..='\u{1164f}', + '\u{1165a}'..='\u{1165f}', '\u{1166d}'..='\u{1167f}', '\u{116ba}'..='\u{116bf}', + '\u{116ca}'..='\u{116cf}', '\u{116e4}'..='\u{116ff}', '\u{1171b}'..='\u{1171c}', + '\u{1172c}'..='\u{1172f}', '\u{11747}'..='\u{117ff}', '\u{1183c}'..='\u{1189f}', + '\u{118f3}'..='\u{118fe}', '\u{11907}'..='\u{11908}', '\u{1190a}'..='\u{1190b}', + '\u{11914}'..='\u{11914}', '\u{11917}'..='\u{11917}', '\u{11936}'..='\u{11936}', + '\u{11939}'..='\u{1193a}', '\u{11947}'..='\u{1194f}', '\u{1195a}'..='\u{1199f}', + '\u{119a8}'..='\u{119a9}', '\u{119d8}'..='\u{119d9}', '\u{119e5}'..='\u{119ff}', + '\u{11a48}'..='\u{11a4f}', '\u{11aa3}'..='\u{11aaf}', '\u{11af9}'..='\u{11aff}', + '\u{11b0a}'..='\u{11b5f}', '\u{11b68}'..='\u{11bbf}', '\u{11be2}'..='\u{11bef}', + '\u{11bfa}'..='\u{11bff}', '\u{11c09}'..='\u{11c09}', '\u{11c37}'..='\u{11c37}', + '\u{11c46}'..='\u{11c4f}', '\u{11c6d}'..='\u{11c6f}', '\u{11c90}'..='\u{11c91}', + '\u{11ca8}'..='\u{11ca8}', '\u{11cb7}'..='\u{11cff}', '\u{11d07}'..='\u{11d07}', + '\u{11d0a}'..='\u{11d0a}', '\u{11d37}'..='\u{11d39}', '\u{11d3b}'..='\u{11d3b}', + '\u{11d3e}'..='\u{11d3e}', '\u{11d48}'..='\u{11d4f}', '\u{11d5a}'..='\u{11d5f}', + '\u{11d66}'..='\u{11d66}', '\u{11d69}'..='\u{11d69}', '\u{11d8f}'..='\u{11d8f}', + '\u{11d92}'..='\u{11d92}', '\u{11d99}'..='\u{11d9f}', '\u{11daa}'..='\u{11daf}', + '\u{11ddc}'..='\u{11ddf}', '\u{11dea}'..='\u{11edf}', '\u{11ef9}'..='\u{11eff}', + '\u{11f11}'..='\u{11f11}', '\u{11f3b}'..='\u{11f3d}', '\u{11f5b}'..='\u{11faf}', + '\u{11fb1}'..='\u{11fbf}', '\u{11ff2}'..='\u{11ffe}', '\u{1239a}'..='\u{123ff}', + '\u{1246f}'..='\u{1246f}', '\u{12475}'..='\u{1247f}', '\u{12544}'..='\u{12f8f}', + '\u{12ff3}'..='\u{12fff}', '\u{13456}'..='\u{1345f}', '\u{143fb}'..='\u{143ff}', + '\u{14647}'..='\u{160ff}', '\u{1613a}'..='\u{167ff}', '\u{16a39}'..='\u{16a3f}', + '\u{16a5f}'..='\u{16a5f}', '\u{16a6a}'..='\u{16a6d}', '\u{16abf}'..='\u{16abf}', + '\u{16aca}'..='\u{16acf}', '\u{16aee}'..='\u{16aef}', '\u{16af6}'..='\u{16aff}', + '\u{16b46}'..='\u{16b4f}', '\u{16b5a}'..='\u{16b5a}', '\u{16b62}'..='\u{16b62}', + '\u{16b78}'..='\u{16b7c}', '\u{16b90}'..='\u{16d3f}', '\u{16d7a}'..='\u{16e3f}', + '\u{16e9b}'..='\u{16e9f}', '\u{16eb9}'..='\u{16eba}', '\u{16ed4}'..='\u{16eff}', + '\u{16f4b}'..='\u{16f4e}', '\u{16f88}'..='\u{16f8e}', '\u{16fa0}'..='\u{16fdf}', + '\u{16fe5}'..='\u{16fef}', '\u{16ff7}'..='\u{16fff}', '\u{18cd6}'..='\u{18cfe}', + '\u{18d1f}'..='\u{18d7f}', '\u{18df3}'..='\u{1afef}', '\u{1aff4}'..='\u{1aff4}', + '\u{1affc}'..='\u{1affc}', '\u{1afff}'..='\u{1afff}', '\u{1b123}'..='\u{1b131}', + '\u{1b133}'..='\u{1b14f}', '\u{1b153}'..='\u{1b154}', '\u{1b156}'..='\u{1b163}', + '\u{1b168}'..='\u{1b16f}', '\u{1b2fc}'..='\u{1bbff}', '\u{1bc6b}'..='\u{1bc6f}', + '\u{1bc7d}'..='\u{1bc7f}', '\u{1bc89}'..='\u{1bc8f}', '\u{1bc9a}'..='\u{1bc9b}', + '\u{1bca4}'..='\u{1cbff}', '\u{1ccfd}'..='\u{1ccff}', '\u{1ceb4}'..='\u{1ceb9}', + '\u{1ced1}'..='\u{1cedf}', '\u{1cef1}'..='\u{1ceff}', '\u{1cf2e}'..='\u{1cf2f}', + '\u{1cf47}'..='\u{1cf4f}', '\u{1cfc4}'..='\u{1cfff}', '\u{1d0f6}'..='\u{1d0ff}', + '\u{1d127}'..='\u{1d128}', '\u{1d1eb}'..='\u{1d1ff}', '\u{1d246}'..='\u{1d2bf}', + '\u{1d2d4}'..='\u{1d2df}', '\u{1d2f4}'..='\u{1d2ff}', '\u{1d357}'..='\u{1d35f}', + '\u{1d379}'..='\u{1d3ff}', '\u{1d455}'..='\u{1d455}', '\u{1d49d}'..='\u{1d49d}', + '\u{1d4a0}'..='\u{1d4a1}', '\u{1d4a3}'..='\u{1d4a4}', '\u{1d4a7}'..='\u{1d4a8}', + '\u{1d4ad}'..='\u{1d4ad}', '\u{1d4ba}'..='\u{1d4ba}', '\u{1d4bc}'..='\u{1d4bc}', + '\u{1d4c4}'..='\u{1d4c4}', '\u{1d506}'..='\u{1d506}', '\u{1d50b}'..='\u{1d50c}', + '\u{1d515}'..='\u{1d515}', '\u{1d51d}'..='\u{1d51d}', '\u{1d53a}'..='\u{1d53a}', + '\u{1d53f}'..='\u{1d53f}', '\u{1d545}'..='\u{1d545}', '\u{1d547}'..='\u{1d549}', + '\u{1d551}'..='\u{1d551}', '\u{1d6a6}'..='\u{1d6a7}', '\u{1d7cc}'..='\u{1d7cd}', + '\u{1da8c}'..='\u{1da9a}', '\u{1daa0}'..='\u{1daa0}', '\u{1dab0}'..='\u{1deff}', + '\u{1df1f}'..='\u{1df24}', '\u{1df2b}'..='\u{1dfff}', '\u{1e007}'..='\u{1e007}', + '\u{1e019}'..='\u{1e01a}', '\u{1e022}'..='\u{1e022}', '\u{1e025}'..='\u{1e025}', + '\u{1e02b}'..='\u{1e02f}', '\u{1e06e}'..='\u{1e08e}', '\u{1e090}'..='\u{1e0ff}', + '\u{1e12d}'..='\u{1e12f}', '\u{1e13e}'..='\u{1e13f}', '\u{1e14a}'..='\u{1e14d}', + '\u{1e150}'..='\u{1e28f}', '\u{1e2af}'..='\u{1e2bf}', '\u{1e2fa}'..='\u{1e2fe}', + '\u{1e300}'..='\u{1e4cf}', '\u{1e4fa}'..='\u{1e5cf}', '\u{1e5fb}'..='\u{1e5fe}', + '\u{1e600}'..='\u{1e6bf}', '\u{1e6df}'..='\u{1e6df}', '\u{1e6f6}'..='\u{1e6fd}', + '\u{1e700}'..='\u{1e7df}', '\u{1e7e7}'..='\u{1e7e7}', '\u{1e7ec}'..='\u{1e7ec}', + '\u{1e7ef}'..='\u{1e7ef}', '\u{1e7ff}'..='\u{1e7ff}', '\u{1e8c5}'..='\u{1e8c6}', + '\u{1e8d7}'..='\u{1e8ff}', '\u{1e94c}'..='\u{1e94f}', '\u{1e95a}'..='\u{1e95d}', + '\u{1e960}'..='\u{1ec70}', '\u{1ecb5}'..='\u{1ed00}', '\u{1ed3e}'..='\u{1edff}', + '\u{1ee04}'..='\u{1ee04}', '\u{1ee20}'..='\u{1ee20}', '\u{1ee23}'..='\u{1ee23}', + '\u{1ee25}'..='\u{1ee26}', '\u{1ee28}'..='\u{1ee28}', '\u{1ee33}'..='\u{1ee33}', + '\u{1ee38}'..='\u{1ee38}', '\u{1ee3a}'..='\u{1ee3a}', '\u{1ee3c}'..='\u{1ee41}', + '\u{1ee43}'..='\u{1ee46}', '\u{1ee48}'..='\u{1ee48}', '\u{1ee4a}'..='\u{1ee4a}', + '\u{1ee4c}'..='\u{1ee4c}', '\u{1ee50}'..='\u{1ee50}', '\u{1ee53}'..='\u{1ee53}', + '\u{1ee55}'..='\u{1ee56}', '\u{1ee58}'..='\u{1ee58}', '\u{1ee5a}'..='\u{1ee5a}', + '\u{1ee5c}'..='\u{1ee5c}', '\u{1ee5e}'..='\u{1ee5e}', '\u{1ee60}'..='\u{1ee60}', + '\u{1ee63}'..='\u{1ee63}', '\u{1ee65}'..='\u{1ee66}', '\u{1ee6b}'..='\u{1ee6b}', + '\u{1ee73}'..='\u{1ee73}', '\u{1ee78}'..='\u{1ee78}', '\u{1ee7d}'..='\u{1ee7d}', + '\u{1ee7f}'..='\u{1ee7f}', '\u{1ee8a}'..='\u{1ee8a}', '\u{1ee9c}'..='\u{1eea0}', + '\u{1eea4}'..='\u{1eea4}', '\u{1eeaa}'..='\u{1eeaa}', '\u{1eebc}'..='\u{1eeef}', + '\u{1eef2}'..='\u{1efff}', '\u{1f02c}'..='\u{1f02f}', '\u{1f094}'..='\u{1f09f}', + '\u{1f0af}'..='\u{1f0b0}', '\u{1f0c0}'..='\u{1f0c0}', '\u{1f0d0}'..='\u{1f0d0}', + '\u{1f0f6}'..='\u{1f0ff}', '\u{1f1ae}'..='\u{1f1e5}', '\u{1f203}'..='\u{1f20f}', + '\u{1f23c}'..='\u{1f23f}', '\u{1f249}'..='\u{1f24f}', '\u{1f252}'..='\u{1f25f}', + '\u{1f266}'..='\u{1f2ff}', '\u{1f6d9}'..='\u{1f6db}', '\u{1f6ed}'..='\u{1f6ef}', + '\u{1f6fd}'..='\u{1f6ff}', '\u{1f7da}'..='\u{1f7df}', '\u{1f7ec}'..='\u{1f7ef}', + '\u{1f7f1}'..='\u{1f7ff}', '\u{1f80c}'..='\u{1f80f}', '\u{1f848}'..='\u{1f84f}', + '\u{1f85a}'..='\u{1f85f}', '\u{1f888}'..='\u{1f88f}', '\u{1f8ae}'..='\u{1f8af}', + '\u{1f8bc}'..='\u{1f8bf}', '\u{1f8c2}'..='\u{1f8cf}', '\u{1f8d9}'..='\u{1f8ff}', + '\u{1fa58}'..='\u{1fa5f}', '\u{1fa6e}'..='\u{1fa6f}', '\u{1fa7d}'..='\u{1fa7f}', + '\u{1fa8b}'..='\u{1fa8d}', '\u{1fac7}'..='\u{1fac7}', '\u{1fac9}'..='\u{1facc}', + '\u{1fadd}'..='\u{1fade}', '\u{1faeb}'..='\u{1faee}', '\u{1faf9}'..='\u{1faff}', + '\u{1fb93}'..='\u{1fb93}', '\u{1fbfb}'..='\u{1ffff}', '\u{2a6e0}'..='\u{2a6ff}', + '\u{2b81e}'..='\u{2b81f}', '\u{2ceae}'..='\u{2ceaf}', '\u{2ebe1}'..='\u{2ebef}', + '\u{2ee5e}'..='\u{2f7ff}', '\u{2fa1e}'..='\u{2ffff}', '\u{3134b}'..='\u{3134f}', + '\u{3347a}'..='\u{3fffd}', +]; + +#[rustfmt::skip] +pub(super) static DEFAULT_IGNORABLE_CODE_POINT: &[RangeInclusive; 17] = &[ + '\u{ad}'..='\u{ad}', '\u{34f}'..='\u{34f}', '\u{61c}'..='\u{61c}', '\u{115f}'..='\u{1160}', + '\u{17b4}'..='\u{17b5}', '\u{180b}'..='\u{180f}', '\u{200b}'..='\u{200f}', + '\u{202a}'..='\u{202e}', '\u{2060}'..='\u{206f}', '\u{3164}'..='\u{3164}', + '\u{fe00}'..='\u{fe0f}', '\u{feff}'..='\u{feff}', '\u{ffa0}'..='\u{ffa0}', + '\u{fff0}'..='\u{fff8}', '\u{1bca0}'..='\u{1bca3}', '\u{1d173}'..='\u{1d17a}', + '\u{e0000}'..='\u{e0fff}', +]; + +#[rustfmt::skip] +pub(super) static GRAPHEME_EXTEND: &[RangeInclusive; 383] = &[ + '\u{300}'..='\u{36f}', '\u{483}'..='\u{489}', '\u{591}'..='\u{5bd}', '\u{5bf}'..='\u{5bf}', + '\u{5c1}'..='\u{5c2}', '\u{5c4}'..='\u{5c5}', '\u{5c7}'..='\u{5c7}', '\u{610}'..='\u{61a}', + '\u{64b}'..='\u{65f}', '\u{670}'..='\u{670}', '\u{6d6}'..='\u{6dc}', '\u{6df}'..='\u{6e4}', + '\u{6e7}'..='\u{6e8}', '\u{6ea}'..='\u{6ed}', '\u{711}'..='\u{711}', '\u{730}'..='\u{74a}', + '\u{7a6}'..='\u{7b0}', '\u{7eb}'..='\u{7f3}', '\u{7fd}'..='\u{7fd}', '\u{816}'..='\u{819}', + '\u{81b}'..='\u{823}', '\u{825}'..='\u{827}', '\u{829}'..='\u{82d}', '\u{859}'..='\u{85b}', + '\u{897}'..='\u{89f}', '\u{8ca}'..='\u{8e1}', '\u{8e3}'..='\u{902}', '\u{93a}'..='\u{93a}', + '\u{93c}'..='\u{93c}', '\u{941}'..='\u{948}', '\u{94d}'..='\u{94d}', '\u{951}'..='\u{957}', + '\u{962}'..='\u{963}', '\u{981}'..='\u{981}', '\u{9bc}'..='\u{9bc}', '\u{9be}'..='\u{9be}', + '\u{9c1}'..='\u{9c4}', '\u{9cd}'..='\u{9cd}', '\u{9d7}'..='\u{9d7}', '\u{9e2}'..='\u{9e3}', + '\u{9fe}'..='\u{9fe}', '\u{a01}'..='\u{a02}', '\u{a3c}'..='\u{a3c}', '\u{a41}'..='\u{a42}', + '\u{a47}'..='\u{a48}', '\u{a4b}'..='\u{a4d}', '\u{a51}'..='\u{a51}', '\u{a70}'..='\u{a71}', + '\u{a75}'..='\u{a75}', '\u{a81}'..='\u{a82}', '\u{abc}'..='\u{abc}', '\u{ac1}'..='\u{ac5}', + '\u{ac7}'..='\u{ac8}', '\u{acd}'..='\u{acd}', '\u{ae2}'..='\u{ae3}', '\u{afa}'..='\u{aff}', + '\u{b01}'..='\u{b01}', '\u{b3c}'..='\u{b3c}', '\u{b3e}'..='\u{b3f}', '\u{b41}'..='\u{b44}', + '\u{b4d}'..='\u{b4d}', '\u{b55}'..='\u{b57}', '\u{b62}'..='\u{b63}', '\u{b82}'..='\u{b82}', + '\u{bbe}'..='\u{bbe}', '\u{bc0}'..='\u{bc0}', '\u{bcd}'..='\u{bcd}', '\u{bd7}'..='\u{bd7}', + '\u{c00}'..='\u{c00}', '\u{c04}'..='\u{c04}', '\u{c3c}'..='\u{c3c}', '\u{c3e}'..='\u{c40}', + '\u{c46}'..='\u{c48}', '\u{c4a}'..='\u{c4d}', '\u{c55}'..='\u{c56}', '\u{c62}'..='\u{c63}', + '\u{c81}'..='\u{c81}', '\u{cbc}'..='\u{cbc}', '\u{cbf}'..='\u{cc0}', '\u{cc2}'..='\u{cc2}', + '\u{cc6}'..='\u{cc8}', '\u{cca}'..='\u{ccd}', '\u{cd5}'..='\u{cd6}', '\u{ce2}'..='\u{ce3}', + '\u{d00}'..='\u{d01}', '\u{d3b}'..='\u{d3c}', '\u{d3e}'..='\u{d3e}', '\u{d41}'..='\u{d44}', + '\u{d4d}'..='\u{d4d}', '\u{d57}'..='\u{d57}', '\u{d62}'..='\u{d63}', '\u{d81}'..='\u{d81}', + '\u{dca}'..='\u{dca}', '\u{dcf}'..='\u{dcf}', '\u{dd2}'..='\u{dd4}', '\u{dd6}'..='\u{dd6}', + '\u{ddf}'..='\u{ddf}', '\u{e31}'..='\u{e31}', '\u{e34}'..='\u{e3a}', '\u{e47}'..='\u{e4e}', + '\u{eb1}'..='\u{eb1}', '\u{eb4}'..='\u{ebc}', '\u{ec8}'..='\u{ece}', '\u{f18}'..='\u{f19}', + '\u{f35}'..='\u{f35}', '\u{f37}'..='\u{f37}', '\u{f39}'..='\u{f39}', '\u{f71}'..='\u{f7e}', + '\u{f80}'..='\u{f84}', '\u{f86}'..='\u{f87}', '\u{f8d}'..='\u{f97}', '\u{f99}'..='\u{fbc}', + '\u{fc6}'..='\u{fc6}', '\u{102d}'..='\u{1030}', '\u{1032}'..='\u{1037}', + '\u{1039}'..='\u{103a}', '\u{103d}'..='\u{103e}', '\u{1058}'..='\u{1059}', + '\u{105e}'..='\u{1060}', '\u{1071}'..='\u{1074}', '\u{1082}'..='\u{1082}', + '\u{1085}'..='\u{1086}', '\u{108d}'..='\u{108d}', '\u{109d}'..='\u{109d}', + '\u{135d}'..='\u{135f}', '\u{1712}'..='\u{1715}', '\u{1732}'..='\u{1734}', + '\u{1752}'..='\u{1753}', '\u{1772}'..='\u{1773}', '\u{17b4}'..='\u{17b5}', + '\u{17b7}'..='\u{17bd}', '\u{17c6}'..='\u{17c6}', '\u{17c9}'..='\u{17d3}', + '\u{17dd}'..='\u{17dd}', '\u{180b}'..='\u{180d}', '\u{180f}'..='\u{180f}', + '\u{1885}'..='\u{1886}', '\u{18a9}'..='\u{18a9}', '\u{1920}'..='\u{1922}', + '\u{1927}'..='\u{1928}', '\u{1932}'..='\u{1932}', '\u{1939}'..='\u{193b}', + '\u{1a17}'..='\u{1a18}', '\u{1a1b}'..='\u{1a1b}', '\u{1a56}'..='\u{1a56}', + '\u{1a58}'..='\u{1a5e}', '\u{1a60}'..='\u{1a60}', '\u{1a62}'..='\u{1a62}', + '\u{1a65}'..='\u{1a6c}', '\u{1a73}'..='\u{1a7c}', '\u{1a7f}'..='\u{1a7f}', + '\u{1ab0}'..='\u{1add}', '\u{1ae0}'..='\u{1aeb}', '\u{1b00}'..='\u{1b03}', + '\u{1b34}'..='\u{1b3d}', '\u{1b42}'..='\u{1b44}', '\u{1b6b}'..='\u{1b73}', + '\u{1b80}'..='\u{1b81}', '\u{1ba2}'..='\u{1ba5}', '\u{1ba8}'..='\u{1bad}', + '\u{1be6}'..='\u{1be6}', '\u{1be8}'..='\u{1be9}', '\u{1bed}'..='\u{1bed}', + '\u{1bef}'..='\u{1bf3}', '\u{1c2c}'..='\u{1c33}', '\u{1c36}'..='\u{1c37}', + '\u{1cd0}'..='\u{1cd2}', '\u{1cd4}'..='\u{1ce0}', '\u{1ce2}'..='\u{1ce8}', + '\u{1ced}'..='\u{1ced}', '\u{1cf4}'..='\u{1cf4}', '\u{1cf8}'..='\u{1cf9}', + '\u{1dc0}'..='\u{1dff}', '\u{200c}'..='\u{200c}', '\u{20d0}'..='\u{20f0}', + '\u{2cef}'..='\u{2cf1}', '\u{2d7f}'..='\u{2d7f}', '\u{2de0}'..='\u{2dff}', + '\u{302a}'..='\u{302f}', '\u{3099}'..='\u{309a}', '\u{a66f}'..='\u{a672}', + '\u{a674}'..='\u{a67d}', '\u{a69e}'..='\u{a69f}', '\u{a6f0}'..='\u{a6f1}', + '\u{a802}'..='\u{a802}', '\u{a806}'..='\u{a806}', '\u{a80b}'..='\u{a80b}', + '\u{a825}'..='\u{a826}', '\u{a82c}'..='\u{a82c}', '\u{a8c4}'..='\u{a8c5}', + '\u{a8e0}'..='\u{a8f1}', '\u{a8ff}'..='\u{a8ff}', '\u{a926}'..='\u{a92d}', + '\u{a947}'..='\u{a951}', '\u{a953}'..='\u{a953}', '\u{a980}'..='\u{a982}', + '\u{a9b3}'..='\u{a9b3}', '\u{a9b6}'..='\u{a9b9}', '\u{a9bc}'..='\u{a9bd}', + '\u{a9c0}'..='\u{a9c0}', '\u{a9e5}'..='\u{a9e5}', '\u{aa29}'..='\u{aa2e}', + '\u{aa31}'..='\u{aa32}', '\u{aa35}'..='\u{aa36}', '\u{aa43}'..='\u{aa43}', + '\u{aa4c}'..='\u{aa4c}', '\u{aa7c}'..='\u{aa7c}', '\u{aab0}'..='\u{aab0}', + '\u{aab2}'..='\u{aab4}', '\u{aab7}'..='\u{aab8}', '\u{aabe}'..='\u{aabf}', + '\u{aac1}'..='\u{aac1}', '\u{aaec}'..='\u{aaed}', '\u{aaf6}'..='\u{aaf6}', + '\u{abe5}'..='\u{abe5}', '\u{abe8}'..='\u{abe8}', '\u{abed}'..='\u{abed}', + '\u{fb1e}'..='\u{fb1e}', '\u{fe00}'..='\u{fe0f}', '\u{fe20}'..='\u{fe2f}', + '\u{ff9e}'..='\u{ff9f}', '\u{101fd}'..='\u{101fd}', '\u{102e0}'..='\u{102e0}', + '\u{10376}'..='\u{1037a}', '\u{10a01}'..='\u{10a03}', '\u{10a05}'..='\u{10a06}', + '\u{10a0c}'..='\u{10a0f}', '\u{10a38}'..='\u{10a3a}', '\u{10a3f}'..='\u{10a3f}', + '\u{10ae5}'..='\u{10ae6}', '\u{10d24}'..='\u{10d27}', '\u{10d69}'..='\u{10d6d}', + '\u{10eab}'..='\u{10eac}', '\u{10efa}'..='\u{10eff}', '\u{10f46}'..='\u{10f50}', + '\u{10f82}'..='\u{10f85}', '\u{11001}'..='\u{11001}', '\u{11038}'..='\u{11046}', + '\u{11070}'..='\u{11070}', '\u{11073}'..='\u{11074}', '\u{1107f}'..='\u{11081}', + '\u{110b3}'..='\u{110b6}', '\u{110b9}'..='\u{110ba}', '\u{110c2}'..='\u{110c2}', + '\u{11100}'..='\u{11102}', '\u{11127}'..='\u{1112b}', '\u{1112d}'..='\u{11134}', + '\u{11173}'..='\u{11173}', '\u{11180}'..='\u{11181}', '\u{111b6}'..='\u{111be}', + '\u{111c0}'..='\u{111c0}', '\u{111c9}'..='\u{111cc}', '\u{111cf}'..='\u{111cf}', + '\u{1122f}'..='\u{11231}', '\u{11234}'..='\u{11237}', '\u{1123e}'..='\u{1123e}', + '\u{11241}'..='\u{11241}', '\u{112df}'..='\u{112df}', '\u{112e3}'..='\u{112ea}', + '\u{11300}'..='\u{11301}', '\u{1133b}'..='\u{1133c}', '\u{1133e}'..='\u{1133e}', + '\u{11340}'..='\u{11340}', '\u{1134d}'..='\u{1134d}', '\u{11357}'..='\u{11357}', + '\u{11366}'..='\u{1136c}', '\u{11370}'..='\u{11374}', '\u{113b8}'..='\u{113b8}', + '\u{113bb}'..='\u{113c0}', '\u{113c2}'..='\u{113c2}', '\u{113c5}'..='\u{113c5}', + '\u{113c7}'..='\u{113c9}', '\u{113ce}'..='\u{113d0}', '\u{113d2}'..='\u{113d2}', + '\u{113e1}'..='\u{113e2}', '\u{11438}'..='\u{1143f}', '\u{11442}'..='\u{11444}', + '\u{11446}'..='\u{11446}', '\u{1145e}'..='\u{1145e}', '\u{114b0}'..='\u{114b0}', + '\u{114b3}'..='\u{114b8}', '\u{114ba}'..='\u{114ba}', '\u{114bd}'..='\u{114bd}', + '\u{114bf}'..='\u{114c0}', '\u{114c2}'..='\u{114c3}', '\u{115af}'..='\u{115af}', + '\u{115b2}'..='\u{115b5}', '\u{115bc}'..='\u{115bd}', '\u{115bf}'..='\u{115c0}', + '\u{115dc}'..='\u{115dd}', '\u{11633}'..='\u{1163a}', '\u{1163d}'..='\u{1163d}', + '\u{1163f}'..='\u{11640}', '\u{116ab}'..='\u{116ab}', '\u{116ad}'..='\u{116ad}', + '\u{116b0}'..='\u{116b7}', '\u{1171d}'..='\u{1171d}', '\u{1171f}'..='\u{1171f}', + '\u{11722}'..='\u{11725}', '\u{11727}'..='\u{1172b}', '\u{1182f}'..='\u{11837}', + '\u{11839}'..='\u{1183a}', '\u{11930}'..='\u{11930}', '\u{1193b}'..='\u{1193e}', + '\u{11943}'..='\u{11943}', '\u{119d4}'..='\u{119d7}', '\u{119da}'..='\u{119db}', + '\u{119e0}'..='\u{119e0}', '\u{11a01}'..='\u{11a0a}', '\u{11a33}'..='\u{11a38}', + '\u{11a3b}'..='\u{11a3e}', '\u{11a47}'..='\u{11a47}', '\u{11a51}'..='\u{11a56}', + '\u{11a59}'..='\u{11a5b}', '\u{11a8a}'..='\u{11a96}', '\u{11a98}'..='\u{11a99}', + '\u{11b60}'..='\u{11b60}', '\u{11b62}'..='\u{11b64}', '\u{11b66}'..='\u{11b66}', + '\u{11c30}'..='\u{11c36}', '\u{11c38}'..='\u{11c3d}', '\u{11c3f}'..='\u{11c3f}', + '\u{11c92}'..='\u{11ca7}', '\u{11caa}'..='\u{11cb0}', '\u{11cb2}'..='\u{11cb3}', + '\u{11cb5}'..='\u{11cb6}', '\u{11d31}'..='\u{11d36}', '\u{11d3a}'..='\u{11d3a}', + '\u{11d3c}'..='\u{11d3d}', '\u{11d3f}'..='\u{11d45}', '\u{11d47}'..='\u{11d47}', + '\u{11d90}'..='\u{11d91}', '\u{11d95}'..='\u{11d95}', '\u{11d97}'..='\u{11d97}', + '\u{11ef3}'..='\u{11ef4}', '\u{11f00}'..='\u{11f01}', '\u{11f36}'..='\u{11f3a}', + '\u{11f40}'..='\u{11f42}', '\u{11f5a}'..='\u{11f5a}', '\u{13440}'..='\u{13440}', + '\u{13447}'..='\u{13455}', '\u{1611e}'..='\u{16129}', '\u{1612d}'..='\u{1612f}', + '\u{16af0}'..='\u{16af4}', '\u{16b30}'..='\u{16b36}', '\u{16f4f}'..='\u{16f4f}', + '\u{16f8f}'..='\u{16f92}', '\u{16fe4}'..='\u{16fe4}', '\u{16ff0}'..='\u{16ff1}', + '\u{1bc9d}'..='\u{1bc9e}', '\u{1cf00}'..='\u{1cf2d}', '\u{1cf30}'..='\u{1cf46}', + '\u{1d165}'..='\u{1d169}', '\u{1d16d}'..='\u{1d172}', '\u{1d17b}'..='\u{1d182}', + '\u{1d185}'..='\u{1d18b}', '\u{1d1aa}'..='\u{1d1ad}', '\u{1d242}'..='\u{1d244}', + '\u{1da00}'..='\u{1da36}', '\u{1da3b}'..='\u{1da6c}', '\u{1da75}'..='\u{1da75}', + '\u{1da84}'..='\u{1da84}', '\u{1da9b}'..='\u{1da9f}', '\u{1daa1}'..='\u{1daaf}', + '\u{1e000}'..='\u{1e006}', '\u{1e008}'..='\u{1e018}', '\u{1e01b}'..='\u{1e021}', + '\u{1e023}'..='\u{1e024}', '\u{1e026}'..='\u{1e02a}', '\u{1e08f}'..='\u{1e08f}', + '\u{1e130}'..='\u{1e136}', '\u{1e2ae}'..='\u{1e2ae}', '\u{1e2ec}'..='\u{1e2ef}', + '\u{1e4ec}'..='\u{1e4ef}', '\u{1e5ee}'..='\u{1e5ef}', '\u{1e6e3}'..='\u{1e6e3}', + '\u{1e6e6}'..='\u{1e6e6}', '\u{1e6ee}'..='\u{1e6ef}', '\u{1e6f5}'..='\u{1e6f5}', + '\u{1e8d0}'..='\u{1e8d6}', '\u{1e944}'..='\u{1e94a}', '\u{e0020}'..='\u{e007f}', + '\u{e0100}'..='\u{e01ef}', +]; + +#[rustfmt::skip] +pub(super) static LOWERCASE: &[RangeInclusive; 676] = &[ + '\u{aa}'..='\u{aa}', '\u{b5}'..='\u{b5}', '\u{ba}'..='\u{ba}', '\u{df}'..='\u{f6}', + '\u{f8}'..='\u{ff}', '\u{101}'..='\u{101}', '\u{103}'..='\u{103}', '\u{105}'..='\u{105}', + '\u{107}'..='\u{107}', '\u{109}'..='\u{109}', '\u{10b}'..='\u{10b}', '\u{10d}'..='\u{10d}', + '\u{10f}'..='\u{10f}', '\u{111}'..='\u{111}', '\u{113}'..='\u{113}', '\u{115}'..='\u{115}', + '\u{117}'..='\u{117}', '\u{119}'..='\u{119}', '\u{11b}'..='\u{11b}', '\u{11d}'..='\u{11d}', + '\u{11f}'..='\u{11f}', '\u{121}'..='\u{121}', '\u{123}'..='\u{123}', '\u{125}'..='\u{125}', + '\u{127}'..='\u{127}', '\u{129}'..='\u{129}', '\u{12b}'..='\u{12b}', '\u{12d}'..='\u{12d}', + '\u{12f}'..='\u{12f}', '\u{131}'..='\u{131}', '\u{133}'..='\u{133}', '\u{135}'..='\u{135}', + '\u{137}'..='\u{138}', '\u{13a}'..='\u{13a}', '\u{13c}'..='\u{13c}', '\u{13e}'..='\u{13e}', + '\u{140}'..='\u{140}', '\u{142}'..='\u{142}', '\u{144}'..='\u{144}', '\u{146}'..='\u{146}', + '\u{148}'..='\u{149}', '\u{14b}'..='\u{14b}', '\u{14d}'..='\u{14d}', '\u{14f}'..='\u{14f}', + '\u{151}'..='\u{151}', '\u{153}'..='\u{153}', '\u{155}'..='\u{155}', '\u{157}'..='\u{157}', + '\u{159}'..='\u{159}', '\u{15b}'..='\u{15b}', '\u{15d}'..='\u{15d}', '\u{15f}'..='\u{15f}', + '\u{161}'..='\u{161}', '\u{163}'..='\u{163}', '\u{165}'..='\u{165}', '\u{167}'..='\u{167}', + '\u{169}'..='\u{169}', '\u{16b}'..='\u{16b}', '\u{16d}'..='\u{16d}', '\u{16f}'..='\u{16f}', + '\u{171}'..='\u{171}', '\u{173}'..='\u{173}', '\u{175}'..='\u{175}', '\u{177}'..='\u{177}', + '\u{17a}'..='\u{17a}', '\u{17c}'..='\u{17c}', '\u{17e}'..='\u{180}', '\u{183}'..='\u{183}', + '\u{185}'..='\u{185}', '\u{188}'..='\u{188}', '\u{18c}'..='\u{18d}', '\u{192}'..='\u{192}', + '\u{195}'..='\u{195}', '\u{199}'..='\u{19b}', '\u{19e}'..='\u{19e}', '\u{1a1}'..='\u{1a1}', + '\u{1a3}'..='\u{1a3}', '\u{1a5}'..='\u{1a5}', '\u{1a8}'..='\u{1a8}', '\u{1aa}'..='\u{1ab}', + '\u{1ad}'..='\u{1ad}', '\u{1b0}'..='\u{1b0}', '\u{1b4}'..='\u{1b4}', '\u{1b6}'..='\u{1b6}', + '\u{1b9}'..='\u{1ba}', '\u{1bd}'..='\u{1bf}', '\u{1c6}'..='\u{1c6}', '\u{1c9}'..='\u{1c9}', + '\u{1cc}'..='\u{1cc}', '\u{1ce}'..='\u{1ce}', '\u{1d0}'..='\u{1d0}', '\u{1d2}'..='\u{1d2}', + '\u{1d4}'..='\u{1d4}', '\u{1d6}'..='\u{1d6}', '\u{1d8}'..='\u{1d8}', '\u{1da}'..='\u{1da}', + '\u{1dc}'..='\u{1dd}', '\u{1df}'..='\u{1df}', '\u{1e1}'..='\u{1e1}', '\u{1e3}'..='\u{1e3}', + '\u{1e5}'..='\u{1e5}', '\u{1e7}'..='\u{1e7}', '\u{1e9}'..='\u{1e9}', '\u{1eb}'..='\u{1eb}', + '\u{1ed}'..='\u{1ed}', '\u{1ef}'..='\u{1f0}', '\u{1f3}'..='\u{1f3}', '\u{1f5}'..='\u{1f5}', + '\u{1f9}'..='\u{1f9}', '\u{1fb}'..='\u{1fb}', '\u{1fd}'..='\u{1fd}', '\u{1ff}'..='\u{1ff}', + '\u{201}'..='\u{201}', '\u{203}'..='\u{203}', '\u{205}'..='\u{205}', '\u{207}'..='\u{207}', + '\u{209}'..='\u{209}', '\u{20b}'..='\u{20b}', '\u{20d}'..='\u{20d}', '\u{20f}'..='\u{20f}', + '\u{211}'..='\u{211}', '\u{213}'..='\u{213}', '\u{215}'..='\u{215}', '\u{217}'..='\u{217}', + '\u{219}'..='\u{219}', '\u{21b}'..='\u{21b}', '\u{21d}'..='\u{21d}', '\u{21f}'..='\u{21f}', + '\u{221}'..='\u{221}', '\u{223}'..='\u{223}', '\u{225}'..='\u{225}', '\u{227}'..='\u{227}', + '\u{229}'..='\u{229}', '\u{22b}'..='\u{22b}', '\u{22d}'..='\u{22d}', '\u{22f}'..='\u{22f}', + '\u{231}'..='\u{231}', '\u{233}'..='\u{239}', '\u{23c}'..='\u{23c}', '\u{23f}'..='\u{240}', + '\u{242}'..='\u{242}', '\u{247}'..='\u{247}', '\u{249}'..='\u{249}', '\u{24b}'..='\u{24b}', + '\u{24d}'..='\u{24d}', '\u{24f}'..='\u{293}', '\u{296}'..='\u{2b8}', '\u{2c0}'..='\u{2c1}', + '\u{2e0}'..='\u{2e4}', '\u{345}'..='\u{345}', '\u{371}'..='\u{371}', '\u{373}'..='\u{373}', + '\u{377}'..='\u{377}', '\u{37a}'..='\u{37d}', '\u{390}'..='\u{390}', '\u{3ac}'..='\u{3ce}', + '\u{3d0}'..='\u{3d1}', '\u{3d5}'..='\u{3d7}', '\u{3d9}'..='\u{3d9}', '\u{3db}'..='\u{3db}', + '\u{3dd}'..='\u{3dd}', '\u{3df}'..='\u{3df}', '\u{3e1}'..='\u{3e1}', '\u{3e3}'..='\u{3e3}', + '\u{3e5}'..='\u{3e5}', '\u{3e7}'..='\u{3e7}', '\u{3e9}'..='\u{3e9}', '\u{3eb}'..='\u{3eb}', + '\u{3ed}'..='\u{3ed}', '\u{3ef}'..='\u{3f3}', '\u{3f5}'..='\u{3f5}', '\u{3f8}'..='\u{3f8}', + '\u{3fb}'..='\u{3fc}', '\u{430}'..='\u{45f}', '\u{461}'..='\u{461}', '\u{463}'..='\u{463}', + '\u{465}'..='\u{465}', '\u{467}'..='\u{467}', '\u{469}'..='\u{469}', '\u{46b}'..='\u{46b}', + '\u{46d}'..='\u{46d}', '\u{46f}'..='\u{46f}', '\u{471}'..='\u{471}', '\u{473}'..='\u{473}', + '\u{475}'..='\u{475}', '\u{477}'..='\u{477}', '\u{479}'..='\u{479}', '\u{47b}'..='\u{47b}', + '\u{47d}'..='\u{47d}', '\u{47f}'..='\u{47f}', '\u{481}'..='\u{481}', '\u{48b}'..='\u{48b}', + '\u{48d}'..='\u{48d}', '\u{48f}'..='\u{48f}', '\u{491}'..='\u{491}', '\u{493}'..='\u{493}', + '\u{495}'..='\u{495}', '\u{497}'..='\u{497}', '\u{499}'..='\u{499}', '\u{49b}'..='\u{49b}', + '\u{49d}'..='\u{49d}', '\u{49f}'..='\u{49f}', '\u{4a1}'..='\u{4a1}', '\u{4a3}'..='\u{4a3}', + '\u{4a5}'..='\u{4a5}', '\u{4a7}'..='\u{4a7}', '\u{4a9}'..='\u{4a9}', '\u{4ab}'..='\u{4ab}', + '\u{4ad}'..='\u{4ad}', '\u{4af}'..='\u{4af}', '\u{4b1}'..='\u{4b1}', '\u{4b3}'..='\u{4b3}', + '\u{4b5}'..='\u{4b5}', '\u{4b7}'..='\u{4b7}', '\u{4b9}'..='\u{4b9}', '\u{4bb}'..='\u{4bb}', + '\u{4bd}'..='\u{4bd}', '\u{4bf}'..='\u{4bf}', '\u{4c2}'..='\u{4c2}', '\u{4c4}'..='\u{4c4}', + '\u{4c6}'..='\u{4c6}', '\u{4c8}'..='\u{4c8}', '\u{4ca}'..='\u{4ca}', '\u{4cc}'..='\u{4cc}', + '\u{4ce}'..='\u{4cf}', '\u{4d1}'..='\u{4d1}', '\u{4d3}'..='\u{4d3}', '\u{4d5}'..='\u{4d5}', + '\u{4d7}'..='\u{4d7}', '\u{4d9}'..='\u{4d9}', '\u{4db}'..='\u{4db}', '\u{4dd}'..='\u{4dd}', + '\u{4df}'..='\u{4df}', '\u{4e1}'..='\u{4e1}', '\u{4e3}'..='\u{4e3}', '\u{4e5}'..='\u{4e5}', + '\u{4e7}'..='\u{4e7}', '\u{4e9}'..='\u{4e9}', '\u{4eb}'..='\u{4eb}', '\u{4ed}'..='\u{4ed}', + '\u{4ef}'..='\u{4ef}', '\u{4f1}'..='\u{4f1}', '\u{4f3}'..='\u{4f3}', '\u{4f5}'..='\u{4f5}', + '\u{4f7}'..='\u{4f7}', '\u{4f9}'..='\u{4f9}', '\u{4fb}'..='\u{4fb}', '\u{4fd}'..='\u{4fd}', + '\u{4ff}'..='\u{4ff}', '\u{501}'..='\u{501}', '\u{503}'..='\u{503}', '\u{505}'..='\u{505}', + '\u{507}'..='\u{507}', '\u{509}'..='\u{509}', '\u{50b}'..='\u{50b}', '\u{50d}'..='\u{50d}', + '\u{50f}'..='\u{50f}', '\u{511}'..='\u{511}', '\u{513}'..='\u{513}', '\u{515}'..='\u{515}', + '\u{517}'..='\u{517}', '\u{519}'..='\u{519}', '\u{51b}'..='\u{51b}', '\u{51d}'..='\u{51d}', + '\u{51f}'..='\u{51f}', '\u{521}'..='\u{521}', '\u{523}'..='\u{523}', '\u{525}'..='\u{525}', + '\u{527}'..='\u{527}', '\u{529}'..='\u{529}', '\u{52b}'..='\u{52b}', '\u{52d}'..='\u{52d}', + '\u{52f}'..='\u{52f}', '\u{560}'..='\u{588}', '\u{10d0}'..='\u{10fa}', + '\u{10fc}'..='\u{10ff}', '\u{13f8}'..='\u{13fd}', '\u{1c80}'..='\u{1c88}', + '\u{1c8a}'..='\u{1c8a}', '\u{1d00}'..='\u{1dbf}', '\u{1e01}'..='\u{1e01}', + '\u{1e03}'..='\u{1e03}', '\u{1e05}'..='\u{1e05}', '\u{1e07}'..='\u{1e07}', + '\u{1e09}'..='\u{1e09}', '\u{1e0b}'..='\u{1e0b}', '\u{1e0d}'..='\u{1e0d}', + '\u{1e0f}'..='\u{1e0f}', '\u{1e11}'..='\u{1e11}', '\u{1e13}'..='\u{1e13}', + '\u{1e15}'..='\u{1e15}', '\u{1e17}'..='\u{1e17}', '\u{1e19}'..='\u{1e19}', + '\u{1e1b}'..='\u{1e1b}', '\u{1e1d}'..='\u{1e1d}', '\u{1e1f}'..='\u{1e1f}', + '\u{1e21}'..='\u{1e21}', '\u{1e23}'..='\u{1e23}', '\u{1e25}'..='\u{1e25}', + '\u{1e27}'..='\u{1e27}', '\u{1e29}'..='\u{1e29}', '\u{1e2b}'..='\u{1e2b}', + '\u{1e2d}'..='\u{1e2d}', '\u{1e2f}'..='\u{1e2f}', '\u{1e31}'..='\u{1e31}', + '\u{1e33}'..='\u{1e33}', '\u{1e35}'..='\u{1e35}', '\u{1e37}'..='\u{1e37}', + '\u{1e39}'..='\u{1e39}', '\u{1e3b}'..='\u{1e3b}', '\u{1e3d}'..='\u{1e3d}', + '\u{1e3f}'..='\u{1e3f}', '\u{1e41}'..='\u{1e41}', '\u{1e43}'..='\u{1e43}', + '\u{1e45}'..='\u{1e45}', '\u{1e47}'..='\u{1e47}', '\u{1e49}'..='\u{1e49}', + '\u{1e4b}'..='\u{1e4b}', '\u{1e4d}'..='\u{1e4d}', '\u{1e4f}'..='\u{1e4f}', + '\u{1e51}'..='\u{1e51}', '\u{1e53}'..='\u{1e53}', '\u{1e55}'..='\u{1e55}', + '\u{1e57}'..='\u{1e57}', '\u{1e59}'..='\u{1e59}', '\u{1e5b}'..='\u{1e5b}', + '\u{1e5d}'..='\u{1e5d}', '\u{1e5f}'..='\u{1e5f}', '\u{1e61}'..='\u{1e61}', + '\u{1e63}'..='\u{1e63}', '\u{1e65}'..='\u{1e65}', '\u{1e67}'..='\u{1e67}', + '\u{1e69}'..='\u{1e69}', '\u{1e6b}'..='\u{1e6b}', '\u{1e6d}'..='\u{1e6d}', + '\u{1e6f}'..='\u{1e6f}', '\u{1e71}'..='\u{1e71}', '\u{1e73}'..='\u{1e73}', + '\u{1e75}'..='\u{1e75}', '\u{1e77}'..='\u{1e77}', '\u{1e79}'..='\u{1e79}', + '\u{1e7b}'..='\u{1e7b}', '\u{1e7d}'..='\u{1e7d}', '\u{1e7f}'..='\u{1e7f}', + '\u{1e81}'..='\u{1e81}', '\u{1e83}'..='\u{1e83}', '\u{1e85}'..='\u{1e85}', + '\u{1e87}'..='\u{1e87}', '\u{1e89}'..='\u{1e89}', '\u{1e8b}'..='\u{1e8b}', + '\u{1e8d}'..='\u{1e8d}', '\u{1e8f}'..='\u{1e8f}', '\u{1e91}'..='\u{1e91}', + '\u{1e93}'..='\u{1e93}', '\u{1e95}'..='\u{1e9d}', '\u{1e9f}'..='\u{1e9f}', + '\u{1ea1}'..='\u{1ea1}', '\u{1ea3}'..='\u{1ea3}', '\u{1ea5}'..='\u{1ea5}', + '\u{1ea7}'..='\u{1ea7}', '\u{1ea9}'..='\u{1ea9}', '\u{1eab}'..='\u{1eab}', + '\u{1ead}'..='\u{1ead}', '\u{1eaf}'..='\u{1eaf}', '\u{1eb1}'..='\u{1eb1}', + '\u{1eb3}'..='\u{1eb3}', '\u{1eb5}'..='\u{1eb5}', '\u{1eb7}'..='\u{1eb7}', + '\u{1eb9}'..='\u{1eb9}', '\u{1ebb}'..='\u{1ebb}', '\u{1ebd}'..='\u{1ebd}', + '\u{1ebf}'..='\u{1ebf}', '\u{1ec1}'..='\u{1ec1}', '\u{1ec3}'..='\u{1ec3}', + '\u{1ec5}'..='\u{1ec5}', '\u{1ec7}'..='\u{1ec7}', '\u{1ec9}'..='\u{1ec9}', + '\u{1ecb}'..='\u{1ecb}', '\u{1ecd}'..='\u{1ecd}', '\u{1ecf}'..='\u{1ecf}', + '\u{1ed1}'..='\u{1ed1}', '\u{1ed3}'..='\u{1ed3}', '\u{1ed5}'..='\u{1ed5}', + '\u{1ed7}'..='\u{1ed7}', '\u{1ed9}'..='\u{1ed9}', '\u{1edb}'..='\u{1edb}', + '\u{1edd}'..='\u{1edd}', '\u{1edf}'..='\u{1edf}', '\u{1ee1}'..='\u{1ee1}', + '\u{1ee3}'..='\u{1ee3}', '\u{1ee5}'..='\u{1ee5}', '\u{1ee7}'..='\u{1ee7}', + '\u{1ee9}'..='\u{1ee9}', '\u{1eeb}'..='\u{1eeb}', '\u{1eed}'..='\u{1eed}', + '\u{1eef}'..='\u{1eef}', '\u{1ef1}'..='\u{1ef1}', '\u{1ef3}'..='\u{1ef3}', + '\u{1ef5}'..='\u{1ef5}', '\u{1ef7}'..='\u{1ef7}', '\u{1ef9}'..='\u{1ef9}', + '\u{1efb}'..='\u{1efb}', '\u{1efd}'..='\u{1efd}', '\u{1eff}'..='\u{1f07}', + '\u{1f10}'..='\u{1f15}', '\u{1f20}'..='\u{1f27}', '\u{1f30}'..='\u{1f37}', + '\u{1f40}'..='\u{1f45}', '\u{1f50}'..='\u{1f57}', '\u{1f60}'..='\u{1f67}', + '\u{1f70}'..='\u{1f7d}', '\u{1f80}'..='\u{1f87}', '\u{1f90}'..='\u{1f97}', + '\u{1fa0}'..='\u{1fa7}', '\u{1fb0}'..='\u{1fb4}', '\u{1fb6}'..='\u{1fb7}', + '\u{1fbe}'..='\u{1fbe}', '\u{1fc2}'..='\u{1fc4}', '\u{1fc6}'..='\u{1fc7}', + '\u{1fd0}'..='\u{1fd3}', '\u{1fd6}'..='\u{1fd7}', '\u{1fe0}'..='\u{1fe7}', + '\u{1ff2}'..='\u{1ff4}', '\u{1ff6}'..='\u{1ff7}', '\u{2071}'..='\u{2071}', + '\u{207f}'..='\u{207f}', '\u{2090}'..='\u{209c}', '\u{210a}'..='\u{210a}', + '\u{210e}'..='\u{210f}', '\u{2113}'..='\u{2113}', '\u{212f}'..='\u{212f}', + '\u{2134}'..='\u{2134}', '\u{2139}'..='\u{2139}', '\u{213c}'..='\u{213d}', + '\u{2146}'..='\u{2149}', '\u{214e}'..='\u{214e}', '\u{2170}'..='\u{217f}', + '\u{2184}'..='\u{2184}', '\u{24d0}'..='\u{24e9}', '\u{2c30}'..='\u{2c5f}', + '\u{2c61}'..='\u{2c61}', '\u{2c65}'..='\u{2c66}', '\u{2c68}'..='\u{2c68}', + '\u{2c6a}'..='\u{2c6a}', '\u{2c6c}'..='\u{2c6c}', '\u{2c71}'..='\u{2c71}', + '\u{2c73}'..='\u{2c74}', '\u{2c76}'..='\u{2c7d}', '\u{2c81}'..='\u{2c81}', + '\u{2c83}'..='\u{2c83}', '\u{2c85}'..='\u{2c85}', '\u{2c87}'..='\u{2c87}', + '\u{2c89}'..='\u{2c89}', '\u{2c8b}'..='\u{2c8b}', '\u{2c8d}'..='\u{2c8d}', + '\u{2c8f}'..='\u{2c8f}', '\u{2c91}'..='\u{2c91}', '\u{2c93}'..='\u{2c93}', + '\u{2c95}'..='\u{2c95}', '\u{2c97}'..='\u{2c97}', '\u{2c99}'..='\u{2c99}', + '\u{2c9b}'..='\u{2c9b}', '\u{2c9d}'..='\u{2c9d}', '\u{2c9f}'..='\u{2c9f}', + '\u{2ca1}'..='\u{2ca1}', '\u{2ca3}'..='\u{2ca3}', '\u{2ca5}'..='\u{2ca5}', + '\u{2ca7}'..='\u{2ca7}', '\u{2ca9}'..='\u{2ca9}', '\u{2cab}'..='\u{2cab}', + '\u{2cad}'..='\u{2cad}', '\u{2caf}'..='\u{2caf}', '\u{2cb1}'..='\u{2cb1}', + '\u{2cb3}'..='\u{2cb3}', '\u{2cb5}'..='\u{2cb5}', '\u{2cb7}'..='\u{2cb7}', + '\u{2cb9}'..='\u{2cb9}', '\u{2cbb}'..='\u{2cbb}', '\u{2cbd}'..='\u{2cbd}', + '\u{2cbf}'..='\u{2cbf}', '\u{2cc1}'..='\u{2cc1}', '\u{2cc3}'..='\u{2cc3}', + '\u{2cc5}'..='\u{2cc5}', '\u{2cc7}'..='\u{2cc7}', '\u{2cc9}'..='\u{2cc9}', + '\u{2ccb}'..='\u{2ccb}', '\u{2ccd}'..='\u{2ccd}', '\u{2ccf}'..='\u{2ccf}', + '\u{2cd1}'..='\u{2cd1}', '\u{2cd3}'..='\u{2cd3}', '\u{2cd5}'..='\u{2cd5}', + '\u{2cd7}'..='\u{2cd7}', '\u{2cd9}'..='\u{2cd9}', '\u{2cdb}'..='\u{2cdb}', + '\u{2cdd}'..='\u{2cdd}', '\u{2cdf}'..='\u{2cdf}', '\u{2ce1}'..='\u{2ce1}', + '\u{2ce3}'..='\u{2ce4}', '\u{2cec}'..='\u{2cec}', '\u{2cee}'..='\u{2cee}', + '\u{2cf3}'..='\u{2cf3}', '\u{2d00}'..='\u{2d25}', '\u{2d27}'..='\u{2d27}', + '\u{2d2d}'..='\u{2d2d}', '\u{a641}'..='\u{a641}', '\u{a643}'..='\u{a643}', + '\u{a645}'..='\u{a645}', '\u{a647}'..='\u{a647}', '\u{a649}'..='\u{a649}', + '\u{a64b}'..='\u{a64b}', '\u{a64d}'..='\u{a64d}', '\u{a64f}'..='\u{a64f}', + '\u{a651}'..='\u{a651}', '\u{a653}'..='\u{a653}', '\u{a655}'..='\u{a655}', + '\u{a657}'..='\u{a657}', '\u{a659}'..='\u{a659}', '\u{a65b}'..='\u{a65b}', + '\u{a65d}'..='\u{a65d}', '\u{a65f}'..='\u{a65f}', '\u{a661}'..='\u{a661}', + '\u{a663}'..='\u{a663}', '\u{a665}'..='\u{a665}', '\u{a667}'..='\u{a667}', + '\u{a669}'..='\u{a669}', '\u{a66b}'..='\u{a66b}', '\u{a66d}'..='\u{a66d}', + '\u{a681}'..='\u{a681}', '\u{a683}'..='\u{a683}', '\u{a685}'..='\u{a685}', + '\u{a687}'..='\u{a687}', '\u{a689}'..='\u{a689}', '\u{a68b}'..='\u{a68b}', + '\u{a68d}'..='\u{a68d}', '\u{a68f}'..='\u{a68f}', '\u{a691}'..='\u{a691}', + '\u{a693}'..='\u{a693}', '\u{a695}'..='\u{a695}', '\u{a697}'..='\u{a697}', + '\u{a699}'..='\u{a699}', '\u{a69b}'..='\u{a69d}', '\u{a723}'..='\u{a723}', + '\u{a725}'..='\u{a725}', '\u{a727}'..='\u{a727}', '\u{a729}'..='\u{a729}', + '\u{a72b}'..='\u{a72b}', '\u{a72d}'..='\u{a72d}', '\u{a72f}'..='\u{a731}', + '\u{a733}'..='\u{a733}', '\u{a735}'..='\u{a735}', '\u{a737}'..='\u{a737}', + '\u{a739}'..='\u{a739}', '\u{a73b}'..='\u{a73b}', '\u{a73d}'..='\u{a73d}', + '\u{a73f}'..='\u{a73f}', '\u{a741}'..='\u{a741}', '\u{a743}'..='\u{a743}', + '\u{a745}'..='\u{a745}', '\u{a747}'..='\u{a747}', '\u{a749}'..='\u{a749}', + '\u{a74b}'..='\u{a74b}', '\u{a74d}'..='\u{a74d}', '\u{a74f}'..='\u{a74f}', + '\u{a751}'..='\u{a751}', '\u{a753}'..='\u{a753}', '\u{a755}'..='\u{a755}', + '\u{a757}'..='\u{a757}', '\u{a759}'..='\u{a759}', '\u{a75b}'..='\u{a75b}', + '\u{a75d}'..='\u{a75d}', '\u{a75f}'..='\u{a75f}', '\u{a761}'..='\u{a761}', + '\u{a763}'..='\u{a763}', '\u{a765}'..='\u{a765}', '\u{a767}'..='\u{a767}', + '\u{a769}'..='\u{a769}', '\u{a76b}'..='\u{a76b}', '\u{a76d}'..='\u{a76d}', + '\u{a76f}'..='\u{a778}', '\u{a77a}'..='\u{a77a}', '\u{a77c}'..='\u{a77c}', + '\u{a77f}'..='\u{a77f}', '\u{a781}'..='\u{a781}', '\u{a783}'..='\u{a783}', + '\u{a785}'..='\u{a785}', '\u{a787}'..='\u{a787}', '\u{a78c}'..='\u{a78c}', + '\u{a78e}'..='\u{a78e}', '\u{a791}'..='\u{a791}', '\u{a793}'..='\u{a795}', + '\u{a797}'..='\u{a797}', '\u{a799}'..='\u{a799}', '\u{a79b}'..='\u{a79b}', + '\u{a79d}'..='\u{a79d}', '\u{a79f}'..='\u{a79f}', '\u{a7a1}'..='\u{a7a1}', + '\u{a7a3}'..='\u{a7a3}', '\u{a7a5}'..='\u{a7a5}', '\u{a7a7}'..='\u{a7a7}', + '\u{a7a9}'..='\u{a7a9}', '\u{a7af}'..='\u{a7af}', '\u{a7b5}'..='\u{a7b5}', + '\u{a7b7}'..='\u{a7b7}', '\u{a7b9}'..='\u{a7b9}', '\u{a7bb}'..='\u{a7bb}', + '\u{a7bd}'..='\u{a7bd}', '\u{a7bf}'..='\u{a7bf}', '\u{a7c1}'..='\u{a7c1}', + '\u{a7c3}'..='\u{a7c3}', '\u{a7c8}'..='\u{a7c8}', '\u{a7ca}'..='\u{a7ca}', + '\u{a7cd}'..='\u{a7cd}', '\u{a7cf}'..='\u{a7cf}', '\u{a7d1}'..='\u{a7d1}', + '\u{a7d3}'..='\u{a7d3}', '\u{a7d5}'..='\u{a7d5}', '\u{a7d7}'..='\u{a7d7}', + '\u{a7d9}'..='\u{a7d9}', '\u{a7db}'..='\u{a7db}', '\u{a7f1}'..='\u{a7f4}', + '\u{a7f6}'..='\u{a7f6}', '\u{a7f8}'..='\u{a7fa}', '\u{ab30}'..='\u{ab5a}', + '\u{ab5c}'..='\u{ab69}', '\u{ab70}'..='\u{abbf}', '\u{fb00}'..='\u{fb06}', + '\u{fb13}'..='\u{fb17}', '\u{ff41}'..='\u{ff5a}', '\u{10428}'..='\u{1044f}', + '\u{104d8}'..='\u{104fb}', '\u{10597}'..='\u{105a1}', '\u{105a3}'..='\u{105b1}', + '\u{105b3}'..='\u{105b9}', '\u{105bb}'..='\u{105bc}', '\u{10780}'..='\u{10780}', + '\u{10783}'..='\u{10785}', '\u{10787}'..='\u{107b0}', '\u{107b2}'..='\u{107ba}', + '\u{10cc0}'..='\u{10cf2}', '\u{10d70}'..='\u{10d85}', '\u{118c0}'..='\u{118df}', + '\u{16e60}'..='\u{16e7f}', '\u{16ebb}'..='\u{16ed3}', '\u{1d41a}'..='\u{1d433}', + '\u{1d44e}'..='\u{1d454}', '\u{1d456}'..='\u{1d467}', '\u{1d482}'..='\u{1d49b}', + '\u{1d4b6}'..='\u{1d4b9}', '\u{1d4bb}'..='\u{1d4bb}', '\u{1d4bd}'..='\u{1d4c3}', + '\u{1d4c5}'..='\u{1d4cf}', '\u{1d4ea}'..='\u{1d503}', '\u{1d51e}'..='\u{1d537}', + '\u{1d552}'..='\u{1d56b}', '\u{1d586}'..='\u{1d59f}', '\u{1d5ba}'..='\u{1d5d3}', + '\u{1d5ee}'..='\u{1d607}', '\u{1d622}'..='\u{1d63b}', '\u{1d656}'..='\u{1d66f}', + '\u{1d68a}'..='\u{1d6a5}', '\u{1d6c2}'..='\u{1d6da}', '\u{1d6dc}'..='\u{1d6e1}', + '\u{1d6fc}'..='\u{1d714}', '\u{1d716}'..='\u{1d71b}', '\u{1d736}'..='\u{1d74e}', + '\u{1d750}'..='\u{1d755}', '\u{1d770}'..='\u{1d788}', '\u{1d78a}'..='\u{1d78f}', + '\u{1d7aa}'..='\u{1d7c2}', '\u{1d7c4}'..='\u{1d7c9}', '\u{1d7cb}'..='\u{1d7cb}', + '\u{1df00}'..='\u{1df09}', '\u{1df0b}'..='\u{1df1e}', '\u{1df25}'..='\u{1df2a}', + '\u{1e030}'..='\u{1e06d}', '\u{1e922}'..='\u{1e943}', +]; + +#[rustfmt::skip] +pub(super) static LT: &[RangeInclusive; 10] = &[ + '\u{1c5}'..='\u{1c5}', '\u{1c8}'..='\u{1c8}', '\u{1cb}'..='\u{1cb}', '\u{1f2}'..='\u{1f2}', + '\u{1f88}'..='\u{1f8f}', '\u{1f98}'..='\u{1f9f}', '\u{1fa8}'..='\u{1faf}', + '\u{1fbc}'..='\u{1fbc}', '\u{1fcc}'..='\u{1fcc}', '\u{1ffc}'..='\u{1ffc}', +]; + +#[rustfmt::skip] +pub(super) static N: &[RangeInclusive; 145] = &[ + '\u{b2}'..='\u{b3}', '\u{b9}'..='\u{b9}', '\u{bc}'..='\u{be}', '\u{660}'..='\u{669}', + '\u{6f0}'..='\u{6f9}', '\u{7c0}'..='\u{7c9}', '\u{966}'..='\u{96f}', '\u{9e6}'..='\u{9ef}', + '\u{9f4}'..='\u{9f9}', '\u{a66}'..='\u{a6f}', '\u{ae6}'..='\u{aef}', '\u{b66}'..='\u{b6f}', + '\u{b72}'..='\u{b77}', '\u{be6}'..='\u{bf2}', '\u{c66}'..='\u{c6f}', '\u{c78}'..='\u{c7e}', + '\u{ce6}'..='\u{cef}', '\u{d58}'..='\u{d5e}', '\u{d66}'..='\u{d78}', '\u{de6}'..='\u{def}', + '\u{e50}'..='\u{e59}', '\u{ed0}'..='\u{ed9}', '\u{f20}'..='\u{f33}', + '\u{1040}'..='\u{1049}', '\u{1090}'..='\u{1099}', '\u{1369}'..='\u{137c}', + '\u{16ee}'..='\u{16f0}', '\u{17e0}'..='\u{17e9}', '\u{17f0}'..='\u{17f9}', + '\u{1810}'..='\u{1819}', '\u{1946}'..='\u{194f}', '\u{19d0}'..='\u{19da}', + '\u{1a80}'..='\u{1a89}', '\u{1a90}'..='\u{1a99}', '\u{1b50}'..='\u{1b59}', + '\u{1bb0}'..='\u{1bb9}', '\u{1c40}'..='\u{1c49}', '\u{1c50}'..='\u{1c59}', + '\u{2070}'..='\u{2070}', '\u{2074}'..='\u{2079}', '\u{2080}'..='\u{2089}', + '\u{2150}'..='\u{2182}', '\u{2185}'..='\u{2189}', '\u{2460}'..='\u{249b}', + '\u{24ea}'..='\u{24ff}', '\u{2776}'..='\u{2793}', '\u{2cfd}'..='\u{2cfd}', + '\u{3007}'..='\u{3007}', '\u{3021}'..='\u{3029}', '\u{3038}'..='\u{303a}', + '\u{3192}'..='\u{3195}', '\u{3220}'..='\u{3229}', '\u{3248}'..='\u{324f}', + '\u{3251}'..='\u{325f}', '\u{3280}'..='\u{3289}', '\u{32b1}'..='\u{32bf}', + '\u{a620}'..='\u{a629}', '\u{a6e6}'..='\u{a6ef}', '\u{a830}'..='\u{a835}', + '\u{a8d0}'..='\u{a8d9}', '\u{a900}'..='\u{a909}', '\u{a9d0}'..='\u{a9d9}', + '\u{a9f0}'..='\u{a9f9}', '\u{aa50}'..='\u{aa59}', '\u{abf0}'..='\u{abf9}', + '\u{ff10}'..='\u{ff19}', '\u{10107}'..='\u{10133}', '\u{10140}'..='\u{10178}', + '\u{1018a}'..='\u{1018b}', '\u{102e1}'..='\u{102fb}', '\u{10320}'..='\u{10323}', + '\u{10341}'..='\u{10341}', '\u{1034a}'..='\u{1034a}', '\u{103d1}'..='\u{103d5}', + '\u{104a0}'..='\u{104a9}', '\u{10858}'..='\u{1085f}', '\u{10879}'..='\u{1087f}', + '\u{108a7}'..='\u{108af}', '\u{108fb}'..='\u{108ff}', '\u{10916}'..='\u{1091b}', + '\u{109bc}'..='\u{109bd}', '\u{109c0}'..='\u{109cf}', '\u{109d2}'..='\u{109ff}', + '\u{10a40}'..='\u{10a48}', '\u{10a7d}'..='\u{10a7e}', '\u{10a9d}'..='\u{10a9f}', + '\u{10aeb}'..='\u{10aef}', '\u{10b58}'..='\u{10b5f}', '\u{10b78}'..='\u{10b7f}', + '\u{10ba9}'..='\u{10baf}', '\u{10cfa}'..='\u{10cff}', '\u{10d30}'..='\u{10d39}', + '\u{10d40}'..='\u{10d49}', '\u{10e60}'..='\u{10e7e}', '\u{10f1d}'..='\u{10f26}', + '\u{10f51}'..='\u{10f54}', '\u{10fc5}'..='\u{10fcb}', '\u{11052}'..='\u{1106f}', + '\u{110f0}'..='\u{110f9}', '\u{11136}'..='\u{1113f}', '\u{111d0}'..='\u{111d9}', + '\u{111e1}'..='\u{111f4}', '\u{112f0}'..='\u{112f9}', '\u{11450}'..='\u{11459}', + '\u{114d0}'..='\u{114d9}', '\u{11650}'..='\u{11659}', '\u{116c0}'..='\u{116c9}', + '\u{116d0}'..='\u{116e3}', '\u{11730}'..='\u{1173b}', '\u{118e0}'..='\u{118f2}', + '\u{11950}'..='\u{11959}', '\u{11bf0}'..='\u{11bf9}', '\u{11c50}'..='\u{11c6c}', + '\u{11d50}'..='\u{11d59}', '\u{11da0}'..='\u{11da9}', '\u{11de0}'..='\u{11de9}', + '\u{11f50}'..='\u{11f59}', '\u{11fc0}'..='\u{11fd4}', '\u{12400}'..='\u{1246e}', + '\u{16130}'..='\u{16139}', '\u{16a60}'..='\u{16a69}', '\u{16ac0}'..='\u{16ac9}', + '\u{16b50}'..='\u{16b59}', '\u{16b5b}'..='\u{16b61}', '\u{16d70}'..='\u{16d79}', + '\u{16e80}'..='\u{16e96}', '\u{16ff4}'..='\u{16ff6}', '\u{1ccf0}'..='\u{1ccf9}', + '\u{1d2c0}'..='\u{1d2d3}', '\u{1d2e0}'..='\u{1d2f3}', '\u{1d360}'..='\u{1d378}', + '\u{1d7ce}'..='\u{1d7ff}', '\u{1e140}'..='\u{1e149}', '\u{1e2f0}'..='\u{1e2f9}', + '\u{1e4f0}'..='\u{1e4f9}', '\u{1e5f1}'..='\u{1e5fa}', '\u{1e8c7}'..='\u{1e8cf}', + '\u{1e950}'..='\u{1e959}', '\u{1ec71}'..='\u{1ecab}', '\u{1ecad}'..='\u{1ecaf}', + '\u{1ecb1}'..='\u{1ecb4}', '\u{1ed01}'..='\u{1ed2d}', '\u{1ed2f}'..='\u{1ed3d}', + '\u{1f100}'..='\u{1f10c}', '\u{1fbf0}'..='\u{1fbf9}', +]; + +#[rustfmt::skip] +pub(super) static UPPERCASE: &[RangeInclusive; 659] = &[ + '\u{c0}'..='\u{d6}', '\u{d8}'..='\u{de}', '\u{100}'..='\u{100}', '\u{102}'..='\u{102}', + '\u{104}'..='\u{104}', '\u{106}'..='\u{106}', '\u{108}'..='\u{108}', '\u{10a}'..='\u{10a}', + '\u{10c}'..='\u{10c}', '\u{10e}'..='\u{10e}', '\u{110}'..='\u{110}', '\u{112}'..='\u{112}', + '\u{114}'..='\u{114}', '\u{116}'..='\u{116}', '\u{118}'..='\u{118}', '\u{11a}'..='\u{11a}', + '\u{11c}'..='\u{11c}', '\u{11e}'..='\u{11e}', '\u{120}'..='\u{120}', '\u{122}'..='\u{122}', + '\u{124}'..='\u{124}', '\u{126}'..='\u{126}', '\u{128}'..='\u{128}', '\u{12a}'..='\u{12a}', + '\u{12c}'..='\u{12c}', '\u{12e}'..='\u{12e}', '\u{130}'..='\u{130}', '\u{132}'..='\u{132}', + '\u{134}'..='\u{134}', '\u{136}'..='\u{136}', '\u{139}'..='\u{139}', '\u{13b}'..='\u{13b}', + '\u{13d}'..='\u{13d}', '\u{13f}'..='\u{13f}', '\u{141}'..='\u{141}', '\u{143}'..='\u{143}', + '\u{145}'..='\u{145}', '\u{147}'..='\u{147}', '\u{14a}'..='\u{14a}', '\u{14c}'..='\u{14c}', + '\u{14e}'..='\u{14e}', '\u{150}'..='\u{150}', '\u{152}'..='\u{152}', '\u{154}'..='\u{154}', + '\u{156}'..='\u{156}', '\u{158}'..='\u{158}', '\u{15a}'..='\u{15a}', '\u{15c}'..='\u{15c}', + '\u{15e}'..='\u{15e}', '\u{160}'..='\u{160}', '\u{162}'..='\u{162}', '\u{164}'..='\u{164}', + '\u{166}'..='\u{166}', '\u{168}'..='\u{168}', '\u{16a}'..='\u{16a}', '\u{16c}'..='\u{16c}', + '\u{16e}'..='\u{16e}', '\u{170}'..='\u{170}', '\u{172}'..='\u{172}', '\u{174}'..='\u{174}', + '\u{176}'..='\u{176}', '\u{178}'..='\u{179}', '\u{17b}'..='\u{17b}', '\u{17d}'..='\u{17d}', + '\u{181}'..='\u{182}', '\u{184}'..='\u{184}', '\u{186}'..='\u{187}', '\u{189}'..='\u{18b}', + '\u{18e}'..='\u{191}', '\u{193}'..='\u{194}', '\u{196}'..='\u{198}', '\u{19c}'..='\u{19d}', + '\u{19f}'..='\u{1a0}', '\u{1a2}'..='\u{1a2}', '\u{1a4}'..='\u{1a4}', '\u{1a6}'..='\u{1a7}', + '\u{1a9}'..='\u{1a9}', '\u{1ac}'..='\u{1ac}', '\u{1ae}'..='\u{1af}', '\u{1b1}'..='\u{1b3}', + '\u{1b5}'..='\u{1b5}', '\u{1b7}'..='\u{1b8}', '\u{1bc}'..='\u{1bc}', '\u{1c4}'..='\u{1c4}', + '\u{1c7}'..='\u{1c7}', '\u{1ca}'..='\u{1ca}', '\u{1cd}'..='\u{1cd}', '\u{1cf}'..='\u{1cf}', + '\u{1d1}'..='\u{1d1}', '\u{1d3}'..='\u{1d3}', '\u{1d5}'..='\u{1d5}', '\u{1d7}'..='\u{1d7}', + '\u{1d9}'..='\u{1d9}', '\u{1db}'..='\u{1db}', '\u{1de}'..='\u{1de}', '\u{1e0}'..='\u{1e0}', + '\u{1e2}'..='\u{1e2}', '\u{1e4}'..='\u{1e4}', '\u{1e6}'..='\u{1e6}', '\u{1e8}'..='\u{1e8}', + '\u{1ea}'..='\u{1ea}', '\u{1ec}'..='\u{1ec}', '\u{1ee}'..='\u{1ee}', '\u{1f1}'..='\u{1f1}', + '\u{1f4}'..='\u{1f4}', '\u{1f6}'..='\u{1f8}', '\u{1fa}'..='\u{1fa}', '\u{1fc}'..='\u{1fc}', + '\u{1fe}'..='\u{1fe}', '\u{200}'..='\u{200}', '\u{202}'..='\u{202}', '\u{204}'..='\u{204}', + '\u{206}'..='\u{206}', '\u{208}'..='\u{208}', '\u{20a}'..='\u{20a}', '\u{20c}'..='\u{20c}', + '\u{20e}'..='\u{20e}', '\u{210}'..='\u{210}', '\u{212}'..='\u{212}', '\u{214}'..='\u{214}', + '\u{216}'..='\u{216}', '\u{218}'..='\u{218}', '\u{21a}'..='\u{21a}', '\u{21c}'..='\u{21c}', + '\u{21e}'..='\u{21e}', '\u{220}'..='\u{220}', '\u{222}'..='\u{222}', '\u{224}'..='\u{224}', + '\u{226}'..='\u{226}', '\u{228}'..='\u{228}', '\u{22a}'..='\u{22a}', '\u{22c}'..='\u{22c}', + '\u{22e}'..='\u{22e}', '\u{230}'..='\u{230}', '\u{232}'..='\u{232}', '\u{23a}'..='\u{23b}', + '\u{23d}'..='\u{23e}', '\u{241}'..='\u{241}', '\u{243}'..='\u{246}', '\u{248}'..='\u{248}', + '\u{24a}'..='\u{24a}', '\u{24c}'..='\u{24c}', '\u{24e}'..='\u{24e}', '\u{370}'..='\u{370}', + '\u{372}'..='\u{372}', '\u{376}'..='\u{376}', '\u{37f}'..='\u{37f}', '\u{386}'..='\u{386}', + '\u{388}'..='\u{38a}', '\u{38c}'..='\u{38c}', '\u{38e}'..='\u{38f}', '\u{391}'..='\u{3a1}', + '\u{3a3}'..='\u{3ab}', '\u{3cf}'..='\u{3cf}', '\u{3d2}'..='\u{3d4}', '\u{3d8}'..='\u{3d8}', + '\u{3da}'..='\u{3da}', '\u{3dc}'..='\u{3dc}', '\u{3de}'..='\u{3de}', '\u{3e0}'..='\u{3e0}', + '\u{3e2}'..='\u{3e2}', '\u{3e4}'..='\u{3e4}', '\u{3e6}'..='\u{3e6}', '\u{3e8}'..='\u{3e8}', + '\u{3ea}'..='\u{3ea}', '\u{3ec}'..='\u{3ec}', '\u{3ee}'..='\u{3ee}', '\u{3f4}'..='\u{3f4}', + '\u{3f7}'..='\u{3f7}', '\u{3f9}'..='\u{3fa}', '\u{3fd}'..='\u{42f}', '\u{460}'..='\u{460}', + '\u{462}'..='\u{462}', '\u{464}'..='\u{464}', '\u{466}'..='\u{466}', '\u{468}'..='\u{468}', + '\u{46a}'..='\u{46a}', '\u{46c}'..='\u{46c}', '\u{46e}'..='\u{46e}', '\u{470}'..='\u{470}', + '\u{472}'..='\u{472}', '\u{474}'..='\u{474}', '\u{476}'..='\u{476}', '\u{478}'..='\u{478}', + '\u{47a}'..='\u{47a}', '\u{47c}'..='\u{47c}', '\u{47e}'..='\u{47e}', '\u{480}'..='\u{480}', + '\u{48a}'..='\u{48a}', '\u{48c}'..='\u{48c}', '\u{48e}'..='\u{48e}', '\u{490}'..='\u{490}', + '\u{492}'..='\u{492}', '\u{494}'..='\u{494}', '\u{496}'..='\u{496}', '\u{498}'..='\u{498}', + '\u{49a}'..='\u{49a}', '\u{49c}'..='\u{49c}', '\u{49e}'..='\u{49e}', '\u{4a0}'..='\u{4a0}', + '\u{4a2}'..='\u{4a2}', '\u{4a4}'..='\u{4a4}', '\u{4a6}'..='\u{4a6}', '\u{4a8}'..='\u{4a8}', + '\u{4aa}'..='\u{4aa}', '\u{4ac}'..='\u{4ac}', '\u{4ae}'..='\u{4ae}', '\u{4b0}'..='\u{4b0}', + '\u{4b2}'..='\u{4b2}', '\u{4b4}'..='\u{4b4}', '\u{4b6}'..='\u{4b6}', '\u{4b8}'..='\u{4b8}', + '\u{4ba}'..='\u{4ba}', '\u{4bc}'..='\u{4bc}', '\u{4be}'..='\u{4be}', '\u{4c0}'..='\u{4c1}', + '\u{4c3}'..='\u{4c3}', '\u{4c5}'..='\u{4c5}', '\u{4c7}'..='\u{4c7}', '\u{4c9}'..='\u{4c9}', + '\u{4cb}'..='\u{4cb}', '\u{4cd}'..='\u{4cd}', '\u{4d0}'..='\u{4d0}', '\u{4d2}'..='\u{4d2}', + '\u{4d4}'..='\u{4d4}', '\u{4d6}'..='\u{4d6}', '\u{4d8}'..='\u{4d8}', '\u{4da}'..='\u{4da}', + '\u{4dc}'..='\u{4dc}', '\u{4de}'..='\u{4de}', '\u{4e0}'..='\u{4e0}', '\u{4e2}'..='\u{4e2}', + '\u{4e4}'..='\u{4e4}', '\u{4e6}'..='\u{4e6}', '\u{4e8}'..='\u{4e8}', '\u{4ea}'..='\u{4ea}', + '\u{4ec}'..='\u{4ec}', '\u{4ee}'..='\u{4ee}', '\u{4f0}'..='\u{4f0}', '\u{4f2}'..='\u{4f2}', + '\u{4f4}'..='\u{4f4}', '\u{4f6}'..='\u{4f6}', '\u{4f8}'..='\u{4f8}', '\u{4fa}'..='\u{4fa}', + '\u{4fc}'..='\u{4fc}', '\u{4fe}'..='\u{4fe}', '\u{500}'..='\u{500}', '\u{502}'..='\u{502}', + '\u{504}'..='\u{504}', '\u{506}'..='\u{506}', '\u{508}'..='\u{508}', '\u{50a}'..='\u{50a}', + '\u{50c}'..='\u{50c}', '\u{50e}'..='\u{50e}', '\u{510}'..='\u{510}', '\u{512}'..='\u{512}', + '\u{514}'..='\u{514}', '\u{516}'..='\u{516}', '\u{518}'..='\u{518}', '\u{51a}'..='\u{51a}', + '\u{51c}'..='\u{51c}', '\u{51e}'..='\u{51e}', '\u{520}'..='\u{520}', '\u{522}'..='\u{522}', + '\u{524}'..='\u{524}', '\u{526}'..='\u{526}', '\u{528}'..='\u{528}', '\u{52a}'..='\u{52a}', + '\u{52c}'..='\u{52c}', '\u{52e}'..='\u{52e}', '\u{531}'..='\u{556}', + '\u{10a0}'..='\u{10c5}', '\u{10c7}'..='\u{10c7}', '\u{10cd}'..='\u{10cd}', + '\u{13a0}'..='\u{13f5}', '\u{1c89}'..='\u{1c89}', '\u{1c90}'..='\u{1cba}', + '\u{1cbd}'..='\u{1cbf}', '\u{1e00}'..='\u{1e00}', '\u{1e02}'..='\u{1e02}', + '\u{1e04}'..='\u{1e04}', '\u{1e06}'..='\u{1e06}', '\u{1e08}'..='\u{1e08}', + '\u{1e0a}'..='\u{1e0a}', '\u{1e0c}'..='\u{1e0c}', '\u{1e0e}'..='\u{1e0e}', + '\u{1e10}'..='\u{1e10}', '\u{1e12}'..='\u{1e12}', '\u{1e14}'..='\u{1e14}', + '\u{1e16}'..='\u{1e16}', '\u{1e18}'..='\u{1e18}', '\u{1e1a}'..='\u{1e1a}', + '\u{1e1c}'..='\u{1e1c}', '\u{1e1e}'..='\u{1e1e}', '\u{1e20}'..='\u{1e20}', + '\u{1e22}'..='\u{1e22}', '\u{1e24}'..='\u{1e24}', '\u{1e26}'..='\u{1e26}', + '\u{1e28}'..='\u{1e28}', '\u{1e2a}'..='\u{1e2a}', '\u{1e2c}'..='\u{1e2c}', + '\u{1e2e}'..='\u{1e2e}', '\u{1e30}'..='\u{1e30}', '\u{1e32}'..='\u{1e32}', + '\u{1e34}'..='\u{1e34}', '\u{1e36}'..='\u{1e36}', '\u{1e38}'..='\u{1e38}', + '\u{1e3a}'..='\u{1e3a}', '\u{1e3c}'..='\u{1e3c}', '\u{1e3e}'..='\u{1e3e}', + '\u{1e40}'..='\u{1e40}', '\u{1e42}'..='\u{1e42}', '\u{1e44}'..='\u{1e44}', + '\u{1e46}'..='\u{1e46}', '\u{1e48}'..='\u{1e48}', '\u{1e4a}'..='\u{1e4a}', + '\u{1e4c}'..='\u{1e4c}', '\u{1e4e}'..='\u{1e4e}', '\u{1e50}'..='\u{1e50}', + '\u{1e52}'..='\u{1e52}', '\u{1e54}'..='\u{1e54}', '\u{1e56}'..='\u{1e56}', + '\u{1e58}'..='\u{1e58}', '\u{1e5a}'..='\u{1e5a}', '\u{1e5c}'..='\u{1e5c}', + '\u{1e5e}'..='\u{1e5e}', '\u{1e60}'..='\u{1e60}', '\u{1e62}'..='\u{1e62}', + '\u{1e64}'..='\u{1e64}', '\u{1e66}'..='\u{1e66}', '\u{1e68}'..='\u{1e68}', + '\u{1e6a}'..='\u{1e6a}', '\u{1e6c}'..='\u{1e6c}', '\u{1e6e}'..='\u{1e6e}', + '\u{1e70}'..='\u{1e70}', '\u{1e72}'..='\u{1e72}', '\u{1e74}'..='\u{1e74}', + '\u{1e76}'..='\u{1e76}', '\u{1e78}'..='\u{1e78}', '\u{1e7a}'..='\u{1e7a}', + '\u{1e7c}'..='\u{1e7c}', '\u{1e7e}'..='\u{1e7e}', '\u{1e80}'..='\u{1e80}', + '\u{1e82}'..='\u{1e82}', '\u{1e84}'..='\u{1e84}', '\u{1e86}'..='\u{1e86}', + '\u{1e88}'..='\u{1e88}', '\u{1e8a}'..='\u{1e8a}', '\u{1e8c}'..='\u{1e8c}', + '\u{1e8e}'..='\u{1e8e}', '\u{1e90}'..='\u{1e90}', '\u{1e92}'..='\u{1e92}', + '\u{1e94}'..='\u{1e94}', '\u{1e9e}'..='\u{1e9e}', '\u{1ea0}'..='\u{1ea0}', + '\u{1ea2}'..='\u{1ea2}', '\u{1ea4}'..='\u{1ea4}', '\u{1ea6}'..='\u{1ea6}', + '\u{1ea8}'..='\u{1ea8}', '\u{1eaa}'..='\u{1eaa}', '\u{1eac}'..='\u{1eac}', + '\u{1eae}'..='\u{1eae}', '\u{1eb0}'..='\u{1eb0}', '\u{1eb2}'..='\u{1eb2}', + '\u{1eb4}'..='\u{1eb4}', '\u{1eb6}'..='\u{1eb6}', '\u{1eb8}'..='\u{1eb8}', + '\u{1eba}'..='\u{1eba}', '\u{1ebc}'..='\u{1ebc}', '\u{1ebe}'..='\u{1ebe}', + '\u{1ec0}'..='\u{1ec0}', '\u{1ec2}'..='\u{1ec2}', '\u{1ec4}'..='\u{1ec4}', + '\u{1ec6}'..='\u{1ec6}', '\u{1ec8}'..='\u{1ec8}', '\u{1eca}'..='\u{1eca}', + '\u{1ecc}'..='\u{1ecc}', '\u{1ece}'..='\u{1ece}', '\u{1ed0}'..='\u{1ed0}', + '\u{1ed2}'..='\u{1ed2}', '\u{1ed4}'..='\u{1ed4}', '\u{1ed6}'..='\u{1ed6}', + '\u{1ed8}'..='\u{1ed8}', '\u{1eda}'..='\u{1eda}', '\u{1edc}'..='\u{1edc}', + '\u{1ede}'..='\u{1ede}', '\u{1ee0}'..='\u{1ee0}', '\u{1ee2}'..='\u{1ee2}', + '\u{1ee4}'..='\u{1ee4}', '\u{1ee6}'..='\u{1ee6}', '\u{1ee8}'..='\u{1ee8}', + '\u{1eea}'..='\u{1eea}', '\u{1eec}'..='\u{1eec}', '\u{1eee}'..='\u{1eee}', + '\u{1ef0}'..='\u{1ef0}', '\u{1ef2}'..='\u{1ef2}', '\u{1ef4}'..='\u{1ef4}', + '\u{1ef6}'..='\u{1ef6}', '\u{1ef8}'..='\u{1ef8}', '\u{1efa}'..='\u{1efa}', + '\u{1efc}'..='\u{1efc}', '\u{1efe}'..='\u{1efe}', '\u{1f08}'..='\u{1f0f}', + '\u{1f18}'..='\u{1f1d}', '\u{1f28}'..='\u{1f2f}', '\u{1f38}'..='\u{1f3f}', + '\u{1f48}'..='\u{1f4d}', '\u{1f59}'..='\u{1f59}', '\u{1f5b}'..='\u{1f5b}', + '\u{1f5d}'..='\u{1f5d}', '\u{1f5f}'..='\u{1f5f}', '\u{1f68}'..='\u{1f6f}', + '\u{1fb8}'..='\u{1fbb}', '\u{1fc8}'..='\u{1fcb}', '\u{1fd8}'..='\u{1fdb}', + '\u{1fe8}'..='\u{1fec}', '\u{1ff8}'..='\u{1ffb}', '\u{2102}'..='\u{2102}', + '\u{2107}'..='\u{2107}', '\u{210b}'..='\u{210d}', '\u{2110}'..='\u{2112}', + '\u{2115}'..='\u{2115}', '\u{2119}'..='\u{211d}', '\u{2124}'..='\u{2124}', + '\u{2126}'..='\u{2126}', '\u{2128}'..='\u{2128}', '\u{212a}'..='\u{212d}', + '\u{2130}'..='\u{2133}', '\u{213e}'..='\u{213f}', '\u{2145}'..='\u{2145}', + '\u{2160}'..='\u{216f}', '\u{2183}'..='\u{2183}', '\u{24b6}'..='\u{24cf}', + '\u{2c00}'..='\u{2c2f}', '\u{2c60}'..='\u{2c60}', '\u{2c62}'..='\u{2c64}', + '\u{2c67}'..='\u{2c67}', '\u{2c69}'..='\u{2c69}', '\u{2c6b}'..='\u{2c6b}', + '\u{2c6d}'..='\u{2c70}', '\u{2c72}'..='\u{2c72}', '\u{2c75}'..='\u{2c75}', + '\u{2c7e}'..='\u{2c80}', '\u{2c82}'..='\u{2c82}', '\u{2c84}'..='\u{2c84}', + '\u{2c86}'..='\u{2c86}', '\u{2c88}'..='\u{2c88}', '\u{2c8a}'..='\u{2c8a}', + '\u{2c8c}'..='\u{2c8c}', '\u{2c8e}'..='\u{2c8e}', '\u{2c90}'..='\u{2c90}', + '\u{2c92}'..='\u{2c92}', '\u{2c94}'..='\u{2c94}', '\u{2c96}'..='\u{2c96}', + '\u{2c98}'..='\u{2c98}', '\u{2c9a}'..='\u{2c9a}', '\u{2c9c}'..='\u{2c9c}', + '\u{2c9e}'..='\u{2c9e}', '\u{2ca0}'..='\u{2ca0}', '\u{2ca2}'..='\u{2ca2}', + '\u{2ca4}'..='\u{2ca4}', '\u{2ca6}'..='\u{2ca6}', '\u{2ca8}'..='\u{2ca8}', + '\u{2caa}'..='\u{2caa}', '\u{2cac}'..='\u{2cac}', '\u{2cae}'..='\u{2cae}', + '\u{2cb0}'..='\u{2cb0}', '\u{2cb2}'..='\u{2cb2}', '\u{2cb4}'..='\u{2cb4}', + '\u{2cb6}'..='\u{2cb6}', '\u{2cb8}'..='\u{2cb8}', '\u{2cba}'..='\u{2cba}', + '\u{2cbc}'..='\u{2cbc}', '\u{2cbe}'..='\u{2cbe}', '\u{2cc0}'..='\u{2cc0}', + '\u{2cc2}'..='\u{2cc2}', '\u{2cc4}'..='\u{2cc4}', '\u{2cc6}'..='\u{2cc6}', + '\u{2cc8}'..='\u{2cc8}', '\u{2cca}'..='\u{2cca}', '\u{2ccc}'..='\u{2ccc}', + '\u{2cce}'..='\u{2cce}', '\u{2cd0}'..='\u{2cd0}', '\u{2cd2}'..='\u{2cd2}', + '\u{2cd4}'..='\u{2cd4}', '\u{2cd6}'..='\u{2cd6}', '\u{2cd8}'..='\u{2cd8}', + '\u{2cda}'..='\u{2cda}', '\u{2cdc}'..='\u{2cdc}', '\u{2cde}'..='\u{2cde}', + '\u{2ce0}'..='\u{2ce0}', '\u{2ce2}'..='\u{2ce2}', '\u{2ceb}'..='\u{2ceb}', + '\u{2ced}'..='\u{2ced}', '\u{2cf2}'..='\u{2cf2}', '\u{a640}'..='\u{a640}', + '\u{a642}'..='\u{a642}', '\u{a644}'..='\u{a644}', '\u{a646}'..='\u{a646}', + '\u{a648}'..='\u{a648}', '\u{a64a}'..='\u{a64a}', '\u{a64c}'..='\u{a64c}', + '\u{a64e}'..='\u{a64e}', '\u{a650}'..='\u{a650}', '\u{a652}'..='\u{a652}', + '\u{a654}'..='\u{a654}', '\u{a656}'..='\u{a656}', '\u{a658}'..='\u{a658}', + '\u{a65a}'..='\u{a65a}', '\u{a65c}'..='\u{a65c}', '\u{a65e}'..='\u{a65e}', + '\u{a660}'..='\u{a660}', '\u{a662}'..='\u{a662}', '\u{a664}'..='\u{a664}', + '\u{a666}'..='\u{a666}', '\u{a668}'..='\u{a668}', '\u{a66a}'..='\u{a66a}', + '\u{a66c}'..='\u{a66c}', '\u{a680}'..='\u{a680}', '\u{a682}'..='\u{a682}', + '\u{a684}'..='\u{a684}', '\u{a686}'..='\u{a686}', '\u{a688}'..='\u{a688}', + '\u{a68a}'..='\u{a68a}', '\u{a68c}'..='\u{a68c}', '\u{a68e}'..='\u{a68e}', + '\u{a690}'..='\u{a690}', '\u{a692}'..='\u{a692}', '\u{a694}'..='\u{a694}', + '\u{a696}'..='\u{a696}', '\u{a698}'..='\u{a698}', '\u{a69a}'..='\u{a69a}', + '\u{a722}'..='\u{a722}', '\u{a724}'..='\u{a724}', '\u{a726}'..='\u{a726}', + '\u{a728}'..='\u{a728}', '\u{a72a}'..='\u{a72a}', '\u{a72c}'..='\u{a72c}', + '\u{a72e}'..='\u{a72e}', '\u{a732}'..='\u{a732}', '\u{a734}'..='\u{a734}', + '\u{a736}'..='\u{a736}', '\u{a738}'..='\u{a738}', '\u{a73a}'..='\u{a73a}', + '\u{a73c}'..='\u{a73c}', '\u{a73e}'..='\u{a73e}', '\u{a740}'..='\u{a740}', + '\u{a742}'..='\u{a742}', '\u{a744}'..='\u{a744}', '\u{a746}'..='\u{a746}', + '\u{a748}'..='\u{a748}', '\u{a74a}'..='\u{a74a}', '\u{a74c}'..='\u{a74c}', + '\u{a74e}'..='\u{a74e}', '\u{a750}'..='\u{a750}', '\u{a752}'..='\u{a752}', + '\u{a754}'..='\u{a754}', '\u{a756}'..='\u{a756}', '\u{a758}'..='\u{a758}', + '\u{a75a}'..='\u{a75a}', '\u{a75c}'..='\u{a75c}', '\u{a75e}'..='\u{a75e}', + '\u{a760}'..='\u{a760}', '\u{a762}'..='\u{a762}', '\u{a764}'..='\u{a764}', + '\u{a766}'..='\u{a766}', '\u{a768}'..='\u{a768}', '\u{a76a}'..='\u{a76a}', + '\u{a76c}'..='\u{a76c}', '\u{a76e}'..='\u{a76e}', '\u{a779}'..='\u{a779}', + '\u{a77b}'..='\u{a77b}', '\u{a77d}'..='\u{a77e}', '\u{a780}'..='\u{a780}', + '\u{a782}'..='\u{a782}', '\u{a784}'..='\u{a784}', '\u{a786}'..='\u{a786}', + '\u{a78b}'..='\u{a78b}', '\u{a78d}'..='\u{a78d}', '\u{a790}'..='\u{a790}', + '\u{a792}'..='\u{a792}', '\u{a796}'..='\u{a796}', '\u{a798}'..='\u{a798}', + '\u{a79a}'..='\u{a79a}', '\u{a79c}'..='\u{a79c}', '\u{a79e}'..='\u{a79e}', + '\u{a7a0}'..='\u{a7a0}', '\u{a7a2}'..='\u{a7a2}', '\u{a7a4}'..='\u{a7a4}', + '\u{a7a6}'..='\u{a7a6}', '\u{a7a8}'..='\u{a7a8}', '\u{a7aa}'..='\u{a7ae}', + '\u{a7b0}'..='\u{a7b4}', '\u{a7b6}'..='\u{a7b6}', '\u{a7b8}'..='\u{a7b8}', + '\u{a7ba}'..='\u{a7ba}', '\u{a7bc}'..='\u{a7bc}', '\u{a7be}'..='\u{a7be}', + '\u{a7c0}'..='\u{a7c0}', '\u{a7c2}'..='\u{a7c2}', '\u{a7c4}'..='\u{a7c7}', + '\u{a7c9}'..='\u{a7c9}', '\u{a7cb}'..='\u{a7cc}', '\u{a7ce}'..='\u{a7ce}', + '\u{a7d0}'..='\u{a7d0}', '\u{a7d2}'..='\u{a7d2}', '\u{a7d4}'..='\u{a7d4}', + '\u{a7d6}'..='\u{a7d6}', '\u{a7d8}'..='\u{a7d8}', '\u{a7da}'..='\u{a7da}', + '\u{a7dc}'..='\u{a7dc}', '\u{a7f5}'..='\u{a7f5}', '\u{ff21}'..='\u{ff3a}', + '\u{10400}'..='\u{10427}', '\u{104b0}'..='\u{104d3}', '\u{10570}'..='\u{1057a}', + '\u{1057c}'..='\u{1058a}', '\u{1058c}'..='\u{10592}', '\u{10594}'..='\u{10595}', + '\u{10c80}'..='\u{10cb2}', '\u{10d50}'..='\u{10d65}', '\u{118a0}'..='\u{118bf}', + '\u{16e40}'..='\u{16e5f}', '\u{16ea0}'..='\u{16eb8}', '\u{1d400}'..='\u{1d419}', + '\u{1d434}'..='\u{1d44d}', '\u{1d468}'..='\u{1d481}', '\u{1d49c}'..='\u{1d49c}', + '\u{1d49e}'..='\u{1d49f}', '\u{1d4a2}'..='\u{1d4a2}', '\u{1d4a5}'..='\u{1d4a6}', + '\u{1d4a9}'..='\u{1d4ac}', '\u{1d4ae}'..='\u{1d4b5}', '\u{1d4d0}'..='\u{1d4e9}', + '\u{1d504}'..='\u{1d505}', '\u{1d507}'..='\u{1d50a}', '\u{1d50d}'..='\u{1d514}', + '\u{1d516}'..='\u{1d51c}', '\u{1d538}'..='\u{1d539}', '\u{1d53b}'..='\u{1d53e}', + '\u{1d540}'..='\u{1d544}', '\u{1d546}'..='\u{1d546}', '\u{1d54a}'..='\u{1d550}', + '\u{1d56c}'..='\u{1d585}', '\u{1d5a0}'..='\u{1d5b9}', '\u{1d5d4}'..='\u{1d5ed}', + '\u{1d608}'..='\u{1d621}', '\u{1d63c}'..='\u{1d655}', '\u{1d670}'..='\u{1d689}', + '\u{1d6a8}'..='\u{1d6c0}', '\u{1d6e2}'..='\u{1d6fa}', '\u{1d71c}'..='\u{1d734}', + '\u{1d756}'..='\u{1d76e}', '\u{1d790}'..='\u{1d7a8}', '\u{1d7ca}'..='\u{1d7ca}', + '\u{1e900}'..='\u{1e921}', '\u{1f130}'..='\u{1f149}', '\u{1f150}'..='\u{1f169}', + '\u{1f170}'..='\u{1f189}', +]; + +#[rustfmt::skip] +pub(super) static WHITE_SPACE: &[RangeInclusive; 8] = &[ + '\u{85}'..='\u{85}', '\u{a0}'..='\u{a0}', '\u{1680}'..='\u{1680}', '\u{2000}'..='\u{200a}', + '\u{2028}'..='\u{2029}', '\u{202f}'..='\u{202f}', '\u{205f}'..='\u{205f}', + '\u{3000}'..='\u{3000}', +]; + +#[rustfmt::skip] +pub(super) static TO_LOWER: &[(char, [char; 3]); 1462] = &[ + ('\u{c0}', ['\u{e0}', '\u{0}', '\u{0}']), ('\u{c1}', ['\u{e1}', '\u{0}', '\u{0}']), + ('\u{c2}', ['\u{e2}', '\u{0}', '\u{0}']), ('\u{c3}', ['\u{e3}', '\u{0}', '\u{0}']), + ('\u{c4}', ['\u{e4}', '\u{0}', '\u{0}']), ('\u{c5}', ['\u{e5}', '\u{0}', '\u{0}']), + ('\u{c6}', ['\u{e6}', '\u{0}', '\u{0}']), ('\u{c7}', ['\u{e7}', '\u{0}', '\u{0}']), + ('\u{c8}', ['\u{e8}', '\u{0}', '\u{0}']), ('\u{c9}', ['\u{e9}', '\u{0}', '\u{0}']), + ('\u{ca}', ['\u{ea}', '\u{0}', '\u{0}']), ('\u{cb}', ['\u{eb}', '\u{0}', '\u{0}']), + ('\u{cc}', ['\u{ec}', '\u{0}', '\u{0}']), ('\u{cd}', ['\u{ed}', '\u{0}', '\u{0}']), + ('\u{ce}', ['\u{ee}', '\u{0}', '\u{0}']), ('\u{cf}', ['\u{ef}', '\u{0}', '\u{0}']), + ('\u{d0}', ['\u{f0}', '\u{0}', '\u{0}']), ('\u{d1}', ['\u{f1}', '\u{0}', '\u{0}']), + ('\u{d2}', ['\u{f2}', '\u{0}', '\u{0}']), ('\u{d3}', ['\u{f3}', '\u{0}', '\u{0}']), + ('\u{d4}', ['\u{f4}', '\u{0}', '\u{0}']), ('\u{d5}', ['\u{f5}', '\u{0}', '\u{0}']), + ('\u{d6}', ['\u{f6}', '\u{0}', '\u{0}']), ('\u{d8}', ['\u{f8}', '\u{0}', '\u{0}']), + ('\u{d9}', ['\u{f9}', '\u{0}', '\u{0}']), ('\u{da}', ['\u{fa}', '\u{0}', '\u{0}']), + ('\u{db}', ['\u{fb}', '\u{0}', '\u{0}']), ('\u{dc}', ['\u{fc}', '\u{0}', '\u{0}']), + ('\u{dd}', ['\u{fd}', '\u{0}', '\u{0}']), ('\u{de}', ['\u{fe}', '\u{0}', '\u{0}']), + ('\u{100}', ['\u{101}', '\u{0}', '\u{0}']), ('\u{102}', ['\u{103}', '\u{0}', '\u{0}']), + ('\u{104}', ['\u{105}', '\u{0}', '\u{0}']), ('\u{106}', ['\u{107}', '\u{0}', '\u{0}']), + ('\u{108}', ['\u{109}', '\u{0}', '\u{0}']), ('\u{10a}', ['\u{10b}', '\u{0}', '\u{0}']), + ('\u{10c}', ['\u{10d}', '\u{0}', '\u{0}']), ('\u{10e}', ['\u{10f}', '\u{0}', '\u{0}']), + ('\u{110}', ['\u{111}', '\u{0}', '\u{0}']), ('\u{112}', ['\u{113}', '\u{0}', '\u{0}']), + ('\u{114}', ['\u{115}', '\u{0}', '\u{0}']), ('\u{116}', ['\u{117}', '\u{0}', '\u{0}']), + ('\u{118}', ['\u{119}', '\u{0}', '\u{0}']), ('\u{11a}', ['\u{11b}', '\u{0}', '\u{0}']), + ('\u{11c}', ['\u{11d}', '\u{0}', '\u{0}']), ('\u{11e}', ['\u{11f}', '\u{0}', '\u{0}']), + ('\u{120}', ['\u{121}', '\u{0}', '\u{0}']), ('\u{122}', ['\u{123}', '\u{0}', '\u{0}']), + ('\u{124}', ['\u{125}', '\u{0}', '\u{0}']), ('\u{126}', ['\u{127}', '\u{0}', '\u{0}']), + ('\u{128}', ['\u{129}', '\u{0}', '\u{0}']), ('\u{12a}', ['\u{12b}', '\u{0}', '\u{0}']), + ('\u{12c}', ['\u{12d}', '\u{0}', '\u{0}']), ('\u{12e}', ['\u{12f}', '\u{0}', '\u{0}']), + ('\u{130}', ['i', '\u{307}', '\u{0}']), ('\u{132}', ['\u{133}', '\u{0}', '\u{0}']), + ('\u{134}', ['\u{135}', '\u{0}', '\u{0}']), ('\u{136}', ['\u{137}', '\u{0}', '\u{0}']), + ('\u{139}', ['\u{13a}', '\u{0}', '\u{0}']), ('\u{13b}', ['\u{13c}', '\u{0}', '\u{0}']), + ('\u{13d}', ['\u{13e}', '\u{0}', '\u{0}']), ('\u{13f}', ['\u{140}', '\u{0}', '\u{0}']), + ('\u{141}', ['\u{142}', '\u{0}', '\u{0}']), ('\u{143}', ['\u{144}', '\u{0}', '\u{0}']), + ('\u{145}', ['\u{146}', '\u{0}', '\u{0}']), ('\u{147}', ['\u{148}', '\u{0}', '\u{0}']), + ('\u{14a}', ['\u{14b}', '\u{0}', '\u{0}']), ('\u{14c}', ['\u{14d}', '\u{0}', '\u{0}']), + ('\u{14e}', ['\u{14f}', '\u{0}', '\u{0}']), ('\u{150}', ['\u{151}', '\u{0}', '\u{0}']), + ('\u{152}', ['\u{153}', '\u{0}', '\u{0}']), ('\u{154}', ['\u{155}', '\u{0}', '\u{0}']), + ('\u{156}', ['\u{157}', '\u{0}', '\u{0}']), ('\u{158}', ['\u{159}', '\u{0}', '\u{0}']), + ('\u{15a}', ['\u{15b}', '\u{0}', '\u{0}']), ('\u{15c}', ['\u{15d}', '\u{0}', '\u{0}']), + ('\u{15e}', ['\u{15f}', '\u{0}', '\u{0}']), ('\u{160}', ['\u{161}', '\u{0}', '\u{0}']), + ('\u{162}', ['\u{163}', '\u{0}', '\u{0}']), ('\u{164}', ['\u{165}', '\u{0}', '\u{0}']), + ('\u{166}', ['\u{167}', '\u{0}', '\u{0}']), ('\u{168}', ['\u{169}', '\u{0}', '\u{0}']), + ('\u{16a}', ['\u{16b}', '\u{0}', '\u{0}']), ('\u{16c}', ['\u{16d}', '\u{0}', '\u{0}']), + ('\u{16e}', ['\u{16f}', '\u{0}', '\u{0}']), ('\u{170}', ['\u{171}', '\u{0}', '\u{0}']), + ('\u{172}', ['\u{173}', '\u{0}', '\u{0}']), ('\u{174}', ['\u{175}', '\u{0}', '\u{0}']), + ('\u{176}', ['\u{177}', '\u{0}', '\u{0}']), ('\u{178}', ['\u{ff}', '\u{0}', '\u{0}']), + ('\u{179}', ['\u{17a}', '\u{0}', '\u{0}']), ('\u{17b}', ['\u{17c}', '\u{0}', '\u{0}']), + ('\u{17d}', ['\u{17e}', '\u{0}', '\u{0}']), ('\u{181}', ['\u{253}', '\u{0}', '\u{0}']), + ('\u{182}', ['\u{183}', '\u{0}', '\u{0}']), ('\u{184}', ['\u{185}', '\u{0}', '\u{0}']), + ('\u{186}', ['\u{254}', '\u{0}', '\u{0}']), ('\u{187}', ['\u{188}', '\u{0}', '\u{0}']), + ('\u{189}', ['\u{256}', '\u{0}', '\u{0}']), ('\u{18a}', ['\u{257}', '\u{0}', '\u{0}']), + ('\u{18b}', ['\u{18c}', '\u{0}', '\u{0}']), ('\u{18e}', ['\u{1dd}', '\u{0}', '\u{0}']), + ('\u{18f}', ['\u{259}', '\u{0}', '\u{0}']), ('\u{190}', ['\u{25b}', '\u{0}', '\u{0}']), + ('\u{191}', ['\u{192}', '\u{0}', '\u{0}']), ('\u{193}', ['\u{260}', '\u{0}', '\u{0}']), + ('\u{194}', ['\u{263}', '\u{0}', '\u{0}']), ('\u{196}', ['\u{269}', '\u{0}', '\u{0}']), + ('\u{197}', ['\u{268}', '\u{0}', '\u{0}']), ('\u{198}', ['\u{199}', '\u{0}', '\u{0}']), + ('\u{19c}', ['\u{26f}', '\u{0}', '\u{0}']), ('\u{19d}', ['\u{272}', '\u{0}', '\u{0}']), + ('\u{19f}', ['\u{275}', '\u{0}', '\u{0}']), ('\u{1a0}', ['\u{1a1}', '\u{0}', '\u{0}']), + ('\u{1a2}', ['\u{1a3}', '\u{0}', '\u{0}']), ('\u{1a4}', ['\u{1a5}', '\u{0}', '\u{0}']), + ('\u{1a6}', ['\u{280}', '\u{0}', '\u{0}']), ('\u{1a7}', ['\u{1a8}', '\u{0}', '\u{0}']), + ('\u{1a9}', ['\u{283}', '\u{0}', '\u{0}']), ('\u{1ac}', ['\u{1ad}', '\u{0}', '\u{0}']), + ('\u{1ae}', ['\u{288}', '\u{0}', '\u{0}']), ('\u{1af}', ['\u{1b0}', '\u{0}', '\u{0}']), + ('\u{1b1}', ['\u{28a}', '\u{0}', '\u{0}']), ('\u{1b2}', ['\u{28b}', '\u{0}', '\u{0}']), + ('\u{1b3}', ['\u{1b4}', '\u{0}', '\u{0}']), ('\u{1b5}', ['\u{1b6}', '\u{0}', '\u{0}']), + ('\u{1b7}', ['\u{292}', '\u{0}', '\u{0}']), ('\u{1b8}', ['\u{1b9}', '\u{0}', '\u{0}']), + ('\u{1bc}', ['\u{1bd}', '\u{0}', '\u{0}']), ('\u{1c4}', ['\u{1c6}', '\u{0}', '\u{0}']), + ('\u{1c5}', ['\u{1c6}', '\u{0}', '\u{0}']), ('\u{1c7}', ['\u{1c9}', '\u{0}', '\u{0}']), + ('\u{1c8}', ['\u{1c9}', '\u{0}', '\u{0}']), ('\u{1ca}', ['\u{1cc}', '\u{0}', '\u{0}']), + ('\u{1cb}', ['\u{1cc}', '\u{0}', '\u{0}']), ('\u{1cd}', ['\u{1ce}', '\u{0}', '\u{0}']), + ('\u{1cf}', ['\u{1d0}', '\u{0}', '\u{0}']), ('\u{1d1}', ['\u{1d2}', '\u{0}', '\u{0}']), + ('\u{1d3}', ['\u{1d4}', '\u{0}', '\u{0}']), ('\u{1d5}', ['\u{1d6}', '\u{0}', '\u{0}']), + ('\u{1d7}', ['\u{1d8}', '\u{0}', '\u{0}']), ('\u{1d9}', ['\u{1da}', '\u{0}', '\u{0}']), + ('\u{1db}', ['\u{1dc}', '\u{0}', '\u{0}']), ('\u{1de}', ['\u{1df}', '\u{0}', '\u{0}']), + ('\u{1e0}', ['\u{1e1}', '\u{0}', '\u{0}']), ('\u{1e2}', ['\u{1e3}', '\u{0}', '\u{0}']), + ('\u{1e4}', ['\u{1e5}', '\u{0}', '\u{0}']), ('\u{1e6}', ['\u{1e7}', '\u{0}', '\u{0}']), + ('\u{1e8}', ['\u{1e9}', '\u{0}', '\u{0}']), ('\u{1ea}', ['\u{1eb}', '\u{0}', '\u{0}']), + ('\u{1ec}', ['\u{1ed}', '\u{0}', '\u{0}']), ('\u{1ee}', ['\u{1ef}', '\u{0}', '\u{0}']), + ('\u{1f1}', ['\u{1f3}', '\u{0}', '\u{0}']), ('\u{1f2}', ['\u{1f3}', '\u{0}', '\u{0}']), + ('\u{1f4}', ['\u{1f5}', '\u{0}', '\u{0}']), ('\u{1f6}', ['\u{195}', '\u{0}', '\u{0}']), + ('\u{1f7}', ['\u{1bf}', '\u{0}', '\u{0}']), ('\u{1f8}', ['\u{1f9}', '\u{0}', '\u{0}']), + ('\u{1fa}', ['\u{1fb}', '\u{0}', '\u{0}']), ('\u{1fc}', ['\u{1fd}', '\u{0}', '\u{0}']), + ('\u{1fe}', ['\u{1ff}', '\u{0}', '\u{0}']), ('\u{200}', ['\u{201}', '\u{0}', '\u{0}']), + ('\u{202}', ['\u{203}', '\u{0}', '\u{0}']), ('\u{204}', ['\u{205}', '\u{0}', '\u{0}']), + ('\u{206}', ['\u{207}', '\u{0}', '\u{0}']), ('\u{208}', ['\u{209}', '\u{0}', '\u{0}']), + ('\u{20a}', ['\u{20b}', '\u{0}', '\u{0}']), ('\u{20c}', ['\u{20d}', '\u{0}', '\u{0}']), + ('\u{20e}', ['\u{20f}', '\u{0}', '\u{0}']), ('\u{210}', ['\u{211}', '\u{0}', '\u{0}']), + ('\u{212}', ['\u{213}', '\u{0}', '\u{0}']), ('\u{214}', ['\u{215}', '\u{0}', '\u{0}']), + ('\u{216}', ['\u{217}', '\u{0}', '\u{0}']), ('\u{218}', ['\u{219}', '\u{0}', '\u{0}']), + ('\u{21a}', ['\u{21b}', '\u{0}', '\u{0}']), ('\u{21c}', ['\u{21d}', '\u{0}', '\u{0}']), + ('\u{21e}', ['\u{21f}', '\u{0}', '\u{0}']), ('\u{220}', ['\u{19e}', '\u{0}', '\u{0}']), + ('\u{222}', ['\u{223}', '\u{0}', '\u{0}']), ('\u{224}', ['\u{225}', '\u{0}', '\u{0}']), + ('\u{226}', ['\u{227}', '\u{0}', '\u{0}']), ('\u{228}', ['\u{229}', '\u{0}', '\u{0}']), + ('\u{22a}', ['\u{22b}', '\u{0}', '\u{0}']), ('\u{22c}', ['\u{22d}', '\u{0}', '\u{0}']), + ('\u{22e}', ['\u{22f}', '\u{0}', '\u{0}']), ('\u{230}', ['\u{231}', '\u{0}', '\u{0}']), + ('\u{232}', ['\u{233}', '\u{0}', '\u{0}']), ('\u{23a}', ['\u{2c65}', '\u{0}', '\u{0}']), + ('\u{23b}', ['\u{23c}', '\u{0}', '\u{0}']), ('\u{23d}', ['\u{19a}', '\u{0}', '\u{0}']), + ('\u{23e}', ['\u{2c66}', '\u{0}', '\u{0}']), ('\u{241}', ['\u{242}', '\u{0}', '\u{0}']), + ('\u{243}', ['\u{180}', '\u{0}', '\u{0}']), ('\u{244}', ['\u{289}', '\u{0}', '\u{0}']), + ('\u{245}', ['\u{28c}', '\u{0}', '\u{0}']), ('\u{246}', ['\u{247}', '\u{0}', '\u{0}']), + ('\u{248}', ['\u{249}', '\u{0}', '\u{0}']), ('\u{24a}', ['\u{24b}', '\u{0}', '\u{0}']), + ('\u{24c}', ['\u{24d}', '\u{0}', '\u{0}']), ('\u{24e}', ['\u{24f}', '\u{0}', '\u{0}']), + ('\u{370}', ['\u{371}', '\u{0}', '\u{0}']), ('\u{372}', ['\u{373}', '\u{0}', '\u{0}']), + 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('\u{39e}', ['\u{3be}', '\u{0}', '\u{0}']), ('\u{39f}', ['\u{3bf}', '\u{0}', '\u{0}']), + ('\u{3a0}', ['\u{3c0}', '\u{0}', '\u{0}']), ('\u{3a1}', ['\u{3c1}', '\u{0}', '\u{0}']), + ('\u{3a3}', ['\u{3c3}', '\u{0}', '\u{0}']), ('\u{3a4}', ['\u{3c4}', '\u{0}', '\u{0}']), + ('\u{3a5}', ['\u{3c5}', '\u{0}', '\u{0}']), ('\u{3a6}', ['\u{3c6}', '\u{0}', '\u{0}']), + ('\u{3a7}', ['\u{3c7}', '\u{0}', '\u{0}']), ('\u{3a8}', ['\u{3c8}', '\u{0}', '\u{0}']), + ('\u{3a9}', ['\u{3c9}', '\u{0}', '\u{0}']), ('\u{3aa}', ['\u{3ca}', '\u{0}', '\u{0}']), + ('\u{3ab}', ['\u{3cb}', '\u{0}', '\u{0}']), ('\u{3cf}', ['\u{3d7}', '\u{0}', '\u{0}']), + ('\u{3d8}', ['\u{3d9}', '\u{0}', '\u{0}']), ('\u{3da}', ['\u{3db}', '\u{0}', '\u{0}']), + ('\u{3dc}', ['\u{3dd}', '\u{0}', '\u{0}']), ('\u{3de}', ['\u{3df}', '\u{0}', '\u{0}']), + ('\u{3e0}', ['\u{3e1}', '\u{0}', '\u{0}']), ('\u{3e2}', ['\u{3e3}', '\u{0}', '\u{0}']), + ('\u{3e4}', ['\u{3e5}', '\u{0}', '\u{0}']), ('\u{3e6}', ['\u{3e7}', '\u{0}', '\u{0}']), + ('\u{3e8}', ['\u{3e9}', '\u{0}', '\u{0}']), ('\u{3ea}', ['\u{3eb}', '\u{0}', '\u{0}']), + ('\u{3ec}', ['\u{3ed}', '\u{0}', '\u{0}']), ('\u{3ee}', ['\u{3ef}', '\u{0}', '\u{0}']), + ('\u{3f4}', ['\u{3b8}', '\u{0}', '\u{0}']), ('\u{3f7}', ['\u{3f8}', '\u{0}', '\u{0}']), + ('\u{3f9}', ['\u{3f2}', '\u{0}', '\u{0}']), ('\u{3fa}', ['\u{3fb}', '\u{0}', '\u{0}']), + ('\u{3fd}', ['\u{37b}', '\u{0}', '\u{0}']), ('\u{3fe}', ['\u{37c}', '\u{0}', '\u{0}']), + ('\u{3ff}', ['\u{37d}', '\u{0}', '\u{0}']), ('\u{400}', ['\u{450}', '\u{0}', '\u{0}']), + ('\u{401}', ['\u{451}', '\u{0}', '\u{0}']), ('\u{402}', ['\u{452}', '\u{0}', '\u{0}']), + ('\u{403}', ['\u{453}', '\u{0}', '\u{0}']), ('\u{404}', ['\u{454}', '\u{0}', '\u{0}']), + ('\u{405}', ['\u{455}', '\u{0}', '\u{0}']), ('\u{406}', ['\u{456}', '\u{0}', '\u{0}']), + ('\u{407}', ['\u{457}', '\u{0}', '\u{0}']), ('\u{408}', ['\u{458}', '\u{0}', '\u{0}']), + ('\u{409}', ['\u{459}', '\u{0}', '\u{0}']), ('\u{40a}', ['\u{45a}', '\u{0}', '\u{0}']), + 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['\u{2d16}', '\u{0}', '\u{0}']), + ('\u{10b7}', ['\u{2d17}', '\u{0}', '\u{0}']), ('\u{10b8}', ['\u{2d18}', '\u{0}', '\u{0}']), + ('\u{10b9}', ['\u{2d19}', '\u{0}', '\u{0}']), ('\u{10ba}', ['\u{2d1a}', '\u{0}', '\u{0}']), + ('\u{10bb}', ['\u{2d1b}', '\u{0}', '\u{0}']), ('\u{10bc}', ['\u{2d1c}', '\u{0}', '\u{0}']), + ('\u{10bd}', ['\u{2d1d}', '\u{0}', '\u{0}']), ('\u{10be}', ['\u{2d1e}', '\u{0}', '\u{0}']), + ('\u{10bf}', ['\u{2d1f}', '\u{0}', '\u{0}']), ('\u{10c0}', ['\u{2d20}', '\u{0}', '\u{0}']), + ('\u{10c1}', ['\u{2d21}', '\u{0}', '\u{0}']), ('\u{10c2}', ['\u{2d22}', '\u{0}', '\u{0}']), + ('\u{10c3}', ['\u{2d23}', '\u{0}', '\u{0}']), ('\u{10c4}', ['\u{2d24}', '\u{0}', '\u{0}']), + ('\u{10c5}', ['\u{2d25}', '\u{0}', '\u{0}']), ('\u{10c7}', ['\u{2d27}', '\u{0}', '\u{0}']), + ('\u{10cd}', ['\u{2d2d}', '\u{0}', '\u{0}']), ('\u{13a0}', ['\u{ab70}', '\u{0}', '\u{0}']), + ('\u{13a1}', ['\u{ab71}', '\u{0}', '\u{0}']), ('\u{13a2}', ['\u{ab72}', '\u{0}', '\u{0}']), + ('\u{13a3}', ['\u{ab73}', '\u{0}', '\u{0}']), ('\u{13a4}', ['\u{ab74}', '\u{0}', '\u{0}']), + ('\u{13a5}', ['\u{ab75}', '\u{0}', '\u{0}']), ('\u{13a6}', ['\u{ab76}', '\u{0}', '\u{0}']), + ('\u{13a7}', ['\u{ab77}', '\u{0}', '\u{0}']), ('\u{13a8}', ['\u{ab78}', '\u{0}', '\u{0}']), + ('\u{13a9}', ['\u{ab79}', '\u{0}', '\u{0}']), ('\u{13aa}', ['\u{ab7a}', '\u{0}', '\u{0}']), + ('\u{13ab}', ['\u{ab7b}', '\u{0}', '\u{0}']), ('\u{13ac}', ['\u{ab7c}', '\u{0}', '\u{0}']), + ('\u{13ad}', ['\u{ab7d}', '\u{0}', '\u{0}']), ('\u{13ae}', ['\u{ab7e}', '\u{0}', '\u{0}']), + ('\u{13af}', ['\u{ab7f}', '\u{0}', '\u{0}']), ('\u{13b0}', ['\u{ab80}', '\u{0}', '\u{0}']), + ('\u{13b1}', ['\u{ab81}', '\u{0}', '\u{0}']), ('\u{13b2}', ['\u{ab82}', '\u{0}', '\u{0}']), + ('\u{13b3}', ['\u{ab83}', '\u{0}', '\u{0}']), ('\u{13b4}', ['\u{ab84}', '\u{0}', '\u{0}']), + ('\u{13b5}', ['\u{ab85}', '\u{0}', '\u{0}']), ('\u{13b6}', ['\u{ab86}', '\u{0}', '\u{0}']), + ('\u{13b7}', ['\u{ab87}', '\u{0}', '\u{0}']), ('\u{13b8}', ['\u{ab88}', '\u{0}', '\u{0}']), + ('\u{13b9}', ['\u{ab89}', '\u{0}', '\u{0}']), ('\u{13ba}', ['\u{ab8a}', '\u{0}', '\u{0}']), + ('\u{13bb}', ['\u{ab8b}', '\u{0}', '\u{0}']), ('\u{13bc}', ['\u{ab8c}', '\u{0}', '\u{0}']), + ('\u{13bd}', ['\u{ab8d}', '\u{0}', '\u{0}']), ('\u{13be}', ['\u{ab8e}', '\u{0}', '\u{0}']), + ('\u{13bf}', ['\u{ab8f}', '\u{0}', '\u{0}']), ('\u{13c0}', ['\u{ab90}', '\u{0}', '\u{0}']), + ('\u{13c1}', ['\u{ab91}', '\u{0}', '\u{0}']), ('\u{13c2}', ['\u{ab92}', '\u{0}', '\u{0}']), + ('\u{13c3}', ['\u{ab93}', '\u{0}', '\u{0}']), ('\u{13c4}', ['\u{ab94}', '\u{0}', '\u{0}']), + ('\u{13c5}', ['\u{ab95}', '\u{0}', '\u{0}']), ('\u{13c6}', ['\u{ab96}', '\u{0}', '\u{0}']), + ('\u{13c7}', ['\u{ab97}', '\u{0}', '\u{0}']), ('\u{13c8}', ['\u{ab98}', '\u{0}', '\u{0}']), + ('\u{13c9}', ['\u{ab99}', '\u{0}', '\u{0}']), ('\u{13ca}', ['\u{ab9a}', '\u{0}', '\u{0}']), + ('\u{13cb}', ['\u{ab9b}', '\u{0}', '\u{0}']), ('\u{13cc}', ['\u{ab9c}', '\u{0}', '\u{0}']), + ('\u{13cd}', ['\u{ab9d}', '\u{0}', '\u{0}']), ('\u{13ce}', ['\u{ab9e}', '\u{0}', '\u{0}']), + ('\u{13cf}', ['\u{ab9f}', '\u{0}', '\u{0}']), ('\u{13d0}', ['\u{aba0}', '\u{0}', '\u{0}']), + ('\u{13d1}', ['\u{aba1}', '\u{0}', '\u{0}']), ('\u{13d2}', ['\u{aba2}', '\u{0}', '\u{0}']), + ('\u{13d3}', ['\u{aba3}', '\u{0}', '\u{0}']), ('\u{13d4}', ['\u{aba4}', '\u{0}', '\u{0}']), + ('\u{13d5}', ['\u{aba5}', '\u{0}', '\u{0}']), ('\u{13d6}', ['\u{aba6}', '\u{0}', '\u{0}']), + ('\u{13d7}', ['\u{aba7}', '\u{0}', '\u{0}']), ('\u{13d8}', ['\u{aba8}', '\u{0}', '\u{0}']), + ('\u{13d9}', ['\u{aba9}', '\u{0}', '\u{0}']), ('\u{13da}', ['\u{abaa}', '\u{0}', '\u{0}']), + ('\u{13db}', ['\u{abab}', '\u{0}', '\u{0}']), ('\u{13dc}', ['\u{abac}', '\u{0}', '\u{0}']), + ('\u{13dd}', ['\u{abad}', '\u{0}', '\u{0}']), ('\u{13de}', ['\u{abae}', '\u{0}', '\u{0}']), + ('\u{13df}', ['\u{abaf}', '\u{0}', '\u{0}']), ('\u{13e0}', ['\u{abb0}', '\u{0}', '\u{0}']), + ('\u{13e1}', ['\u{abb1}', '\u{0}', '\u{0}']), ('\u{13e2}', ['\u{abb2}', '\u{0}', '\u{0}']), + ('\u{13e3}', ['\u{abb3}', '\u{0}', '\u{0}']), ('\u{13e4}', ['\u{abb4}', '\u{0}', '\u{0}']), + ('\u{13e5}', ['\u{abb5}', '\u{0}', '\u{0}']), ('\u{13e6}', ['\u{abb6}', '\u{0}', '\u{0}']), + ('\u{13e7}', ['\u{abb7}', '\u{0}', '\u{0}']), ('\u{13e8}', ['\u{abb8}', '\u{0}', '\u{0}']), + ('\u{13e9}', ['\u{abb9}', '\u{0}', '\u{0}']), ('\u{13ea}', ['\u{abba}', '\u{0}', '\u{0}']), + ('\u{13eb}', ['\u{abbb}', '\u{0}', '\u{0}']), ('\u{13ec}', ['\u{abbc}', '\u{0}', '\u{0}']), + ('\u{13ed}', ['\u{abbd}', '\u{0}', '\u{0}']), ('\u{13ee}', ['\u{abbe}', '\u{0}', '\u{0}']), + ('\u{13ef}', ['\u{abbf}', '\u{0}', '\u{0}']), ('\u{13f0}', ['\u{13f8}', '\u{0}', '\u{0}']), + ('\u{13f1}', ['\u{13f9}', '\u{0}', '\u{0}']), ('\u{13f2}', ['\u{13fa}', '\u{0}', '\u{0}']), + ('\u{13f3}', ['\u{13fb}', '\u{0}', '\u{0}']), ('\u{13f4}', ['\u{13fc}', '\u{0}', '\u{0}']), + ('\u{13f5}', ['\u{13fd}', '\u{0}', '\u{0}']), ('\u{1c89}', ['\u{1c8a}', '\u{0}', '\u{0}']), + ('\u{1c90}', ['\u{10d0}', '\u{0}', '\u{0}']), ('\u{1c91}', ['\u{10d1}', '\u{0}', '\u{0}']), + ('\u{1c92}', ['\u{10d2}', '\u{0}', '\u{0}']), ('\u{1c93}', ['\u{10d3}', '\u{0}', '\u{0}']), + ('\u{1c94}', ['\u{10d4}', '\u{0}', '\u{0}']), ('\u{1c95}', ['\u{10d5}', '\u{0}', '\u{0}']), + ('\u{1c96}', ['\u{10d6}', '\u{0}', '\u{0}']), ('\u{1c97}', ['\u{10d7}', '\u{0}', '\u{0}']), + ('\u{1c98}', ['\u{10d8}', '\u{0}', '\u{0}']), ('\u{1c99}', ['\u{10d9}', '\u{0}', '\u{0}']), + ('\u{1c9a}', ['\u{10da}', '\u{0}', '\u{0}']), ('\u{1c9b}', ['\u{10db}', '\u{0}', '\u{0}']), + ('\u{1c9c}', ['\u{10dc}', '\u{0}', '\u{0}']), ('\u{1c9d}', ['\u{10dd}', '\u{0}', '\u{0}']), + ('\u{1c9e}', ['\u{10de}', '\u{0}', '\u{0}']), ('\u{1c9f}', ['\u{10df}', '\u{0}', '\u{0}']), + ('\u{1ca0}', ['\u{10e0}', '\u{0}', '\u{0}']), ('\u{1ca1}', ['\u{10e1}', '\u{0}', '\u{0}']), + ('\u{1ca2}', ['\u{10e2}', '\u{0}', '\u{0}']), ('\u{1ca3}', ['\u{10e3}', '\u{0}', '\u{0}']), + ('\u{1ca4}', ['\u{10e4}', '\u{0}', '\u{0}']), ('\u{1ca5}', ['\u{10e5}', '\u{0}', '\u{0}']), + ('\u{1ca6}', ['\u{10e6}', '\u{0}', '\u{0}']), ('\u{1ca7}', ['\u{10e7}', '\u{0}', '\u{0}']), + ('\u{1ca8}', ['\u{10e8}', '\u{0}', '\u{0}']), ('\u{1ca9}', ['\u{10e9}', '\u{0}', '\u{0}']), + ('\u{1caa}', ['\u{10ea}', '\u{0}', '\u{0}']), ('\u{1cab}', ['\u{10eb}', '\u{0}', '\u{0}']), + ('\u{1cac}', ['\u{10ec}', '\u{0}', '\u{0}']), ('\u{1cad}', ['\u{10ed}', '\u{0}', '\u{0}']), + ('\u{1cae}', ['\u{10ee}', '\u{0}', '\u{0}']), ('\u{1caf}', ['\u{10ef}', '\u{0}', '\u{0}']), + ('\u{1cb0}', ['\u{10f0}', '\u{0}', '\u{0}']), ('\u{1cb1}', ['\u{10f1}', '\u{0}', '\u{0}']), + ('\u{1cb2}', ['\u{10f2}', '\u{0}', '\u{0}']), ('\u{1cb3}', ['\u{10f3}', '\u{0}', '\u{0}']), + ('\u{1cb4}', ['\u{10f4}', '\u{0}', '\u{0}']), ('\u{1cb5}', ['\u{10f5}', '\u{0}', '\u{0}']), + ('\u{1cb6}', ['\u{10f6}', '\u{0}', '\u{0}']), ('\u{1cb7}', ['\u{10f7}', '\u{0}', '\u{0}']), + ('\u{1cb8}', ['\u{10f8}', '\u{0}', '\u{0}']), ('\u{1cb9}', ['\u{10f9}', '\u{0}', '\u{0}']), + ('\u{1cba}', ['\u{10fa}', '\u{0}', '\u{0}']), ('\u{1cbd}', ['\u{10fd}', '\u{0}', '\u{0}']), + ('\u{1cbe}', ['\u{10fe}', '\u{0}', '\u{0}']), ('\u{1cbf}', ['\u{10ff}', '\u{0}', '\u{0}']), + ('\u{1e00}', ['\u{1e01}', '\u{0}', '\u{0}']), ('\u{1e02}', ['\u{1e03}', '\u{0}', '\u{0}']), + ('\u{1e04}', ['\u{1e05}', '\u{0}', '\u{0}']), ('\u{1e06}', ['\u{1e07}', '\u{0}', '\u{0}']), + ('\u{1e08}', ['\u{1e09}', '\u{0}', '\u{0}']), ('\u{1e0a}', ['\u{1e0b}', '\u{0}', '\u{0}']), + ('\u{1e0c}', ['\u{1e0d}', '\u{0}', '\u{0}']), ('\u{1e0e}', ['\u{1e0f}', '\u{0}', '\u{0}']), + ('\u{1e10}', ['\u{1e11}', '\u{0}', '\u{0}']), ('\u{1e12}', ['\u{1e13}', '\u{0}', '\u{0}']), + ('\u{1e14}', ['\u{1e15}', '\u{0}', '\u{0}']), ('\u{1e16}', ['\u{1e17}', '\u{0}', '\u{0}']), + ('\u{1e18}', ['\u{1e19}', '\u{0}', '\u{0}']), ('\u{1e1a}', ['\u{1e1b}', '\u{0}', '\u{0}']), + ('\u{1e1c}', ['\u{1e1d}', '\u{0}', '\u{0}']), ('\u{1e1e}', ['\u{1e1f}', '\u{0}', '\u{0}']), + ('\u{1e20}', ['\u{1e21}', '\u{0}', '\u{0}']), ('\u{1e22}', ['\u{1e23}', '\u{0}', '\u{0}']), + ('\u{1e24}', ['\u{1e25}', '\u{0}', '\u{0}']), ('\u{1e26}', ['\u{1e27}', '\u{0}', '\u{0}']), + ('\u{1e28}', ['\u{1e29}', '\u{0}', '\u{0}']), ('\u{1e2a}', ['\u{1e2b}', '\u{0}', '\u{0}']), + ('\u{1e2c}', ['\u{1e2d}', '\u{0}', '\u{0}']), ('\u{1e2e}', ['\u{1e2f}', '\u{0}', '\u{0}']), + ('\u{1e30}', ['\u{1e31}', '\u{0}', '\u{0}']), ('\u{1e32}', ['\u{1e33}', '\u{0}', '\u{0}']), + ('\u{1e34}', ['\u{1e35}', '\u{0}', '\u{0}']), ('\u{1e36}', ['\u{1e37}', '\u{0}', '\u{0}']), + ('\u{1e38}', ['\u{1e39}', '\u{0}', '\u{0}']), ('\u{1e3a}', ['\u{1e3b}', '\u{0}', '\u{0}']), + ('\u{1e3c}', ['\u{1e3d}', '\u{0}', '\u{0}']), ('\u{1e3e}', ['\u{1e3f}', '\u{0}', '\u{0}']), + ('\u{1e40}', ['\u{1e41}', '\u{0}', '\u{0}']), ('\u{1e42}', ['\u{1e43}', '\u{0}', '\u{0}']), + ('\u{1e44}', ['\u{1e45}', '\u{0}', '\u{0}']), ('\u{1e46}', ['\u{1e47}', '\u{0}', '\u{0}']), + ('\u{1e48}', ['\u{1e49}', '\u{0}', '\u{0}']), ('\u{1e4a}', ['\u{1e4b}', '\u{0}', '\u{0}']), + ('\u{1e4c}', ['\u{1e4d}', '\u{0}', '\u{0}']), ('\u{1e4e}', ['\u{1e4f}', '\u{0}', '\u{0}']), + ('\u{1e50}', ['\u{1e51}', '\u{0}', '\u{0}']), ('\u{1e52}', ['\u{1e53}', '\u{0}', '\u{0}']), + ('\u{1e54}', ['\u{1e55}', '\u{0}', '\u{0}']), ('\u{1e56}', ['\u{1e57}', '\u{0}', '\u{0}']), + ('\u{1e58}', ['\u{1e59}', '\u{0}', '\u{0}']), ('\u{1e5a}', ['\u{1e5b}', '\u{0}', '\u{0}']), + ('\u{1e5c}', ['\u{1e5d}', '\u{0}', '\u{0}']), ('\u{1e5e}', ['\u{1e5f}', '\u{0}', '\u{0}']), + ('\u{1e60}', ['\u{1e61}', '\u{0}', '\u{0}']), ('\u{1e62}', ['\u{1e63}', '\u{0}', '\u{0}']), + ('\u{1e64}', ['\u{1e65}', '\u{0}', '\u{0}']), ('\u{1e66}', ['\u{1e67}', '\u{0}', '\u{0}']), + ('\u{1e68}', ['\u{1e69}', '\u{0}', '\u{0}']), ('\u{1e6a}', ['\u{1e6b}', '\u{0}', '\u{0}']), + ('\u{1e6c}', ['\u{1e6d}', '\u{0}', '\u{0}']), ('\u{1e6e}', ['\u{1e6f}', '\u{0}', '\u{0}']), + ('\u{1e70}', ['\u{1e71}', '\u{0}', '\u{0}']), ('\u{1e72}', ['\u{1e73}', '\u{0}', '\u{0}']), + ('\u{1e74}', ['\u{1e75}', '\u{0}', '\u{0}']), ('\u{1e76}', ['\u{1e77}', '\u{0}', '\u{0}']), + ('\u{1e78}', ['\u{1e79}', '\u{0}', '\u{0}']), ('\u{1e7a}', ['\u{1e7b}', '\u{0}', '\u{0}']), + ('\u{1e7c}', ['\u{1e7d}', '\u{0}', '\u{0}']), ('\u{1e7e}', ['\u{1e7f}', '\u{0}', '\u{0}']), + ('\u{1e80}', ['\u{1e81}', '\u{0}', '\u{0}']), ('\u{1e82}', ['\u{1e83}', '\u{0}', '\u{0}']), + ('\u{1e84}', ['\u{1e85}', '\u{0}', '\u{0}']), ('\u{1e86}', ['\u{1e87}', '\u{0}', '\u{0}']), + ('\u{1e88}', ['\u{1e89}', '\u{0}', '\u{0}']), ('\u{1e8a}', ['\u{1e8b}', '\u{0}', '\u{0}']), + ('\u{1e8c}', ['\u{1e8d}', '\u{0}', '\u{0}']), ('\u{1e8e}', ['\u{1e8f}', '\u{0}', '\u{0}']), + ('\u{1e90}', ['\u{1e91}', '\u{0}', '\u{0}']), ('\u{1e92}', ['\u{1e93}', '\u{0}', '\u{0}']), + ('\u{1e94}', ['\u{1e95}', '\u{0}', '\u{0}']), ('\u{1e9e}', ['\u{df}', '\u{0}', '\u{0}']), + ('\u{1ea0}', ['\u{1ea1}', '\u{0}', '\u{0}']), ('\u{1ea2}', ['\u{1ea3}', '\u{0}', '\u{0}']), + ('\u{1ea4}', ['\u{1ea5}', '\u{0}', '\u{0}']), ('\u{1ea6}', ['\u{1ea7}', '\u{0}', '\u{0}']), + ('\u{1ea8}', ['\u{1ea9}', '\u{0}', '\u{0}']), ('\u{1eaa}', ['\u{1eab}', '\u{0}', '\u{0}']), + ('\u{1eac}', ['\u{1ead}', '\u{0}', '\u{0}']), ('\u{1eae}', ['\u{1eaf}', '\u{0}', '\u{0}']), + ('\u{1eb0}', ['\u{1eb1}', '\u{0}', '\u{0}']), ('\u{1eb2}', ['\u{1eb3}', '\u{0}', '\u{0}']), + ('\u{1eb4}', ['\u{1eb5}', '\u{0}', '\u{0}']), ('\u{1eb6}', ['\u{1eb7}', '\u{0}', '\u{0}']), + ('\u{1eb8}', ['\u{1eb9}', '\u{0}', '\u{0}']), ('\u{1eba}', ['\u{1ebb}', '\u{0}', '\u{0}']), + ('\u{1ebc}', ['\u{1ebd}', '\u{0}', '\u{0}']), ('\u{1ebe}', ['\u{1ebf}', '\u{0}', '\u{0}']), + ('\u{1ec0}', ['\u{1ec1}', '\u{0}', '\u{0}']), ('\u{1ec2}', ['\u{1ec3}', '\u{0}', '\u{0}']), + ('\u{1ec4}', ['\u{1ec5}', '\u{0}', '\u{0}']), ('\u{1ec6}', ['\u{1ec7}', '\u{0}', '\u{0}']), + ('\u{1ec8}', ['\u{1ec9}', '\u{0}', '\u{0}']), ('\u{1eca}', ['\u{1ecb}', '\u{0}', '\u{0}']), + ('\u{1ecc}', ['\u{1ecd}', '\u{0}', '\u{0}']), ('\u{1ece}', ['\u{1ecf}', '\u{0}', '\u{0}']), + ('\u{1ed0}', ['\u{1ed1}', '\u{0}', '\u{0}']), ('\u{1ed2}', ['\u{1ed3}', '\u{0}', '\u{0}']), + ('\u{1ed4}', ['\u{1ed5}', '\u{0}', '\u{0}']), ('\u{1ed6}', ['\u{1ed7}', '\u{0}', '\u{0}']), + ('\u{1ed8}', ['\u{1ed9}', '\u{0}', '\u{0}']), ('\u{1eda}', ['\u{1edb}', '\u{0}', '\u{0}']), + ('\u{1edc}', ['\u{1edd}', '\u{0}', '\u{0}']), ('\u{1ede}', ['\u{1edf}', '\u{0}', '\u{0}']), + ('\u{1ee0}', ['\u{1ee1}', '\u{0}', '\u{0}']), ('\u{1ee2}', ['\u{1ee3}', '\u{0}', '\u{0}']), + ('\u{1ee4}', ['\u{1ee5}', '\u{0}', '\u{0}']), ('\u{1ee6}', ['\u{1ee7}', '\u{0}', '\u{0}']), + ('\u{1ee8}', ['\u{1ee9}', '\u{0}', '\u{0}']), ('\u{1eea}', ['\u{1eeb}', '\u{0}', '\u{0}']), + ('\u{1eec}', ['\u{1eed}', '\u{0}', '\u{0}']), ('\u{1eee}', ['\u{1eef}', '\u{0}', '\u{0}']), + ('\u{1ef0}', ['\u{1ef1}', '\u{0}', '\u{0}']), ('\u{1ef2}', ['\u{1ef3}', '\u{0}', '\u{0}']), + ('\u{1ef4}', ['\u{1ef5}', '\u{0}', '\u{0}']), ('\u{1ef6}', ['\u{1ef7}', '\u{0}', '\u{0}']), + ('\u{1ef8}', ['\u{1ef9}', '\u{0}', '\u{0}']), ('\u{1efa}', ['\u{1efb}', '\u{0}', '\u{0}']), + ('\u{1efc}', ['\u{1efd}', '\u{0}', '\u{0}']), ('\u{1efe}', ['\u{1eff}', '\u{0}', '\u{0}']), + ('\u{1f08}', ['\u{1f00}', '\u{0}', '\u{0}']), ('\u{1f09}', ['\u{1f01}', '\u{0}', '\u{0}']), + ('\u{1f0a}', ['\u{1f02}', '\u{0}', '\u{0}']), ('\u{1f0b}', ['\u{1f03}', '\u{0}', '\u{0}']), + ('\u{1f0c}', ['\u{1f04}', '\u{0}', '\u{0}']), ('\u{1f0d}', ['\u{1f05}', '\u{0}', '\u{0}']), + ('\u{1f0e}', ['\u{1f06}', '\u{0}', '\u{0}']), ('\u{1f0f}', ['\u{1f07}', '\u{0}', '\u{0}']), + ('\u{1f18}', ['\u{1f10}', '\u{0}', '\u{0}']), ('\u{1f19}', ['\u{1f11}', '\u{0}', '\u{0}']), + ('\u{1f1a}', ['\u{1f12}', '\u{0}', '\u{0}']), ('\u{1f1b}', ['\u{1f13}', '\u{0}', '\u{0}']), + ('\u{1f1c}', ['\u{1f14}', '\u{0}', '\u{0}']), ('\u{1f1d}', ['\u{1f15}', '\u{0}', '\u{0}']), + ('\u{1f28}', ['\u{1f20}', '\u{0}', '\u{0}']), ('\u{1f29}', ['\u{1f21}', '\u{0}', '\u{0}']), + ('\u{1f2a}', ['\u{1f22}', '\u{0}', '\u{0}']), ('\u{1f2b}', ['\u{1f23}', '\u{0}', '\u{0}']), + ('\u{1f2c}', ['\u{1f24}', '\u{0}', '\u{0}']), ('\u{1f2d}', ['\u{1f25}', '\u{0}', '\u{0}']), + ('\u{1f2e}', ['\u{1f26}', '\u{0}', '\u{0}']), ('\u{1f2f}', ['\u{1f27}', '\u{0}', '\u{0}']), + ('\u{1f38}', ['\u{1f30}', '\u{0}', '\u{0}']), ('\u{1f39}', ['\u{1f31}', '\u{0}', '\u{0}']), + ('\u{1f3a}', ['\u{1f32}', '\u{0}', '\u{0}']), ('\u{1f3b}', ['\u{1f33}', '\u{0}', '\u{0}']), + ('\u{1f3c}', ['\u{1f34}', '\u{0}', '\u{0}']), ('\u{1f3d}', ['\u{1f35}', '\u{0}', '\u{0}']), + ('\u{1f3e}', ['\u{1f36}', '\u{0}', '\u{0}']), ('\u{1f3f}', ['\u{1f37}', '\u{0}', '\u{0}']), + ('\u{1f48}', ['\u{1f40}', '\u{0}', '\u{0}']), ('\u{1f49}', ['\u{1f41}', '\u{0}', '\u{0}']), + ('\u{1f4a}', ['\u{1f42}', '\u{0}', '\u{0}']), ('\u{1f4b}', ['\u{1f43}', '\u{0}', '\u{0}']), + ('\u{1f4c}', ['\u{1f44}', '\u{0}', '\u{0}']), ('\u{1f4d}', ['\u{1f45}', '\u{0}', '\u{0}']), + ('\u{1f59}', ['\u{1f51}', '\u{0}', '\u{0}']), ('\u{1f5b}', ['\u{1f53}', '\u{0}', '\u{0}']), + ('\u{1f5d}', ['\u{1f55}', '\u{0}', '\u{0}']), ('\u{1f5f}', ['\u{1f57}', '\u{0}', '\u{0}']), + ('\u{1f68}', ['\u{1f60}', '\u{0}', '\u{0}']), ('\u{1f69}', ['\u{1f61}', '\u{0}', '\u{0}']), + ('\u{1f6a}', ['\u{1f62}', '\u{0}', '\u{0}']), ('\u{1f6b}', ['\u{1f63}', '\u{0}', '\u{0}']), + ('\u{1f6c}', ['\u{1f64}', '\u{0}', '\u{0}']), ('\u{1f6d}', ['\u{1f65}', '\u{0}', '\u{0}']), + ('\u{1f6e}', ['\u{1f66}', '\u{0}', '\u{0}']), ('\u{1f6f}', ['\u{1f67}', '\u{0}', '\u{0}']), + ('\u{1f88}', ['\u{1f80}', '\u{0}', '\u{0}']), ('\u{1f89}', ['\u{1f81}', '\u{0}', '\u{0}']), + ('\u{1f8a}', ['\u{1f82}', '\u{0}', '\u{0}']), ('\u{1f8b}', ['\u{1f83}', '\u{0}', '\u{0}']), + ('\u{1f8c}', ['\u{1f84}', '\u{0}', '\u{0}']), ('\u{1f8d}', ['\u{1f85}', '\u{0}', '\u{0}']), + ('\u{1f8e}', ['\u{1f86}', '\u{0}', '\u{0}']), ('\u{1f8f}', ['\u{1f87}', '\u{0}', '\u{0}']), + ('\u{1f98}', ['\u{1f90}', '\u{0}', '\u{0}']), ('\u{1f99}', ['\u{1f91}', '\u{0}', '\u{0}']), + ('\u{1f9a}', ['\u{1f92}', '\u{0}', '\u{0}']), ('\u{1f9b}', ['\u{1f93}', '\u{0}', '\u{0}']), + ('\u{1f9c}', ['\u{1f94}', '\u{0}', '\u{0}']), ('\u{1f9d}', ['\u{1f95}', '\u{0}', '\u{0}']), + ('\u{1f9e}', ['\u{1f96}', '\u{0}', '\u{0}']), ('\u{1f9f}', ['\u{1f97}', '\u{0}', '\u{0}']), + ('\u{1fa8}', ['\u{1fa0}', '\u{0}', '\u{0}']), ('\u{1fa9}', ['\u{1fa1}', '\u{0}', '\u{0}']), + ('\u{1faa}', ['\u{1fa2}', '\u{0}', '\u{0}']), ('\u{1fab}', ['\u{1fa3}', '\u{0}', '\u{0}']), + ('\u{1fac}', ['\u{1fa4}', '\u{0}', '\u{0}']), ('\u{1fad}', ['\u{1fa5}', '\u{0}', '\u{0}']), + ('\u{1fae}', ['\u{1fa6}', '\u{0}', '\u{0}']), ('\u{1faf}', ['\u{1fa7}', '\u{0}', '\u{0}']), + ('\u{1fb8}', ['\u{1fb0}', '\u{0}', '\u{0}']), ('\u{1fb9}', ['\u{1fb1}', '\u{0}', '\u{0}']), + ('\u{1fba}', ['\u{1f70}', '\u{0}', '\u{0}']), ('\u{1fbb}', ['\u{1f71}', '\u{0}', '\u{0}']), + ('\u{1fbc}', ['\u{1fb3}', '\u{0}', '\u{0}']), ('\u{1fc8}', ['\u{1f72}', '\u{0}', '\u{0}']), + ('\u{1fc9}', ['\u{1f73}', '\u{0}', '\u{0}']), ('\u{1fca}', ['\u{1f74}', '\u{0}', '\u{0}']), + ('\u{1fcb}', ['\u{1f75}', '\u{0}', '\u{0}']), ('\u{1fcc}', ['\u{1fc3}', '\u{0}', '\u{0}']), + ('\u{1fd8}', ['\u{1fd0}', '\u{0}', '\u{0}']), ('\u{1fd9}', ['\u{1fd1}', '\u{0}', '\u{0}']), + ('\u{1fda}', ['\u{1f76}', '\u{0}', '\u{0}']), ('\u{1fdb}', ['\u{1f77}', '\u{0}', '\u{0}']), + ('\u{1fe8}', ['\u{1fe0}', '\u{0}', '\u{0}']), ('\u{1fe9}', ['\u{1fe1}', '\u{0}', '\u{0}']), + ('\u{1fea}', ['\u{1f7a}', '\u{0}', '\u{0}']), ('\u{1feb}', ['\u{1f7b}', '\u{0}', '\u{0}']), + ('\u{1fec}', ['\u{1fe5}', '\u{0}', '\u{0}']), ('\u{1ff8}', ['\u{1f78}', '\u{0}', '\u{0}']), + ('\u{1ff9}', ['\u{1f79}', '\u{0}', '\u{0}']), ('\u{1ffa}', ['\u{1f7c}', '\u{0}', '\u{0}']), + ('\u{1ffb}', ['\u{1f7d}', '\u{0}', '\u{0}']), ('\u{1ffc}', ['\u{1ff3}', '\u{0}', '\u{0}']), + ('\u{2126}', ['\u{3c9}', '\u{0}', '\u{0}']), ('\u{212a}', ['k', '\u{0}', '\u{0}']), + ('\u{212b}', ['\u{e5}', '\u{0}', '\u{0}']), ('\u{2132}', ['\u{214e}', '\u{0}', '\u{0}']), + ('\u{2160}', ['\u{2170}', '\u{0}', '\u{0}']), ('\u{2161}', ['\u{2171}', '\u{0}', '\u{0}']), + ('\u{2162}', ['\u{2172}', '\u{0}', '\u{0}']), ('\u{2163}', ['\u{2173}', '\u{0}', '\u{0}']), + ('\u{2164}', ['\u{2174}', '\u{0}', '\u{0}']), ('\u{2165}', ['\u{2175}', '\u{0}', '\u{0}']), + ('\u{2166}', ['\u{2176}', '\u{0}', '\u{0}']), ('\u{2167}', ['\u{2177}', '\u{0}', '\u{0}']), + ('\u{2168}', ['\u{2178}', '\u{0}', '\u{0}']), ('\u{2169}', ['\u{2179}', '\u{0}', '\u{0}']), + ('\u{216a}', ['\u{217a}', '\u{0}', '\u{0}']), ('\u{216b}', ['\u{217b}', '\u{0}', '\u{0}']), + ('\u{216c}', ['\u{217c}', '\u{0}', '\u{0}']), ('\u{216d}', ['\u{217d}', '\u{0}', '\u{0}']), + ('\u{216e}', ['\u{217e}', '\u{0}', '\u{0}']), ('\u{216f}', ['\u{217f}', '\u{0}', '\u{0}']), + ('\u{2183}', ['\u{2184}', '\u{0}', '\u{0}']), ('\u{24b6}', ['\u{24d0}', '\u{0}', '\u{0}']), + ('\u{24b7}', ['\u{24d1}', '\u{0}', '\u{0}']), ('\u{24b8}', ['\u{24d2}', '\u{0}', '\u{0}']), + ('\u{24b9}', ['\u{24d3}', '\u{0}', '\u{0}']), ('\u{24ba}', ['\u{24d4}', '\u{0}', '\u{0}']), + ('\u{24bb}', ['\u{24d5}', '\u{0}', '\u{0}']), ('\u{24bc}', ['\u{24d6}', '\u{0}', '\u{0}']), + ('\u{24bd}', ['\u{24d7}', '\u{0}', '\u{0}']), ('\u{24be}', ['\u{24d8}', '\u{0}', '\u{0}']), + ('\u{24bf}', ['\u{24d9}', '\u{0}', '\u{0}']), ('\u{24c0}', ['\u{24da}', '\u{0}', '\u{0}']), + ('\u{24c1}', ['\u{24db}', '\u{0}', '\u{0}']), ('\u{24c2}', ['\u{24dc}', '\u{0}', '\u{0}']), + ('\u{24c3}', ['\u{24dd}', '\u{0}', '\u{0}']), ('\u{24c4}', ['\u{24de}', '\u{0}', '\u{0}']), + ('\u{24c5}', ['\u{24df}', '\u{0}', '\u{0}']), ('\u{24c6}', ['\u{24e0}', '\u{0}', '\u{0}']), + ('\u{24c7}', ['\u{24e1}', '\u{0}', '\u{0}']), ('\u{24c8}', ['\u{24e2}', '\u{0}', '\u{0}']), + ('\u{24c9}', ['\u{24e3}', '\u{0}', '\u{0}']), ('\u{24ca}', ['\u{24e4}', '\u{0}', '\u{0}']), + ('\u{24cb}', ['\u{24e5}', '\u{0}', '\u{0}']), ('\u{24cc}', ['\u{24e6}', '\u{0}', '\u{0}']), + ('\u{24cd}', ['\u{24e7}', '\u{0}', '\u{0}']), ('\u{24ce}', ['\u{24e8}', '\u{0}', '\u{0}']), + ('\u{24cf}', ['\u{24e9}', '\u{0}', '\u{0}']), ('\u{2c00}', ['\u{2c30}', '\u{0}', '\u{0}']), + ('\u{2c01}', ['\u{2c31}', '\u{0}', '\u{0}']), ('\u{2c02}', ['\u{2c32}', '\u{0}', '\u{0}']), + ('\u{2c03}', ['\u{2c33}', '\u{0}', '\u{0}']), ('\u{2c04}', ['\u{2c34}', '\u{0}', '\u{0}']), + ('\u{2c05}', ['\u{2c35}', '\u{0}', '\u{0}']), ('\u{2c06}', ['\u{2c36}', '\u{0}', '\u{0}']), + ('\u{2c07}', ['\u{2c37}', '\u{0}', '\u{0}']), ('\u{2c08}', ['\u{2c38}', '\u{0}', '\u{0}']), + ('\u{2c09}', ['\u{2c39}', '\u{0}', '\u{0}']), ('\u{2c0a}', ['\u{2c3a}', '\u{0}', '\u{0}']), + ('\u{2c0b}', ['\u{2c3b}', '\u{0}', '\u{0}']), ('\u{2c0c}', ['\u{2c3c}', '\u{0}', '\u{0}']), + ('\u{2c0d}', ['\u{2c3d}', '\u{0}', '\u{0}']), ('\u{2c0e}', ['\u{2c3e}', '\u{0}', '\u{0}']), + ('\u{2c0f}', ['\u{2c3f}', '\u{0}', '\u{0}']), ('\u{2c10}', ['\u{2c40}', '\u{0}', '\u{0}']), + ('\u{2c11}', ['\u{2c41}', '\u{0}', '\u{0}']), ('\u{2c12}', ['\u{2c42}', '\u{0}', '\u{0}']), + ('\u{2c13}', ['\u{2c43}', '\u{0}', '\u{0}']), ('\u{2c14}', ['\u{2c44}', '\u{0}', '\u{0}']), + ('\u{2c15}', ['\u{2c45}', '\u{0}', '\u{0}']), ('\u{2c16}', ['\u{2c46}', '\u{0}', '\u{0}']), + ('\u{2c17}', ['\u{2c47}', '\u{0}', '\u{0}']), ('\u{2c18}', ['\u{2c48}', '\u{0}', '\u{0}']), + ('\u{2c19}', ['\u{2c49}', '\u{0}', '\u{0}']), ('\u{2c1a}', ['\u{2c4a}', '\u{0}', '\u{0}']), + ('\u{2c1b}', ['\u{2c4b}', '\u{0}', '\u{0}']), ('\u{2c1c}', ['\u{2c4c}', '\u{0}', '\u{0}']), + ('\u{2c1d}', ['\u{2c4d}', '\u{0}', '\u{0}']), ('\u{2c1e}', ['\u{2c4e}', '\u{0}', '\u{0}']), + ('\u{2c1f}', ['\u{2c4f}', '\u{0}', '\u{0}']), ('\u{2c20}', ['\u{2c50}', '\u{0}', '\u{0}']), + ('\u{2c21}', ['\u{2c51}', '\u{0}', '\u{0}']), ('\u{2c22}', ['\u{2c52}', '\u{0}', '\u{0}']), + ('\u{2c23}', ['\u{2c53}', '\u{0}', '\u{0}']), ('\u{2c24}', ['\u{2c54}', '\u{0}', '\u{0}']), + ('\u{2c25}', ['\u{2c55}', '\u{0}', '\u{0}']), ('\u{2c26}', ['\u{2c56}', '\u{0}', '\u{0}']), + ('\u{2c27}', ['\u{2c57}', '\u{0}', '\u{0}']), ('\u{2c28}', ['\u{2c58}', '\u{0}', '\u{0}']), + ('\u{2c29}', ['\u{2c59}', '\u{0}', '\u{0}']), ('\u{2c2a}', ['\u{2c5a}', '\u{0}', '\u{0}']), + ('\u{2c2b}', ['\u{2c5b}', '\u{0}', '\u{0}']), ('\u{2c2c}', ['\u{2c5c}', '\u{0}', '\u{0}']), + ('\u{2c2d}', ['\u{2c5d}', '\u{0}', '\u{0}']), ('\u{2c2e}', ['\u{2c5e}', '\u{0}', '\u{0}']), + ('\u{2c2f}', ['\u{2c5f}', '\u{0}', '\u{0}']), ('\u{2c60}', ['\u{2c61}', '\u{0}', '\u{0}']), + ('\u{2c62}', ['\u{26b}', '\u{0}', '\u{0}']), ('\u{2c63}', ['\u{1d7d}', '\u{0}', '\u{0}']), + ('\u{2c64}', ['\u{27d}', '\u{0}', '\u{0}']), ('\u{2c67}', ['\u{2c68}', '\u{0}', '\u{0}']), + ('\u{2c69}', ['\u{2c6a}', '\u{0}', '\u{0}']), ('\u{2c6b}', ['\u{2c6c}', '\u{0}', '\u{0}']), + ('\u{2c6d}', ['\u{251}', '\u{0}', '\u{0}']), ('\u{2c6e}', ['\u{271}', '\u{0}', '\u{0}']), + ('\u{2c6f}', ['\u{250}', '\u{0}', '\u{0}']), ('\u{2c70}', ['\u{252}', '\u{0}', '\u{0}']), + ('\u{2c72}', ['\u{2c73}', '\u{0}', '\u{0}']), ('\u{2c75}', ['\u{2c76}', '\u{0}', '\u{0}']), + ('\u{2c7e}', ['\u{23f}', '\u{0}', '\u{0}']), ('\u{2c7f}', ['\u{240}', '\u{0}', '\u{0}']), + ('\u{2c80}', ['\u{2c81}', '\u{0}', '\u{0}']), ('\u{2c82}', ['\u{2c83}', '\u{0}', '\u{0}']), + ('\u{2c84}', ['\u{2c85}', '\u{0}', '\u{0}']), ('\u{2c86}', ['\u{2c87}', '\u{0}', '\u{0}']), + ('\u{2c88}', ['\u{2c89}', '\u{0}', '\u{0}']), ('\u{2c8a}', ['\u{2c8b}', '\u{0}', '\u{0}']), + ('\u{2c8c}', ['\u{2c8d}', '\u{0}', '\u{0}']), ('\u{2c8e}', ['\u{2c8f}', '\u{0}', '\u{0}']), + ('\u{2c90}', ['\u{2c91}', '\u{0}', '\u{0}']), ('\u{2c92}', ['\u{2c93}', '\u{0}', '\u{0}']), + ('\u{2c94}', ['\u{2c95}', '\u{0}', '\u{0}']), ('\u{2c96}', ['\u{2c97}', '\u{0}', '\u{0}']), + ('\u{2c98}', ['\u{2c99}', '\u{0}', '\u{0}']), ('\u{2c9a}', ['\u{2c9b}', '\u{0}', '\u{0}']), + ('\u{2c9c}', ['\u{2c9d}', '\u{0}', '\u{0}']), ('\u{2c9e}', ['\u{2c9f}', '\u{0}', '\u{0}']), + ('\u{2ca0}', ['\u{2ca1}', '\u{0}', '\u{0}']), ('\u{2ca2}', ['\u{2ca3}', '\u{0}', '\u{0}']), + ('\u{2ca4}', ['\u{2ca5}', '\u{0}', '\u{0}']), ('\u{2ca6}', ['\u{2ca7}', '\u{0}', '\u{0}']), + ('\u{2ca8}', ['\u{2ca9}', '\u{0}', '\u{0}']), ('\u{2caa}', ['\u{2cab}', '\u{0}', '\u{0}']), + ('\u{2cac}', ['\u{2cad}', '\u{0}', '\u{0}']), ('\u{2cae}', ['\u{2caf}', '\u{0}', '\u{0}']), + ('\u{2cb0}', ['\u{2cb1}', '\u{0}', '\u{0}']), ('\u{2cb2}', ['\u{2cb3}', '\u{0}', '\u{0}']), + ('\u{2cb4}', ['\u{2cb5}', '\u{0}', '\u{0}']), ('\u{2cb6}', ['\u{2cb7}', '\u{0}', '\u{0}']), + ('\u{2cb8}', ['\u{2cb9}', '\u{0}', '\u{0}']), ('\u{2cba}', ['\u{2cbb}', '\u{0}', '\u{0}']), + ('\u{2cbc}', ['\u{2cbd}', '\u{0}', '\u{0}']), ('\u{2cbe}', ['\u{2cbf}', '\u{0}', '\u{0}']), + ('\u{2cc0}', ['\u{2cc1}', '\u{0}', '\u{0}']), ('\u{2cc2}', ['\u{2cc3}', '\u{0}', '\u{0}']), + ('\u{2cc4}', ['\u{2cc5}', '\u{0}', '\u{0}']), ('\u{2cc6}', ['\u{2cc7}', '\u{0}', '\u{0}']), + ('\u{2cc8}', ['\u{2cc9}', '\u{0}', '\u{0}']), ('\u{2cca}', ['\u{2ccb}', '\u{0}', '\u{0}']), + ('\u{2ccc}', ['\u{2ccd}', '\u{0}', '\u{0}']), ('\u{2cce}', ['\u{2ccf}', '\u{0}', '\u{0}']), + ('\u{2cd0}', ['\u{2cd1}', '\u{0}', '\u{0}']), ('\u{2cd2}', ['\u{2cd3}', '\u{0}', '\u{0}']), + ('\u{2cd4}', ['\u{2cd5}', '\u{0}', '\u{0}']), ('\u{2cd6}', ['\u{2cd7}', '\u{0}', '\u{0}']), + ('\u{2cd8}', ['\u{2cd9}', '\u{0}', '\u{0}']), ('\u{2cda}', ['\u{2cdb}', '\u{0}', '\u{0}']), + ('\u{2cdc}', ['\u{2cdd}', '\u{0}', '\u{0}']), ('\u{2cde}', ['\u{2cdf}', '\u{0}', '\u{0}']), + ('\u{2ce0}', ['\u{2ce1}', '\u{0}', '\u{0}']), ('\u{2ce2}', ['\u{2ce3}', '\u{0}', '\u{0}']), + ('\u{2ceb}', ['\u{2cec}', '\u{0}', '\u{0}']), ('\u{2ced}', ['\u{2cee}', '\u{0}', '\u{0}']), + ('\u{2cf2}', ['\u{2cf3}', '\u{0}', '\u{0}']), ('\u{a640}', ['\u{a641}', '\u{0}', '\u{0}']), + ('\u{a642}', ['\u{a643}', '\u{0}', '\u{0}']), ('\u{a644}', ['\u{a645}', '\u{0}', '\u{0}']), + ('\u{a646}', ['\u{a647}', '\u{0}', '\u{0}']), ('\u{a648}', ['\u{a649}', '\u{0}', '\u{0}']), + ('\u{a64a}', ['\u{a64b}', '\u{0}', '\u{0}']), ('\u{a64c}', ['\u{a64d}', '\u{0}', '\u{0}']), + ('\u{a64e}', ['\u{a64f}', '\u{0}', '\u{0}']), ('\u{a650}', ['\u{a651}', '\u{0}', '\u{0}']), + ('\u{a652}', ['\u{a653}', '\u{0}', '\u{0}']), ('\u{a654}', ['\u{a655}', '\u{0}', '\u{0}']), + ('\u{a656}', ['\u{a657}', '\u{0}', '\u{0}']), ('\u{a658}', ['\u{a659}', '\u{0}', '\u{0}']), + ('\u{a65a}', ['\u{a65b}', '\u{0}', '\u{0}']), ('\u{a65c}', ['\u{a65d}', '\u{0}', '\u{0}']), + ('\u{a65e}', ['\u{a65f}', '\u{0}', '\u{0}']), ('\u{a660}', ['\u{a661}', '\u{0}', '\u{0}']), + ('\u{a662}', ['\u{a663}', '\u{0}', '\u{0}']), ('\u{a664}', ['\u{a665}', '\u{0}', '\u{0}']), + ('\u{a666}', ['\u{a667}', '\u{0}', '\u{0}']), ('\u{a668}', ['\u{a669}', '\u{0}', '\u{0}']), + ('\u{a66a}', ['\u{a66b}', '\u{0}', '\u{0}']), ('\u{a66c}', ['\u{a66d}', '\u{0}', '\u{0}']), + ('\u{a680}', ['\u{a681}', '\u{0}', '\u{0}']), ('\u{a682}', ['\u{a683}', '\u{0}', '\u{0}']), + ('\u{a684}', ['\u{a685}', '\u{0}', '\u{0}']), ('\u{a686}', ['\u{a687}', '\u{0}', '\u{0}']), + ('\u{a688}', ['\u{a689}', '\u{0}', '\u{0}']), ('\u{a68a}', ['\u{a68b}', '\u{0}', '\u{0}']), + ('\u{a68c}', ['\u{a68d}', '\u{0}', '\u{0}']), ('\u{a68e}', ['\u{a68f}', '\u{0}', '\u{0}']), + ('\u{a690}', ['\u{a691}', '\u{0}', '\u{0}']), ('\u{a692}', ['\u{a693}', '\u{0}', '\u{0}']), + ('\u{a694}', ['\u{a695}', '\u{0}', '\u{0}']), ('\u{a696}', ['\u{a697}', '\u{0}', '\u{0}']), + ('\u{a698}', ['\u{a699}', '\u{0}', '\u{0}']), ('\u{a69a}', ['\u{a69b}', '\u{0}', '\u{0}']), + ('\u{a722}', ['\u{a723}', '\u{0}', '\u{0}']), ('\u{a724}', ['\u{a725}', '\u{0}', '\u{0}']), + ('\u{a726}', ['\u{a727}', '\u{0}', '\u{0}']), ('\u{a728}', ['\u{a729}', '\u{0}', '\u{0}']), + ('\u{a72a}', ['\u{a72b}', '\u{0}', '\u{0}']), ('\u{a72c}', ['\u{a72d}', '\u{0}', '\u{0}']), + ('\u{a72e}', ['\u{a72f}', '\u{0}', '\u{0}']), ('\u{a732}', ['\u{a733}', '\u{0}', '\u{0}']), + ('\u{a734}', ['\u{a735}', '\u{0}', '\u{0}']), ('\u{a736}', ['\u{a737}', '\u{0}', '\u{0}']), + ('\u{a738}', ['\u{a739}', '\u{0}', '\u{0}']), ('\u{a73a}', ['\u{a73b}', '\u{0}', '\u{0}']), + ('\u{a73c}', ['\u{a73d}', '\u{0}', '\u{0}']), ('\u{a73e}', ['\u{a73f}', '\u{0}', '\u{0}']), + ('\u{a740}', ['\u{a741}', '\u{0}', '\u{0}']), ('\u{a742}', ['\u{a743}', '\u{0}', '\u{0}']), + ('\u{a744}', ['\u{a745}', '\u{0}', '\u{0}']), ('\u{a746}', ['\u{a747}', '\u{0}', '\u{0}']), + ('\u{a748}', ['\u{a749}', '\u{0}', '\u{0}']), ('\u{a74a}', ['\u{a74b}', '\u{0}', '\u{0}']), + ('\u{a74c}', ['\u{a74d}', '\u{0}', '\u{0}']), ('\u{a74e}', ['\u{a74f}', '\u{0}', '\u{0}']), + ('\u{a750}', ['\u{a751}', '\u{0}', '\u{0}']), ('\u{a752}', ['\u{a753}', '\u{0}', '\u{0}']), + ('\u{a754}', ['\u{a755}', '\u{0}', '\u{0}']), ('\u{a756}', ['\u{a757}', '\u{0}', '\u{0}']), + ('\u{a758}', ['\u{a759}', '\u{0}', '\u{0}']), ('\u{a75a}', ['\u{a75b}', '\u{0}', '\u{0}']), + ('\u{a75c}', ['\u{a75d}', '\u{0}', '\u{0}']), ('\u{a75e}', ['\u{a75f}', '\u{0}', '\u{0}']), + ('\u{a760}', ['\u{a761}', '\u{0}', '\u{0}']), ('\u{a762}', ['\u{a763}', '\u{0}', '\u{0}']), + ('\u{a764}', ['\u{a765}', '\u{0}', '\u{0}']), ('\u{a766}', ['\u{a767}', '\u{0}', '\u{0}']), + ('\u{a768}', ['\u{a769}', '\u{0}', '\u{0}']), ('\u{a76a}', ['\u{a76b}', '\u{0}', '\u{0}']), + ('\u{a76c}', ['\u{a76d}', '\u{0}', '\u{0}']), ('\u{a76e}', ['\u{a76f}', '\u{0}', '\u{0}']), + ('\u{a779}', ['\u{a77a}', '\u{0}', '\u{0}']), ('\u{a77b}', ['\u{a77c}', '\u{0}', '\u{0}']), + ('\u{a77d}', ['\u{1d79}', '\u{0}', '\u{0}']), ('\u{a77e}', ['\u{a77f}', '\u{0}', '\u{0}']), + ('\u{a780}', ['\u{a781}', '\u{0}', '\u{0}']), ('\u{a782}', ['\u{a783}', '\u{0}', '\u{0}']), + ('\u{a784}', ['\u{a785}', '\u{0}', '\u{0}']), ('\u{a786}', ['\u{a787}', '\u{0}', '\u{0}']), + ('\u{a78b}', ['\u{a78c}', '\u{0}', '\u{0}']), ('\u{a78d}', ['\u{265}', '\u{0}', '\u{0}']), + ('\u{a790}', ['\u{a791}', '\u{0}', '\u{0}']), ('\u{a792}', ['\u{a793}', '\u{0}', '\u{0}']), + ('\u{a796}', ['\u{a797}', '\u{0}', '\u{0}']), ('\u{a798}', ['\u{a799}', '\u{0}', '\u{0}']), + ('\u{a79a}', ['\u{a79b}', '\u{0}', '\u{0}']), ('\u{a79c}', ['\u{a79d}', '\u{0}', '\u{0}']), + ('\u{a79e}', ['\u{a79f}', '\u{0}', '\u{0}']), ('\u{a7a0}', ['\u{a7a1}', '\u{0}', '\u{0}']), + ('\u{a7a2}', ['\u{a7a3}', '\u{0}', '\u{0}']), ('\u{a7a4}', ['\u{a7a5}', '\u{0}', '\u{0}']), + ('\u{a7a6}', ['\u{a7a7}', '\u{0}', '\u{0}']), ('\u{a7a8}', ['\u{a7a9}', '\u{0}', '\u{0}']), + ('\u{a7aa}', ['\u{266}', '\u{0}', '\u{0}']), ('\u{a7ab}', ['\u{25c}', '\u{0}', '\u{0}']), + ('\u{a7ac}', ['\u{261}', '\u{0}', '\u{0}']), ('\u{a7ad}', ['\u{26c}', '\u{0}', '\u{0}']), + ('\u{a7ae}', ['\u{26a}', '\u{0}', '\u{0}']), ('\u{a7b0}', ['\u{29e}', '\u{0}', '\u{0}']), + ('\u{a7b1}', ['\u{287}', '\u{0}', '\u{0}']), ('\u{a7b2}', ['\u{29d}', '\u{0}', '\u{0}']), + ('\u{a7b3}', ['\u{ab53}', '\u{0}', '\u{0}']), ('\u{a7b4}', ['\u{a7b5}', '\u{0}', '\u{0}']), + ('\u{a7b6}', ['\u{a7b7}', '\u{0}', '\u{0}']), ('\u{a7b8}', ['\u{a7b9}', '\u{0}', '\u{0}']), + ('\u{a7ba}', ['\u{a7bb}', '\u{0}', '\u{0}']), ('\u{a7bc}', ['\u{a7bd}', '\u{0}', '\u{0}']), + ('\u{a7be}', ['\u{a7bf}', '\u{0}', '\u{0}']), ('\u{a7c0}', ['\u{a7c1}', '\u{0}', '\u{0}']), + ('\u{a7c2}', ['\u{a7c3}', '\u{0}', '\u{0}']), ('\u{a7c4}', ['\u{a794}', '\u{0}', '\u{0}']), + ('\u{a7c5}', ['\u{282}', '\u{0}', '\u{0}']), ('\u{a7c6}', ['\u{1d8e}', '\u{0}', '\u{0}']), + ('\u{a7c7}', ['\u{a7c8}', '\u{0}', '\u{0}']), ('\u{a7c9}', ['\u{a7ca}', '\u{0}', '\u{0}']), + ('\u{a7cb}', ['\u{264}', '\u{0}', '\u{0}']), ('\u{a7cc}', ['\u{a7cd}', '\u{0}', '\u{0}']), + ('\u{a7ce}', ['\u{a7cf}', '\u{0}', '\u{0}']), ('\u{a7d0}', ['\u{a7d1}', '\u{0}', '\u{0}']), + ('\u{a7d2}', ['\u{a7d3}', '\u{0}', '\u{0}']), ('\u{a7d4}', ['\u{a7d5}', '\u{0}', '\u{0}']), + ('\u{a7d6}', ['\u{a7d7}', '\u{0}', '\u{0}']), ('\u{a7d8}', ['\u{a7d9}', '\u{0}', '\u{0}']), + ('\u{a7da}', ['\u{a7db}', '\u{0}', '\u{0}']), ('\u{a7dc}', ['\u{19b}', '\u{0}', '\u{0}']), + ('\u{a7f5}', ['\u{a7f6}', '\u{0}', '\u{0}']), ('\u{ff21}', ['\u{ff41}', '\u{0}', '\u{0}']), + ('\u{ff22}', ['\u{ff42}', '\u{0}', '\u{0}']), ('\u{ff23}', ['\u{ff43}', '\u{0}', '\u{0}']), + ('\u{ff24}', ['\u{ff44}', '\u{0}', '\u{0}']), ('\u{ff25}', ['\u{ff45}', '\u{0}', '\u{0}']), + ('\u{ff26}', ['\u{ff46}', '\u{0}', '\u{0}']), ('\u{ff27}', ['\u{ff47}', '\u{0}', '\u{0}']), + ('\u{ff28}', ['\u{ff48}', '\u{0}', '\u{0}']), ('\u{ff29}', ['\u{ff49}', '\u{0}', '\u{0}']), + ('\u{ff2a}', ['\u{ff4a}', '\u{0}', '\u{0}']), ('\u{ff2b}', ['\u{ff4b}', '\u{0}', '\u{0}']), + ('\u{ff2c}', ['\u{ff4c}', '\u{0}', '\u{0}']), ('\u{ff2d}', ['\u{ff4d}', '\u{0}', '\u{0}']), + ('\u{ff2e}', ['\u{ff4e}', '\u{0}', '\u{0}']), ('\u{ff2f}', ['\u{ff4f}', '\u{0}', '\u{0}']), + ('\u{ff30}', ['\u{ff50}', '\u{0}', '\u{0}']), ('\u{ff31}', ['\u{ff51}', '\u{0}', '\u{0}']), + ('\u{ff32}', ['\u{ff52}', '\u{0}', '\u{0}']), ('\u{ff33}', ['\u{ff53}', '\u{0}', '\u{0}']), + ('\u{ff34}', ['\u{ff54}', '\u{0}', '\u{0}']), ('\u{ff35}', ['\u{ff55}', '\u{0}', '\u{0}']), + ('\u{ff36}', ['\u{ff56}', '\u{0}', '\u{0}']), ('\u{ff37}', ['\u{ff57}', '\u{0}', '\u{0}']), + ('\u{ff38}', ['\u{ff58}', '\u{0}', '\u{0}']), ('\u{ff39}', ['\u{ff59}', '\u{0}', '\u{0}']), + ('\u{ff3a}', ['\u{ff5a}', '\u{0}', '\u{0}']), + ('\u{10400}', ['\u{10428}', '\u{0}', '\u{0}']), + ('\u{10401}', ['\u{10429}', '\u{0}', '\u{0}']), + ('\u{10402}', ['\u{1042a}', '\u{0}', '\u{0}']), + ('\u{10403}', ['\u{1042b}', '\u{0}', '\u{0}']), + ('\u{10404}', ['\u{1042c}', '\u{0}', '\u{0}']), + ('\u{10405}', ['\u{1042d}', '\u{0}', '\u{0}']), + ('\u{10406}', ['\u{1042e}', '\u{0}', '\u{0}']), + ('\u{10407}', ['\u{1042f}', '\u{0}', '\u{0}']), + ('\u{10408}', ['\u{10430}', '\u{0}', '\u{0}']), + ('\u{10409}', ['\u{10431}', '\u{0}', '\u{0}']), + ('\u{1040a}', ['\u{10432}', '\u{0}', '\u{0}']), + ('\u{1040b}', ['\u{10433}', '\u{0}', '\u{0}']), + ('\u{1040c}', ['\u{10434}', '\u{0}', '\u{0}']), + ('\u{1040d}', ['\u{10435}', '\u{0}', '\u{0}']), + ('\u{1040e}', ['\u{10436}', '\u{0}', '\u{0}']), + ('\u{1040f}', ['\u{10437}', '\u{0}', '\u{0}']), + ('\u{10410}', ['\u{10438}', '\u{0}', '\u{0}']), + ('\u{10411}', ['\u{10439}', '\u{0}', '\u{0}']), + ('\u{10412}', ['\u{1043a}', '\u{0}', '\u{0}']), + ('\u{10413}', ['\u{1043b}', '\u{0}', '\u{0}']), + ('\u{10414}', ['\u{1043c}', '\u{0}', '\u{0}']), + ('\u{10415}', ['\u{1043d}', '\u{0}', '\u{0}']), + ('\u{10416}', ['\u{1043e}', '\u{0}', '\u{0}']), + ('\u{10417}', ['\u{1043f}', '\u{0}', '\u{0}']), + ('\u{10418}', ['\u{10440}', '\u{0}', '\u{0}']), + ('\u{10419}', ['\u{10441}', '\u{0}', '\u{0}']), + ('\u{1041a}', ['\u{10442}', '\u{0}', '\u{0}']), + ('\u{1041b}', ['\u{10443}', '\u{0}', '\u{0}']), + ('\u{1041c}', ['\u{10444}', '\u{0}', '\u{0}']), + ('\u{1041d}', ['\u{10445}', '\u{0}', '\u{0}']), + ('\u{1041e}', ['\u{10446}', '\u{0}', '\u{0}']), + ('\u{1041f}', ['\u{10447}', '\u{0}', '\u{0}']), + ('\u{10420}', ['\u{10448}', '\u{0}', '\u{0}']), + ('\u{10421}', ['\u{10449}', '\u{0}', '\u{0}']), + ('\u{10422}', ['\u{1044a}', '\u{0}', '\u{0}']), + ('\u{10423}', ['\u{1044b}', '\u{0}', '\u{0}']), + ('\u{10424}', ['\u{1044c}', '\u{0}', '\u{0}']), + ('\u{10425}', ['\u{1044d}', '\u{0}', '\u{0}']), + ('\u{10426}', ['\u{1044e}', '\u{0}', '\u{0}']), + ('\u{10427}', ['\u{1044f}', '\u{0}', '\u{0}']), + ('\u{104b0}', ['\u{104d8}', '\u{0}', '\u{0}']), + ('\u{104b1}', ['\u{104d9}', '\u{0}', '\u{0}']), + ('\u{104b2}', ['\u{104da}', '\u{0}', '\u{0}']), + ('\u{104b3}', ['\u{104db}', '\u{0}', '\u{0}']), + ('\u{104b4}', ['\u{104dc}', '\u{0}', '\u{0}']), + ('\u{104b5}', ['\u{104dd}', '\u{0}', '\u{0}']), + ('\u{104b6}', ['\u{104de}', '\u{0}', '\u{0}']), + ('\u{104b7}', ['\u{104df}', '\u{0}', '\u{0}']), + ('\u{104b8}', ['\u{104e0}', '\u{0}', '\u{0}']), + ('\u{104b9}', ['\u{104e1}', '\u{0}', '\u{0}']), + ('\u{104ba}', ['\u{104e2}', '\u{0}', '\u{0}']), + ('\u{104bb}', ['\u{104e3}', '\u{0}', '\u{0}']), + ('\u{104bc}', ['\u{104e4}', '\u{0}', '\u{0}']), + ('\u{104bd}', ['\u{104e5}', '\u{0}', '\u{0}']), + ('\u{104be}', ['\u{104e6}', '\u{0}', '\u{0}']), + ('\u{104bf}', ['\u{104e7}', '\u{0}', '\u{0}']), + ('\u{104c0}', ['\u{104e8}', '\u{0}', '\u{0}']), + ('\u{104c1}', ['\u{104e9}', '\u{0}', '\u{0}']), + ('\u{104c2}', ['\u{104ea}', '\u{0}', '\u{0}']), + ('\u{104c3}', ['\u{104eb}', '\u{0}', '\u{0}']), + ('\u{104c4}', ['\u{104ec}', '\u{0}', '\u{0}']), + ('\u{104c5}', ['\u{104ed}', '\u{0}', '\u{0}']), + ('\u{104c6}', ['\u{104ee}', '\u{0}', '\u{0}']), + ('\u{104c7}', ['\u{104ef}', '\u{0}', '\u{0}']), + ('\u{104c8}', ['\u{104f0}', '\u{0}', '\u{0}']), + ('\u{104c9}', ['\u{104f1}', '\u{0}', '\u{0}']), + ('\u{104ca}', ['\u{104f2}', '\u{0}', '\u{0}']), + ('\u{104cb}', ['\u{104f3}', '\u{0}', '\u{0}']), + ('\u{104cc}', ['\u{104f4}', '\u{0}', '\u{0}']), + ('\u{104cd}', ['\u{104f5}', '\u{0}', '\u{0}']), + ('\u{104ce}', ['\u{104f6}', '\u{0}', '\u{0}']), + ('\u{104cf}', ['\u{104f7}', '\u{0}', '\u{0}']), + ('\u{104d0}', ['\u{104f8}', '\u{0}', '\u{0}']), + ('\u{104d1}', ['\u{104f9}', '\u{0}', '\u{0}']), + ('\u{104d2}', ['\u{104fa}', '\u{0}', '\u{0}']), + ('\u{104d3}', ['\u{104fb}', '\u{0}', '\u{0}']), + ('\u{10570}', ['\u{10597}', '\u{0}', '\u{0}']), + ('\u{10571}', ['\u{10598}', '\u{0}', '\u{0}']), + ('\u{10572}', ['\u{10599}', '\u{0}', '\u{0}']), + ('\u{10573}', ['\u{1059a}', '\u{0}', '\u{0}']), + ('\u{10574}', ['\u{1059b}', '\u{0}', '\u{0}']), + ('\u{10575}', ['\u{1059c}', '\u{0}', '\u{0}']), + ('\u{10576}', ['\u{1059d}', '\u{0}', '\u{0}']), + ('\u{10577}', ['\u{1059e}', '\u{0}', '\u{0}']), + ('\u{10578}', ['\u{1059f}', '\u{0}', '\u{0}']), + ('\u{10579}', ['\u{105a0}', '\u{0}', '\u{0}']), + ('\u{1057a}', ['\u{105a1}', '\u{0}', '\u{0}']), + ('\u{1057c}', ['\u{105a3}', '\u{0}', '\u{0}']), + ('\u{1057d}', ['\u{105a4}', '\u{0}', '\u{0}']), + ('\u{1057e}', ['\u{105a5}', '\u{0}', '\u{0}']), + ('\u{1057f}', ['\u{105a6}', '\u{0}', '\u{0}']), + ('\u{10580}', ['\u{105a7}', '\u{0}', '\u{0}']), + ('\u{10581}', ['\u{105a8}', '\u{0}', '\u{0}']), + ('\u{10582}', ['\u{105a9}', '\u{0}', '\u{0}']), + ('\u{10583}', ['\u{105aa}', '\u{0}', '\u{0}']), + ('\u{10584}', ['\u{105ab}', '\u{0}', '\u{0}']), + ('\u{10585}', ['\u{105ac}', '\u{0}', '\u{0}']), + ('\u{10586}', ['\u{105ad}', '\u{0}', '\u{0}']), + ('\u{10587}', ['\u{105ae}', '\u{0}', '\u{0}']), + ('\u{10588}', ['\u{105af}', '\u{0}', '\u{0}']), + ('\u{10589}', ['\u{105b0}', '\u{0}', '\u{0}']), + ('\u{1058a}', ['\u{105b1}', '\u{0}', '\u{0}']), + ('\u{1058c}', ['\u{105b3}', '\u{0}', '\u{0}']), + ('\u{1058d}', ['\u{105b4}', '\u{0}', '\u{0}']), + ('\u{1058e}', ['\u{105b5}', '\u{0}', '\u{0}']), + ('\u{1058f}', ['\u{105b6}', '\u{0}', '\u{0}']), + ('\u{10590}', ['\u{105b7}', '\u{0}', '\u{0}']), + ('\u{10591}', ['\u{105b8}', '\u{0}', '\u{0}']), + ('\u{10592}', ['\u{105b9}', '\u{0}', '\u{0}']), + ('\u{10594}', ['\u{105bb}', '\u{0}', '\u{0}']), + ('\u{10595}', ['\u{105bc}', '\u{0}', '\u{0}']), + ('\u{10c80}', ['\u{10cc0}', '\u{0}', '\u{0}']), + ('\u{10c81}', ['\u{10cc1}', '\u{0}', '\u{0}']), + ('\u{10c82}', ['\u{10cc2}', '\u{0}', '\u{0}']), + ('\u{10c83}', ['\u{10cc3}', '\u{0}', '\u{0}']), + ('\u{10c84}', ['\u{10cc4}', '\u{0}', '\u{0}']), + ('\u{10c85}', ['\u{10cc5}', '\u{0}', '\u{0}']), + ('\u{10c86}', ['\u{10cc6}', '\u{0}', '\u{0}']), + ('\u{10c87}', ['\u{10cc7}', '\u{0}', '\u{0}']), + ('\u{10c88}', ['\u{10cc8}', '\u{0}', '\u{0}']), + ('\u{10c89}', ['\u{10cc9}', '\u{0}', '\u{0}']), + ('\u{10c8a}', ['\u{10cca}', '\u{0}', '\u{0}']), + ('\u{10c8b}', ['\u{10ccb}', '\u{0}', '\u{0}']), + ('\u{10c8c}', ['\u{10ccc}', '\u{0}', '\u{0}']), + ('\u{10c8d}', ['\u{10ccd}', '\u{0}', '\u{0}']), + ('\u{10c8e}', ['\u{10cce}', '\u{0}', '\u{0}']), + ('\u{10c8f}', ['\u{10ccf}', '\u{0}', '\u{0}']), + ('\u{10c90}', ['\u{10cd0}', '\u{0}', '\u{0}']), + ('\u{10c91}', ['\u{10cd1}', '\u{0}', '\u{0}']), + ('\u{10c92}', ['\u{10cd2}', '\u{0}', '\u{0}']), + ('\u{10c93}', ['\u{10cd3}', '\u{0}', '\u{0}']), + ('\u{10c94}', ['\u{10cd4}', '\u{0}', '\u{0}']), + ('\u{10c95}', ['\u{10cd5}', '\u{0}', '\u{0}']), + ('\u{10c96}', ['\u{10cd6}', '\u{0}', '\u{0}']), + ('\u{10c97}', ['\u{10cd7}', '\u{0}', '\u{0}']), + ('\u{10c98}', ['\u{10cd8}', '\u{0}', '\u{0}']), + ('\u{10c99}', ['\u{10cd9}', '\u{0}', '\u{0}']), + ('\u{10c9a}', ['\u{10cda}', '\u{0}', '\u{0}']), + ('\u{10c9b}', ['\u{10cdb}', '\u{0}', '\u{0}']), + ('\u{10c9c}', ['\u{10cdc}', '\u{0}', '\u{0}']), + ('\u{10c9d}', ['\u{10cdd}', '\u{0}', '\u{0}']), + ('\u{10c9e}', ['\u{10cde}', '\u{0}', '\u{0}']), + ('\u{10c9f}', ['\u{10cdf}', '\u{0}', '\u{0}']), + ('\u{10ca0}', ['\u{10ce0}', '\u{0}', '\u{0}']), + ('\u{10ca1}', ['\u{10ce1}', '\u{0}', '\u{0}']), + ('\u{10ca2}', ['\u{10ce2}', '\u{0}', '\u{0}']), + ('\u{10ca3}', ['\u{10ce3}', '\u{0}', '\u{0}']), + ('\u{10ca4}', ['\u{10ce4}', '\u{0}', '\u{0}']), + ('\u{10ca5}', ['\u{10ce5}', '\u{0}', '\u{0}']), + ('\u{10ca6}', ['\u{10ce6}', '\u{0}', '\u{0}']), + ('\u{10ca7}', ['\u{10ce7}', '\u{0}', '\u{0}']), + ('\u{10ca8}', ['\u{10ce8}', '\u{0}', '\u{0}']), + ('\u{10ca9}', ['\u{10ce9}', '\u{0}', '\u{0}']), + ('\u{10caa}', ['\u{10cea}', '\u{0}', '\u{0}']), + ('\u{10cab}', ['\u{10ceb}', '\u{0}', '\u{0}']), + ('\u{10cac}', ['\u{10cec}', '\u{0}', '\u{0}']), + ('\u{10cad}', ['\u{10ced}', '\u{0}', '\u{0}']), + ('\u{10cae}', ['\u{10cee}', '\u{0}', '\u{0}']), + ('\u{10caf}', ['\u{10cef}', '\u{0}', '\u{0}']), + ('\u{10cb0}', ['\u{10cf0}', '\u{0}', '\u{0}']), + ('\u{10cb1}', ['\u{10cf1}', '\u{0}', '\u{0}']), + ('\u{10cb2}', ['\u{10cf2}', '\u{0}', '\u{0}']), + ('\u{10d50}', ['\u{10d70}', '\u{0}', '\u{0}']), + ('\u{10d51}', ['\u{10d71}', '\u{0}', '\u{0}']), + ('\u{10d52}', ['\u{10d72}', '\u{0}', '\u{0}']), + ('\u{10d53}', ['\u{10d73}', '\u{0}', '\u{0}']), + ('\u{10d54}', ['\u{10d74}', '\u{0}', '\u{0}']), + ('\u{10d55}', ['\u{10d75}', '\u{0}', '\u{0}']), + ('\u{10d56}', ['\u{10d76}', '\u{0}', '\u{0}']), + ('\u{10d57}', ['\u{10d77}', '\u{0}', '\u{0}']), + ('\u{10d58}', ['\u{10d78}', '\u{0}', '\u{0}']), + ('\u{10d59}', ['\u{10d79}', '\u{0}', '\u{0}']), + ('\u{10d5a}', ['\u{10d7a}', '\u{0}', '\u{0}']), + ('\u{10d5b}', ['\u{10d7b}', '\u{0}', '\u{0}']), + ('\u{10d5c}', ['\u{10d7c}', '\u{0}', '\u{0}']), + ('\u{10d5d}', ['\u{10d7d}', '\u{0}', '\u{0}']), + ('\u{10d5e}', ['\u{10d7e}', '\u{0}', '\u{0}']), + ('\u{10d5f}', ['\u{10d7f}', '\u{0}', '\u{0}']), + ('\u{10d60}', ['\u{10d80}', '\u{0}', '\u{0}']), + ('\u{10d61}', ['\u{10d81}', '\u{0}', '\u{0}']), + ('\u{10d62}', ['\u{10d82}', '\u{0}', '\u{0}']), + ('\u{10d63}', ['\u{10d83}', '\u{0}', '\u{0}']), + ('\u{10d64}', ['\u{10d84}', '\u{0}', '\u{0}']), + ('\u{10d65}', ['\u{10d85}', '\u{0}', '\u{0}']), + ('\u{118a0}', ['\u{118c0}', '\u{0}', '\u{0}']), + ('\u{118a1}', ['\u{118c1}', '\u{0}', '\u{0}']), + ('\u{118a2}', ['\u{118c2}', '\u{0}', '\u{0}']), + ('\u{118a3}', ['\u{118c3}', '\u{0}', '\u{0}']), + ('\u{118a4}', ['\u{118c4}', '\u{0}', '\u{0}']), + ('\u{118a5}', ['\u{118c5}', '\u{0}', '\u{0}']), + ('\u{118a6}', ['\u{118c6}', '\u{0}', '\u{0}']), + ('\u{118a7}', ['\u{118c7}', '\u{0}', '\u{0}']), + ('\u{118a8}', ['\u{118c8}', '\u{0}', '\u{0}']), + ('\u{118a9}', ['\u{118c9}', '\u{0}', '\u{0}']), + ('\u{118aa}', ['\u{118ca}', '\u{0}', '\u{0}']), + ('\u{118ab}', ['\u{118cb}', '\u{0}', '\u{0}']), + ('\u{118ac}', ['\u{118cc}', '\u{0}', '\u{0}']), + ('\u{118ad}', ['\u{118cd}', '\u{0}', '\u{0}']), + ('\u{118ae}', ['\u{118ce}', '\u{0}', '\u{0}']), + ('\u{118af}', ['\u{118cf}', '\u{0}', '\u{0}']), + ('\u{118b0}', ['\u{118d0}', '\u{0}', '\u{0}']), + ('\u{118b1}', ['\u{118d1}', '\u{0}', '\u{0}']), + ('\u{118b2}', ['\u{118d2}', '\u{0}', '\u{0}']), + ('\u{118b3}', ['\u{118d3}', '\u{0}', '\u{0}']), + ('\u{118b4}', ['\u{118d4}', '\u{0}', '\u{0}']), + ('\u{118b5}', ['\u{118d5}', '\u{0}', '\u{0}']), + ('\u{118b6}', ['\u{118d6}', '\u{0}', '\u{0}']), + ('\u{118b7}', ['\u{118d7}', '\u{0}', '\u{0}']), + ('\u{118b8}', ['\u{118d8}', '\u{0}', '\u{0}']), + ('\u{118b9}', ['\u{118d9}', '\u{0}', '\u{0}']), + ('\u{118ba}', ['\u{118da}', '\u{0}', '\u{0}']), + ('\u{118bb}', ['\u{118db}', '\u{0}', '\u{0}']), + ('\u{118bc}', ['\u{118dc}', '\u{0}', '\u{0}']), + ('\u{118bd}', ['\u{118dd}', '\u{0}', '\u{0}']), + ('\u{118be}', ['\u{118de}', '\u{0}', '\u{0}']), + ('\u{118bf}', ['\u{118df}', '\u{0}', '\u{0}']), + ('\u{16e40}', ['\u{16e60}', '\u{0}', '\u{0}']), + ('\u{16e41}', ['\u{16e61}', '\u{0}', '\u{0}']), + ('\u{16e42}', ['\u{16e62}', '\u{0}', '\u{0}']), + ('\u{16e43}', ['\u{16e63}', '\u{0}', '\u{0}']), + ('\u{16e44}', ['\u{16e64}', '\u{0}', '\u{0}']), + ('\u{16e45}', ['\u{16e65}', '\u{0}', '\u{0}']), + ('\u{16e46}', ['\u{16e66}', '\u{0}', '\u{0}']), + ('\u{16e47}', ['\u{16e67}', '\u{0}', '\u{0}']), + ('\u{16e48}', ['\u{16e68}', '\u{0}', '\u{0}']), + ('\u{16e49}', ['\u{16e69}', '\u{0}', '\u{0}']), + ('\u{16e4a}', ['\u{16e6a}', '\u{0}', '\u{0}']), + ('\u{16e4b}', ['\u{16e6b}', '\u{0}', '\u{0}']), + ('\u{16e4c}', ['\u{16e6c}', '\u{0}', '\u{0}']), + ('\u{16e4d}', ['\u{16e6d}', '\u{0}', '\u{0}']), + ('\u{16e4e}', ['\u{16e6e}', '\u{0}', '\u{0}']), + ('\u{16e4f}', ['\u{16e6f}', '\u{0}', '\u{0}']), + ('\u{16e50}', ['\u{16e70}', '\u{0}', '\u{0}']), + ('\u{16e51}', ['\u{16e71}', '\u{0}', '\u{0}']), + ('\u{16e52}', ['\u{16e72}', '\u{0}', '\u{0}']), + ('\u{16e53}', ['\u{16e73}', '\u{0}', '\u{0}']), + ('\u{16e54}', ['\u{16e74}', '\u{0}', '\u{0}']), + ('\u{16e55}', ['\u{16e75}', '\u{0}', '\u{0}']), + ('\u{16e56}', ['\u{16e76}', '\u{0}', '\u{0}']), + ('\u{16e57}', ['\u{16e77}', '\u{0}', '\u{0}']), + ('\u{16e58}', ['\u{16e78}', '\u{0}', '\u{0}']), + ('\u{16e59}', ['\u{16e79}', '\u{0}', '\u{0}']), + ('\u{16e5a}', ['\u{16e7a}', '\u{0}', '\u{0}']), + ('\u{16e5b}', ['\u{16e7b}', '\u{0}', '\u{0}']), + ('\u{16e5c}', ['\u{16e7c}', '\u{0}', '\u{0}']), + ('\u{16e5d}', ['\u{16e7d}', '\u{0}', '\u{0}']), + ('\u{16e5e}', ['\u{16e7e}', '\u{0}', '\u{0}']), + ('\u{16e5f}', ['\u{16e7f}', '\u{0}', '\u{0}']), + ('\u{16ea0}', ['\u{16ebb}', '\u{0}', '\u{0}']), + ('\u{16ea1}', ['\u{16ebc}', '\u{0}', '\u{0}']), + ('\u{16ea2}', ['\u{16ebd}', '\u{0}', '\u{0}']), + ('\u{16ea3}', ['\u{16ebe}', '\u{0}', '\u{0}']), + ('\u{16ea4}', ['\u{16ebf}', '\u{0}', '\u{0}']), + ('\u{16ea5}', ['\u{16ec0}', '\u{0}', '\u{0}']), + ('\u{16ea6}', ['\u{16ec1}', '\u{0}', '\u{0}']), + ('\u{16ea7}', ['\u{16ec2}', '\u{0}', '\u{0}']), + ('\u{16ea8}', ['\u{16ec3}', '\u{0}', '\u{0}']), + ('\u{16ea9}', ['\u{16ec4}', '\u{0}', '\u{0}']), + ('\u{16eaa}', ['\u{16ec5}', '\u{0}', '\u{0}']), + ('\u{16eab}', ['\u{16ec6}', '\u{0}', '\u{0}']), + ('\u{16eac}', ['\u{16ec7}', '\u{0}', '\u{0}']), + ('\u{16ead}', ['\u{16ec8}', '\u{0}', '\u{0}']), + ('\u{16eae}', ['\u{16ec9}', '\u{0}', '\u{0}']), + ('\u{16eaf}', ['\u{16eca}', '\u{0}', '\u{0}']), + ('\u{16eb0}', ['\u{16ecb}', '\u{0}', '\u{0}']), + ('\u{16eb1}', ['\u{16ecc}', '\u{0}', '\u{0}']), + ('\u{16eb2}', ['\u{16ecd}', '\u{0}', '\u{0}']), + ('\u{16eb3}', ['\u{16ece}', '\u{0}', '\u{0}']), + ('\u{16eb4}', ['\u{16ecf}', '\u{0}', '\u{0}']), + ('\u{16eb5}', ['\u{16ed0}', '\u{0}', '\u{0}']), + ('\u{16eb6}', ['\u{16ed1}', '\u{0}', '\u{0}']), + ('\u{16eb7}', ['\u{16ed2}', '\u{0}', '\u{0}']), + ('\u{16eb8}', ['\u{16ed3}', '\u{0}', '\u{0}']), + ('\u{1e900}', ['\u{1e922}', '\u{0}', '\u{0}']), + ('\u{1e901}', ['\u{1e923}', '\u{0}', '\u{0}']), + ('\u{1e902}', ['\u{1e924}', '\u{0}', '\u{0}']), + ('\u{1e903}', ['\u{1e925}', '\u{0}', '\u{0}']), + ('\u{1e904}', ['\u{1e926}', '\u{0}', '\u{0}']), + ('\u{1e905}', ['\u{1e927}', '\u{0}', '\u{0}']), + ('\u{1e906}', ['\u{1e928}', '\u{0}', '\u{0}']), + ('\u{1e907}', ['\u{1e929}', '\u{0}', '\u{0}']), + ('\u{1e908}', ['\u{1e92a}', '\u{0}', '\u{0}']), + ('\u{1e909}', ['\u{1e92b}', '\u{0}', '\u{0}']), + ('\u{1e90a}', ['\u{1e92c}', '\u{0}', '\u{0}']), + ('\u{1e90b}', ['\u{1e92d}', '\u{0}', '\u{0}']), + ('\u{1e90c}', ['\u{1e92e}', '\u{0}', '\u{0}']), + ('\u{1e90d}', ['\u{1e92f}', '\u{0}', '\u{0}']), + ('\u{1e90e}', ['\u{1e930}', '\u{0}', '\u{0}']), + ('\u{1e90f}', ['\u{1e931}', '\u{0}', '\u{0}']), + ('\u{1e910}', ['\u{1e932}', '\u{0}', '\u{0}']), + ('\u{1e911}', ['\u{1e933}', '\u{0}', '\u{0}']), + ('\u{1e912}', ['\u{1e934}', '\u{0}', '\u{0}']), + ('\u{1e913}', ['\u{1e935}', '\u{0}', '\u{0}']), + ('\u{1e914}', ['\u{1e936}', '\u{0}', '\u{0}']), + ('\u{1e915}', ['\u{1e937}', '\u{0}', '\u{0}']), + ('\u{1e916}', ['\u{1e938}', '\u{0}', '\u{0}']), + ('\u{1e917}', ['\u{1e939}', '\u{0}', '\u{0}']), + ('\u{1e918}', ['\u{1e93a}', '\u{0}', '\u{0}']), + ('\u{1e919}', ['\u{1e93b}', '\u{0}', '\u{0}']), + ('\u{1e91a}', ['\u{1e93c}', '\u{0}', '\u{0}']), + ('\u{1e91b}', ['\u{1e93d}', '\u{0}', '\u{0}']), + ('\u{1e91c}', ['\u{1e93e}', '\u{0}', '\u{0}']), + ('\u{1e91d}', ['\u{1e93f}', '\u{0}', '\u{0}']), + ('\u{1e91e}', ['\u{1e940}', '\u{0}', '\u{0}']), + ('\u{1e91f}', ['\u{1e941}', '\u{0}', '\u{0}']), + ('\u{1e920}', ['\u{1e942}', '\u{0}', '\u{0}']), + ('\u{1e921}', ['\u{1e943}', '\u{0}', '\u{0}']), +]; + +#[rustfmt::skip] +pub(super) static TO_UPPER: &[(char, [char; 3]); 1554] = &[ + ('\u{b5}', ['\u{39c}', '\u{0}', '\u{0}']), ('\u{df}', ['S', 'S', '\u{0}']), + ('\u{e0}', ['\u{c0}', '\u{0}', '\u{0}']), ('\u{e1}', ['\u{c1}', '\u{0}', '\u{0}']), + ('\u{e2}', ['\u{c2}', '\u{0}', '\u{0}']), ('\u{e3}', ['\u{c3}', '\u{0}', '\u{0}']), + ('\u{e4}', ['\u{c4}', '\u{0}', '\u{0}']), ('\u{e5}', ['\u{c5}', '\u{0}', '\u{0}']), + ('\u{e6}', ['\u{c6}', '\u{0}', '\u{0}']), ('\u{e7}', ['\u{c7}', '\u{0}', '\u{0}']), + ('\u{e8}', ['\u{c8}', '\u{0}', '\u{0}']), ('\u{e9}', ['\u{c9}', '\u{0}', '\u{0}']), + ('\u{ea}', ['\u{ca}', '\u{0}', '\u{0}']), ('\u{eb}', ['\u{cb}', '\u{0}', '\u{0}']), + ('\u{ec}', ['\u{cc}', '\u{0}', '\u{0}']), ('\u{ed}', ['\u{cd}', '\u{0}', '\u{0}']), + ('\u{ee}', ['\u{ce}', '\u{0}', '\u{0}']), ('\u{ef}', ['\u{cf}', '\u{0}', '\u{0}']), + ('\u{f0}', ['\u{d0}', '\u{0}', '\u{0}']), ('\u{f1}', ['\u{d1}', '\u{0}', '\u{0}']), + ('\u{f2}', ['\u{d2}', '\u{0}', '\u{0}']), ('\u{f3}', ['\u{d3}', '\u{0}', '\u{0}']), + ('\u{f4}', ['\u{d4}', '\u{0}', '\u{0}']), ('\u{f5}', ['\u{d5}', '\u{0}', '\u{0}']), + ('\u{f6}', ['\u{d6}', '\u{0}', '\u{0}']), ('\u{f8}', ['\u{d8}', '\u{0}', '\u{0}']), + ('\u{f9}', ['\u{d9}', '\u{0}', '\u{0}']), ('\u{fa}', ['\u{da}', '\u{0}', '\u{0}']), + ('\u{fb}', ['\u{db}', '\u{0}', '\u{0}']), ('\u{fc}', ['\u{dc}', '\u{0}', '\u{0}']), + ('\u{fd}', ['\u{dd}', '\u{0}', '\u{0}']), ('\u{fe}', ['\u{de}', '\u{0}', '\u{0}']), + ('\u{ff}', ['\u{178}', '\u{0}', '\u{0}']), ('\u{101}', ['\u{100}', '\u{0}', '\u{0}']), + ('\u{103}', ['\u{102}', '\u{0}', '\u{0}']), ('\u{105}', ['\u{104}', '\u{0}', '\u{0}']), + ('\u{107}', ['\u{106}', '\u{0}', '\u{0}']), ('\u{109}', ['\u{108}', '\u{0}', '\u{0}']), + ('\u{10b}', ['\u{10a}', '\u{0}', '\u{0}']), ('\u{10d}', ['\u{10c}', '\u{0}', '\u{0}']), + ('\u{10f}', ['\u{10e}', '\u{0}', '\u{0}']), ('\u{111}', ['\u{110}', '\u{0}', '\u{0}']), + ('\u{113}', ['\u{112}', '\u{0}', '\u{0}']), ('\u{115}', ['\u{114}', '\u{0}', '\u{0}']), + ('\u{117}', ['\u{116}', '\u{0}', '\u{0}']), ('\u{119}', ['\u{118}', '\u{0}', '\u{0}']), + ('\u{11b}', ['\u{11a}', '\u{0}', '\u{0}']), ('\u{11d}', ['\u{11c}', '\u{0}', '\u{0}']), + ('\u{11f}', ['\u{11e}', '\u{0}', '\u{0}']), ('\u{121}', ['\u{120}', '\u{0}', '\u{0}']), + ('\u{123}', ['\u{122}', '\u{0}', '\u{0}']), ('\u{125}', ['\u{124}', '\u{0}', '\u{0}']), + ('\u{127}', ['\u{126}', '\u{0}', '\u{0}']), ('\u{129}', ['\u{128}', '\u{0}', '\u{0}']), + ('\u{12b}', ['\u{12a}', '\u{0}', '\u{0}']), ('\u{12d}', ['\u{12c}', '\u{0}', '\u{0}']), + ('\u{12f}', ['\u{12e}', '\u{0}', '\u{0}']), ('\u{131}', ['I', '\u{0}', '\u{0}']), + ('\u{133}', ['\u{132}', '\u{0}', '\u{0}']), ('\u{135}', ['\u{134}', '\u{0}', '\u{0}']), + ('\u{137}', ['\u{136}', '\u{0}', '\u{0}']), ('\u{13a}', ['\u{139}', '\u{0}', '\u{0}']), + ('\u{13c}', ['\u{13b}', '\u{0}', '\u{0}']), ('\u{13e}', ['\u{13d}', '\u{0}', '\u{0}']), + ('\u{140}', ['\u{13f}', '\u{0}', '\u{0}']), ('\u{142}', ['\u{141}', '\u{0}', '\u{0}']), + ('\u{144}', ['\u{143}', '\u{0}', '\u{0}']), ('\u{146}', ['\u{145}', '\u{0}', '\u{0}']), + ('\u{148}', ['\u{147}', '\u{0}', '\u{0}']), ('\u{149}', ['\u{2bc}', 'N', '\u{0}']), + ('\u{14b}', ['\u{14a}', '\u{0}', '\u{0}']), ('\u{14d}', ['\u{14c}', '\u{0}', '\u{0}']), + ('\u{14f}', ['\u{14e}', '\u{0}', '\u{0}']), ('\u{151}', ['\u{150}', '\u{0}', '\u{0}']), + ('\u{153}', ['\u{152}', '\u{0}', '\u{0}']), ('\u{155}', ['\u{154}', '\u{0}', '\u{0}']), + ('\u{157}', ['\u{156}', '\u{0}', '\u{0}']), ('\u{159}', ['\u{158}', '\u{0}', '\u{0}']), + ('\u{15b}', ['\u{15a}', '\u{0}', '\u{0}']), ('\u{15d}', ['\u{15c}', '\u{0}', '\u{0}']), + ('\u{15f}', ['\u{15e}', '\u{0}', '\u{0}']), ('\u{161}', ['\u{160}', '\u{0}', '\u{0}']), + ('\u{163}', ['\u{162}', '\u{0}', '\u{0}']), ('\u{165}', ['\u{164}', '\u{0}', '\u{0}']), + ('\u{167}', ['\u{166}', '\u{0}', '\u{0}']), ('\u{169}', ['\u{168}', '\u{0}', '\u{0}']), + ('\u{16b}', ['\u{16a}', '\u{0}', '\u{0}']), ('\u{16d}', ['\u{16c}', '\u{0}', '\u{0}']), + ('\u{16f}', ['\u{16e}', '\u{0}', '\u{0}']), ('\u{171}', ['\u{170}', '\u{0}', '\u{0}']), + ('\u{173}', ['\u{172}', '\u{0}', '\u{0}']), ('\u{175}', ['\u{174}', '\u{0}', '\u{0}']), + ('\u{177}', ['\u{176}', '\u{0}', '\u{0}']), ('\u{17a}', ['\u{179}', '\u{0}', '\u{0}']), + ('\u{17c}', ['\u{17b}', '\u{0}', '\u{0}']), ('\u{17e}', ['\u{17d}', '\u{0}', '\u{0}']), + ('\u{17f}', ['S', '\u{0}', '\u{0}']), ('\u{180}', ['\u{243}', '\u{0}', '\u{0}']), + ('\u{183}', ['\u{182}', '\u{0}', '\u{0}']), ('\u{185}', ['\u{184}', '\u{0}', '\u{0}']), + ('\u{188}', ['\u{187}', '\u{0}', '\u{0}']), ('\u{18c}', ['\u{18b}', '\u{0}', '\u{0}']), + ('\u{192}', ['\u{191}', '\u{0}', '\u{0}']), ('\u{195}', ['\u{1f6}', '\u{0}', '\u{0}']), + ('\u{199}', ['\u{198}', '\u{0}', '\u{0}']), ('\u{19a}', ['\u{23d}', '\u{0}', '\u{0}']), + ('\u{19b}', ['\u{a7dc}', '\u{0}', '\u{0}']), ('\u{19e}', ['\u{220}', '\u{0}', '\u{0}']), + ('\u{1a1}', ['\u{1a0}', '\u{0}', '\u{0}']), ('\u{1a3}', ['\u{1a2}', '\u{0}', '\u{0}']), + ('\u{1a5}', ['\u{1a4}', '\u{0}', '\u{0}']), ('\u{1a8}', ['\u{1a7}', '\u{0}', '\u{0}']), + ('\u{1ad}', ['\u{1ac}', '\u{0}', '\u{0}']), ('\u{1b0}', ['\u{1af}', '\u{0}', '\u{0}']), + ('\u{1b4}', ['\u{1b3}', '\u{0}', '\u{0}']), ('\u{1b6}', ['\u{1b5}', '\u{0}', '\u{0}']), + ('\u{1b9}', ['\u{1b8}', '\u{0}', '\u{0}']), ('\u{1bd}', ['\u{1bc}', '\u{0}', '\u{0}']), + ('\u{1bf}', ['\u{1f7}', '\u{0}', '\u{0}']), ('\u{1c5}', ['\u{1c4}', '\u{0}', '\u{0}']), + ('\u{1c6}', ['\u{1c4}', '\u{0}', '\u{0}']), ('\u{1c8}', ['\u{1c7}', '\u{0}', '\u{0}']), + ('\u{1c9}', ['\u{1c7}', '\u{0}', '\u{0}']), ('\u{1cb}', ['\u{1ca}', '\u{0}', '\u{0}']), + ('\u{1cc}', ['\u{1ca}', '\u{0}', '\u{0}']), ('\u{1ce}', ['\u{1cd}', '\u{0}', '\u{0}']), + ('\u{1d0}', ['\u{1cf}', '\u{0}', '\u{0}']), ('\u{1d2}', ['\u{1d1}', '\u{0}', '\u{0}']), + ('\u{1d4}', ['\u{1d3}', '\u{0}', '\u{0}']), ('\u{1d6}', ['\u{1d5}', '\u{0}', '\u{0}']), + ('\u{1d8}', ['\u{1d7}', '\u{0}', '\u{0}']), ('\u{1da}', ['\u{1d9}', '\u{0}', '\u{0}']), + ('\u{1dc}', ['\u{1db}', '\u{0}', '\u{0}']), ('\u{1dd}', ['\u{18e}', '\u{0}', '\u{0}']), + ('\u{1df}', ['\u{1de}', '\u{0}', '\u{0}']), ('\u{1e1}', ['\u{1e0}', '\u{0}', '\u{0}']), + ('\u{1e3}', ['\u{1e2}', '\u{0}', '\u{0}']), ('\u{1e5}', ['\u{1e4}', '\u{0}', '\u{0}']), + ('\u{1e7}', ['\u{1e6}', '\u{0}', '\u{0}']), ('\u{1e9}', ['\u{1e8}', '\u{0}', '\u{0}']), + ('\u{1eb}', ['\u{1ea}', '\u{0}', '\u{0}']), ('\u{1ed}', ['\u{1ec}', '\u{0}', '\u{0}']), + ('\u{1ef}', ['\u{1ee}', '\u{0}', '\u{0}']), ('\u{1f0}', ['J', '\u{30c}', '\u{0}']), + ('\u{1f2}', ['\u{1f1}', '\u{0}', '\u{0}']), ('\u{1f3}', ['\u{1f1}', '\u{0}', '\u{0}']), + ('\u{1f5}', ['\u{1f4}', '\u{0}', '\u{0}']), ('\u{1f9}', ['\u{1f8}', '\u{0}', '\u{0}']), + ('\u{1fb}', ['\u{1fa}', '\u{0}', '\u{0}']), ('\u{1fd}', ['\u{1fc}', '\u{0}', '\u{0}']), + ('\u{1ff}', ['\u{1fe}', '\u{0}', '\u{0}']), ('\u{201}', ['\u{200}', '\u{0}', '\u{0}']), + ('\u{203}', ['\u{202}', '\u{0}', '\u{0}']), ('\u{205}', ['\u{204}', '\u{0}', '\u{0}']), + ('\u{207}', ['\u{206}', '\u{0}', '\u{0}']), ('\u{209}', ['\u{208}', '\u{0}', '\u{0}']), + ('\u{20b}', ['\u{20a}', '\u{0}', '\u{0}']), ('\u{20d}', ['\u{20c}', '\u{0}', '\u{0}']), + ('\u{20f}', ['\u{20e}', '\u{0}', '\u{0}']), ('\u{211}', ['\u{210}', '\u{0}', '\u{0}']), + ('\u{213}', ['\u{212}', '\u{0}', '\u{0}']), ('\u{215}', ['\u{214}', '\u{0}', '\u{0}']), + ('\u{217}', ['\u{216}', '\u{0}', '\u{0}']), ('\u{219}', ['\u{218}', '\u{0}', '\u{0}']), + ('\u{21b}', ['\u{21a}', '\u{0}', '\u{0}']), ('\u{21d}', ['\u{21c}', '\u{0}', '\u{0}']), + ('\u{21f}', ['\u{21e}', '\u{0}', '\u{0}']), ('\u{223}', ['\u{222}', '\u{0}', '\u{0}']), + ('\u{225}', ['\u{224}', '\u{0}', '\u{0}']), ('\u{227}', ['\u{226}', '\u{0}', '\u{0}']), + ('\u{229}', ['\u{228}', '\u{0}', '\u{0}']), ('\u{22b}', ['\u{22a}', '\u{0}', '\u{0}']), + ('\u{22d}', ['\u{22c}', '\u{0}', '\u{0}']), ('\u{22f}', ['\u{22e}', '\u{0}', '\u{0}']), + ('\u{231}', ['\u{230}', '\u{0}', '\u{0}']), ('\u{233}', ['\u{232}', '\u{0}', '\u{0}']), + ('\u{23c}', ['\u{23b}', '\u{0}', '\u{0}']), ('\u{23f}', ['\u{2c7e}', '\u{0}', '\u{0}']), + ('\u{240}', ['\u{2c7f}', '\u{0}', '\u{0}']), ('\u{242}', ['\u{241}', '\u{0}', '\u{0}']), + ('\u{247}', ['\u{246}', '\u{0}', '\u{0}']), ('\u{249}', ['\u{248}', '\u{0}', '\u{0}']), + ('\u{24b}', ['\u{24a}', '\u{0}', '\u{0}']), ('\u{24d}', ['\u{24c}', '\u{0}', '\u{0}']), + ('\u{24f}', ['\u{24e}', '\u{0}', '\u{0}']), ('\u{250}', ['\u{2c6f}', '\u{0}', '\u{0}']), + ('\u{251}', ['\u{2c6d}', '\u{0}', '\u{0}']), ('\u{252}', ['\u{2c70}', '\u{0}', '\u{0}']), + ('\u{253}', ['\u{181}', '\u{0}', '\u{0}']), ('\u{254}', ['\u{186}', '\u{0}', '\u{0}']), + ('\u{256}', ['\u{189}', '\u{0}', '\u{0}']), ('\u{257}', ['\u{18a}', '\u{0}', '\u{0}']), + ('\u{259}', ['\u{18f}', '\u{0}', '\u{0}']), ('\u{25b}', ['\u{190}', '\u{0}', '\u{0}']), + ('\u{25c}', ['\u{a7ab}', '\u{0}', '\u{0}']), ('\u{260}', ['\u{193}', '\u{0}', '\u{0}']), + ('\u{261}', ['\u{a7ac}', '\u{0}', '\u{0}']), ('\u{263}', ['\u{194}', '\u{0}', '\u{0}']), + ('\u{264}', ['\u{a7cb}', '\u{0}', '\u{0}']), ('\u{265}', ['\u{a78d}', '\u{0}', '\u{0}']), + ('\u{266}', ['\u{a7aa}', '\u{0}', '\u{0}']), ('\u{268}', ['\u{197}', '\u{0}', '\u{0}']), + ('\u{269}', ['\u{196}', '\u{0}', '\u{0}']), ('\u{26a}', ['\u{a7ae}', '\u{0}', '\u{0}']), + ('\u{26b}', ['\u{2c62}', '\u{0}', '\u{0}']), ('\u{26c}', ['\u{a7ad}', '\u{0}', '\u{0}']), + ('\u{26f}', ['\u{19c}', '\u{0}', '\u{0}']), ('\u{271}', ['\u{2c6e}', '\u{0}', '\u{0}']), + ('\u{272}', ['\u{19d}', '\u{0}', '\u{0}']), ('\u{275}', ['\u{19f}', '\u{0}', '\u{0}']), + ('\u{27d}', ['\u{2c64}', '\u{0}', '\u{0}']), ('\u{280}', ['\u{1a6}', '\u{0}', '\u{0}']), + ('\u{282}', ['\u{a7c5}', '\u{0}', '\u{0}']), ('\u{283}', ['\u{1a9}', '\u{0}', '\u{0}']), + ('\u{287}', ['\u{a7b1}', '\u{0}', '\u{0}']), ('\u{288}', ['\u{1ae}', '\u{0}', '\u{0}']), + ('\u{289}', ['\u{244}', '\u{0}', '\u{0}']), ('\u{28a}', ['\u{1b1}', '\u{0}', '\u{0}']), + ('\u{28b}', ['\u{1b2}', '\u{0}', '\u{0}']), ('\u{28c}', ['\u{245}', '\u{0}', '\u{0}']), + ('\u{292}', ['\u{1b7}', '\u{0}', '\u{0}']), ('\u{29d}', ['\u{a7b2}', '\u{0}', '\u{0}']), + ('\u{29e}', ['\u{a7b0}', '\u{0}', '\u{0}']), ('\u{345}', ['\u{399}', '\u{0}', '\u{0}']), + ('\u{371}', ['\u{370}', '\u{0}', '\u{0}']), ('\u{373}', ['\u{372}', '\u{0}', '\u{0}']), + ('\u{377}', ['\u{376}', '\u{0}', '\u{0}']), ('\u{37b}', ['\u{3fd}', '\u{0}', '\u{0}']), + ('\u{37c}', ['\u{3fe}', '\u{0}', '\u{0}']), ('\u{37d}', ['\u{3ff}', '\u{0}', '\u{0}']), + ('\u{390}', ['\u{399}', '\u{308}', '\u{301}']), ('\u{3ac}', ['\u{386}', '\u{0}', '\u{0}']), + ('\u{3ad}', ['\u{388}', '\u{0}', '\u{0}']), ('\u{3ae}', ['\u{389}', '\u{0}', '\u{0}']), + ('\u{3af}', ['\u{38a}', '\u{0}', '\u{0}']), ('\u{3b0}', ['\u{3a5}', '\u{308}', '\u{301}']), + ('\u{3b1}', ['\u{391}', '\u{0}', '\u{0}']), ('\u{3b2}', ['\u{392}', '\u{0}', '\u{0}']), + ('\u{3b3}', ['\u{393}', '\u{0}', '\u{0}']), ('\u{3b4}', ['\u{394}', '\u{0}', '\u{0}']), + ('\u{3b5}', ['\u{395}', '\u{0}', '\u{0}']), ('\u{3b6}', ['\u{396}', '\u{0}', '\u{0}']), + ('\u{3b7}', ['\u{397}', '\u{0}', '\u{0}']), ('\u{3b8}', ['\u{398}', '\u{0}', '\u{0}']), + ('\u{3b9}', ['\u{399}', '\u{0}', '\u{0}']), ('\u{3ba}', ['\u{39a}', '\u{0}', '\u{0}']), + ('\u{3bb}', ['\u{39b}', '\u{0}', '\u{0}']), ('\u{3bc}', ['\u{39c}', '\u{0}', '\u{0}']), + ('\u{3bd}', ['\u{39d}', '\u{0}', '\u{0}']), ('\u{3be}', ['\u{39e}', '\u{0}', '\u{0}']), + ('\u{3bf}', ['\u{39f}', '\u{0}', '\u{0}']), ('\u{3c0}', ['\u{3a0}', '\u{0}', '\u{0}']), + ('\u{3c1}', ['\u{3a1}', '\u{0}', '\u{0}']), ('\u{3c2}', ['\u{3a3}', '\u{0}', '\u{0}']), + ('\u{3c3}', ['\u{3a3}', '\u{0}', '\u{0}']), ('\u{3c4}', ['\u{3a4}', '\u{0}', '\u{0}']), + ('\u{3c5}', ['\u{3a5}', '\u{0}', '\u{0}']), ('\u{3c6}', ['\u{3a6}', '\u{0}', '\u{0}']), + ('\u{3c7}', ['\u{3a7}', '\u{0}', '\u{0}']), ('\u{3c8}', ['\u{3a8}', '\u{0}', '\u{0}']), + ('\u{3c9}', ['\u{3a9}', '\u{0}', '\u{0}']), ('\u{3ca}', ['\u{3aa}', '\u{0}', '\u{0}']), + ('\u{3cb}', ['\u{3ab}', '\u{0}', '\u{0}']), ('\u{3cc}', ['\u{38c}', '\u{0}', '\u{0}']), + ('\u{3cd}', ['\u{38e}', '\u{0}', '\u{0}']), ('\u{3ce}', ['\u{38f}', '\u{0}', '\u{0}']), + ('\u{3d0}', ['\u{392}', '\u{0}', '\u{0}']), ('\u{3d1}', ['\u{398}', '\u{0}', '\u{0}']), + ('\u{3d5}', ['\u{3a6}', '\u{0}', '\u{0}']), ('\u{3d6}', ['\u{3a0}', '\u{0}', '\u{0}']), + ('\u{3d7}', ['\u{3cf}', '\u{0}', '\u{0}']), ('\u{3d9}', ['\u{3d8}', '\u{0}', '\u{0}']), + ('\u{3db}', ['\u{3da}', '\u{0}', '\u{0}']), ('\u{3dd}', ['\u{3dc}', '\u{0}', '\u{0}']), + ('\u{3df}', ['\u{3de}', '\u{0}', '\u{0}']), ('\u{3e1}', ['\u{3e0}', '\u{0}', '\u{0}']), + ('\u{3e3}', ['\u{3e2}', '\u{0}', '\u{0}']), ('\u{3e5}', ['\u{3e4}', '\u{0}', '\u{0}']), + ('\u{3e7}', ['\u{3e6}', '\u{0}', '\u{0}']), ('\u{3e9}', ['\u{3e8}', '\u{0}', '\u{0}']), + ('\u{3eb}', ['\u{3ea}', '\u{0}', '\u{0}']), ('\u{3ed}', ['\u{3ec}', '\u{0}', '\u{0}']), + ('\u{3ef}', ['\u{3ee}', '\u{0}', '\u{0}']), ('\u{3f0}', ['\u{39a}', '\u{0}', '\u{0}']), + ('\u{3f1}', ['\u{3a1}', '\u{0}', '\u{0}']), ('\u{3f2}', ['\u{3f9}', '\u{0}', '\u{0}']), + ('\u{3f3}', ['\u{37f}', '\u{0}', '\u{0}']), ('\u{3f5}', ['\u{395}', '\u{0}', '\u{0}']), + ('\u{3f8}', ['\u{3f7}', '\u{0}', '\u{0}']), ('\u{3fb}', ['\u{3fa}', '\u{0}', '\u{0}']), + ('\u{430}', ['\u{410}', '\u{0}', '\u{0}']), ('\u{431}', ['\u{411}', '\u{0}', '\u{0}']), + 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'\u{0}']), ('\u{10f2}', ['\u{1cb2}', '\u{0}', '\u{0}']), + ('\u{10f3}', ['\u{1cb3}', '\u{0}', '\u{0}']), ('\u{10f4}', ['\u{1cb4}', '\u{0}', '\u{0}']), + ('\u{10f5}', ['\u{1cb5}', '\u{0}', '\u{0}']), ('\u{10f6}', ['\u{1cb6}', '\u{0}', '\u{0}']), + ('\u{10f7}', ['\u{1cb7}', '\u{0}', '\u{0}']), ('\u{10f8}', ['\u{1cb8}', '\u{0}', '\u{0}']), + ('\u{10f9}', ['\u{1cb9}', '\u{0}', '\u{0}']), ('\u{10fa}', ['\u{1cba}', '\u{0}', '\u{0}']), + ('\u{10fd}', ['\u{1cbd}', '\u{0}', '\u{0}']), ('\u{10fe}', ['\u{1cbe}', '\u{0}', '\u{0}']), + ('\u{10ff}', ['\u{1cbf}', '\u{0}', '\u{0}']), ('\u{13f8}', ['\u{13f0}', '\u{0}', '\u{0}']), + ('\u{13f9}', ['\u{13f1}', '\u{0}', '\u{0}']), ('\u{13fa}', ['\u{13f2}', '\u{0}', '\u{0}']), + ('\u{13fb}', ['\u{13f3}', '\u{0}', '\u{0}']), ('\u{13fc}', ['\u{13f4}', '\u{0}', '\u{0}']), + ('\u{13fd}', ['\u{13f5}', '\u{0}', '\u{0}']), ('\u{1c80}', ['\u{412}', '\u{0}', '\u{0}']), + ('\u{1c81}', ['\u{414}', '\u{0}', '\u{0}']), ('\u{1c82}', ['\u{41e}', '\u{0}', '\u{0}']), + ('\u{1c83}', ['\u{421}', '\u{0}', '\u{0}']), ('\u{1c84}', ['\u{422}', '\u{0}', '\u{0}']), + ('\u{1c85}', ['\u{422}', '\u{0}', '\u{0}']), ('\u{1c86}', ['\u{42a}', '\u{0}', '\u{0}']), + ('\u{1c87}', ['\u{462}', '\u{0}', '\u{0}']), ('\u{1c88}', ['\u{a64a}', '\u{0}', '\u{0}']), + ('\u{1c8a}', ['\u{1c89}', '\u{0}', '\u{0}']), ('\u{1d79}', ['\u{a77d}', '\u{0}', '\u{0}']), + ('\u{1d7d}', ['\u{2c63}', '\u{0}', '\u{0}']), ('\u{1d8e}', ['\u{a7c6}', '\u{0}', '\u{0}']), + ('\u{1e01}', ['\u{1e00}', '\u{0}', '\u{0}']), ('\u{1e03}', ['\u{1e02}', '\u{0}', '\u{0}']), + ('\u{1e05}', ['\u{1e04}', '\u{0}', '\u{0}']), ('\u{1e07}', ['\u{1e06}', '\u{0}', '\u{0}']), + ('\u{1e09}', ['\u{1e08}', '\u{0}', '\u{0}']), ('\u{1e0b}', ['\u{1e0a}', '\u{0}', '\u{0}']), + ('\u{1e0d}', ['\u{1e0c}', '\u{0}', '\u{0}']), ('\u{1e0f}', ['\u{1e0e}', '\u{0}', '\u{0}']), + ('\u{1e11}', ['\u{1e10}', '\u{0}', '\u{0}']), ('\u{1e13}', ['\u{1e12}', '\u{0}', '\u{0}']), + ('\u{1e15}', ['\u{1e14}', '\u{0}', '\u{0}']), ('\u{1e17}', ['\u{1e16}', '\u{0}', '\u{0}']), + ('\u{1e19}', ['\u{1e18}', '\u{0}', '\u{0}']), ('\u{1e1b}', ['\u{1e1a}', '\u{0}', '\u{0}']), + ('\u{1e1d}', ['\u{1e1c}', '\u{0}', '\u{0}']), ('\u{1e1f}', ['\u{1e1e}', '\u{0}', '\u{0}']), + ('\u{1e21}', ['\u{1e20}', '\u{0}', '\u{0}']), ('\u{1e23}', ['\u{1e22}', '\u{0}', '\u{0}']), + ('\u{1e25}', ['\u{1e24}', '\u{0}', '\u{0}']), ('\u{1e27}', ['\u{1e26}', '\u{0}', '\u{0}']), + ('\u{1e29}', ['\u{1e28}', '\u{0}', '\u{0}']), ('\u{1e2b}', ['\u{1e2a}', '\u{0}', '\u{0}']), + ('\u{1e2d}', ['\u{1e2c}', '\u{0}', '\u{0}']), ('\u{1e2f}', ['\u{1e2e}', '\u{0}', '\u{0}']), + ('\u{1e31}', ['\u{1e30}', '\u{0}', '\u{0}']), ('\u{1e33}', ['\u{1e32}', '\u{0}', '\u{0}']), + ('\u{1e35}', ['\u{1e34}', '\u{0}', '\u{0}']), ('\u{1e37}', ['\u{1e36}', '\u{0}', '\u{0}']), + ('\u{1e39}', ['\u{1e38}', '\u{0}', '\u{0}']), ('\u{1e3b}', ['\u{1e3a}', '\u{0}', '\u{0}']), + ('\u{1e3d}', ['\u{1e3c}', '\u{0}', '\u{0}']), ('\u{1e3f}', ['\u{1e3e}', '\u{0}', '\u{0}']), + ('\u{1e41}', ['\u{1e40}', '\u{0}', '\u{0}']), ('\u{1e43}', ['\u{1e42}', '\u{0}', '\u{0}']), + ('\u{1e45}', ['\u{1e44}', '\u{0}', '\u{0}']), ('\u{1e47}', ['\u{1e46}', '\u{0}', '\u{0}']), + ('\u{1e49}', ['\u{1e48}', '\u{0}', '\u{0}']), ('\u{1e4b}', ['\u{1e4a}', '\u{0}', '\u{0}']), + ('\u{1e4d}', ['\u{1e4c}', '\u{0}', '\u{0}']), ('\u{1e4f}', ['\u{1e4e}', '\u{0}', '\u{0}']), + ('\u{1e51}', ['\u{1e50}', '\u{0}', '\u{0}']), ('\u{1e53}', ['\u{1e52}', '\u{0}', '\u{0}']), + ('\u{1e55}', ['\u{1e54}', '\u{0}', '\u{0}']), ('\u{1e57}', ['\u{1e56}', '\u{0}', '\u{0}']), + ('\u{1e59}', ['\u{1e58}', '\u{0}', '\u{0}']), ('\u{1e5b}', ['\u{1e5a}', '\u{0}', '\u{0}']), + ('\u{1e5d}', ['\u{1e5c}', '\u{0}', '\u{0}']), ('\u{1e5f}', ['\u{1e5e}', '\u{0}', '\u{0}']), + ('\u{1e61}', ['\u{1e60}', '\u{0}', '\u{0}']), ('\u{1e63}', ['\u{1e62}', '\u{0}', '\u{0}']), + ('\u{1e65}', ['\u{1e64}', '\u{0}', '\u{0}']), ('\u{1e67}', ['\u{1e66}', '\u{0}', '\u{0}']), + ('\u{1e69}', ['\u{1e68}', '\u{0}', '\u{0}']), ('\u{1e6b}', ['\u{1e6a}', '\u{0}', '\u{0}']), + ('\u{1e6d}', ['\u{1e6c}', '\u{0}', '\u{0}']), ('\u{1e6f}', ['\u{1e6e}', '\u{0}', '\u{0}']), + ('\u{1e71}', ['\u{1e70}', '\u{0}', '\u{0}']), ('\u{1e73}', ['\u{1e72}', '\u{0}', '\u{0}']), + ('\u{1e75}', ['\u{1e74}', '\u{0}', '\u{0}']), ('\u{1e77}', ['\u{1e76}', '\u{0}', '\u{0}']), + ('\u{1e79}', ['\u{1e78}', '\u{0}', '\u{0}']), ('\u{1e7b}', ['\u{1e7a}', '\u{0}', '\u{0}']), + ('\u{1e7d}', ['\u{1e7c}', '\u{0}', '\u{0}']), ('\u{1e7f}', ['\u{1e7e}', '\u{0}', '\u{0}']), + ('\u{1e81}', ['\u{1e80}', '\u{0}', '\u{0}']), ('\u{1e83}', ['\u{1e82}', '\u{0}', '\u{0}']), + ('\u{1e85}', ['\u{1e84}', '\u{0}', '\u{0}']), ('\u{1e87}', ['\u{1e86}', '\u{0}', '\u{0}']), + ('\u{1e89}', ['\u{1e88}', '\u{0}', '\u{0}']), ('\u{1e8b}', ['\u{1e8a}', '\u{0}', '\u{0}']), + ('\u{1e8d}', ['\u{1e8c}', '\u{0}', '\u{0}']), ('\u{1e8f}', ['\u{1e8e}', '\u{0}', '\u{0}']), + ('\u{1e91}', ['\u{1e90}', '\u{0}', '\u{0}']), ('\u{1e93}', ['\u{1e92}', '\u{0}', '\u{0}']), + ('\u{1e95}', ['\u{1e94}', '\u{0}', '\u{0}']), ('\u{1e96}', ['H', '\u{331}', '\u{0}']), + ('\u{1e97}', ['T', '\u{308}', '\u{0}']), ('\u{1e98}', ['W', '\u{30a}', '\u{0}']), + ('\u{1e99}', ['Y', '\u{30a}', '\u{0}']), ('\u{1e9a}', ['A', '\u{2be}', '\u{0}']), + ('\u{1e9b}', ['\u{1e60}', '\u{0}', '\u{0}']), ('\u{1ea1}', ['\u{1ea0}', '\u{0}', '\u{0}']), + ('\u{1ea3}', ['\u{1ea2}', '\u{0}', '\u{0}']), ('\u{1ea5}', ['\u{1ea4}', '\u{0}', '\u{0}']), + ('\u{1ea7}', ['\u{1ea6}', '\u{0}', '\u{0}']), ('\u{1ea9}', ['\u{1ea8}', '\u{0}', '\u{0}']), + ('\u{1eab}', ['\u{1eaa}', '\u{0}', '\u{0}']), ('\u{1ead}', ['\u{1eac}', '\u{0}', '\u{0}']), + ('\u{1eaf}', ['\u{1eae}', '\u{0}', '\u{0}']), ('\u{1eb1}', ['\u{1eb0}', '\u{0}', '\u{0}']), + ('\u{1eb3}', ['\u{1eb2}', '\u{0}', '\u{0}']), ('\u{1eb5}', ['\u{1eb4}', '\u{0}', '\u{0}']), + ('\u{1eb7}', ['\u{1eb6}', '\u{0}', '\u{0}']), ('\u{1eb9}', ['\u{1eb8}', '\u{0}', '\u{0}']), + ('\u{1ebb}', ['\u{1eba}', '\u{0}', '\u{0}']), ('\u{1ebd}', ['\u{1ebc}', '\u{0}', '\u{0}']), + ('\u{1ebf}', ['\u{1ebe}', '\u{0}', '\u{0}']), ('\u{1ec1}', ['\u{1ec0}', '\u{0}', '\u{0}']), + ('\u{1ec3}', ['\u{1ec2}', '\u{0}', '\u{0}']), ('\u{1ec5}', ['\u{1ec4}', '\u{0}', '\u{0}']), + ('\u{1ec7}', ['\u{1ec6}', '\u{0}', '\u{0}']), ('\u{1ec9}', ['\u{1ec8}', '\u{0}', '\u{0}']), + ('\u{1ecb}', ['\u{1eca}', '\u{0}', '\u{0}']), ('\u{1ecd}', ['\u{1ecc}', '\u{0}', '\u{0}']), + ('\u{1ecf}', ['\u{1ece}', '\u{0}', '\u{0}']), ('\u{1ed1}', ['\u{1ed0}', '\u{0}', '\u{0}']), + ('\u{1ed3}', ['\u{1ed2}', '\u{0}', '\u{0}']), ('\u{1ed5}', ['\u{1ed4}', '\u{0}', '\u{0}']), + ('\u{1ed7}', ['\u{1ed6}', '\u{0}', '\u{0}']), ('\u{1ed9}', ['\u{1ed8}', '\u{0}', '\u{0}']), + ('\u{1edb}', ['\u{1eda}', '\u{0}', '\u{0}']), ('\u{1edd}', ['\u{1edc}', '\u{0}', '\u{0}']), + ('\u{1edf}', ['\u{1ede}', '\u{0}', '\u{0}']), ('\u{1ee1}', ['\u{1ee0}', '\u{0}', '\u{0}']), + ('\u{1ee3}', ['\u{1ee2}', '\u{0}', '\u{0}']), ('\u{1ee5}', ['\u{1ee4}', '\u{0}', '\u{0}']), + ('\u{1ee7}', ['\u{1ee6}', '\u{0}', '\u{0}']), ('\u{1ee9}', ['\u{1ee8}', '\u{0}', '\u{0}']), + ('\u{1eeb}', ['\u{1eea}', '\u{0}', '\u{0}']), ('\u{1eed}', ['\u{1eec}', '\u{0}', '\u{0}']), + ('\u{1eef}', ['\u{1eee}', '\u{0}', '\u{0}']), ('\u{1ef1}', ['\u{1ef0}', '\u{0}', '\u{0}']), + ('\u{1ef3}', ['\u{1ef2}', '\u{0}', '\u{0}']), ('\u{1ef5}', ['\u{1ef4}', '\u{0}', '\u{0}']), + ('\u{1ef7}', ['\u{1ef6}', '\u{0}', '\u{0}']), ('\u{1ef9}', ['\u{1ef8}', '\u{0}', '\u{0}']), + ('\u{1efb}', ['\u{1efa}', '\u{0}', '\u{0}']), ('\u{1efd}', ['\u{1efc}', '\u{0}', '\u{0}']), + ('\u{1eff}', ['\u{1efe}', '\u{0}', '\u{0}']), ('\u{1f00}', ['\u{1f08}', '\u{0}', '\u{0}']), + ('\u{1f01}', ['\u{1f09}', '\u{0}', '\u{0}']), ('\u{1f02}', ['\u{1f0a}', '\u{0}', '\u{0}']), + ('\u{1f03}', ['\u{1f0b}', '\u{0}', '\u{0}']), ('\u{1f04}', ['\u{1f0c}', '\u{0}', '\u{0}']), + ('\u{1f05}', ['\u{1f0d}', '\u{0}', '\u{0}']), ('\u{1f06}', ['\u{1f0e}', '\u{0}', '\u{0}']), + ('\u{1f07}', ['\u{1f0f}', '\u{0}', '\u{0}']), ('\u{1f10}', ['\u{1f18}', '\u{0}', '\u{0}']), + ('\u{1f11}', ['\u{1f19}', '\u{0}', '\u{0}']), ('\u{1f12}', ['\u{1f1a}', '\u{0}', '\u{0}']), + ('\u{1f13}', ['\u{1f1b}', '\u{0}', '\u{0}']), ('\u{1f14}', ['\u{1f1c}', '\u{0}', '\u{0}']), + ('\u{1f15}', ['\u{1f1d}', '\u{0}', '\u{0}']), ('\u{1f20}', ['\u{1f28}', '\u{0}', '\u{0}']), + ('\u{1f21}', ['\u{1f29}', '\u{0}', '\u{0}']), ('\u{1f22}', ['\u{1f2a}', '\u{0}', '\u{0}']), + ('\u{1f23}', ['\u{1f2b}', '\u{0}', '\u{0}']), ('\u{1f24}', ['\u{1f2c}', '\u{0}', '\u{0}']), + ('\u{1f25}', ['\u{1f2d}', '\u{0}', '\u{0}']), ('\u{1f26}', ['\u{1f2e}', '\u{0}', '\u{0}']), + ('\u{1f27}', ['\u{1f2f}', '\u{0}', '\u{0}']), ('\u{1f30}', ['\u{1f38}', '\u{0}', '\u{0}']), + ('\u{1f31}', ['\u{1f39}', '\u{0}', '\u{0}']), ('\u{1f32}', ['\u{1f3a}', '\u{0}', '\u{0}']), + ('\u{1f33}', ['\u{1f3b}', '\u{0}', '\u{0}']), ('\u{1f34}', ['\u{1f3c}', '\u{0}', '\u{0}']), + ('\u{1f35}', ['\u{1f3d}', '\u{0}', '\u{0}']), ('\u{1f36}', ['\u{1f3e}', '\u{0}', '\u{0}']), + ('\u{1f37}', ['\u{1f3f}', '\u{0}', '\u{0}']), ('\u{1f40}', ['\u{1f48}', '\u{0}', '\u{0}']), + ('\u{1f41}', ['\u{1f49}', '\u{0}', '\u{0}']), ('\u{1f42}', ['\u{1f4a}', '\u{0}', '\u{0}']), + ('\u{1f43}', ['\u{1f4b}', '\u{0}', '\u{0}']), ('\u{1f44}', ['\u{1f4c}', '\u{0}', '\u{0}']), + ('\u{1f45}', ['\u{1f4d}', '\u{0}', '\u{0}']), ('\u{1f50}', ['\u{3a5}', '\u{313}', '\u{0}']), + ('\u{1f51}', ['\u{1f59}', '\u{0}', '\u{0}']), + ('\u{1f52}', ['\u{3a5}', '\u{313}', '\u{300}']), + ('\u{1f53}', ['\u{1f5b}', '\u{0}', '\u{0}']), + ('\u{1f54}', ['\u{3a5}', '\u{313}', '\u{301}']), + ('\u{1f55}', ['\u{1f5d}', '\u{0}', '\u{0}']), + ('\u{1f56}', ['\u{3a5}', '\u{313}', '\u{342}']), + ('\u{1f57}', ['\u{1f5f}', '\u{0}', '\u{0}']), ('\u{1f60}', ['\u{1f68}', '\u{0}', '\u{0}']), + ('\u{1f61}', ['\u{1f69}', '\u{0}', '\u{0}']), ('\u{1f62}', ['\u{1f6a}', '\u{0}', '\u{0}']), + ('\u{1f63}', ['\u{1f6b}', '\u{0}', '\u{0}']), ('\u{1f64}', ['\u{1f6c}', '\u{0}', '\u{0}']), + ('\u{1f65}', ['\u{1f6d}', '\u{0}', '\u{0}']), ('\u{1f66}', ['\u{1f6e}', '\u{0}', '\u{0}']), + ('\u{1f67}', ['\u{1f6f}', '\u{0}', '\u{0}']), ('\u{1f70}', ['\u{1fba}', '\u{0}', '\u{0}']), + ('\u{1f71}', ['\u{1fbb}', '\u{0}', '\u{0}']), ('\u{1f72}', ['\u{1fc8}', '\u{0}', '\u{0}']), + ('\u{1f73}', ['\u{1fc9}', '\u{0}', '\u{0}']), ('\u{1f74}', ['\u{1fca}', '\u{0}', '\u{0}']), + ('\u{1f75}', ['\u{1fcb}', '\u{0}', '\u{0}']), ('\u{1f76}', ['\u{1fda}', '\u{0}', '\u{0}']), + ('\u{1f77}', ['\u{1fdb}', '\u{0}', '\u{0}']), ('\u{1f78}', ['\u{1ff8}', '\u{0}', '\u{0}']), + ('\u{1f79}', ['\u{1ff9}', '\u{0}', '\u{0}']), ('\u{1f7a}', ['\u{1fea}', '\u{0}', '\u{0}']), + ('\u{1f7b}', ['\u{1feb}', '\u{0}', '\u{0}']), ('\u{1f7c}', ['\u{1ffa}', '\u{0}', '\u{0}']), + ('\u{1f7d}', ['\u{1ffb}', '\u{0}', '\u{0}']), + ('\u{1f80}', ['\u{1f08}', '\u{399}', '\u{0}']), + ('\u{1f81}', ['\u{1f09}', '\u{399}', '\u{0}']), + ('\u{1f82}', ['\u{1f0a}', '\u{399}', '\u{0}']), + ('\u{1f83}', ['\u{1f0b}', '\u{399}', '\u{0}']), + ('\u{1f84}', ['\u{1f0c}', '\u{399}', '\u{0}']), + ('\u{1f85}', ['\u{1f0d}', '\u{399}', '\u{0}']), + ('\u{1f86}', ['\u{1f0e}', '\u{399}', '\u{0}']), + ('\u{1f87}', ['\u{1f0f}', '\u{399}', '\u{0}']), + ('\u{1f88}', ['\u{1f08}', '\u{399}', '\u{0}']), + ('\u{1f89}', ['\u{1f09}', '\u{399}', '\u{0}']), + ('\u{1f8a}', ['\u{1f0a}', '\u{399}', '\u{0}']), + ('\u{1f8b}', ['\u{1f0b}', '\u{399}', '\u{0}']), + ('\u{1f8c}', ['\u{1f0c}', '\u{399}', '\u{0}']), + ('\u{1f8d}', ['\u{1f0d}', '\u{399}', '\u{0}']), + ('\u{1f8e}', ['\u{1f0e}', '\u{399}', '\u{0}']), + ('\u{1f8f}', ['\u{1f0f}', '\u{399}', '\u{0}']), + ('\u{1f90}', ['\u{1f28}', '\u{399}', '\u{0}']), + ('\u{1f91}', ['\u{1f29}', '\u{399}', '\u{0}']), + ('\u{1f92}', ['\u{1f2a}', '\u{399}', '\u{0}']), + ('\u{1f93}', ['\u{1f2b}', '\u{399}', '\u{0}']), + ('\u{1f94}', ['\u{1f2c}', '\u{399}', '\u{0}']), + ('\u{1f95}', ['\u{1f2d}', '\u{399}', '\u{0}']), + ('\u{1f96}', ['\u{1f2e}', '\u{399}', '\u{0}']), + ('\u{1f97}', ['\u{1f2f}', '\u{399}', '\u{0}']), + ('\u{1f98}', ['\u{1f28}', '\u{399}', '\u{0}']), + ('\u{1f99}', ['\u{1f29}', '\u{399}', '\u{0}']), + ('\u{1f9a}', ['\u{1f2a}', '\u{399}', '\u{0}']), + ('\u{1f9b}', ['\u{1f2b}', '\u{399}', '\u{0}']), + ('\u{1f9c}', ['\u{1f2c}', '\u{399}', '\u{0}']), + ('\u{1f9d}', ['\u{1f2d}', '\u{399}', '\u{0}']), + ('\u{1f9e}', ['\u{1f2e}', '\u{399}', '\u{0}']), + ('\u{1f9f}', ['\u{1f2f}', '\u{399}', '\u{0}']), + ('\u{1fa0}', ['\u{1f68}', '\u{399}', '\u{0}']), + ('\u{1fa1}', ['\u{1f69}', '\u{399}', '\u{0}']), + ('\u{1fa2}', ['\u{1f6a}', '\u{399}', '\u{0}']), + ('\u{1fa3}', ['\u{1f6b}', '\u{399}', '\u{0}']), + ('\u{1fa4}', ['\u{1f6c}', '\u{399}', '\u{0}']), + ('\u{1fa5}', ['\u{1f6d}', '\u{399}', '\u{0}']), + ('\u{1fa6}', ['\u{1f6e}', '\u{399}', '\u{0}']), + ('\u{1fa7}', ['\u{1f6f}', '\u{399}', '\u{0}']), + ('\u{1fa8}', ['\u{1f68}', '\u{399}', '\u{0}']), + ('\u{1fa9}', ['\u{1f69}', '\u{399}', '\u{0}']), + ('\u{1faa}', ['\u{1f6a}', '\u{399}', '\u{0}']), + ('\u{1fab}', ['\u{1f6b}', '\u{399}', '\u{0}']), + ('\u{1fac}', ['\u{1f6c}', '\u{399}', '\u{0}']), + ('\u{1fad}', ['\u{1f6d}', '\u{399}', '\u{0}']), + ('\u{1fae}', ['\u{1f6e}', '\u{399}', '\u{0}']), + ('\u{1faf}', ['\u{1f6f}', '\u{399}', '\u{0}']), + ('\u{1fb0}', ['\u{1fb8}', '\u{0}', '\u{0}']), ('\u{1fb1}', ['\u{1fb9}', '\u{0}', '\u{0}']), + ('\u{1fb2}', ['\u{1fba}', '\u{399}', '\u{0}']), + ('\u{1fb3}', ['\u{391}', '\u{399}', '\u{0}']), + ('\u{1fb4}', ['\u{386}', '\u{399}', '\u{0}']), + ('\u{1fb6}', ['\u{391}', '\u{342}', '\u{0}']), + ('\u{1fb7}', ['\u{391}', '\u{342}', '\u{399}']), + ('\u{1fbc}', ['\u{391}', '\u{399}', '\u{0}']), ('\u{1fbe}', ['\u{399}', '\u{0}', '\u{0}']), + ('\u{1fc2}', ['\u{1fca}', '\u{399}', '\u{0}']), + ('\u{1fc3}', ['\u{397}', '\u{399}', '\u{0}']), + ('\u{1fc4}', ['\u{389}', '\u{399}', '\u{0}']), + ('\u{1fc6}', ['\u{397}', '\u{342}', '\u{0}']), + ('\u{1fc7}', ['\u{397}', '\u{342}', '\u{399}']), + ('\u{1fcc}', ['\u{397}', '\u{399}', '\u{0}']), ('\u{1fd0}', ['\u{1fd8}', '\u{0}', '\u{0}']), + ('\u{1fd1}', ['\u{1fd9}', '\u{0}', '\u{0}']), + ('\u{1fd2}', ['\u{399}', '\u{308}', '\u{300}']), + ('\u{1fd3}', ['\u{399}', '\u{308}', '\u{301}']), + ('\u{1fd6}', ['\u{399}', '\u{342}', '\u{0}']), + ('\u{1fd7}', ['\u{399}', '\u{308}', '\u{342}']), + ('\u{1fe0}', ['\u{1fe8}', '\u{0}', '\u{0}']), ('\u{1fe1}', ['\u{1fe9}', '\u{0}', '\u{0}']), + ('\u{1fe2}', ['\u{3a5}', '\u{308}', '\u{300}']), + ('\u{1fe3}', ['\u{3a5}', '\u{308}', '\u{301}']), + ('\u{1fe4}', ['\u{3a1}', '\u{313}', '\u{0}']), ('\u{1fe5}', ['\u{1fec}', '\u{0}', '\u{0}']), + ('\u{1fe6}', ['\u{3a5}', '\u{342}', '\u{0}']), + ('\u{1fe7}', ['\u{3a5}', '\u{308}', '\u{342}']), + ('\u{1ff2}', ['\u{1ffa}', '\u{399}', '\u{0}']), + ('\u{1ff3}', ['\u{3a9}', '\u{399}', '\u{0}']), + ('\u{1ff4}', ['\u{38f}', '\u{399}', '\u{0}']), + ('\u{1ff6}', ['\u{3a9}', '\u{342}', '\u{0}']), + ('\u{1ff7}', ['\u{3a9}', '\u{342}', '\u{399}']), + ('\u{1ffc}', ['\u{3a9}', '\u{399}', '\u{0}']), ('\u{214e}', ['\u{2132}', '\u{0}', '\u{0}']), + ('\u{2170}', ['\u{2160}', '\u{0}', '\u{0}']), ('\u{2171}', ['\u{2161}', '\u{0}', '\u{0}']), + ('\u{2172}', ['\u{2162}', '\u{0}', '\u{0}']), ('\u{2173}', ['\u{2163}', '\u{0}', '\u{0}']), + ('\u{2174}', ['\u{2164}', '\u{0}', '\u{0}']), ('\u{2175}', ['\u{2165}', '\u{0}', '\u{0}']), + ('\u{2176}', ['\u{2166}', '\u{0}', '\u{0}']), ('\u{2177}', ['\u{2167}', '\u{0}', '\u{0}']), + ('\u{2178}', ['\u{2168}', '\u{0}', '\u{0}']), ('\u{2179}', ['\u{2169}', '\u{0}', '\u{0}']), + ('\u{217a}', ['\u{216a}', '\u{0}', '\u{0}']), ('\u{217b}', ['\u{216b}', '\u{0}', '\u{0}']), + ('\u{217c}', ['\u{216c}', '\u{0}', '\u{0}']), ('\u{217d}', ['\u{216d}', '\u{0}', '\u{0}']), + ('\u{217e}', ['\u{216e}', '\u{0}', '\u{0}']), ('\u{217f}', ['\u{216f}', '\u{0}', '\u{0}']), + ('\u{2184}', ['\u{2183}', '\u{0}', '\u{0}']), ('\u{24d0}', ['\u{24b6}', '\u{0}', '\u{0}']), + ('\u{24d1}', ['\u{24b7}', '\u{0}', '\u{0}']), ('\u{24d2}', ['\u{24b8}', '\u{0}', '\u{0}']), + ('\u{24d3}', ['\u{24b9}', '\u{0}', '\u{0}']), ('\u{24d4}', ['\u{24ba}', '\u{0}', '\u{0}']), + ('\u{24d5}', ['\u{24bb}', '\u{0}', '\u{0}']), ('\u{24d6}', ['\u{24bc}', '\u{0}', '\u{0}']), + ('\u{24d7}', ['\u{24bd}', '\u{0}', '\u{0}']), ('\u{24d8}', ['\u{24be}', '\u{0}', '\u{0}']), + ('\u{24d9}', ['\u{24bf}', '\u{0}', '\u{0}']), ('\u{24da}', ['\u{24c0}', '\u{0}', '\u{0}']), + ('\u{24db}', ['\u{24c1}', '\u{0}', '\u{0}']), ('\u{24dc}', ['\u{24c2}', '\u{0}', '\u{0}']), + ('\u{24dd}', ['\u{24c3}', '\u{0}', '\u{0}']), ('\u{24de}', ['\u{24c4}', '\u{0}', '\u{0}']), + ('\u{24df}', ['\u{24c5}', '\u{0}', '\u{0}']), ('\u{24e0}', ['\u{24c6}', '\u{0}', '\u{0}']), + ('\u{24e1}', ['\u{24c7}', '\u{0}', '\u{0}']), ('\u{24e2}', ['\u{24c8}', '\u{0}', '\u{0}']), + ('\u{24e3}', ['\u{24c9}', '\u{0}', '\u{0}']), ('\u{24e4}', ['\u{24ca}', '\u{0}', '\u{0}']), + ('\u{24e5}', ['\u{24cb}', '\u{0}', '\u{0}']), ('\u{24e6}', ['\u{24cc}', '\u{0}', '\u{0}']), + ('\u{24e7}', ['\u{24cd}', '\u{0}', '\u{0}']), ('\u{24e8}', ['\u{24ce}', '\u{0}', '\u{0}']), + ('\u{24e9}', ['\u{24cf}', '\u{0}', '\u{0}']), ('\u{2c30}', ['\u{2c00}', '\u{0}', '\u{0}']), + ('\u{2c31}', ['\u{2c01}', '\u{0}', '\u{0}']), ('\u{2c32}', ['\u{2c02}', '\u{0}', '\u{0}']), + ('\u{2c33}', ['\u{2c03}', '\u{0}', '\u{0}']), ('\u{2c34}', ['\u{2c04}', '\u{0}', '\u{0}']), + ('\u{2c35}', ['\u{2c05}', '\u{0}', '\u{0}']), ('\u{2c36}', ['\u{2c06}', '\u{0}', '\u{0}']), + ('\u{2c37}', ['\u{2c07}', '\u{0}', '\u{0}']), ('\u{2c38}', ['\u{2c08}', '\u{0}', '\u{0}']), + ('\u{2c39}', ['\u{2c09}', '\u{0}', '\u{0}']), ('\u{2c3a}', ['\u{2c0a}', '\u{0}', '\u{0}']), + ('\u{2c3b}', ['\u{2c0b}', '\u{0}', '\u{0}']), ('\u{2c3c}', ['\u{2c0c}', '\u{0}', '\u{0}']), + ('\u{2c3d}', ['\u{2c0d}', '\u{0}', '\u{0}']), ('\u{2c3e}', ['\u{2c0e}', '\u{0}', '\u{0}']), + ('\u{2c3f}', ['\u{2c0f}', '\u{0}', '\u{0}']), ('\u{2c40}', ['\u{2c10}', '\u{0}', '\u{0}']), + ('\u{2c41}', ['\u{2c11}', '\u{0}', '\u{0}']), ('\u{2c42}', ['\u{2c12}', '\u{0}', '\u{0}']), + ('\u{2c43}', ['\u{2c13}', '\u{0}', '\u{0}']), ('\u{2c44}', ['\u{2c14}', '\u{0}', '\u{0}']), + ('\u{2c45}', ['\u{2c15}', '\u{0}', '\u{0}']), ('\u{2c46}', ['\u{2c16}', '\u{0}', '\u{0}']), + ('\u{2c47}', ['\u{2c17}', '\u{0}', '\u{0}']), ('\u{2c48}', ['\u{2c18}', '\u{0}', '\u{0}']), + ('\u{2c49}', ['\u{2c19}', '\u{0}', '\u{0}']), ('\u{2c4a}', ['\u{2c1a}', '\u{0}', '\u{0}']), + ('\u{2c4b}', ['\u{2c1b}', '\u{0}', '\u{0}']), ('\u{2c4c}', ['\u{2c1c}', '\u{0}', '\u{0}']), + ('\u{2c4d}', ['\u{2c1d}', '\u{0}', '\u{0}']), ('\u{2c4e}', ['\u{2c1e}', '\u{0}', '\u{0}']), + ('\u{2c4f}', ['\u{2c1f}', '\u{0}', '\u{0}']), ('\u{2c50}', ['\u{2c20}', '\u{0}', '\u{0}']), + ('\u{2c51}', ['\u{2c21}', '\u{0}', '\u{0}']), ('\u{2c52}', ['\u{2c22}', '\u{0}', '\u{0}']), + ('\u{2c53}', ['\u{2c23}', '\u{0}', '\u{0}']), ('\u{2c54}', ['\u{2c24}', '\u{0}', '\u{0}']), + ('\u{2c55}', ['\u{2c25}', '\u{0}', '\u{0}']), ('\u{2c56}', ['\u{2c26}', '\u{0}', '\u{0}']), + ('\u{2c57}', ['\u{2c27}', '\u{0}', '\u{0}']), ('\u{2c58}', ['\u{2c28}', '\u{0}', '\u{0}']), + ('\u{2c59}', ['\u{2c29}', '\u{0}', '\u{0}']), ('\u{2c5a}', ['\u{2c2a}', '\u{0}', '\u{0}']), + ('\u{2c5b}', ['\u{2c2b}', '\u{0}', '\u{0}']), ('\u{2c5c}', ['\u{2c2c}', '\u{0}', '\u{0}']), + ('\u{2c5d}', ['\u{2c2d}', '\u{0}', '\u{0}']), ('\u{2c5e}', ['\u{2c2e}', '\u{0}', '\u{0}']), + ('\u{2c5f}', ['\u{2c2f}', '\u{0}', '\u{0}']), ('\u{2c61}', ['\u{2c60}', '\u{0}', '\u{0}']), + ('\u{2c65}', ['\u{23a}', '\u{0}', '\u{0}']), ('\u{2c66}', ['\u{23e}', '\u{0}', '\u{0}']), + ('\u{2c68}', ['\u{2c67}', '\u{0}', '\u{0}']), ('\u{2c6a}', ['\u{2c69}', '\u{0}', '\u{0}']), + ('\u{2c6c}', ['\u{2c6b}', '\u{0}', '\u{0}']), ('\u{2c73}', ['\u{2c72}', '\u{0}', '\u{0}']), + ('\u{2c76}', ['\u{2c75}', '\u{0}', '\u{0}']), ('\u{2c81}', ['\u{2c80}', '\u{0}', '\u{0}']), + ('\u{2c83}', ['\u{2c82}', '\u{0}', '\u{0}']), ('\u{2c85}', ['\u{2c84}', '\u{0}', '\u{0}']), + ('\u{2c87}', ['\u{2c86}', '\u{0}', '\u{0}']), ('\u{2c89}', ['\u{2c88}', '\u{0}', '\u{0}']), + ('\u{2c8b}', ['\u{2c8a}', '\u{0}', '\u{0}']), ('\u{2c8d}', ['\u{2c8c}', '\u{0}', '\u{0}']), + ('\u{2c8f}', ['\u{2c8e}', '\u{0}', '\u{0}']), ('\u{2c91}', ['\u{2c90}', '\u{0}', '\u{0}']), + ('\u{2c93}', ['\u{2c92}', '\u{0}', '\u{0}']), ('\u{2c95}', ['\u{2c94}', '\u{0}', '\u{0}']), + ('\u{2c97}', ['\u{2c96}', '\u{0}', '\u{0}']), ('\u{2c99}', ['\u{2c98}', '\u{0}', '\u{0}']), + ('\u{2c9b}', ['\u{2c9a}', '\u{0}', '\u{0}']), ('\u{2c9d}', ['\u{2c9c}', '\u{0}', '\u{0}']), + ('\u{2c9f}', ['\u{2c9e}', '\u{0}', '\u{0}']), ('\u{2ca1}', ['\u{2ca0}', '\u{0}', '\u{0}']), + ('\u{2ca3}', ['\u{2ca2}', '\u{0}', '\u{0}']), ('\u{2ca5}', ['\u{2ca4}', '\u{0}', '\u{0}']), + ('\u{2ca7}', ['\u{2ca6}', '\u{0}', '\u{0}']), ('\u{2ca9}', ['\u{2ca8}', '\u{0}', '\u{0}']), + ('\u{2cab}', ['\u{2caa}', '\u{0}', '\u{0}']), ('\u{2cad}', ['\u{2cac}', '\u{0}', '\u{0}']), + ('\u{2caf}', ['\u{2cae}', '\u{0}', '\u{0}']), ('\u{2cb1}', ['\u{2cb0}', '\u{0}', '\u{0}']), + ('\u{2cb3}', ['\u{2cb2}', '\u{0}', '\u{0}']), ('\u{2cb5}', ['\u{2cb4}', '\u{0}', '\u{0}']), + ('\u{2cb7}', ['\u{2cb6}', '\u{0}', '\u{0}']), ('\u{2cb9}', ['\u{2cb8}', '\u{0}', '\u{0}']), + ('\u{2cbb}', ['\u{2cba}', '\u{0}', '\u{0}']), ('\u{2cbd}', ['\u{2cbc}', '\u{0}', '\u{0}']), + ('\u{2cbf}', ['\u{2cbe}', '\u{0}', '\u{0}']), ('\u{2cc1}', ['\u{2cc0}', '\u{0}', '\u{0}']), + ('\u{2cc3}', ['\u{2cc2}', '\u{0}', '\u{0}']), ('\u{2cc5}', ['\u{2cc4}', '\u{0}', '\u{0}']), + ('\u{2cc7}', ['\u{2cc6}', '\u{0}', '\u{0}']), ('\u{2cc9}', ['\u{2cc8}', '\u{0}', '\u{0}']), + ('\u{2ccb}', ['\u{2cca}', '\u{0}', '\u{0}']), ('\u{2ccd}', ['\u{2ccc}', '\u{0}', '\u{0}']), + ('\u{2ccf}', ['\u{2cce}', '\u{0}', '\u{0}']), ('\u{2cd1}', ['\u{2cd0}', '\u{0}', '\u{0}']), + ('\u{2cd3}', ['\u{2cd2}', '\u{0}', '\u{0}']), ('\u{2cd5}', ['\u{2cd4}', '\u{0}', '\u{0}']), + ('\u{2cd7}', ['\u{2cd6}', '\u{0}', '\u{0}']), ('\u{2cd9}', ['\u{2cd8}', '\u{0}', '\u{0}']), + ('\u{2cdb}', ['\u{2cda}', '\u{0}', '\u{0}']), ('\u{2cdd}', ['\u{2cdc}', '\u{0}', '\u{0}']), + ('\u{2cdf}', ['\u{2cde}', '\u{0}', '\u{0}']), ('\u{2ce1}', ['\u{2ce0}', '\u{0}', '\u{0}']), + ('\u{2ce3}', ['\u{2ce2}', '\u{0}', '\u{0}']), ('\u{2cec}', ['\u{2ceb}', '\u{0}', '\u{0}']), + ('\u{2cee}', ['\u{2ced}', '\u{0}', '\u{0}']), ('\u{2cf3}', ['\u{2cf2}', '\u{0}', '\u{0}']), + ('\u{2d00}', ['\u{10a0}', '\u{0}', '\u{0}']), ('\u{2d01}', ['\u{10a1}', '\u{0}', '\u{0}']), + ('\u{2d02}', ['\u{10a2}', '\u{0}', '\u{0}']), ('\u{2d03}', ['\u{10a3}', '\u{0}', '\u{0}']), + ('\u{2d04}', ['\u{10a4}', '\u{0}', '\u{0}']), ('\u{2d05}', ['\u{10a5}', '\u{0}', '\u{0}']), + ('\u{2d06}', ['\u{10a6}', '\u{0}', '\u{0}']), ('\u{2d07}', ['\u{10a7}', '\u{0}', '\u{0}']), + ('\u{2d08}', ['\u{10a8}', '\u{0}', '\u{0}']), ('\u{2d09}', ['\u{10a9}', '\u{0}', '\u{0}']), + ('\u{2d0a}', ['\u{10aa}', '\u{0}', '\u{0}']), ('\u{2d0b}', ['\u{10ab}', '\u{0}', '\u{0}']), + ('\u{2d0c}', ['\u{10ac}', '\u{0}', '\u{0}']), ('\u{2d0d}', ['\u{10ad}', '\u{0}', '\u{0}']), + ('\u{2d0e}', ['\u{10ae}', '\u{0}', '\u{0}']), ('\u{2d0f}', ['\u{10af}', '\u{0}', '\u{0}']), + ('\u{2d10}', ['\u{10b0}', '\u{0}', '\u{0}']), ('\u{2d11}', ['\u{10b1}', '\u{0}', '\u{0}']), + ('\u{2d12}', ['\u{10b2}', '\u{0}', '\u{0}']), ('\u{2d13}', ['\u{10b3}', '\u{0}', '\u{0}']), + ('\u{2d14}', ['\u{10b4}', '\u{0}', '\u{0}']), ('\u{2d15}', ['\u{10b5}', '\u{0}', '\u{0}']), + ('\u{2d16}', ['\u{10b6}', '\u{0}', '\u{0}']), ('\u{2d17}', ['\u{10b7}', '\u{0}', '\u{0}']), + ('\u{2d18}', ['\u{10b8}', '\u{0}', '\u{0}']), ('\u{2d19}', ['\u{10b9}', '\u{0}', '\u{0}']), + ('\u{2d1a}', ['\u{10ba}', '\u{0}', '\u{0}']), ('\u{2d1b}', ['\u{10bb}', '\u{0}', '\u{0}']), + ('\u{2d1c}', ['\u{10bc}', '\u{0}', '\u{0}']), ('\u{2d1d}', ['\u{10bd}', '\u{0}', '\u{0}']), + ('\u{2d1e}', ['\u{10be}', '\u{0}', '\u{0}']), ('\u{2d1f}', ['\u{10bf}', '\u{0}', '\u{0}']), + ('\u{2d20}', ['\u{10c0}', '\u{0}', '\u{0}']), ('\u{2d21}', ['\u{10c1}', '\u{0}', '\u{0}']), + ('\u{2d22}', ['\u{10c2}', '\u{0}', '\u{0}']), ('\u{2d23}', ['\u{10c3}', '\u{0}', '\u{0}']), + ('\u{2d24}', ['\u{10c4}', '\u{0}', '\u{0}']), ('\u{2d25}', ['\u{10c5}', '\u{0}', '\u{0}']), + ('\u{2d27}', ['\u{10c7}', '\u{0}', '\u{0}']), ('\u{2d2d}', ['\u{10cd}', '\u{0}', '\u{0}']), + ('\u{a641}', ['\u{a640}', '\u{0}', '\u{0}']), ('\u{a643}', ['\u{a642}', '\u{0}', '\u{0}']), + ('\u{a645}', ['\u{a644}', '\u{0}', '\u{0}']), ('\u{a647}', ['\u{a646}', '\u{0}', '\u{0}']), + ('\u{a649}', ['\u{a648}', '\u{0}', '\u{0}']), ('\u{a64b}', ['\u{a64a}', '\u{0}', '\u{0}']), + ('\u{a64d}', ['\u{a64c}', '\u{0}', '\u{0}']), ('\u{a64f}', ['\u{a64e}', '\u{0}', '\u{0}']), + ('\u{a651}', ['\u{a650}', '\u{0}', '\u{0}']), ('\u{a653}', ['\u{a652}', '\u{0}', '\u{0}']), + ('\u{a655}', ['\u{a654}', '\u{0}', '\u{0}']), ('\u{a657}', ['\u{a656}', '\u{0}', '\u{0}']), + ('\u{a659}', ['\u{a658}', '\u{0}', '\u{0}']), ('\u{a65b}', ['\u{a65a}', '\u{0}', '\u{0}']), + ('\u{a65d}', ['\u{a65c}', '\u{0}', '\u{0}']), ('\u{a65f}', ['\u{a65e}', '\u{0}', '\u{0}']), + ('\u{a661}', ['\u{a660}', '\u{0}', '\u{0}']), ('\u{a663}', ['\u{a662}', '\u{0}', '\u{0}']), + ('\u{a665}', ['\u{a664}', '\u{0}', '\u{0}']), ('\u{a667}', ['\u{a666}', '\u{0}', '\u{0}']), + ('\u{a669}', ['\u{a668}', '\u{0}', '\u{0}']), ('\u{a66b}', ['\u{a66a}', '\u{0}', '\u{0}']), + ('\u{a66d}', ['\u{a66c}', '\u{0}', '\u{0}']), ('\u{a681}', ['\u{a680}', '\u{0}', '\u{0}']), + ('\u{a683}', ['\u{a682}', '\u{0}', '\u{0}']), ('\u{a685}', ['\u{a684}', '\u{0}', '\u{0}']), + ('\u{a687}', ['\u{a686}', '\u{0}', '\u{0}']), ('\u{a689}', ['\u{a688}', '\u{0}', '\u{0}']), + ('\u{a68b}', ['\u{a68a}', '\u{0}', '\u{0}']), ('\u{a68d}', ['\u{a68c}', '\u{0}', '\u{0}']), + ('\u{a68f}', ['\u{a68e}', '\u{0}', '\u{0}']), ('\u{a691}', ['\u{a690}', '\u{0}', '\u{0}']), + ('\u{a693}', ['\u{a692}', '\u{0}', '\u{0}']), ('\u{a695}', ['\u{a694}', '\u{0}', '\u{0}']), + ('\u{a697}', ['\u{a696}', '\u{0}', '\u{0}']), ('\u{a699}', ['\u{a698}', '\u{0}', '\u{0}']), + ('\u{a69b}', ['\u{a69a}', '\u{0}', '\u{0}']), ('\u{a723}', ['\u{a722}', '\u{0}', '\u{0}']), + ('\u{a725}', ['\u{a724}', '\u{0}', '\u{0}']), ('\u{a727}', ['\u{a726}', '\u{0}', '\u{0}']), + ('\u{a729}', ['\u{a728}', '\u{0}', '\u{0}']), ('\u{a72b}', ['\u{a72a}', '\u{0}', '\u{0}']), + ('\u{a72d}', ['\u{a72c}', '\u{0}', '\u{0}']), ('\u{a72f}', ['\u{a72e}', '\u{0}', '\u{0}']), + ('\u{a733}', ['\u{a732}', '\u{0}', '\u{0}']), ('\u{a735}', ['\u{a734}', '\u{0}', '\u{0}']), + ('\u{a737}', ['\u{a736}', '\u{0}', '\u{0}']), ('\u{a739}', ['\u{a738}', '\u{0}', '\u{0}']), + ('\u{a73b}', ['\u{a73a}', '\u{0}', '\u{0}']), ('\u{a73d}', ['\u{a73c}', '\u{0}', '\u{0}']), + ('\u{a73f}', ['\u{a73e}', '\u{0}', '\u{0}']), ('\u{a741}', ['\u{a740}', '\u{0}', '\u{0}']), + ('\u{a743}', ['\u{a742}', '\u{0}', '\u{0}']), ('\u{a745}', ['\u{a744}', '\u{0}', '\u{0}']), + ('\u{a747}', ['\u{a746}', '\u{0}', '\u{0}']), ('\u{a749}', ['\u{a748}', '\u{0}', '\u{0}']), + ('\u{a74b}', ['\u{a74a}', '\u{0}', '\u{0}']), ('\u{a74d}', ['\u{a74c}', '\u{0}', '\u{0}']), + ('\u{a74f}', ['\u{a74e}', '\u{0}', '\u{0}']), ('\u{a751}', ['\u{a750}', '\u{0}', '\u{0}']), + ('\u{a753}', ['\u{a752}', '\u{0}', '\u{0}']), ('\u{a755}', ['\u{a754}', '\u{0}', '\u{0}']), + ('\u{a757}', ['\u{a756}', '\u{0}', '\u{0}']), ('\u{a759}', ['\u{a758}', '\u{0}', '\u{0}']), + ('\u{a75b}', ['\u{a75a}', '\u{0}', '\u{0}']), ('\u{a75d}', ['\u{a75c}', '\u{0}', '\u{0}']), + ('\u{a75f}', ['\u{a75e}', '\u{0}', '\u{0}']), ('\u{a761}', ['\u{a760}', '\u{0}', '\u{0}']), + ('\u{a763}', ['\u{a762}', '\u{0}', '\u{0}']), ('\u{a765}', ['\u{a764}', '\u{0}', '\u{0}']), + ('\u{a767}', ['\u{a766}', '\u{0}', '\u{0}']), ('\u{a769}', ['\u{a768}', '\u{0}', '\u{0}']), + ('\u{a76b}', ['\u{a76a}', '\u{0}', '\u{0}']), ('\u{a76d}', ['\u{a76c}', '\u{0}', '\u{0}']), + ('\u{a76f}', ['\u{a76e}', '\u{0}', '\u{0}']), ('\u{a77a}', ['\u{a779}', '\u{0}', '\u{0}']), + ('\u{a77c}', ['\u{a77b}', '\u{0}', '\u{0}']), ('\u{a77f}', ['\u{a77e}', '\u{0}', '\u{0}']), + ('\u{a781}', ['\u{a780}', '\u{0}', '\u{0}']), ('\u{a783}', ['\u{a782}', '\u{0}', '\u{0}']), + ('\u{a785}', ['\u{a784}', '\u{0}', '\u{0}']), ('\u{a787}', ['\u{a786}', '\u{0}', '\u{0}']), + ('\u{a78c}', ['\u{a78b}', '\u{0}', '\u{0}']), ('\u{a791}', ['\u{a790}', '\u{0}', '\u{0}']), + ('\u{a793}', ['\u{a792}', '\u{0}', '\u{0}']), ('\u{a794}', ['\u{a7c4}', '\u{0}', '\u{0}']), + ('\u{a797}', ['\u{a796}', '\u{0}', '\u{0}']), ('\u{a799}', ['\u{a798}', '\u{0}', '\u{0}']), + ('\u{a79b}', ['\u{a79a}', '\u{0}', '\u{0}']), ('\u{a79d}', ['\u{a79c}', '\u{0}', '\u{0}']), + ('\u{a79f}', ['\u{a79e}', '\u{0}', '\u{0}']), ('\u{a7a1}', ['\u{a7a0}', '\u{0}', '\u{0}']), + ('\u{a7a3}', ['\u{a7a2}', '\u{0}', '\u{0}']), ('\u{a7a5}', ['\u{a7a4}', '\u{0}', '\u{0}']), + ('\u{a7a7}', ['\u{a7a6}', '\u{0}', '\u{0}']), ('\u{a7a9}', ['\u{a7a8}', '\u{0}', '\u{0}']), + ('\u{a7b5}', ['\u{a7b4}', '\u{0}', '\u{0}']), ('\u{a7b7}', ['\u{a7b6}', '\u{0}', '\u{0}']), + ('\u{a7b9}', ['\u{a7b8}', '\u{0}', '\u{0}']), ('\u{a7bb}', ['\u{a7ba}', '\u{0}', '\u{0}']), + ('\u{a7bd}', ['\u{a7bc}', '\u{0}', '\u{0}']), ('\u{a7bf}', ['\u{a7be}', '\u{0}', '\u{0}']), + ('\u{a7c1}', ['\u{a7c0}', '\u{0}', '\u{0}']), ('\u{a7c3}', ['\u{a7c2}', '\u{0}', '\u{0}']), + ('\u{a7c8}', ['\u{a7c7}', '\u{0}', '\u{0}']), ('\u{a7ca}', ['\u{a7c9}', '\u{0}', '\u{0}']), + ('\u{a7cd}', ['\u{a7cc}', '\u{0}', '\u{0}']), ('\u{a7cf}', ['\u{a7ce}', '\u{0}', '\u{0}']), + ('\u{a7d1}', ['\u{a7d0}', '\u{0}', '\u{0}']), ('\u{a7d3}', ['\u{a7d2}', '\u{0}', '\u{0}']), + ('\u{a7d5}', ['\u{a7d4}', '\u{0}', '\u{0}']), ('\u{a7d7}', ['\u{a7d6}', '\u{0}', '\u{0}']), + ('\u{a7d9}', ['\u{a7d8}', '\u{0}', '\u{0}']), ('\u{a7db}', ['\u{a7da}', '\u{0}', '\u{0}']), + ('\u{a7f6}', ['\u{a7f5}', '\u{0}', '\u{0}']), ('\u{ab53}', ['\u{a7b3}', '\u{0}', '\u{0}']), + ('\u{ab70}', ['\u{13a0}', '\u{0}', '\u{0}']), ('\u{ab71}', ['\u{13a1}', '\u{0}', '\u{0}']), + ('\u{ab72}', ['\u{13a2}', '\u{0}', '\u{0}']), ('\u{ab73}', ['\u{13a3}', '\u{0}', '\u{0}']), + ('\u{ab74}', ['\u{13a4}', '\u{0}', '\u{0}']), ('\u{ab75}', ['\u{13a5}', '\u{0}', '\u{0}']), + ('\u{ab76}', ['\u{13a6}', '\u{0}', '\u{0}']), ('\u{ab77}', ['\u{13a7}', '\u{0}', '\u{0}']), + ('\u{ab78}', ['\u{13a8}', '\u{0}', '\u{0}']), ('\u{ab79}', ['\u{13a9}', '\u{0}', '\u{0}']), + ('\u{ab7a}', ['\u{13aa}', '\u{0}', '\u{0}']), ('\u{ab7b}', ['\u{13ab}', '\u{0}', '\u{0}']), + ('\u{ab7c}', ['\u{13ac}', '\u{0}', '\u{0}']), ('\u{ab7d}', ['\u{13ad}', '\u{0}', '\u{0}']), + ('\u{ab7e}', ['\u{13ae}', '\u{0}', '\u{0}']), ('\u{ab7f}', ['\u{13af}', '\u{0}', '\u{0}']), + ('\u{ab80}', ['\u{13b0}', '\u{0}', '\u{0}']), ('\u{ab81}', ['\u{13b1}', '\u{0}', '\u{0}']), + ('\u{ab82}', ['\u{13b2}', '\u{0}', '\u{0}']), ('\u{ab83}', ['\u{13b3}', '\u{0}', '\u{0}']), + ('\u{ab84}', ['\u{13b4}', '\u{0}', '\u{0}']), ('\u{ab85}', ['\u{13b5}', '\u{0}', '\u{0}']), + ('\u{ab86}', ['\u{13b6}', '\u{0}', '\u{0}']), ('\u{ab87}', ['\u{13b7}', '\u{0}', '\u{0}']), + ('\u{ab88}', ['\u{13b8}', '\u{0}', '\u{0}']), ('\u{ab89}', ['\u{13b9}', '\u{0}', '\u{0}']), + ('\u{ab8a}', ['\u{13ba}', '\u{0}', '\u{0}']), ('\u{ab8b}', ['\u{13bb}', '\u{0}', '\u{0}']), + ('\u{ab8c}', ['\u{13bc}', '\u{0}', '\u{0}']), ('\u{ab8d}', ['\u{13bd}', '\u{0}', '\u{0}']), + ('\u{ab8e}', ['\u{13be}', '\u{0}', '\u{0}']), ('\u{ab8f}', ['\u{13bf}', '\u{0}', '\u{0}']), + ('\u{ab90}', ['\u{13c0}', '\u{0}', '\u{0}']), ('\u{ab91}', ['\u{13c1}', '\u{0}', '\u{0}']), + ('\u{ab92}', ['\u{13c2}', '\u{0}', '\u{0}']), ('\u{ab93}', ['\u{13c3}', '\u{0}', '\u{0}']), + ('\u{ab94}', ['\u{13c4}', '\u{0}', '\u{0}']), ('\u{ab95}', ['\u{13c5}', '\u{0}', '\u{0}']), + ('\u{ab96}', ['\u{13c6}', '\u{0}', '\u{0}']), ('\u{ab97}', ['\u{13c7}', '\u{0}', '\u{0}']), + ('\u{ab98}', ['\u{13c8}', '\u{0}', '\u{0}']), ('\u{ab99}', ['\u{13c9}', '\u{0}', '\u{0}']), + ('\u{ab9a}', ['\u{13ca}', '\u{0}', '\u{0}']), ('\u{ab9b}', ['\u{13cb}', '\u{0}', '\u{0}']), + ('\u{ab9c}', ['\u{13cc}', '\u{0}', '\u{0}']), ('\u{ab9d}', ['\u{13cd}', '\u{0}', '\u{0}']), + ('\u{ab9e}', ['\u{13ce}', '\u{0}', '\u{0}']), ('\u{ab9f}', ['\u{13cf}', '\u{0}', '\u{0}']), + ('\u{aba0}', ['\u{13d0}', '\u{0}', '\u{0}']), ('\u{aba1}', ['\u{13d1}', '\u{0}', '\u{0}']), + ('\u{aba2}', ['\u{13d2}', '\u{0}', '\u{0}']), ('\u{aba3}', ['\u{13d3}', '\u{0}', '\u{0}']), + ('\u{aba4}', ['\u{13d4}', '\u{0}', '\u{0}']), ('\u{aba5}', ['\u{13d5}', '\u{0}', '\u{0}']), + ('\u{aba6}', ['\u{13d6}', '\u{0}', '\u{0}']), ('\u{aba7}', ['\u{13d7}', '\u{0}', '\u{0}']), + ('\u{aba8}', ['\u{13d8}', '\u{0}', '\u{0}']), ('\u{aba9}', ['\u{13d9}', '\u{0}', '\u{0}']), + ('\u{abaa}', ['\u{13da}', '\u{0}', '\u{0}']), ('\u{abab}', ['\u{13db}', '\u{0}', '\u{0}']), + ('\u{abac}', ['\u{13dc}', '\u{0}', '\u{0}']), ('\u{abad}', ['\u{13dd}', '\u{0}', '\u{0}']), + ('\u{abae}', ['\u{13de}', '\u{0}', '\u{0}']), ('\u{abaf}', ['\u{13df}', '\u{0}', '\u{0}']), + ('\u{abb0}', ['\u{13e0}', '\u{0}', '\u{0}']), ('\u{abb1}', ['\u{13e1}', '\u{0}', '\u{0}']), + ('\u{abb2}', ['\u{13e2}', '\u{0}', '\u{0}']), ('\u{abb3}', ['\u{13e3}', '\u{0}', '\u{0}']), + ('\u{abb4}', ['\u{13e4}', '\u{0}', '\u{0}']), ('\u{abb5}', ['\u{13e5}', '\u{0}', '\u{0}']), + ('\u{abb6}', ['\u{13e6}', '\u{0}', '\u{0}']), ('\u{abb7}', ['\u{13e7}', '\u{0}', '\u{0}']), + ('\u{abb8}', ['\u{13e8}', '\u{0}', '\u{0}']), ('\u{abb9}', ['\u{13e9}', '\u{0}', '\u{0}']), + ('\u{abba}', ['\u{13ea}', '\u{0}', '\u{0}']), ('\u{abbb}', ['\u{13eb}', '\u{0}', '\u{0}']), + ('\u{abbc}', ['\u{13ec}', '\u{0}', '\u{0}']), ('\u{abbd}', ['\u{13ed}', '\u{0}', '\u{0}']), + ('\u{abbe}', ['\u{13ee}', '\u{0}', '\u{0}']), ('\u{abbf}', ['\u{13ef}', '\u{0}', '\u{0}']), + ('\u{fb00}', ['F', 'F', '\u{0}']), ('\u{fb01}', ['F', 'I', '\u{0}']), + ('\u{fb02}', ['F', 'L', '\u{0}']), ('\u{fb03}', ['F', 'F', 'I']), + ('\u{fb04}', ['F', 'F', 'L']), ('\u{fb05}', ['S', 'T', '\u{0}']), + ('\u{fb06}', ['S', 'T', '\u{0}']), ('\u{fb13}', ['\u{544}', '\u{546}', '\u{0}']), + ('\u{fb14}', ['\u{544}', '\u{535}', '\u{0}']), + ('\u{fb15}', ['\u{544}', '\u{53b}', '\u{0}']), + ('\u{fb16}', ['\u{54e}', '\u{546}', '\u{0}']), + ('\u{fb17}', ['\u{544}', '\u{53d}', '\u{0}']), ('\u{ff41}', ['\u{ff21}', '\u{0}', '\u{0}']), + ('\u{ff42}', ['\u{ff22}', '\u{0}', '\u{0}']), ('\u{ff43}', ['\u{ff23}', '\u{0}', '\u{0}']), + ('\u{ff44}', ['\u{ff24}', '\u{0}', '\u{0}']), ('\u{ff45}', ['\u{ff25}', '\u{0}', '\u{0}']), + ('\u{ff46}', ['\u{ff26}', '\u{0}', '\u{0}']), ('\u{ff47}', ['\u{ff27}', '\u{0}', '\u{0}']), + ('\u{ff48}', ['\u{ff28}', '\u{0}', '\u{0}']), ('\u{ff49}', ['\u{ff29}', '\u{0}', '\u{0}']), + ('\u{ff4a}', ['\u{ff2a}', '\u{0}', '\u{0}']), ('\u{ff4b}', ['\u{ff2b}', '\u{0}', '\u{0}']), + ('\u{ff4c}', ['\u{ff2c}', '\u{0}', '\u{0}']), ('\u{ff4d}', ['\u{ff2d}', '\u{0}', '\u{0}']), + ('\u{ff4e}', ['\u{ff2e}', '\u{0}', '\u{0}']), ('\u{ff4f}', ['\u{ff2f}', '\u{0}', '\u{0}']), + ('\u{ff50}', ['\u{ff30}', '\u{0}', '\u{0}']), ('\u{ff51}', ['\u{ff31}', '\u{0}', '\u{0}']), + ('\u{ff52}', ['\u{ff32}', '\u{0}', '\u{0}']), ('\u{ff53}', ['\u{ff33}', '\u{0}', '\u{0}']), + ('\u{ff54}', ['\u{ff34}', '\u{0}', '\u{0}']), ('\u{ff55}', ['\u{ff35}', '\u{0}', '\u{0}']), + ('\u{ff56}', ['\u{ff36}', '\u{0}', '\u{0}']), ('\u{ff57}', ['\u{ff37}', '\u{0}', '\u{0}']), + ('\u{ff58}', ['\u{ff38}', '\u{0}', '\u{0}']), ('\u{ff59}', ['\u{ff39}', '\u{0}', '\u{0}']), + ('\u{ff5a}', ['\u{ff3a}', '\u{0}', '\u{0}']), + ('\u{10428}', ['\u{10400}', '\u{0}', '\u{0}']), + ('\u{10429}', ['\u{10401}', '\u{0}', '\u{0}']), + ('\u{1042a}', ['\u{10402}', '\u{0}', '\u{0}']), + ('\u{1042b}', ['\u{10403}', '\u{0}', '\u{0}']), + ('\u{1042c}', ['\u{10404}', '\u{0}', '\u{0}']), + ('\u{1042d}', ['\u{10405}', '\u{0}', '\u{0}']), + ('\u{1042e}', ['\u{10406}', '\u{0}', '\u{0}']), + ('\u{1042f}', ['\u{10407}', '\u{0}', '\u{0}']), + ('\u{10430}', ['\u{10408}', '\u{0}', '\u{0}']), + ('\u{10431}', ['\u{10409}', '\u{0}', '\u{0}']), + ('\u{10432}', ['\u{1040a}', '\u{0}', '\u{0}']), + ('\u{10433}', ['\u{1040b}', '\u{0}', '\u{0}']), + ('\u{10434}', ['\u{1040c}', '\u{0}', '\u{0}']), + ('\u{10435}', ['\u{1040d}', '\u{0}', '\u{0}']), + ('\u{10436}', ['\u{1040e}', '\u{0}', '\u{0}']), + ('\u{10437}', ['\u{1040f}', '\u{0}', '\u{0}']), + ('\u{10438}', ['\u{10410}', '\u{0}', '\u{0}']), + ('\u{10439}', ['\u{10411}', '\u{0}', '\u{0}']), + ('\u{1043a}', ['\u{10412}', '\u{0}', '\u{0}']), + ('\u{1043b}', ['\u{10413}', '\u{0}', '\u{0}']), + ('\u{1043c}', ['\u{10414}', '\u{0}', '\u{0}']), + ('\u{1043d}', ['\u{10415}', '\u{0}', '\u{0}']), + ('\u{1043e}', ['\u{10416}', '\u{0}', '\u{0}']), + ('\u{1043f}', ['\u{10417}', '\u{0}', '\u{0}']), + ('\u{10440}', ['\u{10418}', '\u{0}', '\u{0}']), + ('\u{10441}', ['\u{10419}', '\u{0}', '\u{0}']), + ('\u{10442}', ['\u{1041a}', '\u{0}', '\u{0}']), + ('\u{10443}', ['\u{1041b}', '\u{0}', '\u{0}']), + ('\u{10444}', ['\u{1041c}', '\u{0}', '\u{0}']), + ('\u{10445}', ['\u{1041d}', '\u{0}', '\u{0}']), + ('\u{10446}', ['\u{1041e}', '\u{0}', '\u{0}']), + ('\u{10447}', ['\u{1041f}', '\u{0}', '\u{0}']), + ('\u{10448}', ['\u{10420}', '\u{0}', '\u{0}']), + ('\u{10449}', ['\u{10421}', '\u{0}', '\u{0}']), + ('\u{1044a}', ['\u{10422}', '\u{0}', '\u{0}']), + ('\u{1044b}', ['\u{10423}', '\u{0}', '\u{0}']), + ('\u{1044c}', ['\u{10424}', '\u{0}', '\u{0}']), + ('\u{1044d}', ['\u{10425}', '\u{0}', '\u{0}']), + ('\u{1044e}', ['\u{10426}', '\u{0}', '\u{0}']), + ('\u{1044f}', ['\u{10427}', '\u{0}', '\u{0}']), + ('\u{104d8}', ['\u{104b0}', '\u{0}', '\u{0}']), + ('\u{104d9}', ['\u{104b1}', '\u{0}', '\u{0}']), + ('\u{104da}', ['\u{104b2}', '\u{0}', '\u{0}']), + ('\u{104db}', ['\u{104b3}', '\u{0}', '\u{0}']), + ('\u{104dc}', ['\u{104b4}', '\u{0}', '\u{0}']), + ('\u{104dd}', ['\u{104b5}', '\u{0}', '\u{0}']), + ('\u{104de}', ['\u{104b6}', '\u{0}', '\u{0}']), + ('\u{104df}', ['\u{104b7}', '\u{0}', '\u{0}']), + ('\u{104e0}', ['\u{104b8}', '\u{0}', '\u{0}']), + ('\u{104e1}', ['\u{104b9}', '\u{0}', '\u{0}']), + ('\u{104e2}', ['\u{104ba}', '\u{0}', '\u{0}']), + ('\u{104e3}', ['\u{104bb}', '\u{0}', '\u{0}']), + ('\u{104e4}', ['\u{104bc}', '\u{0}', '\u{0}']), + ('\u{104e5}', ['\u{104bd}', '\u{0}', '\u{0}']), + ('\u{104e6}', ['\u{104be}', '\u{0}', '\u{0}']), + ('\u{104e7}', ['\u{104bf}', '\u{0}', '\u{0}']), + ('\u{104e8}', ['\u{104c0}', '\u{0}', '\u{0}']), + ('\u{104e9}', ['\u{104c1}', '\u{0}', '\u{0}']), + ('\u{104ea}', ['\u{104c2}', '\u{0}', '\u{0}']), + ('\u{104eb}', ['\u{104c3}', '\u{0}', '\u{0}']), + ('\u{104ec}', ['\u{104c4}', '\u{0}', '\u{0}']), + ('\u{104ed}', ['\u{104c5}', '\u{0}', '\u{0}']), + ('\u{104ee}', ['\u{104c6}', '\u{0}', '\u{0}']), + ('\u{104ef}', ['\u{104c7}', '\u{0}', '\u{0}']), + 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('\u{105b5}', ['\u{1058e}', '\u{0}', '\u{0}']), + ('\u{105b6}', ['\u{1058f}', '\u{0}', '\u{0}']), + ('\u{105b7}', ['\u{10590}', '\u{0}', '\u{0}']), + ('\u{105b8}', ['\u{10591}', '\u{0}', '\u{0}']), + ('\u{105b9}', ['\u{10592}', '\u{0}', '\u{0}']), + ('\u{105bb}', ['\u{10594}', '\u{0}', '\u{0}']), + ('\u{105bc}', ['\u{10595}', '\u{0}', '\u{0}']), + ('\u{10cc0}', ['\u{10c80}', '\u{0}', '\u{0}']), + ('\u{10cc1}', ['\u{10c81}', '\u{0}', '\u{0}']), + ('\u{10cc2}', ['\u{10c82}', '\u{0}', '\u{0}']), + ('\u{10cc3}', ['\u{10c83}', '\u{0}', '\u{0}']), + ('\u{10cc4}', ['\u{10c84}', '\u{0}', '\u{0}']), + ('\u{10cc5}', ['\u{10c85}', '\u{0}', '\u{0}']), + ('\u{10cc6}', ['\u{10c86}', '\u{0}', '\u{0}']), + ('\u{10cc7}', ['\u{10c87}', '\u{0}', '\u{0}']), + ('\u{10cc8}', ['\u{10c88}', '\u{0}', '\u{0}']), + ('\u{10cc9}', ['\u{10c89}', '\u{0}', '\u{0}']), + ('\u{10cca}', ['\u{10c8a}', '\u{0}', '\u{0}']), + ('\u{10ccb}', ['\u{10c8b}', '\u{0}', '\u{0}']), + ('\u{10ccc}', ['\u{10c8c}', '\u{0}', '\u{0}']), + ('\u{10ccd}', ['\u{10c8d}', '\u{0}', '\u{0}']), + ('\u{10cce}', ['\u{10c8e}', '\u{0}', '\u{0}']), + ('\u{10ccf}', ['\u{10c8f}', '\u{0}', '\u{0}']), + ('\u{10cd0}', ['\u{10c90}', '\u{0}', '\u{0}']), + ('\u{10cd1}', ['\u{10c91}', '\u{0}', '\u{0}']), + ('\u{10cd2}', ['\u{10c92}', '\u{0}', '\u{0}']), + ('\u{10cd3}', ['\u{10c93}', '\u{0}', '\u{0}']), + ('\u{10cd4}', ['\u{10c94}', '\u{0}', '\u{0}']), + ('\u{10cd5}', ['\u{10c95}', '\u{0}', '\u{0}']), + ('\u{10cd6}', ['\u{10c96}', '\u{0}', '\u{0}']), + ('\u{10cd7}', ['\u{10c97}', '\u{0}', '\u{0}']), + ('\u{10cd8}', ['\u{10c98}', '\u{0}', '\u{0}']), + ('\u{10cd9}', ['\u{10c99}', '\u{0}', '\u{0}']), + ('\u{10cda}', ['\u{10c9a}', '\u{0}', '\u{0}']), + ('\u{10cdb}', ['\u{10c9b}', '\u{0}', '\u{0}']), + ('\u{10cdc}', ['\u{10c9c}', '\u{0}', '\u{0}']), + ('\u{10cdd}', ['\u{10c9d}', '\u{0}', '\u{0}']), + ('\u{10cde}', ['\u{10c9e}', '\u{0}', '\u{0}']), + ('\u{10cdf}', ['\u{10c9f}', '\u{0}', '\u{0}']), + ('\u{10ce0}', ['\u{10ca0}', '\u{0}', '\u{0}']), + ('\u{10ce1}', ['\u{10ca1}', '\u{0}', '\u{0}']), + ('\u{10ce2}', ['\u{10ca2}', '\u{0}', '\u{0}']), + ('\u{10ce3}', ['\u{10ca3}', '\u{0}', '\u{0}']), + ('\u{10ce4}', ['\u{10ca4}', '\u{0}', '\u{0}']), + ('\u{10ce5}', ['\u{10ca5}', '\u{0}', '\u{0}']), + ('\u{10ce6}', ['\u{10ca6}', '\u{0}', '\u{0}']), + ('\u{10ce7}', ['\u{10ca7}', '\u{0}', '\u{0}']), + ('\u{10ce8}', ['\u{10ca8}', '\u{0}', '\u{0}']), + ('\u{10ce9}', ['\u{10ca9}', '\u{0}', '\u{0}']), + ('\u{10cea}', ['\u{10caa}', '\u{0}', '\u{0}']), + ('\u{10ceb}', ['\u{10cab}', '\u{0}', '\u{0}']), + ('\u{10cec}', ['\u{10cac}', '\u{0}', '\u{0}']), + ('\u{10ced}', ['\u{10cad}', '\u{0}', '\u{0}']), + ('\u{10cee}', ['\u{10cae}', '\u{0}', '\u{0}']), + ('\u{10cef}', ['\u{10caf}', '\u{0}', '\u{0}']), + ('\u{10cf0}', ['\u{10cb0}', '\u{0}', '\u{0}']), + ('\u{10cf1}', ['\u{10cb1}', '\u{0}', '\u{0}']), + ('\u{10cf2}', ['\u{10cb2}', '\u{0}', '\u{0}']), + ('\u{10d70}', ['\u{10d50}', '\u{0}', '\u{0}']), + ('\u{10d71}', ['\u{10d51}', '\u{0}', '\u{0}']), + ('\u{10d72}', ['\u{10d52}', '\u{0}', '\u{0}']), + ('\u{10d73}', ['\u{10d53}', '\u{0}', '\u{0}']), + ('\u{10d74}', ['\u{10d54}', '\u{0}', '\u{0}']), + ('\u{10d75}', ['\u{10d55}', '\u{0}', '\u{0}']), + ('\u{10d76}', ['\u{10d56}', '\u{0}', '\u{0}']), + ('\u{10d77}', ['\u{10d57}', '\u{0}', '\u{0}']), + ('\u{10d78}', ['\u{10d58}', '\u{0}', '\u{0}']), + ('\u{10d79}', ['\u{10d59}', '\u{0}', '\u{0}']), + ('\u{10d7a}', ['\u{10d5a}', '\u{0}', '\u{0}']), + ('\u{10d7b}', ['\u{10d5b}', '\u{0}', '\u{0}']), + ('\u{10d7c}', ['\u{10d5c}', '\u{0}', '\u{0}']), + ('\u{10d7d}', ['\u{10d5d}', '\u{0}', '\u{0}']), + ('\u{10d7e}', ['\u{10d5e}', '\u{0}', '\u{0}']), + ('\u{10d7f}', ['\u{10d5f}', '\u{0}', '\u{0}']), + ('\u{10d80}', ['\u{10d60}', '\u{0}', '\u{0}']), + ('\u{10d81}', ['\u{10d61}', '\u{0}', '\u{0}']), + ('\u{10d82}', ['\u{10d62}', '\u{0}', '\u{0}']), + ('\u{10d83}', ['\u{10d63}', '\u{0}', '\u{0}']), + ('\u{10d84}', ['\u{10d64}', '\u{0}', '\u{0}']), + ('\u{10d85}', ['\u{10d65}', '\u{0}', '\u{0}']), + ('\u{118c0}', ['\u{118a0}', '\u{0}', '\u{0}']), + ('\u{118c1}', ['\u{118a1}', '\u{0}', '\u{0}']), + ('\u{118c2}', ['\u{118a2}', '\u{0}', '\u{0}']), + ('\u{118c3}', ['\u{118a3}', '\u{0}', '\u{0}']), + ('\u{118c4}', ['\u{118a4}', '\u{0}', '\u{0}']), + ('\u{118c5}', ['\u{118a5}', '\u{0}', '\u{0}']), + ('\u{118c6}', ['\u{118a6}', '\u{0}', '\u{0}']), + ('\u{118c7}', ['\u{118a7}', '\u{0}', '\u{0}']), + ('\u{118c8}', ['\u{118a8}', '\u{0}', '\u{0}']), + ('\u{118c9}', ['\u{118a9}', '\u{0}', '\u{0}']), + ('\u{118ca}', ['\u{118aa}', '\u{0}', '\u{0}']), + ('\u{118cb}', ['\u{118ab}', '\u{0}', '\u{0}']), + ('\u{118cc}', ['\u{118ac}', '\u{0}', '\u{0}']), + ('\u{118cd}', ['\u{118ad}', '\u{0}', '\u{0}']), + ('\u{118ce}', ['\u{118ae}', '\u{0}', '\u{0}']), + ('\u{118cf}', ['\u{118af}', '\u{0}', '\u{0}']), + ('\u{118d0}', ['\u{118b0}', '\u{0}', '\u{0}']), + ('\u{118d1}', ['\u{118b1}', '\u{0}', '\u{0}']), + ('\u{118d2}', ['\u{118b2}', '\u{0}', '\u{0}']), + ('\u{118d3}', ['\u{118b3}', '\u{0}', '\u{0}']), + ('\u{118d4}', ['\u{118b4}', '\u{0}', '\u{0}']), + ('\u{118d5}', ['\u{118b5}', '\u{0}', '\u{0}']), + ('\u{118d6}', ['\u{118b6}', '\u{0}', '\u{0}']), + ('\u{118d7}', ['\u{118b7}', '\u{0}', '\u{0}']), + ('\u{118d8}', ['\u{118b8}', '\u{0}', '\u{0}']), + ('\u{118d9}', ['\u{118b9}', '\u{0}', '\u{0}']), + ('\u{118da}', ['\u{118ba}', '\u{0}', '\u{0}']), + ('\u{118db}', ['\u{118bb}', '\u{0}', '\u{0}']), + ('\u{118dc}', ['\u{118bc}', '\u{0}', '\u{0}']), + ('\u{118dd}', ['\u{118bd}', '\u{0}', '\u{0}']), + ('\u{118de}', ['\u{118be}', '\u{0}', '\u{0}']), + ('\u{118df}', ['\u{118bf}', '\u{0}', '\u{0}']), + ('\u{16e60}', ['\u{16e40}', '\u{0}', '\u{0}']), + ('\u{16e61}', ['\u{16e41}', '\u{0}', '\u{0}']), + ('\u{16e62}', ['\u{16e42}', '\u{0}', '\u{0}']), + ('\u{16e63}', ['\u{16e43}', '\u{0}', '\u{0}']), + ('\u{16e64}', ['\u{16e44}', '\u{0}', '\u{0}']), + ('\u{16e65}', ['\u{16e45}', '\u{0}', '\u{0}']), + ('\u{16e66}', ['\u{16e46}', '\u{0}', '\u{0}']), + ('\u{16e67}', ['\u{16e47}', '\u{0}', '\u{0}']), + ('\u{16e68}', ['\u{16e48}', '\u{0}', '\u{0}']), + ('\u{16e69}', ['\u{16e49}', '\u{0}', '\u{0}']), + ('\u{16e6a}', ['\u{16e4a}', '\u{0}', '\u{0}']), + ('\u{16e6b}', ['\u{16e4b}', '\u{0}', '\u{0}']), + ('\u{16e6c}', ['\u{16e4c}', '\u{0}', '\u{0}']), + ('\u{16e6d}', ['\u{16e4d}', '\u{0}', '\u{0}']), + ('\u{16e6e}', ['\u{16e4e}', '\u{0}', '\u{0}']), + ('\u{16e6f}', ['\u{16e4f}', '\u{0}', '\u{0}']), + ('\u{16e70}', ['\u{16e50}', '\u{0}', '\u{0}']), + ('\u{16e71}', ['\u{16e51}', '\u{0}', '\u{0}']), + ('\u{16e72}', ['\u{16e52}', '\u{0}', '\u{0}']), + ('\u{16e73}', ['\u{16e53}', '\u{0}', '\u{0}']), + ('\u{16e74}', ['\u{16e54}', '\u{0}', '\u{0}']), + ('\u{16e75}', ['\u{16e55}', '\u{0}', '\u{0}']), + ('\u{16e76}', ['\u{16e56}', '\u{0}', '\u{0}']), + ('\u{16e77}', ['\u{16e57}', '\u{0}', '\u{0}']), + ('\u{16e78}', ['\u{16e58}', '\u{0}', '\u{0}']), + ('\u{16e79}', ['\u{16e59}', '\u{0}', '\u{0}']), + ('\u{16e7a}', ['\u{16e5a}', '\u{0}', '\u{0}']), + ('\u{16e7b}', ['\u{16e5b}', '\u{0}', '\u{0}']), + ('\u{16e7c}', ['\u{16e5c}', '\u{0}', '\u{0}']), + ('\u{16e7d}', ['\u{16e5d}', '\u{0}', '\u{0}']), + ('\u{16e7e}', ['\u{16e5e}', '\u{0}', '\u{0}']), + ('\u{16e7f}', ['\u{16e5f}', '\u{0}', '\u{0}']), + ('\u{16ebb}', ['\u{16ea0}', '\u{0}', '\u{0}']), + ('\u{16ebc}', ['\u{16ea1}', '\u{0}', '\u{0}']), + ('\u{16ebd}', ['\u{16ea2}', '\u{0}', '\u{0}']), + ('\u{16ebe}', ['\u{16ea3}', '\u{0}', '\u{0}']), + ('\u{16ebf}', ['\u{16ea4}', '\u{0}', '\u{0}']), + ('\u{16ec0}', ['\u{16ea5}', '\u{0}', '\u{0}']), + ('\u{16ec1}', ['\u{16ea6}', '\u{0}', '\u{0}']), + ('\u{16ec2}', ['\u{16ea7}', '\u{0}', '\u{0}']), + ('\u{16ec3}', ['\u{16ea8}', '\u{0}', '\u{0}']), + ('\u{16ec4}', ['\u{16ea9}', '\u{0}', '\u{0}']), + ('\u{16ec5}', ['\u{16eaa}', '\u{0}', '\u{0}']), + ('\u{16ec6}', ['\u{16eab}', '\u{0}', '\u{0}']), + ('\u{16ec7}', ['\u{16eac}', '\u{0}', '\u{0}']), + ('\u{16ec8}', ['\u{16ead}', '\u{0}', '\u{0}']), + ('\u{16ec9}', ['\u{16eae}', '\u{0}', '\u{0}']), + ('\u{16eca}', ['\u{16eaf}', '\u{0}', '\u{0}']), + ('\u{16ecb}', ['\u{16eb0}', '\u{0}', '\u{0}']), + ('\u{16ecc}', ['\u{16eb1}', '\u{0}', '\u{0}']), + ('\u{16ecd}', ['\u{16eb2}', '\u{0}', '\u{0}']), + ('\u{16ece}', ['\u{16eb3}', '\u{0}', '\u{0}']), + ('\u{16ecf}', ['\u{16eb4}', '\u{0}', '\u{0}']), + ('\u{16ed0}', ['\u{16eb5}', '\u{0}', '\u{0}']), + ('\u{16ed1}', ['\u{16eb6}', '\u{0}', '\u{0}']), + ('\u{16ed2}', ['\u{16eb7}', '\u{0}', '\u{0}']), + ('\u{16ed3}', ['\u{16eb8}', '\u{0}', '\u{0}']), + ('\u{1e922}', ['\u{1e900}', '\u{0}', '\u{0}']), + ('\u{1e923}', ['\u{1e901}', '\u{0}', '\u{0}']), + ('\u{1e924}', ['\u{1e902}', '\u{0}', '\u{0}']), + ('\u{1e925}', ['\u{1e903}', '\u{0}', '\u{0}']), + ('\u{1e926}', ['\u{1e904}', '\u{0}', '\u{0}']), + ('\u{1e927}', ['\u{1e905}', '\u{0}', '\u{0}']), + ('\u{1e928}', ['\u{1e906}', '\u{0}', '\u{0}']), + ('\u{1e929}', ['\u{1e907}', '\u{0}', '\u{0}']), + ('\u{1e92a}', ['\u{1e908}', '\u{0}', '\u{0}']), + ('\u{1e92b}', ['\u{1e909}', '\u{0}', '\u{0}']), + ('\u{1e92c}', ['\u{1e90a}', '\u{0}', '\u{0}']), + ('\u{1e92d}', ['\u{1e90b}', '\u{0}', '\u{0}']), + ('\u{1e92e}', ['\u{1e90c}', '\u{0}', '\u{0}']), + ('\u{1e92f}', ['\u{1e90d}', '\u{0}', '\u{0}']), + ('\u{1e930}', ['\u{1e90e}', '\u{0}', '\u{0}']), + ('\u{1e931}', ['\u{1e90f}', '\u{0}', '\u{0}']), + ('\u{1e932}', ['\u{1e910}', '\u{0}', '\u{0}']), + ('\u{1e933}', ['\u{1e911}', '\u{0}', '\u{0}']), + ('\u{1e934}', ['\u{1e912}', '\u{0}', '\u{0}']), + ('\u{1e935}', ['\u{1e913}', '\u{0}', '\u{0}']), + ('\u{1e936}', ['\u{1e914}', '\u{0}', '\u{0}']), + ('\u{1e937}', ['\u{1e915}', '\u{0}', '\u{0}']), + ('\u{1e938}', ['\u{1e916}', '\u{0}', '\u{0}']), + ('\u{1e939}', ['\u{1e917}', '\u{0}', '\u{0}']), + ('\u{1e93a}', ['\u{1e918}', '\u{0}', '\u{0}']), + ('\u{1e93b}', ['\u{1e919}', '\u{0}', '\u{0}']), + ('\u{1e93c}', ['\u{1e91a}', '\u{0}', '\u{0}']), + ('\u{1e93d}', ['\u{1e91b}', '\u{0}', '\u{0}']), + ('\u{1e93e}', ['\u{1e91c}', '\u{0}', '\u{0}']), + ('\u{1e93f}', ['\u{1e91d}', '\u{0}', '\u{0}']), + ('\u{1e940}', ['\u{1e91e}', '\u{0}', '\u{0}']), + ('\u{1e941}', ['\u{1e91f}', '\u{0}', '\u{0}']), + ('\u{1e942}', ['\u{1e920}', '\u{0}', '\u{0}']), + ('\u{1e943}', ['\u{1e921}', '\u{0}', '\u{0}']), +]; + +#[rustfmt::skip] +pub(super) static TO_TITLE: &[(char, [char; 3]); 135] = &[ + ('\u{df}', ['S', 's', '\u{0}']), ('\u{1c4}', ['\u{1c5}', '\u{0}', '\u{0}']), + ('\u{1c5}', ['\u{1c5}', '\u{0}', '\u{0}']), ('\u{1c6}', ['\u{1c5}', '\u{0}', '\u{0}']), + ('\u{1c7}', ['\u{1c8}', '\u{0}', '\u{0}']), ('\u{1c8}', ['\u{1c8}', '\u{0}', '\u{0}']), + ('\u{1c9}', ['\u{1c8}', '\u{0}', '\u{0}']), ('\u{1ca}', ['\u{1cb}', '\u{0}', '\u{0}']), + ('\u{1cb}', ['\u{1cb}', '\u{0}', '\u{0}']), ('\u{1cc}', ['\u{1cb}', '\u{0}', '\u{0}']), + ('\u{1f1}', ['\u{1f2}', '\u{0}', '\u{0}']), ('\u{1f2}', ['\u{1f2}', '\u{0}', '\u{0}']), + ('\u{1f3}', ['\u{1f2}', '\u{0}', '\u{0}']), ('\u{587}', ['\u{535}', '\u{582}', '\u{0}']), + ('\u{10d0}', ['\u{10d0}', '\u{0}', '\u{0}']), ('\u{10d1}', ['\u{10d1}', '\u{0}', '\u{0}']), + ('\u{10d2}', ['\u{10d2}', '\u{0}', '\u{0}']), ('\u{10d3}', ['\u{10d3}', '\u{0}', '\u{0}']), + ('\u{10d4}', ['\u{10d4}', '\u{0}', '\u{0}']), ('\u{10d5}', ['\u{10d5}', '\u{0}', '\u{0}']), + ('\u{10d6}', ['\u{10d6}', '\u{0}', '\u{0}']), ('\u{10d7}', ['\u{10d7}', '\u{0}', '\u{0}']), + ('\u{10d8}', ['\u{10d8}', '\u{0}', '\u{0}']), ('\u{10d9}', ['\u{10d9}', '\u{0}', '\u{0}']), + ('\u{10da}', ['\u{10da}', '\u{0}', '\u{0}']), ('\u{10db}', ['\u{10db}', '\u{0}', '\u{0}']), + ('\u{10dc}', ['\u{10dc}', '\u{0}', '\u{0}']), ('\u{10dd}', ['\u{10dd}', '\u{0}', '\u{0}']), + ('\u{10de}', ['\u{10de}', '\u{0}', '\u{0}']), ('\u{10df}', ['\u{10df}', '\u{0}', '\u{0}']), + ('\u{10e0}', ['\u{10e0}', '\u{0}', '\u{0}']), ('\u{10e1}', ['\u{10e1}', '\u{0}', '\u{0}']), + ('\u{10e2}', ['\u{10e2}', '\u{0}', '\u{0}']), ('\u{10e3}', ['\u{10e3}', '\u{0}', '\u{0}']), + ('\u{10e4}', ['\u{10e4}', '\u{0}', '\u{0}']), ('\u{10e5}', ['\u{10e5}', '\u{0}', '\u{0}']), + ('\u{10e6}', ['\u{10e6}', '\u{0}', '\u{0}']), ('\u{10e7}', ['\u{10e7}', '\u{0}', '\u{0}']), + ('\u{10e8}', ['\u{10e8}', '\u{0}', '\u{0}']), ('\u{10e9}', ['\u{10e9}', '\u{0}', '\u{0}']), + ('\u{10ea}', ['\u{10ea}', '\u{0}', '\u{0}']), ('\u{10eb}', ['\u{10eb}', '\u{0}', '\u{0}']), + ('\u{10ec}', ['\u{10ec}', '\u{0}', '\u{0}']), ('\u{10ed}', ['\u{10ed}', '\u{0}', '\u{0}']), + ('\u{10ee}', ['\u{10ee}', '\u{0}', '\u{0}']), ('\u{10ef}', ['\u{10ef}', '\u{0}', '\u{0}']), + ('\u{10f0}', ['\u{10f0}', '\u{0}', '\u{0}']), ('\u{10f1}', ['\u{10f1}', '\u{0}', '\u{0}']), + ('\u{10f2}', ['\u{10f2}', '\u{0}', '\u{0}']), ('\u{10f3}', ['\u{10f3}', '\u{0}', '\u{0}']), + ('\u{10f4}', ['\u{10f4}', '\u{0}', '\u{0}']), ('\u{10f5}', ['\u{10f5}', '\u{0}', '\u{0}']), + ('\u{10f6}', ['\u{10f6}', '\u{0}', '\u{0}']), ('\u{10f7}', ['\u{10f7}', '\u{0}', '\u{0}']), + ('\u{10f8}', ['\u{10f8}', '\u{0}', '\u{0}']), ('\u{10f9}', ['\u{10f9}', '\u{0}', '\u{0}']), + ('\u{10fa}', ['\u{10fa}', '\u{0}', '\u{0}']), ('\u{10fd}', ['\u{10fd}', '\u{0}', '\u{0}']), + ('\u{10fe}', ['\u{10fe}', '\u{0}', '\u{0}']), ('\u{10ff}', ['\u{10ff}', '\u{0}', '\u{0}']), + ('\u{1f80}', ['\u{1f88}', '\u{0}', '\u{0}']), ('\u{1f81}', ['\u{1f89}', '\u{0}', '\u{0}']), + ('\u{1f82}', ['\u{1f8a}', '\u{0}', '\u{0}']), ('\u{1f83}', ['\u{1f8b}', '\u{0}', '\u{0}']), + ('\u{1f84}', ['\u{1f8c}', '\u{0}', '\u{0}']), ('\u{1f85}', ['\u{1f8d}', '\u{0}', '\u{0}']), + ('\u{1f86}', ['\u{1f8e}', '\u{0}', '\u{0}']), ('\u{1f87}', ['\u{1f8f}', '\u{0}', '\u{0}']), + ('\u{1f88}', ['\u{1f88}', '\u{0}', '\u{0}']), ('\u{1f89}', ['\u{1f89}', '\u{0}', '\u{0}']), + ('\u{1f8a}', ['\u{1f8a}', '\u{0}', '\u{0}']), ('\u{1f8b}', ['\u{1f8b}', '\u{0}', '\u{0}']), + ('\u{1f8c}', ['\u{1f8c}', '\u{0}', '\u{0}']), ('\u{1f8d}', ['\u{1f8d}', '\u{0}', '\u{0}']), + ('\u{1f8e}', ['\u{1f8e}', '\u{0}', '\u{0}']), ('\u{1f8f}', ['\u{1f8f}', '\u{0}', '\u{0}']), + ('\u{1f90}', ['\u{1f98}', '\u{0}', '\u{0}']), ('\u{1f91}', ['\u{1f99}', '\u{0}', '\u{0}']), + ('\u{1f92}', ['\u{1f9a}', '\u{0}', '\u{0}']), ('\u{1f93}', ['\u{1f9b}', '\u{0}', '\u{0}']), + ('\u{1f94}', ['\u{1f9c}', '\u{0}', '\u{0}']), ('\u{1f95}', ['\u{1f9d}', '\u{0}', '\u{0}']), + ('\u{1f96}', ['\u{1f9e}', '\u{0}', '\u{0}']), ('\u{1f97}', ['\u{1f9f}', '\u{0}', '\u{0}']), + ('\u{1f98}', ['\u{1f98}', '\u{0}', '\u{0}']), ('\u{1f99}', ['\u{1f99}', '\u{0}', '\u{0}']), + ('\u{1f9a}', ['\u{1f9a}', '\u{0}', '\u{0}']), ('\u{1f9b}', ['\u{1f9b}', '\u{0}', '\u{0}']), + ('\u{1f9c}', ['\u{1f9c}', '\u{0}', '\u{0}']), ('\u{1f9d}', ['\u{1f9d}', '\u{0}', '\u{0}']), + ('\u{1f9e}', ['\u{1f9e}', '\u{0}', '\u{0}']), ('\u{1f9f}', ['\u{1f9f}', '\u{0}', '\u{0}']), + ('\u{1fa0}', ['\u{1fa8}', '\u{0}', '\u{0}']), ('\u{1fa1}', ['\u{1fa9}', '\u{0}', '\u{0}']), + ('\u{1fa2}', ['\u{1faa}', '\u{0}', '\u{0}']), ('\u{1fa3}', ['\u{1fab}', '\u{0}', '\u{0}']), + ('\u{1fa4}', ['\u{1fac}', '\u{0}', '\u{0}']), ('\u{1fa5}', ['\u{1fad}', '\u{0}', '\u{0}']), + ('\u{1fa6}', ['\u{1fae}', '\u{0}', '\u{0}']), ('\u{1fa7}', ['\u{1faf}', '\u{0}', '\u{0}']), + ('\u{1fa8}', ['\u{1fa8}', '\u{0}', '\u{0}']), ('\u{1fa9}', ['\u{1fa9}', '\u{0}', '\u{0}']), + ('\u{1faa}', ['\u{1faa}', '\u{0}', '\u{0}']), ('\u{1fab}', ['\u{1fab}', '\u{0}', '\u{0}']), + ('\u{1fac}', ['\u{1fac}', '\u{0}', '\u{0}']), ('\u{1fad}', ['\u{1fad}', '\u{0}', '\u{0}']), + ('\u{1fae}', ['\u{1fae}', '\u{0}', '\u{0}']), ('\u{1faf}', ['\u{1faf}', '\u{0}', '\u{0}']), + ('\u{1fb2}', ['\u{1fba}', '\u{345}', '\u{0}']), + ('\u{1fb3}', ['\u{1fbc}', '\u{0}', '\u{0}']), ('\u{1fb4}', ['\u{386}', '\u{345}', '\u{0}']), + ('\u{1fb7}', ['\u{391}', '\u{342}', '\u{345}']), + ('\u{1fbc}', ['\u{1fbc}', '\u{0}', '\u{0}']), + ('\u{1fc2}', ['\u{1fca}', '\u{345}', '\u{0}']), + ('\u{1fc3}', ['\u{1fcc}', '\u{0}', '\u{0}']), ('\u{1fc4}', ['\u{389}', '\u{345}', '\u{0}']), + ('\u{1fc7}', ['\u{397}', '\u{342}', '\u{345}']), + ('\u{1fcc}', ['\u{1fcc}', '\u{0}', '\u{0}']), + ('\u{1ff2}', ['\u{1ffa}', '\u{345}', '\u{0}']), + ('\u{1ff3}', ['\u{1ffc}', '\u{0}', '\u{0}']), ('\u{1ff4}', ['\u{38f}', '\u{345}', '\u{0}']), + ('\u{1ff7}', ['\u{3a9}', '\u{342}', '\u{345}']), + ('\u{1ffc}', ['\u{1ffc}', '\u{0}', '\u{0}']), ('\u{fb00}', ['F', 'f', '\u{0}']), + ('\u{fb01}', ['F', 'i', '\u{0}']), ('\u{fb02}', ['F', 'l', '\u{0}']), + ('\u{fb03}', ['F', 'f', 'i']), ('\u{fb04}', ['F', 'f', 'l']), + ('\u{fb05}', ['S', 't', '\u{0}']), ('\u{fb06}', ['S', 't', '\u{0}']), + ('\u{fb13}', ['\u{544}', '\u{576}', '\u{0}']), + ('\u{fb14}', ['\u{544}', '\u{565}', '\u{0}']), + ('\u{fb15}', ['\u{544}', '\u{56b}', '\u{0}']), + ('\u{fb16}', ['\u{54e}', '\u{576}', '\u{0}']), + ('\u{fb17}', ['\u{544}', '\u{56d}', '\u{0}']), +]; + +#[rustfmt::skip] +pub(super) static TO_CASEFOLD: &[(char, [char; 3]); 174] = &[ + ('\u{131}', ['\u{131}', '\u{0}', '\u{0}']), ('\u{13a0}', ['\u{13a0}', '\u{0}', '\u{0}']), + ('\u{13a1}', ['\u{13a1}', '\u{0}', '\u{0}']), ('\u{13a2}', ['\u{13a2}', '\u{0}', '\u{0}']), + ('\u{13a3}', ['\u{13a3}', '\u{0}', '\u{0}']), ('\u{13a4}', ['\u{13a4}', '\u{0}', '\u{0}']), + ('\u{13a5}', ['\u{13a5}', '\u{0}', '\u{0}']), ('\u{13a6}', ['\u{13a6}', '\u{0}', '\u{0}']), + ('\u{13a7}', ['\u{13a7}', '\u{0}', '\u{0}']), ('\u{13a8}', ['\u{13a8}', '\u{0}', '\u{0}']), + ('\u{13a9}', ['\u{13a9}', '\u{0}', '\u{0}']), ('\u{13aa}', ['\u{13aa}', '\u{0}', '\u{0}']), + ('\u{13ab}', ['\u{13ab}', '\u{0}', '\u{0}']), ('\u{13ac}', ['\u{13ac}', '\u{0}', '\u{0}']), + ('\u{13ad}', ['\u{13ad}', '\u{0}', '\u{0}']), ('\u{13ae}', ['\u{13ae}', '\u{0}', '\u{0}']), + ('\u{13af}', ['\u{13af}', '\u{0}', '\u{0}']), ('\u{13b0}', ['\u{13b0}', '\u{0}', '\u{0}']), + ('\u{13b1}', ['\u{13b1}', '\u{0}', '\u{0}']), ('\u{13b2}', ['\u{13b2}', '\u{0}', '\u{0}']), + ('\u{13b3}', ['\u{13b3}', '\u{0}', '\u{0}']), ('\u{13b4}', ['\u{13b4}', '\u{0}', '\u{0}']), + ('\u{13b5}', ['\u{13b5}', '\u{0}', '\u{0}']), ('\u{13b6}', ['\u{13b6}', '\u{0}', '\u{0}']), + ('\u{13b7}', ['\u{13b7}', '\u{0}', '\u{0}']), ('\u{13b8}', ['\u{13b8}', '\u{0}', '\u{0}']), + ('\u{13b9}', ['\u{13b9}', '\u{0}', '\u{0}']), ('\u{13ba}', ['\u{13ba}', '\u{0}', '\u{0}']), + ('\u{13bb}', ['\u{13bb}', '\u{0}', '\u{0}']), ('\u{13bc}', ['\u{13bc}', '\u{0}', '\u{0}']), + ('\u{13bd}', ['\u{13bd}', '\u{0}', '\u{0}']), ('\u{13be}', ['\u{13be}', '\u{0}', '\u{0}']), + ('\u{13bf}', ['\u{13bf}', '\u{0}', '\u{0}']), ('\u{13c0}', ['\u{13c0}', '\u{0}', '\u{0}']), + ('\u{13c1}', ['\u{13c1}', '\u{0}', '\u{0}']), ('\u{13c2}', ['\u{13c2}', '\u{0}', '\u{0}']), + ('\u{13c3}', ['\u{13c3}', '\u{0}', '\u{0}']), ('\u{13c4}', ['\u{13c4}', '\u{0}', '\u{0}']), + ('\u{13c5}', ['\u{13c5}', '\u{0}', '\u{0}']), ('\u{13c6}', ['\u{13c6}', '\u{0}', '\u{0}']), + ('\u{13c7}', ['\u{13c7}', '\u{0}', '\u{0}']), ('\u{13c8}', ['\u{13c8}', '\u{0}', '\u{0}']), + ('\u{13c9}', ['\u{13c9}', '\u{0}', '\u{0}']), ('\u{13ca}', ['\u{13ca}', '\u{0}', '\u{0}']), + ('\u{13cb}', ['\u{13cb}', '\u{0}', '\u{0}']), ('\u{13cc}', ['\u{13cc}', '\u{0}', '\u{0}']), + ('\u{13cd}', ['\u{13cd}', '\u{0}', '\u{0}']), ('\u{13ce}', ['\u{13ce}', '\u{0}', '\u{0}']), + ('\u{13cf}', ['\u{13cf}', '\u{0}', '\u{0}']), ('\u{13d0}', ['\u{13d0}', '\u{0}', '\u{0}']), + ('\u{13d1}', ['\u{13d1}', '\u{0}', '\u{0}']), ('\u{13d2}', ['\u{13d2}', '\u{0}', '\u{0}']), + ('\u{13d3}', ['\u{13d3}', '\u{0}', '\u{0}']), ('\u{13d4}', ['\u{13d4}', '\u{0}', '\u{0}']), + ('\u{13d5}', ['\u{13d5}', '\u{0}', '\u{0}']), ('\u{13d6}', ['\u{13d6}', '\u{0}', '\u{0}']), + ('\u{13d7}', ['\u{13d7}', '\u{0}', '\u{0}']), ('\u{13d8}', ['\u{13d8}', '\u{0}', '\u{0}']), + ('\u{13d9}', ['\u{13d9}', '\u{0}', '\u{0}']), ('\u{13da}', ['\u{13da}', '\u{0}', '\u{0}']), + ('\u{13db}', ['\u{13db}', '\u{0}', '\u{0}']), ('\u{13dc}', ['\u{13dc}', '\u{0}', '\u{0}']), + ('\u{13dd}', ['\u{13dd}', '\u{0}', '\u{0}']), ('\u{13de}', ['\u{13de}', '\u{0}', '\u{0}']), + ('\u{13df}', ['\u{13df}', '\u{0}', '\u{0}']), ('\u{13e0}', ['\u{13e0}', '\u{0}', '\u{0}']), + ('\u{13e1}', ['\u{13e1}', '\u{0}', '\u{0}']), ('\u{13e2}', ['\u{13e2}', '\u{0}', '\u{0}']), + ('\u{13e3}', ['\u{13e3}', '\u{0}', '\u{0}']), ('\u{13e4}', ['\u{13e4}', '\u{0}', '\u{0}']), + ('\u{13e5}', ['\u{13e5}', '\u{0}', '\u{0}']), ('\u{13e6}', ['\u{13e6}', '\u{0}', '\u{0}']), + ('\u{13e7}', ['\u{13e7}', '\u{0}', '\u{0}']), ('\u{13e8}', ['\u{13e8}', '\u{0}', '\u{0}']), + ('\u{13e9}', ['\u{13e9}', '\u{0}', '\u{0}']), ('\u{13ea}', ['\u{13ea}', '\u{0}', '\u{0}']), + ('\u{13eb}', ['\u{13eb}', '\u{0}', '\u{0}']), ('\u{13ec}', ['\u{13ec}', '\u{0}', '\u{0}']), + ('\u{13ed}', ['\u{13ed}', '\u{0}', '\u{0}']), ('\u{13ee}', ['\u{13ee}', '\u{0}', '\u{0}']), + ('\u{13ef}', ['\u{13ef}', '\u{0}', '\u{0}']), ('\u{13f0}', ['\u{13f0}', '\u{0}', '\u{0}']), + ('\u{13f1}', ['\u{13f1}', '\u{0}', '\u{0}']), ('\u{13f2}', ['\u{13f2}', '\u{0}', '\u{0}']), + ('\u{13f3}', ['\u{13f3}', '\u{0}', '\u{0}']), ('\u{13f4}', ['\u{13f4}', '\u{0}', '\u{0}']), + ('\u{13f5}', ['\u{13f5}', '\u{0}', '\u{0}']), ('\u{13f8}', ['\u{13f0}', '\u{0}', '\u{0}']), + ('\u{13f9}', ['\u{13f1}', '\u{0}', '\u{0}']), ('\u{13fa}', ['\u{13f2}', '\u{0}', '\u{0}']), + ('\u{13fb}', ['\u{13f3}', '\u{0}', '\u{0}']), ('\u{13fc}', ['\u{13f4}', '\u{0}', '\u{0}']), + ('\u{13fd}', ['\u{13f5}', '\u{0}', '\u{0}']), ('\u{1e9e}', ['s', 's', '\u{0}']), + ('\u{ab70}', ['\u{13a0}', '\u{0}', '\u{0}']), ('\u{ab71}', ['\u{13a1}', '\u{0}', '\u{0}']), + ('\u{ab72}', ['\u{13a2}', '\u{0}', '\u{0}']), ('\u{ab73}', ['\u{13a3}', '\u{0}', '\u{0}']), + ('\u{ab74}', ['\u{13a4}', '\u{0}', '\u{0}']), ('\u{ab75}', ['\u{13a5}', '\u{0}', '\u{0}']), + ('\u{ab76}', ['\u{13a6}', '\u{0}', '\u{0}']), ('\u{ab77}', ['\u{13a7}', '\u{0}', '\u{0}']), + ('\u{ab78}', ['\u{13a8}', '\u{0}', '\u{0}']), ('\u{ab79}', ['\u{13a9}', '\u{0}', '\u{0}']), + ('\u{ab7a}', ['\u{13aa}', '\u{0}', '\u{0}']), ('\u{ab7b}', ['\u{13ab}', '\u{0}', '\u{0}']), + ('\u{ab7c}', ['\u{13ac}', '\u{0}', '\u{0}']), ('\u{ab7d}', ['\u{13ad}', '\u{0}', '\u{0}']), + ('\u{ab7e}', ['\u{13ae}', '\u{0}', '\u{0}']), ('\u{ab7f}', ['\u{13af}', '\u{0}', '\u{0}']), + ('\u{ab80}', ['\u{13b0}', '\u{0}', '\u{0}']), ('\u{ab81}', ['\u{13b1}', '\u{0}', '\u{0}']), + ('\u{ab82}', ['\u{13b2}', '\u{0}', '\u{0}']), ('\u{ab83}', ['\u{13b3}', '\u{0}', '\u{0}']), + ('\u{ab84}', ['\u{13b4}', '\u{0}', '\u{0}']), ('\u{ab85}', ['\u{13b5}', '\u{0}', '\u{0}']), + ('\u{ab86}', ['\u{13b6}', '\u{0}', '\u{0}']), ('\u{ab87}', ['\u{13b7}', '\u{0}', '\u{0}']), + ('\u{ab88}', ['\u{13b8}', '\u{0}', '\u{0}']), ('\u{ab89}', ['\u{13b9}', '\u{0}', '\u{0}']), + ('\u{ab8a}', ['\u{13ba}', '\u{0}', '\u{0}']), ('\u{ab8b}', ['\u{13bb}', '\u{0}', '\u{0}']), + ('\u{ab8c}', ['\u{13bc}', '\u{0}', '\u{0}']), ('\u{ab8d}', ['\u{13bd}', '\u{0}', '\u{0}']), + ('\u{ab8e}', ['\u{13be}', '\u{0}', '\u{0}']), ('\u{ab8f}', ['\u{13bf}', '\u{0}', '\u{0}']), + ('\u{ab90}', ['\u{13c0}', '\u{0}', '\u{0}']), ('\u{ab91}', ['\u{13c1}', '\u{0}', '\u{0}']), + ('\u{ab92}', ['\u{13c2}', '\u{0}', '\u{0}']), ('\u{ab93}', ['\u{13c3}', '\u{0}', '\u{0}']), + ('\u{ab94}', ['\u{13c4}', '\u{0}', '\u{0}']), ('\u{ab95}', ['\u{13c5}', '\u{0}', '\u{0}']), + ('\u{ab96}', ['\u{13c6}', '\u{0}', '\u{0}']), ('\u{ab97}', ['\u{13c7}', '\u{0}', '\u{0}']), + ('\u{ab98}', ['\u{13c8}', '\u{0}', '\u{0}']), ('\u{ab99}', ['\u{13c9}', '\u{0}', '\u{0}']), + ('\u{ab9a}', ['\u{13ca}', '\u{0}', '\u{0}']), ('\u{ab9b}', ['\u{13cb}', '\u{0}', '\u{0}']), + ('\u{ab9c}', ['\u{13cc}', '\u{0}', '\u{0}']), ('\u{ab9d}', ['\u{13cd}', '\u{0}', '\u{0}']), + ('\u{ab9e}', ['\u{13ce}', '\u{0}', '\u{0}']), ('\u{ab9f}', ['\u{13cf}', '\u{0}', '\u{0}']), + ('\u{aba0}', ['\u{13d0}', '\u{0}', '\u{0}']), ('\u{aba1}', ['\u{13d1}', '\u{0}', '\u{0}']), + ('\u{aba2}', ['\u{13d2}', '\u{0}', '\u{0}']), ('\u{aba3}', ['\u{13d3}', '\u{0}', '\u{0}']), + ('\u{aba4}', ['\u{13d4}', '\u{0}', '\u{0}']), ('\u{aba5}', ['\u{13d5}', '\u{0}', '\u{0}']), + ('\u{aba6}', ['\u{13d6}', '\u{0}', '\u{0}']), ('\u{aba7}', ['\u{13d7}', '\u{0}', '\u{0}']), + ('\u{aba8}', ['\u{13d8}', '\u{0}', '\u{0}']), ('\u{aba9}', ['\u{13d9}', '\u{0}', '\u{0}']), + ('\u{abaa}', ['\u{13da}', '\u{0}', '\u{0}']), ('\u{abab}', ['\u{13db}', '\u{0}', '\u{0}']), + ('\u{abac}', ['\u{13dc}', '\u{0}', '\u{0}']), ('\u{abad}', ['\u{13dd}', '\u{0}', '\u{0}']), + ('\u{abae}', ['\u{13de}', '\u{0}', '\u{0}']), ('\u{abaf}', ['\u{13df}', '\u{0}', '\u{0}']), + ('\u{abb0}', ['\u{13e0}', '\u{0}', '\u{0}']), ('\u{abb1}', ['\u{13e1}', '\u{0}', '\u{0}']), + ('\u{abb2}', ['\u{13e2}', '\u{0}', '\u{0}']), ('\u{abb3}', ['\u{13e3}', '\u{0}', '\u{0}']), + ('\u{abb4}', ['\u{13e4}', '\u{0}', '\u{0}']), ('\u{abb5}', ['\u{13e5}', '\u{0}', '\u{0}']), + ('\u{abb6}', ['\u{13e6}', '\u{0}', '\u{0}']), ('\u{abb7}', ['\u{13e7}', '\u{0}', '\u{0}']), + ('\u{abb8}', ['\u{13e8}', '\u{0}', '\u{0}']), ('\u{abb9}', ['\u{13e9}', '\u{0}', '\u{0}']), + ('\u{abba}', ['\u{13ea}', '\u{0}', '\u{0}']), ('\u{abbb}', ['\u{13eb}', '\u{0}', '\u{0}']), + ('\u{abbc}', ['\u{13ec}', '\u{0}', '\u{0}']), ('\u{abbd}', ['\u{13ed}', '\u{0}', '\u{0}']), + ('\u{abbe}', ['\u{13ee}', '\u{0}', '\u{0}']), ('\u{abbf}', ['\u{13ef}', '\u{0}', '\u{0}']), +]; diff --git a/library/coretests/tests/waker.rs b/library/coretests/tests/waker.rs index 4889b8959ece4..be8b07b8ad009 100644 --- a/library/coretests/tests/waker.rs +++ b/library/coretests/tests/waker.rs @@ -5,16 +5,16 @@ use std::task::{RawWaker, RawWakerVTable, Waker}; fn test_waker_getters() { let raw_waker = RawWaker::new(ptr::without_provenance_mut(42usize), &WAKER_VTABLE); let waker = unsafe { Waker::from_raw(raw_waker) }; - assert_eq!(waker.data() as usize, 42); + assert_eq!(waker.data().addr(), 42); assert!(ptr::eq(waker.vtable(), &WAKER_VTABLE)); let waker2 = waker.clone(); - assert_eq!(waker2.data() as usize, 43); + assert_eq!(waker2.data().addr(), 43); assert!(ptr::eq(waker2.vtable(), &WAKER_VTABLE)); } static WAKER_VTABLE: RawWakerVTable = RawWakerVTable::new( - |data| RawWaker::new(ptr::without_provenance_mut(data as usize + 1), &WAKER_VTABLE), + |data| RawWaker::new(ptr::without_provenance_mut(data.addr() + 1), &WAKER_VTABLE), |_| {}, |_| {}, |_| {}, diff --git a/library/panic_abort/src/lib.rs b/library/panic_abort/src/lib.rs index d1706b6525295..e62d758e9e5d1 100644 --- a/library/panic_abort/src/lib.rs +++ b/library/panic_abort/src/lib.rs @@ -49,46 +49,3 @@ pub unsafe fn __rust_start_panic(_payload: &mut dyn PanicPayload) -> u32 { __rust_abort() } - -// This... is a bit of an oddity. The tl;dr; is that this is required to link -// correctly, the longer explanation is below. -// -// Right now the binaries of core/std that we ship are all compiled with -// `-C panic=unwind`. This is done to ensure that the binaries are maximally -// compatible with as many situations as possible. The compiler, however, -// requires a "personality function" for all functions compiled with `-C -// panic=unwind`. This personality function is hardcoded to the symbol -// `rust_eh_personality` and is defined by the `eh_personality` lang item. -// -// So... why not just define that lang item here? Good question! The way that -// panic runtimes are linked in is actually a little subtle in that they're -// "sort of" in the compiler's crate store, but only actually linked if another -// isn't actually linked. This ends up meaning that both this crate and the -// panic_unwind crate can appear in the compiler's crate store, and if both -// define the `eh_personality` lang item then that'll hit an error. -// -// To handle this the compiler only requires the `eh_personality` is defined if -// the panic runtime being linked in is the unwinding runtime, and otherwise -// it's not required to be defined (rightfully so). In this case, however, this -// library just defines this symbol so there's at least some personality -// somewhere. -// -// Essentially this symbol is just defined to get wired up to core/std -// binaries, but it should never be called as we don't link in an unwinding -// runtime at all. -pub mod personalities { - // In the past this module used to contain stubs for the personality - // functions of various platforms, but these where removed when personality - // functions were moved to std. - - // This corresponds to the `eh_catch_typeinfo` lang item - // that's only used on Emscripten currently. - // - // Since panics don't generate exceptions and foreign exceptions are - // currently UB with -C panic=abort (although this may be subject to - // change), any catch_unwind calls will never use this typeinfo. - #[rustc_std_internal_symbol] - #[allow(non_upper_case_globals)] - #[cfg(target_os = "emscripten")] - static rust_eh_catch_typeinfo: [usize; 2] = [0; 2]; -} diff --git a/library/panic_unwind/Cargo.toml b/library/panic_unwind/Cargo.toml index 67fc919c42c2b..72c1041b46795 100644 --- a/library/panic_unwind/Cargo.toml +++ b/library/panic_unwind/Cargo.toml @@ -18,7 +18,3 @@ unwind = { path = "../unwind" } [target.'cfg(not(all(windows, target_env = "msvc")))'.dependencies] libc = { version = "0.2", default-features = false } - -[lints.rust.unexpected_cfgs] -level = "warn" -check-cfg = ['cfg(emscripten_wasm_eh)'] diff --git a/library/panic_unwind/src/dummy.rs b/library/panic_unwind/src/dummy.rs index a0d6876691833..3ba0bec71b7bf 100644 --- a/library/panic_unwind/src/dummy.rs +++ b/library/panic_unwind/src/dummy.rs @@ -4,12 +4,17 @@ use alloc::boxed::Box; use core::any::Any; -use core::intrinsics; + +unsafe extern "Rust" { + // This is defined in std::rt + #[rustc_std_internal_symbol] + safe fn __rust_abort() -> !; +} pub(crate) unsafe fn cleanup(_ptr: *mut u8) -> Box { - intrinsics::abort() + __rust_abort() } pub(crate) unsafe fn panic(_data: Box) -> u32 { - intrinsics::abort() + __rust_abort() } diff --git a/library/panic_unwind/src/emcc.rs b/library/panic_unwind/src/emcc.rs deleted file mode 100644 index bad795a019c9a..0000000000000 --- a/library/panic_unwind/src/emcc.rs +++ /dev/null @@ -1,135 +0,0 @@ -//! Unwinding for *emscripten* target. -//! -//! Whereas Rust's usual unwinding implementation for Unix platforms -//! calls into the libunwind APIs directly, on Emscripten we instead -//! call into the C++ unwinding APIs. This is just an expedience since -//! Emscripten's runtime always implements those APIs and does not -//! implement libunwind. - -use alloc::boxed::Box; -use core::any::Any; -use core::sync::atomic::{AtomicBool, Ordering}; -use core::{intrinsics, ptr}; - -use unwind as uw; - -// This matches the layout of std::type_info in C++ -#[repr(C)] -struct TypeInfo { - vtable: *const usize, - name: *const u8, -} -unsafe impl Sync for TypeInfo {} - -unsafe extern "C" { - // The leading `\x01` byte here is actually a magical signal to LLVM to - // *not* apply any other mangling like prefixing with a `_` character. - // - // This symbol is the vtable used by C++'s `std::type_info`. Objects of type - // `std::type_info`, type descriptors, have a pointer to this table. Type - // descriptors are referenced by the C++ EH structures defined above and - // that we construct below. - // - // Note that the real size is larger than 3 usize, but we only need our - // vtable to point to the third element. - #[link_name = "\x01_ZTVN10__cxxabiv117__class_type_infoE"] - static CLASS_TYPE_INFO_VTABLE: [usize; 3]; -} - -// std::type_info for a rust_panic class -#[lang = "eh_catch_typeinfo"] -static EXCEPTION_TYPE_INFO: TypeInfo = TypeInfo { - // Normally we would use .as_ptr().add(2) but this doesn't work in a const context. - vtable: unsafe { &CLASS_TYPE_INFO_VTABLE[2] }, - // This intentionally doesn't use the normal name mangling scheme because - // we don't want C++ to be able to produce or catch Rust panics. - name: b"rust_panic\0".as_ptr(), -}; - -// NOTE(nbdd0121): The `canary` field is part of stable ABI. -#[repr(C)] -struct Exception { - // See `gcc.rs` on why this is present. We already have a static here so just use it. - canary: *const TypeInfo, - - // This is necessary because C++ code can capture our exception with - // std::exception_ptr and rethrow it multiple times, possibly even in - // another thread. - caught: AtomicBool, - - // This needs to be an Option because the object's lifetime follows C++ - // semantics: when catch_unwind moves the Box out of the exception it must - // still leave the exception object in a valid state because its destructor - // is still going to be called by __cxa_end_catch. - data: Option>, -} - -pub(crate) unsafe fn cleanup(ptr: *mut u8) -> Box { - // intrinsics::try actually gives us a pointer to this structure. - #[repr(C)] - struct CatchData { - ptr: *mut u8, - is_rust_panic: bool, - } - unsafe { - let catch_data = &*(ptr as *mut CatchData); - - let adjusted_ptr = __cxa_begin_catch(catch_data.ptr as *mut libc::c_void) as *mut Exception; - if !catch_data.is_rust_panic { - super::__rust_foreign_exception(); - } - - let canary = (&raw const (*adjusted_ptr).canary).read(); - if !ptr::eq(canary, &EXCEPTION_TYPE_INFO) { - super::__rust_foreign_exception(); - } - - let was_caught = (*adjusted_ptr).caught.swap(true, Ordering::Relaxed); - if was_caught { - // Since cleanup() isn't allowed to panic, we just abort instead. - intrinsics::abort(); - } - let out = (*adjusted_ptr).data.take().unwrap(); - __cxa_end_catch(); - out - } -} - -pub(crate) unsafe fn panic(data: Box) -> u32 { - unsafe { - let exception = __cxa_allocate_exception(size_of::()) as *mut Exception; - if exception.is_null() { - return uw::_URC_FATAL_PHASE1_ERROR as u32; - } - ptr::write( - exception, - Exception { - canary: &EXCEPTION_TYPE_INFO, - caught: AtomicBool::new(false), - data: Some(data), - }, - ); - __cxa_throw(exception as *mut _, &EXCEPTION_TYPE_INFO, exception_cleanup); - } -} - -extern "C" fn exception_cleanup(ptr: *mut libc::c_void) -> *mut libc::c_void { - unsafe { - if let Some(b) = (ptr as *mut Exception).read().data { - drop(b); - super::__rust_drop_panic(); - } - ptr - } -} - -unsafe extern "C" { - fn __cxa_allocate_exception(thrown_size: libc::size_t) -> *mut libc::c_void; - fn __cxa_begin_catch(thrown_exception: *mut libc::c_void) -> *mut libc::c_void; - fn __cxa_end_catch(); - fn __cxa_throw( - thrown_exception: *mut libc::c_void, - tinfo: *const TypeInfo, - dest: extern "C" fn(*mut libc::c_void) -> *mut libc::c_void, - ) -> !; -} diff --git a/library/panic_unwind/src/gcc.rs b/library/panic_unwind/src/gcc.rs index 5f95870069dc5..adcbe5170623c 100644 --- a/library/panic_unwind/src/gcc.rs +++ b/library/panic_unwind/src/gcc.rs @@ -63,7 +63,7 @@ pub(crate) unsafe fn panic(data: Box) -> u32 { _uwe: uw::_Unwind_Exception { exception_class: RUST_EXCEPTION_CLASS, exception_cleanup: Some(exception_cleanup), - private: [core::ptr::null(); uw::unwinder_private_data_size], + private: [core::ptr::null(); _], }, canary: &CANARY, cause: data, diff --git a/library/panic_unwind/src/hermit.rs b/library/panic_unwind/src/hermit.rs deleted file mode 100644 index b36d1a019fddb..0000000000000 --- a/library/panic_unwind/src/hermit.rs +++ /dev/null @@ -1,20 +0,0 @@ -//! Unwinding for *hermit* target. -//! -//! Right now we don't support this, so this is just stubs. - -use alloc::boxed::Box; -use core::any::Any; - -unsafe extern "Rust" { - // This is defined in std::rt - #[rustc_std_internal_symbol] - safe fn __rust_abort() -> !; -} - -pub(crate) unsafe fn cleanup(_ptr: *mut u8) -> Box { - __rust_abort() -} - -pub(crate) unsafe fn panic(_data: Box) -> u32 { - __rust_abort() -} diff --git a/library/panic_unwind/src/lib.rs b/library/panic_unwind/src/lib.rs index 1be19913f260f..3f409be039567 100644 --- a/library/panic_unwind/src/lib.rs +++ b/library/panic_unwind/src/lib.rs @@ -2,11 +2,12 @@ //! //! This crate is an implementation of panics in Rust using "most native" stack //! unwinding mechanism of the platform this is being compiled for. This -//! essentially gets categorized into three buckets currently: +//! essentially gets categorized into four buckets currently: //! -//! 1. MSVC targets use SEH in the `seh.rs` file. -//! 2. Emscripten uses C++ exceptions in the `emcc.rs` file. -//! 3. All other targets use libunwind/libgcc in the `gcc.rs` file. +//! 1. When running inside miri, MSVC targets use Miri intrinsics in the `miri.rs` file. +//! 2. MSVC targets use SEH in the `seh.rs` file. +//! 3. Some targets use an aborting implementation in the `dummy.rs` or `hermit.rs` files. +//! 4. All other targets use libunwind/libgcc in the `gcc.rs` file. //! //! More documentation about each implementation can be found in the respective //! module. @@ -14,10 +15,7 @@ #![no_std] #![unstable(feature = "panic_unwind", issue = "32837")] #![doc(issue_tracker_base_url = "https://github.com/rust-lang/rust/issues/")] -#![feature(cfg_emscripten_wasm_eh)] -#![feature(cfg_select)] #![feature(core_intrinsics)] -#![feature(lang_items)] #![feature(panic_unwind)] #![feature(staged_api)] #![feature(std_internals)] @@ -25,6 +23,7 @@ #![panic_runtime] #![feature(panic_runtime)] #![allow(internal_features)] +#![allow(unused_features)] #![warn(unreachable_pub)] #![deny(unsafe_op_in_unsafe_fn)] @@ -33,19 +32,6 @@ use core::any::Any; use core::panic::PanicPayload; cfg_select! { - all(target_os = "emscripten", not(emscripten_wasm_eh)) => { - #[path = "emcc.rs"] - mod imp; - } - target_os = "hermit" => { - #[path = "hermit.rs"] - mod imp; - } - target_os = "l4re" => { - // L4Re is unix family but does not yet support unwinding. - #[path = "dummy.rs"] - mod imp; - } any( all(target_family = "windows", target_env = "gnu"), target_os = "psp", @@ -74,6 +60,7 @@ cfg_select! { // - os=none ("bare metal" targets) // - os=uefi // - os=espidf + // - os=hermit // - nvptx64-nvidia-cuda // - arch=avr #[path = "dummy.rs"] diff --git a/library/panic_unwind/src/seh.rs b/library/panic_unwind/src/seh.rs index 257916c4d5cdc..ad99fb8c5b5f5 100644 --- a/library/panic_unwind/src/seh.rs +++ b/library/panic_unwind/src/seh.rs @@ -290,12 +290,12 @@ macro_rules! define_cleanup { } } cfg_select! { - target_arch = "x86" => { - define_cleanup!("thiscall" "thiscall-unwind"); - } - _ => { - define_cleanup!("C" "C-unwind"); - } + target_arch = "x86" => { + define_cleanup!("thiscall" "thiscall-unwind"); + } + _ => { + define_cleanup!("C" "C-unwind"); + } } pub(crate) unsafe fn panic(data: Box) -> u32 { @@ -337,24 +337,24 @@ unsafe fn throw_exception(data: Option>) -> ! { // express more operations in statics (and we may never be able to). unsafe { #[allow(function_casts_as_integer)] - atomic_store::<_, { AtomicOrdering::SeqCst }>( + atomic_store::<_, { AtomicOrdering::SeqCst }, /* VOLATILE */ false>( (&raw mut THROW_INFO.pmfnUnwind).cast(), ptr_t::new(exception_cleanup as *mut u8).raw(), ); - atomic_store::<_, { AtomicOrdering::SeqCst }>( + atomic_store::<_, { AtomicOrdering::SeqCst }, /* VOLATILE */ false>( (&raw mut THROW_INFO.pCatchableTypeArray).cast(), ptr_t::new((&raw mut CATCHABLE_TYPE_ARRAY).cast()).raw(), ); - atomic_store::<_, { AtomicOrdering::SeqCst }>( + atomic_store::<_, { AtomicOrdering::SeqCst }, /* VOLATILE */ false>( (&raw mut CATCHABLE_TYPE_ARRAY.arrayOfCatchableTypes[0]).cast(), ptr_t::new((&raw mut CATCHABLE_TYPE).cast()).raw(), ); - atomic_store::<_, { AtomicOrdering::SeqCst }>( + atomic_store::<_, { AtomicOrdering::SeqCst }, /* VOLATILE */ false>( (&raw mut CATCHABLE_TYPE.pType).cast(), ptr_t::new((&raw mut TYPE_DESCRIPTOR).cast()).raw(), ); #[allow(function_casts_as_integer)] - atomic_store::<_, { AtomicOrdering::SeqCst }>( + atomic_store::<_, { AtomicOrdering::SeqCst }, /* VOLATILE */ false>( (&raw mut CATCHABLE_TYPE.copyFunction).cast(), ptr_t::new(exception_copy as *mut u8).raw(), ); diff --git a/library/portable-simd/.github/PULL_REQUEST_TEMPLATE.md b/library/portable-simd/.github/PULL_REQUEST_TEMPLATE.md index 31422b7934501..5d354305e56de 100644 --- a/library/portable-simd/.github/PULL_REQUEST_TEMPLATE.md +++ b/library/portable-simd/.github/PULL_REQUEST_TEMPLATE.md @@ -10,7 +10,7 @@ For a given vector math operation on TxN, please add tests for interactions with - [ ] 0 -For a given vector math operation on TxN where T is a float, please add tests for test interactions with: +For a given vector math operation on TxN where T is a float, please add tests for interactions with: - [ ] a really large number, larger than the mantissa - [ ] a really small "subnormal" number - [ ] NaN diff --git a/library/portable-simd/.github/workflows/ci.yml b/library/portable-simd/.github/workflows/ci.yml index de7efa3552836..759a5337bd826 100644 --- a/library/portable-simd/.github/workflows/ci.yml +++ b/library/portable-simd/.github/workflows/ci.yml @@ -59,7 +59,7 @@ jobs: strategy: fail-fast: false matrix: - target: [x86_64-pc-windows-msvc, i686-pc-windows-msvc, x86_64-unknown-linux-gnu] + target: [x86_64-pc-windows-msvc, x86_64-pc-windows-gnu, i686-pc-windows-msvc, x86_64-unknown-linux-gnu] # `default` means we use the default target config for the target, # `native` means we run with `-Ctarget-cpu=native`, and anything else is # an arg to `-Ctarget-feature` @@ -73,6 +73,7 @@ jobs: # Populate the `matrix.os` field - { target: x86_64-unknown-linux-gnu, os: ubuntu-latest } - { target: x86_64-pc-windows-msvc, os: windows-latest } + - { target: x86_64-pc-windows-gnu, os: windows-latest } - { target: i686-pc-windows-msvc, os: windows-latest } # Annoyingly, the x86_64-unknown-linux-gnu runner *almost* always has diff --git a/library/portable-simd/Cargo.lock b/library/portable-simd/Cargo.lock index 5a5f0d8907ae3..80a0e1999cfaf 100644 --- a/library/portable-simd/Cargo.lock +++ b/library/portable-simd/Cargo.lock @@ -2,6 +2,17 @@ # It is not intended for manual editing. version = 4 +[[package]] +name = "async-trait" +version = "0.1.89" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9035ad2d096bed7955a320ee7e2230574d28fd3c3a0f186cbea1ff3c7eed5dbb" +dependencies = [ + "proc-macro2", + "quote", + "syn", +] + [[package]] name = "autocfg" version = "1.5.0" @@ -10,41 +21,43 @@ checksum = "c08606f8c3cbf4ce6ec8e28fb0014a2c086708fe954eaa885384a6165172e7e8" [[package]] name = "bitflags" -version = "1.3.2" +version = "2.11.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "bef38d45163c2f1dde094a7dfd33ccf595c92905c8f8f4fdc18d06fb1037718a" +checksum = "843867be96c8daad0d758b57df9392b6d8d271134fce549de6ce169ff98a92af" [[package]] name = "bumpalo" -version = "3.19.0" +version = "3.20.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "46c5e41b57b8bba42a04676d81cb89e9ee8e859a1a66f80a5a72e1cb76b34d43" +checksum = "5d20789868f4b01b2f2caec9f5c4e0213b41e3e5702a50157d699ae31ced2fcb" [[package]] -name = "byteorder" -version = "1.5.0" +name = "cast" +version = "0.3.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1fd0f2584146f6f2ef48085050886acf353beff7305ebd1ae69500e27c67f64b" +checksum = "37b2a672a2cb129a2e41c10b1224bb368f9f37a2b16b612598138befd7b37eb5" [[package]] name = "cc" -version = "1.2.33" +version = "1.2.58" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3ee0f8803222ba5a7e2777dd72ca451868909b1ac410621b676adf07280e9b5f" +checksum = "e1e928d4b69e3077709075a938a05ffbedfa53a84c8f766efbf8220bb1ff60e1" dependencies = [ + "find-msvc-tools", "shlex", ] [[package]] name = "cfg-if" -version = "1.0.1" +version = "1.0.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9555578bc9e57714c812a1f84e4fc5b4d21fcb063490c624de019f7464c91268" +checksum = "9330f8b2ff13f34540b44e946ef35111825727b38d33286ef986142615121801" [[package]] name = "core_simd" version = "0.1.0" dependencies = [ + "getrandom", "proptest", "std_float", "test_helpers", @@ -53,40 +66,104 @@ dependencies = [ ] [[package]] -name = "float-cmp" -version = "0.10.0" +name = "find-msvc-tools" +version = "0.1.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5baebc0774151f905a1a2cc41989300b1e6fbb29aff0ceffa1064fdd3088d582" + +[[package]] +name = "futures-core" +version = "0.3.32" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7e3450815272ef58cec6d564423f6e755e25379b217b0bc688e295ba24df6b1d" + +[[package]] +name = "futures-task" +version = "0.3.32" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "037711b3d59c33004d3856fbdc83b99d4ff37a24768fa1be9ce3538a1cde4393" + +[[package]] +name = "futures-util" +version = "0.3.32" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "389ca41296e6190b48053de0321d02a77f32f8a5d2461dd38762c0593805c6d6" +dependencies = [ + "futures-core", + "futures-task", + "pin-project-lite", + "slab", +] + +[[package]] +name = "getrandom" +version = "0.3.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b09cf3155332e944990140d967ff5eceb70df778b34f77d8075db46e4704e6d8" +checksum = "899def5c37c4fd7b2664648c28120ecec138e4d395b459e5ca34f9cce2dd77fd" dependencies = [ - "num-traits", + "cfg-if", + "js-sys", + "libc", + "r-efi", + "wasip2", + "wasm-bindgen", ] +[[package]] +name = "itoa" +version = "1.0.18" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8f42a60cbdf9a97f5d2305f08a87dc4e09308d1276d28c869c684d7777685682" + [[package]] name = "js-sys" -version = "0.3.77" +version = "0.3.92" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1cfaf33c695fc6e08064efbc1f72ec937429614f25eef83af942d0e227c3a28f" +checksum = "cc4c90f45aa2e6eacbe8645f77fdea542ac97a494bcd117a67df9ff4d611f995" dependencies = [ + "cfg-if", + "futures-util", "once_cell", "wasm-bindgen", ] [[package]] -name = "log" -version = "0.4.27" +name = "libc" +version = "0.2.183" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b5b646652bf6661599e1da8901b3b9522896f01e736bad5f723fe7a3a27f899d" + +[[package]] +name = "libm" +version = "0.2.16" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "13dc2df351e3202783a1fe0d44375f7295ffb4049267b0f3018346dc122a1d94" +checksum = "b6d2cec3eae94f9f509c767b45932f1ada8350c4bdb85af2fcab4a3c14807981" + +[[package]] +name = "memchr" +version = "2.8.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f8ca58f447f06ed17d5fc4043ce1b10dd205e060fb3ce5b979b8ed8e59ff3f79" [[package]] name = "minicov" -version = "0.3.7" +version = "0.3.8" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f27fe9f1cc3c22e1687f9446c2083c4c5fc7f0bcf1c7a86bdbded14985895b4b" +checksum = "4869b6a491569605d66d3952bcdf03df789e5b536e5f0cf7758a7f08a55ae24d" dependencies = [ "cc", "walkdir", ] +[[package]] +name = "nu-ansi-term" +version = "0.50.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7957b9740744892f114936ab4a57b3f487491bbeafaf8083688b16841a4240e5" +dependencies = [ + "windows-sys", +] + [[package]] name = "num-traits" version = "0.2.19" @@ -94,13 +171,26 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "071dfc062690e90b734c0b2273ce72ad0ffa95f0c74596bc250dcfd960262841" dependencies = [ "autocfg", + "libm", ] [[package]] name = "once_cell" -version = "1.21.3" +version = "1.21.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "42f5e15c9953c5e4ccceeb2e7382a716482c34515315f7b03532b8b4e8393d2d" +checksum = "9f7c3e4beb33f85d45ae3e3a1792185706c8e16d043238c593331cc7cd313b50" + +[[package]] +name = "oorandom" +version = "11.1.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d6790f58c7ff633d8771f42965289203411a5e5c68388703c06e14f24770b41e" + +[[package]] +name = "pin-project-lite" +version = "0.2.17" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "a89322df9ebe1c1578d689c92318e070967d1042b512afbe49518723f4e6d5cd" [[package]] name = "ppv-lite86" @@ -113,52 +203,58 @@ dependencies = [ [[package]] name = "proc-macro2" -version = "1.0.101" +version = "1.0.106" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "89ae43fd86e4158d6db51ad8e2b80f313af9cc74f5c0e03ccb87de09998732de" +checksum = "8fd00f0bb2e90d81d1044c2b32617f68fcb9fa3bb7640c23e9c748e53fb30934" dependencies = [ "unicode-ident", ] [[package]] name = "proptest" -version = "0.10.1" +version = "1.11.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "12e6c80c1139113c28ee4670dc50cc42915228b51f56a9e407f0ec60f966646f" +checksum = "4b45fcc2344c680f5025fe57779faef368840d0bd1f42f216291f0dc4ace4744" dependencies = [ "bitflags", - "byteorder", "num-traits", "rand", "rand_chacha", "rand_xorshift", + "regex-syntax", + "unarray", ] [[package]] name = "quote" -version = "1.0.40" +version = "1.0.45" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1885c039570dc00dcb4ff087a89e185fd56bae234ddc7f056a945bf36467248d" +checksum = "41f2619966050689382d2b44f664f4bc593e129785a36d6ee376ddf37259b924" dependencies = [ "proc-macro2", ] +[[package]] +name = "r-efi" +version = "5.3.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "69cdb34c158ceb288df11e18b4bd39de994f6657d83847bdffdbd7f346754b0f" + [[package]] name = "rand" -version = "0.7.3" +version = "0.9.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "6a6b1679d49b24bbfe0c803429aa1874472f50d9b363131f0e89fc356b544d03" +checksum = "6db2770f06117d490610c7488547d543617b21bfa07796d7a12f6f1bd53850d1" dependencies = [ "rand_chacha", "rand_core", - "rand_hc", ] [[package]] name = "rand_chacha" -version = "0.2.2" +version = "0.9.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f4c8ed856279c9737206bf725bf36935d8666ead7aa69b52be55af369d193402" +checksum = "d3022b5f1df60f26e1ffddd6c66e8aa15de382ae63b3a0c1bfc0e4d3e3f325cb" dependencies = [ "ppv-lite86", "rand_core", @@ -166,28 +262,28 @@ dependencies = [ [[package]] name = "rand_core" -version = "0.5.1" +version = "0.9.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "90bde5296fc891b0cef12a6d03ddccc162ce7b2aff54160af9338f8d40df6d19" - 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"float-cmp", "proptest", ] +[[package]] +name = "unarray" +version = "0.1.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "eaea85b334db583fe3274d12b4cd1880032beab409c0d774be044d4480ab9a94" + [[package]] name = "unicode-ident" -version = "1.0.18" +version = "1.0.24" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5a5f39404a5da50712a4c1eecf25e90dd62b613502b7e925fd4e4d19b5c96512" +checksum = "e6e4313cd5fcd3dad5cafa179702e2b244f760991f45397d14d4ebf38247da75" [[package]] name = "walkdir" @@ -255,49 +405,42 @@ dependencies = [ ] [[package]] -name = "wasm-bindgen" -version = "0.2.100" +name = "wasip2" +version = "1.0.2+wasi-0.2.9" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1edc8929d7499fc4e8f0be2262a241556cfc54a0bea223790e71446f2aab1ef5" +checksum = "9517f9239f02c069db75e65f174b3da828fe5f5b945c4dd26bd25d89c03ebcf5" dependencies = [ - "cfg-if", - "once_cell", - "rustversion", - "wasm-bindgen-macro", + "wit-bindgen", ] [[package]] -name = "wasm-bindgen-backend" -version = "0.2.100" +name = "wasm-bindgen" +version = "0.2.115" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2f0a0651a5c2bc21487bde11ee802ccaf4c51935d0d3d42a6101f98161700bc6" +checksum = "6523d69017b7633e396a89c5efab138161ed5aafcbc8d3e5c5a42ae38f50495a" dependencies = [ - "bumpalo", - "log", - "proc-macro2", - "quote", - "syn", + "cfg-if", + "once_cell", + "rustversion", + "wasm-bindgen-macro", "wasm-bindgen-shared", ] [[package]] name = "wasm-bindgen-futures" -version = "0.4.50" +version = "0.4.65" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "555d470ec0bc3bb57890405e5d4322cc9ea83cebb085523ced7be4144dac1e61" +checksum = "2d1faf851e778dfa54db7cd438b70758eba9755cb47403f3496edd7c8fc212f0" dependencies = [ - "cfg-if", "js-sys", - "once_cell", "wasm-bindgen", - "web-sys", ] [[package]] name = "wasm-bindgen-macro" -version = "0.2.100" +version = "0.2.115" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7fe63fc6d09ed3792bd0897b314f53de8e16568c2b3f7982f468c0bf9bd0b407" +checksum = "4e3a6c758eb2f701ed3d052ff5737f5bfe6614326ea7f3bbac7156192dc32e67" dependencies = [ "quote", "wasm-bindgen-macro-support", @@ -305,44 +448,53 @@ dependencies = [ [[package]] name = "wasm-bindgen-macro-support" -version = "0.2.100" +version = "0.2.115" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "8ae87ea40c9f689fc23f209965b6fb8a99ad69aeeb0231408be24920604395de" +checksum = "921de2737904886b52bcbb237301552d05969a6f9c40d261eb0533c8b055fedf" dependencies = [ + "bumpalo", "proc-macro2", "quote", "syn", - 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"windows_aarch64_gnullvm", - "windows_aarch64_msvc", - "windows_i686_gnu", - "windows_i686_gnullvm", - "windows_i686_msvc", - "windows_x86_64_gnu", - "windows_x86_64_gnullvm", - "windows_x86_64_msvc", + "windows-link", ] [[package]] -name = "windows_aarch64_gnullvm" -version = "0.52.6" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "32a4622180e7a0ec044bb555404c800bc9fd9ec262ec147edd5989ccd0c02cd3" - -[[package]] -name = "windows_aarch64_msvc" -version = "0.52.6" +name = "wit-bindgen" +version = "0.51.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "09ec2a7bb152e2252b53fa7803150007879548bc709c039df7627cabbd05d469" - -[[package]] -name = "windows_i686_gnu" -version = "0.52.6" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "8e9b5ad5ab802e97eb8e295ac6720e509ee4c243f69d781394014ebfe8bbfa0b" - -[[package]] -name = "windows_i686_gnullvm" -version = "0.52.6" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "0eee52d38c090b3caa76c563b86c3a4bd71ef1a819287c19d586d7334ae8ed66" - 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If you know that you're targeting a specific CPU you can instead use the [target-cpu](https://rust-lang.github.io/packed_simd/perf-guide/target-feature/rustflags.html#target-cpu) flag and the compiler will enable the correct set of features for that CPU. diff --git a/library/portable-simd/crates/core_simd/Cargo.toml b/library/portable-simd/crates/core_simd/Cargo.toml index 537ce459c07cd..05fc63a6a29d3 100644 --- a/library/portable-simd/crates/core_simd/Cargo.toml +++ b/library/portable-simd/crates/core_simd/Cargo.toml @@ -18,12 +18,24 @@ wasm-bindgen = "0.2" wasm-bindgen-test = "0.3" [dev-dependencies.proptest] -version = "0.10" +workspace = true + +# Enable the `wasm_js` feature so that getrandom works on wasm32-unknown-unknown. +[dev-dependencies.getrandom] +version = "0.3.4" default-features = false -features = ["alloc"] +features = ["wasm_js"] [dev-dependencies.test_helpers] path = "../test_helpers" [dev-dependencies] std_float = { path = "../std_float/", features = ["as_crate"] } + +[lints.rust.unexpected_cfgs] +level = "warn" +check-cfg = [ + # Internal features aren't marked known config by default, we use these to + # gate tests. + 'cfg(target_has_reliable_f16_math)', +] diff --git a/library/portable-simd/crates/core_simd/src/alias.rs b/library/portable-simd/crates/core_simd/src/alias.rs index 23f121c46197c..6dcfcb660c26a 100644 --- a/library/portable-simd/crates/core_simd/src/alias.rs +++ b/library/portable-simd/crates/core_simd/src/alias.rs @@ -153,6 +153,16 @@ alias! { usizex64 64 } + f16 = { + f16x1 1 + f16x2 2 + f16x4 4 + f16x8 8 + f16x16 16 + f16x32 32 + f16x64 64 + } + f32 = { f32x1 1 f32x2 2 diff --git a/library/portable-simd/crates/core_simd/src/cast.rs b/library/portable-simd/crates/core_simd/src/cast.rs index 1c3592f807578..81187ae68ad19 100644 --- a/library/portable-simd/crates/core_simd/src/cast.rs +++ b/library/portable-simd/crates/core_simd/src/cast.rs @@ -1,51 +1,35 @@ use crate::simd::SimdElement; -mod sealed { - /// Cast vector elements to other types. - /// - /// # Safety - /// Implementing this trait asserts that the type is a valid vector element for the `simd_cast` - /// or `simd_as` intrinsics. - pub unsafe trait Sealed {} -} -use sealed::Sealed; - /// Supporting trait for `Simd::cast`. Typically doesn't need to be used directly. -pub trait SimdCast: Sealed + SimdElement {} +/// +/// # Safety +/// Implementing this trait asserts that the type is a valid vector element for the `simd_cast` or +/// `simd_as` intrinsics. +pub impl(self) unsafe trait SimdCast: SimdElement {} // Safety: primitive number types can be cast to other primitive number types -unsafe impl Sealed for i8 {} -impl SimdCast for i8 {} +unsafe impl SimdCast for i8 {} +// Safety: primitive number types can be cast to other primitive number types +unsafe impl SimdCast for i16 {} // Safety: primitive number types can be cast to other primitive number types -unsafe impl Sealed for i16 {} -impl SimdCast for i16 {} +unsafe impl SimdCast for i32 {} // Safety: primitive number types can be cast to other primitive number types -unsafe impl Sealed for i32 {} -impl SimdCast for i32 {} +unsafe impl SimdCast for i64 {} // Safety: primitive number types can be cast to other primitive number types -unsafe impl Sealed for i64 {} -impl SimdCast for i64 {} +unsafe impl SimdCast for isize {} // Safety: primitive number types can be cast to other primitive number types -unsafe impl Sealed for isize {} -impl SimdCast for isize {} +unsafe impl SimdCast for u8 {} // Safety: primitive number types can be cast to other primitive number types -unsafe impl Sealed for u8 {} -impl SimdCast for u8 {} +unsafe impl SimdCast for u16 {} // Safety: primitive number types can be cast to other primitive number types -unsafe impl Sealed for u16 {} -impl SimdCast for u16 {} +unsafe impl SimdCast for u32 {} // Safety: primitive number types can be cast to other primitive number types -unsafe impl Sealed for u32 {} -impl SimdCast for u32 {} +unsafe impl SimdCast for u64 {} // Safety: primitive number types can be cast to other primitive number types -unsafe impl Sealed for u64 {} -impl SimdCast for u64 {} +unsafe impl SimdCast for usize {} // Safety: primitive number types can be cast to other primitive number types -unsafe impl Sealed for usize {} -impl SimdCast for usize {} +unsafe impl SimdCast for f16 {} // Safety: primitive number types can be cast to other primitive number types -unsafe impl Sealed for f32 {} -impl SimdCast for f32 {} +unsafe impl SimdCast for f32 {} // Safety: primitive number types can be cast to other primitive number types -unsafe impl Sealed for f64 {} -impl SimdCast for f64 {} +unsafe impl SimdCast for f64 {} diff --git a/library/portable-simd/crates/core_simd/src/lib.rs b/library/portable-simd/crates/core_simd/src/lib.rs index fe26d99b9194c..e59b286f780da 100644 --- a/library/portable-simd/crates/core_simd/src/lib.rs +++ b/library/portable-simd/crates/core_simd/src/lib.rs @@ -1,17 +1,17 @@ #![no_std] #![feature( - const_eval_select, convert_float_to_int, + f16, core_intrinsics, decl_macro, - intra_doc_pointers, + impl_restriction, repr_simd, - simd_ffi, staged_api, prelude_import, ptr_metadata, rustc_attrs )] +#![cfg_attr(doc, feature(intra_doc_pointers))] #![cfg_attr( all( any(target_arch = "aarch64", target_arch = "arm64ec", target_arch = "arm",), @@ -31,6 +31,7 @@ any(target_arch = "powerpc", target_arch = "powerpc64"), feature(stdarch_powerpc) )] +#![cfg_attr(target_arch = "hexagon", feature(stdarch_hexagon))] #![warn(missing_docs, clippy::missing_inline_in_public_items)] // basically all items, really #![deny( unsafe_op_in_unsafe_fn, diff --git a/library/portable-simd/crates/core_simd/src/masks.rs b/library/portable-simd/crates/core_simd/src/masks.rs index 3e2209556b66b..01e88a0dc3088 100644 --- a/library/portable-simd/crates/core_simd/src/masks.rs +++ b/library/portable-simd/crates/core_simd/src/masks.rs @@ -29,7 +29,7 @@ macro_rules! impl_fix_endianness { impl_fix_endianness! { u8, u16, u32, u64 } -mod sealed { +mod private_methods { use super::*; /// Not only does this seal the `MaskElement` trait, but these functions prevent other traits @@ -38,7 +38,7 @@ mod sealed { /// For example, `eq` could be provided by requiring `MaskElement: PartialEq`, but that would /// prevent us from ever removing that bound, or from implementing `MaskElement` on /// non-`PartialEq` types in the future. - pub trait Sealed { + pub impl(super) trait PrivateMethods { fn valid(values: Simd) -> bool where Self: SimdElement; @@ -55,17 +55,20 @@ mod sealed { const FALSE: Self; } } -use sealed::Sealed; +use private_methods::PrivateMethods; /// Marker trait for types that may be used as SIMD mask elements. /// /// # Safety /// Type must be a signed integer. -pub unsafe trait MaskElement: SimdElement + SimdCast + Sealed {} +pub impl(self) unsafe trait MaskElement: + SimdElement + SimdCast + PrivateMethods +{ +} macro_rules! impl_element { { $ty:ty, $unsigned:ty } => { - impl Sealed for $ty { + impl PrivateMethods for $ty { #[inline] fn valid(value: Simd) -> bool { @@ -196,7 +199,7 @@ where pub unsafe fn from_simd_unchecked(value: Simd) -> Self { // Safety: the caller must confirm this invariant unsafe { - core::intrinsics::assume(::valid(value)); + core::intrinsics::assume(::valid(value)); } Self(value) } @@ -361,8 +364,7 @@ where pub fn first_set(self) -> Option { // If bitmasks are efficient, using them is better if cfg!(target_feature = "sse") && N <= 64 { - let tz = self.to_bitmask().trailing_zeros(); - return if tz == 64 { None } else { Some(tz as usize) }; + return self.to_bitmask().lowest_one().map(|i| i as usize); } // To find the first set index: @@ -371,22 +373,20 @@ where // * perform _unsigned_ reduce-min // * check if the result is -1 or an index - let index = Simd::from_array( - const { - let mut index = [0; N]; - let mut i = 0; - while i < N { - index[i] = i; - i += 1; - } - index - }, - ); + let index: Simd = const { + let mut index = [0; N]; + let mut i = 0; + while i < N { + index[i] = i; + i += 1; + } + // Safety: the input and output are integer vectors + unsafe { core::intrinsics::simd::simd_cast(Simd::from_array(index)) } + }; // Safety: the input and output are integer vectors - let index: Simd = unsafe { core::intrinsics::simd::simd_cast(index) }; - - let masked_index = self.select(index, Self::splat(true).to_simd()); + let masked_index: Simd = + unsafe { core::intrinsics::simd::simd_or((!self).to_simd(), index) }; // Safety: the input and output are integer vectors let masked_index: Simd = @@ -402,7 +402,75 @@ where if min_index.eq(T::TRUE) { None } else { - Some(min_index.to_usize()) + let min_index = min_index.to_usize(); + + // Allow eliminating bounds checks when using the index + // Safety: the index can't exceed the number of elements in the vector + unsafe { + core::hint::assert_unchecked(min_index < N); + } + + Some(min_index) + } + } + + /// Finds the index of the last set element. + /// + /// ``` + /// # #![feature(portable_simd)] + /// # #[cfg(feature = "as_crate")] use core_simd::simd; + /// # #[cfg(not(feature = "as_crate"))] use core::simd; + /// # use simd::mask32x8; + /// assert_eq!(mask32x8::splat(false).last_set(), None); + /// assert_eq!(mask32x8::splat(true).last_set(), Some(7)); + /// + /// let mask = mask32x8::from_array([false, true, false, false, true, false, true, false]); + /// assert_eq!(mask.last_set(), Some(6)); + /// ``` + #[inline] + #[must_use = "method returns the index and does not mutate the original value"] + pub fn last_set(self) -> Option { + // If bitmasks are efficient, using them is better + if cfg!(target_feature = "sse") && N <= 64 { + return self.to_bitmask().highest_one().map(|i| i as usize); + } + + // To find the first set index: + // * create a vector 0..N + // * replace unset mask elements in that vector with -1 + // * perform _signed_ reduce-max + // * check if the result is -1 or an index + + let index: Simd = const { + let mut index = [0; N]; + let mut i = 0; + while i < N { + index[i] = i; + i += 1; + } + // Safety: the input and output are integer vectors + unsafe { core::intrinsics::simd::simd_cast(Simd::from_array(index)) } + }; + + // Safety: the input and output are integer vectors + let masked_index: Simd = + unsafe { core::intrinsics::simd::simd_or((!self).to_simd(), index) }; + + // Safety: the input is an integer vector + let max_index: T = unsafe { core::intrinsics::simd::simd_reduce_max(masked_index) }; + + if max_index.eq(T::TRUE) { + None + } else { + let max_index = max_index.to_usize(); + + // Allow eliminating bounds checks when using the index + // Safety: the index can't exceed the number of elements in the vector + unsafe { + core::hint::assert_unchecked(max_index < N); + } + + Some(max_index) } } } diff --git a/library/portable-simd/crates/core_simd/src/ops.rs b/library/portable-simd/crates/core_simd/src/ops.rs index eb6601f734831..c0a06ed465129 100644 --- a/library/portable-simd/crates/core_simd/src/ops.rs +++ b/library/portable-simd/crates/core_simd/src/ops.rs @@ -245,7 +245,7 @@ for_base_ops! { // We don't need any special precautions here: // Floats always accept arithmetic ops, but may become NaN. for_base_ops! { - T = (f32, f64); + T = (f16, f32, f64); type Lhs = Simd; type Rhs = Simd; type Output = Self; diff --git a/library/portable-simd/crates/core_simd/src/ops/unary.rs b/library/portable-simd/crates/core_simd/src/ops/unary.rs index e1c06167f9790..af7aa8a823d99 100644 --- a/library/portable-simd/crates/core_simd/src/ops/unary.rs +++ b/library/portable-simd/crates/core_simd/src/ops/unary.rs @@ -19,6 +19,8 @@ macro_rules! neg { } neg! { + impl Neg for Simd + impl Neg for Simd impl Neg for Simd diff --git a/library/portable-simd/crates/core_simd/src/simd/cmp/eq.rs b/library/portable-simd/crates/core_simd/src/simd/cmp/eq.rs index d553d6c040c91..76836404cbc4e 100644 --- a/library/portable-simd/crates/core_simd/src/simd/cmp/eq.rs +++ b/library/portable-simd/crates/core_simd/src/simd/cmp/eq.rs @@ -42,7 +42,7 @@ macro_rules! impl_number { } } -impl_number! { f32, f64, u8, u16, u32, u64, usize, i8, i16, i32, i64, isize } +impl_number! { f16, f32, f64, u8, u16, u32, u64, usize, i8, i16, i32, i64, isize } macro_rules! impl_mask { { $($integer:ty),* } => { diff --git a/library/portable-simd/crates/core_simd/src/simd/cmp/ord.rs b/library/portable-simd/crates/core_simd/src/simd/cmp/ord.rs index 5672fbbf54caa..5a4e74c753b5a 100644 --- a/library/portable-simd/crates/core_simd/src/simd/cmp/ord.rs +++ b/library/portable-simd/crates/core_simd/src/simd/cmp/ord.rs @@ -144,7 +144,7 @@ macro_rules! impl_float { } } -impl_float! { f32, f64 } +impl_float! { f16, f32, f64 } macro_rules! impl_mask { { $($integer:ty),* } => { diff --git a/library/portable-simd/crates/core_simd/src/simd/num.rs b/library/portable-simd/crates/core_simd/src/simd/num.rs index 22a4802ec6cb5..d1186d3734b49 100644 --- a/library/portable-simd/crates/core_simd/src/simd/num.rs +++ b/library/portable-simd/crates/core_simd/src/simd/num.rs @@ -4,10 +4,6 @@ mod float; mod int; mod uint; -mod sealed { - pub trait Sealed {} -} - pub use float::*; pub use int::*; pub use uint::*; diff --git a/library/portable-simd/crates/core_simd/src/simd/num/float.rs b/library/portable-simd/crates/core_simd/src/simd/num/float.rs index efd7c2469512b..142740ad01560 100644 --- a/library/portable-simd/crates/core_simd/src/simd/num/float.rs +++ b/library/portable-simd/crates/core_simd/src/simd/num/float.rs @@ -1,11 +1,10 @@ -use super::sealed::Sealed; use crate::simd::{ Mask, Select, Simd, SimdCast, SimdElement, cmp::{SimdPartialEq, SimdPartialOrd}, }; /// Operations on SIMD vectors of floats. -pub trait SimdFloat: Copy + Sealed { +pub impl(self) trait SimdFloat: Copy { /// Mask type used for manipulating this SIMD vector type. type Mask; @@ -240,8 +239,6 @@ pub trait SimdFloat: Copy + Sealed { macro_rules! impl_trait { { $($ty:ty { bits: $bits_ty:ty, mask: $mask_ty:ty }),* } => { $( - impl Sealed for Simd<$ty, N> {} - impl SimdFloat for Simd<$ty, N> { type Mask = Mask<<$mask_ty as SimdElement>::Mask, N>; @@ -385,13 +382,13 @@ macro_rules! impl_trait { #[inline] fn simd_min(self, other: Self) -> Self { // Safety: `self` and `other` are float vectors - unsafe { core::intrinsics::simd::simd_fmin(self, other) } + unsafe { core::intrinsics::simd::simd_minimum_number_nsz(self, other) } } #[inline] fn simd_max(self, other: Self) -> Self { // Safety: `self` and `other` are floating point vectors - unsafe { core::intrinsics::simd::simd_fmax(self, other) } + unsafe { core::intrinsics::simd::simd_maximum_number_nsz(self, other) } } #[inline] @@ -430,18 +427,18 @@ macro_rules! impl_trait { #[inline] fn reduce_max(self) -> Self::Scalar { - // Safety: `self` is a float vector - unsafe { core::intrinsics::simd::simd_reduce_max(self) } + // LLVM has no intrinsic we can use here + // (https://github.com/llvm/llvm-project/issues/185827). + self.as_array().iter().copied().fold(Self::Scalar::NAN, Self::Scalar::max) } #[inline] fn reduce_min(self) -> Self::Scalar { - // Safety: `self` is a float vector - unsafe { core::intrinsics::simd::simd_reduce_min(self) } + self.as_array().iter().copied().fold(Self::Scalar::NAN, Self::Scalar::min) } } )* } } -impl_trait! { f32 { bits: u32, mask: i32 }, f64 { bits: u64, mask: i64 } } +impl_trait! { f16 { bits: u16, mask: i16 }, f32 { bits: u32, mask: i32 }, f64 { bits: u64, mask: i64 } } diff --git a/library/portable-simd/crates/core_simd/src/simd/num/int.rs b/library/portable-simd/crates/core_simd/src/simd/num/int.rs index eee54d3968808..ab556c14d6371 100644 --- a/library/portable-simd/crates/core_simd/src/simd/num/int.rs +++ b/library/portable-simd/crates/core_simd/src/simd/num/int.rs @@ -1,10 +1,9 @@ -use super::sealed::Sealed; use crate::simd::{ Mask, Select, Simd, SimdCast, SimdElement, cmp::SimdOrd, cmp::SimdPartialOrd, num::SimdUint, }; /// Operations on SIMD vectors of signed integers. -pub trait SimdInt: Copy + Sealed { +pub impl(self) trait SimdInt: Copy { /// Mask type used for manipulating this SIMD vector type. type Mask; @@ -241,8 +240,6 @@ pub trait SimdInt: Copy + Sealed { macro_rules! impl_trait { { $($ty:ident ($unsigned:ident)),* } => { $( - impl Sealed for Simd<$ty, N> {} - impl SimdInt for Simd<$ty, N> { type Mask = Mask<<$ty as SimdElement>::Mask, N>; type Scalar = $ty; diff --git a/library/portable-simd/crates/core_simd/src/simd/num/uint.rs b/library/portable-simd/crates/core_simd/src/simd/num/uint.rs index 606107a1f06f8..e4d383a0c21a5 100644 --- a/library/portable-simd/crates/core_simd/src/simd/num/uint.rs +++ b/library/portable-simd/crates/core_simd/src/simd/num/uint.rs @@ -1,8 +1,7 @@ -use super::sealed::Sealed; use crate::simd::{Simd, SimdCast, SimdElement, cmp::SimdOrd}; /// Operations on SIMD vectors of unsigned integers. -pub trait SimdUint: Copy + Sealed { +pub impl(self) trait SimdUint: Copy { /// Scalar type contained by this SIMD vector type. type Scalar; @@ -124,8 +123,6 @@ pub trait SimdUint: Copy + Sealed { macro_rules! impl_trait { { $($ty:ident ($signed:ident)),* } => { $( - impl Sealed for Simd<$ty, N> {} - impl SimdUint for Simd<$ty, N> { type Scalar = $ty; diff --git a/library/portable-simd/crates/core_simd/src/simd/prelude.rs b/library/portable-simd/crates/core_simd/src/simd/prelude.rs index e5d7a2aeb73df..51b8def3d6eed 100644 --- a/library/portable-simd/crates/core_simd/src/simd/prelude.rs +++ b/library/portable-simd/crates/core_simd/src/simd/prelude.rs @@ -7,13 +7,17 @@ #[doc(no_inline)] pub use super::{ - Mask, Simd, + Mask, Select, Simd, ToBytes, cmp::{SimdOrd, SimdPartialEq, SimdPartialOrd}, num::{SimdFloat, SimdInt, SimdUint}, ptr::{SimdConstPtr, SimdMutPtr}, simd_swizzle, }; +#[rustfmt::skip] +#[doc(no_inline)] +pub use super::{f16x1, f16x2, f16x4, f16x8, f16x16, f16x32, f16x64}; + #[rustfmt::skip] #[doc(no_inline)] pub use super::{f32x1, f32x2, f32x4, f32x8, f32x16, f32x32, f32x64}; diff --git a/library/portable-simd/crates/core_simd/src/simd/ptr.rs b/library/portable-simd/crates/core_simd/src/simd/ptr.rs index 3f8e666911853..bb5d9c870f448 100644 --- a/library/portable-simd/crates/core_simd/src/simd/ptr.rs +++ b/library/portable-simd/crates/core_simd/src/simd/ptr.rs @@ -3,9 +3,51 @@ mod const_ptr; mod mut_ptr; -mod sealed { - pub trait Sealed {} -} - pub use const_ptr::*; pub use mut_ptr::*; + +use crate::simd::Simd; + +/// Creates pointers with the given addresses and no provenance. +/// +/// Equivalent to calling [`core::ptr::without_provenance`] on each element. +#[inline] +pub fn without_provenance(addr: Simd) -> Simd<*const T, N> { + // An int-to-pointer transmute currently has exactly the intended semantics: it creates a + // pointer without provenance. Note that this is *not* a stable guarantee about transmute + // semantics, it relies on sysroot crates having special status. + // SAFETY: every valid integer is also a valid pointer (as long as you don't dereference that + // pointer). + unsafe { core::mem::transmute_copy(&addr) } +} + +/// Creates mutable pointers with the given addresses and no provenance. +/// +/// Equivalent to calling [`core::ptr::without_provenance_mut`] on each element. +#[inline] +pub fn without_provenance_mut(addr: Simd) -> Simd<*mut T, N> { + // An int-to-pointer transmute currently has exactly the intended semantics: it creates a + // pointer without provenance. Note that this is *not* a stable guarantee about transmute + // semantics, it relies on sysroot crates having special status. + // SAFETY: every valid integer is also a valid pointer (as long as you don't dereference that + // pointer). + unsafe { core::mem::transmute_copy(&addr) } +} + +/// Converts addresses back to pointers, picking up some previously "exposed" provenance. +/// +/// Equivalent to calling [`core::ptr::with_exposed_provenance`] on each element. +#[inline] +pub fn with_exposed_provenance(addr: Simd) -> Simd<*const T, N> { + // SAFETY: addr is a vector of usize + unsafe { core::intrinsics::simd::simd_with_exposed_provenance(addr) } +} + +/// Converts addresses back to mutable pointers, picking up some previously "exposed" provenance. +/// +/// Equivalent to calling [`core::ptr::with_exposed_provenance_mut`] on each element. +#[inline] +pub fn with_exposed_provenance_mut(addr: Simd) -> Simd<*mut T, N> { + // SAFETY: addr is a vector of usize + unsafe { core::intrinsics::simd::simd_with_exposed_provenance(addr) } +} diff --git a/library/portable-simd/crates/core_simd/src/simd/ptr/const_ptr.rs b/library/portable-simd/crates/core_simd/src/simd/ptr/const_ptr.rs index 7ef9dc21373ec..4d21af5270b3e 100644 --- a/library/portable-simd/crates/core_simd/src/simd/ptr/const_ptr.rs +++ b/library/portable-simd/crates/core_simd/src/simd/ptr/const_ptr.rs @@ -1,8 +1,7 @@ -use super::sealed::Sealed; use crate::simd::{Mask, Simd, cmp::SimdPartialEq, num::SimdUint}; /// Operations on SIMD vectors of constant pointers. -pub trait SimdConstPtr: Copy + Sealed { +pub impl(self) trait SimdConstPtr: Copy { /// Vector of `usize` with the same number of elements. type Usize; @@ -33,44 +32,21 @@ pub trait SimdConstPtr: Copy + Sealed { /// Gets the "address" portion of the pointer. /// - /// This method discards pointer semantic metadata, so the result cannot be - /// directly cast into a valid pointer. - /// - /// This method semantically discards *provenance* and - /// *address-space* information. To properly restore that information, use [`Self::with_addr`]. - /// /// Equivalent to calling [`pointer::addr`] on each element. fn addr(self) -> Self::Usize; - /// Converts an address to a pointer without giving it any provenance. - /// - /// Without provenance, this pointer is not associated with any actual allocation. Such a - /// no-provenance pointer may be used for zero-sized memory accesses (if suitably aligned), but - /// non-zero-sized memory accesses with a no-provenance pointer are UB. No-provenance pointers - /// are little more than a usize address in disguise. - /// - /// This is different from [`Self::with_exposed_provenance`], which creates a pointer that picks up a - /// previously exposed provenance. - /// - /// Equivalent to calling [`core::ptr::without_provenance`] on each element. - fn without_provenance(addr: Self::Usize) -> Self; - /// Creates a new pointer with the given address. /// - /// This performs the same operation as a cast, but copies the *address-space* and - /// *provenance* of `self` to the new pointer. - /// /// Equivalent to calling [`pointer::with_addr`] on each element. fn with_addr(self, addr: Self::Usize) -> Self; /// Exposes the "provenance" part of the pointer for future use in - /// [`Self::with_exposed_provenance`] and returns the "address" portion. - fn expose_provenance(self) -> Self::Usize; - - /// Converts an address back to a pointer, picking up a previously "exposed" provenance. + /// [`super::with_exposed_provenance`] and returns the "address" portion. /// - /// Equivalent to calling [`core::ptr::with_exposed_provenance`] on each element. - fn with_exposed_provenance(addr: Self::Usize) -> Self; + /// Equivalent to calling [`pointer::expose_provenance`] on each element. + /// + /// See [`super::with_exposed_provenance`] for the matching constructor. + fn expose_provenance(self) -> Self::Usize; /// Calculates the offset from a pointer using wrapping arithmetic. /// @@ -88,8 +64,6 @@ pub trait SimdConstPtr: Copy + Sealed { fn wrapping_sub(self, count: Self::Usize) -> Self; } -impl Sealed for Simd<*const T, N> {} - impl SimdConstPtr for Simd<*const T, N> { type Usize = Simd; type Isize = Simd; @@ -128,14 +102,6 @@ impl SimdConstPtr for Simd<*const T, N> { unsafe { core::mem::transmute_copy(&self) } } - #[inline] - fn without_provenance(addr: Self::Usize) -> Self { - // FIXME(strict_provenance_magic): I am magic and should be a compiler intrinsic. - // SAFETY: Integer-to-pointer transmutes are valid (if you are okay with not getting any - // provenance). - unsafe { core::mem::transmute_copy(&addr) } - } - #[inline] fn with_addr(self, addr: Self::Usize) -> Self { // FIXME(strict_provenance_magic): I am magic and should be a compiler intrinsic. @@ -154,12 +120,6 @@ impl SimdConstPtr for Simd<*const T, N> { unsafe { core::intrinsics::simd::simd_expose_provenance(self) } } - #[inline] - fn with_exposed_provenance(addr: Self::Usize) -> Self { - // Safety: `self` is a pointer vector - unsafe { core::intrinsics::simd::simd_with_exposed_provenance(addr) } - } - #[inline] fn wrapping_offset(self, count: Self::Isize) -> Self { // Safety: simd_arith_offset takes a vector of pointers and a vector of offsets diff --git a/library/portable-simd/crates/core_simd/src/simd/ptr/mut_ptr.rs b/library/portable-simd/crates/core_simd/src/simd/ptr/mut_ptr.rs index 3b9b75ddf5660..b7b96d5e98722 100644 --- a/library/portable-simd/crates/core_simd/src/simd/ptr/mut_ptr.rs +++ b/library/portable-simd/crates/core_simd/src/simd/ptr/mut_ptr.rs @@ -1,8 +1,7 @@ -use super::sealed::Sealed; use crate::simd::{Mask, Simd, cmp::SimdPartialEq, num::SimdUint}; /// Operations on SIMD vectors of mutable pointers. -pub trait SimdMutPtr: Copy + Sealed { +pub impl(self) trait SimdMutPtr: Copy { /// Vector of `usize` with the same number of elements. type Usize; @@ -33,41 +32,21 @@ pub trait SimdMutPtr: Copy + Sealed { /// Gets the "address" portion of the pointer. /// - /// This method discards pointer semantic metadata, so the result cannot be - /// directly cast into a valid pointer. - /// /// Equivalent to calling [`pointer::addr`] on each element. fn addr(self) -> Self::Usize; - /// Converts an address to a pointer without giving it any provenance. - /// - /// Without provenance, this pointer is not associated with any actual allocation. Such a - /// no-provenance pointer may be used for zero-sized memory accesses (if suitably aligned), but - /// non-zero-sized memory accesses with a no-provenance pointer are UB. No-provenance pointers - /// are little more than a usize address in disguise. - /// - /// This is different from [`Self::with_exposed_provenance`], which creates a pointer that picks up a - /// previously exposed provenance. - /// - /// Equivalent to calling [`core::ptr::without_provenance`] on each element. - fn without_provenance(addr: Self::Usize) -> Self; - /// Creates a new pointer with the given address. /// - /// This performs the same operation as a cast, but copies the *address-space* and - /// *provenance* of `self` to the new pointer. - /// /// Equivalent to calling [`pointer::with_addr`] on each element. fn with_addr(self, addr: Self::Usize) -> Self; /// Exposes the "provenance" part of the pointer for future use in - /// [`Self::with_exposed_provenance`] and returns the "address" portion. - fn expose_provenance(self) -> Self::Usize; - - /// Converts an address back to a pointer, picking up a previously "exposed" provenance. + /// [`super::with_exposed_provenance_mut`] and returns the "address" portion. /// - /// Equivalent to calling [`core::ptr::with_exposed_provenance_mut`] on each element. - fn with_exposed_provenance(addr: Self::Usize) -> Self; + /// Equivalent to calling [`pointer::expose_provenance`] on each element. + /// + /// See [`super::with_exposed_provenance_mut`] for the matching constructor. + fn expose_provenance(self) -> Self::Usize; /// Calculates the offset from a pointer using wrapping arithmetic. /// @@ -85,8 +64,6 @@ pub trait SimdMutPtr: Copy + Sealed { fn wrapping_sub(self, count: Self::Usize) -> Self; } -impl Sealed for Simd<*mut T, N> {} - impl SimdMutPtr for Simd<*mut T, N> { type Usize = Simd; type Isize = Simd; @@ -125,14 +102,6 @@ impl SimdMutPtr for Simd<*mut T, N> { unsafe { core::mem::transmute_copy(&self) } } - #[inline] - fn without_provenance(addr: Self::Usize) -> Self { - // FIXME(strict_provenance_magic): I am magic and should be a compiler intrinsic. - // SAFETY: Integer-to-pointer transmutes are valid (if you are okay with not getting any - // provenance). - unsafe { core::mem::transmute_copy(&addr) } - } - #[inline] fn with_addr(self, addr: Self::Usize) -> Self { // FIXME(strict_provenance_magic): I am magic and should be a compiler intrinsic. @@ -151,12 +120,6 @@ impl SimdMutPtr for Simd<*mut T, N> { unsafe { core::intrinsics::simd::simd_expose_provenance(self) } } - #[inline] - fn with_exposed_provenance(addr: Self::Usize) -> Self { - // Safety: `self` is a pointer vector - unsafe { core::intrinsics::simd::simd_with_exposed_provenance(addr) } - } - #[inline] fn wrapping_offset(self, count: Self::Isize) -> Self { // Safety: simd_arith_offset takes a vector of pointers and a vector of offsets diff --git a/library/portable-simd/crates/core_simd/src/swizzle_dyn.rs b/library/portable-simd/crates/core_simd/src/swizzle_dyn.rs index ae0b174973da7..f0253c284e35f 100644 --- a/library/portable-simd/crates/core_simd/src/swizzle_dyn.rs +++ b/library/portable-simd/crates/core_simd/src/swizzle_dyn.rs @@ -13,11 +13,6 @@ impl Simd { #[inline] pub fn swizzle_dyn(self, idxs: Simd) -> Self { #![allow(unused_imports, unused_unsafe)] - #[cfg(all( - any(target_arch = "aarch64", target_arch = "arm64ec"), - target_endian = "little" - ))] - use core::arch::aarch64::{uint8x8_t, vqtbl1q_u8, vtbl1_u8}; #[cfg(all( target_arch = "arm", target_feature = "v7", @@ -35,27 +30,20 @@ impl Simd { use core::arch::x86_64 as x86; // SAFETY: Intrinsics covered by cfg unsafe { + #[allow( + unreachable_patterns, + reason = "avoids writing verbose cfg(not), earlier branches take priority" + )] match N { - #[cfg(all( - any( - target_arch = "aarch64", - target_arch = "arm64ec", - all(target_arch = "arm", target_feature = "v7") - ), - target_feature = "neon", - target_endian = "little" - ))] - 8 => transize(vtbl1_u8, self, idxs), - #[cfg(target_feature = "ssse3")] - 16 => transize(x86::_mm_shuffle_epi8, self, zeroing_idxs(idxs)), - #[cfg(target_feature = "simd128")] - 16 => transize(wasm::i8x16_swizzle, self, idxs), + // Aarch64 #[cfg(all( any(target_arch = "aarch64", target_arch = "arm64ec"), target_feature = "neon", target_endian = "little" ))] - 16 => transize(vqtbl1q_u8, self, idxs), + 8 | 16 | 24 | 32 | 48 | 64 => aarch64_swizzle(self, idxs), + + // 32-bit ARMv7 #[cfg(all( target_arch = "arm", target_feature = "v7", @@ -63,8 +51,26 @@ impl Simd { target_endian = "little" ))] 16 => transize(armv7_neon_swizzle_u8x16, self, idxs), - #[cfg(all(target_feature = "avx2", not(target_feature = "avx512vbmi")))] - 32 => transize(avx2_pshufb, self, idxs), + + // WASM SIMD128 + #[cfg(target_feature = "simd128")] + 16 => transize(wasm::i8x16_swizzle, self, idxs), + #[cfg(target_feature = "simd128")] + 32 => transize(swizzle_dyn_split::<32, 16>, self, idxs), + + // LoongArch64 + #[cfg(all(target_arch = "loongarch64", target_feature = "lsx"))] + 16 => transize(loong64_lsx_swizzle, self, idxs), + #[cfg(all(target_arch = "loongarch64", target_feature = "lasx"))] + 32 => transize(loong64_lasx_swizzle, self, idxs), + #[cfg(all(target_arch = "loongarch64", target_feature = "lsx"))] + 32 => transize(swizzle_dyn_split::<32, 16>, self, idxs), + #[cfg(all(target_arch = "loongarch64", target_feature = "lasx"))] + 64 => transize(swizzle_dyn_split::<64, 32>, self, idxs), + + // x86, x86-64 + #[cfg(target_feature = "ssse3")] + 16 => transize(x86::_mm_shuffle_epi8, self, zeroing_idxs(idxs)), #[cfg(all(target_feature = "avx512vl", target_feature = "avx512vbmi"))] 32 => { // Unlike vpshufb, vpermb doesn't zero out values in the result based on the index high bit @@ -77,6 +83,10 @@ impl Simd { }; transize(swizzler, self, idxs) } + #[cfg(target_feature = "avx2")] + 32 => transize(avx2_pshufb, self, idxs), + #[cfg(target_feature = "ssse3")] + 32 => transize(swizzle_dyn_split::<32, 16>, self, idxs), // Notable absence: avx512bw pshufb shuffle #[cfg(all(target_feature = "avx512vl", target_feature = "avx512vbmi"))] 64 => { @@ -90,6 +100,10 @@ impl Simd { }; transize(swizzler, self, idxs) } + #[cfg(target_feature = "avx2")] + 64 => transize(swizzle_dyn_split::<64, 32>, self, idxs), + + // scalar fallback _ => { let mut array = [0; N]; for (i, k) in idxs.to_array().into_iter().enumerate() { @@ -104,6 +118,48 @@ impl Simd { } } +#[allow(dead_code, reason = "only used on some targets/features")] +/// Implements an arbitrary shuffle over double the native vector width +/// using 4 native-width shuffles +fn swizzle_dyn_split( + bytes: Simd, + idxs: Simd, +) -> Simd { + let table_low = bytes.extract::<0, HALF>(); + let table_high = bytes.extract::(); + let idxs_low = idxs.extract::<0, HALF>(); + let idxs_high = idxs.extract::(); + let table_high_offset = Simd::::splat(HALF as u8); + + let output_low_from_low = table_low.swizzle_dyn(idxs_low); + let output_low_from_high = table_high.swizzle_dyn(idxs_low - table_high_offset); + let output_low = output_low_from_low | output_low_from_high; + + let output_high_from_low = table_low.swizzle_dyn(idxs_high); + let output_high_from_high = table_high.swizzle_dyn(idxs_high - table_high_offset); + let output_high = output_high_from_low | output_high_from_high; + + // This is simply a concatenation of two native-sized vectors. + // The swizzle does nothing - it maps the elements right back where they already are. + // There doesn't seem to be a more direct way to do this as of this writing. + // TODO: simplify once a plain `concat` is available. + use crate::simd::Swizzle; + struct CombineHalves; + impl Swizzle for CombineHalves { + const INDEX: [usize; N] = const { + let mut index = [0; N]; + let mut i = 0; + while i < N { + index[i] = i; + i += 1; + } + index + }; + } + + CombineHalves::concat_swizzle(output_low, output_high) +} + /// armv7 neon supports swizzling `u8x16` by swizzling two u8x8 blocks /// with a u8x8x2 lookup table. /// @@ -126,6 +182,73 @@ unsafe fn armv7_neon_swizzle_u8x16(bytes: Simd, idxs: Simd) -> S } } +/// AArch64 NEON supports swizzling 8, 16, 24, 32, 48 or 64 by stacking multiple TBL instructions. +/// +/// # Safety +/// This requires AArch64 NEON to work +#[cfg(all( + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_feature = "neon", + target_endian = "little" +))] +unsafe fn aarch64_swizzle(bytes: Simd, idxs: Simd) -> Simd { + use core::arch::aarch64::*; + use core::mem::transmute_copy; + + // SAFETY: Caller promised AArch64 NEON support + unsafe { + match N { + 8 => transmute_copy(&vtbl1_u8(transmute_copy(&bytes), transmute_copy(&idxs))), + 16 => transmute_copy(&vqtbl1q_u8(transmute_copy(&bytes), transmute_copy(&idxs))), + 24 => { + let bytes: uint8x8x3_t = transmute_copy(&bytes); + let idxs: uint8x8x3_t = transmute_copy(&idxs); + + let ret0 = vtbl3_u8(bytes, idxs.0); + let ret1 = vtbl3_u8(bytes, idxs.1); + let ret2 = vtbl3_u8(bytes, idxs.2); + + let ret = uint8x8x3_t(ret0, ret1, ret2); + transmute_copy(&ret) + } + 32 => { + let bytes: uint8x16x2_t = transmute_copy(&bytes); + let idxs: uint8x16x2_t = transmute_copy(&idxs); + + let ret0 = vqtbl2q_u8(bytes, idxs.0); + let ret1 = vqtbl2q_u8(bytes, idxs.1); + + let ret = uint8x16x2_t(ret0, ret1); + transmute_copy(&ret) + } + 48 => { + let bytes: uint8x16x3_t = transmute_copy(&bytes); + let idxs: uint8x16x3_t = transmute_copy(&idxs); + + let ret0 = vqtbl3q_u8(bytes, idxs.0); + let ret1 = vqtbl3q_u8(bytes, idxs.1); + let ret2 = vqtbl3q_u8(bytes, idxs.2); + + let ret = uint8x16x3_t(ret0, ret1, ret2); + transmute_copy(&ret) + } + 64 => { + let bytes: uint8x16x4_t = transmute_copy(&bytes); + let idxs: uint8x16x4_t = transmute_copy(&idxs); + + let ret0 = vqtbl4q_u8(bytes, idxs.0); + let ret1 = vqtbl4q_u8(bytes, idxs.1); + let ret2 = vqtbl4q_u8(bytes, idxs.2); + let ret3 = vqtbl4q_u8(bytes, idxs.3); + + let ret = uint8x16x4_t(ret0, ret1, ret2, ret3); + transmute_copy(&ret) + } + _ => unreachable!(), + } + } +} + /// "vpshufb like it was meant to be" on AVX2 /// /// # Safety @@ -136,35 +259,59 @@ unsafe fn armv7_neon_swizzle_u8x16(bytes: Simd, idxs: Simd) -> S #[inline] #[allow(clippy::let_and_return)] unsafe fn avx2_pshufb(bytes: Simd, idxs: Simd) -> Simd { - use crate::simd::{Select, cmp::SimdPartialOrd}; #[cfg(target_arch = "x86")] use core::arch::x86; #[cfg(target_arch = "x86_64")] use core::arch::x86_64 as x86; use x86::_mm256_permute2x128_si256 as avx2_cross_shuffle; use x86::_mm256_shuffle_epi8 as avx2_half_pshufb; - let mid = Simd::splat(16u8); - let high = mid + mid; // SAFETY: Caller promised AVX2 unsafe { - // This is ordering sensitive, and LLVM will order these how you put them. - // Most AVX2 impls use ~5 "ports", and only 1 or 2 are capable of permutes. - // But the "compose" step will lower to ops that can also use at least 1 other port. - // So this tries to break up permutes so composition flows through "open" ports. - // Comparative benches should be done on multiple AVX2 CPUs before reordering this - - let hihi = avx2_cross_shuffle::<0x11>(bytes.into(), bytes.into()); - let hi_shuf = Simd::from(avx2_half_pshufb( - hihi, // duplicate the vector's top half - idxs.into(), // so that using only 4 bits of an index still picks bytes 16-31 - )); - // A zero-fill during the compose step gives the "all-Neon-like" OOB-is-0 semantics - let compose = idxs.simd_lt(high).select(hi_shuf, Simd::splat(0)); let lolo = avx2_cross_shuffle::<0x00>(bytes.into(), bytes.into()); - let lo_shuf = Simd::from(avx2_half_pshufb(lolo, idxs.into())); - // Repeat, then pick indices < 16, overwriting indices 0-15 from previous compose step - let compose = idxs.simd_lt(mid).select(lo_shuf, compose); - compose + let hihi = avx2_cross_shuffle::<0x11>(bytes.into(), bytes.into()); + + // Adding 0x60 preserves the low nibble and bit 4 for valid + // indices 0..=31. Larger indices get their high bit set, so + // VPSHUFB supplies the required out-of-bounds zeroing. + let control = x86::_mm256_adds_epu8(idxs.into(), x86::_mm256_set1_epi8(0x60)); + + // Move index bit 4 into each byte's sign bit for VPBLENDVB. + let select_high = x86::_mm256_slli_epi16::<3>(control); + let from_low = avx2_half_pshufb(lolo, control); + let from_high = avx2_half_pshufb(hihi, control); + x86::_mm256_blendv_epi8(from_low, from_high, select_high).into() + } +} + +/// LoongArch64 LSX supports swizzling `u8x16` +/// +/// # Safety +/// This requires LoongArch LSX to work +#[cfg(all(target_arch = "loongarch64", target_feature = "lsx"))] +unsafe fn loong64_lsx_swizzle(bytes: Simd, idxs: Simd) -> Simd { + use core::arch::loongarch64::{lsx_vand_v, lsx_vshuf_b, lsx_vslei_bu}; + // SAFETY: Caller promised loongarch lsx support + unsafe { + let bytes = lsx_vshuf_b(bytes.into(), bytes.into(), idxs.into()); + let mask = lsx_vslei_bu::<15>(idxs.into()); + lsx_vand_v(bytes, mask).into() + } +} + +/// LoongArch64 LASX supports swizzling `u8x32` +/// +/// # Safety +/// This requires LoongArch LASX to work +#[cfg(all(target_arch = "loongarch64", target_feature = "lasx"))] +unsafe fn loong64_lasx_swizzle(bytes: Simd, idxs: Simd) -> Simd { + use core::arch::loongarch64::{lasx_xvand_v, lasx_xvpermi_q, lasx_xvshuf_b, lasx_xvslei_bu}; + // SAFETY: Caller promised loongarch lasx support + unsafe { + let lolo = lasx_xvpermi_q::<0x00>(bytes.into(), bytes.into()); + let hihi = lasx_xvpermi_q::<0x11>(bytes.into(), bytes.into()); + let bytes = lasx_xvshuf_b(hihi, lolo, idxs.into()); + let mask = lasx_xvslei_bu::<31>(idxs.into()); + lasx_xvand_v(bytes, mask).into() } } @@ -191,7 +338,8 @@ unsafe fn transize( #[allow(unused)] #[inline(always)] fn zeroing_idxs(idxs: Simd) -> Simd { - use crate::simd::{Select, cmp::SimdPartialOrd}; - idxs.simd_lt(Simd::splat(N as u8)) - .select(idxs, Simd::splat(u8::MAX)) + // Adding this sets the high bit for indices N..=127, while PSHUFB ignores + // the other changed bits. The OR preserves the high bit for indices 128..=255. + let zeroing_bits = idxs + Simd::splat((127 - N + 1) as u8); + idxs | zeroing_bits } diff --git a/library/portable-simd/crates/core_simd/src/to_bytes.rs b/library/portable-simd/crates/core_simd/src/to_bytes.rs index 1fd285e457db8..becc4e5a93a3c 100644 --- a/library/portable-simd/crates/core_simd/src/to_bytes.rs +++ b/library/portable-simd/crates/core_simd/src/to_bytes.rs @@ -1,17 +1,10 @@ use crate::simd::{ - Simd, SimdElement, + Simd, num::{SimdFloat, SimdInt, SimdUint}, }; -mod sealed { - use super::*; - pub trait Sealed {} - impl Sealed for Simd {} -} -use sealed::Sealed; - /// Converts SIMD vectors to vectors of bytes -pub trait ToBytes: Sealed { +pub impl(self) trait ToBytes { /// This type, reinterpreted as bytes. type Bytes: Copy + Unpin diff --git a/library/portable-simd/crates/core_simd/src/vector.rs b/library/portable-simd/crates/core_simd/src/vector.rs index e75327f175453..8bb9d58623163 100644 --- a/library/portable-simd/crates/core_simd/src/vector.rs +++ b/library/portable-simd/crates/core_simd/src/vector.rs @@ -367,7 +367,7 @@ where /// corresponding element in `enable` is `true`. /// /// When the element is disabled or out of bounds for the slice, that memory location - /// is not accessed and the corresponding value from `or` is passed through. + /// is not accessed and the default value for the element type is returned. /// /// # Examples /// ``` @@ -375,12 +375,11 @@ where /// # #[cfg(feature = "as_crate")] use core_simd::simd; /// # #[cfg(not(feature = "as_crate"))] use core::simd; /// # use simd::{Simd, Mask}; - /// let vec: Vec = vec![10, 11, 12, 13, 14, 15, 16, 17, 18]; - /// let enable = Mask::from_array([true, true, false, true]); - /// let or = Simd::from_array([-5, -4, -3, -2]); + /// let vec: Vec = vec![10, 11, 12]; + /// let enable = Mask::from_array([false, true, true, true]); /// - /// let result = Simd::load_select(&vec, enable, or); - /// assert_eq!(result, Simd::from_array([10, 11, -3, 13])); + /// let result = Simd::load_select_or_default(&vec, enable); + /// assert_eq!(result, Simd::from_array([0, 11, 12, 0])); /// ``` #[must_use] #[inline] @@ -1063,11 +1062,6 @@ where } } -mod sealed { - pub trait Sealed {} -} -use sealed::Sealed; - /// Marker trait for types that may be used as SIMD vector elements. /// /// # Safety @@ -1076,97 +1070,76 @@ use sealed::Sealed; /// Strictly, it is valid to impl if the vector will not be miscompiled. /// Practically, it is user-unfriendly to impl it if the vector won't compile, /// even when no soundness guarantees are broken by allowing the user to try. -pub unsafe trait SimdElement: Sealed + Copy { +pub impl(self) unsafe trait SimdElement: Copy { /// The mask element type corresponding to this element type. type Mask: MaskElement; } -impl Sealed for u8 {} - // Safety: u8 is a valid SIMD element type, and is supported by this API unsafe impl SimdElement for u8 { type Mask = i8; } -impl Sealed for u16 {} - // Safety: u16 is a valid SIMD element type, and is supported by this API unsafe impl SimdElement for u16 { type Mask = i16; } -impl Sealed for u32 {} - // Safety: u32 is a valid SIMD element type, and is supported by this API unsafe impl SimdElement for u32 { type Mask = i32; } -impl Sealed for u64 {} - // Safety: u64 is a valid SIMD element type, and is supported by this API unsafe impl SimdElement for u64 { type Mask = i64; } -impl Sealed for usize {} - // Safety: usize is a valid SIMD element type, and is supported by this API unsafe impl SimdElement for usize { type Mask = isize; } -impl Sealed for i8 {} - // Safety: i8 is a valid SIMD element type, and is supported by this API unsafe impl SimdElement for i8 { type Mask = i8; } -impl Sealed for i16 {} - // Safety: i16 is a valid SIMD element type, and is supported by this API unsafe impl SimdElement for i16 { type Mask = i16; } -impl Sealed for i32 {} - // Safety: i32 is a valid SIMD element type, and is supported by this API unsafe impl SimdElement for i32 { type Mask = i32; } -impl Sealed for i64 {} - // Safety: i64 is a valid SIMD element type, and is supported by this API unsafe impl SimdElement for i64 { type Mask = i64; } -impl Sealed for isize {} - // Safety: isize is a valid SIMD element type, and is supported by this API unsafe impl SimdElement for isize { type Mask = isize; } -impl Sealed for f32 {} +// Safety: f16 is a valid SIMD element type, and is supported by this API +unsafe impl SimdElement for f16 { + type Mask = i16; +} // Safety: f32 is a valid SIMD element type, and is supported by this API unsafe impl SimdElement for f32 { type Mask = i32; } -impl Sealed for f64 {} - // Safety: f64 is a valid SIMD element type, and is supported by this API unsafe impl SimdElement for f64 { type Mask = i64; } -impl Sealed for *const T {} - // Safety: (thin) const pointers are valid SIMD element types, and are supported by this API // // Fat pointers may be supported in the future. @@ -1177,8 +1150,6 @@ where type Mask = isize; } -impl Sealed for *mut T {} - // Safety: (thin) mut pointers are valid SIMD element types, and are supported by this API // // Fat pointers may be supported in the future. diff --git a/library/portable-simd/crates/core_simd/src/vendor.rs b/library/portable-simd/crates/core_simd/src/vendor.rs index 57536e4fc77dc..6b3c640c2f7c5 100644 --- a/library/portable-simd/crates/core_simd/src/vendor.rs +++ b/library/portable-simd/crates/core_simd/src/vendor.rs @@ -32,3 +32,6 @@ mod powerpc; #[cfg(target_arch = "loongarch64")] mod loongarch64; + +#[cfg(target_arch = "hexagon")] +mod hexagon; diff --git a/library/portable-simd/crates/core_simd/src/vendor/arm.rs b/library/portable-simd/crates/core_simd/src/vendor/arm.rs index 3dc54481b6fd4..d2f4ffd8e867e 100644 --- a/library/portable-simd/crates/core_simd/src/vendor/arm.rs +++ b/library/portable-simd/crates/core_simd/src/vendor/arm.rs @@ -7,6 +7,16 @@ use core::arch::arm::*; #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] use core::arch::aarch64::*; +/// Transmute between `Simd` and ACLE tuple types. +macro_rules! tuple { + ($scalar:ty,$tuple:ty) => { + from_transmute! { unsafe Simd<$scalar, { size_of::<$tuple>() / size_of::<$scalar>() }> => $tuple } + }; + ($scalar:ty,$($tuples:ty),*) => { + $(tuple! { $scalar, $tuples })* + }; +} + #[cfg(all( any( target_arch = "aarch64", @@ -18,9 +28,6 @@ use core::arch::aarch64::*; mod neon { use super::*; - from_transmute! { unsafe f32x2 => float32x2_t } - from_transmute! { unsafe f32x4 => float32x4_t } - from_transmute! { unsafe u8x8 => uint8x8_t } from_transmute! { unsafe u8x16 => uint8x16_t } from_transmute! { unsafe i8x8 => int8x8_t } @@ -34,11 +41,15 @@ mod neon { from_transmute! { unsafe i16x8 => int16x8_t } from_transmute! { unsafe u16x4 => poly16x4_t } from_transmute! { unsafe u16x8 => poly16x8_t } + from_transmute! { unsafe f16x4 => float16x4_t } + from_transmute! { unsafe f16x8 => float16x8_t } from_transmute! { unsafe u32x2 => uint32x2_t } from_transmute! { unsafe u32x4 => uint32x4_t } from_transmute! { unsafe i32x2 => int32x2_t } from_transmute! { unsafe i32x4 => int32x4_t } + from_transmute! { unsafe f32x2 => float32x2_t } + from_transmute! { unsafe f32x4 => float32x4_t } from_transmute! { unsafe Simd => uint64x1_t } from_transmute! { unsafe u64x2 => uint64x2_t } @@ -46,6 +57,36 @@ mod neon { from_transmute! { unsafe i64x2 => int64x2_t } from_transmute! { unsafe Simd => poly64x1_t } from_transmute! { unsafe u64x2 => poly64x2_t } + + tuple!(i8, int8x8x2_t, int8x8x3_t, int8x8x4_t); + tuple!(i8, int8x16x2_t, int8x16x3_t, int8x16x4_t); + tuple!(u8, uint8x8x2_t, uint8x8x3_t, uint8x8x4_t); + tuple!(u8, uint8x16x2_t, uint8x16x3_t, uint8x16x4_t); + tuple!(u8, poly8x8x2_t, poly8x8x3_t, poly8x8x4_t); + tuple!(u8, poly8x16x2_t, poly8x16x3_t, poly8x16x4_t); + + tuple!(i16, int16x4x2_t, int16x4x3_t, int16x4x4_t); + tuple!(i16, int16x8x2_t, int16x8x3_t, int16x8x4_t); + tuple!(u16, uint16x4x2_t, uint16x4x3_t, uint16x4x4_t); + tuple!(u16, uint16x8x2_t, uint16x8x3_t, uint16x8x4_t); + tuple!(u16, poly16x4x2_t, poly16x4x3_t, poly16x4x4_t); + tuple!(u16, poly16x8x2_t, poly16x8x3_t, poly16x8x4_t); + tuple!(f16, float16x4x2_t, float16x4x3_t, float16x4x4_t); + tuple!(f16, float16x8x2_t, float16x8x3_t, float16x8x4_t); + + tuple!(i32, int32x2x2_t, int32x2x3_t, int32x2x4_t); + tuple!(i32, int32x4x2_t, int32x4x3_t, int32x4x4_t); + tuple!(u32, uint32x2x2_t, uint32x2x3_t, uint32x2x4_t); + tuple!(u32, uint32x4x2_t, uint32x4x3_t, uint32x4x4_t); + tuple!(f32, float32x2x2_t, float32x2x3_t, float32x2x4_t); + tuple!(f32, float32x4x2_t, float32x4x3_t, float32x4x4_t); + + tuple!(i64, int64x1x2_t, int64x1x3_t, int64x1x4_t); + tuple!(i64, int64x2x2_t, int64x2x3_t, int64x2x4_t); + tuple!(u64, uint64x1x2_t, uint64x1x3_t, uint64x1x4_t); + tuple!(u64, uint64x2x2_t, uint64x2x3_t, uint64x2x4_t); + tuple!(u64, poly64x1x2_t, poly64x1x3_t, poly64x1x4_t); + tuple!(u64, poly64x2x2_t, poly64x2x3_t, poly64x2x4_t); } #[cfg(any( @@ -71,4 +112,7 @@ mod aarch64 { from_transmute! { unsafe Simd => float64x1_t } from_transmute! { unsafe f64x2 => float64x2_t } + + tuple!(f64, float64x1x2_t, float64x1x3_t, float64x1x4_t); + tuple!(f64, float64x2x2_t, float64x2x3_t, float64x2x4_t); } diff --git a/library/portable-simd/crates/core_simd/src/vendor/hexagon.rs b/library/portable-simd/crates/core_simd/src/vendor/hexagon.rs new file mode 100644 index 0000000000000..2b8ea55fde659 --- /dev/null +++ b/library/portable-simd/crates/core_simd/src/vendor/hexagon.rs @@ -0,0 +1,40 @@ +//! Conversions to Hexagon HVX SIMD types. + +use crate::simd::*; + +// HVX 128-byte mode (1024-bit vectors) +// Enable with: -C target-feature=+hvx-length128b +#[cfg(target_feature = "hvx-length128b")] +mod hvx_128b { + use super::*; + use core::arch::hexagon::v128::HvxVector; + + // Full vectors (1024-bit) map to HvxVector + from_transmute! { unsafe u16x64 => HvxVector } + from_transmute! { unsafe i16x64 => HvxVector } + from_transmute! { unsafe u32x32 => HvxVector } + from_transmute! { unsafe i32x32 => HvxVector } + from_transmute! { unsafe u64x16 => HvxVector } + from_transmute! { unsafe i64x16 => HvxVector } + + // FIXME: u8x128/i8x128 don't exist in portable-simd (max lane count is 64) + // u8x64/i8x64 are only 512-bit (half of HvxVector in 128B mode) +} + +// HVX 64-byte mode (512-bit vectors) +// Default when hvx-length128b is not specified +#[cfg(not(target_feature = "hvx-length128b"))] +mod hvx_64b { + use super::*; + use core::arch::hexagon::v64::HvxVector; + + // Full vectors (512-bit) map to HvxVector + from_transmute! { unsafe u8x64 => HvxVector } + from_transmute! { unsafe i8x64 => HvxVector } + from_transmute! { unsafe u16x32 => HvxVector } + from_transmute! { unsafe i16x32 => HvxVector } + from_transmute! { unsafe u32x16 => HvxVector } + from_transmute! { unsafe i32x16 => HvxVector } + from_transmute! { unsafe u64x8 => HvxVector } + from_transmute! { unsafe i64x8 => HvxVector } +} diff --git a/library/portable-simd/crates/core_simd/tests/f16_ops.rs b/library/portable-simd/crates/core_simd/tests/f16_ops.rs new file mode 100644 index 0000000000000..d512ca4e07ba2 --- /dev/null +++ b/library/portable-simd/crates/core_simd/tests/f16_ops.rs @@ -0,0 +1,13 @@ +#![feature(portable_simd)] +#![feature(f16)] +#![expect(internal_features)] +#![feature(cfg_target_has_reliable_f16_f128)] +#![allow(unused_features)] +#[macro_use] +mod ops_macros; + +// FIXME: some f16 operations cause rustc to hang on wasm simd +// https://github.com/llvm/llvm-project/issues/189251 +#[cfg(not(all(target_arch = "wasm32", target_feature = "simd128")))] +#[cfg(target_has_reliable_f16_math)] +impl_float_tests! { f16, i16 } diff --git a/library/portable-simd/crates/core_simd/tests/masks.rs b/library/portable-simd/crates/core_simd/tests/masks.rs index 53fb2367b6055..6bcf02ee12075 100644 --- a/library/portable-simd/crates/core_simd/tests/masks.rs +++ b/library/portable-simd/crates/core_simd/tests/masks.rs @@ -133,6 +133,24 @@ macro_rules! test_mask_api { cast_impl::(); cast_impl::(); } + + #[test] + fn first_set() { + for bitmask in 0..=u8::MAX { + let mask = Mask::<$type, 8>::from_bitmask(bitmask as u64); + let expected = bitmask.lowest_one().map(|i| i as usize); + assert_eq!(mask.first_set(), expected); + } + } + + #[test] + fn last_set() { + for bitmask in 0..=u8::MAX { + let mask = Mask::<$type, 8>::from_bitmask(bitmask as u64); + let expected = bitmask.highest_one().map(|i| i as usize); + assert_eq!(mask.last_set(), expected); + } + } } } } diff --git a/library/portable-simd/crates/core_simd/tests/pointers.rs b/library/portable-simd/crates/core_simd/tests/pointers.rs index 6e74c2d18b1ed..06670cc9dd976 100644 --- a/library/portable-simd/crates/core_simd/tests/pointers.rs +++ b/library/portable-simd/crates/core_simd/tests/pointers.rs @@ -2,7 +2,7 @@ use core_simd::simd::{ Simd, - ptr::{SimdConstPtr, SimdMutPtr}, + ptr::{self, SimdConstPtr, SimdMutPtr}, }; macro_rules! common_tests { @@ -82,11 +82,20 @@ mod const_ptr { fn with_exposed_provenance() { test_helpers::test_unary_elementwise( - &Simd::<*const u32, LANES>::with_exposed_provenance, + &ptr::with_exposed_provenance::, &core::ptr::with_exposed_provenance::, &|_| true, ); } + + fn without_provenance() { + test_helpers::test_unary_elementwise( + &ptr::without_provenance::, + &core::ptr::without_provenance::, + &|_| true, + ); + } + } } @@ -105,10 +114,19 @@ mod mut_ptr { fn with_exposed_provenance() { test_helpers::test_unary_elementwise( - &Simd::<*mut u32, LANES>::with_exposed_provenance, + &ptr::with_exposed_provenance_mut::, &core::ptr::with_exposed_provenance_mut::, &|_| true, ); } + + fn without_provenance() { + test_helpers::test_unary_elementwise( + &ptr::without_provenance_mut::, + &core::ptr::without_provenance_mut::, + &|_| true, + ); + } + } } diff --git a/library/portable-simd/crates/core_simd/tests/round.rs b/library/portable-simd/crates/core_simd/tests/round.rs index 4c1ac3c36f894..95b17f415822b 100644 --- a/library/portable-simd/crates/core_simd/tests/round.rs +++ b/library/portable-simd/crates/core_simd/tests/round.rs @@ -42,6 +42,14 @@ macro_rules! float_rounding_test { ) } + fn round_ties_even() { + test_helpers::test_unary_elementwise( + &Vector::::round_ties_even, + &Scalar::round_ties_even, + &|_| true, + ) + } + fn fract() { test_helpers::test_unary_elementwise_flush_subnormals( &Vector::::fract, diff --git a/library/portable-simd/crates/core_simd/tests/swizzle_dyn.rs b/library/portable-simd/crates/core_simd/tests/swizzle_dyn.rs index 19ffe1417c8c4..4ab6c41c074eb 100644 --- a/library/portable-simd/crates/core_simd/tests/swizzle_dyn.rs +++ b/library/portable-simd/crates/core_simd/tests/swizzle_dyn.rs @@ -61,7 +61,7 @@ pub trait SwizzleStrategy { impl SwizzleStrategy for u8 { type Strategy = RangeInclusive; fn swizzled_strategy() -> Self::Strategy { - 0..=64 + 0..=u8::MAX } } diff --git a/library/portable-simd/crates/std_float/Cargo.toml b/library/portable-simd/crates/std_float/Cargo.toml index 0896094ee63f4..08360a455b792 100644 --- a/library/portable-simd/crates/std_float/Cargo.toml +++ b/library/portable-simd/crates/std_float/Cargo.toml @@ -18,3 +18,11 @@ wasm-bindgen-test = "0.3" [features] default = ["as_crate"] as_crate = [] + +[lints.rust.unexpected_cfgs] +level = "warn" +check-cfg = [ + # Internal features aren't marked known config by default, we use these to + # gate tests. + 'cfg(target_has_reliable_f16_math)', +] diff --git a/library/portable-simd/crates/std_float/src/lib.rs b/library/portable-simd/crates/std_float/src/lib.rs index b269efc9b1d76..d9499e539365f 100644 --- a/library/portable-simd/crates/std_float/src/lib.rs +++ b/library/portable-simd/crates/std_float/src/lib.rs @@ -2,27 +2,18 @@ feature = "as_crate", feature(core_intrinsics), feature(portable_simd), + feature(f16), + feature(impl_restriction), allow(internal_features) )] +use core::intrinsics::simd as intrinsics; #[cfg(not(feature = "as_crate"))] use core::simd; + #[cfg(feature = "as_crate")] use core_simd::simd; - -use core::intrinsics::simd as intrinsics; - use simd::Simd; -#[cfg(feature = "as_crate")] -mod experimental { - pub trait Sealed {} -} - -#[cfg(feature = "as_crate")] -use experimental as sealed; - -use crate::sealed::Sealed; - /// This trait provides a possibly-temporary implementation of float functions /// that may, in the absence of hardware support, canonicalize to calling an /// operating system's `math.h` dynamically-loaded library (also known as a @@ -42,7 +33,7 @@ use crate::sealed::Sealed; /// when either the compiler or its supporting runtime functions are improved. /// For now this trait is available to permit experimentation with SIMD float /// operations that may lack hardware support, such as `mul_add`. -pub trait StdFloat: Sealed + Sized { +pub impl(self) trait StdFloat: Sized { /// Elementwise fused multiply-add. Computes `(self * a) + b` with only one rounding error, /// yielding a more accurate result than an unfused multiply-add. /// @@ -156,13 +147,25 @@ pub trait StdFloat: Sealed + Sized { unsafe { intrinsics::simd_trunc(self) } } + /// Rounds each element to the nearest integer-valued float. + /// Ties are resolved by rounding to the number with an even least significant digit. + #[must_use = "method returns a new vector and does not mutate the original value"] + #[inline] + fn round_ties_even(self) -> Self { + unsafe { intrinsics::simd_round_ties_even(self) } + } + /// Returns the floating point's fractional value, with its integer part removed. #[must_use = "method returns a new vector and does not mutate the original value"] fn fract(self) -> Self; } -impl Sealed for Simd {} -impl Sealed for Simd {} +impl StdFloat for Simd { + #[inline] + fn fract(self) -> Self { + self - self.trunc() + } +} impl StdFloat for Simd { #[inline] diff --git a/library/portable-simd/crates/std_float/tests/float.rs b/library/portable-simd/crates/std_float/tests/float.rs index c608ba49564e0..e0ab7ac4fbd2b 100644 --- a/library/portable-simd/crates/std_float/tests/float.rs +++ b/library/portable-simd/crates/std_float/tests/float.rs @@ -1,4 +1,8 @@ #![feature(portable_simd)] +#![feature(f16)] +#![feature(cfg_target_has_reliable_f16_f128)] +#![allow(internal_features)] +#![allow(unused_features)] macro_rules! unary_test { { $scalar:tt, $($func:tt),+ } => { @@ -25,23 +29,6 @@ macro_rules! unary_approx_test { &core_simd::simd::Simd::<$scalar, LANES>::$func, &$scalar::$func, &|_| true, - 8, - ) - } - )* - } - } -} - -macro_rules! binary_approx_test { - { $scalar:tt, $($func:tt),+ } => { - test_helpers::test_lanes! { - $( - fn $func() { - test_helpers::test_binary_elementwise_approx( - &core_simd::simd::Simd::<$scalar, LANES>::$func, - &$scalar::$func, - &|_, _| true, 16, ) } @@ -71,12 +58,24 @@ macro_rules! impl_tests { mod $scalar { use std_float::StdFloat; - unary_test! { $scalar, sqrt, ceil, floor, round, trunc } + unary_test! { $scalar, sqrt, ceil, floor, round, trunc, round_ties_even } ternary_test! { $scalar, mul_add } // https://github.com/rust-lang/miri/issues/3555 unary_approx_test! { $scalar, sin, cos, exp, exp2, ln, log2, log10 } - binary_approx_test! { $scalar, log } + + // The implementation of log is a.ln() / b.ln(), so there are 2 inexact operations, + // hence a larger ulps is needed. + test_helpers::test_lanes! { + fn log() { + test_helpers::test_binary_elementwise_approx( + &core_simd::simd::Simd::<$scalar, LANES>::log, + &$scalar::log, + &|_, _| true, + 32, + ) + } + } test_helpers::test_lanes! { fn fract() { @@ -91,5 +90,7 @@ macro_rules! impl_tests { } } +#[cfg(target_has_reliable_f16_math)] +impl_tests! { f16 } impl_tests! { f32 } impl_tests! { f64 } diff --git a/library/portable-simd/crates/test_helpers/Cargo.toml b/library/portable-simd/crates/test_helpers/Cargo.toml index 408bb04c7aa40..2abacd89b8e0b 100644 --- a/library/portable-simd/crates/test_helpers/Cargo.toml +++ b/library/portable-simd/crates/test_helpers/Cargo.toml @@ -5,5 +5,4 @@ edition = "2021" publish = false [dependencies] -proptest = { version = "0.10", default-features = false, features = ["alloc"] } -float-cmp = "0.10" +proptest = { workspace = true, features = ["alloc", "std"] } diff --git a/library/portable-simd/crates/test_helpers/src/approxeq.rs b/library/portable-simd/crates/test_helpers/src/approxeq.rs index 57b43a16bc6fe..b868e09e1483a 100644 --- a/library/portable-simd/crates/test_helpers/src/approxeq.rs +++ b/library/portable-simd/crates/test_helpers/src/approxeq.rs @@ -1,7 +1,5 @@ //! Compare numeric types approximately. -use float_cmp::Ulps; - pub trait ApproxEq { fn approxeq(&self, other: &Self, _ulps: i64) -> bool; fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result; @@ -43,7 +41,14 @@ macro_rules! impl_float_approxeq { if self.is_nan() && other.is_nan() { true } else { - (self.ulps(other) as i64).abs() <= ulps + let allowed_ulp_diff = ulps; + + // Approximate the ULP by taking half the distance between the number one place "up" + // and the number one place "down". + let ulp = (other.next_up() - other.next_down()) / 2.0; + let ulp_diff = ((self - other) / ulp).abs().round() as i64; + + ulp_diff <= allowed_ulp_diff } } @@ -55,7 +60,7 @@ macro_rules! impl_float_approxeq { }; } -impl_float_approxeq! { f32, f64 } +impl_float_approxeq! { f16, f32, f64 } impl ApproxEq for [T; N] { fn approxeq(&self, other: &Self, ulps: i64) -> bool { diff --git a/library/portable-simd/crates/test_helpers/src/biteq.rs b/library/portable-simd/crates/test_helpers/src/biteq.rs index cbc20cda0d626..36761e37dea76 100644 --- a/library/portable-simd/crates/test_helpers/src/biteq.rs +++ b/library/portable-simd/crates/test_helpers/src/biteq.rs @@ -53,7 +53,7 @@ macro_rules! impl_float_biteq { }; } -impl_float_biteq! { f32, f64 } +impl_float_biteq! { f16, f32, f64 } impl BitEq for *const T { fn biteq(&self, other: &Self) -> bool { diff --git a/library/portable-simd/crates/test_helpers/src/lib.rs b/library/portable-simd/crates/test_helpers/src/lib.rs index eb3d3f68bc2ea..6661b0c53c7a9 100644 --- a/library/portable-simd/crates/test_helpers/src/lib.rs +++ b/library/portable-simd/crates/test_helpers/src/lib.rs @@ -1,7 +1,7 @@ -#![feature(powerpc_target_feature)] +#![feature(f16)] #![cfg_attr( any(target_arch = "powerpc", target_arch = "powerpc64"), - feature(stdarch_powerpc) + feature(powerpc_target_feature, stdarch_powerpc) )] pub mod array; @@ -47,6 +47,7 @@ impl_num! { u16 } impl_num! { u32 } impl_num! { u64 } impl_num! { usize } +impl_num! { f16 } impl_num! { f32 } impl_num! { f64 } @@ -121,12 +122,23 @@ pub fn make_runner() -> proptest::test_runner::TestRunner { proptest::test_runner::TestRunner::new(proptest::test_runner::Config::with_cases(4)) } +#[track_caller] +fn unwrap_test_error( + x: Result>, +) -> T { + // Using the `Display` instance of the error is much more readable. + match x { + Ok(v) => v, + Err(e) => panic!("{e}"), + } +} + /// Test a function that takes a single value. pub fn test_1( f: &dyn Fn(A) -> proptest::test_runner::TestCaseResult, ) { let mut runner = make_runner(); - runner.run(&A::default_strategy(), f).unwrap(); + unwrap_test_error(runner.run(&A::default_strategy(), f)) } /// Test a function that takes two values. @@ -134,11 +146,11 @@ pub fn test_2 proptest::test_runner::TestCaseResult, ) { let mut runner = make_runner(); - runner - .run(&(A::default_strategy(), B::default_strategy()), |(a, b)| { + unwrap_test_error( + runner.run(&(A::default_strategy(), B::default_strategy()), |(a, b)| { f(a, b) - }) - .unwrap(); + }), + ) } /// Test a function that takes two values. @@ -150,16 +162,14 @@ pub fn test_3< f: &dyn Fn(A, B, C) -> proptest::test_runner::TestCaseResult, ) { let mut runner = make_runner(); - runner - .run( - &( - A::default_strategy(), - B::default_strategy(), - C::default_strategy(), - ), - |(a, b, c)| f(a, b, c), - ) - .unwrap(); + unwrap_test_error(runner.run( + &( + A::default_strategy(), + B::default_strategy(), + C::default_strategy(), + ), + |(a, b, c)| f(a, b, c), + )); } /// Test a unary vector function against a unary scalar function, applied elementwise. @@ -668,7 +678,7 @@ macro_rules! test_lanes { //lanes_45 45; //lanes_46 46; lanes_47 47; - //lanes_48 48; + lanes_48 48; //lanes_49 49; //lanes_50 50; //lanes_51 51; diff --git a/library/portable-simd/crates/test_helpers/src/subnormals.rs b/library/portable-simd/crates/test_helpers/src/subnormals.rs index b5f19ba47b819..44dfbb3d6c955 100644 --- a/library/portable-simd/crates/test_helpers/src/subnormals.rs +++ b/library/portable-simd/crates/test_helpers/src/subnormals.rs @@ -39,7 +39,7 @@ macro_rules! impl_else { } } -impl_float! { f32, f64 } +impl_float! { f16, f32, f64 } impl_else! { i8, i16, i32, i64, isize, u8, u16, u32, u64, usize } /// AltiVec should flush subnormal inputs to zero, but QEMU seems to only flush outputs. diff --git a/library/portable-simd/rust-toolchain.toml b/library/portable-simd/rust-toolchain.toml index 639d07df73374..27d2dd6efbbb8 100644 --- a/library/portable-simd/rust-toolchain.toml +++ b/library/portable-simd/rust-toolchain.toml @@ -1,3 +1,3 @@ [toolchain] -channel = "nightly-2026-01-26" +channel = "nightly-2026-04-28" components = ["rustfmt", "clippy", "miri", "rust-src"] diff --git a/library/portable-simd/subtree-sync.sh b/library/portable-simd/subtree-sync.sh index 18360077623b1..eab56bd03c65d 100755 --- a/library/portable-simd/subtree-sync.sh +++ b/library/portable-simd/subtree-sync.sh @@ -12,8 +12,8 @@ if [ "$(git rev-parse --show-prefix)" != "" ]; then exit 1 fi -if [ "$(git rev-parse HEAD)" != "$(git rev-parse origin/master)" ]; then - echo "$(pwd) is not at origin/master" >&2 +if [ "$(git rev-parse HEAD)" != "$(git rev-parse origin/main)" ]; then + echo "$(pwd) is not at origin/main" >&2 exit 1 fi diff --git a/library/portable-simd/triagebot.toml b/library/portable-simd/triagebot.toml new file mode 100644 index 0000000000000..43048b5e4514c --- /dev/null +++ b/library/portable-simd/triagebot.toml @@ -0,0 +1,44 @@ +## See for documentation +## of these features. + +# Allow users to use labels commands. +# Documentation at: https://forge.rust-lang.org/triagebot/labeling.html +[relabel] +allow-unauthenticated = [ + "A-*", + "C-*", + "E-*", + "F-*", + "I-*", + "ISA-*", + "O-*", +] + +# Allow users to assign 'r?` someone to an issue or PR. +# Documentation at: https://forge.rust-lang.org/triagebot/issue-assignment.html +[assign] +warn_non_default_branch = true + +# Warns when a PR contains merge commits +# Documentation at: https://forge.rust-lang.org/triagebot/no-merge.html +[no-merges] +exclude_titles = ["Sync from"] + +# Canonicalize issue numbers to avoid closing the wrong issue +# when commits are included in upstream sync, as well as warning links in commits. +# Documentation at: https://forge.rust-lang.org/triagebot/issue-links.html +[issue-links] +check-commits = "uncanonicalized" + +# Enable issue transfers within the org +# Documentation at: https://forge.rust-lang.org/triagebot/transfer.html +[transfer] + +# Enable comments linking to triagebot range-diff when a PR is rebased +# onto a different base commit +# Documentation at: https://forge.rust-lang.org/triagebot/range-diff.html +[range-diff] + +# Add link to the review body to review changes since posting it. +# Documentation at: https://forge.rust-lang.org/triagebot/review-changes-since.html +[review-changes-since] diff --git a/library/proc_macro/Cargo.toml b/library/proc_macro/Cargo.toml index 1e5046ca61c39..286080e1bea2e 100644 --- a/library/proc_macro/Cargo.toml +++ b/library/proc_macro/Cargo.toml @@ -9,7 +9,7 @@ std = { path = "../std" } # `core` when resolving doc links. Without this line a different `core` will be # loaded from sysroot causing duplicate lang items and other similar errors. core = { path = "../core" } -rustc-literal-escaper = { version = "0.0.7", features = ["rustc-dep-of-std"] } +rustc-literal-escaper = { version = "0.0.8", features = ["rustc-dep-of-std"] } [features] default = ["rustc-dep-of-std"] diff --git a/library/proc_macro/src/bridge/arena.rs b/library/proc_macro/src/bridge/arena.rs index 5e0393e98fdd2..d4879021f9d87 100644 --- a/library/proc_macro/src/bridge/arena.rs +++ b/library/proc_macro/src/bridge/arena.rs @@ -58,11 +58,10 @@ impl Arena { // Also ensure that this chunk can fit `additional`. new_cap = cmp::max(additional, new_cap); - let mut chunk = Box::new_uninit_slice(new_cap); + let chunk = chunks.push_mut(Box::new_uninit_slice(new_cap)); let Range { start, end } = chunk.as_mut_ptr_range(); self.start.set(start); self.end.set(end); - chunks.push(chunk); } /// Allocates a byte slice with specified size from the current memory diff --git a/library/proc_macro/src/bridge/buffer.rs b/library/proc_macro/src/bridge/buffer.rs index 3760749d83a54..3176b9ea35c8c 100644 --- a/library/proc_macro/src/bridge/buffer.rs +++ b/library/proc_macro/src/bridge/buffer.rs @@ -1,8 +1,7 @@ //! Buffer management for same-process client<->server communication. -use std::io::{self, Write}; use std::mem::{self, ManuallyDrop}; -use std::ops::{Deref, DerefMut}; +use std::ops::Deref; use std::slice; #[repr(C)] @@ -32,13 +31,6 @@ impl Deref for Buffer { } } -impl DerefMut for Buffer { - #[inline] - fn deref_mut(&mut self) -> &mut [u8] { - unsafe { slice::from_raw_parts_mut(self.data, self.len) } - } -} - impl Buffer { #[inline] pub(super) fn new() -> Self { @@ -99,25 +91,6 @@ impl Buffer { } } -impl Write for Buffer { - #[inline] - fn write(&mut self, xs: &[u8]) -> io::Result { - self.extend_from_slice(xs); - Ok(xs.len()) - } - - #[inline] - fn write_all(&mut self, xs: &[u8]) -> io::Result<()> { - self.extend_from_slice(xs); - Ok(()) - } - - #[inline] - fn flush(&mut self) -> io::Result<()> { - Ok(()) - } -} - impl Drop for Buffer { #[inline] fn drop(&mut self) { @@ -128,8 +101,7 @@ impl Drop for Buffer { impl From> for Buffer { fn from(v: Vec) -> Self { - let mut v = ManuallyDrop::new(v); - let (data, len, capacity) = (v.as_mut_ptr(), v.len(), v.capacity()); + let (data, len, capacity) = v.into_raw_parts(); // This utility function is nested in here because it can *only* // be safely called on `Buffer`s created by *this* `proc_macro`. diff --git a/library/proc_macro/src/bridge/client.rs b/library/proc_macro/src/bridge/client.rs index 8f4a79b389f62..48e6245ecf98b 100644 --- a/library/proc_macro/src/bridge/client.rs +++ b/library/proc_macro/src/bridge/client.rs @@ -1,19 +1,14 @@ //! Client-side types. use std::cell::RefCell; -use std::marker::PhantomData; -use std::sync::atomic::AtomicU32; +use std::ops::{Bound, Range}; +use std::sync::Once; +use std::{fmt, mem, panic}; -use super::*; - -#[repr(C)] -pub(super) struct HandleCounters { - pub(super) token_stream: AtomicU32, - pub(super) span: AtomicU32, -} - -static COUNTERS: HandleCounters = - HandleCounters { token_stream: AtomicU32::new(1), span: AtomicU32::new(1) }; +use crate::bridge::{ + ApiTags, BridgeConfig, Buffer, Decode, Diagnostic, Encode, ExpnGlobals, Literal, PanicMessage, + TokenTree, closure, handle, +}; pub(crate) struct TokenStream { handle: handle::Handle, @@ -30,23 +25,40 @@ impl Drop for TokenStream { } impl Encode for TokenStream { + #[inline] fn encode(self, w: &mut Buffer, s: &mut S) { mem::ManuallyDrop::new(self).handle.encode(w, s); } } impl Encode for &TokenStream { + #[inline] fn encode(self, w: &mut Buffer, s: &mut S) { self.handle.encode(w, s); } } impl Decode<'_, '_, S> for TokenStream { + #[inline] fn decode(r: &mut &[u8], s: &mut S) -> Self { TokenStream { handle: handle::Handle::decode(r, s) } } } +impl Encode<()> for crate::TokenStream { + #[inline] + fn encode(self, w: &mut Buffer, s: &mut ()) { + self.0.encode(w, s) + } +} + +impl Decode<'_, '_, ()> for crate::TokenStream { + #[inline] + fn decode(r: &mut &[u8], s: &mut ()) -> Self { + crate::TokenStream(Some(Decode::decode(r, s))) + } +} + #[derive(Copy, Clone, PartialEq, Eq, Hash)] pub(crate) struct Span { handle: handle::Handle, @@ -56,12 +68,14 @@ impl !Send for Span {} impl !Sync for Span {} impl Encode for Span { + #[inline] fn encode(self, w: &mut Buffer, s: &mut S) { self.handle.encode(w, s); } } impl Decode<'_, '_, S> for Span { + #[inline] fn decode(r: &mut &[u8], s: &mut S) -> Self { Span { handle: handle::Handle::decode(r, s) } } @@ -98,7 +112,7 @@ pub(crate) use super::symbol::Symbol; macro_rules! define_client_side { ( - $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)*;)* + $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)?;)* ) => { impl Methods { $(pub(crate) fn $method($($arg: $arg_ty),*) $(-> $ret_ty)? { @@ -121,7 +135,7 @@ macro_rules! define_client_side { } } } -with_api!(self, define_client_side); +with_api!(define_client_side, TokenStream, Span, Symbol); struct Bridge<'a> { /// Reusable buffer (only `clear`-ed, never shrunk), primarily @@ -129,7 +143,7 @@ struct Bridge<'a> { cached_buffer: Buffer, /// Server-side function that the client uses to make requests. - dispatch: closure::Closure<'a, Buffer, Buffer>, + dispatch: closure::Closure<'a>, /// Provided globals for this macro expansion. globals: ExpnGlobals, @@ -199,28 +213,13 @@ pub(crate) fn is_available() -> bool { /// A client-side RPC entry-point, which may be using a different `proc_macro` /// from the one used by the server, but can be invoked compatibly. /// -/// Note that the (phantom) `I` ("input") and `O` ("output") type parameters -/// decorate the `Client` with the RPC "interface" of the entry-point, but -/// do not themselves participate in ABI, at all, only facilitate type-checking. -/// -/// E.g. `Client` is the common proc macro interface, -/// used for `#[proc_macro] fn foo(input: TokenStream) -> TokenStream`, -/// indicating that the RPC input and output will be serialized token streams, -/// and forcing the use of APIs that take/return `S::TokenStream`, server-side. +/// Note that the input and output type parameters are erased. They do not +/// participate in the ABI, so while using the wrong runN method will likely +/// result in a panic, it will not result in UB. #[repr(C)] -pub struct Client { - pub(super) handle_counters: &'static HandleCounters, - +#[derive(Copy, Clone)] +pub struct Client { pub(super) run: extern "C" fn(BridgeConfig<'_>) -> Buffer, - - pub(super) _marker: PhantomData O>, -} - -impl Copy for Client {} -impl Clone for Client { - fn clone(&self) -> Self { - *self - } } fn maybe_install_panic_hook(force_show_panics: bool) { @@ -243,14 +242,13 @@ fn maybe_install_panic_hook(force_show_panics: bool) { /// Client-side helper for handling client panics, entering the bridge, /// deserializing input and serializing output. -// FIXME(eddyb) maybe replace `Bridge::enter` with this? -fn run_client Decode<'a, 's, ()>, R: Encode<()>>( +fn run_client Decode<'a, 's, ()>>( config: BridgeConfig<'_>, - f: impl FnOnce(A) -> R, + f: impl FnOnce(A) -> crate::TokenStream, ) -> Buffer { let BridgeConfig { input: mut buf, dispatch, force_show_panics, .. } = config; - panic::catch_unwind(panic::AssertUnwindSafe(|| { + let res = panic::catch_unwind(panic::AssertUnwindSafe(|| { maybe_install_panic_hook(force_show_panics); // Make sure the symbol store is empty before decoding inputs. @@ -267,23 +265,12 @@ fn run_client Decode<'a, 's, ()>, R: Encode<()>>( // Take the `cached_buffer` back out, for the output value. buf = RefCell::into_inner(state).cached_buffer; - // HACK(eddyb) Separate encoding a success value (`Ok(output)`) - // from encoding a panic (`Err(e: PanicMessage)`) to avoid - // having handles outside the `bridge.enter(|| ...)` scope, and - // to catch panics that could happen while encoding the success. - // - // Note that panics should be impossible beyond this point, but - // this is defensively trying to avoid any accidental panicking - // reaching the `extern "C"` (which should `abort` but might not - // at the moment, so this is also potentially preventing UB). - buf.clear(); - Ok::<_, ()>(output).encode(&mut buf, &mut ()); - })) - .map_err(PanicMessage::from) - .unwrap_or_else(|e| { - buf.clear(); - Err::<(), _>(e).encode(&mut buf, &mut ()); - }); + output + })); + + // Serialize response of type `Result`. + buf.clear(); + res.map_err(PanicMessage::from).encode(&mut buf, &mut ()); // Now that a response has been serialized, invalidate all symbols // registered with the interner. @@ -291,82 +278,22 @@ fn run_client Decode<'a, 's, ()>, R: Encode<()>>( buf } -impl Client { +impl Client { pub const fn expand1(f: impl Fn(crate::TokenStream) -> crate::TokenStream + Copy) -> Self { Client { - handle_counters: &COUNTERS, run: super::selfless_reify::reify_to_extern_c_fn_hrt_bridge(move |bridge| { - run_client(bridge, |input| f(crate::TokenStream(Some(input))).0) + run_client(bridge, f) }), - _marker: PhantomData, } } -} -impl Client<(crate::TokenStream, crate::TokenStream), crate::TokenStream> { pub const fn expand2( f: impl Fn(crate::TokenStream, crate::TokenStream) -> crate::TokenStream + Copy, ) -> Self { Client { - handle_counters: &COUNTERS, run: super::selfless_reify::reify_to_extern_c_fn_hrt_bridge(move |bridge| { - run_client(bridge, |(input, input2)| { - f(crate::TokenStream(Some(input)), crate::TokenStream(Some(input2))).0 - }) + run_client(bridge, |(input, input2)| f(input, input2)) }), - _marker: PhantomData, - } - } -} - -#[repr(C)] -#[derive(Copy, Clone)] -pub enum ProcMacro { - CustomDerive { - trait_name: &'static str, - attributes: &'static [&'static str], - client: Client, - }, - - Attr { - name: &'static str, - client: Client<(crate::TokenStream, crate::TokenStream), crate::TokenStream>, - }, - - Bang { - name: &'static str, - client: Client, - }, -} - -impl ProcMacro { - pub fn name(&self) -> &'static str { - match self { - ProcMacro::CustomDerive { trait_name, .. } => trait_name, - ProcMacro::Attr { name, .. } => name, - ProcMacro::Bang { name, .. } => name, } } - - pub const fn custom_derive( - trait_name: &'static str, - attributes: &'static [&'static str], - expand: impl Fn(crate::TokenStream) -> crate::TokenStream + Copy, - ) -> Self { - ProcMacro::CustomDerive { trait_name, attributes, client: Client::expand1(expand) } - } - - pub const fn attr( - name: &'static str, - expand: impl Fn(crate::TokenStream, crate::TokenStream) -> crate::TokenStream + Copy, - ) -> Self { - ProcMacro::Attr { name, client: Client::expand2(expand) } - } - - pub const fn bang( - name: &'static str, - expand: impl Fn(crate::TokenStream) -> crate::TokenStream + Copy, - ) -> Self { - ProcMacro::Bang { name, client: Client::expand1(expand) } - } } diff --git a/library/proc_macro/src/bridge/closure.rs b/library/proc_macro/src/bridge/closure.rs index e5133907854b2..88c4dd6630b15 100644 --- a/library/proc_macro/src/bridge/closure.rs +++ b/library/proc_macro/src/bridge/closure.rs @@ -1,10 +1,12 @@ -//! Closure type (equivalent to `&mut dyn FnMut(A) -> R`) that's `repr(C)`. +//! Closure type (equivalent to `&mut dyn FnMut(Buffer) -> Buffer`) that's `repr(C)`. use std::marker::PhantomData; +use super::Buffer; + #[repr(C)] -pub(super) struct Closure<'a, A, R> { - call: unsafe extern "C" fn(*mut Env, A) -> R, +pub(super) struct Closure<'a> { + call: extern "C" fn(*mut Env, Buffer) -> Buffer, env: *mut Env, // Prevent Send and Sync impls. // @@ -14,17 +16,17 @@ pub(super) struct Closure<'a, A, R> { struct Env; -impl<'a, A, R, F: FnMut(A) -> R> From<&'a mut F> for Closure<'a, A, R> { +impl<'a, F: FnMut(Buffer) -> Buffer> From<&'a mut F> for Closure<'a> { fn from(f: &'a mut F) -> Self { - unsafe extern "C" fn call R>(env: *mut Env, arg: A) -> R { + extern "C" fn call Buffer>(env: *mut Env, arg: Buffer) -> Buffer { unsafe { (*(env as *mut _ as *mut F))(arg) } } - Closure { call: call::, env: f as *mut _ as *mut Env, _marker: PhantomData } + Closure { call: call::, env: f as *mut _ as *mut Env, _marker: PhantomData } } } -impl<'a, A, R> Closure<'a, A, R> { - pub(super) fn call(&mut self, arg: A) -> R { - unsafe { (self.call)(self.env, arg) } +impl<'a> Closure<'a> { + pub(super) fn call(&mut self, arg: Buffer) -> Buffer { + (self.call)(self.env, arg) } } diff --git a/library/proc_macro/src/bridge/mod.rs b/library/proc_macro/src/bridge/mod.rs index 244ab7d81b022..8b60043f5dc2a 100644 --- a/library/proc_macro/src/bridge/mod.rs +++ b/library/proc_macro/src/bridge/mod.rs @@ -9,80 +9,75 @@ #![deny(unsafe_code)] use std::hash::Hash; +use std::marker; use std::ops::{Bound, Range}; -use std::sync::Once; -use std::{fmt, marker, mem, panic, thread}; use crate::{Delimiter, Level}; /// Higher-order macro describing the server RPC API, allowing automatic /// generation of type-safe Rust APIs, both client-side and server-side. /// -/// `with_api!(MySelf, my_macro)` expands to: +/// `with_api!(my_macro, MyTokenStream, MySpan, MySymbol)` expands to: /// ```rust,ignore (pseudo-code) /// my_macro! { -/// fn lit_character(ch: char) -> MySelf::Literal; -/// fn lit_span(lit: &MySelf::Literal) -> MySelf::Span; -/// fn lit_set_span(lit: &mut MySelf::Literal, span: MySelf::Span); +/// fn ts_clone(stream: &MyTokenStream) -> MyTokenStream; +/// fn span_debug(span: &MySpan) -> String; /// // ... /// } /// ``` /// -/// The first argument serves to customize the argument/return types, -/// to enable several different usecases: -/// -/// If `MySelf` is just `Self`, then the types are only valid inside -/// a trait or a trait impl, where the trait has associated types -/// for each of the API types. If non-associated types are desired, -/// a module name (`self` in practice) can be used instead of `Self`. +/// The second (`TokenStream`), third (`Span`) and fourth (`Symbol`) +/// argument serve to customize the argument/return types that need +/// special handling, to enable several different representations of +/// these types. macro_rules! with_api { - ($S:ident, $m:ident) => { + ($m:ident, $TokenStream: path, $Span: path, $Symbol: path) => { $m! { fn injected_env_var(var: &str) -> Option; fn track_env_var(var: &str, value: Option<&str>); fn track_path(path: &str); - fn literal_from_str(s: &str) -> Result, ()>; - fn emit_diagnostic(diagnostic: Diagnostic<$S::Span>); - - fn ts_drop(stream: $S::TokenStream); - fn ts_clone(stream: &$S::TokenStream) -> $S::TokenStream; - fn ts_is_empty(stream: &$S::TokenStream) -> bool; - fn ts_expand_expr(stream: &$S::TokenStream) -> Result<$S::TokenStream, ()>; - fn ts_from_str(src: &str) -> $S::TokenStream; - fn ts_to_string(stream: &$S::TokenStream) -> String; + fn literal_from_str(s: &str) -> Result, String>; + fn emit_diagnostic(diagnostic: Diagnostic<$Span>); + + fn ts_drop(stream: $TokenStream); + fn ts_clone(stream: &$TokenStream) -> $TokenStream; + fn ts_is_empty(stream: &$TokenStream) -> bool; + fn ts_expand_expr(stream: &$TokenStream) -> Result<$TokenStream, ()>; + fn ts_from_str(src: &str) -> Result<$TokenStream, String>; + fn ts_to_string(stream: &$TokenStream) -> String; fn ts_from_token_tree( - tree: TokenTree<$S::TokenStream, $S::Span, $S::Symbol>, - ) -> $S::TokenStream; + tree: TokenTree<$TokenStream, $Span, $Symbol>, + ) -> $TokenStream; fn ts_concat_trees( - base: Option<$S::TokenStream>, - trees: Vec>, - ) -> $S::TokenStream; + base: Option<$TokenStream>, + trees: Vec>, + ) -> $TokenStream; fn ts_concat_streams( - base: Option<$S::TokenStream>, - streams: Vec<$S::TokenStream>, - ) -> $S::TokenStream; + base: Option<$TokenStream>, + streams: Vec<$TokenStream>, + ) -> $TokenStream; fn ts_into_trees( - stream: $S::TokenStream - ) -> Vec>; - - fn span_debug(span: $S::Span) -> String; - fn span_parent(span: $S::Span) -> Option<$S::Span>; - fn span_source(span: $S::Span) -> $S::Span; - fn span_byte_range(span: $S::Span) -> Range; - fn span_start(span: $S::Span) -> $S::Span; - fn span_end(span: $S::Span) -> $S::Span; - fn span_line(span: $S::Span) -> usize; - fn span_column(span: $S::Span) -> usize; - fn span_file(span: $S::Span) -> String; - fn span_local_file(span: $S::Span) -> Option; - fn span_join(span: $S::Span, other: $S::Span) -> Option<$S::Span>; - fn span_subspan(span: $S::Span, start: Bound, end: Bound) -> Option<$S::Span>; - fn span_resolved_at(span: $S::Span, at: $S::Span) -> $S::Span; - fn span_source_text(span: $S::Span) -> Option; - fn span_save_span(span: $S::Span) -> usize; - fn span_recover_proc_macro_span(id: usize) -> $S::Span; - - fn symbol_normalize_and_validate_ident(string: &str) -> Result<$S::Symbol, ()>; + stream: $TokenStream + ) -> Vec>; + + fn span_debug(span: $Span) -> String; + fn span_parent(span: $Span) -> Option<$Span>; + fn span_source(span: $Span) -> $Span; + fn span_byte_range(span: $Span) -> Range; + fn span_start(span: $Span) -> $Span; + fn span_end(span: $Span) -> $Span; + fn span_line(span: $Span) -> usize; + fn span_column(span: $Span) -> usize; + fn span_file(span: $Span) -> String; + fn span_local_file(span: $Span) -> Option; + fn span_join(span: $Span, other: $Span) -> Option<$Span>; + fn span_subspan(span: $Span, start: Bound, end: Bound) -> Option<$Span>; + fn span_resolved_at(span: $Span, at: $Span) -> $Span; + fn span_source_text(span: $Span) -> Option; + fn span_save_span(span: $Span) -> usize; + fn span_recover_proc_macro_span(id: usize) -> $Span; + + fn symbol_normalize_and_validate_ident(string: &str) -> Result<$Symbol, ()>; } }; } @@ -104,6 +99,8 @@ mod handle; #[macro_use] #[forbid(unsafe_code)] mod rpc; +#[forbid(unsafe_code)] +mod panic_message; #[allow(unsafe_code)] mod selfless_reify; #[forbid(unsafe_code)] @@ -112,7 +109,7 @@ pub mod server; mod symbol; use buffer::Buffer; -pub use rpc::PanicMessage; +pub use panic_message::PanicMessage; use rpc::{Decode, Encode}; /// Configuration for establishing an active connection between a server and a @@ -126,7 +123,7 @@ pub struct BridgeConfig<'a> { input: Buffer, /// Server-side function that the client uses to make requests. - dispatch: closure::Closure<'a, Buffer, Buffer>, + dispatch: closure::Closure<'a>, /// If 'true', always invoke the default panic hook force_show_panics: bool, @@ -137,7 +134,7 @@ impl !Sync for BridgeConfig<'_> {} macro_rules! declare_tags { ( - $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)*;)* + $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)?;)* ) => { #[allow(non_camel_case_types)] pub(super) enum ApiTags { @@ -146,7 +143,7 @@ macro_rules! declare_tags { rpc_encode_decode!(enum ApiTags { $($method),* }); } } -with_api!(self, declare_tags); +with_api!(declare_tags, __, __, __); /// Helper to wrap associated types to allow trait impl dispatch. /// That is, normally a pair of impls for `T::Foo` and `T::Bar` @@ -166,18 +163,21 @@ struct Marked { impl Mark for Marked { type Unmarked = T; + #[inline] fn mark(unmarked: Self::Unmarked) -> Self { Marked { value: unmarked, _marker: marker::PhantomData } } + #[inline] fn unmark(self) -> Self::Unmarked { self.value } } -impl<'a, T, M> Mark for &'a Marked { +impl<'a, T> Mark for &'a Marked { type Unmarked = &'a T; fn mark(_: Self::Unmarked) -> Self { unreachable!() } + #[inline] fn unmark(self) -> Self::Unmarked { &self.value } @@ -185,10 +185,12 @@ impl<'a, T, M> Mark for &'a Marked { impl Mark for Vec { type Unmarked = Vec; + #[inline] fn mark(unmarked: Self::Unmarked) -> Self { // Should be a no-op due to std's in-place collect optimizations. unmarked.into_iter().map(T::mark).collect() } + #[inline] fn unmark(self) -> Self::Unmarked { // Should be a no-op due to std's in-place collect optimizations. self.into_iter().map(T::unmark).collect() @@ -200,9 +202,11 @@ macro_rules! mark_noop { $( impl Mark for $ty { type Unmarked = Self; + #[inline] fn mark(unmarked: Self::Unmarked) -> Self { unmarked } + #[inline] fn unmark(self) -> Self::Unmarked { self } @@ -220,6 +224,8 @@ mark_noop! { Delimiter, LitKind, Level, + Bound, + Range, } rpc_encode_decode!( @@ -278,11 +284,13 @@ macro_rules! mark_compound { (struct $name:ident <$($T:ident),+> { $($field:ident),* $(,)? }) => { impl<$($T: Mark),+> Mark for $name <$($T),+> { type Unmarked = $name <$($T::Unmarked),+>; + #[inline] fn mark(unmarked: Self::Unmarked) -> Self { $name { $($field: Mark::mark(unmarked.$field)),* } } + #[inline] fn unmark(self) -> Self::Unmarked { $name { $($field: Mark::unmark(self.$field)),* @@ -293,6 +301,7 @@ macro_rules! mark_compound { (enum $name:ident <$($T:ident),+> { $($variant:ident $(($field:ident))?),* $(,)? }) => { impl<$($T: Mark),+> Mark for $name <$($T),+> { type Unmarked = $name <$($T::Unmarked),+>; + #[inline] fn mark(unmarked: Self::Unmarked) -> Self { match unmarked { $($name::$variant $(($field))? => { @@ -300,6 +309,7 @@ macro_rules! mark_compound { })* } } + #[inline] fn unmark(self) -> Self::Unmarked { match self { $($name::$variant $(($field))? => { @@ -318,7 +328,7 @@ macro_rules! compound_traits { }; } -compound_traits!( +rpc_encode_decode!( enum Bound { Included(x), Excluded(x), @@ -390,7 +400,7 @@ pub struct Literal { pub span: Span, } -compound_traits!(struct Literal { kind, symbol, suffix, span }); +compound_traits!(struct Literal { kind, symbol, suffix, span }); #[derive(Clone)] pub enum TokenTree { @@ -434,6 +444,6 @@ compound_traits!( struct ExpnGlobals { def_site, call_site, mixed_site } ); -compound_traits!( +rpc_encode_decode!( struct Range { start, end } ); diff --git a/library/proc_macro/src/bridge/panic_message.rs b/library/proc_macro/src/bridge/panic_message.rs new file mode 100644 index 0000000000000..a91bdddea576c --- /dev/null +++ b/library/proc_macro/src/bridge/panic_message.rs @@ -0,0 +1,71 @@ +use std::any::Any; + +use crate::bridge::{Buffer, Decode, Encode}; + +/// Simplified version of panic payloads, ignoring +/// types other than `&'static str` and `String`. +pub enum PanicMessage { + StaticStr(&'static str), + String(String), + Unknown, +} + +impl From> for PanicMessage { + fn from(payload: Box) -> Self { + if let Some(s) = payload.downcast_ref::<&'static str>() { + return PanicMessage::StaticStr(s); + } + if let Ok(s) = payload.downcast::() { + return PanicMessage::String(*s); + } + PanicMessage::Unknown + } +} + +impl From for Box { + fn from(val: PanicMessage) -> Self { + match val { + PanicMessage::StaticStr(s) => Box::new(s), + PanicMessage::String(s) => Box::new(s), + PanicMessage::Unknown => { + struct UnknownPanicMessage; + Box::new(UnknownPanicMessage) + } + } + } +} + +impl PanicMessage { + pub fn as_str(&self) -> Option<&str> { + match self { + PanicMessage::StaticStr(s) => Some(s), + PanicMessage::String(s) => Some(s), + PanicMessage::Unknown => None, + } + } + + pub fn into_string(self) -> Option { + match self { + PanicMessage::StaticStr(s) => Some(s.into()), + PanicMessage::String(s) => Some(s), + PanicMessage::Unknown => None, + } + } +} + +impl Encode for PanicMessage { + #[inline] + fn encode(self, w: &mut Buffer, s: &mut S) { + self.as_str().encode(w, s); + } +} + +impl Decode<'_, '_, S> for PanicMessage { + #[inline] + fn decode(r: &mut &[u8], s: &mut S) -> Self { + match Option::::decode(r, s) { + Some(s) => PanicMessage::String(s), + None => PanicMessage::Unknown, + } + } +} diff --git a/library/proc_macro/src/bridge/rpc.rs b/library/proc_macro/src/bridge/rpc.rs index 63329c8c02601..2c72497ad2723 100644 --- a/library/proc_macro/src/bridge/rpc.rs +++ b/library/proc_macro/src/bridge/rpc.rs @@ -1,7 +1,5 @@ //! Serialization for client-server communication. -use std::any::Any; -use std::io::Write; use std::num::NonZero; use super::buffer::Buffer; @@ -17,12 +15,14 @@ pub(super) trait Decode<'a, 's, S>: Sized { macro_rules! rpc_encode_decode { (le $ty:ty) => { impl Encode for $ty { + #[inline] fn encode(self, w: &mut Buffer, _: &mut S) { w.extend_from_array(&self.to_le_bytes()); } } impl Decode<'_, '_, S> for $ty { + #[inline] fn decode(r: &mut &[u8], _: &mut S) -> Self { const N: usize = size_of::<$ty>(); @@ -44,6 +44,7 @@ macro_rules! rpc_encode_decode { impl<'a, S, $($($T: for<'s> Decode<'a, 's, S>),+)?> Decode<'a, '_, S> for $name $(<$($T),+>)? { + #[inline] fn decode(r: &mut &'a [u8], s: &mut S) -> Self { $name { $($field: Decode::decode(r, s)),* @@ -52,63 +53,61 @@ macro_rules! rpc_encode_decode { } }; (enum $name:ident $(<$($T:ident),+>)? { $($variant:ident $(($field:ident))*),* $(,)? }) => { - impl),+)?> Encode for $name $(<$($T),+>)? { - fn encode(self, w: &mut Buffer, s: &mut S) { - // HACK(eddyb): `Tag` enum duplicated between the - // two impls as there's no other place to stash it. - #[allow(non_camel_case_types)] - #[repr(u8)] - enum Tag { $($variant),* } - - match self { - $($name::$variant $(($field))* => { - (Tag::$variant as u8).encode(w, s); - $($field.encode(w, s);)* - })* + #[allow(non_upper_case_globals, non_camel_case_types)] + const _: () = { + #[repr(u8)] enum Tag { $($variant),* } + + $(const $variant: u8 = Tag::$variant as u8;)* + + impl),+)?> Encode for $name $(<$($T),+>)? { + #[inline] + fn encode(self, w: &mut Buffer, s: &mut S) { + match self { + $($name::$variant $(($field))* => { + $variant.encode(w, s); + $($field.encode(w, s);)* + })* + } } } - } - impl<'a, S, $($($T: for<'s> Decode<'a, 's, S>),+)?> Decode<'a, '_, S> - for $name $(<$($T),+>)? - { - fn decode(r: &mut &'a [u8], s: &mut S) -> Self { - // HACK(eddyb): `Tag` enum duplicated between the - // two impls as there's no other place to stash it. - #[allow(non_upper_case_globals, non_camel_case_types)] - mod tag { - #[repr(u8)] enum Tag { $($variant),* } - - $(pub(crate) const $variant: u8 = Tag::$variant as u8;)* - } - - match u8::decode(r, s) { - $(tag::$variant => { - $(let $field = Decode::decode(r, s);)* - $name::$variant $(($field))* - })* - _ => unreachable!(), + impl<'a, S, $($($T: for<'s> Decode<'a, 's, S>),+)?> Decode<'a, '_, S> + for $name $(<$($T),+>)? + { + #[inline] + fn decode(r: &mut &'a [u8], s: &mut S) -> Self { + match u8::decode(r, s) { + $($variant => { + $(let $field = Decode::decode(r, s);)* + $name::$variant $(($field))* + })* + _ => unreachable!(), + } } } - } + }; } } impl Encode for () { + #[inline] fn encode(self, _: &mut Buffer, _: &mut S) {} } impl Decode<'_, '_, S> for () { + #[inline] fn decode(_: &mut &[u8], _: &mut S) -> Self {} } impl Encode for u8 { + #[inline] fn encode(self, w: &mut Buffer, _: &mut S) { w.push(self); } } impl Decode<'_, '_, S> for u8 { + #[inline] fn decode(r: &mut &[u8], _: &mut S) -> Self { let x = r[0]; *r = &r[1..]; @@ -117,15 +116,53 @@ impl Decode<'_, '_, S> for u8 { } rpc_encode_decode!(le u32); +#[cfg(target_pointer_width = "64")] rpc_encode_decode!(le usize); +#[cfg(not(target_pointer_width = "64"))] +const MAX_USIZE_SIZE: usize = 8; + +#[cfg(not(target_pointer_width = "64"))] +impl Encode for usize { + #[inline] + fn encode(self, w: &mut Buffer, _: &mut S) { + const N: usize = size_of::(); + + // We can pad with zeros without changing the value because of + // little endian encoding. + let mut bytes = [0; MAX_USIZE_SIZE]; + bytes[..N].copy_from_slice(&self.to_le_bytes()); + + w.extend_from_array(&bytes); + } +} + +#[cfg(not(target_pointer_width = "64"))] +impl Decode<'_, '_, S> for usize { + #[inline] + fn decode(r: &mut &[u8], _: &mut S) -> Self { + const N: usize = size_of::(); + const { + assert!(N <= MAX_USIZE_SIZE); + } + + let mut bytes = [0; N]; + bytes.copy_from_slice(&r[..N]); + *r = &r[MAX_USIZE_SIZE..]; + + Self::from_le_bytes(bytes) + } +} + impl Encode for bool { + #[inline] fn encode(self, w: &mut Buffer, s: &mut S) { (self as u8).encode(w, s); } } impl Decode<'_, '_, S> for bool { + #[inline] fn decode(r: &mut &[u8], s: &mut S) -> Self { match u8::decode(r, s) { 0 => false, @@ -136,18 +173,21 @@ impl Decode<'_, '_, S> for bool { } impl Encode for NonZero { + #[inline] fn encode(self, w: &mut Buffer, s: &mut S) { self.get().encode(w, s); } } impl Decode<'_, '_, S> for NonZero { + #[inline] fn decode(r: &mut &[u8], s: &mut S) -> Self { Self::new(u32::decode(r, s)).unwrap() } } impl, B: Encode> Encode for (A, B) { + #[inline] fn encode(self, w: &mut Buffer, s: &mut S) { self.0.encode(w, s); self.1.encode(w, s); @@ -157,20 +197,23 @@ impl, B: Encode> Encode for (A, B) { impl<'a, S, A: for<'s> Decode<'a, 's, S>, B: for<'s> Decode<'a, 's, S>> Decode<'a, '_, S> for (A, B) { + #[inline] fn decode(r: &mut &'a [u8], s: &mut S) -> Self { (Decode::decode(r, s), Decode::decode(r, s)) } } impl Encode for &str { + #[inline] fn encode(self, w: &mut Buffer, s: &mut S) { let bytes = self.as_bytes(); bytes.len().encode(w, s); - w.write_all(bytes).unwrap(); + w.extend_from_slice(bytes); } } impl<'a, S> Decode<'a, '_, S> for &'a str { + #[inline] fn decode(r: &mut &'a [u8], s: &mut S) -> Self { let len = usize::decode(r, s); let xs = &r[..len]; @@ -180,18 +223,21 @@ impl<'a, S> Decode<'a, '_, S> for &'a str { } impl Encode for String { + #[inline] fn encode(self, w: &mut Buffer, s: &mut S) { self[..].encode(w, s); } } impl Decode<'_, '_, S> for String { + #[inline] fn decode(r: &mut &[u8], s: &mut S) -> Self { <&str>::decode(r, s).to_string() } } impl> Encode for Vec { + #[inline] fn encode(self, w: &mut Buffer, s: &mut S) { self.len().encode(w, s); for x in self { @@ -201,6 +247,7 @@ impl> Encode for Vec { } impl<'a, S, T: for<'s> Decode<'a, 's, S>> Decode<'a, '_, S> for Vec { + #[inline] fn decode(r: &mut &'a [u8], s: &mut S) -> Self { let len = usize::decode(r, s); let mut vec = Vec::with_capacity(len); @@ -210,61 +257,3 @@ impl<'a, S, T: for<'s> Decode<'a, 's, S>> Decode<'a, '_, S> for Vec { vec } } - -/// Simplified version of panic payloads, ignoring -/// types other than `&'static str` and `String`. -pub enum PanicMessage { - StaticStr(&'static str), - String(String), - Unknown, -} - -impl From> for PanicMessage { - fn from(payload: Box) -> Self { - if let Some(s) = payload.downcast_ref::<&'static str>() { - return PanicMessage::StaticStr(s); - } - if let Ok(s) = payload.downcast::() { - return PanicMessage::String(*s); - } - PanicMessage::Unknown - } -} - -impl From for Box { - fn from(val: PanicMessage) -> Self { - match val { - PanicMessage::StaticStr(s) => Box::new(s), - PanicMessage::String(s) => Box::new(s), - PanicMessage::Unknown => { - struct UnknownPanicMessage; - Box::new(UnknownPanicMessage) - } - } - } -} - -impl PanicMessage { - pub fn as_str(&self) -> Option<&str> { - match self { - PanicMessage::StaticStr(s) => Some(s), - PanicMessage::String(s) => Some(s), - PanicMessage::Unknown => None, - } - } -} - -impl Encode for PanicMessage { - fn encode(self, w: &mut Buffer, s: &mut S) { - self.as_str().encode(w, s); - } -} - -impl Decode<'_, '_, S> for PanicMessage { - fn decode(r: &mut &[u8], s: &mut S) -> Self { - match Option::::decode(r, s) { - Some(s) => PanicMessage::String(s), - None => PanicMessage::Unknown, - } - } -} diff --git a/library/proc_macro/src/bridge/selfless_reify.rs b/library/proc_macro/src/bridge/selfless_reify.rs index a53550e0b9e0c..1a9951af8c9f1 100644 --- a/library/proc_macro/src/bridge/selfless_reify.rs +++ b/library/proc_macro/src/bridge/selfless_reify.rs @@ -38,47 +38,27 @@ use std::mem; -// FIXME(eddyb) this could be `trait` impls except for the `const fn` requirement. -macro_rules! define_reify_functions { - ($( - fn $name:ident $(<$($param:ident),*>)? - for $(extern $abi:tt)? fn($($arg:ident: $arg_ty:ty),*) -> $ret_ty:ty; - )+) => { - $(pub(super) const fn $name< - $($($param,)*)? - F: Fn($($arg_ty),*) -> $ret_ty + Copy - >(f: F) -> $(extern $abi)? fn($($arg_ty),*) -> $ret_ty { - // FIXME(eddyb) describe the `F` type (e.g. via `type_name::`) once panic - // formatting becomes possible in `const fn`. - const { assert!(size_of::() == 0, "selfless_reify: closure must be zero-sized"); } - - $(extern $abi)? fn wrapper< - $($($param,)*)? - F: Fn($($arg_ty),*) -> $ret_ty + Copy - >($($arg: $arg_ty),*) -> $ret_ty { - let f = unsafe { - // SAFETY: `F` satisfies all criteria for "out of thin air" - // reconstructability (see module-level doc comment). - mem::MaybeUninit::::uninit().assume_init() - }; - f($($arg),*) - } - let _f_proof = f; - wrapper::< - $($($param,)*)? - F - > - })+ +pub(super) const fn reify_to_extern_c_fn_hrt_bridge< + R, + F: Fn(super::BridgeConfig<'_>) -> R + Copy, +>( + f: F, +) -> extern "C" fn(super::BridgeConfig<'_>) -> R { + // FIXME(eddyb) describe the `F` type (e.g. via `type_name::`) once panic + // formatting becomes possible in `const fn`. + const { + assert!(size_of::() == 0, "selfless_reify: closure must be zero-sized"); } -} - -define_reify_functions! { - fn _reify_to_extern_c_fn_unary for extern "C" fn(arg: A) -> R; - - // HACK(eddyb) this abstraction is used with `for<'a> fn(BridgeConfig<'a>) - // -> T` but that doesn't work with just `reify_to_extern_c_fn_unary` - // because of the `fn` pointer type being "higher-ranked" (i.e. the - // `for<'a>` binder). - // FIXME(eddyb) try to remove the lifetime from `BridgeConfig`, that'd help. - fn reify_to_extern_c_fn_hrt_bridge for extern "C" fn(bridge: super::BridgeConfig<'_>) -> R; + extern "C" fn wrapper) -> R + Copy>( + bridge: super::BridgeConfig<'_>, + ) -> R { + let f = unsafe { + // SAFETY: `F` satisfies all criteria for "out of thin air" + // reconstructability (see module-level doc comment). + mem::conjure_zst::() + }; + f(bridge) + } + let _f_proof = f; + wrapper:: } diff --git a/library/proc_macro/src/bridge/server.rs b/library/proc_macro/src/bridge/server.rs index 073ddb554994c..ff525c6cd7735 100644 --- a/library/proc_macro/src/bridge/server.rs +++ b/library/proc_macro/src/bridge/server.rs @@ -1,9 +1,16 @@ //! Server-side traits. use std::cell::Cell; -use std::marker::PhantomData; +use std::hash::Hash; +use std::ops::{Bound, Range}; +use std::sync::atomic::AtomicU32; +use std::sync::mpsc; +use std::{panic, thread}; -use super::*; +use crate::bridge::{ + ApiTags, BridgeConfig, Buffer, Decode, Diagnostic, Encode, ExpnGlobals, Literal, Mark, Marked, + PanicMessage, TokenTree, client, handle, +}; pub(super) struct HandleStore { token_stream: handle::OwnedStore>, @@ -11,10 +18,13 @@ pub(super) struct HandleStore { } impl HandleStore { - fn new(handle_counters: &'static client::HandleCounters) -> Self { + fn new() -> Self { + static TOKEN_STREAM: AtomicU32 = AtomicU32::new(1); + static SPAN: AtomicU32 = AtomicU32::new(1); + HandleStore { - token_stream: handle::OwnedStore::new(&handle_counters.token_stream), - span: handle::InternedStore::new(&handle_counters.span), + token_stream: handle::OwnedStore::new(&TOKEN_STREAM), + span: handle::InternedStore::new(&SPAN), } } } @@ -53,17 +63,12 @@ impl Decode<'_, '_, HandleStore> for MarkedSpan { } } -struct Dispatcher { - handle_store: HandleStore, - server: S, -} - -macro_rules! define_server_dispatcher_impl { +macro_rules! define_server { ( - $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)*;)* + $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)?;)* ) => { pub trait Server { - type TokenStream: 'static + Clone; + type TokenStream: 'static + Clone + Default; type Span: 'static + Copy + Eq + Hash; type Symbol: 'static; @@ -77,22 +82,21 @@ macro_rules! define_server_dispatcher_impl { $(fn $method(&mut self, $($arg: $arg_ty),*) $(-> $ret_ty)?;)* } + } +} +with_api!(define_server, Self::TokenStream, Self::Span, Self::Symbol); - // FIXME(eddyb) `pub` only for `ExecutionStrategy` below. - pub trait DispatcherTrait { - // HACK(eddyb) these are here to allow `Self::$name` to work below. - type TokenStream; - type Span; - type Symbol; - - fn dispatch(&mut self, buf: Buffer) -> Buffer; - } - - impl DispatcherTrait for Dispatcher { - type TokenStream = MarkedTokenStream; - type Span = MarkedSpan; - type Symbol = MarkedSymbol; +// FIXME(eddyb) `pub` only for `ExecutionStrategy` below. +pub struct Dispatcher { + handle_store: HandleStore, + server: S, +} +macro_rules! define_dispatcher { + ( + $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)?;)* + ) => { + impl Dispatcher { fn dispatch(&mut self, mut buf: Buffer) -> Buffer { let Dispatcher { handle_store, server } = self; @@ -102,9 +106,7 @@ macro_rules! define_server_dispatcher_impl { let mut call_method = || { $(let $arg = <$arg_ty>::decode(&mut reader, handle_store).unmark();)* let r = server.$method($($arg),*); - $( - let r: $ret_ty = Mark::mark(r); - )* + $(let r: $ret_ty = Mark::mark(r);)? r }; // HACK(eddyb) don't use `panic::catch_unwind` in a panic. @@ -127,12 +129,15 @@ macro_rules! define_server_dispatcher_impl { } } } -with_api!(Self, define_server_dispatcher_impl); +with_api!(define_dispatcher, MarkedTokenStream, MarkedSpan, MarkedSymbol); +// This trait is currently only implemented and used once, inside of this crate. +// We keep it public to allow implementing more complex execution strategies in +// the future, such as wasm proc-macros. pub trait ExecutionStrategy { fn run_bridge_and_client( &self, - dispatcher: &mut impl DispatcherTrait, + dispatcher: &mut Dispatcher, input: Buffer, run_client: extern "C" fn(BridgeConfig<'_>) -> Buffer, force_show_panics: bool, @@ -171,110 +176,78 @@ impl Drop for RunningSameThreadGuard { } } -pub struct MaybeCrossThread

{ - cross_thread: bool, - marker: PhantomData

, +pub struct MaybeCrossThread { + pub cross_thread: bool, } -impl

MaybeCrossThread

{ - pub const fn new(cross_thread: bool) -> Self { - MaybeCrossThread { cross_thread, marker: PhantomData } - } -} +pub const SAME_THREAD: MaybeCrossThread = MaybeCrossThread { cross_thread: false }; +pub const CROSS_THREAD: MaybeCrossThread = MaybeCrossThread { cross_thread: true }; -impl

ExecutionStrategy for MaybeCrossThread

-where - P: MessagePipe + Send + 'static, -{ +impl ExecutionStrategy for MaybeCrossThread { fn run_bridge_and_client( &self, - dispatcher: &mut impl DispatcherTrait, + dispatcher: &mut Dispatcher, input: Buffer, run_client: extern "C" fn(BridgeConfig<'_>) -> Buffer, force_show_panics: bool, ) -> Buffer { if self.cross_thread || ALREADY_RUNNING_SAME_THREAD.get() { - >::new().run_bridge_and_client( - dispatcher, - input, - run_client, - force_show_panics, - ) - } else { - SameThread.run_bridge_and_client(dispatcher, input, run_client, force_show_panics) - } - } -} - -pub struct SameThread; - -impl ExecutionStrategy for SameThread { - fn run_bridge_and_client( - &self, - dispatcher: &mut impl DispatcherTrait, - input: Buffer, - run_client: extern "C" fn(BridgeConfig<'_>) -> Buffer, - force_show_panics: bool, - ) -> Buffer { - let _guard = RunningSameThreadGuard::new(); - - let mut dispatch = |buf| dispatcher.dispatch(buf); - - run_client(BridgeConfig { input, dispatch: (&mut dispatch).into(), force_show_panics }) - } -} - -pub struct CrossThread

(PhantomData

); - -impl

CrossThread

{ - pub const fn new() -> Self { - CrossThread(PhantomData) - } -} + let (mut server, mut client) = MessagePipe::new(); + + let join_handle = thread::spawn(move || { + let mut dispatch = |b: Buffer| -> Buffer { + client.send(b); + client.recv().expect("server died while client waiting for reply") + }; + + run_client(BridgeConfig { + input, + dispatch: (&mut dispatch).into(), + force_show_panics, + }) + }); + + while let Some(b) = server.recv() { + server.send(dispatcher.dispatch(b)); + } -impl

ExecutionStrategy for CrossThread

-where - P: MessagePipe + Send + 'static, -{ - fn run_bridge_and_client( - &self, - dispatcher: &mut impl DispatcherTrait, - input: Buffer, - run_client: extern "C" fn(BridgeConfig<'_>) -> Buffer, - force_show_panics: bool, - ) -> Buffer { - let (mut server, mut client) = P::new(); + join_handle.join().unwrap() + } else { + let _guard = RunningSameThreadGuard::new(); - let join_handle = thread::spawn(move || { - let mut dispatch = |b: Buffer| -> Buffer { - client.send(b); - client.recv().expect("server died while client waiting for reply") - }; + let mut dispatch = |buf| dispatcher.dispatch(buf); run_client(BridgeConfig { input, dispatch: (&mut dispatch).into(), force_show_panics }) - }); - - while let Some(b) = server.recv() { - server.send(dispatcher.dispatch(b)); } - - join_handle.join().unwrap() } } /// A message pipe used for communicating between server and client threads. -pub trait MessagePipe: Sized { +struct MessagePipe { + tx: mpsc::SyncSender, + rx: mpsc::Receiver, +} + +impl MessagePipe { /// Creates a new pair of endpoints for the message pipe. - fn new() -> (Self, Self); + fn new() -> (Self, Self) { + let (tx1, rx1) = mpsc::sync_channel(1); + let (tx2, rx2) = mpsc::sync_channel(1); + (MessagePipe { tx: tx1, rx: rx2 }, MessagePipe { tx: tx2, rx: rx1 }) + } /// Send a message to the other endpoint of this pipe. - fn send(&mut self, value: T); + fn send(&mut self, value: T) { + self.tx.send(value).unwrap(); + } /// Receive a message from the other endpoint of this pipe. /// /// Returns `None` if the other end of the pipe has been destroyed, and no /// message was received. - fn recv(&mut self) -> Option; + fn recv(&mut self) -> Option { + self.rx.recv().ok() + } } fn run_server< @@ -283,13 +256,12 @@ fn run_server< O: for<'a, 's> Decode<'a, 's, HandleStore>, >( strategy: &impl ExecutionStrategy, - handle_counters: &'static client::HandleCounters, server: S, input: I, run_client: extern "C" fn(BridgeConfig<'_>) -> Buffer, force_show_panics: bool, ) -> Result { - let mut dispatcher = Dispatcher { handle_store: HandleStore::new(handle_counters), server }; + let mut dispatcher = Dispatcher { handle_store: HandleStore::new(), server }; let globals = dispatcher.server.globals(); @@ -302,8 +274,8 @@ fn run_server< Result::decode(&mut &buf[..], &mut dispatcher.handle_store) } -impl client::Client { - pub fn run( +impl client::Client { + pub fn run1( &self, strategy: &impl ExecutionStrategy, server: S, @@ -312,23 +284,13 @@ impl client::Client { ) -> Result where S: Server, - S::TokenStream: Default, { - let client::Client { handle_counters, run, _marker } = *self; - run_server( - strategy, - handle_counters, - server, - >::mark(input), - run, - force_show_panics, - ) - .map(|s| >>::unmark(s).unwrap_or_default()) + let client::Client { run } = *self; + run_server(strategy, server, >::mark(input), run, force_show_panics) + .map(|s| >>::unmark(s).unwrap_or_default()) } -} -impl client::Client<(crate::TokenStream, crate::TokenStream), crate::TokenStream> { - pub fn run( + pub fn run2( &self, strategy: &impl ExecutionStrategy, server: S, @@ -338,12 +300,10 @@ impl client::Client<(crate::TokenStream, crate::TokenStream), crate::TokenStream ) -> Result where S: Server, - S::TokenStream: Default, { - let client::Client { handle_counters, run, _marker } = *self; + let client::Client { run } = *self; run_server( strategy, - handle_counters, server, (>::mark(input), >::mark(input2)), run, diff --git a/library/proc_macro/src/bridge/symbol.rs b/library/proc_macro/src/bridge/symbol.rs index 2a04f7d808bd5..1e632489f31e1 100644 --- a/library/proc_macro/src/bridge/symbol.rs +++ b/library/proc_macro/src/bridge/symbol.rs @@ -10,9 +10,10 @@ //! proc_macro, this module should probably be removed or simplified. use std::cell::RefCell; +use std::fmt; use std::num::NonZero; -use super::*; +use crate::bridge::{Buffer, Decode, Encode, Mark, arena, client, fxhash, server}; /// Handle for a symbol string stored within the Interner. #[derive(Copy, Clone, PartialEq, Eq, Hash)] diff --git a/library/proc_macro/src/lib.rs b/library/proc_macro/src/lib.rs index 49b6f2ae41f89..2f026fb81ee1b 100644 --- a/library/proc_macro/src/lib.rs +++ b/library/proc_macro/src/lib.rs @@ -27,6 +27,8 @@ #![feature(restricted_std)] #![feature(rustc_attrs)] #![feature(extend_one)] +#![feature(mem_conjure_zst)] +#![feature(f16)] #![recursion_limit = "256"] #![allow(internal_features)] #![deny(ffi_unwind_calls)] @@ -35,7 +37,7 @@ #![warn(unreachable_pub)] #![deny(unsafe_op_in_unsafe_fn)] -#[unstable(feature = "proc_macro_internals", issue = "27812")] +#[unstable(feature = "proc_macro_internals", issue = "none")] #[doc(hidden)] pub mod bridge; @@ -43,7 +45,9 @@ mod diagnostic; mod escape; mod to_tokens; +use core::convert::From; use core::ops::BitOr; +use std::borrow::Cow; use std::ffi::CStr; use std::ops::{Range, RangeBounds}; use std::path::PathBuf; @@ -52,8 +56,6 @@ use std::{error, fmt}; #[unstable(feature = "proc_macro_diagnostic", issue = "54140")] pub use diagnostic::{Diagnostic, Level, MultiSpan}; -#[unstable(feature = "proc_macro_value", issue = "136652")] -pub use rustc_literal_escaper::EscapeError; use rustc_literal_escaper::{ MixedUnit, unescape_byte, unescape_byte_str, unescape_c_str, unescape_char, unescape_str, }; @@ -63,9 +65,139 @@ pub use to_tokens::ToTokens; use crate::bridge::client::Methods as BridgeMethods; use crate::escape::{EscapeOptions, escape_bytes}; +/// Mostly relating to malformed escape sequences, but also a few other problems. +#[unstable(feature = "proc_macro_value", issue = "136652")] +#[derive(Debug, PartialEq, Eq)] +#[non_exhaustive] +pub enum EscapeError { + /// Expected 1 char, but 0 were found. + ZeroChars, + /// Expected 1 char, but more than 1 were found. + MoreThanOneChar, + + /// Escaped '\' character without continuation. + LoneSlash, + /// Invalid escape character (e.g. '\z'). + InvalidEscape, + /// Raw '\r' encountered. + BareCarriageReturn, + /// Raw '\r' encountered in raw string. + BareCarriageReturnInRawString, + /// Unescaped character that was expected to be escaped (e.g. raw '\t'). + EscapeOnlyChar, + + /// Numeric character escape is too short (e.g. '\x1'). + TooShortHexEscape, + /// Invalid character in numeric escape (e.g. '\xz') + InvalidCharInHexEscape, + /// Character code in numeric escape is non-ascii (e.g. '\xFF'). + OutOfRangeHexEscape, + + /// '\u' not followed by '{'. + NoBraceInUnicodeEscape, + /// Non-hexadecimal value in '\u{..}'. + InvalidCharInUnicodeEscape, + /// '\u{}' + EmptyUnicodeEscape, + /// No closing brace in '\u{..}', e.g. '\u{12'. + UnclosedUnicodeEscape, + /// '\u{_12}' + LeadingUnderscoreUnicodeEscape, + /// More than 6 characters in '\u{..}', e.g. '\u{10FFFF_FF}' + OverlongUnicodeEscape, + /// Invalid in-bound unicode character code, e.g. '\u{DFFF}'. + LoneSurrogateUnicodeEscape, + /// Out of bounds unicode character code, e.g. '\u{FFFFFF}'. + OutOfRangeUnicodeEscape, + + /// Unicode escape code in byte literal. + UnicodeEscapeInByte, + /// Non-ascii character in byte literal, byte string literal, or raw byte string literal. + NonAsciiCharInByte, + + /// `\0` in a C string literal. + NulInCStr, + + /// After a line ending with '\', the next line contains whitespace + /// characters that are not skipped. + UnskippedWhitespaceWarning, + + /// After a line ending with '\', multiple lines are skipped. + MultipleSkippedLinesWarning, +} + +#[unstable(feature = "proc_macro_value", issue = "136652")] +#[doc(hidden)] +impl From for EscapeError { + fn from(value: rustc_literal_escaper::EscapeError) -> Self { + use rustc_literal_escaper::EscapeError as EE; + + match value { + EE::ZeroChars => Self::ZeroChars, + EE::MoreThanOneChar => Self::MoreThanOneChar, + EE::LoneSlash => Self::LoneSlash, + EE::InvalidEscape => Self::InvalidEscape, + EE::BareCarriageReturn => Self::BareCarriageReturn, + EE::BareCarriageReturnInRawString => Self::BareCarriageReturnInRawString, + EE::EscapeOnlyChar => Self::EscapeOnlyChar, + EE::TooShortHexEscape => Self::TooShortHexEscape, + EE::InvalidCharInHexEscape => Self::InvalidCharInHexEscape, + EE::OutOfRangeHexEscape => Self::OutOfRangeHexEscape, + EE::NoBraceInUnicodeEscape => Self::NoBraceInUnicodeEscape, + EE::InvalidCharInUnicodeEscape => Self::InvalidCharInUnicodeEscape, + EE::EmptyUnicodeEscape => Self::EmptyUnicodeEscape, + EE::UnclosedUnicodeEscape => Self::UnclosedUnicodeEscape, + EE::LeadingUnderscoreUnicodeEscape => Self::LeadingUnderscoreUnicodeEscape, + EE::OverlongUnicodeEscape => Self::OverlongUnicodeEscape, + EE::LoneSurrogateUnicodeEscape => Self::LoneSurrogateUnicodeEscape, + EE::OutOfRangeUnicodeEscape => Self::OutOfRangeUnicodeEscape, + EE::UnicodeEscapeInByte => Self::UnicodeEscapeInByte, + EE::NonAsciiCharInByte => Self::NonAsciiCharInByte, + EE::NulInCStr => Self::NulInCStr, + EE::UnskippedWhitespaceWarning => Self::UnskippedWhitespaceWarning, + EE::MultipleSkippedLinesWarning => Self::MultipleSkippedLinesWarning, + } + } +} + +#[unstable(feature = "proc_macro_value", issue = "136652")] +impl error::Error for EscapeError {} + +#[unstable(feature = "proc_macro_value", issue = "136652")] +impl fmt::Display for EscapeError { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.write_str(match self { + Self::ZeroChars => "zero chars", + Self::MoreThanOneChar => "more than one char", + Self::LoneSlash => "lone slash", + Self::InvalidEscape => "invalid escape", + Self::BareCarriageReturn => "bare carriage return", + Self::BareCarriageReturnInRawString => "bare carriage return in raw string", + Self::EscapeOnlyChar => "escape only char", + Self::TooShortHexEscape => "too short hex escape", + Self::InvalidCharInHexEscape => "invalid char in hex escape", + Self::OutOfRangeHexEscape => "out of range hex escape", + Self::NoBraceInUnicodeEscape => "no brace in unicode escape", + Self::InvalidCharInUnicodeEscape => "invalid char in unicode escape", + Self::EmptyUnicodeEscape => "empty unicode escape", + Self::UnclosedUnicodeEscape => "unclosed unicode escape", + Self::LeadingUnderscoreUnicodeEscape => "leading underscore unicode escape", + Self::OverlongUnicodeEscape => "overlong unicode escape", + Self::LoneSurrogateUnicodeEscape => "lone surrogate unicode escape", + Self::OutOfRangeUnicodeEscape => "out of range unicode escape", + Self::UnicodeEscapeInByte => "unicode escape in byte", + Self::NonAsciiCharInByte => "non ascii char in byte", + Self::NulInCStr => "nul in CStr", + Self::UnskippedWhitespaceWarning => "unskipped whitespace warning", + Self::MultipleSkippedLinesWarning => "multiple skipped lines warning", + }) + } +} + /// Errors returned when trying to retrieve a literal unescaped value. #[unstable(feature = "proc_macro_value", issue = "136652")] #[derive(Debug, PartialEq, Eq)] +#[non_exhaustive] pub enum ConversionErrorKind { /// The literal failed to be escaped, take a look at [`EscapeError`] for more information. FailedToUnescape(EscapeError), @@ -109,15 +241,17 @@ impl !Send for TokenStream {} impl !Sync for TokenStream {} /// Error returned from `TokenStream::from_str`. +/// +/// The contained error message is explicitly not guaranteed to be stable in any way, +/// and may change between Rust versions or across compilations. #[stable(feature = "proc_macro_lib", since = "1.15.0")] -#[non_exhaustive] #[derive(Debug)] -pub struct LexError; +pub struct LexError(String); #[stable(feature = "proc_macro_lexerror_impls", since = "1.44.0")] impl fmt::Display for LexError { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - f.write_str("cannot parse string into token stream") + f.write_str(&self.0) } } @@ -161,7 +295,7 @@ impl TokenStream { /// Checks if this `TokenStream` is empty. #[stable(feature = "proc_macro_lib2", since = "1.29.0")] pub fn is_empty(&self) -> bool { - self.0.as_ref().map(|h| BridgeMethods::ts_is_empty(h)).unwrap_or(true) + self.0.as_ref().map(BridgeMethods::ts_is_empty).unwrap_or(true) } /// Parses this `TokenStream` as an expression and attempts to expand any @@ -196,7 +330,7 @@ impl FromStr for TokenStream { type Err = LexError; fn from_str(src: &str) -> Result { - Ok(TokenStream(Some(BridgeMethods::ts_from_str(src)))) + Ok(TokenStream(Some(BridgeMethods::ts_from_str(src).map_err(LexError)?))) } } @@ -440,9 +574,7 @@ pub mod token_stream { type IntoIter = IntoIter; fn into_iter(self) -> IntoIter { - IntoIter( - self.0.map(|v| BridgeMethods::ts_into_trees(v)).unwrap_or_default().into_iter(), - ) + IntoIter(self.0.map(BridgeMethods::ts_into_trees).unwrap_or_default().into_iter()) } } } @@ -460,7 +592,7 @@ pub macro quote($($t:tt)*) { /* compiler built-in */ } -#[unstable(feature = "proc_macro_internals", issue = "27812")] +#[unstable(feature = "proc_macro_internals", issue = "none")] #[doc(hidden)] mod quote; @@ -620,14 +752,14 @@ impl Span { // Used by the implementation of `Span::quote` #[doc(hidden)] - #[unstable(feature = "proc_macro_internals", issue = "27812")] + #[unstable(feature = "proc_macro_internals", issue = "none")] pub fn save_span(&self) -> usize { BridgeMethods::span_save_span(self.0) } // Used by the implementation of `Span::quote` #[doc(hidden)] - #[unstable(feature = "proc_macro_internals", issue = "27812")] + #[unstable(feature = "proc_macro_internals", issue = "none")] pub fn recover_proc_macro_span(id: usize) -> Span { Span(BridgeMethods::span_recover_proc_macro_span(id)) } @@ -1161,7 +1293,7 @@ macro_rules! unsuffixed_int_literals { /// specified on this token, meaning that invocations like /// `Literal::i8_unsuffixed(1)` are equivalent to /// `Literal::u32_unsuffixed(1)`. - /// Literals created from negative numbers might not survive rountrips through + /// Literals created from negative numbers might not survive roundtrips through /// `TokenStream` or strings and may be broken into two tokens (`-` and positive literal). /// /// Literals created through this method have the `Span::call_site()` @@ -1179,6 +1311,63 @@ macro_rules! unsuffixed_int_literals { )*) } +macro_rules! integer_values { + ($($nb:ident => $fn_name:ident,)+) => { + $( + #[doc = concat!( + "Returns the unescaped `", + stringify!($nb), + "` value if the literal is a `", + stringify!($nb), + "` or if it's an \"unmarked\" integer which doesn't overflow.")] + #[unstable(feature = "proc_macro_value", issue = "136652")] + pub fn $fn_name(&self) -> Result<$nb, ConversionErrorKind> { + if self.0.kind != bridge::LitKind::Integer { + return Err(ConversionErrorKind::InvalidLiteralKind); + } + self.with_symbol_and_suffix(|symbol, suffix| { + match suffix { + stringify!($nb) | "" => { + let symbol = strip_underscores(symbol); + let (number, base) = parse_number(&symbol); + $nb::from_str_radix(&number, base as u32).map_err(|_| ConversionErrorKind::InvalidLiteralKind) + } + _ => Err(ConversionErrorKind::InvalidLiteralKind), + } + }) + } + )+ + } +} + +macro_rules! float_values { + ($($nb:ident => $fn_name:ident,)+) => { + $( + #[doc = concat!( + "Returns the unescaped `", + stringify!($nb), + "` value if the literal is a `", + stringify!($nb), + "` or if it's an \"unmarked\" float which doesn't overflow.")] + #[unstable(feature = "proc_macro_value", issue = "136652")] + pub fn $fn_name(&self) -> Result<$nb, ConversionErrorKind> { + if self.0.kind != bridge::LitKind::Float { + return Err(ConversionErrorKind::InvalidLiteralKind); + } + self.with_symbol_and_suffix(|symbol, suffix| { + match suffix { + stringify!($nb) | "" => { + let number = strip_underscores(symbol); + $nb::from_str(&number).map_err(|_| ConversionErrorKind::InvalidLiteralKind) + } + _ => Err(ConversionErrorKind::InvalidLiteralKind), + } + }) + } + )+ + } +} + impl Literal { fn new(kind: bridge::LitKind, value: &str, suffix: Option<&str>) -> Self { Literal(bridge::Literal { @@ -1224,7 +1413,7 @@ impl Literal { /// This constructor is similar to those like `Literal::i8_unsuffixed` where /// the float's value is emitted directly into the token but no suffix is /// used, so it may be inferred to be a `f64` later in the compiler. - /// Literals created from negative numbers might not survive rountrips through + /// Literals created from negative numbers might not survive roundtrips through /// `TokenStream` or strings and may be broken into two tokens (`-` and positive literal). /// /// # Panics @@ -1249,7 +1438,7 @@ impl Literal { /// specified is the preceding part of the token and `f32` is the suffix of /// the token. This token will always be inferred to be an `f32` in the /// compiler. - /// Literals created from negative numbers might not survive rountrips through + /// Literals created from negative numbers might not survive roundtrips through /// `TokenStream` or strings and may be broken into two tokens (`-` and positive literal). /// /// # Panics @@ -1269,7 +1458,7 @@ impl Literal { /// This constructor is similar to those like `Literal::i8_unsuffixed` where /// the float's value is emitted directly into the token but no suffix is /// used, so it may be inferred to be a `f64` later in the compiler. - /// Literals created from negative numbers might not survive rountrips through + /// Literals created from negative numbers might not survive roundtrips through /// `TokenStream` or strings and may be broken into two tokens (`-` and positive literal). /// /// # Panics @@ -1294,7 +1483,7 @@ impl Literal { /// specified is the preceding part of the token and `f64` is the suffix of /// the token. This token will always be inferred to be an `f64` in the /// compiler. - /// Literals created from negative numbers might not survive rountrips through + /// Literals created from negative numbers might not survive roundtrips through /// `TokenStream` or strings and may be broken into two tokens (`-` and positive literal). /// /// # Panics @@ -1457,9 +1646,8 @@ impl Literal { #[unstable(feature = "proc_macro_value", issue = "136652")] pub fn byte_character_value(&self) -> Result { self.0.symbol.with(|symbol| match self.0.kind { - bridge::LitKind::Char => { - unescape_byte(symbol).map_err(ConversionErrorKind::FailedToUnescape) - } + bridge::LitKind::Byte => unescape_byte(symbol) + .map_err(|err| ConversionErrorKind::FailedToUnescape(err.into())), _ => Err(ConversionErrorKind::InvalidLiteralKind), }) } @@ -1468,9 +1656,8 @@ impl Literal { #[unstable(feature = "proc_macro_value", issue = "136652")] pub fn character_value(&self) -> Result { self.0.symbol.with(|symbol| match self.0.kind { - bridge::LitKind::Char => { - unescape_char(symbol).map_err(ConversionErrorKind::FailedToUnescape) - } + bridge::LitKind::Char => unescape_char(symbol) + .map_err(|err| ConversionErrorKind::FailedToUnescape(err.into())), _ => Err(ConversionErrorKind::InvalidLiteralKind), }) } @@ -1493,7 +1680,7 @@ impl Literal { Ok(c) => buf.push(c), Err(err) => { if err.is_fatal() { - error = Some(ConversionErrorKind::FailedToUnescape(err)); + error = Some(ConversionErrorKind::FailedToUnescape(err.into())); } } }, @@ -1524,7 +1711,7 @@ impl Literal { Ok(MixedUnit::HighByte(b)) => buf.push(b.get()), Err(err) => { if err.is_fatal() { - error = Some(ConversionErrorKind::FailedToUnescape(err)); + error = Some(ConversionErrorKind::FailedToUnescape(err.into())); } } }); @@ -1560,7 +1747,7 @@ impl Literal { Ok(b) => buf.push(b), Err(err) => { if err.is_fatal() { - error = Some(ConversionErrorKind::FailedToUnescape(err)); + error = Some(ConversionErrorKind::FailedToUnescape(err.into())); } } }); @@ -1574,6 +1761,82 @@ impl Literal { _ => Err(ConversionErrorKind::InvalidLiteralKind), }) } + + integer_values! { + u8 => u8_value, + u16 => u16_value, + u32 => u32_value, + u64 => u64_value, + u128 => u128_value, + i8 => i8_value, + i16 => i16_value, + i32 => i32_value, + i64 => i64_value, + i128 => i128_value, + } + + float_values! { + f16 => f16_value, + f32 => f32_value, + f64 => f64_value, + // FIXME: `f128` doesn't implement `FromStr` for the moment so we cannot obtain it from + // a `&str`. To be uncommented when it's added. + // f128 => f128_value, + } +} + +#[repr(u32)] +#[derive(PartialEq, Eq)] +enum Base { + Decimal = 10, + Binary = 2, + Octal = 8, + Hexadecimal = 16, +} + +fn parse_number(value: &str) -> (&str, Base) { + let mut iter = value.as_bytes().iter().copied(); + let Some(first_digit) = iter.next() else { + return ("0", Base::Decimal); + }; + let Some(second_digit) = iter.next() else { + return (value, Base::Decimal); + }; + + let mut base = Base::Decimal; + if first_digit == b'0' { + // Attempt to parse encoding base. + match second_digit { + b'b' => { + base = Base::Binary; + } + b'o' => { + base = Base::Octal; + } + b'x' => { + base = Base::Hexadecimal; + } + _ => {} + } + } + + let offset = if base == Base::Decimal { 0 } else { 2 }; + + (&value[offset..], base) +} + +fn strip_underscores(value_s: &str) -> Cow<'_, str> { + let value = value_s.as_bytes(); + if value.iter().copied().all(|c| c != b'_' && c != b'f') { + return Cow::Borrowed(value_s); + } + let mut output = String::with_capacity(value.len()); + for c in value.iter().copied() { + if c != b'_' { + output.push(c as char); + } + } + Cow::Owned(output) } /// Parse a single literal from its stringified representation. @@ -1593,7 +1856,7 @@ impl FromStr for Literal { fn from_str(src: &str) -> Result { match BridgeMethods::literal_from_str(src) { Ok(literal) => Ok(Literal(literal)), - Err(()) => Err(LexError), + Err(msg) => Err(LexError(msg)), } } } diff --git a/library/rtstartup/rsbegin.rs b/library/rtstartup/rsbegin.rs index 62d247fafb7ad..d268090fe77ae 100644 --- a/library/rtstartup/rsbegin.rs +++ b/library/rtstartup/rsbegin.rs @@ -39,12 +39,9 @@ auto trait Freeze {} impl Copy for *mut T {} -#[lang = "drop_in_place"] +#[lang = "drop_glue"] #[inline] -#[allow(unconditional_recursion)] -pub unsafe fn drop_in_place(to_drop: *mut T) { - drop_in_place(to_drop); -} +pub unsafe fn drop_glue(_to_drop: &mut T) {} // Frame unwind info registration // @@ -90,12 +87,12 @@ pub mod eh_frames { unsafe extern "C" fn init() { // register unwind info on module startup - __register_frame_info(&__EH_FRAME_BEGIN__ as *const u8, &mut OBJ as *mut _ as *mut u8); + __register_frame_info(&__EH_FRAME_BEGIN__ as *const u8, &raw mut OBJ as *mut u8); } unsafe extern "C" fn uninit() { // unregister on shutdown - __deregister_frame_info(&__EH_FRAME_BEGIN__ as *const u8, &mut OBJ as *mut _ as *mut u8); + __deregister_frame_info(&__EH_FRAME_BEGIN__ as *const u8, &raw mut OBJ as *mut u8); } // MinGW-specific init/uninit routine registration diff --git a/library/rtstartup/rsend.rs b/library/rtstartup/rsend.rs index d763971445069..8121135debef3 100644 --- a/library/rtstartup/rsend.rs +++ b/library/rtstartup/rsend.rs @@ -27,12 +27,9 @@ auto trait Freeze {} impl Copy for *mut T {} -#[lang = "drop_in_place"] +#[lang = "drop_glue"] #[inline] -#[allow(unconditional_recursion)] -pub unsafe fn drop_in_place(to_drop: *mut T) { - drop_in_place(to_drop); -} +pub unsafe fn drop_glue(_to_drop: &mut T) {} #[cfg(all(target_os = "windows", target_arch = "x86", target_env = "gnu"))] pub mod eh_frames { diff --git a/library/std/Cargo.toml b/library/std/Cargo.toml index b37787165062c..b6f713a487d52 100644 --- a/library/std/Cargo.toml +++ b/library/std/Cargo.toml @@ -20,26 +20,26 @@ panic_unwind = { path = "../panic_unwind", optional = true } panic_abort = { path = "../panic_abort" } core = { path = "../core", public = true } unwind = { path = "../unwind" } -hashbrown = { version = "0.16.1", default-features = false, features = [ +hashbrown = { version = "0.17.1", default-features = false, features = [ 'rustc-dep-of-std', ] } std_detect = { path = "../std_detect", public = true } safety = { path = "../contracts/safety" } # Dependencies of the `backtrace` crate -rustc-demangle = { version = "0.1.27", features = ['rustc-dep-of-std'] } +rustc-demangle = { version = "0.1.28", features = ['rustc-dep-of-std'] } [target.'cfg(not(all(windows, target_env = "msvc", not(target_vendor = "uwp"))))'.dependencies] -miniz_oxide = { version = "0.8.0", optional = true, default-features = false } -addr2line = { version = "0.25.0", optional = true, default-features = false } +miniz_oxide = { version = "0.9.0", optional = true, default-features = false } +addr2line = { version = "0.27.0", optional = true, default-features = false } [target.'cfg(not(all(windows, target_env = "msvc")))'.dependencies] -libc = { version = "0.2.178", default-features = false, features = [ +libc = { version = "0.2.189", default-features = false, features = [ 'rustc-dep-of-std', ], public = true } [target.'cfg(all(not(target_os = "aix"), not(all(windows, target_env = "msvc", not(target_vendor = "uwp")))))'.dependencies] -object = { version = "0.37.1", default-features = false, optional = true, features = [ +object = { version = "0.39", default-features = false, optional = true, features = [ 'read_core', 'elf', 'macho', @@ -49,7 +49,7 @@ object = { version = "0.37.1", default-features = false, optional = true, featur ] } [target.'cfg(target_os = "aix")'.dependencies] -object = { version = "0.37.1", default-features = false, optional = true, features = [ +object = { version = "0.39", default-features = false, optional = true, features = [ 'read_core', 'xcoff', 'unaligned', @@ -63,7 +63,7 @@ path = "../windows_link" rand = { version = "0.9.0", default-features = false, features = ["alloc"] } rand_xorshift = "0.4.0" -[target.'cfg(any(all(target_family = "wasm", target_os = "unknown"), target_os = "xous", target_os = "vexos", all(target_vendor = "fortanix", target_env = "sgx")))'.dependencies] +[target.'cfg(any(all(target_family = "wasm", not(any(unix, target_os = "wasi"))), target_os = "xous", target_os = "vexos", all(target_vendor = "fortanix", target_env = "sgx")))'.dependencies] dlmalloc = { version = "0.2.10", features = ['rustc-dep-of-std'] } [target.x86_64-fortanix-unknown-sgx.dependencies] @@ -80,19 +80,19 @@ hermit-abi = { version = "0.5.0", features = [ ], public = true } [target.'cfg(all(target_os = "wasi", target_env = "p1"))'.dependencies] -wasi = { version = "0.11.0", features = [ +wasip1 = { version = "1.0.0", features = [ 'rustc-dep-of-std', ], default-features = false } [target.'cfg(all(target_os = "wasi", target_env = "p2"))'.dependencies] -wasip2 = { version = '0.14.4', features = [ +wasip2 = { version = '1.0.3', features = [ 'rustc-dep-of-std', -], default-features = false, package = 'wasi' } +], default-features = false } [target.'cfg(all(target_os = "wasi", target_env = "p3"))'.dependencies] -wasip2 = { version = '0.14.4', features = [ +wasip3 = { version = '0.7.0', features = [ 'rustc-dep-of-std', -], default-features = false, package = 'wasi' } +], default-features = false } [target.'cfg(target_os = "uefi")'.dependencies] r-efi = { version = "5.2.0", features = ['rustc-dep-of-std'] } @@ -126,8 +126,6 @@ optimize_for_size = ["core/optimize_for_size", "alloc/optimize_for_size"] # a borrow error occurs debug_refcell = ["core/debug_refcell"] -llvm_enzyme = ["core/llvm_enzyme"] - # Enable using raw-dylib for Windows imports. # This will eventually be the default. windows_raw_dylib = ["windows-link/windows_raw_dylib"] @@ -147,10 +145,6 @@ harness = false name = "sync" path = "tests/sync/lib.rs" -[[test]] -name = "floats" -path = "tests/floats/lib.rs" - [[test]] name = "thread_local" path = "tests/thread_local/lib.rs" diff --git a/library/std/benches/lib.rs b/library/std/benches/lib.rs index e749d9c0f7998..2707b414f578b 100644 --- a/library/std/benches/lib.rs +++ b/library/std/benches/lib.rs @@ -1,4 +1,4 @@ -// Disabling in Miri as these would take too long. +// This is marked as `test = true` and hence picked up by `./x miri`, but that would be too slow. #![cfg(not(miri))] #![feature(test)] diff --git a/library/std/benches/path.rs b/library/std/benches/path.rs index 912c783b31e4c..b6d5a8672aa6c 100644 --- a/library/std/benches/path.rs +++ b/library/std/benches/path.rs @@ -4,7 +4,6 @@ use std::hash::{DefaultHasher, Hash, Hasher}; use std::path::*; #[bench] -#[cfg_attr(miri, ignore)] // Miri isn't fast... fn bench_path_cmp_fast_path_buf_sort(b: &mut test::Bencher) { let prefix = "my/home"; let mut paths: Vec<_> = @@ -18,7 +17,6 @@ fn bench_path_cmp_fast_path_buf_sort(b: &mut test::Bencher) { } #[bench] -#[cfg_attr(miri, ignore)] // Miri isn't fast... fn bench_path_cmp_fast_path_long(b: &mut test::Bencher) { let prefix = "/my/home/is/my/castle/and/my/castle/has/a/rusty/workbench/"; let paths: Vec<_> = @@ -37,7 +35,6 @@ fn bench_path_cmp_fast_path_long(b: &mut test::Bencher) { } #[bench] -#[cfg_attr(miri, ignore)] // Miri isn't fast... fn bench_path_cmp_fast_path_short(b: &mut test::Bencher) { let prefix = "my/home"; let paths: Vec<_> = @@ -80,7 +77,6 @@ fn bench_path_file_name(b: &mut test::Bencher) { } #[bench] -#[cfg_attr(miri, ignore)] // Miri isn't fast... fn bench_path_hashset(b: &mut test::Bencher) { let prefix = "/my/home/is/my/castle/and/my/castle/has/a/rusty/workbench/"; let paths: Vec<_> = @@ -99,7 +95,6 @@ fn bench_path_hashset(b: &mut test::Bencher) { } #[bench] -#[cfg_attr(miri, ignore)] // Miri isn't fast... fn bench_path_hashset_miss(b: &mut test::Bencher) { let prefix = "/my/home/is/my/castle/and/my/castle/has/a/rusty/workbench/"; let paths: Vec<_> = diff --git a/library/std/build.rs b/library/std/build.rs index c0a6e30b38082..98856b58d890f 100644 --- a/library/std/build.rs +++ b/library/std/build.rs @@ -48,6 +48,7 @@ fn main() { || target_os == "vita" || target_os == "aix" || target_os == "nto" + || target_os == "qnx" || target_os == "xous" || target_os == "hurd" || target_os == "uefi" @@ -79,4 +80,28 @@ fn main() { println!("cargo:rustc-cfg=backtrace_in_libstd"); println!("cargo:rustc-env=STD_ENV_ARCH={}", env::var("CARGO_CFG_TARGET_ARCH").unwrap()); + + println!("cargo:rustc-check-cfg=cfg(vxworks_lt_25_09)"); + + if target_os == "vxworks" { + match vxworks_version_code() { + Some((major, minor)) if (major, minor) < (25, 9) => { + println!("cargo:rustc-cfg=vxworks_lt_25_09"); + } + _ => {} + } + } +} + +/// Retrieve the VxWorks release version from the environment variable set by the VxWorks build +/// environment, in `(minor, patch)` form. +fn vxworks_version_code() -> Option<(u32, u32)> { + let version = env::var("WIND_RELEASE_ID").ok()?; + + let mut pieces = version.trim().split(['.']); + + let major: u32 = pieces.next().and_then(|x| x.parse().ok()).unwrap_or(0); + let minor: u32 = pieces.next().and_then(|x| x.parse().ok()).unwrap_or(0); + + Some((major, minor)) } diff --git a/library/std/src/alloc.rs b/library/std/src/alloc.rs index 27b92b6ee8458..caccef2d14f7a 100644 --- a/library/std/src/alloc.rs +++ b/library/std/src/alloc.rs @@ -53,6 +53,11 @@ //! The `#[global_allocator]` can only be used once in a crate //! or its recursive dependencies. //! +//! The global allocator is invoked via the functions in this module +//! ([`alloc`][crate::alloc::alloc], [`alloc_zeroed`], [`dealloc`], [`realloc`]). Note, however, +//! that invoking those functions is *not* equivalent to directly invoking the underlying methods on +//! the declared global allocator! See the documentation of those functions for details. +//! //! [^system-alloc]: Note that the Rust standard library internals may still //! directly call [`System`] when necessary (for example for the runtime //! support typically required to implement a global allocator, see [re-entrance] on [`GlobalAlloc`] @@ -65,15 +70,17 @@ #[cfg(kani)] use core::kani; -use core::ptr::NonNull; -use core::sync::atomic::{AtomicBool, AtomicPtr, Ordering}; -use core::{hint, mem, ptr}; #[stable(feature = "alloc_module", since = "1.28.0")] #[doc(inline)] pub use alloc_crate::alloc::*; use safety::requires; +use crate::ptr::NonNull; +use crate::sync::atomic::{AtomicBool, AtomicPtr, Ordering}; +use crate::sys::alloc as imp; +use crate::{hint, mem, ptr}; + /// The default memory allocator provided by the operating system. /// /// This is based on `malloc` on Unix platforms and `HeapAlloc` on Windows, @@ -138,23 +145,26 @@ use safety::requires; /// program opts in to using jemalloc as the global allocator, `System` will /// still allocate memory using `malloc` and `HeapAlloc`. #[stable(feature = "alloc_system_type", since = "1.28.0")] -#[derive(Debug, Default, Copy, Clone)] +#[derive(Copy, Debug)] +#[derive_const(Clone, Default)] pub struct System; +#[unstable(feature = "allocator_api", issue = "32838")] +unsafe impl core::alloc::AllocatorClone for System {} + +#[unstable(feature = "allocator_api", issue = "32838")] +unsafe impl core::alloc::StaticAllocator for System {} + impl System { #[inline] fn alloc_impl(&self, layout: Layout, zeroed: bool) -> Result, AllocError> { match layout.size() { - 0 => Ok(NonNull::slice_from_raw_parts(layout.dangling_ptr(), 0)), + 0 => Ok(layout.dangling_ptr().cast_slice(0)), // SAFETY: `layout` is non-zero in size, size => unsafe { - let raw_ptr = if zeroed { - GlobalAlloc::alloc_zeroed(self, layout) - } else { - GlobalAlloc::alloc(self, layout) - }; + let raw_ptr = if zeroed { imp::alloc_zeroed(layout) } else { imp::alloc(layout) }; let ptr = NonNull::new(raw_ptr).ok_or(AllocError)?; - Ok(NonNull::slice_from_raw_parts(ptr, size)) + Ok(ptr.cast_slice(size)) }, } } @@ -189,12 +199,12 @@ impl System { // `realloc` probably checks for `new_size >= old_layout.size()` or something similar. hint::assert_unchecked(new_size >= old_layout.size()); - let raw_ptr = GlobalAlloc::realloc(self, ptr.as_ptr(), old_layout, new_size); + let raw_ptr = imp::realloc(ptr.as_ptr(), old_layout, new_size); let ptr = NonNull::new(raw_ptr).ok_or(AllocError)?; if zeroed { raw_ptr.add(old_size).write_bytes(0, new_size - old_size); } - Ok(NonNull::slice_from_raw_parts(ptr, new_size)) + Ok(ptr.cast_slice(new_size)) }, // SAFETY: because `new_layout.size()` must be greater than or equal to `old_size`, @@ -212,8 +222,8 @@ impl System { } } -// The Allocator impl checks the layout size to be non-zero and forwards to the GlobalAlloc impl, -// which is in `std::sys::*::alloc`. +// The Allocator impl checks the layout size to be non-zero and forwards to the +// platform functions in `std::sys::*::alloc`. #[unstable(feature = "allocator_api", issue = "32838")] unsafe impl Allocator for System { #[inline] @@ -232,7 +242,7 @@ unsafe impl Allocator for System { if layout.size() != 0 { // SAFETY: `layout` is non-zero in size, // other conditions must be upheld by the caller - unsafe { GlobalAlloc::dealloc(self, ptr.as_ptr(), layout) } + unsafe { imp::dealloc(ptr.as_ptr(), layout) } } } @@ -277,7 +287,7 @@ unsafe impl Allocator for System { // SAFETY: conditions must be upheld by the caller 0 => unsafe { Allocator::deallocate(self, ptr, old_layout); - Ok(NonNull::slice_from_raw_parts(new_layout.dangling_ptr(), 0)) + Ok(new_layout.dangling_ptr().cast_slice(0)) }, // SAFETY: `new_size` is non-zero. Other conditions must be upheld by the caller @@ -285,9 +295,9 @@ unsafe impl Allocator for System { // `realloc` probably checks for `new_size <= old_layout.size()` or something similar. hint::assert_unchecked(new_size <= old_layout.size()); - let raw_ptr = GlobalAlloc::realloc(self, ptr.as_ptr(), old_layout, new_size); + let raw_ptr = imp::realloc(ptr.as_ptr(), old_layout, new_size); let ptr = NonNull::new(raw_ptr).ok_or(AllocError)?; - Ok(NonNull::slice_from_raw_parts(ptr, new_size)) + Ok(ptr.cast_slice(new_size)) }, // SAFETY: because `new_size` must be smaller than or equal to `old_layout.size()`, @@ -305,6 +315,9 @@ unsafe impl Allocator for System { } } +#[unstable(feature = "allocator_api", issue = "32838")] +unsafe impl GlobalAllocator for System {} + static HOOK: AtomicPtr<()> = AtomicPtr::new(ptr::null_mut()); /// Registers a custom allocation error hook, replacing any that was previously registered. @@ -451,7 +464,11 @@ pub mod __default_lib_allocator { use safety::requires; - use super::{GlobalAlloc, Layout, System}; + use super::Layout; + // We call the system functions directly to avoid any overheads introduced + // by the roundtrip through `impl Allocator for System` and + // `impl GlobalAlloc for A`. + use crate::sys::alloc as imp; // These magic symbol names are used as a fallback for implementing the // `__rust_alloc` etc symbols (see `src/liballoc/alloc.rs`) when there is // no `#[global_allocator]` attribute. @@ -469,7 +486,7 @@ pub mod __default_lib_allocator { // `GlobalAlloc::alloc`. unsafe { let layout = Layout::from_size_align_unchecked(size, align); - System.alloc(layout) + imp::alloc(layout) } } @@ -478,7 +495,7 @@ pub mod __default_lib_allocator { pub unsafe extern "C" fn __rdl_dealloc(ptr: *mut u8, size: usize, align: usize) { // SAFETY: see the guarantees expected by `Layout::from_size_align` and // `GlobalAlloc::dealloc`. - unsafe { System.dealloc(ptr, Layout::from_size_align_unchecked(size, align)) } + unsafe { imp::dealloc(ptr, Layout::from_size_align_unchecked(size, align)) } } #[requires(align.is_power_of_two())] @@ -493,7 +510,7 @@ pub mod __default_lib_allocator { // `GlobalAlloc::realloc`. unsafe { let old_layout = Layout::from_size_align_unchecked(old_size, align); - System.realloc(ptr, old_layout, new_size) + imp::realloc(ptr, old_layout, new_size) } } @@ -504,7 +521,7 @@ pub mod __default_lib_allocator { // `GlobalAlloc::alloc_zeroed`. unsafe { let layout = Layout::from_size_align_unchecked(size, align); - System.alloc_zeroed(layout) + imp::alloc_zeroed(layout) } } } diff --git a/library/std/src/backtrace/tests.rs b/library/std/src/backtrace/tests.rs index 174d62813bd58..b68b528c18668 100644 --- a/library/std/src/backtrace/tests.rs +++ b/library/std/src/backtrace/tests.rs @@ -44,10 +44,9 @@ fn generate_fake_frames() -> Vec { #[test] fn test_debug() { let backtrace = Backtrace { - inner: Inner::Captured(LazyLock::preinit(Capture { - actual_start: 1, - frames: generate_fake_frames(), - })), + inner: Inner::Captured( + (Capture { actual_start: 1, frames: generate_fake_frames() }).into(), + ), }; #[rustfmt::skip] @@ -66,10 +65,9 @@ fn test_debug() { #[test] fn test_frames() { let backtrace = Backtrace { - inner: Inner::Captured(LazyLock::preinit(Capture { - actual_start: 1, - frames: generate_fake_frames(), - })), + inner: Inner::Captured( + (Capture { actual_start: 1, frames: generate_fake_frames() }).into(), + ), }; let frames = backtrace.frames(); diff --git a/library/std/src/collections/hash/map.rs b/library/std/src/collections/hash/map.rs index b82beb3b8b2ef..fef0b1b4df88e 100644 --- a/library/std/src/collections/hash/map.rs +++ b/library/std/src/collections/hash/map.rs @@ -1,13 +1,12 @@ #[cfg(test)] mod tests; -use hashbrown::hash_map as base; +use hashbrown::hash_map::{self as base, RustcOccupiedError}; use self::Entry::*; use crate::alloc::{Allocator, Global}; use crate::borrow::Borrow; use crate::collections::{TryReserveError, TryReserveErrorKind}; -use crate::error::Error; use crate::fmt::{self, Debug}; use crate::hash::{BuildHasher, Hash, RandomState}; use crate::iter::FusedIterator; @@ -20,7 +19,7 @@ use crate::ops::Index; /// reasonable best-effort is made to generate this seed from a high quality, /// secure source of randomness provided by the host without blocking the /// program. Because of this, the randomness of the seed depends on the output -/// quality of the system's random number coroutine when the seed is created. +/// quality of the system's random number generator when the seed is created. /// In particular, seeds generated when the system's entropy pool is abnormally /// low such as during system boot may be of a lower quality. /// @@ -240,7 +239,6 @@ use crate::ops::Index; /// static RANDOM_MAP: LazyLock>>> = /// LazyLock::new(|| Mutex::new(HashMap::new())); /// ``` - #[cfg_attr(not(test), rustc_diagnostic_item = "HashMap")] #[stable(feature = "rust1", since = "1.0.0")] #[rustc_insignificant_dtor] @@ -301,8 +299,11 @@ impl HashMap { /// # Examples /// /// ``` + /// # #![feature(allocator_api)] /// use std::collections::HashMap; - /// let mut map: HashMap<&str, i32> = HashMap::new(); + /// use std::alloc::Global; + /// + /// let map: HashMap = HashMap::new_in(Global); /// ``` #[inline] #[must_use] @@ -321,8 +322,11 @@ impl HashMap { /// # Examples /// /// ``` + /// # #![feature(allocator_api)] /// use std::collections::HashMap; - /// let mut map: HashMap<&str, i32> = HashMap::with_capacity(10); + /// use std::alloc::Global; + /// + /// let map: HashMap = HashMap::with_capacity_in(10, Global); /// ``` #[inline] #[must_use] @@ -357,6 +361,7 @@ impl HashMap { /// map.insert(1, 2); /// ``` #[inline] + #[must_use] #[stable(feature = "hashmap_build_hasher", since = "1.7.0")] #[rustc_const_stable(feature = "const_collections_with_hasher", since = "1.85.0")] pub const fn with_hasher(hash_builder: S) -> HashMap { @@ -389,6 +394,7 @@ impl HashMap { /// map.insert(1, 2); /// ``` #[inline] + #[must_use] #[stable(feature = "hashmap_build_hasher", since = "1.7.0")] pub fn with_capacity_and_hasher(capacity: usize, hasher: S) -> HashMap { HashMap { base: base::HashMap::with_capacity_and_hasher(capacity, hasher) } @@ -408,7 +414,20 @@ impl HashMap { /// /// The `hash_builder` passed should implement the [`BuildHasher`] trait for /// the `HashMap` to be useful, see its documentation for details. + /// + /// # Examples + /// + /// ``` + /// #![feature(allocator_api)] + /// use std::alloc::Global; + /// use std::collections::HashMap; + /// use std::hash::RandomState; + /// + /// let s = RandomState::new(); + /// let map: HashMap = HashMap::with_hasher_in(s, Global); + /// ``` #[inline] + #[must_use] #[unstable(feature = "allocator_api", issue = "32838")] pub fn with_hasher_in(hash_builder: S, alloc: A) -> Self { HashMap { base: base::HashMap::with_hasher_in(hash_builder, alloc) } @@ -429,7 +448,19 @@ impl HashMap { /// The `hasher` passed should implement the [`BuildHasher`] trait for /// the `HashMap` to be useful, see its documentation for details. /// + /// # Examples + /// + /// ``` + /// #![feature(allocator_api)] + /// use std::alloc::Global; + /// use std::collections::HashMap; + /// use std::hash::RandomState; + /// + /// let s = RandomState::new(); + /// let map: HashMap = HashMap::with_capacity_and_hasher_in(10, s, Global); + /// ``` #[inline] + #[must_use] #[unstable(feature = "allocator_api", issue = "32838")] pub fn with_capacity_and_hasher_in(capacity: usize, hash_builder: S, alloc: A) -> Self { HashMap { base: base::HashMap::with_capacity_and_hasher_in(capacity, hash_builder, alloc) } @@ -461,15 +492,16 @@ impl HashMap { /// ``` /// use std::collections::HashMap; /// - /// let map = HashMap::from([ + /// let map: HashMap<&str, i32> = HashMap::from([ /// ("a", 1), /// ("b", 2), /// ("c", 3), /// ]); /// - /// for key in map.keys() { - /// println!("{key}"); - /// } + /// let mut values: Vec<_> = map.keys().copied().collect(); + /// values.sort(); + /// + /// assert_eq!(values, vec!["a", "b", "c"]); /// ``` /// /// # Performance @@ -523,15 +555,16 @@ impl HashMap { /// ``` /// use std::collections::HashMap; /// - /// let map = HashMap::from([ + /// let map: HashMap<&str, i32> = HashMap::from([ /// ("a", 1), /// ("b", 2), /// ("c", 3), /// ]); /// - /// for val in map.values() { - /// println!("{val}"); - /// } + /// let mut values: Vec<_> = map.values().copied().collect(); + /// values.sort(); + /// + /// assert_eq!(values, vec![1, 2, 3]); /// ``` /// /// # Performance @@ -559,12 +592,12 @@ impl HashMap { /// ]); /// /// for val in map.values_mut() { - /// *val = *val + 10; + /// *val += 10; /// } /// - /// for val in map.values() { - /// println!("{val}"); - /// } + /// assert_eq!(map.get("a"), Some(&11)); + /// assert_eq!(map.get("b"), Some(&12)); + /// assert_eq!(map.get("c"), Some(&13)); /// ``` /// /// # Performance @@ -624,9 +657,13 @@ impl HashMap { /// ("c", 3), /// ]); /// - /// for (key, val) in map.iter() { - /// println!("key: {key} val: {val}"); + /// let mut count = 0; + /// + /// for (_key, _val) in map.iter() { + /// count += 1; /// } + /// + /// assert_eq!(count, 3); /// ``` /// /// # Performance @@ -659,9 +696,9 @@ impl HashMap { /// *val *= 2; /// } /// - /// for (key, val) in &map { - /// println!("key: {key} val: {val}"); - /// } + /// assert_eq!(map.get("a"), Some(&2)); + /// assert_eq!(map.get("b"), Some(&4)); + /// assert_eq!(map.get("c"), Some(&6)); /// ``` /// /// # Performance @@ -1300,7 +1337,7 @@ where /// a mutable reference to the value in the entry. /// /// If the map already had this key present, nothing is updated, and - /// an error containing the occupied entry and the value is returned. + /// an error containing the occupied entry, key, and the value is returned. /// /// # Examples /// @@ -1317,13 +1354,16 @@ where /// let err = map.try_insert(37, "b").unwrap_err(); /// assert_eq!(err.entry.key(), &37); /// assert_eq!(err.entry.get(), &"a"); + /// assert_eq!(err.key, 37); /// assert_eq!(err.value, "b"); /// ``` #[unstable(feature = "map_try_insert", issue = "82766")] pub fn try_insert(&mut self, key: K, value: V) -> Result<&mut V, OccupiedError<'_, K, V, A>> { - match self.entry(key) { - Occupied(entry) => Err(OccupiedError { entry, value }), - Vacant(entry) => Ok(entry.insert(value)), + match self.base.rustc_try_insert(key, value) { + Result::Ok(value) => Ok(value), + Result::Err(RustcOccupiedError { entry, key, value, .. }) => { + Err(OccupiedError { entry: OccupiedEntry { base: entry }, key, value }) + } } } @@ -1445,7 +1485,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for HashMap +const impl Default for HashMap where S: [const] Default, { @@ -1974,8 +2014,9 @@ impl Debug for VacantEntry<'_, K, V, A> { /// The error returned by [`try_insert`](HashMap::try_insert) when the key already exists. /// -/// Contains the occupied entry, and the value that was not inserted. +/// Contains the occupied entry, key, and the value that was not inserted. #[unstable(feature = "map_try_insert", issue = "82766")] +#[non_exhaustive] pub struct OccupiedError< 'a, K: 'a, @@ -1984,6 +2025,8 @@ pub struct OccupiedError< > { /// The entry in the map that was already occupied. pub entry: OccupiedEntry<'a, K, V, A>, + /// The key which was not inserted, because the entry was already occupied. + pub key: K, /// The value which was not inserted, because the entry was already occupied. pub value: V, } @@ -1993,28 +2036,13 @@ impl Debug for OccupiedError<'_, K, V, A> { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { f.debug_struct("OccupiedError") .field("key", self.entry.key()) + .field("uninserted_key", &self.key) .field("old_value", self.entry.get()) .field("new_value", &self.value) .finish_non_exhaustive() } } -#[unstable(feature = "map_try_insert", issue = "82766")] -impl<'a, K: Debug, V: Debug, A: Allocator> fmt::Display for OccupiedError<'a, K, V, A> { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - write!( - f, - "failed to insert {:?}, key {:?} already exists with value {:?}", - self.value, - self.entry.key(), - self.entry.get(), - ) - } -} - -#[unstable(feature = "map_try_insert", issue = "82766")] -impl<'a, K: Debug, V: Debug, A: Allocator> Error for OccupiedError<'a, K, V, A> {} - #[stable(feature = "rust1", since = "1.0.0")] impl<'a, K, V, S, A: Allocator> IntoIterator for &'a HashMap { type Item = (&'a K, &'a V); @@ -2509,9 +2537,42 @@ impl<'a, K, V, A: Allocator> Entry<'a, K, V, A> { #[inline] #[stable(feature = "rust1", since = "1.0.0")] pub fn or_insert_with V>(self, default: F) -> &'a mut V { + self.or_try_insert_with(|| Result::<_, !>::Ok(default())).unwrap() + } + + /// Ensures a value is in the entry by inserting the result of a fallible default function + /// if empty, and returns a mutable reference to the value in the entry. + /// + /// This method works identically to [`or_insert_with`] except that the default function + /// should return a `Result` and, in the case of an error, the error is propagated. + /// + /// [`or_insert_with`]: Self::or_insert_with + /// + /// # Examples + /// + /// ``` + /// #![feature(try_entry)] + /// # fn main() -> Result<(), std::num::ParseIntError> { + /// use std::collections::HashMap; + /// + /// let mut map: HashMap<&str, usize> = HashMap::new(); + /// let value = "42"; + /// + /// map.entry("poneyland").or_try_insert_with(|| value.parse())?; + /// + /// assert_eq!(map["poneyland"], 42); + /// # Ok(()) + /// # } + /// ``` + #[inline] + #[unstable(feature = "try_entry", issue = "157354")] + pub fn or_try_insert_with Result, E>( + self, + default: F, + ) -> Result<&'a mut V, E> { match self { - Occupied(entry) => entry.into_mut(), - Vacant(entry) => entry.insert(default()), + Occupied(entry) => Ok(entry.into_mut()), + Vacant(entry) => Ok(entry.insert(default()?)), } } @@ -2536,11 +2597,44 @@ impl<'a, K, V, A: Allocator> Entry<'a, K, V, A> { #[inline] #[stable(feature = "or_insert_with_key", since = "1.50.0")] pub fn or_insert_with_key V>(self, default: F) -> &'a mut V { + self.or_try_insert_with_key(|k| Result::<_, !>::Ok(default(k))).into_ok() + } + + /// Ensures a value is in the entry by inserting, if empty, the result of the default function. + /// This method allows for generating key-derived values for insertion by providing the default + /// function a reference to the key that was moved during the `entry(key)` method call. + /// + /// This method works identically to [`or_insert_with_key`] except that the default function + /// should return a `Result` and, in the case of an error, the error is propagated. + /// + /// [`or_insert_with_key`]: Self::or_insert_with_key + /// + /// # Examples + /// + /// ``` + /// #![feature(try_entry)] + /// # fn main() -> Result<(), std::num::ParseIntError> { + /// use std::collections::HashMap; + /// + /// let mut map: HashMap<&str, usize> = HashMap::new(); + /// + /// map.entry("42").or_try_insert_with_key(|key| key.parse())?; + /// + /// assert_eq!(map["42"], 42); + /// # Ok(()) + /// # } + /// ``` + #[inline] + #[unstable(feature = "try_entry", issue = "157354")] + pub fn or_try_insert_with_key Result, E>( + self, + default: F, + ) -> Result<&'a mut V, E> { match self { - Occupied(entry) => entry.into_mut(), + Occupied(entry) => Ok(entry.into_mut()), Vacant(entry) => { - let value = default(entry.key()); - entry.insert(value) + let value = default(entry.key())?; + Ok(entry.insert(value)) } } } diff --git a/library/std/src/collections/hash/set.rs b/library/std/src/collections/hash/set.rs index 3f3d601e4d30c..b0a8e8ff42149 100644 --- a/library/std/src/collections/hash/set.rs +++ b/library/std/src/collections/hash/set.rs @@ -176,6 +176,15 @@ impl HashSet { /// /// The hash set is initially created with a capacity of 0, so it will not allocate until it /// is first inserted into. + /// # Examples + /// + /// ``` + /// # #![feature(allocator_api)] + /// use std::alloc::Global; + /// use std::collections::HashSet; + /// + /// let set: HashSet = HashSet::new_in(Global); + /// ``` #[inline] #[must_use] #[unstable(feature = "allocator_api", issue = "32838")] @@ -192,9 +201,11 @@ impl HashSet { /// # Examples /// /// ``` + /// # #![feature(allocator_api)] /// use std::collections::HashSet; - /// let set: HashSet = HashSet::with_capacity(10); - /// assert!(set.capacity() >= 10); + /// use std::alloc::Global; + /// + /// let set: HashSet = HashSet::with_capacity_in(10, Global); /// ``` #[inline] #[must_use] @@ -229,6 +240,7 @@ impl HashSet { /// set.insert(2); /// ``` #[inline] + #[must_use] #[stable(feature = "hashmap_build_hasher", since = "1.7.0")] #[rustc_const_stable(feature = "const_collections_with_hasher", since = "1.85.0")] pub const fn with_hasher(hasher: S) -> HashSet { @@ -261,6 +273,7 @@ impl HashSet { /// set.insert(1); /// ``` #[inline] + #[must_use] #[stable(feature = "hashmap_build_hasher", since = "1.7.0")] pub fn with_capacity_and_hasher(capacity: usize, hasher: S) -> HashSet { HashSet { base: base::HashSet::with_capacity_and_hasher(capacity, hasher) } @@ -280,7 +293,20 @@ impl HashSet { /// /// The `hash_builder` passed should implement the [`BuildHasher`] trait for /// the `HashSet` to be useful, see its documentation for details. + /// + /// # Examples + /// + /// ``` + /// # #![feature(allocator_api)] + /// use std::alloc::Global; + /// use std::collections::HashSet; + /// use std::hash::RandomState; + /// + /// let s = RandomState::new(); + /// let set: HashSet = HashSet::with_hasher_in(s, Global); + /// ``` #[inline] + #[must_use] #[unstable(feature = "allocator_api", issue = "32838")] pub fn with_hasher_in(hasher: S, alloc: A) -> HashSet { HashSet { base: base::HashSet::with_hasher_in(hasher, alloc) } @@ -300,7 +326,20 @@ impl HashSet { /// /// The `hash_builder` passed should implement the [`BuildHasher`] trait for /// the `HashSet` to be useful, see its documentation for details. + /// + /// # Examples + /// + /// ``` + /// # #![feature(allocator_api)] + /// use std::alloc::Global; + /// use std::collections::HashSet; + /// use std::hash::RandomState; + /// + /// let s = RandomState::new(); + /// let set: HashSet = HashSet::with_capacity_and_hasher_in(10, s, Global); + /// ``` #[inline] + #[must_use] #[unstable(feature = "allocator_api", issue = "32838")] pub fn with_capacity_and_hasher_in(capacity: usize, hasher: S, alloc: A) -> HashSet { HashSet { base: base::HashSet::with_capacity_and_hasher_in(capacity, hasher, alloc) } @@ -1237,7 +1276,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for HashSet +const impl Default for HashSet where S: [const] Default, { diff --git a/library/std/src/collections/hash/set/tests.rs b/library/std/src/collections/hash/set/tests.rs index d7bbc7bdc6a5b..5dfc02935c112 100644 --- a/library/std/src/collections/hash/set/tests.rs +++ b/library/std/src/collections/hash/set/tests.rs @@ -418,14 +418,32 @@ fn test_retain() { } #[test] -fn test_extract_if() { - let mut x: HashSet<_> = [1].iter().copied().collect(); - let mut y: HashSet<_> = [1].iter().copied().collect(); - - x.extract_if(|_| true).for_each(drop); - y.extract_if(|_| false).for_each(drop); - assert_eq!(x.len(), 0); - assert_eq!(y.len(), 1); +fn test_extract_if_empty() { + let mut set: HashSet = HashSet::new(); + let extracted: Vec<_> = + set.extract_if(|_| unreachable!("there's nothing to decide on")).collect(); + + assert!(extracted.is_empty()); + assert!(set.is_empty()); +} + +#[test] +fn test_extract_if_consuming_nothing() { + let mut set: HashSet<_> = (0..3).collect(); + let extracted: Vec<_> = set.extract_if(|_| false).collect(); + + assert!(extracted.is_empty()); + assert_eq!(set, HashSet::from([0, 1, 2])); +} + +#[test] +fn test_extract_if_consuming_all() { + let mut set: HashSet<_> = (0..3).collect(); + let mut extracted: Vec<_> = set.extract_if(|_| true).collect(); + extracted.sort_unstable(); + + assert_eq!(extracted, vec![0, 1, 2]); + assert!(set.is_empty()); } #[test] diff --git a/library/std/src/env.rs b/library/std/src/env.rs index 1f0ced5d0fd0d..f5c60f7562d4a 100644 --- a/library/std/src/env.rs +++ b/library/std/src/env.rs @@ -15,7 +15,7 @@ use crate::ffi::{OsStr, OsString}; use crate::num::NonZero; use crate::ops::Try; use crate::path::{Path, PathBuf}; -use crate::sys::{env as env_imp, os as os_imp}; +use crate::sys::{env as env_imp, paths as paths_imp}; use crate::{array, fmt, io, sys}; /// Returns the current working directory as a [`PathBuf`]. @@ -51,7 +51,7 @@ use crate::{array, fmt, io, sys}; #[doc(alias = "GetCurrentDirectory")] #[stable(feature = "env", since = "1.0.0")] pub fn current_dir() -> io::Result { - os_imp::getcwd() + paths_imp::getcwd() } /// Changes the current working directory to the specified path. @@ -78,7 +78,7 @@ pub fn current_dir() -> io::Result { #[doc(alias = "chdir", alias = "SetCurrentDirectory", alias = "SetCurrentDirectoryW")] #[stable(feature = "env", since = "1.0.0")] pub fn set_current_dir>(path: P) -> io::Result<()> { - os_imp::chdir(path.as_ref()) + paths_imp::chdir(path.as_ref()) } /// An iterator over a snapshot of the environment variables of this process. @@ -101,6 +101,12 @@ pub struct VarsOs { inner: env_imp::Env, } +#[stable(feature = "env_vars_unimpl_send_sync", since = "1.98.0")] +impl !Send for VarsOs {} + +#[stable(feature = "env_vars_unimpl_send_sync", since = "1.98.0")] +impl !Sync for VarsOs {} + /// Returns an iterator of (variable, value) pairs of strings, for all the /// environment variables of the current process. /// @@ -220,14 +226,13 @@ impl fmt::Debug for VarsOs { /// ``` #[stable(feature = "env", since = "1.0.0")] pub fn var>(key: K) -> Result { - _var(key.as_ref()) -} - -fn _var(key: &OsStr) -> Result { - match var_os(key) { - Some(s) => s.into_string().map_err(VarError::NotUnicode), - None => Err(VarError::NotPresent), + fn inner(key: &OsStr) -> Result { + env_imp::getenv(key) + .ok_or(VarError::NotPresent)? + .into_string() + .map_err(VarError::NotUnicode) } + inner(key.as_ref()) } /// Fetches the environment variable `key` from the current process, returning @@ -257,11 +262,7 @@ fn _var(key: &OsStr) -> Result { #[must_use] #[stable(feature = "env", since = "1.0.0")] pub fn var_os>(key: K) -> Option { - _var_os(key.as_ref()) -} - -fn _var_os(key: &OsStr) -> Option { - env_imp::getenv(key) + env_imp::getenv(key.as_ref()) } /// The error type for operations interacting with environment variables. @@ -303,12 +304,12 @@ impl Error for VarError {} /// /// # Safety /// -/// This function is safe to call in a single-threaded program. +/// This function is sound to call in a single-threaded program. /// -/// This function is also always safe to call on Windows, in single-threaded +/// This function is also always sound to call on Windows, in single-threaded /// and multi-threaded programs. /// -/// In multi-threaded programs on other operating systems, the only safe option is +/// In multi-threaded programs on other operating systems, the only sound option is /// to not use `set_var` or `remove_var` at all. /// /// The exact requirement is: you @@ -322,7 +323,7 @@ impl Error for VarError {} /// lookups from [`std::net::ToSocketAddrs`]. No stable guarantee is made about /// which functions may read from the environment in future versions of a /// library. All this makes it not practically possible for you to guarantee -/// that no other thread will read the environment, so the only safe option is +/// that no other thread will read the environment, so the only sound option is /// to not use `set_var` or `remove_var` in multi-threaded programs at all. /// /// Discussion of this unsafety on Unix may be found in: @@ -366,12 +367,12 @@ pub unsafe fn set_var, V: AsRef>(key: K, value: V) { /// /// # Safety /// -/// This function is safe to call in a single-threaded program. +/// This function is sound to call in a single-threaded program. /// -/// This function is also always safe to call on Windows, in single-threaded +/// This function is also always sound to call on Windows, in single-threaded /// and multi-threaded programs. /// -/// In multi-threaded programs on other operating systems, the only safe option is +/// In multi-threaded programs on other operating systems, the only sound option is /// to not use `set_var` or `remove_var` at all. /// /// The exact requirement is: you @@ -385,7 +386,7 @@ pub unsafe fn set_var, V: AsRef>(key: K, value: V) { /// lookups from [`std::net::ToSocketAddrs`]. No stable guarantee is made about /// which functions may read from the environment in future versions of a /// library. All this makes it not practically possible for you to guarantee -/// that no other thread will read the environment, so the only safe option is +/// that no other thread will read the environment, so the only sound option is /// to not use `set_var` or `remove_var` in multi-threaded programs at all. /// /// Discussion of this unsafety on Unix may be found in: @@ -444,7 +445,7 @@ pub unsafe fn remove_var>(key: K) { #[must_use = "iterators are lazy and do nothing unless consumed"] #[stable(feature = "env", since = "1.0.0")] pub struct SplitPaths<'a> { - inner: os_imp::SplitPaths<'a>, + inner: paths_imp::SplitPaths<'a>, } /// Parses input according to platform conventions for the `PATH` @@ -480,7 +481,7 @@ pub struct SplitPaths<'a> { /// ``` #[stable(feature = "env", since = "1.0.0")] pub fn split_paths + ?Sized>(unparsed: &T) -> SplitPaths<'_> { - SplitPaths { inner: os_imp::split_paths(unparsed.as_ref()) } + SplitPaths { inner: paths_imp::split_paths(unparsed.as_ref()) } } #[stable(feature = "env", since = "1.0.0")] @@ -508,7 +509,7 @@ impl fmt::Debug for SplitPaths<'_> { #[derive(Debug)] #[stable(feature = "env", since = "1.0.0")] pub struct JoinPathsError { - inner: os_imp::JoinPathsError, + inner: paths_imp::JoinPathsError, } /// Joins a collection of [`Path`]s appropriately for the `PATH` @@ -579,7 +580,7 @@ where I: IntoIterator, T: AsRef, { - os_imp::join_paths(paths.into_iter()).map_err(|e| JoinPathsError { inner: e }) + paths_imp::join_paths(paths.into_iter()).map_err(|e| JoinPathsError { inner: e }) } #[stable(feature = "env", since = "1.0.0")] @@ -605,6 +606,7 @@ impl Error for JoinPathsError { /// For example, [XDG Base Directories] on Unix or the `LOCALAPPDATA` and `APPDATA` environment variables on Windows. /// /// [XDG Base Directories]: https://specifications.freedesktop.org/basedir-spec/latest/ +// feature(xdg_basedir): This should link to std::os::unix::xdg once it's stabilized /// /// # Unix /// @@ -640,8 +642,9 @@ impl Error for JoinPathsError { /// ``` #[must_use] #[stable(feature = "env", since = "1.0.0")] +#[doc(alias = "home")] pub fn home_dir() -> Option { - os_imp::home_dir() + paths_imp::home_dir() } /// Returns the path of a temporary directory. @@ -670,6 +673,17 @@ pub fn home_dir() -> Option { /// /// On Windows, the behavior is equivalent to that of [`GetTempPath2`][GetTempPath2] / /// [`GetTempPath`][GetTempPath], which this function uses internally. +/// Specifically, for non-SYSTEM processes, the function checks for the +/// following environment variables in order and returns the first path found: +/// +/// 1. The path specified by the `TMP` environment variable. +/// 2. The path specified by the `TEMP` environment variable. +/// 3. The path specified by the `USERPROFILE` environment variable. +/// 4. The Windows directory. +/// +/// When called from a process running as SYSTEM, +/// [`GetTempPath2`][GetTempPath2] returns `C:\Windows\SystemTemp` +/// regardless of environment variables. /// /// Note that, this [may change in the future][changes]. /// @@ -678,7 +692,7 @@ pub fn home_dir() -> Option { /// [GetTempPath]: https://docs.microsoft.com/en-us/windows/win32/api/fileapi/nf-fileapi-gettemppatha /// [appledoc]: https://developer.apple.com/library/archive/documentation/Security/Conceptual/SecureCodingGuide/Articles/RaceConditions.html#//apple_ref/doc/uid/TP40002585-SW10 /// -/// ```no_run +/// ``` /// use std::env; /// /// fn main() { @@ -690,7 +704,7 @@ pub fn home_dir() -> Option { #[doc(alias = "GetTempPath", alias = "GetTempPath2")] #[stable(feature = "env", since = "1.0.0")] pub fn temp_dir() -> PathBuf { - os_imp::temp_dir() + paths_imp::temp_dir() } /// Returns the full filesystem path of the current running executable. @@ -712,28 +726,21 @@ pub fn temp_dir() -> PathBuf { /// /// # Security /// -/// The output of this function should not be trusted for anything -/// that might have security implications. Basically, if users can run -/// the executable, they can change the output arbitrarily. +/// The output of this function must be treated with care to avoid security +/// vulnerabilities, particularly in processes that run with privileges higher +/// than the user, such as setuid or setgid programs. /// -/// As an example, you can easily introduce a race condition. It goes -/// like this: +/// For example, on some Unix platforms, the result is calculated by +/// searching `$PATH` for an executable matching `argv[0]`, but both the +/// environment and arguments can be be set arbitrarily by the user who +/// invokes the program. /// -/// 1. You get the path to the current executable using `current_exe()`, and -/// store it in a variable. -/// 2. Time passes. A malicious actor removes the current executable, and -/// replaces it with a malicious one. -/// 3. You then use the stored path to re-execute the current -/// executable. +/// On Linux, if `fs.secure_hardlinks` is not set, an attacker who can +/// create hardlinks to the executable may be able to cause this function +/// to return an attacker-controlled path, which they later replace with +/// a different program. /// -/// You expected to safely execute the current executable, but you're -/// instead executing something completely different. The code you -/// just executed runs with your privileges. -/// -/// This sort of behavior has been known to [lead to privilege escalation] when -/// used incorrectly. -/// -/// [lead to privilege escalation]: https://securityvulns.com/Wdocument183.html +/// This list of illustrative example attacks is not exhaustive. /// /// # Examples /// @@ -748,7 +755,7 @@ pub fn temp_dir() -> PathBuf { /// ``` #[stable(feature = "env", since = "1.0.0")] pub fn current_exe() -> io::Result { - os_imp::current_exe() + paths_imp::current_exe() } /// An iterator over the arguments of a process, yielding a [`String`] value for @@ -1067,41 +1074,43 @@ pub mod consts { /// ///

Full list of possible values /// - /// * `"linux"` - /// * `"windows"` - /// * `"macos"` - /// * `"android"` - /// * `"ios"` - /// * `"openbsd"` - /// * `"freebsd"` - /// * `"netbsd"` - /// * `"wasi"` - /// * `"hermit"` + // tidy-alphabetical-start /// * `"aix"` + /// * `"android"` /// * `"apple"` /// * `"dragonfly"` /// * `"emscripten"` /// * `"espidf"` /// * `"fortanix"` - /// * `"uefi"` + /// * `"freebsd"` /// * `"fuchsia"` /// * `"haiku"` /// * `"hermit"` - /// * `"watchos"` - /// * `"visionos"` - /// * `"tvos"` /// * `"horizon"` /// * `"hurd"` /// * `"illumos"` + /// * `"ios"` /// * `"l4re"` + /// * `"linux"` + /// * `"macos"` + /// * `"netbsd"` /// * `"nto"` + /// * `"openbsd"` + /// * `"qnx"` /// * `"redox"` /// * `"solaris"` /// * `"solid_asp3"` + /// * `"tvos"` + /// * `"uefi"` /// * `"vexos"` + /// * `"visionos"` /// * `"vita"` /// * `"vxworks"` + /// * `"wasi"` + /// * `"watchos"` + /// * `"windows"` /// * `"xous"` + // tidy-alphabetical-end /// ///
#[stable(feature = "env", since = "1.0.0")] diff --git a/library/std/src/error.rs b/library/std/src/error.rs index def5f984c88e4..5b059b4d39e65 100644 --- a/library/std/src/error.rs +++ b/library/std/src/error.rs @@ -450,13 +450,12 @@ where // have to grab the backtrace on the first error directly since that error may not be // 'static let backtrace = request_ref(&self.error); - let backtrace = backtrace.or_else(|| { + backtrace.or_else(|| { self.error .source() .map(|source| source.sources().find_map(|source| request_ref(source))) .flatten() - }); - backtrace + }) } /// Format the report as a single line. diff --git a/library/std/src/ffi/mod.rs b/library/std/src/ffi/mod.rs index 999bd5e63dc45..b339a80f45397 100644 --- a/library/std/src/ffi/mod.rs +++ b/library/std/src/ffi/mod.rs @@ -166,12 +166,7 @@ pub mod c_str; #[stable(feature = "core_c_void", since = "1.30.0")] pub use core::ffi::c_void; -#[unstable( - feature = "c_variadic", - reason = "the `c_variadic` feature has not been properly tested on \ - all supported platforms", - issue = "44930" -)] +#[stable(feature = "c_variadic", since = "1.99.0")] pub use core::ffi::{VaArgSafe, VaList}; #[stable(feature = "core_ffi_c", since = "1.64.0")] pub use core::ffi::{ diff --git a/library/std/src/ffi/os_str.rs b/library/std/src/ffi/os_str.rs index 4e4d377ae2708..27039f0d3d2eb 100644 --- a/library/std/src/ffi/os_str.rs +++ b/library/std/src/ffi/os_str.rs @@ -94,10 +94,6 @@ pub struct OsString { inner: Buf, } -/// Allows extension traits within `std`. -#[unstable(feature = "sealed", issue = "none")] -impl crate::sealed::Sealed for OsString {} - /// Borrowed reference to an OS string (see [`OsString`]). /// /// This type represents a borrowed reference to a string in the operating system's preferred @@ -120,10 +116,6 @@ pub struct OsStr { inner: Slice, } -/// Allows extension traits within `std`. -#[unstable(feature = "sealed", issue = "none")] -impl crate::sealed::Sealed for OsStr {} - impl OsString { /// Constructs a new empty `OsString`. /// @@ -576,15 +568,21 @@ impl OsString { /// Truncate the `OsString` to the specified length. /// + /// If `new_len` is greater than the string's current length, this has no + /// effect. + /// /// # Panics + /// /// Panics if `len` does not lie on a valid `OsStr` boundary /// (as described in [`OsStr::slice_encoded_bytes`]). #[inline] #[unstable(feature = "os_string_truncate", issue = "133262")] pub fn truncate(&mut self, len: usize) { - self.as_os_str().inner.check_public_boundary(len); - // SAFETY: The length was just checked to be at a valid boundary. - unsafe { self.inner.truncate_unchecked(len) }; + if len <= self.len() { + self.as_os_str().inner.check_public_boundary(len); + // SAFETY: The length was just checked to be at a valid boundary. + unsafe { self.inner.truncate_unchecked(len) }; + } } /// Provides plumbing to `Vec::extend_from_slice` without giving full @@ -721,7 +719,7 @@ impl fmt::Debug for OsString { impl PartialEq for OsString { #[inline] fn eq(&self, other: &OsString) -> bool { - &**self == &**other + **self == **other } } @@ -764,23 +762,23 @@ impl Eq for OsString {} impl PartialOrd for OsString { #[inline] fn partial_cmp(&self, other: &OsString) -> Option { - (&**self).partial_cmp(&**other) + (**self).partial_cmp(&**other) } #[inline] fn lt(&self, other: &OsString) -> bool { - &**self < &**other + **self < **other } #[inline] fn le(&self, other: &OsString) -> bool { - &**self <= &**other + **self <= **other } #[inline] fn gt(&self, other: &OsString) -> bool { - &**self > &**other + **self > **other } #[inline] fn ge(&self, other: &OsString) -> bool { - &**self >= &**other + **self >= **other } } @@ -788,7 +786,7 @@ impl PartialOrd for OsString { impl PartialOrd for OsString { #[inline] fn partial_cmp(&self, other: &str) -> Option { - (&**self).partial_cmp(other) + (**self).partial_cmp(other) } } @@ -796,7 +794,7 @@ impl PartialOrd for OsString { impl Ord for OsString { #[inline] fn cmp(&self, other: &OsString) -> cmp::Ordering { - (&**self).cmp(&**other) + (**self).cmp(&**other) } } @@ -804,7 +802,7 @@ impl Ord for OsString { impl Hash for OsString { #[inline] fn hash(&self, state: &mut H) { - (&**self).hash(state) + (**self).hash(state) } } @@ -1049,6 +1047,61 @@ impl OsStr { OsString { inner: Buf::from_box(boxed) } } + /// Divides one string slice into two at an index. + /// + /// The two slices returned go from the start of the string slice to `mid`, and from `mid` to the end of the string slice. + /// + /// The argument, `mid`, should be a byte offset from the start of the string. + /// It must also be on a valid `OsStr` boundary. + /// See [`split_at_checked`][Self::split_at_checked] for the definition of a valid boundary. + /// + /// Panics + /// + /// Panics if `mid` is not on a valid boundary, or if it is past the end of the last code point of the string slice. + /// For a non-panicking alternative see [`split_at_checked`][Self::split_at_checked]. + #[unstable(feature = "os_str_split_at", issue = "none")] + pub fn split_at(&self, mid: usize) -> (&OsStr, &OsStr) { + self.inner.check_public_boundary(mid); + + // SAFETY: we've checked it's in bounds and a valid boundary + unsafe { self.split_at_unchecked(mid) } + } + + /// Divides one string slice into two at an index. + /// + /// The two slices returned go from the start of the string slice to `mid`, and from `mid` to the end of the string slice. + /// + /// The argument, `mid`, should be a valid byte offset from the start of the string. + /// It must also be on a valid `OsStr` boundary. + /// The method returns `None` if that’s not the case. + /// A valid `OsStr` boundary is one of: + /// - The start of the string + /// - The end of the string + /// - The start of a valid non-empty UTF-8 substring + /// - Immediately follows a valid non-empty UTF-8 substring + #[unstable(feature = "os_str_split_at", issue = "none")] + pub fn split_at_checked(&self, mid: usize) -> Option<(&OsStr, &OsStr)> { + self.inner.try_check_public_boundary(mid)?; + + // SAFETY: we've checked it's in bounds and a valid boundary + unsafe { Some(self.split_at_unchecked(mid)) } + } + + /// Splits an `OsStr` without checking if `mid` is a valid boundary. + /// You should use `split_at` or `split_at_checked` instead. + /// + /// # Safety + /// + /// Any caller must ensure `mid` is within bounds and lies on + /// a valid `OsStr` boundary for the platform. + unsafe fn split_at_unchecked(&self, mid: usize) -> (&OsStr, &OsStr) { + // SAFETY: it's up to the caller to ensure this is safe. + unsafe { + let (first, second) = self.as_encoded_bytes().split_at_unchecked(mid); + (Self::from_encoded_bytes_unchecked(first), Self::from_encoded_bytes_unchecked(second)) + } + } + /// Converts an OS string slice to a byte slice. To convert the byte slice back into an OS /// string slice, use the [`OsStr::from_encoded_bytes_unchecked`] function. /// @@ -1565,7 +1618,7 @@ impl Ord for OsStr { macro_rules! impl_cmp { ($lhs:ty, $rhs: ty) => { #[stable(feature = "cmp_os_str", since = "1.8.0")] - impl<'a, 'b> PartialEq<$rhs> for $lhs { + impl PartialEq<$rhs> for $lhs { #[inline] fn eq(&self, other: &$rhs) -> bool { ::eq(self, other) @@ -1573,7 +1626,7 @@ macro_rules! impl_cmp { } #[stable(feature = "cmp_os_str", since = "1.8.0")] - impl<'a, 'b> PartialEq<$lhs> for $rhs { + impl PartialEq<$lhs> for $rhs { #[inline] fn eq(&self, other: &$lhs) -> bool { ::eq(self, other) @@ -1581,7 +1634,7 @@ macro_rules! impl_cmp { } #[stable(feature = "cmp_os_str", since = "1.8.0")] - impl<'a, 'b> PartialOrd<$rhs> for $lhs { + impl PartialOrd<$rhs> for $lhs { #[inline] fn partial_cmp(&self, other: &$rhs) -> Option { ::partial_cmp(self, other) @@ -1589,7 +1642,7 @@ macro_rules! impl_cmp { } #[stable(feature = "cmp_os_str", since = "1.8.0")] - impl<'a, 'b> PartialOrd<$lhs> for $rhs { + impl PartialOrd<$lhs> for $rhs { #[inline] fn partial_cmp(&self, other: &$lhs) -> Option { ::partial_cmp(self, other) @@ -1599,10 +1652,10 @@ macro_rules! impl_cmp { } impl_cmp!(OsString, OsStr); -impl_cmp!(OsString, &'a OsStr); -impl_cmp!(Cow<'a, OsStr>, OsStr); -impl_cmp!(Cow<'a, OsStr>, &'b OsStr); -impl_cmp!(Cow<'a, OsStr>, OsString); +impl_cmp!(OsString, &OsStr); +impl_cmp!(Cow<'_, OsStr>, OsStr); +impl_cmp!(Cow<'_, OsStr>, &OsStr); +impl_cmp!(Cow<'_, OsStr>, OsString); #[stable(feature = "rust1", since = "1.0.0")] impl Hash for OsStr { @@ -1697,7 +1750,7 @@ impl ToOwned for OsStr { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef for OsStr { +const impl AsRef for OsStr { #[inline] fn as_ref(&self) -> &OsStr { self @@ -1724,7 +1777,7 @@ impl AsRef for str { impl AsRef for String { #[inline] fn as_ref(&self) -> &OsStr { - (&**self).as_ref() + (**self).as_ref() } } diff --git a/library/std/src/ffi/os_str/tests.rs b/library/std/src/ffi/os_str/tests.rs index 3474f0ab50684..1075c43e0b3bf 100644 --- a/library/std/src/ffi/os_str/tests.rs +++ b/library/std/src/ffi/os_str/tests.rs @@ -289,6 +289,108 @@ fn slice_surrogate_edge() { assert_eq!(post_crab.slice_encoded_bytes(4..), surrogate); } +#[test] +fn os_str_slice_at() { + #[track_caller] + fn slice_at_ok(input: &OsStr, index: usize, expected: (&str, &str)) { + let expected = (OsStr::new(expected.0), OsStr::new(expected.1)); + assert_eq!(input.split_at(index), expected); + assert_eq!(input.split_at_checked(index), Some(expected)); + } + + let os_str = OsStr::new("123გ🦀4"); + slice_at_ok(os_str, 0, ("", "123გ🦀4")); + slice_at_ok(os_str, 1, ("1", "23გ🦀4")); + slice_at_ok(os_str, 2, ("12", "3გ🦀4")); + slice_at_ok(os_str, 3, ("123", "გ🦀4")); + slice_at_ok(os_str, 6, ("123გ", "🦀4")); + slice_at_ok(os_str, 10, ("123გ🦀", "4")); + slice_at_ok(os_str, 11, ("123გ🦀4", "")); + + // Invalid boundaries should fail. + assert!(os_str.split_at_checked(4).is_none()); + assert!(os_str.split_at_checked(5).is_none()); + assert!(os_str.split_at_checked(7).is_none()); + assert!(os_str.split_at_checked(8).is_none()); + assert!(os_str.split_at_checked(9).is_none()); + // Out of bounds + assert!(os_str.split_at_checked(12).is_none()); +} + +#[test] +#[should_panic] +fn os_str_slice_at_out_of_bounds() { + let crab = OsStr::new("🦀"); + let _ = crab.split_at(5); +} + +#[test] +#[should_panic] +fn os_str_slice_at_mid_char() { + let crab = OsStr::new("🦀"); + let _ = crab.split_at(2); +} + +#[cfg(unix)] +#[test] +fn os_str_slice_at_unix() { + use crate::os::unix::ffi::OsStrExt; + + let broken_utf8 = OsStr::from_bytes(&"🦀".as_bytes()[..3]); + let invalid = OsStr::from_bytes(b"\xFF"); + + // Check that broken UTF-8 isn't treated as if it's valid. + let mut os_string = invalid.to_os_string(); + os_string.push(broken_utf8); + assert_eq!(os_string.split_at_checked(1), None); + + // We should be able to split on ascii with invalid UTF-8 between + let os_string = OsStr::from_bytes(b"a\xFFa"); + assert_eq!(os_string.split_at_checked(1), Some(("a".as_ref(), OsStr::from_bytes(b"\xFFa")))); + assert_eq!(os_string.split_at_checked(2), Some((OsStr::from_bytes(b"a\xFF"), "a".as_ref(),))); + + let os_string = OsStr::from_bytes(&"abc🦀".as_bytes()[..6]); + assert_eq!( + os_string.split_at_checked(3), + Some(("abc".as_ref(), OsStr::from_bytes(b"\xF0\x9F\xA6"))) + ); + + let mut os_string = invalid.to_os_string(); + os_string.push("🦀"); + assert_eq!(os_string.split_at_checked(1), Some((invalid, "🦀".as_ref()))); +} + +#[test] +#[cfg(windows)] +fn os_str_slice_at_windows() { + use crate::os::windows::ffi::OsStringExt; + + // slicing between unpaired surrogates should not be possible + // checking is implemented as a loop so we're agnostic towards + // the internal encoding + let os_string = OsString::from_wide(&[0xD800, 0xD800]); + for i in 1..os_string.len() { + assert_eq!(os_string.split_at_checked(i), None); + } + // For completeness, check that splitting at the start and end still works. + assert!(os_string.split_at_checked(0).is_some()); + assert!(os_string.split_at_checked(os_string.len()).is_some()); + + // check that slicing before and after unpaired surrogates work + let surrogate = OsString::from_wide(&[0xD800]); + + let mut os_string = surrogate.clone(); + os_string.push("🦀"); + assert_eq!( + os_string.split_at_checked(surrogate.len()), + Some((surrogate.as_ref(), "🦀".as_ref())) + ); + + let mut os_string = OsString::from("🦀"); + os_string.push(&surrogate); + assert_eq!(os_string.split_at_checked("🦀".len()), Some(("🦀".as_ref(), surrogate.as_ref()))); +} + #[test] fn clone_to_uninit() { let a = OsStr::new("hello.txt"); diff --git a/library/std/src/fs.rs b/library/std/src/fs.rs index a24baad615012..0702148957695 100644 --- a/library/std/src/fs.rs +++ b/library/std/src/fs.rs @@ -37,6 +37,7 @@ target_env = "sgx", target_os = "xous", target_os = "trusty", + target_os = "l4re", )) ))] mod tests; @@ -44,8 +45,6 @@ mod tests; use crate::ffi::OsString; use crate::io::{self, BorrowedCursor, IoSlice, IoSliceMut, Read, Seek, SeekFrom, Write}; use crate::path::{Path, PathBuf}; -use crate::sealed::Sealed; -use crate::sync::Arc; use crate::sys::{AsInner, AsInnerMut, FromInner, IntoInner, fs as fs_imp}; use crate::time::SystemTime; use crate::{error, fmt}; @@ -132,6 +131,7 @@ use crate::{error, fmt}; /// [`read`]: File::read #[stable(feature = "rust1", since = "1.0.0")] #[cfg_attr(not(test), rustc_diagnostic_item = "File")] +#[diagnostic::on_move(note = "you can use `File::try_clone` to duplicate a `File` instance")] pub struct File { inner: fs_imp::File, } @@ -185,6 +185,7 @@ pub enum TryLockError { /// /// [TOCTOU]: self#time-of-check-to-time-of-use-toctou #[unstable(feature = "dirfd", issue = "120426")] +#[cfg_attr(not(test), rustc_diagnostic_item = "FsDir")] pub struct Dir { inner: fs_imp::Dir, } @@ -197,6 +198,7 @@ pub struct Dir { /// times, etc. #[stable(feature = "rust1", since = "1.0.0")] #[derive(Clone)] +#[cfg_attr(not(test), rustc_diagnostic_item = "FsMetadata")] pub struct Metadata(fs_imp::FileAttr); /// Iterator over the entries in a directory. @@ -214,6 +216,7 @@ pub struct Metadata(fs_imp::FileAttr); /// the next entry from the OS. #[stable(feature = "rust1", since = "1.0.0")] #[derive(Debug)] +#[cfg_attr(not(test), rustc_diagnostic_item = "FsReadDir")] pub struct ReadDir(fs_imp::ReadDir); /// Entries returned by the [`ReadDir`] iterator. @@ -232,6 +235,7 @@ pub struct ReadDir(fs_imp::ReadDir); /// /// [changes]: io#platform-specific-behavior #[stable(feature = "rust1", since = "1.0.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "FsDirEntry")] pub struct DirEntry(fs_imp::DirEntry); /// Options and flags which can be used to configure how a file is opened. @@ -277,6 +281,7 @@ pub struct OpenOptions(fs_imp::OpenOptions); /// Representation of the various timestamps on a file. #[derive(Copy, Clone, Debug, Default)] #[stable(feature = "file_set_times", since = "1.75.0")] +#[must_use = "must be applied to a file via `File::set_times` to have any effect"] pub struct FileTimes(fs_imp::FileTimes); /// Representation of the various permissions on a file. @@ -337,6 +342,7 @@ pub struct DirBuilder { /// } /// ``` #[stable(feature = "fs_read_write_bytes", since = "1.26.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_read")] pub fn read>(path: P) -> io::Result> { fn inner(path: &Path) -> io::Result> { let mut file = File::open(path)?; @@ -379,6 +385,7 @@ pub fn read>(path: P) -> io::Result> { /// } /// ``` #[stable(feature = "fs_read_write", since = "1.26.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_read_to_string")] pub fn read_to_string>(path: P) -> io::Result { fn inner(path: &Path) -> io::Result { let mut file = File::open(path)?; @@ -416,6 +423,7 @@ pub fn read_to_string>(path: P) -> io::Result { /// } /// ``` #[stable(feature = "fs_read_write_bytes", since = "1.26.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_write")] pub fn write, C: AsRef<[u8]>>(path: P, contents: C) -> io::Result<()> { fn inner(path: &Path, contents: &[u8]) -> io::Result<()> { File::create(path)?.write_all(contents) @@ -442,7 +450,6 @@ pub fn write, C: AsRef<[u8]>>(path: P, contents: C) -> io::Result /// # Examples /// /// ```no_run -/// #![feature(fs_set_times)] /// use std::fs::{self, FileTimes}; /// use std::time::SystemTime; /// @@ -455,10 +462,11 @@ pub fn write, C: AsRef<[u8]>>(path: P, contents: C) -> io::Result /// Ok(()) /// } /// ``` -#[unstable(feature = "fs_set_times", issue = "147455")] +#[stable(feature = "fs_set_times", since = "1.99.0")] #[doc(alias = "utimens")] #[doc(alias = "utimes")] #[doc(alias = "utime")] +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_set_times")] pub fn set_times>(path: P, times: FileTimes) -> io::Result<()> { fs_imp::set_times(path.as_ref(), times.0) } @@ -483,7 +491,6 @@ pub fn set_times>(path: P, times: FileTimes) -> io::Result<()> { /// # Examples /// /// ```no_run -/// #![feature(fs_set_times)] /// use std::fs::{self, FileTimes}; /// use std::time::SystemTime; /// @@ -496,10 +503,11 @@ pub fn set_times>(path: P, times: FileTimes) -> io::Result<()> { /// Ok(()) /// } /// ``` -#[unstable(feature = "fs_set_times", issue = "147455")] +#[stable(feature = "fs_set_times", since = "1.99.0")] #[doc(alias = "utimensat")] #[doc(alias = "lutimens")] #[doc(alias = "lutimes")] +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_set_times_nofollow")] pub fn set_times_nofollow>(path: P, times: FileTimes) -> io::Result<()> { fs_imp::set_times_nofollow(path.as_ref(), times.0) } @@ -604,9 +612,7 @@ impl File { #[unstable(feature = "file_buffered", issue = "130804")] pub fn open_buffered>(path: P) -> io::Result> { // Allocate the buffer *first* so we don't affect the filesystem otherwise. - let buffer = io::BufReader::::try_new_buffer()?; - let file = File::open(path)?; - Ok(io::BufReader::with_buffer(file, buffer)) + io::BufReader::try_new_with(|| File::open(path)) } /// Opens a file in write-only mode. @@ -672,9 +678,7 @@ impl File { #[unstable(feature = "file_buffered", issue = "130804")] pub fn create_buffered>(path: P) -> io::Result> { // Allocate the buffer *first* so we don't affect the filesystem otherwise. - let buffer = io::BufWriter::::try_new_buffer()?; - let file = File::create(path)?; - Ok(io::BufWriter::with_buffer(file, buffer)) + io::BufWriter::try_new_with(|| File::create(path)) } /// Creates a new file in read-write mode; error if the file exists. @@ -814,17 +818,17 @@ impl File { /// Acquire an exclusive lock on the file. Blocks until the lock can be acquired. /// - /// This acquires an exclusive lock; no other file handle to this file may acquire another lock. + /// This acquires an exclusive lock. No *other* file handle to this file, in this or any other + /// process, may acquire another lock. + /// If this file handle/descriptor, or a clone of it, already holds a lock, the exact behavior + /// is unspecified and platform dependent, including the possibility that it will deadlock. + /// However, if this method returns, then an exclusive lock is held. /// /// This lock may be advisory or mandatory. This lock is meant to interact with [`lock`], /// [`try_lock`], [`lock_shared`], [`try_lock_shared`], and [`unlock`]. Its interactions with /// other methods, such as [`read`] and [`write`] are platform specific, and it may or may not /// cause non-lockholders to block. /// - /// If this file handle/descriptor, or a clone of it, already holds a lock the exact behavior - /// is unspecified and platform dependent, including the possibility that it will deadlock. - /// However, if this method returns, then an exclusive lock is held. - /// /// If the file is not open for writing, it is unspecified whether this function returns an error. /// /// The lock will be released when this file (along with any other file descriptors/handles @@ -867,18 +871,18 @@ impl File { /// Acquire a shared (non-exclusive) lock on the file. Blocks until the lock can be acquired. /// - /// This acquires a shared lock; more than one file handle may hold a shared lock, but none may - /// hold an exclusive lock at the same time. + /// This acquires a shared lock. More than one file handle to this file, in this or any other + /// process, may hold a shared lock, but no *other* file handle may hold an exclusive lock at + /// the same time. + /// If this file handle/descriptor, or a clone of it, already holds a lock, the exact + /// behavior is unspecified and platform dependent, including the possibility that it will + /// deadlock. However, if this method returns, then a shared lock is held. /// /// This lock may be advisory or mandatory. This lock is meant to interact with [`lock`], /// [`try_lock`], [`lock_shared`], [`try_lock_shared`], and [`unlock`]. Its interactions with /// other methods, such as [`read`] and [`write`] are platform specific, and it may or may not /// cause non-lockholders to block. /// - /// If this file handle/descriptor, or a clone of it, already holds a lock, the exact behavior - /// is unspecified and platform dependent, including the possibility that it will deadlock. - /// However, if this method returns, then a shared lock is held. - /// /// The lock will be released when this file (along with any other file descriptors/handles /// duplicated or inherited from it) is closed, or if the [`unlock`] method is called. /// @@ -922,7 +926,8 @@ impl File { /// Returns `Err(TryLockError::WouldBlock)` if a different lock is already held on this file /// (via another handle/descriptor). /// - /// This acquires an exclusive lock; no other file handle to this file may acquire another lock. + /// This acquires an exclusive lock; no other file handle to this file, in this or any other + /// process, may acquire another lock. /// /// This lock may be advisory or mandatory. This lock is meant to interact with [`lock`], /// [`try_lock`], [`lock_shared`], [`try_lock_shared`], and [`unlock`]. Its interactions with @@ -986,8 +991,8 @@ impl File { /// Returns `Err(TryLockError::WouldBlock)` if a different lock is already held on this file /// (via another handle/descriptor). /// - /// This acquires a shared lock; more than one file handle may hold a shared lock, but none may - /// hold an exclusive lock at the same time. + /// This acquires a shared lock; more than one file handle, in this or any other process, may + /// hold a shared lock, but none may hold an exclusive lock at the same time. /// /// This lock may be advisory or mandatory. This lock is meant to interact with [`lock`], /// [`try_lock`], [`lock_shared`], [`try_lock_shared`], and [`unlock`]. Its interactions with @@ -1262,6 +1267,7 @@ impl File { #[doc(alias = "futimens")] #[doc(alias = "futimes")] #[doc(alias = "SetFileTime")] + #[doc(alias = "filetime")] pub fn set_times(&self, times: FileTimes) -> io::Result<()> { self.inner.set_times(times.0) } @@ -1350,7 +1356,7 @@ impl Read for &File { } #[inline] - fn read_buf(&mut self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { self.inner.read_buf(cursor) } @@ -1495,12 +1501,12 @@ impl Read for File { fn read_vectored(&mut self, bufs: &mut [IoSliceMut<'_>]) -> io::Result { (&*self).read_vectored(bufs) } - fn read_buf(&mut self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { (&*self).read_buf(cursor) } #[inline] fn is_read_vectored(&self) -> bool { - (&&*self).is_read_vectored() + (&self).is_read_vectored() } fn read_to_end(&mut self, buf: &mut Vec) -> io::Result { (&*self).read_to_end(buf) @@ -1519,7 +1525,7 @@ impl Write for File { } #[inline] fn is_write_vectored(&self) -> bool { - (&&*self).is_write_vectored() + (&self).is_write_vectored() } #[inline] fn flush(&mut self) -> io::Result<()> { @@ -1538,62 +1544,15 @@ impl Seek for File { (&*self).stream_position() } } - -#[stable(feature = "io_traits_arc", since = "1.73.0")] -impl Read for Arc { - fn read(&mut self, buf: &mut [u8]) -> io::Result { - (&**self).read(buf) - } - fn read_vectored(&mut self, bufs: &mut [IoSliceMut<'_>]) -> io::Result { - (&**self).read_vectored(bufs) - } - fn read_buf(&mut self, cursor: BorrowedCursor<'_>) -> io::Result<()> { - (&**self).read_buf(cursor) - } - #[inline] - fn is_read_vectored(&self) -> bool { - (&**self).is_read_vectored() - } - fn read_to_end(&mut self, buf: &mut Vec) -> io::Result { - (&**self).read_to_end(buf) - } - fn read_to_string(&mut self, buf: &mut String) -> io::Result { - (&**self).read_to_string(buf) - } -} -#[stable(feature = "io_traits_arc", since = "1.73.0")] -impl Write for Arc { - fn write(&mut self, buf: &[u8]) -> io::Result { - (&**self).write(buf) - } - fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { - (&**self).write_vectored(bufs) - } - #[inline] - fn is_write_vectored(&self) -> bool { - (&**self).is_write_vectored() - } - #[inline] - fn flush(&mut self) -> io::Result<()> { - (&**self).flush() - } -} -#[stable(feature = "io_traits_arc", since = "1.73.0")] -impl Seek for Arc { - fn seek(&mut self, pos: SeekFrom) -> io::Result { - (&**self).seek(pos) - } - fn stream_len(&mut self) -> io::Result { - (&**self).stream_len() - } - fn stream_position(&mut self) -> io::Result { - (&**self).stream_position() - } -} +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +impl crate::io::IoHandle for File {} impl Dir { /// Attempts to open a directory at `path` in read-only mode. /// + /// This function opens a directory. To open a file instead, see [`File::open`]. + /// /// # Errors /// /// This function will return an error if `path` does not point to an existing directory. @@ -1619,8 +1578,30 @@ impl Dir { .map(|inner| Self { inner }) } + /// Queries metadata about the underlying directory. + /// + /// # Examples + /// + /// ```no_run + /// #![feature(dirfd)] + /// use std::fs::Dir; + /// + /// fn main() -> std::io::Result<()> { + /// let dir = Dir::open("foo")?; + /// let metadata = dir.metadata()?; + /// Ok(()) + /// } + /// ``` + #[unstable(feature = "dirfd", issue = "120426")] + pub fn metadata(&self) -> io::Result { + self.inner.metadata().map(Metadata) + } + /// Attempts to open a file in read-only mode relative to this directory. /// + /// This function interprets `path` relative to the directory provided by `self`. To open a file + /// relative to the current working directory, or at an absolute path, see [`File::open`]. + /// /// # Errors /// /// This function will return an error if `path` does not point to an existing file. @@ -1646,6 +1627,98 @@ impl Dir { .open_file(path.as_ref(), &OpenOptions::new().read(true).0) .map(|f| File { inner: f }) } + + /// Attempts to open a file according to `opts` relative to this directory. + /// + /// This function interprets `path` relative to the directory provided by `self`. To open a file + /// relative to the current working directory, or at an absolute path, see [`File::open`]. + /// + /// # Errors + /// + /// This function will return an error if `path` does not point to an existing file. + /// Other errors may also be returned according to [`OpenOptions::open`]. + /// + /// # Examples + /// + /// ```no_run + /// #![feature(dirfd)] + /// use std::{fs::{Dir, OpenOptions}, io::{self, Write}}; + /// + /// fn main() -> io::Result<()> { + /// let dir = Dir::open("foo")?; + /// let mut opts = OpenOptions::new(); + /// opts.read(true).write(true); + /// let mut f = dir.open_file_with("bar.txt", &opts)?; + /// f.write_all(b"Hello, world!")?; + /// let contents = io::read_to_string(f)?; + /// assert_eq!(contents, "Hello, world!"); + /// Ok(()) + /// } + /// ``` + #[unstable(feature = "dirfd", issue = "120426")] + pub fn open_file_with>(&self, path: P, opts: &OpenOptions) -> io::Result { + self.inner.open_file(path.as_ref(), &opts.0).map(|f| File { inner: f }) + } + + /// Attempts to remove a file relative to this directory. + /// + /// This function interprets `path` relative to the directory provided by `self`. To remove a file + /// relative to the current working directory, or at an absolute path, see [`fs::remove_file`][remove_file]. + /// + /// # Errors + /// + /// This function will return an error if `path` does not point to an existing file. + /// Other errors may also be returned according to [`OpenOptions::open`]. + /// + /// # Examples + /// + /// ```no_run + /// #![feature(dirfd)] + /// use std::fs::Dir; + /// + /// fn main() -> std::io::Result<()> { + /// let dir = Dir::open("foo")?; + /// dir.remove_file("bar.txt")?; + /// Ok(()) + /// } + /// ``` + #[unstable(feature = "dirfd", issue = "120426")] + pub fn remove_file>(&self, path: P) -> io::Result<()> { + self.inner.remove_file(path.as_ref()) + } + + /// Attempts to rename a file or directory relative to this directory to a new name, replacing + /// the destination file if present. + /// + /// This function interprets `from` relative to the directory provided by `self` and `to` relative to the directory + /// provided by `to_dir`. To rename a file relative to the current working directory, or at an absolute path, see [`fs::rename`][rename]. + /// + /// # Errors + /// + /// This function will return an error if `from` does not point to an existing file or directory. + /// Other errors may also be returned according to [`OpenOptions::open`]. + /// + /// # Examples + /// + /// ```no_run + /// #![feature(dirfd)] + /// use std::fs::Dir; + /// + /// fn main() -> std::io::Result<()> { + /// let dir = Dir::open("foo")?; + /// dir.rename("bar.txt", &dir, "quux.txt")?; + /// Ok(()) + /// } + /// ``` + #[unstable(feature = "dirfd", issue = "120426")] + pub fn rename, Q: AsRef>( + &self, + from: P, + to_dir: &Self, + to: Q, + ) -> io::Result<()> { + self.inner.rename(from.as_ref(), &to_dir.inner, to.as_ref()) + } } impl AsInner for Dir { @@ -2195,6 +2268,12 @@ impl fmt::Debug for Metadata { } } +impl IntoInner for Metadata { + fn into_inner(self) -> fs_imp::FileAttr { + self.0 + } +} + impl AsInner for Metadata { #[inline] fn as_inner(&self) -> &fs_imp::FileAttr { @@ -2238,10 +2317,6 @@ impl AsInnerMut for FileTimes { } } -// For implementing OS extension traits in `std::os` -#[stable(feature = "file_set_times", since = "1.75.0")] -impl Sealed for FileTimes {} - impl Permissions { /// Returns `true` if these permissions describe a readonly (unwritable) file. /// @@ -2679,7 +2754,7 @@ impl AsInner for DirEntry { /// /// This function will only ever return an error of kind `NotFound` if the given /// path does not exist. Note that the inverse is not true, -/// ie. if a path does not exist, its removal may fail for a number of reasons, +/// i.e. if a path does not exist, its removal may fail for a number of reasons, /// such as insufficient permissions. /// /// # Examples @@ -2694,6 +2769,7 @@ impl AsInner for DirEntry { /// ``` #[doc(alias = "rm", alias = "unlink", alias = "DeleteFile")] #[stable(feature = "rust1", since = "1.0.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_remove_file")] pub fn remove_file>(path: P) -> io::Result<()> { fs_imp::remove_file(path.as_ref()) } @@ -2702,7 +2778,8 @@ pub fn remove_file>(path: P) -> io::Result<()> { /// directory, etc. /// /// This function will traverse symbolic links to query information about the -/// destination file. +/// destination file. To query metadata about the path itself without following +/// symbolic links, use [`symlink_metadata`]. /// /// # Platform-specific behavior /// @@ -2719,6 +2796,7 @@ pub fn remove_file>(path: P) -> io::Result<()> { /// /// * The user lacks permissions to perform `metadata` call on `path`. /// * `path` does not exist. +/// * `path` is a symbolic link, but the destination file cannot be resolved. /// /// # Examples /// @@ -2733,12 +2811,18 @@ pub fn remove_file>(path: P) -> io::Result<()> { /// ``` #[doc(alias = "stat")] #[stable(feature = "rust1", since = "1.0.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_metadata")] pub fn metadata>(path: P) -> io::Result { fs_imp::metadata(path.as_ref()).map(Metadata) } /// Queries the metadata about a file without following symlinks. /// +/// This function will return the [`Metadata`] of the exact path without +/// traversing symbolic links to a resolved destination file. Using this function +/// on a path that is a file or directory (not a symbolic link) will behave the +/// same as [`metadata`]. +/// /// # Platform-specific behavior /// /// This function currently corresponds to the `lstat` function on Unix @@ -2768,6 +2852,7 @@ pub fn metadata>(path: P) -> io::Result { /// ``` #[doc(alias = "lstat")] #[stable(feature = "symlink_metadata", since = "1.1.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_symlink_metadata")] pub fn symlink_metadata>(path: P) -> io::Result { fs_imp::symlink_metadata(path.as_ref()).map(Metadata) } @@ -2779,19 +2864,21 @@ pub fn symlink_metadata>(path: P) -> io::Result { /// /// # Platform-specific behavior /// -/// This function currently corresponds to the `rename` function on Unix -/// and the `MoveFileExW` or `SetFileInformationByHandle` function on Windows. +/// This function currently corresponds to the [rename] function on Unix, and +/// `MoveFileExW` with a fallback to `SetFileInformationByHandle` on Windows. +/// The exact behavior differs: /// -/// Because of this, the behavior when both `from` and `to` exist differs. On -/// Unix, if `from` is a directory, `to` must also be an (empty) directory. If -/// `from` is not a directory, `to` must also be not a directory. The behavior -/// on Windows is the same on Windows 10 1607 and higher if `FileRenameInfoEx` -/// is supported by the filesystem; otherwise, `from` can be anything, but -/// `to` must *not* be a directory. +/// - If `to` does not exist, `from` can be anything. +/// - On Unix, when `from` is a directory and `to` exists, `to` must be an empty directory. +/// - On Unix, when `from` is not a directory and `to` exists, `to` may not be a directory. +/// - On Windows 10 version 1607 and above, the behavior is the same as Unix if the +/// filesystem supports `FileRenameInfoEx`. +/// - Otherwise on Windows, `from` can be anything but `to` must not be a directory. /// /// Note that, this [may change in the future][changes]. /// /// [changes]: io#platform-specific-behavior +/// [rename]: https://pubs.opengroup.org/onlinepubs/9799919799/functions/rename.html /// /// # Errors /// @@ -2814,6 +2901,7 @@ pub fn symlink_metadata>(path: P) -> io::Result { /// ``` #[doc(alias = "mv", alias = "MoveFile", alias = "MoveFileEx")] #[stable(feature = "rust1", since = "1.0.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_rename")] pub fn rename, Q: AsRef>(from: P, to: Q) -> io::Result<()> { fs_imp::rename(from.as_ref(), to.as_ref()) } @@ -2838,8 +2926,9 @@ pub fn rename, Q: AsRef>(from: P, to: Q) -> io::Result<()> /// with `O_RDONLY` for `from` and `O_WRONLY`, `O_CREAT`, and `O_TRUNC` for `to`. /// `O_CLOEXEC` is set for returned file descriptors. /// -/// On Linux (including Android), this function attempts to use `copy_file_range(2)`, -/// and falls back to reading and writing if that is not possible. +/// On Linux (including Android), this function uses copy_file_range(2), +/// sendfile(2), or splice(2) syscalls to move data directly between files +/// if possible. /// /// On Windows, this function currently corresponds to `CopyFileEx`. Alternate /// NTFS streams are copied but only the size of the main stream is returned by @@ -2876,6 +2965,7 @@ pub fn rename, Q: AsRef>(from: P, to: Q) -> io::Result<()> #[doc(alias = "CopyFile", alias = "CopyFileEx")] #[doc(alias = "fclonefileat", alias = "fcopyfile")] #[stable(feature = "rust1", since = "1.0.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_copy")] pub fn copy, Q: AsRef>(from: P, to: Q) -> io::Result { fs_imp::copy(from.as_ref(), to.as_ref()) } @@ -2893,9 +2983,9 @@ pub fn copy, Q: AsRef>(from: P, to: Q) -> io::Result { /// /// # Platform-specific behavior /// -/// This function currently corresponds the `CreateHardLink` function on Windows. +/// This function currently corresponds to the `CreateHardLink` function on Windows. /// On most Unix systems, it corresponds to the `linkat` function with no flags. -/// On Android, VxWorks, and Redox, it instead corresponds to the `link` function. +/// On VxWorks and Redox, it instead corresponds to the `link` function. /// On MacOS, it uses the `linkat` function if it is available, but on very old /// systems where `linkat` is not available, `link` is selected at runtime instead. /// Note that, this [may change in the future][changes]. @@ -2922,6 +3012,7 @@ pub fn copy, Q: AsRef>(from: P, to: Q) -> io::Result { /// ``` #[doc(alias = "CreateHardLink", alias = "linkat")] #[stable(feature = "rust1", since = "1.0.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_hard_link")] pub fn hard_link, Q: AsRef>(original: P, link: Q) -> io::Result<()> { fs_imp::hard_link(original.as_ref(), link.as_ref()) } @@ -2988,6 +3079,7 @@ pub fn soft_link, Q: AsRef>(original: P, link: Q) -> io::Re /// } /// ``` #[stable(feature = "rust1", since = "1.0.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_read_link")] pub fn read_link>(path: P) -> io::Result { fs_imp::read_link(path.as_ref()) } @@ -3031,6 +3123,7 @@ pub fn read_link>(path: P) -> io::Result { #[doc(alias = "realpath")] #[doc(alias = "GetFinalPathNameByHandle")] #[stable(feature = "fs_canonicalize", since = "1.5.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_canonicalize")] pub fn canonicalize>(path: P) -> io::Result { fs_imp::canonicalize(path.as_ref()) } @@ -3119,6 +3212,7 @@ pub fn create_dir>(path: P) -> io::Result<()> { /// } /// ``` #[stable(feature = "rust1", since = "1.0.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_create_dir_all")] pub fn create_dir_all>(path: P) -> io::Result<()> { DirBuilder::new().recursive(true).create(path.as_ref()) } @@ -3149,7 +3243,7 @@ pub fn create_dir_all>(path: P) -> io::Result<()> { /// /// This function will only ever return an error of kind `NotFound` if the given /// path does not exist. Note that the inverse is not true, -/// ie. if a path does not exist, its removal may fail for a number of reasons, +/// i.e. if a path does not exist, its removal may fail for a number of reasons, /// such as insufficient permissions. /// /// # Examples @@ -3164,6 +3258,7 @@ pub fn create_dir_all>(path: P) -> io::Result<()> { /// ``` #[doc(alias = "rmdir", alias = "RemoveDirectory")] #[stable(feature = "rust1", since = "1.0.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_remove_dir")] pub fn remove_dir>(path: P) -> io::Result<()> { fs_imp::remove_dir(path.as_ref()) } @@ -3192,8 +3287,9 @@ pub fn remove_dir>(path: P) -> io::Result<()> { /// not be used in security-sensitive contexts: /// - **Miri**: Even when emulating targets where the underlying implementation will protect against /// TOCTOU races, Miri will not do so. -/// - **Redox OS**: This function does not protect against TOCTOU races, as Redox does not implement -/// the required platform support to do so. +/// - **ESP-IDF**, **Horizon**, **PS Vita**, **QNX**, **Redox OS**, **VxWorks**: This function does +/// not protect against TOCTOU races, as the underlying platform does not implement the required +/// platform support to do so. /// /// [TOCTOU]: self#time-of-check-to-time-of-use-toctou /// [changes]: io#platform-specific-behavior @@ -3228,6 +3324,7 @@ pub fn remove_dir>(path: P) -> io::Result<()> { /// } /// ``` #[stable(feature = "rust1", since = "1.0.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_remove_dir_all")] pub fn remove_dir_all>(path: P) -> io::Result<()> { fs_imp::remove_dir_all(path.as_ref()) } @@ -3307,6 +3404,7 @@ pub fn remove_dir_all>(path: P) -> io::Result<()> { /// ``` #[doc(alias = "ls", alias = "opendir", alias = "FindFirstFile", alias = "FindNextFile")] #[stable(feature = "rust1", since = "1.0.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_read_dir")] pub fn read_dir>(path: P) -> io::Result { fs_imp::read_dir(path.as_ref()).map(ReadDir) } @@ -3358,27 +3456,71 @@ pub fn read_dir>(path: P) -> io::Result { /// ``` #[doc(alias = "chmod", alias = "SetFileAttributes")] #[stable(feature = "set_permissions", since = "1.1.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_set_permissions")] pub fn set_permissions>(path: P, perm: Permissions) -> io::Result<()> { fs_imp::set_permissions(path.as_ref(), perm.0) } -/// Set the permissions of a file, unless it is a symlink. +/// Changes the permissions found on a file or a directory. On certain platforms, if the file +/// is a symlink, it will change the permissions bits on the symlink itself rather than +/// the target (e.g. Windows, BSD, MacOS). On other platforms, this results in an error when +/// attempting to change permissions on a symlink (e.g. Linux). /// -/// Note that the non-final path elements are allowed to be symlinks. +/// Note that non-final path elements are allowed to be symlinks. /// /// # Platform-specific behavior /// -/// Currently unimplemented on Windows. +/// This function currently corresponds to: +/// * `open` with `O_NOFOLLOW` flag enabled + `fchmod` on WASI +/// * `fchmodat` function with the flag `AT_SYMLINK_NOFOLLOW` enabled +/// on Unix platforms +/// * The flag `FILE_FLAG_OPEN_REPARSE_POINT` is enabled and then the +/// permissions of the file is set through `SetFileInformationByHandle` +/// on Windows. +/// * On all other platforms, the behavior remains the same with +/// [`fs::set_permissions`]. /// -/// On Unix platforms, this results in a [`FilesystemLoop`] error if the last element is a symlink. +/// [`fs::set_permissions`]: crate::fs::set_permissions /// -/// This behavior may change in the future. +/// Note that, this [may change in the future][changes]. /// -/// [`FilesystemLoop`]: crate::io::ErrorKind::FilesystemLoop -#[doc(alias = "chmod", alias = "SetFileAttributes")] +/// [changes]: io#platform-specific-behavior +/// +/// # Errors +/// +/// This function will return an error in the following situations, but is not +/// limited to just these cases: +/// +/// * `path` does not exist. +/// * The user lacks the permission to change attributes of the file. +/// +/// Note: On Linux, this will result in a [`Unsupported`] error +/// if the final element is a symlink. On BSD-based systems, the +/// behavior can vary from symlink permission bits changing or +/// there being no effects on symlinks +/// +/// [`Unsupported`]: crate::io::ErrorKind::Unsupported +/// +/// # Examples +/// +/// ```no_run +/// #![feature(set_permissions_nofollow)] +/// use std::fs; +/// +/// fn main() -> std::io::Result<()> { +/// let mut perms = fs::symlink_metadata("foo.txt")?.permissions(); +/// perms.set_readonly(true); +/// // This should result in an error on certain platforms +/// // or succeed in modifying the permissions of a symlink +/// fs::set_permissions_nofollow("foo.txt", perms)?; +/// Ok(()) +/// } +/// ``` +#[doc(alias = "fchmodat", alias = "SetFileInformationByHandle")] #[unstable(feature = "set_permissions_nofollow", issue = "141607")] +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_set_permissions_nofollow")] pub fn set_permissions_nofollow>(path: P, perm: Permissions) -> io::Result<()> { - fs_imp::set_permissions_nofollow(path.as_ref(), perm) + fs_imp::set_permissions_nofollow(path.as_ref(), perm.0) } impl DirBuilder { @@ -3524,6 +3666,7 @@ impl AsInnerMut for DirBuilder { /// [`Path::exists`]: crate::path::Path::exists /// [TOCTOU]: self#time-of-check-to-time-of-use-toctou #[stable(feature = "fs_try_exists", since = "1.81.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_exists")] #[inline] pub fn exists>(path: P) -> io::Result { fs_imp::exists(path.as_ref()) diff --git a/library/std/src/fs/tests.rs b/library/std/src/fs/tests.rs index 42f3ccc340b27..3a6c04146922a 100644 --- a/library/std/src/fs/tests.rs +++ b/library/std/src/fs/tests.rs @@ -1,10 +1,7 @@ use rand::RngCore; -#[cfg(not(miri))] use super::Dir; -use crate::fs::{self, File, FileTimes, OpenOptions, TryLockError}; -#[cfg(not(miri))] -use crate::io; +use crate::fs::{self, File, FileTimes, OpenOptions, TryLockError, exists}; use crate::io::prelude::*; use crate::io::{BorrowedBuf, ErrorKind, SeekFrom}; use crate::mem::MaybeUninit; @@ -20,7 +17,7 @@ use crate::path::Path; use crate::sync::Arc; use crate::test_helpers::{TempDir, tmpdir}; use crate::time::{Duration, Instant, SystemTime}; -use crate::{assert_matches, env, str, thread}; +use crate::{assert_matches, env, io, str, thread}; macro_rules! check { ($e:expr) => { @@ -31,25 +28,6 @@ macro_rules! check { }; } -#[cfg(windows)] -macro_rules! error { - ($e:expr, $s:expr) => { - match $e { - Ok(_) => panic!("Unexpected success. Should've been: {:?}", $s), - Err(ref err) => { - assert!(err.raw_os_error() == Some($s), "`{}` did not have a code of `{}`", err, $s) - } - } - }; -} - -#[cfg(unix)] -macro_rules! error { - ($e:expr, $s:expr) => { - error_contains!($e, $s) - }; -} - macro_rules! error_contains { ($e:expr, $s:expr) => { match $e { @@ -105,14 +83,8 @@ fn file_test_io_smoke_test() { fn invalid_path_raises() { let tmpdir = tmpdir(); let filename = &tmpdir.join("file_that_does_not_exist.txt"); - let result = File::open(filename); - - #[cfg(all(unix, not(target_os = "vxworks")))] - error!(result, "No such file or directory"); - #[cfg(target_os = "vxworks")] - error!(result, "no such file or directory"); - #[cfg(windows)] - error!(result, 2); // ERROR_FILE_NOT_FOUND + let err = File::open(filename).unwrap_err(); + assert_eq!(err.kind(), ErrorKind::NotFound); } #[test] @@ -120,14 +92,8 @@ fn file_test_iounlinking_invalid_path_should_raise_condition() { let tmpdir = tmpdir(); let filename = &tmpdir.join("file_another_file_that_does_not_exist.txt"); - let result = fs::remove_file(filename); - - #[cfg(all(unix, not(target_os = "vxworks")))] - error!(result, "No such file or directory"); - #[cfg(target_os = "vxworks")] - error!(result, "no such file or directory"); - #[cfg(windows)] - error!(result, 2); // ERROR_FILE_NOT_FOUND + let err = fs::remove_file(filename).unwrap_err(); + assert_eq!(err.kind(), ErrorKind::NotFound); } #[test] @@ -221,6 +187,7 @@ fn file_test_io_seek_and_write() { target_os = "netbsd", target_os = "openbsd", target_os = "solaris", + target_os = "android", target_vendor = "apple", )), should_panic @@ -254,6 +221,7 @@ fn file_lock_multiple_shared() { target_os = "netbsd", target_os = "openbsd", target_os = "solaris", + target_os = "android", target_vendor = "apple", )), should_panic @@ -288,6 +256,7 @@ fn file_lock_blocking() { target_os = "netbsd", target_os = "openbsd", target_os = "solaris", + target_os = "android", target_vendor = "apple", )), should_panic @@ -319,6 +288,7 @@ fn file_lock_drop() { target_os = "netbsd", target_os = "openbsd", target_os = "solaris", + target_os = "android", target_vendor = "apple", )), should_panic @@ -339,18 +309,43 @@ fn file_lock_dup() { } #[test] -#[cfg(windows)] -fn file_lock_double_unlock() { +#[cfg_attr( + not(any( + windows, + target_os = "aix", + target_os = "cygwin", + target_os = "freebsd", + target_os = "fuchsia", + target_os = "hurd", + target_os = "illumos", + target_os = "linux", + target_os = "netbsd", + target_os = "openbsd", + target_os = "solaris", + target_os = "android", + target_vendor = "apple", + )), + should_panic +)] +fn file_lock_double() { let tmpdir = tmpdir(); - let filename = &tmpdir.join("file_lock_double_unlock_test.txt"); + let filename = &tmpdir.join("file_lock_double_test.txt"); let f1 = check!(File::create(filename)); let f2 = check!(OpenOptions::new().write(true).open(filename)); - // On Windows a file handle may acquire both a shared and exclusive lock. - // Check that both are released by unlock() + // A file handle may acquire both a shared and exclusive lock. check!(f1.lock()); check!(f1.lock_shared()); + // The behavior here differs between Windows and Unix: on Windows, f1 holds both locks; + // on Unix, the lock got downgraded so f1 only holds the shared lock. assert_matches!(f2.try_lock(), Err(TryLockError::WouldBlock)); + if cfg!(windows) { + assert_matches!(f2.try_lock_shared(), Err(TryLockError::WouldBlock)); + } else { + check!(f2.try_lock_shared()); + check!(f2.unlock()); + } + // Check that both are released by unlock(). check!(f1.unlock()); check!(f2.try_lock()); } @@ -618,6 +613,98 @@ fn set_get_unix_permissions() { assert_eq!(mask & metadata1.permissions().mode(), 0o0777); } +#[test] +fn set_get_permissions_nofollows() { + let tmpdir = tmpdir(); + let filename = tmpdir.join("set_get_unix_permissions_file"); + check!(File::create(&filename)); + let file_metadata = check!(fs::metadata(&filename)); + assert!(!file_metadata.permissions().readonly()); + let mut permission_bits = file_metadata.permissions(); + permission_bits.set_readonly(true); + let result = fs::set_permissions_nofollow(&filename, permission_bits); + + cfg_select! { + any(windows, unix, target_os = "uefi", target_os = "solid_asp3", target_os = "motor") => { + assert_eq!(result.unwrap(), ()); + let metadata0 = check!(fs::metadata(&filename)); + assert!(metadata0.permissions().readonly()); + + // Reset the read-only bit under Windows 7: avoids the + // `TempDir::drop` from crashing on a permission denial when + // trying to delete the file that has it. + #[cfg(all(windows, target_vendor = "win7"))] + { + let mut permission_bits = metadata0.permissions(); + permission_bits.set_readonly(false); + check!(fs::set_permissions_nofollow(&filename, permission_bits)); + } + } + _ => { + let error_kind = result.unwrap_err().kind(); + assert_eq!(error_kind, crate::io::ErrorKind::Unsupported); + } + } +} + +// Only Windows and Unix support `fs::set_permissions_nofollow` +#[test] +#[cfg(all(any(windows, unix), not(any(target_os = "espidf", target_os = "horizon"))))] +fn set_get_permissions_nofollows_symlink() { + #[cfg(not(windows))] + use crate::os::unix::fs::symlink as symlink_dir; + #[cfg(windows)] + use crate::os::windows::fs::symlink_dir; + + let tmpdir = tmpdir(); + let filename = tmpdir.join("set_get_unix_permissions_file"); + let symlink_name = tmpdir.join("set_get_unix_permissions"); + check!(File::create(&filename)); + check!(symlink_dir(&filename, &symlink_name)); + + let sym_metadata = check!(fs::symlink_metadata(&symlink_name)); + let mut permission_bits = sym_metadata.permissions(); + permission_bits.set_readonly(true); + let result = fs::set_permissions_nofollow(&symlink_name, permission_bits); + + cfg_select! { + any( + windows, + target_os = "android", + target_os = "macos", + target_os = "freebsd", + target_os = "openbsd", + target_os = "netbsd", + target_os = "dragonfly" + ) => { + assert_eq!(result.unwrap(), ()); + let metadata0 = check!(fs::symlink_metadata(&symlink_name)); + // So seems like BSD-based systems trying to set permissions + // on symlinks could lead to no effect, so we should expect + // there being no change to BSD-based systems. + // https://superuser.com/questions/1099634/change-permissions-symbolic-link-mac-os + #[cfg(windows)] + assert!(metadata0.permissions().readonly()); + #[cfg(not(windows))] + assert!(!metadata0.permissions().readonly()); + + // Reset the read-only bit under Windows 7: avoids the + // `TempDir::drop` from crashing on a permission denial when + // trying to delete the file that has it. + #[cfg(all(windows, target_vendor = "win7"))] + { + let mut permission_bits = metadata0.permissions(); + permission_bits.set_readonly(false); + check!(fs::set_permissions_nofollow(&symlink_name, permission_bits)); + } + } + _ => { + let error_kind = result.unwrap_err().kind(); + assert_eq!(error_kind, crate::io::ErrorKind::Unsupported); + } + } +} + #[test] #[cfg(windows)] fn file_test_io_seek_read_write() { @@ -717,7 +804,7 @@ fn file_test_read_buf() { check!(file.read_buf(buf.unfilled())); assert_eq!(buf.filled(), &[1, 2, 3, 4]); // File::read_buf should omit buffer initialization. - assert_eq!(buf.init_len(), 4); + assert!(!buf.is_init()); check!(fs::remove_file(filename)); } @@ -856,10 +943,12 @@ fn recursive_mkdir_failure() { #[test] fn concurrent_recursive_mkdir() { - for _ in 0..100 { + let count = if cfg!(miri) { 10 } else { 100 }; + let nest = if cfg!(miri) { 10 } else { 40 }; + for _ in 0..count { let dir = tmpdir(); let mut dir = dir.join("a"); - for _ in 0..40 { + for _ in 0..nest { dir = dir.join("a"); } let mut join = vec![]; @@ -881,6 +970,10 @@ fn recursive_mkdir_slash() { } #[test] +#[cfg_attr( + target_os = "l4re", + ignore = "Path '.' in the file system root can not be resolved in L4Re" +)] fn recursive_mkdir_dot() { check!(fs::create_dir_all(Path::new("."))); } @@ -939,12 +1032,8 @@ fn recursive_rmdir_of_file_fails() { let tmpdir = tmpdir(); let canary = tmpdir.join("do_not_delete"); check!(check!(File::create(&canary)).write(b"foo")); - let result = fs::remove_dir_all(&canary); - #[cfg(unix)] - error!(result, "Not a directory"); - #[cfg(windows)] - error!(result, 267); // ERROR_DIRECTORY - The directory name is invalid. - assert!(result.is_err()); + let err = fs::remove_dir_all(&canary).unwrap_err(); + assert_eq!(err.kind(), ErrorKind::NotADirectory); assert!(canary.exists()); } @@ -1337,6 +1426,29 @@ fn fchmod_works() { check!(file.set_permissions(p)); } +#[test] +fn fchmodat_works() { + let tmpdir = tmpdir(); + let file = tmpdir.join("in.txt"); + + check!(File::create(&file)); + let attr = check!(fs::metadata(&file)); + assert!(!attr.permissions().readonly()); + let mut p = attr.permissions(); + p.set_readonly(true); + check!(fs::set_permissions_nofollow(&file, p.clone())); + let attr = check!(fs::metadata(&file)); + assert!(attr.permissions().readonly()); + + match fs::set_permissions_nofollow(&tmpdir.join("foo"), p.clone()) { + Ok(..) => panic!("wanted an error"), + Err(..) => {} + } + + p.set_readonly(false); + check!(fs::set_permissions_nofollow(&file, p)); +} + #[test] fn sync_doesnt_kill_anything() { let tmpdir = tmpdir(); @@ -1404,7 +1516,9 @@ fn open_flavors() { let mut ra = OO::new(); ra.read(true).append(true); + // This error string is set by std itself so we are not at the whim of the OS here. let invalid_options = "creating or truncating a file requires write or append access"; + let append_truncate_error = "append and truncate cannot both be enabled"; // Test various combinations of creation modes and access modes. // @@ -1442,15 +1556,21 @@ fn open_flavors() { // append check!(c(&a).create_new(true).open(&tmpdir.join("d"))); - error_contains!(c(&a).create(true).truncate(true).open(&tmpdir.join("d")), invalid_options); - error_contains!(c(&a).truncate(true).open(&tmpdir.join("d")), invalid_options); + error_contains!( + c(&a).create(true).truncate(true).open(&tmpdir.join("d")), + append_truncate_error + ); + error_contains!(c(&a).truncate(true).open(&tmpdir.join("d")), append_truncate_error); check!(c(&a).create(true).open(&tmpdir.join("d"))); check!(c(&a).open(&tmpdir.join("d"))); // read-append check!(c(&ra).create_new(true).open(&tmpdir.join("e"))); - error_contains!(c(&ra).create(true).truncate(true).open(&tmpdir.join("e")), invalid_options); - error_contains!(c(&ra).truncate(true).open(&tmpdir.join("e")), invalid_options); + error_contains!( + c(&ra).create(true).truncate(true).open(&tmpdir.join("e")), + append_truncate_error + ); + error_contains!(c(&ra).truncate(true).open(&tmpdir.join("e")), append_truncate_error); check!(c(&ra).create(true).open(&tmpdir.join("e"))); check!(c(&ra).open(&tmpdir.join("e"))); @@ -1729,8 +1849,29 @@ fn create_dir_all_with_junctions() { assert!(d.exists()); } +#[test] +#[cfg(windows)] +fn junction_point_overlong_path() { + // Regression test: an `original` path long enough to exceed the inline + // reparse buffer used to be copied past the end of the stack array. It must + // now be rejected with a clean error instead of overflowing. + let tmpdir = tmpdir(); + let link = tmpdir.join("junction"); + + // The `\\?\` prefix bypasses MAX_PATH normalization so the path is copied + // through verbatim. 20_000 code units lands in the old overflow window: it + // passed the previous `> u16::MAX` byte check yet exceeded the buffer. + let mut original = String::from(r"\\?\C:\"); + original.push_str(&"a".repeat(20_000)); + + let err = junction_point(Path::new(&original), &link).unwrap_err(); + assert_eq!(err.kind(), ErrorKind::InvalidInput); +} + #[test] fn metadata_access_times() { + let start_time = SystemTime::now(); + let tmpdir = tmpdir(); let b = tmpdir.join("b"); @@ -1751,7 +1892,14 @@ fn metadata_access_times() { if cfg!(target_os = "linux") { // Not always available match (a.created(), b.created()) { - (Ok(t1), Ok(t2)) => assert!(t1 <= t2), + // It could be that, when the system clock goes backwards (e.g., due time change) + // b, that gets created after a, has a greater creation date than a. + // When such rare case occurs we skip the test, since the test to check that b + // should be created after a would fail. + (Ok(t1), Ok(t2)) => match start_time.elapsed() { + Ok(_) => assert!(t1 <= t2), + Err(_) => {} + }, (Err(e1), Err(e2)) if e1.kind() == ErrorKind::Uncategorized && e2.kind() == ErrorKind::Uncategorized @@ -1860,7 +2008,7 @@ fn create_dir_long_paths() { fn read_large_dir() { let tmpdir = tmpdir(); - let count = 32 * 1024; + let count = if cfg!(miri) { 1024 } else { 32 * 1024 }; for i in 0..count { check!(fs::File::create(tmpdir.join(&i.to_string()))); } @@ -1945,6 +2093,7 @@ fn test_eq_windows_file_type() { /// Regression test for https://github.com/rust-lang/rust/issues/50619. #[test] #[cfg(target_os = "linux")] +#[cfg_attr(miri, ignore)] // Cannot spawn processes on Miri fn test_read_dir_infinite_loop() { use crate::io::ErrorKind; use crate::process::Command; @@ -1987,6 +2136,7 @@ fn rename_directory() { } #[test] +#[cfg_attr(target_os = "l4re", ignore = "futimens")] fn test_file_times() { #[cfg(target_vendor = "apple")] use crate::os::darwin::fs::FileTimesExt; @@ -2015,7 +2165,8 @@ fn test_file_times() { target_os = "android", target_os = "redox", target_os = "espidf", - target_os = "horizon" + target_os = "horizon", + target_os = "l4re", )) ) )))] @@ -2139,7 +2290,6 @@ fn test_hidden_file_truncation() { // See https://github.com/rust-lang/rust/pull/131072 for more details about why // these two tests are disabled under Windows 7 here. -#[cfg(windows)] #[test] #[cfg_attr(target_vendor = "win7", ignore = "Unsupported under Windows 7.")] fn test_rename_file_over_open_file() { @@ -2165,10 +2315,9 @@ fn test_rename_file_over_open_file() { } #[test] -#[cfg(windows)] #[cfg_attr(target_vendor = "win7", ignore = "Unsupported under Windows 7.")] fn test_rename_directory_to_non_empty_directory() { - // Renaming a directory over a non-empty existing directory should fail on Windows. + // Renaming a directory over a non-empty existing directory should fail. let tmpdir: TempDir = tmpdir(); let source_path = tmpdir.join("source_directory"); @@ -2179,7 +2328,14 @@ fn test_rename_directory_to_non_empty_directory() { fs::write(target_path.join("target_file.txt"), b"target hello world").unwrap(); - error!(fs::rename(source_path, target_path), 145); // ERROR_DIR_NOT_EMPTY + let err = fs::rename(source_path, target_path).unwrap_err(); + assert_matches!( + err.kind(), + // On ext4, ntfs, apfs, tmpfs, and btrfs `DirectoryNotEmpty` is returned. + // On xfs `AlreadyExists` is returned. + ErrorKind::DirectoryNotEmpty | ErrorKind::AlreadyExists, + "Expected DirectoryNotEmpty or AlreadyExists error, got {err}" + ); } #[test] @@ -2227,7 +2383,6 @@ fn test_open_options_invalid_combinations() { (|| OO::new().create(true).read(true).clone(), "create without write"), (|| OO::new().create_new(true).read(true).clone(), "create_new without write"), (|| OO::new().truncate(true).read(true).clone(), "truncate without write"), - (|| OO::new().truncate(true).append(true).clone(), "truncate with append"), ]; for (make_opts, desc) in test_cases { @@ -2242,7 +2397,13 @@ fn test_open_options_invalid_combinations() { "{desc} - wrong error message" ); } + let result = OO::new().truncate(true).append(true).open("nonexistent.txt"); + assert!(result.is_err(), "truncate with append should fail"); + + let err = result.unwrap_err(); + assert_eq!(err.kind(), ErrorKind::InvalidInput); + assert_eq!(err.to_string(), "append and truncate cannot both be enabled"); let result = OO::new().open("nonexistent.txt"); assert!(result.is_err(), "no access mode should fail"); let err = result.unwrap_err(); @@ -2360,6 +2521,9 @@ fn test_fs_set_times_follows_symlink() { use crate::os::windows::fs::FileTimesExt; let tmp = tmpdir(); + if !got_symlink_permission(&tmp) { + return; + } // Create a target file let target = tmp.join("target"); @@ -2458,6 +2622,9 @@ fn test_fs_set_times_nofollow() { use crate::os::windows::fs::FileTimesExt; let tmp = tmpdir(); + if !got_symlink_permission(&tmp) { + return; + } // Create a target file and a symlink to it let target = tmp.join("target"); @@ -2521,8 +2688,6 @@ fn test_fs_set_times_nofollow() { } #[test] -// FIXME: libc calls fail on miri -#[cfg(not(miri))] fn test_dir_smoke_test() { let tmpdir = tmpdir(); let dir = Dir::open(tmpdir.path()); @@ -2530,13 +2695,10 @@ fn test_dir_smoke_test() { } #[test] -// FIXME: libc calls fail on miri -#[cfg(not(miri))] fn test_dir_read_file() { let tmpdir = tmpdir(); let mut f = check!(File::create(tmpdir.join("foo.txt"))); - check!(f.write(b"bar")); - check!(f.flush()); + check!(f.write_all(b"bar")); drop(f); let dir = check!(Dir::open(tmpdir.path())); let f = check!(dir.open_file("foo.txt")); @@ -2546,3 +2708,51 @@ fn test_dir_read_file() { let buf = check!(io::read_to_string(f)); assert_eq!("bar", &buf); } + +#[test] +fn test_dir_metadata() { + let tmpdir = tmpdir(); + let dir = check!(Dir::open(tmpdir.path())); + let metadata = check!(dir.metadata()); + assert!(metadata.is_dir()); +} + +#[test] +fn test_dir_write_file() { + let tmpdir = tmpdir(); + let dir = check!(Dir::open(tmpdir.path())); + let mut f = check!(dir.open_file_with("foo.txt", &OpenOptions::new().write(true).create(true))); + check!(f.write(b"bar")); + check!(f.flush()); + drop(f); + let mut f = check!(File::open(tmpdir.join("foo.txt"))); + let mut buf = [0u8; 3]; + check!(f.read_exact(&mut buf)); + assert_eq!(b"bar", &buf); +} + +#[test] +fn test_dir_remove_file() { + let tmpdir = tmpdir(); + let mut f = check!(File::create(tmpdir.join("foo.txt"))); + check!(f.write(b"bar")); + check!(f.flush()); + drop(f); + let dir = check!(Dir::open(tmpdir.path())); + check!(dir.remove_file("foo.txt")); + assert!(!matches!(exists(tmpdir.join("foo.txt")), Ok(true))); +} + +#[test] +fn test_dir_rename_file() { + let tmpdir = tmpdir(); + let mut f = check!(File::create(tmpdir.join("foo.txt"))); + check!(f.write_all(b"bar")); + drop(f); + let dir = check!(Dir::open(tmpdir.path())); + check!(dir.rename("foo.txt", &dir, "baz.txt")); + let mut f = check!(File::open(tmpdir.join("baz.txt"))); + let mut buf = [0u8; 3]; + check!(f.read_exact(&mut buf)); + assert_eq!(b"bar", &buf); +} diff --git a/library/std/src/hash/random.rs b/library/std/src/hash/random.rs index 3c1b21eec9759..b9c21ab2d6a65 100644 --- a/library/std/src/hash/random.rs +++ b/library/std/src/hash/random.rs @@ -110,7 +110,7 @@ impl DefaultHasher { #[stable(feature = "hashmap_default_hasher", since = "1.13.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for DefaultHasher { +const impl Default for DefaultHasher { /// Creates a new `DefaultHasher` using [`new`]. /// See its documentation for more. /// diff --git a/library/std/src/io/error.rs b/library/std/src/io/error.rs index e6c6f7d766c02..6dbe37ca9fba8 100644 --- a/library/std/src/io/error.rs +++ b/library/std/src/io/error.rs @@ -1,633 +1,20 @@ #[cfg(test)] mod tests; -// On 64-bit platforms, `io::Error` may use a bit-packed representation to -// reduce size. However, this representation assumes that error codes are -// always 32-bit wide. -// -// This assumption is invalid on 64-bit UEFI, where error codes are 64-bit. -// Therefore, the packed representation is explicitly disabled for UEFI -// targets, and the unpacked representation must be used instead. -#[cfg(all(target_pointer_width = "64", not(target_os = "uefi")))] -mod repr_bitpacked; -#[cfg(all(target_pointer_width = "64", not(target_os = "uefi")))] -use repr_bitpacked::Repr; - -#[cfg(any(not(target_pointer_width = "64"), target_os = "uefi"))] -mod repr_unpacked; -#[cfg(any(not(target_pointer_width = "64"), target_os = "uefi"))] -use repr_unpacked::Repr; - -use crate::{error, fmt, result, sys}; - -/// A specialized [`Result`] type for I/O operations. -/// -/// This type is broadly used across [`std::io`] for any operation which may -/// produce an error. -/// -/// This type alias is generally used to avoid writing out [`io::Error`] directly and -/// is otherwise a direct mapping to [`Result`]. -/// -/// While usual Rust style is to import types directly, aliases of [`Result`] -/// often are not, to make it easier to distinguish between them. [`Result`] is -/// generally assumed to be [`std::result::Result`][`Result`], and so users of this alias -/// will generally use `io::Result` instead of shadowing the [prelude]'s import -/// of [`std::result::Result`][`Result`]. -/// -/// [`std::io`]: crate::io -/// [`io::Error`]: Error -/// [`Result`]: crate::result::Result -/// [prelude]: crate::prelude -/// -/// # Examples -/// -/// A convenience function that bubbles an `io::Result` to its caller: -/// -/// ``` -/// use std::io; -/// -/// fn get_string() -> io::Result { -/// let mut buffer = String::new(); -/// -/// io::stdin().read_line(&mut buffer)?; -/// -/// Ok(buffer) -/// } -/// ``` -#[stable(feature = "rust1", since = "1.0.0")] -#[doc(search_unbox)] -pub type Result = result::Result; - -/// The error type for I/O operations of the [`Read`], [`Write`], [`Seek`], and -/// associated traits. -/// -/// Errors mostly originate from the underlying OS, but custom instances of -/// `Error` can be created with crafted error messages and a particular value of -/// [`ErrorKind`]. -/// -/// [`Read`]: crate::io::Read -/// [`Write`]: crate::io::Write -/// [`Seek`]: crate::io::Seek -#[stable(feature = "rust1", since = "1.0.0")] -pub struct Error { - repr: Repr, -} - -#[stable(feature = "rust1", since = "1.0.0")] -impl fmt::Debug for Error { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - fmt::Debug::fmt(&self.repr, f) - } -} - -/// Common errors constants for use in std -#[allow(dead_code)] -impl Error { - pub(crate) const INVALID_UTF8: Self = - const_error!(ErrorKind::InvalidData, "stream did not contain valid UTF-8"); - - pub(crate) const READ_EXACT_EOF: Self = - const_error!(ErrorKind::UnexpectedEof, "failed to fill whole buffer"); - - pub(crate) const UNKNOWN_THREAD_COUNT: Self = const_error!( - ErrorKind::NotFound, - "the number of hardware threads is not known for the target platform", - ); - - pub(crate) const UNSUPPORTED_PLATFORM: Self = - const_error!(ErrorKind::Unsupported, "operation not supported on this platform"); - - pub(crate) const WRITE_ALL_EOF: Self = - const_error!(ErrorKind::WriteZero, "failed to write whole buffer"); - - pub(crate) const ZERO_TIMEOUT: Self = - const_error!(ErrorKind::InvalidInput, "cannot set a 0 duration timeout"); - - pub(crate) const NO_ADDRESSES: Self = - const_error!(ErrorKind::InvalidInput, "could not resolve to any addresses"); -} - -#[stable(feature = "rust1", since = "1.0.0")] -impl From for Error { - /// Converts a [`alloc::ffi::NulError`] into a [`Error`]. - fn from(_: alloc::ffi::NulError) -> Error { - const_error!(ErrorKind::InvalidInput, "data provided contains a nul byte") - } -} - -#[stable(feature = "io_error_from_try_reserve", since = "1.78.0")] -impl From for Error { - /// Converts `TryReserveError` to an error with [`ErrorKind::OutOfMemory`]. - /// - /// `TryReserveError` won't be available as the error `source()`, - /// but this may change in the future. - fn from(_: alloc::collections::TryReserveError) -> Error { - // ErrorData::Custom allocates, which isn't great for handling OOM errors. - ErrorKind::OutOfMemory.into() - } -} - -// Only derive debug in tests, to make sure it -// doesn't accidentally get printed. -#[cfg_attr(test, derive(Debug))] -enum ErrorData { - Os(RawOsError), - Simple(ErrorKind), - SimpleMessage(&'static SimpleMessage), - Custom(C), -} - -/// The type of raw OS error codes returned by [`Error::raw_os_error`]. -/// -/// This is an [`i32`] on all currently supported platforms, but platforms -/// added in the future (such as UEFI) may use a different primitive type like -/// [`usize`]. Use `as`or [`into`] conversions where applicable to ensure maximum -/// portability. -/// -/// [`into`]: Into::into -#[unstable(feature = "raw_os_error_ty", issue = "107792")] -pub type RawOsError = sys::io::RawOsError; - -// `#[repr(align(4))]` is probably redundant, it should have that value or -// higher already. We include it just because repr_bitpacked.rs's encoding -// requires an alignment >= 4 (note that `#[repr(align)]` will not reduce the -// alignment required by the struct, only increase it). -// -// If we add more variants to ErrorData, this can be increased to 8, but it -// should probably be behind `#[cfg_attr(target_pointer_width = "64", ...)]` or -// whatever cfg we're using to enable the `repr_bitpacked` code, since only the -// that version needs the alignment, and 8 is higher than the alignment we'll -// have on 32 bit platforms. -// -// (For the sake of being explicit: the alignment requirement here only matters -// if `error/repr_bitpacked.rs` is in use — for the unpacked repr it doesn't -// matter at all) -#[doc(hidden)] -#[unstable(feature = "io_const_error_internals", issue = "none")] -#[repr(align(4))] -#[derive(Debug)] -pub struct SimpleMessage { - pub kind: ErrorKind, - pub message: &'static str, -} - -/// Creates a new I/O error from a known kind of error and a string literal. -/// -/// Contrary to [`Error::new`], this macro does not allocate and can be used in -/// `const` contexts. -/// -/// # Example -/// ``` -/// #![feature(io_const_error)] -/// use std::io::{const_error, Error, ErrorKind}; -/// -/// const FAIL: Error = const_error!(ErrorKind::Unsupported, "tried something that never works"); -/// -/// fn not_here() -> Result<(), Error> { -/// Err(FAIL) -/// } -/// ``` -#[rustc_macro_transparency = "semiopaque"] -#[unstable(feature = "io_const_error", issue = "133448")] -#[allow_internal_unstable(hint_must_use, io_const_error_internals)] -pub macro const_error($kind:expr, $message:expr $(,)?) { - $crate::hint::must_use($crate::io::Error::from_static_message( - const { &$crate::io::SimpleMessage { kind: $kind, message: $message } }, - )) -} - -// As with `SimpleMessage`: `#[repr(align(4))]` here is just because -// repr_bitpacked's encoding requires it. In practice it almost certainly be -// already be this high or higher. -#[derive(Debug)] -#[repr(align(4))] -struct Custom { - kind: ErrorKind, - error: Box, -} - -/// A list specifying general categories of I/O error. -/// -/// This list is intended to grow over time and it is not recommended to -/// exhaustively match against it. -/// -/// It is used with the [`io::Error`] type. -/// -/// [`io::Error`]: Error -/// -/// # Handling errors and matching on `ErrorKind` -/// -/// In application code, use `match` for the `ErrorKind` values you are -/// expecting; use `_` to match "all other errors". -/// -/// In comprehensive and thorough tests that want to verify that a test doesn't -/// return any known incorrect error kind, you may want to cut-and-paste the -/// current full list of errors from here into your test code, and then match -/// `_` as the correct case. This seems counterintuitive, but it will make your -/// tests more robust. In particular, if you want to verify that your code does -/// produce an unrecognized error kind, the robust solution is to check for all -/// the recognized error kinds and fail in those cases. -#[derive(Clone, Copy, Debug, Eq, Hash, Ord, PartialEq, PartialOrd)] -#[stable(feature = "rust1", since = "1.0.0")] -#[cfg_attr(not(test), rustc_diagnostic_item = "io_errorkind")] -#[allow(deprecated)] -#[non_exhaustive] -pub enum ErrorKind { - /// An entity was not found, often a file. - #[stable(feature = "rust1", since = "1.0.0")] - NotFound, - /// The operation lacked the necessary privileges to complete. - #[stable(feature = "rust1", since = "1.0.0")] - PermissionDenied, - /// The connection was refused by the remote server. - #[stable(feature = "rust1", since = "1.0.0")] - ConnectionRefused, - /// The connection was reset by the remote server. - #[stable(feature = "rust1", since = "1.0.0")] - ConnectionReset, - /// The remote host is not reachable. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - HostUnreachable, - /// The network containing the remote host is not reachable. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - NetworkUnreachable, - /// The connection was aborted (terminated) by the remote server. - #[stable(feature = "rust1", since = "1.0.0")] - ConnectionAborted, - /// The network operation failed because it was not connected yet. - #[stable(feature = "rust1", since = "1.0.0")] - NotConnected, - /// A socket address could not be bound because the address is already in - /// use elsewhere. - #[stable(feature = "rust1", since = "1.0.0")] - AddrInUse, - /// A nonexistent interface was requested or the requested address was not - /// local. - #[stable(feature = "rust1", since = "1.0.0")] - AddrNotAvailable, - /// The system's networking is down. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - NetworkDown, - /// The operation failed because a pipe was closed. - #[stable(feature = "rust1", since = "1.0.0")] - BrokenPipe, - /// An entity already exists, often a file. - #[stable(feature = "rust1", since = "1.0.0")] - AlreadyExists, - /// The operation needs to block to complete, but the blocking operation was - /// requested to not occur. - #[stable(feature = "rust1", since = "1.0.0")] - WouldBlock, - /// A filesystem object is, unexpectedly, not a directory. - /// - /// For example, a filesystem path was specified where one of the intermediate directory - /// components was, in fact, a plain file. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - NotADirectory, - /// The filesystem object is, unexpectedly, a directory. - /// - /// A directory was specified when a non-directory was expected. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - IsADirectory, - /// A non-empty directory was specified where an empty directory was expected. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - DirectoryNotEmpty, - /// The filesystem or storage medium is read-only, but a write operation was attempted. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - ReadOnlyFilesystem, - /// Loop in the filesystem or IO subsystem; often, too many levels of symbolic links. - /// - /// There was a loop (or excessively long chain) resolving a filesystem object - /// or file IO object. - /// - /// On Unix this is usually the result of a symbolic link loop; or, of exceeding the - /// system-specific limit on the depth of symlink traversal. - #[unstable(feature = "io_error_more", issue = "86442")] - FilesystemLoop, - /// Stale network file handle. - /// - /// With some network filesystems, notably NFS, an open file (or directory) can be invalidated - /// by problems with the network or server. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - StaleNetworkFileHandle, - /// A parameter was incorrect. - #[stable(feature = "rust1", since = "1.0.0")] - InvalidInput, - /// Data not valid for the operation were encountered. - /// - /// Unlike [`InvalidInput`], this typically means that the operation - /// parameters were valid, however the error was caused by malformed - /// input data. - /// - /// For example, a function that reads a file into a string will error with - /// `InvalidData` if the file's contents are not valid UTF-8. - /// - /// [`InvalidInput`]: ErrorKind::InvalidInput - #[stable(feature = "io_invalid_data", since = "1.2.0")] - InvalidData, - /// The I/O operation's timeout expired, causing it to be canceled. - #[stable(feature = "rust1", since = "1.0.0")] - TimedOut, - /// An error returned when an operation could not be completed because a - /// call to [`write`] returned [`Ok(0)`]. - /// - /// This typically means that an operation could only succeed if it wrote a - /// particular number of bytes but only a smaller number of bytes could be - /// written. - /// - /// [`write`]: crate::io::Write::write - /// [`Ok(0)`]: Ok - #[stable(feature = "rust1", since = "1.0.0")] - WriteZero, - /// The underlying storage (typically, a filesystem) is full. - /// - /// This does not include out of quota errors. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - StorageFull, - /// Seek on unseekable file. - /// - /// Seeking was attempted on an open file handle which is not suitable for seeking - for - /// example, on Unix, a named pipe opened with `File::open`. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - NotSeekable, - /// Filesystem quota or some other kind of quota was exceeded. - #[stable(feature = "io_error_quota_exceeded", since = "1.85.0")] - QuotaExceeded, - /// File larger than allowed or supported. - /// - /// This might arise from a hard limit of the underlying filesystem or file access API, or from - /// an administratively imposed resource limitation. Simple disk full, and out of quota, have - /// their own errors. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - FileTooLarge, - /// Resource is busy. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - ResourceBusy, - /// Executable file is busy. - /// - /// An attempt was made to write to a file which is also in use as a running program. (Not all - /// operating systems detect this situation.) - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - ExecutableFileBusy, - /// Deadlock (avoided). - /// - /// A file locking operation would result in deadlock. This situation is typically detected, if - /// at all, on a best-effort basis. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - Deadlock, - /// Cross-device or cross-filesystem (hard) link or rename. - #[stable(feature = "io_error_crosses_devices", since = "1.85.0")] - CrossesDevices, - /// Too many (hard) links to the same filesystem object. - /// - /// The filesystem does not support making so many hardlinks to the same file. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - TooManyLinks, - /// A filename was invalid. - /// - /// This error can also occur if a length limit for a name was exceeded. - #[stable(feature = "io_error_invalid_filename", since = "1.87.0")] - InvalidFilename, - /// Program argument list too long. - /// - /// When trying to run an external program, a system or process limit on the size of the - /// arguments would have been exceeded. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - ArgumentListTooLong, - /// This operation was interrupted. - /// - /// Interrupted operations can typically be retried. - #[stable(feature = "rust1", since = "1.0.0")] - Interrupted, - - /// This operation is unsupported on this platform. - /// - /// This means that the operation can never succeed. - #[stable(feature = "unsupported_error", since = "1.53.0")] - Unsupported, - - // ErrorKinds which are primarily categorisations for OS error - // codes should be added above. - // - /// An error returned when an operation could not be completed because an - /// "end of file" was reached prematurely. - /// - /// This typically means that an operation could only succeed if it read a - /// particular number of bytes but only a smaller number of bytes could be - /// read. - #[stable(feature = "read_exact", since = "1.6.0")] - UnexpectedEof, - - /// An operation could not be completed, because it failed - /// to allocate enough memory. - #[stable(feature = "out_of_memory_error", since = "1.54.0")] - OutOfMemory, - - /// The operation was partially successful and needs to be checked - /// later on due to not blocking. - #[unstable(feature = "io_error_inprogress", issue = "130840")] - InProgress, - - // "Unusual" error kinds which do not correspond simply to (sets - // of) OS error codes, should be added just above this comment. - // `Other` and `Uncategorized` should remain at the end: - // - /// A custom error that does not fall under any other I/O error kind. - /// - /// This can be used to construct your own [`Error`]s that do not match any - /// [`ErrorKind`]. - /// - /// This [`ErrorKind`] is not used by the standard library. - /// - /// Errors from the standard library that do not fall under any of the I/O - /// error kinds cannot be `match`ed on, and will only match a wildcard (`_`) pattern. - /// New [`ErrorKind`]s might be added in the future for some of those. - #[stable(feature = "rust1", since = "1.0.0")] - Other, - - /// Any I/O error from the standard library that's not part of this list. - /// - /// Errors that are `Uncategorized` now may move to a different or a new - /// [`ErrorKind`] variant in the future. It is not recommended to match - /// an error against `Uncategorized`; use a wildcard match (`_`) instead. - #[unstable(feature = "io_error_uncategorized", issue = "none")] - #[doc(hidden)] - Uncategorized, -} - -impl ErrorKind { - pub(crate) fn as_str(&self) -> &'static str { - use ErrorKind::*; - match *self { - // tidy-alphabetical-start - AddrInUse => "address in use", - AddrNotAvailable => "address not available", - AlreadyExists => "entity already exists", - ArgumentListTooLong => "argument list too long", - BrokenPipe => "broken pipe", - ConnectionAborted => "connection aborted", - ConnectionRefused => "connection refused", - ConnectionReset => "connection reset", - CrossesDevices => "cross-device link or rename", - Deadlock => "deadlock", - DirectoryNotEmpty => "directory not empty", - ExecutableFileBusy => "executable file busy", - FileTooLarge => "file too large", - FilesystemLoop => "filesystem loop or indirection limit (e.g. symlink loop)", - HostUnreachable => "host unreachable", - InProgress => "in progress", - Interrupted => "operation interrupted", - InvalidData => "invalid data", - InvalidFilename => "invalid filename", - InvalidInput => "invalid input parameter", - IsADirectory => "is a directory", - NetworkDown => "network down", - NetworkUnreachable => "network unreachable", - NotADirectory => "not a directory", - NotConnected => "not connected", - NotFound => "entity not found", - NotSeekable => "seek on unseekable file", - Other => "other error", - OutOfMemory => "out of memory", - PermissionDenied => "permission denied", - QuotaExceeded => "quota exceeded", - ReadOnlyFilesystem => "read-only filesystem or storage medium", - ResourceBusy => "resource busy", - StaleNetworkFileHandle => "stale network file handle", - StorageFull => "no storage space", - TimedOut => "timed out", - TooManyLinks => "too many links", - Uncategorized => "uncategorized error", - UnexpectedEof => "unexpected end of file", - Unsupported => "unsupported", - WouldBlock => "operation would block", - WriteZero => "write zero", - // tidy-alphabetical-end - } - } -} - -#[stable(feature = "io_errorkind_display", since = "1.60.0")] -impl fmt::Display for ErrorKind { - /// Shows a human-readable description of the `ErrorKind`. - /// - /// This is similar to `impl Display for Error`, but doesn't require first converting to Error. - /// - /// # Examples - /// ``` - /// use std::io::ErrorKind; - /// assert_eq!("entity not found", ErrorKind::NotFound.to_string()); - /// ``` - fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { - fmt.write_str(self.as_str()) - } -} - -/// Intended for use for errors not exposed to the user, where allocating onto -/// the heap (for normal construction via Error::new) is too costly. -#[stable(feature = "io_error_from_errorkind", since = "1.14.0")] -impl From for Error { - /// Converts an [`ErrorKind`] into an [`Error`]. - /// - /// This conversion creates a new error with a simple representation of error kind. - /// - /// # Examples - /// - /// ``` - /// use std::io::{Error, ErrorKind}; - /// - /// let not_found = ErrorKind::NotFound; - /// let error = Error::from(not_found); - /// assert_eq!("entity not found", format!("{error}")); - /// ``` - #[inline] - fn from(kind: ErrorKind) -> Error { - Error { repr: Repr::new_simple(kind) } - } -} - +#[cfg_attr( + test, + expect(unused, reason = "only used in implementation for non-test compilation") +)] +use crate::{ + io::{Error, OsFunctions, RawOsError}, + sys::io::{decode_error_kind, errno, error_string, is_interrupted}, +}; + +// Because std is linked in during testing, these incoherent implementations would +// be duplicated if this was unconditionally included. +// See #2912 for details. +#[cfg(not(test))] impl Error { - /// Creates a new I/O error from a known kind of error as well as an - /// arbitrary error payload. - /// - /// This function is used to generically create I/O errors which do not - /// originate from the OS itself. The `error` argument is an arbitrary - /// payload which will be contained in this [`Error`]. - /// - /// Note that this function allocates memory on the heap. - /// If no extra payload is required, use the `From` conversion from - /// `ErrorKind`. - /// - /// # Examples - /// - /// ``` - /// use std::io::{Error, ErrorKind}; - /// - /// // errors can be created from strings - /// let custom_error = Error::new(ErrorKind::Other, "oh no!"); - /// - /// // errors can also be created from other errors - /// let custom_error2 = Error::new(ErrorKind::Interrupted, custom_error); - /// - /// // creating an error without payload (and without memory allocation) - /// let eof_error = Error::from(ErrorKind::UnexpectedEof); - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - #[cfg_attr(not(test), rustc_diagnostic_item = "io_error_new")] - #[inline(never)] - pub fn new(kind: ErrorKind, error: E) -> Error - where - E: Into>, - { - Self::_new(kind, error.into()) - } - - /// Creates a new I/O error from an arbitrary error payload. - /// - /// This function is used to generically create I/O errors which do not - /// originate from the OS itself. It is a shortcut for [`Error::new`] - /// with [`ErrorKind::Other`]. - /// - /// # Examples - /// - /// ``` - /// use std::io::Error; - /// - /// // errors can be created from strings - /// let custom_error = Error::other("oh no!"); - /// - /// // errors can also be created from other errors - /// let custom_error2 = Error::other(custom_error); - /// ``` - #[stable(feature = "io_error_other", since = "1.74.0")] - pub fn other(error: E) -> Error - where - E: Into>, - { - Self::_new(ErrorKind::Other, error.into()) - } - - fn _new(kind: ErrorKind, error: Box) -> Error { - Error { repr: Repr::new_custom(Box::new(Custom { kind, error })) } - } - - /// Creates a new I/O error from a known kind of error as well as a constant - /// message. - /// - /// This function does not allocate. - /// - /// You should not use this directly, and instead use the `const_error!` - /// macro: `io::const_error!(ErrorKind::Something, "some_message")`. - /// - /// This function should maybe change to `from_static_message(kind: ErrorKind)` in the future, when const generics allow that. - #[inline] - #[doc(hidden)] - #[unstable(feature = "io_const_error_internals", issue = "none")] - pub const fn from_static_message(msg: &'static SimpleMessage) -> Error { - Self { repr: Repr::new_simple_message(msg) } - } - /// Returns an error representing the last OS error which occurred. /// /// This function reads the value of `errno` for the target platform (e.g. @@ -647,13 +34,14 @@ impl Error { /// let os_error = Error::last_os_error(); /// println!("last OS error: {os_error:?}"); /// ``` + #[rustc_allow_incoherent_impl] #[stable(feature = "rust1", since = "1.0.0")] #[doc(alias = "GetLastError")] #[doc(alias = "errno")] #[must_use] #[inline] pub fn last_os_error() -> Error { - Error::from_raw_os_error(sys::io::errno()) + Error::from_raw_os_error(errno()) } /// Creates a new instance of an [`Error`] from a particular OS error code. @@ -681,405 +69,18 @@ impl Error { /// assert_eq!(error.kind(), io::ErrorKind::InvalidInput); /// # } /// ``` + #[rustc_allow_incoherent_impl] #[stable(feature = "rust1", since = "1.0.0")] #[must_use] #[inline] pub fn from_raw_os_error(code: RawOsError) -> Error { - Error { repr: Repr::new_os(code) } - } + const FUNCTIONS: &'static OsFunctions = &OsFunctions { + format_os_error: |code, fmt| fmt.write_str(&error_string(code)), + decode_error_kind, + is_interrupted, + }; - /// Returns the OS error that this error represents (if any). - /// - /// If this [`Error`] was constructed via [`last_os_error`] or - /// [`from_raw_os_error`], then this function will return [`Some`], otherwise - /// it will return [`None`]. - /// - /// [`last_os_error`]: Error::last_os_error - /// [`from_raw_os_error`]: Error::from_raw_os_error - /// - /// # Examples - /// - /// ``` - /// use std::io::{Error, ErrorKind}; - /// - /// fn print_os_error(err: &Error) { - /// if let Some(raw_os_err) = err.raw_os_error() { - /// println!("raw OS error: {raw_os_err:?}"); - /// } else { - /// println!("Not an OS error"); - /// } - /// } - /// - /// fn main() { - /// // Will print "raw OS error: ...". - /// print_os_error(&Error::last_os_error()); - /// // Will print "Not an OS error". - /// print_os_error(&Error::new(ErrorKind::Other, "oh no!")); - /// } - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - #[must_use] - #[inline] - pub fn raw_os_error(&self) -> Option { - match self.repr.data() { - ErrorData::Os(i) => Some(i), - ErrorData::Custom(..) => None, - ErrorData::Simple(..) => None, - ErrorData::SimpleMessage(..) => None, - } + // SAFETY: `FUNCTIONS` is a constant and not created at runtime. + unsafe { Error::from_raw_os_error_with_functions(code, FUNCTIONS) } } - - /// Returns a reference to the inner error wrapped by this error (if any). - /// - /// If this [`Error`] was constructed via [`new`] then this function will - /// return [`Some`], otherwise it will return [`None`]. - /// - /// [`new`]: Error::new - /// - /// # Examples - /// - /// ``` - /// use std::io::{Error, ErrorKind}; - /// - /// fn print_error(err: &Error) { - /// if let Some(inner_err) = err.get_ref() { - /// println!("Inner error: {inner_err:?}"); - /// } else { - /// println!("No inner error"); - /// } - /// } - /// - /// fn main() { - /// // Will print "No inner error". - /// print_error(&Error::last_os_error()); - /// // Will print "Inner error: ...". - /// print_error(&Error::new(ErrorKind::Other, "oh no!")); - /// } - /// ``` - #[stable(feature = "io_error_inner", since = "1.3.0")] - #[must_use] - #[inline] - pub fn get_ref(&self) -> Option<&(dyn error::Error + Send + Sync + 'static)> { - match self.repr.data() { - ErrorData::Os(..) => None, - ErrorData::Simple(..) => None, - ErrorData::SimpleMessage(..) => None, - ErrorData::Custom(c) => Some(&*c.error), - } - } - - /// Returns a mutable reference to the inner error wrapped by this error - /// (if any). - /// - /// If this [`Error`] was constructed via [`new`] then this function will - /// return [`Some`], otherwise it will return [`None`]. - /// - /// [`new`]: Error::new - /// - /// # Examples - /// - /// ``` - /// use std::io::{Error, ErrorKind}; - /// use std::{error, fmt}; - /// use std::fmt::Display; - /// - /// #[derive(Debug)] - /// struct MyError { - /// v: String, - /// } - /// - /// impl MyError { - /// fn new() -> MyError { - /// MyError { - /// v: "oh no!".to_string() - /// } - /// } - /// - /// fn change_message(&mut self, new_message: &str) { - /// self.v = new_message.to_string(); - /// } - /// } - /// - /// impl error::Error for MyError {} - /// - /// impl Display for MyError { - /// fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - /// write!(f, "MyError: {}", self.v) - /// } - /// } - /// - /// fn change_error(mut err: Error) -> Error { - /// if let Some(inner_err) = err.get_mut() { - /// inner_err.downcast_mut::().unwrap().change_message("I've been changed!"); - /// } - /// err - /// } - /// - /// fn print_error(err: &Error) { - /// if let Some(inner_err) = err.get_ref() { - /// println!("Inner error: {inner_err}"); - /// } else { - /// println!("No inner error"); - /// } - /// } - /// - /// fn main() { - /// // Will print "No inner error". - /// print_error(&change_error(Error::last_os_error())); - /// // Will print "Inner error: ...". - /// print_error(&change_error(Error::new(ErrorKind::Other, MyError::new()))); - /// } - /// ``` - #[stable(feature = "io_error_inner", since = "1.3.0")] - #[must_use] - #[inline] - pub fn get_mut(&mut self) -> Option<&mut (dyn error::Error + Send + Sync + 'static)> { - match self.repr.data_mut() { - ErrorData::Os(..) => None, - ErrorData::Simple(..) => None, - ErrorData::SimpleMessage(..) => None, - ErrorData::Custom(c) => Some(&mut *c.error), - } - } - - /// Consumes the `Error`, returning its inner error (if any). - /// - /// If this [`Error`] was constructed via [`new`] or [`other`], - /// then this function will return [`Some`], - /// otherwise it will return [`None`]. - /// - /// [`new`]: Error::new - /// [`other`]: Error::other - /// - /// # Examples - /// - /// ``` - /// use std::io::{Error, ErrorKind}; - /// - /// fn print_error(err: Error) { - /// if let Some(inner_err) = err.into_inner() { - /// println!("Inner error: {inner_err}"); - /// } else { - /// println!("No inner error"); - /// } - /// } - /// - /// fn main() { - /// // Will print "No inner error". - /// print_error(Error::last_os_error()); - /// // Will print "Inner error: ...". - /// print_error(Error::new(ErrorKind::Other, "oh no!")); - /// } - /// ``` - #[stable(feature = "io_error_inner", since = "1.3.0")] - #[must_use = "`self` will be dropped if the result is not used"] - #[inline] - pub fn into_inner(self) -> Option> { - match self.repr.into_data() { - ErrorData::Os(..) => None, - ErrorData::Simple(..) => None, - ErrorData::SimpleMessage(..) => None, - ErrorData::Custom(c) => Some(c.error), - } - } - - /// Attempts to downcast the custom boxed error to `E`. - /// - /// If this [`Error`] contains a custom boxed error, - /// then it would attempt downcasting on the boxed error, - /// otherwise it will return [`Err`]. - /// - /// If the custom boxed error has the same type as `E`, it will return [`Ok`], - /// otherwise it will also return [`Err`]. - /// - /// This method is meant to be a convenience routine for calling - /// `Box::downcast` on the custom boxed error, returned by - /// [`Error::into_inner`]. - /// - /// - /// # Examples - /// - /// ``` - /// use std::fmt; - /// use std::io; - /// use std::error::Error; - /// - /// #[derive(Debug)] - /// enum E { - /// Io(io::Error), - /// SomeOtherVariant, - /// } - /// - /// impl fmt::Display for E { - /// // ... - /// # fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - /// # todo!() - /// # } - /// } - /// impl Error for E {} - /// - /// impl From for E { - /// fn from(err: io::Error) -> E { - /// err.downcast::() - /// .unwrap_or_else(E::Io) - /// } - /// } - /// - /// impl From for io::Error { - /// fn from(err: E) -> io::Error { - /// match err { - /// E::Io(io_error) => io_error, - /// e => io::Error::new(io::ErrorKind::Other, e), - /// } - /// } - /// } - /// - /// # fn main() { - /// let e = E::SomeOtherVariant; - /// // Convert it to an io::Error - /// let io_error = io::Error::from(e); - /// // Cast it back to the original variant - /// let e = E::from(io_error); - /// assert!(matches!(e, E::SomeOtherVariant)); - /// - /// let io_error = io::Error::from(io::ErrorKind::AlreadyExists); - /// // Convert it to E - /// let e = E::from(io_error); - /// // Cast it back to the original variant - /// let io_error = io::Error::from(e); - /// assert_eq!(io_error.kind(), io::ErrorKind::AlreadyExists); - /// assert!(io_error.get_ref().is_none()); - /// assert!(io_error.raw_os_error().is_none()); - /// # } - /// ``` - #[stable(feature = "io_error_downcast", since = "1.79.0")] - pub fn downcast(self) -> result::Result - where - E: error::Error + Send + Sync + 'static, - { - if let ErrorData::Custom(c) = self.repr.data() - && c.error.is::() - { - if let ErrorData::Custom(b) = self.repr.into_data() - && let Ok(err) = b.error.downcast::() - { - Ok(*err) - } else { - // Safety: We have just checked that the condition is true - unsafe { crate::hint::unreachable_unchecked() } - } - } else { - Err(self) - } - } - - /// Returns the corresponding [`ErrorKind`] for this error. - /// - /// This may be a value set by Rust code constructing custom `io::Error`s, - /// or if this `io::Error` was sourced from the operating system, - /// it will be a value inferred from the system's error encoding. - /// See [`last_os_error`] for more details. - /// - /// [`last_os_error`]: Error::last_os_error - /// - /// # Examples - /// - /// ``` - /// use std::io::{Error, ErrorKind}; - /// - /// fn print_error(err: Error) { - /// println!("{:?}", err.kind()); - /// } - /// - /// fn main() { - /// // As no error has (visibly) occurred, this may print anything! - /// // It likely prints a placeholder for unidentified (non-)errors. - /// print_error(Error::last_os_error()); - /// // Will print "AddrInUse". - /// print_error(Error::new(ErrorKind::AddrInUse, "oh no!")); - /// } - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - #[must_use] - #[inline] - pub fn kind(&self) -> ErrorKind { - match self.repr.data() { - ErrorData::Os(code) => sys::io::decode_error_kind(code), - ErrorData::Custom(c) => c.kind, - ErrorData::Simple(kind) => kind, - ErrorData::SimpleMessage(m) => m.kind, - } - } - - #[inline] - pub(crate) fn is_interrupted(&self) -> bool { - match self.repr.data() { - ErrorData::Os(code) => sys::io::is_interrupted(code), - ErrorData::Custom(c) => c.kind == ErrorKind::Interrupted, - ErrorData::Simple(kind) => kind == ErrorKind::Interrupted, - ErrorData::SimpleMessage(m) => m.kind == ErrorKind::Interrupted, - } - } -} - -impl fmt::Debug for Repr { - fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { - match self.data() { - ErrorData::Os(code) => fmt - .debug_struct("Os") - .field("code", &code) - .field("kind", &sys::io::decode_error_kind(code)) - .field("message", &sys::io::error_string(code)) - .finish(), - ErrorData::Custom(c) => fmt::Debug::fmt(&c, fmt), - ErrorData::Simple(kind) => fmt.debug_tuple("Kind").field(&kind).finish(), - ErrorData::SimpleMessage(msg) => fmt - .debug_struct("Error") - .field("kind", &msg.kind) - .field("message", &msg.message) - .finish(), - } - } -} - -#[stable(feature = "rust1", since = "1.0.0")] -impl fmt::Display for Error { - fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { - match self.repr.data() { - ErrorData::Os(code) => { - let detail = sys::io::error_string(code); - write!(fmt, "{detail} (os error {code})") - } - ErrorData::Custom(ref c) => c.error.fmt(fmt), - ErrorData::Simple(kind) => write!(fmt, "{}", kind.as_str()), - ErrorData::SimpleMessage(msg) => msg.message.fmt(fmt), - } - } -} - -#[stable(feature = "rust1", since = "1.0.0")] -impl error::Error for Error { - #[allow(deprecated)] - fn cause(&self) -> Option<&dyn error::Error> { - match self.repr.data() { - ErrorData::Os(..) => None, - ErrorData::Simple(..) => None, - ErrorData::SimpleMessage(..) => None, - ErrorData::Custom(c) => c.error.cause(), - } - } - - fn source(&self) -> Option<&(dyn error::Error + 'static)> { - match self.repr.data() { - ErrorData::Os(..) => None, - ErrorData::Simple(..) => None, - ErrorData::SimpleMessage(..) => None, - ErrorData::Custom(c) => c.error.source(), - } - } -} - -fn _assert_error_is_sync_send() { - fn _is_sync_send() {} - _is_sync_send::(); } diff --git a/library/std/src/io/error/tests.rs b/library/std/src/io/error/tests.rs index a8eef06381dae..a3a2f5830ae91 100644 --- a/library/std/src/io/error/tests.rs +++ b/library/std/src/io/error/tests.rs @@ -1,4 +1,4 @@ -use super::{Custom, Error, ErrorData, ErrorKind, Repr, SimpleMessage, const_error}; +use crate::io::{Error, ErrorKind, const_error}; use crate::sys::io::{decode_error_kind, error_string}; use crate::{assert_matches, error, fmt}; @@ -12,12 +12,7 @@ fn test_debug_error() { let code = 6; let msg = error_string(code); let kind = decode_error_kind(code); - let err = Error { - repr: Repr::new_custom(Box::new(Custom { - kind: ErrorKind::InvalidInput, - error: Box::new(Error { repr: super::Repr::new_os(code) }), - })), - }; + let err = Error::new(ErrorKind::InvalidInput, Error::from_raw_os_error(code)); let expected = format!( "Custom {{ \ kind: InvalidInput, \ @@ -70,10 +65,6 @@ fn test_os_packing() { for code in -20..20 { let e = Error::from_raw_os_error(code); assert_eq!(e.raw_os_error(), Some(code)); - assert_matches!( - e.repr.data(), - ErrorData::Os(c) if c == code, - ); } } @@ -82,28 +73,17 @@ fn test_errorkind_packing() { assert_eq!(Error::from(ErrorKind::NotFound).kind(), ErrorKind::NotFound); assert_eq!(Error::from(ErrorKind::PermissionDenied).kind(), ErrorKind::PermissionDenied); assert_eq!(Error::from(ErrorKind::Uncategorized).kind(), ErrorKind::Uncategorized); - // Check that the innards look like what we want. - assert_matches!( - Error::from(ErrorKind::OutOfMemory).repr.data(), - ErrorData::Simple(ErrorKind::OutOfMemory), - ); } #[test] fn test_simple_message_packing() { - use super::ErrorKind::*; - use super::SimpleMessage; + use ErrorKind::*; macro_rules! check_simple_msg { ($err:expr, $kind:ident, $msg:literal) => {{ let e = &$err; // Check that the public api is right. assert_eq!(e.kind(), $kind); assert!(format!("{e:?}").contains($msg)); - // and we got what we expected - assert_matches!( - e.repr.data(), - ErrorData::SimpleMessage(SimpleMessage { kind: $kind, message: $msg }) - ); }}; } @@ -128,14 +108,11 @@ impl fmt::Display for Bojji { #[test] fn test_custom_error_packing() { - use super::Custom; let test = Error::new(ErrorKind::Uncategorized, Bojji(true)); + assert_eq!(test.kind(), ErrorKind::Uncategorized); assert_matches!( - test.repr.data(), - ErrorData::Custom(Custom { - kind: ErrorKind::Uncategorized, - error, - }) if error.downcast_ref::().as_deref() == Some(&Bojji(true)), + test.get_ref(), + Some(error) if error.downcast_ref::().as_deref() == Some(&Bojji(true)), ); } @@ -181,11 +158,11 @@ fn test_std_io_error_downcast() { assert_eq!(kind, io_error.kind()); // Case 5: simple message - const SIMPLE_MESSAGE: SimpleMessage = - SimpleMessage { kind: ErrorKind::Other, message: "simple message error test" }; - let io_error = Error::from_static_message(&SIMPLE_MESSAGE); + const KIND: ErrorKind = ErrorKind::Other; + const MESSAGE: &str = "simple message error test"; + let io_error = const_error!(KIND, MESSAGE); let io_error = io_error.downcast::().unwrap_err(); - assert_eq!(SIMPLE_MESSAGE.kind, io_error.kind()); - assert_eq!(SIMPLE_MESSAGE.message, format!("{io_error}")); + assert_eq!(KIND, io_error.kind()); + assert_eq!(MESSAGE, format!("{io_error}")); } diff --git a/library/std/src/io/mod.rs b/library/std/src/io/mod.rs index 623c34c6d2910..c0ed06d5311bc 100644 --- a/library/std/src/io/mod.rs +++ b/library/std/src/io/mod.rs @@ -294,3115 +294,54 @@ #![stable(feature = "rust1", since = "1.0.0")] -#[cfg(test)] -mod tests; - -#[unstable(feature = "read_buf", issue = "78485")] -pub use core::io::{BorrowedBuf, BorrowedCursor}; -use core::slice::memchr; - -#[stable(feature = "bufwriter_into_parts", since = "1.56.0")] -pub use self::buffered::WriterPanicked; +use alloc_crate::io::OsFunctions; #[unstable(feature = "raw_os_error_ty", issue = "107792")] -pub use self::error::RawOsError; +pub use alloc_crate::io::RawOsError; #[doc(hidden)] #[unstable(feature = "io_const_error_internals", issue = "none")] -pub use self::error::SimpleMessage; +pub use alloc_crate::io::SimpleMessage; +#[stable(feature = "bufwriter_into_parts", since = "1.56.0")] +pub use alloc_crate::io::WriterPanicked; #[unstable(feature = "io_const_error", issue = "133448")] -pub use self::error::const_error; +pub use alloc_crate::io::const_error; +#[stable(feature = "io_read_to_string", since = "1.65.0")] +pub use alloc_crate::io::read_to_string; +#[unstable(feature = "read_buf", issue = "78485")] +pub use alloc_crate::io::{BorrowedBuf, BorrowedCursor}; +#[stable(feature = "rust1", since = "1.0.0")] +pub use alloc_crate::io::{ + BufRead, BufReader, BufWriter, Bytes, Chain, Cursor, Empty, Error, ErrorKind, IntoInnerError, + LineWriter, Lines, Read, Repeat, Result, Seek, SeekFrom, Sink, Split, Take, Write, copy, empty, + repeat, sink, +}; +#[allow(unused_imports, reason = "only used by certain platforms")] +pub(crate) use alloc_crate::io::{ + CopyState, DEFAULT_BUF_SIZE, SpecCopy, default_read_buf, default_read_vectored, + default_write_vectored, +}; +pub(crate) use alloc_crate::io::{ + IoHandle, SpecReadByte, default_read_to_end, default_read_to_string, stream_len_default, +}; +#[stable(feature = "iovec", since = "1.36.0")] +pub use alloc_crate::io::{IoSlice, IoSliceMut}; + #[stable(feature = "anonymous_pipe", since = "1.87.0")] pub use self::pipe::{PipeReader, PipeWriter, pipe}; #[stable(feature = "is_terminal", since = "1.70.0")] pub use self::stdio::IsTerminal; -pub(crate) use self::stdio::attempt_print_to_stderr; #[unstable(feature = "print_internals", issue = "none")] #[doc(hidden)] pub use self::stdio::{_eprint, _print}; +#[stable(feature = "rust1", since = "1.0.0")] +pub use self::stdio::{ + Stderr, StderrLock, Stdin, StdinLock, Stdout, StdoutLock, stderr, stdin, stdout, +}; +pub(crate) use self::stdio::{attempt_print_to_stderr, cleanup}; #[unstable(feature = "internal_output_capture", issue = "none")] #[doc(no_inline, hidden)] pub use self::stdio::{set_output_capture, try_set_output_capture}; -#[stable(feature = "rust1", since = "1.0.0")] -pub use self::{ - buffered::{BufReader, BufWriter, IntoInnerError, LineWriter}, - copy::copy, - cursor::Cursor, - error::{Error, ErrorKind, Result}, - stdio::{Stderr, StderrLock, Stdin, StdinLock, Stdout, StdoutLock, stderr, stdin, stdout}, - util::{Empty, Repeat, Sink, empty, repeat, sink}, -}; -use crate::mem::{MaybeUninit, take}; -use crate::ops::{Deref, DerefMut}; -use crate::{cmp, fmt, slice, str, sys}; -mod buffered; -pub(crate) mod copy; -mod cursor; mod error; -mod impls; mod pipe; pub mod prelude; mod stdio; -mod util; - -const DEFAULT_BUF_SIZE: usize = crate::sys::io::DEFAULT_BUF_SIZE; - -pub(crate) use stdio::cleanup; - -struct Guard<'a> { - buf: &'a mut Vec, - len: usize, -} - -impl Drop for Guard<'_> { - fn drop(&mut self) { - unsafe { - self.buf.set_len(self.len); - } - } -} - -// Several `read_to_string` and `read_line` methods in the standard library will -// append data into a `String` buffer, but we need to be pretty careful when -// doing this. The implementation will just call `.as_mut_vec()` and then -// delegate to a byte-oriented reading method, but we must ensure that when -// returning we never leave `buf` in a state such that it contains invalid UTF-8 -// in its bounds. -// -// To this end, we use an RAII guard (to protect against panics) which updates -// the length of the string when it is dropped. This guard initially truncates -// the string to the prior length and only after we've validated that the -// new contents are valid UTF-8 do we allow it to set a longer length. -// -// The unsafety in this function is twofold: -// -// 1. We're looking at the raw bytes of `buf`, so we take on the burden of UTF-8 -// checks. -// 2. We're passing a raw buffer to the function `f`, and it is expected that -// the function only *appends* bytes to the buffer. We'll get undefined -// behavior if existing bytes are overwritten to have non-UTF-8 data. -pub(crate) unsafe fn append_to_string(buf: &mut String, f: F) -> Result -where - F: FnOnce(&mut Vec) -> Result, -{ - let mut g = Guard { len: buf.len(), buf: unsafe { buf.as_mut_vec() } }; - let ret = f(g.buf); - - // SAFETY: the caller promises to only append data to `buf` - let appended = unsafe { g.buf.get_unchecked(g.len..) }; - if str::from_utf8(appended).is_err() { - ret.and_then(|_| Err(Error::INVALID_UTF8)) - } else { - g.len = g.buf.len(); - ret - } -} - -// Here we must serve many masters with conflicting goals: -// -// - avoid allocating unless necessary -// - avoid overallocating if we know the exact size (#89165) -// - avoid passing large buffers to readers that always initialize the free capacity if they perform short reads (#23815, #23820) -// - pass large buffers to readers that do not initialize the spare capacity. this can amortize per-call overheads -// - and finally pass not-too-small and not-too-large buffers to Windows read APIs because they manage to suffer from both problems -// at the same time, i.e. small reads suffer from syscall overhead, all reads incur costs proportional to buffer size (#110650) -// -pub(crate) fn default_read_to_end( - r: &mut R, - buf: &mut Vec, - size_hint: Option, -) -> Result { - let start_len = buf.len(); - let start_cap = buf.capacity(); - // Optionally limit the maximum bytes read on each iteration. - // This adds an arbitrary fiddle factor to allow for more data than we expect. - let mut max_read_size = size_hint - .and_then(|s| s.checked_add(1024)?.checked_next_multiple_of(DEFAULT_BUF_SIZE)) - .unwrap_or(DEFAULT_BUF_SIZE); - - let mut initialized = 0; // Extra initialized bytes from previous loop iteration - - const PROBE_SIZE: usize = 32; - - fn small_probe_read(r: &mut R, buf: &mut Vec) -> Result { - let mut probe = [0u8; PROBE_SIZE]; - - loop { - match r.read(&mut probe) { - Ok(n) => { - // there is no way to recover from allocation failure here - // because the data has already been read. - buf.extend_from_slice(&probe[..n]); - return Ok(n); - } - Err(ref e) if e.is_interrupted() => continue, - Err(e) => return Err(e), - } - } - } - - // avoid inflating empty/small vecs before we have determined that there's anything to read - if (size_hint.is_none() || size_hint == Some(0)) && buf.capacity() - buf.len() < PROBE_SIZE { - let read = small_probe_read(r, buf)?; - - if read == 0 { - return Ok(0); - } - } - - let mut consecutive_short_reads = 0; - - loop { - if buf.len() == buf.capacity() && buf.capacity() == start_cap { - // The buffer might be an exact fit. Let's read into a probe buffer - // and see if it returns `Ok(0)`. If so, we've avoided an - // unnecessary doubling of the capacity. But if not, append the - // probe buffer to the primary buffer and let its capacity grow. - let read = small_probe_read(r, buf)?; - - if read == 0 { - return Ok(buf.len() - start_len); - } - } - - if buf.len() == buf.capacity() { - // buf is full, need more space - buf.try_reserve(PROBE_SIZE)?; - } - - let mut spare = buf.spare_capacity_mut(); - let buf_len = cmp::min(spare.len(), max_read_size); - spare = &mut spare[..buf_len]; - let mut read_buf: BorrowedBuf<'_> = spare.into(); - - // SAFETY: These bytes were initialized but not filled in the previous loop - unsafe { - read_buf.set_init(initialized); - } - - let mut cursor = read_buf.unfilled(); - let result = loop { - match r.read_buf(cursor.reborrow()) { - Err(e) if e.is_interrupted() => continue, - // Do not stop now in case of error: we might have received both data - // and an error - res => break res, - } - }; - - let unfilled_but_initialized = cursor.init_mut().len(); - let bytes_read = cursor.written(); - let was_fully_initialized = read_buf.init_len() == buf_len; - - // SAFETY: BorrowedBuf's invariants mean this much memory is initialized. - unsafe { - let new_len = bytes_read + buf.len(); - buf.set_len(new_len); - } - - // Now that all data is pushed to the vector, we can fail without data loss - result?; - - if bytes_read == 0 { - return Ok(buf.len() - start_len); - } - - if bytes_read < buf_len { - consecutive_short_reads += 1; - } else { - consecutive_short_reads = 0; - } - - // store how much was initialized but not filled - initialized = unfilled_but_initialized; - - // Use heuristics to determine the max read size if no initial size hint was provided - if size_hint.is_none() { - // The reader is returning short reads but it doesn't call ensure_init(). - // In that case we no longer need to restrict read sizes to avoid - // initialization costs. - // When reading from disk we usually don't get any short reads except at EOF. - // So we wait for at least 2 short reads before uncapping the read buffer; - // this helps with the Windows issue. - if !was_fully_initialized && consecutive_short_reads > 1 { - max_read_size = usize::MAX; - } - - // we have passed a larger buffer than previously and the - // reader still hasn't returned a short read - if buf_len >= max_read_size && bytes_read == buf_len { - max_read_size = max_read_size.saturating_mul(2); - } - } - } -} - -pub(crate) fn default_read_to_string( - r: &mut R, - buf: &mut String, - size_hint: Option, -) -> Result { - // Note that we do *not* call `r.read_to_end()` here. We are passing - // `&mut Vec` (the raw contents of `buf`) into the `read_to_end` - // method to fill it up. An arbitrary implementation could overwrite the - // entire contents of the vector, not just append to it (which is what - // we are expecting). - // - // To prevent extraneously checking the UTF-8-ness of the entire buffer - // we pass it to our hardcoded `default_read_to_end` implementation which - // we know is guaranteed to only read data into the end of the buffer. - unsafe { append_to_string(buf, |b| default_read_to_end(r, b, size_hint)) } -} - -pub(crate) fn default_read_vectored(read: F, bufs: &mut [IoSliceMut<'_>]) -> Result -where - F: FnOnce(&mut [u8]) -> Result, -{ - let buf = bufs.iter_mut().find(|b| !b.is_empty()).map_or(&mut [][..], |b| &mut **b); - read(buf) -} - -pub(crate) fn default_write_vectored(write: F, bufs: &[IoSlice<'_>]) -> Result -where - F: FnOnce(&[u8]) -> Result, -{ - let buf = bufs.iter().find(|b| !b.is_empty()).map_or(&[][..], |b| &**b); - write(buf) -} - -pub(crate) fn default_read_exact(this: &mut R, mut buf: &mut [u8]) -> Result<()> { - while !buf.is_empty() { - match this.read(buf) { - Ok(0) => break, - Ok(n) => { - buf = &mut buf[n..]; - } - Err(ref e) if e.is_interrupted() => {} - Err(e) => return Err(e), - } - } - if !buf.is_empty() { Err(Error::READ_EXACT_EOF) } else { Ok(()) } -} - -pub(crate) fn default_read_buf(read: F, mut cursor: BorrowedCursor<'_>) -> Result<()> -where - F: FnOnce(&mut [u8]) -> Result, -{ - let n = read(cursor.ensure_init().init_mut())?; - cursor.advance(n); - Ok(()) -} - -pub(crate) fn default_read_buf_exact( - this: &mut R, - mut cursor: BorrowedCursor<'_>, -) -> Result<()> { - while cursor.capacity() > 0 { - let prev_written = cursor.written(); - match this.read_buf(cursor.reborrow()) { - Ok(()) => {} - Err(e) if e.is_interrupted() => continue, - Err(e) => return Err(e), - } - - if cursor.written() == prev_written { - return Err(Error::READ_EXACT_EOF); - } - } - - Ok(()) -} - -pub(crate) fn default_write_fmt( - this: &mut W, - args: fmt::Arguments<'_>, -) -> Result<()> { - // Create a shim which translates a `Write` to a `fmt::Write` and saves off - // I/O errors, instead of discarding them. - struct Adapter<'a, T: ?Sized + 'a> { - inner: &'a mut T, - error: Result<()>, - } - - impl fmt::Write for Adapter<'_, T> { - fn write_str(&mut self, s: &str) -> fmt::Result { - match self.inner.write_all(s.as_bytes()) { - Ok(()) => Ok(()), - Err(e) => { - self.error = Err(e); - Err(fmt::Error) - } - } - } - } - - let mut output = Adapter { inner: this, error: Ok(()) }; - match fmt::write(&mut output, args) { - Ok(()) => Ok(()), - Err(..) => { - // Check whether the error came from the underlying `Write`. - if output.error.is_err() { - output.error - } else { - // This shouldn't happen: the underlying stream did not error, - // but somehow the formatter still errored? - panic!( - "a formatting trait implementation returned an error when the underlying stream did not" - ); - } - } - } -} - -/// The `Read` trait allows for reading bytes from a source. -/// -/// Implementors of the `Read` trait are called 'readers'. -/// -/// Readers are defined by one required method, [`read()`]. Each call to [`read()`] -/// will attempt to pull bytes from this source into a provided buffer. A -/// number of other methods are implemented in terms of [`read()`], giving -/// implementors a number of ways to read bytes while only needing to implement -/// a single method. -/// -/// Readers are intended to be composable with one another. Many implementors -/// throughout [`std::io`] take and provide types which implement the `Read` -/// trait. -/// -/// Please note that each call to [`read()`] may involve a system call, and -/// therefore, using something that implements [`BufRead`], such as -/// [`BufReader`], will be more efficient. -/// -/// Repeated calls to the reader use the same cursor, so for example -/// calling `read_to_end` twice on a [`File`] will only return the file's -/// contents once. It's recommended to first call `rewind()` in that case. -/// -/// # Examples -/// -/// [`File`]s implement `Read`: -/// -/// ```no_run -/// use std::io; -/// use std::io::prelude::*; -/// use std::fs::File; -/// -/// fn main() -> io::Result<()> { -/// let mut f = File::open("foo.txt")?; -/// let mut buffer = [0; 10]; -/// -/// // read up to 10 bytes -/// f.read(&mut buffer)?; -/// -/// let mut buffer = Vec::new(); -/// // read the whole file -/// f.read_to_end(&mut buffer)?; -/// -/// // read into a String, so that you don't need to do the conversion. -/// let mut buffer = String::new(); -/// f.read_to_string(&mut buffer)?; -/// -/// // and more! See the other methods for more details. -/// Ok(()) -/// } -/// ``` -/// -/// Read from [`&str`] because [`&[u8]`][prim@slice] implements `Read`: -/// -/// ```no_run -/// # use std::io; -/// use std::io::prelude::*; -/// -/// fn main() -> io::Result<()> { -/// let mut b = "This string will be read".as_bytes(); -/// let mut buffer = [0; 10]; -/// -/// // read up to 10 bytes -/// b.read(&mut buffer)?; -/// -/// // etc... it works exactly as a File does! -/// Ok(()) -/// } -/// ``` -/// -/// [`read()`]: Read::read -/// [`&str`]: prim@str -/// [`std::io`]: self -/// [`File`]: crate::fs::File -#[stable(feature = "rust1", since = "1.0.0")] -#[doc(notable_trait)] -#[cfg_attr(not(test), rustc_diagnostic_item = "IoRead")] -pub trait Read { - /// Pull some bytes from this source into the specified buffer, returning - /// how many bytes were read. - /// - /// This function does not provide any guarantees about whether it blocks - /// waiting for data, but if an object needs to block for a read and cannot, - /// it will typically signal this via an [`Err`] return value. - /// - /// If the return value of this method is [`Ok(n)`], then implementations must - /// guarantee that `0 <= n <= buf.len()`. A nonzero `n` value indicates - /// that the buffer `buf` has been filled in with `n` bytes of data from this - /// source. If `n` is `0`, then it can indicate one of two scenarios: - /// - /// 1. This reader has reached its "end of file" and will likely no longer - /// be able to produce bytes. Note that this does not mean that the - /// reader will *always* no longer be able to produce bytes. As an example, - /// on Linux, this method will call the `recv` syscall for a [`TcpStream`], - /// where returning zero indicates the connection was shut down correctly. While - /// for [`File`], it is possible to reach the end of file and get zero as result, - /// but if more data is appended to the file, future calls to `read` will return - /// more data. - /// 2. The buffer specified was 0 bytes in length. - /// - /// It is not an error if the returned value `n` is smaller than the buffer size, - /// even when the reader is not at the end of the stream yet. - /// This may happen for example because fewer bytes are actually available right now - /// (e. g. being close to end-of-file) or because read() was interrupted by a signal. - /// - /// As this trait is safe to implement, callers in unsafe code cannot rely on - /// `n <= buf.len()` for safety. - /// Extra care needs to be taken when `unsafe` functions are used to access the read bytes. - /// Callers have to ensure that no unchecked out-of-bounds accesses are possible even if - /// `n > buf.len()`. - /// - /// *Implementations* of this method can make no assumptions about the contents of `buf` when - /// this function is called. It is recommended that implementations only write data to `buf` - /// instead of reading its contents. - /// - /// Correspondingly, however, *callers* of this method in unsafe code must not assume - /// any guarantees about how the implementation uses `buf`. The trait is safe to implement, - /// so it is possible that the code that's supposed to write to the buffer might also read - /// from it. It is your responsibility to make sure that `buf` is initialized - /// before calling `read`. Calling `read` with an uninitialized `buf` (of the kind one - /// obtains via [`MaybeUninit`]) is not safe, and can lead to undefined behavior. - /// - /// [`MaybeUninit`]: crate::mem::MaybeUninit - /// - /// # Errors - /// - /// If this function encounters any form of I/O or other error, an error - /// variant will be returned. If an error is returned then it must be - /// guaranteed that no bytes were read. - /// - /// An error of the [`ErrorKind::Interrupted`] kind is non-fatal and the read - /// operation should be retried if there is nothing else to do. - /// - /// # Examples - /// - /// [`File`]s implement `Read`: - /// - /// [`Ok(n)`]: Ok - /// [`File`]: crate::fs::File - /// [`TcpStream`]: crate::net::TcpStream - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let mut f = File::open("foo.txt")?; - /// let mut buffer = [0; 10]; - /// - /// // read up to 10 bytes - /// let n = f.read(&mut buffer[..])?; - /// - /// println!("The bytes: {:?}", &buffer[..n]); - /// Ok(()) - /// } - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - fn read(&mut self, buf: &mut [u8]) -> Result; - - /// Like `read`, except that it reads into a slice of buffers. - /// - /// Data is copied to fill each buffer in order, with the final buffer - /// written to possibly being only partially filled. This method must - /// behave equivalently to a single call to `read` with concatenated - /// buffers. - /// - /// The default implementation calls `read` with either the first nonempty - /// buffer provided, or an empty one if none exists. - #[stable(feature = "iovec", since = "1.36.0")] - fn read_vectored(&mut self, bufs: &mut [IoSliceMut<'_>]) -> Result { - default_read_vectored(|b| self.read(b), bufs) - } - - /// Determines if this `Read`er has an efficient `read_vectored` - /// implementation. - /// - /// If a `Read`er does not override the default `read_vectored` - /// implementation, code using it may want to avoid the method all together - /// and coalesce writes into a single buffer for higher performance. - /// - /// The default implementation returns `false`. - #[unstable(feature = "can_vector", issue = "69941")] - fn is_read_vectored(&self) -> bool { - false - } - - /// Reads all bytes until EOF in this source, placing them into `buf`. - /// - /// All bytes read from this source will be appended to the specified buffer - /// `buf`. This function will continuously call [`read()`] to append more data to - /// `buf` until [`read()`] returns either [`Ok(0)`] or an error of - /// non-[`ErrorKind::Interrupted`] kind. - /// - /// If successful, this function will return the total number of bytes read. - /// - /// # Errors - /// - /// If this function encounters an error of the kind - /// [`ErrorKind::Interrupted`] then the error is ignored and the operation - /// will continue. - /// - /// If any other read error is encountered then this function immediately - /// returns. Any bytes which have already been read will be appended to - /// `buf`. - /// - /// # Examples - /// - /// [`File`]s implement `Read`: - /// - /// [`read()`]: Read::read - /// [`Ok(0)`]: Ok - /// [`File`]: crate::fs::File - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let mut f = File::open("foo.txt")?; - /// let mut buffer = Vec::new(); - /// - /// // read the whole file - /// f.read_to_end(&mut buffer)?; - /// Ok(()) - /// } - /// ``` - /// - /// (See also the [`std::fs::read`] convenience function for reading from a - /// file.) - /// - /// [`std::fs::read`]: crate::fs::read - /// - /// ## Implementing `read_to_end` - /// - /// When implementing the `io::Read` trait, it is recommended to allocate - /// memory using [`Vec::try_reserve`]. However, this behavior is not guaranteed - /// by all implementations, and `read_to_end` may not handle out-of-memory - /// situations gracefully. - /// - /// ```no_run - /// # use std::io::{self, BufRead}; - /// # struct Example { example_datasource: io::Empty } impl Example { - /// # fn get_some_data_for_the_example(&self) -> &'static [u8] { &[] } - /// fn read_to_end(&mut self, dest_vec: &mut Vec) -> io::Result { - /// let initial_vec_len = dest_vec.len(); - /// loop { - /// let src_buf = self.example_datasource.fill_buf()?; - /// if src_buf.is_empty() { - /// break; - /// } - /// dest_vec.try_reserve(src_buf.len())?; - /// dest_vec.extend_from_slice(src_buf); - /// - /// // Any irreversible side effects should happen after `try_reserve` succeeds, - /// // to avoid losing data on allocation error. - /// let read = src_buf.len(); - /// self.example_datasource.consume(read); - /// } - /// Ok(dest_vec.len() - initial_vec_len) - /// } - /// # } - /// ``` - /// - /// # Usage Notes - /// - /// `read_to_end` attempts to read a source until EOF, but many sources are continuous streams - /// that do not send EOF. In these cases, `read_to_end` will block indefinitely. Standard input - /// is one such stream which may be finite if piped, but is typically continuous. For example, - /// `cat file | my-rust-program` will correctly terminate with an `EOF` upon closure of cat. - /// Reading user input or running programs that remain open indefinitely will never terminate - /// the stream with `EOF` (e.g. `yes | my-rust-program`). - /// - /// Using `.lines()` with a [`BufReader`] or using [`read`] can provide a better solution - /// - ///[`read`]: Read::read - /// - /// [`Vec::try_reserve`]: crate::vec::Vec::try_reserve - #[stable(feature = "rust1", since = "1.0.0")] - fn read_to_end(&mut self, buf: &mut Vec) -> Result { - default_read_to_end(self, buf, None) - } - - /// Reads all bytes until EOF in this source, appending them to `buf`. - /// - /// If successful, this function returns the number of bytes which were read - /// and appended to `buf`. - /// - /// # Errors - /// - /// If the data in this stream is *not* valid UTF-8 then an error is - /// returned and `buf` is unchanged. - /// - /// See [`read_to_end`] for other error semantics. - /// - /// [`read_to_end`]: Read::read_to_end - /// - /// # Examples - /// - /// [`File`]s implement `Read`: - /// - /// [`File`]: crate::fs::File - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let mut f = File::open("foo.txt")?; - /// let mut buffer = String::new(); - /// - /// f.read_to_string(&mut buffer)?; - /// Ok(()) - /// } - /// ``` - /// - /// (See also the [`std::fs::read_to_string`] convenience function for - /// reading from a file.) - /// - /// # Usage Notes - /// - /// `read_to_string` attempts to read a source until EOF, but many sources are continuous streams - /// that do not send EOF. In these cases, `read_to_string` will block indefinitely. Standard input - /// is one such stream which may be finite if piped, but is typically continuous. For example, - /// `cat file | my-rust-program` will correctly terminate with an `EOF` upon closure of cat. - /// Reading user input or running programs that remain open indefinitely will never terminate - /// the stream with `EOF` (e.g. `yes | my-rust-program`). - /// - /// Using `.lines()` with a [`BufReader`] or using [`read`] can provide a better solution - /// - ///[`read`]: Read::read - /// - /// [`std::fs::read_to_string`]: crate::fs::read_to_string - #[stable(feature = "rust1", since = "1.0.0")] - fn read_to_string(&mut self, buf: &mut String) -> Result { - default_read_to_string(self, buf, None) - } - - /// Reads the exact number of bytes required to fill `buf`. - /// - /// This function reads as many bytes as necessary to completely fill the - /// specified buffer `buf`. - /// - /// *Implementations* of this method can make no assumptions about the contents of `buf` when - /// this function is called. It is recommended that implementations only write data to `buf` - /// instead of reading its contents. The documentation on [`read`] has a more detailed - /// explanation of this subject. - /// - /// # Errors - /// - /// If this function encounters an error of the kind - /// [`ErrorKind::Interrupted`] then the error is ignored and the operation - /// will continue. - /// - /// If this function encounters an "end of file" before completely filling - /// the buffer, it returns an error of the kind [`ErrorKind::UnexpectedEof`]. - /// The contents of `buf` are unspecified in this case. - /// - /// If any other read error is encountered then this function immediately - /// returns. The contents of `buf` are unspecified in this case. - /// - /// If this function returns an error, it is unspecified how many bytes it - /// has read, but it will never read more than would be necessary to - /// completely fill the buffer. - /// - /// # Examples - /// - /// [`File`]s implement `Read`: - /// - /// [`read`]: Read::read - /// [`File`]: crate::fs::File - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let mut f = File::open("foo.txt")?; - /// let mut buffer = [0; 10]; - /// - /// // read exactly 10 bytes - /// f.read_exact(&mut buffer)?; - /// Ok(()) - /// } - /// ``` - #[stable(feature = "read_exact", since = "1.6.0")] - fn read_exact(&mut self, buf: &mut [u8]) -> Result<()> { - default_read_exact(self, buf) - } - - /// Pull some bytes from this source into the specified buffer. - /// - /// This is equivalent to the [`read`](Read::read) method, except that it is passed a [`BorrowedCursor`] rather than `[u8]` to allow use - /// with uninitialized buffers. The new data will be appended to any existing contents of `buf`. - /// - /// The default implementation delegates to `read`. - /// - /// This method makes it possible to return both data and an error but it is advised against. - #[unstable(feature = "read_buf", issue = "78485")] - fn read_buf(&mut self, buf: BorrowedCursor<'_>) -> Result<()> { - default_read_buf(|b| self.read(b), buf) - } - - /// Reads the exact number of bytes required to fill `cursor`. - /// - /// This is similar to the [`read_exact`](Read::read_exact) method, except - /// that it is passed a [`BorrowedCursor`] rather than `[u8]` to allow use - /// with uninitialized buffers. - /// - /// # Errors - /// - /// If this function encounters an error of the kind [`ErrorKind::Interrupted`] - /// then the error is ignored and the operation will continue. - /// - /// If this function encounters an "end of file" before completely filling - /// the buffer, it returns an error of the kind [`ErrorKind::UnexpectedEof`]. - /// - /// If any other read error is encountered then this function immediately - /// returns. - /// - /// If this function returns an error, all bytes read will be appended to `cursor`. - #[unstable(feature = "read_buf", issue = "78485")] - fn read_buf_exact(&mut self, cursor: BorrowedCursor<'_>) -> Result<()> { - default_read_buf_exact(self, cursor) - } - - /// Creates a "by reference" adapter for this instance of `Read`. - /// - /// The returned adapter also implements `Read` and will simply borrow this - /// current reader. - /// - /// # Examples - /// - /// [`File`]s implement `Read`: - /// - /// [`File`]: crate::fs::File - /// - /// ```no_run - /// use std::io; - /// use std::io::Read; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let mut f = File::open("foo.txt")?; - /// let mut buffer = Vec::new(); - /// let mut other_buffer = Vec::new(); - /// - /// { - /// let reference = f.by_ref(); - /// - /// // read at most 5 bytes - /// reference.take(5).read_to_end(&mut buffer)?; - /// - /// } // drop our &mut reference so we can use f again - /// - /// // original file still usable, read the rest - /// f.read_to_end(&mut other_buffer)?; - /// Ok(()) - /// } - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - fn by_ref(&mut self) -> &mut Self - where - Self: Sized, - { - self - } - - /// Transforms this `Read` instance to an [`Iterator`] over its bytes. - /// - /// The returned type implements [`Iterator`] where the [`Item`] is - /// [Result]<[u8], [io::Error]>. - /// The yielded item is [`Ok`] if a byte was successfully read and [`Err`] - /// otherwise. EOF is mapped to returning [`None`] from this iterator. - /// - /// The default implementation calls `read` for each byte, - /// which can be very inefficient for data that's not in memory, - /// such as [`File`]. Consider using a [`BufReader`] in such cases. - /// - /// # Examples - /// - /// [`File`]s implement `Read`: - /// - /// [`Item`]: Iterator::Item - /// [`File`]: crate::fs::File "fs::File" - /// [Result]: crate::result::Result "Result" - /// [io::Error]: self::Error "io::Error" - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// use std::io::BufReader; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let f = BufReader::new(File::open("foo.txt")?); - /// - /// for byte in f.bytes() { - /// println!("{}", byte?); - /// } - /// Ok(()) - /// } - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - fn bytes(self) -> Bytes - where - Self: Sized, - { - Bytes { inner: self } - } - - /// Creates an adapter which will chain this stream with another. - /// - /// The returned `Read` instance will first read all bytes from this object - /// until EOF is encountered. Afterwards the output is equivalent to the - /// output of `next`. - /// - /// # Examples - /// - /// [`File`]s implement `Read`: - /// - /// [`File`]: crate::fs::File - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let f1 = File::open("foo.txt")?; - /// let f2 = File::open("bar.txt")?; - /// - /// let mut handle = f1.chain(f2); - /// let mut buffer = String::new(); - /// - /// // read the value into a String. We could use any Read method here, - /// // this is just one example. - /// handle.read_to_string(&mut buffer)?; - /// Ok(()) - /// } - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - fn chain(self, next: R) -> Chain - where - Self: Sized, - { - Chain { first: self, second: next, done_first: false } - } - - /// Creates an adapter which will read at most `limit` bytes from it. - /// - /// This function returns a new instance of `Read` which will read at most - /// `limit` bytes, after which it will always return EOF ([`Ok(0)`]). Any - /// read errors will not count towards the number of bytes read and future - /// calls to [`read()`] may succeed. - /// - /// # Examples - /// - /// [`File`]s implement `Read`: - /// - /// [`File`]: crate::fs::File - /// [`Ok(0)`]: Ok - /// [`read()`]: Read::read - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let f = File::open("foo.txt")?; - /// let mut buffer = [0; 5]; - /// - /// // read at most five bytes - /// let mut handle = f.take(5); - /// - /// handle.read(&mut buffer)?; - /// Ok(()) - /// } - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - fn take(self, limit: u64) -> Take - where - Self: Sized, - { - Take { inner: self, len: limit, limit } - } - - /// Read and return a fixed array of bytes from this source. - /// - /// This function uses an array sized based on a const generic size known at compile time. You - /// can specify the size with turbofish (`reader.read_array::<8>()`), or let type inference - /// determine the number of bytes needed based on how the return value gets used. For instance, - /// this function works well with functions like [`u64::from_le_bytes`] to turn an array of - /// bytes into an integer of the same size. - /// - /// Like `read_exact`, if this function encounters an "end of file" before reading the desired - /// number of bytes, it returns an error of the kind [`ErrorKind::UnexpectedEof`]. - /// - /// ``` - /// #![feature(read_array)] - /// use std::io::Cursor; - /// use std::io::prelude::*; - /// - /// fn main() -> std::io::Result<()> { - /// let mut buf = Cursor::new([1, 2, 3, 4, 5, 6, 7, 8, 9, 8, 7, 6, 5, 4, 3, 2]); - /// let x = u64::from_le_bytes(buf.read_array()?); - /// let y = u32::from_be_bytes(buf.read_array()?); - /// let z = u16::from_be_bytes(buf.read_array()?); - /// assert_eq!(x, 0x807060504030201); - /// assert_eq!(y, 0x9080706); - /// assert_eq!(z, 0x504); - /// Ok(()) - /// } - /// ``` - #[unstable(feature = "read_array", issue = "148848")] - fn read_array(&mut self) -> Result<[u8; N]> - where - Self: Sized, - { - let mut buf = [MaybeUninit::uninit(); N]; - let mut borrowed_buf = BorrowedBuf::from(buf.as_mut_slice()); - self.read_buf_exact(borrowed_buf.unfilled())?; - // Guard against incorrect `read_buf_exact` implementations. - assert_eq!(borrowed_buf.len(), N); - Ok(unsafe { MaybeUninit::array_assume_init(buf) }) - } -} - -/// Reads all bytes from a [reader][Read] into a new [`String`]. -/// -/// This is a convenience function for [`Read::read_to_string`]. Using this -/// function avoids having to create a variable first and provides more type -/// safety since you can only get the buffer out if there were no errors. (If you -/// use [`Read::read_to_string`] you have to remember to check whether the read -/// succeeded because otherwise your buffer will be empty or only partially full.) -/// -/// # Performance -/// -/// The downside of this function's increased ease of use and type safety is -/// that it gives you less control over performance. For example, you can't -/// pre-allocate memory like you can using [`String::with_capacity`] and -/// [`Read::read_to_string`]. Also, you can't re-use the buffer if an error -/// occurs while reading. -/// -/// In many cases, this function's performance will be adequate and the ease of use -/// and type safety tradeoffs will be worth it. However, there are cases where you -/// need more control over performance, and in those cases you should definitely use -/// [`Read::read_to_string`] directly. -/// -/// Note that in some special cases, such as when reading files, this function will -/// pre-allocate memory based on the size of the input it is reading. In those -/// cases, the performance should be as good as if you had used -/// [`Read::read_to_string`] with a manually pre-allocated buffer. -/// -/// # Errors -/// -/// This function forces you to handle errors because the output (the `String`) -/// is wrapped in a [`Result`]. See [`Read::read_to_string`] for the errors -/// that can occur. If any error occurs, you will get an [`Err`], so you -/// don't have to worry about your buffer being empty or partially full. -/// -/// # Examples -/// -/// ```no_run -/// # use std::io; -/// fn main() -> io::Result<()> { -/// let stdin = io::read_to_string(io::stdin())?; -/// println!("Stdin was:"); -/// println!("{stdin}"); -/// Ok(()) -/// } -/// ``` -/// -/// # Usage Notes -/// -/// `read_to_string` attempts to read a source until EOF, but many sources are continuous streams -/// that do not send EOF. In these cases, `read_to_string` will block indefinitely. Standard input -/// is one such stream which may be finite if piped, but is typically continuous. For example, -/// `cat file | my-rust-program` will correctly terminate with an `EOF` upon closure of cat. -/// Reading user input or running programs that remain open indefinitely will never terminate -/// the stream with `EOF` (e.g. `yes | my-rust-program`). -/// -/// Using `.lines()` with a [`BufReader`] or using [`read`] can provide a better solution -/// -///[`read`]: Read::read -/// -#[stable(feature = "io_read_to_string", since = "1.65.0")] -pub fn read_to_string(mut reader: R) -> Result { - let mut buf = String::new(); - reader.read_to_string(&mut buf)?; - Ok(buf) -} - -/// A buffer type used with `Read::read_vectored`. -/// -/// It is semantically a wrapper around a `&mut [u8]`, but is guaranteed to be -/// ABI compatible with the `iovec` type on Unix platforms and `WSABUF` on -/// Windows. -#[stable(feature = "iovec", since = "1.36.0")] -#[repr(transparent)] -pub struct IoSliceMut<'a>(sys::io::IoSliceMut<'a>); - -#[stable(feature = "iovec_send_sync", since = "1.44.0")] -unsafe impl<'a> Send for IoSliceMut<'a> {} - -#[stable(feature = "iovec_send_sync", since = "1.44.0")] -unsafe impl<'a> Sync for IoSliceMut<'a> {} - -#[stable(feature = "iovec", since = "1.36.0")] -impl<'a> fmt::Debug for IoSliceMut<'a> { - fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { - fmt::Debug::fmt(self.0.as_slice(), fmt) - } -} - -impl<'a> IoSliceMut<'a> { - /// Creates a new `IoSliceMut` wrapping a byte slice. - /// - /// # Panics - /// - /// Panics on Windows if the slice is larger than 4GB. - #[stable(feature = "iovec", since = "1.36.0")] - #[inline] - pub fn new(buf: &'a mut [u8]) -> IoSliceMut<'a> { - IoSliceMut(sys::io::IoSliceMut::new(buf)) - } - - /// Advance the internal cursor of the slice. - /// - /// Also see [`IoSliceMut::advance_slices`] to advance the cursors of - /// multiple buffers. - /// - /// # Panics - /// - /// Panics when trying to advance beyond the end of the slice. - /// - /// # Examples - /// - /// ``` - /// use std::io::IoSliceMut; - /// use std::ops::Deref; - /// - /// let mut data = [1; 8]; - /// let mut buf = IoSliceMut::new(&mut data); - /// - /// // Mark 3 bytes as read. - /// buf.advance(3); - /// assert_eq!(buf.deref(), [1; 5].as_ref()); - /// ``` - #[stable(feature = "io_slice_advance", since = "1.81.0")] - #[inline] - pub fn advance(&mut self, n: usize) { - self.0.advance(n) - } - - /// Advance a slice of slices. - /// - /// Shrinks the slice to remove any `IoSliceMut`s that are fully advanced over. - /// If the cursor ends up in the middle of an `IoSliceMut`, it is modified - /// to start at that cursor. - /// - /// For example, if we have a slice of two 8-byte `IoSliceMut`s, and we advance by 10 bytes, - /// the result will only include the second `IoSliceMut`, advanced by 2 bytes. - /// - /// # Panics - /// - /// Panics when trying to advance beyond the end of the slices. - /// - /// # Examples - /// - /// ``` - /// use std::io::IoSliceMut; - /// use std::ops::Deref; - /// - /// let mut buf1 = [1; 8]; - /// let mut buf2 = [2; 16]; - /// let mut buf3 = [3; 8]; - /// let mut bufs = &mut [ - /// IoSliceMut::new(&mut buf1), - /// IoSliceMut::new(&mut buf2), - /// IoSliceMut::new(&mut buf3), - /// ][..]; - /// - /// // Mark 10 bytes as read. - /// IoSliceMut::advance_slices(&mut bufs, 10); - /// assert_eq!(bufs[0].deref(), [2; 14].as_ref()); - /// assert_eq!(bufs[1].deref(), [3; 8].as_ref()); - /// ``` - #[stable(feature = "io_slice_advance", since = "1.81.0")] - #[inline] - pub fn advance_slices(bufs: &mut &mut [IoSliceMut<'a>], n: usize) { - // Number of buffers to remove. - let mut remove = 0; - // Remaining length before reaching n. - let mut left = n; - for buf in bufs.iter() { - if let Some(remainder) = left.checked_sub(buf.len()) { - left = remainder; - remove += 1; - } else { - break; - } - } - - *bufs = &mut take(bufs)[remove..]; - if bufs.is_empty() { - assert!(left == 0, "advancing io slices beyond their length"); - } else { - bufs[0].advance(left); - } - } - - /// Get the underlying bytes as a mutable slice with the original lifetime. - /// - /// # Examples - /// - /// ``` - /// #![feature(io_slice_as_bytes)] - /// use std::io::IoSliceMut; - /// - /// let mut data = *b"abcdef"; - /// let io_slice = IoSliceMut::new(&mut data); - /// io_slice.into_slice()[0] = b'A'; - /// - /// assert_eq!(&data, b"Abcdef"); - /// ``` - #[unstable(feature = "io_slice_as_bytes", issue = "132818")] - pub const fn into_slice(self) -> &'a mut [u8] { - self.0.into_slice() - } -} - -#[stable(feature = "iovec", since = "1.36.0")] -impl<'a> Deref for IoSliceMut<'a> { - type Target = [u8]; - - #[inline] - fn deref(&self) -> &[u8] { - self.0.as_slice() - } -} - -#[stable(feature = "iovec", since = "1.36.0")] -impl<'a> DerefMut for IoSliceMut<'a> { - #[inline] - fn deref_mut(&mut self) -> &mut [u8] { - self.0.as_mut_slice() - } -} - -/// A buffer type used with `Write::write_vectored`. -/// -/// It is semantically a wrapper around a `&[u8]`, but is guaranteed to be -/// ABI compatible with the `iovec` type on Unix platforms and `WSABUF` on -/// Windows. -#[stable(feature = "iovec", since = "1.36.0")] -#[derive(Copy, Clone)] -#[repr(transparent)] -pub struct IoSlice<'a>(sys::io::IoSlice<'a>); - -#[stable(feature = "iovec_send_sync", since = "1.44.0")] -unsafe impl<'a> Send for IoSlice<'a> {} - -#[stable(feature = "iovec_send_sync", since = "1.44.0")] -unsafe impl<'a> Sync for IoSlice<'a> {} - -#[stable(feature = "iovec", since = "1.36.0")] -impl<'a> fmt::Debug for IoSlice<'a> { - fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { - fmt::Debug::fmt(self.0.as_slice(), fmt) - } -} - -impl<'a> IoSlice<'a> { - /// Creates a new `IoSlice` wrapping a byte slice. - /// - /// # Panics - /// - /// Panics on Windows if the slice is larger than 4GB. - #[stable(feature = "iovec", since = "1.36.0")] - #[must_use] - #[inline] - pub fn new(buf: &'a [u8]) -> IoSlice<'a> { - IoSlice(sys::io::IoSlice::new(buf)) - } - - /// Advance the internal cursor of the slice. - /// - /// Also see [`IoSlice::advance_slices`] to advance the cursors of multiple - /// buffers. - /// - /// # Panics - /// - /// Panics when trying to advance beyond the end of the slice. - /// - /// # Examples - /// - /// ``` - /// use std::io::IoSlice; - /// use std::ops::Deref; - /// - /// let data = [1; 8]; - /// let mut buf = IoSlice::new(&data); - /// - /// // Mark 3 bytes as read. - /// buf.advance(3); - /// assert_eq!(buf.deref(), [1; 5].as_ref()); - /// ``` - #[stable(feature = "io_slice_advance", since = "1.81.0")] - #[inline] - pub fn advance(&mut self, n: usize) { - self.0.advance(n) - } - - /// Advance a slice of slices. - /// - /// Shrinks the slice to remove any `IoSlice`s that are fully advanced over. - /// If the cursor ends up in the middle of an `IoSlice`, it is modified - /// to start at that cursor. - /// - /// For example, if we have a slice of two 8-byte `IoSlice`s, and we advance by 10 bytes, - /// the result will only include the second `IoSlice`, advanced by 2 bytes. - /// - /// # Panics - /// - /// Panics when trying to advance beyond the end of the slices. - /// - /// # Examples - /// - /// ``` - /// use std::io::IoSlice; - /// use std::ops::Deref; - /// - /// let buf1 = [1; 8]; - /// let buf2 = [2; 16]; - /// let buf3 = [3; 8]; - /// let mut bufs = &mut [ - /// IoSlice::new(&buf1), - /// IoSlice::new(&buf2), - /// IoSlice::new(&buf3), - /// ][..]; - /// - /// // Mark 10 bytes as written. - /// IoSlice::advance_slices(&mut bufs, 10); - /// assert_eq!(bufs[0].deref(), [2; 14].as_ref()); - /// assert_eq!(bufs[1].deref(), [3; 8].as_ref()); - #[stable(feature = "io_slice_advance", since = "1.81.0")] - #[inline] - pub fn advance_slices(bufs: &mut &mut [IoSlice<'a>], n: usize) { - // Number of buffers to remove. - let mut remove = 0; - // Remaining length before reaching n. This prevents overflow - // that could happen if the length of slices in `bufs` were instead - // accumulated. Those slice may be aliased and, if they are large - // enough, their added length may overflow a `usize`. - let mut left = n; - for buf in bufs.iter() { - if let Some(remainder) = left.checked_sub(buf.len()) { - left = remainder; - remove += 1; - } else { - break; - } - } - - *bufs = &mut take(bufs)[remove..]; - if bufs.is_empty() { - assert!(left == 0, "advancing io slices beyond their length"); - } else { - bufs[0].advance(left); - } - } - - /// Get the underlying bytes as a slice with the original lifetime. - /// - /// This doesn't borrow from `self`, so is less restrictive than calling - /// `.deref()`, which does. - /// - /// # Examples - /// - /// ``` - /// #![feature(io_slice_as_bytes)] - /// use std::io::IoSlice; - /// - /// let data = b"abcdef"; - /// - /// let mut io_slice = IoSlice::new(data); - /// let tail = &io_slice.as_slice()[3..]; - /// - /// // This works because `tail` doesn't borrow `io_slice` - /// io_slice = IoSlice::new(tail); - /// - /// assert_eq!(io_slice.as_slice(), b"def"); - /// ``` - #[unstable(feature = "io_slice_as_bytes", issue = "132818")] - pub const fn as_slice(self) -> &'a [u8] { - self.0.as_slice() - } -} - -#[stable(feature = "iovec", since = "1.36.0")] -impl<'a> Deref for IoSlice<'a> { - type Target = [u8]; - - #[inline] - fn deref(&self) -> &[u8] { - self.0.as_slice() - } -} - -/// A trait for objects which are byte-oriented sinks. -/// -/// Implementors of the `Write` trait are sometimes called 'writers'. -/// -/// Writers are defined by two required methods, [`write`] and [`flush`]: -/// -/// * The [`write`] method will attempt to write some data into the object, -/// returning how many bytes were successfully written. -/// -/// * The [`flush`] method is useful for adapters and explicit buffers -/// themselves for ensuring that all buffered data has been pushed out to the -/// 'true sink'. -/// -/// Writers are intended to be composable with one another. Many implementors -/// throughout [`std::io`] take and provide types which implement the `Write` -/// trait. -/// -/// [`write`]: Write::write -/// [`flush`]: Write::flush -/// [`std::io`]: self -/// -/// # Examples -/// -/// ```no_run -/// use std::io::prelude::*; -/// use std::fs::File; -/// -/// fn main() -> std::io::Result<()> { -/// let data = b"some bytes"; -/// -/// let mut pos = 0; -/// let mut buffer = File::create("foo.txt")?; -/// -/// while pos < data.len() { -/// let bytes_written = buffer.write(&data[pos..])?; -/// pos += bytes_written; -/// } -/// Ok(()) -/// } -/// ``` -/// -/// The trait also provides convenience methods like [`write_all`], which calls -/// `write` in a loop until its entire input has been written. -/// -/// [`write_all`]: Write::write_all -#[stable(feature = "rust1", since = "1.0.0")] -#[doc(notable_trait)] -#[cfg_attr(not(test), rustc_diagnostic_item = "IoWrite")] -pub trait Write { - /// Writes a buffer into this writer, returning how many bytes were written. - /// - /// This function will attempt to write the entire contents of `buf`, but - /// the entire write might not succeed, or the write may also generate an - /// error. Typically, a call to `write` represents one attempt to write to - /// any wrapped object. - /// - /// Calls to `write` are not guaranteed to block waiting for data to be - /// written, and a write which would otherwise block can be indicated through - /// an [`Err`] variant. - /// - /// If this method consumed `n > 0` bytes of `buf` it must return [`Ok(n)`]. - /// If the return value is `Ok(n)` then `n` must satisfy `n <= buf.len()`. - /// A return value of `Ok(0)` typically means that the underlying object is - /// no longer able to accept bytes and will likely not be able to in the - /// future as well, or that the buffer provided is empty. - /// - /// # Errors - /// - /// Each call to `write` may generate an I/O error indicating that the - /// operation could not be completed. If an error is returned then no bytes - /// in the buffer were written to this writer. - /// - /// It is **not** considered an error if the entire buffer could not be - /// written to this writer. - /// - /// An error of the [`ErrorKind::Interrupted`] kind is non-fatal and the - /// write operation should be retried if there is nothing else to do. - /// - /// # Examples - /// - /// ```no_run - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> std::io::Result<()> { - /// let mut buffer = File::create("foo.txt")?; - /// - /// // Writes some prefix of the byte string, not necessarily all of it. - /// buffer.write(b"some bytes")?; - /// Ok(()) - /// } - /// ``` - /// - /// [`Ok(n)`]: Ok - #[stable(feature = "rust1", since = "1.0.0")] - fn write(&mut self, buf: &[u8]) -> Result; - - /// Like [`write`], except that it writes from a slice of buffers. - /// - /// Data is copied from each buffer in order, with the final buffer - /// read from possibly being only partially consumed. This method must - /// behave as a call to [`write`] with the buffers concatenated would. - /// - /// The default implementation calls [`write`] with either the first nonempty - /// buffer provided, or an empty one if none exists. - /// - /// # Examples - /// - /// ```no_run - /// use std::io::IoSlice; - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> std::io::Result<()> { - /// let data1 = [1; 8]; - /// let data2 = [15; 8]; - /// let io_slice1 = IoSlice::new(&data1); - /// let io_slice2 = IoSlice::new(&data2); - /// - /// let mut buffer = File::create("foo.txt")?; - /// - /// // Writes some prefix of the byte string, not necessarily all of it. - /// buffer.write_vectored(&[io_slice1, io_slice2])?; - /// Ok(()) - /// } - /// ``` - /// - /// [`write`]: Write::write - #[stable(feature = "iovec", since = "1.36.0")] - fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> Result { - default_write_vectored(|b| self.write(b), bufs) - } - - /// Determines if this `Write`r has an efficient [`write_vectored`] - /// implementation. - /// - /// If a `Write`r does not override the default [`write_vectored`] - /// implementation, code using it may want to avoid the method all together - /// and coalesce writes into a single buffer for higher performance. - /// - /// The default implementation returns `false`. - /// - /// [`write_vectored`]: Write::write_vectored - #[unstable(feature = "can_vector", issue = "69941")] - fn is_write_vectored(&self) -> bool { - false - } - - /// Flushes this output stream, ensuring that all intermediately buffered - /// contents reach their destination. - /// - /// # Errors - /// - /// It is considered an error if not all bytes could be written due to - /// I/O errors or EOF being reached. - /// - /// # Examples - /// - /// ```no_run - /// use std::io::prelude::*; - /// use std::io::BufWriter; - /// use std::fs::File; - /// - /// fn main() -> std::io::Result<()> { - /// let mut buffer = BufWriter::new(File::create("foo.txt")?); - /// - /// buffer.write_all(b"some bytes")?; - /// buffer.flush()?; - /// Ok(()) - /// } - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - fn flush(&mut self) -> Result<()>; - - /// Attempts to write an entire buffer into this writer. - /// - /// This method will continuously call [`write`] until there is no more data - /// to be written or an error of non-[`ErrorKind::Interrupted`] kind is - /// returned. This method will not return until the entire buffer has been - /// successfully written or such an error occurs. The first error that is - /// not of [`ErrorKind::Interrupted`] kind generated from this method will be - /// returned. - /// - /// If the buffer contains no data, this will never call [`write`]. - /// - /// # Errors - /// - /// This function will return the first error of - /// non-[`ErrorKind::Interrupted`] kind that [`write`] returns. - /// - /// [`write`]: Write::write - /// - /// # Examples - /// - /// ```no_run - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> std::io::Result<()> { - /// let mut buffer = File::create("foo.txt")?; - /// - /// buffer.write_all(b"some bytes")?; - /// Ok(()) - /// } - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - fn write_all(&mut self, mut buf: &[u8]) -> Result<()> { - while !buf.is_empty() { - match self.write(buf) { - Ok(0) => { - return Err(Error::WRITE_ALL_EOF); - } - Ok(n) => buf = &buf[n..], - Err(ref e) if e.is_interrupted() => {} - Err(e) => return Err(e), - } - } - Ok(()) - } - - /// Attempts to write multiple buffers into this writer. - /// - /// This method will continuously call [`write_vectored`] until there is no - /// more data to be written or an error of non-[`ErrorKind::Interrupted`] - /// kind is returned. This method will not return until all buffers have - /// been successfully written or such an error occurs. The first error that - /// is not of [`ErrorKind::Interrupted`] kind generated from this method - /// will be returned. - /// - /// If the buffer contains no data, this will never call [`write_vectored`]. - /// - /// # Notes - /// - /// Unlike [`write_vectored`], this takes a *mutable* reference to - /// a slice of [`IoSlice`]s, not an immutable one. That's because we need to - /// modify the slice to keep track of the bytes already written. - /// - /// Once this function returns, the contents of `bufs` are unspecified, as - /// this depends on how many calls to [`write_vectored`] were necessary. It is - /// best to understand this function as taking ownership of `bufs` and to - /// not use `bufs` afterwards. The underlying buffers, to which the - /// [`IoSlice`]s point (but not the [`IoSlice`]s themselves), are unchanged and - /// can be reused. - /// - /// [`write_vectored`]: Write::write_vectored - /// - /// # Examples - /// - /// ``` - /// #![feature(write_all_vectored)] - /// # fn main() -> std::io::Result<()> { - /// - /// use std::io::{Write, IoSlice}; - /// - /// let mut writer = Vec::new(); - /// let bufs = &mut [ - /// IoSlice::new(&[1]), - /// IoSlice::new(&[2, 3]), - /// IoSlice::new(&[4, 5, 6]), - /// ]; - /// - /// writer.write_all_vectored(bufs)?; - /// // Note: the contents of `bufs` is now undefined, see the Notes section. - /// - /// assert_eq!(writer, &[1, 2, 3, 4, 5, 6]); - /// # Ok(()) } - /// ``` - #[unstable(feature = "write_all_vectored", issue = "70436")] - fn write_all_vectored(&mut self, mut bufs: &mut [IoSlice<'_>]) -> Result<()> { - // Guarantee that bufs is empty if it contains no data, - // to avoid calling write_vectored if there is no data to be written. - IoSlice::advance_slices(&mut bufs, 0); - while !bufs.is_empty() { - match self.write_vectored(bufs) { - Ok(0) => { - return Err(Error::WRITE_ALL_EOF); - } - Ok(n) => IoSlice::advance_slices(&mut bufs, n), - Err(ref e) if e.is_interrupted() => {} - Err(e) => return Err(e), - } - } - Ok(()) - } - - /// Writes a formatted string into this writer, returning any error - /// encountered. - /// - /// This method is primarily used to interface with the - /// [`format_args!()`] macro, and it is rare that this should - /// explicitly be called. The [`write!()`] macro should be favored to - /// invoke this method instead. - /// - /// This function internally uses the [`write_all`] method on - /// this trait and hence will continuously write data so long as no errors - /// are received. This also means that partial writes are not indicated in - /// this signature. - /// - /// [`write_all`]: Write::write_all - /// - /// # Errors - /// - /// This function will return any I/O error reported while formatting. - /// - /// # Examples - /// - /// ```no_run - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> std::io::Result<()> { - /// let mut buffer = File::create("foo.txt")?; - /// - /// // this call - /// write!(buffer, "{:.*}", 2, 1.234567)?; - /// // turns into this: - /// buffer.write_fmt(format_args!("{:.*}", 2, 1.234567))?; - /// Ok(()) - /// } - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - fn write_fmt(&mut self, args: fmt::Arguments<'_>) -> Result<()> { - if let Some(s) = args.as_statically_known_str() { - self.write_all(s.as_bytes()) - } else { - default_write_fmt(self, args) - } - } - - /// Creates a "by reference" adapter for this instance of `Write`. - /// - /// The returned adapter also implements `Write` and will simply borrow this - /// current writer. - /// - /// # Examples - /// - /// ```no_run - /// use std::io::Write; - /// use std::fs::File; - /// - /// fn main() -> std::io::Result<()> { - /// let mut buffer = File::create("foo.txt")?; - /// - /// let reference = buffer.by_ref(); - /// - /// // we can use reference just like our original buffer - /// reference.write_all(b"some bytes")?; - /// Ok(()) - /// } - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - fn by_ref(&mut self) -> &mut Self - where - Self: Sized, - { - self - } -} - -/// The `Seek` trait provides a cursor which can be moved within a stream of -/// bytes. -/// -/// The stream typically has a fixed size, allowing seeking relative to either -/// end or the current offset. -/// -/// # Examples -/// -/// [`File`]s implement `Seek`: -/// -/// [`File`]: crate::fs::File -/// -/// ```no_run -/// use std::io; -/// use std::io::prelude::*; -/// use std::fs::File; -/// use std::io::SeekFrom; -/// -/// fn main() -> io::Result<()> { -/// let mut f = File::open("foo.txt")?; -/// -/// // move the cursor 42 bytes from the start of the file -/// f.seek(SeekFrom::Start(42))?; -/// Ok(()) -/// } -/// ``` -#[stable(feature = "rust1", since = "1.0.0")] -#[cfg_attr(not(test), rustc_diagnostic_item = "IoSeek")] -pub trait Seek { - /// Seek to an offset, in bytes, in a stream. - /// - /// A seek beyond the end of a stream is allowed, but behavior is defined - /// by the implementation. - /// - /// If the seek operation completed successfully, - /// this method returns the new position from the start of the stream. - /// That position can be used later with [`SeekFrom::Start`]. - /// - /// # Errors - /// - /// Seeking can fail, for example because it might involve flushing a buffer. - /// - /// Seeking to a negative offset is considered an error. - #[stable(feature = "rust1", since = "1.0.0")] - fn seek(&mut self, pos: SeekFrom) -> Result; - - /// Rewind to the beginning of a stream. - /// - /// This is a convenience method, equivalent to `seek(SeekFrom::Start(0))`. - /// - /// # Errors - /// - /// Rewinding can fail, for example because it might involve flushing a buffer. - /// - /// # Example - /// - /// ```no_run - /// use std::io::{Read, Seek, Write}; - /// use std::fs::OpenOptions; - /// - /// let mut f = OpenOptions::new() - /// .write(true) - /// .read(true) - /// .create(true) - /// .open("foo.txt")?; - /// - /// let hello = "Hello!\n"; - /// write!(f, "{hello}")?; - /// f.rewind()?; - /// - /// let mut buf = String::new(); - /// f.read_to_string(&mut buf)?; - /// assert_eq!(&buf, hello); - /// # std::io::Result::Ok(()) - /// ``` - #[stable(feature = "seek_rewind", since = "1.55.0")] - fn rewind(&mut self) -> Result<()> { - self.seek(SeekFrom::Start(0))?; - Ok(()) - } - - /// Returns the length of this stream (in bytes). - /// - /// The default implementation uses up to three seek operations. If this - /// method returns successfully, the seek position is unchanged (i.e. the - /// position before calling this method is the same as afterwards). - /// However, if this method returns an error, the seek position is - /// unspecified. - /// - /// If you need to obtain the length of *many* streams and you don't care - /// about the seek position afterwards, you can reduce the number of seek - /// operations by simply calling `seek(SeekFrom::End(0))` and using its - /// return value (it is also the stream length). - /// - /// Note that length of a stream can change over time (for example, when - /// data is appended to a file). So calling this method multiple times does - /// not necessarily return the same length each time. - /// - /// # Example - /// - /// ```no_run - /// #![feature(seek_stream_len)] - /// use std::{ - /// io::{self, Seek}, - /// fs::File, - /// }; - /// - /// fn main() -> io::Result<()> { - /// let mut f = File::open("foo.txt")?; - /// - /// let len = f.stream_len()?; - /// println!("The file is currently {len} bytes long"); - /// Ok(()) - /// } - /// ``` - #[unstable(feature = "seek_stream_len", issue = "59359")] - fn stream_len(&mut self) -> Result { - stream_len_default(self) - } - - /// Returns the current seek position from the start of the stream. - /// - /// This is equivalent to `self.seek(SeekFrom::Current(0))`. - /// - /// # Example - /// - /// ```no_run - /// use std::{ - /// io::{self, BufRead, BufReader, Seek}, - /// fs::File, - /// }; - /// - /// fn main() -> io::Result<()> { - /// let mut f = BufReader::new(File::open("foo.txt")?); - /// - /// let before = f.stream_position()?; - /// f.read_line(&mut String::new())?; - /// let after = f.stream_position()?; - /// - /// println!("The first line was {} bytes long", after - before); - /// Ok(()) - /// } - /// ``` - #[stable(feature = "seek_convenience", since = "1.51.0")] - fn stream_position(&mut self) -> Result { - self.seek(SeekFrom::Current(0)) - } - - /// Seeks relative to the current position. - /// - /// This is equivalent to `self.seek(SeekFrom::Current(offset))` but - /// doesn't return the new position which can allow some implementations - /// such as [`BufReader`] to perform more efficient seeks. - /// - /// # Example - /// - /// ```no_run - /// use std::{ - /// io::{self, Seek}, - /// fs::File, - /// }; - /// - /// fn main() -> io::Result<()> { - /// let mut f = File::open("foo.txt")?; - /// f.seek_relative(10)?; - /// assert_eq!(f.stream_position()?, 10); - /// Ok(()) - /// } - /// ``` - /// - /// [`BufReader`]: crate::io::BufReader - #[stable(feature = "seek_seek_relative", since = "1.80.0")] - fn seek_relative(&mut self, offset: i64) -> Result<()> { - self.seek(SeekFrom::Current(offset))?; - Ok(()) - } -} - -pub(crate) fn stream_len_default(self_: &mut T) -> Result { - let old_pos = self_.stream_position()?; - let len = self_.seek(SeekFrom::End(0))?; - - // Avoid seeking a third time when we were already at the end of the - // stream. The branch is usually way cheaper than a seek operation. - if old_pos != len { - self_.seek(SeekFrom::Start(old_pos))?; - } - - Ok(len) -} - -/// Enumeration of possible methods to seek within an I/O object. -/// -/// It is used by the [`Seek`] trait. -#[derive(Copy, PartialEq, Eq, Clone, Debug)] -#[stable(feature = "rust1", since = "1.0.0")] -#[cfg_attr(not(test), rustc_diagnostic_item = "SeekFrom")] -pub enum SeekFrom { - /// Sets the offset to the provided number of bytes. - #[stable(feature = "rust1", since = "1.0.0")] - Start(#[stable(feature = "rust1", since = "1.0.0")] u64), - - /// Sets the offset to the size of this object plus the specified number of - /// bytes. - /// - /// It is possible to seek beyond the end of an object, but it's an error to - /// seek before byte 0. - #[stable(feature = "rust1", since = "1.0.0")] - End(#[stable(feature = "rust1", since = "1.0.0")] i64), - - /// Sets the offset to the current position plus the specified number of - /// bytes. - /// - /// It is possible to seek beyond the end of an object, but it's an error to - /// seek before byte 0. - #[stable(feature = "rust1", since = "1.0.0")] - Current(#[stable(feature = "rust1", since = "1.0.0")] i64), -} - -fn read_until(r: &mut R, delim: u8, buf: &mut Vec) -> Result { - let mut read = 0; - loop { - let (done, used) = { - let available = match r.fill_buf() { - Ok(n) => n, - Err(ref e) if e.is_interrupted() => continue, - Err(e) => return Err(e), - }; - match memchr::memchr(delim, available) { - Some(i) => { - buf.extend_from_slice(&available[..=i]); - (true, i + 1) - } - None => { - buf.extend_from_slice(available); - (false, available.len()) - } - } - }; - r.consume(used); - read += used; - if done || used == 0 { - return Ok(read); - } - } -} - -fn skip_until(r: &mut R, delim: u8) -> Result { - let mut read = 0; - loop { - let (done, used) = { - let available = match r.fill_buf() { - Ok(n) => n, - Err(ref e) if e.kind() == ErrorKind::Interrupted => continue, - Err(e) => return Err(e), - }; - match memchr::memchr(delim, available) { - Some(i) => (true, i + 1), - None => (false, available.len()), - } - }; - r.consume(used); - read += used; - if done || used == 0 { - return Ok(read); - } - } -} - -/// A `BufRead` is a type of `Read`er which has an internal buffer, allowing it -/// to perform extra ways of reading. -/// -/// For example, reading line-by-line is inefficient without using a buffer, so -/// if you want to read by line, you'll need `BufRead`, which includes a -/// [`read_line`] method as well as a [`lines`] iterator. -/// -/// # Examples -/// -/// A locked standard input implements `BufRead`: -/// -/// ```no_run -/// use std::io; -/// use std::io::prelude::*; -/// -/// let stdin = io::stdin(); -/// for line in stdin.lock().lines() { -/// println!("{}", line?); -/// } -/// # std::io::Result::Ok(()) -/// ``` -/// -/// If you have something that implements [`Read`], you can use the [`BufReader` -/// type][`BufReader`] to turn it into a `BufRead`. -/// -/// For example, [`File`] implements [`Read`], but not `BufRead`. -/// [`BufReader`] to the rescue! -/// -/// [`File`]: crate::fs::File -/// [`read_line`]: BufRead::read_line -/// [`lines`]: BufRead::lines -/// -/// ```no_run -/// use std::io::{self, BufReader}; -/// use std::io::prelude::*; -/// use std::fs::File; -/// -/// fn main() -> io::Result<()> { -/// let f = File::open("foo.txt")?; -/// let f = BufReader::new(f); -/// -/// for line in f.lines() { -/// let line = line?; -/// println!("{line}"); -/// } -/// -/// Ok(()) -/// } -/// ``` -#[stable(feature = "rust1", since = "1.0.0")] -#[cfg_attr(not(test), rustc_diagnostic_item = "IoBufRead")] -pub trait BufRead: Read { - /// Returns the contents of the internal buffer, filling it with more data, via `Read` methods, if empty. - /// - /// This is a lower-level method and is meant to be used together with [`consume`], - /// which can be used to mark bytes that should not be returned by subsequent calls to `read`. - /// - /// [`consume`]: BufRead::consume - /// - /// Returns an empty buffer when the stream has reached EOF. - /// - /// # Errors - /// - /// This function will return an I/O error if a `Read` method was called, but returned an error. - /// - /// # Examples - /// - /// A locked standard input implements `BufRead`: - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// - /// let stdin = io::stdin(); - /// let mut stdin = stdin.lock(); - /// - /// let buffer = stdin.fill_buf()?; - /// - /// // work with buffer - /// println!("{buffer:?}"); - /// - /// // mark the bytes we worked with as read - /// let length = buffer.len(); - /// stdin.consume(length); - /// # std::io::Result::Ok(()) - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - fn fill_buf(&mut self) -> Result<&[u8]>; - - /// Marks the given `amount` of additional bytes from the internal buffer as having been read. - /// Subsequent calls to `read` only return bytes that have not been marked as read. - /// - /// This is a lower-level method and is meant to be used together with [`fill_buf`], - /// which can be used to fill the internal buffer via `Read` methods. - /// - /// It is a logic error if `amount` exceeds the number of unread bytes in the internal buffer, which is returned by [`fill_buf`]. - /// - /// # Examples - /// - /// Since `consume()` is meant to be used with [`fill_buf`], - /// that method's example includes an example of `consume()`. - /// - /// [`fill_buf`]: BufRead::fill_buf - #[stable(feature = "rust1", since = "1.0.0")] - fn consume(&mut self, amount: usize); - - /// Checks if there is any data left to be `read`. - /// - /// This function may fill the buffer to check for data, - /// so this function returns `Result`, not `bool`. - /// - /// The default implementation calls `fill_buf` and checks that the - /// returned slice is empty (which means that there is no data left, - /// since EOF is reached). - /// - /// # Errors - /// - /// This function will return an I/O error if a `Read` method was called, but returned an error. - /// - /// Examples - /// - /// ``` - /// #![feature(buf_read_has_data_left)] - /// use std::io; - /// use std::io::prelude::*; - /// - /// let stdin = io::stdin(); - /// let mut stdin = stdin.lock(); - /// - /// while stdin.has_data_left()? { - /// let mut line = String::new(); - /// stdin.read_line(&mut line)?; - /// // work with line - /// println!("{line:?}"); - /// } - /// # std::io::Result::Ok(()) - /// ``` - #[unstable(feature = "buf_read_has_data_left", issue = "86423")] - fn has_data_left(&mut self) -> Result { - self.fill_buf().map(|b| !b.is_empty()) - } - - /// Reads all bytes into `buf` until the delimiter `byte` or EOF is reached. - /// - /// This function will read bytes from the underlying stream until the - /// delimiter or EOF is found. Once found, all bytes up to, and including, - /// the delimiter (if found) will be appended to `buf`. - /// - /// If successful, this function will return the total number of bytes read. - /// - /// This function is blocking and should be used carefully: it is possible for - /// an attacker to continuously send bytes without ever sending the delimiter - /// or EOF. - /// - /// # Errors - /// - /// This function will ignore all instances of [`ErrorKind::Interrupted`] and - /// will otherwise return any errors returned by [`fill_buf`]. - /// - /// If an I/O error is encountered then all bytes read so far will be - /// present in `buf` and its length will have been adjusted appropriately. - /// - /// [`fill_buf`]: BufRead::fill_buf - /// - /// # Examples - /// - /// [`std::io::Cursor`][`Cursor`] is a type that implements `BufRead`. In - /// this example, we use [`Cursor`] to read all the bytes in a byte slice - /// in hyphen delimited segments: - /// - /// ``` - /// use std::io::{self, BufRead}; - /// - /// let mut cursor = io::Cursor::new(b"lorem-ipsum"); - /// let mut buf = vec![]; - /// - /// // cursor is at 'l' - /// let num_bytes = cursor.read_until(b'-', &mut buf) - /// .expect("reading from cursor won't fail"); - /// assert_eq!(num_bytes, 6); - /// assert_eq!(buf, b"lorem-"); - /// buf.clear(); - /// - /// // cursor is at 'i' - /// let num_bytes = cursor.read_until(b'-', &mut buf) - /// .expect("reading from cursor won't fail"); - /// assert_eq!(num_bytes, 5); - /// assert_eq!(buf, b"ipsum"); - /// buf.clear(); - /// - /// // cursor is at EOF - /// let num_bytes = cursor.read_until(b'-', &mut buf) - /// .expect("reading from cursor won't fail"); - /// assert_eq!(num_bytes, 0); - /// assert_eq!(buf, b""); - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - fn read_until(&mut self, byte: u8, buf: &mut Vec) -> Result { - read_until(self, byte, buf) - } - - /// Skips all bytes until the delimiter `byte` or EOF is reached. - /// - /// This function will read (and discard) bytes from the underlying stream until the - /// delimiter or EOF is found. - /// - /// If successful, this function will return the total number of bytes read, - /// including the delimiter byte if found. - /// - /// This is useful for efficiently skipping data such as NUL-terminated strings - /// in binary file formats without buffering. - /// - /// This function is blocking and should be used carefully: it is possible for - /// an attacker to continuously send bytes without ever sending the delimiter - /// or EOF. - /// - /// # Errors - /// - /// This function will ignore all instances of [`ErrorKind::Interrupted`] and - /// will otherwise return any errors returned by [`fill_buf`]. - /// - /// If an I/O error is encountered then all bytes read so far will be - /// present in `buf` and its length will have been adjusted appropriately. - /// - /// [`fill_buf`]: BufRead::fill_buf - /// - /// # Examples - /// - /// [`std::io::Cursor`][`Cursor`] is a type that implements `BufRead`. In - /// this example, we use [`Cursor`] to read some NUL-terminated information - /// about Ferris from a binary string, skipping the fun fact: - /// - /// ``` - /// use std::io::{self, BufRead}; - /// - /// let mut cursor = io::Cursor::new(b"Ferris\0Likes long walks on the beach\0Crustacean\0!"); - /// - /// // read name - /// let mut name = Vec::new(); - /// let num_bytes = cursor.read_until(b'\0', &mut name) - /// .expect("reading from cursor won't fail"); - /// assert_eq!(num_bytes, 7); - /// assert_eq!(name, b"Ferris\0"); - /// - /// // skip fun fact - /// let num_bytes = cursor.skip_until(b'\0') - /// .expect("reading from cursor won't fail"); - /// assert_eq!(num_bytes, 30); - /// - /// // read animal type - /// let mut animal = Vec::new(); - /// let num_bytes = cursor.read_until(b'\0', &mut animal) - /// .expect("reading from cursor won't fail"); - /// assert_eq!(num_bytes, 11); - /// assert_eq!(animal, b"Crustacean\0"); - /// - /// // reach EOF - /// let num_bytes = cursor.skip_until(b'\0') - /// .expect("reading from cursor won't fail"); - /// assert_eq!(num_bytes, 1); - /// ``` - #[stable(feature = "bufread_skip_until", since = "1.83.0")] - fn skip_until(&mut self, byte: u8) -> Result { - skip_until(self, byte) - } - - /// Reads all bytes until a newline (the `0xA` byte) is reached, and append - /// them to the provided `String` buffer. - /// - /// Previous content of the buffer will be preserved. To avoid appending to - /// the buffer, you need to [`clear`] it first. - /// - /// This function will read bytes from the underlying stream until the - /// newline delimiter (the `0xA` byte) or EOF is found. Once found, all bytes - /// up to, and including, the delimiter (if found) will be appended to - /// `buf`. - /// - /// If successful, this function will return the total number of bytes read. - /// - /// If this function returns [`Ok(0)`], the stream has reached EOF. - /// - /// This function is blocking and should be used carefully: it is possible for - /// an attacker to continuously send bytes without ever sending a newline - /// or EOF. You can use [`take`] to limit the maximum number of bytes read. - /// - /// [`Ok(0)`]: Ok - /// [`clear`]: String::clear - /// [`take`]: crate::io::Read::take - /// - /// # Errors - /// - /// This function has the same error semantics as [`read_until`] and will - /// also return an error if the read bytes are not valid UTF-8. If an I/O - /// error is encountered then `buf` may contain some bytes already read in - /// the event that all data read so far was valid UTF-8. - /// - /// [`read_until`]: BufRead::read_until - /// - /// # Examples - /// - /// [`std::io::Cursor`][`Cursor`] is a type that implements `BufRead`. In - /// this example, we use [`Cursor`] to read all the lines in a byte slice: - /// - /// ``` - /// use std::io::{self, BufRead}; - /// - /// let mut cursor = io::Cursor::new(b"foo\nbar"); - /// let mut buf = String::new(); - /// - /// // cursor is at 'f' - /// let num_bytes = cursor.read_line(&mut buf) - /// .expect("reading from cursor won't fail"); - /// assert_eq!(num_bytes, 4); - /// assert_eq!(buf, "foo\n"); - /// buf.clear(); - /// - /// // cursor is at 'b' - /// let num_bytes = cursor.read_line(&mut buf) - /// .expect("reading from cursor won't fail"); - /// assert_eq!(num_bytes, 3); - /// assert_eq!(buf, "bar"); - /// buf.clear(); - /// - /// // cursor is at EOF - /// let num_bytes = cursor.read_line(&mut buf) - /// .expect("reading from cursor won't fail"); - /// assert_eq!(num_bytes, 0); - /// assert_eq!(buf, ""); - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - fn read_line(&mut self, buf: &mut String) -> Result { - // Note that we are not calling the `.read_until` method here, but - // rather our hardcoded implementation. For more details as to why, see - // the comments in `default_read_to_string`. - unsafe { append_to_string(buf, |b| read_until(self, b'\n', b)) } - } - - /// Returns an iterator over the contents of this reader split on the byte - /// `byte`. - /// - /// The iterator returned from this function will return instances of - /// [io::Result]<[Vec]\>. Each vector returned will *not* have - /// the delimiter byte at the end. - /// - /// This function will yield errors whenever [`read_until`] would have - /// also yielded an error. - /// - /// [io::Result]: self::Result "io::Result" - /// [`read_until`]: BufRead::read_until - /// - /// # Examples - /// - /// [`std::io::Cursor`][`Cursor`] is a type that implements `BufRead`. In - /// this example, we use [`Cursor`] to iterate over all hyphen delimited - /// segments in a byte slice - /// - /// ``` - /// use std::io::{self, BufRead}; - /// - /// let cursor = io::Cursor::new(b"lorem-ipsum-dolor"); - /// - /// let mut split_iter = cursor.split(b'-').map(|l| l.unwrap()); - /// assert_eq!(split_iter.next(), Some(b"lorem".to_vec())); - /// assert_eq!(split_iter.next(), Some(b"ipsum".to_vec())); - /// assert_eq!(split_iter.next(), Some(b"dolor".to_vec())); - /// assert_eq!(split_iter.next(), None); - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - fn split(self, byte: u8) -> Split - where - Self: Sized, - { - Split { buf: self, delim: byte } - } - - /// Returns an iterator over the lines of this reader. - /// - /// The iterator returned from this function will yield instances of - /// [io::Result]<[String]>. Each string returned will *not* have a newline - /// byte (the `0xA` byte) or `CRLF` (`0xD`, `0xA` bytes) at the end. - /// - /// [io::Result]: self::Result "io::Result" - /// - /// # Examples - /// - /// [`std::io::Cursor`][`Cursor`] is a type that implements `BufRead`. In - /// this example, we use [`Cursor`] to iterate over all the lines in a byte - /// slice. - /// - /// ``` - /// use std::io::{self, BufRead}; - /// - /// let cursor = io::Cursor::new(b"lorem\nipsum\r\ndolor"); - /// - /// let mut lines_iter = cursor.lines().map(|l| l.unwrap()); - /// assert_eq!(lines_iter.next(), Some(String::from("lorem"))); - /// assert_eq!(lines_iter.next(), Some(String::from("ipsum"))); - /// assert_eq!(lines_iter.next(), Some(String::from("dolor"))); - /// assert_eq!(lines_iter.next(), None); - /// ``` - /// - /// # Errors - /// - /// Each line of the iterator has the same error semantics as [`BufRead::read_line`]. - #[stable(feature = "rust1", since = "1.0.0")] - fn lines(self) -> Lines - where - Self: Sized, - { - Lines { buf: self } - } -} - -/// Adapter to chain together two readers. -/// -/// This struct is generally created by calling [`chain`] on a reader. -/// Please see the documentation of [`chain`] for more details. -/// -/// [`chain`]: Read::chain -#[stable(feature = "rust1", since = "1.0.0")] -#[derive(Debug)] -pub struct Chain { - first: T, - second: U, - done_first: bool, -} - -impl Chain { - /// Consumes the `Chain`, returning the wrapped readers. - /// - /// # Examples - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let mut foo_file = File::open("foo.txt")?; - /// let mut bar_file = File::open("bar.txt")?; - /// - /// let chain = foo_file.chain(bar_file); - /// let (foo_file, bar_file) = chain.into_inner(); - /// Ok(()) - /// } - /// ``` - #[stable(feature = "more_io_inner_methods", since = "1.20.0")] - pub fn into_inner(self) -> (T, U) { - (self.first, self.second) - } - - /// Gets references to the underlying readers in this `Chain`. - /// - /// Care should be taken to avoid modifying the internal I/O state of the - /// underlying readers as doing so may corrupt the internal state of this - /// `Chain`. - /// - /// # Examples - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let mut foo_file = File::open("foo.txt")?; - /// let mut bar_file = File::open("bar.txt")?; - /// - /// let chain = foo_file.chain(bar_file); - /// let (foo_file, bar_file) = chain.get_ref(); - /// Ok(()) - /// } - /// ``` - #[stable(feature = "more_io_inner_methods", since = "1.20.0")] - pub fn get_ref(&self) -> (&T, &U) { - (&self.first, &self.second) - } - - /// Gets mutable references to the underlying readers in this `Chain`. - /// - /// Care should be taken to avoid modifying the internal I/O state of the - /// underlying readers as doing so may corrupt the internal state of this - /// `Chain`. - /// - /// # Examples - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let mut foo_file = File::open("foo.txt")?; - /// let mut bar_file = File::open("bar.txt")?; - /// - /// let mut chain = foo_file.chain(bar_file); - /// let (foo_file, bar_file) = chain.get_mut(); - /// Ok(()) - /// } - /// ``` - #[stable(feature = "more_io_inner_methods", since = "1.20.0")] - pub fn get_mut(&mut self) -> (&mut T, &mut U) { - (&mut self.first, &mut self.second) - } -} - -#[stable(feature = "rust1", since = "1.0.0")] -impl Read for Chain { - fn read(&mut self, buf: &mut [u8]) -> Result { - if !self.done_first { - match self.first.read(buf)? { - 0 if !buf.is_empty() => self.done_first = true, - n => return Ok(n), - } - } - self.second.read(buf) - } - - fn read_vectored(&mut self, bufs: &mut [IoSliceMut<'_>]) -> Result { - if !self.done_first { - match self.first.read_vectored(bufs)? { - 0 if bufs.iter().any(|b| !b.is_empty()) => self.done_first = true, - n => return Ok(n), - } - } - self.second.read_vectored(bufs) - } - - #[inline] - fn is_read_vectored(&self) -> bool { - self.first.is_read_vectored() || self.second.is_read_vectored() - } - - fn read_to_end(&mut self, buf: &mut Vec) -> Result { - let mut read = 0; - if !self.done_first { - read += self.first.read_to_end(buf)?; - self.done_first = true; - } - read += self.second.read_to_end(buf)?; - Ok(read) - } - - // We don't override `read_to_string` here because an UTF-8 sequence could - // be split between the two parts of the chain - - fn read_buf(&mut self, mut buf: BorrowedCursor<'_>) -> Result<()> { - if buf.capacity() == 0 { - return Ok(()); - } - - if !self.done_first { - let old_len = buf.written(); - self.first.read_buf(buf.reborrow())?; - - if buf.written() != old_len { - return Ok(()); - } else { - self.done_first = true; - } - } - self.second.read_buf(buf) - } -} - -#[stable(feature = "chain_bufread", since = "1.9.0")] -impl BufRead for Chain { - fn fill_buf(&mut self) -> Result<&[u8]> { - if !self.done_first { - match self.first.fill_buf()? { - buf if buf.is_empty() => self.done_first = true, - buf => return Ok(buf), - } - } - self.second.fill_buf() - } - - fn consume(&mut self, amt: usize) { - if !self.done_first { self.first.consume(amt) } else { self.second.consume(amt) } - } - - fn read_until(&mut self, byte: u8, buf: &mut Vec) -> Result { - let mut read = 0; - if !self.done_first { - let n = self.first.read_until(byte, buf)?; - read += n; - - match buf.last() { - Some(b) if *b == byte && n != 0 => return Ok(read), - _ => self.done_first = true, - } - } - read += self.second.read_until(byte, buf)?; - Ok(read) - } - - // We don't override `read_line` here because an UTF-8 sequence could be - // split between the two parts of the chain -} - -impl SizeHint for Chain { - #[inline] - fn lower_bound(&self) -> usize { - SizeHint::lower_bound(&self.first) + SizeHint::lower_bound(&self.second) - } - - #[inline] - fn upper_bound(&self) -> Option { - match (SizeHint::upper_bound(&self.first), SizeHint::upper_bound(&self.second)) { - (Some(first), Some(second)) => first.checked_add(second), - _ => None, - } - } -} - -/// Reader adapter which limits the bytes read from an underlying reader. -/// -/// This struct is generally created by calling [`take`] on a reader. -/// Please see the documentation of [`take`] for more details. -/// -/// [`take`]: Read::take -#[stable(feature = "rust1", since = "1.0.0")] -#[derive(Debug)] -pub struct Take { - inner: T, - len: u64, - limit: u64, -} - -impl Take { - /// Returns the number of bytes that can be read before this instance will - /// return EOF. - /// - /// # Note - /// - /// This instance may reach `EOF` after reading fewer bytes than indicated by - /// this method if the underlying [`Read`] instance reaches EOF. - /// - /// # Examples - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let f = File::open("foo.txt")?; - /// - /// // read at most five bytes - /// let handle = f.take(5); - /// - /// println!("limit: {}", handle.limit()); - /// Ok(()) - /// } - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - pub fn limit(&self) -> u64 { - self.limit - } - - /// Returns the number of bytes read so far. - #[unstable(feature = "seek_io_take_position", issue = "97227")] - pub fn position(&self) -> u64 { - self.len - self.limit - } - - /// Sets the number of bytes that can be read before this instance will - /// return EOF. This is the same as constructing a new `Take` instance, so - /// the amount of bytes read and the previous limit value don't matter when - /// calling this method. - /// - /// # Examples - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let f = File::open("foo.txt")?; - /// - /// // read at most five bytes - /// let mut handle = f.take(5); - /// handle.set_limit(10); - /// - /// assert_eq!(handle.limit(), 10); - /// Ok(()) - /// } - /// ``` - #[stable(feature = "take_set_limit", since = "1.27.0")] - pub fn set_limit(&mut self, limit: u64) { - self.len = limit; - self.limit = limit; - } - - /// Consumes the `Take`, returning the wrapped reader. - /// - /// # Examples - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let mut file = File::open("foo.txt")?; - /// - /// let mut buffer = [0; 5]; - /// let mut handle = file.take(5); - /// handle.read(&mut buffer)?; - /// - /// let file = handle.into_inner(); - /// Ok(()) - /// } - /// ``` - #[stable(feature = "io_take_into_inner", since = "1.15.0")] - pub fn into_inner(self) -> T { - self.inner - } - - /// Gets a reference to the underlying reader. - /// - /// Care should be taken to avoid modifying the internal I/O state of the - /// underlying reader as doing so may corrupt the internal limit of this - /// `Take`. - /// - /// # Examples - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let mut file = File::open("foo.txt")?; - /// - /// let mut buffer = [0; 5]; - /// let mut handle = file.take(5); - /// handle.read(&mut buffer)?; - /// - /// let file = handle.get_ref(); - /// Ok(()) - /// } - /// ``` - #[stable(feature = "more_io_inner_methods", since = "1.20.0")] - pub fn get_ref(&self) -> &T { - &self.inner - } - - /// Gets a mutable reference to the underlying reader. - /// - /// Care should be taken to avoid modifying the internal I/O state of the - /// underlying reader as doing so may corrupt the internal limit of this - /// `Take`. - /// - /// # Examples - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let mut file = File::open("foo.txt")?; - /// - /// let mut buffer = [0; 5]; - /// let mut handle = file.take(5); - /// handle.read(&mut buffer)?; - /// - /// let file = handle.get_mut(); - /// Ok(()) - /// } - /// ``` - #[stable(feature = "more_io_inner_methods", since = "1.20.0")] - pub fn get_mut(&mut self) -> &mut T { - &mut self.inner - } -} - -#[stable(feature = "rust1", since = "1.0.0")] -impl Read for Take { - fn read(&mut self, buf: &mut [u8]) -> Result { - // Don't call into inner reader at all at EOF because it may still block - if self.limit == 0 { - return Ok(0); - } - - let max = cmp::min(buf.len() as u64, self.limit) as usize; - let n = self.inner.read(&mut buf[..max])?; - assert!(n as u64 <= self.limit, "number of read bytes exceeds limit"); - self.limit -= n as u64; - Ok(n) - } - - fn read_buf(&mut self, mut buf: BorrowedCursor<'_>) -> Result<()> { - // Don't call into inner reader at all at EOF because it may still block - if self.limit == 0 { - return Ok(()); - } - - if self.limit < buf.capacity() as u64 { - // The condition above guarantees that `self.limit` fits in `usize`. - let limit = self.limit as usize; - - let extra_init = cmp::min(limit, buf.init_mut().len()); - - // SAFETY: no uninit data is written to ibuf - let ibuf = unsafe { &mut buf.as_mut()[..limit] }; - - let mut sliced_buf: BorrowedBuf<'_> = ibuf.into(); - - // SAFETY: extra_init bytes of ibuf are known to be initialized - unsafe { - sliced_buf.set_init(extra_init); - } - - let mut cursor = sliced_buf.unfilled(); - let result = self.inner.read_buf(cursor.reborrow()); - - let new_init = cursor.init_mut().len(); - let filled = sliced_buf.len(); - - // cursor / sliced_buf / ibuf must drop here - - unsafe { - // SAFETY: filled bytes have been filled and therefore initialized - buf.advance_unchecked(filled); - // SAFETY: new_init bytes of buf's unfilled buffer have been initialized - buf.set_init(new_init); - } - - self.limit -= filled as u64; - - result - } else { - let written = buf.written(); - let result = self.inner.read_buf(buf.reborrow()); - self.limit -= (buf.written() - written) as u64; - result - } - } -} - -#[stable(feature = "rust1", since = "1.0.0")] -impl BufRead for Take { - fn fill_buf(&mut self) -> Result<&[u8]> { - // Don't call into inner reader at all at EOF because it may still block - if self.limit == 0 { - return Ok(&[]); - } - - let buf = self.inner.fill_buf()?; - let cap = cmp::min(buf.len() as u64, self.limit) as usize; - Ok(&buf[..cap]) - } - - fn consume(&mut self, amt: usize) { - // Don't let callers reset the limit by passing an overlarge value - let amt = cmp::min(amt as u64, self.limit) as usize; - self.limit -= amt as u64; - self.inner.consume(amt); - } -} - -impl SizeHint for Take { - #[inline] - fn lower_bound(&self) -> usize { - cmp::min(SizeHint::lower_bound(&self.inner) as u64, self.limit) as usize - } - - #[inline] - fn upper_bound(&self) -> Option { - match SizeHint::upper_bound(&self.inner) { - Some(upper_bound) => Some(cmp::min(upper_bound as u64, self.limit) as usize), - None => self.limit.try_into().ok(), - } - } -} - -#[stable(feature = "seek_io_take", since = "1.89.0")] -impl Seek for Take { - fn seek(&mut self, pos: SeekFrom) -> Result { - let new_position = match pos { - SeekFrom::Start(v) => Some(v), - SeekFrom::Current(v) => self.position().checked_add_signed(v), - SeekFrom::End(v) => self.len.checked_add_signed(v), - }; - let new_position = match new_position { - Some(v) if v <= self.len => v, - _ => return Err(ErrorKind::InvalidInput.into()), - }; - while new_position != self.position() { - if let Some(offset) = new_position.checked_signed_diff(self.position()) { - self.inner.seek_relative(offset)?; - self.limit = self.limit.wrapping_sub(offset as u64); - break; - } - let offset = if new_position > self.position() { i64::MAX } else { i64::MIN }; - self.inner.seek_relative(offset)?; - self.limit = self.limit.wrapping_sub(offset as u64); - } - Ok(new_position) - } - - fn stream_len(&mut self) -> Result { - Ok(self.len) - } - - fn stream_position(&mut self) -> Result { - Ok(self.position()) - } - - fn seek_relative(&mut self, offset: i64) -> Result<()> { - if !self.position().checked_add_signed(offset).is_some_and(|p| p <= self.len) { - return Err(ErrorKind::InvalidInput.into()); - } - self.inner.seek_relative(offset)?; - self.limit = self.limit.wrapping_sub(offset as u64); - Ok(()) - } -} - -/// An iterator over `u8` values of a reader. -/// -/// This struct is generally created by calling [`bytes`] on a reader. -/// Please see the documentation of [`bytes`] for more details. -/// -/// [`bytes`]: Read::bytes -#[stable(feature = "rust1", since = "1.0.0")] -#[derive(Debug)] -pub struct Bytes { - inner: R, -} - -#[stable(feature = "rust1", since = "1.0.0")] -impl Iterator for Bytes { - type Item = Result; - - // Not `#[inline]`. This function gets inlined even without it, but having - // the inline annotation can result in worse code generation. See #116785. - fn next(&mut self) -> Option> { - SpecReadByte::spec_read_byte(&mut self.inner) - } - - #[inline] - fn size_hint(&self) -> (usize, Option) { - SizeHint::size_hint(&self.inner) - } -} - -/// For the specialization of `Bytes::next`. -trait SpecReadByte { - fn spec_read_byte(&mut self) -> Option>; -} - -impl SpecReadByte for R -where - Self: Read, -{ - #[inline] - default fn spec_read_byte(&mut self) -> Option> { - inlined_slow_read_byte(self) - } -} - -/// Reads a single byte in a slow, generic way. This is used by the default -/// `spec_read_byte`. -#[inline] -fn inlined_slow_read_byte(reader: &mut R) -> Option> { - let mut byte = 0; - loop { - return match reader.read(slice::from_mut(&mut byte)) { - Ok(0) => None, - Ok(..) => Some(Ok(byte)), - Err(ref e) if e.is_interrupted() => continue, - Err(e) => Some(Err(e)), - }; - } -} - -// Used by `BufReader::spec_read_byte`, for which the `inline(never)` is -// important. -#[inline(never)] -fn uninlined_slow_read_byte(reader: &mut R) -> Option> { - inlined_slow_read_byte(reader) -} - -trait SizeHint { - fn lower_bound(&self) -> usize; - - fn upper_bound(&self) -> Option; - - fn size_hint(&self) -> (usize, Option) { - (self.lower_bound(), self.upper_bound()) - } -} - -impl SizeHint for T { - #[inline] - default fn lower_bound(&self) -> usize { - 0 - } - - #[inline] - default fn upper_bound(&self) -> Option { - None - } -} - -impl SizeHint for &mut T { - #[inline] - fn lower_bound(&self) -> usize { - SizeHint::lower_bound(*self) - } - - #[inline] - fn upper_bound(&self) -> Option { - SizeHint::upper_bound(*self) - } -} - -impl SizeHint for Box { - #[inline] - fn lower_bound(&self) -> usize { - SizeHint::lower_bound(&**self) - } - - #[inline] - fn upper_bound(&self) -> Option { - SizeHint::upper_bound(&**self) - } -} - -impl SizeHint for &[u8] { - #[inline] - fn lower_bound(&self) -> usize { - self.len() - } - - #[inline] - fn upper_bound(&self) -> Option { - Some(self.len()) - } -} - -/// An iterator over the contents of an instance of `BufRead` split on a -/// particular byte. -/// -/// This struct is generally created by calling [`split`] on a `BufRead`. -/// Please see the documentation of [`split`] for more details. -/// -/// [`split`]: BufRead::split -#[stable(feature = "rust1", since = "1.0.0")] -#[derive(Debug)] -pub struct Split { - buf: B, - delim: u8, -} - -#[stable(feature = "rust1", since = "1.0.0")] -impl Iterator for Split { - type Item = Result>; - - fn next(&mut self) -> Option>> { - let mut buf = Vec::new(); - match self.buf.read_until(self.delim, &mut buf) { - Ok(0) => None, - Ok(_n) => { - if buf[buf.len() - 1] == self.delim { - buf.pop(); - } - Some(Ok(buf)) - } - Err(e) => Some(Err(e)), - } - } -} - -/// An iterator over the lines of an instance of `BufRead`. -/// -/// This struct is generally created by calling [`lines`] on a `BufRead`. -/// Please see the documentation of [`lines`] for more details. -/// -/// [`lines`]: BufRead::lines -#[stable(feature = "rust1", since = "1.0.0")] -#[derive(Debug)] -#[cfg_attr(not(test), rustc_diagnostic_item = "IoLines")] -pub struct Lines { - buf: B, -} - -#[stable(feature = "rust1", since = "1.0.0")] -impl Iterator for Lines { - type Item = Result; - - fn next(&mut self) -> Option> { - let mut buf = String::new(); - match self.buf.read_line(&mut buf) { - Ok(0) => None, - Ok(_n) => { - if buf.ends_with('\n') { - buf.pop(); - if buf.ends_with('\r') { - buf.pop(); - } - } - Some(Ok(buf)) - } - Err(e) => Some(Err(e)), - } - } -} diff --git a/library/std/src/io/pipe.rs b/library/std/src/io/pipe.rs index 61b81cf074a6e..11df101248c28 100644 --- a/library/std/src/io/pipe.rs +++ b/library/std/src/io/pipe.rs @@ -40,8 +40,6 @@ use crate::sys::{FromInner, IntoInner, pipe as imp}; /// # Example /// /// ```no_run -/// # #[cfg(miri)] fn main() {} -/// # #[cfg(not(miri))] /// # fn main() -> std::io::Result<()> { /// use std::io::{Read, Write, pipe}; /// use std::process::Command; @@ -126,8 +124,6 @@ impl PipeReader { /// # Examples /// /// ```no_run - /// # #[cfg(miri)] fn main() {} - /// # #[cfg(not(miri))] /// # fn main() -> std::io::Result<()> { /// use std::fs; /// use std::io::{pipe, Write}; @@ -185,8 +181,6 @@ impl PipeWriter { /// # Examples /// /// ```no_run - /// # #[cfg(miri)] fn main() {} - /// # #[cfg(not(miri))] /// # fn main() -> std::io::Result<()> { /// use std::process::Command; /// use std::io::{pipe, Read}; @@ -233,7 +227,7 @@ impl io::Read for &PipeReader { fn read_to_end(&mut self, buf: &mut Vec) -> io::Result { self.0.read_to_end(buf) } - fn read_buf(&mut self, buf: io::BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, buf: io::BorrowedCursor<'_, u8>) -> io::Result<()> { self.0.read_buf(buf) } } @@ -253,7 +247,7 @@ impl io::Read for PipeReader { fn read_to_end(&mut self, buf: &mut Vec) -> io::Result { self.0.read_to_end(buf) } - fn read_buf(&mut self, buf: io::BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, buf: io::BorrowedCursor<'_, u8>) -> io::Result<()> { self.0.read_buf(buf) } } diff --git a/library/std/src/io/pipe/tests.rs b/library/std/src/io/pipe/tests.rs index f113b157459d3..2c2d35cc63d9e 100644 --- a/library/std/src/io/pipe/tests.rs +++ b/library/std/src/io/pipe/tests.rs @@ -1,7 +1,6 @@ use crate::io::{Read, Write, pipe}; #[test] -#[cfg(all(any(unix, windows), not(miri)))] fn pipe_creation_clone_and_rw() { let (rx, tx) = pipe().unwrap(); diff --git a/library/std/src/io/stdio.rs b/library/std/src/io/stdio.rs index 2d80fe49e80a7..b104ea69cd1fc 100644 --- a/library/std/src/io/stdio.rs +++ b/library/std/src/io/stdio.rs @@ -100,7 +100,7 @@ impl Read for StdinRaw { handle_ebadf(self.0.read(buf), || Ok(0)) } - fn read_buf(&mut self, buf: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, buf: BorrowedCursor<'_, u8>) -> io::Result<()> { handle_ebadf(self.0.read_buf(buf), || Ok(())) } @@ -120,7 +120,7 @@ impl Read for StdinRaw { handle_ebadf(self.0.read_exact(buf), || Err(io::Error::READ_EXACT_EOF)) } - fn read_buf_exact(&mut self, buf: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf_exact(&mut self, buf: BorrowedCursor<'_, u8>) -> io::Result<()> { if buf.capacity() == 0 { return Ok(()); } @@ -285,6 +285,7 @@ pub struct Stdin { /// ``` #[must_use = "if unused stdin will immediately unlock"] #[stable(feature = "rust1", since = "1.0.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "StdinLock")] pub struct StdinLock<'a> { inner: MutexGuard<'a, BufReader>, } @@ -446,7 +447,7 @@ impl Read for Stdin { fn read(&mut self, buf: &mut [u8]) -> io::Result { self.lock().read(buf) } - fn read_buf(&mut self, buf: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, buf: BorrowedCursor<'_, u8>) -> io::Result<()> { self.lock().read_buf(buf) } fn read_vectored(&mut self, bufs: &mut [IoSliceMut<'_>]) -> io::Result { @@ -465,7 +466,7 @@ impl Read for Stdin { fn read_exact(&mut self, buf: &mut [u8]) -> io::Result<()> { self.lock().read_exact(buf) } - fn read_buf_exact(&mut self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf_exact(&mut self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { self.lock().read_buf_exact(cursor) } } @@ -475,7 +476,7 @@ impl Read for &Stdin { fn read(&mut self, buf: &mut [u8]) -> io::Result { self.lock().read(buf) } - fn read_buf(&mut self, buf: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, buf: BorrowedCursor<'_, u8>) -> io::Result<()> { self.lock().read_buf(buf) } fn read_vectored(&mut self, bufs: &mut [IoSliceMut<'_>]) -> io::Result { @@ -494,7 +495,7 @@ impl Read for &Stdin { fn read_exact(&mut self, buf: &mut [u8]) -> io::Result<()> { self.lock().read_exact(buf) } - fn read_buf_exact(&mut self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf_exact(&mut self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { self.lock().read_buf_exact(cursor) } } @@ -513,7 +514,7 @@ impl Read for StdinLock<'_> { self.inner.read(buf) } - fn read_buf(&mut self, buf: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, buf: BorrowedCursor<'_, u8>) -> io::Result<()> { self.inner.read_buf(buf) } @@ -538,11 +539,13 @@ impl Read for StdinLock<'_> { self.inner.read_exact(buf) } - fn read_buf_exact(&mut self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf_exact(&mut self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { self.inner.read_buf_exact(cursor) } } +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] impl SpecReadByte for StdinLock<'_> { #[inline] fn spec_read_byte(&mut self) -> Option> { @@ -793,7 +796,7 @@ impl Write for Stdout { } #[inline] fn is_write_vectored(&self) -> bool { - io::Write::is_write_vectored(&&*self) + io::Write::is_write_vectored(&self) } fn flush(&mut self) -> io::Result<()> { (&*self).flush() @@ -1025,7 +1028,7 @@ impl Write for Stderr { } #[inline] fn is_write_vectored(&self) -> bool { - io::Write::is_write_vectored(&&*self) + io::Write::is_write_vectored(&self) } fn flush(&mut self) -> io::Result<()> { (&*self).flush() @@ -1194,7 +1197,7 @@ pub(crate) fn attempt_print_to_stderr(args: fmt::Arguments<'_>) { /// Trait to determine if a descriptor/handle refers to a terminal/tty. #[stable(feature = "is_terminal", since = "1.70.0")] -pub trait IsTerminal: crate::sealed::Sealed { +pub impl(crate) trait IsTerminal { /// Returns `true` if the descriptor/handle refers to a terminal/tty. /// /// On platforms where Rust does not know how to detect a terminal yet, this will return @@ -1242,16 +1245,13 @@ pub trait IsTerminal: crate::sealed::Sealed { /// /// [changes]: io#platform-specific-behavior /// [`Stdin`]: crate::io::Stdin - #[doc(alias = "isatty")] + #[doc(alias = "isatty", alias = "atty")] #[stable(feature = "is_terminal", since = "1.70.0")] fn is_terminal(&self) -> bool; } macro_rules! impl_is_terminal { ($($t:ty),*$(,)?) => {$( - #[unstable(feature = "sealed", issue = "none")] - impl crate::sealed::Sealed for $t {} - #[stable(feature = "is_terminal", since = "1.70.0")] impl IsTerminal for $t { #[inline] diff --git a/library/std/src/io/util.rs b/library/std/src/io/util.rs deleted file mode 100644 index 0410df3ef1a3e..0000000000000 --- a/library/std/src/io/util.rs +++ /dev/null @@ -1,448 +0,0 @@ -#![allow(missing_copy_implementations)] - -#[cfg(test)] -mod tests; - -use crate::fmt; -use crate::io::{ - self, BorrowedCursor, BufRead, IoSlice, IoSliceMut, Read, Seek, SeekFrom, SizeHint, Write, -}; - -/// `Empty` ignores any data written via [`Write`], and will always be empty -/// (returning zero bytes) when read via [`Read`]. -/// -/// This struct is generally created by calling [`empty()`]. Please -/// see the documentation of [`empty()`] for more details. -#[stable(feature = "rust1", since = "1.0.0")] -#[non_exhaustive] -#[derive(Copy, Clone, Debug, Default)] -pub struct Empty; - -/// Creates a value that is always at EOF for reads, and ignores all data written. -/// -/// All calls to [`write`] on the returned instance will return [`Ok(buf.len())`] -/// and the contents of the buffer will not be inspected. -/// -/// All calls to [`read`] from the returned reader will return [`Ok(0)`]. -/// -/// [`Ok(buf.len())`]: Ok -/// [`Ok(0)`]: Ok -/// -/// [`write`]: Write::write -/// [`read`]: Read::read -/// -/// # Examples -/// -/// ```rust -/// use std::io::{self, Write}; -/// -/// let buffer = vec![1, 2, 3, 5, 8]; -/// let num_bytes = io::empty().write(&buffer).unwrap(); -/// assert_eq!(num_bytes, 5); -/// ``` -/// -/// -/// ```rust -/// use std::io::{self, Read}; -/// -/// let mut buffer = String::new(); -/// io::empty().read_to_string(&mut buffer).unwrap(); -/// assert!(buffer.is_empty()); -/// ``` -#[must_use] -#[stable(feature = "rust1", since = "1.0.0")] -#[rustc_const_stable(feature = "const_io_structs", since = "1.79.0")] -pub const fn empty() -> Empty { - Empty -} - -#[stable(feature = "rust1", since = "1.0.0")] -impl Read for Empty { - #[inline] - fn read(&mut self, _buf: &mut [u8]) -> io::Result { - Ok(0) - } - - #[inline] - fn read_buf(&mut self, _cursor: BorrowedCursor<'_>) -> io::Result<()> { - Ok(()) - } - - #[inline] - fn read_vectored(&mut self, _bufs: &mut [IoSliceMut<'_>]) -> io::Result { - Ok(0) - } - - #[inline] - fn is_read_vectored(&self) -> bool { - // Do not force `Chain` or `Chain` to use vectored - // reads, unless the other reader is vectored. - false - } - - #[inline] - fn read_exact(&mut self, buf: &mut [u8]) -> io::Result<()> { - if !buf.is_empty() { Err(io::Error::READ_EXACT_EOF) } else { Ok(()) } - } - - #[inline] - fn read_buf_exact(&mut self, cursor: BorrowedCursor<'_>) -> io::Result<()> { - if cursor.capacity() != 0 { Err(io::Error::READ_EXACT_EOF) } else { Ok(()) } - } - - #[inline] - fn read_to_end(&mut self, _buf: &mut Vec) -> io::Result { - Ok(0) - } - - #[inline] - fn read_to_string(&mut self, _buf: &mut String) -> io::Result { - Ok(0) - } -} -#[stable(feature = "rust1", since = "1.0.0")] -impl BufRead for Empty { - #[inline] - fn fill_buf(&mut self) -> io::Result<&[u8]> { - Ok(&[]) - } - - #[inline] - fn consume(&mut self, _n: usize) {} - - #[inline] - fn has_data_left(&mut self) -> io::Result { - Ok(false) - } - - #[inline] - fn read_until(&mut self, _byte: u8, _buf: &mut Vec) -> io::Result { - Ok(0) - } - - #[inline] - fn skip_until(&mut self, _byte: u8) -> io::Result { - Ok(0) - } - - #[inline] - fn read_line(&mut self, _buf: &mut String) -> io::Result { - Ok(0) - } -} - -#[stable(feature = "empty_seek", since = "1.51.0")] -impl Seek for Empty { - #[inline] - fn seek(&mut self, _pos: SeekFrom) -> io::Result { - Ok(0) - } - - #[inline] - fn stream_len(&mut self) -> io::Result { - Ok(0) - } - - #[inline] - fn stream_position(&mut self) -> io::Result { - Ok(0) - } -} - -impl SizeHint for Empty { - #[inline] - fn upper_bound(&self) -> Option { - Some(0) - } -} - -#[stable(feature = "empty_write", since = "1.73.0")] -impl Write for Empty { - #[inline] - fn write(&mut self, buf: &[u8]) -> io::Result { - Ok(buf.len()) - } - - #[inline] - fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { - let total_len = bufs.iter().map(|b| b.len()).sum(); - Ok(total_len) - } - - #[inline] - fn is_write_vectored(&self) -> bool { - true - } - - #[inline] - fn write_all(&mut self, _buf: &[u8]) -> io::Result<()> { - Ok(()) - } - - #[inline] - fn write_all_vectored(&mut self, _bufs: &mut [IoSlice<'_>]) -> io::Result<()> { - Ok(()) - } - - #[inline] - fn write_fmt(&mut self, _args: fmt::Arguments<'_>) -> io::Result<()> { - Ok(()) - } - - #[inline] - fn flush(&mut self) -> io::Result<()> { - Ok(()) - } -} - -#[stable(feature = "empty_write", since = "1.73.0")] -impl Write for &Empty { - #[inline] - fn write(&mut self, buf: &[u8]) -> io::Result { - Ok(buf.len()) - } - - #[inline] - fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { - let total_len = bufs.iter().map(|b| b.len()).sum(); - Ok(total_len) - } - - #[inline] - fn is_write_vectored(&self) -> bool { - true - } - - #[inline] - fn write_all(&mut self, _buf: &[u8]) -> io::Result<()> { - Ok(()) - } - - #[inline] - fn write_all_vectored(&mut self, _bufs: &mut [IoSlice<'_>]) -> io::Result<()> { - Ok(()) - } - - #[inline] - fn write_fmt(&mut self, _args: fmt::Arguments<'_>) -> io::Result<()> { - Ok(()) - } - - #[inline] - fn flush(&mut self) -> io::Result<()> { - Ok(()) - } -} - -/// A reader which yields one byte over and over and over and over and over and... -/// -/// This struct is generally created by calling [`repeat()`]. Please -/// see the documentation of [`repeat()`] for more details. -#[stable(feature = "rust1", since = "1.0.0")] -pub struct Repeat { - byte: u8, -} - -/// Creates an instance of a reader that infinitely repeats one byte. -/// -/// All reads from this reader will succeed by filling the specified buffer with -/// the given byte. -/// -/// # Examples -/// -/// ``` -/// use std::io::{self, Read}; -/// -/// let mut buffer = [0; 3]; -/// io::repeat(0b101).read_exact(&mut buffer).unwrap(); -/// assert_eq!(buffer, [0b101, 0b101, 0b101]); -/// ``` -#[must_use] -#[stable(feature = "rust1", since = "1.0.0")] -#[rustc_const_stable(feature = "const_io_structs", since = "1.79.0")] -pub const fn repeat(byte: u8) -> Repeat { - Repeat { byte } -} - -#[stable(feature = "rust1", since = "1.0.0")] -impl Read for Repeat { - #[inline] - fn read(&mut self, buf: &mut [u8]) -> io::Result { - buf.fill(self.byte); - Ok(buf.len()) - } - - #[inline] - fn read_exact(&mut self, buf: &mut [u8]) -> io::Result<()> { - buf.fill(self.byte); - Ok(()) - } - - #[inline] - fn read_buf(&mut self, mut buf: BorrowedCursor<'_>) -> io::Result<()> { - // SAFETY: No uninit bytes are being written. - unsafe { buf.as_mut() }.write_filled(self.byte); - // SAFETY: the entire unfilled portion of buf has been initialized. - unsafe { buf.advance_unchecked(buf.capacity()) }; - Ok(()) - } - - #[inline] - fn read_buf_exact(&mut self, buf: BorrowedCursor<'_>) -> io::Result<()> { - self.read_buf(buf) - } - - /// This function is not supported by `io::Repeat`, because there's no end of its data - fn read_to_end(&mut self, _: &mut Vec) -> io::Result { - Err(io::Error::from(io::ErrorKind::OutOfMemory)) - } - - /// This function is not supported by `io::Repeat`, because there's no end of its data - fn read_to_string(&mut self, _: &mut String) -> io::Result { - Err(io::Error::from(io::ErrorKind::OutOfMemory)) - } - - #[inline] - fn read_vectored(&mut self, bufs: &mut [IoSliceMut<'_>]) -> io::Result { - let mut nwritten = 0; - for buf in bufs { - nwritten += self.read(buf)?; - } - Ok(nwritten) - } - - #[inline] - fn is_read_vectored(&self) -> bool { - true - } -} - -impl SizeHint for Repeat { - #[inline] - fn lower_bound(&self) -> usize { - usize::MAX - } - - #[inline] - fn upper_bound(&self) -> Option { - None - } -} - -#[stable(feature = "std_debug", since = "1.16.0")] -impl fmt::Debug for Repeat { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - f.debug_struct("Repeat").finish_non_exhaustive() - } -} - -/// A writer which will move data into the void. -/// -/// This struct is generally created by calling [`sink()`]. Please -/// see the documentation of [`sink()`] for more details. -#[stable(feature = "rust1", since = "1.0.0")] -#[non_exhaustive] -#[derive(Copy, Clone, Debug, Default)] -pub struct Sink; - -/// Creates an instance of a writer which will successfully consume all data. -/// -/// All calls to [`write`] on the returned instance will return [`Ok(buf.len())`] -/// and the contents of the buffer will not be inspected. -/// -/// [`write`]: Write::write -/// [`Ok(buf.len())`]: Ok -/// -/// # Examples -/// -/// ```rust -/// use std::io::{self, Write}; -/// -/// let buffer = vec![1, 2, 3, 5, 8]; -/// let num_bytes = io::sink().write(&buffer).unwrap(); -/// assert_eq!(num_bytes, 5); -/// ``` -#[must_use] -#[stable(feature = "rust1", since = "1.0.0")] -#[rustc_const_stable(feature = "const_io_structs", since = "1.79.0")] -pub const fn sink() -> Sink { - Sink -} - -#[stable(feature = "rust1", since = "1.0.0")] -impl Write for Sink { - #[inline] - fn write(&mut self, buf: &[u8]) -> io::Result { - Ok(buf.len()) - } - - #[inline] - fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { - let total_len = bufs.iter().map(|b| b.len()).sum(); - Ok(total_len) - } - - #[inline] - fn is_write_vectored(&self) -> bool { - true - } - - #[inline] - fn write_all(&mut self, _buf: &[u8]) -> io::Result<()> { - Ok(()) - } - - #[inline] - fn write_all_vectored(&mut self, _bufs: &mut [IoSlice<'_>]) -> io::Result<()> { - Ok(()) - } - - #[inline] - fn write_fmt(&mut self, _args: fmt::Arguments<'_>) -> io::Result<()> { - Ok(()) - } - - #[inline] - fn flush(&mut self) -> io::Result<()> { - Ok(()) - } -} - -#[stable(feature = "write_mt", since = "1.48.0")] -impl Write for &Sink { - #[inline] - fn write(&mut self, buf: &[u8]) -> io::Result { - Ok(buf.len()) - } - - #[inline] - fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { - let total_len = bufs.iter().map(|b| b.len()).sum(); - Ok(total_len) - } - - #[inline] - fn is_write_vectored(&self) -> bool { - true - } - - #[inline] - fn write_all(&mut self, _buf: &[u8]) -> io::Result<()> { - Ok(()) - } - - #[inline] - fn write_all_vectored(&mut self, _bufs: &mut [IoSlice<'_>]) -> io::Result<()> { - Ok(()) - } - - #[inline] - fn write_fmt(&mut self, _args: fmt::Arguments<'_>) -> io::Result<()> { - Ok(()) - } - - #[inline] - fn flush(&mut self) -> io::Result<()> { - Ok(()) - } -} diff --git a/library/std/src/lib.rs b/library/std/src/lib.rs index 724d4c68fb47d..10f15f8fa8393 100644 --- a/library/std/src/lib.rs +++ b/library/std/src/lib.rs @@ -94,8 +94,8 @@ //! pull-requests for your suggested changes. //! //! Contributions are appreciated! If you see a part of the docs that can be -//! improved, submit a PR, or chat with us first on [Zulip][rust-zulip] -//! #docs. +//! improved, submit a PR, or chat with us first on [Zulip][t-libs-zulip] +//! #t-libs. //! //! # A Tour of The Rust Standard Library //! @@ -209,7 +209,7 @@ //! [multithreading]: thread //! [other]: #what-is-in-the-standard-library-documentation //! [primitive types]: ../book/ch03-02-data-types.html -//! [rust-zulip]: https://rust-lang.zulipchat.com/ +//! [t-libs-zulip]: https://rust-lang.zulipchat.com/#narrow/channel/219381-t-libs/ //! [array]: prim@array //! [slice]: prim@slice @@ -245,7 +245,7 @@ #![allow(explicit_outlives_requirements)] #![allow(unused_lifetimes)] #![allow(internal_features)] -#![deny(fuzzy_provenance_casts)] +#![deny(implicit_provenance_casts)] #![deny(unsafe_op_in_unsafe_fn)] #![allow(rustdoc::redundant_explicit_links)] #![warn(rustdoc::unescaped_backticks)] @@ -255,7 +255,10 @@ #![allow(unused_features)] // // Features: -#![cfg_attr(test, feature(internal_output_capture, print_internals, update_panic_count, rt))] +#![cfg_attr( + test, + feature(internal_output_capture, print_internals, super_let, update_panic_count, rt) +)] #![cfg_attr( all(target_vendor = "fortanix", target_env = "sgx"), feature(slice_index_methods, coerce_unsized, sgx_platform) @@ -274,31 +277,28 @@ #![feature(asm_experimental_arch)] #![feature(autodiff)] #![feature(cfg_sanitizer_cfi)] +#![feature(cfg_target_has_threads)] #![feature(cfg_target_thread_local)] #![feature(cfi_encoding)] -#![feature(const_default)] #![feature(const_trait_impl)] -#![feature(core_float_math)] #![feature(decl_macro)] #![feature(deprecated_suggestion)] +#![feature(diagnostic_on_move)] #![feature(doc_cfg)] #![feature(doc_masked)] #![feature(doc_notable_trait)] #![feature(dropck_eyepatch)] +#![feature(exact_div)] #![feature(f16)] #![feature(f128)] #![feature(ffi_const)] -#![feature(formatting_options)] -#![feature(funnel_shifts)] -#![feature(if_let_guard)] +#![feature(gpu_offload)] +#![feature(impl_restriction)] #![feature(intra_doc_pointers)] -#![feature(iter_advance_by)] -#![feature(iter_next_chunk)] #![feature(lang_items)] #![feature(link_cfg)] #![feature(linkage)] #![feature(macro_metavar_expr_concat)] -#![feature(maybe_uninit_fill)] #![feature(min_specialization)] #![feature(must_not_suspend)] #![feature(needs_panic_runtime)] @@ -311,25 +311,34 @@ #![feature(staged_api)] #![feature(stmt_expr_attributes)] #![feature(strict_provenance_lints)] -#![feature(target_feature_inline_always)] #![feature(thread_local)] #![feature(try_blocks)] #![feature(try_trait_v2)] #![feature(type_alias_impl_trait)] +#![feature(unwrap_infallible)] // tidy-alphabetical-end // // Library features (core): // tidy-alphabetical-start +#![feature(borrowed_buf_init)] #![feature(bstr)] #![feature(bstr_internals)] +#![feature(c_size_t)] +#![feature(can_vector)] #![feature(cast_maybe_uninit)] -#![feature(cfg_select)] #![feature(char_internals)] #![feature(clone_to_uninit)] +#![feature(const_clone)] #![feature(const_convert)] +#![feature(const_default)] +#![feature(core_float_math)] #![feature(core_intrinsics)] +#![feature(core_io)] #![feature(core_io_borrowed_buf)] +#![feature(core_io_internals)] #![feature(cstr_display)] +#![feature(cursor_split)] +#![feature(derive_const)] #![feature(drop_guard)] #![feature(duration_constants)] #![feature(error_generic_member_access)] @@ -337,26 +346,44 @@ #![feature(exact_size_is_empty)] #![feature(exclusive_wrapper)] #![feature(extend_one)] -#![feature(float_algebraic)] #![feature(float_gamma)] #![feature(float_minimum_maximum)] #![feature(fmt_internals)] -#![feature(fn_ptr_trait)] +#![feature(fn_static)] +#![feature(formatting_options)] +#![feature(funnel_shifts)] #![feature(generic_atomic)] +#![feature(hash_map_internals)] +#![feature(hash_map_macro)] #![feature(hasher_prefixfree_extras)] #![feature(hashmap_internals)] #![feature(hint_must_use)] #![feature(int_from_ascii)] +#![feature(io_error_inprogress)] +#![feature(io_error_input_output_error)] +#![feature(io_error_more)] +#![feature(io_error_too_many_open_files)] +#![feature(io_error_uncategorized)] +#![feature(io_slice_as_bytes)] #![feature(ip)] +#![feature(iter_advance_by)] +#![feature(iter_next_chunk)] +#![feature(maybe_dangling)] #![feature(maybe_uninit_array_assume_init)] +#![feature(maybe_uninit_fill)] #![feature(panic_can_unwind)] #![feature(panic_internals)] #![feature(pin_coerce_unsized_trait)] #![feature(pointer_is_aligned_to)] #![feature(portable_simd)] #![feature(ptr_as_uninit)] +#![feature(ptr_cast_slice)] #![feature(ptr_mask)] #![feature(random)] +#![feature(raw_os_error_ty)] +#![feature(seek_io_take_position)] +#![feature(seek_stream_len)] +#![feature(share_trait)] #![feature(slice_internals)] #![feature(slice_ptr_get)] #![feature(slice_range)] @@ -366,15 +393,20 @@ #![feature(sync_unsafe_cell)] #![feature(temporary_niche_types)] #![feature(ub_checks)] +#![feature(uint_carryless_mul)] #![feature(used_with_arg)] +#![feature(write_all_vectored)] // tidy-alphabetical-end // // Library features (alloc): // tidy-alphabetical-start +#![feature(alloc_io)] #![feature(allocator_api)] +#![feature(buf_read_has_data_left)] #![feature(clone_from_ref)] #![feature(get_mut_unchecked)] #![feature(map_try_insert)] +#![feature(read_buf)] #![feature(slice_concat_trait)] #![feature(thin_box)] #![feature(try_reserve_kind)] @@ -395,9 +427,7 @@ // // Only for re-exporting: // tidy-alphabetical-start -#![feature(assert_matches)] #![feature(async_iterator)] -#![feature(c_variadic)] #![feature(cfg_accessible)] #![feature(cfg_eval)] #![feature(concat_bytes)] @@ -418,6 +448,13 @@ // tidy-alphabetical-end // #![default_lib_allocator] +// Removed features +#![unstable_removed( + feature = "concat_idents", + reason = "Replaced by the macro_metavar_expr_concat feature", + link = "https://github.com/rust-lang/rust/issues/29599#issuecomment-2986866250", + since = "1.90.0" +)] // The Rust prelude // The compiler expects the prelude definition to be defined before its use statement. @@ -471,9 +508,7 @@ extern crate std as realstd; // The standard macros that are not built-in to the compiler. #[macro_use] -#[doc(hidden)] -#[unstable(feature = "std_internals", issue = "none")] -pub mod macros; +mod macros; // The runtime entry point and a few unstable public functions used by the // compiler @@ -498,29 +533,31 @@ pub use core::cmp; pub use core::convert; #[stable(feature = "rust1", since = "1.0.0")] pub use core::default; +#[unstable(feature = "field_projections", issue = "145383")] +pub use core::field; #[stable(feature = "futures_api", since = "1.36.0")] pub use core::future; #[stable(feature = "core_hint", since = "1.27.0")] pub use core::hint; #[stable(feature = "rust1", since = "1.0.0")] -#[allow(deprecated, deprecated_in_future)] +#[allow(deprecated, deprecated_in_future, clippy::legacy_numeric_constants)] pub use core::i8; #[stable(feature = "rust1", since = "1.0.0")] -#[allow(deprecated, deprecated_in_future)] +#[allow(deprecated, deprecated_in_future, clippy::legacy_numeric_constants)] pub use core::i16; #[stable(feature = "rust1", since = "1.0.0")] -#[allow(deprecated, deprecated_in_future)] +#[allow(deprecated, deprecated_in_future, clippy::legacy_numeric_constants)] pub use core::i32; #[stable(feature = "rust1", since = "1.0.0")] -#[allow(deprecated, deprecated_in_future)] +#[allow(deprecated, deprecated_in_future, clippy::legacy_numeric_constants)] pub use core::i64; #[stable(feature = "i128", since = "1.26.0")] -#[allow(deprecated, deprecated_in_future)] +#[allow(deprecated, deprecated_in_future, clippy::legacy_numeric_constants)] pub use core::i128; #[stable(feature = "rust1", since = "1.0.0")] pub use core::intrinsics; #[stable(feature = "rust1", since = "1.0.0")] -#[allow(deprecated, deprecated_in_future)] +#[allow(deprecated, deprecated_in_future, clippy::legacy_numeric_constants)] pub use core::isize; #[stable(feature = "rust1", since = "1.0.0")] pub use core::iter; @@ -536,29 +573,29 @@ pub use core::option; pub use core::pin; #[stable(feature = "rust1", since = "1.0.0")] pub use core::ptr; -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "1.96.0")] pub use core::range; #[stable(feature = "rust1", since = "1.0.0")] pub use core::result; #[stable(feature = "rust1", since = "1.0.0")] -#[allow(deprecated, deprecated_in_future)] +#[allow(deprecated, deprecated_in_future, clippy::legacy_numeric_constants)] pub use core::u8; #[stable(feature = "rust1", since = "1.0.0")] -#[allow(deprecated, deprecated_in_future)] +#[allow(deprecated, deprecated_in_future, clippy::legacy_numeric_constants)] pub use core::u16; #[stable(feature = "rust1", since = "1.0.0")] -#[allow(deprecated, deprecated_in_future)] +#[allow(deprecated, deprecated_in_future, clippy::legacy_numeric_constants)] pub use core::u32; #[stable(feature = "rust1", since = "1.0.0")] -#[allow(deprecated, deprecated_in_future)] +#[allow(deprecated, deprecated_in_future, clippy::legacy_numeric_constants)] pub use core::u64; #[stable(feature = "i128", since = "1.26.0")] -#[allow(deprecated, deprecated_in_future)] +#[allow(deprecated, deprecated_in_future, clippy::legacy_numeric_constants)] pub use core::u128; #[unstable(feature = "unsafe_binders", issue = "130516")] pub use core::unsafe_binder; #[stable(feature = "rust1", since = "1.0.0")] -#[allow(deprecated, deprecated_in_future)] +#[allow(deprecated, deprecated_in_future, clippy::legacy_numeric_constants)] pub use core::usize; #[stable(feature = "rust1", since = "1.0.0")] @@ -614,6 +651,8 @@ pub mod process; pub mod random; pub mod sync; pub mod time; +#[unstable(feature = "view_type_macro", issue = "155938")] +pub mod view; // Pull in `std_float` crate into std. The contents of // `std_float` are in a different repository: rust-lang/portable-simd. @@ -635,12 +674,18 @@ pub mod simd { } #[unstable(feature = "autodiff", issue = "124509")] -/// This module provides support for automatic differentiation. +#[doc = include_str!("../../core/src/autodiff.md")] pub mod autodiff { /// This macro handles automatic differentiation. pub use core::autodiff::{autodiff_forward, autodiff_reverse}; } +#[unstable(feature = "gpu_offload", issue = "131513")] +#[doc = include_str!("../../core/src/offload.md")] +pub mod offload { + pub use core::offload::{offload, offload_kernel}; +} + #[stable(feature = "futures_api", since = "1.36.0")] pub mod task { //! Types and Traits for working with asynchronous tasks. @@ -694,10 +739,11 @@ pub mod alloc; mod panicking; #[path = "../../backtrace/src/lib.rs"] -#[allow(dead_code, unused_attributes, fuzzy_provenance_casts, unsafe_op_in_unsafe_fn)] +#[allow(dead_code, unused_attributes, implicit_provenance_casts, unsafe_op_in_unsafe_fn)] +#[allow(clippy::len_zero, clippy::needless_borrow)] // FIXME mod backtrace_rs; -#[unstable(feature = "cfg_select", issue = "115585")] +#[stable(feature = "cfg_select", since = "1.95.0")] pub use core::cfg_select; #[unstable( feature = "concat_bytes", @@ -705,6 +751,8 @@ pub use core::cfg_select; reason = "`concat_bytes` is not stable enough for use and is subject to change" )] pub use core::concat_bytes; +#[unstable(feature = "derive_macro_global_path", issue = "154645")] +pub use core::derive; #[stable(feature = "matches_macro", since = "1.42.0")] #[allow(deprecated, deprecated_in_future)] pub use core::matches; @@ -727,7 +775,7 @@ pub use core::{ assert_eq, assert_ne, debug_assert, debug_assert_eq, debug_assert_ne, r#try, unimplemented, unreachable, write, writeln, }; -#[unstable(feature = "assert_matches", issue = "82775")] +#[stable(feature = "assert_matches", since = "1.96.0")] pub use core::{assert_matches, debug_assert_matches}; // Re-export unstable derive macro defined through core. @@ -738,15 +786,23 @@ pub mod from { pub use core::from::From; } +// We include the following files here *again* (they are already included in libcore) +// so that they show up in search results for the std crate, and to avoid breaking +// existing links: + +// documentation for built-in attributes. Using `include!` because rustdoc +// only looks for these modules at the crate level. +include!("../../core/src/attribute_docs.rs"); + // Include a number of private modules that exist solely to provide -// the rustdoc documentation for primitive types. Using `include!` +// the rustdoc documentation for the existing keywords. Using `include!` // because rustdoc only looks for these modules at the crate level. -include!("../../core/src/primitive_docs.rs"); +include!("../../core/src/keyword_docs.rs"); // Include a number of private modules that exist solely to provide -// the rustdoc documentation for the existing keywords. Using `include!` +// the rustdoc documentation for primitive types. Using `include!` // because rustdoc only looks for these modules at the crate level. -include!("keyword_docs.rs"); +include!("../../core/src/primitive_docs.rs"); // This is required to avoid an unstable error when `restricted-std` is not // enabled. The use of #![feature(restricted_std)] in rustc-std-workspace-std @@ -754,14 +810,6 @@ include!("keyword_docs.rs"); #[unstable(feature = "restricted_std", issue = "none")] mod __restricted_std_workaround {} -mod sealed { - /// This trait being unreachable from outside the crate - /// prevents outside implementations of our extension traits. - /// This allows adding more trait methods in the future. - #[unstable(feature = "sealed", issue = "none")] - pub trait Sealed {} -} - #[cfg(test)] #[allow(dead_code)] // Not used in all configurations. pub(crate) mod test_helpers; diff --git a/library/std/src/macros.rs b/library/std/src/macros.rs index 0bb14552432d5..ea574fc4146e7 100644 --- a/library/std/src/macros.rs +++ b/library/std/src/macros.rs @@ -3,7 +3,10 @@ //! This module contains a set of macros which are exported from the standard //! library. Each macro is available for use when linking against the standard //! library. -// ignore-tidy-dbg +// ignore-tidy-file-dbg + +#[cfg(test)] +mod tests; #[doc = include_str!("../../core/src/macros/panic.md")] #[macro_export] @@ -79,6 +82,7 @@ macro_rules! panic { #[stable(feature = "rust1", since = "1.0.0")] #[cfg_attr(not(test), rustc_diagnostic_item = "print_macro")] #[allow_internal_unstable(print_internals)] +#[rustc_diagnostic_opaque] macro_rules! print { ($($arg:tt)*) => {{ $crate::io::_print($crate::format_args!($($arg)*)); @@ -135,6 +139,7 @@ macro_rules! print { #[stable(feature = "rust1", since = "1.0.0")] #[cfg_attr(not(test), rustc_diagnostic_item = "println_macro")] #[allow_internal_unstable(print_internals, format_args_nl)] +#[rustc_diagnostic_opaque] macro_rules! println { () => { $crate::print!("\n") @@ -347,70 +352,112 @@ macro_rules! eprintln { /// [`debug!`]: https://docs.rs/log/*/log/macro.debug.html /// [`log`]: https://crates.io/crates/log #[macro_export] -#[allow_internal_unstable(std_internals)] #[cfg_attr(not(test), rustc_diagnostic_item = "dbg_macro")] #[stable(feature = "dbg_macro", since = "1.32.0")] +#[rustc_diagnostic_opaque] macro_rules! dbg { + // NOTE: We cannot use `concat!` to make a static string as a format argument + // of `eprintln!` because `file!` could contain a `{` or + // `$val` expression could be a block (`{ .. }`), in which case the `eprintln!` + // will be malformed. () => { $crate::eprintln!("[{}:{}:{}]", $crate::file!(), $crate::line!(), $crate::column!()) }; + ($val:expr $(,)?) => { + // Use of `match` here is intentional because it affects the lifetimes + // of temporaries - https://stackoverflow.com/a/48732525/1063961 + match $val { + tmp => { + $crate::eprintln!("[{}:{}:{}] {} = {:#?}", + $crate::file!(), + $crate::line!(), + $crate::column!(), + $crate::stringify!($val), + // The `&T: Debug` check happens here (not in the format literal desugaring) + // to avoid format literal related messages and suggestions. + &&tmp as &dyn $crate::fmt::Debug, + ); + tmp + } + } + }; ($($val:expr),+ $(,)?) => { - $crate::macros::dbg_internal!(() () ($($val),+)) + ($($crate::dbg!($val)),+,) }; } -/// Internal macro that processes a list of expressions and produces a chain of -/// nested `match`es, one for each expression, before finally calling `eprint!` -/// with the collected information and returning all the evaluated expressions -/// in a tuple. -/// -/// E.g. `dbg_internal!(() () (1, 2))` expands into -/// ```rust, ignore -/// match 1 { -/// tmp_1 => match 2 { -/// tmp_2 => { -/// eprint!("...", &tmp_1, &tmp_2, /* some other arguments */); -/// (tmp_1, tmp_2) -/// } -/// } -/// } +#[doc(hidden)] +#[macro_export] +#[allow_internal_unstable(hash_map_internals)] +#[unstable(feature = "hash_map_internals", issue = "none")] +macro_rules! repetition_utils { + (@count $($tokens:tt),*) => {{ + [$($crate::repetition_utils!(@replace $tokens => ())),*].len() + }}; + + (@replace $x:tt => $y:tt) => { $y } +} + +/// Creates a [`HashMap`] containing the arguments. +/// +/// `hash_map!` allows specifying the entries that make +/// up the [`HashMap`] where the key and value are separated by a `=>`. +/// +/// The entries are separated by commas with a trailing comma being allowed. +/// +/// It is semantically equivalent to using repeated [`HashMap::insert`] +/// on a newly created hashmap. +/// +/// `hash_map!` will attempt to avoid repeated reallocations by +/// using [`HashMap::with_capacity`]. +/// +/// # Examples +/// +/// ```rust +/// #![feature(hash_map_macro)] +/// use std::hash_map; +/// +/// let map = hash_map! { +/// "key" => "value", +/// "key1" => "value1" +/// }; +/// +/// assert_eq!(map.get("key"), Some(&"value")); +/// assert_eq!(map.get("key1"), Some(&"value1")); +/// assert!(map.get("brrrrrrooooommm").is_none()); /// ``` /// -/// This is necessary so that `dbg!` outputs don't get torn, see #136703. -#[doc(hidden)] -#[rustc_macro_transparency = "semiopaque"] -pub macro dbg_internal { - (($($piece:literal),+) ($($processed:expr => $bound:expr),+) ()) => {{ - $crate::eprint!( - $crate::concat!($($piece),+), - $( - $crate::stringify!($processed), - // The `&T: Debug` check happens here (not in the format literal desugaring) - // to avoid format literal related messages and suggestions. - &&$bound as &dyn $crate::fmt::Debug - ),+, - // The location returned here is that of the macro invocation, so - // it will be the same for all expressions. Thus, label these - // arguments so that they can be reused in every piece of the - // formatting template. - file=$crate::file!(), - line=$crate::line!(), - column=$crate::column!() +/// And with a trailing comma +/// +///```rust +/// #![feature(hash_map_macro)] +/// use std::hash_map; +/// +/// let map = hash_map! { +/// "key" => "value", // notice the , +/// }; +/// +/// assert_eq!(map.get("key"), Some(&"value")); +/// ``` +/// +/// The key and value are moved into the HashMap. +/// +/// [`HashMap`]: crate::collections::HashMap +/// [`HashMap::insert`]: crate::collections::HashMap::insert +/// [`HashMap::with_capacity`]: crate::collections::HashMap::with_capacity +#[macro_export] +#[allow_internal_unstable(hash_map_internals)] +#[unstable(feature = "hash_map_macro", issue = "144032")] +macro_rules! hash_map { + () => {{ + $crate::collections::HashMap::new() + }}; + + ( $( $key:expr => $value:expr ),* $(,)? ) => {{ + let mut map = $crate::collections::HashMap::with_capacity( + const { $crate::repetition_utils!(@count $($key),*) } ); - // Comma separate the variables only when necessary so that this will - // not yield a tuple for a single expression, but rather just parenthesize - // the expression. - ($($bound),+) - }}, - (($($piece:literal),*) ($($processed:expr => $bound:expr),*) ($val:expr $(,$rest:expr)*)) => { - // Use of `match` here is intentional because it affects the lifetimes - // of temporaries - https://stackoverflow.com/a/48732525/1063961 - match $val { - tmp => $crate::macros::dbg_internal!( - ($($piece,)* "[{file}:{line}:{column}] {} = {:#?}\n") - ($($processed => $bound,)* $val => tmp) - ($($rest),*) - ), - } - }, + $( map.insert($key, $value); )* + map + }} } diff --git a/library/std/src/macros/tests.rs b/library/std/src/macros/tests.rs new file mode 100644 index 0000000000000..c2ead4655d314 --- /dev/null +++ b/library/std/src/macros/tests.rs @@ -0,0 +1,65 @@ +use core::fmt::Debug; + +/// Test for : +/// `dbg!` shouldn't drop arguments' temporaries. +#[test] +fn no_dropping_temps() { + fn temp() {} + + *dbg!(&temp()); + *dbg!(&temp(), 1).0; + *dbg!(0, &temp()).1; + *dbg!(0, &temp(), 2).1; +} + +/// Test for : +/// `dbg!` shouldn't create a temporary that lives past its invocation. +#[test] +fn no_leaking_internal_temps_from_dbg() { + #[derive(Debug)] + struct Foo; + + #[derive(Debug)] + struct Bar<'a>(#[allow(unused)] &'a Foo); + impl Drop for Bar<'_> { + fn drop(&mut self) {} + } + + let foo = Foo; + let bar = Bar(&foo); + // If `dbg!` creates a `(Bar<'_>,)` temporary that lasts past its expansion, this will fail + // to compile, because it will be dropped after `foo`, which it borrows from. The tuple + // mimics the drop order of block tail expressions before Rust 2024: first the result of `dbg!` + // is dropped, then `foo`, then any temporaries left over from `dbg!` are dropped, if present. + (drop(dbg!(bar)), drop(foo)); +} + +/// Test for : +/// `dbg!` shouldn't create a temporary that borrowck thinks can live past its invocation on a false +/// unwind path. +#[test] +fn no_leaking_internal_temps_from_dbg_even_on_false_unwind() { + #[derive(Debug)] + struct Foo; + impl Drop for Foo { + fn drop(&mut self) {} + } + + #[derive(Debug)] + struct Bar<'a>(#[allow(unused)] &'a Foo); + impl Drop for Bar<'_> { + fn drop(&mut self) {} + } + + { + let foo = Foo; + let bar = Bar(&foo); + // The temporaries of this `super let`'s scrutinee will outlive `bar` and `foo`, emulating + // the drop order of block tail expressions before Rust 2024. If borrowck thinks that a + // panic from moving `bar` is possible and that a `Bar<'_>`-containing temporary lives past + // the end of the block because of that, this will fail to compile. Because `Foo` implements + // `Drop`, it's an error for `foo` to be dropped before such a temporary when unwinding; + // otherwise, `foo` would just live to the end of the stack frame when unwinding. + super let _ = drop(dbg!(bar)); + } +} diff --git a/library/std/src/net/ip_addr.rs b/library/std/src/net/ip_addr.rs index 7262899b3bbbe..6bd78de910fec 100644 --- a/library/std/src/net/ip_addr.rs +++ b/library/std/src/net/ip_addr.rs @@ -1,5 +1,12 @@ // Tests for this module -#[cfg(all(test, not(any(target_os = "emscripten", all(target_os = "wasi", target_env = "p1")))))] +#[cfg(all( + test, + not(any( + target_os = "emscripten", + all(target_os = "wasi", target_env = "p1"), + target_os = "l4re" + )) +))] mod tests; #[stable(feature = "ip_addr", since = "1.7.0")] diff --git a/library/std/src/net/ip_addr/tests.rs b/library/std/src/net/ip_addr/tests.rs index 7bed6f8a0f523..666146319d161 100644 --- a/library/std/src/net/ip_addr/tests.rs +++ b/library/std/src/net/ip_addr/tests.rs @@ -1,5 +1,5 @@ use crate::net::Ipv4Addr; -use crate::net::test::{sa4, tsa}; +use crate::net::tests::{sa4, tsa}; #[test] fn to_socket_addr_socketaddr() { diff --git a/library/std/src/net/mod.rs b/library/std/src/net/mod.rs index 3e4447eb33f2a..1b1096925dd4a 100644 --- a/library/std/src/net/mod.rs +++ b/library/std/src/net/mod.rs @@ -42,8 +42,8 @@ mod hostname; mod ip_addr; mod socket_addr; mod tcp; -#[cfg(test)] -pub(crate) mod test; +#[cfg(all(test, not(target_os = "l4re")))] +pub(crate) mod tests; mod udp; /// Possible values which can be passed to the [`TcpStream::shutdown`] method. diff --git a/library/std/src/net/socket_addr.rs b/library/std/src/net/socket_addr.rs index 8214ad381f1f7..6aa625d66a363 100644 --- a/library/std/src/net/socket_addr.rs +++ b/library/std/src/net/socket_addr.rs @@ -1,5 +1,12 @@ // Tests for this module -#[cfg(all(test, not(any(target_os = "emscripten", all(target_os = "wasi", target_env = "p1")))))] +#[cfg(all( + test, + not(any( + target_os = "emscripten", + all(target_os = "wasi", target_env = "p1"), + target_os = "l4re" + )) +))] mod tests; #[stable(feature = "rust1", since = "1.0.0")] @@ -189,11 +196,6 @@ impl ToSocketAddrs for (Ipv6Addr, u16) { } } -fn lookup_host(host: &str, port: u16) -> io::Result> { - let addrs = crate::sys::net::lookup_host(host, port)?; - Ok(Vec::from_iter(addrs).into_iter()) -} - #[stable(feature = "rust1", since = "1.0.0")] impl ToSocketAddrs for (&str, u16) { type Iter = vec::IntoIter; @@ -207,7 +209,7 @@ impl ToSocketAddrs for (&str, u16) { } // Otherwise, make the system look it up. - lookup_host(host, port) + crate::sys::net::lookup_host(host, port).map(|addrs| Vec::from_iter(addrs).into_iter()) } } @@ -229,16 +231,8 @@ impl ToSocketAddrs for str { return Ok(vec![addr].into_iter()); } - // Otherwise, split the string by ':' and convert the second part to u16... - let Some((host, port_str)) = self.rsplit_once(':') else { - return Err(io::const_error!(io::ErrorKind::InvalidInput, "invalid socket address")); - }; - let Ok(port) = port_str.parse::() else { - return Err(io::const_error!(io::ErrorKind::InvalidInput, "invalid port value")); - }; - - // ... and make the system look up the host. - lookup_host(host, port) + // Otherwise, make the system look it up. + crate::sys::net::lookup_host_string(self).map(|addrs| Vec::from_iter(addrs).into_iter()) } } @@ -263,6 +257,6 @@ impl ToSocketAddrs for &T { impl ToSocketAddrs for String { type Iter = vec::IntoIter; fn to_socket_addrs(&self) -> io::Result> { - (&**self).to_socket_addrs() + (**self).to_socket_addrs() } } diff --git a/library/std/src/net/socket_addr/tests.rs b/library/std/src/net/socket_addr/tests.rs index 6a065cfba2105..2f3e3add5c22d 100644 --- a/library/std/src/net/socket_addr/tests.rs +++ b/library/std/src/net/socket_addr/tests.rs @@ -1,4 +1,4 @@ -use crate::net::test::{sa4, sa6, tsa}; +use crate::net::tests::{sa4, sa6, tsa}; use crate::net::*; #[test] diff --git a/library/std/src/net/tcp.rs b/library/std/src/net/tcp.rs index dac568e419f3f..00f802e5d9155 100644 --- a/library/std/src/net/tcp.rs +++ b/library/std/src/net/tcp.rs @@ -7,6 +7,7 @@ all(target_os = "wasi", target_env = "p1"), target_os = "xous", target_os = "trusty", + target_os = "l4re", )) ))] mod tests; @@ -239,7 +240,7 @@ impl TcpStream { /// /// let stream = TcpStream::connect("127.0.0.1:8080") /// .expect("Couldn't connect to the server..."); - /// stream.shutdown(Shutdown::Both).expect("shutdown call failed"); + /// stream.shutdown(Shutdown::Both).expect("shutdown should succeed"); /// ``` #[stable(feature = "rust1", since = "1.0.0")] pub fn shutdown(&self, how: Shutdown) -> io::Result<()> { @@ -260,7 +261,7 @@ impl TcpStream { /// /// let stream = TcpStream::connect("127.0.0.1:8080") /// .expect("Couldn't connect to the server..."); - /// let stream_clone = stream.try_clone().expect("clone failed..."); + /// let stream_clone = stream.try_clone().expect("clone should succeed"); /// ``` #[stable(feature = "rust1", since = "1.0.0")] pub fn try_clone(&self) -> io::Result { @@ -290,7 +291,7 @@ impl TcpStream { /// /// let stream = TcpStream::connect("127.0.0.1:8080") /// .expect("Couldn't connect to the server..."); - /// stream.set_read_timeout(None).expect("set_read_timeout call failed"); + /// stream.set_read_timeout(None).expect("set_read_timeout should succeed"); /// ``` /// /// An [`Err`] is returned if the zero [`Duration`] is passed to this @@ -334,7 +335,7 @@ impl TcpStream { /// /// let stream = TcpStream::connect("127.0.0.1:8080") /// .expect("Couldn't connect to the server..."); - /// stream.set_write_timeout(None).expect("set_write_timeout call failed"); + /// stream.set_write_timeout(None).expect("set_write_timeout should succeed"); /// ``` /// /// An [`Err`] is returned if the zero [`Duration`] is passed to this @@ -372,7 +373,7 @@ impl TcpStream { /// /// let stream = TcpStream::connect("127.0.0.1:8080") /// .expect("Couldn't connect to the server..."); - /// stream.set_read_timeout(None).expect("set_read_timeout call failed"); + /// stream.set_read_timeout(None).expect("set_read_timeout should succeed"); /// assert_eq!(stream.read_timeout().unwrap(), None); /// ``` #[stable(feature = "socket_timeout", since = "1.4.0")] @@ -397,7 +398,7 @@ impl TcpStream { /// /// let stream = TcpStream::connect("127.0.0.1:8080") /// .expect("Couldn't connect to the server..."); - /// stream.set_write_timeout(None).expect("set_write_timeout call failed"); + /// stream.set_write_timeout(None).expect("set_write_timeout should succeed"); /// assert_eq!(stream.write_timeout().unwrap(), None); /// ``` #[stable(feature = "socket_timeout", since = "1.4.0")] @@ -420,7 +421,7 @@ impl TcpStream { /// let stream = TcpStream::connect("127.0.0.1:8000") /// .expect("Couldn't connect to the server..."); /// let mut buf = [0; 10]; - /// let len = stream.peek(&mut buf).expect("peek failed"); + /// let len = stream.peek(&mut buf).expect("peek should succeed"); /// ``` #[stable(feature = "peek", since = "1.18.0")] pub fn peek(&self, buf: &mut [u8]) -> io::Result { @@ -445,7 +446,7 @@ impl TcpStream { /// /// let stream = TcpStream::connect("127.0.0.1:8080") /// .expect("Couldn't connect to the server..."); - /// stream.set_linger(Some(Duration::from_secs(0))).expect("set_linger call failed"); + /// stream.set_linger(Some(Duration::from_secs(0))).expect("set_linger should succeed"); /// ``` #[unstable(feature = "tcp_linger", issue = "88494")] pub fn set_linger(&self, linger: Option) -> io::Result<()> { @@ -466,7 +467,7 @@ impl TcpStream { /// /// let stream = TcpStream::connect("127.0.0.1:8080") /// .expect("Couldn't connect to the server..."); - /// stream.set_linger(Some(Duration::from_secs(0))).expect("set_linger call failed"); + /// stream.set_linger(Some(Duration::from_secs(0))).expect("set_linger should succeed"); /// assert_eq!(stream.linger().unwrap(), Some(Duration::from_secs(0))); /// ``` #[unstable(feature = "tcp_linger", issue = "88494")] @@ -474,6 +475,57 @@ impl TcpStream { self.0.linger() } + /// Sets the value of the `SO_KEEPALIVE` option on this socket. + /// + /// If set to `true`, the operating system will periodically send keepalive + /// probes on an idle connection to verify that the remote peer is still + /// reachable. If the peer fails to respond after a system-determined number + /// of probes, the connection is considered broken and subsequent I/O calls + /// will return an error. + /// + /// This is useful for detecting dead peers on long-lived connections where + /// no application-level traffic is exchanged, such as database or SSH + /// connections. + /// + /// The timing and frequency of keepalive probes are controlled by + /// system-level settings and are not configured by this method alone. + /// + /// # Examples + /// + /// ```no_run + /// #![feature(tcp_keepalive)] + /// + /// use std::net::TcpStream; + /// + /// let stream = TcpStream::connect("127.0.0.1:8080") + /// .expect("Couldn't connect to the server..."); + /// stream.set_keepalive(true).expect("set_keepalive should succeed"); + #[unstable(feature = "tcp_keepalive", issue = "155889")] + pub fn set_keepalive(&self, keepalive: bool) -> io::Result<()> { + self.0.set_keepalive(keepalive) + } + + /// Gets the value of the `SO_KEEPALIVE` option on this socket. + /// + /// For more information about this option, see [`TcpStream::set_keepalive`]. + /// + /// # Examples + /// + /// ```no_run + /// #![feature(tcp_keepalive)] + /// + /// use std::net::TcpStream; + /// + /// let stream = TcpStream::connect("127.0.0.1:8080") + /// .expect("Couldn't connect to the server..."); + /// stream.set_keepalive(true).expect("set_keepalive should succeed"); + /// assert_eq!(stream.keepalive().unwrap_or(false), true); + /// ``` + #[unstable(feature = "tcp_keepalive", issue = "155889")] + pub fn keepalive(&self) -> io::Result { + self.0.keepalive() + } + /// Sets the value of the `TCP_NODELAY` option on this socket. /// /// If set, this option disables the Nagle algorithm. This means that @@ -489,7 +541,7 @@ impl TcpStream { /// /// let stream = TcpStream::connect("127.0.0.1:8080") /// .expect("Couldn't connect to the server..."); - /// stream.set_nodelay(true).expect("set_nodelay call failed"); + /// stream.set_nodelay(true).expect("set_nodelay should succeed"); /// ``` #[stable(feature = "net2_mutators", since = "1.9.0")] pub fn set_nodelay(&self, nodelay: bool) -> io::Result<()> { @@ -507,7 +559,7 @@ impl TcpStream { /// /// let stream = TcpStream::connect("127.0.0.1:8080") /// .expect("Couldn't connect to the server..."); - /// stream.set_nodelay(true).expect("set_nodelay call failed"); + /// stream.set_nodelay(true).expect("set_nodelay should succeed"); /// assert_eq!(stream.nodelay().unwrap_or(false), true); /// ``` #[stable(feature = "net2_mutators", since = "1.9.0")] @@ -527,7 +579,7 @@ impl TcpStream { /// /// let stream = TcpStream::connect("127.0.0.1:8080") /// .expect("Couldn't connect to the server..."); - /// stream.set_ttl(100).expect("set_ttl call failed"); + /// stream.set_ttl(100).expect("set_ttl should succeed"); /// ``` #[stable(feature = "net2_mutators", since = "1.9.0")] pub fn set_ttl(&self, ttl: u32) -> io::Result<()> { @@ -545,7 +597,7 @@ impl TcpStream { /// /// let stream = TcpStream::connect("127.0.0.1:8080") /// .expect("Couldn't connect to the server..."); - /// stream.set_ttl(100).expect("set_ttl call failed"); + /// stream.set_ttl(100).expect("set_ttl should succeed"); /// assert_eq!(stream.ttl().unwrap_or(0), 100); /// ``` #[stable(feature = "net2_mutators", since = "1.9.0")] @@ -582,8 +634,8 @@ impl TcpStream { /// to be retried, an error with kind [`io::ErrorKind::WouldBlock`] is /// returned. /// - /// On Unix platforms, calling this method corresponds to calling `fcntl` - /// `FIONBIO`. On Windows calling this method corresponds to calling + /// On most Unix platforms, calling this method corresponds to calling `ioctl` + /// `FIONBIO`. On Windows, calling this method corresponds to calling /// `ioctlsocket` `FIONBIO`. /// /// # Examples @@ -596,7 +648,7 @@ impl TcpStream { /// /// let mut stream = TcpStream::connect("127.0.0.1:7878") /// .expect("Couldn't connect to the server..."); - /// stream.set_nonblocking(true).expect("set_nonblocking call failed"); + /// stream.set_nonblocking(true).expect("set_nonblocking should succeed"); /// /// # fn wait_for_fd() { unimplemented!() } /// let mut buf = vec![]; @@ -631,7 +683,7 @@ impl Read for TcpStream { self.0.read(buf) } - fn read_buf(&mut self, buf: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, buf: BorrowedCursor<'_, u8>) -> io::Result<()> { self.0.read_buf(buf) } @@ -670,7 +722,7 @@ impl Read for &TcpStream { self.0.read(buf) } - fn read_buf(&mut self, buf: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, buf: BorrowedCursor<'_, u8>) -> io::Result<()> { self.0.read_buf(buf) } @@ -825,6 +877,29 @@ impl TcpListener { /// is established. When established, the corresponding [`TcpStream`] and the /// remote peer's address will be returned. /// + /// # Errors + /// + /// Some errors this function returns do not indicate a problem with the + /// listener itself, and a program serving a long-lived listener will + /// usually want to handle them and keep accepting connections rather than + /// treat them as fatal. These include, but are not limited to: + /// + /// - An error specific to a single incoming connection that failed before + /// it could be accepted, such as one aborted by the peer + /// ([`ConnectionAborted`]). A later call may succeed immediately. + /// - An error from reaching the per-process or system-wide open file + /// descriptor limit. The call can be retried once other file descriptors + /// have been closed, typically after a short delay. + /// - An error from failing to allocate memory while accepting a connection + /// ([`OutOfMemory`]). + /// + /// Which errors can occur is platform-specific. On Unix, [`Interrupted`] + /// errors are retried internally rather than being returned. + /// + /// [`ConnectionAborted`]: io::ErrorKind::ConnectionAborted + /// [`OutOfMemory`]: io::ErrorKind::OutOfMemory + /// [`Interrupted`]: io::ErrorKind::Interrupted + /// /// # Examples /// /// ```no_run @@ -851,6 +926,11 @@ impl TcpListener { /// the peer's [`SocketAddr`] structure. Iterating over it is equivalent to /// calling [`TcpListener::accept`] in a loop. /// + /// # Errors + /// + /// Each connection yielded by the iterator can fail for the same reasons as + /// [`TcpListener::accept`]; see its documentation for details. + /// /// # Examples /// /// ```no_run @@ -886,6 +966,11 @@ impl TcpListener { /// the peer's [`SocketAddr`] structure. Iterating over it is equivalent to /// calling [`TcpListener::accept`] in a loop. /// + /// # Errors + /// + /// Each connection yielded by the iterator can fail for the same reasons as + /// [`TcpListener::accept`]; see its documentation for details. + /// /// # Examples /// /// ```no_run @@ -922,7 +1007,7 @@ impl TcpListener { /// use std::net::TcpListener; /// /// let listener = TcpListener::bind("127.0.0.1:80").unwrap(); - /// listener.set_ttl(100).expect("could not set TTL"); + /// listener.set_ttl(100).expect("set_ttl should succeed"); /// ``` #[stable(feature = "net2_mutators", since = "1.9.0")] pub fn set_ttl(&self, ttl: u32) -> io::Result<()> { @@ -939,7 +1024,7 @@ impl TcpListener { /// use std::net::TcpListener; /// /// let listener = TcpListener::bind("127.0.0.1:80").unwrap(); - /// listener.set_ttl(100).expect("could not set TTL"); + /// listener.set_ttl(100).expect("set_ttl should succeed"); /// assert_eq!(listener.ttl().unwrap_or(0), 100); /// ``` #[stable(feature = "net2_mutators", since = "1.9.0")] @@ -973,7 +1058,7 @@ impl TcpListener { /// use std::net::TcpListener; /// /// let listener = TcpListener::bind("127.0.0.1:80").unwrap(); - /// listener.take_error().expect("No error was expected"); + /// listener.take_error().expect("`take_error` should succeed"); /// ``` #[stable(feature = "net2_mutators", since = "1.9.0")] pub fn take_error(&self) -> io::Result> { @@ -988,8 +1073,8 @@ impl TcpListener { /// IO operation could not be completed and needs to be retried, an error /// with kind [`io::ErrorKind::WouldBlock`] is returned. /// - /// On Unix platforms, calling this method corresponds to calling `fcntl` - /// `FIONBIO`. On Windows calling this method corresponds to calling + /// On most Unix platforms, calling this method corresponds to calling `ioctl` + /// `FIONBIO`. On Windows, calling this method corresponds to calling /// `ioctlsocket` `FIONBIO`. /// /// # Examples @@ -1002,7 +1087,7 @@ impl TcpListener { /// use std::net::TcpListener; /// /// let listener = TcpListener::bind("127.0.0.1:7878").unwrap(); - /// listener.set_nonblocking(true).expect("Cannot set non-blocking"); + /// listener.set_nonblocking(true).expect("set_nonblocking should succeed"); /// /// # fn wait_for_fd() { unimplemented!() } /// # fn handle_connection(stream: std::net::TcpStream) { unimplemented!() } diff --git a/library/std/src/net/tcp/tests.rs b/library/std/src/net/tcp/tests.rs index e4a30b80e3df4..45a512cb9b4c7 100644 --- a/library/std/src/net/tcp/tests.rs +++ b/library/std/src/net/tcp/tests.rs @@ -1,17 +1,14 @@ +use rand::Rng; + use crate::io::prelude::*; use crate::io::{BorrowedBuf, ErrorKind, IoSlice, IoSliceMut}; use crate::mem::MaybeUninit; -use crate::net::test::{next_test_ip4, next_test_ip6}; +use crate::net::tests::{LOCALHOST_IP4, LOCALHOST_IP6}; use crate::net::*; use crate::sync::mpsc::channel; use crate::time::{Duration, Instant}; use crate::{fmt, thread}; -fn each_ip(f: &mut dyn FnMut(SocketAddr)) { - f(next_test_ip4()); - f(next_test_ip6()); -} - macro_rules! t { ($e:expr) => { match $e { @@ -21,6 +18,11 @@ macro_rules! t { }; } +fn each_ip(f: &mut dyn FnMut(TcpListener)) { + f(t!(TcpListener::bind(LOCALHOST_IP4))); + f(t!(TcpListener::bind(LOCALHOST_IP6))); +} + #[test] fn bind_error() { match TcpListener::bind("1.1.1.1:9999") { @@ -46,10 +48,18 @@ fn connect_error() { } } +/// Regression test for `Duration::MAX` timeout issue +/// (https://github.com/rust-lang/rust/issues/112405). #[test] #[cfg_attr(target_env = "sgx", ignore)] // FIXME: https://github.com/fortanix/rust-sgx/issues/31 fn connect_timeout_error() { - let socket_addr = next_test_ip4(); + // Pick a random port, but not in the range usually used by the OS's automatic port assignment + // so we cannot conflict with the other tests. + let mut rng = crate::test_helpers::test_rng(); + let port = rng.random_range((16 * 1024)..(48 * 1024)); + let socket_addr = SocketAddr::V4(SocketAddrV4::new(Ipv4Addr::new(127, 0, 0, 1), port)); + + // Ensure we error immediately rather than timing out. let result = TcpStream::connect_timeout(&socket_addr, Duration::MAX); assert!(!matches!(result, Err(e) if e.kind() == ErrorKind::TimedOut)); @@ -60,11 +70,11 @@ fn connect_timeout_error() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn listen_localhost() { - let socket_addr = next_test_ip4(); - let listener = t!(TcpListener::bind(&socket_addr)); + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); + let addr = t!(listener.local_addr()); let _t = thread::spawn(move || { - let mut stream = t!(TcpStream::connect(&("localhost", socket_addr.port()))); + let mut stream = t!(TcpStream::connect(addr)); t!(stream.write(&[144])); }); @@ -77,15 +87,11 @@ fn listen_localhost() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn connect_loopback() { - each_ip(&mut |addr| { - let acceptor = t!(TcpListener::bind(&addr)); + each_ip(&mut |acceptor| { + let addr = t!(acceptor.local_addr()); let _t = thread::spawn(move || { - let host = match addr { - SocketAddr::V4(..) => "127.0.0.1", - SocketAddr::V6(..) => "::1", - }; - let mut stream = t!(TcpStream::connect(&(host, addr.port()))); + let mut stream = t!(TcpStream::connect(addr)); t!(stream.write(&[66])); }); @@ -99,8 +105,8 @@ fn connect_loopback() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn smoke_test() { - each_ip(&mut |addr| { - let acceptor = t!(TcpListener::bind(&addr)); + each_ip(&mut |acceptor| { + let addr = t!(acceptor.local_addr()); let (tx, rx) = channel(); let _t = thread::spawn(move || { @@ -120,8 +126,8 @@ fn smoke_test() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn read_eof() { - each_ip(&mut |addr| { - let acceptor = t!(TcpListener::bind(&addr)); + each_ip(&mut |acceptor| { + let addr = t!(acceptor.local_addr()); let _t = thread::spawn(move || { let _stream = t!(TcpStream::connect(&addr)); @@ -140,8 +146,8 @@ fn read_eof() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn write_close() { - each_ip(&mut |addr| { - let acceptor = t!(TcpListener::bind(&addr)); + each_ip(&mut |acceptor| { + let addr = t!(acceptor.local_addr()); let (tx, rx) = channel(); let _t = thread::spawn(move || { @@ -169,9 +175,9 @@ fn write_close() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn multiple_connect_serial() { - each_ip(&mut |addr| { + each_ip(&mut |acceptor| { + let addr = t!(acceptor.local_addr()); let max = 10; - let acceptor = t!(TcpListener::bind(&addr)); let _t = thread::spawn(move || { for _ in 0..max { @@ -193,8 +199,8 @@ fn multiple_connect_serial() { #[cfg_attr(target_os = "wasi", ignore)] // no threads fn multiple_connect_interleaved_greedy_schedule() { const MAX: usize = 10; - each_ip(&mut |addr| { - let acceptor = t!(TcpListener::bind(&addr)); + each_ip(&mut |acceptor| { + let addr = t!(acceptor.local_addr()); let _t = thread::spawn(move || { let acceptor = acceptor; @@ -231,8 +237,8 @@ fn multiple_connect_interleaved_greedy_schedule() { #[cfg_attr(target_os = "wasi", ignore)] // no threads fn multiple_connect_interleaved_lazy_schedule() { const MAX: usize = 10; - each_ip(&mut |addr| { - let acceptor = t!(TcpListener::bind(&addr)); + each_ip(&mut |acceptor| { + let addr = t!(acceptor.local_addr()); let _t = thread::spawn(move || { for stream in acceptor.incoming().take(MAX) { @@ -266,25 +272,25 @@ fn multiple_connect_interleaved_lazy_schedule() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn socket_and_peer_name() { - each_ip(&mut |addr| { - let listener = t!(TcpListener::bind(&addr)); - let so_name = t!(listener.local_addr()); - assert_eq!(addr, so_name); - let _t = thread::spawn(move || { - t!(listener.accept()); - }); + each_ip(&mut |listener| { + let addr = t!(listener.local_addr()); + let other_stream = thread::spawn(move || t!(listener.accept())); let stream = t!(TcpStream::connect(&addr)); assert_eq!(addr, t!(stream.peer_addr())); + let (other_stream, other_peer) = other_stream.join().unwrap(); + assert_eq!(addr, t!(other_stream.local_addr())); + assert_eq!(other_peer, t!(other_stream.peer_addr())); + assert_eq!(other_peer, t!(stream.local_addr())); }) } #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn partial_read() { - each_ip(&mut |addr| { + each_ip(&mut |srv| { + let addr = t!(srv.local_addr()); let (tx, rx) = channel(); - let srv = t!(TcpListener::bind(&addr)); let _t = thread::spawn(move || { let mut cl = t!(srv.accept()).0; cl.write(&[10]).unwrap(); @@ -304,8 +310,8 @@ fn partial_read() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn read_buf() { - each_ip(&mut |addr| { - let srv = t!(TcpListener::bind(&addr)); + each_ip(&mut |srv| { + let addr = t!(srv.local_addr()); let t = thread::spawn(move || { let mut s = t!(TcpStream::connect(&addr)); s.write_all(&[1, 2, 3, 4]).unwrap(); @@ -317,7 +323,7 @@ fn read_buf() { t!(s.read_buf(buf.unfilled())); assert_eq!(buf.filled(), &[1, 2, 3, 4]); // TcpStream::read_buf should omit buffer initialization. - assert_eq!(buf.init_len(), 4); + assert!(!buf.is_init()); t.join().ok().expect("thread panicked"); }) @@ -325,8 +331,8 @@ fn read_buf() { #[test] fn read_vectored() { - each_ip(&mut |addr| { - let srv = t!(TcpListener::bind(&addr)); + each_ip(&mut |srv| { + let addr = t!(srv.local_addr()); let mut s1 = t!(TcpStream::connect(&addr)); let mut s2 = t!(srv.accept()).0; @@ -350,8 +356,8 @@ fn read_vectored() { #[test] fn write_vectored() { - each_ip(&mut |addr| { - let srv = t!(TcpListener::bind(&addr)); + each_ip(&mut |srv| { + let addr = t!(srv.local_addr()); let mut s1 = t!(TcpStream::connect(&addr)); let mut s2 = t!(srv.accept()).0; @@ -374,8 +380,8 @@ fn write_vectored() { #[test] fn double_bind() { - each_ip(&mut |addr| { - let listener1 = t!(TcpListener::bind(&addr)); + each_ip(&mut |listener1| { + let addr = t!(listener1.local_addr()); match TcpListener::bind(&addr) { Ok(listener2) => panic!( "This system (perhaps due to options set by TcpListener::bind) \ @@ -399,8 +405,8 @@ fn double_bind() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn tcp_clone_smoke() { - each_ip(&mut |addr| { - let acceptor = t!(TcpListener::bind(&addr)); + each_ip(&mut |acceptor| { + let addr = t!(acceptor.local_addr()); let _t = thread::spawn(move || { let mut s = t!(TcpStream::connect(&addr)); @@ -431,8 +437,8 @@ fn tcp_clone_smoke() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn tcp_clone_two_read() { - each_ip(&mut |addr| { - let acceptor = t!(TcpListener::bind(&addr)); + each_ip(&mut |acceptor| { + let addr = t!(acceptor.local_addr()); let (tx1, rx) = channel(); let tx2 = tx1.clone(); @@ -466,8 +472,8 @@ fn tcp_clone_two_read() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn tcp_clone_two_write() { - each_ip(&mut |addr| { - let acceptor = t!(TcpListener::bind(&addr)); + each_ip(&mut |acceptor| { + let addr = t!(acceptor.local_addr()); let _t = thread::spawn(move || { let mut s = t!(TcpStream::connect(&addr)); @@ -496,8 +502,8 @@ fn tcp_clone_two_write() { #[cfg_attr(target_env = "sgx", ignore)] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn shutdown_smoke() { - each_ip(&mut |addr| { - let a = t!(TcpListener::bind(&addr)); + each_ip(&mut |a| { + let addr = t!(a.local_addr()); let _t = thread::spawn(move || { let mut c = t!(a.accept()).0; let mut b = [0]; @@ -519,8 +525,8 @@ fn shutdown_smoke() { #[cfg_attr(target_env = "sgx", ignore)] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn close_readwrite_smoke() { - each_ip(&mut |addr| { - let a = t!(TcpListener::bind(&addr)); + each_ip(&mut |a| { + let addr = t!(a.local_addr()); let (tx, rx) = channel::<()>(); let _t = thread::spawn(move || { let _s = t!(a.accept()); @@ -562,8 +568,8 @@ fn close_readwrite_smoke() { #[cfg_attr(windows, ignore)] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn close_read_wakes_up() { - each_ip(&mut |addr| { - let listener = t!(TcpListener::bind(&addr)); + each_ip(&mut |listener| { + let addr = t!(listener.local_addr()); let _t = thread::spawn(move || { let (stream, _) = t!(listener.accept()); stream @@ -590,8 +596,8 @@ fn close_read_wakes_up() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn clone_while_reading() { - each_ip(&mut |addr| { - let accept = t!(TcpListener::bind(&addr)); + each_ip(&mut |accept| { + let addr = t!(accept.local_addr()); // Enqueue a thread to write to a socket let (tx, rx) = channel(); @@ -631,8 +637,8 @@ fn clone_while_reading() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn clone_accept_smoke() { - each_ip(&mut |addr| { - let a = t!(TcpListener::bind(&addr)); + each_ip(&mut |a| { + let addr = t!(a.local_addr()); let a2 = t!(a.try_clone()); let _t = thread::spawn(move || { @@ -650,8 +656,8 @@ fn clone_accept_smoke() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn clone_accept_concurrent() { - each_ip(&mut |addr| { - let a = t!(TcpListener::bind(&addr)); + each_ip(&mut |a| { + let addr = t!(a.local_addr()); let a2 = t!(a.try_clone()); let (tx, rx) = channel(); @@ -701,9 +707,9 @@ fn debug() { } let inner_name = if cfg!(windows) { "socket" } else { "fd" }; - let socket_addr = next_test_ip4(); - let listener = t!(TcpListener::bind(&socket_addr)); + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); + let socket_addr = t!(listener.local_addr()); let compare = format!( "TcpListener {{ addr: {:?}, {}: {:?} }}", render_socket_addr(&socket_addr), @@ -727,17 +733,22 @@ fn debug() { // no longer has rounding errors. // VxWorks ignores SO_SNDTIMEO. #[cfg_attr( - any(target_os = "netbsd", target_os = "openbsd", target_os = "vxworks", target_os = "nto"), + any( + target_os = "netbsd", + target_os = "openbsd", + target_os = "vxworks", + target_os = "nto", + target_os = "qnx" + ), ignore )] #[cfg_attr(target_env = "sgx", ignore)] // FIXME: https://github.com/fortanix/rust-sgx/issues/31 #[cfg_attr(target_os = "wasi", ignore)] // timeout not supported #[test] fn timeouts() { - let addr = next_test_ip4(); - let listener = t!(TcpListener::bind(&addr)); + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); - let stream = t!(TcpStream::connect(&("localhost", addr.port()))); + let stream = t!(TcpStream::connect(t!(listener.local_addr()))); let dur = Duration::new(15410, 0); assert_eq!(None, t!(stream.read_timeout())); @@ -762,10 +773,9 @@ fn timeouts() { #[cfg_attr(target_env = "sgx", ignore)] // FIXME: https://github.com/fortanix/rust-sgx/issues/31 #[cfg_attr(target_os = "wasi", ignore)] // timeout not supported fn test_read_timeout() { - let addr = next_test_ip4(); - let listener = t!(TcpListener::bind(&addr)); + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); - let mut stream = t!(TcpStream::connect(&("localhost", addr.port()))); + let mut stream = t!(TcpStream::connect(t!(listener.local_addr()))); t!(stream.set_read_timeout(Some(Duration::from_millis(1000)))); let mut buf = [0; 10]; @@ -784,10 +794,9 @@ fn test_read_timeout() { #[cfg_attr(target_env = "sgx", ignore)] // FIXME: https://github.com/fortanix/rust-sgx/issues/31 #[cfg_attr(target_os = "wasi", ignore)] // timeout not supported fn test_read_with_timeout() { - let addr = next_test_ip4(); - let listener = t!(TcpListener::bind(&addr)); + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); - let mut stream = t!(TcpStream::connect(&("localhost", addr.port()))); + let mut stream = t!(TcpStream::connect(t!(listener.local_addr()))); t!(stream.set_read_timeout(Some(Duration::from_millis(1000)))); let mut other_end = t!(listener.accept()).0; @@ -812,10 +821,8 @@ fn test_read_with_timeout() { // when passed zero Durations #[test] fn test_timeout_zero_duration() { - let addr = next_test_ip4(); - - let listener = t!(TcpListener::bind(&addr)); - let stream = t!(TcpStream::connect(&addr)); + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); + let stream = t!(TcpStream::connect(t!(listener.local_addr()))); let result = stream.set_write_timeout(Some(Duration::new(0, 0))); let err = result.unwrap_err(); @@ -832,10 +839,9 @@ fn test_timeout_zero_duration() { #[cfg_attr(target_env = "sgx", ignore)] #[cfg_attr(target_os = "wasi", ignore)] // linger not supported fn linger() { - let addr = next_test_ip4(); - let _listener = t!(TcpListener::bind(&addr)); + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); - let stream = t!(TcpStream::connect(&("localhost", addr.port()))); + let stream = t!(TcpStream::connect(t!(listener.local_addr()))); assert_eq!(None, t!(stream.linger())); t!(stream.set_linger(Some(Duration::from_secs(1)))); @@ -844,13 +850,26 @@ fn linger() { assert_eq!(None, t!(stream.linger())); } +#[test] +#[cfg_attr(target_env = "sgx", ignore)] +#[cfg_attr(target_os = "wasi", ignore)] +fn keepalive() { + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); + let stream = t!(TcpStream::connect(t!(listener.local_addr()))); + + assert_eq!(false, t!(stream.keepalive())); + t!(stream.set_keepalive(true)); + assert_eq!(true, t!(stream.keepalive())); + t!(stream.set_keepalive(false)); + assert_eq!(false, t!(stream.keepalive())); +} + #[test] #[cfg_attr(target_env = "sgx", ignore)] fn nodelay() { - let addr = next_test_ip4(); - let _listener = t!(TcpListener::bind(&addr)); + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); - let stream = t!(TcpStream::connect(&("localhost", addr.port()))); + let stream = t!(TcpStream::connect(t!(listener.local_addr()))); assert_eq!(false, t!(stream.nodelay())); t!(stream.set_nodelay(true)); @@ -864,13 +883,12 @@ fn nodelay() { fn ttl() { let ttl = 100; - let addr = next_test_ip4(); - let listener = t!(TcpListener::bind(&addr)); + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); t!(listener.set_ttl(ttl)); assert_eq!(ttl, t!(listener.ttl())); - let stream = t!(TcpStream::connect(&("localhost", addr.port()))); + let stream = t!(TcpStream::connect(t!(listener.local_addr()))); t!(stream.set_ttl(ttl)); assert_eq!(ttl, t!(stream.ttl())); @@ -879,13 +897,12 @@ fn ttl() { #[test] #[cfg_attr(target_env = "sgx", ignore)] fn set_nonblocking() { - let addr = next_test_ip4(); - let listener = t!(TcpListener::bind(&addr)); + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); t!(listener.set_nonblocking(true)); t!(listener.set_nonblocking(false)); - let mut stream = t!(TcpStream::connect(&("localhost", addr.port()))); + let mut stream = t!(TcpStream::connect(t!(listener.local_addr()))); t!(stream.set_nonblocking(false)); t!(stream.set_nonblocking(true)); @@ -902,10 +919,11 @@ fn set_nonblocking() { #[cfg_attr(target_env = "sgx", ignore)] // FIXME: https://github.com/fortanix/rust-sgx/issues/31 #[cfg_attr(target_os = "wasi", ignore)] // no threads fn peek() { - each_ip(&mut |addr| { + each_ip(&mut |srv| { + let addr = t!(srv.local_addr()); + let (txdone, rxdone) = channel(); - let srv = t!(TcpListener::bind(&addr)); let _t = thread::spawn(move || { let mut cl = t!(srv.accept()).0; cl.write(&[1, 3, 3, 7]).unwrap(); @@ -938,3 +956,37 @@ fn connect_timeout_valid() { let addr = listener.local_addr().unwrap(); TcpStream::connect_timeout(&addr, Duration::from_secs(2)).unwrap(); } + +// #115325: writing a buffer larger than `c_int::MAX` bytes used to fail on +// macOS with `EINVAL`; `write_all` should now transfer it via short sends. +#[test] +#[cfg(all(target_pointer_width = "64", unix))] +fn write_buffer_larger_than_c_int_max() { + const LEN: usize = crate::ffi::c_int::MAX as usize + 1; + + // Back the source buffer with a read-only anonymous mapping rather than a + // 2 GiB `Vec`, so the test doesn't actually consume ~2 GiB of physical + // memory while `write_all` reads through the buffer. + let data = crate::net::tests::ZeroedMmap::new(LEN); + + let listener = t!(TcpListener::bind("127.0.0.1:0")); + let addr = t!(listener.local_addr()); + let reader = thread::spawn(move || { + let (mut sock, _) = t!(listener.accept()); + let mut received = 0usize; + let mut buf = vec![0u8; 1 << 20]; + loop { + match sock.read(&mut buf) { + Ok(0) => break, + Ok(n) => received += n, + Err(e) => panic!("read error: {e}"), + } + } + received + }); + + let mut stream = t!(TcpStream::connect(addr)); + t!(stream.write_all(&data)); + drop(stream); // signal EOF so the reader loop terminates + assert_eq!(reader.join().unwrap(), LEN); +} diff --git a/library/std/src/net/test.rs b/library/std/src/net/test.rs deleted file mode 100644 index df48b2f2420c3..0000000000000 --- a/library/std/src/net/test.rs +++ /dev/null @@ -1,44 +0,0 @@ -#![allow(warnings)] // not used on emscripten - -use crate::env; -use crate::net::{Ipv4Addr, Ipv6Addr, SocketAddr, SocketAddrV4, SocketAddrV6, ToSocketAddrs}; -use crate::sync::atomic::{AtomicUsize, Ordering}; - -static PORT: AtomicUsize = AtomicUsize::new(0); -const BASE_PORT: u16 = 19600; - -pub fn next_test_ip4() -> SocketAddr { - let port = PORT.fetch_add(1, Ordering::Relaxed) as u16 + BASE_PORT; - SocketAddr::V4(SocketAddrV4::new(Ipv4Addr::new(127, 0, 0, 1), port)) -} - -pub fn next_test_ip6() -> SocketAddr { - let port = PORT.fetch_add(1, Ordering::Relaxed) as u16 + BASE_PORT; - SocketAddr::V6(SocketAddrV6::new(Ipv6Addr::new(0, 0, 0, 0, 0, 0, 0, 1), port, 0, 0)) -} - -pub fn sa4(a: Ipv4Addr, p: u16) -> SocketAddr { - SocketAddr::V4(SocketAddrV4::new(a, p)) -} - -pub fn sa6(a: Ipv6Addr, p: u16) -> SocketAddr { - SocketAddr::V6(SocketAddrV6::new(a, p, 0, 0)) -} - -pub fn tsa(a: A) -> Result, String> { - match a.to_socket_addrs() { - Ok(a) => Ok(a.collect()), - Err(e) => Err(e.to_string()), - } -} - -pub fn compare_ignore_zoneid(a: &SocketAddr, b: &SocketAddr) -> bool { - match (a, b) { - (SocketAddr::V6(a), SocketAddr::V6(b)) => { - a.ip().segments() == b.ip().segments() - && a.flowinfo() == b.flowinfo() - && a.port() == b.port() - } - _ => a == b, - } -} diff --git a/library/std/src/net/tests.rs b/library/std/src/net/tests.rs new file mode 100644 index 0000000000000..213c9a5a3e3a1 --- /dev/null +++ b/library/std/src/net/tests.rs @@ -0,0 +1,99 @@ +#![allow(warnings)] // not used on emscripten + +use crate::env; +use crate::net::{Ipv4Addr, Ipv6Addr, SocketAddr, SocketAddrV4, SocketAddrV6, ToSocketAddrs}; +use crate::sync::atomic::{AtomicUsize, Ordering}; + +/// A localhost address whose port will be picked automatically by the OS. +pub const LOCALHOST_IP4: SocketAddr = + SocketAddr::V4(SocketAddrV4::new(Ipv4Addr::new(127, 0, 0, 1), 0)); +/// A localhost address whose port will be picked automatically by the OS. +pub const LOCALHOST_IP6: SocketAddr = + SocketAddr::V6(SocketAddrV6::new(Ipv6Addr::new(0, 0, 0, 0, 0, 0, 0, 1), 0, 0, 0)); + +pub fn sa4(a: Ipv4Addr, p: u16) -> SocketAddr { + SocketAddr::V4(SocketAddrV4::new(a, p)) +} + +pub fn sa6(a: Ipv6Addr, p: u16) -> SocketAddr { + SocketAddr::V6(SocketAddrV6::new(a, p, 0, 0)) +} + +pub fn tsa(a: A) -> Result, String> { + match a.to_socket_addrs() { + Ok(a) => Ok(a.collect()), + Err(e) => Err(e.to_string()), + } +} + +pub fn compare_ignore_zoneid(a: &SocketAddr, b: &SocketAddr) -> bool { + match (a, b) { + (SocketAddr::V6(a), SocketAddr::V6(b)) => { + a.ip().segments() == b.ip().segments() + && a.flowinfo() == b.flowinfo() + && a.port() == b.port() + } + _ => a == b, + } +} + +/// A read-only anonymous mapping of `len` zero bytes. +/// +/// The tests that need a buffer larger than `c_int::MAX` use this instead of a +/// `Vec`: the pages are demand-zero and never written, so they stay mapped to +/// the shared zero page and the mapping doesn't actually consume `len` bytes of +/// physical memory. +#[cfg(all(target_pointer_width = "64", unix))] +pub struct ZeroedMmap { + ptr: *mut libc::c_void, + len: usize, +} + +#[cfg(all(target_pointer_width = "64", unix))] +impl ZeroedMmap { + pub fn new(len: usize) -> ZeroedMmap { + let ptr = unsafe { + libc::mmap( + crate::ptr::null_mut(), + len, + libc::PROT_READ, + libc::MAP_PRIVATE | libc::MAP_ANON, + -1, + 0, + ) + }; + assert_ne!(ptr, libc::MAP_FAILED, "mmap failed: {}", crate::io::Error::last_os_error()); + ZeroedMmap { ptr, len } + } +} + +#[cfg(all(target_pointer_width = "64", unix))] +impl crate::ops::Deref for ZeroedMmap { + type Target = [u8]; + + fn deref(&self) -> &[u8] { + // SAFETY: the mapping is live for `self.len` readable bytes until `Drop`. + unsafe { crate::slice::from_raw_parts(self.ptr as *const u8, self.len) } + } +} + +#[cfg(all(target_pointer_width = "64", unix))] +impl Drop for ZeroedMmap { + fn drop(&mut self) { + // SAFETY: `ptr`/`len` come from the `mmap` call above and are unmapped once. + unsafe { + libc::munmap(self.ptr, self.len); + } + } +} + +#[test] +fn hostname_smoketest() { + // Just a smoke test to ensure it can be called. + let name = crate::net::hostname(); + if cfg!(any(all(windows, not(target_vendor = "win7")), unix)) { + // At least on Windows and Unix, this should succeed. + // The `win7` Windows targets do not support it yet though. + name.unwrap(); + } +} diff --git a/library/std/src/net/udp.rs b/library/std/src/net/udp.rs index 136803ab16f1f..428ab6047244e 100644 --- a/library/std/src/net/udp.rs +++ b/library/std/src/net/udp.rs @@ -6,6 +6,7 @@ target_env = "sgx", target_os = "xous", target_os = "trusty", + target_os = "l4re", )) ))] mod tests; @@ -83,7 +84,7 @@ impl UdpSocket { /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:3400").expect("couldn't bind to address"); + /// let socket = UdpSocket::bind("127.0.0.1:3400").expect("bind should succeed"); /// ``` /// /// Creates a UDP socket bound to `127.0.0.1:3400`. If the socket cannot be @@ -96,7 +97,7 @@ impl UdpSocket { /// SocketAddr::from(([127, 0, 0, 1], 3400)), /// SocketAddr::from(([127, 0, 0, 1], 3401)), /// ]; - /// let socket = UdpSocket::bind(&addrs[..]).expect("couldn't bind to address"); + /// let socket = UdpSocket::bind(&addrs[..]).expect("bind should succeed"); /// ``` /// /// Creates a UDP socket bound to a port assigned by the operating system @@ -129,15 +130,19 @@ impl UdpSocket { /// hold the message bytes. If a message is too long to fit in the supplied buffer, /// excess bytes may be discarded. /// + /// Refer to the platform-specific documentation on this function; it is considered + /// correct for its behavior to differ from [`UdpSocket::recv`] if the underlying system + /// call does so. + /// /// # Examples /// /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); /// let mut buf = [0; 10]; /// let (number_of_bytes, src_addr) = socket.recv_from(&mut buf) - /// .expect("Didn't receive data"); + /// .expect("recv_from should succeed"); /// let filled_buf = &mut buf[..number_of_bytes]; /// ``` #[stable(feature = "rust1", since = "1.0.0")] @@ -163,10 +168,10 @@ impl UdpSocket { /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); /// let mut buf = [0; 10]; /// let (number_of_bytes, src_addr) = socket.peek_from(&mut buf) - /// .expect("Didn't receive data"); + /// .expect("recv_from should succeed"); /// let filled_buf = &mut buf[..number_of_bytes]; /// ``` #[stable(feature = "peek", since = "1.18.0")] @@ -195,8 +200,8 @@ impl UdpSocket { /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); - /// socket.send_to(&[0; 10], "127.0.0.1:4242").expect("couldn't send data"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); + /// socket.send_to(&[0; 10], "127.0.0.1:4242").expect("send_to should succeed"); /// ``` /// /// [Issue #34202]: https://github.com/rust-lang/rust/issues/34202 @@ -215,8 +220,8 @@ impl UdpSocket { /// ```no_run /// use std::net::{Ipv4Addr, SocketAddr, SocketAddrV4, UdpSocket}; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); - /// socket.connect("192.168.0.1:41203").expect("couldn't connect to address"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); + /// socket.connect("192.168.0.1:41203").expect("connect should succeed"); /// assert_eq!(socket.peer_addr().unwrap(), /// SocketAddr::V4(SocketAddrV4::new(Ipv4Addr::new(192, 168, 0, 1), 41203))); /// ``` @@ -228,7 +233,7 @@ impl UdpSocket { /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); /// assert_eq!(socket.peer_addr().unwrap_err().kind(), /// std::io::ErrorKind::NotConnected); /// ``` @@ -244,7 +249,7 @@ impl UdpSocket { /// ```no_run /// use std::net::{Ipv4Addr, SocketAddr, SocketAddrV4, UdpSocket}; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); /// assert_eq!(socket.local_addr().unwrap(), /// SocketAddr::V4(SocketAddrV4::new(Ipv4Addr::new(127, 0, 0, 1), 34254))); /// ``` @@ -264,8 +269,8 @@ impl UdpSocket { /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); - /// let socket_clone = socket.try_clone().expect("couldn't clone the socket"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); + /// let socket_clone = socket.try_clone().expect("try_clone should succeed"); /// ``` #[stable(feature = "rust1", since = "1.0.0")] pub fn try_clone(&self) -> io::Result { @@ -293,8 +298,8 @@ impl UdpSocket { /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); - /// socket.set_read_timeout(None).expect("set_read_timeout call failed"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); + /// socket.set_read_timeout(None).expect("set_read_timeout should succeed"); /// ``` /// /// An [`Err`] is returned if the zero [`Duration`] is passed to this @@ -336,8 +341,8 @@ impl UdpSocket { /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); - /// socket.set_write_timeout(None).expect("set_write_timeout call failed"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); + /// socket.set_write_timeout(None).expect("set_write_timeout should succeed"); /// ``` /// /// An [`Err`] is returned if the zero [`Duration`] is passed to this @@ -369,8 +374,8 @@ impl UdpSocket { /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); - /// socket.set_read_timeout(None).expect("set_read_timeout call failed"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); + /// socket.set_read_timeout(None).expect("set_read_timeout should succeed"); /// assert_eq!(socket.read_timeout().unwrap(), None); /// ``` #[stable(feature = "socket_timeout", since = "1.4.0")] @@ -389,8 +394,8 @@ impl UdpSocket { /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); - /// socket.set_write_timeout(None).expect("set_write_timeout call failed"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); + /// socket.set_write_timeout(None).expect("set_write_timeout should succeed"); /// assert_eq!(socket.write_timeout().unwrap(), None); /// ``` #[stable(feature = "socket_timeout", since = "1.4.0")] @@ -408,8 +413,8 @@ impl UdpSocket { /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); - /// socket.set_broadcast(false).expect("set_broadcast call failed"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); + /// socket.set_broadcast(false).expect("set_broadcast should succeed"); /// ``` #[stable(feature = "net2_mutators", since = "1.9.0")] pub fn set_broadcast(&self, broadcast: bool) -> io::Result<()> { @@ -425,8 +430,8 @@ impl UdpSocket { /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); - /// socket.set_broadcast(false).expect("set_broadcast call failed"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); + /// socket.set_broadcast(false).expect("set_broadcast should succeed"); /// assert_eq!(socket.broadcast().unwrap(), false); /// ``` #[stable(feature = "net2_mutators", since = "1.9.0")] @@ -444,8 +449,8 @@ impl UdpSocket { /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); - /// socket.set_multicast_loop_v4(false).expect("set_multicast_loop_v4 call failed"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); + /// socket.set_multicast_loop_v4(false).expect("set_multicast_loop_v4 should succeed"); /// ``` #[stable(feature = "net2_mutators", since = "1.9.0")] pub fn set_multicast_loop_v4(&self, multicast_loop_v4: bool) -> io::Result<()> { @@ -461,8 +466,8 @@ impl UdpSocket { /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); - /// socket.set_multicast_loop_v4(false).expect("set_multicast_loop_v4 call failed"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); + /// socket.set_multicast_loop_v4(false).expect("set_multicast_loop_v4 should succeed"); /// assert_eq!(socket.multicast_loop_v4().unwrap(), false); /// ``` #[stable(feature = "net2_mutators", since = "1.9.0")] @@ -483,8 +488,8 @@ impl UdpSocket { /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); - /// socket.set_multicast_ttl_v4(42).expect("set_multicast_ttl_v4 call failed"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); + /// socket.set_multicast_ttl_v4(42).expect("set_multicast_ttl_v4 should succeed"); /// ``` #[stable(feature = "net2_mutators", since = "1.9.0")] pub fn set_multicast_ttl_v4(&self, multicast_ttl_v4: u32) -> io::Result<()> { @@ -500,8 +505,8 @@ impl UdpSocket { /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); - /// socket.set_multicast_ttl_v4(42).expect("set_multicast_ttl_v4 call failed"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); + /// socket.set_multicast_ttl_v4(42).expect("set_multicast_ttl_v4 should succeed"); /// assert_eq!(socket.multicast_ttl_v4().unwrap(), 42); /// ``` #[stable(feature = "net2_mutators", since = "1.9.0")] @@ -519,8 +524,8 @@ impl UdpSocket { /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); - /// socket.set_multicast_loop_v6(false).expect("set_multicast_loop_v6 call failed"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); + /// socket.set_multicast_loop_v6(false).expect("set_multicast_loop_v6 should succeed"); /// ``` #[stable(feature = "net2_mutators", since = "1.9.0")] pub fn set_multicast_loop_v6(&self, multicast_loop_v6: bool) -> io::Result<()> { @@ -536,8 +541,8 @@ impl UdpSocket { /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); - /// socket.set_multicast_loop_v6(false).expect("set_multicast_loop_v6 call failed"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); + /// socket.set_multicast_loop_v6(false).expect("set_multicast_loop_v6 should succeed"); /// assert_eq!(socket.multicast_loop_v6().unwrap(), false); /// ``` #[stable(feature = "net2_mutators", since = "1.9.0")] @@ -555,8 +560,8 @@ impl UdpSocket { /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); - /// socket.set_ttl(42).expect("set_ttl call failed"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); + /// socket.set_ttl(42).expect("set_ttl should succeed"); /// ``` #[stable(feature = "net2_mutators", since = "1.9.0")] pub fn set_ttl(&self, ttl: u32) -> io::Result<()> { @@ -572,8 +577,8 @@ impl UdpSocket { /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); - /// socket.set_ttl(42).expect("set_ttl call failed"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); + /// socket.set_ttl(42).expect("set_ttl should succeed"); /// assert_eq!(socket.ttl().unwrap(), 42); /// ``` #[stable(feature = "net2_mutators", since = "1.9.0")] @@ -630,7 +635,7 @@ impl UdpSocket { /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); /// match socket.take_error() { /// Ok(Some(error)) => println!("UdpSocket error: {error:?}"), /// Ok(None) => println!("No error"), @@ -662,8 +667,8 @@ impl UdpSocket { /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:3400").expect("couldn't bind to address"); - /// socket.connect("127.0.0.1:8080").expect("connect function failed"); + /// let socket = UdpSocket::bind("127.0.0.1:3400").expect("bind should succeed"); + /// socket.connect("127.0.0.1:8080").expect("connect should succeed"); /// ``` /// /// Unlike in the TCP case, passing an array of addresses to the `connect` @@ -692,9 +697,9 @@ impl UdpSocket { /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); - /// socket.connect("127.0.0.1:8080").expect("connect function failed"); - /// socket.send(&[0, 1, 2]).expect("couldn't send message"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); + /// socket.connect("127.0.0.1:8080").expect("connect should succeed"); + /// socket.send(&[0, 1, 2]).expect("send should succeed"); /// ``` #[stable(feature = "net2_mutators", since = "1.9.0")] pub fn send(&self, buf: &[u8]) -> io::Result { @@ -711,13 +716,17 @@ impl UdpSocket { /// [`UdpSocket::connect`] will connect this socket to a remote address. This /// method will fail if the socket is not connected. /// + /// Refer to the platform-specific documentation on this function; it is considered + /// correct for its behavior to differ from [`UdpSocket::recv_from`] if the underlying + /// system call does so. + /// /// # Examples /// /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); - /// socket.connect("127.0.0.1:8080").expect("connect function failed"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); + /// socket.connect("127.0.0.1:8080").expect("connect should succeed"); /// let mut buf = [0; 10]; /// match socket.recv(&mut buf) { /// Ok(received) => println!("received {received} bytes {:?}", &buf[..received]), @@ -756,8 +765,8 @@ impl UdpSocket { /// ```no_run /// use std::net::UdpSocket; /// - /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("couldn't bind to address"); - /// socket.connect("127.0.0.1:8080").expect("connect function failed"); + /// let socket = UdpSocket::bind("127.0.0.1:34254").expect("bind should succeed"); + /// socket.connect("127.0.0.1:8080").expect("connect should succeed"); /// let mut buf = [0; 10]; /// match socket.peek(&mut buf) { /// Ok(received) => println!("received {received} bytes"), @@ -778,8 +787,8 @@ impl UdpSocket { /// and needs to be retried, an error with kind /// [`io::ErrorKind::WouldBlock`] is returned. /// - /// On Unix platforms, calling this method corresponds to calling `fcntl` - /// `FIONBIO`. On Windows calling this method corresponds to calling + /// On most Unix platforms, calling this method corresponds to calling `ioctl` + /// `FIONBIO`. On Windows, calling this method corresponds to calling /// `ioctlsocket` `FIONBIO`. /// /// # Examples diff --git a/library/std/src/net/udp/tests.rs b/library/std/src/net/udp/tests.rs index 0638b36c54f9d..38d6dab80f64e 100644 --- a/library/std/src/net/udp/tests.rs +++ b/library/std/src/net/udp/tests.rs @@ -1,15 +1,10 @@ use crate::io::ErrorKind; -use crate::net::test::{compare_ignore_zoneid, next_test_ip4, next_test_ip6}; +use crate::net::tests::{LOCALHOST_IP4, LOCALHOST_IP6, compare_ignore_zoneid}; use crate::net::*; use crate::sync::mpsc::channel; use crate::thread; use crate::time::{Duration, Instant}; -fn each_ip(f: &mut dyn FnMut(SocketAddr, SocketAddr)) { - f(next_test_ip4(), next_test_ip4()); - f(next_test_ip6(), next_test_ip6()); -} - macro_rules! t { ($e:expr) => { match $e { @@ -19,6 +14,11 @@ macro_rules! t { }; } +fn each_ip(f: &mut dyn FnMut(UdpSocket, UdpSocket)) { + f(t!(UdpSocket::bind(LOCALHOST_IP4)), t!(UdpSocket::bind(LOCALHOST_IP4))); + f(t!(UdpSocket::bind(LOCALHOST_IP6)), t!(UdpSocket::bind(LOCALHOST_IP6))); +} + #[test] fn bind_error() { match UdpSocket::bind("1.1.1.1:9999") { @@ -30,18 +30,19 @@ fn bind_error() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn socket_smoke_test_ip4() { - each_ip(&mut |server_ip, client_ip| { + each_ip(&mut |server, client| { + let server_ip = t!(server.local_addr()); + let client_ip = t!(client.local_addr()); + let (tx1, rx1) = channel(); let (tx2, rx2) = channel(); let _t = thread::spawn(move || { - let client = t!(UdpSocket::bind(&client_ip)); rx1.recv().unwrap(); t!(client.send_to(&[99], &server_ip)); tx2.send(()).unwrap(); }); - let server = t!(UdpSocket::bind(&server_ip)); tx1.send(()).unwrap(); let mut buf = [0]; let (nread, src) = t!(server.recv_from(&mut buf)); @@ -53,29 +54,28 @@ fn socket_smoke_test_ip4() { } #[test] -fn socket_name() { - each_ip(&mut |addr, _| { - let server = t!(UdpSocket::bind(&addr)); - assert_eq!(addr, t!(server.local_addr())); - }) -} +fn socket_and_peer_name() { + each_ip(&mut |sock1, sock2| { + let addr1 = t!(sock1.local_addr()); + let addr2 = t!(sock2.local_addr()); -#[test] -fn socket_peer() { - each_ip(&mut |addr1, addr2| { - let server = t!(UdpSocket::bind(&addr1)); - assert_eq!(server.peer_addr().unwrap_err().kind(), ErrorKind::NotConnected); - t!(server.connect(&addr2)); - assert_eq!(addr2, t!(server.peer_addr())); + assert_eq!(sock1.peer_addr().unwrap_err().kind(), ErrorKind::NotConnected); + assert!(addr1.ip() == LOCALHOST_IP4.ip() || addr1.ip() == LOCALHOST_IP6.ip()); + + t!(sock1.connect(addr2)); + t!(sock2.connect(addr1)); + + assert_eq!(addr2, t!(sock1.peer_addr())); + assert_eq!(addr1, t!(sock2.peer_addr())); }) } #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn udp_clone_smoke() { - each_ip(&mut |addr1, addr2| { - let sock1 = t!(UdpSocket::bind(&addr1)); - let sock2 = t!(UdpSocket::bind(&addr2)); + each_ip(&mut |sock1, sock2| { + let addr1 = t!(sock1.local_addr()); + let addr2 = t!(sock2.local_addr()); let _t = thread::spawn(move || { let mut buf = [0, 0]; @@ -107,9 +107,9 @@ fn udp_clone_smoke() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn udp_clone_two_read() { - each_ip(&mut |addr1, addr2| { - let sock1 = t!(UdpSocket::bind(&addr1)); - let sock2 = t!(UdpSocket::bind(&addr2)); + each_ip(&mut |sock1, sock2| { + let addr1 = t!(sock1.local_addr()); + let (tx1, rx) = channel(); let tx2 = tx1.clone(); @@ -140,9 +140,8 @@ fn udp_clone_two_read() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn udp_clone_two_write() { - each_ip(&mut |addr1, addr2| { - let sock1 = t!(UdpSocket::bind(&addr1)); - let sock2 = t!(UdpSocket::bind(&addr2)); + each_ip(&mut |sock1, sock2| { + let addr2 = t!(sock2.local_addr()); let (tx, rx) = channel(); let (serv_tx, serv_rx) = channel(); @@ -177,9 +176,9 @@ fn udp_clone_two_write() { #[test] fn debug() { let name = if cfg!(windows) { "socket" } else { "fd" }; - let socket_addr = next_test_ip4(); - let udpsock = t!(UdpSocket::bind(&socket_addr)); + let udpsock = t!(UdpSocket::bind(LOCALHOST_IP4)); + let socket_addr = t!(udpsock.local_addr()); let udpsock_inner = udpsock.0.socket().as_raw(); let compare = format!("UdpSocket {{ addr: {socket_addr:?}, {name}: {udpsock_inner:?} }}"); assert_eq!(format!("{udpsock:?}"), compare); @@ -189,15 +188,19 @@ fn debug() { // no longer has rounding errors. // VxWorks ignores SO_SNDTIMEO. #[cfg_attr( - any(target_os = "netbsd", target_os = "openbsd", target_os = "vxworks", target_os = "nto"), + any( + target_os = "netbsd", + target_os = "openbsd", + target_os = "vxworks", + target_os = "nto", + target_os = "qnx" + ), ignore )] #[cfg_attr(target_os = "wasi", ignore)] // timeout not supported #[test] fn timeouts() { - let addr = next_test_ip4(); - - let stream = t!(UdpSocket::bind(&addr)); + let stream = t!(UdpSocket::bind(LOCALHOST_IP4)); let dur = Duration::new(15410, 0); assert_eq!(None, t!(stream.read_timeout())); @@ -220,9 +223,7 @@ fn timeouts() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // timeout not supported fn test_read_timeout() { - let addr = next_test_ip4(); - - let stream = t!(UdpSocket::bind(&addr)); + let stream = t!(UdpSocket::bind(LOCALHOST_IP4)); t!(stream.set_read_timeout(Some(Duration::from_millis(1000)))); let mut buf = [0; 10]; @@ -245,9 +246,8 @@ fn test_read_timeout() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // timeout not supported fn test_read_with_timeout() { - let addr = next_test_ip4(); - - let stream = t!(UdpSocket::bind(&addr)); + let stream = t!(UdpSocket::bind(LOCALHOST_IP4)); + let addr = t!(stream.local_addr()); t!(stream.set_read_timeout(Some(Duration::from_millis(1000)))); t!(stream.send_to(b"hello world", &addr)); @@ -275,9 +275,7 @@ fn test_read_with_timeout() { // when passed zero Durations #[test] fn test_timeout_zero_duration() { - let addr = next_test_ip4(); - - let socket = t!(UdpSocket::bind(&addr)); + let socket = t!(UdpSocket::bind(LOCALHOST_IP4)); let result = socket.set_write_timeout(Some(Duration::new(0, 0))); let err = result.unwrap_err(); @@ -290,9 +288,8 @@ fn test_timeout_zero_duration() { #[test] fn connect_send_recv() { - let addr = next_test_ip4(); - - let socket = t!(UdpSocket::bind(&addr)); + let socket = t!(UdpSocket::bind(LOCALHOST_IP4)); + let addr = t!(socket.local_addr()); t!(socket.connect(addr)); t!(socket.send(b"hello world")); @@ -305,8 +302,8 @@ fn connect_send_recv() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // peek not supported fn connect_send_peek_recv() { - each_ip(&mut |addr, _| { - let socket = t!(UdpSocket::bind(&addr)); + each_ip(&mut |socket, _| { + let addr = t!(socket.local_addr()); t!(socket.connect(addr)); t!(socket.send(b"hello world")); @@ -328,8 +325,8 @@ fn connect_send_peek_recv() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // peek_from not supported fn peek_from() { - each_ip(&mut |addr, _| { - let socket = t!(UdpSocket::bind(&addr)); + each_ip(&mut |socket, _| { + let addr = t!(socket.local_addr()); t!(socket.send_to(b"hello world", &addr)); for _ in 1..3 { @@ -350,9 +347,7 @@ fn peek_from() { fn ttl() { let ttl = 100; - let addr = next_test_ip4(); - - let stream = t!(UdpSocket::bind(&addr)); + let stream = t!(UdpSocket::bind(LOCALHOST_IP4)); t!(stream.set_ttl(ttl)); assert_eq!(ttl, t!(stream.ttl())); @@ -360,8 +355,8 @@ fn ttl() { #[test] fn set_nonblocking() { - each_ip(&mut |addr, _| { - let socket = t!(UdpSocket::bind(&addr)); + each_ip(&mut |socket, _| { + let addr = t!(socket.local_addr()); t!(socket.set_nonblocking(true)); t!(socket.set_nonblocking(false)); @@ -379,3 +374,35 @@ fn set_nonblocking() { } }) } + +// #115325: a datagram larger than `c_int::MAX` bytes can't be sent atomically +// and must be rejected rather than truncated. +#[test] +#[cfg(all(target_pointer_width = "64", unix))] +fn send_datagram_larger_than_c_int_max() { + // A read-only anonymous mapping rather than a 2 GiB `Vec`: the datagram is + // rejected before the kernel ever reads the pages, so this costs no + // physical memory. + let data = crate::net::tests::ZeroedMmap::new(crate::ffi::c_int::MAX as usize + 1); + + let socket = t!(UdpSocket::bind("127.0.0.1:0")); + let addr = t!(socket.local_addr()); + assert!(socket.send_to(&data, addr).is_err()); + t!(socket.connect(addr)); + assert!(socket.send(&data).is_err()); +} + +// Same as above, for the platforms where the `mmap` trick isn't available and +// the buffer really has to be allocated. +#[test] +#[cfg(all(target_pointer_width = "64", not(unix)))] +#[ignore = "requires ~2 GiB of memory"] +fn send_datagram_larger_than_c_int_max() { + let data = vec![0u8; crate::ffi::c_int::MAX as usize + 1]; + + let socket = t!(UdpSocket::bind("127.0.0.1:0")); + let addr = t!(socket.local_addr()); + assert!(socket.send_to(&data, addr).is_err()); + t!(socket.connect(addr)); + assert!(socket.send(&data).is_err()); +} diff --git a/library/std/src/num/f128.rs b/library/std/src/num/f128.rs index 6f1fd2975b714..aaf9c1b54efb8 100644 --- a/library/std/src/num/f128.rs +++ b/library/std/src/num/f128.rs @@ -16,6 +16,7 @@ use crate::intrinsics; use crate::sys::cmath; #[cfg(not(test))] +#[doc(test(attr(allow(unused_features))))] impl f128 { /// Raises a number to a floating point power. /// @@ -33,7 +34,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = 2.0_f128; @@ -64,7 +64,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let one = 1.0f128; @@ -96,7 +95,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let f = 2.0f128; @@ -128,7 +126,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let one = 1.0f128; @@ -145,7 +142,6 @@ impl f128 { /// Non-positive values: /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// assert_eq!(0_f128.ln(), f128::NEG_INFINITY); @@ -177,7 +173,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let five = 5.0f128; @@ -192,7 +187,6 @@ impl f128 { /// Non-positive values: /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// assert_eq!(0_f128.log(10.0), f128::NEG_INFINITY); @@ -220,7 +214,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let two = 2.0f128; @@ -235,7 +228,6 @@ impl f128 { /// Non-positive values: /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// assert_eq!(0_f128.log2(), f128::NEG_INFINITY); @@ -263,7 +255,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let ten = 10.0f128; @@ -278,7 +269,6 @@ impl f128 { /// Non-positive values: /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// assert_eq!(0_f128.log10(), f128::NEG_INFINITY); @@ -308,7 +298,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = 8.0f128; @@ -345,7 +334,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = 2.0f128; @@ -376,7 +364,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = std::f128::consts::FRAC_PI_2; @@ -405,7 +392,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = 2.0 * std::f128::consts::PI; @@ -437,7 +423,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = std::f128::consts::FRAC_PI_4; @@ -470,7 +455,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let f = std::f128::consts::FRAC_PI_4; @@ -506,7 +490,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let f = std::f128::consts::FRAC_PI_4; @@ -541,7 +524,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let f = 1.0f128; @@ -582,7 +564,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// // Positive angles measured counter-clockwise @@ -625,7 +606,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = std::f128::consts::FRAC_PI_4; @@ -642,6 +622,7 @@ impl f128 { #[doc(alias = "sincos")] #[rustc_allow_incoherent_impl] #[unstable(feature = "f128", issue = "116909")] + #[must_use = "this returns the result of the operation, without modifying the original"] pub fn sin_cos(self) -> (f128, f128) { (self.sin(), self.cos()) } @@ -661,7 +642,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = 1e-8_f128; @@ -698,7 +678,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = 1e-8_f128; @@ -714,7 +693,6 @@ impl f128 { /// Out-of-range values: /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// assert_eq!((-1.0_f128).ln_1p(), f128::NEG_INFINITY); @@ -744,7 +722,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let e = std::f128::consts::E; @@ -780,7 +757,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let e = std::f128::consts::E; @@ -816,7 +792,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let e = std::f128::consts::E; @@ -849,7 +824,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = 1.0f128; @@ -866,9 +840,7 @@ impl f128 { #[unstable(feature = "f128", issue = "116909")] #[must_use = "method returns a new number and does not mutate the original value"] pub fn asinh(self) -> f128 { - let ax = self.abs(); - let ix = 1.0 / ax; - (ax + (ax / (Self::hypot(1.0, ix) + ix))).ln_1p().copysign(self) + cmath::asinhf128(self) } /// Inverse hyperbolic cosine function. @@ -882,7 +854,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = 1.0f128; @@ -899,11 +870,7 @@ impl f128 { #[unstable(feature = "f128", issue = "116909")] #[must_use = "method returns a new number and does not mutate the original value"] pub fn acosh(self) -> f128 { - if self < 1.0 { - Self::NAN - } else { - (self + ((self - 1.0).sqrt() * (self + 1.0).sqrt())).ln() - } + cmath::acoshf128(self) } /// Inverse hyperbolic tangent function. @@ -917,7 +884,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = std::f128::consts::FRAC_PI_6; @@ -952,7 +918,6 @@ impl f128 { /// ``` /// #![feature(f128)] /// #![feature(float_gamma)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = 5.0f128; @@ -988,7 +953,6 @@ impl f128 { /// ``` /// #![feature(f128)] /// #![feature(float_gamma)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = 2.0f128; @@ -1024,7 +988,6 @@ impl f128 { /// ``` /// #![feature(f128)] /// #![feature(float_erf)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// The error function relates what percent of a normal distribution lies /// /// within `x` standard deviations (scaled by `1/sqrt(2)`). @@ -1064,7 +1027,6 @@ impl f128 { /// ``` /// #![feature(f128)] /// #![feature(float_erf)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// let x: f128 = 0.123; /// diff --git a/library/std/src/num/f16.rs b/library/std/src/num/f16.rs index 20d0b4e1e552b..4a7493fb5a5ed 100644 --- a/library/std/src/num/f16.rs +++ b/library/std/src/num/f16.rs @@ -16,6 +16,7 @@ use crate::intrinsics; use crate::sys::cmath; #[cfg(not(test))] +#[doc(test(attr(allow(unused_features))))] impl f16 { /// Raises a number to a floating point power. /// @@ -33,12 +34,11 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = 2.0_f16; /// let abs_difference = (x.powf(2.0) - (x * x)).abs(); - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-1); /// /// assert_eq!(f16::powf(1.0, f16::NAN), 1.0); /// assert_eq!(f16::powf(f16::NAN, 0.0), 1.0); @@ -64,7 +64,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let one = 1.0f16; @@ -74,7 +73,7 @@ impl f16 { /// // ln(e) - 1 == 0 /// let abs_difference = (e.ln() - 1.0).abs(); /// - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-2); /// # } /// ``` #[inline] @@ -96,7 +95,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let f = 2.0f16; @@ -104,7 +102,7 @@ impl f16 { /// // 2^2 - 4 == 0 /// let abs_difference = (f.exp2() - 4.0).abs(); /// - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-1); /// # } /// ``` #[inline] @@ -128,7 +126,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let one = 1.0f16; @@ -138,14 +135,13 @@ impl f16 { /// // ln(e) - 1 == 0 /// let abs_difference = (e.ln() - 1.0).abs(); /// - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-2); /// # } /// ``` /// /// Non-positive values: /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// assert_eq!(0_f16.ln(), f16::NEG_INFINITY); @@ -177,7 +173,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let five = 5.0f16; @@ -185,14 +180,13 @@ impl f16 { /// // log5(5) - 1 == 0 /// let abs_difference = (five.log(5.0) - 1.0).abs(); /// - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-2); /// # } /// ``` /// /// Non-positive values: /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// assert_eq!(0_f16.log(10.0), f16::NEG_INFINITY); @@ -220,7 +214,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let two = 2.0f16; @@ -228,14 +221,13 @@ impl f16 { /// // log2(2) - 1 == 0 /// let abs_difference = (two.log2() - 1.0).abs(); /// - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-2); /// # } /// ``` /// /// Non-positive values: /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// assert_eq!(0_f16.log2(), f16::NEG_INFINITY); @@ -263,7 +255,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let ten = 10.0f16; @@ -271,14 +262,13 @@ impl f16 { /// // log10(10) - 1 == 0 /// let abs_difference = (ten.log10() - 1.0).abs(); /// - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-2); /// # } /// ``` /// /// Non-positive values: /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// assert_eq!(0_f16.log10(), f16::NEG_INFINITY); @@ -310,7 +300,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = 2.0f16; @@ -319,7 +308,7 @@ impl f16 { /// // sqrt(x^2 + y^2) /// let abs_difference = (x.hypot(y) - (x.powi(2) + y.powi(2)).sqrt()).abs(); /// - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-2); /// # } /// ``` #[inline] @@ -341,14 +330,13 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = std::f16::consts::FRAC_PI_2; /// /// let abs_difference = (x.sin() - 1.0).abs(); /// - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-2); /// # } /// ``` #[inline] @@ -370,14 +358,13 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = 2.0 * std::f16::consts::PI; /// /// let abs_difference = (x.cos() - 1.0).abs(); /// - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-2); /// # } /// ``` #[inline] @@ -402,7 +389,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = std::f16::consts::FRAC_PI_4; @@ -435,7 +421,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let f = std::f16::consts::FRAC_PI_4; @@ -443,7 +428,7 @@ impl f16 { /// // asin(sin(pi/2)) /// let abs_difference = (f.sin().asin() - f).abs(); /// - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-2); /// # } /// ``` #[inline] @@ -471,7 +456,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let f = std::f16::consts::FRAC_PI_4; @@ -479,7 +463,7 @@ impl f16 { /// // acos(cos(pi/4)) /// let abs_difference = (f.cos().acos() - std::f16::consts::FRAC_PI_4).abs(); /// - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-2); /// # } /// ``` #[inline] @@ -506,7 +490,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let f = 1.0f16; @@ -547,7 +530,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// // Positive angles measured counter-clockwise @@ -590,7 +572,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = std::f16::consts::FRAC_PI_4; @@ -599,14 +580,15 @@ impl f16 { /// let abs_difference_0 = (f.0 - x.sin()).abs(); /// let abs_difference_1 = (f.1 - x.cos()).abs(); /// - /// assert!(abs_difference_0 <= f16::EPSILON); - /// assert!(abs_difference_1 <= f16::EPSILON); + /// assert!(abs_difference_0 <= 1e-2); + /// assert!(abs_difference_1 <= 1e-2); /// # } /// ``` #[inline] #[doc(alias = "sincos")] #[rustc_allow_incoherent_impl] #[unstable(feature = "f16", issue = "116909")] + #[must_use = "this returns the result of the operation, without modifying the original"] pub fn sin_cos(self) -> (f16, f16) { (self.sin(), self.cos()) } @@ -626,7 +608,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = 1e-4_f16; @@ -663,7 +644,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = 1e-4_f16; @@ -679,7 +659,6 @@ impl f16 { /// Out-of-range values: /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// assert_eq!((-1.0_f16).ln_1p(), f16::NEG_INFINITY); @@ -709,7 +688,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let e = std::f16::consts::E; @@ -745,7 +723,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let e = std::f16::consts::E; @@ -781,7 +758,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let e = std::f16::consts::E; @@ -814,7 +790,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = 1.0f16; @@ -831,9 +806,7 @@ impl f16 { #[unstable(feature = "f16", issue = "116909")] #[must_use = "method returns a new number and does not mutate the original value"] pub fn asinh(self) -> f16 { - let ax = self.abs(); - let ix = 1.0 / ax; - (ax + (ax / (Self::hypot(1.0, ix) + ix))).ln_1p().copysign(self) + cmath::asinhf(self as f32) as f16 } /// Inverse hyperbolic cosine function. @@ -847,7 +820,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = 1.0f16; @@ -864,11 +836,7 @@ impl f16 { #[unstable(feature = "f16", issue = "116909")] #[must_use = "method returns a new number and does not mutate the original value"] pub fn acosh(self) -> f16 { - if self < 1.0 { - Self::NAN - } else { - (self + ((self - 1.0).sqrt() * (self + 1.0).sqrt())).ln() - } + cmath::acoshf(self as f32) as f16 } /// Inverse hyperbolic tangent function. @@ -882,7 +850,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = std::f16::consts::FRAC_PI_6; @@ -916,8 +883,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// #![feature(float_gamma)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = 5.0f16; @@ -952,8 +917,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// #![feature(float_gamma)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = 2.0f16; @@ -988,8 +951,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// #![feature(float_erf)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// The error function relates what percent of a normal distribution lies /// /// within `x` standard deviations (scaled by `1/sqrt(2)`). @@ -1028,8 +989,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// #![feature(float_erf)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// let x: f16 = 0.123; /// diff --git a/library/std/src/num/f32.rs b/library/std/src/num/f32.rs index 77e6824784605..385533748cb5d 100644 --- a/library/std/src/num/f32.rs +++ b/library/std/src/num/f32.rs @@ -13,7 +13,7 @@ #![allow(missing_docs)] #[stable(feature = "rust1", since = "1.0.0")] -#[allow(deprecated, deprecated_in_future)] +#[allow(deprecated, deprecated_in_future, clippy::legacy_numeric_constants)] pub use core::f32::{ DIGITS, EPSILON, INFINITY, MANTISSA_DIGITS, MAX, MAX_10_EXP, MAX_EXP, MIN, MIN_10_EXP, MIN_EXP, MIN_POSITIVE, NAN, NEG_INFINITY, RADIX, consts, @@ -26,7 +26,7 @@ use crate::sys::cmath; #[cfg(not(test))] impl f32 { - /// Returns the largest integer less than or equal to `self`. + /// Returns the largest integer that is less than or equal to `self`. /// /// This function always returns the precise result. /// @@ -50,7 +50,7 @@ impl f32 { core::f32::math::floor(self) } - /// Returns the smallest integer greater than or equal to `self`. + /// Returns the smallest integer that is greater than or equal to `self`. /// /// This function always returns the precise result. /// @@ -59,9 +59,11 @@ impl f32 { /// ``` /// let f = 3.01_f32; /// let g = 4.0_f32; + /// let h = -3.01_f32; /// /// assert_eq!(f.ceil(), 4.0); /// assert_eq!(g.ceil(), 4.0); + /// assert_eq!(h.ceil(), -3.0); /// ``` #[doc(alias = "ceiling")] #[rustc_allow_incoherent_impl] @@ -907,6 +909,7 @@ impl f32 { #[rustc_allow_incoherent_impl] #[stable(feature = "rust1", since = "1.0.0")] #[inline] + #[must_use = "this returns the result of the operation, without modifying the original"] pub fn sin_cos(self) -> (f32, f32) { (self.sin(), self.cos()) } @@ -1091,9 +1094,7 @@ impl f32 { #[stable(feature = "rust1", since = "1.0.0")] #[inline] pub fn asinh(self) -> f32 { - let ax = self.abs(); - let ix = 1.0 / ax; - (ax + (ax / (Self::hypot(1.0, ix) + ix))).ln_1p().copysign(self) + cmath::asinhf(self) } /// Inverse hyperbolic cosine function. @@ -1119,11 +1120,7 @@ impl f32 { #[stable(feature = "rust1", since = "1.0.0")] #[inline] pub fn acosh(self) -> f32 { - if self < 1.0 { - Self::NAN - } else { - (self + ((self - 1.0).sqrt() * (self + 1.0).sqrt())).ln() - } + cmath::acoshf(self) } /// Inverse hyperbolic tangent function. diff --git a/library/std/src/num/f64.rs b/library/std/src/num/f64.rs index e0b9948a924db..66482a8b654a5 100644 --- a/library/std/src/num/f64.rs +++ b/library/std/src/num/f64.rs @@ -13,7 +13,7 @@ #![allow(missing_docs)] #[stable(feature = "rust1", since = "1.0.0")] -#[allow(deprecated, deprecated_in_future)] +#[allow(deprecated, deprecated_in_future, clippy::legacy_numeric_constants)] pub use core::f64::{ DIGITS, EPSILON, INFINITY, MANTISSA_DIGITS, MAX, MAX_10_EXP, MAX_EXP, MIN, MIN_10_EXP, MIN_EXP, MIN_POSITIVE, NAN, NEG_INFINITY, RADIX, consts, @@ -26,7 +26,7 @@ use crate::sys::cmath; #[cfg(not(test))] impl f64 { - /// Returns the largest integer less than or equal to `self`. + /// Returns the largest integer that is less than or equal to `self`. /// /// This function always returns the precise result. /// @@ -50,7 +50,7 @@ impl f64 { core::f64::math::floor(self) } - /// Returns the smallest integer greater than or equal to `self`. + /// Returns the smallest integer that is greater than or equal to `self`. /// /// This function always returns the precise result. /// @@ -59,9 +59,11 @@ impl f64 { /// ``` /// let f = 3.01_f64; /// let g = 4.0_f64; + /// let h = -3.01_f64; /// /// assert_eq!(f.ceil(), 4.0); /// assert_eq!(g.ceil(), 4.0); + /// assert_eq!(h.ceil(), -3.0); /// ``` #[doc(alias = "ceiling")] #[rustc_allow_incoherent_impl] @@ -907,6 +909,7 @@ impl f64 { #[rustc_allow_incoherent_impl] #[stable(feature = "rust1", since = "1.0.0")] #[inline] + #[must_use = "this returns the result of the operation, without modifying the original"] pub fn sin_cos(self) -> (f64, f64) { (self.sin(), self.cos()) } @@ -1091,9 +1094,7 @@ impl f64 { #[stable(feature = "rust1", since = "1.0.0")] #[inline] pub fn asinh(self) -> f64 { - let ax = self.abs(); - let ix = 1.0 / ax; - (ax + (ax / (Self::hypot(1.0, ix) + ix))).ln_1p().copysign(self) + cmath::asinh(self) } /// Inverse hyperbolic cosine function. @@ -1119,11 +1120,7 @@ impl f64 { #[stable(feature = "rust1", since = "1.0.0")] #[inline] pub fn acosh(self) -> f64 { - if self < 1.0 { - Self::NAN - } else { - (self + ((self - 1.0).sqrt() * (self + 1.0).sqrt())).ln() - } + cmath::acosh(self) } /// Inverse hyperbolic tangent function. diff --git a/library/std/src/num/mod.rs b/library/std/src/num/mod.rs index ffb8789c906ef..5aa6c1492ec65 100644 --- a/library/std/src/num/mod.rs +++ b/library/std/src/num/mod.rs @@ -6,6 +6,8 @@ #![stable(feature = "rust1", since = "1.0.0")] #![allow(missing_docs)] +#[unstable(feature = "complex_numbers", issue = "154023")] +pub use core::num::Complex; #[stable(feature = "int_error_matching", since = "1.55.0")] pub use core::num::IntErrorKind; #[stable(feature = "generic_nonzero", since = "1.79.0")] diff --git a/library/std/src/os/aix/fs.rs b/library/std/src/os/aix/fs.rs index 2a940c6b9c97c..1a56736a38d54 100644 --- a/library/std/src/os/aix/fs.rs +++ b/library/std/src/os/aix/fs.rs @@ -16,7 +16,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "aix", doc = "```no_run")] + #[cfg_attr(not(target_os = "aix"), doc = "```ignore (needs aix)")] /// use std::fs; /// use std::io; /// use std::os::aix::fs::MetadataExt; @@ -33,7 +34,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "aix", doc = "```no_run")] + #[cfg_attr(not(target_os = "aix"), doc = "```ignore (needs aix)")] /// use std::fs; /// use std::io; /// use std::os::aix::fs::MetadataExt; @@ -50,7 +52,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "aix", doc = "```no_run")] + #[cfg_attr(not(target_os = "aix"), doc = "```ignore (needs aix)")] /// use std::fs; /// use std::io; /// use std::os::aix::fs::MetadataExt; @@ -67,7 +70,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "aix", doc = "```no_run")] + #[cfg_attr(not(target_os = "aix"), doc = "```ignore (needs aix)")] /// use std::fs; /// use std::io; /// use std::os::aix::fs::MetadataExt; @@ -84,7 +88,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "aix", doc = "```no_run")] + #[cfg_attr(not(target_os = "aix"), doc = "```ignore (needs aix)")] /// use std::fs; /// use std::io; /// use std::os::aix::fs::MetadataExt; @@ -101,7 +106,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "aix", doc = "```no_run")] + #[cfg_attr(not(target_os = "aix"), doc = "```ignore (needs aix)")] /// use std::fs; /// use std::io; /// use std::os::aix::fs::MetadataExt; @@ -118,7 +124,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "aix", doc = "```no_run")] + #[cfg_attr(not(target_os = "aix"), doc = "```ignore (needs aix)")] /// use std::fs; /// use std::io; /// use std::os::aix::fs::MetadataExt; @@ -138,7 +145,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "aix", doc = "```no_run")] + #[cfg_attr(not(target_os = "aix"), doc = "```ignore (needs aix)")] /// use std::fs; /// use std::io; /// use std::os::aix::fs::MetadataExt; @@ -155,7 +163,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "aix", doc = "```no_run")] + #[cfg_attr(not(target_os = "aix"), doc = "```ignore (needs aix)")] /// use std::fs; /// use std::io; /// use std::os::aix::fs::MetadataExt; @@ -174,7 +183,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "aix", doc = "```no_run")] + #[cfg_attr(not(target_os = "aix"), doc = "```ignore (needs aix)")] /// use std::fs; /// use std::io; /// use std::os::aix::fs::MetadataExt; @@ -191,7 +201,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "aix", doc = "```no_run")] + #[cfg_attr(not(target_os = "aix"), doc = "```ignore (needs aix)")] /// use std::fs; /// use std::io; /// use std::os::aix::fs::MetadataExt; @@ -210,7 +221,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "aix", doc = "```no_run")] + #[cfg_attr(not(target_os = "aix"), doc = "```ignore (needs aix)")] /// use std::fs; /// use std::io; /// use std::os::aix::fs::MetadataExt; @@ -227,7 +239,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "aix", doc = "```no_run")] + #[cfg_attr(not(target_os = "aix"), doc = "```ignore (needs aix)")] /// use std::fs; /// use std::io; /// use std::os::aix::fs::MetadataExt; @@ -246,7 +259,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "aix", doc = "```no_run")] + #[cfg_attr(not(target_os = "aix"), doc = "```ignore (needs aix)")] /// use std::fs; /// use std::io; /// use std::os::aix::fs::MetadataExt; @@ -263,7 +277,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "aix", doc = "```no_run")] + #[cfg_attr(not(target_os = "aix"), doc = "```ignore (needs aix)")] /// use std::fs; /// use std::io; /// use std::os::aix::fs::MetadataExt; @@ -280,7 +295,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "aix", doc = "```no_run")] + #[cfg_attr(not(target_os = "aix"), doc = "```ignore (needs aix)")] /// use std::fs; /// use std::io; /// use std::os::aix::fs::MetadataExt; @@ -322,22 +338,22 @@ impl MetadataExt for Metadata { self.as_inner().as_inner().st_size as u64 } fn st_atime(&self) -> i64 { - self.as_inner().as_inner().st_atime.tv_sec as i64 + self.as_inner().as_inner().st_atim.tv_sec as i64 } fn st_atime_nsec(&self) -> i64 { - self.as_inner().as_inner().st_atime.tv_nsec as i64 + self.as_inner().as_inner().st_atim.tv_nsec as i64 } fn st_mtime(&self) -> i64 { - self.as_inner().as_inner().st_mtime.tv_sec as i64 + self.as_inner().as_inner().st_mtim.tv_sec as i64 } fn st_mtime_nsec(&self) -> i64 { - self.as_inner().as_inner().st_mtime.tv_nsec as i64 + self.as_inner().as_inner().st_mtim.tv_nsec as i64 } fn st_ctime(&self) -> i64 { - self.as_inner().as_inner().st_ctime.tv_sec as i64 + self.as_inner().as_inner().st_ctim.tv_sec as i64 } fn st_ctime_nsec(&self) -> i64 { - self.as_inner().as_inner().st_ctime.tv_nsec as i64 + self.as_inner().as_inner().st_ctim.tv_nsec as i64 } fn st_blksize(&self) -> u64 { self.as_inner().as_inner().st_blksize as u64 diff --git a/library/std/src/os/darwin/fs.rs b/library/std/src/os/darwin/fs.rs index af98e069b41a3..fc2869d6b13f6 100644 --- a/library/std/src/os/darwin/fs.rs +++ b/library/std/src/os/darwin/fs.rs @@ -4,7 +4,6 @@ #![stable(feature = "metadata_ext", since = "1.1.0")] use crate::fs::{self, Metadata}; -use crate::sealed::Sealed; use crate::sys::{AsInner, AsInnerMut, IntoInner}; use crate::time::SystemTime; @@ -157,7 +156,7 @@ impl MetadataExt for Metadata { /// OS-specific extensions to [`fs::FileTimes`]. #[stable(feature = "file_set_times", since = "1.75.0")] -pub trait FileTimesExt: Sealed { +pub impl(self) trait FileTimesExt { /// Set the creation time of a file. #[stable(feature = "file_set_times", since = "1.75.0")] fn set_created(self, t: SystemTime) -> Self; diff --git a/library/std/src/os/fd/mod.rs b/library/std/src/os/fd/mod.rs index 95cf4932e6e2c..735f1cf8925fb 100644 --- a/library/std/src/os/fd/mod.rs +++ b/library/std/src/os/fd/mod.rs @@ -16,7 +16,11 @@ mod owned; #[cfg(not(target_os = "trusty"))] mod net; +// Implementation of stdio file descriptor constants. +mod stdio; + #[cfg(test)] +#[cfg(not(target_os = "l4re"))] mod tests; // Export the types and traits for the public API. @@ -24,3 +28,5 @@ mod tests; pub use owned::*; #[stable(feature = "os_fd", since = "1.66.0")] pub use raw::*; +#[unstable(feature = "stdio_fd_consts", issue = "150836")] +pub use stdio::*; diff --git a/library/std/src/os/fd/owned.rs b/library/std/src/os/fd/owned.rs index 8a39fe073bf95..4ed5c43616a29 100644 --- a/library/std/src/os/fd/owned.rs +++ b/library/std/src/os/fd/owned.rs @@ -12,7 +12,7 @@ use crate::fs; use crate::marker::PhantomData; use crate::mem::ManuallyDrop; #[cfg(not(any( - target_arch = "wasm32", + all(target_arch = "wasm32", not(target_os = "emscripten")), target_env = "sgx", target_os = "hermit", target_os = "trusty", @@ -104,7 +104,7 @@ impl BorrowedFd<'_> { /// Creates a new `OwnedFd` instance that shares the same underlying file /// description as the existing `BorrowedFd` instance. #[cfg(not(any( - target_arch = "wasm32", + all(target_arch = "wasm32", not(target_os = "emscripten")), target_os = "hermit", target_os = "trusty", target_os = "motor" @@ -131,7 +131,11 @@ impl BorrowedFd<'_> { /// Creates a new `OwnedFd` instance that shares the same underlying file /// description as the existing `BorrowedFd` instance. - #[cfg(any(target_arch = "wasm32", target_os = "hermit", target_os = "trusty"))] + #[cfg(any( + all(target_arch = "wasm32", not(target_os = "emscripten")), + target_os = "hermit", + target_os = "trusty" + ))] #[stable(feature = "io_safety", since = "1.63.0")] pub fn try_clone_to_owned(&self) -> io::Result { Err(io::Error::UNSUPPORTED_PLATFORM) @@ -199,7 +203,7 @@ impl Drop for OwnedFd { unsafe { // Note that errors are ignored when closing a file descriptor. According to POSIX 2024, // we can and indeed should retry `close` on `EINTR` - // (https://pubs.opengroup.org/onlinepubs/9799919799.2024edition/functions/close.html), + // (https://pubs.opengroup.org/onlinepubs/9799919799/functions/close.html), // but it is not clear yet how well widely-used implementations are conforming with this // mandate since older versions of POSIX left the state of the FD after an `EINTR` // unspecified. Ignoring errors is "fine" because some of the major Unices (in @@ -237,9 +241,6 @@ impl fmt::Debug for OwnedFd { macro_rules! impl_is_terminal { ($($t:ty),*$(,)?) => {$( - #[unstable(feature = "sealed", issue = "none")] - impl crate::sealed::Sealed for $t {} - #[stable(feature = "is_terminal", since = "1.70.0")] impl io::IsTerminal for $t { #[inline] @@ -358,7 +359,7 @@ impl From for OwnedFd { /// Takes ownership of a [`TcpStream`](crate::net::TcpStream)'s socket file descriptor. #[inline] fn from(tcp_stream: crate::net::TcpStream) -> OwnedFd { - tcp_stream.into_inner().into_socket().into_inner().into_inner().into() + tcp_stream.into_inner().into_socket().into_inner().into_inner() } } @@ -388,7 +389,7 @@ impl From for OwnedFd { /// Takes ownership of a [`TcpListener`](crate::net::TcpListener)'s socket file descriptor. #[inline] fn from(tcp_listener: crate::net::TcpListener) -> OwnedFd { - tcp_listener.into_inner().into_socket().into_inner().into_inner().into() + tcp_listener.into_inner().into_socket().into_inner().into_inner() } } @@ -418,7 +419,7 @@ impl From for OwnedFd { /// Takes ownership of a [`UdpSocket`](crate::net::UdpSocket)'s file descriptor. #[inline] fn from(udp_socket: crate::net::UdpSocket) -> OwnedFd { - udp_socket.into_inner().into_socket().into_inner().into_inner().into() + udp_socket.into_inner().into_socket().into_inner().into_inner() } } diff --git a/library/std/src/os/fd/raw.rs b/library/std/src/os/fd/raw.rs index 39e374174646c..a0c96e2836fc5 100644 --- a/library/std/src/os/fd/raw.rs +++ b/library/std/src/os/fd/raw.rs @@ -16,7 +16,7 @@ use crate::io; use crate::os::hermit::io::OwnedFd; #[cfg(all(not(target_os = "hermit"), not(target_os = "motor")))] use crate::os::raw; -#[cfg(all(doc, not(target_arch = "wasm32")))] +#[cfg(all(doc, not(any(target_arch = "wasm32", target_env = "sgx", target_os = "l4re"))))] use crate::os::unix::io::AsFd; #[cfg(unix)] use crate::os::unix::io::OwnedFd; diff --git a/library/std/src/os/fd/stdio.rs b/library/std/src/os/fd/stdio.rs new file mode 100644 index 0000000000000..c50cbd39849b7 --- /dev/null +++ b/library/std/src/os/fd/stdio.rs @@ -0,0 +1,53 @@ +use super::BorrowedFd; + +/// The file descriptor for the standard input stream of the current process. +/// +/// See [`io::stdin()`][`crate::io::stdin`] for the higher level handle, which should be preferred +/// whenever possible. See [`STDERR`] for why the file descriptor might be required and caveats. +#[unstable(feature = "stdio_fd_consts", issue = "150836")] +pub const STDIN: BorrowedFd<'static> = unsafe { BorrowedFd::borrow_raw(0) }; + +/// The file descriptor for the standard output stream of the current process. +/// +/// See [`io::stdout()`][`crate::io::stdout`] for the higher level handle, which should be preferred +/// whenever possible. See [`STDERR`] for why the file descriptor might be required and caveats. In +/// addition to the issues discussed there, note that [`Stdout`][`crate::io::Stdout`] is buffered by +/// default, and writing to the file descriptor will bypass this buffer. +#[unstable(feature = "stdio_fd_consts", issue = "150836")] +pub const STDOUT: BorrowedFd<'static> = unsafe { BorrowedFd::borrow_raw(1) }; + +/// The file descriptor for the standard error stream of the current process. +/// +/// See [`io::stderr()`][`crate::io::stderr`] for the higher level handle, which should be preferred +/// whenever possible. However, there are situations where touching the `std::io` handles (or most +/// other parts of the standard library) risks deadlocks or other subtle bugs. For example: +/// +/// - Global allocators must be careful to [avoid reentrancy][global-alloc-reentrancy], and the +/// `std::io` handles may allocate memory on (some) accesses. +/// - Signal handlers must be *async-signal-safe*, which rules out panicking, taking locks (may +/// deadlock if the signal handler interrupted a thread holding that lock), allocating memory, or +/// anything else that is not explicitly declared async-signal-safe. +/// - `CommandExt::pre_exec` callbacks can safely panic (with some limitations), but otherwise must +/// abide by similar limitations as signal handlers. In particular, at the time these callbacks +/// run, the stdio file descriptors have already been replaced, but the locks protecting the +/// `std::io` handles may be permanently locked if another thread held the lock at `fork()` time. +/// +/// In these and similar cases, direct access to the file descriptor may be required. However, in +/// most cases, using the `std::io` handles and accessing the file descriptor via the `AsFd` +/// implementations is preferable, as it enables cooperation with the standard library's locking and +/// buffering. +/// +/// # I/O safety +/// +/// This is a `BorrowedFd<'static>` because the standard input/output/error streams are shared +/// resources that must remain available for the lifetime of the process. This is only true when +/// linking `std`, and may not always hold for [code running before `main()`][before-after-main] or +/// in `no_std` environments. It is [unsound][io-safety] to close these file descriptors. Safe +/// patterns for changing these file descriptors are available on Unix via the `StdioExt` extension +/// trait. +/// +/// [before-after-main]: ../../../std/index.html#use-before-and-after-main +/// [io-safety]: ../../../std/io/index.html#io-safety +/// [global-alloc-reentrancy]: ../../../std/alloc/trait.GlobalAlloc.html#re-entrance +#[unstable(feature = "stdio_fd_consts", issue = "150836")] +pub const STDERR: BorrowedFd<'static> = unsafe { BorrowedFd::borrow_raw(2) }; diff --git a/library/std/src/os/fortanix_sgx/ffi.rs b/library/std/src/os/fortanix_sgx/ffi.rs index ac1db0e5e39cc..c2d71eada095f 100644 --- a/library/std/src/os/fortanix_sgx/ffi.rs +++ b/library/std/src/os/fortanix_sgx/ffi.rs @@ -2,7 +2,11 @@ //! //! # Examples //! -//! ``` +#![cfg_attr(all(target_vendor = "fortanix", target_env = "sgx"), doc = "```")] +#![cfg_attr( + not(all(target_vendor = "fortanix", target_env = "sgx")), + doc = "```ignore (needs aix)" +)] //! use std::ffi::OsString; //! use std::os::fortanix_sgx::ffi::OsStringExt; //! @@ -17,7 +21,11 @@ //! assert_eq!(bytes, b"foo"); //! ``` //! -//! ``` +#![cfg_attr(all(target_vendor = "fortanix", target_env = "sgx"), doc = "```")] +#![cfg_attr( + not(all(target_vendor = "fortanix", target_env = "sgx")), + doc = "```ignore (needs aix)" +)] //! use std::ffi::OsStr; //! use std::os::fortanix_sgx::ffi::OsStrExt; //! diff --git a/library/std/src/os/freebsd/net.rs b/library/std/src/os/freebsd/net.rs index f759b91921b55..550696e9536dd 100644 --- a/library/std/src/os/freebsd/net.rs +++ b/library/std/src/os/freebsd/net.rs @@ -5,7 +5,6 @@ use crate::ffi::CStr; use crate::io; use crate::os::unix::net; -use crate::sealed::Sealed; use crate::sys::AsInner; /// FreeBSD-specific functionality for `AF_UNIX` sockets [`UnixDatagram`] @@ -14,7 +13,7 @@ use crate::sys::AsInner; /// [`UnixDatagram`]: net::UnixDatagram /// [`UnixStream`]: net::UnixStream #[unstable(feature = "unix_socket_ancillary_data", issue = "76915")] -pub trait UnixSocketExt: Sealed { +pub impl(self) trait UnixSocketExt { /// Query the current setting of socket option `LOCAL_CREDS_PERSISTENT`. #[unstable(feature = "unix_socket_ancillary_data", issue = "76915")] fn local_creds_persistent(&self) -> io::Result; @@ -28,7 +27,8 @@ pub trait UnixSocketExt: Sealed { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "freebsd", doc = "```no_run")] + #[cfg_attr(not(target_os = "freebsd"), doc = "```ignore (needs freebsd)")] /// #![feature(unix_socket_ancillary_data)] /// use std::os::freebsd::net::UnixSocketExt; /// use std::os::unix::net::UnixDatagram; diff --git a/library/std/src/os/hermit/ffi.rs b/library/std/src/os/hermit/ffi.rs index 19761fd99b400..d6be3c4615816 100644 --- a/library/std/src/os/hermit/ffi.rs +++ b/library/std/src/os/hermit/ffi.rs @@ -1,8 +1,9 @@ -//! HermitCore-specific extension to the primitives in the `std::ffi` module +//! Hermit-specific extension to the primitives in the `std::ffi` module //! //! # Examples //! -//! ``` +#![cfg_attr(target_os = "hermit", doc = "```")] +#![cfg_attr(not(target_os = "hermit"), doc = "```ignore (needs hermit)")] //! use std::ffi::OsString; //! use std::os::hermit::ffi::OsStringExt; //! @@ -17,7 +18,8 @@ //! assert_eq!(bytes, b"foo"); //! ``` //! -//! ``` +#![cfg_attr(target_os = "hermit", doc = "```")] +#![cfg_attr(not(target_os = "hermit"), doc = "```ignore (needs hermit)")] //! use std::ffi::OsStr; //! use std::os::hermit::ffi::OsStrExt; //! diff --git a/library/std/src/os/hurd/fs.rs b/library/std/src/os/hurd/fs.rs index e0fc544fed1db..dc6f61180cb1b 100644 --- a/library/std/src/os/hurd/fs.rs +++ b/library/std/src/os/hurd/fs.rs @@ -16,7 +16,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "hurd", doc = "```no_run")] + #[cfg_attr(not(target_os = "hurd"), doc = "```ignore (needs hurd)")] /// use std::fs; /// use std::io; /// use std::os::hurd::fs::MetadataExt; @@ -33,7 +34,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "hurd", doc = "```no_run")] + #[cfg_attr(not(target_os = "hurd"), doc = "```ignore (needs hurd)")] /// use std::fs; /// use std::io; /// use std::os::hurd::fs::MetadataExt; @@ -50,7 +52,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "hurd", doc = "```no_run")] + #[cfg_attr(not(target_os = "hurd"), doc = "```ignore (needs hurd)")] /// use std::fs; /// use std::io; /// use std::os::hurd::fs::MetadataExt; @@ -67,7 +70,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "hurd", doc = "```no_run")] + #[cfg_attr(not(target_os = "hurd"), doc = "```ignore (needs hurd)")] /// use std::fs; /// use std::io; /// use std::os::hurd::fs::MetadataExt; @@ -84,7 +88,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "hurd", doc = "```no_run")] + #[cfg_attr(not(target_os = "hurd"), doc = "```ignore (needs hurd)")] /// use std::fs; /// use std::io; /// use std::os::hurd::fs::MetadataExt; @@ -101,7 +106,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "hurd", doc = "```no_run")] + #[cfg_attr(not(target_os = "hurd"), doc = "```ignore (needs hurd)")] /// use std::fs; /// use std::io; /// use std::os::hurd::fs::MetadataExt; @@ -118,7 +124,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "hurd", doc = "```no_run")] + #[cfg_attr(not(target_os = "hurd"), doc = "```ignore (needs hurd)")] /// use std::fs; /// use std::io; /// use std::os::hurd::fs::MetadataExt; @@ -138,7 +145,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "hurd", doc = "```no_run")] + #[cfg_attr(not(target_os = "hurd"), doc = "```ignore (needs hurd)")] /// use std::fs; /// use std::io; /// use std::os::hurd::fs::MetadataExt; @@ -155,7 +163,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "hurd", doc = "```no_run")] + #[cfg_attr(not(target_os = "hurd"), doc = "```ignore (needs hurd)")] /// use std::fs; /// use std::io; /// use std::os::hurd::fs::MetadataExt; @@ -174,7 +183,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "hurd", doc = "```no_run")] + #[cfg_attr(not(target_os = "hurd"), doc = "```ignore (needs hurd)")] /// use std::fs; /// use std::io; /// use std::os::hurd::fs::MetadataExt; @@ -191,7 +201,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "hurd", doc = "```no_run")] + #[cfg_attr(not(target_os = "hurd"), doc = "```ignore (needs hurd)")] /// use std::fs; /// use std::io; /// use std::os::hurd::fs::MetadataExt; @@ -210,7 +221,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "hurd", doc = "```no_run")] + #[cfg_attr(not(target_os = "hurd"), doc = "```ignore (needs hurd)")] /// use std::fs; /// use std::io; /// use std::os::hurd::fs::MetadataExt; @@ -227,7 +239,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "hurd", doc = "```no_run")] + #[cfg_attr(not(target_os = "hurd"), doc = "```ignore (needs hurd)")] /// use std::fs; /// use std::io; /// use std::os::hurd::fs::MetadataExt; @@ -246,7 +259,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "hurd", doc = "```no_run")] + #[cfg_attr(not(target_os = "hurd"), doc = "```ignore (needs hurd)")] /// use std::fs; /// use std::io; /// use std::os::hurd::fs::MetadataExt; @@ -263,7 +277,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "hurd", doc = "```no_run")] + #[cfg_attr(not(target_os = "hurd"), doc = "```ignore (needs hurd)")] /// use std::fs; /// use std::io; /// use std::os::hurd::fs::MetadataExt; @@ -280,7 +295,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "hurd", doc = "```no_run")] + #[cfg_attr(not(target_os = "hurd"), doc = "```ignore (needs hurd)")] /// use std::fs; /// use std::io; /// use std::os::hurd::fs::MetadataExt; diff --git a/library/std/src/os/illumos/net.rs b/library/std/src/os/illumos/net.rs index c21c887edbdf9..65512348033cb 100644 --- a/library/std/src/os/illumos/net.rs +++ b/library/std/src/os/illumos/net.rs @@ -4,7 +4,6 @@ use crate::io; use crate::os::unix::net; -use crate::sealed::Sealed; use crate::sys::AsInner; /// illumos-specific functionality for `AF_UNIX` sockets [`UnixDatagram`] @@ -13,7 +12,7 @@ use crate::sys::AsInner; /// [`UnixDatagram`]: net::UnixDatagram /// [`UnixStream`]: net::UnixStream #[unstable(feature = "unix_socket_exclbind", issue = "123481")] -pub trait UnixSocketExt: Sealed { +pub impl(self) trait UnixSocketExt { /// Enables exclusive binding on the socket. /// /// If true and if the socket had been set with `SO_REUSEADDR`, diff --git a/library/std/src/os/l4re/fs.rs b/library/std/src/os/l4re/fs.rs index 1f0bacae1ca68..2dc899bcb5a6e 100644 --- a/library/std/src/os/l4re/fs.rs +++ b/library/std/src/os/l4re/fs.rs @@ -21,14 +21,15 @@ pub trait MetadataExt { /// Unix platforms. The `os::unix::fs::MetadataExt` trait contains the /// cross-Unix abstractions contained within the raw stat. /// - /// [`stat`]: struct@crate::os::linux::raw::stat + /// [`stat`]: struct@crate::os::l4re::raw::stat /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "l4re", doc = "```no_run")] + #[cfg_attr(not(target_os = "l4re"), doc = "```ignore (needs l4re)")] /// use std::fs; /// use std::io; - /// use std::os::linux::fs::MetadataExt; + /// use std::os::l4re::fs::MetadataExt; /// /// fn main() -> io::Result<()> { /// let meta = fs::metadata("some_file")?; @@ -45,10 +46,11 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "l4re", doc = "```no_run")] + #[cfg_attr(not(target_os = "l4re"), doc = "```ignore (needs l4re)")] /// use std::fs; /// use std::io; - /// use std::os::linux::fs::MetadataExt; + /// use std::os::l4re::fs::MetadataExt; /// /// fn main() -> io::Result<()> { /// let meta = fs::metadata("some_file")?; @@ -62,10 +64,11 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "l4re", doc = "```no_run")] + #[cfg_attr(not(target_os = "l4re"), doc = "```ignore (needs l4re)")] /// use std::fs; /// use std::io; - /// use std::os::linux::fs::MetadataExt; + /// use std::os::l4re::fs::MetadataExt; /// /// fn main() -> io::Result<()> { /// let meta = fs::metadata("some_file")?; @@ -79,10 +82,11 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "l4re", doc = "```no_run")] + #[cfg_attr(not(target_os = "l4re"), doc = "```ignore (needs l4re)")] /// use std::fs; /// use std::io; - /// use std::os::linux::fs::MetadataExt; + /// use std::os::l4re::fs::MetadataExt; /// /// fn main() -> io::Result<()> { /// let meta = fs::metadata("some_file")?; @@ -96,10 +100,11 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "l4re", doc = "```no_run")] + #[cfg_attr(not(target_os = "l4re"), doc = "```ignore (needs l4re)")] /// use std::fs; /// use std::io; - /// use std::os::linux::fs::MetadataExt; + /// use std::os::l4re::fs::MetadataExt; /// /// fn main() -> io::Result<()> { /// let meta = fs::metadata("some_file")?; @@ -113,10 +118,11 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "l4re", doc = "```no_run")] + #[cfg_attr(not(target_os = "l4re"), doc = "```ignore (needs l4re)")] /// use std::fs; /// use std::io; - /// use std::os::linux::fs::MetadataExt; + /// use std::os::l4re::fs::MetadataExt; /// /// fn main() -> io::Result<()> { /// let meta = fs::metadata("some_file")?; @@ -130,10 +136,11 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "l4re", doc = "```no_run")] + #[cfg_attr(not(target_os = "l4re"), doc = "```ignore (needs l4re)")] /// use std::fs; /// use std::io; - /// use std::os::linux::fs::MetadataExt; + /// use std::os::l4re::fs::MetadataExt; /// /// fn main() -> io::Result<()> { /// let meta = fs::metadata("some_file")?; @@ -147,10 +154,11 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "l4re", doc = "```no_run")] + #[cfg_attr(not(target_os = "l4re"), doc = "```ignore (needs l4re)")] /// use std::fs; /// use std::io; - /// use std::os::linux::fs::MetadataExt; + /// use std::os::l4re::fs::MetadataExt; /// /// fn main() -> io::Result<()> { /// let meta = fs::metadata("some_file")?; @@ -167,10 +175,11 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "l4re", doc = "```no_run")] + #[cfg_attr(not(target_os = "l4re"), doc = "```ignore (needs l4re)")] /// use std::fs; /// use std::io; - /// use std::os::linux::fs::MetadataExt; + /// use std::os::l4re::fs::MetadataExt; /// /// fn main() -> io::Result<()> { /// let meta = fs::metadata("some_file")?; @@ -184,10 +193,11 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "l4re", doc = "```no_run")] + #[cfg_attr(not(target_os = "l4re"), doc = "```ignore (needs l4re)")] /// use std::fs; /// use std::io; - /// use std::os::linux::fs::MetadataExt; + /// use std::os::l4re::fs::MetadataExt; /// /// fn main() -> io::Result<()> { /// let meta = fs::metadata("some_file")?; @@ -203,10 +213,11 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "l4re", doc = "```no_run")] + #[cfg_attr(not(target_os = "l4re"), doc = "```ignore (needs l4re)")] /// use std::fs; /// use std::io; - /// use std::os::linux::fs::MetadataExt; + /// use std::os::l4re::fs::MetadataExt; /// /// fn main() -> io::Result<()> { /// let meta = fs::metadata("some_file")?; @@ -220,10 +231,11 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "l4re", doc = "```no_run")] + #[cfg_attr(not(target_os = "l4re"), doc = "```ignore (needs l4re)")] /// use std::fs; /// use std::io; - /// use std::os::linux::fs::MetadataExt; + /// use std::os::l4re::fs::MetadataExt; /// /// fn main() -> io::Result<()> { /// let meta = fs::metadata("some_file")?; @@ -239,10 +251,11 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "l4re", doc = "```no_run")] + #[cfg_attr(not(target_os = "l4re"), doc = "```ignore (needs l4re)")] /// use std::fs; /// use std::io; - /// use std::os::linux::fs::MetadataExt; + /// use std::os::l4re::fs::MetadataExt; /// /// fn main() -> io::Result<()> { /// let meta = fs::metadata("some_file")?; @@ -256,10 +269,11 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "l4re", doc = "```no_run")] + #[cfg_attr(not(target_os = "l4re"), doc = "```ignore (needs l4re)")] /// use std::fs; /// use std::io; - /// use std::os::linux::fs::MetadataExt; + /// use std::os::l4re::fs::MetadataExt; /// /// fn main() -> io::Result<()> { /// let meta = fs::metadata("some_file")?; @@ -275,10 +289,11 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "l4re", doc = "```no_run")] + #[cfg_attr(not(target_os = "l4re"), doc = "```ignore (needs l4re)")] /// use std::fs; /// use std::io; - /// use std::os::linux::fs::MetadataExt; + /// use std::os::l4re::fs::MetadataExt; /// /// fn main() -> io::Result<()> { /// let meta = fs::metadata("some_file")?; @@ -292,10 +307,11 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "l4re", doc = "```no_run")] + #[cfg_attr(not(target_os = "l4re"), doc = "```ignore (needs l4re)")] /// use std::fs; /// use std::io; - /// use std::os::linux::fs::MetadataExt; + /// use std::os::l4re::fs::MetadataExt; /// /// fn main() -> io::Result<()> { /// let meta = fs::metadata("some_file")?; @@ -309,10 +325,11 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "l4re", doc = "```no_run")] + #[cfg_attr(not(target_os = "l4re"), doc = "```ignore (needs l4re)")] /// use std::fs; /// use std::io; - /// use std::os::linux::fs::MetadataExt; + /// use std::os::l4re::fs::MetadataExt; /// /// fn main() -> io::Result<()> { /// let meta = fs::metadata("some_file")?; @@ -328,7 +345,7 @@ pub trait MetadataExt { impl MetadataExt for Metadata { #[allow(deprecated)] fn as_raw_stat(&self) -> &raw::stat { - unsafe { &*(self.as_inner().as_inner() as *const libc::stat64 as *const raw::stat) } + unsafe { &*(self.as_inner().as_inner() as *const _ as *const raw::stat) } } fn st_dev(&self) -> u64 { self.as_inner().as_inner().st_dev as u64 @@ -355,22 +372,22 @@ impl MetadataExt for Metadata { self.as_inner().as_inner().st_size as u64 } fn st_atime(&self) -> i64 { - self.as_inner().as_inner().st_atime as i64 + self.as_inner().as_inner().st_atim.tv_sec as i64 } fn st_atime_nsec(&self) -> i64 { - self.as_inner().as_inner().st_atime_nsec as i64 + self.as_inner().as_inner().st_atim.tv_nsec as i64 } fn st_mtime(&self) -> i64 { - self.as_inner().as_inner().st_mtime as i64 + self.as_inner().as_inner().st_mtim.tv_sec as i64 } fn st_mtime_nsec(&self) -> i64 { - self.as_inner().as_inner().st_mtime_nsec as i64 + self.as_inner().as_inner().st_mtim.tv_nsec as i64 } fn st_ctime(&self) -> i64 { - self.as_inner().as_inner().st_ctime as i64 + self.as_inner().as_inner().st_ctim.tv_sec as i64 } fn st_ctime_nsec(&self) -> i64 { - self.as_inner().as_inner().st_ctime_nsec as i64 + self.as_inner().as_inner().st_ctim.tv_nsec as i64 } fn st_blksize(&self) -> u64 { self.as_inner().as_inner().st_blksize as u64 diff --git a/library/std/src/os/l4re/raw.rs b/library/std/src/os/l4re/raw.rs index 8fb6e99ecfa1e..f41fff015cab6 100644 --- a/library/std/src/os/l4re/raw.rs +++ b/library/std/src/os/l4re/raw.rs @@ -10,355 +10,14 @@ )] #![allow(deprecated)] -use crate::os::raw::c_ulong; - #[stable(feature = "raw_ext", since = "1.1.0")] -pub type dev_t = u64; +pub type dev_t = libc::dev_t; #[stable(feature = "raw_ext", since = "1.1.0")] -pub type mode_t = u32; +pub type mode_t = libc::mode_t; #[stable(feature = "pthread_t", since = "1.8.0")] -pub type pthread_t = c_ulong; +pub type pthread_t = libc::pthread_t; #[doc(inline)] #[stable(feature = "raw_ext", since = "1.1.0")] -pub use self::arch::{blkcnt_t, blksize_t, ino_t, nlink_t, off_t, stat, time_t}; - -#[cfg(any( - target_arch = "x86", - target_arch = "m68k", - target_arch = "csky", - target_arch = "powerpc", - target_arch = "sparc", - target_arch = "arm", - target_arch = "wasm32" -))] -mod arch { - use crate::os::raw::{c_long, c_short, c_uint}; - - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type blkcnt_t = u64; - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type blksize_t = u64; - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type ino_t = u64; - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type nlink_t = u64; - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type off_t = u64; - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type time_t = i64; - - #[repr(C)] - #[derive(Clone)] - #[stable(feature = "raw_ext", since = "1.1.0")] - pub struct stat { - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_dev: u64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub __pad1: c_short, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub __st_ino: u32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_mode: u32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_nlink: u32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_uid: u32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_gid: u32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_rdev: u64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub __pad2: c_uint, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_size: i64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_blksize: i32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_blocks: i64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_atime: i32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_atime_nsec: c_long, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_mtime: i32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_mtime_nsec: c_long, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_ctime: i32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_ctime_nsec: c_long, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_ino: u64, - } -} - -#[cfg(target_arch = "mips")] -mod arch { - use crate::os::raw::{c_long, c_ulong}; - - #[cfg(target_env = "musl")] - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type blkcnt_t = i64; - #[cfg(not(target_env = "musl"))] - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type blkcnt_t = u64; - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type blksize_t = u64; - #[cfg(target_env = "musl")] - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type ino_t = u64; - #[cfg(not(target_env = "musl"))] - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type ino_t = u64; - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type nlink_t = u64; - #[cfg(target_env = "musl")] - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type off_t = u64; - #[cfg(not(target_env = "musl"))] - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type off_t = u64; - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type time_t = i64; - - #[repr(C)] - #[derive(Clone)] - #[stable(feature = "raw_ext", since = "1.1.0")] - pub struct stat { - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_dev: c_ulong, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_pad1: [c_long; 3], - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_ino: u64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_mode: u32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_nlink: u32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_uid: u32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_gid: u32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_rdev: c_ulong, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_pad2: [c_long; 2], - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_size: i64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_atime: i32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_atime_nsec: c_long, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_mtime: i32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_mtime_nsec: c_long, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_ctime: i32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_ctime_nsec: c_long, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_blksize: i32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_blocks: i64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_pad5: [c_long; 14], - } -} - -#[cfg(target_arch = "hexagon")] -mod arch { - use crate::os::raw::{c_int, c_long, c_uint}; - - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type blkcnt_t = i64; - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type blksize_t = c_long; - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type ino_t = u64; - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type nlink_t = c_uint; - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type off_t = i64; - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type time_t = i64; - - #[repr(C)] - #[derive(Clone)] - #[stable(feature = "raw_ext", since = "1.1.0")] - pub struct stat { - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_dev: u64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_ino: u64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_mode: u32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_nlink: u32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_uid: u32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_gid: u32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_rdev: u64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub __pad1: u32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_size: i64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_blksize: i32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub __pad2: i32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_blocks: i64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_atime: i64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_atime_nsec: c_long, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_mtime: i64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_mtime_nsec: c_long, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_ctime: i64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_ctime_nsec: c_long, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub __pad3: [c_int; 2], - } -} - -#[cfg(any( - target_arch = "mips64", - target_arch = "s390x", - target_arch = "sparc64", - target_arch = "riscv64", - target_arch = "riscv32" -))] -mod arch { - pub use libc::{blkcnt_t, blksize_t, ino_t, nlink_t, off_t, stat, time_t}; -} - -#[cfg(target_arch = "aarch64")] -mod arch { - use crate::os::raw::{c_int, c_long}; - - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type blkcnt_t = i64; - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type blksize_t = i32; - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type ino_t = u64; - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type nlink_t = u32; - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type off_t = i64; - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type time_t = c_long; - - #[repr(C)] - #[derive(Clone)] - #[stable(feature = "raw_ext", since = "1.1.0")] - pub struct stat { - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_dev: u64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_ino: u64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_mode: u32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_nlink: u32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_uid: u32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_gid: u32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_rdev: u64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub __pad1: u64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_size: i64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_blksize: i32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub __pad2: c_int, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_blocks: i64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_atime: time_t, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_atime_nsec: c_long, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_mtime: time_t, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_mtime_nsec: c_long, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_ctime: time_t, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_ctime_nsec: c_long, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub __unused: [c_int; 2], - } -} - -#[cfg(any(target_arch = "x86_64", target_arch = "powerpc64"))] -mod arch { - use crate::os::raw::{c_int, c_long}; - - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type blkcnt_t = u64; - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type blksize_t = u64; - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type ino_t = u64; - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type nlink_t = u64; - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type off_t = u64; - #[stable(feature = "raw_ext", since = "1.1.0")] - pub type time_t = i64; - - #[repr(C)] - #[derive(Clone)] - #[stable(feature = "raw_ext", since = "1.1.0")] - pub struct stat { - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_dev: u64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_ino: u64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_nlink: u64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_mode: u32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_uid: u32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_gid: u32, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub __pad0: c_int, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_rdev: u64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_size: i64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_blksize: i64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_blocks: i64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_atime: i64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_atime_nsec: c_long, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_mtime: i64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_mtime_nsec: c_long, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_ctime: i64, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub st_ctime_nsec: c_long, - #[stable(feature = "raw_ext", since = "1.1.0")] - pub __unused: [c_long; 3], - } -} +pub use libc::{blkcnt_t, blksize_t, ino_t, nlink_t, off_t, stat, time_t}; diff --git a/library/std/src/os/linux/fs.rs b/library/std/src/os/linux/fs.rs index e52a63bc798ea..0e8fa0a15da09 100644 --- a/library/std/src/os/linux/fs.rs +++ b/library/std/src/os/linux/fs.rs @@ -25,7 +25,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "linux", doc = "```no_run")] + #[cfg_attr(not(target_os = "linux"), doc = "```ignore (needs linux)")] /// use std::fs; /// use std::io; /// use std::os::linux::fs::MetadataExt; @@ -45,7 +46,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "linux", doc = "```no_run")] + #[cfg_attr(not(target_os = "linux"), doc = "```ignore (needs linux)")] /// use std::fs; /// use std::io; /// use std::os::linux::fs::MetadataExt; @@ -62,7 +64,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "linux", doc = "```no_run")] + #[cfg_attr(not(target_os = "linux"), doc = "```ignore (needs linux)")] /// use std::fs; /// use std::io; /// use std::os::linux::fs::MetadataExt; @@ -79,7 +82,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "linux", doc = "```no_run")] + #[cfg_attr(not(target_os = "linux"), doc = "```ignore (needs linux)")] /// use std::fs; /// use std::io; /// use std::os::linux::fs::MetadataExt; @@ -96,7 +100,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "linux", doc = "```no_run")] + #[cfg_attr(not(target_os = "linux"), doc = "```ignore (needs linux)")] /// use std::fs; /// use std::io; /// use std::os::linux::fs::MetadataExt; @@ -113,7 +118,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "linux", doc = "```no_run")] + #[cfg_attr(not(target_os = "linux"), doc = "```ignore (needs linux)")] /// use std::fs; /// use std::io; /// use std::os::linux::fs::MetadataExt; @@ -130,7 +136,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "linux", doc = "```no_run")] + #[cfg_attr(not(target_os = "linux"), doc = "```ignore (needs linux)")] /// use std::fs; /// use std::io; /// use std::os::linux::fs::MetadataExt; @@ -147,7 +154,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "linux", doc = "```no_run")] + #[cfg_attr(not(target_os = "linux"), doc = "```ignore (needs linux)")] /// use std::fs; /// use std::io; /// use std::os::linux::fs::MetadataExt; @@ -167,7 +175,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "linux", doc = "```no_run")] + #[cfg_attr(not(target_os = "linux"), doc = "```ignore (needs linux)")] /// use std::fs; /// use std::io; /// use std::os::linux::fs::MetadataExt; @@ -184,7 +193,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "linux", doc = "```no_run")] + #[cfg_attr(not(target_os = "linux"), doc = "```ignore (needs linux)")] /// use std::fs; /// use std::io; /// use std::os::linux::fs::MetadataExt; @@ -203,7 +213,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "linux", doc = "```no_run")] + #[cfg_attr(not(target_os = "linux"), doc = "```ignore (needs linux)")] /// use std::fs; /// use std::io; /// use std::os::linux::fs::MetadataExt; @@ -220,7 +231,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "linux", doc = "```no_run")] + #[cfg_attr(not(target_os = "linux"), doc = "```ignore (needs linux)")] /// use std::fs; /// use std::io; /// use std::os::linux::fs::MetadataExt; @@ -239,7 +251,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "linux", doc = "```no_run")] + #[cfg_attr(not(target_os = "linux"), doc = "```ignore (needs linux)")] /// use std::fs; /// use std::io; /// use std::os::linux::fs::MetadataExt; @@ -256,7 +269,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "linux", doc = "```no_run")] + #[cfg_attr(not(target_os = "linux"), doc = "```ignore (needs linux)")] /// use std::fs; /// use std::io; /// use std::os::linux::fs::MetadataExt; @@ -275,7 +289,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "linux", doc = "```no_run")] + #[cfg_attr(not(target_os = "linux"), doc = "```ignore (needs linux)")] /// use std::fs; /// use std::io; /// use std::os::linux::fs::MetadataExt; @@ -292,7 +307,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "linux", doc = "```no_run")] + #[cfg_attr(not(target_os = "linux"), doc = "```ignore (needs linux)")] /// use std::fs; /// use std::io; /// use std::os::linux::fs::MetadataExt; @@ -309,7 +325,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "linux", doc = "```no_run")] + #[cfg_attr(not(target_os = "linux"), doc = "```ignore (needs linux)")] /// use std::fs; /// use std::io; /// use std::os::linux::fs::MetadataExt; diff --git a/library/std/src/os/linux/process.rs b/library/std/src/os/linux/process.rs index 60851db831bf9..e0ddaa85cb82e 100644 --- a/library/std/src/os/linux/process.rs +++ b/library/std/src/os/linux/process.rs @@ -7,10 +7,9 @@ use crate::io::Result; use crate::os::unix::io::{AsFd, AsRawFd, BorrowedFd, FromRawFd, IntoRawFd, OwnedFd, RawFd}; use crate::process::{self, ExitStatus}; -use crate::sealed::Sealed; use crate::sys::{AsInner, AsInnerMut, FromInner, IntoInner}; #[cfg(not(doc))] -use crate::sys::{fd::FileDesc, linux::pidfd::PidFd as InnerPidFd}; +use crate::sys::{fd::FileDesc, process::PidFd as InnerPidFd}; #[cfg(doc)] struct InnerPidFd; @@ -21,8 +20,10 @@ struct InnerPidFd; /// with [`create_pidfd`]. Subsequently, the created pidfd can be retrieved /// from the [`Child`] by calling [`pidfd`] or [`into_pidfd`]. /// -/// Example: -/// ```no_run +/// # Examples +/// +#[cfg_attr(target_os = "linux", doc = "```no_run")] +#[cfg_attr(not(target_os = "linux"), doc = "```ignore (needs linux)")] /// #![feature(linux_pidfd)] /// use std::os::linux::process::{CommandExt, ChildExt}; /// use std::process::Command; @@ -147,7 +148,7 @@ impl From for OwnedFd { /// Os-specific extensions for [`Child`] /// /// [`Child`]: process::Child -pub trait ChildExt: Sealed { +pub impl(crate) trait ChildExt { /// Obtains a reference to the [`PidFd`] created for this [`Child`], if available. /// /// A pidfd will only be available if its creation was requested with @@ -186,7 +187,7 @@ pub trait ChildExt: Sealed { /// Os-specific extensions for [`Command`] /// /// [`Command`]: process::Command -pub trait CommandExt: Sealed { +pub impl(self) trait CommandExt { /// Sets whether a [`PidFd`](struct@PidFd) should be created for the [`Child`] /// spawned by this [`Command`]. /// By default, no pidfd will be created. diff --git a/library/std/src/os/linux/raw.rs b/library/std/src/os/linux/raw.rs index 6483f0861139b..6f2da15a98d69 100644 --- a/library/std/src/os/linux/raw.rs +++ b/library/std/src/os/linux/raw.rs @@ -31,7 +31,6 @@ pub use self::arch::{blkcnt_t, blksize_t, ino_t, nlink_t, off_t, stat, time_t}; target_arch = "powerpc", target_arch = "sparc", target_arch = "arm", - target_arch = "wasm32" ))] mod arch { use crate::os::raw::{c_long, c_short, c_uint}; @@ -311,7 +310,9 @@ mod arch { } } -#[cfg(any(target_arch = "x86_64", target_arch = "powerpc64"))] +#[cfg(any(target_arch = "x86_64", target_arch = "powerpc64", + // `wasm32-wali-linux-musl` uses ABI similar to x86_64 + target_arch = "wasm32"))] mod arch { use crate::os::raw::{c_int, c_long}; diff --git a/library/std/src/os/mod.rs b/library/std/src/os/mod.rs index 76374402be4b3..8068f92bcc93c 100644 --- a/library/std/src/os/mod.rs +++ b/library/std/src/os/mod.rs @@ -6,121 +6,83 @@ pub mod raw; -// The code below could be written clearer using `cfg_if!`. However, the items below are -// publicly exported by `std` and external tools can have trouble analysing them because of the use -// of a macro that is not vendored by Rust and included in the toolchain. -// See https://github.com/rust-analyzer/rust-analyzer/issues/6038. +// # Important platforms -// On certain platforms right now the "main modules" modules that are -// documented don't compile (missing things in `libc` which is empty), -// so just omit them with an empty module and add the "unstable" attribute. - -// darwin, unix, linux, wasi and windows are handled a bit differently. -#[cfg(all( - doc, - any( - all(target_arch = "wasm32", not(target_os = "wasi")), - all(target_vendor = "fortanix", target_env = "sgx") - ) -))] -#[unstable(issue = "none", feature = "std_internals")] -pub mod darwin {} -#[cfg(all( - doc, - any( - all(target_arch = "wasm32", not(target_os = "wasi")), - all(target_vendor = "fortanix", target_env = "sgx") - ) -))] -#[unstable(issue = "none", feature = "std_internals")] -pub mod unix {} -#[cfg(all( - doc, - any( - all(target_arch = "wasm32", not(target_os = "wasi")), - all(target_vendor = "fortanix", target_env = "sgx") - ) -))] -#[unstable(issue = "none", feature = "std_internals")] -pub mod linux {} -#[cfg(all( - doc, - any( - all(target_arch = "wasm32", not(target_os = "wasi")), - all(target_vendor = "fortanix", target_env = "sgx") - ) -))] -#[unstable(issue = "none", feature = "std_internals")] -pub mod wasi {} -#[cfg(all( - doc, +// We always want to show documentation for the most important platforms, +// so these are handled specially here. +// +// FIXME: On certain platforms compilation errors (due to empty `libc`), +// prevent this, so we substitute an unstable empty module. +#[cfg(doc)] +cfg_select! { any( all(target_arch = "wasm32", not(target_os = "wasi")), all(target_vendor = "fortanix", target_env = "sgx") - ) -))] -#[unstable(issue = "none", feature = "std_internals")] -pub mod windows {} + ) => { + #[unstable(issue = "none", feature = "std_internals")] + pub mod darwin {} -// darwin -#[cfg(not(all( - doc, - any( - all(target_arch = "wasm32", not(target_os = "wasi")), - all(target_vendor = "fortanix", target_env = "sgx") - ) -)))] -#[cfg(any(target_vendor = "apple", doc))] -pub mod darwin; + #[unstable(issue = "none", feature = "std_internals")] + pub mod unix {} -// unix -#[cfg(not(all( - doc, - any( - all(target_arch = "wasm32", not(target_os = "wasi")), - all(target_vendor = "fortanix", target_env = "sgx") - ) -)))] -#[cfg(all(not(target_os = "hermit"), any(unix, doc)))] -pub mod unix; + #[unstable(issue = "none", feature = "std_internals")] + pub mod linux {} -// linux -#[cfg(not(all( - doc, - any( - all(target_arch = "wasm32", not(target_os = "wasi")), - all(target_vendor = "fortanix", target_env = "sgx") - ) -)))] -#[cfg(any(target_os = "linux", doc))] -pub mod linux; + #[unstable(issue = "none", feature = "std_internals")] + pub mod wasi {} -// wasi -#[cfg(not(all( - doc, - any( - all(target_arch = "wasm32", not(target_os = "wasi")), - all(target_vendor = "fortanix", target_env = "sgx") - ) -)))] -#[cfg(any(target_os = "wasi", any(target_env = "p1", target_env = "p2"), doc))] -pub mod wasi; + #[unstable(issue = "none", feature = "std_internals")] + pub mod windows {} + } + _ => { + // important platforms + pub mod darwin; + pub mod linux; + pub mod unix; + pub mod wasi; + pub mod wasip2; + pub mod windows; + } +} +#[cfg(not(doc))] // to prevent double module declarations +cfg_select! { + target_family = "unix" => { + pub mod unix; + #[cfg(target_vendor = "apple")] + pub mod darwin; + #[cfg(target_os = "linux")] + pub mod linux; + } + target_family = "wasm" => { + #[cfg(any(target_env = "p1", target_env = "p2", target_env = "p3"))] + pub mod wasi; + #[cfg(target_env = "p2")] + pub mod wasip2; + } + target_family = "windows" => { + pub mod windows; + } + _ => { /* handled below */ } +} -#[cfg(any(all(target_os = "wasi", target_env = "p2"), doc))] -pub mod wasip2; +// # Special modules -// windows -#[cfg(not(all( - doc, - any( - all(target_arch = "wasm32", not(target_os = "wasi")), - all(target_vendor = "fortanix", target_env = "sgx") - ) -)))] -#[cfg(any(windows, doc))] -pub mod windows; +#[cfg(any( + unix, + target_os = "hermit", + target_os = "trusty", + target_os = "wasi", + target_os = "motor", + doc +))] +pub mod fd; + +#[cfg(any(target_os = "linux", target_os = "android", target_os = "cygwin", doc))] +mod net; + +// # Ordinary platforms +// `cfg(doc)` not handled specially -// Others. #[cfg(target_os = "aix")] pub mod aix; #[cfg(target_os = "android")] @@ -159,7 +121,7 @@ pub mod macos; pub mod motor; #[cfg(target_os = "netbsd")] pub mod netbsd; -#[cfg(target_os = "nto")] +#[cfg(any(target_os = "nto", target_os = "qnx"))] pub mod nto; #[cfg(target_os = "nuttx")] pub mod nuttx; @@ -183,16 +145,3 @@ pub mod vita; pub mod vxworks; #[cfg(target_os = "xous")] pub mod xous; - -#[cfg(any( - unix, - target_os = "hermit", - target_os = "trusty", - target_os = "wasi", - target_os = "motor", - doc -))] -pub mod fd; - -#[cfg(any(target_os = "linux", target_os = "android", target_os = "cygwin", doc))] -mod net; diff --git a/library/std/src/os/motor/ffi.rs b/library/std/src/os/motor/ffi.rs index e65a7736d3fa0..08fa4d206c10f 100644 --- a/library/std/src/os/motor/ffi.rs +++ b/library/std/src/os/motor/ffi.rs @@ -2,14 +2,10 @@ #![unstable(feature = "motor_ext", issue = "147456")] use crate::ffi::{OsStr, OsString}; -use crate::sealed::Sealed; use crate::sys::{AsInner, IntoInner}; /// Motor OS–specific extensions to [`OsString`]. -/// -/// This trait is sealed: it cannot be implemented outside the standard library. -/// This is so that future additional methods are not breaking changes. -pub trait OsStringExt: Sealed { +pub impl(self) trait OsStringExt { /// Yields the underlying UTF-8 string of this [`OsString`]. /// /// OS strings on Motor OS are guaranteed to be UTF-8, so are just strings. @@ -24,10 +20,7 @@ impl OsStringExt for OsString { } /// Motor OS–specific extensions to [`OsString`]. -/// -/// This trait is sealed: it cannot be implemented outside the standard library. -/// This is so that future additional methods are not breaking changes. -pub trait OsStrExt: Sealed { +pub impl(self) trait OsStrExt { /// Gets the underlying UTF-8 string view of the [`OsStr`] slice. /// /// OS strings on Motor OS are guaranteed to be UTF-8, so are just strings. diff --git a/library/std/src/os/motor/process.rs b/library/std/src/os/motor/process.rs index 09f38a4721bbc..43c8ff5a42987 100644 --- a/library/std/src/os/motor/process.rs +++ b/library/std/src/os/motor/process.rs @@ -1,9 +1,8 @@ #![unstable(feature = "motor_ext", issue = "147456")] -use crate::sealed::Sealed; use crate::sys::AsInner; -pub trait ChildExt: Sealed { +pub impl(self) trait ChildExt { /// Extracts the main thread raw handle, without taking ownership fn sys_handle(&self) -> u64; } diff --git a/library/std/src/os/net/linux_ext/addr.rs b/library/std/src/os/net/linux_ext/addr.rs index 41009c0e28457..07adee90b0bc0 100644 --- a/library/std/src/os/net/linux_ext/addr.rs +++ b/library/std/src/os/net/linux_ext/addr.rs @@ -1,11 +1,10 @@ //! Linux and Android-specific extensions to socket addresses. use crate::os::unix::net::SocketAddr; -use crate::sealed::Sealed; /// Platform-specific extensions to [`SocketAddr`]. #[stable(feature = "unix_socket_abstract", since = "1.70.0")] -pub trait SocketAddrExt: Sealed { +pub impl(in crate::os) trait SocketAddrExt { /// Creates a Unix socket address in the abstract namespace. /// /// The abstract namespace is a Linux-specific extension that allows Unix @@ -21,7 +20,14 @@ pub trait SocketAddrExt: Sealed { /// /// # Examples /// - /// ```no_run + #[cfg_attr( + any(target_os = "linux", target_os = "android", target_os = "cygwin"), + doc = "```no_run" + )] + #[cfg_attr( + not(any(target_os = "linux", target_os = "android", target_os = "cygwin")), + doc = "```ignore (needs linux)" + )] /// use std::os::unix::net::{UnixListener, SocketAddr}; /// #[cfg(target_os = "linux")] /// use std::os::linux::net::SocketAddrExt; @@ -49,7 +55,14 @@ pub trait SocketAddrExt: Sealed { /// /// # Examples /// - /// ```no_run + #[cfg_attr( + any(target_os = "linux", target_os = "android", target_os = "cygwin"), + doc = "```no_run" + )] + #[cfg_attr( + not(any(target_os = "linux", target_os = "android", target_os = "cygwin")), + doc = "```ignore (needs linux)" + )] /// use std::os::unix::net::{UnixListener, SocketAddr}; /// #[cfg(target_os = "linux")] /// use std::os::linux::net::SocketAddrExt; diff --git a/library/std/src/os/net/linux_ext/socket.rs b/library/std/src/os/net/linux_ext/socket.rs index ecc2758961e1d..777587fe4ce7c 100644 --- a/library/std/src/os/net/linux_ext/socket.rs +++ b/library/std/src/os/net/linux_ext/socket.rs @@ -2,7 +2,6 @@ use crate::io; use crate::os::unix::net; -use crate::sealed::Sealed; use crate::sys::AsInner; /// Linux-specific functionality for `AF_UNIX` sockets [`UnixDatagram`] @@ -11,7 +10,7 @@ use crate::sys::AsInner; /// [`UnixDatagram`]: net::UnixDatagram /// [`UnixStream`]: net::UnixStream #[unstable(feature = "unix_socket_ancillary_data", issue = "76915")] -pub trait UnixSocketExt: Sealed { +pub impl(self) trait UnixSocketExt { /// Query the current setting of socket option `SO_PASSCRED`. #[unstable(feature = "unix_socket_ancillary_data", issue = "76915")] fn passcred(&self) -> io::Result; @@ -25,7 +24,14 @@ pub trait UnixSocketExt: Sealed { /// /// # Examples /// - /// ```no_run + #[cfg_attr( + any(target_os = "linux", target_os = "android", target_os = "cygwin"), + doc = "```no_run" + )] + #[cfg_attr( + not(any(target_os = "linux", target_os = "android", target_os = "cygwin")), + doc = "```ignore (needs linux)" + )] /// #![feature(unix_socket_ancillary_data)] /// #[cfg(target_os = "linux")] /// use std::os::linux::net::UnixSocketExt; diff --git a/library/std/src/os/net/linux_ext/tcp.rs b/library/std/src/os/net/linux_ext/tcp.rs index c97063dd16505..2fc6b2769568e 100644 --- a/library/std/src/os/net/linux_ext/tcp.rs +++ b/library/std/src/os/net/linux_ext/tcp.rs @@ -2,7 +2,6 @@ //! //! [`std::net`]: crate::net -use crate::sealed::Sealed; use crate::sys::AsInner; #[cfg(target_os = "linux")] use crate::time::Duration; @@ -12,7 +11,7 @@ use crate::{io, net}; /// /// [`TcpStream`]: net::TcpStream #[stable(feature = "tcp_quickack", since = "1.89.0")] -pub trait TcpStreamExt: Sealed { +pub impl(self) trait TcpStreamExt { /// Enable or disable `TCP_QUICKACK`. /// /// This flag causes Linux to eagerly send ACKs rather than delaying them. @@ -24,7 +23,14 @@ pub trait TcpStreamExt: Sealed { /// /// # Examples /// - /// ```no_run + #[cfg_attr( + any(target_os = "linux", target_os = "android", target_os = "cygwin"), + doc = "```no_run" + )] + #[cfg_attr( + not(any(target_os = "linux", target_os = "android", target_os = "cygwin")), + doc = "```ignore (needs linux)" + )] /// use std::net::TcpStream; /// #[cfg(target_os = "linux")] /// use std::os::linux::net::TcpStreamExt; @@ -44,7 +50,14 @@ pub trait TcpStreamExt: Sealed { /// /// # Examples /// - /// ```no_run + #[cfg_attr( + any(target_os = "linux", target_os = "android", target_os = "cygwin"), + doc = "```no_run" + )] + #[cfg_attr( + not(any(target_os = "linux", target_os = "android", target_os = "cygwin")), + doc = "```ignore (needs linux)" + )] /// use std::net::TcpStream; /// #[cfg(target_os = "linux")] /// use std::os::linux::net::TcpStreamExt; @@ -93,7 +106,14 @@ pub trait TcpStreamExt: Sealed { /// /// # Examples /// - /// ```no_run + #[cfg_attr( + any(target_os = "linux", target_os = "android", target_os = "cygwin"), + doc = "```no_run" + )] + #[cfg_attr( + not(any(target_os = "linux", target_os = "android", target_os = "cygwin")), + doc = "```ignore (needs linux)" + )] /// #![feature(tcp_deferaccept)] /// use std::net::TcpStream; /// use std::os::linux::net::TcpStreamExt; @@ -109,9 +129,6 @@ pub trait TcpStreamExt: Sealed { fn deferaccept(&self) -> io::Result; } -#[stable(feature = "tcp_quickack", since = "1.89.0")] -impl Sealed for net::TcpStream {} - #[stable(feature = "tcp_quickack", since = "1.89.0")] impl TcpStreamExt for net::TcpStream { fn set_quickack(&self, quickack: bool) -> io::Result<()> { diff --git a/library/std/src/os/net/linux_ext/tests.rs b/library/std/src/os/net/linux_ext/tests.rs index 0758b426ccc59..a63524e63b6d8 100644 --- a/library/std/src/os/net/linux_ext/tests.rs +++ b/library/std/src/os/net/linux_ext/tests.rs @@ -1,6 +1,6 @@ #[test] fn quickack() { - use crate::net::test::next_test_ip4; + use crate::net::tests::LOCALHOST_IP4; use crate::net::{TcpListener, TcpStream}; use crate::os::net::linux_ext::tcp::TcpStreamExt; @@ -13,8 +13,8 @@ fn quickack() { }; } - let addr = next_test_ip4(); - let _listener = t!(TcpListener::bind(&addr)); + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); + let addr = t!(listener.local_addr()); let stream = t!(TcpStream::connect(&("localhost", addr.port()))); @@ -29,7 +29,7 @@ fn quickack() { #[test] #[cfg(target_os = "linux")] fn deferaccept() { - use crate::net::test::next_test_ip4; + use crate::net::tests::LOCALHOST_IP4; use crate::net::{TcpListener, TcpStream}; use crate::os::net::linux_ext::tcp::TcpStreamExt; use crate::time::Duration; @@ -43,10 +43,11 @@ fn deferaccept() { }; } - let addr = next_test_ip4(); let one = Duration::from_secs(1u64); let zero = Duration::from_secs(0u64); - let _listener = t!(TcpListener::bind(&addr)); + + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); + let addr = t!(listener.local_addr()); let stream = t!(TcpStream::connect(&("localhost", addr.port()))); stream.set_deferaccept(one).expect("set_deferaccept failed"); assert_eq!(stream.deferaccept().unwrap(), one); diff --git a/library/std/src/os/netbsd/net.rs b/library/std/src/os/netbsd/net.rs index 9174fee2f9962..a0e9ba3f7cf7c 100644 --- a/library/std/src/os/netbsd/net.rs +++ b/library/std/src/os/netbsd/net.rs @@ -5,7 +5,6 @@ use crate::ffi::CStr; use crate::io; use crate::os::unix::net; -use crate::sealed::Sealed; use crate::sys::AsInner; /// NetBSD-specific functionality for `AF_UNIX` sockets [`UnixDatagram`] @@ -14,7 +13,7 @@ use crate::sys::AsInner; /// [`UnixDatagram`]: net::UnixDatagram /// [`UnixStream`]: net::UnixStream #[unstable(feature = "unix_socket_ancillary_data", issue = "76915")] -pub trait UnixSocketExt: Sealed { +pub impl(self) trait UnixSocketExt { /// Query the current setting of socket option `LOCAL_CREDS`. #[unstable(feature = "unix_socket_ancillary_data", issue = "76915")] fn local_creds(&self) -> io::Result; @@ -28,7 +27,8 @@ pub trait UnixSocketExt: Sealed { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "netbsd", doc = "```no_run")] + #[cfg_attr(not(target_os = "netbsd"), doc = "```ignore (needs netbsd)")] /// #![feature(unix_socket_ancillary_data)] /// use std::os::netbsd::net::UnixSocketExt; /// use std::os::unix::net::UnixDatagram; diff --git a/library/std/src/os/redox/fs.rs b/library/std/src/os/redox/fs.rs index 0451e91071bcf..ed6c8cb08677d 100644 --- a/library/std/src/os/redox/fs.rs +++ b/library/std/src/os/redox/fs.rs @@ -21,7 +21,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "redox", doc = "```no_run")] + #[cfg_attr(not(target_os = "redox"), doc = "```ignore (needs redox)")] /// use std::fs; /// use std::io; /// use std::os::redox::fs::MetadataExt; @@ -45,7 +46,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "redox", doc = "```no_run")] + #[cfg_attr(not(target_os = "redox"), doc = "```ignore (needs redox)")] /// use std::fs; /// use std::io; /// use std::os::redox::fs::MetadataExt; @@ -62,7 +64,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "redox", doc = "```no_run")] + #[cfg_attr(not(target_os = "redox"), doc = "```ignore (needs redox)")] /// use std::fs; /// use std::io; /// use std::os::redox::fs::MetadataExt; @@ -79,7 +82,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "redox", doc = "```no_run")] + #[cfg_attr(not(target_os = "redox"), doc = "```ignore (needs redox)")] /// use std::fs; /// use std::io; /// use std::os::redox::fs::MetadataExt; @@ -96,7 +100,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "redox", doc = "```no_run")] + #[cfg_attr(not(target_os = "redox"), doc = "```ignore (needs redox)")] /// use std::fs; /// use std::io; /// use std::os::redox::fs::MetadataExt; @@ -113,7 +118,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "redox", doc = "```no_run")] + #[cfg_attr(not(target_os = "redox"), doc = "```ignore (needs redox)")] /// use std::fs; /// use std::io; /// use std::os::redox::fs::MetadataExt; @@ -130,7 +136,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "redox", doc = "```no_run")] + #[cfg_attr(not(target_os = "redox"), doc = "```ignore (needs redox)")] /// use std::fs; /// use std::io; /// use std::os::redox::fs::MetadataExt; @@ -147,7 +154,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "redox", doc = "```no_run")] + #[cfg_attr(not(target_os = "redox"), doc = "```ignore (needs redox)")] /// use std::fs; /// use std::io; /// use std::os::redox::fs::MetadataExt; @@ -167,7 +175,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "redox", doc = "```no_run")] + #[cfg_attr(not(target_os = "redox"), doc = "```ignore (needs redox)")] /// use std::fs; /// use std::io; /// use std::os::redox::fs::MetadataExt; @@ -184,7 +193,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "redox", doc = "```no_run")] + #[cfg_attr(not(target_os = "redox"), doc = "```ignore (needs redox)")] /// use std::fs; /// use std::io; /// use std::os::redox::fs::MetadataExt; @@ -203,7 +213,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "redox", doc = "```no_run")] + #[cfg_attr(not(target_os = "redox"), doc = "```ignore (needs redox)")] /// use std::fs; /// use std::io; /// use std::os::redox::fs::MetadataExt; @@ -220,7 +231,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "redox", doc = "```no_run")] + #[cfg_attr(not(target_os = "redox"), doc = "```ignore (needs redox)")] /// use std::fs; /// use std::io; /// use std::os::redox::fs::MetadataExt; @@ -239,7 +251,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "redox", doc = "```no_run")] + #[cfg_attr(not(target_os = "redox"), doc = "```ignore (needs redox)")] /// use std::fs; /// use std::io; /// use std::os::redox::fs::MetadataExt; @@ -256,7 +269,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "redox", doc = "```no_run")] + #[cfg_attr(not(target_os = "redox"), doc = "```ignore (needs redox)")] /// use std::fs; /// use std::io; /// use std::os::redox::fs::MetadataExt; @@ -275,7 +289,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "redox", doc = "```no_run")] + #[cfg_attr(not(target_os = "redox"), doc = "```ignore (needs redox)")] /// use std::fs; /// use std::io; /// use std::os::redox::fs::MetadataExt; @@ -292,7 +307,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "redox", doc = "```no_run")] + #[cfg_attr(not(target_os = "redox"), doc = "```ignore (needs redox)")] /// use std::fs; /// use std::io; /// use std::os::redox::fs::MetadataExt; @@ -309,7 +325,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "redox", doc = "```no_run")] + #[cfg_attr(not(target_os = "redox"), doc = "```ignore (needs redox)")] /// use std::fs; /// use std::io; /// use std::os::redox::fs::MetadataExt; diff --git a/library/std/src/os/rtems/fs.rs b/library/std/src/os/rtems/fs.rs index 97a0c9004c00a..ab662e5654071 100644 --- a/library/std/src/os/rtems/fs.rs +++ b/library/std/src/os/rtems/fs.rs @@ -12,7 +12,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "rtems", doc = "```no_run")] + #[cfg_attr(not(target_os = "rtems"), doc = "```ignore (needs rtems)")] /// use std::fs; /// use std::io; /// use std::os::rtems::fs::MetadataExt; @@ -30,7 +31,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "rtems", doc = "```no_run")] + #[cfg_attr(not(target_os = "rtems"), doc = "```ignore (needs rtems)")] /// use std::fs; /// use std::io; /// use std::os::rtems::fs::MetadataExt; @@ -48,7 +50,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "rtems", doc = "```no_run")] + #[cfg_attr(not(target_os = "rtems"), doc = "```ignore (needs rtems)")] /// use std::fs; /// use std::io; /// use std::os::rtems::fs::MetadataExt; @@ -66,7 +69,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "rtems", doc = "```no_run")] + #[cfg_attr(not(target_os = "rtems"), doc = "```ignore (needs rtems)")] /// use std::fs; /// use std::io; /// use std::os::rtems::fs::MetadataExt; @@ -84,7 +88,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "rtems", doc = "```no_run")] + #[cfg_attr(not(target_os = "rtems"), doc = "```ignore (needs rtems)")] /// use std::fs; /// use std::io; /// use std::os::rtems::fs::MetadataExt; @@ -102,7 +107,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "rtems", doc = "```no_run")] + #[cfg_attr(not(target_os = "rtems"), doc = "```ignore (needs rtems)")] /// use std::fs; /// use std::io; /// use std::os::rtems::fs::MetadataExt; @@ -120,7 +126,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "rtems", doc = "```no_run")] + #[cfg_attr(not(target_os = "rtems"), doc = "```ignore (needs rtems)")] /// use std::fs; /// use std::io; /// use std::os::rtems::fs::MetadataExt; @@ -141,7 +148,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "rtems", doc = "```no_run")] + #[cfg_attr(not(target_os = "rtems"), doc = "```ignore (needs rtems)")] /// use std::fs; /// use std::io; /// use std::os::rtems::fs::MetadataExt; @@ -159,7 +167,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "rtems", doc = "```no_run")] + #[cfg_attr(not(target_os = "rtems"), doc = "```ignore (needs rtems)")] /// use std::fs; /// use std::io; /// use std::os::rtems::fs::MetadataExt; @@ -179,7 +188,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "rtems", doc = "```no_run")] + #[cfg_attr(not(target_os = "rtems"), doc = "```ignore (needs rtems)")] /// use std::fs; /// use std::io; /// use std::os::rtems::fs::MetadataExt; @@ -197,7 +207,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "rtems", doc = "```no_run")] + #[cfg_attr(not(target_os = "rtems"), doc = "```ignore (needs rtems)")] /// use std::fs; /// use std::io; /// use std::os::rtems::fs::MetadataExt; @@ -217,7 +228,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "rtems", doc = "```no_run")] + #[cfg_attr(not(target_os = "rtems"), doc = "```ignore (needs rtems)")] /// use std::fs; /// use std::io; /// use std::os::rtems::fs::MetadataExt; @@ -235,7 +247,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "rtems", doc = "```no_run")] + #[cfg_attr(not(target_os = "rtems"), doc = "```ignore (needs rtems)")] /// use std::fs; /// use std::io; /// use std::os::rtems::fs::MetadataExt; @@ -255,7 +268,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "rtems", doc = "```no_run")] + #[cfg_attr(not(target_os = "rtems"), doc = "```ignore (needs rtems)")] /// use std::fs; /// use std::io; /// use std::os::rtems::fs::MetadataExt; @@ -273,7 +287,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "rtems", doc = "```no_run")] + #[cfg_attr(not(target_os = "rtems"), doc = "```ignore (needs rtems)")] /// use std::fs; /// use std::io; /// use std::os::rtems::fs::MetadataExt; @@ -291,7 +306,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_os = "rtems", doc = "```no_run")] + #[cfg_attr(not(target_os = "rtems"), doc = "```ignore (needs rtems)")] /// use std::fs; /// use std::io; /// use std::os::rtems::fs::MetadataExt; diff --git a/library/std/src/os/solaris/net.rs b/library/std/src/os/solaris/net.rs index cea65f6ee7019..6376a0fe1024b 100644 --- a/library/std/src/os/solaris/net.rs +++ b/library/std/src/os/solaris/net.rs @@ -4,7 +4,6 @@ use crate::io; use crate::os::unix::net; -use crate::sealed::Sealed; use crate::sys::AsInner; /// solaris-specific functionality for `AF_UNIX` sockets [`UnixDatagram`] @@ -13,7 +12,7 @@ use crate::sys::AsInner; /// [`UnixDatagram`]: net::UnixDatagram /// [`UnixStream`]: net::UnixStream #[unstable(feature = "unix_socket_exclbind", issue = "123481")] -pub trait UnixSocketExt: Sealed { +pub impl(self) trait UnixSocketExt { /// Enables exclusive binding on the socket. /// /// If true and if the socket had been set with `SO_REUSEADDR`, diff --git a/library/std/src/os/solid/ffi.rs b/library/std/src/os/solid/ffi.rs index aaa2070a6abe9..d4c287ca70407 100644 --- a/library/std/src/os/solid/ffi.rs +++ b/library/std/src/os/solid/ffi.rs @@ -2,7 +2,8 @@ //! //! # Examples //! -//! ``` +#![cfg_attr(target_os = "solid", doc = "```")] +#![cfg_attr(not(target_os = "solid"), doc = "```ignore (needs solid)")] //! use std::ffi::OsString; //! use std::os::solid::ffi::OsStringExt; //! @@ -17,7 +18,8 @@ //! assert_eq!(bytes, b"foo"); //! ``` //! -//! ``` +#![cfg_attr(target_os = "solid", doc = "```")] +#![cfg_attr(not(target_os = "solid"), doc = "```ignore (needs solid)")] //! use std::ffi::OsStr; //! use std::os::solid::ffi::OsStrExt; //! diff --git a/library/std/src/os/solid/io.rs b/library/std/src/os/solid/io.rs index ac112e739170d..d4defb5f47fb0 100644 --- a/library/std/src/os/solid/io.rs +++ b/library/std/src/os/solid/io.rs @@ -180,9 +180,6 @@ impl fmt::Debug for OwnedFd { macro_rules! impl_is_terminal { ($($t:ty),*$(,)?) => {$( - #[unstable(feature = "sealed", issue = "none")] - impl crate::sealed::Sealed for $t {} - #[stable(feature = "is_terminal", since = "1.70.0")] impl io::IsTerminal for $t { #[inline] @@ -260,7 +257,8 @@ macro_rules! impl_owned_fd_traits { impl_owned_fd_traits! { TcpStream TcpListener UdpSocket } /// This impl allows implementing traits that require `AsFd` on Arc. -/// ``` +#[cfg_attr(target_os = "solid", doc = "```")] +#[cfg_attr(not(target_os = "solid"), doc = "```ignore (needs solid)")] /// # #[cfg(target_os = "solid_asp3")] mod group_cfg { /// # use std::os::solid::io::AsFd; /// use std::net::UdpSocket; diff --git a/library/std/src/os/unix/ffi/mod.rs b/library/std/src/os/unix/ffi/mod.rs index 5b49f50763d74..7736c8598ec45 100644 --- a/library/std/src/os/unix/ffi/mod.rs +++ b/library/std/src/os/unix/ffi/mod.rs @@ -2,7 +2,8 @@ //! //! # Examples //! -//! ``` +#![cfg_attr(target_family = "unix", doc = "```")] +#![cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] //! use std::ffi::OsString; //! use std::os::unix::ffi::OsStringExt; //! @@ -17,7 +18,8 @@ //! assert_eq!(bytes, b"foo"); //! ``` //! -//! ``` +#![cfg_attr(target_family = "unix", doc = "```")] +#![cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] //! use std::ffi::OsStr; //! use std::os::unix::ffi::OsStrExt; //! diff --git a/library/std/src/os/unix/ffi/os_str.rs b/library/std/src/os/unix/ffi/os_str.rs index da47112f7cb47..5beabd5618084 100644 --- a/library/std/src/os/unix/ffi/os_str.rs +++ b/library/std/src/os/unix/ffi/os_str.rs @@ -1,6 +1,5 @@ use crate::ffi::{OsStr, OsString}; use crate::mem; -use crate::sealed::Sealed; use crate::sys::os_str::Buf; use crate::sys::{AsInner, FromInner, IntoInner}; @@ -8,11 +7,8 @@ use crate::sys::{AsInner, FromInner, IntoInner}; // Keep this in mind when applying changes to this file that only apply to `unix`. /// Platform-specific extensions to [`OsString`]. -/// -/// This trait is sealed: it cannot be implemented outside the standard library. -/// This is so that future additional methods are not breaking changes. #[stable(feature = "rust1", since = "1.0.0")] -pub trait OsStringExt: Sealed { +pub impl(self) trait OsStringExt { /// Creates an [`OsString`] from a byte vector. /// /// See the module documentation for an example. @@ -39,11 +35,8 @@ impl OsStringExt for OsString { } /// Platform-specific extensions to [`OsStr`]. -/// -/// This trait is sealed: it cannot be implemented outside the standard library. -/// This is so that future additional methods are not breaking changes. #[stable(feature = "rust1", since = "1.0.0")] -pub trait OsStrExt: Sealed { +pub impl(self) trait OsStrExt { #[stable(feature = "rust1", since = "1.0.0")] /// Creates an [`OsStr`] from a byte slice. /// diff --git a/library/std/src/os/unix/fs.rs b/library/std/src/os/unix/fs.rs index 219b340b92469..b93f94225070a 100644 --- a/library/std/src/os/unix/fs.rs +++ b/library/std/src/os/unix/fs.rs @@ -14,11 +14,11 @@ use crate::fs::{self, OpenOptions, Permissions}; use crate::io::BorrowedCursor; use crate::os::unix::io::{AsFd, AsRawFd}; use crate::path::Path; -use crate::sealed::Sealed; use crate::sys::{AsInner, AsInnerMut, FromInner}; use crate::{io, sys}; // Tests for this module +#[cfg(not(target_os = "l4re"))] #[cfg(test)] mod tests; @@ -41,7 +41,8 @@ pub trait FileExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::io; /// use std::fs::File; /// use std::os::unix::prelude::FileExt; @@ -99,7 +100,8 @@ pub trait FileExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::io; /// use std::fs::File; /// use std::os::unix::prelude::FileExt; @@ -139,7 +141,8 @@ pub trait FileExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// #![feature(core_io_borrowed_buf)] /// #![feature(read_buf_at)] /// @@ -163,7 +166,7 @@ pub trait FileExt { /// } /// ``` #[unstable(feature = "read_buf_at", issue = "140771")] - fn read_buf_at(&self, buf: BorrowedCursor<'_>, offset: u64) -> io::Result<()> { + fn read_buf_at(&self, buf: BorrowedCursor<'_, u8>, offset: u64) -> io::Result<()> { io::default_read_buf(|b| self.read_at(b, offset), buf) } @@ -175,7 +178,8 @@ pub trait FileExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// #![feature(core_io_borrowed_buf)] /// #![feature(read_buf_at)] /// @@ -199,7 +203,12 @@ pub trait FileExt { /// } /// ``` #[unstable(feature = "read_buf_at", issue = "140771")] - fn read_buf_exact_at(&self, mut buf: BorrowedCursor<'_>, mut offset: u64) -> io::Result<()> { + #[doc(alias("read_exact_buf_at"))] + fn read_buf_exact_at( + &self, + mut buf: BorrowedCursor<'_, u8>, + mut offset: u64, + ) -> io::Result<()> { while buf.capacity() > 0 { let prev_written = buf.written(); match self.read_buf_at(buf.reborrow(), offset) { @@ -241,7 +250,8 @@ pub trait FileExt { /// Therefore, it is important to be vigilant while changing options to mitigate /// unexpected behavior. /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs::File; /// use std::io; /// use std::os::unix::prelude::FileExt; @@ -264,7 +274,8 @@ pub trait FileExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs::File; /// use std::io; /// use std::os::unix::prelude::FileExt; @@ -313,7 +324,8 @@ pub trait FileExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs::File; /// use std::io; /// use std::os::unix::prelude::FileExt; @@ -350,7 +362,7 @@ impl FileExt for fs::File { fn read_at(&self, buf: &mut [u8], offset: u64) -> io::Result { self.as_inner().read_at(buf, offset) } - fn read_buf_at(&self, buf: BorrowedCursor<'_>, offset: u64) -> io::Result<()> { + fn read_buf_at(&self, buf: BorrowedCursor<'_, u8>, offset: u64) -> io::Result<()> { self.as_inner().read_buf_at(buf, offset) } fn read_vectored_at(&self, bufs: &mut [io::IoSliceMut<'_>], offset: u64) -> io::Result { @@ -368,7 +380,8 @@ impl FileExt for fs::File { /// /// # Examples /// -/// ```no_run +#[cfg_attr(target_family = "unix", doc = "```no_run")] +#[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs::{File, Permissions}; /// use std::io::{ErrorKind, Result as IoResult}; /// use std::os::unix::fs::PermissionsExt; @@ -423,7 +436,8 @@ impl FileExt for fs::File { /// } /// ``` /// -/// ```no_run +#[cfg_attr(target_family = "unix", doc = "```no_run")] +#[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs::Permissions; /// use std::os::unix::fs::PermissionsExt; /// @@ -481,7 +495,8 @@ pub trait OpenOptionsExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs::OpenOptions; /// use std::os::unix::fs::OpenOptionsExt; /// @@ -504,7 +519,8 @@ pub trait OpenOptionsExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// # mod libc { pub const O_NOFOLLOW: i32 = 0; } /// use std::fs::OpenOptions; /// use std::os::unix::fs::OpenOptionsExt; @@ -540,7 +556,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::io; /// use std::fs; /// use std::os::unix::fs::MetadataExt; @@ -557,7 +574,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs; /// use std::os::unix::fs::MetadataExt; /// use std::io; @@ -574,7 +592,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs; /// use std::os::unix::fs::MetadataExt; /// use std::io; @@ -595,7 +614,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs; /// use std::os::unix::fs::MetadataExt; /// use std::io; @@ -612,7 +632,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs; /// use std::os::unix::fs::MetadataExt; /// use std::io; @@ -629,7 +650,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs; /// use std::os::unix::fs::MetadataExt; /// use std::io; @@ -646,7 +668,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs; /// use std::os::unix::fs::MetadataExt; /// use std::io; @@ -663,7 +686,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs; /// use std::os::unix::fs::MetadataExt; /// use std::io; @@ -680,7 +704,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs; /// use std::os::unix::fs::MetadataExt; /// use std::io; @@ -699,7 +724,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs; /// use std::os::unix::fs::MetadataExt; /// use std::io; @@ -716,7 +742,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs; /// use std::os::unix::fs::MetadataExt; /// use std::io; @@ -735,7 +762,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs; /// use std::os::unix::fs::MetadataExt; /// use std::io; @@ -752,7 +780,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs; /// use std::os::unix::fs::MetadataExt; /// use std::io; @@ -771,7 +800,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs; /// use std::os::unix::fs::MetadataExt; /// use std::io; @@ -788,7 +818,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs; /// use std::os::unix::fs::MetadataExt; /// use std::io; @@ -807,7 +838,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs; /// use std::os::unix::fs::MetadataExt; /// use std::io; @@ -891,7 +923,8 @@ pub trait FileTypeExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs; /// use std::os::unix::fs::FileTypeExt; /// use std::io; @@ -909,7 +942,8 @@ pub trait FileTypeExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs; /// use std::os::unix::fs::FileTypeExt; /// use std::io; @@ -927,7 +961,8 @@ pub trait FileTypeExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs; /// use std::os::unix::fs::FileTypeExt; /// use std::io; @@ -945,7 +980,8 @@ pub trait FileTypeExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs; /// use std::os::unix::fs::FileTypeExt; /// use std::io; @@ -985,7 +1021,8 @@ pub trait DirEntryExt { /// /// # Examples /// - /// ``` + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs; /// use std::os::unix::fs::DirEntryExt; /// @@ -1009,14 +1046,15 @@ impl DirEntryExt for fs::DirEntry { } } -/// Sealed Unix-specific extension methods for [`fs::DirEntry`]. +/// Unix-specific extension methods for [`fs::DirEntry`]. #[unstable(feature = "dir_entry_ext2", issue = "85573")] -pub trait DirEntryExt2: Sealed { +pub impl(self) trait DirEntryExt2 { /// Returns a reference to the underlying `OsStr` of this entry's filename. /// /// # Examples /// - /// ``` + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// #![feature(dir_entry_ext2)] /// use std::os::unix::fs::DirEntryExt2; /// use std::{fs, io}; @@ -1035,10 +1073,6 @@ pub trait DirEntryExt2: Sealed { fn file_name_ref(&self) -> &OsStr; } -/// Allows extension traits within `std`. -#[unstable(feature = "sealed", issue = "none")] -impl Sealed for fs::DirEntry {} - #[unstable(feature = "dir_entry_ext2", issue = "85573")] impl DirEntryExt2 for fs::DirEntry { fn file_name_ref(&self) -> &OsStr { @@ -1052,7 +1086,8 @@ impl DirEntryExt2 for fs::DirEntry { /// /// # Examples /// -/// ```no_run +#[cfg_attr(target_family = "unix", doc = "```no_run")] +#[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::fs; /// /// fn main() -> std::io::Result<()> { @@ -1061,6 +1096,7 @@ impl DirEntryExt2 for fs::DirEntry { /// } /// ``` #[stable(feature = "symlink", since = "1.1.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_symlink")] pub fn symlink, Q: AsRef>(original: P, link: Q) -> io::Result<()> { sys::fs::symlink(original.as_ref(), link.as_ref()) } @@ -1073,7 +1109,8 @@ pub trait DirBuilderExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::fs::DirBuilder; /// use std::os::unix::fs::DirBuilderExt; /// @@ -1110,7 +1147,8 @@ impl DirBuilderExt for fs::DirBuilder { /// /// # Examples /// -/// ```no_run +#[cfg_attr(target_family = "unix", doc = "```no_run")] +#[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::fs; /// /// fn main() -> std::io::Result<()> { @@ -1129,7 +1167,8 @@ pub fn chown>(dir: P, uid: Option, gid: Option) -> io:: /// /// # Examples /// -/// ```no_run +#[cfg_attr(target_family = "unix", doc = "```no_run")] +#[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::fs; /// /// fn main() -> std::io::Result<()> { @@ -1150,7 +1189,8 @@ pub fn fchown(fd: F, uid: Option, gid: Option) -> io::Result< /// /// # Examples /// -/// ```no_run +#[cfg_attr(target_family = "unix", doc = "```no_run")] +#[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::fs; /// /// fn main() -> std::io::Result<()> { @@ -1172,7 +1212,8 @@ pub fn lchown>(dir: P, uid: Option, gid: Option) -> io: /// /// # Examples /// -/// ```no_run +#[cfg_attr(target_family = "unix", doc = "```no_run")] +#[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::fs; /// /// fn main() -> std::io::Result<()> { @@ -1192,7 +1233,8 @@ pub fn chroot>(dir: P) -> io::Result<()> { /// /// # Examples /// -/// ```no_run +#[cfg_attr(target_family = "unix", doc = "```no_run")] +#[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// # #![feature(unix_mkfifo)] /// # #[cfg(not(unix))] /// # fn main() {} diff --git a/library/std/src/os/unix/io/mod.rs b/library/std/src/os/unix/io/mod.rs index 18b0f70c06877..4afb8ffa71017 100644 --- a/library/std/src/os/unix/io/mod.rs +++ b/library/std/src/os/unix/io/mod.rs @@ -103,7 +103,7 @@ use crate::sys::cvt; mod tests; #[unstable(feature = "stdio_swap", issue = "150667")] -pub trait StdioExt: crate::sealed::Sealed { +pub impl(self) trait StdioExt { /// Redirects the stdio file descriptor to point to the file description underpinning `fd`. /// /// Rust std::io write buffers (if any) are flushed, but other runtimes @@ -119,7 +119,8 @@ pub trait StdioExt: crate::sealed::Sealed { /// /// [currently]: crate::io#platform-specific-behavior /// - /// ``` + #[cfg_attr(target_family = "unix", doc = "```")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// #![feature(stdio_swap)] /// use std::io::{self, Read, Write}; /// use std::os::unix::io::StdioExt; @@ -211,16 +212,15 @@ fn null_fd() -> io::Result { fn replace_stdio_fd(this: BorrowedFd<'_>, other: OwnedFd) -> io::Result<()> { cfg_select! { all(target_os = "wasi", target_env = "p1") => { - cvt(unsafe { libc::__wasilibc_fd_renumber(other.as_raw_fd(), this.as_raw_fd()) }).map(|_| ()) + cvt(unsafe { libc::__wasilibc_fd_renumber(other.as_raw_fd(), this.as_raw_fd()) }) + .map(|_| ()) } not(any( - target_arch = "wasm32", + all(target_arch = "wasm32", not(target_os = "emscripten")), target_os = "hermit", target_os = "trusty", target_os = "motor" - )) => { - cvt(unsafe {libc::dup2(other.as_raw_fd(), this.as_raw_fd())}).map(|_| ()) - } + )) => cvt(unsafe { libc::dup2(other.as_raw_fd(), this.as_raw_fd()) }).map(|_| ()), _ => { let _ = (this, other); Err(io::Error::UNSUPPORTED_PLATFORM) diff --git a/library/std/src/os/unix/io/tests.rs b/library/std/src/os/unix/io/tests.rs index fc147730578ac..ce5e7aac5a99d 100644 --- a/library/std/src/os/unix/io/tests.rs +++ b/library/std/src/os/unix/io/tests.rs @@ -2,8 +2,7 @@ use crate::os::unix::io::RawFd; #[test] fn test_raw_fd_layout() { - // `OwnedFd` and `BorrowedFd` use `rustc_layout_scalar_valid_range_start` - // and `rustc_layout_scalar_valid_range_end`, with values that depend on + // `OwnedFd` and `BorrowedFd` use pattern types, with ranges that depend on // the bit width of `RawFd`. If this ever changes, those values will need // to be updated. assert_eq!(size_of::(), 4); diff --git a/library/std/src/os/unix/mod.rs b/library/std/src/os/unix/mod.rs index 78c957270c451..c994174b744dd 100644 --- a/library/std/src/os/unix/mod.rs +++ b/library/std/src/os/unix/mod.rs @@ -11,7 +11,8 @@ //! //! # Examples //! -//! ```no_run +#![cfg_attr(target_family = "unix", doc = "```no_run")] +#![cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] //! use std::fs::File; //! use std::os::unix::prelude::*; //! @@ -69,7 +70,7 @@ mod platform { pub use crate::os::linux::*; #[cfg(target_os = "netbsd")] pub use crate::os::netbsd::*; - #[cfg(target_os = "nto")] + #[cfg(any(target_os = "nto", target_os = "qnx"))] pub use crate::os::nto::*; #[cfg(target_os = "nuttx")] pub use crate::os::nuttx::*; @@ -94,6 +95,7 @@ pub mod net; pub mod process; pub mod raw; pub mod thread; +pub mod xdg; /// A prelude for conveniently writing platform-specific code. /// diff --git a/library/std/src/os/unix/net/addr.rs b/library/std/src/os/unix/net/addr.rs index 0748f6984a825..3daddc2d34323 100644 --- a/library/std/src/os/unix/net/addr.rs +++ b/library/std/src/os/unix/net/addr.rs @@ -4,7 +4,6 @@ use crate::ffi::OsStr; use crate::os::net::linux_ext; use crate::os::unix::ffi::OsStrExt; use crate::path::Path; -use crate::sealed::Sealed; use crate::sys::cvt; use crate::{fmt, io, mem, ptr}; @@ -54,7 +53,15 @@ pub(super) fn sockaddr_un(path: &Path) -> io::Result<(libc::sockaddr_un, libc::s let mut len = SUN_PATH_OFFSET + bytes.len(); match bytes.get(0) { Some(&0) | None => {} - Some(_) => len += 1, + Some(_) => { + // on QNX7.1 and QNX8 the `len` value returned by the SUN_LEN + // macro in its libc does not include the null byte in the count so + // don't add it here to match what a C program passes to bind(2) and + // similar functions + if cfg!(not(any(target_os = "qnx", target_env = "nto71"))) { + len += 1 + } + } } Ok((addr, len as libc::socklen_t)) } @@ -69,7 +76,8 @@ enum AddressKind<'a> { /// /// # Examples /// -/// ``` +#[cfg_attr(target_family = "unix", doc = "```")] +#[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixListener; /// /// let socket = match UnixListener::bind("/tmp/sock") { @@ -138,7 +146,8 @@ impl SocketAddr { /// /// # Examples /// - /// ``` + #[cfg_attr(target_family = "unix", doc = "```")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::SocketAddr; /// use std::path::Path; /// @@ -151,7 +160,8 @@ impl SocketAddr { /// /// Creating a `SocketAddr` with a NULL byte results in an error. /// - /// ``` + #[cfg_attr(target_family = "unix", doc = "```")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::SocketAddr; /// /// assert!(SocketAddr::from_pathname("/path/with/\0/bytes").is_err()); @@ -170,7 +180,8 @@ impl SocketAddr { /// /// A named address: /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixListener; /// /// fn main() -> std::io::Result<()> { @@ -183,7 +194,8 @@ impl SocketAddr { /// /// An unnamed address: /// - /// ``` + #[cfg_attr(target_family = "unix", doc = "```")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixDatagram; /// /// fn main() -> std::io::Result<()> { @@ -205,7 +217,8 @@ impl SocketAddr { /// /// With a pathname: /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixListener; /// use std::path::Path; /// @@ -219,7 +232,8 @@ impl SocketAddr { /// /// Without a pathname: /// - /// ``` + #[cfg_attr(target_family = "unix", doc = "```")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixDatagram; /// /// fn main() -> std::io::Result<()> { @@ -248,14 +262,15 @@ impl SocketAddr { } else if self.addr.sun_path[0] == 0 { AddressKind::Abstract(ByteStr::from_bytes(&path[1..len])) } else { - AddressKind::Pathname(OsStr::from_bytes(&path[..len - 1]).as_ref()) + // linux adds a trailing NUL and counts it in the length, freebsd, netbsd + // and qnx do not, and a caller may bind(2) without one either. unix(7) + // gives the portable rule: strnlen(sun_path, len - offsetof(sun_path)) + let end = core::slice::memchr::memchr(0, &path[..len]).unwrap_or(len); + AddressKind::Pathname(OsStr::from_bytes(&path[..end]).as_ref()) } } } -#[stable(feature = "unix_socket_abstract", since = "1.70.0")] -impl Sealed for SocketAddr {} - #[doc(cfg(any(target_os = "android", target_os = "linux", target_os = "cygwin")))] #[cfg(any(doc, target_os = "android", target_os = "linux", target_os = "cygwin"))] #[stable(feature = "unix_socket_abstract", since = "1.70.0")] diff --git a/library/std/src/os/unix/net/ancillary.rs b/library/std/src/os/unix/net/ancillary.rs index d0984bdfb99d1..bdf0384e34f80 100644 --- a/library/std/src/os/unix/net/ancillary.rs +++ b/library/std/src/os/unix/net/ancillary.rs @@ -506,12 +506,12 @@ impl<'a> AncillaryData<'a> { fn try_from_cmsghdr(cmsg: &'a libc::cmsghdr) -> Result { unsafe { let cmsg_len_zero = libc::CMSG_LEN(0) as usize; - let data_len = (*cmsg).cmsg_len as usize - cmsg_len_zero; + let data_len = cmsg.cmsg_len as usize - cmsg_len_zero; let data = libc::CMSG_DATA(cmsg).cast(); let data = from_raw_parts(data, data_len); - match (*cmsg).cmsg_level { - libc::SOL_SOCKET => match (*cmsg).cmsg_type { + match cmsg.cmsg_level { + libc::SOL_SOCKET => match cmsg.cmsg_type { libc::SCM_RIGHTS => Ok(AncillaryData::as_rights(data)), #[cfg(any(target_os = "android", target_os = "linux", target_os = "cygwin"))] libc::SCM_CREDENTIALS => Ok(AncillaryData::as_credentials(data)), @@ -524,7 +524,7 @@ impl<'a> AncillaryData<'a> { } }, cmsg_level => { - Err(AncillaryError::Unknown { cmsg_level, cmsg_type: (*cmsg).cmsg_type }) + Err(AncillaryError::Unknown { cmsg_level, cmsg_type: cmsg.cmsg_type }) } } } @@ -576,7 +576,15 @@ impl<'a> Iterator for Messages<'a> { /// A Unix socket Ancillary data struct. /// /// # Example -/// ```no_run +/// +#[cfg_attr( + any(target_os = "android", target_os = "linux", target_os = "cygwin"), + doc = "```no_run" +)] +#[cfg_attr( + not(any(target_os = "android", target_os = "linux", target_os = "cygwin")), + doc = "```ignore (needs unix)" +)] /// #![feature(unix_socket_ancillary_data)] /// use std::os::unix::net::{UnixStream, SocketAncillary, AncillaryData}; /// use std::io::IoSliceMut; @@ -615,7 +623,14 @@ impl<'a> SocketAncillary<'a> { /// /// # Example /// - /// ```no_run + #[cfg_attr( + any(target_os = "android", target_os = "linux", target_os = "cygwin"), + doc = "```no_run" + )] + #[cfg_attr( + not(any(target_os = "android", target_os = "linux", target_os = "cygwin")), + doc = "```ignore (needs unix)" + )] /// # #![allow(unused_mut)] /// #![feature(unix_socket_ancillary_data)] /// use std::os::unix::net::SocketAncillary; @@ -658,7 +673,14 @@ impl<'a> SocketAncillary<'a> { /// /// # Example /// - /// ```no_run + #[cfg_attr( + any(target_os = "android", target_os = "linux", target_os = "cygwin"), + doc = "```no_run" + )] + #[cfg_attr( + not(any(target_os = "android", target_os = "linux", target_os = "cygwin")), + doc = "```ignore (needs unix)" + )] /// #![feature(unix_socket_ancillary_data)] /// use std::os::unix::net::{UnixStream, SocketAncillary}; /// use std::io::IoSliceMut; @@ -692,7 +714,14 @@ impl<'a> SocketAncillary<'a> { /// /// # Example /// - /// ```no_run + #[cfg_attr( + any(target_os = "android", target_os = "linux", target_os = "cygwin"), + doc = "```no_run" + )] + #[cfg_attr( + not(any(target_os = "android", target_os = "linux", target_os = "cygwin")), + doc = "```ignore (needs unix)" + )] /// #![feature(unix_socket_ancillary_data)] /// use std::os::unix::net::{UnixStream, SocketAncillary}; /// use std::os::unix::io::AsRawFd; @@ -715,7 +744,7 @@ impl<'a> SocketAncillary<'a> { pub fn add_fds(&mut self, fds: &[RawFd]) -> bool { self.truncated = false; add_to_ancillary_data( - &mut self.buffer, + self.buffer, &mut self.length, fds, libc::SOL_SOCKET, @@ -742,7 +771,7 @@ impl<'a> SocketAncillary<'a> { pub fn add_creds(&mut self, creds: &[SocketCred]) -> bool { self.truncated = false; add_to_ancillary_data( - &mut self.buffer, + self.buffer, &mut self.length, creds, libc::SOL_SOCKET, @@ -759,7 +788,14 @@ impl<'a> SocketAncillary<'a> { /// /// # Example /// - /// ```no_run + #[cfg_attr( + any(target_os = "android", target_os = "linux", target_os = "cygwin"), + doc = "```no_run" + )] + #[cfg_attr( + not(any(target_os = "android", target_os = "linux", target_os = "cygwin")), + doc = "```ignore (needs unix)" + )] /// #![feature(unix_socket_ancillary_data)] /// use std::os::unix::net::{UnixStream, SocketAncillary, AncillaryData}; /// use std::io::IoSliceMut; diff --git a/library/std/src/os/unix/net/datagram.rs b/library/std/src/os/unix/net/datagram.rs index beda370006f73..e03ecd7eed9ea 100644 --- a/library/std/src/os/unix/net/datagram.rs +++ b/library/std/src/os/unix/net/datagram.rs @@ -9,6 +9,7 @@ target_os = "illumos", target_os = "haiku", target_os = "nto", + target_os = "qnx", target_os = "cygwin" ))] use libc::MSG_NOSIGNAL; @@ -21,7 +22,6 @@ use crate::io::{IoSlice, IoSliceMut}; use crate::net::Shutdown; use crate::os::unix::io::{AsFd, AsRawFd, BorrowedFd, FromRawFd, IntoRawFd, OwnedFd, RawFd}; use crate::path::Path; -use crate::sealed::Sealed; use crate::sys::net::Socket; use crate::sys::{AsInner, FromInner, IntoInner, cvt}; use crate::time::Duration; @@ -37,6 +37,7 @@ use crate::{fmt, io}; target_os = "illumos", target_os = "haiku", target_os = "nto", + target_os = "qnx", target_os = "cygwin" )))] const MSG_NOSIGNAL: core::ffi::c_int = 0x0; @@ -45,7 +46,8 @@ const MSG_NOSIGNAL: core::ffi::c_int = 0x0; /// /// # Examples /// -/// ```no_run +#[cfg_attr(target_family = "unix", doc = "```no_run")] +#[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixDatagram; /// /// fn main() -> std::io::Result<()> { @@ -60,10 +62,6 @@ const MSG_NOSIGNAL: core::ffi::c_int = 0x0; #[stable(feature = "unix_socket", since = "1.10.0")] pub struct UnixDatagram(Socket); -/// Allows extension traits within `std`. -#[unstable(feature = "sealed", issue = "none")] -impl Sealed for UnixDatagram {} - #[stable(feature = "unix_socket", since = "1.10.0")] impl fmt::Debug for UnixDatagram { fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { @@ -84,7 +82,8 @@ impl UnixDatagram { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixDatagram; /// /// let sock = match UnixDatagram::bind("/path/to/the/socket") { @@ -111,7 +110,8 @@ impl UnixDatagram { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::{UnixDatagram}; /// /// fn main() -> std::io::Result<()> { @@ -145,7 +145,8 @@ impl UnixDatagram { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixDatagram; /// /// let sock = match UnixDatagram::unbound() { @@ -168,7 +169,8 @@ impl UnixDatagram { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixDatagram; /// /// let (sock1, sock2) = match UnixDatagram::pair() { @@ -196,7 +198,8 @@ impl UnixDatagram { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixDatagram; /// /// fn main() -> std::io::Result<()> { @@ -225,7 +228,8 @@ impl UnixDatagram { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::{UnixDatagram}; /// /// fn main() -> std::io::Result<()> { @@ -263,7 +267,8 @@ impl UnixDatagram { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixDatagram; /// /// fn main() -> std::io::Result<()> { @@ -281,7 +286,8 @@ impl UnixDatagram { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixDatagram; /// /// fn main() -> std::io::Result<()> { @@ -303,7 +309,8 @@ impl UnixDatagram { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixDatagram; /// /// fn main() -> std::io::Result<()> { @@ -353,7 +360,8 @@ impl UnixDatagram { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixDatagram; /// /// fn main() -> std::io::Result<()> { @@ -375,7 +383,8 @@ impl UnixDatagram { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixDatagram; /// /// fn main() -> std::io::Result<()> { @@ -508,7 +517,8 @@ impl UnixDatagram { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixDatagram; /// /// fn main() -> std::io::Result<()> { @@ -542,7 +552,8 @@ impl UnixDatagram { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::{UnixDatagram}; /// /// fn main() -> std::io::Result<()> { @@ -578,7 +589,8 @@ impl UnixDatagram { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixDatagram; /// /// fn main() -> std::io::Result<()> { @@ -699,7 +711,8 @@ impl UnixDatagram { /// /// # Examples /// - /// ``` + #[cfg_attr(target_family = "unix", doc = "```")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixDatagram; /// use std::time::Duration; /// @@ -714,7 +727,8 @@ impl UnixDatagram { /// An [`Err`] is returned if the zero [`Duration`] is passed to this /// method: /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::io; /// use std::os::unix::net::UnixDatagram; /// use std::time::Duration; @@ -743,7 +757,8 @@ impl UnixDatagram { /// /// # Examples /// - /// ``` + #[cfg_attr(target_family = "unix", doc = "```")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixDatagram; /// use std::time::Duration; /// @@ -758,7 +773,8 @@ impl UnixDatagram { /// An [`Err`] is returned if the zero [`Duration`] is passed to this /// method: /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::io; /// use std::os::unix::net::UnixDatagram; /// use std::time::Duration; @@ -780,7 +796,8 @@ impl UnixDatagram { /// /// # Examples /// - /// ``` + #[cfg_attr(target_family = "unix", doc = "```")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixDatagram; /// use std::time::Duration; /// @@ -801,7 +818,8 @@ impl UnixDatagram { /// /// # Examples /// - /// ``` + #[cfg_attr(target_family = "unix", doc = "```")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixDatagram; /// use std::time::Duration; /// @@ -822,7 +840,8 @@ impl UnixDatagram { /// /// # Examples /// - /// ``` + #[cfg_attr(target_family = "unix", doc = "```")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixDatagram; /// /// fn main() -> std::io::Result<()> { @@ -865,7 +884,8 @@ impl UnixDatagram { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixDatagram; /// /// fn main() -> std::io::Result<()> { @@ -887,7 +907,8 @@ impl UnixDatagram { /// specified portions to immediately return with an appropriate value /// (see the documentation of [`Shutdown`]). /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixDatagram; /// use std::net::Shutdown; /// @@ -911,7 +932,8 @@ impl UnixDatagram { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// #![feature(unix_socket_peek)] /// /// use std::os::unix::net::UnixDatagram; @@ -943,7 +965,8 @@ impl UnixDatagram { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// #![feature(unix_socket_peek)] /// /// use std::os::unix::net::UnixDatagram; diff --git a/library/std/src/os/unix/net/listener.rs b/library/std/src/os/unix/net/listener.rs index 99eef7f4013d6..b7f8d25a85ae5 100644 --- a/library/std/src/os/unix/net/listener.rs +++ b/library/std/src/os/unix/net/listener.rs @@ -9,7 +9,8 @@ use crate::{fmt, io, mem}; /// /// # Examples /// -/// ```no_run +#[cfg_attr(target_family = "unix", doc = "```no_run")] +#[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::thread; /// use std::os::unix::net::{UnixStream, UnixListener}; /// @@ -56,7 +57,8 @@ impl UnixListener { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixListener; /// /// let listener = match UnixListener::bind("/path/to/the/socket") { @@ -115,7 +117,8 @@ impl UnixListener { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::{UnixListener}; /// /// fn main() -> std::io::Result<()> { @@ -160,7 +163,8 @@ impl UnixListener { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixListener; /// /// fn main() -> std::io::Result<()> { @@ -190,7 +194,8 @@ impl UnixListener { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixListener; /// /// fn main() -> std::io::Result<()> { @@ -208,7 +213,8 @@ impl UnixListener { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixListener; /// /// fn main() -> std::io::Result<()> { @@ -232,7 +238,8 @@ impl UnixListener { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixListener; /// /// fn main() -> std::io::Result<()> { @@ -250,7 +257,8 @@ impl UnixListener { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixListener; /// /// fn main() -> std::io::Result<()> { @@ -277,7 +285,8 @@ impl UnixListener { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::thread; /// use std::os::unix::net::{UnixStream, UnixListener}; /// @@ -372,7 +381,8 @@ impl<'a> IntoIterator for &'a UnixListener { /// /// # Examples /// -/// ```no_run +#[cfg_attr(target_family = "unix", doc = "```no_run")] +#[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::thread; /// use std::os::unix::net::{UnixStream, UnixListener}; /// diff --git a/library/std/src/os/unix/net/mod.rs b/library/std/src/os/unix/net/mod.rs index a44b23a77d2d4..92d2696a5ef43 100644 --- a/library/std/src/os/unix/net/mod.rs +++ b/library/std/src/os/unix/net/mod.rs @@ -10,7 +10,7 @@ mod ancillary; mod datagram; mod listener; mod stream; -#[cfg(all(test, not(target_os = "emscripten")))] +#[cfg(all(test, not(any(target_os = "emscripten", target_os = "l4re"))))] mod tests; #[cfg(any( target_os = "android", @@ -20,6 +20,7 @@ mod tests; target_os = "netbsd", target_os = "openbsd", target_os = "nto", + target_os = "qnx", target_vendor = "apple", target_os = "cygwin" ))] @@ -44,6 +45,7 @@ pub use self::stream::*; target_os = "netbsd", target_os = "openbsd", target_os = "nto", + target_os = "qnx", target_vendor = "apple", target_os = "cygwin", ))] diff --git a/library/std/src/os/unix/net/stream.rs b/library/std/src/os/unix/net/stream.rs index 30124d96951eb..31a908dfe187e 100644 --- a/library/std/src/os/unix/net/stream.rs +++ b/library/std/src/os/unix/net/stream.rs @@ -1,11 +1,17 @@ cfg_select! { any( - target_os = "linux", target_os = "android", + target_os = "linux", + target_os = "android", target_os = "hurd", - target_os = "dragonfly", target_os = "freebsd", - target_os = "openbsd", target_os = "netbsd", - target_os = "solaris", target_os = "illumos", - target_os = "haiku", target_os = "nto", + target_os = "dragonfly", + target_os = "freebsd", + target_os = "openbsd", + target_os = "netbsd", + target_os = "solaris", + target_os = "illumos", + target_os = "haiku", + target_os = "nto", + target_os = "qnx", target_os = "cygwin", ) => { use libc::MSG_NOSIGNAL; @@ -26,6 +32,7 @@ use super::{SocketAncillary, recv_vectored_with_ancillary_from, send_vectored_wi target_os = "netbsd", target_os = "openbsd", target_os = "nto", + target_os = "qnx", target_vendor = "apple", target_os = "cygwin" ))] @@ -35,7 +42,6 @@ use crate::io::{self, IoSlice, IoSliceMut}; use crate::net::Shutdown; use crate::os::unix::io::{AsFd, AsRawFd, BorrowedFd, FromRawFd, IntoRawFd, OwnedFd, RawFd}; use crate::path::Path; -use crate::sealed::Sealed; use crate::sys::net::Socket; use crate::sys::{AsInner, FromInner, cvt}; use crate::time::Duration; @@ -44,7 +50,8 @@ use crate::time::Duration; /// /// # Examples /// -/// ```no_run +#[cfg_attr(target_family = "unix", doc = "```no_run")] +#[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixStream; /// use std::io::prelude::*; /// @@ -73,10 +80,6 @@ use crate::time::Duration; #[stable(feature = "unix_socket", since = "1.10.0")] pub struct UnixStream(pub(super) Socket); -/// Allows extension traits within `std`. -#[unstable(feature = "sealed", issue = "none")] -impl Sealed for UnixStream {} - #[stable(feature = "unix_socket", since = "1.10.0")] impl fmt::Debug for UnixStream { fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { @@ -97,7 +100,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixStream; /// /// let socket = match UnixStream::connect("/tmp/sock") { @@ -125,7 +129,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::{UnixListener, UnixStream}; /// /// fn main() -> std::io::Result<()> { @@ -141,7 +146,7 @@ impl UnixStream { /// }; /// Ok(()) /// } - /// ```` + /// ``` #[stable(feature = "unix_socket_abstract", since = "1.70.0")] pub fn connect_addr(socket_addr: &SocketAddr) -> io::Result { unsafe { @@ -161,7 +166,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixStream; /// /// let (sock1, sock2) = match UnixStream::pair() { @@ -187,7 +193,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixStream; /// /// fn main() -> std::io::Result<()> { @@ -205,7 +212,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixStream; /// /// fn main() -> std::io::Result<()> { @@ -223,7 +231,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixStream; /// /// fn main() -> std::io::Result<()> { @@ -241,7 +250,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// #![feature(peer_credentials_unix_socket)] /// use std::os::unix::net::UnixStream; /// @@ -260,6 +270,7 @@ impl UnixStream { target_os = "netbsd", target_os = "openbsd", target_os = "nto", + target_os = "qnx", target_vendor = "apple", target_os = "cygwin" ))] @@ -277,7 +288,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixStream; /// use std::time::Duration; /// @@ -291,7 +303,8 @@ impl UnixStream { /// An [`Err`] is returned if the zero [`Duration`] is passed to this /// method: /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::io; /// use std::os::unix::net::UnixStream; /// use std::time::Duration; @@ -319,7 +332,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixStream; /// use std::time::Duration; /// @@ -334,7 +348,8 @@ impl UnixStream { /// An [`Err`] is returned if the zero [`Duration`] is passed to this /// method: /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::io; /// use std::os::unix::net::UnixStream; /// use std::time::Duration; @@ -356,7 +371,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixStream; /// use std::time::Duration; /// @@ -376,7 +392,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixStream; /// use std::time::Duration; /// @@ -397,7 +414,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixStream; /// /// fn main() -> std::io::Result<()> { @@ -440,7 +458,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixStream; /// /// fn main() -> std::io::Result<()> { @@ -467,7 +486,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::os::unix::net::UnixStream; /// use std::net::Shutdown; /// @@ -491,7 +511,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// #![feature(unix_socket_peek)] /// /// use std::os::unix::net::UnixStream; @@ -617,7 +638,7 @@ impl io::Read for UnixStream { io::Read::read(&mut &*self, buf) } - fn read_buf(&mut self, buf: io::BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, buf: io::BorrowedCursor<'_, u8>) -> io::Result<()> { io::Read::read_buf(&mut &*self, buf) } @@ -627,7 +648,7 @@ impl io::Read for UnixStream { #[inline] fn is_read_vectored(&self) -> bool { - io::Read::is_read_vectored(&&*self) + io::Read::is_read_vectored(&self) } } @@ -637,7 +658,7 @@ impl<'a> io::Read for &'a UnixStream { self.0.read(buf) } - fn read_buf(&mut self, buf: io::BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, buf: io::BorrowedCursor<'_, u8>) -> io::Result<()> { self.0.read_buf(buf) } @@ -663,7 +684,7 @@ impl io::Write for UnixStream { #[inline] fn is_write_vectored(&self) -> bool { - io::Write::is_write_vectored(&&*self) + io::Write::is_write_vectored(&self) } fn flush(&mut self) -> io::Result<()> { diff --git a/library/std/src/os/unix/net/tests.rs b/library/std/src/os/unix/net/tests.rs index d88c97113efeb..9c3119e787b33 100644 --- a/library/std/src/os/unix/net/tests.rs +++ b/library/std/src/os/unix/net/tests.rs @@ -9,6 +9,7 @@ use crate::os::cygwin::net::{SocketAddrExt, UnixSocketExt}; use crate::os::linux::net::{SocketAddrExt, UnixSocketExt}; #[cfg(any(target_os = "android", target_os = "linux"))] use crate::os::unix::io::AsRawFd; +use crate::path::Path; use crate::test_helpers::tmpdir; use crate::thread; use crate::time::Duration; @@ -22,6 +23,35 @@ macro_rules! or_panic { }; } +#[test] +fn sock_addr_from_pathname() { + let address = or_panic!(SocketAddr::from_pathname("/path/to/socket")); + assert_eq!(address.as_pathname(), Some(Path::new("/path/to/socket"))); +} + +// the trailing NUL is not counted in the reported length on freebsd, netbsd +// and qnx, and a caller may bind(2) without one anywhere +#[test] +fn sock_addr_without_trailing_nul() { + const PATH: &[u8] = b"/path/to/socket"; + + // SAFETY: all zeros is a valid representation for `sockaddr_un`. + let mut addr: libc::sockaddr_un = unsafe { crate::mem::zeroed() }; + addr.sun_family = libc::AF_UNIX as libc::sa_family_t; + for (dst, &src) in addr.sun_path.iter_mut().zip(PATH) { + *dst = src as _; + } + let offset = crate::mem::offset_of!(libc::sockaddr_un, sun_path); + + // length excluding the NUL, as reported by freebsd, netbsd and qnx + let address = or_panic!(SocketAddr::from_parts(addr, (offset + PATH.len()) as _)); + assert_eq!(address.as_pathname(), Some(Path::new("/path/to/socket"))); + + // length including the NUL, as reported by linux + let address = or_panic!(SocketAddr::from_parts(addr, (offset + PATH.len() + 1) as _)); + assert_eq!(address.as_pathname(), Some(Path::new("/path/to/socket"))); +} + #[test] #[cfg_attr(target_os = "android", ignore)] // Android SELinux rules prevent creating Unix sockets #[cfg_attr(target_os = "vxworks", ignore = "Unix sockets are not implemented in VxWorks")] @@ -32,6 +62,7 @@ fn basic() { let msg2 = b"world!"; let listener = or_panic!(UnixListener::bind(&socket_path)); + assert_eq!(Some(&*socket_path), listener.local_addr().unwrap().as_pathname()); let thread = thread::spawn(move || { let mut stream = or_panic!(listener.accept()).0; let mut buf = [0; 5]; @@ -79,6 +110,8 @@ fn pair() { let msg2 = b"world!"; let (mut s1, mut s2) = or_panic!(UnixStream::pair()); + assert!(s1.local_addr().unwrap().is_unnamed()); + assert!(s2.peer_addr().unwrap().is_unnamed()); let thread = thread::spawn(move || { // s1 must be moved in or the test will hang! let mut buf = [0; 5]; @@ -176,7 +209,7 @@ fn long_path() { } #[test] -#[cfg(not(target_os = "nto"))] +#[cfg(not(any(target_os = "nto", target_os = "qnx")))] #[cfg_attr(target_os = "android", ignore)] // Android SELinux rules prevent creating Unix sockets #[cfg_attr(target_os = "cygwin", ignore)] // Cygwin connect needs handshake #[cfg_attr(target_os = "vxworks", ignore = "Unix sockets are not implemented in VxWorks")] diff --git a/library/std/src/os/unix/net/ucred.rs b/library/std/src/os/unix/net/ucred.rs index 1395d2ef4be3c..36b67cb1163d8 100644 --- a/library/std/src/os/unix/net/ucred.rs +++ b/library/std/src/os/unix/net/ucred.rs @@ -30,7 +30,8 @@ pub(super) use self::impl_apple::peer_cred; target_os = "freebsd", target_os = "openbsd", target_os = "netbsd", - target_os = "nto" + target_os = "nto", + target_os = "qnx" ))] pub(super) use self::impl_bsd::peer_cred; #[cfg(any(target_os = "android", target_os = "linux", target_os = "cygwin"))] @@ -79,6 +80,7 @@ mod impl_linux { target_os = "openbsd", target_os = "netbsd", target_os = "nto", + target_os = "qnx", ))] mod impl_bsd { use super::UCred; diff --git a/library/std/src/os/unix/process.rs b/library/std/src/os/unix/process.rs index fab1b20b8c0e9..9fa731de82691 100644 --- a/library/std/src/os/unix/process.rs +++ b/library/std/src/os/unix/process.rs @@ -7,7 +7,8 @@ use crate::ffi::OsStr; use crate::os::unix::io::{AsFd, AsRawFd, BorrowedFd, FromRawFd, IntoRawFd, OwnedFd, RawFd}; use crate::path::Path; -use crate::sealed::Sealed; +#[cfg(doc)] +use crate::process::{ExitStatus, ExitStatusError}; use crate::sys::process::ChildPipe; use crate::sys::{AsInner, AsInnerMut, FromInner, IntoInner}; use crate::{io, process, sys}; @@ -17,10 +18,10 @@ cfg_select! { type UserId = u16; type GroupId = u16; } - target_os = "nto" => { - // Both IDs are signed, see `sys/target_nto.h` of the QNX Neutrino SDP. + any(target_os = "nto", target_os = "qnx") => { + // Both IDs are signed, see `sys/target_nto.h` of the QNX SDP. // Only positive values should be used, see e.g. - // https://www.qnx.com/developers/docs/7.1/#com.qnx.doc.neutrino.lib_ref/topic/s/setuid.html + // https://www.qnx.com/developers/docs/7.1/com.qnx.doc.neutrino.lib_ref/topic/s/setuid.html type UserId = i32; type GroupId = i32; } @@ -31,11 +32,8 @@ cfg_select! { } /// Unix-specific extensions to the [`process::Command`] builder. -/// -/// This trait is sealed: it cannot be implemented outside the standard library. -/// This is so that future additional methods are not breaking changes. #[stable(feature = "rust1", since = "1.0.0")] -pub trait CommandExt: Sealed { +pub impl(self) trait CommandExt { /// Sets the child process's user ID. This translates to a /// `setuid` call in the child process. Failure in the `setuid` /// call will cause the spawn to fail. @@ -104,10 +102,10 @@ pub trait CommandExt: Sealed { /// locations might not appear where intended. /// /// [POSIX fork() specification]: - /// https://pubs.opengroup.org/onlinepubs/9699919799/functions/fork.html + /// https://pubs.opengroup.org/onlinepubs/9799919799/functions/fork.html /// [`std::env`]: mod@crate::env - /// [`Error::new`]: crate::io::Error::new - /// [`Error::other`]: crate::io::Error::other + /// [`Error::new`]: ../../../io/struct.Error.html#method.new + /// [`Error::other`]: ../../../io/struct.Error.html#method.other #[stable(feature = "process_pre_exec", since = "1.34.0")] unsafe fn pre_exec(&mut self, f: F) -> &mut process::Command where @@ -190,7 +188,8 @@ pub trait CommandExt: Sealed { /// /// A process group ID of 0 will use the process ID as the PGID. /// - /// ```no_run + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// use std::process::Command; /// use std::os::unix::process::CommandExt; /// @@ -276,38 +275,108 @@ impl CommandExt for process::Command { } } -/// Unix-specific extensions to [`process::ExitStatus`] and -/// [`ExitStatusError`](process::ExitStatusError). +/// Unix-specific extensions to [`ExitStatus`] and [`ExitStatusError`]. /// -/// On Unix, `ExitStatus` **does not necessarily represent an exit status**, as +/// On Unix, [`ExitStatus`] **does not necessarily represent an exit status**, as /// passed to the `_exit` system call or returned by -/// [`ExitStatus::code()`](crate::process::ExitStatus::code). It represents **any wait status** -/// as returned by one of the `wait` family of system +/// [`ExitStatus::code()`](ExitStatus::code). It represents **any wait status** +/// as returned by one of the [`wait`] family of system /// calls. /// -/// A Unix wait status (a Rust `ExitStatus`) can represent a Unix exit status, but can also +/// A Unix wait status (a Rust [`ExitStatus`]) can represent a Unix exit status, but can also /// represent other kinds of process event. /// -/// This trait is sealed: it cannot be implemented outside the standard library. -/// This is so that future additional methods are not breaking changes. +/// [`wait`]: https://pubs.opengroup.org/onlinepubs/9799919799/functions/wait.html #[stable(feature = "rust1", since = "1.0.0")] -pub trait ExitStatusExt: Sealed { - /// Creates a new `ExitStatus` or `ExitStatusError` from the raw underlying integer status - /// value from `wait` +pub impl(self) trait ExitStatusExt { + /// Creates a new [`ExitStatus`] or [`ExitStatusError`] from the raw underlying integer status + /// value from [`wait`]. /// /// The value should be a **wait status, not an exit status**. /// + /// # Example + /// + /// A signal-terminated [`wait`] status carries the signal number, which [`ExitStatus::signal`] + /// recovers using the platform's [`WTERMSIG`][`wait`] macro. Note that the bit layout of a + /// wait status is **not** specified by POSIX and is platform-specific. By convention on most + /// Unix platforms, the signal number occupies the low 7 bits with the exit-code byte left + /// zero, so a bare signal number between 1 and 126 is treated as a signal-terminated wait + /// status. The following example relies on that convention and is therefore not guaranteed to + /// hold on every target: + /// + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] + /// # if cfg!(target_os = "fuchsia") { return; } + /// use std::os::unix::process::ExitStatusExt; + /// use std::process::ExitStatus; + /// + /// let signal = 15; // SIGTERM + /// assert!(signal > 0 && signal < 0x7f, "not a valid Unix termination signal: {signal}"); + /// + /// let status = ExitStatus::from_raw(signal); + /// assert!(!status.success()); + /// assert_eq!(status.code(), None); + /// assert_eq!(status.signal(), Some(15)); + /// ``` + /// + /// Generating an [`ExitStatus`] with a given exit code (0-255) is system-dependent. + /// The value returned by [`ExitStatus::code`] is specified to come from applying the + /// [`WEXITSTATUS`][`wait`] macro, but there is no POSIX-specified constructor and the bit + /// layout is left unspecified. By near-universal convention every Unix libc stores the + /// 8-bit exit code in bits 8..16, so a status built with `(code & 0xff) << 8` will usually + /// round-trip back to the original exit code: + /// + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] + /// # if cfg!(target_os = "fuchsia") { return; } + /// use std::os::unix::process::ExitStatusExt; + /// use std::process::ExitStatus; + /// + /// let code = 41; + /// let status = ExitStatus::from_raw((code & 0xff) << 8); + /// assert_eq!(status.code(), Some(41)); + /// assert!(!status.success()); + /// ``` + /// /// # Panics /// - /// Panics on an attempt to make an `ExitStatusError` from a wait status of `0`. + /// - `ExitStatusError::from_raw` panics on an attempt to make an [`ExitStatusError`] from a + /// [`wait`] status of `0`. + /// - `ExitStatus::from_raw` always succeeds and never panics. /// - /// Making an `ExitStatus` always succeeds and never panics. + /// [`wait`]: https://pubs.opengroup.org/onlinepubs/9799919799/functions/wait.html #[stable(feature = "exit_status_from", since = "1.12.0")] fn from_raw(raw: i32) -> Self; /// If the process was terminated by a signal, returns that signal. /// - /// In other words, if `WIFSIGNALED`, this returns `WTERMSIG`. + /// In other words, if [`WIFSIGNALED`][`wait`], this returns [`WTERMSIG`][`wait`]. For such a status, + /// [`ExitStatus::code`] returns `None`: + /// + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] + /// # if cfg!(target_os = "fuchsia") { return; } + /// use std::os::unix::process::ExitStatusExt; + /// use std::process::ExitStatus; + /// + /// let sigterm = 15; + /// let status = ExitStatus::from_raw(sigterm); + /// assert_eq!(status.code(), None); + /// assert_eq!(status.signal(), Some(sigterm)); + /// ``` + /// + /// A process that receives a signal may catch and handle it, then exit normally with an + /// exit code. When that happens, `signal` returns `None`. + /// + /// Rust does not pass commands through a shell, such as `bash` and `sh`, but it + /// is possible to do so manually. When invoking a shell, the signal value indicates whether + /// the top-level shell itself received a terminating signal. If instead a command *within* + /// an invoked shell receives a terminating signal, many shells convert the signal number + /// into an exit code by adding 128. For example, a command run under `sh` that receives a + /// [`SIGTERM`] canonically causes the shell to report an exit code of `15 + 128`, i.e. `143`. + /// + /// [`SIGTERM`]: https://pubs.opengroup.org/onlinepubs/9799919799/utilities/kill.html + /// [`wait`]: https://pubs.opengroup.org/onlinepubs/9799919799/functions/wait.html #[stable(feature = "rust1", since = "1.0.0")] fn signal(&self) -> Option; @@ -317,21 +386,27 @@ pub trait ExitStatusExt: Sealed { /// If the process was stopped by a signal, returns that signal. /// - /// In other words, if `WIFSTOPPED`, this returns `WSTOPSIG`. This is only possible if the status came from - /// a `wait` system call which was passed `WUNTRACED`, and was then converted into an `ExitStatus`. + /// In other words, if [`WIFSTOPPED`][`wait`], this returns [`WSTOPSIG`][`wait`]. This is only possible if the status came from + /// a [`wait`] system call which was passed [`WUNTRACED`][`wait`], and was then converted into an [`ExitStatus`]. + /// + /// [`wait`]: https://pubs.opengroup.org/onlinepubs/9799919799/functions/wait.html #[stable(feature = "unix_process_wait_more", since = "1.58.0")] fn stopped_signal(&self) -> Option; /// Whether the process was continued from a stopped status. /// - /// Ie, `WIFCONTINUED`. This is only possible if the status came from a `wait` system call - /// which was passed `WCONTINUED`, and was then converted into an `ExitStatus`. + /// I.e. [`WIFCONTINUED`][`wait`]. This is only possible if the status came from a [`wait`] system call + /// which was passed [`WCONTINUED`][`wait`], and was then converted into an [`ExitStatus`]. + /// + /// [`wait`]: https://pubs.opengroup.org/onlinepubs/9799919799/functions/wait.html #[stable(feature = "unix_process_wait_more", since = "1.58.0")] fn continued(&self) -> bool; - /// Returns the underlying raw `wait` status. + /// Returns the underlying raw [`wait`] status. /// /// The returned integer is a **wait status, not an exit status**. + /// + /// [`wait`]: https://pubs.opengroup.org/onlinepubs/9799919799/functions/wait.html #[stable(feature = "unix_process_wait_more", since = "1.58.0")] fn into_raw(self) -> i32; } @@ -393,7 +468,7 @@ impl ExitStatusExt for process::ExitStatusError { } #[unstable(feature = "unix_send_signal", issue = "141975")] -pub trait ChildExt: Sealed { +pub impl(self) trait ChildExt { /// Sends a signal to a child process. /// /// # Errors @@ -404,7 +479,8 @@ pub trait ChildExt: Sealed { /// /// # Examples /// - /// ```rust + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] /// #![feature(unix_send_signal)] /// /// use std::{io, os::unix::process::ChildExt, process::{Command, Stdio}}; @@ -420,6 +496,70 @@ pub trait ChildExt: Sealed { /// } /// ``` fn send_signal(&self, signal: i32) -> io::Result<()>; + + /// Sends a signal to a child process's process group. + /// + /// # Errors + /// + /// This function will return an error if the signal is invalid or if the + /// child process does not have a process group. The integer values + /// associated with signals are implementation-specific, so it's encouraged + /// to use a crate that provides posix bindings. + /// + /// # Examples + /// + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] + /// #![feature(unix_send_signal)] + /// + /// use std::{io, os::unix::process::{ChildExt, CommandExt}, process::{Command, Stdio}}; + /// + /// use libc::SIGTERM; + /// + /// fn main() -> io::Result<()> { + /// # if cfg!(not(all(target_vendor = "apple", not(target_os = "macos")))) { + /// let child = Command::new("cat") + /// .stdin(Stdio::piped()) + /// .process_group(0) + /// .spawn()?; + /// child.send_process_group_signal(SIGTERM)?; + /// # } + /// Ok(()) + /// } + /// ``` + #[unstable(feature = "unix_send_signal", issue = "141975")] + fn send_process_group_signal(&self, signal: i32) -> io::Result<()>; + + /// Forces the child process's process group to exit. + /// + /// This is analogous to [`Child::kill`] but applies to every process in + /// the child process's process group. + /// + /// Use [`CommandExt::process_group`] to assign a child process to an + /// existing process group, or to make it the leader of a new process group. + /// By default spawned processes are in the parent's process group. + /// + /// # Examples + /// + #[cfg_attr(target_family = "unix", doc = "```no_run")] + #[cfg_attr(not(target_family = "unix"), doc = "```ignore (needs unix)")] + /// #![feature(unix_kill_process_group)] + /// + /// use std::{os::unix::process::{ChildExt, CommandExt}, process::{Command, Stdio}}; + /// + /// fn main() -> std::io::Result<()> { + /// let mut child = Command::new("cat") + /// .stdin(Stdio::piped()) + /// .process_group(0) + /// .spawn()?; + /// child.kill_process_group()?; + /// Ok(()) + /// } + /// ``` + /// + /// [`Child::kill`]: process::Child::kill + #[unstable(feature = "unix_kill_process_group", issue = "156537")] + fn kill_process_group(&mut self) -> io::Result<()>; } #[unstable(feature = "unix_send_signal", issue = "141975")] @@ -427,6 +567,23 @@ impl ChildExt for process::Child { fn send_signal(&self, signal: i32) -> io::Result<()> { self.handle.send_signal(signal) } + + fn send_process_group_signal(&self, signal: i32) -> io::Result<()> { + self.handle.send_process_group_signal(signal) + } + + #[cfg(not(target_os = "espidf"))] + fn kill_process_group(&mut self) -> io::Result<()> { + self.handle.send_process_group_signal(libc::SIGKILL) + } + + #[cfg(target_os = "espidf")] + fn kill_process_group(&mut self) -> io::Result<()> { + Err(io::Error::new( + io::ErrorKind::Unsupported, + "process groups are not supported on espidf", + )) + } } #[stable(feature = "process_extensions", since = "1.2.0")] @@ -593,5 +750,5 @@ impl From for process::ChildStderr { #[must_use] #[stable(feature = "unix_ppid", since = "1.27.0")] pub fn parent_id() -> u32 { - crate::sys::os::getppid() + crate::sys::process::getppid() } diff --git a/library/std/src/os/unix/thread.rs b/library/std/src/os/unix/thread.rs index 32085e525942e..c19ccaf742da9 100644 --- a/library/std/src/os/unix/thread.rs +++ b/library/std/src/os/unix/thread.rs @@ -31,10 +31,15 @@ pub trait JoinHandleExt { #[stable(feature = "thread_extensions", since = "1.9.0")] impl JoinHandleExt for JoinHandle { + // This is an int2ptr cast on some platforms (e.g., *-musl) where RawPthread + // is an integer but libc::pthread_t is a pointer. Exposed provenance is the + // safe choice here, but `as` also works when it's int2int or ptr2ptr. + #[allow(implicit_provenance_casts)] fn as_pthread_t(&self) -> RawPthread { self.as_inner().id() as RawPthread } + #[allow(implicit_provenance_casts)] // see above for why fn into_pthread_t(self) -> RawPthread { self.into_inner().into_id() as RawPthread } diff --git a/library/std/src/os/unix/xdg.rs b/library/std/src/os/unix/xdg.rs new file mode 100644 index 0000000000000..b51b8ac916c24 --- /dev/null +++ b/library/std/src/os/unix/xdg.rs @@ -0,0 +1,167 @@ +//! XDG (X Desktop Group) related functionality for Unix platforms. +//! +//! The [XDG Base Directory Specification][basedir] defines a set of base +//! directories, relative to which user-specific files should be looked for. The +//! functions in this module provide those directory paths as configured by +//! the environment. +//! +//! Note that the use of these functions is not enforced by the system, and as +//! such, not all programs will necessarily respect all details of the XDG path +//! environment. This is a set of guidelines, and each program is ultimately +//! responsible for defining where and how it both reads and writes files. +//! +//! Use of XDG paths can be generally considered the conventional expectation +//! on Linux-based systems. Other Unix-based systems may or may not play well +//! with the XDG conventions. +//! +//! Directories returned by this module are not guaranteed to exist yet. If the +//! directory does not exist, an application should attempt to create it with +//! [permissions mode][super::fs::PermissionsExt::from_mode] `0o700`. +//! +//! [basedir]: https://specifications.freedesktop.org/basedir/latest/ +#![unstable(feature = "xdg_basedir", issue = "157515")] + +use crate::env::{home_dir, split_paths, var_os}; +use crate::ffi::{OsStr, OsString}; +use crate::path::PathBuf; + +fn xdg_home_dir() -> PathBuf { + // Note: home_dir can return `Some("")` in some cases. We assume that in + // this case the expected behavior is for `$HOME/path` to become `/path`, + // i.e. the home directory is effectively `/`. + match home_dir() { + None => panic!("an XDG environment should have a home directory"), + Some(home) if home.is_empty() => PathBuf::from("/"), + Some(home) => home, + } +} + +fn xdg_dir(env: &str, fallback_home_subdir: &str) -> PathBuf { + var_os(env) + .filter(|s| !s.is_empty()) + .map(PathBuf::from) + .unwrap_or_else(|| xdg_home_dir().join(fallback_home_subdir)) +} + +/// A base directory relative to which user-specific data files should be written. +/// +/// An application `appid` would typically be expected to write its data files +/// to `{data_home_dir}/{appid}/**/*`. +pub fn data_home_dir() -> PathBuf { + xdg_dir("XDG_DATA_HOME", ".local/share") +} + +/// A base directory relative to which user-specific configuration files should be written. +/// +/// An application `appid` would typically be expected to write its configuration +/// files to `{config_home_dir}/{appid}/**/*`. +pub fn config_home_dir() -> PathBuf { + xdg_dir("XDG_CONFIG_HOME", ".config") +} + +/// A base directory relative to which user-specific state data should be written. +/// +/// An application `appid` would typically be expected to write its state data to +/// `{state_home_dir}/{appid}/**/*`. +/// +/// Common kinds of state data include actions history (such as logs, history, +/// recently used files, etc.) and state of the application that can be reused +/// after application restart (such as view, layout, open files, undo history, +/// etc.). +pub fn state_home_dir() -> PathBuf { + xdg_dir("XDG_STATE_HOME", ".local/state") +} + +/// A base directory relative to which user-specific non-essential (cached) data should be written. +/// +/// An application `appid` would typically be expected to write its cache data to +/// `{cache_home_dir}/{appid}/**/*`. +pub fn cache_home_dir() -> PathBuf { + xdg_dir("XDG_CACHE_HOME", ".cache") +} + +/// An iterator that produces directory paths from XDG environment configuration. +/// +/// The iterator element type is [`PathBuf`]. +/// +/// This structure is created by [`xdg::data_dirs`] and [`xdg::config_dirs`]. +/// See the documentation of those functions for more. +/// +/// [`xdg::data_dirs`]: data_dirs +/// [`xdg::config_dirs`]: config_dirs +#[derive(Debug, Clone)] +pub struct XdgDirsIter { + list: OsString, + off: usize, +} + +impl XdgDirsIter { + fn new(env: &str, default: &str) -> Self { + let dirs = var_os(env).filter(|s| !s.is_empty()).unwrap_or_else(|| default.into()); + Self { list: dirs, off: 0 } + } + + fn remaining(&self) -> Option<&OsStr> { + self.list.as_encoded_bytes().get(self.off..).map(|bytes| { + // SAFETY: `self.off` is the index after a path separator (or the + // start of the string), so is a valid OsStr boundary. + unsafe { OsStr::from_encoded_bytes_unchecked(bytes) } + }) + } +} + +impl Iterator for XdgDirsIter { + type Item = PathBuf; + + fn next(&mut self) -> Option { + let rest = self.remaining()?; + let next = split_paths(rest).next()?; + let len = next.as_os_str().len(); + self.off += len + 1; // Offset after this path and the separator after it. + Some(next) + } + + fn size_hint(&self) -> (usize, Option) { + let Some(dirs) = self.remaining() else { return (0, Some(0)) }; + split_paths(dirs).size_hint() + } +} + +/// A set of preference ordered directories relative to which data files should be searched. +/// +/// If an application defines a data file to be at `$XDG_DATA_DIRS/appid/file.name`, this means that: +/// +/// - The initial data file should be installed to `{system_data_dir}/appid/file.name`. +/// - A user-specific version of the data file may be created at +/// {[data_home_dir][]()}/appid/file.name. +/// - Lookups for the data file should search for `./appid/file.name` relative to +/// `data_home_dir` and each directory in `data_dirs`, giving preference to +/// files found relative to an earlier directory in the search order. +/// +/// An application may choose to handle a file being located under multiple base +/// directories however it sees fit, so long as it respects the search order. +/// For example, it could say that only the first file found is used, or that +/// data within the files is merged in some way. +pub fn data_dirs() -> XdgDirsIter { + // NB: the spec uses trailing slashes only for this default, for some reason + XdgDirsIter::new("XDG_DATA_DIRS", "/usr/local/share/:/usr/share/") +} + +/// A set of preference ordered directories relative to which configuration files should be searched. +/// +/// If an application defines a configuration file to be at `$XDG_CONFIG_DIRS/appid/file.name`, this means that: +/// +/// - The initial configuration file should be installed to `{system_config_dir}/xdg/appid/file.name`. +/// - A user-specific version of the configuration file may be created at +/// {[config_home_dir][]()}/appid/file.name. +/// - Lookups for the configuration file should search for `./appid/file.name` +/// relative to `config_home_dir` and each directory in `config_dirs`, giving +/// preference to files found relative to an earlier directory in the search order. +/// +/// An application may choose to handle a file being located under multiple base +/// directories however it sees fit, so long as it respects the search order. +/// For example, it could say that only the first file found is used, or that +/// data within the files is merged in some way. +pub fn config_dirs() -> XdgDirsIter { + XdgDirsIter::new("XDG_CONFIG_DIRS", "/etc/xdg") +} diff --git a/library/std/src/os/vxworks/fs.rs b/library/std/src/os/vxworks/fs.rs index b88ed19b067a5..a21748ce9fe00 100644 --- a/library/std/src/os/vxworks/fs.rs +++ b/library/std/src/os/vxworks/fs.rs @@ -69,24 +69,54 @@ impl MetadataExt for Metadata { fn st_size(&self) -> u64 { self.as_inner().as_inner().st_size as u64 } + #[cfg(vxworks_lt_25_09)] fn st_atime(&self) -> i64 { self.as_inner().as_inner().st_atime as i64 } + #[cfg(not(vxworks_lt_25_09))] + fn st_atime(&self) -> i64 { + self.as_inner().as_inner().st_atim.tv_sec as i64 + } + #[cfg(vxworks_lt_25_09)] fn st_atime_nsec(&self) -> i64 { 0 } + #[cfg(not(vxworks_lt_25_09))] + fn st_atime_nsec(&self) -> i64 { + self.as_inner().as_inner().st_atim.tv_nsec as i64 + } + #[cfg(vxworks_lt_25_09)] fn st_mtime(&self) -> i64 { self.as_inner().as_inner().st_mtime as i64 } + #[cfg(not(vxworks_lt_25_09))] + fn st_mtime(&self) -> i64 { + self.as_inner().as_inner().st_mtim.tv_sec as i64 + } + #[cfg(vxworks_lt_25_09)] fn st_mtime_nsec(&self) -> i64 { 0 } + #[cfg(not(vxworks_lt_25_09))] + fn st_mtime_nsec(&self) -> i64 { + self.as_inner().as_inner().st_mtim.tv_nsec as i64 + } + #[cfg(vxworks_lt_25_09)] fn st_ctime(&self) -> i64 { self.as_inner().as_inner().st_ctime as i64 } + #[cfg(not(vxworks_lt_25_09))] + fn st_ctime(&self) -> i64 { + self.as_inner().as_inner().st_ctim.tv_sec as i64 + } + #[cfg(vxworks_lt_25_09)] fn st_ctime_nsec(&self) -> i64 { 0 } + #[cfg(not(vxworks_lt_25_09))] + fn st_ctime_nsec(&self) -> i64 { + self.as_inner().as_inner().st_ctim.tv_nsec as i64 + } fn st_blksize(&self) -> u64 { self.as_inner().as_inner().st_blksize as u64 } diff --git a/library/std/src/os/wasi/fs.rs b/library/std/src/os/wasi/fs.rs index 248112cb369dc..369e5d4b0fb9d 100644 --- a/library/std/src/os/wasi/fs.rs +++ b/library/std/src/os/wasi/fs.rs @@ -52,7 +52,7 @@ pub trait FileExt { /// This equivalent to the [`read_at`](FileExt::read_at) method, except that it is passed a /// [`BorrowedCursor`] rather than `&mut [u8]` to allow use with uninitialized buffers. The new /// data will be appended to any existing contents of `buf`. - fn read_buf_at(&self, buf: BorrowedCursor<'_>, offset: u64) -> io::Result<()>; + fn read_buf_at(&self, buf: BorrowedCursor<'_, u8>, offset: u64) -> io::Result<()>; /// Reads the exact number of byte required to fill `buf` from the given offset. /// @@ -228,7 +228,7 @@ impl FileExt for File { self.as_inner().read_at(buf, offset) } - fn read_buf_at(&self, buf: BorrowedCursor<'_>, offset: u64) -> io::Result<()> { + fn read_buf_at(&self, buf: BorrowedCursor<'_, u8>, offset: u64) -> io::Result<()> { self.as_inner().read_buf_at(buf, offset) } @@ -246,13 +246,15 @@ impl FileExt for File { #[cfg(target_env = "p1")] fn fdstat_set_flags(&self, flags: u16) -> io::Result<()> { - unsafe { wasi::fd_fdstat_set_flags(self.as_raw_fd() as wasi::Fd, flags).map_err(err2io) } + unsafe { + wasip1::fd_fdstat_set_flags(self.as_raw_fd() as wasip1::Fd, flags).map_err(err2io) + } } #[cfg(target_env = "p1")] fn fdstat_set_rights(&self, rights: u64, inheriting: u64) -> io::Result<()> { unsafe { - wasi::fd_fdstat_set_rights(self.as_raw_fd() as wasi::Fd, rights, inheriting) + wasip1::fd_fdstat_set_rights(self.as_raw_fd() as wasip1::Fd, rights, inheriting) .map_err(err2io) } } @@ -260,12 +262,12 @@ impl FileExt for File { #[cfg(target_env = "p1")] fn advise(&self, offset: u64, len: u64, advice: u8) -> io::Result<()> { let advice = match advice { - a if a == wasi::ADVICE_NORMAL.raw() => wasi::ADVICE_NORMAL, - a if a == wasi::ADVICE_SEQUENTIAL.raw() => wasi::ADVICE_SEQUENTIAL, - a if a == wasi::ADVICE_RANDOM.raw() => wasi::ADVICE_RANDOM, - a if a == wasi::ADVICE_WILLNEED.raw() => wasi::ADVICE_WILLNEED, - a if a == wasi::ADVICE_DONTNEED.raw() => wasi::ADVICE_DONTNEED, - a if a == wasi::ADVICE_NOREUSE.raw() => wasi::ADVICE_NOREUSE, + a if a == wasip1::ADVICE_NORMAL.raw() => wasip1::ADVICE_NORMAL, + a if a == wasip1::ADVICE_SEQUENTIAL.raw() => wasip1::ADVICE_SEQUENTIAL, + a if a == wasip1::ADVICE_RANDOM.raw() => wasip1::ADVICE_RANDOM, + a if a == wasip1::ADVICE_WILLNEED.raw() => wasip1::ADVICE_WILLNEED, + a if a == wasip1::ADVICE_DONTNEED.raw() => wasip1::ADVICE_DONTNEED, + a if a == wasip1::ADVICE_NOREUSE.raw() => wasip1::ADVICE_NOREUSE, _ => { return Err(io::const_error!( io::ErrorKind::InvalidInput, @@ -275,31 +277,35 @@ impl FileExt for File { }; unsafe { - wasi::fd_advise(self.as_raw_fd() as wasi::Fd, offset, len, advice).map_err(err2io) + wasip1::fd_advise(self.as_raw_fd() as wasip1::Fd, offset, len, advice).map_err(err2io) } } #[cfg(target_env = "p1")] fn allocate(&self, offset: u64, len: u64) -> io::Result<()> { - unsafe { wasi::fd_allocate(self.as_raw_fd() as wasi::Fd, offset, len).map_err(err2io) } + unsafe { wasip1::fd_allocate(self.as_raw_fd() as wasip1::Fd, offset, len).map_err(err2io) } } #[cfg(target_env = "p1")] fn create_directory>(&self, dir: P) -> io::Result<()> { let path = osstr2str(dir.as_ref().as_ref())?; - unsafe { wasi::path_create_directory(self.as_raw_fd() as wasi::Fd, path).map_err(err2io) } + unsafe { + wasip1::path_create_directory(self.as_raw_fd() as wasip1::Fd, path).map_err(err2io) + } } #[cfg(target_env = "p1")] fn remove_file>(&self, path: P) -> io::Result<()> { let path = osstr2str(path.as_ref().as_ref())?; - unsafe { wasi::path_unlink_file(self.as_raw_fd() as wasi::Fd, path).map_err(err2io) } + unsafe { wasip1::path_unlink_file(self.as_raw_fd() as wasip1::Fd, path).map_err(err2io) } } #[cfg(target_env = "p1")] fn remove_directory>(&self, path: P) -> io::Result<()> { let path = osstr2str(path.as_ref().as_ref())?; - unsafe { wasi::path_remove_directory(self.as_raw_fd() as wasi::Fd, path).map_err(err2io) } + unsafe { + wasip1::path_remove_directory(self.as_raw_fd() as wasip1::Fd, path).map_err(err2io) + } } } @@ -388,11 +394,11 @@ pub fn link, U: AsRef>( new_path: U, ) -> io::Result<()> { unsafe { - wasi::path_link( - old_fd.as_raw_fd() as wasi::Fd, + wasip1::path_link( + old_fd.as_raw_fd() as wasip1::Fd, old_flags, osstr2str(old_path.as_ref().as_ref())?, - new_fd.as_raw_fd() as wasi::Fd, + new_fd.as_raw_fd() as wasip1::Fd, osstr2str(new_path.as_ref().as_ref())?, ) .map_err(err2io) @@ -411,10 +417,10 @@ pub fn rename, U: AsRef>( new_path: U, ) -> io::Result<()> { unsafe { - wasi::path_rename( - old_fd.as_raw_fd() as wasi::Fd, + wasip1::path_rename( + old_fd.as_raw_fd() as wasip1::Fd, osstr2str(old_path.as_ref().as_ref())?, - new_fd.as_raw_fd() as wasi::Fd, + new_fd.as_raw_fd() as wasip1::Fd, osstr2str(new_path.as_ref().as_ref())?, ) .map_err(err2io) @@ -432,9 +438,9 @@ pub fn symlink, U: AsRef>( new_path: U, ) -> io::Result<()> { unsafe { - wasi::path_symlink( + wasip1::path_symlink( osstr2str(old_path.as_ref().as_ref())?, - fd.as_raw_fd() as wasi::Fd, + fd.as_raw_fd() as wasip1::Fd, osstr2str(new_path.as_ref().as_ref())?, ) .map_err(err2io) @@ -445,6 +451,7 @@ pub fn symlink, U: AsRef>( /// /// This is a convenience API similar to `std::os::unix::fs::symlink` and /// `std::os::windows::fs::symlink_file` and `std::os::windows::fs::symlink_dir`. +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_symlink_path")] pub fn symlink_path, U: AsRef>(old_path: P, new_path: U) -> io::Result<()> { crate::sys::fs::symlink(old_path.as_ref(), new_path.as_ref()) } diff --git a/library/std/src/os/wasi/io/tests.rs b/library/std/src/os/wasi/io/tests.rs index c5c6a19a6c885..d18b9fe10cab0 100644 --- a/library/std/src/os/wasi/io/tests.rs +++ b/library/std/src/os/wasi/io/tests.rs @@ -2,8 +2,7 @@ use crate::os::wasi::io::RawFd; #[test] fn test_raw_fd_layout() { - // `OwnedFd` and `BorrowedFd` use `rustc_layout_scalar_valid_range_start` - // and `rustc_layout_scalar_valid_range_end`, with values that depend on + // `OwnedFd` and `BorrowedFd` use pattern types with ranges that depend on // the bit width of `RawFd`. If this ever changes, those values will need // to be updated. assert_eq!(size_of::(), 4); diff --git a/library/std/src/os/wasi/mod.rs b/library/std/src/os/wasi/mod.rs index 2ee6aa4660094..1db9ec906726f 100644 --- a/library/std/src/os/wasi/mod.rs +++ b/library/std/src/os/wasi/mod.rs @@ -11,7 +11,8 @@ //! //! # Examples //! -//! ```no_run +#![cfg_attr(target_os = "wasi", doc = "```no_run")] +#![cfg_attr(not(target_os = "wasi"), doc = "```ignore (needs wasi)")] //! use std::fs::File; //! use std::os::wasi::prelude::*; //! diff --git a/library/std/src/os/wasi/net/mod.rs b/library/std/src/os/wasi/net/mod.rs index 9430cd3b05eee..fd5889bf9b7b5 100644 --- a/library/std/src/os/wasi/net/mod.rs +++ b/library/std/src/os/wasi/net/mod.rs @@ -18,6 +18,6 @@ pub trait TcpListenerExt { impl TcpListenerExt for net::TcpListener { fn sock_accept(&self, flags: u16) -> io::Result { - unsafe { wasi::sock_accept(self.as_raw_fd() as wasi::Fd, flags).map_err(err2io) } + unsafe { wasip1::sock_accept(self.as_raw_fd() as wasip1::Fd, flags).map_err(err2io) } } } diff --git a/library/std/src/os/windows/ffi.rs b/library/std/src/os/windows/ffi.rs index fa115385c5d4e..3cda3e25fb544 100644 --- a/library/std/src/os/windows/ffi.rs +++ b/library/std/src/os/windows/ffi.rs @@ -58,16 +58,12 @@ use alloc::wtf8::Wtf8Buf; use crate::ffi::{OsStr, OsString}; use crate::fmt; use crate::iter::FusedIterator; -use crate::sealed::Sealed; use crate::sys::os_str::Buf; use crate::sys::{AsInner, FromInner}; /// Windows-specific extensions to [`OsString`]. -/// -/// This trait is sealed: it cannot be implemented outside the standard library. -/// This is so that future additional methods are not breaking changes. #[stable(feature = "rust1", since = "1.0.0")] -pub trait OsStringExt: Sealed { +pub impl(self) trait OsStringExt { /// Creates an `OsString` from a potentially ill-formed UTF-16 slice of /// 16-bit code units. /// @@ -76,7 +72,8 @@ pub trait OsStringExt: Sealed { /// /// # Examples /// - /// ``` + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// use std::ffi::OsString; /// use std::os::windows::prelude::*; /// @@ -97,11 +94,8 @@ impl OsStringExt for OsString { } /// Windows-specific extensions to [`OsStr`]. -/// -/// This trait is sealed: it cannot be implemented outside the standard library. -/// This is so that future additional methods are not breaking changes. #[stable(feature = "rust1", since = "1.0.0")] -pub trait OsStrExt: Sealed { +pub impl(self) trait OsStrExt { /// Re-encodes an `OsStr` as a wide character sequence, i.e., potentially /// ill-formed UTF-16. /// @@ -111,7 +105,8 @@ pub trait OsStrExt: Sealed { /// /// # Examples /// - /// ``` + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// use std::ffi::OsString; /// use std::os::windows::prelude::*; /// diff --git a/library/std/src/os/windows/fs.rs b/library/std/src/os/windows/fs.rs index 73f3e589e2432..21560638c1d0f 100644 --- a/library/std/src/os/windows/fs.rs +++ b/library/std/src/os/windows/fs.rs @@ -4,11 +4,10 @@ #![stable(feature = "rust1", since = "1.0.0")] -use crate::fs::{self, Metadata, OpenOptions}; +use crate::fs::{self, Metadata, OpenOptions, Permissions}; use crate::io::BorrowedCursor; use crate::path::Path; -use crate::sealed::Sealed; -use crate::sys::{AsInner, AsInnerMut, IntoInner}; +use crate::sys::{AsInner, AsInnerMut, FromInner, IntoInner}; use crate::time::SystemTime; use crate::{io, sys}; @@ -32,7 +31,8 @@ pub trait FileExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// use std::io; /// use std::fs::File; /// use std::os::windows::prelude::*; @@ -60,7 +60,8 @@ pub trait FileExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(core_io_borrowed_buf)] /// #![feature(read_buf_at)] /// @@ -84,7 +85,7 @@ pub trait FileExt { /// } /// ``` #[unstable(feature = "read_buf_at", issue = "140771")] - fn seek_read_buf(&self, buf: BorrowedCursor<'_>, offset: u64) -> io::Result<()> { + fn seek_read_buf(&self, buf: BorrowedCursor<'_, u8>, offset: u64) -> io::Result<()> { io::default_read_buf(|b| self.seek_read(b, offset), buf) } @@ -105,7 +106,8 @@ pub trait FileExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// use std::fs::File; /// use std::os::windows::prelude::*; /// @@ -128,7 +130,7 @@ impl FileExt for fs::File { self.as_inner().read_at(buf, offset) } - fn seek_read_buf(&self, buf: BorrowedCursor<'_>, offset: u64) -> io::Result<()> { + fn seek_read_buf(&self, buf: BorrowedCursor<'_, u8>, offset: u64) -> io::Result<()> { self.as_inner().read_buf_at(buf, offset) } @@ -138,6 +140,8 @@ impl FileExt for fs::File { } /// Windows-specific extensions to [`fs::OpenOptions`]. +// WARNING: This trait is not sealed. DON'T add any new methods! +// Add them to OpenOptionsExt2 instead. #[stable(feature = "open_options_ext", since = "1.10.0")] pub trait OpenOptionsExt { /// Overrides the `dwDesiredAccess` argument to the call to [`CreateFile`] @@ -150,7 +154,8 @@ pub trait OpenOptionsExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// use std::fs::OpenOptions; /// use std::os::windows::prelude::*; /// @@ -175,7 +180,8 @@ pub trait OpenOptionsExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// use std::fs::OpenOptions; /// use std::os::windows::prelude::*; /// @@ -201,7 +207,8 @@ pub trait OpenOptionsExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// # #![allow(unexpected_cfgs)] /// # #[cfg(for_demonstration_only)] /// extern crate winapi; @@ -239,7 +246,8 @@ pub trait OpenOptionsExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// # #![allow(unexpected_cfgs)] /// # #[cfg(for_demonstration_only)] /// extern crate winapi; @@ -278,10 +286,11 @@ pub trait OpenOptionsExt { /// For information about possible values, see [Impersonation Levels] on the /// Windows Dev Center site. The `SECURITY_SQOS_PRESENT` flag is set /// automatically when using this method. - + /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// # #![allow(unexpected_cfgs)] /// # #[cfg(for_demonstration_only)] /// extern crate winapi; @@ -305,18 +314,6 @@ pub trait OpenOptionsExt { /// https://docs.microsoft.com/en-us/windows/win32/api/winnt/ne-winnt-security_impersonation_level #[stable(feature = "open_options_ext", since = "1.10.0")] fn security_qos_flags(&mut self, flags: u32) -> &mut Self; - - /// If set to `true`, prevent the "last access time" of the file from being changed. - /// - /// Default to `false`. - #[unstable(feature = "windows_freeze_file_times", issue = "149715")] - fn freeze_last_access_time(&mut self, freeze: bool) -> &mut Self; - - /// If set to `true`, prevent the "last write time" of the file from being changed. - /// - /// Default to `false`. - #[unstable(feature = "windows_freeze_file_times", issue = "149715")] - fn freeze_last_write_time(&mut self, freeze: bool) -> &mut Self; } #[stable(feature = "open_options_ext", since = "1.10.0")] @@ -345,7 +342,25 @@ impl OpenOptionsExt for OpenOptions { self.as_inner_mut().security_qos_flags(flags); self } +} + +#[unstable(feature = "windows_freeze_file_times", issue = "149715")] +pub impl(self) trait OpenOptionsExt2 { + /// If set to `true`, prevent the "last access time" of the file from being changed. + /// + /// Default to `false`. + #[unstable(feature = "windows_freeze_file_times", issue = "149715")] + fn freeze_last_access_time(&mut self, freeze: bool) -> &mut Self; + + /// If set to `true`, prevent the "last write time" of the file from being changed. + /// + /// Default to `false`. + #[unstable(feature = "windows_freeze_file_times", issue = "149715")] + fn freeze_last_write_time(&mut self, freeze: bool) -> &mut Self; +} +#[unstable(feature = "windows_freeze_file_times", issue = "149715")] +impl OpenOptionsExt2 for OpenOptions { fn freeze_last_access_time(&mut self, freeze: bool) -> &mut Self { self.as_inner_mut().freeze_last_access_time(freeze); self @@ -357,6 +372,66 @@ impl OpenOptionsExt for OpenOptions { } } +/// Windows-specific extensions to [`fs::Permissions`]. This extension trait +/// provides extra utilities to shows what Windows file attributes are enabled +/// in [`Permissions`] and to manually set file attributes on [`Permissions`]. +/// +/// See Microsoft's [`File Attribute Constants`] page to know what file +/// attribute metadata are defined and stored on Windows files. +/// +/// [`Permissions`]: fs::Permissions +/// [`File Attribute Constants`]: +/// https://learn.microsoft.com/en-us/windows/win32/fileio/file-attribute-constants +/// +/// # Example +/// +#[cfg_attr(windows, doc = "```no_run")] +#[cfg_attr(not(windows), doc = "```ignore (needs windows)")] +/// #![feature(windows_permissions_ext)] +/// use std::fs::Permissions; +/// use std::os::windows::fs::PermissionsExt; +/// +/// const FILE_ATTRIBUTE_SYSTEM: u32 = 0x4; +/// const FILE_ATTRIBUTE_ARCHIVE: u32 = 0x20; +/// let my_file_attr = FILE_ATTRIBUTE_SYSTEM | FILE_ATTRIBUTE_ARCHIVE; +/// let mut permissions = Permissions::from_file_attributes(my_file_attr); +/// assert_eq!(permissions.file_attributes(), my_file_attr); +/// +/// const FILE_ATTRIBUTE_HIDDEN: u32 = 0x2; +/// let new_file_attr = permissions.file_attributes() | FILE_ATTRIBUTE_HIDDEN; +/// permissions.set_file_attributes(new_file_attr); +/// assert_eq!(permissions.file_attributes(), new_file_attr); +/// ``` +#[unstable(feature = "windows_permissions_ext", issue = "152956")] +pub impl(self) trait PermissionsExt { + /// Returns the file attribute bits. + #[unstable(feature = "windows_permissions_ext", issue = "152956")] + fn file_attributes(&self) -> u32; + + /// Sets the file attribute bits. + #[unstable(feature = "windows_permissions_ext", issue = "152956")] + fn set_file_attributes(&mut self, mask: u32); + + /// Creates a new instance from the given file attribute bits. + #[unstable(feature = "windows_permissions_ext", issue = "152956")] + fn from_file_attributes(mask: u32) -> Self; +} + +#[unstable(feature = "windows_permissions_ext", issue = "152956")] +impl PermissionsExt for fs::Permissions { + fn file_attributes(&self) -> u32 { + self.as_inner().file_attributes() + } + + fn set_file_attributes(&mut self, mask: u32) { + *self = Permissions::from_inner(FromInner::from_inner(mask)); + } + + fn from_file_attributes(mask: u32) -> Self { + Permissions::from_inner(FromInner::from_inner(mask)) + } +} + /// Windows-specific extensions to [`fs::Metadata`]. /// /// The data members that this trait exposes correspond to the members @@ -374,7 +449,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// use std::io; /// use std::fs; /// use std::os::windows::prelude::*; @@ -404,7 +480,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// use std::io; /// use std::fs; /// use std::os::windows::prelude::*; @@ -439,7 +516,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// use std::io; /// use std::fs; /// use std::os::windows::prelude::*; @@ -472,7 +550,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// use std::io; /// use std::fs; /// use std::os::windows::prelude::*; @@ -495,7 +574,8 @@ pub trait MetadataExt { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// use std::io; /// use std::fs; /// use std::os::windows::prelude::*; @@ -583,7 +663,7 @@ impl MetadataExt for Metadata { /// /// On Windows, a symbolic link knows whether it is a file or directory. #[stable(feature = "windows_file_type_ext", since = "1.64.0")] -pub trait FileTypeExt: Sealed { +pub impl(self) trait FileTypeExt { /// Returns `true` if this file type is a symbolic link that is also a directory. #[stable(feature = "windows_file_type_ext", since = "1.64.0")] fn is_symlink_dir(&self) -> bool; @@ -592,9 +672,6 @@ pub trait FileTypeExt: Sealed { fn is_symlink_file(&self) -> bool; } -#[stable(feature = "windows_file_type_ext", since = "1.64.0")] -impl Sealed for fs::FileType {} - #[stable(feature = "windows_file_type_ext", since = "1.64.0")] impl FileTypeExt for fs::FileType { fn is_symlink_dir(&self) -> bool { @@ -607,7 +684,7 @@ impl FileTypeExt for fs::FileType { /// Windows-specific extensions to [`fs::FileTimes`]. #[stable(feature = "file_set_times", since = "1.75.0")] -pub trait FileTimesExt: Sealed { +pub impl(self) trait FileTimesExt { /// Set the creation time of a file. #[stable(feature = "file_set_times", since = "1.75.0")] fn set_created(self, t: SystemTime) -> Self; @@ -637,7 +714,8 @@ impl FileTimesExt for fs::FileTimes { /// /// # Examples /// -/// ```no_run +#[cfg_attr(windows, doc = "```no_run")] +#[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// use std::os::windows::fs; /// /// fn main() -> std::io::Result<()> { @@ -656,6 +734,7 @@ impl FileTimesExt for fs::FileTimes { /// /// [symlink-security]: https://docs.microsoft.com/en-us/windows/security/threat-protection/security-policy-settings/create-symbolic-links #[stable(feature = "symlink", since = "1.1.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_symlink_file")] pub fn symlink_file, Q: AsRef>(original: P, link: Q) -> io::Result<()> { sys::fs::symlink_inner(original.as_ref(), link.as_ref(), false) } @@ -676,7 +755,8 @@ pub fn symlink_file, Q: AsRef>(original: P, link: Q) -> io: /// /// # Examples /// -/// ```no_run +#[cfg_attr(windows, doc = "```no_run")] +#[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// use std::os::windows::fs; /// /// fn main() -> std::io::Result<()> { @@ -695,6 +775,7 @@ pub fn symlink_file, Q: AsRef>(original: P, link: Q) -> io: /// /// [symlink-security]: https://docs.microsoft.com/en-us/windows/security/threat-protection/security-policy-settings/create-symbolic-links #[stable(feature = "symlink", since = "1.1.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "fs_symlink_dir")] pub fn symlink_dir, Q: AsRef>(original: P, link: Q) -> io::Result<()> { sys::fs::symlink_inner(original.as_ref(), link.as_ref(), true) } diff --git a/library/std/src/os/windows/io/handle.rs b/library/std/src/os/windows/io/handle.rs index 13c0752b560b9..29697bbb5f8fc 100644 --- a/library/std/src/os/windows/io/handle.rs +++ b/library/std/src/os/windows/io/handle.rs @@ -405,9 +405,6 @@ impl fmt::Debug for OwnedHandle { macro_rules! impl_is_terminal { ($($t:ty),*$(,)?) => {$( - #[unstable(feature = "sealed", issue = "none")] - impl crate::sealed::Sealed for $t {} - #[stable(feature = "is_terminal", since = "1.70.0")] impl io::IsTerminal for $t { #[inline] @@ -427,7 +424,8 @@ pub trait AsHandle { /// /// # Example /// - /// ```rust,no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// use std::fs::File; /// # use std::io; /// use std::os::windows::io::{AsHandle, BorrowedHandle}; diff --git a/library/std/src/os/windows/io/mod.rs b/library/std/src/os/windows/io/mod.rs index 3d3ae38788639..bf0605aa08a95 100644 --- a/library/std/src/os/windows/io/mod.rs +++ b/library/std/src/os/windows/io/mod.rs @@ -65,5 +65,115 @@ pub use raw::*; #[stable(feature = "io_safety", since = "1.63.0")] pub use socket::*; +use crate::io::{self, Stderr, StderrLock, Stdin, StdinLock, Stdout, StdoutLock, Write}; +use crate::ptr; +#[cfg(not(doc))] +use crate::sys::c; + #[cfg(test)] mod tests; + +#[unstable(feature = "stdio_swap", issue = "150667", reason = "recently added")] +pub impl(self) trait StdioExt { + /// Sets the stdio console handle to `handle`, or `NULL` if it is `None`. + /// The old handle, if any, will not be closed, i.e. it is leaked because + /// console handles are shared global resources. + /// + /// Rust std::io write buffers (if any) are flushed, but other runtimes + /// (e.g. C stdio) or libraries that acquire a clone of the file handle + /// will not be aware of this change. + /// + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] + /// #![feature(stdio_swap)] + /// use std::io::{self, Read, Write}; + /// use std::os::windows::io::StdioExt; + /// + /// fn main() -> io::Result<()> { + /// let (reader, mut writer) = io::pipe()?; + /// let mut stdin = io::stdin(); + /// stdin.set_handle(Some(reader))?; + /// writer.write_all(b"Hello, world!")?; + /// let mut buffer = vec![0; 13]; + /// assert_eq!(stdin.read(&mut buffer)?, 13); + /// assert_eq!(&buffer, b"Hello, world!"); + /// Ok(()) + /// } + /// ``` + fn set_handle>(&mut self, handle: Option) -> io::Result<()>; + + /// Sets the stdio console handle to `replace_with`. The previous handle is returned, or + /// `None` if it was `NULL`. + /// + /// The returned handle is a `BorrowedHandle<'static>` because console handles are shared global resources + /// and may have been obtained by other functions or threads. + /// Only if you have ensured that no other part of the program has borrowed this handle you can convert it into + /// an `OwnedHandle` and drop that to close it. + /// + /// Like `set_handle()`, Rust std::io write buffers (if any) are flushed. + fn replace_handle>( + &mut self, + replace_with: T, + ) -> io::Result>>; + + /// Sets the stdio console handle to `NULL` and returns the old one + /// + /// See [`set_handle()`] for additional details. + /// + /// [`set_handle()`]: StdioExt::set_handle + fn take_handle(&mut self) -> io::Result>>; +} + +macro io_ext_impl($stdio_ty:ty, $stdio_lock_ty:ty, $handle:path, $writer:literal) { + #[unstable(feature = "stdio_swap", issue = "150667", reason = "recently added")] + impl StdioExt for $stdio_ty { + fn set_handle>(&mut self, handle: Option) -> io::Result<()> { + self.lock().set_handle(handle) + } + + fn replace_handle>( + &mut self, + replace_with: T, + ) -> io::Result>> { + self.lock().replace_handle(replace_with) + } + + fn take_handle(&mut self) -> io::Result>> { + self.lock().take_handle() + } + } + + #[unstable(feature = "stdio_swap", issue = "150667", reason = "recently added")] + impl StdioExt for $stdio_lock_ty { + fn set_handle>(&mut self, handle: Option) -> io::Result<()> { + #[cfg($writer)] + self.flush()?; + let raw = handle.map(|h| h.into().into_raw_handle()).unwrap_or(ptr::null_mut()); + unsafe { c::SetStdHandle($handle, raw) }; + Ok(()) + } + + fn replace_handle>( + &mut self, + replace_with: T, + ) -> io::Result>> { + let old = unsafe { BorrowedHandle::borrow_raw(self.as_raw_handle()) }; + self.set_handle(Some(replace_with))?; + let handle = if old.as_raw_handle().is_null() { None } else { Some(old) }; + Ok(handle) + } + + fn take_handle(&mut self) -> io::Result>> { + let old = unsafe { BorrowedHandle::borrow_raw(self.as_raw_handle()) }; + #[cfg($writer)] + self.flush()?; + unsafe { c::SetStdHandle($handle, ptr::null_mut()) }; + let handle = if old.as_raw_handle().is_null() { None } else { Some(old) }; + Ok(handle) + } + } +} + +io_ext_impl!(Stdout, StdoutLock<'_>, c::STD_OUTPUT_HANDLE, true); +io_ext_impl!(Stdin, StdinLock<'_>, c::STD_INPUT_HANDLE, false); +io_ext_impl!(Stderr, StderrLock<'_>, c::STD_ERROR_HANDLE, true); diff --git a/library/std/src/os/windows/io/raw.rs b/library/std/src/os/windows/io/raw.rs index 0d3f24005f369..d050c28832517 100644 --- a/library/std/src/os/windows/io/raw.rs +++ b/library/std/src/os/windows/io/raw.rs @@ -142,7 +142,7 @@ impl<'a> AsRawHandle for io::StderrLock<'a> { // Translate a handle returned from `GetStdHandle` into a handle to return to // the user. -fn stdio_handle(raw: RawHandle) -> RawHandle { +pub(super) fn stdio_handle(raw: RawHandle) -> RawHandle { // `GetStdHandle` isn't expected to actually fail, so when it returns // `INVALID_HANDLE_VALUE`, it means we were launched from a parent which // didn't provide us with stdio handles, such as a parent with a detached diff --git a/library/std/src/os/windows/io/socket.rs b/library/std/src/os/windows/io/socket.rs index 28e972925e667..ae1b7eaee8d12 100644 --- a/library/std/src/os/windows/io/socket.rs +++ b/library/std/src/os/windows/io/socket.rs @@ -75,7 +75,7 @@ impl OwnedSocket { } // FIXME(strict_provenance_magic): we defined RawSocket to be a u64 ;-; - #[allow(fuzzy_provenance_casts)] + #[allow(implicit_provenance_casts)] #[cfg(not(target_vendor = "uwp"))] pub(crate) fn set_no_inherit(&self) -> io::Result<()> { cvt(unsafe { diff --git a/library/std/src/os/windows/mod.rs b/library/std/src/os/windows/mod.rs index 53c33d17a9f65..a7e032dbf4d4d 100644 --- a/library/std/src/os/windows/mod.rs +++ b/library/std/src/os/windows/mod.rs @@ -8,7 +8,8 @@ //! //! # Examples //! -//! ```no_run +#![cfg_attr(windows, doc = "```no_run")] +#![cfg_attr(not(windows), doc = "```ignore (needs windows)")] //! use std::fs::File; //! use std::os::windows::prelude::*; //! diff --git a/library/std/src/os/windows/net/addr.rs b/library/std/src/os/windows/net/addr.rs index ef2263edcf617..c330432039a8f 100644 --- a/library/std/src/os/windows/net/addr.rs +++ b/library/std/src/os/windows/net/addr.rs @@ -79,7 +79,8 @@ impl SocketAddr { /// /// With a pathname: /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::UnixListener; /// use std::path::Path; @@ -104,7 +105,8 @@ impl SocketAddr { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::SocketAddr; /// use std::path::Path; @@ -118,7 +120,8 @@ impl SocketAddr { /// /// Creating a `SocketAddr` with a NULL byte results in an error. /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::SocketAddr; /// @@ -151,7 +154,8 @@ impl SocketAddr { /// /// A named address: /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::UnixListener; /// diff --git a/library/std/src/os/windows/net/listener.rs b/library/std/src/os/windows/net/listener.rs index 332b116ee1a39..19f5254e08bf9 100644 --- a/library/std/src/os/windows/net/listener.rs +++ b/library/std/src/os/windows/net/listener.rs @@ -12,9 +12,12 @@ use crate::{fmt, io}; /// A structure representing a Unix domain socket server. /// +/// Under Windows, it will only work starting from Windows 10 17063. +/// /// # Examples /// -/// ```no_run +#[cfg_attr(windows, doc = "```no_run")] +#[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::thread; /// use std::os::windows::net::{UnixStream, UnixListener}; @@ -59,7 +62,8 @@ impl UnixListener { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::UnixListener; /// @@ -82,7 +86,8 @@ impl UnixListener { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::{UnixListener}; /// @@ -120,7 +125,8 @@ impl UnixListener { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::UnixListener; /// @@ -146,7 +152,8 @@ impl UnixListener { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::UnixListener; /// @@ -168,7 +175,8 @@ impl UnixListener { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::UnixListener; /// @@ -192,7 +200,8 @@ impl UnixListener { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::UnixListener; /// @@ -210,7 +219,8 @@ impl UnixListener { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::UnixListener; /// @@ -234,7 +244,8 @@ impl UnixListener { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::thread; /// use std::os::windows::net::{UnixStream, UnixListener}; @@ -270,7 +281,8 @@ impl UnixListener { /// /// # Examples /// -/// ```no_run +#[cfg_attr(windows, doc = "```no_run")] +#[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::thread; /// use std::os::windows::net::{UnixStream, UnixListener}; diff --git a/library/std/src/os/windows/net/stream.rs b/library/std/src/os/windows/net/stream.rs index c31f03fdf53f8..c0f32e75411e9 100644 --- a/library/std/src/os/windows/net/stream.rs +++ b/library/std/src/os/windows/net/stream.rs @@ -17,9 +17,12 @@ use crate::time::Duration; use crate::{fmt, io}; /// A Unix stream socket. /// +/// Under Windows, it will only work starting from Windows 10 17063. +/// /// # Examples /// -/// ```no_run +#[cfg_attr(windows, doc = "```no_run")] +#[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::UnixStream; /// use std::io::prelude::*; @@ -52,7 +55,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::UnixStream; /// @@ -75,7 +79,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::{UnixListener, UnixStream}; /// @@ -110,7 +115,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::UnixStream; /// @@ -128,7 +134,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::UnixStream; /// @@ -146,7 +153,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::UnixStream; /// use std::time::Duration; @@ -166,7 +174,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::UnixStream; /// @@ -190,7 +199,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::UnixStream; /// use std::time::Duration; @@ -205,7 +215,8 @@ impl UnixStream { /// An [`Err`] is returned if the zero [`Duration`] is passed to this /// method: /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::io; /// use std::os::windows::net::UnixStream; @@ -233,7 +244,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::UnixStream; /// use std::time::Duration; @@ -249,7 +261,8 @@ impl UnixStream { /// An [`Err`] is returned if the zero [`Duration`] is passed to this /// method: /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::io; /// use std::os::windows::net::UnixStream; @@ -275,7 +288,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::UnixStream; /// use std::net::Shutdown; @@ -294,7 +308,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::UnixStream; /// @@ -319,7 +334,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::UnixStream; /// @@ -337,7 +353,8 @@ impl UnixStream { /// /// # Examples /// - /// ```no_run + #[cfg_attr(windows, doc = "```no_run")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_unix_domain_sockets)] /// use std::os::windows::net::UnixStream; /// use std::time::Duration; diff --git a/library/std/src/os/windows/process.rs b/library/std/src/os/windows/process.rs index b32c6cd442ffa..41dcb70c59c9f 100644 --- a/library/std/src/os/windows/process.rs +++ b/library/std/src/os/windows/process.rs @@ -9,7 +9,6 @@ use crate::mem::MaybeUninit; use crate::os::windows::io::{ AsHandle, AsRawHandle, BorrowedHandle, FromRawHandle, IntoRawHandle, OwnedHandle, RawHandle, }; -use crate::sealed::Sealed; use crate::sys::{AsInner, AsInnerMut, FromInner, IntoInner}; use crate::{io, marker, process, ptr, sys}; @@ -149,11 +148,8 @@ impl From for process::ChildStderr { } /// Windows-specific extensions to [`process::ExitStatus`]. -/// -/// This trait is sealed: it cannot be implemented outside the standard library. -/// This is so that future additional methods are not breaking changes. #[stable(feature = "exit_status_from", since = "1.12.0")] -pub trait ExitStatusExt: Sealed { +pub impl(self) trait ExitStatusExt { /// Creates a new `ExitStatus` from the raw underlying `u32` return value of /// a process. #[stable(feature = "exit_status_from", since = "1.12.0")] @@ -168,11 +164,8 @@ impl ExitStatusExt for process::ExitStatus { } /// Windows-specific extensions to the [`process::Command`] builder. -/// -/// This trait is sealed: it cannot be implemented outside the standard library. -/// This is so that future additional methods are not breaking changes. #[stable(feature = "windows_process_extensions", since = "1.16.0")] -pub trait CommandExt: Sealed { +pub impl(self) trait CommandExt { /// Sets the [process creation flags][1] to be passed to `CreateProcess`. /// /// These will always be ORed with `CREATE_UNICODE_ENVIRONMENT`. @@ -280,7 +273,8 @@ pub trait CommandExt: Sealed { /// /// # Example /// - /// ``` + #[cfg_attr(windows, doc = "```")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_process_extensions_async_pipes)] /// use std::os::windows::process::CommandExt; /// use std::process::{Command, Stdio}; @@ -311,7 +305,8 @@ pub trait CommandExt: Sealed { /// /// # Example /// - /// ``` + #[cfg_attr(windows, doc = "```")] + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] /// #![feature(windows_process_extensions_raw_attribute)] /// use std::os::windows::io::AsRawHandle; /// use std::os::windows::process::{CommandExt, ProcThreadAttributeList}; @@ -443,7 +438,7 @@ impl CommandExt for process::Command { } #[unstable(feature = "windows_process_extensions_main_thread_handle", issue = "96723")] -pub trait ChildExt: Sealed { +pub impl(self) trait ChildExt { /// Extracts the main thread raw handle, without taking ownership #[unstable(feature = "windows_process_extensions_main_thread_handle", issue = "96723")] fn main_thread_handle(&self) -> BorrowedHandle<'_>; @@ -457,11 +452,8 @@ impl ChildExt for process::Child { } /// Windows-specific extensions to [`process::ExitCode`]. -/// -/// This trait is sealed: it cannot be implemented outside the standard library. -/// This is so that future additional methods are not breaking changes. #[unstable(feature = "windows_process_exit_code_from", issue = "111688")] -pub trait ExitCodeExt: Sealed { +pub impl(self) trait ExitCodeExt { /// Creates a new `ExitCode` from the raw underlying `u32` return value of /// a process. /// @@ -573,7 +565,9 @@ impl<'a> ProcThreadAttributeListBuilder<'a> { /// /// # Example /// - /// ``` + #[cfg_attr(not(windows), doc = "```ignore (needs windows)")] + #[cfg_attr(all(windows, target_vendor = "win7"), doc = "```no_run")] + #[cfg_attr(all(windows, not(target_vendor = "win7")), doc = "```")] /// #![feature(windows_process_extensions_raw_attribute)] /// use std::ffi::c_void; /// use std::os::windows::process::{CommandExt, ProcThreadAttributeList}; diff --git a/library/std/src/os/xous/ffi.rs b/library/std/src/os/xous/ffi.rs index 9394f0a0496b2..8a499446e98d0 100644 --- a/library/std/src/os/xous/ffi.rs +++ b/library/std/src/os/xous/ffi.rs @@ -24,7 +24,7 @@ fn lend_mut_impl( let mut a1: usize = connection.try_into().unwrap(); let mut a2 = InvokeType::LendMut as usize; let a3 = opcode; - let a4 = data.as_mut_ptr() as usize; + let a4 = data.as_mut_ptr(); let a5 = data.len(); let a6 = arg1; let a7 = arg2; @@ -86,7 +86,7 @@ fn lend_impl( let a1: usize = connection.try_into().unwrap(); let a2 = InvokeType::Lend as usize; let a3 = opcode; - let a4 = data.as_ptr() as usize; + let a4 = data.as_ptr(); let a5 = data.len(); let a6 = arg1; let a7 = arg2; @@ -359,15 +359,19 @@ pub(crate) fn do_yield() { /// This function is safe unless a virtual address is specified. In that case, /// the kernel will return an alias to the existing range. This violates Rust's /// pointer uniqueness guarantee. +// The phys argument uses an integer rather than pointer type as pointer +// provenance only covers virtual memory, not physical memory. pub(crate) unsafe fn map_memory( - phys: Option>, + phys: Option, virt: Option>, count: usize, flags: MemoryFlags, ) -> Result<&'static mut [T], Error> { let mut a0 = Syscall::MapMemory as usize; - let mut a1 = phys.map(|p| p.as_ptr() as usize).unwrap_or_default(); - let mut a2 = virt.map(|p| p.as_ptr() as usize).unwrap_or_default(); + let a1 = phys.map_or(0, |p| p.get()); + let a1_out: *mut T; + let a2 = virt.map_or(core::ptr::null(), |p| p.as_ptr()); + let a2_out: usize; let a3 = count * size_of::(); let a4 = flags.bits(); let a5 = 0; @@ -378,8 +382,8 @@ pub(crate) unsafe fn map_memory( core::arch::asm!( "ecall", inlateout("a0") a0, - inlateout("a1") a1, - inlateout("a2") a2, + inlateout("a1") a1 => a1_out, + inlateout("a2") a2 => a2_out, inlateout("a3") a3 => _, inlateout("a4") a4 => _, inlateout("a5") a5 => _, @@ -391,12 +395,12 @@ pub(crate) unsafe fn map_memory( let result = a0; if result == SyscallResult::MemoryRange as usize { - let start = core::ptr::with_exposed_provenance_mut::(a1); - let len = a2 / size_of::(); + let start = a1_out; + let len = a2_out / size_of::(); let end = unsafe { start.add(len) }; Ok(unsafe { core::slice::from_raw_parts_mut(start, len) }) } else if result == SyscallResult::Error as usize { - Err(a1.into()) + Err(a1_out.addr().into()) } else { Err(Error::InternalError) } @@ -408,7 +412,7 @@ pub(crate) unsafe fn map_memory( /// function returns, even if this function returns Err(). pub(crate) unsafe fn unmap_memory(range: *mut [T]) -> Result<(), Error> { let mut a0 = Syscall::UnmapMemory as usize; - let mut a1 = range.as_mut_ptr() as usize; + let mut a1 = range.as_mut_ptr(); let a2 = range.len() * size_of::(); let a3 = 0; let a4 = 0; @@ -435,7 +439,7 @@ pub(crate) unsafe fn unmap_memory(range: *mut [T]) -> Result<(), Error> { if result == SyscallResult::Ok as usize { Ok(()) } else if result == SyscallResult::Error as usize { - Err(a1.into()) + Err(a1.addr().into()) } else { Err(Error::InternalError) } @@ -454,7 +458,8 @@ pub(crate) unsafe fn update_memory_flags( new_flags: MemoryFlags, ) -> Result<(), Error> { let mut a0 = Syscall::UpdateMemoryFlags as usize; - let mut a1 = range.as_mut_ptr() as usize; + let a1 = range.as_mut_ptr(); + let a1_out: usize; let a2 = range.len() * size_of::(); let a3 = new_flags.bits(); let a4 = 0; // Process ID is currently None @@ -466,7 +471,7 @@ pub(crate) unsafe fn update_memory_flags( core::arch::asm!( "ecall", inlateout("a0") a0, - inlateout("a1") a1, + inlateout("a1") a1 => a1_out, inlateout("a2") a2 => _, inlateout("a3") a3 => _, inlateout("a4") a4 => _, @@ -481,24 +486,25 @@ pub(crate) unsafe fn update_memory_flags( if result == SyscallResult::Ok as usize { Ok(()) } else if result == SyscallResult::Error as usize { - Err(a1.into()) + Err(a1_out.into()) } else { Err(Error::InternalError) } } /// Creates a thread with a given stack and up to four arguments. -pub(crate) fn create_thread( - start: *mut usize, +pub(crate) unsafe fn create_thread( + start: unsafe extern "C" fn(*mut usize, usize, usize) -> !, stack: *mut [u8], - arg0: usize, - arg1: usize, + arg0: *mut T, + arg1: *const u8, arg2: usize, arg3: usize, ) -> Result { let mut a0 = Syscall::CreateThread as usize; - let mut a1 = start as usize; - let a2 = stack.as_mut_ptr() as usize; + let a1 = start; + let a1_out: usize; + let a2 = stack.as_mut_ptr(); let a3 = stack.len(); let a4 = arg0; let a5 = arg1; @@ -509,7 +515,7 @@ pub(crate) fn create_thread( core::arch::asm!( "ecall", inlateout("a0") a0, - inlateout("a1") a1, + inlateout("a1") a1 => a1_out, inlateout("a2") a2 => _, inlateout("a3") a3 => _, inlateout("a4") a4 => _, @@ -522,9 +528,9 @@ pub(crate) fn create_thread( let result = a0; if result == SyscallResult::ThreadId as usize { - Ok(a1.into()) + Ok(a1_out.into()) } else if result == SyscallResult::Error as usize { - Err(a1.into()) + Err(a1_out.into()) } else { Err(Error::InternalError) } diff --git a/library/std/src/panic.rs b/library/std/src/panic.rs index 658026a8020f9..a07a5fb6290ca 100644 --- a/library/std/src/panic.rs +++ b/library/std/src/panic.rs @@ -41,7 +41,7 @@ pub type PanicInfo<'a> = PanicHookInfo<'a>; #[derive(Debug)] pub struct PanicHookInfo<'a> { payload: &'a (dyn Any + Send), - location: &'a Location<'a>, + location: &'static Location<'static>, can_unwind: bool, force_no_backtrace: bool, } @@ -49,7 +49,7 @@ pub struct PanicHookInfo<'a> { impl<'a> PanicHookInfo<'a> { #[inline] pub(crate) fn new( - location: &'a Location<'a>, + location: &'static Location<'static>, payload: &'a (dyn Any + Send), can_unwind: bool, force_no_backtrace: bool, @@ -160,10 +160,10 @@ impl<'a> PanicHookInfo<'a> { #[must_use] #[inline] #[stable(feature = "panic_hooks", since = "1.10.0")] - pub fn location(&self) -> Option<&Location<'_>> { + pub fn location(&self) -> Option<&'static Location<'static>> { // NOTE: If this is changed to sometimes return None, // deal with that case in std::panicking::default_hook and core::panicking::panic_fmt. - Some(&self.location) + Some(self.location) } /// Returns whether the panic handler is allowed to unwind the stack from @@ -285,7 +285,7 @@ where } #[unstable(feature = "abort_unwind", issue = "130338")] -pub use core::panic::abort_unwind; +pub use core::panic::abort_on_unwind; /// Invokes a closure, capturing the cause of an unwinding panic if one occurs. /// diff --git a/library/std/src/panicking.rs b/library/std/src/panicking.rs index a4a974d0447b8..7db6e93e8bd02 100644 --- a/library/std/src/panicking.rs +++ b/library/std/src/panicking.rs @@ -415,6 +415,7 @@ pub mod panic_count { // // This also updates thread-local state to keep track of whether a panic // hook is currently executing. + #[must_use = "MustAbort may not be ignored"] pub fn increase(run_panic_hook: bool) -> Option { let global_count = GLOBAL_PANIC_COUNT.fetch_add(1, Ordering::Relaxed); if global_count & ALWAYS_ABORT_FLAG != 0 { @@ -530,7 +531,6 @@ pub unsafe fn catch_unwind R>(f: F) -> Result R>(f: F) -> Result, data_ptr, do_catch::) == 0 { - Ok(ManuallyDrop::into_inner(data.r)) - } else { + return if intrinsics::catch_unwind(do_call, &raw mut data, do_catch) { Err(ManuallyDrop::into_inner(data.p)) + } else { + Ok(ManuallyDrop::into_inner(data.r)) }; } @@ -568,17 +568,12 @@ pub unsafe fn catch_unwind R>(f: F) -> Result` // Its must contains a valid `f` (type: F) value that can be use to fill // `data.r`. - // - // This function cannot be marked as `unsafe` because `intrinsics::catch_unwind` - // expects normal function pointers. #[inline] - fn do_call R, R>(data: *mut u8) { + unsafe fn do_call R, R>(data: *mut Data) { // SAFETY: this is the responsibility of the caller, see above. unsafe { - let data = data as *mut Data; - let data = &mut (*data); - let f = ManuallyDrop::take(&mut data.f); - data.r = ManuallyDrop::new(f()); + let f = ManuallyDrop::take(&mut (*data).f); + (*data).r = ManuallyDrop::new(f()); } } @@ -590,22 +585,17 @@ pub unsafe fn catch_unwind R>(f: F) -> Result` // Since this uses `cleanup` it also hinges on a correct implementation of // `__rustc_panic_cleanup`. - // - // This function cannot be marked as `unsafe` because `intrinsics::catch_unwind` - // expects normal function pointers. #[inline] #[rustc_nounwind] // `intrinsic::catch_unwind` requires catch fn to be nounwind - fn do_catch R, R>(data: *mut u8, payload: *mut u8) { + unsafe fn do_catch R, R>(data: *mut Data, payload: *mut u8) { // SAFETY: this is the responsibility of the caller, see above. // // When `__rustc_panic_cleaner` is correctly implemented we can rely // on `obj` being the correct thing to pass to `data.p` (after wrapping // in `ManuallyDrop`). unsafe { - let data = data as *mut Data; - let data = &mut (*data); let obj = cleanup(payload); - data.p = ManuallyDrop::new(obj); + (*data).p = ManuallyDrop::new(obj); } } } @@ -786,7 +776,7 @@ fn payload_as_str(payload: &dyn Any) -> &str { #[optimize(size)] fn panic_with_hook( payload: &mut dyn PanicPayload, - location: &Location<'_>, + location: &'static Location<'static>, can_unwind: bool, force_no_backtrace: bool, ) -> ! { @@ -854,7 +844,18 @@ fn panic_with_hook( /// It just forwards the payload to the panic runtime. #[cfg_attr(panic = "immediate-abort", inline)] pub fn resume_unwind(payload: Box) -> ! { - panic_count::increase(false); + if let Some(must_abort) = panic_count::increase(false) { + match must_abort { + panic_count::MustAbort::PanicInHook => { + rtprintpanic!("thread panicked while processing panic. aborting.\n"); + } + panic_count::MustAbort::AlwaysAbort => { + rtprintpanic!("aborting due to panic\n"); + } + } + + crate::process::abort(); + } struct RewrapBox(Box); diff --git a/library/std/src/path.rs b/library/std/src/path.rs index 25bd7005b9942..8b41a3792ac9a 100644 --- a/library/std/src/path.rs +++ b/library/std/src/path.rs @@ -19,6 +19,20 @@ //! matter the platform or filesystem. An exception to this is made for Windows //! drive letters. //! +//! ## Path normalization +//! +//! Several methods in this module perform basic path normalization by disregarding +//! repeated separators, non-leading `.` components, and trailing separators. These include: +//! - Methods for iteration, such as [`Path::components`] and [`Path::iter`] +//! - Methods for inspection, such as [`Path::has_root`] +//! - Comparisons using [`PartialEq`], [`PartialOrd`], and [`Ord`] +//! +//! [`Path::join`] and [`PathBuf::push`] also disregard trailing slashes. +//! +// FIXME(normalize_lexically): mention normalize_lexically once stable +//! These methods **do not** resolve `..` components or symlinks. For full normalization +//! including `..` resolution, use [`Path::canonicalize`] (which does access the filesystem). +//! //! ## Simple usage //! //! Path manipulation includes both parsing components from slices and building @@ -79,7 +93,7 @@ use crate::ops::{self, Deref}; use crate::rc::Rc; use crate::str::FromStr; use crate::sync::Arc; -use crate::sys::path::{HAS_PREFIXES, MAIN_SEP_STR, is_sep_byte, is_verbatim_sep, parse_prefix}; +use crate::sys::path::{HAS_PREFIXES, is_sep_byte, is_verbatim_sep, parse_prefix}; use crate::{cmp, fmt, fs, io, sys}; //////////////////////////////////////////////////////////////////////////////// @@ -252,22 +266,33 @@ impl<'a> Prefix<'a> { /// ``` #[must_use] #[stable(feature = "rust1", since = "1.0.0")] -pub fn is_separator(c: char) -> bool { +#[rustc_const_unstable(feature = "const_path_separators", issue = "153106")] +pub const fn is_separator(c: char) -> bool { c.is_ascii() && is_sep_byte(c as u8) } -/// The primary separator of path components for the current platform. -/// -/// For example, `/` on Unix and `\` on Windows. +/// All path separators recognized on the current platform, represented as [`char`]s; for example, +/// this is `&['/'][..]` on Unix and `&['\\', '/'][..]` on Windows. The [primary +/// separator](MAIN_SEPARATOR) is always element 0 of the slice. +#[unstable(feature = "const_path_separators", issue = "153106")] +pub const SEPARATORS: &[char] = crate::sys::path::SEPARATORS; + +/// All path separators recognized on the current platform, represented as [`&str`]s; for example, +/// this is `&["/"][..]` on Unix and `&["\\", "/"][..]` on Windows. The [primary +/// separator](MAIN_SEPARATOR_STR) is always element 0 of the slice. +#[unstable(feature = "const_path_separators", issue = "153106")] +pub const SEPARATORS_STR: &[&str] = crate::sys::path::SEPARATORS_STR; + +/// The primary separator of path components for the current platform, represented as a [`char`]; +/// for example, this is `'/'` on Unix and `'\\'` on Windows. #[stable(feature = "rust1", since = "1.0.0")] #[cfg_attr(not(test), rustc_diagnostic_item = "path_main_separator")] -pub const MAIN_SEPARATOR: char = crate::sys::path::MAIN_SEP; +pub const MAIN_SEPARATOR: char = SEPARATORS[0]; -/// The primary separator of path components for the current platform. -/// -/// For example, `/` on Unix and `\` on Windows. +/// The primary separator of path components for the current platform, represented as a [`&str`]; +/// for example, this is `"/"` on Unix and `"\\"` on Windows. #[stable(feature = "main_separator_str", since = "1.68.0")] -pub const MAIN_SEPARATOR_STR: &str = crate::sys::path::MAIN_SEP_STR; +pub const MAIN_SEPARATOR_STR: &str = SEPARATORS_STR[0]; //////////////////////////////////////////////////////////////////////////////// // Misc helpers @@ -548,7 +573,7 @@ impl<'a> Component<'a> { pub fn as_os_str(self) -> &'a OsStr { match self { Component::Prefix(p) => p.as_os_str(), - Component::RootDir => OsStr::new(MAIN_SEP_STR), + Component::RootDir => OsStr::new(MAIN_SEPARATOR_STR), Component::CurDir => OsStr::new("."), Component::ParentDir => OsStr::new(".."), Component::Normal(path) => path, @@ -1339,7 +1364,7 @@ impl PathBuf { // absolute `path` replaces `self` if need_clear { - self.inner.truncate(0); + self.inner.clear(); // verbatim paths need . and .. removed } else if comps.prefix_verbatim() && !path.inner.is_empty() { @@ -1365,7 +1390,7 @@ impl PathBuf { for c in buf { if need_sep && c != Component::RootDir { - res.push(MAIN_SEP_STR); + res.push(MAIN_SEPARATOR_STR); } res.push(c.as_os_str()); @@ -1388,7 +1413,7 @@ impl PathBuf { // `path` is a pure relative path } else if need_sep { - self.inner.push(MAIN_SEP_STR); + self.inner.push(MAIN_SEPARATOR_STR); } self.inner.push(path); @@ -1771,6 +1796,24 @@ impl PathBuf { self.inner } + /// Converts the `PathBuf` into a `String` if it contains valid Unicode data. + /// + /// On failure, ownership of the original `PathBuf` is returned. + /// + /// # Examples + /// + /// ``` + /// use std::path::PathBuf; + /// + /// let path_buf = PathBuf::from("foo"); + /// let string = path_buf.into_string(); + /// assert_eq!(string, Ok(String::from("foo"))); + /// ``` + #[stable(feature = "pathbuf_into_string", since = "1.98.0")] + pub fn into_string(self) -> Result { + self.into_os_string().into_string().map_err(PathBuf::from) + } + /// Converts this `PathBuf` into a [boxed](Box) [`Path`]. #[stable(feature = "into_boxed_path", since = "1.20.0")] #[must_use = "`self` will be dropped if the result is not used"] @@ -2630,7 +2673,7 @@ impl Path { #[stable(feature = "path_ancestors", since = "1.28.0")] #[inline] pub fn ancestors(&self) -> Ancestors<'_> { - Ancestors { next: Some(&self) } + Ancestors { next: Some(self) } } /// Returns the final component of the `Path`, if there is one. @@ -2700,6 +2743,41 @@ impl Path { self._strip_prefix(base.as_ref()) } + /// Returns a path with the optional prefix removed. + /// + /// If `base` is not a prefix of `self` (i.e., [`starts_with`] returns `false`), returns the original path (`self`) + /// + /// [`starts_with`]: Path::starts_with + /// + /// # Examples + /// + /// ``` + /// #![feature(trim_prefix_suffix)] + /// use std::path::Path; + /// + /// let path = Path::new("/test/haha/foo.txt"); + /// + /// // Prefix present - remove it + /// assert_eq!(path.trim_prefix("/"), Path::new("test/haha/foo.txt")); + /// assert_eq!(path.trim_prefix("/test"), Path::new("haha/foo.txt")); + /// assert_eq!(path.trim_prefix("/test/"), Path::new("haha/foo.txt")); + /// assert_eq!(path.trim_prefix("/test/haha/foo.txt"), Path::new("")); + /// assert_eq!(path.trim_prefix("/test/haha/foo.txt/"), Path::new("")); + /// + /// // Prefix absent - return original + /// assert_eq!(path.trim_prefix("test"), path); + /// assert_eq!(path.trim_prefix("/te"), path); + /// assert_eq!(path.trim_prefix("/haha"), path); + /// ``` + #[must_use = "this returns the remaining path as a new path, without modifying the original"] + #[unstable(feature = "trim_prefix_suffix", issue = "142312")] + pub fn trim_prefix

(&self, base: P) -> &Path + where + P: AsRef, + { + self._strip_prefix(base.as_ref()).unwrap_or(self) + } + fn _strip_prefix(&self, base: &Path) -> Result<&Path, StripPrefixError> { iter_after(self.components(), base.components()) .map(|c| c.as_path()) @@ -2768,10 +2846,13 @@ impl Path { /// Checks whether the `Path` is empty. /// + /// Passing an empty path to most OS filesystem APIs will always result in an error. + /// + /// [Pushing][PathBuf::push] an empty path to an existing path will append a directory separator unless it already ends with a separator or the existing path is itself empty. + /// /// # Examples /// /// ``` - /// #![feature(path_is_empty)] /// use std::path::Path; /// /// let path = Path::new(""); @@ -2783,7 +2864,7 @@ impl Path { /// let path = Path::new("."); /// assert!(!path.is_empty()); /// ``` - #[unstable(feature = "path_is_empty", issue = "148494")] + #[stable(feature = "path_is_empty", since = "1.98.0")] pub fn is_empty(&self) -> bool { self.as_os_str().is_empty() } @@ -3095,7 +3176,9 @@ impl Path { /// Creates an owned [`PathBuf`] like `self` but with the extension added. /// - /// See [`PathBuf::add_extension`] for more details. + /// See [`PathBuf::add_extension`] for more details. The return value of + /// [`PathBuf::add_extension`] is ignored, which means no extension + /// will be added to paths with no [`Path::file_name`]. /// /// # Examples /// @@ -3109,6 +3192,13 @@ impl Path { /// assert_eq!(path.with_added_extension(""), PathBuf::from("foo.tar.gz")); /// assert_eq!(path.with_added_extension("xz"), PathBuf::from("foo.tar.gz.xz")); /// assert_eq!(path.with_added_extension("").with_added_extension("txt"), PathBuf::from("foo.tar.gz.txt")); + /// + /// let path = Path::new("/"); + /// assert_eq!(path.with_added_extension("gz"), PathBuf::from("/")); + /// let path = Path::new("/dir/"); + /// assert_eq!(path.with_added_extension("gz"), PathBuf::from("/dir.gz")); + /// let path = Path::new("/dir/.."); + /// assert_eq!(path.with_added_extension("gz"), PathBuf::from("/dir/..")); /// ``` #[stable(feature = "path_add_extension", since = "1.91.0")] pub fn with_added_extension>(&self, extension: S) -> PathBuf { @@ -3294,6 +3384,34 @@ impl Path { fs::canonicalize(self) } + /// Makes the path absolute without accessing the filesystem. + /// + /// This is an alias to [`path::absolute`](absolute). + /// + /// # Errors + /// + /// This function may return an error in the following situations: + /// + /// * If the path is syntactically invalid; in particular, if it is empty. + /// * If getting the [current directory][crate::env::current_dir] fails. + /// + /// # Examples + /// + /// ```no_run + /// #![feature(path_absolute_method)] + /// use std::path::Path; + /// + /// let path = Path::new("foo/./bar"); + /// let absolute = path.absolute()?; + /// assert!(absolute.is_absolute()); + /// # Ok::<(), std::io::Error>(()) + /// ``` + #[unstable(feature = "path_absolute_method", issue = "153328")] + #[inline] + pub fn absolute(&self) -> io::Result { + absolute(self) + } + /// Normalize a path, including `..` without traversing the filesystem. /// /// Returns an error if normalization would leave leading `..` components. @@ -3579,7 +3697,7 @@ unsafe impl CloneToUninit for Path { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef for Path { +const impl AsRef for Path { #[inline] fn as_ref(&self) -> &OsStr { &self.inner @@ -3750,7 +3868,7 @@ impl Ord for Path { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef for Path { +const impl AsRef for Path { #[inline] fn as_ref(&self) -> &Path { self @@ -3759,7 +3877,7 @@ impl const AsRef for Path { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef for OsStr { +const impl AsRef for OsStr { #[inline] fn as_ref(&self) -> &Path { Path::new(self) @@ -3827,9 +3945,9 @@ impl<'a> IntoIterator for &'a Path { } macro_rules! impl_cmp { - (<$($life:lifetime),*> $lhs:ty, $rhs: ty) => { + ($lhs:ty, $rhs: ty) => { #[stable(feature = "partialeq_path", since = "1.6.0")] - impl<$($life),*> PartialEq<$rhs> for $lhs { + impl PartialEq<$rhs> for $lhs { #[inline] fn eq(&self, other: &$rhs) -> bool { ::eq(self, other) @@ -3837,7 +3955,7 @@ macro_rules! impl_cmp { } #[stable(feature = "partialeq_path", since = "1.6.0")] - impl<$($life),*> PartialEq<$lhs> for $rhs { + impl PartialEq<$lhs> for $rhs { #[inline] fn eq(&self, other: &$lhs) -> bool { ::eq(self, other) @@ -3845,7 +3963,7 @@ macro_rules! impl_cmp { } #[stable(feature = "cmp_path", since = "1.8.0")] - impl<$($life),*> PartialOrd<$rhs> for $lhs { + impl PartialOrd<$rhs> for $lhs { #[inline] fn partial_cmp(&self, other: &$rhs) -> Option { ::partial_cmp(self, other) @@ -3853,7 +3971,7 @@ macro_rules! impl_cmp { } #[stable(feature = "cmp_path", since = "1.8.0")] - impl<$($life),*> PartialOrd<$lhs> for $rhs { + impl PartialOrd<$lhs> for $rhs { #[inline] fn partial_cmp(&self, other: &$lhs) -> Option { ::partial_cmp(self, other) @@ -3862,16 +3980,16 @@ macro_rules! impl_cmp { }; } -impl_cmp!(<> PathBuf, Path); -impl_cmp!(<'a> PathBuf, &'a Path); -impl_cmp!(<'a> Cow<'a, Path>, Path); -impl_cmp!(<'a, 'b> Cow<'a, Path>, &'b Path); -impl_cmp!(<'a> Cow<'a, Path>, PathBuf); +impl_cmp!(PathBuf, Path); +impl_cmp!(PathBuf, &Path); +impl_cmp!(Cow<'_, Path>, Path); +impl_cmp!(Cow<'_, Path>, &Path); +impl_cmp!(Cow<'_, Path>, PathBuf); macro_rules! impl_cmp_os_str { - (<$($life:lifetime),*> $lhs:ty, $rhs: ty) => { + ($lhs:ty, $rhs: ty) => { #[stable(feature = "cmp_path", since = "1.8.0")] - impl<$($life),*> PartialEq<$rhs> for $lhs { + impl PartialEq<$rhs> for $lhs { #[inline] fn eq(&self, other: &$rhs) -> bool { ::eq(self, other.as_ref()) @@ -3879,7 +3997,7 @@ macro_rules! impl_cmp_os_str { } #[stable(feature = "cmp_path", since = "1.8.0")] - impl<$($life),*> PartialEq<$lhs> for $rhs { + impl PartialEq<$lhs> for $rhs { #[inline] fn eq(&self, other: &$lhs) -> bool { ::eq(self.as_ref(), other) @@ -3887,7 +4005,7 @@ macro_rules! impl_cmp_os_str { } #[stable(feature = "cmp_path", since = "1.8.0")] - impl<$($life),*> PartialOrd<$rhs> for $lhs { + impl PartialOrd<$rhs> for $lhs { #[inline] fn partial_cmp(&self, other: &$rhs) -> Option { ::partial_cmp(self, other.as_ref()) @@ -3895,7 +4013,7 @@ macro_rules! impl_cmp_os_str { } #[stable(feature = "cmp_path", since = "1.8.0")] - impl<$($life),*> PartialOrd<$lhs> for $rhs { + impl PartialOrd<$lhs> for $rhs { #[inline] fn partial_cmp(&self, other: &$lhs) -> Option { ::partial_cmp(self.as_ref(), other) @@ -3904,20 +4022,20 @@ macro_rules! impl_cmp_os_str { }; } -impl_cmp_os_str!(<> PathBuf, OsStr); -impl_cmp_os_str!(<'a> PathBuf, &'a OsStr); -impl_cmp_os_str!(<'a> PathBuf, Cow<'a, OsStr>); -impl_cmp_os_str!(<> PathBuf, OsString); -impl_cmp_os_str!(<> Path, OsStr); -impl_cmp_os_str!(<'a> Path, &'a OsStr); -impl_cmp_os_str!(<'a> Path, Cow<'a, OsStr>); -impl_cmp_os_str!(<> Path, OsString); -impl_cmp_os_str!(<'a> &'a Path, OsStr); -impl_cmp_os_str!(<'a, 'b> &'a Path, Cow<'b, OsStr>); -impl_cmp_os_str!(<'a> &'a Path, OsString); -impl_cmp_os_str!(<'a> Cow<'a, Path>, OsStr); -impl_cmp_os_str!(<'a, 'b> Cow<'a, Path>, &'b OsStr); -impl_cmp_os_str!(<'a> Cow<'a, Path>, OsString); +impl_cmp_os_str!(PathBuf, OsStr); +impl_cmp_os_str!(PathBuf, &OsStr); +impl_cmp_os_str!(PathBuf, Cow<'_, OsStr>); +impl_cmp_os_str!(PathBuf, OsString); +impl_cmp_os_str!(Path, OsStr); +impl_cmp_os_str!(Path, &OsStr); +impl_cmp_os_str!(Path, Cow<'_, OsStr>); +impl_cmp_os_str!(Path, OsString); +impl_cmp_os_str!(&Path, OsStr); +impl_cmp_os_str!(&Path, Cow<'_, OsStr>); +impl_cmp_os_str!(&Path, OsString); +impl_cmp_os_str!(Cow<'_, Path>, OsStr); +impl_cmp_os_str!(Cow<'_, Path>, &OsStr); +impl_cmp_os_str!(Cow<'_, Path>, OsString); #[stable(since = "1.7.0", feature = "strip_prefix")] impl fmt::Display for StripPrefixError { @@ -4019,7 +4137,7 @@ impl Error for NormalizeError {} /// Note that this [may change in the future][changes]. /// /// [changes]: io#platform-specific-behavior -/// [posix-semantics]: https://pubs.opengroup.org/onlinepubs/9699919799/basedefs/V1_chap04.html#tag_04_13 +/// [posix-semantics]: https://pubs.opengroup.org/onlinepubs/9799919799/basedefs/V1_chap04.html#tag_04_16 /// [windows-path]: https://docs.microsoft.com/en-us/windows/win32/api/fileapi/nf-fileapi-getfullpathnamew /// [cygwin-path]: https://cygwin.com/cygwin-api/func-cygwin-conv-path.html #[stable(feature = "absolute_path", since = "1.79.0")] diff --git a/library/std/src/prelude/v1.rs b/library/std/src/prelude/v1.rs index af9d28ebad356..aeefec8b9e084 100644 --- a/library/std/src/prelude/v1.rs +++ b/library/std/src/prelude/v1.rs @@ -79,7 +79,7 @@ mod ambiguous_macros_only { #[doc(no_inline)] pub use self::ambiguous_macros_only::{vec, panic}; -#[unstable(feature = "cfg_select", issue = "115585")] +#[stable(feature = "cfg_select", since = "1.95.0")] #[doc(no_inline)] pub use core::prelude::v1::cfg_select; @@ -115,9 +115,13 @@ pub use core::prelude::v1::trace_macros; // (no public module for them to be re-exported from). #[stable(feature = "builtin_macro_prelude", since = "1.38.0")] pub use core::prelude::v1::{ - alloc_error_handler, bench, derive, global_allocator, test, test_case, + alloc_error_handler, bench, global_allocator, test, test_case, }; +#[stable(feature = "builtin_macro_prelude", since = "1.38.0")] +#[doc(no_inline)] +pub use core::prelude::v1::derive; + #[unstable(feature = "derive_const", issue = "118304")] pub use core::prelude::v1::derive_const; diff --git a/library/std/src/process.rs b/library/std/src/process.rs index 6838bb422b0e0..a4c461737b620 100644 --- a/library/std/src/process.rs +++ b/library/std/src/process.rs @@ -14,7 +14,7 @@ //! let output = Command::new("echo") //! .arg("Hello world") //! .output() -//! .expect("Failed to execute command"); +//! .expect("echo command should execute successfully"); //! //! assert_eq!(b"Hello world\n", output.stdout.as_slice()); //! ``` @@ -41,20 +41,20 @@ //! .arg("Oh no, a tpyo!") //! .stdout(Stdio::piped()) //! .spawn() -//! .expect("Failed to start echo process"); +//! .expect("echo command should start"); //! //! // Note that `echo_child` is moved here, but we won't be needing //! // `echo_child` anymore -//! let echo_out = echo_child.stdout.expect("Failed to open echo stdout"); +//! let echo_out = echo_child.stdout.expect("child stdout should open"); //! //! let mut sed_child = Command::new("sed") //! .arg("s/tpyo/typo/") //! .stdin(Stdio::from(echo_out)) //! .stdout(Stdio::piped()) //! .spawn() -//! .expect("Failed to start sed process"); +//! .expect("sed command should start"); //! -//! let output = sed_child.wait_with_output().expect("Failed to wait on sed"); +//! let output = sed_child.wait_with_output().expect("wait_with_output on sed should succeed"); //! assert_eq!(b"Oh no, a typo!\n", output.stdout.as_slice()); //! ``` //! @@ -69,21 +69,21 @@ //! .stdin(Stdio::piped()) //! .stdout(Stdio::piped()) //! .spawn() -//! .expect("failed to execute child"); +//! .expect("child should start"); //! //! // If the child process fills its stdout buffer, it may end up //! // waiting until the parent reads the stdout, and not be able to //! // read stdin in the meantime, causing a deadlock. //! // Writing from another thread ensures that stdout is being read //! // at the same time, avoiding the problem. -//! let mut stdin = child.stdin.take().expect("failed to get stdin"); +//! let mut stdin = child.stdin.take().expect("stdin should be able to be retrieved"); //! std::thread::spawn(move || { -//! stdin.write_all(b"test").expect("failed to write to stdin"); +//! stdin.write_all(b"test").expect("writing to stdin should succeed"); //! }); //! //! let output = child //! .wait_with_output() -//! .expect("failed to wait on child"); +//! .expect("wait_with_output on child should succeed"); //! //! assert_eq!(b"test", output.stdout.as_slice()); //! ``` @@ -156,6 +156,8 @@ target_env = "sgx", target_os = "xous", target_os = "trusty", + target_os = "hermit", + target_os = "l4re", )) ))] mod tests; @@ -205,9 +207,9 @@ use crate::{fmt, format_args_nl, fs, str}; /// let mut child = Command::new("/bin/cat") /// .arg("file.txt") /// .spawn() -/// .expect("failed to execute child"); +/// .expect("child should spawn"); /// -/// let ecode = child.wait().expect("failed to wait on child"); +/// let ecode = child.wait().expect("child should be running"); /// /// assert!(ecode.success()); /// ``` @@ -222,7 +224,7 @@ pub struct Child { /// has been captured. You might find it helpful to do /// /// ```ignore (incomplete) - /// let stdin = child.stdin.take().expect("handle present"); + /// let stdin = child.stdin.take().expect("handle should be present"); /// ``` /// /// to avoid partially moving the `child` and thus blocking yourself from calling @@ -234,7 +236,7 @@ pub struct Child { /// has been captured. You might find it helpful to do /// /// ```ignore (incomplete) - /// let stdout = child.stdout.take().expect("handle present"); + /// let stdout = child.stdout.take().expect("handle should be present"); /// ``` /// /// to avoid partially moving the `child` and thus blocking yourself from calling @@ -246,7 +248,7 @@ pub struct Child { /// has been captured. You might find it helpful to do /// /// ```ignore (incomplete) - /// let stderr = child.stderr.take().expect("handle present"); + /// let stderr = child.stderr.take().expect("handle should be present"); /// ``` /// /// to avoid partially moving the `child` and thus blocking yourself from calling @@ -255,10 +257,6 @@ pub struct Child { pub stderr: Option, } -/// Allows extension traits within `std`. -#[unstable(feature = "sealed", issue = "none")] -impl crate::sealed::Sealed for Child {} - impl AsInner for Child { #[inline] fn as_inner(&self) -> &imp::Process { @@ -335,7 +333,7 @@ impl Write for ChildStdin { } fn is_write_vectored(&self) -> bool { - io::Write::is_write_vectored(&&*self) + io::Write::is_write_vectored(&self) } #[inline] @@ -416,7 +414,7 @@ impl Read for ChildStdout { self.inner.read(buf) } - fn read_buf(&mut self, buf: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, buf: BorrowedCursor<'_, u8>) -> io::Result<()> { self.inner.read_buf(buf) } @@ -486,7 +484,7 @@ impl Read for ChildStderr { self.inner.read(buf) } - fn read_buf(&mut self, buf: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, buf: BorrowedCursor<'_, u8>) -> io::Result<()> { self.inner.read_buf(buf) } @@ -546,13 +544,13 @@ impl fmt::Debug for ChildStderr { /// Command::new("cmd") /// .args(["/C", "echo hello"]) /// .output() -/// .expect("failed to execute process") +/// .expect("process should execute successfully") /// } else { /// Command::new("sh") /// .arg("-c") /// .arg("echo hello") /// .output() -/// .expect("failed to execute process") +/// .expect("process should execute successfully") /// }; /// /// let hello = output.stdout; @@ -567,8 +565,8 @@ impl fmt::Debug for ChildStderr { /// /// let mut echo_hello = Command::new("sh"); /// echo_hello.arg("-c").arg("echo hello"); -/// let hello_1 = echo_hello.output().expect("failed to execute process"); -/// let hello_2 = echo_hello.output().expect("failed to execute process"); +/// let hello_1 = echo_hello.output().expect("process should execute successfully"); +/// let hello_2 = echo_hello.output().expect("process should execute successfully"); /// ``` /// /// Similarly, you can call builder methods after spawning a process and then @@ -580,7 +578,7 @@ impl fmt::Debug for ChildStderr { /// let mut list_dir = Command::new("ls"); /// /// // Execute `ls` in the current directory of the program. -/// list_dir.status().expect("process failed to execute"); +/// list_dir.status().expect("process should execute successfully"); /// /// println!(); /// @@ -588,7 +586,7 @@ impl fmt::Debug for ChildStderr { /// list_dir.current_dir("/"); /// /// // And then execute `ls` again but in the root directory. -/// list_dir.status().expect("process failed to execute"); +/// list_dir.status().expect("process should execute successfully"); /// ``` #[stable(feature = "process", since = "1.0.0")] #[cfg_attr(not(test), rustc_diagnostic_item = "Command")] @@ -596,10 +594,6 @@ pub struct Command { inner: imp::Command, } -/// Allows extension traits within `std`. -#[unstable(feature = "sealed", issue = "none")] -impl crate::sealed::Sealed for Command {} - impl Command { /// Constructs a new `Command` for launching the program at /// path `program`, with the following default configuration: @@ -616,21 +610,50 @@ impl Command { /// Builder methods are provided to change these defaults and /// otherwise configure the process. /// - /// If `program` is not an absolute path, the `PATH` will be searched in - /// an OS-defined way. - /// - /// The search path to be used may be controlled by setting the - /// `PATH` environment variable on the Command, - /// but this has some implementation limitations on Windows - /// (see issue #37519). + /// If `program` is not an absolute path, the `PATH` environment variable + /// will be searched in an OS-defined way. /// /// # Platform-specific behavior /// - /// Note on Windows: For executable files with the .exe extension, - /// it can be omitted when specifying the program for this Command. - /// However, if the file has a different extension, - /// a filename including the extension needs to be provided, - /// otherwise the file won't be found. + /// The details below describe the current behavior, but these details + /// may change in future versions of Rust. + /// + /// On Unix, the `PATH` searched comes from the child's environment: + /// + /// - If the environment is unmodified, the child inherits the parent's + /// `PATH` and that is what is searched. + /// - If `PATH` is explicitly set via [`env`], that new value is searched. + /// - If [`env_clear`] or [`env_remove`] removes `PATH` without a + /// replacement, `execvp` falls back to an OS-defined default (typically + /// `/bin:/usr/bin`), **not** the parent's `PATH`. This may fail to find + /// programs that rely on the parent's `PATH`. + /// + /// To avoid surprises, use an absolute path or explicitly set `PATH` on + /// the `Command` when modifying the child's environment. + /// + /// On Windows, Rust resolves the executable path before spawning, rather + /// than passing the name to `CreateProcessW` for resolution. When + /// `program` is not an absolute path, the following locations are searched + /// in order: + /// + /// 1. The child's `PATH`, if explicitly set via [`env`]. + /// 2. The directory of the current executable. + /// 3. The system directory (`GetSystemDirectoryW`). + /// 4. The Windows directory (`GetWindowsDirectoryW`). + /// 5. The parent process's `PATH`. + /// + /// Note: when `PATH` is cleared via [`env_clear`] or [`env_remove`] on + /// Windows, step 1 is skipped but the parent process's `PATH` is still + /// searched at step 5, unlike on Unix. + /// + /// For executable files, the `.exe` extension may be omitted. Files with + /// other extensions must include the extension, otherwise they will not be + /// found. Note that this behavior has some known limitations + /// (see issue #37519). + /// + /// [`env`]: Self::env + /// [`env_remove`]: Self::env_remove + /// [`env_clear`]: Self::env_clear /// /// # Examples /// @@ -639,7 +662,7 @@ impl Command { /// /// Command::new("sh") /// .spawn() - /// .expect("sh command failed to start"); + /// .expect("sh command should start"); /// ``` /// /// # Caveats @@ -655,7 +678,7 @@ impl Command { /// Command::new("ls") /// .arg("-l") // arg passed separately /// .spawn() - /// .expect("ls command failed to start"); + /// .expect("ls command should start"); /// ``` /// /// [`arg`]: Self::arg @@ -721,7 +744,7 @@ impl Command { /// .arg("-l") /// .arg("-a") /// .spawn() - /// .expect("ls command failed to start"); + /// .expect("ls command should start"); /// ``` #[stable(feature = "process", since = "1.0.0")] pub fn arg>(&mut self, arg: S) -> &mut Command { @@ -767,7 +790,7 @@ impl Command { /// Command::new("ls") /// .args(["-l", "-a"]) /// .spawn() - /// .expect("ls command failed to start"); + /// .expect("ls command should start"); /// ``` #[stable(feature = "process", since = "1.0.0")] pub fn args(&mut self, args: I) -> &mut Command @@ -803,7 +826,7 @@ impl Command { /// Command::new("ls") /// .env("PATH", "/bin") /// .spawn() - /// .expect("ls command failed to start"); + /// .expect("ls command should start"); /// ``` #[stable(feature = "process", since = "1.0.0")] pub fn env(&mut self, key: K, val: V) -> &mut Command @@ -847,7 +870,7 @@ impl Command { /// .env_clear() /// .envs(&filtered_env) /// .spawn() - /// .expect("printenv failed to start"); + /// .expect("printenv command should start"); /// ``` #[stable(feature = "command_envs", since = "1.19.0")] pub fn envs(&mut self, vars: I) -> &mut Command @@ -945,7 +968,7 @@ impl Command { /// Command::new("ls") /// .current_dir("/bin") /// .spawn() - /// .expect("ls command failed to start"); + /// .expect("ls command should start"); /// ``` /// /// [`canonicalize`]: crate::fs::canonicalize @@ -974,7 +997,7 @@ impl Command { /// Command::new("ls") /// .stdin(Stdio::null()) /// .spawn() - /// .expect("ls command failed to start"); + /// .expect("ls command should start"); /// ``` #[stable(feature = "process", since = "1.0.0")] pub fn stdin>(&mut self, cfg: T) -> &mut Command { @@ -1001,7 +1024,7 @@ impl Command { /// Command::new("ls") /// .stdout(Stdio::null()) /// .spawn() - /// .expect("ls command failed to start"); + /// .expect("ls command should start"); /// ``` #[stable(feature = "process", since = "1.0.0")] pub fn stdout>(&mut self, cfg: T) -> &mut Command { @@ -1028,7 +1051,7 @@ impl Command { /// Command::new("ls") /// .stderr(Stdio::null()) /// .spawn() - /// .expect("ls command failed to start"); + /// .expect("ls command should start"); /// ``` #[stable(feature = "process", since = "1.0.0")] pub fn stderr>(&mut self, cfg: T) -> &mut Command { @@ -1040,6 +1063,26 @@ impl Command { /// /// By default, stdin, stdout and stderr are inherited from the parent. /// + /// # Errors + /// + /// This method returns an [`io::Error`] if the child process could not be + /// spawned. Common reasons include: + /// + /// * the program could not be found (for example, it does not exist, or, + /// when given a bare name, it is not present in the `PATH`); + /// * the current process does not have permission to execute the program + /// (for example, the file is not marked executable, or execution is + /// denied by a security policy such as `seccomp`); + /// * the operating system could not create the new process because of + /// resource exhaustion (for example, a limit on the number of processes + /// was reached). + /// + /// An error is only returned for failures that occur while the child is + /// being spawned. Once the child has started successfully, anything that + /// happens to it afterwards — including being terminated by a signal — is + /// reported through its [`ExitStatus`] rather than as an error from the + /// spawning method. + /// /// # Examples /// /// ```no_run @@ -1047,7 +1090,7 @@ impl Command { /// /// Command::new("ls") /// .spawn() - /// .expect("ls command failed to start"); + /// .expect("ls command should start"); /// ``` #[stable(feature = "process", since = "1.0.0")] pub fn spawn(&mut self) -> io::Result { @@ -1062,6 +1105,20 @@ impl Command { /// attempt by the child process to read from the stdin stream will result /// in the stream immediately closing. /// + /// # Errors + /// + /// Like [`spawn`], this method returns an [`io::Error`] if the child + /// process could not be spawned; see [`spawn`] for the common reasons. It + /// may also return an error if reading the child's output or waiting on the + /// child fails. + /// + /// Note that this method does **not** return an error if the child runs and + /// then exits unsuccessfully, or is terminated by a signal. In those cases + /// it still returns [`Ok`], and the outcome is reflected in the + /// [`ExitStatus`] stored in the returned [`Output`]. + /// + /// [`spawn`]: Command::spawn + /// /// # Examples /// /// ```should_panic @@ -1089,6 +1146,19 @@ impl Command { /// /// By default, stdin, stdout and stderr are inherited from the parent. /// + /// # Errors + /// + /// Like [`spawn`], this method returns an [`io::Error`] if the child + /// process could not be spawned; see [`spawn`] for the common reasons. It + /// may also return an error if waiting on the child fails. + /// + /// Note that this method does **not** return an error if the child runs and + /// then exits unsuccessfully, or is terminated by a signal. In those cases + /// it still returns [`Ok`], and the outcome is reflected in the returned + /// [`ExitStatus`]. + /// + /// [`spawn`]: Command::spawn + /// /// # Examples /// /// ```should_panic @@ -1097,7 +1167,7 @@ impl Command { /// let status = Command::new("/bin/cat") /// .arg("file.txt") /// .status() - /// .expect("failed to execute process"); + /// .expect("process should execute successfully"); /// /// println!("process finished with: {status}"); /// @@ -1155,7 +1225,8 @@ impl Command { /// [`Command::env_remove`] can be retrieved with this method. /// /// Note that this output does not include environment variables inherited from the parent - /// process. + /// process. To see the full list of environment variables, including those inherited from the + /// parent process, use [`Command::get_resolved_envs`]. /// /// Each element is a tuple key/value pair `(&OsStr, Option<&OsStr>)`. A [`None`] value /// indicates its key was explicitly removed via [`Command::env_remove`]. The associated key for @@ -1184,6 +1255,42 @@ impl Command { CommandEnvs { iter: self.inner.get_envs() } } + /// Returns an iterator of the environment variables that will be set when the process is spawned. + /// + /// This returns the environment as it would be if the command were executed at the time of calling + /// this method. The returned environment includes: + /// - All inherited environment variables from the parent process (unless [`Command::env_clear`] was called) + /// - All environment variables explicitly set via [`Command::env`] or [`Command::envs`] + /// - Excluding any environment variables removed via [`Command::env_remove`] + /// + /// Note that the returned environment is a snapshot at the time this method is called and will not + /// reflect any subsequent changes to the `Command` or the parent process's environment. Additionally, + /// it will not reflect changes made in a `pre_exec` hook (on Unix platforms). + /// + /// Each element is a tuple `(OsString, OsString)` representing an environment variable key and value. + /// + /// # Examples + /// + /// ``` + /// #![feature(command_resolved_envs)] + /// use std::process::Command; + /// use std::ffi::{OsString, OsStr}; + /// use std::env; + /// use std::collections::HashMap; + /// + /// let mut cmd = Command::new("ls"); + /// cmd.env("TZ", "UTC"); + /// unsafe { env::set_var("EDITOR", "vim"); } + /// + /// let resolved: HashMap = cmd.get_resolved_envs().collect(); + /// assert_eq!(resolved.get(OsStr::new("TZ")), Some(&OsString::from("UTC"))); + /// assert_eq!(resolved.get(OsStr::new("EDITOR")), Some(&OsString::from("vim"))); + /// ``` + #[unstable(feature = "command_resolved_envs", issue = "149070")] + pub fn get_resolved_envs(&self) -> CommandResolvedEnvs { + self.inner.get_resolved_envs() + } + /// Returns the working directory for the child process. /// /// This returns [`None`] if the working directory will not be changed. @@ -1295,6 +1402,12 @@ impl<'a> ExactSizeIterator for CommandArgs<'a> { } } +const fn assert_send() {} +const fn assert_sync() {} + +const _: () = assert_send::>(); +const _: () = assert_sync::>(); + /// An iterator over the command environment variables. /// /// This struct is created by @@ -1337,6 +1450,9 @@ impl<'a> fmt::Debug for CommandEnvs<'a> { } } +#[unstable(feature = "command_resolved_envs", issue = "149070")] +pub use imp::CommandResolvedEnvs; + /// The output of a finished process. /// /// This is returned in a Result by either the [`output`] method of a @@ -1380,6 +1496,7 @@ impl Output { /// # Examples /// /// ``` + /// # #![allow(unused_features)] /// #![feature(exit_status_error)] /// # #[cfg(all(unix, not(target_os = "android"), not(all(target_vendor = "apple", not(target_os = "macos")))))] { /// use std::process::Command; @@ -1441,7 +1558,7 @@ impl Stdio { /// .arg("Hello, world!") /// .stdout(Stdio::piped()) /// .output() - /// .expect("Failed to execute command"); + /// .expect("process should execute successfully"); /// /// assert_eq!(String::from_utf8_lossy(&output.stdout), "Hello, world!\n"); /// // Nothing echoed to console @@ -1457,14 +1574,14 @@ impl Stdio { /// .stdin(Stdio::piped()) /// .stdout(Stdio::piped()) /// .spawn() - /// .expect("Failed to spawn child process"); + /// .expect("rev command should start"); /// - /// let mut stdin = child.stdin.take().expect("Failed to open stdin"); + /// let mut stdin = child.stdin.take().expect("child stdin should be retrievable"); /// std::thread::spawn(move || { - /// stdin.write_all("Hello, world!".as_bytes()).expect("Failed to write to stdin"); + /// stdin.write_all("Hello, world!".as_bytes()).expect("writing to child stdin should succeed"); /// }); /// - /// let output = child.wait_with_output().expect("Failed to read stdout"); + /// let output = child.wait_with_output().expect("child stdout should be able to be read"); /// assert_eq!(String::from_utf8_lossy(&output.stdout), "!dlrow ,olleH"); /// ``` /// @@ -1493,7 +1610,7 @@ impl Stdio { /// .arg("Hello, world!") /// .stdout(Stdio::inherit()) /// .output() - /// .expect("Failed to execute command"); + /// .expect("process should execute successfully"); /// /// assert_eq!(String::from_utf8_lossy(&output.stdout), ""); /// // "Hello, world!" echoed to console @@ -1534,7 +1651,7 @@ impl Stdio { /// .arg("Hello, world!") /// .stdout(Stdio::null()) /// .output() - /// .expect("Failed to execute command"); + /// .expect("process should execute successfully"); /// /// assert_eq!(String::from_utf8_lossy(&output.stdout), ""); /// // Nothing echoed to console @@ -1549,7 +1666,7 @@ impl Stdio { /// .stdin(Stdio::null()) /// .stdout(Stdio::piped()) /// .output() - /// .expect("Failed to execute command"); + /// .expect("process should execute successfully"); /// /// assert_eq!(String::from_utf8_lossy(&output.stdout), ""); /// // Ignores any piped-in input @@ -1604,13 +1721,13 @@ impl From for Stdio { /// let reverse = Command::new("rev") /// .stdin(Stdio::piped()) /// .spawn() - /// .expect("failed reverse command"); + /// .expect("rev command should start"); /// /// let _echo = Command::new("echo") /// .arg("Hello, world!") /// .stdout(reverse.stdin.unwrap()) // Converted into a Stdio here /// .output() - /// .expect("failed echo command"); + /// .expect("echo command should execute successfully"); /// /// // "!dlrow ,olleH" echoed to console /// ``` @@ -1634,12 +1751,12 @@ impl From for Stdio { /// .arg("Hello, world!") /// .stdout(Stdio::piped()) /// .spawn() - /// .expect("failed echo command"); + /// .expect("echo command should start"); /// /// let reverse = Command::new("rev") /// .stdin(hello.stdout.unwrap()) // Converted into a Stdio here /// .output() - /// .expect("failed reverse command"); + /// .expect("rev command should execute successfully"); /// /// assert_eq!(reverse.stdout, b"!dlrow ,olleH\n"); /// ``` @@ -1661,13 +1778,13 @@ impl From for Stdio { /// .arg("non_existing_file.txt") /// .stderr(Stdio::piped()) /// .spawn() - /// .expect("failed reverse command"); + /// .expect("rev command should start"); /// /// let cat = Command::new("cat") /// .arg("-") /// .stdin(reverse.stderr.unwrap()) // Converted into a Stdio here /// .output() - /// .expect("failed echo command"); + /// .expect("cat command should execute successfully"); /// /// assert_eq!( /// String::from_utf8_lossy(&cat.stdout), @@ -1822,10 +1939,6 @@ impl Default for ExitStatus { } } -/// Allows extension traits within `std`. -#[unstable(feature = "sealed", issue = "none")] -impl crate::sealed::Sealed for ExitStatus {} - impl ExitStatus { /// Was termination successful? Returns a `Result`. /// @@ -1839,7 +1952,7 @@ impl ExitStatus { /// let status = Command::new("ls") /// .arg("/dev/nonexistent") /// .status() - /// .expect("ls could not be executed"); + /// .expect("ls command should execute successfully"); /// /// println!("ls: {status}"); /// status.exit_ok().expect_err("/dev/nonexistent could be listed!"); @@ -1861,7 +1974,7 @@ impl ExitStatus { /// let status = Command::new("mkdir") /// .arg("projects") /// .status() - /// .expect("failed to execute mkdir"); + /// .expect("mkdir command should execute successfully"); /// /// if status.success() { /// println!("'projects/' directory created"); @@ -1894,7 +2007,7 @@ impl ExitStatus { /// let status = Command::new("mkdir") /// .arg("projects") /// .status() - /// .expect("failed to execute mkdir"); + /// .expect("mkdir command should execute successfully"); /// /// match status.code() { /// Some(code) => println!("Exited with status code: {code}"), @@ -1928,10 +2041,6 @@ impl fmt::Display for ExitStatus { } } -/// Allows extension traits within `std`. -#[unstable(feature = "sealed", issue = "none")] -impl crate::sealed::Sealed for ExitStatusError {} - /// Describes the result of a process after it has failed /// /// Produced by the [`.exit_ok`](ExitStatus::exit_ok) method on [`ExitStatus`]. @@ -1959,6 +2068,7 @@ impl crate::sealed::Sealed for ExitStatusError {} pub struct ExitStatusError(imp::ExitStatusError); #[unstable(feature = "exit_status_error", issue = "84908")] +#[doc(test(attr(allow(unused_features))))] impl ExitStatusError { /// Reports the exit code, if applicable, from an `ExitStatusError`. /// @@ -2099,10 +2209,6 @@ impl crate::error::Error for ExitStatusError {} #[stable(feature = "process_exitcode", since = "1.61.0")] pub struct ExitCode(imp::ExitCode); -/// Allows extension traits within `std`. -#[unstable(feature = "sealed", issue = "none")] -impl crate::sealed::Sealed for ExitCode {} - #[stable(feature = "process_exitcode", since = "1.61.0")] impl ExitCode { /// The canonical `ExitCode` for successful termination on this platform. @@ -2229,7 +2335,7 @@ impl Child { /// /// let mut command = Command::new("yes"); /// if let Ok(mut child) = command.spawn() { - /// child.kill().expect("command couldn't be killed"); + /// child.kill().expect("process should be killed"); /// } else { /// println!("yes command didn't start"); /// } @@ -2280,7 +2386,7 @@ impl Child { /// /// let mut command = Command::new("ls"); /// if let Ok(mut child) = command.spawn() { - /// child.wait().expect("command wasn't running"); + /// child.wait().expect("child should be running"); /// println!("Child has finished its execution!"); /// } else { /// println!("ls command didn't start"); @@ -2353,11 +2459,11 @@ impl Child { /// .arg("file.txt") /// .stdout(Stdio::piped()) /// .spawn() - /// .expect("failed to execute child"); + /// .expect("child should spawn"); /// /// let output = child /// .wait_with_output() - /// .expect("failed to wait on child"); + /// .expect("wait_with_output on child should succeed"); /// /// assert!(output.status.success()); /// ``` @@ -2464,7 +2570,7 @@ impl Child { #[cfg_attr(not(test), rustc_diagnostic_item = "process_exit")] pub fn exit(code: i32) -> ! { crate::rt::cleanup(); - crate::sys::os::exit(code) + crate::sys::exit::exit(code) } /// Terminates the process in an abnormal fashion. @@ -2533,6 +2639,10 @@ pub fn abort() -> ! { crate::sys::abort_internal(); } +#[doc(inline)] +#[unstable(feature = "abort_immediate", issue = "154601")] +pub use core::process::abort_immediate; + /// Returns the OS-assigned process identifier associated with this process. /// /// # Examples @@ -2545,7 +2655,7 @@ pub fn abort() -> ! { #[must_use] #[stable(feature = "getpid", since = "1.26.0")] pub fn id() -> u32 { - crate::sys::os::getpid() + imp::getpid() } /// A trait for implementing arbitrary return types in the `main` function. diff --git a/library/std/src/process/tests.rs b/library/std/src/process/tests.rs index 12c5130defe5a..9fe14b2e468a5 100644 --- a/library/std/src/process/tests.rs +++ b/library/std/src/process/tests.rs @@ -28,7 +28,11 @@ fn shell_cmd() -> Command { #[test] #[cfg_attr( - any(target_os = "vxworks", all(target_vendor = "apple", not(target_os = "macos"))), + any( + target_os = "vxworks", + all(target_vendor = "apple", not(target_os = "macos")), + target_os = "l4re" + ), ignore = "no shell available" )] fn smoke() { @@ -53,7 +57,11 @@ fn smoke_failure() { #[test] #[cfg_attr( - any(target_os = "vxworks", all(target_vendor = "apple", not(target_os = "macos"))), + any( + target_os = "vxworks", + all(target_vendor = "apple", not(target_os = "macos")), + target_os = "l4re" + ), ignore = "no shell available" )] fn exit_reported_right() { @@ -71,7 +79,11 @@ fn exit_reported_right() { #[test] #[cfg(unix)] #[cfg_attr( - any(target_os = "vxworks", all(target_vendor = "apple", not(target_os = "macos"))), + any( + target_os = "vxworks", + all(target_vendor = "apple", not(target_os = "macos")), + target_os = "l4re" + ), ignore = "no shell available" )] fn signal_reported_right() { @@ -98,7 +110,11 @@ pub fn run_output(mut cmd: Command) -> String { #[test] #[cfg_attr( - any(target_os = "vxworks", all(target_vendor = "apple", not(target_os = "macos"))), + any( + target_os = "vxworks", + all(target_vendor = "apple", not(target_os = "macos")), + target_os = "l4re" + ), ignore = "no shell available" )] fn stdout_works() { @@ -116,7 +132,11 @@ fn stdout_works() { #[test] #[cfg_attr(windows, ignore)] #[cfg_attr( - any(target_os = "vxworks", all(target_vendor = "apple", not(target_os = "macos"))), + any( + target_os = "vxworks", + all(target_vendor = "apple", not(target_os = "macos")), + target_os = "l4re" + ), ignore = "no shell available" )] fn set_current_dir_works() { @@ -142,7 +162,11 @@ fn set_current_dir_works() { #[test] #[cfg_attr(windows, ignore)] #[cfg_attr( - any(target_os = "vxworks", all(target_vendor = "apple", not(target_os = "macos"))), + any( + target_os = "vxworks", + all(target_vendor = "apple", not(target_os = "macos")), + target_os = "l4re" + ), ignore = "no shell available" )] fn stdin_works() { @@ -163,7 +187,11 @@ fn stdin_works() { #[test] #[cfg_attr( - any(target_os = "vxworks", all(target_vendor = "apple", not(target_os = "macos"))), + any( + target_os = "vxworks", + all(target_vendor = "apple", not(target_os = "macos")), + target_os = "l4re" + ), ignore = "no shell available" )] fn child_stdout_read_buf() { @@ -188,16 +216,20 @@ fn child_stdout_read_buf() { // ChildStdout::read_buf should omit buffer initialization. if cfg!(target_os = "windows") { assert_eq!(buf.filled(), b"abc\r\n"); - assert_eq!(buf.init_len(), 5); + assert!(!buf.is_init()); } else { assert_eq!(buf.filled(), b"abc\n"); - assert_eq!(buf.init_len(), 4); + assert!(!buf.is_init()); }; } #[test] #[cfg_attr( - any(target_os = "vxworks", all(target_vendor = "apple", not(target_os = "macos"))), + any( + target_os = "vxworks", + all(target_vendor = "apple", not(target_os = "macos")), + target_os = "l4re" + ), ignore = "no shell available" )] fn test_process_status() { @@ -217,6 +249,7 @@ fn test_process_status() { } #[test] +#[cfg_attr(any(target_os = "l4re"), ignore = "no fork/exec available")] fn test_process_output_fail_to_start() { match Command::new("/no-binary-by-this-name-should-exist").output() { Err(e) => assert_eq!(e.kind(), ErrorKind::NotFound), @@ -226,7 +259,11 @@ fn test_process_output_fail_to_start() { #[test] #[cfg_attr( - any(target_os = "vxworks", all(target_vendor = "apple", not(target_os = "macos"))), + any( + target_os = "vxworks", + all(target_vendor = "apple", not(target_os = "macos")), + target_os = "l4re" + ), ignore = "no shell available" )] fn test_process_output_output() { @@ -244,7 +281,11 @@ fn test_process_output_output() { #[test] #[cfg_attr( - any(target_os = "vxworks", all(target_vendor = "apple", not(target_os = "macos"))), + any( + target_os = "vxworks", + all(target_vendor = "apple", not(target_os = "macos")), + target_os = "l4re" + ), ignore = "no shell available" )] fn test_process_output_error() { @@ -262,7 +303,11 @@ fn test_process_output_error() { #[test] #[cfg_attr( - any(target_os = "vxworks", all(target_vendor = "apple", not(target_os = "macos"))), + any( + target_os = "vxworks", + all(target_vendor = "apple", not(target_os = "macos")), + target_os = "l4re" + ), ignore = "no shell available" )] fn test_finish_once() { @@ -276,7 +321,11 @@ fn test_finish_once() { #[test] #[cfg_attr( - any(target_os = "vxworks", all(target_vendor = "apple", not(target_os = "macos"))), + any( + target_os = "vxworks", + all(target_vendor = "apple", not(target_os = "macos")), + target_os = "l4re" + ), ignore = "no shell available" )] fn test_finish_twice() { @@ -291,7 +340,11 @@ fn test_finish_twice() { #[test] #[cfg_attr( - any(target_os = "vxworks", all(target_vendor = "apple", not(target_os = "macos"))), + any( + target_os = "vxworks", + all(target_vendor = "apple", not(target_os = "macos")), + target_os = "l4re" + ), ignore = "no shell available" )] fn test_wait_with_output_once() { @@ -329,7 +382,11 @@ pub fn env_cmd() -> Command { #[test] #[cfg_attr( - any(target_os = "vxworks", all(target_vendor = "apple", not(target_os = "macos"))), + any( + target_os = "vxworks", + all(target_vendor = "apple", not(target_os = "macos")), + target_os = "l4re" + ), ignore = "no shell available" )] fn test_override_env() { @@ -355,7 +412,11 @@ fn test_override_env() { #[test] #[cfg_attr( - any(target_os = "vxworks", all(target_vendor = "apple", not(target_os = "macos"))), + any( + target_os = "vxworks", + all(target_vendor = "apple", not(target_os = "macos")), + target_os = "l4re" + ), ignore = "no shell available" )] fn test_add_to_env() { @@ -370,7 +431,11 @@ fn test_add_to_env() { #[test] #[cfg_attr( - any(target_os = "vxworks", all(target_vendor = "apple", not(target_os = "macos"))), + any( + target_os = "vxworks", + all(target_vendor = "apple", not(target_os = "macos")), + target_os = "l4re" + ), ignore = "no shell available" )] fn test_capture_env_at_spawn() { @@ -654,6 +719,7 @@ fn run_canonical_bat_script() { } #[test] +#[cfg_attr(target_os = "l4re", ignore = "no shell available")] fn terminate_exited_process() { let mut cmd = if cfg!(target_os = "android") { let mut p = shell_cmd(); diff --git a/library/std/src/random.rs b/library/std/src/random.rs index 3994c5cfaf6f4..853756fcd32b6 100644 --- a/library/std/src/random.rs +++ b/library/std/src/random.rs @@ -1,11 +1,59 @@ //! Random value generation. +//! +//! This module provides two low-level interfaces for random number generation: +//! * The [`Rng`] trait abstracts over all random number generators (RNGs) and +//! is intended to be used in all cases where the choice of RNG is left to the +//! user. It provides the [`fill_bytes`](Rng::fill_bytes) method that fills a +//! buffer of [`u8`]s with freshly-generated random data. +//! * The [`SystemRng`] implements the [`Rng`] trait by asking the operating +//! system for cryptographically-secure random data on every call to +//! `fill_bytes`. +//! +//! In the future, higher-level interfaces for features like sampling distributions +//! may be added to this module. Until that time, users of `fill_bytes` should +//! take care to avoid sampling bias when using the filled byte buffer to create +//! an instance of another type. In particular, the modulo operation is **not** +//! suitable for constraining the range of an unconstrained number: +//! ```compile_fail +//! let mut buf = [0; 2]; +//! rng.fill_bytes(&mut buf); +//! // 💀 **DO NOT DO THIS** 💀 +//! // Numbers below ca. 22000 will be twice as likely. +//! let very_bad_random_number = u16::from_ne_bytes(buf) % 45000; +//! ``` +//! +//! # Examples +//! +//! Generating a [version 4/variant 1 UUID] represented as text: +//! ``` +//! #![feature(random)] +//! +//! use std::random::{Rng, SystemRng}; +//! +//! fn uuid(rng: &mut impl Rng) -> String { +//! let mut buf = [0; 16]; +//! rng.fill_bytes(&mut buf); +//! // Use little-endian to make the result reproducible across architectures. +//! let bits = u128::from_le_bytes(buf); +//! let g1 = (bits >> 96) as u32; +//! let g2 = (bits >> 80) as u16; +//! let g3 = (0x4000 | (bits >> 64) & 0x0fff) as u16; +//! let g4 = (0x8000 | (bits >> 48) & 0x3fff) as u16; +//! let g5 = (bits & 0xffffffffffff) as u64; +//! format!("{g1:08x}-{g2:04x}-{g3:04x}-{g4:04x}-{g5:012x}") +//! } +//! +//! println!("{}", uuid(&mut SystemRng)); +//! ``` +//! +//! [version 4/variant 1 UUID]: https://en.wikipedia.org/wiki/Universally_unique_identifier#Version_4_(random) #[unstable(feature = "random", issue = "130703")] pub use core::random::*; use crate::sys::random as sys; -/// The default random source. +/// The system random number generator. /// /// This asks the system for random data suitable for cryptographic purposes /// such as key generation. If security is a concern, consult the platform @@ -13,8 +61,28 @@ use crate::sys::random as sys; /// /// The high quality of randomness provided by this source means it can be quite /// slow on some targets. If you need a large quantity of random numbers and -/// security is not a concern, consider using an alternative random number -/// generator (potentially seeded from this one). +/// security is not a concern, you might want to consider using an alternative +/// random number generator. That said, `std` attempts to use the fastest source +/// available on the system that still provides strong security. A custom random +/// number generator will in nearly all cases have weaker security attributes +/// than `SystemRng`. +/// +/// # Blocking +/// +/// The underlying syscalls might block the calling thread until there is +/// sufficient [entropy] in the system to seed a procedural random number +/// generator. This is usually only a concern if the program runs immediately +/// after the system boots. +/// +/// # Panicking +/// +/// Calling `fill_bytes` will panic if the system cannot provide the required +/// random data. Due to the blocking behaviour described above, this is a +/// permanent condition in nearly all cases and implies that the system lacks +/// the facilities (hardware or software) necessary for collecting entropy. +/// Non-embedded systems usually do not suffer from this limitation. +/// +/// [entropy]: https://en.wikipedia.org/wiki/Entropy_(information_theory) /// /// # Underlying sources /// @@ -35,15 +103,17 @@ use crate::sys::random as sys; /// Vita | `arc4random_buf` /// Hermit | `read_entropy` /// Horizon, Cygwin | `getrandom` -/// AIX, Hurd, L4Re, QNX | `/dev/urandom` +/// AIX, Hurd, QNX | `/dev/urandom` /// Redox | `/scheme/rand` -/// RTEMS | [`arc4random_buf`](https://docs.rtems.org/branches/master/bsp-howto/getentropy.html) +/// RTEMS | [`arc4random_buf`](https://docs.rtems.org/branches/main/bsp-howto/getentropy.html) /// SGX | [`rdrand`](https://en.wikipedia.org/wiki/RDRAND) /// SOLID | `SOLID_RNG_SampleRandomBytes` /// TEEOS | `TEE_GenerateRandom` /// UEFI | [`EFI_RNG_PROTOCOL`](https://uefi.org/specs/UEFI/2.10/37_Secure_Technologies.html#random-number-generator-protocol) /// VxWorks | `randABytes` after waiting for `randSecure` to become ready -/// WASI | [`random_get`](https://github.com/WebAssembly/WASI/blob/main/legacy/preview1/docs.md#-random_getbuf-pointeru8-buf_len-size---result-errno) +/// WASIp1 | [`random_get`](https://github.com/WebAssembly/WASI/blob/wasi-0.1/preview1/docs.md#-random_getbuf-pointeru8-buf_len-size---result-errno) +/// WASIp2 | [`get-random-bytes`] +/// WASIp3 | [`get-random-bytes`] /// ZKVM | `sys_rand` /// /// Note that the sources used might change over time. @@ -54,12 +124,27 @@ use crate::sys::random as sys; /// /// [`getrandom`]: https://www.man7.org/linux/man-pages/man2/getrandom.2.html /// [`/dev/urandom`]: https://www.man7.org/linux/man-pages/man4/random.4.html +/// [`get-random-bytes`]: https://github.com/WebAssembly/WASI/blob/main/proposals/random/imports.md#get-random-bytes-func +/// +/// # Examples +/// +/// Filling a buffer with random bytes +/// ``` +/// #![feature(random)] +/// +/// use std::random::{Rng, SystemRng}; +/// +/// let mut buf = [0; 16]; +/// SystemRng.fill_bytes(&mut buf); +/// dbg!(buf); +/// ``` +#[doc(alias = "getrandom", alias = "getentropy", alias = "arc4random")] #[derive(Default, Debug, Clone, Copy)] #[unstable(feature = "random", issue = "130703")] -pub struct DefaultRandomSource; +pub struct SystemRng; #[unstable(feature = "random", issue = "130703")] -impl RandomSource for DefaultRandomSource { +impl Rng for SystemRng { fn fill_bytes(&mut self, bytes: &mut [u8]) { sys::fill_bytes(bytes) } @@ -67,9 +152,9 @@ impl RandomSource for DefaultRandomSource { /// Generates a random value from a distribution, using the default random source. /// -/// This is a convenience function for `dist.sample(&mut DefaultRandomSource)` and will sample -/// according to the same distribution as the underlying [`Distribution`] trait implementation. See -/// [`DefaultRandomSource`] for more information about how randomness is sourced. +/// This is a convenience function for `dist.sample(&mut SystemRng)` and will sample according to +/// the same distribution as the underlying [`Distribution`] trait implementation. See [`SystemRng`] +/// for more information about how randomness is sourced. /// /// # Examples /// @@ -92,5 +177,5 @@ impl RandomSource for DefaultRandomSource { /// [version 4/variant 1 UUID]: https://en.wikipedia.org/wiki/Universally_unique_identifier#Version_4_(random) #[unstable(feature = "random", issue = "130703")] pub fn random(dist: impl Distribution) -> T { - dist.sample(&mut DefaultRandomSource) + dist.sample(&mut SystemRng) } diff --git a/library/std/src/rt.rs b/library/std/src/rt.rs index 11c0a0b9daf7b..35d17d56ddd49 100644 --- a/library/std/src/rt.rs +++ b/library/std/src/rt.rs @@ -166,8 +166,8 @@ fn lang_start_internal( // prevent std from accidentally introducing a panic to these functions. Another is from // user code from `main` or, more nefariously, as described in e.g. issue #86030. // - // We use `catch_unwind` with `handle_rt_panic` instead of `abort_unwind` to make the error in - // case of a panic a bit nicer. + // We use `catch_unwind` with `handle_rt_panic` instead of `abort_on_unwind` to make the error + // in case of a panic a bit nicer. panic::catch_unwind(move || { // SAFETY: Only called once during runtime initialization. unsafe { init(argc, argv, sigpipe) }; @@ -187,7 +187,7 @@ fn lang_start_internal( cleanup(); // Guard against multiple threads calling `libc::exit` concurrently. // See the documentation for `unique_thread_exit` for more information. - crate::sys::exit_guard::unique_thread_exit(); + crate::sys::exit::unique_thread_exit(); ret_code }) diff --git a/library/std/src/sync/lazy_lock.rs b/library/std/src/sync/lazy_lock.rs index 7274b5d10c75b..f150d42a3137c 100644 --- a/library/std/src/sync/lazy_lock.rs +++ b/library/std/src/sync/lazy_lock.rs @@ -105,15 +105,6 @@ impl T> LazyLock { LazyLock { once: Once::new(), data: UnsafeCell::new(Data { f: ManuallyDrop::new(f) }) } } - /// Creates a new lazy value that is already initialized. - #[inline] - #[cfg(test)] - pub(crate) fn preinit(value: T) -> LazyLock { - let once = Once::new(); - once.call_once(|| {}); - LazyLock { once, data: UnsafeCell::new(Data { value: ManuallyDrop::new(value) }) } - } - /// Consumes this `LazyLock` returning the stored value. /// /// Returns `Ok(value)` if `Lazy` is initialized and `Err(f)` otherwise. @@ -267,7 +258,7 @@ impl T> LazyLock { // * the closure was not called, but a previous call initialized `value`. // * the closure was not called because the Once is poisoned, which we handled above. // So `value` has definitely been initialized and will not be modified again. - unsafe { &*(*this.data.get()).value } + unsafe { &(*this.data.get()).value } } } @@ -384,7 +375,8 @@ impl T> DerefMut for LazyLock { } #[stable(feature = "lazy_cell", since = "1.80.0")] -impl Default for LazyLock { +#[rustc_const_unstable(feature = "const_default", issue = "143894")] +const impl Default for LazyLock { /// Creates a new lazy value using `Default` as the initializing function. #[inline] fn default() -> LazyLock { @@ -404,6 +396,19 @@ impl fmt::Debug for LazyLock { } } +#[stable(feature = "from_wrapper_impls", since = "1.96.0")] +impl From for LazyLock { + /// Constructs a `LazyLock` that starts already initialized + /// with the provided value. + #[inline] + fn from(value: T) -> Self { + LazyLock { + once: Once::new_complete(), + data: UnsafeCell::new(Data { value: ManuallyDrop::new(value) }), + } + } +} + #[cold] #[inline(never)] fn panic_poisoned() -> ! { diff --git a/library/std/src/sync/mod.rs b/library/std/src/sync/mod.rs index 5da50480c7232..9426d9a684ef6 100644 --- a/library/std/src/sync/mod.rs +++ b/library/std/src/sync/mod.rs @@ -9,7 +9,7 @@ //! Consider the following code, operating on some global static variables: //! //! ```rust -//! // FIXME(static_mut_refs): Do not allow `static_mut_refs` lint +//! // FIXME(static_mut_refs): use raw pointers instead of references //! #![allow(static_mut_refs)] //! //! static mut A: u32 = 0; @@ -164,6 +164,14 @@ //! [`Once`]: crate::sync::Once //! [`OnceLock`]: crate::sync::OnceLock //! [`RwLock`]: crate::sync::RwLock +//! +//! ## Blocking guarantees +//! +//! Methods that are documented not to block will never block for an unbounded length of time. +//! That is, they may internally block through platform primitives but still "behave" like they are non-blocking. This difference is invisible to most programs. +//! +//! This is only of note to platforms which disallow blocking, such as multithreaded WebAssembly on the main thread. +//! None of the implementations in `std::sync` are guaranteed to be (or remain) non-blocking in this regard. #![stable(feature = "rust1", since = "1.0.0")] @@ -172,7 +180,7 @@ // These come from `core` & `alloc` and only in one flavor: no poisoning. #[unstable(feature = "exclusive_wrapper", issue = "98407")] -pub use core::sync::Exclusive; +pub use core::sync::SyncView; #[stable(feature = "rust1", since = "1.0.0")] pub use core::sync::atomic; diff --git a/library/std/src/sync/mpmc/mod.rs b/library/std/src/sync/mpmc/mod.rs index 8df81a580f7b8..a34eabbccb1fc 100644 --- a/library/std/src/sync/mpmc/mod.rs +++ b/library/std/src/sync/mpmc/mod.rs @@ -15,8 +15,9 @@ //! //! 1. An asynchronous, infinitely buffered channel. The [`channel`] function //! will return a `(Sender, Receiver)` tuple where all sends will be -//! **asynchronous** (they never block). The channel conceptually has an -//! infinite buffer. +//! **asynchronous** (they never block for space to become available; see +//! [`std::sync`] for precise guarantees on blocking.) The channel +//! conceptually has an infinite buffer. //! //! 2. A synchronous, bounded channel. The [`sync_channel`] function will //! return a `(Sender, Receiver)` tuple where the storage for pending @@ -26,6 +27,7 @@ //! channel where each sender atomically hands off a message to a receiver. //! //! [`send`]: Sender::send +//! [`std::sync`]: ../index.html#blocking-guarantees //! //! ## Disconnection //! @@ -297,6 +299,7 @@ pub fn sync_channel(cap: usize) -> (Sender, Receiver) { /// assert_eq!(3, msg + msg2); /// ``` #[unstable(feature = "mpmc_channel", issue = "126840")] +#[cfg_attr(not(test), rustc_diagnostic_item = "MpmcSender")] pub struct Sender { flavor: SenderFlavor, } @@ -373,6 +376,11 @@ impl Sender { /// If called on a zero-capacity channel, this method will wait for a receive /// operation to appear on the other side of the channel. /// + /// If called on an unbounded channel, this method will never block in order to wait for space to + /// become available. (See [`std::sync`] for precise guarantees on blocking.) + /// + /// [`std::sync`]: ../index.html#blocking-guarantees + /// /// # Examples /// /// ``` @@ -623,6 +631,33 @@ impl Sender { _ => false, } } + + /// Returns `true` if the channel is disconnected. + /// + /// Note that a return value of `false` does not guarantee the channel will + /// remain connected. The channel may be disconnected immediately after this method + /// returns, so a subsequent [`Sender::send`] may still fail with [`SendError`]. + /// + /// # Examples + /// + /// ``` + /// #![feature(mpmc_channel)] + /// + /// use std::sync::mpmc::channel; + /// + /// let (tx, rx) = channel::(); + /// assert!(!tx.is_disconnected()); + /// drop(rx); + /// assert!(tx.is_disconnected()); + /// ``` + #[unstable(feature = "mpmc_channel", issue = "126840")] + pub fn is_disconnected(&self) -> bool { + match &self.flavor { + SenderFlavor::Array(chan) => chan.is_disconnected(), + SenderFlavor::List(chan) => chan.is_disconnected(), + SenderFlavor::Zero(chan) => chan.is_disconnected(), + } + } } #[unstable(feature = "mpmc_channel", issue = "126840")] @@ -695,6 +730,7 @@ impl fmt::Debug for Sender { /// rx_thread_2.join().unwrap(); /// ``` #[unstable(feature = "mpmc_channel", issue = "126840")] +#[cfg_attr(not(test), rustc_diagnostic_item = "MpmcReceiver")] pub struct Receiver { flavor: ReceiverFlavor, } @@ -741,9 +777,11 @@ pub struct Iter<'a, T: 'a> { /// if the corresponding channel has hung up. /// /// This iterator will never block the caller in order to wait for data to -/// become available. Instead, it will return [`None`]. +/// become available. Instead, it will return [`None`]. (See [`std::sync`] for +/// precise guarantees on blocking.) /// /// [`try_iter`]: Receiver::try_iter +/// [`std::sync`]: ../index.html#blocking-guarantees /// /// # Examples /// @@ -888,7 +926,8 @@ impl Receiver { /// /// This method will never block the caller in order to wait for data to /// become available. Instead, this will always return immediately with a - /// possible option of pending data on the channel. + /// possible option of pending data on the channel. (See [`std::sync`] for precise + /// guarantees on blocking.) /// /// If called on a zero-capacity channel, this method will receive a message only if there /// happens to be a send operation on the other side of the channel at the same time. @@ -900,6 +939,7 @@ impl Receiver { /// (one for disconnection, one for an empty buffer). /// /// [`recv`]: Self::recv + /// [`std::sync`]: ../index.html#blocking-guarantees /// /// # Examples /// @@ -1349,6 +1389,33 @@ impl Receiver { pub fn iter(&self) -> Iter<'_, T> { Iter { rx: self } } + + /// Returns `true` if the channel is disconnected. + /// + /// Note that a return value of `false` does not guarantee the channel will + /// remain connected. The channel may be disconnected immediately after this method + /// returns, so a subsequent [`Receiver::recv`] may still fail with [`RecvError`]. + /// + /// # Examples + /// + /// ``` + /// #![feature(mpmc_channel)] + /// + /// use std::sync::mpmc::channel; + /// + /// let (tx, rx) = channel::(); + /// assert!(!rx.is_disconnected()); + /// drop(tx); + /// assert!(rx.is_disconnected()); + /// ``` + #[unstable(feature = "mpmc_channel", issue = "126840")] + pub fn is_disconnected(&self) -> bool { + match &self.flavor { + ReceiverFlavor::Array(chan) => chan.is_disconnected(), + ReceiverFlavor::List(chan) => chan.is_disconnected(), + ReceiverFlavor::Zero(chan) => chan.is_disconnected(), + } + } } #[unstable(feature = "mpmc_channel", issue = "126840")] diff --git a/library/std/src/sync/mpmc/select.rs b/library/std/src/sync/mpmc/select.rs index 56a83fee2e119..ff537aa686157 100644 --- a/library/std/src/sync/mpmc/select.rs +++ b/library/std/src/sync/mpmc/select.rs @@ -22,7 +22,7 @@ impl Operation { /// and is alive for the entire duration of a blocking operation. #[inline] pub fn hook(r: &mut T) -> Operation { - let val = r as *mut T as usize; + let val = (r as *mut T).addr(); // Make sure that the pointer address doesn't equal the numerical representation of // `Selected::{Waiting, Aborted, Disconnected}`. assert!(val > 2); diff --git a/library/std/src/sync/mpmc/zero.rs b/library/std/src/sync/mpmc/zero.rs index f1ecf80fcb9f6..4f645e16fbb6f 100644 --- a/library/std/src/sync/mpmc/zero.rs +++ b/library/std/src/sync/mpmc/zero.rs @@ -25,7 +25,7 @@ impl Default for ZeroToken { impl fmt::Debug for ZeroToken { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - fmt::Debug::fmt(&(self.0 as usize), f) + fmt::Debug::fmt(&self.0.addr(), f) } } @@ -316,4 +316,10 @@ impl Channel { pub(crate) fn is_full(&self) -> bool { true } + + /// Returns `true` if the channel is disconnected. + pub(crate) fn is_disconnected(&self) -> bool { + let inner = self.inner.lock().unwrap(); + inner.is_disconnected + } } diff --git a/library/std/src/sync/mpsc.rs b/library/std/src/sync/mpsc.rs index 0ae23f6e13bf2..ad74ac2248878 100644 --- a/library/std/src/sync/mpsc.rs +++ b/library/std/src/sync/mpsc.rs @@ -15,8 +15,9 @@ //! //! 1. An asynchronous, infinitely buffered channel. The [`channel`] function //! will return a `(Sender, Receiver)` tuple where all sends will be -//! **asynchronous** (they never block). The channel conceptually has an -//! infinite buffer. +//! **asynchronous** (they never block for space to become available; see +//! [`std::sync`] for precise guarantees on blocking.) The channel +//! conceptually has an infinite buffer. //! //! 2. A synchronous, bounded channel. The [`sync_channel`] function will //! return a `(SyncSender, Receiver)` tuple where the storage for pending @@ -26,6 +27,7 @@ //! channel where each sender atomically hands off a message to a receiver. //! //! [`send`]: Sender::send +//! [`std::sync`]: ../index.html#blocking-guarantees //! //! ## Disconnection //! @@ -142,6 +144,8 @@ // not exposed publicly, but if you are curious about the implementation, // that's where everything is. +use core::clone::Share; + use crate::sync::mpmc; use crate::time::{Duration, Instant}; use crate::{error, fmt}; @@ -173,7 +177,7 @@ use crate::{error, fmt}; /// println!("{}", recv.recv().unwrap()); // Received after 2 seconds /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[cfg_attr(not(test), rustc_diagnostic_item = "Receiver")] +#[cfg_attr(not(test), rustc_diagnostic_item = "MpscReceiver")] pub struct Receiver { inner: mpmc::Receiver, } @@ -226,9 +230,11 @@ pub struct Iter<'a, T: 'a> { /// if the corresponding channel has hung up. /// /// This iterator will never block the caller in order to wait for data to -/// become available. Instead, it will return [`None`]. +/// become available. Instead, it will return [`None`]. (See [`std::sync`] for +/// precise guarantees on blocking.) /// /// [`try_iter`]: Receiver::try_iter +/// [`std::sync`]: ../index.html#blocking-guarantees /// /// # Examples /// @@ -330,6 +336,7 @@ pub struct IntoIter { /// assert_eq!(3, msg + msg2); /// ``` #[stable(feature = "rust1", since = "1.0.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "MpscSender")] pub struct Sender { inner: mpmc::Sender, } @@ -587,7 +594,10 @@ impl Sender { /// will be received. It is possible for the corresponding receiver to /// hang up immediately after this function returns [`Ok`]. /// - /// This method will never block the current thread. + /// This method will never block the caller in order to wait for space to + /// become available. (See [`std::sync`] for precise guarantees on blocking.) + /// + /// [`std::sync`]: ../index.html#blocking-guarantees /// /// # Examples /// @@ -607,6 +617,29 @@ impl Sender { pub fn send(&self, t: T) -> Result<(), SendError> { self.inner.send(t) } + + /// Returns `true` if the channel is disconnected. + /// + /// Note that a return value of `false` does not guarantee the channel will + /// remain connected. The channel may be disconnected immediately after this method + /// returns, so a subsequent [`Sender::send`] may still fail with [`SendError`]. + /// + /// # Examples + /// + /// ``` + /// #![feature(mpsc_is_disconnected)] + /// + /// use std::sync::mpsc::channel; + /// + /// let (tx, rx) = channel::(); + /// assert!(!tx.is_disconnected()); + /// drop(rx); + /// assert!(tx.is_disconnected()); + /// ``` + #[unstable(feature = "mpsc_is_disconnected", issue = "153668")] + pub fn is_disconnected(&self) -> bool { + self.inner.is_disconnected() + } } #[stable(feature = "rust1", since = "1.0.0")] @@ -621,6 +654,9 @@ impl Clone for Sender { } } +#[unstable(feature = "share_trait", issue = "156756")] +impl Share for Sender {} + #[stable(feature = "mpsc_debug", since = "1.8.0")] impl fmt::Debug for Sender { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { @@ -750,6 +786,9 @@ impl Clone for SyncSender { } } +#[unstable(feature = "share_trait", issue = "156756")] +impl Share for SyncSender {} + #[stable(feature = "mpsc_debug", since = "1.8.0")] impl fmt::Debug for SyncSender { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { @@ -766,7 +805,8 @@ impl Receiver { /// /// This method will never block the caller in order to wait for data to /// become available. Instead, this will always return immediately with a - /// possible option of pending data on the channel. + /// possible option of pending data on the channel. (See [`std::sync`] for + /// precise guarantees on blocking.) /// /// This is useful for a flavor of "optimistic check" before deciding to /// block on a receiver. @@ -775,6 +815,7 @@ impl Receiver { /// (one for disconnection, one for an empty buffer). /// /// [`recv`]: Self::recv + /// [`std::sync`]: ../index.html#blocking-guarantees /// /// # Examples /// @@ -1038,6 +1079,29 @@ impl Receiver { pub fn try_iter(&self) -> TryIter<'_, T> { TryIter { rx: self } } + + /// Returns `true` if the channel is disconnected. + /// + /// Note that a return value of `false` does not guarantee the channel will + /// remain connected. The channel may be disconnected immediately after this method + /// returns, so a subsequent [`Receiver::recv`] may still fail with [`RecvError`]. + /// + /// # Examples + /// + /// ``` + /// #![feature(mpsc_is_disconnected)] + /// + /// use std::sync::mpsc::channel; + /// + /// let (tx, rx) = channel::(); + /// assert!(!rx.is_disconnected()); + /// drop(tx); + /// assert!(rx.is_disconnected()); + /// ``` + #[unstable(feature = "mpsc_is_disconnected", issue = "153668")] + pub fn is_disconnected(&self) -> bool { + self.inner.is_disconnected() + } } #[stable(feature = "rust1", since = "1.0.0")] diff --git a/library/std/src/sync/nonpoison/mutex.rs b/library/std/src/sync/nonpoison/mutex.rs index 307bf8eaf512e..ca3a0ada088af 100644 --- a/library/std/src/sync/nonpoison/mutex.rs +++ b/library/std/src/sync/nonpoison/mutex.rs @@ -447,7 +447,7 @@ impl fmt::Debug for Mutex { impl<'mutex, T: ?Sized> MutexGuard<'mutex, T> { unsafe fn new(lock: &'mutex Mutex) -> MutexGuard<'mutex, T> { - return MutexGuard { lock }; + MutexGuard { lock } } } diff --git a/library/std/src/sync/nonpoison/rwlock.rs b/library/std/src/sync/nonpoison/rwlock.rs index dc5d9479ba5a9..19064fdd1ce10 100644 --- a/library/std/src/sync/nonpoison/rwlock.rs +++ b/library/std/src/sync/nonpoison/rwlock.rs @@ -636,7 +636,7 @@ impl<'rwlock, T: ?Sized> RwLockReadGuard<'rwlock, T> { // reference passed to it. If the closure panics, the guard will be dropped. let data = NonNull::from(f(unsafe { orig.data.as_ref() })); let orig = ManuallyDrop::new(orig); - MappedRwLockReadGuard { data, inner_lock: &orig.inner_lock } + MappedRwLockReadGuard { data, inner_lock: orig.inner_lock } } /// Makes a [`MappedRwLockReadGuard`] for a component of the borrowed data. The @@ -668,7 +668,7 @@ impl<'rwlock, T: ?Sized> RwLockReadGuard<'rwlock, T> { Some(data) => { let data = NonNull::from(data); let orig = ManuallyDrop::new(orig); - Ok(MappedRwLockReadGuard { data, inner_lock: &orig.inner_lock }) + Ok(MappedRwLockReadGuard { data, inner_lock: orig.inner_lock }) } None => Err(orig), } @@ -861,7 +861,7 @@ impl<'rwlock, T: ?Sized> MappedRwLockReadGuard<'rwlock, T> { // reference passed to it. If the closure panics, the guard will be dropped. let data = NonNull::from(f(unsafe { orig.data.as_ref() })); let orig = ManuallyDrop::new(orig); - MappedRwLockReadGuard { data, inner_lock: &orig.inner_lock } + MappedRwLockReadGuard { data, inner_lock: orig.inner_lock } } /// Makes a [`MappedRwLockReadGuard`] for a component of the borrowed data. @@ -893,7 +893,7 @@ impl<'rwlock, T: ?Sized> MappedRwLockReadGuard<'rwlock, T> { Some(data) => { let data = NonNull::from(data); let orig = ManuallyDrop::new(orig); - Ok(MappedRwLockReadGuard { data, inner_lock: &orig.inner_lock }) + Ok(MappedRwLockReadGuard { data, inner_lock: orig.inner_lock }) } None => Err(orig), } diff --git a/library/std/src/sync/once.rs b/library/std/src/sync/once.rs index bcfc9f581fd28..d37e57e399660 100644 --- a/library/std/src/sync/once.rs +++ b/library/std/src/sync/once.rs @@ -84,6 +84,13 @@ impl Once { Once { inner: sys::Once::new() } } + /// Creates a new `Once` value that starts already completed. + #[inline] + #[must_use] + pub(crate) const fn new_complete() -> Once { + Once { inner: sys::Once::new_complete() } + } + /// Performs an initialization routine once and only once. The given closure /// will be executed if this is the first time `call_once` has been called, /// and otherwise the routine will *not* be invoked. @@ -289,6 +296,7 @@ impl Once { /// If this [`Once`] has been poisoned because an initialization closure has /// panicked, this method will also panic. Use [`wait_force`](Self::wait_force) /// if this behavior is not desired. + #[inline] #[stable(feature = "once_wait", since = "1.86.0")] #[rustc_should_not_be_called_on_const_items] pub fn wait(&self) { @@ -302,6 +310,7 @@ impl Once { /// /// If this [`Once`] has been poisoned, this function blocks until it /// becomes completed, unlike [`Once::wait()`], which panics in this case. + #[inline] #[stable(feature = "once_wait", since = "1.86.0")] #[rustc_should_not_be_called_on_const_items] pub fn wait_force(&self) { diff --git a/library/std/src/sync/once_lock.rs b/library/std/src/sync/once_lock.rs index f6ea3c1a039b2..4b41fc4587829 100644 --- a/library/std/src/sync/once_lock.rs +++ b/library/std/src/sync/once_lock.rs @@ -145,6 +145,35 @@ impl OnceLock { } } + /// Creates a new initialized cell. + /// + /// This is equivalent to `OnceLock::from(value)`, but can be used in + /// const contexts, unlike the `From` implementation. + /// + /// # Examples + /// + /// ``` + /// #![feature(once_lock_new_init)] + /// use std::sync::OnceLock; + /// + /// static CELL: OnceLock = OnceLock::new_init(1); + /// + /// assert_eq!(CELL.get(), Some(&1)); + /// + /// // Already initialized, so this closure never runs. + /// assert_eq!(CELL.get_or_init(|| panic!("Kaboom!")), &1); + /// ``` + #[inline] + #[must_use] + #[unstable(feature = "once_lock_new_init", issue = "159860")] + pub const fn new_init(init_value: T) -> OnceLock { + OnceLock { + once: Once::new_complete(), + value: UnsafeCell::new(MaybeUninit::new(init_value)), + _marker: PhantomData, + } + } + /// Gets the reference to the underlying value. /// /// Returns `None` if the cell is uninitialized, or being initialized. @@ -592,7 +621,7 @@ impl UnwindSafe for OnceLock {} #[stable(feature = "once_cell", since = "1.70.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for OnceLock { +const impl Default for OnceLock { /// Creates a new uninitialized cell. /// /// # Example @@ -626,14 +655,7 @@ impl fmt::Debug for OnceLock { impl Clone for OnceLock { #[inline] fn clone(&self) -> OnceLock { - let cell = Self::new(); - if let Some(value) = self.get() { - match cell.set(value.clone()) { - Ok(()) => (), - Err(_) => unreachable!(), - } - } - cell + self.get().cloned().map_or_default(Self::from) } } @@ -656,10 +678,10 @@ impl From for OnceLock { /// ``` #[inline] fn from(value: T) -> Self { - let cell = Self::new(); - match cell.set(value) { - Ok(()) => cell, - Err(_) => unreachable!(), + OnceLock { + once: Once::new_complete(), + value: UnsafeCell::new(MaybeUninit::new(value)), + _marker: PhantomData, } } } diff --git a/library/std/src/sync/poison.rs b/library/std/src/sync/poison.rs index 9f40c01546632..3c32ec34dee5b 100644 --- a/library/std/src/sync/poison.rs +++ b/library/std/src/sync/poison.rs @@ -57,9 +57,6 @@ //! //! [`Once`]: crate::sync::Once -// If we are not unwinding, `PoisonError` is uninhabited. -#![cfg_attr(not(panic = "unwind"), expect(unreachable_code))] - #[stable(feature = "rust1", since = "1.0.0")] pub use self::condvar::Condvar; #[unstable(feature = "mapped_lock_guards", issue = "117108")] @@ -266,6 +263,7 @@ impl PoisonError { /// or [`RwLock::read`](crate::sync::RwLock::read). /// /// This method may panic if std was built with `panic="abort"`. + #[doc(auto_cfg = false)] #[cfg(panic = "unwind")] #[stable(feature = "sync_poison", since = "1.2.0")] pub fn new(data: T) -> PoisonError { @@ -278,6 +276,7 @@ impl PoisonError { /// or [`RwLock::read`](crate::sync::RwLock::read). /// /// This method may panic if std was built with `panic="abort"`. + #[doc(auto_cfg = false)] #[cfg(not(panic = "unwind"))] #[stable(feature = "sync_poison", since = "1.2.0")] #[track_caller] diff --git a/library/std/src/sync/poison/rwlock.rs b/library/std/src/sync/poison/rwlock.rs index acfeb96900cc9..de1fedf88f63a 100644 --- a/library/std/src/sync/poison/rwlock.rs +++ b/library/std/src/sync/poison/rwlock.rs @@ -16,7 +16,7 @@ use crate::sys::sync as sys; /// /// In comparison, a [`Mutex`] does not distinguish between readers or writers /// that acquire the lock, therefore blocking any threads waiting for the lock to -/// become available. An `RwLock` will allow any number of readers to acquire the +/// become available. An `RwLock` will allow multiple readers to acquire the /// lock as long as a writer is not holding the lock. /// /// The priority policy of the lock is dependent on the underlying operating @@ -56,24 +56,36 @@ use crate::sys::sync as sys; /// # Examples /// /// ``` -/// use std::sync::RwLock; +/// use std::sync::{Arc, RwLock}; +/// use std::thread; +/// use std::time::Duration; /// -/// let lock = RwLock::new(5); +/// let data = Arc::new(RwLock::new(5)); /// -/// // many reader locks can be held at once -/// { -/// let r1 = lock.read().unwrap(); -/// let r2 = lock.read().unwrap(); -/// assert_eq!(*r1, 5); -/// assert_eq!(*r2, 5); -/// } // read locks are dropped at this point +/// // Multiple readers can access in parallel. +/// for i in 0..3 { +/// let lock_clone = Arc::clone(&data); /// -/// // only one write lock may be held, however -/// { -/// let mut w = lock.write().unwrap(); -/// *w += 1; -/// assert_eq!(*w, 6); -/// } // write lock is dropped here +/// thread::spawn(move || { +/// let value = lock_clone.read().unwrap(); +/// +/// println!("Reader {}: Read value {}, now holding lock...", i, *value); +/// +/// // Simulating a long read operation +/// thread::sleep(Duration::from_secs(1)); +/// +/// println!("Reader {}: Dropping lock.", i); +/// // Read lock unlocked when going out of scope. +/// }); +/// } +/// +/// thread::sleep(Duration::from_millis(100)); // Wait for readers to start +/// +/// // While all readers can proceed, a call to .write() has to wait for +// // current active reader locks. +/// let mut writable_data = data.write().unwrap(); +/// println!("Writer proceeds..."); +/// *writable_data += 1; /// ``` /// /// [`Mutex`]: super::Mutex @@ -370,7 +382,8 @@ impl RwLock { /// /// # Panics /// - /// This function might panic when called if the lock is already held by the current thread. + /// This function might panic when called if the lock is already held by the current thread + /// in read or write mode. /// /// # Examples /// @@ -467,7 +480,8 @@ impl RwLock { /// /// # Panics /// - /// This function might panic when called if the lock is already held by the current thread. + /// This function might panic when called if the lock is already held by the current thread + /// in read or write mode. /// /// # Examples /// @@ -756,7 +770,7 @@ impl<'rwlock, T: ?Sized> RwLockReadGuard<'rwlock, T> { // reference passed to it. If the closure panics, the guard will be dropped. let data = NonNull::from(f(unsafe { orig.data.as_ref() })); let orig = ManuallyDrop::new(orig); - MappedRwLockReadGuard { data, inner_lock: &orig.inner_lock } + MappedRwLockReadGuard { data, inner_lock: orig.inner_lock } } /// Makes a [`MappedRwLockReadGuard`] for a component of the borrowed data. The @@ -788,7 +802,7 @@ impl<'rwlock, T: ?Sized> RwLockReadGuard<'rwlock, T> { Some(data) => { let data = NonNull::from(data); let orig = ManuallyDrop::new(orig); - Ok(MappedRwLockReadGuard { data, inner_lock: &orig.inner_lock }) + Ok(MappedRwLockReadGuard { data, inner_lock: orig.inner_lock }) } None => Err(orig), } @@ -982,7 +996,7 @@ impl<'rwlock, T: ?Sized> MappedRwLockReadGuard<'rwlock, T> { // reference passed to it. If the closure panics, the guard will be dropped. let data = NonNull::from(f(unsafe { orig.data.as_ref() })); let orig = ManuallyDrop::new(orig); - MappedRwLockReadGuard { data, inner_lock: &orig.inner_lock } + MappedRwLockReadGuard { data, inner_lock: orig.inner_lock } } /// Makes a [`MappedRwLockReadGuard`] for a component of the borrowed data. @@ -1014,7 +1028,7 @@ impl<'rwlock, T: ?Sized> MappedRwLockReadGuard<'rwlock, T> { Some(data) => { let data = NonNull::from(data); let orig = ManuallyDrop::new(orig); - Ok(MappedRwLockReadGuard { data, inner_lock: &orig.inner_lock }) + Ok(MappedRwLockReadGuard { data, inner_lock: orig.inner_lock }) } None => Err(orig), } diff --git a/library/std/src/sync/reentrant_lock.rs b/library/std/src/sync/reentrant_lock.rs index f560b616dd922..fd8a2507f68fd 100644 --- a/library/std/src/sync/reentrant_lock.rs +++ b/library/std/src/sync/reentrant_lock.rs @@ -87,7 +87,8 @@ pub struct ReentrantLock { cfg_select!( target_has_atomic = "64" => { - use crate::sync::atomic::{Atomic, AtomicU64, Ordering::Relaxed}; + use crate::sync::atomic::Ordering::Relaxed; + use crate::sync::atomic::{Atomic, AtomicU64}; struct Tid(Atomic); @@ -118,11 +119,7 @@ cfg_select!( X.with(|p| <*const u8>::addr(p)) } - use crate::sync::atomic::{ - Atomic, - AtomicUsize, - Ordering, - }; + use crate::sync::atomic::{Atomic, AtomicUsize, Ordering}; struct Tid { // When a thread calls `set()`, this value gets updated to diff --git a/library/std/src/sys/alloc/hermit.rs b/library/std/src/sys/alloc/hermit.rs index 77f8200a70a64..9afcb315f4ab5 100644 --- a/library/std/src/sys/alloc/hermit.rs +++ b/library/std/src/sys/alloc/hermit.rs @@ -1,27 +1,24 @@ -use crate::alloc::{GlobalAlloc, Layout, System}; +use crate::alloc::Layout; -#[stable(feature = "alloc_system_type", since = "1.28.0")] -unsafe impl GlobalAlloc for System { - #[inline] - unsafe fn alloc(&self, layout: Layout) -> *mut u8 { - let size = layout.size(); - let align = layout.align(); - unsafe { hermit_abi::malloc(size, align) } - } +#[inline] +pub unsafe fn alloc(layout: Layout) -> *mut u8 { + let size = layout.size(); + let align = layout.align(); + unsafe { hermit_abi::malloc(size, align) } +} - #[inline] - unsafe fn dealloc(&self, ptr: *mut u8, layout: Layout) { - let size = layout.size(); - let align = layout.align(); - unsafe { - hermit_abi::free(ptr, size, align); - } +#[inline] +pub unsafe fn dealloc(ptr: *mut u8, layout: Layout) { + let size = layout.size(); + let align = layout.align(); + unsafe { + hermit_abi::free(ptr, size, align); } +} - #[inline] - unsafe fn realloc(&self, ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { - let size = layout.size(); - let align = layout.align(); - unsafe { hermit_abi::realloc(ptr, size, align, new_size) } - } +#[inline] +pub unsafe fn realloc(ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { + let size = layout.size(); + let align = layout.align(); + unsafe { hermit_abi::realloc(ptr, size, align, new_size) } } diff --git a/library/std/src/sys/alloc/mod.rs b/library/std/src/sys/alloc/mod.rs index f2f1d1c7feceb..66a2c3be33cba 100644 --- a/library/std/src/sys/alloc/mod.rs +++ b/library/std/src/sys/alloc/mod.rs @@ -1,6 +1,6 @@ #![forbid(unsafe_op_in_unsafe_fn)] -use crate::alloc::{GlobalAlloc, Layout, System}; +use crate::alloc::Layout; use crate::ptr; // The minimum alignment guaranteed by the architecture. This value is used to @@ -47,21 +47,16 @@ const MIN_ALIGN: usize = if cfg!(any( }; #[allow(dead_code)] -unsafe fn realloc_fallback( - alloc: &System, - ptr: *mut u8, - old_layout: Layout, - new_size: usize, -) -> *mut u8 { +unsafe fn realloc_fallback(ptr: *mut u8, old_layout: Layout, new_size: usize) -> *mut u8 { // SAFETY: Docs for GlobalAlloc::realloc require this to be valid unsafe { let new_layout = Layout::from_size_align_unchecked(new_size, old_layout.align()); - let new_ptr = GlobalAlloc::alloc(alloc, new_layout); + let new_ptr = alloc(new_layout); if !new_ptr.is_null() { let size = usize::min(old_layout.size(), new_size); ptr::copy_nonoverlapping(ptr, new_ptr, size); - GlobalAlloc::dealloc(alloc, ptr, old_layout); + dealloc(ptr, old_layout); } new_ptr @@ -69,42 +64,66 @@ unsafe fn realloc_fallback( } cfg_select! { - any( - target_family = "unix", - target_os = "wasi", - target_os = "teeos", - target_os = "trusty", - ) => { + any(target_family = "unix", target_os = "wasi", target_os = "teeos", target_os = "trusty") => { mod unix; + use unix as imp; } target_os = "windows" => { mod windows; + use windows as imp; } target_os = "hermit" => { mod hermit; + use hermit as imp; } target_os = "motor" => { mod motor; + use motor as imp; } all(target_vendor = "fortanix", target_env = "sgx") => { mod sgx; + use sgx as imp; } target_os = "solid_asp3" => { mod solid; + use solid as imp; } target_os = "uefi" => { mod uefi; + use uefi as imp; } target_os = "vexos" => { mod vexos; + use vexos as imp; } target_family = "wasm" => { mod wasm; + use wasm as imp; } target_os = "xous" => { mod xous; + use xous as imp; } target_os = "zkvm" => { mod zkvm; + use zkvm as imp; + } +} + +pub use imp::{alloc, dealloc, realloc}; + +cfg_select! { + any(target_os = "hermit", target_os = "solid_asp3", target_os = "uefi", target_os = "zkvm") => { + #[inline] + pub unsafe fn alloc_zeroed(layout: Layout) -> *mut u8 { + let ptr = unsafe { alloc(layout) }; + if !ptr.is_null() { + unsafe { ptr.write_bytes(0, layout.size()) }; + } + ptr + } + } + _ => { + pub use imp::alloc_zeroed; } } diff --git a/library/std/src/sys/alloc/motor.rs b/library/std/src/sys/alloc/motor.rs index 271e3c40c26ae..090dc198bb500 100644 --- a/library/std/src/sys/alloc/motor.rs +++ b/library/std/src/sys/alloc/motor.rs @@ -1,28 +1,13 @@ -use crate::alloc::{GlobalAlloc, Layout, System}; +use crate::alloc::Layout; -#[stable(feature = "alloc_system_type", since = "1.28.0")] -unsafe impl GlobalAlloc for System { - #[inline] - unsafe fn alloc(&self, layout: Layout) -> *mut u8 { - // SAFETY: same requirements as in GlobalAlloc::alloc. - moto_rt::alloc::alloc(layout) - } - - #[inline] - unsafe fn alloc_zeroed(&self, layout: Layout) -> *mut u8 { - // SAFETY: same requirements as in GlobalAlloc::alloc_zeroed. - moto_rt::alloc::alloc_zeroed(layout) - } - - #[inline] - unsafe fn dealloc(&self, ptr: *mut u8, layout: Layout) { - // SAFETY: same requirements as in GlobalAlloc::dealloc. - unsafe { moto_rt::alloc::dealloc(ptr, layout) } - } +#[inline] +pub unsafe fn alloc(layout: Layout) -> *mut u8 { + moto_rt::alloc::alloc(layout) +} - #[inline] - unsafe fn realloc(&self, ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { - // SAFETY: same requirements as in GlobalAlloc::realloc. - unsafe { moto_rt::alloc::realloc(ptr, layout, new_size) } - } +#[inline] +pub unsafe fn alloc_zeroed(layout: Layout) -> *mut u8 { + moto_rt::alloc::alloc_zeroed(layout) } + +pub use moto_rt::alloc::{dealloc, realloc}; diff --git a/library/std/src/sys/alloc/sgx.rs b/library/std/src/sys/alloc/sgx.rs index afdef7a5cb647..c20761259048e 100644 --- a/library/std/src/sys/alloc/sgx.rs +++ b/library/std/src/sys/alloc/sgx.rs @@ -1,4 +1,4 @@ -use crate::alloc::{GlobalAlloc, Layout, System}; +use crate::alloc::Layout; use crate::ptr; use crate::sync::atomic::{Atomic, AtomicBool, Ordering}; use crate::sys::pal::abi::mem as sgx_mem; @@ -57,31 +57,28 @@ unsafe impl dlmalloc::Allocator for Sgx { } } -#[stable(feature = "alloc_system_type", since = "1.28.0")] -unsafe impl GlobalAlloc for System { - #[inline] - unsafe fn alloc(&self, layout: Layout) -> *mut u8 { - // SAFETY: the caller must uphold the safety contract for `malloc` - unsafe { DLMALLOC.lock().malloc(layout.size(), layout.align()) } - } +#[inline] +pub unsafe fn alloc(layout: Layout) -> *mut u8 { + // SAFETY: the caller must uphold the safety contract for `malloc` + unsafe { DLMALLOC.lock().malloc(layout.size(), layout.align()) } +} - #[inline] - unsafe fn alloc_zeroed(&self, layout: Layout) -> *mut u8 { - // SAFETY: the caller must uphold the safety contract for `malloc` - unsafe { DLMALLOC.lock().calloc(layout.size(), layout.align()) } - } +#[inline] +pub unsafe fn alloc_zeroed(layout: Layout) -> *mut u8 { + // SAFETY: the caller must uphold the safety contract for `malloc` + unsafe { DLMALLOC.lock().calloc(layout.size(), layout.align()) } +} - #[inline] - unsafe fn dealloc(&self, ptr: *mut u8, layout: Layout) { - // SAFETY: the caller must uphold the safety contract for `malloc` - unsafe { DLMALLOC.lock().free(ptr, layout.size(), layout.align()) } - } +#[inline] +pub unsafe fn dealloc(ptr: *mut u8, layout: Layout) { + // SAFETY: the caller must uphold the safety contract for `malloc` + unsafe { DLMALLOC.lock().free(ptr, layout.size(), layout.align()) } +} - #[inline] - unsafe fn realloc(&self, ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { - // SAFETY: the caller must uphold the safety contract for `malloc` - unsafe { DLMALLOC.lock().realloc(ptr, layout.size(), layout.align(), new_size) } - } +#[inline] +pub unsafe fn realloc(ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { + // SAFETY: the caller must uphold the safety contract for `malloc` + unsafe { DLMALLOC.lock().realloc(ptr, layout.size(), layout.align(), new_size) } } // The following functions are needed by libunwind. These symbols are named diff --git a/library/std/src/sys/alloc/solid.rs b/library/std/src/sys/alloc/solid.rs index 47cfa2eb1162b..5d3f396f0dd11 100644 --- a/library/std/src/sys/alloc/solid.rs +++ b/library/std/src/sys/alloc/solid.rs @@ -1,30 +1,27 @@ use super::{MIN_ALIGN, realloc_fallback}; -use crate::alloc::{GlobalAlloc, Layout, System}; +use crate::alloc::Layout; -#[stable(feature = "alloc_system_type", since = "1.28.0")] -unsafe impl GlobalAlloc for System { - #[inline] - unsafe fn alloc(&self, layout: Layout) -> *mut u8 { - if layout.align() <= MIN_ALIGN && layout.align() <= layout.size() { - unsafe { libc::malloc(layout.size()) as *mut u8 } - } else { - unsafe { libc::memalign(layout.align(), layout.size()) as *mut u8 } - } +#[inline] +pub unsafe fn alloc(layout: Layout) -> *mut u8 { + if layout.align() <= MIN_ALIGN && layout.align() <= layout.size() { + unsafe { libc::malloc(layout.size()) as *mut u8 } + } else { + unsafe { libc::memalign(layout.align(), layout.size()) as *mut u8 } } +} - #[inline] - unsafe fn dealloc(&self, ptr: *mut u8, _layout: Layout) { - unsafe { libc::free(ptr as *mut libc::c_void) } - } +#[inline] +pub unsafe fn dealloc(ptr: *mut u8, _layout: Layout) { + unsafe { libc::free(ptr as *mut libc::c_void) } +} - #[inline] - unsafe fn realloc(&self, ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { - unsafe { - if layout.align() <= MIN_ALIGN && layout.align() <= new_size { - libc::realloc(ptr as *mut libc::c_void, new_size) as *mut u8 - } else { - realloc_fallback(self, ptr, layout, new_size) - } +#[inline] +pub unsafe fn realloc(ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { + unsafe { + if layout.align() <= MIN_ALIGN && layout.align() <= new_size { + libc::realloc(ptr as *mut libc::c_void, new_size) as *mut u8 + } else { + realloc_fallback(ptr, layout, new_size) } } } diff --git a/library/std/src/sys/alloc/uefi.rs b/library/std/src/sys/alloc/uefi.rs index 5221876e90866..aa7fcc9fe110c 100644 --- a/library/std/src/sys/alloc/uefi.rs +++ b/library/std/src/sys/alloc/uefi.rs @@ -3,47 +3,48 @@ use r_efi::protocols::loaded_image; -use crate::alloc::{GlobalAlloc, Layout, System}; +use crate::alloc::Layout; use crate::sync::OnceLock; use crate::sys::pal::helpers; -#[stable(feature = "alloc_system_type", since = "1.28.0")] -unsafe impl GlobalAlloc for System { - unsafe fn alloc(&self, layout: Layout) -> *mut u8 { - static EFI_MEMORY_TYPE: OnceLock = OnceLock::new(); - - // Return null pointer if boot services are not available - if crate::os::uefi::env::boot_services().is_none() { - return crate::ptr::null_mut(); - } - - // If boot services is valid then SystemTable is not null. - let system_table = crate::os::uefi::env::system_table().as_ptr().cast(); - - // Each loaded image has an image handle that supports `EFI_LOADED_IMAGE_PROTOCOL`. Thus, this - // will never fail. - let mem_type = EFI_MEMORY_TYPE.get_or_init(|| { - let protocol = helpers::image_handle_protocol::( - loaded_image::PROTOCOL_GUID, - ) - .unwrap(); - // Gives allocations the memory type that the data sections were loaded as. - unsafe { (*protocol.as_ptr()).image_data_type } - }); - - // The caller must ensure non-0 layout - unsafe { r_efi_alloc::raw::alloc(system_table, layout, *mem_type) } +pub unsafe fn alloc(layout: Layout) -> *mut u8 { + static EFI_MEMORY_TYPE: OnceLock = OnceLock::new(); + + // Return null pointer if boot services are not available + if crate::os::uefi::env::boot_services().is_none() { + return crate::ptr::null_mut(); } - unsafe fn dealloc(&self, ptr: *mut u8, layout: Layout) { - // Do nothing if boot services are not available - if crate::os::uefi::env::boot_services().is_none() { - return; - } + // If boot services is valid then SystemTable is not null. + let system_table = crate::os::uefi::env::system_table().as_ptr().cast(); + + // Each loaded image has an image handle that supports `EFI_LOADED_IMAGE_PROTOCOL`. Thus, this + // will never fail. + let mem_type = EFI_MEMORY_TYPE.get_or_init(|| { + let protocol = + helpers::image_handle_protocol::(loaded_image::PROTOCOL_GUID) + .unwrap(); + // Gives allocations the memory type that the data sections were loaded as. + unsafe { (*protocol.as_ptr()).image_data_type } + }); + + // The caller must ensure non-0 layout + unsafe { r_efi_alloc::raw::alloc(system_table, layout, *mem_type) } +} - // If boot services is valid then SystemTable is not null. - let system_table = crate::os::uefi::env::system_table().as_ptr().cast(); - // The caller must ensure non-0 layout - unsafe { r_efi_alloc::raw::dealloc(system_table, ptr, layout) } +pub unsafe fn dealloc(ptr: *mut u8, layout: Layout) { + // Do nothing if boot services are not available + if crate::os::uefi::env::boot_services().is_none() { + return; } + + // If boot services is valid then SystemTable is not null. + let system_table = crate::os::uefi::env::system_table().as_ptr().cast(); + // The caller must ensure non-0 layout + unsafe { r_efi_alloc::raw::dealloc(system_table, ptr, layout) } +} + +pub unsafe fn realloc(ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { + // SAFETY: this is just a `pub` wrapper. + unsafe { super::realloc_fallback(ptr, layout, new_size) } } diff --git a/library/std/src/sys/alloc/unix.rs b/library/std/src/sys/alloc/unix.rs index 3d369b08abc77..2411ca0a48c48 100644 --- a/library/std/src/sys/alloc/unix.rs +++ b/library/std/src/sys/alloc/unix.rs @@ -1,60 +1,76 @@ use super::{MIN_ALIGN, realloc_fallback}; -use crate::alloc::{GlobalAlloc, Layout, System}; +use crate::alloc::Layout; use crate::ptr; -#[stable(feature = "alloc_system_type", since = "1.28.0")] -unsafe impl GlobalAlloc for System { - #[inline] - unsafe fn alloc(&self, layout: Layout) -> *mut u8 { - // jemalloc provides alignment less than MIN_ALIGN for small allocations. - // So only rely on MIN_ALIGN if size >= align. - // Also see and - // . - if layout.align() <= MIN_ALIGN && layout.align() <= layout.size() { - unsafe { libc::malloc(layout.size()) as *mut u8 } - } else { - // `posix_memalign` returns a non-aligned value if supplied a very - // large alignment on older versions of Apple's platforms (unknown - // exactly which version range, but the issue is definitely - // present in macOS 10.14 and iOS 13.3). - // - // - #[cfg(target_vendor = "apple")] - { - if layout.align() > (1 << 31) { - return ptr::null_mut(); - } - } - unsafe { aligned_malloc(&layout) } - } +// Used by rustc for checking the definitions of other function with the same symbol names +// +// See the `invalid_runtime_symbols_definitions` lint. +#[cfg(not(test))] +mod runtime_symbols { + use core::ffi::{c_size_t, c_void}; + + unsafe extern "C" { + #[rustc_canonical_symbol] + fn malloc(size: c_size_t) -> *mut c_void; + + #[rustc_canonical_symbol] + fn realloc(ptr: *mut c_void, size: c_size_t) -> *mut c_void; + + #[rustc_canonical_symbol] + fn free(ptr: *mut c_void); } +} - #[inline] - unsafe fn alloc_zeroed(&self, layout: Layout) -> *mut u8 { - // See the comment above in `alloc` for why this check looks the way it does. - if layout.align() <= MIN_ALIGN && layout.align() <= layout.size() { - unsafe { libc::calloc(layout.size(), 1) as *mut u8 } - } else { - let ptr = unsafe { self.alloc(layout) }; - if !ptr.is_null() { - unsafe { ptr::write_bytes(ptr, 0, layout.size()) }; +#[inline] +pub unsafe fn alloc(layout: Layout) -> *mut u8 { + // jemalloc provides alignment less than MIN_ALIGN for small allocations. + // So only rely on MIN_ALIGN if size >= align. + // Also see and + // . + if layout.align() <= MIN_ALIGN && layout.align() <= layout.size() { + unsafe { libc::malloc(layout.size()) as *mut u8 } + } else { + // `posix_memalign` returns a non-aligned value if supplied a very + // large alignment on older versions of Apple's platforms (unknown + // exactly which version range, but the issue is definitely + // present in macOS 10.14 and iOS 13.3). + // + // + #[cfg(target_vendor = "apple")] + { + if layout.align() > (1 << 31) { + return ptr::null_mut(); } - ptr } + unsafe { aligned_malloc(&layout) } } +} - #[inline] - unsafe fn dealloc(&self, ptr: *mut u8, _layout: Layout) { - unsafe { libc::free(ptr as *mut libc::c_void) } +#[inline] +pub unsafe fn alloc_zeroed(layout: Layout) -> *mut u8 { + // See the comment above in `alloc` for why this check looks the way it does. + if layout.align() <= MIN_ALIGN && layout.align() <= layout.size() { + unsafe { libc::calloc(layout.size(), 1) as *mut u8 } + } else { + let ptr = unsafe { alloc(layout) }; + if !ptr.is_null() { + unsafe { ptr::write_bytes(ptr, 0, layout.size()) }; + } + ptr } +} - #[inline] - unsafe fn realloc(&self, ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { - if layout.align() <= MIN_ALIGN && layout.align() <= new_size { - unsafe { libc::realloc(ptr as *mut libc::c_void, new_size) as *mut u8 } - } else { - unsafe { realloc_fallback(self, ptr, layout, new_size) } - } +#[inline] +pub unsafe fn dealloc(ptr: *mut u8, _layout: Layout) { + unsafe { libc::free(ptr as *mut libc::c_void) } +} + +#[inline] +pub unsafe fn realloc(ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { + if layout.align() <= MIN_ALIGN && layout.align() <= new_size { + unsafe { libc::realloc(ptr as *mut libc::c_void, new_size) as *mut u8 } + } else { + unsafe { realloc_fallback(ptr, layout, new_size) } } } diff --git a/library/std/src/sys/alloc/vexos.rs b/library/std/src/sys/alloc/vexos.rs index c1fb6896a89ae..6aba6dc474911 100644 --- a/library/std/src/sys/alloc/vexos.rs +++ b/library/std/src/sys/alloc/vexos.rs @@ -1,7 +1,7 @@ -// FIXME(static_mut_refs): Do not allow `static_mut_refs` lint +// FIXME(static_mut_refs): use raw pointers instead of references #![allow(static_mut_refs)] -use crate::alloc::{GlobalAlloc, Layout, System}; +use crate::alloc::Layout; use crate::ptr; use crate::sync::atomic::{AtomicBool, Ordering}; @@ -60,37 +60,34 @@ unsafe impl dlmalloc::Allocator for Vexos { } } -#[stable(feature = "alloc_system_type", since = "1.28.0")] -unsafe impl GlobalAlloc for System { - #[inline] - unsafe fn alloc(&self, layout: Layout) -> *mut u8 { - // SAFETY: DLMALLOC access is guaranteed to be safe because we are a single-threaded target, which - // guarantees unique and non-reentrant access to the allocator. As such, no allocator lock is used. - // Calling malloc() is safe because preconditions on this function match the trait method preconditions. - unsafe { DLMALLOC.malloc(layout.size(), layout.align()) } - } +#[inline] +pub unsafe fn alloc(layout: Layout) -> *mut u8 { + // SAFETY: DLMALLOC access is guaranteed to be safe because we are a single-threaded target, which + // guarantees unique and non-reentrant access to the allocator. As such, no allocator lock is used. + // Calling malloc() is safe because preconditions on this function match the trait method preconditions. + unsafe { DLMALLOC.malloc(layout.size(), layout.align()) } +} - #[inline] - unsafe fn alloc_zeroed(&self, layout: Layout) -> *mut u8 { - // SAFETY: DLMALLOC access is guaranteed to be safe because we are a single-threaded target, which - // guarantees unique and non-reentrant access to the allocator. As such, no allocator lock is used. - // Calling calloc() is safe because preconditions on this function match the trait method preconditions. - unsafe { DLMALLOC.calloc(layout.size(), layout.align()) } - } +#[inline] +pub unsafe fn alloc_zeroed(layout: Layout) -> *mut u8 { + // SAFETY: DLMALLOC access is guaranteed to be safe because we are a single-threaded target, which + // guarantees unique and non-reentrant access to the allocator. As such, no allocator lock is used. + // Calling calloc() is safe because preconditions on this function match the trait method preconditions. + unsafe { DLMALLOC.calloc(layout.size(), layout.align()) } +} - #[inline] - unsafe fn dealloc(&self, ptr: *mut u8, layout: Layout) { - // SAFETY: DLMALLOC access is guaranteed to be safe because we are a single-threaded target, which - // guarantees unique and non-reentrant access to the allocator. As such, no allocator lock is used. - // Calling free() is safe because preconditions on this function match the trait method preconditions. - unsafe { DLMALLOC.free(ptr, layout.size(), layout.align()) } - } +#[inline] +pub unsafe fn dealloc(ptr: *mut u8, layout: Layout) { + // SAFETY: DLMALLOC access is guaranteed to be safe because we are a single-threaded target, which + // guarantees unique and non-reentrant access to the allocator. As such, no allocator lock is used. + // Calling free() is safe because preconditions on this function match the trait method preconditions. + unsafe { DLMALLOC.free(ptr, layout.size(), layout.align()) } +} - #[inline] - unsafe fn realloc(&self, ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { - // SAFETY: DLMALLOC access is guaranteed to be safe because we are a single-threaded target, which - // guarantees unique and non-reentrant access to the allocator. As such, no allocator lock is used. - // Calling realloc() is safe because preconditions on this function match the trait method preconditions. - unsafe { DLMALLOC.realloc(ptr, layout.size(), layout.align(), new_size) } - } +#[inline] +pub unsafe fn realloc(ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { + // SAFETY: DLMALLOC access is guaranteed to be safe because we are a single-threaded target, which + // guarantees unique and non-reentrant access to the allocator. As such, no allocator lock is used. + // Calling realloc() is safe because preconditions on this function match the trait method preconditions. + unsafe { DLMALLOC.realloc(ptr, layout.size(), layout.align(), new_size) } } diff --git a/library/std/src/sys/alloc/wasm.rs b/library/std/src/sys/alloc/wasm.rs index 48e2fdd4eccec..995230aebaa01 100644 --- a/library/std/src/sys/alloc/wasm.rs +++ b/library/std/src/sys/alloc/wasm.rs @@ -18,7 +18,7 @@ use core::cell::SyncUnsafeCell; -use crate::alloc::{GlobalAlloc, Layout, System}; +use crate::alloc::Layout; struct SyncDlmalloc(dlmalloc::Dlmalloc); unsafe impl Sync for SyncDlmalloc {} @@ -26,39 +26,36 @@ unsafe impl Sync for SyncDlmalloc {} static DLMALLOC: SyncUnsafeCell = SyncUnsafeCell::new(SyncDlmalloc(dlmalloc::Dlmalloc::new())); -#[stable(feature = "alloc_system_type", since = "1.28.0")] -unsafe impl GlobalAlloc for System { - #[inline] - unsafe fn alloc(&self, layout: Layout) -> *mut u8 { - // SAFETY: DLMALLOC access is guaranteed to be safe because the lock gives us unique and non-reentrant access. - // Calling malloc() is safe because preconditions on this function match the trait method preconditions. - let _lock = lock::lock(); - unsafe { (*DLMALLOC.get()).0.malloc(layout.size(), layout.align()) } - } +#[inline] +pub unsafe fn alloc(layout: Layout) -> *mut u8 { + // SAFETY: DLMALLOC access is guaranteed to be safe because the lock gives us unique and non-reentrant access. + // Calling malloc() is safe because preconditions on this function match the trait method preconditions. + let _lock = lock::lock(); + unsafe { (*DLMALLOC.get()).0.malloc(layout.size(), layout.align()) } +} - #[inline] - unsafe fn alloc_zeroed(&self, layout: Layout) -> *mut u8 { - // SAFETY: DLMALLOC access is guaranteed to be safe because the lock gives us unique and non-reentrant access. - // Calling calloc() is safe because preconditions on this function match the trait method preconditions. - let _lock = lock::lock(); - unsafe { (*DLMALLOC.get()).0.calloc(layout.size(), layout.align()) } - } +#[inline] +pub unsafe fn alloc_zeroed(layout: Layout) -> *mut u8 { + // SAFETY: DLMALLOC access is guaranteed to be safe because the lock gives us unique and non-reentrant access. + // Calling calloc() is safe because preconditions on this function match the trait method preconditions. + let _lock = lock::lock(); + unsafe { (*DLMALLOC.get()).0.calloc(layout.size(), layout.align()) } +} - #[inline] - unsafe fn dealloc(&self, ptr: *mut u8, layout: Layout) { - // SAFETY: DLMALLOC access is guaranteed to be safe because the lock gives us unique and non-reentrant access. - // Calling free() is safe because preconditions on this function match the trait method preconditions. - let _lock = lock::lock(); - unsafe { (*DLMALLOC.get()).0.free(ptr, layout.size(), layout.align()) } - } +#[inline] +pub unsafe fn dealloc(ptr: *mut u8, layout: Layout) { + // SAFETY: DLMALLOC access is guaranteed to be safe because the lock gives us unique and non-reentrant access. + // Calling free() is safe because preconditions on this function match the trait method preconditions. + let _lock = lock::lock(); + unsafe { (*DLMALLOC.get()).0.free(ptr, layout.size(), layout.align()) } +} - #[inline] - unsafe fn realloc(&self, ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { - // SAFETY: DLMALLOC access is guaranteed to be safe because the lock gives us unique and non-reentrant access. - // Calling realloc() is safe because preconditions on this function match the trait method preconditions. - let _lock = lock::lock(); - unsafe { (*DLMALLOC.get()).0.realloc(ptr, layout.size(), layout.align(), new_size) } - } +#[inline] +pub unsafe fn realloc(ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { + // SAFETY: DLMALLOC access is guaranteed to be safe because the lock gives us unique and non-reentrant access. + // Calling realloc() is safe because preconditions on this function match the trait method preconditions. + let _lock = lock::lock(); + unsafe { (*DLMALLOC.get()).0.realloc(ptr, layout.size(), layout.align(), new_size) } } #[cfg(target_feature = "atomics")] diff --git a/library/std/src/sys/alloc/windows.rs b/library/std/src/sys/alloc/windows.rs index 90da0b7e9965c..1d75cbd9d54f1 100644 --- a/library/std/src/sys/alloc/windows.rs +++ b/library/std/src/sys/alloc/windows.rs @@ -1,5 +1,18 @@ +//! Implements `System` on Windows. +//! +//! All pointers returned by this allocator have, in addition to the guarantees of `GlobalAlloc`, the +//! following properties: +//! +//! If the pointer was allocated or reallocated with a `layout` specifying an alignment <= `MIN_ALIGN` +//! the pointer will be aligned to at least `MIN_ALIGN` and point to the start of the allocated block. +//! +//! If the pointer was allocated or reallocated with a `layout` specifying an alignment > `MIN_ALIGN` +//! the pointer will be aligned to the specified alignment and not point to the start of the allocated block. +//! Instead there will be a header readable directly before the returned pointer, containing the actual +//! location of the start of the block. + use super::{MIN_ALIGN, realloc_fallback}; -use crate::alloc::{GlobalAlloc, Layout, System}; +use crate::alloc::Layout; use crate::ffi::c_void; use crate::mem::MaybeUninit; use crate::ptr; @@ -118,6 +131,9 @@ unsafe fn allocate(layout: Layout, zeroed: bool) -> *mut u8 { process_heap_alloc(MaybeUninit::uninit(), flags, layout.size()) as *mut u8 } else { // Allocate extra padding in order to be able to satisfy the alignment. + // This addition does not overflow due to `Layout` type invariants, + // `size()` is at most `isize::MAX` while + // `align()` is at most `1 << (bits in usize - 2)` if `size()` is non-zero. let total = layout.align() + layout.size(); let ptr = process_heap_alloc(MaybeUninit::uninit(), flags, total) as *mut u8; @@ -147,70 +163,56 @@ unsafe fn allocate(layout: Layout, zeroed: bool) -> *mut u8 { } } -// All pointers returned by this allocator have, in addition to the guarantees of `GlobalAlloc`, the -// following properties: -// -// If the pointer was allocated or reallocated with a `layout` specifying an alignment <= `MIN_ALIGN` -// the pointer will be aligned to at least `MIN_ALIGN` and point to the start of the allocated block. -// -// If the pointer was allocated or reallocated with a `layout` specifying an alignment > `MIN_ALIGN` -// the pointer will be aligned to the specified alignment and not point to the start of the allocated block. -// Instead there will be a header readable directly before the returned pointer, containing the actual -// location of the start of the block. -#[stable(feature = "alloc_system_type", since = "1.28.0")] -unsafe impl GlobalAlloc for System { - #[inline] - unsafe fn alloc(&self, layout: Layout) -> *mut u8 { - // SAFETY: Pointers returned by `allocate` satisfy the guarantees of `System` - let zeroed = false; - unsafe { allocate(layout, zeroed) } - } +pub unsafe fn alloc(layout: Layout) -> *mut u8 { + // SAFETY: Pointers returned by `allocate` satisfy the guarantees of `System` + let zeroed = false; + unsafe { allocate(layout, zeroed) } +} - #[inline] - unsafe fn alloc_zeroed(&self, layout: Layout) -> *mut u8 { - // SAFETY: Pointers returned by `allocate` satisfy the guarantees of `System` - let zeroed = true; - unsafe { allocate(layout, zeroed) } - } +#[inline] +pub unsafe fn alloc_zeroed(layout: Layout) -> *mut u8 { + // SAFETY: Pointers returned by `allocate` satisfy the guarantees of `System` + let zeroed = true; + unsafe { allocate(layout, zeroed) } +} - #[inline] - unsafe fn dealloc(&self, ptr: *mut u8, layout: Layout) { - let block = { - if layout.align() <= MIN_ALIGN { - ptr - } else { - // The location of the start of the block is stored in the padding before `ptr`. +#[inline] +pub unsafe fn dealloc(ptr: *mut u8, layout: Layout) { + let block = { + if layout.align() <= MIN_ALIGN { + ptr + } else { + // The location of the start of the block is stored in the padding before `ptr`. - // SAFETY: Because of the contract of `System`, `ptr` is guaranteed to be non-null - // and have a header readable directly before it. - unsafe { ptr::read((ptr as *mut Header).sub(1)).0 } - } - }; + // SAFETY: Because of the contract of `System`, `ptr` is guaranteed to be non-null + // and have a header readable directly before it. + unsafe { ptr::read((ptr as *mut Header).sub(1)).0 } + } + }; + // because `ptr` has been successfully allocated with this allocator, + // there must be a valid process heap. + let heap = get_process_heap(); + + // SAFETY: `heap` is a non-null handle returned by `GetProcessHeap`, + // `block` is a pointer to the start of an allocated block. + unsafe { HeapFree(heap, 0, block.cast::()) }; +} + +#[inline] +pub unsafe fn realloc(ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { + if layout.align() <= MIN_ALIGN { // because `ptr` has been successfully allocated with this allocator, // there must be a valid process heap. let heap = get_process_heap(); // SAFETY: `heap` is a non-null handle returned by `GetProcessHeap`, - // `block` is a pointer to the start of an allocated block. - unsafe { HeapFree(heap, 0, block.cast::()) }; - } - - #[inline] - unsafe fn realloc(&self, ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { - if layout.align() <= MIN_ALIGN { - // because `ptr` has been successfully allocated with this allocator, - // there must be a valid process heap. - let heap = get_process_heap(); - - // SAFETY: `heap` is a non-null handle returned by `GetProcessHeap`, - // `ptr` is a pointer to the start of an allocated block. - // The returned pointer points to the start of an allocated block. - unsafe { HeapReAlloc(heap, 0, ptr.cast::(), new_size).cast::() } - } else { - // SAFETY: `realloc_fallback` is implemented using `dealloc` and `alloc`, which will - // correctly handle `ptr` and return a pointer satisfying the guarantees of `System` - unsafe { realloc_fallback(self, ptr, layout, new_size) } - } + // `ptr` is a pointer to the start of an allocated block. + // The returned pointer points to the start of an allocated block. + unsafe { HeapReAlloc(heap, 0, ptr.cast::(), new_size).cast::() } + } else { + // SAFETY: `realloc_fallback` is implemented using `dealloc` and `alloc`, which will + // correctly handle `ptr` and return a pointer satisfying the guarantees of `System` + unsafe { realloc_fallback(ptr, layout, new_size) } } } diff --git a/library/std/src/sys/alloc/xous.rs b/library/std/src/sys/alloc/xous.rs index c7f973b802791..74229351f6d22 100644 --- a/library/std/src/sys/alloc/xous.rs +++ b/library/std/src/sys/alloc/xous.rs @@ -1,7 +1,7 @@ -// FIXME(static_mut_refs): Do not allow `static_mut_refs` lint +// FIXME(static_mut_refs): use raw pointers instead of references #![allow(static_mut_refs)] -use crate::alloc::{GlobalAlloc, Layout, System}; +use crate::alloc::Layout; #[cfg(not(test))] #[unsafe(export_name = "_ZN16__rust_internals3std3sys4xous5alloc8DLMALLOCE")] @@ -13,39 +13,36 @@ unsafe extern "Rust" { static mut DLMALLOC: dlmalloc::Dlmalloc; } -#[stable(feature = "alloc_system_type", since = "1.28.0")] -unsafe impl GlobalAlloc for System { - #[inline] - unsafe fn alloc(&self, layout: Layout) -> *mut u8 { - // SAFETY: DLMALLOC access is guaranteed to be safe because the lock gives us unique and non-reentrant access. - // Calling malloc() is safe because preconditions on this function match the trait method preconditions. - let _lock = lock::lock(); - unsafe { DLMALLOC.malloc(layout.size(), layout.align()) } - } +#[inline] +pub unsafe fn alloc(layout: Layout) -> *mut u8 { + // SAFETY: DLMALLOC access is guaranteed to be safe because the lock gives us unique and non-reentrant access. + // Calling malloc() is safe because preconditions on this function match the trait method preconditions. + let _lock = lock::lock(); + unsafe { DLMALLOC.malloc(layout.size(), layout.align()) } +} - #[inline] - unsafe fn alloc_zeroed(&self, layout: Layout) -> *mut u8 { - // SAFETY: DLMALLOC access is guaranteed to be safe because the lock gives us unique and non-reentrant access. - // Calling calloc() is safe because preconditions on this function match the trait method preconditions. - let _lock = lock::lock(); - unsafe { DLMALLOC.calloc(layout.size(), layout.align()) } - } +#[inline] +pub unsafe fn alloc_zeroed(layout: Layout) -> *mut u8 { + // SAFETY: DLMALLOC access is guaranteed to be safe because the lock gives us unique and non-reentrant access. + // Calling calloc() is safe because preconditions on this function match the trait method preconditions. + let _lock = lock::lock(); + unsafe { DLMALLOC.calloc(layout.size(), layout.align()) } +} - #[inline] - unsafe fn dealloc(&self, ptr: *mut u8, layout: Layout) { - // SAFETY: DLMALLOC access is guaranteed to be safe because the lock gives us unique and non-reentrant access. - // Calling free() is safe because preconditions on this function match the trait method preconditions. - let _lock = lock::lock(); - unsafe { DLMALLOC.free(ptr, layout.size(), layout.align()) } - } +#[inline] +pub unsafe fn dealloc(ptr: *mut u8, layout: Layout) { + // SAFETY: DLMALLOC access is guaranteed to be safe because the lock gives us unique and non-reentrant access. + // Calling free() is safe because preconditions on this function match the trait method preconditions. + let _lock = lock::lock(); + unsafe { DLMALLOC.free(ptr, layout.size(), layout.align()) } +} - #[inline] - unsafe fn realloc(&self, ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { - // SAFETY: DLMALLOC access is guaranteed to be safe because the lock gives us unique and non-reentrant access. - // Calling realloc() is safe because preconditions on this function match the trait method preconditions. - let _lock = lock::lock(); - unsafe { DLMALLOC.realloc(ptr, layout.size(), layout.align(), new_size) } - } +#[inline] +pub unsafe fn realloc(ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { + // SAFETY: DLMALLOC access is guaranteed to be safe because the lock gives us unique and non-reentrant access. + // Calling realloc() is safe because preconditions on this function match the trait method preconditions. + let _lock = lock::lock(); + unsafe { DLMALLOC.realloc(ptr, layout.size(), layout.align(), new_size) } } mod lock { diff --git a/library/std/src/sys/alloc/zkvm.rs b/library/std/src/sys/alloc/zkvm.rs index a600cfa2220dd..7f39d7fed777e 100644 --- a/library/std/src/sys/alloc/zkvm.rs +++ b/library/std/src/sys/alloc/zkvm.rs @@ -1,15 +1,18 @@ -use crate::alloc::{GlobalAlloc, Layout, System}; +use crate::alloc::Layout; use crate::sys::pal::abi; -#[stable(feature = "alloc_system_type", since = "1.28.0")] -unsafe impl GlobalAlloc for System { - #[inline] - unsafe fn alloc(&self, layout: Layout) -> *mut u8 { - unsafe { abi::sys_alloc_aligned(layout.size(), layout.align()) } - } +#[inline] +pub unsafe fn alloc(layout: Layout) -> *mut u8 { + unsafe { abi::sys_alloc_aligned(layout.size(), layout.align()) } +} + +#[inline] +pub unsafe fn dealloc(_ptr: *mut u8, _layout: Layout) { + // this allocator never deallocates memory +} - #[inline] - unsafe fn dealloc(&self, _ptr: *mut u8, _layout: Layout) { - // this allocator never deallocates memory - } +#[inline] +pub unsafe fn realloc(ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { + // SAFETY: this is just a `pub` wrapper. + unsafe { super::realloc_fallback(ptr, layout, new_size) } } diff --git a/library/std/src/sys/args/mod.rs b/library/std/src/sys/args/mod.rs index 5424d40a15883..c8011a6fed374 100644 --- a/library/std/src/sys/args/mod.rs +++ b/library/std/src/sys/args/mod.rs @@ -15,7 +15,14 @@ mod common; cfg_select! { any( - all(target_family = "unix", not(any(target_os = "espidf", target_os = "vita"))), + all( + target_family = "unix", + not(any( + all(target_family = "wasm", target_os = "linux"), + target_os = "espidf", + target_os = "vita" + )) + ), target_os = "hermit", ) => { mod unix; @@ -42,8 +49,12 @@ cfg_select! { pub use wasip1::*; } all(target_os = "wasi", any(target_env = "p2", target_env = "p3")) => { - mod wasip2; - pub use wasip2::*; + mod wasi; + pub use wasi::*; + } + all(target_family = "wasm", target_os = "linux") => { + mod wali; + pub use wali::*; } target_os = "xous" => { mod xous; diff --git a/library/std/src/sys/args/sgx.rs b/library/std/src/sys/args/sgx.rs index 6ff94f5681b6f..6750cf33d7686 100644 --- a/library/std/src/sys/args/sgx.rs +++ b/library/std/src/sys/args/sgx.rs @@ -1,9 +1,7 @@ -#![allow(fuzzy_provenance_casts)] // FIXME: this module systematically confuses pointers and integers - use crate::ffi::OsString; use crate::num::NonZero; use crate::ops::Try; -use crate::sync::atomic::{Atomic, AtomicUsize, Ordering}; +use crate::sync::OnceLock; use crate::sys::FromInner; use crate::sys::os_str::Buf; use crate::sys::pal::abi::usercalls::alloc; @@ -13,8 +11,7 @@ use crate::{fmt, slice}; // Specifying linkage/symbol name is solely to ensure a single instance between this crate and its unit tests #[cfg_attr(test, linkage = "available_externally")] #[unsafe(export_name = "_ZN16__rust_internals3std3sys3sgx4args4ARGSE")] -static ARGS: Atomic = AtomicUsize::new(0); -type ArgsStore = Vec; +static ARGS: OnceLock> = OnceLock::new(); #[cfg_attr(test, allow(dead_code))] pub unsafe fn init(argc: isize, argv: *const *const u8) { @@ -23,15 +20,16 @@ pub unsafe fn init(argc: isize, argv: *const *const u8) { let args = args .iter() .map(|a| OsString::from_inner(Buf { inner: a.copy_user_buffer() })) - .collect::(); - ARGS.store(Box::into_raw(Box::new(args)) as _, Ordering::Relaxed); + .collect::>(); + + if let Err(_) = ARGS.set(args) { + rtabort!("init called twice"); + } } } pub fn args() -> Args { - let args = unsafe { (ARGS.load(Ordering::Relaxed) as *const ArgsStore).as_ref() }; - let slice = args.map(|args| args.as_slice()).unwrap_or(&[]); - Args { iter: slice.iter() } + Args { iter: ARGS.get().map_or_default(|args| args.iter()) } } pub struct Args { diff --git a/library/std/src/sys/args/uefi.rs b/library/std/src/sys/args/uefi.rs index 02dada382eff0..edf6f6873f8d2 100644 --- a/library/std/src/sys/args/uefi.rs +++ b/library/std/src/sys/args/uefi.rs @@ -93,7 +93,7 @@ fn parse_lp_cmd_line(code_units: &[u16]) -> Option> { // If not `in_quotes`, a space or tab ends the argument. SPACE if !in_quotes => { ret_val.push(OsString::from(&cur[..])); - cur.truncate(0); + cur.clear(); // Skip whitespace. while code_units_iter.next_if_eq(&Ok(SPACE)).is_some() {} diff --git a/library/std/src/sys/args/unix.rs b/library/std/src/sys/args/unix.rs index 0dfbd5f03eba9..197931d8cc8d2 100644 --- a/library/std/src/sys/args/unix.rs +++ b/library/std/src/sys/args/unix.rs @@ -81,6 +81,7 @@ pub fn args() -> Args { target_os = "horizon", target_os = "aix", target_os = "nto", + target_os = "qnx", target_os = "hurd", target_os = "rtems", target_os = "nuttx", @@ -164,7 +165,7 @@ mod imp { // of this used `[[NSProcessInfo processInfo] arguments]`. #[cfg(target_vendor = "apple")] mod imp { - use crate::ffi::{c_char, c_int}; + use crate::ffi::c_char; pub unsafe fn init(_argc: isize, _argv: *const *const u8) { // No need to initialize anything in here, `libdyld.dylib` has already @@ -172,12 +173,6 @@ mod imp { } pub fn argc_argv() -> (isize, *const *const c_char) { - unsafe extern "C" { - // These functions are in crt_externs.h. - fn _NSGetArgc() -> *mut c_int; - fn _NSGetArgv() -> *mut *mut *mut c_char; - } - // SAFETY: The returned pointer points to a static initialized early // in the program lifetime by `libdyld.dylib`, and as such is always // valid. @@ -187,9 +182,9 @@ mod imp { // doesn't exist a lock that we can take. Instead, it is generally // expected that it's only modified in `main` / before other code // runs, so reading this here should be fine. - let argc = unsafe { _NSGetArgc().read() }; + let argc = unsafe { libc::_NSGetArgc().read() }; // SAFETY: Same as above. - let argv = unsafe { _NSGetArgv().read() }; + let argv = unsafe { libc::_NSGetArgv().read() }; // Cast from `*mut *mut c_char` to `*const *const c_char` (argc as isize, argv.cast()) diff --git a/library/std/src/sys/args/wali.rs b/library/std/src/sys/args/wali.rs new file mode 100644 index 0000000000000..dc6295a483334 --- /dev/null +++ b/library/std/src/sys/args/wali.rs @@ -0,0 +1,54 @@ +pub use super::common::Args; + +/// One-time global initialization. +pub unsafe fn init(argc: isize, argv: *const *const u8) { + unsafe { imp::init(argc, argv) } +} + +/// Returns the command line arguments +pub fn args() -> Args { + imp::args() +} + +mod imp { + use super::Args; + use crate::ffi::{CString, OsString}; + use crate::os::raw::{c_uint as WaliArgIdx, c_uint}; + use crate::os::unix::prelude::*; + use crate::sync::OnceLock; + + #[link(wasm_import_module = "wali")] + unsafe extern "C" { + pub fn __cl_get_argc() -> WaliArgIdx; + pub fn __cl_get_argv_len(offset: WaliArgIdx) -> c_uint; + pub fn __cl_copy_argv(buf: *mut i8, offset: WaliArgIdx) -> c_uint; + } + + static ARGS: OnceLock> = OnceLock::new(); + + pub unsafe fn init(_argc: isize, _argv: *const *const u8) { + // Uses the WALI arguments API + ARGS.set(argc_argv()).ok(); + } + + unsafe fn load_arg(idx: c_uint) -> OsString { + let arg_len = unsafe { __cl_get_argv_len(idx) }; + let arg_buf = CString::new(vec![b'x'; arg_len as usize]).unwrap(); + let ptr = arg_buf.into_raw(); + let arg_buf = unsafe { + __cl_copy_argv(ptr, idx); + CString::from_raw(ptr) + }; + OsStringExt::from_vec(arg_buf.into_bytes()) + } + + fn argc_argv() -> Vec { + let argc = unsafe { __cl_get_argc() }; + (0..argc).map(|x| unsafe { load_arg(x) }).collect() + } + + pub fn args() -> Args { + let cached = ARGS.get().cloned().unwrap_or_default(); + Args::new(cached) + } +} diff --git a/library/std/src/sys/args/wasi.rs b/library/std/src/sys/args/wasi.rs new file mode 100644 index 0000000000000..3d26a76ad6db6 --- /dev/null +++ b/library/std/src/sys/args/wasi.rs @@ -0,0 +1,11 @@ +#[cfg(target_env = "p2")] +use wasip2 as wasi; +#[cfg(target_env = "p3")] +use wasip3 as wasi; + +pub use super::common::Args; + +/// Returns the command line arguments +pub fn args() -> Args { + Args::new(wasi::cli::environment::get_arguments().into_iter().map(|arg| arg.into()).collect()) +} diff --git a/library/std/src/sys/args/wasip1.rs b/library/std/src/sys/args/wasip1.rs index 72063a87dc9f5..c09175a23f50f 100644 --- a/library/std/src/sys/args/wasip1.rs +++ b/library/std/src/sys/args/wasip1.rs @@ -11,10 +11,10 @@ pub fn args() -> Args { fn maybe_args() -> Option> { unsafe { - let (argc, buf_size) = wasi::args_sizes_get().ok()?; + let (argc, buf_size) = wasip1::args_sizes_get().ok()?; let mut argv = Vec::with_capacity(argc); let mut buf = Vec::with_capacity(buf_size); - wasi::args_get(argv.as_mut_ptr(), buf.as_mut_ptr()).ok()?; + wasip1::args_get(argv.as_mut_ptr(), buf.as_mut_ptr()).ok()?; argv.set_len(argc); let mut ret = Vec::with_capacity(argc); for ptr in argv { diff --git a/library/std/src/sys/args/wasip2.rs b/library/std/src/sys/args/wasip2.rs deleted file mode 100644 index a57e4b97786d0..0000000000000 --- a/library/std/src/sys/args/wasip2.rs +++ /dev/null @@ -1,6 +0,0 @@ -pub use super::common::Args; - -/// Returns the command line arguments -pub fn args() -> Args { - Args::new(wasip2::cli::environment::get_arguments().into_iter().map(|arg| arg.into()).collect()) -} diff --git a/library/std/src/sys/args/windows.rs b/library/std/src/sys/args/windows.rs index c1988657ff1b1..bd26db7fea553 100644 --- a/library/std/src/sys/args/windows.rs +++ b/library/std/src/sys/args/windows.rs @@ -12,9 +12,9 @@ use crate::num::NonZero; use crate::os::windows::prelude::*; use crate::path::{Path, PathBuf}; use crate::sys::helpers::WStrUnits; -use crate::sys::pal::os::current_exe; use crate::sys::pal::{ensure_no_nuls, fill_utf16_buf}; use crate::sys::path::get_long_path; +use crate::sys::paths::current_exe; use crate::sys::{AsInner, c, to_u16s}; use crate::{io, iter, ptr}; @@ -106,7 +106,7 @@ fn parse_lp_cmd_line<'a, F: Fn() -> OsString>( // If not `in_quotes`, a space or tab ends the argument. SPACE | TAB if !in_quotes => { ret_val.push(OsString::from_wide(&cur[..])); - cur.truncate(0); + cur.clear(); // Skip whitespace. code_units.advance_while(|w| w == SPACE || w == TAB); diff --git a/library/std/src/sys/args/xous.rs b/library/std/src/sys/args/xous.rs index 2010bad14d1fb..9025ed4f1354c 100644 --- a/library/std/src/sys/args/xous.rs +++ b/library/std/src/sys/args/xous.rs @@ -1,9 +1,8 @@ pub use super::common::Args; -use crate::sys::pal::os::get_application_parameters; -use crate::sys::pal::os::params::ArgumentList; +use crate::sys::pal::params::{self, ArgumentList}; pub fn args() -> Args { - let Some(params) = get_application_parameters() else { + let Some(params) = params::get() else { return Args::new(vec![]); }; diff --git a/library/std/src/sys/cmath.rs b/library/std/src/sys/cmath.rs index 1592218ead8b0..2104087141d1a 100644 --- a/library/std/src/sys/cmath.rs +++ b/library/std/src/sys/cmath.rs @@ -4,7 +4,9 @@ // or by `compiler-builtins` on unsupported platforms. unsafe extern "C" { pub safe fn acos(n: f64) -> f64; + pub safe fn acosh(n: f64) -> f64; pub safe fn asin(n: f64) -> f64; + pub safe fn asinh(n: f64) -> f64; pub safe fn atan(n: f64) -> f64; pub safe fn atan2(a: f64, b: f64) -> f64; pub safe fn cosh(n: f64) -> f64; @@ -30,7 +32,9 @@ unsafe extern "C" { pub safe fn erfcf(n: f32) -> f32; pub safe fn acosf128(n: f128) -> f128; + pub safe fn acoshf128(n: f128) -> f128; pub safe fn asinf128(n: f128) -> f128; + pub safe fn asinhf128(n: f128) -> f128; pub safe fn atanf128(n: f128) -> f128; pub safe fn atan2f128(a: f128, b: f128) -> f128; pub safe fn cbrtf128(n: f128) -> f128; @@ -57,6 +61,16 @@ cfg_select! { f64::acos(n as f64) as f32 } + #[inline] + pub fn acoshf(n: f32) -> f32 { + f64::acosh(n as f64) as f32 + } + + #[inline] + pub fn asinhf(n: f32) -> f32 { + f64::asinh(n as f64) as f32 + } + #[inline] pub fn asinf(n: f32) -> f32 { f64::asin(n as f64) as f32 @@ -95,7 +109,9 @@ cfg_select! { _ => { unsafe extern "C" { pub safe fn acosf(n: f32) -> f32; + pub safe fn acoshf(n: f32) -> f32; pub safe fn asinf(n: f32) -> f32; + pub safe fn asinhf(n: f32) -> f32; pub safe fn atan2f(a: f32, b: f32) -> f32; pub safe fn atanf(n: f32) -> f32; pub safe fn coshf(n: f32) -> f32; diff --git a/library/std/src/sys/env/common.rs b/library/std/src/sys/env/common.rs index 87e86e2947fad..d620c8b4acdd9 100644 --- a/library/std/src/sys/env/common.rs +++ b/library/std/src/sys/env/common.rs @@ -17,9 +17,6 @@ impl fmt::Debug for Env { } } -impl !Send for Env {} -impl !Sync for Env {} - impl Iterator for Env { type Item = (OsString, OsString); fn next(&mut self) -> Option<(OsString, OsString)> { diff --git a/library/std/src/sys/env/sgx.rs b/library/std/src/sys/env/sgx.rs index 09090ec7cf0dd..b45acfe7c1ba7 100644 --- a/library/std/src/sys/env/sgx.rs +++ b/library/std/src/sys/env/sgx.rs @@ -1,54 +1,35 @@ -#![allow(fuzzy_provenance_casts)] // FIXME: this module systematically confuses pointers and integers - pub use super::common::Env; use crate::collections::HashMap; use crate::ffi::{OsStr, OsString}; use crate::io; -use crate::sync::atomic::{Atomic, AtomicUsize, Ordering}; -use crate::sync::{Mutex, Once}; +use crate::sync::{Mutex, OnceLock}; + +type EnvStore = Mutex>; // Specifying linkage/symbol name is solely to ensure a single instance between this crate and its unit tests #[cfg_attr(test, linkage = "available_externally")] #[unsafe(export_name = "_ZN16__rust_internals3std3sys3pal3sgx2os3ENVE")] -static ENV: Atomic = AtomicUsize::new(0); -// Specifying linkage/symbol name is solely to ensure a single instance between this crate and its unit tests -#[cfg_attr(test, linkage = "available_externally")] -#[unsafe(export_name = "_ZN16__rust_internals3std3sys3pal3sgx2os8ENV_INITE")] -static ENV_INIT: Once = Once::new(); -type EnvStore = Mutex>; - -fn get_env_store() -> Option<&'static EnvStore> { - unsafe { (ENV.load(Ordering::Relaxed) as *const EnvStore).as_ref() } -} - -fn create_env_store() -> &'static EnvStore { - ENV_INIT.call_once(|| { - ENV.store(Box::into_raw(Box::new(EnvStore::default())) as _, Ordering::Relaxed) - }); - unsafe { &*(ENV.load(Ordering::Relaxed) as *const EnvStore) } -} +static ENV: OnceLock = OnceLock::new(); pub fn env() -> Env { - let clone_to_vec = |map: &HashMap| -> Vec<_> { - map.iter().map(|(k, v)| (k.clone(), v.clone())).collect() - }; - - let env = get_env_store().map(|env| clone_to_vec(&env.lock().unwrap())).unwrap_or_default(); + let env = ENV + .get() + .map(|env| env.lock().unwrap().iter().map(|(k, v)| (k.clone(), v.clone())).collect()) + .unwrap_or_default(); Env::new(env) } pub fn getenv(k: &OsStr) -> Option { - get_env_store().and_then(|s| s.lock().unwrap().get(k).cloned()) + ENV.get().and_then(|s| s.lock().unwrap().get(k).cloned()) } pub unsafe fn setenv(k: &OsStr, v: &OsStr) -> io::Result<()> { - let (k, v) = (k.to_owned(), v.to_owned()); - create_env_store().lock().unwrap().insert(k, v); + ENV.get_or_init(|| EnvStore::default()).lock().unwrap().insert(k.to_owned(), v.to_owned()); Ok(()) } pub unsafe fn unsetenv(k: &OsStr) -> io::Result<()> { - if let Some(env) = get_env_store() { + if let Some(env) = ENV.get() { env.lock().unwrap().remove(k); } Ok(()) diff --git a/library/std/src/sys/env/uefi.rs b/library/std/src/sys/env/uefi.rs index af16a02642a4c..bc2aed4231797 100644 --- a/library/std/src/sys/env/uefi.rs +++ b/library/std/src/sys/env/uefi.rs @@ -43,7 +43,20 @@ mod uefi_env { pub(crate) fn unset(key: &OsStr) -> io::Result<()> { let mut key_ptr = helpers::os_string_to_raw(key) .ok_or(io::const_error!(io::ErrorKind::InvalidInput, "invalid key"))?; - unsafe { set_raw(key_ptr.as_mut_ptr(), crate::ptr::null_mut()) } + let r = unsafe { set_raw(key_ptr.as_mut_ptr(), crate::ptr::null_mut()) }; + + // The UEFI Shell spec only lists `EFI_SUCCESS` as a possible return value for + // `SetEnv`, but the edk2 implementation can return errors. Allow most of these + // errors to bubble up to the caller, but ignore `NotFound` errors; deleting a + // nonexistent variable is not listed as an error condition of + // `std::env::remove_var`. + if let Err(err) = &r + && err.kind() == io::ErrorKind::NotFound + { + Ok(()) + } else { + r + } } pub(crate) fn get_all() -> io::Result> { diff --git a/library/std/src/sys/env/unix.rs b/library/std/src/sys/env/unix.rs index 66805ce3fa71e..f9ecec0c7304f 100644 --- a/library/std/src/sys/env/unix.rs +++ b/library/std/src/sys/env/unix.rs @@ -38,8 +38,23 @@ pub unsafe fn environ() -> *mut *const *const c_char { unsafe { libc::_NSGetEnviron() as *mut *const *const c_char } } +// On FreeBSD, environ lives in crt1.o, not libc.so, so a shared library +// cannot take a strong link-time reference to it (#153451), and dlsym cannot +// find it in a statically linked executable, which has no dynamic symbol +// table to search (#158939). A weak reference covers both: it binds at link +// time in any executable, and in a shared library the runtime linker +// resolves it against the environ the executable exports. +#[cfg(target_os = "freebsd")] +pub unsafe fn environ() -> *mut *const *const c_char { + unsafe extern "C" { + #[linkage = "extern_weak"] + static environ: *mut *const *const c_char; + } + unsafe { environ } +} + // Use the `environ` static which is part of POSIX. -#[cfg(not(target_vendor = "apple"))] +#[cfg(not(any(target_os = "freebsd", target_vendor = "apple")))] pub unsafe fn environ() -> *mut *const *const c_char { unsafe extern "C" { static mut environ: *const *const c_char; @@ -58,14 +73,19 @@ pub fn env_read_lock() -> impl Drop { pub fn env() -> Env { unsafe { let _guard = env_read_lock(); - let mut environ = *environ(); let mut result = Vec::new(); - if !environ.is_null() { - while !(*environ).is_null() { - if let Some(key_value) = parse(CStr::from_ptr(*environ).to_bytes()) { - result.push(key_value); + // A null return means the platform could not locate the symbol; + // treat it like an empty environment. + let environ_ptr = environ(); + if !environ_ptr.is_null() { + let mut environ = *environ_ptr; + if !environ.is_null() { + while !(*environ).is_null() { + if let Some(key_value) = parse(CStr::from_ptr(*environ).to_bytes()) { + result.push(key_value); + } + environ = environ.add(1); } - environ = environ.add(1); } } return Env::new(result); diff --git a/library/std/src/sys/env/wasi.rs b/library/std/src/sys/env/wasi.rs index c970aac182604..6b892376fd0cf 100644 --- a/library/std/src/sys/env/wasi.rs +++ b/library/std/src/sys/env/wasi.rs @@ -1,11 +1,16 @@ use core::slice::memchr; pub use super::common::Env; -use crate::ffi::{CStr, OsStr, OsString}; +use crate::ffi::{CStr, OsStr, OsString, c_char}; use crate::io; use crate::os::wasi::prelude::*; use crate::sys::helpers::run_with_cstr; -use crate::sys::pal::os::{cvt, libc}; +use crate::sys::pal::cvt; + +// This is not available yet in libc. +unsafe extern "C" { + fn __wasilibc_get_environ() -> *mut *mut c_char; +} cfg_select! { target_feature = "atomics" => { @@ -37,7 +42,7 @@ pub fn env() -> Env { // Use `__wasilibc_get_environ` instead of `environ` here so that we // don't require wasi-libc to eagerly initialize the environment // variables. - let mut environ = libc::__wasilibc_get_environ(); + let mut environ = __wasilibc_get_environ(); let mut result = Vec::new(); if !environ.is_null() { diff --git a/library/std/src/sys/env/xous.rs b/library/std/src/sys/env/xous.rs index 8f65f30d35fcc..f576cfa0025a1 100644 --- a/library/std/src/sys/env/xous.rs +++ b/library/std/src/sys/env/xous.rs @@ -2,21 +2,19 @@ pub use super::common::Env; use crate::collections::HashMap; use crate::ffi::{OsStr, OsString}; use crate::io; -use crate::sync::atomic::{Atomic, AtomicUsize, Ordering}; -use crate::sync::{Mutex, Once}; -use crate::sys::pal::os::{get_application_parameters, params}; +use crate::sync::{Mutex, OnceLock}; +use crate::sys::pal::params; -static ENV: Atomic = AtomicUsize::new(0); -static ENV_INIT: Once = Once::new(); type EnvStore = Mutex>; +static ENV: OnceLock = OnceLock::new(); + fn get_env_store() -> &'static EnvStore { - ENV_INIT.call_once(|| { - let env_store = EnvStore::default(); - if let Some(params) = get_application_parameters() { + ENV.get_or_init(|| { + let mut env_store = HashMap::new(); + if let Some(params) = params::get() { for param in params { if let Ok(envs) = params::EnvironmentBlock::try_from(¶m) { - let mut env_store = env_store.lock().unwrap(); for env in envs { env_store.insert(env.key.into(), env.value.into()); } @@ -24,17 +22,12 @@ fn get_env_store() -> &'static EnvStore { } } } - ENV.store(Box::into_raw(Box::new(env_store)) as _, Ordering::Relaxed) - }); - unsafe { &*core::ptr::with_exposed_provenance::(ENV.load(Ordering::Relaxed)) } + Mutex::new(env_store) + }) } pub fn env() -> Env { - let clone_to_vec = |map: &HashMap| -> Vec<_> { - map.iter().map(|(k, v)| (k.clone(), v.clone())).collect() - }; - - let env = clone_to_vec(&*get_env_store().lock().unwrap()); + let env = get_env_store().lock().unwrap().iter().map(|(k, v)| (k.clone(), v.clone())).collect(); Env::new(env) } diff --git a/library/std/src/sys/env_consts.rs b/library/std/src/sys/env_consts.rs index 573f540483b1a..b14160cf4ad32 100644 --- a/library/std/src/sys/env_consts.rs +++ b/library/std/src/sys/env_consts.rs @@ -224,6 +224,17 @@ pub mod os { pub const EXE_EXTENSION: &str = ""; } +#[cfg(target_os = "qnx")] +pub mod os { + pub const FAMILY: &str = "unix"; + pub const OS: &str = "qnx"; + pub const DLL_PREFIX: &str = "lib"; + pub const DLL_SUFFIX: &str = ".so"; + pub const DLL_EXTENSION: &str = "so"; + pub const EXE_SUFFIX: &str = ""; + pub const EXE_EXTENSION: &str = ""; +} + #[cfg(target_os = "nuttx")] pub mod os { pub const FAMILY: &str = "unix"; diff --git a/library/std/src/sys/exit_guard.rs b/library/std/src/sys/exit.rs similarity index 53% rename from library/std/src/sys/exit_guard.rs rename to library/std/src/sys/exit.rs index e7d7a478a5baa..b9ebe2d974fec 100644 --- a/library/std/src/sys/exit_guard.rs +++ b/library/std/src/sys/exit.rs @@ -19,8 +19,7 @@ cfg_select! { /// * If it is called again on the same thread as the first call, it will abort. /// * If it is called again on a different thread, it will wait in a loop /// (waiting for the process to exit). - #[cfg_attr(any(test, doctest), allow(dead_code))] - pub(crate) fn unique_thread_exit() { + pub fn unique_thread_exit() { use crate::ffi::c_int; use crate::ptr; use crate::sync::atomic::AtomicPtr; @@ -35,7 +34,12 @@ cfg_select! { // async-signal-safe, so this function is available in all imaginable // circumstances. let this_thread_id = crate::sys::io::errno_location(); - match EXITING_THREAD_ID.compare_exchange(ptr::null_mut(), this_thread_id, Acquire, Relaxed) { + match EXITING_THREAD_ID.compare_exchange( + ptr::null_mut(), + this_thread_id, + Acquire, + Relaxed, + ) { Ok(_) => { // This is the first thread to call `unique_thread_exit`, // and this is the first time it is called. Continue exiting. @@ -51,7 +55,9 @@ cfg_select! { // Pause until the process exits. loop { // Safety: libc::pause is safe to call. - unsafe { libc::pause(); } + unsafe { + libc::pause(); + } } } } @@ -62,9 +68,86 @@ cfg_select! { /// /// Mitigation is ***NOT*** implemented on this platform, either because this platform /// is not affected, or because mitigation is not yet implemented for this platform. - #[cfg_attr(any(test, doctest), allow(dead_code))] - pub(crate) fn unique_thread_exit() { + #[cfg_attr(any(test, doctest), expect(dead_code))] + pub fn unique_thread_exit() { // Mitigation not required on platforms where `exit` is thread-safe. } } } + +#[cfg(not(test))] +cfg_select! { + any(target_family = "unix", target_os = "wasi") => { + // Used by rustc for checking the definitions of other function with the same symbol names + // + // See the `invalid_runtime_symbols_definitions` lint. + mod runtime_symbols { + unsafe extern "C" { + #[rustc_canonical_symbol] + fn exit(status: core::ffi::c_int) -> !; + } + } + } + _ => {} +} + +pub fn exit(code: i32) -> ! { + cfg_select! { + target_os = "hermit" => unsafe { hermit_abi::exit(code) }, + target_os = "linux" => unsafe { + unique_thread_exit(); + libc::exit(code) + }, + target_os = "motor" => moto_rt::process::exit(code), + all(target_vendor = "fortanix", target_env = "sgx") => { + crate::sys::pal::abi::exit_with_code(code as _) + } + target_os = "solid_asp3" => { + rtabort!("exit({}) called", code) + } + target_os = "teeos" => { + let _ = code; + panic!("TA should not call `exit`") + } + target_os = "uefi" => { + use r_efi::base::Status; + + use crate::os::uefi::env; + + if let (Some(boot_services), Some(handle)) = + (env::boot_services(), env::try_image_handle()) + { + let boot_services = boot_services.cast::(); + let _ = unsafe { + ((*boot_services.as_ptr()).exit)( + handle.as_ptr(), + Status::from_usize(code as usize), + 0, + crate::ptr::null_mut(), + ) + }; + } + crate::intrinsics::abort() + } + any(target_family = "unix", target_os = "wasi") => unsafe { + libc::exit(code as crate::ffi::c_int) + }, + target_os = "vexos" => { + let _ = code; + + unsafe { + vex_sdk::vexSystemExitRequest(); + + loop { + vex_sdk::vexTasksRun(); + } + } + } + target_os = "windows" => unsafe { crate::sys::pal::c::ExitProcess(code as u32) }, + target_os = "xous" => crate::os::xous::ffi::exit(code as u32), + _ => { + let _ = code; + crate::intrinsics::abort() + } + } +} diff --git a/library/std/src/sys/fd/hermit.rs b/library/std/src/sys/fd/hermit.rs index 2666da16420c4..fe1b3082a0aa2 100644 --- a/library/std/src/sys/fd/hermit.rs +++ b/library/std/src/sys/fd/hermit.rs @@ -22,7 +22,7 @@ impl FileDesc { Ok(result as usize) } - pub fn read_buf(&self, mut buf: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, mut buf: BorrowedCursor<'_, u8>) -> io::Result<()> { // SAFETY: The `read` syscall does not read from the buffer, so it is // safe to use `&mut [MaybeUninit]`. let result = cvt(unsafe { @@ -33,7 +33,7 @@ impl FileDesc { ) })?; // SAFETY: Exactly `result` bytes have been filled. - unsafe { buf.advance_unchecked(result as usize) }; + unsafe { buf.advance(result as usize) }; Ok(()) } diff --git a/library/std/src/sys/fd/motor.rs b/library/std/src/sys/fd/motor.rs index edeb99ccf8efe..b81072bcb50c7 100644 --- a/library/std/src/sys/fd/motor.rs +++ b/library/std/src/sys/fd/motor.rs @@ -12,7 +12,7 @@ impl FileDesc { moto_rt::fs::read(self.as_raw_fd(), buf).map_err(map_motor_error) } - pub fn read_buf(&self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { crate::io::default_read_buf(|buf| self.read(buf), cursor) } @@ -64,7 +64,7 @@ impl<'a> Read for &'a FileDesc { (**self).read(buf) } - fn read_buf(&mut self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { (**self).read_buf(cursor) } diff --git a/library/std/src/sys/fd/sgx.rs b/library/std/src/sys/fd/sgx.rs index 1ef768db64c7f..5daa90c4b9f5d 100644 --- a/library/std/src/sys/fd/sgx.rs +++ b/library/std/src/sys/fd/sgx.rs @@ -28,7 +28,7 @@ impl FileDesc { usercalls::read(self.fd, &mut [IoSliceMut::new(buf)]) } - pub fn read_buf(&self, buf: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, buf: BorrowedCursor<'_, u8>) -> io::Result<()> { usercalls::read_buf(self.fd, buf) } diff --git a/library/std/src/sys/fd/unix.rs b/library/std/src/sys/fd/unix.rs index bb6c0ac9e18e6..aa84f6bc28023 100644 --- a/library/std/src/sys/fd/unix.rs +++ b/library/std/src/sys/fd/unix.rs @@ -19,17 +19,35 @@ use libc::off_t as off64_t; use libc::off64_t; cfg_select! { - any( - all(target_os = "linux", not(target_env = "musl")), - target_os = "android", - target_os = "hurd", - ) => { + target_os = "vxworks" => { + // VxWorks does not have pread/pwrite. + // See . + pub unsafe fn pread64( + _fd: libc::c_int, + _buf: *mut libc::c_void, + _count: libc::size_t, + _offset: off64_t, + ) -> libc::ssize_t { + -1 + } + + pub unsafe fn pwrite64( + _fd: libc::c_int, + _buf: *const libc::c_void, + _count: libc::size_t, + _offset: off64_t, + ) -> libc::ssize_t { + -1 + } + } + any(all(target_os = "linux", not(target_env = "musl")), target_os = "android", target_os = "hurd") => + { // Prefer explicit pread64 for 64-bit offset independently of libc // #[cfg(gnu_file_offset_bits64)]. - use libc::pread64; + use libc::{pread64, pwrite64}; } _ => { - use libc::pread as pread64; + use libc::{pread as pread64, pwrite as pwrite64}; } } @@ -38,7 +56,10 @@ use crate::io::{self, BorrowedCursor, IoSlice, IoSliceMut, Read}; use crate::os::fd::{AsFd, AsRawFd, BorrowedFd, FromRawFd, IntoRawFd, OwnedFd, RawFd}; #[cfg(all(target_os = "android", target_pointer_width = "64"))] use crate::sys::pal::weak::syscall; -#[cfg(any(all(target_os = "android", target_pointer_width = "32"), target_vendor = "apple"))] +#[cfg(any( + all(target_os = "android", target_pointer_width = "32"), + all(target_vendor = "apple", not(all(target_os = "macos", target_arch = "aarch64"))) +))] use crate::sys::pal::weak::weak; use crate::sys::{AsInner, FromInner, IntoInner, cvt}; @@ -76,6 +97,7 @@ const fn max_iov() -> usize { target_os = "emscripten", target_os = "linux", target_os = "nto", + target_os = "qnx", ))] const fn max_iov() -> usize { libc::UIO_MAXIOV as usize @@ -91,6 +113,7 @@ const fn max_iov() -> usize { target_os = "netbsd", target_os = "nuttx", target_os = "nto", + target_os = "qnx", target_os = "openbsd", target_os = "horizon", target_os = "vita", @@ -173,7 +196,7 @@ impl FileDesc { .map(|n| n as usize) } - pub fn read_buf(&self, mut cursor: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, mut cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { // SAFETY: `cursor.as_mut()` starts with `cursor.capacity()` writable bytes let ret = cvt(unsafe { libc::read( @@ -185,12 +208,12 @@ impl FileDesc { // SAFETY: `ret` bytes were written to the initialized portion of the buffer unsafe { - cursor.advance_unchecked(ret as usize); + cursor.advance(ret as usize); } Ok(()) } - pub fn read_buf_at(&self, mut cursor: BorrowedCursor<'_>, offset: u64) -> io::Result<()> { + pub fn read_buf_at(&self, mut cursor: BorrowedCursor<'_, u8>, offset: u64) -> io::Result<()> { // SAFETY: `cursor.as_mut()` starts with `cursor.capacity()` writable bytes let ret = cvt(unsafe { pread64( @@ -203,7 +226,7 @@ impl FileDesc { // SAFETY: `ret` bytes were written to the initialized portion of the buffer unsafe { - cursor.advance_unchecked(ret as usize); + cursor.advance(ret as usize); } Ok(()) } @@ -219,6 +242,7 @@ impl FileDesc { target_os = "linux", target_os = "netbsd", target_os = "openbsd", // OpenBSD 2.7 + all(target_os = "macos", target_arch = "aarch64"), ))] pub fn read_vectored_at(&self, bufs: &mut [IoSliceMut<'_>], offset: u64) -> io::Result { let ret = cvt(unsafe { @@ -307,14 +331,15 @@ impl FileDesc { // We support old MacOS, iOS, watchOS, tvOS and visionOS. `preadv` was added in the following // Apple OS versions: - // ios 14.0 - // tvos 14.0 - // macos 11.0 - // watchos 7.0 + // iOS 14.0 + // tvOS 14.0 + // macOS 11.0 + // watchOS 7.0 // - // These versions may be newer than the minimum supported versions of OS's we support so we must - // use "weak" linking. - #[cfg(target_vendor = "apple")] + // Since macOS 11.0 is also the first version with AArch64 support, we can + // `preadv` unconditionally there. But on all other targets we must use + // "weak" linking. + #[cfg(all(target_vendor = "apple", not(all(target_os = "macos", target_arch = "aarch64"))))] pub fn read_vectored_at(&self, bufs: &mut [IoSliceMut<'_>], offset: u64) -> io::Result { weak!( fn preadv( @@ -391,19 +416,6 @@ impl FileDesc { } pub fn write_at(&self, buf: &[u8], offset: u64) -> io::Result { - #[cfg(not(any( - all(target_os = "linux", not(target_env = "musl")), - target_os = "android", - target_os = "hurd" - )))] - use libc::pwrite as pwrite64; - #[cfg(any( - all(target_os = "linux", not(target_env = "musl")), - target_os = "android", - target_os = "hurd" - ))] - use libc::pwrite64; - unsafe { cvt(pwrite64( self.as_raw_fd(), @@ -426,6 +438,7 @@ impl FileDesc { target_os = "linux", target_os = "netbsd", target_os = "openbsd", // OpenBSD 2.7 + all(target_os = "macos", target_arch = "aarch64"), ))] pub fn write_vectored_at(&self, bufs: &[IoSlice<'_>], offset: u64) -> io::Result { let ret = cvt(unsafe { @@ -514,14 +527,15 @@ impl FileDesc { // We support old MacOS, iOS, watchOS, tvOS and visionOS. `pwritev` was added in the following // Apple OS versions: - // ios 14.0 - // tvos 14.0 - // macos 11.0 - // watchos 7.0 + // iOS 14.0 + // tvOS 14.0 + // macOS 11.0 + // watchOS 7.0 // - // These versions may be newer than the minimum supported versions of OS's we support so we must - // use "weak" linking. - #[cfg(target_vendor = "apple")] + // Since macOS 11.0 is also the first version with AArch64 support, we can + // `pwritev` unconditionally there. But on all other targets we must use + // "weak" linking. + #[cfg(all(target_vendor = "apple", not(all(target_os = "macos", target_arch = "aarch64")),))] pub fn write_vectored_at(&self, bufs: &[IoSlice<'_>], offset: u64) -> io::Result { weak!( fn pwritev( @@ -561,6 +575,7 @@ impl FileDesc { target_os = "redox", target_os = "vxworks", target_os = "nto", + target_os = "qnx", target_os = "wasi", )))] pub fn set_cloexec(&self) -> io::Result<()> { @@ -585,6 +600,7 @@ impl FileDesc { target_os = "redox", target_os = "vxworks", target_os = "nto", + target_os = "qnx", target_os = "wasi", ))] pub fn set_cloexec(&self) -> io::Result<()> { @@ -640,7 +656,7 @@ impl<'a> Read for &'a FileDesc { (**self).read(buf) } - fn read_buf(&mut self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { (**self).read_buf(cursor) } diff --git a/library/std/src/sys/fs/common.rs b/library/std/src/sys/fs/common.rs index 4d47d392a8268..edc31d21ca1fa 100644 --- a/library/std/src/sys/fs/common.rs +++ b/library/std/src/sys/fs/common.rs @@ -1,8 +1,10 @@ #![allow(dead_code)] // not used on all platforms +use crate::fs::{remove_file, rename}; use crate::io::{self, Error, ErrorKind}; use crate::path::{Path, PathBuf}; -use crate::sys::fs::{File, OpenOptions}; +use crate::sys::IntoInner; +use crate::sys::fs::{File, FileAttr, OpenOptions}; use crate::sys::helpers::ignore_notfound; use crate::{fmt, fs}; @@ -70,7 +72,19 @@ impl Dir { } pub fn open_file(&self, path: &Path, opts: &OpenOptions) -> io::Result { - File::open(&self.path.join(path), &opts) + File::open(&self.path.join(path), opts) + } + + pub fn metadata(&self) -> io::Result { + self.path.metadata().map(|m| m.into_inner()) + } + + pub fn remove_file(&self, path: &Path) -> io::Result<()> { + remove_file(self.path.join(path)) + } + + pub fn rename(&self, from: &Path, to_dir: &Self, to: &Path) -> io::Result<()> { + rename(self.path.join(from), to_dir.path.join(to)) } } diff --git a/library/std/src/sys/fs/hermit.rs b/library/std/src/sys/fs/hermit.rs index 1e281eb0d9d18..180dc08b4b04a 100644 --- a/library/std/src/sys/fs/hermit.rs +++ b/library/std/src/sys/fs/hermit.rs @@ -1,6 +1,7 @@ -use crate::ffi::{CStr, OsStr, OsString, c_char}; +use crate::ffi::{CStr, OsStr, OsString}; use crate::fs::TryLockError; -use crate::io::{self, BorrowedCursor, Error, ErrorKind, IoSlice, IoSliceMut, SeekFrom}; +use crate::io::{self, BorrowedCursor, ErrorKind, IoSlice, IoSliceMut, SeekFrom}; +use crate::mem::MaybeUninit; use crate::os::hermit::ffi::OsStringExt; use crate::os::hermit::hermit_abi::{ self, DT_DIR, DT_LNK, DT_REG, DT_UNKNOWN, O_APPEND, O_CREAT, O_DIRECTORY, O_EXCL, O_RDONLY, @@ -12,9 +13,10 @@ use crate::sync::Arc; use crate::sys::fd::FileDesc; pub use crate::sys::fs::common::{Dir, copy, exists}; use crate::sys::helpers::run_path_with_cstr; +use crate::sys::io::DEFAULT_BUF_SIZE; use crate::sys::time::SystemTime; use crate::sys::{AsInner, AsInnerMut, FromInner, IntoInner, cvt, unsupported, unsupported_err}; -use crate::{fmt, mem}; +use crate::{cmp, fmt, mem, slice}; #[derive(Debug)] pub struct File(FileDesc); @@ -33,29 +35,75 @@ impl FileAttr { // all DirEntry's will have a reference to this struct struct InnerReadDir { root: PathBuf, - dir: Vec, -} - -impl InnerReadDir { - pub fn new(root: PathBuf, dir: Vec) -> Self { - Self { root, dir } - } } pub struct ReadDir { inner: Arc, + fd: FileDesc, + buf: GetdentsBuffer, +} + +/// A buffer containing [`dirent64`]s, filled with [`getdents64`]. +/// +/// This struct is roughly modeled after the `BufReader`'s `Buffer`. +struct GetdentsBuffer { + // The buffer. + buf: Box<[MaybeUninit]>, + // The current seek offset into `buf`, must always be <= `filled`. pos: usize, + // Each call to `fill_buf` sets `filled` to indicate how many bytes at the start of `buf` are + // initialized with bytes from a read. + filled: usize, } -impl ReadDir { - fn new(inner: InnerReadDir) -> Self { - Self { inner: Arc::new(inner), pos: 0 } +impl GetdentsBuffer { + /// Creates a new buffer with at least `capacity` bytes for use with dirent. + fn with_capacity(capacity: usize) -> Self { + let buf = Box::new_uninit_slice(capacity.div_ceil(size_of::())); + Self { buf, pos: 0, filled: 0 } + } + + fn buffer(&self) -> &[u8] { + // SAFETY: self.pos and self.filled are valid, and self.filled >= self.pos, and + // that region is initialized because those are all invariants of this type. + unsafe { + let ptr = self.buf.as_ptr().cast::>().add(self.pos); + slice::from_raw_parts(ptr, self.filled - self.pos).assume_init_ref() + } + } + + fn consume(&mut self, amt: usize) { + self.pos = cmp::min(self.pos + amt, self.filled); + } + + fn fill_buf(&mut self, fd: BorrowedFd<'_>) -> io::Result<&[u8]> { + // If we've reached the end of our internal buffer then we need to fetch + // some more data from the reader. + // Branch using `>=` instead of the more correct `==` + // to tell the compiler that the pos..cap slice is always valid. + if self.pos >= self.filled { + debug_assert!(self.pos == self.filled); + + let result = unsafe { + cvt(hermit_abi::getdents64( + fd.as_raw_fd(), + self.buf.as_mut_ptr().cast(), + self.buf.len() * size_of::(), + )) + }; + + self.pos = 0; + self.filled = 0; + + self.filled = result? as usize; + } + + Ok(self.buffer()) } } pub struct DirEntry { - /// path to the entry - root: PathBuf, + dir: Arc, /// 64-bit inode number ino: u64, /// File type @@ -109,15 +157,15 @@ pub struct DirBuilder { impl FileAttr { pub fn modified(&self) -> io::Result { - Ok(SystemTime::new(self.stat_val.st_mtim.tv_sec, self.stat_val.st_mtim.tv_nsec)) + SystemTime::new(self.stat_val.st_mtim.tv_sec, self.stat_val.st_mtim.tv_nsec.into()) } pub fn accessed(&self) -> io::Result { - Ok(SystemTime::new(self.stat_val.st_atim.tv_sec, self.stat_val.st_atim.tv_nsec)) + SystemTime::new(self.stat_val.st_atim.tv_sec, self.stat_val.st_atim.tv_nsec.into()) } pub fn created(&self) -> io::Result { - Ok(SystemTime::new(self.stat_val.st_ctim.tv_sec, self.stat_val.st_ctim.tv_nsec)) + SystemTime::new(self.stat_val.st_ctim.tv_sec, self.stat_val.st_ctim.tv_nsec.into()) } pub fn size(&self) -> u64 { @@ -185,48 +233,59 @@ impl Iterator for ReadDir { type Item = io::Result; fn next(&mut self) -> Option> { - let mut counter: usize = 0; - let mut offset: usize = 0; - - // loop over all directory entries and search the entry for the current position loop { - // leave function, if the loop reaches the of the buffer (with all entries) - if offset >= self.inner.dir.len() { + let buf = match self.buf.fill_buf(self.fd.as_fd()) { + Ok(buf) => buf, + Err(err) => return Some(Err(err)), + }; + + if buf.len() == 0 { + // No more entries left. return None; } - let dir = unsafe { &*(self.inner.dir.as_ptr().add(offset) as *const dirent64) }; - - if counter == self.pos { - self.pos += 1; - - // After dirent64, the file name is stored. d_reclen represents the length of the dirent64 - // plus the length of the file name. Consequently, file name has a size of d_reclen minus - // the size of dirent64. The file name is always a C string and terminated by `\0`. - // Consequently, we are able to ignore the last byte. - let name_bytes = - unsafe { CStr::from_ptr(&dir.d_name as *const _ as *const c_char).to_bytes() }; - let entry = DirEntry { - root: self.inner.root.clone(), - ino: dir.d_ino, - type_: dir.d_type, - name: OsString::from_vec(name_bytes.to_vec()), - }; - - return Some(Ok(entry)); + let entry_ptr = buf.as_ptr().cast::(); + + // The dirent64 struct is a weird imaginary thing that isn't ever supposed + // to be worked with by value. Its trailing d_name field is declared + // variously as [c_char; 256] or [c_char; 1] on different systems but + // either way that size is meaningless; only the offset of d_name is + // meaningful. The dirent64 pointers that libc returns from getdents64 are + // allowed to point to allocations smaller _or_ LARGER than implied by the + // definition of the struct. + // + // As such, we need to be even more careful with dirent64 than if its + // contents were "simply" partially initialized data. + // + // Like for uninitialized contents, converting entry_ptr to `&dirent64` + // would not be legal. However, we can use `&raw const (*entry_ptr).d_name` + // to refer the fields individually, because that operation is equivalent + // to `byte_offset` and thus does not require the full extent of `*entry_ptr` + // to be in bounds of the same allocation, only the offset of the field + // being referenced. + + self.buf.consume(usize::from(unsafe { (*entry_ptr).d_reclen })); + + // d_name is guaranteed to be null-terminated. + let name = unsafe { CStr::from_ptr((&raw const (*entry_ptr).d_name).cast()) }; + let name_bytes = name.to_bytes(); + if name_bytes == b"." || name_bytes == b".." { + continue; } - counter += 1; - - // move to the next dirent64, which is directly stored after the previous one - offset = offset + usize::from(dir.d_reclen); + return Some(Ok(DirEntry { + dir: Arc::clone(&self.inner), + ino: unsafe { (*entry_ptr).d_ino }, + type_: unsafe { (*entry_ptr).d_type }, + name: OsString::from_vec(name_bytes.to_vec()), + })); } } } impl DirEntry { pub fn path(&self) -> PathBuf { - self.root.join(self.file_name_os_str()) + self.dir.root.join(self.file_name_os_str()) } pub fn file_name(&self) -> OsString { @@ -342,7 +401,7 @@ impl File { } let fd = unsafe { cvt(hermit_abi::open(path.as_ptr(), flags, mode))? }; - Ok(File(unsafe { FileDesc::from_raw_fd(fd as i32) })) + Ok(File(unsafe { FileDesc::from_raw_fd(fd) })) } pub fn file_attr(&self) -> io::Result { @@ -352,7 +411,7 @@ impl File { } pub fn fsync(&self) -> io::Result<()> { - Err(Error::from_raw_os_error(22)) + unsupported() } pub fn datasync(&self) -> io::Result<()> { @@ -380,7 +439,7 @@ impl File { } pub fn truncate(&self, _size: u64) -> io::Result<()> { - Err(Error::from_raw_os_error(22)) + unsupported() } pub fn read(&self, buf: &mut [u8]) -> io::Result { @@ -396,7 +455,7 @@ impl File { self.0.is_read_vectored() } - pub fn read_buf(&self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { self.0.read_buf(cursor) } @@ -431,15 +490,15 @@ impl File { } pub fn duplicate(&self) -> io::Result { - Err(Error::from_raw_os_error(22)) + unsupported() } pub fn set_permissions(&self, _perm: FilePermissions) -> io::Result<()> { - Err(Error::from_raw_os_error(22)) + unsupported() } pub fn set_times(&self, _times: FileTimes) -> io::Result<()> { - Err(Error::from_raw_os_error(22)) + unsupported() } } @@ -516,42 +575,14 @@ pub fn readdir(path: &Path) -> io::Result { let fd_raw = run_path_with_cstr(path, &|path| { cvt(unsafe { hermit_abi::open(path.as_ptr(), O_RDONLY | O_DIRECTORY, 0) }) })?; - let fd = unsafe { FileDesc::from_raw_fd(fd_raw as i32) }; - let root = path.to_path_buf(); - - // read all director entries - let mut vec: Vec = Vec::new(); - let mut sz = 512; - loop { - // reserve memory to receive all directory entries - vec.resize(sz, 0); - - let readlen = unsafe { - hermit_abi::getdents64(fd.as_raw_fd(), vec.as_mut_ptr() as *mut dirent64, sz) - }; - if readlen > 0 { - // shrink down to the minimal size - vec.resize(readlen.try_into().unwrap(), 0); - break; - } - - // if the buffer is too small, getdents64 returns EINVAL - // otherwise, getdents64 returns an error number - if readlen != (-hermit_abi::errno::EINVAL).into() { - return Err(Error::from_raw_os_error(readlen.try_into().unwrap())); - } + let fd = unsafe { FileDesc::from_raw_fd(fd_raw) }; - // we don't have enough memory => try to increase the vector size - sz = sz * 2; - - // 1 MB for directory entries should be enough - // stop here to avoid an endless loop - if sz > 0x100000 { - return Err(Error::from(ErrorKind::Uncategorized)); - } - } + let root = path.to_path_buf(); + let inner = Arc::new(InnerReadDir { root }); + let buf_size = usize::max(DEFAULT_BUF_SIZE, size_of::()); + let buf = GetdentsBuffer::with_capacity(buf_size); - Ok(ReadDir::new(InnerReadDir::new(root, vec))) + Ok(ReadDir { inner, fd, buf }) } pub fn unlink(path: &Path) -> io::Result<()> { @@ -563,15 +594,19 @@ pub fn rename(_old: &Path, _new: &Path) -> io::Result<()> { } pub fn set_perm(_p: &Path, _perm: FilePermissions) -> io::Result<()> { - Err(Error::from_raw_os_error(22)) + unsupported() +} + +pub fn set_perm_nofollow(_p: &Path, _perm: FilePermissions) -> io::Result<()> { + unsupported() } pub fn set_times(_p: &Path, _times: FileTimes) -> io::Result<()> { - Err(Error::from_raw_os_error(22)) + unsupported() } pub fn set_times_nofollow(_p: &Path, _times: FileTimes) -> io::Result<()> { - Err(Error::from_raw_os_error(22)) + unsupported() } pub fn rmdir(path: &Path) -> io::Result<()> { diff --git a/library/std/src/sys/fs/mod.rs b/library/std/src/sys/fs/mod.rs index 0c297c5766b82..b2666eb2a3da9 100644 --- a/library/std/src/sys/fs/mod.rs +++ b/library/std/src/sys/fs/mod.rs @@ -9,20 +9,22 @@ cfg_select! { any(target_family = "unix", target_os = "wasi") => { mod unix; use unix as imp; - #[cfg(not(target_os = "wasi"))] - pub use unix::{chown, fchown, lchown, mkfifo}; + #[cfg(any(target_os = "linux", target_os = "android"))] + pub(super) use unix::CachedFileMetadata; #[cfg(not(any(target_os = "fuchsia", target_os = "wasi")))] pub use unix::chroot; #[cfg(not(target_os = "wasi"))] pub(crate) use unix::debug_assert_fd_is_open; - #[cfg(any(target_os = "linux", target_os = "android"))] - pub(super) use unix::CachedFileMetadata; + #[cfg(not(target_os = "wasi"))] + pub use unix::{chown, fchown, lchown, mkfifo}; + use crate::sys::helpers::run_path_with_cstr as with_native_path; } target_os = "windows" => { mod windows; use windows as imp; - pub use windows::{symlink_inner, junction_point}; + pub use windows::{junction_point, symlink_inner}; + use crate::sys::path::with_native_path; } target_os = "hermit" => { @@ -120,28 +122,8 @@ pub fn set_permissions(path: &Path, perm: FilePermissions) -> io::Result<()> { with_native_path(path, &|path| imp::set_perm(path, perm.clone())) } -#[cfg(all(unix, not(target_os = "vxworks")))] -pub fn set_permissions_nofollow(path: &Path, perm: crate::fs::Permissions) -> io::Result<()> { - use crate::fs::OpenOptions; - - let mut options = OpenOptions::new(); - - // ESP-IDF and Horizon do not support O_NOFOLLOW, so we skip setting it. - // Their filesystems do not have symbolic links, so no special handling is required. - #[cfg(not(any(target_os = "espidf", target_os = "horizon")))] - { - use crate::os::unix::fs::OpenOptionsExt; - options.custom_flags(libc::O_NOFOLLOW); - } - - options.open(path)?.set_permissions(perm) -} - -#[cfg(any(not(unix), target_os = "vxworks"))] -pub fn set_permissions_nofollow(_path: &Path, _perm: crate::fs::Permissions) -> io::Result<()> { - crate::unimplemented!( - "`set_permissions_nofollow` is currently only implemented on Unix platforms" - ) +pub fn set_permissions_nofollow(path: &Path, perm: FilePermissions) -> io::Result<()> { + with_native_path(path, &|path| imp::set_perm_nofollow(path, perm.clone())) } pub fn canonicalize(path: &Path) -> io::Result { diff --git a/library/std/src/sys/fs/motor.rs b/library/std/src/sys/fs/motor.rs index 2ae01db24be5c..a76f64a47c24a 100644 --- a/library/std/src/sys/fs/motor.rs +++ b/library/std/src/sys/fs/motor.rs @@ -203,7 +203,7 @@ impl File { false } - pub fn read_buf(&self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { crate::io::default_read_buf(|buf| self.read(buf), cursor) } @@ -319,6 +319,11 @@ pub fn remove_dir_all(path: &Path) -> io::Result<()> { } pub fn set_perm(path: &Path, perm: FilePermissions) -> io::Result<()> { + // Motor does not support symlinks + set_perm_nofollow(path, perm) +} + +pub fn set_perm_nofollow(path: &Path, perm: FilePermissions) -> io::Result<()> { let path = path.to_str().ok_or(io::Error::from(io::ErrorKind::InvalidFilename))?; moto_rt::fs::set_perm(path, perm.rt_perm).map_err(map_motor_error) } diff --git a/library/std/src/sys/fs/solid.rs b/library/std/src/sys/fs/solid.rs index 114ffda57bc52..bd963b1d2f038 100644 --- a/library/std/src/sys/fs/solid.rs +++ b/library/std/src/sys/fs/solid.rs @@ -383,7 +383,7 @@ impl File { } } - pub fn read_buf(&self, mut cursor: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, mut cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { unsafe { let len = cursor.capacity(); let mut out_num_bytes = MaybeUninit::uninit(); @@ -401,7 +401,7 @@ impl File { // Safety: `num_bytes_read` bytes were written to the unfilled // portion of the buffer - cursor.advance_unchecked(num_bytes_read); + cursor.advance(num_bytes_read); Ok(()) } @@ -531,6 +531,11 @@ pub fn rename(old: &Path, new: &Path) -> io::Result<()> { } pub fn set_perm(p: &Path, perm: FilePermissions) -> io::Result<()> { + // Solid does not support symlinks + set_perm_nofollow(p, perm) +} + +pub fn set_perm_nofollow(p: &Path, perm: FilePermissions) -> io::Result<()> { error::SolidError::err_if_negative(unsafe { abi::SOLID_FS_Chmod(cstr(p)?.as_ptr(), perm.0.into()) }) diff --git a/library/std/src/sys/fs/uefi.rs b/library/std/src/sys/fs/uefi.rs index 8135519317a02..1a0da329ce1a3 100644 --- a/library/std/src/sys/fs/uefi.rs +++ b/library/std/src/sys/fs/uefi.rs @@ -332,7 +332,7 @@ impl File { false } - pub fn read_buf(&self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { crate::io::default_read_buf(|buf| self.read(buf), cursor) } @@ -480,6 +480,11 @@ pub fn rename(old: &Path, new: &Path) -> io::Result<()> { } pub fn set_perm(p: &Path, perm: FilePermissions) -> io::Result<()> { + // UEFI does not support symlinks + set_perm_nofollow(p, perm) +} + +pub fn set_perm_nofollow(p: &Path, perm: FilePermissions) -> io::Result<()> { let f = uefi_fs::File::from_path(p, file::MODE_READ | file::MODE_WRITE, 0)?; set_perm_inner(&f, perm) } @@ -588,6 +593,11 @@ mod uefi_fs { path: crate::path::PathBuf, } + // SAFETY: UEFI has no regular threads, and as per + // std does not support being invoked from "irregular threads" such as interrupt handlers or other + // CPU cores that run outside the scope of UEFI. + unsafe impl Send for File {} + impl File { pub(crate) fn from_path(path: &Path, open_mode: u64, attr: u64) -> io::Result { let absolute = crate::path::absolute(path)?; diff --git a/library/std/src/sys/fs/unix.rs b/library/std/src/sys/fs/unix.rs index 3ca84db0f47fc..b33ebadebe4ad 100644 --- a/library/std/src/sys/fs/unix.rs +++ b/library/std/src/sys/fs/unix.rs @@ -21,40 +21,6 @@ use libc::dirfd; use libc::fstatat as fstatat64; #[cfg(any(all(target_os = "linux", not(target_env = "musl")), target_os = "hurd"))] use libc::fstatat64; -#[cfg(any( - target_os = "aix", - target_os = "android", - target_os = "freebsd", - target_os = "fuchsia", - target_os = "illumos", - target_os = "nto", - target_os = "redox", - target_os = "solaris", - target_os = "vita", - target_os = "wasi", - all(target_os = "linux", target_env = "musl"), -))] -use libc::readdir as readdir64; -#[cfg(not(any( - target_os = "aix", - target_os = "android", - target_os = "freebsd", - target_os = "fuchsia", - target_os = "hurd", - target_os = "illumos", - target_os = "l4re", - target_os = "linux", - target_os = "nto", - target_os = "redox", - target_os = "solaris", - target_os = "vita", - target_os = "wasi", -)))] -use libc::readdir_r as readdir64_r; -#[cfg(any(all(target_os = "linux", not(target_env = "musl")), target_os = "hurd"))] -use libc::readdir64; -#[cfg(target_os = "l4re")] -use libc::readdir64_r; use libc::{c_int, mode_t}; #[cfg(target_os = "android")] use libc::{ @@ -63,19 +29,20 @@ use libc::{ }; #[cfg(not(any( all(target_os = "linux", not(target_env = "musl")), - target_os = "l4re", target_os = "android", target_os = "hurd", + target_os = "l4re", )))] use libc::{ dirent as dirent64, fstat as fstat64, ftruncate as ftruncate64, lseek as lseek64, lstat as lstat64, off_t as off64_t, open as open64, stat as stat64, }; -#[cfg(any( - all(target_os = "linux", not(target_env = "musl")), - target_os = "l4re", - target_os = "hurd" -))] +#[cfg(target_os = "l4re")] +use libc::{ + dirent64, fstat as fstat64, ftruncate as ftruncate64, lseek as lseek64, lstat as lstat64, + off_t as off64_t, open as open64, stat as stat64, +}; +#[cfg(any(all(target_os = "linux", not(target_env = "musl")), target_os = "hurd"))] use libc::{dirent64, fstat64, ftruncate64, lseek64, lstat64, off64_t, open64, stat64}; use crate::ffi::{CStr, OsStr, OsString}; @@ -100,6 +67,28 @@ use crate::sys::weak::weak; use crate::sys::{AsInner, AsInnerMut, FromInner, IntoInner, cvt, cvt_r}; use crate::{mem, ptr}; +// Used by rustc for checking the definitions of other function with the same symbol names +// +// See the `invalid_runtime_symbols_definitions` lint. +#[cfg(not(test))] +mod runtime_symbols { + use core::ffi::{c_char, c_int, c_size_t, c_ssize_t, c_void}; + + unsafe extern "C" { + #[rustc_canonical_symbol] + fn open(pathname: *const c_char, flags: c_int, ...) -> c_int; + + #[rustc_canonical_symbol] + fn read(fd: c_int, buf: *mut c_void, count: c_size_t) -> c_ssize_t; + + #[rustc_canonical_symbol] + fn write(fd: c_int, buf: *const c_void, count: c_size_t) -> c_ssize_t; + + #[rustc_canonical_symbol] + fn close(fd: c_int) -> c_int; + } +} + pub struct File(FileDesc); // FIXME: This should be available on Linux with all `target_env`. @@ -282,7 +271,9 @@ cfg_select! { target_os = "horizon", target_os = "vita", target_os = "nto", + target_os = "qnx", target_os = "vxworks", + target_os = "l4re", ) => { pub use crate::sys::fs::common::Dir; } @@ -339,14 +330,14 @@ fn get_path_from_fd(fd: c_int) -> Option { // alternatives. If a better method is invented, it should be used // instead. let mut buf = vec![0; libc::PATH_MAX as usize]; - let n = unsafe { libc::fcntl(fd, libc::F_GETPATH, buf.as_ptr()) }; + let n = unsafe { libc::fcntl(fd, libc::F_GETPATH, buf.as_mut_ptr()) }; if n == -1 { cfg_select! { target_os = "netbsd" => { // fallback to procfs as last resort let mut p = PathBuf::from("/proc/self/fd"); p.push(&fd.to_string()); - return run_path_with_cstr(&p, &readlink).ok() + return run_path_with_cstr(&p, &readlink).ok(); } _ => { return None; @@ -375,7 +366,7 @@ fn get_path_from_fd(fd: c_int) -> Option { #[cfg(target_os = "vxworks")] fn get_path(fd: c_int) -> Option { let mut buf = vec![0; libc::PATH_MAX as usize]; - let n = unsafe { libc::ioctl(fd, libc::FIOGETNAME, buf.as_ptr()) }; + let n = unsafe { libc::ioctl(fd, libc::FIOGETNAME, buf.as_mut_ptr()) }; if n == -1 { return None; } @@ -401,20 +392,6 @@ fn get_path_from_fd(fd: c_int) -> Option { get_path(fd) } -#[cfg(any( - target_os = "aix", - target_os = "android", - target_os = "freebsd", - target_os = "fuchsia", - target_os = "hurd", - target_os = "illumos", - target_os = "linux", - target_os = "nto", - target_os = "redox", - target_os = "solaris", - target_os = "vita", - target_os = "wasi", -))] pub struct DirEntry { dir: Arc, entry: dirent64_min, @@ -427,52 +404,21 @@ pub struct DirEntry { // Define a minimal subset of fields we need from `dirent64`, especially since // we're not using the immediate `d_name` on these targets. Keeping this as an // `entry` field in `DirEntry` helps reduce the `cfg` boilerplate elsewhere. -#[cfg(any( - target_os = "aix", - target_os = "android", - target_os = "freebsd", - target_os = "fuchsia", - target_os = "hurd", - target_os = "illumos", - target_os = "linux", - target_os = "nto", - target_os = "redox", - target_os = "solaris", - target_os = "vita", - target_os = "wasi", -))] struct dirent64_min { d_ino: u64, #[cfg(not(any( target_os = "solaris", target_os = "illumos", + target_os = "haiku", + target_os = "vxworks", target_os = "aix", target_os = "nto", + target_os = "qnx", target_os = "vita", )))] d_type: u8, } -#[cfg(not(any( - target_os = "aix", - target_os = "android", - target_os = "freebsd", - target_os = "fuchsia", - target_os = "hurd", - target_os = "illumos", - target_os = "linux", - target_os = "nto", - target_os = "redox", - target_os = "solaris", - target_os = "vita", - target_os = "wasi", -)))] -pub struct DirEntry { - dir: Arc, - // The full entry includes a fixed-length `d_name`. - entry: dirent64, -} - #[derive(Clone)] pub struct OpenOptions { // generic @@ -599,19 +545,26 @@ impl FileAttr { #[cfg(target_os = "aix")] impl FileAttr { pub fn modified(&self) -> io::Result { - SystemTime::new(self.stat.st_mtime.tv_sec as i64, self.stat.st_mtime.tv_nsec as i64) + SystemTime::new(self.stat.st_mtim.tv_sec as i64, self.stat.st_mtim.tv_nsec as i64) } pub fn accessed(&self) -> io::Result { - SystemTime::new(self.stat.st_atime.tv_sec as i64, self.stat.st_atime.tv_nsec as i64) + SystemTime::new(self.stat.st_atim.tv_sec as i64, self.stat.st_atim.tv_nsec as i64) } pub fn created(&self) -> io::Result { - SystemTime::new(self.stat.st_ctime.tv_sec as i64, self.stat.st_ctime.tv_nsec as i64) + SystemTime::new(self.stat.st_ctim.tv_sec as i64, self.stat.st_ctim.tv_nsec as i64) } } -#[cfg(not(any(target_os = "netbsd", target_os = "nto", target_os = "aix", target_os = "wasi")))] +#[cfg(not(any( + target_os = "netbsd", + target_os = "nto", + target_os = "qnx", + target_os = "aix", + target_os = "wasi", + target_os = "l4re" +)))] impl FileAttr { #[cfg(not(any( target_os = "vxworks", @@ -634,7 +587,7 @@ impl FileAttr { } #[cfg(any( - target_os = "vxworks", + all(target_os = "vxworks", vxworks_lt_25_09), target_os = "espidf", target_os = "vita", target_os = "rtems", @@ -643,7 +596,12 @@ impl FileAttr { SystemTime::new(self.stat.st_mtime as i64, 0) } - #[cfg(any(target_os = "horizon", target_os = "hurd", target_os = "nuttx"))] + #[cfg(any( + target_os = "horizon", + target_os = "hurd", + target_os = "nuttx", + all(target_os = "vxworks", not(vxworks_lt_25_09)) + ))] pub fn modified(&self) -> io::Result { SystemTime::new(self.stat.st_mtim.tv_sec as i64, self.stat.st_mtim.tv_nsec as i64) } @@ -669,7 +627,7 @@ impl FileAttr { } #[cfg(any( - target_os = "vxworks", + all(target_os = "vxworks", vxworks_lt_25_09), target_os = "espidf", target_os = "vita", target_os = "rtems" @@ -678,7 +636,12 @@ impl FileAttr { SystemTime::new(self.stat.st_atime as i64, 0) } - #[cfg(any(target_os = "horizon", target_os = "hurd", target_os = "nuttx"))] + #[cfg(any( + target_os = "horizon", + target_os = "hurd", + target_os = "nuttx", + all(target_os = "vxworks", not(vxworks_lt_25_09)) + ))] pub fn accessed(&self) -> io::Result { SystemTime::new(self.stat.st_atim.tv_sec as i64, self.stat.st_atim.tv_nsec as i64) } @@ -726,7 +689,7 @@ impl FileAttr { } } -#[cfg(any(target_os = "nto", target_os = "wasi"))] +#[cfg(any(target_os = "nto", target_os = "qnx", target_os = "wasi", target_os = "l4re"))] impl FileAttr { pub fn modified(&self) -> io::Result { SystemTime::new(self.stat.st_mtim.tv_sec, self.stat.st_mtim.tv_nsec.into()) @@ -835,47 +798,89 @@ impl fmt::Debug for ReadDir { impl Iterator for ReadDir { type Item = io::Result; - #[cfg(any( - target_os = "aix", - target_os = "android", - target_os = "freebsd", - target_os = "fuchsia", - target_os = "hurd", - target_os = "illumos", - target_os = "linux", - target_os = "nto", - target_os = "redox", - target_os = "solaris", - target_os = "vita", - target_os = "wasi", - ))] fn next(&mut self) -> Option> { - use crate::sys::io::{errno, set_errno}; - if self.end_of_stream { return None; } unsafe { loop { - // As of POSIX.1-2017, readdir() is not required to be thread safe; only - // readdir_r() is. However, readdir_r() cannot correctly handle platforms - // with unlimited or variable NAME_MAX. Many modern platforms guarantee - // thread safety for readdir() as long an individual DIR* is not accessed - // concurrently, which is sufficient for Rust. - set_errno(0); - let entry_ptr: *const dirent64 = readdir64(self.inner.dirp.0); - if entry_ptr.is_null() { - // We either encountered an error, or reached the end. Either way, - // the next call to next() should return None. - self.end_of_stream = true; - - // To distinguish between errors and end-of-directory, we had to clear - // errno beforehand to check for an error now. - return match errno() { - 0 => None, - e => Some(Err(Error::from_raw_os_error(e))), - }; + // POSIX.1-2024 formalized what was already guaranteed by a lot + // of implementations and required readdir() to be thread-safe as + // long as an individual DIR* is not accessed concurrently. Taking + // a mutable reference to the `ReadDir` iterator prevents that. + // Even POSIX.1-1994 specified that the data in the returned + // dirent + // > is not overwritten by another call to readdir() on a + // > different directory stream. + // + // and that guarantee together with the requirement that the + // underlying syscalls need to be thread-safe because of readdir_r + // make it very unlikely for an implementation to be non-conforming. + // Nevertheless, there are still some platforms where we either + // cannot confirm `readdir` to be thread-safe or know that it + // isn't. + cfg_select! { + any( + target_os = "espidf", // readdir truly isn't thread-safe. + target_os = "lynxos178", + target_os = "qurt", + target_os = "rtems", + target_os = "vxworks", + ) => { + use crate::mem::MaybeUninit; + + let mut entry = MaybeUninit::uninit(); + let mut entry_ptr: *mut dirent64 = ptr::null_mut(); + let err = + libc::readdir_r(self.inner.dirp.0, entry.as_mut_ptr(), &mut entry_ptr); + if err != 0 { + if entry_ptr.is_null() { + // We encountered an error (which will be returned in this iteration), but + // we also reached the end of the directory stream. The `end_of_stream` + // flag is enabled to make sure that we return `None` in the next iteration + // (instead of looping forever) + self.end_of_stream = true; + } + return Some(Err(Error::from_raw_os_error(err))); + } + if entry_ptr.is_null() { + return None; + } + + let entry_ptr = entry_ptr.cast_const(); + } + _ => { + #[cfg(not(any( + all(target_os = "linux", not(target_env = "musl")), + target_os = "hurd", + target_os = "l4re", + )))] + use libc::readdir as readdir64; + #[cfg(any( + all(target_os = "linux", not(target_env = "musl")), + target_os = "hurd", + target_os = "l4re" + ))] + use libc::readdir64; + + use crate::sys::io::{errno, set_errno}; + + set_errno(0); + let entry_ptr: *const dirent64 = readdir64(self.inner.dirp.0); + if entry_ptr.is_null() { + // We either encountered an error, or reached the end. Either way, + // the next call to next() should return None. + self.end_of_stream = true; + + // To distinguish between errors and end-of-directory, we had to clear + // errno beforehand to check for an error now. + return match errno() { + 0 => None, + e => Some(Err(Error::from_raw_os_error(e))), + }; + } + } } // The dirent64 struct is a weird imaginary thing that isn't ever supposed @@ -906,24 +911,38 @@ impl Iterator for ReadDir { // When loading from a field, we can skip the `&raw const`; `(*entry_ptr).d_ino` as // a value expression will do the right thing: `byte_offset` to the field and then // only access those bytes. - #[cfg(not(target_os = "vita"))] let entry = dirent64_min { - #[cfg(target_os = "freebsd")] + #[cfg(any( + target_os = "dragonfly", + target_os = "freebsd", + target_os = "netbsd", + target_os = "openbsd", + ))] d_ino: (*entry_ptr).d_fileno, - #[cfg(not(target_os = "freebsd"))] + #[cfg(any(target_os = "nuttx", target_os = "vita",))] + d_ino: 0, + #[cfg(not(any( + target_os = "dragonfly", + target_os = "freebsd", + target_os = "netbsd", + target_os = "nuttx", + target_os = "openbsd", + target_os = "vita", + )))] d_ino: (*entry_ptr).d_ino as u64, #[cfg(not(any( target_os = "solaris", target_os = "illumos", + target_os = "haiku", + target_os = "vxworks", target_os = "aix", target_os = "nto", + target_os = "qnx", + target_os = "vita", )))] d_type: (*entry_ptr).d_type as u8, }; - #[cfg(target_os = "vita")] - let entry = dirent64_min { d_ino: 0u64 }; - return Some(Ok(DirEntry { entry, name: name.to_owned(), @@ -932,50 +951,6 @@ impl Iterator for ReadDir { } } } - - #[cfg(not(any( - target_os = "aix", - target_os = "android", - target_os = "freebsd", - target_os = "fuchsia", - target_os = "hurd", - target_os = "illumos", - target_os = "linux", - target_os = "nto", - target_os = "redox", - target_os = "solaris", - target_os = "vita", - target_os = "wasi", - )))] - fn next(&mut self) -> Option> { - if self.end_of_stream { - return None; - } - - unsafe { - let mut ret = DirEntry { entry: mem::zeroed(), dir: Arc::clone(&self.inner) }; - let mut entry_ptr = ptr::null_mut(); - loop { - let err = readdir64_r(self.inner.dirp.0, &mut ret.entry, &mut entry_ptr); - if err != 0 { - if entry_ptr.is_null() { - // We encountered an error (which will be returned in this iteration), but - // we also reached the end of the directory stream. The `end_of_stream` - // flag is enabled to make sure that we return `None` in the next iteration - // (instead of looping forever) - self.end_of_stream = true; - } - return Some(Err(Error::from_raw_os_error(err))); - } - if entry_ptr.is_null() { - return None; - } - if ret.name_bytes() != b"." && ret.name_bytes() != b".." { - return Some(Ok(ret)); - } - } - } - } } /// Aborts the process if a file desceriptor is not open, if debug asserts are enabled @@ -1005,6 +980,7 @@ impl Drop for DirStream { miri, target_os = "redox", target_os = "nto", + target_os = "qnx", target_os = "vita", target_os = "hurd", target_os = "espidf", @@ -1053,7 +1029,7 @@ impl DirEntry { ))] pub fn metadata(&self) -> io::Result { let fd = cvt(unsafe { dirfd(self.dir.dirp.0) })?; - let name = self.name_cstr().as_ptr(); + let name = self.name.as_ptr(); cfg_has_statx! { if let Some(ret) = unsafe { try_statx( @@ -1080,7 +1056,7 @@ impl DirEntry { target_os = "illumos", target_vendor = "apple", )), - miri + miri // no dirfd on Miri ))] pub fn metadata(&self) -> io::Result { run_path_with_cstr(&self.path(), &lstat) @@ -1093,7 +1069,9 @@ impl DirEntry { target_os = "vxworks", target_os = "aix", target_os = "nto", + target_os = "qnx", target_os = "vita", + target_os = "l4re", ))] pub fn file_type(&self) -> io::Result { self.metadata().map(|m| m.file_type()) @@ -1106,7 +1084,9 @@ impl DirEntry { target_os = "vxworks", target_os = "aix", target_os = "nto", + target_os = "qnx", target_os = "vita", + target_os = "l4re", )))] pub fn file_type(&self) -> io::Result { match self.entry.d_type { @@ -1121,107 +1101,12 @@ impl DirEntry { } } - #[cfg(any( - target_os = "aix", - target_os = "android", - target_os = "cygwin", - target_os = "emscripten", - target_os = "espidf", - target_os = "freebsd", - target_os = "fuchsia", - target_os = "haiku", - target_os = "horizon", - target_os = "hurd", - target_os = "illumos", - target_os = "l4re", - target_os = "linux", - target_os = "nto", - target_os = "redox", - target_os = "rtems", - target_os = "solaris", - target_os = "vita", - target_os = "vxworks", - target_os = "wasi", - target_vendor = "apple", - ))] pub fn ino(&self) -> u64 { - self.entry.d_ino as u64 - } - - #[cfg(any(target_os = "openbsd", target_os = "netbsd", target_os = "dragonfly"))] - pub fn ino(&self) -> u64 { - self.entry.d_fileno as u64 - } - - #[cfg(target_os = "nuttx")] - pub fn ino(&self) -> u64 { - // Leave this 0 for now, as NuttX does not provide an inode number - // in its directory entries. - 0 - } - - #[cfg(any( - target_os = "netbsd", - target_os = "openbsd", - target_os = "dragonfly", - target_vendor = "apple", - ))] - fn name_bytes(&self) -> &[u8] { - use crate::slice; - unsafe { - slice::from_raw_parts( - self.entry.d_name.as_ptr() as *const u8, - self.entry.d_namlen as usize, - ) - } - } - #[cfg(not(any( - target_os = "netbsd", - target_os = "openbsd", - target_os = "dragonfly", - target_vendor = "apple", - )))] - fn name_bytes(&self) -> &[u8] { - self.name_cstr().to_bytes() - } - - #[cfg(not(any( - target_os = "android", - target_os = "freebsd", - target_os = "linux", - target_os = "solaris", - target_os = "illumos", - target_os = "fuchsia", - target_os = "redox", - target_os = "aix", - target_os = "nto", - target_os = "vita", - target_os = "hurd", - target_os = "wasi", - )))] - fn name_cstr(&self) -> &CStr { - unsafe { CStr::from_ptr(self.entry.d_name.as_ptr()) } - } - #[cfg(any( - target_os = "android", - target_os = "freebsd", - target_os = "linux", - target_os = "solaris", - target_os = "illumos", - target_os = "fuchsia", - target_os = "redox", - target_os = "aix", - target_os = "nto", - target_os = "vita", - target_os = "hurd", - target_os = "wasi", - ))] - fn name_cstr(&self) -> &CStr { - &self.name + self.entry.d_ino } pub fn file_name_os_str(&self) -> &OsStr { - OsStr::from_bytes(self.name_bytes()) + OsStr::from_bytes(self.name.as_bytes()) } } @@ -1308,7 +1193,7 @@ impl OpenOptions { if self.truncate && !self.create_new { return Err(io::Error::new( io::ErrorKind::InvalidInput, - "creating or truncating a file requires write or append access", + "append and truncate cannot both be enabled", )); } } @@ -1409,7 +1294,9 @@ impl File { target_os = "netbsd", target_os = "openbsd", target_os = "nto", + target_os = "qnx", target_os = "hurd", + target_os = "l4re", ))] unsafe fn os_datasync(fd: c_int) -> c_int { libc::fdatasync(fd) @@ -1423,7 +1310,9 @@ impl File { target_os = "netbsd", target_os = "openbsd", target_os = "nto", + target_os = "qnx", target_os = "hurd", + target_os = "l4re", target_vendor = "apple", )))] unsafe fn os_datasync(fd: c_int) -> c_int { @@ -1431,257 +1320,138 @@ impl File { } } - #[cfg(any( - target_os = "freebsd", - target_os = "fuchsia", - target_os = "hurd", - target_os = "linux", - target_os = "netbsd", - target_os = "openbsd", - target_os = "cygwin", - target_os = "illumos", - target_os = "aix", - target_vendor = "apple", - ))] - pub fn lock(&self) -> io::Result<()> { - cvt(unsafe { libc::flock(self.as_raw_fd(), libc::LOCK_EX) })?; - return Ok(()); - } - - #[cfg(target_os = "solaris")] - pub fn lock(&self) -> io::Result<()> { - let mut flock: libc::flock = unsafe { mem::zeroed() }; - flock.l_type = libc::F_WRLCK as libc::c_short; - flock.l_whence = libc::SEEK_SET as libc::c_short; - cvt(unsafe { libc::fcntl(self.as_raw_fd(), libc::F_SETLKW, &flock) })?; - Ok(()) - } - - #[cfg(not(any( - target_os = "freebsd", - target_os = "fuchsia", - target_os = "hurd", - target_os = "linux", - target_os = "netbsd", - target_os = "openbsd", - target_os = "cygwin", - target_os = "solaris", - target_os = "illumos", - target_os = "aix", - target_vendor = "apple", - )))] pub fn lock(&self) -> io::Result<()> { - Err(io::const_error!(io::ErrorKind::Unsupported, "lock() not supported")) - } - - #[cfg(any( - target_os = "freebsd", - target_os = "fuchsia", - target_os = "hurd", - target_os = "linux", - target_os = "netbsd", - target_os = "openbsd", - target_os = "cygwin", - target_os = "illumos", - target_os = "aix", - target_vendor = "apple", - ))] - pub fn lock_shared(&self) -> io::Result<()> { - cvt(unsafe { libc::flock(self.as_raw_fd(), libc::LOCK_SH) })?; - return Ok(()); - } - - #[cfg(target_os = "solaris")] - pub fn lock_shared(&self) -> io::Result<()> { - let mut flock: libc::flock = unsafe { mem::zeroed() }; - flock.l_type = libc::F_RDLCK as libc::c_short; - flock.l_whence = libc::SEEK_SET as libc::c_short; - cvt(unsafe { libc::fcntl(self.as_raw_fd(), libc::F_SETLKW, &flock) })?; - Ok(()) - } - - #[cfg(not(any( - target_os = "freebsd", - target_os = "fuchsia", - target_os = "hurd", - target_os = "linux", - target_os = "netbsd", - target_os = "openbsd", - target_os = "cygwin", - target_os = "solaris", - target_os = "illumos", - target_os = "aix", - target_vendor = "apple", - )))] - pub fn lock_shared(&self) -> io::Result<()> { - Err(io::const_error!(io::ErrorKind::Unsupported, "lock_shared() not supported")) - } - - #[cfg(any( - target_os = "freebsd", - target_os = "fuchsia", - target_os = "hurd", - target_os = "linux", - target_os = "netbsd", - target_os = "openbsd", - target_os = "cygwin", - target_os = "illumos", - target_os = "aix", - target_vendor = "apple", - ))] - pub fn try_lock(&self) -> Result<(), TryLockError> { - let result = cvt(unsafe { libc::flock(self.as_raw_fd(), libc::LOCK_EX | libc::LOCK_NB) }); - if let Err(err) = result { - if err.kind() == io::ErrorKind::WouldBlock { - Err(TryLockError::WouldBlock) - } else { - Err(TryLockError::Error(err)) + cfg_select! { + any( + target_os = "freebsd", + target_os = "fuchsia", + target_os = "hurd", + target_os = "linux", + target_os = "netbsd", + target_os = "openbsd", + target_os = "cygwin", + target_os = "illumos", + target_os = "aix", + target_os = "android", + target_vendor = "apple", + ) => { + cvt(unsafe { libc::flock(self.as_raw_fd(), libc::LOCK_EX) })?; + Ok(()) } - } else { - Ok(()) + _ => Err(io::const_error!(io::ErrorKind::Unsupported, "lock() not supported")), } } - #[cfg(target_os = "solaris")] - pub fn try_lock(&self) -> Result<(), TryLockError> { - let mut flock: libc::flock = unsafe { mem::zeroed() }; - flock.l_type = libc::F_WRLCK as libc::c_short; - flock.l_whence = libc::SEEK_SET as libc::c_short; - let result = cvt(unsafe { libc::fcntl(self.as_raw_fd(), libc::F_SETLK, &flock) }); - if let Err(err) = result { - if err.kind() == io::ErrorKind::WouldBlock { - Err(TryLockError::WouldBlock) - } else { - Err(TryLockError::Error(err)) + pub fn lock_shared(&self) -> io::Result<()> { + cfg_select! { + any( + target_os = "freebsd", + target_os = "fuchsia", + target_os = "hurd", + target_os = "linux", + target_os = "netbsd", + target_os = "openbsd", + target_os = "cygwin", + target_os = "illumos", + target_os = "aix", + target_os = "android", + target_vendor = "apple", + ) => { + cvt(unsafe { libc::flock(self.as_raw_fd(), libc::LOCK_SH) })?; + Ok(()) } - } else { - Ok(()) + _ => Err(io::const_error!(io::ErrorKind::Unsupported, "lock_shared() not supported")), } } - #[cfg(not(any( - target_os = "freebsd", - target_os = "fuchsia", - target_os = "hurd", - target_os = "linux", - target_os = "netbsd", - target_os = "openbsd", - target_os = "cygwin", - target_os = "solaris", - target_os = "illumos", - target_os = "aix", - target_vendor = "apple", - )))] pub fn try_lock(&self) -> Result<(), TryLockError> { - Err(TryLockError::Error(io::const_error!( - io::ErrorKind::Unsupported, - "try_lock() not supported" - ))) - } - - #[cfg(any( - target_os = "freebsd", - target_os = "fuchsia", - target_os = "hurd", - target_os = "linux", - target_os = "netbsd", - target_os = "openbsd", - target_os = "cygwin", - target_os = "illumos", - target_os = "aix", - target_vendor = "apple", - ))] - pub fn try_lock_shared(&self) -> Result<(), TryLockError> { - let result = cvt(unsafe { libc::flock(self.as_raw_fd(), libc::LOCK_SH | libc::LOCK_NB) }); - if let Err(err) = result { - if err.kind() == io::ErrorKind::WouldBlock { - Err(TryLockError::WouldBlock) - } else { - Err(TryLockError::Error(err)) + cfg_select! { + any( + target_os = "freebsd", + target_os = "fuchsia", + target_os = "hurd", + target_os = "linux", + target_os = "netbsd", + target_os = "openbsd", + target_os = "cygwin", + target_os = "illumos", + target_os = "aix", + target_os = "android", + target_vendor = "apple", + ) => { + let result = + cvt(unsafe { libc::flock(self.as_raw_fd(), libc::LOCK_EX | libc::LOCK_NB) }); + if let Err(err) = result { + if err.kind() == io::ErrorKind::WouldBlock { + Err(TryLockError::WouldBlock) + } else { + Err(TryLockError::Error(err)) + } + } else { + Ok(()) + } } - } else { - Ok(()) + _ => Err(TryLockError::Error(io::const_error!( + io::ErrorKind::Unsupported, + "try_lock() not supported" + ))), } } - #[cfg(target_os = "solaris")] pub fn try_lock_shared(&self) -> Result<(), TryLockError> { - let mut flock: libc::flock = unsafe { mem::zeroed() }; - flock.l_type = libc::F_RDLCK as libc::c_short; - flock.l_whence = libc::SEEK_SET as libc::c_short; - let result = cvt(unsafe { libc::fcntl(self.as_raw_fd(), libc::F_SETLK, &flock) }); - if let Err(err) = result { - if err.kind() == io::ErrorKind::WouldBlock { - Err(TryLockError::WouldBlock) - } else { - Err(TryLockError::Error(err)) + cfg_select! { + any( + target_os = "freebsd", + target_os = "fuchsia", + target_os = "hurd", + target_os = "linux", + target_os = "netbsd", + target_os = "openbsd", + target_os = "cygwin", + target_os = "illumos", + target_os = "aix", + target_os = "android", + target_vendor = "apple", + ) => { + let result = + cvt(unsafe { libc::flock(self.as_raw_fd(), libc::LOCK_SH | libc::LOCK_NB) }); + if let Err(err) = result { + if err.kind() == io::ErrorKind::WouldBlock { + Err(TryLockError::WouldBlock) + } else { + Err(TryLockError::Error(err)) + } + } else { + Ok(()) + } } - } else { - Ok(()) + _ => Err(TryLockError::Error(io::const_error!( + io::ErrorKind::Unsupported, + "try_lock_shared() not supported" + ))), } } - #[cfg(not(any( - target_os = "freebsd", - target_os = "fuchsia", - target_os = "hurd", - target_os = "linux", - target_os = "netbsd", - target_os = "openbsd", - target_os = "cygwin", - target_os = "solaris", - target_os = "illumos", - target_os = "aix", - target_vendor = "apple", - )))] - pub fn try_lock_shared(&self) -> Result<(), TryLockError> { - Err(TryLockError::Error(io::const_error!( - io::ErrorKind::Unsupported, - "try_lock_shared() not supported" - ))) - } - - #[cfg(any( - target_os = "freebsd", - target_os = "fuchsia", - target_os = "hurd", - target_os = "linux", - target_os = "netbsd", - target_os = "openbsd", - target_os = "cygwin", - target_os = "illumos", - target_os = "aix", - target_vendor = "apple", - ))] - pub fn unlock(&self) -> io::Result<()> { - cvt(unsafe { libc::flock(self.as_raw_fd(), libc::LOCK_UN) })?; - return Ok(()); - } - - #[cfg(target_os = "solaris")] pub fn unlock(&self) -> io::Result<()> { - let mut flock: libc::flock = unsafe { mem::zeroed() }; - flock.l_type = libc::F_UNLCK as libc::c_short; - flock.l_whence = libc::SEEK_SET as libc::c_short; - cvt(unsafe { libc::fcntl(self.as_raw_fd(), libc::F_SETLKW, &flock) })?; - Ok(()) - } - - #[cfg(not(any( - target_os = "freebsd", - target_os = "fuchsia", - target_os = "hurd", - target_os = "linux", - target_os = "netbsd", - target_os = "openbsd", - target_os = "cygwin", - target_os = "solaris", - target_os = "illumos", - target_os = "aix", - target_vendor = "apple", - )))] - pub fn unlock(&self) -> io::Result<()> { - Err(io::const_error!(io::ErrorKind::Unsupported, "unlock() not supported")) + cfg_select! { + any( + target_os = "freebsd", + target_os = "fuchsia", + target_os = "hurd", + target_os = "linux", + target_os = "netbsd", + target_os = "openbsd", + target_os = "cygwin", + target_os = "illumos", + target_os = "aix", + target_os = "android", + target_vendor = "apple", + ) => { + cvt(unsafe { libc::flock(self.as_raw_fd(), libc::LOCK_UN) })?; + Ok(()) + } + _ => Err(io::const_error!(io::ErrorKind::Unsupported, "unlock() not supported")), + } } pub fn truncate(&self, size: u64) -> io::Result<()> { @@ -1707,11 +1477,11 @@ impl File { self.0.read_at(buf, offset) } - pub fn read_buf(&self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { self.0.read_buf(cursor) } - pub fn read_buf_at(&self, cursor: BorrowedCursor<'_>, offset: u64) -> io::Result<()> { + pub fn read_buf_at(&self, cursor: BorrowedCursor<'_, u8>, offset: u64) -> io::Result<()> { self.0.read_buf_at(cursor, offset) } @@ -1781,7 +1551,13 @@ impl File { pub fn set_times(&self, times: FileTimes) -> io::Result<()> { cfg_select! { - any(target_os = "redox", target_os = "espidf", target_os = "horizon", target_os = "nuttx") => { + any( + target_os = "redox", + target_os = "espidf", + target_os = "horizon", + target_os = "nuttx", + target_os = "l4re" + ) => { // Redox doesn't appear to support `UTIME_OMIT`. // ESP-IDF and HorizonOS do not support `futimens` at all and the behavior for those OS is therefore // the same as for Redox. @@ -1793,17 +1569,22 @@ impl File { } target_vendor = "apple" => { let ta = TimesAttrlist::from_times(×)?; - cvt(unsafe { libc::fsetattrlist( - self.as_raw_fd(), - ta.attrlist(), - ta.times_buf(), - ta.times_buf_size(), - 0 - ) })?; + cvt(unsafe { + libc::fsetattrlist( + self.as_raw_fd(), + ta.attrlist(), + ta.times_buf(), + ta.times_buf_size(), + 0, + ) + })?; Ok(()) } target_os = "android" => { - let times = [file_time_to_timespec(times.accessed)?, file_time_to_timespec(times.modified)?]; + let times = [ + file_time_to_timespec(times.accessed)?, + file_time_to_timespec(times.modified)?, + ]; // futimens requires Android API level 19 cvt(unsafe { weak!( @@ -1811,18 +1592,26 @@ impl File { ); match futimens.get() { Some(futimens) => futimens(self.as_raw_fd(), times.as_ptr()), - None => return Err(io::const_error!( - io::ErrorKind::Unsupported, - "setting file times requires Android API level >= 19", - )), + None => { + return Err(io::const_error!( + io::ErrorKind::Unsupported, + "setting file times requires Android API level >= 19", + )); + } } })?; Ok(()) } _ => { - #[cfg(all(target_os = "linux", target_env = "gnu", target_pointer_width = "32", not(target_arch = "riscv32")))] + #[cfg(all( + target_os = "linux", + target_env = "gnu", + target_pointer_width = "32", + not(target_arch = "riscv32") + ))] { - use crate::sys::pal::{time::__timespec64, weak::weak}; + use crate::sys::pal::time::__timespec64; + use crate::sys::pal::weak::weak; // Added in glibc 2.34 weak!( @@ -1830,14 +1619,19 @@ impl File { ); if let Some(futimens64) = __futimens64.get() { - let to_timespec = |time: Option| time.map(|time| time.t.to_timespec64()) - .unwrap_or(__timespec64::new(0, libc::UTIME_OMIT as _)); + let to_timespec = |time: Option| { + time.map(|time| time.t.to_timespec64()) + .unwrap_or(__timespec64::new(0, libc::UTIME_OMIT as _)) + }; let times = [to_timespec(times.accessed), to_timespec(times.modified)]; cvt(unsafe { futimens64(self.as_raw_fd(), times.as_ptr()) })?; return Ok(()); } } - let times = [file_time_to_timespec(times.accessed)?, file_time_to_timespec(times.modified)?]; + let times = [ + file_time_to_timespec(times.accessed)?, + file_time_to_timespec(times.modified)?, + ]; cvt(unsafe { libc::futimens(self.as_raw_fd(), times.as_ptr()) })?; Ok(()) } @@ -1862,7 +1656,12 @@ fn file_time_to_timespec(time: Option) -> io::Result io::ErrorKind::InvalidInput, "timestamp is too small to set as a file time", )), - None => Ok(libc::timespec { tv_sec: 0, tv_nsec: libc::UTIME_OMIT as _ }), + None => Ok({ + let mut ts = libc::timespec::default(); + ts.tv_sec = 0; + ts.tv_nsec = libc::UTIME_OMIT as _; + ts + }), } } @@ -1998,7 +1797,7 @@ impl fmt::Debug for File { // Format in octal, followed by the mode format used in `ls -l`. // // References: -// https://pubs.opengroup.org/onlinepubs/009696899/utilities/ls.html +// https://pubs.opengroup.org/onlinepubs/9799919799/utilities/ls.html // https://www.gnu.org/software/libc/manual/html_node/Testing-File-Type.html // https://www.gnu.org/software/libc/manual/html_node/Permission-Bits.html // @@ -2085,6 +1884,34 @@ pub fn set_perm(p: &CStr, perm: FilePermissions) -> io::Result<()> { cvt_r(|| unsafe { libc::chmod(p.as_ptr(), perm.mode) }).map(|_| ()) } +pub fn set_perm_nofollow(p: &CStr, perm: FilePermissions) -> io::Result<()> { + // ESP-IDF and Horizon do not support O_NOFOLLOW, so we skip setting it. + // Their filesystems do not have symbolic links, so no special handling is required. + cfg_select! { + // wasm32-wasip1 targets do not support fchmodat, so we fall down to + // open + fchmod + target_os = "wasi" => { + use crate::fs::{OpenOptions, Permissions}; + use crate::os::wasi::ffi::OsStrExt; + use crate::os::wasi::fs::OpenOptionsExt; + + let mut options = OpenOptions::new(); + options.custom_flags(libc::O_NOFOLLOW); + + let bytes = p.to_bytes(); + let os_str = OsStr::from_bytes(bytes); + options.open(Path::new(os_str))?.set_permissions(Permissions::from_inner(perm)) + } + all(target_os = "linux", not(any(target_os = "espidf", target_os = "horizon"))) => { + cvt_r(|| unsafe { + libc::fchmodat(libc::AT_FDCWD, p.as_ptr(), perm.mode, libc::AT_SYMLINK_NOFOLLOW) + }) + .map(|_| ()) + } + _ => cvt_r(|| unsafe { libc::fchmodat(libc::AT_FDCWD, p.as_ptr(), perm.mode, 0) }).map(|_| ()), + } +} + pub fn rmdir(p: &CStr) -> io::Result<()> { cvt(unsafe { libc::rmdir(p.as_ptr()) }).map(|_| ()) } @@ -2129,15 +1956,10 @@ pub fn link(original: &CStr, link: &CStr) -> io::Result<()> { target_os = "vxworks", target_os = "redox", target_os = "espidf", - // Android has `linkat` on newer versions, but we happen to know - // `link` always has the correct behavior, so it's here as well. - target_os = "android", - // wasi-sdk-29-and-prior have a buggy `linkat` so use `link` instead - // until wasi-sdk is updated (see WebAssembly/wasi-libc#690) - target_os = "wasi", // Other misc platforms target_os = "horizon", target_os = "vita", + target_os = "l4re", target_env = "nto70", ) => { cvt(unsafe { libc::link(original.as_ptr(), link.as_ptr()) })?; @@ -2145,7 +1967,9 @@ pub fn link(original: &CStr, link: &CStr) -> io::Result<()> { _ => { // Where we can, use `linkat` instead of `link`; see the comment above // this one for details on why. - cvt(unsafe { libc::linkat(libc::AT_FDCWD, original.as_ptr(), libc::AT_FDCWD, link.as_ptr(), 0) })?; + cvt(unsafe { + libc::linkat(libc::AT_FDCWD, original.as_ptr(), libc::AT_FDCWD, link.as_ptr(), 0) + })?; } } Ok(()) @@ -2211,72 +2035,96 @@ fn open_from(from: &Path) -> io::Result<(crate::fs::File, crate::fs::Metadata)> fn set_times_impl(p: &CStr, times: FileTimes, follow_symlinks: bool) -> io::Result<()> { cfg_select! { - any(target_os = "redox", target_os = "espidf", target_os = "horizon", target_os = "nuttx", target_os = "vita", target_os = "rtems") => { + any( + target_os = "redox", + target_os = "espidf", + target_os = "horizon", + target_os = "nuttx", + target_os = "vita", + target_os = "rtems" + ) => { let _ = (p, times, follow_symlinks); - Err(io::const_error!( - io::ErrorKind::Unsupported, - "setting file times not supported", - )) - } - target_vendor = "apple" => { + Err(io::const_error!(io::ErrorKind::Unsupported, "setting file times not supported")) + } + target_vendor = "apple" => { // Apple platforms use setattrlist which supports setting times on symlinks let ta = TimesAttrlist::from_times(×)?; - let options = if follow_symlinks { - 0 - } else { - libc::FSOPT_NOFOLLOW - }; + let options = if follow_symlinks { 0 } else { libc::FSOPT_NOFOLLOW }; - cvt(unsafe { libc::setattrlist( - p.as_ptr(), - ta.attrlist(), - ta.times_buf(), - ta.times_buf_size(), - options as u32 - ) })?; + cvt(unsafe { + libc::setattrlist( + p.as_ptr(), + ta.attrlist(), + ta.times_buf(), + ta.times_buf_size(), + options as u32, + ) + })?; Ok(()) - } - target_os = "android" => { - let times = [file_time_to_timespec(times.accessed)?, file_time_to_timespec(times.modified)?]; + } + target_os = "android" => { + let times = + [file_time_to_timespec(times.accessed)?, file_time_to_timespec(times.modified)?]; let flags = if follow_symlinks { 0 } else { libc::AT_SYMLINK_NOFOLLOW }; // utimensat requires Android API level 19 cvt(unsafe { weak!( - fn utimensat(dirfd: c_int, path: *const libc::c_char, times: *const libc::timespec, flags: c_int) -> c_int; + fn utimensat( + dirfd: c_int, + path: *const libc::c_char, + times: *const libc::timespec, + flags: c_int, + ) -> c_int; ); match utimensat.get() { Some(utimensat) => utimensat(libc::AT_FDCWD, p.as_ptr(), times.as_ptr(), flags), - None => return Err(io::const_error!( - io::ErrorKind::Unsupported, - "setting file times requires Android API level >= 19", - )), + None => { + return Err(io::const_error!( + io::ErrorKind::Unsupported, + "setting file times requires Android API level >= 19", + )); + } } })?; Ok(()) - } - _ => { + } + _ => { let flags = if follow_symlinks { 0 } else { libc::AT_SYMLINK_NOFOLLOW }; - #[cfg(all(target_os = "linux", target_env = "gnu", target_pointer_width = "32", not(target_arch = "riscv32")))] + #[cfg(all( + target_os = "linux", + target_env = "gnu", + target_pointer_width = "32", + not(target_arch = "riscv32") + ))] { - use crate::sys::pal::{time::__timespec64, weak::weak}; + use crate::sys::pal::time::__timespec64; + use crate::sys::pal::weak::weak; // Added in glibc 2.34 weak!( - fn __utimensat64(dirfd: c_int, path: *const c_char, times: *const __timespec64, flags: c_int) -> c_int; + fn __utimensat64( + dirfd: c_int, + path: *const c_char, + times: *const __timespec64, + flags: c_int, + ) -> c_int; ); if let Some(utimensat64) = __utimensat64.get() { - let to_timespec = |time: Option| time.map(|time| time.t.to_timespec64()) - .unwrap_or(__timespec64::new(0, libc::UTIME_OMIT as _)); + let to_timespec = |time: Option| { + time.map(|time| time.t.to_timespec64()) + .unwrap_or(__timespec64::new(0, libc::UTIME_OMIT as _)) + }; let times = [to_timespec(times.accessed), to_timespec(times.modified)]; cvt(unsafe { utimensat64(libc::AT_FDCWD, p.as_ptr(), times.as_ptr(), flags) })?; return Ok(()); } } - let times = [file_time_to_timespec(times.accessed)?, file_time_to_timespec(times.modified)?]; + let times = + [file_time_to_timespec(times.accessed)?, file_time_to_timespec(times.modified)?]; cvt(unsafe { libc::utimensat(libc::AT_FDCWD, p.as_ptr(), times.as_ptr(), flags) })?; Ok(()) - } + } } } @@ -2343,7 +2191,7 @@ mod cfm { fn read_vectored(&mut self, bufs: &mut [IoSliceMut<'_>]) -> Result { self.0.read_vectored(bufs) } - fn read_buf(&mut self, cursor: BorrowedCursor<'_>) -> Result<()> { + fn read_buf(&mut self, cursor: BorrowedCursor<'_, u8>) -> Result<()> { self.0.read_buf(cursor) } #[inline] @@ -2504,7 +2352,9 @@ pub use remove_dir_impl::remove_dir_all; target_os = "horizon", target_os = "vita", target_os = "nto", + target_os = "qnx", target_os = "vxworks", + target_os = "l4re", miri ))] mod remove_dir_impl { @@ -2518,7 +2368,9 @@ mod remove_dir_impl { target_os = "horizon", target_os = "vita", target_os = "nto", + target_os = "qnx", target_os = "vxworks", + target_os = "l4re", miri )))] mod remove_dir_impl { @@ -2601,7 +2453,7 @@ mod remove_dir_impl { fn remove_dir_all_recursive(parent_fd: Option, path: &CStr) -> io::Result<()> { // try opening as directory - let fd = match openat_nofollow_dironly(parent_fd, &path) { + let fd = match openat_nofollow_dironly(parent_fd, path) { Err(err) if matches!(err.raw_os_error(), Some(libc::ENOTDIR | libc::ELOOP)) => { // not a directory - don't traverse further // (for symlinks, older Linux kernels may return ELOOP instead of ENOTDIR) @@ -2631,24 +2483,23 @@ mod remove_dir_impl { for child in dir { let child = child?; - let child_name = child.name_cstr(); // we need an inner try block, because if one of these // directories has already been deleted, then we need to // continue the loop, not return ok. let result: io::Result<()> = try { match is_dir(&child) { Some(true) => { - remove_dir_all_recursive(Some(fd), child_name)?; + remove_dir_all_recursive(Some(fd), &child.name)?; } Some(false) => { - cvt(unsafe { unlinkat(fd, child_name.as_ptr(), 0) })?; + cvt(unsafe { unlinkat(fd, child.name.as_ptr(), 0) })?; } None => { // POSIX specifies that calling unlink()/unlinkat(..., 0) on a directory can succeed // if the process has the appropriate privileges. This however can causing orphaned // directories requiring an fsck e.g. on Solaris and Illumos. So we try recursing // into it first instead of trying to unlink() it. - remove_dir_all_recursive(Some(fd), child_name)?; + remove_dir_all_recursive(Some(fd), &child.name)?; } } }; @@ -2672,7 +2523,7 @@ mod remove_dir_impl { if attr.file_type().is_symlink() { super::unlink(p) } else { - remove_dir_all_recursive(None, &p) + remove_dir_all_recursive(None, p) } } diff --git a/library/std/src/sys/fs/unix/dir.rs b/library/std/src/sys/fs/unix/dir.rs index 094d1bfd31685..84c5c24668bff 100644 --- a/library/std/src/sys/fs/unix/dir.rs +++ b/library/std/src/sys/fs/unix/dir.rs @@ -1,14 +1,12 @@ -use libc::c_int; +use libc::{c_int, renameat, unlinkat}; cfg_select! { - not( - any( - all(target_os = "linux", not(target_env = "musl")), - target_os = "l4re", - target_os = "android", - target_os = "hurd", - ) - ) => { + not(any( + all(target_os = "linux", not(target_env = "musl")), + target_os = "l4re", + target_os = "android", + target_os = "hurd", + )) => { use libc::{open as open64, openat as openat64}; } _ => { @@ -25,9 +23,9 @@ use crate::os::wasi::io::{AsRawFd, FromRawFd}; use crate::path::Path; use crate::sys::fd::FileDesc; use crate::sys::fs::OpenOptions; -use crate::sys::fs::unix::{File, debug_path_fd}; +use crate::sys::fs::unix::{File, FileAttr, debug_path_fd}; use crate::sys::helpers::run_path_with_cstr; -use crate::sys::{AsInner, FromInner, IntoInner, cvt_r}; +use crate::sys::{AsInner, FromInner, IntoInner, cvt, cvt_r}; use crate::{fmt, fs, io}; pub struct Dir(OwnedFd); @@ -38,7 +36,27 @@ impl Dir { } pub fn open_file(&self, path: &Path, opts: &OpenOptions) -> io::Result { - run_path_with_cstr(path.as_ref(), &|path| self.open_file_c(path, &opts)) + run_path_with_cstr(path.as_ref(), &|path| self.open_file_c(path, opts)) + } + + pub fn metadata(&self) -> io::Result { + // Reuse the implementation for files, which should work for all FDs. + let fd = self.0.as_raw_fd(); + let f = core::mem::ManuallyDrop::new(File( + // SAFETY: we borrowed `self` so the FD will not be closed while this function runs. + unsafe { FileDesc::from_raw_fd(fd) }, + )); + f.file_attr() + } + + pub fn remove_file(&self, path: &Path) -> io::Result<()> { + run_path_with_cstr(path, &|path| self.remove_c(path, false)) + } + + pub fn rename(&self, from: &Path, to_dir: &Self, to: &Path) -> io::Result<()> { + run_path_with_cstr(from, &|from| { + run_path_with_cstr(to, &|to| self.rename_c(from, to_dir, to)) + }) } pub fn open_with_c(path: &CStr, opts: &OpenOptions) -> io::Result { @@ -61,6 +79,24 @@ impl Dir { })?; Ok(File(unsafe { FileDesc::from_raw_fd(fd) })) } + + fn remove_c(&self, path: &CStr, remove_dir: bool) -> io::Result<()> { + cvt(unsafe { + unlinkat( + self.0.as_raw_fd(), + path.as_ptr(), + if remove_dir { libc::AT_REMOVEDIR } else { 0 }, + ) + }) + .map(|_| ()) + } + + fn rename_c(&self, from: &CStr, to_dir: &Self, to: &CStr) -> io::Result<()> { + cvt(unsafe { + renameat(self.0.as_raw_fd(), from.as_ptr(), to_dir.0.as_raw_fd(), to.as_ptr()) + }) + .map(|_| ()) + } } impl fmt::Debug for Dir { diff --git a/library/std/src/sys/fs/unsupported.rs b/library/std/src/sys/fs/unsupported.rs index 069b4fb8a29ce..512af27401dfe 100644 --- a/library/std/src/sys/fs/unsupported.rs +++ b/library/std/src/sys/fs/unsupported.rs @@ -236,7 +236,7 @@ impl File { self.0 } - pub fn read_buf(&self, _cursor: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, _cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { self.0 } @@ -313,6 +313,10 @@ pub fn set_perm(_p: &Path, perm: FilePermissions) -> io::Result<()> { match perm.0 {} } +pub fn set_perm_nofollow(_p: &Path, perm: FilePermissions) -> io::Result<()> { + match perm.0 {} +} + pub fn set_times(_p: &Path, _times: FileTimes) -> io::Result<()> { unsupported() } diff --git a/library/std/src/sys/fs/vexos.rs b/library/std/src/sys/fs/vexos.rs index 81083a4fa81d3..1357787c44c77 100644 --- a/library/std/src/sys/fs/vexos.rs +++ b/library/std/src/sys/fs/vexos.rs @@ -12,8 +12,8 @@ use crate::sys::{unsupported, unsupported_err}; #[path = "unsupported.rs"] mod unsupported_fs; pub use unsupported_fs::{ - DirBuilder, FileTimes, canonicalize, link, readlink, remove_dir_all, rename, rmdir, symlink, - unlink, + Dir, DirBuilder, FileTimes, canonicalize, link, readlink, remove_dir_all, rename, rmdir, + symlink, unlink, }; /// VEXos file descriptor. @@ -339,7 +339,7 @@ impl File { false } - pub fn read_buf(&self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { crate::io::default_read_buf(|b| self.read(b), cursor) } @@ -492,6 +492,10 @@ pub fn set_perm(_p: &Path, _perm: FilePermissions) -> io::Result<()> { unsupported() } +pub fn set_perm_nofollow(_p: &Path, _perm: FilePermissions) -> io::Result<()> { + unsupported() +} + pub fn set_times(_p: &Path, _times: FileTimes) -> io::Result<()> { unsupported() } @@ -545,7 +549,7 @@ fn map_fresult(fresult: vex_sdk::FRESULT) -> io::Result<()> { match fresult { vex_sdk::FRESULT::FR_OK => Ok(()), vex_sdk::FRESULT::FR_DISK_ERR => Err(io::const_error!( - io::ErrorKind::Uncategorized, + io::ErrorKind::InputOutputError, "internal function reported an unrecoverable hard error", )), vex_sdk::FRESULT::FR_INT_ERR => Err(io::const_error!( @@ -612,7 +616,7 @@ fn map_fresult(fresult: vex_sdk::FRESULT) -> io::Result<()> { Err(io::const_error!(io::ErrorKind::OutOfMemory, "not enough memory for the operation")) } vex_sdk::FRESULT::FR_TOO_MANY_OPEN_FILES => Err(io::const_error!( - io::ErrorKind::Uncategorized, + io::ErrorKind::TooManyOpenFiles, "maximum number of open files has been reached", )), vex_sdk::FRESULT::FR_INVALID_PARAMETER => { diff --git a/library/std/src/sys/fs/windows.rs b/library/std/src/sys/fs/windows.rs index 74854cdeb498d..c10b266ccb726 100644 --- a/library/std/src/sys/fs/windows.rs +++ b/library/std/src/sys/fs/windows.rs @@ -301,7 +301,7 @@ impl OpenOptions { if self.truncate && !self.create_new { return Err(io::Error::new( io::ErrorKind::InvalidInput, - "creating or truncating a file requires write or append access", + "append and truncate cannot both be enabled", )); } } @@ -339,7 +339,7 @@ impl File { let path = maybe_verbatim(path)?; // SAFETY: maybe_verbatim returns null-terminated strings let path = unsafe { WCStr::from_wchars_with_null_unchecked(&path) }; - Self::open_native(&path, opts) + Self::open_native(path, opts) } fn open_native(path: &WCStr, opts: &OpenOptions) -> io::Result { @@ -597,7 +597,7 @@ impl File { (&raw mut info) as *mut c_void, size as u32, ))?; - attr.file_size = info.AllocationSize as u64; + attr.file_size = info.EndOfFile as u64; attr.number_of_links = Some(info.NumberOfLinks); if attr.attributes & c::FILE_ATTRIBUTE_REPARSE_POINT != 0 { let mut attr_tag: c::FILE_ATTRIBUTE_TAG_INFO = mem::zeroed(); @@ -632,11 +632,11 @@ impl File { self.handle.read_at(buf, offset) } - pub fn read_buf(&self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { self.handle.read_buf(cursor) } - pub fn read_buf_at(&self, cursor: BorrowedCursor<'_>, offset: u64) -> io::Result<()> { + pub fn read_buf_at(&self, cursor: BorrowedCursor<'_, u8>, offset: u64) -> io::Result<()> { self.handle.read_buf_at(cursor, offset) } @@ -1167,6 +1167,16 @@ impl FilePermissions { self.attrs &= !c::FILE_ATTRIBUTE_READONLY; } } + + pub fn file_attributes(&self) -> u32 { + self.attrs as u32 + } +} + +impl FromInner for FilePermissions { + fn from_inner(attrs: u32) -> FilePermissions { + FilePermissions { attrs } + } } impl FileTimes { @@ -1295,7 +1305,7 @@ pub fn unlink(path: &WCStr) -> io::Result<()> { let mut opts = OpenOptions::new(); opts.access_mode(c::DELETE); opts.custom_flags(c::FILE_FLAG_OPEN_REPARSE_POINT); - if let Ok(f) = File::open_native(&path, &opts) { + if let Ok(f) = File::open_native(path, &opts) { if f.posix_delete().is_ok() { return Ok(()); } @@ -1318,7 +1328,7 @@ pub fn rename(old: &WCStr, new: &WCStr) -> io::Result<()> { let mut opts = OpenOptions::new(); opts.access_mode(c::DELETE); opts.custom_flags(c::FILE_FLAG_OPEN_REPARSE_POINT | c::FILE_FLAG_BACKUP_SEMANTICS); - let Ok(f) = File::open_native(&old, &opts) else { return Err(err).io_result() }; + let Ok(f) = File::open_native(old, &opts) else { return Err(err).io_result() }; // Calculate the layout of the `FILE_RENAME_INFO` we pass to `SetFileInformation` // This is a dynamically sized struct so we need to get the position of the last field to calculate the actual size. @@ -1409,7 +1419,7 @@ pub fn readlink(path: &WCStr) -> io::Result { let mut opts = OpenOptions::new(); opts.access_mode(0); opts.custom_flags(c::FILE_FLAG_OPEN_REPARSE_POINT | c::FILE_FLAG_BACKUP_SEMANTICS); - let file = File::open_native(&path, &opts)?; + let file = File::open_native(path, &opts)?; file.readlink() } @@ -1496,7 +1506,7 @@ fn metadata(path: &WCStr, reparse: ReparsePoint) -> io::Result { // Attempt to open the file normally. // If that fails with `ERROR_SHARING_VIOLATION` then retry using `FindFirstFileExW`. // If the fallback fails for any reason we return the original error. - match File::open_native(&path, &opts) { + match File::open_native(path, &opts) { Ok(file) => file.file_attr(), Err(e) if [Some(c::ERROR_SHARING_VIOLATION as _), Some(c::ERROR_ACCESS_DENIED as _)] @@ -1554,6 +1564,15 @@ pub fn set_perm(p: &WCStr, perm: FilePermissions) -> io::Result<()> { } } +pub fn set_perm_nofollow(p: &WCStr, perm: FilePermissions) -> io::Result<()> { + let mut opts = OpenOptions::new(); + opts.access_mode(c::FILE_WRITE_ATTRIBUTES); + // `FILE_FLAG_OPEN_REPARSE_POINT` for no_follow behavior + opts.custom_flags(c::FILE_FLAG_BACKUP_SEMANTICS | c::FILE_FLAG_OPEN_REPARSE_POINT); + let file = File::open_native(p, &opts)?; + file.set_permissions(perm) +} + pub fn set_times(p: &WCStr, times: FileTimes) -> io::Result<()> { let mut opts = OpenOptions::new(); opts.access_mode(c::FILE_WRITE_ATTRIBUTES); @@ -1643,7 +1662,7 @@ pub fn junction_point(original: &Path, link: &Path) -> io::Result<()> { } else { // Get an absolute path and then convert the prefix to `\??\` let abs_path = crate::path::absolute(original)?.into_os_string().into_encoded_bytes(); - if abs_path.len() > 0 && abs_path[1..].starts_with(br":\") { + if !abs_path.is_empty() && abs_path[1..].starts_with(br":\") { let bytes = unsafe { OsStr::from_encoded_bytes_unchecked(&abs_path) }; r"\??\".encode_utf16().chain(bytes.encode_wide()).collect() } else if abs_path.starts_with(br"\\.\") { @@ -1666,33 +1685,46 @@ pub fn junction_point(original: &Path, link: &Path) -> io::Result<()> { SubstituteNameLength: u16, PrintNameOffset: u16, PrintNameLength: u16, - PathBuffer: [MaybeUninit; c::MAXIMUM_REPARSE_DATA_BUFFER_SIZE as usize], + // `MAXIMUM_REPARSE_DATA_BUFFER_SIZE` is a size in bytes, but this is a + // buffer of `u16`s, so it holds half as many elements. + PathBuffer: [MaybeUninit; c::MAXIMUM_REPARSE_DATA_BUFFER_SIZE as usize / 2], } - let data_len = 12 + (abs_path.len() * 2); - if data_len > u16::MAX as usize { - return Err(io::const_error!(io::ErrorKind::InvalidInput, "`original` path is too long")); - } - let data_len = data_len as u16; let mut header = MountPointBuffer { ReparseTag: c::IO_REPARSE_TAG_MOUNT_POINT, - ReparseDataLength: data_len, + ReparseDataLength: 0, // filled in below Reserved: 0, SubstituteNameOffset: 0, SubstituteNameLength: (abs_path.len() * 2) as u16, + // The print name follows the substitute name and its null terminator. PrintNameOffset: ((abs_path.len() + 1) * 2) as u16, PrintNameLength: 0, - PathBuffer: [MaybeUninit::uninit(); c::MAXIMUM_REPARSE_DATA_BUFFER_SIZE as usize], + PathBuffer: [MaybeUninit::uninit(); c::MAXIMUM_REPARSE_DATA_BUFFER_SIZE as usize / 2], }; + // A mount point reparse point requires both the substitute name and the + // (empty) print name to be null terminated, even though their lengths are + // explicit. Bounds-check and copy in a single step so an over-long path + // fails cleanly instead of overflowing the buffer. + let Some(path_buffer) = header.PathBuffer.get_mut(..abs_path.len() + 2) else { + return Err(io::const_error!(io::ErrorKind::InvalidInput, "`original` path is too long")); + }; + let (substitute_name, terminators) = path_buffer.split_at_mut(abs_path.len()); + substitute_name.write_copy_of_slice(&abs_path); + terminators.write_copy_of_slice(&[0, 0]); + // Total size of the structure: the fixed header fields, the path, and the + // two null terminators. + let total_len = offset_of!(MountPointBuffer, PathBuffer) + (abs_path.len() + 2) * 2; + // `ReparseDataLength` counts only the bytes after the 8-byte common header + // (`ReparseTag`, `ReparseDataLength`, `Reserved`), i.e. + // `SubstituteNameLength + PrintNameLength + 12`. + header.ReparseDataLength = + (total_len - offset_of!(MountPointBuffer, SubstituteNameOffset)) as u16; unsafe { - let ptr = header.PathBuffer.as_mut_ptr(); - ptr.copy_from(abs_path.as_ptr().cast_uninit(), abs_path.len()); - let mut ret = 0; cvt(c::DeviceIoControl( d.as_raw_handle(), c::FSCTL_SET_REPARSE_POINT, (&raw const header).cast::(), - data_len as u32 + 8, + total_len as u32, ptr::null_mut(), 0, &mut ret, diff --git a/library/std/src/sys/fs/windows/dir.rs b/library/std/src/sys/fs/windows/dir.rs index 3f617806c6c36..5e69515b66599 100644 --- a/library/std/src/sys/fs/windows/dir.rs +++ b/library/std/src/sys/fs/windows/dir.rs @@ -1,3 +1,6 @@ +use crate::alloc::{Layout, alloc, dealloc}; +use crate::ffi::c_void; +use crate::mem::offset_of; use crate::os::windows::io::{ AsHandle, AsRawHandle, BorrowedHandle, FromRawHandle, HandleOrInvalid, IntoRawHandle, OwnedHandle, RawHandle, @@ -5,7 +8,7 @@ use crate::os::windows::io::{ use crate::path::Path; use crate::sys::api::{UnicodeStrRef, WinError}; use crate::sys::fs::windows::debug_path_handle; -use crate::sys::fs::{File, OpenOptions}; +use crate::sys::fs::{File, FileAttr, OpenOptions}; use crate::sys::handle::Handle; use crate::sys::path::{WCStr, with_native_path}; use crate::sys::{AsInner, FromInner, IntoInner, IoResult, c, to_u16s}; @@ -15,6 +18,12 @@ pub struct Dir { handle: Handle, } +fn to_u16s_without_nul(path: &Path) -> io::Result> { + let mut path = to_u16s(path)?; + path.pop(); + Ok(path) +} + /// A wrapper around a raw NtCreateFile call. /// /// This isn't completely safe because `OBJECT_ATTRIBUTES` contains raw pointers. @@ -62,9 +71,20 @@ impl Dir { if path.is_absolute() { return File::open(path, opts); } - let path = to_u16s(path)?; - let path = &path[..path.len() - 1]; // trim 0 byte - self.open_file_native(&path, opts).map(|handle| File { handle }) + let path = to_u16s_without_nul(path)?; + self.open_file_native(&path, opts, false).map(|handle| File { handle }) + } + + pub fn remove_file(&self, path: &Path) -> io::Result<()> { + let path = to_u16s_without_nul(path)?; + self.remove_native(&path, false) + } + + pub fn rename(&self, from: &Path, to_dir: &Self, to: &Path) -> io::Result<()> { + let is_dir = from.is_dir(); + let from = to_u16s_without_nul(from)?; + let to = to_u16s_without_nul(to)?; + self.rename_native(&from, to_dir, &to, is_dir) } fn open_with_native(path: &WCStr, opts: &OpenOptions) -> io::Result { @@ -92,14 +112,92 @@ impl Dir { } } - fn open_file_native(&self, path: &[u16], opts: &OpenOptions) -> io::Result { + fn open_file_native(&self, path: &[u16], opts: &OpenOptions, dir: bool) -> io::Result { let name = UnicodeStrRef::from_slice(path); let object_attributes = c::OBJECT_ATTRIBUTES { RootDirectory: self.handle.as_raw_handle(), ObjectName: name.as_ptr(), ..c::OBJECT_ATTRIBUTES::with_length() }; - unsafe { nt_create_file(opts, &object_attributes, c::FILE_NON_DIRECTORY_FILE) } + let create_opt = if dir { c::FILE_DIRECTORY_FILE } else { c::FILE_NON_DIRECTORY_FILE }; + unsafe { nt_create_file(opts, &object_attributes, create_opt) } + } + + fn remove_native(&self, path: &[u16], dir: bool) -> io::Result<()> { + let mut opts = OpenOptions::new(); + opts.access_mode(c::DELETE); + let handle = self.open_file_native(path, &opts, dir)?; + File::from_inner(handle).delete().io_result() + } + + fn rename_native(&self, from: &[u16], to_dir: &Self, to: &[u16], dir: bool) -> io::Result<()> { + let mut opts = OpenOptions::new(); + opts.access_mode(c::DELETE); + opts.custom_flags(c::FILE_FLAG_OPEN_REPARSE_POINT | c::FILE_FLAG_BACKUP_SEMANTICS); + let handle = self.open_file_native(from, &opts, dir)?; + // Calculate the layout of the `FILE_RENAME_INFORMATION` we pass to `NtSetInformationFile` + // This is a dynamically sized struct so we need to get the position of the last field to calculate the actual size. + const too_long_err: io::Error = + io::const_error!(io::ErrorKind::InvalidFilename, "Filename too long"); + let struct_size = to + .len() + .checked_mul(2) + .and_then(|x| x.checked_add(offset_of!(c::FILE_RENAME_INFORMATION, FileName))) + .ok_or(too_long_err)?; + let layout = Layout::from_size_align(struct_size, align_of::()) + .map_err(|_| too_long_err)?; + let struct_size = u32::try_from(struct_size).map_err(|_| too_long_err)?; + let to_byte_len = u32::try_from(to.len() * 2).map_err(|_| too_long_err)?; + + let file_rename_info; + // SAFETY: We allocate enough memory for a full FILE_RENAME_INFORMATION struct and the filename. + unsafe { + file_rename_info = alloc(layout).cast::(); + if file_rename_info.is_null() { + return Err(io::ErrorKind::OutOfMemory.into()); + } + + (&raw mut (*file_rename_info).Anonymous).write(c::FILE_RENAME_INFORMATION_0 { + Flags: c::FILE_RENAME_FLAG_REPLACE_IF_EXISTS | c::FILE_RENAME_FLAG_POSIX_SEMANTICS, + }); + + (&raw mut (*file_rename_info).RootDirectory).write(to_dir.handle.as_raw_handle()); + // Don't include the NULL in the size + (&raw mut (*file_rename_info).FileNameLength).write(to_byte_len); + + to.as_ptr().copy_to_nonoverlapping( + (&raw mut (*file_rename_info).FileName).cast::(), + to.len(), + ); + } + + let status = unsafe { + c::NtSetInformationFile( + handle.as_raw_handle(), + &mut c::IO_STATUS_BLOCK::default(), + file_rename_info.cast::(), + struct_size, + c::FileRenameInformation, + ) + }; + unsafe { dealloc(file_rename_info.cast::(), layout) }; + if c::nt_success(status) { + // SAFETY: nt_success guarantees that handle is no longer null + Ok(()) + } else { + Err(WinError::new(unsafe { c::RtlNtStatusToDosError(status) })) + } + .io_result() + } + + pub fn metadata(&self) -> io::Result { + // Reuse the implementation for files, which should work for all handles. + let handle = self.handle.as_raw_handle(); + let f = core::mem::ManuallyDrop::new(File { + // SAFETY: we borrowed `self` so the handle will not be closed while this function runs. + handle: unsafe { Handle::from_raw_handle(handle) }, + }); + f.file_attr() } } @@ -117,35 +215,35 @@ impl AsRawHandle for fs::Dir { } } -#[unstable(feature = "dirhandle", issue = "120426")] +#[unstable(feature = "dirfd", issue = "120426")] impl IntoRawHandle for fs::Dir { fn into_raw_handle(self) -> RawHandle { self.into_inner().handle.into_raw_handle() } } -#[unstable(feature = "dirhandle", issue = "120426")] +#[unstable(feature = "dirfd", issue = "120426")] impl FromRawHandle for fs::Dir { unsafe fn from_raw_handle(handle: RawHandle) -> Self { Self::from_inner(Dir { handle: unsafe { FromRawHandle::from_raw_handle(handle) } }) } } -#[unstable(feature = "dirhandle", issue = "120426")] +#[unstable(feature = "dirfd", issue = "120426")] impl AsHandle for fs::Dir { fn as_handle(&self) -> BorrowedHandle<'_> { self.as_inner().handle.as_handle() } } -#[unstable(feature = "dirhandle", issue = "120426")] +#[unstable(feature = "dirfd", issue = "120426")] impl From for OwnedHandle { fn from(value: fs::Dir) -> Self { value.into_inner().handle.into_inner() } } -#[unstable(feature = "dirhandle", issue = "120426")] +#[unstable(feature = "dirfd", issue = "120426")] impl From for fs::Dir { fn from(value: OwnedHandle) -> Self { Self::from_inner(Dir { handle: Handle::from_inner(value) }) diff --git a/library/std/src/sys/io/error/mod.rs b/library/std/src/sys/io/error/mod.rs index d7a0b9b4b301d..a56030f17709f 100644 --- a/library/std/src/sys/io/error/mod.rs +++ b/library/std/src/sys/io/error/mod.rs @@ -15,22 +15,14 @@ cfg_select! { mod solid; pub use solid::*; } - target_os = "teeos" => { - mod teeos; - pub use teeos::*; - } target_os = "uefi" => { mod uefi; pub use uefi::*; } - target_family = "unix" => { + any(target_family = "unix", target_os = "wasi", target_os = "teeos") => { mod unix; pub use unix::*; } - target_os = "wasi" => { - mod wasi; - pub use wasi::*; - } target_os = "windows" => { mod windows; pub use windows::*; @@ -39,17 +31,8 @@ cfg_select! { mod xous; pub use xous::*; } - any( - target_os = "vexos", - target_family = "wasm", - target_os = "zkvm", - ) => { + any(target_os = "vexos", target_family = "wasm", target_os = "zkvm", target_os = "trusty") => { mod generic; pub use generic::*; } } - -pub type RawOsError = cfg_select! { - target_os = "uefi" => usize, - _ => i32, -}; diff --git a/library/std/src/sys/io/error/motor.rs b/library/std/src/sys/io/error/motor.rs index 7d612d817cdd7..3c22d5fcb7b06 100644 --- a/library/std/src/sys/io/error/motor.rs +++ b/library/std/src/sys/io/error/motor.rs @@ -1,7 +1,6 @@ use crate::io; -use crate::sys::io::RawOsError; -pub fn errno() -> RawOsError { +pub fn errno() -> io::RawOsError { // Not used in Motor OS because it is ambiguous: Motor OS // is micro-kernel-based, and I/O happens via a shared-memory // ring buffer, so an I/O operation that on a unix is a syscall @@ -57,7 +56,7 @@ pub fn decode_error_kind(code: io::RawOsError) -> io::ErrorKind { } } -pub fn error_string(errno: RawOsError) -> String { +pub fn error_string(errno: io::RawOsError) -> String { let error: moto_rt::Error = match errno { x if x < 0 => moto_rt::Error::Unknown, x if x > u16::MAX.into() => moto_rt::Error::Unknown, diff --git a/library/std/src/sys/io/error/sgx.rs b/library/std/src/sys/io/error/sgx.rs index 8b3e08b0b661b..b7b4030422e12 100644 --- a/library/std/src/sys/io/error/sgx.rs +++ b/library/std/src/sys/io/error/sgx.rs @@ -60,6 +60,6 @@ pub fn error_string(errno: i32) -> String { } else if ((Error::UserRangeStart as _)..=(Error::UserRangeEnd as _)).contains(&errno) { format!("user-specified error {errno:08x}") } else { - decode_error_kind(errno).as_str().into() + format!("{}", decode_error_kind(errno)) } } diff --git a/library/std/src/sys/io/error/teeos.rs b/library/std/src/sys/io/error/teeos.rs deleted file mode 100644 index 18826ffc3894f..0000000000000 --- a/library/std/src/sys/io/error/teeos.rs +++ /dev/null @@ -1,64 +0,0 @@ -use crate::io; - -pub fn errno() -> i32 { - unsafe { (*libc::__errno_location()) as i32 } -} - -#[inline] -pub fn is_interrupted(errno: i32) -> bool { - errno == libc::EINTR -} - -// Note: code below is 1:1 copied from unix/mod.rs -pub fn decode_error_kind(errno: i32) -> io::ErrorKind { - use io::ErrorKind::*; - match errno as libc::c_int { - libc::E2BIG => ArgumentListTooLong, - libc::EADDRINUSE => AddrInUse, - libc::EADDRNOTAVAIL => AddrNotAvailable, - libc::EBUSY => ResourceBusy, - libc::ECONNABORTED => ConnectionAborted, - libc::ECONNREFUSED => ConnectionRefused, - libc::ECONNRESET => ConnectionReset, - libc::EDEADLK => Deadlock, - libc::EDQUOT => QuotaExceeded, - libc::EEXIST => AlreadyExists, - libc::EFBIG => FileTooLarge, - libc::EHOSTUNREACH => HostUnreachable, - libc::EINTR => Interrupted, - libc::EINVAL => InvalidInput, - libc::EISDIR => IsADirectory, - libc::ELOOP => FilesystemLoop, - libc::ENOENT => NotFound, - libc::ENOMEM => OutOfMemory, - libc::ENOSPC => StorageFull, - libc::ENOSYS => Unsupported, - libc::EMLINK => TooManyLinks, - libc::ENAMETOOLONG => InvalidFilename, - libc::ENETDOWN => NetworkDown, - libc::ENETUNREACH => NetworkUnreachable, - libc::ENOTCONN => NotConnected, - libc::ENOTDIR => NotADirectory, - libc::ENOTEMPTY => DirectoryNotEmpty, - libc::EPIPE => BrokenPipe, - libc::EROFS => ReadOnlyFilesystem, - libc::ESPIPE => NotSeekable, - libc::ESTALE => StaleNetworkFileHandle, - libc::ETIMEDOUT => TimedOut, - libc::ETXTBSY => ExecutableFileBusy, - libc::EXDEV => CrossesDevices, - - libc::EACCES | libc::EPERM => PermissionDenied, - - // These two constants can have the same value on some systems, - // but different values on others, so we can't use a match - // clause - x if x == libc::EAGAIN || x == libc::EWOULDBLOCK => WouldBlock, - - _ => Uncategorized, - } -} - -pub fn error_string(_errno: i32) -> String { - "error string unimplemented".to_string() -} diff --git a/library/std/src/sys/io/error/unix.rs b/library/std/src/sys/io/error/unix.rs index b10343b2752c2..12acde7311e4c 100644 --- a/library/std/src/sys/io/error/unix.rs +++ b/library/std/src/sys/io/error/unix.rs @@ -1,8 +1,15 @@ -use crate::ffi::{CStr, c_char, c_int}; +use crate::ffi::c_int; +#[cfg(not(target_os = "teeos"))] +use crate::ffi::{CStr, c_char}; use crate::io; unsafe extern "C" { - #[cfg(not(any(target_os = "dragonfly", target_os = "vxworks", target_os = "rtems")))] + #[cfg(not(any( + target_os = "dragonfly", + target_os = "vxworks", + target_os = "rtems", + target_os = "wasi" + )))] #[cfg_attr( any( target_os = "linux", @@ -10,6 +17,7 @@ unsafe extern "C" { target_os = "fuchsia", target_os = "l4re", target_os = "hurd", + target_os = "teeos", ), link_name = "__errno_location" )] @@ -27,6 +35,7 @@ unsafe extern "C" { )] #[cfg_attr(any(target_os = "solaris", target_os = "illumos"), link_name = "___errno")] #[cfg_attr(target_os = "nto", link_name = "__get_errno_ptr")] + #[cfg_attr(target_os = "qnx", link_name = "__get_errno_ptr")] #[cfg_attr(any(target_os = "freebsd", target_vendor = "apple"), link_name = "__error")] #[cfg_attr(target_os = "haiku", link_name = "_errnop")] #[cfg_attr(target_os = "aix", link_name = "_Errno")] @@ -36,7 +45,12 @@ unsafe extern "C" { } /// Returns the platform-specific value of errno -#[cfg(not(any(target_os = "dragonfly", target_os = "vxworks", target_os = "rtems")))] +#[cfg(not(any( + target_os = "dragonfly", + target_os = "vxworks", + target_os = "rtems", + target_os = "wasi" +)))] #[inline] pub fn errno() -> i32 { unsafe { (*errno_location()) as i32 } @@ -44,8 +58,15 @@ pub fn errno() -> i32 { /// Sets the platform-specific value of errno // needed for readdir and syscall! -#[cfg(all(not(target_os = "dragonfly"), not(target_os = "vxworks"), not(target_os = "rtems")))] -#[allow(dead_code)] // but not all target cfgs actually end up using it +#[cfg(not(any( + target_os = "dragonfly", + target_os = "espidf", + target_os = "lynxos178", + target_os = "qurt", + target_os = "rtems", + target_os = "vxworks", + target_os = "wasi", +)))] #[inline] pub fn set_errno(e: i32) { unsafe { *errno_location() = e as c_int } @@ -73,14 +94,13 @@ pub fn errno() -> i32 { pub fn errno() -> i32 { unsafe extern "C" { #[thread_local] - static errno: c_int; + static mut errno: c_int; } unsafe { errno as i32 } } #[cfg(target_os = "dragonfly")] -#[allow(dead_code)] #[inline] pub fn set_errno(e: i32) { unsafe extern "C" { @@ -88,8 +108,25 @@ pub fn set_errno(e: i32) { static mut errno: c_int; } + unsafe { errno = e }; +} + +#[cfg(target_os = "wasi")] +unsafe extern "C" { + #[thread_local] + #[link_name = "errno"] + static mut libc_errno: libc::c_int; +} + +#[cfg(target_os = "wasi")] +pub fn errno() -> i32 { + unsafe { libc_errno as i32 } +} + +#[cfg(target_os = "wasi")] +pub fn set_errno(val: i32) { unsafe { - errno = e; + libc_errno = val; } } @@ -120,7 +157,6 @@ pub fn decode_error_kind(errno: i32) -> io::ErrorKind { libc::ENOENT => NotFound, libc::ENOMEM => OutOfMemory, libc::ENOSPC => StorageFull, - libc::ENOSYS => Unsupported, libc::EMLINK => TooManyLinks, libc::ENAMETOOLONG => InvalidFilename, libc::ENETDOWN => NetworkDown, @@ -137,10 +173,17 @@ pub fn decode_error_kind(errno: i32) -> io::ErrorKind { libc::ETXTBSY => ExecutableFileBusy, libc::EXDEV => CrossesDevices, libc::EINPROGRESS => InProgress, - libc::EOPNOTSUPP => Unsupported, + libc::EMFILE | libc::ENFILE => TooManyOpenFiles, + libc::EIO => InputOutputError, libc::EACCES | libc::EPERM => PermissionDenied, + libc::ENOSYS => Unsupported, + // EOPNOTSUPP and ENOTSUP can have the same value on some systems, + // but different values on others (e.g. Apple), so we can't use a + // match clause + x if x == libc::EOPNOTSUPP || x == libc::ENOTSUP => Unsupported, + // These two constants can have the same value on some systems, // but different values on others, so we can't use a match // clause @@ -151,8 +194,9 @@ pub fn decode_error_kind(errno: i32) -> io::ErrorKind { } /// Gets a detailed string description for the given error number. +#[cfg(any(target_family = "unix", target_os = "wasi"))] pub fn error_string(errno: i32) -> String { - const TMPBUF_SZ: usize = 128; + const TMPBUF_SZ: usize = if cfg!(target_os = "wasi") { 1024 } else { 128 }; unsafe extern "C" { #[cfg_attr( @@ -161,7 +205,8 @@ pub fn error_string(errno: i32) -> String { target_os = "linux", target_os = "hurd", target_env = "newlib", - target_os = "cygwin" + target_os = "cygwin", + target_env = "uclibc", ), not(target_env = "ohos") ), @@ -184,3 +229,8 @@ pub fn error_string(errno: i32) -> String { String::from_utf8_lossy(CStr::from_ptr(p).to_bytes()).into() } } + +#[cfg(target_os = "teeos")] +pub fn error_string(_errno: i32) -> String { + "error string unimplemented".to_string() +} diff --git a/library/std/src/sys/io/error/wasi.rs b/library/std/src/sys/io/error/wasi.rs deleted file mode 100644 index 719fc0c900adc..0000000000000 --- a/library/std/src/sys/io/error/wasi.rs +++ /dev/null @@ -1,80 +0,0 @@ -use crate::ffi::CStr; -use crate::io as std_io; - -unsafe extern "C" { - #[thread_local] - #[link_name = "errno"] - static mut libc_errno: libc::c_int; -} - -pub fn errno() -> i32 { - unsafe { libc_errno as i32 } -} - -pub fn set_errno(val: i32) { - unsafe { - libc_errno = val; - } -} - -#[inline] -pub fn is_interrupted(errno: i32) -> bool { - errno == libc::EINTR -} - -pub fn decode_error_kind(errno: i32) -> std_io::ErrorKind { - use std_io::ErrorKind::*; - match errno as libc::c_int { - libc::E2BIG => ArgumentListTooLong, - libc::EADDRINUSE => AddrInUse, - libc::EADDRNOTAVAIL => AddrNotAvailable, - libc::EBUSY => ResourceBusy, - libc::ECONNABORTED => ConnectionAborted, - libc::ECONNREFUSED => ConnectionRefused, - libc::ECONNRESET => ConnectionReset, - libc::EDEADLK => Deadlock, - libc::EDQUOT => QuotaExceeded, - libc::EEXIST => AlreadyExists, - libc::EFBIG => FileTooLarge, - libc::EHOSTUNREACH => HostUnreachable, - libc::EINTR => Interrupted, - libc::EINVAL => InvalidInput, - libc::EISDIR => IsADirectory, - libc::ELOOP => FilesystemLoop, - libc::ENOENT => NotFound, - libc::ENOMEM => OutOfMemory, - libc::ENOSPC => StorageFull, - libc::ENOSYS => Unsupported, - libc::EMLINK => TooManyLinks, - libc::ENAMETOOLONG => InvalidFilename, - libc::ENETDOWN => NetworkDown, - libc::ENETUNREACH => NetworkUnreachable, - libc::ENOTCONN => NotConnected, - libc::ENOTDIR => NotADirectory, - libc::EPIPE => BrokenPipe, - libc::EROFS => ReadOnlyFilesystem, - libc::ESPIPE => NotSeekable, - libc::ESTALE => StaleNetworkFileHandle, - libc::ETIMEDOUT => TimedOut, - libc::ETXTBSY => ExecutableFileBusy, - libc::EXDEV => CrossesDevices, - libc::EINPROGRESS => InProgress, - libc::EOPNOTSUPP => Unsupported, - libc::EACCES | libc::EPERM => PermissionDenied, - libc::EWOULDBLOCK => WouldBlock, - - _ => Uncategorized, - } -} - -pub fn error_string(errno: i32) -> String { - let mut buf = [0 as libc::c_char; 1024]; - - let p = buf.as_mut_ptr(); - unsafe { - if libc::strerror_r(errno as libc::c_int, p, buf.len()) < 0 { - panic!("strerror_r failure"); - } - str::from_utf8(CStr::from_ptr(p).to_bytes()).unwrap().to_owned() - } -} diff --git a/library/std/src/sys/io/error/windows.rs b/library/std/src/sys/io/error/windows.rs index d7607082a30a0..0ca3aee389b3e 100644 --- a/library/std/src/sys/io/error/windows.rs +++ b/library/std/src/sys/io/error/windows.rs @@ -1,6 +1,9 @@ use crate::sys::pal::{api, c}; use crate::{io, ptr}; +#[cfg(test)] +mod tests; + pub fn errno() -> i32 { api::get_last_error().code as i32 } @@ -58,8 +61,11 @@ pub fn decode_error_kind(errno: i32) -> io::ErrorKind { c::ERROR_POSSIBLE_DEADLOCK => return Deadlock, c::ERROR_NOT_SAME_DEVICE => return CrossesDevices, c::ERROR_TOO_MANY_LINKS => return TooManyLinks, + c::ERROR_TOO_MANY_OPEN_FILES => return TooManyOpenFiles, c::ERROR_FILENAME_EXCED_RANGE => return InvalidFilename, c::ERROR_CANT_RESOLVE_FILENAME => return FilesystemLoop, + c::ERROR_IO_DEVICE => return InputOutputError, + c::ERROR_NEGATIVE_SEEK => return InvalidInput, _ => {} } @@ -78,6 +84,11 @@ pub fn decode_error_kind(errno: i32) -> io::ErrorKind { c::WSAENETDOWN => NetworkDown, c::WSAENETUNREACH => NetworkUnreachable, c::WSAEDQUOT => QuotaExceeded, + c::WSAEMFILE => TooManyOpenFiles, + // Not a perfect mapping but this error is only returned when writing to + // a socket after shutting down the write-end. On Unix targets, EPIPE is + // returned in those cases. + c::WSAESHUTDOWN => BrokenPipe, _ => Uncategorized, } diff --git a/library/std/src/sys/pal/windows/os/tests.rs b/library/std/src/sys/io/error/windows/tests.rs similarity index 93% rename from library/std/src/sys/pal/windows/os/tests.rs rename to library/std/src/sys/io/error/windows/tests.rs index 458d6e11c2098..7fc545ad00666 100644 --- a/library/std/src/sys/pal/windows/os/tests.rs +++ b/library/std/src/sys/io/error/windows/tests.rs @@ -1,5 +1,5 @@ use crate::io::Error; -use crate::sys::c; +use crate::sys::pal::c; // tests `error_string` above #[test] diff --git a/library/std/src/sys/io/io_slice/windows.rs b/library/std/src/sys/io/io_slice/windows.rs deleted file mode 100644 index c3d8ec87c19e3..0000000000000 --- a/library/std/src/sys/io/io_slice/windows.rs +++ /dev/null @@ -1,82 +0,0 @@ -use crate::marker::PhantomData; -use crate::slice; -use crate::sys::c; - -#[derive(Copy, Clone)] -#[repr(transparent)] -pub struct IoSlice<'a> { - vec: c::WSABUF, - _p: PhantomData<&'a [u8]>, -} - -impl<'a> IoSlice<'a> { - #[inline] - pub fn new(buf: &'a [u8]) -> IoSlice<'a> { - assert!(buf.len() <= u32::MAX as usize); - IoSlice { - vec: c::WSABUF { len: buf.len() as u32, buf: buf.as_ptr() as *mut u8 }, - _p: PhantomData, - } - } - - #[inline] - pub fn advance(&mut self, n: usize) { - if (self.vec.len as usize) < n { - panic!("advancing IoSlice beyond its length"); - } - - unsafe { - self.vec.len -= n as u32; - self.vec.buf = self.vec.buf.add(n); - } - } - - #[inline] - pub const fn as_slice(&self) -> &'a [u8] { - unsafe { slice::from_raw_parts(self.vec.buf, self.vec.len as usize) } - } -} - -#[repr(transparent)] -pub struct IoSliceMut<'a> { - vec: c::WSABUF, - _p: PhantomData<&'a mut [u8]>, -} - -impl<'a> IoSliceMut<'a> { - #[inline] - pub fn new(buf: &'a mut [u8]) -> IoSliceMut<'a> { - assert!(buf.len() <= u32::MAX as usize); - IoSliceMut { - vec: c::WSABUF { len: buf.len() as u32, buf: buf.as_mut_ptr() }, - _p: PhantomData, - } - } - - #[inline] - pub fn advance(&mut self, n: usize) { - if (self.vec.len as usize) < n { - panic!("advancing IoSliceMut beyond its length"); - } - - unsafe { - self.vec.len -= n as u32; - self.vec.buf = self.vec.buf.add(n); - } - } - - #[inline] - pub fn as_slice(&self) -> &[u8] { - unsafe { slice::from_raw_parts(self.vec.buf, self.vec.len as usize) } - } - - #[inline] - pub const fn into_slice(self) -> &'a mut [u8] { - unsafe { slice::from_raw_parts_mut(self.vec.buf, self.vec.len as usize) } - } - - #[inline] - pub fn as_mut_slice(&mut self) -> &mut [u8] { - unsafe { slice::from_raw_parts_mut(self.vec.buf, self.vec.len as usize) } - } -} diff --git a/library/std/src/sys/io/kernel_copy/linux.rs b/library/std/src/sys/io/kernel_copy/linux.rs index 1c00d317f2a52..433fabc3f9733 100644 --- a/library/std/src/sys/io/kernel_copy/linux.rs +++ b/library/std/src/sys/io/kernel_copy/linux.rs @@ -48,12 +48,11 @@ use libc::sendfile as sendfile64; use libc::sendfile64; use libc::{EBADF, EINVAL, ENOSYS, EOPNOTSUPP, EOVERFLOW, EPERM, EXDEV}; -use super::CopyState; use crate::cmp::min; use crate::fs::{File, Metadata}; use crate::io::{ - BufRead, BufReader, BufWriter, Error, PipeReader, PipeWriter, Read, Result, StderrLock, - StdinLock, StdoutLock, Take, Write, + self, BufRead, BufReader, BufWriter, CopyState, Error, PipeReader, PipeWriter, Read, Result, + StderrLock, StdinLock, StdoutLock, Take, Write, }; use crate::mem::ManuallyDrop; use crate::net::TcpStream; @@ -70,12 +69,98 @@ use crate::sys::weak::syscall; #[cfg(test)] mod tests; -pub fn kernel_copy( - read: &mut R, - write: &mut W, -) -> Result { - let copier = Copier { read, write }; - SpecCopy::copy(copier) +#[doc(hidden)] +#[unstable(feature = "io_copy_internals", reason = "implementation detail", issue = "none")] +impl io::SpecCopy for File { + fn copy(read: &mut R, write: &mut W) -> Result { + SpecCopy::copy(Copier { read, write }) + } +} + +#[doc(hidden)] +#[unstable(feature = "io_copy_internals", reason = "implementation detail", issue = "none")] +impl io::SpecCopy for &File { + fn copy(read: &mut R, write: &mut W) -> Result { + SpecCopy::copy(Copier { read, write }) + } +} + +#[doc(hidden)] +#[unstable(feature = "io_copy_internals", reason = "implementation detail", issue = "none")] +impl io::SpecCopy for TcpStream { + fn copy(read: &mut R, write: &mut W) -> Result { + SpecCopy::copy(Copier { read, write }) + } +} + +#[doc(hidden)] +#[unstable(feature = "io_copy_internals", reason = "implementation detail", issue = "none")] +impl io::SpecCopy for &TcpStream { + fn copy(read: &mut R, write: &mut W) -> Result { + SpecCopy::copy(Copier { read, write }) + } +} + +#[doc(hidden)] +#[unstable(feature = "io_copy_internals", reason = "implementation detail", issue = "none")] +impl io::SpecCopy for UnixStream { + fn copy(read: &mut R, write: &mut W) -> Result { + SpecCopy::copy(Copier { read, write }) + } +} + +#[doc(hidden)] +#[unstable(feature = "io_copy_internals", reason = "implementation detail", issue = "none")] +impl io::SpecCopy for &UnixStream { + fn copy(read: &mut R, write: &mut W) -> Result { + SpecCopy::copy(Copier { read, write }) + } +} + +#[doc(hidden)] +#[unstable(feature = "io_copy_internals", reason = "implementation detail", issue = "none")] +impl io::SpecCopy for PipeReader { + fn copy(read: &mut R, write: &mut W) -> Result { + SpecCopy::copy(Copier { read, write }) + } +} + +#[doc(hidden)] +#[unstable(feature = "io_copy_internals", reason = "implementation detail", issue = "none")] +impl io::SpecCopy for &PipeReader { + fn copy(read: &mut R, write: &mut W) -> Result { + SpecCopy::copy(Copier { read, write }) + } +} + +#[doc(hidden)] +#[unstable(feature = "io_copy_internals", reason = "implementation detail", issue = "none")] +impl io::SpecCopy for ChildStdout { + fn copy(read: &mut R, write: &mut W) -> Result { + SpecCopy::copy(Copier { read, write }) + } +} + +#[doc(hidden)] +#[unstable(feature = "io_copy_internals", reason = "implementation detail", issue = "none")] +impl io::SpecCopy for ChildStderr { + fn copy(read: &mut R, write: &mut W) -> Result { + SpecCopy::copy(Copier { read, write }) + } +} + +#[doc(hidden)] +#[unstable(feature = "io_copy_internals", reason = "implementation detail", issue = "none")] +impl io::SpecCopy for StdinLock<'_> { + fn copy(read: &mut R, write: &mut W) -> Result { + SpecCopy::copy(Copier { read, write }) + } +} + +impl io::SpecCopy for CachedFileMetadata { + fn copy(read: &mut R, write: &mut W) -> Result { + SpecCopy::copy(Copier { read, write }) + } } /// This type represents either the inferred `FileType` of a `RawFd` based on the source diff --git a/library/std/src/sys/io/kernel_copy/linux/tests.rs b/library/std/src/sys/io/kernel_copy/linux/tests.rs index 9b2d9cbef9902..ba0828039dddb 100644 --- a/library/std/src/sys/io/kernel_copy/linux/tests.rs +++ b/library/std/src/sys/io/kernel_copy/linux/tests.rs @@ -166,10 +166,14 @@ fn bench_file_to_socket_copy(b: &mut test::Bencher) { let mut sink = crate::net::TcpStream::connect(sink_drainer.local_addr().unwrap()).unwrap(); let mut sink_drainer = sink_drainer.accept().unwrap().0; - crate::thread::spawn(move || { + let t = crate::thread::spawn(move || { let mut sink_buf = vec![0u8; 1024 * 1024]; loop { - sink_drainer.read(&mut sink_buf[..]).unwrap(); + let n = sink_drainer.read(&mut sink_buf[..]).unwrap(); + if n == 0 { + // EOF + break; + } } }); @@ -178,6 +182,9 @@ fn bench_file_to_socket_copy(b: &mut test::Bencher) { src.seek(SeekFrom::Start(0)).unwrap(); assert_eq!(BYTES as u64, io::copy(&mut src, &mut sink).unwrap()); }); + + drop(sink); // close our end, so that the thread goes down + t.join().unwrap(); } #[bench] @@ -196,10 +203,14 @@ fn bench_file_to_uds_copy(b: &mut test::Bencher) { let (mut sink, mut sink_drainer) = crate::os::unix::net::UnixStream::pair().unwrap(); - crate::thread::spawn(move || { + let t = crate::thread::spawn(move || { let mut sink_buf = vec![0u8; 1024 * 1024]; loop { - sink_drainer.read(&mut sink_buf[..]).unwrap(); + let n = sink_drainer.read(&mut sink_buf[..]).unwrap(); + if n == 0 { + // EOF + break; + } } }); @@ -208,6 +219,9 @@ fn bench_file_to_uds_copy(b: &mut test::Bencher) { src.seek(SeekFrom::Start(0)).unwrap(); assert_eq!(BYTES as u64, io::copy(&mut src, &mut sink).unwrap()); }); + + drop(sink); // close our end, so that the thread goes down + t.join().unwrap(); } #[cfg(any(target_os = "linux", target_os = "android"))] diff --git a/library/std/src/sys/io/kernel_copy/mod.rs b/library/std/src/sys/io/kernel_copy/mod.rs index a89279412cf7f..6f4b13042cd7f 100644 --- a/library/std/src/sys/io/kernel_copy/mod.rs +++ b/library/std/src/sys/io/kernel_copy/mod.rs @@ -1,23 +1,6 @@ -pub enum CopyState { - #[cfg_attr(not(any(target_os = "linux", target_os = "android")), expect(dead_code))] - Ended(u64), - Fallback(u64), -} - cfg_select! { any(target_os = "linux", target_os = "android") => { mod linux; - pub use linux::kernel_copy; - } - _ => { - use crate::io::{Result, Read, Write}; - - pub fn kernel_copy(_reader: &mut R, _writer: &mut W) -> Result - where - R: Read, - W: Write, - { - Ok(CopyState::Fallback(0)) - } } + _ => {} } diff --git a/library/std/src/sys/io/mod.rs b/library/std/src/sys/io/mod.rs index b3587ab63696a..33182e4eb5539 100644 --- a/library/std/src/sys/io/mod.rs +++ b/library/std/src/sys/io/mod.rs @@ -2,27 +2,6 @@ mod error; -mod io_slice { - cfg_select! { - any(target_family = "unix", target_os = "hermit", target_os = "solid_asp3", target_os = "trusty", target_os = "wasi") => { - mod iovec; - pub use iovec::*; - } - target_os = "windows" => { - mod windows; - pub use windows::*; - } - target_os = "uefi" => { - mod uefi; - pub use uefi::*; - } - _ => { - mod unsupported; - pub use unsupported::*; - } - } -} - mod is_terminal { cfg_select! { any(target_family = "unix", target_os = "wasi") => { @@ -50,23 +29,27 @@ mod is_terminal { mod kernel_copy; +#[allow(unused_imports, reason = "only used by certain target configurations")] +pub use alloc_crate::io::DEFAULT_BUF_SIZE; #[cfg_attr(not(target_os = "linux"), allow(unused_imports))] #[cfg(all( target_family = "unix", not(any(target_os = "dragonfly", target_os = "vxworks", target_os = "rtems")) ))] pub use error::errno_location; -#[cfg_attr(not(target_os = "linux"), allow(unused_imports))] #[cfg(any( - all(target_family = "unix", not(any(target_os = "vxworks", target_os = "rtems"))), + all( + target_family = "unix", + not(any( + target_os = "espidf", + target_os = "lynxos178", + target_os = "qurt", + target_os = "rtems", + target_os = "vxworks", + )) + ), target_os = "wasi", ))] pub use error::set_errno; -pub use error::{RawOsError, decode_error_kind, errno, error_string, is_interrupted}; -pub use io_slice::{IoSlice, IoSliceMut}; +pub use error::{decode_error_kind, errno, error_string, is_interrupted}; pub use is_terminal::is_terminal; -pub use kernel_copy::{CopyState, kernel_copy}; - -// Bare metal platforms usually have very small amounts of RAM -// (in the order of hundreds of KB) -pub const DEFAULT_BUF_SIZE: usize = if cfg!(target_os = "espidf") { 512 } else { 8 * 1024 }; diff --git a/library/std/src/sys/mod.rs b/library/std/src/sys/mod.rs index 5436c144d3330..58c8dc43e12ae 100644 --- a/library/std/src/sys/mod.rs +++ b/library/std/src/sys/mod.rs @@ -1,23 +1,24 @@ #![allow(unsafe_op_in_unsafe_fn)] -mod alloc; mod configure_builtins; mod helpers; mod pal; mod personality; +pub mod alloc; pub mod args; pub mod backtrace; pub mod cmath; pub mod env; pub mod env_consts; -pub mod exit_guard; +pub mod exit; pub mod fd; pub mod fs; pub mod io; pub mod net; pub mod os_str; pub mod path; +pub mod paths; pub mod pipe; pub mod platform_version; pub mod process; diff --git a/library/std/src/sys/net/connection/mod.rs b/library/std/src/sys/net/connection/mod.rs index 2f064914a8317..49a0f47c959d2 100644 --- a/library/std/src/sys/net/connection/mod.rs +++ b/library/std/src/sys/net/connection/mod.rs @@ -1,6 +1,6 @@ cfg_select! { any( - all(target_family = "unix", not(target_os = "l4re")), + target_family = "unix", target_os = "windows", target_os = "hermit", all(target_os = "wasi", any(target_env = "p2", target_env = "p3")), @@ -59,3 +59,22 @@ where None => Err(Error::NO_ADDRESSES), } } + +// Default implementation, may be overridden by platform-specific implementations. +#[cfg(not(all(target_vendor = "fortanix", target_env = "sgx")))] +pub(crate) fn lookup_host_string( + addr: &str, +) -> crate::io::Result> { + use crate::io; + + // Split the string by ':' and convert the second part to u16... + let Some((host, port_str)) = addr.rsplit_once(':') else { + return Err(io::const_error!(io::ErrorKind::InvalidInput, "invalid socket address")); + }; + let Ok(port) = port_str.parse::() else { + return Err(io::const_error!(io::ErrorKind::InvalidInput, "invalid port value")); + }; + + // ... and make the system look up the host. + crate::sys::net::lookup_host(host, port) +} diff --git a/library/std/src/sys/net/connection/motor.rs b/library/std/src/sys/net/connection/motor.rs index 79a528792106c..d42c70352367d 100644 --- a/library/std/src/sys/net/connection/motor.rs +++ b/library/std/src/sys/net/connection/motor.rs @@ -5,7 +5,7 @@ use crate::net::SocketAddr::{V4, V6}; use crate::net::{Ipv4Addr, Ipv6Addr, Shutdown, SocketAddr, ToSocketAddrs}; use crate::os::fd::{AsFd, AsRawFd, BorrowedFd, FromRawFd, IntoRawFd, RawFd}; use crate::sys::fd::FileDesc; -use crate::sys::{AsInner, FromInner, IntoInner, map_motor_error}; +use crate::sys::{AsInner, FromInner, IntoInner, map_motor_error, unsupported}; use crate::time::Duration; // We want to re-use as much of Rust's stdlib code as possible, @@ -65,7 +65,7 @@ impl TcpStream { moto_rt::fs::read(self.inner.as_raw_fd(), buf).map_err(map_motor_error) } - pub fn read_buf(&self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { crate::io::default_read_buf(|buf| self.read(buf), cursor) } @@ -127,6 +127,14 @@ impl TcpStream { moto_rt::net::linger(self.inner.as_raw_fd()).map_err(map_motor_error) } + pub fn set_keepalive(&self, _: bool) -> io::Result<()> { + unsupported() + } + + pub fn keepalive(&self) -> io::Result { + unsupported() + } + pub fn set_nodelay(&self, nodelay: bool) -> io::Result<()> { moto_rt::net::set_nodelay(self.inner.as_raw_fd(), nodelay).map_err(map_motor_error) } diff --git a/library/std/src/sys/net/connection/sgx.rs b/library/std/src/sys/net/connection/sgx.rs index 8c9c17d3f1714..acebb8c5bd60c 100644 --- a/library/std/src/sys/net/connection/sgx.rs +++ b/library/std/src/sys/net/connection/sgx.rs @@ -68,8 +68,8 @@ impl fmt::Debug for TcpStream { /// /// SGX doesn't support DNS resolution but rather accepts hostnames in /// the same place as socket addresses. So, to make e.g. -/// ```rust -/// TcpStream::connect("example.com:80")` +/// ```rust,ignore (incomplete example) +/// TcpStream::connect("example.com:80") /// ``` /// work, the DNS lookup returns a special error (`NonIpSockAddr`) instead, /// which contains the hostname being looked up. When `.to_socket_addrs()` @@ -169,7 +169,7 @@ impl TcpStream { self.inner.inner.read(buf) } - pub fn read_buf(&self, buf: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, buf: BorrowedCursor<'_, u8>) -> io::Result<()> { self.inner.inner.read_buf(buf) } @@ -219,6 +219,14 @@ impl TcpStream { sgx_ineffective(None) } + pub fn set_keepalive(&self, _: bool) -> io::Result<()> { + sgx_ineffective(()) + } + + pub fn keepalive(&self) -> io::Result { + sgx_ineffective(false) + } + pub fn set_nodelay(&self, _: bool) -> io::Result<()> { sgx_ineffective(()) } @@ -506,9 +514,23 @@ impl Iterator for LookupHost { } } +pub(crate) fn lookup_host_string(addr: impl Into) -> io::Result { + Err(io::Error::new(io::ErrorKind::Uncategorized, NonIpSockAddr { host: addr.into() })) +} + pub fn lookup_host(host: &str, port: u16) -> io::Result { - Err(io::Error::new( - io::ErrorKind::Uncategorized, - NonIpSockAddr { host: format!("{host}:{port}") }, - )) + lookup_host_string(format!("{host}:{port}")) +} + +#[cfg(test)] +mod tests { + use super::*; + + #[test] + fn unparseable_sockaddr() { + let addr = "local"; + let error = addr.to_socket_addrs().unwrap_err(); + let non_ip_addr = error.downcast::().unwrap(); + assert_eq!(addr, non_ip_addr.host); + } } diff --git a/library/std/src/sys/net/connection/socket/hermit.rs b/library/std/src/sys/net/connection/socket/hermit.rs index 59f515d31aff9..f43395ce8fd80 100644 --- a/library/std/src/sys/net/connection/socket/hermit.rs +++ b/library/std/src/sys/net/connection/socket/hermit.rs @@ -132,7 +132,7 @@ impl Socket { Ok(Socket(unsafe { FileDesc::from_raw_fd(fd) })) } - fn recv_with_flags(&self, mut buf: BorrowedCursor<'_>, flags: i32) -> io::Result<()> { + fn recv_with_flags(&self, mut buf: BorrowedCursor<'_, u8>, flags: i32) -> io::Result<()> { let ret = cvt(unsafe { netc::recv( self.0.as_raw_fd(), @@ -142,7 +142,7 @@ impl Socket { ) })?; unsafe { - buf.advance_unchecked(ret as usize); + buf.advance(ret as usize); } Ok(()) } @@ -159,7 +159,7 @@ impl Socket { Ok(buf.len()) } - pub fn read_buf(&self, buf: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, buf: BorrowedCursor<'_, u8>) -> io::Result<()> { self.recv_with_flags(buf, 0) } @@ -260,7 +260,7 @@ impl Socket { pub fn set_linger(&self, linger: Option) -> io::Result<()> { let linger = netc::linger { l_onoff: linger.is_some() as i32, - l_linger: linger.unwrap_or_default().as_secs() as libc::c_int, + l_linger: cmp::min(linger.unwrap_or_default().as_secs(), c_int::MAX as u64) as c_int, }; unsafe { setsockopt(self, netc::SOL_SOCKET, netc::SO_LINGER, linger) } @@ -272,6 +272,15 @@ impl Socket { Ok((val.l_onoff != 0).then(|| Duration::from_secs(val.l_linger as u64))) } + pub fn set_keepalive(&self, keepalive: bool) -> io::Result<()> { + unsafe { setsockopt(self, netc::SOL_SOCKET, netc::SO_KEEPALIVE, keepalive as c_int) } + } + + pub fn keepalive(&self) -> io::Result { + let raw: c_int = unsafe { getsockopt(self, netc::SOL_SOCKET, netc::SO_KEEPALIVE)? }; + Ok(raw != 0) + } + pub fn set_nodelay(&self, nodelay: bool) -> io::Result<()> { let value: i32 = if nodelay { 1 } else { 0 }; unsafe { setsockopt(self, netc::IPPROTO_TCP, netc::TCP_NODELAY, value) } @@ -295,8 +304,8 @@ impl Socket { } pub fn take_error(&self) -> io::Result> { - let raw: c_int = unsafe { getsockopt(self, libc::SOL_SOCKET, libc::SO_ERROR)? }; - if raw == 0 { Ok(None) } else { Ok(Some(io::Error::from_raw_os_error(raw as i32))) } + let raw = unsafe { getsockopt(self, libc::SOL_SOCKET, libc::SO_ERROR)? }; + if raw == 0 { Ok(None) } else { Ok(Some(io::Error::from_raw_os_error(raw))) } } pub fn as_raw(&self) -> RawFd { diff --git a/library/std/src/sys/net/connection/socket/mod.rs b/library/std/src/sys/net/connection/socket/mod.rs index 256b99dfa9874..9defc24ee2e10 100644 --- a/library/std/src/sys/net/connection/socket/mod.rs +++ b/library/std/src/sys/net/connection/socket/mod.rs @@ -1,4 +1,5 @@ #[cfg(test)] +#[cfg(not(target_os = "l4re"))] mod tests; use crate::ffi::{c_int, c_void}; @@ -35,6 +36,9 @@ cfg_select! { use netc as c; +const MAX_SEND_LEN: usize = + if cfg!(target_vendor = "apple") { c_int::MAX as usize } else { ::MAX as usize }; + cfg_select! { any( target_os = "dragonfly", @@ -46,26 +50,31 @@ cfg_select! { target_os = "haiku", target_os = "l4re", target_os = "nto", + target_os = "qnx", target_os = "nuttx", target_vendor = "apple", ) => { - use c::IPV6_JOIN_GROUP as IPV6_ADD_MEMBERSHIP; - use c::IPV6_LEAVE_GROUP as IPV6_DROP_MEMBERSHIP; + use c::{IPV6_JOIN_GROUP as IPV6_ADD_MEMBERSHIP, IPV6_LEAVE_GROUP as IPV6_DROP_MEMBERSHIP}; } _ => { - use c::IPV6_ADD_MEMBERSHIP; - use c::IPV6_DROP_MEMBERSHIP; + use c::{IPV6_ADD_MEMBERSHIP, IPV6_DROP_MEMBERSHIP}; } } cfg_select! { any( - target_os = "linux", target_os = "android", + target_os = "linux", + target_os = "android", target_os = "hurd", - target_os = "dragonfly", target_os = "freebsd", - target_os = "openbsd", target_os = "netbsd", - target_os = "solaris", target_os = "illumos", - target_os = "haiku", target_os = "nto", + target_os = "dragonfly", + target_os = "freebsd", + target_os = "openbsd", + target_os = "netbsd", + target_os = "solaris", + target_os = "illumos", + target_os = "haiku", + target_os = "nto", + target_os = "qnx", target_os = "cygwin", ) => { use libc::MSG_NOSIGNAL; @@ -77,10 +86,14 @@ cfg_select! { cfg_select! { any( - target_os = "dragonfly", target_os = "freebsd", - target_os = "openbsd", target_os = "netbsd", - target_os = "solaris", target_os = "illumos", + target_os = "dragonfly", + target_os = "freebsd", + target_os = "openbsd", + target_os = "netbsd", + target_os = "solaris", + target_os = "illumos", target_os = "nto", + target_os = "qnx", ) => { use crate::ffi::c_uchar; type IpV4MultiCastType = c_uchar; @@ -414,7 +427,7 @@ impl TcpStream { self.inner.read(buf) } - pub fn read_buf(&self, buf: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, buf: BorrowedCursor<'_, u8>) -> io::Result<()> { self.inner.read_buf(buf) } @@ -428,7 +441,7 @@ impl TcpStream { } pub fn write(&self, buf: &[u8]) -> io::Result { - let len = cmp::min(buf.len(), ::MAX as usize) as wrlen_t; + let len = cmp::min(buf.len(), MAX_SEND_LEN) as wrlen_t; let ret = cvt(unsafe { c::send(self.inner.as_raw(), buf.as_ptr() as *const c_void, len, MSG_NOSIGNAL) })?; @@ -468,6 +481,14 @@ impl TcpStream { self.inner.linger() } + pub fn set_keepalive(&self, keepalive: bool) -> io::Result<()> { + self.inner.set_keepalive(keepalive) + } + + pub fn keepalive(&self) -> io::Result { + self.inner.keepalive() + } + pub fn set_nodelay(&self, nodelay: bool) -> io::Result<()> { self.inner.set_nodelay(nodelay) } @@ -696,14 +717,18 @@ impl UdpSocket { self.inner.peek_from(buf) } + // `MAX_SEND_LEN` is `usize::MAX` off Apple/Windows, where the guard is a no-op. + #[allow(clippy::absurd_extreme_comparisons)] pub fn send_to(&self, buf: &[u8], dst: &SocketAddr) -> io::Result { - let len = cmp::min(buf.len(), ::MAX as usize) as wrlen_t; + if buf.len() > MAX_SEND_LEN { + return Err(io::Error::from_raw_os_error(c::EMSGSIZE)); + } let (dst, dstlen) = socket_addr_to_c(dst); let ret = cvt(unsafe { c::sendto( self.inner.as_raw(), buf.as_ptr() as *const c_void, - len, + buf.len() as wrlen_t, MSG_NOSIGNAL, dst.as_ptr(), dstlen, @@ -849,10 +874,19 @@ impl UdpSocket { self.inner.peek(buf) } + // `MAX_SEND_LEN` is `usize::MAX` off Apple/Windows, where the guard is a no-op. + #[allow(clippy::absurd_extreme_comparisons)] pub fn send(&self, buf: &[u8]) -> io::Result { - let len = cmp::min(buf.len(), ::MAX as usize) as wrlen_t; + if buf.len() > MAX_SEND_LEN { + return Err(io::Error::from_raw_os_error(c::EMSGSIZE)); + } let ret = cvt(unsafe { - c::send(self.inner.as_raw(), buf.as_ptr() as *const c_void, len, MSG_NOSIGNAL) + c::send( + self.inner.as_raw(), + buf.as_ptr() as *const c_void, + buf.len() as wrlen_t, + MSG_NOSIGNAL, + ) })?; Ok(ret as usize) } diff --git a/library/std/src/sys/net/connection/socket/solid.rs b/library/std/src/sys/net/connection/socket/solid.rs index e20a3fbb76b72..9fe08ec951e75 100644 --- a/library/std/src/sys/net/connection/socket/solid.rs +++ b/library/std/src/sys/net/connection/socket/solid.rs @@ -6,6 +6,7 @@ use crate::ffi::CStr; use crate::io::{self, BorrowedBuf, BorrowedCursor, ErrorKind, IoSlice, IoSliceMut}; use crate::net::{Shutdown, SocketAddr}; use crate::os::solid::io::{AsFd, AsRawFd, BorrowedFd, FromRawFd, IntoRawFd, OwnedFd}; +use crate::sys::pal::unsupported; use crate::sys::{FromInner, IntoInner, abi}; use crate::time::Duration; use crate::{cmp, mem, ptr, str}; @@ -141,8 +142,13 @@ impl Socket { return Err(io::Error::ZERO_TIMEOUT); } - let mut timeout = - netc::timeval { tv_sec: timeout.as_secs() as _, tv_usec: timeout.subsec_micros() as _ }; + let secs = if timeout.as_secs() > netc::c_long::MAX as u64 { + netc::c_long::MAX + } else { + timeout.as_secs() as netc::c_long + }; + + let mut timeout = netc::timeval { tv_sec: secs, tv_usec: timeout.subsec_micros() as _ }; if timeout.tv_sec == 0 && timeout.tv_usec == 0 { timeout.tv_usec = 1; } @@ -185,12 +191,12 @@ impl Socket { Ok(Self(self.0.try_clone()?)) } - fn recv_with_flags(&self, mut buf: BorrowedCursor<'_>, flags: c_int) -> io::Result<()> { + fn recv_with_flags(&self, mut buf: BorrowedCursor<'_, u8>, flags: c_int) -> io::Result<()> { let ret = cvt(unsafe { netc::recv(self.as_raw_fd(), buf.as_mut().as_mut_ptr().cast(), buf.capacity(), flags) })?; unsafe { - buf.advance_unchecked(ret as usize); + buf.advance(ret as usize); } Ok(()) } @@ -207,7 +213,7 @@ impl Socket { Ok(buf.len()) } - pub fn read_buf(&self, buf: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, buf: BorrowedCursor<'_, u8>) -> io::Result<()> { self.recv_with_flags(buf, 0) } @@ -319,7 +325,8 @@ impl Socket { pub fn set_linger(&self, linger: Option) -> io::Result<()> { let linger = netc::linger { l_onoff: linger.is_some() as netc::c_int, - l_linger: linger.unwrap_or_default().as_secs() as netc::c_int, + l_linger: cmp::min(linger.unwrap_or_default().as_secs(), netc::c_int::MAX as u64) + as netc::c_int, }; unsafe { setsockopt(self, netc::SOL_SOCKET, netc::SO_LINGER, linger) } @@ -331,6 +338,14 @@ impl Socket { Ok((val.l_onoff != 0).then(|| Duration::from_secs(val.l_linger as u64))) } + pub fn set_keepalive(&self, _: bool) -> io::Result<()> { + unsupported() + } + + pub fn keepalive(&self) -> io::Result { + unsupported() + } + pub fn set_nodelay(&self, nodelay: bool) -> io::Result<()> { unsafe { setsockopt(self, netc::IPPROTO_TCP, netc::TCP_NODELAY, nodelay as c_int) } } diff --git a/library/std/src/sys/net/connection/socket/tests.rs b/library/std/src/sys/net/connection/socket/tests.rs index 049355afca7ac..e6f02d7a93859 100644 --- a/library/std/src/sys/net/connection/socket/tests.rs +++ b/library/std/src/sys/net/connection/socket/tests.rs @@ -17,3 +17,14 @@ fn no_lookup_host_duplicates() { "There should be no duplicate localhost entries" ); } + +// #115325: on Apple, `send` rejects a length > `c_int::MAX` with `EINVAL`, so +// the clamp must not regress to the unbounded `wrlen_t::MAX`. +#[test] +fn max_send_len_within_platform_limit() { + if cfg!(target_vendor = "apple") { + assert_eq!(MAX_SEND_LEN, c_int::MAX as usize); + } else { + assert_eq!(MAX_SEND_LEN, ::MAX as usize); + } +} diff --git a/library/std/src/sys/net/connection/socket/unix.rs b/library/std/src/sys/net/connection/socket/unix.rs index 5e20c0ffdfa6a..15e9dc2c7cc9d 100644 --- a/library/std/src/sys/net/connection/socket/unix.rs +++ b/library/std/src/sys/net/connection/socket/unix.rs @@ -76,6 +76,7 @@ impl Socket { target_os = "openbsd", target_os = "cygwin", target_os = "nto", + target_os = "qnx", target_os = "solaris", ) => { // On platforms that support it we pass the SOCK_CLOEXEC @@ -87,7 +88,9 @@ impl Socket { // DragonFlyBSD, FreeBSD and NetBSD use `SO_NOSIGPIPE` as a `setsockopt` // flag to disable `SIGPIPE` emission on socket. #[cfg(any(target_os = "freebsd", target_os = "netbsd", target_os = "dragonfly"))] - unsafe { setsockopt(&socket, libc::SOL_SOCKET, libc::SO_NOSIGPIPE, 1)? }; + unsafe { + setsockopt(&socket, libc::SOL_SOCKET, libc::SO_NOSIGPIPE, 1)? + }; Ok(socket) } @@ -100,7 +103,9 @@ impl Socket { // macOS and iOS use `SO_NOSIGPIPE` as a `setsockopt` // flag to disable `SIGPIPE` emission on socket. #[cfg(target_vendor = "apple")] - unsafe { setsockopt(&socket, libc::SOL_SOCKET, libc::SO_NOSIGPIPE, 1)? }; + unsafe { + setsockopt(&socket, libc::SOL_SOCKET, libc::SO_NOSIGPIPE, 1)? + }; Ok(socket) } @@ -124,10 +129,14 @@ impl Socket { target_os = "openbsd", target_os = "cygwin", target_os = "nto", + target_os = "qnx", ) => { // Like above, set cloexec atomically cvt(libc::socketpair(fam, ty | libc::SOCK_CLOEXEC, 0, fds.as_mut_ptr()))?; - Ok((Socket(FileDesc::from_raw_fd(fds[0])), Socket(FileDesc::from_raw_fd(fds[1])))) + Ok(( + Socket(FileDesc::from_raw_fd(fds[0])), + Socket(FileDesc::from_raw_fd(fds[1])), + )) } _ => { cvt(libc::socketpair(fam, ty, 0, fds.as_mut_ptr()))?; @@ -254,20 +263,17 @@ impl Socket { target_os = "netbsd", target_os = "openbsd", target_os = "cygwin", - ) => { - unsafe { - let fd = cvt_r(|| libc::accept4(self.as_raw_fd(), storage, len, libc::SOCK_CLOEXEC))?; - Ok(Socket(FileDesc::from_raw_fd(fd))) - } - } - _ => { - unsafe { - let fd = cvt_r(|| libc::accept(self.as_raw_fd(), storage, len))?; - let fd = FileDesc::from_raw_fd(fd); - fd.set_cloexec()?; - Ok(Socket(fd)) - } - } + ) => unsafe { + let fd = + cvt_r(|| libc::accept4(self.as_raw_fd(), storage, len, libc::SOCK_CLOEXEC))?; + Ok(Socket(FileDesc::from_raw_fd(fd))) + }, + _ => unsafe { + let fd = cvt_r(|| libc::accept(self.as_raw_fd(), storage, len))?; + let fd = FileDesc::from_raw_fd(fd); + fd.set_cloexec()?; + Ok(Socket(fd)) + }, } } @@ -277,14 +283,14 @@ impl Socket { #[cfg(not(target_os = "wasi"))] pub fn send_with_flags(&self, buf: &[u8], flags: c_int) -> io::Result { - let len = cmp::min(buf.len(), ::MAX as usize) as wrlen_t; + let len = cmp::min(buf.len(), super::MAX_SEND_LEN) as wrlen_t; let ret = cvt(unsafe { libc::send(self.as_raw_fd(), buf.as_ptr() as *const c_void, len, flags) })?; Ok(ret as usize) } - fn recv_with_flags(&self, mut buf: BorrowedCursor<'_>, flags: c_int) -> io::Result<()> { + fn recv_with_flags(&self, mut buf: BorrowedCursor<'_, u8>, flags: c_int) -> io::Result<()> { let ret = cvt(unsafe { libc::recv( self.as_raw_fd(), @@ -294,7 +300,7 @@ impl Socket { ) })?; unsafe { - buf.advance_unchecked(ret as usize); + buf.advance(ret as usize); } Ok(()) } @@ -311,7 +317,7 @@ impl Socket { Ok(buf.len()) } - pub fn read_buf(&self, buf: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, buf: BorrowedCursor<'_, u8>) -> io::Result<()> { self.recv_with_flags(buf, 0) } @@ -394,10 +400,7 @@ impl Socket { } else { dur.as_secs() as libc::time_t }; - let mut timeout = libc::timeval { - tv_sec: secs, - tv_usec: dur.subsec_micros() as libc::suseconds_t, - }; + let mut timeout = libc::timeval { tv_sec: secs, tv_usec: dur.subsec_micros() as _ }; if timeout.tv_sec == 0 && timeout.tv_usec == 0 { timeout.tv_usec = 1; } @@ -432,8 +435,8 @@ impl Socket { #[cfg(not(target_os = "cygwin"))] pub fn set_linger(&self, linger: Option) -> io::Result<()> { let linger = libc::linger { - l_onoff: linger.is_some() as libc::c_int, - l_linger: linger.unwrap_or_default().as_secs() as libc::c_int, + l_onoff: linger.is_some() as c_int, + l_linger: cmp::min(linger.unwrap_or_default().as_secs(), c_int::MAX as u64) as c_int, }; unsafe { setsockopt(self, libc::SOL_SOCKET, SO_LINGER, linger) } @@ -443,7 +446,8 @@ impl Socket { pub fn set_linger(&self, linger: Option) -> io::Result<()> { let linger = libc::linger { l_onoff: linger.is_some() as libc::c_ushort, - l_linger: linger.unwrap_or_default().as_secs() as libc::c_ushort, + l_linger: cmp::min(linger.unwrap_or_default().as_secs(), libc::c_ushort::MAX as u64) + as libc::c_ushort, }; unsafe { setsockopt(self, libc::SOL_SOCKET, SO_LINGER, linger) } @@ -455,6 +459,15 @@ impl Socket { Ok((val.l_onoff != 0).then(|| Duration::from_secs(val.l_linger as u64))) } + pub fn set_keepalive(&self, keepalive: bool) -> io::Result<()> { + unsafe { setsockopt(self, libc::SOL_SOCKET, libc::SO_KEEPALIVE, keepalive as c_int) } + } + + pub fn keepalive(&self) -> io::Result { + let raw: c_int = unsafe { getsockopt(self, libc::SOL_SOCKET, libc::SO_KEEPALIVE)? }; + Ok(raw != 0) + } + pub fn set_nodelay(&self, nodelay: bool) -> io::Result<()> { unsafe { setsockopt(self, libc::IPPROTO_TCP, libc::TCP_NODELAY, nodelay as c_int) } } @@ -684,7 +697,7 @@ fn on_resolver_failure() { use crate::sys; // If the version fails to parse, we treat it the same as "not glibc". - if let Some(version) = sys::os::glibc_version() { + if let Some(version) = sys::pal::conf::glibc_version() { if version < (2, 26) { unsafe { libc::res_init() }; } diff --git a/library/std/src/sys/net/connection/socket/windows.rs b/library/std/src/sys/net/connection/socket/windows.rs index b23fb9c09f871..075e77bc4457c 100644 --- a/library/std/src/sys/net/connection/socket/windows.rs +++ b/library/std/src/sys/net/connection/socket/windows.rs @@ -31,8 +31,8 @@ pub(super) mod netc { IP_DROP_MEMBERSHIP, IP_MULTICAST_LOOP, IP_MULTICAST_TTL, IP_TTL, IPPROTO_IP, IPPROTO_IPV6, IPV6_ADD_MEMBERSHIP, IPV6_DROP_MEMBERSHIP, IPV6_MULTICAST_LOOP, IPV6_V6ONLY, SO_BROADCAST, SO_RCVTIMEO, SO_SNDTIMEO, SOCK_DGRAM, SOCK_STREAM, SOCKADDR as sockaddr, - SOCKADDR_STORAGE as sockaddr_storage, SOL_SOCKET, bind, connect, freeaddrinfo, getpeername, - getsockname, getsockopt, listen, setsockopt, + SOCKADDR_STORAGE as sockaddr_storage, SOL_SOCKET, WSAEMSGSIZE as EMSGSIZE, bind, connect, + freeaddrinfo, getpeername, getsockname, getsockopt, listen, setsockopt, }; #[allow(non_camel_case_types)] @@ -225,7 +225,7 @@ impl Socket { Ok(Self(self.0.try_clone()?)) } - fn recv_with_flags(&self, mut buf: BorrowedCursor<'_>, flags: c_int) -> io::Result<()> { + fn recv_with_flags(&self, mut buf: BorrowedCursor<'_, u8>, flags: c_int) -> io::Result<()> { // On unix when a socket is shut down all further reads return 0, so we // do the same on windows to map a shut down socket to returning EOF. let length = cmp::min(buf.capacity(), i32::MAX as usize) as i32; @@ -243,7 +243,7 @@ impl Socket { } } _ => { - unsafe { buf.advance_unchecked(result as usize) }; + unsafe { buf.advance(result as usize) }; Ok(()) } } @@ -255,7 +255,7 @@ impl Socket { Ok(buf.len()) } - pub fn read_buf(&self, buf: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, buf: BorrowedCursor<'_, u8>) -> io::Result<()> { self.recv_with_flags(buf, 0) } @@ -413,7 +413,8 @@ impl Socket { pub fn set_linger(&self, linger: Option) -> io::Result<()> { let linger = c::LINGER { l_onoff: linger.is_some() as c_ushort, - l_linger: linger.unwrap_or_default().as_secs() as c_ushort, + l_linger: cmp::min(linger.unwrap_or_default().as_secs(), c_ushort::MAX as u64) + as c_ushort, }; unsafe { setsockopt(self, c::SOL_SOCKET, c::SO_LINGER, linger) } @@ -425,6 +426,15 @@ impl Socket { Ok((val.l_onoff != 0).then(|| Duration::from_secs(val.l_linger as u64))) } + pub fn set_keepalive(&self, keepalive: bool) -> io::Result<()> { + unsafe { setsockopt(self, c::SOL_SOCKET, c::SO_KEEPALIVE, keepalive as c::BOOL) } + } + + pub fn keepalive(&self) -> io::Result { + let raw: c::BOOL = unsafe { getsockopt(self, c::SOL_SOCKET, c::SO_KEEPALIVE)? }; + Ok(raw != 0) + } + pub fn set_nodelay(&self, nodelay: bool) -> io::Result<()> { unsafe { setsockopt(self, c::IPPROTO_TCP, c::TCP_NODELAY, nodelay as c::BOOL) } } diff --git a/library/std/src/sys/net/connection/uefi/mod.rs b/library/std/src/sys/net/connection/uefi/mod.rs index 107a3e23733de..e839b8728de8e 100644 --- a/library/std/src/sys/net/connection/uefi/mod.rs +++ b/library/std/src/sys/net/connection/uefi/mod.rs @@ -64,7 +64,7 @@ impl TcpStream { self.inner.read(buf, self.read_timeout()?) } - pub fn read_buf(&self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { crate::io::default_read_buf(|buf| self.read(buf), cursor) } @@ -112,6 +112,14 @@ impl TcpStream { unsupported() } + pub fn set_keepalive(&self, _: bool) -> io::Result<()> { + unsupported() + } + + pub fn keepalive(&self) -> io::Result { + unsupported() + } + pub fn set_nodelay(&self, _: bool) -> io::Result<()> { unsupported() } @@ -139,7 +147,8 @@ impl TcpStream { impl fmt::Debug for TcpStream { fn fmt(&self, _f: &mut fmt::Formatter<'_>) -> fmt::Result { - todo!() + // FIXME(implement this) + unimplemented!() } } @@ -198,7 +207,8 @@ impl TcpListener { impl fmt::Debug for TcpListener { fn fmt(&self, _f: &mut fmt::Formatter<'_>) -> fmt::Result { - todo!() + // FIXME(implement this) + unimplemented!() } } diff --git a/library/std/src/sys/net/connection/uefi/tcp.rs b/library/std/src/sys/net/connection/uefi/tcp.rs index 1e58db0d70468..85962ce880d55 100644 --- a/library/std/src/sys/net/connection/uefi/tcp.rs +++ b/library/std/src/sys/net/connection/uefi/tcp.rs @@ -9,7 +9,9 @@ pub(crate) enum Tcp { V4(tcp4::Tcp4), } -// SAFETY: UEFI has no threads. +// SAFETY: UEFI has no regular threads, and as per +// std does not support being invoked from "irregular threads" such as interrupt handlers or other +// CPU cores that run outside the scope of UEFI. unsafe impl Send for Tcp {} impl Tcp { diff --git a/library/std/src/sys/net/connection/unsupported.rs b/library/std/src/sys/net/connection/unsupported.rs index fb18e8dec557c..7a4d3a97b8324 100644 --- a/library/std/src/sys/net/connection/unsupported.rs +++ b/library/std/src/sys/net/connection/unsupported.rs @@ -39,7 +39,7 @@ impl TcpStream { self.0 } - pub fn read_buf(&self, _buf: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, _buf: BorrowedCursor<'_, u8>) -> io::Result<()> { self.0 } @@ -87,6 +87,14 @@ impl TcpStream { self.0 } + pub fn set_keepalive(&self, _: bool) -> io::Result<()> { + self.0 + } + + pub fn keepalive(&self) -> io::Result { + self.0 + } + pub fn set_nodelay(&self, _: bool) -> io::Result<()> { self.0 } diff --git a/library/std/src/sys/net/connection/wasip1.rs b/library/std/src/sys/net/connection/wasip1.rs index 95a4ab2fbf0fd..d461ea85f9fea 100644 --- a/library/std/src/sys/net/connection/wasip1.rs +++ b/library/std/src/sys/net/connection/wasip1.rs @@ -91,7 +91,7 @@ impl TcpStream { self.read_vectored(&mut [IoSliceMut::new(buf)]) } - pub fn read_buf(&self, buf: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, buf: BorrowedCursor<'_, u8>) -> io::Result<()> { self.socket().as_inner().read_buf(buf) } @@ -125,12 +125,12 @@ impl TcpStream { pub fn shutdown(&self, how: Shutdown) -> io::Result<()> { let wasi_how = match how { - Shutdown::Read => wasi::SDFLAGS_RD, - Shutdown::Write => wasi::SDFLAGS_WR, - Shutdown::Both => wasi::SDFLAGS_RD | wasi::SDFLAGS_WR, + Shutdown::Read => wasip1::SDFLAGS_RD, + Shutdown::Write => wasip1::SDFLAGS_WR, + Shutdown::Both => wasip1::SDFLAGS_RD | wasip1::SDFLAGS_WR, }; - unsafe { wasi::sock_shutdown(self.socket().as_raw_fd() as _, wasi_how).map_err(err2io) } + unsafe { wasip1::sock_shutdown(self.socket().as_raw_fd() as _, wasi_how).map_err(err2io) } } pub fn duplicate(&self) -> io::Result { @@ -145,6 +145,14 @@ impl TcpStream { unsupported() } + pub fn set_keepalive(&self, _: bool) -> io::Result<()> { + unsupported() + } + + pub fn keepalive(&self) -> io::Result { + unsupported() + } + pub fn set_nodelay(&self, _: bool) -> io::Result<()> { unsupported() } @@ -167,19 +175,20 @@ impl TcpStream { pub fn set_nonblocking(&self, state: bool) -> io::Result<()> { let fdstat = unsafe { - wasi::fd_fdstat_get(self.socket().as_inner().as_raw_fd() as wasi::Fd).map_err(err2io)? + wasip1::fd_fdstat_get(self.socket().as_inner().as_raw_fd() as wasip1::Fd) + .map_err(err2io)? }; let mut flags = fdstat.fs_flags; if state { - flags |= wasi::FDFLAGS_NONBLOCK; + flags |= wasip1::FDFLAGS_NONBLOCK; } else { - flags &= !wasi::FDFLAGS_NONBLOCK; + flags &= !wasip1::FDFLAGS_NONBLOCK; } unsafe { - wasi::fd_fdstat_set_flags(self.socket().as_inner().as_raw_fd() as wasi::Fd, flags) + wasip1::fd_fdstat_set_flags(self.socket().as_inner().as_raw_fd() as wasip1::Fd, flags) .map_err(err2io) } } @@ -221,7 +230,7 @@ impl TcpListener { pub fn accept(&self) -> io::Result<(TcpStream, SocketAddr)> { let fd = unsafe { - wasi::sock_accept(self.as_inner().as_inner().as_raw_fd() as _, 0).map_err(err2io)? + wasip1::sock_accept(self.as_inner().as_inner().as_raw_fd() as _, 0).map_err(err2io)? }; Ok(( @@ -258,19 +267,20 @@ impl TcpListener { pub fn set_nonblocking(&self, state: bool) -> io::Result<()> { let fdstat = unsafe { - wasi::fd_fdstat_get(self.socket().as_inner().as_raw_fd() as wasi::Fd).map_err(err2io)? + wasip1::fd_fdstat_get(self.socket().as_inner().as_raw_fd() as wasip1::Fd) + .map_err(err2io)? }; let mut flags = fdstat.fs_flags; if state { - flags |= wasi::FDFLAGS_NONBLOCK; + flags |= wasip1::FDFLAGS_NONBLOCK; } else { - flags &= !wasi::FDFLAGS_NONBLOCK; + flags &= !wasip1::FDFLAGS_NONBLOCK; } unsafe { - wasi::fd_fdstat_set_flags(self.socket().as_inner().as_raw_fd() as wasi::Fd, flags) + wasip1::fd_fdstat_set_flags(self.socket().as_inner().as_raw_fd() as wasip1::Fd, flags) .map_err(err2io) } } diff --git a/library/std/src/sys/net/connection/xous/dns.rs b/library/std/src/sys/net/connection/xous/dns.rs index b139376f59768..0ed15b28c36e1 100644 --- a/library/std/src/sys/net/connection/xous/dns.rs +++ b/library/std/src/sys/net/connection/xous/dns.rs @@ -43,9 +43,8 @@ impl Iterator for LookupHost { return None; } let mut new_addr = [0u8; 16]; - for (src, octet) in self.data.0[(self.offset + 1)..(self.offset + 16 + 1)] - .iter() - .zip(new_addr.iter_mut()) + for (src, octet) in + self.data.0[self.offset..(self.offset + 16)].iter().zip(new_addr.iter_mut()) { *octet = *src; } diff --git a/library/std/src/sys/net/connection/xous/tcplistener.rs b/library/std/src/sys/net/connection/xous/tcplistener.rs index 8818ef2ca9a9b..f406b4381f29a 100644 --- a/library/std/src/sys/net/connection/xous/tcplistener.rs +++ b/library/std/src/sys/net/connection/xous/tcplistener.rs @@ -129,12 +129,13 @@ impl TcpListener { 0, ) { if receive_request.raw[0] != 0 { - // error case - if receive_request.raw[1] == NetError::TimedOut as u8 { + // Error case — code lives at byte 4 (where the send path + // also reads it). Byte 1 is part of the marker header. + if receive_request.raw[4] == NetError::TimedOut as u8 { return Err(io::const_error!(io::ErrorKind::TimedOut, "accept timed out")); - } else if receive_request.raw[1] == NetError::WouldBlock as u8 { + } else if receive_request.raw[4] == NetError::WouldBlock as u8 { return Err(io::const_error!(io::ErrorKind::WouldBlock, "accept would block")); - } else if receive_request.raw[1] == NetError::LibraryError as u8 { + } else if receive_request.raw[4] == NetError::LibraryError as u8 { return Err(io::const_error!(io::ErrorKind::Other, "library error")); } else { return Err(io::const_error!(io::ErrorKind::Other, "library error")); diff --git a/library/std/src/sys/net/connection/xous/tcpstream.rs b/library/std/src/sys/net/connection/xous/tcpstream.rs index 4df75453d1f45..45fe0418a27fa 100644 --- a/library/std/src/sys/net/connection/xous/tcpstream.rs +++ b/library/std/src/sys/net/connection/xous/tcpstream.rs @@ -213,11 +213,14 @@ impl TcpStream { } else { let result = receive_request.raw; if result[0] != 0 { - if result[1] == 8 { + // The error code lives at byte 4 of the kernel's response buffer + // (matches the byte the send path reads in `write` below). Byte 1 + // is part of the marker header, not the code. + if result[4] == 8 { // timed out return Err(io::const_error!(io::ErrorKind::TimedOut, "timeout")); } - if result[1] == 9 { + if result[4] == 9 { // would block return Err(io::const_error!(io::ErrorKind::WouldBlock, "would block")); } @@ -238,7 +241,7 @@ impl TcpStream { crate::io::default_read_vectored(|b| self.read(b), bufs) } - pub fn read_buf(&self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { crate::io::default_read_buf(|buf| self.read(buf), cursor) } @@ -353,6 +356,14 @@ impl TcpStream { unimpl!(); } + pub fn set_keepalive(&self, _: bool) -> io::Result<()> { + unimpl!(); + } + + pub fn keepalive(&self) -> io::Result { + unimpl!(); + } + pub fn set_nodelay(&self, enabled: bool) -> io::Result<()> { crate::os::xous::ffi::blocking_scalar( services::net_server(), diff --git a/library/std/src/sys/net/connection/xous/udp.rs b/library/std/src/sys/net/connection/xous/udp.rs index ce54ea3b79ef8..281639488a015 100644 --- a/library/std/src/sys/net/connection/xous/udp.rs +++ b/library/std/src/sys/net/connection/xous/udp.rs @@ -145,12 +145,13 @@ impl UdpSocket { 0, ) { if receive_request.raw[0] != 0 { - // error case - if receive_request.raw[1] == NetError::TimedOut as u8 { + // Error case — code lives at byte 4 (where `send_message` + // also reads it). Byte 1 is part of the marker header. + if receive_request.raw[4] == NetError::TimedOut as u8 { return Err(io::const_error!(io::ErrorKind::TimedOut, "recv timed out")); - } else if receive_request.raw[1] == NetError::WouldBlock as u8 { + } else if receive_request.raw[4] == NetError::WouldBlock as u8 { return Err(io::const_error!(io::ErrorKind::WouldBlock, "recv would block")); - } else if receive_request.raw[1] == NetError::LibraryError as u8 { + } else if receive_request.raw[4] == NetError::LibraryError as u8 { return Err(io::const_error!(io::ErrorKind::Other, "library error")); } else { return Err(io::const_error!(io::ErrorKind::Other, "library error")); @@ -178,10 +179,12 @@ impl UdpSocket { } else { return Err(io::const_error!(io::ErrorKind::Other, "library error")); }; - for (&s, d) in rr[22..22 + rxlen as usize].iter().zip(buf.iter_mut()) { - *d = s; - } - Ok((rxlen as usize, addr)) + let max = (rxlen as usize).min(buf.len()).min(rr.len() - 22); + // Both sides must be sliced: `max` is shorter than `buf` whenever + // the datagram doesn't fill it, and `copy_from_slice` panics on a + // length mismatch. + buf[..max].copy_from_slice(&rr[22..][..max]); + Ok((max, addr)) } } else { Err(io::const_error!(io::ErrorKind::InvalidInput, "unable to recv")) @@ -240,13 +243,12 @@ impl UdpSocket { } } } - let len = buf.len() as u16; - let len_bytes = len.to_le_bytes(); + let header_len = 21; + let len = buf.len().min(tx_req.raw.len() - header_len); + let len_bytes = (len as u16).to_le_bytes(); tx_req.raw[19] = len_bytes[0]; tx_req.raw[20] = len_bytes[1]; - for (&s, d) in buf.iter().zip(tx_req.raw[21..].iter_mut()) { - *d = s; - } + tx_req.raw[header_len..header_len + len].copy_from_slice(&buf[..len]); // let buf = unsafe { // xous::MemoryRange::new( @@ -305,7 +307,7 @@ impl UdpSocket { } } else { // no error - return Ok(len as usize); + return Ok(len); } } Err(crate::os::xous::ffi::Error::ServerQueueFull) => { diff --git a/library/std/src/sys/os_str/bytes.rs b/library/std/src/sys/os_str/bytes.rs index 5482663ef0079..a57da01a5d85d 100644 --- a/library/std/src/sys/os_str/bytes.rs +++ b/library/std/src/sys/os_str/bytes.rs @@ -238,16 +238,24 @@ impl Slice { #[track_caller] #[inline] pub fn check_public_boundary(&self, index: usize) { + if self.try_check_public_boundary(index).is_none() { + panic!("byte index {index} is not an OsStr boundary"); + } + } + + #[track_caller] + #[inline] + pub fn try_check_public_boundary(&self, index: usize) -> Option<()> { if index == 0 || index == self.inner.len() { - return; + return Some(()); } if index < self.inner.len() && (self.inner[index - 1].is_ascii() || self.inner[index].is_ascii()) { - return; + return Some(()); } - slow_path(&self.inner, index); + return slow_path(&self.inner, index); /// We're betting that typical splits will involve an ASCII character. /// @@ -255,26 +263,26 @@ impl Slice { /// better assembly. #[track_caller] #[inline(never)] - fn slow_path(bytes: &[u8], index: usize) { - let (before, after) = bytes.split_at(index); + fn slow_path(bytes: &[u8], index: usize) -> Option<()> { + let (before, after) = bytes.split_at_checked(index)?; // UTF-8 takes at most 4 bytes per codepoint, so we don't // need to check more than that. let after = after.get(..4).unwrap_or(after); match str::from_utf8(after) { - Ok(_) => return, - Err(err) if err.valid_up_to() != 0 => return, + Ok(_) => return Some(()), + Err(err) if err.valid_up_to() != 0 => return Some(()), Err(_) => (), } for len in 2..=4.min(index) { let before = &before[index - len..]; if str::from_utf8(before).is_ok() { - return; + return Some(()); } } - panic!("byte index {index} is not an OsStr boundary"); + None } } diff --git a/library/std/src/sys/os_str/utf8.rs b/library/std/src/sys/os_str/utf8.rs index a324a478325e6..289f58aa480f7 100644 --- a/library/std/src/sys/os_str/utf8.rs +++ b/library/std/src/sys/os_str/utf8.rs @@ -224,10 +224,16 @@ impl Slice { Slice::from_str(unsafe { str::from_utf8_unchecked(s) }) } + #[track_caller] + #[inline] + pub fn try_check_public_boundary(&self, index: usize) -> Option<()> { + if self.inner.is_char_boundary(index) { Some(()) } else { None } + } + #[track_caller] #[inline] pub fn check_public_boundary(&self, index: usize) { - if !self.inner.is_char_boundary(index) { + if self.try_check_public_boundary(index).is_none() { panic!("byte index {index} is not an OsStr boundary"); } } diff --git a/library/std/src/sys/os_str/wtf8.rs b/library/std/src/sys/os_str/wtf8.rs index 1f130d91cf393..9a32ab3f3ea12 100644 --- a/library/std/src/sys/os_str/wtf8.rs +++ b/library/std/src/sys/os_str/wtf8.rs @@ -240,6 +240,11 @@ impl Slice { unsafe { mem::transmute(Wtf8::from_bytes_unchecked(s)) } } + #[inline] + pub fn try_check_public_boundary(&self, index: usize) -> Option<()> { + self.inner.try_check_utf8_boundary(index).ok() + } + #[track_caller] #[inline] pub fn check_public_boundary(&self, index: usize) { diff --git a/library/std/src/sys/pal/hermit/mod.rs b/library/std/src/sys/pal/hermit/mod.rs index db64f8d882e24..e8c9bf70b99df 100644 --- a/library/std/src/sys/pal/hermit/mod.rs +++ b/library/std/src/sys/pal/hermit/mod.rs @@ -1,7 +1,7 @@ -//! System bindings for HermitCore +//! System bindings for Hermit //! //! This module contains the facade (aka platform-specific) implementations of -//! OS level functionality for HermitCore. +//! OS level functionality for Hermit. //! //! This is all super highly experimental and not actually intended for //! wide/production use yet, it's still all in the experimental category. This @@ -21,8 +21,7 @@ use crate::os::hermit::hermit_abi; use crate::os::raw::c_char; use crate::sys::env; -pub mod futex; -pub mod os; +#[path = "../unix/time.rs"] pub mod time; pub fn unsupported() -> io::Result { @@ -30,7 +29,7 @@ pub fn unsupported() -> io::Result { } pub fn unsupported_err() -> io::Error { - io::const_error!(io::ErrorKind::Unsupported, "operation not supported on HermitCore yet") + io::const_error!(io::ErrorKind::Unsupported, "operation not supported on Hermit yet") } pub fn abort_internal() -> ! { diff --git a/library/std/src/sys/pal/hermit/os.rs b/library/std/src/sys/pal/hermit/os.rs deleted file mode 100644 index 48a7cdcd2f763..0000000000000 --- a/library/std/src/sys/pal/hermit/os.rs +++ /dev/null @@ -1,66 +0,0 @@ -use super::hermit_abi; -use crate::ffi::{OsStr, OsString}; -use crate::marker::PhantomData; -use crate::path::{self, PathBuf}; -use crate::sys::unsupported; -use crate::{fmt, io}; - -pub fn getcwd() -> io::Result { - Ok(PathBuf::from("/")) -} - -pub fn chdir(_: &path::Path) -> io::Result<()> { - unsupported() -} - -pub struct SplitPaths<'a>(!, PhantomData<&'a ()>); - -pub fn split_paths(_unparsed: &OsStr) -> SplitPaths<'_> { - panic!("unsupported") -} - -impl<'a> Iterator for SplitPaths<'a> { - type Item = PathBuf; - fn next(&mut self) -> Option { - self.0 - } -} - -#[derive(Debug)] -pub struct JoinPathsError; - -pub fn join_paths(_paths: I) -> Result -where - I: Iterator, - T: AsRef, -{ - Err(JoinPathsError) -} - -impl fmt::Display for JoinPathsError { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - "not supported on hermit yet".fmt(f) - } -} - -impl crate::error::Error for JoinPathsError {} - -pub fn current_exe() -> io::Result { - unsupported() -} - -pub fn temp_dir() -> PathBuf { - PathBuf::from("/tmp") -} - -pub fn home_dir() -> Option { - None -} - -pub fn exit(code: i32) -> ! { - unsafe { hermit_abi::exit(code) } -} - -pub fn getpid() -> u32 { - unsafe { hermit_abi::getpid() as u32 } -} diff --git a/library/std/src/sys/pal/hermit/time.rs b/library/std/src/sys/pal/hermit/time.rs deleted file mode 100644 index b9851eb6754d6..0000000000000 --- a/library/std/src/sys/pal/hermit/time.rs +++ /dev/null @@ -1,110 +0,0 @@ -use hermit_abi::{self, timespec}; - -use crate::cmp::Ordering; -use crate::hash::{Hash, Hasher}; -use crate::time::Duration; - -const NSEC_PER_SEC: i32 = 1_000_000_000; - -#[derive(Copy, Clone, Debug)] -pub struct Timespec { - pub t: timespec, -} - -impl Timespec { - pub const MAX: Timespec = Self::new(i64::MAX, 1_000_000_000 - 1); - - pub const MIN: Timespec = Self::new(i64::MIN, 0); - - pub const fn zero() -> Timespec { - Timespec { t: timespec { tv_sec: 0, tv_nsec: 0 } } - } - - pub const fn new(tv_sec: i64, tv_nsec: i32) -> Timespec { - assert!(tv_nsec >= 0 && tv_nsec < NSEC_PER_SEC); - // SAFETY: The assert above checks tv_nsec is within the valid range - Timespec { t: timespec { tv_sec, tv_nsec } } - } - - pub fn sub_timespec(&self, other: &Timespec) -> Result { - fn sub_ge_to_unsigned(a: i64, b: i64) -> u64 { - debug_assert!(a >= b); - a.wrapping_sub(b).cast_unsigned() - } - - if self >= other { - // Logic here is identical to Unix version of `Timestamp::sub_timespec`, - // check comments there why operations do not overflow. - Ok(if self.t.tv_nsec >= other.t.tv_nsec { - Duration::new( - sub_ge_to_unsigned(self.t.tv_sec, other.t.tv_sec), - (self.t.tv_nsec - other.t.tv_nsec) as u32, - ) - } else { - Duration::new( - sub_ge_to_unsigned(self.t.tv_sec - 1, other.t.tv_sec), - (self.t.tv_nsec + NSEC_PER_SEC - other.t.tv_nsec) as u32, - ) - }) - } else { - match other.sub_timespec(self) { - Ok(d) => Err(d), - Err(d) => Ok(d), - } - } - } - - pub fn checked_add_duration(&self, other: &Duration) -> Option { - let mut secs = self.t.tv_sec.checked_add_unsigned(other.as_secs())?; - - // Nano calculations can't overflow because nanos are <1B which fit - // in a u32. - let mut nsec = other.subsec_nanos() + u32::try_from(self.t.tv_nsec).unwrap(); - if nsec >= NSEC_PER_SEC.try_into().unwrap() { - nsec -= u32::try_from(NSEC_PER_SEC).unwrap(); - secs = secs.checked_add(1)?; - } - Some(Timespec { t: timespec { tv_sec: secs, tv_nsec: nsec as _ } }) - } - - pub fn checked_sub_duration(&self, other: &Duration) -> Option { - let mut secs = self.t.tv_sec.checked_sub_unsigned(other.as_secs())?; - - // Similar to above, nanos can't overflow. - let mut nsec = self.t.tv_nsec as i32 - other.subsec_nanos() as i32; - if nsec < 0 { - nsec += NSEC_PER_SEC as i32; - secs = secs.checked_sub(1)?; - } - Some(Timespec { t: timespec { tv_sec: secs, tv_nsec: nsec as _ } }) - } -} - -impl PartialEq for Timespec { - fn eq(&self, other: &Timespec) -> bool { - self.t.tv_sec == other.t.tv_sec && self.t.tv_nsec == other.t.tv_nsec - } -} - -impl Eq for Timespec {} - -impl PartialOrd for Timespec { - fn partial_cmp(&self, other: &Timespec) -> Option { - Some(self.cmp(other)) - } -} - -impl Ord for Timespec { - fn cmp(&self, other: &Timespec) -> Ordering { - let me = (self.t.tv_sec, self.t.tv_nsec); - let other = (other.t.tv_sec, other.t.tv_nsec); - me.cmp(&other) - } -} - -impl Hash for Timespec { - fn hash(&self, state: &mut H) { - self.t.tv_sec.hash(state); - self.t.tv_nsec.hash(state); - } -} diff --git a/library/std/src/sys/pal/motor/mod.rs b/library/std/src/sys/pal/motor/mod.rs index a520375a4bbff..5bf217db9013a 100644 --- a/library/std/src/sys/pal/motor/mod.rs +++ b/library/std/src/sys/pal/motor/mod.rs @@ -1,9 +1,5 @@ #![allow(unsafe_op_in_unsafe_fn)] -pub mod os; - -pub use moto_rt::futex; - use crate::io; pub(crate) fn map_motor_error(err: moto_rt::Error) -> io::Error { @@ -44,5 +40,5 @@ pub fn unsupported_err() -> io::Error { } pub fn abort_internal() -> ! { - core::intrinsics::abort(); + moto_rt::process::exit(-1) } diff --git a/library/std/src/sys/pal/motor/os.rs b/library/std/src/sys/pal/motor/os.rs deleted file mode 100644 index cdf66e3958dbe..0000000000000 --- a/library/std/src/sys/pal/motor/os.rs +++ /dev/null @@ -1,72 +0,0 @@ -use super::map_motor_error; -use crate::error::Error as StdError; -use crate::ffi::{OsStr, OsString}; -use crate::marker::PhantomData; -use crate::os::motor::ffi::OsStrExt; -use crate::path::{self, PathBuf}; -use crate::{fmt, io}; - -pub fn getcwd() -> io::Result { - moto_rt::fs::getcwd().map(PathBuf::from).map_err(map_motor_error) -} - -pub fn chdir(path: &path::Path) -> io::Result<()> { - moto_rt::fs::chdir(path.as_os_str().as_str()).map_err(map_motor_error) -} - -pub struct SplitPaths<'a>(!, PhantomData<&'a ()>); - -pub fn split_paths(_unparsed: &OsStr) -> SplitPaths<'_> { - panic!("unsupported") -} - -impl<'a> Iterator for SplitPaths<'a> { - type Item = PathBuf; - fn next(&mut self) -> Option { - self.0 - } -} - -#[derive(Debug)] -pub struct JoinPathsError; - -pub fn join_paths(_paths: I) -> Result -where - I: Iterator, - T: AsRef, -{ - Err(JoinPathsError) -} - -impl fmt::Display for JoinPathsError { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - "not supported on this platform yet".fmt(f) - } -} - -impl StdError for JoinPathsError { - #[allow(deprecated)] - fn description(&self) -> &str { - "not supported on this platform yet" - } -} - -pub fn current_exe() -> io::Result { - moto_rt::process::current_exe().map(PathBuf::from).map_err(map_motor_error) -} - -pub fn temp_dir() -> PathBuf { - PathBuf::from(moto_rt::fs::TEMP_DIR) -} - -pub fn home_dir() -> Option { - None -} - -pub fn exit(code: i32) -> ! { - moto_rt::process::exit(code) -} - -pub fn getpid() -> u32 { - panic!("Pids on Motor OS are u64.") -} diff --git a/library/std/src/sys/pal/sgx/abi/mod.rs b/library/std/src/sys/pal/sgx/abi/mod.rs index 1c6c681d4c179..3314f4f3b6223 100644 --- a/library/std/src/sys/pal/sgx/abi/mod.rs +++ b/library/std/src/sys/pal/sgx/abi/mod.rs @@ -96,7 +96,7 @@ extern "C" fn entry(p1: u64, p2: u64, p3: u64, secondary: bool, p4: u64, p5: u64 } } -pub(super) fn exit_with_code(code: isize) -> ! { +pub fn exit_with_code(code: isize) -> ! { if code != 0 { if let Some(mut out) = panic::SgxPanicOutput::new() { let _ = write!(out, "Exited with status code {code}"); diff --git a/library/std/src/sys/pal/sgx/abi/tls/mod.rs b/library/std/src/sys/pal/sgx/abi/tls/mod.rs index 553814dcb5fda..537b506d94506 100644 --- a/library/std/src/sys/pal/sgx/abi/tls/mod.rs +++ b/library/std/src/sys/pal/sgx/abi/tls/mod.rs @@ -1,3 +1,14 @@ +#![deny( + clippy::arithmetic_side_effects, + clippy::expect_used, + clippy::unwrap_used, + clippy::indexing_slicing, + clippy::panic, + clippy::unreachable, + clippy::unimplemented, + reason = "TLS accesses must not call the global allocator, including via panic (#160930)" +)] + mod sync_bitset; use self::sync_bitset::*; @@ -31,11 +42,11 @@ pub struct Key(NonZero); impl Key { fn to_index(self) -> usize { - self.0.get() - 1 + self.0.get().wrapping_sub(1) } fn from_index(index: usize) -> Self { - Key(NonZero::new(index + 1).unwrap()) + Key(rtunwrap!(Some, NonZero::new(index.wrapping_add(1)))) } pub fn as_usize(self) -> usize { @@ -43,7 +54,7 @@ impl Key { } pub fn from_usize(index: usize) -> Self { - Key(NonZero::new(index).unwrap()) + Key(rtunwrap!(Some, NonZero::new(index))) } } @@ -61,7 +72,7 @@ impl<'a> Drop for ActiveTls<'a> { let value_with_destructor = |key: usize| { let ptr = TLS_DESTRUCTOR[key].load(Ordering::Relaxed); unsafe { mem::transmute::<_, Option>(ptr) } - .map(|dtor| (&self.tls.data[key], dtor)) + .map(|dtor| (self.tls.data_index(key), dtor)) }; let mut any_non_null_dtor = true; @@ -94,27 +105,32 @@ impl Tls { unsafe { &*(get_tls_ptr() as *const Tls) } } + fn data_index(&self, idx: usize) -> &Cell<*mut u8> { + rtunwrap!(Some, self.data.get(idx)) + } + pub fn create(dtor: Option) -> Key { let index = if let Some(index) = TLS_KEY_IN_USE.set() { index } else { rtabort!("TLS limit exceeded") }; - TLS_DESTRUCTOR[index].store(dtor.map_or(0, |f| f as usize), Ordering::Relaxed); - unsafe { Self::current() }.data[index].set(ptr::null_mut()); + rtunwrap!(Some, TLS_DESTRUCTOR.get(index)) + .store(dtor.map_or(0, |f| f as usize), Ordering::Relaxed); + unsafe { Self::current() }.data_index(index).set(ptr::null_mut()); Key::from_index(index) } pub fn set(key: Key, value: *mut u8) { let index = key.to_index(); rtassert!(TLS_KEY_IN_USE.get(index)); - unsafe { Self::current() }.data[index].set(value); + unsafe { Self::current() }.data_index(index).set(value); } pub fn get(key: Key) -> *mut u8 { let index = key.to_index(); rtassert!(TLS_KEY_IN_USE.get(index)); - unsafe { Self::current() }.data[index].get() + unsafe { Self::current() }.data_index(index).get() } pub fn destroy(key: Key) { diff --git a/library/std/src/sys/pal/sgx/abi/tls/sync_bitset.rs b/library/std/src/sys/pal/sgx/abi/tls/sync_bitset.rs index 9087168589aa5..173d88b97cc9d 100644 --- a/library/std/src/sys/pal/sgx/abi/tls/sync_bitset.rs +++ b/library/std/src/sys/pal/sgx/abi/tls/sync_bitset.rs @@ -13,9 +13,13 @@ pub(super) const SYNC_BITSET_INIT: SyncBitset = SyncBitset([AtomicUsize::new(0), AtomicUsize::new(0)]); impl SyncBitset { + fn inner_get(&self, idx: usize) -> &Atomic { + rtunwrap!(Some, self.0.get(idx)) + } + pub fn get(&self, index: usize) -> bool { let (hi, lo) = Self::split(index); - (self.0[hi].load(Ordering::Relaxed) & lo) != 0 + (self.inner_get(hi).load(Ordering::Relaxed) & lo) != 0 } /// Not atomic. @@ -25,7 +29,7 @@ impl SyncBitset { pub fn clear(&self, index: usize) { let (hi, lo) = Self::split(index); - self.0[hi].fetch_and(!lo, Ordering::Relaxed); + self.inner_get(hi).fetch_and(!lo, Ordering::Relaxed); } /// Sets any unset bit. Not atomic. Returns `None` if all bits were @@ -44,7 +48,7 @@ impl SyncBitset { Ordering::AcqRel, Ordering::Relaxed, ) { - Ok(_) => return Some(idx * USIZE_BITS + trailing_ones), + Ok(_) => return Some(idx.wrapping_mul(USIZE_BITS).wrapping_add(trailing_ones)), Err(previous) => current = previous, } } @@ -68,17 +72,17 @@ impl<'a> Iterator for SyncBitsetIter<'a> { fn next(&mut self) -> Option { self.iter.peek().cloned().and_then(|(idx, elem)| { let elem = elem.load(Ordering::Relaxed); - let low_mask = (1 << self.elem_idx) - 1; + let low_mask = usize::wrapping_sub(1 << self.elem_idx, 1); let next = elem & !low_mask; let next_idx = next.trailing_zeros() as usize; - self.elem_idx = next_idx + 1; + self.elem_idx = next_idx.wrapping_add(1); if self.elem_idx >= 64 { self.elem_idx = 0; self.iter.next(); } match next_idx { 64 => self.next(), - _ => Some(idx * USIZE_BITS + next_idx), + _ => Some(idx.wrapping_mul(USIZE_BITS).wrapping_add(next_idx)), } }) } diff --git a/library/std/src/sys/pal/sgx/abi/usercalls/alloc.rs b/library/std/src/sys/pal/sgx/abi/usercalls/alloc.rs index aaf380d1bef47..f4115ca6124a7 100644 --- a/library/std/src/sys/pal/sgx/abi/usercalls/alloc.rs +++ b/library/std/src/sys/pal/sgx/abi/usercalls/alloc.rs @@ -8,7 +8,6 @@ use crate::cell::UnsafeCell; use crate::convert::TryInto; use crate::mem::{self, ManuallyDrop, MaybeUninit}; use crate::ops::{CoerceUnsized, Deref, DerefMut, Index, IndexMut}; -use crate::pin::PinCoerceUnsized; use crate::ptr::{self, NonNull}; use crate::slice::SliceIndex; use crate::{cmp, intrinsics, slice}; @@ -152,7 +151,7 @@ unsafe impl UserSafe for [T] { let elem_size = size_of::(); assert_eq!(size % elem_size, 0); let len = size / elem_size; - ptr::slice_from_raw_parts_mut(ptr as _, len) + ptr.cast::().cast_slice(len) } } @@ -773,9 +772,6 @@ where #[unstable(feature = "sgx_platform", issue = "56975")] impl, U> CoerceUnsized> for UserRef {} -#[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -unsafe impl PinCoerceUnsized for UserRef {} - #[unstable(feature = "sgx_platform", issue = "56975")] impl Index for UserRef<[T]> where diff --git a/library/std/src/sys/pal/sgx/abi/usercalls/mod.rs b/library/std/src/sys/pal/sgx/abi/usercalls/mod.rs index f49e940c5044c..2378028ccab92 100644 --- a/library/std/src/sys/pal/sgx/abi/usercalls/mod.rs +++ b/library/std/src/sys/pal/sgx/abi/usercalls/mod.rs @@ -39,12 +39,12 @@ pub fn read(fd: Fd, bufs: &mut [IoSliceMut<'_>]) -> io::Result { /// Usercall `read` with an uninitialized buffer. See the ABI documentation for /// more information. #[unstable(feature = "sgx_platform", issue = "56975")] -pub fn read_buf(fd: Fd, mut buf: BorrowedCursor<'_>) -> io::Result<()> { +pub fn read_buf(fd: Fd, mut buf: BorrowedCursor<'_, u8>) -> io::Result<()> { unsafe { let mut userbuf = alloc::User::<[u8]>::uninitialized(buf.capacity()); let len = raw::read(fd, userbuf.as_mut_ptr().cast(), userbuf.len()).from_sgx_result()?; userbuf[..len].copy_to_enclave(&mut buf.as_mut()[..len]); - buf.advance_unchecked(len); + buf.advance(len); Ok(()) } } diff --git a/library/std/src/sys/pal/sgx/mod.rs b/library/std/src/sys/pal/sgx/mod.rs index 1de3ca4a5d79c..6ed6e39c61897 100644 --- a/library/std/src/sys/pal/sgx/mod.rs +++ b/library/std/src/sys/pal/sgx/mod.rs @@ -3,14 +3,13 @@ //! This module contains the facade (aka platform-specific) implementations of //! OS level functionality for Fortanix SGX. #![deny(unsafe_op_in_unsafe_fn)] -#![allow(fuzzy_provenance_casts)] // FIXME: this entire module systematically confuses pointers and integers +#![allow(implicit_provenance_casts)] // FIXME: this entire module systematically confuses pointers and integers use crate::io; use crate::sync::atomic::{Atomic, AtomicBool, Ordering}; pub mod abi; mod libunwind_integration; -pub mod os; pub mod thread_parking; pub mod waitqueue; diff --git a/library/std/src/sys/pal/sgx/os.rs b/library/std/src/sys/pal/sgx/os.rs deleted file mode 100644 index ba47af7ff88d7..0000000000000 --- a/library/std/src/sys/pal/sgx/os.rs +++ /dev/null @@ -1,65 +0,0 @@ -use crate::ffi::{OsStr, OsString}; -use crate::marker::PhantomData; -use crate::path::{self, PathBuf}; -use crate::sys::{sgx_ineffective, unsupported}; -use crate::{fmt, io}; - -pub fn getcwd() -> io::Result { - unsupported() -} - -pub fn chdir(_: &path::Path) -> io::Result<()> { - sgx_ineffective(()) -} - -pub struct SplitPaths<'a>(!, PhantomData<&'a ()>); - -pub fn split_paths(_unparsed: &OsStr) -> SplitPaths<'_> { - panic!("unsupported") -} - -impl<'a> Iterator for SplitPaths<'a> { - type Item = PathBuf; - fn next(&mut self) -> Option { - self.0 - } -} - -#[derive(Debug)] -pub struct JoinPathsError; - -pub fn join_paths(_paths: I) -> Result -where - I: Iterator, - T: AsRef, -{ - Err(JoinPathsError) -} - -impl fmt::Display for JoinPathsError { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - "not supported in SGX yet".fmt(f) - } -} - -impl crate::error::Error for JoinPathsError {} - -pub fn current_exe() -> io::Result { - unsupported() -} - -pub fn temp_dir() -> PathBuf { - panic!("no filesystem in SGX") -} - -pub fn home_dir() -> Option { - None -} - -pub fn exit(code: i32) -> ! { - super::abi::exit_with_code(code as _) -} - -pub fn getpid() -> u32 { - panic!("no pids in SGX") -} diff --git a/library/std/src/sys/pal/solid/error.rs b/library/std/src/sys/pal/solid/error.rs index 3e85cdb3c1d9f..a737abcc04eda 100644 --- a/library/std/src/sys/pal/solid/error.rs +++ b/library/std/src/sys/pal/solid/error.rs @@ -3,6 +3,14 @@ use super::{abi, itron}; use crate::io; use crate::sys::net; +// SOLID directly maps `errno`s to μITRON error codes. +impl SolidError { + #[inline] + pub(crate) fn as_io_error(self) -> crate::io::Error { + crate::io::Error::from_raw_os_error(self.as_raw()) + } +} + /// Describe the specified SOLID error code. Returns `None` if it's an /// undefined error code. /// diff --git a/library/std/src/sys/pal/solid/mod.rs b/library/std/src/sys/pal/solid/mod.rs index 1376af8304cf6..c3f9e47945901 100644 --- a/library/std/src/sys/pal/solid/mod.rs +++ b/library/std/src/sys/pal/solid/mod.rs @@ -19,7 +19,6 @@ pub mod itron { // `error` is `pub(crate)` so that it can be accessed by `itron/error.rs` as // `crate::sys::error` pub(crate) mod error; -pub mod os; pub use self::itron::thread_parking; // SAFETY: must be called only once during runtime initialization. diff --git a/library/std/src/sys/pal/solid/os.rs b/library/std/src/sys/pal/solid/os.rs deleted file mode 100644 index c336a1042da40..0000000000000 --- a/library/std/src/sys/pal/solid/os.rs +++ /dev/null @@ -1,72 +0,0 @@ -use super::{itron, unsupported}; -use crate::ffi::{OsStr, OsString}; -use crate::path::{self, PathBuf}; -use crate::{fmt, io}; - -// `solid` directly maps `errno`s to μITRON error codes. -impl itron::error::ItronError { - #[inline] - pub(crate) fn as_io_error(self) -> crate::io::Error { - crate::io::Error::from_raw_os_error(self.as_raw()) - } -} - -pub fn getcwd() -> io::Result { - unsupported() -} - -pub fn chdir(_: &path::Path) -> io::Result<()> { - unsupported() -} - -pub struct SplitPaths<'a>(&'a !); - -pub fn split_paths(_unparsed: &OsStr) -> SplitPaths<'_> { - panic!("unsupported") -} - -impl<'a> Iterator for SplitPaths<'a> { - type Item = PathBuf; - fn next(&mut self) -> Option { - *self.0 - } -} - -#[derive(Debug)] -pub struct JoinPathsError; - -pub fn join_paths(_paths: I) -> Result -where - I: Iterator, - T: AsRef, -{ - Err(JoinPathsError) -} - -impl fmt::Display for JoinPathsError { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - "not supported on this platform yet".fmt(f) - } -} - -impl crate::error::Error for JoinPathsError {} - -pub fn current_exe() -> io::Result { - unsupported() -} - -pub fn temp_dir() -> PathBuf { - panic!("no standard temporary directory on this platform") -} - -pub fn home_dir() -> Option { - None -} - -pub fn exit(code: i32) -> ! { - rtabort!("exit({}) called", code); -} - -pub fn getpid() -> u32 { - panic!("no pids on this platform") -} diff --git a/library/std/src/sys/pal/teeos/conf.rs b/library/std/src/sys/pal/teeos/conf.rs new file mode 100644 index 0000000000000..1d13a283c458b --- /dev/null +++ b/library/std/src/sys/pal/teeos/conf.rs @@ -0,0 +1,5 @@ +// Hardcoded to return 4096, since `sysconf` is only implemented as a stub. +pub fn page_size() -> usize { + // unsafe { libc::sysconf(libc::_SC_PAGESIZE) as usize }; + 4096 +} diff --git a/library/std/src/sys/pal/teeos/mod.rs b/library/std/src/sys/pal/teeos/mod.rs index f76c26d3c966c..5caed277dbf59 100644 --- a/library/std/src/sys/pal/teeos/mod.rs +++ b/library/std/src/sys/pal/teeos/mod.rs @@ -6,7 +6,7 @@ #![allow(unused_variables)] #![allow(dead_code)] -pub mod os; +pub mod conf; #[path = "../unix/time.rs"] pub mod time; diff --git a/library/std/src/sys/pal/teeos/os.rs b/library/std/src/sys/pal/teeos/os.rs deleted file mode 100644 index a4b1d3c6ae670..0000000000000 --- a/library/std/src/sys/pal/teeos/os.rs +++ /dev/null @@ -1,76 +0,0 @@ -//! Implementation of `std::os` functionality for teeos - -use core::marker::PhantomData; - -use super::unsupported; -use crate::ffi::{OsStr, OsString}; -use crate::path::PathBuf; -use crate::{fmt, io, path}; - -// Hardcoded to return 4096, since `sysconf` is only implemented as a stub. -pub fn page_size() -> usize { - // unsafe { libc::sysconf(libc::_SC_PAGESIZE) as usize }; - 4096 -} - -// Everything below are stubs and copied from unsupported.rs - -pub fn getcwd() -> io::Result { - unsupported() -} - -pub fn chdir(_: &path::Path) -> io::Result<()> { - unsupported() -} - -pub struct SplitPaths<'a>(!, PhantomData<&'a ()>); - -pub fn split_paths(_unparsed: &OsStr) -> SplitPaths<'_> { - panic!("unsupported") -} - -impl<'a> Iterator for SplitPaths<'a> { - type Item = PathBuf; - fn next(&mut self) -> Option { - self.0 - } -} - -#[derive(Debug)] -pub struct JoinPathsError; - -pub fn join_paths(_paths: I) -> Result -where - I: Iterator, - T: AsRef, -{ - Err(JoinPathsError) -} - -impl fmt::Display for JoinPathsError { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - "not supported on this platform yet".fmt(f) - } -} - -impl crate::error::Error for JoinPathsError {} - -pub fn current_exe() -> io::Result { - unsupported() -} - -pub fn temp_dir() -> PathBuf { - panic!("no filesystem on this platform") -} - -pub fn home_dir() -> Option { - None -} - -pub fn exit(_code: i32) -> ! { - panic!("TA should not call `exit`") -} - -pub fn getpid() -> u32 { - panic!("no pids on this platform") -} diff --git a/library/std/src/sys/pal/trusty/mod.rs b/library/std/src/sys/pal/trusty/mod.rs index b785c2dbb7892..ec2d938ed8367 100644 --- a/library/std/src/sys/pal/trusty/mod.rs +++ b/library/std/src/sys/pal/trusty/mod.rs @@ -3,7 +3,5 @@ #[path = "../unsupported/common.rs"] #[deny(unsafe_op_in_unsafe_fn)] mod common; -#[path = "../unsupported/os.rs"] -pub mod os; pub use common::*; diff --git a/library/std/src/sys/pal/uefi/mod.rs b/library/std/src/sys/pal/uefi/mod.rs index e4a8f50e4274d..67499d2c6f17c 100644 --- a/library/std/src/sys/pal/uefi/mod.rs +++ b/library/std/src/sys/pal/uefi/mod.rs @@ -14,7 +14,6 @@ #![forbid(unsafe_op_in_unsafe_fn)] pub mod helpers; -pub mod os; pub mod system_time; #[cfg(test)] diff --git a/library/std/src/sys/pal/unix/conf.rs b/library/std/src/sys/pal/unix/conf.rs new file mode 100644 index 0000000000000..6d42e890fd45b --- /dev/null +++ b/library/std/src/sys/pal/unix/conf.rs @@ -0,0 +1,95 @@ +#[cfg(test)] +mod tests; + +#[cfg(not(target_os = "espidf"))] +pub fn page_size() -> usize { + unsafe { libc::sysconf(libc::_SC_PAGESIZE) as usize } +} + +/// Returns the value for [`confstr(key, ...)`][posix_confstr]. Currently only +/// used on Darwin, but should work on any unix (in case we need to get +/// `_CS_PATH` or `_CS_V[67]_ENV` in the future). +/// +/// [posix_confstr]: +/// https://pubs.opengroup.org/onlinepubs/9799919799/functions/confstr.html +#[cfg(target_vendor = "apple")] +pub fn confstr( + key: crate::ffi::c_int, + size_hint: Option, +) -> crate::io::Result { + use crate::ffi::OsString; + use crate::io; + use crate::os::unix::ffi::OsStringExt; + + let mut buf: Vec = Vec::with_capacity(0); + let mut bytes_needed_including_nul = size_hint + .unwrap_or_else(|| { + // Treat "None" as "do an extra call to get the length". In theory + // we could move this into the loop below, but it's hard to do given + // that it isn't 100% clear if it's legal to pass 0 for `len` when + // the buffer isn't null. + unsafe { libc::confstr(key, core::ptr::null_mut(), 0) } + }) + .max(1); + // If the value returned by `confstr` is greater than the len passed into + // it, then the value was truncated, meaning we need to retry. Note that + // while `confstr` results don't seem to change for a process, it's unclear + // if this is guaranteed anywhere, so looping does seem required. + while bytes_needed_including_nul > buf.capacity() { + // We write into the spare capacity of `buf`. This lets us avoid + // changing buf's `len`, which both simplifies `reserve` computation, + // allows working with `Vec` instead of `Vec>`, and + // may avoid a copy, since the Vec knows that none of the bytes are needed + // when reallocating (well, in theory anyway). + buf.reserve(bytes_needed_including_nul); + // `confstr` returns + // - 0 in the case of errors: we break and return an error. + // - The number of bytes written, iff the provided buffer is enough to + // hold the entire value: we break and return the data in `buf`. + // - Otherwise, the number of bytes needed (including nul): we go + // through the loop again. + bytes_needed_including_nul = + unsafe { libc::confstr(key, buf.as_mut_ptr().cast(), buf.capacity()) }; + } + // `confstr` returns 0 in the case of an error. + if bytes_needed_including_nul == 0 { + return Err(io::Error::last_os_error()); + } + // Safety: `confstr(..., buf.as_mut_ptr(), buf.capacity())` returned a + // non-zero value, meaning `bytes_needed_including_nul` bytes were + // initialized. + unsafe { + buf.set_len(bytes_needed_including_nul); + // Remove the NUL-terminator. + let last_byte = buf.pop(); + // ... and smoke-check that it *was* a NUL-terminator. + assert_eq!(last_byte, Some(0), "`confstr` provided a string which wasn't nul-terminated"); + }; + Ok(OsString::from_vec(buf)) +} + +#[cfg(all(target_os = "linux", target_env = "gnu"))] +pub fn glibc_version() -> Option<(usize, usize)> { + use crate::ffi::CStr; + + unsafe extern "C" { + fn gnu_get_libc_version() -> *const libc::c_char; + } + let version_cstr = unsafe { CStr::from_ptr(gnu_get_libc_version()) }; + if let Ok(version_str) = version_cstr.to_str() { + parse_glibc_version(version_str) + } else { + None + } +} + +/// Returns Some((major, minor)) if the string is a valid "x.y" version, +/// ignoring any extra dot-separated parts. Otherwise return None. +#[cfg(all(target_os = "linux", target_env = "gnu"))] +fn parse_glibc_version(version: &str) -> Option<(usize, usize)> { + let mut parsed_ints = version.split('.').map(str::parse::).fuse(); + match (parsed_ints.next(), parsed_ints.next()) { + (Some(Ok(major)), Some(Ok(minor))) => Some((major, minor)), + _ => None, + } +} diff --git a/library/std/src/sys/pal/unix/os/tests.rs b/library/std/src/sys/pal/unix/conf/tests.rs similarity index 96% rename from library/std/src/sys/pal/unix/os/tests.rs rename to library/std/src/sys/pal/unix/conf/tests.rs index 63a1cc1e94a1d..a84086037ce0b 100644 --- a/library/std/src/sys/pal/unix/os/tests.rs +++ b/library/std/src/sys/pal/unix/conf/tests.rs @@ -25,7 +25,7 @@ fn test_parse_glibc_version() { // Smoke check `confstr`, do it for several hint values, to ensure our resizing // logic is correct. #[test] -#[cfg(all(target_vendor = "apple", not(miri)))] +#[cfg(target_vendor = "apple")] fn test_confstr() { for key in [libc::_CS_DARWIN_USER_TEMP_DIR, libc::_CS_PATH] { let value_nohint = super::confstr(key, None).unwrap_or_else(|e| { diff --git a/library/std/src/sys/pal/unix/linux/mod.rs b/library/std/src/sys/pal/unix/linux/mod.rs deleted file mode 100644 index 88aa1e3deccf8..0000000000000 --- a/library/std/src/sys/pal/unix/linux/mod.rs +++ /dev/null @@ -1 +0,0 @@ -pub mod pidfd; diff --git a/library/std/src/sys/pal/unix/mod.rs b/library/std/src/sys/pal/unix/mod.rs index 6127bb98f80ef..e4a18794f7823 100644 --- a/library/std/src/sys/pal/unix/mod.rs +++ b/library/std/src/sys/pal/unix/mod.rs @@ -2,12 +2,9 @@ use crate::io; +pub mod conf; #[cfg(target_os = "fuchsia")] pub mod fuchsia; -pub mod futex; -#[cfg(target_os = "linux")] -pub mod linux; -pub mod os; pub mod stack_overflow; pub mod sync; pub mod thread_parking; @@ -78,7 +75,6 @@ pub unsafe fn init(argc: isize, argv: *const *const u8, sigpipe: u8) { // fast path with a single syscall for systems with poll() #[cfg(not(any( - miri, target_os = "emscripten", target_os = "fuchsia", target_os = "vxworks", @@ -87,7 +83,7 @@ pub unsafe fn init(argc: isize, argv: *const *const u8, sigpipe: u8) { target_os = "horizon", target_os = "vita", target_os = "rtems", - // The poll on Darwin doesn't set POLLNVAL for closed fds. + // The poll on Darwin doesn't set POLLNVAL for closed fds when `events == 0`. target_vendor = "apple", )))] 'poll: { @@ -125,8 +121,6 @@ pub unsafe fn init(argc: isize, argv: *const *const u8, sigpipe: u8) { // fallback in case poll isn't available or limited by RLIMIT_NOFILE #[cfg(not(any( - // The standard fds are always available in Miri. - miri, target_os = "emscripten", target_os = "fuchsia", target_os = "vxworks", @@ -151,6 +145,7 @@ pub unsafe fn init(argc: isize, argv: *const *const u8, sigpipe: u8) { target_os = "horizon", target_os = "vxworks", target_os = "vita", + target_os = "l4re", // Unikraft's `signal` implementation is currently broken: // https://github.com/unikraft/lib-musl/issues/57 target_vendor = "unikraft", @@ -169,15 +164,15 @@ pub unsafe fn init(argc: isize, argv: *const *const u8, sigpipe: u8) { pub const SIG_DFL: u8 = 3; } - let (sigpipe_attr_specified, handler) = match sigpipe { + let (on_broken_pipe_used, handler) = match sigpipe { sigpipe::DEFAULT => (false, Some(libc::SIG_IGN)), sigpipe::INHERIT => (true, None), sigpipe::SIG_IGN => (true, Some(libc::SIG_IGN)), sigpipe::SIG_DFL => (true, Some(libc::SIG_DFL)), _ => unreachable!(), }; - if sigpipe_attr_specified { - ON_BROKEN_PIPE_FLAG_USED.store(true, crate::sync::atomic::Ordering::Relaxed); + if on_broken_pipe_used { + ON_BROKEN_PIPE_USED.store(true, crate::sync::atomic::Ordering::Relaxed); } if let Some(handler) = handler { rtassert!(signal(libc::SIGPIPE, handler) != libc::SIG_ERR); @@ -199,7 +194,7 @@ pub unsafe fn init(argc: isize, argv: *const *const u8, sigpipe: u8) { target_os = "vxworks", target_os = "vita", )))] -static ON_BROKEN_PIPE_FLAG_USED: crate::sync::atomic::Atomic = +static ON_BROKEN_PIPE_USED: crate::sync::atomic::Atomic = crate::sync::atomic::AtomicBool::new(false); #[cfg(not(any( @@ -211,15 +206,15 @@ static ON_BROKEN_PIPE_FLAG_USED: crate::sync::atomic::Atomic = target_os = "vita", target_os = "nuttx", )))] -pub(crate) fn on_broken_pipe_flag_used() -> bool { - ON_BROKEN_PIPE_FLAG_USED.load(crate::sync::atomic::Ordering::Relaxed) +pub(crate) fn on_broken_pipe_used() -> bool { + ON_BROKEN_PIPE_USED.load(crate::sync::atomic::Ordering::Relaxed) } // SAFETY: must be called only once during runtime cleanup. -// NOTE: this is not guaranteed to run, for example when the program aborts. -pub unsafe fn cleanup() { - stack_overflow::cleanup(); -} +// NOTE: this is not guaranteed to run, for example when the program aborts, and +// is not guaranteed to run on the main thread (#161018 was caused by that +// mistaken assumption). +pub unsafe fn cleanup() {} #[allow(unused_imports)] pub use libc::signal; @@ -307,8 +302,12 @@ pub fn abort_internal() -> ! { cfg_select! { target_os = "android" => { - #[link(name = "dl", kind = "static", modifiers = "-bundle", - cfg(target_feature = "crt-static"))] + #[link( + name = "dl", + kind = "static", + modifiers = "-bundle", + cfg(target_feature = "crt-static") + )] #[link(name = "dl", cfg(not(target_feature = "crt-static")))] #[link(name = "log", cfg(not(target_feature = "crt-static")))] unsafe extern "C" {} @@ -369,15 +368,24 @@ cfg_select! { _ => {} } -#[cfg(any(target_os = "espidf", target_os = "horizon", target_os = "vita", target_os = "nuttx"))] -pub mod unsupported { - use crate::io; - - pub fn unsupported() -> io::Result { - Err(unsupported_err()) - } +#[cfg(any( + target_os = "espidf", + target_os = "horizon", + target_os = "vita", + target_os = "nuttx", + target_os = "l4re", +))] +pub fn unsupported() -> crate::io::Result { + Err(unsupported_err()) +} - pub fn unsupported_err() -> io::Error { - io::Error::UNSUPPORTED_PLATFORM - } +#[cfg(any( + target_os = "espidf", + target_os = "horizon", + target_os = "vita", + target_os = "nuttx", + target_os = "l4re", +))] +pub fn unsupported_err() -> crate::io::Error { + io::Error::UNSUPPORTED_PLATFORM } diff --git a/library/std/src/sys/pal/unix/stack_overflow.rs b/library/std/src/sys/pal/unix/stack_overflow.rs index 040fda75a5080..d6d03e0d1d877 100644 --- a/library/std/src/sys/pal/unix/stack_overflow.rs +++ b/library/std/src/sys/pal/unix/stack_overflow.rs @@ -1,6 +1,6 @@ #![cfg_attr(test, allow(dead_code))] -pub use self::imp::{cleanup, init}; +pub use self::imp::init; use self::imp::{drop_handler, make_handler}; pub struct Handler { @@ -70,7 +70,7 @@ mod imp { use super::thread_info::{delete_current_info, set_current_info, with_current_info}; use crate::ops::Range; use crate::sync::atomic::{Atomic, AtomicBool, AtomicPtr, AtomicUsize, Ordering}; - use crate::sys::pal::unix::os; + use crate::sys::pal::unix::conf; use crate::{io, mem, ptr}; // Signal handler for the SIGSEGV and SIGBUS handlers. We've got guard pages @@ -143,6 +143,12 @@ mod imp { } static PAGE_SIZE: Atomic = AtomicUsize::new(0); + // Store a pointer to the allocation for the main thread's altstack so that + // tools like valgrind don't complain about a leaked unreachable allocation. + // + // If the main thread exits, the process will terminate so there's no use in + // freeing resources. It also means that the altstack is still installed + // while TLS destructors are run on the main thread (c.f. #111272). static MAIN_ALTSTACK: Atomic<*mut libc::c_void> = AtomicPtr::new(ptr::null_mut()); static NEED_ALTSTACK: Atomic = AtomicBool::new(false); @@ -150,7 +156,7 @@ mod imp { /// Must be called only once #[forbid(unsafe_op_in_unsafe_fn)] pub unsafe fn init() { - PAGE_SIZE.store(os::page_size(), Ordering::Relaxed); + PAGE_SIZE.store(conf::page_size(), Ordering::Relaxed); let mut guard_page_range = unsafe { install_main_guard() }; @@ -190,18 +196,6 @@ mod imp { } } - /// # Safety - /// Must be called only once - #[forbid(unsafe_op_in_unsafe_fn)] - pub unsafe fn cleanup() { - if cfg!(panic = "immediate-abort") { - return; - } - // FIXME: I probably cause more bugs than I'm worth! - // see https://github.com/rust-lang/rust/issues/111272 - unsafe { drop_handler(MAIN_ALTSTACK.load(Ordering::Relaxed)) }; - } - unsafe fn get_stack() -> libc::stack_t { // OpenBSD requires this flag for stack mapping // otherwise the said mapping will fail as a no-op on most systems @@ -305,7 +299,7 @@ mod imp { } /// Modern kernels on modern hardware can have dynamic signal stack sizes. - #[cfg(any(target_os = "linux", target_os = "android"))] + #[cfg(all(any(target_os = "linux", target_os = "android"), not(target_env = "uclibc")))] fn sigstack_size() -> usize { let dynamic_sigstksz = unsafe { libc::getauxval(libc::AT_MINSIGSTKSZ) }; // If getauxval couldn't find the entry, it returns 0, @@ -315,7 +309,7 @@ mod imp { } /// Not all OS support hardware where this is needed. - #[cfg(not(any(target_os = "linux", target_os = "android")))] + #[cfg(not(all(any(target_os = "linux", target_os = "android"), not(target_env = "uclibc"))))] fn sigstack_size() -> usize { libc::SIGSTKSZ } @@ -429,6 +423,11 @@ mod imp { #[forbid(unsafe_op_in_unsafe_fn)] unsafe fn install_main_guard_linux(page_size: usize) -> Option> { + // See the corresponding conditional in init(). + // Avoid stack_start_aligned, which makes slow syscalls to read /proc/self/maps + if cfg!(panic = "immediate-abort") { + return None; + } // Linux doesn't allocate the whole stack right away, and // the kernel has its own stack-guard mechanism to fault // when growing too close to an existing mapping. If we map @@ -456,6 +455,10 @@ mod imp { #[forbid(unsafe_op_in_unsafe_fn)] #[cfg(target_os = "freebsd")] unsafe fn install_main_guard_freebsd(page_size: usize) -> Option> { + // See the corresponding conditional in install_main_guard_linux(). + if cfg!(panic = "immediate-abort") { + return None; + } // FreeBSD's stack autogrows, and optionally includes a guard page // at the bottom. If we try to remap the bottom of the stack // ourselves, FreeBSD's guard page moves upwards. So we'll just use @@ -489,6 +492,10 @@ mod imp { #[forbid(unsafe_op_in_unsafe_fn)] unsafe fn install_main_guard_bsds(page_size: usize) -> Option> { + // See the corresponding conditional in install_main_guard_linux(). + if cfg!(panic = "immediate-abort") { + return None; + } // OpenBSD stack already includes a guard page, and stack is // immutable. // NetBSD stack includes the guard page. @@ -638,8 +645,6 @@ mod imp { mod imp { pub unsafe fn init() {} - pub unsafe fn cleanup() {} - pub unsafe fn make_handler(_main_thread: bool) -> super::Handler { super::Handler::null() } @@ -722,8 +727,6 @@ mod imp { reserve_stack(); } - pub unsafe fn cleanup() {} - pub unsafe fn make_handler(main_thread: bool) -> super::Handler { if !main_thread { reserve_stack(); diff --git a/library/std/src/sys/pal/unix/sync/condvar.rs b/library/std/src/sys/pal/unix/sync/condvar.rs index 73768860723d0..51162296ea3fc 100644 --- a/library/std/src/sys/pal/unix/sync/condvar.rs +++ b/library/std/src/sys/pal/unix/sync/condvar.rs @@ -1,9 +1,9 @@ use super::Mutex; use crate::cell::UnsafeCell; use crate::pin::Pin; -#[cfg(not(target_os = "nto"))] +#[cfg(not(any(target_os = "nto", target_os = "qnx")))] use crate::sys::pal::time::TIMESPEC_MAX; -#[cfg(target_os = "nto")] +#[cfg(any(target_os = "nto", target_os = "qnx"))] use crate::sys::pal::time::TIMESPEC_MAX_CAPPED; use crate::time::Duration; @@ -69,10 +69,10 @@ impl Condvar { let timeout = Timespec::now(Self::CLOCK).checked_add_duration(&dur); - #[cfg(not(target_os = "nto"))] + #[cfg(not(any(target_os = "nto", target_os = "qnx")))] let timeout = timeout.and_then(|t| t.to_timespec()).unwrap_or(TIMESPEC_MAX); - #[cfg(target_os = "nto")] + #[cfg(any(target_os = "nto", target_os = "qnx"))] let timeout = timeout.and_then(|t| t.to_timespec_capped()).unwrap_or(TIMESPEC_MAX_CAPPED); let r = unsafe { libc::pthread_cond_timedwait(self.raw(), mutex, &timeout) }; diff --git a/library/std/src/sys/pal/unix/sync/mutex.rs b/library/std/src/sys/pal/unix/sync/mutex.rs index 557e70af94ba7..145bfb1e22413 100644 --- a/library/std/src/sys/pal/unix/sync/mutex.rs +++ b/library/std/src/sys/pal/unix/sync/mutex.rs @@ -25,7 +25,7 @@ impl Mutex { // A pthread mutex initialized with PTHREAD_MUTEX_INITIALIZER will have // a type of PTHREAD_MUTEX_DEFAULT, which has undefined behavior if you // try to re-lock it from the same thread when you already hold a lock - // (https://pubs.opengroup.org/onlinepubs/9699919799/functions/pthread_mutex_init.html). + // (https://pubs.opengroup.org/onlinepubs/9799919799/functions/pthread_mutex_init.html). // This is the case even if PTHREAD_MUTEX_DEFAULT == PTHREAD_MUTEX_NORMAL // (https://github.com/rust-lang/rust/issues/33770#issuecomment-220847521) -- in that // case, `pthread_mutexattr_settype(PTHREAD_MUTEX_DEFAULT)` will of course be the same diff --git a/library/std/src/sys/pal/unix/time.rs b/library/std/src/sys/pal/unix/time.rs index fbea94ec84e79..9c4ba9f5f388a 100644 --- a/library/std/src/sys/pal/unix/time.rs +++ b/library/std/src/sys/pal/unix/time.rs @@ -1,3 +1,4 @@ +use core::mem; use core::num::niche_types::Nanoseconds; use crate::io; @@ -6,18 +7,22 @@ use crate::time::Duration; const NSEC_PER_SEC: u64 = 1_000_000_000; #[allow(dead_code)] // Used for pthread condvar timeouts -pub const TIMESPEC_MAX: libc::timespec = - libc::timespec { tv_sec: ::MAX, tv_nsec: 1_000_000_000 - 1 }; +pub const TIMESPEC_MAX: libc::timespec = { + let mut ts = unsafe { mem::zeroed::() }; + ts.tv_sec = ::MAX; + ts.tv_nsec = 1_000_000_000 - 1; + ts +}; // This additional constant is only used when calling // `libc::pthread_cond_timedwait`. -#[cfg(target_os = "nto")] +#[cfg(any(target_os = "nto", target_os = "qnx"))] pub(in crate::sys) const TIMESPEC_MAX_CAPPED: libc::timespec = libc::timespec { tv_sec: (u64::MAX / NSEC_PER_SEC) as i64, tv_nsec: (u64::MAX % NSEC_PER_SEC) as i64, }; -#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)] +#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug, Hash)] pub(crate) struct Timespec { pub tv_sec: i64, pub tv_nsec: Nanoseconds, @@ -66,6 +71,7 @@ impl Timespec { } } + #[allow(dead_code)] pub fn now(clock: libc::clockid_t) -> Timespec { use crate::mem::MaybeUninit; use crate::sys::cvt; @@ -163,15 +169,17 @@ impl Timespec { #[allow(dead_code)] pub fn to_timespec(&self) -> Option { - Some(libc::timespec { - tv_sec: self.tv_sec.try_into().ok()?, - tv_nsec: self.tv_nsec.as_inner().try_into().ok()?, + Some({ + let mut ts = libc::timespec::default(); + ts.tv_sec = self.tv_sec.try_into().ok()?; + ts.tv_nsec = self.tv_nsec.as_inner().try_into().ok()?; + ts }) } - // On QNX Neutrino, the maximum timespec for e.g. pthread_cond_timedwait + // On QNX, the maximum timespec for e.g. pthread_cond_timedwait // is 2^64 nanoseconds - #[cfg(target_os = "nto")] + #[cfg(any(target_os = "nto", target_os = "qnx"))] pub(in crate::sys) fn to_timespec_capped(&self) -> Option { // Check if timeout in nanoseconds would fit into an u64 if (self.tv_nsec.as_inner() as u64) diff --git a/library/std/src/sys/pal/unix/weak/dlsym.rs b/library/std/src/sys/pal/unix/weak/dlsym.rs index 4967b93cc52b5..170e356dbc72f 100644 --- a/library/std/src/sys/pal/unix/weak/dlsym.rs +++ b/library/std/src/sys/pal/unix/weak/dlsym.rs @@ -1,5 +1,6 @@ use crate::ffi::{CStr, c_char, c_void}; -use crate::marker::{FnPtr, PhantomData}; +use crate::marker::PhantomData; +use crate::ops::FnPtr; use crate::sync::atomic::{Atomic, AtomicPtr, Ordering}; use crate::{mem, ptr}; diff --git a/library/std/src/sys/pal/unsupported/mod.rs b/library/std/src/sys/pal/unsupported/mod.rs index 0f157819d5a66..c4b14ab44436f 100644 --- a/library/std/src/sys/pal/unsupported/mod.rs +++ b/library/std/src/sys/pal/unsupported/mod.rs @@ -1,6 +1,4 @@ #![deny(unsafe_op_in_unsafe_fn)] -pub mod os; - mod common; pub use common::*; diff --git a/library/std/src/sys/pal/unsupported/os.rs b/library/std/src/sys/pal/unsupported/os.rs deleted file mode 100644 index cb925ef4348db..0000000000000 --- a/library/std/src/sys/pal/unsupported/os.rs +++ /dev/null @@ -1,65 +0,0 @@ -use super::unsupported; -use crate::ffi::{OsStr, OsString}; -use crate::marker::PhantomData; -use crate::path::{self, PathBuf}; -use crate::{fmt, io}; - -pub fn getcwd() -> io::Result { - unsupported() -} - -pub fn chdir(_: &path::Path) -> io::Result<()> { - unsupported() -} - -pub struct SplitPaths<'a>(!, PhantomData<&'a ()>); - -pub fn split_paths(_unparsed: &OsStr) -> SplitPaths<'_> { - panic!("unsupported") -} - -impl<'a> Iterator for SplitPaths<'a> { - type Item = PathBuf; - fn next(&mut self) -> Option { - self.0 - } -} - -#[derive(Debug)] -pub struct JoinPathsError; - -pub fn join_paths(_paths: I) -> Result -where - I: Iterator, - T: AsRef, -{ - Err(JoinPathsError) -} - -impl fmt::Display for JoinPathsError { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - "not supported on this platform yet".fmt(f) - } -} - -impl crate::error::Error for JoinPathsError {} - -pub fn current_exe() -> io::Result { - unsupported() -} - -pub fn temp_dir() -> PathBuf { - panic!("no filesystem on this platform") -} - -pub fn home_dir() -> Option { - None -} - -pub fn exit(_code: i32) -> ! { - crate::intrinsics::abort() -} - -pub fn getpid() -> u32 { - panic!("no pids on this platform") -} diff --git a/library/std/src/sys/pal/vexos/mod.rs b/library/std/src/sys/pal/vexos/mod.rs index 16aa3f088f04b..540da6cbc950f 100644 --- a/library/std/src/sys/pal/vexos/mod.rs +++ b/library/std/src/sys/pal/vexos/mod.rs @@ -1,5 +1,3 @@ -pub mod os; - #[expect(dead_code)] #[path = "../unsupported/common.rs"] mod unsupported_common; @@ -16,9 +14,10 @@ global_asm!( .section .boot, "ax" .global _boot + .arm _boot: ldr sp, =__stack_top @ Set up the user stack. - b _start @ Jump to the Rust entrypoint. + blx _start @ Jump to the Rust entrypoint. "# ); diff --git a/library/std/src/sys/pal/vexos/os.rs b/library/std/src/sys/pal/vexos/os.rs deleted file mode 100644 index 303b452a078ff..0000000000000 --- a/library/std/src/sys/pal/vexos/os.rs +++ /dev/null @@ -1,19 +0,0 @@ -#[expect(dead_code)] -#[path = "../unsupported/os.rs"] -mod unsupported_os; -pub use unsupported_os::{ - JoinPathsError, SplitPaths, chdir, current_exe, getcwd, getpid, home_dir, join_paths, - split_paths, temp_dir, -}; - -pub use super::unsupported; - -pub fn exit(_code: i32) -> ! { - unsafe { - vex_sdk::vexSystemExitRequest(); - - loop { - vex_sdk::vexTasksRun(); - } - } -} diff --git a/library/std/src/sys/pal/wasi/conf.rs b/library/std/src/sys/pal/wasi/conf.rs new file mode 100644 index 0000000000000..cf76ae733358e --- /dev/null +++ b/library/std/src/sys/pal/wasi/conf.rs @@ -0,0 +1,4 @@ +#[allow(dead_code)] +pub fn page_size() -> usize { + unsafe { libc::sysconf(libc::_SC_PAGESIZE) as usize } +} diff --git a/library/std/src/sys/pal/wasi/helpers.rs b/library/std/src/sys/pal/wasi/helpers.rs deleted file mode 100644 index 4f2eb1148f0b3..0000000000000 --- a/library/std/src/sys/pal/wasi/helpers.rs +++ /dev/null @@ -1,11 +0,0 @@ -#![forbid(unsafe_op_in_unsafe_fn)] - -pub fn abort_internal() -> ! { - unsafe { libc::abort() } -} - -#[inline] -#[cfg(target_env = "p1")] -pub(crate) fn err2io(err: wasi::Errno) -> crate::io::Error { - crate::io::Error::from_raw_os_error(err.raw().into()) -} diff --git a/library/std/src/sys/pal/wasi/mod.rs b/library/std/src/sys/pal/wasi/mod.rs index 9b49db9af6b05..056f632ae0be2 100644 --- a/library/std/src/sys/pal/wasi/mod.rs +++ b/library/std/src/sys/pal/wasi/mod.rs @@ -4,34 +4,60 @@ //! OS level functionality for WASI. Currently this includes both WASIp1 and //! WASIp2. -#[allow(unused)] -#[path = "../wasm/atomics/futex.rs"] -pub mod futex; +use crate::io; -pub mod os; +pub mod conf; pub mod stack_overflow; #[path = "../unix/time.rs"] pub mod time; +#[cfg(not(target_env = "p1"))] +mod cabi_realloc; + #[path = "../unsupported/common.rs"] #[deny(unsafe_op_in_unsafe_fn)] -#[allow(unused)] +#[expect(dead_code)] mod common; +pub use common::{cleanup, init, unsupported}; -pub use common::*; - -mod helpers; - -// The following exports are listed individually to work around Rust's glob -// import conflict rules. If we glob export `helpers` and `common` together, -// then the compiler complains about conflicts. +pub fn abort_internal() -> ! { + unsafe { libc::abort() } +} -pub(crate) use helpers::abort_internal; +#[inline] #[cfg(target_env = "p1")] -pub(crate) use helpers::err2io; -#[cfg(not(target_env = "p1"))] -pub use os::IsMinusOne; -pub use os::{cvt, cvt_r}; - -#[cfg(not(target_env = "p1"))] -mod cabi_realloc; +pub(crate) fn err2io(err: wasip1::Errno) -> crate::io::Error { + crate::io::Error::from_raw_os_error(err.raw().into()) +} + +#[doc(hidden)] +pub trait IsMinusOne { + fn is_minus_one(&self) -> bool; +} + +macro_rules! impl_is_minus_one { + ($($t:ident)*) => ($(impl IsMinusOne for $t { + fn is_minus_one(&self) -> bool { + *self == -1 + } + })*) +} + +impl_is_minus_one! { i8 i16 i32 i64 isize } + +pub fn cvt(t: T) -> io::Result { + if t.is_minus_one() { Err(io::Error::last_os_error()) } else { Ok(t) } +} + +pub fn cvt_r(mut f: F) -> io::Result +where + T: IsMinusOne, + F: FnMut() -> T, +{ + loop { + match cvt(f()) { + Err(ref e) if e.is_interrupted() => {} + other => return other, + } + } +} diff --git a/library/std/src/sys/pal/wasi/os.rs b/library/std/src/sys/pal/wasi/os.rs deleted file mode 100644 index 285be3ca9fda4..0000000000000 --- a/library/std/src/sys/pal/wasi/os.rs +++ /dev/null @@ -1,143 +0,0 @@ -#![forbid(unsafe_op_in_unsafe_fn)] - -use crate::ffi::{CStr, OsStr, OsString}; -use crate::marker::PhantomData; -use crate::os::wasi::prelude::*; -use crate::path::{self, PathBuf}; -use crate::sys::helpers::run_path_with_cstr; -use crate::sys::unsupported; -use crate::{fmt, io}; - -// Add a few symbols not in upstream `libc` just yet. -pub mod libc { - pub use libc::*; - - unsafe extern "C" { - pub fn getcwd(buf: *mut c_char, size: size_t) -> *mut c_char; - pub fn chdir(dir: *const c_char) -> c_int; - pub fn __wasilibc_get_environ() -> *mut *mut c_char; - } -} - -pub fn getcwd() -> io::Result { - let mut buf = Vec::with_capacity(512); - loop { - unsafe { - let ptr = buf.as_mut_ptr() as *mut libc::c_char; - if !libc::getcwd(ptr, buf.capacity()).is_null() { - let len = CStr::from_ptr(buf.as_ptr() as *const libc::c_char).to_bytes().len(); - buf.set_len(len); - buf.shrink_to_fit(); - return Ok(PathBuf::from(OsString::from_vec(buf))); - } else { - let error = io::Error::last_os_error(); - if error.raw_os_error() != Some(libc::ERANGE) { - return Err(error); - } - } - - // Trigger the internal buffer resizing logic of `Vec` by requiring - // more space than the current capacity. - let cap = buf.capacity(); - buf.set_len(cap); - buf.reserve(1); - } - } -} - -pub fn chdir(p: &path::Path) -> io::Result<()> { - let result = run_path_with_cstr(p, &|p| unsafe { Ok(libc::chdir(p.as_ptr())) })?; - match result == (0 as libc::c_int) { - true => Ok(()), - false => Err(io::Error::last_os_error()), - } -} - -pub struct SplitPaths<'a>(!, PhantomData<&'a ()>); - -pub fn split_paths(_unparsed: &OsStr) -> SplitPaths<'_> { - panic!("unsupported") -} - -impl<'a> Iterator for SplitPaths<'a> { - type Item = PathBuf; - fn next(&mut self) -> Option { - self.0 - } -} - -#[derive(Debug)] -pub struct JoinPathsError; - -pub fn join_paths(_paths: I) -> Result -where - I: Iterator, - T: AsRef, -{ - Err(JoinPathsError) -} - -impl fmt::Display for JoinPathsError { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - "not supported on wasm yet".fmt(f) - } -} - -impl crate::error::Error for JoinPathsError {} - -pub fn current_exe() -> io::Result { - unsupported() -} - -#[allow(dead_code)] -pub fn page_size() -> usize { - unsafe { libc::sysconf(libc::_SC_PAGESIZE) as usize } -} - -pub fn temp_dir() -> PathBuf { - panic!("no filesystem on wasm") -} - -pub fn home_dir() -> Option { - None -} - -pub fn exit(code: i32) -> ! { - unsafe { libc::exit(code) } -} - -pub fn getpid() -> u32 { - panic!("unsupported"); -} - -#[doc(hidden)] -pub trait IsMinusOne { - fn is_minus_one(&self) -> bool; -} - -macro_rules! impl_is_minus_one { - ($($t:ident)*) => ($(impl IsMinusOne for $t { - fn is_minus_one(&self) -> bool { - *self == -1 - } - })*) -} - -impl_is_minus_one! { i8 i16 i32 i64 isize } - -pub fn cvt(t: T) -> io::Result { - if t.is_minus_one() { Err(io::Error::last_os_error()) } else { Ok(t) } -} - -pub fn cvt_r(mut f: F) -> io::Result -where - T: IsMinusOne, - F: FnMut() -> T, -{ - loop { - match cvt(f()) { - Err(ref e) if e.is_interrupted() => {} - other => return other, - } - } -} diff --git a/library/std/src/sys/pal/wasm/mod.rs b/library/std/src/sys/pal/wasm/mod.rs index 5f56eddd6a819..72e5982fc0732 100644 --- a/library/std/src/sys/pal/wasm/mod.rs +++ b/library/std/src/sys/pal/wasm/mod.rs @@ -16,13 +16,6 @@ #![deny(unsafe_op_in_unsafe_fn)] -#[path = "../unsupported/os.rs"] -pub mod os; - -#[cfg(target_feature = "atomics")] -#[path = "atomics/futex.rs"] -pub mod futex; - #[path = "../unsupported/common.rs"] #[deny(unsafe_op_in_unsafe_fn)] mod common; diff --git a/library/std/src/sys/pal/windows/c.rs b/library/std/src/sys/pal/windows/c.rs index 9f1a51c7dd3f6..c2ddb4931365a 100644 --- a/library/std/src/sys/pal/windows/c.rs +++ b/library/std/src/sys/pal/windows/c.rs @@ -5,7 +5,7 @@ #![unstable(issue = "none", feature = "windows_c")] #![allow(clippy::style)] -use core::ffi::{CStr, c_uint, c_ulong, c_ushort, c_void}; +use core::ffi::{CStr, c_int, c_uint, c_ulong, c_ushort, c_void}; use core::ptr; mod windows_sys; @@ -241,3 +241,7 @@ cfg_select! { // Only available starting with Windows 8. #[cfg(not(target_vendor = "win7"))] windows_link::link!("ws2_32.dll" "system" fn GetHostNameW(name : PWSTR, namelen : i32) -> i32); + +unsafe extern "C" { + pub fn atexit(cb: unsafe extern "C" fn()) -> c_int; +} diff --git a/library/std/src/sys/pal/windows/c/bindings.txt b/library/std/src/sys/pal/windows/c/bindings.txt index c21d1de81341f..a0b2126af9a58 100644 --- a/library/std/src/sys/pal/windows/c/bindings.txt +++ b/library/std/src/sys/pal/windows/c/bindings.txt @@ -2075,6 +2075,7 @@ FILE_READ_EA FILE_RENAME_FLAG_POSIX_SEMANTICS FILE_RENAME_FLAG_REPLACE_IF_EXISTS FILE_RENAME_INFO +FILE_RENAME_INFORMATION FILE_RESERVE_OPFILTER FILE_SEQUENTIAL_ONLY FILE_SESSION_AWARE @@ -2120,6 +2121,8 @@ FileNormalizedNameInfo FileRemoteProtocolInfo FileRenameInfo FileRenameInfoEx +FileRenameInformation +FileRenameInformationEx FileStandardInfo FileStorageInfo FileStreamInfo @@ -2130,6 +2133,11 @@ FindExSearchNameMatch FindFirstFileExW FindNextFileW FIONBIO +FLS_OUT_OF_INDEXES +FlsAlloc +FlsFree +FlsGetValue +FlsSetValue FlushFileBuffers FORMAT_MESSAGE_ALLOCATE_BUFFER FORMAT_MESSAGE_ARGUMENT_ARRAY @@ -2149,6 +2157,8 @@ GENERIC_ALL GENERIC_EXECUTE GENERIC_READ GENERIC_WRITE +GET_MODULE_HANDLE_EX_FLAG_FROM_ADDRESS +GET_MODULE_HANDLE_EX_FLAG_UNCHANGED_REFCOUNT GetActiveProcessorCount getaddrinfo GetCommandLineW @@ -2173,6 +2183,7 @@ GetFullPathNameW GetLastError GetModuleFileNameW GetModuleHandleA +GetModuleHandleExW GetModuleHandleW GetOverlappedResult getpeername @@ -2258,6 +2269,7 @@ IPV6_DROP_MEMBERSHIP IPV6_MREQ IPV6_MULTICAST_LOOP IPV6_V6ONLY +IsThreadAFiber LINGER listen LocalFree @@ -2302,6 +2314,7 @@ NTCREATEFILE_CREATE_DISPOSITION NTCREATEFILE_CREATE_OPTIONS NtOpenFile NtReadFile +NtSetInformationFile NTSTATUS NtWriteFile OBJ_CASE_INSENSITIVE @@ -2318,6 +2331,7 @@ OPEN_ALWAYS OPEN_EXISTING OpenProcessToken OVERLAPPED +PFLS_CALLBACK_FUNCTION PIPE_ACCEPT_REMOTE_CLIENTS PIPE_ACCESS_DUPLEX PIPE_ACCESS_INBOUND @@ -2380,6 +2394,7 @@ SetFileTime SetHandleInformation SetLastError setsockopt +SetStdHandle SetThreadStackGuarantee SetWaitableTimer shutdown @@ -2388,6 +2403,7 @@ SleepConditionVariableSRW SleepEx SO_BROADCAST SO_ERROR +SO_KEEPALIVE SO_LINGER SO_RCVTIMEO SO_SNDTIMEO diff --git a/library/std/src/sys/pal/windows/c/windows_sys.rs b/library/std/src/sys/pal/windows/c/windows_sys.rs index eb54efd1c1fe0..9c6f593e1e108 100644 --- a/library/std/src/sys/pal/windows/c/windows_sys.rs +++ b/library/std/src/sys/pal/windows/c/windows_sys.rs @@ -27,6 +27,10 @@ windows_link::link!("kernel32.dll" "system" fn ExitProcess(uexitcode : u32) -> ! windows_link::link!("kernel32.dll" "system" fn FindClose(hfindfile : HANDLE) -> BOOL); windows_link::link!("kernel32.dll" "system" fn FindFirstFileExW(lpfilename : PCWSTR, finfolevelid : FINDEX_INFO_LEVELS, lpfindfiledata : *mut core::ffi::c_void, fsearchop : FINDEX_SEARCH_OPS, lpsearchfilter : *const core::ffi::c_void, dwadditionalflags : FIND_FIRST_EX_FLAGS) -> HANDLE); windows_link::link!("kernel32.dll" "system" fn FindNextFileW(hfindfile : HANDLE, lpfindfiledata : *mut WIN32_FIND_DATAW) -> BOOL); +windows_link::link!("kernel32.dll" "system" fn FlsAlloc(lpcallback : PFLS_CALLBACK_FUNCTION) -> u32); +windows_link::link!("kernel32.dll" "system" fn FlsFree(dwflsindex : u32) -> BOOL); +windows_link::link!("kernel32.dll" "system" fn FlsGetValue(dwflsindex : u32) -> *mut core::ffi::c_void); +windows_link::link!("kernel32.dll" "system" fn FlsSetValue(dwflsindex : u32, lpflsdata : *const core::ffi::c_void) -> BOOL); windows_link::link!("kernel32.dll" "system" fn FlushFileBuffers(hfile : HANDLE) -> BOOL); windows_link::link!("kernel32.dll" "system" fn FormatMessageW(dwflags : FORMAT_MESSAGE_OPTIONS, lpsource : *const core::ffi::c_void, dwmessageid : u32, dwlanguageid : u32, lpbuffer : PWSTR, nsize : u32, arguments : *const *const i8) -> u32); windows_link::link!("kernel32.dll" "system" fn FreeEnvironmentStringsW(penv : PCWSTR) -> BOOL); @@ -52,6 +56,7 @@ windows_link::link!("kernel32.dll" "system" fn GetFullPathNameW(lpfilename : PCW windows_link::link!("kernel32.dll" "system" fn GetLastError() -> WIN32_ERROR); windows_link::link!("kernel32.dll" "system" fn GetModuleFileNameW(hmodule : HMODULE, lpfilename : PWSTR, nsize : u32) -> u32); windows_link::link!("kernel32.dll" "system" fn GetModuleHandleA(lpmodulename : PCSTR) -> HMODULE); +windows_link::link!("kernel32.dll" "system" fn GetModuleHandleExW(dwflags : u32, lpmodulename : PCWSTR, phmodule : *mut HMODULE) -> BOOL); windows_link::link!("kernel32.dll" "system" fn GetModuleHandleW(lpmodulename : PCWSTR) -> HMODULE); windows_link::link!("kernel32.dll" "system" fn GetOverlappedResult(hfile : HANDLE, lpoverlapped : *const OVERLAPPED, lpnumberofbytestransferred : *mut u32, bwait : BOOL) -> BOOL); windows_link::link!("kernel32.dll" "system" fn GetProcAddress(hmodule : HMODULE, lpprocname : PCSTR) -> FARPROC); @@ -67,6 +72,7 @@ windows_link::link!("kernel32.dll" "system" fn GetWindowsDirectoryW(lpbuffer : P windows_link::link!("kernel32.dll" "system" fn InitOnceBeginInitialize(lpinitonce : *mut INIT_ONCE, dwflags : u32, fpending : *mut BOOL, lpcontext : *mut *mut core::ffi::c_void) -> BOOL); windows_link::link!("kernel32.dll" "system" fn InitOnceComplete(lpinitonce : *mut INIT_ONCE, dwflags : u32, lpcontext : *const core::ffi::c_void) -> BOOL); windows_link::link!("kernel32.dll" "system" fn InitializeProcThreadAttributeList(lpattributelist : LPPROC_THREAD_ATTRIBUTE_LIST, dwattributecount : u32, dwflags : u32, lpsize : *mut usize) -> BOOL); +windows_link::link!("kernel32.dll" "system" fn IsThreadAFiber() -> BOOL); windows_link::link!("kernel32.dll" "system" fn LocalFree(hmem : HLOCAL) -> HLOCAL); windows_link::link!("kernel32.dll" "system" fn LockFileEx(hfile : HANDLE, dwflags : LOCK_FILE_FLAGS, dwreserved : u32, nnumberofbytestolocklow : u32, nnumberofbytestolockhigh : u32, lpoverlapped : *mut OVERLAPPED) -> BOOL); windows_link::link!("kernel32.dll" "system" fn MoveFileExW(lpexistingfilename : PCWSTR, lpnewfilename : PCWSTR, dwflags : MOVE_FILE_FLAGS) -> BOOL); @@ -74,6 +80,7 @@ windows_link::link!("kernel32.dll" "system" fn MultiByteToWideChar(codepage : u3 windows_link::link!("ntdll.dll" "system" fn NtCreateFile(filehandle : *mut HANDLE, desiredaccess : FILE_ACCESS_RIGHTS, objectattributes : *const OBJECT_ATTRIBUTES, iostatusblock : *mut IO_STATUS_BLOCK, allocationsize : *const i64, fileattributes : FILE_FLAGS_AND_ATTRIBUTES, shareaccess : FILE_SHARE_MODE, createdisposition : NTCREATEFILE_CREATE_DISPOSITION, createoptions : NTCREATEFILE_CREATE_OPTIONS, eabuffer : *const core::ffi::c_void, ealength : u32) -> NTSTATUS); windows_link::link!("ntdll.dll" "system" fn NtOpenFile(filehandle : *mut HANDLE, desiredaccess : u32, objectattributes : *const OBJECT_ATTRIBUTES, iostatusblock : *mut IO_STATUS_BLOCK, shareaccess : u32, openoptions : u32) -> NTSTATUS); windows_link::link!("ntdll.dll" "system" fn NtReadFile(filehandle : HANDLE, event : HANDLE, apcroutine : PIO_APC_ROUTINE, apccontext : *const core::ffi::c_void, iostatusblock : *mut IO_STATUS_BLOCK, buffer : *mut core::ffi::c_void, length : u32, byteoffset : *const i64, key : *const u32) -> NTSTATUS); +windows_link::link!("ntdll.dll" "system" fn NtSetInformationFile(filehandle : HANDLE, iostatusblock : *mut IO_STATUS_BLOCK, fileinformation : *const core::ffi::c_void, length : u32, fileinformationclass : FILE_INFORMATION_CLASS) -> NTSTATUS); windows_link::link!("ntdll.dll" "system" fn NtWriteFile(filehandle : HANDLE, event : HANDLE, apcroutine : PIO_APC_ROUTINE, apccontext : *const core::ffi::c_void, iostatusblock : *mut IO_STATUS_BLOCK, buffer : *const core::ffi::c_void, length : u32, byteoffset : *const i64, key : *const u32) -> NTSTATUS); windows_link::link!("advapi32.dll" "system" fn OpenProcessToken(processhandle : HANDLE, desiredaccess : TOKEN_ACCESS_MASK, tokenhandle : *mut HANDLE) -> BOOL); windows_link::link!("kernel32.dll" "system" fn QueryPerformanceCounter(lpperformancecount : *mut i64) -> BOOL); @@ -94,6 +101,7 @@ windows_link::link!("kernel32.dll" "system" fn SetFilePointerEx(hfile : HANDLE, windows_link::link!("kernel32.dll" "system" fn SetFileTime(hfile : HANDLE, lpcreationtime : *const FILETIME, lplastaccesstime : *const FILETIME, lplastwritetime : *const FILETIME) -> BOOL); windows_link::link!("kernel32.dll" "system" fn SetHandleInformation(hobject : HANDLE, dwmask : u32, dwflags : HANDLE_FLAGS) -> BOOL); windows_link::link!("kernel32.dll" "system" fn SetLastError(dwerrcode : WIN32_ERROR)); +windows_link::link!("kernel32.dll" "system" fn SetStdHandle(nstdhandle : STD_HANDLE, hhandle : HANDLE) -> BOOL); windows_link::link!("kernel32.dll" "system" fn SetThreadStackGuarantee(stacksizeinbytes : *mut u32) -> BOOL); windows_link::link!("kernel32.dll" "system" fn SetWaitableTimer(htimer : HANDLE, lpduetime : *const i64, lperiod : i32, pfncompletionroutine : PTIMERAPCROUTINE, lpargtocompletionroutine : *const core::ffi::c_void, fresume : BOOL) -> BOOL); windows_link::link!("kernel32.dll" "system" fn Sleep(dwmilliseconds : u32)); @@ -2531,6 +2539,7 @@ impl Default for FILE_ID_BOTH_DIR_INFO { unsafe { core::mem::zeroed() } } } +pub type FILE_INFORMATION_CLASS = i32; pub type FILE_INFO_BY_HANDLE_CLASS = i32; #[repr(C)] #[derive(Clone, Copy, Default)] @@ -2592,6 +2601,30 @@ impl Default for FILE_RENAME_INFO_0 { unsafe { core::mem::zeroed() } } } +#[repr(C)] +#[derive(Clone, Copy)] +pub struct FILE_RENAME_INFORMATION { + pub Anonymous: FILE_RENAME_INFORMATION_0, + pub RootDirectory: HANDLE, + pub FileNameLength: u32, + pub FileName: [u16; 1], +} +impl Default for FILE_RENAME_INFORMATION { + fn default() -> Self { + unsafe { core::mem::zeroed() } + } +} +#[repr(C)] +#[derive(Clone, Copy)] +pub union FILE_RENAME_INFORMATION_0 { + pub ReplaceIfExists: bool, + pub Flags: u32, +} +impl Default for FILE_RENAME_INFORMATION_0 { + fn default() -> Self { + unsafe { core::mem::zeroed() } + } +} pub const FILE_RESERVE_OPFILTER: NTCREATEFILE_CREATE_OPTIONS = 1048576u32; pub const FILE_SEQUENTIAL_ONLY: NTCREATEFILE_CREATE_OPTIONS = 4u32; pub const FILE_SESSION_AWARE: NTCREATEFILE_CREATE_OPTIONS = 262144u32; @@ -2667,6 +2700,7 @@ impl Default for FLOATING_SAVE_AREA { unsafe { core::mem::zeroed() } } } +pub const FLS_OUT_OF_INDEXES: u32 = 4294967295u32; pub const FORMAT_MESSAGE_ALLOCATE_BUFFER: FORMAT_MESSAGE_OPTIONS = 256u32; pub const FORMAT_MESSAGE_ARGUMENT_ARRAY: FORMAT_MESSAGE_OPTIONS = 8192u32; pub const FORMAT_MESSAGE_FROM_HMODULE: FORMAT_MESSAGE_OPTIONS = 2048u32; @@ -2699,6 +2733,8 @@ pub const FileNormalizedNameInfo: FILE_INFO_BY_HANDLE_CLASS = 24i32; pub const FileRemoteProtocolInfo: FILE_INFO_BY_HANDLE_CLASS = 13i32; pub const FileRenameInfo: FILE_INFO_BY_HANDLE_CLASS = 3i32; pub const FileRenameInfoEx: FILE_INFO_BY_HANDLE_CLASS = 22i32; +pub const FileRenameInformation: FILE_INFORMATION_CLASS = 10i32; +pub const FileRenameInformationEx: FILE_INFORMATION_CLASS = 65i32; pub const FileStandardInfo: FILE_INFO_BY_HANDLE_CLASS = 1i32; pub const FileStorageInfo: FILE_INFO_BY_HANDLE_CLASS = 16i32; pub const FileStreamInfo: FILE_INFO_BY_HANDLE_CLASS = 7i32; @@ -2710,6 +2746,8 @@ pub const GENERIC_EXECUTE: GENERIC_ACCESS_RIGHTS = 536870912u32; pub const GENERIC_READ: GENERIC_ACCESS_RIGHTS = 2147483648u32; pub const GENERIC_WRITE: GENERIC_ACCESS_RIGHTS = 1073741824u32; pub type GETFINALPATHNAMEBYHANDLE_FLAGS = u32; +pub const GET_MODULE_HANDLE_EX_FLAG_FROM_ADDRESS: u32 = 4u32; +pub const GET_MODULE_HANDLE_EX_FLAG_UNCHANGED_REFCOUNT: u32 = 2u32; #[repr(C)] #[derive(Clone, Copy)] pub struct GUID { @@ -3037,6 +3075,8 @@ pub struct OVERLAPPED_0_0 { } pub type PCSTR = *const u8; pub type PCWSTR = *const u16; +pub type PFLS_CALLBACK_FUNCTION = + Option; pub type PIO_APC_ROUTINE = Option< unsafe extern "system" fn( apccontext: *mut core::ffi::c_void, @@ -3189,6 +3229,7 @@ pub const SOCK_STREAM: WINSOCK_SOCKET_TYPE = 1i32; pub const SOL_SOCKET: i32 = 65535i32; pub const SO_BROADCAST: i32 = 32i32; pub const SO_ERROR: i32 = 4103i32; +pub const SO_KEEPALIVE: i32 = 8i32; pub const SO_LINGER: i32 = 128i32; pub const SO_RCVTIMEO: i32 = 4102i32; pub const SO_SNDTIMEO: i32 = 4101i32; @@ -3660,4 +3701,4 @@ pub struct WSADATA { } #[cfg(target_arch = "arm")] pub enum CONTEXT {} -// ignore-tidy-filelength +// ignore-tidy-file-filelength diff --git a/library/std/src/sys/pal/windows/handle.rs b/library/std/src/sys/pal/windows/handle.rs index 9b92cd79c06f4..f0885789d7070 100644 --- a/library/std/src/sys/pal/windows/handle.rs +++ b/library/std/src/sys/pal/windows/handle.rs @@ -109,7 +109,7 @@ impl Handle { } } - pub fn read_buf(&self, mut cursor: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, mut cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { let res = unsafe { self.synchronous_read(cursor.as_mut().as_mut_ptr(), cursor.capacity(), None) }; @@ -117,7 +117,7 @@ impl Handle { Ok(read) => { // Safety: `read` bytes were written to the initialized portion of the buffer unsafe { - cursor.advance_unchecked(read); + cursor.advance(read); } Ok(()) } @@ -132,7 +132,7 @@ impl Handle { } } - pub fn read_buf_at(&self, mut cursor: BorrowedCursor<'_>, offset: u64) -> io::Result<()> { + pub fn read_buf_at(&self, mut cursor: BorrowedCursor<'_, u8>, offset: u64) -> io::Result<()> { // SAFETY: `cursor.as_mut()` starts with `cursor.capacity()` writable bytes let read = unsafe { self.synchronous_read(cursor.as_mut().as_mut_ptr(), cursor.capacity(), Some(offset)) @@ -140,7 +140,7 @@ impl Handle { // SAFETY: `read` bytes were written to the initialized portion of the buffer unsafe { - cursor.advance_unchecked(read); + cursor.advance(read); } Ok(()) } @@ -347,7 +347,7 @@ impl<'a> Read for &'a Handle { (**self).read(buf) } - fn read_buf(&mut self, buf: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, buf: BorrowedCursor<'_, u8>) -> io::Result<()> { (**self).read_buf(buf) } diff --git a/library/std/src/sys/pal/windows/mod.rs b/library/std/src/sys/pal/windows/mod.rs index 0cd9152614716..2a8ffaa0baab8 100644 --- a/library/std/src/sys/pal/windows/mod.rs +++ b/library/std/src/sys/pal/windows/mod.rs @@ -15,10 +15,7 @@ pub mod compat; pub mod api; pub mod c; -#[cfg(not(target_vendor = "win7"))] -pub mod futex; pub mod handle; -pub mod os; pub mod time; cfg_select! { // We don't care about printing nice error messages for panic=immediate-abort @@ -55,7 +52,9 @@ pub unsafe fn init(_argc: isize, _argv: *const *const u8, _sigpipe: u8) { } // SAFETY: must be called only once during runtime cleanup. -// NOTE: this is not guaranteed to run, for example when the program aborts. +// NOTE: this is not guaranteed to run, for example when the program aborts, and +// is not guaranteed to run on the main thread (#161018 was caused by that +// mistaken assumption). pub unsafe fn cleanup() { winsock::cleanup(); } diff --git a/library/std/src/sys/pal/windows/time.rs b/library/std/src/sys/pal/windows/time.rs index b4b1d50a88896..2646ad28b84a2 100644 --- a/library/std/src/sys/pal/windows/time.rs +++ b/library/std/src/sys/pal/windows/time.rs @@ -20,7 +20,7 @@ pub fn intervals2dur(intervals: u64) -> Duration { pub mod perf_counter { use super::NANOS_PER_SEC; - use crate::sync::atomic::{Atomic, AtomicU64, Ordering}; + use crate::sync::atomic::{AtomicI64, Ordering}; use crate::sys::{c, cvt}; use crate::time::Duration; @@ -32,23 +32,32 @@ pub mod perf_counter { pub fn frequency() -> i64 { // Either the cached result of `QueryPerformanceFrequency` or `0` for - // uninitialized. Storing this as a single `AtomicU64` allows us to use + // uninitialized. Storing this as a single `AtomicI64` allows us to use // `Relaxed` operations, as we are only interested in the effects on a // single memory location. - static FREQUENCY: Atomic = AtomicU64::new(0); + static FREQUENCY: AtomicI64 = AtomicI64::new(0); let cached = FREQUENCY.load(Ordering::Relaxed); // If a previous thread has filled in this global state, use that. if cached != 0 { - return cached as i64; + return cached; } // ... otherwise learn for ourselves ... + frequency_init(&FREQUENCY) + } + + #[cold] + fn frequency_init(cache: &AtomicI64) -> i64 { let mut frequency = 0; unsafe { cvt(c::QueryPerformanceFrequency(&mut frequency)).unwrap(); } - FREQUENCY.store(frequency as u64, Ordering::Relaxed); + // SAFETY: According to the MSDN entry for `QueryPerformanceFrequency`, + // a value of 0 will never be returned starting from Windows XP. + unsafe { crate::hint::assert_unchecked(frequency != 0) } + + cache.store(frequency, Ordering::Relaxed); frequency } diff --git a/library/std/src/sys/pal/windows/winsock.rs b/library/std/src/sys/pal/windows/winsock.rs index b110a43ef3aa8..7b2e7fe59171c 100644 --- a/library/std/src/sys/pal/windows/winsock.rs +++ b/library/std/src/sys/pal/windows/winsock.rs @@ -1,18 +1,17 @@ use super::c; use crate::ffi::c_int; -use crate::sync::atomic::Atomic; -use crate::sync::atomic::Ordering::{AcqRel, Relaxed}; +use crate::sync::Once; use crate::{io, mem}; -static WSA_STARTED: Atomic = Atomic::::new(false); +static WSA_INIT: Once = Once::new(); /// Checks whether the Windows socket interface has been started already, and /// if not, starts it. #[inline] pub fn startup() { - if !WSA_STARTED.load(Relaxed) { - wsa_startup(); - } + // Make sure to only call `WSAStartup` once, because it's not thread-safe + // on Wine: https://bugs.winehq.org/show_bug.cgi?id=60084. + WSA_INIT.call_once_force(|_| wsa_startup()); } #[cold] @@ -24,11 +23,6 @@ fn wsa_startup() { &mut data, ); assert_eq!(ret, 0); - if WSA_STARTED.swap(true, AcqRel) { - // If another thread raced with us and called WSAStartup first then call - // WSACleanup so it's as though WSAStartup was only called once. - c::WSACleanup(); - } } } diff --git a/library/std/src/sys/pal/xous/mod.rs b/library/std/src/sys/pal/xous/mod.rs index 87c99068929c3..b5b3fd91b4fa6 100644 --- a/library/std/src/sys/pal/xous/mod.rs +++ b/library/std/src/sys/pal/xous/mod.rs @@ -1,7 +1,54 @@ #![forbid(unsafe_op_in_unsafe_fn)] -pub mod os; +pub mod params; #[path = "../unsupported/common.rs"] mod common; pub use common::*; + +#[cfg(not(test))] +#[cfg(feature = "panic-unwind")] +mod eh_unwinding { + pub(crate) struct EhFrameFinder; + pub(crate) static mut EH_FRAME_ADDRESS: usize = 0; + pub(crate) static EH_FRAME_SETTINGS: EhFrameFinder = EhFrameFinder; + + unsafe impl unwind::EhFrameFinder for EhFrameFinder { + fn find(&self, _pc: usize) -> Option { + if unsafe { EH_FRAME_ADDRESS == 0 } { + None + } else { + Some(unwind::FrameInfo { + text_base: None, + kind: unwind::FrameInfoKind::EhFrame(unsafe { EH_FRAME_ADDRESS }), + }) + } + } + } +} + +#[cfg(not(test))] +mod c_compat { + use crate::os::xous::ffi::exit; + + unsafe extern "C" { + fn main() -> u32; + } + + #[unsafe(no_mangle)] + pub extern "C" fn abort() { + exit(1); + } + + #[unsafe(no_mangle)] + pub extern "C" fn _start(eh_frame: usize, params: *mut u8) { + #[cfg(feature = "panic-unwind")] + { + unsafe { super::eh_unwinding::EH_FRAME_ADDRESS = eh_frame }; + unwind::set_custom_eh_frame_finder(&super::eh_unwinding::EH_FRAME_SETTINGS).ok(); + } + + unsafe { super::params::set(params) }; + exit(unsafe { main() }); + } +} diff --git a/library/std/src/sys/pal/xous/os.rs b/library/std/src/sys/pal/xous/os.rs deleted file mode 100644 index cd7b7b59d1127..0000000000000 --- a/library/std/src/sys/pal/xous/os.rs +++ /dev/null @@ -1,128 +0,0 @@ -use super::unsupported; -use crate::ffi::{OsStr, OsString}; -use crate::marker::PhantomData; -use crate::path::{self, PathBuf}; -use crate::sync::atomic::{Atomic, AtomicPtr, Ordering}; -use crate::{fmt, io}; - -pub(crate) mod params; - -static PARAMS_ADDRESS: Atomic<*mut u8> = AtomicPtr::new(core::ptr::null_mut()); - -#[cfg(not(test))] -#[cfg(feature = "panic-unwind")] -mod eh_unwinding { - pub(crate) struct EhFrameFinder; - pub(crate) static mut EH_FRAME_ADDRESS: usize = 0; - pub(crate) static EH_FRAME_SETTINGS: EhFrameFinder = EhFrameFinder; - - unsafe impl unwind::EhFrameFinder for EhFrameFinder { - fn find(&self, _pc: usize) -> Option { - if unsafe { EH_FRAME_ADDRESS == 0 } { - None - } else { - Some(unwind::FrameInfo { - text_base: None, - kind: unwind::FrameInfoKind::EhFrame(unsafe { EH_FRAME_ADDRESS }), - }) - } - } - } -} - -#[cfg(not(test))] -mod c_compat { - use crate::os::xous::ffi::exit; - unsafe extern "C" { - fn main() -> u32; - } - - #[unsafe(no_mangle)] - pub extern "C" fn abort() { - exit(1); - } - - #[unsafe(no_mangle)] - pub extern "C" fn _start(eh_frame: usize, params_address: usize) { - #[cfg(feature = "panic-unwind")] - { - unsafe { super::eh_unwinding::EH_FRAME_ADDRESS = eh_frame }; - unwind::set_custom_eh_frame_finder(&super::eh_unwinding::EH_FRAME_SETTINGS).ok(); - } - - if params_address != 0 { - let params_address = crate::ptr::with_exposed_provenance_mut::(params_address); - if unsafe { - super::params::ApplicationParameters::new_from_ptr(params_address).is_some() - } { - super::PARAMS_ADDRESS.store(params_address, core::sync::atomic::Ordering::Relaxed); - } - } - exit(unsafe { main() }); - } -} - -pub fn getcwd() -> io::Result { - unsupported() -} - -pub fn chdir(_: &path::Path) -> io::Result<()> { - unsupported() -} - -pub struct SplitPaths<'a>(!, PhantomData<&'a ()>); - -pub fn split_paths(_unparsed: &OsStr) -> SplitPaths<'_> { - panic!("unsupported") -} - -impl<'a> Iterator for SplitPaths<'a> { - type Item = PathBuf; - fn next(&mut self) -> Option { - self.0 - } -} - -#[derive(Debug)] -pub struct JoinPathsError; - -pub fn join_paths(_paths: I) -> Result -where - I: Iterator, - T: AsRef, -{ - Err(JoinPathsError) -} - -impl fmt::Display for JoinPathsError { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - "not supported on this platform yet".fmt(f) - } -} - -impl crate::error::Error for JoinPathsError {} - -pub fn current_exe() -> io::Result { - unsupported() -} - -pub(crate) fn get_application_parameters() -> Option { - let params_address = PARAMS_ADDRESS.load(Ordering::Relaxed); - unsafe { params::ApplicationParameters::new_from_ptr(params_address) } -} - -pub fn temp_dir() -> PathBuf { - panic!("no filesystem on this platform") -} - -pub fn home_dir() -> Option { - None -} - -pub fn exit(code: i32) -> ! { - crate::os::xous::ffi::exit(code as u32); -} - -pub fn getpid() -> u32 { - panic!("no pids on this platform") -} diff --git a/library/std/src/sys/pal/xous/os/params.rs b/library/std/src/sys/pal/xous/params.rs similarity index 67% rename from library/std/src/sys/pal/xous/os/params.rs rename to library/std/src/sys/pal/xous/params.rs index 0d02cf35477f9..d6f671e9a6b68 100644 --- a/library/std/src/sys/pal/xous/os/params.rs +++ b/library/std/src/sys/pal/xous/params.rs @@ -1,75 +1,100 @@ -/// Xous passes a pointer to the parameter block as the second argument. -/// This is used for passing flags such as environment variables. The -/// format of the argument block is: -/// -/// #[repr(C)] -/// struct BlockHeader { -/// /// Magic number that identifies this block. Must be printable ASCII. -/// magic: [u8; 4], -/// -/// /// The size of the data block. Does not include this header. May be 0. -/// size: u32, -/// -/// /// The contents of this block. Varies depending on the block type. -/// data: [u8; 0], -/// } -/// -/// There is a BlockHeader at the start that has magic `AppP`, and the data -/// that follows is the number of blocks present: -/// -/// #[repr(C)] -/// struct ApplicationParameters { -/// magic: b"AppP", -/// size: 4u32, -/// -/// /// The size of the entire application slice, in bytes, including all headers -/// length: u32, -/// -/// /// Number of application parameters present. Must be at least 1 (this block) -/// entries: (parameter_count as u32).to_bytes_le(), -/// } -/// -/// #[repr(C)] -/// struct EnvironmentBlock { -/// magic: b"EnvB", -/// -/// /// Total number of bytes, excluding this header -/// size: 2+data.len(), -/// -/// /// The number of environment variables -/// count: u16, -/// -/// /// Environment variable iteration -/// data: [u8; 0], -/// } -/// -/// Environment variables are present in an `EnvB` block. The `data` section is -/// a sequence of bytes of the form: -/// -/// (u16 /* key_len */; [0u8; key_len as usize] /* key */, -/// u16 /* val_len */ [0u8; val_len as usize]) -/// -/// #[repr(C)] -/// struct ArgumentList { -/// magic: b"ArgL", -/// -/// /// Total number of bytes, excluding this header -/// size: 2+data.len(), -/// -/// /// The number of arguments variables -/// count: u16, -/// -/// /// Argument variable iteration -/// data: [u8; 0], -/// } -/// -/// Args are just an array of strings that represent command line arguments. -/// They are a sequence of the form: -/// -/// (u16 /* val_len */ [0u8; val_len as usize]) -use core::slice; +//! Xous passes a pointer to the parameter block as the second argument. +//! This is used for passing flags such as environment variables. The +//! format of the argument block is: +//! +//! #[repr(C)] +//! struct BlockHeader { +//! /// Magic number that identifies this block. Must be printable ASCII. +//! magic: [u8; 4], +//! +//! /// The size of the data block. Does not include this header. May be 0. +//! size: u32, +//! +//! /// The contents of this block. Varies depending on the block type. +//! data: [u8; 0], +//! } +//! +//! There is a BlockHeader at the start that has magic `AppP`, and the data +//! that follows is the number of blocks present: +//! +//! #[repr(C)] +//! struct ApplicationParameters { +//! magic: b"AppP", +//! size: 4u32, +//! +//! /// The size of the entire application slice, in bytes, including all headers +//! length: u32, +//! +//! /// Number of application parameters present. Must be at least 1 (this block) +//! entries: (parameter_count as u32).to_bytes_le(), +//! } +//! +//! #[repr(C)] +//! struct EnvironmentBlock { +//! magic: b"EnvB", +//! +//! /// Total number of bytes, excluding this header +//! size: 2+data.len(), +//! +//! /// The number of environment variables +//! count: u16, +//! +//! /// Environment variable iteration +//! data: [u8; 0], +//! } +//! +//! Environment variables are present in an `EnvB` block. The `data` section is +//! a sequence of bytes of the form: +//! +//! (u16 /* key_len */; [0u8; key_len as usize] /* key */, +//! u16 /* val_len */ [0u8; val_len as usize]) +//! +//! #[repr(C)] +//! struct ArgumentList { +//! magic: b"ArgL", +//! +//! /// Total number of bytes, excluding this header +//! size: 2+data.len(), +//! +//! /// The number of arguments variables +//! count: u16, +//! +//! /// Argument variable iteration +//! data: [u8; 0], +//! } +//! +//! Args are just an array of strings that represent command line arguments. +//! They are a sequence of the form: +//! +//! (u16 /* val_len */ [0u8; val_len as usize]) use crate::ffi::OsString; +use crate::slice; + +#[cfg(test)] +mod tests; + +static mut PARAMS: *mut u8 = crate::ptr::null_mut(); + +/// Remember the location of the parameter block. +/// +/// # Safety +/// * This function may only be called before `main`. +/// * `data` must either be `null` or point to a valid parameter block. +pub(super) unsafe fn set(data: *mut u8) { + // SAFETY: + // Since this function is called before `main`, there cannot be any threads + // already running. Thus this write cannot race, and all threads will observe + // this write and the parameter block initialization since it happens-before + // their creation. + unsafe { PARAMS = data }; +} + +pub(crate) fn get() -> Option { + // SAFETY: See above. + let data = unsafe { PARAMS }; + unsafe { ApplicationParameters::new_from_ptr(data) } +} /// Magic number indicating we have an environment block const ENV_MAGIC: [u8; 4] = *b"EnvB"; @@ -80,9 +105,6 @@ const ARGS_MAGIC: [u8; 4] = *b"ArgL"; /// Magic number indicating the loader has passed application parameters const PARAMS_MAGIC: [u8; 4] = *b"AppP"; -#[cfg(test)] -mod tests; - pub(crate) struct ApplicationParameters { data: &'static [u8], offset: usize, @@ -90,7 +112,7 @@ pub(crate) struct ApplicationParameters { } impl ApplicationParameters { - pub(crate) unsafe fn new_from_ptr(data: *const u8) -> Option { + unsafe fn new_from_ptr(data: *const u8) -> Option { if data.is_null() { return None; } diff --git a/library/std/src/sys/pal/xous/os/params/tests.rs b/library/std/src/sys/pal/xous/params/tests.rs similarity index 100% rename from library/std/src/sys/pal/xous/os/params/tests.rs rename to library/std/src/sys/pal/xous/params/tests.rs diff --git a/library/std/src/sys/pal/zkvm/mod.rs b/library/std/src/sys/pal/zkvm/mod.rs index 1b18adb811d95..1a64d3c93d701 100644 --- a/library/std/src/sys/pal/zkvm/mod.rs +++ b/library/std/src/sys/pal/zkvm/mod.rs @@ -11,7 +11,6 @@ pub const WORD_SIZE: usize = size_of::(); pub mod abi; -pub mod os; use crate::io as std_io; diff --git a/library/std/src/sys/path/cygwin.rs b/library/std/src/sys/path/cygwin.rs index 75f0de6beaeb5..494dd91f23140 100644 --- a/library/std/src/sys/path/cygwin.rs +++ b/library/std/src/sys/path/cygwin.rs @@ -5,25 +5,20 @@ use crate::sys::cvt; use crate::sys::helpers::run_path_with_cstr; use crate::{io, ptr}; -#[inline] -pub fn is_sep_byte(b: u8) -> bool { - b == b'/' || b == b'\\' -} +path_separator_bytes!(b'/', b'\\'); /// Cygwin always prefers `/` over `\`, and it always converts all `/` to `\` /// internally when calling Win32 APIs. Therefore, the server component of path /// `\\?\UNC\localhost/share` is `localhost/share` on Win32, but `localhost` /// on Cygwin. #[inline] -pub fn is_verbatim_sep(b: u8) -> bool { - b == b'/' || b == b'\\' +pub const fn is_verbatim_sep(b: u8) -> bool { + is_sep_byte(b) } pub use super::windows_prefix::parse_prefix; pub const HAS_PREFIXES: bool = true; -pub const MAIN_SEP_STR: &str = "/"; -pub const MAIN_SEP: char = '/'; unsafe extern "C" { // Doc: https://cygwin.com/cygwin-api/func-cygwin-conv-path.html diff --git a/library/std/src/sys/path/mod.rs b/library/std/src/sys/path/mod.rs index 254683bc83f91..bbb7577e186ae 100644 --- a/library/std/src/sys/path/mod.rs +++ b/library/std/src/sys/path/mod.rs @@ -1,3 +1,22 @@ +// There's a lot of necessary redundancy in separator definition. Consolidated into a macro to +// prevent transcription errors. +macro_rules! path_separator_bytes { + ($($sep:literal),+) => ( + pub const SEPARATORS: &[char] = &[$($sep as char,)+]; + pub const SEPARATORS_STR: &[&str] = &[$( + match str::from_utf8(&[$sep]) { + Ok(s) => s, + Err(_) => panic!("path_separator_bytes must be ASCII bytes"), + } + ),+]; + + #[inline] + pub const fn is_sep_byte(b: u8) -> bool { + $(b == $sep) ||+ + } + ) +} + cfg_select! { target_os = "windows" => { mod windows; diff --git a/library/std/src/sys/path/sgx.rs b/library/std/src/sys/path/sgx.rs index dca61f3ea145d..9b7ab30a9c652 100644 --- a/library/std/src/sys/path/sgx.rs +++ b/library/std/src/sys/path/sgx.rs @@ -3,14 +3,11 @@ use crate::io; use crate::path::{Path, PathBuf, Prefix}; use crate::sys::unsupported; -#[inline] -pub fn is_sep_byte(b: u8) -> bool { - b == b'/' -} +path_separator_bytes!(b'/'); #[inline] -pub fn is_verbatim_sep(b: u8) -> bool { - b == b'/' +pub const fn is_verbatim_sep(b: u8) -> bool { + is_sep_byte(b) } pub fn parse_prefix(_: &OsStr) -> Option> { @@ -18,8 +15,6 @@ pub fn parse_prefix(_: &OsStr) -> Option> { } pub const HAS_PREFIXES: bool = false; -pub const MAIN_SEP_STR: &str = "/"; -pub const MAIN_SEP: char = '/'; pub(crate) fn absolute(_path: &Path) -> io::Result { unsupported() diff --git a/library/std/src/sys/path/uefi.rs b/library/std/src/sys/path/uefi.rs index 84d634af93cf1..8c911ee5f9c53 100644 --- a/library/std/src/sys/path/uefi.rs +++ b/library/std/src/sys/path/uefi.rs @@ -5,17 +5,14 @@ use crate::path::{Path, PathBuf, Prefix}; use crate::sys::pal::helpers; use crate::sys::unsupported_err; +path_separator_bytes!(b'\\'); + const FORWARD_SLASH: u8 = b'/'; const COLON: u8 = b':'; #[inline] -pub fn is_sep_byte(b: u8) -> bool { - b == b'\\' -} - -#[inline] -pub fn is_verbatim_sep(b: u8) -> bool { - b == b'\\' +pub const fn is_verbatim_sep(b: u8) -> bool { + is_sep_byte(b) } pub fn parse_prefix(_: &OsStr) -> Option> { @@ -23,8 +20,6 @@ pub fn parse_prefix(_: &OsStr) -> Option> { } pub const HAS_PREFIXES: bool = true; -pub const MAIN_SEP_STR: &str = "\\"; -pub const MAIN_SEP: char = '\\'; /// UEFI paths can be of 4 types: /// diff --git a/library/std/src/sys/path/unix.rs b/library/std/src/sys/path/unix.rs index 611d250db4050..5a8c0c77745e0 100644 --- a/library/std/src/sys/path/unix.rs +++ b/library/std/src/sys/path/unix.rs @@ -2,14 +2,11 @@ use crate::ffi::OsStr; use crate::path::{Path, PathBuf, Prefix}; use crate::{env, io}; -#[inline] -pub fn is_sep_byte(b: u8) -> bool { - b == b'/' -} +path_separator_bytes!(b'/'); #[inline] -pub fn is_verbatim_sep(b: u8) -> bool { - b == b'/' +pub const fn is_verbatim_sep(b: u8) -> bool { + is_sep_byte(b) } #[inline] @@ -18,15 +15,13 @@ pub fn parse_prefix(_: &OsStr) -> Option> { } pub const HAS_PREFIXES: bool = false; -pub const MAIN_SEP_STR: &str = "/"; -pub const MAIN_SEP: char = '/'; /// Make a POSIX path absolute without changing its semantics. pub(crate) fn absolute(path: &Path) -> io::Result { // This is mostly a wrapper around collecting `Path::components`, with // exceptions made where this conflicts with the POSIX specification. - // See 4.13 Pathname Resolution, IEEE Std 1003.1-2017 - // https://pubs.opengroup.org/onlinepubs/9699919799/basedefs/V1_chap04.html#tag_04_13 + // See 4.16 Pathname Resolution, IEEE Std 1003.1-2024 + // https://pubs.opengroup.org/onlinepubs/9799919799/basedefs/V1_chap04.html#tag_04_16 // Get the components, skipping the redundant leading "." component if it exists. let mut components = path.strip_prefix(".").unwrap_or(path).components(); diff --git a/library/std/src/sys/path/unsupported_backslash.rs b/library/std/src/sys/path/unsupported_backslash.rs index 8ed1fdc36e23f..ce1851e938395 100644 --- a/library/std/src/sys/path/unsupported_backslash.rs +++ b/library/std/src/sys/path/unsupported_backslash.rs @@ -4,14 +4,11 @@ use crate::io; use crate::path::{Path, PathBuf, Prefix}; use crate::sys::unsupported; -#[inline] -pub fn is_sep_byte(b: u8) -> bool { - b == b'\\' -} +path_separator_bytes!(b'\\'); #[inline] -pub fn is_verbatim_sep(b: u8) -> bool { - b == b'\\' +pub const fn is_verbatim_sep(b: u8) -> bool { + is_sep_byte(b) } pub fn parse_prefix(_: &OsStr) -> Option> { @@ -19,8 +16,6 @@ pub fn parse_prefix(_: &OsStr) -> Option> { } pub const HAS_PREFIXES: bool = true; -pub const MAIN_SEP_STR: &str = "\\"; -pub const MAIN_SEP: char = '\\'; pub(crate) fn absolute(_path: &Path) -> io::Result { unsupported() diff --git a/library/std/src/sys/path/windows.rs b/library/std/src/sys/path/windows.rs index 509b13b6ae812..2dbe33e2cf8b0 100644 --- a/library/std/src/sys/path/windows.rs +++ b/library/std/src/sys/path/windows.rs @@ -9,9 +9,9 @@ mod tests; pub use super::windows_prefix::parse_prefix; +path_separator_bytes!(b'\\', b'/'); + pub const HAS_PREFIXES: bool = true; -pub const MAIN_SEP_STR: &str = "\\"; -pub const MAIN_SEP: char = '\\'; /// A null terminated wide string. #[repr(transparent)] @@ -48,12 +48,7 @@ pub fn with_native_path(path: &Path, f: &dyn Fn(&WCStr) -> io::Result) -> } #[inline] -pub fn is_sep_byte(b: u8) -> bool { - b == b'/' || b == b'\\' -} - -#[inline] -pub fn is_verbatim_sep(b: u8) -> bool { +pub const fn is_verbatim_sep(b: u8) -> bool { b == b'\\' } @@ -256,6 +251,6 @@ pub(crate) fn is_absolute_exact(path: &[u16]) -> bool { unsafe { new_path.set_len((result as usize) + 1); } - path == &new_path + path == new_path } } diff --git a/library/std/src/sys/paths/hermit.rs b/library/std/src/sys/paths/hermit.rs new file mode 100644 index 0000000000000..36f667d300539 --- /dev/null +++ b/library/std/src/sys/paths/hermit.rs @@ -0,0 +1,10 @@ +use crate::io; +use crate::path::PathBuf; + +pub fn getcwd() -> io::Result { + Ok(PathBuf::from("/")) +} + +pub fn temp_dir() -> PathBuf { + PathBuf::from("/tmp") +} diff --git a/library/std/src/sys/paths/mod.rs b/library/std/src/sys/paths/mod.rs new file mode 100644 index 0000000000000..57f894249ae74 --- /dev/null +++ b/library/std/src/sys/paths/mod.rs @@ -0,0 +1,68 @@ +cfg_select! { + target_os = "hermit" => { + mod hermit; + #[expect(dead_code)] + mod unsupported; + mod imp { + pub use super::hermit::{getcwd, temp_dir}; + pub use super::unsupported::{ + JoinPathsError, SplitPaths, chdir, current_exe, home_dir, join_paths, split_paths, + }; + } + } + target_os = "motor" => { + mod motor; + #[expect(dead_code)] + mod unsupported; + mod imp { + pub use super::motor::{chdir, current_exe, getcwd, temp_dir}; + pub use super::unsupported::{ + JoinPathsError, SplitPaths, home_dir, join_paths, split_paths, + }; + } + } + all(target_vendor = "fortanix", target_env = "sgx") => { + mod sgx; + #[expect(dead_code)] + mod unsupported; + mod imp { + pub use super::sgx::chdir; + pub use super::unsupported::{ + JoinPathsError, SplitPaths, current_exe, getcwd, home_dir, join_paths, split_paths, + temp_dir, + }; + } + } + target_os = "uefi" => { + mod uefi; + use uefi as imp; + } + target_family = "unix" => { + mod unix; + use unix as imp; + } + target_os = "wasi" => { + mod wasi; + #[expect(dead_code)] + mod unsupported; + mod imp { + pub use super::unsupported::{ + JoinPathsError, SplitPaths, current_exe, home_dir, join_paths, split_paths, + }; + pub use super::wasi::{chdir, getcwd, temp_dir}; + } + } + target_os = "windows" => { + mod windows; + use windows as imp; + } + _ => { + mod unsupported; + use unsupported as imp; + } +} + +pub use imp::{ + JoinPathsError, SplitPaths, chdir, current_exe, getcwd, home_dir, join_paths, split_paths, + temp_dir, +}; diff --git a/library/std/src/sys/paths/motor.rs b/library/std/src/sys/paths/motor.rs new file mode 100644 index 0000000000000..33d746b13d592 --- /dev/null +++ b/library/std/src/sys/paths/motor.rs @@ -0,0 +1,20 @@ +use crate::io; +use crate::os::motor::ffi::OsStrExt; +use crate::path::{self, PathBuf}; +use crate::sys::pal::map_motor_error; + +pub fn getcwd() -> io::Result { + moto_rt::fs::getcwd().map(PathBuf::from).map_err(map_motor_error) +} + +pub fn chdir(path: &path::Path) -> io::Result<()> { + moto_rt::fs::chdir(path.as_os_str().as_str()).map_err(map_motor_error) +} + +pub fn current_exe() -> io::Result { + moto_rt::process::current_exe().map(PathBuf::from).map_err(map_motor_error) +} + +pub fn temp_dir() -> PathBuf { + PathBuf::from(moto_rt::fs::TEMP_DIR) +} diff --git a/library/std/src/sys/paths/sgx.rs b/library/std/src/sys/paths/sgx.rs new file mode 100644 index 0000000000000..6a4cbe93b1b88 --- /dev/null +++ b/library/std/src/sys/paths/sgx.rs @@ -0,0 +1,7 @@ +use crate::io; +use crate::path::Path; +use crate::sys::pal::sgx_ineffective; + +pub fn chdir(_: &Path) -> io::Result<()> { + sgx_ineffective(()) +} diff --git a/library/std/src/sys/pal/uefi/os.rs b/library/std/src/sys/paths/uefi.rs similarity index 75% rename from library/std/src/sys/pal/uefi/os.rs rename to library/std/src/sys/paths/uefi.rs index 5b9785c8371e3..7fddcfdff7724 100644 --- a/library/std/src/sys/pal/uefi/os.rs +++ b/library/std/src/sys/paths/uefi.rs @@ -1,13 +1,9 @@ -use r_efi::efi::Status; use r_efi::efi::protocols::{device_path, loaded_image_device_path}; -use super::{helpers, unsupported_err}; use crate::ffi::{OsStr, OsString}; -use crate::marker::PhantomData; -use crate::os::uefi; use crate::os::uefi::ffi::{OsStrExt, OsStringExt}; use crate::path::{self, PathBuf}; -use crate::ptr::NonNull; +use crate::sys::pal::{helpers, unsupported_err}; use crate::{fmt, io}; const PATHS_SEP: u16 = b';' as u16; @@ -41,16 +37,37 @@ pub fn chdir(p: &path::Path) -> io::Result<()> { if r.is_error() { Err(io::Error::from_raw_os_error(r.as_usize())) } else { Ok(()) } } -pub struct SplitPaths<'a>(!, PhantomData<&'a ()>); +pub struct SplitPaths<'a> { + data: crate::os::uefi::ffi::EncodeWide<'a>, + must_yield: bool, +} -pub fn split_paths(_unparsed: &OsStr) -> SplitPaths<'_> { - panic!("unsupported") +pub fn split_paths(unparsed: &OsStr) -> SplitPaths<'_> { + SplitPaths { data: unparsed.encode_wide(), must_yield: true } } impl<'a> Iterator for SplitPaths<'a> { type Item = PathBuf; + fn next(&mut self) -> Option { - self.0 + let must_yield = self.must_yield; + self.must_yield = false; + + let mut in_progress = Vec::new(); + for b in self.data.by_ref() { + if b == PATHS_SEP { + self.must_yield = true; + break; + } else { + in_progress.push(b) + } + } + + if !must_yield && in_progress.is_empty() { + None + } else { + Some(PathBuf::from(OsString::from_wide(&in_progress))) + } } } @@ -98,30 +115,9 @@ pub fn current_exe() -> io::Result { } pub fn temp_dir() -> PathBuf { - panic!("no filesystem on this platform") + panic!("UEFI doesn't have a dedicated temp directory") } pub fn home_dir() -> Option { None } - -pub fn exit(code: i32) -> ! { - if let (Some(boot_services), Some(handle)) = - (uefi::env::boot_services(), uefi::env::try_image_handle()) - { - let boot_services: NonNull = boot_services.cast(); - let _ = unsafe { - ((*boot_services.as_ptr()).exit)( - handle.as_ptr(), - Status::from_usize(code as usize), - 0, - crate::ptr::null_mut(), - ) - }; - } - crate::intrinsics::abort() -} - -pub fn getpid() -> u32 { - panic!("no pids on this platform") -} diff --git a/library/std/src/sys/pal/unix/os.rs b/library/std/src/sys/paths/unix.rs similarity index 73% rename from library/std/src/sys/pal/unix/os.rs rename to library/std/src/sys/paths/unix.rs index b8280a8f29a02..e023451b13c8c 100644 --- a/library/std/src/sys/pal/unix/os.rs +++ b/library/std/src/sys/paths/unix.rs @@ -2,16 +2,13 @@ #![allow(unused_imports)] // lots of cfg code here -#[cfg(test)] -mod tests; - use libc::{c_char, c_int, c_void}; use crate::ffi::{CStr, OsStr, OsString}; use crate::os::unix::prelude::*; use crate::path::{self, PathBuf}; -use crate::sys::cvt; use crate::sys::helpers::run_path_with_cstr; +use crate::sys::pal::cvt; use crate::{fmt, io, iter, mem, ptr, slice, str}; const PATH_SEPARATOR: u8 = b':'; @@ -50,7 +47,7 @@ pub fn getcwd() -> io::Result { #[cfg(target_os = "espidf")] pub fn chdir(_p: &path::Path) -> io::Result<()> { - super::unsupported::unsupported() + crate::sys::pal::unsupported() } #[cfg(not(target_os = "espidf"))] @@ -210,7 +207,7 @@ pub fn current_exe() -> io::Result { cvt(libc::sysctl( mib.as_ptr(), mib.len() as libc::c_uint, - path.as_ptr() as *mut libc::c_void, + path.as_mut_ptr() as *mut libc::c_void, &mut path_len, ptr::null(), 0, @@ -237,18 +234,31 @@ pub fn current_exe() -> io::Result { unsafe { let mut mib = [libc::CTL_KERN, libc::KERN_PROC_ARGS, libc::getpid(), libc::KERN_PROC_ARGV]; let mib = mib.as_mut_ptr(); - let mut argv_len = 0; - cvt(libc::sysctl(mib, 4, ptr::null_mut(), &mut argv_len, ptr::null_mut(), 0))?; - let mut argv = Vec::<*const libc::c_char>::with_capacity(argv_len as usize); - cvt(libc::sysctl(mib, 4, argv.as_mut_ptr() as *mut _, &mut argv_len, ptr::null_mut(), 0))?; - argv.set_len(argv_len as usize); + + // Determine the required size (in bytes) for the argument array ... + let mut argv_size = 0; + cvt(libc::sysctl(mib, 4, ptr::null_mut(), &mut argv_size, ptr::null_mut(), 0))?; + + // ... allocate a buffer for it ... + let argc = argv_size.div_exact(size_of::<*const libc::c_char>()).unwrap(); + let mut argv = Vec::<*const libc::c_char>::with_capacity(argc); + + // ... and retrieve the argument array. + cvt(libc::sysctl(mib, 4, argv.as_mut_ptr() as *mut _, &mut argv_size, ptr::null_mut(), 0))?; + let argc = argv_size.div_exact(size_of::<*const libc::c_char>()).unwrap(); + argv.set_len(argc); + if argv[0].is_null() { return Err(io::const_error!(io::ErrorKind::Uncategorized, "no current exe available")); } let argv0 = CStr::from_ptr(argv[0]).to_bytes(); - if argv0[0] == b'.' || argv0.iter().any(|b| *b == b'/') { + if argv0.iter().any(|b| *b == b'/') { + // The program name is path-like, so try to canonicalize it. crate::fs::canonicalize(OsStr::from_bytes(argv0)) } else { + // The program was probably found in the PATH. Instead of trying to + // find it again (which might not succeed if PATH has changed), just + // return the program name – this function is best-effort anyway. Ok(PathBuf::from(OsStr::from_bytes(argv0))) } } @@ -272,10 +282,10 @@ pub fn current_exe() -> io::Result { } } -#[cfg(target_os = "nto")] +#[cfg(any(target_os = "nto", target_os = "qnx"))] pub fn current_exe() -> io::Result { let mut e = crate::fs::read("/proc/self/exefile")?; - // Current versions of QNX Neutrino provide a null-terminated path. + // Current versions of QNX SDP provide a null-terminated path. // Ensure the trailing null byte is not returned here. if let Some(0) = e.last() { e.pop(); @@ -375,7 +385,7 @@ pub fn current_exe() -> io::Result { #[cfg(any(target_os = "espidf", target_os = "horizon", target_os = "vita"))] pub fn current_exe() -> io::Result { - super::unsupported::unsupported() + crate::sys::pal::unsupported() } #[cfg(target_os = "fuchsia")] @@ -396,81 +406,21 @@ pub fn current_exe() -> io::Result { if !path.is_absolute() { getcwd().map(|cwd| cwd.join(path)) } else { Ok(path) } } -#[cfg(not(target_os = "espidf"))] -pub fn page_size() -> usize { - unsafe { libc::sysconf(libc::_SC_PAGESIZE) as usize } -} - -// Returns the value for [`confstr(key, ...)`][posix_confstr]. Currently only -// used on Darwin, but should work on any unix (in case we need to get -// `_CS_PATH` or `_CS_V[67]_ENV` in the future). -// -// [posix_confstr]: -// https://pubs.opengroup.org/onlinepubs/9699919799/functions/confstr.html -// -// FIXME: Support `confstr` in Miri. -#[cfg(all(target_vendor = "apple", not(miri)))] -fn confstr(key: c_int, size_hint: Option) -> io::Result { - let mut buf: Vec = Vec::with_capacity(0); - let mut bytes_needed_including_nul = size_hint - .unwrap_or_else(|| { - // Treat "None" as "do an extra call to get the length". In theory - // we could move this into the loop below, but it's hard to do given - // that it isn't 100% clear if it's legal to pass 0 for `len` when - // the buffer isn't null. - unsafe { libc::confstr(key, core::ptr::null_mut(), 0) } - }) - .max(1); - // If the value returned by `confstr` is greater than the len passed into - // it, then the value was truncated, meaning we need to retry. Note that - // while `confstr` results don't seem to change for a process, it's unclear - // if this is guaranteed anywhere, so looping does seem required. - while bytes_needed_including_nul > buf.capacity() { - // We write into the spare capacity of `buf`. This lets us avoid - // changing buf's `len`, which both simplifies `reserve` computation, - // allows working with `Vec` instead of `Vec>`, and - // may avoid a copy, since the Vec knows that none of the bytes are needed - // when reallocating (well, in theory anyway). - buf.reserve(bytes_needed_including_nul); - // `confstr` returns - // - 0 in the case of errors: we break and return an error. - // - The number of bytes written, iff the provided buffer is enough to - // hold the entire value: we break and return the data in `buf`. - // - Otherwise, the number of bytes needed (including nul): we go - // through the loop again. - bytes_needed_including_nul = - unsafe { libc::confstr(key, buf.as_mut_ptr().cast::(), buf.capacity()) }; - } - // `confstr` returns 0 in the case of an error. - if bytes_needed_including_nul == 0 { - return Err(io::Error::last_os_error()); - } - // Safety: `confstr(..., buf.as_mut_ptr(), buf.capacity())` returned a - // non-zero value, meaning `bytes_needed_including_nul` bytes were - // initialized. - unsafe { - buf.set_len(bytes_needed_including_nul); - // Remove the NUL-terminator. - let last_byte = buf.pop(); - // ... and smoke-check that it *was* a NUL-terminator. - assert_eq!(last_byte, Some(0), "`confstr` provided a string which wasn't nul-terminated"); - }; - Ok(OsString::from_vec(buf)) -} - -#[cfg(all(target_vendor = "apple", not(miri)))] +#[cfg(target_vendor = "apple")] fn darwin_temp_dir() -> PathBuf { - confstr(libc::_CS_DARWIN_USER_TEMP_DIR, Some(64)).map(PathBuf::from).unwrap_or_else(|_| { - // It failed for whatever reason (there are several possible reasons), - // so return the global one. - PathBuf::from("/tmp") - }) + crate::sys::pal::conf::confstr(libc::_CS_DARWIN_USER_TEMP_DIR, Some(64)) + .map(PathBuf::from) + .unwrap_or_else(|_| { + // It failed for whatever reason (there are several possible reasons), + // so return the global one. + PathBuf::from("/tmp") + }) } pub fn temp_dir() -> PathBuf { crate::env::var_os("TMPDIR").map(PathBuf::from).unwrap_or_else(|| { cfg_select! { - all(target_vendor = "apple", not(miri)) => darwin_temp_dir(), + target_vendor = "apple" => darwin_temp_dir(), target_os = "android" => PathBuf::from("/data/local/tmp"), _ => PathBuf::from("/tmp"), } @@ -532,40 +482,3 @@ pub fn home_dir() -> Option { } } } - -pub fn exit(code: i32) -> ! { - crate::sys::exit_guard::unique_thread_exit(); - unsafe { libc::exit(code as c_int) } -} - -pub fn getpid() -> u32 { - unsafe { libc::getpid() as u32 } -} - -pub fn getppid() -> u32 { - unsafe { libc::getppid() as u32 } -} - -#[cfg(all(target_os = "linux", target_env = "gnu"))] -pub fn glibc_version() -> Option<(usize, usize)> { - unsafe extern "C" { - fn gnu_get_libc_version() -> *const libc::c_char; - } - let version_cstr = unsafe { CStr::from_ptr(gnu_get_libc_version()) }; - if let Ok(version_str) = version_cstr.to_str() { - parse_glibc_version(version_str) - } else { - None - } -} - -// Returns Some((major, minor)) if the string is a valid "x.y" version, -// ignoring any extra dot-separated parts. Otherwise return None. -#[cfg(all(target_os = "linux", target_env = "gnu"))] -fn parse_glibc_version(version: &str) -> Option<(usize, usize)> { - let mut parsed_ints = version.split('.').map(str::parse::).fuse(); - match (parsed_ints.next(), parsed_ints.next()) { - (Some(Ok(major)), Some(Ok(minor))) => Some((major, minor)), - _ => None, - } -} diff --git a/library/std/src/sys/pal/zkvm/os.rs b/library/std/src/sys/paths/unsupported.rs similarity index 87% rename from library/std/src/sys/pal/zkvm/os.rs rename to library/std/src/sys/paths/unsupported.rs index cb925ef4348db..024830a254fd7 100644 --- a/library/std/src/sys/pal/zkvm/os.rs +++ b/library/std/src/sys/paths/unsupported.rs @@ -1,7 +1,7 @@ -use super::unsupported; use crate::ffi::{OsStr, OsString}; use crate::marker::PhantomData; use crate::path::{self, PathBuf}; +use crate::sys::pal::unsupported; use crate::{fmt, io}; pub fn getcwd() -> io::Result { @@ -55,11 +55,3 @@ pub fn temp_dir() -> PathBuf { pub fn home_dir() -> Option { None } - -pub fn exit(_code: i32) -> ! { - crate::intrinsics::abort() -} - -pub fn getpid() -> u32 { - panic!("no pids on this platform") -} diff --git a/library/std/src/sys/paths/wasi.rs b/library/std/src/sys/paths/wasi.rs new file mode 100644 index 0000000000000..1e1f951cd6793 --- /dev/null +++ b/library/std/src/sys/paths/wasi.rs @@ -0,0 +1,45 @@ +#![forbid(unsafe_op_in_unsafe_fn)] + +use crate::ffi::{CStr, OsString}; +use crate::io; +use crate::os::wasi::prelude::*; +use crate::path::{self, PathBuf}; +use crate::sys::helpers::run_path_with_cstr; + +pub fn getcwd() -> io::Result { + let mut buf = Vec::with_capacity(512); + loop { + unsafe { + let ptr = buf.as_mut_ptr() as *mut libc::c_char; + if !libc::getcwd(ptr, buf.capacity()).is_null() { + let len = CStr::from_ptr(buf.as_ptr() as *const libc::c_char).to_bytes().len(); + buf.set_len(len); + buf.shrink_to_fit(); + return Ok(PathBuf::from(OsString::from_vec(buf))); + } else { + let error = io::Error::last_os_error(); + if error.raw_os_error() != Some(libc::ERANGE) { + return Err(error); + } + } + + // Trigger the internal buffer resizing logic of `Vec` by requiring + // more space than the current capacity. + let cap = buf.capacity(); + buf.set_len(cap); + buf.reserve(1); + } + } +} + +pub fn chdir(p: &path::Path) -> io::Result<()> { + let result = run_path_with_cstr(p, &|p| unsafe { Ok(libc::chdir(p.as_ptr())) })?; + match result == (0 as libc::c_int) { + true => Ok(()), + false => Err(io::Error::last_os_error()), + } +} + +pub fn temp_dir() -> PathBuf { + panic!("not supported by WASI yet") +} diff --git a/library/std/src/sys/pal/windows/os.rs b/library/std/src/sys/paths/windows.rs similarity index 85% rename from library/std/src/sys/pal/windows/os.rs rename to library/std/src/sys/paths/windows.rs index 3eb6ec8278401..cfdc93847a97a 100644 --- a/library/std/src/sys/pal/windows/os.rs +++ b/library/std/src/sys/paths/windows.rs @@ -2,17 +2,13 @@ #![allow(nonstandard_style)] -#[cfg(test)] -mod tests; - -use super::api; -#[cfg(not(target_vendor = "uwp"))] -use super::api::WinError; use crate::ffi::{OsStr, OsString}; use crate::os::windows::ffi::EncodeWide; use crate::os::windows::prelude::*; use crate::path::{self, PathBuf}; -use crate::sys::pal::{c, cvt}; +#[cfg(not(target_vendor = "uwp"))] +use crate::sys::pal::api::WinError; +use crate::sys::pal::{api, c, cvt, fill_utf16_buf, os2path}; use crate::{fmt, io, ptr}; pub struct SplitPaths<'a> { @@ -56,11 +52,7 @@ impl<'a> Iterator for SplitPaths<'a> { } } - if !must_yield && in_progress.is_empty() { - None - } else { - Some(super::os2path(&in_progress)) - } + if !must_yield && in_progress.is_empty() { None } else { Some(os2path(&in_progress)) } } } @@ -104,14 +96,11 @@ impl fmt::Display for JoinPathsError { impl crate::error::Error for JoinPathsError {} pub fn current_exe() -> io::Result { - super::fill_utf16_buf( - |buf, sz| unsafe { c::GetModuleFileNameW(ptr::null_mut(), buf, sz) }, - super::os2path, - ) + fill_utf16_buf(|buf, sz| unsafe { c::GetModuleFileNameW(ptr::null_mut(), buf, sz) }, os2path) } pub fn getcwd() -> io::Result { - super::fill_utf16_buf(|buf, sz| unsafe { c::GetCurrentDirectoryW(sz, buf) }, super::os2path) + fill_utf16_buf(|buf, sz| unsafe { c::GetCurrentDirectoryW(sz, buf) }, os2path) } pub fn chdir(p: &path::Path) -> io::Result<()> { @@ -123,7 +112,7 @@ pub fn chdir(p: &path::Path) -> io::Result<()> { } pub fn temp_dir() -> PathBuf { - super::fill_utf16_buf(|buf, sz| unsafe { c::GetTempPath2W(sz, buf) }, super::os2path).unwrap() + fill_utf16_buf(|buf, sz| unsafe { c::GetTempPath2W(sz, buf) }, os2path).unwrap() } #[cfg(all(not(target_vendor = "uwp"), not(target_vendor = "win7")))] @@ -132,7 +121,7 @@ fn home_dir_crt() -> Option { // Defined in processthreadsapi.h. const CURRENT_PROCESS_TOKEN: usize = -4_isize as usize; - super::fill_utf16_buf( + fill_utf16_buf( |buf, mut sz| { // GetUserProfileDirectoryW does not quite use the usual protocol for // negotiating the buffer size, so we have to translate. @@ -146,7 +135,7 @@ fn home_dir_crt() -> Option { _ => sz - 1, // sz includes the null terminator } }, - super::os2path, + os2path, ) .ok() } @@ -163,7 +152,7 @@ fn home_dir_crt() -> Option { return None; } let _handle = Handle::from_raw_handle(token); - super::fill_utf16_buf( + fill_utf16_buf( |buf, mut sz| { match c::GetUserProfileDirectoryW(token, buf, &mut sz) { 0 if api::get_last_error() != WinError::INSUFFICIENT_BUFFER => 0, @@ -171,7 +160,7 @@ fn home_dir_crt() -> Option { _ => sz - 1, // sz includes the null terminator } }, - super::os2path, + os2path, ) .ok() } @@ -188,11 +177,3 @@ pub fn home_dir() -> Option { .map(PathBuf::from) .or_else(home_dir_crt) } - -pub fn exit(code: i32) -> ! { - unsafe { c::ExitProcess(code as u32) } -} - -pub fn getpid() -> u32 { - unsafe { c::GetCurrentProcessId() } -} diff --git a/library/std/src/sys/personality/emcc.rs b/library/std/src/sys/personality/emcc.rs deleted file mode 100644 index d374e3ad4c8f6..0000000000000 --- a/library/std/src/sys/personality/emcc.rs +++ /dev/null @@ -1,21 +0,0 @@ -//! On Emscripten Rust panics are wrapped in C++ exceptions, so we just forward -//! to `__gxx_personality_v0` which is provided by Emscripten. - -use unwind as uw; - -use crate::ffi::c_int; - -// This is required by the compiler to exist (e.g., it's a lang item), but it's -// never actually called by the compiler. Emscripten EH doesn't use a -// personality function at all, it instead uses __cxa_find_matching_catch. -// Wasm error handling would use __gxx_personality_wasm0. -#[lang = "eh_personality"] -unsafe extern "C" fn rust_eh_personality( - _version: c_int, - _actions: uw::_Unwind_Action, - _exception_class: uw::_Unwind_Exception_Class, - _exception_object: *mut uw::_Unwind_Exception, - _context: *mut uw::_Unwind_Context, -) -> uw::_Unwind_Reason_Code { - core::intrinsics::abort() -} diff --git a/library/std/src/sys/personality/gcc.rs b/library/std/src/sys/personality/gcc.rs index 019d5629d6d6e..b2fa38293f4e5 100644 --- a/library/std/src/sys/personality/gcc.rs +++ b/library/std/src/sys/personality/gcc.rs @@ -94,11 +94,7 @@ const UNWIND_DATA_REG: (i32, i32) = (4, 5); // a0, a1 // https://github.com/gcc-mirror/gcc/blob/trunk/libgcc/unwind-c.c cfg_select! { - all( - target_arch = "arm", - not(target_vendor = "apple"), - not(target_os = "netbsd"), - ) => { + all(target_arch = "arm", not(target_vendor = "apple"), not(target_os = "netbsd")) => { /// personality fn called by [ARM EHABI][armeabi-eh] /// /// 32-bit ARM on iOS/tvOS/watchOS does not use ARM EHABI, it uses @@ -138,7 +134,11 @@ cfg_select! { // take only the context pointer, GCC personality routines stash a pointer to // exception_object in the context, using location reserved for ARM's // "scratch register" (r12). - uw::_Unwind_SetGR(context, uw::UNWIND_POINTER_REG, exception_object as uw::_Unwind_Ptr); + uw::_Unwind_SetGR( + context, + uw::UNWIND_POINTER_REG, + exception_object as uw::_Unwind_Ptr, + ); // ...A more principled approach would be to provide the full definition of ARM's // _Unwind_Context in our libunwind bindings and fetch the required data from there // directly, bypassing DWARF compatibility functions. @@ -164,8 +164,12 @@ cfg_select! { } else { match eh_action { EHAction::None => return continue_unwind(exception_object, context), - EHAction::Filter(_) if state & uw::_US_FORCE_UNWIND as c_int != 0 => return continue_unwind(exception_object, context), - EHAction::Cleanup(lpad) | EHAction::Catch(lpad) | EHAction::Filter(lpad) => { + EHAction::Filter(_) if state & uw::_US_FORCE_UNWIND as c_int != 0 => { + return continue_unwind(exception_object, context); + } + EHAction::Cleanup(lpad) + | EHAction::Catch(lpad) + | EHAction::Filter(lpad) => { uw::_Unwind_SetGR( context, UNWIND_DATA_REG.0, @@ -204,6 +208,35 @@ cfg_select! { } } _ => { + #[rustc_force_inline] + unsafe fn sign_lpad(context: *mut uw::_Unwind_Context, lpad: *const u8) -> *const u8 { + cfg_select! { + all(target_abi = "pauthtest", target_arch = "aarch64") => { + // DWARF register number for SP on AArch64. + const SP_REG: i32 = 31; + + unsafe { + let sp = uw::_Unwind_GetGR(context, SP_REG).addr() as u64; + let mut addr = lpad.addr(); + + // `pacib` corresponds to `ptrauth_key_process_dependent_code` in . + core::arch::asm!( + "pacib {addr}, {sp}", + addr = inout(reg) addr, + sp = in(reg) sp, + options(nostack, preserves_flags) + ); + + lpad.with_addr(addr) + } + } + _ => { + let _ = context; + lpad + } + } + } + /// Default personality routine, which is used directly on most targets /// and indirectly on Windows x86_64 and AArch64 via SEH. unsafe extern "C" fn rust_eh_personality_impl( @@ -231,15 +264,16 @@ cfg_select! { match eh_action { EHAction::None => uw::_URC_CONTINUE_UNWIND, // Forced unwinding hits a terminate action. - EHAction::Filter(_) if actions & uw::_UA_FORCE_UNWIND != 0 => uw::_URC_CONTINUE_UNWIND, - EHAction::Cleanup(lpad) | EHAction::Catch(lpad) | EHAction::Filter(lpad) => { - uw::_Unwind_SetGR( - context, - UNWIND_DATA_REG.0, - exception_object.cast(), - ); + EHAction::Filter(_) if actions & uw::_UA_FORCE_UNWIND != 0 => { + uw::_URC_CONTINUE_UNWIND + } + EHAction::Cleanup(lpad) + | EHAction::Catch(lpad) + | EHAction::Filter(lpad) => { + uw::_Unwind_SetGR(context, UNWIND_DATA_REG.0, exception_object.cast()); uw::_Unwind_SetGR(context, UNWIND_DATA_REG.1, core::ptr::null()); - uw::_Unwind_SetIP(context, lpad); + let maybe_signed_lpad = sign_lpad(context, lpad); + uw::_Unwind_SetIP(context, maybe_signed_lpad); uw::_URC_INSTALL_CONTEXT } EHAction::Terminate => uw::_URC_FATAL_PHASE2_ERROR, @@ -250,7 +284,11 @@ cfg_select! { cfg_select! { any( - all(windows, any(target_arch = "aarch64", target_arch = "x86_64"), target_env = "gnu"), + all( + windows, + any(target_arch = "aarch64", target_arch = "x86_64"), + target_env = "gnu" + ), target_os = "cygwin", ) => { /// personality fn called by [Windows Structured Exception Handling][windows-eh] diff --git a/library/std/src/sys/personality/mod.rs b/library/std/src/sys/personality/mod.rs index eabef92244d01..31bd457adbe6b 100644 --- a/library/std/src/sys/personality/mod.rs +++ b/library/std/src/sys/personality/mod.rs @@ -14,10 +14,7 @@ mod dwarf; #[cfg(not(any(test, doctest)))] cfg_select! { - target_os = "emscripten" => { - mod emcc; - } - any(target_env = "msvc", target_family = "wasm", target_os = "motor") => { + any(target_env = "msvc", target_family = "wasm") => { // This is required by the compiler to exist (e.g., it's a lang item), // but it's never actually called by the compiler because // __CxxFrameHandler3 (msvc) / __gxx_wasm_personality_v0 (wasm) is the @@ -33,7 +30,7 @@ cfg_select! { target_os = "psp", target_os = "xous", target_os = "solid_asp3", - all(target_family = "unix", not(target_os = "espidf"), not(target_os = "l4re"), not(target_os = "nuttx")), + all(target_family = "unix", not(target_os = "espidf"), not(target_os = "nuttx")), all(target_vendor = "fortanix", target_env = "sgx"), ) => { mod gcc; @@ -44,6 +41,7 @@ cfg_select! { // - os=uefi // - os=espidf // - os=hermit + // - os=motor // - nvptx64-nvidia-cuda // - arch=avr } diff --git a/library/std/src/sys/pipe/unix.rs b/library/std/src/sys/pipe/unix.rs index bb97e806a0400..86397ecd0badf 100644 --- a/library/std/src/sys/pipe/unix.rs +++ b/library/std/src/sys/pipe/unix.rs @@ -23,22 +23,18 @@ pub fn pipe() -> io::Result<(Pipe, Pipe)> { target_os = "openbsd", target_os = "cygwin", target_os = "redox" - ) => { - unsafe { - cvt(libc::pipe2(fds.as_mut_ptr(), libc::O_CLOEXEC))?; - Ok((Pipe::from_raw_fd(fds[0]), Pipe::from_raw_fd(fds[1]))) - } - } - _ => { - unsafe { - cvt(libc::pipe(fds.as_mut_ptr()))?; + ) => unsafe { + cvt(libc::pipe2(fds.as_mut_ptr(), libc::O_CLOEXEC))?; + Ok((Pipe::from_raw_fd(fds[0]), Pipe::from_raw_fd(fds[1]))) + }, + _ => unsafe { + cvt(libc::pipe(fds.as_mut_ptr()))?; - let fd0 = Pipe::from_raw_fd(fds[0]); - let fd1 = Pipe::from_raw_fd(fds[1]); - fd0.set_cloexec()?; - fd1.set_cloexec()?; - Ok((fd0, fd1)) - } - } + let fd0 = Pipe::from_raw_fd(fds[0]); + let fd1 = Pipe::from_raw_fd(fds[1]); + fd0.set_cloexec()?; + fd1.set_cloexec()?; + Ok((fd0, fd1)) + }, } } diff --git a/library/std/src/sys/pipe/unsupported.rs b/library/std/src/sys/pipe/unsupported.rs index 1c5df47c95817..3b1a71eb3af17 100644 --- a/library/std/src/sys/pipe/unsupported.rs +++ b/library/std/src/sys/pipe/unsupported.rs @@ -17,7 +17,7 @@ impl Pipe { self.0 } - pub fn read_buf(&self, _buf: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, _buf: BorrowedCursor<'_, u8>) -> io::Result<()> { self.0 } diff --git a/library/std/src/sys/platform_version/darwin/mod.rs b/library/std/src/sys/platform_version/darwin/mod.rs index 06b97fcdef4f2..4756716452c88 100644 --- a/library/std/src/sys/platform_version/darwin/mod.rs +++ b/library/std/src/sys/platform_version/darwin/mod.rs @@ -313,17 +313,17 @@ unsafe fn string_version_key( /// Parse an OS version from a bytestring like b"10.1" or b"14.3.7". fn parse_os_version(version: &[u8]) -> Result { if let Some((major, minor)) = version.split_once(|&b| b == b'.') { - let major = u16::from_ascii(major)?; + let major = u16::from_ascii_bytes(major)?; if let Some((minor, patch)) = minor.split_once(|&b| b == b'.') { - let minor = u8::from_ascii(minor)?; - let patch = u8::from_ascii(patch)?; + let minor = u8::from_ascii_bytes(minor)?; + let patch = u8::from_ascii_bytes(patch)?; Ok(pack_os_version(major, minor, patch)) } else { - let minor = u8::from_ascii(minor)?; + let minor = u8::from_ascii_bytes(minor)?; Ok(pack_os_version(major, minor, 0)) } } else { - let major = u16::from_ascii(version)?; + let major = u16::from_ascii_bytes(version)?; Ok(pack_os_version(major, 0, 0)) } } diff --git a/library/std/src/sys/process/env.rs b/library/std/src/sys/process/env.rs index e08b476540ef9..15065c6e2c922 100644 --- a/library/std/src/sys/process/env.rs +++ b/library/std/src/sys/process/env.rs @@ -113,3 +113,34 @@ impl<'a> ExactSizeIterator for CommandEnvs<'a> { self.iter.is_empty() } } + +/// An iterator over the fully resolved environment variables. +/// +/// This struct is created by +/// [`Command::get_resolved_envs`][crate::process::Command::get_resolved_envs]. See its +/// documentation for more. +#[derive(Debug)] +#[must_use = "iterators are lazy and do nothing unless consumed"] +#[unstable(feature = "command_resolved_envs", issue = "149070")] +pub struct CommandResolvedEnvs { + inner: crate::collections::btree_map::IntoIter, +} + +impl CommandResolvedEnvs { + pub(crate) fn new(map: BTreeMap) -> Self { + Self { inner: map.into_iter() } + } +} + +#[unstable(feature = "command_resolved_envs", issue = "149070")] +impl Iterator for CommandResolvedEnvs { + type Item = (OsString, OsString); + + fn next(&mut self) -> Option { + self.inner.next().map(|(key, value)| (key.into(), value)) + } + + fn size_hint(&self) -> (usize, Option) { + self.inner.size_hint() + } +} diff --git a/library/std/src/sys/process/mod.rs b/library/std/src/sys/process/mod.rs index 121d3bc9d5c3c..f46870e0c4042 100644 --- a/library/std/src/sys/process/mod.rs +++ b/library/std/src/sys/process/mod.rs @@ -27,9 +27,15 @@ cfg_select! { mod env; pub use env::CommandEnvs; +#[unstable(feature = "command_resolved_envs", issue = "149070")] +pub use env::CommandResolvedEnvs; +#[cfg(target_os = "linux")] +pub use imp::PidFd; +#[cfg(target_family = "unix")] +pub use imp::getppid; pub use imp::{ ChildPipe, Command, CommandArgs, EnvKey, ExitCode, ExitStatus, ExitStatusError, Process, Stdio, - read_output, + getpid, read_output, }; #[cfg(any( @@ -39,7 +45,8 @@ pub use imp::{ target_os = "espidf", target_os = "horizon", target_os = "vita", - target_os = "nuttx" + target_os = "nuttx", + target_os = "l4re" )) ), target_os = "windows", @@ -77,7 +84,8 @@ pub fn output(cmd: &mut Command) -> crate::io::Result<(ExitStatus, Vec, Vec< target_os = "espidf", target_os = "horizon", target_os = "vita", - target_os = "nuttx" + target_os = "nuttx", + target_os = "l4re" )) ), target_os = "windows", diff --git a/library/std/src/sys/process/motor.rs b/library/std/src/sys/process/motor.rs index a5d0184478904..080da9be3af92 100644 --- a/library/std/src/sys/process/motor.rs +++ b/library/std/src/sys/process/motor.rs @@ -1,5 +1,5 @@ use super::CommandEnvs; -use super::env::CommandEnv; +use super::env::{CommandEnv, CommandResolvedEnvs}; use crate::ffi::OsStr; pub use crate::ffi::OsString as EnvKey; use crate::num::NonZeroI32; @@ -100,6 +100,10 @@ impl Command { self.env.does_clear() } + pub fn get_resolved_envs(&self) -> CommandResolvedEnvs { + CommandResolvedEnvs::new(self.env.capture()) + } + pub fn get_current_dir(&self) -> Option<&Path> { self.cwd.as_ref().map(Path::new) } @@ -327,3 +331,7 @@ pub fn read_output( ) -> io::Result<()> { Err(io::Error::from_raw_os_error(moto_rt::E_NOT_IMPLEMENTED.into())) } + +pub fn getpid() -> u32 { + panic!("Pids on Motor OS are u64.") +} diff --git a/library/std/src/sys/process/uefi.rs b/library/std/src/sys/process/uefi.rs index 31914aeb67c59..e0c4fa579275a 100644 --- a/library/std/src/sys/process/uefi.rs +++ b/library/std/src/sys/process/uefi.rs @@ -1,11 +1,11 @@ use r_efi::protocols::{simple_text_input, simple_text_output}; -use super::env::{CommandEnv, CommandEnvs}; +use super::env::{CommandEnv, CommandEnvs, CommandResolvedEnvs}; use crate::collections::BTreeMap; pub use crate::ffi::OsString as EnvKey; use crate::ffi::{OsStr, OsString}; use crate::num::{NonZero, NonZeroI32}; -use crate::path::Path; +use crate::path::{Path, PathBuf}; use crate::process::StdioPipes; use crate::sys::fs::File; use crate::sys::io::error_string; @@ -27,11 +27,13 @@ pub struct Command { env: CommandEnv, } -#[derive(Copy, Clone, Debug)] +#[derive(Debug)] pub enum Stdio { Inherit, Null, MakePipe, + #[allow(dead_code)] // This variant exists only for the Debug impl + InheritFile(File), } impl Command { @@ -86,6 +88,10 @@ impl Command { self.env.does_clear() } + pub fn get_resolved_envs(&self) -> CommandResolvedEnvs { + CommandResolvedEnvs::new(self.env.capture()) + } + pub fn get_current_dir(&self) -> Option<&Path> { None } @@ -116,6 +122,7 @@ impl Command { ) } .map(Some), + Stdio::InheritFile(_) => Err(unsupported()?), Stdio::Inherit => Ok(None), } } @@ -131,6 +138,7 @@ impl Command { ) } .map(Some), + Stdio::InheritFile(_) => Err(unsupported()?), Stdio::Inherit => Ok(None), Stdio::MakePipe => unsupported(), } @@ -138,7 +146,9 @@ impl Command { } pub fn output(command: &mut Command) -> io::Result<(ExitStatus, Vec, Vec)> { - let mut cmd = uefi_command_internal::Image::load_image(&command.prog)?; + let prog_path = resolve_program(&command.prog) + .ok_or(io::const_error!(io::ErrorKind::NotFound, "could not find the program."))?; + let mut cmd = uefi_command_internal::Image::load_image(prog_path.as_os_str())?; // UEFI adds the bin name by default if !command.args.is_empty() { @@ -147,7 +157,7 @@ pub fn output(command: &mut Command) -> io::Result<(ExitStatus, Vec, Vec } // Setup Stdout - let stdout = command.stdout.unwrap_or(Stdio::MakePipe); + let stdout = command.stdout.take().unwrap_or(Stdio::MakePipe); let stdout = Command::create_pipe(stdout)?; if let Some(con) = stdout { cmd.stdout_init(con) @@ -156,7 +166,7 @@ pub fn output(command: &mut Command) -> io::Result<(ExitStatus, Vec, Vec }; // Setup Stderr - let stderr = command.stderr.unwrap_or(Stdio::MakePipe); + let stderr = command.stderr.take().unwrap_or(Stdio::MakePipe); let stderr = Command::create_pipe(stderr)?; if let Some(con) = stderr { cmd.stderr_init(con) @@ -165,7 +175,7 @@ pub fn output(command: &mut Command) -> io::Result<(ExitStatus, Vec, Vec }; // Setup Stdin - let stdin = command.stdin.unwrap_or(Stdio::Null); + let stdin = command.stdin.take().unwrap_or(Stdio::Null); let stdin = Command::create_stdin(stdin)?; if let Some(con) = stdin { cmd.stdin_init(con) @@ -211,25 +221,19 @@ impl From for Stdio { impl From for Stdio { fn from(_: io::Stdout) -> Stdio { - // FIXME: This is wrong. - // Instead, the Stdio we have here should be a unit struct. - panic!("unsupported") + Stdio::Inherit } } impl From for Stdio { fn from(_: io::Stderr) -> Stdio { - // FIXME: This is wrong. - // Instead, the Stdio we have here should be a unit struct. - panic!("unsupported") + Stdio::Inherit } } impl From for Stdio { - fn from(_file: File) -> Stdio { - // FIXME: This is wrong. - // Instead, the Stdio we have here should be a unit struct. - panic!("unsupported") + fn from(file: File) -> Stdio { + Stdio::InheritFile(file) } } @@ -366,6 +370,36 @@ pub fn read_output( match out.diverge() {} } +// Search for programs similar to UEFI Shell defined in Section 3.6.1. It follows the following flow: +// 1. If program is already absolute path, just check if it exists. +// 2. For non-absolute path, search relative to current directory. +// 3. Search the path list sequentially. +// +// [UEFI Shell Specification](https://uefi.org/sites/default/files/resources/UEFI_Shell_2_2.pdf). +fn resolve_program + ?Sized>(prog: &S) -> Option { + let absolute_prog_path = crate::path::absolute(prog.as_ref()).ok()?; + + match crate::fs::exists(&absolute_prog_path) { + Ok(true) => return Some(absolute_prog_path), + // If program path was already absolute and is not found, then stop. + Ok(false) if Path::new(prog.as_ref()).is_absolute() => return None, + _ => {} + } + + // Search for the program in path. + if let Ok(path_var) = crate::env::var("path") { + for p in crate::env::split_paths(&path_var) { + let temp = p.join(prog.as_ref()); + + if let Ok(true) = crate::fs::exists(&temp) { + return Some(temp); + } + } + } + + None +} + #[allow(dead_code)] mod uefi_command_internal { use r_efi::protocols::{loaded_image, simple_text_input, simple_text_output}; @@ -606,7 +640,7 @@ mod uefi_command_internal { } if let Some((ptr, len)) = self.args { - let _ = unsafe { Box::from_raw(crate::ptr::slice_from_raw_parts_mut(ptr, len)) }; + let _ = unsafe { Box::from_raw(ptr.cast_slice(len)) }; } } } @@ -900,3 +934,7 @@ fn env_changes(env: &CommandEnv) -> Option, O Some(result) } + +pub fn getpid() -> u32 { + panic!("no pids on this platform") +} diff --git a/library/std/src/sys/process/unix/common.rs b/library/std/src/sys/process/unix/common.rs index f6bbfed61ef31..4f281a4d62751 100644 --- a/library/std/src/sys/process/unix/common.rs +++ b/library/std/src/sys/process/unix/common.rs @@ -12,10 +12,10 @@ use crate::path::Path; use crate::process::StdioPipes; use crate::sys::fd::FileDesc; use crate::sys::fs::File; -#[cfg(not(target_os = "fuchsia"))] +#[cfg(not(any(target_os = "fuchsia", target_os = "l4re")))] use crate::sys::fs::OpenOptions; use crate::sys::pipe::pipe; -use crate::sys::process::env::{CommandEnv, CommandEnvs}; +use crate::sys::process::env::{CommandEnv, CommandEnvs, CommandResolvedEnvs}; use crate::sys::{FromInner, IntoInner, cvt_r}; use crate::{fmt, io, mem}; @@ -25,6 +25,9 @@ cfg_select! { target_os = "fuchsia" => { // fuchsia doesn't have /dev/null } + target_os = "l4re" => { + // l4re doesn't have /dev/null + } target_os = "vxworks" => { const DEV_NULL: &CStr = c"/null"; } @@ -48,9 +51,10 @@ cfg_select! { #[allow(dead_code)] pub unsafe fn sigaddset(set: *mut libc::sigset_t, signum: libc::c_int) -> libc::c_int { - use crate::slice; use libc::{c_ulong, sigset_t}; + use crate::slice; + // The implementations from bionic (android libc) type pun `sigset_t` as an // array of `c_ulong`. This works, but lets add a smoke check to make sure // that doesn't change. @@ -75,7 +79,7 @@ cfg_select! { } _ => { #[allow(unused_imports)] - pub use libc::{sigemptyset, sigaddset}; + pub use libc::{sigaddset, sigemptyset}; } } @@ -119,9 +123,9 @@ pub enum ChildStdio { Explicit(c_int), Owned(FileDesc), - // On Fuchsia, null stdio is the default, so we simply don't specify - // any actions at the time of spawning. - #[cfg(target_os = "fuchsia")] + // On Fuchsia and L4Re, null stdio is the default, so we simply don't + // specify any actions at the time of spawning. + #[cfg(any(target_os = "fuchsia", target_os = "l4re"))] Null, } @@ -215,7 +219,7 @@ impl Command { pub fn chroot(&mut self, dir: &Path) { self.chroot = Some(os2c(dir.as_os_str(), &mut self.saw_nul)); if self.cwd.is_none() { - self.cwd(&OsStr::new("/")); + self.cwd(OsStr::new("/")); } } pub fn setsid(&mut self, setsid: bool) { @@ -267,6 +271,10 @@ impl Command { self.env.does_clear() } + pub fn get_resolved_envs(&self) -> CommandResolvedEnvs { + CommandResolvedEnvs::new(self.env.capture()) + } + pub fn get_current_dir(&self) -> Option<&Path> { self.cwd.as_ref().map(|cs| Path::new(OsStr::from_bytes(cs.as_bytes()))) } @@ -423,7 +431,7 @@ impl Stdio { Ok((ChildStdio::Owned(theirs), Some(ours))) } - #[cfg(not(target_os = "fuchsia"))] + #[cfg(not(any(target_os = "fuchsia", target_os = "l4re")))] Stdio::Null => { let mut opts = OpenOptions::new(); opts.read(readable); @@ -432,7 +440,7 @@ impl Stdio { Ok((ChildStdio::Owned(fd.into_inner()), None)) } - #[cfg(target_os = "fuchsia")] + #[cfg(any(target_os = "fuchsia", target_os = "l4re"))] Stdio::Null => Ok((ChildStdio::Null, None)), } } @@ -479,7 +487,7 @@ impl ChildStdio { ChildStdio::Explicit(fd) => Some(fd), ChildStdio::Owned(ref fd) => Some(fd.as_raw_fd()), - #[cfg(target_os = "fuchsia")] + #[cfg(any(target_os = "fuchsia", target_os = "l4re"))] ChildStdio::Null => None, } } @@ -679,3 +687,11 @@ pub fn read_output( } } } + +pub fn getpid() -> u32 { + unsafe { libc::getpid() as u32 } +} + +pub fn getppid() -> u32 { + unsafe { libc::getppid() as u32 } +} diff --git a/library/std/src/sys/process/unix/common/cstring_array.rs b/library/std/src/sys/process/unix/common/cstring_array.rs index 1c840a85df9ba..36202451ba707 100644 --- a/library/std/src/sys/process/unix/common/cstring_array.rs +++ b/library/std/src/sys/process/unix/common/cstring_array.rs @@ -35,10 +35,12 @@ impl CStringArray { /// Push an additional string to the array. pub fn push(&mut self, item: CString) { let argc = self.ptrs.len() - 1; - // Replace the null pointer at the end of the array... - self.ptrs[argc] = item.into_raw(); - // ... and recreate it to restore the data structure invariant. + // Amend the array by another null pointer first, to ensure that the + // array is null-terminated even when the `push` panics, in which case + // the array will be left undisturbed (see #155748). self.ptrs.push(ptr::null()); + // Now, replace the previous null pointer. + self.ptrs[argc] = item.into_raw(); } /// Returns a pointer to the C-string array managed by this type. @@ -91,6 +93,11 @@ pub struct CStringIter<'a> { iter: crate::slice::Iter<'a, *const c_char>, } +// SAFETY: `CStringIter` is basically just a `slice::Iter<&'a CStr>` +unsafe impl Send for CStringIter<'_> {} +// SAFETY: `CStringIter` is basically just a `slice::Iter<&'a CStr>` +unsafe impl Sync for CStringIter<'_> {} + impl<'a> Iterator for CStringIter<'a> { type Item = &'a CStr; fn next(&mut self) -> Option<&'a CStr> { diff --git a/library/std/src/sys/process/unix/common/tests.rs b/library/std/src/sys/process/unix/common/tests.rs index 5f71bf051f8a8..eacb4d2d43122 100644 --- a/library/std/src/sys/process/unix/common/tests.rs +++ b/library/std/src/sys/process/unix/common/tests.rs @@ -19,6 +19,8 @@ macro_rules! t { // newly spawned process may just be raced in the macOS, so to prevent this // test from being flaky we ignore it on macOS. target_os = "macos", + // cat not available + target_os = "l4re", // When run under our current QEMU emulation test suite this test fails, // although the reason isn't very clear as to why. For now this test is // ignored there. @@ -84,6 +86,8 @@ fn test_process_mask() { any( // See test_process_mask target_os = "macos", + // cat not available + target_os = "l4re", target_arch = "arm", target_arch = "aarch64", target_arch = "riscv64", @@ -99,8 +103,13 @@ fn test_process_group_posix_spawn() { cmd.stdout(Stdio::MakePipe); let (mut cat, _pipes) = t!(cmd.spawn(Stdio::Null, true)); + let pid = cat.id() as libc::pid_t; + let pgid = libc::getpgid(pid); + assert_ne!(-1, pgid, "getpgid failed"); + assert_eq!(pid, pgid, "child process ID does not match its process group ID"); + // Check that we can kill its process group, which means there *is* one. - t!(cvt(libc::kill(-(cat.id() as libc::pid_t), libc::SIGINT))); + t!(cvt(libc::kill(-pgid, libc::SIGINT))); t!(cat.wait()); } @@ -111,6 +120,8 @@ fn test_process_group_posix_spawn() { any( // See test_process_mask target_os = "macos", + // cat not available + target_os = "l4re", target_arch = "arm", target_arch = "aarch64", target_arch = "riscv64", @@ -127,8 +138,18 @@ fn test_process_group_no_posix_spawn() { cmd.stdout(Stdio::MakePipe); let (mut cat, _pipes) = t!(cmd.spawn(Stdio::Null, true)); + let pid = cat.id() as libc::pid_t; + let pgid = libc::getpgid(pid); + assert_ne!(-1, pgid, "getpgid failed"); + assert_eq!(pid, pgid, "child process ID does not match its process group ID"); + + if cfg!(target_os = "qnx") { + // kill(-pgid) appears to be unable to terminate the child process on QNX8 + return; + } + // Check that we can kill its process group, which means there *is* one. - t!(cvt(libc::kill(-(cat.id() as libc::pid_t), libc::SIGINT))); + t!(cvt(libc::kill(-pgid, libc::SIGINT))); t!(cat.wait()); } @@ -139,6 +160,8 @@ fn test_process_group_no_posix_spawn() { any( // See test_process_mask target_os = "macos", + // cat not available + target_os = "l4re", target_arch = "arm", target_arch = "aarch64", target_arch = "riscv64", @@ -154,9 +177,19 @@ fn test_setsid_posix_spawn() { let (mut cat, _pipes) = t!(cmd.spawn(Stdio::Null, true)); unsafe { + let pid = cat.id() as libc::pid_t; + let pgid = libc::getpgid(pid); + assert_ne!(-1, pgid, "getpgid failed"); + assert_eq!(pid, pgid, "child process ID does not match its process group ID"); + + if cfg!(target_os = "qnx") { + // kill(-pgid) appears to be unable to terminate the child process on QNX8 + return; + } + // Setsid will create a new session and process group, so check that // we can kill the process group, which means there *is* one. - t!(cvt(libc::kill(-(cat.id() as libc::pid_t), libc::SIGINT))); + t!(cvt(libc::kill(-pgid, libc::SIGINT))); t!(cat.wait()); } @@ -167,6 +200,8 @@ fn test_setsid_posix_spawn() { any( // See test_process_mask target_os = "macos", + // cat not available + target_os = "l4re", target_arch = "arm", target_arch = "aarch64", target_arch = "riscv64", @@ -184,9 +219,19 @@ fn test_setsid_no_posix_spawn() { cmd.pre_exec(Box::new(|| Ok(()))); // pre_exec forces fork + exec rather than posix spawn. let (mut cat, _pipes) = t!(cmd.spawn(Stdio::Null, true)); + let pid = cat.id() as libc::pid_t; + let pgid = libc::getpgid(pid); + assert_ne!(-1, pgid, "getpgid failed"); + assert_eq!(pid, pgid, "child process ID does not match its process group ID"); + + if cfg!(target_os = "qnx") { + // kill(-pgid) appears to be unable to terminate the child process on QNX8 + return; + } + // Setsid will create a new session and process group, so check that // we can kill the process group, which means there *is* one. - t!(cvt(libc::kill(-(cat.id() as libc::pid_t), libc::SIGINT))); + t!(cvt(libc::kill(-pgid, libc::SIGINT))); t!(cat.wait()); } diff --git a/library/std/src/sys/process/unix/fuchsia.rs b/library/std/src/sys/process/unix/fuchsia.rs index 3fae5ec1468b1..65ef7bf8c60c8 100644 --- a/library/std/src/sys/process/unix/fuchsia.rs +++ b/library/std/src/sys/process/unix/fuchsia.rs @@ -158,6 +158,11 @@ impl Process { unimplemented!() } + pub fn send_process_group_signal(&self, _signal: i32) -> io::Result<()> { + // Fuchsia doesn't have a direct equivalent for signals + unimplemented!() + } + pub fn wait(&mut self) -> io::Result { let mut proc_info: zx_info_process_t = Default::default(); let mut actual: size_t = 0; diff --git a/library/std/src/sys/process/unix/mod.rs b/library/std/src/sys/process/unix/mod.rs index 1938e8f4b737c..f56163757c0ef 100644 --- a/library/std/src/sys/process/unix/mod.rs +++ b/library/std/src/sys/process/unix/mod.rs @@ -1,4 +1,7 @@ -#[cfg_attr(any(target_os = "espidf", target_os = "horizon", target_os = "nuttx"), allow(unused))] +#[cfg_attr( + any(target_os = "espidf", target_os = "horizon", target_os = "nuttx", target_os = "l4re"), + allow(unused) +)] mod common; cfg_select! { @@ -10,7 +13,13 @@ cfg_select! { mod vxworks; use vxworks as imp; } - any(target_os = "espidf", target_os = "horizon", target_os = "vita", target_os = "nuttx") => { + any( + target_os = "espidf", + target_os = "horizon", + target_os = "vita", + target_os = "nuttx", + target_os = "l4re" + ) => { mod unsupported; use unsupported as imp; pub use unsupported::output; @@ -21,7 +30,14 @@ cfg_select! { } } +#[cfg(target_os = "linux")] +mod pidfd; + pub use imp::{ExitStatus, ExitStatusError, Process}; +#[cfg(target_os = "linux")] +pub use pidfd::PidFd; -pub use self::common::{ChildPipe, Command, CommandArgs, ExitCode, Stdio, read_output}; +pub use self::common::{ + ChildPipe, Command, CommandArgs, ExitCode, Stdio, getpid, getppid, read_output, +}; pub use crate::ffi::OsString as EnvKey; diff --git a/library/std/src/sys/pal/unix/linux/pidfd.rs b/library/std/src/sys/process/unix/pidfd.rs similarity index 83% rename from library/std/src/sys/pal/unix/linux/pidfd.rs rename to library/std/src/sys/process/unix/pidfd.rs index 671046949aa16..c586354861dcd 100644 --- a/library/std/src/sys/pal/unix/linux/pidfd.rs +++ b/library/std/src/sys/process/unix/pidfd.rs @@ -1,14 +1,14 @@ +use super::ExitStatus; use crate::io; use crate::os::fd::{AsRawFd, FromRawFd, IntoRawFd, RawFd}; use crate::sys::fd::FileDesc; -use crate::sys::process::ExitStatus; -use crate::sys::{AsInner, FromInner, IntoInner, cvt}; +use crate::sys::{AsInner, FromInner, IntoInner, cvt, cvt_r}; #[cfg(test)] mod tests; #[derive(Debug)] -pub(crate) struct PidFd(FileDesc); +pub struct PidFd(FileDesc); impl PidFd { pub fn kill(&self) -> io::Result<()> { @@ -16,14 +16,14 @@ impl PidFd { } #[cfg(any(test, target_env = "gnu", target_env = "musl"))] - pub(crate) fn current_process() -> io::Result { + pub fn current_process() -> io::Result { let pid = crate::process::id(); let pidfd = cvt(unsafe { libc::syscall(libc::SYS_pidfd_open, pid, 0) })?; Ok(unsafe { PidFd::from_raw_fd(pidfd as RawFd) }) } #[cfg(any(test, target_env = "gnu", target_env = "musl"))] - pub(crate) fn pid(&self) -> io::Result { + pub fn pid(&self) -> io::Result { use crate::sys::weak::weak; // since kernel 6.13 @@ -61,7 +61,7 @@ impl PidFd { fn waitid(&self, options: libc::c_int) -> io::Result> { let mut siginfo: libc::siginfo_t = unsafe { crate::mem::zeroed() }; - let r = cvt(unsafe { + let r = cvt_r(|| unsafe { libc::waitid(libc::P_PIDFD, self.0.as_raw_fd() as u32, &mut siginfo, options) }); match r { @@ -82,7 +82,7 @@ impl PidFd { } } - pub(crate) fn send_signal(&self, signal: i32) -> io::Result<()> { + pub fn send_signal(&self, signal: i32) -> io::Result<()> { cvt(unsafe { libc::syscall( libc::SYS_pidfd_send_signal, @@ -95,6 +95,21 @@ impl PidFd { .map(drop) } + pub fn send_process_group_signal(&self, signal: i32) -> io::Result<()> { + // since kernel 6.9 + // https://lore.kernel.org/all/20240210-chihuahua-hinzog-3945b6abd44a@brauner/ + cvt(unsafe { + libc::syscall( + libc::SYS_pidfd_send_signal, + self.0.as_raw_fd(), + signal, + crate::ptr::null::<()>(), + libc::PIDFD_SIGNAL_PROCESS_GROUP, + ) + }) + .map(drop) + } + pub fn wait(&self) -> io::Result { let r = self.waitid(libc::WEXITED)?; match r { diff --git a/library/std/src/sys/pal/unix/linux/pidfd/tests.rs b/library/std/src/sys/process/unix/pidfd/tests.rs similarity index 100% rename from library/std/src/sys/pal/unix/linux/pidfd/tests.rs rename to library/std/src/sys/process/unix/pidfd/tests.rs diff --git a/library/std/src/sys/process/unix/unix.rs b/library/std/src/sys/process/unix/unix.rs index 62d6e0581e6c8..6103fa3576f37 100644 --- a/library/std/src/sys/process/unix/unix.rs +++ b/library/std/src/sys/process/unix/unix.rs @@ -16,22 +16,22 @@ use crate::num::NonZero; use crate::process::StdioPipes; use crate::sys::cvt; #[cfg(target_os = "linux")] -use crate::sys::pal::linux::pidfd::PidFd; +use crate::sys::process::PidFd; use crate::{fmt, mem, sys}; cfg_select! { - target_os = "nto" => { - use crate::thread; + any(target_os = "nto", target_os = "qnx") => { use libc::{c_char, posix_spawn_file_actions_t, posix_spawnattr_t}; - use crate::time::Duration; + use crate::sync::LazyLock; + use crate::thread; + use crate::time::Duration; // Get smallest amount of time we can sleep. // Return a common value if it cannot be determined. fn get_clock_resolution() -> Duration { static MIN_DELAY: LazyLock Duration> = LazyLock::new(|| { let mut mindelay = libc::timespec { tv_sec: 0, tv_nsec: 0 }; - if unsafe { libc::clock_getres(libc::CLOCK_MONOTONIC, &mut mindelay) } == 0 - { + if unsafe { libc::clock_getres(libc::CLOCK_MONOTONIC, &mut mindelay) } == 0 { Duration::from_nanos(mindelay.tv_nsec as u64) } else { Duration::from_millis(1) @@ -183,16 +183,21 @@ impl Command { // Attempts to fork the process. If successful, returns Ok((0, -1)) // in the child, and Ok((child_pid, -1)) in the parent. - #[cfg(not(any(target_os = "watchos", target_os = "tvos", target_os = "nto")))] + #[cfg(not(any( + target_os = "watchos", + target_os = "tvos", + target_os = "nto", + target_os = "qnx" + )))] unsafe fn do_fork(&mut self) -> Result { cvt(libc::fork()) } - // On QNX Neutrino, fork can fail with EBADF in case "another thread might have opened + // On QNX SDP, fork can fail with EBADF in case "another thread might have opened // or closed a file descriptor while the fork() was occurring". // Documentation says "... or try calling fork() again". This is what we do here. - // See also https://www.qnx.com/developers/docs/7.1/#com.qnx.doc.neutrino.lib_ref/topic/f/fork.html - #[cfg(target_os = "nto")] + // See also https://www.qnx.com/developers/docs/7.1/com.qnx.doc.neutrino.lib_ref/topic/f/fork.html + #[cfg(any(target_os = "nto", target_os = "qnx"))] unsafe fn do_fork(&mut self) -> Result { use crate::sys::io::errno; @@ -318,7 +323,7 @@ impl Command { // An alternative would be to require CAP_SETGID (in // addition to CAP_SETUID) for setting the UID. if e.raw_os_error() != Some(libc::EPERM) { - return Err(e.into()); + return Err(e); } } } @@ -356,7 +361,7 @@ impl Command { // If -Zon-broken-pipe is not used, reset SIGPIPE to SIG_DFL for backward compatibility. // // -Zon-broken-pipe is an opportunity to change the default here. - if !crate::sys::pal::on_broken_pipe_flag_used() { + if !crate::sys::pal::on_broken_pipe_used() { #[cfg(target_os = "android")] // see issue #88585 { let mut action: libc::sigaction = mem::zeroed(); @@ -424,6 +429,7 @@ impl Command { all(target_os = "linux", target_env = "gnu"), all(target_os = "linux", target_env = "musl"), target_os = "nto", + target_os = "qnx", target_vendor = "apple", target_os = "cygwin", )))] @@ -443,6 +449,7 @@ impl Command { all(target_os = "linux", target_env = "gnu"), all(target_os = "linux", target_env = "musl"), target_os = "nto", + target_os = "qnx", target_vendor = "apple", target_os = "cygwin", ))] @@ -455,7 +462,7 @@ impl Command { use core::sync::atomic::{Atomic, AtomicU8, Ordering}; use crate::mem::MaybeUninit; - use crate::sys::{self, cvt_nz, on_broken_pipe_flag_used}; + use crate::sys::{self, cvt_nz, on_broken_pipe_used}; if self.get_gid().is_some() || self.get_uid().is_some() @@ -505,15 +512,22 @@ impl Command { support = FORK_EXEC; // but for the fast path we need both spawnp and the // pidfd -> pid conversion to work. - if pidfd_spawnp.get().is_some() && let Ok(pid) = pidfd.pid() { + if pidfd_spawnp.get().is_some() + && let Ok(pid) = pidfd.pid() + { assert_eq!(pid, crate::process::id(), "sanity check"); support = SPAWN; } } - Err(e) if e.raw_os_error() == Some(libc::EMFILE) => { - // We're temporarily(?) out of file descriptors. In this case pidfd_spawnp would also fail + Err(e) + if matches!( + e.raw_os_error(), + Some(libc::EMFILE | libc::ENFILE | libc::ENOMEM) + ) => + { + // We're temporarily(?) out of file descriptors or memory. In this case pidfd_spawnp would also fail // Don't update the support flag so we can probe again later. - return Err(e) + return Err(e); } _ => { // pidfd_open not available? likely an old kernel without pidfd support. @@ -537,7 +551,7 @@ impl Command { // Only glibc 2.24+ posix_spawn() supports returning ENOENT directly. #[cfg(all(target_os = "linux", target_env = "gnu"))] { - if let Some(version) = sys::os::glibc_version() { + if let Some(version) = sys::pal::conf::glibc_version() { if version < (2, 24) { return Ok(None); } @@ -546,11 +560,11 @@ impl Command { } } - // On QNX Neutrino, posix_spawnp can fail with EBADF in case "another thread might have opened + // On QNX SDP, posix_spawnp can fail with EBADF in case "another thread might have opened // or closed a file descriptor while the posix_spawn() was occurring". // Documentation says "... or try calling posix_spawn() again". This is what we do here. - // See also http://www.qnx.com/developers/docs/7.1/#com.qnx.doc.neutrino.lib_ref/topic/p/posix_spawn.html - #[cfg(target_os = "nto")] + // See also https://www.qnx.com/developers/docs/7.1/com.qnx.doc.neutrino.lib_ref/topic/p/posix_spawn.html + #[cfg(any(target_os = "nto", target_os = "qnx"))] unsafe fn retrying_libc_posix_spawnp( pid: *mut pid_t, file: *const c_char, @@ -731,7 +745,7 @@ impl Command { // If -Zon-broken-pipe is not used, reset SIGPIPE to SIG_DFL for backward compatibility. // // -Zon-broken-pipe is an opportunity to change the default here. - if !on_broken_pipe_flag_used() { + if !on_broken_pipe_used() { let mut default_set = MaybeUninit::::uninit(); cvt(sigemptyset(default_set.as_mut_ptr()))?; cvt(sigaddset(default_set.as_mut_ptr(), libc::SIGPIPE))?; @@ -749,7 +763,7 @@ impl Command { if self.get_setsid() { cfg_select! { all(target_os = "linux", target_env = "gnu") => { - flags |= libc::POSIX_SPAWN_SETSID; + flags |= libc::POSIX_SPAWN_SETSID as i32; } _ => { return Ok(None); @@ -763,9 +777,9 @@ impl Command { let _env_lock = sys::env::env_read_lock(); let envp = envp.map(|c| c.as_ptr()).unwrap_or_else(|| *sys::env::environ() as *const _); - #[cfg(not(target_os = "nto"))] + #[cfg(not(any(target_os = "nto", target_os = "qnx")))] let spawn_fn = libc::posix_spawnp; - #[cfg(target_os = "nto")] + #[cfg(any(target_os = "nto", target_os = "qnx"))] let spawn_fn = retrying_libc_posix_spawnp; #[cfg(target_os = "linux")] @@ -822,7 +836,7 @@ impl Command { envp as *const _, ); - #[cfg(target_os = "nto")] + #[cfg(any(target_os = "nto", target_os = "qnx"))] let spawn_res = spawn_res?; cvt_nz(spawn_res)?; @@ -881,7 +895,7 @@ impl Command { // we send the 0-length message even if we failed to acquire the pidfd // so we get a consistent SEQPACKET order - match cvt_r(|| libc::sendmsg(sock.as_raw(), &msg, 0)) { + match cvt_r(|| libc::sendmsg(sock.as_raw(), &msg, libc::MSG_EOR)) { Ok(0) => {} other => rtabort!("failed to communicate with parent process. {:?}", other), } @@ -1002,6 +1016,19 @@ impl Process { cvt(unsafe { libc::kill(self.pid, signal) }).map(drop) } + pub(crate) fn send_process_group_signal(&self, signal: i32) -> io::Result<()> { + // See note in `send_signal` regarding recycled PIDs. + if self.status.is_some() { + return Ok(()); + } + #[cfg(target_os = "linux")] + if let Some(pid_fd) = self.pidfd.as_ref() { + // The `PIDFD_SIGNAL_PROCESS_GROUP` flag requires kernel >= 6.9 + return pid_fd.send_process_group_signal(signal); + } + cvt(unsafe { libc::killpg(self.pid, signal) }).map(drop) + } + pub fn wait(&mut self) -> io::Result { use crate::sys::cvt_r; if let Some(status) = self.status { @@ -1081,7 +1108,7 @@ impl ExitStatus { pub fn exit_ok(&self) -> Result<(), ExitStatusError> { // This assumes that WIFEXITED(status) && WEXITSTATUS==0 corresponds to status==0. This is // true on all actual versions of Unix, is widely assumed, and is specified in SuS - // https://pubs.opengroup.org/onlinepubs/9699919799/functions/wait.html. If it is not + // https://pubs.opengroup.org/onlinepubs/9799919799/functions/wait.html. If it is not // true for a platform pretending to be Unix, the tests (our doctests, and also // unix/tests.rs) will spot it. `ExitStatusError::code` assumes this too. match NonZero::try_from(self.0) { @@ -1189,7 +1216,12 @@ fn signal_string(signal: i32) -> &'static str { ) ))] libc::SIGSTKFLT => " (SIGSTKFLT)", - #[cfg(any(target_os = "linux", target_os = "nto", target_os = "cygwin"))] + #[cfg(any( + target_os = "linux", + target_os = "nto", + target_os = "qnx", + target_os = "cygwin" + ))] libc::SIGPWR => " (SIGPWR)", #[cfg(any( target_os = "freebsd", @@ -1197,6 +1229,7 @@ fn signal_string(signal: i32) -> &'static str { target_os = "openbsd", target_os = "dragonfly", target_os = "nto", + target_os = "qnx", target_vendor = "apple", target_os = "cygwin", ))] @@ -1266,8 +1299,7 @@ impl ExitStatusError { mod linux_child_ext { use crate::io::ErrorKind; use crate::os::linux::process as os; - use crate::sys::FromInner; - use crate::sys::pal::linux::pidfd as imp; + use crate::sys::{FromInner, process as imp}; use crate::{io, mem}; #[unstable(feature = "linux_pidfd", issue = "82971")] diff --git a/library/std/src/sys/process/unix/unix/tests.rs b/library/std/src/sys/process/unix/unix/tests.rs index 663ba61f966c9..9a029f16a3a20 100644 --- a/library/std/src/sys/process/unix/unix/tests.rs +++ b/library/std/src/sys/process/unix/unix/tests.rs @@ -51,7 +51,10 @@ fn exitstatus_display_tests() { #[test] #[cfg_attr(target_os = "emscripten", ignore)] -#[cfg_attr(any(target_os = "tvos", target_os = "watchos"), ignore = "fork is prohibited")] +#[cfg_attr( + any(target_os = "tvos", target_os = "watchos", target_os = "l4re"), + ignore = "fork is prohibited" +)] fn test_command_fork_no_unwind() { let got = catch_unwind(|| { let mut c = Command::new("echo"); diff --git a/library/std/src/sys/process/unix/unsupported.rs b/library/std/src/sys/process/unix/unsupported.rs index 9bda394f24659..2235ec1f1c3b6 100644 --- a/library/std/src/sys/process/unix/unsupported.rs +++ b/library/std/src/sys/process/unix/unsupported.rs @@ -4,7 +4,7 @@ use super::common::*; use crate::io; use crate::num::NonZero; use crate::process::StdioPipes; -use crate::sys::pal::unsupported::*; +use crate::sys::pal::{unsupported, unsupported_err}; //////////////////////////////////////////////////////////////////////////////// // Command @@ -49,6 +49,10 @@ impl Process { unsupported() } + pub fn send_process_group_signal(&self, _signal: i32) -> io::Result<()> { + unsupported() + } + pub fn wait(&mut self) -> io::Result { unsupported() } diff --git a/library/std/src/sys/process/unix/unsupported/wait_status.rs b/library/std/src/sys/process/unix/unsupported/wait_status.rs index f348d557e4b7e..ac54824875813 100644 --- a/library/std/src/sys/process/unix/unsupported/wait_status.rs +++ b/library/std/src/sys/process/unix/unsupported/wait_status.rs @@ -46,7 +46,7 @@ impl ExitStatus { pub fn exit_ok(&self) -> Result<(), ExitStatusError> { // This assumes that WIFEXITED(status) && WEXITSTATUS==0 corresponds to status==0. This is // true on all actual versions of Unix, is widely assumed, and is specified in SuS - // https://pubs.opengroup.org/onlinepubs/9699919799/functions/wait.html. If it is not + // https://pubs.opengroup.org/onlinepubs/9799919799/functions/wait.html. If it is not // true for a platform pretending to be Unix, the tests (our doctests, and also // unix/tests.rs) will spot it. `ExitStatusError::code` assumes this too. match NonZero::try_from(self.wait_status) { diff --git a/library/std/src/sys/process/unix/unsupported/wait_status/tests.rs b/library/std/src/sys/process/unix/unsupported/wait_status/tests.rs index 0d9232fac5e4e..51af14f0aaace 100644 --- a/library/std/src/sys/process/unix/unsupported/wait_status/tests.rs +++ b/library/std/src/sys/process/unix/unsupported/wait_status/tests.rs @@ -8,6 +8,7 @@ // I.e. we're using Linux as a proxy for "trad unix". #[cfg(target_os = "linux")] #[test] +#[cfg_attr(miri, ignore)] // Miri is too slow fn compare_with_linux() { use super::ExitStatus as Emulated; use crate::os::unix::process::ExitStatusExt as _; diff --git a/library/std/src/sys/process/unix/vxworks.rs b/library/std/src/sys/process/unix/vxworks.rs index 346ca6d74c9bd..18b9782f40230 100644 --- a/library/std/src/sys/process/unix/vxworks.rs +++ b/library/std/src/sys/process/unix/vxworks.rs @@ -124,7 +124,17 @@ impl Command { Ok(t) => unsafe { let mut status = 0 as c_int; libc::waitpid(t.0.pid, &mut status, 0); - libc::exit(0); + // If the task was killed by a signal, terminate the same way by + // restoring the default disposition and resending it to ourselves. + if libc::WIFSIGNALED(status) { + let signal = libc::WTERMSIG(status); + libc::signal(signal, libc::SIG_DFL); + libc::kill(libc::getpid(), signal); + // The signal should have already terminated us; abort if it + // was blocked or ignored. + libc::abort(); + } + libc::exit(libc::WEXITSTATUS(status)); }, Err(e) => e, } @@ -161,6 +171,11 @@ impl Process { } } + pub fn send_process_group_signal(&self, _signal: i32) -> io::Result<()> { + // VxWorks doesn't have process groups + unimplemented!() + } + pub fn wait(&mut self) -> io::Result { use crate::sys::cvt_r; if let Some(status) = self.status { @@ -203,7 +218,7 @@ impl ExitStatus { pub fn exit_ok(&self) -> Result<(), ExitStatusError> { // This assumes that WIFEXITED(status) && WEXITSTATUS==0 corresponds to status==0. This is // true on all actual versions of Unix, is widely assumed, and is specified in SuS - // https://pubs.opengroup.org/onlinepubs/9699919799/functions/wait.html. If it is not + // https://pubs.opengroup.org/onlinepubs/9799919799/functions/wait.html. If it is not // true for a platform pretending to be Unix, the tests (our doctests, and also // unix/tests.rs) will spot it. `ExitStatusError::code` assumes this too. match NonZero::try_from(self.0) { diff --git a/library/std/src/sys/process/unsupported.rs b/library/std/src/sys/process/unsupported.rs index 455c38e55b7ba..f7d7f489ec079 100644 --- a/library/std/src/sys/process/unsupported.rs +++ b/library/std/src/sys/process/unsupported.rs @@ -1,4 +1,4 @@ -use super::env::{CommandEnv, CommandEnvs}; +use super::env::{CommandEnv, CommandEnvs, CommandResolvedEnvs}; pub use crate::ffi::OsString as EnvKey; use crate::ffi::{OsStr, OsString}; use crate::num::NonZero; @@ -89,6 +89,10 @@ impl Command { self.env.does_clear() } + pub fn get_resolved_envs(&self) -> CommandResolvedEnvs { + CommandResolvedEnvs::new(self.env.capture()) + } + pub fn get_current_dir(&self) -> Option<&Path> { self.cwd.as_ref().map(|cs| Path::new(cs)) } @@ -195,7 +199,6 @@ impl fmt::Debug for Command { } #[derive(PartialEq, Eq, Clone, Copy, Debug, Default)] -#[non_exhaustive] pub struct ExitStatus(); impl ExitStatus { @@ -327,3 +330,7 @@ pub fn read_output( ) -> io::Result<()> { match out.diverge() {} } + +pub fn getpid() -> u32 { + panic!("no pids on this platform") +} diff --git a/library/std/src/sys/process/windows.rs b/library/std/src/sys/process/windows.rs index b40833ad212c4..0cff0fb7945c4 100644 --- a/library/std/src/sys/process/windows.rs +++ b/library/std/src/sys/process/windows.rs @@ -5,7 +5,7 @@ mod tests; use core::ffi::c_void; -use super::env::{CommandEnv, CommandEnvs}; +use super::env::{CommandEnv, CommandEnvs, CommandResolvedEnvs}; use crate::collections::BTreeMap; use crate::env::consts::{EXE_EXTENSION, EXE_SUFFIX}; use crate::ffi::{OsStr, OsString}; @@ -256,6 +256,10 @@ impl Command { self.env.does_clear() } + pub fn get_resolved_envs(&self) -> CommandResolvedEnvs { + CommandResolvedEnvs::new(self.env.capture()) + } + pub fn get_current_dir(&self) -> Option<&Path> { self.cwd.as_ref().map(Path::new) } @@ -636,7 +640,24 @@ impl Stdio { opts.read(stdio_id == c::STD_INPUT_HANDLE); opts.write(stdio_id != c::STD_INPUT_HANDLE); opts.inherit_handle(true); - File::open(Path::new(r"\\.\NUL"), &opts).map(|file| file.into_inner()) + File::open(Path::new(r"\\.\NUL"), &opts).map(|file| file.into_inner()).map_err( + |e| { + // A raw `NotFound` here is easily mistaken for the program + // being missing, so say what actually failed to open. + // `spawn` only passes the three standard ids, but print + // anything else as a number rather than mislabeling it. + let stream = match stdio_id { + c::STD_INPUT_HANDLE => "stdin".to_string(), + c::STD_OUTPUT_HANDLE => "stdout".to_string(), + c::STD_ERROR_HANDLE => "stderr".to_string(), + id => format!("stdio handle {id}"), + }; + Error::new( + e.kind(), + format!("failed to open NUL device for child {stream}: {e}"), + ) + }, + ) } } } @@ -976,3 +997,7 @@ impl<'a> fmt::Debug for CommandArgs<'a> { f.debug_list().entries(self.iter.clone()).finish() } } + +pub fn getpid() -> u32 { + unsafe { c::GetCurrentProcessId() } +} diff --git a/library/std/src/sys/process/windows/child_pipe.rs b/library/std/src/sys/process/windows/child_pipe.rs index da7a86ca072e3..9ac024c45b917 100644 --- a/library/std/src/sys/process/windows/child_pipe.rs +++ b/library/std/src/sys/process/windows/child_pipe.rs @@ -1,6 +1,8 @@ use crate::io::{self, BorrowedCursor, IoSlice, IoSliceMut}; use crate::ops::Neg; use crate::os::windows::prelude::*; +use crate::sync::atomic::Atomic; +use crate::sync::atomic::Ordering::Relaxed; use crate::sys::handle::Handle; use crate::sys::{FromInner, IntoInner, api, c}; use crate::{mem, ptr}; @@ -70,10 +72,19 @@ pub(super) fn child_pipe(ours_readable: bool, their_handle_inheritable: bool) -> let mut object_attributes = c::OBJECT_ATTRIBUTES::default(); object_attributes.Length = size_of::() as u32; - // Open a handle to the pipe filesystem (`\??\PIPE\`). - // This will be used when creating a new annon pipe. - let pipe_fs = { - let path = api::unicode_str!(r"\??\PIPE\"); + // Open a handle to the pipe filesystem (`\Device\NamedPipe\`). + // This will be used when creating a new anonymous pipe. + // + // We cache the handle once so we can reuse it without needing to reopen it each time. + // NOTE: this means the handle may appear to be leaked but that's fine because + // it's only one handle and the OS will clean it up when the process exits. + static PIPE_FS: Atomic = Atomic::::new(ptr::null_mut()); + let pipe_fs = if let handle = PIPE_FS.load(Relaxed) + && !handle.is_null() + { + handle + } else { + let path = api::unicode_str!(r"\Device\NamedPipe\"); object_attributes.ObjectName = path.as_ptr(); let mut pipe_fs = ptr::null_mut(); let status = c::NtOpenFile( @@ -85,7 +96,13 @@ pub(super) fn child_pipe(ours_readable: bool, their_handle_inheritable: bool) -> c::FILE_SYNCHRONOUS_IO_NONALERT, // synchronous access ); if c::nt_success(status) { - Handle::from_raw_handle(pipe_fs) + match PIPE_FS.compare_exchange(ptr::null_mut(), pipe_fs, Relaxed, Relaxed) { + Ok(_) => pipe_fs, + Err(existing) => { + c::CloseHandle(pipe_fs); + existing + } + } } else { return Err(io::Error::from_raw_os_error(c::RtlNtStatusToDosError(status) as i32)); } @@ -104,7 +121,7 @@ pub(super) fn child_pipe(ours_readable: bool, their_handle_inheritable: bool) -> let ours = { // Use the pipe filesystem as the root directory. // With no name provided, an anonymous pipe will be created. - object_attributes.RootDirectory = pipe_fs.as_raw_handle(); + object_attributes.RootDirectory = pipe_fs; // A negative timeout value is a relative time (rather than an absolute time). // The time is given in 100's of nanoseconds so this is 50 milliseconds. @@ -242,7 +259,7 @@ impl ChildPipe { } } - pub fn read_buf(&self, mut buf: BorrowedCursor<'_>) -> io::Result<()> { + pub fn read_buf(&self, mut buf: BorrowedCursor<'_, u8>) -> io::Result<()> { let result = unsafe { let len = crate::cmp::min(buf.capacity(), u32::MAX as usize) as u32; let ptr = buf.as_mut().as_mut_ptr().cast::(); @@ -260,7 +277,7 @@ impl ChildPipe { Err(e) => Err(e), Ok(n) => { unsafe { - buf.advance_unchecked(n); + buf.advance(n); } Ok(()) } diff --git a/library/std/src/sys/random/arc4random.rs b/library/std/src/sys/random/arc4random.rs index e1957bceb9002..92e7fbaf87d76 100644 --- a/library/std/src/sys/random/arc4random.rs +++ b/library/std/src/sys/random/arc4random.rs @@ -3,28 +3,17 @@ //! Contrary to its name, `arc4random` doesn't actually use the horribly-broken //! RC4 cypher anymore, at least not on modern systems, but rather something //! like ChaCha20 with continual reseeding from the OS. That makes it an ideal -//! source of large quantities of cryptographically secure data, which is exactly -//! what we need for `DefaultRandomSource`. Unfortunately, it's not available -//! on all UNIX systems, most notably Linux (until recently, but it's just a -//! wrapper for `getrandom`. Since we need to hook into `getrandom` directly -//! for `HashMap` keys anyway, we just keep our version). +//! source of large quantities of cryptographically secure data, which is +//! exactly what we need for `SystemRng`. Unfortunately, it's not available on +//! all UNIX systems, most notably Linux (until recently, but it's just a +//! wrapper for `getrandom`. Since we need to hook into `getrandom` directly for +//! `HashMap` keys anyway, we just keep our version). -#[cfg(not(any( - target_os = "haiku", - target_os = "illumos", - target_os = "solaris", - target_os = "vita", -)))] +#[cfg(not(target_os = "vita"))] use libc::arc4random_buf; -// FIXME: move these to libc (except Haiku, that one needs to link to libbsd.so). -#[cfg(any( - target_os = "haiku", // See https://git.haiku-os.org/haiku/tree/headers/compatibility/bsd/stdlib.h - target_os = "illumos", // See https://www.illumos.org/man/3C/arc4random - target_os = "solaris", // See https://docs.oracle.com/cd/E88353_01/html/E37843/arc4random-3c.html - target_os = "vita", // See https://github.com/vitasdk/newlib/blob/b89e5bc183b516945f9ee07eef483ecb916e45ff/newlib/libc/include/stdlib.h#L74 -))] -#[cfg_attr(target_os = "haiku", link(name = "bsd"))] +// FIXME: move this to libc +#[cfg(target_os = "vita")] // See https://github.com/vitasdk/newlib/blob/b89e5bc183b516945f9ee07eef483ecb916e45ff/newlib/libc/include/stdlib.h#L74 unsafe extern "C" { fn arc4random_buf(buf: *mut core::ffi::c_void, nbytes: libc::size_t); } diff --git a/library/std/src/sys/random/linux.rs b/library/std/src/sys/random/linux.rs index a5b790a1db42c..6a4e4f3e670db 100644 --- a/library/std/src/sys/random/linux.rs +++ b/library/std/src/sys/random/linux.rs @@ -23,11 +23,11 @@ //! //! One additional consideration to make is that the non-blocking pool is not //! always initialized during early boot. We want the best quality of randomness -//! for the output of `DefaultRandomSource` so we simply wait until it is -//! initialized. When `HashMap` keys however, this represents a potential source -//! of deadlocks, as the additional entropy may only be generated once the -//! program makes forward progress. In that case, we just use the best random -//! data the system has available at the time. +//! for the output of `SystemRng` so we simply wait until it is initialized. +//! When `HashMap` keys however, this represents a potential source of +//! deadlocks, as the additional entropy may only be generated once the program +//! makes forward progress. In that case, we just use the best random data the +//! system has available at the time. //! //! So in conclusion, we always want the output of the non-blocking pool, but //! may need to wait until it is initialized. The default behavior of `getrandom` @@ -123,7 +123,9 @@ fn getrandom(mut bytes: &mut [u8], insecure: bool) { GETRANDOM_AVAILABLE.store(false, Relaxed); break; } - _ => panic!("failed to generate random data"), + other => { + panic!("failed to generate random data: errno={other:?}, flags={flags:?}") + } } } } diff --git a/library/std/src/sys/random/mod.rs b/library/std/src/sys/random/mod.rs index 91f72d0738790..bc3dd501730b7 100644 --- a/library/std/src/sys/random/mod.rs +++ b/library/std/src/sys/random/mod.rs @@ -11,7 +11,7 @@ cfg_select! { target_vendor = "apple" => { mod apple; pub use apple::fill_bytes; - // Others, in alphabetical ordering. + // Others, in alphabetical ordering. } any( target_os = "dragonfly", @@ -49,12 +49,7 @@ cfg_select! { mod getrandom; pub use getrandom::fill_bytes; } - any( - target_os = "aix", - target_os = "hurd", - target_os = "l4re", - target_os = "nto", - ) => { + any(target_os = "aix", target_os = "hurd", target_os = "nto", target_os = "qnx") => { mod unix_legacy; pub use unix_legacy::fill_bytes; } @@ -95,8 +90,8 @@ cfg_select! { pub use wasip1::fill_bytes; } all(target_os = "wasi", any(target_env = "p2", target_env = "p3")) => { - mod wasip2; - pub use wasip2::{fill_bytes, hashmap_random_keys}; + mod wasi; + pub use wasi::{fill_bytes, hashmap_random_keys}; } target_os = "zkvm" => { mod zkvm; @@ -106,6 +101,7 @@ cfg_select! { all(target_family = "wasm", target_os = "unknown"), target_os = "xous", target_os = "vexos", + target_os = "l4re", ) => { // FIXME: finally remove std support for wasm32-unknown-unknown // FIXME: add random data generation to xous @@ -122,6 +118,7 @@ cfg_select! { all(target_os = "wasi", not(target_env = "p1")), target_os = "xous", target_os = "vexos", + target_os = "l4re", )))] pub fn hashmap_random_keys() -> (u64, u64) { let mut buf = [0; 16]; diff --git a/library/std/src/sys/random/uefi.rs b/library/std/src/sys/random/uefi.rs index f7a7600835195..e6fbb5379c964 100644 --- a/library/std/src/sys/random/uefi.rs +++ b/library/std/src/sys/random/uefi.rs @@ -57,13 +57,15 @@ mod rng_protocol { mod rdrand { cfg_select! { target_arch = "x86_64" => { - use crate::arch::x86_64 as arch; use arch::_rdrand64_step as rdrand_step; + + use crate::arch::x86_64 as arch; type Word = u64; } target_arch = "x86" => { - use crate::arch::x86 as arch; use arch::_rdrand32_step as rdrand_step; + + use crate::arch::x86 as arch; type Word = u32; } } diff --git a/library/std/src/sys/random/wasi.rs b/library/std/src/sys/random/wasi.rs new file mode 100644 index 0000000000000..80a9153bdb923 --- /dev/null +++ b/library/std/src/sys/random/wasi.rs @@ -0,0 +1,12 @@ +#[cfg(target_env = "p2")] +use wasip2::random::{insecure_seed::insecure_seed as get_insecure_seed, random::get_random_bytes}; +#[cfg(target_env = "p3")] +use wasip3::random::{insecure_seed::get_insecure_seed, random::get_random_bytes}; + +pub fn fill_bytes(bytes: &mut [u8]) { + bytes.copy_from_slice(&get_random_bytes(u64::try_from(bytes.len()).unwrap())); +} + +pub fn hashmap_random_keys() -> (u64, u64) { + get_insecure_seed() +} diff --git a/library/std/src/sys/random/wasip1.rs b/library/std/src/sys/random/wasip1.rs index d41da3751fc04..cb91575fe30ef 100644 --- a/library/std/src/sys/random/wasip1.rs +++ b/library/std/src/sys/random/wasip1.rs @@ -1,5 +1,5 @@ pub fn fill_bytes(bytes: &mut [u8]) { unsafe { - wasi::random_get(bytes.as_mut_ptr(), bytes.len()).expect("failed to generate random data") + wasip1::random_get(bytes.as_mut_ptr(), bytes.len()).expect("failed to generate random data") } } diff --git a/library/std/src/sys/random/wasip2.rs b/library/std/src/sys/random/wasip2.rs deleted file mode 100644 index a67c8a6428d18..0000000000000 --- a/library/std/src/sys/random/wasip2.rs +++ /dev/null @@ -1,9 +0,0 @@ -pub fn fill_bytes(bytes: &mut [u8]) { - bytes.copy_from_slice(&wasip2::random::random::get_random_bytes( - u64::try_from(bytes.len()).unwrap(), - )); -} - -pub fn hashmap_random_keys() -> (u64, u64) { - wasip2::random::insecure_seed::insecure_seed() -} diff --git a/library/std/src/sys/stdio/motor.rs b/library/std/src/sys/stdio/motor.rs index 2b1bc15285f9c..acc30b134d828 100644 --- a/library/std/src/sys/stdio/motor.rs +++ b/library/std/src/sys/stdio/motor.rs @@ -28,8 +28,6 @@ impl Stderr { } } -impl crate::sealed::Sealed for Stdin {} - impl crate::io::IsTerminal for Stdin { fn is_terminal(&self) -> bool { moto_rt::fs::is_terminal(moto_rt::FD_STDIN) diff --git a/library/std/src/sys/stdio/sgx.rs b/library/std/src/sys/stdio/sgx.rs index 2cf47f4919209..428b2a3a92aef 100644 --- a/library/std/src/sys/stdio/sgx.rs +++ b/library/std/src/sys/stdio/sgx.rs @@ -25,7 +25,7 @@ impl io::Read for Stdin { with_std_fd(abi::FD_STDIN, |fd| fd.read(buf)) } - fn read_buf(&mut self, buf: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, buf: BorrowedCursor<'_, u8>) -> io::Result<()> { with_std_fd(abi::FD_STDIN, |fd| fd.read_buf(buf)) } diff --git a/library/std/src/sys/stdio/unix.rs b/library/std/src/sys/stdio/unix.rs index ffed376a8e96e..205478f2a5e99 100644 --- a/library/std/src/sys/stdio/unix.rs +++ b/library/std/src/sys/stdio/unix.rs @@ -23,7 +23,7 @@ impl io::Read for Stdin { unsafe { ManuallyDrop::new(FileDesc::from_raw_fd(STDIN_FILENO)).read(buf) } } - fn read_buf(&mut self, buf: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, buf: BorrowedCursor<'_, u8>) -> io::Result<()> { unsafe { ManuallyDrop::new(FileDesc::from_raw_fd(STDIN_FILENO)).read_buf(buf) } } diff --git a/library/std/src/sys/stdio/unsupported.rs b/library/std/src/sys/stdio/unsupported.rs index 177264f5c1042..e35f7797d730f 100644 --- a/library/std/src/sys/stdio/unsupported.rs +++ b/library/std/src/sys/stdio/unsupported.rs @@ -17,7 +17,7 @@ impl io::Read for Stdin { } #[inline] - fn read_buf(&mut self, _cursor: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, _cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { Ok(()) } @@ -39,7 +39,7 @@ impl io::Read for Stdin { } #[inline] - fn read_buf_exact(&mut self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf_exact(&mut self, cursor: BorrowedCursor<'_, u8>) -> io::Result<()> { if cursor.capacity() != 0 { Err(io::Error::READ_EXACT_EOF) } else { Ok(()) } } diff --git a/library/std/src/sys/stdio/windows.rs b/library/std/src/sys/stdio/windows.rs index 62ec115d7b0cb..48df73a97a8e3 100644 --- a/library/std/src/sys/stdio/windows.rs +++ b/library/std/src/sys/stdio/windows.rs @@ -109,7 +109,7 @@ fn write(handle_id: u32, data: &[u8], incomplete_utf8: &mut IncompleteUtf8) -> i let handle = Handle::from_raw_handle(handle); let ret = handle.write(data); let _ = handle.into_raw_handle(); // Don't close the handle - return ret; + ret } } else { write_console_utf16(data, incomplete_utf8, handle) @@ -222,7 +222,7 @@ fn write_valid_utf8_to_console(handle: c::HANDLE, utf8: &str) -> io::Result io::Result 1, 0x0080..=0x07FF => 2, - 0xDCEE..=0xDFFF => 1, // Low surrogate. We already counted 3 bytes for the other. + 0xDC00..=0xDFFF => 1, // Low surrogate. We already counted 3 bytes for the other. _ => 3, }; } @@ -278,7 +278,7 @@ impl io::Read for Stdin { Ok(bytes_copied) } else if buf.len() - bytes_copied < 4 { // Not enough space to get a UTF-8 byte. We will use the incomplete UTF8. - let mut utf16_buf = [MaybeUninit::new(0); 1]; + let mut utf16_buf = [MaybeUninit::new(0); 2]; // Read one u16 character. let read = read_u16s_fixup_surrogates(handle, &mut utf16_buf, 1, &mut self.surrogate)?; // Read bytes, using the (now-empty) self.incomplete_utf8 as extra space. @@ -305,8 +305,8 @@ impl io::Read for Stdin { // initialized. let utf16s = unsafe { utf16_buf[..read].assume_init_ref() }; match utf16_to_utf8(utf16s, buf) { - Ok(value) => return Ok(bytes_copied + value), - Err(e) => return Err(e), + Ok(value) => Ok(bytes_copied + value), + Err(e) => Err(e), } } } diff --git a/library/std/src/sys/stdio/zkvm.rs b/library/std/src/sys/stdio/zkvm.rs index f31c6c26e87cd..326d7d8ff2218 100644 --- a/library/std/src/sys/stdio/zkvm.rs +++ b/library/std/src/sys/stdio/zkvm.rs @@ -16,10 +16,10 @@ impl io::Read for Stdin { Ok(unsafe { abi::sys_read(fileno::STDIN, buf.as_mut_ptr(), buf.len()) }) } - fn read_buf(&mut self, mut buf: BorrowedCursor<'_>) -> io::Result<()> { + fn read_buf(&mut self, mut buf: BorrowedCursor<'_, u8>) -> io::Result<()> { unsafe { let n = abi::sys_read(fileno::STDIN, buf.as_mut().as_mut_ptr().cast(), buf.capacity()); - buf.advance_unchecked(n); + buf.advance(n); } Ok(()) } diff --git a/library/std/src/sys/sync/condvar/futex.rs b/library/std/src/sys/sync/condvar/futex.rs index 0d0c5f0dbe701..b5b82e4c38257 100644 --- a/library/std/src/sys/sync/condvar/futex.rs +++ b/library/std/src/sys/sync/condvar/futex.rs @@ -1,6 +1,6 @@ use crate::sync::atomic::Ordering::Relaxed; -use crate::sys::futex::{Futex, futex_wait, futex_wake, futex_wake_all}; use crate::sys::sync::Mutex; +use crate::sys::sync::futex::{Futex, futex_wait, futex_wake, futex_wake_all}; use crate::time::Duration; pub struct Condvar { diff --git a/library/std/src/sys/sync/condvar/mod.rs b/library/std/src/sys/sync/condvar/mod.rs index 83cf0ae629851..615781ea9b7dc 100644 --- a/library/std/src/sys/sync/condvar/mod.rs +++ b/library/std/src/sys/sync/condvar/mod.rs @@ -1,6 +1,6 @@ cfg_select! { any( - all(target_os = "windows", not(target_vendor="win7")), + all(target_os = "windows", not(target_vendor = "win7")), target_os = "linux", target_os = "android", target_os = "freebsd", @@ -10,14 +10,12 @@ cfg_select! { target_os = "fuchsia", all(target_family = "wasm", target_feature = "atomics"), target_os = "hermit", + all(target_os = "wasi", target_env = "p3"), ) => { mod futex; pub use futex::Condvar; } - any( - target_family = "unix", - target_os = "teeos", - ) => { + any(target_family = "unix", target_os = "teeos") => { mod pthread; pub use pthread::Condvar; } diff --git a/library/std/src/sys/sync/condvar/no_threads.rs b/library/std/src/sys/sync/condvar/no_threads.rs index 18d97d4b17ab0..9dbba490b2851 100644 --- a/library/std/src/sys/sync/condvar/no_threads.rs +++ b/library/std/src/sys/sync/condvar/no_threads.rs @@ -2,6 +2,9 @@ use crate::sys::sync::Mutex; use crate::thread::sleep; use crate::time::Duration; +#[cfg(target_has_threads)] +compile_error!("Using no_threads implementation on a target with threads"); + pub struct Condvar {} impl Condvar { diff --git a/library/std/src/sys/sync/condvar/xous.rs b/library/std/src/sys/sync/condvar/xous.rs index 21a1587214a11..b907c3467ff4b 100644 --- a/library/std/src/sys/sync/condvar/xous.rs +++ b/library/std/src/sys/sync/condvar/xous.rs @@ -38,7 +38,7 @@ impl Condvar { // possible for `counter` to decrease due to a condvar timing out, in which // case the corresponding `timed_out` will increase accordingly. let Ok(waiter_count) = - self.counter.fetch_update(Ordering::Relaxed, Ordering::Relaxed, |counter| { + self.counter.try_update(Ordering::Relaxed, Ordering::Relaxed, |counter| { if counter == 0 { return None; } else { @@ -124,11 +124,9 @@ impl Condvar { } pub unsafe fn wait_timeout(&self, mutex: &Mutex, dur: Duration) -> bool { - let mut millis = dur.as_millis() as usize; - // Ensure we don't wait for 0 ms, which would cause us to wait forever - if millis == 0 { - millis = 1; - } + // A value of zero indicates an indefinite wait, so clamp the number of + // milliseconds to the representable range and avoid waiting forever. + let millis = usize::max(dur.as_millis().try_into().unwrap_or(usize::MAX), 1); self.wait_ms(mutex, millis) } } diff --git a/library/std/src/sys/pal/hermit/futex.rs b/library/std/src/sys/sync/futex/hermit.rs similarity index 97% rename from library/std/src/sys/pal/hermit/futex.rs rename to library/std/src/sys/sync/futex/hermit.rs index 78c86071fdd53..783052526c525 100644 --- a/library/std/src/sys/pal/hermit/futex.rs +++ b/library/std/src/sys/sync/futex/hermit.rs @@ -1,4 +1,4 @@ -use super::hermit_abi; +use crate::os::hermit::hermit_abi; use crate::ptr::null; use crate::sync::atomic::Atomic; use crate::time::Duration; diff --git a/library/std/src/sys/sync/futex/mod.rs b/library/std/src/sys/sync/futex/mod.rs new file mode 100644 index 0000000000000..0edb46cc10f86 --- /dev/null +++ b/library/std/src/sys/sync/futex/mod.rs @@ -0,0 +1,39 @@ +cfg_select! { + any( + target_os = "linux", + target_os = "android", + all(target_os = "emscripten", target_feature = "atomics"), + target_os = "freebsd", + target_os = "openbsd", + target_os = "dragonfly", + target_os = "fuchsia", + ) => { + mod unix; + pub use unix::*; + } + all(target_os = "windows", not(target_vendor = "win7")) => { + mod windows; + pub use windows::*; + } + target_os = "hermit" => { + mod hermit; + pub use hermit::*; + } + // The wasi-libc based futex is new enough that it's not present in older + // wasi-libc builds. For now that means it's only required on wasip3 (which + // requires a newer wasi-libc anyway). In the future this'll probably switch to + // unconditionally using `wasilibc` as the implementation for all WASI + // targets (and switching all synchronization primitives to the futex version). + all(target_os = "wasi", target_env = "p3") => { + mod wasilibc; + pub use wasilibc::*; + } + all(target_family = "wasm", target_feature = "atomics") => { + mod wasm; + pub use wasm::*; + } + target_os = "motor" => { + pub use moto_rt::futex::*; + } + _ => {} +} diff --git a/library/std/src/sys/pal/unix/futex.rs b/library/std/src/sys/sync/futex/unix.rs similarity index 94% rename from library/std/src/sys/pal/unix/futex.rs rename to library/std/src/sys/sync/futex/unix.rs index 2948d3d594eaa..9291860d4934c 100644 --- a/library/std/src/sys/pal/unix/futex.rs +++ b/library/std/src/sys/sync/futex/unix.rs @@ -1,13 +1,3 @@ -#![cfg(any( - target_os = "linux", - target_os = "android", - all(target_os = "emscripten", target_feature = "atomics"), - target_os = "freebsd", - target_os = "openbsd", - target_os = "dragonfly", - target_os = "fuchsia", -))] - use crate::sync::atomic::Atomic; use crate::time::Duration; @@ -28,9 +18,9 @@ pub type SmallPrimitive = u32; /// Returns false on timeout, and true in all other cases. #[cfg(any(target_os = "linux", target_os = "android", target_os = "freebsd"))] pub fn futex_wait(futex: &Atomic, expected: u32, timeout: Option) -> bool { - use super::time::Timespec; use crate::ptr::null; use crate::sync::atomic::Ordering::Relaxed; + use crate::sys::pal::time::Timespec; // Calculate the timeout as an absolute timespec. // @@ -77,7 +67,7 @@ pub fn futex_wait(futex: &Atomic, expected: u32, timeout: Option) expected, timespec.as_ref().map_or(null(), |t| t as *const libc::timespec), null::(), // This argument is unused for FUTEX_WAIT_BITSET. - !0u32, // A full bitmask, to make it behave like a regular FUTEX_WAIT. + !0u32, // A full bitmask, to make it behave like a regular FUTEX_WAIT. ) } _ => { @@ -149,8 +139,8 @@ pub fn futex_wake_all(futex: &Atomic) { #[cfg(target_os = "openbsd")] pub fn futex_wait(futex: &Atomic, expected: u32, timeout: Option) -> bool { - use super::time::Timespec; use crate::ptr::{null, null_mut}; + use crate::sys::pal::time::Timespec; // Overflows are rounded up to an infinite timeout (None). let timespec = timeout @@ -258,7 +248,7 @@ pub fn futex_wake_all(futex: &Atomic) { #[cfg(target_os = "fuchsia")] pub fn futex_wait(futex: &Atomic, expected: u32, timeout: Option) -> bool { - use super::fuchsia::*; + use crate::sys::pal::fuchsia::*; // Sleep forever if the timeout is longer than fits in a i64. let deadline = timeout @@ -274,11 +264,11 @@ pub fn futex_wait(futex: &Atomic, expected: u32, timeout: Option) // Fuchsia doesn't tell us how many threads are woken up, so this always returns false. #[cfg(target_os = "fuchsia")] pub fn futex_wake(futex: &Atomic) -> bool { - unsafe { super::fuchsia::zx_futex_wake(futex, 1) }; + unsafe { crate::sys::pal::fuchsia::zx_futex_wake(futex, 1) }; false } #[cfg(target_os = "fuchsia")] pub fn futex_wake_all(futex: &Atomic) { - unsafe { super::fuchsia::zx_futex_wake(futex, u32::MAX) }; + unsafe { crate::sys::pal::fuchsia::zx_futex_wake(futex, u32::MAX) }; } diff --git a/library/std/src/sys/sync/futex/wasilibc.rs b/library/std/src/sys/sync/futex/wasilibc.rs new file mode 100644 index 0000000000000..b83e75acac3ae --- /dev/null +++ b/library/std/src/sys/sync/futex/wasilibc.rs @@ -0,0 +1,68 @@ +//! A futex implementation based on the primitives provided by `wasi-libc`. +//! +//! This is currently only used on wasip3 targets, but in the future once +//! `wasi-libc`'s implementation of these symbols have percolated further it'll +//! be possible to use this on all WASI targets. The `wasi-libc` implementation +//! of these symbols differs depending on the target and configuration: +//! +//! * `wasm32-wasip{1,2}` - this will abort if blocking actually happens +//! * `wasm32-wasip1-threads` - this uses wasm `memory.atomic.*` instructions +//! * `wasm32-wasip3` - depending on libc configuration (`ENABLE_COOP_THREADS`) +//! this either aborts (coop threads disables) on blocking or does the +//! coop-thread-thing to manage threads. +//! +//! Regardless this module is effectively delegating to `wasi-libc` to determine +//! how to do thread management. + +use libc::c_int; + +use crate::ptr; +use crate::sync::atomic::Atomic; +use crate::time::Duration; + +const __WASILIBC_FUTEX_WAKE_ALL: c_int = -1; + +unsafe extern "C" { + fn __wasilibc_futex_wait( + addr: *mut c_int, + val: c_int, + clock: libc::clockid_t, + at: *const libc::timespec, + flags: libc::c_uint, + ) -> c_int; + fn __wasilibc_futex_wake(addr: *const c_int, count: c_int, flags: libc::c_uint) -> c_int; +} + +pub type Futex = Atomic; +pub type Primitive = u32; + +pub type SmallFutex = Atomic; +pub type SmallPrimitive = u32; + +pub fn futex_wait(futex: &Atomic, expected: u32, timeout: Option) -> bool { + let timespec = timeout.and_then(|t| { + Some(libc::timespec { + tv_sec: t.as_secs().try_into().ok()?, + tv_nsec: t.subsec_nanos().try_into().ok()?, + }) + }); + unsafe { + __wasilibc_futex_wait( + futex.as_ptr().cast(), + expected.cast_signed(), + libc::CLOCK_REALTIME, + timespec.as_ref().map(ptr::from_ref).unwrap_or(ptr::null()), + 0, + ) == 0 + } +} + +pub fn futex_wake(futex: &Atomic) -> bool { + unsafe { __wasilibc_futex_wake(futex.as_ptr().cast(), 1, 0) == 1 } +} + +pub fn futex_wake_all(futex: &Atomic) { + unsafe { + __wasilibc_futex_wake(futex.as_ptr().cast(), __WASILIBC_FUTEX_WAKE_ALL, 0); + } +} diff --git a/library/std/src/sys/pal/wasm/atomics/futex.rs b/library/std/src/sys/sync/futex/wasm.rs similarity index 100% rename from library/std/src/sys/pal/wasm/atomics/futex.rs rename to library/std/src/sys/sync/futex/wasm.rs diff --git a/library/std/src/sys/pal/windows/futex.rs b/library/std/src/sys/sync/futex/windows.rs similarity index 98% rename from library/std/src/sys/pal/windows/futex.rs rename to library/std/src/sys/sync/futex/windows.rs index cfa0a6b3815bd..eed0bb2548c1d 100644 --- a/library/std/src/sys/pal/windows/futex.rs +++ b/library/std/src/sys/sync/futex/windows.rs @@ -6,7 +6,7 @@ use core::sync::atomic::{ }; use core::time::Duration; -use super::api::{self, WinError}; +use crate::sys::pal::api::{self, WinError}; use crate::sys::{c, dur2timeout}; /// An atomic for use as a futex that is at least 32-bits but may be larger diff --git a/library/std/src/sys/sync/mod.rs b/library/std/src/sys/sync/mod.rs index 0691e96785198..8ee0b2649ed3d 100644 --- a/library/std/src/sys/sync/mod.rs +++ b/library/std/src/sys/sync/mod.rs @@ -1,4 +1,5 @@ mod condvar; +mod futex; mod mutex; mod once; mod once_box; diff --git a/library/std/src/sys/sync/mutex/futex.rs b/library/std/src/sys/sync/mutex/futex.rs index 70e2ea9f60586..015b5aacbc53b 100644 --- a/library/std/src/sys/sync/mutex/futex.rs +++ b/library/std/src/sys/sync/mutex/futex.rs @@ -1,5 +1,5 @@ use crate::sync::atomic::Ordering::{Acquire, Relaxed, Release}; -use crate::sys::futex::{self, futex_wait, futex_wake}; +use crate::sys::sync::futex::{self, futex_wait, futex_wake}; type Futex = futex::SmallFutex; type State = futex::SmallPrimitive; diff --git a/library/std/src/sys/sync/mutex/mod.rs b/library/std/src/sys/sync/mutex/mod.rs index e3d6ad1129c83..895ab9c895697 100644 --- a/library/std/src/sys/sync/mutex/mod.rs +++ b/library/std/src/sys/sync/mutex/mod.rs @@ -9,6 +9,7 @@ cfg_select! { target_os = "dragonfly", all(target_family = "wasm", target_feature = "atomics"), target_os = "hermit", + all(target_os = "wasi", target_env = "p3"), ) => { mod futex; pub use futex::Mutex; @@ -17,10 +18,7 @@ cfg_select! { mod fuchsia; pub use fuchsia::Mutex; } - any( - target_family = "unix", - target_os = "teeos", - ) => { + any(target_family = "unix", target_os = "teeos") => { mod pthread; pub use pthread::Mutex; } diff --git a/library/std/src/sys/sync/mutex/no_threads.rs b/library/std/src/sys/sync/mutex/no_threads.rs index 57c78f454c57c..a87c2747451c5 100644 --- a/library/std/src/sys/sync/mutex/no_threads.rs +++ b/library/std/src/sys/sync/mutex/no_threads.rs @@ -1,5 +1,8 @@ use crate::cell::Cell; +#[cfg(target_has_threads)] +compile_error!("Using no_threads implementation on a target with threads"); + pub struct Mutex { // This platform has no threads, so we can use a Cell here. locked: Cell, @@ -26,6 +29,6 @@ impl Mutex { #[inline] pub fn try_lock(&self) -> bool { - self.locked.replace(true) == false + !self.locked.replace(true) } } diff --git a/library/std/src/sys/sync/once/futex.rs b/library/std/src/sys/sync/once/futex.rs index 096f1d879ef26..8f17f065669a8 100644 --- a/library/std/src/sys/sync/once/futex.rs +++ b/library/std/src/sys/sync/once/futex.rs @@ -2,7 +2,7 @@ use crate::cell::Cell; use crate::sync as public; use crate::sync::atomic::Ordering::{Acquire, Relaxed, Release}; use crate::sync::once::OnceExclusiveState; -use crate::sys::futex::{Futex, Primitive, futex_wait, futex_wake_all}; +use crate::sys::sync::futex::{Futex, Primitive, futex_wait, futex_wake_all}; // On some platforms, the OS is very nice and handles the waiter queue for us. // This means we only need one atomic value with 4 states: @@ -75,6 +75,11 @@ impl Once { Once { state_and_queued: Futex::new(INCOMPLETE) } } + #[inline] + pub const fn new_complete() -> Once { + Once { state_and_queued: Futex::new(COMPLETE) } + } + #[inline] pub fn is_completed(&self) -> bool { // Use acquire ordering to make all initialization changes visible to the diff --git a/library/std/src/sys/sync/once/mod.rs b/library/std/src/sys/sync/once/mod.rs index aeea884b9f617..eee7edf8575fc 100644 --- a/library/std/src/sys/sync/once/mod.rs +++ b/library/std/src/sys/sync/once/mod.rs @@ -9,16 +9,17 @@ cfg_select! { any( - all(target_os = "windows", not(target_vendor="win7")), + all(target_os = "windows", not(target_vendor = "win7")), target_os = "linux", target_os = "android", - all(target_arch = "wasm32", target_feature = "atomics"), + all(target_family = "wasm", target_feature = "atomics"), target_os = "freebsd", target_os = "motor", target_os = "openbsd", target_os = "dragonfly", target_os = "fuchsia", target_os = "hermit", + all(target_os = "wasi", target_env = "p3"), ) => { mod futex; pub use futex::{Once, OnceState}; diff --git a/library/std/src/sys/sync/once/no_threads.rs b/library/std/src/sys/sync/once/no_threads.rs index 576bbf644cbed..31c9aedb98f96 100644 --- a/library/std/src/sys/sync/once/no_threads.rs +++ b/library/std/src/sys/sync/once/no_threads.rs @@ -2,6 +2,9 @@ use crate::cell::Cell; use crate::sync as public; use crate::sync::once::OnceExclusiveState; +#[cfg(target_has_threads)] +compile_error!("Using no_threads implementation on a target with threads"); + pub struct Once { state: Cell, } @@ -39,6 +42,11 @@ impl Once { Once { state: Cell::new(State::Incomplete) } } + #[inline] + pub const fn new_complete() -> Once { + Once { state: Cell::new(State::Complete) } + } + #[inline] pub fn is_completed(&self) -> bool { self.state.get() == State::Complete diff --git a/library/std/src/sys/sync/once/queue.rs b/library/std/src/sys/sync/once/queue.rs index d7219a7361cff..311c7b0db2d90 100644 --- a/library/std/src/sys/sync/once/queue.rs +++ b/library/std/src/sys/sync/once/queue.rs @@ -60,7 +60,7 @@ use crate::sync::atomic::Ordering::{AcqRel, Acquire, Release}; use crate::sync::atomic::{Atomic, AtomicBool, AtomicPtr}; use crate::sync::once::OnceExclusiveState; use crate::thread::{self, Thread}; -use crate::{fmt, ptr, sync as public}; +use crate::{fmt, mem, ptr, sync as public}; type StateAndQueue = *mut (); @@ -121,6 +121,11 @@ impl Once { Once { state_and_queue: AtomicPtr::new(ptr::without_provenance_mut(INCOMPLETE)) } } + #[inline] + pub const fn new_complete() -> Once { + Once { state_and_queue: AtomicPtr::new(ptr::without_provenance_mut(COMPLETE)) } + } + #[inline] pub fn is_completed(&self) -> bool { // An `Acquire` load is enough because that makes all the initialization @@ -232,6 +237,15 @@ impl Once { } } +/// A type to guard against the unwinds of stacks that nodes are located on due to panics. +struct PanicGuard; + +impl Drop for PanicGuard { + fn drop(&mut self) { + rtabort!("tried to drop node in intrusive list."); + } +} + fn wait( state_and_queue: &Atomic<*mut ()>, mut current: StateAndQueue, @@ -267,6 +281,9 @@ fn wait( continue; } + // Guard against unwinds using a `PanicGuard` that aborts when dropped. + let guard = PanicGuard; + // We have enqueued ourselves, now lets wait. // It is important not to return before being signaled, otherwise we // would drop our `Waiter` node and leave a hole in the linked list @@ -283,6 +300,9 @@ fn wait( unsafe { node.thread.park() } } + // The node was removed from the queue, disarm the guard. + mem::forget(guard); + return state_and_queue.load(Acquire); } } diff --git a/library/std/src/sys/sync/rwlock/futex.rs b/library/std/src/sys/sync/rwlock/futex.rs index 961819cae8d6e..c9389fe144b4d 100644 --- a/library/std/src/sys/sync/rwlock/futex.rs +++ b/library/std/src/sys/sync/rwlock/futex.rs @@ -1,5 +1,5 @@ use crate::sync::atomic::Ordering::{Acquire, Relaxed, Release}; -use crate::sys::futex::{Futex, Primitive, futex_wait, futex_wake, futex_wake_all}; +use crate::sys::sync::futex::{Futex, Primitive, futex_wait, futex_wake, futex_wake_all}; pub struct RwLock { // The state consists of a 30-bit reader counter, a 'readers waiting' flag, and a 'writers waiting' flag. @@ -86,7 +86,7 @@ impl RwLock { #[inline] pub fn try_read(&self) -> bool { self.state - .fetch_update(Acquire, Relaxed, |s| is_read_lockable(s).then(|| s + READ_LOCKED)) + .try_update(Acquire, Relaxed, |s| is_read_lockable(s).then(|| s + READ_LOCKED)) .is_ok() } @@ -164,7 +164,7 @@ impl RwLock { #[inline] pub fn try_write(&self) -> bool { self.state - .fetch_update(Acquire, Relaxed, |s| is_unlocked(s).then(|| s + WRITE_LOCKED)) + .try_update(Acquire, Relaxed, |s| is_unlocked(s).then(|| s + WRITE_LOCKED)) .is_ok() } diff --git a/library/std/src/sys/sync/rwlock/mod.rs b/library/std/src/sys/sync/rwlock/mod.rs index 8603fca2da5b5..9991f290e46d1 100644 --- a/library/std/src/sys/sync/rwlock/mod.rs +++ b/library/std/src/sys/sync/rwlock/mod.rs @@ -9,7 +9,8 @@ cfg_select! { target_os = "fuchsia", all(target_family = "wasm", target_feature = "atomics"), target_os = "hermit", - target_os = "motor", + target_os = "motor", + all(target_os = "wasi", target_env = "p3"), ) => { mod futex; pub use futex::RwLock; diff --git a/library/std/src/sys/sync/rwlock/no_threads.rs b/library/std/src/sys/sync/rwlock/no_threads.rs index 573d0d602dbd6..efa2629b3110d 100644 --- a/library/std/src/sys/sync/rwlock/no_threads.rs +++ b/library/std/src/sys/sync/rwlock/no_threads.rs @@ -1,5 +1,8 @@ use crate::cell::Cell; +#[cfg(target_has_threads)] +compile_error!("Using no_threads implementation on a target with threads"); + pub struct RwLock { // This platform has no threads, so we can use a Cell here. mode: Cell, @@ -18,7 +21,7 @@ impl RwLock { pub fn read(&self) { let m = self.mode.get(); if m >= 0 { - self.mode.set(m + 1); + self.mode.set(m.checked_add(1).expect("rwlock overflowed read locks")); } else { rtabort!("rwlock locked for writing"); } @@ -28,6 +31,9 @@ impl RwLock { pub fn try_read(&self) -> bool { let m = self.mode.get(); if m >= 0 { + if m == isize::MAX { + return false; + } self.mode.set(m + 1); true } else { @@ -37,8 +43,10 @@ impl RwLock { #[inline] pub fn write(&self) { - if self.mode.replace(-1) != 0 { - rtabort!("rwlock locked for reading") + if self.mode.get() == 0 { + self.mode.set(-1); + } else { + rtabort!("rwlock locked for reading"); } } @@ -54,16 +62,19 @@ impl RwLock { #[inline] pub unsafe fn read_unlock(&self) { - self.mode.set(self.mode.get() - 1); + assert!( + self.mode.replace(self.mode.get() - 1) > 0, + "rwlock has not been locked for reading" + ); } #[inline] pub unsafe fn write_unlock(&self) { - assert_eq!(self.mode.replace(0), -1); + assert_eq!(self.mode.replace(0), -1, "rwlock has not been locked for writing"); } #[inline] pub unsafe fn downgrade(&self) { - assert_eq!(self.mode.replace(1), -1); + assert_eq!(self.mode.replace(1), -1, "rwlock has not been locked for writing"); } } diff --git a/library/std/src/sys/sync/rwlock/queue.rs b/library/std/src/sys/sync/rwlock/queue.rs index 62f084acfd259..b41a65f7303b2 100644 --- a/library/std/src/sys/sync/rwlock/queue.rs +++ b/library/std/src/sys/sync/rwlock/queue.rs @@ -329,7 +329,7 @@ impl RwLock { #[inline] pub fn try_read(&self) -> bool { - self.state.fetch_update(Acquire, Relaxed, read_lock).is_ok() + self.state.try_update(Acquire, Relaxed, read_lock).is_ok() } #[inline] @@ -343,7 +343,7 @@ impl RwLock { pub fn try_write(&self) -> bool { // Atomically set the `LOCKED` bit. This is lowered to a single atomic instruction on most // modern processors (e.g. "lock bts" on x86 and "ldseta" on modern AArch64), and therefore - // is more efficient than `fetch_update(lock(true))`, which can spuriously fail if a new + // is more efficient than `try_update(lock(true))`, which can spuriously fail if a new // node is appended to the queue. self.state.fetch_or(LOCKED, Acquire).addr() & LOCKED == 0 } @@ -453,7 +453,7 @@ impl RwLock { #[inline] pub unsafe fn read_unlock(&self) { - match self.state.fetch_update(Release, Acquire, |state| { + match self.state.try_update(Release, Acquire, |state| { if state.addr() & QUEUED == 0 { // If there are no threads queued, simply decrement the reader count. let count = state.addr() - (SINGLE | LOCKED); diff --git a/library/std/src/sys/sync/thread_parking/futex.rs b/library/std/src/sys/sync/thread_parking/futex.rs index c8f7f26386a01..691d839c41e6d 100644 --- a/library/std/src/sys/sync/thread_parking/futex.rs +++ b/library/std/src/sys/sync/thread_parking/futex.rs @@ -1,7 +1,7 @@ #![forbid(unsafe_op_in_unsafe_fn)] use crate::pin::Pin; use crate::sync::atomic::Ordering::{Acquire, Release}; -use crate::sys::futex::{self, futex_wait, futex_wake}; +use crate::sys::sync::futex::{self, futex_wait, futex_wake}; use crate::time::Duration; type Futex = futex::SmallFutex; diff --git a/library/std/src/sys/sync/thread_parking/mod.rs b/library/std/src/sys/sync/thread_parking/mod.rs index 74b5b72b19a75..f1385ef7bdde6 100644 --- a/library/std/src/sys/sync/thread_parking/mod.rs +++ b/library/std/src/sys/sync/thread_parking/mod.rs @@ -3,13 +3,14 @@ cfg_select! { all(target_os = "windows", not(target_vendor = "win7")), target_os = "linux", target_os = "android", - all(target_arch = "wasm32", target_feature = "atomics"), + all(target_family = "wasm", target_feature = "atomics"), target_os = "freebsd", target_os = "openbsd", target_os = "dragonfly", target_os = "fuchsia", target_os = "motor", target_os = "hermit", + all(target_os = "wasi", target_env = "p3"), ) => { mod futex; pub use futex::Parker; @@ -35,10 +36,7 @@ cfg_select! { mod xous; pub use xous::Parker; } - any( - target_family = "unix", - target_os = "teeos", - ) => { + any(target_family = "unix", target_os = "teeos") => { mod pthread; pub use pthread::Parker; } diff --git a/library/std/src/sys/thread/mod.rs b/library/std/src/sys/thread/mod.rs index 9816981c7fc88..fb5d65150395d 100644 --- a/library/std/src/sys/thread/mod.rs +++ b/library/std/src/sys/thread/mod.rs @@ -1,7 +1,7 @@ cfg_select! { target_os = "hermit" => { mod hermit; - pub use hermit::{Thread, available_parallelism, sleep, yield_now, DEFAULT_MIN_STACK_SIZE}; + pub use hermit::{DEFAULT_MIN_STACK_SIZE, Thread, available_parallelism, sleep, yield_now}; #[expect(dead_code)] mod unsupported; pub use unsupported::{current_os_id, set_name}; @@ -12,7 +12,7 @@ cfg_select! { } all(target_vendor = "fortanix", target_env = "sgx") => { mod sgx; - pub use sgx::{Thread, current_os_id, sleep, yield_now, DEFAULT_MIN_STACK_SIZE}; + pub use sgx::{DEFAULT_MIN_STACK_SIZE, Thread, current_os_id, sleep, yield_now}; // SGX should protect in-enclave data from outside attackers, so there // must not be any data leakage to the OS, particularly no 1-1 mapping @@ -29,14 +29,14 @@ cfg_select! { } target_os = "solid_asp3" => { mod solid; - pub use solid::{Thread, sleep, yield_now, DEFAULT_MIN_STACK_SIZE}; + pub use solid::{DEFAULT_MIN_STACK_SIZE, Thread, sleep, yield_now}; #[expect(dead_code)] mod unsupported; pub use unsupported::{available_parallelism, current_os_id, set_name}; } target_os = "teeos" => { mod teeos; - pub use teeos::{Thread, sleep, yield_now, DEFAULT_MIN_STACK_SIZE}; + pub use teeos::{DEFAULT_MIN_STACK_SIZE, Thread, sleep, yield_now}; #[expect(dead_code)] mod unsupported; pub use unsupported::{available_parallelism, current_os_id, set_name}; @@ -46,11 +46,10 @@ cfg_select! { pub use uefi::{available_parallelism, sleep}; #[expect(dead_code)] mod unsupported; - pub use unsupported::{Thread, current_os_id, set_name, yield_now, DEFAULT_MIN_STACK_SIZE}; + pub use unsupported::{DEFAULT_MIN_STACK_SIZE, Thread, current_os_id, set_name, yield_now}; } any(target_family = "unix", target_os = "wasi") => { mod unix; - pub use unix::{Thread, available_parallelism, current_os_id, sleep, yield_now, DEFAULT_MIN_STACK_SIZE}; #[cfg(not(any( target_env = "newlib", target_os = "l4re", @@ -75,6 +74,9 @@ cfg_select! { target_vendor = "apple", ))] pub use unix::sleep_until; + pub use unix::{ + DEFAULT_MIN_STACK_SIZE, Thread, available_parallelism, current_os_id, sleep, yield_now, + }; #[expect(dead_code)] mod unsupported; #[cfg(any( @@ -93,7 +95,9 @@ cfg_select! { pub use vexos::{sleep, sleep_until, yield_now}; #[expect(dead_code)] mod unsupported; - pub use unsupported::{Thread, available_parallelism, current_os_id, set_name, DEFAULT_MIN_STACK_SIZE}; + pub use unsupported::{ + DEFAULT_MIN_STACK_SIZE, Thread, available_parallelism, current_os_id, set_name, + }; } all(target_family = "wasm", target_feature = "atomics") => { mod wasm; @@ -101,15 +105,21 @@ cfg_select! { #[expect(dead_code)] mod unsupported; - pub use unsupported::{Thread, available_parallelism, current_os_id, set_name, yield_now, DEFAULT_MIN_STACK_SIZE}; + pub use unsupported::{ + DEFAULT_MIN_STACK_SIZE, Thread, available_parallelism, current_os_id, set_name, + yield_now, + }; } target_os = "windows" => { mod windows; - pub use windows::{Thread, available_parallelism, current_os_id, set_name, set_name_wide, sleep, yield_now, DEFAULT_MIN_STACK_SIZE}; + pub use windows::{ + DEFAULT_MIN_STACK_SIZE, Thread, available_parallelism, current_os_id, set_name, + set_name_wide, sleep, yield_now, + }; } target_os = "xous" => { mod xous; - pub use xous::{Thread, available_parallelism, sleep, yield_now, DEFAULT_MIN_STACK_SIZE}; + pub use xous::{DEFAULT_MIN_STACK_SIZE, Thread, available_parallelism, sleep, yield_now}; #[expect(dead_code)] mod unsupported; @@ -117,7 +127,10 @@ cfg_select! { } _ => { mod unsupported; - pub use unsupported::{Thread, available_parallelism, current_os_id, set_name, sleep, yield_now, DEFAULT_MIN_STACK_SIZE}; + pub use unsupported::{ + DEFAULT_MIN_STACK_SIZE, Thread, available_parallelism, current_os_id, set_name, sleep, + yield_now, + }; } } diff --git a/library/std/src/sys/thread/solid.rs b/library/std/src/sys/thread/solid.rs index 5953c0e7b6129..acea047a66455 100644 --- a/library/std/src/sys/thread/solid.rs +++ b/library/std/src/sys/thread/solid.rs @@ -169,8 +169,7 @@ impl Thread { } } - // Safety: `Box::into_raw` returns a non-null pointer - let p_inner = unsafe { NonNull::new_unchecked(Box::into_raw(inner)) }; + let p_inner = Box::into_non_null(inner); let new_task = ItronError::err_if_negative(unsafe { abi::acre_tsk(&abi::T_CTSK { diff --git a/library/std/src/sys/thread/teeos.rs b/library/std/src/sys/thread/teeos.rs index 5e71f757eaa4b..aa679e780c18c 100644 --- a/library/std/src/sys/thread/teeos.rs +++ b/library/std/src/sys/thread/teeos.rs @@ -1,5 +1,5 @@ use crate::mem::{self, ManuallyDrop}; -use crate::sys::os; +use crate::sys::pal::conf; use crate::thread::ThreadInit; use crate::time::Duration; use crate::{cmp, io, ptr}; @@ -52,7 +52,7 @@ impl Thread { // multiple of the system page size. Because it's definitely // >= PTHREAD_STACK_MIN, it must be an alignment issue. // Round up to the nearest page and try again. - let page_size = os::page_size(); + let page_size = conf::page_size(); let stack_size = (stack_size + page_size - 1) & (-(page_size as isize - 1) as usize - 1); assert_eq!(unsafe { libc::pthread_attr_setstacksize(&mut attr, stack_size) }, 0); diff --git a/library/std/src/sys/thread/unix.rs b/library/std/src/sys/thread/unix.rs index b758737d00c64..abcdfe89476e1 100644 --- a/library/std/src/sys/thread/unix.rs +++ b/library/std/src/sys/thread/unix.rs @@ -12,7 +12,12 @@ use crate::mem::{self, DropGuard, ManuallyDrop}; use crate::num::NonZero; #[cfg(all(target_os = "linux", target_env = "gnu"))] use crate::sys::weak::dlsym; -#[cfg(any(target_os = "solaris", target_os = "illumos", target_os = "nto",))] +#[cfg(any( + target_os = "solaris", + target_os = "illumos", + target_os = "nto", + target_os = "qnx", +))] use crate::sys::weak::weak; use crate::thread::ThreadInit; use crate::time::Duration; @@ -44,15 +49,6 @@ impl Thread { // unsafe: see thread::Builder::spawn_unchecked for safety requirements #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces pub unsafe fn new(stack: usize, init: Box) -> io::Result { - // FIXME: remove this block once wasi-sdk is updated with the fix from - // https://github.com/WebAssembly/wasi-libc/pull/716 - // WASI does not support threading via pthreads. While wasi-libc provides - // pthread stubs, pthread_create returns EAGAIN, which causes confusing - // errors. We return UNSUPPORTED_PLATFORM directly instead. - if cfg!(all(target_os = "wasi", not(target_feature = "atomics"))) { - return Err(io::Error::UNSUPPORTED_PLATFORM); - } - let data = init; let mut attr: mem::MaybeUninit = mem::MaybeUninit::uninit(); assert_eq!(libc::pthread_attr_init(attr.as_mut_ptr()), 0); @@ -85,7 +81,7 @@ impl Thread { // multiple of the system page size. Because it's definitely // >= PTHREAD_STACK_MIN, it must be an alignment issue. // Round up to the nearest page and try again. - let page_size = sys::os::page_size(); + let page_size = sys::pal::conf::page_size(); let stack_size = (stack_size + page_size - 1) & (-(page_size as isize - 1) as usize - 1); @@ -164,6 +160,8 @@ pub fn available_parallelism() -> io::Result> { target_os = "aix", target_vendor = "apple", target_os = "cygwin", + target_os = "redox", + target_os = "wasi", ) => { #[allow(unused_assignments)] #[allow(unused_mut)] @@ -183,7 +181,7 @@ pub fn available_parallelism() -> io::Result> { // none was explicitly set. // In that case we use the sysconf fallback. if let Some(count) = NonZero::new(count) { - return Ok(count) + return Ok(count); } } } @@ -200,10 +198,10 @@ pub fn available_parallelism() -> io::Result> { } } any( - target_os = "freebsd", - target_os = "dragonfly", - target_os = "openbsd", - target_os = "netbsd", + target_os = "freebsd", + target_os = "dragonfly", + target_os = "openbsd", + target_os = "netbsd", ) => { use crate::ptr; @@ -217,7 +215,8 @@ pub fn available_parallelism() -> io::Result> { -1, size_of::(), &mut set, - ) == 0 { + ) == 0 + { let count = libc::CPU_COUNT(&set) as usize; if count > 0 { return Ok(NonZero::new_unchecked(count)); @@ -232,7 +231,12 @@ pub fn available_parallelism() -> io::Result> { let set = libc::_cpuset_create(); if !set.is_null() { let mut count: usize = 0; - if libc::pthread_getaffinity_np(libc::pthread_self(), libc::_cpuset_size(set), set) == 0 { + if libc::pthread_getaffinity_np( + libc::pthread_self(), + libc::_cpuset_size(set), + set, + ) == 0 + { for i in 0..libc::cpuid_t::MAX { match libc::_cpuset_isset(i, set) { -1 => break, @@ -280,21 +284,26 @@ pub fn available_parallelism() -> io::Result> { Ok(unsafe { NonZero::new_unchecked(cpus as usize) }) } - target_os = "nto" => { - unsafe { - use libc::_syspage_ptr; - if _syspage_ptr.is_null() { - Err(io::const_error!(io::ErrorKind::NotFound, "no syspage available")) - } else { - let cpus = (*_syspage_ptr).num_cpu; - NonZero::new(cpus as usize) - .ok_or(io::Error::UNKNOWN_THREAD_COUNT) - } + any(target_os = "nto", target_os = "qnx") => unsafe { + use libc::_syspage_ptr; + if _syspage_ptr.is_null() { + Err(io::const_error!(io::ErrorKind::NotFound, "no syspage available")) + } else { + let cpus = (*_syspage_ptr).num_cpu; + NonZero::new(cpus as usize).ok_or(io::Error::UNKNOWN_THREAD_COUNT) } - } + }, any(target_os = "solaris", target_os = "illumos") => { let mut cpus = 0u32; - if unsafe { libc::pset_info(libc::PS_MYID, core::ptr::null_mut(), &mut cpus, core::ptr::null_mut()) } != 0 { + if unsafe { + libc::pset_info( + libc::PS_MYID, + core::ptr::null_mut(), + &mut cpus, + core::ptr::null_mut(), + ) + } != 0 + { return Err(io::Error::UNKNOWN_THREAD_COUNT); } Ok(unsafe { NonZero::new_unchecked(cpus as usize) }) @@ -318,14 +327,17 @@ pub fn available_parallelism() -> io::Result> { // expectations than the actual cores availability. // SAFETY: `vxCpuEnabledGet` always fetches a mask with at least one bit set - unsafe{ + unsafe { let set = libc::vxCpuEnabledGet(); Ok(NonZero::new_unchecked(set.count_ones() as usize)) } } _ => { - // FIXME: implement on Redox, l4re - Err(io::const_error!(io::ErrorKind::Unsupported, "getting the number of hardware threads is not supported on the target platform")) + // FIXME: implement on l4re + Err(io::const_error!( + io::ErrorKind::Unsupported, + "getting the number of hardware threads is not supported on the target platform" + )) } } } @@ -343,13 +355,15 @@ pub fn current_os_id() -> Option { // `libc::gettid` is only available on glibc 2.30+, but the syscall is available // since Linux 2.4.11. - syscall!(fn gettid() -> libc::pid_t;); + syscall!( + fn gettid() -> libc::pid_t; + ); // SAFETY: FFI call with no preconditions. let id: libc::pid_t = unsafe { gettid() }; Some(id as u64) } - target_os = "nto" => { + any(target_os = "nto", target_os = "qnx") => { // SAFETY: FFI call with no preconditions. let id: libc::pid_t = unsafe { libc::gettid() }; Some(id as u64) @@ -380,11 +394,7 @@ pub fn current_os_id() -> Option { let mut id = 0u64; // SAFETY: `thread_id` is a valid pointer, no other preconditions. let status: libc::c_int = unsafe { libc::pthread_threadid_np(0, &mut id) }; - if status == 0 { - Some(id) - } else { - None - } + if status == 0 { Some(id) } else { None } } // Other platforms don't have an OS thread ID or don't have a way to access it. _ => None, @@ -394,11 +404,13 @@ pub fn current_os_id() -> Option { #[cfg(any( target_os = "linux", target_os = "nto", + target_os = "qnx", target_os = "solaris", target_os = "illumos", target_os = "vxworks", target_os = "cygwin", target_vendor = "apple", + target_os = "netbsd", ))] fn truncate_cstr(cstr: &CStr) -> [libc::c_char; MAX_WITH_NUL] { let mut result = [0; MAX_WITH_NUL]; @@ -470,7 +482,12 @@ pub fn set_name(name: &CStr) { #[cfg(target_os = "netbsd")] pub fn set_name(name: &CStr) { + // See https://github.com/NetBSD/src/blob/8d40872b4c550a802379f3b9c22a40212d5e149d/lib/libpthread/pthread.h#L281 + // FIXME: move to libc. + const PTHREAD_MAX_NAMELEN_NP: usize = 32; + unsafe { + let name = truncate_cstr::<{ PTHREAD_MAX_NAMELEN_NP }>(name); let res = libc::pthread_setname_np( libc::pthread_self(), c"%s".as_ptr(), @@ -480,14 +497,14 @@ pub fn set_name(name: &CStr) { } } -#[cfg(any(target_os = "solaris", target_os = "illumos", target_os = "nto"))] +#[cfg(any(target_os = "solaris", target_os = "illumos", target_os = "nto", target_os = "qnx"))] pub fn set_name(name: &CStr) { weak!( fn pthread_setname_np(thread: libc::pthread_t, name: *const libc::c_char) -> libc::c_int; ); if let Some(f) = pthread_setname_np.get() { - #[cfg(target_os = "nto")] + #[cfg(any(target_os = "nto", target_os = "qnx"))] const THREAD_NAME_MAX: usize = libc::_NTO_THREAD_NAME_MAX as usize; #[cfg(any(target_os = "solaris", target_os = "illumos"))] const THREAD_NAME_MAX: usize = 32; @@ -558,12 +575,18 @@ pub fn sleep(dur: Duration) { // wasi-libc prior to WebAssembly/wasi-libc#696 has a broken implementation // of `nanosleep` which used `CLOCK_REALTIME` even though it is unsupported // on WASIp2. Using `clock_nanosleep` directly bypasses the issue. - unsafe fn nanosleep(rqtp: *const libc::timespec, rmtp: *mut libc::timespec) -> libc::c_int { + unsafe fn nanosleep( + rqtp: *const libc::timespec, + rmtp: *mut libc::timespec, + ) -> libc::c_int { unsafe { libc::clock_nanosleep(crate::sys::time::Instant::CLOCK_ID, 0, rqtp, rmtp) } } } _ => { - unsafe fn nanosleep(rqtp: *const libc::timespec, rmtp: *mut libc::timespec) -> libc::c_int { + unsafe fn nanosleep( + rqtp: *const libc::timespec, + rmtp: *mut libc::timespec, + ) -> libc::c_int { let r = unsafe { libc::nanosleep(rqtp, rmtp) }; // `clock_nanosleep` returns the error number directly, so mimic // that behaviour to make the shared code below simpler. @@ -579,10 +602,10 @@ pub fn sleep(dur: Duration) { // nanosleep will fill in `ts` with the remaining time. unsafe { while secs > 0 || nsecs > 0 { - let mut ts = libc::timespec { - tv_sec: cmp::min(libc::time_t::MAX as u64, secs) as libc::time_t, - tv_nsec: nsecs, - }; + let mut ts = libc::timespec::default(); + ts.tv_sec = cmp::min(libc::time_t::MAX as u64, secs) as libc::time_t; + ts.tv_nsec = nsecs; + secs -= ts.tv_sec as u64; let ts_ptr = &raw mut ts; let r = nanosleep(ts_ptr, ts_ptr); diff --git a/library/std/src/sys/thread/xous.rs b/library/std/src/sys/thread/xous.rs index 208d43bb2c065..3ddd45851dde2 100644 --- a/library/std/src/sys/thread/xous.rs +++ b/library/std/src/sys/thread/xous.rs @@ -58,11 +58,11 @@ impl Thread { .map_err(|code| io::Error::from_raw_os_error(code as i32))? }; - let guard_page_pre = stack_plus_guard_pages.as_ptr() as usize; + let guard_page_pre = stack_plus_guard_pages.as_ptr(); let tid = create_thread( - thread_start as *mut usize, + thread_start, &mut stack_plus_guard_pages[GUARD_PAGE_SIZE..(stack_size + GUARD_PAGE_SIZE)], - data as usize, + data, guard_page_pre, stack_size, 0, @@ -75,7 +75,7 @@ impl Thread { rust_start(); } - extern "C" fn thread_start( + unsafe extern "C" fn thread_start( data: *mut usize, guard_page_pre: usize, stack_size: usize, diff --git a/library/std/src/sys/thread_local/destructors/list.rs b/library/std/src/sys/thread_local/destructors/list.rs index 44e00c8a5ae59..dc767639797fb 100644 --- a/library/std/src/sys/thread_local/destructors/list.rs +++ b/library/std/src/sys/thread_local/destructors/list.rs @@ -11,6 +11,11 @@ pub unsafe fn register(t: *mut u8, dtor: unsafe extern "C" fn(*mut u8)) { rtabort!("the System allocator may not use TLS with destructors") }; guard::enable(); + + // Avoid calling the alloc error hook + if dtors.capacity() == dtors.len() { + dtors.try_reserve(1).unwrap_or_else(|_| rtabort!("Failed to grow TLS destructor list")) + } dtors.push((t, dtor)); } diff --git a/library/std/src/sys/thread_local/guard/windows.rs b/library/std/src/sys/thread_local/guard/windows.rs index f747129465d6d..d59631d5d6ca3 100644 --- a/library/std/src/sys/thread_local/guard/windows.rs +++ b/library/std/src/sys/thread_local/guard/windows.rs @@ -1,103 +1,267 @@ //! Support for Windows TLS destructors. //! -//! Unfortunately, Windows does not provide a nice API to provide a destructor -//! for a TLS variable. Thus, the solution here ended up being a little more -//! obscure, but fear not, the internet has informed me [1][2] that this solution -//! is not unique (no way I could have thought of it as well!). The key idea is -//! to insert some hook somewhere to run arbitrary code on thread termination. -//! With this in place we'll be able to run anything we like, including all -//! TLS destructors! +//! Windows has an API to provide a destructor for a FLS (fiber local storage) variable, +//! which behaves similarly to a TLS variable for our purpose [1]. //! -//! In order to realize this, all TLS destructors are tracked by *us*, not the -//! Windows runtime. This means that we have a global list of destructors for +//! All TLS destructors are tracked by *us*, not the Windows runtime. +//! This means that we have a global list of destructors for //! each TLS key or variable that we know about. //! -//! # What's up with CRT$XLB? -//! -//! For anything about TLS destructors to work on Windows, we have to be able -//! to run *something* when a thread exits. To do so, we place a very special -//! static in a very special location. If this is encoded in just the right -//! way, the kernel's loader is apparently nice enough to run some function -//! of ours whenever a thread exits! How nice of the kernel! -//! -//! Lots of detailed information can be found in source [1] above, but the -//! gist of it is that this is leveraging a feature of Microsoft's PE format -//! (executable format) which is not actually used by any compilers today. -//! This apparently translates to any callbacks in the ".CRT$XLB" section -//! being run on certain events. -//! -//! So after all that, we use the compiler's `#[link_section]` feature to place -//! a callback pointer into the magic section so it ends up being called. -//! -//! # What's up with this callback? -//! -//! The callback specified receives a number of parameters from... someone! -//! (the kernel? the runtime? I'm not quite sure!) There are a few events that -//! this gets invoked for, but we're currently only interested on when a -//! thread or a process "detaches" (exits). The process part happens for the -//! last thread and the thread part happens for any normal thread. -//! -//! # The article mentions weird stuff about "/INCLUDE"? -//! -//! It sure does! Specifically we're talking about this quote: -//! -//! ```quote -//! The Microsoft run-time library facilitates this process by defining a -//! memory image of the TLS Directory and giving it the special name -//! “__tls_used” (Intel x86 platforms) or “_tls_used” (other platforms). The -//! linker looks for this memory image and uses the data there to create the -//! TLS Directory. Other compilers that support TLS and work with the -//! Microsoft linker must use this same technique. -//! ``` -//! -//! Basically what this means is that if we want support for our TLS -//! destructors/our hook being called then we need to make sure the linker does -//! not omit this symbol. Otherwise it will omit it and our callback won't be -//! wired up. -//! -//! We don't actually use the `/INCLUDE` linker flag here like the article -//! mentions because the Rust compiler doesn't propagate linker flags, but -//! instead we use a shim function which performs a volatile 1-byte load from -//! the address of the _tls_used symbol to ensure it sticks around. -//! -//! [1]: https://www.codeproject.com/Articles/8113/Thread-Local-Storage-The-C-Way -//! [2]: https://github.com/ChromiumWebApps/chromium/blob/master/base/threading/thread_local_storage_win.cc#L42 +//! [1]: https://devblogs.microsoft.com/oldnewthing/20191011-00/?p=102989 use core::ffi::c_void; +use core::sync::atomic::{AtomicBool, AtomicU32, Ordering, fence}; +use crate::cell::Cell; use crate::ptr; -use crate::sys::c; +use crate::sys::c::{self, FLS_OUT_OF_INDEXES}; + +pub type Key = u32; + +unsafe fn create(dtor: c::PFLS_CALLBACK_FUNCTION) -> Key { + let key_result = unsafe { c::FlsAlloc(dtor) }; + + if key_result == c::FLS_OUT_OF_INDEXES { + rtabort!("out of FLS keys"); + } + + key_result +} + +unsafe fn set(key: Key, ptr: *const c_void) { + let result = unsafe { c::FlsSetValue(key, ptr) }; + + if result == c::FALSE { + rtabort!("failed to set FLS value"); + } +} + +fn is_thread_a_fiber() -> bool { + let res = unsafe { c::IsThreadAFiber() }; + res == c::TRUE +} + +static KEY: AtomicU32 = AtomicU32::new(FLS_OUT_OF_INDEXES); + +/// Used to track whether we are currently in the critical section of `enable`. +/// For miri, these atomic operations cause synchronization that can mask user bugs, +/// and they are not needed as `atexit` is anyway not supported, so we can skip them. +struct EnableGuard; +static AT_EXIT_HOOK_CALLED: AtomicBool = AtomicBool::new(false); +static ACTIVE_ENABLE_CALLS: AtomicU32 = AtomicU32::new(0); + +impl EnableGuard { + // Mark the start of an `enable` call, returning whether the `atexit` hook has already been called or not. + fn new() -> (Self, bool) { + if cfg!(miri) { + return (Self, false); + } + ACTIVE_ENABLE_CALLS.fetch_add(1, Ordering::Relaxed); + + // Both `new` and `start_exit` publish state to one atomic and inspect the other. + // `AcqRel` is insufficient because neither read is required to observe the other's publication, + // so we could create the guard but `start_exit` would not see any active enable calls. + // `SeqCst` ensures that there's a single global order between the publish and check, + // so at least one side must observe the other and bail. + fence(Ordering::SeqCst); + + let at_exit_called = AT_EXIT_HOOK_CALLED.load(Ordering::Relaxed); + + (Self, at_exit_called) + } + + /// Mark the start of process exit, returning whether we should free the FLS key or not. + fn start_exit() -> bool { + // After this hook starts, new destructor registration will be skipped, + // causing TLS destructors initialized after this point to leak. + if AT_EXIT_HOOK_CALLED.swap(true, Ordering::Relaxed) { + // Cleanup already started, there is nothing else to do. + return false; + } -unsafe extern "C" { - #[link_name = "_tls_used"] - static TLS_USED: u8; + fence(Ordering::SeqCst); + + let any_active_enabled_called = ACTIVE_ENABLE_CALLS.load(Ordering::Relaxed) != 0; + + if any_active_enabled_called { + // If another thread is currently in `enable`, it may already have loaded this key and may be about to call `FlsSetValue`. + // So we must *not* call free the FLS key. + // + // During real process exit this is harmless because the `cleanup` hook is always available, + // and the FLS callback will be triggered normally by the OS. + // + // During DLL unload, the unloader cannot safely have threads running code from the DLL except for the destructors, + // so there must not be any `enable` calls active anyway. + return false; + } + + true + } } + +#[cfg(not(miri))] +impl Drop for EnableGuard { + fn drop(&mut self) { + ACTIVE_ENABLE_CALLS.fetch_sub(1, Ordering::Relaxed); + } +} + +/// Set up the current thread to invoke `cleanup` when it finishes. pub fn enable() { - // When destructors are used, we need to add a reference to the _tls_used - // symbol provided by the CRT, otherwise the TLS support code will get - // GC'd by the linker and our callback won't be called. - unsafe { ptr::from_ref(&TLS_USED).read_volatile() }; - // We also need to reference CALLBACK to make sure it does not get GC'd - // by the compiler/LLVM. The callback will end up inside the TLS - // callback array pointed to by _TLS_USED through linker shenanigans, - // but as far as the compiler is concerned, it looks like the data is - // unused, so we need this hack to prevent it from disappearing. - unsafe { ptr::from_ref(&CALLBACK).read_volatile() }; + let registered = if cfg!(target_thread_local) { + #[thread_local] + static REGISTERED: Cell = Cell::new(false); + REGISTERED.replace(true) + } else { + // `#[thread_local]` is unavailable on windows-gnu (`target_thread_local` is off), + // but setting the FLS key's value is about as expensive as `TlsGet`, so we don't bother tracking registration separately. + false + }; + + if !registered { + // We are in a critical section where we are trying to register a destructor for the current thread. + // We need to avoid racing with the `atexit` hook that frees the FLS slot, which would cause us to call `FlsSetValue` on a freed key, + // or calling `atexit` during process shutdown, which would cause a deadlock. + let (_guard, at_exit_called) = EnableGuard::new(); + + if at_exit_called { + // We are exiting and don't want to race with the `atexit` hook, so we won't be able to run the destructors for this thread. + return; + } + + let current_key = KEY.load(Ordering::Acquire); + + // If we already allocated a key, we only need to set it to a non-null value so that the destructors hook is run for this thread. + let key = if current_key != FLS_OUT_OF_INDEXES { + current_key + } else { + // Otherwise, we try to allocate a key. + let new_key = unsafe { create(Some(cleanup)) }; + + // Now we need to set this key to be used by everyone else. + // If we won the race, our key is the right one and we can set it to non-null value. + // If we lost, we'll use the winning key and free our losing key. + match KEY.compare_exchange(current_key, new_key, Ordering::Release, Ordering::Acquire) { + Ok(_) => { + // If the current DLL is unloaded, the registered `cleanup` hook will not be available later during thread exit, + // triggering a `STATUS_ACCESS_VIOLATION`. To avoid this, we use the `atexit` hook, which is called during DLL unload + // to manually free the FLS slot, triggering the destructors. + // + // However, calling `atexit` during process exit can cause a deadlock. + // In a Rust binary, `enable` is called during the main thread startup and before any user code, + // and we checked using `at_exit_called` that we aren't in process shutdown. + // + // In a Rust DLL, dynamic unloading can only happen safely when no other threads are + // concurrently executing Rust code, so if we are here we cannot be unloading yet. + // + // If a main non-Rust binary is exiting, it must not be trigger the `enable` guard + // for the first time during process shutdown. + // + // Miri has no DLL unloading so we can skip this step here. + if !cfg!(miri) { + if cleanup_is_unloadable() { + let res = unsafe { c::atexit(free_fls_key_at_exit) }; + if res != 0 { + rtabort!("failed to register fls atexit hook"); + } + } + } + + new_key + } + Err(other_key) => { + unsafe { c::FlsFree(new_key) }; + other_key + } + } + }; + + // Setting the key's value to non-zero will cause the dtor callback to be called when the thread exits. + unsafe { set(key, ptr::without_provenance(1)) }; + } } -#[unsafe(link_section = ".CRT$XLB")] -#[cfg_attr(miri, used)] // Miri only considers explicitly `#[used]` statics for `lookup_link_section` -pub static CALLBACK: unsafe extern "system" fn(*mut c_void, u32, *mut c_void) = tls_callback; +/// Checks if `cleanup` is in a different module from the main executable, +/// using `GetModuleHandleExW(FLAG_FROM_ADDRESS, cleanup) != GetModuleHandleW(ptr::null())`. +/// +/// If `cleanup` lives in the main executable, its code cannot be unmapped +/// before process exit, so no unload hook is needed. +/// +/// If it lives in a DLL, the DLL may be unloaded while the process keeps +/// running, so the FLS callback must be unregistered before that image is +/// unmapped. +/// +/// On failure, return true, which assumes it can be unloaded. +fn cleanup_is_unloadable() -> bool { + // Get a handle to the module of `cleanup`. + let cleanup_module = { + let mut handle: c::HMODULE = ptr::null_mut(); -unsafe extern "system" fn tls_callback(_h: *mut c_void, dw_reason: u32, _pv: *mut c_void) { - if dw_reason == c::DLL_THREAD_DETACH || dw_reason == c::DLL_PROCESS_DETACH { - unsafe { - #[cfg(target_thread_local)] - super::super::destructors::run(); - #[cfg(not(target_thread_local))] - super::super::key::run_dtors(); + let res = unsafe { + c::GetModuleHandleExW( + c::GET_MODULE_HANDLE_EX_FLAG_FROM_ADDRESS + | c::GET_MODULE_HANDLE_EX_FLAG_UNCHANGED_REFCOUNT, + cleanup as *const () as c::PCWSTR, + &mut handle, + ) + }; - crate::rt::thread_cleanup(); + if res == c::FALSE || handle.is_null() { + return true; } + + handle + }; + + // Get a handle to the file used to create the calling process (.exe file). + let main_exe_module = unsafe { c::GetModuleHandleW(ptr::null()) }; + + if main_exe_module.is_null() { + return true; + } + + cleanup_module != main_exe_module +} + +extern "C" fn free_fls_key_at_exit() { + // The main purpose of this hook is to free the FLS slot during DLL unload. + // However, this hook will also be called during normal process exit, while other Rust threads are still running, + // so we must be careful to avoid races with `enable`. + let should_free_key = EnableGuard::start_exit(); + if !should_free_key { + return; } + + let current_key = KEY.swap(c::FLS_OUT_OF_INDEXES, Ordering::AcqRel); + if current_key != c::FLS_OUT_OF_INDEXES { + // Calling `FlsFree` will cause the OS to call the `cleanup` hook, in the current thread, *for each thread* (or fiber) with a value in this FLS slot. + // `cleanup` is safe to run repeatedly: it only drains the current thread's TLS destructor list, and we check that we are not running in a fiber before doing so. + // We only call this when no `enable` call is active, so it cannot race with `FlsSetValue` using this key. + // Destructors of thread locals in other threads will not run and therefore leak, which is allowed since we are exiting or unloading. + unsafe { c::FlsFree(current_key) }; + } +} + +unsafe extern "system" fn cleanup(_ptr: *const c_void) { + // Avoid running the hook if we are in a fiber. + // This will cause destructors of thread locals to not run, leaking them. + // Thread-local runtime state will not be cleaned. + // + // We need to verify that we won't run the destructors *before* the thread exits, + // but if the fiber that registered the callback is deleted, the thread might still be running other fibers. + // + // By checking that we are not running in a fiber here, we are guaranteed that the hook is only running during the thread's exit. + // See also the `fiber_does_not_trigger_dtor` test. + if is_thread_a_fiber() { + return; + } + + unsafe { + #[cfg(target_thread_local)] + super::super::destructors::run(); + #[cfg(not(target_thread_local))] + super::super::key::run_dtors(); + } + + crate::rt::thread_cleanup(); } diff --git a/library/std/src/sys/thread_local/key/racy.rs b/library/std/src/sys/thread_local/key/racy.rs index a12ff7ac36ba5..37ccb10337cf9 100644 --- a/library/std/src/sys/thread_local/key/racy.rs +++ b/library/std/src/sys/thread_local/key/racy.rs @@ -21,12 +21,12 @@ pub struct LazyKey { // Define a sentinel value that is likely not to be returned // as a TLS key. -#[cfg(not(target_os = "nto"))] +#[cfg(not(any(target_os = "nto", target_os = "qnx")))] const KEY_SENTVAL: usize = 0; -// On QNX Neutrino, 0 is always returned when currently not in use. -// Using 0 would mean to always create two keys and remote the first +// On QNX SDP, 0 is always returned when currently not in use. +// Using 0 would mean to always create two keys and remove the first // one (with value of 0) immediately afterwards. -#[cfg(target_os = "nto")] +#[cfg(any(target_os = "nto", target_os = "qnx"))] const KEY_SENTVAL: usize = libc::PTHREAD_KEYS_MAX + 1; impl LazyKey { @@ -42,6 +42,7 @@ impl LazyKey { } } + #[cold] fn lazy_init(&self) -> usize { // POSIX allows the key created here to be KEY_SENTVAL, but the compare_exchange // below relies on using KEY_SENTVAL as a sentinel value to check who won the diff --git a/library/std/src/sys/thread_local/key/tests.rs b/library/std/src/sys/thread_local/key/tests.rs index c7d2c8e6301ef..33c7f2dbd8b31 100644 --- a/library/std/src/sys/thread_local/key/tests.rs +++ b/library/std/src/sys/thread_local/key/tests.rs @@ -1,3 +1,13 @@ +#![allow( + clippy::arithmetic_side_effects, + clippy::expect_used, + clippy::unwrap_used, + clippy::indexing_slicing, + clippy::panic, + clippy::unreachable, + clippy::unimplemented +)] + use super::{LazyKey, get, set}; use crate::ptr; @@ -18,8 +28,8 @@ fn smoke() { assert!(get(k2).is_null()); set(k1, ptr::without_provenance_mut(1)); set(k2, ptr::without_provenance_mut(2)); - assert_eq!(get(k1) as usize, 1); - assert_eq!(get(k2) as usize, 2); + assert_eq!(get(k1).addr(), 1); + assert_eq!(get(k2).addr(), 2); } } diff --git a/library/std/src/sys/thread_local/key/unix.rs b/library/std/src/sys/thread_local/key/unix.rs index 8fa24265e432a..a43eaf6dfaae5 100644 --- a/library/std/src/sys/thread_local/key/unix.rs +++ b/library/std/src/sys/thread_local/key/unix.rs @@ -31,10 +31,18 @@ pub fn create(dtor: Option) -> Key { key } +#[cold] +fn fail() -> ! { + rtabort!("Unexpected TLS failure") +} + #[inline] pub unsafe fn set(key: Key, value: *mut u8) { let r = unsafe { libc::pthread_setspecific(key, value as *mut _) }; - debug_assert_eq!(r, 0); + // May happen on memory exhaustion + if r != 0 { + fail() + } } #[inline] @@ -46,5 +54,8 @@ pub unsafe fn get(key: Key) -> *mut u8 { #[inline] pub unsafe fn destroy(key: Key) { let r = unsafe { libc::pthread_key_delete(key) }; - debug_assert_eq!(r, 0); + // only documented error is for invalid keys + if r != 0 { + fail() + } } diff --git a/library/std/src/sys/thread_local/key/windows.rs b/library/std/src/sys/thread_local/key/windows.rs index 2ff0fd1196e12..36c744d92d9f2 100644 --- a/library/std/src/sys/thread_local/key/windows.rs +++ b/library/std/src/sys/thread_local/key/windows.rs @@ -47,6 +47,11 @@ pub struct LazyKey { once: UnsafeCell, } +#[cold] +fn fail() -> ! { + rtabort!("Unexpected TLS failure") +} + impl LazyKey { #[inline] pub const fn new(dtor: Option) -> LazyKey { @@ -60,9 +65,15 @@ impl LazyKey { #[inline] pub fn force(&'static self) -> Key { - match self.key.load(Acquire) { - 0 => unsafe { self.init() }, - key => key - 1, + if self.dtor.is_some() { + // Needs to be called on all threads where the key might have a non-null value! + // Otherwise, `run_dtors` might not be called on this thread. + guard::enable(); + } + + match self.key.load(Acquire).checked_sub(1) { + None => unsafe { self.init() }, + Some(dec) => dec, } } @@ -73,11 +84,13 @@ impl LazyKey { let r = unsafe { c::InitOnceBeginInitialize(self.once.get(), 0, &mut pending, ptr::null_mut()) }; - assert_eq!(r, c::TRUE); + if r != c::TRUE { + fail() + } if pending == c::FALSE { // Some other thread initialized the key, load it. - self.key.load(Relaxed) - 1 + self.key.load(Relaxed).wrapping_sub(1) } else { let key = unsafe { c::TlsAlloc() }; if key == c::TLS_OUT_OF_INDEXES { @@ -88,6 +101,8 @@ impl LazyKey { } unsafe { + // Add ourselves to the `DTORS` list, so that when `run_dtors` gets called, + // our dtor is invoked. register_dtor(self); } @@ -96,10 +111,12 @@ impl LazyKey { // and if that sees this write then it will entirely bypass the `InitOnce`. We thus // need to establish synchronization through `key`. In particular that acquire load // must happen-after the register_dtor above, to ensure the dtor actually runs! - self.key.store(key + 1, Release); + self.key.store(key.wrapping_add(1), Release); let r = unsafe { c::InitOnceComplete(self.once.get(), 0, ptr::null_mut()) }; - debug_assert_eq!(r, c::TRUE); + if r != c::TRUE { + fail() + } key } @@ -111,14 +128,16 @@ impl LazyKey { rtabort!("out of TLS indexes"); } - match self.key.compare_exchange(0, key + 1, AcqRel, Acquire) { + match self.key.compare_exchange(0, key.wrapping_add(1), AcqRel, Acquire) { Ok(_) => key, Err(new) => unsafe { // Some other thread completed initialization first, so destroy // our key and use theirs. let r = c::TlsFree(key); - debug_assert_eq!(r, c::TRUE); - new - 1 + if r != c::TRUE { + fail() + } + new.wrapping_sub(1) }, } } @@ -131,7 +150,10 @@ unsafe impl Sync for LazyKey {} #[inline] pub unsafe fn set(key: Key, val: *mut u8) { let r = unsafe { c::TlsSetValue(key, val.cast()) }; - debug_assert_eq!(r, c::TRUE); + // According to MS documentation, `TlsSetValue` returns zero "if it fails" + if r != c::TRUE { + fail() + } } #[inline] @@ -144,8 +166,6 @@ static DTORS: Atomic<*mut LazyKey> = AtomicPtr::new(ptr::null_mut()); /// Should only be called once per key, otherwise loops or breaks may occur in /// the linked list. unsafe fn register_dtor(key: &'static LazyKey) { - guard::enable(); - let this = <*const LazyKey>::cast_mut(key); // Use acquire ordering to pass along the changes done by the previously // registered keys when we store the new head with release ordering. @@ -168,22 +188,21 @@ pub unsafe fn run_dtors() { let mut cur = DTORS.load(Acquire); while !cur.is_null() { let pre_key = unsafe { (*cur).key.load(Acquire) }; - let dtor = unsafe { (*cur).dtor.unwrap() }; + let dtor = unsafe { rtunwrap!(Some, (*cur).dtor) }; cur = unsafe { (*cur).next.load(Relaxed) }; // In LazyKey::init, we register the dtor before setting `key`. // So if one thread's `run_dtors` races with another thread executing `init` on the same // `LazyKey`, we can encounter a key of 0 here. That means this key was never // initialized in this thread so we can safely skip it. - if pre_key == 0 { + let Some(key) = pre_key.checked_sub(1) else { continue; - } + }; + // If this is non-zero, then via the `Acquire` load above we synchronized with // everything relevant for this key. (It's not clear that this is needed, since the // release-acquire pair on DTORS also establishes synchronization, but better safe than // sorry.) - let key = pre_key - 1; - let ptr = unsafe { c::TlsGetValue(key) }; if !ptr.is_null() { unsafe { diff --git a/library/std/src/sys/thread_local/key/xous.rs b/library/std/src/sys/thread_local/key/xous.rs index db83d2bf4a13a..02b68df38ab68 100644 --- a/library/std/src/sys/thread_local/key/xous.rs +++ b/library/std/src/sys/thread_local/key/xous.rs @@ -68,48 +68,54 @@ unsafe extern "Rust" { static DTORS: Atomic<*mut Node>; } +#[inline] fn tls_ptr_addr() -> *mut *mut u8 { - let mut tp: usize; + let tp: *mut *mut u8; unsafe { asm!( "mv {}, tp", out(reg) tp, ); } - core::ptr::with_exposed_provenance_mut::<*mut u8>(tp) + tp } /// Creates an area of memory that's unique per thread. This area will /// contain all thread local pointers. +#[inline] fn tls_table() -> &'static mut [*mut u8] { let tp = tls_ptr_addr(); if !tp.is_null() { - return unsafe { - core::slice::from_raw_parts_mut(tp, TLS_MEMORY_SIZE / size_of::<*mut u8>()) - }; + unsafe { core::slice::from_raw_parts_mut(tp, TLS_MEMORY_SIZE / size_of::<*mut u8>()) } + } else { + tls_table_slow() } +} + +#[cold] +fn tls_table_slow() -> &'static mut [*mut u8] { // If the TP register is `0`, then this thread hasn't initialized // its TLS yet. Allocate a new page to store this memory. - let tp = unsafe { + let tp: &mut [*mut u8] = unsafe { map_memory( None, None, TLS_MEMORY_SIZE / size_of::<*mut u8>(), MemoryFlags::R | MemoryFlags::W, ) - .expect("Unable to allocate memory for thread local storage") + .unwrap_or_else(|_| rtabort!("Unable to allocate memory for thread local storage")) }; for val in tp.iter() { - assert!(*val as usize == 0); + rtassert!((*val).is_null()); } unsafe { // Set the thread's `$tp` register asm!( "mv tp, {}", - in(reg) tp.as_mut_ptr() as usize, + in(reg) tp.as_mut_ptr(), ); } tp @@ -128,15 +134,16 @@ pub fn create(dtor: Option) -> Key { #[inline] pub unsafe fn set(key: Key, value: *mut u8) { - assert!((key < 1022) && (key >= 1)); + rtassert!((key < 1022) && (key >= 1)); let table = tls_table(); - table[key] = value; + *rtunwrap!(Some, table.get_mut(key)) = value; } #[inline] pub unsafe fn get(key: Key) -> *mut u8 { - assert!((key < 1022) && (key >= 1)); - tls_table()[key] + rtassert!((key < 1022) && (key >= 1)); + let table = tls_table(); + *rtunwrap!(Some, table.get(key)) } #[inline] @@ -180,10 +187,10 @@ pub unsafe fn destroy_tls() { unsafe { run_dtors() }; // Finally, free the TLS array - unsafe { + let result = unsafe { unmap_memory(core::slice::from_raw_parts_mut(tp, TLS_MEMORY_SIZE / size_of::())) - .unwrap() }; + rtunwrap!(Ok, result); } // This is marked inline(never) to prevent dealloc calls from being reordered diff --git a/library/std/src/sys/thread_local/mod.rs b/library/std/src/sys/thread_local/mod.rs index e88011aa22dad..809ef5cfe9c60 100644 --- a/library/std/src/sys/thread_local/mod.rs +++ b/library/std/src/sys/thread_local/mod.rs @@ -22,10 +22,20 @@ reason = "internal details of the thread_local macro", issue = "none" )] +#![deny( + clippy::arithmetic_side_effects, + clippy::expect_used, + clippy::unwrap_used, + clippy::indexing_slicing, + clippy::panic, + clippy::unreachable, + clippy::unimplemented, + reason = "TLS accesses must not call the global allocator, including via panic (#160930)" +)] cfg_select! { any( - all(target_family = "wasm", not(target_feature = "atomics")), + all(target_family = "wasm", not(target_feature = "atomics"), not(target_env = "p3")), target_os = "uefi", target_os = "zkvm", target_os = "trusty", @@ -42,8 +52,8 @@ cfg_select! { } _ => { mod os; - pub use os::{Storage, thread_local_inner, value_align}; pub(crate) use os::{LocalPointer, local_pointer}; + pub use os::{Storage, thread_local_inner, value_align}; } } @@ -54,7 +64,10 @@ cfg_select! { /// destructor for each variable. On these platforms, we keep track of the /// destructors ourselves and register (through the [`guard`] module) only a /// single callback that runs all of the destructors in the list. -#[cfg(all(target_thread_local, not(all(target_family = "wasm", not(target_feature = "atomics")))))] +#[cfg(all( + target_thread_local, + not(all(target_family = "wasm", not(target_feature = "atomics"), not(target_env = "p3"))) +))] pub(crate) mod destructors { cfg_select! { any( @@ -81,7 +94,7 @@ pub(crate) mod destructors { /// This module provides a way to schedule the execution of the destructor list /// and the [runtime cleanup](crate::rt::thread_cleanup) function. Calling `enable` -/// should ensure that these functions are called at the right times. +/// sets up the current thread to ensure that these functions are called at the right times. pub(crate) mod guard { cfg_select! { all(target_thread_local, target_vendor = "apple") => { @@ -93,9 +106,7 @@ pub(crate) mod guard { pub(crate) use windows::enable; } any( - all(target_family = "wasm", not( - all(target_os = "wasi", target_env = "p1", target_feature = "atomics") - )), + all(target_family = "wasm", not(target_env = "p3")), target_os = "uefi", target_os = "zkvm", target_os = "trusty", @@ -115,10 +126,7 @@ pub(crate) mod guard { use crate::rt::thread_cleanup; } } - any( - target_os = "hermit", - target_os = "xous", - ) => { + any(target_os = "hermit", target_os = "xous") => { // `std` is the only runtime, so it just calls the destructor functions // itself when the time comes. pub(crate) fn enable() {} @@ -143,23 +151,19 @@ pub(crate) mod guard { pub(crate) mod key { cfg_select! { any( - all( - not(target_vendor = "apple"), - not(target_family = "wasm"), - target_family = "unix", - ), + all(not(target_vendor = "apple"), not(target_family = "wasm"), target_family = "unix"), all(not(target_thread_local), target_vendor = "apple"), target_os = "teeos", - all(target_os = "wasi", target_env = "p1", target_feature = "atomics"), + all(target_os = "wasi", target_env = "p3"), ) => { mod racy; mod unix; #[cfg(test)] mod tests; pub(super) use racy::LazyKey; - pub(super) use unix::{Key, set}; #[cfg(any(not(target_thread_local), test))] pub(super) use unix::get; + pub(super) use unix::{Key, set}; use unix::{create, destroy}; } all(not(target_thread_local), target_os = "windows") => { @@ -191,9 +195,9 @@ pub(crate) mod key { mod racy; #[cfg(test)] mod tests; - pub(super) use racy::LazyKey; pub(super) use moto_rt::tls::{Key, get, set}; use moto_rt::tls::{create, destroy}; + pub(super) use racy::LazyKey; } _ => {} } diff --git a/library/std/src/sys/thread_local/native/eager.rs b/library/std/src/sys/thread_local/native/eager.rs index 23abad645c1a3..0acef0bfcc597 100644 --- a/library/std/src/sys/thread_local/native/eager.rs +++ b/library/std/src/sys/thread_local/native/eager.rs @@ -4,8 +4,8 @@ use crate::sys::thread_local::{abort_on_dtor_unwind, destructors}; #[derive(Clone, Copy)] enum State { - Initial, - Alive, + Alive = 0, + Unregistered, Destroyed, } @@ -19,7 +19,7 @@ pub struct Storage { impl Storage { pub const fn new(val: T) -> Storage { - Storage { state: Cell::new(State::Initial), val: UnsafeCell::new(val) } + Storage { state: Cell::new(State::Unregistered), val: UnsafeCell::new(val) } } /// Gets a pointer to the TLS value. If the TLS variable has been destroyed, @@ -32,16 +32,22 @@ impl Storage { /// The `self` reference must remain valid until the TLS destructor is run. #[inline] pub unsafe fn get(&self) -> *const T { - match self.state.get() { - State::Alive => self.val.get(), - State::Destroyed => ptr::null(), - State::Initial => unsafe { self.initialize() }, + if let State::Alive = self.state.get() { + self.val.get() + } else { + unsafe { self.get_or_init_slow() } } } #[cold] - unsafe fn initialize(&self) -> *const T { - // Register the destructor + unsafe fn get_or_init_slow(&self) -> *const T { + match self.state.get() { + State::Unregistered => {} + State::Alive => return self.val.get(), + State::Destroyed => return ptr::null(), + } + + // Register the destructor. // SAFETY: // The caller guarantees that `self` will be valid until thread destruction. diff --git a/library/std/src/sys/thread_local/native/lazy.rs b/library/std/src/sys/thread_local/native/lazy.rs index 02939a74fc089..c9bf5ea74c92f 100644 --- a/library/std/src/sys/thread_local/native/lazy.rs +++ b/library/std/src/sys/thread_local/native/lazy.rs @@ -95,7 +95,7 @@ where // as we've already registered the destructor. State::Alive => unsafe { old_value.assume_init_drop() }, - State::Destroyed(_) => unreachable!(), + State::Destroyed(_) => rtabort!("unreachable"), } self.value.get().cast() diff --git a/library/std/src/sys/thread_local/no_threads.rs b/library/std/src/sys/thread_local/no_threads.rs index 27a589a4a76ac..9f4e7710dffb7 100644 --- a/library/std/src/sys/thread_local/no_threads.rs +++ b/library/std/src/sys/thread_local/no_threads.rs @@ -5,6 +5,9 @@ use crate::cell::{Cell, UnsafeCell}; use crate::mem::MaybeUninit; use crate::ptr; +#[cfg(target_has_threads)] +compile_error!("Using no_threads implementation on a target with threads"); + #[doc(hidden)] #[allow_internal_unstable(thread_local_internals)] #[allow_internal_unsafe] @@ -92,7 +95,7 @@ impl LazyStorage { let value = i.and_then(Option::take).unwrap_or_else(f); // Destroy the old value if it is initialized - // FIXME(#110897): maybe panic on recursive initialization. + // FIXME(#110897): maybe abort on recursive initialization. if self.state.get() == State::Alive { self.state.set(State::Destroying); // Safety: we check for no initialization during drop below @@ -104,7 +107,7 @@ impl LazyStorage { // Guard against initialization during drop if self.state.get() == State::Destroying { - panic!("Attempted to initialize thread-local while it is being dropped"); + rtabort!("Attempted to initialize thread-local while it is being dropped"); } unsafe { diff --git a/library/std/src/sys/thread_local/os.rs b/library/std/src/sys/thread_local/os.rs index 3f06c9bd1d774..428339a16f4ea 100644 --- a/library/std/src/sys/thread_local/os.rs +++ b/library/std/src/sys/thread_local/os.rs @@ -1,6 +1,6 @@ use super::key::{Key, LazyKey, get, set}; use super::{abort_on_dtor_unwind, guard}; -use crate::alloc::{self, GlobalAlloc, Layout, System}; +use crate::alloc::{GlobalAlloc, Layout, System}; use crate::cell::Cell; use crate::marker::PhantomData; use crate::mem::ManuallyDrop; @@ -62,25 +62,7 @@ pub macro thread_local_inner { // by translating it into a `cfg`ed block and recursing. // https://doc.rust-lang.org/reference/conditional-compilation.html#railroad-ConfigurationPredicate - (@align $final_align:ident, cfg_attr(true, $($cfg_rhs:tt)*) $(, $($attr_rest:tt)+)?) => { - #[cfg(true)] - { - $crate::thread::local_impl::thread_local_inner!(@align $final_align, $($cfg_rhs)*); - } - - $($crate::thread::local_impl::thread_local_inner!(@align $final_align, $($attr_rest)+);)? - }, - - (@align $final_align:ident, cfg_attr(false, $($cfg_rhs:tt)*) $(, $($attr_rest:tt)+)?) => { - #[cfg(false)] - { - $crate::thread::local_impl::thread_local_inner!(@align $final_align, $($cfg_rhs)*); - } - - $($crate::thread::local_impl::thread_local_inner!(@align $final_align, $($attr_rest)+);)? - }, - - (@align $final_align:ident, cfg_attr($cfg_pred:meta, $($cfg_rhs:tt)*) $(, $($attr_rest:tt)+)?) => { + (@align $final_align:ident, cfg_attr($cfg_pred:expr, $($cfg_rhs:tt)*) $(, $($attr_rest:tt)+)?) => { #[cfg($cfg_pred)] { $crate::thread::local_impl::thread_local_inner!(@align $final_align, $($cfg_rhs)*); @@ -121,13 +103,14 @@ struct AlignedSystemBox { impl AlignedSystemBox { #[inline] fn new(v: Value) -> Self { - let layout = Layout::new::>().align_to(ALIGN).unwrap(); + let layout = rtunwrap!(Ok, Layout::new::>().align_to(ALIGN)); // We use the System allocator here to avoid interfering with a potential // Global allocator using thread-local storage. let ptr: *mut Value = (unsafe { System.alloc(layout) }).cast(); let Some(ptr) = NonNull::new(ptr) else { - alloc::handle_alloc_error(layout); + // Do not call the alloc error hook here. It may allocate! + rtabort!("Allocation failure"); }; unsafe { ptr.write(v) }; Self { ptr } @@ -157,7 +140,7 @@ impl Deref for AlignedSystemBox { impl Drop for AlignedSystemBox { #[inline] fn drop(&mut self) { - let layout = Layout::new::>().align_to(ALIGN).unwrap(); + let layout = rtunwrap!(Ok, Layout::new::>().align_to(ALIGN)); unsafe { let unwind_result = catch_unwind(AssertUnwindSafe(|| self.ptr.drop_in_place())); @@ -180,6 +163,7 @@ impl Storage { /// /// The resulting pointer may not be used after reentrant inialialization /// or thread destruction has occurred. + #[inline] pub fn get(&'static self, i: Option<&mut Option>, f: impl FnOnce() -> T) -> *const T { let key = self.key.force(); let ptr = unsafe { get(key) as *mut Value }; @@ -196,6 +180,7 @@ impl Storage { /// # Safety /// * `key` must be the result of calling `self.key.force()` /// * `ptr` must be the current value associated with `key`. + #[cold] unsafe fn try_initialize( key: Key, ptr: *mut Value, diff --git a/library/std/src/sys/time/hermit.rs b/library/std/src/sys/time/hermit.rs deleted file mode 100644 index 18ece2e3010d0..0000000000000 --- a/library/std/src/sys/time/hermit.rs +++ /dev/null @@ -1,63 +0,0 @@ -use hermit_abi::{self, CLOCK_MONOTONIC, CLOCK_REALTIME}; - -use crate::hash::Hash; -use crate::sys::pal::time::Timespec; -use crate::time::Duration; - -#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug, Hash)] -pub struct Instant(Timespec); - -impl Instant { - pub fn now() -> Instant { - let mut time: Timespec = Timespec::zero(); - let _ = unsafe { hermit_abi::clock_gettime(CLOCK_MONOTONIC, &raw mut time.t) }; - - Instant(time) - } - - pub fn checked_sub_instant(&self, other: &Instant) -> Option { - self.0.sub_timespec(&other.0).ok() - } - - pub fn checked_add_duration(&self, other: &Duration) -> Option { - Some(Instant(self.0.checked_add_duration(other)?)) - } - - pub fn checked_sub_duration(&self, other: &Duration) -> Option { - Some(Instant(self.0.checked_sub_duration(other)?)) - } -} - -#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug)] -pub struct SystemTime(Timespec); - -pub const UNIX_EPOCH: SystemTime = SystemTime(Timespec::zero()); - -impl SystemTime { - pub const MAX: SystemTime = SystemTime(Timespec::MAX); - - pub const MIN: SystemTime = SystemTime(Timespec::MIN); - - pub fn new(tv_sec: i64, tv_nsec: i32) -> SystemTime { - SystemTime(Timespec::new(tv_sec, tv_nsec)) - } - - pub fn now() -> SystemTime { - let mut time: Timespec = Timespec::zero(); - let _ = unsafe { hermit_abi::clock_gettime(CLOCK_REALTIME, &raw mut time.t) }; - - SystemTime(time) - } - - pub fn sub_time(&self, other: &SystemTime) -> Result { - self.0.sub_timespec(&other.0) - } - - pub fn checked_add_duration(&self, other: &Duration) -> Option { - Some(SystemTime(self.0.checked_add_duration(other)?)) - } - - pub fn checked_sub_duration(&self, other: &Duration) -> Option { - Some(SystemTime(self.0.checked_sub_duration(other)?)) - } -} diff --git a/library/std/src/sys/time/mod.rs b/library/std/src/sys/time/mod.rs index 6cd1850e7cca1..179c968ee2681 100644 --- a/library/std/src/sys/time/mod.rs +++ b/library/std/src/sys/time/mod.rs @@ -1,8 +1,4 @@ cfg_select! { - target_os = "hermit" => { - mod hermit; - use hermit as imp; - } target_os = "motor" => { use moto_rt::time as imp; } @@ -18,11 +14,7 @@ cfg_select! { mod uefi; use uefi as imp; } - any( - target_os = "teeos", - target_family = "unix", - target_os = "wasi", - ) => { + any(target_os = "hermit", target_os = "teeos", target_family = "unix", target_os = "wasi") => { mod unix; use unix as imp; } @@ -32,8 +24,8 @@ cfg_select! { mod unsupported; mod imp { - pub use super::vexos::Instant; pub use super::unsupported::{SystemTime, UNIX_EPOCH}; + pub use super::vexos::Instant; } } target_os = "windows" => { diff --git a/library/std/src/sys/time/windows.rs b/library/std/src/sys/time/windows.rs index 2e38dbf5cf288..b2abee4219fe3 100644 --- a/library/std/src/sys/time/windows.rs +++ b/library/std/src/sys/time/windows.rs @@ -35,7 +35,14 @@ impl Instant { let freq = perf_counter::frequency() as u64; let now = perf_counter::now(); + + // We convert now to `u64` to be able to use `Duration`. let instant_nsec = mul_div_u64(now as u64, NANOS_PER_SEC, freq); + // We can add an arbitrary offset to shift the epoch of this clock. We do that to avoid + // being too close to 0 which would lead to underflow when computing times in the past. Also + // see . + let instant_nsec = instant_nsec + (u64::MAX / 4); + Self { t: Duration::from_nanos(instant_nsec) } } diff --git a/library/std/src/thread/functions.rs b/library/std/src/thread/functions.rs index 95d7aaf518408..355a00c2a95ad 100644 --- a/library/std/src/thread/functions.rs +++ b/library/std/src/thread/functions.rs @@ -168,7 +168,11 @@ pub fn yield_now() { imp::yield_now() } -/// Determines whether the current thread is unwinding because of panic. +/// Determines whether the current thread is panicking. +/// +/// This returns `true` both when the thread is unwinding due to a panic, +/// or executing a panic hook. Note that the latter case will still happen +/// when `panic=abort` is set. /// /// A common use of this feature is to poison shared resources when writing /// unsafe code, by checking `panicking` when the `drop` is called. @@ -309,14 +313,14 @@ pub fn sleep(dur: Duration) { /// /// | Platform | System call | /// |-----------|----------------------------------------------------------------------| -/// | Linux | [clock_nanosleep] (Monotonic clock) | -/// | BSD except OpenBSD | [clock_nanosleep] (Monotonic Clock)] | -/// | Android | [clock_nanosleep] (Monotonic Clock)] | -/// | Solaris | [clock_nanosleep] (Monotonic Clock)] | -/// | Illumos | [clock_nanosleep] (Monotonic Clock)] | -/// | Dragonfly | [clock_nanosleep] (Monotonic Clock)] | -/// | Hurd | [clock_nanosleep] (Monotonic Clock)] | -/// | Vxworks | [clock_nanosleep] (Monotonic Clock)] | +/// | Linux | [clock_nanosleep] (Monotonic Clock) | +/// | BSD except OpenBSD | [clock_nanosleep] (Monotonic Clock) | +/// | Android | [clock_nanosleep] (Monotonic Clock) | +/// | Solaris | [clock_nanosleep] (Monotonic Clock) | +/// | Illumos | [clock_nanosleep] (Monotonic Clock) | +/// | Dragonfly | [clock_nanosleep] (Monotonic Clock) | +/// | Hurd | [clock_nanosleep] (Monotonic Clock) | +/// | Vxworks | [clock_nanosleep] (Monotonic Clock) | /// | Apple | `mach_wait_until` | /// | Other | `sleep_until` uses [`sleep`] and does not issue a syscall itself | /// @@ -636,10 +640,13 @@ pub fn park_timeout(dur: Duration) { /// /// On Windows: /// - It may undercount the amount of parallelism available on systems with more -/// than 64 logical CPUs. However, programs typically need specific support to -/// take advantage of more than 64 logical CPUs, and in the absence of such -/// support, the number returned by this function accurately reflects the -/// number of logical CPUs the program can use by default. +/// than 64 logical CPUs, because it reports only the logical CPUs in one +/// processor group. Before Windows 11 and Windows Server 2022, a process was by +/// default confined to a single processor group, so this count reflected the CPUs +/// it could use without explicitly opting into other groups. Starting with Windows +/// 11 and Windows Server 2022, a process and its threads have affinities that by +/// default span all processor groups, so on systems with more than 64 logical CPUs +/// this may report fewer CPUs than are available to the program. /// - It may overcount the amount of parallelism available on systems limited by /// process-wide affinity masks, or job object limitations. /// @@ -674,13 +681,10 @@ pub fn park_timeout(dur: Duration) { /// # Examples /// /// ``` -/// # #![allow(dead_code)] -/// use std::{io, thread}; +/// use std::thread; /// -/// fn main() -> io::Result<()> { -/// let count = thread::available_parallelism()?.get(); -/// assert!(count >= 1_usize); -/// Ok(()) +/// if let Ok(count) = thread::available_parallelism() { +/// assert!(count.get() >= 1_usize); /// } /// ``` #[doc(alias = "available_concurrency")] // Alias for a previous name we gave this API on unstable. diff --git a/library/std/src/thread/id.rs b/library/std/src/thread/id.rs index 3da0825db604d..33b1c453614ff 100644 --- a/library/std/src/thread/id.rs +++ b/library/std/src/thread/id.rs @@ -50,7 +50,12 @@ impl ThreadId { exhausted(); }; - match COUNTER.compare_exchange_weak(last, id, Ordering::Relaxed, Ordering::Relaxed) { + match COUNTER.compare_exchange_weak( + last, + id, + Ordering::Relaxed, + Ordering::Relaxed, + ) { Ok(_) => return ThreadId(NonZero::new(id).unwrap()), Err(id) => last = id, } diff --git a/library/std/src/thread/lifecycle.rs b/library/std/src/thread/lifecycle.rs index 0bb1f347ffaad..d3a97bbf08fa2 100644 --- a/library/std/src/thread/lifecycle.rs +++ b/library/std/src/thread/lifecycle.rs @@ -7,7 +7,7 @@ use super::thread::Thread; use super::{Result, spawnhook}; use crate::cell::UnsafeCell; use crate::marker::PhantomData; -use crate::mem::{ManuallyDrop, MaybeUninit}; +use crate::mem::MaybeDangling; use crate::sync::Arc; use crate::sync::atomic::{Atomic, AtomicUsize, Ordering}; use crate::sys::{AsInner, IntoInner, thread as imp}; @@ -57,29 +57,8 @@ where Arc::new(Packet { scope: scope_data, result: UnsafeCell::new(None), _marker: PhantomData }); let their_packet = my_packet.clone(); - // Pass `f` in `MaybeUninit` because actually that closure might *run longer than the lifetime of `F`*. + // Pass `f` in `MaybeDangling` because actually that closure might *run longer than the lifetime of `F`*. // See for more details. - // To prevent leaks we use a wrapper that drops its contents. - #[repr(transparent)] - struct MaybeDangling(MaybeUninit); - impl MaybeDangling { - fn new(x: T) -> Self { - MaybeDangling(MaybeUninit::new(x)) - } - fn into_inner(self) -> T { - // Make sure we don't drop. - let this = ManuallyDrop::new(self); - // SAFETY: we are always initialized. - unsafe { this.0.assume_init_read() } - } - } - impl Drop for MaybeDangling { - fn drop(&mut self) { - // SAFETY: we are always initialized. - unsafe { self.0.assume_init_drop() }; - } - } - let f = MaybeDangling::new(f); // The entrypoint of the Rust thread, after platform-specific thread @@ -87,7 +66,7 @@ where let rust_start = move || { let f = f.into_inner(); let try_result = panic::catch_unwind(panic::AssertUnwindSafe(|| { - crate::sys::backtrace::__rust_begin_short_backtrace(|| hooks.run()); + crate::sys::backtrace::__rust_begin_short_backtrace(|| hooks.inherit_and_run()); crate::sys::backtrace::__rust_begin_short_backtrace(f) })); // SAFETY: `their_packet` as been built just above and moved by the diff --git a/library/std/src/thread/local.rs b/library/std/src/thread/local.rs index 1318d8dc27809..7a05a962e2ac0 100644 --- a/library/std/src/thread/local.rs +++ b/library/std/src/thread/local.rs @@ -98,17 +98,18 @@ use crate::fmt; /// run on the thread that causes the process to exit. This is because the /// other threads may be forcibly terminated. /// -/// ## Synchronization in thread-local destructors +/// If a thread is [converted into a fiber], destructors will not be run unless +/// the fiber is [converted back into a thread] before the underlying thread exits. /// -/// On Windows, synchronization operations (such as [`JoinHandle::join`]) in -/// thread local destructors are prone to deadlocks and so should be avoided. -/// This is because the [loader lock] is held while a destructor is run. The -/// lock is acquired whenever a thread starts or exits or when a DLL is loaded -/// or unloaded. Therefore these events are blocked for as long as a thread -/// local destructor is running. +/// If a process loads a Rust `cdylib`, it must not cause the Rust TLS destructor support +// to be initialized for the first time during process shutdown. /// +/// When dynamically unloading a Rust `cdylib`, pending TLS destructors may run +// during the unload or may be leaked. +/// +/// [converted into a fiber]: https://learn.microsoft.com/en-us/windows/win32/api/winbase/nf-winbase-convertthreadtofiber +/// [converted back into a thread]: https://learn.microsoft.com/en-us/windows/win32/api/winbase/nf-winbase-convertfibertothread /// [loader lock]: https://docs.microsoft.com/en-us/windows/win32/dlls/dynamic-link-library-best-practices -/// [`JoinHandle::join`]: crate::thread::JoinHandle::join /// [`with`]: LocalKey::with #[cfg_attr(not(test), rustc_diagnostic_item = "LocalKey")] #[stable(feature = "rust1", since = "1.0.0")] @@ -198,41 +199,10 @@ pub macro thread_local_process_attrs { ); ), - // it's a nested `cfg_attr(true, ...)`; recurse into RHS - ( - [$($prev_align_attrs:tt)*] [$($prev_other_attrs:tt)*]; - @processing_cfg_attr { pred: ($($predicate:tt)*), rhs: [cfg_attr(true, $($cfg_rhs:tt)*) $(, $($attr_rhs:tt)*)?] }; - $($rest:tt)* - ) => ( - $crate::thread::local_impl::thread_local_process_attrs!( - [] []; - @processing_cfg_attr { pred: (true), rhs: [$($cfg_rhs)*] }; - [$($prev_align_attrs)*] [$($prev_other_attrs)*]; - @processing_cfg_attr { pred: ($($predicate)*), rhs: [$($($attr_rhs)*)?] }; - $($rest)* - ); - ), - - // it's a nested `cfg_attr(false, ...)`; recurse into RHS - ( - [$($prev_align_attrs:tt)*] [$($prev_other_attrs:tt)*]; - @processing_cfg_attr { pred: ($($predicate:tt)*), rhs: [cfg_attr(false, $($cfg_rhs:tt)*) $(, $($attr_rhs:tt)*)?] }; - $($rest:tt)* - ) => ( - $crate::thread::local_impl::thread_local_process_attrs!( - [] []; - @processing_cfg_attr { pred: (false), rhs: [$($cfg_rhs)*] }; - [$($prev_align_attrs)*] [$($prev_other_attrs)*]; - @processing_cfg_attr { pred: ($($predicate)*), rhs: [$($($attr_rhs)*)?] }; - $($rest)* - ); - ), - - // it's a nested `cfg_attr(..., ...)`; recurse into RHS ( [$($prev_align_attrs:tt)*] [$($prev_other_attrs:tt)*]; - @processing_cfg_attr { pred: ($($predicate:tt)*), rhs: [cfg_attr($cfg_lhs:meta, $($cfg_rhs:tt)*) $(, $($attr_rhs:tt)*)?] }; + @processing_cfg_attr { pred: ($($predicate:tt)*), rhs: [cfg_attr($cfg_lhs:expr, $($cfg_rhs:tt)*) $(, $($attr_rhs:tt)*)?] }; $($rest:tt)* ) => ( $crate::thread::local_impl::thread_local_process_attrs!( @@ -268,28 +238,8 @@ pub macro thread_local_process_attrs { ); ), - // `cfg_attr(true, ...)` attribute; parse it - ([$($prev_align_attrs:tt)*] [$($prev_other_attrs:tt)*]; #[cfg_attr(true, $($cfg_rhs:tt)*)] $($rest:tt)*) => ( - $crate::thread::local_impl::thread_local_process_attrs!( - [] []; - @processing_cfg_attr { pred: (true), rhs: [$($cfg_rhs)*] }; - [$($prev_align_attrs)*] [$($prev_other_attrs)*]; - $($rest)* - ); - ), - - // `cfg_attr(false, ...)` attribute; parse it - ([$($prev_align_attrs:tt)*] [$($prev_other_attrs:tt)*]; #[cfg_attr(false, $($cfg_rhs:tt)*)] $($rest:tt)*) => ( - $crate::thread::local_impl::thread_local_process_attrs!( - [] []; - @processing_cfg_attr { pred: (false), rhs: [$($cfg_rhs)*] }; - [$($prev_align_attrs)*] [$($prev_other_attrs)*]; - $($rest)* - ); - ), - // `cfg_attr(..., ...)` attribute; parse it - ([$($prev_align_attrs:tt)*] [$($prev_other_attrs:tt)*]; #[cfg_attr($cfg_pred:meta, $($cfg_rhs:tt)*)] $($rest:tt)*) => ( + ([$($prev_align_attrs:tt)*] [$($prev_other_attrs:tt)*]; #[cfg_attr($cfg_pred:expr, $($cfg_rhs:tt)*)] $($rest:tt)*) => ( $crate::thread::local_impl::thread_local_process_attrs!( [] []; @processing_cfg_attr { pred: ($cfg_pred), rhs: [$($cfg_rhs)*] }; @@ -396,6 +346,7 @@ pub macro thread_local_process_attrs { #[stable(feature = "rust1", since = "1.0.0")] #[cfg_attr(not(test), rustc_diagnostic_item = "thread_local_macro")] #[allow_internal_unstable(thread_local_internals)] +#[rustc_diagnostic_opaque] macro_rules! thread_local { () => {}; @@ -484,7 +435,7 @@ impl LocalKey { /// /// This will lazily initialize the value if this thread has not referenced /// this key yet. If the key has been destroyed (which may happen if this is called - /// in a destructor), this function will return an [`AccessError`]. + /// in a destructor), this function may return an [`AccessError`]. /// /// # Panics /// @@ -670,10 +621,17 @@ impl LocalKey> { /// Updates the contained value using a function. /// + /// This will lazily initialize the value if this thread has not referenced + /// this key yet. + /// + /// # Panics + /// + /// Panics if the key currently has its destructor running, + /// and it **may** panic if the destructor has previously been run for this thread. + /// /// # Examples /// /// ``` - /// #![feature(local_key_cell_update)] /// use std::cell::Cell; /// /// thread_local! { @@ -683,7 +641,7 @@ impl LocalKey> { /// X.update(|x| x + 1); /// assert_eq!(X.get(), 6); /// ``` - #[unstable(feature = "local_key_cell_update", issue = "143989")] + #[stable(feature = "local_key_cell_update", since = "1.99.0")] pub fn update(&'static self, f: impl FnOnce(T) -> T) where T: Copy, diff --git a/library/std/src/thread/main_thread.rs b/library/std/src/thread/main_thread.rs index 394074a593674..2e1d23ebdb369 100644 --- a/library/std/src/thread/main_thread.rs +++ b/library/std/src/thread/main_thread.rs @@ -14,8 +14,8 @@ cfg_select! { target_has_atomic = "64" => { use super::id::ThreadId; - use crate::sync::atomic::{Atomic, AtomicU64}; use crate::sync::atomic::Ordering::Relaxed; + use crate::sync::atomic::{Atomic, AtomicU64}; static MAIN: Atomic = AtomicU64::new(0); @@ -32,18 +32,14 @@ cfg_select! { _ => { use super::id::ThreadId; use crate::mem::MaybeUninit; - use crate::sync::atomic::{Atomic, AtomicBool}; use crate::sync::atomic::Ordering::{Acquire, Release}; + use crate::sync::atomic::{Atomic, AtomicBool}; static INIT: Atomic = AtomicBool::new(false); static mut MAIN: MaybeUninit = MaybeUninit::uninit(); pub(super) fn get() -> Option { - if INIT.load(Acquire) { - Some(unsafe { MAIN.assume_init() }) - } else { - None - } + if INIT.load(Acquire) { Some(unsafe { MAIN.assume_init() }) } else { None } } /// # Safety diff --git a/library/std/src/thread/mod.rs b/library/std/src/thread/mod.rs index 00aeb70e6e076..955d1f61e7535 100644 --- a/library/std/src/thread/mod.rs +++ b/library/std/src/thread/mod.rs @@ -26,9 +26,10 @@ //! non-zero exit code. //! //! When the main thread of a Rust program terminates, the entire program shuts -//! down, even if other threads are still running. However, this module provides -//! convenient facilities for automatically waiting for the termination of a -//! thread (i.e., join). +//! down, even if other threads are still running, and any destructors on the +//! remaining threads' stacks may not be executed. However, this module +//! provides convenient facilities for automatically waiting for the +//! termination of a thread (i.e., join). //! //! ## Spawning a thread //! diff --git a/library/std/src/thread/scoped.rs b/library/std/src/thread/scoped.rs index 929f7fdc6dcac..d8e018bde7471 100644 --- a/library/std/src/thread/scoped.rs +++ b/library/std/src/thread/scoped.rs @@ -177,7 +177,7 @@ impl<'scope, 'env> Scope<'scope, 'env> { /// Spawns a new thread within a scope, returning a [`ScopedJoinHandle`] for it. /// /// Unlike non-scoped threads, threads spawned with this function may - /// borrow non-`'static` data from the outside the scope. See [`scope`] for + /// borrow non-`'static` data from outside the scope. See [`scope`] for /// details. /// /// The join handle provides a [`join`] method that can be used to join the spawned diff --git a/library/std/src/thread/spawnhook.rs b/library/std/src/thread/spawnhook.rs index 254793ac33d08..92fb586d39dcf 100644 --- a/library/std/src/thread/spawnhook.rs +++ b/library/std/src/thread/spawnhook.rs @@ -1,7 +1,7 @@ use super::thread::Thread; use crate::cell::Cell; use crate::iter; -use crate::sync::Arc; +use crate::sync::{Arc, UniqueArc}; crate::thread_local! { /// A thread local linked list of spawn hooks. @@ -44,10 +44,12 @@ struct SpawnHook { /// In other words, adding a hook has no effect on already running threads (other than the current /// thread) and the threads they might spawn in the future. /// -/// Hooks can only be added, not removed. -/// /// The hooks will run in reverse order, starting with the most recently added. /// +/// Hooks can only be added, not removed. +/// Note that this does *not* mean that they are guaranteed to run. See [`Builder::no_hooks`]. +/// You cannot rely on a hook running for soundness. +/// /// # Usage /// /// ``` @@ -88,6 +90,8 @@ struct SpawnHook { /// assert_eq!(X.get(), 123); /// }).join().unwrap(); /// ``` +/// +/// [`Builder::no_hooks`]: crate::thread::Builder::no_hooks #[unstable(feature = "thread_spawn_hook", issue = "132951")] pub fn add_spawn_hook(hook: F) where @@ -95,12 +99,14 @@ where G: 'static + Send + FnOnce(), { SPAWN_HOOKS.with(|h| { - let mut hooks = h.take(); - let next = hooks.first.take(); - hooks.first = Some(Arc::new(SpawnHook { + // Perform all fallible operations before taking the current hooks (see #159923) + let mut new_first = UniqueArc::new(SpawnHook { hook: Box::new(move |thread| Box::new(hook(thread))), - next, - })); + next: None, + }); + let mut hooks = h.take(); + new_first.next = hooks.first.take(); + hooks.first = Some(UniqueArc::into_arc(new_first)); h.set(hooks); }); } @@ -144,7 +150,7 @@ pub(super) struct ChildSpawnHooks { impl ChildSpawnHooks { // This is run on the newly spawned thread, directly at the start. - pub(super) fn run(self) { + pub(super) fn inherit_and_run(self) { SPAWN_HOOKS.set(self.hooks); for run in self.to_run { run(); diff --git a/library/std/src/thread/tests.rs b/library/std/src/thread/tests.rs index 4b934c039a36f..78b6f7c35e8db 100644 --- a/library/std/src/thread/tests.rs +++ b/library/std/src/thread/tests.rs @@ -152,11 +152,11 @@ where { let (tx, rx) = channel(); - let x: Box<_> = Box::new(1); - let x_in_parent = (&*x) as *const i32 as usize; + let x: Box = Box::new(1); + let x_in_parent = (&raw const *x).addr(); spawnfn(Box::new(move || { - let x_in_child = (&*x) as *const i32 as usize; + let x_in_child = (&raw const *x).addr(); tx.send(x_in_child).unwrap(); })); diff --git a/library/std/src/time.rs b/library/std/src/time.rs index 1805d8926098d..5566c497e06cb 100644 --- a/library/std/src/time.rs +++ b/library/std/src/time.rs @@ -112,17 +112,16 @@ use crate::sys::{FromInner, IntoInner, time}; /// |-----------|----------------------------------------------------------------------| /// | SGX | [`insecure_time` usercall]. More information on [timekeeping in SGX] | /// | UNIX | [clock_gettime] with `CLOCK_MONOTONIC` | +/// | WASI | [clock_gettime] with `CLOCK_MONOTONIC` | /// | Darwin | [clock_gettime] with `CLOCK_UPTIME_RAW` | /// | VXWorks | [clock_gettime] with `CLOCK_MONOTONIC` | /// | SOLID | `get_tim` | -/// | WASI | [__wasi_clock_time_get] with `monotonic` | /// | Windows | [QueryPerformanceCounter] | /// /// [currently]: crate::io#platform-specific-behavior /// [QueryPerformanceCounter]: https://docs.microsoft.com/en-us/windows/win32/api/profileapi/nf-profileapi-queryperformancecounter /// [`insecure_time` usercall]: https://edp.fortanix.com/docs/api/fortanix_sgx_abi/struct.Usercalls.html#method.insecure_time /// [timekeeping in SGX]: https://edp.fortanix.com/docs/concepts/rust-std/#codestdtimecode -/// [__wasi_clock_time_get]: https://github.com/WebAssembly/WASI/blob/main/legacy/preview1/docs.md#clock_time_get /// [clock_gettime]: https://pubs.opengroup.org/onlinepubs/9799919799/functions/clock_getres.html /// /// **Disclaimer:** These system calls might change over time. @@ -138,9 +137,9 @@ use crate::sys::{FromInner, IntoInner, time}; /// if available, which is the case for all [tier 1] platforms. /// In practice such guarantees are – under rare circumstances – broken by hardware, virtualization /// or operating system bugs. To work around these bugs and platforms not offering monotonic clocks -/// [`duration_since`], [`elapsed`] and [`sub`] saturate to zero. In older Rust versions this -/// lead to a panic instead. [`checked_duration_since`] can be used to detect and handle situations -/// where monotonicity is violated, or `Instant`s are subtracted in the wrong order. +/// [`duration_since`], [`elapsed`] and [`sub`](#impl-Sub-for-Instant) saturate to zero. In older +/// Rust versions this lead to a panic instead. [`checked_duration_since`] can be used to detect and +/// handle situations where monotonicity is violated, or `Instant`s are subtracted in the wrong order. /// /// This workaround obscures programming errors where earlier and later instants are accidentally /// swapped. For this reason future Rust versions may reintroduce panics. @@ -224,17 +223,16 @@ pub struct Instant(time::Instant); /// |-----------|----------------------------------------------------------------------| /// | SGX | [`insecure_time` usercall]. More information on [timekeeping in SGX] | /// | UNIX | [clock_gettime (Realtime Clock)] | +/// | WASI | [clock_gettime (Realtime Clock)] | /// | Darwin | [clock_gettime (Realtime Clock)] | /// | VXWorks | [clock_gettime (Realtime Clock)] | /// | SOLID | `SOLID_RTC_ReadTime` | -/// | WASI | [__wasi_clock_time_get (Realtime Clock)] | /// | Windows | [GetSystemTimePreciseAsFileTime] / [GetSystemTimeAsFileTime] | /// /// [currently]: crate::io#platform-specific-behavior /// [`insecure_time` usercall]: https://edp.fortanix.com/docs/api/fortanix_sgx_abi/struct.Usercalls.html#method.insecure_time /// [timekeeping in SGX]: https://edp.fortanix.com/docs/concepts/rust-std/#codestdtimecode /// [clock_gettime (Realtime Clock)]: https://pubs.opengroup.org/onlinepubs/9799919799/functions/clock_getres.html -/// [__wasi_clock_time_get (Realtime Clock)]: https://github.com/WebAssembly/WASI/blob/main/legacy/preview1/docs.md#clock_time_get /// [GetSystemTimePreciseAsFileTime]: https://docs.microsoft.com/en-us/windows/win32/api/sysinfoapi/nf-sysinfoapi-getsystemtimepreciseasfiletime /// [GetSystemTimeAsFileTime]: https://docs.microsoft.com/en-us/windows/win32/api/sysinfoapi/nf-sysinfoapi-getsystemtimeasfiletime /// @@ -425,6 +423,7 @@ impl Add for Instant { /// /// This function may panic if the resulting point in time cannot be represented by the /// underlying data structure. See [`Instant::checked_add`] for a version without panic. + #[track_caller] fn add(self, other: Duration) -> Instant { self.checked_add(other).expect("overflow when adding duration to instant") } @@ -441,6 +440,7 @@ impl AddAssign for Instant { impl Sub for Instant { type Output = Instant; + #[track_caller] fn sub(self, other: Duration) -> Instant { self.checked_sub(other).expect("overflow when subtracting duration from instant") } @@ -742,8 +742,9 @@ impl Add for SystemTime { /// /// This function may panic if the resulting point in time cannot be represented by the /// underlying data structure. See [`SystemTime::checked_add`] for a version without panic. + #[track_caller] fn add(self, dur: Duration) -> SystemTime { - self.checked_add(dur).expect("overflow when adding duration to instant") + self.checked_add(dur).expect("overflow when adding duration to `SystemTime`") } } @@ -758,8 +759,9 @@ impl AddAssign for SystemTime { impl Sub for SystemTime { type Output = SystemTime; + #[track_caller] fn sub(self, dur: Duration) -> SystemTime { - self.checked_sub(dur).expect("overflow when subtracting duration from instant") + self.checked_sub(dur).expect("overflow when subtracting duration from `SystemTime`") } } diff --git a/library/std/src/view.rs b/library/std/src/view.rs new file mode 100644 index 0000000000000..5806cf27c2cc8 --- /dev/null +++ b/library/std/src/view.rs @@ -0,0 +1,3 @@ +//! Helper module for exporting the `view_types` macro. + +pub use core::view_type; diff --git a/library/std/tests/env.rs b/library/std/tests/env.rs index b53fd69b7070b..758d0a069a831 100644 --- a/library/std/tests/env.rs +++ b/library/std/tests/env.rs @@ -4,7 +4,10 @@ use std::path::Path; mod common; #[test] -#[cfg_attr(any(target_os = "emscripten", target_os = "wasi", target_env = "sgx"), ignore)] +#[cfg_attr( + any(target_os = "emscripten", target_os = "wasi", target_env = "sgx", target_os = "l4re"), + ignore +)] fn test_self_exe_path() { let path = current_exe(); assert!(path.is_ok()); @@ -59,6 +62,23 @@ fn split_paths_unix() { assert!(check_parse("/:/usr/local", &mut ["/", "/usr/local"])); } +#[test] +#[cfg(target_os = "uefi")] +fn split_paths_uefi() { + use std::path::PathBuf; + + fn check_parse(unparsed: &str, parsed: &[&str]) -> bool { + split_paths(unparsed).collect::>() + == parsed.iter().map(|s| PathBuf::from(*s)).collect::>() + } + + assert!(check_parse("", &mut [""])); + assert!(check_parse(";;", &mut ["", "", ""])); + assert!(check_parse(r"fs0:\", &mut [r"fs0:\"])); + assert!(check_parse(r"fs0:\;", &mut [r"fs0:\", ""])); + assert!(check_parse(r"fs0:\;fs0:\boot\", &mut [r"fs0:\", r"fs0:\boot\"])); +} + #[test] #[cfg(unix)] fn join_paths_unix() { diff --git a/library/std/tests/env_modify.rs b/library/std/tests/env_modify.rs index 4cd87bf7a0027..71d15bc1c47c0 100644 --- a/library/std/tests/env_modify.rs +++ b/library/std/tests/env_modify.rs @@ -1,6 +1,5 @@ // These tests are in a separate integration test as they modify the environment, // and would otherwise cause some other tests to fail. -#![feature(cfg_select)] use std::env::*; use std::ffi::{OsStr, OsString}; @@ -129,7 +128,11 @@ fn env_home_dir() { assert_ne!(home_dir(), Some(PathBuf::from("/home/MountainView"))); } - if let Some(oldhome) = oldhome { unsafe { set_var("HOME", oldhome); } } + if let Some(oldhome) = oldhome { + unsafe { + set_var("HOME", oldhome); + } + } } windows => { let oldhome = var_to_os_string(var("HOME")); @@ -142,7 +145,11 @@ fn env_home_dir() { assert!(home_dir().is_some()); set_var("HOME", "/home/PaloAlto"); - assert_ne!(home_dir(), Some(PathBuf::from("/home/PaloAlto")), "HOME must not be used"); + assert_ne!( + home_dir(), + Some(PathBuf::from("/home/PaloAlto")), + "HOME must not be used" + ); set_var("USERPROFILE", "/home/MountainView"); assert_eq!(home_dir(), Some(PathBuf::from("/home/MountainView"))); @@ -152,12 +159,20 @@ fn env_home_dir() { assert_eq!(home_dir(), Some(PathBuf::from("/home/MountainView"))); set_var("USERPROFILE", ""); - assert_ne!(home_dir(), Some(PathBuf::from("")), "Empty USERPROFILE must be ignored"); + assert_ne!( + home_dir(), + Some(PathBuf::from("")), + "Empty USERPROFILE must be ignored" + ); remove_var("USERPROFILE"); - if let Some(oldhome) = oldhome { set_var("HOME", oldhome); } - if let Some(olduserprofile) = olduserprofile { set_var("USERPROFILE", olduserprofile); } + if let Some(oldhome) = oldhome { + set_var("HOME", oldhome); + } + if let Some(olduserprofile) = olduserprofile { + set_var("USERPROFILE", olduserprofile); + } } } _ => {} diff --git a/library/std/tests/floats/f128.rs b/library/std/tests/floats/f128.rs deleted file mode 100644 index d20762023caf1..0000000000000 --- a/library/std/tests/floats/f128.rs +++ /dev/null @@ -1,320 +0,0 @@ -#![cfg(target_has_reliable_f128)] - -use std::f128::consts; -use std::ops::{Add, Div, Mul, Sub}; - -// Note these tolerances make sense around zero, but not for more extreme exponents. - -/// Default tolerances. Works for values that should be near precise but not exact. Roughly -/// the precision carried by `100 * 100`. -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -const TOL: f128 = 1e-12; - -/// For operations that are near exact, usually not involving math of different -/// signs. -const TOL_PRECISE: f128 = 1e-28; - -/// Tolerances for math that is allowed to be imprecise, usually due to multiple chained -/// operations. -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -const TOL_IMPR: f128 = 1e-10; - -/// Compare by representation -#[allow(unused_macros)] -macro_rules! assert_f128_biteq { - ($a:expr, $b:expr) => { - let (l, r): (&f128, &f128) = (&$a, &$b); - let lb = l.to_bits(); - let rb = r.to_bits(); - assert_eq!(lb, rb, "float {l:?} is not bitequal to {r:?}.\na: {lb:#034x}\nb: {rb:#034x}"); - }; -} - -#[test] -fn test_num_f128() { - // FIXME(f128): replace with a `test_num` call once the required `fmodl`/`fmodf128` - // function is available on all platforms. - let ten = 10f128; - let two = 2f128; - assert_eq!(ten.add(two), ten + two); - assert_eq!(ten.sub(two), ten - two); - assert_eq!(ten.mul(two), ten * two); - assert_eq!(ten.div(two), ten / two); -} - -// Many math functions allow for less accurate results, so the next tolerance up is used - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_powf() { - let nan: f128 = f128::NAN; - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - assert_eq!(1.0f128.powf(1.0), 1.0); - assert_approx_eq!(3.4f128.powf(4.5), 246.40818323761892815995637964326426756, TOL_IMPR); - assert_approx_eq!(2.7f128.powf(-3.2), 0.041652009108526178281070304373500889273, TOL_IMPR); - assert_approx_eq!((-3.1f128).powf(2.0), 9.6100000000000005506706202140776519387, TOL_IMPR); - assert_approx_eq!(5.9f128.powf(-2.0), 0.028727377190462507313100483690639638451, TOL_IMPR); - assert_eq!(8.3f128.powf(0.0), 1.0); - assert!(nan.powf(2.0).is_nan()); - assert_eq!(inf.powf(2.0), inf); - assert_eq!(neg_inf.powf(3.0), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_exp() { - assert_eq!(1.0, 0.0f128.exp()); - assert_approx_eq!(consts::E, 1.0f128.exp(), TOL); - assert_approx_eq!(148.41315910257660342111558004055227962348775, 5.0f128.exp(), TOL); - - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - let nan: f128 = f128::NAN; - assert_eq!(inf, inf.exp()); - assert_eq!(0.0, neg_inf.exp()); - assert!(nan.exp().is_nan()); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_exp2() { - assert_eq!(32.0, 5.0f128.exp2()); - assert_eq!(1.0, 0.0f128.exp2()); - - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - let nan: f128 = f128::NAN; - assert_eq!(inf, inf.exp2()); - assert_eq!(0.0, neg_inf.exp2()); - assert!(nan.exp2().is_nan()); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_ln() { - let nan: f128 = f128::NAN; - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - assert_approx_eq!(1.0f128.exp().ln(), 1.0, TOL); - assert!(nan.ln().is_nan()); - assert_eq!(inf.ln(), inf); - assert!(neg_inf.ln().is_nan()); - assert!((-2.3f128).ln().is_nan()); - assert_eq!((-0.0f128).ln(), neg_inf); - assert_eq!(0.0f128.ln(), neg_inf); - assert_approx_eq!(4.0f128.ln(), 1.3862943611198906188344642429163531366, TOL); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_log() { - let nan: f128 = f128::NAN; - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - assert_eq!(10.0f128.log(10.0), 1.0); - assert_approx_eq!(2.3f128.log(3.5), 0.66485771361478710036766645911922010272, TOL); - assert_eq!(1.0f128.exp().log(1.0f128.exp()), 1.0); - assert!(1.0f128.log(1.0).is_nan()); - assert!(1.0f128.log(-13.9).is_nan()); - assert!(nan.log(2.3).is_nan()); - assert_eq!(inf.log(10.0), inf); - assert!(neg_inf.log(8.8).is_nan()); - assert!((-2.3f128).log(0.1).is_nan()); - assert_eq!((-0.0f128).log(2.0), neg_inf); - assert_eq!(0.0f128.log(7.0), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_log2() { - let nan: f128 = f128::NAN; - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - assert_approx_eq!(10.0f128.log2(), 3.32192809488736234787031942948939017, TOL); - assert_approx_eq!(2.3f128.log2(), 1.2016338611696504130002982471978765921, TOL); - assert_approx_eq!(1.0f128.exp().log2(), 1.4426950408889634073599246810018921381, TOL); - assert!(nan.log2().is_nan()); - assert_eq!(inf.log2(), inf); - assert!(neg_inf.log2().is_nan()); - assert!((-2.3f128).log2().is_nan()); - assert_eq!((-0.0f128).log2(), neg_inf); - assert_eq!(0.0f128.log2(), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_log10() { - let nan: f128 = f128::NAN; - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - assert_eq!(10.0f128.log10(), 1.0); - assert_approx_eq!(2.3f128.log10(), 0.36172783601759284532595218865859309898, TOL); - assert_approx_eq!(1.0f128.exp().log10(), 0.43429448190325182765112891891660508222, TOL); - assert_eq!(1.0f128.log10(), 0.0); - assert!(nan.log10().is_nan()); - assert_eq!(inf.log10(), inf); - assert!(neg_inf.log10().is_nan()); - assert!((-2.3f128).log10().is_nan()); - assert_eq!((-0.0f128).log10(), neg_inf); - assert_eq!(0.0f128.log10(), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_asinh() { - // Lower accuracy results are allowed, use increased tolerances - assert_eq!(0.0f128.asinh(), 0.0f128); - assert_eq!((-0.0f128).asinh(), -0.0f128); - - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - let nan: f128 = f128::NAN; - assert_eq!(inf.asinh(), inf); - assert_eq!(neg_inf.asinh(), neg_inf); - assert!(nan.asinh().is_nan()); - assert!((-0.0f128).asinh().is_sign_negative()); - - // issue 63271 - assert_approx_eq!(2.0f128.asinh(), 1.443635475178810342493276740273105f128, TOL_IMPR); - assert_approx_eq!((-2.0f128).asinh(), -1.443635475178810342493276740273105f128, TOL_IMPR); - // regression test for the catastrophic cancellation fixed in 72486 - assert_approx_eq!( - (-67452098.07139316f128).asinh(), - -18.720075426274544393985484294000831757220, - TOL_IMPR - ); - - // test for low accuracy from issue 104548 - assert_approx_eq!(60.0f128, 60.0f128.sinh().asinh(), TOL_IMPR); - // mul needed for approximate comparison to be meaningful - assert_approx_eq!(1.0f128, 1e-15f128.sinh().asinh() * 1e15f128, TOL_IMPR); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_acosh() { - assert_eq!(1.0f128.acosh(), 0.0f128); - assert!(0.999f128.acosh().is_nan()); - - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - let nan: f128 = f128::NAN; - assert_eq!(inf.acosh(), inf); - assert!(neg_inf.acosh().is_nan()); - assert!(nan.acosh().is_nan()); - assert_approx_eq!(2.0f128.acosh(), 1.31695789692481670862504634730796844f128, TOL_IMPR); - assert_approx_eq!(3.0f128.acosh(), 1.76274717403908605046521864995958461f128, TOL_IMPR); - - // test for low accuracy from issue 104548 - assert_approx_eq!(60.0f128, 60.0f128.cosh().acosh(), TOL_IMPR); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_atanh() { - assert_eq!(0.0f128.atanh(), 0.0f128); - assert_eq!((-0.0f128).atanh(), -0.0f128); - - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - let nan: f128 = f128::NAN; - assert_eq!(1.0f128.atanh(), inf); - assert_eq!((-1.0f128).atanh(), neg_inf); - assert!(2f128.atanh().atanh().is_nan()); - assert!((-2f128).atanh().atanh().is_nan()); - assert!(inf.atanh().is_nan()); - assert!(neg_inf.atanh().is_nan()); - assert!(nan.atanh().is_nan()); - assert_approx_eq!(0.5f128.atanh(), 0.54930614433405484569762261846126285f128, TOL_IMPR); - assert_approx_eq!((-0.5f128).atanh(), -0.54930614433405484569762261846126285f128, TOL_IMPR); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_gamma() { - // precision can differ among platforms - assert_approx_eq!(1.0f128.gamma(), 1.0f128, TOL_IMPR); - assert_approx_eq!(2.0f128.gamma(), 1.0f128, TOL_IMPR); - assert_approx_eq!(3.0f128.gamma(), 2.0f128, TOL_IMPR); - assert_approx_eq!(4.0f128.gamma(), 6.0f128, TOL_IMPR); - assert_approx_eq!(5.0f128.gamma(), 24.0f128, TOL_IMPR); - assert_approx_eq!(0.5f128.gamma(), consts::PI.sqrt(), TOL_IMPR); - assert_approx_eq!((-0.5f128).gamma(), -2.0 * consts::PI.sqrt(), TOL_IMPR); - assert_eq!(0.0f128.gamma(), f128::INFINITY); - assert_eq!((-0.0f128).gamma(), f128::NEG_INFINITY); - assert!((-1.0f128).gamma().is_nan()); - assert!((-2.0f128).gamma().is_nan()); - assert!(f128::NAN.gamma().is_nan()); - assert!(f128::NEG_INFINITY.gamma().is_nan()); - assert_eq!(f128::INFINITY.gamma(), f128::INFINITY); - assert_eq!(1760.9f128.gamma(), f128::INFINITY); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_ln_gamma() { - assert_approx_eq!(1.0f128.ln_gamma().0, 0.0f128, TOL_IMPR); - assert_eq!(1.0f128.ln_gamma().1, 1); - assert_approx_eq!(2.0f128.ln_gamma().0, 0.0f128, TOL_IMPR); - assert_eq!(2.0f128.ln_gamma().1, 1); - assert_approx_eq!(3.0f128.ln_gamma().0, 2.0f128.ln(), TOL_IMPR); - assert_eq!(3.0f128.ln_gamma().1, 1); - assert_approx_eq!((-0.5f128).ln_gamma().0, (2.0 * consts::PI.sqrt()).ln(), TOL_IMPR); - assert_eq!((-0.5f128).ln_gamma().1, -1); -} - -#[test] -fn test_real_consts() { - let pi: f128 = consts::PI; - let frac_pi_2: f128 = consts::FRAC_PI_2; - let frac_pi_3: f128 = consts::FRAC_PI_3; - let frac_pi_4: f128 = consts::FRAC_PI_4; - let frac_pi_6: f128 = consts::FRAC_PI_6; - let frac_pi_8: f128 = consts::FRAC_PI_8; - let frac_1_pi: f128 = consts::FRAC_1_PI; - let frac_2_pi: f128 = consts::FRAC_2_PI; - - assert_approx_eq!(frac_pi_2, pi / 2f128, TOL_PRECISE); - assert_approx_eq!(frac_pi_3, pi / 3f128, TOL_PRECISE); - assert_approx_eq!(frac_pi_4, pi / 4f128, TOL_PRECISE); - assert_approx_eq!(frac_pi_6, pi / 6f128, TOL_PRECISE); - assert_approx_eq!(frac_pi_8, pi / 8f128, TOL_PRECISE); - assert_approx_eq!(frac_1_pi, 1f128 / pi, TOL_PRECISE); - assert_approx_eq!(frac_2_pi, 2f128 / pi, TOL_PRECISE); - - #[cfg(not(miri))] - #[cfg(target_has_reliable_f128_math)] - { - let frac_2_sqrtpi: f128 = consts::FRAC_2_SQRT_PI; - let sqrt2: f128 = consts::SQRT_2; - let frac_1_sqrt2: f128 = consts::FRAC_1_SQRT_2; - let e: f128 = consts::E; - let log2_e: f128 = consts::LOG2_E; - let log10_e: f128 = consts::LOG10_E; - let ln_2: f128 = consts::LN_2; - let ln_10: f128 = consts::LN_10; - - assert_approx_eq!(frac_2_sqrtpi, 2f128 / pi.sqrt(), TOL_PRECISE); - assert_approx_eq!(sqrt2, 2f128.sqrt(), TOL_PRECISE); - assert_approx_eq!(frac_1_sqrt2, 1f128 / 2f128.sqrt(), TOL_PRECISE); - assert_approx_eq!(log2_e, e.log2(), TOL_PRECISE); - assert_approx_eq!(log10_e, e.log10(), TOL_PRECISE); - assert_approx_eq!(ln_2, 2f128.ln(), TOL_PRECISE); - assert_approx_eq!(ln_10, 10f128.ln(), TOL_PRECISE); - } -} diff --git a/library/std/tests/floats/f16.rs b/library/std/tests/floats/f16.rs deleted file mode 100644 index cc0960765f411..0000000000000 --- a/library/std/tests/floats/f16.rs +++ /dev/null @@ -1,297 +0,0 @@ -#![cfg(target_has_reliable_f16)] - -use std::f16::consts; - -/// Tolerance for results on the order of 10.0e-2 -#[allow(unused)] -const TOL_N2: f16 = 0.0001; - -/// Tolerance for results on the order of 10.0e+0 -#[allow(unused)] -const TOL_0: f16 = 0.01; - -/// Tolerance for results on the order of 10.0e+2 -#[allow(unused)] -const TOL_P2: f16 = 0.5; - -/// Tolerance for results on the order of 10.0e+4 -#[allow(unused)] -const TOL_P4: f16 = 10.0; - -/// Compare by representation -#[allow(unused_macros)] -macro_rules! assert_f16_biteq { - ($a:expr, $b:expr) => { - let (l, r): (&f16, &f16) = (&$a, &$b); - let lb = l.to_bits(); - let rb = r.to_bits(); - assert_eq!(lb, rb, "float {l:?} ({lb:#04x}) is not bitequal to {r:?} ({rb:#04x})"); - }; -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_powf() { - let nan: f16 = f16::NAN; - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - assert_eq!(1.0f16.powf(1.0), 1.0); - assert_approx_eq!(3.4f16.powf(4.5), 246.408183, TOL_P2); - assert_approx_eq!(2.7f16.powf(-3.2), 0.041652, TOL_N2); - assert_approx_eq!((-3.1f16).powf(2.0), 9.61, TOL_P2); - assert_approx_eq!(5.9f16.powf(-2.0), 0.028727, TOL_N2); - assert_eq!(8.3f16.powf(0.0), 1.0); - assert!(nan.powf(2.0).is_nan()); - assert_eq!(inf.powf(2.0), inf); - assert_eq!(neg_inf.powf(3.0), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_exp() { - assert_eq!(1.0, 0.0f16.exp()); - assert_approx_eq!(2.718282, 1.0f16.exp(), TOL_0); - assert_approx_eq!(148.413159, 5.0f16.exp(), TOL_0); - - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - let nan: f16 = f16::NAN; - assert_eq!(inf, inf.exp()); - assert_eq!(0.0, neg_inf.exp()); - assert!(nan.exp().is_nan()); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_exp2() { - assert_eq!(32.0, 5.0f16.exp2()); - assert_eq!(1.0, 0.0f16.exp2()); - - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - let nan: f16 = f16::NAN; - assert_eq!(inf, inf.exp2()); - assert_eq!(0.0, neg_inf.exp2()); - assert!(nan.exp2().is_nan()); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_ln() { - let nan: f16 = f16::NAN; - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - assert_approx_eq!(1.0f16.exp().ln(), 1.0, TOL_0); - assert!(nan.ln().is_nan()); - assert_eq!(inf.ln(), inf); - assert!(neg_inf.ln().is_nan()); - assert!((-2.3f16).ln().is_nan()); - assert_eq!((-0.0f16).ln(), neg_inf); - assert_eq!(0.0f16.ln(), neg_inf); - assert_approx_eq!(4.0f16.ln(), 1.386294, TOL_0); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_log() { - let nan: f16 = f16::NAN; - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - assert_eq!(10.0f16.log(10.0), 1.0); - assert_approx_eq!(2.3f16.log(3.5), 0.664858, TOL_0); - assert_eq!(1.0f16.exp().log(1.0f16.exp()), 1.0); - assert!(1.0f16.log(1.0).is_nan()); - assert!(1.0f16.log(-13.9).is_nan()); - assert!(nan.log(2.3).is_nan()); - assert_eq!(inf.log(10.0), inf); - assert!(neg_inf.log(8.8).is_nan()); - assert!((-2.3f16).log(0.1).is_nan()); - assert_eq!((-0.0f16).log(2.0), neg_inf); - assert_eq!(0.0f16.log(7.0), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_log2() { - let nan: f16 = f16::NAN; - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - assert_approx_eq!(10.0f16.log2(), 3.321928, TOL_0); - assert_approx_eq!(2.3f16.log2(), 1.201634, TOL_0); - assert_approx_eq!(1.0f16.exp().log2(), 1.442695, TOL_0); - assert!(nan.log2().is_nan()); - assert_eq!(inf.log2(), inf); - assert!(neg_inf.log2().is_nan()); - assert!((-2.3f16).log2().is_nan()); - assert_eq!((-0.0f16).log2(), neg_inf); - assert_eq!(0.0f16.log2(), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_log10() { - let nan: f16 = f16::NAN; - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - assert_eq!(10.0f16.log10(), 1.0); - assert_approx_eq!(2.3f16.log10(), 0.361728, TOL_0); - assert_approx_eq!(1.0f16.exp().log10(), 0.434294, TOL_0); - assert_eq!(1.0f16.log10(), 0.0); - assert!(nan.log10().is_nan()); - assert_eq!(inf.log10(), inf); - assert!(neg_inf.log10().is_nan()); - assert!((-2.3f16).log10().is_nan()); - assert_eq!((-0.0f16).log10(), neg_inf); - assert_eq!(0.0f16.log10(), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_asinh() { - assert_eq!(0.0f16.asinh(), 0.0f16); - assert_eq!((-0.0f16).asinh(), -0.0f16); - - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - let nan: f16 = f16::NAN; - assert_eq!(inf.asinh(), inf); - assert_eq!(neg_inf.asinh(), neg_inf); - assert!(nan.asinh().is_nan()); - assert!((-0.0f16).asinh().is_sign_negative()); - // issue 63271 - assert_approx_eq!(2.0f16.asinh(), 1.443635475178810342493276740273105f16, TOL_0); - assert_approx_eq!((-2.0f16).asinh(), -1.443635475178810342493276740273105f16, TOL_0); - // regression test for the catastrophic cancellation fixed in 72486 - assert_approx_eq!((-200.0f16).asinh(), -5.991470797049389, TOL_0); - - // test for low accuracy from issue 104548 - assert_approx_eq!(10.0f16, 10.0f16.sinh().asinh(), TOL_0); - // mul needed for approximate comparison to be meaningful - assert_approx_eq!(1.0f16, 1e-3f16.sinh().asinh() * 1e3f16, TOL_0); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_acosh() { - assert_eq!(1.0f16.acosh(), 0.0f16); - assert!(0.999f16.acosh().is_nan()); - - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - let nan: f16 = f16::NAN; - assert_eq!(inf.acosh(), inf); - assert!(neg_inf.acosh().is_nan()); - assert!(nan.acosh().is_nan()); - assert_approx_eq!(2.0f16.acosh(), 1.31695789692481670862504634730796844f16, TOL_0); - assert_approx_eq!(3.0f16.acosh(), 1.76274717403908605046521864995958461f16, TOL_0); - - // test for low accuracy from issue 104548 - assert_approx_eq!(10.0f16, 10.0f16.cosh().acosh(), TOL_P2); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_atanh() { - assert_eq!(0.0f16.atanh(), 0.0f16); - assert_eq!((-0.0f16).atanh(), -0.0f16); - - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - let nan: f16 = f16::NAN; - assert_eq!(1.0f16.atanh(), inf); - assert_eq!((-1.0f16).atanh(), neg_inf); - assert!(2f16.atanh().atanh().is_nan()); - assert!((-2f16).atanh().atanh().is_nan()); - assert!(inf.atanh().is_nan()); - assert!(neg_inf.atanh().is_nan()); - assert!(nan.atanh().is_nan()); - assert_approx_eq!(0.5f16.atanh(), 0.54930614433405484569762261846126285f16, TOL_0); - assert_approx_eq!((-0.5f16).atanh(), -0.54930614433405484569762261846126285f16, TOL_0); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_gamma() { - // precision can differ among platforms - assert_approx_eq!(1.0f16.gamma(), 1.0f16, TOL_0); - assert_approx_eq!(2.0f16.gamma(), 1.0f16, TOL_0); - assert_approx_eq!(3.0f16.gamma(), 2.0f16, TOL_0); - assert_approx_eq!(4.0f16.gamma(), 6.0f16, TOL_0); - assert_approx_eq!(5.0f16.gamma(), 24.0f16, TOL_0); - assert_approx_eq!(0.5f16.gamma(), consts::PI.sqrt(), TOL_0); - assert_approx_eq!((-0.5f16).gamma(), -2.0 * consts::PI.sqrt(), TOL_0); - assert_eq!(0.0f16.gamma(), f16::INFINITY); - assert_eq!((-0.0f16).gamma(), f16::NEG_INFINITY); - assert!((-1.0f16).gamma().is_nan()); - assert!((-2.0f16).gamma().is_nan()); - assert!(f16::NAN.gamma().is_nan()); - assert!(f16::NEG_INFINITY.gamma().is_nan()); - assert_eq!(f16::INFINITY.gamma(), f16::INFINITY); - assert_eq!(171.71f16.gamma(), f16::INFINITY); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_ln_gamma() { - assert_approx_eq!(1.0f16.ln_gamma().0, 0.0f16, TOL_0); - assert_eq!(1.0f16.ln_gamma().1, 1); - assert_approx_eq!(2.0f16.ln_gamma().0, 0.0f16, TOL_0); - assert_eq!(2.0f16.ln_gamma().1, 1); - assert_approx_eq!(3.0f16.ln_gamma().0, 2.0f16.ln(), TOL_0); - assert_eq!(3.0f16.ln_gamma().1, 1); - assert_approx_eq!((-0.5f16).ln_gamma().0, (2.0 * consts::PI.sqrt()).ln(), TOL_0); - assert_eq!((-0.5f16).ln_gamma().1, -1); -} - -#[test] -fn test_real_consts() { - let pi: f16 = consts::PI; - let frac_pi_2: f16 = consts::FRAC_PI_2; - let frac_pi_3: f16 = consts::FRAC_PI_3; - let frac_pi_4: f16 = consts::FRAC_PI_4; - let frac_pi_6: f16 = consts::FRAC_PI_6; - let frac_pi_8: f16 = consts::FRAC_PI_8; - let frac_1_pi: f16 = consts::FRAC_1_PI; - let frac_2_pi: f16 = consts::FRAC_2_PI; - - assert_approx_eq!(frac_pi_2, pi / 2f16, TOL_0); - assert_approx_eq!(frac_pi_3, pi / 3f16, TOL_0); - assert_approx_eq!(frac_pi_4, pi / 4f16, TOL_0); - assert_approx_eq!(frac_pi_6, pi / 6f16, TOL_0); - assert_approx_eq!(frac_pi_8, pi / 8f16, TOL_0); - assert_approx_eq!(frac_1_pi, 1f16 / pi, TOL_0); - assert_approx_eq!(frac_2_pi, 2f16 / pi, TOL_0); - - #[cfg(not(miri))] - #[cfg(target_has_reliable_f16_math)] - { - let frac_2_sqrtpi: f16 = consts::FRAC_2_SQRT_PI; - let sqrt2: f16 = consts::SQRT_2; - let frac_1_sqrt2: f16 = consts::FRAC_1_SQRT_2; - let e: f16 = consts::E; - let log2_e: f16 = consts::LOG2_E; - let log10_e: f16 = consts::LOG10_E; - let ln_2: f16 = consts::LN_2; - let ln_10: f16 = consts::LN_10; - - assert_approx_eq!(frac_2_sqrtpi, 2f16 / pi.sqrt(), TOL_0); - assert_approx_eq!(sqrt2, 2f16.sqrt(), TOL_0); - assert_approx_eq!(frac_1_sqrt2, 1f16 / 2f16.sqrt(), TOL_0); - assert_approx_eq!(log2_e, e.log2(), TOL_0); - assert_approx_eq!(log10_e, e.log10(), TOL_0); - assert_approx_eq!(ln_2, 2f16.ln(), TOL_0); - assert_approx_eq!(ln_10, 10f16.ln(), TOL_0); - } -} diff --git a/library/std/tests/floats/f32.rs b/library/std/tests/floats/f32.rs deleted file mode 100644 index 3acd067091415..0000000000000 --- a/library/std/tests/floats/f32.rs +++ /dev/null @@ -1,258 +0,0 @@ -use std::f32::consts; - -/// Miri adds some extra errors to float functions; make sure the tests still pass. -/// These values are purely used as a canary to test against and are thus not a stable guarantee Rust provides. -/// They serve as a way to get an idea of the real precision of floating point operations on different platforms. -const APPROX_DELTA: f32 = if cfg!(miri) { 1e-3 } else { 1e-6 }; - -#[allow(unused_macros)] -macro_rules! assert_f32_biteq { - ($left : expr, $right : expr) => { - let l: &f32 = &$left; - let r: &f32 = &$right; - let lb = l.to_bits(); - let rb = r.to_bits(); - assert_eq!(lb, rb, "float {l} ({lb:#010x}) is not bitequal to {r} ({rb:#010x})"); - }; -} - -#[test] -fn test_powf() { - let nan: f32 = f32::NAN; - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - assert_eq!(1.0f32.powf(1.0), 1.0); - assert_approx_eq!(3.4f32.powf(4.5), 246.408218, APPROX_DELTA); - assert_approx_eq!(2.7f32.powf(-3.2), 0.041652); - assert_approx_eq!((-3.1f32).powf(2.0), 9.61, APPROX_DELTA); - assert_approx_eq!(5.9f32.powf(-2.0), 0.028727); - assert_eq!(8.3f32.powf(0.0), 1.0); - assert!(nan.powf(2.0).is_nan()); - assert_eq!(inf.powf(2.0), inf); - assert_eq!(neg_inf.powf(3.0), neg_inf); -} - -#[test] -fn test_exp() { - assert_eq!(1.0, 0.0f32.exp()); - assert_approx_eq!(2.718282, 1.0f32.exp(), APPROX_DELTA); - assert_approx_eq!(148.413162, 5.0f32.exp(), APPROX_DELTA); - - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - let nan: f32 = f32::NAN; - assert_eq!(inf, inf.exp()); - assert_eq!(0.0, neg_inf.exp()); - assert!(nan.exp().is_nan()); -} - -#[test] -fn test_exp2() { - assert_approx_eq!(32.0, 5.0f32.exp2(), APPROX_DELTA); - assert_eq!(1.0, 0.0f32.exp2()); - - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - let nan: f32 = f32::NAN; - assert_eq!(inf, inf.exp2()); - assert_eq!(0.0, neg_inf.exp2()); - assert!(nan.exp2().is_nan()); -} - -#[test] -fn test_ln() { - let nan: f32 = f32::NAN; - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - assert_approx_eq!(1.0f32.exp().ln(), 1.0); - assert!(nan.ln().is_nan()); - assert_eq!(inf.ln(), inf); - assert!(neg_inf.ln().is_nan()); - assert!((-2.3f32).ln().is_nan()); - assert_eq!((-0.0f32).ln(), neg_inf); - assert_eq!(0.0f32.ln(), neg_inf); - assert_approx_eq!(4.0f32.ln(), 1.386294, APPROX_DELTA); -} - -#[test] -fn test_log() { - let nan: f32 = f32::NAN; - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - assert_approx_eq!(10.0f32.log(10.0), 1.0); - assert_approx_eq!(2.3f32.log(3.5), 0.664858); - assert_approx_eq!(1.0f32.exp().log(1.0f32.exp()), 1.0, APPROX_DELTA); - assert!(1.0f32.log(1.0).is_nan()); - assert!(1.0f32.log(-13.9).is_nan()); - assert!(nan.log(2.3).is_nan()); - assert_eq!(inf.log(10.0), inf); - assert!(neg_inf.log(8.8).is_nan()); - assert!((-2.3f32).log(0.1).is_nan()); - assert_eq!((-0.0f32).log(2.0), neg_inf); - assert_eq!(0.0f32.log(7.0), neg_inf); -} - -#[test] -fn test_log2() { - let nan: f32 = f32::NAN; - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - assert_approx_eq!(10.0f32.log2(), 3.321928, APPROX_DELTA); - assert_approx_eq!(2.3f32.log2(), 1.201634); - assert_approx_eq!(1.0f32.exp().log2(), 1.442695, APPROX_DELTA); - assert!(nan.log2().is_nan()); - assert_eq!(inf.log2(), inf); - assert!(neg_inf.log2().is_nan()); - assert!((-2.3f32).log2().is_nan()); - assert_eq!((-0.0f32).log2(), neg_inf); - assert_eq!(0.0f32.log2(), neg_inf); -} - -#[test] -fn test_log10() { - let nan: f32 = f32::NAN; - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - assert_approx_eq!(10.0f32.log10(), 1.0); - assert_approx_eq!(2.3f32.log10(), 0.361728); - assert_approx_eq!(1.0f32.exp().log10(), 0.434294); - assert_eq!(1.0f32.log10(), 0.0); - assert!(nan.log10().is_nan()); - assert_eq!(inf.log10(), inf); - assert!(neg_inf.log10().is_nan()); - assert!((-2.3f32).log10().is_nan()); - assert_eq!((-0.0f32).log10(), neg_inf); - assert_eq!(0.0f32.log10(), neg_inf); -} - -#[test] -fn test_asinh() { - assert_eq!(0.0f32.asinh(), 0.0f32); - assert_eq!((-0.0f32).asinh(), -0.0f32); - - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - let nan: f32 = f32::NAN; - assert_eq!(inf.asinh(), inf); - assert_eq!(neg_inf.asinh(), neg_inf); - assert!(nan.asinh().is_nan()); - assert!((-0.0f32).asinh().is_sign_negative()); // issue 63271 - assert_approx_eq!(2.0f32.asinh(), 1.443635475178810342493276740273105f32); - assert_approx_eq!((-2.0f32).asinh(), -1.443635475178810342493276740273105f32); - // regression test for the catastrophic cancellation fixed in 72486 - assert_approx_eq!((-3000.0f32).asinh(), -8.699514775987968673236893537700647f32, APPROX_DELTA); - - // test for low accuracy from issue 104548 - assert_approx_eq!(60.0f32, 60.0f32.sinh().asinh(), APPROX_DELTA); - // mul needed for approximate comparison to be meaningful - assert_approx_eq!(1.0f32, 1e-15f32.sinh().asinh() * 1e15f32); -} - -#[test] -fn test_acosh() { - assert_eq!(1.0f32.acosh(), 0.0f32); - assert!(0.999f32.acosh().is_nan()); - - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - let nan: f32 = f32::NAN; - assert_eq!(inf.acosh(), inf); - assert!(neg_inf.acosh().is_nan()); - assert!(nan.acosh().is_nan()); - assert_approx_eq!(2.0f32.acosh(), 1.31695789692481670862504634730796844f32); - assert_approx_eq!(3.0f32.acosh(), 1.76274717403908605046521864995958461f32); - - // test for low accuracy from issue 104548 - assert_approx_eq!(60.0f32, 60.0f32.cosh().acosh(), APPROX_DELTA); -} - -#[test] -fn test_atanh() { - assert_eq!(0.0f32.atanh(), 0.0f32); - assert_eq!((-0.0f32).atanh(), -0.0f32); - - let inf32: f32 = f32::INFINITY; - let neg_inf32: f32 = f32::NEG_INFINITY; - assert_eq!(1.0f32.atanh(), inf32); - assert_eq!((-1.0f32).atanh(), neg_inf32); - - assert!(2f64.atanh().atanh().is_nan()); - assert!((-2f64).atanh().atanh().is_nan()); - - let inf64: f32 = f32::INFINITY; - let neg_inf64: f32 = f32::NEG_INFINITY; - let nan32: f32 = f32::NAN; - assert!(inf64.atanh().is_nan()); - assert!(neg_inf64.atanh().is_nan()); - assert!(nan32.atanh().is_nan()); - - assert_approx_eq!(0.5f32.atanh(), 0.54930614433405484569762261846126285f32); - assert_approx_eq!((-0.5f32).atanh(), -0.54930614433405484569762261846126285f32); -} - -#[test] -fn test_gamma() { - // precision can differ between platforms - assert_approx_eq!(1.0f32.gamma(), 1.0f32, APPROX_DELTA); - assert_approx_eq!(2.0f32.gamma(), 1.0f32, APPROX_DELTA); - assert_approx_eq!(3.0f32.gamma(), 2.0f32, APPROX_DELTA); - assert_approx_eq!(4.0f32.gamma(), 6.0f32, APPROX_DELTA); - assert_approx_eq!(5.0f32.gamma(), 24.0f32, APPROX_DELTA); - assert_approx_eq!(0.5f32.gamma(), consts::PI.sqrt(), APPROX_DELTA); - assert_approx_eq!((-0.5f32).gamma(), -2.0 * consts::PI.sqrt(), APPROX_DELTA); - assert_eq!(0.0f32.gamma(), f32::INFINITY); - assert_eq!((-0.0f32).gamma(), f32::NEG_INFINITY); - assert!((-1.0f32).gamma().is_nan()); - assert!((-2.0f32).gamma().is_nan()); - assert!(f32::NAN.gamma().is_nan()); - assert!(f32::NEG_INFINITY.gamma().is_nan()); - assert_eq!(f32::INFINITY.gamma(), f32::INFINITY); - assert_eq!(171.71f32.gamma(), f32::INFINITY); -} - -#[test] -fn test_ln_gamma() { - assert_approx_eq!(1.0f32.ln_gamma().0, 0.0f32); - assert_eq!(1.0f32.ln_gamma().1, 1); - assert_approx_eq!(2.0f32.ln_gamma().0, 0.0f32); - assert_eq!(2.0f32.ln_gamma().1, 1); - assert_approx_eq!(3.0f32.ln_gamma().0, 2.0f32.ln()); - assert_eq!(3.0f32.ln_gamma().1, 1); - assert_approx_eq!((-0.5f32).ln_gamma().0, (2.0 * consts::PI.sqrt()).ln(), APPROX_DELTA); - assert_eq!((-0.5f32).ln_gamma().1, -1); -} - -#[test] -fn test_real_consts() { - let pi: f32 = consts::PI; - let frac_pi_2: f32 = consts::FRAC_PI_2; - let frac_pi_3: f32 = consts::FRAC_PI_3; - let frac_pi_4: f32 = consts::FRAC_PI_4; - let frac_pi_6: f32 = consts::FRAC_PI_6; - let frac_pi_8: f32 = consts::FRAC_PI_8; - let frac_1_pi: f32 = consts::FRAC_1_PI; - let frac_2_pi: f32 = consts::FRAC_2_PI; - let frac_2_sqrtpi: f32 = consts::FRAC_2_SQRT_PI; - let sqrt2: f32 = consts::SQRT_2; - let frac_1_sqrt2: f32 = consts::FRAC_1_SQRT_2; - let e: f32 = consts::E; - let log2_e: f32 = consts::LOG2_E; - let log10_e: f32 = consts::LOG10_E; - let ln_2: f32 = consts::LN_2; - let ln_10: f32 = consts::LN_10; - - assert_approx_eq!(frac_pi_2, pi / 2f32); - assert_approx_eq!(frac_pi_3, pi / 3f32, APPROX_DELTA); - assert_approx_eq!(frac_pi_4, pi / 4f32); - assert_approx_eq!(frac_pi_6, pi / 6f32); - assert_approx_eq!(frac_pi_8, pi / 8f32); - assert_approx_eq!(frac_1_pi, 1f32 / pi); - assert_approx_eq!(frac_2_pi, 2f32 / pi); - assert_approx_eq!(frac_2_sqrtpi, 2f32 / pi.sqrt()); - assert_approx_eq!(sqrt2, 2f32.sqrt()); - assert_approx_eq!(frac_1_sqrt2, 1f32 / 2f32.sqrt()); - assert_approx_eq!(log2_e, e.log2()); - assert_approx_eq!(log10_e, e.log10()); - assert_approx_eq!(ln_2, 2f32.ln()); - assert_approx_eq!(ln_10, 10f32.ln(), APPROX_DELTA); -} diff --git a/library/std/tests/floats/f64.rs b/library/std/tests/floats/f64.rs deleted file mode 100644 index fccf20097278b..0000000000000 --- a/library/std/tests/floats/f64.rs +++ /dev/null @@ -1,249 +0,0 @@ -use std::f64::consts; - -#[allow(unused_macros)] -macro_rules! assert_f64_biteq { - ($left : expr, $right : expr) => { - let l: &f64 = &$left; - let r: &f64 = &$right; - let lb = l.to_bits(); - let rb = r.to_bits(); - assert_eq!(lb, rb, "float {l} ({lb:#018x}) is not bitequal to {r} ({rb:#018x})"); - }; -} - -#[test] -fn test_powf() { - let nan: f64 = f64::NAN; - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - assert_eq!(1.0f64.powf(1.0), 1.0); - assert_approx_eq!(3.4f64.powf(4.5), 246.408183); - assert_approx_eq!(2.7f64.powf(-3.2), 0.041652); - assert_approx_eq!((-3.1f64).powf(2.0), 9.61); - assert_approx_eq!(5.9f64.powf(-2.0), 0.028727); - assert_eq!(8.3f64.powf(0.0), 1.0); - assert!(nan.powf(2.0).is_nan()); - assert_eq!(inf.powf(2.0), inf); - assert_eq!(neg_inf.powf(3.0), neg_inf); -} - -#[test] -fn test_exp() { - assert_eq!(1.0, 0.0f64.exp()); - assert_approx_eq!(2.718282, 1.0f64.exp()); - assert_approx_eq!(148.413159, 5.0f64.exp()); - - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - let nan: f64 = f64::NAN; - assert_eq!(inf, inf.exp()); - assert_eq!(0.0, neg_inf.exp()); - assert!(nan.exp().is_nan()); -} - -#[test] -fn test_exp2() { - assert_approx_eq!(32.0, 5.0f64.exp2()); - assert_eq!(1.0, 0.0f64.exp2()); - - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - let nan: f64 = f64::NAN; - assert_eq!(inf, inf.exp2()); - assert_eq!(0.0, neg_inf.exp2()); - assert!(nan.exp2().is_nan()); -} - -#[test] -fn test_ln() { - let nan: f64 = f64::NAN; - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - assert_approx_eq!(1.0f64.exp().ln(), 1.0); - assert!(nan.ln().is_nan()); - assert_eq!(inf.ln(), inf); - assert!(neg_inf.ln().is_nan()); - assert!((-2.3f64).ln().is_nan()); - assert_eq!((-0.0f64).ln(), neg_inf); - assert_eq!(0.0f64.ln(), neg_inf); - assert_approx_eq!(4.0f64.ln(), 1.386294); -} - -#[test] -fn test_log() { - let nan: f64 = f64::NAN; - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - assert_approx_eq!(10.0f64.log(10.0), 1.0); - assert_approx_eq!(2.3f64.log(3.5), 0.664858); - assert_approx_eq!(1.0f64.exp().log(1.0f64.exp()), 1.0); - assert!(1.0f64.log(1.0).is_nan()); - assert!(1.0f64.log(-13.9).is_nan()); - assert!(nan.log(2.3).is_nan()); - assert_eq!(inf.log(10.0), inf); - assert!(neg_inf.log(8.8).is_nan()); - assert!((-2.3f64).log(0.1).is_nan()); - assert_eq!((-0.0f64).log(2.0), neg_inf); - assert_eq!(0.0f64.log(7.0), neg_inf); -} - -#[test] -fn test_log2() { - let nan: f64 = f64::NAN; - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - assert_approx_eq!(10.0f64.log2(), 3.321928); - assert_approx_eq!(2.3f64.log2(), 1.201634); - assert_approx_eq!(1.0f64.exp().log2(), 1.442695); - assert!(nan.log2().is_nan()); - assert_eq!(inf.log2(), inf); - assert!(neg_inf.log2().is_nan()); - assert!((-2.3f64).log2().is_nan()); - assert_eq!((-0.0f64).log2(), neg_inf); - assert_eq!(0.0f64.log2(), neg_inf); -} - -#[test] -fn test_log10() { - let nan: f64 = f64::NAN; - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - assert_approx_eq!(10.0f64.log10(), 1.0); - assert_approx_eq!(2.3f64.log10(), 0.361728); - assert_approx_eq!(1.0f64.exp().log10(), 0.434294); - assert_eq!(1.0f64.log10(), 0.0); - assert!(nan.log10().is_nan()); - assert_eq!(inf.log10(), inf); - assert!(neg_inf.log10().is_nan()); - assert!((-2.3f64).log10().is_nan()); - assert_eq!((-0.0f64).log10(), neg_inf); - assert_eq!(0.0f64.log10(), neg_inf); -} - -#[test] -fn test_asinh() { - assert_eq!(0.0f64.asinh(), 0.0f64); - assert_eq!((-0.0f64).asinh(), -0.0f64); - - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - let nan: f64 = f64::NAN; - assert_eq!(inf.asinh(), inf); - assert_eq!(neg_inf.asinh(), neg_inf); - assert!(nan.asinh().is_nan()); - assert!((-0.0f64).asinh().is_sign_negative()); - // issue 63271 - assert_approx_eq!(2.0f64.asinh(), 1.443635475178810342493276740273105f64); - assert_approx_eq!((-2.0f64).asinh(), -1.443635475178810342493276740273105f64); - // regression test for the catastrophic cancellation fixed in 72486 - assert_approx_eq!((-67452098.07139316f64).asinh(), -18.72007542627454439398548429400083); - - // test for low accuracy from issue 104548 - assert_approx_eq!(60.0f64, 60.0f64.sinh().asinh()); - // mul needed for approximate comparison to be meaningful - assert_approx_eq!(1.0f64, 1e-15f64.sinh().asinh() * 1e15f64); -} - -#[test] -fn test_acosh() { - assert_eq!(1.0f64.acosh(), 0.0f64); - assert!(0.999f64.acosh().is_nan()); - - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - let nan: f64 = f64::NAN; - assert_eq!(inf.acosh(), inf); - assert!(neg_inf.acosh().is_nan()); - assert!(nan.acosh().is_nan()); - assert_approx_eq!(2.0f64.acosh(), 1.31695789692481670862504634730796844f64); - assert_approx_eq!(3.0f64.acosh(), 1.76274717403908605046521864995958461f64); - - // test for low accuracy from issue 104548 - assert_approx_eq!(60.0f64, 60.0f64.cosh().acosh()); -} - -#[test] -fn test_atanh() { - assert_eq!(0.0f64.atanh(), 0.0f64); - assert_eq!((-0.0f64).atanh(), -0.0f64); - - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - let nan: f64 = f64::NAN; - assert_eq!(1.0f64.atanh(), inf); - assert_eq!((-1.0f64).atanh(), neg_inf); - assert!(2f64.atanh().atanh().is_nan()); - assert!((-2f64).atanh().atanh().is_nan()); - assert!(inf.atanh().is_nan()); - assert!(neg_inf.atanh().is_nan()); - assert!(nan.atanh().is_nan()); - assert_approx_eq!(0.5f64.atanh(), 0.54930614433405484569762261846126285f64); - assert_approx_eq!((-0.5f64).atanh(), -0.54930614433405484569762261846126285f64); -} - -#[test] -fn test_gamma() { - // precision can differ between platforms - assert_approx_eq!(1.0f64.gamma(), 1.0f64); - assert_approx_eq!(2.0f64.gamma(), 1.0f64); - assert_approx_eq!(3.0f64.gamma(), 2.0f64); - assert_approx_eq!(4.0f64.gamma(), 6.0f64); - assert_approx_eq!(5.0f64.gamma(), 24.0f64); - assert_approx_eq!(0.5f64.gamma(), consts::PI.sqrt()); - assert_approx_eq!((-0.5f64).gamma(), -2.0 * consts::PI.sqrt()); - assert_eq!(0.0f64.gamma(), f64::INFINITY); - assert_eq!((-0.0f64).gamma(), f64::NEG_INFINITY); - assert!((-1.0f64).gamma().is_nan()); - assert!((-2.0f64).gamma().is_nan()); - assert!(f64::NAN.gamma().is_nan()); - assert!(f64::NEG_INFINITY.gamma().is_nan()); - assert_eq!(f64::INFINITY.gamma(), f64::INFINITY); - assert_eq!(171.71f64.gamma(), f64::INFINITY); -} - -#[test] -fn test_ln_gamma() { - assert_approx_eq!(1.0f64.ln_gamma().0, 0.0f64); - assert_eq!(1.0f64.ln_gamma().1, 1); - assert_approx_eq!(2.0f64.ln_gamma().0, 0.0f64); - assert_eq!(2.0f64.ln_gamma().1, 1); - assert_approx_eq!(3.0f64.ln_gamma().0, 2.0f64.ln()); - assert_eq!(3.0f64.ln_gamma().1, 1); - assert_approx_eq!((-0.5f64).ln_gamma().0, (2.0 * consts::PI.sqrt()).ln()); - assert_eq!((-0.5f64).ln_gamma().1, -1); -} - -#[test] -fn test_real_consts() { - let pi: f64 = consts::PI; - let frac_pi_2: f64 = consts::FRAC_PI_2; - let frac_pi_3: f64 = consts::FRAC_PI_3; - let frac_pi_4: f64 = consts::FRAC_PI_4; - let frac_pi_6: f64 = consts::FRAC_PI_6; - let frac_pi_8: f64 = consts::FRAC_PI_8; - let frac_1_pi: f64 = consts::FRAC_1_PI; - let frac_2_pi: f64 = consts::FRAC_2_PI; - let frac_2_sqrtpi: f64 = consts::FRAC_2_SQRT_PI; - let sqrt2: f64 = consts::SQRT_2; - let frac_1_sqrt2: f64 = consts::FRAC_1_SQRT_2; - let e: f64 = consts::E; - let log2_e: f64 = consts::LOG2_E; - let log10_e: f64 = consts::LOG10_E; - let ln_2: f64 = consts::LN_2; - let ln_10: f64 = consts::LN_10; - - assert_approx_eq!(frac_pi_2, pi / 2f64); - assert_approx_eq!(frac_pi_3, pi / 3f64); - assert_approx_eq!(frac_pi_4, pi / 4f64); - assert_approx_eq!(frac_pi_6, pi / 6f64); - assert_approx_eq!(frac_pi_8, pi / 8f64); - assert_approx_eq!(frac_1_pi, 1f64 / pi); - assert_approx_eq!(frac_2_pi, 2f64 / pi); - assert_approx_eq!(frac_2_sqrtpi, 2f64 / pi.sqrt()); - assert_approx_eq!(sqrt2, 2f64.sqrt()); - assert_approx_eq!(frac_1_sqrt2, 1f64 / 2f64.sqrt()); - assert_approx_eq!(log2_e, e.log2()); - assert_approx_eq!(log10_e, e.log10()); - assert_approx_eq!(ln_2, 2f64.ln()); - assert_approx_eq!(ln_10, 10f64.ln()); -} diff --git a/library/std/tests/floats/lib.rs b/library/std/tests/floats/lib.rs deleted file mode 100644 index 8bb8eb4bfc1ae..0000000000000 --- a/library/std/tests/floats/lib.rs +++ /dev/null @@ -1,43 +0,0 @@ -#![feature(f16, f128, float_gamma, float_minimum_maximum, cfg_target_has_reliable_f16_f128)] -#![expect(internal_features)] // for reliable_f16_f128 - -use std::fmt; -use std::ops::{Add, Div, Mul, Rem, Sub}; - -/// Verify that floats are within a tolerance of each other, 1.0e-6 by default. -macro_rules! assert_approx_eq { - ($a:expr, $b:expr) => {{ assert_approx_eq!($a, $b, 1.0e-6) }}; - ($a:expr, $b:expr, $lim:expr) => {{ - let (a, b) = (&$a, &$b); - let diff = (*a - *b).abs(); - assert!( - diff <= $lim, - "{a:?} is not approximately equal to {b:?} (threshold {lim:?}, difference {diff:?})", - lim = $lim - ); - }}; -} - -/// Helper function for testing numeric operations -pub fn test_num(ten: T, two: T) -where - T: PartialEq - + Add - + Sub - + Mul - + Div - + Rem - + fmt::Debug - + Copy, -{ - assert_eq!(ten.add(two), ten + two); - assert_eq!(ten.sub(two), ten - two); - assert_eq!(ten.mul(two), ten * two); - assert_eq!(ten.div(two), ten / two); - assert_eq!(ten.rem(two), ten % two); -} - -mod f128; -mod f16; -mod f32; -mod f64; diff --git a/library/std/tests/path.rs b/library/std/tests/path.rs index 4094b7acd8749..8997b8ad192dc 100644 --- a/library/std/tests/path.rs +++ b/library/std/tests/path.rs @@ -2291,6 +2291,26 @@ fn display_format_flags() { assert_eq!(format!("a{:#<5}b", Path::new("a").display()), "aa####b"); } +#[test] +fn display_path_with_padding_no_align() { + assert_eq!(format!("{:10}", Path::new("/foo/bar").display()), "/foo/bar "); +} + +#[test] +fn display_path_with_padding_align_left() { + assert_eq!(format!("{:<10}", Path::new("/foo/bar").display()), "/foo/bar "); +} + +#[test] +fn display_path_with_padding_align_right() { + assert_eq!(format!("{:>10}", Path::new("/foo/bar").display()), " /foo/bar"); +} + +#[test] +fn display_path_with_padding_align_center() { + assert_eq!(format!("{:^10}", Path::new("/foo/bar").display()), " /foo/bar "); +} + #[test] fn into_rc() { let orig = "hello/world"; diff --git a/library/std/tests/pipe_subprocess.rs b/library/std/tests/pipe_subprocess.rs index c51a4459e718b..c14db690224db 100644 --- a/library/std/tests/pipe_subprocess.rs +++ b/library/std/tests/pipe_subprocess.rs @@ -1,5 +1,10 @@ fn main() { - #[cfg(all(not(miri), any(unix, windows), not(target_os = "emscripten")))] + // No `Command` on Miri, emscripten or L4Re + #[cfg(all( + not(miri), + any(unix, windows), + not(any(target_os = "emscripten", target_os = "l4re")) + ))] { use std::io::{Read, pipe}; use std::{env, process}; @@ -12,10 +17,16 @@ fn main() { fn parent() { let me = env::current_exe().unwrap(); + // If a custom `runner` is set up for the current target, we'll be + // executing `./runner ./test`, not just `./test`. For such a case, + // use the same arguments for child to avoid executing `runner` + // without an actual executable. + let args = env::args(); let (rx, tx) = pipe().unwrap(); assert!( process::Command::new(me) + .args(args) .env("I_AM_THE_CHILD", "1") .stdout(tx) .status() diff --git a/library/std/tests/process_spawning.rs b/library/std/tests/process_spawning.rs index 93f73ccad3ea4..b7a9a1077696b 100644 --- a/library/std/tests/process_spawning.rs +++ b/library/std/tests/process_spawning.rs @@ -7,7 +7,10 @@ mod common; #[test] // Process spawning not supported by Miri, Emscripten and wasi #[cfg_attr(any(miri, target_os = "emscripten", target_os = "wasi"), ignore)] -#[cfg_attr(any(target_os = "tvos", target_os = "watchos"), ignore = "fork is prohibited")] +#[cfg_attr( + any(target_os = "tvos", target_os = "watchos", target_os = "l4re"), + ignore = "fork is prohibited" +)] fn issue_15149() { // If we're the parent, copy our own binary to a new directory. let my_path = env::current_exe().unwrap(); @@ -26,8 +29,16 @@ fn issue_15149() { env::join_paths(paths).unwrap() }; - let child_output = - process::Command::new("mytest").env("PATH", &path).arg("child").output().unwrap(); + // If a custom `runner` is set up for the current target, we'll be executing `./runner ./test`, + // not just `./test`. For such a case, use the same arguments for child to avoid executing + // `runner` without an actual executable. + let args = env::args(); + let child_output = process::Command::new("mytest") + .args(args) + .env("PATH", &path) + .arg("child") + .output() + .unwrap(); assert!( child_output.status.success(), diff --git a/library/std/tests/sync/lazy_lock.rs b/library/std/tests/sync/lazy_lock.rs index 68aeea834b4fa..c549094dd1381 100644 --- a/library/std/tests/sync/lazy_lock.rs +++ b/library/std/tests/sync/lazy_lock.rs @@ -33,6 +33,15 @@ fn lazy_default() { assert_eq!(CALLED.load(SeqCst), 1); } +#[test] +fn const_lazy_default() { + // using Box as it cannot be initialized in const contexts + const X: LazyLock> = <_>::default(); + const Y: LazyCell> = <_>::default(); + assert_eq!(**X, 0); + assert_eq!(**Y, 0); +} + #[test] #[cfg_attr(any(target_os = "emscripten", target_os = "wasi"), ignore)] // no threads fn sync_lazy_new() { diff --git a/library/std/tests/sync/lib.rs b/library/std/tests/sync/lib.rs index 32a7efde2a257..92c4c2f511be3 100644 --- a/library/std/tests/sync/lib.rs +++ b/library/std/tests/sync/lib.rs @@ -1,3 +1,5 @@ +#![feature(const_default)] +#![feature(const_trait_impl)] #![feature(mapped_lock_guards)] #![feature(mpmc_channel)] #![feature(oneshot_channel)] diff --git a/library/std/tests/sync/mpmc.rs b/library/std/tests/sync/mpmc.rs index bf80ab96a88bd..e8ed5ab13d009 100644 --- a/library/std/tests/sync/mpmc.rs +++ b/library/std/tests/sync/mpmc.rs @@ -419,34 +419,48 @@ fn oneshot_multi_thread_send_recv_stress() { #[test] fn stream_send_recv_stress() { - for _ in 0..stress_factor() { - let (tx, rx) = channel(); - - send(tx, 0); - recv(rx, 0); + thread::scope(|s| { + for _ in 0..stress_factor() { + let (tx, rx) = channel(); + + send(tx, 0, s); + recv(rx, 0, s); + + fn send<'scope, 'env>( + tx: Sender>, + i: i32, + s: &'scope thread::Scope<'scope, 'env>, + ) where + 'env: 'scope, + { + if i == 10 { + return; + } - fn send(tx: Sender>, i: i32) { - if i == 10 { - return; + s.spawn(move || { + tx.send(Box::new(i)).unwrap(); + send(tx, i + 1, s); + }); } - thread::spawn(move || { - tx.send(Box::new(i)).unwrap(); - send(tx, i + 1); - }); - } + fn recv<'scope, 'env>( + rx: Receiver>, + i: i32, + s: &'scope thread::Scope<'scope, 'env>, + ) where + 'env: 'scope, + { + if i == 10 { + return; + } - fn recv(rx: Receiver>, i: i32) { - if i == 10 { - return; + s.spawn(move || { + assert!(*rx.recv().unwrap() == i); + recv(rx, i + 1, s); + }); } - - thread::spawn(move || { - assert!(*rx.recv().unwrap() == i); - recv(rx, i + 1); - }); } - } + }) } #[test] @@ -475,7 +489,6 @@ fn stress_recv_timeout_two_threads() { }); let mut recv_count = 0; - let mut got_timeout = false; loop { match rx.recv_timeout(timeout) { Ok(n) => { @@ -483,7 +496,6 @@ fn stress_recv_timeout_two_threads() { recv_count += 1; } Err(RecvTimeoutError::Timeout) => { - got_timeout = true; continue; } Err(RecvTimeoutError::Disconnected) => break, @@ -491,7 +503,6 @@ fn stress_recv_timeout_two_threads() { } assert_eq!(recv_count, stress); - assert!(got_timeout); } #[test] diff --git a/library/std/tests/sync/mpsc.rs b/library/std/tests/sync/mpsc.rs index 9de4a71987b8e..f1364dda713a1 100644 --- a/library/std/tests/sync/mpsc.rs +++ b/library/std/tests/sync/mpsc.rs @@ -382,34 +382,48 @@ fn oneshot_multi_thread_send_recv_stress() { #[test] fn stream_send_recv_stress() { - for _ in 0..stress_factor() { - let (tx, rx) = channel(); - - send(tx, 0); - recv(rx, 0); + thread::scope(|s| { + for _ in 0..stress_factor() { + let (tx, rx) = channel(); + + send(tx, 0, s); + recv(rx, 0, s); + + fn send<'scope, 'env>( + tx: Sender>, + i: i32, + s: &'scope thread::Scope<'scope, 'env>, + ) where + 'env: 'scope, + { + if i == 10 { + return; + } - fn send(tx: Sender>, i: i32) { - if i == 10 { - return; + s.spawn(move || { + tx.send(Box::new(i)).unwrap(); + send(tx, i + 1, s); + }); } - thread::spawn(move || { - tx.send(Box::new(i)).unwrap(); - send(tx, i + 1); - }); - } + fn recv<'scope, 'env>( + rx: Receiver>, + i: i32, + s: &'scope thread::Scope<'scope, 'env>, + ) where + 'env: 'scope, + { + if i == 10 { + return; + } - fn recv(rx: Receiver>, i: i32) { - if i == 10 { - return; + s.spawn(move || { + assert!(*rx.recv().unwrap() == i); + recv(rx, i + 1, s); + }); } - - thread::spawn(move || { - assert!(*rx.recv().unwrap() == i); - recv(rx, i + 1); - }); } - } + }) } #[test] @@ -438,7 +452,6 @@ fn stress_recv_timeout_two_threads() { }); let mut recv_count = 0; - let mut got_timeout = false; loop { match rx.recv_timeout(timeout) { Ok(n) => { @@ -446,7 +459,6 @@ fn stress_recv_timeout_two_threads() { recv_count += 1; } Err(RecvTimeoutError::Timeout) => { - got_timeout = true; continue; } Err(RecvTimeoutError::Disconnected) => break, @@ -454,7 +466,6 @@ fn stress_recv_timeout_two_threads() { } assert_eq!(recv_count, stress); - assert!(got_timeout); } #[test] diff --git a/library/std/tests/sync/oneshot.rs b/library/std/tests/sync/oneshot.rs index 6a87c72b9cb5b..6eaacfbc6497d 100644 --- a/library/std/tests/sync/oneshot.rs +++ b/library/std/tests/sync/oneshot.rs @@ -89,15 +89,15 @@ fn send_before_recv_timeout() { assert!(sender.send(22i128).is_ok()); - let start = Instant::now(); - let timeout = Duration::from_secs(1); match receiver.recv_timeout(timeout) { Ok(22) => {} _ => panic!("expected Ok(22)"), } - assert!(start.elapsed() < timeout); + // FIXME(#152648): There previously was a timing assertion here. + // This was removed, because under load there's no guarantee that the main thread is + // scheduled and run before `timeout` expires } #[test] @@ -127,6 +127,7 @@ fn recv_before_send() { } #[test] +#[ignore = "Inherently flaky and has caused several CI failures"] fn recv_timeout_before_send() { let (sender, receiver) = oneshot::channel(); @@ -135,6 +136,8 @@ fn recv_timeout_before_send() { sender.send(99u128).unwrap(); }); + // FIXME(#152145): Under load, there's no guarantee that thread `t` has + // ever been scheduled and run before this timeout expires. match receiver.recv_timeout(Duration::from_secs(1)) { Ok(99) => {} _ => panic!("expected Ok(99)"), @@ -240,7 +243,9 @@ fn recv_deadline_passed() { } assert!(start.elapsed() >= timeout); - assert!(start.elapsed() < timeout * 3); + // FIXME(#152878): An upper-bound assertion on the elapsed time was removed, + // because CI runners can starve individual threads for a surprisingly long + // time, leading to flaky failures. } #[test] @@ -249,12 +254,16 @@ fn recv_time_passed() { let start = Instant::now(); let timeout = Duration::from_millis(100); + match receiver.recv_timeout(timeout) { Err(RecvTimeoutError::Timeout(_)) => {} _ => panic!("expected timeout error"), } + assert!(start.elapsed() >= timeout); - assert!(start.elapsed() < timeout * 3); + // FIXME(#152878): An upper-bound assertion on the elapsed time was removed, + // because CI runners can starve individual threads for a surprisingly long + // time, leading to flaky failures. } #[test] diff --git a/library/std/tests/sync/rwlock.rs b/library/std/tests/sync/rwlock.rs index 392c45c8ba05d..311866dab4733 100644 --- a/library/std/tests/sync/rwlock.rs +++ b/library/std/tests/sync/rwlock.rs @@ -883,3 +883,63 @@ fn test_rwlock_with_mut() { assert_eq!(*rwlock.read(), 5); assert_eq!(result, 10); } + +// To note: there are (currently) four different implementations of Rwlock: +// - On Windows (but not Win 7), Linux, Android, FreeBSD, OpenBSD, DragonFly, +// Fuchsia, WASM, Hermit, and Motor OSs, it relies on rwlock/futex.rs, which has +// a max reader of 1 << 30 - 2 (or 1073741822). A "too many active reader" error +// is displayed after it exceeds the max number of readers. +// - On Unix, Win 7, Fortranix (target env of sgx), Xous, and TeeOS, it leans +// on rwlock/queue.rs, which uses a linked list under the hood stored on the stack +// to hold a queue of waiters. Assuming no stack overflow, the max number of readers +// that can be queued up at one time is limited to usize::MAX - (1 << 4) as the first +// four bits are reserved for LOCKED, QUEUED, QUEUE_LOCKED, and DOWNGRADED flags. Any +// pending readers after that max count, parks the thread and tries to acquire a read lock +// again when the thread wakes up. +// - On SolidASP3, it leans on rwlock/solid.rs, which utilizes rwl_loc_rdl, so the max +// number of readers depends on the internal implementation of rwl_loc_rdl. +// - Every other platforms utilizes rwlock/no_threads.rs, which has a max reader of +// isize::MAX. An arithmetic overflow error occurs if it exceeds the max reader count. +#[test] +fn test_rwlock_max_readers() { + let mut read_lock_ctr: u32 = 0; + let rwlock: RwLock = RwLock::new(0); + + const MAX_READERS: u32 = + cfg_select! { + miri => 100, + any( + all(target_os = "windows", not(target_vendor = "win7")), + target_os = "linux", + target_os = "android", + target_os = "freebsd", + target_os = "openbsd", + target_os = "dragonfly", + target_os = "fuchsia", + all(target_family = "wasm", target_feature = "atomics"), + target_os = "hermit", + target_os = "motor", + ) => (1 << 30) - 2, + any( + target_family = "unix", + all(target_os = "windows", target_vendor = "win7", target_pointer_width = "64"), + all(target_vendor = "fortanix", target_env = "sgx"), + target_os = "xous", + target_os = "teeos", + ) => u32::MAX, + // Otherwise a form of deadlock is observed. + all(target_os = "windows", target_vendor = "win7", target_pointer_width = "32") => { + (1 << 28) - 1 + } + target_os = "solid_asp3" => (1 << 30), + _ => u32::MAX, + }; + + while read_lock_ctr < MAX_READERS { + let lock = rwlock.read(); + mem::forget(lock); + read_lock_ctr += 1; + } + + assert_eq!(read_lock_ctr, MAX_READERS); +} diff --git a/library/std/tests/thread.rs b/library/std/tests/thread.rs index dc8eadd75148b..ef13ce44d3180 100644 --- a/library/std/tests/thread.rs +++ b/library/std/tests/thread.rs @@ -85,7 +85,6 @@ fn thread_local_hygeiene() { target_env = "sgx", target_os = "solid_asp3", target_os = "teeos", - target_os = "wasi" ), should_panic )] diff --git a/library/std/tests/thread_local/tests.rs b/library/std/tests/thread_local/tests.rs index 5df1a0e25ee51..1a25d91e43bc0 100644 --- a/library/std/tests/thread_local/tests.rs +++ b/library/std/tests/thread_local/tests.rs @@ -21,6 +21,12 @@ impl Signal { set = cvar.wait(set).unwrap(); } } + + fn is_set(&self) -> bool { + let (set, _cvar) = &*self.0; + let set = set.lock().unwrap(); + *set + } } struct NotifyOnDrop(Signal); @@ -97,13 +103,14 @@ fn smoke_dtor() { }); }); signal.wait(); + assert!(signal.is_set()); t.join().unwrap(); } } #[test] fn circular() { - // FIXME(static_mut_refs): Do not allow `static_mut_refs` lint + // FIXME(static_mut_refs): use raw pointers instead of references #![allow(static_mut_refs)] struct S1(&'static LocalKey>>, &'static LocalKey>>); @@ -393,3 +400,52 @@ fn thread_current_in_dtor() { let name = name.as_ref().unwrap(); assert_eq!(name, "test"); } + +// Test that if a thread uses fibers while the dtors callback is running, +// we do NOT trigger dtors. +// This prevents a UAF if a fiber is the first to use Tls and is deleted, +// like in the example here: +// https://github.com/rust-lang/rust/pull/148799#issuecomment-3731806901 +#[cfg(target_os = "windows")] +#[test] +#[cfg_attr(miri, ignore)] // Miri does not support fibers +fn fiber_does_not_trigger_dtor() { + use core::ffi::c_void; + use std::ptr; + + unsafe extern "system" { + fn ConvertFiberToThread() -> i32; + fn ConvertThreadToFiber(lpParameter: *const c_void) -> *mut c_void; + } + + thread_local!(static FOO: UnsafeCell> = UnsafeCell::new(None)); + let signal = Signal::default(); + + let signal2 = signal.clone(); + let t = thread::spawn(move || unsafe { + let mut signal = Some(signal2); + FOO.with(|f| { + *f.get() = Some(NotifyOnDrop(signal.take().unwrap())); + }); + let _main = ConvertThreadToFiber(ptr::null()); + // A user can then switch to a new fiber and delete the main fiber. + // If destructors are triggered when the fiber is deleted, + // the new fiber will be able to observe already-destructed values. + }); + t.join().unwrap(); + assert!(!signal.is_set()); + + // As long as we stop using fibers before thread teardown, everything works as expected. + let signal2 = signal.clone(); + let t = thread::spawn(move || unsafe { + let mut signal = Some(signal2); + let _ = ConvertThreadToFiber(ptr::null()); + FOO.with(|f| { + *f.get() = Some(NotifyOnDrop(signal.take().unwrap())); + }); + let _ = ConvertFiberToThread(); + }); + signal.wait(); + assert!(signal.is_set()); + t.join().unwrap(); +} diff --git a/library/std/tests/time.rs b/library/std/tests/time.rs index b73e7bc3962eb..6d8b4cbfd094f 100644 --- a/library/std/tests/time.rs +++ b/library/std/tests/time.rs @@ -1,4 +1,5 @@ #![feature(duration_constants)] +#![feature(duration_constructors)] #![feature(time_systemtime_limits)] #![feature(time_saturating_systemtime)] @@ -104,7 +105,8 @@ fn instant_math_is_associative() { #[test] fn instant_duration_since_saturates() { let a = Instant::now(); - assert_eq!((a - Duration::SECOND).duration_since(a), Duration::ZERO); + // This also checks that computing an instant before program startup works. + assert_eq!((a - Duration::from_days(1)).duration_since(a), Duration::ZERO); } #[test] @@ -179,6 +181,7 @@ fn system_time_elapsed() { } #[test] +#[cfg_attr(target_os = "l4re", ignore = "No wallclock time support in L4Re")] fn since_epoch() { let ts = SystemTime::now(); let a = ts.duration_since(UNIX_EPOCH + Duration::SECOND).unwrap(); diff --git a/library/std/tests/volatile-fat-ptr.rs b/library/std/tests/volatile-fat-ptr.rs index b005c12c6187b..406eb7c80afb5 100644 --- a/library/std/tests/volatile-fat-ptr.rs +++ b/library/std/tests/volatile-fat-ptr.rs @@ -1,6 +1,3 @@ -#![allow(stable_features)] -#![feature(volatile)] - use std::ptr::{read_volatile, write_volatile}; #[test] diff --git a/library/std/tests/windows_unix_socket.rs b/library/std/tests/windows_unix_socket.rs index 1f20cf586ca25..dd71b1f135dce 100644 --- a/library/std/tests/windows_unix_socket.rs +++ b/library/std/tests/windows_unix_socket.rs @@ -1,14 +1,28 @@ #![cfg(windows)] -#![cfg(not(miri))] // no socket support in Miri +#![cfg(not(miri))] // no Windows socket support in Miri #![feature(windows_unix_domain_sockets)] // Now only test windows_unix_domain_sockets feature // in the future, will test both unix and windows uds use std::io::{Read, Write}; use std::os::windows::net::{UnixListener, UnixStream}; -use std::thread; +use std::{mem, thread}; + +macro_rules! skip_nonapplicable_oses { + () => { + // UDS have been available under Windows since Insider Preview Build + // 17063. "Redstone 4" (RS4, version 1803, build number 17134) is + // therefore the first official release to include it. + if !is_windows_10_v1803_or_greater() { + println!("Not running this test on too-old Windows."); + return; + } + }; +} #[test] fn win_uds_smoke_bind_connect() { + skip_nonapplicable_oses!(); + let tmp = std::env::temp_dir(); let sock_path = tmp.join("rust-test-uds-smoke.sock"); let _ = std::fs::remove_file(&sock_path); @@ -32,6 +46,8 @@ fn win_uds_smoke_bind_connect() { #[test] fn win_uds_echo() { + skip_nonapplicable_oses!(); + let tmp = std::env::temp_dir(); let sock_path = tmp.join("rust-test-uds-echo.sock"); let _ = std::fs::remove_file(&sock_path); @@ -68,14 +84,19 @@ fn win_uds_echo() { #[test] fn win_uds_path_too_long() { + skip_nonapplicable_oses!(); + let tmp = std::env::temp_dir(); let long_path = tmp.join("a".repeat(200)); let result = UnixListener::bind(&long_path); assert!(result.is_err()); let _ = std::fs::remove_file(&long_path); } + #[test] fn win_uds_existing_bind() { + skip_nonapplicable_oses!(); + let tmp = std::env::temp_dir(); let sock_path = tmp.join("rust-test-uds-existing.sock"); let _ = std::fs::remove_file(&sock_path); @@ -85,3 +106,115 @@ fn win_uds_existing_bind() { drop(listener); let _ = std::fs::remove_file(&sock_path); } + +/// Returns true if we are currently running on Windows 10 v1803 (RS4) or greater. +fn is_windows_10_v1803_or_greater() -> bool { + is_windows_version_greater_or_equal(NTDDI_WIN10_RS4) +} + +/// Returns true if we are currently running on the given version of Windows +/// 10 (or newer). +fn is_windows_version_greater_or_equal(min_version: u32) -> bool { + is_windows_version_or_greater(HIBYTE(OSVER(min_version)), LOBYTE(OSVER(min_version)), 0, 0) +} + +/// Checks if we are running a version of Windows newer than the specified one. +fn is_windows_version_or_greater( + major: u8, + minor: u8, + service_pack: u8, + build_number: u32, +) -> bool { + let mut osvi = OSVERSIONINFOEXW { + dwOSVersionInfoSize: mem::size_of::() as _, + dwMajorVersion: u32::from(major), + dwMinorVersion: u32::from(minor), + wServicePackMajor: u16::from(service_pack), + dwBuildNumber: build_number, + ..OSVERSIONINFOEXW::default() + }; + + // SAFETY: this function is always safe to call. + let condmask = unsafe { + VerSetConditionMask( + VerSetConditionMask( + VerSetConditionMask( + VerSetConditionMask(0, VER_MAJORVERSION, VER_GREATER_EQUAL as _), + VER_MINORVERSION, + VER_GREATER_EQUAL as _, + ), + VER_SERVICEPACKMAJOR, + VER_GREATER_EQUAL as _, + ), + VER_BUILDNUMBER, + VER_GREATER_EQUAL as _, + ) + }; + + // SAFETY: osvi needs to point to a memory region valid for at least + // dwOSVersionInfoSize bytes, which is the case here. + (unsafe { + RtlVerifyVersionInfo( + &raw mut osvi, + VER_MAJORVERSION | VER_MINORVERSION | VER_SERVICEPACKMAJOR, + condmask, + ) + }) == STATUS_SUCCESS +} + +#[expect(non_snake_case)] +const fn HIBYTE(x: u16) -> u8 { + ((x >> 8) & 0xFF) as u8 +} + +#[expect(non_snake_case)] +const fn LOBYTE(x: u16) -> u8 { + (x & 0xFF) as u8 +} + +#[expect(non_snake_case)] +const fn OSVER(x: u32) -> u16 { + ((x & OSVERSION_MASK) >> 16) as u16 +} + +// Inlined bindings because outside of `std` here. + +type NTSTATUS = i32; +const STATUS_SUCCESS: NTSTATUS = 0; + +#[expect(non_camel_case_types)] +type VER_FLAGS = u32; +const VER_BUILDNUMBER: VER_FLAGS = 4u32; +const VER_GREATER_EQUAL: VER_FLAGS = 3u32; +const VER_MAJORVERSION: VER_FLAGS = 2u32; +const VER_MINORVERSION: VER_FLAGS = 1u32; +const VER_SERVICEPACKMAJOR: VER_FLAGS = 32u32; + +const OSVERSION_MASK: u32 = 4294901760u32; +const NTDDI_WIN10_RS4: u32 = 167772165u32; + +#[expect(non_snake_case)] +#[repr(C)] +#[derive(Clone, Copy)] +struct OSVERSIONINFOEXW { + pub dwOSVersionInfoSize: u32, + pub dwMajorVersion: u32, + pub dwMinorVersion: u32, + pub dwBuildNumber: u32, + pub dwPlatformId: u32, + pub szCSDVersion: [u16; 128], + pub wServicePackMajor: u16, + pub wServicePackMinor: u16, + pub wSuiteMask: u16, + pub wProductType: u8, + pub wReserved: u8, +} + +impl Default for OSVERSIONINFOEXW { + fn default() -> Self { + unsafe { core::mem::zeroed() } + } +} + +windows_link::link!("ntdll.dll" "system" fn RtlVerifyVersionInfo(versioninfo : *const OSVERSIONINFOEXW, typemask : u32, conditionmask : u64) -> NTSTATUS); +windows_link::link!("kernel32.dll" "system" fn VerSetConditionMask(conditionmask : u64, typemask : VER_FLAGS, condition : u8) -> u64); diff --git a/library/std_detect/README.md b/library/std_detect/README.md index 895f3426d0495..8f94d3069c6a9 100644 --- a/library/std_detect/README.md +++ b/library/std_detect/README.md @@ -25,7 +25,7 @@ regard to better serve the needs of `#[no_std]` targets. * All `x86`/`x86_64` targets are supported on all platforms by querying the `cpuid` instruction directly for the features supported by the hardware and - the operating system. `std_detect` assumes that the binary is an user-space + the operating system. `std_detect` assumes that the binary is a user-space application. * Linux/Android: diff --git a/library/std_detect/src/detect/arch/loongarch.rs b/library/std_detect/src/detect/arch/loongarch.rs index 6299627738111..b37f44972a74f 100644 --- a/library/std_detect/src/detect/arch/loongarch.rs +++ b/library/std_detect/src/detect/arch/loongarch.rs @@ -35,19 +35,19 @@ features! { /// D @FEATURE: #[stable(feature = "stdarch_loongarch_feature", since = "1.89.0")] frecipe: "frecipe"; /// Frecipe - @FEATURE: #[unstable(feature = "stdarch_loongarch_feature_detection", issue = "117425")] div32: "div32"; + @FEATURE: #[stable(feature = "stdarch_loongarch_div32", since = "1.97.0")] div32: "div32"; /// Div32 @FEATURE: #[stable(feature = "stdarch_loongarch_feature", since = "1.89.0")] lsx: "lsx"; /// LSX @FEATURE: #[stable(feature = "stdarch_loongarch_feature", since = "1.89.0")] lasx: "lasx"; /// LASX - @FEATURE: #[unstable(feature = "stdarch_loongarch_feature_detection", issue = "117425")] lam_bh: "lam-bh"; + @FEATURE: #[stable(feature = "stdarch_loongarch_lam_bh", since = "1.97.0")] lam_bh: "lam-bh"; /// LAM-BH - @FEATURE: #[unstable(feature = "stdarch_loongarch_feature_detection", issue = "117425")] lamcas: "lamcas"; + @FEATURE: #[stable(feature = "stdarch_loongarch_lamcas", since = "1.97.0")] lamcas: "lamcas"; /// LAM-CAS - @FEATURE: #[unstable(feature = "stdarch_loongarch_feature_detection", issue = "117425")] ld_seq_sa: "ld-seq-sa"; + @FEATURE: #[stable(feature = "stdarch_loongarch_ld_seq_sa", since = "1.97.0")] ld_seq_sa: "ld-seq-sa"; /// LD-SEQ-SA - @FEATURE: #[unstable(feature = "stdarch_loongarch_feature_detection", issue = "117425")] scq: "scq"; + @FEATURE: #[stable(feature = "stdarch_loongarch_scq", since = "1.97.0")] scq: "scq"; /// SCQ @FEATURE: #[stable(feature = "stdarch_loongarch_feature", since = "1.89.0")] lbt: "lbt"; /// LBT diff --git a/library/std_detect/src/detect/arch/mod.rs b/library/std_detect/src/detect/arch/mod.rs index 2be7f091c285e..2ca4cbd1e3fa0 100644 --- a/library/std_detect/src/detect/arch/mod.rs +++ b/library/std_detect/src/detect/arch/mod.rs @@ -67,7 +67,7 @@ cfg_select! { // Unimplemented architecture: #[doc(hidden)] pub(crate) enum Feature { - Null + Null, } #[doc(hidden)] #[unstable(feature = "stdarch_internal", issue = "none")] @@ -75,9 +75,13 @@ cfg_select! { impl Feature { #[doc(hidden)] - pub(crate) fn from_str(_s: &str) -> Result { Err(()) } + pub(crate) fn from_str(_s: &str) -> Result { + Err(()) + } #[doc(hidden)] - pub(crate) fn to_str(self) -> &'static str { "" } + pub(crate) fn to_str(self) -> &'static str { + "" + } } } } diff --git a/library/std_detect/src/detect/arch/x86.rs b/library/std_detect/src/detect/arch/x86.rs index 4c3a71ebc5ee7..e054546afcb19 100644 --- a/library/std_detect/src/detect/arch/x86.rs +++ b/library/std_detect/src/detect/arch/x86.rs @@ -91,7 +91,6 @@ features! { /// * `"amx-avx512"` /// * `"amx-fp8"` /// * `"amx-movrs"` - /// * `"amx-tf32"` /// * `"f16c"` /// * `"fma"` /// * `"bmi1"` @@ -106,6 +105,7 @@ features! { /// * `"xsaves"` /// * `"xsavec"` /// * `"cmpxchg16b"` + /// * `"clflushopt"` /// * `"kl"` /// * `"widekl"` /// * `"adx"` @@ -227,8 +227,6 @@ features! { /// AMX-FP8 (Float8 Operations) @FEATURE: #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] amx_movrs: "amx-movrs"; /// AMX-MOVRS (Matrix MOVERS operations) - @FEATURE: #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] amx_tf32: "amx-tf32"; - /// AMX-TF32 (TensorFloat32 Operations) @FEATURE: #[unstable(feature = "apx_target_feature", issue = "139284")] apxf: "apxf"; /// APX-F (Advanced Performance Extensions - Foundation) @FEATURE: #[unstable(feature = "avx10_target_feature", issue = "138843")] avx10_1: "avx10.1"; @@ -261,6 +259,8 @@ features! { /// XSAVEC (Save Processor Extended States Compacted) @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] cmpxchg16b: "cmpxchg16b"; /// CMPXCH16B (16-byte compare-and-swap instruction) + @FEATURE: #[unstable(feature = "clflushopt_target_feature", issue = "157096")] clflushopt: "clflushopt"; + /// CLFLUSHOPT (Cache Line Flush Optimized) @FEATURE: #[stable(feature = "keylocker_x86", since = "1.89.0")] kl: "kl"; /// Intel Key Locker @FEATURE: #[stable(feature = "keylocker_x86", since = "1.89.0")] widekl: "widekl"; diff --git a/library/std_detect/src/detect/cache.rs b/library/std_detect/src/detect/cache.rs index c0c0b7b7f8635..4f1907b060572 100644 --- a/library/std_detect/src/detect/cache.rs +++ b/library/std_detect/src/detect/cache.rs @@ -121,22 +121,36 @@ cfg_select! { use alloc::vec; #[link(name = "kernel32")] unsafe extern "system" { - fn GetEnvironmentVariableA(name: *const u8, buffer: *mut u8, size: u32) -> u32; + fn GetEnvironmentVariableA( + name: *const u8, + buffer: *mut u8, + size: u32, + ) -> u32; } - let len = unsafe { GetEnvironmentVariableA(RUST_STD_DETECT_UNSTABLE.as_ptr().cast::(), core::ptr::null_mut(), 0) }; + let len = unsafe { + GetEnvironmentVariableA( + RUST_STD_DETECT_UNSTABLE.as_ptr().cast::(), + core::ptr::null_mut(), + 0, + ) + }; if len > 0 { // +1 to include the null terminator. let mut env = vec![0; len as usize + 1]; - let len = unsafe { GetEnvironmentVariableA(RUST_STD_DETECT_UNSTABLE.as_ptr().cast::(), env.as_mut_ptr(), len + 1) }; + let len = unsafe { + GetEnvironmentVariableA( + RUST_STD_DETECT_UNSTABLE.as_ptr().cast::(), + env.as_mut_ptr(), + len + 1, + ) + }; if len > 0 { disable_features(&env[..len as usize], &mut value); } } } _ => { - let env = unsafe { - libc::getenv(RUST_STD_DETECT_UNSTABLE.as_ptr()) - }; + let env = unsafe { libc::getenv(RUST_STD_DETECT_UNSTABLE.as_ptr()) }; if !env.is_null() { let len = unsafe { libc::strlen(env) }; let env = unsafe { core::slice::from_raw_parts(env as *const u8, len) }; diff --git a/library/std_detect/src/detect/macros.rs b/library/std_detect/src/detect/macros.rs index 17140e15653d2..43f59e22c3a9b 100644 --- a/library/std_detect/src/detect/macros.rs +++ b/library/std_detect/src/detect/macros.rs @@ -75,7 +75,7 @@ macro_rules! features { }; )* ($t:tt,) => { - $crate::$macro_name!($t); + $crate::$macro_name!($t) }; ($t:tt) => { compile_error!( diff --git a/library/std_detect/src/detect/os/darwin/aarch64.rs b/library/std_detect/src/detect/os/darwin/aarch64.rs index a23d65a23d811..35009a2b147cd 100644 --- a/library/std_detect/src/detect/os/darwin/aarch64.rs +++ b/library/std_detect/src/detect/os/darwin/aarch64.rs @@ -36,7 +36,7 @@ pub(crate) fn detect_features() -> cache::Initializer { // Armv8.0 features not using the standard identifiers let fp = _sysctlbyname(c"hw.optional.floatingpoint"); - let asimd = _sysctlbyname(c"hw.optional.AdvSIMD"); + let asimd = _sysctlbyname(c"hw.optional.AdvSIMD") || _sysctlbyname(c"hw.optional.arm.AdvSIMD"); let crc_old = _sysctlbyname(c"hw.optional.armv8_crc32"); // Armv8 and Armv9 features using the standard identifiers @@ -81,6 +81,7 @@ pub(crate) fn detect_features() -> cache::Initializer { let sme_f64f64 = _sysctlbyname(c"hw.optional.arm.FEAT_SME_F64F64"); let sme_i16i64 = _sysctlbyname(c"hw.optional.arm.FEAT_SME_I16I64"); let ssbs = _sysctlbyname(c"hw.optional.arm.FEAT_SSBS"); + let sve_b16b16 = _sysctlbyname(c"hw.optional.arm.FEAT_SVE_B16B16"); let wfxt = _sysctlbyname(c"hw.optional.arm.FEAT_WFxT"); // The following features are not exposed by `is_aarch64_feature_detected`, @@ -160,6 +161,7 @@ pub(crate) fn detect_features() -> cache::Initializer { enable_feature(Feature::sme_f64f64, sme_f64f64); enable_feature(Feature::sme_i16i64, sme_i16i64); enable_feature(Feature::ssbs, ssbs); + enable_feature(Feature::sve_b16b16, sve_b16b16); enable_feature(Feature::wfxt, wfxt); value diff --git a/library/std_detect/src/detect/os/linux/aarch64.rs b/library/std_detect/src/detect/os/linux/aarch64.rs index b733b8a9eb236..936f06859491e 100644 --- a/library/std_detect/src/detect/os/linux/aarch64.rs +++ b/library/std_detect/src/detect/os/linux/aarch64.rs @@ -258,7 +258,7 @@ impl AtHwcap { /// Initializes the cache from the feature -bits. /// /// The feature dependencies here come directly from LLVM's feature definitions: - /// https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AArch64/AArch64.td + /// fn cache(self, is_exynos9810: bool) -> cache::Initializer { let mut value = cache::Initializer::default(); { diff --git a/library/std_detect/src/detect/os/linux/auxvec/tests.rs b/library/std_detect/src/detect/os/linux/auxvec/tests.rs index 88f0d6d493376..8028106cc8b1c 100644 --- a/library/std_detect/src/detect/os/linux/auxvec/tests.rs +++ b/library/std_detect/src/detect/os/linux/auxvec/tests.rs @@ -47,7 +47,10 @@ cfg_select! { // files on disk, so we need to embed them with `include_bytes!`. #[test] fn linux_rpi3() { - let auxv = include_bytes!(concat!(env!("CARGO_MANIFEST_DIR"), "/src/detect/test_data/linux-rpi3.auxv")); + let auxv = include_bytes!(concat!( + env!("CARGO_MANIFEST_DIR"), + "/src/detect/test_data/linux-rpi3.auxv" + )); let v = auxv_from_file_bytes(auxv).unwrap(); assert_eq!(v.hwcap, 4174038); assert_eq!(v.hwcap2, 16); @@ -55,7 +58,10 @@ cfg_select! { #[test] fn linux_macos_vb() { - let auxv = include_bytes!(concat!(env!("CARGO_MANIFEST_DIR"), "/src/detect/test_data/macos-virtualbox-linux-x86-4850HQ.auxv")); + let auxv = include_bytes!(concat!( + env!("CARGO_MANIFEST_DIR"), + "/src/detect/test_data/macos-virtualbox-linux-x86-4850HQ.auxv" + )); // The file contains HWCAP but not HWCAP2. In that case, we treat HWCAP2 as zero. let v = auxv_from_file_bytes(auxv).unwrap(); assert_eq!(v.hwcap, 126614527); @@ -66,7 +72,10 @@ cfg_select! { #[cfg(target_endian = "little")] #[test] fn linux_artificial_aarch64() { - let auxv = include_bytes!(concat!(env!("CARGO_MANIFEST_DIR"), "/src/detect/test_data/linux-artificial-aarch64.auxv")); + let auxv = include_bytes!(concat!( + env!("CARGO_MANIFEST_DIR"), + "/src/detect/test_data/linux-artificial-aarch64.auxv" + )); let v = auxv_from_file_bytes(auxv).unwrap(); assert_eq!(v.hwcap, 0x0123456789abcdef); assert_eq!(v.hwcap2, 0x02468ace13579bdf); @@ -74,7 +83,10 @@ cfg_select! { #[cfg(target_endian = "little")] #[test] fn linux_no_hwcap2_aarch64() { - let auxv = include_bytes!(concat!(env!("CARGO_MANIFEST_DIR"), "/src/detect/test_data/linux-no-hwcap2-aarch64.auxv")); + let auxv = include_bytes!(concat!( + env!("CARGO_MANIFEST_DIR"), + "/src/detect/test_data/linux-no-hwcap2-aarch64.auxv" + )); let v = auxv_from_file_bytes(auxv).unwrap(); // An absent HWCAP2 is treated as zero, and does not prevent acceptance of HWCAP. assert_ne!(v.hwcap, 0); diff --git a/library/std_detect/src/detect/os/windows/aarch64.rs b/library/std_detect/src/detect/os/windows/aarch64.rs index 937f9f26eedc1..825e16bc2f864 100644 --- a/library/std_detect/src/detect/os/windows/aarch64.rs +++ b/library/std_detect/src/detect/os/windows/aarch64.rs @@ -31,8 +31,14 @@ pub(crate) fn detect_features() -> cache::Initializer { const PF_ARM_SVE_SHA3_INSTRUCTIONS_AVAILABLE: u32 = 55; const PF_ARM_SVE_SM4_INSTRUCTIONS_AVAILABLE: u32 = 56; // const PF_ARM_SVE_I8MM_INSTRUCTIONS_AVAILABLE: u32 = 57; - // const PF_ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE: u32 = 58; - // const PF_ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE: u32 = 59; + const PF_ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE: u32 = 58; + const PF_ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE: u32 = 59; + const PF_ARM_LSE2_AVAILABLE: u32 = 62; + const PF_ARM_SHA3_INSTRUCTIONS_AVAILABLE: u32 = 64; + const PF_ARM_SHA512_INSTRUCTIONS_AVAILABLE: u32 = 65; + const PF_ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE: u32 = 66; + const PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE: u32 = 67; + const PF_ARM_V86_BF16_INSTRUCTIONS_AVAILABLE: u32 = 68; unsafe extern "system" { fn IsProcessorFeaturePresent(ProcessorFeature: DWORD) -> BOOL; @@ -46,9 +52,11 @@ pub(crate) fn detect_features() -> cache::Initializer { } }; - // Some features may be supported on current CPU, - // but no way to detect it by OS API. - // Also, we require unsafe block for the extern "system" calls. + // Some features may be supported on the current CPU but have no + // detection path through the Win32 API; those report `false`. + // SAFETY: `IsProcessorFeaturePresent` is a Win32 entry point taking a + // `DWORD` by value and returning a `BOOL`. No pointer parameters, + // no out-parameters, no thread-safety constraints. unsafe { enable_feature( Feature::fp, @@ -112,6 +120,46 @@ pub(crate) fn detect_features() -> cache::Initializer { Feature::sve2_sm4, IsProcessorFeaturePresent(PF_ARM_SVE_SM4_INSTRUCTIONS_AVAILABLE) != FALSE, ); + enable_feature( + Feature::f32mm, + IsProcessorFeaturePresent(PF_ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE) != FALSE, + ); + enable_feature( + Feature::f64mm, + IsProcessorFeaturePresent(PF_ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE) != FALSE, + ); + enable_feature( + Feature::lse2, + IsProcessorFeaturePresent(PF_ARM_LSE2_AVAILABLE) != FALSE, + ); + enable_feature( + Feature::fp16, + IsProcessorFeaturePresent(PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE) != FALSE, + ); + enable_feature( + Feature::i8mm, + IsProcessorFeaturePresent(PF_ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE) != FALSE, + ); + enable_feature( + Feature::bf16, + IsProcessorFeaturePresent(PF_ARM_V86_BF16_INSTRUCTIONS_AVAILABLE) != FALSE, + ); + // stdarch `sha3` is FEAT_SHA3 + FEAT_SHA512 together; Windows + // exposes them as two separate flags. + enable_feature( + Feature::sha3, + IsProcessorFeaturePresent(PF_ARM_SHA3_INSTRUCTIONS_AVAILABLE) != FALSE + && IsProcessorFeaturePresent(PF_ARM_SHA512_INSTRUCTIONS_AVAILABLE) != FALSE, + ); + // No PF_ARM_RDM_* constant exists. Derive FEAT_RDM from FEAT_DotProd: + // DotProd is an optional v8.2-A feature only present on cores that + // implement at least v8.1-A; v8.1-A with AdvSIMD mandates FEAT_RDM + // (Arm ARM K.a §D17.2.91), and AdvSIMD is universal on Windows-on-ARM. + // Same inference shipped in .NET 10 (dotnet/runtime PR 109493). + enable_feature( + Feature::rdm, + IsProcessorFeaturePresent(PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE) != FALSE, + ); // PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE means aes, sha1, sha2 and // pmull support let crypto = diff --git a/library/std_detect/src/detect/os/x86.rs b/library/std_detect/src/detect/os/x86.rs index f2205ba07dd41..4e739fb38d56e 100644 --- a/library/std_detect/src/detect/os/x86.rs +++ b/library/std_detect/src/detect/os/x86.rs @@ -127,6 +127,8 @@ pub(crate) fn detect_features() -> cache::Initializer { enable(extended_features_ebx, 9, Feature::ermsb); + enable(extended_features_ebx, 23, Feature::clflushopt); + enable(extended_features_eax_leaf_1, 31, Feature::movrs); // Detect if CPUID.19h available @@ -202,6 +204,27 @@ pub(crate) fn detect_features() -> cache::Initializer { // Test `XCR0.APX[19]` with the mask `0b1000_0000_0000_0000_0000 == 0x80000` let os_apx_support = xcr0 & 0x80000 == 0x80000; + if os_amx_support { + enable(extended_features_edx, 24, Feature::amx_tile); + enable(extended_features_edx, 25, Feature::amx_int8); + enable(extended_features_edx, 22, Feature::amx_bf16); + enable(extended_features_eax_leaf_1, 21, Feature::amx_fp16); + enable(extended_features_edx_leaf_1, 8, Feature::amx_complex); + + if max_basic_leaf >= 0x1e { + let CpuidResult { eax: amx_feature_flags_eax, .. } = + __cpuid_count(0x1e_u32, 1); + + enable(amx_feature_flags_eax, 4, Feature::amx_fp8); + enable(amx_feature_flags_eax, 7, Feature::amx_avx512); + enable(amx_feature_flags_eax, 8, Feature::amx_movrs); + } + } + + if os_apx_support { + enable(extended_features_edx_leaf_1, 21, Feature::apxf); + } + // Only if the OS and the CPU support saving/restoring the AVX // registers we enable `xsave` support: if os_avx_support { @@ -236,9 +259,10 @@ pub(crate) fn detect_features() -> cache::Initializer { enable(extended_features_ebx, 5, Feature::avx2); // "Short" versions of AVX512 instructions - enable(extended_features_eax_leaf_1, 4, Feature::avxvnni); - enable(extended_features_eax_leaf_1, 23, Feature::avxifma); - enable(extended_features_edx_leaf_1, 4, Feature::avxvnniint8); + let avxvnni = enable(extended_features_eax_leaf_1, 4, Feature::avxvnni); + let avxvnniint8 = enable(extended_features_eax_leaf_1, 23, Feature::avxifma); + let avxvnniint16 = + enable(extended_features_edx_leaf_1, 4, Feature::avxvnniint8); enable(extended_features_edx_leaf_1, 5, Feature::avxneconvert); enable(extended_features_edx_leaf_1, 10, Feature::avxvnniint16); @@ -269,37 +293,18 @@ pub(crate) fn detect_features() -> cache::Initializer { enable(extended_features_edx, 8, Feature::avx512vp2intersect); enable(extended_features_edx, 23, Feature::avx512fp16); enable(extended_features_eax_leaf_1, 5, Feature::avx512bf16); - } - } - - if os_amx_support { - enable(extended_features_edx, 24, Feature::amx_tile); - enable(extended_features_edx, 25, Feature::amx_int8); - enable(extended_features_edx, 22, Feature::amx_bf16); - enable(extended_features_eax_leaf_1, 21, Feature::amx_fp16); - enable(extended_features_edx_leaf_1, 8, Feature::amx_complex); - - if max_basic_leaf >= 0x1e { - let CpuidResult { eax: amx_feature_flags_eax, .. } = - __cpuid_count(0x1e_u32, 1); - - enable(amx_feature_flags_eax, 4, Feature::amx_fp8); - enable(amx_feature_flags_eax, 6, Feature::amx_tf32); - enable(amx_feature_flags_eax, 7, Feature::amx_avx512); - enable(amx_feature_flags_eax, 8, Feature::amx_movrs); - } - } - - if os_apx_support { - enable(extended_features_edx_leaf_1, 21, Feature::apxf); - } - let avx10_1 = enable(extended_features_edx_leaf_1, 19, Feature::avx10_1); - if avx10_1 { - let CpuidResult { ebx, .. } = __cpuid(0x24); - let avx10_version = ebx & 0xff; - if avx10_version >= 2 { - value.set(Feature::avx10_2 as u32); + let avx10_1 = enable(extended_features_edx_leaf_1, 19, Feature::avx10_1); + if avx10_1 { + let CpuidResult { ebx, .. } = __cpuid(0x24); + let avx10_version = ebx & 0xff; + + // AVX10.2 supports masked versions of dot-product instructions available in avxvnni etc, + // so it doesn't make sense to have it without the unmasked versions + if avx10_version >= 2 && avxvnni && avxvnniint8 && avxvnniint16 { + value.set(Feature::avx10_2 as u32); + } + } } } } diff --git a/library/std_detect/src/lib.rs b/library/std_detect/src/lib.rs index 5e1d21bbfd17d..f9d79df670a0f 100644 --- a/library/std_detect/src/lib.rs +++ b/library/std_detect/src/lib.rs @@ -15,7 +15,7 @@ //! * `s390x`: [`is_s390x_feature_detected`] #![unstable(feature = "stdarch_internal", issue = "none")] -#![feature(staged_api, cfg_select, doc_cfg, allow_internal_unstable)] +#![feature(staged_api, doc_cfg, allow_internal_unstable)] #![deny(rust_2018_idioms)] #![allow(clippy::shadow_reuse)] #![cfg_attr(test, allow(unused_imports))] diff --git a/library/std_detect/tests/cpu-detection.rs b/library/std_detect/tests/cpu-detection.rs index 196abfdb7c4dd..f0b276072108d 100644 --- a/library/std_detect/tests/cpu-detection.rs +++ b/library/std_detect/tests/cpu-detection.rs @@ -1,4 +1,4 @@ -#![allow(internal_features)] +#![allow(internal_features, unused_features)] #![feature(stdarch_internal)] #![cfg_attr(target_arch = "arm", feature(stdarch_arm_feature_detection))] #![cfg_attr( @@ -150,14 +150,22 @@ fn aarch64_linux() { fn aarch64_windows() { println!("asimd: {:?}", is_aarch64_feature_detected!("asimd")); println!("fp: {:?}", is_aarch64_feature_detected!("fp")); + println!("fp16: {:?}", is_aarch64_feature_detected!("fp16")); println!("crc: {:?}", is_aarch64_feature_detected!("crc")); println!("lse: {:?}", is_aarch64_feature_detected!("lse")); + println!("lse2: {:?}", is_aarch64_feature_detected!("lse2")); + println!("rdm: {:?}", is_aarch64_feature_detected!("rdm")); println!("dotprod: {:?}", is_aarch64_feature_detected!("dotprod")); + println!("i8mm: {:?}", is_aarch64_feature_detected!("i8mm")); + println!("bf16: {:?}", is_aarch64_feature_detected!("bf16")); println!("jsconv: {:?}", is_aarch64_feature_detected!("jsconv")); println!("rcpc: {:?}", is_aarch64_feature_detected!("rcpc")); println!("aes: {:?}", is_aarch64_feature_detected!("aes")); println!("pmull: {:?}", is_aarch64_feature_detected!("pmull")); println!("sha2: {:?}", is_aarch64_feature_detected!("sha2")); + println!("sha3: {:?}", is_aarch64_feature_detected!("sha3")); + println!("f32mm: {:?}", is_aarch64_feature_detected!("f32mm")); + println!("f64mm: {:?}", is_aarch64_feature_detected!("f64mm")); } #[test] diff --git a/library/std_detect/tests/macro_trailing_commas.rs b/library/std_detect/tests/macro_trailing_commas.rs index 29bd3f1162a42..a60b34acb872f 100644 --- a/library/std_detect/tests/macro_trailing_commas.rs +++ b/library/std_detect/tests/macro_trailing_commas.rs @@ -1,4 +1,4 @@ -#![allow(internal_features)] +#![allow(internal_features, unused_features)] #![cfg_attr( any( target_arch = "arm", diff --git a/library/std_detect/tests/x86-specific.rs b/library/std_detect/tests/x86-specific.rs index 90ca32208e78d..117182558f46a 100644 --- a/library/std_detect/tests/x86-specific.rs +++ b/library/std_detect/tests/x86-specific.rs @@ -1,6 +1,12 @@ #![cfg(any(target_arch = "x86", target_arch = "x86_64"))] #![allow(internal_features)] -#![feature(stdarch_internal, x86_amx_intrinsics, xop_target_feature, movrs_target_feature)] +#![feature( + stdarch_internal, + x86_amx_intrinsics, + xop_target_feature, + movrs_target_feature, + clflushopt_target_feature +)] #[macro_use] extern crate std_detect; @@ -58,6 +64,7 @@ fn dump() { println!("xsaves: {:?}", is_x86_feature_detected!("xsaves")); println!("xsavec: {:?}", is_x86_feature_detected!("xsavec")); println!("cmpxchg16b: {:?}", is_x86_feature_detected!("cmpxchg16b")); + println!("clflushopt: {:?}", is_x86_feature_detected!("clflushopt")); println!("adx: {:?}", is_x86_feature_detected!("adx")); println!("rtm: {:?}", is_x86_feature_detected!("rtm")); println!("movbe: {:?}", is_x86_feature_detected!("movbe")); @@ -76,7 +83,6 @@ fn dump() { println!("widekl: {:?}", is_x86_feature_detected!("widekl")); println!("movrs: {:?}", is_x86_feature_detected!("movrs")); println!("amx-fp8: {:?}", is_x86_feature_detected!("amx-fp8")); - println!("amx-tf32: {:?}", is_x86_feature_detected!("amx-tf32")); println!("amx-avx512: {:?}", is_x86_feature_detected!("amx-avx512")); println!("amx-movrs: {:?}", is_x86_feature_detected!("amx-movrs")); } diff --git a/library/stdarch/.github/workflows/main.yml b/library/stdarch/.github/workflows/main.yml index 6cf0e9f02fe54..5c2e2ae4a8e21 100644 --- a/library/stdarch/.github/workflows/main.yml +++ b/library/stdarch/.github/workflows/main.yml @@ -8,7 +8,7 @@ jobs: name: Check Style runs-on: ubuntu-latest steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v6 - name: Install Rust run: rustup update nightly --no-self-update && rustup default nightly - run: ci/style.sh @@ -18,7 +18,7 @@ jobs: needs: [style] runs-on: ubuntu-latest steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v6 - name: Install Rust run: rustup update nightly --no-self-update && rustup default nightly - run: ci/dox.sh @@ -30,7 +30,7 @@ jobs: needs: [style] runs-on: ubuntu-latest steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v6 - name: Install Rust run: rustup update nightly --no-self-update && rustup default nightly - run: cargo test --manifest-path crates/stdarch-verify/Cargo.toml @@ -96,14 +96,17 @@ jobs: os: ubuntu-latest - tuple: loongarch64-unknown-linux-gnu os: ubuntu-latest + # hexagon doesn't build at the moment due to a libc issue. + # - tuple: hexagon-unknown-linux-musl + # os: ubuntu-latest - tuple: wasm32-wasip1 os: ubuntu-latest # macOS targets - tuple: x86_64-apple-darwin - os: macos-15-large + os: macos-15-intel - tuple: x86_64-apple-ios-macabi - os: macos-15-large + os: macos-15-intel - tuple: aarch64-apple-darwin os: macos-15 - tuple: aarch64-apple-ios-macabi @@ -207,9 +210,15 @@ jobs: tuple: amdgcn-amd-amdhsa os: ubuntu-latest norun: true + # hexagon doesn't build at the moment due to a libc issue. + # - target: + # tuple: hexagon-unknown-linux-musl + # os: ubuntu-latest + # norun: true + # build_std: true steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v6 - name: Install Rust run: | rustup update nightly --no-self-update @@ -263,22 +272,30 @@ jobs: intrinsic-test: needs: [style] name: Intrinsic Test - runs-on: ubuntu-latest + runs-on: ubuntu-latest strategy: matrix: target: - aarch64-unknown-linux-gnu - aarch64_be-unknown-linux-gnu - armv7-unknown-linux-gnueabihf - - arm-unknown-linux-gnueabihf - x86_64-unknown-linux-gnu profile: [dev, release] + cc: [clang, gcc] include: - target: aarch64_be-unknown-linux-gnu build_std: true - + - target: x86_64-unknown-linux-gnu + cc: icx + profile: dev + - target: x86_64-unknown-linux-gnu + cc: icx + profile: release + exclude: + - target: armv7-unknown-linux-gnueabihf + cc: gcc steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v6 - name: Install Rust run: | rustup update nightly --no-self-update @@ -289,10 +306,11 @@ jobs: rustup component add rust-src echo "CARGO_UNSTABLE_BUILD_STD=std" >> $GITHUB_ENV if: ${{ matrix.build_std }} + - run: rustup component add rustfmt # Configure some env vars based on matrix configuration - run: echo "PROFILE=${{ matrix.profile }}" >> $GITHUB_ENV - - run: ./ci/intrinsic-test-docker.sh ${{ matrix.target }} + - run: ./ci/intrinsic-test-docker.sh ${{ matrix.target }} ${{ matrix.cc }} if: ${{ !startsWith(matrix.target, 'thumb') }} env: TARGET: ${{ matrix.target }} @@ -300,30 +318,58 @@ jobs: # Check that the generated files agree with the checked-in versions. check-stdarch-gen: needs: [style] - name: Check stdarch-gen-{arm, loongarch} output + name: Check stdarch-gen-{arm, loongarch, hexagon} output runs-on: ubuntu-latest + env: + STDARCH_GEN_MODE: check steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v6 - name: Install Rust run: rustup update nightly && rustup default nightly && rustup component add rustfmt - name: Check arm spec run: | cargo run --bin=stdarch-gen-arm --release -- crates/stdarch-gen-arm/spec + - name: Check loongarch lsx + run: | + cargo run -p stdarch-gen-loongarch --release -- lsx git diff --exit-code - - name: Check lsx.spec + - name: Check loongarch lasx run: | - cargo run --bin=stdarch-gen-loongarch --release -- crates/stdarch-gen-loongarch/lsx.spec + cargo run -p stdarch-gen-loongarch --release -- lasx git diff --exit-code - - name: Check lasx.spec + - name: Check hexagon run: | - cargo run --bin=stdarch-gen-loongarch --release -- crates/stdarch-gen-loongarch/lasx.spec + cargo run -p stdarch-gen-hexagon --release git diff --exit-code + + # Run some tests with Miri. Most stdarch functions use platform-specific intrinsics + # that Miri does not support. Also Miri is reltively slow. + # + # Below we run some tests where Miri might catch UB, for instance on intrinsics that read from + # or write to pointers. + miri: + needs: [style] + name: Run some tests with miri + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v6 + - name: Install Rust + run: rustup update nightly && rustup default nightly && rustup component add miri + - name: Run miri tests + env: + TARGET: "aarch64-unknown-linux-gnu" + RUSTFLAGS: "-Ctarget-cpu=neoverse-v3" + run: | + # read filters and join them with a space. + FILTERS=$(cat aarch64-miri-tests.txt | tr '\n' ' ') + cargo miri test -p core_arch --target aarch64-unknown-linux-gnu -- $FILTERS conclusion: needs: - docs - verify - test + - miri - intrinsic-test - check-stdarch-gen runs-on: ubuntu-latest diff --git a/library/stdarch/.github/workflows/rustc-pull.yml b/library/stdarch/.github/workflows/rustc-pull.yml index ee0c498878f42..d2feb1add6344 100644 --- a/library/stdarch/.github/workflows/rustc-pull.yml +++ b/library/stdarch/.github/workflows/rustc-pull.yml @@ -13,6 +13,7 @@ jobs: uses: rust-lang/josh-sync/.github/workflows/rustc-pull.yml@main with: github-app-id: ${{ vars.APP_CLIENT_ID }} + pr-author: "workflows-stdarch[bot]" # https://rust-lang.zulipchat.com/#narrow/channel/208962-t-libs.2Fstdarch/topic/Subtree.20sync.20automation/with/528461782 zulip-stream-id: 208962 zulip-bot-email: "stdarch-ci-bot@rust-lang.zulipchat.com" diff --git a/library/stdarch/Cargo.lock b/library/stdarch/Cargo.lock index 70f09adf2c857..9923b630cd5bb 100644 --- a/library/stdarch/Cargo.lock +++ b/library/stdarch/Cargo.lock @@ -4,18 +4,18 @@ version = 4 [[package]] name = "aho-corasick" -version = "1.1.3" +version = "1.1.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "8e60d3430d3a69478ad0993f19238d2df97c507009a52b3c10addcd7f6bcb916" +checksum = "ddd31a130427c27518df266943a5308ed92d4b226cc639f5a8f1002816174301" dependencies = [ "memchr", ] [[package]] name = "anstream" -version = "0.6.20" +version = "1.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3ae563653d1938f79b1ab1b5e668c87c76a9930414574a6583a7b7e11a8e6192" +checksum = "824a212faf96e9acacdbd09febd34438f8f711fb84e09a8916013cd7815ca28d" dependencies = [ "anstyle", "anstyle-parse", @@ -28,44 +28,44 @@ dependencies = [ [[package]] name = "anstyle" -version = "1.0.11" +version = "1.0.14" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "862ed96ca487e809f1c8e5a8447f6ee2cf102f846893800b20cebdf541fc6bbd" +checksum = "940b3a0ca603d1eade50a4846a2afffd5ef57a9feac2c0e2ec2e14f9ead76000" [[package]] name = "anstyle-parse" -version = "0.2.7" +version = "1.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "4e7644824f0aa2c7b9384579234ef10eb7efb6a0deb83f9630a49594dd9c15c2" +checksum = "52ce7f38b242319f7cabaa6813055467063ecdc9d355bbb4ce0c68908cd8130e" dependencies = [ "utf8parse", ] [[package]] name = "anstyle-query" -version = "1.1.4" +version = "1.1.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9e231f6134f61b71076a3eab506c379d4f36122f2af15a9ff04415ea4c3339e2" +checksum = "40c48f72fd53cd289104fc64099abca73db4166ad86ea0b4341abe65af83dadc" dependencies = [ - "windows-sys 0.60.2", + "windows-sys", ] [[package]] name = "anstyle-wincon" -version = "3.0.10" +version = "3.0.11" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3e0633414522a32ffaac8ac6cc8f748e090c5717661fddeea04219e2344f5f2a" +checksum = "291e6a250ff86cd4a820112fb8898808a366d8f9f58ce16d1f538353ad55747d" dependencies = [ "anstyle", "once_cell_polyfill", - "windows-sys 0.60.2", + "windows-sys", ] [[package]] name = "anyhow" -version = "1.0.99" +version = "1.0.102" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b0674a1ddeecb70197781e945de4b3b8ffb61fa939a5597bcf48503737663100" +checksum = "7f202df86484c868dbad7eaa557ef785d5c66295e41b460ef922eca0723b842c" [[package]] name = "assert-instr-macro" @@ -84,15 +84,15 @@ checksum = "c08606f8c3cbf4ce6ec8e28fb0014a2c086708fe954eaa885384a6165172e7e8" [[package]] name = "bitflags" -version = "2.9.4" +version = "2.11.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2261d10cca569e4643e526d8dc2e62e433cc8aba21ab764233731f8d369bf394" +checksum = "843867be96c8daad0d758b57df9392b6d8d271134fce549de6ce169ff98a92af" [[package]] name = "cc" -version = "1.2.36" +version = "1.2.59" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5252b3d2648e5eedbc1a6f501e3c795e07025c1e93bbf8bbdd6eef7f447a6d54" +checksum = "b7a4d3ec6524d28a329fc53654bbadc9bdd7b0431f5d65f1a56ffb28a1ee5283" dependencies = [ "find-msvc-tools", "shlex", @@ -100,15 +100,15 @@ dependencies = [ [[package]] name = "cfg-if" -version = "1.0.3" +version = "1.0.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2fd1289c04a9ea8cb22300a459a72a385d7c73d3259e2ed7dcb2af674838cfa9" +checksum = "9330f8b2ff13f34540b44e946ef35111825727b38d33286ef986142615121801" [[package]] name = "clap" -version = "4.5.47" +version = "4.6.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7eac00902d9d136acd712710d71823fb8ac8004ca445a89e73a41d45aa712931" +checksum = "b193af5b67834b676abd72466a96c1024e6a6ad978a1f484bd90b85c94041351" dependencies = [ "clap_builder", "clap_derive", @@ -116,9 +116,9 @@ dependencies = [ [[package]] name = "clap_builder" -version = "4.5.47" +version = "4.6.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2ad9bbf750e73b5884fb8a211a9424a1906c1e156724260fdae972f31d70e1d6" +checksum = "714a53001bf66416adb0e2ef5ac857140e7dc3a0c48fb28b2f10762fc4b5069f" dependencies = [ "anstream", "anstyle", @@ -128,9 +128,9 @@ dependencies = [ [[package]] name = "clap_derive" -version = "4.5.47" +version = "4.6.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "bbfd7eae0b0f1a6e63d4b13c9c478de77c2eb546fba158ad50b4203dc24b9f9c" +checksum = "1110bd8a634a1ab8cb04345d8d878267d57c3cf1b38d91b71af6686408bbca6a" dependencies = [ "heck", "proc-macro2", @@ -140,15 +140,15 @@ dependencies = [ [[package]] name = "clap_lex" -version = "0.7.5" +version = "1.1.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b94f61472cee1439c0b966b47e3aca9ae07e45d070759512cd390ea2bebc6675" +checksum = "c8d4a3bb8b1e0c1050499d1815f5ab16d04f0959b233085fb31653fbfc9d98f9" [[package]] name = "colorchoice" -version = "1.0.4" +version = "1.0.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b05b61dc5112cbb17e4b6cd61790d9845d13888356391624cbe7e41efeac1e75" +checksum = "1d07550c9036bf2ae0c684c4297d503f838287c83c53686d05370d0e139ae570" [[package]] name = "core_arch" @@ -185,9 +185,9 @@ checksum = "d0a5c400df2834b80a4c3327b3aad3a4c4cd4de0629063962b03235697506a28" [[package]] name = "darling" -version = "0.20.11" +version = "0.23.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "fc7f46116c46ff9ab3eb1597a45688b6715c6e628b5c133e288e709a29bcb4ee" +checksum = "25ae13da2f202d56bd7f91c25fba009e7717a1e4a1cc98a76d844b65ae912e9d" dependencies = [ "darling_core", "darling_macro", @@ -195,11 +195,10 @@ dependencies = [ [[package]] name = "darling_core" -version = "0.20.11" +version = "0.23.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "0d00b9596d185e565c2207a0b01f8bd1a135483d02d9b7b0a54b11da8d53412e" +checksum = "9865a50f7c335f53564bb694ef660825eb8610e0a53d3e11bf1b0d3df31e03b0" dependencies = [ - "fnv", "ident_case", "proc-macro2", "quote", @@ -209,9 +208,9 @@ dependencies = [ [[package]] name = "darling_macro" -version = "0.20.11" +version = "0.23.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "fc34b93ccb385b40dc71c6fceac4b2ad23662c7eeb248cf10d529b7e055b6ead" +checksum = "ac3984ec7bd6cfa798e62b4a642426a5be0e68f9401cfc2a01e3fa9ea2fcdb8d" dependencies = [ "darling_core", "quote", @@ -231,10 +230,10 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "48c757948c5ede0e46177b7add2e67155f70e33c07fea8284df6576da70b3719" [[package]] -name = "env_logger" -version = "0.8.4" +name = "env_filter" +version = "1.0.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a19187fea3ac7e84da7dacf48de0c45d63c6a76f9490dae389aead16c243fce3" +checksum = "32e90c2accc4b07a8456ea0debdc2e7587bdd890680d71173a15d4ae604f6eef" dependencies = [ "log", "regex", @@ -253,33 +252,74 @@ dependencies = [ "termcolor", ] +[[package]] +name = "env_logger" +version = "0.11.10" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0621c04f2196ac3f488dd583365b9c09be011a4ab8b9f37248ffcc8f6198b56a" +dependencies = [ + "env_filter", + "log", +] + [[package]] name = "equivalent" version = "1.0.2" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "877a4ace8713b0bcf2a4e7eec82529c029f1d0619886d18145fea96c3ffe5c0f" +[[package]] +name = "errno" +version = "0.3.14" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "39cab71617ae0d63f51a36d69f866391735b51691dbda63cf6f96d042b63efeb" +dependencies = [ + "libc", + "windows-sys", +] + +[[package]] +name = "fastrand" +version = "2.4.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9f1f227452a390804cdb637b74a86990f2a7d7ba4b7d5693aac9b4dd6defd8d6" + [[package]] name = "find-msvc-tools" -version = "0.1.1" +version = "0.1.9" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7fd99930f64d146689264c637b5af2f0233a933bef0d8570e2526bf9e083192d" +checksum = "5baebc0774151f905a1a2cc41989300b1e6fbb29aff0ceffa1064fdd3088d582" [[package]] -name = "fnv" -version = "1.0.7" +name = "foldhash" +version = "0.1.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3f9eec918d3f24069decb9af1554cad7c880e2da24a9afd88aca000531ab82c1" +checksum = "d9c4f5dac5e15c24eb999c26181a6ca40b39fe946cbe4c263c7209467bc83af2" [[package]] name = "getrandom" -version = "0.2.16" +version = "0.3.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "335ff9f135e4384c8150d6f27c6daed433577f86b4750418338c01a1a2528592" +checksum = "899def5c37c4fd7b2664648c28120ecec138e4d395b459e5ca34f9cce2dd77fd" dependencies = [ "cfg-if", "libc", - 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"xml-rs", + "xml", +] + +[[package]] +name = "serde_core" +version = "1.0.228" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "41d385c7d4ca58e59fc732af25c3983b67ac852c1a25000afe1175de458b67ad" +dependencies = [ + "serde_derive", ] [[package]] name = "serde_derive" -version = "1.0.219" +version = "1.0.228" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5b0276cf7f2c73365f7157c8123c21cd9a50fbbd844757af28ca1f5925fc2a00" +checksum = "d540f220d3187173da220f885ab66608367b6574e925011a9353e4badda91d79" dependencies = [ "proc-macro2", "quote", @@ -625,32 +760,32 @@ dependencies = [ [[package]] name = "serde_json" -version = "1.0.143" +version = "1.0.149" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d401abef1d108fbd9cbaebc3e46611f4b1021f714a0597a71f41ee463f5f4a5a" +checksum = "83fc039473c5595ace860d8c4fafa220ff474b3fc6bfdb4293327f1a37e94d86" dependencies = [ "itoa", "memchr", - "ryu", "serde", + "serde_core", + "zmij", ] [[package]] name = "serde_with" -version = "3.14.0" +version = "3.18.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f2c45cd61fefa9db6f254525d46e392b852e0e61d9a1fd36e5bd183450a556d5" +checksum = "dd5414fad8e6907dbdd5bc441a50ae8d6e26151a03b1de04d89a5576de61d01f" dependencies = [ - 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"rand", + "rand 0.9.4", ] [[package]] @@ -747,9 +898,9 @@ checksum = "7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f" [[package]] name = "syn" -version = "2.0.106" +version = "2.0.117" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ede7c438028d4436d71104916910f5bb611972c5cfd7f89b8300a8186e6fada6" +checksum = "e665b8803e7b1d2a727f4023456bbbbe74da67099c585258af0ad9c5013b9b99" dependencies = [ "proc-macro2", "quote", @@ -762,6 +913,19 @@ version = "0.6.18" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "43d0e35dc7d73976a53c7e6d7d177ef804a0c0ee774ec77bcc520c2216fd7cbe" +[[package]] +name = "tempfile" +version = "3.27.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "32497e9a4c7b38532efcdebeef879707aa9f794296a4f0244f6f69e9bc8574bd" +dependencies = [ + "fastrand", + "getrandom 0.4.2", + "once_cell", + "rustix", + "windows-sys", +] + [[package]] name = "termcolor" version = "1.4.1" @@ -773,18 +937,18 @@ dependencies = [ [[package]] name = "thiserror" -version = "1.0.69" +version = "2.0.18" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b6aaf5339b578ea85b50e080feb250a3e8ae8cfcdff9a461c9ec2904bc923f52" +checksum = "4288b5bcbc7920c07a1149a35cf9590a2aa808e0bc1eafaade0b80947865fbc4" dependencies = [ "thiserror-impl", ] [[package]] name = "thiserror-impl" -version = "1.0.69" +version = "2.0.18" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "4fee6c4efc90059e10f81e6d42c60a18f76588c3d74cb83a0b242a2b6c7504c1" +checksum = "ebc4ee7f67670e9b64d05fa4253e753e016c6c95ff35b89b7941d6b856dec1d5" dependencies = [ "proc-macro2", "quote", @@ -793,9 +957,15 @@ dependencies = [ [[package]] name = "unicode-ident" -version = "1.0.18" +version = "1.0.24" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e6e4313cd5fcd3dad5cafa179702e2b244f760991f45397d14d4ebf38247da75" + +[[package]] +name = "unicode-xid" +version = "0.2.6" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5a5f39404a5da50712a4c1eecf25e90dd62b613502b7e925fd4e4d19b5c96512" +checksum = "ebc1c04c71510c7f702b52b7c350734c9ff1295c464a03335b00bb84fc54f853" [[package]] name = "utf8parse" @@ -814,10 +984,44 @@ dependencies = [ ] [[package]] -name = "wasi" -version = "0.11.1+wasi-snapshot-preview1" +name = "wasip2" +version = "1.0.2+wasi-0.2.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9517f9239f02c069db75e65f174b3da828fe5f5b945c4dd26bd25d89c03ebcf5" +dependencies = [ + "wit-bindgen", +] + +[[package]] +name = "wasip3" +version = "0.4.0+wasi-0.3.0-rc-2026-01-06" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ccf3ec651a847eb01de73ccad15eb7d99f80485de043efb2f370cd654f4ea44b" +checksum = "5428f8bf88ea5ddc08faddef2ac4a67e390b88186c703ce6dbd955e1c145aca5" +dependencies = [ + "wit-bindgen", +] + +[[package]] +name = "wasm-encoder" +version = "0.244.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "990065f2fe63003fe337b932cfb5e3b80e0b4d0f5ff650e6985b1048f62c8319" +dependencies = [ + "leb128fmt", + "wasmparser 0.244.0", +] + +[[package]] +name = "wasm-metadata" +version = "0.244.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bb0e353e6a2fbdc176932bbaab493762eb1255a7900fe0fea1a2f96c296cc909" +dependencies = [ + "anyhow", + "indexmap 2.13.1", + "wasm-encoder", + "wasmparser 0.244.0", +] [[package]] name = "wasmparser" @@ -826,7 +1030,19 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "161296c618fa2d63f6ed5fffd1112937e803cb9ec71b32b01a76321555660917" dependencies = [ "bitflags", - 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"windows-targets 0.52.6", + "windows-link", ] [[package]] -name = "windows-sys" -version = "0.60.2" +name = "wit-bindgen" +version = "0.51.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f2f500e4d28234f72040990ec9d39e3a6b950f9f22d3dba18416c35882612bcb" +checksum = "d7249219f66ced02969388cf2bb044a09756a083d0fab1e566056b04d9fbcaa5" dependencies = [ - "windows-targets 0.53.3", + "wit-bindgen-rust-macro", ] [[package]] -name = "windows-targets" -version = "0.52.6" +name = "wit-bindgen-core" +version = "0.51.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9b724f72796e036ab90c1021d4780d4d3d648aca59e491e6b98e725b84e99973" +checksum = "ea61de684c3ea68cb082b7a88508a8b27fcc8b797d738bfc99a82facf1d752dc" dependencies = [ - "windows_aarch64_gnullvm 0.52.6", - "windows_aarch64_msvc 0.52.6", - "windows_i686_gnu 0.52.6", - "windows_i686_gnullvm 0.52.6", - "windows_i686_msvc 0.52.6", - "windows_x86_64_gnu 0.52.6", - "windows_x86_64_gnullvm 0.52.6", - "windows_x86_64_msvc 0.52.6", + "anyhow", + "heck", + "wit-parser", ] [[package]] -name = "windows-targets" -version = "0.53.3" +name = "wit-bindgen-rust" +version = "0.51.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d5fe6031c4041849d7c496a8ded650796e7b6ecc19df1a431c1a363342e5dc91" +checksum = "b7c566e0f4b284dd6561c786d9cb0142da491f46a9fbed79ea69cdad5db17f21" dependencies = [ - "windows-link", - "windows_aarch64_gnullvm 0.53.0", - "windows_aarch64_msvc 0.53.0", - "windows_i686_gnu 0.53.0", - "windows_i686_gnullvm 0.53.0", - "windows_i686_msvc 0.53.0", - "windows_x86_64_gnu 0.53.0", - "windows_x86_64_gnullvm 0.53.0", - "windows_x86_64_msvc 0.53.0", + "anyhow", + "heck", + "indexmap 2.13.1", + "prettyplease", + "syn", + "wasm-metadata", + "wit-bindgen-core", + "wit-component", ] [[package]] -name = "windows_aarch64_gnullvm" -version = "0.52.6" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "32a4622180e7a0ec044bb555404c800bc9fd9ec262ec147edd5989ccd0c02cd3" - -[[package]] -name = "windows_aarch64_gnullvm" -version = "0.53.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "86b8d5f90ddd19cb4a147a5fa63ca848db3df085e25fee3cc10b39b6eebae764" - -[[package]] -name = "windows_aarch64_msvc" -version = "0.52.6" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "09ec2a7bb152e2252b53fa7803150007879548bc709c039df7627cabbd05d469" - -[[package]] -name = "windows_aarch64_msvc" -version = "0.53.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "c7651a1f62a11b8cbd5e0d42526e55f2c99886c77e007179efff86c2b137e66c" - -[[package]] -name = "windows_i686_gnu" -version = "0.52.6" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "8e9b5ad5ab802e97eb8e295ac6720e509ee4c243f69d781394014ebfe8bbfa0b" - -[[package]] -name = "windows_i686_gnu" -version = "0.53.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "c1dc67659d35f387f5f6c479dc4e28f1d4bb90ddd1a5d3da2e5d97b42d6272c3" - -[[package]] -name = "windows_i686_gnullvm" -version = "0.52.6" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "0eee52d38c090b3caa76c563b86c3a4bd71ef1a819287c19d586d7334ae8ed66" - -[[package]] -name = "windows_i686_gnullvm" -version = "0.53.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9ce6ccbdedbf6d6354471319e781c0dfef054c81fbc7cf83f338a4296c0cae11" - -[[package]] -name = "windows_i686_msvc" -version = "0.52.6" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "240948bc05c5e7c6dabba28bf89d89ffce3e303022809e73deaefe4f6ec56c66" - -[[package]] -name = "windows_i686_msvc" -version = "0.53.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "581fee95406bb13382d2f65cd4a908ca7b1e4c2f1917f143ba16efe98a589b5d" - -[[package]] -name = "windows_x86_64_gnu" -version = "0.52.6" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "147a5c80aabfbf0c7d901cb5895d1de30ef2907eb21fbbab29ca94c5b08b1a78" - -[[package]] -name = "windows_x86_64_gnu" -version = "0.53.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2e55b5ac9ea33f2fc1716d1742db15574fd6fc8dadc51caab1c16a3d3b4190ba" - -[[package]] -name = "windows_x86_64_gnullvm" -version = "0.52.6" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "24d5b23dc417412679681396f2b49f3de8c1473deb516bd34410872eff51ed0d" - -[[package]] -name = "windows_x86_64_gnullvm" -version = "0.53.0" +name = "wit-bindgen-rust-macro" +version = "0.51.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "0a6e035dd0599267ce1ee132e51c27dd29437f63325753051e71dd9e42406c57" +checksum = "0c0f9bfd77e6a48eccf51359e3ae77140a7f50b1e2ebfe62422d8afdaffab17a" +dependencies = [ + "anyhow", + "prettyplease", + "proc-macro2", + "quote", + "syn", + "wit-bindgen-core", + "wit-bindgen-rust", +] [[package]] -name = "windows_x86_64_msvc" -version = "0.52.6" +name = "wit-component" +version = "0.244.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "589f6da84c646204747d1270a2a5661ea66ed1cced2631d546fdfb155959f9ec" +checksum = "9d66ea20e9553b30172b5e831994e35fbde2d165325bec84fc43dbf6f4eb9cb2" +dependencies = [ + "anyhow", + "bitflags", + "indexmap 2.13.1", + "log", + "serde", + "serde_derive", + "serde_json", + "wasm-encoder", + "wasm-metadata", + "wasmparser 0.244.0", + "wit-parser", +] [[package]] -name = "windows_x86_64_msvc" -version = "0.53.0" +name = "wit-parser" +version = "0.244.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "271414315aff87387382ec3d271b52d7ae78726f5d44ac98b4f4030c91880486" +checksum = "ecc8ac4bc1dc3381b7f59c34f00b67e18f910c2c0f50015669dde7def656a736" +dependencies = [ + "anyhow", + "id-arena", + "indexmap 2.13.1", + "log", + "semver", + "serde", + "serde_derive", + "serde_json", + "unicode-xid", + "wasmparser 0.244.0", +] [[package]] -name = "xml-rs" -version = "0.8.27" +name = "xml" +version = "1.2.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "6fd8403733700263c6eb89f192880191f1b83e332f7a20371ddcf421c4a337c7" +checksum = "b8aa498d22c9bbaf482329839bc5620c46be275a19a812e9a22a2b07529a642a" [[package]] name = "yaml-rust" @@ -1020,20 +1186,26 @@ dependencies = [ [[package]] name = "zerocopy" -version = "0.8.27" +version = "0.8.48" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "0894878a5fa3edfd6da3f88c4805f4c8558e2b996227a3d864f47fe11e38282c" +checksum = "eed437bf9d6692032087e337407a86f04cd8d6a16a37199ed57949d415bd68e9" dependencies = [ "zerocopy-derive", ] [[package]] name = "zerocopy-derive" -version = "0.8.27" +version = "0.8.48" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "88d2b8d9c68ad2b9e4340d7832716a4d21a22a1154777ad56ea55c51a9cf3831" +checksum = "70e3cd084b1788766f53af483dd21f93881ff30d7320490ec3ef7526d203bad4" dependencies = [ "proc-macro2", "quote", "syn", ] + +[[package]] +name = "zmij" +version = "1.0.21" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b8848ee67ecc8aedbaf3e4122217aff892639231befc6a1b58d29fff4c2cabaa" diff --git a/library/stdarch/Cargo.toml b/library/stdarch/Cargo.toml index 5979096439118..e3963a69879a1 100644 --- a/library/stdarch/Cargo.toml +++ b/library/stdarch/Cargo.toml @@ -1,5 +1,5 @@ [workspace] -resolver = "1" +resolver = "3" members = [ "crates/*", "examples", diff --git a/library/stdarch/aarch64-miri-tests.txt b/library/stdarch/aarch64-miri-tests.txt new file mode 100644 index 0000000000000..2c0dbb8297a1f --- /dev/null +++ b/library/stdarch/aarch64-miri-tests.txt @@ -0,0 +1,4 @@ +test_vld3 +test_vld4 +neon::load_tests +neon::store_tests diff --git a/library/stdarch/ci/docker/aarch64-unknown-linux-gnu/Dockerfile b/library/stdarch/ci/docker/aarch64-unknown-linux-gnu/Dockerfile index 2768c521ebccc..0ae4172f9dd37 100644 --- a/library/stdarch/ci/docker/aarch64-unknown-linux-gnu/Dockerfile +++ b/library/stdarch/ci/docker/aarch64-unknown-linux-gnu/Dockerfile @@ -1,18 +1,23 @@ FROM ubuntu:25.10 RUN apt-get update && apt-get install -y --no-install-recommends \ gcc \ - g++ \ ca-certificates \ libc6-dev \ gcc-aarch64-linux-gnu \ - g++-aarch64-linux-gnu \ libc6-dev-arm64-cross \ qemu-user \ make \ file \ - clang \ - lld + xz-utils \ + wget + +RUN wget https://ci-mirrors.rust-lang.org/llvm/llvm-22.1.4-x86_64.tar.gz -O llvm.tar.xz +RUN mkdir llvm +RUN tar -xvf llvm.tar.xz --strip-components=1 -C llvm + +ENV CLANG_PATH="/llvm/bin/clang" +ENV GCC_PATH=aarch64-linux-gnu-gcc ENV CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_LINKER=aarch64-linux-gnu-gcc \ - CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_RUNNER="qemu-aarch64 -cpu max -L /usr/aarch64-linux-gnu" \ + CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_RUNNER="qemu-aarch64 -cpu max,sve512=on -L /usr/aarch64-linux-gnu" \ OBJDUMP=aarch64-linux-gnu-objdump diff --git a/library/stdarch/ci/docker/aarch64_be-unknown-linux-gnu/Dockerfile b/library/stdarch/ci/docker/aarch64_be-unknown-linux-gnu/Dockerfile index f85c6a2592e99..0b7a59cc08d83 100644 --- a/library/stdarch/ci/docker/aarch64_be-unknown-linux-gnu/Dockerfile +++ b/library/stdarch/ci/docker/aarch64_be-unknown-linux-gnu/Dockerfile @@ -2,17 +2,15 @@ FROM ubuntu:25.10 RUN apt-get update && apt-get install -y --no-install-recommends \ gcc \ - g++ \ ca-certificates \ libc6-dev \ libc6-dev-arm64-cross \ qemu-user \ make \ file \ - clang \ curl \ xz-utils \ - lld + wget ENV TOOLCHAIN="arm-gnu-toolchain-14.3.rel1-x86_64-aarch64_be-none-linux-gnu" @@ -21,9 +19,16 @@ RUN curl -L "https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/bin RUN tar -xvf "${TOOLCHAIN}.tar.xz" RUN mkdir /toolchains && mv "./${TOOLCHAIN}" /toolchains +RUN wget https://ci-mirrors.rust-lang.org/llvm/llvm-22.1.4-x86_64.tar.gz -O llvm.tar.xz +RUN mkdir llvm +RUN tar -xvf llvm.tar.xz --strip-components=1 -C llvm + ENV AARCH64_BE_TOOLCHAIN="/toolchains/${TOOLCHAIN}" ENV AARCH64_BE_LIBC="${AARCH64_BE_TOOLCHAIN}/aarch64_be-none-linux-gnu/libc" +ENV CLANG_PATH="/llvm/bin/clang" +ENV GCC_PATH="${AARCH64_BE_TOOLCHAIN}/bin/aarch64_be-none-linux-gnu-gcc" + ENV CARGO_TARGET_AARCH64_BE_UNKNOWN_LINUX_GNU_LINKER="${AARCH64_BE_TOOLCHAIN}/bin/aarch64_be-none-linux-gnu-gcc" ENV CARGO_TARGET_AARCH64_BE_UNKNOWN_LINUX_GNU_RUNNER="qemu-aarch64_be -cpu max -L ${AARCH64_BE_LIBC}" ENV OBJDUMP="${AARCH64_BE_TOOLCHAIN}/bin/aarch64_be-none-linux-gnu-objdump" diff --git a/library/stdarch/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile b/library/stdarch/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile index 6d4ff24828672..23e4d5a341152 100644 --- a/library/stdarch/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile +++ b/library/stdarch/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile @@ -7,7 +7,9 @@ RUN apt-get update && apt-get install -y --no-install-recommends \ libc6-dev-armhf-cross \ qemu-user \ make \ - file + file \ + clang \ + lld ENV CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABIHF_LINKER=arm-linux-gnueabihf-gcc \ CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABIHF_RUNNER="qemu-arm -cpu max -L /usr/arm-linux-gnueabihf" \ OBJDUMP=arm-linux-gnueabihf-objdump diff --git a/library/stdarch/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile b/library/stdarch/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile index 602249c0ece5a..f4240be7bb47b 100644 --- a/library/stdarch/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile +++ b/library/stdarch/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile @@ -1,17 +1,22 @@ FROM ubuntu:24.04 RUN apt-get update && apt-get install -y --no-install-recommends \ gcc \ - g++ \ ca-certificates \ libc6-dev \ gcc-arm-linux-gnueabihf \ - g++-arm-linux-gnueabihf \ libc6-dev-armhf-cross \ qemu-user \ make \ file \ - clang \ - lld + wget + +RUN wget https://ci-mirrors.rust-lang.org/llvm/llvm-22.1.4-x86_64.tar.gz -O llvm.tar.xz +RUN mkdir llvm +RUN tar -xvf llvm.tar.xz --strip-components=1 -C llvm + +ENV CLANG_PATH="/llvm/bin/clang" +ENV GCC_PATH=arm-linux-gnueabihf-gcc + ENV CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_LINKER=arm-linux-gnueabihf-gcc \ CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_RUNNER="qemu-arm -cpu max -L /usr/arm-linux-gnueabihf" \ OBJDUMP=arm-linux-gnueabihf-objdump diff --git a/library/stdarch/ci/docker/hexagon-unknown-linux-musl/Dockerfile b/library/stdarch/ci/docker/hexagon-unknown-linux-musl/Dockerfile new file mode 100644 index 0000000000000..f6c0efd94629a --- /dev/null +++ b/library/stdarch/ci/docker/hexagon-unknown-linux-musl/Dockerfile @@ -0,0 +1,46 @@ +FROM ubuntu:25.10 + +RUN apt-get update && apt-get install -y --no-install-recommends \ + gcc \ + libc6-dev \ + ca-certificates \ + curl \ + zstd \ + file \ + make \ + libc++1 \ + libglib2.0-0t64 \ + libunwind-20 \ + liburing2 \ + llvm + +# The Hexagon toolchain requires libc++ and libunwind at runtime - create symlinks from versioned files +RUN cd /usr/lib/x86_64-linux-gnu && \ + for f in libc++.so.1.0.*; do ln -sf "$f" libc++.so.1; done && \ + for f in libc++abi.so.1.0.*; do ln -sf "$f" libc++abi.so.1; done && \ + for f in libunwind.so.1.0.*; do ln -sf "$f" libunwind.so.1; done + +# Download and install the Hexagon cross toolchain from +# https://github.com/quic/toolchain_for_hexagon/releases/tag/v21.1.8 +# Includes clang cross-compiler, musl sysroot, and qemu-hexagon. +# +# The tarball contains directories with restrictive (0700) permissions. +# In rootless Podman, chmod fails on tar-extracted files within the same +# layer due to overlayfs limitations in user namespaces. Splitting into +# two RUN steps lets chmod work via overlayfs copy-up from the lower layer. +RUN curl -L -o /tmp/hexagon-toolchain.tar.zst \ + https://artifacts.codelinaro.org/artifactory/codelinaro-toolchain-for-hexagon/21.1.8/clang+llvm-21.1.8-cross-hexagon-unknown-linux-musl.tar.zst && \ + mkdir -p /opt/hexagon-toolchain && \ + cd /opt/hexagon-toolchain && \ + (unzstd -c /tmp/hexagon-toolchain.tar.zst | tar -xf - --strip-components=2 --no-same-permissions || true) && \ + rm /tmp/hexagon-toolchain.tar.zst +RUN find /opt/hexagon-toolchain -type d -exec chmod a+rx {} + 2>/dev/null; \ + find /opt/hexagon-toolchain -type f -exec chmod a+r {} + 2>/dev/null; \ + find /opt/hexagon-toolchain -type f -perm /111 -exec chmod a+rx {} + 2>/dev/null; \ + /opt/hexagon-toolchain/bin/hexagon-unknown-linux-musl-clang --version + +ENV PATH="/opt/hexagon-toolchain/bin:${PATH}" \ + CARGO_TARGET_HEXAGON_UNKNOWN_LINUX_MUSL_LINKER=hexagon-unknown-linux-musl-clang \ + CARGO_TARGET_HEXAGON_UNKNOWN_LINUX_MUSL_RUNNER="qemu-hexagon -L /opt/hexagon-toolchain/target/hexagon-unknown-linux-musl" \ + CARGO_UNSTABLE_BUILD_STD_FEATURES=llvm-libunwind \ + OBJDUMP=llvm-objdump diff --git a/library/stdarch/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile b/library/stdarch/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile index a8b352881e813..8bcd6409453c4 100644 --- a/library/stdarch/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile +++ b/library/stdarch/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile @@ -1,4 +1,4 @@ -FROM ubuntu:25.10 +FROM ubuntu:25.04 # gcc-mips64-linux-gnuabi64 not available in 25.10 RUN apt-get update && apt-get install -y --no-install-recommends \ gcc libc6-dev qemu-user ca-certificates \ diff --git a/library/stdarch/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile b/library/stdarch/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile index 147a3df614554..9aa0ce05783c5 100644 --- a/library/stdarch/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile +++ b/library/stdarch/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile @@ -1,4 +1,4 @@ -FROM ubuntu:25.10 +FROM ubuntu:25.04 # gcc-mips64el-linux-gnuabi64 not available in 25.10 RUN apt-get update && apt-get install -y --no-install-recommends \ gcc libc6-dev qemu-user ca-certificates \ diff --git a/library/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile b/library/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile index 2743896375cf3..3a566febd548f 100644 --- a/library/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile +++ b/library/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile @@ -7,14 +7,29 @@ RUN apt-get update && apt-get install -y --no-install-recommends \ ca-certificates \ wget \ xz-utils \ - clang \ - libstdc++-14-dev \ - build-essential \ - lld + gpg -RUN wget http://ci-mirrors.rust-lang.org/stdarch/sde-external-9.58.0-2025-06-16-lin.tar.xz -O sde.tar.xz +RUN wget http://ci-mirrors.rust-lang.org/sde-external-10.8.0-2026-03-15-lin.tar.xz -O sde.tar.xz RUN mkdir intel-sde RUN tar -xJf sde.tar.xz --strip-components=1 -C intel-sde + +RUN wget https://ci-mirrors.rust-lang.org/llvm/llvm-22.1.4-x86_64.tar.gz -O llvm.tar.xz +RUN mkdir llvm +RUN tar -xvf llvm.tar.xz --strip-components=1 -C llvm + +RUN wget -O- https://apt.repos.intel.com/intel-gpg-keys/GPG-PUB-KEY-INTEL-SW-PRODUCTS.PUB |\ + gpg --dearmor |\ + tee /usr/share/keyrings/oneapi-archive-keyring.gpg > /dev/null + +RUN echo "deb [signed-by=/usr/share/keyrings/oneapi-archive-keyring.gpg] https://apt.repos.intel.com/oneapi all main" |\ + tee /etc/apt/sources.list.d/oneAPI.list + +RUN apt-get update && apt-get install -y --no-install-recommends intel-oneapi-compiler-dpcpp-cpp + +ENV CLANG_PATH="/llvm/bin/clang" +ENV GCC_PATH="gcc" +ENV ICX_PATH="/opt/intel/oneapi/compiler/2026.1/bin/icx" + ENV CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER="/intel-sde/sde64 \ -cpuid-in /checkout/ci/docker/x86_64-unknown-linux-gnu/cpuid.def \ -rtm-mode full -tsx --" diff --git a/library/stdarch/ci/docker/x86_64-unknown-linux-gnu/cpuid.def b/library/stdarch/ci/docker/x86_64-unknown-linux-gnu/cpuid.def index 342f7d83a63e3..3bd657873e553 100644 --- a/library/stdarch/ci/docker/x86_64-unknown-linux-gnu/cpuid.def +++ b/library/stdarch/ci/docker/x86_64-unknown-linux-gnu/cpuid.def @@ -1,4 +1,4 @@ -# Copyright (C) 2017-2025 Intel Corporation. +# Copyright (C) 2017-2026 Intel Corporation. # # This software and the related documents are Intel copyrighted materials, and your # use of them is governed by the express license under which they were provided to @@ -12,7 +12,7 @@ # CPUID_VERSION = 1.0 # Input => Output # EAX ECX => EAX EBX ECX EDX -00000000 ******** => 00000024 756e6547 6c65746e 49656e69 +00000000 ******** => 00000029 756e6547 6c65746e 49656e69 00000001 ******** => 00400f10 00100800 7ffaf3ff bfebfbff 00000002 ******** => 76035a01 00f0b6ff 00000000 00c10000 00000003 ******** => 00000000 00000000 00000000 00000000 @@ -23,8 +23,9 @@ 00000004 00000004 => 00000000 00000000 00000000 00000000 00000005 ******** => 00000040 00000040 00000003 00042120 #MONITOR/MWAIT 00000006 ******** => 00000077 00000002 00000001 00000000 #Thermal and Power -00000007 00000000 => 00000001 f3bfbfbf bac05ffe 03d54130 #Extended Features +00000007 00000000 => 00000002 f3bfbfbf bac05ffe 03d54130 #Extended Features 00000007 00000001 => 98ee00bf 00000002 00000020 1d29cd3e +00000007 00000002 => 00000000 00000000 00000000 00000010 00000008 ******** => 00000000 00000000 00000000 00000000 00000009 ******** => 00000000 00000000 00000000 00000000 #Direct Cache 0000000a ******** => 07300403 00000000 00000000 00000603 @@ -48,6 +49,7 @@ 0000001e 00000001 => 000001ff 00000000 00000000 00000000 00000024 00000000 => 00000001 00070002 00000000 00000000 #AVX10 00000024 00000001 => 00000000 00000000 00000004 00000000 +00000029 ******** => 00000000 00000001 00000000 00000000 80000000 ******** => 80000008 00000000 00000000 00000000 80000001 ******** => 00000000 00000000 00000121 2c100000 80000002 ******** => 00000000 00000000 00000000 00000000 diff --git a/library/stdarch/ci/dox.sh b/library/stdarch/ci/dox.sh index 9803f7e371119..d65192688f81a 100755 --- a/library/stdarch/ci/dox.sh +++ b/library/stdarch/ci/dox.sh @@ -22,6 +22,7 @@ dox() { export CARGO_UNSTABLE_BUILD_STD=core # amdgpu needs a target-cpu, any is fine export RUSTFLAGS="${RUSTFLAGS} -Ctarget-cpu=gfx900" + export RUSTDOCFLAGS="${RUSTDOCFLAGS} -Ctarget-cpu=gfx900" fi cargo build --verbose --target "${1}" --manifest-path crates/core_arch/Cargo.toml diff --git a/library/stdarch/ci/intrinsic-test-docker.sh b/library/stdarch/ci/intrinsic-test-docker.sh index beeff42c76212..c1d44dca91c5e 100755 --- a/library/stdarch/ci/intrinsic-test-docker.sh +++ b/library/stdarch/ci/intrinsic-test-docker.sh @@ -5,8 +5,8 @@ set -ex -if [ $# -lt 1 ]; then - >&2 echo "Usage: $0 " +if [ $# -lt 2 ]; then + >&2 echo "Usage: $0 " exit 1 fi @@ -29,7 +29,6 @@ run() { --user "$(id -u)":"$(id -g)" \ --env CARGO_HOME=/cargo \ --env CARGO_TARGET_DIR=/checkout/target \ - --env TARGET="${1}" \ --env PROFILE \ --env "${HOST_LINKER}"="cc" \ --env STDARCH_DISABLE_ASSERT_INSTR \ @@ -48,12 +47,12 @@ run() { --workdir /checkout \ --privileged \ stdarch \ - sh -c "HOME=/tmp PATH=\$PATH:/rust/bin exec ci/intrinsic-test.sh ${1}" + sh -c "HOME=/tmp PATH=\$PATH:/rust/bin exec ci/intrinsic-test.sh ${1} ${2}" } if [ -z "$1" ]; then >&2 echo "No target specified!" exit 1 else - run "${1}" + run "${1}" "${2}" fi diff --git a/library/stdarch/ci/intrinsic-test.sh b/library/stdarch/ci/intrinsic-test.sh index 89104e2672ad9..3966aa88d8f41 100755 --- a/library/stdarch/ci/intrinsic-test.sh +++ b/library/stdarch/ci/intrinsic-test.sh @@ -1,131 +1,94 @@ #!/usr/bin/env sh -set -ex +if [ $# -lt 2 ]; then + >&2 echo "Usage: $0 <..args for \`cargo test\`..>" + exit 1 +fi -: "${TARGET?The TARGET environment variable must be set.}" +set -ex -export RUSTFLAGS="${RUSTFLAGS} -D warnings -Z merge-functions=disabled -Z verify-llvm-ir" -export HOST_RUSTFLAGS="${RUSTFLAGS}" -export PROFILE="${PROFILE:="release"}" +# Pop both arguments and leave "$@" as containing args to be forwarded to `cargo test` +TARGET="$1" +shift +CC_KIND="$1" +shift -case ${TARGET} in - # On 32-bit use a static relocation model which avoids some extra - # instructions when dealing with static data, notably allowing some - # instruction assertion checks to pass below the 20 instruction limit. If - # this is the default, dynamic, then too many instructions are generated - # when we assert the instruction for a function and it causes tests to fail. - i686-* | i586-*) - export RUSTFLAGS="${RUSTFLAGS} -C relocation-model=static" +case ${CC_KIND} in + clang) + export CC="${CLANG_PATH}" + CC_ARG_STYLE=clang ;; - # Some x86_64 targets enable by default more features beyond SSE2, - # which cause some instruction assertion checks to fail. - x86_64-*) - export RUSTFLAGS="${RUSTFLAGS} -C target-feature=-sse3" + gcc) + export CC="${GCC_PATH}" + CC_ARG_STYLE=gcc ;; - #Unoptimized build uses fast-isel which breaks with msa - mips-* | mipsel-*) - export RUSTFLAGS="${RUSTFLAGS} -C llvm-args=-fast-isel=false" - ;; - armv7-*eabihf | thumbv7-*eabihf) - export RUSTFLAGS="${RUSTFLAGS} -Ctarget-feature=+neon" + icx) + export CC="${ICX_PATH}" + # `icx` uses clang-style arguments + CC_ARG_STYLE=clang ;; - # Some of our test dependencies use the deprecated `gcc` crates which - # doesn't detect RISC-V compilers automatically, so do it manually here. - riscv*) - export RUSTFLAGS="${RUSTFLAGS} -Ctarget-feature=+zk,+zks,+zbb,+zbc" + *) + >&2 echo "Unknown compiler: ${CC_KIND}" + exit 1 ;; esac +export RUSTFLAGS="${RUSTFLAGS} -D warnings -Z merge-functions=disabled -Z verify-llvm-ir" +export PROFILE="${PROFILE:="release"}" + echo "RUSTFLAGS=${RUSTFLAGS}" -echo "OBJDUMP=${OBJDUMP}" echo "PROFILE=${PROFILE}" INTRINSIC_TEST="--manifest-path=crates/intrinsic-test/Cargo.toml" -# Test targets compiled with extra features. case ${TARGET} in - # Setup aarch64 & armv7 specific variables, the runner, along with some - # tests to skip - aarch64-unknown-linux-gnu*) - TEST_CPPFLAGS="-fuse-ld=lld -I/usr/aarch64-linux-gnu/include/ -I/usr/aarch64-linux-gnu/include/c++/9/aarch64-linux-gnu/" - TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_aarch64.txt - TEST_CXX_COMPILER="clang++" - TEST_RUNNER="${CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_RUNNER}" - : "${TEST_SAMPLE_INTRINSICS_PERCENTAGE:=100}" + aarch64_be*) + export CFLAGS="-I${AARCH64_BE_TOOLCHAIN}/aarch64_be-none-linux-gnu/libc/usr/include --sysroot={AARCH64_BE_TOOLCHAIN}/aarch64_be-none-linux-gnu/libc -Wno-nonportable-vector-initialization" + ARCH=aarch64_be + RUNTIME_RUSTFLAGS= ;; - aarch64_be-unknown-linux-gnu*) - TEST_CPPFLAGS="-fuse-ld=lld" - TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_aarch64_be.txt - TEST_CXX_COMPILER="clang++" - TEST_RUNNER="${CARGO_TARGET_AARCH64_BE_UNKNOWN_LINUX_GNU_RUNNER}" - : "${TEST_SAMPLE_INTRINSICS_PERCENTAGE:=100}" + aarch64*) + export CFLAGS="-I/usr/aarch64-linux-gnu/include/" + ARCH=aarch64 + RUNTIME_RUSTFLAGS=-Ctarget-feature=+sve,+sve2 ;; - armv7-unknown-linux-gnueabihf*) - TEST_CPPFLAGS="-fuse-ld=lld -I/usr/arm-linux-gnueabihf/include/ -I/usr/arm-linux-gnueabihf/include/c++/9/arm-linux-gnueabihf/" - TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_arm.txt - TEST_CXX_COMPILER="clang++" - TEST_RUNNER="${CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_RUNNER}" - : "${TEST_SAMPLE_INTRINSICS_PERCENTAGE:=100}" + armv7*) + export CFLAGS="-I/usr/arm-linux-gnueabihf/include/" + ARCH=arm + RUNTIME_RUSTFLAGS= ;; - x86_64-unknown-linux-gnu*) - TEST_CPPFLAGS="-fuse-ld=lld -I/usr/include/x86_64-linux-gnu/" - TEST_CXX_COMPILER="clang++" - TEST_RUNNER="${CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER}" - TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_x86.txt - : "${TEST_SAMPLE_INTRINSICS_PERCENTAGE:=20}" + x86_64*) + export CFLAGS="-I/usr/include/x86_64-linux-gnu/" + ARCH=x86 + RUNTIME_RUSTFLAGS= ;; *) ;; esac -# Arm specific case "${TARGET}" in - aarch64-unknown-linux-gnu*|armv7-unknown-linux-gnueabihf*) - CPPFLAGS="${TEST_CPPFLAGS}" RUSTFLAGS="${HOST_RUSTFLAGS}" RUST_LOG=warn \ - cargo run "${INTRINSIC_TEST}" --release \ - --bin intrinsic-test -- intrinsics_data/arm_intrinsics.json \ - --runner "${TEST_RUNNER}" \ - --cppcompiler "${TEST_CXX_COMPILER}" \ - --skip "${TEST_SKIP_INTRINSICS}" \ - --target "${TARGET}" \ - --profile "${PROFILE}" \ - --sample-percentage "${TEST_SAMPLE_INTRINSICS_PERCENTAGE}" - ;; - - aarch64_be-unknown-linux-gnu*) - CPPFLAGS="${TEST_CPPFLAGS}" RUSTFLAGS="${HOST_RUSTFLAGS}" RUST_LOG=warn \ - cargo run "${INTRINSIC_TEST}" --release \ - --bin intrinsic-test -- intrinsics_data/arm_intrinsics.json \ - --runner "${TEST_RUNNER}" \ - --cppcompiler "${TEST_CXX_COMPILER}" \ - --skip "${TEST_SKIP_INTRINSICS}" \ - --target "${TARGET}" \ - --profile "${PROFILE}" \ - --linker "${CARGO_TARGET_AARCH64_BE_UNKNOWN_LINUX_GNU_LINKER}" \ - --cxx-toolchain-dir "${AARCH64_BE_TOOLCHAIN}" \ - --sample-percentage "${TEST_SAMPLE_INTRINSICS_PERCENTAGE}" - ;; - x86_64-unknown-linux-gnu*) - # `CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER` is not necessary for `intrinsic-test` - # because the binary needs to run directly on the host. - # Hence the use of `env -u`. env -u CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER \ - CPPFLAGS="${TEST_CPPFLAGS}" RUSTFLAGS="${HOST_RUSTFLAGS}" \ - RUST_LOG=warn RUST_BACKTRACE=1 \ cargo run "${INTRINSIC_TEST}" --release \ --bin intrinsic-test -- intrinsics_data/x86-intel.xml \ - --runner "${TEST_RUNNER}" \ - --skip "${TEST_SKIP_INTRINSICS}" \ - --cppcompiler "${TEST_CXX_COMPILER}" \ + --skip "crates/intrinsic-test/missing_${ARCH}_common.txt" \ + --skip "crates/intrinsic-test/missing_${ARCH}_${CC_KIND}.txt" \ --target "${TARGET}" \ - --profile "${PROFILE}" \ - --sample-percentage "${TEST_SAMPLE_INTRINSICS_PERCENTAGE}" + --cc-arg-style "${CC_ARG_STYLE}" ;; - *) + *) + cargo run "${INTRINSIC_TEST}" --release \ + --bin intrinsic-test -- intrinsics_data/arm_intrinsics.json \ + --skip "crates/intrinsic-test/missing_${ARCH}_common.txt" \ + --skip "crates/intrinsic-test/missing_${ARCH}_${CC_KIND}.txt" \ + --target "${TARGET}" \ + --cc-arg-style "${CC_ARG_STYLE}" ;; esac + +RUSTFLAGS="${RUNTIME_RUSTFLAGS}" cargo test --manifest-path=rust_programs/Cargo.toml \ + --target "${TARGET}" --profile "${PROFILE}" --tests --no-fail-fast "$@" diff --git a/library/stdarch/ci/run.sh b/library/stdarch/ci/run.sh index 8a0b5fa26f66c..8c75df6afbe4f 100755 --- a/library/stdarch/ci/run.sh +++ b/library/stdarch/ci/run.sh @@ -50,6 +50,9 @@ case ${TARGET} in riscv*) export RUSTFLAGS="${RUSTFLAGS} -Ctarget-feature=+zk,+zks,+zbb,+zbc" ;; + hexagon*) + export RUSTFLAGS="${RUSTFLAGS} -Ctarget-feature=+hvxv60,+hvx-length128b" + ;; esac echo "RUSTFLAGS=${RUSTFLAGS}" @@ -79,7 +82,7 @@ cargo_test() { else dir="debug" fi - export CARGO_TARGET_WASM32_WASIP1_RUNNER="wasmtime -Wexceptions --dir /checkout/target/wasm32-wasip1/$dir/deps::." + export CARGO_TARGET_WASM32_WASIP1_RUNNER="wasmtime -Wexceptions --dir /checkout/target/wasm32-wasip1/$dir/build::." cmd="$cmd --nocapture" ;; esac diff --git a/library/stdarch/crates/assert-instr-macro/src/lib.rs b/library/stdarch/crates/assert-instr-macro/src/lib.rs index 13c3c3851b43c..839aae67cb2b0 100644 --- a/library/stdarch/crates/assert-instr-macro/src/lib.rs +++ b/library/stdarch/crates/assert-instr-macro/src/lib.rs @@ -14,6 +14,7 @@ extern crate quote; use proc_macro2::TokenStream; use quote::ToTokens; +use syn::spanned::Spanned; #[proc_macro_attribute] pub fn assert_instr( @@ -67,21 +68,21 @@ pub fn assert_instr( ); let mut inputs = Vec::new(); let mut input_vals = Vec::new(); - let mut const_vals = Vec::new(); + let mut param_vals = Vec::new(); let ret = &func.sig.output; for arg in func.sig.inputs.iter() { let capture = match *arg { - syn::FnArg::Typed(ref c) => c, + syn::FnArg::Typed(ref c) => c.to_owned(), ref v => panic!( "arguments must not have patterns: `{:?}`", v.clone().into_token_stream() ), }; - let ident = match *capture.pat { - syn::Pat::Ident(ref i) => &i.ident, + let ident = match capture.pat.as_ref() { + syn::Pat::Ident(i) => &i.ident.to_owned(), _ => panic!("must have bare arguments"), }; - if let Some((_, tokens)) = invoc.args.iter().find(|a| *ident == a.0) { + if let Some(&(_, ref tokens)) = invoc.args.iter().find(|a| *ident == a.0) { input_vals.push(quote! { #tokens }); } else { inputs.push(capture); @@ -89,18 +90,48 @@ pub fn assert_instr( } } for arg in func.sig.generics.params.iter() { - let c = match *arg { - syn::GenericParam::Const(ref c) => c, + match *arg { + syn::GenericParam::Const(ref c) => { + if let Some((_, tokens)) = invoc.args.iter().find(|a| c.ident == a.0) { + param_vals.push(quote! { #tokens }); + } else { + panic!("const generics must have a value for tests"); + } + } + syn::GenericParam::Type(ref t) => { + if let Some((_, tokens)) = invoc.args.iter().find(|a| t.ident == a.0) + && let syn::Expr::Path(syn::ExprPath { qself, path, .. }) = tokens + { + param_vals.push(syn::Token![_](tokens.span()).to_token_stream()); + + let generic_ty_value = syn::TypePath { + qself: qself.clone(), + path: path.clone(), + }; + + // Replace any function arguments that use generic parameters with the + // instantiation provided in the macro invocation. + inputs.iter_mut().for_each(|arg| { + update_type_path(arg.ty.as_mut(), |type_path: &mut syn::TypePath| { + if let Some(syn::PathSegment { + ident: last_ident, .. + }) = type_path.path.segments.last_mut() + { + if *last_ident == t.ident { + *type_path = generic_ty_value.to_owned() + } + } + }) + }); + } else { + panic!("type generics must have a type for tests"); + } + } ref v => panic!( - "only const generics are allowed: `{:?}`", + "only type and const generics are allowed: `{:?}`", v.clone().into_token_stream() ), }; - if let Some((_, tokens)) = invoc.args.iter().find(|a| c.ident == a.0) { - const_vals.push(quote! { #tokens }); - } else { - panic!("const generics must have a value for tests"); - } } let attrs = func @@ -138,7 +169,7 @@ pub fn assert_instr( #[unsafe(no_mangle)] #[inline(never)] pub unsafe extern #abi fn #shim_name(#(#inputs),*) #ret { - #name::<#(#const_vals),*>(#(#input_vals),*) + #name::<#(#param_vals),*>(#(#input_vals),*) } }; @@ -222,3 +253,23 @@ where } } } + +/// Calls `update` on type paths so that type generics can be replaced with the instantiation from +/// the attribute. +fn update_type_path(ty: &mut syn::Type, update: F) +where + F: Fn(&mut syn::TypePath), +{ + use syn::Type::*; + match ty { + Array(syn::TypeArray { elem, .. }) + | Group(syn::TypeGroup { elem, .. }) + | Paren(syn::TypeParen { elem, .. }) + | Ptr(syn::TypePtr { elem, .. }) + | Reference(syn::TypeReference { elem, .. }) + | Slice(syn::TypeSlice { elem, .. }) => update_type_path(elem.as_mut(), update), + Path(path @ syn::TypePath { .. }) => update(path), + Tuple(..) => panic!("tuples and generic types together are not yet supported"), + _ => {} + } +} diff --git a/library/stdarch/crates/core_arch/missing-x86.md b/library/stdarch/crates/core_arch/missing-x86.md index 640ec7d0fe7d1..637c8d4a8657b 100644 --- a/library/stdarch/crates/core_arch/missing-x86.md +++ b/library/stdarch/crates/core_arch/missing-x86.md @@ -1,41 +1,4 @@ -

["AMX-BF16"]

- - * [ ] [`__tile_dpbf16ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_dpbf16ps) -

- - -
["AMX-COMPLEX"]

- - * [ ] [`__tile_cmmimfp16ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_cmmimfp16ps) - * [ ] [`__tile_cmmrlfp16ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_cmmrlfp16ps) -

- - -
["AMX-FP16"]

- - * [ ] [`__tile_dpfp16ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_dpfp16ps) -

- - -
["AMX-INT8"]

- - * [ ] [`__tile_dpbssd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_dpbssd) - * [ ] [`__tile_dpbsud`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_dpbsud) - * [ ] [`__tile_dpbusd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_dpbusd) - * [ ] [`__tile_dpbuud`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_dpbuud) -

- - -
["AMX-TILE"]

- - * [ ] [`__tile_loadd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_loadd) - * [ ] [`__tile_stored`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_stored) - * [ ] [`__tile_stream_loadd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_stream_loadd) - * [ ] [`__tile_zero`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_zero) -

- -
["AVX512_FP16"]

* [ ] [`_mm256_set1_pch`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set1_pch) @@ -44,22 +7,6 @@

-
["AVX512_VP2INTERSECT", "AVX512F"]

- - * [ ] [`_mm512_2intersect_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_2intersect_epi32) - * [ ] [`_mm512_2intersect_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_2intersect_epi64) -

- - -
["AVX512_VP2INTERSECT", "AVX512VL"]

- - * [ ] [`_mm256_2intersect_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_2intersect_epi32) - * [ ] [`_mm256_2intersect_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_2intersect_epi64) - * [ ] [`_mm_2intersect_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_2intersect_epi32) - * [ ] [`_mm_2intersect_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_2intersect_epi64) -

- -
["CET_SS"]

* [ ] [`_clrssbsy`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_clrssbsy) @@ -86,12 +33,6 @@

-
["CLFLUSHOPT"]

- - * [ ] [`_mm_clflushopt`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_clflushopt) -

- -
["CLWB"]

* [ ] [`_mm_clwb`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_clwb) diff --git a/library/stdarch/crates/core_arch/src/aarch64/mod.rs b/library/stdarch/crates/core_arch/src/aarch64/mod.rs index b48bdac57e7db..1f07f024721dc 100644 --- a/library/stdarch/crates/core_arch/src/aarch64/mod.rs +++ b/library/stdarch/crates/core_arch/src/aarch64/mod.rs @@ -17,10 +17,28 @@ mod mte; #[unstable(feature = "stdarch_aarch64_mte", issue = "129010")] pub use self::mte::*; +mod rand; +#[unstable(feature = "stdarch_aarch64_rand", issue = "153514")] +pub use self::rand::*; + mod neon; #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub use self::neon::*; +// The rest of `core_arch::aarch64` is available on `arm64ec` but SVE is not supported on `arm64ec`. +#[cfg(any(all(target_arch = "aarch64", target_endian = "little"), doc))] +mod sve; +#[cfg(any(all(target_arch = "aarch64", target_endian = "little"), doc))] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub use self::sve::*; + +// The rest of `core_arch::aarch64` is available on `arm64ec` but SVE is not supported on `arm64ec`. +#[cfg(any(all(target_arch = "aarch64", target_endian = "little"), doc))] +mod sve2; +#[cfg(any(all(target_arch = "aarch64", target_endian = "little"), doc))] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub use self::sve2::*; + mod prefetch; #[unstable(feature = "stdarch_aarch64_prefetch", issue = "117217")] pub use self::prefetch::*; diff --git a/library/stdarch/crates/core_arch/src/aarch64/mte.rs b/library/stdarch/crates/core_arch/src/aarch64/mte.rs index c400f774bcce0..a5031a45c1a0e 100644 --- a/library/stdarch/crates/core_arch/src/aarch64/mte.rs +++ b/library/stdarch/crates/core_arch/src/aarch64/mte.rs @@ -3,35 +3,17 @@ //! [ACLE documentation](https://arm-software.github.io/acle/main/acle.html#markdown-toc-mte-intrinsics) unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.irg" - )] + #[link_name = "llvm.aarch64.irg"] fn irg_(ptr: *const (), exclude: i64) -> *const (); - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.gmi" - )] + #[link_name = "llvm.aarch64.gmi"] fn gmi_(ptr: *const (), exclude: i64) -> i64; - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.ldg" - )] + #[link_name = "llvm.aarch64.ldg"] fn ldg_(ptr: *const (), tag_ptr: *const ()) -> *const (); - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.stg" - )] + #[link_name = "llvm.aarch64.stg"] fn stg_(tagged_ptr: *const (), addr_to_tag: *const ()); - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.addg" - )] + #[link_name = "llvm.aarch64.addg"] fn addg_(ptr: *const (), value: i64) -> *const (); - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.subp" - )] + #[link_name = "llvm.aarch64.subp"] fn subp_(ptr_a: *const (), ptr_b: *const ()) -> i64; } @@ -127,42 +109,46 @@ mod test { use super::*; use stdarch_test::assert_instr; - #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(irg))] // FIXME: MSVC `dumpbin` doesn't support MTE + // Instruction tests are separate because the functions use generics. + // + // FIXME: As of 2026 MSVC `dumpbin` doesn't support MTE. + + #[cfg_attr(not(target_env = "msvc"), assert_instr(irg))] #[allow(dead_code)] #[target_feature(enable = "mte")] unsafe fn test_arm_mte_create_random_tag(src: *const (), mask: u64) -> *const () { __arm_mte_create_random_tag(src, mask) } - #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(addg))] + #[cfg_attr(not(target_env = "msvc"), assert_instr(addg))] #[allow(dead_code)] #[target_feature(enable = "mte")] unsafe fn test_arm_mte_increment_tag(src: *const ()) -> *const () { __arm_mte_increment_tag::<1, _>(src) } - #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(gmi))] + #[cfg_attr(not(target_env = "msvc"), assert_instr(gmi))] #[allow(dead_code)] #[target_feature(enable = "mte")] unsafe fn test_arm_mte_exclude_tag(src: *const (), excluded: u64) -> u64 { __arm_mte_exclude_tag(src, excluded) } - #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stg))] + #[cfg_attr(not(target_env = "msvc"), assert_instr(stg))] #[allow(dead_code)] #[target_feature(enable = "mte")] unsafe fn test_arm_mte_set_tag(src: *const ()) { __arm_mte_set_tag(src) } - #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldg))] + #[cfg_attr(not(target_env = "msvc"), assert_instr(ldg))] #[allow(dead_code)] #[target_feature(enable = "mte")] unsafe fn test_arm_mte_get_tag(src: *const ()) -> *const () { __arm_mte_get_tag(src) } - #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(subp))] + #[cfg_attr(not(target_env = "msvc"), assert_instr(subp))] #[allow(dead_code)] #[target_feature(enable = "mte")] unsafe fn test_arm_mte_ptrdiff(a: *const (), b: *const ()) -> i64 { diff --git a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs index 9507b71106dd1..1b5b17e538bde 100644 --- a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs +++ b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs @@ -14,7 +14,7 @@ use super::*; #[doc = "CRC32-C single round checksum for quad words (64 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)"] -#[inline(always)] +#[inline] #[target_feature(enable = "crc")] #[cfg_attr(test, assert_instr(crc32cx))] #[stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")] @@ -30,7 +30,7 @@ pub fn __crc32cd(crc: u32, data: u64) -> u32 { } #[doc = "CRC32 single round checksum for quad words (64 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)"] -#[inline(always)] +#[inline] #[target_feature(enable = "crc")] #[cfg_attr(test, assert_instr(crc32x))] #[stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")] @@ -46,10 +46,10 @@ pub fn __crc32d(crc: u32, data: u64) -> u32 { } #[doc = "Floating-point JavaScript convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__jcvt)"] -#[inline(always)] +#[inline] #[target_feature(enable = "jsconv")] #[cfg_attr(test, assert_instr(fjcvtzs))] -#[stable(feature = "stdarch_aarch64_jscvt", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_aarch64_jscvt", since = "1.95.0")] pub fn __jcvt(a: f64) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( @@ -62,94 +62,106 @@ pub fn __jcvt(a: f64) -> i32 { } #[doc = "Signed Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(sabal2) +)] pub fn vabal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { + let d = vget_high_s8(b); + let e = vget_high_s8(c); + let f = vabd_s8(d, e); unsafe { - let d: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let e: int8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - let f: int8x8_t = vabd_s8(d, e); let f: uint8x8_t = simd_cast(f); simd_add(a, simd_cast(f)) } } #[doc = "Signed Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(sabal2) +)] pub fn vabal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { + let d = vget_high_s16(b); + let e = vget_high_s16(c); + let f = vabd_s16(d, e); unsafe { - let d: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let e: int16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - let f: int16x4_t = vabd_s16(d, e); let f: uint16x4_t = simd_cast(f); simd_add(a, simd_cast(f)) } } #[doc = "Signed Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(sabal2) +)] pub fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { + let d = vget_high_s32(b); + let e = vget_high_s32(c); + let f = vabd_s32(d, e); unsafe { - let d: int32x2_t = simd_shuffle!(b, b, [2, 3]); - let e: int32x2_t = simd_shuffle!(c, c, [2, 3]); - let f: int32x2_t = vabd_s32(d, e); let f: uint32x2_t = simd_cast(f); simd_add(a, simd_cast(f)) } } #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uabal2) +)] pub fn vabal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { - unsafe { - let d: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let e: uint8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - let f: uint8x8_t = vabd_u8(d, e); - simd_add(a, simd_cast(f)) - } + let d = vget_high_u8(b); + let e = vget_high_u8(c); + let f = vabd_u8(d, e); + unsafe { simd_add(a, simd_cast(f)) } } #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uabal2) +)] pub fn vabal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { - unsafe { - let d: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let e: uint16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - let f: uint16x4_t = vabd_u16(d, e); - simd_add(a, simd_cast(f)) - } + let d = vget_high_u16(b); + let e = vget_high_u16(c); + let f = vabd_u16(d, e); + unsafe { simd_add(a, simd_cast(f)) } } #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uabal2) +)] pub fn vabal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { - unsafe { - let d: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - let e: uint32x2_t = simd_shuffle!(c, c, [2, 3]); - let f: uint32x2_t = vabd_u32(d, e); - simd_add(a, simd_cast(f)) - } + let d = vget_high_u32(b); + let e = vget_high_u32(c); + let f = vabd_u32(d, e); + unsafe { simd_add(a, simd_cast(f)) } } #[doc = "Absolute difference between the arguments of Floating"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fabd))] @@ -165,7 +177,7 @@ pub fn vabd_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } #[doc = "Absolute difference between the arguments of Floating"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fabd))] @@ -181,116 +193,110 @@ pub fn vabdq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Floating-point absolute difference"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fabd))] pub fn vabdd_f64(a: f64, b: f64) -> f64 { - unsafe { simd_extract!(vabd_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } + vget_lane_f64::<0>(vabd_f64(vdup_n_f64(a), vdup_n_f64(b))) } #[doc = "Floating-point absolute difference"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabds_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fabd))] pub fn vabds_f32(a: f32, b: f32) -> f32 { - unsafe { simd_extract!(vabd_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } + vget_lane_f32::<0>(vabd_f32(vdup_n_f32(a), vdup_n_f32(b))) } #[doc = "Floating-point absolute difference"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fabd))] pub fn vabdh_f16(a: f16, b: f16) -> f16 { - unsafe { simd_extract!(vabd_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) } + vget_lane_f16::<0>(vabd_f16(vdup_n_f16(a), vdup_n_f16(b))) } #[doc = "Signed Absolute difference Long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s8)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(sabdl2))] -pub fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sabdl2))] +pub fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { + let c = vget_high_s8(a); + let d = vget_high_s8(b); unsafe { - let c: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let d: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let e: uint16x4_t = simd_cast(vabd_s16(c, d)); + let e: uint8x8_t = simd_cast(vabd_s8(c, d)); simd_cast(e) } } #[doc = "Signed Absolute difference Long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s16)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(sabdl2))] -pub fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sabdl2))] +pub fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { + let c = vget_high_s16(a); + let d = vget_high_s16(b); unsafe { - let c: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let d: int32x2_t = simd_shuffle!(b, b, [2, 3]); - let e: uint32x2_t = simd_cast(vabd_s32(c, d)); + let e: uint16x4_t = simd_cast(vabd_s16(c, d)); simd_cast(e) } } #[doc = "Signed Absolute difference Long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s32)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(sabdl2))] -pub fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sabdl2))] +pub fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { + let c = vget_high_s32(a); + let d = vget_high_s32(b); unsafe { - let c: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let d: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let e: uint8x8_t = simd_cast(vabd_s8(c, d)); + let e: uint32x2_t = simd_cast(vabd_s32(c, d)); simd_cast(e) } } #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uabdl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uabdl2))] pub fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { - unsafe { - let c: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let d: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - simd_cast(vabd_u8(c, d)) - } + let c = vget_high_u8(a); + let d = vget_high_u8(b); + unsafe { simd_cast(vabd_u8(c, d)) } } #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uabdl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uabdl2))] pub fn vabdl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { - unsafe { - let c: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let d: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - simd_cast(vabd_u16(c, d)) - } + let c = vget_high_u16(a); + let d = vget_high_u16(b); + unsafe { simd_cast(vabd_u16(c, d)) } } #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uabdl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uabdl2))] pub fn vabdl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { - unsafe { - let c: uint32x2_t = simd_shuffle!(a, a, [2, 3]); - let d: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - simd_cast(vabd_u32(c, d)) - } + let c = vget_high_u32(a); + let d = vget_high_u32(b); + unsafe { simd_cast(vabd_u32(c, d)) } } #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fabs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -299,7 +305,7 @@ pub fn vabs_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fabs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -308,7 +314,7 @@ pub fn vabsq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Absolute Value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(abs))] @@ -321,7 +327,7 @@ pub fn vabs_s64(a: int64x1_t) -> int64x1_t { } #[doc = "Absolute Value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(abs))] @@ -334,7 +340,7 @@ pub fn vabsq_s64(a: int64x2_t) -> int64x2_t { } #[doc = "Absolute Value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(abs))] @@ -350,7 +356,7 @@ pub fn vabsd_s64(a: i64) -> i64 { } #[doc = "Add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] @@ -359,7 +365,7 @@ pub fn vaddd_s64(a: i64, b: i64) -> i64 { } #[doc = "Add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] @@ -368,7 +374,7 @@ pub fn vaddd_u64(a: u64, b: u64) -> u64 { } #[doc = "Signed Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(saddlv))] @@ -384,7 +390,7 @@ pub fn vaddlv_s16(a: int16x4_t) -> i32 { } #[doc = "Signed Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(saddlv))] @@ -400,7 +406,7 @@ pub fn vaddlvq_s16(a: int16x8_t) -> i32 { } #[doc = "Signed Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(saddlv))] @@ -416,7 +422,7 @@ pub fn vaddlvq_s32(a: int32x4_t) -> i64 { } #[doc = "Signed Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(saddlp))] @@ -432,7 +438,7 @@ pub fn vaddlv_s32(a: int32x2_t) -> i64 { } #[doc = "Signed Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(saddlv))] @@ -448,7 +454,7 @@ pub fn vaddlv_s8(a: int8x8_t) -> i16 { } #[doc = "Signed Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(saddlv))] @@ -464,7 +470,7 @@ pub fn vaddlvq_s8(a: int8x16_t) -> i16 { } #[doc = "Unsigned Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uaddlv))] @@ -480,7 +486,7 @@ pub fn vaddlv_u16(a: uint16x4_t) -> u32 { } #[doc = "Unsigned Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uaddlv))] @@ -496,7 +502,7 @@ pub fn vaddlvq_u16(a: uint16x8_t) -> u32 { } #[doc = "Unsigned Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uaddlv))] @@ -512,7 +518,7 @@ pub fn vaddlvq_u32(a: uint32x4_t) -> u64 { } #[doc = "Unsigned Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uaddlp))] @@ -528,7 +534,7 @@ pub fn vaddlv_u32(a: uint32x2_t) -> u64 { } #[doc = "Unsigned Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uaddlv))] @@ -544,7 +550,7 @@ pub fn vaddlv_u8(a: uint8x8_t) -> u16 { } #[doc = "Unsigned Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uaddlv))] @@ -560,7 +566,7 @@ pub fn vaddlvq_u8(a: uint8x16_t) -> u16 { } #[doc = "Floating-point add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(faddp))] @@ -576,7 +582,7 @@ pub fn vaddv_f32(a: float32x2_t) -> f32 { } #[doc = "Floating-point add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(faddp))] @@ -592,7 +598,7 @@ pub fn vaddvq_f32(a: float32x4_t) -> f32 { } #[doc = "Floating-point add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(faddp))] @@ -608,7 +614,7 @@ pub fn vaddvq_f64(a: float64x2_t) -> f64 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] @@ -617,7 +623,7 @@ pub fn vaddv_s32(a: int32x2_t) -> i32 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] @@ -626,7 +632,7 @@ pub fn vaddv_s8(a: int8x8_t) -> i8 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] @@ -635,7 +641,7 @@ pub fn vaddvq_s8(a: int8x16_t) -> i8 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] @@ -644,7 +650,7 @@ pub fn vaddv_s16(a: int16x4_t) -> i16 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] @@ -653,7 +659,7 @@ pub fn vaddvq_s16(a: int16x8_t) -> i16 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] @@ -662,7 +668,7 @@ pub fn vaddvq_s32(a: int32x4_t) -> i32 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] @@ -671,7 +677,7 @@ pub fn vaddv_u32(a: uint32x2_t) -> u32 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] @@ -680,7 +686,7 @@ pub fn vaddv_u8(a: uint8x8_t) -> u8 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] @@ -689,7 +695,7 @@ pub fn vaddvq_u8(a: uint8x16_t) -> u8 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] @@ -698,7 +704,7 @@ pub fn vaddv_u16(a: uint16x4_t) -> u16 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] @@ -707,7 +713,7 @@ pub fn vaddvq_u16(a: uint16x8_t) -> u16 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] @@ -716,7 +722,7 @@ pub fn vaddvq_u32(a: uint32x4_t) -> u32 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] @@ -725,7 +731,7 @@ pub fn vaddvq_s64(a: int64x2_t) -> i64 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] @@ -734,7 +740,7 @@ pub fn vaddvq_u64(a: uint64x2_t) -> u64 { } #[doc = "Multi-vector floating-point absolute maximum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))] #[unstable(feature = "faminmax", issue = "137933")] @@ -750,7 +756,7 @@ pub fn vamax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { } #[doc = "Multi-vector floating-point absolute maximum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))] #[unstable(feature = "faminmax", issue = "137933")] @@ -766,7 +772,7 @@ pub fn vamaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { } #[doc = "Multi-vector floating-point absolute maximum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))] #[unstable(feature = "faminmax", issue = "137933")] @@ -782,7 +788,7 @@ pub fn vamax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } #[doc = "Multi-vector floating-point absolute maximum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))] #[unstable(feature = "faminmax", issue = "137933")] @@ -798,7 +804,7 @@ pub fn vamaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } #[doc = "Multi-vector floating-point absolute maximum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))] #[unstable(feature = "faminmax", issue = "137933")] @@ -814,7 +820,7 @@ pub fn vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Multi-vector floating-point absolute minimum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))] #[unstable(feature = "faminmax", issue = "137933")] @@ -830,7 +836,7 @@ pub fn vamin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { } #[doc = "Multi-vector floating-point absolute minimum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))] #[unstable(feature = "faminmax", issue = "137933")] @@ -846,7 +852,7 @@ pub fn vaminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { } #[doc = "Multi-vector floating-point absolute minimum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))] #[unstable(feature = "faminmax", issue = "137933")] @@ -862,7 +868,7 @@ pub fn vamin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } #[doc = "Multi-vector floating-point absolute minimum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))] #[unstable(feature = "faminmax", issue = "137933")] @@ -878,7 +884,7 @@ pub fn vaminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } #[doc = "Multi-vector floating-point absolute minimum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))] #[unstable(feature = "faminmax", issue = "137933")] @@ -894,7 +900,7 @@ pub fn vaminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] @@ -910,7 +916,7 @@ pub fn vbcaxq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] @@ -926,7 +932,7 @@ pub fn vbcaxq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] @@ -942,7 +948,7 @@ pub fn vbcaxq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] @@ -958,7 +964,7 @@ pub fn vbcaxq_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t { } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] @@ -974,7 +980,7 @@ pub fn vbcaxq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] @@ -990,7 +996,7 @@ pub fn vbcaxq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] @@ -1006,7 +1012,7 @@ pub fn vbcaxq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] @@ -1022,7 +1028,8 @@ pub fn vbcaxq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { } #[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot270_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] @@ -1039,8 +1046,33 @@ pub fn vcadd_rot270_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { _vcadd_rot270_f16(a, b) } } #[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot270_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fcadd))] +pub fn vcadd_rot270_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot270.v4f16" + )] + fn _vcadd_rot270_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = _vcadd_rot270_f16(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] @@ -1057,8 +1089,33 @@ pub fn vcaddq_rot270_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe { _vcaddq_rot270_f16(a, b) } } #[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fcadd))] +pub fn vcaddq_rot270_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot270.v8f16" + )] + fn _vcaddq_rot270_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = _vcaddq_rot270_f16(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot270_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcadd))] @@ -1073,8 +1130,31 @@ pub fn vcadd_rot270_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe { _vcadd_rot270_f32(a, b) } } #[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot270_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcadd))] +pub fn vcadd_rot270_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot270.v2f32" + )] + fn _vcadd_rot270_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = _vcadd_rot270_f32(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcadd))] @@ -1089,8 +1169,31 @@ pub fn vcaddq_rot270_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe { _vcaddq_rot270_f32(a, b) } } #[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcadd))] +pub fn vcaddq_rot270_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot270.v4f32" + )] + fn _vcaddq_rot270_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = _vcaddq_rot270_f32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcadd))] @@ -1105,8 +1208,31 @@ pub fn vcaddq_rot270_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe { _vcaddq_rot270_f64(a, b) } } #[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcadd))] +pub fn vcaddq_rot270_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot270.v2f64" + )] + fn _vcaddq_rot270_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = _vcaddq_rot270_f64(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot90_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] @@ -1123,8 +1249,33 @@ pub fn vcadd_rot90_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { _vcadd_rot90_f16(a, b) } } #[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot90_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fcadd))] +pub fn vcadd_rot90_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot90.v4f16" + )] + fn _vcadd_rot90_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = _vcadd_rot90_f16(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] @@ -1141,8 +1292,33 @@ pub fn vcaddq_rot90_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe { _vcaddq_rot90_f16(a, b) } } #[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fcadd))] +pub fn vcaddq_rot90_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot90.v8f16" + )] + fn _vcaddq_rot90_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = _vcaddq_rot90_f16(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot90_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcadd))] @@ -1157,8 +1333,31 @@ pub fn vcadd_rot90_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe { _vcadd_rot90_f32(a, b) } } #[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot90_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcadd))] +pub fn vcadd_rot90_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot90.v2f32" + )] + fn _vcadd_rot90_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = _vcadd_rot90_f32(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcadd))] @@ -1173,8 +1372,31 @@ pub fn vcaddq_rot90_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe { _vcaddq_rot90_f32(a, b) } } #[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcadd))] +pub fn vcaddq_rot90_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot90.v4f32" + )] + fn _vcaddq_rot90_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = _vcaddq_rot90_f32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcadd))] @@ -1188,9 +1410,31 @@ pub fn vcaddq_rot90_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } unsafe { _vcaddq_rot90_f64(a, b) } } +#[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcadd))] +pub fn vcaddq_rot90_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot90.v2f64" + )] + fn _vcaddq_rot90_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = _vcaddq_rot90_f64(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1206,7 +1450,7 @@ pub fn vcage_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1222,7 +1466,7 @@ pub fn vcageq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaged_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1238,7 +1482,7 @@ pub fn vcaged_f64(a: f64, b: f64) -> u64 { } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcages_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1254,7 +1498,7 @@ pub fn vcages_f32(a: f32, b: f32) -> u32 { } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(facge))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -1271,7 +1515,7 @@ pub fn vcageh_f16(a: f16, b: f16) -> u16 { } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1287,7 +1531,7 @@ pub fn vcagt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1303,7 +1547,7 @@ pub fn vcagtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1319,7 +1563,7 @@ pub fn vcagtd_f64(a: f64, b: f64) -> u64 { } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagts_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1335,7 +1579,7 @@ pub fn vcagts_f32(a: f32, b: f32) -> u32 { } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagth_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(facgt))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -1352,7 +1596,7 @@ pub fn vcagth_f16(a: f16, b: f16) -> u16 { } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1361,7 +1605,7 @@ pub fn vcale_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1370,7 +1614,7 @@ pub fn vcaleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaled_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1379,7 +1623,7 @@ pub fn vcaled_f64(a: f64, b: f64) -> u64 { } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcales_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1388,7 +1632,7 @@ pub fn vcales_f32(a: f32, b: f32) -> u32 { } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(facge))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -1398,7 +1642,7 @@ pub fn vcaleh_f16(a: f16, b: f16) -> u16 { } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1407,7 +1651,7 @@ pub fn vcalt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1416,7 +1660,7 @@ pub fn vcaltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1425,7 +1669,7 @@ pub fn vcaltd_f64(a: f64, b: f64) -> u64 { } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalts_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1434,7 +1678,7 @@ pub fn vcalts_f32(a: f32, b: f32) -> u32 { } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalth_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(facgt))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -1444,7 +1688,7 @@ pub fn vcalth_f16(a: f16, b: f16) -> u16 { } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1453,7 +1697,7 @@ pub fn vceq_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1462,7 +1706,7 @@ pub fn vceqq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1471,7 +1715,7 @@ pub fn vceq_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1480,7 +1724,7 @@ pub fn vceqq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1489,7 +1733,7 @@ pub fn vceq_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1498,7 +1742,7 @@ pub fn vceqq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1507,7 +1751,7 @@ pub fn vceq_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1516,25 +1760,25 @@ pub fn vceqq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t { } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vceqd_f64(a: f64, b: f64) -> u64 { - unsafe { simd_extract!(vceq_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } + vget_lane_u64::<0>(vceq_f64(vdup_n_f64(a), vdup_n_f64(b))) } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqs_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vceqs_f32(a: f32, b: f32) -> u32 { - unsafe { simd_extract!(vceq_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } + vget_lane_u32::<0>(vceq_f32(vdup_n_f32(a), vdup_n_f32(b))) } #[doc = "Compare bitwise equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1543,7 +1787,7 @@ pub fn vceqd_s64(a: i64, b: i64) -> u64 { } #[doc = "Compare bitwise equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1552,20 +1796,20 @@ pub fn vceqd_u64(a: u64, b: u64) -> u64 { } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vceqh_f16(a: f16, b: f16) -> u16 { - unsafe { simd_extract!(vceq_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) } + vget_lane_u16::<0>(vceq_f16(vdup_n_f16(a), vdup_n_f16(b))) } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmeq))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vceqz_f16(a: float16x4_t) -> uint16x4_t { let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0); @@ -1573,10 +1817,10 @@ pub fn vceqz_f16(a: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmeq))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vceqzq_f16(a: float16x8_t) -> uint16x8_t { let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0); @@ -1584,7 +1828,7 @@ pub fn vceqzq_f16(a: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1594,7 +1838,7 @@ pub fn vceqz_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1604,7 +1848,7 @@ pub fn vceqzq_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1614,7 +1858,7 @@ pub fn vceqz_f64(a: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1624,7 +1868,7 @@ pub fn vceqzq_f64(a: float64x2_t) -> uint64x2_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1634,7 +1878,7 @@ pub fn vceqz_s8(a: int8x8_t) -> uint8x8_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1644,7 +1888,7 @@ pub fn vceqzq_s8(a: int8x16_t) -> uint8x16_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1654,7 +1898,7 @@ pub fn vceqz_s16(a: int16x4_t) -> uint16x4_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1664,7 +1908,7 @@ pub fn vceqzq_s16(a: int16x8_t) -> uint16x8_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1674,7 +1918,7 @@ pub fn vceqz_s32(a: int32x2_t) -> uint32x2_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1684,7 +1928,7 @@ pub fn vceqzq_s32(a: int32x4_t) -> uint32x4_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1694,7 +1938,7 @@ pub fn vceqz_s64(a: int64x1_t) -> uint64x1_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1704,7 +1948,7 @@ pub fn vceqzq_s64(a: int64x2_t) -> uint64x2_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1714,7 +1958,7 @@ pub fn vceqz_p8(a: poly8x8_t) -> uint8x8_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1724,7 +1968,7 @@ pub fn vceqzq_p8(a: poly8x16_t) -> uint8x16_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1734,7 +1978,7 @@ pub fn vceqz_p64(a: poly64x1_t) -> uint64x1_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1744,7 +1988,7 @@ pub fn vceqzq_p64(a: poly64x2_t) -> uint64x2_t { } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1754,7 +1998,7 @@ pub fn vceqz_u8(a: uint8x8_t) -> uint8x8_t { } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1764,7 +2008,7 @@ pub fn vceqzq_u8(a: uint8x16_t) -> uint8x16_t { } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1774,7 +2018,7 @@ pub fn vceqz_u16(a: uint16x4_t) -> uint16x4_t { } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1784,7 +2028,7 @@ pub fn vceqzq_u16(a: uint16x8_t) -> uint16x8_t { } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1794,7 +2038,7 @@ pub fn vceqz_u32(a: uint32x2_t) -> uint32x2_t { } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1804,7 +2048,7 @@ pub fn vceqzq_u32(a: uint32x4_t) -> uint32x4_t { } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1814,7 +2058,7 @@ pub fn vceqz_u64(a: uint64x1_t) -> uint64x1_t { } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1824,7 +2068,7 @@ pub fn vceqzq_u64(a: uint64x2_t) -> uint64x2_t { } #[doc = "Compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1833,7 +2077,7 @@ pub fn vceqzd_s64(a: i64) -> u64 { } #[doc = "Compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1842,35 +2086,35 @@ pub fn vceqzd_u64(a: u64) -> u64 { } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vceqzh_f16(a: f16) -> u16 { - unsafe { simd_extract!(vceqz_f16(vdup_n_f16(a)), 0) } + vget_lane_u16::<0>(vceqz_f16(vdup_n_f16(a))) } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzs_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vceqzs_f32(a: f32) -> u32 { - unsafe { simd_extract!(vceqz_f32(vdup_n_f32(a)), 0) } + vget_lane_u32::<0>(vceqz_f32(vdup_n_f32(a))) } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vceqzd_f64(a: f64) -> u64 { - unsafe { simd_extract!(vceqz_f64(vdup_n_f64(a)), 0) } + vget_lane_u64::<0>(vceqz_f64(vdup_n_f64(a))) } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1879,7 +2123,7 @@ pub fn vcge_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1888,7 +2132,7 @@ pub fn vcgeq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1897,7 +2141,7 @@ pub fn vcge_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1906,7 +2150,7 @@ pub fn vcgeq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1915,7 +2159,7 @@ pub fn vcge_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1924,25 +2168,25 @@ pub fn vcgeq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcged_f64(a: f64, b: f64) -> u64 { - unsafe { simd_extract!(vcge_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } + vget_lane_u64::<0>(vcge_f64(vdup_n_f64(a), vdup_n_f64(b))) } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcges_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcges_f32(a: f32, b: f32) -> u32 { - unsafe { simd_extract!(vcge_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } + vget_lane_u32::<0>(vcge_f32(vdup_n_f32(a), vdup_n_f32(b))) } #[doc = "Compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1951,7 +2195,7 @@ pub fn vcged_s64(a: i64, b: i64) -> u64 { } #[doc = "Compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1960,17 +2204,17 @@ pub fn vcged_u64(a: u64, b: u64) -> u64 { } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcgeh_f16(a: f16, b: f16) -> u16 { - unsafe { simd_extract!(vcge_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) } + vget_lane_u16::<0>(vcge_f16(vdup_n_f16(a), vdup_n_f16(b))) } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1980,7 +2224,7 @@ pub fn vcgez_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1990,7 +2234,7 @@ pub fn vcgezq_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2000,7 +2244,7 @@ pub fn vcgez_f64(a: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2010,7 +2254,7 @@ pub fn vcgezq_f64(a: float64x2_t) -> uint64x2_t { } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2020,7 +2264,7 @@ pub fn vcgez_s8(a: int8x8_t) -> uint8x8_t { } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2030,7 +2274,7 @@ pub fn vcgezq_s8(a: int8x16_t) -> uint8x16_t { } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2040,7 +2284,7 @@ pub fn vcgez_s16(a: int16x4_t) -> uint16x4_t { } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2050,7 +2294,7 @@ pub fn vcgezq_s16(a: int16x8_t) -> uint16x8_t { } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2060,7 +2304,7 @@ pub fn vcgez_s32(a: int32x2_t) -> uint32x2_t { } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2070,7 +2314,7 @@ pub fn vcgezq_s32(a: int32x4_t) -> uint32x4_t { } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2080,7 +2324,7 @@ pub fn vcgez_s64(a: int64x1_t) -> uint64x1_t { } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2090,25 +2334,25 @@ pub fn vcgezq_s64(a: int64x2_t) -> uint64x2_t { } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcgezd_f64(a: f64) -> u64 { - unsafe { simd_extract!(vcgez_f64(vdup_n_f64(a)), 0) } + vget_lane_u64::<0>(vcgez_f64(vdup_n_f64(a))) } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezs_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcgezs_f32(a: f32) -> u32 { - unsafe { simd_extract!(vcgez_f32(vdup_n_f32(a)), 0) } + vget_lane_u32::<0>(vcgez_f32(vdup_n_f32(a))) } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2117,17 +2361,17 @@ pub fn vcgezd_s64(a: i64) -> u64 { } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcgezh_f16(a: f16) -> u16 { - unsafe { simd_extract!(vcgez_f16(vdup_n_f16(a)), 0) } + vget_lane_u16::<0>(vcgez_f16(vdup_n_f16(a))) } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2136,7 +2380,7 @@ pub fn vcgt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2145,7 +2389,7 @@ pub fn vcgtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2154,7 +2398,7 @@ pub fn vcgt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2163,7 +2407,7 @@ pub fn vcgtq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhi))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2172,7 +2416,7 @@ pub fn vcgt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhi))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2181,25 +2425,25 @@ pub fn vcgtq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcgtd_f64(a: f64, b: f64) -> u64 { - unsafe { simd_extract!(vcgt_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } + vget_lane_u64::<0>(vcgt_f64(vdup_n_f64(a), vdup_n_f64(b))) } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgts_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcgts_f32(a: f32, b: f32) -> u32 { - unsafe { simd_extract!(vcgt_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } + vget_lane_u32::<0>(vcgt_f32(vdup_n_f32(a), vdup_n_f32(b))) } #[doc = "Compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2208,7 +2452,7 @@ pub fn vcgtd_s64(a: i64, b: i64) -> u64 { } #[doc = "Compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2217,17 +2461,17 @@ pub fn vcgtd_u64(a: u64, b: u64) -> u64 { } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgth_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcgth_f16(a: f16, b: f16) -> u16 { - unsafe { simd_extract!(vcgt_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) } + vget_lane_u16::<0>(vcgt_f16(vdup_n_f16(a), vdup_n_f16(b))) } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2237,7 +2481,7 @@ pub fn vcgtz_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2247,7 +2491,7 @@ pub fn vcgtzq_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2257,7 +2501,7 @@ pub fn vcgtz_f64(a: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2267,7 +2511,7 @@ pub fn vcgtzq_f64(a: float64x2_t) -> uint64x2_t { } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2277,7 +2521,7 @@ pub fn vcgtz_s8(a: int8x8_t) -> uint8x8_t { } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2287,7 +2531,7 @@ pub fn vcgtzq_s8(a: int8x16_t) -> uint8x16_t { } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2297,7 +2541,7 @@ pub fn vcgtz_s16(a: int16x4_t) -> uint16x4_t { } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2307,7 +2551,7 @@ pub fn vcgtzq_s16(a: int16x8_t) -> uint16x8_t { } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2317,7 +2561,7 @@ pub fn vcgtz_s32(a: int32x2_t) -> uint32x2_t { } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2327,7 +2571,7 @@ pub fn vcgtzq_s32(a: int32x4_t) -> uint32x4_t { } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2337,7 +2581,7 @@ pub fn vcgtz_s64(a: int64x1_t) -> uint64x1_t { } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2347,25 +2591,25 @@ pub fn vcgtzq_s64(a: int64x2_t) -> uint64x2_t { } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcgtzd_f64(a: f64) -> u64 { - unsafe { simd_extract!(vcgtz_f64(vdup_n_f64(a)), 0) } + vget_lane_u64::<0>(vcgtz_f64(vdup_n_f64(a))) } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzs_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcgtzs_f32(a: f32) -> u32 { - unsafe { simd_extract!(vcgtz_f32(vdup_n_f32(a)), 0) } + vget_lane_u32::<0>(vcgtz_f32(vdup_n_f32(a))) } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2374,17 +2618,17 @@ pub fn vcgtzd_s64(a: i64) -> u64 { } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcgtzh_f16(a: f16) -> u16 { - unsafe { simd_extract!(vcgtz_f16(vdup_n_f16(a)), 0) } + vget_lane_u16::<0>(vcgtz_f16(vdup_n_f16(a))) } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2393,7 +2637,7 @@ pub fn vcle_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2402,7 +2646,7 @@ pub fn vcleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2411,7 +2655,7 @@ pub fn vcle_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2420,7 +2664,7 @@ pub fn vcleq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2429,7 +2673,7 @@ pub fn vcle_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2438,25 +2682,25 @@ pub fn vcleq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcled_f64(a: f64, b: f64) -> u64 { - unsafe { simd_extract!(vcle_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } + vget_lane_u64::<0>(vcle_f64(vdup_n_f64(a), vdup_n_f64(b))) } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcles_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcles_f32(a: f32, b: f32) -> u32 { - unsafe { simd_extract!(vcle_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } + vget_lane_u32::<0>(vcle_f32(vdup_n_f32(a), vdup_n_f32(b))) } #[doc = "Compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2465,7 +2709,7 @@ pub fn vcled_u64(a: u64, b: u64) -> u64 { } #[doc = "Compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2474,17 +2718,17 @@ pub fn vcled_s64(a: i64, b: i64) -> u64 { } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcleh_f16(a: f16, b: f16) -> u16 { - unsafe { simd_extract!(vcle_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) } + vget_lane_u16::<0>(vcle_f16(vdup_n_f16(a), vdup_n_f16(b))) } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2494,7 +2738,7 @@ pub fn vclez_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2504,7 +2748,7 @@ pub fn vclezq_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2514,7 +2758,7 @@ pub fn vclez_f64(a: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2524,7 +2768,7 @@ pub fn vclezq_f64(a: float64x2_t) -> uint64x2_t { } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2534,7 +2778,7 @@ pub fn vclez_s8(a: int8x8_t) -> uint8x8_t { } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2544,7 +2788,7 @@ pub fn vclezq_s8(a: int8x16_t) -> uint8x16_t { } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2554,7 +2798,7 @@ pub fn vclez_s16(a: int16x4_t) -> uint16x4_t { } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2564,7 +2808,7 @@ pub fn vclezq_s16(a: int16x8_t) -> uint16x8_t { } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2574,7 +2818,7 @@ pub fn vclez_s32(a: int32x2_t) -> uint32x2_t { } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2584,7 +2828,7 @@ pub fn vclezq_s32(a: int32x4_t) -> uint32x4_t { } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2594,7 +2838,7 @@ pub fn vclez_s64(a: int64x1_t) -> uint64x1_t { } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2604,25 +2848,25 @@ pub fn vclezq_s64(a: int64x2_t) -> uint64x2_t { } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vclezd_f64(a: f64) -> u64 { - unsafe { simd_extract!(vclez_f64(vdup_n_f64(a)), 0) } + vget_lane_u64::<0>(vclez_f64(vdup_n_f64(a))) } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezs_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vclezs_f32(a: f32) -> u32 { - unsafe { simd_extract!(vclez_f32(vdup_n_f32(a)), 0) } + vget_lane_u32::<0>(vclez_f32(vdup_n_f32(a))) } #[doc = "Compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2631,17 +2875,17 @@ pub fn vclezd_s64(a: i64) -> u64 { } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vclezh_f16(a: f16) -> u16 { - unsafe { simd_extract!(vclez_f16(vdup_n_f16(a)), 0) } + vget_lane_u16::<0>(vclez_f16(vdup_n_f16(a))) } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2650,7 +2894,7 @@ pub fn vclt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2659,7 +2903,7 @@ pub fn vcltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2668,7 +2912,7 @@ pub fn vclt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2677,7 +2921,7 @@ pub fn vcltq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhi))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2686,7 +2930,7 @@ pub fn vclt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhi))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2695,7 +2939,7 @@ pub fn vcltq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2704,7 +2948,7 @@ pub fn vcltd_u64(a: u64, b: u64) -> u64 { } #[doc = "Compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2713,35 +2957,35 @@ pub fn vcltd_s64(a: i64, b: i64) -> u64 { } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclth_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vclth_f16(a: f16, b: f16) -> u16 { - unsafe { simd_extract!(vclt_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) } + vget_lane_u16::<0>(vclt_f16(vdup_n_f16(a), vdup_n_f16(b))) } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclts_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vclts_f32(a: f32, b: f32) -> u32 { - unsafe { simd_extract!(vclt_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } + vget_lane_u32::<0>(vclt_f32(vdup_n_f32(a), vdup_n_f32(b))) } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcltd_f64(a: f64, b: f64) -> u64 { - unsafe { simd_extract!(vclt_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } + vget_lane_u64::<0>(vclt_f64(vdup_n_f64(a), vdup_n_f64(b))) } #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2751,7 +2995,7 @@ pub fn vcltz_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2761,7 +3005,7 @@ pub fn vcltzq_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2771,7 +3015,7 @@ pub fn vcltz_f64(a: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2781,7 +3025,7 @@ pub fn vcltzq_f64(a: float64x2_t) -> uint64x2_t { } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2791,7 +3035,7 @@ pub fn vcltz_s8(a: int8x8_t) -> uint8x8_t { } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2801,7 +3045,7 @@ pub fn vcltzq_s8(a: int8x16_t) -> uint8x16_t { } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2811,7 +3055,7 @@ pub fn vcltz_s16(a: int16x4_t) -> uint16x4_t { } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2821,7 +3065,7 @@ pub fn vcltzq_s16(a: int16x8_t) -> uint16x8_t { } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2831,7 +3075,7 @@ pub fn vcltz_s32(a: int32x2_t) -> uint32x2_t { } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2841,7 +3085,7 @@ pub fn vcltzq_s32(a: int32x4_t) -> uint32x4_t { } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2851,7 +3095,7 @@ pub fn vcltz_s64(a: int64x1_t) -> uint64x1_t { } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2861,25 +3105,25 @@ pub fn vcltzq_s64(a: int64x2_t) -> uint64x2_t { } #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcltzd_f64(a: f64) -> u64 { - unsafe { simd_extract!(vcltz_f64(vdup_n_f64(a)), 0) } + vget_lane_u64::<0>(vcltz_f64(vdup_n_f64(a))) } #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzs_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcltzs_f32(a: f32) -> u32 { - unsafe { simd_extract!(vcltz_f32(vdup_n_f32(a)), 0) } + vget_lane_u32::<0>(vcltz_f32(vdup_n_f32(a))) } #[doc = "Compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(asr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2888,17 +3132,18 @@ pub fn vcltzd_s64(a: i64) -> u64 { } #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcltzh_f16(a: f16) -> u16 { - unsafe { simd_extract!(vcltz_f16(vdup_n_f16(a)), 0) } + vget_lane_u16::<0>(vcltz_f16(vdup_n_f16(a))) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] @@ -2915,42 +3160,118 @@ pub fn vcmla_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t unsafe { _vcmla_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fcmla))] -pub fn vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { +pub fn vcmla_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vcmla.rot0.v8f16" + link_name = "llvm.aarch64.neon.vcmla.rot0.v4f16" )] - fn _vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t; + fn _vcmla_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t; + } + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: float16x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: float16x4_t = _vcmla_f16(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } - unsafe { _vcmlaq_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] +#[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fcmla))] -pub fn vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { +pub fn vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vcmla.rot0.v2f32" + link_name = "llvm.aarch64.neon.vcmla.rot0.v8f16" )] - fn _vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; + fn _vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t; + } + unsafe { _vcmlaq_f16(a, b, c) } +} +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot0.v8f16" + )] + fn _vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t; + } + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let c: float16x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = _vcmlaq_f16(a, b, c); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f32)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot0.v2f32" + )] + fn _vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; } unsafe { _vcmla_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot0.v2f32" + )] + fn _vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let c: float32x2_t = simd_shuffle!(c, c, [1, 0]); + let ret_val: float32x2_t = _vcmla_f32(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] @@ -2965,8 +3286,32 @@ pub fn vcmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t unsafe { _vcmlaq_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot0.v4f32" + )] + fn _vcmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t; + } + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: float32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: float32x4_t = _vcmlaq_f32(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] @@ -2981,8 +3326,31 @@ pub fn vcmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t unsafe { _vcmlaq_f64(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot0.v2f64" + )] + fn _vcmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let c: float64x2_t = simd_shuffle!(c, c, [1, 0]); + let ret_val: float64x2_t = _vcmlaq_f64(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_lane_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -2995,23 +3363,14 @@ pub fn vcmla_lane_f16( c: float16x4_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_f16(a, b, c) - } + let c = vreinterpret_u32_f16(c); + let c = vdup_lane_u32::(c); + let c = vreinterpret_f16_u32(c); + vcmla_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_lane_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3024,27 +3383,14 @@ pub fn vcmlaq_lane_f16( c: float16x4_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_f16(a, b, c) - } + let c = vreinterpret_u32_f16(c); + let c = vdupq_lane_u32::(c); + let c = vreinterpretq_f16_u32(c); + vcmlaq_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3055,14 +3401,14 @@ pub fn vcmla_lane_f32( c: float32x2_t, ) -> float32x2_t { static_assert!(LANE == 0); - unsafe { - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_f32(a, b, c) - } + let c = vreinterpret_u64_f32(c); + let c = vdup_lane_u64::(c); + let c = vreinterpret_f32_u64(c); + vcmla_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3073,23 +3419,14 @@ pub fn vcmlaq_lane_f32( c: float32x2_t, ) -> float32x4_t { static_assert!(LANE == 0); - unsafe { - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_f32(a, b, c) - } + let c = vreinterpret_u64_f32(c); + let c = vdupq_lane_u64::(c); + let c = vreinterpretq_f32_u64(c); + vcmlaq_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_laneq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3102,23 +3439,14 @@ pub fn vcmla_laneq_f16( c: float16x8_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_f16(a, b, c) - } + let c = vreinterpretq_u32_f16(c); + let c = vdup_laneq_u32::(c); + let c = vreinterpret_f16_u32(c); + vcmla_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_laneq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3131,27 +3459,14 @@ pub fn vcmlaq_laneq_f16( c: float16x8_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_f16(a, b, c) - } + let c = vreinterpretq_u32_f16(c); + let c = vdupq_laneq_u32::(c); + let c = vreinterpretq_f16_u32(c); + vcmlaq_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3162,14 +3477,14 @@ pub fn vcmla_laneq_f32( c: float32x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_f32(a, b, c) - } + let c = vreinterpretq_u64_f32(c); + let c = vdup_laneq_u64::(c); + let c = vreinterpret_f32_u64(c); + vcmla_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3180,23 +3495,15 @@ pub fn vcmlaq_laneq_f32( c: float32x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_f32(a, b, c) - } + let c = vreinterpretq_u64_f32(c); + let c = vdupq_laneq_u64::(c); + let c = vreinterpretq_f32_u64(c); + vcmlaq_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] @@ -3213,8 +3520,34 @@ pub fn vcmla_rot180_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float unsafe { _vcmla_rot180_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmla_rot180_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot180.v4f16" + )] + fn _vcmla_rot180_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t; + } + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: float16x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: float16x4_t = _vcmla_rot180_f16(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] @@ -3231,8 +3564,34 @@ pub fn vcmlaq_rot180_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> floa unsafe { _vcmlaq_rot180_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_rot180_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot180.v8f16" + )] + fn _vcmlaq_rot180_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t; + } + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let c: float16x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = _vcmlaq_rot180_f16(a, b, c); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] @@ -3247,8 +3606,32 @@ pub fn vcmla_rot180_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float unsafe { _vcmla_rot180_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmla_rot180_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot180.v2f32" + )] + fn _vcmla_rot180_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let c: float32x2_t = simd_shuffle!(c, c, [1, 0]); + let ret_val: float32x2_t = _vcmla_rot180_f32(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] @@ -3263,8 +3646,32 @@ pub fn vcmlaq_rot180_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> floa unsafe { _vcmlaq_rot180_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_rot180_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot180.v4f32" + )] + fn _vcmlaq_rot180_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t; + } + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: float32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: float32x4_t = _vcmlaq_rot180_f32(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] @@ -3279,8 +3686,31 @@ pub fn vcmlaq_rot180_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> floa unsafe { _vcmlaq_rot180_f64(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_rot180_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot180.v2f64" + )] + fn _vcmlaq_rot180_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let c: float64x2_t = simd_shuffle!(c, c, [1, 0]); + let ret_val: float64x2_t = _vcmlaq_rot180_f64(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_lane_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3293,23 +3723,14 @@ pub fn vcmla_rot180_lane_f16( c: float16x4_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_rot180_f16(a, b, c) - } + let c = vreinterpret_u32_f16(c); + let c = vdup_lane_u32::(c); + let c = vreinterpret_f16_u32(c); + vcmla_rot180_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_lane_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3322,27 +3743,14 @@ pub fn vcmlaq_rot180_lane_f16( c: float16x4_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot180_f16(a, b, c) - } + let c = vreinterpret_u32_f16(c); + let c = vdupq_lane_u32::(c); + let c = vreinterpretq_f16_u32(c); + vcmlaq_rot180_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3353,14 +3761,14 @@ pub fn vcmla_rot180_lane_f32( c: float32x2_t, ) -> float32x2_t { static_assert!(LANE == 0); - unsafe { - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot180_f32(a, b, c) - } + let c = vreinterpret_u64_f32(c); + let c = vdup_lane_u64::(c); + let c = vreinterpret_f32_u64(c); + vcmla_rot180_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3371,23 +3779,14 @@ pub fn vcmlaq_rot180_lane_f32( c: float32x2_t, ) -> float32x4_t { static_assert!(LANE == 0); - unsafe { - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot180_f32(a, b, c) - } + let c = vreinterpret_u64_f32(c); + let c = vdupq_lane_u64::(c); + let c = vreinterpretq_f32_u64(c); + vcmlaq_rot180_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_laneq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3400,23 +3799,14 @@ pub fn vcmla_rot180_laneq_f16( c: float16x8_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_rot180_f16(a, b, c) - } + let c = vreinterpretq_u32_f16(c); + let c = vdup_laneq_u32::(c); + let c = vreinterpret_f16_u32(c); + vcmla_rot180_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_laneq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3429,27 +3819,14 @@ pub fn vcmlaq_rot180_laneq_f16( c: float16x8_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot180_f16(a, b, c) - } + let c = vreinterpretq_u32_f16(c); + let c = vdupq_laneq_u32::(c); + let c = vreinterpretq_f16_u32(c); + vcmlaq_rot180_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3460,14 +3837,14 @@ pub fn vcmla_rot180_laneq_f32( c: float32x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot180_f32(a, b, c) - } + let c = vreinterpretq_u64_f32(c); + let c = vdup_laneq_u64::(c); + let c = vreinterpret_f32_u64(c); + vcmla_rot180_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3478,23 +3855,15 @@ pub fn vcmlaq_rot180_laneq_f32( c: float32x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot180_f32(a, b, c) - } + let c = vreinterpretq_u64_f32(c); + let c = vdupq_laneq_u64::(c); + let c = vreinterpretq_f32_u64(c); + vcmlaq_rot180_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] @@ -3511,8 +3880,34 @@ pub fn vcmla_rot270_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float unsafe { _vcmla_rot270_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmla_rot270_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot270.v4f16" + )] + fn _vcmla_rot270_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t; + } + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: float16x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: float16x4_t = _vcmla_rot270_f16(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] @@ -3529,8 +3924,34 @@ pub fn vcmlaq_rot270_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> floa unsafe { _vcmlaq_rot270_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_rot270_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot270.v8f16" + )] + fn _vcmlaq_rot270_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t; + } + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let c: float16x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = _vcmlaq_rot270_f16(a, b, c); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] @@ -3545,8 +3966,32 @@ pub fn vcmla_rot270_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float unsafe { _vcmla_rot270_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmla_rot270_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot270.v2f32" + )] + fn _vcmla_rot270_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let c: float32x2_t = simd_shuffle!(c, c, [1, 0]); + let ret_val: float32x2_t = _vcmla_rot270_f32(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] @@ -3561,8 +4006,32 @@ pub fn vcmlaq_rot270_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> floa unsafe { _vcmlaq_rot270_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_rot270_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot270.v4f32" + )] + fn _vcmlaq_rot270_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t; + } + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: float32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: float32x4_t = _vcmlaq_rot270_f32(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] @@ -3577,8 +4046,31 @@ pub fn vcmlaq_rot270_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> floa unsafe { _vcmlaq_rot270_f64(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_rot270_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot270.v2f64" + )] + fn _vcmlaq_rot270_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let c: float64x2_t = simd_shuffle!(c, c, [1, 0]); + let ret_val: float64x2_t = _vcmlaq_rot270_f64(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_lane_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3591,23 +4083,14 @@ pub fn vcmla_rot270_lane_f16( c: float16x4_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_rot270_f16(a, b, c) - } + let c = vreinterpret_u32_f16(c); + let c = vdup_lane_u32::(c); + let c = vreinterpret_f16_u32(c); + vcmla_rot270_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_lane_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3620,27 +4103,14 @@ pub fn vcmlaq_rot270_lane_f16( c: float16x4_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot270_f16(a, b, c) - } + let c = vreinterpret_u32_f16(c); + let c = vdupq_lane_u32::(c); + let c = vreinterpretq_f16_u32(c); + vcmlaq_rot270_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3651,14 +4121,14 @@ pub fn vcmla_rot270_lane_f32( c: float32x2_t, ) -> float32x2_t { static_assert!(LANE == 0); - unsafe { - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot270_f32(a, b, c) - } + let c = vreinterpret_u64_f32(c); + let c = vdup_lane_u64::(c); + let c = vreinterpret_f32_u64(c); + vcmla_rot270_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3669,23 +4139,14 @@ pub fn vcmlaq_rot270_lane_f32( c: float32x2_t, ) -> float32x4_t { static_assert!(LANE == 0); - unsafe { - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot270_f32(a, b, c) - } + let c = vreinterpret_u64_f32(c); + let c = vdupq_lane_u64::(c); + let c = vreinterpretq_f32_u64(c); + vcmlaq_rot270_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_laneq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3698,23 +4159,14 @@ pub fn vcmla_rot270_laneq_f16( c: float16x8_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_rot270_f16(a, b, c) - } + let c = vreinterpretq_u32_f16(c); + let c = vdup_laneq_u32::(c); + let c = vreinterpret_f16_u32(c); + vcmla_rot270_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_laneq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3727,27 +4179,14 @@ pub fn vcmlaq_rot270_laneq_f16( c: float16x8_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot270_f16(a, b, c) - } + let c = vreinterpretq_u32_f16(c); + let c = vdupq_laneq_u32::(c); + let c = vreinterpretq_f16_u32(c); + vcmlaq_rot270_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3758,14 +4197,14 @@ pub fn vcmla_rot270_laneq_f32( c: float32x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot270_f32(a, b, c) - } + let c = vreinterpretq_u64_f32(c); + let c = vdup_laneq_u64::(c); + let c = vreinterpret_f32_u64(c); + vcmla_rot270_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3776,23 +4215,15 @@ pub fn vcmlaq_rot270_laneq_f32( c: float32x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot270_f32(a, b, c) - } + let c = vreinterpretq_u64_f32(c); + let c = vdupq_laneq_u64::(c); + let c = vreinterpretq_f32_u64(c); + vcmlaq_rot270_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] @@ -3809,8 +4240,34 @@ pub fn vcmla_rot90_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float1 unsafe { _vcmla_rot90_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmla_rot90_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot90.v4f16" + )] + fn _vcmla_rot90_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t; + } + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: float16x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: float16x4_t = _vcmla_rot90_f16(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] @@ -3827,8 +4284,34 @@ pub fn vcmlaq_rot90_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float unsafe { _vcmlaq_rot90_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_rot90_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot90.v8f16" + )] + fn _vcmlaq_rot90_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t; + } + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let c: float16x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = _vcmlaq_rot90_f16(a, b, c); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] @@ -3843,8 +4326,32 @@ pub fn vcmla_rot90_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float3 unsafe { _vcmla_rot90_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmla_rot90_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot90.v2f32" + )] + fn _vcmla_rot90_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let c: float32x2_t = simd_shuffle!(c, c, [1, 0]); + let ret_val: float32x2_t = _vcmla_rot90_f32(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] @@ -3859,8 +4366,32 @@ pub fn vcmlaq_rot90_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float unsafe { _vcmlaq_rot90_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_rot90_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot90.v4f32" + )] + fn _vcmlaq_rot90_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t; + } + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: float32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: float32x4_t = _vcmlaq_rot90_f32(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] @@ -3875,8 +4406,31 @@ pub fn vcmlaq_rot90_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float unsafe { _vcmlaq_rot90_f64(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_rot90_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot90.v2f64" + )] + fn _vcmlaq_rot90_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let c: float64x2_t = simd_shuffle!(c, c, [1, 0]); + let ret_val: float64x2_t = _vcmlaq_rot90_f64(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_lane_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3889,23 +4443,14 @@ pub fn vcmla_rot90_lane_f16( c: float16x4_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_rot90_f16(a, b, c) - } + let c = vreinterpret_u32_f16(c); + let c = vdup_lane_u32::(c); + let c = vreinterpret_f16_u32(c); + vcmla_rot90_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_lane_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3918,27 +4463,14 @@ pub fn vcmlaq_rot90_lane_f16( c: float16x4_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot90_f16(a, b, c) - } + let c = vreinterpret_u32_f16(c); + let c = vdupq_lane_u32::(c); + let c = vreinterpretq_f16_u32(c); + vcmlaq_rot90_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3949,14 +4481,14 @@ pub fn vcmla_rot90_lane_f32( c: float32x2_t, ) -> float32x2_t { static_assert!(LANE == 0); - unsafe { - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot90_f32(a, b, c) - } + let c = vreinterpret_u64_f32(c); + let c = vdup_lane_u64::(c); + let c = vreinterpret_f32_u64(c); + vcmla_rot90_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3967,23 +4499,14 @@ pub fn vcmlaq_rot90_lane_f32( c: float32x2_t, ) -> float32x4_t { static_assert!(LANE == 0); - unsafe { - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot90_f32(a, b, c) - } + let c = vreinterpret_u64_f32(c); + let c = vdupq_lane_u64::(c); + let c = vreinterpretq_f32_u64(c); + vcmlaq_rot90_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_laneq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3996,23 +4519,14 @@ pub fn vcmla_rot90_laneq_f16( c: float16x8_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_rot90_f16(a, b, c) - } + let c = vreinterpretq_u32_f16(c); + let c = vdup_laneq_u32::(c); + let c = vreinterpret_f16_u32(c); + vcmla_rot90_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_laneq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -4025,27 +4539,14 @@ pub fn vcmlaq_rot90_laneq_f16( c: float16x8_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot90_f16(a, b, c) - } + let c = vreinterpretq_u32_f16(c); + let c = vdupq_laneq_u32::(c); + let c = vreinterpretq_f16_u32(c); + vcmlaq_rot90_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -4056,14 +4557,14 @@ pub fn vcmla_rot90_laneq_f32( c: float32x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot90_f32(a, b, c) - } + let c = vreinterpretq_u64_f32(c); + let c = vdup_laneq_u64::(c); + let c = vreinterpret_f32_u64(c); + vcmla_rot90_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -4074,25 +4575,42 @@ pub fn vcmlaq_rot90_laneq_f32( c: float32x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); + let c = vreinterpretq_u64_f32(c); + let c = vdupq_laneq_u64::(c); + let c = vreinterpretq_f32_u64(c); + vcmlaq_rot90_f32(a, b, c) +} +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f64)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(mov))] +pub fn vcombine_f64(a: float64x1_t, b: float64x1_t) -> float64x2_t { + unsafe { simd_shuffle!(a, b, [0, 1]) } +} +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(mov))] +pub fn vcombine_f64(a: float64x1_t, b: float64x1_t) -> float64x2_t { unsafe { - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot90_f32(a, b, c) + let ret_val: float64x2_t = simd_shuffle!(a, b, [0, 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_f32( @@ -4101,105 +4619,76 @@ pub fn vcopy_lane_f32( ) -> float32x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 1); - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_f32::(vget_lane_f32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 3); - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_s8::(vget_lane_s8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 2); - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_s16::(vget_lane_s16::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 1); - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_s32::(vget_lane_s32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 3); - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_u8::(vget_lane_u8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_u16( @@ -4208,21 +4697,16 @@ pub fn vcopy_lane_u16( ) -> uint16x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 2); - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_u16::(vget_lane_u16::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_u32( @@ -4231,43 +4715,31 @@ pub fn vcopy_lane_u32( ) -> uint32x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 1); - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_u32::(vget_lane_u32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 3); - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_p8::(vget_lane_p8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_p16( @@ -4276,21 +4748,76 @@ pub fn vcopy_lane_p16( ) -> poly16x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 2); - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_p16::(vget_lane_p16::(b), a) +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 0))] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopy_lane_f64( + _a: float64x1_t, + b: float64x1_t, +) -> float64x1_t { + static_assert!(LANE1 == 0); + static_assert!(LANE2 == 0); + b +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 0))] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopy_lane_s64( + _a: int64x1_t, + b: int64x1_t, +) -> int64x1_t { + static_assert!(LANE1 == 0); + static_assert!(LANE2 == 0); + b +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 0))] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopy_lane_u64( + _a: uint64x1_t, + b: uint64x1_t, +) -> uint64x1_t { + static_assert!(LANE1 == 0); + static_assert!(LANE2 == 0); + b +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 0))] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopy_lane_p64( + _a: poly64x1_t, + b: poly64x1_t, +) -> poly64x1_t { + static_assert!(LANE1 == 0); + static_assert!(LANE2 == 0); + b } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_f32( @@ -4299,46 +4826,31 @@ pub fn vcopy_laneq_f32( ) -> float32x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 2); - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }; - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_f32::(vgetq_lane_f32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_s8(a: int8x8_t, b: int8x16_t) -> int8x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 4); - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }; - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_s8::(vgetq_lane_s8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_s16( @@ -4347,22 +4859,16 @@ pub fn vcopy_laneq_s16( ) -> int16x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 3); - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }; - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_s16::(vgetq_lane_s16::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_s32( @@ -4371,20 +4877,16 @@ pub fn vcopy_laneq_s32( ) -> int32x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 2); - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }; - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_s32::(vgetq_lane_s32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_u8( @@ -4393,27 +4895,16 @@ pub fn vcopy_laneq_u8( ) -> uint8x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 4); - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }; - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_u8::(vgetq_lane_u8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_u16( @@ -4422,22 +4913,16 @@ pub fn vcopy_laneq_u16( ) -> uint16x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 3); - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }; - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_u16::(vgetq_lane_u16::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_u32( @@ -4446,20 +4931,16 @@ pub fn vcopy_laneq_u32( ) -> uint32x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 2); - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }; - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_u32::(vgetq_lane_u32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_p8( @@ -4468,27 +4949,16 @@ pub fn vcopy_laneq_p8( ) -> poly8x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 4); - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }; - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_p8::(vgetq_lane_p8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_p16( @@ -4497,20 +4967,71 @@ pub fn vcopy_laneq_p16( ) -> poly16x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 3); - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }; - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_p16::(vgetq_lane_p16::(b), a) +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopy_laneq_f64( + _a: float64x1_t, + b: float64x2_t, +) -> float64x1_t { + static_assert!(LANE1 == 0); + static_assert_uimm_bits!(LANE2, 1); + unsafe { transmute(vgetq_lane_f64::(b)) } +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopy_laneq_s64( + _a: int64x1_t, + b: int64x2_t, +) -> int64x1_t { + static_assert!(LANE1 == 0); + static_assert_uimm_bits!(LANE2, 1); + unsafe { transmute(vgetq_lane_s64::(b)) } +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopy_laneq_u64( + _a: uint64x1_t, + b: uint64x2_t, +) -> uint64x1_t { + static_assert!(LANE1 == 0); + static_assert_uimm_bits!(LANE2, 1); + unsafe { transmute(vgetq_lane_u64::(b)) } +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopy_laneq_p64( + _a: poly64x1_t, + b: poly64x2_t, +) -> poly64x1_t { + static_assert!(LANE1 == 0); + static_assert_uimm_bits!(LANE2, 1); + unsafe { transmute(vgetq_lane_p64::(b)) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] @@ -4521,22 +5042,16 @@ pub fn vcopyq_lane_f32( ) -> float32x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 1); - let b: float32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) }; - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vsetq_lane_f32::(vget_lane_f32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 1, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_f64( @@ -4545,20 +5060,17 @@ pub fn vcopyq_lane_f64( ) -> float64x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert!(LANE2 == 0); - let b: float64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) }; - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + let b: float64x2_t = vcombine_f64(b, b); + vsetq_lane_f64::(vgetq_lane_f64::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 1, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_s64( @@ -4567,20 +5079,17 @@ pub fn vcopyq_lane_s64( ) -> int64x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert!(LANE2 == 0); - let b: int64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) }; - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + let b: int64x2_t = vcombine_s64(b, b); + vsetq_lane_s64::(vgetq_lane_s64::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 1, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_u64( @@ -4589,20 +5098,38 @@ pub fn vcopyq_lane_u64( ) -> uint64x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert!(LANE2 == 0); - let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) }; - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + let b: uint64x2_t = vcombine_u64(b, b); + vsetq_lane_u64::(vgetq_lane_u64::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 1, LANE2 = 0) +)] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopyq_lane_p64( + a: poly64x2_t, + b: poly64x1_t, +) -> poly64x2_t { + static_assert_uimm_bits!(LANE1, 1); + static_assert!(LANE2 == 0); + let b: poly64x2_t = vcombine_p64(b, b); + unsafe { simd_insert!(a, LANE1 as u32, simd_extract!(b, LANE2 as u32, p64)) } +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 1, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_p64( @@ -4611,390 +5138,38 @@ pub fn vcopyq_lane_p64( ) -> poly64x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert!(LANE2 == 0); - let b: poly64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) }; unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: poly64x2_t = vcombine_p64(b, b); + let ret_val: poly64x2_t = + simd_insert!(a, LANE1 as u32, simd_extract!(b, LANE2 as u32, p64)); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_s8(a: int8x16_t, b: int8x8_t) -> int8x16_t { static_assert_uimm_bits!(LANE1, 4); static_assert_uimm_bits!(LANE2, 3); - let b: int8x16_t = - unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }; - unsafe { - match LANE1 & 0b1111 { - 0 => simd_shuffle!( - a, - b, - [ - 16 + LANE2 as u32, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 1 => simd_shuffle!( - a, - b, - [ - 0, - 16 + LANE2 as u32, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 2 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 16 + LANE2 as u32, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 3 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 16 + LANE2 as u32, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 4 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 16 + LANE2 as u32, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 5 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 16 + LANE2 as u32, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 6 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 16 + LANE2 as u32, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 7 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 16 + LANE2 as u32, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 8 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 16 + LANE2 as u32, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 9 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 16 + LANE2 as u32, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 10 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 16 + LANE2 as u32, - 11, - 12, - 13, - 14, - 15 - ] - ), - 11 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 16 + LANE2 as u32, - 12, - 13, - 14, - 15 - ] - ), - 12 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 16 + LANE2 as u32, - 13, - 14, - 15 - ] - ), - 13 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 16 + LANE2 as u32, - 14, - 15 - ] - ), - 14 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 16 + LANE2 as u32, - 15 - ] - ), - 15 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 16 + LANE2 as u32 - ] - ), - _ => unreachable_unchecked(), - } - } + let b: int8x16_t = vcombine_s8(b, b); + vsetq_lane_s8::(vgetq_lane_s8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_s16( @@ -5003,26 +5178,17 @@ pub fn vcopyq_lane_s16( ) -> int16x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 2); - let b: int16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) }; - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + let b: int16x8_t = vcombine_s16(b, b); + vsetq_lane_s16::(vgetq_lane_s16::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_s32( @@ -5031,22 +5197,17 @@ pub fn vcopyq_lane_s32( ) -> int32x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 1); - let b: int32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) }; - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + let b: int32x4_t = vcombine_s32(b, b); + vsetq_lane_s32::(vgetq_lane_s32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_u8( @@ -5055,371 +5216,17 @@ pub fn vcopyq_lane_u8( ) -> uint8x16_t { static_assert_uimm_bits!(LANE1, 4); static_assert_uimm_bits!(LANE2, 3); - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }; - unsafe { - match LANE1 & 0b1111 { - 0 => simd_shuffle!( - a, - b, - [ - 16 + LANE2 as u32, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 1 => simd_shuffle!( - a, - b, - [ - 0, - 16 + LANE2 as u32, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 2 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 16 + LANE2 as u32, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 3 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 16 + LANE2 as u32, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 4 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 16 + LANE2 as u32, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 5 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 16 + LANE2 as u32, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 6 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 16 + LANE2 as u32, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 7 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 16 + LANE2 as u32, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 8 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 16 + LANE2 as u32, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 9 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 16 + LANE2 as u32, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 10 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 16 + LANE2 as u32, - 11, - 12, - 13, - 14, - 15 - ] - ), - 11 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 16 + LANE2 as u32, - 12, - 13, - 14, - 15 - ] - ), - 12 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 16 + LANE2 as u32, - 13, - 14, - 15 - ] - ), - 13 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 16 + LANE2 as u32, - 14, - 15 - ] - ), - 14 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 16 + LANE2 as u32, - 15 - ] - ), - 15 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 16 + LANE2 as u32 - ] - ), - _ => unreachable_unchecked(), - } - } + let b: uint8x16_t = vcombine_u8(b, b); + vsetq_lane_u8::(vgetq_lane_u8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_u16( @@ -5428,26 +5235,17 @@ pub fn vcopyq_lane_u16( ) -> uint16x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 2); - let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) }; - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + let b: uint16x8_t = vcombine_u16(b, b); + vsetq_lane_u16::(vgetq_lane_u16::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_u32( @@ -5456,22 +5254,17 @@ pub fn vcopyq_lane_u32( ) -> uint32x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 1); - let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) }; - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + let b: uint32x4_t = vcombine_u32(b, b); + vsetq_lane_u32::(vgetq_lane_u32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_p8( @@ -5480,371 +5273,17 @@ pub fn vcopyq_lane_p8( ) -> poly8x16_t { static_assert_uimm_bits!(LANE1, 4); static_assert_uimm_bits!(LANE2, 3); - let b: poly8x16_t = - unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }; - unsafe { - match LANE1 & 0b1111 { - 0 => simd_shuffle!( - a, - b, - [ - 16 + LANE2 as u32, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 1 => simd_shuffle!( - a, - b, - [ - 0, - 16 + LANE2 as u32, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 2 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 16 + LANE2 as u32, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 3 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 16 + LANE2 as u32, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 4 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 16 + LANE2 as u32, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 5 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 16 + LANE2 as u32, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 6 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 16 + LANE2 as u32, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 7 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 16 + LANE2 as u32, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 8 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 16 + LANE2 as u32, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 9 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 16 + LANE2 as u32, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 10 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 16 + LANE2 as u32, - 11, - 12, - 13, - 14, - 15 - ] - ), - 11 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 16 + LANE2 as u32, - 12, - 13, - 14, - 15 - ] - ), - 12 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 16 + LANE2 as u32, - 13, - 14, - 15 - ] - ), - 13 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 16 + LANE2 as u32, - 14, - 15 - ] - ), - 14 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 16 + LANE2 as u32, - 15 - ] - ), - 15 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 16 + LANE2 as u32 - ] - ), - _ => unreachable_unchecked(), - } - } + let b: poly8x16_t = vcombine_p8(b, b); + vsetq_lane_p8::(vgetq_lane_p8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_p16( @@ -5853,26 +5292,17 @@ pub fn vcopyq_lane_p16( ) -> poly16x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 2); - let b: poly16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) }; - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + let b: poly16x8_t = vcombine_p16(b, b); + vsetq_lane_p16::(vgetq_lane_p16::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_f32( @@ -5881,21 +5311,16 @@ pub fn vcopyq_laneq_f32( ) -> float32x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 2); - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vsetq_lane_f32::(vgetq_lane_f32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_f64( @@ -5904,19 +5329,16 @@ pub fn vcopyq_laneq_f64( ) -> float64x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 1); - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vsetq_lane_f64::(vgetq_lane_f64::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_s8( @@ -5925,369 +5347,16 @@ pub fn vcopyq_laneq_s8( ) -> int8x16_t { static_assert_uimm_bits!(LANE1, 4); static_assert_uimm_bits!(LANE2, 4); - unsafe { - match LANE1 & 0b1111 { - 0 => simd_shuffle!( - a, - b, - [ - 16 + LANE2 as u32, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 1 => simd_shuffle!( - a, - b, - [ - 0, - 16 + LANE2 as u32, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 2 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 16 + LANE2 as u32, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 3 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 16 + LANE2 as u32, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 4 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 16 + LANE2 as u32, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 5 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 16 + LANE2 as u32, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 6 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 16 + LANE2 as u32, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 7 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 16 + LANE2 as u32, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 8 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 16 + LANE2 as u32, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 9 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 16 + LANE2 as u32, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 10 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 16 + LANE2 as u32, - 11, - 12, - 13, - 14, - 15 - ] - ), - 11 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 16 + LANE2 as u32, - 12, - 13, - 14, - 15 - ] - ), - 12 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 16 + LANE2 as u32, - 13, - 14, - 15 - ] - ), - 13 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 16 + LANE2 as u32, - 14, - 15 - ] - ), - 14 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 16 + LANE2 as u32, - 15 - ] - ), - 15 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 16 + LANE2 as u32 - ] - ), - _ => unreachable_unchecked(), - } - } + vsetq_lane_s8::(vgetq_lane_s8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_s16( @@ -6296,25 +5365,16 @@ pub fn vcopyq_laneq_s16( ) -> int16x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 3); - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vsetq_lane_s16::(vgetq_lane_s16::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_s32( @@ -6323,21 +5383,16 @@ pub fn vcopyq_laneq_s32( ) -> int32x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 2); - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vsetq_lane_s32::(vgetq_lane_s32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_s64( @@ -6346,19 +5401,16 @@ pub fn vcopyq_laneq_s64( ) -> int64x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 1); - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vsetq_lane_s64::(vgetq_lane_s64::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_u8( @@ -6367,369 +5419,16 @@ pub fn vcopyq_laneq_u8( ) -> uint8x16_t { static_assert_uimm_bits!(LANE1, 4); static_assert_uimm_bits!(LANE2, 4); - unsafe { - match LANE1 & 0b1111 { - 0 => simd_shuffle!( - a, - b, - [ - 16 + LANE2 as u32, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 1 => simd_shuffle!( - a, - b, - [ - 0, - 16 + LANE2 as u32, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 2 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 16 + LANE2 as u32, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 3 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 16 + LANE2 as u32, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 4 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 16 + LANE2 as u32, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 5 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 16 + LANE2 as u32, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 6 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 16 + LANE2 as u32, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 7 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 16 + LANE2 as u32, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 8 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 16 + LANE2 as u32, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 9 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 16 + LANE2 as u32, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 10 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 16 + LANE2 as u32, - 11, - 12, - 13, - 14, - 15 - ] - ), - 11 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 16 + LANE2 as u32, - 12, - 13, - 14, - 15 - ] - ), - 12 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 16 + LANE2 as u32, - 13, - 14, - 15 - ] - ), - 13 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 16 + LANE2 as u32, - 14, - 15 - ] - ), - 14 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 16 + LANE2 as u32, - 15 - ] - ), - 15 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 16 + LANE2 as u32 - ] - ), - _ => unreachable_unchecked(), - } - } + vsetq_lane_u8::(vgetq_lane_u8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_u16( @@ -6738,25 +5437,16 @@ pub fn vcopyq_laneq_u16( ) -> uint16x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 3); - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vsetq_lane_u16::(vgetq_lane_u16::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_u32( @@ -6765,21 +5455,16 @@ pub fn vcopyq_laneq_u32( ) -> uint32x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 2); - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vsetq_lane_u32::(vgetq_lane_u32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_u64( @@ -6788,19 +5473,16 @@ pub fn vcopyq_laneq_u64( ) -> uint64x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 1); - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vsetq_lane_u64::(vgetq_lane_u64::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_p8( @@ -6809,369 +5491,16 @@ pub fn vcopyq_laneq_p8( ) -> poly8x16_t { static_assert_uimm_bits!(LANE1, 4); static_assert_uimm_bits!(LANE2, 4); - unsafe { - match LANE1 & 0b1111 { - 0 => simd_shuffle!( - a, - b, - [ - 16 + LANE2 as u32, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 1 => simd_shuffle!( - a, - b, - [ - 0, - 16 + LANE2 as u32, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 2 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 16 + LANE2 as u32, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 3 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 16 + LANE2 as u32, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 4 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 16 + LANE2 as u32, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 5 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 16 + LANE2 as u32, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 6 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 16 + LANE2 as u32, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 7 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 16 + LANE2 as u32, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 8 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 16 + LANE2 as u32, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 9 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 16 + LANE2 as u32, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 10 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 16 + LANE2 as u32, - 11, - 12, - 13, - 14, - 15 - ] - ), - 11 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 16 + LANE2 as u32, - 12, - 13, - 14, - 15 - ] - ), - 12 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 16 + LANE2 as u32, - 13, - 14, - 15 - ] - ), - 13 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 16 + LANE2 as u32, - 14, - 15 - ] - ), - 14 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 16 + LANE2 as u32, - 15 - ] - ), - 15 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 16 + LANE2 as u32 - ] - ), - _ => unreachable_unchecked(), - } - } + vsetq_lane_p8::(vgetq_lane_p8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_p16( @@ -7180,25 +5509,36 @@ pub fn vcopyq_laneq_p16( ) -> poly16x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 3); - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vsetq_lane_p16::(vgetq_lane_p16::(b), a) +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p64)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopyq_laneq_p64( + a: poly64x2_t, + b: poly64x2_t, +) -> poly64x2_t { + static_assert_uimm_bits!(LANE1, 1); + static_assert_uimm_bits!(LANE2, 1); + unsafe { simd_insert!(a, LANE1 as u32, simd_extract!(b, LANE2 as u32, p64)) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_p64( @@ -7208,16 +5548,16 @@ pub fn vcopyq_laneq_p64( static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 1); unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: poly64x2_t = + simd_insert!(a, LANE1 as u32, simd_extract!(b, LANE2 as u32, p64)); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7226,16 +5566,16 @@ pub fn vcreate_f64(a: u64) -> float64x1_t { } #[doc = "Floating-point convert"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtn))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcvt_f32_f64(a: float64x2_t) -> float32x2_t { unsafe { simd_cast(a) } } #[doc = "Floating-point convert to higher precision long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7244,7 +5584,7 @@ pub fn vcvt_f64_f32(a: float32x2_t) -> float64x2_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7253,7 +5593,7 @@ pub fn vcvt_f64_s64(a: int64x1_t) -> float64x1_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7262,7 +5602,7 @@ pub fn vcvtq_f64_s64(a: int64x2_t) -> float64x2_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7271,7 +5611,7 @@ pub fn vcvt_f64_u64(a: uint64x1_t) -> float64x1_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7280,48 +5620,45 @@ pub fn vcvtq_f64_u64(a: uint64x2_t) -> float64x2_t { } #[doc = "Floating-point convert to lower precision"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f16_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtn2))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtn2))] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t { vcombine_f16(a, vcvt_f16_f32(b)) } #[doc = "Floating-point convert to higher precision"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtl2))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtl2))] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvt_high_f32_f16(a: float16x8_t) -> float32x4_t { vcvt_f32_f16(vget_high_f16(a)) } #[doc = "Floating-point convert to lower precision narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t { - unsafe { simd_shuffle!(a, simd_cast(b), [0, 1, 2, 3]) } + vcombine_f32(a, vcvt_f32_f64(b)) } #[doc = "Floating-point convert to higher precision long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f64_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcvt_high_f64_f32(a: float32x4_t) -> float64x2_t { - unsafe { - let b: float32x2_t = simd_shuffle!(a, a, [2, 3]); - simd_cast(b) - } + unsafe { simd_cast(vget_high_f32(a)) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f64_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] @@ -7339,7 +5676,7 @@ pub fn vcvt_n_f64_s64(a: int64x1_t) -> float64x1_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f64_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] @@ -7357,7 +5694,7 @@ pub fn vcvtq_n_f64_s64(a: int64x2_t) -> float64x2_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f64_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] @@ -7375,7 +5712,7 @@ pub fn vcvt_n_f64_u64(a: uint64x1_t) -> float64x1_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f64_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] @@ -7393,7 +5730,7 @@ pub fn vcvtq_n_f64_u64(a: uint64x2_t) -> float64x2_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] @@ -7411,7 +5748,7 @@ pub fn vcvt_n_s64_f64(a: float64x1_t) -> int64x1_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] @@ -7429,7 +5766,7 @@ pub fn vcvtq_n_s64_f64(a: float64x2_t) -> int64x2_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] @@ -7447,7 +5784,7 @@ pub fn vcvt_n_u64_f64(a: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] @@ -7465,7 +5802,7 @@ pub fn vcvtq_n_u64_f64(a: float64x2_t) -> uint64x2_t { } #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7481,7 +5818,7 @@ pub fn vcvt_s64_f64(a: float64x1_t) -> int64x1_t { } #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7497,7 +5834,7 @@ pub fn vcvtq_s64_f64(a: float64x2_t) -> int64x2_t { } #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7513,7 +5850,7 @@ pub fn vcvt_u64_f64(a: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7529,10 +5866,10 @@ pub fn vcvtq_u64_f64(a: float64x2_t) -> uint64x2_t { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtas))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvta_s16_f16(a: float16x4_t) -> int16x4_t { unsafe extern "unadjusted" { @@ -7546,10 +5883,10 @@ pub fn vcvta_s16_f16(a: float16x4_t) -> int16x4_t { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtas))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtaq_s16_f16(a: float16x8_t) -> int16x8_t { unsafe extern "unadjusted" { @@ -7563,7 +5900,7 @@ pub fn vcvtaq_s16_f16(a: float16x8_t) -> int16x8_t { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7579,7 +5916,7 @@ pub fn vcvta_s32_f32(a: float32x2_t) -> int32x2_t { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7595,7 +5932,7 @@ pub fn vcvtaq_s32_f32(a: float32x4_t) -> int32x4_t { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7611,7 +5948,7 @@ pub fn vcvta_s64_f64(a: float64x1_t) -> int64x1_t { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7627,10 +5964,10 @@ pub fn vcvtaq_s64_f64(a: float64x2_t) -> int64x2_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtau))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvta_u16_f16(a: float16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { @@ -7644,10 +5981,10 @@ pub fn vcvta_u16_f16(a: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtau))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtaq_u16_f16(a: float16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { @@ -7661,7 +5998,7 @@ pub fn vcvtaq_u16_f16(a: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7677,7 +6014,7 @@ pub fn vcvta_u32_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7693,7 +6030,7 @@ pub fn vcvtaq_u32_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7709,7 +6046,7 @@ pub fn vcvta_u64_f64(a: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7725,17 +6062,24 @@ pub fn vcvtaq_u64_f64(a: float64x2_t) -> uint64x2_t { } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtas))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtah_s16_f16(a: f16) -> i16 { - vcvtah_s32_f16(a) as i16 + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtas.i16.f16" + )] + fn _vcvtah_s16_f16(a: f16) -> i16; + } + unsafe { _vcvtah_s16_f16(a) } } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_s32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtas))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -7752,7 +6096,7 @@ pub fn vcvtah_s32_f16(a: f16) -> i32 { } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_s64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtas))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -7769,17 +6113,24 @@ pub fn vcvtah_s64_f16(a: f16) -> i64 { } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtau))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtah_u16_f16(a: f16) -> u16 { - vcvtah_u32_f16(a) as u16 + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtau.i16.f16" + )] + fn _vcvtah_u16_f16(a: f16) -> u16; + } + unsafe { _vcvtah_u16_f16(a) } } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_u32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtau))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -7796,7 +6147,7 @@ pub fn vcvtah_u32_f16(a: f16) -> u32 { } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_u64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtau))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -7813,7 +6164,7 @@ pub fn vcvtah_u64_f16(a: f16) -> u64 { } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtas_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7829,7 +6180,7 @@ pub fn vcvtas_s32_f32(a: f32) -> i32 { } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtad_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7845,7 +6196,7 @@ pub fn vcvtad_s64_f64(a: f64) -> i64 { } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtas_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7861,7 +6212,7 @@ pub fn vcvtas_u32_f32(a: f32) -> u32 { } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtad_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7877,7 +6228,7 @@ pub fn vcvtad_u64_f64(a: f64) -> u64 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_f64_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7886,7 +6237,7 @@ pub fn vcvtd_f64_s64(a: i64) -> f64 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_f32_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7895,7 +6246,7 @@ pub fn vcvts_f32_s32(a: i32) -> f32 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_s16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(scvtf))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -7905,7 +6256,7 @@ pub fn vcvth_f16_s16(a: i16) -> f16 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_s32)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(scvtf))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -7915,7 +6266,7 @@ pub fn vcvth_f16_s32(a: i32) -> f16 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_s64)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(scvtf))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -7925,7 +6276,7 @@ pub fn vcvth_f16_s64(a: i64) -> f16 { } #[doc = "Unsigned fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_u16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(ucvtf))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -7935,7 +6286,7 @@ pub fn vcvth_f16_u16(a: u16) -> f16 { } #[doc = "Unsigned fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_u32)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(ucvtf))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -7945,7 +6296,7 @@ pub fn vcvth_f16_u32(a: u32) -> f16 { } #[doc = "Unsigned fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_u64)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(ucvtf))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -7955,7 +6306,7 @@ pub fn vcvth_f16_u64(a: u64) -> f16 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -7967,7 +6318,7 @@ pub fn vcvth_n_f16_s16(a: i16) -> f16 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s32)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -7986,7 +6337,7 @@ pub fn vcvth_n_f16_s32(a: i32) -> f16 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s64)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -8005,7 +6356,7 @@ pub fn vcvth_n_f16_s64(a: i64) -> f16 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -8017,7 +6368,7 @@ pub fn vcvth_n_f16_u16(a: u16) -> f16 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u32)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -8036,7 +6387,7 @@ pub fn vcvth_n_f16_u32(a: u32) -> f16 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u64)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -8055,7 +6406,7 @@ pub fn vcvth_n_f16_u64(a: u64) -> f16 { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -8067,7 +6418,7 @@ pub fn vcvth_n_s16_f16(a: f16) -> i16 { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -8086,7 +6437,7 @@ pub fn vcvth_n_s32_f16(a: f16) -> i32 { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -8105,7 +6456,7 @@ pub fn vcvth_n_s64_f16(a: f16) -> i64 { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -8117,7 +6468,7 @@ pub fn vcvth_n_u16_f16(a: f16) -> u16 { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -8136,7 +6487,7 @@ pub fn vcvth_n_u32_f16(a: f16) -> u32 { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -8155,7 +6506,7 @@ pub fn vcvth_n_u64_f16(a: f16) -> u64 { } #[doc = "Floating-point convert to signed fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzs))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8165,7 +6516,7 @@ pub fn vcvth_s16_f16(a: f16) -> i16 { } #[doc = "Floating-point convert to signed fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_s32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzs))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8175,7 +6526,7 @@ pub fn vcvth_s32_f16(a: f16) -> i32 { } #[doc = "Floating-point convert to signed fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_s64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzs))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8185,7 +6536,7 @@ pub fn vcvth_s64_f16(a: f16) -> i64 { } #[doc = "Floating-point convert to unsigned fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8195,7 +6546,7 @@ pub fn vcvth_u16_f16(a: f16) -> u16 { } #[doc = "Floating-point convert to unsigned fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_u32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8205,7 +6556,7 @@ pub fn vcvth_u32_f16(a: f16) -> u32 { } #[doc = "Floating-point convert to unsigned fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_u64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8215,10 +6566,10 @@ pub fn vcvth_u64_f16(a: f16) -> u64 { } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtms))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtm_s16_f16(a: float16x4_t) -> int16x4_t { unsafe extern "unadjusted" { @@ -8232,10 +6583,10 @@ pub fn vcvtm_s16_f16(a: float16x4_t) -> int16x4_t { } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtms))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtmq_s16_f16(a: float16x8_t) -> int16x8_t { unsafe extern "unadjusted" { @@ -8249,7 +6600,7 @@ pub fn vcvtmq_s16_f16(a: float16x8_t) -> int16x8_t { } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8265,7 +6616,7 @@ pub fn vcvtm_s32_f32(a: float32x2_t) -> int32x2_t { } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8281,7 +6632,7 @@ pub fn vcvtmq_s32_f32(a: float32x4_t) -> int32x4_t { } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8297,7 +6648,7 @@ pub fn vcvtm_s64_f64(a: float64x1_t) -> int64x1_t { } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8313,10 +6664,10 @@ pub fn vcvtmq_s64_f64(a: float64x2_t) -> int64x2_t { } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtmu))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtm_u16_f16(a: float16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { @@ -8330,10 +6681,10 @@ pub fn vcvtm_u16_f16(a: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtmu))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtmq_u16_f16(a: float16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { @@ -8347,7 +6698,7 @@ pub fn vcvtmq_u16_f16(a: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8363,7 +6714,7 @@ pub fn vcvtm_u32_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8379,7 +6730,7 @@ pub fn vcvtmq_u32_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8395,7 +6746,7 @@ pub fn vcvtm_u64_f64(a: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8411,17 +6762,24 @@ pub fn vcvtmq_u64_f64(a: float64x2_t) -> uint64x2_t { } #[doc = "Floating-point convert to integer, rounding towards minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtms))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtmh_s16_f16(a: f16) -> i16 { - vcvtmh_s32_f16(a) as i16 + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtms.i16.f16" + )] + fn _vcvtmh_s16_f16(a: f16) -> i16; + } + unsafe { _vcvtmh_s16_f16(a) } } #[doc = "Floating-point convert to integer, rounding towards minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_s32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtms))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8438,7 +6796,7 @@ pub fn vcvtmh_s32_f16(a: f16) -> i32 { } #[doc = "Floating-point convert to integer, rounding towards minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_s64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtms))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8453,19 +6811,26 @@ pub fn vcvtmh_s64_f16(a: f16) -> i64 { } unsafe { _vcvtmh_s64_f16(a) } } -#[doc = "Floating-point convert to integer, rounding towards minus infinity"] +#[doc = "Floating-point convert to unsigned integer, rounding towards minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtmu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtmh_u16_f16(a: f16) -> u16 { - vcvtmh_u32_f16(a) as u16 + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtmu.i16.f16" + )] + fn _vcvtmh_u16_f16(a: f16) -> u16; + } + unsafe { _vcvtmh_u16_f16(a) } } #[doc = "Floating-point convert to unsigned integer, rounding towards minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_u32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtmu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8482,7 +6847,7 @@ pub fn vcvtmh_u32_f16(a: f16) -> u32 { } #[doc = "Floating-point convert to unsigned integer, rounding towards minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_u64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtmu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8499,7 +6864,7 @@ pub fn vcvtmh_u64_f16(a: f16) -> u64 { } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtms_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8515,7 +6880,7 @@ pub fn vcvtms_s32_f32(a: f32) -> i32 { } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmd_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8531,7 +6896,7 @@ pub fn vcvtmd_s64_f64(a: f64) -> i64 { } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtms_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8547,7 +6912,7 @@ pub fn vcvtms_u32_f32(a: f32) -> u32 { } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmd_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8563,10 +6928,10 @@ pub fn vcvtmd_u64_f64(a: f64) -> u64 { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtns))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtn_s16_f16(a: float16x4_t) -> int16x4_t { unsafe extern "unadjusted" { @@ -8580,10 +6945,10 @@ pub fn vcvtn_s16_f16(a: float16x4_t) -> int16x4_t { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtns))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtnq_s16_f16(a: float16x8_t) -> int16x8_t { unsafe extern "unadjusted" { @@ -8597,7 +6962,7 @@ pub fn vcvtnq_s16_f16(a: float16x8_t) -> int16x8_t { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8613,7 +6978,7 @@ pub fn vcvtn_s32_f32(a: float32x2_t) -> int32x2_t { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8629,7 +6994,7 @@ pub fn vcvtnq_s32_f32(a: float32x4_t) -> int32x4_t { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8645,7 +7010,7 @@ pub fn vcvtn_s64_f64(a: float64x1_t) -> int64x1_t { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8661,10 +7026,10 @@ pub fn vcvtnq_s64_f64(a: float64x2_t) -> int64x2_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtnu))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtn_u16_f16(a: float16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { @@ -8678,10 +7043,10 @@ pub fn vcvtn_u16_f16(a: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtnu))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtnq_u16_f16(a: float16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { @@ -8695,7 +7060,7 @@ pub fn vcvtnq_u16_f16(a: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8711,7 +7076,7 @@ pub fn vcvtn_u32_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8727,7 +7092,7 @@ pub fn vcvtnq_u32_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8743,7 +7108,7 @@ pub fn vcvtn_u64_f64(a: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8759,17 +7124,24 @@ pub fn vcvtnq_u64_f64(a: float64x2_t) -> uint64x2_t { } #[doc = "Floating-point convert to integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtns))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtnh_s16_f16(a: f16) -> i16 { - vcvtnh_s32_f16(a) as i16 + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtns.i16.f16" + )] + fn _vcvtnh_s16_f16(a: f16) -> i16; + } + unsafe { _vcvtnh_s16_f16(a) } } #[doc = "Floating-point convert to integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_s32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtns))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8786,7 +7158,7 @@ pub fn vcvtnh_s32_f16(a: f16) -> i32 { } #[doc = "Floating-point convert to integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_s64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtns))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8803,17 +7175,24 @@ pub fn vcvtnh_s64_f16(a: f16) -> i64 { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtnu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtnh_u16_f16(a: f16) -> u16 { - vcvtnh_u32_f16(a) as u16 + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtnu.i16.f16" + )] + fn _vcvtnh_u16_f16(a: f16) -> u16; + } + unsafe { _vcvtnh_u16_f16(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_u32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtnu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8830,7 +7209,7 @@ pub fn vcvtnh_u32_f16(a: f16) -> u32 { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_u64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtnu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8847,7 +7226,7 @@ pub fn vcvtnh_u64_f16(a: f16) -> u64 { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtns_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8863,7 +7242,7 @@ pub fn vcvtns_s32_f32(a: f32) -> i32 { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnd_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8879,7 +7258,7 @@ pub fn vcvtnd_s64_f64(a: f64) -> i64 { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtns_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8895,7 +7274,7 @@ pub fn vcvtns_u32_f32(a: f32) -> u32 { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnd_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8911,10 +7290,10 @@ pub fn vcvtnd_u64_f64(a: f64) -> u64 { } #[doc = "Floating-point convert to signed integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtps))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtp_s16_f16(a: float16x4_t) -> int16x4_t { unsafe extern "unadjusted" { @@ -8928,10 +7307,10 @@ pub fn vcvtp_s16_f16(a: float16x4_t) -> int16x4_t { } #[doc = "Floating-point convert to signed integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtps))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtpq_s16_f16(a: float16x8_t) -> int16x8_t { unsafe extern "unadjusted" { @@ -8945,7 +7324,7 @@ pub fn vcvtpq_s16_f16(a: float16x8_t) -> int16x8_t { } #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8961,7 +7340,7 @@ pub fn vcvtp_s32_f32(a: float32x2_t) -> int32x2_t { } #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8977,7 +7356,7 @@ pub fn vcvtpq_s32_f32(a: float32x4_t) -> int32x4_t { } #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8993,7 +7372,7 @@ pub fn vcvtp_s64_f64(a: float64x1_t) -> int64x1_t { } #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9009,10 +7388,10 @@ pub fn vcvtpq_s64_f64(a: float64x2_t) -> int64x2_t { } #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtpu))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtp_u16_f16(a: float16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { @@ -9026,10 +7405,10 @@ pub fn vcvtp_u16_f16(a: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtpu))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtpq_u16_f16(a: float16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { @@ -9043,7 +7422,7 @@ pub fn vcvtpq_u16_f16(a: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9059,7 +7438,7 @@ pub fn vcvtp_u32_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9075,7 +7454,7 @@ pub fn vcvtpq_u32_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9091,7 +7470,7 @@ pub fn vcvtp_u64_f64(a: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9107,17 +7486,24 @@ pub fn vcvtpq_u64_f64(a: float64x2_t) -> uint64x2_t { } #[doc = "Floating-point convert to integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtps))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtph_s16_f16(a: f16) -> i16 { - vcvtph_s32_f16(a) as i16 + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtps.i16.f16" + )] + fn _vcvtph_s16_f16(a: f16) -> i16; + } + unsafe { _vcvtph_s16_f16(a) } } #[doc = "Floating-point convert to integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_s32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtps))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -9134,7 +7520,7 @@ pub fn vcvtph_s32_f16(a: f16) -> i32 { } #[doc = "Floating-point convert to integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_s64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtps))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -9151,17 +7537,24 @@ pub fn vcvtph_s64_f16(a: f16) -> i64 { } #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtpu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtph_u16_f16(a: f16) -> u16 { - vcvtph_u32_f16(a) as u16 + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtpu.i16.f16" + )] + fn _vcvtph_u16_f16(a: f16) -> u16; + } + unsafe { _vcvtph_u16_f16(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtpu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -9178,7 +7571,7 @@ pub fn vcvtph_u32_f16(a: f16) -> u32 { } #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtpu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -9195,7 +7588,7 @@ pub fn vcvtph_u64_f16(a: f16) -> u64 { } #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtps_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9211,7 +7604,7 @@ pub fn vcvtps_s32_f32(a: f32) -> i32 { } #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpd_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9227,7 +7620,7 @@ pub fn vcvtpd_s64_f64(a: f64) -> i64 { } #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtps_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9243,7 +7636,7 @@ pub fn vcvtps_u32_f32(a: f32) -> u32 { } #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpd_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9259,7 +7652,7 @@ pub fn vcvtpd_u64_f64(a: f64) -> u64 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_f32_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9268,7 +7661,7 @@ pub fn vcvts_f32_u32(a: u32) -> f32 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_f64_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9277,7 +7670,7 @@ pub fn vcvtd_f64_u64(a: u64) -> f64 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_f32_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] @@ -9295,7 +7688,7 @@ pub fn vcvts_n_f32_s32(a: i32) -> f32 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_f64_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] @@ -9313,7 +7706,7 @@ pub fn vcvtd_n_f64_s64(a: i64) -> f64 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_f32_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] @@ -9331,7 +7724,7 @@ pub fn vcvts_n_f32_u32(a: u32) -> f32 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_f64_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] @@ -9349,7 +7742,7 @@ pub fn vcvtd_n_f64_u64(a: u64) -> f64 { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] @@ -9367,7 +7760,7 @@ pub fn vcvts_n_s32_f32(a: f32) -> i32 { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] @@ -9385,7 +7778,7 @@ pub fn vcvtd_n_s64_f64(a: f64) -> i64 { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] @@ -9403,7 +7796,7 @@ pub fn vcvts_n_u32_f32(a: f32) -> u32 { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] @@ -9421,7 +7814,7 @@ pub fn vcvtd_n_u64_f64(a: f64) -> u64 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9430,7 +7823,7 @@ pub fn vcvts_s32_f32(a: f32) -> i32 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9439,7 +7832,7 @@ pub fn vcvtd_s64_f64(a: f64) -> i64 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9448,7 +7841,7 @@ pub fn vcvts_u32_f32(a: f32) -> u32 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9457,9 +7850,9 @@ pub fn vcvtd_u64_f64(a: f64) -> u64 { } #[doc = "Floating-point convert to lower precision narrow, rounding to odd"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_f32_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtxn))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtxn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t { unsafe extern "unadjusted" { @@ -9473,27 +7866,27 @@ pub fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t { } #[doc = "Floating-point convert to lower precision narrow, rounding to odd"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_high_f32_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtxn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtxn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcvtx_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t { - unsafe { simd_shuffle!(a, vcvtx_f32_f64(b), [0, 1, 2, 3]) } + vcombine_f32(a, vcvtx_f32_f64(b)) } #[doc = "Floating-point convert to lower precision narrow, rounding to odd"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtxd_f32_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtxn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcvtxd_f32_f64(a: f64) -> f32 { - unsafe { simd_extract!(vcvtx_f32_f64(vdupq_n_f64(a)), 0) } + vget_lane_f32::<0>(vcvtx_f32_f64(vdupq_n_f64(a))) } #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fdiv))] pub fn vdiv_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -9501,9 +7894,9 @@ pub fn vdiv_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { } #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fdiv))] pub fn vdivq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -9511,7 +7904,7 @@ pub fn vdivq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { } #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fdiv))] @@ -9520,7 +7913,7 @@ pub fn vdiv_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fdiv))] @@ -9529,7 +7922,7 @@ pub fn vdivq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fdiv))] @@ -9538,7 +7931,7 @@ pub fn vdiv_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fdiv))] @@ -9547,7 +7940,7 @@ pub fn vdivq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -9557,7 +7950,7 @@ pub fn vdivh_f16(a: f16, b: f16) -> f16 { } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 0))] #[rustc_legacy_const_generics(1)] @@ -9568,7 +7961,7 @@ pub fn vdup_lane_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 0))] #[rustc_legacy_const_generics(1)] @@ -9579,161 +7972,161 @@ pub fn vdup_lane_p64(a: poly64x1_t) -> poly64x1_t { } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdup_laneq_f64(a: float64x2_t) -> float64x1_t { static_assert_uimm_bits!(N, 1); - unsafe { transmute::(simd_extract!(a, N as u32)) } + unsafe { transmute(vgetq_lane_f64::(a)) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdup_laneq_p64(a: poly64x2_t) -> poly64x1_t { static_assert_uimm_bits!(N, 1); - unsafe { transmute::(simd_extract!(a, N as u32)) } + unsafe { transmute(vgetq_lane_p64::(a)) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupb_lane_s8(a: int8x8_t) -> i8 { static_assert_uimm_bits!(N, 3); - unsafe { simd_extract!(a, N as u32) } + vget_lane_s8::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vduph_laneq_s16(a: int16x8_t) -> i16 { static_assert_uimm_bits!(N, 3); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_s16::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupb_lane_u8(a: uint8x8_t) -> u8 { static_assert_uimm_bits!(N, 3); - unsafe { simd_extract!(a, N as u32) } + vget_lane_u8::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vduph_laneq_u16(a: uint16x8_t) -> u16 { static_assert_uimm_bits!(N, 3); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_u16::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupb_lane_p8(a: poly8x8_t) -> p8 { static_assert_uimm_bits!(N, 3); - unsafe { simd_extract!(a, N as u32) } + vget_lane_p8::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vduph_laneq_p16(a: poly16x8_t) -> p16 { static_assert_uimm_bits!(N, 3); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_p16::(a) } #[doc = "Extract an element from a vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 8))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupb_laneq_s8(a: int8x16_t) -> i8 { static_assert_uimm_bits!(N, 4); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_s8::(a) } #[doc = "Extract an element from a vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 8))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupb_laneq_u8(a: uint8x16_t) -> u8 { static_assert_uimm_bits!(N, 4); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_u8::(a) } #[doc = "Extract an element from a vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 8))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupb_laneq_p8(a: poly8x16_t) -> p8 { static_assert_uimm_bits!(N, 4); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_p8::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 0))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupd_lane_f64(a: float64x1_t) -> f64 { static_assert!(N == 0); - unsafe { simd_extract!(a, N as u32) } + vget_lane_f64::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 0))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupd_lane_s64(a: int64x1_t) -> i64 { static_assert!(N == 0); - unsafe { simd_extract!(a, N as u32) } + vget_lane_s64::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 0))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupd_lane_u64(a: uint64x1_t) -> u64 { static_assert!(N == 0); - unsafe { simd_extract!(a, N as u32) } + vget_lane_u64::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -9741,11 +8134,11 @@ pub fn vdupd_lane_u64(a: uint64x1_t) -> u64 { #[cfg(not(target_arch = "arm64ec"))] pub fn vduph_lane_f16(a: float16x4_t) -> f16 { static_assert_uimm_bits!(N, 2); - unsafe { simd_extract!(a, N as u32) } + vget_lane_f16::(a) } #[doc = "Extract an element from a vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -9753,11 +8146,12 @@ pub fn vduph_lane_f16(a: float16x4_t) -> f16 { #[cfg(not(target_arch = "arm64ec"))] pub fn vduph_laneq_f16(a: float16x8_t) -> f16 { static_assert_uimm_bits!(N, 4); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_f16::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(dup, N = 0))] #[rustc_legacy_const_generics(1)] @@ -9767,8 +8161,24 @@ pub fn vdupq_lane_f64(a: float64x1_t) -> float64x2_t { unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(dup, N = 0))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vdupq_lane_f64(a: float64x1_t) -> float64x2_t { + static_assert!(N == 0); + unsafe { + let ret_val: float64x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(dup, N = 0))] #[rustc_legacy_const_generics(1)] @@ -9778,8 +8188,24 @@ pub fn vdupq_lane_p64(a: poly64x1_t) -> poly64x2_t { unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(dup, N = 0))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vdupq_lane_p64(a: poly64x1_t) -> poly64x2_t { + static_assert!(N == 0); + unsafe { + let ret_val: poly64x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(dup, N = 1))] #[rustc_legacy_const_generics(1)] @@ -9789,151 +8215,184 @@ pub fn vdupq_laneq_f64(a: float64x2_t) -> float64x2_t { unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(dup, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vdupq_laneq_p64(a: poly64x2_t) -> poly64x2_t { +pub fn vdupq_laneq_f64(a: float64x2_t) -> float64x2_t { static_assert_uimm_bits!(N, 1); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: float64x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 1))] +#[cfg_attr(test, assert_instr(dup, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vdups_lane_f32(a: float32x2_t) -> f32 { +pub fn vdupq_laneq_p64(a: poly64x2_t) -> poly64x2_t { static_assert_uimm_bits!(N, 1); - unsafe { simd_extract!(a, N as u32) } + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_f64)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(dup, N = 1))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vdupq_laneq_p64(a: poly64x2_t) -> poly64x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: poly64x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_f32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(nop, N = 1))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vdups_lane_f32(a: float32x2_t) -> f32 { + static_assert_uimm_bits!(N, 1); + vget_lane_f32::(a) +} +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_f64)"] +#[inline] +#[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupd_laneq_f64(a: float64x2_t) -> f64 { static_assert_uimm_bits!(N, 1); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_f64::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdups_lane_s32(a: int32x2_t) -> i32 { static_assert_uimm_bits!(N, 1); - unsafe { simd_extract!(a, N as u32) } + vget_lane_s32::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupd_laneq_s64(a: int64x2_t) -> i64 { static_assert_uimm_bits!(N, 1); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_s64::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdups_lane_u32(a: uint32x2_t) -> u32 { static_assert_uimm_bits!(N, 1); - unsafe { simd_extract!(a, N as u32) } + vget_lane_u32::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupd_laneq_u64(a: uint64x2_t) -> u64 { static_assert_uimm_bits!(N, 1); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_u64::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdups_laneq_f32(a: float32x4_t) -> f32 { static_assert_uimm_bits!(N, 2); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_f32::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vduph_lane_s16(a: int16x4_t) -> i16 { static_assert_uimm_bits!(N, 2); - unsafe { simd_extract!(a, N as u32) } + vget_lane_s16::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdups_laneq_s32(a: int32x4_t) -> i32 { static_assert_uimm_bits!(N, 2); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_s32::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vduph_lane_u16(a: uint16x4_t) -> u16 { static_assert_uimm_bits!(N, 2); - unsafe { simd_extract!(a, N as u32) } + vget_lane_u16::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdups_laneq_u32(a: uint32x4_t) -> u32 { static_assert_uimm_bits!(N, 2); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_u32::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vduph_lane_p16(a: poly16x4_t) -> p16 { static_assert_uimm_bits!(N, 2); - unsafe { simd_extract!(a, N as u32) } + vget_lane_p16::(a) } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] @@ -9949,7 +8408,7 @@ pub fn veor3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] @@ -9965,7 +8424,7 @@ pub fn veor3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] @@ -9981,7 +8440,7 @@ pub fn veor3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] @@ -9997,7 +8456,7 @@ pub fn veor3q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t { } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] @@ -10013,7 +8472,7 @@ pub fn veor3q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] @@ -10029,7 +8488,7 @@ pub fn veor3q_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] @@ -10045,7 +8504,7 @@ pub fn veor3q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] @@ -10061,7 +8520,20 @@ pub fn veor3q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(ext, N = 1))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vextq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1]) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ext, N = 1))] #[rustc_legacy_const_generics(2)] @@ -10069,16 +8541,28 @@ pub fn veor3q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { pub fn vextq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { static_assert_uimm_bits!(N, 1); unsafe { - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), - } + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = simd_shuffle!(a, b, [N as u32, N as u32 + 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(ext, N = 1))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vextq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1]) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ext, N = 1))] #[rustc_legacy_const_generics(2)] @@ -10086,16 +8570,15 @@ pub fn vextq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { pub fn vextq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { static_assert_uimm_bits!(N, 1); unsafe { - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), - } + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: poly64x2_t = simd_shuffle!(a, b, [N as u32, N as u32 + 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmadd))] @@ -10104,11 +8587,11 @@ pub fn vfma_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfma_lane_f16( a: float16x4_t, @@ -10116,15 +8599,15 @@ pub fn vfma_lane_f16( c: float16x4_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfma_f16(a, b, vdup_n_f16(simd_extract!(c, LANE as u32))) } + vfma_f16(a, b, vdup_n_f16(vget_lane_f16::(c))) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfma_laneq_f16( a: float16x4_t, @@ -10132,15 +8615,15 @@ pub fn vfma_laneq_f16( c: float16x8_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfma_f16(a, b, vdup_n_f16(simd_extract!(c, LANE as u32))) } + vfma_f16(a, b, vdup_n_f16(vgetq_lane_f16::(c))) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmaq_lane_f16( a: float16x8_t, @@ -10148,15 +8631,15 @@ pub fn vfmaq_lane_f16( c: float16x4_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmaq_f16(a, b, vdupq_n_f16(simd_extract!(c, LANE as u32))) } + vfmaq_f16(a, b, vdupq_n_f16(vget_lane_f16::(c))) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmaq_laneq_f16( a: float16x8_t, @@ -10164,11 +8647,11 @@ pub fn vfmaq_laneq_f16( c: float16x8_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfmaq_f16(a, b, vdupq_n_f16(simd_extract!(c, LANE as u32))) } + vfmaq_f16(a, b, vdupq_n_f16(vgetq_lane_f16::(c))) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10179,11 +8662,11 @@ pub fn vfma_lane_f32( c: float32x2_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vfma_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) } + vfma_f32(a, b, vdup_n_f32(vget_lane_f32::(c))) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10194,11 +8677,11 @@ pub fn vfma_laneq_f32( c: float32x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfma_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) } + vfma_f32(a, b, vdup_n_f32(vgetq_lane_f32::(c))) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10209,11 +8692,11 @@ pub fn vfmaq_lane_f32( c: float32x2_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vfmaq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) } + vfmaq_f32(a, b, vdupq_n_f32(vget_lane_f32::(c))) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10224,11 +8707,11 @@ pub fn vfmaq_laneq_f32( c: float32x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmaq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) } + vfmaq_f32(a, b, vdupq_n_f32(vgetq_lane_f32::(c))) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10239,11 +8722,11 @@ pub fn vfmaq_laneq_f64( c: float64x2_t, ) -> float64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vfmaq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) } + vfmaq_f64(a, b, vdupq_n_f64(vgetq_lane_f64::(c))) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10254,13 +8737,13 @@ pub fn vfma_lane_f64( c: float64x1_t, ) -> float64x1_t { static_assert!(LANE == 0); - unsafe { vfma_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) } + vfma_f64(a, b, vdup_n_f64(vget_lane_f64::(c))) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vfma_laneq_f64( @@ -10269,11 +8752,11 @@ pub fn vfma_laneq_f64( c: float64x2_t, ) -> float64x1_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vfma_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) } + vfma_f64(a, b, vdup_n_f64(vgetq_lane_f64::(c))) } #[doc = "Floating-point fused Multiply-Subtract from accumulator."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -10283,7 +8766,7 @@ pub fn vfma_n_f16(a: float16x4_t, b: float16x4_t, c: f16) -> float16x4_t { } #[doc = "Floating-point fused Multiply-Subtract from accumulator."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -10293,7 +8776,7 @@ pub fn vfmaq_n_f16(a: float16x8_t, b: float16x8_t, c: f16) -> float16x8_t { } #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmadd))] @@ -10302,21 +8785,19 @@ pub fn vfma_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t { } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vfmad_lane_f64(a: f64, b: f64, c: float64x1_t) -> f64 { static_assert!(LANE == 0); - unsafe { - let c: f64 = simd_extract!(c, LANE as u32); - fmaf64(b, c, a) - } + let c: f64 = vget_lane_f64::(c); + fmaf64(b, c, a) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmadd))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -10326,37 +8807,33 @@ pub fn vfmah_f16(a: f16, b: f16, c: f16) -> f16 { } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_lane_f16)"] -#[inline(always)] -#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] +#[inline] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmah_lane_f16(a: f16, b: f16, v: float16x4_t) -> f16 { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: f16 = simd_extract!(v, LANE as u32); - vfmah_f16(a, b, c) - } + let c: f16 = vget_lane_f16::(v); + vfmah_f16(a, b, c) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_laneq_f16)"] -#[inline(always)] -#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] +#[inline] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmah_laneq_f16(a: f16, b: f16, v: float16x8_t) -> f16 { static_assert_uimm_bits!(LANE, 3); - unsafe { - let c: f16 = simd_extract!(v, LANE as u32); - vfmah_f16(a, b, c) - } + let c: f16 = vgetq_lane_f16::(v); + vfmah_f16(a, b, c) } #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmla))] @@ -10365,7 +8842,7 @@ pub fn vfmaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10376,11 +8853,11 @@ pub fn vfmaq_lane_f64( c: float64x1_t, ) -> float64x2_t { static_assert!(LANE == 0); - unsafe { vfmaq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) } + vfmaq_f64(a, b, vdupq_n_f64(vget_lane_f64::(c))) } #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmla))] @@ -10389,52 +8866,47 @@ pub fn vfmaq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t { } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vfmas_lane_f32(a: f32, b: f32, c: float32x2_t) -> f32 { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: f32 = simd_extract!(c, LANE as u32); - fmaf32(b, c, a) - } + let c: f32 = vget_lane_f32::(c); + fmaf32(b, c, a) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vfmas_laneq_f32(a: f32, b: f32, c: float32x4_t) -> f32 { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: f32 = simd_extract!(c, LANE as u32); - fmaf32(b, c, a) - } + let c: f32 = vgetq_lane_f32::(c); + fmaf32(b, c, a) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vfmad_laneq_f64(a: f64, b: f64, c: float64x2_t) -> f64 { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: f64 = simd_extract!(c, LANE as u32); - fmaf64(b, c, a) - } + let c: f64 = vgetq_lane_f64::(c); + fmaf64(b, c, a) } #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_high_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlal2))] pub fn vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { @@ -10448,11 +8920,37 @@ pub fn vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float3 unsafe { _vfmlal_high_f16(r, a, b) } } #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_high_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmlal2))] +pub fn vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmlal2.v2f32.v4f16" + )] + fn _vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t; + } + unsafe { + let r: float32x2_t = simd_shuffle!(r, r, [1, 0]); + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x2_t = _vfmlal_high_f16(r, a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_high_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlal2))] pub fn vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { @@ -10465,14 +8963,39 @@ pub fn vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float } unsafe { _vfmlalq_high_f16(r, a, b) } } +#[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_high_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmlal2))] +pub fn vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmlal2.v4f32.v8f16" + )] + fn _vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t; + } + unsafe { + let r: float32x4_t = simd_shuffle!(r, r, [3, 2, 1, 0]); + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float32x4_t = _vfmlalq_high_f16(r, a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_lane_high_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlal_lane_high_f16( r: float32x2_t, @@ -10480,16 +9003,16 @@ pub fn vfmlal_lane_high_f16( b: float16x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmlal_high_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } + vfmlal_high_f16(r, a, vdup_lane_f16::(b)) } #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_laneq_high_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlal_laneq_high_f16( r: float32x2_t, @@ -10497,16 +9020,16 @@ pub fn vfmlal_laneq_high_f16( b: float16x8_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfmlal_high_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } + vfmlal_high_f16(r, a, vdup_laneq_f16::(b)) } #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_lane_high_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlalq_lane_high_f16( r: float32x4_t, @@ -10514,16 +9037,16 @@ pub fn vfmlalq_lane_high_f16( b: float16x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmlalq_high_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } + vfmlalq_high_f16(r, a, vdupq_lane_f16::(b)) } #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_laneq_high_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlalq_laneq_high_f16( r: float32x4_t, @@ -10531,16 +9054,16 @@ pub fn vfmlalq_laneq_high_f16( b: float16x8_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfmlalq_high_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } + vfmlalq_high_f16(r, a, vdupq_laneq_f16::(b)) } #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_lane_low_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlal, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlal_lane_low_f16( r: float32x2_t, @@ -10548,16 +9071,16 @@ pub fn vfmlal_lane_low_f16( b: float16x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmlal_low_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } + vfmlal_low_f16(r, a, vdup_lane_f16::(b)) } #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_laneq_low_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlal, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlal_laneq_low_f16( r: float32x2_t, @@ -10565,16 +9088,16 @@ pub fn vfmlal_laneq_low_f16( b: float16x8_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfmlal_low_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } + vfmlal_low_f16(r, a, vdup_laneq_f16::(b)) } #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_lane_low_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlal, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlalq_lane_low_f16( r: float32x4_t, @@ -10582,16 +9105,16 @@ pub fn vfmlalq_lane_low_f16( b: float16x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmlalq_low_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } + vfmlalq_low_f16(r, a, vdupq_lane_f16::(b)) } #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_laneq_low_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlal, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlalq_laneq_low_f16( r: float32x4_t, @@ -10599,14 +9122,15 @@ pub fn vfmlalq_laneq_low_f16( b: float16x8_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfmlalq_low_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } + vfmlalq_low_f16(r, a, vdupq_laneq_f16::(b)) } #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_low_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlal))] pub fn vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { @@ -10620,11 +9144,37 @@ pub fn vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32 unsafe { _vfmlal_low_f16(r, a, b) } } #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_low_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmlal))] +pub fn vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmlal.v2f32.v4f16" + )] + fn _vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t; + } + unsafe { + let r: float32x2_t = simd_shuffle!(r, r, [1, 0]); + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x2_t = _vfmlal_low_f16(r, a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_low_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlal))] pub fn vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { @@ -10637,12 +9187,38 @@ pub fn vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float3 } unsafe { _vfmlalq_low_f16(r, a, b) } } +#[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_low_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmlal))] +pub fn vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmlal.v4f32.v8f16" + )] + fn _vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t; + } + unsafe { + let r: float32x4_t = simd_shuffle!(r, r, [3, 2, 1, 0]); + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float32x4_t = _vfmlalq_low_f16(r, a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_high_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlsl2))] pub fn vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { @@ -10656,11 +9232,37 @@ pub fn vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float3 unsafe { _vfmlsl_high_f16(r, a, b) } } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_high_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmlsl2))] +pub fn vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmlsl2.v2f32.v4f16" + )] + fn _vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t; + } + unsafe { + let r: float32x2_t = simd_shuffle!(r, r, [1, 0]); + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x2_t = _vfmlsl_high_f16(r, a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_high_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlsl2))] pub fn vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { @@ -10673,14 +9275,39 @@ pub fn vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float } unsafe { _vfmlslq_high_f16(r, a, b) } } +#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_high_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmlsl2))] +pub fn vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmlsl2.v4f32.v8f16" + )] + fn _vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t; + } + unsafe { + let r: float32x4_t = simd_shuffle!(r, r, [3, 2, 1, 0]); + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float32x4_t = _vfmlslq_high_f16(r, a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_lane_high_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlsl_lane_high_f16( r: float32x2_t, @@ -10688,16 +9315,16 @@ pub fn vfmlsl_lane_high_f16( b: float16x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmlsl_high_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } + vfmlsl_high_f16(r, a, vdup_lane_f16::(b)) } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_laneq_high_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlsl_laneq_high_f16( r: float32x2_t, @@ -10705,16 +9332,16 @@ pub fn vfmlsl_laneq_high_f16( b: float16x8_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfmlsl_high_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } + vfmlsl_high_f16(r, a, vdup_laneq_f16::(b)) } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_lane_high_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlslq_lane_high_f16( r: float32x4_t, @@ -10722,16 +9349,16 @@ pub fn vfmlslq_lane_high_f16( b: float16x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmlslq_high_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } + vfmlslq_high_f16(r, a, vdupq_lane_f16::(b)) } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_laneq_high_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlslq_laneq_high_f16( r: float32x4_t, @@ -10739,16 +9366,16 @@ pub fn vfmlslq_laneq_high_f16( b: float16x8_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfmlslq_high_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } + vfmlslq_high_f16(r, a, vdupq_laneq_f16::(b)) } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_lane_low_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlsl_lane_low_f16( r: float32x2_t, @@ -10756,16 +9383,16 @@ pub fn vfmlsl_lane_low_f16( b: float16x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmlsl_low_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } + vfmlsl_low_f16(r, a, vdup_lane_f16::(b)) } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_laneq_low_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlsl_laneq_low_f16( r: float32x2_t, @@ -10773,16 +9400,16 @@ pub fn vfmlsl_laneq_low_f16( b: float16x8_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfmlsl_low_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } + vfmlsl_low_f16(r, a, vdup_laneq_f16::(b)) } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_lane_low_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlslq_lane_low_f16( r: float32x4_t, @@ -10790,16 +9417,16 @@ pub fn vfmlslq_lane_low_f16( b: float16x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmlslq_low_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } + vfmlslq_low_f16(r, a, vdupq_lane_f16::(b)) } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_laneq_low_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlslq_laneq_low_f16( r: float32x4_t, @@ -10807,14 +9434,15 @@ pub fn vfmlslq_laneq_low_f16( b: float16x8_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfmlslq_low_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } + vfmlslq_low_f16(r, a, vdupq_laneq_f16::(b)) } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_low_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlsl))] pub fn vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { @@ -10828,11 +9456,37 @@ pub fn vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32 unsafe { _vfmlsl_low_f16(r, a, b) } } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_low_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmlsl))] +pub fn vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmlsl.v2f32.v4f16" + )] + fn _vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t; + } + unsafe { + let r: float32x2_t = simd_shuffle!(r, r, [1, 0]); + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x2_t = _vfmlsl_low_f16(r, a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_low_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlsl))] pub fn vfmlslq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { @@ -10845,9 +9499,34 @@ pub fn vfmlslq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float3 } unsafe { _vfmlslq_low_f16(r, a, b) } } +#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_low_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmlsl))] +pub fn vfmlslq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmlsl.v4f32.v8f16" + )] + fn _vfmlslq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t; + } + unsafe { + let r: float32x4_t = simd_shuffle!(r, r, [3, 2, 1, 0]); + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float32x4_t = _vfmlslq_low_f16(r, a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmsub))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -10859,11 +9538,11 @@ pub fn vfms_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfms_lane_f16( a: float16x4_t, @@ -10871,15 +9550,15 @@ pub fn vfms_lane_f16( c: float16x4_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfms_f16(a, b, vdup_n_f16(simd_extract!(c, LANE as u32))) } + vfms_f16(a, b, vdup_n_f16(vget_lane_f16::(c))) } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfms_laneq_f16( a: float16x4_t, @@ -10887,15 +9566,15 @@ pub fn vfms_laneq_f16( c: float16x8_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfms_f16(a, b, vdup_n_f16(simd_extract!(c, LANE as u32))) } + vfms_f16(a, b, vdup_n_f16(vgetq_lane_f16::(c))) } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmsq_lane_f16( a: float16x8_t, @@ -10903,15 +9582,15 @@ pub fn vfmsq_lane_f16( c: float16x4_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmsq_f16(a, b, vdupq_n_f16(simd_extract!(c, LANE as u32))) } + vfmsq_f16(a, b, vdupq_n_f16(vget_lane_f16::(c))) } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmsq_laneq_f16( a: float16x8_t, @@ -10919,11 +9598,11 @@ pub fn vfmsq_laneq_f16( c: float16x8_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfmsq_f16(a, b, vdupq_n_f16(simd_extract!(c, LANE as u32))) } + vfmsq_f16(a, b, vdupq_n_f16(vgetq_lane_f16::(c))) } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10934,11 +9613,11 @@ pub fn vfms_lane_f32( c: float32x2_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vfms_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) } + vfms_f32(a, b, vdup_n_f32(vget_lane_f32::(c))) } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10949,11 +9628,11 @@ pub fn vfms_laneq_f32( c: float32x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfms_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) } + vfms_f32(a, b, vdup_n_f32(vgetq_lane_f32::(c))) } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10964,11 +9643,11 @@ pub fn vfmsq_lane_f32( c: float32x2_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vfmsq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) } + vfmsq_f32(a, b, vdupq_n_f32(vget_lane_f32::(c))) } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10979,11 +9658,11 @@ pub fn vfmsq_laneq_f32( c: float32x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmsq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) } + vfmsq_f32(a, b, vdupq_n_f32(vgetq_lane_f32::(c))) } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10994,11 +9673,11 @@ pub fn vfmsq_laneq_f64( c: float64x2_t, ) -> float64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vfmsq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) } + vfmsq_f64(a, b, vdupq_n_f64(vgetq_lane_f64::(c))) } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -11009,13 +9688,13 @@ pub fn vfms_lane_f64( c: float64x1_t, ) -> float64x1_t { static_assert!(LANE == 0); - unsafe { vfms_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) } + vfms_f64(a, b, vdup_n_f64(vget_lane_f64::(c))) } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vfms_laneq_f64( @@ -11024,11 +9703,11 @@ pub fn vfms_laneq_f64( c: float64x2_t, ) -> float64x1_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vfms_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) } + vfms_f64(a, b, vdup_n_f64(vgetq_lane_f64::(c))) } #[doc = "Floating-point fused Multiply-Subtract from accumulator."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -11038,7 +9717,7 @@ pub fn vfms_n_f16(a: float16x4_t, b: float16x4_t, c: f16) -> float16x4_t { } #[doc = "Floating-point fused Multiply-Subtract from accumulator."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -11048,7 +9727,7 @@ pub fn vfmsq_n_f16(a: float16x8_t, b: float16x8_t, c: f16) -> float16x8_t { } #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmsub))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11057,7 +9736,7 @@ pub fn vfms_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t { } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmsub))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -11067,37 +9746,33 @@ pub fn vfmsh_f16(a: f16, b: f16, c: f16) -> f16 { } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_lane_f16)"] -#[inline(always)] -#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[inline] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmsh_lane_f16(a: f16, b: f16, v: float16x4_t) -> f16 { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: f16 = simd_extract!(v, LANE as u32); - vfmsh_f16(a, b, c) - } + let c: f16 = vget_lane_f16::(v); + vfmsh_f16(a, b, c) } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_laneq_f16)"] -#[inline(always)] -#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[inline] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmsh_laneq_f16(a: f16, b: f16, v: float16x8_t) -> f16 { static_assert_uimm_bits!(LANE, 3); - unsafe { - let c: f16 = simd_extract!(v, LANE as u32); - vfmsh_f16(a, b, c) - } + let c: f16 = vgetq_lane_f16::(v); + vfmsh_f16(a, b, c) } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11109,7 +9784,7 @@ pub fn vfmsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -11120,11 +9795,11 @@ pub fn vfmsq_lane_f64( c: float64x1_t, ) -> float64x2_t { static_assert!(LANE == 0); - unsafe { vfmsq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) } + vfmsq_f64(a, b, vdupq_n_f64(vget_lane_f64::(c))) } #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11133,9 +9808,9 @@ pub fn vfmsq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t { } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vfmss_lane_f32(a: f32, b: f32, c: float32x2_t) -> f32 { @@ -11143,9 +9818,9 @@ pub fn vfmss_lane_f32(a: f32, b: f32, c: float32x2_t) -> f32 { } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vfmss_laneq_f32(a: f32, b: f32, c: float32x4_t) -> f32 { @@ -11153,9 +9828,9 @@ pub fn vfmss_laneq_f32(a: f32, b: f32, c: float32x4_t) -> f32 { } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vfmsd_lane_f64(a: f64, b: f64, c: float64x1_t) -> f64 { @@ -11163,31 +9838,104 @@ pub fn vfmsd_lane_f64(a: f64, b: f64, c: float64x1_t) -> f64 { } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vfmsd_laneq_f64(a: f64, b: f64, c: float64x2_t) -> f64 { vfmad_laneq_f64::(a, -b, c) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,fp16")] -#[cfg_attr(test, assert_instr(ldr))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t { - crate::ptr::read_unaligned(ptr.cast()) +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f64)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub fn vget_high_f64(a: float64x2_t) -> float64x1_t { + unsafe { float64x1_t([simd_extract!(a, 1)]) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"] -#[doc = "## Safety"] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub fn vget_high_f64(a: float64x2_t) -> float64x1_t { + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + float64x1_t([simd_extract!(a, 1)]) + } +} +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f64)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub fn vget_low_f64(a: float64x2_t) -> float64x1_t { + unsafe { float64x1_t([simd_extract!(a, 0)]) } +} +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub fn vget_low_f64(a: float64x2_t) -> float64x1_t { + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + float64x1_t([simd_extract!(a, 0)]) + } +} +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f64)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 0))] +pub fn vgetq_lane_f64(a: float64x2_t) -> f64 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { simd_extract!(a, IMM5 as u32) } +} +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 0))] +pub fn vgetq_lane_f64(a: float64x2_t) -> f64 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + simd_extract!(a, IMM5 as u32) + } +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(test, assert_instr(ldr))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t { + crate::ptr::read_unaligned(ptr.cast()) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"] +#[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(test, assert_instr(ldr))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -11199,7 +9947,7 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11210,7 +9958,7 @@ pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11221,7 +9969,7 @@ pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11232,7 +9980,7 @@ pub unsafe fn vld1_f64(ptr: *const f64) -> float64x1_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11243,7 +9991,7 @@ pub unsafe fn vld1q_f64(ptr: *const f64) -> float64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11254,7 +10002,7 @@ pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11265,7 +10013,7 @@ pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11276,7 +10024,7 @@ pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11287,7 +10035,7 @@ pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11298,7 +10046,7 @@ pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11309,7 +10057,7 @@ pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11320,7 +10068,7 @@ pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11331,7 +10079,7 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11342,7 +10090,7 @@ pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11353,7 +10101,7 @@ pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11364,7 +10112,7 @@ pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11375,7 +10123,7 @@ pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11386,7 +10134,7 @@ pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11397,7 +10145,7 @@ pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11408,7 +10156,7 @@ pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11419,7 +10167,7 @@ pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11430,7 +10178,7 @@ pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11441,7 +10189,7 @@ pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11452,7 +10200,7 @@ pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11463,7 +10211,7 @@ pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11474,7 +10222,7 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11485,115 +10233,73 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld1))] -pub unsafe fn vld1_f64_x2(a: *const f64) -> float64x1x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v1f64.p0" - )] - fn _vld1_f64_x2(a: *const f64) -> float64x1x2_t; - } - _vld1_f64_x2(a) +#[cfg_attr(test, assert_instr(ld))] +pub unsafe fn vld1_f64_x2(ptr: *const f64) -> float64x1x2_t { + crate::ptr::read_unaligned(ptr.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld1))] -pub unsafe fn vld1_f64_x3(a: *const f64) -> float64x1x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v1f64.p0" - )] - fn _vld1_f64_x3(a: *const f64) -> float64x1x3_t; - } - _vld1_f64_x3(a) +#[cfg_attr(test, assert_instr(ld))] +pub unsafe fn vld1_f64_x3(ptr: *const f64) -> float64x1x3_t { + crate::ptr::read_unaligned(ptr.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld1))] -pub unsafe fn vld1_f64_x4(a: *const f64) -> float64x1x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v1f64.p0" - )] - fn _vld1_f64_x4(a: *const f64) -> float64x1x4_t; - } - _vld1_f64_x4(a) +#[cfg_attr(test, assert_instr(ld))] +pub unsafe fn vld1_f64_x4(ptr: *const f64) -> float64x1x4_t { + crate::ptr::read_unaligned(ptr.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld1))] -pub unsafe fn vld1q_f64_x2(a: *const f64) -> float64x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v2f64.p0" - )] - fn _vld1q_f64_x2(a: *const f64) -> float64x2x2_t; - } - _vld1q_f64_x2(a) +#[cfg_attr(test, assert_instr(ld))] +pub unsafe fn vld1q_f64_x2(ptr: *const f64) -> float64x2x2_t { + crate::ptr::read_unaligned(ptr.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld1))] -pub unsafe fn vld1q_f64_x3(a: *const f64) -> float64x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v2f64.p0" - )] - fn _vld1q_f64_x3(a: *const f64) -> float64x2x3_t; - } - _vld1q_f64_x3(a) +#[cfg_attr(test, assert_instr(ld))] +pub unsafe fn vld1q_f64_x3(ptr: *const f64) -> float64x2x3_t { + crate::ptr::read_unaligned(ptr.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld1))] -pub unsafe fn vld1q_f64_x4(a: *const f64) -> float64x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v2f64.p0" - )] - fn _vld1q_f64_x4(a: *const f64) -> float64x2x4_t; - } - _vld1q_f64_x4(a) +#[cfg_attr(test, assert_instr(ld))] +pub unsafe fn vld1q_f64_x4(ptr: *const f64) -> float64x2x4_t { + crate::ptr::read_unaligned(ptr.cast()) } #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld2r))] @@ -11611,7 +10317,7 @@ pub unsafe fn vld2_dup_f64(a: *const f64) -> float64x1x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld2r))] @@ -11629,7 +10335,7 @@ pub unsafe fn vld2q_dup_f64(a: *const f64) -> float64x2x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld2r))] @@ -11647,25 +10353,18 @@ pub unsafe fn vld2q_dup_s64(a: *const i64) -> int64x2x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vld2_f64(a: *const f64) -> float64x1x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v1f64.p0" - )] - fn _vld2_f64(ptr: *const float64x1_t) -> float64x1x2_t; - } - _vld2_f64(a as _) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -11685,7 +10384,7 @@ pub unsafe fn vld2_lane_f64(a: *const f64, b: float64x1x2_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -11705,7 +10404,7 @@ pub unsafe fn vld2_lane_s64(a: *const i64, b: int64x1x2_t) -> i #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -11718,7 +10417,7 @@ pub unsafe fn vld2_lane_p64(a: *const p64, b: poly64x1x2_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -11731,8 +10430,7 @@ pub unsafe fn vld2_lane_u64(a: *const u64, b: uint64x1x2_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon,aes")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld2r))] @@ -11740,52 +10438,21 @@ pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t { transmute(vld2q_dup_s64(transmute(a))) } #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2r))] -pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t { - let mut ret_val: poly64x2x2_t = transmute(vld2q_dup_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val -} -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld2r))] pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t { transmute(vld2q_dup_s64(transmute(a))) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2r))] -pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t { - let mut ret_val: uint64x2x2_t = transmute(vld2q_dup_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val -} #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld2))] @@ -11803,7 +10470,7 @@ pub unsafe fn vld2q_f64(a: *const f64) -> float64x2x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld2))] @@ -11821,7 +10488,7 @@ pub unsafe fn vld2q_s64(a: *const i64) -> int64x2x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -11842,7 +10509,7 @@ pub unsafe fn vld2q_lane_f64(a: *const f64, b: float64x2x2_t) - #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -11862,7 +10529,7 @@ pub unsafe fn vld2q_lane_s8(a: *const i8, b: int8x16x2_t) -> in #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -11882,7 +10549,7 @@ pub unsafe fn vld2q_lane_s64(a: *const i64, b: int64x2x2_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -11895,7 +10562,7 @@ pub unsafe fn vld2q_lane_p64(a: *const p64, b: poly64x2x2_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -11908,7 +10575,7 @@ pub unsafe fn vld2q_lane_u8(a: *const u8, b: uint8x16x2_t) -> u #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -11921,7 +10588,7 @@ pub unsafe fn vld2q_lane_u64(a: *const u64, b: uint64x2x2_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -11934,8 +10601,7 @@ pub unsafe fn vld2q_lane_p8(a: *const p8, b: poly8x16x2_t) -> p #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon,aes")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld2))] @@ -11943,52 +10609,21 @@ pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t { transmute(vld2q_s64(transmute(a))) } #[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2))] -pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t { - let mut ret_val: poly64x2x2_t = transmute(vld2q_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val -} -#[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld2))] pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t { transmute(vld2q_s64(transmute(a))) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2))] -pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t { - let mut ret_val: uint64x2x2_t = transmute(vld2q_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val -} #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3r))] @@ -12006,7 +10641,7 @@ pub unsafe fn vld3_dup_f64(a: *const f64) -> float64x1x3_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3r))] @@ -12024,7 +10659,7 @@ pub unsafe fn vld3q_dup_f64(a: *const f64) -> float64x2x3_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3r))] @@ -12042,25 +10677,18 @@ pub unsafe fn vld3q_dup_s64(a: *const i64) -> int64x2x3_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vld3_f64(a: *const f64) -> float64x1x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v1f64.p0" - )] - fn _vld3_f64(ptr: *const float64x1_t) -> float64x1x3_t; - } - _vld3_f64(a as _) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12086,7 +10714,7 @@ pub unsafe fn vld3_lane_f64(a: *const f64, b: float64x1x3_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12099,7 +10727,7 @@ pub unsafe fn vld3_lane_p64(a: *const p64, b: poly64x1x3_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12125,7 +10753,7 @@ pub unsafe fn vld3_lane_s64(a: *const i64, b: int64x1x3_t) -> i #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12138,8 +10766,7 @@ pub unsafe fn vld3_lane_u64(a: *const u64, b: uint64x1x3_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon,aes")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3r))] @@ -12147,90 +10774,43 @@ pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t { transmute(vld3q_dup_s64(transmute(a))) } #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3r))] -pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t { - let mut ret_val: poly64x2x3_t = transmute(vld3q_dup_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val -} -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3r))] pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t { transmute(vld3q_dup_s64(transmute(a))) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3r))] -pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t { - let mut ret_val: uint64x2x3_t = transmute(vld3q_dup_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val -} #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3q_f64(a: *const f64) -> float64x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v2f64.p0" - )] - fn _vld3q_f64(ptr: *const float64x2_t) -> float64x2x3_t; - } - _vld3q_f64(a as _) + crate::core_arch::macros::deinterleaving_load!(f64, 2, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3q_s64(a: *const i64) -> int64x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v2i64.p0" - )] - fn _vld3q_s64(ptr: *const int64x2_t) -> int64x2x3_t; - } - _vld3q_s64(a as _) + crate::core_arch::macros::deinterleaving_load!(i64, 2, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12256,7 +10836,7 @@ pub unsafe fn vld3q_lane_f64(a: *const f64, b: float64x2x3_t) - #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12269,13 +10849,13 @@ pub unsafe fn vld3q_lane_p64(a: *const p64, b: poly64x2x3_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vld3q_lane_s8(a: *const i8, b: int8x16x3_t) -> int8x16x3_t { - static_assert_uimm_bits!(LANE, 3); + static_assert_uimm_bits!(LANE, 4); unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -12295,7 +10875,7 @@ pub unsafe fn vld3q_lane_s8(a: *const i8, b: int8x16x3_t) -> in #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12321,7 +10901,7 @@ pub unsafe fn vld3q_lane_s64(a: *const i64, b: int64x2x3_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12334,7 +10914,7 @@ pub unsafe fn vld3q_lane_u8(a: *const u8, b: uint8x16x3_t) -> u #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12347,7 +10927,7 @@ pub unsafe fn vld3q_lane_u64(a: *const u64, b: uint64x2x3_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12360,8 +10940,7 @@ pub unsafe fn vld3q_lane_p8(a: *const p8, b: poly8x16x3_t) -> p #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon,aes")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3))] @@ -12369,54 +10948,21 @@ pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t { transmute(vld3q_s64(transmute(a))) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3))] -pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t { - let mut ret_val: poly64x2x3_t = transmute(vld3q_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val -} -#[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t { transmute(vld3q_s64(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3))] -pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t { - let mut ret_val: uint64x2x3_t = transmute(vld3q_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val -} #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12434,7 +10980,7 @@ pub unsafe fn vld4_dup_f64(a: *const f64) -> float64x1x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12452,7 +10998,7 @@ pub unsafe fn vld4q_dup_f64(a: *const f64) -> float64x2x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12470,25 +11016,18 @@ pub unsafe fn vld4q_dup_s64(a: *const i64) -> int64x2x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vld4_f64(a: *const f64) -> float64x1x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v1f64.p0" - )] - fn _vld4_f64(ptr: *const float64x1_t) -> float64x1x4_t; - } - _vld4_f64(a as _) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12515,7 +11054,7 @@ pub unsafe fn vld4_lane_f64(a: *const f64, b: float64x1x4_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12542,7 +11081,7 @@ pub unsafe fn vld4_lane_s64(a: *const i64, b: int64x1x4_t) -> i #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12555,7 +11094,7 @@ pub unsafe fn vld4_lane_p64(a: *const p64, b: poly64x1x4_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12568,8 +11107,7 @@ pub unsafe fn vld4_lane_u64(a: *const u64, b: uint64x1x4_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12577,92 +11115,43 @@ pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t { transmute(vld4q_dup_s64(transmute(a))) } #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(ld4r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t { - let mut ret_val: poly64x2x4_t = transmute(vld4q_dup_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; - ret_val -} -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t { transmute(vld4q_dup_s64(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t { - let mut ret_val: uint64x2x4_t = transmute(vld4q_dup_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; - ret_val -} #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4q_f64(a: *const f64) -> float64x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v2f64.p0" - )] - fn _vld4q_f64(ptr: *const float64x2_t) -> float64x2x4_t; - } - _vld4q_f64(a as _) + crate::core_arch::macros::deinterleaving_load!(f64, 2, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4q_s64(a: *const i64) -> int64x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v2i64.p0" - )] - fn _vld4q_s64(ptr: *const int64x2_t) -> int64x2x4_t; - } - _vld4q_s64(a as _) + crate::core_arch::macros::deinterleaving_load!(i64, 2, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12689,13 +11178,13 @@ pub unsafe fn vld4q_lane_f64(a: *const f64, b: float64x2x4_t) - #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vld4q_lane_s8(a: *const i8, b: int8x16x4_t) -> int8x16x4_t { - static_assert_uimm_bits!(LANE, 3); + static_assert_uimm_bits!(LANE, 4); unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -12716,7 +11205,7 @@ pub unsafe fn vld4q_lane_s8(a: *const i8, b: int8x16x4_t) -> in #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12743,7 +11232,7 @@ pub unsafe fn vld4q_lane_s64(a: *const i64, b: int64x2x4_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12756,7 +11245,7 @@ pub unsafe fn vld4q_lane_p64(a: *const p64, b: poly64x2x4_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12769,7 +11258,7 @@ pub unsafe fn vld4q_lane_u8(a: *const u8, b: uint8x16x4_t) -> u #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12782,7 +11271,7 @@ pub unsafe fn vld4q_lane_u64(a: *const u64, b: uint64x2x4_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12795,8 +11284,7 @@ pub unsafe fn vld4q_lane_p8(a: *const p8, b: poly8x16x4_t) -> p #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld4))] @@ -12804,60 +11292,26 @@ pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t { transmute(vld4q_s64(transmute(a))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(ld4))] -pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t { - let mut ret_val: poly64x2x4_t = transmute(vld4q_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; - ret_val -} -#[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t { transmute(vld4q_s64(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld4))] -pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t { - let mut ret_val: uint64x2x4_t = transmute(vld4q_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; - ret_val -} #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub unsafe fn vldap1_lane_s64(ptr: *const i64, src: int64x1_t) -> int64x1_t { static_assert!(LANE == 0); let atomic_src = crate::sync::atomic::AtomicI64::from_ptr(ptr as *mut i64); @@ -12871,11 +11325,12 @@ pub unsafe fn vldap1_lane_s64(ptr: *const i64, src: int64x1_t) #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub unsafe fn vldap1q_lane_s64(ptr: *const i64, src: int64x2_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); let atomic_src = crate::sync::atomic::AtomicI64::from_ptr(ptr as *mut i64); @@ -12889,11 +11344,12 @@ pub unsafe fn vldap1q_lane_s64(ptr: *const i64, src: int64x2_t) #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub unsafe fn vldap1q_lane_f64(ptr: *const f64, src: float64x2_t) -> float64x2_t { static_assert_uimm_bits!(LANE, 1); transmute(vldap1q_lane_s64::(ptr as *mut i64, transmute(src))) @@ -12902,11 +11358,12 @@ pub unsafe fn vldap1q_lane_f64(ptr: *const f64, src: float64x2_ #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub unsafe fn vldap1_lane_u64(ptr: *const u64, src: uint64x1_t) -> uint64x1_t { static_assert!(LANE == 0); transmute(vldap1_lane_s64::(ptr as *mut i64, transmute(src))) @@ -12915,11 +11372,12 @@ pub unsafe fn vldap1_lane_u64(ptr: *const u64, src: uint64x1_t) #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub unsafe fn vldap1q_lane_u64(ptr: *const u64, src: uint64x2_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); transmute(vldap1q_lane_s64::(ptr as *mut i64, transmute(src))) @@ -12928,11 +11386,12 @@ pub unsafe fn vldap1q_lane_u64(ptr: *const u64, src: uint64x2_t #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub unsafe fn vldap1_lane_p64(ptr: *const p64, src: poly64x1_t) -> poly64x1_t { static_assert!(LANE == 0); transmute(vldap1_lane_s64::(ptr as *mut i64, transmute(src))) @@ -12941,11 +11400,12 @@ pub unsafe fn vldap1_lane_p64(ptr: *const p64, src: poly64x1_t) #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub unsafe fn vldap1q_lane_p64(ptr: *const p64, src: poly64x2_t) -> poly64x2_t { static_assert_uimm_bits!(LANE, 1); transmute(vldap1q_lane_s64::(ptr as *mut i64, transmute(src))) @@ -12954,7 +11414,7 @@ pub unsafe fn vldap1q_lane_p64(ptr: *const p64, src: poly64x2_t #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -12967,7 +11427,7 @@ pub unsafe fn vluti2_lane_f16(a: float16x4_t, b: uint8x8_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -12980,7 +11440,7 @@ pub unsafe fn vluti2q_lane_f16(a: float16x8_t, b: uint8x8_t) - #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -12993,7 +11453,7 @@ pub unsafe fn vluti2_lane_u8(a: uint8x8_t, b: uint8x8_t) -> ui #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13006,7 +11466,7 @@ pub unsafe fn vluti2q_lane_u8(a: uint8x16_t, b: uint8x8_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13019,7 +11479,7 @@ pub unsafe fn vluti2_lane_u16(a: uint16x4_t, b: uint8x8_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13032,7 +11492,7 @@ pub unsafe fn vluti2q_lane_u16(a: uint16x8_t, b: uint8x8_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13045,7 +11505,7 @@ pub unsafe fn vluti2_lane_p8(a: poly8x8_t, b: uint8x8_t) -> po #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13058,7 +11518,7 @@ pub unsafe fn vluti2q_lane_p8(a: poly8x16_t, b: uint8x8_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13071,7 +11531,7 @@ pub unsafe fn vluti2_lane_p16(a: poly16x4_t, b: uint8x8_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13084,7 +11544,7 @@ pub unsafe fn vluti2q_lane_p16(a: poly16x8_t, b: uint8x8_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13104,7 +11564,7 @@ pub unsafe fn vluti2_lane_s8(a: int8x8_t, b: uint8x8_t) -> int8 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13124,7 +11584,7 @@ pub unsafe fn vluti2q_lane_s8(a: int8x16_t, b: uint8x8_t) -> in #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13144,7 +11604,7 @@ pub unsafe fn vluti2_lane_s16(a: int16x4_t, b: uint8x8_t) -> in #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13164,7 +11624,7 @@ pub unsafe fn vluti2q_lane_s16(a: int16x8_t, b: uint8x8_t) -> i #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13177,7 +11637,7 @@ pub unsafe fn vluti2_laneq_f16(a: float16x4_t, b: uint8x16_t) #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13190,7 +11650,7 @@ pub unsafe fn vluti2q_laneq_f16(a: float16x8_t, b: uint8x16_t) #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13203,7 +11663,7 @@ pub unsafe fn vluti2_laneq_u8(a: uint8x8_t, b: uint8x16_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13216,7 +11676,7 @@ pub unsafe fn vluti2q_laneq_u8(a: uint8x16_t, b: uint8x16_t) - #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13229,7 +11689,7 @@ pub unsafe fn vluti2_laneq_u16(a: uint16x4_t, b: uint8x16_t) - #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13242,7 +11702,7 @@ pub unsafe fn vluti2q_laneq_u16(a: uint16x8_t, b: uint8x16_t) #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13255,7 +11715,7 @@ pub unsafe fn vluti2_laneq_p8(a: poly8x8_t, b: uint8x16_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13268,7 +11728,7 @@ pub unsafe fn vluti2q_laneq_p8(a: poly8x16_t, b: uint8x16_t) - #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13281,7 +11741,7 @@ pub unsafe fn vluti2_laneq_p16(a: poly16x4_t, b: uint8x16_t) - #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13294,7 +11754,7 @@ pub unsafe fn vluti2q_laneq_p16(a: poly16x8_t, b: uint8x16_t) #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13314,7 +11774,7 @@ pub unsafe fn vluti2_laneq_s8(a: int8x8_t, b: uint8x16_t) -> i #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13334,7 +11794,7 @@ pub unsafe fn vluti2q_laneq_s8(a: int8x16_t, b: uint8x16_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13354,7 +11814,7 @@ pub unsafe fn vluti2_laneq_s16(a: int16x4_t, b: uint8x16_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13374,7 +11834,7 @@ pub unsafe fn vluti2q_laneq_s16(a: int16x8_t, b: uint8x16_t) - #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_f16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut,fp16")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13387,7 +11847,7 @@ pub unsafe fn vluti4q_lane_f16_x2(a: float16x8x2_t, b: uint8x8_ #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_u16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13400,7 +11860,7 @@ pub unsafe fn vluti4q_lane_u16_x2(a: uint16x8x2_t, b: uint8x8_t #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_p16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13413,7 +11873,7 @@ pub unsafe fn vluti4q_lane_p16_x2(a: poly16x8x2_t, b: uint8x8_t #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_s16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13433,7 +11893,7 @@ pub unsafe fn vluti4q_lane_s16_x2(a: int16x8x2_t, b: uint8x8_t) #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13443,7 +11903,7 @@ pub unsafe fn vluti4q_lane_s8(a: int8x16_t, b: uint8x8_t) -> in unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vluti4q.lane.v8i8" + link_name = "llvm.aarch64.neon.vluti4q.lane.v16i8" )] fn _vluti4q_lane_s8(a: int8x16_t, b: uint8x8_t, n: i32) -> int8x16_t; } @@ -13453,7 +11913,7 @@ pub unsafe fn vluti4q_lane_s8(a: int8x16_t, b: uint8x8_t) -> in #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13466,7 +11926,7 @@ pub unsafe fn vluti4q_lane_u8(a: uint8x16_t, b: uint8x8_t) -> u #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13479,7 +11939,7 @@ pub unsafe fn vluti4q_lane_p8(a: poly8x16_t, b: uint8x8_t) -> p #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_f16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut,fp16")] #[cfg_attr(test, assert_instr(nop, LANE = 3))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13495,7 +11955,7 @@ pub unsafe fn vluti4q_laneq_f16_x2( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_u16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 3))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13508,7 +11968,7 @@ pub unsafe fn vluti4q_laneq_u16_x2(a: uint16x8x2_t, b: uint8x16 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_p16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 3))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13521,7 +11981,7 @@ pub unsafe fn vluti4q_laneq_p16_x2(a: poly16x8x2_t, b: uint8x16 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_s16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 3))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13541,7 +12001,7 @@ pub unsafe fn vluti4q_laneq_s16_x2(a: int16x8x2_t, b: uint8x16_ #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13561,7 +12021,7 @@ pub unsafe fn vluti4q_laneq_s8(a: int8x16_t, b: uint8x16_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13574,7 +12034,7 @@ pub unsafe fn vluti4q_laneq_u8(a: uint8x16_t, b: uint8x16_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13585,7 +12045,7 @@ pub unsafe fn vluti4q_laneq_p8(a: poly8x16_t, b: uint8x16_t) -> } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmax))] @@ -13601,7 +12061,7 @@ pub fn vmax_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmax))] @@ -13617,7 +12077,7 @@ pub fn vmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -13634,82 +12094,138 @@ pub fn vmaxh_f16(a: f16, b: f16) -> f16 { } #[doc = "Floating-point Maximum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnm))] pub fn vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { - unsafe { simd_fmax(a, b) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnm.v1f64" + )] + fn _vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t; + } + unsafe { _vmaxnm_f64(a, b) } } #[doc = "Floating-point Maximum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnm))] pub fn vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - unsafe { simd_fmax(a, b) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnm.v2f64" + )] + fn _vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + } + unsafe { _vmaxnmq_f64(a, b) } } #[doc = "Floating-point Maximum Number"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmaxnm))] pub fn vmaxnmh_f16(a: f16, b: f16) -> f16 { - f16::max(a, b) + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnm.f16" + )] + fn _vmaxnmh_f16(a: f16, b: f16) -> f16; + } + unsafe { _vmaxnmh_f16(a, b) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmaxnmv))] pub fn vmaxnmv_f16(a: float16x4_t) -> f16 { - unsafe { simd_reduce_max(a) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmv.f16.v4f16" + )] + fn _vmaxnmv_f16(a: float16x4_t) -> f16; + } + unsafe { _vmaxnmv_f16(a) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmaxnmv))] pub fn vmaxnmvq_f16(a: float16x8_t) -> f16 { - unsafe { simd_reduce_max(a) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmv.f16.v8f16" + )] + fn _vmaxnmvq_f16(a: float16x8_t) -> f16; + } + unsafe { _vmaxnmvq_f16(a) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnmp))] pub fn vmaxnmv_f32(a: float32x2_t) -> f32 { - unsafe { simd_reduce_max(a) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmv.f32.v2f32" + )] + fn _vmaxnmv_f32(a: float32x2_t) -> f32; + } + unsafe { _vmaxnmv_f32(a) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnmp))] pub fn vmaxnmvq_f64(a: float64x2_t) -> f64 { - unsafe { simd_reduce_max(a) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmv.f64.v2f64" + )] + fn _vmaxnmvq_f64(a: float64x2_t) -> f64; + } + unsafe { _vmaxnmvq_f64(a) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnmv))] pub fn vmaxnmvq_f32(a: float32x4_t) -> f32 { - unsafe { simd_reduce_max(a) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmv.f32.v4f32" + )] + fn _vmaxnmvq_f32(a: float32x4_t) -> f32; + } + unsafe { _vmaxnmvq_f32(a) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -13726,7 +12242,7 @@ pub fn vmaxv_f16(a: float16x4_t) -> f16 { } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -13743,7 +12259,7 @@ pub fn vmaxvq_f16(a: float16x8_t) -> f16 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxp))] @@ -13759,7 +12275,7 @@ pub fn vmaxv_f32(a: float32x2_t) -> f32 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxv))] @@ -13775,7 +12291,7 @@ pub fn vmaxvq_f32(a: float32x4_t) -> f32 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxp))] @@ -13791,7 +12307,7 @@ pub fn vmaxvq_f64(a: float64x2_t) -> f64 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxv))] @@ -13800,7 +12316,7 @@ pub fn vmaxv_s8(a: int8x8_t) -> i8 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxv))] @@ -13809,7 +12325,7 @@ pub fn vmaxvq_s8(a: int8x16_t) -> i8 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxv))] @@ -13818,7 +12334,7 @@ pub fn vmaxv_s16(a: int16x4_t) -> i16 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxv))] @@ -13827,7 +12343,7 @@ pub fn vmaxvq_s16(a: int16x8_t) -> i16 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxp))] @@ -13836,7 +12352,7 @@ pub fn vmaxv_s32(a: int32x2_t) -> i32 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxv))] @@ -13845,7 +12361,7 @@ pub fn vmaxvq_s32(a: int32x4_t) -> i32 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxv))] @@ -13854,7 +12370,7 @@ pub fn vmaxv_u8(a: uint8x8_t) -> u8 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxv))] @@ -13863,7 +12379,7 @@ pub fn vmaxvq_u8(a: uint8x16_t) -> u8 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxv))] @@ -13872,7 +12388,7 @@ pub fn vmaxv_u16(a: uint16x4_t) -> u16 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxv))] @@ -13881,7 +12397,7 @@ pub fn vmaxvq_u16(a: uint16x8_t) -> u16 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxp))] @@ -13890,7 +12406,7 @@ pub fn vmaxv_u32(a: uint32x2_t) -> u32 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxv))] @@ -13899,7 +12415,7 @@ pub fn vmaxvq_u32(a: uint32x4_t) -> u32 { } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmin))] @@ -13915,7 +12431,7 @@ pub fn vmin_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmin))] @@ -13931,7 +12447,7 @@ pub fn vminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -13948,82 +12464,138 @@ pub fn vminh_f16(a: f16, b: f16) -> f16 { } #[doc = "Floating-point Minimum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminnm))] pub fn vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { - unsafe { simd_fmin(a, b) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnm.v1f64" + )] + fn _vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t; + } + unsafe { _vminnm_f64(a, b) } } #[doc = "Floating-point Minimum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminnm))] pub fn vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - unsafe { simd_fmin(a, b) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnm.v2f64" + )] + fn _vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + } + unsafe { _vminnmq_f64(a, b) } } #[doc = "Floating-point Minimum Number"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fminnm))] pub fn vminnmh_f16(a: f16, b: f16) -> f16 { - f16::min(a, b) + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnm.f16" + )] + fn _vminnmh_f16(a: f16, b: f16) -> f16; + } + unsafe { _vminnmh_f16(a, b) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fminnmv))] pub fn vminnmv_f16(a: float16x4_t) -> f16 { - unsafe { simd_reduce_min(a) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmv.f16.v4f16" + )] + fn _vminnmv_f16(a: float16x4_t) -> f16; + } + unsafe { _vminnmv_f16(a) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fminnmv))] pub fn vminnmvq_f16(a: float16x8_t) -> f16 { - unsafe { simd_reduce_min(a) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmv.f16.v8f16" + )] + fn _vminnmvq_f16(a: float16x8_t) -> f16; + } + unsafe { _vminnmvq_f16(a) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vminnmv_f32(a: float32x2_t) -> f32 { - unsafe { simd_reduce_min(a) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmv.f32.v2f32" + )] + fn _vminnmv_f32(a: float32x2_t) -> f32; + } + unsafe { _vminnmv_f32(a) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vminnmvq_f64(a: float64x2_t) -> f64 { - unsafe { simd_reduce_min(a) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmv.f64.v2f64" + )] + fn _vminnmvq_f64(a: float64x2_t) -> f64; + } + unsafe { _vminnmvq_f64(a) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmv))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vminnmvq_f32(a: float32x4_t) -> f32 { - unsafe { simd_reduce_min(a) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmv.f32.v4f32" + )] + fn _vminnmvq_f32(a: float32x4_t) -> f32; + } + unsafe { _vminnmvq_f32(a) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -14040,7 +12612,7 @@ pub fn vminv_f16(a: float16x4_t) -> f16 { } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -14057,7 +12629,7 @@ pub fn vminvq_f16(a: float16x8_t) -> f16 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminp))] @@ -14073,7 +12645,7 @@ pub fn vminv_f32(a: float32x2_t) -> f32 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminv))] @@ -14089,7 +12661,7 @@ pub fn vminvq_f32(a: float32x4_t) -> f32 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminp))] @@ -14105,7 +12677,7 @@ pub fn vminvq_f64(a: float64x2_t) -> f64 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminv))] @@ -14114,7 +12686,7 @@ pub fn vminv_s8(a: int8x8_t) -> i8 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminv))] @@ -14123,7 +12695,7 @@ pub fn vminvq_s8(a: int8x16_t) -> i8 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminv))] @@ -14132,7 +12704,7 @@ pub fn vminv_s16(a: int16x4_t) -> i16 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminv))] @@ -14141,7 +12713,7 @@ pub fn vminvq_s16(a: int16x8_t) -> i16 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminp))] @@ -14150,7 +12722,7 @@ pub fn vminv_s32(a: int32x2_t) -> i32 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminv))] @@ -14159,7 +12731,7 @@ pub fn vminvq_s32(a: int32x4_t) -> i32 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminv))] @@ -14168,7 +12740,7 @@ pub fn vminv_u8(a: uint8x8_t) -> u8 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminv))] @@ -14177,7 +12749,7 @@ pub fn vminvq_u8(a: uint8x16_t) -> u8 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminv))] @@ -14186,7 +12758,7 @@ pub fn vminv_u16(a: uint16x4_t) -> u16 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminv))] @@ -14195,7 +12767,7 @@ pub fn vminvq_u16(a: uint16x8_t) -> u16 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminp))] @@ -14204,7 +12776,7 @@ pub fn vminv_u32(a: uint32x2_t) -> u32 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminv))] @@ -14213,7 +12785,7 @@ pub fn vminvq_u32(a: uint32x4_t) -> u32 { } #[doc = "Floating-point multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -14222,7 +12794,7 @@ pub fn vmla_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { } #[doc = "Floating-point multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -14231,39 +12803,20 @@ pub fn vmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_lane_s16(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlal_high_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + vmlal_high_s16(a, b, vdupq_lane_s16::(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_laneq_s16( @@ -14272,49 +12825,24 @@ pub fn vmlal_high_laneq_s16( c: int16x8_t, ) -> int32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmlal_high_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + vmlal_high_s16(a, b, vdupq_laneq_s16::(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_lane_s32(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - vmlal_high_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlal_high_s32(a, b, vdupq_lane_s32::(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_laneq_s32( @@ -14323,19 +12851,13 @@ pub fn vmlal_high_laneq_s32( c: int32x4_t, ) -> int64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlal_high_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlal_high_s32(a, b, vdupq_laneq_s32::(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_lane_u16( @@ -14344,32 +12866,13 @@ pub fn vmlal_high_lane_u16( c: uint16x4_t, ) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlal_high_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + vmlal_high_u16(a, b, vdupq_lane_u16::(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_laneq_u16( @@ -14378,32 +12881,13 @@ pub fn vmlal_high_laneq_u16( c: uint16x8_t, ) -> uint32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmlal_high_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + vmlal_high_u16(a, b, vdupq_laneq_u16::(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_lane_u32( @@ -14412,19 +12896,13 @@ pub fn vmlal_high_lane_u32( c: uint32x2_t, ) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - vmlal_high_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlal_high_u32(a, b, vdupq_lane_u32::(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_laneq_u32( @@ -14433,131 +12911,113 @@ pub fn vmlal_high_laneq_u32( c: uint32x4_t, ) -> uint64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlal_high_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlal_high_u32(a, b, vdupq_laneq_u32::(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { vmlal_high_s16(a, b, vdupq_n_s16(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { vmlal_high_s32(a, b, vdupq_n_s32(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t { vmlal_high_u16(a, b, vdupq_n_u16(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t { vmlal_high_u32(a, b, vdupq_n_u32(c)) } #[doc = "Signed multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { - unsafe { - let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let c: int8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - vmlal_s8(a, b, c) - } + let b = vget_high_s8(b); + let c = vget_high_s8(c); + vmlal_s8(a, b, c) } #[doc = "Signed multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { - unsafe { - let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let c: int16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - vmlal_s16(a, b, c) - } + let b = vget_high_s16(b); + let c = vget_high_s16(c); + vmlal_s16(a, b, c) } #[doc = "Signed multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { - unsafe { - let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); - let c: int32x2_t = simd_shuffle!(c, c, [2, 3]); - vmlal_s32(a, b, c) - } + let b = vget_high_s32(b); + let c = vget_high_s32(c); + vmlal_s32(a, b, c) } #[doc = "Unsigned multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { - unsafe { - let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let c: uint8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - vmlal_u8(a, b, c) - } + let b = vget_high_u8(b); + let c = vget_high_u8(c); + vmlal_u8(a, b, c) } #[doc = "Unsigned multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { - unsafe { - let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let c: uint16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - vmlal_u16(a, b, c) - } + let b = vget_high_u16(b); + let c = vget_high_u16(c); + vmlal_u16(a, b, c) } #[doc = "Unsigned multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { - unsafe { - let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - let c: uint32x2_t = simd_shuffle!(c, c, [2, 3]); - vmlal_u32(a, b, c) - } + let b = vget_high_u32(b); + let c = vget_high_u32(c); + vmlal_u32(a, b, c) } #[doc = "Floating-point multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -14566,7 +13026,7 @@ pub fn vmls_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { } #[doc = "Floating-point multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -14575,39 +13035,20 @@ pub fn vmlsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_lane_s16(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlsl_high_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + vmlsl_high_s16(a, b, vdupq_lane_s16::(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_laneq_s16( @@ -14616,49 +13057,24 @@ pub fn vmlsl_high_laneq_s16( c: int16x8_t, ) -> int32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmlsl_high_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + vmlsl_high_s16(a, b, vdupq_laneq_s16::(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_lane_s32(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - vmlsl_high_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlsl_high_s32(a, b, vdupq_lane_s32::(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_laneq_s32( @@ -14667,19 +13083,13 @@ pub fn vmlsl_high_laneq_s32( c: int32x4_t, ) -> int64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlsl_high_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlsl_high_s32(a, b, vdupq_laneq_s32::(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_lane_u16( @@ -14688,32 +13098,13 @@ pub fn vmlsl_high_lane_u16( c: uint16x4_t, ) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlsl_high_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + vmlsl_high_u16(a, b, vdupq_lane_u16::(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_laneq_u16( @@ -14722,32 +13113,13 @@ pub fn vmlsl_high_laneq_u16( c: uint16x8_t, ) -> uint32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmlsl_high_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + vmlsl_high_u16(a, b, vdupq_laneq_u16::(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_lane_u32( @@ -14756,19 +13128,13 @@ pub fn vmlsl_high_lane_u32( c: uint32x2_t, ) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - vmlsl_high_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlsl_high_u32(a, b, vdupq_lane_u32::(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_laneq_u32( @@ -14777,275 +13143,227 @@ pub fn vmlsl_high_laneq_u32( c: uint32x4_t, ) -> uint64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlsl_high_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlsl_high_u32(a, b, vdupq_laneq_u32::(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { vmlsl_high_s16(a, b, vdupq_n_s16(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { vmlsl_high_s32(a, b, vdupq_n_s32(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t { vmlsl_high_u16(a, b, vdupq_n_u16(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t { vmlsl_high_u32(a, b, vdupq_n_u32(c)) } #[doc = "Signed multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { - unsafe { - let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let c: int8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - vmlsl_s8(a, b, c) - } + let b = vget_high_s8(b); + let c = vget_high_s8(c); + vmlsl_s8(a, b, c) } #[doc = "Signed multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { - unsafe { - let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let c: int16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - vmlsl_s16(a, b, c) - } + let b = vget_high_s16(b); + let c = vget_high_s16(c); + vmlsl_s16(a, b, c) } #[doc = "Signed multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { - unsafe { - let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); - let c: int32x2_t = simd_shuffle!(c, c, [2, 3]); - vmlsl_s32(a, b, c) - } + let b = vget_high_s32(b); + let c = vget_high_s32(c); + vmlsl_s32(a, b, c) } #[doc = "Unsigned multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { - unsafe { - let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let c: uint8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - vmlsl_u8(a, b, c) - } + let b = vget_high_u8(b); + let c = vget_high_u8(c); + vmlsl_u8(a, b, c) } #[doc = "Unsigned multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { - unsafe { - let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let c: uint16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - vmlsl_u16(a, b, c) - } + let b = vget_high_u16(b); + let c = vget_high_u16(c); + vmlsl_u16(a, b, c) } #[doc = "Unsigned multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { - unsafe { - let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - let c: uint32x2_t = simd_shuffle!(c, c, [2, 3]); - vmlsl_u32(a, b, c) - } + let b = vget_high_u32(b); + let c = vget_high_u32(c); + vmlsl_u32(a, b, c) } #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(sxtl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sxtl2))] pub fn vmovl_high_s8(a: int8x16_t) -> int16x8_t { - unsafe { - let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - vmovl_s8(a) - } + let a = vget_high_s8(a); + vmovl_s8(a) } #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(sxtl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sxtl2))] pub fn vmovl_high_s16(a: int16x8_t) -> int32x4_t { - unsafe { - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - vmovl_s16(a) - } + let a = vget_high_s16(a); + vmovl_s16(a) } #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(sxtl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sxtl2))] pub fn vmovl_high_s32(a: int32x4_t) -> int64x2_t { - unsafe { - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - vmovl_s32(a) - } + let a = vget_high_s32(a); + vmovl_s32(a) } #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(uxtl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uxtl2))] pub fn vmovl_high_u8(a: uint8x16_t) -> uint16x8_t { - unsafe { - let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - vmovl_u8(a) - } + let a = vget_high_u8(a); + vmovl_u8(a) } #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(uxtl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uxtl2))] pub fn vmovl_high_u16(a: uint16x8_t) -> uint32x4_t { - unsafe { - let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - vmovl_u16(a) - } + let a = vget_high_u16(a); + vmovl_u16(a) } #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(uxtl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uxtl2))] pub fn vmovl_high_u32(a: uint32x4_t) -> uint64x2_t { - unsafe { - let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]); - vmovl_u32(a) - } + let a = vget_high_u32(a); + vmovl_u32(a) } #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(xtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))] pub fn vmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { - unsafe { - let c: int8x8_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) - } + unsafe { vcombine_s8(a, simd_cast(b)) } } #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(xtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))] pub fn vmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { - unsafe { - let c: int16x4_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7]) - } + unsafe { vcombine_s16(a, simd_cast(b)) } } #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(xtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))] pub fn vmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { - unsafe { - let c: int32x2_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3]) - } + unsafe { vcombine_s32(a, simd_cast(b)) } } #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(xtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))] pub fn vmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { - unsafe { - let c: uint8x8_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) - } + unsafe { vcombine_u8(a, simd_cast(b)) } } #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(xtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))] pub fn vmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { - unsafe { - let c: uint16x4_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7]) - } + unsafe { vcombine_u16(a, simd_cast(b)) } } #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(xtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))] pub fn vmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { - unsafe { - let c: uint32x2_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3]) - } + unsafe { vcombine_u32(a, simd_cast(b)) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmul))] @@ -15054,7 +13372,7 @@ pub fn vmul_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmul))] @@ -15063,76 +13381,53 @@ pub fn vmulq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmul_lane_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { static_assert!(LANE == 0); - unsafe { simd_mul(a, transmute::(simd_extract!(b, LANE as u32))) } + unsafe { simd_mul(a, transmute::(vget_lane_f64::(b))) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vmul_laneq_f16(a: float16x4_t, b: float16x8_t) -> float16x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { simd_mul(a, vdup_laneq_f16::(b)) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vmulq_laneq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - simd_mul( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + unsafe { simd_mul(a, vdupq_laneq_f16::(b)) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmul_laneq_f64(a: float64x1_t, b: float64x2_t) -> float64x1_t { static_assert_uimm_bits!(LANE, 1); - unsafe { simd_mul(a, transmute::(simd_extract!(b, LANE as u32))) } + unsafe { simd_mul(a, transmute::(vgetq_lane_f64::(b))) } } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -15141,7 +13436,7 @@ pub fn vmul_n_f64(a: float64x1_t, b: f64) -> float64x1_t { } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -15150,21 +13445,19 @@ pub fn vmulq_n_f64(a: float64x2_t, b: f64) -> float64x2_t { } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuld_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmuld_lane_f64(a: f64, b: float64x1_t) -> f64 { static_assert!(LANE == 0); - unsafe { - let b: f64 = simd_extract!(b, LANE as u32); - a * b - } + let b: f64 = vget_lane_f64::(b); + a * b } #[doc = "Add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -15174,7 +13467,7 @@ pub fn vmulh_f16(a: f16, b: f16) -> f16 { } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulh_lane_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] @@ -15182,14 +13475,12 @@ pub fn vmulh_f16(a: f16, b: f16) -> f16 { #[cfg(not(target_arch = "arm64ec"))] pub fn vmulh_lane_f16(a: f16, b: float16x4_t) -> f16 { static_assert_uimm_bits!(LANE, 2); - unsafe { - let b: f16 = simd_extract!(b, LANE as u32); - a * b - } + let b: f16 = vget_lane_f16::(b); + a * b } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulh_laneq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] @@ -15197,330 +13488,222 @@ pub fn vmulh_lane_f16(a: f16, b: float16x4_t) -> f16 { #[cfg(not(target_arch = "arm64ec"))] pub fn vmulh_laneq_f16(a: f16, b: float16x8_t) -> f16 { static_assert_uimm_bits!(LANE, 3); - unsafe { - let b: f16 = simd_extract!(b, LANE as u32); - a * b - } + let b: f16 = vgetq_lane_f16::(b); + a * b } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smull2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_lane_s16(a: int16x8_t, b: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmull_high_s16( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + vmull_high_s16(a, vdupq_lane_s16::(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smull2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_laneq_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmull_high_s16( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + vmull_high_s16(a, vdupq_laneq_s16::(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smull2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_lane_s32(a: int32x4_t, b: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - vmull_high_s32( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmull_high_s32(a, vdupq_lane_s32::(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smull2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_laneq_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmull_high_s32( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmull_high_s32(a, vdupq_laneq_s32::(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umull2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_lane_u16(a: uint16x8_t, b: uint16x4_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmull_high_u16( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + vmull_high_u16(a, vdupq_lane_u16::(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umull2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_laneq_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmull_high_u16( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + vmull_high_u16(a, vdupq_laneq_u16::(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umull2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_lane_u32(a: uint32x4_t, b: uint32x2_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - vmull_high_u32( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmull_high_u32(a, vdupq_lane_u32::(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umull2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_laneq_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmull_high_u32( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmull_high_u32(a, vdupq_laneq_u32::(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t { vmull_high_s16(a, vdupq_n_s16(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t { vmull_high_s32(a, vdupq_n_s32(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_n_u16(a: uint16x8_t, b: u16) -> uint32x4_t { vmull_high_u16(a, vdupq_n_u16(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_n_u32(a: uint32x4_t, b: u32) -> uint64x2_t { vmull_high_u32(a, vdupq_n_u32(b)) } #[doc = "Polynomial multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(pmull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(pmull2))] pub fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 { - unsafe { vmull_p64(simd_extract!(a, 1), simd_extract!(b, 1)) } + vmull_p64(vgetq_lane_p64::<1>(a), vgetq_lane_p64::<1>(b)) } #[doc = "Polynomial multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(pmull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(pmull2))] pub fn vmull_high_p8(a: poly8x16_t, b: poly8x16_t) -> poly16x8_t { - unsafe { - let a: poly8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let b: poly8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - vmull_p8(a, b) - } + let a = vget_high_p8(a); + let b = vget_high_p8(b); + vmull_p8(a, b) } #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(smull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))] pub fn vmull_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { - unsafe { - let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - vmull_s8(a, b) - } + let a = vget_high_s8(a); + let b = vget_high_s8(b); + vmull_s8(a, b) } #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(smull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))] pub fn vmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { - unsafe { - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - vmull_s16(a, b) - } + let a = vget_high_s16(a); + let b = vget_high_s16(b); + vmull_s16(a, b) } #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(smull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))] pub fn vmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { - unsafe { - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); - vmull_s32(a, b) - } + let a = vget_high_s32(a); + let b = vget_high_s32(b); + vmull_s32(a, b) } #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(umull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))] pub fn vmull_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { - unsafe { - let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - vmull_u8(a, b) - } + let a = vget_high_u8(a); + let b = vget_high_u8(b); + vmull_u8(a, b) } #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(umull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))] pub fn vmull_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { - unsafe { - let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - vmull_u16(a, b) - } + let a = vget_high_u16(a); + let b = vget_high_u16(b); + vmull_u16(a, b) } #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(umull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))] pub fn vmull_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { - unsafe { - let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - vmull_u32(a, b) - } + let a = vget_high_u32(a); + let b = vget_high_u32(b); + vmull_u32(a, b) } #[doc = "Polynomial multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(pmull))] @@ -15536,73 +13719,67 @@ pub fn vmull_p64(a: p64, b: p64) -> p128 { } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulq_lane_f64(a: float64x2_t, b: float64x1_t) -> float64x2_t { static_assert!(LANE == 0); - unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } + unsafe { simd_mul(a, vdupq_lane_f64::(b)) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulq_laneq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } + unsafe { simd_mul(a, vdupq_laneq_f64::(b)) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmuls_lane_f32(a: f32, b: float32x2_t) -> f32 { static_assert_uimm_bits!(LANE, 1); - unsafe { - let b: f32 = simd_extract!(b, LANE as u32); - a * b - } + let b: f32 = vget_lane_f32::(b); + a * b } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmuls_laneq_f32(a: f32, b: float32x4_t) -> f32 { static_assert_uimm_bits!(LANE, 2); - unsafe { - let b: f32 = simd_extract!(b, LANE as u32); - a * b - } + let b: f32 = vgetq_lane_f32::(b); + a * b } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuld_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmuld_laneq_f64(a: f64, b: float64x2_t) -> f64 { static_assert_uimm_bits!(LANE, 1); - unsafe { - let b: f64 = simd_extract!(b, LANE as u32); - a * b - } + let b: f64 = vgetq_lane_f64::(b); + a * b } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmulx))] pub fn vmulx_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -15617,9 +13794,9 @@ pub fn vmulx_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmulx))] pub fn vmulxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -15634,7 +13811,7 @@ pub fn vmulxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmulx))] @@ -15650,7 +13827,7 @@ pub fn vmulx_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmulx))] @@ -15666,7 +13843,7 @@ pub fn vmulxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmulx))] @@ -15682,7 +13859,7 @@ pub fn vmulx_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmulx))] @@ -15698,188 +13875,132 @@ pub fn vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vmulx_lane_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmulx_f16( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmulx_f16(a, vdup_lane_f16::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vmulx_laneq_f16(a: float16x4_t, b: float16x8_t) -> float16x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmulx_f16( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmulx_f16(a, vdup_laneq_f16::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vmulxq_lane_f16(a: float16x8_t, b: float16x4_t) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmulxq_f16( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + vmulxq_f16(a, vdupq_lane_f16::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vmulxq_laneq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmulxq_f16( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + vmulxq_f16(a, vdupq_laneq_f16::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulx_lane_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } + vmulx_f32(a, vdup_lane_f32::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulx_laneq_f32(a: float32x2_t, b: float32x4_t) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } + vmulx_f32(a, vdup_laneq_f32::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulxq_lane_f32(a: float32x4_t, b: float32x2_t) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - vmulxq_f32( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmulxq_f32(a, vdupq_lane_f32::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulxq_laneq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmulxq_f32( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmulxq_f32(a, vdupq_laneq_f32::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulxq_laneq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } + vmulxq_f64(a, vdupq_laneq_f64::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulx_lane_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { static_assert!(LANE == 0); - unsafe { vmulx_f64(a, transmute::(simd_extract!(b, LANE as u32))) } + unsafe { vmulx_f64(a, transmute(vget_lane_f64::(b))) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulx_laneq_f64(a: float64x1_t, b: float64x2_t) -> float64x1_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmulx_f64(a, transmute::(simd_extract!(b, LANE as u32))) } + unsafe { vmulx_f64(a, transmute(vgetq_lane_f64::(b))) } } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_n_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmulx))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -15889,7 +14010,7 @@ pub fn vmulx_n_f16(a: float16x4_t, b: f16) -> float16x4_t { } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_n_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmulx))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -15899,7 +14020,7 @@ pub fn vmulxq_n_f16(a: float16x8_t, b: f16) -> float16x8_t { } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmulx))] @@ -15915,7 +14036,7 @@ pub fn vmulxd_f64(a: f64, b: f64) -> f64 { } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmulx))] @@ -15931,51 +14052,51 @@ pub fn vmulxs_f32(a: f32, b: f32) -> f32 { } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulxd_lane_f64(a: f64, b: float64x1_t) -> f64 { static_assert!(LANE == 0); - unsafe { vmulxd_f64(a, simd_extract!(b, LANE as u32)) } + vmulxd_f64(a, vget_lane_f64::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulxd_laneq_f64(a: f64, b: float64x2_t) -> f64 { static_assert_uimm_bits!(LANE, 1); - unsafe { vmulxd_f64(a, simd_extract!(b, LANE as u32)) } + vmulxd_f64(a, vgetq_lane_f64::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulxs_lane_f32(a: f32, b: float32x2_t) -> f32 { static_assert_uimm_bits!(LANE, 1); - unsafe { vmulxs_f32(a, simd_extract!(b, LANE as u32)) } + vmulxs_f32(a, vget_lane_f32::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulxs_laneq_f32(a: f32, b: float32x4_t) -> f32 { static_assert_uimm_bits!(LANE, 2); - unsafe { vmulxs_f32(a, simd_extract!(b, LANE as u32)) } + vmulxs_f32(a, vgetq_lane_f32::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -15992,7 +14113,7 @@ pub fn vmulxh_f16(a: f16, b: f16) -> f16 { } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxh_lane_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] @@ -16000,11 +14121,11 @@ pub fn vmulxh_f16(a: f16, b: f16) -> f16 { #[cfg(not(target_arch = "arm64ec"))] pub fn vmulxh_lane_f16(a: f16, b: float16x4_t) -> f16 { static_assert_uimm_bits!(LANE, 2); - unsafe { vmulxh_f16(a, simd_extract!(b, LANE as u32)) } + vmulxh_f16(a, vget_lane_f16::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxh_laneq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] @@ -16012,22 +14133,22 @@ pub fn vmulxh_lane_f16(a: f16, b: float16x4_t) -> f16 { #[cfg(not(target_arch = "arm64ec"))] pub fn vmulxh_laneq_f16(a: f16, b: float16x8_t) -> f16 { static_assert_uimm_bits!(LANE, 3); - unsafe { vmulxh_f16(a, simd_extract!(b, LANE as u32)) } + vmulxh_f16(a, vgetq_lane_f16::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulxq_lane_f64(a: float64x2_t, b: float64x1_t) -> float64x2_t { static_assert!(LANE == 0); - unsafe { vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } + vmulxq_f64(a, vdupq_lane_f64::(b)) } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fneg))] @@ -16036,7 +14157,7 @@ pub fn vneg_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fneg))] @@ -16045,7 +14166,7 @@ pub fn vnegq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(neg))] @@ -16054,7 +14175,7 @@ pub fn vneg_s64(a: int64x1_t) -> int64x1_t { } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(neg))] @@ -16063,7 +14184,7 @@ pub fn vnegq_s64(a: int64x2_t) -> int64x2_t { } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(neg))] @@ -16072,7 +14193,7 @@ pub fn vnegd_s64(a: i64) -> i64 { } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -16082,33 +14203,29 @@ pub fn vnegh_f16(a: f16) -> f16 { } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub fn vpaddd_f64(a: float64x2_t) -> f64 { - unsafe { - let a1: f64 = simd_extract!(a, 0); - let a2: f64 = simd_extract!(a, 1); - a1 + a2 - } + let a1: f64 = vgetq_lane_f64::<0>(a); + let a2: f64 = vgetq_lane_f64::<1>(a); + a1 + a2 } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadds_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub fn vpadds_f32(a: float32x2_t) -> f32 { - unsafe { - let a1: f32 = simd_extract!(a, 0); - let a2: f32 = simd_extract!(a, 1); - a1 + a2 - } + let a1: f32 = vget_lane_f32::<0>(a); + let a2: f32 = vget_lane_f32::<1>(a); + a1 + a2 } #[doc = "Add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] @@ -16117,7 +14234,7 @@ pub fn vpaddd_s64(a: int64x2_t) -> i64 { } #[doc = "Add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] @@ -16126,141 +14243,259 @@ pub fn vpaddd_u64(a: uint64x2_t) -> u64 { } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(faddp))] pub fn vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.faddp.v8f16" - )] - fn _vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>()); + simd_add(even, odd) + } +} +#[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(faddp))] +pub fn vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>()); + let ret_val: float16x8_t = simd_add(even, odd); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } - unsafe { _vpaddq_f16(a, b) } } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(faddp))] pub fn vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.faddp.v4f32" - )] - fn _vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>()); + simd_add(even, odd) + } +} +#[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(faddp))] +pub fn vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>()); + let ret_val: float32x4_t = simd_add(even, odd); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } - unsafe { _vpaddq_f32(a, b) } } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(faddp))] pub fn vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.faddp.v2f64" - )] - fn _vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>()); + simd_add(even, odd) + } +} +#[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(faddp))] +pub fn vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>()); + let ret_val: float64x2_t = simd_add(even, odd); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Add Pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s8)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(addp))] +pub fn vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<16>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<16>()); + simd_add(even, odd) } - unsafe { _vpaddq_f64(a, b) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.addp.v16i8" - )] - fn _vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<16>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<16>()); + let ret_val: int8x16_t = simd_add(even, odd); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) } - unsafe { _vpaddq_s8(a, b) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.addp.v8i16" - )] - fn _vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>()); + simd_add(even, odd) + } +} +#[doc = "Add Pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(addp))] +pub fn vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>()); + let ret_val: int16x8_t = simd_add(even, odd); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } - unsafe { _vpaddq_s16(a, b) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.addp.v4i32" - )] - fn _vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>()); + simd_add(even, odd) + } +} +#[doc = "Add Pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(addp))] +pub fn vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>()); + let ret_val: int32x4_t = simd_add(even, odd); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } - unsafe { _vpaddq_s32(a, b) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.addp.v2i64" - )] - fn _vpaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>()); + simd_add(even, odd) + } +} +#[doc = "Add Pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(addp))] +pub fn vpaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { + let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int64x2_t = simd_shuffle!(b, b, [1, 0]); + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>()); + let ret_val: int64x2_t = simd_add(even, odd); + simd_shuffle!(ret_val, ret_val, [1, 0]) } - unsafe { _vpaddq_s64(a, b) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - unsafe { transmute(vpaddq_s8(transmute(a), transmute(b))) } + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<16>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<16>()); + simd_add(even, odd) + } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; unsafe { - let ret_val: uint8x16_t = transmute(vpaddq_s8(transmute(a), transmute(b))); + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<16>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<16>()); + let ret_val: uint8x16_t = simd_add(even, odd); simd_shuffle!( ret_val, ret_val, @@ -16270,84 +14505,103 @@ pub fn vpaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u16)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - unsafe { transmute(vpaddq_s16(transmute(a), transmute(b))) } + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>()); + simd_add(even, odd) + } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u16)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; unsafe { - let ret_val: uint16x8_t = transmute(vpaddq_s16(transmute(a), transmute(b))); + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>()); + let ret_val: uint16x8_t = simd_add(even, odd); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u32)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - unsafe { transmute(vpaddq_s32(transmute(a), transmute(b))) } + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>()); + simd_add(even, odd) + } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u32)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) }; unsafe { - let ret_val: uint32x4_t = transmute(vpaddq_s32(transmute(a), transmute(b))); + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>()); + let ret_val: uint32x4_t = simd_add(even, odd); simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u64)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - unsafe { transmute(vpaddq_s64(transmute(a), transmute(b))) } + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>()); + simd_add(even, odd) + } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u64)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) }; unsafe { - let ret_val: uint64x2_t = transmute(vpaddq_s64(transmute(a), transmute(b))); + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>()); + let ret_val: uint64x2_t = simd_add(even, odd); simd_shuffle!(ret_val, ret_val, [1, 0]) } } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmaxp))] pub fn vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -16361,10 +14615,34 @@ pub fn vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { _vpmax_f16(a, b) } } #[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmaxp))] +pub fn vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxp.v4f16" + )] + fn _vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = _vpmax_f16(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmaxp))] pub fn vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -16378,10 +14656,34 @@ pub fn vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe { _vpmaxq_f16(a, b) } } #[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmaxp))] +pub fn vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxp.v8f16" + )] + fn _vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = _vpmaxq_f16(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmaxnmp))] pub fn vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -16395,25 +14697,73 @@ pub fn vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { _vpmaxnm_f16(a, b) } } #[doc = "Floating-point add pairwise"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmaxnmp))] -pub fn vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub fn vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmaxnmp.v8f16" + link_name = "llvm.aarch64.neon.fmaxnmp.v4f16" )] - fn _vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + fn _vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = _vpmaxnm_f16(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f16)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmaxnmp))] +pub fn vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmp.v8f16" + )] + fn _vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { _vpmaxnmq_f16(a, b) } +} +#[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmaxnmp))] +pub fn vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmp.v8f16" + )] + fn _vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = _vpmaxnmq_f16(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } - unsafe { _vpmaxnmq_f16(a, b) } } #[doc = "Floating-point Maximum Number Pairwise (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmaxnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -16428,8 +14778,31 @@ pub fn vpmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe { _vpmaxnm_f32(a, b) } } #[doc = "Floating-point Maximum Number Pairwise (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fmaxnmp))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vpmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmp.v2f32" + )] + fn _vpmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = _vpmaxnm_f32(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point Maximum Number Pairwise (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmaxnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -16444,8 +14817,31 @@ pub fn vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe { _vpmaxnmq_f32(a, b) } } #[doc = "Floating-point Maximum Number Pairwise (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fmaxnmp))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmp.v4f32" + )] + fn _vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = _vpmaxnmq_f32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point Maximum Number Pairwise (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmaxnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -16459,9 +14855,32 @@ pub fn vpmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } unsafe { _vpmaxnmq_f64(a, b) } } +#[doc = "Floating-point Maximum Number Pairwise (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fmaxnmp))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vpmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmp.v2f64" + )] + fn _vpmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = _vpmaxnmq_f64(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} #[doc = "Floating-point maximum number pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmqd_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmaxnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -16476,8 +14895,29 @@ pub fn vpmaxnmqd_f64(a: float64x2_t) -> f64 { unsafe { _vpmaxnmqd_f64(a) } } #[doc = "Floating-point maximum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmqd_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fmaxnmp))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vpmaxnmqd_f64(a: float64x2_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmv.f64.v2f64" + )] + fn _vpmaxnmqd_f64(a: float64x2_t) -> f64; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + _vpmaxnmqd_f64(a) + } +} +#[doc = "Floating-point maximum number pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnms_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmaxnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -16491,9 +14931,30 @@ pub fn vpmaxnms_f32(a: float32x2_t) -> f32 { } unsafe { _vpmaxnms_f32(a) } } +#[doc = "Floating-point maximum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnms_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fmaxnmp))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vpmaxnms_f32(a: float32x2_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmv.f32.v2f32" + )] + fn _vpmaxnms_f32(a: float32x2_t) -> f32; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + _vpmaxnms_f32(a) + } +} #[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxp))] @@ -16508,8 +14969,31 @@ pub fn vpmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe { _vpmaxq_f32(a, b) } } #[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(fmaxp))] +pub fn vpmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxp.v4f32" + )] + fn _vpmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = _vpmaxq_f32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxp))] @@ -16524,8 +15008,31 @@ pub fn vpmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe { _vpmaxq_f64(a, b) } } #[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(fmaxp))] +pub fn vpmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxp.v2f64" + )] + fn _vpmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = _vpmaxq_f64(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxp))] @@ -16540,8 +15047,37 @@ pub fn vpmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe { _vpmaxq_s8(a, b) } } #[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn vpmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smaxp.v16i8" + )] + fn _vpmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + } + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = _vpmaxq_s8(a, b); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxp))] @@ -16556,8 +15092,31 @@ pub fn vpmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe { _vpmaxq_s16(a, b) } } #[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn vpmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smaxp.v8i16" + )] + fn _vpmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = _vpmaxq_s16(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxp))] @@ -16572,8 +15131,31 @@ pub fn vpmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe { _vpmaxq_s32(a, b) } } #[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn vpmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smaxp.v4i32" + )] + fn _vpmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int32x4_t = _vpmaxq_s32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxp))] @@ -16588,40 +15170,114 @@ pub fn vpmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe { _vpmaxq_u8(a, b) } } #[doc = "Folding maximum of adjacent pairs"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxp))] -pub fn vpmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vpmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.umaxp.v8i16" + link_name = "llvm.aarch64.neon.umaxp.v16i8" )] - fn _vpmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; + fn _vpmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; + } + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = _vpmaxq_u8(a, b); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) } - unsafe { _vpmaxq_u16(a, b) } } #[doc = "Folding maximum of adjacent pairs"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxp))] -pub fn vpmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vpmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.umaxp.v4i32" + link_name = "llvm.aarch64.neon.umaxp.v8i16" )] - fn _vpmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; + fn _vpmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; + } + unsafe { _vpmaxq_u16(a, b) } +} +#[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn vpmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umaxp.v8i16" + )] + fn _vpmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; + } + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = _vpmaxq_u16(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u32)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn vpmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umaxp.v4i32" + )] + fn _vpmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; } unsafe { _vpmaxq_u32(a, b) } } +#[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn vpmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umaxp.v4i32" + )] + fn _vpmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vpmaxq_u32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "Floating-point maximum pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxqd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxp))] @@ -16637,7 +15293,7 @@ pub fn vpmaxqd_f64(a: float64x2_t) -> f64 { } #[doc = "Floating-point maximum pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxs_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxp))] @@ -16653,9 +15309,10 @@ pub fn vpmaxs_f32(a: float32x2_t) -> f32 { } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fminp))] pub fn vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -16669,10 +15326,34 @@ pub fn vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { _vpmin_f16(a, b) } } #[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fminp))] +pub fn vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminp.v4f16" + )] + fn _vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = _vpmin_f16(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fminp))] pub fn vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -16686,10 +15367,34 @@ pub fn vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe { _vpminq_f16(a, b) } } #[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fminp))] +pub fn vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminp.v8f16" + )] + fn _vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = _vpminq_f16(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fminnmp))] pub fn vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -16703,10 +15408,34 @@ pub fn vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { _vpminnm_f16(a, b) } } #[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fminnmp))] +pub fn vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmp.v4f16" + )] + fn _vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = _vpminnm_f16(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fminnmp))] pub fn vpminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -16719,9 +15448,33 @@ pub fn vpminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { } unsafe { _vpminnmq_f16(a, b) } } +#[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fminnmp))] +pub fn vpminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmp.v8f16" + )] + fn _vpminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = _vpminnmq_f16(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} #[doc = "Floating-point Minimum Number Pairwise (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -16736,8 +15489,31 @@ pub fn vpminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe { _vpminnm_f32(a, b) } } #[doc = "Floating-point Minimum Number Pairwise (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fminnmp))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vpminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmp.v2f32" + )] + fn _vpminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = _vpminnm_f32(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point Minimum Number Pairwise (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -16752,8 +15528,31 @@ pub fn vpminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe { _vpminnmq_f32(a, b) } } #[doc = "Floating-point Minimum Number Pairwise (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fminnmp))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vpminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmp.v4f32" + )] + fn _vpminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = _vpminnmq_f32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point Minimum Number Pairwise (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -16767,9 +15566,32 @@ pub fn vpminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } unsafe { _vpminnmq_f64(a, b) } } +#[doc = "Floating-point Minimum Number Pairwise (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fminnmp))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vpminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmp.v2f64" + )] + fn _vpminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = _vpminnmq_f64(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} #[doc = "Floating-point minimum number pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmqd_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -16784,8 +15606,29 @@ pub fn vpminnmqd_f64(a: float64x2_t) -> f64 { unsafe { _vpminnmqd_f64(a) } } #[doc = "Floating-point minimum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmqd_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fminnmp))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vpminnmqd_f64(a: float64x2_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmv.f64.v2f64" + )] + fn _vpminnmqd_f64(a: float64x2_t) -> f64; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + _vpminnmqd_f64(a) + } +} +#[doc = "Floating-point minimum number pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnms_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -16799,9 +15642,30 @@ pub fn vpminnms_f32(a: float32x2_t) -> f32 { } unsafe { _vpminnms_f32(a) } } +#[doc = "Floating-point minimum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnms_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fminnmp))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vpminnms_f32(a: float32x2_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmv.f32.v2f32" + )] + fn _vpminnms_f32(a: float32x2_t) -> f32; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + _vpminnms_f32(a) + } +} #[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminp))] @@ -16816,56 +15680,154 @@ pub fn vpminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe { _vpminq_f32(a, b) } } #[doc = "Folding minimum of adjacent pairs"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminp))] -pub fn vpminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { +pub fn vpminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fminp.v2f64" + link_name = "llvm.aarch64.neon.fminp.v4f32" )] - fn _vpminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + fn _vpminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = _vpminq_f32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } - unsafe { _vpminq_f64(a, b) } } #[doc = "Folding minimum of adjacent pairs"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(sminp))] -pub fn vpminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +#[cfg_attr(test, assert_instr(fminp))] +pub fn vpminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sminp.v16i8" + link_name = "llvm.aarch64.neon.fminp.v2f64" )] - fn _vpminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + fn _vpminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; } - unsafe { _vpminq_s8(a, b) } + unsafe { _vpminq_f64(a, b) } } #[doc = "Folding minimum of adjacent pairs"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(sminp))] -pub fn vpminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +#[cfg_attr(test, assert_instr(fminp))] +pub fn vpminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sminp.v8i16" + link_name = "llvm.aarch64.neon.fminp.v2f64" + )] + fn _vpminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = _vpminq_f64(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s8)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn vpminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sminp.v16i8" + )] + fn _vpminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + } + unsafe { _vpminq_s8(a, b) } +} +#[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn vpminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sminp.v16i8" + )] + fn _vpminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + } + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = _vpminq_s8(a, b); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s16)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn vpminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sminp.v8i16" )] fn _vpminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } unsafe { _vpminq_s16(a, b) } } #[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn vpminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sminp.v8i16" + )] + fn _vpminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = _vpminq_s16(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminp))] @@ -16880,8 +15842,31 @@ pub fn vpminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe { _vpminq_s32(a, b) } } #[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn vpminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sminp.v4i32" + )] + fn _vpminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int32x4_t = _vpminq_s32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminp))] @@ -16896,8 +15881,37 @@ pub fn vpminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe { _vpminq_u8(a, b) } } #[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn vpminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uminp.v16i8" + )] + fn _vpminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; + } + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = _vpminq_u8(a, b); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminp))] @@ -16912,8 +15926,31 @@ pub fn vpminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe { _vpminq_u16(a, b) } } #[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn vpminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uminp.v8i16" + )] + fn _vpminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; + } + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = _vpminq_u16(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminp))] @@ -16927,9 +15964,32 @@ pub fn vpminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } unsafe { _vpminq_u32(a, b) } } +#[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn vpminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uminp.v4i32" + )] + fn _vpminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vpminq_u32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "Floating-point minimum pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminqd_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminp))] @@ -16944,8 +16004,29 @@ pub fn vpminqd_f64(a: float64x2_t) -> f64 { unsafe { _vpminqd_f64(a) } } #[doc = "Floating-point minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminqd_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(fminp))] +pub fn vpminqd_f64(a: float64x2_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminv.f64.v2f64" + )] + fn _vpminqd_f64(a: float64x2_t) -> f64; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + _vpminqd_f64(a) + } +} +#[doc = "Floating-point minimum pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmins_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminp))] @@ -16959,9 +16040,29 @@ pub fn vpmins_f32(a: float32x2_t) -> f32 { } unsafe { _vpmins_f32(a) } } +#[doc = "Floating-point minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmins_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(fminp))] +pub fn vpmins_f32(a: float32x2_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminv.f32.v2f32" + )] + fn _vpmins_f32(a: float32x2_t) -> f32; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + _vpmins_f32(a) + } +} #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] @@ -16977,7 +16078,7 @@ pub fn vqabs_s64(a: int64x1_t) -> int64x1_t { } #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] @@ -16993,25 +16094,25 @@ pub fn vqabsq_s64(a: int64x2_t) -> int64x2_t { } #[doc = "Signed saturating absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsb_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] pub fn vqabsb_s8(a: i8) -> i8 { - unsafe { simd_extract!(vqabs_s8(vdup_n_s8(a)), 0) } + vget_lane_s8::<0>(vqabs_s8(vdup_n_s8(a))) } #[doc = "Signed saturating absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] pub fn vqabsh_s16(a: i16) -> i16 { - unsafe { simd_extract!(vqabs_s16(vdup_n_s16(a)), 0) } + vget_lane_s16::<0>(vqabs_s16(vdup_n_s16(a))) } #[doc = "Signed saturating absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabss_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] @@ -17027,7 +16128,7 @@ pub fn vqabss_s32(a: i32) -> i32 { } #[doc = "Signed saturating absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] @@ -17043,51 +16144,51 @@ pub fn vqabsd_s64(a: i64) -> i64 { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddb_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqadd))] pub fn vqaddb_s8(a: i8, b: i8) -> i8 { let a: int8x8_t = vdup_n_s8(a); let b: int8x8_t = vdup_n_s8(b); - unsafe { simd_extract!(vqadd_s8(a, b), 0) } + vget_lane_s8::<0>(vqadd_s8(a, b)) } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqadd))] pub fn vqaddh_s16(a: i16, b: i16) -> i16 { let a: int16x4_t = vdup_n_s16(a); let b: int16x4_t = vdup_n_s16(b); - unsafe { simd_extract!(vqadd_s16(a, b), 0) } + vget_lane_s16::<0>(vqadd_s16(a, b)) } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddb_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqadd))] pub fn vqaddb_u8(a: u8, b: u8) -> u8 { let a: uint8x8_t = vdup_n_u8(a); let b: uint8x8_t = vdup_n_u8(b); - unsafe { simd_extract!(vqadd_u8(a, b), 0) } + vget_lane_u8::<0>(vqadd_u8(a, b)) } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqadd))] pub fn vqaddh_u16(a: u16, b: u16) -> u16 { let a: uint16x4_t = vdup_n_u16(a); let b: uint16x4_t = vdup_n_u16(b); - unsafe { simd_extract!(vqadd_u16(a, b), 0) } + vget_lane_u16::<0>(vqadd_u16(a, b)) } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadds_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqadd))] @@ -17103,7 +16204,7 @@ pub fn vqadds_s32(a: i32, b: i32) -> i32 { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqadd))] @@ -17119,7 +16220,7 @@ pub fn vqaddd_s64(a: i64, b: i64) -> i64 { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadds_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqadd))] @@ -17135,7 +16236,7 @@ pub fn vqadds_u32(a: u32, b: u32) -> u32 { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqadd))] @@ -17151,9 +16252,9 @@ pub fn vqaddd_u64(a: u64, b: u64) -> u64 { } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlal_high_lane_s16(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { @@ -17162,9 +16263,9 @@ pub fn vqdmlal_high_lane_s16(a: int32x4_t, b: int16x8_t, c: int16x } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlal_high_laneq_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { @@ -17173,9 +16274,9 @@ pub fn vqdmlal_high_laneq_s16(a: int32x4_t, b: int16x8_t, c: int16 } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlal_high_lane_s32(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { @@ -17184,9 +16285,9 @@ pub fn vqdmlal_high_lane_s32(a: int64x2_t, b: int32x4_t, c: int32x } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlal_high_laneq_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { @@ -17195,45 +16296,45 @@ pub fn vqdmlal_high_laneq_s32(a: int64x2_t, b: int32x4_t, c: int32 } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { vqaddq_s32(a, vqdmull_high_n_s16(b, c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { vqaddq_s32(a, vqdmull_high_s16(b, c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { vqaddq_s64(a, vqdmull_high_n_s32(b, c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { vqaddq_s64(a, vqdmull_high_s32(b, c)) } #[doc = "Vector widening saturating doubling multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, N = 2))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlal_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t { @@ -17242,9 +16343,9 @@ pub fn vqdmlal_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t) } #[doc = "Vector widening saturating doubling multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal, N = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlal_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t { @@ -17253,61 +16354,61 @@ pub fn vqdmlal_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlalh_lane_s16(a: i32, b: i16, c: int16x4_t) -> i32 { static_assert_uimm_bits!(LANE, 2); - unsafe { vqdmlalh_s16(a, b, simd_extract!(c, LANE as u32)) } + vqdmlalh_s16(a, b, vget_lane_s16::(c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlalh_laneq_s16(a: i32, b: i16, c: int16x8_t) -> i32 { static_assert_uimm_bits!(LANE, 3); - unsafe { vqdmlalh_s16(a, b, simd_extract!(c, LANE as u32)) } + vqdmlalh_s16(a, b, vgetq_lane_s16::(c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlals_lane_s32(a: i64, b: i32, c: int32x2_t) -> i64 { static_assert_uimm_bits!(LANE, 1); - unsafe { vqdmlals_s32(a, b, simd_extract!(c, LANE as u32)) } + vqdmlals_s32(a, b, vget_lane_s32::(c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlals_laneq_s32(a: i64, b: i32, c: int32x4_t) -> i64 { static_assert_uimm_bits!(LANE, 2); - unsafe { vqdmlals_s32(a, b, simd_extract!(c, LANE as u32)) } + vqdmlals_s32(a, b, vgetq_lane_s32::(c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlalh_s16(a: i32, b: i16, c: i16) -> i32 { let x: int32x4_t = vqdmull_s16(vdup_n_s16(b), vdup_n_s16(c)); - unsafe { vqadds_s32(a, simd_extract!(x, 0)) } + vqadds_s32(a, vgetq_lane_s32::<0>(x)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlal))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -17317,9 +16418,9 @@ pub fn vqdmlals_s32(a: i64, b: i32, c: i32) -> i64 { } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsl_high_lane_s16(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { @@ -17328,9 +16429,9 @@ pub fn vqdmlsl_high_lane_s16(a: int32x4_t, b: int16x8_t, c: int16x } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsl_high_laneq_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { @@ -17339,9 +16440,9 @@ pub fn vqdmlsl_high_laneq_s16(a: int32x4_t, b: int16x8_t, c: int16 } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsl_high_lane_s32(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { @@ -17350,9 +16451,9 @@ pub fn vqdmlsl_high_lane_s32(a: int64x2_t, b: int32x4_t, c: int32x } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsl_high_laneq_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { @@ -17361,45 +16462,45 @@ pub fn vqdmlsl_high_laneq_s32(a: int64x2_t, b: int32x4_t, c: int32 } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { vqsubq_s32(a, vqdmull_high_n_s16(b, c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { vqsubq_s32(a, vqdmull_high_s16(b, c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { vqsubq_s64(a, vqdmull_high_n_s32(b, c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { vqsubq_s64(a, vqdmull_high_s32(b, c)) } #[doc = "Vector widening saturating doubling multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, N = 2))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsl_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t { @@ -17408,9 +16509,9 @@ pub fn vqdmlsl_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t) } #[doc = "Vector widening saturating doubling multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl, N = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsl_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t { @@ -17419,61 +16520,61 @@ pub fn vqdmlsl_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlslh_lane_s16(a: i32, b: i16, c: int16x4_t) -> i32 { static_assert_uimm_bits!(LANE, 2); - unsafe { vqdmlslh_s16(a, b, simd_extract!(c, LANE as u32)) } + vqdmlslh_s16(a, b, vget_lane_s16::(c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlslh_laneq_s16(a: i32, b: i16, c: int16x8_t) -> i32 { static_assert_uimm_bits!(LANE, 3); - unsafe { vqdmlslh_s16(a, b, simd_extract!(c, LANE as u32)) } + vqdmlslh_s16(a, b, vgetq_lane_s16::(c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsls_lane_s32(a: i64, b: i32, c: int32x2_t) -> i64 { static_assert_uimm_bits!(LANE, 1); - unsafe { vqdmlsls_s32(a, b, simd_extract!(c, LANE as u32)) } + vqdmlsls_s32(a, b, vget_lane_s32::(c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsls_laneq_s32(a: i64, b: i32, c: int32x4_t) -> i64 { static_assert_uimm_bits!(LANE, 2); - unsafe { vqdmlsls_s32(a, b, simd_extract!(c, LANE as u32)) } + vqdmlsls_s32(a, b, vgetq_lane_s32::(c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlslh_s16(a: i32, b: i16, c: i16) -> i32 { let x: int32x4_t = vqdmull_s16(vdup_n_s16(b), vdup_n_s16(c)); - unsafe { vqsubs_s32(a, simd_extract!(x, 0)) } + vqsubs_s32(a, vgetq_lane_s32::<0>(x)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlsl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -17483,336 +16584,300 @@ pub fn vqdmlsls_s32(a: i64, b: i32, c: i32) -> i64 { } #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulh_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vqdmulh_s16(a, vdup_n_s16(simd_extract!(b, LANE as u32))) } + vqdmulh_s16(a, vdup_n_s16(vget_lane_s16::(b))) } #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulhq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vqdmulhq_s16(a, vdupq_n_s16(simd_extract!(b, LANE as u32))) } + vqdmulhq_s16(a, vdupq_n_s16(vget_lane_s16::(b))) } #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulh_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vqdmulh_s32(a, vdup_n_s32(simd_extract!(b, LANE as u32))) } + vqdmulh_s32(a, vdup_n_s32(vget_lane_s32::(b))) } #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulhq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vqdmulhq_s32(a, vdupq_n_s32(simd_extract!(b, LANE as u32))) } + vqdmulhq_s32(a, vdupq_n_s32(vget_lane_s32::(b))) } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulhh_lane_s16(a: i16, b: int16x4_t) -> i16 { static_assert_uimm_bits!(N, 2); - unsafe { - let b: i16 = simd_extract!(b, N as u32); - vqdmulhh_s16(a, b) - } + let b: i16 = vget_lane_s16::(b); + vqdmulhh_s16(a, b) } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulhh_laneq_s16(a: i16, b: int16x8_t) -> i16 { static_assert_uimm_bits!(N, 3); - unsafe { - let b: i16 = simd_extract!(b, N as u32); - vqdmulhh_s16(a, b) - } + let b: i16 = vgetq_lane_s16::(b); + vqdmulhh_s16(a, b) } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulhh_s16(a: i16, b: i16) -> i16 { let a: int16x4_t = vdup_n_s16(a); let b: int16x4_t = vdup_n_s16(b); - unsafe { simd_extract!(vqdmulh_s16(a, b), 0) } + vget_lane_s16::<0>(vqdmulh_s16(a, b)) } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulhs_s32(a: i32, b: i32) -> i32 { let a: int32x2_t = vdup_n_s32(a); let b: int32x2_t = vdup_n_s32(b); - unsafe { simd_extract!(vqdmulh_s32(a, b), 0) } + vget_lane_s32::<0>(vqdmulh_s32(a, b)) } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulhs_lane_s32(a: i32, b: int32x2_t) -> i32 { static_assert_uimm_bits!(N, 1); - unsafe { - let b: i32 = simd_extract!(b, N as u32); - vqdmulhs_s32(a, b) - } + let b: i32 = vget_lane_s32::(b); + vqdmulhs_s32(a, b) } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulhs_laneq_s32(a: i32, b: int32x4_t) -> i32 { static_assert_uimm_bits!(N, 2); - unsafe { - let b: i32 = simd_extract!(b, N as u32); - vqdmulhs_s32(a, b) - } + let b: i32 = vgetq_lane_s32::(b); + vqdmulhs_s32(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmull_high_lane_s16(a: int16x8_t, b: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(N, 2); - unsafe { - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); - vqdmull_s16(a, b) - } + let a = vget_high_s16(a); + let b = vdup_lane_s16::(b); + vqdmull_s16(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmull_high_laneq_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { static_assert_uimm_bits!(N, 2); - unsafe { - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); - vqdmull_s32(a, b) - } + let a = vget_high_s32(a); + let b = vdup_laneq_s32::(b); + vqdmull_s32(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2, N = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmull_high_lane_s32(a: int32x4_t, b: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(N, 1); - unsafe { - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); - vqdmull_s32(a, b) - } + let a = vget_high_s32(a); + let b = vdup_lane_s32::(b); + vqdmull_s32(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2, N = 4))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2, N = 4))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmull_high_laneq_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { static_assert_uimm_bits!(N, 3); - unsafe { - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); - vqdmull_s16(a, b) - } + let a = vget_high_s16(a); + let b = vdup_laneq_s16::(b); + vqdmull_s16(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t { - unsafe { - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: int16x4_t = vdup_n_s16(b); - vqdmull_s16(a, b) - } + let a = vget_high_s16(a); + let b = vdup_n_s16(b); + vqdmull_s16(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t { - unsafe { - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: int32x2_t = vdup_n_s32(b); - vqdmull_s32(a, b) - } + let a = vget_high_s32(a); + let b = vdup_n_s32(b); + vqdmull_s32(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { - unsafe { - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - vqdmull_s16(a, b) - } + let a = vget_high_s16(a); + let b = vget_high_s16(b); + vqdmull_s16(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { - unsafe { - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); - vqdmull_s32(a, b) - } + let a = vget_high_s32(a); + let b = vget_high_s32(b); + vqdmull_s32(a, b) } #[doc = "Vector saturating doubling long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull, N = 4))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmull_laneq_s16(a: int16x4_t, b: int16x8_t) -> int32x4_t { static_assert_uimm_bits!(N, 3); - unsafe { - let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); - vqdmull_s16(a, b) - } + let b = vdup_laneq_s16::(b); + vqdmull_s16(a, b) } #[doc = "Vector saturating doubling long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmull_laneq_s32(a: int32x2_t, b: int32x4_t) -> int64x2_t { static_assert_uimm_bits!(N, 2); - unsafe { - let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); - vqdmull_s32(a, b) - } + let b = vdup_laneq_s32::(b); + vqdmull_s32(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmullh_lane_s16(a: i16, b: int16x4_t) -> i32 { static_assert_uimm_bits!(N, 2); - unsafe { - let b: i16 = simd_extract!(b, N as u32); - vqdmullh_s16(a, b) - } + let b: i16 = vget_lane_s16::(b); + vqdmullh_s16(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulls_laneq_s32(a: i32, b: int32x4_t) -> i64 { static_assert_uimm_bits!(N, 2); - unsafe { - let b: i32 = simd_extract!(b, N as u32); - vqdmulls_s32(a, b) - } + let b: i32 = vgetq_lane_s32::(b); + vqdmulls_s32(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull, N = 4))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmullh_laneq_s16(a: i16, b: int16x8_t) -> i32 { static_assert_uimm_bits!(N, 3); - unsafe { - let b: i16 = simd_extract!(b, N as u32); - vqdmullh_s16(a, b) - } + let b: i16 = vgetq_lane_s16::(b); + vqdmullh_s16(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmullh_s16(a: i16, b: i16) -> i32 { let a: int16x4_t = vdup_n_s16(a); let b: int16x4_t = vdup_n_s16(b); - unsafe { simd_extract!(vqdmull_s16(a, b), 0) } + vgetq_lane_s32::<0>(vqdmull_s16(a, b)) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulls_lane_s32(a: i32, b: int32x2_t) -> i64 { static_assert_uimm_bits!(N, 1); - unsafe { - let b: i32 = simd_extract!(b, N as u32); - vqdmulls_s32(a, b) - } + let b: i32 = vget_lane_s32::(b); + vqdmulls_s32(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -17828,73 +16893,61 @@ pub fn vqdmulls_s32(a: i32, b: i32) -> i64 { } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { - unsafe { - simd_shuffle!( - a, - vqmovn_s16(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_s8(a, vqmovn_s16(b)) } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { - unsafe { simd_shuffle!(a, vqmovn_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_s16(a, vqmovn_s32(b)) } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { - unsafe { simd_shuffle!(a, vqmovn_s64(b), [0, 1, 2, 3]) } + vcombine_s32(a, vqmovn_s64(b)) } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqxtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { - unsafe { - simd_shuffle!( - a, - vqmovn_u16(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_u8(a, vqmovn_u16(b)) } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqxtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { - unsafe { simd_shuffle!(a, vqmovn_u32(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_u16(a, vqmovn_u32(b)) } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqxtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { - unsafe { simd_shuffle!(a, vqmovn_u64(b), [0, 1, 2, 3]) } + vcombine_u32(a, vqmovn_u64(b)) } #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -17910,7 +16963,7 @@ pub fn vqmovnd_s64(a: i64) -> i32 { } #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqxtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -17926,103 +16979,97 @@ pub fn vqmovnd_u64(a: u64) -> u32 { } #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovnh_s16(a: i16) -> i8 { - unsafe { simd_extract!(vqmovn_s16(vdupq_n_s16(a)), 0) } + vget_lane_s8::<0>(vqmovn_s16(vdupq_n_s16(a))) } #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovns_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovns_s32(a: i32) -> i16 { - unsafe { simd_extract!(vqmovn_s32(vdupq_n_s32(a)), 0) } + vget_lane_s16::<0>(vqmovn_s32(vdupq_n_s32(a))) } #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnh_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqxtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovnh_u16(a: u16) -> u8 { - unsafe { simd_extract!(vqmovn_u16(vdupq_n_u16(a)), 0) } + vget_lane_u8::<0>(vqmovn_u16(vdupq_n_u16(a))) } #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovns_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqxtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovns_u32(a: u32) -> u16 { - unsafe { simd_extract!(vqmovn_u32(vdupq_n_u32(a)), 0) } + vget_lane_u16::<0>(vqmovn_u32(vdupq_n_u32(a))) } #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtun2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtun2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovun_high_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { - unsafe { - simd_shuffle!( - a, - vqmovun_s16(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_u8(a, vqmovun_s16(b)) } #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtun2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtun2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovun_high_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { - unsafe { simd_shuffle!(a, vqmovun_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_u16(a, vqmovun_s32(b)) } #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtun2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtun2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovun_high_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { - unsafe { simd_shuffle!(a, vqmovun_s64(b), [0, 1, 2, 3]) } + vcombine_u32(a, vqmovun_s64(b)) } #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovunh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtun))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovunh_s16(a: i16) -> u8 { - unsafe { simd_extract!(vqmovun_s16(vdupq_n_s16(a)), 0) } + vget_lane_u8::<0>(vqmovun_s16(vdupq_n_s16(a))) } #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovuns_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtun))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovuns_s32(a: i32) -> u16 { - unsafe { simd_extract!(vqmovun_s32(vdupq_n_s32(a)), 0) } + vget_lane_u16::<0>(vqmovun_s32(vdupq_n_s32(a))) } #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovund_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtun))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovund_s64(a: i64) -> u32 { - unsafe { simd_extract!(vqmovun_s64(vdupq_n_s64(a)), 0) } + vget_lane_u32::<0>(vqmovun_s64(vdupq_n_s64(a))) } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqneg))] @@ -18038,7 +17085,7 @@ pub fn vqneg_s64(a: int64x1_t) -> int64x1_t { } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqneg))] @@ -18054,185 +17101,139 @@ pub fn vqnegq_s64(a: int64x2_t) -> int64x2_t { } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegb_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqneg))] pub fn vqnegb_s8(a: i8) -> i8 { - unsafe { simd_extract!(vqneg_s8(vdup_n_s8(a)), 0) } + vget_lane_s8::<0>(vqneg_s8(vdup_n_s8(a))) } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqneg))] pub fn vqnegh_s16(a: i16) -> i16 { - unsafe { simd_extract!(vqneg_s16(vdup_n_s16(a)), 0) } + vget_lane_s16::<0>(vqneg_s16(vdup_n_s16(a))) } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegs_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqneg))] pub fn vqnegs_s32(a: i32) -> i32 { - unsafe { simd_extract!(vqneg_s32(vdup_n_s32(a)), 0) } + vget_lane_s32::<0>(vqneg_s32(vdup_n_s32(a))) } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqneg))] pub fn vqnegd_s64(a: i64) -> i64 { - unsafe { simd_extract!(vqneg_s64(vdup_n_s64(a)), 0) } + vget_lane_s64::<0>(vqneg_s64(vdup_n_s64(a))) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlah_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: int16x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlah_s16(a, b, c) - } + let c = vdup_lane_s16::(c); + vqrdmlah_s16(a, b, c) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlah_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vqrdmlah_s32(a, b, c) - } + let c = vdup_lane_s32::(c); + vqrdmlah_s32(a, b, c) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlah_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - let c: int16x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlah_s16(a, b, c) - } + let c = vdup_laneq_s16::(c); + vqrdmlah_s16(a, b, c) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlah_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vqrdmlah_s32(a, b, c) - } + let c = vdup_laneq_s32::(c); + vqrdmlah_s32(a, b, c) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlahq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: int16x8_t = simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ); - vqrdmlahq_s16(a, b, c) - } + let c = vdupq_lane_s16::(c); + vqrdmlahq_s16(a, b, c) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlahq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlahq_s32(a, b, c) - } + let c = vdupq_lane_s32::(c); + vqrdmlahq_s32(a, b, c) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlahq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - let c: int16x8_t = simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ); - vqrdmlahq_s16(a, b, c) - } + let c = vdupq_laneq_s16::(c); + vqrdmlahq_s16(a, b, c) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlahq_laneq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlahq_s32(a, b, c) - } + let c = vdupq_laneq_s32::(c); + vqrdmlahq_s32(a, b, c) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -18248,7 +17249,7 @@ pub fn vqrdmlah_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -18264,7 +17265,7 @@ pub fn vqrdmlahq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -18280,7 +17281,7 @@ pub fn vqrdmlah_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -18296,51 +17297,51 @@ pub fn vqrdmlahq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlahh_lane_s16(a: i16, b: i16, c: int16x4_t) -> i16 { static_assert_uimm_bits!(LANE, 2); - unsafe { vqrdmlahh_s16(a, b, simd_extract!(c, LANE as u32)) } + vqrdmlahh_s16(a, b, vget_lane_s16::(c)) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlahh_laneq_s16(a: i16, b: i16, c: int16x8_t) -> i16 { static_assert_uimm_bits!(LANE, 3); - unsafe { vqrdmlahh_s16(a, b, simd_extract!(c, LANE as u32)) } + vqrdmlahh_s16(a, b, vgetq_lane_s16::(c)) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlahs_lane_s32(a: i32, b: i32, c: int32x2_t) -> i32 { static_assert_uimm_bits!(LANE, 1); - unsafe { vqrdmlahs_s32(a, b, simd_extract!(c, LANE as u32)) } + vqrdmlahs_s32(a, b, vget_lane_s32::(c)) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlahs_laneq_s32(a: i32, b: i32, c: int32x4_t) -> i32 { static_assert_uimm_bits!(LANE, 2); - unsafe { vqrdmlahs_s32(a, b, simd_extract!(c, LANE as u32)) } + vqrdmlahs_s32(a, b, vgetq_lane_s32::(c)) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -18348,11 +17349,11 @@ pub fn vqrdmlahh_s16(a: i16, b: i16, c: i16) -> i16 { let a: int16x4_t = vdup_n_s16(a); let b: int16x4_t = vdup_n_s16(b); let c: int16x4_t = vdup_n_s16(c); - unsafe { simd_extract!(vqrdmlah_s16(a, b, c), 0) } + vget_lane_s16::<0>(vqrdmlah_s16(a, b, c)) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -18360,153 +17361,107 @@ pub fn vqrdmlahs_s32(a: i32, b: i32, c: i32) -> i32 { let a: int32x2_t = vdup_n_s32(a); let b: int32x2_t = vdup_n_s32(b); let c: int32x2_t = vdup_n_s32(c); - unsafe { simd_extract!(vqrdmlah_s32(a, b, c), 0) } + vget_lane_s32::<0>(vqrdmlah_s32(a, b, c)) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlsh_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: int16x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlsh_s16(a, b, c) - } + let c = vdup_lane_s16::(c); + vqrdmlsh_s16(a, b, c) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlsh_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vqrdmlsh_s32(a, b, c) - } + let c = vdup_lane_s32::(c); + vqrdmlsh_s32(a, b, c) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlsh_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - let c: int16x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlsh_s16(a, b, c) - } + let c = vdup_laneq_s16::(c); + vqrdmlsh_s16(a, b, c) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlsh_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vqrdmlsh_s32(a, b, c) - } + let c = vdup_laneq_s32::(c); + vqrdmlsh_s32(a, b, c) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlshq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: int16x8_t = simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ); - vqrdmlshq_s16(a, b, c) - } + let c = vdupq_lane_s16::(c); + vqrdmlshq_s16(a, b, c) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlshq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlshq_s32(a, b, c) - } + let c = vdupq_lane_s32::(c); + vqrdmlshq_s32(a, b, c) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlshq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - let c: int16x8_t = simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ); - vqrdmlshq_s16(a, b, c) - } + let c = vdupq_laneq_s16::(c); + vqrdmlshq_s16(a, b, c) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlshq_laneq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlshq_s32(a, b, c) - } + let c = vdupq_laneq_s32::(c); + vqrdmlshq_s32(a, b, c) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -18522,7 +17477,7 @@ pub fn vqrdmlsh_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -18538,7 +17493,7 @@ pub fn vqrdmlshq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -18554,7 +17509,7 @@ pub fn vqrdmlsh_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -18570,51 +17525,51 @@ pub fn vqrdmlshq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlshh_lane_s16(a: i16, b: i16, c: int16x4_t) -> i16 { static_assert_uimm_bits!(LANE, 2); - unsafe { vqrdmlshh_s16(a, b, simd_extract!(c, LANE as u32)) } + vqrdmlshh_s16(a, b, vget_lane_s16::(c)) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlshh_laneq_s16(a: i16, b: i16, c: int16x8_t) -> i16 { static_assert_uimm_bits!(LANE, 3); - unsafe { vqrdmlshh_s16(a, b, simd_extract!(c, LANE as u32)) } + vqrdmlshh_s16(a, b, vgetq_lane_s16::(c)) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlshs_lane_s32(a: i32, b: i32, c: int32x2_t) -> i32 { static_assert_uimm_bits!(LANE, 1); - unsafe { vqrdmlshs_s32(a, b, simd_extract!(c, LANE as u32)) } + vqrdmlshs_s32(a, b, vget_lane_s32::(c)) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlshs_laneq_s32(a: i32, b: i32, c: int32x4_t) -> i32 { static_assert_uimm_bits!(LANE, 2); - unsafe { vqrdmlshs_s32(a, b, simd_extract!(c, LANE as u32)) } + vqrdmlshs_s32(a, b, vgetq_lane_s32::(c)) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -18622,11 +17577,11 @@ pub fn vqrdmlshh_s16(a: i16, b: i16, c: i16) -> i16 { let a: int16x4_t = vdup_n_s16(a); let b: int16x4_t = vdup_n_s16(b); let c: int16x4_t = vdup_n_s16(c); - unsafe { simd_extract!(vqrdmlsh_s16(a, b, c), 0) } + vget_lane_s16::<0>(vqrdmlsh_s16(a, b, c)) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -18634,117 +17589,117 @@ pub fn vqrdmlshs_s32(a: i32, b: i32, c: i32) -> i32 { let a: int32x2_t = vdup_n_s32(a); let b: int32x2_t = vdup_n_s32(b); let c: int32x2_t = vdup_n_s32(c); - unsafe { simd_extract!(vqrdmlsh_s32(a, b, c), 0) } + vget_lane_s32::<0>(vqrdmlsh_s32(a, b, c)) } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrdmulhh_lane_s16(a: i16, b: int16x4_t) -> i16 { static_assert_uimm_bits!(LANE, 2); - unsafe { vqrdmulhh_s16(a, simd_extract!(b, LANE as u32)) } + vqrdmulhh_s16(a, vget_lane_s16::(b)) } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrdmulhh_laneq_s16(a: i16, b: int16x8_t) -> i16 { static_assert_uimm_bits!(LANE, 3); - unsafe { vqrdmulhh_s16(a, simd_extract!(b, LANE as u32)) } + vqrdmulhh_s16(a, vgetq_lane_s16::(b)) } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrdmulhs_lane_s32(a: i32, b: int32x2_t) -> i32 { static_assert_uimm_bits!(LANE, 1); - unsafe { vqrdmulhs_s32(a, simd_extract!(b, LANE as u32)) } + vqrdmulhs_s32(a, vget_lane_s32::(b)) } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrdmulhs_laneq_s32(a: i32, b: int32x4_t) -> i32 { static_assert_uimm_bits!(LANE, 2); - unsafe { vqrdmulhs_s32(a, simd_extract!(b, LANE as u32)) } + vqrdmulhs_s32(a, vgetq_lane_s32::(b)) } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrdmulh))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrdmulhh_s16(a: i16, b: i16) -> i16 { - unsafe { simd_extract!(vqrdmulh_s16(vdup_n_s16(a), vdup_n_s16(b)), 0) } + vget_lane_s16::<0>(vqrdmulh_s16(vdup_n_s16(a), vdup_n_s16(b))) } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrdmulh))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrdmulhs_s32(a: i32, b: i32) -> i32 { - unsafe { simd_extract!(vqrdmulh_s32(vdup_n_s32(a), vdup_n_s32(b)), 0) } + vget_lane_s32::<0>(vqrdmulh_s32(vdup_n_s32(a), vdup_n_s32(b))) } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshlb_s8(a: i8, b: i8) -> i8 { let a: int8x8_t = vdup_n_s8(a); let b: int8x8_t = vdup_n_s8(b); - unsafe { simd_extract!(vqrshl_s8(a, b), 0) } + vget_lane_s8::<0>(vqrshl_s8(a, b)) } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshlh_s16(a: i16, b: i16) -> i16 { let a: int16x4_t = vdup_n_s16(a); let b: int16x4_t = vdup_n_s16(b); - unsafe { simd_extract!(vqrshl_s16(a, b), 0) } + vget_lane_s16::<0>(vqrshl_s16(a, b)) } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshlb_u8(a: u8, b: i8) -> u8 { let a: uint8x8_t = vdup_n_u8(a); let b: int8x8_t = vdup_n_s8(b); - unsafe { simd_extract!(vqrshl_u8(a, b), 0) } + vget_lane_u8::<0>(vqrshl_u8(a, b)) } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshlh_u16(a: u16, b: i16) -> u16 { let a: uint16x4_t = vdup_n_u16(a); let b: int16x4_t = vdup_n_s16(b); - unsafe { simd_extract!(vqrshl_u16(a, b), 0) } + vget_lane_u16::<0>(vqrshl_u16(a, b)) } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshld_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -18760,7 +17715,7 @@ pub fn vqrshld_s64(a: i64, b: i64) -> i64 { } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshls_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -18776,7 +17731,7 @@ pub fn vqrshls_s32(a: i32, b: i32) -> i32 { } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshls_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -18792,7 +17747,7 @@ pub fn vqrshls_u32(a: u32, b: i32) -> u32 { } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshld_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -18808,85 +17763,73 @@ pub fn vqrshld_u64(a: u64, b: i64) -> u64 { } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { static_assert!(N >= 1 && N <= 8); - unsafe { - simd_shuffle!( - a, - vqrshrn_n_s16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_s8(a, vqrshrn_n_s16::(b)) } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { static_assert!(N >= 1 && N <= 16); - unsafe { simd_shuffle!(a, vqrshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_s16(a, vqrshrn_n_s32::(b)) } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); - unsafe { simd_shuffle!(a, vqrshrn_n_s64::(b), [0, 1, 2, 3]) } + vcombine_s32(a, vqrshrn_n_s64::(b)) } #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqrshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqrshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); - unsafe { - simd_shuffle!( - a, - vqrshrn_n_u16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_u8(a, vqrshrn_n_u16::(b)) } #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqrshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqrshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); - unsafe { simd_shuffle!(a, vqrshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_u16(a, vqrshrn_n_u32::(b)) } #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqrshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqrshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); - unsafe { simd_shuffle!(a, vqrshrn_n_u64::(b), [0, 1, 2, 3]) } + vcombine_u32(a, vqrshrn_n_u64::(b)) } #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] @@ -18894,11 +17837,11 @@ pub fn vqrshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x pub fn vqrshrnd_n_u64(a: u64) -> u32 { static_assert!(N >= 1 && N <= 32); let a: uint64x2_t = vdupq_n_u64(a); - unsafe { simd_extract!(vqrshrn_n_u64::(a), 0) } + vget_lane_u32::<0>(vqrshrn_n_u64::(a)) } #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] @@ -18906,11 +17849,11 @@ pub fn vqrshrnd_n_u64(a: u64) -> u32 { pub fn vqrshrnh_n_u16(a: u16) -> u8 { static_assert!(N >= 1 && N <= 8); let a: uint16x8_t = vdupq_n_u16(a); - unsafe { simd_extract!(vqrshrn_n_u16::(a), 0) } + vget_lane_u8::<0>(vqrshrn_n_u16::(a)) } #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] @@ -18918,11 +17861,11 @@ pub fn vqrshrnh_n_u16(a: u16) -> u8 { pub fn vqrshrns_n_u32(a: u32) -> u16 { static_assert!(N >= 1 && N <= 16); let a: uint32x4_t = vdupq_n_u32(a); - unsafe { simd_extract!(vqrshrn_n_u32::(a), 0) } + vget_lane_u16::<0>(vqrshrn_n_u32::(a)) } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] @@ -18930,11 +17873,11 @@ pub fn vqrshrns_n_u32(a: u32) -> u16 { pub fn vqrshrnh_n_s16(a: i16) -> i8 { static_assert!(N >= 1 && N <= 8); let a: int16x8_t = vdupq_n_s16(a); - unsafe { simd_extract!(vqrshrn_n_s16::(a), 0) } + vget_lane_s8::<0>(vqrshrn_n_s16::(a)) } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] @@ -18942,11 +17885,11 @@ pub fn vqrshrnh_n_s16(a: i16) -> i8 { pub fn vqrshrns_n_s32(a: i32) -> i16 { static_assert!(N >= 1 && N <= 16); let a: int32x4_t = vdupq_n_s32(a); - unsafe { simd_extract!(vqrshrn_n_s32::(a), 0) } + vget_lane_s16::<0>(vqrshrn_n_s32::(a)) } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] @@ -18954,50 +17897,44 @@ pub fn vqrshrns_n_s32(a: i32) -> i16 { pub fn vqrshrnd_n_s64(a: i64) -> i32 { static_assert!(N >= 1 && N <= 32); let a: int64x2_t = vdupq_n_s64(a); - unsafe { simd_extract!(vqrshrn_n_s64::(a), 0) } + vget_lane_s32::<0>(vqrshrn_n_s64::(a)) } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrun2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrun2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshrun_high_n_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); - unsafe { - simd_shuffle!( - a, - vqrshrun_n_s16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_u8(a, vqrshrun_n_s16::(b)) } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrun2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrun2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshrun_high_n_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); - unsafe { simd_shuffle!(a, vqrshrun_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_u16(a, vqrshrun_n_s32::(b)) } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrun2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrun2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshrun_high_n_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); - unsafe { simd_shuffle!(a, vqrshrun_n_s64::(b), [0, 1, 2, 3]) } + vcombine_u32(a, vqrshrun_n_s64::(b)) } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrund_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrun, N = 2))] #[rustc_legacy_const_generics(1)] @@ -19005,11 +17942,11 @@ pub fn vqrshrun_high_n_s64(a: uint32x2_t, b: int64x2_t) -> uint32x pub fn vqrshrund_n_s64(a: i64) -> u32 { static_assert!(N >= 1 && N <= 32); let a: int64x2_t = vdupq_n_s64(a); - unsafe { simd_extract!(vqrshrun_n_s64::(a), 0) } + vget_lane_u32::<0>(vqrshrun_n_s64::(a)) } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrunh_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrun, N = 2))] #[rustc_legacy_const_generics(1)] @@ -19017,11 +17954,11 @@ pub fn vqrshrund_n_s64(a: i64) -> u32 { pub fn vqrshrunh_n_s16(a: i16) -> u8 { static_assert!(N >= 1 && N <= 8); let a: int16x8_t = vdupq_n_s16(a); - unsafe { simd_extract!(vqrshrun_n_s16::(a), 0) } + vget_lane_u8::<0>(vqrshrun_n_s16::(a)) } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshruns_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrun, N = 2))] #[rustc_legacy_const_generics(1)] @@ -19029,159 +17966,159 @@ pub fn vqrshrunh_n_s16(a: i16) -> u8 { pub fn vqrshruns_n_s32(a: i32) -> u16 { static_assert!(N >= 1 && N <= 16); let a: int32x4_t = vdupq_n_s32(a); - unsafe { simd_extract!(vqrshrun_n_s32::(a), 0) } + vget_lane_u16::<0>(vqrshrun_n_s32::(a)) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshlb_n_s8(a: i8) -> i8 { static_assert_uimm_bits!(N, 3); - unsafe { simd_extract!(vqshl_n_s8::(vdup_n_s8(a)), 0) } + vget_lane_s8::<0>(vqshl_n_s8::(vdup_n_s8(a))) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshld_n_s64(a: i64) -> i64 { static_assert_uimm_bits!(N, 6); - unsafe { simd_extract!(vqshl_n_s64::(vdup_n_s64(a)), 0) } + vget_lane_s64::<0>(vqshl_n_s64::(vdup_n_s64(a))) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshlh_n_s16(a: i16) -> i16 { static_assert_uimm_bits!(N, 4); - unsafe { simd_extract!(vqshl_n_s16::(vdup_n_s16(a)), 0) } + vget_lane_s16::<0>(vqshl_n_s16::(vdup_n_s16(a))) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshls_n_s32(a: i32) -> i32 { static_assert_uimm_bits!(N, 5); - unsafe { simd_extract!(vqshl_n_s32::(vdup_n_s32(a)), 0) } + vget_lane_s32::<0>(vqshl_n_s32::(vdup_n_s32(a))) } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshlb_n_u8(a: u8) -> u8 { static_assert_uimm_bits!(N, 3); - unsafe { simd_extract!(vqshl_n_u8::(vdup_n_u8(a)), 0) } + vget_lane_u8::<0>(vqshl_n_u8::(vdup_n_u8(a))) } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshld_n_u64(a: u64) -> u64 { static_assert_uimm_bits!(N, 6); - unsafe { simd_extract!(vqshl_n_u64::(vdup_n_u64(a)), 0) } + vget_lane_u64::<0>(vqshl_n_u64::(vdup_n_u64(a))) } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshlh_n_u16(a: u16) -> u16 { static_assert_uimm_bits!(N, 4); - unsafe { simd_extract!(vqshl_n_u16::(vdup_n_u16(a)), 0) } + vget_lane_u16::<0>(vqshl_n_u16::(vdup_n_u16(a))) } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshls_n_u32(a: u32) -> u32 { static_assert_uimm_bits!(N, 5); - unsafe { simd_extract!(vqshl_n_u32::(vdup_n_u32(a)), 0) } + vget_lane_u32::<0>(vqshl_n_u32::(vdup_n_u32(a))) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshlb_s8(a: i8, b: i8) -> i8 { let c: int8x8_t = vqshl_s8(vdup_n_s8(a), vdup_n_s8(b)); - unsafe { simd_extract!(c, 0) } + vget_lane_s8::<0>(c) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshlh_s16(a: i16, b: i16) -> i16 { let c: int16x4_t = vqshl_s16(vdup_n_s16(a), vdup_n_s16(b)); - unsafe { simd_extract!(c, 0) } + vget_lane_s16::<0>(c) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshls_s32(a: i32, b: i32) -> i32 { let c: int32x2_t = vqshl_s32(vdup_n_s32(a), vdup_n_s32(b)); - unsafe { simd_extract!(c, 0) } + vget_lane_s32::<0>(c) } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshlb_u8(a: u8, b: i8) -> u8 { let c: uint8x8_t = vqshl_u8(vdup_n_u8(a), vdup_n_s8(b)); - unsafe { simd_extract!(c, 0) } + vget_lane_u8::<0>(c) } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshlh_u16(a: u16, b: i16) -> u16 { let c: uint16x4_t = vqshl_u16(vdup_n_u16(a), vdup_n_s16(b)); - unsafe { simd_extract!(c, 0) } + vget_lane_u16::<0>(c) } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshls_u32(a: u32, b: i32) -> u32 { let c: uint32x2_t = vqshl_u32(vdup_n_u32(a), vdup_n_s32(b)); - unsafe { simd_extract!(c, 0) } + vget_lane_u32::<0>(c) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19197,7 +18134,7 @@ pub fn vqshld_s64(a: i64, b: i64) -> i64 { } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19213,129 +18150,117 @@ pub fn vqshld_u64(a: u64, b: i64) -> u64 { } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlub_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshlub_n_s8(a: i8) -> u8 { static_assert_uimm_bits!(N, 3); - unsafe { simd_extract!(vqshlu_n_s8::(vdup_n_s8(a)), 0) } + vget_lane_u8::<0>(vqshlu_n_s8::(vdup_n_s8(a))) } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlud_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshlud_n_s64(a: i64) -> u64 { static_assert_uimm_bits!(N, 6); - unsafe { simd_extract!(vqshlu_n_s64::(vdup_n_s64(a)), 0) } + vget_lane_u64::<0>(vqshlu_n_s64::(vdup_n_s64(a))) } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluh_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshluh_n_s16(a: i16) -> u16 { static_assert_uimm_bits!(N, 4); - unsafe { simd_extract!(vqshlu_n_s16::(vdup_n_s16(a)), 0) } + vget_lane_u16::<0>(vqshlu_n_s16::(vdup_n_s16(a))) } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlus_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshlus_n_s32(a: i32) -> u32 { static_assert_uimm_bits!(N, 5); - unsafe { simd_extract!(vqshlu_n_s32::(vdup_n_s32(a)), 0) } + vget_lane_u32::<0>(vqshlu_n_s32::(vdup_n_s32(a))) } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { static_assert!(N >= 1 && N <= 8); - unsafe { - simd_shuffle!( - a, - vqshrn_n_s16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_s8(a, vqshrn_n_s16::(b)) } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { static_assert!(N >= 1 && N <= 16); - unsafe { simd_shuffle!(a, vqshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_s16(a, vqshrn_n_s32::(b)) } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); - unsafe { simd_shuffle!(a, vqshrn_n_s64::(b), [0, 1, 2, 3]) } + vcombine_s32(a, vqshrn_n_s64::(b)) } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); - unsafe { - simd_shuffle!( - a, - vqshrn_n_u16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_u8(a, vqshrn_n_u16::(b)) } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); - unsafe { simd_shuffle!(a, vqshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_u16(a, vqshrn_n_u32::(b)) } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); - unsafe { simd_shuffle!(a, vqshrn_n_u64::(b), [0, 1, 2, 3]) } + vcombine_u32(a, vqshrn_n_u64::(b)) } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnd_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrn, N = 2))] #[rustc_legacy_const_generics(1)] @@ -19353,7 +18278,7 @@ pub fn vqshrnd_n_s64(a: i64) -> i32 { } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnd_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshrn, N = 2))] #[rustc_legacy_const_generics(1)] @@ -19371,167 +18296,161 @@ pub fn vqshrnd_n_u64(a: u64) -> u32 { } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnh_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrnh_n_s16(a: i16) -> i8 { static_assert!(N >= 1 && N <= 8); - unsafe { simd_extract!(vqshrn_n_s16::(vdupq_n_s16(a)), 0) } + vget_lane_s8::<0>(vqshrn_n_s16::(vdupq_n_s16(a))) } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrns_n_s32(a: i32) -> i16 { static_assert!(N >= 1 && N <= 16); - unsafe { simd_extract!(vqshrn_n_s32::(vdupq_n_s32(a)), 0) } + vget_lane_s16::<0>(vqshrn_n_s32::(vdupq_n_s32(a))) } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnh_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrnh_n_u16(a: u16) -> u8 { static_assert!(N >= 1 && N <= 8); - unsafe { simd_extract!(vqshrn_n_u16::(vdupq_n_u16(a)), 0) } + vget_lane_u8::<0>(vqshrn_n_u16::(vdupq_n_u16(a))) } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrns_n_u32(a: u32) -> u16 { static_assert!(N >= 1 && N <= 16); - unsafe { simd_extract!(vqshrn_n_u32::(vdupq_n_u32(a)), 0) } + vget_lane_u16::<0>(vqshrn_n_u32::(vdupq_n_u32(a))) } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrun2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrun2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrun_high_n_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); - unsafe { - simd_shuffle!( - a, - vqshrun_n_s16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_u8(a, vqshrun_n_s16::(b)) } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrun2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrun2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrun_high_n_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); - unsafe { simd_shuffle!(a, vqshrun_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_u16(a, vqshrun_n_s32::(b)) } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrun2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrun2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrun_high_n_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); - unsafe { simd_shuffle!(a, vqshrun_n_s64::(b), [0, 1, 2, 3]) } + vcombine_u32(a, vqshrun_n_s64::(b)) } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrund_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrund_n_s64(a: i64) -> u32 { static_assert!(N >= 1 && N <= 32); - unsafe { simd_extract!(vqshrun_n_s64::(vdupq_n_s64(a)), 0) } + vget_lane_u32::<0>(vqshrun_n_s64::(vdupq_n_s64(a))) } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrunh_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrunh_n_s16(a: i16) -> u8 { static_assert!(N >= 1 && N <= 8); - unsafe { simd_extract!(vqshrun_n_s16::(vdupq_n_s16(a)), 0) } + vget_lane_u8::<0>(vqshrun_n_s16::(vdupq_n_s16(a))) } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshruns_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshruns_n_s32(a: i32) -> u16 { static_assert!(N >= 1 && N <= 16); - unsafe { simd_extract!(vqshrun_n_s32::(vdupq_n_s32(a)), 0) } + vget_lane_u16::<0>(vqshrun_n_s32::(vdupq_n_s32(a))) } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqsub))] pub fn vqsubb_s8(a: i8, b: i8) -> i8 { let a: int8x8_t = vdup_n_s8(a); let b: int8x8_t = vdup_n_s8(b); - unsafe { simd_extract!(vqsub_s8(a, b), 0) } + vget_lane_s8::<0>(vqsub_s8(a, b)) } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqsub))] pub fn vqsubh_s16(a: i16, b: i16) -> i16 { let a: int16x4_t = vdup_n_s16(a); let b: int16x4_t = vdup_n_s16(b); - unsafe { simd_extract!(vqsub_s16(a, b), 0) } + vget_lane_s16::<0>(vqsub_s16(a, b)) } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqsub))] pub fn vqsubb_u8(a: u8, b: u8) -> u8 { let a: uint8x8_t = vdup_n_u8(a); let b: uint8x8_t = vdup_n_u8(b); - unsafe { simd_extract!(vqsub_u8(a, b), 0) } + vget_lane_u8::<0>(vqsub_u8(a, b)) } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqsub))] pub fn vqsubh_u16(a: u16, b: u16) -> u16 { let a: uint16x4_t = vdup_n_u16(a); let b: uint16x4_t = vdup_n_u16(b); - unsafe { simd_extract!(vqsub_u16(a, b), 0) } + vget_lane_u16::<0>(vqsub_u16(a, b)) } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubs_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqsub))] @@ -19547,7 +18466,7 @@ pub fn vqsubs_s32(a: i32, b: i32) -> i32 { } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqsub))] @@ -19563,7 +18482,7 @@ pub fn vqsubd_s64(a: i64, b: i64) -> i64 { } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubs_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqsub))] @@ -19579,7 +18498,7 @@ pub fn vqsubs_u32(a: u32, b: u32) -> u32 { } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqsub))] @@ -19595,7 +18514,7 @@ pub fn vqsubd_u64(a: u64, b: u64) -> u64 { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19611,7 +18530,7 @@ fn vqtbl1(a: int8x16_t, b: uint8x8_t) -> int8x8_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19627,7 +18546,8 @@ fn vqtbl1q(a: int8x16_t, b: uint8x16_t) -> int8x16_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19635,8 +18555,25 @@ pub fn vqtbl1_s8(a: int8x16_t, b: uint8x8_t) -> int8x8_t { vqtbl1(a, b) } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl1_s8(a: int8x16_t, b: uint8x8_t) -> int8x8_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = vqtbl1(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19644,8 +18581,30 @@ pub fn vqtbl1q_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t { vqtbl1q(a, b) } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl1q_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = vqtbl1q(a, b); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19653,8 +18612,25 @@ pub fn vqtbl1_u8(a: uint8x16_t, b: uint8x8_t) -> uint8x8_t { unsafe { transmute(vqtbl1(transmute(a), b)) } } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl1_u8(a: uint8x16_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = transmute(vqtbl1(transmute(a), b)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19662,8 +18638,30 @@ pub fn vqtbl1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe { transmute(vqtbl1q(transmute(a), b)) } } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = transmute(vqtbl1q(transmute(a), b)); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19671,8 +18669,25 @@ pub fn vqtbl1_p8(a: poly8x16_t, b: uint8x8_t) -> poly8x8_t { unsafe { transmute(vqtbl1(transmute(a), b)) } } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl1_p8(a: poly8x16_t, b: uint8x8_t) -> poly8x8_t { + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = transmute(vqtbl1(transmute(a), b)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19680,8 +18695,29 @@ pub fn vqtbl1q_p8(a: poly8x16_t, b: uint8x16_t) -> poly8x16_t { unsafe { transmute(vqtbl1q(transmute(a), b)) } } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl1q_p8(a: poly8x16_t, b: uint8x16_t) -> poly8x16_t { + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = transmute(vqtbl1q(transmute(a), b)); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19697,7 +18733,7 @@ fn vqtbl2(a: int8x16_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19713,7 +18749,8 @@ fn vqtbl2q(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19721,8 +18758,34 @@ pub fn vqtbl2_s8(a: int8x16x2_t, b: uint8x8_t) -> int8x8_t { vqtbl2(a.0, a.1, b) } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl2_s8(a: int8x16x2_t, b: uint8x8_t) -> int8x8_t { + let mut a: int8x16x2_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = vqtbl2(a.0, a.1, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19730,8 +18793,38 @@ pub fn vqtbl2q_s8(a: int8x16x2_t, b: uint8x16_t) -> int8x16_t { vqtbl2q(a.0, a.1, b) } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl2q_s8(a: int8x16x2_t, b: uint8x16_t) -> int8x16_t { + let mut a: int8x16x2_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = vqtbl2q(a.0, a.1, b); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_u8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] @@ -19741,36 +18834,32 @@ pub fn vqtbl2_u8(a: uint8x16x2_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_u8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbl2_u8(a: uint8x16x2_t, b: uint8x8_t) -> uint8x8_t { let mut a: uint8x16x2_t = a; - a.0 = unsafe { - simd_shuffle!( + unsafe { + a.0 = simd_shuffle!( a.0, a.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( + ); + a.1 = simd_shuffle!( a.1, a.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { + ); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); let ret_val: uint8x8_t = transmute(vqtbl2(transmute(a.0), transmute(a.1), b)); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_u8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] @@ -19780,30 +18869,26 @@ pub fn vqtbl2q_u8(a: uint8x16x2_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_u8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbl2q_u8(a: uint8x16x2_t, b: uint8x16_t) -> uint8x16_t { let mut a: uint8x16x2_t = a; - a.0 = unsafe { - simd_shuffle!( + unsafe { + a.0 = simd_shuffle!( a.0, a.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( + ); + a.1 = simd_shuffle!( a.1, a.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { + ); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); let ret_val: uint8x16_t = transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)); simd_shuffle!( ret_val, @@ -19814,7 +18899,7 @@ pub fn vqtbl2q_u8(a: uint8x16x2_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] @@ -19824,36 +18909,32 @@ pub fn vqtbl2_p8(a: poly8x16x2_t, b: uint8x8_t) -> poly8x8_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbl2_p8(a: poly8x16x2_t, b: uint8x8_t) -> poly8x8_t { let mut a: poly8x16x2_t = a; - a.0 = unsafe { - simd_shuffle!( + unsafe { + a.0 = simd_shuffle!( a.0, a.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( + ); + a.1 = simd_shuffle!( a.1, a.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { + ); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); let ret_val: poly8x8_t = transmute(vqtbl2(transmute(a.0), transmute(a.1), b)); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] @@ -19863,30 +18944,26 @@ pub fn vqtbl2q_p8(a: poly8x16x2_t, b: uint8x16_t) -> poly8x16_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbl2q_p8(a: poly8x16x2_t, b: uint8x16_t) -> poly8x16_t { let mut a: poly8x16x2_t = a; - a.0 = unsafe { - simd_shuffle!( + unsafe { + a.0 = simd_shuffle!( a.0, a.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( + ); + a.1 = simd_shuffle!( a.1, a.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { + ); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); let ret_val: poly8x16_t = transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)); simd_shuffle!( ret_val, @@ -19897,7 +18974,7 @@ pub fn vqtbl2q_p8(a: poly8x16x2_t, b: uint8x16_t) -> poly8x16_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19913,7 +18990,7 @@ fn vqtbl3(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x8_t) -> int8x8_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19929,7 +19006,8 @@ fn vqtbl3q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x16_t) -> int8x16_t } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19937,56 +19015,116 @@ pub fn vqtbl3_s8(a: int8x16x3_t, b: uint8x8_t) -> int8x8_t { vqtbl3(a.0, a.1, a.2, b) } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl3q_s8(a: int8x16x3_t, b: uint8x16_t) -> int8x16_t { - vqtbl3q(a.0, a.1, a.2, b) +pub fn vqtbl3_s8(a: int8x16x3_t, b: uint8x8_t) -> int8x8_t { + let mut a: int8x16x3_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.2 = simd_shuffle!( + a.2, + a.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = vqtbl3(a.0, a.1, a.2, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_s8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t { - unsafe { transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)) } +pub fn vqtbl3q_s8(a: int8x16x3_t, b: uint8x16_t) -> int8x16_t { + vqtbl3q(a.0, a.1, a.2, b) } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_s8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t { - let mut a: uint8x16x3_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, +pub fn vqtbl3q_s8(a: int8x16x3_t, b: uint8x16_t) -> int8x16_t { + let mut a: int8x16x3_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, a.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( + ); + a.1 = simd_shuffle!( a.1, a.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( + ); + a.2 = simd_shuffle!( a.2, a.2, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = vqtbl3q(a.0, a.1, a.2, b); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ) - }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; + } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_u8)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t { + unsafe { transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)) } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t { + let mut a: uint8x16x3_t = a; unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.2 = simd_shuffle!( + a.2, + a.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); let ret_val: uint8x8_t = transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) @@ -19994,7 +19132,7 @@ pub fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_u8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] @@ -20004,37 +19142,31 @@ pub fn vqtbl3q_u8(a: uint8x16x3_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_u8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbl3q_u8(a: uint8x16x3_t, b: uint8x16_t) -> uint8x16_t { let mut a: uint8x16x3_t = a; - a.0 = unsafe { - simd_shuffle!( + unsafe { + a.0 = simd_shuffle!( a.0, a.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( + ); + a.1 = simd_shuffle!( a.1, a.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( + ); + a.2 = simd_shuffle!( a.2, a.2, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { + ); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); let ret_val: uint8x16_t = transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)); simd_shuffle!( @@ -20046,7 +19178,7 @@ pub fn vqtbl3q_u8(a: uint8x16x3_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] @@ -20056,36 +19188,30 @@ pub fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t { let mut a: poly8x16x3_t = a; - a.0 = unsafe { - simd_shuffle!( + unsafe { + a.0 = simd_shuffle!( a.0, a.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( + ); + a.1 = simd_shuffle!( a.1, a.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( + ); + a.2 = simd_shuffle!( a.2, a.2, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { + ); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); let ret_val: poly8x8_t = transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) @@ -20093,7 +19219,7 @@ pub fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] @@ -20103,37 +19229,31 @@ pub fn vqtbl3q_p8(a: poly8x16x3_t, b: uint8x16_t) -> poly8x16_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbl3q_p8(a: poly8x16x3_t, b: uint8x16_t) -> poly8x16_t { let mut a: poly8x16x3_t = a; - a.0 = unsafe { - simd_shuffle!( + unsafe { + a.0 = simd_shuffle!( a.0, a.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( + ); + a.1 = simd_shuffle!( a.1, a.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( + ); + a.2 = simd_shuffle!( a.2, a.2, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { + ); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); let ret_val: poly8x16_t = transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)); simd_shuffle!( @@ -20145,7 +19265,7 @@ pub fn vqtbl3q_p8(a: poly8x16x3_t, b: uint8x16_t) -> poly8x16_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20167,7 +19287,7 @@ fn vqtbl4(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x8_t) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20189,7 +19309,8 @@ fn vqtbl4q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x16_t } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20197,8 +19318,44 @@ pub fn vqtbl4_s8(a: int8x16x4_t, b: uint8x8_t) -> int8x8_t { vqtbl4(a.0, a.1, a.2, a.3, b) } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl4_s8(a: int8x16x4_t, b: uint8x8_t) -> int8x8_t { + let mut a: int8x16x4_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.2 = simd_shuffle!( + a.2, + a.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.3 = simd_shuffle!( + a.3, + a.3, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = vqtbl4(a.0, a.1, a.2, a.3, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20206,8 +19363,48 @@ pub fn vqtbl4q_s8(a: int8x16x4_t, b: uint8x16_t) -> int8x16_t { vqtbl4q(a.0, a.1, a.2, a.3, b) } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl4q_s8(a: int8x16x4_t, b: uint8x16_t) -> int8x16_t { + let mut a: int8x16x4_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.2 = simd_shuffle!( + a.2, + a.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.3 = simd_shuffle!( + a.3, + a.3, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = vqtbl4q(a.0, a.1, a.2, a.3, b); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_u8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] @@ -20225,43 +19422,35 @@ pub fn vqtbl4_u8(a: uint8x16x4_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_u8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbl4_u8(a: uint8x16x4_t, b: uint8x8_t) -> uint8x8_t { let mut a: uint8x16x4_t = a; - a.0 = unsafe { - simd_shuffle!( + unsafe { + a.0 = simd_shuffle!( a.0, a.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( + ); + a.1 = simd_shuffle!( a.1, a.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( + ); + a.2 = simd_shuffle!( a.2, a.2, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.3 = unsafe { - simd_shuffle!( + ); + a.3 = simd_shuffle!( a.3, a.3, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { + ); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); let ret_val: uint8x8_t = transmute(vqtbl4( transmute(a.0), transmute(a.1), @@ -20274,7 +19463,7 @@ pub fn vqtbl4_u8(a: uint8x16x4_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_u8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] @@ -20292,44 +19481,36 @@ pub fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_u8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t { let mut a: uint8x16x4_t = a; - a.0 = unsafe { - simd_shuffle!( + unsafe { + a.0 = simd_shuffle!( a.0, a.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( + ); + a.1 = simd_shuffle!( a.1, a.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( + ); + a.2 = simd_shuffle!( a.2, a.2, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.3 = unsafe { - simd_shuffle!( + ); + a.3 = simd_shuffle!( a.3, a.3, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { + ); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); let ret_val: uint8x16_t = transmute(vqtbl4q( transmute(a.0), transmute(a.1), @@ -20346,7 +19527,7 @@ pub fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] @@ -20364,43 +19545,35 @@ pub fn vqtbl4_p8(a: poly8x16x4_t, b: uint8x8_t) -> poly8x8_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbl4_p8(a: poly8x16x4_t, b: uint8x8_t) -> poly8x8_t { let mut a: poly8x16x4_t = a; - a.0 = unsafe { - simd_shuffle!( + unsafe { + a.0 = simd_shuffle!( a.0, a.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( + ); + a.1 = simd_shuffle!( a.1, a.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( + ); + a.2 = simd_shuffle!( a.2, a.2, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.3 = unsafe { - simd_shuffle!( + ); + a.3 = simd_shuffle!( a.3, a.3, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { + ); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); let ret_val: poly8x8_t = transmute(vqtbl4( transmute(a.0), transmute(a.1), @@ -20413,7 +19586,7 @@ pub fn vqtbl4_p8(a: poly8x16x4_t, b: uint8x8_t) -> poly8x8_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] @@ -20431,44 +19604,36 @@ pub fn vqtbl4q_p8(a: poly8x16x4_t, b: uint8x16_t) -> poly8x16_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbl4q_p8(a: poly8x16x4_t, b: uint8x16_t) -> poly8x16_t { let mut a: poly8x16x4_t = a; - a.0 = unsafe { - simd_shuffle!( + unsafe { + a.0 = simd_shuffle!( a.0, a.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( + ); + a.1 = simd_shuffle!( a.1, a.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( + ); + a.2 = simd_shuffle!( a.2, a.2, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.3 = unsafe { - simd_shuffle!( + ); + a.3 = simd_shuffle!( a.3, a.3, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { + ); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); let ret_val: poly8x16_t = transmute(vqtbl4q( transmute(a.0), transmute(a.1), @@ -20485,7 +19650,7 @@ pub fn vqtbl4q_p8(a: poly8x16x4_t, b: uint8x16_t) -> poly8x16_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20501,7 +19666,7 @@ fn vqtbx1(a: int8x8_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20517,7 +19682,8 @@ fn vqtbx1q(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20525,8 +19691,26 @@ pub fn vqtbx1_s8(a: int8x8_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t { vqtbx1(a, b, c) } #[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx1_s8(a: int8x8_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t { + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = vqtbx1(a, b, c); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20534,8 +19718,32 @@ pub fn vqtbx1q_s8(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t { vqtbx1q(a, b, c) } #[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx1q_s8(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = vqtbx1q(a, b, c); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20543,8 +19751,26 @@ pub fn vqtbx1_u8(a: uint8x8_t, b: uint8x16_t, c: uint8x8_t) -> uint8x8_t { unsafe { transmute(vqtbx1(transmute(a), transmute(b), c)) } } #[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx1_u8(a: uint8x8_t, b: uint8x16_t, c: uint8x8_t) -> uint8x8_t { + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = transmute(vqtbx1(transmute(a), transmute(b), c)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20552,8 +19778,32 @@ pub fn vqtbx1q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { unsafe { transmute(vqtbx1q(transmute(a), transmute(b), c)) } } #[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx1q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = transmute(vqtbx1q(transmute(a), transmute(b), c)); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20561,17 +19811,58 @@ pub fn vqtbx1_p8(a: poly8x8_t, b: poly8x16_t, c: uint8x8_t) -> poly8x8_t { unsafe { transmute(vqtbx1(transmute(a), transmute(b), c)) } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx1q_p8(a: poly8x16_t, b: poly8x16_t, c: uint8x16_t) -> poly8x16_t { - unsafe { transmute(vqtbx1q(transmute(a), transmute(b), c)) } +pub fn vqtbx1_p8(a: poly8x8_t, b: poly8x16_t, c: uint8x8_t) -> poly8x8_t { + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = transmute(vqtbx1(transmute(a), transmute(b), c)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_p8)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx1q_p8(a: poly8x16_t, b: poly8x16_t, c: uint8x16_t) -> poly8x16_t { + unsafe { transmute(vqtbx1q(transmute(a), transmute(b), c)) } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx1q_p8(a: poly8x16_t, b: poly8x16_t, c: uint8x16_t) -> poly8x16_t { + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = transmute(vqtbx1q(transmute(a), transmute(b), c)); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20587,7 +19878,7 @@ fn vqtbx2(a: int8x8_t, b: int8x16_t, c: int8x16_t, d: uint8x8_t) -> int8x8_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20603,7 +19894,8 @@ fn vqtbx2q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x16_t) -> int8x16_t } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20611,8 +19903,35 @@ pub fn vqtbx2_s8(a: int8x8_t, b: int8x16x2_t, c: uint8x8_t) -> int8x8_t { vqtbx2(a, b.0, b.1, c) } #[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx2_s8(a: int8x8_t, b: int8x16x2_t, c: uint8x8_t) -> int8x8_t { + let mut b: int8x16x2_t = b; + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = vqtbx2(a, b.0, b.1, c); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20620,8 +19939,40 @@ pub fn vqtbx2q_s8(a: int8x16_t, b: int8x16x2_t, c: uint8x16_t) -> int8x16_t { vqtbx2q(a, b.0, b.1, c) } #[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx2q_s8(a: int8x16_t, b: int8x16x2_t, c: uint8x16_t) -> int8x16_t { + let mut b: int8x16x2_t = b; + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = vqtbx2q(a, b.0, b.1, c); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_u8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] @@ -20631,37 +19982,33 @@ pub fn vqtbx2_u8(a: uint8x8_t, b: uint8x16x2_t, c: uint8x8_t) -> uint8x8_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_u8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbx2_u8(a: uint8x8_t, b: uint8x16x2_t, c: uint8x8_t) -> uint8x8_t { let mut b: uint8x16x2_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( b.0, b.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( + ); + b.1 = simd_shuffle!( b.1, b.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { + ); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); let ret_val: uint8x8_t = transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_u8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] @@ -20671,32 +20018,28 @@ pub fn vqtbx2q_u8(a: uint8x16_t, b: uint8x16x2_t, c: uint8x16_t) -> uint8x16_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_u8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbx2q_u8(a: uint8x16_t, b: uint8x16x2_t, c: uint8x16_t) -> uint8x16_t { let mut b: uint8x16x2_t = b; - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( b.0, b.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( + ); + b.1 = simd_shuffle!( b.1, b.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { + ); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); let ret_val: uint8x16_t = transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)); simd_shuffle!( @@ -20708,7 +20051,7 @@ pub fn vqtbx2q_u8(a: uint8x16_t, b: uint8x16x2_t, c: uint8x16_t) -> uint8x16_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] @@ -20718,37 +20061,33 @@ pub fn vqtbx2_p8(a: poly8x8_t, b: poly8x16x2_t, c: uint8x8_t) -> poly8x8_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbx2_p8(a: poly8x8_t, b: poly8x16x2_t, c: uint8x8_t) -> poly8x8_t { let mut b: poly8x16x2_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( b.0, b.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( + ); + b.1 = simd_shuffle!( b.1, b.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { + ); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); let ret_val: poly8x8_t = transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] @@ -20758,32 +20097,28 @@ pub fn vqtbx2q_p8(a: poly8x16_t, b: poly8x16x2_t, c: uint8x16_t) -> poly8x16_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbx2q_p8(a: poly8x16_t, b: poly8x16x2_t, c: uint8x16_t) -> poly8x16_t { let mut b: poly8x16x2_t = b; - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( b.0, b.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( + ); + b.1 = simd_shuffle!( b.1, b.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { + ); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); let ret_val: poly8x16_t = transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)); simd_shuffle!( @@ -20795,7 +20130,7 @@ pub fn vqtbx2q_p8(a: poly8x16_t, b: poly8x16x2_t, c: uint8x16_t) -> poly8x16_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20812,7 +20147,7 @@ fn vqtbx3(a: int8x8_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x8_t) - } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20834,7 +20169,8 @@ fn vqtbx3q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x16_t } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20842,8 +20178,40 @@ pub fn vqtbx3_s8(a: int8x8_t, b: int8x16x3_t, c: uint8x8_t) -> int8x8_t { vqtbx3(a, b.0, b.1, b.2, c) } #[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx3_s8(a: int8x8_t, b: int8x16x3_t, c: uint8x8_t) -> int8x8_t { + let mut b: int8x16x3_t = b; + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.2 = simd_shuffle!( + b.2, + b.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = vqtbx3(a, b.0, b.1, b.2, c); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20851,8 +20219,45 @@ pub fn vqtbx3q_s8(a: int8x16_t, b: int8x16x3_t, c: uint8x16_t) -> int8x16_t { vqtbx3q(a, b.0, b.1, b.2, c) } #[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx3q_s8(a: int8x16_t, b: int8x16x3_t, c: uint8x16_t) -> int8x16_t { + let mut b: int8x16x3_t = b; + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.2 = simd_shuffle!( + b.2, + b.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = vqtbx3q(a, b.0, b.1, b.2, c); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_u8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] @@ -20870,37 +20275,31 @@ pub fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_u8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t { let mut b: uint8x16x3_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( b.0, b.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( + ); + b.1 = simd_shuffle!( b.1, b.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( + ); + b.2 = simd_shuffle!( b.2, b.2, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { + ); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); let ret_val: uint8x8_t = transmute(vqtbx3( transmute(a), transmute(b.0), @@ -20913,7 +20312,7 @@ pub fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_u8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] @@ -20931,39 +20330,33 @@ pub fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_u8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t { let mut b: uint8x16x3_t = b; - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( b.0, b.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( + ); + b.1 = simd_shuffle!( b.1, b.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( + ); + b.2 = simd_shuffle!( b.2, b.2, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { + ); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); let ret_val: uint8x16_t = transmute(vqtbx3q( transmute(a), transmute(b.0), @@ -20980,7 +20373,7 @@ pub fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] @@ -20998,37 +20391,31 @@ pub fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t { let mut b: poly8x16x3_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( b.0, b.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( + ); + b.1 = simd_shuffle!( b.1, b.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( + ); + b.2 = simd_shuffle!( b.2, b.2, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { + ); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); let ret_val: poly8x8_t = transmute(vqtbx3( transmute(a), transmute(b.0), @@ -21041,7 +20428,7 @@ pub fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] @@ -21059,39 +20446,33 @@ pub fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t { let mut b: poly8x16x3_t = b; - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( b.0, b.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( + ); + b.1 = simd_shuffle!( b.1, b.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( + ); + b.2 = simd_shuffle!( b.2, b.2, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { + ); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); let ret_val: poly8x16_t = transmute(vqtbx3q( transmute(a), transmute(b.0), @@ -21108,7 +20489,7 @@ pub fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -21138,7 +20519,7 @@ fn vqtbx4( } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -21168,7 +20549,8 @@ fn vqtbx4q( } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -21176,87 +20558,158 @@ pub fn vqtbx4_s8(a: int8x8_t, b: int8x16x4_t, c: uint8x8_t) -> int8x8_t { vqtbx4(a, b.0, b.1, b.2, b.3, c) } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx4q_s8(a: int8x16_t, b: int8x16x4_t, c: uint8x16_t) -> int8x16_t { - vqtbx4q(a, b.0, b.1, b.2, b.3, c) -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t { - unsafe { - transmute(vqtbx4( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - )) - } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_s8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t { - let mut b: uint8x16x4_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( +pub fn vqtbx4_s8(a: int8x8_t, b: int8x16x4_t, c: uint8x8_t) -> int8x8_t { + let mut b: int8x16x4_t = b; + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( b.0, b.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( + ); + b.1 = simd_shuffle!( b.1, b.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( + ); + b.2 = simd_shuffle!( b.2, b.2, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.3 = unsafe { - simd_shuffle!( + ); + b.3 = simd_shuffle!( b.3, b.3, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vqtbx4( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - )); + ); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = vqtbx4(a, b.0, b.1, b.2, b.3, c); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_s8)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx4q_s8(a: int8x16_t, b: int8x16x4_t, c: uint8x16_t) -> int8x16_t { + vqtbx4q(a, b.0, b.1, b.2, b.3, c) +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx4q_s8(a: int8x16_t, b: int8x16x4_t, c: uint8x16_t) -> int8x16_t { + let mut b: int8x16x4_t = b; + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.2 = simd_shuffle!( + b.2, + b.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.3 = simd_shuffle!( + b.3, + b.3, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = vqtbx4q(a, b.0, b.1, b.2, b.3, c); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_u8)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t { + unsafe { + transmute(vqtbx4( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + c, + )) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t { + let mut b: uint8x16x4_t = b; + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.2 = simd_shuffle!( + b.2, + b.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.3 = simd_shuffle!( + b.3, + b.3, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = transmute(vqtbx4( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + c, + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_u8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] @@ -21275,46 +20728,38 @@ pub fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8x16_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_u8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8x16_t { let mut b: uint8x16x4_t = b; - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( b.0, b.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( + ); + b.1 = simd_shuffle!( b.1, b.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( + ); + b.2 = simd_shuffle!( b.2, b.2, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.3 = unsafe { - simd_shuffle!( + ); + b.3 = simd_shuffle!( b.3, b.3, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { + ); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); let ret_val: uint8x16_t = transmute(vqtbx4q( transmute(a), transmute(b.0), @@ -21332,7 +20777,7 @@ pub fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8x16_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] @@ -21351,44 +20796,36 @@ pub fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t { let mut b: poly8x16x4_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( b.0, b.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( + ); + b.1 = simd_shuffle!( b.1, b.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( + ); + b.2 = simd_shuffle!( b.2, b.2, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.3 = unsafe { - simd_shuffle!( + ); + b.3 = simd_shuffle!( b.3, b.3, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { + ); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); let ret_val: poly8x8_t = transmute(vqtbx4( transmute(a), transmute(b.0), @@ -21402,7 +20839,7 @@ pub fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] @@ -21421,46 +20858,38 @@ pub fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8x16_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_p8)"] -#[inline(always)] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8x16_t { let mut b: poly8x16x4_t = b; - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( b.0, b.0, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( + ); + b.1 = simd_shuffle!( b.1, b.1, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( + ); + b.2 = simd_shuffle!( b.2, b.2, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.3 = unsafe { - simd_shuffle!( + ); + b.3 = simd_shuffle!( b.3, b.3, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { + ); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); let ret_val: poly8x16_t = transmute(vqtbx4q( transmute(a), transmute(b.0), @@ -21478,7 +20907,7 @@ pub fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8x16_t { } #[doc = "Rotate and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrax1q_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[cfg_attr(test, assert_instr(rax1))] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] @@ -21494,7 +20923,7 @@ pub fn vrax1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(rbit))] @@ -21503,7 +20932,7 @@ pub fn vrbit_s8(a: int8x8_t) -> int8x8_t { } #[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(rbit))] @@ -21512,8 +20941,7 @@ pub fn vrbitq_s8(a: int8x16_t) -> int8x16_t { } #[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(rbit))] @@ -21521,23 +20949,8 @@ pub fn vrbit_u8(a: uint8x8_t) -> uint8x8_t { unsafe { transmute(vrbit_s8(transmute(a))) } } #[doc = "Reverse bit order"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(rbit))] -pub fn vrbit_u8(a: uint8x8_t) -> uint8x8_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vrbit_s8(transmute(a))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(rbit))] @@ -21545,28 +20958,8 @@ pub fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t { unsafe { transmute(vrbitq_s8(transmute(a))) } } #[doc = "Reverse bit order"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(rbit))] -pub fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(vrbitq_s8(transmute(a))); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(rbit))] @@ -21574,51 +20967,17 @@ pub fn vrbit_p8(a: poly8x8_t) -> poly8x8_t { unsafe { transmute(vrbit_s8(transmute(a))) } } #[doc = "Reverse bit order"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(rbit))] -pub fn vrbit_p8(a: poly8x8_t) -> poly8x8_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(vrbit_s8(transmute(a))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(rbit))] pub fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t { unsafe { transmute(vrbitq_s8(transmute(a))) } } -#[doc = "Reverse bit order"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(rbit))] -pub fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(vrbitq_s8(transmute(a))); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecpe))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -21634,7 +20993,7 @@ pub fn vrecpe_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecpe))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -21650,7 +21009,7 @@ pub fn vrecpeq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecped_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecpe))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -21666,7 +21025,7 @@ pub fn vrecped_f64(a: f64) -> f64 { } #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpes_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecpe))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -21682,7 +21041,7 @@ pub fn vrecpes_f32(a: f32) -> f32 { } #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(frecpe))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -21699,7 +21058,7 @@ pub fn vrecpeh_f16(a: f16) -> f16 { } #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -21715,7 +21074,7 @@ pub fn vrecps_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -21731,7 +21090,7 @@ pub fn vrecpsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -21747,7 +21106,7 @@ pub fn vrecpsd_f64(a: f64, b: f64) -> f64 { } #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpss_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -21763,7 +21122,7 @@ pub fn vrecpss_f32(a: f32, b: f32) -> f32 { } #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(frecps))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -21780,7 +21139,7 @@ pub fn vrecpsh_f16(a: f16, b: f16) -> f16 { } #[doc = "Floating-point reciprocal exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecpx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -21796,7 +21155,7 @@ pub fn vrecpxd_f64(a: f64) -> f64 { } #[doc = "Floating-point reciprocal exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxs_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecpx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -21812,7 +21171,7 @@ pub fn vrecpxs_f32(a: f32) -> f32 { } #[doc = "Floating-point reciprocal exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(frecpx))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -21829,423 +21188,344 @@ pub fn vrecpxh_f16(a: f16) -> f16 { } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f16)"] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f64)"] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t { +pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f64)"] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f64)"] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] -#[cfg(not(target_arch = "arm64ec"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t { +pub fn vreinterpret_s64_f64(a: float64x1_t) -> int64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f64)"] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] -#[cfg(not(target_arch = "arm64ec"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t { - unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_u64_f64(a: float64x1_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f64)"] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] -#[cfg(not(target_arch = "arm64ec"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t { +pub fn vreinterpret_p64_f64(a: float64x1_t) -> poly64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f64)"] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] -#[cfg(not(target_arch = "arm64ec"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_p128(a: p128) -> float64x2_t { +pub fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_p128(a: p128) -> float64x2_t { - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t { +pub fn vreinterpret_f64_s64(a: int64x1_t) -> float64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vreinterpret_p64_s64(a: int64x1_t) -> poly64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t { +pub fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t { +pub fn vreinterpret_f64_u64(a: uint64x1_t) -> float64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_p64_u64(a: uint64x1_t) -> poly64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t { +pub fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t { +pub fn vreinterpret_f64_p64(a: poly64x1_t) -> float64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t { - unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_s64_p64(a: poly64x1_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t { +pub fn vreinterpret_u64_p64(a: poly64x1_t) -> uint64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t { - unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t { +pub fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t { - unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t { +pub fn vreinterpretq_f64_p128(a: p128) -> float64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f32)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t { - unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f32)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_s64_f64(a: float64x1_t) -> int64x1_t { +pub fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f32)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t { +pub fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f32)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t { - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t { +pub fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t { - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t { +pub fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t { - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_u64_f64(a: float64x1_t) -> uint64x1_t { +pub fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t { +pub fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t { + unsafe { transmute(a) } +} +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f64)"] +#[inline] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t { - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] @@ -22253,992 +21533,260 @@ pub fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t { - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_p64_f64(a: float64x1_t) -> poly64x1_t { +pub fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 { +pub fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t { +pub fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t { +pub fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t { +pub fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s8)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t { +pub fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s8)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_s64(a: int64x1_t) -> float64x1_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_p64_s64(a: int64x1_t) -> poly64x1_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_u64(a: uint64x1_t) -> float64x1_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_p64_u64(a: uint64x1_t) -> poly64x1_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t { +pub fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s16)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t { +pub fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s16)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s32)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t { +pub fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s32)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t { +pub fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u8)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u8)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t { +pub fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u16)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t { +pub fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t { - unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u16)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_p64(a: poly64x1_t) -> float64x1_t { +pub fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u32)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_s64_p64(a: poly64x1_t) -> int64x1_t { +pub fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u32)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_u64_p64(a: poly64x1_t) -> uint64x1_t { +pub fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p8)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t { +pub fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p8)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t { +pub fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p16)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t { +pub fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p16)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t { +pub fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Floating-point round to 32-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32x_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))] @@ -23254,7 +21802,7 @@ pub fn vrnd32x_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Floating-point round to 32-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32xq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))] @@ -23270,7 +21818,7 @@ pub fn vrnd32xq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Floating-point round to 32-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32xq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))] @@ -23286,7 +21834,7 @@ pub fn vrnd32xq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to 32-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32x_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))] @@ -23298,11 +21846,11 @@ pub fn vrnd32x_f64(a: float64x1_t) -> float64x1_t { )] fn _vrnd32x_f64(a: f64) -> f64; } - unsafe { transmute(_vrnd32x_f64(simd_extract!(a, 0))) } + unsafe { transmute(_vrnd32x_f64(vget_lane_f64::<0>(a))) } } #[doc = "Floating-point round to 32-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32z_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))] @@ -23318,7 +21866,7 @@ pub fn vrnd32z_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Floating-point round to 32-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32zq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))] @@ -23334,7 +21882,7 @@ pub fn vrnd32zq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Floating-point round to 32-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32zq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))] @@ -23350,7 +21898,7 @@ pub fn vrnd32zq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to 32-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32z_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))] @@ -23362,11 +21910,11 @@ pub fn vrnd32z_f64(a: float64x1_t) -> float64x1_t { )] fn _vrnd32z_f64(a: f64) -> f64; } - unsafe { transmute(_vrnd32z_f64(simd_extract!(a, 0))) } + unsafe { transmute(_vrnd32z_f64(vget_lane_f64::<0>(a))) } } #[doc = "Floating-point round to 64-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64x_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))] @@ -23382,7 +21930,7 @@ pub fn vrnd64x_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Floating-point round to 64-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64xq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))] @@ -23398,7 +21946,7 @@ pub fn vrnd64xq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Floating-point round to 64-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64xq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))] @@ -23414,7 +21962,7 @@ pub fn vrnd64xq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to 64-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64x_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))] @@ -23426,11 +21974,11 @@ pub fn vrnd64x_f64(a: float64x1_t) -> float64x1_t { )] fn _vrnd64x_f64(a: f64) -> f64; } - unsafe { transmute(_vrnd64x_f64(simd_extract!(a, 0))) } + unsafe { transmute(_vrnd64x_f64(vget_lane_f64::<0>(a))) } } #[doc = "Floating-point round to 64-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64z_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))] @@ -23446,7 +21994,7 @@ pub fn vrnd64z_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Floating-point round to 64-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64zq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))] @@ -23462,7 +22010,7 @@ pub fn vrnd64zq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Floating-point round to 64-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64zq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))] @@ -23478,7 +22026,7 @@ pub fn vrnd64zq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to 64-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64z_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))] @@ -23490,13 +22038,13 @@ pub fn vrnd64z_f64(a: float64x1_t) -> float64x1_t { )] fn _vrnd64z_f64(a: f64) -> f64; } - unsafe { transmute(_vrnd64z_f64(simd_extract!(a, 0))) } + unsafe { transmute(_vrnd64z_f64(vget_lane_f64::<0>(a))) } } #[doc = "Floating-point round to integral, toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintz))] pub fn vrnd_f16(a: float16x4_t) -> float16x4_t { @@ -23504,9 +22052,9 @@ pub fn vrnd_f16(a: float16x4_t) -> float16x4_t { } #[doc = "Floating-point round to integral, toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintz))] pub fn vrndq_f16(a: float16x8_t) -> float16x8_t { @@ -23514,7 +22062,7 @@ pub fn vrndq_f16(a: float16x8_t) -> float16x8_t { } #[doc = "Floating-point round to integral, toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintz))] @@ -23523,7 +22071,7 @@ pub fn vrnd_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Floating-point round to integral, toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintz))] @@ -23532,7 +22080,7 @@ pub fn vrndq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Floating-point round to integral, toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintz))] @@ -23541,7 +22089,7 @@ pub fn vrnd_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Floating-point round to integral, toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintz))] @@ -23550,9 +22098,9 @@ pub fn vrndq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frinta))] pub fn vrnda_f16(a: float16x4_t) -> float16x4_t { @@ -23560,9 +22108,9 @@ pub fn vrnda_f16(a: float16x4_t) -> float16x4_t { } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frinta))] pub fn vrndaq_f16(a: float16x8_t) -> float16x8_t { @@ -23570,7 +22118,7 @@ pub fn vrndaq_f16(a: float16x8_t) -> float16x8_t { } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinta))] @@ -23579,7 +22127,7 @@ pub fn vrnda_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinta))] @@ -23588,7 +22136,7 @@ pub fn vrndaq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinta))] @@ -23597,7 +22145,7 @@ pub fn vrnda_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinta))] @@ -23606,7 +22154,7 @@ pub fn vrndaq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndah_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -23616,7 +22164,7 @@ pub fn vrndah_f16(a: f16) -> f16 { } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -23626,9 +22174,9 @@ pub fn vrndh_f16(a: f16) -> f16 { } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frinti))] pub fn vrndi_f16(a: float16x4_t) -> float16x4_t { @@ -23643,9 +22191,9 @@ pub fn vrndi_f16(a: float16x4_t) -> float16x4_t { } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frinti))] pub fn vrndiq_f16(a: float16x8_t) -> float16x8_t { @@ -23660,7 +22208,7 @@ pub fn vrndiq_f16(a: float16x8_t) -> float16x8_t { } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinti))] @@ -23676,7 +22224,7 @@ pub fn vrndi_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinti))] @@ -23692,7 +22240,7 @@ pub fn vrndiq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinti))] @@ -23708,7 +22256,7 @@ pub fn vrndi_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinti))] @@ -23724,7 +22272,7 @@ pub fn vrndiq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndih_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -23741,9 +22289,9 @@ pub fn vrndih_f16(a: f16) -> f16 { } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintm))] pub fn vrndm_f16(a: float16x4_t) -> float16x4_t { @@ -23751,9 +22299,9 @@ pub fn vrndm_f16(a: float16x4_t) -> float16x4_t { } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintm))] pub fn vrndmq_f16(a: float16x8_t) -> float16x8_t { @@ -23761,7 +22309,7 @@ pub fn vrndmq_f16(a: float16x8_t) -> float16x8_t { } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintm))] @@ -23770,7 +22318,7 @@ pub fn vrndm_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintm))] @@ -23779,7 +22327,7 @@ pub fn vrndmq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintm))] @@ -23788,7 +22336,7 @@ pub fn vrndm_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintm))] @@ -23797,7 +22345,7 @@ pub fn vrndmq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -23807,7 +22355,7 @@ pub fn vrndmh_f16(a: f16) -> f16 { } #[doc = "Floating-point round to integral, to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintn))] @@ -23823,7 +22371,7 @@ pub fn vrndn_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Floating-point round to integral, to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintn))] @@ -23839,7 +22387,7 @@ pub fn vrndnq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -23856,7 +22404,7 @@ pub fn vrndnh_f16(a: f16) -> f16 { } #[doc = "Floating-point round to integral, to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndns_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintn))] @@ -23872,9 +22420,9 @@ pub fn vrndns_f32(a: f32) -> f32 { } #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintp))] pub fn vrndp_f16(a: float16x4_t) -> float16x4_t { @@ -23882,9 +22430,9 @@ pub fn vrndp_f16(a: float16x4_t) -> float16x4_t { } #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintp))] pub fn vrndpq_f16(a: float16x8_t) -> float16x8_t { @@ -23892,7 +22440,7 @@ pub fn vrndpq_f16(a: float16x8_t) -> float16x8_t { } #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintp))] @@ -23901,7 +22449,7 @@ pub fn vrndp_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintp))] @@ -23910,7 +22458,7 @@ pub fn vrndpq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintp))] @@ -23919,7 +22467,7 @@ pub fn vrndp_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintp))] @@ -23928,7 +22476,7 @@ pub fn vrndpq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndph_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -23938,9 +22486,9 @@ pub fn vrndph_f16(a: f16) -> f16 { } #[doc = "Floating-point round to integral exact, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintx))] pub fn vrndx_f16(a: float16x4_t) -> float16x4_t { @@ -23948,9 +22496,9 @@ pub fn vrndx_f16(a: float16x4_t) -> float16x4_t { } #[doc = "Floating-point round to integral exact, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintx))] pub fn vrndxq_f16(a: float16x8_t) -> float16x8_t { @@ -23958,7 +22506,7 @@ pub fn vrndxq_f16(a: float16x8_t) -> float16x8_t { } #[doc = "Floating-point round to integral exact, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintx))] @@ -23967,7 +22515,7 @@ pub fn vrndx_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Floating-point round to integral exact, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintx))] @@ -23976,7 +22524,7 @@ pub fn vrndxq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Floating-point round to integral exact, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintx))] @@ -23985,7 +22533,7 @@ pub fn vrndx_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Floating-point round to integral exact, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintx))] @@ -23994,7 +22542,7 @@ pub fn vrndxq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -24004,7 +22552,7 @@ pub fn vrndxh_f16(a: f16) -> f16 { } #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshld_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(srshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24020,7 +22568,7 @@ pub fn vrshld_s64(a: i64, b: i64) -> i64 { } #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshld_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(urshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24036,7 +22584,7 @@ pub fn vrshld_u64(a: u64, b: i64) -> u64 { } #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrd_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(srshr, N = 2))] #[rustc_legacy_const_generics(1)] @@ -24047,7 +22595,7 @@ pub fn vrshrd_n_s64(a: i64) -> i64 { } #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrd_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(urshr, N = 2))] #[rustc_legacy_const_generics(1)] @@ -24058,85 +22606,73 @@ pub fn vrshrd_n_u64(a: u64) -> u64 { } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { static_assert!(N >= 1 && N <= 8); - unsafe { - simd_shuffle!( - a, - vrshrn_n_s16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_s8(a, vrshrn_n_s16::(b)) } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { static_assert!(N >= 1 && N <= 16); - unsafe { simd_shuffle!(a, vrshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_s16(a, vrshrn_n_s32::(b)) } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); - unsafe { simd_shuffle!(a, vrshrn_n_s64::(b), [0, 1, 2, 3]) } + vcombine_s32(a, vrshrn_n_s64::(b)) } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); - unsafe { - simd_shuffle!( - a, - vrshrn_n_u16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_u8(a, vrshrn_n_u16::(b)) } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); - unsafe { simd_shuffle!(a, vrshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_u16(a, vrshrn_n_u32::(b)) } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); - unsafe { simd_shuffle!(a, vrshrn_n_u64::(b), [0, 1, 2, 3]) } + vcombine_u32(a, vrshrn_n_u64::(b)) } #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrte))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24152,7 +22688,7 @@ pub fn vrsqrte_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrte))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24168,7 +22704,7 @@ pub fn vrsqrteq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrted_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrte))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24184,7 +22720,7 @@ pub fn vrsqrted_f64(a: f64) -> f64 { } #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtes_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrte))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24200,7 +22736,7 @@ pub fn vrsqrtes_f32(a: f32) -> f32 { } #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(frsqrte))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -24217,7 +22753,7 @@ pub fn vrsqrteh_f16(a: f16) -> f16 { } #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrts))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24233,7 +22769,7 @@ pub fn vrsqrts_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrts))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24249,7 +22785,7 @@ pub fn vrsqrtsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrts))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24265,7 +22801,7 @@ pub fn vrsqrtsd_f64(a: f64, b: f64) -> f64 { } #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtss_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrts))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24281,7 +22817,7 @@ pub fn vrsqrtss_f32(a: f32, b: f32) -> f32 { } #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(test, assert_instr(frsqrts))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -24298,7 +22834,7 @@ pub fn vrsqrtsh_f16(a: f16, b: f16) -> f16 { } #[doc = "Signed rounding shift right and accumulate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsrad_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(srshr, N = 2))] #[rustc_legacy_const_generics(2)] @@ -24310,7 +22846,7 @@ pub fn vrsrad_n_s64(a: i64, b: i64) -> i64 { } #[doc = "Unsigned rounding shift right and accumulate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsrad_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(urshr, N = 2))] #[rustc_legacy_const_generics(2)] @@ -24322,139 +22858,127 @@ pub fn vrsrad_n_u64(a: u64, b: u64) -> u64 { } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "little")] #[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t { - let x: int8x8_t = vrsubhn_s16(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } + vcombine_s8(a, vrsubhn_s16(b, c)) } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "little")] #[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { - let x: int16x4_t = vrsubhn_s32(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_s16(a, vrsubhn_s32(b, c)) } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "little")] #[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t { - let x: int32x2_t = vrsubhn_s64(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) } + vcombine_s32(a, vrsubhn_s64(b, c)) } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "little")] #[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t { - let x: uint8x8_t = vrsubhn_u16(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } + vcombine_u8(a, vrsubhn_u16(b, c)) } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "little")] #[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t { - let x: uint16x4_t = vrsubhn_u32(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_u16(a, vrsubhn_u32(b, c)) } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "little")] #[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t { - let x: uint32x2_t = vrsubhn_u64(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) } + vcombine_u32(a, vrsubhn_u64(b, c)) } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "big")] #[cfg_attr(test, assert_instr(rsubhn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t { - let x: int8x8_t = vrsubhn_s16(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } + vcombine_s8(a, vrsubhn_s16(b, c)) } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "big")] #[cfg_attr(test, assert_instr(rsubhn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { - let x: int16x4_t = vrsubhn_s32(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_s16(a, vrsubhn_s32(b, c)) } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "big")] #[cfg_attr(test, assert_instr(rsubhn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t { - let x: int32x2_t = vrsubhn_s64(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) } + vcombine_s32(a, vrsubhn_s64(b, c)) } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "big")] #[cfg_attr(test, assert_instr(rsubhn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t { - let x: uint8x8_t = vrsubhn_u16(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } + vcombine_u8(a, vrsubhn_u16(b, c)) } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "big")] #[cfg_attr(test, assert_instr(rsubhn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t { - let x: uint16x4_t = vrsubhn_u32(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_u16(a, vrsubhn_u32(b, c)) } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "big")] #[cfg_attr(test, assert_instr(rsubhn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t { - let x: uint32x2_t = vrsubhn_u64(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) } + vcombine_u32(a, vrsubhn_u64(b, c)) } #[doc = "Multi-vector floating-point adjust exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscale_f16)"] -#[inline(always)] +#[inline] #[unstable(feature = "stdarch_neon_fp8", issue = "none")] #[target_feature(enable = "neon,fp8")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))] @@ -24470,7 +22994,7 @@ pub fn vscale_f16(vn: float16x4_t, vm: int16x4_t) -> float16x4_t { } #[doc = "Multi-vector floating-point adjust exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f16)"] -#[inline(always)] +#[inline] #[unstable(feature = "stdarch_neon_fp8", issue = "none")] #[target_feature(enable = "neon,fp8")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))] @@ -24486,7 +23010,7 @@ pub fn vscaleq_f16(vn: float16x8_t, vm: int16x8_t) -> float16x8_t { } #[doc = "Multi-vector floating-point adjust exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscale_f32)"] -#[inline(always)] +#[inline] #[unstable(feature = "stdarch_neon_fp8", issue = "none")] #[target_feature(enable = "neon,fp8")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))] @@ -24502,7 +23026,7 @@ pub fn vscale_f32(vn: float32x2_t, vm: int32x2_t) -> float32x2_t { } #[doc = "Multi-vector floating-point adjust exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f32)"] -#[inline(always)] +#[inline] #[unstable(feature = "stdarch_neon_fp8", issue = "none")] #[target_feature(enable = "neon,fp8")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))] @@ -24518,7 +23042,7 @@ pub fn vscaleq_f32(vn: float32x4_t, vm: int32x4_t) -> float32x4_t { } #[doc = "Multi-vector floating-point adjust exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f64)"] -#[inline(always)] +#[inline] #[unstable(feature = "stdarch_neon_fp8", issue = "none")] #[target_feature(enable = "neon,fp8")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))] @@ -24534,7 +23058,7 @@ pub fn vscaleq_f64(vn: float64x2_t, vm: int64x2_t) -> float64x2_t { } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -24545,7 +23069,8 @@ pub fn vset_lane_f64(a: f64, b: float64x1_t) -> float64x1_t { } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -24554,9 +23079,26 @@ pub fn vsetq_lane_f64(a: f64, b: float64x2_t) -> float64x2_t { static_assert_uimm_bits!(LANE, 1); unsafe { simd_insert!(b, LANE as u32, a) } } +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(nop, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vsetq_lane_f64(a: f64, b: float64x2_t) -> float64x2_t { + static_assert_uimm_bits!(LANE, 1); + unsafe { + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} #[doc = "SHA512 hash update part 2"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512h2q_u64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,sha3")] #[cfg_attr(test, assert_instr(sha512h2))] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] @@ -24570,9 +23112,33 @@ pub fn vsha512h2q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t } unsafe { _vsha512h2q_u64(a, b, c) } } +#[doc = "SHA512 hash update part 2"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512h2q_u64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,sha3")] +#[cfg_attr(test, assert_instr(sha512h2))] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +pub fn vsha512h2q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha512h2" + )] + fn _vsha512h2q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t; + } + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let c: uint64x2_t = simd_shuffle!(c, c, [1, 0]); + let ret_val: uint64x2_t = _vsha512h2q_u64(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} #[doc = "SHA512 hash update part 1"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512hq_u64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,sha3")] #[cfg_attr(test, assert_instr(sha512h))] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] @@ -24586,25 +23152,89 @@ pub fn vsha512hq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t } unsafe { _vsha512hq_u64(a, b, c) } } +#[doc = "SHA512 hash update part 1"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512hq_u64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,sha3")] +#[cfg_attr(test, assert_instr(sha512h))] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +pub fn vsha512hq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha512h" + )] + fn _vsha512hq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t; + } + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let c: uint64x2_t = simd_shuffle!(c, c, [1, 0]); + let ret_val: uint64x2_t = _vsha512hq_u64(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "SHA512 schedule update 0"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su0q_u64)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon,sha3")] +#[cfg_attr(test, assert_instr(sha512su0))] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +pub fn vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha512su0" + )] + fn _vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t; + } + unsafe { _vsha512su0q_u64(a, b) } +} #[doc = "SHA512 schedule update 0"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su0q_u64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon,sha3")] #[cfg_attr(test, assert_instr(sha512su0))] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub fn vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { +pub fn vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha512su0" + )] + fn _vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t; + } + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint64x2_t = _vsha512su0q_u64(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "SHA512 schedule update 1"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su1q_u64)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon,sha3")] +#[cfg_attr(test, assert_instr(sha512su1))] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +pub fn vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.crypto.sha512su0" + link_name = "llvm.aarch64.crypto.sha512su1" )] - fn _vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t; + fn _vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t; } - unsafe { _vsha512su0q_u64(a, b) } + unsafe { _vsha512su1q_u64(a, b, c) } } #[doc = "SHA512 schedule update 1"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su1q_u64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon,sha3")] #[cfg_attr(test, assert_instr(sha512su1))] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] @@ -24616,11 +23246,17 @@ pub fn vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_ )] fn _vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t; } - unsafe { _vsha512su1q_u64(a, b, c) } + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let c: uint64x2_t = simd_shuffle!(c, c, [1, 0]); + let ret_val: uint64x2_t = _vsha512su1q_u64(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshld_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24629,7 +23265,7 @@ pub fn vshld_s64(a: i64, b: i64) -> i64 { } #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshld_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ushl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24638,169 +23274,145 @@ pub fn vshld_u64(a: u64, b: i64) -> u64 { } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sshll2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sshll2, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshll_high_n_s8(a: int8x16_t) -> int16x8_t { static_assert!(N >= 0 && N <= 8); - unsafe { - let b: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - vshll_n_s8::(b) - } + let b = vget_high_s8(a); + vshll_n_s8::(b) } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sshll2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sshll2, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshll_high_n_s16(a: int16x8_t) -> int32x4_t { static_assert!(N >= 0 && N <= 16); - unsafe { - let b: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - vshll_n_s16::(b) - } + let b = vget_high_s16(a); + vshll_n_s16::(b) } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sshll2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sshll2, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshll_high_n_s32(a: int32x4_t) -> int64x2_t { static_assert!(N >= 0 && N <= 32); - unsafe { - let b: int32x2_t = simd_shuffle!(a, a, [2, 3]); - vshll_n_s32::(b) - } + let b = vget_high_s32(a); + vshll_n_s32::(b) } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ushll2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(ushll2, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshll_high_n_u8(a: uint8x16_t) -> uint16x8_t { static_assert!(N >= 0 && N <= 8); - unsafe { - let b: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - vshll_n_u8::(b) - } + let b: uint8x8_t = vget_high_u8(a); + vshll_n_u8::(b) } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ushll2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(ushll2, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshll_high_n_u16(a: uint16x8_t) -> uint32x4_t { static_assert!(N >= 0 && N <= 16); - unsafe { - let b: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - vshll_n_u16::(b) - } + let b: uint16x4_t = vget_high_u16(a); + vshll_n_u16::(b) } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ushll2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(ushll2, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshll_high_n_u32(a: uint32x4_t) -> uint64x2_t { static_assert!(N >= 0 && N <= 32); - unsafe { - let b: uint32x2_t = simd_shuffle!(a, a, [2, 3]); - vshll_n_u32::(b) - } + let b: uint32x2_t = vget_high_u32(a); + vshll_n_u32::(b) } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(shrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { static_assert!(N >= 1 && N <= 8); - unsafe { - simd_shuffle!( - a, - vshrn_n_s16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_s8(a, vshrn_n_s16::(b)) } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(shrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { static_assert!(N >= 1 && N <= 16); - unsafe { simd_shuffle!(a, vshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_s16(a, vshrn_n_s32::(b)) } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(shrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); - unsafe { simd_shuffle!(a, vshrn_n_s64::(b), [0, 1, 2, 3]) } + vcombine_s32(a, vshrn_n_s64::(b)) } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(shrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); - unsafe { - simd_shuffle!( - a, - vshrn_n_u16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_u8(a, vshrn_n_u16::(b)) } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(shrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); - unsafe { simd_shuffle!(a, vshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_u16(a, vshrn_n_u32::(b)) } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(shrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); - unsafe { simd_shuffle!(a, vshrn_n_u64::(b), [0, 1, 2, 3]) } + vcombine_u32(a, vshrn_n_u64::(b)) } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24818,7 +23430,7 @@ pub fn vsli_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24836,7 +23448,7 @@ pub fn vsliq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24854,7 +23466,7 @@ pub fn vsli_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24872,7 +23484,7 @@ pub fn vsliq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24890,7 +23502,7 @@ pub fn vsli_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24908,7 +23520,7 @@ pub fn vsliq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24926,7 +23538,7 @@ pub fn vsli_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24944,7 +23556,7 @@ pub fn vsliq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24955,7 +23567,7 @@ pub fn vsli_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24966,7 +23578,7 @@ pub fn vsliq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24977,7 +23589,7 @@ pub fn vsli_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24988,7 +23600,7 @@ pub fn vsliq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24999,7 +23611,7 @@ pub fn vsli_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -25010,7 +23622,7 @@ pub fn vsliq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -25021,7 +23633,7 @@ pub fn vsli_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -25032,7 +23644,7 @@ pub fn vsliq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -25043,7 +23655,7 @@ pub fn vsli_n_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -25054,7 +23666,7 @@ pub fn vsliq_n_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -25065,7 +23677,7 @@ pub fn vsli_n_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -25076,7 +23688,7 @@ pub fn vsliq_n_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -25087,7 +23699,7 @@ pub fn vsli_n_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -25098,7 +23710,7 @@ pub fn vsliq_n_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { } #[doc = "Shift left and insert"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vslid_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[rustc_legacy_const_generics(2)] @@ -25109,7 +23721,7 @@ pub fn vslid_n_s64(a: i64, b: i64) -> i64 { } #[doc = "Shift left and insert"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vslid_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[rustc_legacy_const_generics(2)] @@ -25120,7 +23732,8 @@ pub fn vslid_n_u64(a: u64, b: u64) -> u64 { } #[doc = "SM3PARTW1"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw1q_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm3partw1))] #[unstable(feature = "stdarch_neon_sm4", issue = "117226")] @@ -25134,9 +23747,33 @@ pub fn vsm3partw1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_ } unsafe { _vsm3partw1q_u32(a, b, c) } } +#[doc = "SM3PARTW1"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw1q_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,sm4")] +#[cfg_attr(test, assert_instr(sm3partw1))] +#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] +pub fn vsm3partw1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sm3partw1" + )] + fn _vsm3partw1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: uint32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsm3partw1q_u32(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SM3PARTW2"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw2q_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm3partw2))] #[unstable(feature = "stdarch_neon_sm4", issue = "117226")] @@ -25150,9 +23787,33 @@ pub fn vsm3partw2q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_ } unsafe { _vsm3partw2q_u32(a, b, c) } } +#[doc = "SM3PARTW2"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw2q_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,sm4")] +#[cfg_attr(test, assert_instr(sm3partw2))] +#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] +pub fn vsm3partw2q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sm3partw2" + )] + fn _vsm3partw2q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: uint32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsm3partw2q_u32(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SM3SS1"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3ss1q_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm3ss1))] #[unstable(feature = "stdarch_neon_sm4", issue = "117226")] @@ -25166,9 +23827,33 @@ pub fn vsm3ss1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { } unsafe { _vsm3ss1q_u32(a, b, c) } } +#[doc = "SM3SS1"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3ss1q_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,sm4")] +#[cfg_attr(test, assert_instr(sm3ss1))] +#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] +pub fn vsm3ss1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sm3ss1" + )] + fn _vsm3ss1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: uint32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsm3ss1q_u32(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SM3TT1A"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt1aq_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm3tt1a, IMM2 = 0))] #[rustc_legacy_const_generics(3)] @@ -25184,9 +23869,35 @@ pub fn vsm3tt1aq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_ } unsafe { _vsm3tt1aq_u32(a, b, c, IMM2 as i64) } } +#[doc = "SM3TT1A"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt1aq_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,sm4")] +#[cfg_attr(test, assert_instr(sm3tt1a, IMM2 = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] +pub fn vsm3tt1aq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(IMM2, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sm3tt1a" + )] + fn _vsm3tt1aq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, n: i64) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: uint32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsm3tt1aq_u32(a, b, c, IMM2 as i64); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SM3TT1B"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt1bq_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm3tt1b, IMM2 = 0))] #[rustc_legacy_const_generics(3)] @@ -25202,9 +23913,35 @@ pub fn vsm3tt1bq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_ } unsafe { _vsm3tt1bq_u32(a, b, c, IMM2 as i64) } } +#[doc = "SM3TT1B"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt1bq_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,sm4")] +#[cfg_attr(test, assert_instr(sm3tt1b, IMM2 = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] +pub fn vsm3tt1bq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(IMM2, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sm3tt1b" + )] + fn _vsm3tt1bq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, n: i64) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: uint32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsm3tt1bq_u32(a, b, c, IMM2 as i64); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SM3TT2A"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt2aq_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm3tt2a, IMM2 = 0))] #[rustc_legacy_const_generics(3)] @@ -25220,9 +23957,35 @@ pub fn vsm3tt2aq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_ } unsafe { _vsm3tt2aq_u32(a, b, c, IMM2 as i64) } } +#[doc = "SM3TT2A"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt2aq_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,sm4")] +#[cfg_attr(test, assert_instr(sm3tt2a, IMM2 = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] +pub fn vsm3tt2aq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(IMM2, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sm3tt2a" + )] + fn _vsm3tt2aq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, n: i64) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: uint32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsm3tt2aq_u32(a, b, c, IMM2 as i64); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SM3TT2B"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt2bq_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm3tt2b, IMM2 = 0))] #[rustc_legacy_const_generics(3)] @@ -25238,9 +24001,35 @@ pub fn vsm3tt2bq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_ } unsafe { _vsm3tt2bq_u32(a, b, c, IMM2 as i64) } } +#[doc = "SM3TT2B"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt2bq_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,sm4")] +#[cfg_attr(test, assert_instr(sm3tt2b, IMM2 = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] +pub fn vsm3tt2bq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(IMM2, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sm3tt2b" + )] + fn _vsm3tt2bq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, n: i64) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: uint32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsm3tt2bq_u32(a, b, c, IMM2 as i64); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SM4 key"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4ekeyq_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm4ekey))] #[unstable(feature = "stdarch_neon_sm4", issue = "117226")] @@ -25254,9 +24043,32 @@ pub fn vsm4ekeyq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } unsafe { _vsm4ekeyq_u32(a, b) } } +#[doc = "SM4 key"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4ekeyq_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,sm4")] +#[cfg_attr(test, assert_instr(sm4ekey))] +#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] +pub fn vsm4ekeyq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sm4ekey" + )] + fn _vsm4ekeyq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsm4ekeyq_u32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SM4 encode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4eq_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm4e))] #[unstable(feature = "stdarch_neon_sm4", issue = "117226")] @@ -25270,9 +24082,31 @@ pub fn vsm4eq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } unsafe { _vsm4eq_u32(a, b) } } +#[doc = "SM4 encode"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4eq_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,sm4")] +#[cfg_attr(test, assert_instr(sm4e))] +#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] +pub fn vsm4eq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sm4e" + )] + fn _vsm4eq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsm4eq_u32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] @@ -25288,7 +24122,7 @@ pub fn vsqadd_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { } #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] @@ -25304,7 +24138,7 @@ pub fn vsqaddq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { } #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] @@ -25320,7 +24154,7 @@ pub fn vsqadd_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { } #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] @@ -25336,7 +24170,7 @@ pub fn vsqaddq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { } #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] @@ -25352,7 +24186,7 @@ pub fn vsqadd_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { } #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] @@ -25368,7 +24202,7 @@ pub fn vsqaddq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { } #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] @@ -25384,7 +24218,7 @@ pub fn vsqadd_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { } #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] @@ -25400,25 +24234,25 @@ pub fn vsqaddq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { } #[doc = "Unsigned saturating accumulate of signed value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddb_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(usqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsqaddb_u8(a: u8, b: i8) -> u8 { - unsafe { simd_extract!(vsqadd_u8(vdup_n_u8(a), vdup_n_s8(b)), 0) } + vget_lane_u8::<0>(vsqadd_u8(vdup_n_u8(a), vdup_n_s8(b))) } #[doc = "Unsigned saturating accumulate of signed value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddh_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(usqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsqaddh_u16(a: u16, b: i16) -> u16 { - unsafe { simd_extract!(vsqadd_u16(vdup_n_u16(a), vdup_n_s16(b)), 0) } + vget_lane_u16::<0>(vsqadd_u16(vdup_n_u16(a), vdup_n_s16(b))) } #[doc = "Unsigned saturating accumulate of signed value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(usqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -25434,7 +24268,7 @@ pub fn vsqaddd_u64(a: u64, b: i64) -> u64 { } #[doc = "Unsigned saturating accumulate of signed value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadds_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(usqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -25450,27 +24284,27 @@ pub fn vsqadds_u32(a: u32, b: i32) -> u32 { } #[doc = "Calculates the square root of each lane."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fsqrt))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vsqrt_f16(a: float16x4_t) -> float16x4_t { unsafe { simd_fsqrt(a) } } #[doc = "Calculates the square root of each lane."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fsqrt))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vsqrtq_f16(a: float16x8_t) -> float16x8_t { unsafe { simd_fsqrt(a) } } #[doc = "Calculates the square root of each lane."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fsqrt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -25479,7 +24313,7 @@ pub fn vsqrt_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Calculates the square root of each lane."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fsqrt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -25488,7 +24322,7 @@ pub fn vsqrtq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Calculates the square root of each lane."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fsqrt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -25497,7 +24331,7 @@ pub fn vsqrt_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Calculates the square root of each lane."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fsqrt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -25506,7 +24340,7 @@ pub fn vsqrtq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrth_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -25516,151 +24350,95 @@ pub fn vsqrth_f16(a: f16) -> f16 { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsri_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { static_assert!(N >= 1 && N <= 8); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v8i8" - )] - fn _vsri_n_s8(a: int8x8_t, b: int8x8_t, n: i32) -> int8x8_t; - } - unsafe { _vsri_n_s8(a, b, N) } + unsafe { super::shift_right_and_insert!(u8, 8, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsriq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { static_assert!(N >= 1 && N <= 8); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v16i8" - )] - fn _vsriq_n_s8(a: int8x16_t, b: int8x16_t, n: i32) -> int8x16_t; - } - unsafe { _vsriq_n_s8(a, b, N) } + unsafe { super::shift_right_and_insert!(u8, 16, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsri_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { static_assert!(N >= 1 && N <= 16); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v4i16" - )] - fn _vsri_n_s16(a: int16x4_t, b: int16x4_t, n: i32) -> int16x4_t; - } - unsafe { _vsri_n_s16(a, b, N) } + unsafe { super::shift_right_and_insert!(u16, 4, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsriq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { static_assert!(N >= 1 && N <= 16); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v8i16" - )] - fn _vsriq_n_s16(a: int16x8_t, b: int16x8_t, n: i32) -> int16x8_t; - } - unsafe { _vsriq_n_s16(a, b, N) } + unsafe { super::shift_right_and_insert!(u16, 8, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsri_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { static_assert!(N >= 1 && N <= 32); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v2i32" - )] - fn _vsri_n_s32(a: int32x2_t, b: int32x2_t, n: i32) -> int32x2_t; - } - unsafe { _vsri_n_s32(a, b, N) } + unsafe { super::shift_right_and_insert!(u32, 2, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsriq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v4i32" - )] - fn _vsriq_n_s32(a: int32x4_t, b: int32x4_t, n: i32) -> int32x4_t; - } - unsafe { _vsriq_n_s32(a, b, N) } + unsafe { super::shift_right_and_insert!(u32, 4, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsri_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { static_assert!(N >= 1 && N <= 64); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v1i64" - )] - fn _vsri_n_s64(a: int64x1_t, b: int64x1_t, n: i32) -> int64x1_t; - } - unsafe { _vsri_n_s64(a, b, N) } + unsafe { super::shift_right_and_insert!(u64, 1, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsriq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - static_assert!(N >= 1 && N <= 64); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v2i64" - )] - fn _vsriq_n_s64(a: int64x2_t, b: int64x2_t, n: i32) -> int64x2_t; - } - unsafe { _vsriq_n_s64(a, b, N) } + static_assert!(N >= 1 && N <= 64); + unsafe { super::shift_right_and_insert!(u64, 2, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -25671,7 +24449,7 @@ pub fn vsri_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -25682,7 +24460,7 @@ pub fn vsriq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -25693,7 +24471,7 @@ pub fn vsri_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -25704,7 +24482,7 @@ pub fn vsriq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -25715,7 +24493,7 @@ pub fn vsri_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -25726,7 +24504,7 @@ pub fn vsriq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -25737,7 +24515,7 @@ pub fn vsri_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -25748,7 +24526,7 @@ pub fn vsriq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -25759,7 +24537,7 @@ pub fn vsri_n_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -25770,7 +24548,7 @@ pub fn vsriq_n_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -25781,7 +24559,7 @@ pub fn vsri_n_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -25792,7 +24570,7 @@ pub fn vsriq_n_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -25803,7 +24581,7 @@ pub fn vsri_n_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -25814,22 +24592,22 @@ pub fn vsriq_n_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { } #[doc = "Shift right and insert"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsrid_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sri, N = 2))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(bfxil, N = 2))] pub fn vsrid_n_s64(a: i64, b: i64) -> i64 { static_assert!(N >= 1 && N <= 64); unsafe { transmute(vsri_n_s64::(transmute(a), transmute(b))) } } #[doc = "Shift right and insert"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsrid_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sri, N = 2))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(bfxil, N = 2))] pub fn vsrid_n_u64(a: u64, b: u64) -> u64 { static_assert!(N >= 1 && N <= 64); unsafe { transmute(vsri_n_u64::(transmute(a), transmute(b))) } @@ -25838,7 +24616,7 @@ pub fn vsrid_n_u64(a: u64, b: u64) -> u64 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -25851,7 +24629,7 @@ pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -25864,7 +24642,7 @@ pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -25876,7 +24654,7 @@ pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -25888,7 +24666,7 @@ pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -25900,7 +24678,7 @@ pub unsafe fn vst1_f64(ptr: *mut f64, a: float64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -25912,7 +24690,7 @@ pub unsafe fn vst1q_f64(ptr: *mut f64, a: float64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -25924,7 +24702,7 @@ pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -25936,7 +24714,7 @@ pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -25948,7 +24726,7 @@ pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -25960,7 +24738,7 @@ pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -25972,7 +24750,7 @@ pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -25984,7 +24762,7 @@ pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -25996,7 +24774,7 @@ pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -26008,7 +24786,7 @@ pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -26020,7 +24798,7 @@ pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -26032,7 +24810,7 @@ pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -26044,7 +24822,7 @@ pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -26056,7 +24834,7 @@ pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -26068,7 +24846,7 @@ pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -26080,7 +24858,7 @@ pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -26092,7 +24870,7 @@ pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -26104,7 +24882,7 @@ pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -26116,7 +24894,7 @@ pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -26128,7 +24906,7 @@ pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -26140,7 +24918,7 @@ pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -26152,7 +24930,7 @@ pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -26164,7 +24942,7 @@ pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -26176,7 +24954,7 @@ pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26194,7 +24972,7 @@ pub unsafe fn vst1_f64_x2(a: *mut f64, b: float64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26212,7 +24990,7 @@ pub unsafe fn vst1q_f64_x2(a: *mut f64, b: float64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26230,7 +25008,7 @@ pub unsafe fn vst1_f64_x3(a: *mut f64, b: float64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26248,7 +25026,7 @@ pub unsafe fn vst1q_f64_x3(a: *mut f64, b: float64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26272,7 +25050,7 @@ pub unsafe fn vst1_f64_x4(a: *mut f64, b: float64x1x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26296,7 +25074,7 @@ pub unsafe fn vst1q_f64_x4(a: *mut f64, b: float64x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -26309,7 +25087,7 @@ pub unsafe fn vst1_lane_f64(a: *mut f64, b: float64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -26322,25 +25100,18 @@ pub unsafe fn vst1q_lane_f64(a: *mut f64, b: float64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(st1))] +#[cfg_attr(test, assert_instr(stp))] pub unsafe fn vst2_f64(a: *mut f64, b: float64x1x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v1f64.p0" - )] - fn _vst2_f64(a: float64x1_t, b: float64x1_t, ptr: *mut i8); - } - _vst2_f64(b.0, b.1, a as _) + core::ptr::write_unaligned(a.cast(), b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -26360,7 +25131,7 @@ pub unsafe fn vst2_lane_f64(a: *mut f64, b: float64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -26380,7 +25151,7 @@ pub unsafe fn vst2_lane_s64(a: *mut i64, b: int64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -26393,7 +25164,7 @@ pub unsafe fn vst2_lane_p64(a: *mut p64, b: poly64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -26406,43 +25177,29 @@ pub unsafe fn vst2_lane_u64(a: *mut u64, b: uint64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] pub unsafe fn vst2q_f64(a: *mut f64, b: float64x2x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v2f64.p0" - )] - fn _vst2q_f64(a: float64x2_t, b: float64x2_t, ptr: *mut i8); - } - _vst2q_f64(b.0, b.1, a as _) + crate::core_arch::macros::interleaving_store!(f64, 2, 2, a, b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] pub unsafe fn vst2q_s64(a: *mut i64, b: int64x2x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v2i64.p0" - )] - fn _vst2q_s64(a: int64x2_t, b: int64x2_t, ptr: *mut i8); - } - _vst2q_s64(b.0, b.1, a as _) + crate::core_arch::macros::interleaving_store!(i64, 2, 2, a, b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -26462,7 +25219,7 @@ pub unsafe fn vst2q_lane_f64(a: *mut f64, b: float64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -26482,7 +25239,7 @@ pub unsafe fn vst2q_lane_s8(a: *mut i8, b: int8x16x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -26502,7 +25259,7 @@ pub unsafe fn vst2q_lane_s64(a: *mut i64, b: int64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -26515,7 +25272,7 @@ pub unsafe fn vst2q_lane_p64(a: *mut p64, b: poly64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -26528,7 +25285,7 @@ pub unsafe fn vst2q_lane_u8(a: *mut u8, b: uint8x16x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -26541,7 +25298,7 @@ pub unsafe fn vst2q_lane_u64(a: *mut u64, b: uint64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -26554,7 +25311,7 @@ pub unsafe fn vst2q_lane_p8(a: *mut p8, b: poly8x16x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26565,7 +25322,7 @@ pub unsafe fn vst2q_p64(a: *mut p64, b: poly64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] @@ -26576,25 +25333,18 @@ pub unsafe fn vst2q_u64(a: *mut u64, b: uint64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vst3_f64(a: *mut f64, b: float64x1x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v1f64.p0" - )] - fn _vst3_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t, ptr: *mut i8); - } - _vst3_f64(b.0, b.1, b.2, a as _) + core::ptr::write_unaligned(a.cast(), b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -26614,7 +25364,7 @@ pub unsafe fn vst3_lane_f64(a: *mut f64, b: float64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -26634,7 +25384,7 @@ pub unsafe fn vst3_lane_s64(a: *mut i64, b: int64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] @@ -26647,7 +25397,7 @@ pub unsafe fn vst3_lane_p64(a: *mut p64, b: poly64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] @@ -26660,43 +25410,29 @@ pub unsafe fn vst3_lane_u64(a: *mut u64, b: uint64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3q_f64(a: *mut f64, b: float64x2x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v2f64.p0" - )] - fn _vst3q_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t, ptr: *mut i8); - } - _vst3q_f64(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(f64, 2, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3q_s64(a: *mut i64, b: int64x2x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v2i64.p0" - )] - fn _vst3q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t, ptr: *mut i8); - } - _vst3q_s64(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(i64, 2, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -26716,7 +25452,7 @@ pub unsafe fn vst3q_lane_f64(a: *mut f64, b: float64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -26736,7 +25472,7 @@ pub unsafe fn vst3q_lane_s8(a: *mut i8, b: int8x16x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -26756,7 +25492,7 @@ pub unsafe fn vst3q_lane_s64(a: *mut i64, b: int64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] @@ -26769,7 +25505,7 @@ pub unsafe fn vst3q_lane_p64(a: *mut p64, b: poly64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] @@ -26782,7 +25518,7 @@ pub unsafe fn vst3q_lane_u8(a: *mut u8, b: uint8x16x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] @@ -26795,7 +25531,7 @@ pub unsafe fn vst3q_lane_u64(a: *mut u64, b: uint64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] @@ -26808,7 +25544,7 @@ pub unsafe fn vst3q_lane_p8(a: *mut p8, b: poly8x16x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st3))] @@ -26819,7 +25555,7 @@ pub unsafe fn vst3q_p64(a: *mut p64, b: poly64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] @@ -26830,25 +25566,18 @@ pub unsafe fn vst3q_u64(a: *mut u64, b: uint64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vst4_f64(a: *mut f64, b: float64x1x4_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v1f64.p0" - )] - fn _vst4_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t, d: float64x1_t, ptr: *mut i8); - } - _vst4_f64(b.0, b.1, b.2, b.3, a as _) + core::ptr::write_unaligned(a.cast(), b) } #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -26875,7 +25604,7 @@ pub unsafe fn vst4_lane_f64(a: *mut f64, b: float64x1x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -26902,7 +25631,7 @@ pub unsafe fn vst4_lane_s64(a: *mut i64, b: int64x1x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] @@ -26915,7 +25644,7 @@ pub unsafe fn vst4_lane_p64(a: *mut p64, b: poly64x1x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] @@ -26928,43 +25657,29 @@ pub unsafe fn vst4_lane_u64(a: *mut u64, b: uint64x1x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4))] pub unsafe fn vst4q_f64(a: *mut f64, b: float64x2x4_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v2f64.p0" - )] - fn _vst4q_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t, d: float64x2_t, ptr: *mut i8); - } - _vst4q_f64(b.0, b.1, b.2, b.3, a as _) + crate::core_arch::macros::interleaving_store!(f64, 2, 4, a, b) } #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4))] pub unsafe fn vst4q_s64(a: *mut i64, b: int64x2x4_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v2i64.p0" - )] - fn _vst4q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t, d: int64x2_t, ptr: *mut i8); - } - _vst4q_s64(b.0, b.1, b.2, b.3, a as _) + crate::core_arch::macros::interleaving_store!(i64, 2, 4, a, b) } #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -26991,7 +25706,7 @@ pub unsafe fn vst4q_lane_f64(a: *mut f64, b: float64x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -27018,7 +25733,7 @@ pub unsafe fn vst4q_lane_s8(a: *mut i8, b: int8x16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -27045,7 +25760,7 @@ pub unsafe fn vst4q_lane_s64(a: *mut i64, b: int64x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] @@ -27058,7 +25773,7 @@ pub unsafe fn vst4q_lane_p64(a: *mut p64, b: poly64x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] @@ -27071,7 +25786,7 @@ pub unsafe fn vst4q_lane_u8(a: *mut u8, b: uint8x16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] @@ -27084,7 +25799,7 @@ pub unsafe fn vst4q_lane_u64(a: *mut u64, b: uint64x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] @@ -27097,7 +25812,7 @@ pub unsafe fn vst4q_lane_p8(a: *mut p8, b: poly8x16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st4))] @@ -27108,7 +25823,7 @@ pub unsafe fn vst4q_p64(a: *mut p64, b: poly64x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4))] @@ -27117,103 +25832,123 @@ pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) { } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_f64)"] -#[inline(always)] +#[doc = "## Safety"] +#[doc = " * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."] +#[inline] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] -pub fn vstl1_lane_f64(ptr: *mut f64, val: float64x1_t) { +#[cfg(target_has_atomic = "64")] +pub unsafe fn vstl1_lane_f64(ptr: *mut f64, val: float64x1_t) { static_assert!(LANE == 0); - unsafe { vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } + vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_f64)"] -#[inline(always)] +#[doc = "## Safety"] +#[doc = " * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."] +#[inline] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] -pub fn vstl1q_lane_f64(ptr: *mut f64, val: float64x2_t) { +#[cfg(target_has_atomic = "64")] +pub unsafe fn vstl1q_lane_f64(ptr: *mut f64, val: float64x2_t) { static_assert_uimm_bits!(LANE, 1); - unsafe { vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } + vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_u64)"] -#[inline(always)] +#[doc = "## Safety"] +#[doc = " * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."] +#[inline] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] -pub fn vstl1_lane_u64(ptr: *mut u64, val: uint64x1_t) { +#[cfg(target_has_atomic = "64")] +pub unsafe fn vstl1_lane_u64(ptr: *mut u64, val: uint64x1_t) { static_assert!(LANE == 0); - unsafe { vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } + vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_u64)"] -#[inline(always)] +#[doc = "## Safety"] +#[doc = " * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."] +#[inline] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] -pub fn vstl1q_lane_u64(ptr: *mut u64, val: uint64x2_t) { +#[cfg(target_has_atomic = "64")] +pub unsafe fn vstl1q_lane_u64(ptr: *mut u64, val: uint64x2_t) { static_assert_uimm_bits!(LANE, 1); - unsafe { vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } + vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_p64)"] -#[inline(always)] +#[doc = "## Safety"] +#[doc = " * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."] +#[inline] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] -pub fn vstl1_lane_p64(ptr: *mut p64, val: poly64x1_t) { +#[cfg(target_has_atomic = "64")] +pub unsafe fn vstl1_lane_p64(ptr: *mut p64, val: poly64x1_t) { static_assert!(LANE == 0); - unsafe { vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } + vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_p64)"] -#[inline(always)] +#[doc = "## Safety"] +#[doc = " * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."] +#[inline] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] -pub fn vstl1q_lane_p64(ptr: *mut p64, val: poly64x2_t) { +#[cfg(target_has_atomic = "64")] +pub unsafe fn vstl1q_lane_p64(ptr: *mut p64, val: poly64x2_t) { static_assert_uimm_bits!(LANE, 1); - unsafe { vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } + vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_s64)"] -#[inline(always)] +#[doc = "## Safety"] +#[doc = " * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."] +#[inline] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] -pub fn vstl1_lane_s64(ptr: *mut i64, val: int64x1_t) { +#[cfg(target_has_atomic = "64")] +pub unsafe fn vstl1_lane_s64(ptr: *mut i64, val: int64x1_t) { static_assert!(LANE == 0); let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64; - unsafe { - let lane: i64 = simd_extract!(val, LANE as u32); - (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release) - } + let lane: i64 = vget_lane_s64::(val); + (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release) } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_s64)"] -#[inline(always)] +#[doc = "## Safety"] +#[doc = " * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."] +#[inline] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] -pub fn vstl1q_lane_s64(ptr: *mut i64, val: int64x2_t) { +#[cfg(target_has_atomic = "64")] +pub unsafe fn vstl1q_lane_s64(ptr: *mut i64, val: int64x2_t) { static_assert_uimm_bits!(LANE, 1); let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64; - unsafe { - let lane: i64 = simd_extract!(val, LANE as u32); - (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release) - } + let lane: i64 = vgetq_lane_s64::(val); + (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release) } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fsub))] @@ -27222,7 +25957,7 @@ pub fn vsub_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fsub))] @@ -27231,7 +25966,7 @@ pub fn vsubq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sub))] @@ -27240,7 +25975,7 @@ pub fn vsubd_s64(a: i64, b: i64) -> i64 { } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sub))] @@ -27249,7 +25984,7 @@ pub fn vsubd_u64(a: u64, b: u64) -> u64 { } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -27259,169 +25994,145 @@ pub fn vsubh_f16(a: f16, b: f16) -> f16 { } #[doc = "Signed Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ssubl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubl2))] pub fn vsubl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { unsafe { - let c: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let d: int16x8_t = simd_cast(c); - let e: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let f: int16x8_t = simd_cast(e); - simd_sub(d, f) + let c: int16x8_t = simd_cast(vget_high_s8(a)); + let d: int16x8_t = simd_cast(vget_high_s8(b)); + simd_sub(c, d) } } #[doc = "Signed Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ssubl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubl2))] pub fn vsubl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { unsafe { - let c: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let d: int32x4_t = simd_cast(c); - let e: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let f: int32x4_t = simd_cast(e); - simd_sub(d, f) + let c: int32x4_t = simd_cast(vget_high_s16(a)); + let d: int32x4_t = simd_cast(vget_high_s16(b)); + simd_sub(c, d) } } #[doc = "Signed Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ssubl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubl2))] pub fn vsubl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { unsafe { - let c: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let d: int64x2_t = simd_cast(c); - let e: int32x2_t = simd_shuffle!(b, b, [2, 3]); - let f: int64x2_t = simd_cast(e); - simd_sub(d, f) + let c: int64x2_t = simd_cast(vget_high_s32(a)); + let d: int64x2_t = simd_cast(vget_high_s32(b)); + simd_sub(c, d) } } #[doc = "Unsigned Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(usubl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubl2))] pub fn vsubl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { unsafe { - let c: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let d: uint16x8_t = simd_cast(c); - let e: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let f: uint16x8_t = simd_cast(e); - simd_sub(d, f) + let c: uint16x8_t = simd_cast(vget_high_u8(a)); + let d: uint16x8_t = simd_cast(vget_high_u8(b)); + simd_sub(c, d) } } #[doc = "Unsigned Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(usubl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubl2))] pub fn vsubl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { unsafe { - let c: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let d: uint32x4_t = simd_cast(c); - let e: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let f: uint32x4_t = simd_cast(e); - simd_sub(d, f) + let c: uint32x4_t = simd_cast(vget_high_u16(a)); + let d: uint32x4_t = simd_cast(vget_high_u16(b)); + simd_sub(c, d) } } #[doc = "Unsigned Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(usubl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubl2))] pub fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { unsafe { - let c: uint32x2_t = simd_shuffle!(a, a, [2, 3]); - let d: uint64x2_t = simd_cast(c); - let e: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - let f: uint64x2_t = simd_cast(e); - simd_sub(d, f) + let c: uint64x2_t = simd_cast(vget_high_u32(a)); + let d: uint64x2_t = simd_cast(vget_high_u32(b)); + simd_sub(c, d) } } #[doc = "Signed Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ssubw2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubw2))] pub fn vsubw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { - unsafe { - let c: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - simd_sub(a, simd_cast(c)) - } + let c = vget_high_s8(b); + unsafe { simd_sub(a, simd_cast(c)) } } #[doc = "Signed Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ssubw2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubw2))] pub fn vsubw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { - unsafe { - let c: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - simd_sub(a, simd_cast(c)) - } + let c = vget_high_s16(b); + unsafe { simd_sub(a, simd_cast(c)) } } #[doc = "Signed Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ssubw2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubw2))] pub fn vsubw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { - unsafe { - let c: int32x2_t = simd_shuffle!(b, b, [2, 3]); - simd_sub(a, simd_cast(c)) - } + let c = vget_high_s32(b); + unsafe { simd_sub(a, simd_cast(c)) } } #[doc = "Unsigned Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(usubw2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubw2))] pub fn vsubw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { - unsafe { - let c: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - simd_sub(a, simd_cast(c)) - } + let c = vget_high_u8(b); + unsafe { simd_sub(a, simd_cast(c)) } } #[doc = "Unsigned Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(usubw2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubw2))] pub fn vsubw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { - unsafe { - let c: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - simd_sub(a, simd_cast(c)) - } + let c = vget_high_u16(b); + unsafe { simd_sub(a, simd_cast(c)) } } #[doc = "Unsigned Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(usubw2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubw2))] pub fn vsubw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { - unsafe { - let c: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - simd_sub(a, simd_cast(c)) - } + let c = vget_high_u32(b); + unsafe { simd_sub(a, simd_cast(c)) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27434,7 +26145,7 @@ pub fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27443,7 +26154,7 @@ pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27452,70 +26163,34 @@ pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t { - unsafe { vqtbl1(transmute(vcombine_s8(a.0, a.1)), transmute(b)) } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t { - unsafe { transmute(vqtbl1(transmute(vcombine_u8(a.0, a.1)), b)) } + vqtbl1_s8(vcombine_s8(a.0, a.1), vreinterpret_u8_s8(b)) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t { - let mut a: uint8x8x2_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vqtbl1(transmute(vcombine_u8(a.0, a.1)), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t { - unsafe { transmute(vqtbl1(transmute(vcombine_p8(a.0, a.1)), b)) } + vqtbl1_u8(vcombine_u8(a.0, a.1), b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t { - let mut a: poly8x8x2_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(vqtbl1(transmute(vcombine_p8(a.0, a.1)), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } + vqtbl1_p8(vcombine_p8(a.0, a.1), b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27524,155 +26199,67 @@ pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t { vcombine_s8(a.0, a.1), vcombine_s8(a.2, unsafe { crate::mem::zeroed() }), ); - unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), transmute(b))) } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { - let x = uint8x16x2_t( - vcombine_u8(a.0, a.1), - vcombine_u8(a.2, unsafe { crate::mem::zeroed() }), - ); - unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) } + vqtbl2_s8(x, vreinterpret_u8_s8(b)) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { - let mut a: uint8x8x3_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; let x = uint8x16x2_t( vcombine_u8(a.0, a.1), vcombine_u8(a.2, unsafe { crate::mem::zeroed() }), ); - unsafe { - let ret_val: uint8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t { - let x = poly8x16x2_t( - vcombine_p8(a.0, a.1), - vcombine_p8(a.2, unsafe { crate::mem::zeroed() }), - ); - unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) } + vqtbl2_u8(x, b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t { - let mut a: poly8x8x3_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; let x = poly8x16x2_t( vcombine_p8(a.0, a.1), vcombine_p8(a.2, unsafe { crate::mem::zeroed() }), ); - unsafe { - let ret_val: poly8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } + vqtbl2_p8(x, b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t { let x = int8x16x2_t(vcombine_s8(a.0, a.1), vcombine_s8(a.2, a.3)); - unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), transmute(b))) } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { - let x = uint8x16x2_t(vcombine_u8(a.0, a.1), vcombine_u8(a.2, a.3)); - unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) } + vqtbl2_s8(x, vreinterpret_u8_s8(b)) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { - let mut a: uint8x8x4_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; let x = uint8x16x2_t(vcombine_u8(a.0, a.1), vcombine_u8(a.2, a.3)); - unsafe { - let ret_val: uint8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t { - let x = poly8x16x2_t(vcombine_p8(a.0, a.1), vcombine_p8(a.2, a.3)); - unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) } + vqtbl2_u8(x, b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t { - let mut a: poly8x8x4_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; let x = poly8x16x2_t(vcombine_p8(a.0, a.1), vcombine_p8(a.2, a.3)); - unsafe { - let ret_val: poly8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } + vqtbl2_p8(x, b) } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27680,18 +26267,18 @@ pub fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { unsafe { simd_select( simd_lt::(c, transmute(i8x8::splat(8))), - transmute(vqtbx1( - transmute(a), - transmute(vcombine_s8(b, crate::mem::zeroed())), - transmute(c), - )), + vqtbx1_s8( + a, + vcombine_s8(b, crate::mem::zeroed()), + vreinterpret_u8_s8(c), + ), a, ) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27699,18 +26286,14 @@ pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { unsafe { simd_select( simd_lt::(c, transmute(u8x8::splat(8))), - transmute(vqtbx1( - transmute(a), - transmute(vcombine_u8(b, crate::mem::zeroed())), - c, - )), + vqtbx1_u8(a, vcombine_u8(b, crate::mem::zeroed()), c), a, ) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27718,85 +26301,59 @@ pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t { unsafe { simd_select( simd_lt::(c, transmute(u8x8::splat(8))), - transmute(vqtbx1( - transmute(a), - transmute(vcombine_p8(b, crate::mem::zeroed())), - c, - )), + vqtbx1_p8(a, vcombine_p8(b, crate::mem::zeroed()), c), a, ) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t { - unsafe { vqtbx1(transmute(a), transmute(vcombine_s8(b.0, b.1)), transmute(c)) } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t { - unsafe { transmute(vqtbx1(transmute(a), transmute(vcombine_u8(b.0, b.1)), c)) } + unsafe { + simd_select( + simd_lt::(c, transmute(i8x8::splat(16))), + vqtbx1_s8(a, vcombine_s8(b.0, b.1), vreinterpret_u8_s8(c)), + a, + ) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t { - let mut b: uint8x8x2_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; unsafe { - let ret_val: uint8x8_t = - transmute(vqtbx1(transmute(a), transmute(vcombine_u8(b.0, b.1)), c)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + simd_select( + simd_lt::(c, transmute(u8x8::splat(16))), + vqtbx1_u8(a, vcombine_u8(b.0, b.1), c), + a, + ) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t { - unsafe { transmute(vqtbx1(transmute(a), transmute(vcombine_p8(b.0, b.1)), c)) } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t { - let mut b: poly8x8x2_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; unsafe { - let ret_val: poly8x8_t = - transmute(vqtbx1(transmute(a), transmute(vcombine_p8(b.0, b.1)), c)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + simd_select( + simd_lt::(c, transmute(u8x8::splat(16))), + vqtbx1_p8(a, vcombine_p8(b.0, b.1), c), + a, + ) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27806,319 +26363,454 @@ pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t { vcombine_s8(b.2, unsafe { crate::mem::zeroed() }), ); unsafe { - transmute(simd_select( - simd_lt::(transmute(c), transmute(i8x8::splat(24))), - transmute(vqtbx2( - transmute(a), - transmute(x.0), - transmute(x.1), - transmute(c), - )), - a, - )) - } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t { - let x = uint8x16x2_t( - vcombine_u8(b.0, b.1), - vcombine_u8(b.2, unsafe { crate::mem::zeroed() }), - ); - unsafe { - transmute(simd_select( - simd_lt::(transmute(c), transmute(u8x8::splat(24))), - transmute(vqtbx2(transmute(a), transmute(x.0), transmute(x.1), c)), + simd_select( + simd_lt::(c, transmute(i8x8::splat(24))), + vqtbx2_s8(a, x, vreinterpret_u8_s8(c)), a, - )) + ) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t { - let mut b: uint8x8x3_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; let x = uint8x16x2_t( vcombine_u8(b.0, b.1), vcombine_u8(b.2, unsafe { crate::mem::zeroed() }), ); unsafe { - let ret_val: uint8x8_t = transmute(simd_select( - simd_lt::(transmute(c), transmute(u8x8::splat(24))), - transmute(vqtbx2(transmute(a), transmute(x.0), transmute(x.1), c)), - a, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t { - let x = poly8x16x2_t( - vcombine_p8(b.0, b.1), - vcombine_p8(b.2, unsafe { crate::mem::zeroed() }), - ); - unsafe { - transmute(simd_select( - simd_lt::(transmute(c), transmute(u8x8::splat(24))), - transmute(vqtbx2(transmute(a), transmute(x.0), transmute(x.1), c)), + simd_select( + simd_lt::(c, transmute(u8x8::splat(24))), + vqtbx2_u8(a, x, c), a, - )) + ) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t { - let mut b: poly8x8x3_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; let x = poly8x16x2_t( vcombine_p8(b.0, b.1), vcombine_p8(b.2, unsafe { crate::mem::zeroed() }), ); unsafe { - let ret_val: poly8x8_t = transmute(simd_select( - simd_lt::(transmute(c), transmute(u8x8::splat(24))), - transmute(vqtbx2(transmute(a), transmute(x.0), transmute(x.1), c)), - a, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t { - unsafe { - vqtbx2( - transmute(a), - transmute(vcombine_s8(b.0, b.1)), - transmute(vcombine_s8(b.2, b.3)), - transmute(c), - ) - } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t { - unsafe { - transmute(vqtbx2( - transmute(a), - transmute(vcombine_u8(b.0, b.1)), - transmute(vcombine_u8(b.2, b.3)), - c, - )) + simd_select( + simd_lt::(c, transmute(u8x8::splat(24))), + vqtbx2_p8(a, x, c), + a, + ) } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t { - let mut b: uint8x8x4_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vqtbx2( - transmute(a), - transmute(vcombine_u8(b.0, b.1)), - transmute(vcombine_u8(b.2, b.3)), - c, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t { + let x = int8x16x2_t(vcombine_s8(b.0, b.1), vcombine_s8(b.2, b.3)); + unsafe { + simd_select( + simd_lt::(c, transmute(i8x8::splat(32))), + vqtbx2_s8(a, x, vreinterpret_u8_s8(c)), + a, + ) } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t { +pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t { + let x = uint8x16x2_t(vcombine_u8(b.0, b.1), vcombine_u8(b.2, b.3)); unsafe { - transmute(vqtbx2( - transmute(a), - transmute(vcombine_p8(b.0, b.1)), - transmute(vcombine_p8(b.2, b.3)), - c, - )) + simd_select( + simd_lt::(c, transmute(u8x8::splat(32))), + vqtbx2_u8(a, x, c), + a, + ) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t { - let mut b: poly8x8x4_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(vqtbx2( - transmute(a), - transmute(vcombine_p8(b.0, b.1)), - transmute(vcombine_p8(b.2, b.3)), - c, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let x = poly8x16x2_t(vcombine_p8(b.0, b.1), vcombine_p8(b.2, b.3)); + unsafe { + simd_select( + simd_lt::(c, transmute(u8x8::splat(32))), + vqtbx2_p8(a, x, c), + a, + ) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vtrn1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vtrn1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vtrn1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vtrn1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vtrn1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vtrn1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vtrn1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vtrn1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { + let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vtrn1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vtrn1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vtrn1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vtrn1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vtrn1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vtrn1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + unsafe { + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: poly64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe { simd_shuffle!( @@ -28129,47 +26821,167 @@ pub fn vtrn1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe { simd_shuffle!( @@ -28180,47 +26992,167 @@ pub fn vtrn1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } } #[doc = "Transpose vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u16)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) } +} +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] -pub fn vtrn1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) } +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { unsafe { simd_shuffle!( @@ -28231,130 +27163,450 @@ pub fn vtrn1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + unsafe { + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vtrn2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vtrn2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vtrn2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vtrn2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vtrn2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vtrn2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vtrn2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vtrn2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { + let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vtrn2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vtrn2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vtrn2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vtrn2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vtrn2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vtrn2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + unsafe { + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: poly64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe { simd_shuffle!( @@ -28365,47 +27617,167 @@ pub fn vtrn2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } } #[doc = "Transpose vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s32)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) } +} +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] -pub fn vtrn2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) } +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe { simd_shuffle!( @@ -28416,47 +27788,167 @@ pub fn vtrn2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { unsafe { simd_shuffle!( @@ -28467,26 +27959,98 @@ pub fn vtrn2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + unsafe { + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } } +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -28499,7 +28063,7 @@ pub fn vtst_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { } #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -28512,7 +28076,7 @@ pub fn vtstq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { } #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -28525,7 +28089,7 @@ pub fn vtst_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t { } #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -28538,7 +28102,7 @@ pub fn vtstq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t { } #[doc = "Unsigned compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -28551,7 +28115,7 @@ pub fn vtst_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Unsigned compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -28564,7 +28128,7 @@ pub fn vtstq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Compare bitwise test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -28573,7 +28137,7 @@ pub fn vtstd_s64(a: i64, b: i64) -> u64 { } #[doc = "Compare bitwise test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -28582,7 +28146,7 @@ pub fn vtstd_u64(a: u64, b: u64) -> u64 { } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] @@ -28598,7 +28162,7 @@ pub fn vuqadd_s8(a: int8x8_t, b: uint8x8_t) -> int8x8_t { } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] @@ -28614,7 +28178,7 @@ pub fn vuqaddq_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t { } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] @@ -28630,7 +28194,7 @@ pub fn vuqadd_s16(a: int16x4_t, b: uint16x4_t) -> int16x4_t { } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] @@ -28646,7 +28210,7 @@ pub fn vuqaddq_s16(a: int16x8_t, b: uint16x8_t) -> int16x8_t { } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] @@ -28662,7 +28226,7 @@ pub fn vuqadd_s32(a: int32x2_t, b: uint32x2_t) -> int32x2_t { } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] @@ -28678,7 +28242,7 @@ pub fn vuqaddq_s32(a: int32x4_t, b: uint32x4_t) -> int32x4_t { } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] @@ -28694,7 +28258,7 @@ pub fn vuqadd_s64(a: int64x1_t, b: uint64x1_t) -> int64x1_t { } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] @@ -28710,25 +28274,25 @@ pub fn vuqaddq_s64(a: int64x2_t, b: uint64x2_t) -> int64x2_t { } #[doc = "Signed saturating accumulate of unsigned value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddb_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(suqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vuqaddb_s8(a: i8, b: u8) -> i8 { - unsafe { simd_extract!(vuqadd_s8(vdup_n_s8(a), vdup_n_u8(b)), 0) } + vget_lane_s8::<0>(vuqadd_s8(vdup_n_s8(a), vdup_n_u8(b))) } #[doc = "Signed saturating accumulate of unsigned value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(suqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vuqaddh_s16(a: i16, b: u16) -> i16 { - unsafe { simd_extract!(vuqadd_s16(vdup_n_s16(a), vdup_n_u16(b)), 0) } + vget_lane_s16::<0>(vuqadd_s16(vdup_n_s16(a), vdup_n_u16(b))) } #[doc = "Signed saturating accumulate of unsigned value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(suqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -28744,7 +28308,7 @@ pub fn vuqaddd_s64(a: i64, b: u64) -> i64 { } #[doc = "Signed saturating accumulate of unsigned value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadds_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(suqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -28760,111 +28324,359 @@ pub fn vuqadds_s32(a: i32, b: u32) -> i32 { } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vuzp1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vuzp1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vuzp1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vuzp1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vuzp1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vuzp1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vuzp1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vuzp1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { + let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vuzp1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vuzp1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vuzp1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vuzp1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vuzp1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vuzp1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + unsafe { + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: poly64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe { simd_shuffle!( @@ -28875,47 +28687,167 @@ pub fn vuzp1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe { simd_shuffle!( @@ -28926,47 +28858,167 @@ pub fn vuzp1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { unsafe { simd_shuffle!( @@ -28977,130 +29029,450 @@ pub fn vuzp1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + unsafe { + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vuzp2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vuzp2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vuzp2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vuzp2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vuzp2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vuzp2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vuzp2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vuzp2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { + let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vuzp2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vuzp2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vuzp2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vuzp2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vuzp2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vuzp2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + unsafe { + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: poly64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f32)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) } + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe { simd_shuffle!( @@ -29111,47 +29483,167 @@ pub fn vuzp2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe { simd_shuffle!( @@ -29162,47 +29654,167 @@ pub fn vuzp2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { unsafe { simd_shuffle!( @@ -29213,26 +29825,98 @@ pub fn vuzp2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + unsafe { + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } } +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} #[doc = "Exclusive OR and rotate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vxarq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[cfg_attr(test, assert_instr(xar, IMM6 = 0))] #[rustc_legacy_const_generics(2)] @@ -29250,135 +29934,437 @@ pub fn vxarq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s8)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { + simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe { - simd_shuffle!( + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = simd_shuffle!( a, b, [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { + let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe { simd_shuffle!( @@ -29389,65 +30375,229 @@ pub fn vzip1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { unsafe { simd_shuffle!( @@ -29458,94 +30608,326 @@ pub fn vzip1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + unsafe { + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + unsafe { + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: poly64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f32)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { simd_shuffle!(a, b, [1, 3]) } +} +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub fn vzip2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - unsafe { simd_shuffle!(a, b, [1, 3]) } +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) } + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe { simd_shuffle!( @@ -29556,65 +30938,229 @@ pub fn vzip2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { + let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe { simd_shuffle!( @@ -29625,65 +31171,229 @@ pub fn vzip2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { unsafe { simd_shuffle!( @@ -29694,29 +31404,123 @@ pub fn vzip2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + unsafe { + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + unsafe { + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: poly64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} diff --git a/library/stdarch/crates/core_arch/src/aarch64/neon/mod.rs b/library/stdarch/crates/core_arch/src/aarch64/neon/mod.rs index b172b57f32543..c66702814cfb2 100644 --- a/library/stdarch/crates/core_arch/src/aarch64/neon/mod.rs +++ b/library/stdarch/crates/core_arch/src/aarch64/neon/mod.rs @@ -12,7 +12,6 @@ pub use self::generated::*; use crate::{ core_arch::{arm_shared::*, simd::*}, - hint::unreachable_unchecked, intrinsics::{simd::*, *}, mem::transmute, }; @@ -70,116 +69,29 @@ pub struct float64x2x4_t( pub float64x2_t, ); -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N1 = 0, N2 = 0))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vcopy_lane_s64(_a: int64x1_t, b: int64x1_t) -> int64x1_t { - static_assert!(N1 == 0); - static_assert!(N2 == 0); - b -} - -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N1 = 0, N2 = 0))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vcopy_lane_u64(_a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - static_assert!(N1 == 0); - static_assert!(N2 == 0); - b -} - -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N1 = 0, N2 = 0))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vcopy_lane_p64(_a: poly64x1_t, b: poly64x1_t) -> poly64x1_t { - static_assert!(N1 == 0); - static_assert!(N2 == 0); - b -} +/// Helper for the 'shift right and insert' functions. +macro_rules! shift_right_and_insert { + ($ty:ty, $width:literal, $N:expr, $a:expr, $b:expr) => {{ + type V = Simd<$ty, $width>; -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N1 = 0, N2 = 0))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vcopy_lane_f64( - _a: float64x1_t, - b: float64x1_t, -) -> float64x1_t { - static_assert!(N1 == 0); - static_assert!(N2 == 0); - b -} + if $N as u32 == <$ty>::BITS { + $a + } else { + let a: V = transmute($a); + let b: V = transmute($b); -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vcopy_laneq_s64( - _a: int64x1_t, - b: int64x2_t, -) -> int64x1_t { - static_assert!(LANE1 == 0); - static_assert_uimm_bits!(LANE2, 1); - unsafe { transmute::(simd_extract!(b, LANE2 as u32)) } -} + let mask = <$ty>::MAX >> $N; + let kept: V = simd_and(a, V::splat(!mask)); -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vcopy_laneq_u64( - _a: uint64x1_t, - b: uint64x2_t, -) -> uint64x1_t { - static_assert!(LANE1 == 0); - static_assert_uimm_bits!(LANE2, 1); - unsafe { transmute::(simd_extract!(b, LANE2 as u32)) } -} + let shift_counts = V::splat($N as $ty); + let shifted = simd_shr(b, shift_counts); -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vcopy_laneq_p64( - _a: poly64x1_t, - b: poly64x2_t, -) -> poly64x1_t { - static_assert!(LANE1 == 0); - static_assert_uimm_bits!(LANE2, 1); - unsafe { transmute::(simd_extract!(b, LANE2 as u32)) } + transmute(simd_or(kept, shifted)) + } + }}; } -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vcopy_laneq_f64( - _a: float64x1_t, - b: float64x2_t, -) -> float64x1_t { - static_assert!(LANE1 == 0); - static_assert_uimm_bits!(LANE2, 1); - unsafe { transmute::(simd_extract!(b, LANE2 as u32)) } -} +pub(crate) use shift_right_and_insert; /// Load multiple single-element structures to one, two, three, or four registers #[inline] @@ -419,42 +331,6 @@ pub fn vmovq_n_f64(value: f64) -> float64x2_t { vdupq_n_f64(value) } -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vget_high_f64(a: float64x2_t) -> float64x1_t { - unsafe { float64x1_t([simd_extract!(a, 1)]) } -} - -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ext))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vget_high_p64(a: poly64x2_t) -> poly64x1_t { - unsafe { transmute(u64x1::new(simd_extract!(a, 1))) } -} - -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vget_low_f64(a: float64x2_t) -> float64x1_t { - unsafe { float64x1_t([simd_extract!(a, 0)]) } -} - -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vget_low_p64(a: poly64x2_t) -> poly64x1_t { - unsafe { transmute(u64x1::new(simd_extract!(a, 0))) } -} - /// Duplicate vector element to vector or scalar #[inline] #[target_feature(enable = "neon")] @@ -469,29 +345,6 @@ pub fn vget_lane_f64(v: float64x1_t) -> f64 { unsafe { simd_extract!(v, IMM5 as u32) } } -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, IMM5 = 0) -)] -pub fn vgetq_lane_f64(v: float64x2_t) -> f64 { - static_assert_uimm_bits!(IMM5, 1); - unsafe { simd_extract!(v, IMM5 as u32) } -} - -/// Vector combine -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vcombine_f64(low: float64x1_t, high: float64x1_t) -> float64x2_t { - unsafe { simd_shuffle!(low, high, [0, 1]) } -} - /// Shift left #[inline] #[target_feature(enable = "neon")] @@ -569,47 +422,46 @@ mod tests { use crate::core_arch::aarch64::test_support::*; use crate::core_arch::arm_shared::test_support::*; use crate::core_arch::{aarch64::neon::*, aarch64::*, simd::*}; - use std::mem::transmute; use stdarch_test::simd_test; #[simd_test(enable = "neon")] - unsafe fn test_vadd_f64() { - let a = 1.; - let b = 8.; - let e = 9.; - let r: f64 = transmute(vadd_f64(transmute(a), transmute(b))); + fn test_vadd_f64() { + let a = f64x1::from_array([1.]); + let b = f64x1::from_array([8.]); + let e = f64x1::from_array([9.]); + let r = f64x1::from(vadd_f64(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vaddq_f64() { + fn test_vaddq_f64() { let a = f64x2::new(1., 2.); let b = f64x2::new(8., 7.); let e = f64x2::new(9., 9.); - let r: f64x2 = transmute(vaddq_f64(transmute(a), transmute(b))); + let r = f64x2::from(vaddq_f64(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vadd_s64() { - let a = 1_i64; - let b = 8_i64; - let e = 9_i64; - let r: i64 = transmute(vadd_s64(transmute(a), transmute(b))); + fn test_vadd_s64() { + let a = i64x1::from_array([1]); + let b = i64x1::from_array([8]); + let e = i64x1::from_array([9]); + let r = i64x1::from(vadd_s64(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vadd_u64() { - let a = 1_u64; - let b = 8_u64; - let e = 9_u64; - let r: u64 = transmute(vadd_u64(transmute(a), transmute(b))); + fn test_vadd_u64() { + let a = u64x1::from_array([1]); + let b = u64x1::from_array([8]); + let e = u64x1::from_array([9]); + let r = u64x1::from(vadd_u64(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vaddd_s64() { + fn test_vaddd_s64() { let a = 1_i64; let b = 8_i64; let e = 9_i64; @@ -618,7 +470,7 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vaddd_u64() { + fn test_vaddd_u64() { let a = 1_u64; let b = 8_u64; let e = 9_u64; @@ -627,25 +479,25 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vext_p64() { - let a: i64x1 = i64x1::new(0); - let b: i64x1 = i64x1::new(1); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vext_p64::<0>(transmute(a), transmute(b))); + fn test_vext_p64() { + let a = u64x1::new(0); + let b = u64x1::new(1); + let e = u64x1::new(0); + let r = u64x1::from(vext_p64::<0>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vext_f64() { - let a: f64x1 = f64x1::new(0.); - let b: f64x1 = f64x1::new(1.); - let e: f64x1 = f64x1::new(0.); - let r: f64x1 = transmute(vext_f64::<0>(transmute(a), transmute(b))); + fn test_vext_f64() { + let a = f64x1::new(0.); + let b = f64x1::new(1.); + let e = f64x1::new(0.); + let r = f64x1::from(vext_f64::<0>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vshld_n_s64() { + fn test_vshld_n_s64() { let a: i64 = 1; let e: i64 = 4; let r: i64 = vshld_n_s64::<2>(a); @@ -653,7 +505,7 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vshld_n_u64() { + fn test_vshld_n_u64() { let a: u64 = 1; let e: u64 = 4; let r: u64 = vshld_n_u64::<2>(a); @@ -661,7 +513,7 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vshrd_n_s64() { + fn test_vshrd_n_s64() { let a: i64 = 4; let e: i64 = 1; let r: i64 = vshrd_n_s64::<2>(a); @@ -669,7 +521,7 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vshrd_n_u64() { + fn test_vshrd_n_u64() { let a: u64 = 4; let e: u64 = 1; let r: u64 = vshrd_n_u64::<2>(a); @@ -677,7 +529,7 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vsrad_n_s64() { + fn test_vsrad_n_s64() { let a: i64 = 1; let b: i64 = 4; let e: i64 = 2; @@ -686,7 +538,7 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vsrad_n_u64() { + fn test_vsrad_n_u64() { let a: u64 = 1; let b: u64 = 4; let e: u64 = 2; @@ -695,298 +547,551 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vdup_n_f64() { + fn test_vdup_n_f64() { let a: f64 = 3.3; let e = f64x1::new(3.3); - let r: f64x1 = transmute(vdup_n_f64(a)); + let r = f64x1::from(vdup_n_f64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vdup_n_p64() { + fn test_vdup_n_p64() { let a: u64 = 3; let e = u64x1::new(3); - let r: u64x1 = transmute(vdup_n_p64(a)); + let r = u64x1::from(vdup_n_p64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vdupq_n_f64() { + fn test_vdupq_n_f64() { let a: f64 = 3.3; let e = f64x2::new(3.3, 3.3); - let r: f64x2 = transmute(vdupq_n_f64(a)); + let r = f64x2::from(vdupq_n_f64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vdupq_n_p64() { + fn test_vdupq_n_p64() { let a: u64 = 3; let e = u64x2::new(3, 3); - let r: u64x2 = transmute(vdupq_n_p64(a)); + let r = u64x2::from(vdupq_n_p64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vmov_n_p64() { + fn test_vmov_n_p64() { let a: u64 = 3; let e = u64x1::new(3); - let r: u64x1 = transmute(vmov_n_p64(a)); + let r = u64x1::from(vmov_n_p64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vmov_n_f64() { + fn test_vmov_n_f64() { let a: f64 = 3.3; let e = f64x1::new(3.3); - let r: f64x1 = transmute(vmov_n_f64(a)); + let r = f64x1::from(vmov_n_f64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vmovq_n_p64() { + fn test_vmovq_n_p64() { let a: u64 = 3; let e = u64x2::new(3, 3); - let r: u64x2 = transmute(vmovq_n_p64(a)); + let r = u64x2::from(vmovq_n_p64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vmovq_n_f64() { + fn test_vmovq_n_f64() { let a: f64 = 3.3; let e = f64x2::new(3.3, 3.3); - let r: f64x2 = transmute(vmovq_n_f64(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vget_high_f64() { - let a = f64x2::new(1.0, 2.0); - let e = f64x1::new(2.0); - let r: f64x1 = transmute(vget_high_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vget_high_p64() { - let a = u64x2::new(1, 2); - let e = u64x1::new(2); - let r: u64x1 = transmute(vget_high_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vget_low_f64() { - let a = f64x2::new(1.0, 2.0); - let e = f64x1::new(1.0); - let r: f64x1 = transmute(vget_low_f64(transmute(a))); + let r = f64x2::from(vmovq_n_f64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vget_low_p64() { - let a = u64x2::new(1, 2); - let e = u64x1::new(1); - let r: u64x1 = transmute(vget_low_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vget_lane_f64() { + fn test_vget_lane_f64() { let v = f64x1::new(1.0); - let r = vget_lane_f64::<0>(transmute(v)); + let r = vget_lane_f64::<0>(v.into()); assert_eq!(r, 1.0); } #[simd_test(enable = "neon")] - unsafe fn test_vgetq_lane_f64() { - let v = f64x2::new(0.0, 1.0); - let r = vgetq_lane_f64::<1>(transmute(v)); - assert_eq!(r, 1.0); - let r = vgetq_lane_f64::<0>(transmute(v)); - assert_eq!(r, 0.0); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopy_lane_s64() { - let a: i64x1 = i64x1::new(1); - let b: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let r: i64x1 = transmute(vcopy_lane_s64::<0, 0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopy_lane_u64() { - let a: u64x1 = u64x1::new(1); - let b: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vcopy_lane_u64::<0, 0>(transmute(a), transmute(b))); + fn test_vcopy_lane_s64() { + let a = i64x1::new(1); + let b = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); + let e = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); + let r = i64x1::from(vcopy_lane_s64::<0, 0>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vcopy_lane_p64() { - let a: i64x1 = i64x1::new(1); - let b: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let r: i64x1 = transmute(vcopy_lane_p64::<0, 0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopy_lane_f64() { - let a: f64 = 1.; - let b: f64 = 0.; - let e: f64 = 0.; - let r: f64 = transmute(vcopy_lane_f64::<0, 0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopy_laneq_s64() { - let a: i64x1 = i64x1::new(1); - let b: i64x2 = i64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF); - let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let r: i64x1 = transmute(vcopy_laneq_s64::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopy_laneq_u64() { - let a: u64x1 = u64x1::new(1); - let b: u64x2 = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vcopy_laneq_u64::<0, 1>(transmute(a), transmute(b))); + fn test_vcopy_lane_u64() { + let a = u64x1::new(1); + let b = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); + let e = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); + let r = u64x1::from(vcopy_lane_u64::<0, 0>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vcopy_laneq_p64() { - let a: i64x1 = i64x1::new(1); - let b: i64x2 = i64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF); - let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let r: i64x1 = transmute(vcopy_laneq_p64::<0, 1>(transmute(a), transmute(b))); + fn test_vcopy_lane_p64() { + let a = u64x1::new(1); + let b = u64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); + let e = u64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); + let r = u64x1::from(vcopy_lane_p64::<0, 0>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vcopy_laneq_f64() { - let a: f64 = 1.; - let b: f64x2 = f64x2::new(0., 0.5); - let e: f64 = 0.5; - let r: f64 = transmute(vcopy_laneq_f64::<0, 1>(transmute(a), transmute(b))); + fn test_vcopy_lane_f64() { + let a = f64x1::from_array([1.]); + let b = f64x1::from_array([0.]); + let e = f64x1::from_array([0.]); + let r = f64x1::from(vcopy_lane_f64::<0, 0>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vbsl_f64() { + fn test_vbsl_f64() { let a = u64x1::new(0x8000000000000000); let b = f64x1::new(-1.23f64); let c = f64x1::new(2.34f64); let e = f64x1::new(-2.34f64); - let r: f64x1 = transmute(vbsl_f64(transmute(a), transmute(b), transmute(c))); + let r = f64x1::from(vbsl_f64(a.into(), b.into(), c.into())); assert_eq!(r, e); } + #[simd_test(enable = "neon")] - unsafe fn test_vbsl_p64() { + fn test_vbsl_p64() { let a = u64x1::new(1); let b = u64x1::new(u64::MAX); let c = u64x1::new(u64::MIN); let e = u64x1::new(1); - let r: u64x1 = transmute(vbsl_p64(transmute(a), transmute(b), transmute(c))); + let r = u64x1::from(vbsl_p64(a.into(), b.into(), c.into())); assert_eq!(r, e); } + #[simd_test(enable = "neon")] - unsafe fn test_vbslq_f64() { + fn test_vbslq_f64() { let a = u64x2::new(1, 0x8000000000000000); let b = f64x2::new(f64::MAX, -1.23f64); let c = f64x2::new(f64::MIN, 2.34f64); let e = f64x2::new(f64::MIN, -2.34f64); - let r: f64x2 = transmute(vbslq_f64(transmute(a), transmute(b), transmute(c))); + let r = f64x2::from(vbslq_f64(a.into(), b.into(), c.into())); assert_eq!(r, e); } + #[simd_test(enable = "neon")] - unsafe fn test_vbslq_p64() { + fn test_vbslq_p64() { let a = u64x2::new(u64::MAX, 1); let b = u64x2::new(u64::MAX, u64::MAX); let c = u64x2::new(u64::MIN, u64::MIN); let e = u64x2::new(u64::MAX, 1); - let r: u64x2 = transmute(vbslq_p64(transmute(a), transmute(b), transmute(c))); + let r = u64x2::from(vbslq_p64(a.into(), b.into(), c.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vld1_f64() { + fn test_vld1_f64() { let a: [f64; 2] = [0., 1.]; let e = f64x1::new(1.); - let r: f64x1 = transmute(vld1_f64(a[1..].as_ptr())); + let r = unsafe { f64x1::from(vld1_f64(a[1..].as_ptr())) }; assert_eq!(r, e) } #[simd_test(enable = "neon")] - unsafe fn test_vld1q_f64() { + fn test_vld1q_f64() { let a: [f64; 3] = [0., 1., 2.]; let e = f64x2::new(1., 2.); - let r: f64x2 = transmute(vld1q_f64(a[1..].as_ptr())); + let r = unsafe { f64x2::from(vld1q_f64(a[1..].as_ptr())) }; assert_eq!(r, e) } #[simd_test(enable = "neon")] - unsafe fn test_vld1_dup_f64() { + fn test_vld1_dup_f64() { let a: [f64; 2] = [1., 42.]; let e = f64x1::new(42.); - let r: f64x1 = transmute(vld1_dup_f64(a[1..].as_ptr())); + let r = unsafe { f64x1::from(vld1_dup_f64(a[1..].as_ptr())) }; assert_eq!(r, e) } #[simd_test(enable = "neon")] - unsafe fn test_vld1q_dup_f64() { + fn test_vld1q_dup_f64() { let elem: f64 = 42.; let e = f64x2::new(42., 42.); - let r: f64x2 = transmute(vld1q_dup_f64(&elem)); + let r = unsafe { f64x2::from(vld1q_dup_f64(&elem)) }; assert_eq!(r, e) } #[simd_test(enable = "neon")] - unsafe fn test_vld1_lane_f64() { + fn test_vld1_lane_f64() { let a = f64x1::new(0.); let elem: f64 = 42.; let e = f64x1::new(42.); - let r: f64x1 = transmute(vld1_lane_f64::<0>(&elem, transmute(a))); + let r = unsafe { f64x1::from(vld1_lane_f64::<0>(&elem, a.into())) }; assert_eq!(r, e) } #[simd_test(enable = "neon")] - unsafe fn test_vld1q_lane_f64() { + fn test_vld1q_lane_f64() { let a = f64x2::new(0., 1.); let elem: f64 = 42.; let e = f64x2::new(0., 42.); - let r: f64x2 = transmute(vld1q_lane_f64::<1>(&elem, transmute(a))); + let r = unsafe { f64x2::from(vld1q_lane_f64::<1>(&elem, a.into())) }; assert_eq!(r, e) } #[simd_test(enable = "neon")] - unsafe fn test_vst1_f64() { + fn test_vst1_f64() { let mut vals = [0_f64; 2]; let a = f64x1::new(1.); - vst1_f64(vals[1..].as_mut_ptr(), transmute(a)); + unsafe { + vst1_f64(vals[1..].as_mut_ptr(), a.into()); + } assert_eq!(vals[0], 0.); assert_eq!(vals[1], 1.); } #[simd_test(enable = "neon")] - unsafe fn test_vst1q_f64() { + fn test_vst1q_f64() { let mut vals = [0_f64; 3]; let a = f64x2::new(1., 2.); - vst1q_f64(vals[1..].as_mut_ptr(), transmute(a)); + unsafe { + vst1q_f64(vals[1..].as_mut_ptr(), a.into()); + } assert_eq!(vals[0], 0.); assert_eq!(vals[1], 1.); assert_eq!(vals[2], 2.); } + + macro_rules! wide_store_load_roundtrip { + ($elem_ty:ty, $len:expr, $vec_ty:ty, $store:expr, $load:expr) => { + let vals: [$elem_ty; $len] = crate::array::from_fn(|i| i as $elem_ty); + let a: $vec_ty = transmute(vals); + let mut tmp = core::mem::MaybeUninit::<[$elem_ty; $len]>::uninit(); + $store(tmp.as_mut_ptr().cast(), a); + + // With Miri this will check that all elements were initialized. + let tmp = tmp.assume_init(); + + let r: $vec_ty = $load(tmp.as_ptr().cast()); + let out: [$elem_ty; $len] = transmute(r); + assert_eq!(out, vals); + }; + } + + macro_rules! wide_store_load_roundtrip_fp16 { + ($( $name:ident $args:tt);* $(;)?) => { + $( + #[cfg_attr(miri, ignore)] // uses unsupported vendor intrinsics + #[simd_test(enable = "neon,fp16")] + #[cfg(not(target_arch = "arm64ec"))] + unsafe fn $name() { + wide_store_load_roundtrip! $args; + } + )* + }; + } + + wide_store_load_roundtrip_fp16! { + test_vld1_f16_x2(f16, 8, float16x4x2_t, vst1_f16_x2, vld1_f16_x2); + test_vld1_f16_x3(f16, 12, float16x4x3_t, vst1_f16_x3, vld1_f16_x3); + test_vld1_f16_x4(f16, 16, float16x4x4_t, vst1_f16_x4, vld1_f16_x4); + + test_vld1q_f16_x2(f16, 16, float16x8x2_t, vst1q_f16_x2, vld1q_f16_x2); + test_vld1q_f16_x3(f16, 24, float16x8x3_t, vst1q_f16_x3, vld1q_f16_x3); + test_vld1q_f16_x4(f16, 32, float16x8x4_t, vst1q_f16_x4, vld1q_f16_x4); + + test_vld2_f16(f16, 8, float16x4x2_t, vst2_f16, vld2_f16); + test_vld3_f16(f16, 12, float16x4x3_t, vst3_f16, vld3_f16); + test_vld4_f16(f16, 16, float16x4x4_t, vst4_f16, vld4_f16); + + test_vld2q_f16(f16, 16, float16x8x2_t, vst2q_f16, vld2q_f16); + test_vld3q_f16(f16, 24, float16x8x3_t, vst3q_f16, vld3q_f16); + test_vld4q_f16(f16, 32, float16x8x4_t, vst4q_f16, vld4q_f16); + } + + macro_rules! wide_store_load_roundtrip_aes { + ($( $name:ident $args:tt);* $(;)?) => { + $( + #[simd_test(enable = "neon,aes")] + unsafe fn $name() { + wide_store_load_roundtrip! $args; + } + )* + }; + } + + wide_store_load_roundtrip_aes! { + test_vld1_p64_x2(p64, 2, poly64x1x2_t, vst1_p64_x2, vld1_p64_x2); + test_vld1_p64_x3(p64, 3, poly64x1x3_t, vst1_p64_x3, vld1_p64_x3); + test_vld1_p64_x4(p64, 4, poly64x1x4_t, vst1_p64_x4, vld1_p64_x4); + + test_vld1q_p64_x2(p64, 4, poly64x2x2_t, vst1q_p64_x2, vld1q_p64_x2); + test_vld1q_p64_x3(p64, 6, poly64x2x3_t, vst1q_p64_x3, vld1q_p64_x3); + test_vld1q_p64_x4(p64, 8, poly64x2x4_t, vst1q_p64_x4, vld1q_p64_x4); + } + + macro_rules! wide_store_load_roundtrip_neon { + ($( $name:ident $args:tt);* $(;)?) => { + $( + #[simd_test(enable = "neon")] + unsafe fn $name() { + wide_store_load_roundtrip! $args; + } + )* + }; + } + + wide_store_load_roundtrip_neon! { + test_vld1_f32_x2(f32, 4, float32x2x2_t, vst1_f32_x2, vld1_f32_x2); + test_vld1_f32_x3(f32, 6, float32x2x3_t, vst1_f32_x3, vld1_f32_x3); + test_vld1_f32_x4(f32, 8, float32x2x4_t, vst1_f32_x4, vld1_f32_x4); + + test_vld1q_f32_x2(f32, 8, float32x4x2_t, vst1q_f32_x2, vld1q_f32_x2); + test_vld1q_f32_x3(f32, 12, float32x4x3_t, vst1q_f32_x3, vld1q_f32_x3); + test_vld1q_f32_x4(f32, 16, float32x4x4_t, vst1q_f32_x4, vld1q_f32_x4); + + test_vld1_f64_x2(f64, 2, float64x1x2_t, vst1_f64_x2, vld1_f64_x2); + test_vld1_f64_x3(f64, 3, float64x1x3_t, vst1_f64_x3, vld1_f64_x3); + test_vld1_f64_x4(f64, 4, float64x1x4_t, vst1_f64_x4, vld1_f64_x4); + + test_vld1q_f64_x2(f64, 4, float64x2x2_t, vst1q_f64_x2, vld1q_f64_x2); + test_vld1q_f64_x3(f64, 6, float64x2x3_t, vst1q_f64_x3, vld1q_f64_x3); + test_vld1q_f64_x4(f64, 8, float64x2x4_t, vst1q_f64_x4, vld1q_f64_x4); + + test_vld1_s8_x2(i8, 16, int8x8x2_t, vst1_s8_x2, vld1_s8_x2); + test_vld1_s8_x3(i8, 24, int8x8x3_t, vst1_s8_x3, vld1_s8_x3); + test_vld1_s8_x4(i8, 32, int8x8x4_t, vst1_s8_x4, vld1_s8_x4); + + test_vld1q_s8_x2(i8, 32, int8x16x2_t, vst1q_s8_x2, vld1q_s8_x2); + test_vld1q_s8_x3(i8, 48, int8x16x3_t, vst1q_s8_x3, vld1q_s8_x3); + test_vld1q_s8_x4(i8, 64, int8x16x4_t, vst1q_s8_x4, vld1q_s8_x4); + + test_vld1_s16_x2(i16, 8, int16x4x2_t, vst1_s16_x2, vld1_s16_x2); + test_vld1_s16_x3(i16, 12, int16x4x3_t, vst1_s16_x3, vld1_s16_x3); + test_vld1_s16_x4(i16, 16, int16x4x4_t, vst1_s16_x4, vld1_s16_x4); + + test_vld1q_s16_x2(i16, 16, int16x8x2_t, vst1q_s16_x2, vld1q_s16_x2); + test_vld1q_s16_x3(i16, 24, int16x8x3_t, vst1q_s16_x3, vld1q_s16_x3); + test_vld1q_s16_x4(i16, 32, int16x8x4_t, vst1q_s16_x4, vld1q_s16_x4); + + test_vld1_s32_x2(i32, 4, int32x2x2_t, vst1_s32_x2, vld1_s32_x2); + test_vld1_s32_x3(i32, 6, int32x2x3_t, vst1_s32_x3, vld1_s32_x3); + test_vld1_s32_x4(i32, 8, int32x2x4_t, vst1_s32_x4, vld1_s32_x4); + + test_vld1q_s32_x2(i32, 8, int32x4x2_t, vst1q_s32_x2, vld1q_s32_x2); + test_vld1q_s32_x3(i32, 12, int32x4x3_t, vst1q_s32_x3, vld1q_s32_x3); + test_vld1q_s32_x4(i32, 16, int32x4x4_t, vst1q_s32_x4, vld1q_s32_x4); + + test_vld1_s64_x2(i64, 2, int64x1x2_t, vst1_s64_x2, vld1_s64_x2); + test_vld1_s64_x3(i64, 3, int64x1x3_t, vst1_s64_x3, vld1_s64_x3); + test_vld1_s64_x4(i64, 4, int64x1x4_t, vst1_s64_x4, vld1_s64_x4); + + test_vld1q_s64_x2(i64, 4, int64x2x2_t, vst1q_s64_x2, vld1q_s64_x2); + test_vld1q_s64_x3(i64, 6, int64x2x3_t, vst1q_s64_x3, vld1q_s64_x3); + test_vld1q_s64_x4(i64, 8, int64x2x4_t, vst1q_s64_x4, vld1q_s64_x4); + + test_vld1_u8_x2(u8, 16, uint8x8x2_t, vst1_u8_x2, vld1_u8_x2); + test_vld1_u8_x3(u8, 24, uint8x8x3_t, vst1_u8_x3, vld1_u8_x3); + test_vld1_u8_x4(u8, 32, uint8x8x4_t, vst1_u8_x4, vld1_u8_x4); + + test_vld1q_u8_x2(u8, 32, uint8x16x2_t, vst1q_u8_x2, vld1q_u8_x2); + test_vld1q_u8_x3(u8, 48, uint8x16x3_t, vst1q_u8_x3, vld1q_u8_x3); + test_vld1q_u8_x4(u8, 64, uint8x16x4_t, vst1q_u8_x4, vld1q_u8_x4); + + test_vld1_u16_x2(u16, 8, uint16x4x2_t, vst1_u16_x2, vld1_u16_x2); + test_vld1_u16_x3(u16, 12, uint16x4x3_t, vst1_u16_x3, vld1_u16_x3); + test_vld1_u16_x4(u16, 16, uint16x4x4_t, vst1_u16_x4, vld1_u16_x4); + + test_vld1q_u16_x2(u16, 16, uint16x8x2_t, vst1q_u16_x2, vld1q_u16_x2); + test_vld1q_u16_x3(u16, 24, uint16x8x3_t, vst1q_u16_x3, vld1q_u16_x3); + test_vld1q_u16_x4(u16, 32, uint16x8x4_t, vst1q_u16_x4, vld1q_u16_x4); + + test_vld1_u32_x2(u32, 4, uint32x2x2_t, vst1_u32_x2, vld1_u32_x2); + test_vld1_u32_x3(u32, 6, uint32x2x3_t, vst1_u32_x3, vld1_u32_x3); + test_vld1_u32_x4(u32, 8, uint32x2x4_t, vst1_u32_x4, vld1_u32_x4); + + test_vld1q_u32_x2(u32, 8, uint32x4x2_t, vst1q_u32_x2, vld1q_u32_x2); + test_vld1q_u32_x3(u32, 12, uint32x4x3_t, vst1q_u32_x3, vld1q_u32_x3); + test_vld1q_u32_x4(u32, 16, uint32x4x4_t, vst1q_u32_x4, vld1q_u32_x4); + + test_vld1_u64_x2(u64, 2, uint64x1x2_t, vst1_u64_x2, vld1_u64_x2); + test_vld1_u64_x3(u64, 3, uint64x1x3_t, vst1_u64_x3, vld1_u64_x3); + test_vld1_u64_x4(u64, 4, uint64x1x4_t, vst1_u64_x4, vld1_u64_x4); + + test_vld1q_u64_x2(u64, 4, uint64x2x2_t, vst1q_u64_x2, vld1q_u64_x2); + test_vld1q_u64_x3(u64, 6, uint64x2x3_t, vst1q_u64_x3, vld1q_u64_x3); + test_vld1q_u64_x4(u64, 8, uint64x2x4_t, vst1q_u64_x4, vld1q_u64_x4); + + test_vld1_p8_x2(p8, 16, poly8x8x2_t, vst1_p8_x2, vld1_p8_x2); + test_vld1_p8_x3(p8, 24, poly8x8x3_t, vst1_p8_x3, vld1_p8_x3); + test_vld1_p8_x4(p8, 32, poly8x8x4_t, vst1_p8_x4, vld1_p8_x4); + + test_vld1q_p8_x2(p8, 32, poly8x16x2_t, vst1q_p8_x2, vld1q_p8_x2); + test_vld1q_p8_x3(p8, 48, poly8x16x3_t, vst1q_p8_x3, vld1q_p8_x3); + test_vld1q_p8_x4(p8, 64, poly8x16x4_t, vst1q_p8_x4, vld1q_p8_x4); + + test_vld1_p16_x2(p16, 8, poly16x4x2_t, vst1_p16_x2, vld1_p16_x2); + test_vld1_p16_x3(p16, 12, poly16x4x3_t, vst1_p16_x3, vld1_p16_x3); + test_vld1_p16_x4(p16, 16, poly16x4x4_t, vst1_p16_x4, vld1_p16_x4); + + test_vld1q_p16_x2(p16, 16, poly16x8x2_t, vst1q_p16_x2, vld1q_p16_x2); + test_vld1q_p16_x3(p16, 24, poly16x8x3_t, vst1q_p16_x3, vld1q_p16_x3); + test_vld1q_p16_x4(p16, 32, poly16x8x4_t, vst1q_p16_x4, vld1q_p16_x4); + } + + wide_store_load_roundtrip_neon! { + test_vld2_f32(f32, 4, float32x2x2_t, vst2_f32, vld2_f32); + test_vld3_f32(f32, 6, float32x2x3_t, vst3_f32, vld3_f32); + test_vld4_f32(f32, 8, float32x2x4_t, vst4_f32, vld4_f32); + + test_vld2q_f32(f32, 8, float32x4x2_t, vst2q_f32, vld2q_f32); + test_vld3q_f32(f32, 12, float32x4x3_t, vst3q_f32, vld3q_f32); + test_vld4q_f32(f32, 16, float32x4x4_t, vst4q_f32, vld4q_f32); + + test_vld2_f64(f64, 2, float64x1x2_t, vst2_f64, vld2_f64); + test_vld3_f64(f64, 3, float64x1x3_t, vst3_f64, vld3_f64); + test_vld4_f64(f64, 4, float64x1x4_t, vst4_f64, vld4_f64); + + test_vld2q_f64(f64, 4, float64x2x2_t, vst2q_f64, vld2q_f64); + test_vld3q_f64(f64, 6, float64x2x3_t, vst3q_f64, vld3q_f64); + test_vld4q_f64(f64, 8, float64x2x4_t, vst4q_f64, vld4q_f64); + + test_vld2_s8(i8, 16, int8x8x2_t, vst2_s8, vld2_s8); + test_vld3_s8(i8, 24, int8x8x3_t, vst3_s8, vld3_s8); + test_vld4_s8(i8, 32, int8x8x4_t, vst4_s8, vld4_s8); + + test_vld2q_s8(i8, 32, int8x16x2_t, vst2q_s8, vld2q_s8); + test_vld3q_s8(i8, 48, int8x16x3_t, vst3q_s8, vld3q_s8); + test_vld4q_s8(i8, 64, int8x16x4_t, vst4q_s8, vld4q_s8); + + test_vld2_s16(i16, 8, int16x4x2_t, vst2_s16, vld2_s16); + test_vld3_s16(i16, 12, int16x4x3_t, vst3_s16, vld3_s16); + test_vld4_s16(i16, 16, int16x4x4_t, vst4_s16, vld4_s16); + + test_vld2q_s16(i16, 16, int16x8x2_t, vst2q_s16, vld2q_s16); + test_vld3q_s16(i16, 24, int16x8x3_t, vst3q_s16, vld3q_s16); + test_vld4q_s16(i16, 32, int16x8x4_t, vst4q_s16, vld4q_s16); + + test_vld2_s32(i32, 4, int32x2x2_t, vst2_s32, vld2_s32); + test_vld3_s32(i32, 6, int32x2x3_t, vst3_s32, vld3_s32); + test_vld4_s32(i32, 8, int32x2x4_t, vst4_s32, vld4_s32); + + test_vld2q_s32(i32, 8, int32x4x2_t, vst2q_s32, vld2q_s32); + test_vld3q_s32(i32, 12, int32x4x3_t, vst3q_s32, vld3q_s32); + test_vld4q_s32(i32, 16, int32x4x4_t, vst4q_s32, vld4q_s32); + + test_vld2_s64(i64, 2, int64x1x2_t, vst2_s64, vld2_s64); + test_vld3_s64(i64, 3, int64x1x3_t, vst3_s64, vld3_s64); + test_vld4_s64(i64, 4, int64x1x4_t, vst4_s64, vld4_s64); + + test_vld2q_s64(i64, 4, int64x2x2_t, vst2q_s64, vld2q_s64); + test_vld3q_s64(i64, 6, int64x2x3_t, vst3q_s64, vld3q_s64); + test_vld4q_s64(i64, 8, int64x2x4_t, vst4q_s64, vld4q_s64); + + test_vld2_u8(u8, 16, uint8x8x2_t, vst2_u8, vld2_u8); + test_vld3_u8(u8, 24, uint8x8x3_t, vst3_u8, vld3_u8); + test_vld4_u8(u8, 32, uint8x8x4_t, vst4_u8, vld4_u8); + + test_vld2q_u8(u8, 32, uint8x16x2_t, vst2q_u8, vld2q_u8); + test_vld3q_u8(u8, 48, uint8x16x3_t, vst3q_u8, vld3q_u8); + test_vld4q_u8(u8, 64, uint8x16x4_t, vst4q_u8, vld4q_u8); + + test_vld2_u16(u16, 8, uint16x4x2_t, vst2_u16, vld2_u16); + test_vld3_u16(u16, 12, uint16x4x3_t, vst3_u16, vld3_u16); + test_vld4_u16(u16, 16, uint16x4x4_t, vst4_u16, vld4_u16); + + test_vld2q_u16(u16, 16, uint16x8x2_t, vst2q_u16, vld2q_u16); + test_vld3q_u16(u16, 24, uint16x8x3_t, vst3q_u16, vld3q_u16); + test_vld4q_u16(u16, 32, uint16x8x4_t, vst4q_u16, vld4q_u16); + + test_vld2_u32(u32, 4, uint32x2x2_t, vst2_u32, vld2_u32); + test_vld3_u32(u32, 6, uint32x2x3_t, vst3_u32, vld3_u32); + test_vld4_u32(u32, 8, uint32x2x4_t, vst4_u32, vld4_u32); + + test_vld2q_u32(u32, 8, uint32x4x2_t, vst2q_u32, vld2q_u32); + test_vld3q_u32(u32, 12, uint32x4x3_t, vst3q_u32, vld3q_u32); + test_vld4q_u32(u32, 16, uint32x4x4_t, vst4q_u32, vld4q_u32); + + test_vld2_u64(u64, 2, uint64x1x2_t, vst2_u64, vld2_u64); + test_vld3_u64(u64, 3, uint64x1x3_t, vst3_u64, vld3_u64); + test_vld4_u64(u64, 4, uint64x1x4_t, vst4_u64, vld4_u64); + + test_vld2q_u64(u64, 4, uint64x2x2_t, vst2q_u64, vld2q_u64); + test_vld3q_u64(u64, 6, uint64x2x3_t, vst3q_u64, vld3q_u64); + test_vld4q_u64(u64, 8, uint64x2x4_t, vst4q_u64, vld4q_u64); + + test_vld2_p8(p8, 16, poly8x8x2_t, vst2_p8, vld2_p8); + test_vld3_p8(p8, 24, poly8x8x3_t, vst3_p8, vld3_p8); + test_vld4_p8(p8, 32, poly8x8x4_t, vst4_p8, vld4_p8); + + test_vld2q_p8(p8, 32, poly8x16x2_t, vst2q_p8, vld2q_p8); + test_vld3q_p8(p8, 48, poly8x16x3_t, vst3q_p8, vld3q_p8); + test_vld4q_p8(p8, 64, poly8x16x4_t, vst4q_p8, vld4q_p8); + + test_vld2_p16(p16, 8, poly16x4x2_t, vst2_p16, vld2_p16); + test_vld3_p16(p16, 12, poly16x4x3_t, vst3_p16, vld3_p16); + test_vld4_p16(p16, 16, poly16x4x4_t, vst4_p16, vld4_p16); + + test_vld2q_p16(p16, 16, poly16x8x2_t, vst2q_p16, vld2q_p16); + test_vld3q_p16(p16, 24, poly16x8x3_t, vst3q_p16, vld3q_p16); + test_vld4q_p16(p16, 32, poly16x8x4_t, vst4q_p16, vld4q_p16); + } + + macro_rules! lane_wide_store_load_roundtrip { + ($elem_ty:ty, $len:expr, $idx:expr, $vec_ty:ty, $store:ident, $load:ident) => { + let vals: [$elem_ty; $len] = crate::array::from_fn(|i| i as $elem_ty); + let a: $vec_ty = transmute(vals); + let mut tmp = [0 as $elem_ty; 4]; + $store::<$idx>(tmp.as_mut_ptr().cast(), a); + let r: $vec_ty = $load::<$idx>(tmp.as_ptr().cast(), a); + let out: [$elem_ty; $len] = transmute(r); + assert_eq!(out, vals); + }; + } + + macro_rules! lane_wide_store_load_roundtrip_neon { + ($( $name:ident $args:tt);* $(;)?) => { + $( + #[cfg_attr(miri, ignore)] // uses unsupported vendor intrinsics + #[simd_test(enable = "neon")] + unsafe fn $name() { + lane_wide_store_load_roundtrip! $args; + } + )* + }; + } + + lane_wide_store_load_roundtrip_neon! { + test_vld2q_lane_s8(i8, 32, 15, int8x16x2_t, vst2q_lane_s8, vld2q_lane_s8); + test_vld3q_lane_s8(i8, 48, 15, int8x16x3_t, vst3q_lane_s8, vld3q_lane_s8); + test_vld4q_lane_s8(i8, 64, 15, int8x16x4_t, vst4q_lane_s8, vld4q_lane_s8); + + test_vld2q_lane_u8(u8, 32, 15, uint8x16x2_t, vst2q_lane_u8, vld2q_lane_u8); + test_vld3q_lane_u8(u8, 48, 15, uint8x16x3_t, vst3q_lane_u8, vld3q_lane_u8); + test_vld4q_lane_u8(u8, 64, 15, uint8x16x4_t, vst4q_lane_u8, vld4q_lane_u8); + + test_vld2_lane_s64(i64, 2, 0, int64x1x2_t, vst2_lane_s64, vld2_lane_s64); + test_vld3_lane_s64(i64, 3, 0, int64x1x3_t, vst3_lane_s64, vld3_lane_s64); + test_vld4_lane_s64(i64, 4, 0, int64x1x4_t, vst4_lane_s64, vld4_lane_s64); + test_vld2q_lane_s64(i64, 4, 1, int64x2x2_t, vst2q_lane_s64, vld2q_lane_s64); + test_vld3q_lane_s64(i64, 6, 1, int64x2x3_t, vst3q_lane_s64, vld3q_lane_s64); + test_vld4q_lane_s64(i64, 8, 1, int64x2x4_t, vst4q_lane_s64, vld4q_lane_s64); + + test_vld2_lane_u64(u64, 2, 0, uint64x1x2_t, vst2_lane_u64, vld2_lane_u64); + test_vld3_lane_u64(u64, 3, 0, uint64x1x3_t, vst3_lane_u64, vld3_lane_u64); + test_vld4_lane_u64(u64, 4, 0, uint64x1x4_t, vst4_lane_u64, vld4_lane_u64); + test_vld2q_lane_u64(u64, 4, 1, uint64x2x2_t, vst2q_lane_u64, vld2q_lane_u64); + test_vld3q_lane_u64(u64, 6, 1, uint64x2x3_t, vst3q_lane_u64, vld3q_lane_u64); + test_vld4q_lane_u64(u64, 8, 1, uint64x2x4_t, vst4q_lane_u64, vld4q_lane_u64); + } } #[cfg(test)] diff --git a/library/stdarch/crates/core_arch/src/aarch64/prefetch.rs b/library/stdarch/crates/core_arch/src/aarch64/prefetch.rs index 4dcbc9549f115..88e5c0987f34d 100644 --- a/library/stdarch/crates/core_arch/src/aarch64/prefetch.rs +++ b/library/stdarch/crates/core_arch/src/aarch64/prefetch.rs @@ -2,7 +2,7 @@ use stdarch_test::assert_instr; unsafe extern "unadjusted" { - #[link_name = "llvm.prefetch"] + #[link_name = "llvm.prefetch.p0"] fn prefetch(p: *const i8, rw: i32, loc: i32, ty: i32); } diff --git a/library/stdarch/crates/core_arch/src/aarch64/rand.rs b/library/stdarch/crates/core_arch/src/aarch64/rand.rs new file mode 100644 index 0000000000000..3f52cf2ce8657 --- /dev/null +++ b/library/stdarch/crates/core_arch/src/aarch64/rand.rs @@ -0,0 +1,48 @@ +//! AArch64 Random Number intrinsics +//! +//! [ACLE documentation](https://arm-software.github.io/acle/main/acle.html#random-number-generation-intrinsics) + +#[cfg(test)] +use stdarch_test::assert_instr; + +unsafe extern "unadjusted" { + #[link_name = "llvm.aarch64.rndr"] + fn rndr_() -> Tuple; + + #[link_name = "llvm.aarch64.rndrrs"] + fn rndrrs_() -> Tuple; +} + +#[repr(C)] +struct Tuple { + bits: u64, + status: bool, +} + +/// Stores a 64-bit random number into the object pointed to by the argument and returns +/// zero. If the implementation could not generate a random number within a reasonable +/// period of time the object pointed to by the input is set to zero and a non-zero value +/// is returned. +#[inline] +#[target_feature(enable = "rand")] +#[cfg_attr(test, assert_instr(mrs))] +#[unstable(feature = "stdarch_aarch64_rand", issue = "153514")] +pub unsafe fn __rndr(value: *mut u64) -> i32 { + let Tuple { bits, status } = rndr_(); + unsafe { *value = bits }; + status as i32 +} + +/// Reseeds the random number generator. After that stores a 64-bit random number into +/// the object pointed to by the argument and returns zero. If the implementation could +/// not generate a random number within a reasonable period of time the object pointed +/// to by the input is set to zero and a non-zero value is returned. +#[inline] +#[target_feature(enable = "rand")] +#[cfg_attr(test, assert_instr(mrs))] +#[unstable(feature = "stdarch_aarch64_rand", issue = "153514")] +pub unsafe fn __rndrrs(value: *mut u64) -> i32 { + let Tuple { bits, status } = rndrrs_(); + unsafe { *value = bits }; + status as i32 +} diff --git a/library/stdarch/crates/core_arch/src/aarch64/sve/generated.rs b/library/stdarch/crates/core_arch/src/aarch64/sve/generated.rs new file mode 100644 index 0000000000000..4e5547b1d083e --- /dev/null +++ b/library/stdarch/crates/core_arch/src/aarch64/sve/generated.rs @@ -0,0 +1,44982 @@ +// This code is automatically generated. DO NOT MODIFY. +// +// Instead, modify `crates/stdarch-gen-arm/spec/` and run the following command to re-generate this file: +// +// ``` +// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec +// ``` +#![allow(improper_ctypes)] + +#[cfg(test)] +use stdarch_test::assert_instr; + +use super::*; +use crate::core_arch::arch::aarch64::*; +use super::{AsSigned, AsUnsigned}; + +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fabd.nxv4f32")] + fn _svabd_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svabd_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svabd_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svabd_f32_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svabd_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svabd_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svabd_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fabd.nxv2f64")] + fn _svabd_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svabd_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svabd_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svabd_f64_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svabd_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svabd_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svabd_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabd.nxv16i8")] + fn _svabd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svabd_s8_m(pg, op1, op2) } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svabd_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svabd_s8_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svabd_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svabd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svabd_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabd.nxv8i16")] + fn _svabd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svabd_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svabd_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svabd_s16_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svabd_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svabd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svabd_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabd.nxv4i32")] + fn _svabd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svabd_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svabd_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svabd_s32_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svabd_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svabd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svabd_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabd.nxv2i64")] + fn _svabd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svabd_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svabd_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svabd_s64_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svabd_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svabd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svabd_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabd.nxv16i8")] + fn _svabd_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svabd_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svabd_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svabd_u8_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svabd_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svabd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svabd_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabd.nxv8i16")] + fn _svabd_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svabd_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svabd_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svabd_u16_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svabd_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svabd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svabd_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabd.nxv4i32")] + fn _svabd_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svabd_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svabd_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svabd_u32_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svabd_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svabd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svabd_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabd.nxv2i64")] + fn _svabd_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svabd_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svabd_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svabd_u64_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svabd_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svabd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svabd_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabs))] +pub fn svabs_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fabs.nxv4f32")] + fn _svabs_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svabs_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabs))] +pub fn svabs_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svabs_f32_m(op, pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabs))] +pub fn svabs_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svabs_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabs))] +pub fn svabs_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fabs.nxv2f64")] + fn _svabs_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svabs_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabs))] +pub fn svabs_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svabs_f64_m(op, pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabs))] +pub fn svabs_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svabs_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.abs.nxv16i8")] + fn _svabs_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svabs_s8_m(inactive, pg, op) } +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t { + svabs_s8_m(op, pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t { + svabs_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.abs.nxv8i16")] + fn _svabs_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svabs_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svabs_s16_m(op, pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svabs_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.abs.nxv4i32")] + fn _svabs_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svabs_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svabs_s32_m(op, pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svabs_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.abs.nxv2i64")] + fn _svabs_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svabs_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svabs_s64_m(op, pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svabs_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Absolute compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacge[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacge_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.facge.nxv4f32")] + fn _svacge_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t; + } + unsafe { _svacge_f32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Absolute compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacge[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacge_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svacge_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Absolute compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacge[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacge_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.facge.nxv2f64")] + fn _svacge_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t; + } + unsafe { _svacge_f64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Absolute compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacge[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacge_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svacge_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Absolute compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacgt[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svacgt_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.facgt.nxv4f32")] + fn _svacgt_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t; + } + unsafe { _svacgt_f32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Absolute compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacgt[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svacgt_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svacgt_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Absolute compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacgt[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svacgt_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.facgt.nxv2f64")] + fn _svacgt_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t; + } + unsafe { _svacgt_f64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Absolute compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacgt[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svacgt_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svacgt_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Absolute compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacle[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacle_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + svacge_f32(pg, op2, op1) +} +#[doc = "Absolute compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacle[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacle_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svacle_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Absolute compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacle[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacle_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + svacge_f64(pg, op2, op1) +} +#[doc = "Absolute compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacle[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacle_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svacle_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Absolute compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaclt[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svaclt_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + svacgt_f32(pg, op2, op1) +} +#[doc = "Absolute compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaclt[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svaclt_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svaclt_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Absolute compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaclt[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svaclt_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + svacgt_f64(pg, op2, op1) +} +#[doc = "Absolute compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaclt[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svaclt_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svaclt_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fadd.nxv4f32")] + fn _svadd_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svadd_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svadd_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svadd_f32_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svadd_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svadd_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svadd_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fadd.nxv2f64")] + fn _svadd_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svadd_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svadd_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svadd_f64_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svadd_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svadd_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svadd_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.add.nxv16i8")] + fn _svadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svadd_s8_m(pg, op1, op2) } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svadd_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svadd_s8_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svadd_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svadd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svadd_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.add.nxv8i16")] + fn _svadd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svadd_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svadd_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svadd_s16_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svadd_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svadd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svadd_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.add.nxv4i32")] + fn _svadd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svadd_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svadd_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svadd_s32_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svadd_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svadd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svadd_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.add.nxv2i64")] + fn _svadd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svadd_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svadd_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svadd_s64_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svadd_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svadd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svadd_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svadd_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svadd_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svadd_u8_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svadd_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svadd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svadd_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svadd_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svadd_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svadd_u16_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svadd_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svadd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svadd_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svadd_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svadd_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svadd_u32_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svadd_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svadd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svadd_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svadd_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svadd_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svadd_u64_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svadd_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svadd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svadd_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Add reduction (strictly-ordered)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadda[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadda))] +pub fn svadda_f32(pg: svbool_t, initial: f32, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fadda.nxv4f32")] + fn _svadda_f32(pg: svbool4_t, initial: f32, op: svfloat32_t) -> f32; + } + unsafe { _svadda_f32(pg.sve_into(), initial, op) } +} +#[doc = "Add reduction (strictly-ordered)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadda[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadda))] +pub fn svadda_f64(pg: svbool_t, initial: f64, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fadda.nxv2f64")] + fn _svadda_f64(pg: svbool2_t, initial: f64, op: svfloat64_t) -> f64; + } + unsafe { _svadda_f64(pg.sve_into(), initial, op) } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(faddv))] +pub fn svaddv_f32(pg: svbool_t, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.faddv.nxv4f32")] + fn _svaddv_f32(pg: svbool4_t, op: svfloat32_t) -> f32; + } + unsafe { _svaddv_f32(pg.sve_into(), op) } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(faddv))] +pub fn svaddv_f64(pg: svbool_t, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.faddv.nxv2f64")] + fn _svaddv_f64(pg: svbool2_t, op: svfloat64_t) -> f64; + } + unsafe { _svaddv_f64(pg.sve_into(), op) } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddv))] +pub fn svaddv_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddv.nxv2i64")] + fn _svaddv_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svaddv_s64(pg.sve_into(), op) } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddv))] +pub fn svaddv_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddv.nxv2i64")] + fn _svaddv_u64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svaddv_u64(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddv))] +pub fn svaddv_s8(pg: svbool_t, op: svint8_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddv.nxv16i8")] + fn _svaddv_s8(pg: svbool_t, op: svint8_t) -> i64; + } + unsafe { _svaddv_s8(pg, op) } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddv))] +pub fn svaddv_s16(pg: svbool_t, op: svint16_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddv.nxv8i16")] + fn _svaddv_s16(pg: svbool8_t, op: svint16_t) -> i64; + } + unsafe { _svaddv_s16(pg.sve_into(), op) } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddv))] +pub fn svaddv_s32(pg: svbool_t, op: svint32_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddv.nxv4i32")] + fn _svaddv_s32(pg: svbool4_t, op: svint32_t) -> i64; + } + unsafe { _svaddv_s32(pg.sve_into(), op) } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddv))] +pub fn svaddv_u8(pg: svbool_t, op: svuint8_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddv.nxv16i8")] + fn _svaddv_u8(pg: svbool_t, op: svint8_t) -> i64; + } + unsafe { _svaddv_u8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddv))] +pub fn svaddv_u16(pg: svbool_t, op: svuint16_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddv.nxv8i16")] + fn _svaddv_u16(pg: svbool8_t, op: svint16_t) -> i64; + } + unsafe { _svaddv_u16(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddv))] +pub fn svaddv_u32(pg: svbool_t, op: svuint32_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddv.nxv4i32")] + fn _svaddv_u32(pg: svbool4_t, op: svint32_t) -> i64; + } + unsafe { _svaddv_u32(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Compute vector addresses for 8-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrb[_u32base]_[s32]offset)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrb_u32base_s32offset(bases: svuint32_t, offsets: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrb.nxv4i32")] + fn _svadrb_u32base_s32offset(bases: svint32_t, offsets: svint32_t) -> svint32_t; + } + unsafe { _svadrb_u32base_s32offset(bases.as_signed(), offsets).as_unsigned() } +} +#[doc = "Compute vector addresses for 16-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrh[_u32base]_[s32]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrh_u32base_s32index(bases: svuint32_t, indices: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrh.nxv4i32")] + fn _svadrh_u32base_s32index(bases: svint32_t, indices: svint32_t) -> svint32_t; + } + unsafe { _svadrh_u32base_s32index(bases.as_signed(), indices).as_unsigned() } +} +#[doc = "Compute vector addresses for 32-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrw[_u32base]_[s32]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrw_u32base_s32index(bases: svuint32_t, indices: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrw.nxv4i32")] + fn _svadrw_u32base_s32index(bases: svint32_t, indices: svint32_t) -> svint32_t; + } + unsafe { _svadrw_u32base_s32index(bases.as_signed(), indices).as_unsigned() } +} +#[doc = "Compute vector addresses for 64-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrd[_u32base]_[s32]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrd_u32base_s32index(bases: svuint32_t, indices: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrd.nxv4i32")] + fn _svadrd_u32base_s32index(bases: svint32_t, indices: svint32_t) -> svint32_t; + } + unsafe { _svadrd_u32base_s32index(bases.as_signed(), indices).as_unsigned() } +} +#[doc = "Compute vector addresses for 8-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrb[_u32base]_[u32]offset)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrb_u32base_u32offset(bases: svuint32_t, offsets: svuint32_t) -> svuint32_t { + unsafe { svadrb_u32base_s32offset(bases, offsets.as_signed()) } +} +#[doc = "Compute vector addresses for 16-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrh[_u32base]_[u32]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrh_u32base_u32index(bases: svuint32_t, indices: svuint32_t) -> svuint32_t { + unsafe { svadrh_u32base_s32index(bases, indices.as_signed()) } +} +#[doc = "Compute vector addresses for 32-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrw[_u32base]_[u32]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrw_u32base_u32index(bases: svuint32_t, indices: svuint32_t) -> svuint32_t { + unsafe { svadrw_u32base_s32index(bases, indices.as_signed()) } +} +#[doc = "Compute vector addresses for 64-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrd[_u32base]_[u32]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrd_u32base_u32index(bases: svuint32_t, indices: svuint32_t) -> svuint32_t { + unsafe { svadrd_u32base_s32index(bases, indices.as_signed()) } +} +#[doc = "Compute vector addresses for 8-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrb[_u64base]_[s64]offset)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrb_u64base_s64offset(bases: svuint64_t, offsets: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrb.nxv2i64")] + fn _svadrb_u64base_s64offset(bases: svint64_t, offsets: svint64_t) -> svint64_t; + } + unsafe { _svadrb_u64base_s64offset(bases.as_signed(), offsets).as_unsigned() } +} +#[doc = "Compute vector addresses for 16-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrh[_u64base]_[s64]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrh_u64base_s64index(bases: svuint64_t, indices: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrh.nxv2i64")] + fn _svadrh_u64base_s64index(bases: svint64_t, indices: svint64_t) -> svint64_t; + } + unsafe { _svadrh_u64base_s64index(bases.as_signed(), indices).as_unsigned() } +} +#[doc = "Compute vector addresses for 32-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrw[_u64base]_[s64]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrw_u64base_s64index(bases: svuint64_t, indices: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrw.nxv2i64")] + fn _svadrw_u64base_s64index(bases: svint64_t, indices: svint64_t) -> svint64_t; + } + unsafe { _svadrw_u64base_s64index(bases.as_signed(), indices).as_unsigned() } +} +#[doc = "Compute vector addresses for 64-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrd[_u64base]_[s64]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrd_u64base_s64index(bases: svuint64_t, indices: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrd.nxv2i64")] + fn _svadrd_u64base_s64index(bases: svint64_t, indices: svint64_t) -> svint64_t; + } + unsafe { _svadrd_u64base_s64index(bases.as_signed(), indices).as_unsigned() } +} +#[doc = "Compute vector addresses for 8-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrb[_u64base]_[u64]offset)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrb_u64base_u64offset(bases: svuint64_t, offsets: svuint64_t) -> svuint64_t { + unsafe { svadrb_u64base_s64offset(bases, offsets.as_signed()) } +} +#[doc = "Compute vector addresses for 16-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrh[_u64base]_[u64]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrh_u64base_u64index(bases: svuint64_t, indices: svuint64_t) -> svuint64_t { + unsafe { svadrh_u64base_s64index(bases, indices.as_signed()) } +} +#[doc = "Compute vector addresses for 32-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrw[_u64base]_[u64]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrw_u64base_u64index(bases: svuint64_t, indices: svuint64_t) -> svuint64_t { + unsafe { svadrw_u64base_s64index(bases, indices.as_signed()) } +} +#[doc = "Compute vector addresses for 64-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrd[_u64base]_[u64]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrd_u64base_u64index(bases: svuint64_t, indices: svuint64_t) -> svuint64_t { + unsafe { svadrd_u64base_s64index(bases, indices.as_signed()) } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.and.z.nxv16i1")] + fn _svand_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svand_b_z(pg, op1, op2) } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.and.nxv16i8")] + fn _svand_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svand_s8_m(pg, op1, op2) } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svand_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svand_s8_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svand_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svand_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svand_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.and.nxv8i16")] + fn _svand_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svand_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svand_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svand_s16_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svand_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svand_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svand_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.and.nxv4i32")] + fn _svand_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svand_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svand_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svand_s32_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svand_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svand_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svand_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.and.nxv2i64")] + fn _svand_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svand_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svand_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svand_s64_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svand_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svand_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svand_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svand_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svand_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svand_u8_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svand_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svand_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svand_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svand_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svand_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svand_u16_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svand_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svand_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svand_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svand_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svand_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svand_u32_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svand_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svand_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svand_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svand_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svand_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svand_u64_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svand_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svand_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svand_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_s8(pg: svbool_t, op: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.andv.nxv16i8")] + fn _svandv_s8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svandv_s8(pg, op) } +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_s16(pg: svbool_t, op: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.andv.nxv8i16")] + fn _svandv_s16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svandv_s16(pg.sve_into(), op) } +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_s32(pg: svbool_t, op: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.andv.nxv4i32")] + fn _svandv_s32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svandv_s32(pg.sve_into(), op) } +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.andv.nxv2i64")] + fn _svandv_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svandv_s64(pg.sve_into(), op) } +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_u8(pg: svbool_t, op: svuint8_t) -> u8 { + unsafe { svandv_s8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_u16(pg: svbool_t, op: svuint16_t) -> u16 { + unsafe { svandv_s16(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_u32(pg: svbool_t, op: svuint32_t) -> u32 { + unsafe { svandv_s32(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe { svandv_s64(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asr.nxv16i8")] + fn _svasr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svasr_s8_m(pg, op1, op2.as_signed()) } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svasr_s8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + svasr_s8_m(pg, op1, op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svasr_s8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + svasr_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svasr_s8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asr.nxv8i16")] + fn _svasr_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svasr_s16_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svasr_s16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + svasr_s16_m(pg, op1, op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svasr_s16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + svasr_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svasr_s16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asr.nxv4i32")] + fn _svasr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svasr_s32_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svasr_s32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + svasr_s32_m(pg, op1, op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svasr_s32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + svasr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svasr_s32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s64_m(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asr.nxv2i64")] + fn _svasr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svasr_s64_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svasr_s64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s64_x(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + svasr_s64_m(pg, op1, op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svasr_s64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s64_z(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + svasr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svasr_s64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.asr.wide.nxv16i8" + )] + fn _svasr_wide_s8_m(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svint8_t; + } + unsafe { _svasr_wide_s8_m(pg, op1, op2.as_signed()) } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t { + svasr_wide_s8_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t { + svasr_wide_s8_m(pg, op1, op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t { + svasr_wide_s8_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t { + svasr_wide_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t { + svasr_wide_s8_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.asr.wide.nxv8i16" + )] + fn _svasr_wide_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svint16_t; + } + unsafe { _svasr_wide_s16_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t { + svasr_wide_s16_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t { + svasr_wide_s16_m(pg, op1, op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t { + svasr_wide_s16_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t { + svasr_wide_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t { + svasr_wide_s16_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.asr.wide.nxv4i32" + )] + fn _svasr_wide_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svasr_wide_s32_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t { + svasr_wide_s32_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t { + svasr_wide_s32_m(pg, op1, op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t { + svasr_wide_s32_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t { + svasr_wide_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t { + svasr_wide_s32_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s8_m(pg: svbool_t, op1: svint8_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asrd.nxv16i8")] + fn _svasrd_n_s8_m(pg: svbool_t, op1: svint8_t, imm2: i32) -> svint8_t; + } + unsafe { _svasrd_n_s8_m(pg, op1, IMM2) } +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s8_x(pg: svbool_t, op1: svint8_t) -> svint8_t { + svasrd_n_s8_m::(pg, op1) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s8_z(pg: svbool_t, op1: svint8_t) -> svint8_t { + svasrd_n_s8_m::(pg, svsel_s8(pg, op1, svdup_n_s8(0))) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s16_m(pg: svbool_t, op1: svint16_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asrd.nxv8i16")] + fn _svasrd_n_s16_m(pg: svbool8_t, op1: svint16_t, imm2: i32) -> svint16_t; + } + unsafe { _svasrd_n_s16_m(pg.sve_into(), op1, IMM2) } +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s16_x(pg: svbool_t, op1: svint16_t) -> svint16_t { + svasrd_n_s16_m::(pg, op1) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s16_z(pg: svbool_t, op1: svint16_t) -> svint16_t { + svasrd_n_s16_m::(pg, svsel_s16(pg, op1, svdup_n_s16(0))) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s32_m(pg: svbool_t, op1: svint32_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asrd.nxv4i32")] + fn _svasrd_n_s32_m(pg: svbool4_t, op1: svint32_t, imm2: i32) -> svint32_t; + } + unsafe { _svasrd_n_s32_m(pg.sve_into(), op1, IMM2) } +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s32_x(pg: svbool_t, op1: svint32_t) -> svint32_t { + svasrd_n_s32_m::(pg, op1) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s32_z(pg: svbool_t, op1: svint32_t) -> svint32_t { + svasrd_n_s32_m::(pg, svsel_s32(pg, op1, svdup_n_s32(0))) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s64_m(pg: svbool_t, op1: svint64_t) -> svint64_t { + static_assert_range!(IMM2, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asrd.nxv2i64")] + fn _svasrd_n_s64_m(pg: svbool2_t, op1: svint64_t, imm2: i32) -> svint64_t; + } + unsafe { _svasrd_n_s64_m(pg.sve_into(), op1, IMM2) } +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s64_x(pg: svbool_t, op1: svint64_t) -> svint64_t { + svasrd_n_s64_m::(pg, op1) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s64_z(pg: svbool_t, op1: svint64_t) -> svint64_t { + svasrd_n_s64_m::(pg, svsel_s64(pg, op1, svdup_n_s64(0))) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bic.z.nxv16i1")] + fn _svbic_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svbic_b_z(pg, op1, op2) } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bic.nxv16i8")] + fn _svbic_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svbic_s8_m(pg, op1, op2) } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svbic_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svbic_s8_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svbic_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svbic_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svbic_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bic.nxv8i16")] + fn _svbic_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svbic_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svbic_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svbic_s16_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svbic_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svbic_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svbic_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bic.nxv4i32")] + fn _svbic_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svbic_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svbic_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svbic_s32_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svbic_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svbic_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svbic_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bic.nxv2i64")] + fn _svbic_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svbic_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svbic_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svbic_s64_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svbic_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svbic_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svbic_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svbic_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svbic_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svbic_u8_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svbic_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svbic_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svbic_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svbic_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svbic_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svbic_u16_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svbic_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svbic_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svbic_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svbic_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svbic_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svbic_u32_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svbic_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svbic_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svbic_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svbic_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svbic_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svbic_u64_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svbic_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svbic_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svbic_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Break after first true condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrka[_b]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(brka))] +pub fn svbrka_b_m(inactive: svbool_t, pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.brka.nxv16i1")] + fn _svbrka_b_m(inactive: svbool_t, pg: svbool_t, op: svbool_t) -> svbool_t; + } + unsafe { _svbrka_b_m(inactive, pg, op) } +} +#[doc = "Break after first true condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrka[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(brka))] +pub fn svbrka_b_z(pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.brka.z.nxv16i1")] + fn _svbrka_b_z(pg: svbool_t, op: svbool_t) -> svbool_t; + } + unsafe { _svbrka_b_z(pg, op) } +} +#[doc = "Break before first true condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkb[_b]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(brkb))] +pub fn svbrkb_b_m(inactive: svbool_t, pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.brkb.nxv16i1")] + fn _svbrkb_b_m(inactive: svbool_t, pg: svbool_t, op: svbool_t) -> svbool_t; + } + unsafe { _svbrkb_b_m(inactive, pg, op) } +} +#[doc = "Break before first true condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkb[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(brkb))] +pub fn svbrkb_b_z(pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.brkb.z.nxv16i1")] + fn _svbrkb_b_z(pg: svbool_t, op: svbool_t) -> svbool_t; + } + unsafe { _svbrkb_b_z(pg, op) } +} +#[doc = "Propagate break to next partition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkn[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(brkn))] +pub fn svbrkn_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.brkn.z.nxv16i1")] + fn _svbrkn_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svbrkn_b_z(pg, op1, op2) } +} +#[doc = "Break after first true condition, propagating from previous partition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkpa[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(brkpa))] +pub fn svbrkpa_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.brkpa.z.nxv16i1" + )] + fn _svbrkpa_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svbrkpa_b_z(pg, op1, op2) } +} +#[doc = "Break before first true condition, propagating from previous partition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkpb[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(brkpb))] +pub fn svbrkpb_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.brkpb.z.nxv16i1" + )] + fn _svbrkpb_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svbrkpb_b_z(pg, op1, op2) } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))] +pub fn svcadd_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, +) -> svfloat32_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcadd.nxv4f32")] + fn _svcadd_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + imm_rotation: i32, + ) -> svfloat32_t; + } + unsafe { _svcadd_f32_m(pg.sve_into(), op1, op2, IMM_ROTATION) } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))] +pub fn svcadd_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, +) -> svfloat32_t { + svcadd_f32_m::(pg, op1, op2) +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))] +pub fn svcadd_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, +) -> svfloat32_t { + svcadd_f32_m::(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))] +pub fn svcadd_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, +) -> svfloat64_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcadd.nxv2f64")] + fn _svcadd_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + imm_rotation: i32, + ) -> svfloat64_t; + } + unsafe { _svcadd_f64_m(pg.sve_into(), op1, op2, IMM_ROTATION) } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))] +pub fn svcadd_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, +) -> svfloat64_t { + svcadd_f64_m::(pg, op1, op2) +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))] +pub fn svcadd_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, +) -> svfloat64_t { + svcadd_f64_m::(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_f32(pg: svbool_t, fallback: svfloat32_t, data: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv4f32")] + fn _svclasta_f32(pg: svbool4_t, fallback: svfloat32_t, data: svfloat32_t) -> svfloat32_t; + } + unsafe { _svclasta_f32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_f64(pg: svbool_t, fallback: svfloat64_t, data: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv2f64")] + fn _svclasta_f64(pg: svbool2_t, fallback: svfloat64_t, data: svfloat64_t) -> svfloat64_t; + } + unsafe { _svclasta_f64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_s8(pg: svbool_t, fallback: svint8_t, data: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv16i8")] + fn _svclasta_s8(pg: svbool_t, fallback: svint8_t, data: svint8_t) -> svint8_t; + } + unsafe { _svclasta_s8(pg, fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_s16(pg: svbool_t, fallback: svint16_t, data: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv8i16")] + fn _svclasta_s16(pg: svbool8_t, fallback: svint16_t, data: svint16_t) -> svint16_t; + } + unsafe { _svclasta_s16(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_s32(pg: svbool_t, fallback: svint32_t, data: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv4i32")] + fn _svclasta_s32(pg: svbool4_t, fallback: svint32_t, data: svint32_t) -> svint32_t; + } + unsafe { _svclasta_s32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_s64(pg: svbool_t, fallback: svint64_t, data: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv2i64")] + fn _svclasta_s64(pg: svbool2_t, fallback: svint64_t, data: svint64_t) -> svint64_t; + } + unsafe { _svclasta_s64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_u8(pg: svbool_t, fallback: svuint8_t, data: svuint8_t) -> svuint8_t { + unsafe { svclasta_s8(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_u16(pg: svbool_t, fallback: svuint16_t, data: svuint16_t) -> svuint16_t { + unsafe { svclasta_s16(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_u32(pg: svbool_t, fallback: svuint32_t, data: svuint32_t) -> svuint32_t { + unsafe { svclasta_s32(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_u64(pg: svbool_t, fallback: svuint64_t, data: svuint64_t) -> svuint64_t { + unsafe { svclasta_s64(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_f32(pg: svbool_t, fallback: f32, data: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clasta.n.nxv4f32" + )] + fn _svclasta_n_f32(pg: svbool4_t, fallback: f32, data: svfloat32_t) -> f32; + } + unsafe { _svclasta_n_f32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_f64(pg: svbool_t, fallback: f64, data: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clasta.n.nxv2f64" + )] + fn _svclasta_n_f64(pg: svbool2_t, fallback: f64, data: svfloat64_t) -> f64; + } + unsafe { _svclasta_n_f64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_s8(pg: svbool_t, fallback: i8, data: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clasta.n.nxv16i8" + )] + fn _svclasta_n_s8(pg: svbool_t, fallback: i8, data: svint8_t) -> i8; + } + unsafe { _svclasta_n_s8(pg, fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_s16(pg: svbool_t, fallback: i16, data: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clasta.n.nxv8i16" + )] + fn _svclasta_n_s16(pg: svbool8_t, fallback: i16, data: svint16_t) -> i16; + } + unsafe { _svclasta_n_s16(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_s32(pg: svbool_t, fallback: i32, data: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clasta.n.nxv4i32" + )] + fn _svclasta_n_s32(pg: svbool4_t, fallback: i32, data: svint32_t) -> i32; + } + unsafe { _svclasta_n_s32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_s64(pg: svbool_t, fallback: i64, data: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clasta.n.nxv2i64" + )] + fn _svclasta_n_s64(pg: svbool2_t, fallback: i64, data: svint64_t) -> i64; + } + unsafe { _svclasta_n_s64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_u8(pg: svbool_t, fallback: u8, data: svuint8_t) -> u8 { + unsafe { svclasta_n_s8(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_u16(pg: svbool_t, fallback: u16, data: svuint16_t) -> u16 { + unsafe { svclasta_n_s16(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_u32(pg: svbool_t, fallback: u32, data: svuint32_t) -> u32 { + unsafe { svclasta_n_s32(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_u64(pg: svbool_t, fallback: u64, data: svuint64_t) -> u64 { + unsafe { svclasta_n_s64(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_f32(pg: svbool_t, fallback: svfloat32_t, data: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv4f32")] + fn _svclastb_f32(pg: svbool4_t, fallback: svfloat32_t, data: svfloat32_t) -> svfloat32_t; + } + unsafe { _svclastb_f32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_f64(pg: svbool_t, fallback: svfloat64_t, data: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv2f64")] + fn _svclastb_f64(pg: svbool2_t, fallback: svfloat64_t, data: svfloat64_t) -> svfloat64_t; + } + unsafe { _svclastb_f64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_s8(pg: svbool_t, fallback: svint8_t, data: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv16i8")] + fn _svclastb_s8(pg: svbool_t, fallback: svint8_t, data: svint8_t) -> svint8_t; + } + unsafe { _svclastb_s8(pg, fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_s16(pg: svbool_t, fallback: svint16_t, data: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv8i16")] + fn _svclastb_s16(pg: svbool8_t, fallback: svint16_t, data: svint16_t) -> svint16_t; + } + unsafe { _svclastb_s16(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_s32(pg: svbool_t, fallback: svint32_t, data: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv4i32")] + fn _svclastb_s32(pg: svbool4_t, fallback: svint32_t, data: svint32_t) -> svint32_t; + } + unsafe { _svclastb_s32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_s64(pg: svbool_t, fallback: svint64_t, data: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv2i64")] + fn _svclastb_s64(pg: svbool2_t, fallback: svint64_t, data: svint64_t) -> svint64_t; + } + unsafe { _svclastb_s64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_u8(pg: svbool_t, fallback: svuint8_t, data: svuint8_t) -> svuint8_t { + unsafe { svclastb_s8(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_u16(pg: svbool_t, fallback: svuint16_t, data: svuint16_t) -> svuint16_t { + unsafe { svclastb_s16(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_u32(pg: svbool_t, fallback: svuint32_t, data: svuint32_t) -> svuint32_t { + unsafe { svclastb_s32(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_u64(pg: svbool_t, fallback: svuint64_t, data: svuint64_t) -> svuint64_t { + unsafe { svclastb_s64(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_f32(pg: svbool_t, fallback: f32, data: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clastb.n.nxv4f32" + )] + fn _svclastb_n_f32(pg: svbool4_t, fallback: f32, data: svfloat32_t) -> f32; + } + unsafe { _svclastb_n_f32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_f64(pg: svbool_t, fallback: f64, data: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clastb.n.nxv2f64" + )] + fn _svclastb_n_f64(pg: svbool2_t, fallback: f64, data: svfloat64_t) -> f64; + } + unsafe { _svclastb_n_f64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_s8(pg: svbool_t, fallback: i8, data: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clastb.n.nxv16i8" + )] + fn _svclastb_n_s8(pg: svbool_t, fallback: i8, data: svint8_t) -> i8; + } + unsafe { _svclastb_n_s8(pg, fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_s16(pg: svbool_t, fallback: i16, data: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clastb.n.nxv8i16" + )] + fn _svclastb_n_s16(pg: svbool8_t, fallback: i16, data: svint16_t) -> i16; + } + unsafe { _svclastb_n_s16(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_s32(pg: svbool_t, fallback: i32, data: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clastb.n.nxv4i32" + )] + fn _svclastb_n_s32(pg: svbool4_t, fallback: i32, data: svint32_t) -> i32; + } + unsafe { _svclastb_n_s32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_s64(pg: svbool_t, fallback: i64, data: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clastb.n.nxv2i64" + )] + fn _svclastb_n_s64(pg: svbool2_t, fallback: i64, data: svint64_t) -> i64; + } + unsafe { _svclastb_n_s64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_u8(pg: svbool_t, fallback: u8, data: svuint8_t) -> u8 { + unsafe { svclastb_n_s8(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_u16(pg: svbool_t, fallback: u16, data: svuint16_t) -> u16 { + unsafe { svclastb_n_s16(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_u32(pg: svbool_t, fallback: u32, data: svuint32_t) -> u32 { + unsafe { svclastb_n_s32(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_u64(pg: svbool_t, fallback: u64, data: svuint64_t) -> u64 { + unsafe { svclastb_n_s64(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s8_m(inactive: svuint8_t, pg: svbool_t, op: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cls.nxv16i8")] + fn _svcls_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svcls_s8_m(inactive.as_signed(), pg, op).as_unsigned() } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s8_x(pg: svbool_t, op: svint8_t) -> svuint8_t { + unsafe { svcls_s8_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s8_z(pg: svbool_t, op: svint8_t) -> svuint8_t { + svcls_s8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s16_m(inactive: svuint16_t, pg: svbool_t, op: svint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cls.nxv8i16")] + fn _svcls_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svcls_s16_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s16_x(pg: svbool_t, op: svint16_t) -> svuint16_t { + unsafe { svcls_s16_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s16_z(pg: svbool_t, op: svint16_t) -> svuint16_t { + svcls_s16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s32_m(inactive: svuint32_t, pg: svbool_t, op: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cls.nxv4i32")] + fn _svcls_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svcls_s32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s32_x(pg: svbool_t, op: svint32_t) -> svuint32_t { + unsafe { svcls_s32_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s32_z(pg: svbool_t, op: svint32_t) -> svuint32_t { + svcls_s32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s64_m(inactive: svuint64_t, pg: svbool_t, op: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cls.nxv2i64")] + fn _svcls_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svcls_s64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s64_x(pg: svbool_t, op: svint64_t) -> svuint64_t { + unsafe { svcls_s64_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s64_z(pg: svbool_t, op: svint64_t) -> svuint64_t { + svcls_s64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s8_m(inactive: svuint8_t, pg: svbool_t, op: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clz.nxv16i8")] + fn _svclz_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svclz_s8_m(inactive.as_signed(), pg, op).as_unsigned() } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s8_x(pg: svbool_t, op: svint8_t) -> svuint8_t { + unsafe { svclz_s8_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s8_z(pg: svbool_t, op: svint8_t) -> svuint8_t { + svclz_s8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s16_m(inactive: svuint16_t, pg: svbool_t, op: svint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clz.nxv8i16")] + fn _svclz_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svclz_s16_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s16_x(pg: svbool_t, op: svint16_t) -> svuint16_t { + unsafe { svclz_s16_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s16_z(pg: svbool_t, op: svint16_t) -> svuint16_t { + svclz_s16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s32_m(inactive: svuint32_t, pg: svbool_t, op: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clz.nxv4i32")] + fn _svclz_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svclz_s32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s32_x(pg: svbool_t, op: svint32_t) -> svuint32_t { + unsafe { svclz_s32_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s32_z(pg: svbool_t, op: svint32_t) -> svuint32_t { + svclz_s32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s64_m(inactive: svuint64_t, pg: svbool_t, op: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clz.nxv2i64")] + fn _svclz_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svclz_s64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s64_x(pg: svbool_t, op: svint64_t) -> svuint64_t { + unsafe { svclz_s64_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s64_z(pg: svbool_t, op: svint64_t) -> svuint64_t { + svclz_s64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_t { + unsafe { svclz_s8_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svclz_u8_m(op, pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svclz_u8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t { + unsafe { svclz_s16_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svclz_u16_m(op, pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svclz_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svclz_s32_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svclz_u32_m(op, pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svclz_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svclz_s64_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svclz_u64_m(op, pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svclz_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))] +pub fn svcmla_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmla.nxv4f32")] + fn _svcmla_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + imm_rotation: i32, + ) -> svfloat32_t; + } + unsafe { _svcmla_f32_m(pg.sve_into(), op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))] +pub fn svcmla_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svcmla_f32_m::(pg, op1, op2, op3) +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))] +pub fn svcmla_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svcmla_f32_m::(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))] +pub fn svcmla_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmla.nxv2f64")] + fn _svcmla_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + imm_rotation: i32, + ) -> svfloat64_t; + } + unsafe { _svcmla_f64_m(pg.sve_into(), op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))] +pub fn svcmla_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svcmla_f64_m::(pg, op1, op2, op3) +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))] +pub fn svcmla_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svcmla_f64_m::(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmla, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svcmla_lane_f32( + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + static_assert_range!(IMM_INDEX, 0..=1); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fcmla.lane.nxv4f32" + )] + fn _svcmla_lane_f32( + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + imm_index: i32, + imm_rotation: i32, + ) -> svfloat32_t; + } + unsafe { _svcmla_lane_f32(op1, op2, op3, IMM_INDEX, IMM_ROTATION) } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmeq))] +pub fn svcmpeq_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpeq.nxv4f32")] + fn _svcmpeq_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t; + } + unsafe { _svcmpeq_f32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmeq))] +pub fn svcmpeq_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svcmpeq_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmeq))] +pub fn svcmpeq_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpeq.nxv2f64")] + fn _svcmpeq_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t; + } + unsafe { _svcmpeq_f64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmeq))] +pub fn svcmpeq_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svcmpeq_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpeq.nxv16i8")] + fn _svcmpeq_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svcmpeq_s8(pg, op1, op2) } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t { + svcmpeq_s8(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpeq.nxv8i16")] + fn _svcmpeq_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svcmpeq_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t { + svcmpeq_s16(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpeq.nxv4i32")] + fn _svcmpeq_s32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t; + } + unsafe { _svcmpeq_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t { + svcmpeq_s32(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpeq.nxv2i64")] + fn _svcmpeq_s64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t; + } + unsafe { _svcmpeq_s64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t { + svcmpeq_s64(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + unsafe { svcmpeq_s8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t { + svcmpeq_u8(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + unsafe { svcmpeq_s16(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t { + svcmpeq_u16(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t { + unsafe { svcmpeq_s32(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t { + svcmpeq_u32(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t { + unsafe { svcmpeq_s64(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t { + svcmpeq_u64(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpeq.wide.nxv16i8" + )] + fn _svcmpeq_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmpeq_wide_s8(pg, op1, op2) } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t { + svcmpeq_wide_s8(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpeq.wide.nxv8i16" + )] + fn _svcmpeq_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmpeq_wide_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t { + svcmpeq_wide_s16(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpeq.wide.nxv4i32" + )] + fn _svcmpeq_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmpeq_wide_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t { + svcmpeq_wide_s32(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmpge_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpge.nxv4f32")] + fn _svcmpge_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t; + } + unsafe { _svcmpge_f32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmpge_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svcmpge_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmpge_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpge.nxv2f64")] + fn _svcmpge_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t; + } + unsafe { _svcmpge_f64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmpge_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svcmpge_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpge.nxv16i8")] + fn _svcmpge_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svcmpge_s8(pg, op1, op2) } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t { + svcmpge_s8(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpge.nxv8i16")] + fn _svcmpge_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svcmpge_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t { + svcmpge_s16(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpge.nxv4i32")] + fn _svcmpge_s32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t; + } + unsafe { _svcmpge_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t { + svcmpge_s32(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpge.nxv2i64")] + fn _svcmpge_s64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t; + } + unsafe { _svcmpge_s64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t { + svcmpge_s64(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphs.nxv16i8")] + fn _svcmpge_u8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svcmpge_u8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t { + svcmpge_u8(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphs.nxv8i16")] + fn _svcmpge_u16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svcmpge_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t { + svcmpge_u16(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphs.nxv4i32")] + fn _svcmpge_u32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t; + } + unsafe { _svcmpge_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t { + svcmpge_u32(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphs.nxv2i64")] + fn _svcmpge_u64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t; + } + unsafe { _svcmpge_u64(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t { + svcmpge_u64(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpge.wide.nxv16i8" + )] + fn _svcmpge_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmpge_wide_s8(pg, op1, op2) } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t { + svcmpge_wide_s8(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpge.wide.nxv8i16" + )] + fn _svcmpge_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmpge_wide_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t { + svcmpge_wide_s16(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpge.wide.nxv4i32" + )] + fn _svcmpge_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmpge_wide_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t { + svcmpge_wide_s32(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_wide_u8(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmphs.wide.nxv16i8" + )] + fn _svcmpge_wide_u8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmpge_wide_u8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_wide_n_u8(pg: svbool_t, op1: svuint8_t, op2: u64) -> svbool_t { + svcmpge_wide_u8(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_wide_u16(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmphs.wide.nxv8i16" + )] + fn _svcmpge_wide_u16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmpge_wide_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_wide_n_u16(pg: svbool_t, op1: svuint16_t, op2: u64) -> svbool_t { + svcmpge_wide_u16(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_wide_u32(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmphs.wide.nxv4i32" + )] + fn _svcmpge_wide_u32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmpge_wide_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_wide_n_u32(pg: svbool_t, op1: svuint32_t, op2: u64) -> svbool_t { + svcmpge_wide_u32(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmpgt_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpgt.nxv4f32")] + fn _svcmpgt_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t; + } + unsafe { _svcmpgt_f32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmpgt_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svcmpgt_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmpgt_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpgt.nxv2f64")] + fn _svcmpgt_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t; + } + unsafe { _svcmpgt_f64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmpgt_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svcmpgt_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpgt.nxv16i8")] + fn _svcmpgt_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svcmpgt_s8(pg, op1, op2) } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t { + svcmpgt_s8(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpgt.nxv8i16")] + fn _svcmpgt_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svcmpgt_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t { + svcmpgt_s16(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpgt.nxv4i32")] + fn _svcmpgt_s32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t; + } + unsafe { _svcmpgt_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t { + svcmpgt_s32(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpgt.nxv2i64")] + fn _svcmpgt_s64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t; + } + unsafe { _svcmpgt_s64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t { + svcmpgt_s64(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphi.nxv16i8")] + fn _svcmpgt_u8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svcmpgt_u8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t { + svcmpgt_u8(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphi.nxv8i16")] + fn _svcmpgt_u16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svcmpgt_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t { + svcmpgt_u16(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphi.nxv4i32")] + fn _svcmpgt_u32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t; + } + unsafe { _svcmpgt_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t { + svcmpgt_u32(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphi.nxv2i64")] + fn _svcmpgt_u64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t; + } + unsafe { _svcmpgt_u64(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t { + svcmpgt_u64(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpgt.wide.nxv16i8" + )] + fn _svcmpgt_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmpgt_wide_s8(pg, op1, op2) } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t { + svcmpgt_wide_s8(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpgt.wide.nxv8i16" + )] + fn _svcmpgt_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmpgt_wide_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t { + svcmpgt_wide_s16(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpgt.wide.nxv4i32" + )] + fn _svcmpgt_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmpgt_wide_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t { + svcmpgt_wide_s32(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_wide_u8(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmphi.wide.nxv16i8" + )] + fn _svcmpgt_wide_u8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmpgt_wide_u8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_wide_n_u8(pg: svbool_t, op1: svuint8_t, op2: u64) -> svbool_t { + svcmpgt_wide_u8(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_wide_u16(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmphi.wide.nxv8i16" + )] + fn _svcmpgt_wide_u16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmpgt_wide_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_wide_n_u16(pg: svbool_t, op1: svuint16_t, op2: u64) -> svbool_t { + svcmpgt_wide_u16(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_wide_u32(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmphi.wide.nxv4i32" + )] + fn _svcmpgt_wide_u32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmpgt_wide_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_wide_n_u32(pg: svbool_t, op1: svuint32_t, op2: u64) -> svbool_t { + svcmpgt_wide_u32(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmple_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + svcmpge_f32(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmple_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svcmple_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmple_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + svcmpge_f64(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmple_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svcmple_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + svcmpge_s8(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t { + svcmple_s8(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + svcmpge_s16(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t { + svcmple_s16(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t { + svcmpge_s32(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t { + svcmple_s32(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t { + svcmpge_s64(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t { + svcmple_s64(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + svcmpge_u8(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t { + svcmple_u8(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + svcmpge_u16(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t { + svcmple_u16(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t { + svcmpge_u32(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t { + svcmple_u32(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t { + svcmpge_u64(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t { + svcmple_u64(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmple))] +pub fn svcmple_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmple.wide.nxv16i8" + )] + fn _svcmple_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmple_wide_s8(pg, op1, op2) } +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmple))] +pub fn svcmple_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t { + svcmple_wide_s8(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmple))] +pub fn svcmple_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmple.wide.nxv8i16" + )] + fn _svcmple_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmple_wide_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmple))] +pub fn svcmple_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t { + svcmple_wide_s16(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmple))] +pub fn svcmple_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmple.wide.nxv4i32" + )] + fn _svcmple_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmple_wide_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmple))] +pub fn svcmple_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t { + svcmple_wide_s32(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpls))] +pub fn svcmple_wide_u8(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpls.wide.nxv16i8" + )] + fn _svcmple_wide_u8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmple_wide_u8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpls))] +pub fn svcmple_wide_n_u8(pg: svbool_t, op1: svuint8_t, op2: u64) -> svbool_t { + svcmple_wide_u8(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpls))] +pub fn svcmple_wide_u16(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpls.wide.nxv8i16" + )] + fn _svcmple_wide_u16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmple_wide_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpls))] +pub fn svcmple_wide_n_u16(pg: svbool_t, op1: svuint16_t, op2: u64) -> svbool_t { + svcmple_wide_u16(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpls))] +pub fn svcmple_wide_u32(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpls.wide.nxv4i32" + )] + fn _svcmple_wide_u32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmple_wide_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpls))] +pub fn svcmple_wide_n_u32(pg: svbool_t, op1: svuint32_t, op2: u64) -> svbool_t { + svcmple_wide_u32(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmplt_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + svcmpgt_f32(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmplt_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svcmplt_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmplt_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + svcmpgt_f64(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmplt_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svcmplt_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + svcmpgt_s8(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t { + svcmplt_s8(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + svcmpgt_s16(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t { + svcmplt_s16(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t { + svcmpgt_s32(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t { + svcmplt_s32(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t { + svcmpgt_s64(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t { + svcmplt_s64(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + svcmpgt_u8(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t { + svcmplt_u8(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + svcmpgt_u16(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t { + svcmplt_u16(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t { + svcmpgt_u32(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t { + svcmplt_u32(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t { + svcmpgt_u64(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t { + svcmplt_u64(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplt))] +pub fn svcmplt_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmplt.wide.nxv16i8" + )] + fn _svcmplt_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmplt_wide_s8(pg, op1, op2) } +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplt))] +pub fn svcmplt_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t { + svcmplt_wide_s8(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplt))] +pub fn svcmplt_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmplt.wide.nxv8i16" + )] + fn _svcmplt_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmplt_wide_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplt))] +pub fn svcmplt_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t { + svcmplt_wide_s16(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplt))] +pub fn svcmplt_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmplt.wide.nxv4i32" + )] + fn _svcmplt_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmplt_wide_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplt))] +pub fn svcmplt_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t { + svcmplt_wide_s32(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplo))] +pub fn svcmplt_wide_u8(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmplo.wide.nxv16i8" + )] + fn _svcmplt_wide_u8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmplt_wide_u8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplo))] +pub fn svcmplt_wide_n_u8(pg: svbool_t, op1: svuint8_t, op2: u64) -> svbool_t { + svcmplt_wide_u8(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplo))] +pub fn svcmplt_wide_u16(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmplo.wide.nxv8i16" + )] + fn _svcmplt_wide_u16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmplt_wide_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplo))] +pub fn svcmplt_wide_n_u16(pg: svbool_t, op1: svuint16_t, op2: u64) -> svbool_t { + svcmplt_wide_u16(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplo))] +pub fn svcmplt_wide_u32(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmplo.wide.nxv4i32" + )] + fn _svcmplt_wide_u32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmplt_wide_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplo))] +pub fn svcmplt_wide_n_u32(pg: svbool_t, op1: svuint32_t, op2: u64) -> svbool_t { + svcmplt_wide_u32(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmne))] +pub fn svcmpne_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpne.nxv4f32")] + fn _svcmpne_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t; + } + unsafe { _svcmpne_f32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmne))] +pub fn svcmpne_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svcmpne_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmne))] +pub fn svcmpne_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpne.nxv2f64")] + fn _svcmpne_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t; + } + unsafe { _svcmpne_f64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmne))] +pub fn svcmpne_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svcmpne_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpne.nxv16i8")] + fn _svcmpne_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svcmpne_s8(pg, op1, op2) } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t { + svcmpne_s8(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpne.nxv8i16")] + fn _svcmpne_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svcmpne_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t { + svcmpne_s16(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpne.nxv4i32")] + fn _svcmpne_s32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t; + } + unsafe { _svcmpne_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t { + svcmpne_s32(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpne.nxv2i64")] + fn _svcmpne_s64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t; + } + unsafe { _svcmpne_s64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t { + svcmpne_s64(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + unsafe { svcmpne_s8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t { + svcmpne_u8(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + unsafe { svcmpne_s16(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t { + svcmpne_u16(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t { + unsafe { svcmpne_s32(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t { + svcmpne_u32(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t { + unsafe { svcmpne_s64(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t { + svcmpne_u64(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpne.wide.nxv16i8" + )] + fn _svcmpne_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmpne_wide_s8(pg, op1, op2) } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t { + svcmpne_wide_s8(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpne.wide.nxv8i16" + )] + fn _svcmpne_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmpne_wide_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t { + svcmpne_wide_s16(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpne.wide.nxv4i32" + )] + fn _svcmpne_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmpne_wide_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t { + svcmpne_wide_s32(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare unordered with"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpuo[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmuo))] +pub fn svcmpuo_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpuo.nxv4f32")] + fn _svcmpuo_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t; + } + unsafe { _svcmpuo_f32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare unordered with"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpuo[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmuo))] +pub fn svcmpuo_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svcmpuo_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Compare unordered with"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpuo[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmuo))] +pub fn svcmpuo_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpuo.nxv2f64")] + fn _svcmpuo_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t; + } + unsafe { _svcmpuo_f64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare unordered with"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpuo[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmuo))] +pub fn svcmpuo_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svcmpuo_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnot.nxv16i8")] + fn _svcnot_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svcnot_s8_m(inactive, pg, op) } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t { + svcnot_s8_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t { + svcnot_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnot.nxv8i16")] + fn _svcnot_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svcnot_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svcnot_s16_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svcnot_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnot.nxv4i32")] + fn _svcnot_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svcnot_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svcnot_s32_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svcnot_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnot.nxv2i64")] + fn _svcnot_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svcnot_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svcnot_s64_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svcnot_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_t { + unsafe { svcnot_s8_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svcnot_u8_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svcnot_u8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t { + unsafe { svcnot_s16_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svcnot_u16_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svcnot_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svcnot_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svcnot_u32_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svcnot_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svcnot_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svcnot_u64_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svcnot_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_f32_m(inactive: svuint32_t, pg: svbool_t, op: svfloat32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv4f32")] + fn _svcnt_f32_m(inactive: svint32_t, pg: svbool4_t, op: svfloat32_t) -> svint32_t; + } + unsafe { _svcnt_f32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_f32_x(pg: svbool_t, op: svfloat32_t) -> svuint32_t { + unsafe { svcnt_f32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_f32_z(pg: svbool_t, op: svfloat32_t) -> svuint32_t { + svcnt_f32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_f64_m(inactive: svuint64_t, pg: svbool_t, op: svfloat64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv2f64")] + fn _svcnt_f64_m(inactive: svint64_t, pg: svbool2_t, op: svfloat64_t) -> svint64_t; + } + unsafe { _svcnt_f64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_f64_x(pg: svbool_t, op: svfloat64_t) -> svuint64_t { + unsafe { svcnt_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_f64_z(pg: svbool_t, op: svfloat64_t) -> svuint64_t { + svcnt_f64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s8_m(inactive: svuint8_t, pg: svbool_t, op: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv16i8")] + fn _svcnt_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svcnt_s8_m(inactive.as_signed(), pg, op).as_unsigned() } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s8_x(pg: svbool_t, op: svint8_t) -> svuint8_t { + unsafe { svcnt_s8_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s8_z(pg: svbool_t, op: svint8_t) -> svuint8_t { + svcnt_s8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s16_m(inactive: svuint16_t, pg: svbool_t, op: svint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv8i16")] + fn _svcnt_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svcnt_s16_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s16_x(pg: svbool_t, op: svint16_t) -> svuint16_t { + unsafe { svcnt_s16_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s16_z(pg: svbool_t, op: svint16_t) -> svuint16_t { + svcnt_s16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s32_m(inactive: svuint32_t, pg: svbool_t, op: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv4i32")] + fn _svcnt_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svcnt_s32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s32_x(pg: svbool_t, op: svint32_t) -> svuint32_t { + unsafe { svcnt_s32_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s32_z(pg: svbool_t, op: svint32_t) -> svuint32_t { + svcnt_s32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s64_m(inactive: svuint64_t, pg: svbool_t, op: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv2i64")] + fn _svcnt_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svcnt_s64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s64_x(pg: svbool_t, op: svint64_t) -> svuint64_t { + unsafe { svcnt_s64_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s64_z(pg: svbool_t, op: svint64_t) -> svuint64_t { + svcnt_s64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_t { + unsafe { svcnt_s8_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svcnt_u8_m(op, pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svcnt_u8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t { + unsafe { svcnt_s16_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svcnt_u16_m(op, pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svcnt_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svcnt_s32_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svcnt_u32_m(op, pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svcnt_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svcnt_s64_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svcnt_u64_m(op, pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svcnt_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Count the number of 8-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntb)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rdvl))] +pub fn svcntb() -> u64 { + svcntb_pat::<{ svpattern::SV_ALL }>() +} +#[doc = "Count the number of 16-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnth)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnth))] +pub fn svcnth() -> u64 { + svcnth_pat::<{ svpattern::SV_ALL }>() +} +#[doc = "Count the number of 32-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntw)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntw))] +pub fn svcntw() -> u64 { + svcntw_pat::<{ svpattern::SV_ALL }>() +} +#[doc = "Count the number of 64-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntd)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntd))] +pub fn svcntd() -> u64 { + svcntd_pat::<{ svpattern::SV_ALL }>() +} +#[doc = "Count the number of 8-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntb_pat)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (rdvl , PATTERN = { svpattern :: SV_ALL }))] +# [cfg_attr (test , assert_instr (cntb , PATTERN = { svpattern :: SV_MUL4 }))] +pub fn svcntb_pat() -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntb")] + fn _svcntb_pat(pattern: svpattern) -> i64; + } + unsafe { _svcntb_pat(PATTERN).as_unsigned() } +} +#[doc = "Count the number of 16-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnth_pat)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (cnth , PATTERN = { svpattern :: SV_ALL }))] +pub fn svcnth_pat() -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnth")] + fn _svcnth_pat(pattern: svpattern) -> i64; + } + unsafe { _svcnth_pat(PATTERN).as_unsigned() } +} +#[doc = "Count the number of 32-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntw_pat)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (cntw , PATTERN = { svpattern :: SV_ALL }))] +pub fn svcntw_pat() -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntw")] + fn _svcntw_pat(pattern: svpattern) -> i64; + } + unsafe { _svcntw_pat(PATTERN).as_unsigned() } +} +#[doc = "Count the number of 64-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntd_pat)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (cntd , PATTERN = { svpattern :: SV_ALL }))] +pub fn svcntd_pat() -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntd")] + fn _svcntd_pat(pattern: svpattern) -> i64; + } + unsafe { _svcntd_pat(PATTERN).as_unsigned() } +} +#[doc = "Count set predicate bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntp_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntp))] +pub fn svcntp_b8(pg: svbool_t, op: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntp.nxv16i1")] + fn _svcntp_b8(pg: svbool_t, op: svbool_t) -> i64; + } + unsafe { _svcntp_b8(pg, op).as_unsigned() } +} +#[doc = "Count set predicate bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntp_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntp))] +pub fn svcntp_b16(pg: svbool_t, op: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntp.nxv8i1")] + fn _svcntp_b16(pg: svbool8_t, op: svbool8_t) -> i64; + } + unsafe { _svcntp_b16(pg.sve_into(), op.sve_into()).as_unsigned() } +} +#[doc = "Count set predicate bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntp_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntp))] +pub fn svcntp_b32(pg: svbool_t, op: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntp.nxv4i1")] + fn _svcntp_b32(pg: svbool4_t, op: svbool4_t) -> i64; + } + unsafe { _svcntp_b32(pg.sve_into(), op.sve_into()).as_unsigned() } +} +#[doc = "Count set predicate bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntp_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntp))] +pub fn svcntp_b64(pg: svbool_t, op: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntp.nxv2i1")] + fn _svcntp_b64(pg: svbool2_t, op: svbool2_t) -> i64; + } + unsafe { _svcntp_b64(pg.sve_into(), op.sve_into()).as_unsigned() } +} +#[doc = "Shuffle active elements of vector to the right and fill with zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(compact))] +pub fn svcompact_f32(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.compact.nxv4f32" + )] + fn _svcompact_f32(pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svcompact_f32(pg.sve_into(), op) } +} +#[doc = "Shuffle active elements of vector to the right and fill with zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(compact))] +pub fn svcompact_f64(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.compact.nxv2f64" + )] + fn _svcompact_f64(pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svcompact_f64(pg.sve_into(), op) } +} +#[doc = "Shuffle active elements of vector to the right and fill with zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(compact))] +pub fn svcompact_s32(pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.compact.nxv4i32" + )] + fn _svcompact_s32(pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svcompact_s32(pg.sve_into(), op) } +} +#[doc = "Shuffle active elements of vector to the right and fill with zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(compact))] +pub fn svcompact_s64(pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.compact.nxv2i64" + )] + fn _svcompact_s64(pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svcompact_s64(pg.sve_into(), op) } +} +#[doc = "Shuffle active elements of vector to the right and fill with zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(compact))] +pub fn svcompact_u32(pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svcompact_s32(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Shuffle active elements of vector to the right and fill with zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(compact))] +pub fn svcompact_u64(pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svcompact_s64(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_f32(x0: svfloat32_t, x1: svfloat32_t) -> svfloat32x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_f64(x0: svfloat64_t, x1: svfloat64_t) -> svfloat64x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_s8(x0: svint8_t, x1: svint8_t) -> svint8x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_s16(x0: svint16_t, x1: svint16_t) -> svint16x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_s32(x0: svint32_t, x1: svint32_t) -> svint32x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_s64(x0: svint64_t, x1: svint64_t) -> svint64x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_u8(x0: svuint8_t, x1: svuint8_t) -> svuint8x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_u16(x0: svuint16_t, x1: svuint16_t) -> svuint16x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_u32(x0: svuint32_t, x1: svuint32_t) -> svuint32x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_u64(x0: svuint64_t, x1: svuint64_t) -> svuint64x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_f32(x0: svfloat32_t, x1: svfloat32_t, x2: svfloat32_t) -> svfloat32x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_f64(x0: svfloat64_t, x1: svfloat64_t, x2: svfloat64_t) -> svfloat64x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_s8(x0: svint8_t, x1: svint8_t, x2: svint8_t) -> svint8x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_s16(x0: svint16_t, x1: svint16_t, x2: svint16_t) -> svint16x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_s32(x0: svint32_t, x1: svint32_t, x2: svint32_t) -> svint32x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_s64(x0: svint64_t, x1: svint64_t, x2: svint64_t) -> svint64x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_u8(x0: svuint8_t, x1: svuint8_t, x2: svuint8_t) -> svuint8x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_u16(x0: svuint16_t, x1: svuint16_t, x2: svuint16_t) -> svuint16x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_u32(x0: svuint32_t, x1: svuint32_t, x2: svuint32_t) -> svuint32x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_u64(x0: svuint64_t, x1: svuint64_t, x2: svuint64_t) -> svuint64x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_f32( + x0: svfloat32_t, + x1: svfloat32_t, + x2: svfloat32_t, + x3: svfloat32_t, +) -> svfloat32x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_f64( + x0: svfloat64_t, + x1: svfloat64_t, + x2: svfloat64_t, + x3: svfloat64_t, +) -> svfloat64x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_s8(x0: svint8_t, x1: svint8_t, x2: svint8_t, x3: svint8_t) -> svint8x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_s16(x0: svint16_t, x1: svint16_t, x2: svint16_t, x3: svint16_t) -> svint16x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_s32(x0: svint32_t, x1: svint32_t, x2: svint32_t, x3: svint32_t) -> svint32x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_s64(x0: svint64_t, x1: svint64_t, x2: svint64_t, x3: svint64_t) -> svint64x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_u8(x0: svuint8_t, x1: svuint8_t, x2: svuint8_t, x3: svuint8_t) -> svuint8x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_u16( + x0: svuint16_t, + x1: svuint16_t, + x2: svuint16_t, + x3: svuint16_t, +) -> svuint16x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_u32( + x0: svuint32_t, + x1: svuint32_t, + x2: svuint32_t, + x3: svuint32_t, +) -> svuint32x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_u64( + x0: svuint64_t, + x1: svuint64_t, + x2: svuint64_t, + x3: svuint64_t, +) -> svuint64x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvt))] +pub fn svcvt_f32_f64_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvt.f32f64")] + fn _svcvt_f32_f64_m(inactive: svfloat32_t, pg: svbool2_t, op: svfloat64_t) -> svfloat32_t; + } + unsafe { _svcvt_f32_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvt))] +pub fn svcvt_f32_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + unsafe { svcvt_f32_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvt))] +pub fn svcvt_f32_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + svcvt_f32_f64_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvt))] +pub fn svcvt_f64_f32_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat32_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvt.f64f32")] + fn _svcvt_f64_f32_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat32_t) -> svfloat64_t; + } + unsafe { _svcvt_f64_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvt))] +pub fn svcvt_f64_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat64_t { + unsafe { svcvt_f64_f32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvt))] +pub fn svcvt_f64_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat64_t { + svcvt_f64_f32_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f32_s32_m(inactive: svfloat32_t, pg: svbool_t, op: svint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.scvtf.nxv4f32.nxv4i32" + )] + fn _svcvt_f32_s32_m(inactive: svfloat32_t, pg: svbool4_t, op: svint32_t) -> svfloat32_t; + } + unsafe { _svcvt_f32_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f32_s32_x(pg: svbool_t, op: svint32_t) -> svfloat32_t { + unsafe { svcvt_f32_s32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f32_s32_z(pg: svbool_t, op: svint32_t) -> svfloat32_t { + svcvt_f32_s32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f32_u32_m(inactive: svfloat32_t, pg: svbool_t, op: svuint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ucvtf.nxv4f32.nxv4i32" + )] + fn _svcvt_f32_u32_m(inactive: svfloat32_t, pg: svbool4_t, op: svint32_t) -> svfloat32_t; + } + unsafe { _svcvt_f32_u32_m(inactive, pg.sve_into(), op.as_signed()) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f32_u32_x(pg: svbool_t, op: svuint32_t) -> svfloat32_t { + unsafe { svcvt_f32_u32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f32_u32_z(pg: svbool_t, op: svuint32_t) -> svfloat32_t { + svcvt_f32_u32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f64_s64_m(inactive: svfloat64_t, pg: svbool_t, op: svint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.scvtf.nxv2f64.nxv2i64" + )] + fn _svcvt_f64_s64_m(inactive: svfloat64_t, pg: svbool2_t, op: svint64_t) -> svfloat64_t; + } + unsafe { _svcvt_f64_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f64_s64_x(pg: svbool_t, op: svint64_t) -> svfloat64_t { + unsafe { svcvt_f64_s64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f64_s64_z(pg: svbool_t, op: svint64_t) -> svfloat64_t { + svcvt_f64_s64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f64_u64_m(inactive: svfloat64_t, pg: svbool_t, op: svuint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ucvtf.nxv2f64.nxv2i64" + )] + fn _svcvt_f64_u64_m(inactive: svfloat64_t, pg: svbool2_t, op: svint64_t) -> svfloat64_t; + } + unsafe { _svcvt_f64_u64_m(inactive, pg.sve_into(), op.as_signed()) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f64_u64_x(pg: svbool_t, op: svuint64_t) -> svfloat64_t { + unsafe { svcvt_f64_u64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f64_u64_z(pg: svbool_t, op: svuint64_t) -> svfloat64_t { + svcvt_f64_u64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f32_s64_m(inactive: svfloat32_t, pg: svbool_t, op: svint64_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.scvtf.f32i64")] + fn _svcvt_f32_s64_m(inactive: svfloat32_t, pg: svbool2_t, op: svint64_t) -> svfloat32_t; + } + unsafe { _svcvt_f32_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f32_s64_x(pg: svbool_t, op: svint64_t) -> svfloat32_t { + unsafe { svcvt_f32_s64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f32_s64_z(pg: svbool_t, op: svint64_t) -> svfloat32_t { + svcvt_f32_s64_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f32_u64_m(inactive: svfloat32_t, pg: svbool_t, op: svuint64_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ucvtf.f32i64")] + fn _svcvt_f32_u64_m(inactive: svfloat32_t, pg: svbool2_t, op: svint64_t) -> svfloat32_t; + } + unsafe { _svcvt_f32_u64_m(inactive, pg.sve_into(), op.as_signed()) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f32_u64_x(pg: svbool_t, op: svuint64_t) -> svfloat32_t { + unsafe { svcvt_f32_u64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f32_u64_z(pg: svbool_t, op: svuint64_t) -> svfloat32_t { + svcvt_f32_u64_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f64_s32_m(inactive: svfloat64_t, pg: svbool_t, op: svint32_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.scvtf.f64i32")] + fn _svcvt_f64_s32_m(inactive: svfloat64_t, pg: svbool2_t, op: svint32_t) -> svfloat64_t; + } + unsafe { _svcvt_f64_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f64_s32_x(pg: svbool_t, op: svint32_t) -> svfloat64_t { + unsafe { svcvt_f64_s32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f64_s32_z(pg: svbool_t, op: svint32_t) -> svfloat64_t { + svcvt_f64_s32_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f64_u32_m(inactive: svfloat64_t, pg: svbool_t, op: svuint32_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ucvtf.f64i32")] + fn _svcvt_f64_u32_m(inactive: svfloat64_t, pg: svbool2_t, op: svint32_t) -> svfloat64_t; + } + unsafe { _svcvt_f64_u32_m(inactive, pg.sve_into(), op.as_signed()) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f64_u32_x(pg: svbool_t, op: svuint32_t) -> svfloat64_t { + unsafe { svcvt_f64_u32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f64_u32_z(pg: svbool_t, op: svuint32_t) -> svfloat64_t { + svcvt_f64_u32_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s32_f32_m(inactive: svint32_t, pg: svbool_t, op: svfloat32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32" + )] + fn _svcvt_s32_f32_m(inactive: svint32_t, pg: svbool4_t, op: svfloat32_t) -> svint32_t; + } + unsafe { _svcvt_s32_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s32_f32_x(pg: svbool_t, op: svfloat32_t) -> svint32_t { + unsafe { svcvt_s32_f32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s32_f32_z(pg: svbool_t, op: svfloat32_t) -> svint32_t { + svcvt_s32_f32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s64_f64_m(inactive: svint64_t, pg: svbool_t, op: svfloat64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fcvtzs.nxv2i64.nxv2f64" + )] + fn _svcvt_s64_f64_m(inactive: svint64_t, pg: svbool2_t, op: svfloat64_t) -> svint64_t; + } + unsafe { _svcvt_s64_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s64_f64_x(pg: svbool_t, op: svfloat64_t) -> svint64_t { + unsafe { svcvt_s64_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s64_f64_z(pg: svbool_t, op: svfloat64_t) -> svint64_t { + svcvt_s64_f64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u32_f32_m(inactive: svuint32_t, pg: svbool_t, op: svfloat32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fcvtzu.nxv4i32.nxv4f32" + )] + fn _svcvt_u32_f32_m(inactive: svint32_t, pg: svbool4_t, op: svfloat32_t) -> svint32_t; + } + unsafe { _svcvt_u32_f32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u32_f32_x(pg: svbool_t, op: svfloat32_t) -> svuint32_t { + unsafe { svcvt_u32_f32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u32_f32_z(pg: svbool_t, op: svfloat32_t) -> svuint32_t { + svcvt_u32_f32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u64_f64_m(inactive: svuint64_t, pg: svbool_t, op: svfloat64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fcvtzu.nxv2i64.nxv2f64" + )] + fn _svcvt_u64_f64_m(inactive: svint64_t, pg: svbool2_t, op: svfloat64_t) -> svint64_t; + } + unsafe { _svcvt_u64_f64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u64_f64_x(pg: svbool_t, op: svfloat64_t) -> svuint64_t { + unsafe { svcvt_u64_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u64_f64_z(pg: svbool_t, op: svfloat64_t) -> svuint64_t { + svcvt_u64_f64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s32_f64_m(inactive: svint32_t, pg: svbool_t, op: svfloat64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzs.i32f64")] + fn _svcvt_s32_f64_m(inactive: svint32_t, pg: svbool2_t, op: svfloat64_t) -> svint32_t; + } + unsafe { _svcvt_s32_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s32_f64_x(pg: svbool_t, op: svfloat64_t) -> svint32_t { + unsafe { svcvt_s32_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s32_f64_z(pg: svbool_t, op: svfloat64_t) -> svint32_t { + svcvt_s32_f64_m(svdup_n_s32(0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s64_f32_m(inactive: svint64_t, pg: svbool_t, op: svfloat32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzs.i64f32")] + fn _svcvt_s64_f32_m(inactive: svint64_t, pg: svbool2_t, op: svfloat32_t) -> svint64_t; + } + unsafe { _svcvt_s64_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s64_f32_x(pg: svbool_t, op: svfloat32_t) -> svint64_t { + unsafe { svcvt_s64_f32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s64_f32_z(pg: svbool_t, op: svfloat32_t) -> svint64_t { + svcvt_s64_f32_m(svdup_n_s64(0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u32_f64_m(inactive: svuint32_t, pg: svbool_t, op: svfloat64_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzu.i32f64")] + fn _svcvt_u32_f64_m(inactive: svint32_t, pg: svbool2_t, op: svfloat64_t) -> svint32_t; + } + unsafe { _svcvt_u32_f64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u32_f64_x(pg: svbool_t, op: svfloat64_t) -> svuint32_t { + unsafe { svcvt_u32_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u32_f64_z(pg: svbool_t, op: svfloat64_t) -> svuint32_t { + svcvt_u32_f64_m(svdup_n_u32(0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u64_f32_m(inactive: svuint64_t, pg: svbool_t, op: svfloat32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzu.i64f32")] + fn _svcvt_u64_f32_m(inactive: svint64_t, pg: svbool2_t, op: svfloat32_t) -> svint64_t; + } + unsafe { _svcvt_u64_f32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u64_f32_x(pg: svbool_t, op: svfloat32_t) -> svuint64_t { + unsafe { svcvt_u64_f32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u64_f32_z(pg: svbool_t, op: svfloat32_t) -> svuint64_t { + svcvt_u64_f32_m(svdup_n_u64(0), pg, op) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fdiv.nxv4f32")] + fn _svdiv_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svdiv_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svdiv_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svdiv_f32_m(pg, op1, op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svdiv_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svdiv_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svdiv_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fdiv.nxv2f64")] + fn _svdiv_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svdiv_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svdiv_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svdiv_f64_m(pg, op1, op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svdiv_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svdiv_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svdiv_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdiv.nxv4i32")] + fn _svdiv_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svdiv_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svdiv_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svdiv_s32_m(pg, op1, op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svdiv_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svdiv_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svdiv_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdiv.nxv2i64")] + fn _svdiv_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svdiv_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svdiv_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svdiv_s64_m(pg, op1, op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svdiv_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svdiv_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svdiv_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udiv.nxv4i32")] + fn _svdiv_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svdiv_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svdiv_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svdiv_u32_m(pg, op1, op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svdiv_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svdiv_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svdiv_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udiv.nxv2i64")] + fn _svdiv_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svdiv_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svdiv_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svdiv_u64_m(pg, op1, op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svdiv_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svdiv_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svdiv_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fdivr.nxv4f32")] + fn _svdivr_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svdivr_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svdivr_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svdivr_f32_m(pg, op1, op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svdivr_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svdivr_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svdivr_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fdivr.nxv2f64")] + fn _svdivr_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svdivr_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svdivr_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svdivr_f64_m(pg, op1, op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svdivr_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svdivr_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svdivr_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdivr.nxv4i32")] + fn _svdivr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svdivr_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svdivr_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svdivr_s32_m(pg, op1, op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svdivr_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svdivr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svdivr_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdivr.nxv2i64")] + fn _svdivr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svdivr_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svdivr_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svdivr_s64_m(pg, op1, op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svdivr_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svdivr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svdivr_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udivr.nxv4i32")] + fn _svdivr_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svdivr_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svdivr_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svdivr_u32_m(pg, op1, op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svdivr_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svdivr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svdivr_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udivr.nxv2i64")] + fn _svdivr_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svdivr_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svdivr_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svdivr_u64_m(pg, op1, op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svdivr_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svdivr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svdivr_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdot, IMM_INDEX = 0))] +pub fn svdot_lane_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sdot.lane.nxv4i32" + )] + fn _svdot_lane_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, + imm_index: i32, + ) -> svint32_t; + } + unsafe { _svdot_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdot, IMM_INDEX = 0))] +pub fn svdot_lane_s64( + op1: svint64_t, + op2: svint16_t, + op3: svint16_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sdot.lane.nxv2i64" + )] + fn _svdot_lane_s64( + op1: svint64_t, + op2: svint16_t, + op3: svint16_t, + imm_index: i32, + ) -> svint64_t; + } + unsafe { _svdot_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udot, IMM_INDEX = 0))] +pub fn svdot_lane_u32( + op1: svuint32_t, + op2: svuint8_t, + op3: svuint8_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.udot.lane.nxv4i32" + )] + fn _svdot_lane_u32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, + imm_index: i32, + ) -> svint32_t; + } + unsafe { + _svdot_lane_u32(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX).as_unsigned() + } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udot, IMM_INDEX = 0))] +pub fn svdot_lane_u64( + op1: svuint64_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.udot.lane.nxv2i64" + )] + fn _svdot_lane_u64( + op1: svint64_t, + op2: svint16_t, + op3: svint16_t, + imm_index: i32, + ) -> svint64_t; + } + unsafe { + _svdot_lane_u64(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX).as_unsigned() + } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdot))] +pub fn svdot_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdot.nxv4i32")] + fn _svdot_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t; + } + unsafe { _svdot_s32(op1, op2, op3) } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdot))] +pub fn svdot_n_s32(op1: svint32_t, op2: svint8_t, op3: i8) -> svint32_t { + svdot_s32(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdot))] +pub fn svdot_s64(op1: svint64_t, op2: svint16_t, op3: svint16_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdot.nxv2i64")] + fn _svdot_s64(op1: svint64_t, op2: svint16_t, op3: svint16_t) -> svint64_t; + } + unsafe { _svdot_s64(op1, op2, op3) } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdot))] +pub fn svdot_n_s64(op1: svint64_t, op2: svint16_t, op3: i16) -> svint64_t { + svdot_s64(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udot))] +pub fn svdot_u32(op1: svuint32_t, op2: svuint8_t, op3: svuint8_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udot.nxv4i32")] + fn _svdot_u32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t; + } + unsafe { _svdot_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udot))] +pub fn svdot_n_u32(op1: svuint32_t, op2: svuint8_t, op3: u8) -> svuint32_t { + svdot_u32(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udot))] +pub fn svdot_u64(op1: svuint64_t, op2: svuint16_t, op3: svuint16_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udot.nxv2i64")] + fn _svdot_u64(op1: svint64_t, op2: svint16_t, op3: svint16_t) -> svint64_t; + } + unsafe { _svdot_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udot))] +pub fn svdot_n_u64(op1: svuint64_t, op2: svuint16_t, op3: u16) -> svuint64_t { + svdot_u64(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_f32(data: svfloat32_t, index: u32) -> svfloat32_t { + svtbl_f32(data, svdup_n_u32(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_f64(data: svfloat64_t, index: u64) -> svfloat64_t { + svtbl_f64(data, svdup_n_u64(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_s8(data: svint8_t, index: u8) -> svint8_t { + svtbl_s8(data, svdup_n_u8(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_s16(data: svint16_t, index: u16) -> svint16_t { + svtbl_s16(data, svdup_n_u16(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_s32(data: svint32_t, index: u32) -> svint32_t { + svtbl_s32(data, svdup_n_u32(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_s64(data: svint64_t, index: u64) -> svint64_t { + svtbl_s64(data, svdup_n_u64(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_u8(data: svuint8_t, index: u8) -> svuint8_t { + svtbl_u8(data, svdup_n_u8(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_u16(data: svuint16_t, index: u16) -> svuint16_t { + svtbl_u16(data, svdup_n_u16(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_u32(data: svuint32_t, index: u32) -> svuint32_t { + svtbl_u32(data, svdup_n_u32(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_u64(data: svuint64_t, index: u64) -> svuint64_t { + svtbl_u64(data, svdup_n_u64(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbfx))] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svdup_n_b8(op: bool) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv16i1")] + fn _svdup_n_b8(op: bool) -> svbool_t; + } + unsafe { _svdup_n_b8(op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbfx))] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svdup_n_b16(op: bool) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv8i1")] + fn _svdup_n_b16(op: bool) -> svbool8_t; + } + unsafe { _svdup_n_b16(op).sve_into() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbfx))] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svdup_n_b32(op: bool) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv4i1")] + fn _svdup_n_b32(op: bool) -> svbool4_t; + } + unsafe { _svdup_n_b32(op).sve_into() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbfx))] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svdup_n_b64(op: bool) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv2i1")] + fn _svdup_n_b64(op: bool) -> svbool2_t; + } + unsafe { _svdup_n_b64(op).sve_into() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f32(op: f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv4f32")] + fn _svdup_n_f32(op: f32) -> svfloat32_t; + } + unsafe { _svdup_n_f32(op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f64(op: f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv2f64")] + fn _svdup_n_f64(op: f64) -> svfloat64_t; + } + unsafe { _svdup_n_f64(op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s8(op: i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv16i8")] + fn _svdup_n_s8(op: i8) -> svint8_t; + } + unsafe { _svdup_n_s8(op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s16(op: i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv8i16")] + fn _svdup_n_s16(op: i16) -> svint16_t; + } + unsafe { _svdup_n_s16(op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s32(op: i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv4i32")] + fn _svdup_n_s32(op: i32) -> svint32_t; + } + unsafe { _svdup_n_s32(op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s64(op: i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv2i64")] + fn _svdup_n_s64(op: i64) -> svint64_t; + } + unsafe { _svdup_n_s64(op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u8(op: u8) -> svuint8_t { + unsafe { svdup_n_s8(op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u16(op: u16) -> svuint16_t { + unsafe { svdup_n_s16(op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u32(op: u32) -> svuint32_t { + unsafe { svdup_n_s32(op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u64(op: u64) -> svuint64_t { + unsafe { svdup_n_s64(op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f32_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f32_m(inactive: svfloat32_t, pg: svbool_t, op: f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv4f32")] + fn _svdup_n_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: f32) -> svfloat32_t; + } + unsafe { _svdup_n_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f32_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f32_x(pg: svbool_t, op: f32) -> svfloat32_t { + svdup_n_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f32_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f32_z(pg: svbool_t, op: f32) -> svfloat32_t { + svdup_n_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f64_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f64_m(inactive: svfloat64_t, pg: svbool_t, op: f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv2f64")] + fn _svdup_n_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: f64) -> svfloat64_t; + } + unsafe { _svdup_n_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f64_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f64_x(pg: svbool_t, op: f64) -> svfloat64_t { + svdup_n_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f64_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f64_z(pg: svbool_t, op: f64) -> svfloat64_t { + svdup_n_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s8_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s8_m(inactive: svint8_t, pg: svbool_t, op: i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv16i8")] + fn _svdup_n_s8_m(inactive: svint8_t, pg: svbool_t, op: i8) -> svint8_t; + } + unsafe { _svdup_n_s8_m(inactive, pg, op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s8_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s8_x(pg: svbool_t, op: i8) -> svint8_t { + svdup_n_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s8_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s8_z(pg: svbool_t, op: i8) -> svint8_t { + svdup_n_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s16_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s16_m(inactive: svint16_t, pg: svbool_t, op: i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv8i16")] + fn _svdup_n_s16_m(inactive: svint16_t, pg: svbool8_t, op: i16) -> svint16_t; + } + unsafe { _svdup_n_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s16_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s16_x(pg: svbool_t, op: i16) -> svint16_t { + svdup_n_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s16_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s16_z(pg: svbool_t, op: i16) -> svint16_t { + svdup_n_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s32_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s32_m(inactive: svint32_t, pg: svbool_t, op: i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv4i32")] + fn _svdup_n_s32_m(inactive: svint32_t, pg: svbool4_t, op: i32) -> svint32_t; + } + unsafe { _svdup_n_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s32_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s32_x(pg: svbool_t, op: i32) -> svint32_t { + svdup_n_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s32_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s32_z(pg: svbool_t, op: i32) -> svint32_t { + svdup_n_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s64_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s64_m(inactive: svint64_t, pg: svbool_t, op: i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv2i64")] + fn _svdup_n_s64_m(inactive: svint64_t, pg: svbool2_t, op: i64) -> svint64_t; + } + unsafe { _svdup_n_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s64_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s64_x(pg: svbool_t, op: i64) -> svint64_t { + svdup_n_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s64_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s64_z(pg: svbool_t, op: i64) -> svint64_t { + svdup_n_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u8_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u8_m(inactive: svuint8_t, pg: svbool_t, op: u8) -> svuint8_t { + unsafe { svdup_n_s8_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u8_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u8_x(pg: svbool_t, op: u8) -> svuint8_t { + svdup_n_u8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u8_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u8_z(pg: svbool_t, op: u8) -> svuint8_t { + svdup_n_u8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u16_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u16_m(inactive: svuint16_t, pg: svbool_t, op: u16) -> svuint16_t { + unsafe { svdup_n_s16_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u16_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u16_x(pg: svbool_t, op: u16) -> svuint16_t { + svdup_n_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u16_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u16_z(pg: svbool_t, op: u16) -> svuint16_t { + svdup_n_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u32_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u32_m(inactive: svuint32_t, pg: svbool_t, op: u32) -> svuint32_t { + unsafe { svdup_n_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u32_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u32_x(pg: svbool_t, op: u32) -> svuint32_t { + svdup_n_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u32_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u32_z(pg: svbool_t, op: u32) -> svuint32_t { + svdup_n_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u64_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u64_m(inactive: svuint64_t, pg: svbool_t, op: u64) -> svuint64_t { + unsafe { svdup_n_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u64_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u64_x(pg: svbool_t, op: u64) -> svuint64_t { + svdup_n_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u64_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u64_z(pg: svbool_t, op: u64) -> svuint64_t { + svdup_n_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_f32(data: svfloat32_t, index: u64) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.dupq.lane.nxv4f32" + )] + fn _svdupq_lane_f32(data: svfloat32_t, index: i64) -> svfloat32_t; + } + unsafe { _svdupq_lane_f32(data, index.as_signed()) } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_f64(data: svfloat64_t, index: u64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.dupq.lane.nxv2f64" + )] + fn _svdupq_lane_f64(data: svfloat64_t, index: i64) -> svfloat64_t; + } + unsafe { _svdupq_lane_f64(data, index.as_signed()) } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_s8(data: svint8_t, index: u64) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.dupq.lane.nxv16i8" + )] + fn _svdupq_lane_s8(data: svint8_t, index: i64) -> svint8_t; + } + unsafe { _svdupq_lane_s8(data, index.as_signed()) } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_s16(data: svint16_t, index: u64) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.dupq.lane.nxv8i16" + )] + fn _svdupq_lane_s16(data: svint16_t, index: i64) -> svint16_t; + } + unsafe { _svdupq_lane_s16(data, index.as_signed()) } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_s32(data: svint32_t, index: u64) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.dupq.lane.nxv4i32" + )] + fn _svdupq_lane_s32(data: svint32_t, index: i64) -> svint32_t; + } + unsafe { _svdupq_lane_s32(data, index.as_signed()) } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_s64(data: svint64_t, index: u64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.dupq.lane.nxv2i64" + )] + fn _svdupq_lane_s64(data: svint64_t, index: i64) -> svint64_t; + } + unsafe { _svdupq_lane_s64(data, index.as_signed()) } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_u8(data: svuint8_t, index: u64) -> svuint8_t { + unsafe { svdupq_lane_s8(data.as_signed(), index).as_unsigned() } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_u16(data: svuint16_t, index: u64) -> svuint16_t { + unsafe { svdupq_lane_s16(data.as_signed(), index).as_unsigned() } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_u32(data: svuint32_t, index: u64) -> svuint32_t { + unsafe { svdupq_lane_s32(data.as_signed(), index).as_unsigned() } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_u64(data: svuint64_t, index: u64) -> svuint64_t { + unsafe { svdupq_lane_s64(data.as_signed(), index).as_unsigned() } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_b16( + x0: bool, + x1: bool, + x2: bool, + x3: bool, + x4: bool, + x5: bool, + x6: bool, + x7: bool, +) -> svbool_t { + let op1 = svdupq_n_s16( + x0 as i16, x1 as i16, x2 as i16, x3 as i16, x4 as i16, x5 as i16, x6 as i16, x7 as i16, + ); + svcmpne_wide_s16(svptrue_b16(), op1, svdup_n_s64(0)) +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_b32(x0: bool, x1: bool, x2: bool, x3: bool) -> svbool_t { + let op1 = svdupq_n_s32(x0 as i32, x1 as i32, x2 as i32, x3 as i32); + svcmpne_wide_s32(svptrue_b32(), op1, svdup_n_s64(0)) +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_b64(x0: bool, x1: bool) -> svbool_t { + let op1 = svdupq_n_s64(x0 as i64, x1 as i64); + svcmpne_s64(svptrue_b64(), op1, svdup_n_s64(0)) +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_b8( + x0: bool, + x1: bool, + x2: bool, + x3: bool, + x4: bool, + x5: bool, + x6: bool, + x7: bool, + x8: bool, + x9: bool, + x10: bool, + x11: bool, + x12: bool, + x13: bool, + x14: bool, + x15: bool, +) -> svbool_t { + let op1 = svdupq_n_s8( + x0 as i8, x1 as i8, x2 as i8, x3 as i8, x4 as i8, x5 as i8, x6 as i8, x7 as i8, x8 as i8, + x9 as i8, x10 as i8, x11 as i8, x12 as i8, x13 as i8, x14 as i8, x15 as i8, + ); + svcmpne_wide_s8(svptrue_b8(), op1, svdup_n_s64(0)) +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_f32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_f32(x0: f32, x1: f32, x2: f32, x3: f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.vector.insert.nxv4f32.v4f32" + )] + fn _svdupq_n_f32(op0: svfloat32_t, op1: float32x4_t, idx: i64) -> svfloat32_t; + } + unsafe { + let op = _svdupq_n_f32(svundef_f32(), crate::mem::transmute([x0, x1, x2, x3]), 0); + svdupq_lane_f32(op, 0) + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_s32(x0: i32, x1: i32, x2: i32, x3: i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.vector.insert.nxv4i32.v4i32" + )] + fn _svdupq_n_s32(op0: svint32_t, op1: int32x4_t, idx: i64) -> svint32_t; + } + unsafe { + let op = _svdupq_n_s32(svundef_s32(), crate::mem::transmute([x0, x1, x2, x3]), 0); + svdupq_lane_s32(op, 0) + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_u32(x0: u32, x1: u32, x2: u32, x3: u32) -> svuint32_t { + unsafe { + svdupq_n_s32( + x0.as_signed(), + x1.as_signed(), + x2.as_signed(), + x3.as_signed(), + ) + .as_unsigned() + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_f64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_f64(x0: f64, x1: f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.vector.insert.nxv2f64.v2f64" + )] + fn _svdupq_n_f64(op0: svfloat64_t, op1: float64x2_t, idx: i64) -> svfloat64_t; + } + unsafe { + let op = _svdupq_n_f64(svundef_f64(), crate::mem::transmute([x0, x1]), 0); + svdupq_lane_f64(op, 0) + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_s64(x0: i64, x1: i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.vector.insert.nxv2i64.v2i64" + )] + fn _svdupq_n_s64(op0: svint64_t, op1: int64x2_t, idx: i64) -> svint64_t; + } + unsafe { + let op = _svdupq_n_s64(svundef_s64(), crate::mem::transmute([x0, x1]), 0); + svdupq_lane_s64(op, 0) + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_u64(x0: u64, x1: u64) -> svuint64_t { + unsafe { svdupq_n_s64(x0.as_signed(), x1.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_s16( + x0: i16, + x1: i16, + x2: i16, + x3: i16, + x4: i16, + x5: i16, + x6: i16, + x7: i16, +) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.vector.insert.nxv8i16.v8i16" + )] + fn _svdupq_n_s16(op0: svint16_t, op1: int16x8_t, idx: i64) -> svint16_t; + } + unsafe { + let op = _svdupq_n_s16( + svundef_s16(), + crate::mem::transmute([x0, x1, x2, x3, x4, x5, x6, x7]), + 0, + ); + svdupq_lane_s16(op, 0) + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_u16( + x0: u16, + x1: u16, + x2: u16, + x3: u16, + x4: u16, + x5: u16, + x6: u16, + x7: u16, +) -> svuint16_t { + unsafe { + svdupq_n_s16( + x0.as_signed(), + x1.as_signed(), + x2.as_signed(), + x3.as_signed(), + x4.as_signed(), + x5.as_signed(), + x6.as_signed(), + x7.as_signed(), + ) + .as_unsigned() + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_s8( + x0: i8, + x1: i8, + x2: i8, + x3: i8, + x4: i8, + x5: i8, + x6: i8, + x7: i8, + x8: i8, + x9: i8, + x10: i8, + x11: i8, + x12: i8, + x13: i8, + x14: i8, + x15: i8, +) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.vector.insert.nxv16i8.v16i8" + )] + fn _svdupq_n_s8(op0: svint8_t, op1: int8x16_t, idx: i64) -> svint8_t; + } + unsafe { + let op = _svdupq_n_s8( + svundef_s8(), + crate::mem::transmute([ + x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, + ]), + 0, + ); + svdupq_lane_s8(op, 0) + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_u8( + x0: u8, + x1: u8, + x2: u8, + x3: u8, + x4: u8, + x5: u8, + x6: u8, + x7: u8, + x8: u8, + x9: u8, + x10: u8, + x11: u8, + x12: u8, + x13: u8, + x14: u8, + x15: u8, +) -> svuint8_t { + unsafe { + svdupq_n_s8( + x0.as_signed(), + x1.as_signed(), + x2.as_signed(), + x3.as_signed(), + x4.as_signed(), + x5.as_signed(), + x6.as_signed(), + x7.as_signed(), + x8.as_signed(), + x9.as_signed(), + x10.as_signed(), + x11.as_signed(), + x12.as_signed(), + x13.as_signed(), + x14.as_signed(), + x15.as_signed(), + ) + .as_unsigned() + } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.z.nxv16i1")] + fn _sveor_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _sveor_b_z(pg, op1, op2) } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.nxv16i8")] + fn _sveor_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _sveor_s8_m(pg, op1, op2) } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + sveor_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + sveor_s8_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + sveor_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + sveor_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + sveor_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.nxv8i16")] + fn _sveor_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _sveor_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + sveor_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + sveor_s16_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + sveor_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + sveor_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + sveor_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.nxv4i32")] + fn _sveor_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _sveor_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + sveor_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + sveor_s32_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + sveor_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + sveor_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + sveor_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.nxv2i64")] + fn _sveor_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _sveor_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + sveor_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + sveor_s64_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + sveor_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + sveor_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + sveor_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { sveor_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + sveor_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + sveor_u8_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + sveor_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + sveor_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + sveor_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { sveor_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + sveor_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + sveor_u16_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + sveor_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + sveor_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + sveor_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { sveor_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + sveor_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + sveor_u32_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + sveor_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + sveor_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + sveor_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { sveor_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + sveor_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + sveor_u64_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + sveor_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + sveor_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + sveor_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_s8(pg: svbool_t, op: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorv.nxv16i8")] + fn _sveorv_s8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _sveorv_s8(pg, op) } +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_s16(pg: svbool_t, op: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorv.nxv8i16")] + fn _sveorv_s16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _sveorv_s16(pg.sve_into(), op) } +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_s32(pg: svbool_t, op: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorv.nxv4i32")] + fn _sveorv_s32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _sveorv_s32(pg.sve_into(), op) } +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorv.nxv2i64")] + fn _sveorv_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _sveorv_s64(pg.sve_into(), op) } +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_u8(pg: svbool_t, op: svuint8_t) -> u8 { + unsafe { sveorv_s8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_u16(pg: svbool_t, op: svuint16_t) -> u16 { + unsafe { sveorv_s16(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_u32(pg: svbool_t, op: svuint32_t) -> u32 { + unsafe { sveorv_s32(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe { sveorv_s64(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Floating-point exponential accelerator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexpa[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fexpa))] +pub fn svexpa_f32(op: svuint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fexpa.x.nxv4f32" + )] + fn _svexpa_f32(op: svint32_t) -> svfloat32_t; + } + unsafe { _svexpa_f32(op.as_signed()) } +} +#[doc = "Floating-point exponential accelerator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexpa[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fexpa))] +pub fn svexpa_f64(op: svuint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fexpa.x.nxv2f64" + )] + fn _svexpa_f64(op: svint64_t) -> svfloat64_t; + } + unsafe { _svexpa_f64(op.as_signed()) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + static_assert_range!(IMM3, 0..=63); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv4f32")] + fn _svext_f32(op1: svfloat32_t, op2: svfloat32_t, imm3: i32) -> svfloat32_t; + } + unsafe { _svext_f32(op1, op2, IMM3) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + static_assert_range!(IMM3, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv2f64")] + fn _svext_f64(op1: svfloat64_t, op2: svfloat64_t, imm3: i32) -> svfloat64_t; + } + unsafe { _svext_f64(op1, op2, IMM3) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert_range!(IMM3, 0..=255); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv16i8")] + fn _svext_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svext_s8(op1, op2, IMM3) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM3, 0..=127); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv8i16")] + fn _svext_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svext_s16(op1, op2, IMM3) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM3, 0..=63); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv4i32")] + fn _svext_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svext_s32(op1, op2, IMM3) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM3, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv2i64")] + fn _svext_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svext_s64(op1, op2, IMM3) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + static_assert_range!(IMM3, 0..=255); + unsafe { svext_s8::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert_range!(IMM3, 0..=127); + unsafe { svext_s16::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert_range!(IMM3, 0..=63); + unsafe { svext_s32::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert_range!(IMM3, 0..=31); + unsafe { svext_s64::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxtb.nxv8i16")] + fn _svextb_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svextb_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svextb_s16_m(op, pg, op) +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svextb_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxtb.nxv4i32")] + fn _svextb_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svextb_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svextb_s32_m(op, pg, op) +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svextb_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Sign-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxth))] +pub fn svexth_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxth.nxv4i32")] + fn _svexth_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svexth_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Sign-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxth))] +pub fn svexth_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svexth_s32_m(op, pg, op) +} +#[doc = "Sign-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxth))] +pub fn svexth_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svexth_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxtb.nxv2i64")] + fn _svextb_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svextb_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svextb_s64_m(op, pg, op) +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svextb_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Sign-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxth))] +pub fn svexth_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxth.nxv2i64")] + fn _svexth_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svexth_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Sign-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxth))] +pub fn svexth_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svexth_s64_m(op, pg, op) +} +#[doc = "Sign-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxth))] +pub fn svexth_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svexth_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Sign-extend the low 32 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtw))] +pub fn svextw_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxtw.nxv2i64")] + fn _svextw_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svextw_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Sign-extend the low 32 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtw))] +pub fn svextw_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svextw_s64_m(op, pg, op) +} +#[doc = "Sign-extend the low 32 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtw))] +pub fn svextw_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svextw_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxtb.nxv8i16")] + fn _svextb_u16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svextb_u16_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svextb_u16_m(op, pg, op) +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svextb_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxtb.nxv4i32")] + fn _svextb_u32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svextb_u32_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svextb_u32_m(op, pg, op) +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svextb_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Zero-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxth))] +pub fn svexth_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxth.nxv4i32")] + fn _svexth_u32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svexth_u32_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Zero-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxth))] +pub fn svexth_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svexth_u32_m(op, pg, op) +} +#[doc = "Zero-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxth))] +pub fn svexth_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svexth_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxtb.nxv2i64")] + fn _svextb_u64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svextb_u64_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svextb_u64_m(op, pg, op) +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svextb_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Zero-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxth))] +pub fn svexth_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxth.nxv2i64")] + fn _svexth_u64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svexth_u64_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Zero-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxth))] +pub fn svexth_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svexth_u64_m(op, pg, op) +} +#[doc = "Zero-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxth))] +pub fn svexth_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svexth_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Zero-extend the low 32 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtw))] +pub fn svextw_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxtw.nxv2i64")] + fn _svextw_u64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svextw_u64_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Zero-extend the low 32 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtw))] +pub fn svextw_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svextw_u64_m(op, pg, op) +} +#[doc = "Zero-extend the low 32 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtw))] +pub fn svextw_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svextw_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_f32(tuple: svfloat32x2_t) -> svfloat32_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_f64(tuple: svfloat64x2_t) -> svfloat64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_s8(tuple: svint8x2_t) -> svint8_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_s16(tuple: svint16x2_t) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_s32(tuple: svint32x2_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_s64(tuple: svint64x2_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_u8(tuple: svuint8x2_t) -> svuint8_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_u16(tuple: svuint16x2_t) -> svuint16_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_u32(tuple: svuint32x2_t) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_u64(tuple: svuint64x2_t) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_f32(tuple: svfloat32x3_t) -> svfloat32_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_f64(tuple: svfloat64x3_t) -> svfloat64_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_s8(tuple: svint8x3_t) -> svint8_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_s16(tuple: svint16x3_t) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_s32(tuple: svint32x3_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_s64(tuple: svint64x3_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_u8(tuple: svuint8x3_t) -> svuint8_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_u16(tuple: svuint16x3_t) -> svuint16_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_u32(tuple: svuint32x3_t) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_u64(tuple: svuint64x3_t) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_f32(tuple: svfloat32x4_t) -> svfloat32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_f64(tuple: svfloat64x4_t) -> svfloat64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_s8(tuple: svint8x4_t) -> svint8_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_s16(tuple: svint16x4_t) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_s32(tuple: svint32x4_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_s64(tuple: svint64x4_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_u8(tuple: svuint8x4_t) -> svuint8_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_u16(tuple: svuint16x4_t) -> svuint16_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_u32(tuple: svuint32x4_t) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_u64(tuple: svuint64x4_t) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_s8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_s8(base: i8, step: i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.index.nxv16i8")] + fn _svindex_s8(base: i8, step: i8) -> svint8_t; + } + unsafe { _svindex_s8(base, step) } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_s16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_s16(base: i16, step: i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.index.nxv8i16")] + fn _svindex_s16(base: i16, step: i16) -> svint16_t; + } + unsafe { _svindex_s16(base, step) } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_s32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_s32(base: i32, step: i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.index.nxv4i32")] + fn _svindex_s32(base: i32, step: i32) -> svint32_t; + } + unsafe { _svindex_s32(base, step) } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_s64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_s64(base: i64, step: i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.index.nxv2i64")] + fn _svindex_s64(base: i64, step: i64) -> svint64_t; + } + unsafe { _svindex_s64(base, step) } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_u8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_u8(base: u8, step: u8) -> svuint8_t { + unsafe { svindex_s8(base.as_signed(), step.as_signed()).as_unsigned() } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_u16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_u16(base: u16, step: u16) -> svuint16_t { + unsafe { svindex_s16(base.as_signed(), step.as_signed()).as_unsigned() } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_u32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_u32(base: u32, step: u32) -> svuint32_t { + unsafe { svindex_s32(base.as_signed(), step.as_signed()).as_unsigned() } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_u64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_u64(base: u64, step: u64) -> svuint64_t { + unsafe { svindex_s64(base.as_signed(), step.as_signed()).as_unsigned() } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_f32(op1: svfloat32_t, op2: f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv4f32")] + fn _svinsr_n_f32(op1: svfloat32_t, op2: f32) -> svfloat32_t; + } + unsafe { _svinsr_n_f32(op1, op2) } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_f64(op1: svfloat64_t, op2: f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv2f64")] + fn _svinsr_n_f64(op1: svfloat64_t, op2: f64) -> svfloat64_t; + } + unsafe { _svinsr_n_f64(op1, op2) } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_s8(op1: svint8_t, op2: i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv16i8")] + fn _svinsr_n_s8(op1: svint8_t, op2: i8) -> svint8_t; + } + unsafe { _svinsr_n_s8(op1, op2) } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_s16(op1: svint16_t, op2: i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv8i16")] + fn _svinsr_n_s16(op1: svint16_t, op2: i16) -> svint16_t; + } + unsafe { _svinsr_n_s16(op1, op2) } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_s32(op1: svint32_t, op2: i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv4i32")] + fn _svinsr_n_s32(op1: svint32_t, op2: i32) -> svint32_t; + } + unsafe { _svinsr_n_s32(op1, op2) } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_s64(op1: svint64_t, op2: i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv2i64")] + fn _svinsr_n_s64(op1: svint64_t, op2: i64) -> svint64_t; + } + unsafe { _svinsr_n_s64(op1, op2) } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + unsafe { svinsr_n_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t { + unsafe { svinsr_n_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + unsafe { svinsr_n_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + unsafe { svinsr_n_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_f32(pg: svbool_t, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv4f32")] + fn _svlasta_f32(pg: svbool4_t, op: svfloat32_t) -> f32; + } + unsafe { _svlasta_f32(pg.sve_into(), op) } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_f64(pg: svbool_t, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv2f64")] + fn _svlasta_f64(pg: svbool2_t, op: svfloat64_t) -> f64; + } + unsafe { _svlasta_f64(pg.sve_into(), op) } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_s8(pg: svbool_t, op: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv16i8")] + fn _svlasta_s8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svlasta_s8(pg, op) } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_s16(pg: svbool_t, op: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv8i16")] + fn _svlasta_s16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svlasta_s16(pg.sve_into(), op) } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_s32(pg: svbool_t, op: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv4i32")] + fn _svlasta_s32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svlasta_s32(pg.sve_into(), op) } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv2i64")] + fn _svlasta_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svlasta_s64(pg.sve_into(), op) } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_u8(pg: svbool_t, op: svuint8_t) -> u8 { + unsafe { svlasta_s8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_u16(pg: svbool_t, op: svuint16_t) -> u16 { + unsafe { svlasta_s16(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_u32(pg: svbool_t, op: svuint32_t) -> u32 { + unsafe { svlasta_s32(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe { svlasta_s64(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_f32(pg: svbool_t, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv4f32")] + fn _svlastb_f32(pg: svbool4_t, op: svfloat32_t) -> f32; + } + unsafe { _svlastb_f32(pg.sve_into(), op) } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_f64(pg: svbool_t, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv2f64")] + fn _svlastb_f64(pg: svbool2_t, op: svfloat64_t) -> f64; + } + unsafe { _svlastb_f64(pg.sve_into(), op) } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_s8(pg: svbool_t, op: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv16i8")] + fn _svlastb_s8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svlastb_s8(pg, op) } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_s16(pg: svbool_t, op: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv8i16")] + fn _svlastb_s16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svlastb_s16(pg.sve_into(), op) } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_s32(pg: svbool_t, op: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv4i32")] + fn _svlastb_s32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svlastb_s32(pg.sve_into(), op) } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv2i64")] + fn _svlastb_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svlastb_s64(pg.sve_into(), op) } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_u8(pg: svbool_t, op: svuint8_t) -> u8 { + unsafe { svlastb_s8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_u16(pg: svbool_t, op: svuint16_t) -> u16 { + unsafe { svlastb_s16(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_u32(pg: svbool_t, op: svuint32_t) -> u32 { + unsafe { svlastb_s32(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe { svlastb_s64(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_f32(pg: svbool_t, base: *const f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4f32")] + fn _svld1_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t; + } + _svld1_f32(pg.sve_into(), base) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_f64(pg: svbool_t, base: *const f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2f64")] + fn _svld1_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t; + } + _svld1_f64(pg.sve_into(), base) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1_s8(pg: svbool_t, base: *const i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv16i8")] + fn _svld1_s8(pg: svbool_t, base: *const i8) -> svint8_t; + } + _svld1_s8(pg, base) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1_s16(pg: svbool_t, base: *const i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv8i16")] + fn _svld1_s16(pg: svbool8_t, base: *const i16) -> svint16_t; + } + _svld1_s16(pg.sve_into(), base) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_s32(pg: svbool_t, base: *const i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4i32")] + fn _svld1_s32(pg: svbool4_t, base: *const i32) -> svint32_t; + } + _svld1_s32(pg.sve_into(), base) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_s64(pg: svbool_t, base: *const i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i64")] + fn _svld1_s64(pg: svbool2_t, base: *const i64) -> svint64_t; + } + _svld1_s64(pg.sve_into(), base) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1_u8(pg: svbool_t, base: *const u8) -> svuint8_t { + svld1_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1_u16(pg: svbool_t, base: *const u16) -> svuint16_t { + svld1_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_u32(pg: svbool_t, base: *const u32) -> svuint32_t { + svld1_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_u64(pg: svbool_t, base: *const u64) -> svuint64_t { + svld1_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_s32index_f32( + pg: svbool_t, + base: *const f32, + indices: svint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4f32" + )] + fn _svld1_gather_s32index_f32( + pg: svbool4_t, + base: *const f32, + indices: svint32_t, + ) -> svfloat32_t; + } + _svld1_gather_s32index_f32(pg.sve_into(), base, indices) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_s32index_s32( + pg: svbool_t, + base: *const i32, + indices: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4i32" + )] + fn _svld1_gather_s32index_s32( + pg: svbool4_t, + base: *const i32, + indices: svint32_t, + ) -> svint32_t; + } + _svld1_gather_s32index_s32(pg.sve_into(), base, indices) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_s32index_u32( + pg: svbool_t, + base: *const u32, + indices: svint32_t, +) -> svuint32_t { + svld1_gather_s32index_s32(pg, base.as_signed(), indices).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_s64index_f64( + pg: svbool_t, + base: *const f64, + indices: svint64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2f64" + )] + fn _svld1_gather_s64index_f64( + pg: svbool2_t, + base: *const f64, + indices: svint64_t, + ) -> svfloat64_t; + } + _svld1_gather_s64index_f64(pg.sve_into(), base, indices) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_s64index_s64( + pg: svbool_t, + base: *const i64, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2i64" + )] + fn _svld1_gather_s64index_s64( + pg: svbool2_t, + base: *const i64, + indices: svint64_t, + ) -> svint64_t; + } + _svld1_gather_s64index_s64(pg.sve_into(), base, indices) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_s64index_u64( + pg: svbool_t, + base: *const u64, + indices: svint64_t, +) -> svuint64_t { + svld1_gather_s64index_s64(pg, base.as_signed(), indices).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32index_f32( + pg: svbool_t, + base: *const f32, + indices: svuint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4f32" + )] + fn _svld1_gather_u32index_f32( + pg: svbool4_t, + base: *const f32, + indices: svint32_t, + ) -> svfloat32_t; + } + _svld1_gather_u32index_f32(pg.sve_into(), base, indices.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32index_s32( + pg: svbool_t, + base: *const i32, + indices: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4i32" + )] + fn _svld1_gather_u32index_s32( + pg: svbool4_t, + base: *const i32, + indices: svint32_t, + ) -> svint32_t; + } + _svld1_gather_u32index_s32(pg.sve_into(), base, indices.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32index_u32( + pg: svbool_t, + base: *const u32, + indices: svuint32_t, +) -> svuint32_t { + svld1_gather_u32index_s32(pg, base.as_signed(), indices).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64index_f64( + pg: svbool_t, + base: *const f64, + indices: svuint64_t, +) -> svfloat64_t { + svld1_gather_s64index_f64(pg, base, indices.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64index_s64( + pg: svbool_t, + base: *const i64, + indices: svuint64_t, +) -> svint64_t { + svld1_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64index_u64( + pg: svbool_t, + base: *const u64, + indices: svuint64_t, +) -> svuint64_t { + svld1_gather_s64index_s64(pg, base.as_signed(), indices.as_signed()).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_s32offset_f32( + pg: svbool_t, + base: *const f32, + offsets: svint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4f32" + )] + fn _svld1_gather_s32offset_f32( + pg: svbool4_t, + base: *const f32, + offsets: svint32_t, + ) -> svfloat32_t; + } + _svld1_gather_s32offset_f32(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_s32offset_s32( + pg: svbool_t, + base: *const i32, + offsets: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4i32" + )] + fn _svld1_gather_s32offset_s32( + pg: svbool4_t, + base: *const i32, + offsets: svint32_t, + ) -> svint32_t; + } + _svld1_gather_s32offset_s32(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_s32offset_u32( + pg: svbool_t, + base: *const u32, + offsets: svint32_t, +) -> svuint32_t { + svld1_gather_s32offset_s32(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_s64offset_f64( + pg: svbool_t, + base: *const f64, + offsets: svint64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2f64" + )] + fn _svld1_gather_s64offset_f64( + pg: svbool2_t, + base: *const f64, + offsets: svint64_t, + ) -> svfloat64_t; + } + _svld1_gather_s64offset_f64(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_s64offset_s64( + pg: svbool_t, + base: *const i64, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2i64" + )] + fn _svld1_gather_s64offset_s64( + pg: svbool2_t, + base: *const i64, + offsets: svint64_t, + ) -> svint64_t; + } + _svld1_gather_s64offset_s64(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_s64offset_u64( + pg: svbool_t, + base: *const u64, + offsets: svint64_t, +) -> svuint64_t { + svld1_gather_s64offset_s64(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32offset_f32( + pg: svbool_t, + base: *const f32, + offsets: svuint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4f32" + )] + fn _svld1_gather_u32offset_f32( + pg: svbool4_t, + base: *const f32, + offsets: svint32_t, + ) -> svfloat32_t; + } + _svld1_gather_u32offset_f32(pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32offset_s32( + pg: svbool_t, + base: *const i32, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4i32" + )] + fn _svld1_gather_u32offset_s32( + pg: svbool4_t, + base: *const i32, + offsets: svint32_t, + ) -> svint32_t; + } + _svld1_gather_u32offset_s32(pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32offset_u32( + pg: svbool_t, + base: *const u32, + offsets: svuint32_t, +) -> svuint32_t { + svld1_gather_u32offset_s32(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64offset_f64( + pg: svbool_t, + base: *const f64, + offsets: svuint64_t, +) -> svfloat64_t { + svld1_gather_s64offset_f64(pg, base, offsets.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64offset_s64( + pg: svbool_t, + base: *const i64, + offsets: svuint64_t, +) -> svint64_t { + svld1_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64offset_u64( + pg: svbool_t, + base: *const u64, + offsets: svuint64_t, +) -> svuint64_t { + svld1_gather_s64offset_s64(pg, base.as_signed(), offsets.as_signed()).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_f32(pg: svbool_t, bases: svuint32_t) -> svfloat32_t { + svld1_gather_u32base_offset_f32(pg, bases, 0) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svld1_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svld1_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_f64(pg: svbool_t, bases: svuint64_t) -> svfloat64_t { + svld1_gather_u64base_offset_f64(pg, bases, 0) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svld1_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svld1_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_index_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_index_f32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svfloat32_t { + svld1_gather_u32base_offset_f32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svld1_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svld1_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_index_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_index_f64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svfloat64_t { + svld1_gather_u64base_offset_f64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svld1_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svld1_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_offset_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_offset_f32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4f32.nxv4i32" + )] + fn _svld1_gather_u32base_offset_f32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> svfloat32_t; + } + _svld1_gather_u32base_offset_f32(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i32.nxv4i32" + )] + fn _svld1_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> svint32_t; + } + _svld1_gather_u32base_offset_s32(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svld1_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_offset_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_offset_f64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2f64.nxv2i64" + )] + fn _svld1_gather_u64base_offset_f64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> svfloat64_t; + } + _svld1_gather_u64base_offset_f64(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i64.nxv2i64" + )] + fn _svld1_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> svint64_t; + } + _svld1_gather_u64base_offset_s64(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svld1_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32_t { + svld1_f32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64_t { + svld1_f64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8_t { + svld1_s8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16_t { + svld1_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32_t { + svld1_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64_t { + svld1_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8_t { + svld1_u8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16_t { + svld1_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32_t { + svld1_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64_t { + svld1_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1row))] +pub unsafe fn svld1ro_f32(pg: svbool_t, base: *const f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv4f32")] + fn _svld1ro_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t; + } + _svld1ro_f32(pg.sve_into(), base) +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rod))] +pub unsafe fn svld1ro_f64(pg: svbool_t, base: *const f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv2f64")] + fn _svld1ro_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t; + } + _svld1ro_f64(pg.sve_into(), base) +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rob))] +pub unsafe fn svld1ro_s8(pg: svbool_t, base: *const i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv16i8")] + fn _svld1ro_s8(pg: svbool_t, base: *const i8) -> svint8_t; + } + _svld1ro_s8(pg, base) +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1roh))] +pub unsafe fn svld1ro_s16(pg: svbool_t, base: *const i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv8i16")] + fn _svld1ro_s16(pg: svbool8_t, base: *const i16) -> svint16_t; + } + _svld1ro_s16(pg.sve_into(), base) +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1row))] +pub unsafe fn svld1ro_s32(pg: svbool_t, base: *const i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv4i32")] + fn _svld1ro_s32(pg: svbool4_t, base: *const i32) -> svint32_t; + } + _svld1ro_s32(pg.sve_into(), base) +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rod))] +pub unsafe fn svld1ro_s64(pg: svbool_t, base: *const i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv2i64")] + fn _svld1ro_s64(pg: svbool2_t, base: *const i64) -> svint64_t; + } + _svld1ro_s64(pg.sve_into(), base) +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rob))] +pub unsafe fn svld1ro_u8(pg: svbool_t, base: *const u8) -> svuint8_t { + svld1ro_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1roh))] +pub unsafe fn svld1ro_u16(pg: svbool_t, base: *const u16) -> svuint16_t { + svld1ro_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1row))] +pub unsafe fn svld1ro_u32(pg: svbool_t, base: *const u32) -> svuint32_t { + svld1ro_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rod))] +pub unsafe fn svld1ro_u64(pg: svbool_t, base: *const u64) -> svuint64_t { + svld1ro_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqw))] +pub unsafe fn svld1rq_f32(pg: svbool_t, base: *const f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv4f32")] + fn _svld1rq_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t; + } + _svld1rq_f32(pg.sve_into(), base) +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqd))] +pub unsafe fn svld1rq_f64(pg: svbool_t, base: *const f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv2f64")] + fn _svld1rq_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t; + } + _svld1rq_f64(pg.sve_into(), base) +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqb))] +pub unsafe fn svld1rq_s8(pg: svbool_t, base: *const i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv16i8")] + fn _svld1rq_s8(pg: svbool_t, base: *const i8) -> svint8_t; + } + _svld1rq_s8(pg, base) +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqh))] +pub unsafe fn svld1rq_s16(pg: svbool_t, base: *const i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv8i16")] + fn _svld1rq_s16(pg: svbool8_t, base: *const i16) -> svint16_t; + } + _svld1rq_s16(pg.sve_into(), base) +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqw))] +pub unsafe fn svld1rq_s32(pg: svbool_t, base: *const i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv4i32")] + fn _svld1rq_s32(pg: svbool4_t, base: *const i32) -> svint32_t; + } + _svld1rq_s32(pg.sve_into(), base) +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqd))] +pub unsafe fn svld1rq_s64(pg: svbool_t, base: *const i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv2i64")] + fn _svld1rq_s64(pg: svbool2_t, base: *const i64) -> svint64_t; + } + _svld1rq_s64(pg.sve_into(), base) +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqb))] +pub unsafe fn svld1rq_u8(pg: svbool_t, base: *const u8) -> svuint8_t { + svld1rq_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqh))] +pub unsafe fn svld1rq_u16(pg: svbool_t, base: *const u16) -> svuint16_t { + svld1rq_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqw))] +pub unsafe fn svld1rq_u32(pg: svbool_t, base: *const u32) -> svuint32_t { + svld1rq_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqd))] +pub unsafe fn svld1rq_u64(pg: svbool_t, base: *const u64) -> svuint64_t { + svld1rq_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_s32offset_s32( + pg: svbool_t, + base: *const i8, + offsets: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4i8" + )] + fn _svld1sb_gather_s32offset_s32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_gather_s32offset_s32(pg.sve_into(), base, offsets)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s32offset_s32( + pg: svbool_t, + base: *const i16, + offsets: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4i16" + )] + fn _svld1sh_gather_s32offset_s32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_s32offset_s32(pg.sve_into(), base, offsets)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_s32offset_u32( + pg: svbool_t, + base: *const i8, + offsets: svint32_t, +) -> svuint32_t { + svld1sb_gather_s32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s32offset_u32( + pg: svbool_t, + base: *const i16, + offsets: svint32_t, +) -> svuint32_t { + svld1sh_gather_s32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_s64offset_s64( + pg: svbool_t, + base: *const i8, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2i8" + )] + fn _svld1sb_gather_s64offset_s64( + pg: svbool2_t, + base: *const i8, + offsets: svint64_t, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_gather_s64offset_s64(pg.sve_into(), base, offsets)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s64offset_s64( + pg: svbool_t, + base: *const i16, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2i16" + )] + fn _svld1sh_gather_s64offset_s64( + pg: svbool2_t, + base: *const i16, + offsets: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_s64offset_s64(pg.sve_into(), base, offsets)) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_s64offset_s64( + pg: svbool_t, + base: *const i32, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2i32" + )] + fn _svld1sw_gather_s64offset_s64( + pg: svbool2_t, + base: *const i32, + offsets: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svld1sw_gather_s64offset_s64(pg.sve_into(), base, offsets)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_s64offset_u64( + pg: svbool_t, + base: *const i8, + offsets: svint64_t, +) -> svuint64_t { + svld1sb_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s64offset_u64( + pg: svbool_t, + base: *const i16, + offsets: svint64_t, +) -> svuint64_t { + svld1sh_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_s64offset_u64( + pg: svbool_t, + base: *const i32, + offsets: svint64_t, +) -> svuint64_t { + svld1sw_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u32offset_s32( + pg: svbool_t, + base: *const i8, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4i8" + )] + fn _svld1sb_gather_u32offset_s32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_gather_u32offset_s32( + pg.sve_into(), + base, + offsets.as_signed(), + )) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32offset_s32( + pg: svbool_t, + base: *const i16, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4i16" + )] + fn _svld1sh_gather_u32offset_s32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_u32offset_s32( + pg.sve_into(), + base, + offsets.as_signed(), + )) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u32offset_u32( + pg: svbool_t, + base: *const i8, + offsets: svuint32_t, +) -> svuint32_t { + svld1sb_gather_u32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32offset_u32( + pg: svbool_t, + base: *const i16, + offsets: svuint32_t, +) -> svuint32_t { + svld1sh_gather_u32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u64offset_s64( + pg: svbool_t, + base: *const i8, + offsets: svuint64_t, +) -> svint64_t { + svld1sb_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64offset_s64( + pg: svbool_t, + base: *const i16, + offsets: svuint64_t, +) -> svint64_t { + svld1sh_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64offset_s64( + pg: svbool_t, + base: *const i32, + offsets: svuint64_t, +) -> svint64_t { + svld1sw_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u64offset_u64( + pg: svbool_t, + base: *const i8, + offsets: svuint64_t, +) -> svuint64_t { + svld1sb_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64offset_u64( + pg: svbool_t, + base: *const i16, + offsets: svuint64_t, +) -> svuint64_t { + svld1sh_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64offset_u64( + pg: svbool_t, + base: *const i32, + offsets: svuint64_t, +) -> svuint64_t { + svld1sw_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svld1sb_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_gather_u32base_offset_s32( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svld1sh_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_u32base_offset_s32( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svld1sb_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svld1sh_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svld1sb_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svld1sh_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svld1sw_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svld1sw_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svld1sb_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svld1sh_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svld1sw_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svld1sb_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svld1sh_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svld1sb_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svld1sh_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svld1sb_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svld1sh_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svld1sw_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svld1sb_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svld1sh_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svld1sw_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_s16(pg: svbool_t, base: *const i8) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv8i8")] + fn _svld1sb_s16(pg: svbool8_t, base: *const i8) -> nxv8i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_s16(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_s32(pg: svbool_t, base: *const i8) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4i8")] + fn _svld1sb_s32(pg: svbool4_t, base: *const i8) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_s32(pg.sve_into(), base)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_s32(pg: svbool_t, base: *const i16) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4i16")] + fn _svld1sh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_s32(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_s64(pg: svbool_t, base: *const i8) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i8")] + fn _svld1sb_s64(pg: svbool2_t, base: *const i8) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_s64(pg.sve_into(), base)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_s64(pg: svbool_t, base: *const i16) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i16")] + fn _svld1sh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_s64(pg.sve_into(), base)) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_s64(pg: svbool_t, base: *const i32) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i32")] + fn _svld1sw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svld1sw_s64(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_u16(pg: svbool_t, base: *const i8) -> svuint16_t { + svld1sb_s16(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_u32(pg: svbool_t, base: *const i8) -> svuint32_t { + svld1sb_s32(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_u32(pg: svbool_t, base: *const i16) -> svuint32_t { + svld1sh_s32(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_u64(pg: svbool_t, base: *const i8) -> svuint64_t { + svld1sb_s64(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_u64(pg: svbool_t, base: *const i16) -> svuint64_t { + svld1sh_s64(pg, base).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_u64(pg: svbool_t, base: *const i32) -> svuint64_t { + svld1sw_s64(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_vnum_s16(pg: svbool_t, base: *const i8, vnum: i64) -> svint16_t { + svld1sb_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_vnum_s32(pg: svbool_t, base: *const i8, vnum: i64) -> svint32_t { + svld1sb_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_vnum_s32(pg: svbool_t, base: *const i16, vnum: i64) -> svint32_t { + svld1sh_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_vnum_s64(pg: svbool_t, base: *const i8, vnum: i64) -> svint64_t { + svld1sb_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_vnum_s64(pg: svbool_t, base: *const i16, vnum: i64) -> svint64_t { + svld1sh_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_vnum_s64(pg: svbool_t, base: *const i32, vnum: i64) -> svint64_t { + svld1sw_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_vnum_u16(pg: svbool_t, base: *const i8, vnum: i64) -> svuint16_t { + svld1sb_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_vnum_u32(pg: svbool_t, base: *const i8, vnum: i64) -> svuint32_t { + svld1sb_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_vnum_u32(pg: svbool_t, base: *const i16, vnum: i64) -> svuint32_t { + svld1sh_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_vnum_u64(pg: svbool_t, base: *const i8, vnum: i64) -> svuint64_t { + svld1sb_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_vnum_u64(pg: svbool_t, base: *const i16, vnum: i64) -> svuint64_t { + svld1sh_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_vnum_u64(pg: svbool_t, base: *const i32, vnum: i64) -> svuint64_t { + svld1sw_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s32index_s32( + pg: svbool_t, + base: *const i16, + indices: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4i16" + )] + fn _svld1sh_gather_s32index_s32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_s32index_s32(pg.sve_into(), base, indices)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s32index_u32( + pg: svbool_t, + base: *const i16, + indices: svint32_t, +) -> svuint32_t { + svld1sh_gather_s32index_s32(pg, base, indices).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s64index_s64( + pg: svbool_t, + base: *const i16, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2i16" + )] + fn _svld1sh_gather_s64index_s64( + pg: svbool2_t, + base: *const i16, + indices: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_s64index_s64(pg.sve_into(), base, indices)) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_s64index_s64( + pg: svbool_t, + base: *const i32, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2i32" + )] + fn _svld1sw_gather_s64index_s64( + pg: svbool2_t, + base: *const i32, + indices: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svld1sw_gather_s64index_s64(pg.sve_into(), base, indices)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s64index_u64( + pg: svbool_t, + base: *const i16, + indices: svint64_t, +) -> svuint64_t { + svld1sh_gather_s64index_s64(pg, base, indices).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_s64index_u64( + pg: svbool_t, + base: *const i32, + indices: svint64_t, +) -> svuint64_t { + svld1sw_gather_s64index_s64(pg, base, indices).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32index_s32( + pg: svbool_t, + base: *const i16, + indices: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4i16" + )] + fn _svld1sh_gather_u32index_s32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_u32index_s32( + pg.sve_into(), + base, + indices.as_signed(), + )) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32index_u32( + pg: svbool_t, + base: *const i16, + indices: svuint32_t, +) -> svuint32_t { + svld1sh_gather_u32index_s32(pg, base, indices).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64index_s64( + pg: svbool_t, + base: *const i16, + indices: svuint64_t, +) -> svint64_t { + svld1sh_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64index_s64( + pg: svbool_t, + base: *const i32, + indices: svuint64_t, +) -> svint64_t { + svld1sw_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64index_u64( + pg: svbool_t, + base: *const i16, + indices: svuint64_t, +) -> svuint64_t { + svld1sh_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64index_u64( + pg: svbool_t, + base: *const i32, + indices: svuint64_t, +) -> svuint64_t { + svld1sw_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svld1sh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svld1sh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svld1sh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svld1sw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svld1sh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svld1sw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_s32offset_s32( + pg: svbool_t, + base: *const u8, + offsets: svint32_t, +) -> svint32_t { + svld1ub_gather_s32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s32offset_s32( + pg: svbool_t, + base: *const u16, + offsets: svint32_t, +) -> svint32_t { + svld1uh_gather_s32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_s32offset_u32( + pg: svbool_t, + base: *const u8, + offsets: svint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4i8" + )] + fn _svld1ub_gather_s32offset_u32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_gather_s32offset_u32(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s32offset_u32( + pg: svbool_t, + base: *const u16, + offsets: svint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4i16" + )] + fn _svld1uh_gather_s32offset_u32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_s32offset_u32(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_s64offset_s64( + pg: svbool_t, + base: *const u8, + offsets: svint64_t, +) -> svint64_t { + svld1ub_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s64offset_s64( + pg: svbool_t, + base: *const u16, + offsets: svint64_t, +) -> svint64_t { + svld1uh_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_s64offset_s64( + pg: svbool_t, + base: *const u32, + offsets: svint64_t, +) -> svint64_t { + svld1uw_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_s64offset_u64( + pg: svbool_t, + base: *const u8, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2i8" + )] + fn _svld1ub_gather_s64offset_u64( + pg: svbool2_t, + base: *const i8, + offsets: svint64_t, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s64offset_u64( + pg: svbool_t, + base: *const u16, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2i16" + )] + fn _svld1uh_gather_s64offset_u64( + pg: svbool2_t, + base: *const i16, + offsets: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_s64offset_u64( + pg: svbool_t, + base: *const u32, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2i32" + )] + fn _svld1uw_gather_s64offset_u64( + pg: svbool2_t, + base: *const i32, + offsets: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svld1uw_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u32offset_s32( + pg: svbool_t, + base: *const u8, + offsets: svuint32_t, +) -> svint32_t { + svld1ub_gather_u32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32offset_s32( + pg: svbool_t, + base: *const u16, + offsets: svuint32_t, +) -> svint32_t { + svld1uh_gather_u32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u32offset_u32( + pg: svbool_t, + base: *const u8, + offsets: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4i8" + )] + fn _svld1ub_gather_u32offset_u32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32offset_u32( + pg: svbool_t, + base: *const u16, + offsets: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4i16" + )] + fn _svld1uh_gather_u32offset_u32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u64offset_s64( + pg: svbool_t, + base: *const u8, + offsets: svuint64_t, +) -> svint64_t { + svld1ub_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64offset_s64( + pg: svbool_t, + base: *const u16, + offsets: svuint64_t, +) -> svint64_t { + svld1uh_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64offset_s64( + pg: svbool_t, + base: *const u32, + offsets: svuint64_t, +) -> svint64_t { + svld1uw_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u64offset_u64( + pg: svbool_t, + base: *const u8, + offsets: svuint64_t, +) -> svuint64_t { + svld1ub_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64offset_u64( + pg: svbool_t, + base: *const u16, + offsets: svuint64_t, +) -> svuint64_t { + svld1uh_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64offset_u64( + pg: svbool_t, + base: *const u32, + offsets: svuint64_t, +) -> svuint64_t { + svld1uw_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + svld1ub_gather_u32base_offset_u32(pg, bases, offset).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + svld1uh_gather_u32base_offset_u32(pg, bases, offset).as_signed() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svld1ub_gather_u32base_offset_u32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svld1uh_gather_u32base_offset_u32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svld1ub_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svld1uh_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svld1uw_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svld1ub_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svld1uh_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svld1uw_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svld1uw_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svld1ub_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svld1uh_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svld1ub_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svld1uh_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svld1ub_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svld1uh_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svld1uw_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svld1ub_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svld1uh_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svld1uw_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_s16(pg: svbool_t, base: *const u8) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv8i8")] + fn _svld1ub_s16(pg: svbool8_t, base: *const i8) -> nxv8i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_s16(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_s32(pg: svbool_t, base: *const u8) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4i8")] + fn _svld1ub_s32(pg: svbool4_t, base: *const i8) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_s32(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_s32(pg: svbool_t, base: *const u16) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4i16")] + fn _svld1uh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_s32(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_s64(pg: svbool_t, base: *const u8) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i8")] + fn _svld1ub_s64(pg: svbool2_t, base: *const i8) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_s64(pg: svbool_t, base: *const u16) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i16")] + fn _svld1uh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_s64(pg: svbool_t, base: *const u32) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i32")] + fn _svld1uw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svld1uw_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_u16(pg: svbool_t, base: *const u8) -> svuint16_t { + svld1ub_s16(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_u32(pg: svbool_t, base: *const u8) -> svuint32_t { + svld1ub_s32(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_u32(pg: svbool_t, base: *const u16) -> svuint32_t { + svld1uh_s32(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_u64(pg: svbool_t, base: *const u8) -> svuint64_t { + svld1ub_s64(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_u64(pg: svbool_t, base: *const u16) -> svuint64_t { + svld1uh_s64(pg, base).as_unsigned() +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_u64(pg: svbool_t, base: *const u32) -> svuint64_t { + svld1uw_s64(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_vnum_s16(pg: svbool_t, base: *const u8, vnum: i64) -> svint16_t { + svld1ub_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_vnum_s32(pg: svbool_t, base: *const u8, vnum: i64) -> svint32_t { + svld1ub_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_vnum_s32(pg: svbool_t, base: *const u16, vnum: i64) -> svint32_t { + svld1uh_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_vnum_s64(pg: svbool_t, base: *const u8, vnum: i64) -> svint64_t { + svld1ub_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_vnum_s64(pg: svbool_t, base: *const u16, vnum: i64) -> svint64_t { + svld1uh_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_vnum_s64(pg: svbool_t, base: *const u32, vnum: i64) -> svint64_t { + svld1uw_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_vnum_u16(pg: svbool_t, base: *const u8, vnum: i64) -> svuint16_t { + svld1ub_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_vnum_u32(pg: svbool_t, base: *const u8, vnum: i64) -> svuint32_t { + svld1ub_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_vnum_u32(pg: svbool_t, base: *const u16, vnum: i64) -> svuint32_t { + svld1uh_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_vnum_u64(pg: svbool_t, base: *const u8, vnum: i64) -> svuint64_t { + svld1ub_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_vnum_u64(pg: svbool_t, base: *const u16, vnum: i64) -> svuint64_t { + svld1uh_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_vnum_u64(pg: svbool_t, base: *const u32, vnum: i64) -> svuint64_t { + svld1uw_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s32index_s32( + pg: svbool_t, + base: *const u16, + indices: svint32_t, +) -> svint32_t { + svld1uh_gather_s32index_u32(pg, base, indices).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s32index_u32( + pg: svbool_t, + base: *const u16, + indices: svint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4i16" + )] + fn _svld1uh_gather_s32index_u32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_s32index_u32(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s64index_s64( + pg: svbool_t, + base: *const u16, + indices: svint64_t, +) -> svint64_t { + svld1uh_gather_s64index_u64(pg, base, indices).as_signed() +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_s64index_s64( + pg: svbool_t, + base: *const u32, + indices: svint64_t, +) -> svint64_t { + svld1uw_gather_s64index_u64(pg, base, indices).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s64index_u64( + pg: svbool_t, + base: *const u16, + indices: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2i16" + )] + fn _svld1uh_gather_s64index_u64( + pg: svbool2_t, + base: *const i16, + indices: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_s64index_u64( + pg: svbool_t, + base: *const u32, + indices: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2i32" + )] + fn _svld1uw_gather_s64index_u64( + pg: svbool2_t, + base: *const i32, + indices: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svld1uw_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32index_s32( + pg: svbool_t, + base: *const u16, + indices: svuint32_t, +) -> svint32_t { + svld1uh_gather_u32index_u32(pg, base, indices).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32index_u32( + pg: svbool_t, + base: *const u16, + indices: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4i16" + )] + fn _svld1uh_gather_u32index_u32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_u32index_u32(pg.sve_into(), base.as_signed(), indices.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64index_s64( + pg: svbool_t, + base: *const u16, + indices: svuint64_t, +) -> svint64_t { + svld1uh_gather_s64index_u64(pg, base, indices.as_signed()).as_signed() +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64index_s64( + pg: svbool_t, + base: *const u32, + indices: svuint64_t, +) -> svint64_t { + svld1uw_gather_s64index_u64(pg, base, indices.as_signed()).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64index_u64( + pg: svbool_t, + base: *const u16, + indices: svuint64_t, +) -> svuint64_t { + svld1uh_gather_s64index_u64(pg, base, indices.as_signed()) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64index_u64( + pg: svbool_t, + base: *const u32, + indices: svuint64_t, +) -> svuint64_t { + svld1uw_gather_s64index_u64(pg, base, indices.as_signed()) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svld1uh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svld1uh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svld1uh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svld1uw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svld1uh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svld1uw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2w))] +pub unsafe fn svld2_f32(pg: svbool_t, base: *const f32) -> svfloat32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld2.sret.nxv4f32" + )] + fn _svld2_f32(pg: svbool4_t, base: *const f32) -> svfloat32x2_t; + } + _svld2_f32(pg.sve_into(), base) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2d))] +pub unsafe fn svld2_f64(pg: svbool_t, base: *const f64) -> svfloat64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld2.sret.nxv2f64" + )] + fn _svld2_f64(pg: svbool2_t, base: *const f64) -> svfloat64x2_t; + } + _svld2_f64(pg.sve_into(), base) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2b))] +pub unsafe fn svld2_s8(pg: svbool_t, base: *const i8) -> svint8x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld2.sret.nxv16i8" + )] + fn _svld2_s8(pg: svbool_t, base: *const i8) -> svint8x2_t; + } + _svld2_s8(pg, base) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2h))] +pub unsafe fn svld2_s16(pg: svbool_t, base: *const i16) -> svint16x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld2.sret.nxv8i16" + )] + fn _svld2_s16(pg: svbool8_t, base: *const i16) -> svint16x2_t; + } + _svld2_s16(pg.sve_into(), base) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2w))] +pub unsafe fn svld2_s32(pg: svbool_t, base: *const i32) -> svint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld2.sret.nxv4i32" + )] + fn _svld2_s32(pg: svbool4_t, base: *const i32) -> svint32x2_t; + } + _svld2_s32(pg.sve_into(), base) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2d))] +pub unsafe fn svld2_s64(pg: svbool_t, base: *const i64) -> svint64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld2.sret.nxv2i64" + )] + fn _svld2_s64(pg: svbool2_t, base: *const i64) -> svint64x2_t; + } + _svld2_s64(pg.sve_into(), base) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2b))] +pub unsafe fn svld2_u8(pg: svbool_t, base: *const u8) -> svuint8x2_t { + svld2_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2h))] +pub unsafe fn svld2_u16(pg: svbool_t, base: *const u16) -> svuint16x2_t { + svld2_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2w))] +pub unsafe fn svld2_u32(pg: svbool_t, base: *const u32) -> svuint32x2_t { + svld2_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2d))] +pub unsafe fn svld2_u64(pg: svbool_t, base: *const u64) -> svuint64x2_t { + svld2_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2w))] +pub unsafe fn svld2_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32x2_t { + svld2_f32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2d))] +pub unsafe fn svld2_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64x2_t { + svld2_f64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2b))] +pub unsafe fn svld2_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8x2_t { + svld2_s8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2h))] +pub unsafe fn svld2_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16x2_t { + svld2_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2w))] +pub unsafe fn svld2_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32x2_t { + svld2_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2d))] +pub unsafe fn svld2_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64x2_t { + svld2_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2b))] +pub unsafe fn svld2_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8x2_t { + svld2_u8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2h))] +pub unsafe fn svld2_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16x2_t { + svld2_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2w))] +pub unsafe fn svld2_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32x2_t { + svld2_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2d))] +pub unsafe fn svld2_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64x2_t { + svld2_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3w))] +pub unsafe fn svld3_f32(pg: svbool_t, base: *const f32) -> svfloat32x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld3.sret.nxv4f32" + )] + fn _svld3_f32(pg: svbool4_t, base: *const f32) -> svfloat32x3_t; + } + _svld3_f32(pg.sve_into(), base) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3d))] +pub unsafe fn svld3_f64(pg: svbool_t, base: *const f64) -> svfloat64x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld3.sret.nxv2f64" + )] + fn _svld3_f64(pg: svbool2_t, base: *const f64) -> svfloat64x3_t; + } + _svld3_f64(pg.sve_into(), base) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3b))] +pub unsafe fn svld3_s8(pg: svbool_t, base: *const i8) -> svint8x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld3.sret.nxv16i8" + )] + fn _svld3_s8(pg: svbool_t, base: *const i8) -> svint8x3_t; + } + _svld3_s8(pg, base) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3h))] +pub unsafe fn svld3_s16(pg: svbool_t, base: *const i16) -> svint16x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld3.sret.nxv8i16" + )] + fn _svld3_s16(pg: svbool8_t, base: *const i16) -> svint16x3_t; + } + _svld3_s16(pg.sve_into(), base) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3w))] +pub unsafe fn svld3_s32(pg: svbool_t, base: *const i32) -> svint32x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld3.sret.nxv4i32" + )] + fn _svld3_s32(pg: svbool4_t, base: *const i32) -> svint32x3_t; + } + _svld3_s32(pg.sve_into(), base) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3d))] +pub unsafe fn svld3_s64(pg: svbool_t, base: *const i64) -> svint64x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld3.sret.nxv2i64" + )] + fn _svld3_s64(pg: svbool2_t, base: *const i64) -> svint64x3_t; + } + _svld3_s64(pg.sve_into(), base) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3b))] +pub unsafe fn svld3_u8(pg: svbool_t, base: *const u8) -> svuint8x3_t { + svld3_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3h))] +pub unsafe fn svld3_u16(pg: svbool_t, base: *const u16) -> svuint16x3_t { + svld3_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3w))] +pub unsafe fn svld3_u32(pg: svbool_t, base: *const u32) -> svuint32x3_t { + svld3_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3d))] +pub unsafe fn svld3_u64(pg: svbool_t, base: *const u64) -> svuint64x3_t { + svld3_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3w))] +pub unsafe fn svld3_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32x3_t { + svld3_f32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3d))] +pub unsafe fn svld3_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64x3_t { + svld3_f64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3b))] +pub unsafe fn svld3_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8x3_t { + svld3_s8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3h))] +pub unsafe fn svld3_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16x3_t { + svld3_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3w))] +pub unsafe fn svld3_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32x3_t { + svld3_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3d))] +pub unsafe fn svld3_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64x3_t { + svld3_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3b))] +pub unsafe fn svld3_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8x3_t { + svld3_u8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3h))] +pub unsafe fn svld3_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16x3_t { + svld3_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3w))] +pub unsafe fn svld3_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32x3_t { + svld3_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3d))] +pub unsafe fn svld3_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64x3_t { + svld3_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4w))] +pub unsafe fn svld4_f32(pg: svbool_t, base: *const f32) -> svfloat32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld4.sret.nxv4f32" + )] + fn _svld4_f32(pg: svbool4_t, base: *const f32) -> svfloat32x4_t; + } + _svld4_f32(pg.sve_into(), base) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4d))] +pub unsafe fn svld4_f64(pg: svbool_t, base: *const f64) -> svfloat64x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld4.sret.nxv2f64" + )] + fn _svld4_f64(pg: svbool2_t, base: *const f64) -> svfloat64x4_t; + } + _svld4_f64(pg.sve_into(), base) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4b))] +pub unsafe fn svld4_s8(pg: svbool_t, base: *const i8) -> svint8x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld4.sret.nxv16i8" + )] + fn _svld4_s8(pg: svbool_t, base: *const i8) -> svint8x4_t; + } + _svld4_s8(pg, base) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4h))] +pub unsafe fn svld4_s16(pg: svbool_t, base: *const i16) -> svint16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld4.sret.nxv8i16" + )] + fn _svld4_s16(pg: svbool8_t, base: *const i16) -> svint16x4_t; + } + _svld4_s16(pg.sve_into(), base) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4w))] +pub unsafe fn svld4_s32(pg: svbool_t, base: *const i32) -> svint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld4.sret.nxv4i32" + )] + fn _svld4_s32(pg: svbool4_t, base: *const i32) -> svint32x4_t; + } + _svld4_s32(pg.sve_into(), base) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4d))] +pub unsafe fn svld4_s64(pg: svbool_t, base: *const i64) -> svint64x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld4.sret.nxv2i64" + )] + fn _svld4_s64(pg: svbool2_t, base: *const i64) -> svint64x4_t; + } + _svld4_s64(pg.sve_into(), base) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4b))] +pub unsafe fn svld4_u8(pg: svbool_t, base: *const u8) -> svuint8x4_t { + svld4_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4h))] +pub unsafe fn svld4_u16(pg: svbool_t, base: *const u16) -> svuint16x4_t { + svld4_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4w))] +pub unsafe fn svld4_u32(pg: svbool_t, base: *const u32) -> svuint32x4_t { + svld4_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4d))] +pub unsafe fn svld4_u64(pg: svbool_t, base: *const u64) -> svuint64x4_t { + svld4_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4w))] +pub unsafe fn svld4_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32x4_t { + svld4_f32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4d))] +pub unsafe fn svld4_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64x4_t { + svld4_f64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4b))] +pub unsafe fn svld4_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8x4_t { + svld4_s8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4h))] +pub unsafe fn svld4_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16x4_t { + svld4_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4w))] +pub unsafe fn svld4_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32x4_t { + svld4_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4d))] +pub unsafe fn svld4_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64x4_t { + svld4_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4b))] +pub unsafe fn svld4_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8x4_t { + svld4_u8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4h))] +pub unsafe fn svld4_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16x4_t { + svld4_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4w))] +pub unsafe fn svld4_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32x4_t { + svld4_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4d))] +pub unsafe fn svld4_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64x4_t { + svld4_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_f32(pg: svbool_t, base: *const f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4f32")] + fn _svldff1_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t; + } + _svldff1_f32(pg.sve_into(), base) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_f64(pg: svbool_t, base: *const f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2f64")] + fn _svldff1_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t; + } + _svldff1_f64(pg.sve_into(), base) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1_s8(pg: svbool_t, base: *const i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv16i8")] + fn _svldff1_s8(pg: svbool_t, base: *const i8) -> svint8_t; + } + _svldff1_s8(pg, base) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1_s16(pg: svbool_t, base: *const i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv8i16")] + fn _svldff1_s16(pg: svbool8_t, base: *const i16) -> svint16_t; + } + _svldff1_s16(pg.sve_into(), base) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_s32(pg: svbool_t, base: *const i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4i32")] + fn _svldff1_s32(pg: svbool4_t, base: *const i32) -> svint32_t; + } + _svldff1_s32(pg.sve_into(), base) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_s64(pg: svbool_t, base: *const i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i64")] + fn _svldff1_s64(pg: svbool2_t, base: *const i64) -> svint64_t; + } + _svldff1_s64(pg.sve_into(), base) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1_u8(pg: svbool_t, base: *const u8) -> svuint8_t { + svldff1_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1_u16(pg: svbool_t, base: *const u16) -> svuint16_t { + svldff1_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_u32(pg: svbool_t, base: *const u32) -> svuint32_t { + svldff1_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_u64(pg: svbool_t, base: *const u64) -> svuint64_t { + svldff1_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_s32index_f32( + pg: svbool_t, + base: *const f32, + indices: svint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4f32" + )] + fn _svldff1_gather_s32index_f32( + pg: svbool4_t, + base: *const f32, + indices: svint32_t, + ) -> svfloat32_t; + } + _svldff1_gather_s32index_f32(pg.sve_into(), base, indices) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_s32index_s32( + pg: svbool_t, + base: *const i32, + indices: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i32" + )] + fn _svldff1_gather_s32index_s32( + pg: svbool4_t, + base: *const i32, + indices: svint32_t, + ) -> svint32_t; + } + _svldff1_gather_s32index_s32(pg.sve_into(), base, indices) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_s32index_u32( + pg: svbool_t, + base: *const u32, + indices: svint32_t, +) -> svuint32_t { + svldff1_gather_s32index_s32(pg, base.as_signed(), indices).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_s64index_f64( + pg: svbool_t, + base: *const f64, + indices: svint64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2f64" + )] + fn _svldff1_gather_s64index_f64( + pg: svbool2_t, + base: *const f64, + indices: svint64_t, + ) -> svfloat64_t; + } + _svldff1_gather_s64index_f64(pg.sve_into(), base, indices) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_s64index_s64( + pg: svbool_t, + base: *const i64, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2i64" + )] + fn _svldff1_gather_s64index_s64( + pg: svbool2_t, + base: *const i64, + indices: svint64_t, + ) -> svint64_t; + } + _svldff1_gather_s64index_s64(pg.sve_into(), base, indices) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_s64index_u64( + pg: svbool_t, + base: *const u64, + indices: svint64_t, +) -> svuint64_t { + svldff1_gather_s64index_s64(pg, base.as_signed(), indices).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32index_f32( + pg: svbool_t, + base: *const f32, + indices: svuint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4f32" + )] + fn _svldff1_gather_u32index_f32( + pg: svbool4_t, + base: *const f32, + indices: svint32_t, + ) -> svfloat32_t; + } + _svldff1_gather_u32index_f32(pg.sve_into(), base, indices.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32index_s32( + pg: svbool_t, + base: *const i32, + indices: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4i32" + )] + fn _svldff1_gather_u32index_s32( + pg: svbool4_t, + base: *const i32, + indices: svint32_t, + ) -> svint32_t; + } + _svldff1_gather_u32index_s32(pg.sve_into(), base, indices.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32index_u32( + pg: svbool_t, + base: *const u32, + indices: svuint32_t, +) -> svuint32_t { + svldff1_gather_u32index_s32(pg, base.as_signed(), indices).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64index_f64( + pg: svbool_t, + base: *const f64, + indices: svuint64_t, +) -> svfloat64_t { + svldff1_gather_s64index_f64(pg, base, indices.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64index_s64( + pg: svbool_t, + base: *const i64, + indices: svuint64_t, +) -> svint64_t { + svldff1_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64index_u64( + pg: svbool_t, + base: *const u64, + indices: svuint64_t, +) -> svuint64_t { + svldff1_gather_s64index_s64(pg, base.as_signed(), indices.as_signed()).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_s32offset_f32( + pg: svbool_t, + base: *const f32, + offsets: svint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4f32" + )] + fn _svldff1_gather_s32offset_f32( + pg: svbool4_t, + base: *const f32, + offsets: svint32_t, + ) -> svfloat32_t; + } + _svldff1_gather_s32offset_f32(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_s32offset_s32( + pg: svbool_t, + base: *const i32, + offsets: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i32" + )] + fn _svldff1_gather_s32offset_s32( + pg: svbool4_t, + base: *const i32, + offsets: svint32_t, + ) -> svint32_t; + } + _svldff1_gather_s32offset_s32(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_s32offset_u32( + pg: svbool_t, + base: *const u32, + offsets: svint32_t, +) -> svuint32_t { + svldff1_gather_s32offset_s32(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_s64offset_f64( + pg: svbool_t, + base: *const f64, + offsets: svint64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2f64" + )] + fn _svldff1_gather_s64offset_f64( + pg: svbool2_t, + base: *const f64, + offsets: svint64_t, + ) -> svfloat64_t; + } + _svldff1_gather_s64offset_f64(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_s64offset_s64( + pg: svbool_t, + base: *const i64, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i64" + )] + fn _svldff1_gather_s64offset_s64( + pg: svbool2_t, + base: *const i64, + offsets: svint64_t, + ) -> svint64_t; + } + _svldff1_gather_s64offset_s64(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_s64offset_u64( + pg: svbool_t, + base: *const u64, + offsets: svint64_t, +) -> svuint64_t { + svldff1_gather_s64offset_s64(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32offset_f32( + pg: svbool_t, + base: *const f32, + offsets: svuint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4f32" + )] + fn _svldff1_gather_u32offset_f32( + pg: svbool4_t, + base: *const f32, + offsets: svint32_t, + ) -> svfloat32_t; + } + _svldff1_gather_u32offset_f32(pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32offset_s32( + pg: svbool_t, + base: *const i32, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i32" + )] + fn _svldff1_gather_u32offset_s32( + pg: svbool4_t, + base: *const i32, + offsets: svint32_t, + ) -> svint32_t; + } + _svldff1_gather_u32offset_s32(pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32offset_u32( + pg: svbool_t, + base: *const u32, + offsets: svuint32_t, +) -> svuint32_t { + svldff1_gather_u32offset_s32(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64offset_f64( + pg: svbool_t, + base: *const f64, + offsets: svuint64_t, +) -> svfloat64_t { + svldff1_gather_s64offset_f64(pg, base, offsets.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64offset_s64( + pg: svbool_t, + base: *const i64, + offsets: svuint64_t, +) -> svint64_t { + svldff1_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64offset_u64( + pg: svbool_t, + base: *const u64, + offsets: svuint64_t, +) -> svuint64_t { + svldff1_gather_s64offset_s64(pg, base.as_signed(), offsets.as_signed()).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_f32(pg: svbool_t, bases: svuint32_t) -> svfloat32_t { + svldff1_gather_u32base_offset_f32(pg, bases, 0) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldff1_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldff1_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_f64(pg: svbool_t, bases: svuint64_t) -> svfloat64_t { + svldff1_gather_u64base_offset_f64(pg, bases, 0) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldff1_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldff1_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_index_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_index_f32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svfloat32_t { + svldff1_gather_u32base_offset_f32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svldff1_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svldff1_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_index_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_index_f64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svfloat64_t { + svldff1_gather_u64base_offset_f64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldff1_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldff1_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_offset_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_offset_f32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4f32.nxv4i32" + )] + fn _svldff1_gather_u32base_offset_f32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> svfloat32_t; + } + _svldff1_gather_u32base_offset_f32(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i32.nxv4i32" + )] + fn _svldff1_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> svint32_t; + } + _svldff1_gather_u32base_offset_s32(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svldff1_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_offset_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_offset_f64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2f64.nxv2i64" + )] + fn _svldff1_gather_u64base_offset_f64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> svfloat64_t; + } + _svldff1_gather_u64base_offset_f64(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i64.nxv2i64" + )] + fn _svldff1_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> svint64_t; + } + _svldff1_gather_u64base_offset_s64(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldff1_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32_t { + svldff1_f32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64_t { + svldff1_f64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8_t { + svldff1_s8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16_t { + svldff1_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32_t { + svldff1_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64_t { + svldff1_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8_t { + svldff1_u8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16_t { + svldff1_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32_t { + svldff1_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64_t { + svldff1_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_s32offset_s32( + pg: svbool_t, + base: *const i8, + offsets: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i8" + )] + fn _svldff1sb_gather_s32offset_s32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_gather_s32offset_s32( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s32offset_s32( + pg: svbool_t, + base: *const i16, + offsets: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i16" + )] + fn _svldff1sh_gather_s32offset_s32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_s32offset_s32( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_s32offset_u32( + pg: svbool_t, + base: *const i8, + offsets: svint32_t, +) -> svuint32_t { + svldff1sb_gather_s32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s32offset_u32( + pg: svbool_t, + base: *const i16, + offsets: svint32_t, +) -> svuint32_t { + svldff1sh_gather_s32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_s64offset_s64( + pg: svbool_t, + base: *const i8, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i8" + )] + fn _svldff1sb_gather_s64offset_s64( + pg: svbool2_t, + base: *const i8, + offsets: svint64_t, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_gather_s64offset_s64( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s64offset_s64( + pg: svbool_t, + base: *const i16, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i16" + )] + fn _svldff1sh_gather_s64offset_s64( + pg: svbool2_t, + base: *const i16, + offsets: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_s64offset_s64( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_s64offset_s64( + pg: svbool_t, + base: *const i32, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i32" + )] + fn _svldff1sw_gather_s64offset_s64( + pg: svbool2_t, + base: *const i32, + offsets: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldff1sw_gather_s64offset_s64( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_s64offset_u64( + pg: svbool_t, + base: *const i8, + offsets: svint64_t, +) -> svuint64_t { + svldff1sb_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s64offset_u64( + pg: svbool_t, + base: *const i16, + offsets: svint64_t, +) -> svuint64_t { + svldff1sh_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_s64offset_u64( + pg: svbool_t, + base: *const i32, + offsets: svint64_t, +) -> svuint64_t { + svldff1sw_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u32offset_s32( + pg: svbool_t, + base: *const i8, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i8" + )] + fn _svldff1sb_gather_u32offset_s32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_gather_u32offset_s32( + pg.sve_into(), + base, + offsets.as_signed(), + )) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32offset_s32( + pg: svbool_t, + base: *const i16, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i16" + )] + fn _svldff1sh_gather_u32offset_s32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_u32offset_s32( + pg.sve_into(), + base, + offsets.as_signed(), + )) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u32offset_u32( + pg: svbool_t, + base: *const i8, + offsets: svuint32_t, +) -> svuint32_t { + svldff1sb_gather_u32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32offset_u32( + pg: svbool_t, + base: *const i16, + offsets: svuint32_t, +) -> svuint32_t { + svldff1sh_gather_u32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u64offset_s64( + pg: svbool_t, + base: *const i8, + offsets: svuint64_t, +) -> svint64_t { + svldff1sb_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64offset_s64( + pg: svbool_t, + base: *const i16, + offsets: svuint64_t, +) -> svint64_t { + svldff1sh_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64offset_s64( + pg: svbool_t, + base: *const i32, + offsets: svuint64_t, +) -> svint64_t { + svldff1sw_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u64offset_u64( + pg: svbool_t, + base: *const i8, + offsets: svuint64_t, +) -> svuint64_t { + svldff1sb_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64offset_u64( + pg: svbool_t, + base: *const i16, + offsets: svuint64_t, +) -> svuint64_t { + svldff1sh_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64offset_u64( + pg: svbool_t, + base: *const i32, + offsets: svuint64_t, +) -> svuint64_t { + svldff1sw_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svldff1sb_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_gather_u32base_offset_s32( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svldff1sh_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_u32base_offset_s32( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svldff1sb_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svldff1sh_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svldff1sb_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svldff1sh_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svldff1sw_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldff1sw_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldff1sb_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldff1sh_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldff1sw_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldff1sb_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldff1sh_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldff1sb_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldff1sh_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldff1sb_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldff1sh_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldff1sw_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldff1sb_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldff1sh_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldff1sw_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_s16(pg: svbool_t, base: *const i8) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv8i8")] + fn _svldff1sb_s16(pg: svbool8_t, base: *const i8) -> nxv8i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_s16(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_s32(pg: svbool_t, base: *const i8) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4i8")] + fn _svldff1sb_s32(pg: svbool4_t, base: *const i8) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_s32(pg.sve_into(), base)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_s32(pg: svbool_t, base: *const i16) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4i16")] + fn _svldff1sh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_s32(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_s64(pg: svbool_t, base: *const i8) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i8")] + fn _svldff1sb_s64(pg: svbool2_t, base: *const i8) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_s64(pg.sve_into(), base)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_s64(pg: svbool_t, base: *const i16) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i16")] + fn _svldff1sh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_s64(pg.sve_into(), base)) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_s64(pg: svbool_t, base: *const i32) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i32")] + fn _svldff1sw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldff1sw_s64(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_u16(pg: svbool_t, base: *const i8) -> svuint16_t { + svldff1sb_s16(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_u32(pg: svbool_t, base: *const i8) -> svuint32_t { + svldff1sb_s32(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_u32(pg: svbool_t, base: *const i16) -> svuint32_t { + svldff1sh_s32(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_u64(pg: svbool_t, base: *const i8) -> svuint64_t { + svldff1sb_s64(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_u64(pg: svbool_t, base: *const i16) -> svuint64_t { + svldff1sh_s64(pg, base).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_u64(pg: svbool_t, base: *const i32) -> svuint64_t { + svldff1sw_s64(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_vnum_s16(pg: svbool_t, base: *const i8, vnum: i64) -> svint16_t { + svldff1sb_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_vnum_s32(pg: svbool_t, base: *const i8, vnum: i64) -> svint32_t { + svldff1sb_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_vnum_s32(pg: svbool_t, base: *const i16, vnum: i64) -> svint32_t { + svldff1sh_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_vnum_s64(pg: svbool_t, base: *const i8, vnum: i64) -> svint64_t { + svldff1sb_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_vnum_s64(pg: svbool_t, base: *const i16, vnum: i64) -> svint64_t { + svldff1sh_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_vnum_s64(pg: svbool_t, base: *const i32, vnum: i64) -> svint64_t { + svldff1sw_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_vnum_u16(pg: svbool_t, base: *const i8, vnum: i64) -> svuint16_t { + svldff1sb_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_vnum_u32(pg: svbool_t, base: *const i8, vnum: i64) -> svuint32_t { + svldff1sb_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_vnum_u32(pg: svbool_t, base: *const i16, vnum: i64) -> svuint32_t { + svldff1sh_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_vnum_u64(pg: svbool_t, base: *const i8, vnum: i64) -> svuint64_t { + svldff1sb_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_vnum_u64(pg: svbool_t, base: *const i16, vnum: i64) -> svuint64_t { + svldff1sh_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_vnum_u64(pg: svbool_t, base: *const i32, vnum: i64) -> svuint64_t { + svldff1sw_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s32index_s32( + pg: svbool_t, + base: *const i16, + indices: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i16" + )] + fn _svldff1sh_gather_s32index_s32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_s32index_s32(pg.sve_into(), base, indices)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s32index_u32( + pg: svbool_t, + base: *const i16, + indices: svint32_t, +) -> svuint32_t { + svldff1sh_gather_s32index_s32(pg, base, indices).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s64index_s64( + pg: svbool_t, + base: *const i16, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2i16" + )] + fn _svldff1sh_gather_s64index_s64( + pg: svbool2_t, + base: *const i16, + indices: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_s64index_s64(pg.sve_into(), base, indices)) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_s64index_s64( + pg: svbool_t, + base: *const i32, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2i32" + )] + fn _svldff1sw_gather_s64index_s64( + pg: svbool2_t, + base: *const i32, + indices: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldff1sw_gather_s64index_s64(pg.sve_into(), base, indices)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s64index_u64( + pg: svbool_t, + base: *const i16, + indices: svint64_t, +) -> svuint64_t { + svldff1sh_gather_s64index_s64(pg, base, indices).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_s64index_u64( + pg: svbool_t, + base: *const i32, + indices: svint64_t, +) -> svuint64_t { + svldff1sw_gather_s64index_s64(pg, base, indices).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32index_s32( + pg: svbool_t, + base: *const i16, + indices: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4i16" + )] + fn _svldff1sh_gather_u32index_s32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_u32index_s32( + pg.sve_into(), + base, + indices.as_signed(), + )) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32index_u32( + pg: svbool_t, + base: *const i16, + indices: svuint32_t, +) -> svuint32_t { + svldff1sh_gather_u32index_s32(pg, base, indices).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64index_s64( + pg: svbool_t, + base: *const i16, + indices: svuint64_t, +) -> svint64_t { + svldff1sh_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64index_s64( + pg: svbool_t, + base: *const i32, + indices: svuint64_t, +) -> svint64_t { + svldff1sw_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64index_u64( + pg: svbool_t, + base: *const i16, + indices: svuint64_t, +) -> svuint64_t { + svldff1sh_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64index_u64( + pg: svbool_t, + base: *const i32, + indices: svuint64_t, +) -> svuint64_t { + svldff1sw_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svldff1sh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svldff1sh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldff1sh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldff1sw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldff1sh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldff1sw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_s32offset_s32( + pg: svbool_t, + base: *const u8, + offsets: svint32_t, +) -> svint32_t { + svldff1ub_gather_s32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s32offset_s32( + pg: svbool_t, + base: *const u16, + offsets: svint32_t, +) -> svint32_t { + svldff1uh_gather_s32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_s32offset_u32( + pg: svbool_t, + base: *const u8, + offsets: svint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i8" + )] + fn _svldff1ub_gather_s32offset_u32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_gather_s32offset_u32(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s32offset_u32( + pg: svbool_t, + base: *const u16, + offsets: svint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i16" + )] + fn _svldff1uh_gather_s32offset_u32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_s32offset_u32(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_s64offset_s64( + pg: svbool_t, + base: *const u8, + offsets: svint64_t, +) -> svint64_t { + svldff1ub_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s64offset_s64( + pg: svbool_t, + base: *const u16, + offsets: svint64_t, +) -> svint64_t { + svldff1uh_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_s64offset_s64( + pg: svbool_t, + base: *const u32, + offsets: svint64_t, +) -> svint64_t { + svldff1uw_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_s64offset_u64( + pg: svbool_t, + base: *const u8, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i8" + )] + fn _svldff1ub_gather_s64offset_u64( + pg: svbool2_t, + base: *const i8, + offsets: svint64_t, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s64offset_u64( + pg: svbool_t, + base: *const u16, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i16" + )] + fn _svldff1uh_gather_s64offset_u64( + pg: svbool2_t, + base: *const i16, + offsets: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_s64offset_u64( + pg: svbool_t, + base: *const u32, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i32" + )] + fn _svldff1uw_gather_s64offset_u64( + pg: svbool2_t, + base: *const i32, + offsets: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uw_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u32offset_s32( + pg: svbool_t, + base: *const u8, + offsets: svuint32_t, +) -> svint32_t { + svldff1ub_gather_u32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32offset_s32( + pg: svbool_t, + base: *const u16, + offsets: svuint32_t, +) -> svint32_t { + svldff1uh_gather_u32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u32offset_u32( + pg: svbool_t, + base: *const u8, + offsets: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i8" + )] + fn _svldff1ub_gather_u32offset_u32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32offset_u32( + pg: svbool_t, + base: *const u16, + offsets: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i16" + )] + fn _svldff1uh_gather_u32offset_u32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u64offset_s64( + pg: svbool_t, + base: *const u8, + offsets: svuint64_t, +) -> svint64_t { + svldff1ub_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64offset_s64( + pg: svbool_t, + base: *const u16, + offsets: svuint64_t, +) -> svint64_t { + svldff1uh_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64offset_s64( + pg: svbool_t, + base: *const u32, + offsets: svuint64_t, +) -> svint64_t { + svldff1uw_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u64offset_u64( + pg: svbool_t, + base: *const u8, + offsets: svuint64_t, +) -> svuint64_t { + svldff1ub_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64offset_u64( + pg: svbool_t, + base: *const u16, + offsets: svuint64_t, +) -> svuint64_t { + svldff1uh_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64offset_u64( + pg: svbool_t, + base: *const u32, + offsets: svuint64_t, +) -> svuint64_t { + svldff1uw_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + svldff1ub_gather_u32base_offset_u32(pg, bases, offset).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + svldff1uh_gather_u32base_offset_u32(pg, bases, offset).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svldff1ub_gather_u32base_offset_u32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svldff1uh_gather_u32base_offset_u32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svldff1ub_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svldff1uh_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svldff1uw_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svldff1ub_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svldff1uh_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svldff1uw_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uw_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldff1ub_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldff1uh_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldff1ub_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldff1uh_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldff1ub_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldff1uh_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldff1uw_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldff1ub_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldff1uh_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldff1uw_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_s16(pg: svbool_t, base: *const u8) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv8i8")] + fn _svldff1ub_s16(pg: svbool8_t, base: *const i8) -> nxv8i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_s16(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_s32(pg: svbool_t, base: *const u8) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4i8")] + fn _svldff1ub_s32(pg: svbool4_t, base: *const i8) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_s32(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_s32(pg: svbool_t, base: *const u16) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4i16")] + fn _svldff1uh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_s32(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_s64(pg: svbool_t, base: *const u8) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i8")] + fn _svldff1ub_s64(pg: svbool2_t, base: *const i8) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_s64(pg: svbool_t, base: *const u16) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i16")] + fn _svldff1uh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_s64(pg: svbool_t, base: *const u32) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i32")] + fn _svldff1uw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uw_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_u16(pg: svbool_t, base: *const u8) -> svuint16_t { + svldff1ub_s16(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_u32(pg: svbool_t, base: *const u8) -> svuint32_t { + svldff1ub_s32(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_u32(pg: svbool_t, base: *const u16) -> svuint32_t { + svldff1uh_s32(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_u64(pg: svbool_t, base: *const u8) -> svuint64_t { + svldff1ub_s64(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_u64(pg: svbool_t, base: *const u16) -> svuint64_t { + svldff1uh_s64(pg, base).as_unsigned() +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_u64(pg: svbool_t, base: *const u32) -> svuint64_t { + svldff1uw_s64(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_vnum_s16(pg: svbool_t, base: *const u8, vnum: i64) -> svint16_t { + svldff1ub_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_vnum_s32(pg: svbool_t, base: *const u8, vnum: i64) -> svint32_t { + svldff1ub_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_vnum_s32(pg: svbool_t, base: *const u16, vnum: i64) -> svint32_t { + svldff1uh_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_vnum_s64(pg: svbool_t, base: *const u8, vnum: i64) -> svint64_t { + svldff1ub_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_vnum_s64(pg: svbool_t, base: *const u16, vnum: i64) -> svint64_t { + svldff1uh_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_vnum_s64(pg: svbool_t, base: *const u32, vnum: i64) -> svint64_t { + svldff1uw_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_vnum_u16(pg: svbool_t, base: *const u8, vnum: i64) -> svuint16_t { + svldff1ub_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_vnum_u32(pg: svbool_t, base: *const u8, vnum: i64) -> svuint32_t { + svldff1ub_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_vnum_u32(pg: svbool_t, base: *const u16, vnum: i64) -> svuint32_t { + svldff1uh_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_vnum_u64(pg: svbool_t, base: *const u8, vnum: i64) -> svuint64_t { + svldff1ub_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_vnum_u64(pg: svbool_t, base: *const u16, vnum: i64) -> svuint64_t { + svldff1uh_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_vnum_u64(pg: svbool_t, base: *const u32, vnum: i64) -> svuint64_t { + svldff1uw_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s32index_s32( + pg: svbool_t, + base: *const u16, + indices: svint32_t, +) -> svint32_t { + svldff1uh_gather_s32index_u32(pg, base, indices).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s32index_u32( + pg: svbool_t, + base: *const u16, + indices: svint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i16" + )] + fn _svldff1uh_gather_s32index_u32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_s32index_u32(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s64index_s64( + pg: svbool_t, + base: *const u16, + indices: svint64_t, +) -> svint64_t { + svldff1uh_gather_s64index_u64(pg, base, indices).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_s64index_s64( + pg: svbool_t, + base: *const u32, + indices: svint64_t, +) -> svint64_t { + svldff1uw_gather_s64index_u64(pg, base, indices).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s64index_u64( + pg: svbool_t, + base: *const u16, + indices: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2i16" + )] + fn _svldff1uh_gather_s64index_u64( + pg: svbool2_t, + base: *const i16, + indices: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_s64index_u64( + pg: svbool_t, + base: *const u32, + indices: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2i32" + )] + fn _svldff1uw_gather_s64index_u64( + pg: svbool2_t, + base: *const i32, + indices: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uw_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32index_s32( + pg: svbool_t, + base: *const u16, + indices: svuint32_t, +) -> svint32_t { + svldff1uh_gather_u32index_u32(pg, base, indices).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32index_u32( + pg: svbool_t, + base: *const u16, + indices: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4i16" + )] + fn _svldff1uh_gather_u32index_u32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_u32index_u32(pg.sve_into(), base.as_signed(), indices.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64index_s64( + pg: svbool_t, + base: *const u16, + indices: svuint64_t, +) -> svint64_t { + svldff1uh_gather_s64index_u64(pg, base, indices.as_signed()).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64index_s64( + pg: svbool_t, + base: *const u32, + indices: svuint64_t, +) -> svint64_t { + svldff1uw_gather_s64index_u64(pg, base, indices.as_signed()).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64index_u64( + pg: svbool_t, + base: *const u16, + indices: svuint64_t, +) -> svuint64_t { + svldff1uh_gather_s64index_u64(pg, base, indices.as_signed()) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64index_u64( + pg: svbool_t, + base: *const u32, + indices: svuint64_t, +) -> svuint64_t { + svldff1uw_gather_s64index_u64(pg, base, indices.as_signed()) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svldff1uh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svldff1uh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldff1uh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldff1uw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldff1uh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldff1uw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1_f32(pg: svbool_t, base: *const f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4f32")] + fn _svldnf1_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t; + } + _svldnf1_f32(pg.sve_into(), base) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1d))] +pub unsafe fn svldnf1_f64(pg: svbool_t, base: *const f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2f64")] + fn _svldnf1_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t; + } + _svldnf1_f64(pg.sve_into(), base) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1_s8(pg: svbool_t, base: *const i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv16i8")] + fn _svldnf1_s8(pg: svbool_t, base: *const i8) -> svint8_t; + } + _svldnf1_s8(pg, base) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1_s16(pg: svbool_t, base: *const i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv8i16")] + fn _svldnf1_s16(pg: svbool8_t, base: *const i16) -> svint16_t; + } + _svldnf1_s16(pg.sve_into(), base) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1_s32(pg: svbool_t, base: *const i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4i32")] + fn _svldnf1_s32(pg: svbool4_t, base: *const i32) -> svint32_t; + } + _svldnf1_s32(pg.sve_into(), base) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1d))] +pub unsafe fn svldnf1_s64(pg: svbool_t, base: *const i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i64")] + fn _svldnf1_s64(pg: svbool2_t, base: *const i64) -> svint64_t; + } + _svldnf1_s64(pg.sve_into(), base) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1_u8(pg: svbool_t, base: *const u8) -> svuint8_t { + svldnf1_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1_u16(pg: svbool_t, base: *const u16) -> svuint16_t { + svldnf1_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1_u32(pg: svbool_t, base: *const u32) -> svuint32_t { + svldnf1_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1d))] +pub unsafe fn svldnf1_u64(pg: svbool_t, base: *const u64) -> svuint64_t { + svldnf1_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32_t { + svldnf1_f32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1d))] +pub unsafe fn svldnf1_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64_t { + svldnf1_f64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8_t { + svldnf1_s8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16_t { + svldnf1_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32_t { + svldnf1_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1d))] +pub unsafe fn svldnf1_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64_t { + svldnf1_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8_t { + svldnf1_u8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16_t { + svldnf1_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32_t { + svldnf1_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1d))] +pub unsafe fn svldnf1_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64_t { + svldnf1_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_s16(pg: svbool_t, base: *const i8) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv8i8")] + fn _svldnf1sb_s16(pg: svbool8_t, base: *const i8) -> nxv8i8; + } + crate::intrinsics::simd::simd_cast(_svldnf1sb_s16(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_s32(pg: svbool_t, base: *const i8) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4i8")] + fn _svldnf1sb_s32(pg: svbool4_t, base: *const i8) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svldnf1sb_s32(pg.sve_into(), base)) +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_s32(pg: svbool_t, base: *const i16) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4i16")] + fn _svldnf1sh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldnf1sh_s32(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_s64(pg: svbool_t, base: *const i8) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i8")] + fn _svldnf1sb_s64(pg: svbool2_t, base: *const i8) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svldnf1sb_s64(pg.sve_into(), base)) +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_s64(pg: svbool_t, base: *const i16) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i16")] + fn _svldnf1sh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldnf1sh_s64(pg.sve_into(), base)) +} +#[doc = "Load 32-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sw_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sw))] +pub unsafe fn svldnf1sw_s64(pg: svbool_t, base: *const i32) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i32")] + fn _svldnf1sw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldnf1sw_s64(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_u16(pg: svbool_t, base: *const i8) -> svuint16_t { + svldnf1sb_s16(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_u32(pg: svbool_t, base: *const i8) -> svuint32_t { + svldnf1sb_s32(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_u32(pg: svbool_t, base: *const i16) -> svuint32_t { + svldnf1sh_s32(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_u64(pg: svbool_t, base: *const i8) -> svuint64_t { + svldnf1sb_s64(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_u64(pg: svbool_t, base: *const i16) -> svuint64_t { + svldnf1sh_s64(pg, base).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sw_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sw))] +pub unsafe fn svldnf1sw_u64(pg: svbool_t, base: *const i32) -> svuint64_t { + svldnf1sw_s64(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_vnum_s16(pg: svbool_t, base: *const i8, vnum: i64) -> svint16_t { + svldnf1sb_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_vnum_s32(pg: svbool_t, base: *const i8, vnum: i64) -> svint32_t { + svldnf1sb_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_vnum_s32(pg: svbool_t, base: *const i16, vnum: i64) -> svint32_t { + svldnf1sh_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_vnum_s64(pg: svbool_t, base: *const i8, vnum: i64) -> svint64_t { + svldnf1sb_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_vnum_s64(pg: svbool_t, base: *const i16, vnum: i64) -> svint64_t { + svldnf1sh_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sw_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sw))] +pub unsafe fn svldnf1sw_vnum_s64(pg: svbool_t, base: *const i32, vnum: i64) -> svint64_t { + svldnf1sw_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_vnum_u16(pg: svbool_t, base: *const i8, vnum: i64) -> svuint16_t { + svldnf1sb_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_vnum_u32(pg: svbool_t, base: *const i8, vnum: i64) -> svuint32_t { + svldnf1sb_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_vnum_u32(pg: svbool_t, base: *const i16, vnum: i64) -> svuint32_t { + svldnf1sh_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_vnum_u64(pg: svbool_t, base: *const i8, vnum: i64) -> svuint64_t { + svldnf1sb_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_vnum_u64(pg: svbool_t, base: *const i16, vnum: i64) -> svuint64_t { + svldnf1sh_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sw_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sw))] +pub unsafe fn svldnf1sw_vnum_u64(pg: svbool_t, base: *const i32, vnum: i64) -> svuint64_t { + svldnf1sw_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_s16(pg: svbool_t, base: *const u8) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv8i8")] + fn _svldnf1ub_s16(pg: svbool8_t, base: *const i8) -> nxv8i8; + } + crate::intrinsics::simd::simd_cast::( + _svldnf1ub_s16(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_s32(pg: svbool_t, base: *const u8) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4i8")] + fn _svldnf1ub_s32(pg: svbool4_t, base: *const i8) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svldnf1ub_s32(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_s32(pg: svbool_t, base: *const u16) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4i16")] + fn _svldnf1uh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldnf1uh_s32(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_s64(pg: svbool_t, base: *const u8) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i8")] + fn _svldnf1ub_s64(pg: svbool2_t, base: *const i8) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svldnf1ub_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_s64(pg: svbool_t, base: *const u16) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i16")] + fn _svldnf1uh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldnf1uh_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uw_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1uw_s64(pg: svbool_t, base: *const u32) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i32")] + fn _svldnf1uw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldnf1uw_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_u16(pg: svbool_t, base: *const u8) -> svuint16_t { + svldnf1ub_s16(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_u32(pg: svbool_t, base: *const u8) -> svuint32_t { + svldnf1ub_s32(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_u32(pg: svbool_t, base: *const u16) -> svuint32_t { + svldnf1uh_s32(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_u64(pg: svbool_t, base: *const u8) -> svuint64_t { + svldnf1ub_s64(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_u64(pg: svbool_t, base: *const u16) -> svuint64_t { + svldnf1uh_s64(pg, base).as_unsigned() +} +#[doc = "Load 32-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uw_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1uw_u64(pg: svbool_t, base: *const u32) -> svuint64_t { + svldnf1uw_s64(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_vnum_s16(pg: svbool_t, base: *const u8, vnum: i64) -> svint16_t { + svldnf1ub_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_vnum_s32(pg: svbool_t, base: *const u8, vnum: i64) -> svint32_t { + svldnf1ub_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_vnum_s32(pg: svbool_t, base: *const u16, vnum: i64) -> svint32_t { + svldnf1uh_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_vnum_s64(pg: svbool_t, base: *const u8, vnum: i64) -> svint64_t { + svldnf1ub_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_vnum_s64(pg: svbool_t, base: *const u16, vnum: i64) -> svint64_t { + svldnf1uh_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uw_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1uw_vnum_s64(pg: svbool_t, base: *const u32, vnum: i64) -> svint64_t { + svldnf1uw_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_vnum_u16(pg: svbool_t, base: *const u8, vnum: i64) -> svuint16_t { + svldnf1ub_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_vnum_u32(pg: svbool_t, base: *const u8, vnum: i64) -> svuint32_t { + svldnf1ub_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_vnum_u32(pg: svbool_t, base: *const u16, vnum: i64) -> svuint32_t { + svldnf1uh_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_vnum_u64(pg: svbool_t, base: *const u8, vnum: i64) -> svuint64_t { + svldnf1ub_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_vnum_u64(pg: svbool_t, base: *const u16, vnum: i64) -> svuint64_t { + svldnf1uh_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uw_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1uw_vnum_u64(pg: svbool_t, base: *const u32, vnum: i64) -> svuint64_t { + svldnf1uw_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_f32(pg: svbool_t, base: *const f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv4f32")] + fn _svldnt1_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t; + } + _svldnt1_f32(pg.sve_into(), base) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_f64(pg: svbool_t, base: *const f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv2f64")] + fn _svldnt1_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t; + } + _svldnt1_f64(pg.sve_into(), base) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1_s8(pg: svbool_t, base: *const i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv16i8")] + fn _svldnt1_s8(pg: svbool_t, base: *const i8) -> svint8_t; + } + _svldnt1_s8(pg, base) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1_s16(pg: svbool_t, base: *const i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv8i16")] + fn _svldnt1_s16(pg: svbool8_t, base: *const i16) -> svint16_t; + } + _svldnt1_s16(pg.sve_into(), base) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_s32(pg: svbool_t, base: *const i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv4i32")] + fn _svldnt1_s32(pg: svbool4_t, base: *const i32) -> svint32_t; + } + _svldnt1_s32(pg.sve_into(), base) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_s64(pg: svbool_t, base: *const i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv2i64")] + fn _svldnt1_s64(pg: svbool2_t, base: *const i64) -> svint64_t; + } + _svldnt1_s64(pg.sve_into(), base) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1_u8(pg: svbool_t, base: *const u8) -> svuint8_t { + svldnt1_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1_u16(pg: svbool_t, base: *const u16) -> svuint16_t { + svldnt1_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_u32(pg: svbool_t, base: *const u32) -> svuint32_t { + svldnt1_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_u64(pg: svbool_t, base: *const u64) -> svuint64_t { + svldnt1_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32_t { + svldnt1_f32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64_t { + svldnt1_f64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8_t { + svldnt1_s8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16_t { + svldnt1_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32_t { + svldnt1_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64_t { + svldnt1_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8_t { + svldnt1_u8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16_t { + svldnt1_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32_t { + svldnt1_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64_t { + svldnt1_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntw))] +pub fn svlen_f32(_op: svfloat32_t) -> u64 { + svcntw() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntd))] +pub fn svlen_f64(_op: svfloat64_t) -> u64 { + svcntd() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rdvl))] +pub fn svlen_s8(_op: svint8_t) -> u64 { + svcntb() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnth))] +pub fn svlen_s16(_op: svint16_t) -> u64 { + svcnth() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntw))] +pub fn svlen_s32(_op: svint32_t) -> u64 { + svcntw() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntd))] +pub fn svlen_s64(_op: svint64_t) -> u64 { + svcntd() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rdvl))] +pub fn svlen_u8(_op: svuint8_t) -> u64 { + svcntb() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnth))] +pub fn svlen_u16(_op: svuint16_t) -> u64 { + svcnth() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntw))] +pub fn svlen_u32(_op: svuint32_t) -> u64 { + svcntw() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntd))] +pub fn svlen_u64(_op: svuint64_t) -> u64 { + svcntd() +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsl.nxv16i8")] + fn _svlsl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svlsl_s8_m(pg, op1, op2.as_signed()) } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svlsl_s8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + svlsl_s8_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svlsl_s8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + svlsl_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svlsl_s8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsl.nxv8i16")] + fn _svlsl_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svlsl_s16_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svlsl_s16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + svlsl_s16_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svlsl_s16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + svlsl_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svlsl_s16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsl.nxv4i32")] + fn _svlsl_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svlsl_s32_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svlsl_s32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + svlsl_s32_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svlsl_s32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + svlsl_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svlsl_s32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s64_m(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsl.nxv2i64")] + fn _svlsl_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svlsl_s64_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s64_m(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svlsl_s64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s64_x(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + svlsl_s64_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s64_x(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svlsl_s64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s64_z(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + svlsl_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s64_z(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svlsl_s64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svlsl_s8_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svlsl_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svlsl_u8_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svlsl_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svlsl_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svlsl_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svlsl_s16_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svlsl_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svlsl_u16_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svlsl_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svlsl_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svlsl_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svlsl_s32_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svlsl_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svlsl_u32_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svlsl_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svlsl_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svlsl_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svlsl_s64_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svlsl_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svlsl_u64_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svlsl_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svlsl_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svlsl_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.lsl.wide.nxv16i8" + )] + fn _svlsl_wide_s8_m(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svint8_t; + } + unsafe { _svlsl_wide_s8_m(pg, op1, op2.as_signed()) } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t { + svlsl_wide_s8_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t { + svlsl_wide_s8_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t { + svlsl_wide_s8_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t { + svlsl_wide_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t { + svlsl_wide_s8_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.lsl.wide.nxv8i16" + )] + fn _svlsl_wide_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svint16_t; + } + unsafe { _svlsl_wide_s16_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t { + svlsl_wide_s16_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t { + svlsl_wide_s16_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t { + svlsl_wide_s16_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t { + svlsl_wide_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t { + svlsl_wide_s16_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.lsl.wide.nxv4i32" + )] + fn _svlsl_wide_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svlsl_wide_s32_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t { + svlsl_wide_s32_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t { + svlsl_wide_s32_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t { + svlsl_wide_s32_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t { + svlsl_wide_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t { + svlsl_wide_s32_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t { + unsafe { svlsl_wide_s8_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t { + svlsl_wide_u8_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t { + svlsl_wide_u8_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t { + svlsl_wide_u8_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t { + svlsl_wide_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t { + svlsl_wide_u8_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t { + unsafe { svlsl_wide_s16_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t { + svlsl_wide_u16_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t { + svlsl_wide_u16_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t { + svlsl_wide_u16_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t { + svlsl_wide_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t { + svlsl_wide_u16_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t { + unsafe { svlsl_wide_s32_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t { + svlsl_wide_u32_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t { + svlsl_wide_u32_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t { + svlsl_wide_u32_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t { + svlsl_wide_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t { + svlsl_wide_u32_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsr.nxv16i8")] + fn _svlsr_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svlsr_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svlsr_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svlsr_u8_m(pg, op1, op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svlsr_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svlsr_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svlsr_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsr.nxv8i16")] + fn _svlsr_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svlsr_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svlsr_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svlsr_u16_m(pg, op1, op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svlsr_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svlsr_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svlsr_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsr.nxv4i32")] + fn _svlsr_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svlsr_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svlsr_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svlsr_u32_m(pg, op1, op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svlsr_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svlsr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svlsr_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsr.nxv2i64")] + fn _svlsr_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svlsr_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svlsr_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svlsr_u64_m(pg, op1, op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svlsr_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svlsr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svlsr_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.lsr.wide.nxv16i8" + )] + fn _svlsr_wide_u8_m(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svint8_t; + } + unsafe { _svlsr_wide_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t { + svlsr_wide_u8_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t { + svlsr_wide_u8_m(pg, op1, op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t { + svlsr_wide_u8_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t { + svlsr_wide_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t { + svlsr_wide_u8_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.lsr.wide.nxv8i16" + )] + fn _svlsr_wide_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svint16_t; + } + unsafe { _svlsr_wide_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t { + svlsr_wide_u16_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t { + svlsr_wide_u16_m(pg, op1, op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t { + svlsr_wide_u16_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t { + svlsr_wide_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t { + svlsr_wide_u16_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.lsr.wide.nxv4i32" + )] + fn _svlsr_wide_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svlsr_wide_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t { + svlsr_wide_u32_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t { + svlsr_wide_u32_m(pg, op1, op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t { + svlsr_wide_u32_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t { + svlsr_wide_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t { + svlsr_wide_u32_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmad.nxv4f32")] + fn _svmad_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svmad_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmad_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmad_f32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmad_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmad_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmad_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmad.nxv2f64")] + fn _svmad_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svmad_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmad_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmad_f64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmad_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmad_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmad_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mad.nxv16i8")] + fn _svmad_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svmad_s8_m(pg, op1, op2, op3) } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmad_s8_m(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmad_s8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmad_s8_x(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmad_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmad_s8_z(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mad.nxv8i16")] + fn _svmad_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) + -> svint16_t; + } + unsafe { _svmad_s16_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmad_s16_m(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmad_s16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmad_s16_x(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmad_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmad_s16_z(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mad.nxv4i32")] + fn _svmad_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) + -> svint32_t; + } + unsafe { _svmad_s32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmad_s32_m(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmad_s32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmad_s32_x(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmad_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmad_s32_z(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mad.nxv2i64")] + fn _svmad_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) + -> svint64_t; + } + unsafe { _svmad_s64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmad_s64_m(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmad_s64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmad_s64_x(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmad_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmad_s64_z(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svmad_s8_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmad_u8_m(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmad_u8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmad_u8_x(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmad_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmad_u8_z(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svmad_s16_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmad_u16_m(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmad_u16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmad_u16_x(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmad_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmad_u16_z(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svmad_s32_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmad_u32_m(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmad_u32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmad_u32_x(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmad_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmad_u32_z(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svmad_s64_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmad_u64_m(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmad_u64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmad_u64_x(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmad_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmad_u64_z(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmax.nxv4f32")] + fn _svmax_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmax_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmax_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmax_f32_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmax_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmax_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmax_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmax.nxv2f64")] + fn _svmax_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmax_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmax_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmax_f64_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmax_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmax_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmax_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smax.nxv16i8")] + fn _svmax_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmax_s8_m(pg, op1, op2) } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmax_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmax_s8_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmax_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmax_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmax_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smax.nxv8i16")] + fn _svmax_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmax_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmax_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmax_s16_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmax_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmax_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmax_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smax.nxv4i32")] + fn _svmax_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmax_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmax_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmax_s32_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmax_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmax_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmax_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smax.nxv2i64")] + fn _svmax_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmax_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmax_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmax_s64_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmax_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmax_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmax_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umax.nxv16i8")] + fn _svmax_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmax_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmax_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmax_u8_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmax_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmax_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmax_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umax.nxv8i16")] + fn _svmax_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmax_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmax_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmax_u16_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmax_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmax_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmax_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umax.nxv4i32")] + fn _svmax_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmax_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmax_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmax_u32_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmax_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmax_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmax_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umax.nxv2i64")] + fn _svmax_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmax_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmax_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmax_u64_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmax_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmax_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmax_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxnm.nxv4f32")] + fn _svmaxnm_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmaxnm_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmaxnm_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmaxnm_f32_m(pg, op1, op2) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmaxnm_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmaxnm_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmaxnm_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxnm.nxv2f64")] + fn _svmaxnm_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmaxnm_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmaxnm_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmaxnm_f64_m(pg, op1, op2) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmaxnm_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmaxnm_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmaxnm_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Maximum number reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmv[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnmv))] +pub fn svmaxnmv_f32(pg: svbool_t, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmaxnmv.nxv4f32" + )] + fn _svmaxnmv_f32(pg: svbool4_t, op: svfloat32_t) -> f32; + } + unsafe { _svmaxnmv_f32(pg.sve_into(), op) } +} +#[doc = "Maximum number reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmv[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnmv))] +pub fn svmaxnmv_f64(pg: svbool_t, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmaxnmv.nxv2f64" + )] + fn _svmaxnmv_f64(pg: svbool2_t, op: svfloat64_t) -> f64; + } + unsafe { _svmaxnmv_f64(pg.sve_into(), op) } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxv))] +pub fn svmaxv_f32(pg: svbool_t, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxv.nxv4f32")] + fn _svmaxv_f32(pg: svbool4_t, op: svfloat32_t) -> f32; + } + unsafe { _svmaxv_f32(pg.sve_into(), op) } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxv))] +pub fn svmaxv_f64(pg: svbool_t, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxv.nxv2f64")] + fn _svmaxv_f64(pg: svbool2_t, op: svfloat64_t) -> f64; + } + unsafe { _svmaxv_f64(pg.sve_into(), op) } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxv))] +pub fn svmaxv_s8(pg: svbool_t, op: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxv.nxv16i8")] + fn _svmaxv_s8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svmaxv_s8(pg, op) } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxv))] +pub fn svmaxv_s16(pg: svbool_t, op: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxv.nxv8i16")] + fn _svmaxv_s16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svmaxv_s16(pg.sve_into(), op) } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxv))] +pub fn svmaxv_s32(pg: svbool_t, op: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxv.nxv4i32")] + fn _svmaxv_s32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svmaxv_s32(pg.sve_into(), op) } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxv))] +pub fn svmaxv_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxv.nxv2i64")] + fn _svmaxv_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svmaxv_s64(pg.sve_into(), op) } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxv))] +pub fn svmaxv_u8(pg: svbool_t, op: svuint8_t) -> u8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxv.nxv16i8")] + fn _svmaxv_u8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svmaxv_u8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxv))] +pub fn svmaxv_u16(pg: svbool_t, op: svuint16_t) -> u16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxv.nxv8i16")] + fn _svmaxv_u16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svmaxv_u16(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxv))] +pub fn svmaxv_u32(pg: svbool_t, op: svuint32_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxv.nxv4i32")] + fn _svmaxv_u32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svmaxv_u32(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxv))] +pub fn svmaxv_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxv.nxv2i64")] + fn _svmaxv_u64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svmaxv_u64(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmin.nxv4f32")] + fn _svmin_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmin_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmin_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmin_f32_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmin_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmin_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmin_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmin.nxv2f64")] + fn _svmin_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmin_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmin_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmin_f64_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmin_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmin_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmin_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smin.nxv16i8")] + fn _svmin_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmin_s8_m(pg, op1, op2) } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmin_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmin_s8_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmin_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmin_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmin_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smin.nxv8i16")] + fn _svmin_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmin_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmin_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmin_s16_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmin_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmin_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmin_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smin.nxv4i32")] + fn _svmin_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmin_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmin_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmin_s32_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmin_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmin_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmin_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smin.nxv2i64")] + fn _svmin_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmin_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmin_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmin_s64_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmin_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmin_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmin_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umin.nxv16i8")] + fn _svmin_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmin_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmin_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmin_u8_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmin_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmin_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmin_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umin.nxv8i16")] + fn _svmin_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmin_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmin_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmin_u16_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmin_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmin_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmin_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umin.nxv4i32")] + fn _svmin_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmin_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmin_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmin_u32_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmin_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmin_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmin_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umin.nxv2i64")] + fn _svmin_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmin_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmin_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmin_u64_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmin_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmin_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmin_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminnm.nxv4f32")] + fn _svminnm_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svminnm_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svminnm_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svminnm_f32_m(pg, op1, op2) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svminnm_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svminnm_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svminnm_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminnm.nxv2f64")] + fn _svminnm_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svminnm_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svminnm_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svminnm_f64_m(pg, op1, op2) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svminnm_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svminnm_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svminnm_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Minimum number reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmv[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnmv))] +pub fn svminnmv_f32(pg: svbool_t, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fminnmv.nxv4f32" + )] + fn _svminnmv_f32(pg: svbool4_t, op: svfloat32_t) -> f32; + } + unsafe { _svminnmv_f32(pg.sve_into(), op) } +} +#[doc = "Minimum number reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmv[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnmv))] +pub fn svminnmv_f64(pg: svbool_t, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fminnmv.nxv2f64" + )] + fn _svminnmv_f64(pg: svbool2_t, op: svfloat64_t) -> f64; + } + unsafe { _svminnmv_f64(pg.sve_into(), op) } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminv))] +pub fn svminv_f32(pg: svbool_t, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminv.nxv4f32")] + fn _svminv_f32(pg: svbool4_t, op: svfloat32_t) -> f32; + } + unsafe { _svminv_f32(pg.sve_into(), op) } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminv))] +pub fn svminv_f64(pg: svbool_t, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminv.nxv2f64")] + fn _svminv_f64(pg: svbool2_t, op: svfloat64_t) -> f64; + } + unsafe { _svminv_f64(pg.sve_into(), op) } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminv))] +pub fn svminv_s8(pg: svbool_t, op: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminv.nxv16i8")] + fn _svminv_s8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svminv_s8(pg, op) } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminv))] +pub fn svminv_s16(pg: svbool_t, op: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminv.nxv8i16")] + fn _svminv_s16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svminv_s16(pg.sve_into(), op) } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminv))] +pub fn svminv_s32(pg: svbool_t, op: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminv.nxv4i32")] + fn _svminv_s32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svminv_s32(pg.sve_into(), op) } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminv))] +pub fn svminv_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminv.nxv2i64")] + fn _svminv_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svminv_s64(pg.sve_into(), op) } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminv))] +pub fn svminv_u8(pg: svbool_t, op: svuint8_t) -> u8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminv.nxv16i8")] + fn _svminv_u8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svminv_u8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminv))] +pub fn svminv_u16(pg: svbool_t, op: svuint16_t) -> u16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminv.nxv8i16")] + fn _svminv_u16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svminv_u16(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminv))] +pub fn svminv_u32(pg: svbool_t, op: svuint32_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminv.nxv4i32")] + fn _svminv_u32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svminv_u32(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminv))] +pub fn svminv_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminv.nxv2i64")] + fn _svminv_u64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svminv_u64(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmla.nxv4f32")] + fn _svmla_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svmla_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmla_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmla_f32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmla_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmla_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmla_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmla.nxv2f64")] + fn _svmla_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svmla_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmla_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmla_f64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmla_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmla_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmla_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mla.nxv16i8")] + fn _svmla_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svmla_s8_m(pg, op1, op2, op3) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmla_s8_m(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmla_s8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmla_s8_x(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmla_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmla_s8_z(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mla.nxv8i16")] + fn _svmla_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) + -> svint16_t; + } + unsafe { _svmla_s16_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmla_s16_m(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmla_s16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmla_s16_x(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmla_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmla_s16_z(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mla.nxv4i32")] + fn _svmla_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) + -> svint32_t; + } + unsafe { _svmla_s32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmla_s32_m(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmla_s32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmla_s32_x(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmla_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmla_s32_z(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mla.nxv2i64")] + fn _svmla_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) + -> svint64_t; + } + unsafe { _svmla_s64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmla_s64_m(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmla_s64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmla_s64_x(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmla_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmla_s64_z(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svmla_s8_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmla_u8_m(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmla_u8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmla_u8_x(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmla_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmla_u8_z(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svmla_s16_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmla_u16_m(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmla_u16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmla_u16_x(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmla_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmla_u16_z(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svmla_s32_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmla_u32_m(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmla_u32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmla_u32_x(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmla_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmla_u32_z(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svmla_s64_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmla_u64_m(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmla_u64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmla_u64_x(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmla_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmla_u64_z(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla, IMM_INDEX = 0))] +pub fn svmla_lane_f32( + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmla.lane.nxv4f32" + )] + fn _svmla_lane_f32( + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + IMM_INDEX: i32, + ) -> svfloat32_t; + } + unsafe { _svmla_lane_f32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla, IMM_INDEX = 0))] +pub fn svmla_lane_f64( + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmla.lane.nxv2f64" + )] + fn _svmla_lane_f64( + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + IMM_INDEX: i32, + ) -> svfloat64_t; + } + unsafe { _svmla_lane_f64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmls.nxv4f32")] + fn _svmls_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svmls_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmls_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmls_f32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmls_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmls_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmls_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmls.nxv2f64")] + fn _svmls_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svmls_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmls_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmls_f64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmls_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmls_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmls_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mls.nxv16i8")] + fn _svmls_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svmls_s8_m(pg, op1, op2, op3) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmls_s8_m(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmls_s8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmls_s8_x(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmls_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmls_s8_z(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mls.nxv8i16")] + fn _svmls_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) + -> svint16_t; + } + unsafe { _svmls_s16_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmls_s16_m(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmls_s16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmls_s16_x(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmls_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmls_s16_z(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mls.nxv4i32")] + fn _svmls_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) + -> svint32_t; + } + unsafe { _svmls_s32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmls_s32_m(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmls_s32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmls_s32_x(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmls_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmls_s32_z(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mls.nxv2i64")] + fn _svmls_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) + -> svint64_t; + } + unsafe { _svmls_s64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmls_s64_m(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmls_s64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmls_s64_x(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmls_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmls_s64_z(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svmls_s8_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmls_u8_m(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmls_u8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmls_u8_x(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmls_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmls_u8_z(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svmls_s16_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmls_u16_m(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmls_u16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmls_u16_x(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmls_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmls_u16_z(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svmls_s32_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmls_u32_m(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmls_u32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmls_u32_x(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmls_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmls_u32_z(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svmls_s64_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmls_u64_m(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmls_u64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmls_u64_x(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmls_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmls_u64_z(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls, IMM_INDEX = 0))] +pub fn svmls_lane_f32( + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmls.lane.nxv4f32" + )] + fn _svmls_lane_f32( + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + IMM_INDEX: i32, + ) -> svfloat32_t; + } + unsafe { _svmls_lane_f32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls, IMM_INDEX = 0))] +pub fn svmls_lane_f64( + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmls.lane.nxv2f64" + )] + fn _svmls_lane_f64( + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + IMM_INDEX: i32, + ) -> svfloat64_t; + } + unsafe { _svmls_lane_f64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Matrix multiply-accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmmla[_f32])"] +#[inline] +#[target_feature(enable = "sve,f32mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmmla))] +pub fn svmmla_f32(op1: svfloat32_t, op2: svfloat32_t, op3: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmmla.nxv4f32.nxv4f32" + )] + fn _svmmla_f32(op1: svfloat32_t, op2: svfloat32_t, op3: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmmla_f32(op1, op2, op3) } +} +#[doc = "Matrix multiply-accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmmla[_f64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmmla))] +pub fn svmmla_f64(op1: svfloat64_t, op2: svfloat64_t, op3: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmmla.nxv2f64.nxv2f64" + )] + fn _svmmla_f64(op1: svfloat64_t, op2: svfloat64_t, op3: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmmla_f64(op1, op2, op3) } +} +#[doc = "Matrix multiply-accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmmla[_s32])"] +#[inline] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smmla))] +pub fn svmmla_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smmla.nxv4i32")] + fn _svmmla_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t; + } + unsafe { _svmmla_s32(op1, op2, op3) } +} +#[doc = "Matrix multiply-accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmmla[_u32])"] +#[inline] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ummla))] +pub fn svmmla_u32(op1: svuint32_t, op2: svuint8_t, op3: svuint8_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ummla.nxv4i32")] + fn _svmmla_u32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t; + } + unsafe { _svmmla_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Move"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmov[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svmov_b_z(pg: svbool_t, op: svbool_t) -> svbool_t { + svand_b_z(pg, op, op) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmsb.nxv4f32")] + fn _svmsb_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svmsb_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmsb_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmsb_f32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmsb_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmsb_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmsb_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmsb.nxv2f64")] + fn _svmsb_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svmsb_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmsb_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmsb_f64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmsb_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmsb_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmsb_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.msb.nxv16i8")] + fn _svmsb_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svmsb_s8_m(pg, op1, op2, op3) } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmsb_s8_m(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmsb_s8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmsb_s8_x(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmsb_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmsb_s8_z(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.msb.nxv8i16")] + fn _svmsb_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) + -> svint16_t; + } + unsafe { _svmsb_s16_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmsb_s16_m(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmsb_s16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmsb_s16_x(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmsb_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmsb_s16_z(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.msb.nxv4i32")] + fn _svmsb_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) + -> svint32_t; + } + unsafe { _svmsb_s32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmsb_s32_m(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmsb_s32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmsb_s32_x(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmsb_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmsb_s32_z(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.msb.nxv2i64")] + fn _svmsb_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) + -> svint64_t; + } + unsafe { _svmsb_s64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmsb_s64_m(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmsb_s64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmsb_s64_x(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmsb_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmsb_s64_z(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svmsb_s8_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmsb_u8_m(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmsb_u8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmsb_u8_x(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmsb_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmsb_u8_z(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svmsb_s16_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmsb_u16_m(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmsb_u16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmsb_u16_x(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmsb_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmsb_u16_z(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svmsb_s32_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmsb_u32_m(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmsb_u32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmsb_u32_x(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmsb_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmsb_u32_z(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svmsb_s64_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmsb_u64_m(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmsb_u64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmsb_u64_x(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmsb_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmsb_u64_z(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmul.nxv4f32")] + fn _svmul_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmul_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmul_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmul_f32_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmul_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmul_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmul_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmul.nxv2f64")] + fn _svmul_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmul_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmul_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmul_f64_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmul_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmul_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmul_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mul.nxv16i8")] + fn _svmul_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmul_s8_m(pg, op1, op2) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmul_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmul_s8_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmul_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmul_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmul_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mul.nxv8i16")] + fn _svmul_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmul_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmul_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmul_s16_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmul_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmul_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmul_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mul.nxv4i32")] + fn _svmul_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmul_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmul_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmul_s32_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmul_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmul_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmul_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mul.nxv2i64")] + fn _svmul_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmul_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmul_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmul_s64_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmul_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmul_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmul_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svmul_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmul_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmul_u8_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmul_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmul_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmul_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svmul_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmul_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmul_u16_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmul_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmul_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmul_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svmul_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmul_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmul_u32_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmul_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmul_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmul_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svmul_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmul_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmul_u64_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmul_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmul_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmul_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smulh.nxv16i8")] + fn _svmulh_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmulh_s8_m(pg, op1, op2) } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmulh_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmulh_s8_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmulh_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmulh_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmulh_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smulh.nxv8i16")] + fn _svmulh_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmulh_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmulh_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmulh_s16_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmulh_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmulh_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmulh_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smulh.nxv4i32")] + fn _svmulh_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmulh_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmulh_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmulh_s32_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmulh_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmulh_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmulh_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smulh.nxv2i64")] + fn _svmulh_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmulh_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmulh_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmulh_s64_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmulh_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmulh_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmulh_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umulh.nxv16i8")] + fn _svmulh_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmulh_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmulh_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmulh_u8_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmulh_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmulh_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmulh_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umulh.nxv8i16")] + fn _svmulh_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmulh_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmulh_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmulh_u16_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmulh_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmulh_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmulh_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umulh.nxv4i32")] + fn _svmulh_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmulh_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmulh_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmulh_u32_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmulh_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmulh_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmulh_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umulh.nxv2i64")] + fn _svmulh_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmulh_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmulh_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmulh_u64_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmulh_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmulh_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmulh_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmulx.nxv4f32")] + fn _svmulx_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmulx_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmulx_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmulx_f32_m(pg, op1, op2) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmulx_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmulx_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmulx_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmulx.nxv2f64")] + fn _svmulx_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmulx_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmulx_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmulx_f64_m(pg, op1, op2) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmulx_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmulx_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmulx_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Bitwise NAND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnand[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nand))] +pub fn svnand_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nand.z.nxv16i1")] + fn _svnand_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svnand_b_z(pg, op1, op2) } +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fneg))] +pub fn svneg_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fneg.nxv4f32")] + fn _svneg_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svneg_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fneg))] +pub fn svneg_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svneg_f32_m(op, pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fneg))] +pub fn svneg_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svneg_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fneg))] +pub fn svneg_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fneg.nxv2f64")] + fn _svneg_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svneg_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fneg))] +pub fn svneg_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svneg_f64_m(op, pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fneg))] +pub fn svneg_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svneg_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.neg.nxv16i8")] + fn _svneg_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svneg_s8_m(inactive, pg, op) } +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t { + svneg_s8_m(op, pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t { + svneg_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.neg.nxv8i16")] + fn _svneg_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svneg_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svneg_s16_m(op, pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svneg_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.neg.nxv4i32")] + fn _svneg_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svneg_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svneg_s32_m(op, pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svneg_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.neg.nxv2i64")] + fn _svneg_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svneg_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svneg_s64_m(op, pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svneg_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmad.nxv4f32")] + fn _svnmad_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svnmad_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmad_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmad_f32_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmad_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmad_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmad_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmad.nxv2f64")] + fn _svnmad_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svnmad_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmad_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmad_f64_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmad_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmad_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmad_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmla.nxv4f32")] + fn _svnmla_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svnmla_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmla_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmla_f32_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmla_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmla_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmla_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmla.nxv2f64")] + fn _svnmla_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svnmla_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmla_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmla_f64_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmla_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmla_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmla_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmls.nxv4f32")] + fn _svnmls_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svnmls_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmls_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmls_f32_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmls_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmls_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmls_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmls.nxv2f64")] + fn _svnmls_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svnmls_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmls_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmls_f64_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmls_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmls_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmls_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmsb.nxv4f32")] + fn _svnmsb_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svnmsb_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmsb_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmsb_f32_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmsb_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmsb_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmsb_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmsb.nxv2f64")] + fn _svnmsb_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svnmsb_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmsb_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmsb_f64_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmsb_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmsb_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmsb_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Bitwise NOR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnor[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nor))] +pub fn svnor_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nor.z.nxv16i1")] + fn _svnor_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svnor_b_z(pg, op1, op2) } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_b_z(pg: svbool_t, op: svbool_t) -> svbool_t { + sveor_b_z(pg, op, pg) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.not.nxv16i8")] + fn _svnot_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svnot_s8_m(inactive, pg, op) } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t { + svnot_s8_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t { + svnot_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.not.nxv8i16")] + fn _svnot_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svnot_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svnot_s16_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svnot_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.not.nxv4i32")] + fn _svnot_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svnot_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svnot_s32_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svnot_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.not.nxv2i64")] + fn _svnot_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svnot_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svnot_s64_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svnot_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_t { + unsafe { svnot_s8_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svnot_u8_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svnot_u8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t { + unsafe { svnot_s16_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svnot_u16_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svnot_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svnot_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svnot_u32_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svnot_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svnot_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svnot_u64_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svnot_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Bitwise inclusive OR, inverting second argument"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorn[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orn))] +pub fn svorn_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orn.z.nxv16i1")] + fn _svorn_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svorn_b_z(pg, op1, op2) } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orr.z.nxv16i1")] + fn _svorr_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svorr_b_z(pg, op1, op2) } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orr.nxv16i8")] + fn _svorr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svorr_s8_m(pg, op1, op2) } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svorr_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svorr_s8_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svorr_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svorr_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svorr_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orr.nxv8i16")] + fn _svorr_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svorr_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svorr_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svorr_s16_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svorr_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svorr_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svorr_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orr.nxv4i32")] + fn _svorr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svorr_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svorr_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svorr_s32_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svorr_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svorr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svorr_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orr.nxv2i64")] + fn _svorr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svorr_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svorr_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svorr_s64_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svorr_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svorr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svorr_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svorr_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svorr_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svorr_u8_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svorr_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svorr_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svorr_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svorr_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svorr_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svorr_u16_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svorr_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svorr_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svorr_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svorr_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svorr_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svorr_u32_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svorr_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svorr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svorr_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svorr_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svorr_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svorr_u64_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svorr_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svorr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svorr_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_s8(pg: svbool_t, op: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orv.nxv16i8")] + fn _svorv_s8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svorv_s8(pg, op) } +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_s16(pg: svbool_t, op: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orv.nxv8i16")] + fn _svorv_s16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svorv_s16(pg.sve_into(), op) } +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_s32(pg: svbool_t, op: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orv.nxv4i32")] + fn _svorv_s32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svorv_s32(pg.sve_into(), op) } +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orv.nxv2i64")] + fn _svorv_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svorv_s64(pg.sve_into(), op) } +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_u8(pg: svbool_t, op: svuint8_t) -> u8 { + unsafe { svorv_s8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_u16(pg: svbool_t, op: svuint16_t) -> u16 { + unsafe { svorv_s16(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_u32(pg: svbool_t, op: svuint32_t) -> u32 { + unsafe { svorv_s32(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe { svorv_s64(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Set all predicate elements to false"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpfalse[_b])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svpfalse_b() -> svbool_t { + svdupq_n_b8( + false, false, false, false, false, false, false, false, false, false, false, false, false, + false, false, false, + ) +} +#[doc = "Set the first active predicate element to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpfirst[_b])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pfirst))] +pub fn svpfirst_b(pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pfirst.nxv16i1")] + fn _svpfirst_b(pg: svbool_t, op: svbool_t) -> svbool_t; + } + unsafe { _svpfirst_b(pg, op) } +} +#[doc = "Find next active predicate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpnext_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pnext))] +pub fn svpnext_b8(pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pnext.nxv16i1")] + fn _svpnext_b8(pg: svbool_t, op: svbool_t) -> svbool_t; + } + unsafe { _svpnext_b8(pg, op) } +} +#[doc = "Find next active predicate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpnext_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pnext))] +pub fn svpnext_b16(pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pnext.nxv8i1")] + fn _svpnext_b16(pg: svbool8_t, op: svbool8_t) -> svbool8_t; + } + unsafe { _svpnext_b16(pg.sve_into(), op.sve_into()).sve_into() } +} +#[doc = "Find next active predicate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpnext_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pnext))] +pub fn svpnext_b32(pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pnext.nxv4i1")] + fn _svpnext_b32(pg: svbool4_t, op: svbool4_t) -> svbool4_t; + } + unsafe { _svpnext_b32(pg.sve_into(), op.sve_into()).sve_into() } +} +#[doc = "Find next active predicate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpnext_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pnext))] +pub fn svpnext_b64(pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pnext.nxv2i1")] + fn _svpnext_b64(pg: svbool2_t, op: svbool2_t) -> svbool2_t; + } + unsafe { _svpnext_b64(pg.sve_into(), op.sve_into()).sve_into() } +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfb(pg: svbool_t, base: *const T) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.prf.nxv16i1")] + fn _svprfb(pg: svbool_t, base: *const crate::ffi::c_void, op: svprfop); + } + _svprfb(pg, base as *const crate::ffi::c_void, OP) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfh(pg: svbool_t, base: *const T) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.prf.nxv8i1")] + fn _svprfh(pg: svbool8_t, base: *const crate::ffi::c_void, op: svprfop); + } + _svprfh(pg.sve_into(), base as *const crate::ffi::c_void, OP) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfw(pg: svbool_t, base: *const T) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.prf.nxv4i1")] + fn _svprfw(pg: svbool4_t, base: *const crate::ffi::c_void, op: svprfop); + } + _svprfw(pg.sve_into(), base as *const crate::ffi::c_void, OP) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfd(pg: svbool_t, base: *const T) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.prf.nxv2i1")] + fn _svprfd(pg: svbool2_t, base: *const crate::ffi::c_void, op: svprfop); + } + _svprfd(pg.sve_into(), base as *const crate::ffi::c_void, OP) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather_[s32]offset)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfb_gather_s32offset( + pg: svbool_t, + base: *const T, + offsets: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfb.gather.sxtw.index.nxv4i32" + )] + fn _svprfb_gather_s32offset( + pg: svbool4_t, + base: *const crate::ffi::c_void, + offsets: svint32_t, + op: svprfop, + ); + } + _svprfb_gather_s32offset( + pg.sve_into(), + base as *const crate::ffi::c_void, + offsets, + OP, + ) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather_[s32]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfh_gather_s32index( + pg: svbool_t, + base: *const T, + indices: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfh.gather.sxtw.index.nxv4i32" + )] + fn _svprfh_gather_s32index( + pg: svbool4_t, + base: *const crate::ffi::c_void, + indices: svint32_t, + op: svprfop, + ); + } + _svprfh_gather_s32index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices, + OP, + ) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather_[s32]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfw_gather_s32index( + pg: svbool_t, + base: *const T, + indices: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfw.gather.sxtw.index.nxv4i32" + )] + fn _svprfw_gather_s32index( + pg: svbool4_t, + base: *const crate::ffi::c_void, + indices: svint32_t, + op: svprfop, + ); + } + _svprfw_gather_s32index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices, + OP, + ) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather_[s32]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfd_gather_s32index( + pg: svbool_t, + base: *const T, + indices: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfd.gather.sxtw.index.nxv4i32" + )] + fn _svprfd_gather_s32index( + pg: svbool4_t, + base: *const crate::ffi::c_void, + indices: svint32_t, + op: svprfop, + ); + } + _svprfd_gather_s32index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices, + OP, + ) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather_[s64]offset)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfb_gather_s64offset( + pg: svbool_t, + base: *const T, + offsets: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfb.gather.index.nxv2i64" + )] + fn _svprfb_gather_s64offset( + pg: svbool2_t, + base: *const crate::ffi::c_void, + offsets: svint64_t, + op: svprfop, + ); + } + _svprfb_gather_s64offset( + pg.sve_into(), + base as *const crate::ffi::c_void, + offsets, + OP, + ) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather_[s64]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfh_gather_s64index( + pg: svbool_t, + base: *const T, + indices: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfh.gather.index.nxv2i64" + )] + fn _svprfh_gather_s64index( + pg: svbool2_t, + base: *const crate::ffi::c_void, + indices: svint64_t, + op: svprfop, + ); + } + _svprfh_gather_s64index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices, + OP, + ) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather_[s64]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfw_gather_s64index( + pg: svbool_t, + base: *const T, + indices: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfw.gather.index.nxv2i64" + )] + fn _svprfw_gather_s64index( + pg: svbool2_t, + base: *const crate::ffi::c_void, + indices: svint64_t, + op: svprfop, + ); + } + _svprfw_gather_s64index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices, + OP, + ) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather_[s64]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfd_gather_s64index( + pg: svbool_t, + base: *const T, + indices: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfd.gather.index.nxv2i64" + )] + fn _svprfd_gather_s64index( + pg: svbool2_t, + base: *const crate::ffi::c_void, + indices: svint64_t, + op: svprfop, + ); + } + _svprfd_gather_s64index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices, + OP, + ) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather_[u32]offset)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfb_gather_u32offset( + pg: svbool_t, + base: *const T, + offsets: svuint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfb.gather.uxtw.index.nxv4i32" + )] + fn _svprfb_gather_u32offset( + pg: svbool4_t, + base: *const crate::ffi::c_void, + offsets: svint32_t, + op: svprfop, + ); + } + _svprfb_gather_u32offset( + pg.sve_into(), + base as *const crate::ffi::c_void, + offsets.as_signed(), + OP, + ) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather_[u32]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfh_gather_u32index( + pg: svbool_t, + base: *const T, + indices: svuint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfh.gather.uxtw.index.nxv4i32" + )] + fn _svprfh_gather_u32index( + pg: svbool4_t, + base: *const crate::ffi::c_void, + indices: svint32_t, + op: svprfop, + ); + } + _svprfh_gather_u32index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices.as_signed(), + OP, + ) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather_[u32]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfw_gather_u32index( + pg: svbool_t, + base: *const T, + indices: svuint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfw.gather.uxtw.index.nxv4i32" + )] + fn _svprfw_gather_u32index( + pg: svbool4_t, + base: *const crate::ffi::c_void, + indices: svint32_t, + op: svprfop, + ); + } + _svprfw_gather_u32index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices.as_signed(), + OP, + ) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather_[u32]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfd_gather_u32index( + pg: svbool_t, + base: *const T, + indices: svuint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfd.gather.uxtw.index.nxv4i32" + )] + fn _svprfd_gather_u32index( + pg: svbool4_t, + base: *const crate::ffi::c_void, + indices: svint32_t, + op: svprfop, + ); + } + _svprfd_gather_u32index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices.as_signed(), + OP, + ) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather_[u64]offset)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfb_gather_u64offset( + pg: svbool_t, + base: *const T, + offsets: svuint64_t, +) { + svprfb_gather_s64offset::(pg, base, offsets.as_signed()) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather_[u64]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfh_gather_u64index( + pg: svbool_t, + base: *const T, + indices: svuint64_t, +) { + svprfh_gather_s64index::(pg, base, indices.as_signed()) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather_[u64]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfw_gather_u64index( + pg: svbool_t, + base: *const T, + indices: svuint64_t, +) { + svprfw_gather_s64index::(pg, base, indices.as_signed()) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather_[u64]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfd_gather_u64index( + pg: svbool_t, + base: *const T, + indices: svuint64_t, +) { + svprfd_gather_s64index::(pg, base, indices.as_signed()) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather[_u32base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfb_gather_u32base(pg: svbool_t, bases: svuint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32" + )] + fn _svprfb_gather_u32base(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop); + } + _svprfb_gather_u32base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather[_u32base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfh_gather_u32base(pg: svbool_t, bases: svuint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32" + )] + fn _svprfh_gather_u32base(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop); + } + _svprfh_gather_u32base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather[_u32base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfw_gather_u32base(pg: svbool_t, bases: svuint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32" + )] + fn _svprfw_gather_u32base(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop); + } + _svprfw_gather_u32base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather[_u32base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfd_gather_u32base(pg: svbool_t, bases: svuint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32" + )] + fn _svprfd_gather_u32base(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop); + } + _svprfd_gather_u32base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather[_u64base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfb_gather_u64base(pg: svbool_t, bases: svuint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64" + )] + fn _svprfb_gather_u64base(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop); + } + _svprfb_gather_u64base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather[_u64base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfh_gather_u64base(pg: svbool_t, bases: svuint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfh.gather.scalar.offset.nxv2i64" + )] + fn _svprfh_gather_u64base(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop); + } + _svprfh_gather_u64base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather[_u64base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfw_gather_u64base(pg: svbool_t, bases: svuint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfw.gather.scalar.offset.nxv2i64" + )] + fn _svprfw_gather_u64base(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop); + } + _svprfw_gather_u64base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather[_u64base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfd_gather_u64base(pg: svbool_t, bases: svuint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfd.gather.scalar.offset.nxv2i64" + )] + fn _svprfd_gather_u64base(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop); + } + _svprfd_gather_u64base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather[_u32base]_offset)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfb_gather_u32base_offset( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32" + )] + fn _svprfb_gather_u32base_offset(pg: svbool4_t, bases: svint32_t, offset: i64, op: svprfop); + } + _svprfb_gather_u32base_offset(pg.sve_into(), bases.as_signed(), offset, OP) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather[_u32base]_index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfh_gather_u32base_index( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32" + )] + fn _svprfh_gather_u32base_index(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop); + } + _svprfh_gather_u32base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(1), OP) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather[_u32base]_index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfw_gather_u32base_index( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32" + )] + fn _svprfw_gather_u32base_index(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop); + } + _svprfw_gather_u32base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(2), OP) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather[_u32base]_index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfd_gather_u32base_index( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32" + )] + fn _svprfd_gather_u32base_index(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop); + } + _svprfd_gather_u32base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(3), OP) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather[_u64base]_offset)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfb_gather_u64base_offset( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64" + )] + fn _svprfb_gather_u64base_offset(pg: svbool2_t, bases: svint64_t, offset: i64, op: svprfop); + } + _svprfb_gather_u64base_offset(pg.sve_into(), bases.as_signed(), offset, OP) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather[_u64base]_index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfh_gather_u64base_index( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfh.gather.scalar.offset.nxv2i64" + )] + fn _svprfh_gather_u64base_index(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop); + } + _svprfh_gather_u64base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(1), OP) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather[_u64base]_index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfw_gather_u64base_index( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfw.gather.scalar.offset.nxv2i64" + )] + fn _svprfw_gather_u64base_index(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop); + } + _svprfw_gather_u64base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(2), OP) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather[_u64base]_index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfd_gather_u64base_index( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfd.gather.scalar.offset.nxv2i64" + )] + fn _svprfd_gather_u64base_index(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop); + } + _svprfd_gather_u64base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(3), OP) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_vnum)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfb_vnum(pg: svbool_t, base: *const T, vnum: i64) { + svprfb::(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_vnum)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfh_vnum(pg: svbool_t, base: *const T, vnum: i64) { + svprfh::(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_vnum)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfw_vnum(pg: svbool_t, base: *const T, vnum: i64) { + svprfw::(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_vnum)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfd_vnum(pg: svbool_t, base: *const T, vnum: i64) { + svprfd::(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Test whether any active element is true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptest_any)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ptest))] +pub fn svptest_any(pg: svbool_t, op: svbool_t) -> bool { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ptest.any.nxv16i1" + )] + fn _svptest_any(pg: svbool_t, op: svbool_t) -> bool; + } + unsafe { _svptest_any(pg, op) } +} +#[doc = "Test whether first active element is true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptest_first)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ptest))] +pub fn svptest_first(pg: svbool_t, op: svbool_t) -> bool { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ptest.first.nxv16i1" + )] + fn _svptest_first(pg: svbool_t, op: svbool_t) -> bool; + } + unsafe { _svptest_first(pg, op) } +} +#[doc = "Test whether last active element is true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptest_last)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ptest))] +pub fn svptest_last(pg: svbool_t, op: svbool_t) -> bool { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ptest.last.nxv16i1" + )] + fn _svptest_last(pg: svbool_t, op: svbool_t) -> bool; + } + unsafe { _svptest_last(pg, op) } +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ptrue))] +pub fn svptrue_b8() -> svbool_t { + svptrue_pat_b8::<{ svpattern::SV_ALL }>() +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ptrue))] +pub fn svptrue_b16() -> svbool_t { + svptrue_pat_b16::<{ svpattern::SV_ALL }>() +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ptrue))] +pub fn svptrue_b32() -> svbool_t { + svptrue_pat_b32::<{ svpattern::SV_ALL }>() +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ptrue))] +pub fn svptrue_b64() -> svbool_t { + svptrue_pat_b64::<{ svpattern::SV_ALL }>() +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_pat_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (ptrue , PATTERN = { svpattern :: SV_ALL }))] +pub fn svptrue_pat_b8() -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ptrue.nxv16i1")] + fn _svptrue_pat_b8(pattern: svpattern) -> svbool_t; + } + unsafe { _svptrue_pat_b8(PATTERN) } +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_pat_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (ptrue , PATTERN = { svpattern :: SV_ALL }))] +pub fn svptrue_pat_b16() -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ptrue.nxv8i1")] + fn _svptrue_pat_b16(pattern: svpattern) -> svbool8_t; + } + unsafe { _svptrue_pat_b16(PATTERN).sve_into() } +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_pat_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (ptrue , PATTERN = { svpattern :: SV_ALL }))] +pub fn svptrue_pat_b32() -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ptrue.nxv4i1")] + fn _svptrue_pat_b32(pattern: svpattern) -> svbool4_t; + } + unsafe { _svptrue_pat_b32(PATTERN).sve_into() } +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_pat_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (ptrue , PATTERN = { svpattern :: SV_ALL }))] +pub fn svptrue_pat_b64() -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ptrue.nxv2i1")] + fn _svptrue_pat_b64(pattern: svpattern) -> svbool2_t; + } + unsafe { _svptrue_pat_b64(PATTERN).sve_into() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqadd.x.nxv16i8" + )] + fn _svqadd_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqadd_s8(op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s8(op1: svint8_t, op2: i8) -> svint8_t { + svqadd_s8(op1, svdup_n_s8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqadd.x.nxv8i16" + )] + fn _svqadd_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqadd_s16(op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s16(op1: svint16_t, op2: i16) -> svint16_t { + svqadd_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqadd.x.nxv4i32" + )] + fn _svqadd_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqadd_s32(op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s32(op1: svint32_t, op2: i32) -> svint32_t { + svqadd_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqadd.x.nxv2i64" + )] + fn _svqadd_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqadd_s64(op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s64(op1: svint64_t, op2: i64) -> svint64_t { + svqadd_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqadd.x.nxv16i8" + )] + fn _svqadd_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqadd_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svqadd_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqadd.x.nxv8i16" + )] + fn _svqadd_u16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqadd_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t { + svqadd_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqadd.x.nxv4i32" + )] + fn _svqadd_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqadd_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + svqadd_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqadd.x.nxv2i64" + )] + fn _svqadd_u64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqadd_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + svqadd_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecb, IMM_FACTOR = 1))] +pub fn svqdecb_n_s32(op: i32) -> i32 { + svqdecb_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdech, IMM_FACTOR = 1))] +pub fn svqdech_n_s32(op: i32) -> i32 { + svqdech_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecw, IMM_FACTOR = 1))] +pub fn svqdecw_n_s32(op: i32) -> i32 { + svqdecw_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecd, IMM_FACTOR = 1))] +pub fn svqdecd_n_s32(op: i32) -> i32 { + svqdecd_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecb, IMM_FACTOR = 1))] +pub fn svqdecb_n_s64(op: i64) -> i64 { + svqdecb_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdech, IMM_FACTOR = 1))] +pub fn svqdech_n_s64(op: i64) -> i64 { + svqdech_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecw, IMM_FACTOR = 1))] +pub fn svqdecw_n_s64(op: i64) -> i64 { + svqdecw_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecd, IMM_FACTOR = 1))] +pub fn svqdecd_n_s64(op: i64) -> i64 { + svqdecd_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecb, IMM_FACTOR = 1))] +pub fn svqdecb_n_u32(op: u32) -> u32 { + svqdecb_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdech, IMM_FACTOR = 1))] +pub fn svqdech_n_u32(op: u32) -> u32 { + svqdech_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecw, IMM_FACTOR = 1))] +pub fn svqdecw_n_u32(op: u32) -> u32 { + svqdecw_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecd, IMM_FACTOR = 1))] +pub fn svqdecd_n_u32(op: u32) -> u32 { + svqdecd_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecb, IMM_FACTOR = 1))] +pub fn svqdecb_n_u64(op: u64) -> u64 { + svqdecb_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdech, IMM_FACTOR = 1))] +pub fn svqdech_n_u64(op: u64) -> u64 { + svqdech_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecw, IMM_FACTOR = 1))] +pub fn svqdecw_n_u64(op: u64) -> u64 { + svqdecw_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecd, IMM_FACTOR = 1))] +pub fn svqdecd_n_u64(op: u64) -> u64 { + svqdecd_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb_pat[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecb_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecb.n32")] + fn _svqdecb_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdecb_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdech_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdech.n32")] + fn _svqdech_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdech_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecw_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecw.n32")] + fn _svqdecw_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdecw_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecd_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecd.n32")] + fn _svqdecd_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdecd_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb_pat[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecb_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecb.n64")] + fn _svqdecb_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdecb_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdech_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdech.n64")] + fn _svqdech_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdech_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecw_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecw.n64")] + fn _svqdecw_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdecw_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecd_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecd.n64")] + fn _svqdecd_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdecd_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb_pat[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecb_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecb.n32")] + fn _svqdecb_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdecb_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdech_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdech.n32")] + fn _svqdech_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdech_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecw_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecw.n32")] + fn _svqdecw_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdecw_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecd_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecd.n32")] + fn _svqdecd_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdecd_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb_pat[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecb_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecb.n64")] + fn _svqdecb_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdecb_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdech_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdech.n64")] + fn _svqdech_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdech_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecw_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecw.n64")] + fn _svqdecw_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdecw_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecd_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecd.n64")] + fn _svqdecd_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdecd_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdech_pat_s16( + op: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdech.nxv8i16")] + fn _svqdech_pat_s16(op: svint16_t, pattern: svpattern, imm_factor: i32) -> svint16_t; + } + unsafe { _svqdech_pat_s16(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecw_pat_s32( + op: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecw.nxv4i32")] + fn _svqdecw_pat_s32(op: svint32_t, pattern: svpattern, imm_factor: i32) -> svint32_t; + } + unsafe { _svqdecw_pat_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecd_pat_s64( + op: svint64_t, +) -> svint64_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecd.nxv2i64")] + fn _svqdecd_pat_s64(op: svint64_t, pattern: svpattern, imm_factor: i32) -> svint64_t; + } + unsafe { _svqdecd_pat_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdech_pat_u16( + op: svuint16_t, +) -> svuint16_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdech.nxv8i16")] + fn _svqdech_pat_u16(op: svint16_t, pattern: svpattern, imm_factor: i32) -> svint16_t; + } + unsafe { _svqdech_pat_u16(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecw_pat_u32( + op: svuint32_t, +) -> svuint32_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecw.nxv4i32")] + fn _svqdecw_pat_u32(op: svint32_t, pattern: svpattern, imm_factor: i32) -> svint32_t; + } + unsafe { _svqdecw_pat_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecd_pat_u64( + op: svuint64_t, +) -> svuint64_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecd.nxv2i64")] + fn _svqdecd_pat_u64(op: svint64_t, pattern: svpattern, imm_factor: i32) -> svint64_t; + } + unsafe { _svqdecd_pat_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdech, IMM_FACTOR = 1))] +pub fn svqdech_s16(op: svint16_t) -> svint16_t { + svqdech_pat_s16::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecw, IMM_FACTOR = 1))] +pub fn svqdecw_s32(op: svint32_t) -> svint32_t { + svqdecw_pat_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecd, IMM_FACTOR = 1))] +pub fn svqdecd_s64(op: svint64_t) -> svint64_t { + svqdecd_pat_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdech, IMM_FACTOR = 1))] +pub fn svqdech_u16(op: svuint16_t) -> svuint16_t { + svqdech_pat_u16::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecw, IMM_FACTOR = 1))] +pub fn svqdecw_u32(op: svuint32_t) -> svuint32_t { + svqdecw_pat_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecd, IMM_FACTOR = 1))] +pub fn svqdecd_u64(op: svuint64_t) -> svuint64_t { + svqdecd_pat_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s32]_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s32_b8(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n32.nxv16i1" + )] + fn _svqdecp_n_s32_b8(op: i32, pg: svbool_t) -> i32; + } + unsafe { _svqdecp_n_s32_b8(op, pg) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s32]_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s32_b16(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n32.nxv8i1" + )] + fn _svqdecp_n_s32_b16(op: i32, pg: svbool8_t) -> i32; + } + unsafe { _svqdecp_n_s32_b16(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s32]_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s32_b32(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n32.nxv4i1" + )] + fn _svqdecp_n_s32_b32(op: i32, pg: svbool4_t) -> i32; + } + unsafe { _svqdecp_n_s32_b32(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s32]_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s32_b64(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n32.nxv2i1" + )] + fn _svqdecp_n_s32_b64(op: i32, pg: svbool2_t) -> i32; + } + unsafe { _svqdecp_n_s32_b64(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s64]_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s64_b8(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n64.nxv16i1" + )] + fn _svqdecp_n_s64_b8(op: i64, pg: svbool_t) -> i64; + } + unsafe { _svqdecp_n_s64_b8(op, pg) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s64]_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s64_b16(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n64.nxv8i1" + )] + fn _svqdecp_n_s64_b16(op: i64, pg: svbool8_t) -> i64; + } + unsafe { _svqdecp_n_s64_b16(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s64]_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s64_b32(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n64.nxv4i1" + )] + fn _svqdecp_n_s64_b32(op: i64, pg: svbool4_t) -> i64; + } + unsafe { _svqdecp_n_s64_b32(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s64]_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s64_b64(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n64.nxv2i1" + )] + fn _svqdecp_n_s64_b64(op: i64, pg: svbool2_t) -> i64; + } + unsafe { _svqdecp_n_s64_b64(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u32]_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u32_b8(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n32.nxv16i1" + )] + fn _svqdecp_n_u32_b8(op: i32, pg: svbool_t) -> i32; + } + unsafe { _svqdecp_n_u32_b8(op.as_signed(), pg).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u32]_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u32_b16(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n32.nxv8i1" + )] + fn _svqdecp_n_u32_b16(op: i32, pg: svbool8_t) -> i32; + } + unsafe { _svqdecp_n_u32_b16(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u32]_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u32_b32(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n32.nxv4i1" + )] + fn _svqdecp_n_u32_b32(op: i32, pg: svbool4_t) -> i32; + } + unsafe { _svqdecp_n_u32_b32(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u32]_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u32_b64(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n32.nxv2i1" + )] + fn _svqdecp_n_u32_b64(op: i32, pg: svbool2_t) -> i32; + } + unsafe { _svqdecp_n_u32_b64(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u64]_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u64_b8(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n64.nxv16i1" + )] + fn _svqdecp_n_u64_b8(op: i64, pg: svbool_t) -> i64; + } + unsafe { _svqdecp_n_u64_b8(op.as_signed(), pg).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u64]_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u64_b16(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n64.nxv8i1" + )] + fn _svqdecp_n_u64_b16(op: i64, pg: svbool8_t) -> i64; + } + unsafe { _svqdecp_n_u64_b16(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u64]_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u64_b32(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n64.nxv4i1" + )] + fn _svqdecp_n_u64_b32(op: i64, pg: svbool4_t) -> i64; + } + unsafe { _svqdecp_n_u64_b32(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u64]_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u64_b64(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n64.nxv2i1" + )] + fn _svqdecp_n_u64_b64(op: i64, pg: svbool2_t) -> i64; + } + unsafe { _svqdecp_n_u64_b64(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_s16(op: svint16_t, pg: svbool_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecp.nxv8i16")] + fn _svqdecp_s16(op: svint16_t, pg: svbool8_t) -> svint16_t; + } + unsafe { _svqdecp_s16(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_s32(op: svint32_t, pg: svbool_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecp.nxv4i32")] + fn _svqdecp_s32(op: svint32_t, pg: svbool4_t) -> svint32_t; + } + unsafe { _svqdecp_s32(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_s64(op: svint64_t, pg: svbool_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecp.nxv2i64")] + fn _svqdecp_s64(op: svint64_t, pg: svbool2_t) -> svint64_t; + } + unsafe { _svqdecp_s64(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_u16(op: svuint16_t, pg: svbool_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecp.nxv8i16")] + fn _svqdecp_u16(op: svint16_t, pg: svbool8_t) -> svint16_t; + } + unsafe { _svqdecp_u16(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_u32(op: svuint32_t, pg: svbool_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecp.nxv4i32")] + fn _svqdecp_u32(op: svint32_t, pg: svbool4_t) -> svint32_t; + } + unsafe { _svqdecp_u32(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_u64(op: svuint64_t, pg: svbool_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecp.nxv2i64")] + fn _svqdecp_u64(op: svint64_t, pg: svbool2_t) -> svint64_t; + } + unsafe { _svqdecp_u64(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincb, IMM_FACTOR = 1))] +pub fn svqincb_n_s32(op: i32) -> i32 { + svqincb_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqinch, IMM_FACTOR = 1))] +pub fn svqinch_n_s32(op: i32) -> i32 { + svqinch_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincw, IMM_FACTOR = 1))] +pub fn svqincw_n_s32(op: i32) -> i32 { + svqincw_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincd, IMM_FACTOR = 1))] +pub fn svqincd_n_s32(op: i32) -> i32 { + svqincd_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincb, IMM_FACTOR = 1))] +pub fn svqincb_n_s64(op: i64) -> i64 { + svqincb_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqinch, IMM_FACTOR = 1))] +pub fn svqinch_n_s64(op: i64) -> i64 { + svqinch_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincw, IMM_FACTOR = 1))] +pub fn svqincw_n_s64(op: i64) -> i64 { + svqincw_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincd, IMM_FACTOR = 1))] +pub fn svqincd_n_s64(op: i64) -> i64 { + svqincd_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincb, IMM_FACTOR = 1))] +pub fn svqincb_n_u32(op: u32) -> u32 { + svqincb_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqinch, IMM_FACTOR = 1))] +pub fn svqinch_n_u32(op: u32) -> u32 { + svqinch_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincw, IMM_FACTOR = 1))] +pub fn svqincw_n_u32(op: u32) -> u32 { + svqincw_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincd, IMM_FACTOR = 1))] +pub fn svqincd_n_u32(op: u32) -> u32 { + svqincd_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincb, IMM_FACTOR = 1))] +pub fn svqincb_n_u64(op: u64) -> u64 { + svqincb_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqinch, IMM_FACTOR = 1))] +pub fn svqinch_n_u64(op: u64) -> u64 { + svqinch_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincw, IMM_FACTOR = 1))] +pub fn svqincw_n_u64(op: u64) -> u64 { + svqincw_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincd, IMM_FACTOR = 1))] +pub fn svqincd_n_u64(op: u64) -> u64 { + svqincd_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb_pat[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincb_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincb.n32")] + fn _svqincb_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqincb_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqinch_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqinch.n32")] + fn _svqinch_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqinch_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincw_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincw.n32")] + fn _svqincw_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqincw_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincd_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincd.n32")] + fn _svqincd_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqincd_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb_pat[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincb_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincb.n64")] + fn _svqincb_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqincb_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqinch_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqinch.n64")] + fn _svqinch_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqinch_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincw_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincw.n64")] + fn _svqincw_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqincw_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincd_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincd.n64")] + fn _svqincd_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqincd_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb_pat[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincb_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincb.n32")] + fn _svqincb_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqincb_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqinch_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqinch.n32")] + fn _svqinch_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqinch_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincw_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincw.n32")] + fn _svqincw_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqincw_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincd_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincd.n32")] + fn _svqincd_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqincd_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb_pat[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincb_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincb.n64")] + fn _svqincb_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqincb_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqinch_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqinch.n64")] + fn _svqinch_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqinch_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincw_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincw.n64")] + fn _svqincw_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqincw_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincd_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincd.n64")] + fn _svqincd_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqincd_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqinch_pat_s16( + op: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqinch.nxv8i16")] + fn _svqinch_pat_s16(op: svint16_t, pattern: svpattern, imm_factor: i32) -> svint16_t; + } + unsafe { _svqinch_pat_s16(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincw_pat_s32( + op: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincw.nxv4i32")] + fn _svqincw_pat_s32(op: svint32_t, pattern: svpattern, imm_factor: i32) -> svint32_t; + } + unsafe { _svqincw_pat_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincd_pat_s64( + op: svint64_t, +) -> svint64_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincd.nxv2i64")] + fn _svqincd_pat_s64(op: svint64_t, pattern: svpattern, imm_factor: i32) -> svint64_t; + } + unsafe { _svqincd_pat_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqinch_pat_u16( + op: svuint16_t, +) -> svuint16_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqinch.nxv8i16")] + fn _svqinch_pat_u16(op: svint16_t, pattern: svpattern, imm_factor: i32) -> svint16_t; + } + unsafe { _svqinch_pat_u16(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincw_pat_u32( + op: svuint32_t, +) -> svuint32_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincw.nxv4i32")] + fn _svqincw_pat_u32(op: svint32_t, pattern: svpattern, imm_factor: i32) -> svint32_t; + } + unsafe { _svqincw_pat_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincd_pat_u64( + op: svuint64_t, +) -> svuint64_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincd.nxv2i64")] + fn _svqincd_pat_u64(op: svint64_t, pattern: svpattern, imm_factor: i32) -> svint64_t; + } + unsafe { _svqincd_pat_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqinch, IMM_FACTOR = 1))] +pub fn svqinch_s16(op: svint16_t) -> svint16_t { + svqinch_pat_s16::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincw, IMM_FACTOR = 1))] +pub fn svqincw_s32(op: svint32_t) -> svint32_t { + svqincw_pat_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincd, IMM_FACTOR = 1))] +pub fn svqincd_s64(op: svint64_t) -> svint64_t { + svqincd_pat_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqinch, IMM_FACTOR = 1))] +pub fn svqinch_u16(op: svuint16_t) -> svuint16_t { + svqinch_pat_u16::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincw, IMM_FACTOR = 1))] +pub fn svqincw_u32(op: svuint32_t) -> svuint32_t { + svqincw_pat_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincd, IMM_FACTOR = 1))] +pub fn svqincd_u64(op: svuint64_t) -> svuint64_t { + svqincd_pat_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s32]_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s32_b8(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n32.nxv16i1" + )] + fn _svqincp_n_s32_b8(op: i32, pg: svbool_t) -> i32; + } + unsafe { _svqincp_n_s32_b8(op, pg) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s32]_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s32_b16(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n32.nxv8i1" + )] + fn _svqincp_n_s32_b16(op: i32, pg: svbool8_t) -> i32; + } + unsafe { _svqincp_n_s32_b16(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s32]_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s32_b32(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n32.nxv4i1" + )] + fn _svqincp_n_s32_b32(op: i32, pg: svbool4_t) -> i32; + } + unsafe { _svqincp_n_s32_b32(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s32]_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s32_b64(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n32.nxv2i1" + )] + fn _svqincp_n_s32_b64(op: i32, pg: svbool2_t) -> i32; + } + unsafe { _svqincp_n_s32_b64(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s64]_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s64_b8(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n64.nxv16i1" + )] + fn _svqincp_n_s64_b8(op: i64, pg: svbool_t) -> i64; + } + unsafe { _svqincp_n_s64_b8(op, pg) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s64]_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s64_b16(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n64.nxv8i1" + )] + fn _svqincp_n_s64_b16(op: i64, pg: svbool8_t) -> i64; + } + unsafe { _svqincp_n_s64_b16(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s64]_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s64_b32(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n64.nxv4i1" + )] + fn _svqincp_n_s64_b32(op: i64, pg: svbool4_t) -> i64; + } + unsafe { _svqincp_n_s64_b32(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s64]_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s64_b64(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n64.nxv2i1" + )] + fn _svqincp_n_s64_b64(op: i64, pg: svbool2_t) -> i64; + } + unsafe { _svqincp_n_s64_b64(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u32]_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u32_b8(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n32.nxv16i1" + )] + fn _svqincp_n_u32_b8(op: i32, pg: svbool_t) -> i32; + } + unsafe { _svqincp_n_u32_b8(op.as_signed(), pg).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u32]_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u32_b16(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n32.nxv8i1" + )] + fn _svqincp_n_u32_b16(op: i32, pg: svbool8_t) -> i32; + } + unsafe { _svqincp_n_u32_b16(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u32]_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u32_b32(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n32.nxv4i1" + )] + fn _svqincp_n_u32_b32(op: i32, pg: svbool4_t) -> i32; + } + unsafe { _svqincp_n_u32_b32(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u32]_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u32_b64(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n32.nxv2i1" + )] + fn _svqincp_n_u32_b64(op: i32, pg: svbool2_t) -> i32; + } + unsafe { _svqincp_n_u32_b64(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u64]_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u64_b8(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n64.nxv16i1" + )] + fn _svqincp_n_u64_b8(op: i64, pg: svbool_t) -> i64; + } + unsafe { _svqincp_n_u64_b8(op.as_signed(), pg).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u64]_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u64_b16(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n64.nxv8i1" + )] + fn _svqincp_n_u64_b16(op: i64, pg: svbool8_t) -> i64; + } + unsafe { _svqincp_n_u64_b16(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u64]_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u64_b32(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n64.nxv4i1" + )] + fn _svqincp_n_u64_b32(op: i64, pg: svbool4_t) -> i64; + } + unsafe { _svqincp_n_u64_b32(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u64]_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u64_b64(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n64.nxv2i1" + )] + fn _svqincp_n_u64_b64(op: i64, pg: svbool2_t) -> i64; + } + unsafe { _svqincp_n_u64_b64(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_s16(op: svint16_t, pg: svbool_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincp.nxv8i16")] + fn _svqincp_s16(op: svint16_t, pg: svbool8_t) -> svint16_t; + } + unsafe { _svqincp_s16(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_s32(op: svint32_t, pg: svbool_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincp.nxv4i32")] + fn _svqincp_s32(op: svint32_t, pg: svbool4_t) -> svint32_t; + } + unsafe { _svqincp_s32(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_s64(op: svint64_t, pg: svbool_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincp.nxv2i64")] + fn _svqincp_s64(op: svint64_t, pg: svbool2_t) -> svint64_t; + } + unsafe { _svqincp_s64(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_u16(op: svuint16_t, pg: svbool_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincp.nxv8i16")] + fn _svqincp_u16(op: svint16_t, pg: svbool8_t) -> svint16_t; + } + unsafe { _svqincp_u16(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_u32(op: svuint32_t, pg: svbool_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincp.nxv4i32")] + fn _svqincp_u32(op: svint32_t, pg: svbool4_t) -> svint32_t; + } + unsafe { _svqincp_u32(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_u64(op: svuint64_t, pg: svbool_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincp.nxv2i64")] + fn _svqincp_u64(op: svint64_t, pg: svbool2_t) -> svint64_t; + } + unsafe { _svqincp_u64(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqsub.x.nxv16i8" + )] + fn _svqsub_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqsub_s8(op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s8(op1: svint8_t, op2: i8) -> svint8_t { + svqsub_s8(op1, svdup_n_s8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqsub.x.nxv8i16" + )] + fn _svqsub_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqsub_s16(op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s16(op1: svint16_t, op2: i16) -> svint16_t { + svqsub_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqsub.x.nxv4i32" + )] + fn _svqsub_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqsub_s32(op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s32(op1: svint32_t, op2: i32) -> svint32_t { + svqsub_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqsub.x.nxv2i64" + )] + fn _svqsub_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqsub_s64(op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s64(op1: svint64_t, op2: i64) -> svint64_t { + svqsub_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqsub.x.nxv16i8" + )] + fn _svqsub_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqsub_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svqsub_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqsub.x.nxv8i16" + )] + fn _svqsub_u16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqsub_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t { + svqsub_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqsub.x.nxv4i32" + )] + fn _svqsub_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqsub_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + svqsub_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqsub.x.nxv2i64" + )] + fn _svqsub_u64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqsub_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + svqsub_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rbit.nxv16i8")] + fn _svrbit_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svrbit_s8_m(inactive, pg, op) } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t { + svrbit_s8_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t { + svrbit_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rbit.nxv8i16")] + fn _svrbit_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svrbit_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svrbit_s16_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svrbit_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rbit.nxv4i32")] + fn _svrbit_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svrbit_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svrbit_s32_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svrbit_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rbit.nxv2i64")] + fn _svrbit_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svrbit_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svrbit_s64_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svrbit_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_t { + unsafe { svrbit_s8_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svrbit_u8_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svrbit_u8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t { + unsafe { svrbit_s16_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svrbit_u16_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svrbit_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svrbit_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrbit_u32_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrbit_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svrbit_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrbit_u64_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrbit_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Read FFR, returning predicate of succesfully loaded elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrdffr)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rdffr))] +pub fn svrdffr() -> svbool_t { + svrdffr_z(svptrue_b8()) +} +#[doc = "Read FFR, returning predicate of succesfully loaded elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrdffr_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rdffr))] +pub fn svrdffr_z(pg: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rdffr.z")] + fn _svrdffr_z(pg: svbool_t) -> svbool_t; + } + unsafe { _svrdffr_z(pg) } +} +#[doc = "Reciprocal estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpe))] +pub fn svrecpe_f32(op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frecpe.x.nxv4f32" + )] + fn _svrecpe_f32(op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrecpe_f32(op) } +} +#[doc = "Reciprocal estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpe))] +pub fn svrecpe_f64(op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frecpe.x.nxv2f64" + )] + fn _svrecpe_f64(op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrecpe_f64(op) } +} +#[doc = "Reciprocal step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecps[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecps))] +pub fn svrecps_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frecps.x.nxv4f32" + )] + fn _svrecps_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrecps_f32(op1, op2) } +} +#[doc = "Reciprocal step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecps[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecps))] +pub fn svrecps_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frecps.x.nxv2f64" + )] + fn _svrecps_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrecps_f64(op1, op2) } +} +#[doc = "Reciprocal exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpx))] +pub fn svrecpx_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frecpx.nxv4f32")] + fn _svrecpx_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrecpx_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reciprocal exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpx))] +pub fn svrecpx_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrecpx_f32_m(op, pg, op) +} +#[doc = "Reciprocal exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpx))] +pub fn svrecpx_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrecpx_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Reciprocal exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpx))] +pub fn svrecpx_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frecpx.nxv2f64")] + fn _svrecpx_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrecpx_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reciprocal exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpx))] +pub fn svrecpx_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrecpx_f64_m(op, pg, op) +} +#[doc = "Reciprocal exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpx))] +pub fn svrecpx_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrecpx_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_f32(op: svfloat32_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_f64(op: svfloat64_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_s8(op: svint8_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_s16(op: svint16_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_s32(op: svint32_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_s64(op: svint64_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_u8(op: svuint8_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_u16(op: svuint16_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_u32(op: svuint32_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_u64(op: svuint64_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_f32(op: svfloat32_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_f64(op: svfloat64_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_s8(op: svint8_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_s16(op: svint16_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_s32(op: svint32_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_s64(op: svint64_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_u8(op: svuint8_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_u16(op: svuint16_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_u32(op: svuint32_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_u64(op: svuint64_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_f32(op: svfloat32_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_f64(op: svfloat64_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_s8(op: svint8_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_s16(op: svint16_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_s32(op: svint32_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_s64(op: svint64_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_u8(op: svuint8_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_u16(op: svuint16_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_u32(op: svuint32_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_u64(op: svuint64_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_f32(op: svfloat32_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_f64(op: svfloat64_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_s8(op: svint8_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_s16(op: svint16_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_s32(op: svint32_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_s64(op: svint64_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_u8(op: svuint8_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_u16(op: svuint16_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_u32(op: svuint32_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_u64(op: svuint64_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_f32(op: svfloat32_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_f64(op: svfloat64_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_s8(op: svint8_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_s16(op: svint16_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_s32(op: svint32_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_s64(op: svint64_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_u8(op: svuint8_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_u16(op: svuint16_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_u32(op: svuint32_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_u64(op: svuint64_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_f32(op: svfloat32_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_f64(op: svfloat64_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_s8(op: svint8_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_s16(op: svint16_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_s32(op: svint32_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_s64(op: svint64_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_u8(op: svuint8_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_u16(op: svuint16_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_u32(op: svuint32_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_u64(op: svuint64_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_f32(op: svfloat32_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_f64(op: svfloat64_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_s8(op: svint8_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_s16(op: svint16_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_s32(op: svint32_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_s64(op: svint64_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_u8(op: svuint8_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_u16(op: svuint16_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_u32(op: svuint32_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_u64(op: svuint64_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_f32(op: svfloat32_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_f64(op: svfloat64_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_s8(op: svint8_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_s16(op: svint16_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_s32(op: svint32_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_s64(op: svint64_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_u8(op: svuint8_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_u16(op: svuint16_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_u32(op: svuint32_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_u64(op: svuint64_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_f32(op: svfloat32_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_f64(op: svfloat64_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_s8(op: svint8_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_s16(op: svint16_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_s32(op: svint32_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_s64(op: svint64_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_u8(op: svuint8_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_u16(op: svuint16_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_u32(op: svuint32_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_u64(op: svuint64_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_f32(op: svfloat32_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_f64(op: svfloat64_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_s8(op: svint8_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_s16(op: svint16_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_s32(op: svint32_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_s64(op: svint64_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_u8(op: svuint8_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_u16(op: svuint16_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_u32(op: svuint32_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_u64(op: svuint64_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_b16(op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.b16")] + fn _svrev_b16(op: svbool_t) -> svbool_t; + } + unsafe { _svrev_b16(op.sve_into()) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_b32(op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.b32")] + fn _svrev_b32(op: svbool_t) -> svbool_t; + } + unsafe { _svrev_b32(op.sve_into()) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_b64(op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.b64")] + fn _svrev_b64(op: svbool_t) -> svbool_t; + } + unsafe { _svrev_b64(op.sve_into()) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_f32(op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv4f32")] + fn _svrev_f32(op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrev_f32(op) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_f64(op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv2f64")] + fn _svrev_f64(op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrev_f64(op) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_s8(op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv16i8")] + fn _svrev_s8(op: svint8_t) -> svint8_t; + } + unsafe { _svrev_s8(op) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_s16(op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv8i16")] + fn _svrev_s16(op: svint16_t) -> svint16_t; + } + unsafe { _svrev_s16(op) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_s32(op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv4i32")] + fn _svrev_s32(op: svint32_t) -> svint32_t; + } + unsafe { _svrev_s32(op) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_s64(op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv2i64")] + fn _svrev_s64(op: svint64_t) -> svint64_t; + } + unsafe { _svrev_s64(op) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_u8(op: svuint8_t) -> svuint8_t { + unsafe { svrev_s8(op.as_signed()).as_unsigned() } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_u16(op: svuint16_t) -> svuint16_t { + unsafe { svrev_s16(op.as_signed()).as_unsigned() } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_u32(op: svuint32_t) -> svuint32_t { + unsafe { svrev_s32(op.as_signed()).as_unsigned() } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_u64(op: svuint64_t) -> svuint64_t { + unsafe { svrev_s64(op.as_signed()).as_unsigned() } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_b8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_b8(op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv16i1")] + fn _svrev_b8(op: svbool_t) -> svbool_t; + } + unsafe { _svrev_b8(op) } +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revb.nxv8i16")] + fn _svrevb_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svrevb_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svrevb_s16_m(op, pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svrevb_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revb.nxv4i32")] + fn _svrevb_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svrevb_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svrevb_s32_m(op, pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svrevb_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revb.nxv2i64")] + fn _svrevb_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svrevb_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svrevb_s64_m(op, pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svrevb_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t { + unsafe { svrevb_s16_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svrevb_u16_m(op, pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svrevb_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svrevb_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrevb_u32_m(op, pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrevb_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svrevb_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrevb_u64_m(op, pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrevb_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revh.nxv4i32")] + fn _svrevh_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svrevh_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svrevh_s32_m(op, pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svrevh_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revh.nxv2i64")] + fn _svrevh_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svrevh_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svrevh_s64_m(op, pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svrevh_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svrevh_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrevh_u32_m(op, pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrevh_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svrevh_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrevh_u64_m(op, pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrevh_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Reverse words within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revw))] +pub fn svrevw_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revw.nxv2i64")] + fn _svrevw_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svrevw_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse words within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revw))] +pub fn svrevw_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svrevw_s64_m(op, pg, op) +} +#[doc = "Reverse words within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revw))] +pub fn svrevw_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svrevw_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Reverse words within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revw))] +pub fn svrevw_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svrevw_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse words within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revw))] +pub fn svrevw_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrevw_u64_m(op, pg, op) +} +#[doc = "Reverse words within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revw))] +pub fn svrevw_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrevw_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Round to nearest, ties away from zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinta))] +pub fn svrinta_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frinta.nxv4f32")] + fn _svrinta_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrinta_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round to nearest, ties away from zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinta))] +pub fn svrinta_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrinta_f32_m(op, pg, op) +} +#[doc = "Round to nearest, ties away from zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinta))] +pub fn svrinta_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrinta_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Round to nearest, ties away from zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinta))] +pub fn svrinta_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frinta.nxv2f64")] + fn _svrinta_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrinta_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round to nearest, ties away from zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinta))] +pub fn svrinta_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrinta_f64_m(op, pg, op) +} +#[doc = "Round to nearest, ties away from zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinta))] +pub fn svrinta_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrinta_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Round using current rounding mode (inexact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinti))] +pub fn svrinti_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frinti.nxv4f32")] + fn _svrinti_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrinti_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round using current rounding mode (inexact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinti))] +pub fn svrinti_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrinti_f32_m(op, pg, op) +} +#[doc = "Round using current rounding mode (inexact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinti))] +pub fn svrinti_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrinti_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Round using current rounding mode (inexact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinti))] +pub fn svrinti_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frinti.nxv2f64")] + fn _svrinti_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrinti_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round using current rounding mode (inexact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinti))] +pub fn svrinti_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrinti_f64_m(op, pg, op) +} +#[doc = "Round using current rounding mode (inexact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinti))] +pub fn svrinti_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrinti_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Round towards -∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintm))] +pub fn svrintm_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintm.nxv4f32")] + fn _svrintm_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrintm_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round towards -∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintm))] +pub fn svrintm_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintm_f32_m(op, pg, op) +} +#[doc = "Round towards -∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintm))] +pub fn svrintm_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintm_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Round towards -∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintm))] +pub fn svrintm_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintm.nxv2f64")] + fn _svrintm_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrintm_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round towards -∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintm))] +pub fn svrintm_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintm_f64_m(op, pg, op) +} +#[doc = "Round towards -∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintm))] +pub fn svrintm_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintm_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Round to nearest, ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintn))] +pub fn svrintn_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintn.nxv4f32")] + fn _svrintn_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrintn_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round to nearest, ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintn))] +pub fn svrintn_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintn_f32_m(op, pg, op) +} +#[doc = "Round to nearest, ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintn))] +pub fn svrintn_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintn_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Round to nearest, ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintn))] +pub fn svrintn_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintn.nxv2f64")] + fn _svrintn_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrintn_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round to nearest, ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintn))] +pub fn svrintn_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintn_f64_m(op, pg, op) +} +#[doc = "Round to nearest, ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintn))] +pub fn svrintn_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintn_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Round towards +∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintp))] +pub fn svrintp_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintp.nxv4f32")] + fn _svrintp_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrintp_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round towards +∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintp))] +pub fn svrintp_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintp_f32_m(op, pg, op) +} +#[doc = "Round towards +∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintp))] +pub fn svrintp_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintp_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Round towards +∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintp))] +pub fn svrintp_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintp.nxv2f64")] + fn _svrintp_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrintp_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round towards +∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintp))] +pub fn svrintp_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintp_f64_m(op, pg, op) +} +#[doc = "Round towards +∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintp))] +pub fn svrintp_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintp_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Round using current rounding mode (exact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintx))] +pub fn svrintx_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintx.nxv4f32")] + fn _svrintx_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrintx_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round using current rounding mode (exact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintx))] +pub fn svrintx_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintx_f32_m(op, pg, op) +} +#[doc = "Round using current rounding mode (exact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintx))] +pub fn svrintx_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintx_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Round using current rounding mode (exact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintx))] +pub fn svrintx_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintx.nxv2f64")] + fn _svrintx_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrintx_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round using current rounding mode (exact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintx))] +pub fn svrintx_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintx_f64_m(op, pg, op) +} +#[doc = "Round using current rounding mode (exact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintx))] +pub fn svrintx_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintx_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Round towards zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintz))] +pub fn svrintz_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintz.nxv4f32")] + fn _svrintz_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrintz_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round towards zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintz))] +pub fn svrintz_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintz_f32_m(op, pg, op) +} +#[doc = "Round towards zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintz))] +pub fn svrintz_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintz_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Round towards zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintz))] +pub fn svrintz_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintz.nxv2f64")] + fn _svrintz_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrintz_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round towards zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintz))] +pub fn svrintz_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintz_f64_m(op, pg, op) +} +#[doc = "Round towards zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintz))] +pub fn svrintz_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintz_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Reciprocal square root estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frsqrte))] +pub fn svrsqrte_f32(op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frsqrte.x.nxv4f32" + )] + fn _svrsqrte_f32(op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrsqrte_f32(op) } +} +#[doc = "Reciprocal square root estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frsqrte))] +pub fn svrsqrte_f64(op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frsqrte.x.nxv2f64" + )] + fn _svrsqrte_f64(op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrsqrte_f64(op) } +} +#[doc = "Reciprocal square root step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrts[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frsqrts))] +pub fn svrsqrts_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frsqrts.x.nxv4f32" + )] + fn _svrsqrts_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrsqrts_f32(op1, op2) } +} +#[doc = "Reciprocal square root step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrts[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frsqrts))] +pub fn svrsqrts_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frsqrts.x.nxv2f64" + )] + fn _svrsqrts_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrsqrts_f64(op1, op2) } +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fscale.nxv4f32")] + fn _svscale_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svint32_t) -> svfloat32_t; + } + unsafe { _svscale_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: i32) -> svfloat32_t { + svscale_f32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svint32_t) -> svfloat32_t { + svscale_f32_m(pg, op1, op2) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: i32) -> svfloat32_t { + svscale_f32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svint32_t) -> svfloat32_t { + svscale_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: i32) -> svfloat32_t { + svscale_f32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fscale.nxv2f64")] + fn _svscale_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svint64_t) -> svfloat64_t; + } + unsafe { _svscale_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: i64) -> svfloat64_t { + svscale_f64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svint64_t) -> svfloat64_t { + svscale_f64_m(pg, op1, op2) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: i64) -> svfloat64_t { + svscale_f64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svint64_t) -> svfloat64_t { + svscale_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: i64) -> svfloat64_t { + svscale_f64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_b])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_b(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe { simd_select(pg, op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe { simd_select::(pg, op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { simd_select::(pg, op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_f32(tuple: svfloat32x2_t, x: svfloat32_t) -> svfloat32x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_f64(tuple: svfloat64x2_t, x: svfloat64_t) -> svfloat64x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_s8(tuple: svint8x2_t, x: svint8_t) -> svint8x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_s16(tuple: svint16x2_t, x: svint16_t) -> svint16x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_s32(tuple: svint32x2_t, x: svint32_t) -> svint32x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_s64(tuple: svint64x2_t, x: svint64_t) -> svint64x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_u8(tuple: svuint8x2_t, x: svuint8_t) -> svuint8x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_u16(tuple: svuint16x2_t, x: svuint16_t) -> svuint16x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_u32(tuple: svuint32x2_t, x: svuint32_t) -> svuint32x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_u64(tuple: svuint64x2_t, x: svuint64_t) -> svuint64x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_f32(tuple: svfloat32x3_t, x: svfloat32_t) -> svfloat32x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_f64(tuple: svfloat64x3_t, x: svfloat64_t) -> svfloat64x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_s8(tuple: svint8x3_t, x: svint8_t) -> svint8x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_s16(tuple: svint16x3_t, x: svint16_t) -> svint16x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_s32(tuple: svint32x3_t, x: svint32_t) -> svint32x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_s64(tuple: svint64x3_t, x: svint64_t) -> svint64x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_u8(tuple: svuint8x3_t, x: svuint8_t) -> svuint8x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_u16(tuple: svuint16x3_t, x: svuint16_t) -> svuint16x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_u32(tuple: svuint32x3_t, x: svuint32_t) -> svuint32x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_u64(tuple: svuint64x3_t, x: svuint64_t) -> svuint64x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_f32(tuple: svfloat32x4_t, x: svfloat32_t) -> svfloat32x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_f64(tuple: svfloat64x4_t, x: svfloat64_t) -> svfloat64x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_s8(tuple: svint8x4_t, x: svint8_t) -> svint8x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_s16(tuple: svint16x4_t, x: svint16_t) -> svint16x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_s32(tuple: svint32x4_t, x: svint32_t) -> svint32x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_s64(tuple: svint64x4_t, x: svint64_t) -> svint64x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_u8(tuple: svuint8x4_t, x: svuint8_t) -> svuint8x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_u16(tuple: svuint16x4_t, x: svuint16_t) -> svuint16x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_u32(tuple: svuint32x4_t, x: svuint32_t) -> svuint32x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_u64(tuple: svuint64x4_t, x: svuint64_t) -> svuint64x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Initialize the first-fault register to all-true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsetffr)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(setffr))] +pub fn svsetffr() { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.setffr")] + fn _svsetffr(); + } + unsafe { _svsetffr() } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv4f32")] + fn _svsplice_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svsplice_f32(pg.sve_into(), op1, op2) } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv2f64")] + fn _svsplice_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svsplice_f64(pg.sve_into(), op1, op2) } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv16i8")] + fn _svsplice_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svsplice_s8(pg, op1, op2) } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv8i16")] + fn _svsplice_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svsplice_s16(pg.sve_into(), op1, op2) } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv4i32")] + fn _svsplice_s32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svsplice_s32(pg.sve_into(), op1, op2) } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv2i64")] + fn _svsplice_s64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svsplice_s64(pg.sve_into(), op1, op2) } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svsplice_s8(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svsplice_s16(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svsplice_s32(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svsplice_s64(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Square root"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsqrt))] +pub fn svsqrt_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsqrt.nxv4f32")] + fn _svsqrt_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svsqrt_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Square root"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsqrt))] +pub fn svsqrt_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svsqrt_f32_m(op, pg, op) +} +#[doc = "Square root"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsqrt))] +pub fn svsqrt_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svsqrt_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Square root"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsqrt))] +pub fn svsqrt_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsqrt.nxv2f64")] + fn _svsqrt_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svsqrt_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Square root"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsqrt))] +pub fn svsqrt_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svsqrt_f64_m(op, pg, op) +} +#[doc = "Square root"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsqrt))] +pub fn svsqrt_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svsqrt_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_f32(pg: svbool_t, base: *mut f32, data: svfloat32_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv4f32")] + fn _svst1_f32(data: svfloat32_t, pg: svbool4_t, ptr: *mut f32); + } + _svst1_f32(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_f64(pg: svbool_t, base: *mut f64, data: svfloat64_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv2f64")] + fn _svst1_f64(data: svfloat64_t, pg: svbool2_t, ptr: *mut f64); + } + _svst1_f64(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1_s8(pg: svbool_t, base: *mut i8, data: svint8_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv16i8")] + fn _svst1_s8(data: svint8_t, pg: svbool_t, ptr: *mut i8); + } + _svst1_s8(data, pg, base) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1_s16(pg: svbool_t, base: *mut i16, data: svint16_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv8i16")] + fn _svst1_s16(data: svint16_t, pg: svbool8_t, ptr: *mut i16); + } + _svst1_s16(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_s32(pg: svbool_t, base: *mut i32, data: svint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv4i32")] + fn _svst1_s32(data: svint32_t, pg: svbool4_t, ptr: *mut i32); + } + _svst1_s32(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_s64(pg: svbool_t, base: *mut i64, data: svint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv2i64")] + fn _svst1_s64(data: svint64_t, pg: svbool2_t, ptr: *mut i64); + } + _svst1_s64(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1_u8(pg: svbool_t, base: *mut u8, data: svuint8_t) { + svst1_s8(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1_u16(pg: svbool_t, base: *mut u16, data: svuint16_t) { + svst1_s16(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_u32(pg: svbool_t, base: *mut u32, data: svuint32_t) { + svst1_s32(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_u64(pg: svbool_t, base: *mut u64, data: svuint64_t) { + svst1_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_s32index_f32( + pg: svbool_t, + base: *mut f32, + indices: svint32_t, + data: svfloat32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4f32" + )] + fn _svst1_scatter_s32index_f32( + data: svfloat32_t, + pg: svbool4_t, + base: *mut f32, + indices: svint32_t, + ); + } + _svst1_scatter_s32index_f32(data, pg.sve_into(), base, indices) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_s32index_s32( + pg: svbool_t, + base: *mut i32, + indices: svint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i32" + )] + fn _svst1_scatter_s32index_s32( + data: svint32_t, + pg: svbool4_t, + base: *mut i32, + indices: svint32_t, + ); + } + _svst1_scatter_s32index_s32(data, pg.sve_into(), base, indices) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_s32index_u32( + pg: svbool_t, + base: *mut u32, + indices: svint32_t, + data: svuint32_t, +) { + svst1_scatter_s32index_s32(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_s64index_f64( + pg: svbool_t, + base: *mut f64, + indices: svint64_t, + data: svfloat64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.index.nxv2f64" + )] + fn _svst1_scatter_s64index_f64( + data: svfloat64_t, + pg: svbool2_t, + base: *mut f64, + indices: svint64_t, + ); + } + _svst1_scatter_s64index_f64(data, pg.sve_into(), base, indices) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_s64index_s64( + pg: svbool_t, + base: *mut i64, + indices: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.index.nxv2i64" + )] + fn _svst1_scatter_s64index_s64( + data: svint64_t, + pg: svbool2_t, + base: *mut i64, + indices: svint64_t, + ); + } + _svst1_scatter_s64index_s64(data, pg.sve_into(), base, indices) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_s64index_u64( + pg: svbool_t, + base: *mut u64, + indices: svint64_t, + data: svuint64_t, +) { + svst1_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32index_f32( + pg: svbool_t, + base: *mut f32, + indices: svuint32_t, + data: svfloat32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4f32" + )] + fn _svst1_scatter_u32index_f32( + data: svfloat32_t, + pg: svbool4_t, + base: *mut f32, + indices: svint32_t, + ); + } + _svst1_scatter_u32index_f32(data, pg.sve_into(), base, indices.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32index_s32( + pg: svbool_t, + base: *mut i32, + indices: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4i32" + )] + fn _svst1_scatter_u32index_s32( + data: svint32_t, + pg: svbool4_t, + base: *mut i32, + indices: svint32_t, + ); + } + _svst1_scatter_u32index_s32(data, pg.sve_into(), base, indices.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32index_u32( + pg: svbool_t, + base: *mut u32, + indices: svuint32_t, + data: svuint32_t, +) { + svst1_scatter_u32index_s32(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64index_f64( + pg: svbool_t, + base: *mut f64, + indices: svuint64_t, + data: svfloat64_t, +) { + svst1_scatter_s64index_f64(pg, base, indices.as_signed(), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64index_s64( + pg: svbool_t, + base: *mut i64, + indices: svuint64_t, + data: svint64_t, +) { + svst1_scatter_s64index_s64(pg, base, indices.as_signed(), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64index_u64( + pg: svbool_t, + base: *mut u64, + indices: svuint64_t, + data: svuint64_t, +) { + svst1_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_s32offset_f32( + pg: svbool_t, + base: *mut f32, + offsets: svint32_t, + data: svfloat32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.sxtw.nxv4f32" + )] + fn _svst1_scatter_s32offset_f32( + data: svfloat32_t, + pg: svbool4_t, + base: *mut f32, + offsets: svint32_t, + ); + } + _svst1_scatter_s32offset_f32(data, pg.sve_into(), base, offsets) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_s32offset_s32( + pg: svbool_t, + base: *mut i32, + offsets: svint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.sxtw.nxv4i32" + )] + fn _svst1_scatter_s32offset_s32( + data: svint32_t, + pg: svbool4_t, + base: *mut i32, + offsets: svint32_t, + ); + } + _svst1_scatter_s32offset_s32(data, pg.sve_into(), base, offsets) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_s32offset_u32( + pg: svbool_t, + base: *mut u32, + offsets: svint32_t, + data: svuint32_t, +) { + svst1_scatter_s32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_s64offset_f64( + pg: svbool_t, + base: *mut f64, + offsets: svint64_t, + data: svfloat64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.nxv2f64" + )] + fn _svst1_scatter_s64offset_f64( + data: svfloat64_t, + pg: svbool2_t, + base: *mut f64, + offsets: svint64_t, + ); + } + _svst1_scatter_s64offset_f64(data, pg.sve_into(), base, offsets) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i64, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.nxv2i64" + )] + fn _svst1_scatter_s64offset_s64( + data: svint64_t, + pg: svbool2_t, + base: *mut i64, + offsets: svint64_t, + ); + } + _svst1_scatter_s64offset_s64(data, pg.sve_into(), base, offsets) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u64, + offsets: svint64_t, + data: svuint64_t, +) { + svst1_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32offset_f32( + pg: svbool_t, + base: *mut f32, + offsets: svuint32_t, + data: svfloat32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.uxtw.nxv4f32" + )] + fn _svst1_scatter_u32offset_f32( + data: svfloat32_t, + pg: svbool4_t, + base: *mut f32, + offsets: svint32_t, + ); + } + _svst1_scatter_u32offset_f32(data, pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32offset_s32( + pg: svbool_t, + base: *mut i32, + offsets: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.uxtw.nxv4i32" + )] + fn _svst1_scatter_u32offset_s32( + data: svint32_t, + pg: svbool4_t, + base: *mut i32, + offsets: svint32_t, + ); + } + _svst1_scatter_u32offset_s32(data, pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32offset_u32( + pg: svbool_t, + base: *mut u32, + offsets: svuint32_t, + data: svuint32_t, +) { + svst1_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64offset_f64( + pg: svbool_t, + base: *mut f64, + offsets: svuint64_t, + data: svfloat64_t, +) { + svst1_scatter_s64offset_f64(pg, base, offsets.as_signed(), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i64, + offsets: svuint64_t, + data: svint64_t, +) { + svst1_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u64, + offsets: svuint64_t, + data: svuint64_t, +) { + svst1_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_f32(pg: svbool_t, bases: svuint32_t, data: svfloat32_t) { + svst1_scatter_u32base_offset_f32(pg, bases, 0, data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) { + svst1_scatter_u32base_offset_s32(pg, bases, 0, data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) { + svst1_scatter_u32base_offset_u32(pg, bases, 0, data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_f64(pg: svbool_t, bases: svuint64_t, data: svfloat64_t) { + svst1_scatter_u64base_offset_f64(pg, bases, 0, data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svst1_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svst1_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_index_f32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svfloat32_t, +) { + svst1_scatter_u32base_offset_f32(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svint32_t, +) { + svst1_scatter_u32base_offset_s32(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svuint32_t, +) { + svst1_scatter_u32base_offset_u32(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_index_f64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svfloat64_t, +) { + svst1_scatter_u64base_offset_f64(pg, bases, index.unchecked_shl(3), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svint64_t, +) { + svst1_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(3), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svuint64_t, +) { + svst1_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(3), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_offset_f32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svfloat32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4f32.nxv4i32" + )] + fn _svst1_scatter_u32base_offset_f32( + data: svfloat32_t, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svst1_scatter_u32base_offset_f32(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i32.nxv4i32" + )] + fn _svst1_scatter_u32base_offset_s32( + data: svint32_t, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svst1_scatter_u32base_offset_s32(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svuint32_t, +) { + svst1_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_offset_f64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svfloat64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2f64.nxv2i64" + )] + fn _svst1_scatter_u64base_offset_f64( + data: svfloat64_t, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svst1_scatter_u64base_offset_f64(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i64.nxv2i64" + )] + fn _svst1_scatter_u64base_offset_s64( + data: svint64_t, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svst1_scatter_u64base_offset_s64(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svst1_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfloat32_t) { + svst1_f32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfloat64_t) { + svst1_f64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8_t) { + svst1_s8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svint16_t) { + svst1_s16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svint32_t) { + svst1_s32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svint64_t) { + svst1_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint8_t) { + svst1_u8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint16_t) { + svst1_u16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint32_t) { + svst1_u32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svuint64_t) { + svst1_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_s16(pg: svbool_t, base: *mut i8, data: svint16_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv8i8")] + fn _svst1b_s16(data: nxv8i8, pg: svbool8_t, ptr: *mut i8); + } + _svst1b_s16( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_s32(pg: svbool_t, base: *mut i8, data: svint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv4i8")] + fn _svst1b_s32(data: nxv4i8, pg: svbool4_t, ptr: *mut i8); + } + _svst1b_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_s32(pg: svbool_t, base: *mut i16, data: svint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv4i16")] + fn _svst1h_s32(data: nxv4i16, pg: svbool4_t, ptr: *mut i16); + } + _svst1h_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_s64(pg: svbool_t, base: *mut i8, data: svint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv2i8")] + fn _svst1b_s64(data: nxv2i8, pg: svbool2_t, ptr: *mut i8); + } + _svst1b_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_s64(pg: svbool_t, base: *mut i16, data: svint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv2i16")] + fn _svst1h_s64(data: nxv2i16, pg: svbool2_t, ptr: *mut i16); + } + _svst1h_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + ) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_s64(pg: svbool_t, base: *mut i32, data: svint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv2i32")] + fn _svst1w_s64(data: nxv2i32, pg: svbool2_t, ptr: *mut i32); + } + _svst1w_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_u16(pg: svbool_t, base: *mut u8, data: svuint16_t) { + svst1b_s16(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_u32(pg: svbool_t, base: *mut u8, data: svuint32_t) { + svst1b_s32(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_u32(pg: svbool_t, base: *mut u16, data: svuint32_t) { + svst1h_s32(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_u64(pg: svbool_t, base: *mut u8, data: svuint64_t) { + svst1b_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_u64(pg: svbool_t, base: *mut u16, data: svuint64_t) { + svst1h_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_u64(pg: svbool_t, base: *mut u32, data: svuint64_t) { + svst1w_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[s32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_s32offset_s32( + pg: svbool_t, + base: *mut i8, + offsets: svint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.sxtw.nxv4i8" + )] + fn _svst1b_scatter_s32offset_s32( + data: nxv4i8, + pg: svbool4_t, + base: *mut i8, + offsets: svint32_t, + ); + } + _svst1b_scatter_s32offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s32offset_s32( + pg: svbool_t, + base: *mut i16, + offsets: svint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.sxtw.nxv4i16" + )] + fn _svst1h_scatter_s32offset_s32( + data: nxv4i16, + pg: svbool4_t, + base: *mut i16, + offsets: svint32_t, + ); + } + _svst1h_scatter_s32offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[s32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_s32offset_u32( + pg: svbool_t, + base: *mut u8, + offsets: svint32_t, + data: svuint32_t, +) { + svst1b_scatter_s32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s32offset_u32( + pg: svbool_t, + base: *mut u16, + offsets: svint32_t, + data: svuint32_t, +) { + svst1h_scatter_s32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i8, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.nxv2i8" + )] + fn _svst1b_scatter_s64offset_s64( + data: nxv2i8, + pg: svbool2_t, + base: *mut i8, + offsets: svint64_t, + ); + } + _svst1b_scatter_s64offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i16, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.nxv2i16" + )] + fn _svst1h_scatter_s64offset_s64( + data: nxv2i16, + pg: svbool2_t, + base: *mut i16, + offsets: svint64_t, + ); + } + _svst1h_scatter_s64offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i32, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.nxv2i32" + )] + fn _svst1w_scatter_s64offset_s64( + data: nxv2i32, + pg: svbool2_t, + base: *mut i32, + offsets: svint64_t, + ); + } + _svst1w_scatter_s64offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u8, + offsets: svint64_t, + data: svuint64_t, +) { + svst1b_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u16, + offsets: svint64_t, + data: svuint64_t, +) { + svst1h_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u32, + offsets: svint64_t, + data: svuint64_t, +) { + svst1w_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u32offset_s32( + pg: svbool_t, + base: *mut i8, + offsets: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.uxtw.nxv4i8" + )] + fn _svst1b_scatter_u32offset_s32( + data: nxv4i8, + pg: svbool4_t, + base: *mut i8, + offsets: svint32_t, + ); + } + _svst1b_scatter_u32offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets.as_signed(), + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32offset_s32( + pg: svbool_t, + base: *mut i16, + offsets: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.uxtw.nxv4i16" + )] + fn _svst1h_scatter_u32offset_s32( + data: nxv4i16, + pg: svbool4_t, + base: *mut i16, + offsets: svint32_t, + ); + } + _svst1h_scatter_u32offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets.as_signed(), + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u32offset_u32( + pg: svbool_t, + base: *mut u8, + offsets: svuint32_t, + data: svuint32_t, +) { + svst1b_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32offset_u32( + pg: svbool_t, + base: *mut u16, + offsets: svuint32_t, + data: svuint32_t, +) { + svst1h_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i8, + offsets: svuint64_t, + data: svint64_t, +) { + svst1b_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i16, + offsets: svuint64_t, + data: svint64_t, +) { + svst1h_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i32, + offsets: svuint64_t, + data: svint64_t, +) { + svst1w_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u8, + offsets: svuint64_t, + data: svuint64_t, +) { + svst1b_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u16, + offsets: svuint64_t, + data: svuint64_t, +) { + svst1h_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u32, + offsets: svuint64_t, + data: svuint64_t, +) { + svst1w_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u32base]_offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svst1b_scatter_u32base_offset_s32( + data: nxv4i8, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svst1b_scatter_u32base_offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base]_offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svst1h_scatter_u32base_offset_s32( + data: nxv4i16, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svst1h_scatter_u32base_offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u32base]_offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svuint32_t, +) { + svst1b_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base]_offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svuint32_t, +) { + svst1h_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svst1b_scatter_u64base_offset_s64( + data: nxv2i8, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svst1b_scatter_u64base_offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svst1h_scatter_u64base_offset_s64( + data: nxv2i16, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svst1h_scatter_u64base_offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svst1w_scatter_u64base_offset_s64( + data: nxv2i32, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svst1w_scatter_u64base_offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svst1b_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svst1h_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svst1w_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u32base_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) { + svst1b_scatter_u32base_offset_s32(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) { + svst1h_scatter_u32base_offset_s32(pg, bases, 0, data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u32base_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) { + svst1b_scatter_u32base_offset_u32(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) { + svst1h_scatter_u32base_offset_u32(pg, bases, 0, data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svst1b_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svst1h_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svst1w_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svst1b_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svst1h_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svst1w_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_vnum_s16(pg: svbool_t, base: *mut i8, vnum: i64, data: svint16_t) { + svst1b_s16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_vnum_s32(pg: svbool_t, base: *mut i8, vnum: i64, data: svint32_t) { + svst1b_s32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_vnum_s32(pg: svbool_t, base: *mut i16, vnum: i64, data: svint32_t) { + svst1h_s32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_vnum_s64(pg: svbool_t, base: *mut i8, vnum: i64, data: svint64_t) { + svst1b_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_vnum_s64(pg: svbool_t, base: *mut i16, vnum: i64, data: svint64_t) { + svst1h_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_vnum_s64(pg: svbool_t, base: *mut i32, vnum: i64, data: svint64_t) { + svst1w_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_vnum_u16(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint16_t) { + svst1b_u16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_vnum_u32(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint32_t) { + svst1b_u32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_vnum_u32(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint32_t) { + svst1h_u32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_vnum_u64(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint64_t) { + svst1b_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_vnum_u64(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint64_t) { + svst1h_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_vnum_u64(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint64_t) { + svst1w_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s32index_s32( + pg: svbool_t, + base: *mut i16, + indices: svint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i16" + )] + fn _svst1h_scatter_s32index_s32( + data: nxv4i16, + pg: svbool4_t, + base: *mut i16, + indices: svint32_t, + ); + } + _svst1h_scatter_s32index_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + indices, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s32index_u32( + pg: svbool_t, + base: *mut u16, + indices: svint32_t, + data: svuint32_t, +) { + svst1h_scatter_s32index_s32(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s64index_s64( + pg: svbool_t, + base: *mut i16, + indices: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.index.nxv2i16" + )] + fn _svst1h_scatter_s64index_s64( + data: nxv2i16, + pg: svbool2_t, + base: *mut i16, + indices: svint64_t, + ); + } + _svst1h_scatter_s64index_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + indices, + ) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_s64index_s64( + pg: svbool_t, + base: *mut i32, + indices: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.index.nxv2i32" + )] + fn _svst1w_scatter_s64index_s64( + data: nxv2i32, + pg: svbool2_t, + base: *mut i32, + indices: svint64_t, + ); + } + _svst1w_scatter_s64index_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + indices, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s64index_u64( + pg: svbool_t, + base: *mut u16, + indices: svint64_t, + data: svuint64_t, +) { + svst1h_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_s64index_u64( + pg: svbool_t, + base: *mut u32, + indices: svint64_t, + data: svuint64_t, +) { + svst1w_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32index_s32( + pg: svbool_t, + base: *mut i16, + indices: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4i16" + )] + fn _svst1h_scatter_u32index_s32( + data: nxv4i16, + pg: svbool4_t, + base: *mut i16, + indices: svint32_t, + ); + } + _svst1h_scatter_u32index_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + indices.as_signed(), + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32index_u32( + pg: svbool_t, + base: *mut u16, + indices: svuint32_t, + data: svuint32_t, +) { + svst1h_scatter_u32index_s32(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64index_s64( + pg: svbool_t, + base: *mut i16, + indices: svuint64_t, + data: svint64_t, +) { + svst1h_scatter_s64index_s64(pg, base, indices.as_signed(), data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64index_s64( + pg: svbool_t, + base: *mut i32, + indices: svuint64_t, + data: svint64_t, +) { + svst1w_scatter_s64index_s64(pg, base, indices.as_signed(), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64index_u64( + pg: svbool_t, + base: *mut u16, + indices: svuint64_t, + data: svuint64_t, +) { + svst1h_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64index_u64( + pg: svbool_t, + base: *mut u32, + indices: svuint64_t, + data: svuint64_t, +) { + svst1w_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base]_index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svint32_t, +) { + svst1h_scatter_u32base_offset_s32(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base]_index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svuint32_t, +) { + svst1h_scatter_u32base_offset_u32(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base]_index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svint64_t, +) { + svst1h_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base]_index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svint64_t, +) { + svst1w_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base]_index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svuint64_t, +) { + svst1h_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base]_index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svuint64_t, +) { + svst1w_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2w))] +pub unsafe fn svst2_f32(pg: svbool_t, base: *mut f32, data: svfloat32x2_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv4f32")] + fn _svst2_f32(data0: svfloat32_t, data1: svfloat32_t, pg: svbool4_t, ptr: *mut f32); + } + _svst2_f32( + svget2_f32::<0>(data), + svget2_f32::<1>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2d))] +pub unsafe fn svst2_f64(pg: svbool_t, base: *mut f64, data: svfloat64x2_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv2f64")] + fn _svst2_f64(data0: svfloat64_t, data1: svfloat64_t, pg: svbool2_t, ptr: *mut f64); + } + _svst2_f64( + svget2_f64::<0>(data), + svget2_f64::<1>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2b))] +pub unsafe fn svst2_s8(pg: svbool_t, base: *mut i8, data: svint8x2_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv16i8")] + fn _svst2_s8(data0: svint8_t, data1: svint8_t, pg: svbool_t, ptr: *mut i8); + } + _svst2_s8(svget2_s8::<0>(data), svget2_s8::<1>(data), pg, base) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2h))] +pub unsafe fn svst2_s16(pg: svbool_t, base: *mut i16, data: svint16x2_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv8i16")] + fn _svst2_s16(data0: svint16_t, data1: svint16_t, pg: svbool8_t, ptr: *mut i16); + } + _svst2_s16( + svget2_s16::<0>(data), + svget2_s16::<1>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2w))] +pub unsafe fn svst2_s32(pg: svbool_t, base: *mut i32, data: svint32x2_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv4i32")] + fn _svst2_s32(data0: svint32_t, data1: svint32_t, pg: svbool4_t, ptr: *mut i32); + } + _svst2_s32( + svget2_s32::<0>(data), + svget2_s32::<1>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2d))] +pub unsafe fn svst2_s64(pg: svbool_t, base: *mut i64, data: svint64x2_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv2i64")] + fn _svst2_s64(data0: svint64_t, data1: svint64_t, pg: svbool2_t, ptr: *mut i64); + } + _svst2_s64( + svget2_s64::<0>(data), + svget2_s64::<1>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2b))] +pub unsafe fn svst2_u8(pg: svbool_t, base: *mut u8, data: svuint8x2_t) { + svst2_s8(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2h))] +pub unsafe fn svst2_u16(pg: svbool_t, base: *mut u16, data: svuint16x2_t) { + svst2_s16(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2w))] +pub unsafe fn svst2_u32(pg: svbool_t, base: *mut u32, data: svuint32x2_t) { + svst2_s32(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2d))] +pub unsafe fn svst2_u64(pg: svbool_t, base: *mut u64, data: svuint64x2_t) { + svst2_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2w))] +pub unsafe fn svst2_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfloat32x2_t) { + svst2_f32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2d))] +pub unsafe fn svst2_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfloat64x2_t) { + svst2_f64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2b))] +pub unsafe fn svst2_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8x2_t) { + svst2_s8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2h))] +pub unsafe fn svst2_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svint16x2_t) { + svst2_s16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2w))] +pub unsafe fn svst2_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svint32x2_t) { + svst2_s32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2d))] +pub unsafe fn svst2_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svint64x2_t) { + svst2_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2b))] +pub unsafe fn svst2_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint8x2_t) { + svst2_u8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2h))] +pub unsafe fn svst2_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint16x2_t) { + svst2_u16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2w))] +pub unsafe fn svst2_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint32x2_t) { + svst2_u32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2d))] +pub unsafe fn svst2_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svuint64x2_t) { + svst2_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3w))] +pub unsafe fn svst3_f32(pg: svbool_t, base: *mut f32, data: svfloat32x3_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv4f32")] + fn _svst3_f32( + data0: svfloat32_t, + data1: svfloat32_t, + data2: svfloat32_t, + pg: svbool4_t, + ptr: *mut f32, + ); + } + _svst3_f32( + svget3_f32::<0>(data), + svget3_f32::<1>(data), + svget3_f32::<2>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3d))] +pub unsafe fn svst3_f64(pg: svbool_t, base: *mut f64, data: svfloat64x3_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv2f64")] + fn _svst3_f64( + data0: svfloat64_t, + data1: svfloat64_t, + data2: svfloat64_t, + pg: svbool2_t, + ptr: *mut f64, + ); + } + _svst3_f64( + svget3_f64::<0>(data), + svget3_f64::<1>(data), + svget3_f64::<2>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3b))] +pub unsafe fn svst3_s8(pg: svbool_t, base: *mut i8, data: svint8x3_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv16i8")] + fn _svst3_s8(data0: svint8_t, data1: svint8_t, data2: svint8_t, pg: svbool_t, ptr: *mut i8); + } + _svst3_s8( + svget3_s8::<0>(data), + svget3_s8::<1>(data), + svget3_s8::<2>(data), + pg, + base, + ) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3h))] +pub unsafe fn svst3_s16(pg: svbool_t, base: *mut i16, data: svint16x3_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv8i16")] + fn _svst3_s16( + data0: svint16_t, + data1: svint16_t, + data2: svint16_t, + pg: svbool8_t, + ptr: *mut i16, + ); + } + _svst3_s16( + svget3_s16::<0>(data), + svget3_s16::<1>(data), + svget3_s16::<2>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3w))] +pub unsafe fn svst3_s32(pg: svbool_t, base: *mut i32, data: svint32x3_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv4i32")] + fn _svst3_s32( + data0: svint32_t, + data1: svint32_t, + data2: svint32_t, + pg: svbool4_t, + ptr: *mut i32, + ); + } + _svst3_s32( + svget3_s32::<0>(data), + svget3_s32::<1>(data), + svget3_s32::<2>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3d))] +pub unsafe fn svst3_s64(pg: svbool_t, base: *mut i64, data: svint64x3_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv2i64")] + fn _svst3_s64( + data0: svint64_t, + data1: svint64_t, + data2: svint64_t, + pg: svbool2_t, + ptr: *mut i64, + ); + } + _svst3_s64( + svget3_s64::<0>(data), + svget3_s64::<1>(data), + svget3_s64::<2>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3b))] +pub unsafe fn svst3_u8(pg: svbool_t, base: *mut u8, data: svuint8x3_t) { + svst3_s8(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3h))] +pub unsafe fn svst3_u16(pg: svbool_t, base: *mut u16, data: svuint16x3_t) { + svst3_s16(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3w))] +pub unsafe fn svst3_u32(pg: svbool_t, base: *mut u32, data: svuint32x3_t) { + svst3_s32(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3d))] +pub unsafe fn svst3_u64(pg: svbool_t, base: *mut u64, data: svuint64x3_t) { + svst3_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3w))] +pub unsafe fn svst3_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfloat32x3_t) { + svst3_f32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3d))] +pub unsafe fn svst3_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfloat64x3_t) { + svst3_f64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3b))] +pub unsafe fn svst3_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8x3_t) { + svst3_s8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3h))] +pub unsafe fn svst3_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svint16x3_t) { + svst3_s16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3w))] +pub unsafe fn svst3_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svint32x3_t) { + svst3_s32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3d))] +pub unsafe fn svst3_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svint64x3_t) { + svst3_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3b))] +pub unsafe fn svst3_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint8x3_t) { + svst3_u8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3h))] +pub unsafe fn svst3_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint16x3_t) { + svst3_u16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3w))] +pub unsafe fn svst3_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint32x3_t) { + svst3_u32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3d))] +pub unsafe fn svst3_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svuint64x3_t) { + svst3_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4w))] +pub unsafe fn svst4_f32(pg: svbool_t, base: *mut f32, data: svfloat32x4_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv4f32")] + fn _svst4_f32( + data0: svfloat32_t, + data1: svfloat32_t, + data2: svfloat32_t, + data3: svfloat32_t, + pg: svbool4_t, + ptr: *mut f32, + ); + } + _svst4_f32( + svget4_f32::<0>(data), + svget4_f32::<1>(data), + svget4_f32::<2>(data), + svget4_f32::<3>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4d))] +pub unsafe fn svst4_f64(pg: svbool_t, base: *mut f64, data: svfloat64x4_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv2f64")] + fn _svst4_f64( + data0: svfloat64_t, + data1: svfloat64_t, + data2: svfloat64_t, + data3: svfloat64_t, + pg: svbool2_t, + ptr: *mut f64, + ); + } + _svst4_f64( + svget4_f64::<0>(data), + svget4_f64::<1>(data), + svget4_f64::<2>(data), + svget4_f64::<3>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4b))] +pub unsafe fn svst4_s8(pg: svbool_t, base: *mut i8, data: svint8x4_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv16i8")] + fn _svst4_s8( + data0: svint8_t, + data1: svint8_t, + data2: svint8_t, + data3: svint8_t, + pg: svbool_t, + ptr: *mut i8, + ); + } + _svst4_s8( + svget4_s8::<0>(data), + svget4_s8::<1>(data), + svget4_s8::<2>(data), + svget4_s8::<3>(data), + pg, + base, + ) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4h))] +pub unsafe fn svst4_s16(pg: svbool_t, base: *mut i16, data: svint16x4_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv8i16")] + fn _svst4_s16( + data0: svint16_t, + data1: svint16_t, + data2: svint16_t, + data3: svint16_t, + pg: svbool8_t, + ptr: *mut i16, + ); + } + _svst4_s16( + svget4_s16::<0>(data), + svget4_s16::<1>(data), + svget4_s16::<2>(data), + svget4_s16::<3>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4w))] +pub unsafe fn svst4_s32(pg: svbool_t, base: *mut i32, data: svint32x4_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv4i32")] + fn _svst4_s32( + data0: svint32_t, + data1: svint32_t, + data2: svint32_t, + data3: svint32_t, + pg: svbool4_t, + ptr: *mut i32, + ); + } + _svst4_s32( + svget4_s32::<0>(data), + svget4_s32::<1>(data), + svget4_s32::<2>(data), + svget4_s32::<3>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4d))] +pub unsafe fn svst4_s64(pg: svbool_t, base: *mut i64, data: svint64x4_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv2i64")] + fn _svst4_s64( + data0: svint64_t, + data1: svint64_t, + data2: svint64_t, + data3: svint64_t, + pg: svbool2_t, + ptr: *mut i64, + ); + } + _svst4_s64( + svget4_s64::<0>(data), + svget4_s64::<1>(data), + svget4_s64::<2>(data), + svget4_s64::<3>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4b))] +pub unsafe fn svst4_u8(pg: svbool_t, base: *mut u8, data: svuint8x4_t) { + svst4_s8(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4h))] +pub unsafe fn svst4_u16(pg: svbool_t, base: *mut u16, data: svuint16x4_t) { + svst4_s16(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4w))] +pub unsafe fn svst4_u32(pg: svbool_t, base: *mut u32, data: svuint32x4_t) { + svst4_s32(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4d))] +pub unsafe fn svst4_u64(pg: svbool_t, base: *mut u64, data: svuint64x4_t) { + svst4_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4w))] +pub unsafe fn svst4_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfloat32x4_t) { + svst4_f32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4d))] +pub unsafe fn svst4_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfloat64x4_t) { + svst4_f64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4b))] +pub unsafe fn svst4_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8x4_t) { + svst4_s8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4h))] +pub unsafe fn svst4_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svint16x4_t) { + svst4_s16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4w))] +pub unsafe fn svst4_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svint32x4_t) { + svst4_s32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4d))] +pub unsafe fn svst4_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svint64x4_t) { + svst4_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4b))] +pub unsafe fn svst4_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint8x4_t) { + svst4_u8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4h))] +pub unsafe fn svst4_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint16x4_t) { + svst4_u16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4w))] +pub unsafe fn svst4_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint32x4_t) { + svst4_u32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4d))] +pub unsafe fn svst4_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svuint64x4_t) { + svst4_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_f32(pg: svbool_t, base: *mut f32, data: svfloat32_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv4f32")] + fn _svstnt1_f32(data: svfloat32_t, pg: svbool4_t, ptr: *mut f32); + } + _svstnt1_f32(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_f64(pg: svbool_t, base: *mut f64, data: svfloat64_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv2f64")] + fn _svstnt1_f64(data: svfloat64_t, pg: svbool2_t, ptr: *mut f64); + } + _svstnt1_f64(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1_s8(pg: svbool_t, base: *mut i8, data: svint8_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv16i8")] + fn _svstnt1_s8(data: svint8_t, pg: svbool_t, ptr: *mut i8); + } + _svstnt1_s8(data, pg, base) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1_s16(pg: svbool_t, base: *mut i16, data: svint16_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv8i16")] + fn _svstnt1_s16(data: svint16_t, pg: svbool8_t, ptr: *mut i16); + } + _svstnt1_s16(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_s32(pg: svbool_t, base: *mut i32, data: svint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv4i32")] + fn _svstnt1_s32(data: svint32_t, pg: svbool4_t, ptr: *mut i32); + } + _svstnt1_s32(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_s64(pg: svbool_t, base: *mut i64, data: svint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv2i64")] + fn _svstnt1_s64(data: svint64_t, pg: svbool2_t, ptr: *mut i64); + } + _svstnt1_s64(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1_u8(pg: svbool_t, base: *mut u8, data: svuint8_t) { + svstnt1_s8(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1_u16(pg: svbool_t, base: *mut u16, data: svuint16_t) { + svstnt1_s16(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_u32(pg: svbool_t, base: *mut u32, data: svuint32_t) { + svstnt1_s32(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_u64(pg: svbool_t, base: *mut u64, data: svuint64_t) { + svstnt1_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfloat32_t) { + svstnt1_f32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfloat64_t) { + svstnt1_f64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8_t) { + svstnt1_s8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svint16_t) { + svstnt1_s16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svint32_t) { + svstnt1_s32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svint64_t) { + svstnt1_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint8_t) { + svstnt1_u8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint16_t) { + svstnt1_u16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint32_t) { + svstnt1_u32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svuint64_t) { + svstnt1_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsub.nxv4f32")] + fn _svsub_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svsub_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svsub_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svsub_f32_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svsub_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svsub_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svsub_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsub.nxv2f64")] + fn _svsub_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svsub_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svsub_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svsub_f64_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svsub_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svsub_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svsub_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sub.nxv16i8")] + fn _svsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svsub_s8_m(pg, op1, op2) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svsub_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svsub_s8_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svsub_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svsub_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svsub_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sub.nxv8i16")] + fn _svsub_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svsub_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svsub_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svsub_s16_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svsub_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svsub_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svsub_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sub.nxv4i32")] + fn _svsub_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svsub_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svsub_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svsub_s32_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svsub_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svsub_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svsub_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sub.nxv2i64")] + fn _svsub_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svsub_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svsub_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svsub_s64_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svsub_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svsub_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svsub_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svsub_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svsub_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svsub_u8_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svsub_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svsub_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svsub_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svsub_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svsub_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svsub_u16_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svsub_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svsub_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svsub_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svsub_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svsub_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svsub_u32_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svsub_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svsub_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svsub_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svsub_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svsub_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svsub_u64_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svsub_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svsub_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svsub_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsubr.nxv4f32")] + fn _svsubr_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svsubr_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svsubr_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svsubr_f32_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svsubr_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svsubr_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svsubr_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsubr.nxv2f64")] + fn _svsubr_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svsubr_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svsubr_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svsubr_f64_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svsubr_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svsubr_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svsubr_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subr.nxv16i8")] + fn _svsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svsubr_s8_m(pg, op1, op2) } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svsubr_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svsubr_s8_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svsubr_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svsubr_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svsubr_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subr.nxv8i16")] + fn _svsubr_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svsubr_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svsubr_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svsubr_s16_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svsubr_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svsubr_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svsubr_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subr.nxv4i32")] + fn _svsubr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svsubr_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svsubr_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svsubr_s32_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svsubr_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svsubr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svsubr_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subr.nxv2i64")] + fn _svsubr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svsubr_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svsubr_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svsubr_s64_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svsubr_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svsubr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svsubr_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svsubr_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svsubr_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svsubr_u8_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svsubr_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svsubr_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svsubr_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svsubr_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svsubr_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svsubr_u16_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svsubr_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svsubr_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svsubr_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svsubr_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svsubr_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svsubr_u32_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svsubr_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svsubr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svsubr_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svsubr_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svsubr_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svsubr_u64_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svsubr_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svsubr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svsubr_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Dot product (signed × unsigned)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsudot_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sudot, IMM_INDEX = 0))] +pub fn svsudot_lane_s32( + op1: svint32_t, + op2: svint8_t, + op3: svuint8_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sudot.lane.nxv4i32" + )] + fn _svsudot_lane_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, + imm_index: i32, + ) -> svint32_t; + } + unsafe { _svsudot_lane_s32(op1, op2, op3.as_signed(), IMM_INDEX) } +} +#[doc = "Dot product (signed × unsigned)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsudot[_s32])"] +#[inline] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usdot))] +pub fn svsudot_s32(op1: svint32_t, op2: svint8_t, op3: svuint8_t) -> svint32_t { + svusdot_s32(op1, op3, op2) +} +#[doc = "Dot product (signed × unsigned)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsudot[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usdot))] +pub fn svsudot_n_s32(op1: svint32_t, op2: svint8_t, op3: u8) -> svint32_t { + svsudot_s32(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_f32(data: svfloat32_t, indices: svuint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv4f32")] + fn _svtbl_f32(data: svfloat32_t, indices: svint32_t) -> svfloat32_t; + } + unsafe { _svtbl_f32(data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_f64(data: svfloat64_t, indices: svuint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv2f64")] + fn _svtbl_f64(data: svfloat64_t, indices: svint64_t) -> svfloat64_t; + } + unsafe { _svtbl_f64(data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_s8(data: svint8_t, indices: svuint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv16i8")] + fn _svtbl_s8(data: svint8_t, indices: svint8_t) -> svint8_t; + } + unsafe { _svtbl_s8(data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_s16(data: svint16_t, indices: svuint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv8i16")] + fn _svtbl_s16(data: svint16_t, indices: svint16_t) -> svint16_t; + } + unsafe { _svtbl_s16(data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_s32(data: svint32_t, indices: svuint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv4i32")] + fn _svtbl_s32(data: svint32_t, indices: svint32_t) -> svint32_t; + } + unsafe { _svtbl_s32(data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_s64(data: svint64_t, indices: svuint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv2i64")] + fn _svtbl_s64(data: svint64_t, indices: svint64_t) -> svint64_t; + } + unsafe { _svtbl_s64(data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_u8(data: svuint8_t, indices: svuint8_t) -> svuint8_t { + unsafe { svtbl_s8(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_u16(data: svuint16_t, indices: svuint16_t) -> svuint16_t { + unsafe { svtbl_s16(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_u32(data: svuint32_t, indices: svuint32_t) -> svuint32_t { + unsafe { svtbl_s32(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_u64(data: svuint64_t, indices: svuint64_t) -> svuint64_t { + unsafe { svtbl_s64(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Trigonometric multiply-add coefficient"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtmad[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ftmad, IMM3 = 0))] +pub fn svtmad_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + static_assert_range!(IMM3, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ftmad.x.nxv4f32" + )] + fn _svtmad_f32(op1: svfloat32_t, op2: svfloat32_t, imm3: i32) -> svfloat32_t; + } + unsafe { _svtmad_f32(op1, op2, IMM3) } +} +#[doc = "Trigonometric multiply-add coefficient"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtmad[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ftmad, IMM3 = 0))] +pub fn svtmad_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + static_assert_range!(IMM3, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ftmad.x.nxv2f64" + )] + fn _svtmad_f64(op1: svfloat64_t, op2: svfloat64_t, imm3: i32) -> svfloat64_t; + } + unsafe { _svtmad_f64(op1, op2, IMM3) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.b16")] + fn _svtrn1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svtrn1_b16(op1.sve_into(), op2.sve_into()) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.b32")] + fn _svtrn1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svtrn1_b32(op1.sve_into(), op2.sve_into()) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.b64")] + fn _svtrn1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svtrn1_b64(op1.sve_into(), op2.sve_into()) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv4f32")] + fn _svtrn1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svtrn1_f32(op1, op2) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv2f64")] + fn _svtrn1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svtrn1_f64(op1, op2) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv16i8")] + fn _svtrn1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svtrn1_s8(op1, op2) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv8i16")] + fn _svtrn1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svtrn1_s16(op1, op2) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv4i32")] + fn _svtrn1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svtrn1_s32(op1, op2) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv2i64")] + fn _svtrn1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svtrn1_s64(op1, op2) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svtrn1_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svtrn1_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svtrn1_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svtrn1_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_b8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv16i1")] + fn _svtrn1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svtrn1_b8(op1, op2) } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_f32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv4f32")] + fn _svtrn1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svtrn1q_f32(op1, op2) } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_f64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv2f64")] + fn _svtrn1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svtrn1q_f64(op1, op2) } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_s8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv16i8")] + fn _svtrn1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svtrn1q_s8(op1, op2) } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_s16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv8i16")] + fn _svtrn1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svtrn1q_s16(op1, op2) } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_s32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv4i32")] + fn _svtrn1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svtrn1q_s32(op1, op2) } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_s64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv2i64")] + fn _svtrn1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svtrn1q_s64(op1, op2) } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_u8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svtrn1q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_u16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svtrn1q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_u32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svtrn1q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_u64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svtrn1q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.b16")] + fn _svtrn2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svtrn2_b16(op1.sve_into(), op2.sve_into()) } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.b32")] + fn _svtrn2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svtrn2_b32(op1.sve_into(), op2.sve_into()) } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.b64")] + fn _svtrn2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svtrn2_b64(op1.sve_into(), op2.sve_into()) } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv4f32")] + fn _svtrn2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svtrn2_f32(op1, op2) } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv2f64")] + fn _svtrn2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svtrn2_f64(op1, op2) } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv16i8")] + fn _svtrn2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svtrn2_s8(op1, op2) } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv8i16")] + fn _svtrn2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svtrn2_s16(op1, op2) } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv4i32")] + fn _svtrn2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svtrn2_s32(op1, op2) } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv2i64")] + fn _svtrn2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svtrn2_s64(op1, op2) } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svtrn2_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svtrn2_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svtrn2_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svtrn2_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_b8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv16i1")] + fn _svtrn2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svtrn2_b8(op1, op2) } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_f32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv4f32")] + fn _svtrn2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svtrn2q_f32(op1, op2) } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_f64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv2f64")] + fn _svtrn2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svtrn2q_f64(op1, op2) } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_s8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv16i8")] + fn _svtrn2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svtrn2q_s8(op1, op2) } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_s16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv8i16")] + fn _svtrn2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svtrn2q_s16(op1, op2) } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_s32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv4i32")] + fn _svtrn2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svtrn2q_s32(op1, op2) } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_s64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv2i64")] + fn _svtrn2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svtrn2q_s64(op1, op2) } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_u8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svtrn2q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_u16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svtrn2q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_u32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svtrn2q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_u64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svtrn2q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Trigonometric starting value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtsmul[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ftsmul))] +pub fn svtsmul_f32(op1: svfloat32_t, op2: svuint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ftsmul.x.nxv4f32" + )] + fn _svtsmul_f32(op1: svfloat32_t, op2: svint32_t) -> svfloat32_t; + } + unsafe { _svtsmul_f32(op1, op2.as_signed()) } +} +#[doc = "Trigonometric starting value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtsmul[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ftsmul))] +pub fn svtsmul_f64(op1: svfloat64_t, op2: svuint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ftsmul.x.nxv2f64" + )] + fn _svtsmul_f64(op1: svfloat64_t, op2: svint64_t) -> svfloat64_t; + } + unsafe { _svtsmul_f64(op1, op2.as_signed()) } +} +#[doc = "Trigonometric select coefficient"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtssel[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ftssel))] +pub fn svtssel_f32(op1: svfloat32_t, op2: svuint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ftssel.x.nxv4f32" + )] + fn _svtssel_f32(op1: svfloat32_t, op2: svint32_t) -> svfloat32_t; + } + unsafe { _svtssel_f32(op1, op2.as_signed()) } +} +#[doc = "Trigonometric select coefficient"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtssel[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ftssel))] +pub fn svtssel_f64(op1: svfloat64_t, op2: svuint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ftssel.x.nxv2f64" + )] + fn _svtssel_f64(op1: svfloat64_t, op2: svint64_t) -> svfloat64_t; + } + unsafe { _svtssel_f64(op1, op2.as_signed()) } +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_f32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_f32() -> svfloat32x2_t { + svcreate2_f32(svdup_n_f32(0f32), svdup_n_f32(0f32)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_f64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_f64() -> svfloat64x2_t { + svcreate2_f64(svdup_n_f64(0f64), svdup_n_f64(0f64)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_s8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_s8() -> svint8x2_t { + svcreate2_s8(svdup_n_s8(0), svdup_n_s8(0)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_s16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_s16() -> svint16x2_t { + svcreate2_s16(svdup_n_s16(0), svdup_n_s16(0)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_s32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_s32() -> svint32x2_t { + svcreate2_s32(svdup_n_s32(0), svdup_n_s32(0)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_s64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_s64() -> svint64x2_t { + svcreate2_s64(svdup_n_s64(0), svdup_n_s64(0)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_u8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_u8() -> svuint8x2_t { + svcreate2_u8(svdup_n_u8(0), svdup_n_u8(0)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_u16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_u16() -> svuint16x2_t { + svcreate2_u16(svdup_n_u16(0), svdup_n_u16(0)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_u32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_u32() -> svuint32x2_t { + svcreate2_u32(svdup_n_u32(0), svdup_n_u32(0)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_u64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_u64() -> svuint64x2_t { + svcreate2_u64(svdup_n_u64(0), svdup_n_u64(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_f32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_f32() -> svfloat32x3_t { + svcreate3_f32(svdup_n_f32(0f32), svdup_n_f32(0f32), svdup_n_f32(0f32)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_f64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_f64() -> svfloat64x3_t { + svcreate3_f64(svdup_n_f64(0f64), svdup_n_f64(0f64), svdup_n_f64(0f64)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_s8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_s8() -> svint8x3_t { + svcreate3_s8(svdup_n_s8(0), svdup_n_s8(0), svdup_n_s8(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_s16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_s16() -> svint16x3_t { + svcreate3_s16(svdup_n_s16(0), svdup_n_s16(0), svdup_n_s16(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_s32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_s32() -> svint32x3_t { + svcreate3_s32(svdup_n_s32(0), svdup_n_s32(0), svdup_n_s32(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_s64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_s64() -> svint64x3_t { + svcreate3_s64(svdup_n_s64(0), svdup_n_s64(0), svdup_n_s64(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_u8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_u8() -> svuint8x3_t { + svcreate3_u8(svdup_n_u8(0), svdup_n_u8(0), svdup_n_u8(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_u16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_u16() -> svuint16x3_t { + svcreate3_u16(svdup_n_u16(0), svdup_n_u16(0), svdup_n_u16(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_u32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_u32() -> svuint32x3_t { + svcreate3_u32(svdup_n_u32(0), svdup_n_u32(0), svdup_n_u32(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_u64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_u64() -> svuint64x3_t { + svcreate3_u64(svdup_n_u64(0), svdup_n_u64(0), svdup_n_u64(0)) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_f32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_f32() -> svfloat32x4_t { + svcreate4_f32( + svdup_n_f32(0f32), + svdup_n_f32(0f32), + svdup_n_f32(0f32), + svdup_n_f32(0f32), + ) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_f64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_f64() -> svfloat64x4_t { + svcreate4_f64( + svdup_n_f64(0f64), + svdup_n_f64(0f64), + svdup_n_f64(0f64), + svdup_n_f64(0f64), + ) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_s8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_s8() -> svint8x4_t { + svcreate4_s8(svdup_n_s8(0), svdup_n_s8(0), svdup_n_s8(0), svdup_n_s8(0)) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_s16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_s16() -> svint16x4_t { + svcreate4_s16( + svdup_n_s16(0), + svdup_n_s16(0), + svdup_n_s16(0), + svdup_n_s16(0), + ) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_s32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_s32() -> svint32x4_t { + svcreate4_s32( + svdup_n_s32(0), + svdup_n_s32(0), + svdup_n_s32(0), + svdup_n_s32(0), + ) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_s64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_s64() -> svint64x4_t { + svcreate4_s64( + svdup_n_s64(0), + svdup_n_s64(0), + svdup_n_s64(0), + svdup_n_s64(0), + ) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_u8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_u8() -> svuint8x4_t { + svcreate4_u8(svdup_n_u8(0), svdup_n_u8(0), svdup_n_u8(0), svdup_n_u8(0)) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_u16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_u16() -> svuint16x4_t { + svcreate4_u16( + svdup_n_u16(0), + svdup_n_u16(0), + svdup_n_u16(0), + svdup_n_u16(0), + ) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_u32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_u32() -> svuint32x4_t { + svcreate4_u32( + svdup_n_u32(0), + svdup_n_u32(0), + svdup_n_u32(0), + svdup_n_u32(0), + ) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_u64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_u64() -> svuint64x4_t { + svcreate4_u64( + svdup_n_u64(0), + svdup_n_u64(0), + svdup_n_u64(0), + svdup_n_u64(0), + ) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_f32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_f32() -> svfloat32_t { + svdup_n_f32(0f32) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_f64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_f64() -> svfloat64_t { + svdup_n_f64(0f64) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_s8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_s8() -> svint8_t { + svdup_n_s8(0) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_s16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_s16() -> svint16_t { + svdup_n_s16(0) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_s32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_s32() -> svint32_t { + svdup_n_s32(0) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_s64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_s64() -> svint64_t { + svdup_n_s64(0) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_u8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_u8() -> svuint8_t { + svdup_n_u8(0) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_u16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_u16() -> svuint16_t { + svdup_n_u16(0) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_u32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_u32() -> svuint32_t { + svdup_n_u32(0) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_u64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_u64() -> svuint64_t { + svdup_n_u64(0) +} +#[doc = "Dot product (unsigned × signed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svusdot_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usdot, IMM_INDEX = 0))] +pub fn svusdot_lane_s32( + op1: svint32_t, + op2: svuint8_t, + op3: svint8_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.usdot.lane.nxv4i32" + )] + fn _svusdot_lane_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, + imm_index: i32, + ) -> svint32_t; + } + unsafe { _svusdot_lane_s32(op1, op2.as_signed(), op3, IMM_INDEX) } +} +#[doc = "Dot product (unsigned × signed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svusdot[_s32])"] +#[inline] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usdot))] +pub fn svusdot_s32(op1: svint32_t, op2: svuint8_t, op3: svint8_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usdot.nxv4i32")] + fn _svusdot_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t; + } + unsafe { _svusdot_s32(op1, op2.as_signed(), op3) } +} +#[doc = "Dot product (unsigned × signed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svusdot[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usdot))] +pub fn svusdot_n_s32(op1: svint32_t, op2: svuint8_t, op3: i8) -> svint32_t { + svusdot_s32(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Matrix multiply-accumulate (unsigned × signed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svusmmla[_s32])"] +#[inline] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usmmla))] +pub fn svusmmla_s32(op1: svint32_t, op2: svuint8_t, op3: svint8_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usmmla.nxv4i32")] + fn _svusmmla_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t; + } + unsafe { _svusmmla_s32(op1, op2.as_signed(), op3) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.b16")] + fn _svuzp1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svuzp1_b16(op1.sve_into(), op2.sve_into()) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.b32")] + fn _svuzp1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svuzp1_b32(op1.sve_into(), op2.sve_into()) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.b64")] + fn _svuzp1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svuzp1_b64(op1.sve_into(), op2.sve_into()) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv4f32")] + fn _svuzp1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svuzp1_f32(op1, op2) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv2f64")] + fn _svuzp1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svuzp1_f64(op1, op2) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv16i8")] + fn _svuzp1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svuzp1_s8(op1, op2) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv8i16")] + fn _svuzp1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svuzp1_s16(op1, op2) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv4i32")] + fn _svuzp1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svuzp1_s32(op1, op2) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv2i64")] + fn _svuzp1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svuzp1_s64(op1, op2) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svuzp1_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svuzp1_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svuzp1_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svuzp1_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_b8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv16i1")] + fn _svuzp1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svuzp1_b8(op1, op2) } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_f32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv4f32")] + fn _svuzp1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svuzp1q_f32(op1, op2) } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_f64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv2f64")] + fn _svuzp1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svuzp1q_f64(op1, op2) } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_s8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv16i8")] + fn _svuzp1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svuzp1q_s8(op1, op2) } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_s16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv8i16")] + fn _svuzp1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svuzp1q_s16(op1, op2) } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_s32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv4i32")] + fn _svuzp1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svuzp1q_s32(op1, op2) } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_s64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv2i64")] + fn _svuzp1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svuzp1q_s64(op1, op2) } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_u8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svuzp1q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_u16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svuzp1q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_u32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svuzp1q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_u64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svuzp1q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.b16")] + fn _svuzp2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svuzp2_b16(op1.sve_into(), op2.sve_into()) } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.b32")] + fn _svuzp2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svuzp2_b32(op1.sve_into(), op2.sve_into()) } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.b64")] + fn _svuzp2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svuzp2_b64(op1.sve_into(), op2.sve_into()) } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv4f32")] + fn _svuzp2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svuzp2_f32(op1, op2) } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv2f64")] + fn _svuzp2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svuzp2_f64(op1, op2) } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv16i8")] + fn _svuzp2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svuzp2_s8(op1, op2) } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv8i16")] + fn _svuzp2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svuzp2_s16(op1, op2) } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv4i32")] + fn _svuzp2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svuzp2_s32(op1, op2) } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv2i64")] + fn _svuzp2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svuzp2_s64(op1, op2) } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svuzp2_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svuzp2_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svuzp2_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svuzp2_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_b8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv16i1")] + fn _svuzp2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svuzp2_b8(op1, op2) } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_f32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv4f32")] + fn _svuzp2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svuzp2q_f32(op1, op2) } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_f64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv2f64")] + fn _svuzp2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svuzp2q_f64(op1, op2) } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_s8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv16i8")] + fn _svuzp2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svuzp2q_s8(op1, op2) } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_s16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv8i16")] + fn _svuzp2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svuzp2q_s16(op1, op2) } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_s32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv4i32")] + fn _svuzp2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svuzp2q_s32(op1, op2) } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_s64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv2i64")] + fn _svuzp2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svuzp2q_s64(op1, op2) } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_u8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svuzp2q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_u16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svuzp2q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_u32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svuzp2q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_u64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svuzp2q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b8[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b8_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv16i1.i32" + )] + fn _svwhilele_b8_s32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilele_b8_s32(op1, op2) } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b16[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b16_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv8i1.i32" + )] + fn _svwhilele_b16_s32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilele_b16_s32(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b32[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b32_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv4i1.i32" + )] + fn _svwhilele_b32_s32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilele_b32_s32(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b64[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b64_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv2i1.i32" + )] + fn _svwhilele_b64_s32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilele_b64_s32(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b8[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b8_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv16i1.i64" + )] + fn _svwhilele_b8_s64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilele_b8_s64(op1, op2) } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b16[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b16_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv8i1.i64" + )] + fn _svwhilele_b16_s64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilele_b16_s64(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b32[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b32_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv4i1.i64" + )] + fn _svwhilele_b32_s64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilele_b32_s64(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b64[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b64_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv2i1.i64" + )] + fn _svwhilele_b64_s64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilele_b64_s64(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b8[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b8_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv16i1.i32" + )] + fn _svwhilele_b8_u32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilele_b8_u32(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b16[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b16_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv8i1.i32" + )] + fn _svwhilele_b16_u32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilele_b16_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b32[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b32_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv4i1.i32" + )] + fn _svwhilele_b32_u32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilele_b32_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b64[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b64_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv2i1.i32" + )] + fn _svwhilele_b64_u32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilele_b64_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b8[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b8_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv16i1.i64" + )] + fn _svwhilele_b8_u64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilele_b8_u64(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b16[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b16_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv8i1.i64" + )] + fn _svwhilele_b16_u64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilele_b16_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b32[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b32_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv4i1.i64" + )] + fn _svwhilele_b32_u64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilele_b32_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b64[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b64_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv2i1.i64" + )] + fn _svwhilele_b64_u64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilele_b64_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b8[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b8_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv16i1.i32" + )] + fn _svwhilelt_b8_s32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilelt_b8_s32(op1, op2) } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b16[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b16_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv8i1.i32" + )] + fn _svwhilelt_b16_s32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilelt_b16_s32(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b32[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b32_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv4i1.i32" + )] + fn _svwhilelt_b32_s32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilelt_b32_s32(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b64[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b64_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv2i1.i32" + )] + fn _svwhilelt_b64_s32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilelt_b64_s32(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b8[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b8_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv16i1.i64" + )] + fn _svwhilelt_b8_s64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilelt_b8_s64(op1, op2) } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b16[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b16_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv8i1.i64" + )] + fn _svwhilelt_b16_s64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilelt_b16_s64(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b32[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b32_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv4i1.i64" + )] + fn _svwhilelt_b32_s64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilelt_b32_s64(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b64[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b64_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv2i1.i64" + )] + fn _svwhilelt_b64_s64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilelt_b64_s64(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b8[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b8_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv16i1.i32" + )] + fn _svwhilelt_b8_u32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilelt_b8_u32(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b16[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b16_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv8i1.i32" + )] + fn _svwhilelt_b16_u32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilelt_b16_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b32[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b32_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv4i1.i32" + )] + fn _svwhilelt_b32_u32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilelt_b32_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b64[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b64_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv2i1.i32" + )] + fn _svwhilelt_b64_u32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilelt_b64_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b8[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b8_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv16i1.i64" + )] + fn _svwhilelt_b8_u64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilelt_b8_u64(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b16[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b16_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv8i1.i64" + )] + fn _svwhilelt_b16_u64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilelt_b16_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b32[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b32_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv4i1.i64" + )] + fn _svwhilelt_b32_u64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilelt_b32_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b64[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b64_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv2i1.i64" + )] + fn _svwhilelt_b64_u64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilelt_b64_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Write to the first-fault register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwrffr)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(wrffr))] +pub fn svwrffr(op: svbool_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.wrffr")] + fn _svwrffr(op: svbool_t); + } + unsafe { _svwrffr(op) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.b16")] + fn _svzip1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svzip1_b16(op1.sve_into(), op2.sve_into()) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.b32")] + fn _svzip1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svzip1_b32(op1.sve_into(), op2.sve_into()) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.b64")] + fn _svzip1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svzip1_b64(op1.sve_into(), op2.sve_into()) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv4f32")] + fn _svzip1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svzip1_f32(op1, op2) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv2f64")] + fn _svzip1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svzip1_f64(op1, op2) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv16i8")] + fn _svzip1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svzip1_s8(op1, op2) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv8i16")] + fn _svzip1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svzip1_s16(op1, op2) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv4i32")] + fn _svzip1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svzip1_s32(op1, op2) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv2i64")] + fn _svzip1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svzip1_s64(op1, op2) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svzip1_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svzip1_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svzip1_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svzip1_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_b8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv16i1")] + fn _svzip1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svzip1_b8(op1, op2) } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_f32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv4f32")] + fn _svzip1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svzip1q_f32(op1, op2) } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_f64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv2f64")] + fn _svzip1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svzip1q_f64(op1, op2) } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_s8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv16i8")] + fn _svzip1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svzip1q_s8(op1, op2) } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_s16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv8i16")] + fn _svzip1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svzip1q_s16(op1, op2) } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_s32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv4i32")] + fn _svzip1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svzip1q_s32(op1, op2) } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_s64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv2i64")] + fn _svzip1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svzip1q_s64(op1, op2) } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_u8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svzip1q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_u16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svzip1q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_u32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svzip1q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_u64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svzip1q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.b16")] + fn _svzip2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svzip2_b16(op1.sve_into(), op2.sve_into()) } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.b32")] + fn _svzip2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svzip2_b32(op1.sve_into(), op2.sve_into()) } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.b64")] + fn _svzip2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svzip2_b64(op1.sve_into(), op2.sve_into()) } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv4f32")] + fn _svzip2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svzip2_f32(op1, op2) } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv2f64")] + fn _svzip2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svzip2_f64(op1, op2) } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv16i8")] + fn _svzip2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svzip2_s8(op1, op2) } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv8i16")] + fn _svzip2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svzip2_s16(op1, op2) } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv4i32")] + fn _svzip2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svzip2_s32(op1, op2) } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv2i64")] + fn _svzip2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svzip2_s64(op1, op2) } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svzip2_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svzip2_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svzip2_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svzip2_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_b8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv16i1")] + fn _svzip2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svzip2_b8(op1, op2) } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_f32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv4f32")] + fn _svzip2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svzip2q_f32(op1, op2) } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_f64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv2f64")] + fn _svzip2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svzip2q_f64(op1, op2) } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_s8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv16i8")] + fn _svzip2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svzip2q_s8(op1, op2) } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_s16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv8i16")] + fn _svzip2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svzip2q_s16(op1, op2) } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_s32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv4i32")] + fn _svzip2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svzip2q_s32(op1, op2) } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_s64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv2i64")] + fn _svzip2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svzip2q_s64(op1, op2) } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_u8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svzip2q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_u16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svzip2q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_u32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svzip2q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_u64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svzip2q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} diff --git a/library/stdarch/crates/core_arch/src/aarch64/sve/ld_st_tests_aarch64.rs b/library/stdarch/crates/core_arch/src/aarch64/sve/ld_st_tests_aarch64.rs new file mode 100644 index 0000000000000..ca76106cab089 --- /dev/null +++ b/library/stdarch/crates/core_arch/src/aarch64/sve/ld_st_tests_aarch64.rs @@ -0,0 +1,12794 @@ +// This code is automatically generated. DO NOT MODIFY. +// +// Instead, modify `crates/stdarch-gen-arm/spec/sve` and run the following command to re-generate +// this file: +// +// ``` +// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec +// ``` +#![allow(unused)] +use super::*; +use std::boxed::Box; +use std::convert::{TryFrom, TryInto}; +use std::sync::LazyLock; +use std::vec::Vec; +use stdarch_test::simd_test; +static F32_DATA: LazyLock<[f32; 64 * 5]> = LazyLock::new(|| { + (0..64 * 5) + .map(|i| i as f32) + .collect::>() + .try_into() + .expect("f32 data incorrectly initialised") +}); +static F64_DATA: LazyLock<[f64; 32 * 5]> = LazyLock::new(|| { + (0..32 * 5) + .map(|i| i as f64) + .collect::>() + .try_into() + .expect("f64 data incorrectly initialised") +}); +static I8_DATA: LazyLock<[i8; 256 * 5]> = LazyLock::new(|| { + (0..256 * 5) + .map(|i| ((i + 128) % 256 - 128) as i8) + .collect::>() + .try_into() + .expect("i8 data incorrectly initialised") +}); +static I16_DATA: LazyLock<[i16; 128 * 5]> = LazyLock::new(|| { + (0..128 * 5) + .map(|i| i as i16) + .collect::>() + .try_into() + .expect("i16 data incorrectly initialised") +}); +static I32_DATA: LazyLock<[i32; 64 * 5]> = LazyLock::new(|| { + (0..64 * 5) + .map(|i| i as i32) + .collect::>() + .try_into() + .expect("i32 data incorrectly initialised") +}); +static I64_DATA: LazyLock<[i64; 32 * 5]> = LazyLock::new(|| { + (0..32 * 5) + .map(|i| i as i64) + .collect::>() + .try_into() + .expect("i64 data incorrectly initialised") +}); +static U8_DATA: LazyLock<[u8; 256 * 5]> = LazyLock::new(|| { + (0..256 * 5) + .map(|i| i as u8) + .collect::>() + .try_into() + .expect("u8 data incorrectly initialised") +}); +static U16_DATA: LazyLock<[u16; 128 * 5]> = LazyLock::new(|| { + (0..128 * 5) + .map(|i| i as u16) + .collect::>() + .try_into() + .expect("u16 data incorrectly initialised") +}); +static U32_DATA: LazyLock<[u32; 64 * 5]> = LazyLock::new(|| { + (0..64 * 5) + .map(|i| i as u32) + .collect::>() + .try_into() + .expect("u32 data incorrectly initialised") +}); +static U64_DATA: LazyLock<[u64; 32 * 5]> = LazyLock::new(|| { + (0..32 * 5) + .map(|i| i as u64) + .collect::>() + .try_into() + .expect("u64 data incorrectly initialised") +}); +#[target_feature(enable = "sve")] +fn assert_vector_matches_f32(vector: svfloat32_t, expected: svfloat32_t, defined: svbool_t) { + assert!(svptest_first(svptrue_b32(), defined)); + let cmp = svcmpne_f32(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_f64(vector: svfloat64_t, expected: svfloat64_t, defined: svbool_t) { + assert!(svptest_first(svptrue_b64(), defined)); + let cmp = svcmpne_f64(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i8(vector: svint8_t, expected: svint8_t, defined: svbool_t) { + assert!(svptest_first(svptrue_b8(), defined)); + let cmp = svcmpne_s8(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i16(vector: svint16_t, expected: svint16_t, defined: svbool_t) { + assert!(svptest_first(svptrue_b16(), defined)); + let cmp = svcmpne_s16(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i32(vector: svint32_t, expected: svint32_t, defined: svbool_t) { + assert!(svptest_first(svptrue_b32(), defined)); + let cmp = svcmpne_s32(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i64(vector: svint64_t, expected: svint64_t, defined: svbool_t) { + assert!(svptest_first(svptrue_b64(), defined)); + let cmp = svcmpne_s64(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u8(vector: svuint8_t, expected: svuint8_t, defined: svbool_t) { + assert!(svptest_first(svptrue_b8(), defined)); + let cmp = svcmpne_u8(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u16(vector: svuint16_t, expected: svuint16_t, defined: svbool_t) { + assert!(svptest_first(svptrue_b16(), defined)); + let cmp = svcmpne_u16(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u32(vector: svuint32_t, expected: svuint32_t, defined: svbool_t) { + assert!(svptest_first(svptrue_b32(), defined)); + let cmp = svcmpne_u32(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u64(vector: svuint64_t, expected: svuint64_t, defined: svbool_t) { + assert!(svptest_first(svptrue_b64(), defined)); + let cmp = svcmpne_u64(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_f32_with_svst1_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + svst1_f32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_f32(svptrue_b32(), storage.as_ptr() as *const f32); + let defined = svrdffr(); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_f64_with_svst1_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + svst1_f64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_f64(svptrue_b64(), storage.as_ptr() as *const f64); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_s8_with_svst1_s8() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_s8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1_s8(svptrue_b8(), storage.as_ptr() as *const i8); + let defined = svrdffr(); + assert_vector_matches_i8( + loaded, + svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_s16_with_svst1_s16() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_s16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1_s16(svptrue_b16(), storage.as_ptr() as *const i16); + let defined = svrdffr(); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_s32_with_svst1_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_s32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_s32(svptrue_b32(), storage.as_ptr() as *const i32); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_s64_with_svst1_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_s64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_s64(svptrue_b64(), storage.as_ptr() as *const i64); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_u8_with_svst1_u8() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_u8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1_u8(svptrue_b8(), storage.as_ptr() as *const u8); + let defined = svrdffr(); + assert_vector_matches_u8( + loaded, + svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_u16_with_svst1_u16() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_u16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1_u16(svptrue_b16(), storage.as_ptr() as *const u16); + let defined = svrdffr(); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_u32_with_svst1_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_u32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_u32(svptrue_b32(), storage.as_ptr() as *const u32); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_u64_with_svst1_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_u64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_u64(svptrue_b64(), storage.as_ptr() as *const u64); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s32index_f32_with_svst1_scatter_s32index_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let indices = svindex_s32(0, 1); + svst1_scatter_s32index_f32(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_gather_s32index_f32(svptrue_b32(), storage.as_ptr() as *const f32, indices); + let defined = svrdffr(); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s32index_s32_with_svst1_scatter_s32index_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s32(0, 1); + svst1_scatter_s32index_s32(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_gather_s32index_s32(svptrue_b32(), storage.as_ptr() as *const i32, indices); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s32index_u32_with_svst1_scatter_s32index_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s32(0, 1); + svst1_scatter_s32index_u32(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_gather_s32index_u32(svptrue_b32(), storage.as_ptr() as *const u32, indices); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s64index_f64_with_svst1_scatter_s64index_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let indices = svindex_s64(0, 1); + svst1_scatter_s64index_f64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_gather_s64index_f64(svptrue_b64(), storage.as_ptr() as *const f64, indices); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s64index_s64_with_svst1_scatter_s64index_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1_scatter_s64index_s64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_gather_s64index_s64(svptrue_b64(), storage.as_ptr() as *const i64, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s64index_u64_with_svst1_scatter_s64index_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1_scatter_s64index_u64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_gather_s64index_u64(svptrue_b64(), storage.as_ptr() as *const u64, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32index_f32_with_svst1_scatter_u32index_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let indices = svindex_u32(0, 1); + svst1_scatter_u32index_f32(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_gather_u32index_f32(svptrue_b32(), storage.as_ptr() as *const f32, indices); + let defined = svrdffr(); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32index_s32_with_svst1_scatter_u32index_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u32(0, 1); + svst1_scatter_u32index_s32(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_gather_u32index_s32(svptrue_b32(), storage.as_ptr() as *const i32, indices); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32index_u32_with_svst1_scatter_u32index_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u32(0, 1); + svst1_scatter_u32index_u32(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_gather_u32index_u32(svptrue_b32(), storage.as_ptr() as *const u32, indices); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64index_f64_with_svst1_scatter_u64index_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let indices = svindex_u64(0, 1); + svst1_scatter_u64index_f64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_gather_u64index_f64(svptrue_b64(), storage.as_ptr() as *const f64, indices); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64index_s64_with_svst1_scatter_u64index_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1_scatter_u64index_s64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_gather_u64index_s64(svptrue_b64(), storage.as_ptr() as *const i64, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64index_u64_with_svst1_scatter_u64index_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1_scatter_u64index_u64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_gather_u64index_u64(svptrue_b64(), storage.as_ptr() as *const u64, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s32offset_f32_with_svst1_scatter_s32offset_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let offsets = svindex_s32(0, 4u32.try_into().unwrap()); + svst1_scatter_s32offset_f32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_gather_s32offset_f32(svptrue_b32(), storage.as_ptr() as *const f32, offsets); + let defined = svrdffr(); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s32offset_s32_with_svst1_scatter_s32offset_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 4u32.try_into().unwrap()); + svst1_scatter_s32offset_s32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_gather_s32offset_s32(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s32offset_u32_with_svst1_scatter_s32offset_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 4u32.try_into().unwrap()); + svst1_scatter_s32offset_u32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_gather_s32offset_u32(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s64offset_f64_with_svst1_scatter_s64offset_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + svst1_scatter_s64offset_f64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_gather_s64offset_f64(svptrue_b64(), storage.as_ptr() as *const f64, offsets); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s64offset_s64_with_svst1_scatter_s64offset_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + svst1_scatter_s64offset_s64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_gather_s64offset_s64(svptrue_b64(), storage.as_ptr() as *const i64, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s64offset_u64_with_svst1_scatter_s64offset_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + svst1_scatter_s64offset_u64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_gather_s64offset_u64(svptrue_b64(), storage.as_ptr() as *const u64, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32offset_f32_with_svst1_scatter_u32offset_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32offset_f32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_gather_u32offset_f32(svptrue_b32(), storage.as_ptr() as *const f32, offsets); + let defined = svrdffr(); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32offset_s32_with_svst1_scatter_u32offset_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32offset_s32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_gather_u32offset_s32(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32offset_u32_with_svst1_scatter_u32offset_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32offset_u32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_gather_u32offset_u32(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64offset_f64_with_svst1_scatter_u64offset_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + svst1_scatter_u64offset_f64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_gather_u64offset_f64(svptrue_b64(), storage.as_ptr() as *const f64, offsets); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64offset_s64_with_svst1_scatter_u64offset_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + svst1_scatter_u64offset_s64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_gather_u64offset_s64(svptrue_b64(), storage.as_ptr() as *const i64, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64offset_u64_with_svst1_scatter_u64offset_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + svst1_scatter_u64offset_u64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_gather_u64offset_u64(svptrue_b64(), storage.as_ptr() as *const u64, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_f64_with_svst1_scatter_u64base_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_f64(svptrue_b64(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_gather_u64base_f64(svptrue_b64(), bases); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_s64_with_svst1_scatter_u64base_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_s64(svptrue_b64(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_gather_u64base_s64(svptrue_b64(), bases); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_u64_with_svst1_scatter_u64base_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_u64(svptrue_b64(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_gather_u64base_u64(svptrue_b64(), bases); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32base_index_f32_with_svst1_scatter_u32base_index_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32base_index_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_gather_u32base_index_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + ); + let defined = svrdffr(); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32base_index_s32_with_svst1_scatter_u32base_index_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32base_index_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_gather_u32base_index_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32base_index_u32_with_svst1_scatter_u32base_index_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32base_index_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_gather_u32base_index_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_index_f64_with_svst1_scatter_u64base_index_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_index_f64(svptrue_b64(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_gather_u64base_index_f64(svptrue_b64(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_index_s64_with_svst1_scatter_u64base_index_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_index_s64(svptrue_b64(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_gather_u64base_index_s64(svptrue_b64(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_index_u64_with_svst1_scatter_u64base_index_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_index_u64(svptrue_b64(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_gather_u64base_index_u64(svptrue_b64(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32base_offset_f32_with_svst1_scatter_u32base_offset_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32base_offset_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_gather_u32base_offset_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32base_offset_s32_with_svst1_scatter_u32base_offset_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32base_offset_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_gather_u32base_offset_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32base_offset_u32_with_svst1_scatter_u32base_offset_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32base_offset_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_gather_u32base_offset_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_offset_f64_with_svst1_scatter_u64base_offset_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_offset_f64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_gather_u64base_offset_f64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_offset_s64_with_svst1_scatter_u64base_offset_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_offset_s64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_gather_u64base_offset_s64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_offset_u64_with_svst1_scatter_u64base_offset_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_offset_u64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_gather_u64base_offset_u64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_f32_with_svst1_vnum_f32() { + let len = svcntw() as usize; + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); + svst1_vnum_f32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_vnum_f32(svptrue_b32(), storage.as_ptr() as *const f32, 1); + let defined = svrdffr(); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_f64_with_svst1_vnum_f64() { + let len = svcntd() as usize; + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); + svst1_vnum_f64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_vnum_f64(svptrue_b64(), storage.as_ptr() as *const f64, 1); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_s8_with_svst1_vnum_s8() { + let len = svcntb() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_s8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1_vnum_s8(svptrue_b8(), storage.as_ptr() as *const i8, 1); + let defined = svrdffr(); + assert_vector_matches_i8( + loaded, + svindex_s8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_s16_with_svst1_vnum_s16() { + let len = svcnth() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_s16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1_vnum_s16(svptrue_b16(), storage.as_ptr() as *const i16, 1); + let defined = svrdffr(); + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_s32_with_svst1_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_s32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_vnum_s32(svptrue_b32(), storage.as_ptr() as *const i32, 1); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_s64_with_svst1_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_s64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_vnum_s64(svptrue_b64(), storage.as_ptr() as *const i64, 1); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_u8_with_svst1_vnum_u8() { + let len = svcntb() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_u8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1_vnum_u8(svptrue_b8(), storage.as_ptr() as *const u8, 1); + let defined = svrdffr(); + assert_vector_matches_u8( + loaded, + svindex_u8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_u16_with_svst1_vnum_u16() { + let len = svcnth() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_u16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1_vnum_u16(svptrue_b16(), storage.as_ptr() as *const u16, 1); + let defined = svrdffr(); + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_u32_with_svst1_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_u32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_vnum_u32(svptrue_b32(), storage.as_ptr() as *const u32, 1); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_u64_with_svst1_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_u64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_vnum_u64(svptrue_b64(), storage.as_ptr() as *const u64, 1); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_f32() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_f32 due to SVE vector length"); + return; + } + let ptr = F32_DATA.as_ptr(); + svsetffr(); + let loaded = svld1ro_f32(svptrue_b32(), ptr); + let defined = svrdffr(); + assert_vector_matches_f32( + loaded, + svtrn1q_f32( + svdupq_n_f32(0usize as f32, 1usize as f32, 2usize as f32, 3usize as f32), + svdupq_n_f32(4usize as f32, 5usize as f32, 6usize as f32, 7usize as f32), + ), + defined, + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_f64() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_f64 due to SVE vector length"); + return; + } + let ptr = F64_DATA.as_ptr(); + svsetffr(); + let loaded = svld1ro_f64(svptrue_b64(), ptr); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svtrn1q_f64( + svdupq_n_f64(0usize as f64, 1usize as f64), + svdupq_n_f64(2usize as f64, 3usize as f64), + ), + defined, + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_s8() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_s8 due to SVE vector length"); + return; + } + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let loaded = svld1ro_s8(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_i8( + loaded, + svtrn1q_s8( + svdupq_n_s8( + 0usize as i8, + 1usize as i8, + 2usize as i8, + 3usize as i8, + 4usize as i8, + 5usize as i8, + 6usize as i8, + 7usize as i8, + 8usize as i8, + 9usize as i8, + 10usize as i8, + 11usize as i8, + 12usize as i8, + 13usize as i8, + 14usize as i8, + 15usize as i8, + ), + svdupq_n_s8( + 16usize as i8, + 17usize as i8, + 18usize as i8, + 19usize as i8, + 20usize as i8, + 21usize as i8, + 22usize as i8, + 23usize as i8, + 24usize as i8, + 25usize as i8, + 26usize as i8, + 27usize as i8, + 28usize as i8, + 29usize as i8, + 30usize as i8, + 31usize as i8, + ), + ), + defined, + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_s16() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_s16 due to SVE vector length"); + return; + } + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let loaded = svld1ro_s16(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_i16( + loaded, + svtrn1q_s16( + svdupq_n_s16( + 0usize as i16, + 1usize as i16, + 2usize as i16, + 3usize as i16, + 4usize as i16, + 5usize as i16, + 6usize as i16, + 7usize as i16, + ), + svdupq_n_s16( + 8usize as i16, + 9usize as i16, + 10usize as i16, + 11usize as i16, + 12usize as i16, + 13usize as i16, + 14usize as i16, + 15usize as i16, + ), + ), + defined, + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_s32() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_s32 due to SVE vector length"); + return; + } + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let loaded = svld1ro_s32(svptrue_b32(), ptr); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svtrn1q_s32( + svdupq_n_s32(0usize as i32, 1usize as i32, 2usize as i32, 3usize as i32), + svdupq_n_s32(4usize as i32, 5usize as i32, 6usize as i32, 7usize as i32), + ), + defined, + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_s64() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_s64 due to SVE vector length"); + return; + } + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = svld1ro_s64(svptrue_b64(), ptr); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svtrn1q_s64( + svdupq_n_s64(0usize as i64, 1usize as i64), + svdupq_n_s64(2usize as i64, 3usize as i64), + ), + defined, + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_u8() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_u8 due to SVE vector length"); + return; + } + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let loaded = svld1ro_u8(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_u8( + loaded, + svtrn1q_u8( + svdupq_n_u8( + 0usize as u8, + 1usize as u8, + 2usize as u8, + 3usize as u8, + 4usize as u8, + 5usize as u8, + 6usize as u8, + 7usize as u8, + 8usize as u8, + 9usize as u8, + 10usize as u8, + 11usize as u8, + 12usize as u8, + 13usize as u8, + 14usize as u8, + 15usize as u8, + ), + svdupq_n_u8( + 16usize as u8, + 17usize as u8, + 18usize as u8, + 19usize as u8, + 20usize as u8, + 21usize as u8, + 22usize as u8, + 23usize as u8, + 24usize as u8, + 25usize as u8, + 26usize as u8, + 27usize as u8, + 28usize as u8, + 29usize as u8, + 30usize as u8, + 31usize as u8, + ), + ), + defined, + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_u16() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_u16 due to SVE vector length"); + return; + } + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let loaded = svld1ro_u16(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_u16( + loaded, + svtrn1q_u16( + svdupq_n_u16( + 0usize as u16, + 1usize as u16, + 2usize as u16, + 3usize as u16, + 4usize as u16, + 5usize as u16, + 6usize as u16, + 7usize as u16, + ), + svdupq_n_u16( + 8usize as u16, + 9usize as u16, + 10usize as u16, + 11usize as u16, + 12usize as u16, + 13usize as u16, + 14usize as u16, + 15usize as u16, + ), + ), + defined, + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_u32() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_u32 due to SVE vector length"); + return; + } + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let loaded = svld1ro_u32(svptrue_b32(), ptr); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svtrn1q_u32( + svdupq_n_u32(0usize as u32, 1usize as u32, 2usize as u32, 3usize as u32), + svdupq_n_u32(4usize as u32, 5usize as u32, 6usize as u32, 7usize as u32), + ), + defined, + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_u64() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_u64 due to SVE vector length"); + return; + } + let ptr = U64_DATA.as_ptr(); + svsetffr(); + let loaded = svld1ro_u64(svptrue_b64(), ptr); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svtrn1q_u64( + svdupq_n_u64(0usize as u64, 1usize as u64), + svdupq_n_u64(2usize as u64, 3usize as u64), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_f32() { + let ptr = F32_DATA.as_ptr(); + svsetffr(); + let loaded = svld1rq_f32(svptrue_b32(), ptr); + let defined = svrdffr(); + assert_vector_matches_f32( + loaded, + svdupq_n_f32(0usize as f32, 1usize as f32, 2usize as f32, 3usize as f32), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_f64() { + let ptr = F64_DATA.as_ptr(); + svsetffr(); + let loaded = svld1rq_f64(svptrue_b64(), ptr); + let defined = svrdffr(); + assert_vector_matches_f64(loaded, svdupq_n_f64(0usize as f64, 1usize as f64), defined); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_s8() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let loaded = svld1rq_s8(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_i8( + loaded, + svdupq_n_s8( + 0usize as i8, + 1usize as i8, + 2usize as i8, + 3usize as i8, + 4usize as i8, + 5usize as i8, + 6usize as i8, + 7usize as i8, + 8usize as i8, + 9usize as i8, + 10usize as i8, + 11usize as i8, + 12usize as i8, + 13usize as i8, + 14usize as i8, + 15usize as i8, + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_s16() { + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let loaded = svld1rq_s16(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_i16( + loaded, + svdupq_n_s16( + 0usize as i16, + 1usize as i16, + 2usize as i16, + 3usize as i16, + 4usize as i16, + 5usize as i16, + 6usize as i16, + 7usize as i16, + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_s32() { + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let loaded = svld1rq_s32(svptrue_b32(), ptr); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svdupq_n_s32(0usize as i32, 1usize as i32, 2usize as i32, 3usize as i32), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_s64() { + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = svld1rq_s64(svptrue_b64(), ptr); + let defined = svrdffr(); + assert_vector_matches_i64(loaded, svdupq_n_s64(0usize as i64, 1usize as i64), defined); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_u8() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let loaded = svld1rq_u8(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_u8( + loaded, + svdupq_n_u8( + 0usize as u8, + 1usize as u8, + 2usize as u8, + 3usize as u8, + 4usize as u8, + 5usize as u8, + 6usize as u8, + 7usize as u8, + 8usize as u8, + 9usize as u8, + 10usize as u8, + 11usize as u8, + 12usize as u8, + 13usize as u8, + 14usize as u8, + 15usize as u8, + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_u16() { + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let loaded = svld1rq_u16(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_u16( + loaded, + svdupq_n_u16( + 0usize as u16, + 1usize as u16, + 2usize as u16, + 3usize as u16, + 4usize as u16, + 5usize as u16, + 6usize as u16, + 7usize as u16, + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_u32() { + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let loaded = svld1rq_u32(svptrue_b32(), ptr); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svdupq_n_u32(0usize as u32, 1usize as u32, 2usize as u32, 3usize as u32), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_u64() { + let ptr = U64_DATA.as_ptr(); + svsetffr(); + let loaded = svld1rq_u64(svptrue_b64(), ptr); + let defined = svrdffr(); + assert_vector_matches_u64(loaded, svdupq_n_u64(0usize as u64, 1usize as u64), defined); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_s32offset_s32_with_svst1b_scatter_s32offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 1u32.try_into().unwrap()); + svst1b_scatter_s32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_s32offset_s32(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s32offset_s32_with_svst1h_scatter_s32offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 2u32.try_into().unwrap()); + svst1h_scatter_s32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_s32offset_s32(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_s32offset_u32_with_svst1b_scatter_s32offset_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 1u32.try_into().unwrap()); + svst1b_scatter_s32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_gather_s32offset_u32(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s32offset_u32_with_svst1h_scatter_s32offset_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 2u32.try_into().unwrap()); + svst1h_scatter_s32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_s32offset_u32(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_s64offset_s64_with_svst1b_scatter_s64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svst1b_scatter_s64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_s64offset_s64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s64offset_s64_with_svst1h_scatter_s64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svst1h_scatter_s64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_s64offset_s64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_s64offset_s64_with_svst1w_scatter_s64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svst1w_scatter_s64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1sw_gather_s64offset_s64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_s64offset_u64_with_svst1b_scatter_s64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svst1b_scatter_s64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_gather_s64offset_u64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s64offset_u64_with_svst1h_scatter_s64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svst1h_scatter_s64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_s64offset_u64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_s64offset_u64_with_svst1w_scatter_s64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svst1w_scatter_s64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1sw_gather_s64offset_u64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u32offset_s32_with_svst1b_scatter_u32offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u32offset_s32(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32offset_s32_with_svst1h_scatter_u32offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_u32offset_s32(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u32offset_u32_with_svst1b_scatter_u32offset_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_gather_u32offset_u32(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32offset_u32_with_svst1h_scatter_u32offset_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_u32offset_u32(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u64offset_s64_with_svst1b_scatter_u64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svst1b_scatter_u64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u64offset_s64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64offset_s64_with_svst1h_scatter_u64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svst1h_scatter_u64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_u64offset_s64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64offset_s64_with_svst1w_scatter_u64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svst1w_scatter_u64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1sw_gather_u64offset_s64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u64offset_u64_with_svst1b_scatter_u64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svst1b_scatter_u64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_gather_u64offset_u64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64offset_u64_with_svst1h_scatter_u64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svst1h_scatter_u64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_u64offset_u64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64offset_u64_with_svst1w_scatter_u64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svst1w_scatter_u64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1sw_gather_u64offset_u64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u32base_offset_s32_with_svst1b_scatter_u32base_offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32base_offset_s32_with_svst1h_scatter_u32base_offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u32base_offset_u32_with_svst1b_scatter_u32base_offset_u32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32base_offset_u32_with_svst1h_scatter_u32base_offset_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u64base_offset_s64_with_svst1b_scatter_u64base_offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64base_offset_s64_with_svst1h_scatter_u64base_offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64base_offset_s64_with_svst1w_scatter_u64base_offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u64base_offset_u64_with_svst1b_scatter_u64base_offset_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64base_offset_u64_with_svst1h_scatter_u64base_offset_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64base_offset_u64_with_svst1w_scatter_u64base_offset_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u64base_s64_with_svst1b_scatter_u64base_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_s64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u64base_s64(svptrue_b8(), bases); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64base_s64_with_svst1h_scatter_u64base_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_s64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u64base_s64(svptrue_b16(), bases); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64base_s64_with_svst1w_scatter_u64base_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_s64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_gather_u64base_s64(svptrue_b32(), bases); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u64base_u64_with_svst1b_scatter_u64base_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_u64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u64base_u64(svptrue_b8(), bases); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64base_u64_with_svst1h_scatter_u64base_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_u64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u64base_u64(svptrue_b16(), bases); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64base_u64_with_svst1w_scatter_u64base_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_u64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_gather_u64base_u64(svptrue_b32(), bases); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_s16_with_svst1b_s16() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_s16(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_s16(svptrue_b8(), storage.as_ptr() as *const i8); + let defined = svrdffr(); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_s32_with_svst1b_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_s32(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_s32(svptrue_b8(), storage.as_ptr() as *const i8); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_s32_with_svst1h_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_s32(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_s32(svptrue_b16(), storage.as_ptr() as *const i16); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_s64_with_svst1b_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_s64(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_s64(svptrue_b8(), storage.as_ptr() as *const i8); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_s64_with_svst1h_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_s64(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_s64(svptrue_b16(), storage.as_ptr() as *const i16); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_s64_with_svst1w_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1w_s64(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_s64(svptrue_b32(), storage.as_ptr() as *const i32); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_u16_with_svst1b_u16() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_u16(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_u16(svptrue_b8(), storage.as_ptr() as *const i8); + let defined = svrdffr(); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_u32_with_svst1b_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_u32(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_u32(svptrue_b8(), storage.as_ptr() as *const i8); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_u32_with_svst1h_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_u32(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1sh_u32(svptrue_b16(), storage.as_ptr() as *const i16); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_u64_with_svst1b_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_u64(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_u64(svptrue_b8(), storage.as_ptr() as *const i8); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_u64_with_svst1h_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_u64(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1sh_u64(svptrue_b16(), storage.as_ptr() as *const i16); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_u64_with_svst1w_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1w_u64(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1sw_u64(svptrue_b32(), storage.as_ptr() as *const i32); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_vnum_s16_with_svst1b_vnum_s16() { + let len = svcnth() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_s16(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_vnum_s16(svptrue_b8(), storage.as_ptr() as *const i8, 1); + let defined = svrdffr(); + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_vnum_s32_with_svst1b_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_s32(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_vnum_s32(svptrue_b8(), storage.as_ptr() as *const i8, 1); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_vnum_s32_with_svst1h_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_s32(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_vnum_s32(svptrue_b16(), storage.as_ptr() as *const i16, 1); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_vnum_s64_with_svst1b_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_s64(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_vnum_s64(svptrue_b8(), storage.as_ptr() as *const i8, 1); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_vnum_s64_with_svst1h_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_s64(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_vnum_s64(svptrue_b16(), storage.as_ptr() as *const i16, 1); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_vnum_s64_with_svst1w_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1w_vnum_s64(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_vnum_s64(svptrue_b32(), storage.as_ptr() as *const i32, 1); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_vnum_u16_with_svst1b_vnum_u16() { + let len = svcnth() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_u16(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_vnum_u16(svptrue_b8(), storage.as_ptr() as *const i8, 1); + let defined = svrdffr(); + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_vnum_u32_with_svst1b_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_u32(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_vnum_u32(svptrue_b8(), storage.as_ptr() as *const i8, 1); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_vnum_u32_with_svst1h_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_u32(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1sh_vnum_u32(svptrue_b16(), storage.as_ptr() as *const i16, 1); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_vnum_u64_with_svst1b_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_u64(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_vnum_u64(svptrue_b8(), storage.as_ptr() as *const i8, 1); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_vnum_u64_with_svst1h_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_u64(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1sh_vnum_u64(svptrue_b16(), storage.as_ptr() as *const i16, 1); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_vnum_u64_with_svst1w_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1w_vnum_u64(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1sw_vnum_u64(svptrue_b32(), storage.as_ptr() as *const i32, 1); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s32index_s32_with_svst1h_scatter_s32index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s32(0, 1); + svst1h_scatter_s32index_s32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_s32index_s32(svptrue_b16(), storage.as_ptr() as *const i16, indices); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s32index_u32_with_svst1h_scatter_s32index_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s32(0, 1); + svst1h_scatter_s32index_u32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_s32index_u32(svptrue_b16(), storage.as_ptr() as *const i16, indices); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s64index_s64_with_svst1h_scatter_s64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1h_scatter_s64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_s64index_s64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_s64index_s64_with_svst1w_scatter_s64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1w_scatter_s64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1sw_gather_s64index_s64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s64index_u64_with_svst1h_scatter_s64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1h_scatter_s64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_s64index_u64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_s64index_u64_with_svst1w_scatter_s64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1w_scatter_s64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1sw_gather_s64index_u64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32index_s32_with_svst1h_scatter_u32index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u32(0, 1); + svst1h_scatter_u32index_s32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_u32index_s32(svptrue_b16(), storage.as_ptr() as *const i16, indices); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32index_u32_with_svst1h_scatter_u32index_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u32(0, 1); + svst1h_scatter_u32index_u32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_u32index_u32(svptrue_b16(), storage.as_ptr() as *const i16, indices); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64index_s64_with_svst1h_scatter_u64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1h_scatter_u64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_u64index_s64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64index_s64_with_svst1w_scatter_u64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1w_scatter_u64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1sw_gather_u64index_s64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64index_u64_with_svst1h_scatter_u64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1h_scatter_u64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_u64index_u64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64index_u64_with_svst1w_scatter_u64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1w_scatter_u64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1sw_gather_u64index_u64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32base_index_s32_with_svst1h_scatter_u32base_index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32base_index_u32_with_svst1h_scatter_u32base_index_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64base_index_s64_with_svst1h_scatter_u64base_index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64base_index_s64_with_svst1w_scatter_u64base_index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64base_index_u64_with_svst1h_scatter_u64base_index_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64base_index_u64_with_svst1w_scatter_u64base_index_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_s32offset_s32_with_svst1b_scatter_s32offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 1u32.try_into().unwrap()); + svst1b_scatter_s32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_s32offset_s32(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s32offset_s32_with_svst1h_scatter_s32offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 2u32.try_into().unwrap()); + svst1h_scatter_s32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_s32offset_s32(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_s32offset_u32_with_svst1b_scatter_s32offset_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 1u32.try_into().unwrap()); + svst1b_scatter_s32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_gather_s32offset_u32(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s32offset_u32_with_svst1h_scatter_s32offset_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 2u32.try_into().unwrap()); + svst1h_scatter_s32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_s32offset_u32(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_s64offset_s64_with_svst1b_scatter_s64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svst1b_scatter_s64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_s64offset_s64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s64offset_s64_with_svst1h_scatter_s64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svst1h_scatter_s64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_s64offset_s64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_s64offset_s64_with_svst1w_scatter_s64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svst1w_scatter_s64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1uw_gather_s64offset_s64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_s64offset_u64_with_svst1b_scatter_s64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svst1b_scatter_s64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_gather_s64offset_u64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s64offset_u64_with_svst1h_scatter_s64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svst1h_scatter_s64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_s64offset_u64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_s64offset_u64_with_svst1w_scatter_s64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svst1w_scatter_s64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1uw_gather_s64offset_u64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u32offset_s32_with_svst1b_scatter_u32offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u32offset_s32(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32offset_s32_with_svst1h_scatter_u32offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_u32offset_s32(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u32offset_u32_with_svst1b_scatter_u32offset_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_gather_u32offset_u32(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32offset_u32_with_svst1h_scatter_u32offset_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_u32offset_u32(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u64offset_s64_with_svst1b_scatter_u64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svst1b_scatter_u64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u64offset_s64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64offset_s64_with_svst1h_scatter_u64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svst1h_scatter_u64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_u64offset_s64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64offset_s64_with_svst1w_scatter_u64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svst1w_scatter_u64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1uw_gather_u64offset_s64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u64offset_u64_with_svst1b_scatter_u64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svst1b_scatter_u64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_gather_u64offset_u64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64offset_u64_with_svst1h_scatter_u64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svst1h_scatter_u64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_u64offset_u64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64offset_u64_with_svst1w_scatter_u64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svst1w_scatter_u64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1uw_gather_u64offset_u64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u32base_offset_s32_with_svst1b_scatter_u32base_offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32base_offset_s32_with_svst1h_scatter_u32base_offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u32base_offset_u32_with_svst1b_scatter_u32base_offset_u32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32base_offset_u32_with_svst1h_scatter_u32base_offset_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u64base_offset_s64_with_svst1b_scatter_u64base_offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64base_offset_s64_with_svst1h_scatter_u64base_offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64base_offset_s64_with_svst1w_scatter_u64base_offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u64base_offset_u64_with_svst1b_scatter_u64base_offset_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64base_offset_u64_with_svst1h_scatter_u64base_offset_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64base_offset_u64_with_svst1w_scatter_u64base_offset_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u64base_s64_with_svst1b_scatter_u64base_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_s64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u64base_s64(svptrue_b8(), bases); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64base_s64_with_svst1h_scatter_u64base_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_s64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u64base_s64(svptrue_b16(), bases); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64base_s64_with_svst1w_scatter_u64base_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_s64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_gather_u64base_s64(svptrue_b32(), bases); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u64base_u64_with_svst1b_scatter_u64base_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_u64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u64base_u64(svptrue_b8(), bases); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64base_u64_with_svst1h_scatter_u64base_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_u64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u64base_u64(svptrue_b16(), bases); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64base_u64_with_svst1w_scatter_u64base_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_u64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_gather_u64base_u64(svptrue_b32(), bases); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_s16_with_svst1b_s16() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_s16(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_s16(svptrue_b8(), storage.as_ptr() as *const u8); + let defined = svrdffr(); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_s32_with_svst1b_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_s32(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_s32(svptrue_b8(), storage.as_ptr() as *const u8); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_s32_with_svst1h_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_s32(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_s32(svptrue_b16(), storage.as_ptr() as *const u16); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_s64_with_svst1b_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_s64(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_s64(svptrue_b8(), storage.as_ptr() as *const u8); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_s64_with_svst1h_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_s64(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_s64(svptrue_b16(), storage.as_ptr() as *const u16); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_s64_with_svst1w_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1w_s64(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_s64(svptrue_b32(), storage.as_ptr() as *const u32); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_u16_with_svst1b_u16() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_u16(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_u16(svptrue_b8(), storage.as_ptr() as *const u8); + let defined = svrdffr(); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_u32_with_svst1b_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_u32(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_u32(svptrue_b8(), storage.as_ptr() as *const u8); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_u32_with_svst1h_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_u32(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1uh_u32(svptrue_b16(), storage.as_ptr() as *const u16); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_u64_with_svst1b_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_u64(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_u64(svptrue_b8(), storage.as_ptr() as *const u8); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_u64_with_svst1h_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_u64(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1uh_u64(svptrue_b16(), storage.as_ptr() as *const u16); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_u64_with_svst1w_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1w_u64(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1uw_u64(svptrue_b32(), storage.as_ptr() as *const u32); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_vnum_s16_with_svst1b_vnum_s16() { + let len = svcnth() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_s16(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_vnum_s16(svptrue_b8(), storage.as_ptr() as *const u8, 1); + let defined = svrdffr(); + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_vnum_s32_with_svst1b_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_s32(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_vnum_s32(svptrue_b8(), storage.as_ptr() as *const u8, 1); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_vnum_s32_with_svst1h_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_s32(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_vnum_s32(svptrue_b16(), storage.as_ptr() as *const u16, 1); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_vnum_s64_with_svst1b_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_s64(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_vnum_s64(svptrue_b8(), storage.as_ptr() as *const u8, 1); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_vnum_s64_with_svst1h_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_s64(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_vnum_s64(svptrue_b16(), storage.as_ptr() as *const u16, 1); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_vnum_s64_with_svst1w_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1w_vnum_s64(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_vnum_s64(svptrue_b32(), storage.as_ptr() as *const u32, 1); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_vnum_u16_with_svst1b_vnum_u16() { + let len = svcnth() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_u16(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_vnum_u16(svptrue_b8(), storage.as_ptr() as *const u8, 1); + let defined = svrdffr(); + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_vnum_u32_with_svst1b_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_u32(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_vnum_u32(svptrue_b8(), storage.as_ptr() as *const u8, 1); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_vnum_u32_with_svst1h_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_u32(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1uh_vnum_u32(svptrue_b16(), storage.as_ptr() as *const u16, 1); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_vnum_u64_with_svst1b_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_u64(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_vnum_u64(svptrue_b8(), storage.as_ptr() as *const u8, 1); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_vnum_u64_with_svst1h_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_u64(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1uh_vnum_u64(svptrue_b16(), storage.as_ptr() as *const u16, 1); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_vnum_u64_with_svst1w_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1w_vnum_u64(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1uw_vnum_u64(svptrue_b32(), storage.as_ptr() as *const u32, 1); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s32index_s32_with_svst1h_scatter_s32index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s32(0, 1); + svst1h_scatter_s32index_s32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_s32index_s32(svptrue_b16(), storage.as_ptr() as *const u16, indices); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s32index_u32_with_svst1h_scatter_s32index_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s32(0, 1); + svst1h_scatter_s32index_u32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_s32index_u32(svptrue_b16(), storage.as_ptr() as *const u16, indices); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s64index_s64_with_svst1h_scatter_s64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1h_scatter_s64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_s64index_s64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_s64index_s64_with_svst1w_scatter_s64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1w_scatter_s64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1uw_gather_s64index_s64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s64index_u64_with_svst1h_scatter_s64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1h_scatter_s64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_s64index_u64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_s64index_u64_with_svst1w_scatter_s64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1w_scatter_s64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1uw_gather_s64index_u64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32index_s32_with_svst1h_scatter_u32index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u32(0, 1); + svst1h_scatter_u32index_s32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_u32index_s32(svptrue_b16(), storage.as_ptr() as *const u16, indices); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32index_u32_with_svst1h_scatter_u32index_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u32(0, 1); + svst1h_scatter_u32index_u32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_u32index_u32(svptrue_b16(), storage.as_ptr() as *const u16, indices); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64index_s64_with_svst1h_scatter_u64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1h_scatter_u64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_u64index_s64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64index_s64_with_svst1w_scatter_u64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1w_scatter_u64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1uw_gather_u64index_s64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64index_u64_with_svst1h_scatter_u64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1h_scatter_u64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_u64index_u64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64index_u64_with_svst1w_scatter_u64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1w_scatter_u64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1uw_gather_u64index_u64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32base_index_s32_with_svst1h_scatter_u32base_index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32base_index_u32_with_svst1h_scatter_u32base_index_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64base_index_s64_with_svst1h_scatter_u64base_index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64base_index_s64_with_svst1w_scatter_u64base_index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64base_index_u64_with_svst1h_scatter_u64base_index_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64base_index_u64_with_svst1w_scatter_u64base_index_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_f32_with_svst2_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcreate2_f32( + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + ); + svst2_f32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld2_f32(svptrue_b32(), storage.as_ptr() as *const f32); + let defined = svrdffr(); + assert_vector_matches_f32( + svget2_f32::<{ 0usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + defined, + ); + assert_vector_matches_f32( + svget2_f32::<{ 1usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_f64_with_svst2_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcreate2_f64( + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + ); + svst2_f64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld2_f64(svptrue_b64(), storage.as_ptr() as *const f64); + let defined = svrdffr(); + assert_vector_matches_f64( + svget2_f64::<{ 0usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + defined, + ); + assert_vector_matches_f64( + svget2_f64::<{ 1usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_s8_with_svst2_s8() { + let mut storage = [0 as i8; 1280usize]; + let data = svcreate2_s8( + svindex_s8((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_s8((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_s8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld2_s8(svptrue_b8(), storage.as_ptr() as *const i8); + let defined = svrdffr(); + assert_vector_matches_i8( + svget2_s8::<{ 0usize as i32 }>(loaded), + svindex_s8((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i8( + svget2_s8::<{ 1usize as i32 }>(loaded), + svindex_s8((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_s16_with_svst2_s16() { + let mut storage = [0 as i16; 640usize]; + let data = svcreate2_s16( + svindex_s16((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_s16((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_s16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld2_s16(svptrue_b16(), storage.as_ptr() as *const i16); + let defined = svrdffr(); + assert_vector_matches_i16( + svget2_s16::<{ 0usize as i32 }>(loaded), + svindex_s16((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i16( + svget2_s16::<{ 1usize as i32 }>(loaded), + svindex_s16((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_s32_with_svst2_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svcreate2_s32( + svindex_s32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_s32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_s32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld2_s32(svptrue_b32(), storage.as_ptr() as *const i32); + let defined = svrdffr(); + assert_vector_matches_i32( + svget2_s32::<{ 0usize as i32 }>(loaded), + svindex_s32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i32( + svget2_s32::<{ 1usize as i32 }>(loaded), + svindex_s32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_s64_with_svst2_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svcreate2_s64( + svindex_s64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_s64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_s64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld2_s64(svptrue_b64(), storage.as_ptr() as *const i64); + let defined = svrdffr(); + assert_vector_matches_i64( + svget2_s64::<{ 0usize as i32 }>(loaded), + svindex_s64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i64( + svget2_s64::<{ 1usize as i32 }>(loaded), + svindex_s64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_u8_with_svst2_u8() { + let mut storage = [0 as u8; 1280usize]; + let data = svcreate2_u8( + svindex_u8((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_u8((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_u8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld2_u8(svptrue_b8(), storage.as_ptr() as *const u8); + let defined = svrdffr(); + assert_vector_matches_u8( + svget2_u8::<{ 0usize as i32 }>(loaded), + svindex_u8((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u8( + svget2_u8::<{ 1usize as i32 }>(loaded), + svindex_u8((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_u16_with_svst2_u16() { + let mut storage = [0 as u16; 640usize]; + let data = svcreate2_u16( + svindex_u16((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_u16((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_u16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld2_u16(svptrue_b16(), storage.as_ptr() as *const u16); + let defined = svrdffr(); + assert_vector_matches_u16( + svget2_u16::<{ 0usize as i32 }>(loaded), + svindex_u16((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u16( + svget2_u16::<{ 1usize as i32 }>(loaded), + svindex_u16((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_u32_with_svst2_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svcreate2_u32( + svindex_u32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_u32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_u32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld2_u32(svptrue_b32(), storage.as_ptr() as *const u32); + let defined = svrdffr(); + assert_vector_matches_u32( + svget2_u32::<{ 0usize as i32 }>(loaded), + svindex_u32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u32( + svget2_u32::<{ 1usize as i32 }>(loaded), + svindex_u32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_u64_with_svst2_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svcreate2_u64( + svindex_u64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_u64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_u64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld2_u64(svptrue_b64(), storage.as_ptr() as *const u64); + let defined = svrdffr(); + assert_vector_matches_u64( + svget2_u64::<{ 0usize as i32 }>(loaded), + svindex_u64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u64( + svget2_u64::<{ 1usize as i32 }>(loaded), + svindex_u64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_f32_with_svst2_vnum_f32() { + let len = svcntw() as usize; + let mut storage = [0 as f32; 320usize]; + let data = svcreate2_f32( + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + ); + svst2_vnum_f32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld2_vnum_f32(svptrue_b32(), storage.as_ptr() as *const f32, 1); + let defined = svrdffr(); + assert_vector_matches_f32( + svget2_f32::<{ 0usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + defined, + ); + assert_vector_matches_f32( + svget2_f32::<{ 1usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_f64_with_svst2_vnum_f64() { + let len = svcntd() as usize; + let mut storage = [0 as f64; 160usize]; + let data = svcreate2_f64( + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + ); + svst2_vnum_f64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld2_vnum_f64(svptrue_b64(), storage.as_ptr() as *const f64, 1); + let defined = svrdffr(); + assert_vector_matches_f64( + svget2_f64::<{ 0usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + defined, + ); + assert_vector_matches_f64( + svget2_f64::<{ 1usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_s8_with_svst2_vnum_s8() { + let len = svcntb() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svcreate2_s8( + svindex_s8( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_s8( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_s8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld2_vnum_s8(svptrue_b8(), storage.as_ptr() as *const i8, 1); + let defined = svrdffr(); + assert_vector_matches_i8( + svget2_s8::<{ 0usize as i32 }>(loaded), + svindex_s8( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i8( + svget2_s8::<{ 1usize as i32 }>(loaded), + svindex_s8( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_s16_with_svst2_vnum_s16() { + let len = svcnth() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svcreate2_s16( + svindex_s16( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_s16( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_s16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld2_vnum_s16(svptrue_b16(), storage.as_ptr() as *const i16, 1); + let defined = svrdffr(); + assert_vector_matches_i16( + svget2_s16::<{ 0usize as i32 }>(loaded), + svindex_s16( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i16( + svget2_s16::<{ 1usize as i32 }>(loaded), + svindex_s16( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_s32_with_svst2_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i32; 320usize]; + let data = svcreate2_s32( + svindex_s32( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_s32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld2_vnum_s32(svptrue_b32(), storage.as_ptr() as *const i32, 1); + let defined = svrdffr(); + assert_vector_matches_i32( + svget2_s32::<{ 0usize as i32 }>(loaded), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i32( + svget2_s32::<{ 1usize as i32 }>(loaded), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_s64_with_svst2_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i64; 160usize]; + let data = svcreate2_s64( + svindex_s64( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_s64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld2_vnum_s64(svptrue_b64(), storage.as_ptr() as *const i64, 1); + let defined = svrdffr(); + assert_vector_matches_i64( + svget2_s64::<{ 0usize as i32 }>(loaded), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i64( + svget2_s64::<{ 1usize as i32 }>(loaded), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_u8_with_svst2_vnum_u8() { + let len = svcntb() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svcreate2_u8( + svindex_u8( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_u8( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_u8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld2_vnum_u8(svptrue_b8(), storage.as_ptr() as *const u8, 1); + let defined = svrdffr(); + assert_vector_matches_u8( + svget2_u8::<{ 0usize as i32 }>(loaded), + svindex_u8( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u8( + svget2_u8::<{ 1usize as i32 }>(loaded), + svindex_u8( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_u16_with_svst2_vnum_u16() { + let len = svcnth() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svcreate2_u16( + svindex_u16( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_u16( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_u16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld2_vnum_u16(svptrue_b16(), storage.as_ptr() as *const u16, 1); + let defined = svrdffr(); + assert_vector_matches_u16( + svget2_u16::<{ 0usize as i32 }>(loaded), + svindex_u16( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u16( + svget2_u16::<{ 1usize as i32 }>(loaded), + svindex_u16( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_u32_with_svst2_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u32; 320usize]; + let data = svcreate2_u32( + svindex_u32( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_u32( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_u32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld2_vnum_u32(svptrue_b32(), storage.as_ptr() as *const u32, 1); + let defined = svrdffr(); + assert_vector_matches_u32( + svget2_u32::<{ 0usize as i32 }>(loaded), + svindex_u32( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u32( + svget2_u32::<{ 1usize as i32 }>(loaded), + svindex_u32( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_u64_with_svst2_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u64; 160usize]; + let data = svcreate2_u64( + svindex_u64( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_u64( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_u64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld2_vnum_u64(svptrue_b64(), storage.as_ptr() as *const u64, 1); + let defined = svrdffr(); + assert_vector_matches_u64( + svget2_u64::<{ 0usize as i32 }>(loaded), + svindex_u64( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u64( + svget2_u64::<{ 1usize as i32 }>(loaded), + svindex_u64( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_f32_with_svst3_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcreate3_f32( + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + ); + svst3_f32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld3_f32(svptrue_b32(), storage.as_ptr() as *const f32); + let defined = svrdffr(); + assert_vector_matches_f32( + svget3_f32::<{ 0usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + defined, + ); + assert_vector_matches_f32( + svget3_f32::<{ 1usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + defined, + ); + assert_vector_matches_f32( + svget3_f32::<{ 2usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_f64_with_svst3_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcreate3_f64( + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + ); + svst3_f64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld3_f64(svptrue_b64(), storage.as_ptr() as *const f64); + let defined = svrdffr(); + assert_vector_matches_f64( + svget3_f64::<{ 0usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + defined, + ); + assert_vector_matches_f64( + svget3_f64::<{ 1usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + defined, + ); + assert_vector_matches_f64( + svget3_f64::<{ 2usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_s8_with_svst3_s8() { + let mut storage = [0 as i8; 1280usize]; + let data = svcreate3_s8( + svindex_s8((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s8((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s8((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_s8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld3_s8(svptrue_b8(), storage.as_ptr() as *const i8); + let defined = svrdffr(); + assert_vector_matches_i8( + svget3_s8::<{ 0usize as i32 }>(loaded), + svindex_s8((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i8( + svget3_s8::<{ 1usize as i32 }>(loaded), + svindex_s8((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i8( + svget3_s8::<{ 2usize as i32 }>(loaded), + svindex_s8((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_s16_with_svst3_s16() { + let mut storage = [0 as i16; 640usize]; + let data = svcreate3_s16( + svindex_s16((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s16((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s16((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_s16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld3_s16(svptrue_b16(), storage.as_ptr() as *const i16); + let defined = svrdffr(); + assert_vector_matches_i16( + svget3_s16::<{ 0usize as i32 }>(loaded), + svindex_s16((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i16( + svget3_s16::<{ 1usize as i32 }>(loaded), + svindex_s16((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i16( + svget3_s16::<{ 2usize as i32 }>(loaded), + svindex_s16((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_s32_with_svst3_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svcreate3_s32( + svindex_s32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_s32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld3_s32(svptrue_b32(), storage.as_ptr() as *const i32); + let defined = svrdffr(); + assert_vector_matches_i32( + svget3_s32::<{ 0usize as i32 }>(loaded), + svindex_s32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i32( + svget3_s32::<{ 1usize as i32 }>(loaded), + svindex_s32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i32( + svget3_s32::<{ 2usize as i32 }>(loaded), + svindex_s32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_s64_with_svst3_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svcreate3_s64( + svindex_s64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_s64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld3_s64(svptrue_b64(), storage.as_ptr() as *const i64); + let defined = svrdffr(); + assert_vector_matches_i64( + svget3_s64::<{ 0usize as i32 }>(loaded), + svindex_s64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i64( + svget3_s64::<{ 1usize as i32 }>(loaded), + svindex_s64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i64( + svget3_s64::<{ 2usize as i32 }>(loaded), + svindex_s64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_u8_with_svst3_u8() { + let mut storage = [0 as u8; 1280usize]; + let data = svcreate3_u8( + svindex_u8((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u8((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u8((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_u8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld3_u8(svptrue_b8(), storage.as_ptr() as *const u8); + let defined = svrdffr(); + assert_vector_matches_u8( + svget3_u8::<{ 0usize as i32 }>(loaded), + svindex_u8((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u8( + svget3_u8::<{ 1usize as i32 }>(loaded), + svindex_u8((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u8( + svget3_u8::<{ 2usize as i32 }>(loaded), + svindex_u8((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_u16_with_svst3_u16() { + let mut storage = [0 as u16; 640usize]; + let data = svcreate3_u16( + svindex_u16((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u16((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u16((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_u16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld3_u16(svptrue_b16(), storage.as_ptr() as *const u16); + let defined = svrdffr(); + assert_vector_matches_u16( + svget3_u16::<{ 0usize as i32 }>(loaded), + svindex_u16((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u16( + svget3_u16::<{ 1usize as i32 }>(loaded), + svindex_u16((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u16( + svget3_u16::<{ 2usize as i32 }>(loaded), + svindex_u16((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_u32_with_svst3_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svcreate3_u32( + svindex_u32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_u32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld3_u32(svptrue_b32(), storage.as_ptr() as *const u32); + let defined = svrdffr(); + assert_vector_matches_u32( + svget3_u32::<{ 0usize as i32 }>(loaded), + svindex_u32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u32( + svget3_u32::<{ 1usize as i32 }>(loaded), + svindex_u32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u32( + svget3_u32::<{ 2usize as i32 }>(loaded), + svindex_u32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_u64_with_svst3_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svcreate3_u64( + svindex_u64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_u64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld3_u64(svptrue_b64(), storage.as_ptr() as *const u64); + let defined = svrdffr(); + assert_vector_matches_u64( + svget3_u64::<{ 0usize as i32 }>(loaded), + svindex_u64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u64( + svget3_u64::<{ 1usize as i32 }>(loaded), + svindex_u64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u64( + svget3_u64::<{ 2usize as i32 }>(loaded), + svindex_u64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_f32_with_svst3_vnum_f32() { + let len = svcntw() as usize; + let mut storage = [0 as f32; 320usize]; + let data = svcreate3_f32( + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + ); + svst3_vnum_f32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld3_vnum_f32(svptrue_b32(), storage.as_ptr() as *const f32, 1); + let defined = svrdffr(); + assert_vector_matches_f32( + svget3_f32::<{ 0usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + defined, + ); + assert_vector_matches_f32( + svget3_f32::<{ 1usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + defined, + ); + assert_vector_matches_f32( + svget3_f32::<{ 2usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_f64_with_svst3_vnum_f64() { + let len = svcntd() as usize; + let mut storage = [0 as f64; 160usize]; + let data = svcreate3_f64( + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + ); + svst3_vnum_f64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld3_vnum_f64(svptrue_b64(), storage.as_ptr() as *const f64, 1); + let defined = svrdffr(); + assert_vector_matches_f64( + svget3_f64::<{ 0usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + defined, + ); + assert_vector_matches_f64( + svget3_f64::<{ 1usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + defined, + ); + assert_vector_matches_f64( + svget3_f64::<{ 2usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_s8_with_svst3_vnum_s8() { + let len = svcntb() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svcreate3_s8( + svindex_s8( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s8( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s8( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_s8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld3_vnum_s8(svptrue_b8(), storage.as_ptr() as *const i8, 1); + let defined = svrdffr(); + assert_vector_matches_i8( + svget3_s8::<{ 0usize as i32 }>(loaded), + svindex_s8( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i8( + svget3_s8::<{ 1usize as i32 }>(loaded), + svindex_s8( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i8( + svget3_s8::<{ 2usize as i32 }>(loaded), + svindex_s8( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_s16_with_svst3_vnum_s16() { + let len = svcnth() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svcreate3_s16( + svindex_s16( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s16( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s16( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_s16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld3_vnum_s16(svptrue_b16(), storage.as_ptr() as *const i16, 1); + let defined = svrdffr(); + assert_vector_matches_i16( + svget3_s16::<{ 0usize as i32 }>(loaded), + svindex_s16( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i16( + svget3_s16::<{ 1usize as i32 }>(loaded), + svindex_s16( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i16( + svget3_s16::<{ 2usize as i32 }>(loaded), + svindex_s16( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_s32_with_svst3_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i32; 320usize]; + let data = svcreate3_s32( + svindex_s32( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_s32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld3_vnum_s32(svptrue_b32(), storage.as_ptr() as *const i32, 1); + let defined = svrdffr(); + assert_vector_matches_i32( + svget3_s32::<{ 0usize as i32 }>(loaded), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i32( + svget3_s32::<{ 1usize as i32 }>(loaded), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i32( + svget3_s32::<{ 2usize as i32 }>(loaded), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_s64_with_svst3_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i64; 160usize]; + let data = svcreate3_s64( + svindex_s64( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_s64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld3_vnum_s64(svptrue_b64(), storage.as_ptr() as *const i64, 1); + let defined = svrdffr(); + assert_vector_matches_i64( + svget3_s64::<{ 0usize as i32 }>(loaded), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i64( + svget3_s64::<{ 1usize as i32 }>(loaded), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i64( + svget3_s64::<{ 2usize as i32 }>(loaded), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_u8_with_svst3_vnum_u8() { + let len = svcntb() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svcreate3_u8( + svindex_u8( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u8( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u8( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_u8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld3_vnum_u8(svptrue_b8(), storage.as_ptr() as *const u8, 1); + let defined = svrdffr(); + assert_vector_matches_u8( + svget3_u8::<{ 0usize as i32 }>(loaded), + svindex_u8( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u8( + svget3_u8::<{ 1usize as i32 }>(loaded), + svindex_u8( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u8( + svget3_u8::<{ 2usize as i32 }>(loaded), + svindex_u8( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_u16_with_svst3_vnum_u16() { + let len = svcnth() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svcreate3_u16( + svindex_u16( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u16( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u16( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_u16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld3_vnum_u16(svptrue_b16(), storage.as_ptr() as *const u16, 1); + let defined = svrdffr(); + assert_vector_matches_u16( + svget3_u16::<{ 0usize as i32 }>(loaded), + svindex_u16( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u16( + svget3_u16::<{ 1usize as i32 }>(loaded), + svindex_u16( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u16( + svget3_u16::<{ 2usize as i32 }>(loaded), + svindex_u16( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_u32_with_svst3_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u32; 320usize]; + let data = svcreate3_u32( + svindex_u32( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u32( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u32( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_u32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld3_vnum_u32(svptrue_b32(), storage.as_ptr() as *const u32, 1); + let defined = svrdffr(); + assert_vector_matches_u32( + svget3_u32::<{ 0usize as i32 }>(loaded), + svindex_u32( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u32( + svget3_u32::<{ 1usize as i32 }>(loaded), + svindex_u32( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u32( + svget3_u32::<{ 2usize as i32 }>(loaded), + svindex_u32( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_u64_with_svst3_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u64; 160usize]; + let data = svcreate3_u64( + svindex_u64( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u64( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u64( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_u64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld3_vnum_u64(svptrue_b64(), storage.as_ptr() as *const u64, 1); + let defined = svrdffr(); + assert_vector_matches_u64( + svget3_u64::<{ 0usize as i32 }>(loaded), + svindex_u64( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u64( + svget3_u64::<{ 1usize as i32 }>(loaded), + svindex_u64( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u64( + svget3_u64::<{ 2usize as i32 }>(loaded), + svindex_u64( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_f32_with_svst4_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcreate4_f32( + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + ); + svst4_f32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld4_f32(svptrue_b32(), storage.as_ptr() as *const f32); + let defined = svrdffr(); + assert_vector_matches_f32( + svget4_f32::<{ 0usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + defined, + ); + assert_vector_matches_f32( + svget4_f32::<{ 1usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + defined, + ); + assert_vector_matches_f32( + svget4_f32::<{ 2usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + defined, + ); + assert_vector_matches_f32( + svget4_f32::<{ 3usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_f64_with_svst4_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcreate4_f64( + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + ); + svst4_f64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld4_f64(svptrue_b64(), storage.as_ptr() as *const f64); + let defined = svrdffr(); + assert_vector_matches_f64( + svget4_f64::<{ 0usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + defined, + ); + assert_vector_matches_f64( + svget4_f64::<{ 1usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + defined, + ); + assert_vector_matches_f64( + svget4_f64::<{ 2usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + defined, + ); + assert_vector_matches_f64( + svget4_f64::<{ 3usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_s8_with_svst4_s8() { + let mut storage = [0 as i8; 1280usize]; + let data = svcreate4_s8( + svindex_s8((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s8((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s8((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s8((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_s8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld4_s8(svptrue_b8(), storage.as_ptr() as *const i8); + let defined = svrdffr(); + assert_vector_matches_i8( + svget4_s8::<{ 0usize as i32 }>(loaded), + svindex_s8((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i8( + svget4_s8::<{ 1usize as i32 }>(loaded), + svindex_s8((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i8( + svget4_s8::<{ 2usize as i32 }>(loaded), + svindex_s8((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i8( + svget4_s8::<{ 3usize as i32 }>(loaded), + svindex_s8((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_s16_with_svst4_s16() { + let mut storage = [0 as i16; 640usize]; + let data = svcreate4_s16( + svindex_s16((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s16((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s16((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s16((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_s16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld4_s16(svptrue_b16(), storage.as_ptr() as *const i16); + let defined = svrdffr(); + assert_vector_matches_i16( + svget4_s16::<{ 0usize as i32 }>(loaded), + svindex_s16((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i16( + svget4_s16::<{ 1usize as i32 }>(loaded), + svindex_s16((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i16( + svget4_s16::<{ 2usize as i32 }>(loaded), + svindex_s16((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i16( + svget4_s16::<{ 3usize as i32 }>(loaded), + svindex_s16((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_s32_with_svst4_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svcreate4_s32( + svindex_s32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_s32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld4_s32(svptrue_b32(), storage.as_ptr() as *const i32); + let defined = svrdffr(); + assert_vector_matches_i32( + svget4_s32::<{ 0usize as i32 }>(loaded), + svindex_s32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i32( + svget4_s32::<{ 1usize as i32 }>(loaded), + svindex_s32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i32( + svget4_s32::<{ 2usize as i32 }>(loaded), + svindex_s32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i32( + svget4_s32::<{ 3usize as i32 }>(loaded), + svindex_s32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_s64_with_svst4_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svcreate4_s64( + svindex_s64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_s64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld4_s64(svptrue_b64(), storage.as_ptr() as *const i64); + let defined = svrdffr(); + assert_vector_matches_i64( + svget4_s64::<{ 0usize as i32 }>(loaded), + svindex_s64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i64( + svget4_s64::<{ 1usize as i32 }>(loaded), + svindex_s64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i64( + svget4_s64::<{ 2usize as i32 }>(loaded), + svindex_s64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_i64( + svget4_s64::<{ 3usize as i32 }>(loaded), + svindex_s64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_u8_with_svst4_u8() { + let mut storage = [0 as u8; 1280usize]; + let data = svcreate4_u8( + svindex_u8((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u8((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u8((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u8((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_u8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld4_u8(svptrue_b8(), storage.as_ptr() as *const u8); + let defined = svrdffr(); + assert_vector_matches_u8( + svget4_u8::<{ 0usize as i32 }>(loaded), + svindex_u8((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u8( + svget4_u8::<{ 1usize as i32 }>(loaded), + svindex_u8((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u8( + svget4_u8::<{ 2usize as i32 }>(loaded), + svindex_u8((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u8( + svget4_u8::<{ 3usize as i32 }>(loaded), + svindex_u8((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_u16_with_svst4_u16() { + let mut storage = [0 as u16; 640usize]; + let data = svcreate4_u16( + svindex_u16((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u16((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u16((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u16((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_u16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld4_u16(svptrue_b16(), storage.as_ptr() as *const u16); + let defined = svrdffr(); + assert_vector_matches_u16( + svget4_u16::<{ 0usize as i32 }>(loaded), + svindex_u16((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u16( + svget4_u16::<{ 1usize as i32 }>(loaded), + svindex_u16((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u16( + svget4_u16::<{ 2usize as i32 }>(loaded), + svindex_u16((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u16( + svget4_u16::<{ 3usize as i32 }>(loaded), + svindex_u16((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_u32_with_svst4_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svcreate4_u32( + svindex_u32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_u32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld4_u32(svptrue_b32(), storage.as_ptr() as *const u32); + let defined = svrdffr(); + assert_vector_matches_u32( + svget4_u32::<{ 0usize as i32 }>(loaded), + svindex_u32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u32( + svget4_u32::<{ 1usize as i32 }>(loaded), + svindex_u32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u32( + svget4_u32::<{ 2usize as i32 }>(loaded), + svindex_u32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u32( + svget4_u32::<{ 3usize as i32 }>(loaded), + svindex_u32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_u64_with_svst4_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svcreate4_u64( + svindex_u64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_u64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld4_u64(svptrue_b64(), storage.as_ptr() as *const u64); + let defined = svrdffr(); + assert_vector_matches_u64( + svget4_u64::<{ 0usize as i32 }>(loaded), + svindex_u64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u64( + svget4_u64::<{ 1usize as i32 }>(loaded), + svindex_u64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u64( + svget4_u64::<{ 2usize as i32 }>(loaded), + svindex_u64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); + assert_vector_matches_u64( + svget4_u64::<{ 3usize as i32 }>(loaded), + svindex_u64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_f32_with_svst4_vnum_f32() { + let len = svcntw() as usize; + let mut storage = [0 as f32; 320usize]; + let data = svcreate4_f32( + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + ); + svst4_vnum_f32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld4_vnum_f32(svptrue_b32(), storage.as_ptr() as *const f32, 1); + let defined = svrdffr(); + assert_vector_matches_f32( + svget4_f32::<{ 0usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + defined, + ); + assert_vector_matches_f32( + svget4_f32::<{ 1usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + defined, + ); + assert_vector_matches_f32( + svget4_f32::<{ 2usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + defined, + ); + assert_vector_matches_f32( + svget4_f32::<{ 3usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_f64_with_svst4_vnum_f64() { + let len = svcntd() as usize; + let mut storage = [0 as f64; 160usize]; + let data = svcreate4_f64( + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + ); + svst4_vnum_f64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld4_vnum_f64(svptrue_b64(), storage.as_ptr() as *const f64, 1); + let defined = svrdffr(); + assert_vector_matches_f64( + svget4_f64::<{ 0usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + defined, + ); + assert_vector_matches_f64( + svget4_f64::<{ 1usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + defined, + ); + assert_vector_matches_f64( + svget4_f64::<{ 2usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + defined, + ); + assert_vector_matches_f64( + svget4_f64::<{ 3usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_s8_with_svst4_vnum_s8() { + let len = svcntb() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svcreate4_s8( + svindex_s8( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s8( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s8( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s8( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_s8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld4_vnum_s8(svptrue_b8(), storage.as_ptr() as *const i8, 1); + let defined = svrdffr(); + assert_vector_matches_i8( + svget4_s8::<{ 0usize as i32 }>(loaded), + svindex_s8( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i8( + svget4_s8::<{ 1usize as i32 }>(loaded), + svindex_s8( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i8( + svget4_s8::<{ 2usize as i32 }>(loaded), + svindex_s8( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i8( + svget4_s8::<{ 3usize as i32 }>(loaded), + svindex_s8( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_s16_with_svst4_vnum_s16() { + let len = svcnth() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svcreate4_s16( + svindex_s16( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s16( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s16( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s16( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_s16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld4_vnum_s16(svptrue_b16(), storage.as_ptr() as *const i16, 1); + let defined = svrdffr(); + assert_vector_matches_i16( + svget4_s16::<{ 0usize as i32 }>(loaded), + svindex_s16( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i16( + svget4_s16::<{ 1usize as i32 }>(loaded), + svindex_s16( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i16( + svget4_s16::<{ 2usize as i32 }>(loaded), + svindex_s16( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i16( + svget4_s16::<{ 3usize as i32 }>(loaded), + svindex_s16( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_s32_with_svst4_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i32; 320usize]; + let data = svcreate4_s32( + svindex_s32( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s32( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_s32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld4_vnum_s32(svptrue_b32(), storage.as_ptr() as *const i32, 1); + let defined = svrdffr(); + assert_vector_matches_i32( + svget4_s32::<{ 0usize as i32 }>(loaded), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i32( + svget4_s32::<{ 1usize as i32 }>(loaded), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i32( + svget4_s32::<{ 2usize as i32 }>(loaded), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i32( + svget4_s32::<{ 3usize as i32 }>(loaded), + svindex_s32( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_s64_with_svst4_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i64; 160usize]; + let data = svcreate4_s64( + svindex_s64( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s64( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_s64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld4_vnum_s64(svptrue_b64(), storage.as_ptr() as *const i64, 1); + let defined = svrdffr(); + assert_vector_matches_i64( + svget4_s64::<{ 0usize as i32 }>(loaded), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i64( + svget4_s64::<{ 1usize as i32 }>(loaded), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i64( + svget4_s64::<{ 2usize as i32 }>(loaded), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_i64( + svget4_s64::<{ 3usize as i32 }>(loaded), + svindex_s64( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_u8_with_svst4_vnum_u8() { + let len = svcntb() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svcreate4_u8( + svindex_u8( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u8( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u8( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u8( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_u8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld4_vnum_u8(svptrue_b8(), storage.as_ptr() as *const u8, 1); + let defined = svrdffr(); + assert_vector_matches_u8( + svget4_u8::<{ 0usize as i32 }>(loaded), + svindex_u8( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u8( + svget4_u8::<{ 1usize as i32 }>(loaded), + svindex_u8( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u8( + svget4_u8::<{ 2usize as i32 }>(loaded), + svindex_u8( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u8( + svget4_u8::<{ 3usize as i32 }>(loaded), + svindex_u8( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_u16_with_svst4_vnum_u16() { + let len = svcnth() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svcreate4_u16( + svindex_u16( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u16( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u16( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u16( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_u16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld4_vnum_u16(svptrue_b16(), storage.as_ptr() as *const u16, 1); + let defined = svrdffr(); + assert_vector_matches_u16( + svget4_u16::<{ 0usize as i32 }>(loaded), + svindex_u16( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u16( + svget4_u16::<{ 1usize as i32 }>(loaded), + svindex_u16( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u16( + svget4_u16::<{ 2usize as i32 }>(loaded), + svindex_u16( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u16( + svget4_u16::<{ 3usize as i32 }>(loaded), + svindex_u16( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_u32_with_svst4_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u32; 320usize]; + let data = svcreate4_u32( + svindex_u32( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u32( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u32( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u32( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_u32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld4_vnum_u32(svptrue_b32(), storage.as_ptr() as *const u32, 1); + let defined = svrdffr(); + assert_vector_matches_u32( + svget4_u32::<{ 0usize as i32 }>(loaded), + svindex_u32( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u32( + svget4_u32::<{ 1usize as i32 }>(loaded), + svindex_u32( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u32( + svget4_u32::<{ 2usize as i32 }>(loaded), + svindex_u32( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u32( + svget4_u32::<{ 3usize as i32 }>(loaded), + svindex_u32( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_u64_with_svst4_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u64; 160usize]; + let data = svcreate4_u64( + svindex_u64( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u64( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u64( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u64( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_u64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld4_vnum_u64(svptrue_b64(), storage.as_ptr() as *const u64, 1); + let defined = svrdffr(); + assert_vector_matches_u64( + svget4_u64::<{ 0usize as i32 }>(loaded), + svindex_u64( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u64( + svget4_u64::<{ 1usize as i32 }>(loaded), + svindex_u64( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u64( + svget4_u64::<{ 2usize as i32 }>(loaded), + svindex_u64( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); + assert_vector_matches_u64( + svget4_u64::<{ 3usize as i32 }>(loaded), + svindex_u64( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_f32() { + let ptr = F32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_f32(svptrue_b32(), ptr); + let loaded = svldff1_f32(svptrue_b32(), ptr); + let defined = svrdffr(); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_f64() { + let ptr = F64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_f64(svptrue_b64(), ptr); + let loaded = svldff1_f64(svptrue_b64(), ptr); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_s8() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1_s8(svptrue_b8(), ptr); + let loaded = svldff1_s8(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_i8( + loaded, + svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_s16() { + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1_s16(svptrue_b16(), ptr); + let loaded = svldff1_s16(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_s32() { + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_s32(svptrue_b32(), ptr); + let loaded = svldff1_s32(svptrue_b32(), ptr); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_s64() { + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_s64(svptrue_b64(), ptr); + let loaded = svldff1_s64(svptrue_b64(), ptr); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_u8() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1_u8(svptrue_b8(), ptr); + let loaded = svldff1_u8(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_u8( + loaded, + svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_u16() { + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1_u16(svptrue_b16(), ptr); + let loaded = svldff1_u16(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_u32() { + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_u32(svptrue_b32(), ptr); + let loaded = svldff1_u32(svptrue_b32(), ptr); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_u64() { + let ptr = U64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_u64(svptrue_b64(), ptr); + let loaded = svldff1_u64(svptrue_b64(), ptr); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s32index_f32() { + let indices = svindex_s32(0, 1); + let ptr = F32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_s32index_f32(svptrue_b32(), ptr, indices); + let loaded = svldff1_gather_s32index_f32(svptrue_b32(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s32index_s32() { + let indices = svindex_s32(0, 1); + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_s32index_s32(svptrue_b32(), ptr, indices); + let loaded = svldff1_gather_s32index_s32(svptrue_b32(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s32index_u32() { + let indices = svindex_s32(0, 1); + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_s32index_u32(svptrue_b32(), ptr, indices); + let loaded = svldff1_gather_s32index_u32(svptrue_b32(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s64index_f64() { + let indices = svindex_s64(0, 1); + let ptr = F64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_s64index_f64(svptrue_b64(), ptr, indices); + let loaded = svldff1_gather_s64index_f64(svptrue_b64(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s64index_s64() { + let indices = svindex_s64(0, 1); + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_s64index_s64(svptrue_b64(), ptr, indices); + let loaded = svldff1_gather_s64index_s64(svptrue_b64(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s64index_u64() { + let indices = svindex_s64(0, 1); + let ptr = U64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_s64index_u64(svptrue_b64(), ptr, indices); + let loaded = svldff1_gather_s64index_u64(svptrue_b64(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32index_f32() { + let indices = svindex_u32(0, 1); + let ptr = F32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_u32index_f32(svptrue_b32(), ptr, indices); + let loaded = svldff1_gather_u32index_f32(svptrue_b32(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32index_s32() { + let indices = svindex_u32(0, 1); + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_u32index_s32(svptrue_b32(), ptr, indices); + let loaded = svldff1_gather_u32index_s32(svptrue_b32(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32index_u32() { + let indices = svindex_u32(0, 1); + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_u32index_u32(svptrue_b32(), ptr, indices); + let loaded = svldff1_gather_u32index_u32(svptrue_b32(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64index_f64() { + let indices = svindex_u64(0, 1); + let ptr = F64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_u64index_f64(svptrue_b64(), ptr, indices); + let loaded = svldff1_gather_u64index_f64(svptrue_b64(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64index_s64() { + let indices = svindex_u64(0, 1); + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_u64index_s64(svptrue_b64(), ptr, indices); + let loaded = svldff1_gather_u64index_s64(svptrue_b64(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64index_u64() { + let indices = svindex_u64(0, 1); + let ptr = U64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_u64index_u64(svptrue_b64(), ptr, indices); + let loaded = svldff1_gather_u64index_u64(svptrue_b64(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s32offset_f32() { + let offsets = svindex_s32(0, 4u32.try_into().unwrap()); + let ptr = F32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_s32offset_f32(svptrue_b32(), ptr, offsets); + let loaded = svldff1_gather_s32offset_f32(svptrue_b32(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s32offset_s32() { + let offsets = svindex_s32(0, 4u32.try_into().unwrap()); + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_s32offset_s32(svptrue_b32(), ptr, offsets); + let loaded = svldff1_gather_s32offset_s32(svptrue_b32(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s32offset_u32() { + let offsets = svindex_s32(0, 4u32.try_into().unwrap()); + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_s32offset_u32(svptrue_b32(), ptr, offsets); + let loaded = svldff1_gather_s32offset_u32(svptrue_b32(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s64offset_f64() { + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + let ptr = F64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_s64offset_f64(svptrue_b64(), ptr, offsets); + let loaded = svldff1_gather_s64offset_f64(svptrue_b64(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s64offset_s64() { + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_s64offset_s64(svptrue_b64(), ptr, offsets); + let loaded = svldff1_gather_s64offset_s64(svptrue_b64(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s64offset_u64() { + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + let ptr = U64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_s64offset_u64(svptrue_b64(), ptr, offsets); + let loaded = svldff1_gather_s64offset_u64(svptrue_b64(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32offset_f32() { + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + let ptr = F32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_u32offset_f32(svptrue_b32(), ptr, offsets); + let loaded = svldff1_gather_u32offset_f32(svptrue_b32(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32offset_s32() { + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_u32offset_s32(svptrue_b32(), ptr, offsets); + let loaded = svldff1_gather_u32offset_s32(svptrue_b32(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32offset_u32() { + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_u32offset_u32(svptrue_b32(), ptr, offsets); + let loaded = svldff1_gather_u32offset_u32(svptrue_b32(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64offset_f64() { + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let ptr = F64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_u64offset_f64(svptrue_b64(), ptr, offsets); + let loaded = svldff1_gather_u64offset_f64(svptrue_b64(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64offset_s64() { + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_u64offset_s64(svptrue_b64(), ptr, offsets); + let loaded = svldff1_gather_u64offset_s64(svptrue_b64(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64offset_u64() { + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let ptr = U64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_gather_u64offset_u64(svptrue_b64(), ptr, offsets); + let loaded = svldff1_gather_u64offset_u64(svptrue_b64(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64base_f64() { + let bases = svdup_n_u64(F64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let _ = svld1_gather_u64base_f64(svptrue_b64(), bases); + let loaded = svldff1_gather_u64base_f64(svptrue_b64(), bases); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64base_s64() { + let bases = svdup_n_u64(I64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let _ = svld1_gather_u64base_s64(svptrue_b64(), bases); + let loaded = svldff1_gather_u64base_s64(svptrue_b64(), bases); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64base_u64() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let _ = svld1_gather_u64base_u64(svptrue_b64(), bases); + let loaded = svldff1_gather_u64base_u64(svptrue_b64(), bases); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32base_index_f32() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_u32base_index_f32( + svptrue_b32(), + bases, + F32_DATA.as_ptr() as i64 / (4u32 as i64) + 1, + ); + let loaded = svldff1_gather_u32base_index_f32( + svptrue_b32(), + bases, + F32_DATA.as_ptr() as i64 / (4u32 as i64) + 1, + ); + let defined = svrdffr(); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32base_index_s32() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_u32base_index_s32( + svptrue_b32(), + bases, + I32_DATA.as_ptr() as i64 / (4u32 as i64) + 1, + ); + let loaded = svldff1_gather_u32base_index_s32( + svptrue_b32(), + bases, + I32_DATA.as_ptr() as i64 / (4u32 as i64) + 1, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32base_index_u32() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_u32base_index_u32( + svptrue_b32(), + bases, + U32_DATA.as_ptr() as i64 / (4u32 as i64) + 1, + ); + let loaded = svldff1_gather_u32base_index_u32( + svptrue_b32(), + bases, + U32_DATA.as_ptr() as i64 / (4u32 as i64) + 1, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64base_index_f64() { + let bases = svdup_n_u64(F64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let _ = svld1_gather_u64base_index_f64(svptrue_b64(), bases, 1.try_into().unwrap()); + let loaded = svldff1_gather_u64base_index_f64(svptrue_b64(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64base_index_s64() { + let bases = svdup_n_u64(I64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let _ = svld1_gather_u64base_index_s64(svptrue_b64(), bases, 1.try_into().unwrap()); + let loaded = svldff1_gather_u64base_index_s64(svptrue_b64(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64base_index_u64() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let _ = svld1_gather_u64base_index_u64(svptrue_b64(), bases, 1.try_into().unwrap()); + let loaded = svldff1_gather_u64base_index_u64(svptrue_b64(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32base_offset_f32() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_u32base_offset_f32( + svptrue_b32(), + bases, + F32_DATA.as_ptr() as i64 + 4u32 as i64, + ); + let loaded = svldff1_gather_u32base_offset_f32( + svptrue_b32(), + bases, + F32_DATA.as_ptr() as i64 + 4u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32base_offset_s32() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_u32base_offset_s32( + svptrue_b32(), + bases, + I32_DATA.as_ptr() as i64 + 4u32 as i64, + ); + let loaded = svldff1_gather_u32base_offset_s32( + svptrue_b32(), + bases, + I32_DATA.as_ptr() as i64 + 4u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32base_offset_u32() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_u32base_offset_u32( + svptrue_b32(), + bases, + U32_DATA.as_ptr() as i64 + 4u32 as i64, + ); + let loaded = svldff1_gather_u32base_offset_u32( + svptrue_b32(), + bases, + U32_DATA.as_ptr() as i64 + 4u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64base_offset_f64() { + let bases = svdup_n_u64(F64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let _ = svld1_gather_u64base_offset_f64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + let loaded = svldff1_gather_u64base_offset_f64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64base_offset_s64() { + let bases = svdup_n_u64(I64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let _ = svld1_gather_u64base_offset_s64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + let loaded = svldff1_gather_u64base_offset_s64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64base_offset_u64() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let _ = svld1_gather_u64base_offset_u64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + let loaded = svldff1_gather_u64base_offset_u64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_f32() { + let ptr = F32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_vnum_f32(svptrue_b32(), ptr, 1); + let loaded = svldff1_vnum_f32(svptrue_b32(), ptr, 1); + let defined = svrdffr(); + let len = svcntw() as usize; + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_f64() { + let ptr = F64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_vnum_f64(svptrue_b64(), ptr, 1); + let loaded = svldff1_vnum_f64(svptrue_b64(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_s8() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1_vnum_s8(svptrue_b8(), ptr, 1); + let loaded = svldff1_vnum_s8(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcntb() as usize; + assert_vector_matches_i8( + loaded, + svindex_s8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_s16() { + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1_vnum_s16(svptrue_b16(), ptr, 1); + let loaded = svldff1_vnum_s16(svptrue_b16(), ptr, 1); + let defined = svrdffr(); + let len = svcnth() as usize; + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_s32() { + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_vnum_s32(svptrue_b32(), ptr, 1); + let loaded = svldff1_vnum_s32(svptrue_b32(), ptr, 1); + let defined = svrdffr(); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_s64() { + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_vnum_s64(svptrue_b64(), ptr, 1); + let loaded = svldff1_vnum_s64(svptrue_b64(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_u8() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1_vnum_u8(svptrue_b8(), ptr, 1); + let loaded = svldff1_vnum_u8(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcntb() as usize; + assert_vector_matches_u8( + loaded, + svindex_u8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_u16() { + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1_vnum_u16(svptrue_b16(), ptr, 1); + let loaded = svldff1_vnum_u16(svptrue_b16(), ptr, 1); + let defined = svrdffr(); + let len = svcnth() as usize; + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_u32() { + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_vnum_u32(svptrue_b32(), ptr, 1); + let loaded = svldff1_vnum_u32(svptrue_b32(), ptr, 1); + let defined = svrdffr(); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_u64() { + let ptr = U64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_vnum_u64(svptrue_b64(), ptr, 1); + let loaded = svldff1_vnum_u64(svptrue_b64(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_s32offset_s32() { + let offsets = svindex_s32(0, 1u32.try_into().unwrap()); + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_gather_s32offset_s32(svptrue_b8(), ptr, offsets); + let loaded = svldff1sb_gather_s32offset_s32(svptrue_b8(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_s32offset_s32() { + let offsets = svindex_s32(0, 2u32.try_into().unwrap()); + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_gather_s32offset_s32(svptrue_b16(), ptr, offsets); + let loaded = svldff1sh_gather_s32offset_s32(svptrue_b16(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_s32offset_u32() { + let offsets = svindex_s32(0, 1u32.try_into().unwrap()); + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_gather_s32offset_u32(svptrue_b8(), ptr, offsets); + let loaded = svldff1sb_gather_s32offset_u32(svptrue_b8(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_s32offset_u32() { + let offsets = svindex_s32(0, 2u32.try_into().unwrap()); + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_gather_s32offset_u32(svptrue_b16(), ptr, offsets); + let loaded = svldff1sh_gather_s32offset_u32(svptrue_b16(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_s64offset_s64() { + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_gather_s64offset_s64(svptrue_b8(), ptr, offsets); + let loaded = svldff1sb_gather_s64offset_s64(svptrue_b8(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_s64offset_s64() { + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_gather_s64offset_s64(svptrue_b16(), ptr, offsets); + let loaded = svldff1sh_gather_s64offset_s64(svptrue_b16(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_s64offset_s64() { + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1sw_gather_s64offset_s64(svptrue_b32(), ptr, offsets); + let loaded = svldff1sw_gather_s64offset_s64(svptrue_b32(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_s64offset_u64() { + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_gather_s64offset_u64(svptrue_b8(), ptr, offsets); + let loaded = svldff1sb_gather_s64offset_u64(svptrue_b8(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_s64offset_u64() { + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_gather_s64offset_u64(svptrue_b16(), ptr, offsets); + let loaded = svldff1sh_gather_s64offset_u64(svptrue_b16(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_s64offset_u64() { + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1sw_gather_s64offset_u64(svptrue_b32(), ptr, offsets); + let loaded = svldff1sw_gather_s64offset_u64(svptrue_b32(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_u32offset_s32() { + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_gather_u32offset_s32(svptrue_b8(), ptr, offsets); + let loaded = svldff1sb_gather_u32offset_s32(svptrue_b8(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u32offset_s32() { + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_gather_u32offset_s32(svptrue_b16(), ptr, offsets); + let loaded = svldff1sh_gather_u32offset_s32(svptrue_b16(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_u32offset_u32() { + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_gather_u32offset_u32(svptrue_b8(), ptr, offsets); + let loaded = svldff1sb_gather_u32offset_u32(svptrue_b8(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u32offset_u32() { + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_gather_u32offset_u32(svptrue_b16(), ptr, offsets); + let loaded = svldff1sh_gather_u32offset_u32(svptrue_b16(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_u64offset_s64() { + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_gather_u64offset_s64(svptrue_b8(), ptr, offsets); + let loaded = svldff1sb_gather_u64offset_s64(svptrue_b8(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u64offset_s64() { + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_gather_u64offset_s64(svptrue_b16(), ptr, offsets); + let loaded = svldff1sh_gather_u64offset_s64(svptrue_b16(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_u64offset_s64() { + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1sw_gather_u64offset_s64(svptrue_b32(), ptr, offsets); + let loaded = svldff1sw_gather_u64offset_s64(svptrue_b32(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_u64offset_u64() { + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_gather_u64offset_u64(svptrue_b8(), ptr, offsets); + let loaded = svldff1sb_gather_u64offset_u64(svptrue_b8(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u64offset_u64() { + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_gather_u64offset_u64(svptrue_b16(), ptr, offsets); + let loaded = svldff1sh_gather_u64offset_u64(svptrue_b16(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_u64offset_u64() { + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1sw_gather_u64offset_u64(svptrue_b32(), ptr, offsets); + let loaded = svldff1sw_gather_u64offset_u64(svptrue_b32(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_u32base_offset_s32() { + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sb_gather_u32base_offset_s32( + svptrue_b8(), + bases, + I8_DATA.as_ptr() as i64 + 1u32 as i64, + ); + let loaded = svldff1sb_gather_u32base_offset_s32( + svptrue_b8(), + bases, + I8_DATA.as_ptr() as i64 + 1u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u32base_offset_s32() { + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sh_gather_u32base_offset_s32( + svptrue_b16(), + bases, + I16_DATA.as_ptr() as i64 + 2u32 as i64, + ); + let loaded = svldff1sh_gather_u32base_offset_s32( + svptrue_b16(), + bases, + I16_DATA.as_ptr() as i64 + 2u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_u32base_offset_u32() { + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sb_gather_u32base_offset_u32( + svptrue_b8(), + bases, + I8_DATA.as_ptr() as i64 + 1u32 as i64, + ); + let loaded = svldff1sb_gather_u32base_offset_u32( + svptrue_b8(), + bases, + I8_DATA.as_ptr() as i64 + 1u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u32base_offset_u32() { + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sh_gather_u32base_offset_u32( + svptrue_b16(), + bases, + I16_DATA.as_ptr() as i64 + 2u32 as i64, + ); + let loaded = svldff1sh_gather_u32base_offset_u32( + svptrue_b16(), + bases, + I16_DATA.as_ptr() as i64 + 2u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_u64base_offset_s64() { + let bases = svdup_n_u64(I8_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svsetffr(); + let _ = svld1sb_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + let loaded = svldff1sb_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u64base_offset_s64() { + let bases = svdup_n_u64(I16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1sh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + let loaded = + svldff1sh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_u64base_offset_s64() { + let bases = svdup_n_u64(I32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1sw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + let loaded = + svldff1sw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_u64base_offset_u64() { + let bases = svdup_n_u64(I8_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svsetffr(); + let _ = svld1sb_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + let loaded = svldff1sb_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u64base_offset_u64() { + let bases = svdup_n_u64(I16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1sh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + let loaded = + svldff1sh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_u64base_offset_u64() { + let bases = svdup_n_u64(I32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1sw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + let loaded = + svldff1sw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_u64base_s64() { + let bases = svdup_n_u64(I8_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svsetffr(); + let _ = svld1sb_gather_u64base_s64(svptrue_b8(), bases); + let loaded = svldff1sb_gather_u64base_s64(svptrue_b8(), bases); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u64base_s64() { + let bases = svdup_n_u64(I16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1sh_gather_u64base_s64(svptrue_b16(), bases); + let loaded = svldff1sh_gather_u64base_s64(svptrue_b16(), bases); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_u64base_s64() { + let bases = svdup_n_u64(I32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1sw_gather_u64base_s64(svptrue_b32(), bases); + let loaded = svldff1sw_gather_u64base_s64(svptrue_b32(), bases); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_u64base_u64() { + let bases = svdup_n_u64(I8_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svsetffr(); + let _ = svld1sb_gather_u64base_u64(svptrue_b8(), bases); + let loaded = svldff1sb_gather_u64base_u64(svptrue_b8(), bases); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u64base_u64() { + let bases = svdup_n_u64(I16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1sh_gather_u64base_u64(svptrue_b16(), bases); + let loaded = svldff1sh_gather_u64base_u64(svptrue_b16(), bases); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_u64base_u64() { + let bases = svdup_n_u64(I32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1sw_gather_u64base_u64(svptrue_b32(), bases); + let loaded = svldff1sw_gather_u64base_u64(svptrue_b32(), bases); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_s16() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_s16(svptrue_b8(), ptr); + let loaded = svldff1sb_s16(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_s32() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_s32(svptrue_b8(), ptr); + let loaded = svldff1sb_s32(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_s32() { + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_s32(svptrue_b16(), ptr); + let loaded = svldff1sh_s32(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_s64() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_s64(svptrue_b8(), ptr); + let loaded = svldff1sb_s64(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_s64() { + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_s64(svptrue_b16(), ptr); + let loaded = svldff1sh_s64(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_s64() { + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1sw_s64(svptrue_b32(), ptr); + let loaded = svldff1sw_s64(svptrue_b32(), ptr); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_u16() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_u16(svptrue_b8(), ptr); + let loaded = svldff1sb_u16(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_u32() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_u32(svptrue_b8(), ptr); + let loaded = svldff1sb_u32(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_u32() { + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_u32(svptrue_b16(), ptr); + let loaded = svldff1sh_u32(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_u64() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_u64(svptrue_b8(), ptr); + let loaded = svldff1sb_u64(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_u64() { + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_u64(svptrue_b16(), ptr); + let loaded = svldff1sh_u64(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_u64() { + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1sw_u64(svptrue_b32(), ptr); + let loaded = svldff1sw_u64(svptrue_b32(), ptr); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_vnum_s16() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_vnum_s16(svptrue_b8(), ptr, 1); + let loaded = svldff1sb_vnum_s16(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcnth() as usize; + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_vnum_s32() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_vnum_s32(svptrue_b8(), ptr, 1); + let loaded = svldff1sb_vnum_s32(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_vnum_s32() { + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_vnum_s32(svptrue_b16(), ptr, 1); + let loaded = svldff1sh_vnum_s32(svptrue_b16(), ptr, 1); + let defined = svrdffr(); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_vnum_s64() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_vnum_s64(svptrue_b8(), ptr, 1); + let loaded = svldff1sb_vnum_s64(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_vnum_s64() { + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_vnum_s64(svptrue_b16(), ptr, 1); + let loaded = svldff1sh_vnum_s64(svptrue_b16(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_vnum_s64() { + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1sw_vnum_s64(svptrue_b32(), ptr, 1); + let loaded = svldff1sw_vnum_s64(svptrue_b32(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_vnum_u16() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_vnum_u16(svptrue_b8(), ptr, 1); + let loaded = svldff1sb_vnum_u16(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcnth() as usize; + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_vnum_u32() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_vnum_u32(svptrue_b8(), ptr, 1); + let loaded = svldff1sb_vnum_u32(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_vnum_u32() { + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_vnum_u32(svptrue_b16(), ptr, 1); + let loaded = svldff1sh_vnum_u32(svptrue_b16(), ptr, 1); + let defined = svrdffr(); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_vnum_u64() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_vnum_u64(svptrue_b8(), ptr, 1); + let loaded = svldff1sb_vnum_u64(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_vnum_u64() { + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_vnum_u64(svptrue_b16(), ptr, 1); + let loaded = svldff1sh_vnum_u64(svptrue_b16(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_vnum_u64() { + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1sw_vnum_u64(svptrue_b32(), ptr, 1); + let loaded = svldff1sw_vnum_u64(svptrue_b32(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_s32index_s32() { + let indices = svindex_s32(0, 1); + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_gather_s32index_s32(svptrue_b16(), ptr, indices); + let loaded = svldff1sh_gather_s32index_s32(svptrue_b16(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_s32index_u32() { + let indices = svindex_s32(0, 1); + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_gather_s32index_u32(svptrue_b16(), ptr, indices); + let loaded = svldff1sh_gather_s32index_u32(svptrue_b16(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_s64index_s64() { + let indices = svindex_s64(0, 1); + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_gather_s64index_s64(svptrue_b16(), ptr, indices); + let loaded = svldff1sh_gather_s64index_s64(svptrue_b16(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_s64index_s64() { + let indices = svindex_s64(0, 1); + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1sw_gather_s64index_s64(svptrue_b32(), ptr, indices); + let loaded = svldff1sw_gather_s64index_s64(svptrue_b32(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_s64index_u64() { + let indices = svindex_s64(0, 1); + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_gather_s64index_u64(svptrue_b16(), ptr, indices); + let loaded = svldff1sh_gather_s64index_u64(svptrue_b16(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_s64index_u64() { + let indices = svindex_s64(0, 1); + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1sw_gather_s64index_u64(svptrue_b32(), ptr, indices); + let loaded = svldff1sw_gather_s64index_u64(svptrue_b32(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u32index_s32() { + let indices = svindex_u32(0, 1); + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_gather_u32index_s32(svptrue_b16(), ptr, indices); + let loaded = svldff1sh_gather_u32index_s32(svptrue_b16(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u32index_u32() { + let indices = svindex_u32(0, 1); + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_gather_u32index_u32(svptrue_b16(), ptr, indices); + let loaded = svldff1sh_gather_u32index_u32(svptrue_b16(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u64index_s64() { + let indices = svindex_u64(0, 1); + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_gather_u64index_s64(svptrue_b16(), ptr, indices); + let loaded = svldff1sh_gather_u64index_s64(svptrue_b16(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_u64index_s64() { + let indices = svindex_u64(0, 1); + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1sw_gather_u64index_s64(svptrue_b32(), ptr, indices); + let loaded = svldff1sw_gather_u64index_s64(svptrue_b32(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u64index_u64() { + let indices = svindex_u64(0, 1); + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_gather_u64index_u64(svptrue_b16(), ptr, indices); + let loaded = svldff1sh_gather_u64index_u64(svptrue_b16(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_u64index_u64() { + let indices = svindex_u64(0, 1); + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1sw_gather_u64index_u64(svptrue_b32(), ptr, indices); + let loaded = svldff1sw_gather_u64index_u64(svptrue_b32(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u32base_index_s32() { + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sh_gather_u32base_index_s32( + svptrue_b16(), + bases, + I16_DATA.as_ptr() as i64 / (2u32 as i64) + 1, + ); + let loaded = svldff1sh_gather_u32base_index_s32( + svptrue_b16(), + bases, + I16_DATA.as_ptr() as i64 / (2u32 as i64) + 1, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u32base_index_u32() { + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sh_gather_u32base_index_u32( + svptrue_b16(), + bases, + I16_DATA.as_ptr() as i64 / (2u32 as i64) + 1, + ); + let loaded = svldff1sh_gather_u32base_index_u32( + svptrue_b16(), + bases, + I16_DATA.as_ptr() as i64 / (2u32 as i64) + 1, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u64base_index_s64() { + let bases = svdup_n_u64(I16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1sh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap()); + let loaded = svldff1sh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_u64base_index_s64() { + let bases = svdup_n_u64(I32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1sw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap()); + let loaded = svldff1sw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u64base_index_u64() { + let bases = svdup_n_u64(I16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1sh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap()); + let loaded = svldff1sh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_u64base_index_u64() { + let bases = svdup_n_u64(I32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1sw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap()); + let loaded = svldff1sw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_s32offset_s32() { + let offsets = svindex_s32(0, 1u32.try_into().unwrap()); + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_gather_s32offset_s32(svptrue_b8(), ptr, offsets); + let loaded = svldff1ub_gather_s32offset_s32(svptrue_b8(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_s32offset_s32() { + let offsets = svindex_s32(0, 2u32.try_into().unwrap()); + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_gather_s32offset_s32(svptrue_b16(), ptr, offsets); + let loaded = svldff1uh_gather_s32offset_s32(svptrue_b16(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_s32offset_u32() { + let offsets = svindex_s32(0, 1u32.try_into().unwrap()); + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_gather_s32offset_u32(svptrue_b8(), ptr, offsets); + let loaded = svldff1ub_gather_s32offset_u32(svptrue_b8(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_s32offset_u32() { + let offsets = svindex_s32(0, 2u32.try_into().unwrap()); + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_gather_s32offset_u32(svptrue_b16(), ptr, offsets); + let loaded = svldff1uh_gather_s32offset_u32(svptrue_b16(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_s64offset_s64() { + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_gather_s64offset_s64(svptrue_b8(), ptr, offsets); + let loaded = svldff1ub_gather_s64offset_s64(svptrue_b8(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_s64offset_s64() { + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_gather_s64offset_s64(svptrue_b16(), ptr, offsets); + let loaded = svldff1uh_gather_s64offset_s64(svptrue_b16(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_s64offset_s64() { + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1uw_gather_s64offset_s64(svptrue_b32(), ptr, offsets); + let loaded = svldff1uw_gather_s64offset_s64(svptrue_b32(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_s64offset_u64() { + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_gather_s64offset_u64(svptrue_b8(), ptr, offsets); + let loaded = svldff1ub_gather_s64offset_u64(svptrue_b8(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_s64offset_u64() { + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_gather_s64offset_u64(svptrue_b16(), ptr, offsets); + let loaded = svldff1uh_gather_s64offset_u64(svptrue_b16(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_s64offset_u64() { + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1uw_gather_s64offset_u64(svptrue_b32(), ptr, offsets); + let loaded = svldff1uw_gather_s64offset_u64(svptrue_b32(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_u32offset_s32() { + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_gather_u32offset_s32(svptrue_b8(), ptr, offsets); + let loaded = svldff1ub_gather_u32offset_s32(svptrue_b8(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u32offset_s32() { + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_gather_u32offset_s32(svptrue_b16(), ptr, offsets); + let loaded = svldff1uh_gather_u32offset_s32(svptrue_b16(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_u32offset_u32() { + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_gather_u32offset_u32(svptrue_b8(), ptr, offsets); + let loaded = svldff1ub_gather_u32offset_u32(svptrue_b8(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u32offset_u32() { + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_gather_u32offset_u32(svptrue_b16(), ptr, offsets); + let loaded = svldff1uh_gather_u32offset_u32(svptrue_b16(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_u64offset_s64() { + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_gather_u64offset_s64(svptrue_b8(), ptr, offsets); + let loaded = svldff1ub_gather_u64offset_s64(svptrue_b8(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u64offset_s64() { + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_gather_u64offset_s64(svptrue_b16(), ptr, offsets); + let loaded = svldff1uh_gather_u64offset_s64(svptrue_b16(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_u64offset_s64() { + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1uw_gather_u64offset_s64(svptrue_b32(), ptr, offsets); + let loaded = svldff1uw_gather_u64offset_s64(svptrue_b32(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_u64offset_u64() { + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_gather_u64offset_u64(svptrue_b8(), ptr, offsets); + let loaded = svldff1ub_gather_u64offset_u64(svptrue_b8(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u64offset_u64() { + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_gather_u64offset_u64(svptrue_b16(), ptr, offsets); + let loaded = svldff1uh_gather_u64offset_u64(svptrue_b16(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_u64offset_u64() { + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1uw_gather_u64offset_u64(svptrue_b32(), ptr, offsets); + let loaded = svldff1uw_gather_u64offset_u64(svptrue_b32(), ptr, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_u32base_offset_s32() { + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1ub_gather_u32base_offset_s32( + svptrue_b8(), + bases, + U8_DATA.as_ptr() as i64 + 1u32 as i64, + ); + let loaded = svldff1ub_gather_u32base_offset_s32( + svptrue_b8(), + bases, + U8_DATA.as_ptr() as i64 + 1u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u32base_offset_s32() { + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1uh_gather_u32base_offset_s32( + svptrue_b16(), + bases, + U16_DATA.as_ptr() as i64 + 2u32 as i64, + ); + let loaded = svldff1uh_gather_u32base_offset_s32( + svptrue_b16(), + bases, + U16_DATA.as_ptr() as i64 + 2u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_u32base_offset_u32() { + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1ub_gather_u32base_offset_u32( + svptrue_b8(), + bases, + U8_DATA.as_ptr() as i64 + 1u32 as i64, + ); + let loaded = svldff1ub_gather_u32base_offset_u32( + svptrue_b8(), + bases, + U8_DATA.as_ptr() as i64 + 1u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u32base_offset_u32() { + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1uh_gather_u32base_offset_u32( + svptrue_b16(), + bases, + U16_DATA.as_ptr() as i64 + 2u32 as i64, + ); + let loaded = svldff1uh_gather_u32base_offset_u32( + svptrue_b16(), + bases, + U16_DATA.as_ptr() as i64 + 2u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_u64base_offset_s64() { + let bases = svdup_n_u64(U8_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svsetffr(); + let _ = svld1ub_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + let loaded = svldff1ub_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u64base_offset_s64() { + let bases = svdup_n_u64(U16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1uh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + let loaded = + svldff1uh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_u64base_offset_s64() { + let bases = svdup_n_u64(U32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1uw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + let loaded = + svldff1uw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_u64base_offset_u64() { + let bases = svdup_n_u64(U8_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svsetffr(); + let _ = svld1ub_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + let loaded = svldff1ub_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u64base_offset_u64() { + let bases = svdup_n_u64(U16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1uh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + let loaded = + svldff1uh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_u64base_offset_u64() { + let bases = svdup_n_u64(U32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1uw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + let loaded = + svldff1uw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_u64base_s64() { + let bases = svdup_n_u64(U8_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svsetffr(); + let _ = svld1ub_gather_u64base_s64(svptrue_b8(), bases); + let loaded = svldff1ub_gather_u64base_s64(svptrue_b8(), bases); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u64base_s64() { + let bases = svdup_n_u64(U16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1uh_gather_u64base_s64(svptrue_b16(), bases); + let loaded = svldff1uh_gather_u64base_s64(svptrue_b16(), bases); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_u64base_s64() { + let bases = svdup_n_u64(U32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1uw_gather_u64base_s64(svptrue_b32(), bases); + let loaded = svldff1uw_gather_u64base_s64(svptrue_b32(), bases); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_u64base_u64() { + let bases = svdup_n_u64(U8_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svsetffr(); + let _ = svld1ub_gather_u64base_u64(svptrue_b8(), bases); + let loaded = svldff1ub_gather_u64base_u64(svptrue_b8(), bases); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u64base_u64() { + let bases = svdup_n_u64(U16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1uh_gather_u64base_u64(svptrue_b16(), bases); + let loaded = svldff1uh_gather_u64base_u64(svptrue_b16(), bases); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_u64base_u64() { + let bases = svdup_n_u64(U32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1uw_gather_u64base_u64(svptrue_b32(), bases); + let loaded = svldff1uw_gather_u64base_u64(svptrue_b32(), bases); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_s16() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_s16(svptrue_b8(), ptr); + let loaded = svldff1ub_s16(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_s32() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_s32(svptrue_b8(), ptr); + let loaded = svldff1ub_s32(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_s32() { + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_s32(svptrue_b16(), ptr); + let loaded = svldff1uh_s32(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_s64() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_s64(svptrue_b8(), ptr); + let loaded = svldff1ub_s64(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_s64() { + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_s64(svptrue_b16(), ptr); + let loaded = svldff1uh_s64(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_s64() { + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1uw_s64(svptrue_b32(), ptr); + let loaded = svldff1uw_s64(svptrue_b32(), ptr); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_u16() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_u16(svptrue_b8(), ptr); + let loaded = svldff1ub_u16(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_u32() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_u32(svptrue_b8(), ptr); + let loaded = svldff1ub_u32(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_u32() { + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_u32(svptrue_b16(), ptr); + let loaded = svldff1uh_u32(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_u64() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_u64(svptrue_b8(), ptr); + let loaded = svldff1ub_u64(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_u64() { + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_u64(svptrue_b16(), ptr); + let loaded = svldff1uh_u64(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_u64() { + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1uw_u64(svptrue_b32(), ptr); + let loaded = svldff1uw_u64(svptrue_b32(), ptr); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_vnum_s16() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_vnum_s16(svptrue_b8(), ptr, 1); + let loaded = svldff1ub_vnum_s16(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcnth() as usize; + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_vnum_s32() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_vnum_s32(svptrue_b8(), ptr, 1); + let loaded = svldff1ub_vnum_s32(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_vnum_s32() { + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_vnum_s32(svptrue_b16(), ptr, 1); + let loaded = svldff1uh_vnum_s32(svptrue_b16(), ptr, 1); + let defined = svrdffr(); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_vnum_s64() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_vnum_s64(svptrue_b8(), ptr, 1); + let loaded = svldff1ub_vnum_s64(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_vnum_s64() { + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_vnum_s64(svptrue_b16(), ptr, 1); + let loaded = svldff1uh_vnum_s64(svptrue_b16(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_vnum_s64() { + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1uw_vnum_s64(svptrue_b32(), ptr, 1); + let loaded = svldff1uw_vnum_s64(svptrue_b32(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_vnum_u16() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_vnum_u16(svptrue_b8(), ptr, 1); + let loaded = svldff1ub_vnum_u16(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcnth() as usize; + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_vnum_u32() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_vnum_u32(svptrue_b8(), ptr, 1); + let loaded = svldff1ub_vnum_u32(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_vnum_u32() { + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_vnum_u32(svptrue_b16(), ptr, 1); + let loaded = svldff1uh_vnum_u32(svptrue_b16(), ptr, 1); + let defined = svrdffr(); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_vnum_u64() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_vnum_u64(svptrue_b8(), ptr, 1); + let loaded = svldff1ub_vnum_u64(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_vnum_u64() { + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_vnum_u64(svptrue_b16(), ptr, 1); + let loaded = svldff1uh_vnum_u64(svptrue_b16(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_vnum_u64() { + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1uw_vnum_u64(svptrue_b32(), ptr, 1); + let loaded = svldff1uw_vnum_u64(svptrue_b32(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_s32index_s32() { + let indices = svindex_s32(0, 1); + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_gather_s32index_s32(svptrue_b16(), ptr, indices); + let loaded = svldff1uh_gather_s32index_s32(svptrue_b16(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_s32index_u32() { + let indices = svindex_s32(0, 1); + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_gather_s32index_u32(svptrue_b16(), ptr, indices); + let loaded = svldff1uh_gather_s32index_u32(svptrue_b16(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_s64index_s64() { + let indices = svindex_s64(0, 1); + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_gather_s64index_s64(svptrue_b16(), ptr, indices); + let loaded = svldff1uh_gather_s64index_s64(svptrue_b16(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_s64index_s64() { + let indices = svindex_s64(0, 1); + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1uw_gather_s64index_s64(svptrue_b32(), ptr, indices); + let loaded = svldff1uw_gather_s64index_s64(svptrue_b32(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_s64index_u64() { + let indices = svindex_s64(0, 1); + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_gather_s64index_u64(svptrue_b16(), ptr, indices); + let loaded = svldff1uh_gather_s64index_u64(svptrue_b16(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_s64index_u64() { + let indices = svindex_s64(0, 1); + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1uw_gather_s64index_u64(svptrue_b32(), ptr, indices); + let loaded = svldff1uw_gather_s64index_u64(svptrue_b32(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u32index_s32() { + let indices = svindex_u32(0, 1); + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_gather_u32index_s32(svptrue_b16(), ptr, indices); + let loaded = svldff1uh_gather_u32index_s32(svptrue_b16(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u32index_u32() { + let indices = svindex_u32(0, 1); + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_gather_u32index_u32(svptrue_b16(), ptr, indices); + let loaded = svldff1uh_gather_u32index_u32(svptrue_b16(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u64index_s64() { + let indices = svindex_u64(0, 1); + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_gather_u64index_s64(svptrue_b16(), ptr, indices); + let loaded = svldff1uh_gather_u64index_s64(svptrue_b16(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_u64index_s64() { + let indices = svindex_u64(0, 1); + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1uw_gather_u64index_s64(svptrue_b32(), ptr, indices); + let loaded = svldff1uw_gather_u64index_s64(svptrue_b32(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u64index_u64() { + let indices = svindex_u64(0, 1); + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_gather_u64index_u64(svptrue_b16(), ptr, indices); + let loaded = svldff1uh_gather_u64index_u64(svptrue_b16(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_u64index_u64() { + let indices = svindex_u64(0, 1); + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1uw_gather_u64index_u64(svptrue_b32(), ptr, indices); + let loaded = svldff1uw_gather_u64index_u64(svptrue_b32(), ptr, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u32base_index_s32() { + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1uh_gather_u32base_index_s32( + svptrue_b16(), + bases, + U16_DATA.as_ptr() as i64 / (2u32 as i64) + 1, + ); + let loaded = svldff1uh_gather_u32base_index_s32( + svptrue_b16(), + bases, + U16_DATA.as_ptr() as i64 / (2u32 as i64) + 1, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u32base_index_u32() { + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1uh_gather_u32base_index_u32( + svptrue_b16(), + bases, + U16_DATA.as_ptr() as i64 / (2u32 as i64) + 1, + ); + let loaded = svldff1uh_gather_u32base_index_u32( + svptrue_b16(), + bases, + U16_DATA.as_ptr() as i64 / (2u32 as i64) + 1, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u64base_index_s64() { + let bases = svdup_n_u64(U16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1uh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap()); + let loaded = svldff1uh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_u64base_index_s64() { + let bases = svdup_n_u64(U32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1uw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap()); + let loaded = svldff1uw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u64base_index_u64() { + let bases = svdup_n_u64(U16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1uh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap()); + let loaded = svldff1uh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_u64base_index_u64() { + let bases = svdup_n_u64(U32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1uw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap()); + let loaded = svldff1uw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_f32() { + let ptr = F32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_f32(svptrue_b32(), ptr); + let loaded = svldnf1_f32(svptrue_b32(), ptr); + let defined = svrdffr(); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_f64() { + let ptr = F64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_f64(svptrue_b64(), ptr); + let loaded = svldnf1_f64(svptrue_b64(), ptr); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_s8() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1_s8(svptrue_b8(), ptr); + let loaded = svldnf1_s8(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_i8( + loaded, + svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_s16() { + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1_s16(svptrue_b16(), ptr); + let loaded = svldnf1_s16(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_s32() { + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_s32(svptrue_b32(), ptr); + let loaded = svldnf1_s32(svptrue_b32(), ptr); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_s64() { + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_s64(svptrue_b64(), ptr); + let loaded = svldnf1_s64(svptrue_b64(), ptr); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_u8() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1_u8(svptrue_b8(), ptr); + let loaded = svldnf1_u8(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_u8( + loaded, + svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_u16() { + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1_u16(svptrue_b16(), ptr); + let loaded = svldnf1_u16(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_u32() { + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_u32(svptrue_b32(), ptr); + let loaded = svldnf1_u32(svptrue_b32(), ptr); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_u64() { + let ptr = U64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_u64(svptrue_b64(), ptr); + let loaded = svldnf1_u64(svptrue_b64(), ptr); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_f32() { + let ptr = F32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_vnum_f32(svptrue_b32(), ptr, 1); + let loaded = svldnf1_vnum_f32(svptrue_b32(), ptr, 1); + let defined = svrdffr(); + let len = svcntw() as usize; + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_f64() { + let ptr = F64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_vnum_f64(svptrue_b64(), ptr, 1); + let loaded = svldnf1_vnum_f64(svptrue_b64(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_s8() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1_vnum_s8(svptrue_b8(), ptr, 1); + let loaded = svldnf1_vnum_s8(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcntb() as usize; + assert_vector_matches_i8( + loaded, + svindex_s8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_s16() { + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1_vnum_s16(svptrue_b16(), ptr, 1); + let loaded = svldnf1_vnum_s16(svptrue_b16(), ptr, 1); + let defined = svrdffr(); + let len = svcnth() as usize; + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_s32() { + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_vnum_s32(svptrue_b32(), ptr, 1); + let loaded = svldnf1_vnum_s32(svptrue_b32(), ptr, 1); + let defined = svrdffr(); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_s64() { + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_vnum_s64(svptrue_b64(), ptr, 1); + let loaded = svldnf1_vnum_s64(svptrue_b64(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_u8() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1_vnum_u8(svptrue_b8(), ptr, 1); + let loaded = svldnf1_vnum_u8(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcntb() as usize; + assert_vector_matches_u8( + loaded, + svindex_u8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_u16() { + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1_vnum_u16(svptrue_b16(), ptr, 1); + let loaded = svldnf1_vnum_u16(svptrue_b16(), ptr, 1); + let defined = svrdffr(); + let len = svcnth() as usize; + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_u32() { + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1_vnum_u32(svptrue_b32(), ptr, 1); + let loaded = svldnf1_vnum_u32(svptrue_b32(), ptr, 1); + let defined = svrdffr(); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_u64() { + let ptr = U64_DATA.as_ptr(); + svsetffr(); + let _ = svld1_vnum_u64(svptrue_b64(), ptr, 1); + let loaded = svldnf1_vnum_u64(svptrue_b64(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_s16() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_s16(svptrue_b8(), ptr); + let loaded = svldnf1sb_s16(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_s32() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_s32(svptrue_b8(), ptr); + let loaded = svldnf1sb_s32(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_s32() { + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_s32(svptrue_b16(), ptr); + let loaded = svldnf1sh_s32(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_s64() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_s64(svptrue_b8(), ptr); + let loaded = svldnf1sb_s64(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_s64() { + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_s64(svptrue_b16(), ptr); + let loaded = svldnf1sh_s64(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sw_s64() { + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1sw_s64(svptrue_b32(), ptr); + let loaded = svldnf1sw_s64(svptrue_b32(), ptr); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_u16() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_u16(svptrue_b8(), ptr); + let loaded = svldnf1sb_u16(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_u32() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_u32(svptrue_b8(), ptr); + let loaded = svldnf1sb_u32(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_u32() { + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_u32(svptrue_b16(), ptr); + let loaded = svldnf1sh_u32(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_u64() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_u64(svptrue_b8(), ptr); + let loaded = svldnf1sb_u64(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_u64() { + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_u64(svptrue_b16(), ptr); + let loaded = svldnf1sh_u64(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sw_u64() { + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1sw_u64(svptrue_b32(), ptr); + let loaded = svldnf1sw_u64(svptrue_b32(), ptr); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_vnum_s16() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_vnum_s16(svptrue_b8(), ptr, 1); + let loaded = svldnf1sb_vnum_s16(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcnth() as usize; + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_vnum_s32() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_vnum_s32(svptrue_b8(), ptr, 1); + let loaded = svldnf1sb_vnum_s32(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_vnum_s32() { + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_vnum_s32(svptrue_b16(), ptr, 1); + let loaded = svldnf1sh_vnum_s32(svptrue_b16(), ptr, 1); + let defined = svrdffr(); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_vnum_s64() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_vnum_s64(svptrue_b8(), ptr, 1); + let loaded = svldnf1sb_vnum_s64(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_vnum_s64() { + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_vnum_s64(svptrue_b16(), ptr, 1); + let loaded = svldnf1sh_vnum_s64(svptrue_b16(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sw_vnum_s64() { + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1sw_vnum_s64(svptrue_b32(), ptr, 1); + let loaded = svldnf1sw_vnum_s64(svptrue_b32(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_vnum_u16() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_vnum_u16(svptrue_b8(), ptr, 1); + let loaded = svldnf1sb_vnum_u16(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcnth() as usize; + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_vnum_u32() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_vnum_u32(svptrue_b8(), ptr, 1); + let loaded = svldnf1sb_vnum_u32(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_vnum_u32() { + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_vnum_u32(svptrue_b16(), ptr, 1); + let loaded = svldnf1sh_vnum_u32(svptrue_b16(), ptr, 1); + let defined = svrdffr(); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_vnum_u64() { + let ptr = I8_DATA.as_ptr(); + svsetffr(); + let _ = svld1sb_vnum_u64(svptrue_b8(), ptr, 1); + let loaded = svldnf1sb_vnum_u64(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_vnum_u64() { + let ptr = I16_DATA.as_ptr(); + svsetffr(); + let _ = svld1sh_vnum_u64(svptrue_b16(), ptr, 1); + let loaded = svldnf1sh_vnum_u64(svptrue_b16(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sw_vnum_u64() { + let ptr = I32_DATA.as_ptr(); + svsetffr(); + let _ = svld1sw_vnum_u64(svptrue_b32(), ptr, 1); + let loaded = svldnf1sw_vnum_u64(svptrue_b32(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_s16() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_s16(svptrue_b8(), ptr); + let loaded = svldnf1ub_s16(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_s32() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_s32(svptrue_b8(), ptr); + let loaded = svldnf1ub_s32(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_s32() { + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_s32(svptrue_b16(), ptr); + let loaded = svldnf1uh_s32(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_s64() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_s64(svptrue_b8(), ptr); + let loaded = svldnf1ub_s64(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_s64() { + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_s64(svptrue_b16(), ptr); + let loaded = svldnf1uh_s64(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uw_s64() { + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1uw_s64(svptrue_b32(), ptr); + let loaded = svldnf1uw_s64(svptrue_b32(), ptr); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_u16() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_u16(svptrue_b8(), ptr); + let loaded = svldnf1ub_u16(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_u32() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_u32(svptrue_b8(), ptr); + let loaded = svldnf1ub_u32(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_u32() { + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_u32(svptrue_b16(), ptr); + let loaded = svldnf1uh_u32(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_u64() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_u64(svptrue_b8(), ptr); + let loaded = svldnf1ub_u64(svptrue_b8(), ptr); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_u64() { + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_u64(svptrue_b16(), ptr); + let loaded = svldnf1uh_u64(svptrue_b16(), ptr); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uw_u64() { + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1uw_u64(svptrue_b32(), ptr); + let loaded = svldnf1uw_u64(svptrue_b32(), ptr); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_vnum_s16() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_vnum_s16(svptrue_b8(), ptr, 1); + let loaded = svldnf1ub_vnum_s16(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcnth() as usize; + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_vnum_s32() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_vnum_s32(svptrue_b8(), ptr, 1); + let loaded = svldnf1ub_vnum_s32(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_vnum_s32() { + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_vnum_s32(svptrue_b16(), ptr, 1); + let loaded = svldnf1uh_vnum_s32(svptrue_b16(), ptr, 1); + let defined = svrdffr(); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_vnum_s64() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_vnum_s64(svptrue_b8(), ptr, 1); + let loaded = svldnf1ub_vnum_s64(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_vnum_s64() { + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_vnum_s64(svptrue_b16(), ptr, 1); + let loaded = svldnf1uh_vnum_s64(svptrue_b16(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uw_vnum_s64() { + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1uw_vnum_s64(svptrue_b32(), ptr, 1); + let loaded = svldnf1uw_vnum_s64(svptrue_b32(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_vnum_u16() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_vnum_u16(svptrue_b8(), ptr, 1); + let loaded = svldnf1ub_vnum_u16(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcnth() as usize; + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_vnum_u32() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_vnum_u32(svptrue_b8(), ptr, 1); + let loaded = svldnf1ub_vnum_u32(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_vnum_u32() { + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_vnum_u32(svptrue_b16(), ptr, 1); + let loaded = svldnf1uh_vnum_u32(svptrue_b16(), ptr, 1); + let defined = svrdffr(); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_vnum_u64() { + let ptr = U8_DATA.as_ptr(); + svsetffr(); + let _ = svld1ub_vnum_u64(svptrue_b8(), ptr, 1); + let loaded = svldnf1ub_vnum_u64(svptrue_b8(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_vnum_u64() { + let ptr = U16_DATA.as_ptr(); + svsetffr(); + let _ = svld1uh_vnum_u64(svptrue_b16(), ptr, 1); + let loaded = svldnf1uh_vnum_u64(svptrue_b16(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uw_vnum_u64() { + let ptr = U32_DATA.as_ptr(); + svsetffr(); + let _ = svld1uw_vnum_u64(svptrue_b32(), ptr, 1); + let loaded = svldnf1uw_vnum_u64(svptrue_b32(), ptr, 1); + let defined = svrdffr(); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_f32_with_svstnt1_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + svstnt1_f32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svldnt1_f32(svptrue_b32(), storage.as_ptr() as *const f32); + let defined = svrdffr(); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_f64_with_svstnt1_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + svstnt1_f64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svldnt1_f64(svptrue_b64(), storage.as_ptr() as *const f64); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_s8_with_svstnt1_s8() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_s8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1_s8(svptrue_b8(), storage.as_ptr() as *const i8); + let defined = svrdffr(); + assert_vector_matches_i8( + loaded, + svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_s16_with_svstnt1_s16() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_s16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1_s16(svptrue_b16(), storage.as_ptr() as *const i16); + let defined = svrdffr(); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_s32_with_svstnt1_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_s32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1_s32(svptrue_b32(), storage.as_ptr() as *const i32); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_s64_with_svstnt1_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_s64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svldnt1_s64(svptrue_b64(), storage.as_ptr() as *const i64); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_u8_with_svstnt1_u8() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_u8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svldnt1_u8(svptrue_b8(), storage.as_ptr() as *const u8); + let defined = svrdffr(); + assert_vector_matches_u8( + loaded, + svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_u16_with_svstnt1_u16() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_u16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svldnt1_u16(svptrue_b16(), storage.as_ptr() as *const u16); + let defined = svrdffr(); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_u32_with_svstnt1_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_u32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svldnt1_u32(svptrue_b32(), storage.as_ptr() as *const u32); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_u64_with_svstnt1_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_u64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svldnt1_u64(svptrue_b64(), storage.as_ptr() as *const u64); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_f32_with_svstnt1_vnum_f32() { + let len = svcntw() as usize; + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); + svstnt1_vnum_f32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svldnt1_vnum_f32(svptrue_b32(), storage.as_ptr() as *const f32, 1); + let defined = svrdffr(); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_f64_with_svstnt1_vnum_f64() { + let len = svcntd() as usize; + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); + svstnt1_vnum_f64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svldnt1_vnum_f64(svptrue_b64(), storage.as_ptr() as *const f64, 1); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_s8_with_svstnt1_vnum_s8() { + let len = svcntb() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_s8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1_vnum_s8(svptrue_b8(), storage.as_ptr() as *const i8, 1); + let defined = svrdffr(); + assert_vector_matches_i8( + loaded, + svindex_s8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_s16_with_svstnt1_vnum_s16() { + let len = svcnth() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_s16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1_vnum_s16(svptrue_b16(), storage.as_ptr() as *const i16, 1); + let defined = svrdffr(); + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_s32_with_svstnt1_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_s32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1_vnum_s32(svptrue_b32(), storage.as_ptr() as *const i32, 1); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_s64_with_svstnt1_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_s64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svldnt1_vnum_s64(svptrue_b64(), storage.as_ptr() as *const i64, 1); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_u8_with_svstnt1_vnum_u8() { + let len = svcntb() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_u8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svldnt1_vnum_u8(svptrue_b8(), storage.as_ptr() as *const u8, 1); + let defined = svrdffr(); + assert_vector_matches_u8( + loaded, + svindex_u8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_u16_with_svstnt1_vnum_u16() { + let len = svcnth() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_u16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svldnt1_vnum_u16(svptrue_b16(), storage.as_ptr() as *const u16, 1); + let defined = svrdffr(); + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_u32_with_svstnt1_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_u32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svldnt1_vnum_u32(svptrue_b32(), storage.as_ptr() as *const u32, 1); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_u64_with_svstnt1_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_u64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svldnt1_vnum_u64(svptrue_b64(), storage.as_ptr() as *const u64, 1); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + defined, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb() { + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = svprfb::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b8(), ptr); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh() { + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = svprfh::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b16(), ptr); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw() { + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = svprfw::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b32(), ptr); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd() { + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = svprfd::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b64(), ptr); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_gather_s32offset() { + let offsets = svindex_s32(0, 4u32.try_into().unwrap()); + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = + svprfb_gather_s32offset::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b32(), ptr, offsets); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_gather_s32index() { + let indices = svindex_s32(0, 1); + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = + svprfh_gather_s32index::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b32(), ptr, indices); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_gather_s32index() { + let indices = svindex_s32(0, 1); + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = + svprfw_gather_s32index::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b32(), ptr, indices); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_gather_s32index() { + let indices = svindex_s32(0, 1); + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = + svprfd_gather_s32index::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b32(), ptr, indices); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_gather_s64offset() { + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = + svprfb_gather_s64offset::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b64(), ptr, offsets); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_gather_s64index() { + let indices = svindex_s64(0, 1); + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = + svprfh_gather_s64index::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b64(), ptr, indices); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_gather_s64index() { + let indices = svindex_s64(0, 1); + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = + svprfw_gather_s64index::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b64(), ptr, indices); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_gather_s64index() { + let indices = svindex_s64(0, 1); + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = + svprfd_gather_s64index::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b64(), ptr, indices); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_gather_u32offset() { + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = + svprfb_gather_u32offset::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b32(), ptr, offsets); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_gather_u32index() { + let indices = svindex_u32(0, 1); + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = + svprfh_gather_u32index::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b32(), ptr, indices); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_gather_u32index() { + let indices = svindex_u32(0, 1); + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = + svprfw_gather_u32index::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b32(), ptr, indices); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_gather_u32index() { + let indices = svindex_u32(0, 1); + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = + svprfd_gather_u32index::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b32(), ptr, indices); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_gather_u64offset() { + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = + svprfb_gather_u64offset::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b64(), ptr, offsets); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_gather_u64index() { + let indices = svindex_u64(0, 1); + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = + svprfh_gather_u64index::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b64(), ptr, indices); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_gather_u64index() { + let indices = svindex_u64(0, 1); + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = + svprfw_gather_u64index::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b64(), ptr, indices); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_gather_u64index() { + let indices = svindex_u64(0, 1); + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = + svprfd_gather_u64index::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b64(), ptr, indices); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_gather_u64base() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfb_gather_u64base::<{ svprfop::SV_PLDL1KEEP }>(svptrue_b64(), bases); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_gather_u64base() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfh_gather_u64base::<{ svprfop::SV_PLDL1KEEP }>(svptrue_b64(), bases); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_gather_u64base() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfw_gather_u64base::<{ svprfop::SV_PLDL1KEEP }>(svptrue_b64(), bases); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_gather_u64base() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfd_gather_u64base::<{ svprfop::SV_PLDL1KEEP }>(svptrue_b64(), bases); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_gather_u32base_offset() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let loaded = svprfb_gather_u32base_offset::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b32(), + bases, + U32_DATA.as_ptr() as i64 + 4u32 as i64, + ); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_gather_u32base_index() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let loaded = svprfh_gather_u32base_index::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b32(), + bases, + U32_DATA.as_ptr() as i64 / (4u32 as i64) + 1, + ); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_gather_u32base_index() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let loaded = svprfw_gather_u32base_index::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b32(), + bases, + U32_DATA.as_ptr() as i64 / (4u32 as i64) + 1, + ); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_gather_u32base_index() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let loaded = svprfd_gather_u32base_index::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b32(), + bases, + U32_DATA.as_ptr() as i64 / (4u32 as i64) + 1, + ); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_gather_u64base_offset() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfb_gather_u64base_offset::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b64(), + bases, + 8u32.try_into().unwrap(), + ); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_gather_u64base_index() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfh_gather_u64base_index::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b64(), + bases, + 1.try_into().unwrap(), + ); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_gather_u64base_index() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfw_gather_u64base_index::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b64(), + bases, + 1.try_into().unwrap(), + ); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_gather_u64base_index() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfd_gather_u64base_index::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b64(), + bases, + 1.try_into().unwrap(), + ); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_vnum() { + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = svprfb_vnum::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b8(), ptr, 1); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_vnum() { + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = svprfh_vnum::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b16(), ptr, 1); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_vnum() { + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = svprfw_vnum::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b32(), ptr, 1); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_vnum() { + let ptr = I64_DATA.as_ptr(); + svsetffr(); + let loaded = svprfd_vnum::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b64(), ptr, 1); + let defined = svrdffr(); +} +#[simd_test(enable = "sve")] +unsafe fn test_ffr() { + svsetffr(); + let ffr = svrdffr(); + assert_vector_matches_u8(svdup_n_u8_z(ffr, 1), svindex_u8(1, 0), ffr); + let pred = svdupq_n_b8( + true, false, true, false, true, false, true, false, true, false, true, false, true, false, + true, false, + ); + svwrffr(pred); + let ffr = svrdffr_z(svptrue_b8()); + assert_vector_matches_u8(svdup_n_u8_z(ffr, 1), svdup_n_u8_z(pred, 1), ffr); +} diff --git a/library/stdarch/crates/core_arch/src/aarch64/sve/mod.rs b/library/stdarch/crates/core_arch/src/aarch64/sve/mod.rs new file mode 100644 index 0000000000000..41fd12d3517b4 --- /dev/null +++ b/library/stdarch/crates/core_arch/src/aarch64/sve/mod.rs @@ -0,0 +1,387 @@ +//! SVE intrinsics + +#![allow(non_camel_case_types)] + +// `generated.rs` has a `super::*` and this import is for that +use crate::intrinsics::{simd::*, *}; + +#[rustfmt::skip] +mod generated; +#[rustfmt::skip] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub use self::generated::*; + +use crate::{marker::ConstParamTy, mem::transmute}; + +pub(super) trait AsUnsigned { + type Unsigned; + unsafe fn as_unsigned(self) -> Self::Unsigned; +} + +pub(super) trait AsSigned { + type Signed; + unsafe fn as_signed(self) -> Self::Signed; +} + +/// Same as `Into` but with into being unsafe so that it can have the required `target_feature` +pub(super) trait SveInto: Sized { + unsafe fn sve_into(self) -> T; +} + +impl SveInto for T { + #[inline] + #[target_feature(enable = "sve")] + unsafe fn sve_into(self) -> T { + self + } +} + +macro_rules! impl_sve_type { + ($(($v:vis, $elem_type:ty, $name:ident, $elt:literal))*) => ($( + #[doc = concat!("Scalable vector of type ", stringify!($elem_type))] + #[derive(Clone, Copy)] + #[rustc_scalable_vector($elt)] + #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] + $v struct $name($elem_type); + )*) +} + +macro_rules! impl_sve_tuple_type { + ($(($v:vis, $vec_type:ty, $elt:tt, $name:ident))*) => ($( + impl_sve_tuple_type!(@ ($v, $vec_type, $elt, $name)); + )*); + (@ ($v:vis, $vec_type:ty, 2, $name:ident)) => ( + #[doc = concat!("Two-element tuple of scalable vectors of type ", stringify!($vec_type))] + #[derive(Clone, Copy)] + #[rustc_scalable_vector] + #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] + $v struct $name($vec_type, $vec_type); + ); + (@ ($v:vis, $vec_type:ty, 3, $name:ident)) => ( + #[doc = concat!("Three-element tuple of scalable vectors of type ", stringify!($vec_type))] + #[derive(Clone, Copy)] + #[rustc_scalable_vector] + #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] + $v struct $name($vec_type, $vec_type, $vec_type); + ); + (@ ($v:vis, $vec_type:ty, 4, $name:ident)) => ( + #[doc = concat!("Four-element tuple of scalable vectors of type ", stringify!($vec_type))] + #[derive(Clone, Copy)] + #[rustc_scalable_vector] + #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] + $v struct $name($vec_type, $vec_type, $vec_type, $vec_type); + ); +} + +macro_rules! impl_sign_conversions_sv { + ($(($signed:ty, $unsigned:ty))*) => ($( + impl AsUnsigned for $signed { + type Unsigned = $unsigned; + + #[inline] + #[target_feature(enable = "sve")] + unsafe fn as_unsigned(self) -> $unsigned { + transmute_unchecked(self) + } + } + + impl AsSigned for $unsigned { + type Signed = $signed; + + #[inline] + #[target_feature(enable = "sve")] + unsafe fn as_signed(self) -> $signed { + transmute_unchecked(self) + } + } + )*) +} + +macro_rules! impl_sign_conversions { + ($(($signed:ty, $unsigned:ty))*) => ($( + impl AsUnsigned for $signed { + type Unsigned = $unsigned; + + #[inline] + #[target_feature(enable = "sve")] + unsafe fn as_unsigned(self) -> $unsigned { + transmute(self) + } + } + + impl AsSigned for $unsigned { + type Signed = $signed; + + #[inline] + #[target_feature(enable = "sve")] + unsafe fn as_signed(self) -> $signed { + transmute(self) + } + } + )*) +} + +/// LLVM requires the predicate lane count to be the same as the lane count +/// it's working with. However the ACLE only defines one bool type and the +/// instruction set doesn't have this distinction. As a result we have to +/// create these internal types so we can match the LLVM signature. Each of +/// these internal types can be converted to the public `svbool_t` type and +/// the `svbool_t` type can be converted into these. +macro_rules! impl_internal_sve_predicate { + ($(($name:ident, $elt:literal))*) => ($( + impl_sve_type! { + (pub(super), bool, $name, $elt) + } + + impl SveInto for $name { + #[inline] + #[target_feature(enable = "sve")] + unsafe fn sve_into(self) -> svbool_t { + #[allow(improper_ctypes)] + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = concat!("llvm.aarch64.sve.convert.to.svbool.nxv", $elt, "i1") + )] + fn convert_to_svbool(b: $name) -> svbool_t; + } + unsafe { convert_to_svbool(self) } + } + } + + #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] + impl SveInto<$name> for svbool_t { + #[inline] + #[target_feature(enable = "sve")] + unsafe fn sve_into(self) -> $name { + #[allow(improper_ctypes)] + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = concat!("llvm.aarch64.sve.convert.from.svbool.nxv", $elt, "i1") + )] + fn convert_from_svbool(b: svbool_t) -> $name; + } + unsafe { convert_from_svbool(self) } + } + } + )*) +} + +impl_sve_type! { + (pub, bool, svbool_t, 16) + + (pub, i8, svint8_t, 16) + (pub, u8, svuint8_t, 16) + + (pub, i16, svint16_t, 8) + (pub, u16, svuint16_t, 8) + (pub, f32, svfloat32_t, 4) + (pub, i32, svint32_t, 4) + (pub, u32, svuint32_t, 4) + (pub, f64, svfloat64_t, 2) + (pub, i64, svint64_t, 2) + (pub, u64, svuint64_t, 2) + + // Internal types: + (pub(super), i8, nxv2i8, 2) + (pub(super), i8, nxv4i8, 4) + (pub(super), i8, nxv8i8, 8) + + (pub(super), i16, nxv2i16, 2) + (pub(super), i16, nxv4i16, 4) + + (pub(super), i32, nxv2i32, 2) + + (pub(super), u8, nxv2u8, 2) + (pub(super), u8, nxv4u8, 4) + (pub(super), u8, nxv8u8, 8) + + (pub(super), u16, nxv2u16, 2) + (pub(super), u16, nxv4u16, 4) + + (pub(super), u32, nxv2u32, 2) +} + +impl_sve_tuple_type! { + (pub, svint8_t, 2, svint8x2_t) + (pub, svuint8_t, 2, svuint8x2_t) + (pub, svint16_t, 2, svint16x2_t) + (pub, svuint16_t, 2, svuint16x2_t) + (pub, svfloat32_t, 2, svfloat32x2_t) + (pub, svint32_t, 2, svint32x2_t) + (pub, svuint32_t, 2, svuint32x2_t) + (pub, svfloat64_t, 2, svfloat64x2_t) + (pub, svint64_t, 2, svint64x2_t) + (pub, svuint64_t, 2, svuint64x2_t) + + (pub, svint8_t, 3, svint8x3_t) + (pub, svuint8_t, 3, svuint8x3_t) + (pub, svint16_t, 3, svint16x3_t) + (pub, svuint16_t, 3, svuint16x3_t) + (pub, svfloat32_t, 3, svfloat32x3_t) + (pub, svint32_t, 3, svint32x3_t) + (pub, svuint32_t, 3, svuint32x3_t) + (pub, svfloat64_t, 3, svfloat64x3_t) + (pub, svint64_t, 3, svint64x3_t) + (pub, svuint64_t, 3, svuint64x3_t) + + (pub, svint8_t, 4, svint8x4_t) + (pub, svuint8_t, 4, svuint8x4_t) + (pub, svint16_t, 4, svint16x4_t) + (pub, svuint16_t, 4, svuint16x4_t) + (pub, svfloat32_t, 4, svfloat32x4_t) + (pub, svint32_t, 4, svint32x4_t) + (pub, svuint32_t, 4, svuint32x4_t) + (pub, svfloat64_t, 4, svfloat64x4_t) + (pub, svint64_t, 4, svint64x4_t) + (pub, svuint64_t, 4, svuint64x4_t) +} + +impl_sign_conversions! { + (i8, u8) + (i16, u16) + (i32, u32) + (i64, u64) + (*const i8, *const u8) + (*const i16, *const u16) + (*const i32, *const u32) + (*const i64, *const u64) + (*mut i8, *mut u8) + (*mut i16, *mut u16) + (*mut i32, *mut u32) + (*mut i64, *mut u64) +} + +impl_sign_conversions_sv! { + (svint8_t, svuint8_t) + (svint16_t, svuint16_t) + (svint32_t, svuint32_t) + (svint64_t, svuint64_t) + + (svint8x2_t, svuint8x2_t) + (svint16x2_t, svuint16x2_t) + (svint32x2_t, svuint32x2_t) + (svint64x2_t, svuint64x2_t) + + (svint8x3_t, svuint8x3_t) + (svint16x3_t, svuint16x3_t) + (svint32x3_t, svuint32x3_t) + (svint64x3_t, svuint64x3_t) + + (svint8x4_t, svuint8x4_t) + (svint16x4_t, svuint16x4_t) + (svint32x4_t, svuint32x4_t) + (svint64x4_t, svuint64x4_t) + + // Internal types: + (nxv2i8, nxv2u8) + (nxv4i8, nxv4u8) + (nxv8i8, nxv8u8) + + (nxv2i16, nxv2u16) + (nxv4i16, nxv4u16) + + (nxv2i32, nxv2u32) +} + +impl_internal_sve_predicate! { + (svbool2_t, 2) + (svbool4_t, 4) + (svbool8_t, 8) +} + +/// Patterns returned by a `PTRUE` +#[repr(i32)] +#[allow(non_camel_case_types)] +#[derive(Clone, Copy, Debug, PartialEq, Eq, ConstParamTy)] +#[non_exhaustive] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub enum svpattern { + /// Activate the largest power-of-two number of elements that is less than the vector length + SV_POW2 = 0, + /// Activate the first element + SV_VL1 = 1, + /// Activate the first two elements + SV_VL2 = 2, + /// Activate the first three elements + SV_VL3 = 3, + /// Activate the first four elements + SV_VL4 = 4, + /// Activate the first five elements + SV_VL5 = 5, + /// Activate the first six elements + SV_VL6 = 6, + /// Activate the first seven elements + SV_VL7 = 7, + /// Activate the first eight elements + SV_VL8 = 8, + /// Activate the first sixteen elements + SV_VL16 = 9, + /// Activate the first thirty-two elements + SV_VL32 = 10, + /// Activate the first sixty-four elements + SV_VL64 = 11, + /// Activate the first one-hundred-and-twenty-eight elements + SV_VL128 = 12, + /// Activate the first two-hundred-and-fifty-six elements + SV_VL256 = 13, + /// Activate the largest multiple-of-four number of elements that is less than the vector length + SV_MUL4 = 29, + /// Activate the largest multiple-of-three number of elements that is less than the vector + /// length + SV_MUL3 = 30, + /// Activate all elements + SV_ALL = 31, +} + +/// Addressing mode for prefetch intrinsics - allows the specification of the expected access +/// kind (read or write), the cache level to load the data, the data retention policy +/// (temporal or streaming) +#[repr(i32)] +#[allow(non_camel_case_types)] +#[derive(Clone, Copy, Debug, PartialEq, Eq, ConstParamTy)] +#[non_exhaustive] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub enum svprfop { + /// Temporal fetch of the addressed location for reading to the L1 cache (i.e. allocate in + /// cache normally) + SV_PLDL1KEEP = 0, + /// Streaming fetch of the addressed location for reading to the L1 cache (i.e. memory only + /// used once) + SV_PLDL1STRM = 1, + /// Temporal fetch of the addressed location for reading to the L2 cache (i.e. allocate in + /// cache normally) + SV_PLDL2KEEP = 2, + /// Streaming fetch of the addressed location for reading to the L2 cache (i.e. memory only + /// used once) + SV_PLDL2STRM = 3, + /// Temporal fetch of the addressed location for reading to the L3 cache (i.e. allocate in + /// cache normally) + SV_PLDL3KEEP = 4, + /// Streaming fetch of the addressed location for reading to the L3 cache (i.e. memory only + /// used once) + SV_PLDL3STRM = 5, + /// Temporal fetch of the addressed location for writing to the L1 cache (i.e. allocate in + /// cache normally) + SV_PSTL1KEEP = 8, + /// Temporal fetch of the addressed location for writing to the L1 cache (i.e. memory only + /// used once) + SV_PSTL1STRM = 9, + /// Temporal fetch of the addressed location for writing to the L2 cache (i.e. allocate in + /// cache normally) + SV_PSTL2KEEP = 10, + /// Temporal fetch of the addressed location for writing to the L2 cache (i.e. memory only + /// used once) + SV_PSTL2STRM = 11, + /// Temporal fetch of the addressed location for writing to the L3 cache (i.e. allocate in + /// cache normally) + SV_PSTL3KEEP = 12, + /// Temporal fetch of the addressed location for writing to the L3 cache (i.e. memory only + /// used once) + SV_PSTL3STRM = 13, +} + +#[cfg(test)] +#[path = "ld_st_tests_aarch64.rs"] +mod ld_st_tests; diff --git a/library/stdarch/crates/core_arch/src/aarch64/sve2/generated.rs b/library/stdarch/crates/core_arch/src/aarch64/sve2/generated.rs new file mode 100644 index 0000000000000..e11c20e5dd07d --- /dev/null +++ b/library/stdarch/crates/core_arch/src/aarch64/sve2/generated.rs @@ -0,0 +1,23881 @@ +// This code is automatically generated. DO NOT MODIFY. +// +// Instead, modify `crates/stdarch-gen-arm/spec/` and run the following command to re-generate this file: +// +// ``` +// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec +// ``` +#![allow(improper_ctypes)] + +#[cfg(test)] +use stdarch_test::assert_instr; + +use super::*; + +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saba.nxv16i8")] + fn _svaba_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svaba_s8(op1, op2, op3) } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svaba_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saba.nxv8i16")] + fn _svaba_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svaba_s16(op1, op2, op3) } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svaba_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saba.nxv4i32")] + fn _svaba_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svaba_s32(op1, op2, op3) } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svaba_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saba.nxv2i64")] + fn _svaba_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svaba_s64(op1, op2, op3) } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svaba_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaba.nxv16i8")] + fn _svaba_u8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svaba_u8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svaba_u8(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaba.nxv8i16")] + fn _svaba_u16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svaba_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svaba_u16(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaba.nxv4i32")] + fn _svaba_u32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svaba_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svaba_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaba.nxv2i64")] + fn _svaba_u64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svaba_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svaba_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalb))] +pub fn svabalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalb.nxv8i16")] + fn _svabalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svabalb_s16(op1, op2, op3) } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalb))] +pub fn svabalb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svabalb_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalb))] +pub fn svabalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalb.nxv4i32")] + fn _svabalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svabalb_s32(op1, op2, op3) } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalb))] +pub fn svabalb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svabalb_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalb))] +pub fn svabalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalb.nxv2i64")] + fn _svabalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svabalb_s64(op1, op2, op3) } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalb))] +pub fn svabalb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svabalb_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalb))] +pub fn svabalb_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalb.nxv8i16")] + fn _svabalb_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svabalb_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalb))] +pub fn svabalb_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t { + svabalb_u16(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalb))] +pub fn svabalb_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalb.nxv4i32")] + fn _svabalb_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svabalb_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalb))] +pub fn svabalb_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t { + svabalb_u32(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalb))] +pub fn svabalb_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalb.nxv2i64")] + fn _svabalb_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svabalb_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalb))] +pub fn svabalb_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t { + svabalb_u64(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalt))] +pub fn svabalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalt.nxv8i16")] + fn _svabalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svabalt_s16(op1, op2, op3) } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalt))] +pub fn svabalt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svabalt_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalt))] +pub fn svabalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalt.nxv4i32")] + fn _svabalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svabalt_s32(op1, op2, op3) } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalt))] +pub fn svabalt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svabalt_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalt))] +pub fn svabalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalt.nxv2i64")] + fn _svabalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svabalt_s64(op1, op2, op3) } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalt))] +pub fn svabalt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svabalt_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalt))] +pub fn svabalt_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalt.nxv8i16")] + fn _svabalt_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svabalt_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalt))] +pub fn svabalt_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t { + svabalt_u16(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalt))] +pub fn svabalt_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalt.nxv4i32")] + fn _svabalt_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svabalt_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalt))] +pub fn svabalt_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t { + svabalt_u32(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalt))] +pub fn svabalt_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalt.nxv2i64")] + fn _svabalt_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svabalt_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalt))] +pub fn svabalt_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t { + svabalt_u64(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlb))] +pub fn svabdlb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlb.nxv8i16")] + fn _svabdlb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svabdlb_s16(op1, op2) } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlb))] +pub fn svabdlb_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svabdlb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlb))] +pub fn svabdlb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlb.nxv4i32")] + fn _svabdlb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svabdlb_s32(op1, op2) } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlb))] +pub fn svabdlb_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svabdlb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlb))] +pub fn svabdlb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlb.nxv2i64")] + fn _svabdlb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svabdlb_s64(op1, op2) } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlb))] +pub fn svabdlb_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svabdlb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlb))] +pub fn svabdlb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlb.nxv8i16")] + fn _svabdlb_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svabdlb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlb))] +pub fn svabdlb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svabdlb_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlb))] +pub fn svabdlb_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlb.nxv4i32")] + fn _svabdlb_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svabdlb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlb))] +pub fn svabdlb_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svabdlb_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlb))] +pub fn svabdlb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlb.nxv2i64")] + fn _svabdlb_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svabdlb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlb))] +pub fn svabdlb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svabdlb_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlt))] +pub fn svabdlt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlt.nxv8i16")] + fn _svabdlt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svabdlt_s16(op1, op2) } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlt))] +pub fn svabdlt_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svabdlt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlt))] +pub fn svabdlt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlt.nxv4i32")] + fn _svabdlt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svabdlt_s32(op1, op2) } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlt))] +pub fn svabdlt_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svabdlt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlt))] +pub fn svabdlt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlt.nxv2i64")] + fn _svabdlt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svabdlt_s64(op1, op2) } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlt))] +pub fn svabdlt_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svabdlt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlt))] +pub fn svabdlt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlt.nxv8i16")] + fn _svabdlt_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svabdlt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlt))] +pub fn svabdlt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svabdlt_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlt))] +pub fn svabdlt_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlt.nxv4i32")] + fn _svabdlt_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svabdlt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlt))] +pub fn svabdlt_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svabdlt_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlt))] +pub fn svabdlt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlt.nxv2i64")] + fn _svabdlt_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svabdlt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlt))] +pub fn svabdlt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svabdlt_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s16_m(pg: svbool_t, op1: svint16_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sadalp.nxv8i16")] + fn _svadalp_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svadalp_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s16_x(pg: svbool_t, op1: svint16_t, op2: svint8_t) -> svint16_t { + svadalp_s16_m(pg, op1, op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s16_z(pg: svbool_t, op1: svint16_t, op2: svint8_t) -> svint16_t { + svadalp_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s32_m(pg: svbool_t, op1: svint32_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sadalp.nxv4i32")] + fn _svadalp_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svadalp_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s32_x(pg: svbool_t, op1: svint32_t, op2: svint16_t) -> svint32_t { + svadalp_s32_m(pg, op1, op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s32_z(pg: svbool_t, op1: svint32_t, op2: svint16_t) -> svint32_t { + svadalp_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s64_m(pg: svbool_t, op1: svint64_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sadalp.nxv2i64")] + fn _svadalp_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svadalp_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s64_x(pg: svbool_t, op1: svint64_t, op2: svint32_t) -> svint64_t { + svadalp_s64_m(pg, op1, op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s64_z(pg: svbool_t, op1: svint64_t, op2: svint32_t) -> svint64_t { + svadalp_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uadalp.nxv8i16")] + fn _svadalp_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svadalp_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint8_t) -> svuint16_t { + svadalp_u16_m(pg, op1, op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint8_t) -> svuint16_t { + svadalp_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uadalp.nxv4i32")] + fn _svadalp_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svadalp_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint16_t) -> svuint32_t { + svadalp_u32_m(pg, op1, op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint16_t) -> svuint32_t { + svadalp_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uadalp.nxv2i64")] + fn _svadalp_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svadalp_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint32_t) -> svuint64_t { + svadalp_u64_m(pg, op1, op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint32_t) -> svuint64_t { + svadalp_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Add with carry long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclb))] +pub fn svadclb_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adclb.nxv4i32")] + fn _svadclb_u32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svadclb_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Add with carry long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclb))] +pub fn svadclb_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svadclb_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Add with carry long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclb))] +pub fn svadclb_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adclb.nxv2i64")] + fn _svadclb_u64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svadclb_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Add with carry long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclb))] +pub fn svadclb_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svadclb_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Add with carry long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclt))] +pub fn svadclt_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adclt.nxv4i32")] + fn _svadclt_u32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svadclt_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Add with carry long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclt))] +pub fn svadclt_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svadclt_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Add with carry long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclt))] +pub fn svadclt_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adclt.nxv2i64")] + fn _svadclt_u64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svadclt_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Add with carry long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclt))] +pub fn svadclt_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svadclt_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnb.nxv8i16")] + fn _svaddhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svaddhnb_s16(op1, op2) } +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_n_s16(op1: svint16_t, op2: i16) -> svint8_t { + svaddhnb_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnb.nxv4i32")] + fn _svaddhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svaddhnb_s32(op1, op2) } +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_n_s32(op1: svint32_t, op2: i32) -> svint16_t { + svaddhnb_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnb.nxv2i64")] + fn _svaddhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svaddhnb_s64(op1, op2) } +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_n_s64(op1: svint64_t, op2: i64) -> svint32_t { + svaddhnb_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_u16(op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svaddhnb_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_n_u16(op1: svuint16_t, op2: u16) -> svuint8_t { + svaddhnb_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_u32(op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svaddhnb_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_n_u32(op1: svuint32_t, op2: u32) -> svuint16_t { + svaddhnb_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_u64(op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svaddhnb_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_n_u64(op1: svuint64_t, op2: u64) -> svuint32_t { + svaddhnb_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnt.nxv8i16")] + fn _svaddhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svaddhnt_s16(even, op1, op2) } +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_n_s16(even: svint8_t, op1: svint16_t, op2: i16) -> svint8_t { + svaddhnt_s16(even, op1, svdup_n_s16(op2)) +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnt.nxv4i32")] + fn _svaddhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svaddhnt_s32(even, op1, op2) } +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_n_s32(even: svint16_t, op1: svint32_t, op2: i32) -> svint16_t { + svaddhnt_s32(even, op1, svdup_n_s32(op2)) +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnt.nxv2i64")] + fn _svaddhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svaddhnt_s64(even, op1, op2) } +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_n_s64(even: svint32_t, op1: svint64_t, op2: i64) -> svint32_t { + svaddhnt_s64(even, op1, svdup_n_s64(op2)) +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_u16(even: svuint8_t, op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svaddhnt_s16(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_n_u16(even: svuint8_t, op1: svuint16_t, op2: u16) -> svuint8_t { + svaddhnt_u16(even, op1, svdup_n_u16(op2)) +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_u32(even: svuint16_t, op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svaddhnt_s32(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_n_u32(even: svuint16_t, op1: svuint32_t, op2: u32) -> svuint16_t { + svaddhnt_u32(even, op1, svdup_n_u32(op2)) +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_u64(even: svuint32_t, op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svaddhnt_s64(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_n_u64(even: svuint32_t, op1: svuint64_t, op2: u64) -> svuint32_t { + svaddhnt_u64(even, op1, svdup_n_u64(op2)) +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlb))] +pub fn svaddlb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlb.nxv8i16")] + fn _svaddlb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddlb_s16(op1, op2) } +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlb))] +pub fn svaddlb_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svaddlb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlb))] +pub fn svaddlb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlb.nxv4i32")] + fn _svaddlb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddlb_s32(op1, op2) } +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlb))] +pub fn svaddlb_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svaddlb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlb))] +pub fn svaddlb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlb.nxv2i64")] + fn _svaddlb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddlb_s64(op1, op2) } +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlb))] +pub fn svaddlb_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svaddlb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlb))] +pub fn svaddlb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlb.nxv8i16")] + fn _svaddlb_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddlb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlb))] +pub fn svaddlb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svaddlb_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlb))] +pub fn svaddlb_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlb.nxv4i32")] + fn _svaddlb_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddlb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlb))] +pub fn svaddlb_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svaddlb_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlb))] +pub fn svaddlb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlb.nxv2i64")] + fn _svaddlb_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddlb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlb))] +pub fn svaddlb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svaddlb_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Add long (bottom + top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlbt))] +pub fn svaddlbt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.saddlbt.nxv8i16" + )] + fn _svaddlbt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddlbt_s16(op1, op2) } +} +#[doc = "Add long (bottom + top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlbt))] +pub fn svaddlbt_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svaddlbt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Add long (bottom + top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlbt))] +pub fn svaddlbt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.saddlbt.nxv4i32" + )] + fn _svaddlbt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddlbt_s32(op1, op2) } +} +#[doc = "Add long (bottom + top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlbt))] +pub fn svaddlbt_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svaddlbt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Add long (bottom + top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlbt))] +pub fn svaddlbt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.saddlbt.nxv2i64" + )] + fn _svaddlbt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddlbt_s64(op1, op2) } +} +#[doc = "Add long (bottom + top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlbt))] +pub fn svaddlbt_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svaddlbt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlt))] +pub fn svaddlt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlt.nxv8i16")] + fn _svaddlt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddlt_s16(op1, op2) } +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlt))] +pub fn svaddlt_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svaddlt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlt))] +pub fn svaddlt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlt.nxv4i32")] + fn _svaddlt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddlt_s32(op1, op2) } +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlt))] +pub fn svaddlt_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svaddlt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlt))] +pub fn svaddlt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlt.nxv2i64")] + fn _svaddlt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddlt_s64(op1, op2) } +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlt))] +pub fn svaddlt_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svaddlt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlt))] +pub fn svaddlt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlt.nxv8i16")] + fn _svaddlt_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddlt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlt))] +pub fn svaddlt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svaddlt_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlt))] +pub fn svaddlt_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlt.nxv4i32")] + fn _svaddlt_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddlt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlt))] +pub fn svaddlt_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svaddlt_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlt))] +pub fn svaddlt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlt.nxv2i64")] + fn _svaddlt_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddlt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlt))] +pub fn svaddlt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svaddlt_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(faddp))] +pub fn svaddp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.faddp.nxv4f32")] + fn _svaddp_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svaddp_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(faddp))] +pub fn svaddp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svaddp_f32_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(faddp))] +pub fn svaddp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.faddp.nxv2f64")] + fn _svaddp_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svaddp_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(faddp))] +pub fn svaddp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svaddp_f64_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addp.nxv16i8")] + fn _svaddp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svaddp_s8_m(pg, op1, op2) } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svaddp_s8_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addp.nxv8i16")] + fn _svaddp_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svaddp_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svaddp_s16_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addp.nxv4i32")] + fn _svaddp_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svaddp_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svaddp_s32_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addp.nxv2i64")] + fn _svaddp_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svaddp_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svaddp_s64_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svaddp_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svaddp_u8_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svaddp_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svaddp_u16_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svaddp_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svaddp_u32_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svaddp_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svaddp_u64_m(pg, op1, op2) +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwb))] +pub fn svaddwb_s16(op1: svint16_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwb.nxv8i16")] + fn _svaddwb_s16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddwb_s16(op1, op2) } +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwb))] +pub fn svaddwb_n_s16(op1: svint16_t, op2: i8) -> svint16_t { + svaddwb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwb))] +pub fn svaddwb_s32(op1: svint32_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwb.nxv4i32")] + fn _svaddwb_s32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddwb_s32(op1, op2) } +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwb))] +pub fn svaddwb_n_s32(op1: svint32_t, op2: i16) -> svint32_t { + svaddwb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwb))] +pub fn svaddwb_s64(op1: svint64_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwb.nxv2i64")] + fn _svaddwb_s64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddwb_s64(op1, op2) } +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwb))] +pub fn svaddwb_n_s64(op1: svint64_t, op2: i32) -> svint64_t { + svaddwb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwb))] +pub fn svaddwb_u16(op1: svuint16_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwb.nxv8i16")] + fn _svaddwb_u16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddwb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwb))] +pub fn svaddwb_n_u16(op1: svuint16_t, op2: u8) -> svuint16_t { + svaddwb_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwb))] +pub fn svaddwb_u32(op1: svuint32_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwb.nxv4i32")] + fn _svaddwb_u32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddwb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwb))] +pub fn svaddwb_n_u32(op1: svuint32_t, op2: u16) -> svuint32_t { + svaddwb_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwb))] +pub fn svaddwb_u64(op1: svuint64_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwb.nxv2i64")] + fn _svaddwb_u64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddwb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwb))] +pub fn svaddwb_n_u64(op1: svuint64_t, op2: u32) -> svuint64_t { + svaddwb_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwt))] +pub fn svaddwt_s16(op1: svint16_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwt.nxv8i16")] + fn _svaddwt_s16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddwt_s16(op1, op2) } +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwt))] +pub fn svaddwt_n_s16(op1: svint16_t, op2: i8) -> svint16_t { + svaddwt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwt))] +pub fn svaddwt_s32(op1: svint32_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwt.nxv4i32")] + fn _svaddwt_s32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddwt_s32(op1, op2) } +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwt))] +pub fn svaddwt_n_s32(op1: svint32_t, op2: i16) -> svint32_t { + svaddwt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwt))] +pub fn svaddwt_s64(op1: svint64_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwt.nxv2i64")] + fn _svaddwt_s64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddwt_s64(op1, op2) } +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwt))] +pub fn svaddwt_n_s64(op1: svint64_t, op2: i32) -> svint64_t { + svaddwt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwt))] +pub fn svaddwt_u16(op1: svuint16_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwt.nxv8i16")] + fn _svaddwt_u16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddwt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwt))] +pub fn svaddwt_n_u16(op1: svuint16_t, op2: u8) -> svuint16_t { + svaddwt_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwt))] +pub fn svaddwt_u32(op1: svuint32_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwt.nxv4i32")] + fn _svaddwt_u32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddwt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwt))] +pub fn svaddwt_n_u32(op1: svuint32_t, op2: u16) -> svuint32_t { + svaddwt_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwt))] +pub fn svaddwt_u64(op1: svuint64_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwt.nxv2i64")] + fn _svaddwt_u64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddwt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwt))] +pub fn svaddwt_n_u64(op1: svuint64_t, op2: u32) -> svuint64_t { + svaddwt_u64(op1, svdup_n_u32(op2)) +} +#[doc = "AES single round decryption"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaesd[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(aesd))] +pub fn svaesd_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.aesd")] + fn _svaesd_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svaesd_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "AES single round encryption"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaese[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(aese))] +pub fn svaese_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.aese")] + fn _svaese_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svaese_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "AES inverse mix columns"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaesimc[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(aesimc))] +pub fn svaesimc_u8(op: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.aesimc")] + fn _svaesimc_u8(op: svint8_t) -> svint8_t; + } + unsafe { _svaesimc_u8(op.as_signed()).as_unsigned() } +} +#[doc = "AES mix columns"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaesmc[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(aesmc))] +pub fn svaesmc_u8(op: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.aesmc")] + fn _svaesmc_u8(op: svint8_t) -> svint8_t; + } + unsafe { _svaesmc_u8(op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bcax.nxv16i8")] + fn _svbcax_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svbcax_s8(op1, op2, op3) } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svbcax_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bcax.nxv8i16")] + fn _svbcax_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svbcax_s16(op1, op2, op3) } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svbcax_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bcax.nxv4i32")] + fn _svbcax_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svbcax_s32(op1, op2, op3) } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svbcax_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bcax.nxv2i64")] + fn _svbcax_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svbcax_s64(op1, op2, op3) } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svbcax_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svbcax_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svbcax_u8(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svbcax_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svbcax_u16(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svbcax_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svbcax_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svbcax_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svbcax_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bdep.x.nxv16i8")] + fn _svbdep_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svbdep_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svbdep_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bdep.x.nxv8i16")] + fn _svbdep_u16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svbdep_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t { + svbdep_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bdep.x.nxv4i32")] + fn _svbdep_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svbdep_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + svbdep_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bdep.x.nxv2i64")] + fn _svbdep_u64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svbdep_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + svbdep_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bext.x.nxv16i8")] + fn _svbext_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svbext_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svbext_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bext.x.nxv8i16")] + fn _svbext_u16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svbext_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t { + svbext_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bext.x.nxv4i32")] + fn _svbext_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svbext_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + svbext_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bext.x.nxv2i64")] + fn _svbext_u64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svbext_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + svbext_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bgrp.x.nxv16i8")] + fn _svbgrp_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svbgrp_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svbgrp_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bgrp.x.nxv8i16")] + fn _svbgrp_u16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svbgrp_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t { + svbgrp_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bgrp.x.nxv4i32")] + fn _svbgrp_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svbgrp_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + svbgrp_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bgrp.x.nxv2i64")] + fn _svbgrp_u64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svbgrp_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + svbgrp_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl1n.nxv16i8")] + fn _svbsl1n_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svbsl1n_s8(op1, op2, op3) } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svbsl1n_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl1n.nxv8i16")] + fn _svbsl1n_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svbsl1n_s16(op1, op2, op3) } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svbsl1n_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl1n.nxv4i32")] + fn _svbsl1n_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svbsl1n_s32(op1, op2, op3) } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svbsl1n_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl1n.nxv2i64")] + fn _svbsl1n_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svbsl1n_s64(op1, op2, op3) } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svbsl1n_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svbsl1n_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svbsl1n_u8(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svbsl1n_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svbsl1n_u16(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svbsl1n_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svbsl1n_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svbsl1n_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svbsl1n_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl2n.nxv16i8")] + fn _svbsl2n_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svbsl2n_s8(op1, op2, op3) } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svbsl2n_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl2n.nxv8i16")] + fn _svbsl2n_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svbsl2n_s16(op1, op2, op3) } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svbsl2n_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl2n.nxv4i32")] + fn _svbsl2n_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svbsl2n_s32(op1, op2, op3) } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svbsl2n_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl2n.nxv2i64")] + fn _svbsl2n_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svbsl2n_s64(op1, op2, op3) } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svbsl2n_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svbsl2n_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svbsl2n_u8(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svbsl2n_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svbsl2n_u16(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svbsl2n_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svbsl2n_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svbsl2n_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svbsl2n_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl.nxv16i8")] + fn _svbsl_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svbsl_s8(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svbsl_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl.nxv8i16")] + fn _svbsl_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svbsl_s16(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svbsl_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl.nxv4i32")] + fn _svbsl_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svbsl_s32(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svbsl_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl.nxv2i64")] + fn _svbsl_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svbsl_s64(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svbsl_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svbsl_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svbsl_u8(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svbsl_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svbsl_u16(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svbsl_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svbsl_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svbsl_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svbsl_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cadd.x.nxv16i8")] + fn _svcadd_s8(op1: svint8_t, op2: svint8_t, imm_rotation: i32) -> svint8_t; + } + unsafe { _svcadd_s8(op1, op2, IMM_ROTATION) } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cadd.x.nxv8i16")] + fn _svcadd_s16(op1: svint16_t, op2: svint16_t, imm_rotation: i32) -> svint16_t; + } + unsafe { _svcadd_s16(op1, op2, IMM_ROTATION) } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cadd.x.nxv4i32")] + fn _svcadd_s32(op1: svint32_t, op2: svint32_t, imm_rotation: i32) -> svint32_t; + } + unsafe { _svcadd_s32(op1, op2, IMM_ROTATION) } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cadd.x.nxv2i64")] + fn _svcadd_s64(op1: svint64_t, op2: svint64_t, imm_rotation: i32) -> svint64_t; + } + unsafe { _svcadd_s64(op1, op2, IMM_ROTATION) } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe { svcadd_s8::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe { svcadd_s16::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe { svcadd_s32::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe { svcadd_s64::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Complex dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcdot_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cdot, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svcdot_lane_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cdot.lane.nxv4i32" + )] + fn _svcdot_lane_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, + imm_index: i32, + imm_rotation: i32, + ) -> svint32_t; + } + unsafe { _svcdot_lane_s32(op1, op2, op3, IMM_INDEX, IMM_ROTATION) } +} +#[doc = "Complex dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcdot_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cdot, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svcdot_lane_s64( + op1: svint64_t, + op2: svint16_t, + op3: svint16_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cdot.lane.nxv2i64" + )] + fn _svcdot_lane_s64( + op1: svint64_t, + op2: svint16_t, + op3: svint16_t, + imm_index: i32, + imm_rotation: i32, + ) -> svint64_t; + } + unsafe { _svcdot_lane_s64(op1, op2, op3, IMM_INDEX, IMM_ROTATION) } +} +#[doc = "Complex dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcdot[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cdot, IMM_ROTATION = 90))] +pub fn svcdot_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, +) -> svint32_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cdot.nxv4i32")] + fn _svcdot_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, + imm_rotation: i32, + ) -> svint32_t; + } + unsafe { _svcdot_s32(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcdot[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cdot, IMM_ROTATION = 90))] +pub fn svcdot_s64( + op1: svint64_t, + op2: svint16_t, + op3: svint16_t, +) -> svint64_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cdot.nxv2i64")] + fn _svcdot_s64( + op1: svint64_t, + op2: svint16_t, + op3: svint16_t, + imm_rotation: i32, + ) -> svint64_t; + } + unsafe { _svcdot_s64(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svcmla_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=3); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmla.lane.x.nxv8i16" + )] + fn _svcmla_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + imm_index: i32, + imm_rotation: i32, + ) -> svint16_t; + } + unsafe { _svcmla_lane_s16(op1, op2, op3, IMM_INDEX, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svcmla_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=1); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmla.lane.x.nxv4i32" + )] + fn _svcmla_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + imm_index: i32, + imm_rotation: i32, + ) -> svint32_t; + } + unsafe { _svcmla_lane_s32(op1, op2, op3, IMM_INDEX, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svcmla_lane_u16( + op1: svuint16_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint16_t { + static_assert_range!(IMM_INDEX, 0..=3); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe { + svcmla_lane_s16::( + op1.as_signed(), + op2.as_signed(), + op3.as_signed(), + ) + .as_unsigned() + } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svcmla_lane_u32( + op1: svuint32_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=1); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe { + svcmla_lane_s32::( + op1.as_signed(), + op2.as_signed(), + op3.as_signed(), + ) + .as_unsigned() + } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmla.x.nxv16i8")] + fn _svcmla_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t, imm_rotation: i32) -> svint8_t; + } + unsafe { _svcmla_s8(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmla.x.nxv8i16")] + fn _svcmla_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + imm_rotation: i32, + ) -> svint16_t; + } + unsafe { _svcmla_s16(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmla.x.nxv4i32")] + fn _svcmla_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + imm_rotation: i32, + ) -> svint32_t; + } + unsafe { _svcmla_s32(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, +) -> svint64_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmla.x.nxv2i64")] + fn _svcmla_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, + imm_rotation: i32, + ) -> svint64_t; + } + unsafe { _svcmla_s64(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_u8( + op1: svuint8_t, + op2: svuint8_t, + op3: svuint8_t, +) -> svuint8_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe { + svcmla_s8::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_u16( + op1: svuint16_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint16_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe { + svcmla_s16::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_u32( + op1: svuint32_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint32_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe { + svcmla_s32::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_u64( + op1: svuint64_t, + op2: svuint64_t, + op3: svuint64_t, +) -> svuint64_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe { + svcmla_s64::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Up convert long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtlt_f64[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtlt))] +pub fn svcvtlt_f64_f32_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat32_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtlt.f64f32")] + fn _svcvtlt_f64_f32_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat32_t) + -> svfloat64_t; + } + unsafe { _svcvtlt_f64_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Up convert long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtlt_f64[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtlt))] +pub fn svcvtlt_f64_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat64_t { + unsafe { svcvtlt_f64_f32_m(crate::intrinsics::transmute_unchecked(op), pg, op) } +} +#[doc = "Down convert and narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtnt_f32[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtnt))] +pub fn svcvtnt_f32_f64_m(even: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtnt.f32f64")] + fn _svcvtnt_f32_f64_m(even: svfloat32_t, pg: svbool2_t, op: svfloat64_t) -> svfloat32_t; + } + unsafe { _svcvtnt_f32_f64_m(even, pg.sve_into(), op) } +} +#[doc = "Down convert and narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtnt_f32[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtnt))] +pub fn svcvtnt_f32_f64_x(even: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + svcvtnt_f32_f64_m(even, pg, op) +} +#[doc = "Down convert, rounding to odd"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtx_f32[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtx))] +pub fn svcvtx_f32_f64_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtx.f32f64")] + fn _svcvtx_f32_f64_m(inactive: svfloat32_t, pg: svbool2_t, op: svfloat64_t) -> svfloat32_t; + } + unsafe { _svcvtx_f32_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Down convert, rounding to odd"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtx_f32[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtx))] +pub fn svcvtx_f32_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + unsafe { svcvtx_f32_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Down convert, rounding to odd"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtx_f32[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtx))] +pub fn svcvtx_f32_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + svcvtx_f32_f64_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Down convert, rounding to odd (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtxnt_f32[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtxnt))] +pub fn svcvtxnt_f32_f64_m(even: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtxnt.f32f64")] + fn _svcvtxnt_f32_f64_m(even: svfloat32_t, pg: svbool2_t, op: svfloat64_t) -> svfloat32_t; + } + unsafe { _svcvtxnt_f32_f64_m(even, pg.sve_into(), op) } +} +#[doc = "Down convert, rounding to odd (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtxnt_f32[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtxnt))] +pub fn svcvtxnt_f32_f64_x(even: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + svcvtxnt_f32_f64_m(even, pg, op) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor3.nxv16i8")] + fn _sveor3_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _sveor3_s8(op1, op2, op3) } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + sveor3_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor3.nxv8i16")] + fn _sveor3_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _sveor3_s16(op1, op2, op3) } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + sveor3_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor3.nxv4i32")] + fn _sveor3_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _sveor3_s32(op1, op2, op3) } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + sveor3_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor3.nxv2i64")] + fn _sveor3_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _sveor3_s64(op1, op2, op3) } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + sveor3_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { sveor3_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + sveor3_u8(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { sveor3_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + sveor3_u16(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { sveor3_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + sveor3_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { sveor3_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + sveor3_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_s8(odd: svint8_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorbt.nxv16i8")] + fn _sveorbt_s8(odd: svint8_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _sveorbt_s8(odd, op1, op2) } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_s8(odd: svint8_t, op1: svint8_t, op2: i8) -> svint8_t { + sveorbt_s8(odd, op1, svdup_n_s8(op2)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_s16(odd: svint16_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorbt.nxv8i16")] + fn _sveorbt_s16(odd: svint16_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _sveorbt_s16(odd, op1, op2) } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_s16(odd: svint16_t, op1: svint16_t, op2: i16) -> svint16_t { + sveorbt_s16(odd, op1, svdup_n_s16(op2)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_s32(odd: svint32_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorbt.nxv4i32")] + fn _sveorbt_s32(odd: svint32_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _sveorbt_s32(odd, op1, op2) } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_s32(odd: svint32_t, op1: svint32_t, op2: i32) -> svint32_t { + sveorbt_s32(odd, op1, svdup_n_s32(op2)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_s64(odd: svint64_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorbt.nxv2i64")] + fn _sveorbt_s64(odd: svint64_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _sveorbt_s64(odd, op1, op2) } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_s64(odd: svint64_t, op1: svint64_t, op2: i64) -> svint64_t { + sveorbt_s64(odd, op1, svdup_n_s64(op2)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_u8(odd: svuint8_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { sveorbt_s8(odd.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_u8(odd: svuint8_t, op1: svuint8_t, op2: u8) -> svuint8_t { + sveorbt_u8(odd, op1, svdup_n_u8(op2)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_u16(odd: svuint16_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { sveorbt_s16(odd.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_u16(odd: svuint16_t, op1: svuint16_t, op2: u16) -> svuint16_t { + sveorbt_u16(odd, op1, svdup_n_u16(op2)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_u32(odd: svuint32_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { sveorbt_s32(odd.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_u32(odd: svuint32_t, op1: svuint32_t, op2: u32) -> svuint32_t { + sveorbt_u32(odd, op1, svdup_n_u32(op2)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_u64(odd: svuint64_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { sveorbt_s64(odd.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_u64(odd: svuint64_t, op1: svuint64_t, op2: u64) -> svuint64_t { + sveorbt_u64(odd, op1, svdup_n_u64(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_s8(even: svint8_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eortb.nxv16i8")] + fn _sveortb_s8(even: svint8_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _sveortb_s8(even, op1, op2) } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_s8(even: svint8_t, op1: svint8_t, op2: i8) -> svint8_t { + sveortb_s8(even, op1, svdup_n_s8(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_s16(even: svint16_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eortb.nxv8i16")] + fn _sveortb_s16(even: svint16_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _sveortb_s16(even, op1, op2) } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_s16(even: svint16_t, op1: svint16_t, op2: i16) -> svint16_t { + sveortb_s16(even, op1, svdup_n_s16(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_s32(even: svint32_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eortb.nxv4i32")] + fn _sveortb_s32(even: svint32_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _sveortb_s32(even, op1, op2) } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_s32(even: svint32_t, op1: svint32_t, op2: i32) -> svint32_t { + sveortb_s32(even, op1, svdup_n_s32(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_s64(even: svint64_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eortb.nxv2i64")] + fn _sveortb_s64(even: svint64_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _sveortb_s64(even, op1, op2) } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_s64(even: svint64_t, op1: svint64_t, op2: i64) -> svint64_t { + sveortb_s64(even, op1, svdup_n_s64(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_u8(even: svuint8_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { sveortb_s8(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_u8(even: svuint8_t, op1: svuint8_t, op2: u8) -> svuint8_t { + sveortb_u8(even, op1, svdup_n_u8(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_u16(even: svuint16_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { sveortb_s16(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_u16(even: svuint16_t, op1: svuint16_t, op2: u16) -> svuint16_t { + sveortb_u16(even, op1, svdup_n_u16(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_u32(even: svuint32_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { sveortb_s32(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_u32(even: svuint32_t, op1: svuint32_t, op2: u32) -> svuint32_t { + sveortb_u32(even, op1, svdup_n_u32(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_u64(even: svuint64_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { sveortb_s64(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_u64(even: svuint64_t, op1: svuint64_t, op2: u64) -> svuint64_t { + sveortb_u64(even, op1, svdup_n_u64(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shadd.nxv16i8")] + fn _svhadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svhadd_s8_m(pg, op1, op2) } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhadd_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svhadd_s8_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhadd_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svhadd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhadd_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shadd.nxv8i16")] + fn _svhadd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svhadd_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhadd_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svhadd_s16_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhadd_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svhadd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhadd_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shadd.nxv4i32")] + fn _svhadd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svhadd_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhadd_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svhadd_s32_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhadd_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svhadd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhadd_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shadd.nxv2i64")] + fn _svhadd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svhadd_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhadd_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svhadd_s64_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhadd_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svhadd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhadd_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhadd.nxv16i8")] + fn _svhadd_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svhadd_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhadd_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svhadd_u8_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhadd_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svhadd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhadd_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhadd.nxv8i16")] + fn _svhadd_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svhadd_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhadd_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svhadd_u16_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhadd_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svhadd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhadd_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhadd.nxv4i32")] + fn _svhadd_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svhadd_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhadd_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svhadd_u32_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhadd_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svhadd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhadd_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhadd.nxv2i64")] + fn _svhadd_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svhadd_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhadd_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svhadd_u64_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhadd_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svhadd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhadd_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Count matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistcnt[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(histcnt))] +pub fn svhistcnt_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.histcnt.nxv4i32" + )] + fn _svhistcnt_s32_z(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svhistcnt_s32_z(pg.sve_into(), op1, op2).as_unsigned() } +} +#[doc = "Count matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistcnt[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(histcnt))] +pub fn svhistcnt_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.histcnt.nxv2i64" + )] + fn _svhistcnt_s64_z(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svhistcnt_s64_z(pg.sve_into(), op1, op2).as_unsigned() } +} +#[doc = "Count matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistcnt[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(histcnt))] +pub fn svhistcnt_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svhistcnt_s32_z(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Count matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistcnt[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(histcnt))] +pub fn svhistcnt_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svhistcnt_s64_z(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Count matching elements in 128-bit segments"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistseg[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(histseg))] +pub fn svhistseg_s8(op1: svint8_t, op2: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.histseg.nxv16i8" + )] + fn _svhistseg_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svhistseg_s8(op1, op2).as_unsigned() } +} +#[doc = "Count matching elements in 128-bit segments"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistseg[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(histseg))] +pub fn svhistseg_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svhistseg_s8(op1.as_signed(), op2.as_signed()) } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsub.nxv16i8")] + fn _svhsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svhsub_s8_m(pg, op1, op2) } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhsub_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svhsub_s8_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhsub_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svhsub_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhsub_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsub.nxv8i16")] + fn _svhsub_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svhsub_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhsub_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svhsub_s16_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhsub_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svhsub_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhsub_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsub.nxv4i32")] + fn _svhsub_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svhsub_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhsub_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svhsub_s32_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhsub_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svhsub_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhsub_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsub.nxv2i64")] + fn _svhsub_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svhsub_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhsub_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svhsub_s64_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhsub_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svhsub_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhsub_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsub.nxv16i8")] + fn _svhsub_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svhsub_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhsub_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svhsub_u8_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhsub_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svhsub_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhsub_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsub.nxv8i16")] + fn _svhsub_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svhsub_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhsub_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svhsub_u16_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhsub_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svhsub_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhsub_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsub.nxv4i32")] + fn _svhsub_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svhsub_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhsub_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svhsub_u32_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhsub_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svhsub_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhsub_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsub.nxv2i64")] + fn _svhsub_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svhsub_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhsub_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svhsub_u64_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhsub_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svhsub_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhsub_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsubr.nxv16i8")] + fn _svhsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svhsubr_s8_m(pg, op1, op2) } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhsubr_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svhsubr_s8_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhsubr_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svhsubr_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhsubr_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsubr.nxv8i16")] + fn _svhsubr_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svhsubr_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhsubr_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svhsubr_s16_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhsubr_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svhsubr_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhsubr_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsubr.nxv4i32")] + fn _svhsubr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svhsubr_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhsubr_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svhsubr_s32_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhsubr_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svhsubr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhsubr_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsubr.nxv2i64")] + fn _svhsubr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svhsubr_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhsubr_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svhsubr_s64_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhsubr_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svhsubr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhsubr_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsubr.nxv16i8")] + fn _svhsubr_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svhsubr_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhsubr_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svhsubr_u8_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhsubr_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svhsubr_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhsubr_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsubr.nxv8i16")] + fn _svhsubr_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svhsubr_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhsubr_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svhsubr_u16_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhsubr_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svhsubr_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhsubr_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsubr.nxv4i32")] + fn _svhsubr_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svhsubr_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhsubr_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svhsubr_u32_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhsubr_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svhsubr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhsubr_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsubr.nxv2i64")] + fn _svhsubr_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svhsubr_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhsubr_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svhsubr_u64_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhsubr_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svhsubr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhsubr_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_s64index_f64( + pg: svbool_t, + base: *const f64, + indices: svint64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2f64" + )] + fn _svldnt1_gather_s64index_f64( + pg: svbool2_t, + base: *const f64, + indices: svint64_t, + ) -> svfloat64_t; + } + _svldnt1_gather_s64index_f64(pg.sve_into(), base, indices) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_s64index_s64( + pg: svbool_t, + base: *const i64, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2i64" + )] + fn _svldnt1_gather_s64index_s64( + pg: svbool2_t, + base: *const i64, + indices: svint64_t, + ) -> svint64_t; + } + _svldnt1_gather_s64index_s64(pg.sve_into(), base, indices) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_s64index_u64( + pg: svbool_t, + base: *const u64, + indices: svint64_t, +) -> svuint64_t { + svldnt1_gather_s64index_s64(pg, base.as_signed(), indices).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64index_f64( + pg: svbool_t, + base: *const f64, + indices: svuint64_t, +) -> svfloat64_t { + svldnt1_gather_s64index_f64(pg, base, indices.as_signed()) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64index_s64( + pg: svbool_t, + base: *const i64, + indices: svuint64_t, +) -> svint64_t { + svldnt1_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64index_u64( + pg: svbool_t, + base: *const u64, + indices: svuint64_t, +) -> svuint64_t { + svldnt1_gather_s64index_s64(pg, base.as_signed(), indices.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_s64offset_f64( + pg: svbool_t, + base: *const f64, + offsets: svint64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2f64" + )] + fn _svldnt1_gather_s64offset_f64( + pg: svbool2_t, + base: *const f64, + offsets: svint64_t, + ) -> svfloat64_t; + } + _svldnt1_gather_s64offset_f64(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_s64offset_s64( + pg: svbool_t, + base: *const i64, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i64" + )] + fn _svldnt1_gather_s64offset_s64( + pg: svbool2_t, + base: *const i64, + offsets: svint64_t, + ) -> svint64_t; + } + _svldnt1_gather_s64offset_s64(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_s64offset_u64( + pg: svbool_t, + base: *const u64, + offsets: svint64_t, +) -> svuint64_t { + svldnt1_gather_s64offset_s64(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32offset_f32( + pg: svbool_t, + base: *const f32, + offsets: svuint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4f32" + )] + fn _svldnt1_gather_u32offset_f32( + pg: svbool4_t, + base: *const f32, + offsets: svint32_t, + ) -> svfloat32_t; + } + _svldnt1_gather_u32offset_f32(pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32offset_s32( + pg: svbool_t, + base: *const i32, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i32" + )] + fn _svldnt1_gather_u32offset_s32( + pg: svbool4_t, + base: *const i32, + offsets: svint32_t, + ) -> svint32_t; + } + _svldnt1_gather_u32offset_s32(pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32offset_u32( + pg: svbool_t, + base: *const u32, + offsets: svuint32_t, +) -> svuint32_t { + svldnt1_gather_u32offset_s32(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64offset_f64( + pg: svbool_t, + base: *const f64, + offsets: svuint64_t, +) -> svfloat64_t { + svldnt1_gather_s64offset_f64(pg, base, offsets.as_signed()) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64offset_s64( + pg: svbool_t, + base: *const i64, + offsets: svuint64_t, +) -> svint64_t { + svldnt1_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64offset_u64( + pg: svbool_t, + base: *const u64, + offsets: svuint64_t, +) -> svuint64_t { + svldnt1_gather_s64offset_s64(pg, base.as_signed(), offsets.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_f32(pg: svbool_t, bases: svuint32_t) -> svfloat32_t { + svldnt1_gather_u32base_offset_f32(pg, bases, 0) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldnt1_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldnt1_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_f64(pg: svbool_t, bases: svuint64_t) -> svfloat64_t { + svldnt1_gather_u64base_offset_f64(pg, bases, 0) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldnt1_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldnt1_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_index_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_index_f32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svfloat32_t { + svldnt1_gather_u32base_offset_f32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svldnt1_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svldnt1_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_index_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_index_f64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svfloat64_t { + svldnt1_gather_u64base_offset_f64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldnt1_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldnt1_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_offset_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_offset_f32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4f32.nxv4i32" + )] + fn _svldnt1_gather_u32base_offset_f32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> svfloat32_t; + } + _svldnt1_gather_u32base_offset_f32(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i32.nxv4i32" + )] + fn _svldnt1_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> svint32_t; + } + _svldnt1_gather_u32base_offset_s32(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svldnt1_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_offset_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_offset_f64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2f64.nxv2i64" + )] + fn _svldnt1_gather_u64base_offset_f64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> svfloat64_t; + } + _svldnt1_gather_u64base_offset_f64(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i64.nxv2i64" + )] + fn _svldnt1_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> svint64_t; + } + _svldnt1_gather_u64base_offset_s64(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldnt1_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_s64offset_s64( + pg: svbool_t, + base: *const i8, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i8" + )] + fn _svldnt1sb_gather_s64offset_s64( + pg: svbool2_t, + base: *const i8, + offsets: svint64_t, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svldnt1sb_gather_s64offset_s64( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_s64offset_s64( + pg: svbool_t, + base: *const i16, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i16" + )] + fn _svldnt1sh_gather_s64offset_s64( + pg: svbool2_t, + base: *const i16, + offsets: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldnt1sh_gather_s64offset_s64( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_s64offset_s64( + pg: svbool_t, + base: *const i32, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i32" + )] + fn _svldnt1sw_gather_s64offset_s64( + pg: svbool2_t, + base: *const i32, + offsets: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldnt1sw_gather_s64offset_s64( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_s64offset_u64( + pg: svbool_t, + base: *const i8, + offsets: svint64_t, +) -> svuint64_t { + svldnt1sb_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_s64offset_u64( + pg: svbool_t, + base: *const i16, + offsets: svint64_t, +) -> svuint64_t { + svldnt1sh_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_s64offset_u64( + pg: svbool_t, + base: *const i32, + offsets: svint64_t, +) -> svuint64_t { + svldnt1sw_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u32offset_s32( + pg: svbool_t, + base: *const i8, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i8" + )] + fn _svldnt1sb_gather_u32offset_s32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svldnt1sb_gather_u32offset_s32( + pg.sve_into(), + base, + offsets.as_signed(), + )) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32offset_s32( + pg: svbool_t, + base: *const i16, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i16" + )] + fn _svldnt1sh_gather_u32offset_s32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldnt1sh_gather_u32offset_s32( + pg.sve_into(), + base, + offsets.as_signed(), + )) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u32offset_u32( + pg: svbool_t, + base: *const i8, + offsets: svuint32_t, +) -> svuint32_t { + svldnt1sb_gather_u32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32offset_u32( + pg: svbool_t, + base: *const i16, + offsets: svuint32_t, +) -> svuint32_t { + svldnt1sh_gather_u32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u64offset_s64( + pg: svbool_t, + base: *const i8, + offsets: svuint64_t, +) -> svint64_t { + svldnt1sb_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64offset_s64( + pg: svbool_t, + base: *const i16, + offsets: svuint64_t, +) -> svint64_t { + svldnt1sh_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64offset_s64( + pg: svbool_t, + base: *const i32, + offsets: svuint64_t, +) -> svint64_t { + svldnt1sw_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u64offset_u64( + pg: svbool_t, + base: *const i8, + offsets: svuint64_t, +) -> svuint64_t { + svldnt1sb_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64offset_u64( + pg: svbool_t, + base: *const i16, + offsets: svuint64_t, +) -> svuint64_t { + svldnt1sh_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64offset_u64( + pg: svbool_t, + base: *const i32, + offsets: svuint64_t, +) -> svuint64_t { + svldnt1sw_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svldnt1sb_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svldnt1sb_gather_u32base_offset_s32( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svldnt1sh_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldnt1sh_gather_u32base_offset_s32( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svldnt1sb_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svldnt1sh_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svldnt1sb_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svldnt1sb_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svldnt1sh_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldnt1sh_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svldnt1sw_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldnt1sw_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldnt1sb_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldnt1sh_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldnt1sw_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldnt1sb_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldnt1sh_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldnt1sb_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldnt1sh_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldnt1sb_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldnt1sh_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldnt1sw_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldnt1sb_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldnt1sh_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldnt1sw_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_s64index_s64( + pg: svbool_t, + base: *const i16, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2i16" + )] + fn _svldnt1sh_gather_s64index_s64( + pg: svbool2_t, + base: *const i16, + indices: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldnt1sh_gather_s64index_s64(pg.sve_into(), base, indices)) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_s64index_s64( + pg: svbool_t, + base: *const i32, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2i32" + )] + fn _svldnt1sw_gather_s64index_s64( + pg: svbool2_t, + base: *const i32, + indices: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldnt1sw_gather_s64index_s64(pg.sve_into(), base, indices)) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_s64index_u64( + pg: svbool_t, + base: *const i16, + indices: svint64_t, +) -> svuint64_t { + svldnt1sh_gather_s64index_s64(pg, base, indices).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_s64index_u64( + pg: svbool_t, + base: *const i32, + indices: svint64_t, +) -> svuint64_t { + svldnt1sw_gather_s64index_s64(pg, base, indices).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64index_s64( + pg: svbool_t, + base: *const i16, + indices: svuint64_t, +) -> svint64_t { + svldnt1sh_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64index_s64( + pg: svbool_t, + base: *const i32, + indices: svuint64_t, +) -> svint64_t { + svldnt1sw_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64index_u64( + pg: svbool_t, + base: *const i16, + indices: svuint64_t, +) -> svuint64_t { + svldnt1sh_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64index_u64( + pg: svbool_t, + base: *const i32, + indices: svuint64_t, +) -> svuint64_t { + svldnt1sw_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svldnt1sh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svldnt1sh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldnt1sh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldnt1sw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldnt1sh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldnt1sw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_s64offset_s64( + pg: svbool_t, + base: *const u8, + offsets: svint64_t, +) -> svint64_t { + svldnt1ub_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_s64offset_s64( + pg: svbool_t, + base: *const u16, + offsets: svint64_t, +) -> svint64_t { + svldnt1uh_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_s64offset_s64( + pg: svbool_t, + base: *const u32, + offsets: svint64_t, +) -> svint64_t { + svldnt1uw_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_s64offset_u64( + pg: svbool_t, + base: *const u8, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i8" + )] + fn _svldnt1ub_gather_s64offset_u64( + pg: svbool2_t, + base: *const i8, + offsets: svint64_t, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1ub_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_s64offset_u64( + pg: svbool_t, + base: *const u16, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i16" + )] + fn _svldnt1uh_gather_s64offset_u64( + pg: svbool2_t, + base: *const i16, + offsets: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uh_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_s64offset_u64( + pg: svbool_t, + base: *const u32, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i32" + )] + fn _svldnt1uw_gather_s64offset_u64( + pg: svbool2_t, + base: *const i32, + offsets: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uw_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u32offset_s32( + pg: svbool_t, + base: *const u8, + offsets: svuint32_t, +) -> svint32_t { + svldnt1ub_gather_u32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32offset_s32( + pg: svbool_t, + base: *const u16, + offsets: svuint32_t, +) -> svint32_t { + svldnt1uh_gather_u32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u32offset_u32( + pg: svbool_t, + base: *const u8, + offsets: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i8" + )] + fn _svldnt1ub_gather_u32offset_u32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1ub_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32offset_u32( + pg: svbool_t, + base: *const u16, + offsets: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i16" + )] + fn _svldnt1uh_gather_u32offset_u32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uh_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u64offset_s64( + pg: svbool_t, + base: *const u8, + offsets: svuint64_t, +) -> svint64_t { + svldnt1ub_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64offset_s64( + pg: svbool_t, + base: *const u16, + offsets: svuint64_t, +) -> svint64_t { + svldnt1uh_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64offset_s64( + pg: svbool_t, + base: *const u32, + offsets: svuint64_t, +) -> svint64_t { + svldnt1uw_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u64offset_u64( + pg: svbool_t, + base: *const u8, + offsets: svuint64_t, +) -> svuint64_t { + svldnt1ub_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64offset_u64( + pg: svbool_t, + base: *const u16, + offsets: svuint64_t, +) -> svuint64_t { + svldnt1uh_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64offset_u64( + pg: svbool_t, + base: *const u32, + offsets: svuint64_t, +) -> svuint64_t { + svldnt1uw_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + svldnt1ub_gather_u32base_offset_u32(pg, bases, offset).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + svldnt1uh_gather_u32base_offset_u32(pg, bases, offset).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svldnt1ub_gather_u32base_offset_u32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1ub_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svldnt1uh_gather_u32base_offset_u32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uh_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svldnt1ub_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svldnt1uh_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svldnt1uw_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svldnt1ub_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1ub_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svldnt1uh_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uh_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svldnt1uw_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uw_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldnt1ub_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldnt1uh_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldnt1ub_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldnt1uh_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldnt1ub_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldnt1uh_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldnt1uw_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldnt1ub_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldnt1uh_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldnt1uw_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_s64index_s64( + pg: svbool_t, + base: *const u16, + indices: svint64_t, +) -> svint64_t { + svldnt1uh_gather_s64index_u64(pg, base, indices).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_s64index_s64( + pg: svbool_t, + base: *const u32, + indices: svint64_t, +) -> svint64_t { + svldnt1uw_gather_s64index_u64(pg, base, indices).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_s64index_u64( + pg: svbool_t, + base: *const u16, + indices: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2i16" + )] + fn _svldnt1uh_gather_s64index_u64( + pg: svbool2_t, + base: *const i16, + indices: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uh_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_s64index_u64( + pg: svbool_t, + base: *const u32, + indices: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2i32" + )] + fn _svldnt1uw_gather_s64index_u64( + pg: svbool2_t, + base: *const i32, + indices: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uw_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64index_s64( + pg: svbool_t, + base: *const u16, + indices: svuint64_t, +) -> svint64_t { + svldnt1uh_gather_s64index_u64(pg, base, indices.as_signed()).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64index_s64( + pg: svbool_t, + base: *const u32, + indices: svuint64_t, +) -> svint64_t { + svldnt1uw_gather_s64index_u64(pg, base, indices.as_signed()).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64index_u64( + pg: svbool_t, + base: *const u16, + indices: svuint64_t, +) -> svuint64_t { + svldnt1uh_gather_s64index_u64(pg, base, indices.as_signed()) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64index_u64( + pg: svbool_t, + base: *const u32, + indices: svuint64_t, +) -> svuint64_t { + svldnt1uw_gather_s64index_u64(pg, base, indices.as_signed()) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svldnt1uh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svldnt1uh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldnt1uh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldnt1uw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldnt1uh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldnt1uw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Base 2 logarithm as integer"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(flogb))] +pub fn svlogb_f32_m(inactive: svint32_t, pg: svbool_t, op: svfloat32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.flogb.nxv4f32")] + fn _svlogb_f32_m(inactive: svint32_t, pg: svbool4_t, op: svfloat32_t) -> svint32_t; + } + unsafe { _svlogb_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Base 2 logarithm as integer"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(flogb))] +pub fn svlogb_f32_x(pg: svbool_t, op: svfloat32_t) -> svint32_t { + unsafe { svlogb_f32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Base 2 logarithm as integer"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(flogb))] +pub fn svlogb_f32_z(pg: svbool_t, op: svfloat32_t) -> svint32_t { + svlogb_f32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Base 2 logarithm as integer"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(flogb))] +pub fn svlogb_f64_m(inactive: svint64_t, pg: svbool_t, op: svfloat64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.flogb.nxv2f64")] + fn _svlogb_f64_m(inactive: svint64_t, pg: svbool2_t, op: svfloat64_t) -> svint64_t; + } + unsafe { _svlogb_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Base 2 logarithm as integer"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(flogb))] +pub fn svlogb_f64_x(pg: svbool_t, op: svfloat64_t) -> svint64_t { + unsafe { svlogb_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Base 2 logarithm as integer"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(flogb))] +pub fn svlogb_f64_z(pg: svbool_t, op: svfloat64_t) -> svint64_t { + svlogb_f64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Detect any matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmatch[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(match))] +pub fn svmatch_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.match.nxv16i8")] + fn _svmatch_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svmatch_s8(pg, op1, op2) } +} +#[doc = "Detect any matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmatch[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(match))] +pub fn svmatch_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.match.nxv8i16")] + fn _svmatch_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svmatch_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Detect any matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmatch[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(match))] +pub fn svmatch_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + unsafe { svmatch_s8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Detect any matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmatch[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(match))] +pub fn svmatch_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + unsafe { svmatch_s16(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Maximum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmp[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnmp))] +pub fn svmaxnmp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmaxnmp.nxv4f32" + )] + fn _svmaxnmp_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmaxnmp_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmp[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnmp))] +pub fn svmaxnmp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmaxnmp_f32_m(pg, op1, op2) +} +#[doc = "Maximum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmp[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnmp))] +pub fn svmaxnmp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmaxnmp.nxv2f64" + )] + fn _svmaxnmp_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmaxnmp_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmp[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnmp))] +pub fn svmaxnmp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmaxnmp_f64_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxp))] +pub fn svmaxp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxp.nxv4f32")] + fn _svmaxp_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmaxp_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxp))] +pub fn svmaxp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmaxp_f32_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxp))] +pub fn svmaxp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxp.nxv2f64")] + fn _svmaxp_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmaxp_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxp))] +pub fn svmaxp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmaxp_f64_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxp.nxv16i8")] + fn _svmaxp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmaxp_s8_m(pg, op1, op2) } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmaxp_s8_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxp.nxv8i16")] + fn _svmaxp_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmaxp_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmaxp_s16_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxp.nxv4i32")] + fn _svmaxp_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmaxp_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmaxp_s32_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxp.nxv2i64")] + fn _svmaxp_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmaxp_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmaxp_s64_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxp.nxv16i8")] + fn _svmaxp_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmaxp_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmaxp_u8_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxp.nxv8i16")] + fn _svmaxp_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmaxp_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmaxp_u16_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxp.nxv4i32")] + fn _svmaxp_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmaxp_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmaxp_u32_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxp.nxv2i64")] + fn _svmaxp_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmaxp_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmaxp_u64_m(pg, op1, op2) +} +#[doc = "Minimum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmp[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnmp))] +pub fn svminnmp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fminnmp.nxv4f32" + )] + fn _svminnmp_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svminnmp_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmp[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnmp))] +pub fn svminnmp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svminnmp_f32_m(pg, op1, op2) +} +#[doc = "Minimum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmp[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnmp))] +pub fn svminnmp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fminnmp.nxv2f64" + )] + fn _svminnmp_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svminnmp_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmp[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnmp))] +pub fn svminnmp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svminnmp_f64_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminp))] +pub fn svminp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminp.nxv4f32")] + fn _svminp_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svminp_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminp))] +pub fn svminp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svminp_f32_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminp))] +pub fn svminp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminp.nxv2f64")] + fn _svminp_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svminp_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminp))] +pub fn svminp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svminp_f64_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminp.nxv16i8")] + fn _svminp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svminp_s8_m(pg, op1, op2) } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svminp_s8_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminp.nxv8i16")] + fn _svminp_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svminp_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svminp_s16_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminp.nxv4i32")] + fn _svminp_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svminp_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svminp_s32_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminp.nxv2i64")] + fn _svminp_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svminp_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svminp_s64_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminp.nxv16i8")] + fn _svminp_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svminp_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svminp_u8_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminp.nxv8i16")] + fn _svminp_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svminp_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svminp_u16_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminp.nxv4i32")] + fn _svminp_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svminp_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svminp_u32_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminp.nxv2i64")] + fn _svminp_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svminp_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svminp_u64_m(pg, op1, op2) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))] +pub fn svmla_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mla.lane.nxv8i16" + )] + fn _svmla_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint16_t; + } + unsafe { _svmla_lane_s16(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))] +pub fn svmla_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mla.lane.nxv4i32" + )] + fn _svmla_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svmla_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))] +pub fn svmla_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mla.lane.nxv2i64" + )] + fn _svmla_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svmla_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))] +pub fn svmla_lane_u16( + op1: svuint16_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe { + svmla_lane_s16::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))] +pub fn svmla_lane_u32( + op1: svuint32_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { + svmla_lane_s32::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))] +pub fn svmla_lane_u64( + op1: svuint64_t, + op2: svuint64_t, + op3: svuint64_t, +) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { + svmla_lane_s64::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb, IMM_INDEX = 0))] +pub fn svmlalb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlalb.lane.nxv4i32" + )] + fn _svmlalb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svmlalb_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb, IMM_INDEX = 0))] +pub fn svmlalb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlalb.lane.nxv2i64" + )] + fn _svmlalb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svmlalb_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb, IMM_INDEX = 0))] +pub fn svmlalb_lane_u32( + op1: svuint32_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlalb.lane.nxv4i32" + )] + fn _svmlalb_lane_u32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { + _svmlalb_lane_u32(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb, IMM_INDEX = 0))] +pub fn svmlalb_lane_u64( + op1: svuint64_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlalb.lane.nxv2i64" + )] + fn _svmlalb_lane_u64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { + _svmlalb_lane_u64(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb))] +pub fn svmlalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalb.nxv8i16")] + fn _svmlalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlalb_s16(op1, op2, op3) } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb))] +pub fn svmlalb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svmlalb_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb))] +pub fn svmlalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalb.nxv4i32")] + fn _svmlalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlalb_s32(op1, op2, op3) } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb))] +pub fn svmlalb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svmlalb_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb))] +pub fn svmlalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalb.nxv2i64")] + fn _svmlalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlalb_s64(op1, op2, op3) } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb))] +pub fn svmlalb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svmlalb_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb))] +pub fn svmlalb_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalb.nxv8i16")] + fn _svmlalb_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlalb_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb))] +pub fn svmlalb_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t { + svmlalb_u16(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb))] +pub fn svmlalb_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalb.nxv4i32")] + fn _svmlalb_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlalb_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb))] +pub fn svmlalb_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t { + svmlalb_u32(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb))] +pub fn svmlalb_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalb.nxv2i64")] + fn _svmlalb_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlalb_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb))] +pub fn svmlalb_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t { + svmlalb_u64(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt, IMM_INDEX = 0))] +pub fn svmlalt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlalt.lane.nxv4i32" + )] + fn _svmlalt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svmlalt_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt, IMM_INDEX = 0))] +pub fn svmlalt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlalt.lane.nxv2i64" + )] + fn _svmlalt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svmlalt_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt, IMM_INDEX = 0))] +pub fn svmlalt_lane_u32( + op1: svuint32_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlalt.lane.nxv4i32" + )] + fn _svmlalt_lane_u32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { + _svmlalt_lane_u32(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt, IMM_INDEX = 0))] +pub fn svmlalt_lane_u64( + op1: svuint64_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlalt.lane.nxv2i64" + )] + fn _svmlalt_lane_u64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { + _svmlalt_lane_u64(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt))] +pub fn svmlalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalt.nxv8i16")] + fn _svmlalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlalt_s16(op1, op2, op3) } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt))] +pub fn svmlalt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svmlalt_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt))] +pub fn svmlalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalt.nxv4i32")] + fn _svmlalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlalt_s32(op1, op2, op3) } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt))] +pub fn svmlalt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svmlalt_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt))] +pub fn svmlalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalt.nxv2i64")] + fn _svmlalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlalt_s64(op1, op2, op3) } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt))] +pub fn svmlalt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svmlalt_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt))] +pub fn svmlalt_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalt.nxv8i16")] + fn _svmlalt_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlalt_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt))] +pub fn svmlalt_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t { + svmlalt_u16(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt))] +pub fn svmlalt_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalt.nxv4i32")] + fn _svmlalt_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlalt_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt))] +pub fn svmlalt_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t { + svmlalt_u32(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt))] +pub fn svmlalt_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalt.nxv2i64")] + fn _svmlalt_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlalt_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt))] +pub fn svmlalt_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t { + svmlalt_u64(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))] +pub fn svmls_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mls.lane.nxv8i16" + )] + fn _svmls_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint16_t; + } + unsafe { _svmls_lane_s16(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))] +pub fn svmls_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mls.lane.nxv4i32" + )] + fn _svmls_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svmls_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))] +pub fn svmls_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mls.lane.nxv2i64" + )] + fn _svmls_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svmls_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))] +pub fn svmls_lane_u16( + op1: svuint16_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe { + svmls_lane_s16::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))] +pub fn svmls_lane_u32( + op1: svuint32_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { + svmls_lane_s32::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))] +pub fn svmls_lane_u64( + op1: svuint64_t, + op2: svuint64_t, + op3: svuint64_t, +) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { + svmls_lane_s64::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb, IMM_INDEX = 0))] +pub fn svmlslb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlslb.lane.nxv4i32" + )] + fn _svmlslb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svmlslb_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb, IMM_INDEX = 0))] +pub fn svmlslb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlslb.lane.nxv2i64" + )] + fn _svmlslb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svmlslb_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb, IMM_INDEX = 0))] +pub fn svmlslb_lane_u32( + op1: svuint32_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlslb.lane.nxv4i32" + )] + fn _svmlslb_lane_u32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { + _svmlslb_lane_u32(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb, IMM_INDEX = 0))] +pub fn svmlslb_lane_u64( + op1: svuint64_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlslb.lane.nxv2i64" + )] + fn _svmlslb_lane_u64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { + _svmlslb_lane_u64(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb))] +pub fn svmlslb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslb.nxv8i16")] + fn _svmlslb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlslb_s16(op1, op2, op3) } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb))] +pub fn svmlslb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svmlslb_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb))] +pub fn svmlslb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslb.nxv4i32")] + fn _svmlslb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlslb_s32(op1, op2, op3) } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb))] +pub fn svmlslb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svmlslb_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb))] +pub fn svmlslb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslb.nxv2i64")] + fn _svmlslb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlslb_s64(op1, op2, op3) } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb))] +pub fn svmlslb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svmlslb_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb))] +pub fn svmlslb_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslb.nxv8i16")] + fn _svmlslb_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlslb_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb))] +pub fn svmlslb_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t { + svmlslb_u16(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb))] +pub fn svmlslb_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslb.nxv4i32")] + fn _svmlslb_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlslb_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb))] +pub fn svmlslb_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t { + svmlslb_u32(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb))] +pub fn svmlslb_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslb.nxv2i64")] + fn _svmlslb_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlslb_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb))] +pub fn svmlslb_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t { + svmlslb_u64(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt, IMM_INDEX = 0))] +pub fn svmlslt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlslt.lane.nxv4i32" + )] + fn _svmlslt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svmlslt_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt, IMM_INDEX = 0))] +pub fn svmlslt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlslt.lane.nxv2i64" + )] + fn _svmlslt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svmlslt_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt, IMM_INDEX = 0))] +pub fn svmlslt_lane_u32( + op1: svuint32_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlslt.lane.nxv4i32" + )] + fn _svmlslt_lane_u32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { + _svmlslt_lane_u32(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt, IMM_INDEX = 0))] +pub fn svmlslt_lane_u64( + op1: svuint64_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlslt.lane.nxv2i64" + )] + fn _svmlslt_lane_u64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { + _svmlslt_lane_u64(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt))] +pub fn svmlslt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslt.nxv8i16")] + fn _svmlslt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlslt_s16(op1, op2, op3) } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt))] +pub fn svmlslt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svmlslt_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt))] +pub fn svmlslt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslt.nxv4i32")] + fn _svmlslt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlslt_s32(op1, op2, op3) } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt))] +pub fn svmlslt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svmlslt_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt))] +pub fn svmlslt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslt.nxv2i64")] + fn _svmlslt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlslt_s64(op1, op2, op3) } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt))] +pub fn svmlslt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svmlslt_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt))] +pub fn svmlslt_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslt.nxv8i16")] + fn _svmlslt_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlslt_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt))] +pub fn svmlslt_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t { + svmlslt_u16(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt))] +pub fn svmlslt_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslt.nxv4i32")] + fn _svmlslt_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlslt_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt))] +pub fn svmlslt_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t { + svmlslt_u32(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt))] +pub fn svmlslt_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslt.nxv2i64")] + fn _svmlslt_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlslt_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt))] +pub fn svmlslt_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t { + svmlslt_u64(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Move long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllb))] +pub fn svmovlb_s16(op: svint8_t) -> svint16_t { + svshllb_n_s16::<0>(op) +} +#[doc = "Move long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllb))] +pub fn svmovlb_s32(op: svint16_t) -> svint32_t { + svshllb_n_s32::<0>(op) +} +#[doc = "Move long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllb))] +pub fn svmovlb_s64(op: svint32_t) -> svint64_t { + svshllb_n_s64::<0>(op) +} +#[doc = "Move long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllb))] +pub fn svmovlb_u16(op: svuint8_t) -> svuint16_t { + svshllb_n_u16::<0>(op) +} +#[doc = "Move long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllb))] +pub fn svmovlb_u32(op: svuint16_t) -> svuint32_t { + svshllb_n_u32::<0>(op) +} +#[doc = "Move long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllb))] +pub fn svmovlb_u64(op: svuint32_t) -> svuint64_t { + svshllb_n_u64::<0>(op) +} +#[doc = "Move long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllt))] +pub fn svmovlt_s16(op: svint8_t) -> svint16_t { + svshllt_n_s16::<0>(op) +} +#[doc = "Move long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllt))] +pub fn svmovlt_s32(op: svint16_t) -> svint32_t { + svshllt_n_s32::<0>(op) +} +#[doc = "Move long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllt))] +pub fn svmovlt_s64(op: svint32_t) -> svint64_t { + svshllt_n_s64::<0>(op) +} +#[doc = "Move long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllt))] +pub fn svmovlt_u16(op: svuint8_t) -> svuint16_t { + svshllt_n_u16::<0>(op) +} +#[doc = "Move long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllt))] +pub fn svmovlt_u32(op: svuint16_t) -> svuint32_t { + svshllt_n_u32::<0>(op) +} +#[doc = "Move long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllt))] +pub fn svmovlt_u64(op: svuint32_t) -> svuint64_t { + svshllt_n_u64::<0>(op) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_f32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul, IMM_INDEX = 0))] +pub fn svmul_lane_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmul.lane.nxv4f32" + )] + fn _svmul_lane_f32(op1: svfloat32_t, op2: svfloat32_t, imm_index: i32) -> svfloat32_t; + } + unsafe { _svmul_lane_f32(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_f64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul, IMM_INDEX = 0))] +pub fn svmul_lane_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmul.lane.nxv2f64" + )] + fn _svmul_lane_f64(op1: svfloat64_t, op2: svfloat64_t, imm_index: i32) -> svfloat64_t; + } + unsafe { _svmul_lane_f64(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))] +pub fn svmul_lane_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mul.lane.nxv8i16" + )] + fn _svmul_lane_s16(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint16_t; + } + unsafe { _svmul_lane_s16(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))] +pub fn svmul_lane_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mul.lane.nxv4i32" + )] + fn _svmul_lane_s32(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint32_t; + } + unsafe { _svmul_lane_s32(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))] +pub fn svmul_lane_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mul.lane.nxv2i64" + )] + fn _svmul_lane_s64(op1: svint64_t, op2: svint64_t, imm_index: i32) -> svint64_t; + } + unsafe { _svmul_lane_s64(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))] +pub fn svmul_lane_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe { svmul_lane_s16::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))] +pub fn svmul_lane_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { svmul_lane_s32::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))] +pub fn svmul_lane_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { svmul_lane_s64::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(smullb, IMM_INDEX = 0) +)] +pub fn svmullb_lane_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smullb.lane.nxv4i32" + )] + fn _svmullb_lane_s32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t; + } + unsafe { _svmullb_lane_s32(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(smullb, IMM_INDEX = 0) +)] +pub fn svmullb_lane_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smullb.lane.nxv2i64" + )] + fn _svmullb_lane_s64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t; + } + unsafe { _svmullb_lane_s64(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(umullb, IMM_INDEX = 0) +)] +pub fn svmullb_lane_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umullb.lane.nxv4i32" + )] + fn _svmullb_lane_u32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t; + } + unsafe { _svmullb_lane_u32(op1.as_signed(), op2.as_signed(), IMM_INDEX).as_unsigned() } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(umullb, IMM_INDEX = 0) +)] +pub fn svmullb_lane_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umullb.lane.nxv2i64" + )] + fn _svmullb_lane_u64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t; + } + unsafe { _svmullb_lane_u64(op1.as_signed(), op2.as_signed(), IMM_INDEX).as_unsigned() } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smullb))] +pub fn svmullb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullb.nxv8i16")] + fn _svmullb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svmullb_s16(op1, op2) } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smullb))] +pub fn svmullb_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svmullb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smullb))] +pub fn svmullb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullb.nxv4i32")] + fn _svmullb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svmullb_s32(op1, op2) } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smullb))] +pub fn svmullb_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svmullb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smullb))] +pub fn svmullb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullb.nxv2i64")] + fn _svmullb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svmullb_s64(op1, op2) } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smullb))] +pub fn svmullb_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svmullb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umullb))] +pub fn svmullb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullb.nxv8i16")] + fn _svmullb_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svmullb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umullb))] +pub fn svmullb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svmullb_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umullb))] +pub fn svmullb_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullb.nxv4i32")] + fn _svmullb_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svmullb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umullb))] +pub fn svmullb_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svmullb_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umullb))] +pub fn svmullb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullb.nxv2i64")] + fn _svmullb_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svmullb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umullb))] +pub fn svmullb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svmullb_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(smullt, IMM_INDEX = 0) +)] +pub fn svmullt_lane_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smullt.lane.nxv4i32" + )] + fn _svmullt_lane_s32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t; + } + unsafe { _svmullt_lane_s32(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(smullt, IMM_INDEX = 0) +)] +pub fn svmullt_lane_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smullt.lane.nxv2i64" + )] + fn _svmullt_lane_s64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t; + } + unsafe { _svmullt_lane_s64(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(umullt, IMM_INDEX = 0) +)] +pub fn svmullt_lane_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umullt.lane.nxv4i32" + )] + fn _svmullt_lane_u32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t; + } + unsafe { _svmullt_lane_u32(op1.as_signed(), op2.as_signed(), IMM_INDEX).as_unsigned() } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(umullt, IMM_INDEX = 0) +)] +pub fn svmullt_lane_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umullt.lane.nxv2i64" + )] + fn _svmullt_lane_u64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t; + } + unsafe { _svmullt_lane_u64(op1.as_signed(), op2.as_signed(), IMM_INDEX).as_unsigned() } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))] +pub fn svmullt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullt.nxv8i16")] + fn _svmullt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svmullt_s16(op1, op2) } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))] +pub fn svmullt_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svmullt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))] +pub fn svmullt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullt.nxv4i32")] + fn _svmullt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svmullt_s32(op1, op2) } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))] +pub fn svmullt_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svmullt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))] +pub fn svmullt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullt.nxv2i64")] + fn _svmullt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svmullt_s64(op1, op2) } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))] +pub fn svmullt_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svmullt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))] +pub fn svmullt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullt.nxv8i16")] + fn _svmullt_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svmullt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))] +pub fn svmullt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svmullt_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))] +pub fn svmullt_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullt.nxv4i32")] + fn _svmullt_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svmullt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))] +pub fn svmullt_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svmullt_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))] +pub fn svmullt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullt.nxv2i64")] + fn _svmullt_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svmullt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))] +pub fn svmullt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svmullt_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nbsl.nxv16i8")] + fn _svnbsl_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svnbsl_s8(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svnbsl_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nbsl.nxv8i16")] + fn _svnbsl_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svnbsl_s16(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svnbsl_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nbsl.nxv4i32")] + fn _svnbsl_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svnbsl_s32(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svnbsl_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nbsl.nxv2i64")] + fn _svnbsl_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svnbsl_s64(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svnbsl_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svnbsl_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svnbsl_u8(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svnbsl_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svnbsl_u16(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svnbsl_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svnbsl_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svnbsl_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svnbsl_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Detect no matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmatch[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nmatch))] +pub fn svnmatch_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nmatch.nxv16i8")] + fn _svnmatch_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svnmatch_s8(pg, op1, op2) } +} +#[doc = "Detect no matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmatch[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nmatch))] +pub fn svnmatch_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nmatch.nxv8i16")] + fn _svnmatch_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svnmatch_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Detect no matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmatch[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nmatch))] +pub fn svnmatch_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + unsafe { svnmatch_s8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Detect no matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmatch[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nmatch))] +pub fn svnmatch_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + unsafe { svnmatch_s16(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Polynomial multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmul[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmul))] +pub fn svpmul_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pmul.nxv16i8")] + fn _svpmul_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svpmul_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Polynomial multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmul[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmul))] +pub fn svpmul_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svpmul_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_pair_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.pmullb.pair.nxv16i8" + )] + fn _svpmullb_pair_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svpmullb_pair_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_pair_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svpmullb_pair_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_pair_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.pmullb.pair.nxv4i32" + )] + fn _svpmullb_pair_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svpmullb_pair_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_pair_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + svpmullb_pair_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_pair_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.pmullb.pair.nxv2i64" + )] + fn _svpmullb_pair_u64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svpmullb_pair_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_pair_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + svpmullb_pair_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(svpmullb_pair_u8(op1, op2)) } +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svpmullb_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(svpmullb_pair_u32(op1, op2)) } +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svpmullb_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_pair_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.pmullt.pair.nxv16i8" + )] + fn _svpmullt_pair_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svpmullt_pair_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_pair_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svpmullt_pair_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_pair_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.pmullt.pair.nxv4i32" + )] + fn _svpmullt_pair_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svpmullt_pair_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_pair_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + svpmullt_pair_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_pair_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.pmullt.pair.nxv2i64" + )] + fn _svpmullt_pair_u64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svpmullt_pair_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_pair_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + svpmullt_pair_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(svpmullt_pair_u8(op1, op2)) } +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svpmullt_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(svpmullt_pair_u32(op1, op2)) } +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svpmullt_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqabs.nxv16i8")] + fn _svqabs_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svqabs_s8_m(inactive, pg, op) } +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t { + svqabs_s8_m(op, pg, op) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t { + svqabs_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqabs.nxv8i16")] + fn _svqabs_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svqabs_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svqabs_s16_m(op, pg, op) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svqabs_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqabs.nxv4i32")] + fn _svqabs_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svqabs_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svqabs_s32_m(op, pg, op) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svqabs_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqabs.nxv2i64")] + fn _svqabs_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svqabs_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svqabs_s64_m(op, pg, op) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svqabs_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqadd.nxv16i8")] + fn _svqadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqadd_s8_m(pg, op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqadd_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqadd_s8_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqadd_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqadd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqadd_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqadd.nxv8i16")] + fn _svqadd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqadd_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqadd_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqadd_s16_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqadd_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqadd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqadd_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqadd.nxv4i32")] + fn _svqadd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqadd_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqadd_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqadd_s32_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqadd_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqadd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqadd_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqadd.nxv2i64")] + fn _svqadd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqadd_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqadd_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqadd_s64_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqadd_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqadd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqadd_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqadd.nxv16i8")] + fn _svqadd_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqadd_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqadd_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svqadd_u8_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqadd_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svqadd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqadd_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqadd.nxv8i16")] + fn _svqadd_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqadd_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqadd_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svqadd_u16_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqadd_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svqadd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqadd_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqadd.nxv4i32")] + fn _svqadd_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqadd_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqadd_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svqadd_u32_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqadd_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svqadd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqadd_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqadd.nxv2i64")] + fn _svqadd_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqadd_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqadd_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svqadd_u64_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqadd_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svqadd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqadd_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqcadd[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqcadd, IMM_ROTATION = 90))] +pub fn svqcadd_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqcadd.x.nxv16i8" + )] + fn _svqcadd_s8(op1: svint8_t, op2: svint8_t, imm_rotation: i32) -> svint8_t; + } + unsafe { _svqcadd_s8(op1, op2, IMM_ROTATION) } +} +#[doc = "Saturating complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqcadd[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqcadd, IMM_ROTATION = 90))] +pub fn svqcadd_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqcadd.x.nxv8i16" + )] + fn _svqcadd_s16(op1: svint16_t, op2: svint16_t, imm_rotation: i32) -> svint16_t; + } + unsafe { _svqcadd_s16(op1, op2, IMM_ROTATION) } +} +#[doc = "Saturating complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqcadd[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqcadd, IMM_ROTATION = 90))] +pub fn svqcadd_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqcadd.x.nxv4i32" + )] + fn _svqcadd_s32(op1: svint32_t, op2: svint32_t, imm_rotation: i32) -> svint32_t; + } + unsafe { _svqcadd_s32(op1, op2, IMM_ROTATION) } +} +#[doc = "Saturating complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqcadd[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqcadd, IMM_ROTATION = 90))] +pub fn svqcadd_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqcadd.x.nxv2i64" + )] + fn _svqcadd_s64(op1: svint64_t, op2: svint64_t, imm_rotation: i32) -> svint64_t; + } + unsafe { _svqcadd_s64(op1, op2, IMM_ROTATION) } +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb, IMM_INDEX = 0))] +pub fn svqdmlalb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalb.lane.nxv4i32" + )] + fn _svqdmlalb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svqdmlalb_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb, IMM_INDEX = 0))] +pub fn svqdmlalb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalb.lane.nxv2i64" + )] + fn _svqdmlalb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svqdmlalb_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb))] +pub fn svqdmlalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalb.nxv8i16" + )] + fn _svqdmlalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svqdmlalb_s16(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb))] +pub fn svqdmlalb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svqdmlalb_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb))] +pub fn svqdmlalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalb.nxv4i32" + )] + fn _svqdmlalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svqdmlalb_s32(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb))] +pub fn svqdmlalb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svqdmlalb_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb))] +pub fn svqdmlalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalb.nxv2i64" + )] + fn _svqdmlalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svqdmlalb_s64(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb))] +pub fn svqdmlalb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svqdmlalb_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating doubling multiply-add long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalbt))] +pub fn svqdmlalbt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalbt.nxv8i16" + )] + fn _svqdmlalbt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svqdmlalbt_s16(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalbt))] +pub fn svqdmlalbt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svqdmlalbt_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating doubling multiply-add long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalbt))] +pub fn svqdmlalbt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalbt.nxv4i32" + )] + fn _svqdmlalbt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svqdmlalbt_s32(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalbt))] +pub fn svqdmlalbt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svqdmlalbt_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating doubling multiply-add long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalbt))] +pub fn svqdmlalbt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalbt.nxv2i64" + )] + fn _svqdmlalbt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svqdmlalbt_s64(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalbt))] +pub fn svqdmlalbt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svqdmlalbt_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt, IMM_INDEX = 0))] +pub fn svqdmlalt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalt.lane.nxv4i32" + )] + fn _svqdmlalt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svqdmlalt_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt, IMM_INDEX = 0))] +pub fn svqdmlalt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalt.lane.nxv2i64" + )] + fn _svqdmlalt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svqdmlalt_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt))] +pub fn svqdmlalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalt.nxv8i16" + )] + fn _svqdmlalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svqdmlalt_s16(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt))] +pub fn svqdmlalt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svqdmlalt_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt))] +pub fn svqdmlalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalt.nxv4i32" + )] + fn _svqdmlalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svqdmlalt_s32(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt))] +pub fn svqdmlalt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svqdmlalt_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt))] +pub fn svqdmlalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalt.nxv2i64" + )] + fn _svqdmlalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svqdmlalt_s64(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt))] +pub fn svqdmlalt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svqdmlalt_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb, IMM_INDEX = 0))] +pub fn svqdmlslb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslb.lane.nxv4i32" + )] + fn _svqdmlslb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svqdmlslb_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb, IMM_INDEX = 0))] +pub fn svqdmlslb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslb.lane.nxv2i64" + )] + fn _svqdmlslb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svqdmlslb_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb))] +pub fn svqdmlslb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslb.nxv8i16" + )] + fn _svqdmlslb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svqdmlslb_s16(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb))] +pub fn svqdmlslb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svqdmlslb_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb))] +pub fn svqdmlslb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslb.nxv4i32" + )] + fn _svqdmlslb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svqdmlslb_s32(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb))] +pub fn svqdmlslb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svqdmlslb_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb))] +pub fn svqdmlslb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslb.nxv2i64" + )] + fn _svqdmlslb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svqdmlslb_s64(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb))] +pub fn svqdmlslb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svqdmlslb_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslbt))] +pub fn svqdmlslbt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslbt.nxv8i16" + )] + fn _svqdmlslbt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svqdmlslbt_s16(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslbt))] +pub fn svqdmlslbt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svqdmlslbt_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslbt))] +pub fn svqdmlslbt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslbt.nxv4i32" + )] + fn _svqdmlslbt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svqdmlslbt_s32(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslbt))] +pub fn svqdmlslbt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svqdmlslbt_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslbt))] +pub fn svqdmlslbt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslbt.nxv2i64" + )] + fn _svqdmlslbt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svqdmlslbt_s64(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslbt))] +pub fn svqdmlslbt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svqdmlslbt_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt, IMM_INDEX = 0))] +pub fn svqdmlslt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslt.lane.nxv4i32" + )] + fn _svqdmlslt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svqdmlslt_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt, IMM_INDEX = 0))] +pub fn svqdmlslt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslt.lane.nxv2i64" + )] + fn _svqdmlslt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svqdmlslt_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt))] +pub fn svqdmlslt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslt.nxv8i16" + )] + fn _svqdmlslt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svqdmlslt_s16(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt))] +pub fn svqdmlslt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svqdmlslt_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt))] +pub fn svqdmlslt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslt.nxv4i32" + )] + fn _svqdmlslt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svqdmlslt_s32(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt))] +pub fn svqdmlslt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svqdmlslt_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt))] +pub fn svqdmlslt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslt.nxv2i64" + )] + fn _svqdmlslt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svqdmlslt_s64(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt))] +pub fn svqdmlslt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svqdmlslt_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh_lane[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh, IMM_INDEX = 0))] +pub fn svqdmulh_lane_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmulh.lane.nxv8i16" + )] + fn _svqdmulh_lane_s16(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint16_t; + } + unsafe { _svqdmulh_lane_s16(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh, IMM_INDEX = 0))] +pub fn svqdmulh_lane_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmulh.lane.nxv4i32" + )] + fn _svqdmulh_lane_s32(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint32_t; + } + unsafe { _svqdmulh_lane_s32(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh, IMM_INDEX = 0))] +pub fn svqdmulh_lane_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmulh.lane.nxv2i64" + )] + fn _svqdmulh_lane_s64(op1: svint64_t, op2: svint64_t, imm_index: i32) -> svint64_t; + } + unsafe { _svqdmulh_lane_s64(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmulh.nxv16i8" + )] + fn _svqdmulh_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqdmulh_s8(op1, op2) } +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_n_s8(op1: svint8_t, op2: i8) -> svint8_t { + svqdmulh_s8(op1, svdup_n_s8(op2)) +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmulh.nxv8i16" + )] + fn _svqdmulh_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqdmulh_s16(op1, op2) } +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_n_s16(op1: svint16_t, op2: i16) -> svint16_t { + svqdmulh_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmulh.nxv4i32" + )] + fn _svqdmulh_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqdmulh_s32(op1, op2) } +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_n_s32(op1: svint32_t, op2: i32) -> svint32_t { + svqdmulh_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmulh.nxv2i64" + )] + fn _svqdmulh_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqdmulh_s64(op1, op2) } +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_n_s64(op1: svint64_t, op2: i64) -> svint64_t { + svqdmulh_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb, IMM_INDEX = 0))] +pub fn svqdmullb_lane_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullb.lane.nxv4i32" + )] + fn _svqdmullb_lane_s32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t; + } + unsafe { _svqdmullb_lane_s32(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb, IMM_INDEX = 0))] +pub fn svqdmullb_lane_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullb.lane.nxv2i64" + )] + fn _svqdmullb_lane_s64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t; + } + unsafe { _svqdmullb_lane_s64(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb))] +pub fn svqdmullb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullb.nxv8i16" + )] + fn _svqdmullb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svqdmullb_s16(op1, op2) } +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb))] +pub fn svqdmullb_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svqdmullb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb))] +pub fn svqdmullb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullb.nxv4i32" + )] + fn _svqdmullb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svqdmullb_s32(op1, op2) } +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb))] +pub fn svqdmullb_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svqdmullb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb))] +pub fn svqdmullb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullb.nxv2i64" + )] + fn _svqdmullb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svqdmullb_s64(op1, op2) } +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb))] +pub fn svqdmullb_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svqdmullb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt, IMM_INDEX = 0))] +pub fn svqdmullt_lane_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullt.lane.nxv4i32" + )] + fn _svqdmullt_lane_s32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t; + } + unsafe { _svqdmullt_lane_s32(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt, IMM_INDEX = 0))] +pub fn svqdmullt_lane_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullt.lane.nxv2i64" + )] + fn _svqdmullt_lane_s64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t; + } + unsafe { _svqdmullt_lane_s64(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt))] +pub fn svqdmullt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullt.nxv8i16" + )] + fn _svqdmullt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svqdmullt_s16(op1, op2) } +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt))] +pub fn svqdmullt_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svqdmullt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt))] +pub fn svqdmullt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullt.nxv4i32" + )] + fn _svqdmullt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svqdmullt_s32(op1, op2) } +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt))] +pub fn svqdmullt_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svqdmullt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt))] +pub fn svqdmullt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullt.nxv2i64" + )] + fn _svqdmullt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svqdmullt_s64(op1, op2) } +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt))] +pub fn svqdmullt_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svqdmullt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqneg.nxv16i8")] + fn _svqneg_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svqneg_s8_m(inactive, pg, op) } +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t { + svqneg_s8_m(op, pg, op) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t { + svqneg_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqneg.nxv8i16")] + fn _svqneg_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svqneg_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svqneg_s16_m(op, pg, op) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svqneg_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqneg.nxv4i32")] + fn _svqneg_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svqneg_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svqneg_s32_m(op, pg, op) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svqneg_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqneg.nxv2i64")] + fn _svqneg_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svqneg_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svqneg_s64_m(op, pg, op) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svqneg_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Saturating rounding doubling complex multiply-add high with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah_lane[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svqrdcmlah_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=3); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdcmlah.lane.x.nxv8i16" + )] + fn _svqrdcmlah_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + imm_index: i32, + imm_rotation: i32, + ) -> svint16_t; + } + unsafe { _svqrdcmlah_lane_s16(op1, op2, op3, IMM_INDEX, IMM_ROTATION) } +} +#[doc = "Saturating rounding doubling complex multiply-add high with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svqrdcmlah_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=1); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdcmlah.lane.x.nxv4i32" + )] + fn _svqrdcmlah_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + imm_index: i32, + imm_rotation: i32, + ) -> svint32_t; + } + unsafe { _svqrdcmlah_lane_s32(op1, op2, op3, IMM_INDEX, IMM_ROTATION) } +} +#[doc = "Saturating rounding doubling complex multiply-add high with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_ROTATION = 90))] +pub fn svqrdcmlah_s8( + op1: svint8_t, + op2: svint8_t, + op3: svint8_t, +) -> svint8_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdcmlah.x.nxv16i8" + )] + fn _svqrdcmlah_s8( + op1: svint8_t, + op2: svint8_t, + op3: svint8_t, + imm_rotation: i32, + ) -> svint8_t; + } + unsafe { _svqrdcmlah_s8(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Saturating rounding doubling complex multiply-add high with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_ROTATION = 90))] +pub fn svqrdcmlah_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdcmlah.x.nxv8i16" + )] + fn _svqrdcmlah_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + imm_rotation: i32, + ) -> svint16_t; + } + unsafe { _svqrdcmlah_s16(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Saturating rounding doubling complex multiply-add high with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_ROTATION = 90))] +pub fn svqrdcmlah_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdcmlah.x.nxv4i32" + )] + fn _svqrdcmlah_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + imm_rotation: i32, + ) -> svint32_t; + } + unsafe { _svqrdcmlah_s32(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Saturating rounding doubling complex multiply-add high with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_ROTATION = 90))] +pub fn svqrdcmlah_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, +) -> svint64_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdcmlah.x.nxv2i64" + )] + fn _svqrdcmlah_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, + imm_rotation: i32, + ) -> svint64_t; + } + unsafe { _svqrdcmlah_s64(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah_lane[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah, IMM_INDEX = 0))] +pub fn svqrdmlah_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlah.lane.nxv8i16" + )] + fn _svqrdmlah_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint16_t; + } + unsafe { _svqrdmlah_lane_s16(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah, IMM_INDEX = 0))] +pub fn svqrdmlah_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlah.lane.nxv4i32" + )] + fn _svqrdmlah_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svqrdmlah_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah, IMM_INDEX = 0))] +pub fn svqrdmlah_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlah.lane.nxv2i64" + )] + fn _svqrdmlah_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svqrdmlah_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlah.nxv16i8" + )] + fn _svqrdmlah_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svqrdmlah_s8(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svqrdmlah_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlah.nxv8i16" + )] + fn _svqrdmlah_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svqrdmlah_s16(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svqrdmlah_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlah.nxv4i32" + )] + fn _svqrdmlah_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svqrdmlah_s32(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svqrdmlah_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlah.nxv2i64" + )] + fn _svqrdmlah_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svqrdmlah_s64(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svqrdmlah_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh_lane[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh, IMM_INDEX = 0))] +pub fn svqrdmlsh_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlsh.lane.nxv8i16" + )] + fn _svqrdmlsh_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint16_t; + } + unsafe { _svqrdmlsh_lane_s16(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh, IMM_INDEX = 0))] +pub fn svqrdmlsh_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlsh.lane.nxv4i32" + )] + fn _svqrdmlsh_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svqrdmlsh_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh, IMM_INDEX = 0))] +pub fn svqrdmlsh_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlsh.lane.nxv2i64" + )] + fn _svqrdmlsh_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svqrdmlsh_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlsh.nxv16i8" + )] + fn _svqrdmlsh_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svqrdmlsh_s8(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svqrdmlsh_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlsh.nxv8i16" + )] + fn _svqrdmlsh_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svqrdmlsh_s16(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svqrdmlsh_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlsh.nxv4i32" + )] + fn _svqrdmlsh_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svqrdmlsh_s32(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svqrdmlsh_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlsh.nxv2i64" + )] + fn _svqrdmlsh_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svqrdmlsh_s64(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svqrdmlsh_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh_lane[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh, IMM_INDEX = 0))] +pub fn svqrdmulh_lane_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmulh.lane.nxv8i16" + )] + fn _svqrdmulh_lane_s16(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint16_t; + } + unsafe { _svqrdmulh_lane_s16(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh, IMM_INDEX = 0))] +pub fn svqrdmulh_lane_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmulh.lane.nxv4i32" + )] + fn _svqrdmulh_lane_s32(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint32_t; + } + unsafe { _svqrdmulh_lane_s32(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh, IMM_INDEX = 0))] +pub fn svqrdmulh_lane_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmulh.lane.nxv2i64" + )] + fn _svqrdmulh_lane_s64(op1: svint64_t, op2: svint64_t, imm_index: i32) -> svint64_t; + } + unsafe { _svqrdmulh_lane_s64(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmulh.nxv16i8" + )] + fn _svqrdmulh_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqrdmulh_s8(op1, op2) } +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_n_s8(op1: svint8_t, op2: i8) -> svint8_t { + svqrdmulh_s8(op1, svdup_n_s8(op2)) +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmulh.nxv8i16" + )] + fn _svqrdmulh_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqrdmulh_s16(op1, op2) } +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_n_s16(op1: svint16_t, op2: i16) -> svint16_t { + svqrdmulh_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmulh.nxv4i32" + )] + fn _svqrdmulh_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqrdmulh_s32(op1, op2) } +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_n_s32(op1: svint32_t, op2: i32) -> svint32_t { + svqrdmulh_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmulh.nxv2i64" + )] + fn _svqrdmulh_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqrdmulh_s64(op1, op2) } +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_n_s64(op1: svint64_t, op2: i64) -> svint64_t { + svqrdmulh_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqrshl.nxv16i8")] + fn _svqrshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqrshl_s8_m(pg, op1, op2) } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqrshl_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqrshl_s8_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqrshl_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqrshl_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqrshl_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqrshl.nxv8i16")] + fn _svqrshl_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqrshl_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqrshl_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqrshl_s16_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqrshl_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqrshl_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqrshl_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqrshl.nxv4i32")] + fn _svqrshl_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqrshl_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqrshl_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqrshl_s32_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqrshl_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqrshl_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqrshl_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqrshl.nxv2i64")] + fn _svqrshl_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqrshl_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqrshl_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqrshl_s64_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqrshl_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqrshl_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqrshl_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u8_m(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqrshl.nxv16i8")] + fn _svqrshl_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqrshl_u8_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svqrshl_u8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u8_x(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svqrshl_u8_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svqrshl_u8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u8_z(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svqrshl_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svqrshl_u8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u16_m(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqrshl.nxv8i16")] + fn _svqrshl_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqrshl_u16_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svqrshl_u16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u16_x(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svqrshl_u16_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svqrshl_u16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u16_z(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svqrshl_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svqrshl_u16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u32_m(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqrshl.nxv4i32")] + fn _svqrshl_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqrshl_u32_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svqrshl_u32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u32_x(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svqrshl_u32_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svqrshl_u32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u32_z(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svqrshl_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svqrshl_u32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u64_m(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqrshl.nxv2i64")] + fn _svqrshl_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqrshl_u64_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svqrshl_u64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u64_x(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svqrshl_u64_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svqrshl_u64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u64_z(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svqrshl_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svqrshl_u64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrnb, IMM2 = 1))] +pub fn svqrshrnb_n_s16(op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrnb.nxv8i16" + )] + fn _svqrshrnb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqrshrnb_n_s16(op1, IMM2) } +} +#[doc = "Saturating rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrnb, IMM2 = 1))] +pub fn svqrshrnb_n_s32(op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrnb.nxv4i32" + )] + fn _svqrshrnb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqrshrnb_n_s32(op1, IMM2) } +} +#[doc = "Saturating rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrnb, IMM2 = 1))] +pub fn svqrshrnb_n_s64(op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrnb.nxv2i64" + )] + fn _svqrshrnb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqrshrnb_n_s64(op1, IMM2) } +} +#[doc = "Saturating rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshrnb, IMM2 = 1))] +pub fn svqrshrnb_n_u16(op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqrshrnb.nxv8i16" + )] + fn _svqrshrnb_n_u16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqrshrnb_n_u16(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshrnb, IMM2 = 1))] +pub fn svqrshrnb_n_u32(op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqrshrnb.nxv4i32" + )] + fn _svqrshrnb_n_u32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqrshrnb_n_u32(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshrnb, IMM2 = 1))] +pub fn svqrshrnb_n_u64(op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqrshrnb.nxv2i64" + )] + fn _svqrshrnb_n_u64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqrshrnb_n_u64(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrnt, IMM2 = 1))] +pub fn svqrshrnt_n_s16(even: svint8_t, op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrnt.nxv8i16" + )] + fn _svqrshrnt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqrshrnt_n_s16(even, op1, IMM2) } +} +#[doc = "Saturating rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrnt, IMM2 = 1))] +pub fn svqrshrnt_n_s32(even: svint16_t, op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrnt.nxv4i32" + )] + fn _svqrshrnt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqrshrnt_n_s32(even, op1, IMM2) } +} +#[doc = "Saturating rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrnt, IMM2 = 1))] +pub fn svqrshrnt_n_s64(even: svint32_t, op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrnt.nxv2i64" + )] + fn _svqrshrnt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqrshrnt_n_s64(even, op1, IMM2) } +} +#[doc = "Saturating rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshrnt, IMM2 = 1))] +pub fn svqrshrnt_n_u16(even: svuint8_t, op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqrshrnt.nxv8i16" + )] + fn _svqrshrnt_n_u16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqrshrnt_n_u16(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshrnt, IMM2 = 1))] +pub fn svqrshrnt_n_u32(even: svuint16_t, op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqrshrnt.nxv4i32" + )] + fn _svqrshrnt_n_u32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqrshrnt_n_u32(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshrnt, IMM2 = 1))] +pub fn svqrshrnt_n_u64(even: svuint32_t, op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqrshrnt.nxv2i64" + )] + fn _svqrshrnt_n_u64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqrshrnt_n_u64(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrunb, IMM2 = 1))] +pub fn svqrshrunb_n_s16(op1: svint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrunb.nxv8i16" + )] + fn _svqrshrunb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqrshrunb_n_s16(op1, IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrunb, IMM2 = 1))] +pub fn svqrshrunb_n_s32(op1: svint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrunb.nxv4i32" + )] + fn _svqrshrunb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqrshrunb_n_s32(op1, IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrunb, IMM2 = 1))] +pub fn svqrshrunb_n_s64(op1: svint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrunb.nxv2i64" + )] + fn _svqrshrunb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqrshrunb_n_s64(op1, IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrunt, IMM2 = 1))] +pub fn svqrshrunt_n_s16(even: svuint8_t, op1: svint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrunt.nxv8i16" + )] + fn _svqrshrunt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqrshrunt_n_s16(even.as_signed(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrunt, IMM2 = 1))] +pub fn svqrshrunt_n_s32(even: svuint16_t, op1: svint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrunt.nxv4i32" + )] + fn _svqrshrunt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqrshrunt_n_s32(even.as_signed(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrunt, IMM2 = 1))] +pub fn svqrshrunt_n_s64(even: svuint32_t, op1: svint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrunt.nxv2i64" + )] + fn _svqrshrunt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqrshrunt_n_s64(even.as_signed(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshl.nxv16i8")] + fn _svqshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqshl_s8_m(pg, op1, op2) } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqshl_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqshl_s8_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqshl_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqshl_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqshl_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshl.nxv8i16")] + fn _svqshl_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqshl_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqshl_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqshl_s16_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqshl_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqshl_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqshl_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshl.nxv4i32")] + fn _svqshl_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqshl_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqshl_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqshl_s32_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqshl_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqshl_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqshl_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshl.nxv2i64")] + fn _svqshl_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqshl_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqshl_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqshl_s64_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqshl_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqshl_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqshl_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u8_m(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqshl.nxv16i8")] + fn _svqshl_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqshl_u8_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svqshl_u8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u8_x(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svqshl_u8_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svqshl_u8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u8_z(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svqshl_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svqshl_u8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u16_m(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqshl.nxv8i16")] + fn _svqshl_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqshl_u16_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svqshl_u16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u16_x(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svqshl_u16_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svqshl_u16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u16_z(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svqshl_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svqshl_u16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u32_m(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqshl.nxv4i32")] + fn _svqshl_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqshl_u32_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svqshl_u32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u32_x(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svqshl_u32_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svqshl_u32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u32_z(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svqshl_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svqshl_u32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u64_m(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqshl.nxv2i64")] + fn _svqshl_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqshl_u64_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svqshl_u64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u64_x(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svqshl_u64_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svqshl_u64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u64_z(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svqshl_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svqshl_u64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s8_m(pg: svbool_t, op1: svint8_t) -> svuint8_t { + static_assert_range!(IMM2, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshlu.nxv16i8")] + fn _svqshlu_n_s8_m(pg: svbool_t, op1: svint8_t, imm2: i32) -> svint8_t; + } + unsafe { _svqshlu_n_s8_m(pg, op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s8_x(pg: svbool_t, op1: svint8_t) -> svuint8_t { + svqshlu_n_s8_m::(pg, op1) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s8_z(pg: svbool_t, op1: svint8_t) -> svuint8_t { + svqshlu_n_s8_m::(pg, svsel_s8(pg, op1, svdup_n_s8(0))) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s16_m(pg: svbool_t, op1: svint16_t) -> svuint16_t { + static_assert_range!(IMM2, 0..=15); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshlu.nxv8i16")] + fn _svqshlu_n_s16_m(pg: svbool8_t, op1: svint16_t, imm2: i32) -> svint16_t; + } + unsafe { _svqshlu_n_s16_m(pg.sve_into(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s16_x(pg: svbool_t, op1: svint16_t) -> svuint16_t { + svqshlu_n_s16_m::(pg, op1) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s16_z(pg: svbool_t, op1: svint16_t) -> svuint16_t { + svqshlu_n_s16_m::(pg, svsel_s16(pg, op1, svdup_n_s16(0))) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s32_m(pg: svbool_t, op1: svint32_t) -> svuint32_t { + static_assert_range!(IMM2, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshlu.nxv4i32")] + fn _svqshlu_n_s32_m(pg: svbool4_t, op1: svint32_t, imm2: i32) -> svint32_t; + } + unsafe { _svqshlu_n_s32_m(pg.sve_into(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s32_x(pg: svbool_t, op1: svint32_t) -> svuint32_t { + svqshlu_n_s32_m::(pg, op1) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s32_z(pg: svbool_t, op1: svint32_t) -> svuint32_t { + svqshlu_n_s32_m::(pg, svsel_s32(pg, op1, svdup_n_s32(0))) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s64_m(pg: svbool_t, op1: svint64_t) -> svuint64_t { + static_assert_range!(IMM2, 0..=63); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshlu.nxv2i64")] + fn _svqshlu_n_s64_m(pg: svbool2_t, op1: svint64_t, imm2: i32) -> svint64_t; + } + unsafe { _svqshlu_n_s64_m(pg.sve_into(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s64_x(pg: svbool_t, op1: svint64_t) -> svuint64_t { + svqshlu_n_s64_m::(pg, op1) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s64_z(pg: svbool_t, op1: svint64_t) -> svuint64_t { + svqshlu_n_s64_m::(pg, svsel_s64(pg, op1, svdup_n_s64(0))) +} +#[doc = "Saturating shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrnb, IMM2 = 1))] +pub fn svqshrnb_n_s16(op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrnb.nxv8i16" + )] + fn _svqshrnb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqshrnb_n_s16(op1, IMM2) } +} +#[doc = "Saturating shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrnb, IMM2 = 1))] +pub fn svqshrnb_n_s32(op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrnb.nxv4i32" + )] + fn _svqshrnb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqshrnb_n_s32(op1, IMM2) } +} +#[doc = "Saturating shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrnb, IMM2 = 1))] +pub fn svqshrnb_n_s64(op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrnb.nxv2i64" + )] + fn _svqshrnb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqshrnb_n_s64(op1, IMM2) } +} +#[doc = "Saturating shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshrnb, IMM2 = 1))] +pub fn svqshrnb_n_u16(op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqshrnb.nxv8i16" + )] + fn _svqshrnb_n_u16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqshrnb_n_u16(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshrnb, IMM2 = 1))] +pub fn svqshrnb_n_u32(op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqshrnb.nxv4i32" + )] + fn _svqshrnb_n_u32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqshrnb_n_u32(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshrnb, IMM2 = 1))] +pub fn svqshrnb_n_u64(op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqshrnb.nxv2i64" + )] + fn _svqshrnb_n_u64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqshrnb_n_u64(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrnt, IMM2 = 1))] +pub fn svqshrnt_n_s16(even: svint8_t, op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrnt.nxv8i16" + )] + fn _svqshrnt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqshrnt_n_s16(even, op1, IMM2) } +} +#[doc = "Saturating shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrnt, IMM2 = 1))] +pub fn svqshrnt_n_s32(even: svint16_t, op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrnt.nxv4i32" + )] + fn _svqshrnt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqshrnt_n_s32(even, op1, IMM2) } +} +#[doc = "Saturating shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrnt, IMM2 = 1))] +pub fn svqshrnt_n_s64(even: svint32_t, op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrnt.nxv2i64" + )] + fn _svqshrnt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqshrnt_n_s64(even, op1, IMM2) } +} +#[doc = "Saturating shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshrnt, IMM2 = 1))] +pub fn svqshrnt_n_u16(even: svuint8_t, op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqshrnt.nxv8i16" + )] + fn _svqshrnt_n_u16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqshrnt_n_u16(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshrnt, IMM2 = 1))] +pub fn svqshrnt_n_u32(even: svuint16_t, op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqshrnt.nxv4i32" + )] + fn _svqshrnt_n_u32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqshrnt_n_u32(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshrnt, IMM2 = 1))] +pub fn svqshrnt_n_u64(even: svuint32_t, op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqshrnt.nxv2i64" + )] + fn _svqshrnt_n_u64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqshrnt_n_u64(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating shift right unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrunb, IMM2 = 1))] +pub fn svqshrunb_n_s16(op1: svint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrunb.nxv8i16" + )] + fn _svqshrunb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqshrunb_n_s16(op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift right unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrunb, IMM2 = 1))] +pub fn svqshrunb_n_s32(op1: svint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrunb.nxv4i32" + )] + fn _svqshrunb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqshrunb_n_s32(op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift right unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrunb, IMM2 = 1))] +pub fn svqshrunb_n_s64(op1: svint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrunb.nxv2i64" + )] + fn _svqshrunb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqshrunb_n_s64(op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift right unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrunt, IMM2 = 1))] +pub fn svqshrunt_n_s16(even: svuint8_t, op1: svint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrunt.nxv8i16" + )] + fn _svqshrunt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqshrunt_n_s16(even.as_signed(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift right unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrunt, IMM2 = 1))] +pub fn svqshrunt_n_s32(even: svuint16_t, op1: svint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrunt.nxv4i32" + )] + fn _svqshrunt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqshrunt_n_s32(even.as_signed(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift right unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrunt, IMM2 = 1))] +pub fn svqshrunt_n_s64(even: svuint32_t, op1: svint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrunt.nxv2i64" + )] + fn _svqshrunt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqshrunt_n_s64(even.as_signed(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsub.nxv16i8")] + fn _svqsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqsub_s8_m(pg, op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqsub_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqsub_s8_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqsub_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqsub_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqsub_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsub.nxv8i16")] + fn _svqsub_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqsub_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqsub_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqsub_s16_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqsub_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqsub_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqsub_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsub.nxv4i32")] + fn _svqsub_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqsub_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqsub_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqsub_s32_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqsub_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqsub_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqsub_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsub.nxv2i64")] + fn _svqsub_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqsub_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqsub_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqsub_s64_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqsub_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqsub_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqsub_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsub.nxv16i8")] + fn _svqsub_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqsub_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqsub_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svqsub_u8_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqsub_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svqsub_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqsub_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsub.nxv8i16")] + fn _svqsub_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqsub_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqsub_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svqsub_u16_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqsub_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svqsub_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqsub_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsub.nxv4i32")] + fn _svqsub_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqsub_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqsub_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svqsub_u32_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqsub_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svqsub_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqsub_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsub.nxv2i64")] + fn _svqsub_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqsub_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqsub_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svqsub_u64_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqsub_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svqsub_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqsub_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsubr.nxv16i8")] + fn _svqsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqsubr_s8_m(pg, op1, op2) } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqsubr_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqsubr_s8_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqsubr_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqsubr_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqsubr_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsubr.nxv8i16")] + fn _svqsubr_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqsubr_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqsubr_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqsubr_s16_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqsubr_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqsubr_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqsubr_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsubr.nxv4i32")] + fn _svqsubr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqsubr_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqsubr_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqsubr_s32_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqsubr_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqsubr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqsubr_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsubr.nxv2i64")] + fn _svqsubr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqsubr_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqsubr_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqsubr_s64_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqsubr_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqsubr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqsubr_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsubr.nxv16i8")] + fn _svqsubr_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqsubr_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqsubr_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svqsubr_u8_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqsubr_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svqsubr_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqsubr_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsubr.nxv8i16")] + fn _svqsubr_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqsubr_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqsubr_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svqsubr_u16_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqsubr_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svqsubr_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqsubr_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsubr.nxv4i32")] + fn _svqsubr_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqsubr_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqsubr_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svqsubr_u32_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqsubr_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svqsubr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqsubr_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsubr.nxv2i64")] + fn _svqsubr_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqsubr_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqsubr_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svqsubr_u64_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqsubr_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svqsubr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqsubr_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating extract narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtnb))] +pub fn svqxtnb_s16(op: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnb.nxv8i16")] + fn _svqxtnb_s16(op: svint16_t) -> svint8_t; + } + unsafe { _svqxtnb_s16(op) } +} +#[doc = "Saturating extract narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtnb))] +pub fn svqxtnb_s32(op: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnb.nxv4i32")] + fn _svqxtnb_s32(op: svint32_t) -> svint16_t; + } + unsafe { _svqxtnb_s32(op) } +} +#[doc = "Saturating extract narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtnb))] +pub fn svqxtnb_s64(op: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnb.nxv2i64")] + fn _svqxtnb_s64(op: svint64_t) -> svint32_t; + } + unsafe { _svqxtnb_s64(op) } +} +#[doc = "Saturating extract narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqxtnb))] +pub fn svqxtnb_u16(op: svuint16_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnb.nxv8i16")] + fn _svqxtnb_u16(op: svint16_t) -> svint8_t; + } + unsafe { _svqxtnb_u16(op.as_signed()).as_unsigned() } +} +#[doc = "Saturating extract narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqxtnb))] +pub fn svqxtnb_u32(op: svuint32_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnb.nxv4i32")] + fn _svqxtnb_u32(op: svint32_t) -> svint16_t; + } + unsafe { _svqxtnb_u32(op.as_signed()).as_unsigned() } +} +#[doc = "Saturating extract narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqxtnb))] +pub fn svqxtnb_u64(op: svuint64_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnb.nxv2i64")] + fn _svqxtnb_u64(op: svint64_t) -> svint32_t; + } + unsafe { _svqxtnb_u64(op.as_signed()).as_unsigned() } +} +#[doc = "Saturating extract narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtnt))] +pub fn svqxtnt_s16(even: svint8_t, op: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnt.nxv8i16")] + fn _svqxtnt_s16(even: svint8_t, op: svint16_t) -> svint8_t; + } + unsafe { _svqxtnt_s16(even, op) } +} +#[doc = "Saturating extract narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtnt))] +pub fn svqxtnt_s32(even: svint16_t, op: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnt.nxv4i32")] + fn _svqxtnt_s32(even: svint16_t, op: svint32_t) -> svint16_t; + } + unsafe { _svqxtnt_s32(even, op) } +} +#[doc = "Saturating extract narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtnt))] +pub fn svqxtnt_s64(even: svint32_t, op: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnt.nxv2i64")] + fn _svqxtnt_s64(even: svint32_t, op: svint64_t) -> svint32_t; + } + unsafe { _svqxtnt_s64(even, op) } +} +#[doc = "Saturating extract narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqxtnt))] +pub fn svqxtnt_u16(even: svuint8_t, op: svuint16_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnt.nxv8i16")] + fn _svqxtnt_u16(even: svint8_t, op: svint16_t) -> svint8_t; + } + unsafe { _svqxtnt_u16(even.as_signed(), op.as_signed()).as_unsigned() } +} +#[doc = "Saturating extract narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqxtnt))] +pub fn svqxtnt_u32(even: svuint16_t, op: svuint32_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnt.nxv4i32")] + fn _svqxtnt_u32(even: svint16_t, op: svint32_t) -> svint16_t; + } + unsafe { _svqxtnt_u32(even.as_signed(), op.as_signed()).as_unsigned() } +} +#[doc = "Saturating extract narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqxtnt))] +pub fn svqxtnt_u64(even: svuint32_t, op: svuint64_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnt.nxv2i64")] + fn _svqxtnt_u64(even: svint32_t, op: svint64_t) -> svint32_t; + } + unsafe { _svqxtnt_u64(even.as_signed(), op.as_signed()).as_unsigned() } +} +#[doc = "Saturating extract unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtunb))] +pub fn svqxtunb_s16(op: svint16_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqxtunb.nxv8i16" + )] + fn _svqxtunb_s16(op: svint16_t) -> svint8_t; + } + unsafe { _svqxtunb_s16(op).as_unsigned() } +} +#[doc = "Saturating extract unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtunb))] +pub fn svqxtunb_s32(op: svint32_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqxtunb.nxv4i32" + )] + fn _svqxtunb_s32(op: svint32_t) -> svint16_t; + } + unsafe { _svqxtunb_s32(op).as_unsigned() } +} +#[doc = "Saturating extract unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtunb))] +pub fn svqxtunb_s64(op: svint64_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqxtunb.nxv2i64" + )] + fn _svqxtunb_s64(op: svint64_t) -> svint32_t; + } + unsafe { _svqxtunb_s64(op).as_unsigned() } +} +#[doc = "Saturating extract unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtunt))] +pub fn svqxtunt_s16(even: svuint8_t, op: svint16_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqxtunt.nxv8i16" + )] + fn _svqxtunt_s16(even: svint8_t, op: svint16_t) -> svint8_t; + } + unsafe { _svqxtunt_s16(even.as_signed(), op).as_unsigned() } +} +#[doc = "Saturating extract unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtunt))] +pub fn svqxtunt_s32(even: svuint16_t, op: svint32_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqxtunt.nxv4i32" + )] + fn _svqxtunt_s32(even: svint16_t, op: svint32_t) -> svint16_t; + } + unsafe { _svqxtunt_s32(even.as_signed(), op).as_unsigned() } +} +#[doc = "Saturating extract unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtunt))] +pub fn svqxtunt_s64(even: svuint32_t, op: svint64_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqxtunt.nxv2i64" + )] + fn _svqxtunt_s64(even: svint32_t, op: svint64_t) -> svint32_t; + } + unsafe { _svqxtunt_s64(even.as_signed(), op).as_unsigned() } +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.raddhnb.nxv8i16" + )] + fn _svraddhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svraddhnb_s16(op1, op2) } +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_n_s16(op1: svint16_t, op2: i16) -> svint8_t { + svraddhnb_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.raddhnb.nxv4i32" + )] + fn _svraddhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svraddhnb_s32(op1, op2) } +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_n_s32(op1: svint32_t, op2: i32) -> svint16_t { + svraddhnb_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.raddhnb.nxv2i64" + )] + fn _svraddhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svraddhnb_s64(op1, op2) } +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_n_s64(op1: svint64_t, op2: i64) -> svint32_t { + svraddhnb_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_u16(op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svraddhnb_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_n_u16(op1: svuint16_t, op2: u16) -> svuint8_t { + svraddhnb_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_u32(op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svraddhnb_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_n_u32(op1: svuint32_t, op2: u32) -> svuint16_t { + svraddhnb_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_u64(op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svraddhnb_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_n_u64(op1: svuint64_t, op2: u64) -> svuint32_t { + svraddhnb_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.raddhnt.nxv8i16" + )] + fn _svraddhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svraddhnt_s16(even, op1, op2) } +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_n_s16(even: svint8_t, op1: svint16_t, op2: i16) -> svint8_t { + svraddhnt_s16(even, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.raddhnt.nxv4i32" + )] + fn _svraddhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svraddhnt_s32(even, op1, op2) } +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_n_s32(even: svint16_t, op1: svint32_t, op2: i32) -> svint16_t { + svraddhnt_s32(even, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.raddhnt.nxv2i64" + )] + fn _svraddhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svraddhnt_s64(even, op1, op2) } +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_n_s64(even: svint32_t, op1: svint64_t, op2: i64) -> svint32_t { + svraddhnt_s64(even, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_u16(even: svuint8_t, op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svraddhnt_s16(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_n_u16(even: svuint8_t, op1: svuint16_t, op2: u16) -> svuint8_t { + svraddhnt_u16(even, op1, svdup_n_u16(op2)) +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_u32(even: svuint16_t, op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svraddhnt_s32(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_n_u32(even: svuint16_t, op1: svuint32_t, op2: u32) -> svuint16_t { + svraddhnt_u32(even, op1, svdup_n_u32(op2)) +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_u64(even: svuint32_t, op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svraddhnt_s64(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_n_u64(even: svuint32_t, op1: svuint64_t, op2: u64) -> svuint32_t { + svraddhnt_u64(even, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise rotate left by 1 and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrax1[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-sha3")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rax1))] +pub fn svrax1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rax1")] + fn _svrax1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svrax1_s64(op1, op2) } +} +#[doc = "Bitwise rotate left by 1 and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrax1[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-sha3")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rax1))] +pub fn svrax1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svrax1_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Reciprocal estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urecpe))] +pub fn svrecpe_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urecpe.nxv4i32")] + fn _svrecpe_u32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svrecpe_u32_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Reciprocal estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urecpe))] +pub fn svrecpe_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrecpe_u32_m(op, pg, op) +} +#[doc = "Reciprocal estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urecpe))] +pub fn svrecpe_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrecpe_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srhadd.nxv16i8")] + fn _svrhadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svrhadd_s8_m(pg, op1, op2) } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svrhadd_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svrhadd_s8_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svrhadd_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svrhadd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svrhadd_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srhadd.nxv8i16")] + fn _svrhadd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svrhadd_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svrhadd_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svrhadd_s16_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svrhadd_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svrhadd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svrhadd_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srhadd.nxv4i32")] + fn _svrhadd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svrhadd_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svrhadd_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svrhadd_s32_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svrhadd_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svrhadd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svrhadd_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srhadd.nxv2i64")] + fn _svrhadd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svrhadd_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svrhadd_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svrhadd_s64_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svrhadd_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svrhadd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svrhadd_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urhadd.nxv16i8")] + fn _svrhadd_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svrhadd_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svrhadd_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svrhadd_u8_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svrhadd_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svrhadd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svrhadd_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urhadd.nxv8i16")] + fn _svrhadd_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svrhadd_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svrhadd_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svrhadd_u16_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svrhadd_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svrhadd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svrhadd_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urhadd.nxv4i32")] + fn _svrhadd_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svrhadd_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svrhadd_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svrhadd_u32_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svrhadd_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svrhadd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svrhadd_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urhadd.nxv2i64")] + fn _svrhadd_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svrhadd_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svrhadd_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svrhadd_u64_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svrhadd_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svrhadd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svrhadd_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshl.nxv16i8")] + fn _svrshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svrshl_s8_m(pg, op1, op2) } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svrshl_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svrshl_s8_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svrshl_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svrshl_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svrshl_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshl.nxv8i16")] + fn _svrshl_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svrshl_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svrshl_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svrshl_s16_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svrshl_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svrshl_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svrshl_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshl.nxv4i32")] + fn _svrshl_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svrshl_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svrshl_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svrshl_s32_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svrshl_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svrshl_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svrshl_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshl.nxv2i64")] + fn _svrshl_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svrshl_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svrshl_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svrshl_s64_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svrshl_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svrshl_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svrshl_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u8_m(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshl.nxv16i8")] + fn _svrshl_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svrshl_u8_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svrshl_u8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u8_x(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svrshl_u8_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svrshl_u8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u8_z(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svrshl_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svrshl_u8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u16_m(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshl.nxv8i16")] + fn _svrshl_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svrshl_u16_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svrshl_u16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u16_x(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svrshl_u16_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svrshl_u16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u16_z(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svrshl_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svrshl_u16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u32_m(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshl.nxv4i32")] + fn _svrshl_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svrshl_u32_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svrshl_u32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u32_x(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svrshl_u32_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svrshl_u32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u32_z(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svrshl_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svrshl_u32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u64_m(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshl.nxv2i64")] + fn _svrshl_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svrshl_u64_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svrshl_u64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u64_x(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svrshl_u64_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svrshl_u64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u64_z(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svrshl_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svrshl_u64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s8_m(pg: svbool_t, op1: svint8_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshr.nxv16i8")] + fn _svrshr_n_s8_m(pg: svbool_t, op1: svint8_t, imm2: i32) -> svint8_t; + } + unsafe { _svrshr_n_s8_m(pg, op1, IMM2) } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s8_x(pg: svbool_t, op1: svint8_t) -> svint8_t { + svrshr_n_s8_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s8_z(pg: svbool_t, op1: svint8_t) -> svint8_t { + svrshr_n_s8_m::(pg, svsel_s8(pg, op1, svdup_n_s8(0))) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s16_m(pg: svbool_t, op1: svint16_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshr.nxv8i16")] + fn _svrshr_n_s16_m(pg: svbool8_t, op1: svint16_t, imm2: i32) -> svint16_t; + } + unsafe { _svrshr_n_s16_m(pg.sve_into(), op1, IMM2) } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s16_x(pg: svbool_t, op1: svint16_t) -> svint16_t { + svrshr_n_s16_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s16_z(pg: svbool_t, op1: svint16_t) -> svint16_t { + svrshr_n_s16_m::(pg, svsel_s16(pg, op1, svdup_n_s16(0))) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s32_m(pg: svbool_t, op1: svint32_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshr.nxv4i32")] + fn _svrshr_n_s32_m(pg: svbool4_t, op1: svint32_t, imm2: i32) -> svint32_t; + } + unsafe { _svrshr_n_s32_m(pg.sve_into(), op1, IMM2) } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s32_x(pg: svbool_t, op1: svint32_t) -> svint32_t { + svrshr_n_s32_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s32_z(pg: svbool_t, op1: svint32_t) -> svint32_t { + svrshr_n_s32_m::(pg, svsel_s32(pg, op1, svdup_n_s32(0))) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s64_m(pg: svbool_t, op1: svint64_t) -> svint64_t { + static_assert_range!(IMM2, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshr.nxv2i64")] + fn _svrshr_n_s64_m(pg: svbool2_t, op1: svint64_t, imm2: i32) -> svint64_t; + } + unsafe { _svrshr_n_s64_m(pg.sve_into(), op1, IMM2) } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s64_x(pg: svbool_t, op1: svint64_t) -> svint64_t { + svrshr_n_s64_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s64_z(pg: svbool_t, op1: svint64_t) -> svint64_t { + svrshr_n_s64_m::(pg, svsel_s64(pg, op1, svdup_n_s64(0))) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u8_m(pg: svbool_t, op1: svuint8_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshr.nxv16i8")] + fn _svrshr_n_u8_m(pg: svbool_t, op1: svint8_t, imm2: i32) -> svint8_t; + } + unsafe { _svrshr_n_u8_m(pg, op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u8_x(pg: svbool_t, op1: svuint8_t) -> svuint8_t { + svrshr_n_u8_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u8_z(pg: svbool_t, op1: svuint8_t) -> svuint8_t { + svrshr_n_u8_m::(pg, svsel_u8(pg, op1, svdup_n_u8(0))) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u16_m(pg: svbool_t, op1: svuint16_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshr.nxv8i16")] + fn _svrshr_n_u16_m(pg: svbool8_t, op1: svint16_t, imm2: i32) -> svint16_t; + } + unsafe { _svrshr_n_u16_m(pg.sve_into(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u16_x(pg: svbool_t, op1: svuint16_t) -> svuint16_t { + svrshr_n_u16_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u16_z(pg: svbool_t, op1: svuint16_t) -> svuint16_t { + svrshr_n_u16_m::(pg, svsel_u16(pg, op1, svdup_n_u16(0))) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u32_m(pg: svbool_t, op1: svuint32_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshr.nxv4i32")] + fn _svrshr_n_u32_m(pg: svbool4_t, op1: svint32_t, imm2: i32) -> svint32_t; + } + unsafe { _svrshr_n_u32_m(pg.sve_into(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u32_x(pg: svbool_t, op1: svuint32_t) -> svuint32_t { + svrshr_n_u32_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u32_z(pg: svbool_t, op1: svuint32_t) -> svuint32_t { + svrshr_n_u32_m::(pg, svsel_u32(pg, op1, svdup_n_u32(0))) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u64_m(pg: svbool_t, op1: svuint64_t) -> svuint64_t { + static_assert_range!(IMM2, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshr.nxv2i64")] + fn _svrshr_n_u64_m(pg: svbool2_t, op1: svint64_t, imm2: i32) -> svint64_t; + } + unsafe { _svrshr_n_u64_m(pg.sve_into(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u64_x(pg: svbool_t, op1: svuint64_t) -> svuint64_t { + svrshr_n_u64_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u64_z(pg: svbool_t, op1: svuint64_t) -> svuint64_t { + svrshr_n_u64_m::(pg, svsel_u64(pg, op1, svdup_n_u64(0))) +} +#[doc = "Rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))] +pub fn svrshrnb_n_s16(op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnb.nxv8i16")] + fn _svrshrnb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svrshrnb_n_s16(op1, IMM2) } +} +#[doc = "Rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))] +pub fn svrshrnb_n_s32(op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnb.nxv4i32")] + fn _svrshrnb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svrshrnb_n_s32(op1, IMM2) } +} +#[doc = "Rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))] +pub fn svrshrnb_n_s64(op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnb.nxv2i64")] + fn _svrshrnb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svrshrnb_n_s64(op1, IMM2) } +} +#[doc = "Rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))] +pub fn svrshrnb_n_u16(op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe { svrshrnb_n_s16::(op1.as_signed()).as_unsigned() } +} +#[doc = "Rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))] +pub fn svrshrnb_n_u32(op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe { svrshrnb_n_s32::(op1.as_signed()).as_unsigned() } +} +#[doc = "Rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))] +pub fn svrshrnb_n_u64(op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe { svrshrnb_n_s64::(op1.as_signed()).as_unsigned() } +} +#[doc = "Rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))] +pub fn svrshrnt_n_s16(even: svint8_t, op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnt.nxv8i16")] + fn _svrshrnt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svrshrnt_n_s16(even, op1, IMM2) } +} +#[doc = "Rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))] +pub fn svrshrnt_n_s32(even: svint16_t, op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnt.nxv4i32")] + fn _svrshrnt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svrshrnt_n_s32(even, op1, IMM2) } +} +#[doc = "Rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))] +pub fn svrshrnt_n_s64(even: svint32_t, op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnt.nxv2i64")] + fn _svrshrnt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svrshrnt_n_s64(even, op1, IMM2) } +} +#[doc = "Rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))] +pub fn svrshrnt_n_u16(even: svuint8_t, op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe { svrshrnt_n_s16::(even.as_signed(), op1.as_signed()).as_unsigned() } +} +#[doc = "Rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))] +pub fn svrshrnt_n_u32(even: svuint16_t, op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe { svrshrnt_n_s32::(even.as_signed(), op1.as_signed()).as_unsigned() } +} +#[doc = "Rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))] +pub fn svrshrnt_n_u64(even: svuint32_t, op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe { svrshrnt_n_s64::(even.as_signed(), op1.as_signed()).as_unsigned() } +} +#[doc = "Reciprocal square root estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ursqrte))] +pub fn svrsqrte_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ursqrte.nxv4i32" + )] + fn _svrsqrte_u32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svrsqrte_u32_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Reciprocal square root estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ursqrte))] +pub fn svrsqrte_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrsqrte_u32_m(op, pg, op) +} +#[doc = "Reciprocal square root estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ursqrte))] +pub fn svrsqrte_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrsqrte_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srsra, IMM3 = 1))] +pub fn svrsra_n_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srsra.nxv16i8")] + fn _svrsra_n_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svrsra_n_s8(op1, op2, IMM3) } +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srsra, IMM3 = 1))] +pub fn svrsra_n_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srsra.nxv8i16")] + fn _svrsra_n_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svrsra_n_s16(op1, op2, IMM3) } +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srsra, IMM3 = 1))] +pub fn svrsra_n_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srsra.nxv4i32")] + fn _svrsra_n_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svrsra_n_s32(op1, op2, IMM3) } +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srsra, IMM3 = 1))] +pub fn svrsra_n_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srsra.nxv2i64")] + fn _svrsra_n_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svrsra_n_s64(op1, op2, IMM3) } +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ursra, IMM3 = 1))] +pub fn svrsra_n_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ursra.nxv16i8")] + fn _svrsra_n_u8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svrsra_n_u8(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ursra, IMM3 = 1))] +pub fn svrsra_n_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ursra.nxv8i16")] + fn _svrsra_n_u16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svrsra_n_u16(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ursra, IMM3 = 1))] +pub fn svrsra_n_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ursra.nxv4i32")] + fn _svrsra_n_u32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svrsra_n_u32(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ursra, IMM3 = 1))] +pub fn svrsra_n_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ursra.nxv2i64")] + fn _svrsra_n_u64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svrsra_n_u64(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.rsubhnb.nxv8i16" + )] + fn _svrsubhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svrsubhnb_s16(op1, op2) } +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_n_s16(op1: svint16_t, op2: i16) -> svint8_t { + svrsubhnb_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.rsubhnb.nxv4i32" + )] + fn _svrsubhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svrsubhnb_s32(op1, op2) } +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_n_s32(op1: svint32_t, op2: i32) -> svint16_t { + svrsubhnb_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.rsubhnb.nxv2i64" + )] + fn _svrsubhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svrsubhnb_s64(op1, op2) } +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_n_s64(op1: svint64_t, op2: i64) -> svint32_t { + svrsubhnb_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_u16(op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svrsubhnb_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_n_u16(op1: svuint16_t, op2: u16) -> svuint8_t { + svrsubhnb_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_u32(op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svrsubhnb_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_n_u32(op1: svuint32_t, op2: u32) -> svuint16_t { + svrsubhnb_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_u64(op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svrsubhnb_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_n_u64(op1: svuint64_t, op2: u64) -> svuint32_t { + svrsubhnb_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.rsubhnt.nxv8i16" + )] + fn _svrsubhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svrsubhnt_s16(even, op1, op2) } +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_n_s16(even: svint8_t, op1: svint16_t, op2: i16) -> svint8_t { + svrsubhnt_s16(even, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.rsubhnt.nxv4i32" + )] + fn _svrsubhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svrsubhnt_s32(even, op1, op2) } +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_n_s32(even: svint16_t, op1: svint32_t, op2: i32) -> svint16_t { + svrsubhnt_s32(even, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.rsubhnt.nxv2i64" + )] + fn _svrsubhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svrsubhnt_s64(even, op1, op2) } +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_n_s64(even: svint32_t, op1: svint64_t, op2: i64) -> svint32_t { + svrsubhnt_s64(even, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_u16(even: svuint8_t, op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svrsubhnt_s16(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_n_u16(even: svuint8_t, op1: svuint16_t, op2: u16) -> svuint8_t { + svrsubhnt_u16(even, op1, svdup_n_u16(op2)) +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_u32(even: svuint16_t, op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svrsubhnt_s32(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_n_u32(even: svuint16_t, op1: svuint32_t, op2: u32) -> svuint16_t { + svrsubhnt_u32(even, op1, svdup_n_u32(op2)) +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_u64(even: svuint32_t, op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svrsubhnt_s64(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_n_u64(even: svuint32_t, op1: svuint64_t, op2: u64) -> svuint32_t { + svrsubhnt_u64(even, op1, svdup_n_u64(op2)) +} +#[doc = "Subtract with borrow long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclb))] +pub fn svsbclb_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sbclb.nxv4i32")] + fn _svsbclb_u32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svsbclb_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Subtract with borrow long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclb))] +pub fn svsbclb_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svsbclb_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Subtract with borrow long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclb))] +pub fn svsbclb_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sbclb.nxv2i64")] + fn _svsbclb_u64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svsbclb_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Subtract with borrow long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclb))] +pub fn svsbclb_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svsbclb_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Subtract with borrow long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclt))] +pub fn svsbclt_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sbclt.nxv4i32")] + fn _svsbclt_u32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svsbclt_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Subtract with borrow long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclt))] +pub fn svsbclt_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svsbclt_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Subtract with borrow long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclt))] +pub fn svsbclt_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sbclt.nxv2i64")] + fn _svsbclt_u64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svsbclt_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Subtract with borrow long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclt))] +pub fn svsbclt_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svsbclt_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Shift left long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllb, IMM2 = 0))] +pub fn svshllb_n_s16(op1: svint8_t) -> svint16_t { + static_assert_range!(IMM2, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllb.nxv8i16")] + fn _svshllb_n_s16(op1: svint8_t, imm2: i32) -> svint16_t; + } + unsafe { _svshllb_n_s16(op1, IMM2) } +} +#[doc = "Shift left long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllb, IMM2 = 0))] +pub fn svshllb_n_s32(op1: svint16_t) -> svint32_t { + static_assert_range!(IMM2, 0..=15); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllb.nxv4i32")] + fn _svshllb_n_s32(op1: svint16_t, imm2: i32) -> svint32_t; + } + unsafe { _svshllb_n_s32(op1, IMM2) } +} +#[doc = "Shift left long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllb, IMM2 = 0))] +pub fn svshllb_n_s64(op1: svint32_t) -> svint64_t { + static_assert_range!(IMM2, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllb.nxv2i64")] + fn _svshllb_n_s64(op1: svint32_t, imm2: i32) -> svint64_t; + } + unsafe { _svshllb_n_s64(op1, IMM2) } +} +#[doc = "Shift left long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllb, IMM2 = 0))] +pub fn svshllb_n_u16(op1: svuint8_t) -> svuint16_t { + static_assert_range!(IMM2, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllb.nxv8i16")] + fn _svshllb_n_u16(op1: svint8_t, imm2: i32) -> svint16_t; + } + unsafe { _svshllb_n_u16(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Shift left long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllb, IMM2 = 0))] +pub fn svshllb_n_u32(op1: svuint16_t) -> svuint32_t { + static_assert_range!(IMM2, 0..=15); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllb.nxv4i32")] + fn _svshllb_n_u32(op1: svint16_t, imm2: i32) -> svint32_t; + } + unsafe { _svshllb_n_u32(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Shift left long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllb, IMM2 = 0))] +pub fn svshllb_n_u64(op1: svuint32_t) -> svuint64_t { + static_assert_range!(IMM2, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllb.nxv2i64")] + fn _svshllb_n_u64(op1: svint32_t, imm2: i32) -> svint64_t; + } + unsafe { _svshllb_n_u64(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Shift left long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllt, IMM2 = 0))] +pub fn svshllt_n_s16(op1: svint8_t) -> svint16_t { + static_assert_range!(IMM2, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllt.nxv8i16")] + fn _svshllt_n_s16(op1: svint8_t, imm2: i32) -> svint16_t; + } + unsafe { _svshllt_n_s16(op1, IMM2) } +} +#[doc = "Shift left long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllt, IMM2 = 0))] +pub fn svshllt_n_s32(op1: svint16_t) -> svint32_t { + static_assert_range!(IMM2, 0..=15); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllt.nxv4i32")] + fn _svshllt_n_s32(op1: svint16_t, imm2: i32) -> svint32_t; + } + unsafe { _svshllt_n_s32(op1, IMM2) } +} +#[doc = "Shift left long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllt, IMM2 = 0))] +pub fn svshllt_n_s64(op1: svint32_t) -> svint64_t { + static_assert_range!(IMM2, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllt.nxv2i64")] + fn _svshllt_n_s64(op1: svint32_t, imm2: i32) -> svint64_t; + } + unsafe { _svshllt_n_s64(op1, IMM2) } +} +#[doc = "Shift left long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllt, IMM2 = 0))] +pub fn svshllt_n_u16(op1: svuint8_t) -> svuint16_t { + static_assert_range!(IMM2, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllt.nxv8i16")] + fn _svshllt_n_u16(op1: svint8_t, imm2: i32) -> svint16_t; + } + unsafe { _svshllt_n_u16(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Shift left long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllt, IMM2 = 0))] +pub fn svshllt_n_u32(op1: svuint16_t) -> svuint32_t { + static_assert_range!(IMM2, 0..=15); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllt.nxv4i32")] + fn _svshllt_n_u32(op1: svint16_t, imm2: i32) -> svint32_t; + } + unsafe { _svshllt_n_u32(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Shift left long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllt, IMM2 = 0))] +pub fn svshllt_n_u64(op1: svuint32_t) -> svuint64_t { + static_assert_range!(IMM2, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllt.nxv2i64")] + fn _svshllt_n_u64(op1: svint32_t, imm2: i32) -> svint64_t; + } + unsafe { _svshllt_n_u64(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))] +pub fn svshrnb_n_s16(op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnb.nxv8i16")] + fn _svshrnb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svshrnb_n_s16(op1, IMM2) } +} +#[doc = "Shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))] +pub fn svshrnb_n_s32(op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnb.nxv4i32")] + fn _svshrnb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svshrnb_n_s32(op1, IMM2) } +} +#[doc = "Shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))] +pub fn svshrnb_n_s64(op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnb.nxv2i64")] + fn _svshrnb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svshrnb_n_s64(op1, IMM2) } +} +#[doc = "Shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))] +pub fn svshrnb_n_u16(op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe { svshrnb_n_s16::(op1.as_signed()).as_unsigned() } +} +#[doc = "Shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))] +pub fn svshrnb_n_u32(op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe { svshrnb_n_s32::(op1.as_signed()).as_unsigned() } +} +#[doc = "Shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))] +pub fn svshrnb_n_u64(op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe { svshrnb_n_s64::(op1.as_signed()).as_unsigned() } +} +#[doc = "Shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))] +pub fn svshrnt_n_s16(even: svint8_t, op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnt.nxv8i16")] + fn _svshrnt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svshrnt_n_s16(even, op1, IMM2) } +} +#[doc = "Shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))] +pub fn svshrnt_n_s32(even: svint16_t, op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnt.nxv4i32")] + fn _svshrnt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svshrnt_n_s32(even, op1, IMM2) } +} +#[doc = "Shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))] +pub fn svshrnt_n_s64(even: svint32_t, op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnt.nxv2i64")] + fn _svshrnt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svshrnt_n_s64(even, op1, IMM2) } +} +#[doc = "Shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))] +pub fn svshrnt_n_u16(even: svuint8_t, op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe { svshrnt_n_s16::(even.as_signed(), op1.as_signed()).as_unsigned() } +} +#[doc = "Shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))] +pub fn svshrnt_n_u32(even: svuint16_t, op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe { svshrnt_n_s32::(even.as_signed(), op1.as_signed()).as_unsigned() } +} +#[doc = "Shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))] +pub fn svshrnt_n_u64(even: svuint32_t, op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe { svshrnt_n_s64::(even.as_signed(), op1.as_signed()).as_unsigned() } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert_range!(IMM3, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sli.nxv16i8")] + fn _svsli_n_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svsli_n_s8(op1, op2, IMM3) } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM3, 0..=15); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sli.nxv8i16")] + fn _svsli_n_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svsli_n_s16(op1, op2, IMM3) } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM3, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sli.nxv4i32")] + fn _svsli_n_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svsli_n_s32(op1, op2, IMM3) } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM3, 0..=63); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sli.nxv2i64")] + fn _svsli_n_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svsli_n_s64(op1, op2, IMM3) } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + static_assert_range!(IMM3, 0..=7); + unsafe { svsli_n_s8::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert_range!(IMM3, 0..=15); + unsafe { svsli_n_s16::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert_range!(IMM3, 0..=31); + unsafe { svsli_n_s32::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert_range!(IMM3, 0..=63); + unsafe { svsli_n_s64::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "SM4 encryption and decryption"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsm4e[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-sm4")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sm4e))] +pub fn svsm4e_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sm4e")] + fn _svsm4e_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svsm4e_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "SM4 key updates"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsm4ekey[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-sm4")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sm4ekey))] +pub fn svsm4ekey_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sm4ekey")] + fn _svsm4ekey_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svsm4ekey_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usqadd.nxv16i8")] + fn _svsqadd_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svsqadd_u8_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svsqadd_u8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svsqadd_u8_m(pg, op1, op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svsqadd_u8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svsqadd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svsqadd_u8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usqadd.nxv8i16")] + fn _svsqadd_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svsqadd_u16_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svsqadd_u16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svsqadd_u16_m(pg, op1, op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svsqadd_u16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svsqadd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svsqadd_u16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usqadd.nxv4i32")] + fn _svsqadd_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svsqadd_u32_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svsqadd_u32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svsqadd_u32_m(pg, op1, op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svsqadd_u32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svsqadd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svsqadd_u32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usqadd.nxv2i64")] + fn _svsqadd_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svsqadd_u64_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svsqadd_u64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svsqadd_u64_m(pg, op1, op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svsqadd_u64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svsqadd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svsqadd_u64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssra, IMM3 = 1))] +pub fn svsra_n_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssra.nxv16i8")] + fn _svsra_n_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svsra_n_s8(op1, op2, IMM3) } +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssra, IMM3 = 1))] +pub fn svsra_n_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssra.nxv8i16")] + fn _svsra_n_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svsra_n_s16(op1, op2, IMM3) } +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssra, IMM3 = 1))] +pub fn svsra_n_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssra.nxv4i32")] + fn _svsra_n_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svsra_n_s32(op1, op2, IMM3) } +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssra, IMM3 = 1))] +pub fn svsra_n_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssra.nxv2i64")] + fn _svsra_n_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svsra_n_s64(op1, op2, IMM3) } +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usra, IMM3 = 1))] +pub fn svsra_n_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usra.nxv16i8")] + fn _svsra_n_u8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svsra_n_u8(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usra, IMM3 = 1))] +pub fn svsra_n_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usra.nxv8i16")] + fn _svsra_n_u16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svsra_n_u16(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usra, IMM3 = 1))] +pub fn svsra_n_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usra.nxv4i32")] + fn _svsra_n_u32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svsra_n_u32(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usra, IMM3 = 1))] +pub fn svsra_n_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usra.nxv2i64")] + fn _svsra_n_u64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svsra_n_u64(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sri.nxv16i8")] + fn _svsri_n_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svsri_n_s8(op1, op2, IMM3) } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sri.nxv8i16")] + fn _svsri_n_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svsri_n_s16(op1, op2, IMM3) } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sri.nxv4i32")] + fn _svsri_n_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svsri_n_s32(op1, op2, IMM3) } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sri.nxv2i64")] + fn _svsri_n_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svsri_n_s64(op1, op2, IMM3) } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe { svsri_n_s8::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe { svsri_n_s16::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe { svsri_n_s32::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe { svsri_n_s64::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_s64index_f64( + pg: svbool_t, + base: *mut f64, + indices: svint64_t, + data: svfloat64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.index.nxv2f64" + )] + fn _svstnt1_scatter_s64index_f64( + data: svfloat64_t, + pg: svbool2_t, + base: *mut f64, + indices: svint64_t, + ); + } + _svstnt1_scatter_s64index_f64(data, pg.sve_into(), base, indices) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_s64index_s64( + pg: svbool_t, + base: *mut i64, + indices: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.index.nxv2i64" + )] + fn _svstnt1_scatter_s64index_s64( + data: svint64_t, + pg: svbool2_t, + base: *mut i64, + indices: svint64_t, + ); + } + _svstnt1_scatter_s64index_s64(data, pg.sve_into(), base, indices) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_s64index_u64( + pg: svbool_t, + base: *mut u64, + indices: svint64_t, + data: svuint64_t, +) { + svstnt1_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64index_f64( + pg: svbool_t, + base: *mut f64, + indices: svuint64_t, + data: svfloat64_t, +) { + svstnt1_scatter_s64index_f64(pg, base, indices.as_signed(), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64index_s64( + pg: svbool_t, + base: *mut i64, + indices: svuint64_t, + data: svint64_t, +) { + svstnt1_scatter_s64index_s64(pg, base, indices.as_signed(), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64index_u64( + pg: svbool_t, + base: *mut u64, + indices: svuint64_t, + data: svuint64_t, +) { + svstnt1_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_s64offset_f64( + pg: svbool_t, + base: *mut f64, + offsets: svint64_t, + data: svfloat64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.nxv2f64" + )] + fn _svstnt1_scatter_s64offset_f64( + data: svfloat64_t, + pg: svbool2_t, + base: *mut f64, + offsets: svint64_t, + ); + } + _svstnt1_scatter_s64offset_f64(data, pg.sve_into(), base, offsets) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i64, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.nxv2i64" + )] + fn _svstnt1_scatter_s64offset_s64( + data: svint64_t, + pg: svbool2_t, + base: *mut i64, + offsets: svint64_t, + ); + } + _svstnt1_scatter_s64offset_s64(data, pg.sve_into(), base, offsets) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u64, + offsets: svint64_t, + data: svuint64_t, +) { + svstnt1_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32offset_f32( + pg: svbool_t, + base: *mut f32, + offsets: svuint32_t, + data: svfloat32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4f32" + )] + fn _svstnt1_scatter_u32offset_f32( + data: svfloat32_t, + pg: svbool4_t, + base: *mut f32, + offsets: svint32_t, + ); + } + _svstnt1_scatter_u32offset_f32(data, pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32offset_s32( + pg: svbool_t, + base: *mut i32, + offsets: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4i32" + )] + fn _svstnt1_scatter_u32offset_s32( + data: svint32_t, + pg: svbool4_t, + base: *mut i32, + offsets: svint32_t, + ); + } + _svstnt1_scatter_u32offset_s32(data, pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32offset_u32( + pg: svbool_t, + base: *mut u32, + offsets: svuint32_t, + data: svuint32_t, +) { + svstnt1_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64offset_f64( + pg: svbool_t, + base: *mut f64, + offsets: svuint64_t, + data: svfloat64_t, +) { + svstnt1_scatter_s64offset_f64(pg, base, offsets.as_signed(), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i64, + offsets: svuint64_t, + data: svint64_t, +) { + svstnt1_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u64, + offsets: svuint64_t, + data: svuint64_t, +) { + svstnt1_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_f32(pg: svbool_t, bases: svuint32_t, data: svfloat32_t) { + svstnt1_scatter_u32base_offset_f32(pg, bases, 0, data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) { + svstnt1_scatter_u32base_offset_s32(pg, bases, 0, data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) { + svstnt1_scatter_u32base_offset_u32(pg, bases, 0, data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_f64(pg: svbool_t, bases: svuint64_t, data: svfloat64_t) { + svstnt1_scatter_u64base_offset_f64(pg, bases, 0, data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svstnt1_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svstnt1_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_index_f32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svfloat32_t, +) { + svstnt1_scatter_u32base_offset_f32(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svint32_t, +) { + svstnt1_scatter_u32base_offset_s32(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svuint32_t, +) { + svstnt1_scatter_u32base_offset_u32(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_index_f64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svfloat64_t, +) { + svstnt1_scatter_u64base_offset_f64(pg, bases, index.unchecked_shl(3), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svint64_t, +) { + svstnt1_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(3), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svuint64_t, +) { + svstnt1_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(3), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_offset_f32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svfloat32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4f32.nxv4i32" + )] + fn _svstnt1_scatter_u32base_offset_f32( + data: svfloat32_t, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svstnt1_scatter_u32base_offset_f32(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i32.nxv4i32" + )] + fn _svstnt1_scatter_u32base_offset_s32( + data: svint32_t, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svstnt1_scatter_u32base_offset_s32(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svuint32_t, +) { + svstnt1_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_offset_f64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svfloat64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2f64.nxv2i64" + )] + fn _svstnt1_scatter_u64base_offset_f64( + data: svfloat64_t, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svstnt1_scatter_u64base_offset_f64(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i64.nxv2i64" + )] + fn _svstnt1_scatter_u64base_offset_s64( + data: svint64_t, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svstnt1_scatter_u64base_offset_s64(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svstnt1_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i8, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.nxv2i8" + )] + fn _svstnt1b_scatter_s64offset_s64( + data: nxv2i8, + pg: svbool2_t, + base: *mut i8, + offsets: svint64_t, + ); + } + _svstnt1b_scatter_s64offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i16, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.nxv2i16" + )] + fn _svstnt1h_scatter_s64offset_s64( + data: nxv2i16, + pg: svbool2_t, + base: *mut i16, + offsets: svint64_t, + ); + } + _svstnt1h_scatter_s64offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i32, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.nxv2i32" + )] + fn _svstnt1w_scatter_s64offset_s64( + data: nxv2i32, + pg: svbool2_t, + base: *mut i32, + offsets: svint64_t, + ); + } + _svstnt1w_scatter_s64offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u8, + offsets: svint64_t, + data: svuint64_t, +) { + svstnt1b_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u16, + offsets: svint64_t, + data: svuint64_t, +) { + svstnt1h_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u32, + offsets: svint64_t, + data: svuint64_t, +) { + svstnt1w_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u32offset_s32( + pg: svbool_t, + base: *mut i8, + offsets: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4i8" + )] + fn _svstnt1b_scatter_u32offset_s32( + data: nxv4i8, + pg: svbool4_t, + base: *mut i8, + offsets: svint32_t, + ); + } + _svstnt1b_scatter_u32offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets.as_signed(), + ) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32offset_s32( + pg: svbool_t, + base: *mut i16, + offsets: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4i16" + )] + fn _svstnt1h_scatter_u32offset_s32( + data: nxv4i16, + pg: svbool4_t, + base: *mut i16, + offsets: svint32_t, + ); + } + _svstnt1h_scatter_u32offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets.as_signed(), + ) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u32offset_u32( + pg: svbool_t, + base: *mut u8, + offsets: svuint32_t, + data: svuint32_t, +) { + svstnt1b_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32offset_u32( + pg: svbool_t, + base: *mut u16, + offsets: svuint32_t, + data: svuint32_t, +) { + svstnt1h_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i8, + offsets: svuint64_t, + data: svint64_t, +) { + svstnt1b_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i16, + offsets: svuint64_t, + data: svint64_t, +) { + svstnt1h_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i32, + offsets: svuint64_t, + data: svint64_t, +) { + svstnt1w_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u8, + offsets: svuint64_t, + data: svuint64_t, +) { + svstnt1b_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u16, + offsets: svuint64_t, + data: svuint64_t, +) { + svstnt1h_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u32, + offsets: svuint64_t, + data: svuint64_t, +) { + svstnt1w_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u32base]_offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svstnt1b_scatter_u32base_offset_s32( + data: nxv4i8, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svstnt1b_scatter_u32base_offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base]_offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svstnt1h_scatter_u32base_offset_s32( + data: nxv4i16, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svstnt1h_scatter_u32base_offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u32base]_offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svuint32_t, +) { + svstnt1b_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base]_offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svuint32_t, +) { + svstnt1h_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svstnt1b_scatter_u64base_offset_s64( + data: nxv2i8, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svstnt1b_scatter_u64base_offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svstnt1h_scatter_u64base_offset_s64( + data: nxv2i16, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svstnt1h_scatter_u64base_offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svstnt1w_scatter_u64base_offset_s64( + data: nxv2i32, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svstnt1w_scatter_u64base_offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svstnt1b_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svstnt1h_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svstnt1w_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u32base_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) { + svstnt1b_scatter_u32base_offset_s32(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) { + svstnt1h_scatter_u32base_offset_s32(pg, bases, 0, data) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u32base_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) { + svstnt1b_scatter_u32base_offset_u32(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) { + svstnt1h_scatter_u32base_offset_u32(pg, bases, 0, data) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svstnt1b_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svstnt1h_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svstnt1w_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svstnt1b_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svstnt1h_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svstnt1w_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_s64index_s64( + pg: svbool_t, + base: *mut i16, + indices: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.index.nxv2i16" + )] + fn _svstnt1h_scatter_s64index_s64( + data: nxv2i16, + pg: svbool2_t, + base: *mut i16, + indices: svint64_t, + ); + } + _svstnt1h_scatter_s64index_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + indices, + ) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_s64index_s64( + pg: svbool_t, + base: *mut i32, + indices: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.index.nxv2i32" + )] + fn _svstnt1w_scatter_s64index_s64( + data: nxv2i32, + pg: svbool2_t, + base: *mut i32, + indices: svint64_t, + ); + } + _svstnt1w_scatter_s64index_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + indices, + ) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_s64index_u64( + pg: svbool_t, + base: *mut u16, + indices: svint64_t, + data: svuint64_t, +) { + svstnt1h_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_s64index_u64( + pg: svbool_t, + base: *mut u32, + indices: svint64_t, + data: svuint64_t, +) { + svstnt1w_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64index_s64( + pg: svbool_t, + base: *mut i16, + indices: svuint64_t, + data: svint64_t, +) { + svstnt1h_scatter_s64index_s64(pg, base, indices.as_signed(), data) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64index_s64( + pg: svbool_t, + base: *mut i32, + indices: svuint64_t, + data: svint64_t, +) { + svstnt1w_scatter_s64index_s64(pg, base, indices.as_signed(), data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64index_u64( + pg: svbool_t, + base: *mut u16, + indices: svuint64_t, + data: svuint64_t, +) { + svstnt1h_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64index_u64( + pg: svbool_t, + base: *mut u32, + indices: svuint64_t, + data: svuint64_t, +) { + svstnt1w_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base]_index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svint32_t, +) { + svstnt1h_scatter_u32base_offset_s32(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base]_index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svuint32_t, +) { + svstnt1h_scatter_u32base_offset_u32(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base]_index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svint64_t, +) { + svstnt1h_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base]_index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svint64_t, +) { + svstnt1w_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base]_index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svuint64_t, +) { + svstnt1h_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base]_index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svuint64_t, +) { + svstnt1w_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnb.nxv8i16")] + fn _svsubhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svsubhnb_s16(op1, op2) } +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_n_s16(op1: svint16_t, op2: i16) -> svint8_t { + svsubhnb_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnb.nxv4i32")] + fn _svsubhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svsubhnb_s32(op1, op2) } +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_n_s32(op1: svint32_t, op2: i32) -> svint16_t { + svsubhnb_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnb.nxv2i64")] + fn _svsubhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svsubhnb_s64(op1, op2) } +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_n_s64(op1: svint64_t, op2: i64) -> svint32_t { + svsubhnb_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_u16(op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svsubhnb_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_n_u16(op1: svuint16_t, op2: u16) -> svuint8_t { + svsubhnb_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_u32(op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svsubhnb_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_n_u32(op1: svuint32_t, op2: u32) -> svuint16_t { + svsubhnb_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_u64(op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svsubhnb_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_n_u64(op1: svuint64_t, op2: u64) -> svuint32_t { + svsubhnb_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnt.nxv8i16")] + fn _svsubhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svsubhnt_s16(even, op1, op2) } +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_n_s16(even: svint8_t, op1: svint16_t, op2: i16) -> svint8_t { + svsubhnt_s16(even, op1, svdup_n_s16(op2)) +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnt.nxv4i32")] + fn _svsubhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svsubhnt_s32(even, op1, op2) } +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_n_s32(even: svint16_t, op1: svint32_t, op2: i32) -> svint16_t { + svsubhnt_s32(even, op1, svdup_n_s32(op2)) +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnt.nxv2i64")] + fn _svsubhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svsubhnt_s64(even, op1, op2) } +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_n_s64(even: svint32_t, op1: svint64_t, op2: i64) -> svint32_t { + svsubhnt_s64(even, op1, svdup_n_s64(op2)) +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_u16(even: svuint8_t, op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svsubhnt_s16(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_n_u16(even: svuint8_t, op1: svuint16_t, op2: u16) -> svuint8_t { + svsubhnt_u16(even, op1, svdup_n_u16(op2)) +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_u32(even: svuint16_t, op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svsubhnt_s32(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_n_u32(even: svuint16_t, op1: svuint32_t, op2: u32) -> svuint16_t { + svsubhnt_u32(even, op1, svdup_n_u32(op2)) +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_u64(even: svuint32_t, op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svsubhnt_s64(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_n_u64(even: svuint32_t, op1: svuint64_t, op2: u64) -> svuint32_t { + svsubhnt_u64(even, op1, svdup_n_u64(op2)) +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublb))] +pub fn svsublb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublb.nxv8i16")] + fn _svsublb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsublb_s16(op1, op2) } +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublb))] +pub fn svsublb_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svsublb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublb))] +pub fn svsublb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublb.nxv4i32")] + fn _svsublb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsublb_s32(op1, op2) } +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublb))] +pub fn svsublb_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svsublb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublb))] +pub fn svsublb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublb.nxv2i64")] + fn _svsublb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsublb_s64(op1, op2) } +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublb))] +pub fn svsublb_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svsublb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublb))] +pub fn svsublb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublb.nxv8i16")] + fn _svsublb_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsublb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublb))] +pub fn svsublb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svsublb_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublb))] +pub fn svsublb_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublb.nxv4i32")] + fn _svsublb_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsublb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublb))] +pub fn svsublb_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svsublb_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublb))] +pub fn svsublb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublb.nxv2i64")] + fn _svsublb_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsublb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublb))] +pub fn svsublb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svsublb_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Subtract long (bottom - top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublbt))] +pub fn svsublbt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ssublbt.nxv8i16" + )] + fn _svsublbt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsublbt_s16(op1, op2) } +} +#[doc = "Subtract long (bottom - top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublbt))] +pub fn svsublbt_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svsublbt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Subtract long (bottom - top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublbt))] +pub fn svsublbt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ssublbt.nxv4i32" + )] + fn _svsublbt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsublbt_s32(op1, op2) } +} +#[doc = "Subtract long (bottom - top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublbt))] +pub fn svsublbt_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svsublbt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Subtract long (bottom - top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublbt))] +pub fn svsublbt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ssublbt.nxv2i64" + )] + fn _svsublbt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsublbt_s64(op1, op2) } +} +#[doc = "Subtract long (bottom - top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublbt))] +pub fn svsublbt_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svsublbt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublt))] +pub fn svsublt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublt.nxv8i16")] + fn _svsublt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsublt_s16(op1, op2) } +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublt))] +pub fn svsublt_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svsublt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublt))] +pub fn svsublt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublt.nxv4i32")] + fn _svsublt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsublt_s32(op1, op2) } +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublt))] +pub fn svsublt_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svsublt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublt))] +pub fn svsublt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublt.nxv2i64")] + fn _svsublt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsublt_s64(op1, op2) } +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublt))] +pub fn svsublt_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svsublt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublt))] +pub fn svsublt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublt.nxv8i16")] + fn _svsublt_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsublt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublt))] +pub fn svsublt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svsublt_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublt))] +pub fn svsublt_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublt.nxv4i32")] + fn _svsublt_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsublt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublt))] +pub fn svsublt_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svsublt_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublt))] +pub fn svsublt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublt.nxv2i64")] + fn _svsublt_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsublt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublt))] +pub fn svsublt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svsublt_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Subtract long (top - bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubltb))] +pub fn svsubltb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ssubltb.nxv8i16" + )] + fn _svsubltb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsubltb_s16(op1, op2) } +} +#[doc = "Subtract long (top - bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubltb))] +pub fn svsubltb_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svsubltb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Subtract long (top - bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubltb))] +pub fn svsubltb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ssubltb.nxv4i32" + )] + fn _svsubltb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsubltb_s32(op1, op2) } +} +#[doc = "Subtract long (top - bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubltb))] +pub fn svsubltb_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svsubltb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Subtract long (top - bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubltb))] +pub fn svsubltb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ssubltb.nxv2i64" + )] + fn _svsubltb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsubltb_s64(op1, op2) } +} +#[doc = "Subtract long (top - bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubltb))] +pub fn svsubltb_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svsubltb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwb))] +pub fn svsubwb_s16(op1: svint16_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwb.nxv8i16")] + fn _svsubwb_s16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsubwb_s16(op1, op2) } +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwb))] +pub fn svsubwb_n_s16(op1: svint16_t, op2: i8) -> svint16_t { + svsubwb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwb))] +pub fn svsubwb_s32(op1: svint32_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwb.nxv4i32")] + fn _svsubwb_s32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsubwb_s32(op1, op2) } +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwb))] +pub fn svsubwb_n_s32(op1: svint32_t, op2: i16) -> svint32_t { + svsubwb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwb))] +pub fn svsubwb_s64(op1: svint64_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwb.nxv2i64")] + fn _svsubwb_s64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsubwb_s64(op1, op2) } +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwb))] +pub fn svsubwb_n_s64(op1: svint64_t, op2: i32) -> svint64_t { + svsubwb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwb))] +pub fn svsubwb_u16(op1: svuint16_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwb.nxv8i16")] + fn _svsubwb_u16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsubwb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwb))] +pub fn svsubwb_n_u16(op1: svuint16_t, op2: u8) -> svuint16_t { + svsubwb_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwb))] +pub fn svsubwb_u32(op1: svuint32_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwb.nxv4i32")] + fn _svsubwb_u32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsubwb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwb))] +pub fn svsubwb_n_u32(op1: svuint32_t, op2: u16) -> svuint32_t { + svsubwb_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwb))] +pub fn svsubwb_u64(op1: svuint64_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwb.nxv2i64")] + fn _svsubwb_u64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsubwb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwb))] +pub fn svsubwb_n_u64(op1: svuint64_t, op2: u32) -> svuint64_t { + svsubwb_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwt))] +pub fn svsubwt_s16(op1: svint16_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwt.nxv8i16")] + fn _svsubwt_s16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsubwt_s16(op1, op2) } +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwt))] +pub fn svsubwt_n_s16(op1: svint16_t, op2: i8) -> svint16_t { + svsubwt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwt))] +pub fn svsubwt_s32(op1: svint32_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwt.nxv4i32")] + fn _svsubwt_s32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsubwt_s32(op1, op2) } +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwt))] +pub fn svsubwt_n_s32(op1: svint32_t, op2: i16) -> svint32_t { + svsubwt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwt))] +pub fn svsubwt_s64(op1: svint64_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwt.nxv2i64")] + fn _svsubwt_s64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsubwt_s64(op1, op2) } +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwt))] +pub fn svsubwt_n_s64(op1: svint64_t, op2: i32) -> svint64_t { + svsubwt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwt))] +pub fn svsubwt_u16(op1: svuint16_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwt.nxv8i16")] + fn _svsubwt_u16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsubwt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwt))] +pub fn svsubwt_n_u16(op1: svuint16_t, op2: u8) -> svuint16_t { + svsubwt_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwt))] +pub fn svsubwt_u32(op1: svuint32_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwt.nxv4i32")] + fn _svsubwt_u32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsubwt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwt))] +pub fn svsubwt_n_u32(op1: svuint32_t, op2: u16) -> svuint32_t { + svsubwt_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwt))] +pub fn svsubwt_u64(op1: svuint64_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwt.nxv2i64")] + fn _svsubwt_u64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsubwt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwt))] +pub fn svsubwt_n_u64(op1: svuint64_t, op2: u32) -> svuint64_t { + svsubwt_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_f32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_f32(data: svfloat32x2_t, indices: svuint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv4f32")] + fn _svtbl2_f32(data0: svfloat32_t, data1: svfloat32_t, indices: svint32_t) -> svfloat32_t; + } + unsafe { + _svtbl2_f32( + svget2_f32::<0>(data), + svget2_f32::<1>(data), + indices.as_signed(), + ) + } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_f64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_f64(data: svfloat64x2_t, indices: svuint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv2f64")] + fn _svtbl2_f64(data0: svfloat64_t, data1: svfloat64_t, indices: svint64_t) -> svfloat64_t; + } + unsafe { + _svtbl2_f64( + svget2_f64::<0>(data), + svget2_f64::<1>(data), + indices.as_signed(), + ) + } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_s8(data: svint8x2_t, indices: svuint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv16i8")] + fn _svtbl2_s8(data0: svint8_t, data1: svint8_t, indices: svint8_t) -> svint8_t; + } + unsafe { + _svtbl2_s8( + svget2_s8::<0>(data), + svget2_s8::<1>(data), + indices.as_signed(), + ) + } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_s16(data: svint16x2_t, indices: svuint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv8i16")] + fn _svtbl2_s16(data0: svint16_t, data1: svint16_t, indices: svint16_t) -> svint16_t; + } + unsafe { + _svtbl2_s16( + svget2_s16::<0>(data), + svget2_s16::<1>(data), + indices.as_signed(), + ) + } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_s32(data: svint32x2_t, indices: svuint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv4i32")] + fn _svtbl2_s32(data0: svint32_t, data1: svint32_t, indices: svint32_t) -> svint32_t; + } + unsafe { + _svtbl2_s32( + svget2_s32::<0>(data), + svget2_s32::<1>(data), + indices.as_signed(), + ) + } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_s64(data: svint64x2_t, indices: svuint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv2i64")] + fn _svtbl2_s64(data0: svint64_t, data1: svint64_t, indices: svint64_t) -> svint64_t; + } + unsafe { + _svtbl2_s64( + svget2_s64::<0>(data), + svget2_s64::<1>(data), + indices.as_signed(), + ) + } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_u8(data: svuint8x2_t, indices: svuint8_t) -> svuint8_t { + unsafe { svtbl2_s8(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_u16(data: svuint16x2_t, indices: svuint16_t) -> svuint16_t { + unsafe { svtbl2_s16(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_u32(data: svuint32x2_t, indices: svuint32_t) -> svuint32_t { + unsafe { svtbl2_s32(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_u64(data: svuint64x2_t, indices: svuint64_t) -> svuint64_t { + unsafe { svtbl2_s64(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_f32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_f32(fallback: svfloat32_t, data: svfloat32_t, indices: svuint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv4f32")] + fn _svtbx_f32(fallback: svfloat32_t, data: svfloat32_t, indices: svint32_t) -> svfloat32_t; + } + unsafe { _svtbx_f32(fallback, data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_f64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_f64(fallback: svfloat64_t, data: svfloat64_t, indices: svuint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv2f64")] + fn _svtbx_f64(fallback: svfloat64_t, data: svfloat64_t, indices: svint64_t) -> svfloat64_t; + } + unsafe { _svtbx_f64(fallback, data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_s8(fallback: svint8_t, data: svint8_t, indices: svuint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv16i8")] + fn _svtbx_s8(fallback: svint8_t, data: svint8_t, indices: svint8_t) -> svint8_t; + } + unsafe { _svtbx_s8(fallback, data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_s16(fallback: svint16_t, data: svint16_t, indices: svuint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv8i16")] + fn _svtbx_s16(fallback: svint16_t, data: svint16_t, indices: svint16_t) -> svint16_t; + } + unsafe { _svtbx_s16(fallback, data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_s32(fallback: svint32_t, data: svint32_t, indices: svuint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv4i32")] + fn _svtbx_s32(fallback: svint32_t, data: svint32_t, indices: svint32_t) -> svint32_t; + } + unsafe { _svtbx_s32(fallback, data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_s64(fallback: svint64_t, data: svint64_t, indices: svuint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv2i64")] + fn _svtbx_s64(fallback: svint64_t, data: svint64_t, indices: svint64_t) -> svint64_t; + } + unsafe { _svtbx_s64(fallback, data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_u8(fallback: svuint8_t, data: svuint8_t, indices: svuint8_t) -> svuint8_t { + unsafe { svtbx_s8(fallback.as_signed(), data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_u16(fallback: svuint16_t, data: svuint16_t, indices: svuint16_t) -> svuint16_t { + unsafe { svtbx_s16(fallback.as_signed(), data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_u32(fallback: svuint32_t, data: svuint32_t, indices: svuint32_t) -> svuint32_t { + unsafe { svtbx_s32(fallback.as_signed(), data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_u64(fallback: svuint64_t, data: svuint64_t, indices: svuint64_t) -> svuint64_t { + unsafe { svtbx_s64(fallback.as_signed(), data.as_signed(), indices).as_unsigned() } +} +#[doc = "Unpack and extend high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_b])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(punpkhi))] +pub fn svunpkhi_b(op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.punpkhi.nxv16i1" + )] + fn _svunpkhi_b(op: svbool_t) -> svbool8_t; + } + unsafe { _svunpkhi_b(op).sve_into() } +} +#[doc = "Unpack and extend high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sunpkhi))] +pub fn svunpkhi_s16(op: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sunpkhi.nxv8i16" + )] + fn _svunpkhi_s16(op: svint8_t) -> svint16_t; + } + unsafe { _svunpkhi_s16(op) } +} +#[doc = "Unpack and extend high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sunpkhi))] +pub fn svunpkhi_s32(op: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sunpkhi.nxv4i32" + )] + fn _svunpkhi_s32(op: svint16_t) -> svint32_t; + } + unsafe { _svunpkhi_s32(op) } +} +#[doc = "Unpack and extend high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sunpkhi))] +pub fn svunpkhi_s64(op: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sunpkhi.nxv2i64" + )] + fn _svunpkhi_s64(op: svint32_t) -> svint64_t; + } + unsafe { _svunpkhi_s64(op) } +} +#[doc = "Unpack and extend high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uunpkhi))] +pub fn svunpkhi_u16(op: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uunpkhi.nxv8i16" + )] + fn _svunpkhi_u16(op: svint8_t) -> svint16_t; + } + unsafe { _svunpkhi_u16(op.as_signed()).as_unsigned() } +} +#[doc = "Unpack and extend high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uunpkhi))] +pub fn svunpkhi_u32(op: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uunpkhi.nxv4i32" + )] + fn _svunpkhi_u32(op: svint16_t) -> svint32_t; + } + unsafe { _svunpkhi_u32(op.as_signed()).as_unsigned() } +} +#[doc = "Unpack and extend high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uunpkhi))] +pub fn svunpkhi_u64(op: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uunpkhi.nxv2i64" + )] + fn _svunpkhi_u64(op: svint32_t) -> svint64_t; + } + unsafe { _svunpkhi_u64(op.as_signed()).as_unsigned() } +} +#[doc = "Unpack and extend low half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_b])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(punpklo))] +pub fn svunpklo_b(op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.punpklo.nxv16i1" + )] + fn _svunpklo_b(op: svbool_t) -> svbool8_t; + } + unsafe { _svunpklo_b(op).sve_into() } +} +#[doc = "Unpack and extend low half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sunpklo))] +pub fn svunpklo_s16(op: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sunpklo.nxv8i16" + )] + fn _svunpklo_s16(op: svint8_t) -> svint16_t; + } + unsafe { _svunpklo_s16(op) } +} +#[doc = "Unpack and extend low half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sunpklo))] +pub fn svunpklo_s32(op: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sunpklo.nxv4i32" + )] + fn _svunpklo_s32(op: svint16_t) -> svint32_t; + } + unsafe { _svunpklo_s32(op) } +} +#[doc = "Unpack and extend low half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sunpklo))] +pub fn svunpklo_s64(op: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sunpklo.nxv2i64" + )] + fn _svunpklo_s64(op: svint32_t) -> svint64_t; + } + unsafe { _svunpklo_s64(op) } +} +#[doc = "Unpack and extend low half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uunpklo))] +pub fn svunpklo_u16(op: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uunpklo.nxv8i16" + )] + fn _svunpklo_u16(op: svint8_t) -> svint16_t; + } + unsafe { _svunpklo_u16(op.as_signed()).as_unsigned() } +} +#[doc = "Unpack and extend low half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uunpklo))] +pub fn svunpklo_u32(op: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uunpklo.nxv4i32" + )] + fn _svunpklo_u32(op: svint16_t) -> svint32_t; + } + unsafe { _svunpklo_u32(op.as_signed()).as_unsigned() } +} +#[doc = "Unpack and extend low half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uunpklo))] +pub fn svunpklo_u64(op: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uunpklo.nxv2i64" + )] + fn _svunpklo_u64(op: svint32_t) -> svint64_t; + } + unsafe { _svunpklo_u64(op.as_signed()).as_unsigned() } +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.suqadd.nxv16i8")] + fn _svuqadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svuqadd_s8_m(pg, op1, op2.as_signed()) } +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svuqadd_s8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + svuqadd_s8_m(pg, op1, op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svuqadd_s8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + svuqadd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svuqadd_s8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.suqadd.nxv8i16")] + fn _svuqadd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svuqadd_s16_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svuqadd_s16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + svuqadd_s16_m(pg, op1, op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svuqadd_s16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + svuqadd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svuqadd_s16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.suqadd.nxv4i32")] + fn _svuqadd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svuqadd_s32_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svuqadd_s32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + svuqadd_s32_m(pg, op1, op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svuqadd_s32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + svuqadd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svuqadd_s32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.suqadd.nxv2i64")] + fn _svuqadd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svuqadd_s64_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svuqadd_s64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + svuqadd_s64_m(pg, op1, op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svuqadd_s64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + svuqadd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svuqadd_s64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b8[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b8_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv16i1.i32" + )] + fn _svwhilege_b8_s32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilege_b8_s32(op1, op2) } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b16[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b16_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv8i1.i32" + )] + fn _svwhilege_b16_s32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilege_b16_s32(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b32[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b32_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv4i1.i32" + )] + fn _svwhilege_b32_s32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilege_b32_s32(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b64[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b64_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv2i1.i32" + )] + fn _svwhilege_b64_s32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilege_b64_s32(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b8[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b8_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv16i1.i64" + )] + fn _svwhilege_b8_s64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilege_b8_s64(op1, op2) } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b16[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b16_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv8i1.i64" + )] + fn _svwhilege_b16_s64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilege_b16_s64(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b32[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b32_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv4i1.i64" + )] + fn _svwhilege_b32_s64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilege_b32_s64(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b64[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b64_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv2i1.i64" + )] + fn _svwhilege_b64_s64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilege_b64_s64(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b8[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b8_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv16i1.i32" + )] + fn _svwhilege_b8_u32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilege_b8_u32(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b16[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b16_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv8i1.i32" + )] + fn _svwhilege_b16_u32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilege_b16_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b32[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b32_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv4i1.i32" + )] + fn _svwhilege_b32_u32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilege_b32_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b64[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b64_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv2i1.i32" + )] + fn _svwhilege_b64_u32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilege_b64_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b8[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b8_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv16i1.i64" + )] + fn _svwhilege_b8_u64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilege_b8_u64(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b16[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b16_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv8i1.i64" + )] + fn _svwhilege_b16_u64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilege_b16_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b32[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b32_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv4i1.i64" + )] + fn _svwhilege_b32_u64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilege_b32_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b64[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b64_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv2i1.i64" + )] + fn _svwhilege_b64_u64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilege_b64_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b8[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b8_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv16i1.i32" + )] + fn _svwhilegt_b8_s32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilegt_b8_s32(op1, op2) } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b16[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b16_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv8i1.i32" + )] + fn _svwhilegt_b16_s32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilegt_b16_s32(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b32[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b32_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv4i1.i32" + )] + fn _svwhilegt_b32_s32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilegt_b32_s32(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b64[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b64_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv2i1.i32" + )] + fn _svwhilegt_b64_s32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilegt_b64_s32(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b8[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b8_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv16i1.i64" + )] + fn _svwhilegt_b8_s64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilegt_b8_s64(op1, op2) } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b16[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b16_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv8i1.i64" + )] + fn _svwhilegt_b16_s64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilegt_b16_s64(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b32[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b32_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv4i1.i64" + )] + fn _svwhilegt_b32_s64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilegt_b32_s64(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b64[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b64_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv2i1.i64" + )] + fn _svwhilegt_b64_s64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilegt_b64_s64(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b8[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b8_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv16i1.i32" + )] + fn _svwhilegt_b8_u32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilegt_b8_u32(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b16[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b16_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv8i1.i32" + )] + fn _svwhilegt_b16_u32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilegt_b16_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b32[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b32_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv4i1.i32" + )] + fn _svwhilegt_b32_u32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilegt_b32_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b64[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b64_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv2i1.i32" + )] + fn _svwhilegt_b64_u32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilegt_b64_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b8[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b8_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv16i1.i64" + )] + fn _svwhilegt_b8_u64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilegt_b8_u64(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b16[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b16_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv8i1.i64" + )] + fn _svwhilegt_b16_u64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilegt_b16_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b32[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b32_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv4i1.i64" + )] + fn _svwhilegt_b32_u64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilegt_b32_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b64[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b64_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv2i1.i64" + )] + fn _svwhilegt_b64_u64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilegt_b64_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilerw_8ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilerw.b.nxv16i1.p0" + )] + fn _svwhilerw_8ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool_t; + } + _svwhilerw_8ptr(op1, op2) +} +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilerw_16ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilerw.h.nxv8i1.p0" + )] + fn _svwhilerw_16ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool8_t; + } + _svwhilerw_16ptr(op1, op2).sve_into() +} +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilerw_32ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilerw.s.nxv4i1.p0" + )] + fn _svwhilerw_32ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool4_t; + } + _svwhilerw_32ptr(op1, op2).sve_into() +} +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilerw_64ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilerw.d.nxv2i1.p0" + )] + fn _svwhilerw_64ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool2_t; + } + _svwhilerw_64ptr(op1, op2).sve_into() +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_f32(op1: *const f32, op2: *const f32) -> svbool_t { + svwhilerw_32ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_f64(op1: *const f64, op2: *const f64) -> svbool_t { + svwhilerw_64ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_s8(op1: *const i8, op2: *const i8) -> svbool_t { + svwhilerw_8ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_s16(op1: *const i16, op2: *const i16) -> svbool_t { + svwhilerw_16ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_s32(op1: *const i32, op2: *const i32) -> svbool_t { + svwhilerw_32ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_s64(op1: *const i64, op2: *const i64) -> svbool_t { + svwhilerw_64ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_u8(op1: *const u8, op2: *const u8) -> svbool_t { + svwhilerw_8ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_u16(op1: *const u16, op2: *const u16) -> svbool_t { + svwhilerw_16ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_u32(op1: *const u32, op2: *const u32) -> svbool_t { + svwhilerw_32ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_u64(op1: *const u64, op2: *const u64) -> svbool_t { + svwhilerw_64ptr::(op1, op2) +} +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilewr_8ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilewr.b.nxv16i1.p0" + )] + fn _svwhilewr_8ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool_t; + } + _svwhilewr_8ptr(op1, op2) +} +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilewr_16ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilewr.h.nxv8i1.p0" + )] + fn _svwhilewr_16ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool8_t; + } + _svwhilewr_16ptr(op1, op2).sve_into() +} +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilewr_32ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilewr.s.nxv4i1.p0" + )] + fn _svwhilewr_32ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool4_t; + } + _svwhilewr_32ptr(op1, op2).sve_into() +} +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilewr_64ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilewr.d.nxv2i1.p0" + )] + fn _svwhilewr_64ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool2_t; + } + _svwhilewr_64ptr(op1, op2).sve_into() +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_f32(op1: *const f32, op2: *const f32) -> svbool_t { + svwhilewr_32ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_f64(op1: *const f64, op2: *const f64) -> svbool_t { + svwhilewr_64ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_s8(op1: *const i8, op2: *const i8) -> svbool_t { + svwhilewr_8ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_s16(op1: *const i16, op2: *const i16) -> svbool_t { + svwhilewr_16ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_s32(op1: *const i32, op2: *const i32) -> svbool_t { + svwhilewr_32ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_s64(op1: *const i64, op2: *const i64) -> svbool_t { + svwhilewr_64ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_u8(op1: *const u8, op2: *const u8) -> svbool_t { + svwhilewr_8ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_u16(op1: *const u16, op2: *const u16) -> svbool_t { + svwhilewr_16ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_u32(op1: *const u32, op2: *const u32) -> svbool_t { + svwhilewr_32ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_u64(op1: *const u64, op2: *const u64) -> svbool_t { + svwhilewr_64ptr::(op1, op2) +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.xar.nxv16i8")] + fn _svxar_n_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svxar_n_s8(op1, op2, IMM3) } +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.xar.nxv8i16")] + fn _svxar_n_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svxar_n_s16(op1, op2, IMM3) } +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.xar.nxv4i32")] + fn _svxar_n_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svxar_n_s32(op1, op2, IMM3) } +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.xar.nxv2i64")] + fn _svxar_n_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svxar_n_s64(op1, op2, IMM3) } +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe { svxar_n_s8::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe { svxar_n_s16::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe { svxar_n_s32::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe { svxar_n_s64::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} diff --git a/library/stdarch/crates/core_arch/src/aarch64/sve2/ld_st_tests_aarch64.rs b/library/stdarch/crates/core_arch/src/aarch64/sve2/ld_st_tests_aarch64.rs new file mode 100644 index 0000000000000..e71fd12dec374 --- /dev/null +++ b/library/stdarch/crates/core_arch/src/aarch64/sve2/ld_st_tests_aarch64.rs @@ -0,0 +1,2716 @@ +// This code is automatically generated. DO NOT MODIFY. +// +// Instead, modify `crates/stdarch-gen-arm/spec/sve` and run the following command to re-generate +// this file: +// +// ``` +// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec +// ``` +#![allow(unused)] +use super::*; +use std::boxed::Box; +use std::convert::{TryFrom, TryInto}; +use std::sync::LazyLock; +use std::vec::Vec; +use stdarch_test::simd_test; +static F32_DATA: LazyLock<[f32; 64 * 5]> = LazyLock::new(|| { + (0..64 * 5) + .map(|i| i as f32) + .collect::>() + .try_into() + .expect("f32 data incorrectly initialised") +}); +static F64_DATA: LazyLock<[f64; 32 * 5]> = LazyLock::new(|| { + (0..32 * 5) + .map(|i| i as f64) + .collect::>() + .try_into() + .expect("f64 data incorrectly initialised") +}); +static I8_DATA: LazyLock<[i8; 256 * 5]> = LazyLock::new(|| { + (0..256 * 5) + .map(|i| ((i + 128) % 256 - 128) as i8) + .collect::>() + .try_into() + .expect("i8 data incorrectly initialised") +}); +static I16_DATA: LazyLock<[i16; 128 * 5]> = LazyLock::new(|| { + (0..128 * 5) + .map(|i| i as i16) + .collect::>() + .try_into() + .expect("i16 data incorrectly initialised") +}); +static I32_DATA: LazyLock<[i32; 64 * 5]> = LazyLock::new(|| { + (0..64 * 5) + .map(|i| i as i32) + .collect::>() + .try_into() + .expect("i32 data incorrectly initialised") +}); +static I64_DATA: LazyLock<[i64; 32 * 5]> = LazyLock::new(|| { + (0..32 * 5) + .map(|i| i as i64) + .collect::>() + .try_into() + .expect("i64 data incorrectly initialised") +}); +static U8_DATA: LazyLock<[u8; 256 * 5]> = LazyLock::new(|| { + (0..256 * 5) + .map(|i| i as u8) + .collect::>() + .try_into() + .expect("u8 data incorrectly initialised") +}); +static U16_DATA: LazyLock<[u16; 128 * 5]> = LazyLock::new(|| { + (0..128 * 5) + .map(|i| i as u16) + .collect::>() + .try_into() + .expect("u16 data incorrectly initialised") +}); +static U32_DATA: LazyLock<[u32; 64 * 5]> = LazyLock::new(|| { + (0..64 * 5) + .map(|i| i as u32) + .collect::>() + .try_into() + .expect("u32 data incorrectly initialised") +}); +static U64_DATA: LazyLock<[u64; 32 * 5]> = LazyLock::new(|| { + (0..32 * 5) + .map(|i| i as u64) + .collect::>() + .try_into() + .expect("u64 data incorrectly initialised") +}); +#[target_feature(enable = "sve")] +fn assert_vector_matches_f32(vector: svfloat32_t, expected: svfloat32_t, defined: svbool_t) { + assert!(svptest_first(svptrue_b32(), defined)); + let cmp = svcmpne_f32(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_f64(vector: svfloat64_t, expected: svfloat64_t, defined: svbool_t) { + assert!(svptest_first(svptrue_b64(), defined)); + let cmp = svcmpne_f64(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i8(vector: svint8_t, expected: svint8_t, defined: svbool_t) { + assert!(svptest_first(svptrue_b8(), defined)); + let cmp = svcmpne_s8(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i16(vector: svint16_t, expected: svint16_t, defined: svbool_t) { + assert!(svptest_first(svptrue_b16(), defined)); + let cmp = svcmpne_s16(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i32(vector: svint32_t, expected: svint32_t, defined: svbool_t) { + assert!(svptest_first(svptrue_b32(), defined)); + let cmp = svcmpne_s32(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i64(vector: svint64_t, expected: svint64_t, defined: svbool_t) { + assert!(svptest_first(svptrue_b64(), defined)); + let cmp = svcmpne_s64(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u8(vector: svuint8_t, expected: svuint8_t, defined: svbool_t) { + assert!(svptest_first(svptrue_b8(), defined)); + let cmp = svcmpne_u8(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u16(vector: svuint16_t, expected: svuint16_t, defined: svbool_t) { + assert!(svptest_first(svptrue_b16(), defined)); + let cmp = svcmpne_u16(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u32(vector: svuint32_t, expected: svuint32_t, defined: svbool_t) { + assert!(svptest_first(svptrue_b32(), defined)); + let cmp = svcmpne_u32(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u64(vector: svuint64_t, expected: svuint64_t, defined: svbool_t) { + assert!(svptest_first(svptrue_b64(), defined)); + let cmp = svcmpne_u64(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_s64index_f64_with_svstnt1_scatter_s64index_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let indices = svindex_s64(0, 1); + svstnt1_scatter_s64index_f64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = + svldnt1_gather_s64index_f64(svptrue_b64(), storage.as_ptr() as *const f64, indices); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_s64index_s64_with_svstnt1_scatter_s64index_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1_scatter_s64index_s64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = + svldnt1_gather_s64index_s64(svptrue_b64(), storage.as_ptr() as *const i64, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_s64index_u64_with_svstnt1_scatter_s64index_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1_scatter_s64index_u64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = + svldnt1_gather_s64index_u64(svptrue_b64(), storage.as_ptr() as *const u64, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64index_f64_with_svstnt1_scatter_u64index_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let indices = svindex_u64(0, 1); + svstnt1_scatter_u64index_f64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = + svldnt1_gather_u64index_f64(svptrue_b64(), storage.as_ptr() as *const f64, indices); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64index_s64_with_svstnt1_scatter_u64index_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1_scatter_u64index_s64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = + svldnt1_gather_u64index_s64(svptrue_b64(), storage.as_ptr() as *const i64, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64index_u64_with_svstnt1_scatter_u64index_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1_scatter_u64index_u64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = + svldnt1_gather_u64index_u64(svptrue_b64(), storage.as_ptr() as *const u64, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_s64offset_f64_with_svstnt1_scatter_s64offset_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + svstnt1_scatter_s64offset_f64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = + svldnt1_gather_s64offset_f64(svptrue_b64(), storage.as_ptr() as *const f64, offsets); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_s64offset_s64_with_svstnt1_scatter_s64offset_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + svstnt1_scatter_s64offset_s64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = + svldnt1_gather_s64offset_s64(svptrue_b64(), storage.as_ptr() as *const i64, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_s64offset_u64_with_svstnt1_scatter_s64offset_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + svstnt1_scatter_s64offset_u64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = + svldnt1_gather_s64offset_u64(svptrue_b64(), storage.as_ptr() as *const u64, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32offset_f32_with_svstnt1_scatter_u32offset_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32offset_f32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = + svldnt1_gather_u32offset_f32(svptrue_b32(), storage.as_ptr() as *const f32, offsets); + let defined = svrdffr(); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32offset_s32_with_svstnt1_scatter_u32offset_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32offset_s32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1_gather_u32offset_s32(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32offset_u32_with_svstnt1_scatter_u32offset_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32offset_u32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1_gather_u32offset_u32(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64offset_f64_with_svstnt1_scatter_u64offset_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + svstnt1_scatter_u64offset_f64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = + svldnt1_gather_u64offset_f64(svptrue_b64(), storage.as_ptr() as *const f64, offsets); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64offset_s64_with_svstnt1_scatter_u64offset_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + svstnt1_scatter_u64offset_s64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = + svldnt1_gather_u64offset_s64(svptrue_b64(), storage.as_ptr() as *const i64, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64offset_u64_with_svstnt1_scatter_u64offset_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + svstnt1_scatter_u64offset_u64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = + svldnt1_gather_u64offset_u64(svptrue_b64(), storage.as_ptr() as *const u64, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_f64_with_svstnt1_scatter_u64base_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_f64(svptrue_b64(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_f64(svptrue_b64(), bases); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_s64_with_svstnt1_scatter_u64base_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_s64(svptrue_b64(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_s64(svptrue_b64(), bases); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_u64_with_svstnt1_scatter_u64base_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_u64(svptrue_b64(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_u64(svptrue_b64(), bases); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32base_index_f32_with_svstnt1_scatter_u32base_index_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32base_index_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svldnt1_gather_u32base_index_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + ); + let defined = svrdffr(); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32base_index_s32_with_svstnt1_scatter_u32base_index_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32base_index_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1_gather_u32base_index_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32base_index_u32_with_svstnt1_scatter_u32base_index_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32base_index_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svldnt1_gather_u32base_index_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_index_f64_with_svstnt1_scatter_u64base_index_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_index_f64(svptrue_b64(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_index_f64(svptrue_b64(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_index_s64_with_svstnt1_scatter_u64base_index_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_index_s64(svptrue_b64(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_index_s64(svptrue_b64(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_index_u64_with_svstnt1_scatter_u64base_index_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_index_u64(svptrue_b64(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_index_u64(svptrue_b64(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32base_offset_f32_with_svstnt1_scatter_u32base_offset_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32base_offset_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svldnt1_gather_u32base_offset_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32base_offset_s32_with_svstnt1_scatter_u32base_offset_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32base_offset_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1_gather_u32base_offset_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32base_offset_u32_with_svstnt1_scatter_u32base_offset_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32base_offset_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svldnt1_gather_u32base_offset_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_offset_f64_with_svstnt1_scatter_u64base_offset_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_offset_f64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_offset_f64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_offset_s64_with_svstnt1_scatter_u64base_offset_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_offset_s64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_offset_s64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_offset_u64_with_svstnt1_scatter_u64base_offset_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_offset_u64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_offset_u64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_s64offset_s64_with_svstnt1b_scatter_s64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_s64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = + svldnt1sb_gather_s64offset_s64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_s64offset_s64_with_svstnt1h_scatter_s64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_s64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_s64offset_s64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_s64offset_s64_with_svstnt1w_scatter_s64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_s64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_s64offset_s64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_s64offset_u64_with_svstnt1b_scatter_s64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_s64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = + svldnt1sb_gather_s64offset_u64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_s64offset_u64_with_svstnt1h_scatter_s64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_s64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_s64offset_u64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_s64offset_u64_with_svstnt1w_scatter_s64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_s64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_s64offset_u64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u32offset_s32_with_svstnt1b_scatter_u32offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = + svldnt1sb_gather_u32offset_s32(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u32offset_s32_with_svstnt1h_scatter_u32offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u32offset_s32(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u32offset_u32_with_svstnt1b_scatter_u32offset_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = + svldnt1sb_gather_u32offset_u32(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u32offset_u32_with_svstnt1h_scatter_u32offset_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u32offset_u32(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u64offset_s64_with_svstnt1b_scatter_u64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = + svldnt1sb_gather_u64offset_s64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64offset_s64_with_svstnt1h_scatter_u64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u64offset_s64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64offset_s64_with_svstnt1w_scatter_u64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_u64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_u64offset_s64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u64offset_u64_with_svstnt1b_scatter_u64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = + svldnt1sb_gather_u64offset_u64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64offset_u64_with_svstnt1h_scatter_u64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u64offset_u64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64offset_u64_with_svstnt1w_scatter_u64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_u64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_u64offset_u64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u32base_offset_s32_with_svstnt1b_scatter_u32base_offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1sb_gather_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u32base_offset_s32_with_svstnt1h_scatter_u32base_offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u32base_offset_u32_with_svstnt1b_scatter_u32base_offset_u32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1sb_gather_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u32base_offset_u32_with_svstnt1h_scatter_u32base_offset_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u64base_offset_s64_with_svstnt1b_scatter_u64base_offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1sb_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64base_offset_s64_with_svstnt1h_scatter_u64base_offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64base_offset_s64_with_svstnt1w_scatter_u64base_offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u64base_offset_u64_with_svstnt1b_scatter_u64base_offset_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1sb_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64base_offset_u64_with_svstnt1h_scatter_u64base_offset_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64base_offset_u64_with_svstnt1w_scatter_u64base_offset_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u64base_s64_with_svstnt1b_scatter_u64base_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_s64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1sb_gather_u64base_s64(svptrue_b8(), bases); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64base_s64_with_svstnt1h_scatter_u64base_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_s64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u64base_s64(svptrue_b16(), bases); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64base_s64_with_svstnt1w_scatter_u64base_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_s64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1sw_gather_u64base_s64(svptrue_b32(), bases); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u64base_u64_with_svstnt1b_scatter_u64base_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_u64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1sb_gather_u64base_u64(svptrue_b8(), bases); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64base_u64_with_svstnt1h_scatter_u64base_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_u64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u64base_u64(svptrue_b16(), bases); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64base_u64_with_svstnt1w_scatter_u64base_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_u64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1sw_gather_u64base_u64(svptrue_b32(), bases); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_s64index_s64_with_svstnt1h_scatter_s64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1h_scatter_s64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_s64index_s64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_s64index_s64_with_svstnt1w_scatter_s64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1w_scatter_s64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_s64index_s64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_s64index_u64_with_svstnt1h_scatter_s64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1h_scatter_s64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_s64index_u64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_s64index_u64_with_svstnt1w_scatter_s64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1w_scatter_s64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_s64index_u64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64index_s64_with_svstnt1h_scatter_u64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1h_scatter_u64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u64index_s64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64index_s64_with_svstnt1w_scatter_u64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1w_scatter_u64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_u64index_s64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64index_u64_with_svstnt1h_scatter_u64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1h_scatter_u64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u64index_u64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64index_u64_with_svstnt1w_scatter_u64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1w_scatter_u64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_u64index_u64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u32base_index_s32_with_svstnt1h_scatter_u32base_index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u32base_index_u32_with_svstnt1h_scatter_u32base_index_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64base_index_s64_with_svstnt1h_scatter_u64base_index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64base_index_s64_with_svstnt1w_scatter_u64base_index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1sw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64base_index_u64_with_svstnt1h_scatter_u64base_index_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64base_index_u64_with_svstnt1w_scatter_u64base_index_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1sw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_s64offset_s64_with_svstnt1b_scatter_s64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_s64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = + svldnt1ub_gather_s64offset_s64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_s64offset_s64_with_svstnt1h_scatter_s64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_s64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_s64offset_s64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_s64offset_s64_with_svstnt1w_scatter_s64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_s64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_s64offset_s64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_s64offset_u64_with_svstnt1b_scatter_s64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_s64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = + svldnt1ub_gather_s64offset_u64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_s64offset_u64_with_svstnt1h_scatter_s64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_s64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_s64offset_u64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_s64offset_u64_with_svstnt1w_scatter_s64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_s64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_s64offset_u64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u32offset_s32_with_svstnt1b_scatter_u32offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = + svldnt1ub_gather_u32offset_s32(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u32offset_s32_with_svstnt1h_scatter_u32offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u32offset_s32(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u32offset_u32_with_svstnt1b_scatter_u32offset_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = + svldnt1ub_gather_u32offset_u32(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u32offset_u32_with_svstnt1h_scatter_u32offset_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u32offset_u32(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u64offset_s64_with_svstnt1b_scatter_u64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = + svldnt1ub_gather_u64offset_s64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64offset_s64_with_svstnt1h_scatter_u64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u64offset_s64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64offset_s64_with_svstnt1w_scatter_u64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_u64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_u64offset_s64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u64offset_u64_with_svstnt1b_scatter_u64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = + svldnt1ub_gather_u64offset_u64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64offset_u64_with_svstnt1h_scatter_u64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u64offset_u64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64offset_u64_with_svstnt1w_scatter_u64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_u64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_u64offset_u64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u32base_offset_s32_with_svstnt1b_scatter_u32base_offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1ub_gather_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u32base_offset_s32_with_svstnt1h_scatter_u32base_offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u32base_offset_u32_with_svstnt1b_scatter_u32base_offset_u32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1ub_gather_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u32base_offset_u32_with_svstnt1h_scatter_u32base_offset_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u64base_offset_s64_with_svstnt1b_scatter_u64base_offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1ub_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64base_offset_s64_with_svstnt1h_scatter_u64base_offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64base_offset_s64_with_svstnt1w_scatter_u64base_offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u64base_offset_u64_with_svstnt1b_scatter_u64base_offset_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1ub_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64base_offset_u64_with_svstnt1h_scatter_u64base_offset_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64base_offset_u64_with_svstnt1w_scatter_u64base_offset_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u64base_s64_with_svstnt1b_scatter_u64base_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_s64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1ub_gather_u64base_s64(svptrue_b8(), bases); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64base_s64_with_svstnt1h_scatter_u64base_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_s64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u64base_s64(svptrue_b16(), bases); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64base_s64_with_svstnt1w_scatter_u64base_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_s64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1uw_gather_u64base_s64(svptrue_b32(), bases); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u64base_u64_with_svstnt1b_scatter_u64base_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_u64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1ub_gather_u64base_u64(svptrue_b8(), bases); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64base_u64_with_svstnt1h_scatter_u64base_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_u64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u64base_u64(svptrue_b16(), bases); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64base_u64_with_svstnt1w_scatter_u64base_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_u64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1uw_gather_u64base_u64(svptrue_b32(), bases); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_s64index_s64_with_svstnt1h_scatter_s64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1h_scatter_s64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_s64index_s64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_s64index_s64_with_svstnt1w_scatter_s64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1w_scatter_s64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_s64index_s64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_s64index_u64_with_svstnt1h_scatter_s64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1h_scatter_s64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_s64index_u64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_s64index_u64_with_svstnt1w_scatter_s64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1w_scatter_s64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_s64index_u64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64index_s64_with_svstnt1h_scatter_u64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1h_scatter_u64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u64index_s64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64index_s64_with_svstnt1w_scatter_u64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1w_scatter_u64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_u64index_s64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64index_u64_with_svstnt1h_scatter_u64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1h_scatter_u64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u64index_u64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64index_u64_with_svstnt1w_scatter_u64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1w_scatter_u64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_u64index_u64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u32base_index_s32_with_svstnt1h_scatter_u32base_index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + let defined = svrdffr(); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u32base_index_u32_with_svstnt1h_scatter_u32base_index_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + let defined = svrdffr(); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64base_index_s64_with_svstnt1h_scatter_u64base_index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64base_index_s64_with_svstnt1w_scatter_u64base_index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1uw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64base_index_u64_with_svstnt1h_scatter_u64base_index_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64base_index_u64_with_svstnt1w_scatter_u64base_index_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1uw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap()); + let defined = svrdffr(); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + defined, + ); +} diff --git a/library/stdarch/crates/core_arch/src/aarch64/sve2/mod.rs b/library/stdarch/crates/core_arch/src/aarch64/sve2/mod.rs new file mode 100644 index 0000000000000..acf9070214571 --- /dev/null +++ b/library/stdarch/crates/core_arch/src/aarch64/sve2/mod.rs @@ -0,0 +1,17 @@ +//! SVE2 intrinsics + +#![allow(non_camel_case_types)] + +// `generated.rs` has a `super::*` and this import is for that +use super::sve::*; +use crate::intrinsics::*; + +#[rustfmt::skip] +mod generated; +#[rustfmt::skip] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub use self::generated::*; + +#[cfg(test)] +#[path = "ld_st_tests_aarch64.rs"] +mod ld_st_tests; diff --git a/library/stdarch/crates/core_arch/src/amdgpu/intrinsic_is_convergent.md b/library/stdarch/crates/core_arch/src/amdgpu/intrinsic_is_convergent.md new file mode 100644 index 0000000000000..1bc8899d33e0a --- /dev/null +++ b/library/stdarch/crates/core_arch/src/amdgpu/intrinsic_is_convergent.md @@ -0,0 +1,6 @@ +This intrinsic does not behave like a normal function call; it is a "[convergent]" operation and as such has non-standard control-flow effects which need special treatment by the language. +Rust currently does not properly support convergent operations. +This operation is hence provided on a best-effort basis. +Using it may result in incorrect code under some circumstances. + +[convergent]: https://llvm.org/docs/ConvergentOperations.html diff --git a/library/stdarch/crates/core_arch/src/amdgpu/mod.rs b/library/stdarch/crates/core_arch/src/amdgpu/mod.rs index 40274e4d794fd..00182f154c5ca 100644 --- a/library/stdarch/crates/core_arch/src/amdgpu/mod.rs +++ b/library/stdarch/crates/core_arch/src/amdgpu/mod.rs @@ -244,6 +244,8 @@ pub fn wavefrontsize() -> u32 { /// Synchronize all wavefronts in a workgroup. /// /// Each wavefronts in a workgroup waits at the barrier until all wavefronts in the workgroup arrive at a barrier. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn s_barrier() { @@ -253,6 +255,8 @@ pub fn s_barrier() { /// Signal a specific barrier type. /// /// Only for non-named barriers. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn s_barrier_signal() { @@ -265,6 +269,8 @@ pub unsafe fn s_barrier_signal() { /// Provides access to the s_barrier_signal_first instruction; /// additionally ensures that the result value is valid even when /// the intrinsic is used from a wavefront that is not running in a workgroup. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn s_barrier_signal_isfirst() -> bool { @@ -274,6 +280,8 @@ pub unsafe fn s_barrier_signal_isfirst() -> bool { /// Wait for a specific barrier type. /// /// Only for non-named barriers. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn s_barrier_wait() { @@ -283,6 +291,8 @@ pub unsafe fn s_barrier_wait() { /// Get the state of a specific barrier type. /// /// The `barrier_type` argument must be uniform, otherwise behavior is undefined. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn s_get_barrier_state() -> u32 { @@ -292,6 +302,8 @@ pub unsafe fn s_get_barrier_state() -> u32 { /// A barrier for only the threads within the current wavefront. /// /// Does not result in an instruction but restricts the compiler. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn wave_barrier() { @@ -315,6 +327,8 @@ pub fn wave_barrier() { /// - 0x0100: All DS read instructions may be scheduled across `sched_barrier`. /// - 0x0200: All DS write instructions may be scheduled across `sched_barrier`. /// - 0x0400: All Transcendental (e.g. V_EXP) instructions may be scheduled across `sched_barrier`. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn sched_barrier() { @@ -337,14 +351,17 @@ pub unsafe fn sched_barrier() { /// Combining multiple `sched_group_barrier` intrinsics enables an ordering of specific instruction types during instruction scheduling. /// For example, the following enforces a sequence of 1 VMEM read, followed by 1 VALU instruction, followed by 5 MFMA instructions. /// -/// ```rust +/// ```ignore (only available on AMD) /// // 1 VMEM read -/// sched_group_barrier::<32, 1, 0>() +/// sched_group_barrier::<32, 1, 0>(); /// // 1 VALU -/// sched_group_barrier::<2, 1, 0>() +/// sched_group_barrier::<2, 1, 0>(); /// // 5 MFMA -/// sched_group_barrier::<8, 5, 0>() +/// sched_group_barrier::<8, 5, 0>(); /// ``` +/// +#[doc(cfg(target_arch = "amdgpu"))] +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn sched_group_barrier() { @@ -366,6 +383,8 @@ pub fn s_sleep() { /// Stop execution of the kernel. /// /// This usually signals an error state. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn s_sethalt() -> ! { @@ -407,6 +426,8 @@ pub fn mbcnt_hi(value: u32, init: u32) -> u32 { /// Returns a bitfield (`u32` or `u64`) containing the result of its i1 argument /// in all active lanes, and zero in all inactive lanes. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn ballot(b: bool) -> u64 { @@ -419,6 +440,8 @@ pub fn ballot(b: bool) -> u64 { /// While [`ballot`] converts a `bool` to a mask, `inverse_ballot` converts a mask back to a `bool`. /// This means `inverse_ballot(ballot(b)) == b`. /// The inverse of `ballot(inverse_ballot(value)) ~= value` is not always true as inactive lanes are set to zero by `ballot`. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn inverse_ballot(value: u64) -> bool { @@ -433,6 +456,8 @@ pub fn inverse_ballot(value: u64) -> bool { /// - 2: DPP /// /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn wave_reduce_umin(value: u32) -> u32 { @@ -447,6 +472,8 @@ pub fn wave_reduce_umin(value: u32) -> u32 { /// - 2: DPP /// /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn wave_reduce_min(value: i32) -> i32 { @@ -462,6 +489,8 @@ pub fn wave_reduce_min(value: i32) -> i32 { /// - 2: DPP /// /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn wave_reduce_umax(value: u32) -> u32 { @@ -476,6 +505,8 @@ pub fn wave_reduce_umax(value: u32) -> u32 { /// - 2: DPP /// /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn wave_reduce_max(value: i32) -> i32 { @@ -491,6 +522,8 @@ pub fn wave_reduce_max(value: i32) -> i32 { /// - 2: DPP /// /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn wave_reduce_add(value: u32) -> u32 { @@ -506,6 +539,8 @@ pub fn wave_reduce_add(value: u32) -> u32 { /// - 2: DPP /// /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn wave_reduce_and(value: u32) -> u32 { @@ -520,6 +555,8 @@ pub fn wave_reduce_and(value: u32) -> u32 { /// - 2: DPP /// /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn wave_reduce_or(value: u32) -> u32 { @@ -534,6 +571,8 @@ pub fn wave_reduce_or(value: u32) -> u32 { /// - 2: DPP /// /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn wave_reduce_xor(value: u32) -> u32 { @@ -544,12 +583,16 @@ pub fn wave_reduce_xor(value: u32) -> u32 { // The following intrinsics can have multiple sizes /// Get `value` from the first active lane in the wavefront. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn readfirstlane_u32(value: u32) -> u32 { llvm_readfirstlane_u32(value) } /// Get `value` from the first active lane in the wavefront. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn readfirstlane_u64(value: u64) -> u64 { @@ -559,6 +602,8 @@ pub fn readfirstlane_u64(value: u64) -> u64 { /// /// The lane argument must be uniform across the currently active threads /// of the current wavefront. Otherwise, the result is undefined. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn readlane_u32(value: u32, lane: u32) -> u32 { @@ -568,6 +613,8 @@ pub unsafe fn readlane_u32(value: u32, lane: u32) -> u32 { /// /// The lane argument must be uniform across the currently active threads /// of the current wavefront. Otherwise, the result is undefined. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn readlane_u64(value: u64, lane: u32) -> u64 { @@ -582,6 +629,8 @@ pub unsafe fn readlane_u64(value: u64, lane: u32) -> u64 { /// /// `value` is the value returned by `lane`. /// `default` is the value returned by all lanes other than `lane`. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn writelane_u32(value: u32, lane: u32, default: u32) -> u32 { @@ -596,6 +645,8 @@ pub unsafe fn writelane_u32(value: u32, lane: u32, default: u32) -> u32 { /// /// `value` is the value returned by `lane`. /// `default` is the value returned by all lanes other than `lane`. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn writelane_u64(value: u64, lane: u32, default: u64) -> u64 { @@ -605,6 +656,8 @@ pub unsafe fn writelane_u64(value: u64, lane: u32, default: u64) -> u64 { /// Stop execution of the wavefront. /// /// This usually signals the end of a successful execution. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn endpgm() -> ! { @@ -621,6 +674,8 @@ pub fn endpgm() -> ! { /// v_mov_b32 /// v_mov_b32 /// ``` +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn update_dpp< @@ -651,6 +706,8 @@ pub fn s_memrealtime() -> u64 { /// /// Reading from inactive lanes returns `0`. /// In case multiple values get written to the same `lane`, the value from the source lane with the higher index is taken. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn ds_permute(lane: u32, value: u32) -> u32 { @@ -661,6 +718,8 @@ pub unsafe fn ds_permute(lane: u32, value: u32) -> u32 { /// Returns the `value` given to `ds_permute` by lane `lane`. /// /// Reading from inactive lanes returns `0`. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn ds_bpermute(lane: u32, value: u32) -> u32 { @@ -680,6 +739,8 @@ pub unsafe fn perm(src0: u32, src1: u32, selector: u32) -> u32 { /// /// The third and fourth inputs must be uniform across the current wavefront. /// These are combined into a single 64-bit value representing lane selects used to swizzle within each row. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn permlane16_u32( @@ -696,6 +757,8 @@ pub unsafe fn permlane16_u32( /// /// The third and fourth inputs must be uniform across the current wavefront. /// These are combined into a single 64-bit value representing lane selects used to swizzle within each row. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn permlanex16_u32( @@ -718,6 +781,8 @@ pub fn s_get_waveid_in_workgroup() -> u32 { /// Swap `value` between upper and lower 32 lanes in a wavefront. /// /// Does nothing for wave32. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn permlane64_u32(value: u32) -> u32 { @@ -728,6 +793,8 @@ pub unsafe fn permlane64_u32(value: u32) -> u32 { /// Performs arbitrary gather-style operation within a row (16 contiguous lanes) of the second input operand. /// /// In contrast to [`permlane16_u32`], allows each lane to specify its own gather lane. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn permlane16_var( @@ -742,6 +809,8 @@ pub unsafe fn permlane16_var( /// Performs arbitrary gather-style operation across two rows (16 contiguous lanes) of the second input operand. /// /// In contrast to [`permlanex16_u32`], allows each lane to specify its own gather lane. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn permlanex16_var( @@ -766,6 +835,8 @@ pub fn wave_id() -> u32 { /// Odd rows of the first operand are swapped with even rows of the second operand (one row is 16 lanes). /// Returns a pair for the swapped registers. /// The first element of the return corresponds to the swapped element of the first argument. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn permlane16_swap( @@ -782,6 +853,8 @@ pub unsafe fn permlane16_swap( /// Rows 2 and 3 of the first operand are swapped with rows 0 and 1 of the second operand (one row is 16 lanes). /// Returns a pair for the swapped registers. /// The first element of the return corresponds to the swapped element of the first argument. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn permlane32_swap( diff --git a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs index 3b67208182cb0..3a47ede1acc88 100644 --- a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs +++ b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs @@ -14,7 +14,7 @@ use super::*; #[doc = "CRC32 single round checksum for bytes (8 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32b)"] -#[inline(always)] +#[inline] #[target_feature(enable = "crc")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(crc32b))] @@ -39,7 +39,7 @@ pub fn __crc32b(crc: u32, data: u8) -> u32 { } #[doc = "CRC32-C single round checksum for bytes (8 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cb)"] -#[inline(always)] +#[inline] #[target_feature(enable = "crc")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(crc32cb))] @@ -64,7 +64,7 @@ pub fn __crc32cb(crc: u32, data: u8) -> u32 { } #[doc = "CRC32-C single round checksum for quad words (64 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)"] -#[inline(always)] +#[inline] #[target_feature(enable = "crc")] #[cfg(target_arch = "arm")] #[cfg_attr(test, assert_instr(crc32cw))] @@ -83,7 +83,7 @@ pub fn __crc32cd(crc: u32, data: u64) -> u32 { } #[doc = "CRC32-C single round checksum for bytes (16 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32ch)"] -#[inline(always)] +#[inline] #[target_feature(enable = "crc")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(crc32ch))] @@ -108,7 +108,7 @@ pub fn __crc32ch(crc: u32, data: u16) -> u32 { } #[doc = "CRC32-C single round checksum for bytes (32 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cw)"] -#[inline(always)] +#[inline] #[target_feature(enable = "crc")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(crc32cw))] @@ -133,7 +133,7 @@ pub fn __crc32cw(crc: u32, data: u32) -> u32 { } #[doc = "CRC32 single round checksum for quad words (64 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)"] -#[inline(always)] +#[inline] #[target_feature(enable = "crc")] #[cfg(target_arch = "arm")] #[cfg_attr(test, assert_instr(crc32w))] @@ -152,7 +152,7 @@ pub fn __crc32d(crc: u32, data: u64) -> u32 { } #[doc = "CRC32 single round checksum for bytes (16 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32h)"] -#[inline(always)] +#[inline] #[target_feature(enable = "crc")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(crc32h))] @@ -177,7 +177,7 @@ pub fn __crc32h(crc: u32, data: u16) -> u32 { } #[doc = "CRC32 single round checksum for bytes (32 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32w)"] -#[inline(always)] +#[inline] #[target_feature(enable = "crc")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(crc32w))] @@ -202,7 +202,7 @@ pub fn __crc32w(crc: u32, data: u32) -> u32 { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -220,7 +220,7 @@ fn priv_vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -238,7 +238,7 @@ fn priv_vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -256,7 +256,7 @@ fn priv_vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -274,7 +274,7 @@ fn priv_vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -292,7 +292,7 @@ fn priv_vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -310,7 +310,7 @@ fn priv_vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -328,7 +328,7 @@ fn priv_vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -346,7 +346,7 @@ fn priv_vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -364,7 +364,7 @@ fn priv_vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -382,7 +382,7 @@ fn priv_vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -400,7 +400,7 @@ fn priv_vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -418,7 +418,7 @@ fn priv_vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { } #[doc = "Absolute difference and accumulate (64-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s16"))] @@ -439,7 +439,7 @@ pub fn vaba_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { } #[doc = "Absolute difference and accumulate (64-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s32"))] @@ -460,7 +460,7 @@ pub fn vaba_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { } #[doc = "Absolute difference and accumulate (64-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s8"))] @@ -481,7 +481,7 @@ pub fn vaba_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { } #[doc = "Absolute difference and accumulate (64-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u16"))] @@ -502,7 +502,7 @@ pub fn vaba_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { } #[doc = "Absolute difference and accumulate (64-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u32"))] @@ -523,7 +523,7 @@ pub fn vaba_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { } #[doc = "Absolute difference and accumulate (64-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u8"))] @@ -544,7 +544,7 @@ pub fn vaba_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { } #[doc = "Signed Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s8"))] @@ -569,7 +569,7 @@ pub fn vabal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { } #[doc = "Signed Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s16"))] @@ -594,7 +594,7 @@ pub fn vabal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { } #[doc = "Signed Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s32"))] @@ -619,7 +619,7 @@ pub fn vabal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { } #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u8"))] @@ -641,7 +641,7 @@ pub fn vabal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t { } #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u16"))] @@ -663,7 +663,7 @@ pub fn vabal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { } #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u32"))] @@ -685,7 +685,7 @@ pub fn vabal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { } #[doc = "Absolute difference and accumulate (128-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s16"))] @@ -706,7 +706,7 @@ pub fn vabaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { } #[doc = "Absolute difference and accumulate (128-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s32"))] @@ -727,7 +727,7 @@ pub fn vabaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { } #[doc = "Absolute difference and accumulate (128-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s8"))] @@ -748,7 +748,7 @@ pub fn vabaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { } #[doc = "Absolute difference and accumulate (128-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u16"))] @@ -769,7 +769,7 @@ pub fn vabaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { } #[doc = "Absolute difference and accumulate (128-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u32"))] @@ -790,7 +790,7 @@ pub fn vabaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { } #[doc = "Absolute difference and accumulate (128-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u8"))] @@ -811,7 +811,7 @@ pub fn vabaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { } #[doc = "Absolute difference between the arguments of Floating"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f16"))] #[cfg_attr( @@ -821,7 +821,7 @@ pub fn vabaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -841,7 +841,7 @@ pub fn vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { } #[doc = "Absolute difference between the arguments of Floating"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f16"))] #[cfg_attr( @@ -851,7 +851,7 @@ pub fn vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -871,7 +871,7 @@ pub fn vabdq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { } #[doc = "Absolute difference between the arguments of Floating"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))] @@ -900,7 +900,7 @@ pub fn vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } #[doc = "Absolute difference between the arguments of Floating"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))] @@ -929,7 +929,7 @@ pub fn vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))] @@ -958,7 +958,7 @@ pub fn vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))] @@ -987,7 +987,7 @@ pub fn vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))] @@ -1016,7 +1016,7 @@ pub fn vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))] @@ -1045,7 +1045,7 @@ pub fn vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))] @@ -1074,7 +1074,7 @@ pub fn vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))] @@ -1103,7 +1103,7 @@ pub fn vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))] @@ -1132,7 +1132,7 @@ pub fn vabd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))] @@ -1161,7 +1161,7 @@ pub fn vabdq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))] @@ -1190,7 +1190,7 @@ pub fn vabd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))] @@ -1219,7 +1219,7 @@ pub fn vabdq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))] @@ -1248,7 +1248,7 @@ pub fn vabd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))] @@ -1277,7 +1277,7 @@ pub fn vabdq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Signed Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s8"))] @@ -1301,7 +1301,7 @@ pub fn vabdl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { } #[doc = "Signed Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s16"))] @@ -1325,7 +1325,7 @@ pub fn vabdl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { } #[doc = "Signed Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s32"))] @@ -1349,7 +1349,7 @@ pub fn vabdl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { } #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u8"))] @@ -1370,7 +1370,7 @@ pub fn vabdl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { } #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u16"))] @@ -1391,7 +1391,7 @@ pub fn vabdl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { } #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u32"))] @@ -1412,7 +1412,7 @@ pub fn vabdl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { } #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] #[cfg_attr( @@ -1422,7 +1422,7 @@ pub fn vabdl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -1434,7 +1434,7 @@ pub fn vabs_f16(a: float16x4_t) -> float16x4_t { } #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] #[cfg_attr( @@ -1444,7 +1444,7 @@ pub fn vabs_f16(a: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -1456,7 +1456,7 @@ pub fn vabsq_f16(a: float16x8_t) -> float16x8_t { } #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] @@ -1477,7 +1477,7 @@ pub fn vabs_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] @@ -1498,7 +1498,7 @@ pub fn vabsq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Absolute value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] @@ -1523,7 +1523,7 @@ pub fn vabs_s8(a: int8x8_t) -> int8x8_t { } #[doc = "Absolute value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] @@ -1548,7 +1548,7 @@ pub fn vabsq_s8(a: int8x16_t) -> int8x16_t { } #[doc = "Absolute value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] @@ -1573,7 +1573,7 @@ pub fn vabs_s16(a: int16x4_t) -> int16x4_t { } #[doc = "Absolute value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] @@ -1598,7 +1598,7 @@ pub fn vabsq_s16(a: int16x8_t) -> int16x8_t { } #[doc = "Absolute value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] @@ -1623,7 +1623,7 @@ pub fn vabs_s32(a: int32x2_t) -> int32x2_t { } #[doc = "Absolute value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] @@ -1648,7 +1648,7 @@ pub fn vabsq_s32(a: int32x4_t) -> int32x4_t { } #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] #[cfg_attr( @@ -1659,11 +1659,11 @@ pub fn vabsq_s32(a: int32x4_t) -> int32x4_t { #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vabsh_f16(a: f16) -> f16 { - unsafe { simd_extract!(vabs_f16(vdup_n_f16(a)), 0) } + vget_lane_f16::<0>(vabs_f16(vdup_n_f16(a))) } #[doc = "Floating-point Add (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))] #[cfg_attr( @@ -1673,7 +1673,7 @@ pub fn vabsh_f16(a: f16) -> f16 { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -1685,7 +1685,7 @@ pub fn vadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { } #[doc = "Floating-point Add (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))] #[cfg_attr( @@ -1695,7 +1695,7 @@ pub fn vadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -1707,7 +1707,7 @@ pub fn vaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1728,7 +1728,7 @@ pub fn vadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1749,7 +1749,7 @@ pub fn vadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1770,7 +1770,7 @@ pub fn vadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1791,7 +1791,7 @@ pub fn vadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1812,7 +1812,7 @@ pub fn vadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1833,7 +1833,7 @@ pub fn vadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1854,7 +1854,7 @@ pub fn vadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1875,7 +1875,7 @@ pub fn vaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1896,7 +1896,7 @@ pub fn vaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1917,7 +1917,7 @@ pub fn vaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1938,7 +1938,7 @@ pub fn vaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1959,7 +1959,7 @@ pub fn vaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1980,7 +1980,7 @@ pub fn vaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -2001,7 +2001,7 @@ pub fn vaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -2022,7 +2022,7 @@ pub fn vaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -2043,7 +2043,7 @@ pub fn vaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -2064,7 +2064,7 @@ pub fn vadd_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { } #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -2085,7 +2085,7 @@ pub fn vaddq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { } #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -2106,7 +2106,7 @@ pub fn vadd_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { } #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -2127,7 +2127,7 @@ pub fn vaddq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { } #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -2148,7 +2148,7 @@ pub fn vadd_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t { } #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -2169,7 +2169,7 @@ pub fn vaddq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { } #[doc = "Add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))] #[cfg_attr( @@ -2184,12 +2184,16 @@ pub fn vaddh_f16(a: f16, b: f16) -> f16 { } #[doc = "Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(addhn2) )] #[cfg_attr( @@ -2203,17 +2207,21 @@ pub fn vaddh_f16(a: f16, b: f16) -> f16 { pub fn vaddhn_high_s16(r: int8x8_t, a: int16x8_t, b: int16x8_t) -> int8x16_t { unsafe { let x = simd_cast(simd_shr(simd_add(a, b), int16x8_t::splat(8))); - simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) + vcombine_s8(r, x) } } #[doc = "Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(addhn2) )] #[cfg_attr( @@ -2227,17 +2235,21 @@ pub fn vaddhn_high_s16(r: int8x8_t, a: int16x8_t, b: int16x8_t) -> int8x16_t { pub fn vaddhn_high_s32(r: int16x4_t, a: int32x4_t, b: int32x4_t) -> int16x8_t { unsafe { let x = simd_cast(simd_shr(simd_add(a, b), int32x4_t::splat(16))); - simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7]) + vcombine_s16(r, x) } } #[doc = "Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(addhn2) )] #[cfg_attr( @@ -2251,17 +2263,21 @@ pub fn vaddhn_high_s32(r: int16x4_t, a: int32x4_t, b: int32x4_t) -> int16x8_t { pub fn vaddhn_high_s64(r: int32x2_t, a: int64x2_t, b: int64x2_t) -> int32x4_t { unsafe { let x = simd_cast(simd_shr(simd_add(a, b), int64x2_t::splat(32))); - simd_shuffle!(r, x, [0, 1, 2, 3]) + vcombine_s32(r, x) } } #[doc = "Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(addhn2) )] #[cfg_attr( @@ -2275,17 +2291,21 @@ pub fn vaddhn_high_s64(r: int32x2_t, a: int64x2_t, b: int64x2_t) -> int32x4_t { pub fn vaddhn_high_u16(r: uint8x8_t, a: uint16x8_t, b: uint16x8_t) -> uint8x16_t { unsafe { let x = simd_cast(simd_shr(simd_add(a, b), uint16x8_t::splat(8))); - simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) + vcombine_u8(r, x) } } #[doc = "Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(addhn2) )] #[cfg_attr( @@ -2299,17 +2319,21 @@ pub fn vaddhn_high_u16(r: uint8x8_t, a: uint16x8_t, b: uint16x8_t) -> uint8x16_t pub fn vaddhn_high_u32(r: uint16x4_t, a: uint32x4_t, b: uint32x4_t) -> uint16x8_t { unsafe { let x = simd_cast(simd_shr(simd_add(a, b), uint32x4_t::splat(16))); - simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7]) + vcombine_u16(r, x) } } #[doc = "Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(addhn2) )] #[cfg_attr( @@ -2323,12 +2347,12 @@ pub fn vaddhn_high_u32(r: uint16x4_t, a: uint32x4_t, b: uint32x4_t) -> uint16x8_ pub fn vaddhn_high_u64(r: uint32x2_t, a: uint64x2_t, b: uint64x2_t) -> uint32x4_t { unsafe { let x = simd_cast(simd_shr(simd_add(a, b), uint64x2_t::splat(32))); - simd_shuffle!(r, x, [0, 1, 2, 3]) + vcombine_u32(r, x) } } #[doc = "Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] @@ -2349,7 +2373,7 @@ pub fn vaddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { } #[doc = "Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] @@ -2370,7 +2394,7 @@ pub fn vaddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { } #[doc = "Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] @@ -2391,7 +2415,7 @@ pub fn vaddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { } #[doc = "Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] @@ -2412,7 +2436,7 @@ pub fn vaddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { } #[doc = "Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] @@ -2433,7 +2457,7 @@ pub fn vaddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { } #[doc = "Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] @@ -2454,12 +2478,16 @@ pub fn vaddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { } #[doc = "Signed Add Long (vector, high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(saddl2) )] #[cfg_attr( @@ -2471,9 +2499,9 @@ pub fn vaddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { + let a: int16x4_t = vget_high_s16(a); + let b: int16x4_t = vget_high_s16(b); unsafe { - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); let a: int32x4_t = simd_cast(a); let b: int32x4_t = simd_cast(b); simd_add(a, b) @@ -2481,12 +2509,16 @@ pub fn vaddl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { } #[doc = "Signed Add Long (vector, high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(saddl2) )] #[cfg_attr( @@ -2498,9 +2530,9 @@ pub fn vaddl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { + let a: int32x2_t = vget_high_s32(a); + let b: int32x2_t = vget_high_s32(b); unsafe { - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); let a: int64x2_t = simd_cast(a); let b: int64x2_t = simd_cast(b); simd_add(a, b) @@ -2508,12 +2540,16 @@ pub fn vaddl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { } #[doc = "Signed Add Long (vector, high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(saddl2) )] #[cfg_attr( @@ -2525,9 +2561,9 @@ pub fn vaddl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { + let a: int8x8_t = vget_high_s8(a); + let b: int8x8_t = vget_high_s8(b); unsafe { - let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); let a: int16x8_t = simd_cast(a); let b: int16x8_t = simd_cast(b); simd_add(a, b) @@ -2535,12 +2571,16 @@ pub fn vaddl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { } #[doc = "Signed Add Long (vector, high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(uaddl2) )] #[cfg_attr( @@ -2552,9 +2592,9 @@ pub fn vaddl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { + let a: uint16x4_t = vget_high_u16(a); + let b: uint16x4_t = vget_high_u16(b); unsafe { - let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); let a: uint32x4_t = simd_cast(a); let b: uint32x4_t = simd_cast(b); simd_add(a, b) @@ -2562,12 +2602,16 @@ pub fn vaddl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { } #[doc = "Signed Add Long (vector, high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(uaddl2) )] #[cfg_attr( @@ -2579,9 +2623,9 @@ pub fn vaddl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { + let a: uint32x2_t = vget_high_u32(a); + let b: uint32x2_t = vget_high_u32(b); unsafe { - let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); let a: uint64x2_t = simd_cast(a); let b: uint64x2_t = simd_cast(b); simd_add(a, b) @@ -2589,12 +2633,16 @@ pub fn vaddl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { } #[doc = "Signed Add Long (vector, high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(uaddl2) )] #[cfg_attr( @@ -2606,9 +2654,9 @@ pub fn vaddl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { + let a: uint8x8_t = vget_high_u8(a); + let b: uint8x8_t = vget_high_u8(b); unsafe { - let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); let a: uint16x8_t = simd_cast(a); let b: uint16x8_t = simd_cast(b); simd_add(a, b) @@ -2616,7 +2664,7 @@ pub fn vaddl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { } #[doc = "Add Long (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] @@ -2641,7 +2689,7 @@ pub fn vaddl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { } #[doc = "Add Long (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] @@ -2666,7 +2714,7 @@ pub fn vaddl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { } #[doc = "Add Long (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] @@ -2691,7 +2739,7 @@ pub fn vaddl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { } #[doc = "Add Long (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] @@ -2716,7 +2764,7 @@ pub fn vaddl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { } #[doc = "Add Long (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] @@ -2741,7 +2789,7 @@ pub fn vaddl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { } #[doc = "Add Long (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] @@ -2766,7 +2814,7 @@ pub fn vaddl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { } #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p128)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -2787,12 +2835,16 @@ pub fn vaddq_p128(a: p128, b: p128) -> p128 { } #[doc = "Add Wide (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(saddw2) )] #[cfg_attr( @@ -2804,20 +2856,24 @@ pub fn vaddq_p128(a: p128, b: p128) -> p128 { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { + let b = vget_high_s16(b); unsafe { - let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); let b: int32x4_t = simd_cast(b); simd_add(a, b) } } #[doc = "Add Wide (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(saddw2) )] #[cfg_attr( @@ -2829,20 +2885,24 @@ pub fn vaddw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { + let b = vget_high_s32(b); unsafe { - let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); let b: int64x2_t = simd_cast(b); simd_add(a, b) } } #[doc = "Add Wide (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(saddw2) )] #[cfg_attr( @@ -2854,20 +2914,24 @@ pub fn vaddw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { + let b = vget_high_s8(b); unsafe { - let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); let b: int16x8_t = simd_cast(b); simd_add(a, b) } } #[doc = "Add Wide (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(uaddw2) )] #[cfg_attr( @@ -2879,20 +2943,24 @@ pub fn vaddw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { + let b = vget_high_u16(b); unsafe { - let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); let b: uint32x4_t = simd_cast(b); simd_add(a, b) } } #[doc = "Add Wide (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(uaddw2) )] #[cfg_attr( @@ -2904,20 +2972,24 @@ pub fn vaddw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { + let b = vget_high_u32(b); unsafe { - let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); let b: uint64x2_t = simd_cast(b); simd_add(a, b) } } #[doc = "Add Wide (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(uaddw2) )] #[cfg_attr( @@ -2929,15 +3001,15 @@ pub fn vaddw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { + let b = vget_high_u8(b); unsafe { - let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); let b: uint16x8_t = simd_cast(b); simd_add(a, b) } } #[doc = "Add Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] @@ -2961,7 +3033,7 @@ pub fn vaddw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t { } #[doc = "Add Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] @@ -2985,7 +3057,7 @@ pub fn vaddw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t { } #[doc = "Add Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] @@ -3009,7 +3081,7 @@ pub fn vaddw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t { } #[doc = "Add Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] @@ -3033,7 +3105,7 @@ pub fn vaddw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t { } #[doc = "Add Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] @@ -3057,7 +3129,7 @@ pub fn vaddw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t { } #[doc = "Add Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] @@ -3081,7 +3153,8 @@ pub fn vaddw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t { } #[doc = "AES single round encryption."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesdq_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(aesd))] @@ -3105,8 +3178,52 @@ pub fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t { unsafe { _vaesdq_u8(data, key) } } #[doc = "AES single round encryption."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesdq_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(test, assert_instr(aesd))] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") +)] +pub fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.aesd" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesd")] + fn _vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t; + } + unsafe { + let data: uint8x16_t = simd_shuffle!( + data, + data, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let key: uint8x16_t = simd_shuffle!( + key, + key, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let ret_val: uint8x16_t = _vaesdq_u8(data, key); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "AES single round encryption."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaeseq_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(aese))] @@ -3129,9 +3246,53 @@ pub fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t { } unsafe { _vaeseq_u8(data, key) } } +#[doc = "AES single round encryption."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaeseq_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(test, assert_instr(aese))] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") +)] +pub fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.aese" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aese")] + fn _vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t; + } + unsafe { + let data: uint8x16_t = simd_shuffle!( + data, + data, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let key: uint8x16_t = simd_shuffle!( + key, + key, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let ret_val: uint8x16_t = _vaeseq_u8(data, key); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} #[doc = "AES inverse mix columns."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesimcq_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(aesimc))] @@ -3154,9 +3315,48 @@ pub fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t { } unsafe { _vaesimcq_u8(data) } } +#[doc = "AES inverse mix columns."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesimcq_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(test, assert_instr(aesimc))] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") +)] +pub fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.aesimc" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesimc")] + fn _vaesimcq_u8(data: uint8x16_t) -> uint8x16_t; + } + unsafe { + let data: uint8x16_t = simd_shuffle!( + data, + data, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let ret_val: uint8x16_t = _vaesimcq_u8(data); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} #[doc = "AES mix columns."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesmcq_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(aesmc))] @@ -3179,9 +3379,47 @@ pub fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t { } unsafe { _vaesmcq_u8(data) } } +#[doc = "AES mix columns."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesmcq_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(test, assert_instr(aesmc))] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") +)] +pub fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.aesmc" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesmc")] + fn _vaesmcq_u8(data: uint8x16_t) -> uint8x16_t; + } + unsafe { + let data: uint8x16_t = simd_shuffle!( + data, + data, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let ret_val: uint8x16_t = _vaesmcq_u8(data); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3202,7 +3440,7 @@ pub fn vand_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3223,7 +3461,7 @@ pub fn vandq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3244,7 +3482,7 @@ pub fn vand_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3265,7 +3503,7 @@ pub fn vandq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3286,7 +3524,7 @@ pub fn vand_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3307,7 +3545,7 @@ pub fn vandq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3328,7 +3566,7 @@ pub fn vand_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3349,7 +3587,7 @@ pub fn vandq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3370,7 +3608,7 @@ pub fn vand_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3391,7 +3629,7 @@ pub fn vandq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3412,7 +3650,7 @@ pub fn vand_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3433,7 +3671,7 @@ pub fn vandq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3454,7 +3692,7 @@ pub fn vand_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3475,7 +3713,7 @@ pub fn vandq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3496,7 +3734,7 @@ pub fn vand_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3517,7 +3755,7 @@ pub fn vandq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3539,7 +3777,7 @@ pub fn vbic_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3561,7 +3799,7 @@ pub fn vbic_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3583,7 +3821,7 @@ pub fn vbic_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3605,7 +3843,7 @@ pub fn vbic_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3627,7 +3865,7 @@ pub fn vbicq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3649,7 +3887,7 @@ pub fn vbicq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3671,7 +3909,7 @@ pub fn vbicq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3693,7 +3931,7 @@ pub fn vbicq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3715,7 +3953,7 @@ pub fn vbic_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3737,7 +3975,7 @@ pub fn vbic_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3759,7 +3997,7 @@ pub fn vbic_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3781,7 +4019,7 @@ pub fn vbic_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3803,7 +4041,7 @@ pub fn vbicq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3825,7 +4063,7 @@ pub fn vbicq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3847,7 +4085,7 @@ pub fn vbicq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3869,7 +4107,7 @@ pub fn vbicq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -3879,7 +4117,7 @@ pub fn vbicq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -3897,7 +4135,7 @@ pub fn vbsl_f16(a: uint16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -3907,7 +4145,7 @@ pub fn vbsl_f16(a: uint16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -3925,7 +4163,7 @@ pub fn vbslq_f16(a: uint16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -3952,7 +4190,7 @@ pub fn vbsl_f32(a: uint32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -3979,7 +4217,7 @@ pub fn vbsl_p16(a: uint16x4_t, b: poly16x4_t, c: poly16x4_t) -> poly16x4_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4006,7 +4244,7 @@ pub fn vbsl_p8(a: uint8x8_t, b: poly8x8_t, c: poly8x8_t) -> poly8x8_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4033,7 +4271,7 @@ pub fn vbsl_s16(a: uint16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4060,7 +4298,7 @@ pub fn vbsl_s32(a: uint32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4087,7 +4325,7 @@ pub fn vbsl_s64(a: uint64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4114,7 +4352,7 @@ pub fn vbsl_s8(a: uint8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4141,7 +4379,7 @@ pub fn vbslq_f32(a: uint32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4168,7 +4406,7 @@ pub fn vbslq_p16(a: uint16x8_t, b: poly16x8_t, c: poly16x8_t) -> poly16x8_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4195,7 +4433,7 @@ pub fn vbslq_p8(a: uint8x16_t, b: poly8x16_t, c: poly8x16_t) -> poly8x16_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4222,7 +4460,7 @@ pub fn vbslq_s16(a: uint16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4249,7 +4487,7 @@ pub fn vbslq_s32(a: uint32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4276,7 +4514,7 @@ pub fn vbslq_s64(a: uint64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4303,7 +4541,7 @@ pub fn vbslq_s8(a: uint8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4330,7 +4568,7 @@ pub fn vbsl_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4357,7 +4595,7 @@ pub fn vbsl_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4384,7 +4622,7 @@ pub fn vbsl_u64(a: uint64x1_t, b: uint64x1_t, c: uint64x1_t) -> uint64x1_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4411,7 +4649,7 @@ pub fn vbsl_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4438,7 +4676,7 @@ pub fn vbslq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4465,7 +4703,7 @@ pub fn vbslq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4492,7 +4730,7 @@ pub fn vbslq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4519,7 +4757,7 @@ pub fn vbslq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))] #[cfg_attr( @@ -4529,7 +4767,7 @@ pub fn vbslq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4549,7 +4787,7 @@ pub fn vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))] #[cfg_attr( @@ -4559,7 +4797,7 @@ pub fn vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4579,7 +4817,7 @@ pub fn vcageq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))] @@ -4608,7 +4846,7 @@ pub fn vcage_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))] @@ -4637,7 +4875,7 @@ pub fn vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))] #[cfg_attr( @@ -4647,7 +4885,7 @@ pub fn vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4667,7 +4905,7 @@ pub fn vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))] #[cfg_attr( @@ -4677,7 +4915,7 @@ pub fn vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4697,7 +4935,7 @@ pub fn vcagtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))] @@ -4726,7 +4964,7 @@ pub fn vcagt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))] @@ -4755,7 +4993,7 @@ pub fn vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))] #[cfg_attr( @@ -4765,7 +5003,7 @@ pub fn vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4777,7 +5015,7 @@ pub fn vcale_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))] #[cfg_attr( @@ -4787,7 +5025,7 @@ pub fn vcale_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4799,7 +5037,7 @@ pub fn vcaleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))] @@ -4820,7 +5058,7 @@ pub fn vcale_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))] @@ -4841,7 +5079,7 @@ pub fn vcaleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))] #[cfg_attr( @@ -4851,7 +5089,7 @@ pub fn vcaleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4863,7 +5101,7 @@ pub fn vcalt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))] #[cfg_attr( @@ -4873,7 +5111,7 @@ pub fn vcalt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4885,7 +5123,7 @@ pub fn vcaltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))] @@ -4906,7 +5144,7 @@ pub fn vcalt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))] @@ -4927,7 +5165,7 @@ pub fn vcaltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f16"))] #[cfg_attr( @@ -4937,7 +5175,7 @@ pub fn vcaltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4949,7 +5187,7 @@ pub fn vceq_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f16"))] #[cfg_attr( @@ -4959,7 +5197,7 @@ pub fn vceq_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4971,7 +5209,7 @@ pub fn vceqq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))] @@ -4992,7 +5230,7 @@ pub fn vceq_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))] @@ -5013,7 +5251,7 @@ pub fn vceqq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))] @@ -5034,7 +5272,7 @@ pub fn vceq_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))] @@ -5055,7 +5293,7 @@ pub fn vceqq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))] @@ -5076,7 +5314,7 @@ pub fn vceq_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))] @@ -5097,7 +5335,7 @@ pub fn vceqq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))] @@ -5118,7 +5356,7 @@ pub fn vceq_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))] @@ -5139,7 +5377,7 @@ pub fn vceqq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))] @@ -5160,7 +5398,7 @@ pub fn vceq_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))] @@ -5181,7 +5419,7 @@ pub fn vceqq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))] @@ -5202,7 +5440,7 @@ pub fn vceq_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))] @@ -5223,7 +5461,7 @@ pub fn vceqq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))] @@ -5244,7 +5482,7 @@ pub fn vceq_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))] @@ -5265,7 +5503,7 @@ pub fn vceqq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))] @@ -5286,7 +5524,7 @@ pub fn vceq_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))] @@ -5307,7 +5545,7 @@ pub fn vceqq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))] #[cfg_attr( @@ -5317,7 +5555,7 @@ pub fn vceqq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -5329,7 +5567,7 @@ pub fn vcge_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))] #[cfg_attr( @@ -5339,7 +5577,7 @@ pub fn vcge_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -5351,7 +5589,7 @@ pub fn vcgeq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))] @@ -5372,7 +5610,7 @@ pub fn vcge_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))] @@ -5393,7 +5631,7 @@ pub fn vcgeq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))] @@ -5414,7 +5652,7 @@ pub fn vcge_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))] @@ -5435,7 +5673,7 @@ pub fn vcgeq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))] @@ -5456,7 +5694,7 @@ pub fn vcge_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))] @@ -5477,7 +5715,7 @@ pub fn vcgeq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))] @@ -5498,7 +5736,7 @@ pub fn vcge_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))] @@ -5519,7 +5757,7 @@ pub fn vcgeq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))] @@ -5540,7 +5778,7 @@ pub fn vcge_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))] @@ -5561,7 +5799,7 @@ pub fn vcgeq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))] @@ -5582,7 +5820,7 @@ pub fn vcge_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))] @@ -5603,7 +5841,7 @@ pub fn vcgeq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))] @@ -5624,7 +5862,7 @@ pub fn vcge_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))] @@ -5645,7 +5883,7 @@ pub fn vcgeq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))] #[cfg_attr( @@ -5655,7 +5893,7 @@ pub fn vcgeq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -5668,7 +5906,7 @@ pub fn vcgez_f16(a: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))] #[cfg_attr( @@ -5678,7 +5916,7 @@ pub fn vcgez_f16(a: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -5691,7 +5929,7 @@ pub fn vcgezq_f16(a: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))] #[cfg_attr( @@ -5701,7 +5939,7 @@ pub fn vcgezq_f16(a: float16x8_t) -> uint16x8_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -5713,7 +5951,7 @@ pub fn vcgt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))] #[cfg_attr( @@ -5723,7 +5961,7 @@ pub fn vcgt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -5735,7 +5973,7 @@ pub fn vcgtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))] @@ -5756,7 +5994,7 @@ pub fn vcgt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))] @@ -5777,7 +6015,7 @@ pub fn vcgtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))] @@ -5798,7 +6036,7 @@ pub fn vcgt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))] @@ -5819,7 +6057,7 @@ pub fn vcgtq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))] @@ -5840,7 +6078,7 @@ pub fn vcgt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))] @@ -5861,7 +6099,7 @@ pub fn vcgtq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))] @@ -5882,7 +6120,7 @@ pub fn vcgt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))] @@ -5903,7 +6141,7 @@ pub fn vcgtq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))] @@ -5924,7 +6162,7 @@ pub fn vcgt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))] @@ -5945,7 +6183,7 @@ pub fn vcgtq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))] @@ -5966,7 +6204,7 @@ pub fn vcgt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))] @@ -5987,7 +6225,7 @@ pub fn vcgtq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))] @@ -6008,7 +6246,7 @@ pub fn vcgt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))] @@ -6029,7 +6267,7 @@ pub fn vcgtq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))] #[cfg_attr( @@ -6039,7 +6277,7 @@ pub fn vcgtq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6052,7 +6290,7 @@ pub fn vcgtz_f16(a: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))] #[cfg_attr( @@ -6062,7 +6300,7 @@ pub fn vcgtz_f16(a: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6075,7 +6313,7 @@ pub fn vcgtzq_f16(a: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))] #[cfg_attr( @@ -6085,7 +6323,7 @@ pub fn vcgtzq_f16(a: float16x8_t) -> uint16x8_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6097,7 +6335,7 @@ pub fn vcle_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))] #[cfg_attr( @@ -6107,7 +6345,7 @@ pub fn vcle_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6119,7 +6357,7 @@ pub fn vcleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))] @@ -6140,7 +6378,7 @@ pub fn vcle_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))] @@ -6161,7 +6399,7 @@ pub fn vcleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))] @@ -6182,7 +6420,7 @@ pub fn vcle_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))] @@ -6203,7 +6441,7 @@ pub fn vcleq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))] @@ -6224,7 +6462,7 @@ pub fn vcle_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))] @@ -6245,7 +6483,7 @@ pub fn vcleq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))] @@ -6266,7 +6504,7 @@ pub fn vcle_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))] @@ -6287,7 +6525,7 @@ pub fn vcleq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))] @@ -6308,7 +6546,7 @@ pub fn vcle_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))] @@ -6329,7 +6567,7 @@ pub fn vcleq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))] @@ -6350,7 +6588,7 @@ pub fn vcle_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))] @@ -6371,7 +6609,7 @@ pub fn vcleq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))] @@ -6392,7 +6630,7 @@ pub fn vcle_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))] @@ -6413,7 +6651,7 @@ pub fn vcleq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcle.f16"))] #[cfg_attr( @@ -6423,7 +6661,7 @@ pub fn vcleq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6436,7 +6674,7 @@ pub fn vclez_f16(a: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcle.f16"))] #[cfg_attr( @@ -6446,7 +6684,7 @@ pub fn vclez_f16(a: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6459,7 +6697,7 @@ pub fn vclezq_f16(a: float16x8_t) -> uint16x8_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))] @@ -6488,7 +6726,7 @@ pub fn vcls_s8(a: int8x8_t) -> int8x8_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))] @@ -6517,7 +6755,7 @@ pub fn vclsq_s8(a: int8x16_t) -> int8x16_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))] @@ -6546,7 +6784,7 @@ pub fn vcls_s16(a: int16x4_t) -> int16x4_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))] @@ -6575,7 +6813,7 @@ pub fn vclsq_s16(a: int16x8_t) -> int16x8_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))] @@ -6604,7 +6842,7 @@ pub fn vcls_s32(a: int32x2_t) -> int32x2_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))] @@ -6633,7 +6871,7 @@ pub fn vclsq_s32(a: int32x4_t) -> int32x4_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] @@ -6654,7 +6892,7 @@ pub fn vcls_u8(a: uint8x8_t) -> int8x8_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] @@ -6675,7 +6913,7 @@ pub fn vclsq_u8(a: uint8x16_t) -> int8x16_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] @@ -6696,7 +6934,7 @@ pub fn vcls_u16(a: uint16x4_t) -> int16x4_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] @@ -6717,7 +6955,7 @@ pub fn vclsq_u16(a: uint16x8_t) -> int16x8_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] @@ -6738,7 +6976,7 @@ pub fn vcls_u32(a: uint32x2_t) -> int32x2_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] @@ -6759,7 +6997,7 @@ pub fn vclsq_u32(a: uint32x4_t) -> int32x4_t { } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))] #[cfg_attr( @@ -6769,7 +7007,7 @@ pub fn vclsq_u32(a: uint32x4_t) -> int32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6781,7 +7019,7 @@ pub fn vclt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))] #[cfg_attr( @@ -6791,7 +7029,7 @@ pub fn vclt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6803,7 +7041,7 @@ pub fn vcltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))] @@ -6824,7 +7062,7 @@ pub fn vclt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))] @@ -6845,7 +7083,7 @@ pub fn vcltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))] @@ -6866,7 +7104,7 @@ pub fn vclt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))] @@ -6887,7 +7125,7 @@ pub fn vcltq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))] @@ -6908,7 +7146,7 @@ pub fn vclt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))] @@ -6929,7 +7167,7 @@ pub fn vcltq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))] @@ -6950,7 +7188,7 @@ pub fn vclt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))] @@ -6971,7 +7209,7 @@ pub fn vcltq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))] @@ -6992,7 +7230,7 @@ pub fn vclt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))] @@ -7013,7 +7251,7 @@ pub fn vcltq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))] @@ -7034,7 +7272,7 @@ pub fn vclt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))] @@ -7055,7 +7293,7 @@ pub fn vcltq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))] @@ -7076,7 +7314,7 @@ pub fn vclt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))] @@ -7097,7 +7335,7 @@ pub fn vcltq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclt.f16"))] #[cfg_attr( @@ -7107,7 +7345,7 @@ pub fn vcltq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -7120,7 +7358,7 @@ pub fn vcltz_f16(a: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclt.f16"))] #[cfg_attr( @@ -7130,7 +7368,7 @@ pub fn vcltz_f16(a: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -7143,7 +7381,7 @@ pub fn vcltzq_f16(a: float16x8_t) -> uint16x8_t { } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))] @@ -7164,7 +7402,7 @@ pub fn vclz_s8(a: int8x8_t) -> int8x8_t { } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))] @@ -7185,7 +7423,7 @@ pub fn vclzq_s8(a: int8x16_t) -> int8x16_t { } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))] @@ -7206,7 +7444,7 @@ pub fn vclz_s16(a: int16x4_t) -> int16x4_t { } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))] @@ -7227,7 +7465,7 @@ pub fn vclzq_s16(a: int16x8_t) -> int16x8_t { } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))] @@ -7248,7 +7486,7 @@ pub fn vclz_s32(a: int32x2_t) -> int32x2_t { } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))] @@ -7269,8 +7507,7 @@ pub fn vclzq_s32(a: int32x4_t) -> int32x4_t { } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))] @@ -7290,35 +7527,8 @@ pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t { unsafe { transmute(vclz_s16(transmute(a))) } } #[doc = "Count leading zero bits"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(clz) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x4_t = transmute(vclz_s16(transmute(a))); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))] @@ -7338,35 +7548,8 @@ pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t { unsafe { transmute(vclzq_s16(transmute(a))) } } #[doc = "Count leading zero bits"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(clz) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(vclzq_s16(transmute(a))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))] @@ -7386,35 +7569,8 @@ pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t { unsafe { transmute(vclz_s32(transmute(a))) } } #[doc = "Count leading zero bits"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(clz) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint32x2_t = transmute(vclz_s32(transmute(a))); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))] @@ -7434,35 +7590,8 @@ pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t { unsafe { transmute(vclzq_s32(transmute(a))) } } #[doc = "Count leading zero bits"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(clz) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x4_t = transmute(vclzq_s32(transmute(a))); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))] @@ -7482,35 +7611,8 @@ pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t { unsafe { transmute(vclz_s8(transmute(a))) } } #[doc = "Count leading zero bits"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(clz) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vclz_s8(transmute(a))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))] @@ -7529,40 +7631,9 @@ pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t { pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t { unsafe { transmute(vclzq_s8(transmute(a))) } } -#[doc = "Count leading zero bits"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(clz) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(vclzq_s8(transmute(a))); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} #[doc = "Population count per byte."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))] @@ -7583,7 +7654,7 @@ pub fn vcnt_s8(a: int8x8_t) -> int8x8_t { } #[doc = "Population count per byte."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))] @@ -7604,8 +7675,7 @@ pub fn vcntq_s8(a: int8x16_t) -> int8x16_t { } #[doc = "Population count per byte."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))] @@ -7625,9 +7695,8 @@ pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t { unsafe { transmute(vcnt_s8(transmute(a))) } } #[doc = "Population count per byte."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))] @@ -7643,17 +7712,12 @@ pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vcnt_s8(transmute(a))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t { + unsafe { transmute(vcntq_s8(transmute(a))) } } #[doc = "Population count per byte."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))] @@ -7669,13 +7733,12 @@ pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t { - unsafe { transmute(vcntq_s8(transmute(a))) } +pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t { + unsafe { transmute(vcnt_s8(transmute(a))) } } #[doc = "Population count per byte."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))] @@ -7691,77 +7754,61 @@ pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(vcntq_s8(transmute(a))); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t { + unsafe { transmute(vcntq_s8(transmute(a))) } } -#[doc = "Population count per byte."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cnt) -)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t { - unsafe { transmute(vcnt_s8(transmute(a))) } +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(nop))] +pub fn vcombine_f16(a: float16x4_t, b: float16x4_t) -> float16x8_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) } } -#[doc = "Population count per byte."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cnt) -)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(nop))] +pub fn vcombine_f16(a: float16x4_t, b: float16x4_t) -> float16x8_t { unsafe { - let ret_val: poly8x8_t = transmute(vcnt_s8(transmute(a))); + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x8_t = simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Population count per byte."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cnt) -)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -7770,20 +7817,16 @@ pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t { - unsafe { transmute(vcntq_s8(transmute(a))) } +pub fn vcombine_f32(a: float32x2_t, b: float32x2_t) -> float32x4_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) } } -#[doc = "Population count per byte."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cnt) -)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -7792,40 +7835,36 @@ pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vcombine_f32(a: float32x2_t, b: float32x2_t) -> float32x4_t { unsafe { - let ret_val: poly8x16_t = transmute(vcntq_s8(transmute(a))); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x4_t = simd_shuffle!(a, b, [0, 1, 2, 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } #[doc = "Join two smaller vectors into a single larger vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(test, assert_instr(nop))] -pub fn vcombine_f16(a: float16x4_t, b: float16x4_t) -> float16x8_t { - unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) } +pub fn vcombine_s8(a: int8x8_t, b: int8x8_t) -> int8x16_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } } #[doc = "Join two smaller vectors into a single larger vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -7837,12 +7876,23 @@ pub fn vcombine_f16(a: float16x4_t, b: float16x4_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcombine_f32(a: float32x2_t, b: float32x2_t) -> float32x4_t { - unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) } +pub fn vcombine_s8(a: int8x8_t, b: int8x8_t) -> int8x16_t { + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = + simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Join two smaller vectors into a single larger vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -7854,12 +7904,13 @@ pub fn vcombine_f32(a: float32x2_t, b: float32x2_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcombine_s8(a: int8x8_t, b: int8x8_t) -> int8x16_t { - unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } +pub fn vcombine_s16(a: int16x4_t, b: int16x4_t) -> int16x8_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Join two smaller vectors into a single larger vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -7872,11 +7923,17 @@ pub fn vcombine_s8(a: int8x8_t, b: int8x8_t) -> int8x16_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vcombine_s16(a: int16x4_t, b: int16x4_t) -> int16x8_t { - unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) } + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Join two smaller vectors into a single larger vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -7892,8 +7949,32 @@ pub fn vcombine_s32(a: int32x2_t, b: int32x2_t) -> int32x4_t { unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) } } #[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vcombine_s32(a: int32x2_t, b: int32x2_t) -> int32x4_t { + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x4_t = simd_shuffle!(a, b, [0, 1, 2, 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Join two smaller vectors into a single larger vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -7909,8 +7990,9 @@ pub fn vcombine_s64(a: int64x1_t, b: int64x1_t) -> int64x2_t { unsafe { simd_shuffle!(a, b, [0, 1]) } } #[doc = "Join two smaller vectors into a single larger vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -7922,12 +8004,16 @@ pub fn vcombine_s64(a: int64x1_t, b: int64x1_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcombine_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t { - unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } +pub fn vcombine_s64(a: int64x1_t, b: int64x1_t) -> int64x2_t { + unsafe { + let ret_val: int64x2_t = simd_shuffle!(a, b, [0, 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Join two smaller vectors into a single larger vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -7939,12 +8025,13 @@ pub fn vcombine_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcombine_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x8_t { - unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) } +pub fn vcombine_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } } #[doc = "Join two smaller vectors into a single larger vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -7956,12 +8043,23 @@ pub fn vcombine_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcombine_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x4_t { - unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) } +pub fn vcombine_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t { + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = + simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Join two smaller vectors into a single larger vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -7973,12 +8071,13 @@ pub fn vcombine_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcombine_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x2_t { - unsafe { simd_shuffle!(a, b, [0, 1]) } +pub fn vcombine_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x8_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Join two smaller vectors into a single larger vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -7990,12 +8089,18 @@ pub fn vcombine_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcombine_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x16_t { - unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } +pub fn vcombine_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x8_t { + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Join two smaller vectors into a single larger vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8007,12 +8112,13 @@ pub fn vcombine_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcombine_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x8_t { - unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) } +pub fn vcombine_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x4_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) } } #[doc = "Join two smaller vectors into a single larger vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8024,71 +8130,60 @@ pub fn vcombine_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcombine_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x2_t { - unsafe { simd_shuffle!(a, b, [0, 1]) } +pub fn vcombine_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x4_t { + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint32x4_t = simd_shuffle!(a, b, [0, 1, 2, 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u64)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vcreate_f16(a: u64) -> float16x4_t { - unsafe { transmute(a) } +pub fn vcombine_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x2_t { + unsafe { simd_shuffle!(a, b, [0, 1]) } } -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u64)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vcreate_f16(a: u64) -> float16x4_t { +pub fn vcombine_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x2_t { unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let ret_val: uint64x2_t = simd_shuffle!(a, b, [0, 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -8097,20 +8192,16 @@ pub fn vcreate_f16(a: u64) -> float16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_f32(a: u64) -> float32x2_t { - unsafe { transmute(a) } +pub fn vcombine_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x16_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } } -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -8119,23 +8210,26 @@ pub fn vcreate_f32(a: u64) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_f32(a: u64) -> float32x2_t { +pub fn vcombine_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x16_t { unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = + simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) } } -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -8144,20 +8238,16 @@ pub fn vcreate_f32(a: u64) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_s8(a: u64) -> int8x8_t { - unsafe { transmute(a) } +pub fn vcombine_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x8_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) } } -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -8166,23 +8256,21 @@ pub fn vcreate_s8(a: u64) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_s8(a: u64) -> int8x8_t { +pub fn vcombine_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x8_t { unsafe { - let ret_val: int8x8_t = transmute(a); + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p64)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -8191,20 +8279,16 @@ pub fn vcreate_s8(a: u64) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_s16(a: u64) -> int16x4_t { - unsafe { transmute(a) } +pub fn vcombine_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x2_t { + unsafe { simd_shuffle!(a, b, [0, 1]) } } -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p64)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -8213,16 +8297,15 @@ pub fn vcreate_s16(a: u64) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_s16(a: u64) -> int16x4_t { +pub fn vcombine_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x2_t { unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let ret_val: poly64x2_t = simd_shuffle!(a, b, [0, 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8230,21 +8313,22 @@ pub fn vcreate_s16(a: u64) -> int16x4_t { all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_s32(a: u64) -> int32x2_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vcreate_f16(a: u64) -> float16x4_t { unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8260,15 +8344,12 @@ pub fn vcreate_s32(a: u64) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_s32(a: u64) -> int32x2_t { - unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vcreate_f32(a: u64) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8284,13 +8365,12 @@ pub fn vcreate_s32(a: u64) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_s64(a: u64) -> int64x1_t { +pub fn vcreate_s8(a: u64) -> int8x8_t { unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8306,13 +8386,12 @@ pub fn vcreate_s64(a: u64) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_u8(a: u64) -> uint8x8_t { +pub fn vcreate_s16(a: u64) -> int16x4_t { unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8328,16 +8407,12 @@ pub fn vcreate_u8(a: u64) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_u8(a: u64) -> uint8x8_t { - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vcreate_s32(a: u64) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8353,13 +8428,12 @@ pub fn vcreate_u8(a: u64) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_u16(a: u64) -> uint16x4_t { +pub fn vcreate_s64(a: u64) -> int64x1_t { unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8375,16 +8449,12 @@ pub fn vcreate_u16(a: u64) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_u16(a: u64) -> uint16x4_t { - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vcreate_u8(a: u64) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8400,13 +8470,12 @@ pub fn vcreate_u16(a: u64) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_u32(a: u64) -> uint32x2_t { +pub fn vcreate_u16(a: u64) -> uint16x4_t { unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8423,14 +8492,11 @@ pub fn vcreate_u32(a: u64) -> uint32x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vcreate_u32(a: u64) -> uint32x2_t { - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } + unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8451,8 +8517,7 @@ pub fn vcreate_u64(a: u64) -> uint64x1_t { } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8472,34 +8537,8 @@ pub fn vcreate_p8(a: u64) -> poly8x8_t { unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vcreate_p8(a: u64) -> poly8x8_t { - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8519,33 +8558,8 @@ pub fn vcreate_p16(a: u64) -> poly16x4_t { unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vcreate_p16(a: u64) -> poly16x4_t { - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8566,7 +8580,7 @@ pub fn vcreate_p64(a: u64) -> poly64x1_t { } #[doc = "Floating-point convert to lower precision narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -8577,7 +8591,7 @@ pub fn vcreate_p64(a: u64) -> poly64x1_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8589,7 +8603,7 @@ pub fn vcvt_f16_f32(a: float32x4_t) -> float16x4_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_s16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] #[cfg_attr( @@ -8599,7 +8613,7 @@ pub fn vcvt_f16_f32(a: float32x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8611,7 +8625,7 @@ pub fn vcvt_f16_s16(a: int16x4_t) -> float16x4_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f16_s16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] #[cfg_attr( @@ -8621,7 +8635,7 @@ pub fn vcvt_f16_s16(a: int16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8633,7 +8647,7 @@ pub fn vcvtq_f16_s16(a: int16x8_t) -> float16x8_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_u16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] #[cfg_attr( @@ -8643,7 +8657,7 @@ pub fn vcvtq_f16_s16(a: int16x8_t) -> float16x8_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8655,7 +8669,7 @@ pub fn vcvt_f16_u16(a: uint16x4_t) -> float16x4_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f16_u16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] #[cfg_attr( @@ -8665,7 +8679,7 @@ pub fn vcvt_f16_u16(a: uint16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8677,7 +8691,7 @@ pub fn vcvtq_f16_u16(a: uint16x8_t) -> float16x8_t { } #[doc = "Floating-point convert to higher precision long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -8688,7 +8702,7 @@ pub fn vcvtq_f16_u16(a: uint16x8_t) -> float16x8_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8700,7 +8714,7 @@ pub fn vcvt_f32_f16(a: float16x4_t) -> float32x4_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -8721,7 +8735,7 @@ pub fn vcvt_f32_s32(a: int32x2_t) -> float32x2_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -8742,7 +8756,7 @@ pub fn vcvtq_f32_s32(a: int32x4_t) -> float32x4_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -8763,7 +8777,7 @@ pub fn vcvt_f32_u32(a: uint32x2_t) -> float32x2_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -8784,7 +8798,7 @@ pub fn vcvtq_f32_u32(a: uint32x4_t) -> float32x4_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f16_s16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] #[cfg_attr( @@ -8795,7 +8809,7 @@ pub fn vcvtq_f32_u32(a: uint32x4_t) -> float32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8819,7 +8833,7 @@ pub fn vcvt_n_f16_s16(a: int16x4_t) -> float16x4_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f16_s16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] #[cfg_attr( @@ -8830,7 +8844,7 @@ pub fn vcvt_n_f16_s16(a: int16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8854,7 +8868,7 @@ pub fn vcvtq_n_f16_s16(a: int16x8_t) -> float16x8_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f16_u16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] #[cfg_attr( @@ -8865,7 +8879,7 @@ pub fn vcvtq_n_f16_s16(a: int16x8_t) -> float16x8_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8889,7 +8903,7 @@ pub fn vcvt_n_f16_u16(a: uint16x4_t) -> float16x4_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f16_u16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] #[cfg_attr( @@ -8900,7 +8914,7 @@ pub fn vcvt_n_f16_u16(a: uint16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8924,7 +8938,7 @@ pub fn vcvtq_n_f16_u16(a: uint16x8_t) -> float16x8_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] @@ -8943,7 +8957,7 @@ pub fn vcvt_n_f32_s32(a: int32x2_t) -> float32x2_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] @@ -8962,7 +8976,7 @@ pub fn vcvtq_n_f32_s32(a: int32x4_t) -> float32x4_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(scvtf, N = 2))] @@ -8981,7 +8995,7 @@ pub fn vcvt_n_f32_s32(a: int32x2_t) -> float32x2_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(scvtf, N = 2))] @@ -9000,7 +9014,7 @@ pub fn vcvtq_n_f32_s32(a: int32x4_t) -> float32x4_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] @@ -9019,7 +9033,7 @@ pub fn vcvt_n_f32_u32(a: uint32x2_t) -> float32x2_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] @@ -9038,7 +9052,7 @@ pub fn vcvtq_n_f32_u32(a: uint32x4_t) -> float32x4_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] @@ -9057,7 +9071,7 @@ pub fn vcvt_n_f32_u32(a: uint32x2_t) -> float32x2_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] @@ -9076,7 +9090,7 @@ pub fn vcvtq_n_f32_u32(a: uint32x4_t) -> float32x4_t { } #[doc = "Floating-point convert to signed fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] #[cfg_attr( @@ -9087,7 +9101,7 @@ pub fn vcvtq_n_f32_u32(a: uint32x4_t) -> float32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9111,7 +9125,7 @@ pub fn vcvt_n_s16_f16(a: float16x4_t) -> int16x4_t { } #[doc = "Floating-point convert to signed fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] #[cfg_attr( @@ -9122,7 +9136,7 @@ pub fn vcvt_n_s16_f16(a: float16x4_t) -> int16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9146,7 +9160,7 @@ pub fn vcvtq_n_s16_f16(a: float16x8_t) -> int16x8_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] @@ -9165,7 +9179,7 @@ pub fn vcvt_n_s32_f32(a: float32x2_t) -> int32x2_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] @@ -9184,7 +9198,7 @@ pub fn vcvtq_n_s32_f32(a: float32x4_t) -> int32x4_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] @@ -9203,7 +9217,7 @@ pub fn vcvt_n_s32_f32(a: float32x2_t) -> int32x2_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] @@ -9222,7 +9236,7 @@ pub fn vcvtq_n_s32_f32(a: float32x4_t) -> int32x4_t { } #[doc = "Fixed-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] #[cfg_attr( @@ -9233,7 +9247,7 @@ pub fn vcvtq_n_s32_f32(a: float32x4_t) -> int32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9257,7 +9271,7 @@ pub fn vcvt_n_u16_f16(a: float16x4_t) -> uint16x4_t { } #[doc = "Fixed-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] #[cfg_attr( @@ -9268,7 +9282,7 @@ pub fn vcvt_n_u16_f16(a: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9292,7 +9306,7 @@ pub fn vcvtq_n_u16_f16(a: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] @@ -9311,7 +9325,7 @@ pub fn vcvt_n_u32_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] @@ -9330,7 +9344,7 @@ pub fn vcvtq_n_u32_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] @@ -9349,7 +9363,7 @@ pub fn vcvt_n_u32_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] @@ -9368,7 +9382,7 @@ pub fn vcvtq_n_u32_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] #[cfg_attr( @@ -9378,7 +9392,7 @@ pub fn vcvtq_n_u32_f32(a: float32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9390,7 +9404,7 @@ pub fn vcvt_s16_f16(a: float16x4_t) -> int16x4_t { } #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] #[cfg_attr( @@ -9400,7 +9414,7 @@ pub fn vcvt_s16_f16(a: float16x4_t) -> int16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9412,7 +9426,7 @@ pub fn vcvtq_s16_f16(a: float16x8_t) -> int16x8_t { } #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -9441,7 +9455,7 @@ pub fn vcvt_s32_f32(a: float32x2_t) -> int32x2_t { } #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -9470,7 +9484,7 @@ pub fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t { } #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] #[cfg_attr( @@ -9480,7 +9494,7 @@ pub fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9492,7 +9506,7 @@ pub fn vcvt_u16_f16(a: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] #[cfg_attr( @@ -9502,7 +9516,7 @@ pub fn vcvt_u16_f16(a: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9514,7 +9528,7 @@ pub fn vcvtq_u16_f16(a: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -9543,7 +9557,7 @@ pub fn vcvt_u32_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -9572,8 +9586,7 @@ pub fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] @@ -9584,7 +9597,7 @@ pub fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t { #[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_dotprod", issue = "117224") + stable(feature = "stdarch_neon_dotprod", since = "1.98.0") )] #[cfg_attr( target_arch = "arm", @@ -9592,48 +9605,13 @@ pub fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t { )] pub fn vdot_lane_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: int32x2_t = transmute(c); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vdot_s32(a, b, transmute(c)) - } -} -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sdot, LANE = 0) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - unstable(feature = "stdarch_neon_dotprod", issue = "117224") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vdot_lane_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - let b: int8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let c: int32x2_t = transmute(c); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - let ret_val: int32x2_t = vdot_s32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } + let c = vreinterpret_s32_s8(c); + let c = vdup_lane_s32::(c); + vdot_s32(a, b, vreinterpret_s8_s32(c)) } #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] @@ -9644,7 +9622,7 @@ pub fn vdot_lane_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> #[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_dotprod", issue = "117224") + stable(feature = "stdarch_neon_dotprod", since = "1.98.0") )] #[cfg_attr( target_arch = "arm", @@ -9652,79 +9630,13 @@ pub fn vdot_lane_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> )] pub fn vdotq_lane_s32(a: int32x4_t, b: int8x16_t, c: int8x8_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: int32x2_t = transmute(c); - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vdotq_s32(a, b, transmute(c)) - } -} -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sdot, LANE = 0) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - unstable(feature = "stdarch_neon_dotprod", issue = "117224") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vdotq_lane_s32(a: int32x4_t, b: int8x16_t, c: int8x8_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - let b: int8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let c: int32x2_t = transmute(c); - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - let ret_val: int32x4_t = vdotq_s32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(udot, LANE = 0) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - unstable(feature = "stdarch_neon_dotprod", issue = "117224") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vdot_lane_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: uint32x2_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vdot_u32(a, b, transmute(c)) - } + let c = vreinterpret_s32_s8(c); + let c = vdupq_lane_s32::(c); + vdotq_s32(a, b, vreinterpretq_s8_s32(c)) } #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] @@ -9735,7 +9647,7 @@ pub fn vdot_lane_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) #[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_dotprod", issue = "117224") + stable(feature = "stdarch_neon_dotprod", since = "1.98.0") )] #[cfg_attr( target_arch = "arm", @@ -9743,20 +9655,13 @@ pub fn vdot_lane_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) )] pub fn vdot_lane_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t { static_assert_uimm_bits!(LANE, 1); - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let c: uint32x2_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - let ret_val: uint32x2_t = vdot_u32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } + let c = vreinterpret_u32_u8(c); + let c = vdup_lane_u32::(c); + vdot_u32(a, b, vreinterpret_u8_u32(c)) } #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] @@ -9767,7 +9672,7 @@ pub fn vdot_lane_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) #[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_dotprod", issue = "117224") + stable(feature = "stdarch_neon_dotprod", since = "1.98.0") )] #[cfg_attr( target_arch = "arm", @@ -9775,72 +9680,38 @@ pub fn vdot_lane_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) )] pub fn vdotq_lane_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x8_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: uint32x2_t = transmute(c); - let c: uint32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vdotq_u32(a, b, transmute(c)) - } + let c = vreinterpret_u32_u8(c); + let c = vdupq_lane_u32::(c); + vdotq_u32(a, b, vreinterpretq_u8_u32(c)) } #[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(udot, LANE = 0) + assert_instr(sdot, LANE = 0) )] #[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_dotprod", issue = "117224") + stable(feature = "stdarch_neon_dotprod", since = "1.98.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdotq_lane_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x8_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 1); - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let c: uint32x2_t = transmute(c); - let c: uint32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - let ret_val: uint32x4_t = vdotq_u32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sdot, LANE = 0) -)] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] pub fn vdot_laneq_s32(a: int32x2_t, b: int8x8_t, c: int8x16_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: int32x4_t = transmute(c); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vdot_s32(a, b, transmute(c)) - } + let c = vreinterpretq_s32_s8(c); + let c = vdup_laneq_s32::(c); + vdot_s32(a, b, vreinterpret_s8_s32(c)) } #[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] @@ -9849,74 +9720,23 @@ pub fn vdot_laneq_s32(a: int32x2_t, b: int8x8_t, c: int8x16_t) assert_instr(sdot, LANE = 0) )] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub fn vdot_laneq_s32(a: int32x2_t, b: int8x8_t, c: int8x16_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - let b: int8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: int8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let c: int32x4_t = transmute(c); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - let ret_val: int32x2_t = vdot_s32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sdot, LANE = 0) + not(target_arch = "arm"), + stable(feature = "stdarch_neon_dotprod", since = "1.98.0") )] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub fn vdotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: int32x4_t = transmute(c); - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vdotq_s32(a, b, transmute(c)) - } -} -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sdot, LANE = 0) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] pub fn vdotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - let b: int8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: int8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let c: int32x4_t = transmute(c); - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - let ret_val: int32x4_t = vdotq_s32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } + let c = vreinterpretq_s32_s8(c); + let c = vdupq_laneq_s32::(c); + vdotq_s32(a, b, vreinterpretq_s8_s32(c)) } #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] @@ -9925,45 +9745,23 @@ pub fn vdotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t assert_instr(udot, LANE = 0) )] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub fn vdot_laneq_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x16_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: uint32x4_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vdot_u32(a, b, transmute(c)) - } -} -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(udot, LANE = 0) + not(target_arch = "arm"), + stable(feature = "stdarch_neon_dotprod", since = "1.98.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] pub fn vdot_laneq_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x16_t) -> uint32x2_t { static_assert_uimm_bits!(LANE, 2); - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let c: uint32x4_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - let ret_val: uint32x2_t = vdot_u32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } + let c = vreinterpretq_u32_u8(c); + let c = vdup_laneq_u32::(c); + vdot_u32(a, b, vreinterpret_u8_u32(c)) } #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] @@ -9972,47 +9770,54 @@ pub fn vdot_laneq_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x16_ assert_instr(udot, LANE = 0) )] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "stdarch_neon_dotprod", since = "1.98.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub fn vdotq_laneq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: uint32x4_t = transmute(c); - let c: uint32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vdotq_u32(a, b, transmute(c)) - } + let c = vreinterpretq_u32_u8(c); + let c = vdupq_laneq_u32::(c); + vdotq_u32(a, b, vreinterpretq_u8_u32(c)) } -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Dot product arithmetic (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(udot, LANE = 0) + assert_instr(sdot) )] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub fn vdotq_laneq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 2); - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let c: uint32x4_t = transmute(c); - let c: uint32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - let ret_val: uint32x4_t = vdotq_u32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "stdarch_neon_dotprod", since = "1.98.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sdot.v2i32.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sdot.v2i32.v8i8" + )] + fn _vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t; } + unsafe { _vdot_s32(a, b, c) } } #[doc = "Dot product arithmetic (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))] @@ -10022,7 +9827,7 @@ pub fn vdotq_laneq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x1 )] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_dotprod", issue = "117224") + stable(feature = "stdarch_neon_dotprod", since = "1.98.0") )] #[cfg_attr( target_arch = "arm", @@ -10037,11 +9842,18 @@ pub fn vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t { )] fn _vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t; } - unsafe { _vdot_s32(a, b, c) } + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let c: int8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int32x2_t = _vdot_s32(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Dot product arithmetic (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))] @@ -10051,7 +9863,7 @@ pub fn vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_dotprod", issue = "117224") + stable(feature = "stdarch_neon_dotprod", since = "1.98.0") )] #[cfg_attr( target_arch = "arm", @@ -10069,8 +9881,47 @@ pub fn vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { unsafe { _vdotq_s32(a, b, c) } } #[doc = "Dot product arithmetic (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sdot) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "stdarch_neon_dotprod", since = "1.98.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sdot.v4i32.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sdot.v4i32.v16i8" + )] + fn _vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t; + } + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let c: int8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int32x4_t = _vdotq_s32(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Dot product arithmetic (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))] @@ -10080,7 +9931,7 @@ pub fn vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_dotprod", issue = "117224") + stable(feature = "stdarch_neon_dotprod", since = "1.98.0") )] #[cfg_attr( target_arch = "arm", @@ -10098,8 +9949,45 @@ pub fn vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t { unsafe { _vdot_u32(a, b, c) } } #[doc = "Dot product arithmetic (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(udot) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "stdarch_neon_dotprod", since = "1.98.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.udot.v2i32.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.udot.v2i32.v8i8" + )] + fn _vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t; + } + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint32x2_t = _vdot_u32(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Dot product arithmetic (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))] @@ -10109,7 +9997,7 @@ pub fn vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_dotprod", issue = "117224") + stable(feature = "stdarch_neon_dotprod", since = "1.98.0") )] #[cfg_attr( target_arch = "arm", @@ -10126,9 +10014,48 @@ pub fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { } unsafe { _vdotq_u32(a, b, c) } } +#[doc = "Dot product arithmetic (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(udot) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "stdarch_neon_dotprod", since = "1.98.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.udot.v4i32.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.udot.v4i32.v16i8" + )] + fn _vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint32x4_t = _vdotq_u32(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] @@ -10140,7 +10067,7 @@ pub fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -10149,11 +10076,12 @@ pub fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { #[cfg(not(target_arch = "arm64ec"))] pub fn vdup_lane_f16(a: float16x4_t) -> float16x4_t { static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } + unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] @@ -10165,72 +10093,81 @@ pub fn vdup_lane_f16(a: float16x4_t) -> float16x4_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vdupq_lane_f16(a: float16x4_t) -> float16x8_t { +pub fn vdup_lane_f16(a: float16x4_t) -> float16x4_t { static_assert_uimm_bits!(N, 2); unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: float16x4_t = simd_shuffle!(a, a, [N as u32; 4]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 1) + assert_instr(dup, N = 2) )] #[rustc_legacy_const_generics(1)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_lane_f32(a: float32x2_t) -> float32x2_t { - static_assert_uimm_bits!(N, 1); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vdupq_lane_f16(a: float16x4_t) -> float16x8_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 1) + assert_instr(dup, N = 2) )] #[rustc_legacy_const_generics(1)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_lane_s32(a: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(N, 1); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vdupq_lane_f16(a: float16x4_t) -> float16x8_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: float16x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] @@ -10247,13 +10184,14 @@ pub fn vdup_lane_s32(a: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_lane_u32(a: uint32x2_t) -> uint32x2_t { +pub fn vdup_lane_f32(a: float32x2_t) -> float32x2_t { static_assert_uimm_bits!(N, 1); unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] @@ -10270,13 +10208,18 @@ pub fn vdup_lane_u32(a: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_lane_f32(a: float32x2_t) -> float32x4_t { +pub fn vdup_lane_f32(a: float32x2_t) -> float32x2_t { static_assert_uimm_bits!(N, 1); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] @@ -10293,13 +10236,14 @@ pub fn vdupq_lane_f32(a: float32x2_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_lane_s32(a: int32x2_t) -> int32x4_t { +pub fn vdup_lane_s32(a: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(N, 1); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] @@ -10316,19 +10260,24 @@ pub fn vdupq_lane_s32(a: int32x2_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_lane_u32(a: uint32x2_t) -> uint32x4_t { +pub fn vdup_lane_s32(a: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(N, 1); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 2) + assert_instr(dup, N = 1) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10339,19 +10288,20 @@ pub fn vdupq_lane_u32(a: uint32x2_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_lane_p16(a: poly16x4_t) -> poly16x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } +pub fn vdup_lane_u32(a: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 2) + assert_instr(dup, N = 1) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10362,19 +10312,24 @@ pub fn vdup_lane_p16(a: poly16x4_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_lane_s16(a: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } +pub fn vdup_lane_u32(a: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 2) + assert_instr(dup, N = 1) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10385,19 +10340,20 @@ pub fn vdup_lane_s16(a: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_lane_u16(a: uint16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(N, 2); +pub fn vdupq_lane_f32(a: float32x2_t) -> float32x4_t { + static_assert_uimm_bits!(N, 1); unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 2) + assert_instr(dup, N = 1) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10408,25 +10364,24 @@ pub fn vdup_lane_u16(a: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_lane_p16(a: poly16x4_t) -> poly16x8_t { - static_assert_uimm_bits!(N, 2); +pub fn vdupq_lane_f32(a: float32x2_t) -> float32x4_t { + static_assert_uimm_bits!(N, 1); unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: float32x4_t = simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 2) + assert_instr(dup, N = 1) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10437,25 +10392,20 @@ pub fn vdupq_lane_p16(a: poly16x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_lane_s16(a: int16x4_t) -> int16x8_t { - static_assert_uimm_bits!(N, 2); - unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) - } +pub fn vdupq_lane_s32(a: int32x2_t) -> int32x4_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 2) + assert_instr(dup, N = 1) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10466,25 +10416,24 @@ pub fn vdupq_lane_s16(a: int16x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_lane_u16(a: uint16x4_t) -> uint16x8_t { - static_assert_uimm_bits!(N, 2); +pub fn vdupq_lane_s32(a: int32x2_t) -> int32x4_t { + static_assert_uimm_bits!(N, 1); unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: int32x4_t = simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 4) + assert_instr(dup, N = 1) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10495,25 +10444,20 @@ pub fn vdupq_lane_u16(a: uint16x4_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_lane_p8(a: poly8x8_t) -> poly8x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) - } +pub fn vdupq_lane_u32(a: uint32x2_t) -> uint32x4_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 4) + assert_instr(dup, N = 1) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10524,25 +10468,24 @@ pub fn vdup_lane_p8(a: poly8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_lane_s8(a: int8x8_t) -> int8x8_t { - static_assert_uimm_bits!(N, 3); +pub fn vdupq_lane_u32(a: uint32x2_t) -> uint32x4_t { + static_assert_uimm_bits!(N, 1); unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: uint32x4_t = simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 4) + assert_instr(dup, N = 2) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10553,25 +10496,20 @@ pub fn vdup_lane_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_lane_u8(a: uint8x8_t) -> uint8x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) - } +pub fn vdup_lane_p16(a: poly16x4_t) -> poly16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 4) + assert_instr(dup, N = 2) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10582,28 +10520,24 @@ pub fn vdup_lane_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_lane_p8(a: poly8x8_t) -> poly8x16_t { - static_assert_uimm_bits!(N, 3); +pub fn vdup_lane_p16(a: poly16x4_t) -> poly16x4_t { + static_assert_uimm_bits!(N, 2); unsafe { - simd_shuffle!( - a, - a, - [ - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 - ] - ) + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, a, [N as u32; 4]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 4) + assert_instr(dup, N = 2) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10614,28 +10548,20 @@ pub fn vdupq_lane_p8(a: poly8x8_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_lane_s8(a: int8x8_t) -> int8x16_t { - static_assert_uimm_bits!(N, 3); - unsafe { - simd_shuffle!( - a, - a, - [ - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 - ] - ) - } +pub fn vdup_lane_s16(a: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 4) + assert_instr(dup, N = 2) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10646,28 +10572,24 @@ pub fn vdupq_lane_s8(a: int8x8_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_lane_u8(a: uint8x8_t) -> uint8x16_t { - static_assert_uimm_bits!(N, 3); +pub fn vdup_lane_s16(a: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(N, 2); unsafe { - simd_shuffle!( - a, - a, - [ - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 - ] - ) + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, a, [N as u32; 4]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, N = 0) + assert_instr(dup, N = 2) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10678,19 +10600,20 @@ pub fn vdupq_lane_u8(a: uint8x8_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_lane_s64(a: int64x1_t) -> int64x1_t { - static_assert!(N == 0); - a +pub fn vdup_lane_u16(a: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, N = 0) + assert_instr(dup, N = 2) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10701,72 +10624,73 @@ pub fn vdup_lane_s64(a: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_lane_u64(a: uint64x1_t) -> uint64x1_t { - static_assert!(N == 0); - a +pub fn vdup_lane_u16(a: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, a, [N as u32; 4]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 4) + assert_instr(dup, N = 2) )] #[rustc_legacy_const_generics(1)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vdup_laneq_f16(a: float16x8_t) -> float16x4_t { - static_assert_uimm_bits!(N, 3); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } +pub fn vdupq_lane_p16(a: poly16x4_t) -> poly16x8_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 4) + assert_instr(dup, N = 2) )] #[rustc_legacy_const_generics(1)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vdupq_laneq_f16(a: float16x8_t) -> float16x8_t { - static_assert_uimm_bits!(N, 3); +pub fn vdupq_lane_p16(a: poly16x4_t) -> poly16x8_t { + static_assert_uimm_bits!(N, 2); unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 2) @@ -10780,16 +10704,17 @@ pub fn vdupq_laneq_f16(a: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_laneq_f32(a: float32x4_t) -> float32x2_t { +pub fn vdupq_lane_s16(a: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 2) @@ -10803,16 +10728,21 @@ pub fn vdup_laneq_f32(a: float32x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_laneq_s32(a: int32x4_t) -> int32x2_t { +pub fn vdupq_lane_s16(a: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 2) @@ -10826,16 +10756,17 @@ pub fn vdup_laneq_s32(a: int32x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_laneq_u32(a: uint32x4_t) -> uint32x2_t { +pub fn vdupq_lane_u16(a: uint16x4_t) -> uint16x8_t { static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 2) @@ -10849,19 +10780,24 @@ pub fn vdup_laneq_u32(a: uint32x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_laneq_f32(a: float32x4_t) -> float32x4_t { +pub fn vdupq_lane_u16(a: uint16x4_t) -> uint16x8_t { static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 2) + assert_instr(dup, N = 4) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10872,19 +10808,20 @@ pub fn vdupq_laneq_f32(a: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_laneq_s32(a: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } +pub fn vdup_lane_p8(a: poly8x8_t) -> poly8x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 2) + assert_instr(dup, N = 4) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10895,16 +10832,21 @@ pub fn vdupq_laneq_s32(a: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_laneq_u32(a: uint32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } +pub fn vdup_lane_p8(a: poly8x8_t) -> poly8x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4) @@ -10918,16 +10860,17 @@ pub fn vdupq_laneq_u32(a: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_laneq_p16(a: poly16x8_t) -> poly16x4_t { +pub fn vdup_lane_s8(a: int8x8_t) -> int8x8_t { static_assert_uimm_bits!(N, 3); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4) @@ -10941,16 +10884,21 @@ pub fn vdup_laneq_p16(a: poly16x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_laneq_s16(a: int16x8_t) -> int16x4_t { +pub fn vdup_lane_s8(a: int8x8_t) -> int8x8_t { static_assert_uimm_bits!(N, 3); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4) @@ -10964,16 +10912,17 @@ pub fn vdup_laneq_s16(a: int16x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_laneq_u16(a: uint16x8_t) -> uint16x4_t { +pub fn vdup_lane_u8(a: uint8x8_t) -> uint8x8_t { static_assert_uimm_bits!(N, 3); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4) @@ -10987,22 +10936,21 @@ pub fn vdup_laneq_u16(a: uint16x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_laneq_p16(a: poly16x8_t) -> poly16x8_t { +pub fn vdup_lane_u8(a: uint8x8_t) -> uint8x8_t { static_assert_uimm_bits!(N, 3); unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4) @@ -11016,22 +10964,17 @@ pub fn vdupq_laneq_p16(a: poly16x8_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_laneq_s16(a: int16x8_t) -> int16x8_t { +pub fn vdupq_lane_p8(a: poly8x8_t) -> poly8x16_t { static_assert_uimm_bits!(N, 3); - unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) - } + unsafe { simd_shuffle!(a, a, [N as u32; 16]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4) @@ -11045,25 +10988,28 @@ pub fn vdupq_laneq_s16(a: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_laneq_u16(a: uint16x8_t) -> uint16x8_t { +pub fn vdupq_lane_p8(a: poly8x8_t) -> poly8x16_t { static_assert_uimm_bits!(N, 3); unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = simd_shuffle!(a, a, [N as u32; 16]); simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 8) + assert_instr(dup, N = 4) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -11074,25 +11020,20 @@ pub fn vdupq_laneq_u16(a: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_laneq_p8(a: poly8x16_t) -> poly8x8_t { - static_assert_uimm_bits!(N, 4); - unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) - } +pub fn vdupq_lane_s8(a: int8x8_t) -> int8x16_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shuffle!(a, a, [N as u32; 16]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 8) + assert_instr(dup, N = 4) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -11103,25 +11044,28 @@ pub fn vdup_laneq_p8(a: poly8x16_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_laneq_s8(a: int8x16_t) -> int8x8_t { - static_assert_uimm_bits!(N, 4); +pub fn vdupq_lane_s8(a: int8x8_t) -> int8x16_t { + static_assert_uimm_bits!(N, 3); unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = simd_shuffle!(a, a, [N as u32; 16]); simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 8) + assert_instr(dup, N = 4) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -11132,25 +11076,20 @@ pub fn vdup_laneq_s8(a: int8x16_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_laneq_u8(a: uint8x16_t) -> uint8x8_t { - static_assert_uimm_bits!(N, 4); - unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) - } +pub fn vdupq_lane_u8(a: uint8x8_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shuffle!(a, a, [N as u32; 16]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 8) + assert_instr(dup, N = 4) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -11161,28 +11100,27 @@ pub fn vdup_laneq_u8(a: uint8x16_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_laneq_p8(a: poly8x16_t) -> poly8x16_t { - static_assert_uimm_bits!(N, 4); +pub fn vdupq_lane_u8(a: uint8x8_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 3); unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = simd_shuffle!(a, a, [N as u32; 16]); simd_shuffle!( - a, - a, - [ - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 - ] + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 8) + assert_instr(nop, N = 0) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -11193,28 +11131,19 @@ pub fn vdupq_laneq_p8(a: poly8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_laneq_s8(a: int8x16_t) -> int8x16_t { - static_assert_uimm_bits!(N, 4); - unsafe { - simd_shuffle!( - a, - a, - [ - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 - ] - ) - } +pub fn vdup_lane_s64(a: int64x1_t) -> int64x1_t { + static_assert!(N == 0); + a } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 8) + assert_instr(nop, N = 0) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -11225,107 +11154,134 @@ pub fn vdupq_laneq_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_laneq_u8(a: uint8x16_t) -> uint8x16_t { - static_assert_uimm_bits!(N, 4); - unsafe { - simd_shuffle!( - a, - a, - [ - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 - ] - ) - } +pub fn vdup_lane_u64(a: uint64x1_t) -> uint64x1_t { + static_assert!(N == 0); + a } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, N = 1) + assert_instr(dup, N = 4) )] #[rustc_legacy_const_generics(1)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_laneq_s64(a: int64x2_t) -> int64x1_t { - static_assert_uimm_bits!(N, 1); - unsafe { transmute::(simd_extract!(a, N as u32)) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vdup_laneq_f16(a: float16x8_t) -> float16x4_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, N = 1) + assert_instr(dup, N = 4) )] #[rustc_legacy_const_generics(1)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_laneq_u64(a: uint64x2_t) -> uint64x1_t { - static_assert_uimm_bits!(N, 1); - unsafe { transmute::(simd_extract!(a, N as u32)) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vdup_laneq_f16(a: float16x8_t) -> float16x4_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x4_t = simd_shuffle!(a, a, [N as u32; 4]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Create a new vector with all lanes set to a value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f16)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "stdarch_neon_fp16", since = "1.94.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] #[cfg(not(target_arch = "arm64ec"))] -pub fn vdup_n_f16(a: f16) -> float16x4_t { - float16x4_t::splat(a) +pub fn vdupq_laneq_f16(a: float16x8_t) -> float16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } -#[doc = "Create a new vector with all lanes set to a value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f16)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "stdarch_neon_fp16", since = "1.94.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] #[cfg(not(target_arch = "arm64ec"))] -pub fn vdupq_n_f16(a: f16) -> float16x8_t { - float16x8_t::splat(a) +pub fn vdupq_laneq_f16(a: float16x8_t) -> float16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11334,19 +11290,22 @@ pub fn vdupq_n_f16(a: f16) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_n_f32(value: f32) -> float32x2_t { - float32x2_t::splat(value) +pub fn vdup_laneq_f32(a: float32x4_t) -> float32x2_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p16)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11355,19 +11314,26 @@ pub fn vdup_n_f32(value: f32) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_n_p16(value: p16) -> poly16x4_t { - poly16x4_t::splat(value) +pub fn vdup_laneq_f32(a: float32x4_t) -> float32x2_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11376,19 +11342,22 @@ pub fn vdup_n_p16(value: p16) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_n_p8(value: p8) -> poly8x8_t { - poly8x8_t::splat(value) +pub fn vdup_laneq_s32(a: int32x4_t) -> int32x2_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s16)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11397,19 +11366,26 @@ pub fn vdup_n_p8(value: p8) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_n_s16(value: i16) -> int16x4_t { - int16x4_t::splat(value) +pub fn vdup_laneq_s32(a: int32x4_t) -> int32x2_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s32)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11418,19 +11394,22 @@ pub fn vdup_n_s16(value: i16) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_n_s32(value: i32) -> int32x2_t { - int32x2_t::splat(value) +pub fn vdup_laneq_u32(a: uint32x4_t) -> uint32x2_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s64)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmov) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11439,19 +11418,26 @@ pub fn vdup_n_s32(value: i32) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_n_s64(value: i64) -> int64x1_t { - int64x1_t::splat(value) +pub fn vdup_laneq_u32(a: uint32x4_t) -> uint32x2_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11460,19 +11446,22 @@ pub fn vdup_n_s64(value: i64) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_n_s8(value: i8) -> int8x8_t { - int8x8_t::splat(value) +pub fn vdupq_laneq_f32(a: float32x4_t) -> float32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u16)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11481,19 +11470,26 @@ pub fn vdup_n_s8(value: i8) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_n_u16(value: u16) -> uint16x4_t { - uint16x4_t::splat(value) +pub fn vdupq_laneq_f32(a: float32x4_t) -> float32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: float32x4_t = simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u32)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11502,19 +11498,22 @@ pub fn vdup_n_u16(value: u16) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_n_u32(value: u32) -> uint32x2_t { - uint32x2_t::splat(value) +pub fn vdupq_laneq_s32(a: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u64)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmov) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11523,19 +11522,26 @@ pub fn vdup_n_u32(value: u32) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_n_u64(value: u64) -> uint64x1_t { - uint64x1_t::splat(value) +pub fn vdupq_laneq_s32(a: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: int32x4_t = simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11544,19 +11550,22 @@ pub fn vdup_n_u64(value: u64) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_n_u8(value: u8) -> uint8x8_t { - uint8x8_t::splat(value) +pub fn vdupq_laneq_u32(a: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11565,19 +11574,26 @@ pub fn vdup_n_u8(value: u8) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_n_f32(value: f32) -> float32x4_t { - float32x4_t::splat(value) +pub fn vdupq_laneq_u32(a: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: uint32x4_t = simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p16)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11586,19 +11602,22 @@ pub fn vdupq_n_f32(value: f32) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_n_p16(value: p16) -> poly16x8_t { - poly16x8_t::splat(value) +pub fn vdup_laneq_p16(a: poly16x8_t) -> poly16x4_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11607,19 +11626,26 @@ pub fn vdupq_n_p16(value: p16) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_n_p8(value: p8) -> poly8x16_t { - poly8x16_t::splat(value) +pub fn vdup_laneq_p16(a: poly16x8_t) -> poly16x4_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, a, [N as u32; 4]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s16)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11628,19 +11654,22 @@ pub fn vdupq_n_p8(value: p8) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_n_s16(value: i16) -> int16x8_t { - int16x8_t::splat(value) +pub fn vdup_laneq_s16(a: int16x8_t) -> int16x4_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s32)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11649,19 +11678,26 @@ pub fn vdupq_n_s16(value: i16) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_n_s32(value: i32) -> int32x4_t { - int32x4_t::splat(value) +pub fn vdup_laneq_s16(a: int16x8_t) -> int16x4_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, a, [N as u32; 4]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s64)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11670,19 +11706,22 @@ pub fn vdupq_n_s32(value: i32) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_n_s64(value: i64) -> int64x2_t { - int64x2_t::splat(value) +pub fn vdup_laneq_u16(a: uint16x8_t) -> uint16x4_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11691,19 +11730,26 @@ pub fn vdupq_n_s64(value: i64) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_n_s8(value: i8) -> int8x16_t { - int8x16_t::splat(value) -} -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u16)"] -#[inline(always)] +pub fn vdup_laneq_u16(a: uint16x8_t) -> uint16x4_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, a, [N as u32; 4]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11712,19 +11758,22 @@ pub fn vdupq_n_s8(value: i8) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_n_u16(value: u16) -> uint16x8_t { - uint16x8_t::splat(value) +pub fn vdupq_laneq_p16(a: poly16x8_t) -> poly16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u32)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11733,19 +11782,26 @@ pub fn vdupq_n_u16(value: u16) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_n_u32(value: u32) -> uint32x4_t { - uint32x4_t::splat(value) +pub fn vdupq_laneq_p16(a: poly16x8_t) -> poly16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u64)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11754,19 +11810,22 @@ pub fn vdupq_n_u32(value: u32) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_n_u64(value: u64) -> uint64x2_t { - uint64x2_t::splat(value) +pub fn vdupq_laneq_s16(a: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11775,19 +11834,26 @@ pub fn vdupq_n_u64(value: u64) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_n_u8(value: u8) -> uint8x16_t { - uint8x16_t::splat(value) +pub fn vdupq_laneq_s16(a: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32_vfp4)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11796,19 +11862,22 @@ pub fn vdupq_n_u8(value: u8) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -fn vdup_n_f32_vfp4(value: f32) -> float32x2_t { - float32x2_t::splat(value) +pub fn vdupq_laneq_u16(a: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32_vfp4)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11817,18 +11886,24 @@ fn vdup_n_f32_vfp4(value: f32) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -fn vdupq_n_f32_vfp4(value: f32) -> float32x4_t { - float32x4_t::splat(value) +pub fn vdupq_laneq_u16(a: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 0) + assert_instr(dup, N = 8) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -11839,19 +11914,20 @@ fn vdupq_n_f32_vfp4(value: f32) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_lane_s64(a: int64x1_t) -> int64x2_t { - static_assert!(N == 0); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } +pub fn vdup_laneq_p8(a: poly8x16_t) -> poly8x8_t { + static_assert_uimm_bits!(N, 4); + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 0) + assert_instr(dup, N = 8) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -11862,19 +11938,25 @@ pub fn vdupq_lane_s64(a: int64x1_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_lane_u64(a: uint64x1_t) -> uint64x2_t { - static_assert!(N == 0); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } +pub fn vdup_laneq_p8(a: poly8x16_t) -> poly8x8_t { + static_assert_uimm_bits!(N, 4); + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 1) + assert_instr(dup, N = 8) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -11885,19 +11967,20 @@ pub fn vdupq_lane_u64(a: uint64x1_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_laneq_s64(a: int64x2_t) -> int64x2_t { - static_assert_uimm_bits!(N, 1); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } +pub fn vdup_laneq_s8(a: int8x16_t) -> int8x8_t { + static_assert_uimm_bits!(N, 4); + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 1) + assert_instr(dup, N = 8) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -11908,20 +11991,27 @@ pub fn vdupq_laneq_s64(a: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_laneq_u64(a: uint64x2_t) -> uint64x2_t { - static_assert_uimm_bits!(N, 1); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } +pub fn vdup_laneq_s8(a: int8x16_t) -> int8x8_t { + static_assert_uimm_bits!(N, 4); + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup, N = 8) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11930,19 +12020,22 @@ pub fn vdupq_laneq_u64(a: uint64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veor_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe { simd_xor(a, b) } +pub fn vdup_laneq_u8(a: uint8x16_t) -> uint8x8_t { + static_assert_uimm_bits!(N, 4); + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup, N = 8) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11951,19 +12044,27 @@ pub fn veor_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veorq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe { simd_xor(a, b) } +pub fn vdup_laneq_u8(a: uint8x16_t) -> uint8x8_t { + static_assert_uimm_bits!(N, 4); + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s16)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup, N = 8) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11972,19 +12073,22 @@ pub fn veorq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veor_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe { simd_xor(a, b) } +pub fn vdupq_laneq_p8(a: poly8x16_t) -> poly8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { simd_shuffle!(a, a, [N as u32; 16]) } } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s16)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup, N = 8) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11993,19 +12097,31 @@ pub fn veor_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veorq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe { simd_xor(a, b) } +pub fn vdupq_laneq_p8(a: poly8x16_t) -> poly8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = simd_shuffle!(a, a, [N as u32; 16]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s32)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup, N = 8) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12014,19 +12130,22 @@ pub fn veorq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veor_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe { simd_xor(a, b) } +pub fn vdupq_laneq_s8(a: int8x16_t) -> int8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { simd_shuffle!(a, a, [N as u32; 16]) } } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s32)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup, N = 8) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12035,19 +12154,31 @@ pub fn veor_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veorq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe { simd_xor(a, b) } +pub fn vdupq_laneq_s8(a: int8x16_t) -> int8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = simd_shuffle!(a, a, [N as u32; 16]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s64)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup, N = 8) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12056,19 +12187,22 @@ pub fn veorq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veor_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - unsafe { simd_xor(a, b) } +pub fn vdupq_laneq_u8(a: uint8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { simd_shuffle!(a, a, [N as u32; 16]) } } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s64)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup, N = 8) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12077,19 +12211,30 @@ pub fn veor_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veorq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - unsafe { simd_xor(a, b) } +pub fn vdupq_laneq_u8(a: uint8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = simd_shuffle!(a, a, [N as u32; 16]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(nop, N = 1) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12098,19 +12243,21 @@ pub fn veorq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veor_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - unsafe { simd_xor(a, b) } +pub fn vdup_laneq_s64(a: int64x2_t) -> int64x1_t { + static_assert_uimm_bits!(N, 1); + unsafe { transmute(vgetq_lane_s64::(a)) } } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(nop, N = 1) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12119,18 +12266,51 @@ pub fn veor_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veorq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - unsafe { simd_xor(a, b) } +pub fn vdup_laneq_u64(a: uint64x2_t) -> uint64x1_t { + static_assert_uimm_bits!(N, 1); + unsafe { transmute(vgetq_lane_u64::(a)) } } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u16)"] -#[inline(always)] +#[doc = "Create a new vector with all lanes set to a value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup) +)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vdup_n_f16(a: f16) -> float16x4_t { + float16x4_t::splat(a) +} +#[doc = "Create a new vector with all lanes set to a value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup) +)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vdupq_n_f16(a: f16) -> float16x8_t { + float16x8_t::splat(a) +} +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -12140,18 +12320,18 @@ pub fn veorq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veor_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - unsafe { simd_xor(a, b) } +pub fn vdup_n_f32(value: f32) -> float32x2_t { + float32x2_t::splat(value) } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -12161,18 +12341,18 @@ pub fn veor_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veorq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - unsafe { simd_xor(a, b) } +pub fn vdup_n_p16(value: p16) -> poly16x4_t { + poly16x4_t::splat(value) } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -12182,18 +12362,18 @@ pub fn veorq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veor_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - unsafe { simd_xor(a, b) } +pub fn vdup_n_p8(value: p8) -> poly8x8_t { + poly8x8_t::splat(value) } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -12203,18 +12383,18 @@ pub fn veor_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veorq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - unsafe { simd_xor(a, b) } +pub fn vdup_n_s16(value: i16) -> int16x4_t { + int16x4_t::splat(value) } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u64)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -12224,18 +12404,18 @@ pub fn veorq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veor_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - unsafe { simd_xor(a, b) } +pub fn vdup_n_s32(value: i32) -> int32x2_t { + int32x2_t::splat(value) } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u64)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(fmov) )] #[cfg_attr( not(target_arch = "arm"), @@ -12245,52 +12425,40 @@ pub fn veor_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - unsafe { simd_xor(a, b) } +pub fn vdup_n_s64(value: i64) -> int64x1_t { + int64x1_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s8)"] +#[inline] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 3) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vext_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), - } - } +pub fn vdup_n_s8(value: i8) -> int8x8_t { + int8x8_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 1) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12299,27 +12467,19 @@ pub fn vext_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vext_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - static_assert_uimm_bits!(N, 1); - unsafe { - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), - } - } +pub fn vdup_n_u16(value: u16) -> uint16x4_t { + uint16x4_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 1) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12328,27 +12488,19 @@ pub fn vext_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vext_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(N, 1); - unsafe { - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), - } - } +pub fn vdup_n_u32(value: u32) -> uint32x2_t { + uint32x2_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 1) + assert_instr(fmov) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12357,29 +12509,19 @@ pub fn vext_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vext_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(N, 1); - unsafe { - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), - } - } +pub fn vdup_n_u64(value: u64) -> uint64x1_t { + uint64x1_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, N = 0) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12388,23 +12530,19 @@ pub fn vext_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vext_s64(a: int64x1_t, _b: int64x1_t) -> int64x1_t { - static_assert!(N == 0); - a +pub fn vdup_n_u8(value: u8) -> uint8x8_t { + uint8x8_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, N = 0) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12413,21 +12551,19 @@ pub unsafe fn vext_s64(a: int64x1_t, _b: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vext_u64(a: uint64x1_t, _b: uint64x1_t) -> uint64x1_t { - static_assert!(N == 0); - a +pub fn vdupq_n_f32(value: f32) -> float32x4_t { + float32x4_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s8)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 7) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12436,33 +12572,19 @@ pub unsafe fn vext_u64(a: uint64x1_t, _b: uint64x1_t) -> uint64x1_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vext_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_n_p16(value: p16) -> poly16x8_t { + poly16x8_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 7) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12471,33 +12593,19 @@ pub fn vext_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vextq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_n_p8(value: p8) -> poly8x16_t { + poly8x16_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u8)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 7) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12506,33 +12614,19 @@ pub fn vextq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vext_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_n_s16(value: i16) -> int16x8_t { + int16x8_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 7) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12541,33 +12635,19 @@ pub fn vext_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vextq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_n_s32(value: i32) -> int32x4_t { + int32x4_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p8)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 7) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12576,33 +12656,19 @@ pub fn vextq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vext_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_n_s64(value: i64) -> int64x2_t { + int64x2_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 7) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12611,69 +12677,40 @@ pub fn vext_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vextq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_n_s8(value: i8) -> int8x16_t { + int8x16_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u16)"] +#[inline] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 7) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vextq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_n_u16(value: u16) -> uint16x8_t { + uint16x8_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 3) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12682,29 +12719,19 @@ pub fn vextq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vextq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_n_u32(value: u32) -> uint32x4_t { + uint32x4_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 3) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12713,29 +12740,19 @@ pub fn vextq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vext_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_n_u64(value: u64) -> uint64x2_t { + uint64x2_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 3) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12744,29 +12761,19 @@ pub fn vext_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vextq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_n_u8(value: u8) -> uint8x16_t { + uint8x16_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32_vfp4)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 3) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12775,29 +12782,19 @@ pub fn vextq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vext_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), - } - } +fn vdup_n_f32_vfp4(value: f32) -> float32x2_t { + float32x2_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32_vfp4)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 3) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12806,29 +12803,21 @@ pub fn vext_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vextq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), - } - } +fn vdupq_n_f32_vfp4(value: f32) -> float32x4_t { + float32x4_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p16)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 3) + assert_instr(dup, N = 0) )] -#[rustc_legacy_const_generics(2)] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12837,29 +12826,22 @@ pub fn vextq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vext_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_lane_s64(a: int64x1_t) -> int64x2_t { + static_assert!(N == 0); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s64)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 1) + assert_instr(dup, N = 0) )] -#[rustc_legacy_const_generics(2)] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12868,27 +12850,25 @@ pub fn vext_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vextq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - static_assert_uimm_bits!(N, 1); +pub fn vdupq_lane_s64(a: int64x1_t) -> int64x2_t { + static_assert!(N == 0); unsafe { - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), - } + let ret_val: int64x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u64)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 1) + assert_instr(dup, N = 0) )] -#[rustc_legacy_const_generics(2)] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12897,27 +12877,22 @@ pub fn vextq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vextq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - static_assert_uimm_bits!(N, 1); - unsafe { - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_lane_u64(a: uint64x1_t) -> uint64x2_t { + static_assert!(N == 0); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 15) + assert_instr(dup, N = 0) )] -#[rustc_legacy_const_generics(2)] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12926,101 +12901,25 @@ pub fn vextq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vextq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - static_assert_uimm_bits!(N, 4); +pub fn vdupq_lane_u64(a: uint64x1_t) -> uint64x2_t { + static_assert!(N == 0); unsafe { - match N & 0b1111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 1 => simd_shuffle!( - a, - b, - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16] - ), - 2 => simd_shuffle!( - a, - b, - [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17] - ), - 3 => simd_shuffle!( - a, - b, - [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18] - ), - 4 => simd_shuffle!( - a, - b, - [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19] - ), - 5 => simd_shuffle!( - a, - b, - [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20] - ), - 6 => simd_shuffle!( - a, - b, - [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21] - ), - 7 => simd_shuffle!( - a, - b, - [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22] - ), - 8 => simd_shuffle!( - a, - b, - [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23] - ), - 9 => simd_shuffle!( - a, - b, - [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24] - ), - 10 => simd_shuffle!( - a, - b, - [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25] - ), - 11 => simd_shuffle!( - a, - b, - [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26] - ), - 12 => simd_shuffle!( - a, - b, - [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27] - ), - 13 => simd_shuffle!( - a, - b, - [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28] - ), - 14 => simd_shuffle!( - a, - b, - [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29] - ), - 15 => simd_shuffle!( - a, - b, - [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30] - ), - _ => unreachable_unchecked(), - } + let ret_val: uint64x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 15) + assert_instr(dup, N = 1) )] -#[rustc_legacy_const_generics(2)] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13029,101 +12928,22 @@ pub fn vextq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vextq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - static_assert_uimm_bits!(N, 4); - unsafe { - match N & 0b1111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 1 => simd_shuffle!( - a, - b, - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16] - ), - 2 => simd_shuffle!( - a, - b, - [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17] - ), - 3 => simd_shuffle!( - a, - b, - [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18] - ), - 4 => simd_shuffle!( - a, - b, - [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19] - ), - 5 => simd_shuffle!( - a, - b, - [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20] - ), - 6 => simd_shuffle!( - a, - b, - [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21] - ), - 7 => simd_shuffle!( - a, - b, - [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22] - ), - 8 => simd_shuffle!( - a, - b, - [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23] - ), - 9 => simd_shuffle!( - a, - b, - [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24] - ), - 10 => simd_shuffle!( - a, - b, - [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25] - ), - 11 => simd_shuffle!( - a, - b, - [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26] - ), - 12 => simd_shuffle!( - a, - b, - [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27] - ), - 13 => simd_shuffle!( - a, - b, - [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28] - ), - 14 => simd_shuffle!( - a, - b, - [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29] - ), - 15 => simd_shuffle!( - a, - b, - [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30] - ), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_laneq_s64(a: int64x2_t) -> int64x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 15) + assert_instr(dup, N = 1) )] -#[rustc_legacy_const_generics(2)] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13132,143 +12952,75 @@ pub fn vextq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vextq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { - static_assert_uimm_bits!(N, 4); +pub fn vdupq_laneq_s64(a: int64x2_t) -> int64x2_t { + static_assert_uimm_bits!(N, 1); unsafe { - match N & 0b1111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 1 => simd_shuffle!( - a, - b, - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16] - ), - 2 => simd_shuffle!( - a, - b, - [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17] - ), - 3 => simd_shuffle!( - a, - b, - [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18] - ), - 4 => simd_shuffle!( - a, - b, - [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19] - ), - 5 => simd_shuffle!( - a, - b, - [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20] - ), - 6 => simd_shuffle!( - a, - b, - [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21] - ), - 7 => simd_shuffle!( - a, - b, - [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22] - ), - 8 => simd_shuffle!( - a, - b, - [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23] - ), - 9 => simd_shuffle!( - a, - b, - [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24] - ), - 10 => simd_shuffle!( - a, - b, - [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25] - ), - 11 => simd_shuffle!( - a, - b, - [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26] - ), - 12 => simd_shuffle!( - a, - b, - [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27] - ), - 13 => simd_shuffle!( - a, - b, - [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28] - ), - 14 => simd_shuffle!( - a, - b, - [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29] - ), - 15 => simd_shuffle!( - a, - b, - [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30] - ), - _ => unreachable_unchecked(), - } + let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: int64x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Floating-point fused Multiply-Add to accumulator (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u64)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmla) + assert_instr(dup, N = 1) )] -#[target_feature(enable = "neon,fp16")] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { - unsafe { simd_fma(b, c, a) } +pub fn vdupq_laneq_u64(a: uint64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } -#[doc = "Floating-point fused Multiply-Add to accumulator (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmla) + assert_instr(dup, N = 1) )] -#[target_feature(enable = "neon,fp16")] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vfmaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { - unsafe { simd_fma(b, c, a) } +pub fn vdupq_laneq_u64(a: uint64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: uint64x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f32)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s8)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmla) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13278,18 +13030,18 @@ pub fn vfmaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - unsafe { simd_fma(b, c, a) } +pub fn veor_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { simd_xor(a, b) } } -#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f32)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s8)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmla) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13299,18 +13051,18 @@ pub fn vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - unsafe { simd_fma(b, c, a) } +pub fn veorq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { simd_xor(a, b) } } -#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f32)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s16)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmla) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13320,18 +13072,18 @@ pub fn vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vfma_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { - vfma_f32(a, b, vdup_n_f32_vfp4(c)) +pub fn veor_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { simd_xor(a, b) } } -#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f32)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s16)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmla) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13341,70 +13093,60 @@ pub fn vfma_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vfmaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { - vfmaq_f32(a, b, vdupq_n_f32_vfp4(c)) +pub fn veorq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { simd_xor(a, b) } } -#[doc = "Floating-point fused multiply-subtract from accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmls) + assert_instr(eor) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vfms_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { - unsafe { - let b: float16x4_t = simd_neg(b); - vfma_f16(a, b, c) - } +pub fn veor_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { simd_xor(a, b) } } -#[doc = "Floating-point fused multiply-subtract from accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmls) + assert_instr(eor) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vfmsq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { - unsafe { - let b: float16x8_t = simd_neg(b); - vfmaq_f16(a, b, c) - } +pub fn veorq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { simd_xor(a, b) } } -#[doc = "Floating-point fused multiply-subtract from accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f32)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s64)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmls) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13414,21 +13156,18 @@ pub fn vfmsq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vfms_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - unsafe { - let b: float32x2_t = simd_neg(b); - vfma_f32(a, b, c) - } +pub fn veor_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + unsafe { simd_xor(a, b) } } -#[doc = "Floating-point fused multiply-subtract from accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f32)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s64)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmls) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13438,21 +13177,18 @@ pub fn vfms_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vfmsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - unsafe { - let b: float32x4_t = simd_neg(b); - vfmaq_f32(a, b, c) - } +pub fn veorq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { simd_xor(a, b) } } -#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f32)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u8)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmls) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13462,18 +13198,18 @@ pub fn vfmsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vfms_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { - vfms_f32(a, b, vdup_n_f32_vfp4(c)) +pub fn veor_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_xor(a, b) } } -#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f32)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u8)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmls) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13483,56 +13219,60 @@ pub fn vfms_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vfmsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { - vfmsq_f32(a, b, vdupq_n_f32_vfp4(c)) +pub fn veorq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { simd_xor(a, b) } } -#[doc = "Duplicate vector element to vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f16)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(eor) +)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(test, assert_instr(nop))] -pub fn vget_high_f16(a: float16x8_t) -> float16x4_t { - unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) } +pub fn veor_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_xor(a, b) } } -#[doc = "Duplicate vector element to vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f16)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(eor) +)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(test, assert_instr(nop))] -pub fn vget_low_f16(a: float16x8_t) -> float16x4_t { - unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) } +pub fn veorq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_xor(a, b) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f32)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13542,18 +13282,18 @@ pub fn vget_low_f16(a: float16x8_t) -> float16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_high_f32(a: float32x4_t) -> float32x2_t { - unsafe { simd_shuffle!(a, a, [2, 3]) } +pub fn veor_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_xor(a, b) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p16)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13563,18 +13303,18 @@ pub fn vget_high_f32(a: float32x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_high_p16(a: poly16x8_t) -> poly16x4_t { - unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) } +pub fn veorq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_xor(a, b) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p8)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13584,18 +13324,18 @@ pub fn vget_high_p16(a: poly16x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_high_p8(a: poly8x16_t) -> poly8x8_t { - unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) } +pub fn veor_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + unsafe { simd_xor(a, b) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s16)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13605,61 +13345,77 @@ pub fn vget_high_p8(a: poly8x16_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_high_s16(a: int16x8_t) -> int16x4_t { - unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) } +pub fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { simd_xor(a, b) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext) + assert_instr(ext, N = 3) )] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_high_s32(a: int32x4_t) -> int32x2_t { - unsafe { simd_shuffle!(a, a, [2, 3]) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vext_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext) + assert_instr(ext, N = 3) )] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_high_s8(a: int8x16_t) -> int8x8_t { - unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vext_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = + simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext) + assert_instr(ext, N = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13668,19 +13424,22 @@ pub fn vget_high_s8(a: int8x16_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_high_u16(a: uint16x8_t) -> uint16x4_t { - unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) } +pub fn vext_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u32)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext) + assert_instr(ext, N = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13689,19 +13448,27 @@ pub fn vget_high_u16(a: uint16x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_high_u32(a: uint32x4_t) -> uint32x2_t { - unsafe { simd_shuffle!(a, a, [2, 3]) } +pub fn vext_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, b, [N as u32, N as u32 + 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext) + assert_instr(ext, N = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13710,19 +13477,22 @@ pub fn vget_high_u32(a: uint32x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_high_u8(a: uint8x16_t) -> uint8x8_t { - unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) } +pub fn vext_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s64)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext) + assert_instr(ext, N = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13731,19 +13501,27 @@ pub fn vget_high_u8(a: uint8x16_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_high_s64(a: int64x2_t) -> int64x1_t { - unsafe { int64x1_t([simd_extract!(a, 1)]) } +pub fn vext_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, b, [N as u32, N as u32 + 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u64)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext) + assert_instr(ext, N = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13752,52 +13530,52 @@ pub fn vget_high_s64(a: int64x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_high_u64(a: uint64x2_t) -> uint64x1_t { - unsafe { uint64x1_t([simd_extract!(a, 1)]) } +pub fn vext_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1]) } } -#[doc = "Duplicate vector element to scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) + assert_instr(ext, N = 1) )] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vget_lane_f16(a: float16x4_t) -> f16 { - static_assert_uimm_bits!(LANE, 2); - unsafe { simd_extract!(a, LANE as u32) } +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vext_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, b, [N as u32, N as u32 + 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Duplicate vector element to scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) + assert_instr(nop, N = 0) )] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vgetq_lane_f16(a: float16x8_t) -> f16 { - static_assert_uimm_bits!(LANE, 3); - unsafe { simd_extract!(a, LANE as u32) } -} -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13806,17 +13584,23 @@ pub fn vgetq_lane_f16(a: float16x8_t) -> f16 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_f32(v: float32x2_t) -> f32 { - static_assert_uimm_bits!(IMM5, 1); - unsafe { simd_extract!(v, IMM5 as u32) } +pub unsafe fn vext_s64(a: int64x1_t, _b: int64x1_t) -> int64x1_t { + static_assert!(N == 0); + a } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, N = 0) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13825,17 +13609,22 @@ pub fn vget_lane_f32(v: float32x2_t) -> f32 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_p16(v: poly16x4_t) -> p16 { - static_assert_uimm_bits!(IMM5, 2); - unsafe { simd_extract!(v, IMM5 as u32) } +pub unsafe fn vext_u64(a: uint64x1_t, _b: uint64x1_t) -> uint64x1_t { + static_assert!(N == 0); + a } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13844,17 +13633,37 @@ pub fn vget_lane_p16(v: poly16x4_t) -> p16 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_p8(v: poly8x8_t) -> p8 { - static_assert_uimm_bits!(IMM5, 3); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vext_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13863,17 +13672,40 @@ pub fn vget_lane_p8(v: poly8x8_t) -> p8 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_s16(v: int16x4_t) -> i16 { - static_assert_uimm_bits!(IMM5, 2); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vext_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s32)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13882,17 +13714,37 @@ pub fn vget_lane_s16(v: int16x4_t) -> i16 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_s32(v: int32x2_t) -> i32 { - static_assert_uimm_bits!(IMM5, 1); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vextq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13901,17 +13753,40 @@ pub fn vget_lane_s32(v: int32x2_t) -> i32 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_s8(v: int8x8_t) -> i8 { - static_assert_uimm_bits!(IMM5, 3); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vextq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13920,17 +13795,37 @@ pub fn vget_lane_s8(v: int8x8_t) -> i8 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_u16(v: uint16x4_t) -> u16 { - static_assert_uimm_bits!(IMM5, 2); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vext_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u32)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13939,17 +13834,40 @@ pub fn vget_lane_u16(v: uint16x4_t) -> u16 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_u32(v: uint32x2_t) -> u32 { - static_assert_uimm_bits!(IMM5, 1); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vext_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13958,17 +13876,37 @@ pub fn vget_lane_u32(v: uint32x2_t) -> u32 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_u8(v: uint8x8_t) -> u8 { - static_assert_uimm_bits!(IMM5, 3); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vextq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f32)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13977,17 +13915,40 @@ pub fn vget_lane_u8(v: uint8x8_t) -> u8 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_f32(v: float32x4_t) -> f32 { - static_assert_uimm_bits!(IMM5, 2); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vextq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13996,17 +13957,37 @@ pub fn vgetq_lane_f32(v: float32x4_t) -> f32 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_p16(v: poly16x8_t) -> p16 { - static_assert_uimm_bits!(IMM5, 3); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vext_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p64)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14015,17 +13996,40 @@ pub fn vgetq_lane_p16(v: poly16x8_t) -> p16 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_p64(v: poly64x2_t) -> p64 { - static_assert_uimm_bits!(IMM5, 1); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vext_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14034,17 +14038,37 @@ pub fn vgetq_lane_p64(v: poly64x2_t) -> p64 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_p8(v: poly8x16_t) -> p8 { - static_assert_uimm_bits!(IMM5, 4); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vextq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14053,55 +14077,123 @@ pub fn vgetq_lane_p8(v: poly8x16_t) -> p8 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_s16(v: int16x8_t) -> i16 { - static_assert_uimm_bits!(IMM5, 3); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vextq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_s32(v: int32x4_t) -> i32 { - static_assert_uimm_bits!(IMM5, 2); - unsafe { simd_extract!(v, IMM5 as u32) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vextq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_s64(v: int64x2_t) -> i64 { - static_assert_uimm_bits!(IMM5, 1); - unsafe { simd_extract!(v, IMM5 as u32) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vextq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14110,17 +14202,22 @@ pub fn vgetq_lane_s64(v: int64x2_t) -> i64 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_s8(v: int8x16_t) -> i8 { - static_assert_uimm_bits!(IMM5, 4); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vextq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]) } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14129,17 +14226,28 @@ pub fn vgetq_lane_s8(v: int8x16_t) -> i8 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_u16(v: uint16x8_t) -> u16 { - static_assert_uimm_bits!(IMM5, 3); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vextq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = + simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u32)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14148,17 +14256,22 @@ pub fn vgetq_lane_u16(v: uint16x8_t) -> u16 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_u32(v: uint32x4_t) -> u32 { - static_assert_uimm_bits!(IMM5, 2); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vext_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]) } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u64)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14167,17 +14280,28 @@ pub fn vgetq_lane_u32(v: uint32x4_t) -> u32 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_u64(v: uint64x2_t) -> u64 { - static_assert_uimm_bits!(IMM5, 2); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vext_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x4_t = + simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14186,17 +14310,22 @@ pub fn vgetq_lane_u64(v: uint64x2_t) -> u64 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_u8(v: uint8x16_t) -> u8 { - static_assert_uimm_bits!(IMM5, 4); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vextq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]) } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p64)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14205,17 +14334,28 @@ pub fn vgetq_lane_u8(v: uint8x16_t) -> u8 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_p64(v: poly64x1_t) -> p64 { - static_assert!(IMM5 == 0); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vextq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int32x4_t = + simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s64)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14224,17 +14364,22 @@ pub fn vget_lane_p64(v: poly64x1_t) -> p64 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_s64(v: int64x1_t) -> i64 { - static_assert!(IMM5 == 0); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vext_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]) } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u64)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14243,16 +14388,28 @@ pub fn vget_lane_s64(v: int64x1_t) -> i64 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_u64(v: uint64x1_t) -> u64 { - static_assert!(IMM5 == 0); - unsafe { simd_extract!(v, 0) } +pub fn vext_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint16x4_t = + simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f32)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14261,15 +14418,22 @@ pub fn vget_lane_u64(v: uint64x1_t) -> u64 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_low_f32(a: float32x4_t) -> float32x2_t { - unsafe { simd_shuffle!(a, a, [0, 1]) } +pub fn vextq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14278,15 +14442,28 @@ pub fn vget_low_f32(a: float32x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_low_p16(a: poly16x8_t) -> poly16x4_t { - unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) } +pub fn vextq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = + simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14295,15 +14472,22 @@ pub fn vget_low_p16(a: poly16x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_low_p8(a: poly8x16_t) -> poly8x8_t { - unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) } +pub fn vext_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14312,15 +14496,28 @@ pub fn vget_low_p8(a: poly8x16_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_low_s16(a: int16x8_t) -> int16x4_t { - unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) } +pub fn vext_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: poly16x4_t = + simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s32)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 1) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14329,15 +14526,22 @@ pub fn vget_low_s16(a: int16x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_low_s32(a: int32x4_t) -> int32x2_t { - unsafe { simd_shuffle!(a, a, [0, 1]) } +pub fn vextq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 1) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14346,15 +14550,27 @@ pub fn vget_low_s32(a: int32x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_low_s8(a: int8x16_t) -> int8x8_t { - unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) } +pub fn vextq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { + let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int64x2_t = simd_shuffle!(a, b, [N as u32, N as u32 + 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 1) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14363,15 +14579,22 @@ pub fn vget_low_s8(a: int8x16_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_low_u16(a: uint16x8_t) -> uint16x4_t { - unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) } +pub fn vextq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u32)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 1) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14380,15 +14603,27 @@ pub fn vget_low_u16(a: uint16x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_low_u32(a: uint32x4_t) -> uint32x2_t { - unsafe { simd_shuffle!(a, a, [0, 1]) } +pub fn vextq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint64x2_t = simd_shuffle!(a, b, [N as u32, N as u32 + 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 15) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14397,15 +14632,45 @@ pub fn vget_low_u32(a: uint32x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_low_u8(a: uint8x16_t) -> uint8x8_t { - unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) } +pub fn vextq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { + simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7, + N as u32 + 8, + N as u32 + 9, + N as u32 + 10, + N as u32 + 11, + N as u32 + 12, + N as u32 + 13, + N as u32 + 14, + N as u32 + 15 + ] + ) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s64)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 15) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14414,15 +14679,54 @@ pub fn vget_low_u8(a: uint8x16_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_low_s64(a: int64x2_t) -> int64x1_t { - unsafe { int64x1_t([simd_extract!(a, 0)]) } +pub fn vextq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7, + N as u32 + 8, + N as u32 + 9, + N as u32 + 10, + N as u32 + 11, + N as u32 + 12, + N as u32 + 13, + N as u32 + 14, + N as u32 + 15 + ] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u64)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 15) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14431,19 +14735,45 @@ pub fn vget_low_s64(a: int64x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_low_u64(a: uint64x2_t) -> uint64x1_t { - unsafe { uint64x1_t([simd_extract!(a, 0)]) } +pub fn vextq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { + simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7, + N as u32 + 8, + N as u32 + 9, + N as u32 + 10, + N as u32 + 11, + N as u32 + 12, + N as u32 + 13, + N as u32 + 14, + N as u32 + 15 + ] + ) + } } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shadd) + assert_instr(ext, N = 15) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14452,27 +14782,54 @@ pub fn vget_low_u64(a: uint64x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shadd.v8i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i8")] - fn _vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; +pub fn vextq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7, + N as u32 + 8, + N as u32 + 9, + N as u32 + 10, + N as u32 + 11, + N as u32 + 12, + N as u32 + 13, + N as u32 + 14, + N as u32 + 15 + ] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) } - unsafe { _vhadd_s8(a, b) } } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shadd) + assert_instr(ext, N = 15) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14481,27 +14838,45 @@ pub fn vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shadd.v16i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v16i8")] - fn _vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; +pub fn vextq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { + simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7, + N as u32 + 8, + N as u32 + 9, + N as u32 + 10, + N as u32 + 11, + N as u32 + 12, + N as u32 + 13, + N as u32 + 14, + N as u32 + 15 + ] + ) } - unsafe { _vhaddq_s8(a, b) } } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shadd) + assert_instr(ext, N = 15) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14510,84 +14885,95 @@ pub fn vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shadd.v4i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i16")] - fn _vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; +pub fn vextq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7, + N as u32 + 8, + N as u32 + 9, + N as u32 + 10, + N as u32 + 11, + N as u32 + 12, + N as u32 + 13, + N as u32 + 14, + N as u32 + 15 + ] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) } - unsafe { _vhadd_s16(a, b) } } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))] +#[doc = "Floating-point fused Multiply-Add to accumulator (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shadd) + assert_instr(fmla) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shadd.v8i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i16")] - fn _vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; - } - unsafe { _vhaddq_s16(a, b) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { + unsafe { simd_fma(b, c, a) } } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))] +#[doc = "Floating-point fused Multiply-Add to accumulator (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shadd) + assert_instr(fmla) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shadd.v2i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v2i32")] - fn _vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; - } - unsafe { _vhadd_s32(a, b) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vfmaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { + unsafe { simd_fma(b, c, a) } } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s32)"] -#[inline(always)] +#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shadd) + assert_instr(fmla) )] #[cfg_attr( not(target_arch = "arm"), @@ -14597,26 +14983,18 @@ pub fn vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shadd.v4i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i32")] - fn _vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; - } - unsafe { _vhaddq_s32(a, b) } +pub fn vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + unsafe { simd_fma(b, c, a) } } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u8)"] -#[inline(always)] +#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhadd) + assert_instr(fmla) )] #[cfg_attr( not(target_arch = "arm"), @@ -14626,26 +15004,18 @@ pub fn vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhadd.v8i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i8")] - fn _vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; - } - unsafe { _vhadd_u8(a, b) } +pub fn vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + unsafe { simd_fma(b, c, a) } } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u8)"] -#[inline(always)] +#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhadd) + assert_instr(fmla) )] #[cfg_attr( not(target_arch = "arm"), @@ -14655,26 +15025,18 @@ pub fn vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhadd.v16i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v16i8")] - fn _vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; - } - unsafe { _vhaddq_u8(a, b) } +pub fn vfma_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { + vfma_f32(a, b, vdup_n_f32_vfp4(c)) } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u16)"] -#[inline(always)] +#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhadd) + assert_instr(fmla) )] #[cfg_attr( not(target_arch = "arm"), @@ -14684,84 +15046,70 @@ pub fn vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhadd.v4i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i16")] - fn _vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; - } - unsafe { _vhadd_u16(a, b) } +pub fn vfmaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { + vfmaq_f32(a, b, vdupq_n_f32_vfp4(c)) } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))] +#[doc = "Floating-point fused multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhadd) + assert_instr(fmls) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhadd.v8i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i16")] - fn _vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; +#[cfg(not(target_arch = "arm64ec"))] +pub fn vfms_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { + unsafe { + let b: float16x4_t = simd_neg(b); + vfma_f16(a, b, c) } - unsafe { _vhaddq_u16(a, b) } } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))] +#[doc = "Floating-point fused multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhadd) + assert_instr(fmls) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhadd.v2i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v2i32")] - fn _vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; +#[cfg(not(target_arch = "arm64ec"))] +pub fn vfmsq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { + unsafe { + let b: float16x8_t = simd_neg(b); + vfmaq_f16(a, b, c) } - unsafe { _vhadd_u32(a, b) } } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u32)"] -#[inline(always)] +#[doc = "Floating-point fused multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhadd) + assert_instr(fmls) )] #[cfg_attr( not(target_arch = "arm"), @@ -14771,26 +15119,21 @@ pub fn vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhadd.v4i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i32")] - fn _vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; +pub fn vfms_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + unsafe { + let b: float32x2_t = simd_neg(b); + vfma_f32(a, b, c) } - unsafe { _vhaddq_u32(a, b) } } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s16)"] -#[inline(always)] +#[doc = "Floating-point fused multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shsub) + assert_instr(fmls) )] #[cfg_attr( not(target_arch = "arm"), @@ -14800,26 +15143,21 @@ pub fn vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shsub.v4i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i16")] - fn _vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; +pub fn vfmsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + unsafe { + let b: float32x4_t = simd_neg(b); + vfmaq_f32(a, b, c) } - unsafe { _vhsub_s16(a, b) } } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s16)"] -#[inline(always)] +#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shsub) + assert_instr(fmls) )] #[cfg_attr( not(target_arch = "arm"), @@ -14829,26 +15167,18 @@ pub fn vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shsub.v8i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i16")] - fn _vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; - } - unsafe { _vhsubq_s16(a, b) } +pub fn vfms_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { + vfms_f32(a, b, vdup_n_f32_vfp4(c)) } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s32)"] -#[inline(always)] +#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shsub) + assert_instr(fmls) )] #[cfg_attr( not(target_arch = "arm"), @@ -14858,114 +15188,114 @@ pub fn vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shsub.v2i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v2i32")] - fn _vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; - } - unsafe { _vhsub_s32(a, b) } +pub fn vfmsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { + vfmsq_f32(a, b, vdupq_n_f32_vfp4(c)) } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shsub) -)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shsub.v4i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i32")] - fn _vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; - } - unsafe { _vhsubq_s32(a, b) } +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(nop))] +pub fn vget_high_f16(a: float16x8_t) -> float16x4_t { + unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) } } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s8)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shsub) -)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shsub.v8i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i8")] - fn _vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(nop))] +pub fn vget_high_f16(a: float16x8_t) -> float16x4_t { + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } - unsafe { _vhsub_s8(a, b) } } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s8)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shsub) + not(target_arch = "arm"), + stable(feature = "stdarch_neon_fp16", since = "1.94.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(nop))] +pub fn vget_low_f16(a: float16x8_t) -> float16x4_t { + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) } +} +#[doc = "Duplicate vector element to vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shsub.v16i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v16i8")] - fn _vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(nop))] +pub fn vget_low_f16(a: float16x8_t) -> float16x4_t { + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } - unsafe { _vhsubq_s8(a, b) } } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u8)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhsub) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) +)] +#[cfg_attr( + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) )] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14974,27 +15304,26 @@ pub fn vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhsub.v8i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i8")] - fn _vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; - } - unsafe { _vhsub_u8(a, b) } +pub fn vget_high_f32(a: float32x4_t) -> float32x2_t { + unsafe { simd_shuffle!(a, a, [2, 3]) } } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u8)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhsub) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) +)] +#[cfg_attr( + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) )] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15003,27 +15332,30 @@ pub fn vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhsub.v16i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v16i8")] - fn _vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; +pub fn vget_high_f32(a: float32x4_t) -> float32x2_t { + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, a, [2, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) } - unsafe { _vhsubq_u8(a, b) } } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhsub) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) +)] +#[cfg_attr( + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) )] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15032,27 +15364,26 @@ pub fn vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhsub.v4i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i16")] - fn _vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; - } - unsafe { _vhsub_u16(a, b) } +pub fn vget_high_p16(a: poly16x8_t) -> poly16x4_t { + unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) } } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhsub) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) )] +#[cfg_attr( + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) +)] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15061,27 +15392,30 @@ pub fn vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhsub.v8i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i16")] - fn _vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; +pub fn vget_high_p16(a: poly16x8_t) -> poly16x4_t { + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } - unsafe { _vhsubq_u16(a, b) } } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhsub) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) +)] +#[cfg_attr( + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) )] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15090,27 +15424,26 @@ pub fn vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhsub.v2i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v2i32")] - fn _vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; - } - unsafe { _vhsub_u32(a, b) } +pub fn vget_high_p8(a: poly8x16_t) -> poly8x8_t { + unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) } } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhsub) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) +)] +#[cfg_attr( + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) )] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15119,67 +15452,31 @@ pub fn vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhsub.v4i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i32")] - fn _vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; +pub fn vget_high_p8(a: poly8x16_t) -> poly8x8_t { + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } - unsafe { _vhsubq_u32(a, b) } -} -#[doc = "Load one single-element structure and replicate to all lanes of one register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) -)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld1_dup_f16(ptr: *const f16) -> float16x4_t { - let x: float16x4_t = vld1_lane_f16::<0>(ptr, transmute(f16x4::splat(0.0))); - simd_shuffle!(x, x, [0, 0, 0, 0]) } -#[doc = "Load one single-element structure and replicate to all lanes of one register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld1q_dup_f16(ptr: *const f16) -> float16x8_t { - let x: float16x8_t = vld1q_lane_f16::<0>(ptr, transmute(f16x8::splat(0.0))); - simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0]) -} -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) )] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15188,21 +15485,26 @@ pub unsafe fn vld1q_dup_f16(ptr: *const f16) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_f32(ptr: *const f32) -> float32x2_t { - transmute(f32x2::splat(*ptr)) +pub fn vget_high_s16(a: int16x8_t) -> int16x4_t { + unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) )] +#[cfg_attr( + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) +)] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15211,21 +15513,30 @@ pub unsafe fn vld1_dup_f32(ptr: *const f32) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_p16(ptr: *const p16) -> poly16x4_t { - transmute(u16x4::splat(*ptr)) +pub fn vget_high_s16(a: int16x8_t) -> int16x4_t { + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) +)] +#[cfg_attr( + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) )] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15234,21 +15545,26 @@ pub unsafe fn vld1_dup_p16(ptr: *const p16) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_p8(ptr: *const p8) -> poly8x8_t { - transmute(u8x8::splat(*ptr)) +pub fn vget_high_s32(a: int32x4_t) -> int32x2_t { + unsafe { simd_shuffle!(a, a, [2, 3]) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) )] +#[cfg_attr( + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) +)] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15257,21 +15573,30 @@ pub unsafe fn vld1_dup_p8(ptr: *const p8) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_s16(ptr: *const i16) -> int16x4_t { - transmute(i16x4::splat(*ptr)) +pub fn vget_high_s32(a: int32x4_t) -> int32x2_t { + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, a, [2, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) +)] +#[cfg_attr( + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) )] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15280,21 +15605,26 @@ pub unsafe fn vld1_dup_s16(ptr: *const i16) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_s32(ptr: *const i32) -> int32x2_t { - transmute(i32x2::splat(*ptr)) +pub fn vget_high_s8(a: int8x16_t) -> int8x8_t { + unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) )] +#[cfg_attr( + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) +)] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15303,21 +15633,31 @@ pub unsafe fn vld1_dup_s32(ptr: *const i32) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_s8(ptr: *const i8) -> int8x8_t { - transmute(i8x8::splat(*ptr)) +pub fn vget_high_s8(a: int8x16_t) -> int8x8_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) +)] +#[cfg_attr( + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) )] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15326,21 +15666,26 @@ pub unsafe fn vld1_dup_s8(ptr: *const i8) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_u16(ptr: *const u16) -> uint16x4_t { - transmute(u16x4::splat(*ptr)) +pub fn vget_high_u16(a: uint16x8_t) -> uint16x4_t { + unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) )] +#[cfg_attr( + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) +)] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15349,21 +15694,30 @@ pub unsafe fn vld1_dup_u16(ptr: *const u16) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_u32(ptr: *const u32) -> uint32x2_t { - transmute(u32x2::splat(*ptr)) +pub fn vget_high_u16(a: uint16x8_t) -> uint16x4_t { + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) +)] +#[cfg_attr( + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) )] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15372,21 +15726,26 @@ pub unsafe fn vld1_dup_u32(ptr: *const u32) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_u8(ptr: *const u8) -> uint8x8_t { - transmute(u8x8::splat(*ptr)) +pub fn vget_high_u32(a: uint32x4_t) -> uint32x2_t { + unsafe { simd_shuffle!(a, a, [2, 3]) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) )] +#[cfg_attr( + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) +)] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15395,21 +15754,30 @@ pub unsafe fn vld1_dup_u8(ptr: *const u8) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_dup_f32(ptr: *const f32) -> float32x4_t { - transmute(f32x4::splat(*ptr)) +pub fn vget_high_u32(a: uint32x4_t) -> uint32x2_t { + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, a, [2, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) +)] +#[cfg_attr( + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) )] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15418,21 +15786,26 @@ pub unsafe fn vld1q_dup_f32(ptr: *const f32) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_dup_p16(ptr: *const p16) -> poly16x8_t { - transmute(u16x8::splat(*ptr)) +pub fn vget_high_u8(a: uint8x16_t) -> uint8x8_t { + unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) )] +#[cfg_attr( + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) +)] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15441,21 +15814,31 @@ pub unsafe fn vld1q_dup_p16(ptr: *const p16) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_dup_p8(ptr: *const p8) -> poly8x16_t { - transmute(u8x16::splat(*ptr)) +pub fn vget_high_u8(a: uint8x16_t) -> uint8x8_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) +)] +#[cfg_attr( + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) )] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15464,21 +15847,26 @@ pub unsafe fn vld1q_dup_p8(ptr: *const p8) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_dup_s16(ptr: *const i16) -> int16x8_t { - transmute(i16x8::splat(*ptr)) +pub fn vget_high_p64(a: poly64x2_t) -> poly64x1_t { + unsafe { transmute(u64x1::new(simd_extract!(a, 1))) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) )] +#[cfg_attr( + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) +)] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15487,21 +15875,29 @@ pub unsafe fn vld1q_dup_s16(ptr: *const i16) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_dup_s32(ptr: *const i32) -> int32x4_t { - transmute(i32x4::splat(*ptr)) +pub fn vget_high_p64(a: poly64x2_t) -> poly64x1_t { + unsafe { + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + transmute(u64x1::new(simd_extract!(a, 1))) + } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) +)] +#[cfg_attr( + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) )] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15510,21 +15906,26 @@ pub unsafe fn vld1q_dup_s32(ptr: *const i32) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_dup_s64(ptr: *const i64) -> int64x2_t { - transmute(i64x2::splat(*ptr)) +pub fn vget_high_s64(a: int64x2_t) -> int64x1_t { + unsafe { int64x1_t([simd_extract!(a, 1)]) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) +)] +#[cfg_attr( + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) )] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15533,21 +15934,29 @@ pub unsafe fn vld1q_dup_s64(ptr: *const i64) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_dup_s8(ptr: *const i8) -> int8x16_t { - transmute(i8x16::splat(*ptr)) +pub fn vget_high_s64(a: int64x2_t) -> int64x1_t { + unsafe { + let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); + int64x1_t([simd_extract!(a, 1)]) + } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) )] +#[cfg_attr( + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) +)] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15556,21 +15965,26 @@ pub unsafe fn vld1q_dup_s8(ptr: *const i8) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_dup_u16(ptr: *const u16) -> uint16x8_t { - transmute(u16x8::splat(*ptr)) +pub fn vget_high_u64(a: uint64x2_t) -> uint64x1_t { + unsafe { uint64x1_t([simd_extract!(a, 1)]) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + all(test, target_arch = "aarch64", target_endian = "little", not(windows)), + assert_instr(mov) +)] +#[cfg_attr( + all(test, target_arch = "aarch64", target_endian = "big"), + assert_instr(ext) )] +#[cfg_attr(all(test, target_arch = "arm64ec"), assert_instr(dup))] +#[cfg_attr(all(test, target_arch = "aarch64", windows), assert_instr(dup))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15579,67 +15993,102 @@ pub unsafe fn vld1q_dup_u16(ptr: *const u16) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_dup_u32(ptr: *const u32) -> uint32x4_t { - transmute(u32x4::splat(*ptr)) +pub fn vget_high_u64(a: uint64x2_t) -> uint64x1_t { + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + uint64x1_t([simd_extract!(a, 1)]) + } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(nop, LANE = 0) )] -pub unsafe fn vld1q_dup_u64(ptr: *const u64) -> uint64x2_t { - transmute(u64x2::splat(*ptr)) +#[rustc_legacy_const_generics(1)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vget_lane_f16(a: float16x4_t) -> f16 { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_extract!(a, LANE as u32) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vget_lane_f16(a: float16x4_t) -> f16 { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + simd_extract!(a, LANE as u32) + } +} +#[doc = "Duplicate vector element to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f16)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) )] -pub unsafe fn vld1q_dup_u8(ptr: *const u8) -> uint8x16_t { - transmute(u8x16::splat(*ptr)) +#[rustc_legacy_const_generics(1)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vgetq_lane_f16(a: float16x8_t) -> f16 { + static_assert_uimm_bits!(LANE, 3); + unsafe { simd_extract!(a, LANE as u32) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] +#[doc = "Duplicate vector element to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ldr) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vgetq_lane_f16(a: float16x8_t) -> f16 { + static_assert_uimm_bits!(LANE, 3); + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + simd_extract!(a, LANE as u32) + } +} +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f32)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15648,30 +16097,18 @@ pub unsafe fn vld1q_dup_u8(ptr: *const u8) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_p64(ptr: *const p64) -> poly64x1_t { - let x: poly64x1_t; - #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - { - x = crate::core_arch::aarch64::vld1_p64(ptr); - } - #[cfg(target_arch = "arm")] - { - x = crate::core_arch::arm::vld1_p64(ptr); - }; - x +pub fn vget_lane_f32(v: float32x2_t) -> f32 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ldr) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15680,30 +16117,21 @@ pub unsafe fn vld1_dup_p64(ptr: *const p64) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_s64(ptr: *const i64) -> int64x1_t { - let x: int64x1_t; - #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - { - x = crate::core_arch::aarch64::vld1_s64(ptr); +pub fn vget_lane_f32(v: float32x2_t) -> f32 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { + let v: float32x2_t = simd_shuffle!(v, v, [1, 0]); + simd_extract!(v, IMM5 as u32) } - #[cfg(target_arch = "arm")] - { - x = crate::core_arch::arm::vld1_s64(ptr); - }; - x } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ldr) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15712,455 +16140,84 @@ pub unsafe fn vld1_dup_s64(ptr: *const i64) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_u64(ptr: *const u64) -> uint64x1_t { - let x: uint64x1_t; - #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - { - x = crate::core_arch::aarch64::vld1_u64(ptr); - } - #[cfg(target_arch = "arm")] - { - x = crate::core_arch::arm::vld1_u64(ptr); - }; - x -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] -pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t { - transmute(vld1_v4f16( - ptr as *const i8, - crate::mem::align_of::() as i32, - )) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] -pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t { - let ret_val: float16x4_t = transmute(vld1_v4f16( - ptr as *const i8, - crate::mem::align_of::() as i32, - )); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] -pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t { - transmute(vld1q_v8f16( - ptr as *const i8, - crate::mem::align_of::() as i32, - )) +pub fn vget_lane_p16(v: poly16x4_t) -> p16 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p16)"] +#[inline] #[cfg(target_endian = "big")] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] -pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t { - let ret_val: float16x8_t = transmute(vld1q_v8f16( - ptr as *const i8, - crate::mem::align_of::() as i32, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v4f16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4f16.p0")] - fn _vld1_f16_x2(a: *const f16) -> float16x4x2_t; - } - _vld1_f16_x2(a) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v4f16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4f16.p0")] - fn _vld1_f16_x3(a: *const f16) -> float16x4x3_t; +pub fn vget_lane_p16(v: poly16x4_t) -> p16 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { + let v: poly16x4_t = simd_shuffle!(v, v, [3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) } - _vld1_f16_x3(a) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v4f16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4f16.p0")] - fn _vld1_f16_x4(a: *const f16) -> float16x4x4_t; - } - _vld1_f16_x4(a) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v8f16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8f16.p0")] - fn _vld1q_f16_x2(a: *const f16) -> float16x8x2_t; - } - _vld1q_f16_x2(a) +pub fn vget_lane_p8(v: poly8x8_t) -> p8 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v8f16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8f16.p0")] - fn _vld1q_f16_x3(a: *const f16) -> float16x8x3_t; - } - _vld1q_f16_x3(a) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld1q_f16_x4(a: *const f16) -> float16x8x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v8f16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8f16.p0")] - fn _vld1q_f16_x4(a: *const f16) -> float16x8x4_t; +pub fn vget_lane_p8(v: poly8x8_t) -> p8 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { + let v: poly8x8_t = simd_shuffle!(v, v, [7, 6, 5, 4, 3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) } - _vld1q_f16_x4(a) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] -pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1_v2f32::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] -pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1q_v4f32::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] -pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1_v8i8::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] -pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1q_v16i8::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] -pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1_v4i16::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] -pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1q_v8i16::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] -pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1_v2i32::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] -pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1q_v4i32::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] -pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1_v1i64::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))] -pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1q_v2i64::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] -pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1_v8i8::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] -pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1q_v16i8::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] -pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1_v4i16::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] -pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1q_v8i16::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,aes")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))] -pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1q_v2i64::(ptr as *const i8)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16169,29 +16226,18 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v2f32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2f32.p0")] - fn _vld1_f32_x2(a: *const f32) -> float32x2x2_t; - } - _vld1_f32_x2(a) +pub fn vget_lane_s16(v: int16x4_t) -> i16 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16200,29 +16246,21 @@ pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v2f32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2f32.p0")] - fn _vld1_f32_x3(a: *const f32) -> float32x2x3_t; +pub fn vget_lane_s16(v: int16x4_t) -> i16 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { + let v: int16x4_t = simd_shuffle!(v, v, [3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) } - _vld1_f32_x3(a) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16231,29 +16269,18 @@ pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v2f32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2f32.p0")] - fn _vld1_f32_x4(a: *const f32) -> float32x2x4_t; - } - _vld1_f32_x4(a) +pub fn vget_lane_s32(v: int32x2_t) -> i32 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16262,29 +16289,21 @@ pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v4f32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4f32.p0")] - fn _vld1q_f32_x2(a: *const f32) -> float32x4x2_t; +pub fn vget_lane_s32(v: int32x2_t) -> i32 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { + let v: int32x2_t = simd_shuffle!(v, v, [1, 0]); + simd_extract!(v, IMM5 as u32) } - _vld1q_f32_x2(a) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16293,29 +16312,18 @@ pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v4f32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4f32.p0")] - fn _vld1q_f32_x3(a: *const f32) -> float32x4x3_t; - } - _vld1q_f32_x3(a) +pub fn vget_lane_s8(v: int8x8_t) -> i8 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16324,70 +16332,41 @@ pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v4f32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4f32.p0")] - fn _vld1q_f32_x4(a: *const f32) -> float32x4x4_t; +pub fn vget_lane_s8(v: int8x8_t) -> i8 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { + let v: int8x8_t = simd_shuffle!(v, v, [7, 6, 5, 4, 3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) } - _vld1q_f32_x4(a) } -#[doc = "Load one single-element structure to one lane of one register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 0) + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") )] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld1_lane_f16(ptr: *const f16, src: float16x4_t) -> float16x4_t { - static_assert_uimm_bits!(LANE, 2); - simd_insert!(src, LANE as u32, *ptr) -} -#[doc = "Load one single-element structure to one lane of one register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 0) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld1q_lane_f16(ptr: *const f16, src: float16x8_t) -> float16x8_t { - static_assert_uimm_bits!(LANE, 3); - simd_insert!(src, LANE as u32, *ptr) +pub fn vget_lane_u16(v: uint16x4_t) -> u16 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 1) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16396,23 +16375,21 @@ pub unsafe fn vld1q_lane_f16(ptr: *const f16, src: float16x8_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_f32(ptr: *const f32, src: float32x2_t) -> float32x2_t { - static_assert_uimm_bits!(LANE, 1); - simd_insert!(src, LANE as u32, *ptr) +pub fn vget_lane_u16(v: uint16x4_t) -> u16 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { + let v: uint16x4_t = simd_shuffle!(v, v, [3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 3) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16421,23 +16398,18 @@ pub unsafe fn vld1_lane_f32(ptr: *const f32, src: float32x2_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_p16(ptr: *const p16, src: poly16x4_t) -> poly16x4_t { - static_assert_uimm_bits!(LANE, 2); - simd_insert!(src, LANE as u32, *ptr) +pub fn vget_lane_u32(v: uint32x2_t) -> u32 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 7) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16446,23 +16418,21 @@ pub unsafe fn vld1_lane_p16(ptr: *const p16, src: poly16x4_t) - target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_p8(ptr: *const p8, src: poly8x8_t) -> poly8x8_t { - static_assert_uimm_bits!(LANE, 3); - simd_insert!(src, LANE as u32, *ptr) +pub fn vget_lane_u32(v: uint32x2_t) -> u32 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { + let v: uint32x2_t = simd_shuffle!(v, v, [1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 3) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16471,23 +16441,18 @@ pub unsafe fn vld1_lane_p8(ptr: *const p8, src: poly8x8_t) -> p target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_s16(ptr: *const i16, src: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 2); - simd_insert!(src, LANE as u32, *ptr) +pub fn vget_lane_u8(v: uint8x8_t) -> u8 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 1) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16496,23 +16461,21 @@ pub unsafe fn vld1_lane_s16(ptr: *const i16, src: int16x4_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_s32(ptr: *const i32, src: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - simd_insert!(src, LANE as u32, *ptr) +pub fn vget_lane_u8(v: uint8x8_t) -> u8 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { + let v: uint8x8_t = simd_shuffle!(v, v, [7, 6, 5, 4, 3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ldr, LANE = 0) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16521,23 +16484,18 @@ pub unsafe fn vld1_lane_s32(ptr: *const i32, src: int32x2_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_s64(ptr: *const i64, src: int64x1_t) -> int64x1_t { - static_assert!(LANE == 0); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_f32(v: float32x4_t) -> f32 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 7) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16546,23 +16504,21 @@ pub unsafe fn vld1_lane_s64(ptr: *const i64, src: int64x1_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_s8(ptr: *const i8, src: int8x8_t) -> int8x8_t { - static_assert_uimm_bits!(LANE, 3); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_f32(v: float32x4_t) -> f32 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { + let v: float32x4_t = simd_shuffle!(v, v, [3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 3) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16571,23 +16527,18 @@ pub unsafe fn vld1_lane_s8(ptr: *const i8, src: int8x8_t) -> in target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_u16(ptr: *const u16, src: uint16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(LANE, 2); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_p16(v: poly16x8_t) -> p16 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 1) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16596,23 +16547,21 @@ pub unsafe fn vld1_lane_u16(ptr: *const u16, src: uint16x4_t) - target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_u32(ptr: *const u32, src: uint32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 1); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_p16(v: poly16x8_t) -> p16 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { + let v: poly16x8_t = simd_shuffle!(v, v, [7, 6, 5, 4, 3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ldr, LANE = 0) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16621,23 +16570,18 @@ pub unsafe fn vld1_lane_u32(ptr: *const u32, src: uint32x2_t) - target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_u64(ptr: *const u64, src: uint64x1_t) -> uint64x1_t { - static_assert!(LANE == 0); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_p64(v: poly64x2_t) -> p64 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 7) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16646,23 +16590,21 @@ pub unsafe fn vld1_lane_u64(ptr: *const u64, src: uint64x1_t) - target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_u8(ptr: *const u8, src: uint8x8_t) -> uint8x8_t { - static_assert_uimm_bits!(LANE, 3); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_p64(v: poly64x2_t) -> p64 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { + let v: poly64x2_t = simd_shuffle!(v, v, [1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 3) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16671,23 +16613,18 @@ pub unsafe fn vld1_lane_u8(ptr: *const u8, src: uint8x8_t) -> u target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_f32(ptr: *const f32, src: float32x4_t) -> float32x4_t { - static_assert_uimm_bits!(LANE, 2); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_p8(v: poly8x16_t) -> p8 { + static_assert_uimm_bits!(IMM5, 4); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 7) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16696,23 +16633,22 @@ pub unsafe fn vld1q_lane_f32(ptr: *const f32, src: float32x4_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_p16(ptr: *const p16, src: poly16x8_t) -> poly16x8_t { - static_assert_uimm_bits!(LANE, 3); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_p8(v: poly8x16_t) -> p8 { + static_assert_uimm_bits!(IMM5, 4); + unsafe { + let v: poly8x16_t = + simd_shuffle!(v, v, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 15) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16721,23 +16657,18 @@ pub unsafe fn vld1q_lane_p16(ptr: *const p16, src: poly16x8_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_p8(ptr: *const p8, src: poly8x16_t) -> poly8x16_t { - static_assert_uimm_bits!(LANE, 4); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_s16(v: int16x8_t) -> i16 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 7) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16746,23 +16677,21 @@ pub unsafe fn vld1q_lane_p8(ptr: *const p8, src: poly8x16_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_s16(ptr: *const i16, src: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 3); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_s16(v: int16x8_t) -> i16 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { + let v: int16x8_t = simd_shuffle!(v, v, [7, 6, 5, 4, 3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 3) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16771,23 +16700,18 @@ pub unsafe fn vld1q_lane_s16(ptr: *const i16, src: int16x8_t) - target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_s32(ptr: *const i32, src: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_s32(v: int32x4_t) -> i32 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 1) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16796,23 +16720,21 @@ pub unsafe fn vld1q_lane_s32(ptr: *const i32, src: int32x4_t) - target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_s64(ptr: *const i64, src: int64x2_t) -> int64x2_t { - static_assert_uimm_bits!(LANE, 1); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_s32(v: int32x4_t) -> i32 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { + let v: int32x4_t = simd_shuffle!(v, v, [3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 15) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16821,23 +16743,18 @@ pub unsafe fn vld1q_lane_s64(ptr: *const i64, src: int64x2_t) - target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_s8(ptr: *const i8, src: int8x16_t) -> int8x16_t { - static_assert_uimm_bits!(LANE, 4); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_s64(v: int64x2_t) -> i64 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 7) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16846,23 +16763,21 @@ pub unsafe fn vld1q_lane_s8(ptr: *const i8, src: int8x16_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_u16(ptr: *const u16, src: uint16x8_t) -> uint16x8_t { - static_assert_uimm_bits!(LANE, 3); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_s64(v: int64x2_t) -> i64 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { + let v: int64x2_t = simd_shuffle!(v, v, [1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 3) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16871,23 +16786,18 @@ pub unsafe fn vld1q_lane_u16(ptr: *const u16, src: uint16x8_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_u32(ptr: *const u32, src: uint32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 2); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_s8(v: int8x16_t) -> i8 { + static_assert_uimm_bits!(IMM5, 4); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 1) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16896,23 +16806,22 @@ pub unsafe fn vld1q_lane_u32(ptr: *const u32, src: uint32x4_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_u64(ptr: *const u64, src: uint64x2_t) -> uint64x2_t { - static_assert_uimm_bits!(LANE, 1); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_s8(v: int8x16_t) -> i8 { + static_assert_uimm_bits!(IMM5, 4); + unsafe { + let v: int8x16_t = + simd_shuffle!(v, v, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 15) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16921,23 +16830,18 @@ pub unsafe fn vld1q_lane_u64(ptr: *const u64, src: uint64x2_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_u8(ptr: *const u8, src: uint8x16_t) -> uint8x16_t { - static_assert_uimm_bits!(LANE, 4); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_u16(v: uint16x8_t) -> u16 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ldr, LANE = 0) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16946,23 +16850,21 @@ pub unsafe fn vld1q_lane_u8(ptr: *const u8, src: uint8x16_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_p64(ptr: *const p64, src: poly64x1_t) -> poly64x1_t { - static_assert!(LANE == 0); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_u16(v: uint16x8_t) -> u16 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { + let v: uint16x8_t = simd_shuffle!(v, v, [7, 6, 5, 4, 3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u32)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 1) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16971,40 +16873,18 @@ pub unsafe fn vld1_lane_p64(ptr: *const p64, src: poly64x1_t) - target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_p64(ptr: *const p64, src: poly64x2_t) -> poly64x2_t { - static_assert_uimm_bits!(LANE, 1); - simd_insert!(src, LANE as u32, *ptr) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,aes")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] -pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t { - let a: *const i8 = ptr as *const i8; - let b: i32 = crate::mem::align_of::() as i32; - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v1i64")] - fn _vld1_v1i64(a: *const i8, b: i32) -> int64x1_t; - } - transmute(_vld1_v1i64(a, b)) +pub fn vgetq_lane_u32(v: uint32x4_t) -> u32 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17013,21 +16893,21 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t { - transmute(vld1_s64_x2(transmute(a))) +pub fn vgetq_lane_u32(v: uint32x4_t) -> u32 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { + let v: uint32x4_t = simd_shuffle!(v, v, [3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u64)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17036,21 +16916,18 @@ pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t { - transmute(vld1_s64_x3(transmute(a))) +pub fn vgetq_lane_u64(v: uint64x2_t) -> u64 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17059,22 +16936,21 @@ pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t { - transmute(vld1_s64_x4(transmute(a))) +pub fn vgetq_lane_u64(v: uint64x2_t) -> u64 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { + let v: uint64x2_t = simd_shuffle!(v, v, [1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u8)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17083,22 +16959,18 @@ pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t { - transmute(vld1q_s64_x2(transmute(a))) +pub fn vgetq_lane_u8(v: uint8x16_t) -> u8 { + static_assert_uimm_bits!(IMM5, 4); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u8)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17107,25 +16979,21 @@ pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t { - let mut ret_val: poly64x2x2_t = transmute(vld1q_s64_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val +pub fn vgetq_lane_u8(v: uint8x16_t) -> u8 { + static_assert_uimm_bits!(IMM5, 4); + unsafe { + let v: uint8x16_t = + simd_shuffle!(v, v, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 0))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17134,22 +17002,17 @@ pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t { - transmute(vld1q_s64_x3(transmute(a))) +pub fn vget_lane_p64(v: poly64x1_t) -> p64 { + static_assert!(IMM5 == 0); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 0))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17158,26 +17021,17 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t { - let mut ret_val: poly64x2x3_t = transmute(vld1q_s64_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val +pub fn vget_lane_s64(v: int64x1_t) -> i64 { + static_assert!(IMM5 == 0); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 0))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17186,22 +17040,17 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t { - transmute(vld1q_s64_x4(transmute(a))) +pub fn vget_lane_u64(v: uint64x1_t) -> u64 { + static_assert!(IMM5 == 0); + unsafe { simd_extract!(v, 0) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f32)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17210,130 +17059,16 @@ pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t { - let mut ret_val: poly64x2x4_t = transmute(vld1q_s64_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] -pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - vld1_v8i8::(ptr as *const i8) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] -pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - vld1q_v16i8::(ptr as *const i8) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] -pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - vld1_v4i16::(ptr as *const i8) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] -pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - vld1q_v8i16::(ptr as *const i8) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] -pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - vld1_v2i32::(ptr as *const i8) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] -pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - vld1q_v4i32::(ptr as *const i8) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] -pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - vld1_v1i64::(ptr as *const i8) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))] -pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - vld1q_v2i64::(ptr as *const i8) +pub fn vget_low_f32(a: float32x4_t) -> float32x2_t { + unsafe { simd_shuffle!(a, a, [0, 1]) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17342,29 +17077,20 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v8i8.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8i8.p0")] - fn _vld1_s8_x2(a: *const i8) -> int8x8x2_t; +pub fn vget_low_f32(a: float32x4_t) -> float32x2_t { + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, a, [0, 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) } - _vld1_s8_x2(a) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17373,29 +17099,16 @@ pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v8i8.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8i8.p0")] - fn _vld1_s8_x3(a: *const i8) -> int8x8x3_t; - } - _vld1_s8_x3(a) +pub fn vget_low_p16(a: poly16x8_t) -> poly16x4_t { + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17404,29 +17117,20 @@ pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v8i8.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8i8.p0")] - fn _vld1_s8_x4(a: *const i8) -> int8x8x4_t; +pub fn vget_low_p16(a: poly16x8_t) -> poly16x4_t { + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } - _vld1_s8_x4(a) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17435,29 +17139,16 @@ pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v16i8.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v16i8.p0")] - fn _vld1q_s8_x2(a: *const i8) -> int8x16x2_t; - } - _vld1q_s8_x2(a) +pub fn vget_low_p8(a: poly8x16_t) -> poly8x8_t { + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17466,29 +17157,39 @@ pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v16i8.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v16i8.p0")] - fn _vld1q_s8_x3(a: *const i8) -> int8x16x3_t; +pub fn vget_low_p8(a: poly8x16_t) -> poly8x8_t { + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } - _vld1q_s8_x3(a) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] +pub fn vget_low_s16(a: int16x8_t) -> int16x4_t { + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) } +} +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17497,29 +17198,38 @@ pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v16i8.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v16i8.p0")] - fn _vld1q_s8_x4(a: *const i8) -> int8x16x4_t; +pub fn vget_low_s16(a: int16x8_t) -> int16x4_t { + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } - _vld1q_s8_x4(a) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") )] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vget_low_s32(a: int32x4_t) -> int32x2_t { + unsafe { simd_shuffle!(a, a, [0, 1]) } +} +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17528,29 +17238,38 @@ pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v4i16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4i16.p0")] - fn _vld1_s16_x2(a: *const i16) -> int16x4x2_t; +pub fn vget_low_s32(a: int32x4_t) -> int32x2_t { + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, a, [0, 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) } - _vld1_s16_x2(a) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] +pub fn vget_low_s8(a: int8x16_t) -> int8x8_t { + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) } +} +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17559,29 +17278,39 @@ pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v4i16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4i16.p0")] - fn _vld1_s16_x3(a: *const i16) -> int16x4x3_t; +pub fn vget_low_s8(a: int8x16_t) -> int8x8_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } - _vld1_s16_x3(a) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] +pub fn vget_low_u16(a: uint16x8_t) -> uint16x4_t { + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) } +} +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17590,29 +17319,38 @@ pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v4i16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4i16.p0")] - fn _vld1_s16_x4(a: *const i16) -> int16x4x4_t; +pub fn vget_low_u16(a: uint16x8_t) -> uint16x4_t { + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } - _vld1_s16_x4(a) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] +pub fn vget_low_u32(a: uint32x4_t) -> uint32x2_t { + unsafe { simd_shuffle!(a, a, [0, 1]) } +} +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17621,29 +17359,38 @@ pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v8i16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8i16.p0")] - fn _vld1q_s16_x2(a: *const i16) -> int16x8x2_t; +pub fn vget_low_u32(a: uint32x4_t) -> uint32x2_t { + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, a, [0, 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) } - _vld1q_s16_x2(a) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] +pub fn vget_low_u8(a: uint8x16_t) -> uint8x8_t { + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) } +} +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17652,29 +17399,39 @@ pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v8i16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8i16.p0")] - fn _vld1q_s16_x3(a: *const i16) -> int16x8x3_t; +pub fn vget_low_u8(a: uint8x16_t) -> uint8x8_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } - _vld1q_s16_x3(a) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] +pub fn vget_low_p64(a: poly64x2_t) -> poly64x1_t { + unsafe { transmute(u64x1::new(simd_extract!(a, 0))) } +} +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17683,29 +17440,37 @@ pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v8i16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8i16.p0")] - fn _vld1q_s16_x4(a: *const i16) -> int16x8x4_t; +pub fn vget_low_p64(a: poly64x2_t) -> poly64x1_t { + unsafe { + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + transmute(u64x1::new(simd_extract!(a, 0))) } - _vld1q_s16_x4(a) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") )] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vget_low_s64(a: int64x2_t) -> int64x1_t { + unsafe { int64x1_t([simd_extract!(a, 0)]) } +} +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17714,29 +17479,37 @@ pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v2i32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2i32.p0")] - fn _vld1_s32_x2(a: *const i32) -> int32x2x2_t; +pub fn vget_low_s64(a: int64x2_t) -> int64x1_t { + unsafe { + let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); + int64x1_t([simd_extract!(a, 0)]) } - _vld1_s32_x2(a) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") )] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vget_low_u64(a: uint64x2_t) -> uint64x1_t { + unsafe { uint64x1_t([simd_extract!(a, 0)]) } +} +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17745,28 +17518,21 @@ pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v2i32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2i32.p0")] - fn _vld1_s32_x3(a: *const i32) -> int32x2x3_t; +pub fn vget_low_u64(a: uint64x2_t) -> uint64x1_t { + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + uint64x1_t([simd_extract!(a, 0)]) } - _vld1_s32_x3(a) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(shadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -17776,28 +17542,26 @@ pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t { +pub fn vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v2i32.p0" + link_name = "llvm.aarch64.neon.shadd.v8i8" )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2i32.p0")] - fn _vld1_s32_x4(a: *const i32) -> int32x2x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i8")] + fn _vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } - _vld1_s32_x4(a) + unsafe { _vhadd_s8(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(shadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -17807,28 +17571,26 @@ pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t { +pub fn vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v4i32.p0" + link_name = "llvm.aarch64.neon.shadd.v16i8" )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4i32.p0")] - fn _vld1q_s32_x2(a: *const i32) -> int32x4x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v16i8")] + fn _vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } - _vld1q_s32_x2(a) + unsafe { _vhaddq_s8(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(shadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -17838,28 +17600,26 @@ pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t { +pub fn vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v4i32.p0" + link_name = "llvm.aarch64.neon.shadd.v4i16" )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4i32.p0")] - fn _vld1q_s32_x3(a: *const i32) -> int32x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i16")] + fn _vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } - _vld1q_s32_x3(a) + unsafe { _vhadd_s16(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(shadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -17869,28 +17629,26 @@ pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t { +pub fn vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v4i32.p0" + link_name = "llvm.aarch64.neon.shadd.v8i16" )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4i32.p0")] - fn _vld1q_s32_x4(a: *const i32) -> int32x4x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i16")] + fn _vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } - _vld1q_s32_x4(a) + unsafe { _vhaddq_s16(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(shadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -17900,28 +17658,26 @@ pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t { +pub fn vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v1i64.p0" + link_name = "llvm.aarch64.neon.shadd.v2i32" )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v1i64.p0")] - fn _vld1_s64_x2(a: *const i64) -> int64x1x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v2i32")] + fn _vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } - _vld1_s64_x2(a) + unsafe { _vhadd_s32(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(shadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -17931,28 +17687,26 @@ pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t { +pub fn vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v1i64.p0" + link_name = "llvm.aarch64.neon.shadd.v4i32" )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v1i64.p0")] - fn _vld1_s64_x3(a: *const i64) -> int64x1x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i32")] + fn _vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } - _vld1_s64_x3(a) + unsafe { _vhaddq_s32(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(uhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -17962,28 +17716,26 @@ pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t { +pub fn vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v1i64.p0" + link_name = "llvm.aarch64.neon.uhadd.v8i8" )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v1i64.p0")] - fn _vld1_s64_x4(a: *const i64) -> int64x1x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i8")] + fn _vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; } - _vld1_s64_x4(a) + unsafe { _vhadd_u8(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(uhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -17993,28 +17745,26 @@ pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t { +pub fn vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v2i64.p0" + link_name = "llvm.aarch64.neon.uhadd.v16i8" )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2i64.p0")] - fn _vld1q_s64_x2(a: *const i64) -> int64x2x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v16i8")] + fn _vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; } - _vld1q_s64_x2(a) + unsafe { _vhaddq_u8(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(uhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -18024,28 +17774,26 @@ pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t { +pub fn vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v2i64.p0" + link_name = "llvm.aarch64.neon.uhadd.v4i16" )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2i64.p0")] - fn _vld1q_s64_x3(a: *const i64) -> int64x2x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i16")] + fn _vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; } - _vld1q_s64_x3(a) + unsafe { _vhadd_u16(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(uhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -18055,29 +17803,26 @@ pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t { +pub fn vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v2i64.p0" + link_name = "llvm.aarch64.neon.uhadd.v8i16" )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2i64.p0")] - fn _vld1q_s64_x4(a: *const i64) -> int64x2x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i16")] + fn _vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; } - _vld1q_s64_x4(a) + unsafe { _vhaddq_u16(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(uhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -18087,21 +17832,26 @@ pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { - transmute(vld1_s8_x2(transmute(a))) +pub fn vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhadd.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v2i32")] + fn _vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; + } + unsafe { _vhadd_u32(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(uhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -18111,24 +17861,26 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { - let mut ret_val: uint8x8x2_t = transmute(vld1_s8_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub fn vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhadd.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i32")] + fn _vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; + } + unsafe { _vhaddq_u32(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(shsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -18138,21 +17890,26 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { - transmute(vld1_s8_x3(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +pub fn vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shsub.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i16")] + fn _vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + unsafe { _vhsub_s16(a, b) } +} +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(shsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -18162,25 +17919,26 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { - let mut ret_val: uint8x8x3_t = transmute(vld1_s8_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub fn vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shsub.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i16")] + fn _vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + unsafe { _vhsubq_s16(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(shsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -18190,21 +17948,26 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { - transmute(vld1_s8_x4(transmute(a))) +pub fn vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shsub.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v2i32")] + fn _vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + unsafe { _vhsub_s32(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(shsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -18214,26 +17977,26 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { - let mut ret_val: uint8x8x4_t = transmute(vld1_s8_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub fn vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shsub.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i32")] + fn _vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + unsafe { _vhsubq_s32(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(shsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -18243,21 +18006,26 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { - transmute(vld1q_s8_x2(transmute(a))) +pub fn vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shsub.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i8")] + fn _vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + unsafe { _vhsub_s8(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(shsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -18267,36 +18035,26 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { - let mut ret_val: uint8x16x2_t = transmute(vld1q_s8_x2(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub fn vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shsub.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v16i8")] + fn _vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + } + unsafe { _vhsubq_s8(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(uhsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -18306,21 +18064,26 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { - transmute(vld1q_s8_x3(transmute(a))) +pub fn vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhsub.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i8")] + fn _vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; + } + unsafe { _vhsub_u8(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(uhsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -18330,43 +18093,26 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { - let mut ret_val: uint8x16x3_t = transmute(vld1q_s8_x3(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub fn vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhsub.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v16i8")] + fn _vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; + } + unsafe { _vhsubq_u8(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(uhsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -18376,21 +18122,26 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { - transmute(vld1q_s8_x4(transmute(a))) +pub fn vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhsub.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i16")] + fn _vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; + } + unsafe { _vhsub_u16(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(uhsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -18400,50 +18151,26 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { - let mut ret_val: uint8x16x4_t = transmute(vld1q_s8_x4(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.3 = unsafe { - simd_shuffle!( - ret_val.3, - ret_val.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub fn vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhsub.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i16")] + fn _vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; + } + unsafe { _vhsubq_u16(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(uhsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -18453,21 +18180,26 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { - transmute(vld1_s16_x2(transmute(a))) +pub fn vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhsub.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v2i32")] + fn _vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; + } + unsafe { _vhsub_u32(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(uhsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -18477,48 +18209,66 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { - let mut ret_val: uint16x4x2_t = transmute(vld1_s16_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val +pub fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhsub.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i32")] + fn _vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; + } + unsafe { _vhsubq_u32(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"] +#[doc = "Load one single-element structure and replicate to all lanes of one register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + assert_instr(ld1r) )] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld1_dup_f16(ptr: *const f16) -> float16x4_t { + let x: float16x4_t = vld1_lane_f16::<0>(ptr, transmute(f16x4::splat(0.0))); + simd_shuffle!(x, x, [0, 0, 0, 0]) +} +#[doc = "Load one single-element structure and replicate to all lanes of one register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1r) )] -pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { - transmute(vld1_s16_x3(transmute(a))) +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld1q_dup_f16(ptr: *const f16) -> float16x8_t { + let x: float16x8_t = vld1q_lane_f16::<0>(ptr, transmute(f16x8::splat(0.0))); + simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0]) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18528,25 +18278,20 @@ pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { - let mut ret_val: uint16x4x3_t = transmute(vld1_s16_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_dup_f32(ptr: *const f32) -> float32x2_t { + transmute(f32x2::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18556,21 +18301,20 @@ pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { - transmute(vld1_s16_x4(transmute(a))) +pub unsafe fn vld1_dup_p16(ptr: *const p16) -> poly16x4_t { + transmute(u16x4::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18580,26 +18324,20 @@ pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { - let mut ret_val: uint16x4x4_t = transmute(vld1_s16_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_dup_p8(ptr: *const p8) -> poly8x8_t { + transmute(u8x8::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18609,21 +18347,20 @@ pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { - transmute(vld1q_s16_x2(transmute(a))) +pub unsafe fn vld1_dup_s16(ptr: *const i16) -> int16x4_t { + transmute(i16x4::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18633,24 +18370,20 @@ pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { - let mut ret_val: uint16x8x2_t = transmute(vld1q_s16_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_dup_s32(ptr: *const i32) -> int32x2_t { + transmute(i32x2::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18660,21 +18393,20 @@ pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { - transmute(vld1q_s16_x3(transmute(a))) +pub unsafe fn vld1_dup_s8(ptr: *const i8) -> int8x8_t { + transmute(i8x8::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18684,25 +18416,20 @@ pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { - let mut ret_val: uint16x8x3_t = transmute(vld1q_s16_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_dup_u16(ptr: *const u16) -> uint16x4_t { + transmute(u16x4::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18712,21 +18439,20 @@ pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { - transmute(vld1q_s16_x4(transmute(a))) +pub unsafe fn vld1_dup_u32(ptr: *const u32) -> uint32x2_t { + transmute(u32x2::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18736,26 +18462,20 @@ pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { - let mut ret_val: uint16x8x4_t = transmute(vld1q_s16_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_dup_u8(ptr: *const u8) -> uint8x8_t { + transmute(u8x8::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18765,21 +18485,20 @@ pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { - transmute(vld1_s32_x2(transmute(a))) +pub unsafe fn vld1q_dup_f32(ptr: *const f32) -> float32x4_t { + transmute(f32x4::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18789,24 +18508,20 @@ pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { - let mut ret_val: uint32x2x2_t = transmute(vld1_s32_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val +pub unsafe fn vld1q_dup_p16(ptr: *const p16) -> poly16x8_t { + transmute(u16x8::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18816,21 +18531,20 @@ pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { - transmute(vld1_s32_x3(transmute(a))) +pub unsafe fn vld1q_dup_p8(ptr: *const p8) -> poly8x16_t { + transmute(u8x16::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18840,25 +18554,20 @@ pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { - let mut ret_val: uint32x2x3_t = transmute(vld1_s32_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val +pub unsafe fn vld1q_dup_s16(ptr: *const i16) -> int16x8_t { + transmute(i16x8::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18868,21 +18577,20 @@ pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { - transmute(vld1_s32_x4(transmute(a))) +pub unsafe fn vld1q_dup_s32(ptr: *const i32) -> int32x4_t { + transmute(i32x4::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18892,26 +18600,20 @@ pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { - let mut ret_val: uint32x2x4_t = transmute(vld1_s32_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; - ret_val +pub unsafe fn vld1q_dup_s64(ptr: *const i64) -> int64x2_t { + transmute(i64x2::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18921,21 +18623,20 @@ pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { - transmute(vld1q_s32_x2(transmute(a))) +pub unsafe fn vld1q_dup_s8(ptr: *const i8) -> int8x16_t { + transmute(i8x16::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18945,24 +18646,20 @@ pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { - let mut ret_val: uint32x4x2_t = transmute(vld1q_s32_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_dup_u16(ptr: *const u16) -> uint16x8_t { + transmute(u16x8::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18972,21 +18669,20 @@ pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { - transmute(vld1q_s32_x3(transmute(a))) +pub unsafe fn vld1q_dup_u32(ptr: *const u32) -> uint32x4_t { + transmute(u32x4::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18996,25 +18692,20 @@ pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { - let mut ret_val: uint32x4x3_t = transmute(vld1q_s32_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_dup_u64(ptr: *const u64) -> uint64x2_t { + transmute(u64x2::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -19024,21 +18715,20 @@ pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t { - transmute(vld1q_s32_x4(transmute(a))) +pub unsafe fn vld1q_dup_u8(ptr: *const u8) -> uint8x16_t { + transmute(u8x16::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] +#[inline] +#[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ldr) )] #[cfg_attr( not(target_arch = "arm"), @@ -19048,25 +18738,29 @@ pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t { - let mut ret_val: uint32x4x4_t = transmute(vld1q_s32_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_dup_p64(ptr: *const p64) -> poly64x1_t { + let x: poly64x1_t; + #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] + { + x = crate::core_arch::aarch64::vld1_p64(ptr); + } + #[cfg(target_arch = "arm")] + { + x = crate::core_arch::arm::vld1_p64(ptr); + }; + x } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ldr) )] #[cfg_attr( not(target_arch = "arm"), @@ -19076,20 +18770,29 @@ pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t { - transmute(vld1_s64_x2(transmute(a))) +pub unsafe fn vld1_dup_s64(ptr: *const i64) -> int64x1_t { + let x: int64x1_t; + #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] + { + x = crate::core_arch::aarch64::vld1_s64(ptr); + } + #[cfg(target_arch = "arm")] + { + x = crate::core_arch::arm::vld1_s64(ptr); + }; + x } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ldr) )] #[cfg_attr( not(target_arch = "arm"), @@ -19099,95 +18802,366 @@ pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t { - transmute(vld1_s64_x3(transmute(a))) +pub unsafe fn vld1_dup_u64(ptr: *const u64) -> uint64x1_t { + let x: uint64x1_t; + #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] + { + x = crate::core_arch::aarch64::vld1_u64(ptr); + } + #[cfg(target_arch = "arm")] + { + x = crate::core_arch::arm::vld1_u64(ptr); + }; + x +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t { + transmute(vld1_v4f16( + ptr as *const i8, + crate::mem::align_of::() as i32, + )) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t { + transmute(vld1q_v8f16( + ptr as *const i8, + crate::mem::align_of::() as i32, + )) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(ld) )] -pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t { - transmute(vld1_s64_x4(transmute(a))) +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + assert_instr(ld) )] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t { + crate::ptr::read_unaligned(a.cast()) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) )] -pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t { - transmute(vld1q_s64_x2(transmute(a))) +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t { + crate::ptr::read_unaligned(a.cast()) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) )] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t { + crate::ptr::read_unaligned(a.cast()) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) )] -pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t { - let mut ret_val: uint64x2x2_t = transmute(vld1q_s64_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld1q_f16_x4(a: *const f16) -> float16x8x4_t { + crate::ptr::read_unaligned(a.cast()) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] +pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1_v2f32::(ptr as *const i8)) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] +pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1q_v4f32::(ptr as *const i8)) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1_v8i8::(ptr as *const i8)) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1q_v16i8::(ptr as *const i8)) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1_v4i16::(ptr as *const i8)) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1q_v8i16::(ptr as *const i8)) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] +pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1_v2i32::(ptr as *const i8)) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] +pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1q_v4i32::(ptr as *const i8)) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] +pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1_v1i64::(ptr as *const i8)) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))] +pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1q_v2i64::(ptr as *const i8)) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1_v8i8::(ptr as *const i8)) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1q_v16i8::(ptr as *const i8)) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1_v4i16::(ptr as *const i8)) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1q_v8i16::(ptr as *const i8)) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,aes")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))] +pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1q_v2i64::(ptr as *const i8)) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19197,21 +19171,20 @@ pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t { - transmute(vld1q_s64_x3(transmute(a))) +pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19221,25 +19194,20 @@ pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t { - let mut ret_val: uint64x2x3_t = transmute(vld1q_s64_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val +pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19249,21 +19217,20 @@ pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t { - transmute(vld1q_s64_x4(transmute(a))) +pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19273,26 +19240,20 @@ pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t { - let mut ret_val: uint64x2x4_t = transmute(vld1q_s64_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; - ret_val +pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19302,21 +19263,20 @@ pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t { - transmute(vld1_s8_x2(transmute(a))) +pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19326,48 +19286,61 @@ pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t { - let mut ret_val: poly8x8x2_t = transmute(vld1_s8_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"] +#[doc = "Load one single-element structure to one lane of one register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + assert_instr(ld1, LANE = 0) )] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld1_lane_f16(ptr: *const f16, src: float16x4_t) -> float16x4_t { + static_assert_uimm_bits!(LANE, 2); + simd_insert!(src, LANE as u32, *ptr) +} +#[doc = "Load one single-element structure to one lane of one register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))] #[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1, LANE = 0) )] -pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t { - transmute(vld1_s8_x3(transmute(a))) +#[rustc_legacy_const_generics(2)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld1q_lane_f16(ptr: *const f16, src: float16x8_t) -> float16x8_t { + static_assert_uimm_bits!(LANE, 3); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1, LANE = 1) )] #[cfg_attr( not(target_arch = "arm"), @@ -19377,25 +19350,22 @@ pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t { - let mut ret_val: poly8x8x3_t = transmute(vld1_s8_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_lane_f32(ptr: *const f32, src: float32x2_t) -> float32x2_t { + static_assert_uimm_bits!(LANE, 1); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1, LANE = 3) )] #[cfg_attr( not(target_arch = "arm"), @@ -19405,21 +19375,22 @@ pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t { - transmute(vld1_s8_x4(transmute(a))) +pub unsafe fn vld1_lane_p16(ptr: *const p16, src: poly16x4_t) -> poly16x4_t { + static_assert_uimm_bits!(LANE, 2); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1, LANE = 7) )] #[cfg_attr( not(target_arch = "arm"), @@ -19429,26 +19400,22 @@ pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t { - let mut ret_val: poly8x8x4_t = transmute(vld1_s8_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_lane_p8(ptr: *const p8, src: poly8x8_t) -> poly8x8_t { + static_assert_uimm_bits!(LANE, 3); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1, LANE = 3) )] #[cfg_attr( not(target_arch = "arm"), @@ -19458,21 +19425,22 @@ pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t { - transmute(vld1q_s8_x2(transmute(a))) +pub unsafe fn vld1_lane_s16(ptr: *const i16, src: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(LANE, 2); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1, LANE = 1) )] #[cfg_attr( not(target_arch = "arm"), @@ -19482,36 +19450,22 @@ pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t { - let mut ret_val: poly8x16x2_t = transmute(vld1q_s8_x2(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld1_lane_s32(ptr: *const i32, src: int32x2_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ldr, LANE = 0) )] #[cfg_attr( not(target_arch = "arm"), @@ -19521,21 +19475,22 @@ pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t { - transmute(vld1q_s8_x3(transmute(a))) +pub unsafe fn vld1_lane_s64(ptr: *const i64, src: int64x1_t) -> int64x1_t { + static_assert!(LANE == 0); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1, LANE = 7) )] #[cfg_attr( not(target_arch = "arm"), @@ -19545,43 +19500,22 @@ pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t { - let mut ret_val: poly8x16x3_t = transmute(vld1q_s8_x3(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld1_lane_s8(ptr: *const i8, src: int8x8_t) -> int8x8_t { + static_assert_uimm_bits!(LANE, 3); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1, LANE = 3) )] #[cfg_attr( not(target_arch = "arm"), @@ -19591,21 +19525,22 @@ pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t { - transmute(vld1q_s8_x4(transmute(a))) +pub unsafe fn vld1_lane_u16(ptr: *const u16, src: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(LANE, 2); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1, LANE = 1) )] #[cfg_attr( not(target_arch = "arm"), @@ -19615,50 +19550,22 @@ pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t { - let mut ret_val: poly8x16x4_t = transmute(vld1q_s8_x4(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.3 = unsafe { - simd_shuffle!( - ret_val.3, - ret_val.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld1_lane_u32(ptr: *const u32, src: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 1); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ldr, LANE = 0) )] #[cfg_attr( not(target_arch = "arm"), @@ -19668,21 +19575,22 @@ pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t { - transmute(vld1_s16_x2(transmute(a))) +pub unsafe fn vld1_lane_u64(ptr: *const u64, src: uint64x1_t) -> uint64x1_t { + static_assert!(LANE == 0); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1, LANE = 7) )] #[cfg_attr( not(target_arch = "arm"), @@ -19692,24 +19600,22 @@ pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t { - let mut ret_val: poly16x4x2_t = transmute(vld1_s16_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_lane_u8(ptr: *const u8, src: uint8x8_t) -> uint8x8_t { + static_assert_uimm_bits!(LANE, 3); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1, LANE = 3) )] #[cfg_attr( not(target_arch = "arm"), @@ -19719,21 +19625,22 @@ pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t { - transmute(vld1_s16_x3(transmute(a))) +pub unsafe fn vld1q_lane_f32(ptr: *const f32, src: float32x4_t) -> float32x4_t { + static_assert_uimm_bits!(LANE, 2); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1, LANE = 7) )] #[cfg_attr( not(target_arch = "arm"), @@ -19743,25 +19650,22 @@ pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t { - let mut ret_val: poly16x4x3_t = transmute(vld1_s16_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_lane_p16(ptr: *const p16, src: poly16x8_t) -> poly16x8_t { + static_assert_uimm_bits!(LANE, 3); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1, LANE = 15) )] #[cfg_attr( not(target_arch = "arm"), @@ -19771,21 +19675,22 @@ pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t { - transmute(vld1_s16_x4(transmute(a))) +pub unsafe fn vld1q_lane_p8(ptr: *const p8, src: poly8x16_t) -> poly8x16_t { + static_assert_uimm_bits!(LANE, 4); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1, LANE = 7) )] #[cfg_attr( not(target_arch = "arm"), @@ -19795,26 +19700,22 @@ pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t { - let mut ret_val: poly16x4x4_t = transmute(vld1_s16_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_lane_s16(ptr: *const i16, src: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(LANE, 3); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1, LANE = 3) )] #[cfg_attr( not(target_arch = "arm"), @@ -19824,21 +19725,22 @@ pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t { - transmute(vld1q_s16_x2(transmute(a))) +pub unsafe fn vld1q_lane_s32(ptr: *const i32, src: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1, LANE = 1) )] #[cfg_attr( not(target_arch = "arm"), @@ -19848,24 +19750,22 @@ pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t { - let mut ret_val: poly16x8x2_t = transmute(vld1q_s16_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_lane_s64(ptr: *const i64, src: int64x2_t) -> int64x2_t { + static_assert_uimm_bits!(LANE, 1); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1, LANE = 15) )] #[cfg_attr( not(target_arch = "arm"), @@ -19875,21 +19775,22 @@ pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t { - transmute(vld1q_s16_x3(transmute(a))) +pub unsafe fn vld1q_lane_s8(ptr: *const i8, src: int8x16_t) -> int8x16_t { + static_assert_uimm_bits!(LANE, 4); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1, LANE = 7) )] #[cfg_attr( not(target_arch = "arm"), @@ -19899,25 +19800,22 @@ pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t { - let mut ret_val: poly16x8x3_t = transmute(vld1q_s16_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_lane_u16(ptr: *const u16, src: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(LANE, 3); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1, LANE = 3) )] #[cfg_attr( not(target_arch = "arm"), @@ -19927,21 +19825,22 @@ pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t { - transmute(vld1q_s16_x4(transmute(a))) +pub unsafe fn vld1q_lane_u32(ptr: *const u32, src: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld1, LANE = 1) )] #[cfg_attr( not(target_arch = "arm"), @@ -19951,183 +19850,47 @@ pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t { - let mut ret_val: poly16x8x4_t = transmute(vld1q_s16_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[inline(always)] -#[rustc_legacy_const_generics(1)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vld1_v1i64(a: *const i8) -> int64x1_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v1i64")] - fn _vld1_v1i64(a: *const i8, b: i32) -> int64x1_t; - } - _vld1_v1i64(a, ALIGN) -} -#[inline(always)] -#[rustc_legacy_const_generics(1)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vld1_v2f32(a: *const i8) -> float32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2f32")] - fn _vld1_v2f32(a: *const i8, b: i32) -> float32x2_t; - } - _vld1_v2f32(a, ALIGN) -} -#[inline(always)] -#[rustc_legacy_const_generics(1)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vld1_v2i32(a: *const i8) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2i32")] - fn _vld1_v2i32(a: *const i8, b: i32) -> int32x2_t; - } - _vld1_v2i32(a, ALIGN) -} -#[inline(always)] -#[rustc_legacy_const_generics(1)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vld1_v4i16(a: *const i8) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4i16")] - fn _vld1_v4i16(a: *const i8, b: i32) -> int16x4_t; - } - _vld1_v4i16(a, ALIGN) -} -#[inline(always)] -#[rustc_legacy_const_generics(1)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vld1_v8i8(a: *const i8) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8i8")] - fn _vld1_v8i8(a: *const i8, b: i32) -> int8x8_t; - } - _vld1_v8i8(a, ALIGN) -} -#[inline(always)] -#[rustc_legacy_const_generics(1)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vld1q_v16i8(a: *const i8) -> int8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v16i8")] - fn _vld1q_v16i8(a: *const i8, b: i32) -> int8x16_t; - } - _vld1q_v16i8(a, ALIGN) -} -#[inline(always)] -#[rustc_legacy_const_generics(1)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vld1q_v2i64(a: *const i8) -> int64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2i64")] - fn _vld1q_v2i64(a: *const i8, b: i32) -> int64x2_t; - } - _vld1q_v2i64(a, ALIGN) -} -#[inline(always)] -#[rustc_legacy_const_generics(1)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vld1q_v4f32(a: *const i8) -> float32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4f32")] - fn _vld1q_v4f32(a: *const i8, b: i32) -> float32x4_t; - } - _vld1q_v4f32(a, ALIGN) -} -#[inline(always)] -#[rustc_legacy_const_generics(1)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vld1q_v4i32(a: *const i8) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4i32")] - fn _vld1q_v4i32(a: *const i8, b: i32) -> int32x4_t; - } - _vld1q_v4i32(a, ALIGN) -} -#[inline(always)] -#[rustc_legacy_const_generics(1)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vld1q_v8i16(a: *const i8) -> int16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8i16")] - fn _vld1q_v8i16(a: *const i8, b: i32) -> int16x8_t; - } - _vld1q_v8i16(a, ALIGN) -} -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg(not(target_arch = "arm64ec"))] -unsafe fn vld1_v4f16(a: *const i8, b: i32) -> float16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4f16")] - fn _vld1_v4f16(a: *const i8, b: i32) -> float16x4_t; - } - _vld1_v4f16(a, b) +pub unsafe fn vld1q_lane_u64(ptr: *const u64, src: uint64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 1); + simd_insert!(src, LANE as u32, *ptr) } -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg(not(target_arch = "arm64ec"))] -unsafe fn vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8f16")] - fn _vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t; - } - _vld1q_v8f16(a, b) +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1, LANE = 15) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_lane_u8(ptr: *const u8, src: uint8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(LANE, 4); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p64)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + assert_instr(ldr, LANE = 0) )] #[cfg_attr( not(target_arch = "arm"), @@ -20137,387 +19900,306 @@ unsafe fn vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_dup_p64(ptr: *const p64) -> poly64x2_t { - let x = vld1q_lane_p64::<0>(ptr, transmute(u64x2::splat(0))); - simd_shuffle!(x, x, [0, 0]) +pub unsafe fn vld1_lane_p64(ptr: *const p64, src: poly64x1_t) -> poly64x1_t { + static_assert!(LANE == 0); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[inline] +#[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4f16.p0")] - fn _vld2_dup_f16(ptr: *const f16, size: i32) -> float16x4x2_t; - } - _vld2_dup_f16(a as _, 2) +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1, LANE = 1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_lane_p64(ptr: *const p64, src: poly64x2_t) -> poly64x2_t { + static_assert_uimm_bits!(LANE, 1); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[inline] #[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t { +#[target_feature(enable = "neon,aes")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] +pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t { + let a: *const i8 = ptr as *const i8; + let b: i32 = crate::mem::align_of::() as i32; unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8f16.p0")] - fn _vld2q_dup_f16(ptr: *const f16, size: i32) -> float16x8x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v1i64")] + fn _vld1_v1i64(a: *const i8, b: i32) -> int64x1_t; } - _vld2q_dup_f16(a as _, 2) + transmute(_vld1_v1i64(a, b)) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2r.v4f16.p0" - )] - fn _vld2_dup_f16(ptr: *const f16) -> float16x4x2_t; - } - _vld2_dup_f16(a as _) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2r.v8f16.p0" - )] - fn _vld2q_dup_f16(ptr: *const f16) -> float16x8x2_t; - } - _vld2q_dup_f16(a as _) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v2f32.p0")] - fn _vld2_dup_f32(ptr: *const i8, size: i32) -> float32x2x2_t; - } - _vld2_dup_f32(a as *const i8, 4) +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4f32.p0")] - fn _vld2q_dup_f32(ptr: *const i8, size: i32) -> float32x4x2_t; - } - _vld2q_dup_f32(a as *const i8, 4) +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8i8.p0")] - fn _vld2_dup_s8(ptr: *const i8, size: i32) -> int8x8x2_t; - } - _vld2_dup_s8(a as *const i8, 1) +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v16i8.p0")] - fn _vld2q_dup_s8(ptr: *const i8, size: i32) -> int8x16x2_t; - } - _vld2q_dup_s8(a as *const i8, 1) +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] #[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4i16.p0")] - fn _vld2_dup_s16(ptr: *const i8, size: i32) -> int16x4x2_t; - } - _vld2_dup_s16(a as *const i8, 2) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + vld1_v8i8::(ptr as *const i8) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] #[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8i16.p0")] - fn _vld2q_dup_s16(ptr: *const i8, size: i32) -> int16x8x2_t; - } - _vld2q_dup_s16(a as *const i8, 2) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + vld1q_v16i8::(ptr as *const i8) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] #[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v2i32.p0")] - fn _vld2_dup_s32(ptr: *const i8, size: i32) -> int32x2x2_t; - } - _vld2_dup_s32(a as *const i8, 4) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + vld1_v4i16::(ptr as *const i8) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] #[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4i32.p0")] - fn _vld2q_dup_s32(ptr: *const i8, size: i32) -> int32x4x2_t; - } - _vld2q_dup_s32(a as *const i8, 4) -} -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2r))] -pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2r.v2f32.p0" - )] - fn _vld2_dup_f32(ptr: *const f32) -> float32x2x2_t; - } - _vld2_dup_f32(a as _) -} -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2r))] -pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2r.v4f32.p0" - )] - fn _vld2q_dup_f32(ptr: *const f32) -> float32x4x2_t; - } - _vld2q_dup_f32(a as _) -} -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2r))] -pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2r.v8i8.p0" - )] - fn _vld2_dup_s8(ptr: *const i8) -> int8x8x2_t; - } - _vld2_dup_s8(a as _) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + vld1q_v8i16::(ptr as *const i8) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2r))] -pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2r.v16i8.p0" - )] - fn _vld2q_dup_s8(ptr: *const i8) -> int8x16x2_t; - } - _vld2q_dup_s8(a as _) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] +pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + vld1_v2i32::(ptr as *const i8) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2r))] -pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2r.v4i16.p0" - )] - fn _vld2_dup_s16(ptr: *const i16) -> int16x4x2_t; - } - _vld2_dup_s16(a as _) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] +pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + vld1q_v4i32::(ptr as *const i8) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2r))] -pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2r.v8i16.p0" - )] - fn _vld2q_dup_s16(ptr: *const i16) -> int16x8x2_t; - } - _vld2q_dup_s16(a as _) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] +pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + vld1_v1i64::(ptr as *const i8) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2r))] -pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2r.v2i32.p0" - )] - fn _vld2_dup_s32(ptr: *const i32) -> int32x2x2_t; - } - _vld2_dup_s32(a as _) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))] +pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + vld1q_v2i64::(ptr as *const i8) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2r))] -pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2r.v4i32.p0" - )] - fn _vld2q_dup_s32(ptr: *const i32) -> int32x4x2_t; - } - _vld2q_dup_s32(a as _) -} -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20527,55 +20209,43 @@ pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_dup_p64(a: *const p64) -> poly64x1x2_t { - transmute(vld2_dup_s64(transmute(a))) -} -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v1i64.p0")] - fn _vld2_dup_s64(ptr: *const i8, size: i32) -> int64x1x2_t; - } - _vld2_dup_s64(a as *const i8, 8) +pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2r))] -pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2r.v1i64.p0" - )] - fn _vld2_dup_s64(ptr: *const i64) -> int64x1x2_t; - } - _vld2_dup_s64(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u64)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20585,21 +20255,20 @@ pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_dup_u64(a: *const u64) -> uint64x1x2_t { - transmute(vld2_dup_s64(transmute(a))) +pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20609,21 +20278,20 @@ pub unsafe fn vld2_dup_u64(a: *const u64) -> uint64x1x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t { - transmute(vld2_dup_s8(transmute(a))) +pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20633,24 +20301,20 @@ pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t { - let mut ret_val: uint8x8x2_t = transmute(vld2_dup_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20660,21 +20324,20 @@ pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t { - transmute(vld2q_dup_s8(transmute(a))) +pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20684,36 +20347,20 @@ pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t { - let mut ret_val: uint8x16x2_t = transmute(vld2q_dup_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20723,21 +20370,20 @@ pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t { - transmute(vld2_dup_s16(transmute(a))) +pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20747,24 +20393,20 @@ pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t { - let mut ret_val: uint16x4x2_t = transmute(vld2_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20774,21 +20416,20 @@ pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t { - transmute(vld2q_dup_s16(transmute(a))) +pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20798,24 +20439,20 @@ pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t { - let mut ret_val: uint16x8x2_t = transmute(vld2q_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20825,21 +20462,20 @@ pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t { - transmute(vld2_dup_s32(transmute(a))) +pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20849,24 +20485,20 @@ pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t { - let mut ret_val: uint32x2x2_t = transmute(vld2_dup_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val +pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20876,21 +20508,20 @@ pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t { - transmute(vld2q_dup_s32(transmute(a))) +pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20900,24 +20531,20 @@ pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t { - let mut ret_val: uint32x4x2_t = transmute(vld2q_dup_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20927,21 +20554,20 @@ pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t { - transmute(vld2_dup_s8(transmute(a))) +pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20951,24 +20577,20 @@ pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t { - let mut ret_val: poly8x8x2_t = transmute(vld2_dup_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20978,21 +20600,20 @@ pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t { - transmute(vld2q_dup_s8(transmute(a))) +pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21002,36 +20623,20 @@ pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t { - let mut ret_val: poly8x16x2_t = transmute(vld2q_dup_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21041,21 +20646,20 @@ pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t { - transmute(vld2_dup_s16(transmute(a))) +pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21065,24 +20669,20 @@ pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t { - let mut ret_val: poly16x4x2_t = transmute(vld2_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21092,21 +20692,20 @@ pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t { - transmute(vld2q_dup_s16(transmute(a))) +pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21116,812 +20715,665 @@ pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t { - let mut ret_val: poly16x8x2_t = transmute(vld2q_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4f16.p0")] - fn _vld2_f16(ptr: *const f16, size: i32) -> float16x4x2_t; - } - _vld2_f16(a as _, 2) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8f16.p0")] - fn _vld2q_f16(ptr: *const f16, size: i32) -> float16x8x2_t; - } - _vld2q_f16(a as _, 2) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld) )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v4f16.p0" - )] - fn _vld2_f16(ptr: *const f16) -> float16x4x2_t; - } - _vld2_f16(a as _) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld) )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v8f16.p0" - )] - fn _vld2q_f16(ptr: *const f16) -> float16x8x2_t; - } - _vld2q_f16(a as _) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v2f32")] - fn _vld2_f32(ptr: *const i8, size: i32) -> float32x2x2_t; - } - _vld2_f32(a as *const i8, 4) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4f32")] - fn _vld2q_f32(ptr: *const i8, size: i32) -> float32x4x2_t; - } - _vld2q_f32(a as *const i8, 4) +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8i8")] - fn _vld2_s8(ptr: *const i8, size: i32) -> int8x8x2_t; - } - _vld2_s8(a as *const i8, 1) +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v16i8")] - fn _vld2q_s8(ptr: *const i8, size: i32) -> int8x16x2_t; - } - _vld2q_s8(a as *const i8, 1) +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4i16")] - fn _vld2_s16(ptr: *const i8, size: i32) -> int16x4x2_t; - } - _vld2_s16(a as *const i8, 2) +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8i16")] - fn _vld2q_s16(ptr: *const i8, size: i32) -> int16x8x2_t; - } - _vld2q_s16(a as *const i8, 2) +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v2i32")] - fn _vld2_s32(ptr: *const i8, size: i32) -> int32x2x2_t; - } - _vld2_s32(a as *const i8, 4) +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4i32")] - fn _vld2q_s32(ptr: *const i8, size: i32) -> int32x4x2_t; - } - _vld2q_s32(a as *const i8, 4) +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2))] -pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v2f32.p0" - )] - fn _vld2_f32(ptr: *const float32x2_t) -> float32x2x2_t; - } - _vld2_f32(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2))] -pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v4f32.p0" - )] - fn _vld2q_f32(ptr: *const float32x4_t) -> float32x4x2_t; - } - _vld2q_f32(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2))] -pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v8i8.p0" - )] - fn _vld2_s8(ptr: *const int8x8_t) -> int8x8x2_t; - } - _vld2_s8(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2))] -pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v16i8.p0" - )] - fn _vld2q_s8(ptr: *const int8x16_t) -> int8x16x2_t; - } - _vld2q_s8(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2))] -pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v4i16.p0" - )] - fn _vld2_s16(ptr: *const int16x4_t) -> int16x4x2_t; - } - _vld2_s16(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2))] -pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v8i16.p0" - )] - fn _vld2q_s16(ptr: *const int16x8_t) -> int16x8x2_t; - } - _vld2q_s16(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2))] -pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v2i32.p0" - )] - fn _vld2_s32(ptr: *const int32x2_t) -> int32x2x2_t; - } - _vld2_s32(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2))] -pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v4i32.p0" - )] - fn _vld2q_s32(ptr: *const int32x4_t) -> int32x4x2_t; - } - _vld2q_s32(a as _) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2_lane_f16(a: *const f16, b: float16x4x2_t) -> float16x4x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4f16.p0")] - fn _vld2_lane_f16( - ptr: *const f16, - a: float16x4_t, - b: float16x4_t, - n: i32, - size: i32, - ) -> float16x4x2_t; - } - _vld2_lane_f16(a as _, b.0, b.1, LANE, 2) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2q_lane_f16(a: *const f16, b: float16x8x2_t) -> float16x8x2_t { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8f16.p0")] - fn _vld2q_lane_f16( - ptr: *const f16, - a: float16x8_t, - b: float16x8_t, - n: i32, - size: i32, - ) -> float16x8x2_t; - } - _vld2q_lane_f16(a as _, b.0, b.1, LANE, 2) +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2, LANE = 0) + assert_instr(ld) )] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2_lane_f16(a: *const f16, b: float16x4x2_t) -> float16x4x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2lane.v4f16.p0" - )] - fn _vld2_lane_f16(a: float16x4_t, b: float16x4_t, n: i64, ptr: *const f16) - -> float16x4x2_t; - } - _vld2_lane_f16(b.0, b.1, LANE as i64, a as _) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2, LANE = 0) + assert_instr(ld) )] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2q_lane_f16(a: *const f16, b: float16x8x2_t) -> float16x8x2_t { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2lane.v8f16.p0" - )] - fn _vld2q_lane_f16( - a: float16x8_t, - b: float16x8_t, - n: i64, - ptr: *const f16, - ) -> float16x8x2_t; - } - _vld2q_lane_f16(b.0, b.1, LANE as i64, a as _) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_lane_f32(a: *const f32, b: float32x2x2_t) -> float32x2x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2lane.v2f32.p0" - )] - fn _vld2_lane_f32(a: float32x2_t, b: float32x2_t, n: i64, ptr: *const i8) -> float32x2x2_t; - } - _vld2_lane_f32(b.0, b.1, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_lane_f32(a: *const f32, b: float32x4x2_t) -> float32x4x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2lane.v4f32.p0" - )] - fn _vld2q_lane_f32(a: float32x4_t, b: float32x4_t, n: i64, ptr: *const i8) - -> float32x4x2_t; - } - _vld2q_lane_f32(b.0, b.1, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_lane_s8(a: *const i8, b: int8x8x2_t) -> int8x8x2_t { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2lane.v8i8.p0" - )] - fn _vld2_lane_s8(a: int8x8_t, b: int8x8_t, n: i64, ptr: *const i8) -> int8x8x2_t; - } - _vld2_lane_s8(b.0, b.1, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_lane_s16(a: *const i16, b: int16x4x2_t) -> int16x4x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2lane.v4i16.p0" - )] - fn _vld2_lane_s16(a: int16x4_t, b: int16x4_t, n: i64, ptr: *const i8) -> int16x4x2_t; - } - _vld2_lane_s16(b.0, b.1, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_lane_s16(a: *const i16, b: int16x8x2_t) -> int16x8x2_t { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2lane.v8i16.p0" - )] - fn _vld2q_lane_s16(a: int16x8_t, b: int16x8_t, n: i64, ptr: *const i8) -> int16x8x2_t; - } - _vld2q_lane_s16(b.0, b.1, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_lane_s32(a: *const i32, b: int32x2x2_t) -> int32x2x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2lane.v2i32.p0" - )] - fn _vld2_lane_s32(a: int32x2_t, b: int32x2_t, n: i64, ptr: *const i8) -> int32x2x2_t; - } - _vld2_lane_s32(b.0, b.1, LANE as i64, a as _) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_lane_s32(a: *const i32, b: int32x4x2_t) -> int32x4x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2lane.v4i32.p0" - )] - fn _vld2q_lane_s32(a: int32x4_t, b: int32x4_t, n: i64, ptr: *const i8) -> int32x4x2_t; - } - _vld2q_lane_s32(b.0, b.1, LANE as i64, a as _) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2_lane_f32(a: *const f32, b: float32x2x2_t) -> float32x2x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v2f32.p0")] - fn _vld2_lane_f32( - ptr: *const i8, - a: float32x2_t, - b: float32x2_t, - n: i32, - size: i32, - ) -> float32x2x2_t; - } - _vld2_lane_f32(a as _, b.0, b.1, LANE, 4) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2q_lane_f32(a: *const f32, b: float32x4x2_t) -> float32x4x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4f32.p0")] - fn _vld2q_lane_f32( - ptr: *const i8, - a: float32x4_t, - b: float32x4_t, - n: i32, - size: i32, - ) -> float32x4x2_t; - } - _vld2q_lane_f32(a as _, b.0, b.1, LANE, 4) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2q_lane_s16(a: *const i16, b: int16x8x2_t) -> int16x8x2_t { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8i16.p0")] - fn _vld2q_lane_s16( - ptr: *const i8, - a: int16x8_t, - b: int16x8_t, - n: i32, - size: i32, - ) -> int16x8x2_t; - } - _vld2q_lane_s16(a as _, b.0, b.1, LANE, 2) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2q_lane_s32(a: *const i32, b: int32x4x2_t) -> int32x4x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4i32.p0")] - fn _vld2q_lane_s32( - ptr: *const i8, - a: int32x4_t, - b: int32x4_t, - n: i32, - size: i32, - ) -> int32x4x2_t; - } - _vld2q_lane_s32(a as _, b.0, b.1, LANE, 4) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2_lane_s8(a: *const i8, b: int8x8x2_t) -> int8x8x2_t { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8i8.p0")] - fn _vld2_lane_s8(ptr: *const i8, a: int8x8_t, b: int8x8_t, n: i32, size: i32) - -> int8x8x2_t; - } - _vld2_lane_s8(a as _, b.0, b.1, LANE, 1) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2_lane_s16(a: *const i16, b: int16x4x2_t) -> int16x4x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4i16.p0")] - fn _vld2_lane_s16( - ptr: *const i8, - a: int16x4_t, - b: int16x4_t, - n: i32, - size: i32, - ) -> int16x4x2_t; - } - _vld2_lane_s16(a as _, b.0, b.1, LANE, 2) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2_lane_s32(a: *const i32, b: int32x2x2_t) -> int32x2x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v2i32.p0")] - fn _vld2_lane_s32( - ptr: *const i8, - a: int32x2_t, - b: int32x2_t, - n: i32, - size: i32, - ) -> int32x2x2_t; - } - _vld2_lane_s32(a as _, b.0, b.1, LANE, 4) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2, LANE = 0) + assert_instr(ld) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -21930,23 +21382,21 @@ pub unsafe fn vld2_lane_s32(a: *const i32, b: int32x2x2_t) -> i target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_lane_u8(a: *const u8, b: uint8x8x2_t) -> uint8x8x2_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld2_lane_s8::(transmute(a), transmute(b))) +pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2, LANE = 0) + assert_instr(ld) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -21955,23 +21405,21 @@ pub unsafe fn vld2_lane_u8(a: *const u8, b: uint8x8x2_t) -> uin target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_lane_u16(a: *const u16, b: uint16x4x2_t) -> uint16x4x2_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld2_lane_s16::(transmute(a), transmute(b))) +pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2, LANE = 0) + assert_instr(ld) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -21980,23 +21428,21 @@ pub unsafe fn vld2_lane_u16(a: *const u16, b: uint16x4x2_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_lane_u16(a: *const u16, b: uint16x8x2_t) -> uint16x8x2_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld2q_lane_s16::(transmute(a), transmute(b))) +pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2, LANE = 0) + assert_instr(ld) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -22005,23 +21451,21 @@ pub unsafe fn vld2q_lane_u16(a: *const u16, b: uint16x8x2_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_lane_u32(a: *const u32, b: uint32x2x2_t) -> uint32x2x2_t { - static_assert_uimm_bits!(LANE, 1); - transmute(vld2_lane_s32::(transmute(a), transmute(b))) +pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2, LANE = 0) + assert_instr(ld) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -22030,23 +21474,21 @@ pub unsafe fn vld2_lane_u32(a: *const u32, b: uint32x2x2_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_lane_u32(a: *const u32, b: uint32x4x2_t) -> uint32x4x2_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld2q_lane_s32::(transmute(a), transmute(b))) +pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2, LANE = 0) + assert_instr(ld) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -22055,23 +21497,21 @@ pub unsafe fn vld2q_lane_u32(a: *const u32, b: uint32x4x2_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_lane_p8(a: *const p8, b: poly8x8x2_t) -> poly8x8x2_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld2_lane_s8::(transmute(a), transmute(b))) +pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2, LANE = 0) + assert_instr(ld) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -22080,23 +21520,21 @@ pub unsafe fn vld2_lane_p8(a: *const p8, b: poly8x8x2_t) -> pol target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_lane_p16(a: *const p16, b: poly16x4x2_t) -> poly16x4x2_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld2_lane_s16::(transmute(a), transmute(b))) +pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2, LANE = 0) + assert_instr(ld) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -22105,21 +21543,20 @@ pub unsafe fn vld2_lane_p16(a: *const p16, b: poly16x4x2_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_lane_p16(a: *const p16, b: poly16x8x2_t) -> poly16x8x2_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld2q_lane_s16::(transmute(a), transmute(b))) +pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p64)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -22129,55 +21566,178 @@ pub unsafe fn vld2q_lane_p16(a: *const p16, b: poly16x8x2_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_p64(a: *const p64) -> poly64x1x2_t { - transmute(vld2_s64(transmute(a))) +pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] +#[rustc_legacy_const_generics(1)] +#[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +unsafe fn vld1_v1i64(a: *const i8) -> int64x1_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v1i64")] + fn _vld1_v1i64(a: *const i8, b: i32) -> int64x1_t; + } + _vld1_v1i64(a, ALIGN) +} +#[inline] +#[rustc_legacy_const_generics(1)] #[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t { +unsafe fn vld1_v2f32(a: *const i8) -> float32x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v1i64")] - fn _vld2_s64(ptr: *const i8, size: i32) -> int64x1x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2f32")] + fn _vld1_v2f32(a: *const i8, b: i32) -> float32x2_t; } - _vld2_s64(a as *const i8, 8) + _vld1_v2f32(a, ALIGN) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t { +#[inline] +#[rustc_legacy_const_generics(1)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +unsafe fn vld1_v2i32(a: *const i8) -> int32x2_t { unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v1i64.p0" - )] - fn _vld2_s64(ptr: *const int64x1_t) -> int64x1x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2i32")] + fn _vld1_v2i32(a: *const i8, b: i32) -> int32x2_t; } - _vld2_s64(a as _) + _vld1_v2i32(a, ALIGN) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u64)"] +#[inline] +#[rustc_legacy_const_generics(1)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +unsafe fn vld1_v4i16(a: *const i8) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4i16")] + fn _vld1_v4i16(a: *const i8, b: i32) -> int16x4_t; + } + _vld1_v4i16(a, ALIGN) +} +#[inline] +#[rustc_legacy_const_generics(1)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +unsafe fn vld1_v8i8(a: *const i8) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8i8")] + fn _vld1_v8i8(a: *const i8, b: i32) -> int8x8_t; + } + _vld1_v8i8(a, ALIGN) +} +#[inline] +#[rustc_legacy_const_generics(1)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +unsafe fn vld1q_v16i8(a: *const i8) -> int8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v16i8")] + fn _vld1q_v16i8(a: *const i8, b: i32) -> int8x16_t; + } + _vld1q_v16i8(a, ALIGN) +} +#[inline] +#[rustc_legacy_const_generics(1)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +unsafe fn vld1q_v2i64(a: *const i8) -> int64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2i64")] + fn _vld1q_v2i64(a: *const i8, b: i32) -> int64x2_t; + } + _vld1q_v2i64(a, ALIGN) +} +#[inline] +#[rustc_legacy_const_generics(1)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +unsafe fn vld1q_v4f32(a: *const i8) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4f32")] + fn _vld1q_v4f32(a: *const i8, b: i32) -> float32x4_t; + } + _vld1q_v4f32(a, ALIGN) +} +#[inline] +#[rustc_legacy_const_generics(1)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +unsafe fn vld1q_v4i32(a: *const i8) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4i32")] + fn _vld1q_v4i32(a: *const i8, b: i32) -> int32x4_t; + } + _vld1q_v4i32(a, ALIGN) +} +#[inline] +#[rustc_legacy_const_generics(1)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +unsafe fn vld1q_v8i16(a: *const i8) -> int16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8i16")] + fn _vld1q_v8i16(a: *const i8, b: i32) -> int16x8_t; + } + _vld1q_v8i16(a, ALIGN) +} +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg(not(target_arch = "arm64ec"))] +unsafe fn vld1_v4f16(a: *const i8, b: i32) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4f16")] + fn _vld1_v4f16(a: *const i8, b: i32) -> float16x4_t; + } + _vld1_v4f16(a, b) +} +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg(not(target_arch = "arm64ec"))] +unsafe fn vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8f16")] + fn _vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t; + } + _vld1q_v8f16(a, b) +} +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[inline] +#[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -22187,96 +21747,387 @@ pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t { - transmute(vld2_s64(transmute(a))) +pub unsafe fn vld1q_dup_p64(ptr: *const p64) -> poly64x2_t { + let x = vld1q_lane_p64::<0>(ptr, transmute(u64x2::splat(0))); + simd_shuffle!(x, x, [0, 0]) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t { - transmute(vld2_s8(transmute(a))) +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4f16.p0")] + fn _vld2_dup_f16(ptr: *const f16, size: i32) -> float16x4x2_t; + } + _vld2_dup_f16(a as _, 2) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t { - let mut ret_val: uint8x8x2_t = transmute(vld2_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8f16.p0")] + fn _vld2q_dup_f16(ptr: *const f16, size: i32) -> float16x8x2_t; + } + _vld2q_dup_f16(a as _, 2) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + assert_instr(ld2r) )] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v4f16.p0" + )] + fn _vld2_dup_f16(ptr: *const f16) -> float16x4x2_t; + } + _vld2_dup_f16(a as _) +} +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] #[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2r) )] -pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t { - transmute(vld2q_s8(transmute(a))) +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v8f16.p0" + )] + fn _vld2q_dup_f16(ptr: *const f16) -> float16x8x2_t; + } + _vld2q_dup_f16(a as _) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v2f32.p0")] + fn _vld2_dup_f32(ptr: *const i8, size: i32) -> float32x2x2_t; + } + _vld2_dup_f32(a as *const i8, 4) +} +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4f32.p0")] + fn _vld2q_dup_f32(ptr: *const i8, size: i32) -> float32x4x2_t; + } + _vld2q_dup_f32(a as *const i8, 4) +} +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8i8.p0")] + fn _vld2_dup_s8(ptr: *const i8, size: i32) -> int8x8x2_t; + } + _vld2_dup_s8(a as *const i8, 1) +} +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v16i8.p0")] + fn _vld2q_dup_s8(ptr: *const i8, size: i32) -> int8x16x2_t; + } + _vld2q_dup_s8(a as *const i8, 1) +} +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4i16.p0")] + fn _vld2_dup_s16(ptr: *const i8, size: i32) -> int16x4x2_t; + } + _vld2_dup_s16(a as *const i8, 2) +} +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8i16.p0")] + fn _vld2q_dup_s16(ptr: *const i8, size: i32) -> int16x8x2_t; + } + _vld2q_dup_s16(a as *const i8, 2) +} +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v2i32.p0")] + fn _vld2_dup_s32(ptr: *const i8, size: i32) -> int32x2x2_t; + } + _vld2_dup_s32(a as *const i8, 4) +} +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4i32.p0")] + fn _vld2q_dup_s32(ptr: *const i8, size: i32) -> int32x4x2_t; + } + _vld2q_dup_s32(a as *const i8, 4) +} +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v2f32.p0" + )] + fn _vld2_dup_f32(ptr: *const f32) -> float32x2x2_t; + } + _vld2_dup_f32(a as _) +} +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v4f32.p0" + )] + fn _vld2q_dup_f32(ptr: *const f32) -> float32x4x2_t; + } + _vld2q_dup_f32(a as _) +} +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v8i8.p0" + )] + fn _vld2_dup_s8(ptr: *const i8) -> int8x8x2_t; + } + _vld2_dup_s8(a as _) +} +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v16i8.p0" + )] + fn _vld2q_dup_s8(ptr: *const i8) -> int8x16x2_t; + } + _vld2q_dup_s8(a as _) +} +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v4i16.p0" + )] + fn _vld2_dup_s16(ptr: *const i16) -> int16x4x2_t; + } + _vld2_dup_s16(a as _) +} +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v8i16.p0" + )] + fn _vld2q_dup_s16(ptr: *const i16) -> int16x8x2_t; + } + _vld2q_dup_s16(a as _) +} +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v2i32.p0" + )] + fn _vld2_dup_s32(ptr: *const i32) -> int32x2x2_t; + } + _vld2_dup_s32(a as _) +} +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v4i32.p0" + )] + fn _vld2q_dup_s32(ptr: *const i32) -> int32x4x2_t; + } + _vld2q_dup_s32(a as _) +} +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld2r) )] #[cfg_attr( not(target_arch = "arm"), @@ -22286,36 +22137,55 @@ pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t { - let mut ret_val: uint8x16x2_t = transmute(vld2q_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld2_dup_p64(a: *const p64) -> poly64x1x2_t { + transmute(vld2_dup_s64(transmute(a))) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v1i64.p0")] + fn _vld2_dup_s64(ptr: *const i8, size: i32) -> int64x1x2_t; + } + _vld2_dup_s64(a as *const i8, 8) +} +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v1i64.p0" + )] + fn _vld2_dup_s64(ptr: *const i64) -> int64x1x2_t; + } + _vld2_dup_s64(a as _) +} +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld2r) )] #[cfg_attr( not(target_arch = "arm"), @@ -22325,21 +22195,20 @@ pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t { - transmute(vld2_s16(transmute(a))) +pub unsafe fn vld2_dup_u64(a: *const u64) -> uint64x1x2_t { + transmute(vld2_dup_s64(transmute(a))) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld2r) )] #[cfg_attr( not(target_arch = "arm"), @@ -22349,24 +22218,20 @@ pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t { - let mut ret_val: uint16x4x2_t = transmute(vld2_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t { + transmute(vld2_dup_s8(transmute(a))) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld2r) )] #[cfg_attr( not(target_arch = "arm"), @@ -22376,21 +22241,20 @@ pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t { - transmute(vld2q_s16(transmute(a))) +pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t { + transmute(vld2q_dup_s8(transmute(a))) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld2r) )] #[cfg_attr( not(target_arch = "arm"), @@ -22400,24 +22264,20 @@ pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t { - let mut ret_val: uint16x8x2_t = transmute(vld2q_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t { + transmute(vld2_dup_s16(transmute(a))) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld2r) )] #[cfg_attr( not(target_arch = "arm"), @@ -22427,21 +22287,20 @@ pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t { - transmute(vld2_s32(transmute(a))) +pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t { + transmute(vld2q_dup_s16(transmute(a))) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld2r) )] #[cfg_attr( not(target_arch = "arm"), @@ -22451,24 +22310,20 @@ pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t { - let mut ret_val: uint32x2x2_t = transmute(vld2_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val +pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t { + transmute(vld2_dup_s32(transmute(a))) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld2r) )] #[cfg_attr( not(target_arch = "arm"), @@ -22478,21 +22333,20 @@ pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t { - transmute(vld2q_s32(transmute(a))) +pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t { + transmute(vld2q_dup_s32(transmute(a))) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld2r) )] #[cfg_attr( not(target_arch = "arm"), @@ -22502,24 +22356,20 @@ pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t { - let mut ret_val: uint32x4x2_t = transmute(vld2q_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t { + transmute(vld2_dup_s8(transmute(a))) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld2r) )] #[cfg_attr( not(target_arch = "arm"), @@ -22529,21 +22379,20 @@ pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t { - transmute(vld2_s8(transmute(a))) +pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t { + transmute(vld2q_dup_s8(transmute(a))) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld2r) )] #[cfg_attr( not(target_arch = "arm"), @@ -22553,24 +22402,20 @@ pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t { - let mut ret_val: poly8x8x2_t = transmute(vld2_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t { + transmute(vld2_dup_s16(transmute(a))) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld2r) )] #[cfg_attr( not(target_arch = "arm"), @@ -22580,610 +22425,809 @@ pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t { - transmute(vld2q_s8(transmute(a))) +pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t { + transmute(vld2q_dup_s16(transmute(a))) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t { - let mut ret_val: poly8x16x2_t = transmute(vld2q_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t { - transmute(vld2_s16(transmute(a))) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t { - let mut ret_val: poly16x4x2_t = transmute(vld2_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t { - transmute(vld2q_s16(transmute(a))) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t { - let mut ret_val: poly16x8x2_t = transmute(vld2q_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t { +pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4f16.p0")] - fn _vld3_dup_f16(ptr: *const f16, size: i32) -> float16x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4f16.p0")] + fn _vld2_f16(ptr: *const f16, size: i32) -> float16x4x2_t; } - _vld3_dup_f16(a as _, 2) + _vld2_f16(a as _, 2) } -#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t { +pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8f16.p0")] - fn _vld3q_dup_f16(ptr: *const f16, size: i32) -> float16x8x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8f16.p0")] + fn _vld2q_f16(ptr: *const f16, size: i32) -> float16x8x2_t; } - _vld3q_dup_f16(a as _, 2) + _vld2q_f16(a as _, 2) } -#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld2) )] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t { +pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3r.v4f16.p0" + link_name = "llvm.aarch64.neon.ld2.v4f16.p0" )] - fn _vld3_dup_f16(ptr: *const f16) -> float16x4x3_t; + fn _vld2_f16(ptr: *const f16) -> float16x4x2_t; } - _vld3_dup_f16(a as _) + _vld2_f16(a as _) } -#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld2) )] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t { +pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3r.v8f16.p0" + link_name = "llvm.aarch64.neon.ld2.v8f16.p0" )] - fn _vld3q_dup_f16(ptr: *const f16) -> float16x8x3_t; + fn _vld2q_f16(ptr: *const f16) -> float16x8x2_t; } - _vld3q_dup_f16(a as _) + _vld2q_f16(a as _) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3r))] -pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t { +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t { unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3r.v2f32.p0" - )] - fn _vld3_dup_f32(ptr: *const f32) -> float32x2x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v2f32")] + fn _vld2_f32(ptr: *const i8, size: i32) -> float32x2x2_t; } - _vld3_dup_f32(a as _) + _vld2_f32(a as *const i8, 4) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4f32")] + fn _vld2q_f32(ptr: *const i8, size: i32) -> float32x4x2_t; + } + _vld2q_f32(a as *const i8, 4) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8i8")] + fn _vld2_s8(ptr: *const i8, size: i32) -> int8x8x2_t; + } + _vld2_s8(a as *const i8, 1) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v16i8")] + fn _vld2q_s8(ptr: *const i8, size: i32) -> int8x16x2_t; + } + _vld2q_s8(a as *const i8, 1) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4i16")] + fn _vld2_s16(ptr: *const i8, size: i32) -> int16x4x2_t; + } + _vld2_s16(a as *const i8, 2) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8i16")] + fn _vld2q_s16(ptr: *const i8, size: i32) -> int16x8x2_t; + } + _vld2q_s16(a as *const i8, 2) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v2i32")] + fn _vld2_s32(ptr: *const i8, size: i32) -> int32x2x2_t; + } + _vld2_s32(a as *const i8, 4) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4i32")] + fn _vld2q_s32(ptr: *const i8, size: i32) -> int32x4x2_t; + } + _vld2q_s32(a as *const i8, 4) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3r))] -pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t { +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3r.v4f32.p0" + link_name = "llvm.aarch64.neon.ld2.v2f32.p0" )] - fn _vld3q_dup_f32(ptr: *const f32) -> float32x4x3_t; + fn _vld2_f32(ptr: *const float32x2_t) -> float32x2x2_t; } - _vld3q_dup_f32(a as _) + _vld2_f32(a as _) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3r))] -pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t { +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3r.v8i8.p0" + link_name = "llvm.aarch64.neon.ld2.v4f32.p0" )] - fn _vld3_dup_s8(ptr: *const i8) -> int8x8x3_t; + fn _vld2q_f32(ptr: *const float32x4_t) -> float32x4x2_t; } - _vld3_dup_s8(a as _) + _vld2q_f32(a as _) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3r))] -pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t { +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3r.v16i8.p0" + link_name = "llvm.aarch64.neon.ld2.v8i8.p0" )] - fn _vld3q_dup_s8(ptr: *const i8) -> int8x16x3_t; + fn _vld2_s8(ptr: *const int8x8_t) -> int8x8x2_t; } - _vld3q_dup_s8(a as _) + _vld2_s8(a as _) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3r))] -pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t { +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3r.v4i16.p0" + link_name = "llvm.aarch64.neon.ld2.v16i8.p0" )] - fn _vld3_dup_s16(ptr: *const i16) -> int16x4x3_t; + fn _vld2q_s8(ptr: *const int8x16_t) -> int8x16x2_t; } - _vld3_dup_s16(a as _) + _vld2q_s8(a as _) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3r))] -pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t { +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3r.v8i16.p0" + link_name = "llvm.aarch64.neon.ld2.v4i16.p0" )] - fn _vld3q_dup_s16(ptr: *const i16) -> int16x8x3_t; + fn _vld2_s16(ptr: *const int16x4_t) -> int16x4x2_t; } - _vld3q_dup_s16(a as _) + _vld2_s16(a as _) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3r))] -pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t { +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3r.v2i32.p0" + link_name = "llvm.aarch64.neon.ld2.v8i16.p0" )] - fn _vld3_dup_s32(ptr: *const i32) -> int32x2x3_t; + fn _vld2q_s16(ptr: *const int16x8_t) -> int16x8x2_t; } - _vld3_dup_s32(a as _) + _vld2q_s16(a as _) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3r))] -pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t { +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3r.v4i32.p0" + link_name = "llvm.aarch64.neon.ld2.v2i32.p0" )] - fn _vld3q_dup_s32(ptr: *const i32) -> int32x4x3_t; + fn _vld2_s32(ptr: *const int32x2_t) -> int32x2x2_t; } - _vld3q_dup_s32(a as _) + _vld2_s32(a as _) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3r))] -pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t { +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3r.v1i64.p0" + link_name = "llvm.aarch64.neon.ld2.v4i32.p0" )] - fn _vld3_dup_s64(ptr: *const i64) -> int64x1x3_t; + fn _vld2q_s32(ptr: *const int32x4_t) -> int32x4x2_t; } - _vld3_dup_s64(a as _) + _vld2q_s32(a as _) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld2_lane_f16(a: *const f16, b: float16x4x2_t) -> float16x4x2_t { + static_assert_uimm_bits!(LANE, 2); unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v2f32.p0")] - fn _vld3_dup_f32(ptr: *const i8, size: i32) -> float32x2x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4f16.p0")] + fn _vld2_lane_f16( + ptr: *const f16, + a: float16x4_t, + b: float16x4_t, + n: i32, + size: i32, + ) -> float16x4x2_t; } - _vld3_dup_f32(a as *const i8, 4) + _vld2_lane_f16(a as _, b.0, b.1, LANE, 2) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld2q_lane_f16(a: *const f16, b: float16x8x2_t) -> float16x8x2_t { + static_assert_uimm_bits!(LANE, 3); unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4f32.p0")] - fn _vld3q_dup_f32(ptr: *const i8, size: i32) -> float32x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8f16.p0")] + fn _vld2q_lane_f16( + ptr: *const f16, + a: float16x8_t, + b: float16x8_t, + n: i32, + size: i32, + ) -> float16x8x2_t; } - _vld3q_dup_f32(a as *const i8, 4) + _vld2q_lane_f16(a as _, b.0, b.1, LANE, 2) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t { +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld2_lane_f16(a: *const f16, b: float16x4x2_t) -> float16x4x2_t { + static_assert_uimm_bits!(LANE, 2); unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8i8.p0")] - fn _vld3_dup_s8(ptr: *const i8, size: i32) -> int8x8x3_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v4f16.p0" + )] + fn _vld2_lane_f16(a: float16x4_t, b: float16x4_t, n: i64, ptr: *const f16) + -> float16x4x2_t; } - _vld3_dup_s8(a as *const i8, 1) + _vld2_lane_f16(b.0, b.1, LANE as i64, a as _) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v16i8.p0")] - fn _vld3q_dup_s8(ptr: *const i8, size: i32) -> int8x16x3_t; +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld2q_lane_f16(a: *const f16, b: float16x8x2_t) -> float16x8x2_t { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v8f16.p0" + )] + fn _vld2q_lane_f16( + a: float16x8_t, + b: float16x8_t, + n: i64, + ptr: *const f16, + ) -> float16x8x2_t; } - _vld3q_dup_s8(a as *const i8, 1) + _vld2q_lane_f16(b.0, b.1, LANE as i64, a as _) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld2_lane_f32(a: *const f32, b: float32x2x2_t) -> float32x2x2_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v2f32.p0" + )] + fn _vld2_lane_f32(a: float32x2_t, b: float32x2_t, n: i64, ptr: *const i8) -> float32x2x2_t; + } + _vld2_lane_f32(b.0, b.1, LANE as i64, a as _) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld2q_lane_f32(a: *const f32, b: float32x4x2_t) -> float32x4x2_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v4f32.p0" + )] + fn _vld2q_lane_f32(a: float32x4_t, b: float32x4_t, n: i64, ptr: *const i8) + -> float32x4x2_t; + } + _vld2q_lane_f32(b.0, b.1, LANE as i64, a as _) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld2_lane_s8(a: *const i8, b: int8x8x2_t) -> int8x8x2_t { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v8i8.p0" + )] + fn _vld2_lane_s8(a: int8x8_t, b: int8x8_t, n: i64, ptr: *const i8) -> int8x8x2_t; + } + _vld2_lane_s8(b.0, b.1, LANE as i64, a as _) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld2_lane_s16(a: *const i16, b: int16x4x2_t) -> int16x4x2_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v4i16.p0" + )] + fn _vld2_lane_s16(a: int16x4_t, b: int16x4_t, n: i64, ptr: *const i8) -> int16x4x2_t; + } + _vld2_lane_s16(b.0, b.1, LANE as i64, a as _) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld2q_lane_s16(a: *const i16, b: int16x8x2_t) -> int16x8x2_t { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v8i16.p0" + )] + fn _vld2q_lane_s16(a: int16x8_t, b: int16x8_t, n: i64, ptr: *const i8) -> int16x8x2_t; + } + _vld2q_lane_s16(b.0, b.1, LANE as i64, a as _) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld2_lane_s32(a: *const i32, b: int32x2x2_t) -> int32x2x2_t { + static_assert_uimm_bits!(LANE, 1); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v2i32.p0" + )] + fn _vld2_lane_s32(a: int32x2_t, b: int32x2_t, n: i64, ptr: *const i8) -> int32x2x2_t; + } + _vld2_lane_s32(b.0, b.1, LANE as i64, a as _) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld2q_lane_s32(a: *const i32, b: int32x4x2_t) -> int32x4x2_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v4i32.p0" + )] + fn _vld2q_lane_s32(a: int32x4_t, b: int32x4_t, n: i64, ptr: *const i8) -> int32x4x2_t; + } + _vld2q_lane_s32(b.0, b.1, LANE as i64, a as _) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t { +pub unsafe fn vld2_lane_f32(a: *const f32, b: float32x2x2_t) -> float32x2x2_t { + static_assert_uimm_bits!(LANE, 1); unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4i16.p0")] - fn _vld3_dup_s16(ptr: *const i8, size: i32) -> int16x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v2f32.p0")] + fn _vld2_lane_f32( + ptr: *const i8, + a: float32x2_t, + b: float32x2_t, + n: i32, + size: i32, + ) -> float32x2x2_t; } - _vld3_dup_s16(a as *const i8, 2) + _vld2_lane_f32(a as _, b.0, b.1, LANE, 4) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t { +pub unsafe fn vld2q_lane_f32(a: *const f32, b: float32x4x2_t) -> float32x4x2_t { + static_assert_uimm_bits!(LANE, 2); unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8i16.p0")] - fn _vld3q_dup_s16(ptr: *const i8, size: i32) -> int16x8x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4f32.p0")] + fn _vld2q_lane_f32( + ptr: *const i8, + a: float32x4_t, + b: float32x4_t, + n: i32, + size: i32, + ) -> float32x4x2_t; } - _vld3q_dup_s16(a as *const i8, 2) + _vld2q_lane_f32(a as _, b.0, b.1, LANE, 4) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t { +pub unsafe fn vld2q_lane_s16(a: *const i16, b: int16x8x2_t) -> int16x8x2_t { + static_assert_uimm_bits!(LANE, 3); unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v2i32.p0")] - fn _vld3_dup_s32(ptr: *const i8, size: i32) -> int32x2x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8i16.p0")] + fn _vld2q_lane_s16( + ptr: *const i8, + a: int16x8_t, + b: int16x8_t, + n: i32, + size: i32, + ) -> int16x8x2_t; } - _vld3_dup_s32(a as *const i8, 4) + _vld2q_lane_s16(a as _, b.0, b.1, LANE, 2) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t { +pub unsafe fn vld2q_lane_s32(a: *const i32, b: int32x4x2_t) -> int32x4x2_t { + static_assert_uimm_bits!(LANE, 2); unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4i32.p0")] - fn _vld3q_dup_s32(ptr: *const i8, size: i32) -> int32x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4i32.p0")] + fn _vld2q_lane_s32( + ptr: *const i8, + a: int32x4_t, + b: int32x4_t, + n: i32, + size: i32, + ) -> int32x4x2_t; } - _vld3q_dup_s32(a as *const i8, 4) + _vld2q_lane_s32(a as _, b.0, b.1, LANE, 4) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p64)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_dup_p64(a: *const p64) -> poly64x1x3_t { - transmute(vld3_dup_s64(transmute(a))) +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld2_lane_s8(a: *const i8, b: int8x8x2_t) -> int8x8x2_t { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8i8.p0")] + fn _vld2_lane_s8(ptr: *const i8, a: int8x8_t, b: int8x8_t, n: i32, size: i32) + -> int8x8x2_t; + } + _vld2_lane_s8(a as _, b.0, b.1, LANE, 1) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] +#[inline] #[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t { +pub unsafe fn vld2_lane_s16(a: *const i16, b: int16x4x2_t) -> int16x4x2_t { + static_assert_uimm_bits!(LANE, 2); unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v1i64.p0")] - fn _vld3_dup_s64(ptr: *const i8, size: i32) -> int64x1x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4i16.p0")] + fn _vld2_lane_s16( + ptr: *const i8, + a: int16x4_t, + b: int16x4_t, + n: i32, + size: i32, + ) -> int16x4x2_t; } - _vld3_dup_s64(a as *const i8, 8) + _vld2_lane_s16(a as _, b.0, b.1, LANE, 2) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u64)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_dup_u64(a: *const u64) -> uint64x1x3_t { - transmute(vld3_dup_s64(transmute(a))) +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld2_lane_s32(a: *const i32, b: int32x2x2_t) -> int32x2x2_t { + static_assert_uimm_bits!(LANE, 1); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v2i32.p0")] + fn _vld2_lane_s32( + ptr: *const i8, + a: int32x2_t, + b: int32x2_t, + n: i32, + size: i32, + ) -> int32x2x2_t; + } + _vld2_lane_s32(a as _, b.0, b.1, LANE, 4) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld2, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -23192,22 +23236,23 @@ pub unsafe fn vld3_dup_u64(a: *const u64) -> uint64x1x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t { - transmute(vld3_dup_s8(transmute(a))) +pub unsafe fn vld2_lane_u8(a: *const u8, b: uint8x8x2_t) -> uint8x8x2_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld2_lane_s8::(transmute(a), transmute(b))) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld2, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -23216,26 +23261,23 @@ pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t { - let mut ret_val: uint8x8x3_t = transmute(vld3_dup_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld2_lane_u16(a: *const u16, b: uint16x4x2_t) -> uint16x4x2_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld2_lane_s16::(transmute(a), transmute(b))) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld2, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -23244,22 +23286,23 @@ pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t { - transmute(vld3q_dup_s8(transmute(a))) +pub unsafe fn vld2q_lane_u16(a: *const u16, b: uint16x8x2_t) -> uint16x8x2_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld2q_lane_s16::(transmute(a), transmute(b))) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld2, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -23268,44 +23311,23 @@ pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t { - let mut ret_val: uint8x16x3_t = transmute(vld3q_dup_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld2_lane_u32(a: *const u32, b: uint32x2x2_t) -> uint32x2x2_t { + static_assert_uimm_bits!(LANE, 1); + transmute(vld2_lane_s32::(transmute(a), transmute(b))) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld2, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -23314,22 +23336,23 @@ pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t { - transmute(vld3_dup_s16(transmute(a))) +pub unsafe fn vld2q_lane_u32(a: *const u32, b: uint32x4x2_t) -> uint32x4x2_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld2q_lane_s32::(transmute(a), transmute(b))) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld2, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -23338,26 +23361,23 @@ pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t { - let mut ret_val: uint16x4x3_t = transmute(vld3_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld2_lane_p8(a: *const p8, b: poly8x8x2_t) -> poly8x8x2_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld2_lane_s8::(transmute(a), transmute(b))) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld2, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -23366,22 +23386,23 @@ pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t { - transmute(vld3q_dup_s16(transmute(a))) +pub unsafe fn vld2_lane_p16(a: *const p16, b: poly16x4x2_t) -> poly16x4x2_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld2_lane_s16::(transmute(a), transmute(b))) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld2, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -23390,25 +23411,21 @@ pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t { - let mut ret_val: uint16x8x3_t = transmute(vld3q_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld2q_lane_p16(a: *const p16, b: poly16x8x2_t) -> poly16x8x2_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld2q_lane_s16::(transmute(a), transmute(b))) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(nop) )] #[cfg_attr( not(target_arch = "arm"), @@ -23418,21 +23435,55 @@ pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t { - transmute(vld3_dup_s32(transmute(a))) +pub unsafe fn vld2_p64(a: *const p64) -> poly64x1x2_t { + transmute(vld2_s64(transmute(a))) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v1i64")] + fn _vld2_s64(ptr: *const i8, size: i32) -> int64x1x2_t; + } + _vld2_s64(a as *const i8, 8) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2.v1i64.p0" + )] + fn _vld2_s64(ptr: *const int64x1_t) -> int64x1x2_t; + } + _vld2_s64(a as _) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) )] #[cfg_attr( not(target_arch = "arm"), @@ -23442,25 +23493,20 @@ pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t { - let mut ret_val: uint32x2x3_t = transmute(vld3_dup_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val +pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t { + transmute(vld2_s64(transmute(a))) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld2) )] #[cfg_attr( not(target_arch = "arm"), @@ -23470,21 +23516,20 @@ pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t { - transmute(vld3q_dup_s32(transmute(a))) +pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t { + transmute(vld2_s8(transmute(a))) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld2) )] #[cfg_attr( not(target_arch = "arm"), @@ -23494,25 +23539,20 @@ pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t { - let mut ret_val: uint32x4x3_t = transmute(vld3q_dup_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t { + transmute(vld2q_s8(transmute(a))) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld2) )] #[cfg_attr( not(target_arch = "arm"), @@ -23522,21 +23562,20 @@ pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t { - transmute(vld3_dup_s8(transmute(a))) +pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t { + transmute(vld2_s16(transmute(a))) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld2) )] #[cfg_attr( not(target_arch = "arm"), @@ -23546,25 +23585,20 @@ pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t { - let mut ret_val: poly8x8x3_t = transmute(vld3_dup_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t { + transmute(vld2q_s16(transmute(a))) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld2) )] #[cfg_attr( not(target_arch = "arm"), @@ -23574,21 +23608,20 @@ pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t { - transmute(vld3q_dup_s8(transmute(a))) +pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t { + transmute(vld2_s32(transmute(a))) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld2) )] #[cfg_attr( not(target_arch = "arm"), @@ -23598,43 +23631,20 @@ pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t { - let mut ret_val: poly8x16x3_t = transmute(vld3q_dup_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t { + transmute(vld2q_s32(transmute(a))) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld2) )] #[cfg_attr( not(target_arch = "arm"), @@ -23644,21 +23654,20 @@ pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t { - transmute(vld3_dup_s16(transmute(a))) +pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t { + transmute(vld2_s8(transmute(a))) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld2) )] #[cfg_attr( not(target_arch = "arm"), @@ -23668,25 +23677,20 @@ pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t { - let mut ret_val: poly16x4x3_t = transmute(vld3_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t { + transmute(vld2q_s8(transmute(a))) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld2) )] #[cfg_attr( not(target_arch = "arm"), @@ -23696,21 +23700,20 @@ pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t { - transmute(vld3q_dup_s16(transmute(a))) +pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t { + transmute(vld2_s16(transmute(a))) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld2) )] #[cfg_attr( not(target_arch = "arm"), @@ -23720,18 +23723,14 @@ pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t { - let mut ret_val: poly16x8x3_t = transmute(vld3q_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t { + transmute(vld2q_s16(transmute(a))) } #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg(target_arch = "arm")] @@ -23739,18 +23738,18 @@ pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t { +pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4f16.p0")] - fn _vld3_f16(ptr: *const f16, size: i32) -> float16x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4f16.p0")] + fn _vld3_dup_f16(ptr: *const f16, size: i32) -> float16x4x3_t; } - _vld3_f16(a as _, 2) + _vld3_dup_f16(a as _, 2) } #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg(target_arch = "arm")] @@ -23758,811 +23757,411 @@ pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t { +pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8f16.p0")] - fn _vld3q_f16(ptr: *const f16, size: i32) -> float16x8x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8f16.p0")] + fn _vld3q_dup_f16(ptr: *const f16, size: i32) -> float16x8x3_t; } - _vld3q_f16(a as _, 2) + _vld3q_dup_f16(a as _, 2) } #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) + assert_instr(ld3r) )] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t { +pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v4f16.p0" + link_name = "llvm.aarch64.neon.ld3r.v4f16.p0" )] - fn _vld3_f16(ptr: *const f16) -> float16x4x3_t; + fn _vld3_dup_f16(ptr: *const f16) -> float16x4x3_t; } - _vld3_f16(a as _) + _vld3_dup_f16(a as _) } #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) + assert_instr(ld3r) )] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t { +pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v8f16.p0" + link_name = "llvm.aarch64.neon.ld3r.v8f16.p0" )] - fn _vld3q_f16(ptr: *const f16) -> float16x8x3_t; + fn _vld3q_dup_f16(ptr: *const f16) -> float16x8x3_t; } - _vld3q_f16(a as _) + _vld3q_dup_f16(a as _) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3))] -pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t { +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v2f32.p0" + link_name = "llvm.aarch64.neon.ld3r.v2f32.p0" )] - fn _vld3_f32(ptr: *const float32x2_t) -> float32x2x3_t; + fn _vld3_dup_f32(ptr: *const f32) -> float32x2x3_t; } - _vld3_f32(a as _) + _vld3_dup_f32(a as _) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3))] -pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t { +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v4f32.p0" + link_name = "llvm.aarch64.neon.ld3r.v4f32.p0" )] - fn _vld3q_f32(ptr: *const float32x4_t) -> float32x4x3_t; + fn _vld3q_dup_f32(ptr: *const f32) -> float32x4x3_t; } - _vld3q_f32(a as _) + _vld3q_dup_f32(a as _) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3))] -pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t { +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v8i8.p0" + link_name = "llvm.aarch64.neon.ld3r.v8i8.p0" )] - fn _vld3_s8(ptr: *const int8x8_t) -> int8x8x3_t; + fn _vld3_dup_s8(ptr: *const i8) -> int8x8x3_t; } - _vld3_s8(a as _) + _vld3_dup_s8(a as _) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3))] -pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t { +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v16i8.p0" + link_name = "llvm.aarch64.neon.ld3r.v16i8.p0" )] - fn _vld3q_s8(ptr: *const int8x16_t) -> int8x16x3_t; + fn _vld3q_dup_s8(ptr: *const i8) -> int8x16x3_t; } - _vld3q_s8(a as _) + _vld3q_dup_s8(a as _) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3))] -pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t { +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v4i16.p0" + link_name = "llvm.aarch64.neon.ld3r.v4i16.p0" )] - fn _vld3_s16(ptr: *const int16x4_t) -> int16x4x3_t; + fn _vld3_dup_s16(ptr: *const i16) -> int16x4x3_t; } - _vld3_s16(a as _) + _vld3_dup_s16(a as _) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3))] -pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t { +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v8i16.p0" + link_name = "llvm.aarch64.neon.ld3r.v8i16.p0" )] - fn _vld3q_s16(ptr: *const int16x8_t) -> int16x8x3_t; + fn _vld3q_dup_s16(ptr: *const i16) -> int16x8x3_t; } - _vld3q_s16(a as _) + _vld3q_dup_s16(a as _) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3))] -pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t { +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v2i32.p0" + link_name = "llvm.aarch64.neon.ld3r.v2i32.p0" )] - fn _vld3_s32(ptr: *const int32x2_t) -> int32x2x3_t; + fn _vld3_dup_s32(ptr: *const i32) -> int32x2x3_t; } - _vld3_s32(a as _) + _vld3_dup_s32(a as _) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3))] -pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t { +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v4i32.p0" + link_name = "llvm.aarch64.neon.ld3r.v4i32.p0" )] - fn _vld3q_s32(ptr: *const int32x4_t) -> int32x4x3_t; + fn _vld3q_dup_s32(ptr: *const i32) -> int32x4x3_t; } - _vld3q_s32(a as _) + _vld3q_dup_s32(a as _) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t { +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v2f32.p0")] - fn _vld3_f32(ptr: *const i8, size: i32) -> float32x2x3_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v1i64.p0" + )] + fn _vld3_dup_s64(ptr: *const i64) -> int64x1x3_t; } - _vld3_f32(a as *const i8, 4) + _vld3_dup_s64(a as _) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] +#[inline] #[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4f32.p0")] - fn _vld3q_f32(ptr: *const i8, size: i32) -> float32x4x3_t; - } - _vld3q_f32(a as *const i8, 4) -} -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] #[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t { +pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8i8.p0")] - fn _vld3_s8(ptr: *const i8, size: i32) -> int8x8x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v2f32.p0")] + fn _vld3_dup_f32(ptr: *const i8, size: i32) -> float32x2x3_t; } - _vld3_s8(a as *const i8, 1) + _vld3_dup_f32(a as *const i8, 4) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] +#[inline] #[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t { +pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v16i8.p0")] - fn _vld3q_s8(ptr: *const i8, size: i32) -> int8x16x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4f32.p0")] + fn _vld3q_dup_f32(ptr: *const i8, size: i32) -> float32x4x3_t; } - _vld3q_s8(a as *const i8, 1) + _vld3q_dup_f32(a as *const i8, 4) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] +#[inline] #[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t { +pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4i16.p0")] - fn _vld3_s16(ptr: *const i8, size: i32) -> int16x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8i8.p0")] + fn _vld3_dup_s8(ptr: *const i8, size: i32) -> int8x8x3_t; } - _vld3_s16(a as *const i8, 2) + _vld3_dup_s8(a as *const i8, 1) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] +#[inline] #[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t { +pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8i16.p0")] - fn _vld3q_s16(ptr: *const i8, size: i32) -> int16x8x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v16i8.p0")] + fn _vld3q_dup_s8(ptr: *const i8, size: i32) -> int8x16x3_t; } - _vld3q_s16(a as *const i8, 2) + _vld3q_dup_s8(a as *const i8, 1) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] +#[inline] #[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t { +pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v2i32.p0")] - fn _vld3_s32(ptr: *const i8, size: i32) -> int32x2x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4i16.p0")] + fn _vld3_dup_s16(ptr: *const i8, size: i32) -> int16x4x3_t; } - _vld3_s32(a as *const i8, 4) + _vld3_dup_s16(a as *const i8, 2) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] +#[inline] #[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t { +pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4i32.p0")] - fn _vld3q_s32(ptr: *const i8, size: i32) -> int32x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8i16.p0")] + fn _vld3q_dup_s16(ptr: *const i8, size: i32) -> int16x8x3_t; } - _vld3q_s32(a as *const i8, 4) + _vld3q_dup_s16(a as *const i8, 2) } -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3_lane_f16(a: *const f16, b: float16x4x3_t) -> float16x4x3_t { - static_assert_uimm_bits!(LANE, 2); +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4f16.p0")] - fn _vld3_lane_f16( - ptr: *const f16, - a: float16x4_t, - b: float16x4_t, - c: float16x4_t, - n: i32, - size: i32, - ) -> float16x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v2i32.p0")] + fn _vld3_dup_s32(ptr: *const i8, size: i32) -> int32x2x3_t; } - _vld3_lane_f16(a as _, b.0, b.1, b.2, LANE, 2) + _vld3_dup_s32(a as *const i8, 4) } -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3q_lane_f16(a: *const f16, b: float16x8x3_t) -> float16x8x3_t { - static_assert_uimm_bits!(LANE, 3); +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8f16.p0")] - fn _vld3q_lane_f16( - ptr: *const f16, - a: float16x8_t, - b: float16x8_t, - c: float16x8_t, - n: i32, - size: i32, - ) -> float16x8x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4i32.p0")] + fn _vld3q_dup_s32(ptr: *const i8, size: i32) -> int32x4x3_t; } - _vld3q_lane_f16(a as _, b.0, b.1, b.2, LANE, 2) + _vld3q_dup_s32(a as *const i8, 4) } -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3, LANE = 0) + assert_instr(ld3r) )] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3_lane_f16(a: *const f16, b: float16x4x3_t) -> float16x4x3_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3lane.v4f16.p0" - )] - fn _vld3_lane_f16( - a: float16x4_t, - b: float16x4_t, - c: float16x4_t, - n: i64, - ptr: *const f16, - ) -> float16x4x3_t; - } - _vld3_lane_f16(b.0, b.1, b.2, LANE as i64, a as _) -} -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3, LANE = 0) + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") )] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3q_lane_f16(a: *const f16, b: float16x8x3_t) -> float16x8x3_t { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3lane.v8f16.p0" - )] - fn _vld3q_lane_f16( - a: float16x8_t, - b: float16x8_t, - c: float16x8_t, - n: i64, - ptr: *const f16, - ) -> float16x8x3_t; - } - _vld3q_lane_f16(b.0, b.1, b.2, LANE as i64, a as _) -} -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_lane_f32(a: *const f32, b: float32x2x3_t) -> float32x2x3_t { - static_assert_uimm_bits!(LANE, 1); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3lane.v2f32.p0" - )] - fn _vld3_lane_f32( - a: float32x2_t, - b: float32x2_t, - c: float32x2_t, - n: i64, - ptr: *const i8, - ) -> float32x2x3_t; - } - _vld3_lane_f32(b.0, b.1, b.2, LANE as i64, a as _) -} -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_lane_f32(a: *const f32, b: float32x4x3_t) -> float32x4x3_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3lane.v4f32.p0" - )] - fn _vld3q_lane_f32( - a: float32x4_t, - b: float32x4_t, - c: float32x4_t, - n: i64, - ptr: *const i8, - ) -> float32x4x3_t; - } - _vld3q_lane_f32(b.0, b.1, b.2, LANE as i64, a as _) -} -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3_lane_f32(a: *const f32, b: float32x2x3_t) -> float32x2x3_t { - static_assert_uimm_bits!(LANE, 1); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v2f32.p0")] - fn _vld3_lane_f32( - ptr: *const i8, - a: float32x2_t, - b: float32x2_t, - c: float32x2_t, - n: i32, - size: i32, - ) -> float32x2x3_t; - } - _vld3_lane_f32(a as _, b.0, b.1, b.2, LANE, 4) -} -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_lane_s8(a: *const i8, b: int8x8x3_t) -> int8x8x3_t { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3lane.v8i8.p0" - )] - fn _vld3_lane_s8( - a: int8x8_t, - b: int8x8_t, - c: int8x8_t, - n: i64, - ptr: *const i8, - ) -> int8x8x3_t; - } - _vld3_lane_s8(b.0, b.1, b.2, LANE as i64, a as _) -} -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_lane_s16(a: *const i16, b: int16x4x3_t) -> int16x4x3_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3lane.v4i16.p0" - )] - fn _vld3_lane_s16( - a: int16x4_t, - b: int16x4_t, - c: int16x4_t, - n: i64, - ptr: *const i8, - ) -> int16x4x3_t; - } - _vld3_lane_s16(b.0, b.1, b.2, LANE as i64, a as _) -} -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_lane_s16(a: *const i16, b: int16x8x3_t) -> int16x8x3_t { - static_assert_uimm_bits!(LANE, 4); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3lane.v8i16.p0" - )] - fn _vld3q_lane_s16( - a: int16x8_t, - b: int16x8_t, - c: int16x8_t, - n: i64, - ptr: *const i8, - ) -> int16x8x3_t; - } - _vld3q_lane_s16(b.0, b.1, b.2, LANE as i64, a as _) -} -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_lane_s32(a: *const i32, b: int32x2x3_t) -> int32x2x3_t { - static_assert_uimm_bits!(LANE, 1); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3lane.v2i32.p0" - )] - fn _vld3_lane_s32( - a: int32x2_t, - b: int32x2_t, - c: int32x2_t, - n: i64, - ptr: *const i8, - ) -> int32x2x3_t; - } - _vld3_lane_s32(b.0, b.1, b.2, LANE as i64, a as _) -} -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_lane_s32(a: *const i32, b: int32x4x3_t) -> int32x4x3_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3lane.v4i32.p0" - )] - fn _vld3q_lane_s32( - a: int32x4_t, - b: int32x4_t, - c: int32x4_t, - n: i64, - ptr: *const i8, - ) -> int32x4x3_t; - } - _vld3q_lane_s32(b.0, b.1, b.2, LANE as i64, a as _) -} -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3_lane_s8(a: *const i8, b: int8x8x3_t) -> int8x8x3_t { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8i8.p0")] - fn _vld3_lane_s8( - ptr: *const i8, - a: int8x8_t, - b: int8x8_t, - c: int8x8_t, - n: i32, - size: i32, - ) -> int8x8x3_t; - } - _vld3_lane_s8(a as _, b.0, b.1, b.2, LANE, 1) -} -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3_lane_s16(a: *const i16, b: int16x4x3_t) -> int16x4x3_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4i16.p0")] - fn _vld3_lane_s16( - ptr: *const i8, - a: int16x4_t, - b: int16x4_t, - c: int16x4_t, - n: i32, - size: i32, - ) -> int16x4x3_t; - } - _vld3_lane_s16(a as _, b.0, b.1, b.2, LANE, 2) -} -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3q_lane_s16(a: *const i16, b: int16x8x3_t) -> int16x8x3_t { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8i16.p0")] - fn _vld3q_lane_s16( - ptr: *const i8, - a: int16x8_t, - b: int16x8_t, - c: int16x8_t, - n: i32, - size: i32, - ) -> int16x8x3_t; - } - _vld3q_lane_s16(a as _, b.0, b.1, b.2, LANE, 2) -} -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3_lane_s32(a: *const i32, b: int32x2x3_t) -> int32x2x3_t { - static_assert_uimm_bits!(LANE, 1); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v2i32.p0")] - fn _vld3_lane_s32( - ptr: *const i8, - a: int32x2_t, - b: int32x2_t, - c: int32x2_t, - n: i32, - size: i32, - ) -> int32x2x3_t; - } - _vld3_lane_s32(a as _, b.0, b.1, b.2, LANE, 4) +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_dup_p64(a: *const p64) -> poly64x1x3_t { + transmute(vld3_dup_s64(transmute(a))) } -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3q_lane_s32(a: *const i32, b: int32x4x3_t) -> int32x4x3_t { - static_assert_uimm_bits!(LANE, 2); +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4i32.p0")] - fn _vld3q_lane_s32( - ptr: *const i8, - a: int32x4_t, - b: int32x4_t, - c: int32x4_t, - n: i32, - size: i32, - ) -> int32x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v1i64.p0")] + fn _vld3_dup_s64(ptr: *const i8, size: i32) -> int64x1x3_t; } - _vld3q_lane_s32(a as _, b.0, b.1, b.2, LANE, 4) + _vld3_dup_s64(a as *const i8, 8) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u8)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3, LANE = 0) + assert_instr(ld3r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -24571,23 +24170,21 @@ pub unsafe fn vld3q_lane_s32(a: *const i32, b: int32x4x3_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_lane_u8(a: *const u8, b: uint8x8x3_t) -> uint8x8x3_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld3_lane_s8::(transmute(a), transmute(b))) +pub unsafe fn vld3_dup_u64(a: *const u64) -> uint64x1x3_t { + transmute(vld3_dup_s64(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3, LANE = 0) + assert_instr(ld3r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -24596,23 +24193,21 @@ pub unsafe fn vld3_lane_u8(a: *const u8, b: uint8x8x3_t) -> uin target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_lane_u16(a: *const u16, b: uint16x4x3_t) -> uint16x4x3_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld3_lane_s16::(transmute(a), transmute(b))) +pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t { + transmute(vld3_dup_s8(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3, LANE = 0) + assert_instr(ld3r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -24621,23 +24216,21 @@ pub unsafe fn vld3_lane_u16(a: *const u16, b: uint16x4x3_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_lane_u16(a: *const u16, b: uint16x8x3_t) -> uint16x8x3_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld3q_lane_s16::(transmute(a), transmute(b))) +pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t { + transmute(vld3q_dup_s8(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3, LANE = 0) + assert_instr(ld3r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -24646,23 +24239,21 @@ pub unsafe fn vld3q_lane_u16(a: *const u16, b: uint16x8x3_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_lane_u32(a: *const u32, b: uint32x2x3_t) -> uint32x2x3_t { - static_assert_uimm_bits!(LANE, 1); - transmute(vld3_lane_s32::(transmute(a), transmute(b))) +pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t { + transmute(vld3_dup_s16(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3, LANE = 0) + assert_instr(ld3r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -24671,23 +24262,21 @@ pub unsafe fn vld3_lane_u32(a: *const u32, b: uint32x2x3_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_lane_u32(a: *const u32, b: uint32x4x3_t) -> uint32x4x3_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld3q_lane_s32::(transmute(a), transmute(b))) +pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t { + transmute(vld3q_dup_s16(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p8)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3, LANE = 0) + assert_instr(ld3r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -24696,23 +24285,21 @@ pub unsafe fn vld3q_lane_u32(a: *const u32, b: uint32x4x3_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_lane_p8(a: *const p8, b: poly8x8x3_t) -> poly8x8x3_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld3_lane_s8::(transmute(a), transmute(b))) +pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t { + transmute(vld3_dup_s32(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3, LANE = 0) + assert_instr(ld3r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -24721,23 +24308,21 @@ pub unsafe fn vld3_lane_p8(a: *const p8, b: poly8x8x3_t) -> pol target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_lane_p16(a: *const p16, b: poly16x4x3_t) -> poly16x4x3_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld3_lane_s16::(transmute(a), transmute(b))) +pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t { + transmute(vld3q_dup_s32(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3, LANE = 0) + assert_instr(ld3r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -24746,21 +24331,20 @@ pub unsafe fn vld3_lane_p16(a: *const p16, b: poly16x4x3_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_lane_p16(a: *const p16, b: poly16x8x3_t) -> poly16x8x3_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld3q_lane_s16::(transmute(a), transmute(b))) +pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t { + transmute(vld3_dup_s8(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p64)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ld3r) )] #[cfg_attr( not(target_arch = "arm"), @@ -24770,55 +24354,20 @@ pub unsafe fn vld3q_lane_p16(a: *const p16, b: poly16x8x3_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_p64(a: *const p64) -> poly64x1x3_t { - transmute(vld3_s64(transmute(a))) +pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t { + transmute(vld3q_dup_s8(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v1i64.p0" - )] - fn _vld3_s64(ptr: *const int64x1_t) -> int64x1x3_t; - } - _vld3_s64(a as _) -} -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v1i64.p0")] - fn _vld3_s64(ptr: *const i8, size: i32) -> int64x1x3_t; - } - _vld3_s64(a as *const i8, 8) -} -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ld3r) )] #[cfg_attr( not(target_arch = "arm"), @@ -24828,21 +24377,20 @@ pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t { - transmute(vld3_s64(transmute(a))) +pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t { + transmute(vld3_dup_s16(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) + assert_instr(ld3r) )] #[cfg_attr( not(target_arch = "arm"), @@ -24852,998 +24400,775 @@ pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t { - transmute(vld3_s8(transmute(a))) +pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t { + transmute(vld3q_dup_s16(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"] +#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg(target_arch = "arm")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t { - let mut ret_val: uint8x8x3_t = transmute(vld3_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4f16.p0")] + fn _vld3_f16(ptr: *const f16, size: i32) -> float16x4x3_t; + } + _vld3_f16(a as _, 2) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"] +#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg(target_arch = "arm")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t { - transmute(vld3q_s8(transmute(a))) +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8f16.p0")] + fn _vld3q_f16(ptr: *const f16, size: i32) -> float16x8x3_t; + } + _vld3q_f16(a as _, 2) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"] +#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3) )] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t { - let mut ret_val: uint8x16x3_t = transmute(vld3q_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t { + crate::core_arch::macros::deinterleaving_load!(f16, 4, 3, a) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3) )] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t { - transmute(vld3_s16(transmute(a))) +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t { + crate::core_arch::macros::deinterleaving_load!(f16, 8, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t { - let mut ret_val: uint16x4x3_t = transmute(vld3_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t { + crate::core_arch::macros::deinterleaving_load!(f32, 2, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t { - transmute(vld3q_s16(transmute(a))) +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t { + crate::core_arch::macros::deinterleaving_load!(f32, 4, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t { - let mut ret_val: uint16x8x3_t = transmute(vld3q_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t { + crate::core_arch::macros::deinterleaving_load!(i8, 8, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t { - transmute(vld3_s32(transmute(a))) +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t { + crate::core_arch::macros::deinterleaving_load!(i8, 16, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t { - let mut ret_val: uint32x2x3_t = transmute(vld3_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t { + crate::core_arch::macros::deinterleaving_load!(i16, 4, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t { - transmute(vld3q_s32(transmute(a))) +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t { + crate::core_arch::macros::deinterleaving_load!(i16, 8, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t { - let mut ret_val: uint32x4x3_t = transmute(vld3q_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t { + crate::core_arch::macros::deinterleaving_load!(i32, 2, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t { - transmute(vld3_s8(transmute(a))) +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t { + crate::core_arch::macros::deinterleaving_load!(i32, 4, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t { - let mut ret_val: poly8x8x3_t = transmute(vld3_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v2f32.p0")] + fn _vld3_f32(ptr: *const i8, size: i32) -> float32x2x3_t; + } + _vld3_f32(a as *const i8, 4) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t { - transmute(vld3q_s8(transmute(a))) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4f32.p0")] + fn _vld3q_f32(ptr: *const i8, size: i32) -> float32x4x3_t; + } + _vld3q_f32(a as *const i8, 4) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t { - let mut ret_val: poly8x16x3_t = transmute(vld3q_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8i8.p0")] + fn _vld3_s8(ptr: *const i8, size: i32) -> int8x8x3_t; + } + _vld3_s8(a as *const i8, 1) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t { - transmute(vld3_s16(transmute(a))) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v16i8.p0")] + fn _vld3q_s8(ptr: *const i8, size: i32) -> int8x16x3_t; + } + _vld3q_s8(a as *const i8, 1) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t { - let mut ret_val: poly16x4x3_t = transmute(vld3_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4i16.p0")] + fn _vld3_s16(ptr: *const i8, size: i32) -> int16x4x3_t; + } + _vld3_s16(a as *const i8, 2) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t { - transmute(vld3q_s16(transmute(a))) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8i16.p0")] + fn _vld3q_s16(ptr: *const i8, size: i32) -> int16x8x3_t; + } + _vld3q_s16(a as *const i8, 2) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t { - let mut ret_val: poly16x8x3_t = transmute(vld3q_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v2i32.p0")] + fn _vld3_s32(ptr: *const i8, size: i32) -> int32x2x3_t; + } + _vld3_s32(a as *const i8, 4) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3q_lane_f32(a: *const f32, b: float32x4x3_t) -> float32x4x3_t { - static_assert_uimm_bits!(LANE, 2); +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4f32.p0")] - fn _vld3q_lane_f32( - ptr: *const i8, - a: float32x4_t, - b: float32x4_t, - c: float32x4_t, - n: i32, - size: i32, - ) -> float32x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4i32.p0")] + fn _vld3q_s32(ptr: *const i8, size: i32) -> int32x4x3_t; } - _vld3q_lane_f32(a as _, b.0, b.1, b.2, LANE, 4) + _vld3q_s32(a as *const i8, 4) } -#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"] +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[inline] +#[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[target_feature(enable = "neon,fp16")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t { +pub unsafe fn vld3_lane_f16(a: *const f16, b: float16x4x3_t) -> float16x4x3_t { + static_assert_uimm_bits!(LANE, 2); unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4f16.p0")] - fn _vld4_dup_f16(ptr: *const f16, size: i32) -> float16x4x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4f16.p0")] + fn _vld3_lane_f16( + ptr: *const f16, + a: float16x4_t, + b: float16x4_t, + c: float16x4_t, + n: i32, + size: i32, + ) -> float16x4x3_t; } - _vld4_dup_f16(a as _, 2) + _vld3_lane_f16(a as _, b.0, b.1, b.2, LANE, 2) } -#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"] +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[inline] +#[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[target_feature(enable = "neon,fp16")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t { +pub unsafe fn vld3q_lane_f16(a: *const f16, b: float16x8x3_t) -> float16x8x3_t { + static_assert_uimm_bits!(LANE, 3); unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8f16.p0")] - fn _vld4q_dup_f16(ptr: *const f16, size: i32) -> float16x8x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8f16.p0")] + fn _vld3q_lane_f16( + ptr: *const f16, + a: float16x8_t, + b: float16x8_t, + c: float16x8_t, + n: i32, + size: i32, + ) -> float16x8x3_t; } - _vld4q_dup_f16(a as _, 2) + _vld3q_lane_f16(a as _, b.0, b.1, b.2, LANE, 2) } -#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"] +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] +#[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld3, LANE = 0) )] -#[target_feature(enable = "neon,fp16")] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t { +pub unsafe fn vld3_lane_f16(a: *const f16, b: float16x4x3_t) -> float16x4x3_t { + static_assert_uimm_bits!(LANE, 2); unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4r.v4f16.p0" + link_name = "llvm.aarch64.neon.ld3lane.v4f16.p0" )] - fn _vld4_dup_f16(ptr: *const f16) -> float16x4x4_t; + fn _vld3_lane_f16( + a: float16x4_t, + b: float16x4_t, + c: float16x4_t, + n: i64, + ptr: *const f16, + ) -> float16x4x3_t; } - _vld4_dup_f16(a as _) + _vld3_lane_f16(b.0, b.1, b.2, LANE as i64, a as _) } -#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"] +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] +#[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld3, LANE = 0) )] -#[target_feature(enable = "neon,fp16")] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t { +pub unsafe fn vld3q_lane_f16(a: *const f16, b: float16x8x3_t) -> float16x8x3_t { + static_assert_uimm_bits!(LANE, 3); unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4r.v8f16.p0" + link_name = "llvm.aarch64.neon.ld3lane.v8f16.p0" )] - fn _vld4q_dup_f16(ptr: *const f16) -> float16x8x4_t; - } - _vld4q_dup_f16(a as _) -} -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v2f32.p0")] - fn _vld4_dup_f32(ptr: *const i8, size: i32) -> float32x2x4_t; - } - _vld4_dup_f32(a as *const i8, 4) -} -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4f32.p0")] - fn _vld4q_dup_f32(ptr: *const i8, size: i32) -> float32x4x4_t; - } - _vld4q_dup_f32(a as *const i8, 4) -} -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8i8.p0")] - fn _vld4_dup_s8(ptr: *const i8, size: i32) -> int8x8x4_t; - } - _vld4_dup_s8(a as *const i8, 1) -} -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v16i8.p0")] - fn _vld4q_dup_s8(ptr: *const i8, size: i32) -> int8x16x4_t; - } - _vld4q_dup_s8(a as *const i8, 1) -} -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4i16.p0")] - fn _vld4_dup_s16(ptr: *const i8, size: i32) -> int16x4x4_t; - } - _vld4_dup_s16(a as *const i8, 2) -} -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8i16.p0")] - fn _vld4q_dup_s16(ptr: *const i8, size: i32) -> int16x8x4_t; - } - _vld4q_dup_s16(a as *const i8, 2) -} -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v2i32.p0")] - fn _vld4_dup_s32(ptr: *const i8, size: i32) -> int32x2x4_t; - } - _vld4_dup_s32(a as *const i8, 4) -} -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4i32.p0")] - fn _vld4q_dup_s32(ptr: *const i8, size: i32) -> int32x4x4_t; + fn _vld3q_lane_f16( + a: float16x8_t, + b: float16x8_t, + c: float16x8_t, + n: i64, + ptr: *const f16, + ) -> float16x8x3_t; } - _vld4q_dup_s32(a as *const i8, 4) + _vld3q_lane_f16(b.0, b.1, b.2, LANE as i64, a as _) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4r))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t { +pub unsafe fn vld3_lane_f32(a: *const f32, b: float32x2x3_t) -> float32x2x3_t { + static_assert_uimm_bits!(LANE, 1); unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4r.v2f32.p0.p0" + link_name = "llvm.aarch64.neon.ld3lane.v2f32.p0" )] - fn _vld4_dup_f32(ptr: *const f32) -> float32x2x4_t; + fn _vld3_lane_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, + n: i64, + ptr: *const i8, + ) -> float32x2x3_t; } - _vld4_dup_f32(a as _) + _vld3_lane_f32(b.0, b.1, b.2, LANE as i64, a as _) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4r))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t { +pub unsafe fn vld3q_lane_f32(a: *const f32, b: float32x4x3_t) -> float32x4x3_t { + static_assert_uimm_bits!(LANE, 2); unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4r.v4f32.p0.p0" + link_name = "llvm.aarch64.neon.ld3lane.v4f32.p0" )] - fn _vld4q_dup_f32(ptr: *const f32) -> float32x4x4_t; + fn _vld3q_lane_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, + n: i64, + ptr: *const i8, + ) -> float32x4x3_t; } - _vld4q_dup_f32(a as _) + _vld3q_lane_f32(b.0, b.1, b.2, LANE as i64, a as _) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t { +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld3_lane_f32(a: *const f32, b: float32x2x3_t) -> float32x2x3_t { + static_assert_uimm_bits!(LANE, 1); unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4r.v8i8.p0.p0" - )] - fn _vld4_dup_s8(ptr: *const i8) -> int8x8x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v2f32.p0")] + fn _vld3_lane_f32( + ptr: *const i8, + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, + n: i32, + size: i32, + ) -> float32x2x3_t; } - _vld4_dup_s8(a as _) + _vld3_lane_f32(a as _, b.0, b.1, b.2, LANE, 4) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"] +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4r))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t { +pub unsafe fn vld3_lane_s8(a: *const i8, b: int8x8x3_t) -> int8x8x3_t { + static_assert_uimm_bits!(LANE, 3); unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4r.v16i8.p0.p0" + link_name = "llvm.aarch64.neon.ld3lane.v8i8.p0" )] - fn _vld4q_dup_s8(ptr: *const i8) -> int8x16x4_t; + fn _vld3_lane_s8( + a: int8x8_t, + b: int8x8_t, + c: int8x8_t, + n: i64, + ptr: *const i8, + ) -> int8x8x3_t; } - _vld4q_dup_s8(a as _) + _vld3_lane_s8(b.0, b.1, b.2, LANE as i64, a as _) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"] +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4r))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t { +pub unsafe fn vld3_lane_s16(a: *const i16, b: int16x4x3_t) -> int16x4x3_t { + static_assert_uimm_bits!(LANE, 2); unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4r.v4i16.p0.p0" + link_name = "llvm.aarch64.neon.ld3lane.v4i16.p0" )] - fn _vld4_dup_s16(ptr: *const i16) -> int16x4x4_t; + fn _vld3_lane_s16( + a: int16x4_t, + b: int16x4_t, + c: int16x4_t, + n: i64, + ptr: *const i8, + ) -> int16x4x3_t; } - _vld4_dup_s16(a as _) + _vld3_lane_s16(b.0, b.1, b.2, LANE as i64, a as _) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"] +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4r))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t { +pub unsafe fn vld3q_lane_s16(a: *const i16, b: int16x8x3_t) -> int16x8x3_t { + static_assert_uimm_bits!(LANE, 4); unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4r.v8i16.p0.p0" + link_name = "llvm.aarch64.neon.ld3lane.v8i16.p0" )] - fn _vld4q_dup_s16(ptr: *const i16) -> int16x8x4_t; + fn _vld3q_lane_s16( + a: int16x8_t, + b: int16x8_t, + c: int16x8_t, + n: i64, + ptr: *const i8, + ) -> int16x8x3_t; } - _vld4q_dup_s16(a as _) + _vld3q_lane_s16(b.0, b.1, b.2, LANE as i64, a as _) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"] +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4r))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t { +pub unsafe fn vld3_lane_s32(a: *const i32, b: int32x2x3_t) -> int32x2x3_t { + static_assert_uimm_bits!(LANE, 1); unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4r.v2i32.p0.p0" + link_name = "llvm.aarch64.neon.ld3lane.v2i32.p0" )] - fn _vld4_dup_s32(ptr: *const i32) -> int32x2x4_t; + fn _vld3_lane_s32( + a: int32x2_t, + b: int32x2_t, + c: int32x2_t, + n: i64, + ptr: *const i8, + ) -> int32x2x3_t; } - _vld4_dup_s32(a as _) + _vld3_lane_s32(b.0, b.1, b.2, LANE as i64, a as _) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"] +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4r))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t { +pub unsafe fn vld3q_lane_s32(a: *const i32, b: int32x4x3_t) -> int32x4x3_t { + static_assert_uimm_bits!(LANE, 2); unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4r.v4i32.p0.p0" + link_name = "llvm.aarch64.neon.ld3lane.v4i32.p0" )] - fn _vld4q_dup_s32(ptr: *const i32) -> int32x4x4_t; + fn _vld3q_lane_s32( + a: int32x4_t, + b: int32x4_t, + c: int32x4_t, + n: i64, + ptr: *const i8, + ) -> int32x4x3_t; } - _vld4q_dup_s32(a as _) + _vld3q_lane_s32(b.0, b.1, b.2, LANE as i64, a as _) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"] +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t { +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld3_lane_s8(a: *const i8, b: int8x8x3_t) -> int8x8x3_t { + static_assert_uimm_bits!(LANE, 3); unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4r.v1i64.p0.p0" - )] - fn _vld4_dup_s64(ptr: *const i64) -> int64x1x4_t; - } - _vld4_dup_s64(a as _) -} -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p64)"] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8i8.p0")] + fn _vld3_lane_s8( + ptr: *const i8, + a: int8x8_t, + b: int8x8_t, + c: int8x8_t, + n: i32, + size: i32, + ) -> int8x8x3_t; + } + _vld3_lane_s8(a as _, b.0, b.1, b.2, LANE, 1) +} +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_dup_p64(a: *const p64) -> poly64x1x4_t { - transmute(vld4_dup_s64(transmute(a))) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld3_lane_s16(a: *const i16, b: int16x4x3_t) -> int16x4x3_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4i16.p0")] + fn _vld3_lane_s16( + ptr: *const i8, + a: int16x4_t, + b: int16x4_t, + c: int16x4_t, + n: i32, + size: i32, + ) -> int16x4x3_t; + } + _vld3_lane_s16(a as _, b.0, b.1, b.2, LANE, 2) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"] +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t { +pub unsafe fn vld3q_lane_s16(a: *const i16, b: int16x8x3_t) -> int16x8x3_t { + static_assert_uimm_bits!(LANE, 3); unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v1i64.p0")] - fn _vld4_dup_s64(ptr: *const i8, size: i32) -> int64x1x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8i16.p0")] + fn _vld3q_lane_s16( + ptr: *const i8, + a: int16x8_t, + b: int16x8_t, + c: int16x8_t, + n: i32, + size: i32, + ) -> int16x8x3_t; } - _vld4_dup_s64(a as *const i8, 8) + _vld3q_lane_s16(a as _, b.0, b.1, b.2, LANE, 2) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u64)"] +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld3_lane_s32(a: *const i32, b: int32x2x3_t) -> int32x2x3_t { + static_assert_uimm_bits!(LANE, 1); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v2i32.p0")] + fn _vld3_lane_s32( + ptr: *const i8, + a: int32x2_t, + b: int32x2_t, + c: int32x2_t, + n: i32, + size: i32, + ) -> int32x2x3_t; + } + _vld3_lane_s32(a as _, b.0, b.1, b.2, LANE, 4) +} +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld3q_lane_s32(a: *const i32, b: int32x4x3_t) -> int32x4x3_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4i32.p0")] + fn _vld3q_lane_s32( + ptr: *const i8, + a: int32x4_t, + b: int32x4_t, + c: int32x4_t, + n: i32, + size: i32, + ) -> int32x4x3_t; + } + _vld3q_lane_s32(a as _, b.0, b.1, b.2, LANE, 4) +} +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld3, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -25852,22 +25177,23 @@ pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_dup_u64(a: *const u64) -> uint64x1x4_t { - transmute(vld4_dup_s64(transmute(a))) +pub unsafe fn vld3_lane_u8(a: *const u8, b: uint8x8x3_t) -> uint8x8x3_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld3_lane_s8::(transmute(a), transmute(b))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld3, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -25876,22 +25202,23 @@ pub unsafe fn vld4_dup_u64(a: *const u64) -> uint64x1x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t { - transmute(vld4_dup_s8(transmute(a))) +pub unsafe fn vld3_lane_u16(a: *const u16, b: uint16x4x3_t) -> uint16x4x3_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld3_lane_s16::(transmute(a), transmute(b))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld3, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -25900,27 +25227,23 @@ pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t { - let mut ret_val: uint8x8x4_t = transmute(vld4_dup_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld3q_lane_u16(a: *const u16, b: uint16x8x3_t) -> uint16x8x3_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld3q_lane_s16::(transmute(a), transmute(b))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld3, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -25929,22 +25252,23 @@ pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t { - transmute(vld4q_dup_s8(transmute(a))) +pub unsafe fn vld3_lane_u32(a: *const u32, b: uint32x2x3_t) -> uint32x2x3_t { + static_assert_uimm_bits!(LANE, 1); + transmute(vld3_lane_s32::(transmute(a), transmute(b))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld3, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -25953,51 +25277,23 @@ pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t { - let mut ret_val: uint8x16x4_t = transmute(vld4q_dup_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.3 = unsafe { - simd_shuffle!( - ret_val.3, - ret_val.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld3q_lane_u32(a: *const u32, b: uint32x4x3_t) -> uint32x4x3_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld3q_lane_s32::(transmute(a), transmute(b))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld3, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -26006,22 +25302,23 @@ pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t { - transmute(vld4_dup_s16(transmute(a))) +pub unsafe fn vld3_lane_p8(a: *const p8, b: poly8x8x3_t) -> poly8x8x3_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld3_lane_s8::(transmute(a), transmute(b))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld3, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -26030,27 +25327,23 @@ pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t { - let mut ret_val: uint16x4x4_t = transmute(vld4_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld3_lane_p16(a: *const p16, b: poly16x4x3_t) -> poly16x4x3_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld3_lane_s16::(transmute(a), transmute(b))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld3, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -26059,21 +25352,21 @@ pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t { - transmute(vld4q_dup_s16(transmute(a))) +pub unsafe fn vld3q_lane_p16(a: *const p16, b: poly16x8x3_t) -> poly16x8x3_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld3q_lane_s16::(transmute(a), transmute(b))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(nop) )] #[cfg_attr( not(target_arch = "arm"), @@ -26083,50 +25376,48 @@ pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t { - let mut ret_val: uint16x8x4_t = transmute(vld4q_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld3_p64(a: *const p64) -> poly64x1x3_t { + transmute(vld3_s64(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t { - transmute(vld4_dup_s32(transmute(a))) +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v1i64.p0")] + fn _vld3_s64(ptr: *const i8, size: i32) -> int64x1x3_t; + } + _vld3_s64(a as *const i8, 8) +} +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(nop) )] #[cfg_attr( not(target_arch = "arm"), @@ -26136,26 +25427,20 @@ pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t { - let mut ret_val: uint32x2x4_t = transmute(vld4_dup_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; - ret_val +pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t { + transmute(vld3_s64(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld3) )] #[cfg_attr( not(target_arch = "arm"), @@ -26165,21 +25450,20 @@ pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t { - transmute(vld4q_dup_s32(transmute(a))) +pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t { + transmute(vld3_s8(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld3) )] #[cfg_attr( not(target_arch = "arm"), @@ -26189,26 +25473,20 @@ pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t { - let mut ret_val: uint32x4x4_t = transmute(vld4q_dup_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t { + transmute(vld3q_s8(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld3) )] #[cfg_attr( not(target_arch = "arm"), @@ -26218,21 +25496,20 @@ pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t { - transmute(vld4_dup_s8(transmute(a))) +pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t { + transmute(vld3_s16(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld3) )] #[cfg_attr( not(target_arch = "arm"), @@ -26242,26 +25519,20 @@ pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t { - let mut ret_val: poly8x8x4_t = transmute(vld4_dup_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t { + transmute(vld3q_s16(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld3) )] #[cfg_attr( not(target_arch = "arm"), @@ -26271,21 +25542,20 @@ pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t { - transmute(vld4q_dup_s8(transmute(a))) +pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t { + transmute(vld3_s32(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld3) )] #[cfg_attr( not(target_arch = "arm"), @@ -26295,50 +25565,20 @@ pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t { - let mut ret_val: poly8x16x4_t = transmute(vld4q_dup_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.3 = unsafe { - simd_shuffle!( - ret_val.3, - ret_val.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t { + transmute(vld3q_s32(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld3) )] #[cfg_attr( not(target_arch = "arm"), @@ -26348,21 +25588,20 @@ pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t { - transmute(vld4_dup_s16(transmute(a))) +pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t { + transmute(vld3_s8(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld3) )] #[cfg_attr( not(target_arch = "arm"), @@ -26372,26 +25611,20 @@ pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t { - let mut ret_val: poly16x4x4_t = transmute(vld4_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t { + transmute(vld3q_s8(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld3) )] #[cfg_attr( not(target_arch = "arm"), @@ -26401,21 +25634,20 @@ pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t { - transmute(vld4q_dup_s16(transmute(a))) +pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t { + transmute(vld3_s16(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld3) )] #[cfg_attr( not(target_arch = "arm"), @@ -26425,887 +25657,466 @@ pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t { - let mut ret_val: poly16x8x4_t = transmute(vld4q_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t { + transmute(vld3q_s16(transmute(a))) +} +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld3q_lane_f32(a: *const f32, b: float32x4x3_t) -> float32x4x3_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4f32.p0")] + fn _vld3q_lane_f32( + ptr: *const i8, + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, + n: i32, + size: i32, + ) -> float32x4x3_t; + } + _vld3q_lane_f32(a as _, b.0, b.1, b.2, LANE, 4) } #[doc = "Load single 4-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg(target_arch = "arm")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t { +pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4f16.p0")] - fn _vld4_f16(ptr: *const f16, size: i32) -> float16x4x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4f16.p0")] + fn _vld4_dup_f16(ptr: *const f16, size: i32) -> float16x4x4_t; } - _vld4_f16(a as _, 2) + _vld4_dup_f16(a as _, 2) } #[doc = "Load single 4-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg(target_arch = "arm")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t { +pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8f16.p0")] - fn _vld4q_f16(ptr: *const f16, size: i32) -> float16x8x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8f16.p0")] + fn _vld4q_dup_f16(ptr: *const f16, size: i32) -> float16x8x4_t; } - _vld4q_f16(a as _, 2) + _vld4q_dup_f16(a as _, 2) } #[doc = "Load single 4-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) + assert_instr(ld4r) )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t { +pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v4f16.p0" + link_name = "llvm.aarch64.neon.ld4r.v4f16.p0" )] - fn _vld4_f16(ptr: *const f16) -> float16x4x4_t; + fn _vld4_dup_f16(ptr: *const f16) -> float16x4x4_t; } - _vld4_f16(a as _) + _vld4_dup_f16(a as _) } #[doc = "Load single 4-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) + assert_instr(ld4r) )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v8f16.p0" - )] - fn _vld4q_f16(ptr: *const f16) -> float16x8x4_t; - } - _vld4q_f16(a as _) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld4))] -pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v2f32.p0" - )] - fn _vld4_f32(ptr: *const float32x2_t) -> float32x2x4_t; - } - _vld4_f32(a as _) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld4))] -pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v4f32.p0" - )] - fn _vld4q_f32(ptr: *const float32x4_t) -> float32x4x4_t; - } - _vld4q_f32(a as _) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld4))] -pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v8i8.p0" - )] - fn _vld4_s8(ptr: *const int8x8_t) -> int8x8x4_t; - } - _vld4_s8(a as _) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld4))] -pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v16i8.p0" - )] - fn _vld4q_s8(ptr: *const int8x16_t) -> int8x16x4_t; - } - _vld4q_s8(a as _) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld4))] -pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v4i16.p0" - )] - fn _vld4_s16(ptr: *const int16x4_t) -> int16x4x4_t; - } - _vld4_s16(a as _) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld4))] -pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v8i16.p0" - )] - fn _vld4q_s16(ptr: *const int16x8_t) -> int16x8x4_t; - } - _vld4q_s16(a as _) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld4))] -pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v2i32.p0" - )] - fn _vld4_s32(ptr: *const int32x2_t) -> int32x2x4_t; - } - _vld4_s32(a as _) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld4))] -pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t { +pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v4i32.p0" + link_name = "llvm.aarch64.neon.ld4r.v8f16.p0" )] - fn _vld4q_s32(ptr: *const int32x4_t) -> int32x4x4_t; + fn _vld4q_dup_f16(ptr: *const f16) -> float16x8x4_t; } - _vld4q_s32(a as _) + _vld4q_dup_f16(a as _) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] #[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld4))] -pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v2f32.p0")] - fn _vld4_f32(ptr: *const i8, size: i32) -> float32x2x4_t; - } - _vld4_f32(a as *const i8, 4) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] #[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vld4))] -pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t { +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4f32.p0")] - fn _vld4q_f32(ptr: *const i8, size: i32) -> float32x4x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v2f32.p0")] + fn _vld4_dup_f32(ptr: *const i8, size: i32) -> float32x2x4_t; } - _vld4q_f32(a as *const i8, 4) + _vld4_dup_f32(a as *const i8, 4) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] #[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vld4))] -pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t { +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8i8.p0")] - fn _vld4_s8(ptr: *const i8, size: i32) -> int8x8x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4f32.p0")] + fn _vld4q_dup_f32(ptr: *const i8, size: i32) -> float32x4x4_t; } - _vld4_s8(a as *const i8, 1) + _vld4q_dup_f32(a as *const i8, 4) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] #[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vld4))] -pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t { +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v16i8.p0")] - fn _vld4q_s8(ptr: *const i8, size: i32) -> int8x16x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8i8.p0")] + fn _vld4_dup_s8(ptr: *const i8, size: i32) -> int8x8x4_t; } - _vld4q_s8(a as *const i8, 1) + _vld4_dup_s8(a as *const i8, 1) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] #[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vld4))] -pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t { +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4i16.p0")] - fn _vld4_s16(ptr: *const i8, size: i32) -> int16x4x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v16i8.p0")] + fn _vld4q_dup_s8(ptr: *const i8, size: i32) -> int8x16x4_t; } - _vld4_s16(a as *const i8, 2) + _vld4q_dup_s8(a as *const i8, 1) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] #[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vld4))] -pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t { +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8i16.p0")] - fn _vld4q_s16(ptr: *const i8, size: i32) -> int16x8x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4i16.p0")] + fn _vld4_dup_s16(ptr: *const i8, size: i32) -> int16x4x4_t; } - _vld4q_s16(a as *const i8, 2) + _vld4_dup_s16(a as *const i8, 2) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] #[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vld4))] -pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t { +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v2i32.p0")] - fn _vld4_s32(ptr: *const i8, size: i32) -> int32x2x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8i16.p0")] + fn _vld4q_dup_s16(ptr: *const i8, size: i32) -> int16x8x4_t; } - _vld4_s32(a as *const i8, 4) + _vld4q_dup_s16(a as *const i8, 2) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] #[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vld4))] -pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t { +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4i32.p0")] - fn _vld4q_s32(ptr: *const i8, size: i32) -> int32x4x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v2i32.p0")] + fn _vld4_dup_s32(ptr: *const i8, size: i32) -> int32x2x4_t; } - _vld4q_s32(a as *const i8, 4) + _vld4_dup_s32(a as *const i8, 4) } -#[doc = "Load multiple 4-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] #[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4_lane_f16(a: *const f16, b: float16x4x4_t) -> float16x4x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4f16.p0")] - fn _vld4_lane_f16( - ptr: *const f16, - a: float16x4_t, - b: float16x4_t, - c: float16x4_t, - d: float16x4_t, - n: i32, - size: i32, - ) -> float16x4x4_t; - } - _vld4_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2) -} -#[doc = "Load multiple 4-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] #[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4q_lane_f16(a: *const f16, b: float16x8x4_t) -> float16x8x4_t { - static_assert_uimm_bits!(LANE, 3); +#[cfg_attr(test, assert_instr(vld4))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8f16.p0")] - fn _vld4q_lane_f16( - ptr: *const f16, - a: float16x8_t, - b: float16x8_t, - c: float16x8_t, - d: float16x8_t, - n: i32, - size: i32, - ) -> float16x8x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4i32.p0")] + fn _vld4q_dup_s32(ptr: *const i8, size: i32) -> int32x4x4_t; } - _vld4q_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2) + _vld4q_dup_s32(a as *const i8, 4) } -#[doc = "Load multiple 4-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] +#[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4_lane_f16(a: *const f16, b: float16x4x4_t) -> float16x4x4_t { - static_assert_uimm_bits!(LANE, 2); +#[cfg_attr(test, assert_instr(ld4r))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4lane.v4f16.p0" + link_name = "llvm.aarch64.neon.ld4r.v2f32.p0.p0" )] - fn _vld4_lane_f16( - a: float16x4_t, - b: float16x4_t, - c: float16x4_t, - d: float16x4_t, - n: i64, - ptr: *const f16, - ) -> float16x4x4_t; + fn _vld4_dup_f32(ptr: *const f32) -> float32x2x4_t; } - _vld4_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _) + _vld4_dup_f32(a as _) } -#[doc = "Load multiple 4-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] +#[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4q_lane_f16(a: *const f16, b: float16x8x4_t) -> float16x8x4_t { - static_assert_uimm_bits!(LANE, 3); +#[cfg_attr(test, assert_instr(ld4r))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4lane.v8f16.p0" + link_name = "llvm.aarch64.neon.ld4r.v4f32.p0.p0" )] - fn _vld4q_lane_f16( - a: float16x8_t, - b: float16x8_t, - c: float16x8_t, - d: float16x8_t, - n: i64, - ptr: *const f16, - ) -> float16x8x4_t; + fn _vld4q_dup_f32(ptr: *const f32) -> float32x4x4_t; } - _vld4q_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _) + _vld4q_dup_f32(a as _) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_lane_f32(a: *const f32, b: float32x2x4_t) -> float32x2x4_t { - static_assert_uimm_bits!(LANE, 1); +pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4lane.v2f32.p0" + link_name = "llvm.aarch64.neon.ld4r.v8i8.p0.p0" )] - fn _vld4_lane_f32( - a: float32x2_t, - b: float32x2_t, - c: float32x2_t, - d: float32x2_t, - n: i64, - ptr: *const i8, - ) -> float32x2x4_t; + fn _vld4_dup_s8(ptr: *const i8) -> int8x8x4_t; } - _vld4_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) + _vld4_dup_s8(a as _) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_lane_f32(a: *const f32, b: float32x4x4_t) -> float32x4x4_t { - static_assert_uimm_bits!(LANE, 2); +pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4lane.v4f32.p0" + link_name = "llvm.aarch64.neon.ld4r.v16i8.p0.p0" )] - fn _vld4q_lane_f32( - a: float32x4_t, - b: float32x4_t, - c: float32x4_t, - d: float32x4_t, - n: i64, - ptr: *const i8, - ) -> float32x4x4_t; + fn _vld4q_dup_s8(ptr: *const i8) -> int8x16x4_t; } - _vld4q_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) + _vld4q_dup_s8(a as _) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_lane_s8(a: *const i8, b: int8x8x4_t) -> int8x8x4_t { - static_assert_uimm_bits!(LANE, 3); +pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4lane.v8i8.p0" + link_name = "llvm.aarch64.neon.ld4r.v4i16.p0.p0" )] - fn _vld4_lane_s8( - a: int8x8_t, - b: int8x8_t, - c: int8x8_t, - d: int8x8_t, - n: i64, - ptr: *const i8, - ) -> int8x8x4_t; + fn _vld4_dup_s16(ptr: *const i16) -> int16x4x4_t; } - _vld4_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _) + _vld4_dup_s16(a as _) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_lane_s16(a: *const i16, b: int16x4x4_t) -> int16x4x4_t { - static_assert_uimm_bits!(LANE, 2); +pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4lane.v4i16.p0" + link_name = "llvm.aarch64.neon.ld4r.v8i16.p0.p0" )] - fn _vld4_lane_s16( - a: int16x4_t, - b: int16x4_t, - c: int16x4_t, - d: int16x4_t, - n: i64, - ptr: *const i8, - ) -> int16x4x4_t; + fn _vld4q_dup_s16(ptr: *const i16) -> int16x8x4_t; } - _vld4_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) + _vld4q_dup_s16(a as _) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_lane_s16(a: *const i16, b: int16x8x4_t) -> int16x8x4_t { - static_assert_uimm_bits!(LANE, 3); +pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4lane.v8i16.p0" + link_name = "llvm.aarch64.neon.ld4r.v2i32.p0.p0" )] - fn _vld4q_lane_s16( - a: int16x8_t, - b: int16x8_t, - c: int16x8_t, - d: int16x8_t, - n: i64, - ptr: *const i8, - ) -> int16x8x4_t; + fn _vld4_dup_s32(ptr: *const i32) -> int32x2x4_t; } - _vld4q_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) + _vld4_dup_s32(a as _) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_lane_s32(a: *const i32, b: int32x2x4_t) -> int32x2x4_t { - static_assert_uimm_bits!(LANE, 1); +pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4lane.v2i32.p0" + link_name = "llvm.aarch64.neon.ld4r.v4i32.p0.p0" )] - fn _vld4_lane_s32( - a: int32x2_t, - b: int32x2_t, - c: int32x2_t, - d: int32x2_t, - n: i64, - ptr: *const i8, - ) -> int32x2x4_t; + fn _vld4q_dup_s32(ptr: *const i32) -> int32x4x4_t; } - _vld4_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) + _vld4q_dup_s32(a as _) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_lane_s32(a: *const i32, b: int32x4x4_t) -> int32x4x4_t { - static_assert_uimm_bits!(LANE, 2); +pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4lane.v4i32.p0" + link_name = "llvm.aarch64.neon.ld4r.v1i64.p0.p0" )] - fn _vld4q_lane_s32( - a: int32x4_t, - b: int32x4_t, - c: int32x4_t, - d: int32x4_t, - n: i64, - ptr: *const i8, - ) -> int32x4x4_t; - } - _vld4q_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_lane_f32(a: *const f32, b: float32x2x4_t) -> float32x2x4_t { - static_assert_uimm_bits!(LANE, 1); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v2f32.p0")] - fn _vld4_lane_f32( - ptr: *const i8, - a: float32x2_t, - b: float32x2_t, - c: float32x2_t, - d: float32x2_t, - n: i32, - size: i32, - ) -> float32x2x4_t; - } - _vld4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_lane_f32(a: *const f32, b: float32x4x4_t) -> float32x4x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4f32.p0")] - fn _vld4q_lane_f32( - ptr: *const i8, - a: float32x4_t, - b: float32x4_t, - c: float32x4_t, - d: float32x4_t, - n: i32, - size: i32, - ) -> float32x4x4_t; - } - _vld4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_lane_s8(a: *const i8, b: int8x8x4_t) -> int8x8x4_t { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8i8.p0")] - fn _vld4_lane_s8( - ptr: *const i8, - a: int8x8_t, - b: int8x8_t, - c: int8x8_t, - d: int8x8_t, - n: i32, - size: i32, - ) -> int8x8x4_t; - } - _vld4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_lane_s16(a: *const i16, b: int16x4x4_t) -> int16x4x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4i16.p0")] - fn _vld4_lane_s16( - ptr: *const i8, - a: int16x4_t, - b: int16x4_t, - c: int16x4_t, - d: int16x4_t, - n: i32, - size: i32, - ) -> int16x4x4_t; + fn _vld4_dup_s64(ptr: *const i64) -> int64x1x4_t; } - _vld4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) + _vld4_dup_s64(a as _) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_lane_s16(a: *const i16, b: int16x8x4_t) -> int16x8x4_t { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8i16.p0")] - fn _vld4q_lane_s16( - ptr: *const i8, - a: int16x8_t, - b: int16x8_t, - c: int16x8_t, - d: int16x8_t, - n: i32, - size: i32, - ) -> int16x8x4_t; - } - _vld4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4_dup_p64(a: *const p64) -> poly64x1x4_t { + transmute(vld4_dup_s64(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] #[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_lane_s32(a: *const i32, b: int32x2x4_t) -> int32x2x4_t { - static_assert_uimm_bits!(LANE, 1); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v2i32.p0")] - fn _vld4_lane_s32( - ptr: *const i8, - a: int32x2_t, - b: int32x2_t, - c: int32x2_t, - d: int32x2_t, - n: i32, - size: i32, - ) -> int32x2x4_t; - } - _vld4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] #[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(nop))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_lane_s32(a: *const i32, b: int32x4x4_t) -> int32x4x4_t { - static_assert_uimm_bits!(LANE, 2); +pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4i32.p0")] - fn _vld4q_lane_s32( - ptr: *const i8, - a: int32x4_t, - b: int32x4_t, - c: int32x4_t, - d: int32x4_t, - n: i32, - size: i32, - ) -> int32x4x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v1i64.p0")] + fn _vld4_dup_s64(ptr: *const i8, size: i32) -> int64x1x4_t; } - _vld4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) + _vld4_dup_s64(a as *const i8, 8) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u8)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) + assert_instr(ld4r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -27314,23 +26125,21 @@ pub unsafe fn vld4q_lane_s32(a: *const i32, b: int32x4x4_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_lane_u8(a: *const u8, b: uint8x8x4_t) -> uint8x8x4_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld4_lane_s8::(transmute(a), transmute(b))) +pub unsafe fn vld4_dup_u64(a: *const u64) -> uint64x1x4_t { + transmute(vld4_dup_s64(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u16)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) + assert_instr(ld4r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -27339,23 +26148,21 @@ pub unsafe fn vld4_lane_u8(a: *const u8, b: uint8x8x4_t) -> uin target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_lane_u16(a: *const u16, b: uint16x4x4_t) -> uint16x4x4_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld4_lane_s16::(transmute(a), transmute(b))) +pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t { + transmute(vld4_dup_s8(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u16)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) + assert_instr(ld4r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -27364,23 +26171,21 @@ pub unsafe fn vld4_lane_u16(a: *const u16, b: uint16x4x4_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_lane_u16(a: *const u16, b: uint16x8x4_t) -> uint16x8x4_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld4q_lane_s16::(transmute(a), transmute(b))) +pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t { + transmute(vld4q_dup_s8(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u32)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) + assert_instr(ld4r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -27389,23 +26194,21 @@ pub unsafe fn vld4q_lane_u16(a: *const u16, b: uint16x8x4_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_lane_u32(a: *const u32, b: uint32x2x4_t) -> uint32x2x4_t { - static_assert_uimm_bits!(LANE, 1); - transmute(vld4_lane_s32::(transmute(a), transmute(b))) +pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t { + transmute(vld4_dup_s16(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u32)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) + assert_instr(ld4r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -27414,23 +26217,21 @@ pub unsafe fn vld4_lane_u32(a: *const u32, b: uint32x2x4_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_lane_u32(a: *const u32, b: uint32x4x4_t) -> uint32x4x4_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld4q_lane_s32::(transmute(a), transmute(b))) +pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t { + transmute(vld4q_dup_s16(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p8)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) + assert_instr(ld4r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -27439,23 +26240,21 @@ pub unsafe fn vld4q_lane_u32(a: *const u32, b: uint32x4x4_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_lane_p8(a: *const p8, b: poly8x8x4_t) -> poly8x8x4_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld4_lane_s8::(transmute(a), transmute(b))) +pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t { + transmute(vld4_dup_s32(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p16)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) + assert_instr(ld4r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -27464,23 +26263,21 @@ pub unsafe fn vld4_lane_p8(a: *const p8, b: poly8x8x4_t) -> pol target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_lane_p16(a: *const p16, b: poly16x4x4_t) -> poly16x4x4_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld4_lane_s16::(transmute(a), transmute(b))) +pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t { + transmute(vld4q_dup_s32(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p16)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) + assert_instr(ld4r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -27489,21 +26286,20 @@ pub unsafe fn vld4_lane_p16(a: *const p16, b: poly16x4x4_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_lane_p16(a: *const p16, b: poly16x8x4_t) -> poly16x8x4_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld4q_lane_s16::(transmute(a), transmute(b))) +pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t { + transmute(vld4_dup_s8(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p64)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ld4r) )] #[cfg_attr( not(target_arch = "arm"), @@ -27513,55 +26309,20 @@ pub unsafe fn vld4q_lane_p16(a: *const p16, b: poly16x8x4_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t { - transmute(vld4_s64(transmute(a))) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v1i64.p0" - )] - fn _vld4_s64(ptr: *const int64x1_t) -> int64x1x4_t; - } - _vld4_s64(a as _) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v1i64.p0")] - fn _vld4_s64(ptr: *const i8, size: i32) -> int64x1x4_t; - } - _vld4_s64(a as *const i8, 8) +pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t { + transmute(vld4q_dup_s8(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u64)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ld4r) )] #[cfg_attr( not(target_arch = "arm"), @@ -27571,21 +26332,20 @@ pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t { - transmute(vld4_s64(transmute(a))) +pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t { + transmute(vld4_dup_s16(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) + assert_instr(ld4r) )] #[cfg_attr( not(target_arch = "arm"), @@ -27595,685 +26355,812 @@ pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t { - transmute(vld4_s8(transmute(a))) +pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t { + transmute(vld4q_dup_s16(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"] +#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg(target_arch = "arm")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t { - let mut ret_val: uint8x8x4_t = transmute(vld4_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4f16.p0")] + fn _vld4_f16(ptr: *const f16, size: i32) -> float16x4x4_t; + } + _vld4_f16(a as _, 2) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"] +#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg(target_arch = "arm")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8f16.p0")] + fn _vld4q_f16(ptr: *const f16, size: i32) -> float16x8x4_t; + } + _vld4q_f16(a as _, 2) +} +#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4) )] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t { - transmute(vld4q_s8(transmute(a))) +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t { + crate::core_arch::macros::deinterleaving_load!(f16, 4, 4, a) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"] +#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[inline] +#[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4) )] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t { - let mut ret_val: uint8x16x4_t = transmute(vld4q_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.3 = unsafe { - simd_shuffle!( - ret_val.3, - ret_val.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t { + crate::core_arch::macros::deinterleaving_load!(f16, 8, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t { - transmute(vld4_s16(transmute(a))) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t { + crate::core_arch::macros::deinterleaving_load!(f32, 2, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t { - let mut ret_val: uint16x4x4_t = transmute(vld4_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t { + crate::core_arch::macros::deinterleaving_load!(f32, 4, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t { - transmute(vld4q_s16(transmute(a))) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t { + crate::core_arch::macros::deinterleaving_load!(i8, 8, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t { - let mut ret_val: uint16x8x4_t = transmute(vld4q_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t { + crate::core_arch::macros::deinterleaving_load!(i8, 16, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t { - transmute(vld4_s32(transmute(a))) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t { + crate::core_arch::macros::deinterleaving_load!(i16, 4, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t { - let mut ret_val: uint32x2x4_t = transmute(vld4_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; - ret_val +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t { + crate::core_arch::macros::deinterleaving_load!(i16, 8, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t { - transmute(vld4q_s32(transmute(a))) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t { + crate::core_arch::macros::deinterleaving_load!(i32, 2, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t { - let mut ret_val: uint32x4x4_t = transmute(vld4q_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t { + crate::core_arch::macros::deinterleaving_load!(i32, 4, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t { - transmute(vld4_s8(transmute(a))) +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v2f32.p0")] + fn _vld4_f32(ptr: *const i8, size: i32) -> float32x2x4_t; + } + _vld4_f32(a as *const i8, 4) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t { - let mut ret_val: poly8x8x4_t = transmute(vld4_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4f32.p0")] + fn _vld4q_f32(ptr: *const i8, size: i32) -> float32x4x4_t; + } + _vld4q_f32(a as *const i8, 4) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t { - transmute(vld4q_s8(transmute(a))) +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8i8.p0")] + fn _vld4_s8(ptr: *const i8, size: i32) -> int8x8x4_t; + } + _vld4_s8(a as *const i8, 1) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t { - let mut ret_val: poly8x16x4_t = transmute(vld4q_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.3 = unsafe { - simd_shuffle!( - ret_val.3, - ret_val.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v16i8.p0")] + fn _vld4q_s8(ptr: *const i8, size: i32) -> int8x16x4_t; + } + _vld4q_s8(a as *const i8, 1) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t { - transmute(vld4_s16(transmute(a))) +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4i16.p0")] + fn _vld4_s16(ptr: *const i8, size: i32) -> int16x4x4_t; + } + _vld4_s16(a as *const i8, 2) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t { - let mut ret_val: poly16x4x4_t = transmute(vld4_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8i16.p0")] + fn _vld4q_s16(ptr: *const i8, size: i32) -> int16x8x4_t; + } + _vld4q_s16(a as *const i8, 2) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t { - transmute(vld4q_s16(transmute(a))) +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v2i32.p0")] + fn _vld4_s32(ptr: *const i8, size: i32) -> int32x2x4_t; + } + _vld4_s32(a as *const i8, 4) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t { - let mut ret_val: poly16x8x4_t = transmute(vld4q_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4i32.p0")] + fn _vld4q_s32(ptr: *const i8, size: i32) -> int32x4x4_t; + } + _vld4q_s32(a as *const i8, 4) } -#[doc = "Store SIMD&FP register (immediate offset)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldrq_p128)"] +#[doc = "Load multiple 4-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vldrq_p128(a: *const p128) -> p128 { - *a -} -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmax) -)] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub fn vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { +pub unsafe fn vld4_lane_f16(a: *const f16, b: float16x4x4_t) -> float16x4x4_t { + static_assert_uimm_bits!(LANE, 2); unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4f16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmax.v4f16" - )] - fn _vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4f16.p0")] + fn _vld4_lane_f16( + ptr: *const f16, + a: float16x4_t, + b: float16x4_t, + c: float16x4_t, + d: float16x4_t, + n: i32, + size: i32, + ) -> float16x4x4_t; } - unsafe { _vmax_f16(a, b) } + _vld4_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmax) -)] +#[doc = "Load multiple 4-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld4q_lane_f16(a: *const f16, b: float16x8x4_t) -> float16x8x4_t { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8f16.p0")] + fn _vld4q_lane_f16( + ptr: *const f16, + a: float16x8_t, + b: float16x8_t, + c: float16x8_t, + d: float16x8_t, + n: i32, + size: i32, + ) -> float16x8x4_t; + } + _vld4q_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2) +} +#[doc = "Load multiple 4-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(not(target_arch = "arm"))] #[cfg_attr( - not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub fn vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub unsafe fn vld4_lane_f16(a: *const f16, b: float16x4x4_t) -> float16x4x4_t { + static_assert_uimm_bits!(LANE, 2); unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8f16")] #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmax.v8f16" + link_name = "llvm.aarch64.neon.ld4lane.v4f16.p0" )] - fn _vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + fn _vld4_lane_f16( + a: float16x4_t, + b: float16x4_t, + c: float16x4_t, + d: float16x4_t, + n: i64, + ptr: *const f16, + ) -> float16x4x4_t; } - unsafe { _vmaxq_f16(a, b) } + _vld4_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[doc = "Load multiple 4-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmax) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(ld4, LANE = 0) )] -pub fn vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld4q_lane_f16(a: *const f16, b: float16x8x4_t) -> float16x8x4_t { + static_assert_uimm_bits!(LANE, 3); unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v2f32")] #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmax.v2f32" + link_name = "llvm.aarch64.neon.ld4lane.v8f16.p0" )] - fn _vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + fn _vld4q_lane_f16( + a: float16x8_t, + b: float16x8_t, + c: float16x8_t, + d: float16x8_t, + n: i64, + ptr: *const f16, + ) -> float16x8x4_t; } - unsafe { _vmax_f32(a, b) } + _vld4q_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4_lane_f32(a: *const f32, b: float32x2x4_t) -> float32x2x4_t { + static_assert_uimm_bits!(LANE, 1); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v2f32.p0" + )] + fn _vld4_lane_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, + d: float32x2_t, + n: i64, + ptr: *const i8, + ) -> float32x2x4_t; + } + _vld4_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) +} +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4q_lane_f32(a: *const f32, b: float32x4x4_t) -> float32x4x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v4f32.p0" + )] + fn _vld4q_lane_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, + d: float32x4_t, + n: i64, + ptr: *const i8, + ) -> float32x4x4_t; + } + _vld4q_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) +} +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4_lane_s8(a: *const i8, b: int8x8x4_t) -> int8x8x4_t { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v8i8.p0" + )] + fn _vld4_lane_s8( + a: int8x8_t, + b: int8x8_t, + c: int8x8_t, + d: int8x8_t, + n: i64, + ptr: *const i8, + ) -> int8x8x4_t; + } + _vld4_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _) +} +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4_lane_s16(a: *const i16, b: int16x4x4_t) -> int16x4x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v4i16.p0" + )] + fn _vld4_lane_s16( + a: int16x4_t, + b: int16x4_t, + c: int16x4_t, + d: int16x4_t, + n: i64, + ptr: *const i8, + ) -> int16x4x4_t; + } + _vld4_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) +} +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4q_lane_s16(a: *const i16, b: int16x8x4_t) -> int16x8x4_t { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v8i16.p0" + )] + fn _vld4q_lane_s16( + a: int16x8_t, + b: int16x8_t, + c: int16x8_t, + d: int16x8_t, + n: i64, + ptr: *const i8, + ) -> int16x8x4_t; + } + _vld4q_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) +} +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4_lane_s32(a: *const i32, b: int32x2x4_t) -> int32x2x4_t { + static_assert_uimm_bits!(LANE, 1); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v2i32.p0" + )] + fn _vld4_lane_s32( + a: int32x2_t, + b: int32x2_t, + c: int32x2_t, + d: int32x2_t, + n: i64, + ptr: *const i8, + ) -> int32x2x4_t; + } + _vld4_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) +} +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4q_lane_s32(a: *const i32, b: int32x4x4_t) -> int32x4x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v4i32.p0" + )] + fn _vld4q_lane_s32( + a: int32x4_t, + b: int32x4_t, + c: int32x4_t, + d: int32x4_t, + n: i64, + ptr: *const i8, + ) -> int32x4x4_t; + } + _vld4q_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) +} +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4_lane_f32(a: *const f32, b: float32x2x4_t) -> float32x2x4_t { + static_assert_uimm_bits!(LANE, 1); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v2f32.p0")] + fn _vld4_lane_f32( + ptr: *const i8, + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, + d: float32x2_t, + n: i32, + size: i32, + ) -> float32x2x4_t; + } + _vld4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) +} +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4q_lane_f32(a: *const f32, b: float32x4x4_t) -> float32x4x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4f32.p0")] + fn _vld4q_lane_f32( + ptr: *const i8, + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, + d: float32x4_t, + n: i32, + size: i32, + ) -> float32x4x4_t; + } + _vld4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) +} +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4_lane_s8(a: *const i8, b: int8x8x4_t) -> int8x8x4_t { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8i8.p0")] + fn _vld4_lane_s8( + ptr: *const i8, + a: int8x8_t, + b: int8x8_t, + c: int8x8_t, + d: int8x8_t, + n: i32, + size: i32, + ) -> int8x8x4_t; + } + _vld4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1) +} +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4_lane_s16(a: *const i16, b: int16x4x4_t) -> int16x4x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4i16.p0")] + fn _vld4_lane_s16( + ptr: *const i8, + a: int16x4_t, + b: int16x4_t, + c: int16x4_t, + d: int16x4_t, + n: i32, + size: i32, + ) -> int16x4x4_t; + } + _vld4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) +} +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4q_lane_s16(a: *const i16, b: int16x8x4_t) -> int16x8x4_t { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8i16.p0")] + fn _vld4q_lane_s16( + ptr: *const i8, + a: int16x8_t, + b: int16x8_t, + c: int16x8_t, + d: int16x8_t, + n: i32, + size: i32, + ) -> int16x8x4_t; + } + _vld4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) +} +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4_lane_s32(a: *const i32, b: int32x2x4_t) -> int32x2x4_t { + static_assert_uimm_bits!(LANE, 1); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v2i32.p0")] + fn _vld4_lane_s32( + ptr: *const i8, + a: int32x2_t, + b: int32x2_t, + c: int32x2_t, + d: int32x2_t, + n: i32, + size: i32, + ) -> int32x2x4_t; + } + _vld4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) +} +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4q_lane_s32(a: *const i32, b: int32x4x4_t) -> int32x4x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4i32.p0")] + fn _vld4q_lane_s32( + ptr: *const i8, + a: int32x4_t, + b: int32x4_t, + c: int32x4_t, + d: int32x4_t, + n: i32, + size: i32, + ) -> int32x4x4_t; + } + _vld4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) +} +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmax) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -28282,27 +27169,23 @@ pub fn vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4f32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmax.v4f32" - )] - fn _vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; - } - unsafe { _vmaxq_f32(a, b) } +pub unsafe fn vld4_lane_u8(a: *const u8, b: uint8x8x4_t) -> uint8x8x4_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld4_lane_s8::(transmute(a), transmute(b))) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s8)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smax) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -28311,22 +27194,23 @@ pub fn vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe { - let mask: int8x8_t = simd_ge(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld4_lane_u16(a: *const u16, b: uint16x4x4_t) -> uint16x4x4_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld4_lane_s16::(transmute(a), transmute(b))) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s8)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smax) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -28335,22 +27219,23 @@ pub fn vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe { - let mask: int8x16_t = simd_ge(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld4q_lane_u16(a: *const u16, b: uint16x8x4_t) -> uint16x8x4_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld4q_lane_s16::(transmute(a), transmute(b))) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s16)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smax) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -28359,22 +27244,23 @@ pub fn vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe { - let mask: int16x4_t = simd_ge(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld4_lane_u32(a: *const u32, b: uint32x2x4_t) -> uint32x2x4_t { + static_assert_uimm_bits!(LANE, 1); + transmute(vld4_lane_s32::(transmute(a), transmute(b))) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s16)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smax) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -28383,22 +27269,23 @@ pub fn vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe { - let mask: int16x8_t = simd_ge(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld4q_lane_u32(a: *const u32, b: uint32x4x4_t) -> uint32x4x4_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld4q_lane_s32::(transmute(a), transmute(b))) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smax) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -28407,22 +27294,23 @@ pub fn vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe { - let mask: int32x2_t = simd_ge(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld4_lane_p8(a: *const p8, b: poly8x8x4_t) -> poly8x8x4_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld4_lane_s8::(transmute(a), transmute(b))) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smax) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -28431,22 +27319,23 @@ pub fn vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe { - let mask: int32x4_t = simd_ge(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld4_lane_p16(a: *const p16, b: poly16x4x4_t) -> poly16x4x4_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld4_lane_s16::(transmute(a), transmute(b))) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u8)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umax) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -28455,21 +27344,72 @@ pub fn vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - unsafe { - let mask: uint8x8_t = simd_ge(a, b); - simd_select(mask, a, b) +pub unsafe fn vld4q_lane_p16(a: *const p16, b: poly16x8x4_t) -> poly16x8x4_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld4q_lane_s16::(transmute(a), transmute(b))) +} +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t { + transmute(vld4_s64(transmute(a))) +} +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { + crate::ptr::read_unaligned(a.cast()) +} +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v1i64.p0")] + fn _vld4_s64(ptr: *const i8, size: i32) -> int64x1x4_t; } + _vld4_s64(a as *const i8, 8) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u8)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umax) + assert_instr(nop) )] #[cfg_attr( not(target_arch = "arm"), @@ -28479,21 +27419,20 @@ pub fn vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - unsafe { - let mask: uint8x16_t = simd_ge(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t { + transmute(vld4_s64(transmute(a))) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u16)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umax) + assert_instr(ld4) )] #[cfg_attr( not(target_arch = "arm"), @@ -28503,21 +27442,20 @@ pub fn vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - unsafe { - let mask: uint16x4_t = simd_ge(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t { + transmute(vld4_s8(transmute(a))) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u16)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umax) + assert_instr(ld4) )] #[cfg_attr( not(target_arch = "arm"), @@ -28527,21 +27465,20 @@ pub fn vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - unsafe { - let mask: uint16x8_t = simd_ge(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t { + transmute(vld4q_s8(transmute(a))) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umax) + assert_instr(ld4) )] #[cfg_attr( not(target_arch = "arm"), @@ -28551,21 +27488,20 @@ pub fn vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - unsafe { - let mask: uint32x2_t = simd_ge(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t { + transmute(vld4_s16(transmute(a))) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umax) + assert_instr(ld4) )] #[cfg_attr( not(target_arch = "arm"), @@ -28575,65 +27511,66 @@ pub fn vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - unsafe { - let mask: uint32x4_t = simd_ge(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t { + transmute(vld4q_s16(transmute(a))) } -#[doc = "Floating-point Maximum Number (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmaxnm) + assert_instr(ld4) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - unsafe { simd_fmax(a, b) } +pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t { + transmute(vld4_s32(transmute(a))) } -#[doc = "Floating-point Maximum Number (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmaxnm) + assert_instr(ld4) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - unsafe { simd_fmax(a, b) } +pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t { + transmute(vld4q_s32(transmute(a))) } -#[doc = "Floating-point Maximum Number (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmaxnm) + assert_instr(ld4) )] #[cfg_attr( not(target_arch = "arm"), @@ -28643,18 +27580,20 @@ pub fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - unsafe { simd_fmax(a, b) } +pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t { + transmute(vld4_s8(transmute(a))) } -#[doc = "Floating-point Maximum Number (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmaxnm) + assert_instr(ld4) )] #[cfg_attr( not(target_arch = "arm"), @@ -28664,78 +27603,147 @@ pub fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - unsafe { simd_fmax(a, b) } +pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t { + transmute(vld4q_s8(transmute(a))) } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f16)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t { + transmute(vld4_s16(transmute(a))) +} +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t { + transmute(vld4q_s16(transmute(a))) +} +#[doc = "Store SIMD&FP register (immediate offset)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldrq_p128)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vldrq_p128(a: *const p128) -> p128 { + *a +} +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f16)"] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmin) + assert_instr(fmax) )] #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { +pub fn vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4f16")] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4f16")] #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmin.v4f16" + link_name = "llvm.aarch64.neon.fmax.v4f16" )] - fn _vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + fn _vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; } - unsafe { _vmin_f16(a, b) } + unsafe { _vmax_f16(a, b) } } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f16)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f16)"] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmin) + assert_instr(fmax) )] #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub fn vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8f16")] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8f16")] #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmin.v8f16" + link_name = "llvm.aarch64.neon.fmax.v8f16" )] - fn _vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + fn _vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; } - unsafe { _vminq_f16(a, b) } + unsafe { _vmaxq_f16(a, b) } } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f32)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmin) + assert_instr(fmax) )] #[cfg_attr( not(target_arch = "arm"), @@ -28745,26 +27753,26 @@ pub fn vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +pub fn vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v2f32")] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v2f32")] #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmin.v2f32" + link_name = "llvm.aarch64.neon.fmax.v2f32" )] - fn _vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + fn _vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; } - unsafe { _vmin_f32(a, b) } + unsafe { _vmax_f32(a, b) } } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f32)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmin) + assert_instr(fmax) )] #[cfg_attr( not(target_arch = "arm"), @@ -28774,26 +27782,26 @@ pub fn vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { +pub fn vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4f32")] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4f32")] #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmin.v4f32" + link_name = "llvm.aarch64.neon.fmax.v4f32" )] - fn _vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + fn _vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; } - unsafe { _vminq_f32(a, b) } + unsafe { _vmaxq_f32(a, b) } } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s8)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smin) + assert_instr(smax) )] #[cfg_attr( not(target_arch = "arm"), @@ -28803,21 +27811,21 @@ pub fn vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe { - let mask: int8x8_t = simd_le(a, b); + let mask: int8x8_t = simd_ge(a, b); simd_select(mask, a, b) } } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s8)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smin) + assert_instr(smax) )] #[cfg_attr( not(target_arch = "arm"), @@ -28827,21 +27835,21 @@ pub fn vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe { - let mask: int8x16_t = simd_le(a, b); + let mask: int8x16_t = simd_ge(a, b); simd_select(mask, a, b) } } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s16)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smin) + assert_instr(smax) )] #[cfg_attr( not(target_arch = "arm"), @@ -28851,21 +27859,21 @@ pub fn vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe { - let mask: int16x4_t = simd_le(a, b); + let mask: int16x4_t = simd_ge(a, b); simd_select(mask, a, b) } } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s16)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smin) + assert_instr(smax) )] #[cfg_attr( not(target_arch = "arm"), @@ -28875,21 +27883,21 @@ pub fn vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe { - let mask: int16x8_t = simd_le(a, b); + let mask: int16x8_t = simd_ge(a, b); simd_select(mask, a, b) } } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s32)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smin) + assert_instr(smax) )] #[cfg_attr( not(target_arch = "arm"), @@ -28899,21 +27907,21 @@ pub fn vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe { - let mask: int32x2_t = simd_le(a, b); + let mask: int32x2_t = simd_ge(a, b); simd_select(mask, a, b) } } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s32)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smin) + assert_instr(smax) )] #[cfg_attr( not(target_arch = "arm"), @@ -28923,21 +27931,21 @@ pub fn vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe { - let mask: int32x4_t = simd_le(a, b); + let mask: int32x4_t = simd_ge(a, b); simd_select(mask, a, b) } } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u8)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umin) + assert_instr(umax) )] #[cfg_attr( not(target_arch = "arm"), @@ -28947,21 +27955,21 @@ pub fn vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe { - let mask: uint8x8_t = simd_le(a, b); + let mask: uint8x8_t = simd_ge(a, b); simd_select(mask, a, b) } } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u8)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umin) + assert_instr(umax) )] #[cfg_attr( not(target_arch = "arm"), @@ -28971,21 +27979,21 @@ pub fn vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { +pub fn vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe { - let mask: uint8x16_t = simd_le(a, b); + let mask: uint8x16_t = simd_ge(a, b); simd_select(mask, a, b) } } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u16)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umin) + assert_instr(umax) )] #[cfg_attr( not(target_arch = "arm"), @@ -28995,21 +28003,21 @@ pub fn vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe { - let mask: uint16x4_t = simd_le(a, b); + let mask: uint16x4_t = simd_ge(a, b); simd_select(mask, a, b) } } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u16)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umin) + assert_instr(umax) )] #[cfg_attr( not(target_arch = "arm"), @@ -29019,21 +28027,21 @@ pub fn vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe { - let mask: uint16x8_t = simd_le(a, b); + let mask: uint16x8_t = simd_ge(a, b); simd_select(mask, a, b) } } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u32)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umin) + assert_instr(umax) )] #[cfg_attr( not(target_arch = "arm"), @@ -29043,21 +28051,21 @@ pub fn vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe { - let mask: uint32x2_t = simd_le(a, b); + let mask: uint32x2_t = simd_ge(a, b); simd_select(mask, a, b) } } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u32)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umin) + assert_instr(umax) )] #[cfg_attr( not(target_arch = "arm"), @@ -29067,65 +28075,81 @@ pub fn vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe { - let mask: uint32x4_t = simd_le(a, b); + let mask: uint32x4_t = simd_ge(a, b); simd_select(mask, a, b) } } -#[doc = "Floating-point Minimum Number (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f16)"] -#[inline(always)] +#[doc = "Floating-point Maximum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f16)"] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fminnm) + assert_instr(fmaxnm) )] #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - unsafe { simd_fmin(a, b) } +pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnm.v4f16" + )] + fn _vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { _vmaxnm_f16(a, b) } } -#[doc = "Floating-point Minimum Number (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f16)"] -#[inline(always)] +#[doc = "Floating-point Maximum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f16)"] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fminnm) + assert_instr(fmaxnm) )] #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - unsafe { simd_fmin(a, b) } +pub fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v8f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnm.v8f16" + )] + fn _vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { _vmaxnmq_f16(a, b) } } -#[doc = "Floating-point Minimum Number (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f32)"] -#[inline(always)] +#[doc = "Floating-point Maximum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fminnm) + assert_instr(fmaxnm) )] #[cfg_attr( not(target_arch = "arm"), @@ -29135,18 +28159,26 @@ pub fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - unsafe { simd_fmin(a, b) } +pub fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnm.v2f32" + )] + fn _vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + unsafe { _vmaxnm_f32(a, b) } } -#[doc = "Floating-point Minimum Number (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f32)"] -#[inline(always)] +#[doc = "Floating-point Maximum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fminnm) + assert_instr(fmaxnm) )] #[cfg_attr( not(target_arch = "arm"), @@ -29156,62 +28188,87 @@ pub fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - unsafe { simd_fmin(a, b) } +pub fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnm.v4f32" + )] + fn _vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + unsafe { _vmaxnmq_f32(a, b) } } -#[doc = "Floating-point multiply-add to accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul) + assert_instr(fmin) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - unsafe { simd_add(a, simd_mul(b, c)) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmin.v4f16" + )] + fn _vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { _vmin_f16(a, b) } } -#[doc = "Floating-point multiply-add to accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul) + assert_instr(fmin) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - unsafe { simd_add(a, simd_mul(b, c)) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmin.v8f16" + )] + fn _vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { _vminq_f16(a, b) } } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_f32)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul, LANE = 1) + assert_instr(fmin) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -29220,25 +28277,27 @@ pub fn vmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmla_lane_f32( - a: float32x2_t, - b: float32x2_t, - c: float32x2_t, -) -> float32x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } +pub fn vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmin.v2f32" + )] + fn _vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + unsafe { _vmin_f32(a, b) } } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_f32)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul, LANE = 1) + assert_instr(fmin) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -29247,25 +28306,27 @@ pub fn vmla_lane_f32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmla_laneq_f32( - a: float32x2_t, - b: float32x2_t, - c: float32x4_t, -) -> float32x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } +pub fn vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmin.v4f32" + )] + fn _vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + unsafe { _vminq_f32(a, b) } } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_f32)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul, LANE = 1) + assert_instr(smin) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -29274,31 +28335,22 @@ pub fn vmla_laneq_f32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmlaq_lane_f32( - a: float32x4_t, - b: float32x4_t, - c: float32x2_t, -) -> float32x4_t { - static_assert_uimm_bits!(LANE, 1); +pub fn vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe { - vmlaq_f32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + let mask: int8x8_t = simd_le(a, b); + simd_select(mask, a, b) } } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_f32)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul, LANE = 1) + assert_instr(smin) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -29307,31 +28359,22 @@ pub fn vmlaq_lane_f32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmlaq_laneq_f32( - a: float32x4_t, - b: float32x4_t, - c: float32x4_t, -) -> float32x4_t { - static_assert_uimm_bits!(LANE, 2); +pub fn vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe { - vmlaq_f32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + let mask: int8x16_t = simd_le(a, b); + simd_select(mask, a, b) } } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s16)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) + assert_instr(smin) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -29340,27 +28383,22 @@ pub fn vmlaq_laneq_f32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmla_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 2); +pub fn vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe { - vmla_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + let mask: int16x4_t = simd_le(a, b); + simd_select(mask, a, b) } } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u16)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) + assert_instr(smin) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -29369,27 +28407,22 @@ pub fn vmla_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmla_lane_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(LANE, 2); +pub fn vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe { - vmla_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + let mask: int16x8_t = simd_le(a, b); + simd_select(mask, a, b) } } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s16)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) + assert_instr(smin) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -29398,27 +28431,22 @@ pub fn vmla_lane_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmla_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 3); +pub fn vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe { - vmla_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + let mask: int32x2_t = simd_le(a, b); + simd_select(mask, a, b) } } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u16)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) + assert_instr(smin) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -29427,27 +28455,22 @@ pub fn vmla_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmla_laneq_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x8_t) -> uint16x4_t { - static_assert_uimm_bits!(LANE, 3); +pub fn vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe { - vmla_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + let mask: int32x4_t = simd_le(a, b); + simd_select(mask, a, b) } } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s16)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) + assert_instr(umin) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -29456,40 +28479,22 @@ pub fn vmla_laneq_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x8 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmlaq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 2); +pub fn vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe { - vmlaq_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + let mask: uint8x8_t = simd_le(a, b); + simd_select(mask, a, b) } } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u16)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) + assert_instr(umin) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -29498,40 +28503,22 @@ pub fn vmlaq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x4_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmlaq_lane_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t { - static_assert_uimm_bits!(LANE, 2); +pub fn vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe { - vmlaq_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + let mask: uint8x16_t = simd_le(a, b); + simd_select(mask, a, b) } } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s16)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) + assert_instr(umin) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -29540,40 +28527,22 @@ pub fn vmlaq_lane_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x4 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmlaq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 3); +pub fn vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe { - vmlaq_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + let mask: uint16x4_t = simd_le(a, b); + simd_select(mask, a, b) } } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u16)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) + assert_instr(umin) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -29582,40 +28551,22 @@ pub fn vmlaq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmlaq_laneq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { - static_assert_uimm_bits!(LANE, 3); +pub fn vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe { - vmlaq_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + let mask: uint16x8_t = simd_le(a, b); + simd_select(mask, a, b) } } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s32)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) + assert_instr(umin) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -29624,21 +28575,22 @@ pub fn vmlaq_laneq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmla_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } +pub fn vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { + let mask: uint32x2_t = simd_le(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u32)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) + assert_instr(umin) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -29647,67 +28599,82 @@ pub fn vmla_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmla_lane_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } +pub fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { + let mask: uint32x4_t = simd_le(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] +#[doc = "Floating-point Minimum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) + assert_instr(fminnm) )] -#[rustc_legacy_const_generics(3)] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmla_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnm.v4f16" + )] + fn _vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { _vminnm_f16(a, b) } } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] +#[doc = "Floating-point Minimum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) + assert_instr(fminnm) )] -#[rustc_legacy_const_generics(3)] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmla_laneq_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v8f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnm.v8f16" + )] + fn _vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { _vminnmq_f16(a, b) } } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s32)"] -#[inline(always)] +#[doc = "Floating-point Minimum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) + assert_instr(fminnm) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -29716,19 +28683,498 @@ pub fn vmla_laneq_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x4 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmlaq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { - vmlaq_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) +pub fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnm.v2f32" + )] + fn _vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; } + unsafe { _vminnm_f32(a, b) } } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u32)"] -#[inline(always)] +#[doc = "Floating-point Minimum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fminnm) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnm.v4f32" + )] + fn _vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + unsafe { _vminnmq_f32(a, b) } +} +#[doc = "Floating-point multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + unsafe { simd_add(a, simd_mul(b, c)) } +} +#[doc = "Floating-point multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + unsafe { simd_add(a, simd_mul(b, c)) } +} +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_f32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmla_lane_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, +) -> float32x2_t { + static_assert_uimm_bits!(LANE, 1); + vmla_f32(a, b, vdup_lane_f32::(c)) +} +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_f32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmla_laneq_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x4_t, +) -> float32x2_t { + static_assert_uimm_bits!(LANE, 2); + vmla_f32(a, b, vdup_laneq_f32::(c)) +} +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_f32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmlaq_lane_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x2_t, +) -> float32x4_t { + static_assert_uimm_bits!(LANE, 1); + vmlaq_f32(a, b, vdupq_lane_f32::(c)) +} +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_f32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmlaq_laneq_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, +) -> float32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmlaq_f32(a, b, vdupq_laneq_f32::(c)) +} +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmla_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(LANE, 2); + vmla_s16(a, b, vdup_lane_s16::(c)) +} +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmla_lane_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(LANE, 2); + vmla_u16(a, b, vdup_lane_u16::(c)) +} +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmla_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t { + static_assert_uimm_bits!(LANE, 3); + vmla_s16(a, b, vdup_laneq_s16::(c)) +} +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmla_laneq_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x8_t) -> uint16x4_t { + static_assert_uimm_bits!(LANE, 3); + vmla_u16(a, b, vdup_laneq_u16::(c)) +} +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmlaq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t { + static_assert_uimm_bits!(LANE, 2); + vmlaq_s16(a, b, vdupq_lane_s16::(c)) +} +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmlaq_lane_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t { + static_assert_uimm_bits!(LANE, 2); + vmlaq_u16(a, b, vdupq_lane_u16::(c)) +} +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmlaq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(LANE, 3); + vmlaq_s16(a, b, vdupq_laneq_s16::(c)) +} +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmlaq_laneq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(LANE, 3); + vmlaq_u16(a, b, vdupq_laneq_u16::(c)) +} +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmla_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); + vmla_s32(a, b, vdup_lane_s32::(c)) +} +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmla_lane_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 1); + vmla_u32(a, b, vdup_lane_u32::(c)) +} +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmla_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + vmla_s32(a, b, vdup_laneq_s32::(c)) +} +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmla_laneq_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 2); + vmla_u32(a, b, vdup_laneq_u32::(c)) +} +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmlaq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 1); + vmlaq_s32(a, b, vdupq_lane_s32::(c)) +} +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] @@ -29747,17 +29193,11 @@ pub fn vmlaq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x2_t) )] pub fn vmlaq_lane_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - vmlaq_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlaq_u32(a, b, vdupq_lane_u32::(c)) } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] @@ -29776,17 +29216,11 @@ pub fn vmlaq_lane_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x2 )] pub fn vmlaq_laneq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlaq_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlaq_s32(a, b, vdupq_laneq_s32::(c)) } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] @@ -29805,17 +29239,11 @@ pub fn vmlaq_laneq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t )] pub fn vmlaq_laneq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlaq_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlaq_u32(a, b, vdupq_laneq_u32::(c)) } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))] @@ -29836,7 +29264,7 @@ pub fn vmla_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))] @@ -29857,7 +29285,7 @@ pub fn vmlaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] @@ -29878,7 +29306,7 @@ pub fn vmla_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t { } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] @@ -29899,7 +29327,7 @@ pub fn vmlaq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t { } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] @@ -29920,7 +29348,7 @@ pub fn vmla_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t { } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] @@ -29941,7 +29369,7 @@ pub fn vmlaq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t { } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] @@ -29962,7 +29390,7 @@ pub fn vmla_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t { } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] @@ -29983,7 +29411,7 @@ pub fn vmlaq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t { } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] @@ -30004,7 +29432,7 @@ pub fn vmla_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t { } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] @@ -30025,7 +29453,7 @@ pub fn vmlaq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t { } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))] @@ -30046,7 +29474,7 @@ pub fn vmla_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))] @@ -30067,7 +29495,7 @@ pub fn vmlaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] @@ -30088,7 +29516,7 @@ pub fn vmla_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] @@ -30109,7 +29537,7 @@ pub fn vmlaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] @@ -30130,7 +29558,7 @@ pub fn vmla_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] @@ -30151,7 +29579,7 @@ pub fn vmlaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))] @@ -30172,7 +29600,7 @@ pub fn vmla_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))] @@ -30193,7 +29621,7 @@ pub fn vmlaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] @@ -30214,7 +29642,7 @@ pub fn vmla_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] @@ -30235,7 +29663,7 @@ pub fn vmlaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] @@ -30256,7 +29684,7 @@ pub fn vmla_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] @@ -30277,7 +29705,7 @@ pub fn vmlaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))] @@ -30296,17 +29724,11 @@ pub fn vmlaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { )] pub fn vmlal_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlal_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlal_s16(a, b, vdup_lane_s16::(c)) } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))] @@ -30325,17 +29747,11 @@ pub fn vmlal_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) )] pub fn vmlal_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmlal_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlal_s16(a, b, vdup_laneq_s16::(c)) } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))] @@ -30354,11 +29770,11 @@ pub fn vmlal_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t )] pub fn vmlal_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } + vmlal_s32(a, b, vdup_lane_s32::(c)) } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))] @@ -30377,11 +29793,11 @@ pub fn vmlal_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) )] pub fn vmlal_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } + vmlal_s32(a, b, vdup_laneq_s32::(c)) } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))] @@ -30400,17 +29816,11 @@ pub fn vmlal_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t )] pub fn vmlal_lane_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlal_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlal_u16(a, b, vdup_lane_u16::(c)) } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))] @@ -30429,17 +29839,11 @@ pub fn vmlal_lane_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4 )] pub fn vmlal_laneq_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x8_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmlal_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlal_u16(a, b, vdup_laneq_u16::(c)) } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))] @@ -30458,11 +29862,11 @@ pub fn vmlal_laneq_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x )] pub fn vmlal_lane_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } + vmlal_u32(a, b, vdup_lane_u32::(c)) } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))] @@ -30481,11 +29885,11 @@ pub fn vmlal_lane_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2 )] pub fn vmlal_laneq_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x4_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } + vmlal_u32(a, b, vdup_laneq_u32::(c)) } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))] @@ -30506,7 +29910,7 @@ pub fn vmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))] @@ -30527,7 +29931,7 @@ pub fn vmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))] @@ -30548,7 +29952,7 @@ pub fn vmlal_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t { } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))] @@ -30569,7 +29973,7 @@ pub fn vmlal_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t { } #[doc = "Signed multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s8"))] @@ -30590,7 +29994,7 @@ pub fn vmlal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { } #[doc = "Signed multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))] @@ -30611,7 +30015,7 @@ pub fn vmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { } #[doc = "Signed multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))] @@ -30632,7 +30036,7 @@ pub fn vmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { } #[doc = "Unsigned multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u8"))] @@ -30653,7 +30057,7 @@ pub fn vmlal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t { } #[doc = "Unsigned multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))] @@ -30674,7 +30078,7 @@ pub fn vmlal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { } #[doc = "Unsigned multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))] @@ -30695,7 +30099,7 @@ pub fn vmlal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { } #[doc = "Floating-point multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))] @@ -30716,7 +30120,7 @@ pub fn vmls_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { } #[doc = "Floating-point multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))] @@ -30737,7 +30141,7 @@ pub fn vmlsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))] @@ -30760,11 +30164,11 @@ pub fn vmls_lane_f32( c: float32x2_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } + vmls_f32(a, b, vdup_lane_f32::(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))] @@ -30787,11 +30191,11 @@ pub fn vmls_laneq_f32( c: float32x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } + vmls_f32(a, b, vdup_laneq_f32::(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))] @@ -30814,17 +30218,11 @@ pub fn vmlsq_lane_f32( c: float32x2_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - vmlsq_f32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlsq_f32(a, b, vdupq_lane_f32::(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))] @@ -30847,17 +30245,11 @@ pub fn vmlsq_laneq_f32( c: float32x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlsq_f32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlsq_f32(a, b, vdupq_laneq_f32::(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] @@ -30876,17 +30268,11 @@ pub fn vmlsq_laneq_f32( )] pub fn vmls_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmls_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmls_s16(a, b, vdup_lane_s16::(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] @@ -30905,17 +30291,11 @@ pub fn vmls_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) )] pub fn vmls_lane_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmls_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmls_u16(a, b, vdup_lane_u16::(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] @@ -30934,17 +30314,11 @@ pub fn vmls_lane_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_ )] pub fn vmls_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmls_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmls_s16(a, b, vdup_laneq_s16::(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] @@ -30963,17 +30337,11 @@ pub fn vmls_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) )] pub fn vmls_laneq_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x8_t) -> uint16x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmls_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmls_u16(a, b, vdup_laneq_u16::(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] @@ -30992,30 +30360,11 @@ pub fn vmls_laneq_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x8 )] pub fn vmlsq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlsq_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + vmlsq_s16(a, b, vdupq_lane_s16::(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] @@ -31034,30 +30383,11 @@ pub fn vmlsq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x4_t) )] pub fn vmlsq_lane_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlsq_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + vmlsq_u16(a, b, vdupq_lane_u16::(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] @@ -31076,30 +30406,11 @@ pub fn vmlsq_lane_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x4 )] pub fn vmlsq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmlsq_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + vmlsq_s16(a, b, vdupq_laneq_s16::(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] @@ -31118,30 +30429,11 @@ pub fn vmlsq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t )] pub fn vmlsq_laneq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmlsq_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + vmlsq_u16(a, b, vdupq_laneq_u16::(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] @@ -31160,11 +30452,11 @@ pub fn vmlsq_laneq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x )] pub fn vmls_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } + vmls_s32(a, b, vdup_lane_s32::(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] @@ -31183,11 +30475,11 @@ pub fn vmls_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) )] pub fn vmls_lane_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } + vmls_u32(a, b, vdup_lane_u32::(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] @@ -31206,11 +30498,11 @@ pub fn vmls_lane_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_ )] pub fn vmls_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } + vmls_s32(a, b, vdup_laneq_s32::(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] @@ -31229,11 +30521,11 @@ pub fn vmls_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x4_t) )] pub fn vmls_laneq_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } + vmls_u32(a, b, vdup_laneq_u32::(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] @@ -31252,17 +30544,11 @@ pub fn vmls_laneq_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x4 )] pub fn vmlsq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - vmlsq_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlsq_s32(a, b, vdupq_lane_s32::(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] @@ -31281,17 +30567,11 @@ pub fn vmlsq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x2_t) )] pub fn vmlsq_lane_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - vmlsq_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlsq_u32(a, b, vdupq_lane_u32::(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] @@ -31310,17 +30590,11 @@ pub fn vmlsq_lane_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x2 )] pub fn vmlsq_laneq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlsq_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlsq_s32(a, b, vdupq_laneq_s32::(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] @@ -31339,17 +30613,11 @@ pub fn vmlsq_laneq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t )] pub fn vmlsq_laneq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlsq_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlsq_u32(a, b, vdupq_laneq_u32::(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))] @@ -31370,7 +30638,7 @@ pub fn vmls_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))] @@ -31391,7 +30659,7 @@ pub fn vmlsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] @@ -31412,7 +30680,7 @@ pub fn vmls_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t { } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] @@ -31433,7 +30701,7 @@ pub fn vmlsq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t { } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] @@ -31454,7 +30722,7 @@ pub fn vmls_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t { } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] @@ -31475,7 +30743,7 @@ pub fn vmlsq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t { } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] @@ -31496,7 +30764,7 @@ pub fn vmls_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t { } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] @@ -31517,7 +30785,7 @@ pub fn vmlsq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t { } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] @@ -31538,7 +30806,7 @@ pub fn vmls_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t { } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] @@ -31559,7 +30827,7 @@ pub fn vmlsq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t { } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))] @@ -31580,7 +30848,7 @@ pub fn vmls_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))] @@ -31601,7 +30869,7 @@ pub fn vmlsq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] @@ -31622,7 +30890,7 @@ pub fn vmls_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] @@ -31643,7 +30911,7 @@ pub fn vmlsq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] @@ -31664,7 +30932,7 @@ pub fn vmls_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] @@ -31685,7 +30953,7 @@ pub fn vmlsq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))] @@ -31706,7 +30974,7 @@ pub fn vmls_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))] @@ -31727,7 +30995,7 @@ pub fn vmlsq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] @@ -31748,7 +31016,7 @@ pub fn vmls_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] @@ -31769,7 +31037,7 @@ pub fn vmlsq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] @@ -31790,7 +31058,7 @@ pub fn vmls_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] @@ -31811,7 +31079,7 @@ pub fn vmlsq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))] @@ -31830,17 +31098,11 @@ pub fn vmlsq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { )] pub fn vmlsl_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlsl_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlsl_s16(a, b, vdup_lane_s16::(c)) } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))] @@ -31859,17 +31121,11 @@ pub fn vmlsl_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) )] pub fn vmlsl_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmlsl_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlsl_s16(a, b, vdup_laneq_s16::(c)) } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))] @@ -31888,11 +31144,11 @@ pub fn vmlsl_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t )] pub fn vmlsl_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } + vmlsl_s32(a, b, vdup_lane_s32::(c)) } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))] @@ -31911,11 +31167,11 @@ pub fn vmlsl_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) )] pub fn vmlsl_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } + vmlsl_s32(a, b, vdup_laneq_s32::(c)) } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))] @@ -31934,17 +31190,11 @@ pub fn vmlsl_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t )] pub fn vmlsl_lane_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlsl_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlsl_u16(a, b, vdup_lane_u16::(c)) } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))] @@ -31963,17 +31213,11 @@ pub fn vmlsl_lane_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4 )] pub fn vmlsl_laneq_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x8_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmlsl_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmlsl_u16(a, b, vdup_laneq_u16::(c)) } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))] @@ -31992,11 +31236,11 @@ pub fn vmlsl_laneq_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x )] pub fn vmlsl_lane_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } + vmlsl_u32(a, b, vdup_lane_u32::(c)) } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))] @@ -32015,11 +31259,11 @@ pub fn vmlsl_lane_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2 )] pub fn vmlsl_laneq_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x4_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } + vmlsl_u32(a, b, vdup_laneq_u32::(c)) } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))] @@ -32040,7 +31284,7 @@ pub fn vmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))] @@ -32061,7 +31305,7 @@ pub fn vmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))] @@ -32082,7 +31326,7 @@ pub fn vmlsl_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t { } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))] @@ -32103,7 +31347,7 @@ pub fn vmlsl_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t { } #[doc = "Signed multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s8"))] @@ -32124,7 +31368,7 @@ pub fn vmlsl_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { } #[doc = "Signed multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))] @@ -32145,7 +31389,7 @@ pub fn vmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { } #[doc = "Signed multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))] @@ -32166,7 +31410,7 @@ pub fn vmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { } #[doc = "Unsigned multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u8"))] @@ -32187,7 +31431,7 @@ pub fn vmlsl_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t { } #[doc = "Unsigned multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))] @@ -32208,7 +31452,7 @@ pub fn vmlsl_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { } #[doc = "Unsigned multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))] @@ -32229,7 +31473,7 @@ pub fn vmlsl_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { } #[doc = "8-bit integer matrix multiply-accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,i8mm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -32258,7 +31502,7 @@ pub fn vmmlaq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { } #[doc = "8-bit integer matrix multiply-accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,i8mm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -32287,7 +31531,7 @@ pub fn vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { } #[doc = "Duplicate element to vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] @@ -32303,7 +31547,7 @@ pub fn vmov_n_f16(a: f16) -> float16x4_t { } #[doc = "Duplicate element to vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] @@ -32319,7 +31563,7 @@ pub fn vmovq_n_f16(a: f16) -> float16x8_t { } #[doc = "Duplicate vector element to vector or scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] @@ -32340,7 +31584,7 @@ pub fn vmov_n_f32(value: f32) -> float32x2_t { } #[doc = "Duplicate vector element to vector or scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] @@ -32361,7 +31605,7 @@ pub fn vmov_n_p16(value: p16) -> poly16x4_t { } #[doc = "Duplicate vector element to vector or scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] @@ -32382,7 +31626,7 @@ pub fn vmov_n_p8(value: p8) -> poly8x8_t { } #[doc = "Duplicate vector element to vector or scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] @@ -32403,7 +31647,7 @@ pub fn vmov_n_s16(value: i16) -> int16x4_t { } #[doc = "Duplicate vector element to vector or scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] @@ -32424,7 +31668,7 @@ pub fn vmov_n_s32(value: i32) -> int32x2_t { } #[doc = "Duplicate vector element to vector or scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] @@ -32445,7 +31689,7 @@ pub fn vmov_n_s64(value: i64) -> int64x1_t { } #[doc = "Duplicate vector element to vector or scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] @@ -32466,7 +31710,7 @@ pub fn vmov_n_s8(value: i8) -> int8x8_t { } #[doc = "Duplicate vector element to vector or scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] @@ -32487,7 +31731,7 @@ pub fn vmov_n_u16(value: u16) -> uint16x4_t { } #[doc = "Duplicate vector element to vector or scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] @@ -32508,7 +31752,7 @@ pub fn vmov_n_u32(value: u32) -> uint32x2_t { } #[doc = "Duplicate vector element to vector or scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] @@ -32529,7 +31773,7 @@ pub fn vmov_n_u64(value: u64) -> uint64x1_t { } #[doc = "Duplicate vector element to vector or scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] @@ -32550,7 +31794,7 @@ pub fn vmov_n_u8(value: u8) -> uint8x8_t { } #[doc = "Duplicate vector element to vector or scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] @@ -32571,7 +31815,7 @@ pub fn vmovq_n_f32(value: f32) -> float32x4_t { } #[doc = "Duplicate vector element to vector or scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] @@ -32592,7 +31836,7 @@ pub fn vmovq_n_p16(value: p16) -> poly16x8_t { } #[doc = "Duplicate vector element to vector or scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] @@ -32613,7 +31857,7 @@ pub fn vmovq_n_p8(value: p8) -> poly8x16_t { } #[doc = "Duplicate vector element to vector or scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] @@ -32634,7 +31878,7 @@ pub fn vmovq_n_s16(value: i16) -> int16x8_t { } #[doc = "Duplicate vector element to vector or scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] @@ -32655,7 +31899,7 @@ pub fn vmovq_n_s32(value: i32) -> int32x4_t { } #[doc = "Duplicate vector element to vector or scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] @@ -32676,7 +31920,7 @@ pub fn vmovq_n_s64(value: i64) -> int64x2_t { } #[doc = "Duplicate vector element to vector or scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] @@ -32697,7 +31941,7 @@ pub fn vmovq_n_s8(value: i8) -> int8x16_t { } #[doc = "Duplicate vector element to vector or scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] @@ -32718,7 +31962,7 @@ pub fn vmovq_n_u16(value: u16) -> uint16x8_t { } #[doc = "Duplicate vector element to vector or scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] @@ -32739,7 +31983,7 @@ pub fn vmovq_n_u32(value: u32) -> uint32x4_t { } #[doc = "Duplicate vector element to vector or scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] @@ -32760,7 +32004,7 @@ pub fn vmovq_n_u64(value: u64) -> uint64x2_t { } #[doc = "Duplicate vector element to vector or scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] @@ -32781,7 +32025,7 @@ pub fn vmovq_n_u8(value: u8) -> uint8x16_t { } #[doc = "Vector long move."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))] @@ -32802,7 +32046,7 @@ pub fn vmovl_s16(a: int16x4_t) -> int32x4_t { } #[doc = "Vector long move."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))] @@ -32823,7 +32067,7 @@ pub fn vmovl_s32(a: int32x2_t) -> int64x2_t { } #[doc = "Vector long move."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))] @@ -32844,7 +32088,7 @@ pub fn vmovl_s8(a: int8x8_t) -> int16x8_t { } #[doc = "Vector long move."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))] @@ -32865,7 +32109,7 @@ pub fn vmovl_u16(a: uint16x4_t) -> uint32x4_t { } #[doc = "Vector long move."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))] @@ -32886,7 +32130,7 @@ pub fn vmovl_u32(a: uint32x2_t) -> uint64x2_t { } #[doc = "Vector long move."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))] @@ -32907,7 +32151,7 @@ pub fn vmovl_u8(a: uint8x8_t) -> uint16x8_t { } #[doc = "Vector narrow integer."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))] @@ -32928,7 +32172,7 @@ pub fn vmovn_s16(a: int16x8_t) -> int8x8_t { } #[doc = "Vector narrow integer."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))] @@ -32949,7 +32193,7 @@ pub fn vmovn_s32(a: int32x4_t) -> int16x4_t { } #[doc = "Vector narrow integer."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))] @@ -32970,7 +32214,7 @@ pub fn vmovn_s64(a: int64x2_t) -> int32x2_t { } #[doc = "Vector narrow integer."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))] @@ -32991,7 +32235,7 @@ pub fn vmovn_u16(a: uint16x8_t) -> uint8x8_t { } #[doc = "Vector narrow integer."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))] @@ -33012,7 +32256,7 @@ pub fn vmovn_u32(a: uint32x4_t) -> uint16x4_t { } #[doc = "Vector narrow integer."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))] @@ -33033,7 +32277,7 @@ pub fn vmovn_u64(a: uint64x2_t) -> uint32x2_t { } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))] #[cfg_attr( @@ -33043,7 +32287,7 @@ pub fn vmovn_u64(a: uint64x2_t) -> uint32x2_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -33055,7 +32299,7 @@ pub fn vmul_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))] #[cfg_attr( @@ -33065,7 +32309,7 @@ pub fn vmul_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -33077,7 +32321,7 @@ pub fn vmulq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))] @@ -33098,7 +32342,7 @@ pub fn vmul_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))] @@ -33119,7 +32363,7 @@ pub fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] #[cfg_attr( @@ -33130,7 +32374,7 @@ pub fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -33139,16 +32383,11 @@ pub fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { #[cfg(not(target_arch = "arm64ec"))] pub fn vmul_lane_f16(a: float16x4_t, v: float16x4_t) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - simd_mul( - a, - simd_shuffle!(v, v, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { simd_mul(a, vdup_lane_f16::(v)) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] #[cfg_attr( @@ -33159,7 +32398,7 @@ pub fn vmul_lane_f16(a: float16x4_t, v: float16x4_t) -> float16 #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -33168,29 +32407,11 @@ pub fn vmul_lane_f16(a: float16x4_t, v: float16x4_t) -> float16 #[cfg(not(target_arch = "arm64ec"))] pub fn vmulq_lane_f16(a: float16x8_t, v: float16x4_t) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - simd_mul( - a, - simd_shuffle!( - v, - v, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + unsafe { simd_mul(a, vdupq_lane_f16::(v)) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))] @@ -33209,11 +32430,11 @@ pub fn vmulq_lane_f16(a: float16x8_t, v: float16x4_t) -> float1 )] pub fn vmul_lane_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } + unsafe { simd_mul(a, vdup_lane_f32::(b)) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))] @@ -33232,11 +32453,11 @@ pub fn vmul_lane_f32(a: float32x2_t, b: float32x2_t) -> float32 )] pub fn vmul_laneq_f32(a: float32x2_t, b: float32x4_t) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } + unsafe { simd_mul(a, vdup_laneq_f32::(b)) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))] @@ -33255,16 +32476,11 @@ pub fn vmul_laneq_f32(a: float32x2_t, b: float32x4_t) -> float3 )] pub fn vmulq_lane_f32(a: float32x4_t, b: float32x2_t) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { simd_mul(a, vdupq_lane_f32::(b)) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))] @@ -33283,16 +32499,11 @@ pub fn vmulq_lane_f32(a: float32x4_t, b: float32x2_t) -> float3 )] pub fn vmulq_laneq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { simd_mul(a, vdupq_laneq_f32::(b)) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] @@ -33311,16 +32522,11 @@ pub fn vmulq_laneq_f32(a: float32x4_t, b: float32x4_t) -> float )] pub fn vmul_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { simd_mul(a, vdup_lane_s16::(b)) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] @@ -33339,29 +32545,11 @@ pub fn vmul_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { )] pub fn vmulq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - simd_mul( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + unsafe { simd_mul(a, vdupq_lane_s16::(b)) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] @@ -33380,11 +32568,11 @@ pub fn vmulq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x8_t )] pub fn vmul_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } + unsafe { simd_mul(a, vdup_lane_s32::(b)) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] @@ -33403,16 +32591,11 @@ pub fn vmul_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { )] pub fn vmulq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { simd_mul(a, vdupq_lane_s32::(b)) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] @@ -33431,16 +32614,11 @@ pub fn vmulq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x4_t )] pub fn vmul_lane_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { simd_mul(a, vdup_lane_u16::(b)) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] @@ -33459,29 +32637,11 @@ pub fn vmul_lane_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_ )] pub fn vmulq_lane_u16(a: uint16x8_t, b: uint16x4_t) -> uint16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - simd_mul( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + unsafe { simd_mul(a, vdupq_lane_u16::(b)) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] @@ -33500,11 +32660,11 @@ pub fn vmulq_lane_u16(a: uint16x8_t, b: uint16x4_t) -> uint16x8 )] pub fn vmul_lane_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } + unsafe { simd_mul(a, vdup_lane_u32::(b)) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] @@ -33523,16 +32683,11 @@ pub fn vmul_lane_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_ )] pub fn vmulq_lane_u32(a: uint32x4_t, b: uint32x2_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { simd_mul(a, vdupq_lane_u32::(b)) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] @@ -33551,16 +32706,11 @@ pub fn vmulq_lane_u32(a: uint32x4_t, b: uint32x2_t) -> uint32x4 )] pub fn vmul_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { simd_mul(a, vdup_laneq_s16::(b)) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] @@ -33579,29 +32729,11 @@ pub fn vmul_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4_t )] pub fn vmulq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - simd_mul( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + unsafe { simd_mul(a, vdupq_laneq_s16::(b)) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] @@ -33620,11 +32752,11 @@ pub fn vmulq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t )] pub fn vmul_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } + unsafe { simd_mul(a, vdup_laneq_s32::(b)) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] @@ -33643,16 +32775,11 @@ pub fn vmul_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2_t )] pub fn vmulq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { simd_mul(a, vdupq_laneq_s32::(b)) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] @@ -33671,16 +32798,11 @@ pub fn vmulq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t )] pub fn vmul_laneq_u16(a: uint16x4_t, b: uint16x8_t) -> uint16x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { simd_mul(a, vdup_laneq_u16::(b)) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] @@ -33699,29 +32821,11 @@ pub fn vmul_laneq_u16(a: uint16x4_t, b: uint16x8_t) -> uint16x4 )] pub fn vmulq_laneq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - simd_mul( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + unsafe { simd_mul(a, vdupq_laneq_u16::(b)) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] @@ -33740,11 +32844,11 @@ pub fn vmulq_laneq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x )] pub fn vmul_laneq_u32(a: uint32x2_t, b: uint32x4_t) -> uint32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } + unsafe { simd_mul(a, vdup_laneq_u32::(b)) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] @@ -33763,16 +32867,11 @@ pub fn vmul_laneq_u32(a: uint32x2_t, b: uint32x4_t) -> uint32x2 )] pub fn vmulq_laneq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { simd_mul(a, vdupq_laneq_u32::(b)) } } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] #[cfg_attr( @@ -33787,7 +32886,7 @@ pub fn vmul_n_f16(a: float16x4_t, b: f16) -> float16x4_t { } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] #[cfg_attr( @@ -33802,7 +32901,7 @@ pub fn vmulq_n_f16(a: float16x8_t, b: f16) -> float16x8_t { } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] @@ -33823,7 +32922,7 @@ pub fn vmul_n_f32(a: float32x2_t, b: f32) -> float32x2_t { } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] @@ -33844,7 +32943,7 @@ pub fn vmulq_n_f32(a: float32x4_t, b: f32) -> float32x4_t { } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] @@ -33865,7 +32964,7 @@ pub fn vmul_n_s16(a: int16x4_t, b: i16) -> int16x4_t { } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] @@ -33886,7 +32985,7 @@ pub fn vmulq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] @@ -33907,7 +33006,7 @@ pub fn vmul_n_s32(a: int32x2_t, b: i32) -> int32x2_t { } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] @@ -33928,7 +33027,7 @@ pub fn vmulq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] @@ -33949,7 +33048,7 @@ pub fn vmul_n_u16(a: uint16x4_t, b: u16) -> uint16x4_t { } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] @@ -33970,7 +33069,7 @@ pub fn vmulq_n_u16(a: uint16x8_t, b: u16) -> uint16x8_t { } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] @@ -33991,7 +33090,7 @@ pub fn vmul_n_u32(a: uint32x2_t, b: u32) -> uint32x2_t { } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] @@ -34012,7 +33111,7 @@ pub fn vmulq_n_u32(a: uint32x4_t, b: u32) -> uint32x4_t { } #[doc = "Polynomial multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] @@ -34041,7 +33140,7 @@ pub fn vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { } #[doc = "Polynomial multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] @@ -34070,7 +33169,7 @@ pub fn vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))] @@ -34091,7 +33190,7 @@ pub fn vmul_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))] @@ -34112,7 +33211,7 @@ pub fn vmulq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))] @@ -34133,7 +33232,7 @@ pub fn vmul_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))] @@ -34154,7 +33253,7 @@ pub fn vmulq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))] @@ -34175,7 +33274,7 @@ pub fn vmul_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))] @@ -34196,7 +33295,7 @@ pub fn vmulq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))] @@ -34217,7 +33316,7 @@ pub fn vmul_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))] @@ -34238,7 +33337,7 @@ pub fn vmulq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))] @@ -34259,7 +33358,7 @@ pub fn vmul_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))] @@ -34280,7 +33379,7 @@ pub fn vmulq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))] @@ -34301,7 +33400,7 @@ pub fn vmul_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))] @@ -34322,7 +33421,7 @@ pub fn vmulq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] @@ -34341,16 +33440,11 @@ pub fn vmulq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { )] pub fn vmull_lane_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmull_s16( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmull_s16(a, vdup_lane_s16::(b)) } #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] @@ -34369,16 +33463,11 @@ pub fn vmull_lane_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t )] pub fn vmull_laneq_s16(a: int16x4_t, b: int16x8_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmull_s16( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmull_s16(a, vdup_laneq_s16::(b)) } #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] @@ -34397,11 +33486,11 @@ pub fn vmull_laneq_s16(a: int16x4_t, b: int16x8_t) -> int32x4_t )] pub fn vmull_lane_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } + vmull_s32(a, vdup_lane_s32::(b)) } #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] @@ -34420,11 +33509,11 @@ pub fn vmull_lane_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t )] pub fn vmull_laneq_s32(a: int32x2_t, b: int32x4_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } + vmull_s32(a, vdup_laneq_s32::(b)) } #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] @@ -34443,16 +33532,11 @@ pub fn vmull_laneq_s32(a: int32x2_t, b: int32x4_t) -> int64x2_t )] pub fn vmull_lane_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmull_u16( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmull_u16(a, vdup_lane_u16::(b)) } #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] @@ -34471,16 +33555,11 @@ pub fn vmull_lane_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4 )] pub fn vmull_laneq_u16(a: uint16x4_t, b: uint16x8_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmull_u16( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + vmull_u16(a, vdup_laneq_u16::(b)) } #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] @@ -34499,11 +33578,11 @@ pub fn vmull_laneq_u16(a: uint16x4_t, b: uint16x8_t) -> uint32x )] pub fn vmull_lane_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } + vmull_u32(a, vdup_lane_u32::(b)) } #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] @@ -34522,11 +33601,11 @@ pub fn vmull_lane_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2 )] pub fn vmull_laneq_u32(a: uint32x2_t, b: uint32x4_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } + vmull_u32(a, vdup_laneq_u32::(b)) } #[doc = "Vector long multiply with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))] @@ -34547,7 +33626,7 @@ pub fn vmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t { } #[doc = "Vector long multiply with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))] @@ -34568,7 +33647,7 @@ pub fn vmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t { } #[doc = "Vector long multiply with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))] @@ -34589,7 +33668,7 @@ pub fn vmull_n_u16(a: uint16x4_t, b: u16) -> uint32x4_t { } #[doc = "Vector long multiply with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))] @@ -34610,7 +33689,7 @@ pub fn vmull_n_u32(a: uint32x2_t, b: u32) -> uint64x2_t { } #[doc = "Polynomial multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.p8"))] @@ -34639,7 +33718,7 @@ pub fn vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t { } #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s16"))] @@ -34656,19 +33735,11 @@ pub fn vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.smull.v4i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v4i32")] - fn _vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t; - } - unsafe { _vmull_s16(a, b) } + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s32"))] @@ -34685,19 +33756,11 @@ pub fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.smull.v2i64" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v2i64")] - fn _vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t; - } - unsafe { _vmull_s32(a, b) } + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s8"))] @@ -34714,19 +33777,11 @@ pub fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.smull.v8i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v8i16")] - fn _vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t; - } - unsafe { _vmull_s8(a, b) } + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u8"))] @@ -34743,19 +33798,11 @@ pub fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.umull.v8i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v8i16")] - fn _vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t; - } - unsafe { _vmull_u8(a, b) } + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u16"))] @@ -34772,19 +33819,11 @@ pub fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.umull.v4i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v4i32")] - fn _vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t; - } - unsafe { _vmull_u16(a, b) } + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u32"))] @@ -34801,19 +33840,11 @@ pub fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.umull.v2i64" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v2i64")] - fn _vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t; - } - unsafe { _vmull_u32(a, b) } + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } #[doc = "Vector bitwise not."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] @@ -34835,7 +33866,7 @@ pub fn vmvn_p8(a: poly8x8_t) -> poly8x8_t { } #[doc = "Vector bitwise not."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] @@ -34857,7 +33888,7 @@ pub fn vmvn_s16(a: int16x4_t) -> int16x4_t { } #[doc = "Vector bitwise not."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] @@ -34879,7 +33910,7 @@ pub fn vmvn_s32(a: int32x2_t) -> int32x2_t { } #[doc = "Vector bitwise not."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] @@ -34901,7 +33932,7 @@ pub fn vmvn_s8(a: int8x8_t) -> int8x8_t { } #[doc = "Vector bitwise not."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] @@ -34923,7 +33954,7 @@ pub fn vmvn_u16(a: uint16x4_t) -> uint16x4_t { } #[doc = "Vector bitwise not."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] @@ -34945,7 +33976,7 @@ pub fn vmvn_u32(a: uint32x2_t) -> uint32x2_t { } #[doc = "Vector bitwise not."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] @@ -34967,7 +33998,7 @@ pub fn vmvn_u8(a: uint8x8_t) -> uint8x8_t { } #[doc = "Vector bitwise not."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] @@ -34989,7 +34020,7 @@ pub fn vmvnq_p8(a: poly8x16_t) -> poly8x16_t { } #[doc = "Vector bitwise not."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] @@ -35011,7 +34042,7 @@ pub fn vmvnq_s16(a: int16x8_t) -> int16x8_t { } #[doc = "Vector bitwise not."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] @@ -35033,7 +34064,7 @@ pub fn vmvnq_s32(a: int32x4_t) -> int32x4_t { } #[doc = "Vector bitwise not."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] @@ -35055,7 +34086,7 @@ pub fn vmvnq_s8(a: int8x16_t) -> int8x16_t { } #[doc = "Vector bitwise not."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] @@ -35077,7 +34108,7 @@ pub fn vmvnq_u16(a: uint16x8_t) -> uint16x8_t { } #[doc = "Vector bitwise not."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] @@ -35099,7 +34130,7 @@ pub fn vmvnq_u32(a: uint32x4_t) -> uint32x4_t { } #[doc = "Vector bitwise not."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] @@ -35121,7 +34152,7 @@ pub fn vmvnq_u8(a: uint8x16_t) -> uint8x16_t { } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))] #[cfg_attr( @@ -35131,7 +34162,7 @@ pub fn vmvnq_u8(a: uint8x16_t) -> uint8x16_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -35143,7 +34174,7 @@ pub fn vneg_f16(a: float16x4_t) -> float16x4_t { } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))] #[cfg_attr( @@ -35153,7 +34184,7 @@ pub fn vneg_f16(a: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -35165,7 +34196,7 @@ pub fn vnegq_f16(a: float16x8_t) -> float16x8_t { } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))] @@ -35186,7 +34217,7 @@ pub fn vneg_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))] @@ -35207,7 +34238,7 @@ pub fn vnegq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))] @@ -35228,7 +34259,7 @@ pub fn vneg_s8(a: int8x8_t) -> int8x8_t { } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))] @@ -35249,7 +34280,7 @@ pub fn vnegq_s8(a: int8x16_t) -> int8x16_t { } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))] @@ -35270,7 +34301,7 @@ pub fn vneg_s16(a: int16x4_t) -> int16x4_t { } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))] @@ -35291,7 +34322,7 @@ pub fn vnegq_s16(a: int16x8_t) -> int16x8_t { } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))] @@ -35312,7 +34343,7 @@ pub fn vneg_s32(a: int32x2_t) -> int32x2_t { } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))] @@ -35333,7 +34364,7 @@ pub fn vnegq_s32(a: int32x4_t) -> int32x4_t { } #[doc = "Vector bitwise inclusive OR NOT"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] @@ -35355,7 +34386,7 @@ pub fn vorn_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Vector bitwise inclusive OR NOT"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] @@ -35377,7 +34408,7 @@ pub fn vorn_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Vector bitwise inclusive OR NOT"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] @@ -35399,7 +34430,7 @@ pub fn vorn_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } #[doc = "Vector bitwise inclusive OR NOT"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] @@ -35421,7 +34452,7 @@ pub fn vorn_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Vector bitwise inclusive OR NOT"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] @@ -35443,7 +34474,7 @@ pub fn vornq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Vector bitwise inclusive OR NOT"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] @@ -35465,7 +34496,7 @@ pub fn vornq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Vector bitwise inclusive OR NOT"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] @@ -35487,7 +34518,7 @@ pub fn vornq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } #[doc = "Vector bitwise inclusive OR NOT"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] @@ -35509,7 +34540,7 @@ pub fn vornq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Vector bitwise inclusive OR NOT"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] @@ -35531,7 +34562,7 @@ pub fn vorn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Vector bitwise inclusive OR NOT"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] @@ -35553,7 +34584,7 @@ pub fn vorn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Vector bitwise inclusive OR NOT"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] @@ -35575,7 +34606,7 @@ pub fn vorn_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Vector bitwise inclusive OR NOT"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] @@ -35597,7 +34628,7 @@ pub fn vorn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Vector bitwise inclusive OR NOT"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] @@ -35619,7 +34650,7 @@ pub fn vornq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Vector bitwise inclusive OR NOT"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] @@ -35641,7 +34672,7 @@ pub fn vornq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Vector bitwise inclusive OR NOT"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] @@ -35663,7 +34694,7 @@ pub fn vornq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Vector bitwise inclusive OR NOT"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] @@ -35685,7 +34716,7 @@ pub fn vornq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -35706,7 +34737,7 @@ pub fn vorr_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -35727,7 +34758,7 @@ pub fn vorrq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -35748,7 +34779,7 @@ pub fn vorr_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -35769,7 +34800,7 @@ pub fn vorrq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -35790,7 +34821,7 @@ pub fn vorr_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -35811,7 +34842,7 @@ pub fn vorrq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -35832,7 +34863,7 @@ pub fn vorr_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -35853,7 +34884,7 @@ pub fn vorrq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -35874,7 +34905,7 @@ pub fn vorr_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -35895,7 +34926,7 @@ pub fn vorrq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -35916,7 +34947,7 @@ pub fn vorr_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -35937,7 +34968,7 @@ pub fn vorrq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -35958,7 +34989,7 @@ pub fn vorr_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -35979,7 +35010,7 @@ pub fn vorrq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -36000,7 +35031,7 @@ pub fn vorr_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -36021,7 +35052,7 @@ pub fn vorrq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))] @@ -36051,7 +35082,7 @@ pub fn vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))] @@ -36081,7 +35112,7 @@ pub fn vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))] @@ -36111,7 +35142,7 @@ pub fn vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))] @@ -36141,7 +35172,7 @@ pub fn vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))] @@ -36171,7 +35202,7 @@ pub fn vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))] @@ -36201,7 +35232,7 @@ pub fn vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))] @@ -36231,7 +35262,7 @@ pub fn vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t { } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))] @@ -36261,7 +35292,7 @@ pub fn vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))] @@ -36291,7 +35322,7 @@ pub fn vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t { } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))] @@ -36321,7 +35352,7 @@ pub fn vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))] @@ -36351,7 +35382,7 @@ pub fn vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t { } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))] @@ -36381,7 +35412,8 @@ pub fn vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] #[cfg_attr( @@ -36391,7 +35423,7 @@ pub fn vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -36410,8 +35442,45 @@ pub fn vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { _vpadd_f16(a, b) } } #[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(faddp) +)] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "stdarch_neon_fp16", since = "1.94.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v4f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.faddp.v4f16" + )] + fn _vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = _vpadd_f16(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] @@ -36438,9 +35507,45 @@ pub fn vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } unsafe { _vpadd_f32(a, b) } } +#[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(faddp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.faddp.v2f32" + )] + fn _vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = _vpadd_f32(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} #[doc = "Add pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] @@ -36468,8 +35573,9 @@ pub fn vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe { _vpadd_s8(a, b) } } #[doc = "Add pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] @@ -36485,20 +35591,26 @@ pub fn vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.addp.v4i16" + link_name = "llvm.aarch64.neon.addp.v8i8" )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v4i16")] - fn _vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v8i8")] + fn _vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = _vpadd_s8(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } - unsafe { _vpadd_s16(a, b) } } #[doc = "Add pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] @@ -36514,21 +35626,21 @@ pub fn vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.addp.v2i32" + link_name = "llvm.aarch64.neon.addp.v4i16" )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2i32")] - fn _vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v4i16")] + fn _vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } - unsafe { _vpadd_s32(a, b) } + unsafe { _vpadd_s16(a, b) } } #[doc = "Add pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] @@ -36544,13 +35656,26 @@ pub fn vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - unsafe { transmute(vpadd_s8(transmute(a), transmute(b))) } +pub fn vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.addp.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v4i16")] + fn _vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x4_t = _vpadd_s16(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Add pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] @@ -36566,18 +35691,21 @@ pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vpadd_s8(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.addp.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2i32")] + fn _vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } + unsafe { _vpadd_s32(a, b) } } #[doc = "Add pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] @@ -36593,13 +35721,25 @@ pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - unsafe { transmute(vpadd_s16(transmute(a), transmute(b))) } +pub fn vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.addp.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2i32")] + fn _vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x2_t = _vpadd_s32(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Add pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] @@ -36615,18 +35755,12 @@ pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - let b: uint16x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x4_t = transmute(vpadd_s16(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { transmute(vpadd_s8(transmute(a), transmute(b))) } } #[doc = "Add pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] @@ -36642,13 +35776,12 @@ pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - unsafe { transmute(vpadd_s32(transmute(a), transmute(b))) } +pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { transmute(vpadd_s16(transmute(a), transmute(b))) } } #[doc = "Add pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] @@ -36665,16 +35798,11 @@ pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - let b: uint32x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) }; - unsafe { - let ret_val: uint32x2_t = transmute(vpadd_s32(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } + unsafe { transmute(vpadd_s32(transmute(a), transmute(b))) } } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s8"))] @@ -36703,7 +35831,7 @@ pub fn vpaddl_s8(a: int8x8_t) -> int16x4_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s8"))] @@ -36732,7 +35860,7 @@ pub fn vpaddlq_s8(a: int8x16_t) -> int16x8_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s16"))] @@ -36761,7 +35889,7 @@ pub fn vpaddl_s16(a: int16x4_t) -> int32x2_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s16"))] @@ -36790,7 +35918,7 @@ pub fn vpaddlq_s16(a: int16x8_t) -> int32x4_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s32"))] @@ -36819,7 +35947,7 @@ pub fn vpaddl_s32(a: int32x2_t) -> int64x1_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s32"))] @@ -36848,7 +35976,7 @@ pub fn vpaddlq_s32(a: int32x4_t) -> int64x2_t { } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u8"))] @@ -36877,7 +36005,7 @@ pub fn vpaddl_u8(a: uint8x8_t) -> uint16x4_t { } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u8"))] @@ -36906,7 +36034,7 @@ pub fn vpaddlq_u8(a: uint8x16_t) -> uint16x8_t { } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u16"))] @@ -36935,7 +36063,7 @@ pub fn vpaddl_u16(a: uint16x4_t) -> uint32x2_t { } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u16"))] @@ -36964,7 +36092,7 @@ pub fn vpaddlq_u16(a: uint16x8_t) -> uint32x4_t { } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u32"))] @@ -36993,7 +36121,7 @@ pub fn vpaddl_u32(a: uint32x2_t) -> uint64x1_t { } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u32"))] @@ -37022,7 +36150,8 @@ pub fn vpaddlq_u32(a: uint32x4_t) -> uint64x2_t { } #[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] @@ -37050,8 +36179,44 @@ pub fn vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe { _vpmax_f32(a, b) } } #[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmaxp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxp.v2f32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2f32")] + fn _vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = _vpmax_f32(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] @@ -37079,8 +36244,44 @@ pub fn vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe { _vpmax_s8(a, b) } } #[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smaxp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smaxp.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v8i8")] + fn _vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = _vpmax_s8(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] @@ -37108,8 +36309,44 @@ pub fn vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe { _vpmax_s16(a, b) } } #[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smaxp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smaxp.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v4i16")] + fn _vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x4_t = _vpmax_s16(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] @@ -37137,8 +36374,44 @@ pub fn vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe { _vpmax_s32(a, b) } } #[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smaxp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smaxp.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2i32")] + fn _vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x2_t = _vpmax_s32(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] @@ -37166,8 +36439,44 @@ pub fn vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe { _vpmax_u8(a, b) } } #[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umaxp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umaxp.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v8i8")] + fn _vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; + } + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = _vpmax_u8(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] @@ -37195,8 +36504,44 @@ pub fn vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe { _vpmax_u16(a, b) } } #[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umaxp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umaxp.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v4i16")] + fn _vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; + } + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint16x4_t = _vpmax_u16(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] @@ -37223,9 +36568,45 @@ pub fn vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } unsafe { _vpmax_u32(a, b) } } +#[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umaxp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umaxp.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v2i32")] + fn _vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; + } + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint32x2_t = _vpmax_u32(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} #[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] @@ -37253,8 +36634,44 @@ pub fn vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe { _vpmin_f32(a, b) } } #[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fminp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminp.v2f32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2f32")] + fn _vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = _vpmin_f32(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] @@ -37282,8 +36699,44 @@ pub fn vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe { _vpmin_s8(a, b) } } #[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sminp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sminp.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v8i8")] + fn _vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = _vpmin_s8(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] @@ -37311,8 +36764,44 @@ pub fn vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe { _vpmin_s16(a, b) } } #[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sminp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sminp.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v4i16")] + fn _vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x4_t = _vpmin_s16(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] @@ -37340,8 +36829,44 @@ pub fn vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe { _vpmin_s32(a, b) } } #[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sminp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sminp.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2i32")] + fn _vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x2_t = _vpmin_s32(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] @@ -37369,8 +36894,44 @@ pub fn vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe { _vpmin_u8(a, b) } } #[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uminp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uminp.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v8i8")] + fn _vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; + } + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = _vpmin_u8(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] @@ -37398,8 +36959,44 @@ pub fn vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe { _vpmin_u16(a, b) } } #[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uminp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uminp.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v4i16")] + fn _vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; + } + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint16x4_t = _vpmin_u16(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] @@ -37426,9 +37023,44 @@ pub fn vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } unsafe { _vpmin_u32(a, b) } } +#[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uminp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uminp.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v2i32")] + fn _vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; + } + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint32x2_t = _vpmin_u32(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))] @@ -37457,7 +37089,7 @@ pub fn vqabs_s8(a: int8x8_t) -> int8x8_t { } #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))] @@ -37486,7 +37118,7 @@ pub fn vqabsq_s8(a: int8x16_t) -> int8x16_t { } #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))] @@ -37515,7 +37147,7 @@ pub fn vqabs_s16(a: int16x4_t) -> int16x4_t { } #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))] @@ -37544,7 +37176,7 @@ pub fn vqabsq_s16(a: int16x8_t) -> int16x8_t { } #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))] @@ -37573,7 +37205,7 @@ pub fn vqabs_s32(a: int32x2_t) -> int32x2_t { } #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))] @@ -37602,7 +37234,7 @@ pub fn vqabsq_s32(a: int32x4_t) -> int32x4_t { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))] @@ -37623,7 +37255,7 @@ pub fn vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))] @@ -37644,7 +37276,7 @@ pub fn vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))] @@ -37665,7 +37297,7 @@ pub fn vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))] @@ -37686,7 +37318,7 @@ pub fn vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))] @@ -37707,7 +37339,7 @@ pub fn vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))] @@ -37728,7 +37360,7 @@ pub fn vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))] @@ -37749,7 +37381,7 @@ pub fn vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))] @@ -37770,7 +37402,7 @@ pub fn vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))] @@ -37791,7 +37423,7 @@ pub fn vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))] @@ -37812,7 +37444,7 @@ pub fn vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))] @@ -37833,7 +37465,7 @@ pub fn vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))] @@ -37854,7 +37486,7 @@ pub fn vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))] @@ -37875,7 +37507,7 @@ pub fn vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))] @@ -37896,7 +37528,7 @@ pub fn vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))] @@ -37917,7 +37549,7 @@ pub fn vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))] @@ -37938,12 +37570,16 @@ pub fn vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Vector widening saturating doubling multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 2))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(sqdmlal, N = 2) )] #[rustc_legacy_const_generics(3)] @@ -37961,12 +37597,16 @@ pub fn vqdmlal_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) } #[doc = "Vector widening saturating doubling multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 1))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(sqdmlal, N = 1) )] #[rustc_legacy_const_generics(3)] @@ -37984,7 +37624,7 @@ pub fn vqdmlal_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) } #[doc = "Vector widening saturating doubling multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))] @@ -38005,7 +37645,7 @@ pub fn vqdmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { } #[doc = "Vector widening saturating doubling multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))] @@ -38026,7 +37666,7 @@ pub fn vqdmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))] @@ -38047,7 +37687,7 @@ pub fn vqdmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))] @@ -38068,12 +37708,16 @@ pub fn vqdmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { } #[doc = "Vector widening saturating doubling multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 2))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(sqdmlsl, N = 2) )] #[rustc_legacy_const_generics(3)] @@ -38091,12 +37735,16 @@ pub fn vqdmlsl_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) } #[doc = "Vector widening saturating doubling multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 1))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(sqdmlsl, N = 1) )] #[rustc_legacy_const_generics(3)] @@ -38114,7 +37762,7 @@ pub fn vqdmlsl_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) } #[doc = "Vector widening saturating doubling multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))] @@ -38135,7 +37783,7 @@ pub fn vqdmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { } #[doc = "Vector widening saturating doubling multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))] @@ -38156,7 +37804,7 @@ pub fn vqdmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))] @@ -38177,7 +37825,7 @@ pub fn vqdmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))] @@ -38198,7 +37846,7 @@ pub fn vqdmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { } #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))] @@ -38217,11 +37865,11 @@ pub fn vqdmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { )] pub fn vqdmulh_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vqdmulh_s16(a, vdup_n_s16(simd_extract!(b, LANE as u32))) } + vqdmulh_s16(a, vdup_n_s16(vgetq_lane_s16::(b))) } #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))] @@ -38240,11 +37888,11 @@ pub fn vqdmulh_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4 )] pub fn vqdmulhq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vqdmulhq_s16(a, vdupq_n_s16(simd_extract!(b, LANE as u32))) } + vqdmulhq_s16(a, vdupq_n_s16(vgetq_lane_s16::(b))) } #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))] @@ -38263,11 +37911,11 @@ pub fn vqdmulhq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x )] pub fn vqdmulh_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vqdmulh_s32(a, vdup_n_s32(simd_extract!(b, LANE as u32))) } + vqdmulh_s32(a, vdup_n_s32(vgetq_lane_s32::(b))) } #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))] @@ -38286,11 +37934,11 @@ pub fn vqdmulh_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2 )] pub fn vqdmulhq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vqdmulhq_s32(a, vdupq_n_s32(simd_extract!(b, LANE as u32))) } + vqdmulhq_s32(a, vdupq_n_s32(vgetq_lane_s32::(b))) } #[doc = "Vector saturating doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] @@ -38312,7 +37960,7 @@ pub fn vqdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t { } #[doc = "Vector saturating doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] @@ -38334,7 +37982,7 @@ pub fn vqdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { } #[doc = "Vector saturating doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] @@ -38356,7 +38004,7 @@ pub fn vqdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t { } #[doc = "Vector saturating doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] @@ -38378,7 +38026,7 @@ pub fn vqdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] @@ -38407,7 +38055,7 @@ pub fn vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] @@ -38436,7 +38084,7 @@ pub fn vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] @@ -38465,7 +38113,7 @@ pub fn vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] @@ -38494,7 +38142,7 @@ pub fn vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Vector saturating doubling long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 2))] @@ -38513,14 +38161,12 @@ pub fn vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { )] pub fn vqdmull_lane_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(N, 2); - unsafe { - let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); - vqdmull_s16(a, b) - } + let b = vdup_lane_s16::(b); + vqdmull_s16(a, b) } #[doc = "Vector saturating doubling long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 1))] @@ -38539,14 +38185,12 @@ pub fn vqdmull_lane_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { )] pub fn vqdmull_lane_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(N, 1); - unsafe { - let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); - vqdmull_s32(a, b) - } + let b = vdup_lane_s32::(b); + vqdmull_s32(a, b) } #[doc = "Vector saturating doubling long multiply with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))] @@ -38567,7 +38211,7 @@ pub fn vqdmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t { } #[doc = "Vector saturating doubling long multiply with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))] @@ -38588,7 +38232,7 @@ pub fn vqdmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t { } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))] @@ -38617,7 +38261,7 @@ pub fn vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))] @@ -38646,7 +38290,7 @@ pub fn vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] @@ -38675,7 +38319,7 @@ pub fn vqmovn_s16(a: int16x8_t) -> int8x8_t { } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] @@ -38704,7 +38348,7 @@ pub fn vqmovn_s32(a: int32x4_t) -> int16x4_t { } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] @@ -38733,7 +38377,7 @@ pub fn vqmovn_s64(a: int64x2_t) -> int32x2_t { } #[doc = "Unsigned saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] @@ -38762,7 +38406,7 @@ pub fn vqmovn_u16(a: uint16x8_t) -> uint8x8_t { } #[doc = "Unsigned saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] @@ -38791,7 +38435,7 @@ pub fn vqmovn_u32(a: uint32x4_t) -> uint16x4_t { } #[doc = "Unsigned saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] @@ -38820,7 +38464,7 @@ pub fn vqmovn_u64(a: uint64x2_t) -> uint32x2_t { } #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))] @@ -38849,7 +38493,7 @@ pub fn vqmovun_s16(a: int16x8_t) -> uint8x8_t { } #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))] @@ -38878,7 +38522,7 @@ pub fn vqmovun_s32(a: int32x4_t) -> uint16x4_t { } #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))] @@ -38907,7 +38551,7 @@ pub fn vqmovun_s64(a: int64x2_t) -> uint32x2_t { } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))] @@ -38936,7 +38580,7 @@ pub fn vqneg_s8(a: int8x8_t) -> int8x8_t { } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))] @@ -38965,7 +38609,7 @@ pub fn vqnegq_s8(a: int8x16_t) -> int8x16_t { } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))] @@ -38994,7 +38638,7 @@ pub fn vqneg_s16(a: int16x4_t) -> int16x4_t { } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))] @@ -39023,7 +38667,7 @@ pub fn vqnegq_s16(a: int16x8_t) -> int16x8_t { } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))] @@ -39052,7 +38696,7 @@ pub fn vqneg_s32(a: int32x2_t) -> int32x2_t { } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))] @@ -39081,7 +38725,7 @@ pub fn vqnegq_s32(a: int32x4_t) -> int32x4_t { } #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] @@ -39100,15 +38744,12 @@ pub fn vqnegq_s32(a: int32x4_t) -> int32x4_t { )] pub fn vqrdmulh_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let b: int16x4_t = - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmulh_s16(a, b) - } + let b = vdup_lane_s16::(b); + vqrdmulh_s16(a, b) } #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] @@ -39127,14 +38768,12 @@ pub fn vqrdmulh_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4 )] pub fn vqrdmulh_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]); - vqrdmulh_s32(a, b) - } + let b = vdup_lane_s32::(b); + vqrdmulh_s32(a, b) } #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] @@ -39153,15 +38792,12 @@ pub fn vqrdmulh_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2 )] pub fn vqrdmulh_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - let b: int16x4_t = - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmulh_s16(a, b) - } + let b = vdup_laneq_s16::(b); + vqrdmulh_s16(a, b) } #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] @@ -39180,14 +38816,12 @@ pub fn vqrdmulh_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x )] pub fn vqrdmulh_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]); - vqrdmulh_s32(a, b) - } + let b = vdup_laneq_s32::(b); + vqrdmulh_s32(a, b) } #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] @@ -39206,27 +38840,12 @@ pub fn vqrdmulh_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x )] pub fn vqrdmulhq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let b: int16x8_t = simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ); - vqrdmulhq_s16(a, b) - } + let b = vdupq_lane_s16::(b); + vqrdmulhq_s16(a, b) } #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] @@ -39245,15 +38864,12 @@ pub fn vqrdmulhq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x )] pub fn vqrdmulhq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let b: int32x4_t = - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmulhq_s32(a, b) - } + let b = vdupq_lane_s32::(b); + vqrdmulhq_s32(a, b) } #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] @@ -39272,27 +38888,12 @@ pub fn vqrdmulhq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x )] pub fn vqrdmulhq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - let b: int16x8_t = simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ); - vqrdmulhq_s16(a, b) - } + let b = vdupq_laneq_s16::(b); + vqrdmulhq_s16(a, b) } #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] @@ -39311,15 +38912,12 @@ pub fn vqrdmulhq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16 )] pub fn vqrdmulhq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let b: int32x4_t = - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmulhq_s32(a, b) - } + let b = vdupq_laneq_s32::(b); + vqrdmulhq_s32(a, b) } #[doc = "Vector saturating rounding doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] @@ -39340,7 +38938,7 @@ pub fn vqrdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t { } #[doc = "Vector saturating rounding doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] @@ -39361,7 +38959,7 @@ pub fn vqrdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { } #[doc = "Vector saturating rounding doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] @@ -39382,7 +38980,7 @@ pub fn vqrdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t { } #[doc = "Vector saturating rounding doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] @@ -39403,7 +39001,7 @@ pub fn vqrdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] @@ -39432,7 +39030,7 @@ pub fn vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] @@ -39461,7 +39059,7 @@ pub fn vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] @@ -39490,7 +39088,7 @@ pub fn vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] @@ -39519,7 +39117,7 @@ pub fn vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] @@ -39548,7 +39146,7 @@ pub fn vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] @@ -39577,7 +39175,7 @@ pub fn vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] @@ -39606,7 +39204,7 @@ pub fn vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] @@ -39635,7 +39233,7 @@ pub fn vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] @@ -39664,7 +39262,7 @@ pub fn vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] @@ -39693,7 +39291,7 @@ pub fn vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] @@ -39722,7 +39320,7 @@ pub fn vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] @@ -39751,7 +39349,7 @@ pub fn vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] @@ -39780,7 +39378,7 @@ pub fn vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] @@ -39809,7 +39407,7 @@ pub fn vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] @@ -39838,7 +39436,7 @@ pub fn vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] @@ -39867,7 +39465,7 @@ pub fn vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] @@ -39896,7 +39494,7 @@ pub fn vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] @@ -39925,7 +39523,7 @@ pub fn vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] @@ -39954,7 +39552,7 @@ pub fn vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] @@ -39983,7 +39581,7 @@ pub fn vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqrshrn, N = 2))] @@ -39999,7 +39597,7 @@ pub fn vqrshrn_n_s16(a: int16x8_t) -> int8x8_t { } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqrshrn, N = 2))] @@ -40015,7 +39613,7 @@ pub fn vqrshrn_n_s32(a: int32x4_t) -> int16x4_t { } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqrshrn, N = 2))] @@ -40031,7 +39629,7 @@ pub fn vqrshrn_n_s64(a: int64x2_t) -> int32x2_t { } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqrshrn, N = 2))] @@ -40050,7 +39648,7 @@ pub fn vqrshrn_n_s16(a: int16x8_t) -> int8x8_t { } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqrshrn, N = 2))] @@ -40069,7 +39667,7 @@ pub fn vqrshrn_n_s32(a: int32x4_t) -> int16x4_t { } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqrshrn, N = 2))] @@ -40088,7 +39686,7 @@ pub fn vqrshrn_n_s64(a: int64x2_t) -> int32x2_t { } #[doc = "Unsigned signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqrshrn, N = 2))] @@ -40100,21 +39698,11 @@ pub fn vqrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v8i8")] fn _vqrshrn_n_u16(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t; } - unsafe { - _vqrshrn_n_u16( - a, - const { - uint16x8_t([ - -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, - -N as u16, - ]) - }, - ) - } + unsafe { _vqrshrn_n_u16(a, const { uint16x8_t([-N as u16; 8]) }) } } #[doc = "Unsigned signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqrshrn, N = 2))] @@ -40126,16 +39714,11 @@ pub fn vqrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v4i16")] fn _vqrshrn_n_u32(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t; } - unsafe { - _vqrshrn_n_u32( - a, - const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }, - ) - } + unsafe { _vqrshrn_n_u32(a, const { uint32x4_t([-N as u32; 4]) }) } } #[doc = "Unsigned signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqrshrn, N = 2))] @@ -40147,11 +39730,11 @@ pub fn vqrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v2i32")] fn _vqrshrn_n_u64(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t; } - unsafe { _vqrshrn_n_u64(a, const { uint64x2_t([-N as u64, -N as u64]) }) } + unsafe { _vqrshrn_n_u64(a, const { uint64x2_t([-N as u64; 2]) }) } } #[doc = "Unsigned signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(uqrshrn, N = 2))] @@ -40170,7 +39753,7 @@ pub fn vqrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { } #[doc = "Unsigned signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(uqrshrn, N = 2))] @@ -40189,7 +39772,7 @@ pub fn vqrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { } #[doc = "Unsigned signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(uqrshrn, N = 2))] @@ -40208,7 +39791,7 @@ pub fn vqrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqrshrun, N = 2))] @@ -40224,7 +39807,7 @@ pub fn vqrshrun_n_s16(a: int16x8_t) -> uint8x8_t { } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqrshrun, N = 2))] @@ -40240,7 +39823,7 @@ pub fn vqrshrun_n_s32(a: int32x4_t) -> uint16x4_t { } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqrshrun, N = 2))] @@ -40256,7 +39839,7 @@ pub fn vqrshrun_n_s64(a: int64x2_t) -> uint32x2_t { } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqrshrun, N = 2))] @@ -40275,7 +39858,7 @@ pub fn vqrshrun_n_s16(a: int16x8_t) -> uint8x8_t { } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqrshrun, N = 2))] @@ -40294,7 +39877,7 @@ pub fn vqrshrun_n_s32(a: int32x4_t) -> uint16x4_t { } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqrshrun, N = 2))] @@ -40313,7 +39896,7 @@ pub fn vqrshrun_n_s64(a: int64x2_t) -> uint32x2_t { } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] @@ -40336,7 +39919,7 @@ pub fn vqshl_n_s8(a: int8x8_t) -> int8x8_t { } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] @@ -40359,7 +39942,7 @@ pub fn vqshlq_n_s8(a: int8x16_t) -> int8x16_t { } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] @@ -40382,7 +39965,7 @@ pub fn vqshl_n_s16(a: int16x4_t) -> int16x4_t { } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] @@ -40405,7 +39988,7 @@ pub fn vqshlq_n_s16(a: int16x8_t) -> int16x8_t { } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] @@ -40428,7 +40011,7 @@ pub fn vqshl_n_s32(a: int32x2_t) -> int32x2_t { } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] @@ -40451,7 +40034,7 @@ pub fn vqshlq_n_s32(a: int32x4_t) -> int32x4_t { } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] @@ -40474,7 +40057,7 @@ pub fn vqshl_n_s64(a: int64x1_t) -> int64x1_t { } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] @@ -40497,7 +40080,7 @@ pub fn vqshlq_n_s64(a: int64x2_t) -> int64x2_t { } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] @@ -40520,7 +40103,7 @@ pub fn vqshl_n_u8(a: uint8x8_t) -> uint8x8_t { } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] @@ -40543,7 +40126,7 @@ pub fn vqshlq_n_u8(a: uint8x16_t) -> uint8x16_t { } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] @@ -40566,7 +40149,7 @@ pub fn vqshl_n_u16(a: uint16x4_t) -> uint16x4_t { } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] @@ -40589,7 +40172,7 @@ pub fn vqshlq_n_u16(a: uint16x8_t) -> uint16x8_t { } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] @@ -40612,7 +40195,7 @@ pub fn vqshl_n_u32(a: uint32x2_t) -> uint32x2_t { } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] @@ -40635,7 +40218,7 @@ pub fn vqshlq_n_u32(a: uint32x4_t) -> uint32x4_t { } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] @@ -40658,7 +40241,7 @@ pub fn vqshl_n_u64(a: uint64x1_t) -> uint64x1_t { } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] @@ -40681,7 +40264,7 @@ pub fn vqshlq_n_u64(a: uint64x2_t) -> uint64x2_t { } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] @@ -40710,7 +40293,7 @@ pub fn vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] @@ -40739,7 +40322,7 @@ pub fn vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] @@ -40768,7 +40351,7 @@ pub fn vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] @@ -40797,7 +40380,7 @@ pub fn vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] @@ -40826,7 +40409,7 @@ pub fn vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] @@ -40855,7 +40438,7 @@ pub fn vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] @@ -40884,7 +40467,7 @@ pub fn vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] @@ -40913,7 +40496,7 @@ pub fn vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] @@ -40942,7 +40525,7 @@ pub fn vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] @@ -40971,7 +40554,7 @@ pub fn vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] @@ -41000,7 +40583,7 @@ pub fn vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] @@ -41029,7 +40612,7 @@ pub fn vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] @@ -41058,7 +40641,7 @@ pub fn vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] @@ -41087,7 +40670,7 @@ pub fn vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] @@ -41116,7 +40699,7 @@ pub fn vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] @@ -41145,7 +40728,7 @@ pub fn vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshlu, N = 2))] @@ -41161,7 +40744,7 @@ pub fn vqshlu_n_s8(a: int8x8_t) -> uint8x8_t { } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshlu, N = 2))] @@ -41177,7 +40760,7 @@ pub fn vqshluq_n_s8(a: int8x16_t) -> uint8x16_t { } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshlu, N = 2))] @@ -41193,7 +40776,7 @@ pub fn vqshlu_n_s16(a: int16x4_t) -> uint16x4_t { } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshlu, N = 2))] @@ -41209,7 +40792,7 @@ pub fn vqshluq_n_s16(a: int16x8_t) -> uint16x8_t { } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshlu, N = 2))] @@ -41225,7 +40808,7 @@ pub fn vqshlu_n_s32(a: int32x2_t) -> uint32x2_t { } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshlu, N = 2))] @@ -41241,7 +40824,7 @@ pub fn vqshluq_n_s32(a: int32x4_t) -> uint32x4_t { } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshlu, N = 2))] @@ -41257,7 +40840,7 @@ pub fn vqshlu_n_s64(a: int64x1_t) -> uint64x1_t { } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshlu, N = 2))] @@ -41273,7 +40856,7 @@ pub fn vqshluq_n_s64(a: int64x2_t) -> uint64x2_t { } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] @@ -41292,7 +40875,7 @@ pub fn vqshlu_n_s8(a: int8x8_t) -> uint8x8_t { } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] @@ -41311,7 +40894,7 @@ pub fn vqshluq_n_s8(a: int8x16_t) -> uint8x16_t { } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] @@ -41330,7 +40913,7 @@ pub fn vqshlu_n_s16(a: int16x4_t) -> uint16x4_t { } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] @@ -41349,7 +40932,7 @@ pub fn vqshluq_n_s16(a: int16x8_t) -> uint16x8_t { } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] @@ -41368,7 +40951,7 @@ pub fn vqshlu_n_s32(a: int32x2_t) -> uint32x2_t { } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] @@ -41387,7 +40970,7 @@ pub fn vqshluq_n_s32(a: int32x4_t) -> uint32x4_t { } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] @@ -41406,7 +40989,7 @@ pub fn vqshlu_n_s64(a: int64x1_t) -> uint64x1_t { } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] @@ -41425,7 +41008,7 @@ pub fn vqshluq_n_s64(a: int64x2_t) -> uint64x2_t { } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshrn, N = 2))] @@ -41441,7 +41024,7 @@ pub fn vqshrn_n_s16(a: int16x8_t) -> int8x8_t { } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshrn, N = 2))] @@ -41457,7 +41040,7 @@ pub fn vqshrn_n_s32(a: int32x4_t) -> int16x4_t { } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshrn, N = 2))] @@ -41473,7 +41056,7 @@ pub fn vqshrn_n_s64(a: int64x2_t) -> int32x2_t { } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshrn, N = 2))] @@ -41492,7 +41075,7 @@ pub fn vqshrn_n_s16(a: int16x8_t) -> int8x8_t { } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshrn, N = 2))] @@ -41511,7 +41094,7 @@ pub fn vqshrn_n_s32(a: int32x4_t) -> int16x4_t { } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshrn, N = 2))] @@ -41530,7 +41113,7 @@ pub fn vqshrn_n_s64(a: int64x2_t) -> int32x2_t { } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshrn, N = 2))] @@ -41542,21 +41125,11 @@ pub fn vqshrn_n_u16(a: uint16x8_t) -> uint8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v8i8")] fn _vqshrn_n_u16(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t; } - unsafe { - _vqshrn_n_u16( - a, - const { - uint16x8_t([ - -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, - -N as u16, - ]) - }, - ) - } + unsafe { _vqshrn_n_u16(a, const { uint16x8_t([-N as u16; 8]) }) } } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshrn, N = 2))] @@ -41568,16 +41141,11 @@ pub fn vqshrn_n_u32(a: uint32x4_t) -> uint16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v4i16")] fn _vqshrn_n_u32(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t; } - unsafe { - _vqshrn_n_u32( - a, - const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }, - ) - } + unsafe { _vqshrn_n_u32(a, const { uint32x4_t([-N as u32; 4]) }) } } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshrn, N = 2))] @@ -41589,11 +41157,11 @@ pub fn vqshrn_n_u64(a: uint64x2_t) -> uint32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v2i32")] fn _vqshrn_n_u64(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t; } - unsafe { _vqshrn_n_u64(a, const { uint64x2_t([-N as u64, -N as u64]) }) } + unsafe { _vqshrn_n_u64(a, const { uint64x2_t([-N as u64; 2]) }) } } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(uqshrn, N = 2))] @@ -41612,7 +41180,7 @@ pub fn vqshrn_n_u16(a: uint16x8_t) -> uint8x8_t { } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(uqshrn, N = 2))] @@ -41631,7 +41199,7 @@ pub fn vqshrn_n_u32(a: uint32x4_t) -> uint16x4_t { } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(uqshrn, N = 2))] @@ -41650,7 +41218,7 @@ pub fn vqshrn_n_u64(a: uint64x2_t) -> uint32x2_t { } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshrun, N = 2))] @@ -41666,7 +41234,7 @@ pub fn vqshrun_n_s16(a: int16x8_t) -> uint8x8_t { } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshrun, N = 2))] @@ -41682,7 +41250,7 @@ pub fn vqshrun_n_s32(a: int32x4_t) -> uint16x4_t { } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshrun, N = 2))] @@ -41698,7 +41266,7 @@ pub fn vqshrun_n_s64(a: int64x2_t) -> uint32x2_t { } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshrun, N = 2))] @@ -41717,7 +41285,7 @@ pub fn vqshrun_n_s16(a: int16x8_t) -> uint8x8_t { } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshrun, N = 2))] @@ -41736,7 +41304,7 @@ pub fn vqshrun_n_s32(a: int32x4_t) -> uint16x4_t { } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshrun, N = 2))] @@ -41755,7 +41323,7 @@ pub fn vqshrun_n_s64(a: int64x2_t) -> uint32x2_t { } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))] @@ -41776,7 +41344,7 @@ pub fn vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))] @@ -41797,7 +41365,7 @@ pub fn vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))] @@ -41818,7 +41386,7 @@ pub fn vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))] @@ -41839,7 +41407,7 @@ pub fn vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))] @@ -41860,7 +41428,7 @@ pub fn vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))] @@ -41881,7 +41449,7 @@ pub fn vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))] @@ -41902,7 +41470,7 @@ pub fn vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))] @@ -41923,7 +41491,7 @@ pub fn vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))] @@ -41944,7 +41512,7 @@ pub fn vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))] @@ -41965,7 +41533,7 @@ pub fn vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))] @@ -41986,7 +41554,7 @@ pub fn vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))] @@ -42007,7 +41575,7 @@ pub fn vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))] @@ -42028,7 +41596,7 @@ pub fn vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))] @@ -42049,7 +41617,7 @@ pub fn vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))] @@ -42070,7 +41638,7 @@ pub fn vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))] @@ -42091,12 +41659,16 @@ pub fn vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Rounding Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(raddhn2) )] #[cfg_attr( @@ -42109,16 +41681,20 @@ pub fn vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { )] pub fn vraddhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t { let x = vraddhn_s16(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } + vcombine_s8(a, x) } #[doc = "Rounding Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(raddhn2) )] #[cfg_attr( @@ -42131,16 +41707,20 @@ pub fn vraddhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t { )] pub fn vraddhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { let x = vraddhn_s32(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_s16(a, x) } #[doc = "Rounding Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(raddhn2) )] #[cfg_attr( @@ -42153,16 +41733,20 @@ pub fn vraddhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { )] pub fn vraddhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t { let x = vraddhn_s64(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) } + vcombine_s32(a, x) } #[doc = "Rounding Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(raddhn2) )] #[cfg_attr( @@ -42176,17 +41760,21 @@ pub fn vraddhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t { pub fn vraddhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t { unsafe { let x: uint8x8_t = transmute(vraddhn_s16(transmute(b), transmute(c))); - simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) + vcombine_u8(a, x) } } #[doc = "Rounding Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(raddhn2) )] #[cfg_attr( @@ -42200,17 +41788,21 @@ pub fn vraddhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_ pub fn vraddhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t { unsafe { let x: uint16x4_t = transmute(vraddhn_s32(transmute(b), transmute(c))); - simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) + vcombine_u16(a, x) } } #[doc = "Rounding Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(raddhn2) )] #[cfg_attr( @@ -42224,12 +41816,12 @@ pub fn vraddhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8 pub fn vraddhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t { unsafe { let x: uint32x2_t = transmute(vraddhn_s64(transmute(b), transmute(c))); - simd_shuffle!(a, x, [0, 1, 2, 3]) + vcombine_u32(a, x) } } #[doc = "Rounding Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))] @@ -42258,7 +41850,7 @@ pub fn vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { } #[doc = "Rounding Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))] @@ -42287,7 +41879,7 @@ pub fn vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { } #[doc = "Rounding Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))] @@ -42316,8 +41908,7 @@ pub fn vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { } #[doc = "Rounding Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))] @@ -42337,36 +41928,8 @@ pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { unsafe { transmute(vraddhn_s16(transmute(a), transmute(b))) } } #[doc = "Rounding Add returning High Narrow."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(raddhn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vraddhn_s16(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Rounding Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))] @@ -42386,36 +41949,8 @@ pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { unsafe { transmute(vraddhn_s32(transmute(a), transmute(b))) } } #[doc = "Rounding Add returning High Narrow."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(raddhn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x4_t = transmute(vraddhn_s32(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Rounding Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))] @@ -42434,36 +41969,9 @@ pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { unsafe { transmute(vraddhn_s64(transmute(a), transmute(b))) } } -#[doc = "Rounding Add returning High Narrow."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(raddhn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) }; - unsafe { - let ret_val: uint32x2_t = transmute(vraddhn_s64(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] #[cfg_attr( @@ -42473,7 +41981,7 @@ pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42493,7 +42001,7 @@ pub fn vrecpe_f16(a: float16x4_t) -> float16x4_t { } #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] #[cfg_attr( @@ -42503,7 +42011,7 @@ pub fn vrecpe_f16(a: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42523,7 +42031,7 @@ pub fn vrecpeq_f16(a: float16x8_t) -> float16x8_t { } #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] @@ -42552,7 +42060,7 @@ pub fn vrecpe_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] @@ -42581,7 +42089,7 @@ pub fn vrecpeq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Unsigned reciprocal estimate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] @@ -42610,7 +42118,7 @@ pub fn vrecpe_u32(a: uint32x2_t) -> uint32x2_t { } #[doc = "Unsigned reciprocal estimate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] @@ -42639,7 +42147,7 @@ pub fn vrecpeq_u32(a: uint32x4_t) -> uint32x4_t { } #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))] #[cfg_attr( @@ -42649,7 +42157,7 @@ pub fn vrecpeq_u32(a: uint32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42669,7 +42177,7 @@ pub fn vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { } #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))] #[cfg_attr( @@ -42679,7 +42187,7 @@ pub fn vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42699,7 +42207,7 @@ pub fn vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { } #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))] @@ -42728,7 +42236,7 @@ pub fn vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))] @@ -42757,8 +42265,7 @@ pub fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -42768,7 +42275,7 @@ pub fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42779,9 +42286,8 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -42791,24 +42297,19 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -42818,20 +42319,19 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t { +pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -42841,24 +42341,19 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -42868,20 +42363,19 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t { +pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -42891,24 +42385,19 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -42918,20 +42407,19 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t { +pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -42941,24 +42429,19 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -42968,20 +42451,19 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t { +pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -42991,21 +42473,19 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43015,20 +42495,19 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t { +pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43038,24 +42517,19 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43065,20 +42539,19 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t { +pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43088,24 +42561,19 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43115,20 +42583,19 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t { +pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43138,24 +42605,19 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43165,20 +42627,19 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t { +pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43188,21 +42649,19 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43212,20 +42671,19 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t { +pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43235,24 +42693,19 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43262,20 +42715,19 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t { +pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43285,24 +42737,19 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43312,20 +42759,19 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t { +pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43335,24 +42781,19 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43362,20 +42803,19 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t { +pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43385,28 +42825,19 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43416,20 +42847,19 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t { +pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43439,24 +42869,19 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43466,20 +42891,19 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t { +pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43489,24 +42913,19 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43516,20 +42935,19 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t { +pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43539,24 +42957,19 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43566,20 +42979,19 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t { +pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43589,28 +43001,19 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43620,20 +43023,19 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t { +pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43643,24 +43045,19 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43670,20 +43067,19 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t { +pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43693,24 +43089,19 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43720,20 +43111,19 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t { +pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43743,24 +43133,19 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43770,20 +43155,19 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t { +pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43793,28 +43177,19 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43824,20 +43199,19 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t { +pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43847,24 +43221,19 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43874,20 +43243,18 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t { +pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43897,24 +43264,18 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43924,20 +43285,18 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t { +pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43947,24 +43306,18 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43974,20 +43327,18 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t { +pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -43997,24 +43348,18 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44024,20 +43369,18 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t { +pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44047,25 +43390,18 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44075,20 +43411,18 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t { +pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44098,24 +43432,18 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44125,20 +43453,18 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t { +pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44148,24 +43474,18 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44175,20 +43495,18 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t { +pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44198,24 +43516,18 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44225,20 +43537,18 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t { +pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44248,24 +43558,18 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44275,20 +43579,18 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t { +pub fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44298,23 +43600,18 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t { - unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44324,20 +43621,18 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t { +pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44347,24 +43642,18 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44374,20 +43663,18 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t { +pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44397,24 +43684,18 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44424,20 +43705,18 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t { +pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44447,25 +43726,18 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44475,20 +43747,18 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t { +pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44498,24 +43768,18 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44525,20 +43789,18 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t { +pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44548,24 +43810,18 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44575,20 +43831,18 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t { +pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44598,24 +43852,18 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44625,20 +43873,18 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t { +pub fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44648,24 +43894,18 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44675,20 +43915,18 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t { +pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44698,23 +43936,18 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t { - unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44724,20 +43957,18 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t { +pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44747,24 +43978,18 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44774,20 +43999,18 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t { +pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44797,24 +44020,18 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44824,20 +44041,18 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t { +pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44847,27 +44062,20 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -44875,22 +44083,21 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t { +pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -44898,26 +44105,21 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -44925,22 +44127,21 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t { +pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -44948,24 +44149,19 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44975,20 +44171,19 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t { +pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -44998,25 +44193,21 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t { - unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -45024,22 +44215,20 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t { +pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -45047,23 +44236,20 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -45071,22 +44257,20 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 { +pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -45094,23 +44278,20 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -45118,22 +44299,20 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t { +pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -45141,26 +44320,20 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -45168,22 +44341,20 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t { +pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -45191,25 +44362,20 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t { - unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -45217,22 +44383,20 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t { +pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -45240,24 +44404,18 @@ pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45273,13 +44431,12 @@ pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t { +pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45295,16 +44452,12 @@ pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t { - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45320,13 +44473,12 @@ pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t { +pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45342,17 +44494,12 @@ pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45368,13 +44515,12 @@ pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t { +pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45390,17 +44536,12 @@ pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45416,13 +44557,12 @@ pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t { +pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45438,17 +44578,12 @@ pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45464,13 +44599,12 @@ pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t { +pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45486,14 +44620,12 @@ pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45509,13 +44641,12 @@ pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t { +pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45531,17 +44662,12 @@ pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45557,13 +44683,12 @@ pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t { +pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45579,17 +44704,12 @@ pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45605,13 +44725,12 @@ pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t { +pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45627,17 +44746,12 @@ pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45653,13 +44767,12 @@ pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t { +pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45675,14 +44788,12 @@ pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45698,13 +44809,12 @@ pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t { +pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45720,17 +44830,12 @@ pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45746,13 +44851,12 @@ pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t { +pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45768,17 +44872,12 @@ pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45794,13 +44893,12 @@ pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 { +pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45816,14 +44914,12 @@ pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45839,13 +44935,12 @@ pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t { +pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45861,21 +44956,12 @@ pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45891,13 +44977,12 @@ pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t { +pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45913,17 +44998,12 @@ pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45939,13 +45019,12 @@ pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t { +pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45961,17 +45040,12 @@ pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -45987,13 +45061,12 @@ pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t { +pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46009,17 +45082,12 @@ pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46035,13 +45103,12 @@ pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t { +pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46057,21 +45124,12 @@ pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46087,13 +45145,12 @@ pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t { +pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46109,17 +45166,12 @@ pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46135,13 +45187,12 @@ pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t { +pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46157,17 +45208,12 @@ pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46183,13 +45229,12 @@ pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t { +pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46205,17 +45250,12 @@ pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46231,13 +45271,12 @@ pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t { +pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46253,21 +45292,12 @@ pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46283,13 +45313,12 @@ pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t { +pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46305,17 +45334,12 @@ pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46331,13 +45355,12 @@ pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t { +pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46353,17 +45376,12 @@ pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46379,13 +45397,12 @@ pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t { +pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46401,17 +45418,12 @@ pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46427,13 +45439,12 @@ pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t { +pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46449,17 +45460,12 @@ pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46475,13 +45481,12 @@ pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t { +pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46497,14 +45502,12 @@ pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46520,13 +45523,12 @@ pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t { +pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46542,17 +45544,12 @@ pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46568,13 +45565,12 @@ pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t { +pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46590,17 +45586,12 @@ pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46616,13 +45607,12 @@ pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t { +pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46638,17 +45628,12 @@ pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46664,13 +45649,12 @@ pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t { +pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46686,14 +45670,12 @@ pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46709,13 +45691,12 @@ pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t { +pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46731,17 +45712,12 @@ pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46757,13 +45733,12 @@ pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t { +pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46779,17 +45754,12 @@ pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46805,13 +45775,12 @@ pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t { +pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46827,18 +45796,12 @@ pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46854,13 +45817,12 @@ pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t { +pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46876,18 +45838,12 @@ pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46903,13 +45859,12 @@ pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t { +pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46925,18 +45880,12 @@ pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46952,13 +45901,12 @@ pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t { +pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -46974,18 +45922,12 @@ pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47001,13 +45943,12 @@ pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t { +pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47023,22 +45964,12 @@ pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47054,13 +45985,12 @@ pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t { +pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47076,18 +46006,12 @@ pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47103,13 +46027,12 @@ pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t { +pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47125,18 +46048,12 @@ pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47152,13 +46069,12 @@ pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t { +pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47174,18 +46090,12 @@ pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47201,13 +46111,12 @@ pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t { +pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47223,22 +46132,12 @@ pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47254,13 +46153,12 @@ pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t { +pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47276,18 +46174,12 @@ pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47303,13 +46195,12 @@ pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t { +pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47325,17 +46216,12 @@ pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47351,13 +46237,12 @@ pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t { +pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47373,17 +46258,12 @@ pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47399,13 +46279,12 @@ pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t { +pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47421,17 +46300,12 @@ pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47447,13 +46321,12 @@ pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t { +pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47469,14 +46342,12 @@ pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47492,13 +46363,12 @@ pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t { +pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47514,17 +46384,12 @@ pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47540,13 +46405,12 @@ pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t { +pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47562,17 +46426,12 @@ pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47588,13 +46447,12 @@ pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t { +pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47610,17 +46468,12 @@ pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47636,13 +46489,12 @@ pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t { +pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47658,14 +46510,12 @@ pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47681,13 +46531,12 @@ pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t { +pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47703,17 +46552,12 @@ pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47729,13 +46573,12 @@ pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t { +pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47751,17 +46594,12 @@ pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47777,13 +46615,12 @@ pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t { +pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47799,17 +46636,12 @@ pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47825,13 +46657,12 @@ pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t { +pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47847,21 +46678,12 @@ pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47877,13 +46699,12 @@ pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t { +pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47899,17 +46720,12 @@ pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47925,13 +46741,12 @@ pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t { +pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47947,17 +46762,12 @@ pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47973,13 +46783,12 @@ pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t { +pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47995,21 +46804,12 @@ pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48025,13 +46825,12 @@ pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t { +pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48047,17 +46846,12 @@ pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48073,13 +46867,12 @@ pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t { +pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48095,17 +46888,12 @@ pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48121,13 +46909,12 @@ pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t { +pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48143,17 +46930,12 @@ pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48169,13 +46951,12 @@ pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t { +pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48191,21 +46972,12 @@ pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48221,13 +46993,12 @@ pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t { +pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48243,17 +47014,12 @@ pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48269,13 +47035,12 @@ pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t { +pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48291,17 +47056,12 @@ pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48317,13 +47077,12 @@ pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t { +pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48339,17 +47098,12 @@ pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48365,13 +47119,12 @@ pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t { +pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48387,17 +47140,12 @@ pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48413,13 +47161,12 @@ pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t { +pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48435,14 +47182,12 @@ pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48458,13 +47203,12 @@ pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t { +pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48480,17 +47224,12 @@ pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48506,13 +47245,12 @@ pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t { +pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48528,17 +47266,12 @@ pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48554,13 +47287,12 @@ pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t { +pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48576,17 +47308,12 @@ pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48602,13 +47329,12 @@ pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t { +pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48624,14 +47350,12 @@ pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48647,13 +47371,12 @@ pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t { +pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48669,17 +47392,12 @@ pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48695,13 +47413,12 @@ pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t { +pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48717,17 +47434,12 @@ pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48743,13 +47455,12 @@ pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t { +pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48765,17 +47476,12 @@ pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48791,13 +47497,12 @@ pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t { +pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48813,21 +47518,12 @@ pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48843,13 +47539,12 @@ pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t { +pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48865,17 +47560,12 @@ pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48891,13 +47581,12 @@ pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t { +pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48913,17 +47602,12 @@ pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48939,13 +47623,12 @@ pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t { +pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48961,21 +47644,12 @@ pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48991,13 +47665,12 @@ pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t { +pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49013,17 +47686,12 @@ pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49039,13 +47707,12 @@ pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t { +pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49061,17 +47728,12 @@ pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49087,13 +47749,12 @@ pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t { +pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49109,17 +47770,12 @@ pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49135,13 +47791,12 @@ pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t { +pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49157,21 +47812,12 @@ pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49187,13 +47833,12 @@ pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t { +pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49209,17 +47854,12 @@ pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49235,13 +47875,12 @@ pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t { +pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49257,16 +47896,12 @@ pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t { - unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49282,13 +47917,12 @@ pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t { +pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49304,16 +47938,12 @@ pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t { - unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49329,13 +47959,12 @@ pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t { +pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49351,16 +47980,12 @@ pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t { - unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49376,13 +48001,12 @@ pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t { +pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49398,16 +48022,12 @@ pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t { - unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49423,13 +48043,12 @@ pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t { +pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49445,16 +48064,12 @@ pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t { - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49470,13 +48085,12 @@ pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t { +pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49492,16 +48106,12 @@ pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t { - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49517,13 +48127,12 @@ pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t { +pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49539,15 +48148,12 @@ pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t { - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49563,13 +48169,12 @@ pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t { +pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49585,13 +48190,12 @@ pub fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t { +pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49607,16 +48211,12 @@ pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t { - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49632,13 +48232,12 @@ pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t { +pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49654,16 +48253,12 @@ pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t { - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49679,13 +48274,12 @@ pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t { +pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49701,17 +48295,12 @@ pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49727,13 +48316,12 @@ pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t { +pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49749,21 +48337,12 @@ pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49779,13 +48358,12 @@ pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t { +pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49801,17 +48379,12 @@ pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49827,13 +48400,12 @@ pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t { +pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49849,17 +48421,12 @@ pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49875,13 +48442,12 @@ pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t { +pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49897,21 +48463,12 @@ pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49927,13 +48484,12 @@ pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t { +pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49949,17 +48505,12 @@ pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49975,13 +48526,12 @@ pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t { +pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49997,17 +48547,12 @@ pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50023,13 +48568,12 @@ pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t { +pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50045,17 +48589,12 @@ pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50071,13 +48610,12 @@ pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t { +pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50093,21 +48631,12 @@ pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50123,13 +48652,12 @@ pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t { +pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50145,17 +48673,12 @@ pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50171,13 +48694,12 @@ pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t { +pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50193,17 +48715,12 @@ pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50219,13 +48736,12 @@ pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t { +pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50241,17 +48757,12 @@ pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50267,13 +48778,12 @@ pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t { +pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50289,17 +48799,12 @@ pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50315,13 +48820,12 @@ pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t { +pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50337,17 +48841,12 @@ pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50363,13 +48862,12 @@ pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t { +pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50385,14 +48883,12 @@ pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50408,15 +48904,14 @@ pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t { +pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -50430,19 +48925,14 @@ pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -50456,15 +48946,14 @@ pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t { +pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -50478,19 +48967,14 @@ pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -50504,15 +48988,14 @@ pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t { +pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -50526,16 +49009,14 @@ pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -50549,15 +49030,14 @@ pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t { +pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -50571,19 +49051,14 @@ pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -50597,15 +49072,14 @@ pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t { +pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -50619,41 +49093,14 @@ pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -50667,20 +49114,14 @@ pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -50694,15 +49135,14 @@ pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t { +pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -50716,28 +49156,19 @@ pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 { + unsafe { transmute(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_p8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -50747,19 +49178,19 @@ pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t { - unsafe { transmute(a) } +pub fn vrev16_p8(a: poly8x8_t) -> poly8x8_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_p8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -50769,24 +49200,23 @@ pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vrev16_p8(a: poly8x8_t) -> poly8x8_t { unsafe { - let ret_val: int16x8_t = transmute(a); + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_s8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -50796,19 +49226,19 @@ pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t { - unsafe { transmute(a) } +pub fn vrev16_s8(a: int8x8_t) -> int8x8_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_s8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -50818,24 +49248,23 @@ pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vrev16_s8(a: int8x8_t) -> int8x8_t { unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_u8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -50845,19 +49274,19 @@ pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t { - unsafe { transmute(a) } +pub fn vrev16_u8(a: uint8x8_t) -> uint8x8_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_u8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -50867,24 +49296,23 @@ pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vrev16_u8(a: uint8x8_t) -> uint8x8_t { unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_p8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -50894,19 +49322,19 @@ pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t { - unsafe { transmute(a) } +pub fn vrev16q_p8(a: poly8x16_t) -> poly8x16_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_p8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -50916,24 +49344,29 @@ pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vrev16q_p8(a: poly8x16_t) -> poly8x16_t { unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = + simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_s8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -50943,19 +49376,19 @@ pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t { - unsafe { transmute(a) } +pub fn vrev16q_s8(a: int8x16_t) -> int8x16_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_s8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -50965,24 +49398,29 @@ pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vrev16q_s8(a: int8x16_t) -> int8x16_t { unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = + simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_u8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -50992,19 +49430,19 @@ pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t { - unsafe { transmute(a) } +pub fn vrev16q_u8(a: uint8x16_t) -> uint8x16_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_u8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -51014,24 +49452,29 @@ pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vrev16q_u8(a: uint8x16_t) -> uint8x16_t { unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = + simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51041,19 +49484,19 @@ pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t { - unsafe { transmute(a) } +pub fn vrev32_p16(a: poly16x4_t) -> poly16x4_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51063,28 +49506,23 @@ pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vrev32_p16(a: poly16x4_t) -> poly16x4_t { unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, a, [1, 0, 3, 2]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51094,19 +49532,19 @@ pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t { - unsafe { transmute(a) } +pub fn vrev32_p8(a: poly8x8_t) -> poly8x8_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51116,24 +49554,23 @@ pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vrev32_p8(a: poly8x8_t) -> poly8x8_t { unsafe { - let ret_val: poly16x8_t = transmute(a); + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51143,19 +49580,19 @@ pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t { - unsafe { transmute(a) } +pub fn vrev32_s16(a: int16x4_t) -> int16x4_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51165,23 +49602,23 @@ pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vrev32_s16(a: int16x4_t) -> int16x4_t { unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, a, [1, 0, 3, 2]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51191,19 +49628,19 @@ pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t { - unsafe { transmute(a) } +pub fn vrev32_s8(a: int8x8_t) -> int8x8_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51213,23 +49650,23 @@ pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vrev32_s8(a: int8x8_t) -> int8x8_t { unsafe { - let ret_val: int8x8_t = transmute(a); + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51239,19 +49676,19 @@ pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t { - unsafe { transmute(a) } +pub fn vrev32_u16(a: uint16x4_t) -> uint16x4_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51261,23 +49698,23 @@ pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vrev32_u16(a: uint16x4_t) -> uint16x4_t { unsafe { - let ret_val: int16x4_t = transmute(a); + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, a, [1, 0, 3, 2]); simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51287,19 +49724,19 @@ pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t { - unsafe { transmute(a) } +pub fn vrev32_u8(a: uint8x8_t) -> uint8x8_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51309,23 +49746,23 @@ pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vrev32_u8(a: uint8x8_t) -> uint8x8_t { unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51335,19 +49772,19 @@ pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t { - unsafe { transmute(a) } +pub fn vrev32q_p16(a: poly16x8_t) -> poly16x8_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51357,20 +49794,23 @@ pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vrev32q_p16(a: poly16x8_t) -> poly16x8_t { + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51380,19 +49820,19 @@ pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t { - unsafe { transmute(a) } +pub fn vrev32q_p8(a: poly8x16_t) -> poly8x16_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51402,23 +49842,29 @@ pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vrev32q_p8(a: poly8x16_t) -> poly8x16_t { unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = + simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51428,19 +49874,19 @@ pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t { - unsafe { transmute(a) } +pub fn vrev32q_s16(a: int16x8_t) -> int16x8_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51450,23 +49896,23 @@ pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vrev32q_s16(a: int16x8_t) -> int16x8_t { unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51476,19 +49922,19 @@ pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t { - unsafe { transmute(a) } +pub fn vrev32q_s8(a: int8x16_t) -> int8x16_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51498,20 +49944,29 @@ pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vrev32q_s8(a: int8x16_t) -> int8x16_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = + simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51521,19 +49976,19 @@ pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t { - unsafe { transmute(a) } +pub fn vrev32q_u16(a: uint16x8_t) -> uint16x8_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51543,23 +49998,23 @@ pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vrev32q_u16(a: uint16x8_t) -> uint16x8_t { unsafe { - let ret_val: poly8x8_t = transmute(a); + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51569,19 +50024,19 @@ pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t { - unsafe { transmute(a) } +pub fn vrev32q_u8(a: uint8x16_t) -> uint8x16_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -51591,23 +50046,29 @@ pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vrev32q_u8(a: uint8x16_t) -> uint8x16_t { unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = + simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -51617,19 +50078,19 @@ pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t { - unsafe { transmute(a) } +pub fn vrev64_f32(a: float32x2_t) -> float32x2_t { + unsafe { simd_shuffle!(a, a, [1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -51639,23 +50100,23 @@ pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vrev64_f32(a: float32x2_t) -> float32x2_t { unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, a, [1, 0]); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -51665,19 +50126,19 @@ pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t { - unsafe { transmute(a) } +pub fn vrev64_p16(a: poly16x4_t) -> poly16x4_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -51687,27 +50148,23 @@ pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vrev64_p16(a: poly16x4_t) -> poly16x4_t { unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -51717,19 +50174,19 @@ pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t { - unsafe { transmute(a) } +pub fn vrev64_p8(a: poly8x8_t) -> poly8x8_t { + unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -51739,23 +50196,23 @@ pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vrev64_p8(a: poly8x8_t) -> poly8x8_t { unsafe { - let ret_val: int16x8_t = transmute(a); + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -51765,19 +50222,19 @@ pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t { - unsafe { transmute(a) } +pub fn vrev64_s16(a: int16x4_t) -> int16x4_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -51787,23 +50244,23 @@ pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vrev64_s16(a: int16x4_t) -> int16x4_t { unsafe { - let ret_val: int32x4_t = transmute(a); + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -51813,19 +50270,19 @@ pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t { - unsafe { transmute(a) } +pub fn vrev64_s32(a: int32x2_t) -> int32x2_t { + unsafe { simd_shuffle!(a, a, [1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -51835,23 +50292,23 @@ pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vrev64_s32(a: int32x2_t) -> int32x2_t { unsafe { - let ret_val: int64x2_t = transmute(a); + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, a, [1, 0]); simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -51861,19 +50318,19 @@ pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t { - unsafe { transmute(a) } +pub fn vrev64_s8(a: int8x8_t) -> int8x8_t { + unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -51883,27 +50340,23 @@ pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vrev64_s8(a: int8x8_t) -> int8x8_t { unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -51913,19 +50366,19 @@ pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t { - unsafe { transmute(a) } +pub fn vrev64_u16(a: uint16x4_t) -> uint16x4_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -51935,23 +50388,23 @@ pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vrev64_u16(a: uint16x4_t) -> uint16x4_t { unsafe { - let ret_val: uint32x4_t = transmute(a); + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -51961,19 +50414,19 @@ pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t { - unsafe { transmute(a) } +pub fn vrev64_u32(a: uint32x2_t) -> uint32x2_t { + unsafe { simd_shuffle!(a, a, [1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -51983,23 +50436,23 @@ pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vrev64_u32(a: uint32x2_t) -> uint32x2_t { unsafe { - let ret_val: uint64x2_t = transmute(a); + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, a, [1, 0]); simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -52009,19 +50462,19 @@ pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t { - unsafe { transmute(a) } +pub fn vrev64_u8(a: uint8x8_t) -> uint8x8_t { + unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -52031,27 +50484,23 @@ pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vrev64_u8(a: uint8x8_t) -> uint8x8_t { unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -52061,19 +50510,19 @@ pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t { - unsafe { transmute(a) } +pub fn vrev64q_f32(a: float32x4_t) -> float32x4_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -52083,23 +50532,23 @@ pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vrev64q_f32(a: float32x4_t) -> float32x4_t { unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: float32x4_t = simd_shuffle!(a, a, [1, 0, 3, 2]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -52109,19 +50558,19 @@ pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t { - unsafe { transmute(a) } +pub fn vrev64q_p16(a: poly16x8_t) -> poly16x8_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -52131,23 +50580,23 @@ pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vrev64q_p16(a: poly16x8_t) -> poly16x8_t { unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -52157,19 +50606,19 @@ pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t { - unsafe { transmute(a) } +pub fn vrev64q_p8(a: poly8x16_t) -> poly8x16_t { + unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -52179,23 +50628,29 @@ pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vrev64q_p8(a: poly8x16_t) -> poly8x16_t { unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = + simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -52205,19 +50660,19 @@ pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t { - unsafe { transmute(a) } +pub fn vrev64q_s16(a: int16x8_t) -> int16x8_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -52227,23 +50682,23 @@ pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vrev64q_s16(a: int16x8_t) -> int16x8_t { unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -52253,19 +50708,19 @@ pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t { - unsafe { transmute(a) } +pub fn vrev64q_s32(a: int32x4_t) -> int32x4_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -52275,23 +50730,23 @@ pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vrev64q_s32(a: int32x4_t) -> int32x4_t { unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: int32x4_t = simd_shuffle!(a, a, [1, 0, 3, 2]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -52301,19 +50756,19 @@ pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t { - unsafe { transmute(a) } +pub fn vrev64q_s8(a: int8x16_t) -> int8x16_t { + unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -52323,20 +50778,29 @@ pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { transmute(a) } +pub fn vrev64q_s8(a: int8x16_t) -> int8x16_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = + simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -52346,19 +50810,19 @@ pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t { - unsafe { transmute(a) } +pub fn vrev64q_u16(a: uint16x8_t) -> uint16x8_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -52368,23 +50832,23 @@ pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vrev64q_u16(a: uint16x8_t) -> uint16x8_t { unsafe { - let ret_val: uint8x8_t = transmute(a); + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -52394,19 +50858,19 @@ pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t { - unsafe { transmute(a) } +pub fn vrev64q_u32(a: uint32x4_t) -> uint32x4_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -52416,23 +50880,23 @@ pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vrev64q_u32(a: uint32x4_t) -> uint32x4_t { unsafe { - let ret_val: uint16x4_t = transmute(a); + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: uint32x4_t = simd_shuffle!(a, a, [1, 0, 3, 2]); simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -52442,19 +50906,19 @@ pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t { - unsafe { transmute(a) } +pub fn vrev64q_u8(a: uint8x16_t) -> uint8x16_t { + unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -52464,116 +50928,128 @@ pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { transmute(a) } +pub fn vrev64q_u8(a: uint8x16_t) -> uint8x16_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = + simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"] -#[inline(always)] +#[doc = "Reverse elements in 64-bit doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f16)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t { - unsafe { transmute(a) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vrev64_f16(a: float16x4_t) -> float16x4_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"] -#[inline(always)] +#[doc = "Reverse elements in 64-bit doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f16)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +#[cfg(not(target_arch = "arm64ec"))] +pub fn vrev64_f16(a: float16x4_t) -> float16x4_t { unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"] -#[inline(always)] +#[doc = "Reverse elements in 64-bit doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f16)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t { - unsafe { transmute(a) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vrev64q_f16(a: float16x8_t) -> float16x8_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"] -#[inline(always)] +#[doc = "Reverse elements in 64-bit doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f16)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +#[cfg(not(target_arch = "arm64ec"))] +pub fn vrev64q_f16(a: float16x8_t) -> float16x8_t { unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -52583,19 +51059,26 @@ pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t { - unsafe { transmute(a) } +pub fn vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srhadd.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v8i8")] + fn _vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + unsafe { _vrhadd_s8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -52605,23 +51088,26 @@ pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srhadd.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v16i8")] + fn _vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } + unsafe { _vrhaddq_s8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -52631,19 +51117,26 @@ pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t { - unsafe { transmute(a) } +pub fn vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srhadd.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v4i16")] + fn _vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + unsafe { _vrhadd_s16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -52653,27 +51146,26 @@ pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) +pub fn vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srhadd.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v8i16")] + fn _vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } + unsafe { _vrhaddq_s16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -52683,19 +51175,26 @@ pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t { - unsafe { transmute(a) } +pub fn vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srhadd.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v2i32")] + fn _vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + unsafe { _vrhadd_s32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -52705,23 +51204,26 @@ pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srhadd.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v4i32")] + fn _vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } + unsafe { _vrhaddq_s32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -52731,19 +51233,26 @@ pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t { - unsafe { transmute(a) } +pub fn vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urhadd.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v8i8")] + fn _vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; + } + unsafe { _vrhadd_u8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -52753,23 +51262,26 @@ pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urhadd.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v16i8")] + fn _vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; } + unsafe { _vrhaddq_u8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -52779,19 +51291,26 @@ pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t { - unsafe { transmute(a) } +pub fn vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urhadd.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v4i16")] + fn _vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; + } + unsafe { _vrhadd_u16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -52801,23 +51320,26 @@ pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urhadd.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v8i16")] + fn _vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; } + unsafe { _vrhaddq_u16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -52827,19 +51349,26 @@ pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t { - unsafe { transmute(a) } +pub fn vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urhadd.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v2i32")] + fn _vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; + } + unsafe { _vrhadd_u32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -52849,75 +51378,84 @@ pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) +pub fn vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urhadd.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v4i32")] + fn _vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; } + unsafe { _vrhaddq_u32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Floating-point round to integral, to nearest with ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(frintn) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t { - unsafe { transmute(a) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vrndn_f16(a: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec", target_arch = "arm"), + link_name = "llvm.roundeven.v4f16" + )] + fn _vrndn_f16(a: float16x4_t) -> float16x4_t; + } + unsafe { _vrndn_f16(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Floating-point round to integral, to nearest with ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(frintn) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +#[cfg(not(target_arch = "arm64ec"))] +pub fn vrndnq_f16(a: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec", target_arch = "arm"), + link_name = "llvm.roundeven.v8f16" + )] + fn _vrndnq_f16(a: float16x8_t) -> float16x8_t; } + unsafe { _vrndnq_f16(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Floating-point round to integral, to nearest with ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(frintn) )] #[cfg_attr( not(target_arch = "arm"), @@ -52927,19 +51465,25 @@ pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t { - unsafe { transmute(a) } +pub fn vrndn_f32(a: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec", target_arch = "arm"), + link_name = "llvm.roundeven.v2f32" + )] + fn _vrndn_f32(a: float32x2_t) -> float32x2_t; + } + unsafe { _vrndn_f32(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Floating-point round to integral, to nearest with ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(frintn) )] #[cfg_attr( not(target_arch = "arm"), @@ -52949,23 +51493,25 @@ pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vrndnq_f32(a: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec", target_arch = "arm"), + link_name = "llvm.roundeven.v4f32" + )] + fn _vrndnq_f32(a: float32x4_t) -> float32x4_t; } + unsafe { _vrndnq_f32(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -52975,19 +51521,26 @@ pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t { - unsafe { transmute(a) } +pub fn vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srshl.v8i8" + )] + fn _vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + unsafe { _vrshl_s8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -52997,27 +51550,26 @@ pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) +pub fn vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srshl.v16i8" + )] + fn _vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } + unsafe { _vrshlq_s8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -53027,19 +51579,26 @@ pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t { - unsafe { transmute(a) } +pub fn vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srshl.v4i16" + )] + fn _vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + unsafe { _vrshl_s16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -53049,23 +51608,26 @@ pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srshl.v8i16" + )] + fn _vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } + unsafe { _vrshlq_s16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -53075,19 +51637,26 @@ pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t { - unsafe { transmute(a) } +pub fn vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srshl.v2i32" + )] + fn _vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + unsafe { _vrshl_s32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -53097,22 +51666,26 @@ pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t { - unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srshl.v4i32" + )] + fn _vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } + unsafe { _vrshlq_s32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -53122,19 +51695,26 @@ pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t { - unsafe { transmute(a) } +pub fn vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v1i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srshl.v1i64" + )] + fn _vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t; + } + unsafe { _vrshl_s64(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -53144,44 +51724,26 @@ pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t { - unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v2i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srshl.v2i64" + )] + fn _vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; } + unsafe { _vrshlq_s64(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -53191,22 +51753,26 @@ pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t { - unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urshl.v8i8" + )] + fn _vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t; } + unsafe { _vrshl_u8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -53216,19 +51782,26 @@ pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t { - unsafe { transmute(a) } +pub fn vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urshl.v16i8" + )] + fn _vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t; + } + unsafe { _vrshlq_u8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -53238,21 +51811,26 @@ pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t { - unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urshl.v4i16" + )] + fn _vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t; } + unsafe { _vrshl_u16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u64)"] -#[inline(always)] +#[doc = "Unsigned rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -53262,19 +51840,26 @@ pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t { - unsafe { transmute(a) } +pub fn vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urshl.v8i16" + )] + fn _vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t; + } + unsafe { _vrshlq_u16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -53284,19 +51869,26 @@ pub fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t { - unsafe { transmute(a) } +pub fn vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urshl.v2i32" + )] + fn _vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t; + } + unsafe { _vrshl_u32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -53306,22 +51898,26 @@ pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t { - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urshl.v4i32" + )] + fn _vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t; } + unsafe { _vrshlq_u32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -53331,19 +51927,26 @@ pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t { - unsafe { transmute(a) } +pub fn vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v1i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urshl.v1i64" + )] + fn _vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t; + } + unsafe { _vrshl_u64(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -53353,23 +51956,28 @@ pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t { - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v2i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urshl.v2i64" + )] + fn _vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t; } + unsafe { _vrshlq_u64(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -53378,20 +51986,21 @@ pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t { - unsafe { transmute(a) } +pub fn vrshr_n_s8(a: int8x8_t) -> int8x8_t { + static_assert!(N >= 1 && N <= 8); + vrshl_s8(a, vdup_n_s8(-N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -53400,23 +52009,21 @@ pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t { - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vrshrq_n_s8(a: int8x16_t) -> int8x16_t { + static_assert!(N >= 1 && N <= 8); + vrshlq_s8(a, vdupq_n_s8(-N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -53425,20 +52032,21 @@ pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t { - unsafe { transmute(a) } +pub fn vrshr_n_s16(a: int16x4_t) -> int16x4_t { + static_assert!(N >= 1 && N <= 16); + vrshl_s16(a, vdup_n_s16(-N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -53447,23 +52055,21 @@ pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t { - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vrshrq_n_s16(a: int16x8_t) -> int16x8_t { + static_assert!(N >= 1 && N <= 16); + vrshlq_s16(a, vdupq_n_s16(-N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -53472,20 +52078,21 @@ pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t { - unsafe { transmute(a) } +pub fn vrshr_n_s32(a: int32x2_t) -> int32x2_t { + static_assert!(N >= 1 && N <= 32); + vrshl_s32(a, vdup_n_s32(-N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -53494,23 +52101,21 @@ pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t { - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vrshrq_n_s32(a: int32x4_t) -> int32x4_t { + static_assert!(N >= 1 && N <= 32); + vrshlq_s32(a, vdupq_n_s32(-N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -53519,20 +52124,21 @@ pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t { - unsafe { transmute(a) } +pub fn vrshr_n_s64(a: int64x1_t) -> int64x1_t { + static_assert!(N >= 1 && N <= 64); + vrshl_s64(a, vdup_n_s64(-N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -53541,24 +52147,21 @@ pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vrshrq_n_s64(a: int64x2_t) -> int64x2_t { + static_assert!(N >= 1 && N <= 64); + vrshlq_s64(a, vdupq_n_s64(-N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -53567,20 +52170,21 @@ pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t { - unsafe { transmute(a) } +pub fn vrshr_n_u8(a: uint8x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); + vrshl_u8(a, vdup_n_s8(-N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -53589,28 +52193,21 @@ pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vrshrq_n_u8(a: uint8x16_t) -> uint8x16_t { + static_assert!(N >= 1 && N <= 8); + vrshlq_u8(a, vdupq_n_s8(-N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -53619,20 +52216,21 @@ pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t { - unsafe { transmute(a) } +pub fn vrshr_n_u16(a: uint16x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + vrshl_u16(a, vdup_n_s16(-N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -53641,24 +52239,21 @@ pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vrshrq_n_u16(a: uint16x8_t) -> uint16x8_t { + static_assert!(N >= 1 && N <= 16); + vrshlq_u16(a, vdupq_n_s16(-N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -53667,20 +52262,21 @@ pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t { - unsafe { transmute(a) } +pub fn vrshr_n_u32(a: uint32x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + vrshl_u32(a, vdup_n_s32(-N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -53689,24 +52285,21 @@ pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vrshrq_n_u32(a: uint32x4_t) -> uint32x4_t { + static_assert!(N >= 1 && N <= 32); + vrshlq_u32(a, vdupq_n_s32(-N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -53715,20 +52308,21 @@ pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t { - unsafe { transmute(a) } +pub fn vrshr_n_u64(a: uint64x1_t) -> uint64x1_t { + static_assert!(N >= 1 && N <= 64); + vrshl_u64(a, vdup_n_s64(-N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -53737,46 +52331,126 @@ pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vrshrq_n_u64(a: uint64x2_t) -> uint64x2_t { + static_assert!(N >= 1 && N <= 64); + vrshlq_u64(a, vdupq_n_s64(-N as _)) +} +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vrshrn_n_s16(a: int16x8_t) -> int8x8_t { + static_assert!(N >= 1 && N <= 8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v8i8")] + fn _vrshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t; } + unsafe { _vrshrn_n_s16(a, const { int16x8_t([-N as i16; 8]) }) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t { - unsafe { transmute(a) } +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vrshrn_n_s32(a: int32x4_t) -> int16x4_t { + static_assert!(N >= 1 && N <= 16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v4i16")] + fn _vrshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t; + } + unsafe { _vrshrn_n_s32(a, const { int32x4_t([-N; 4]) }) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vrshrn_n_s64(a: int64x2_t) -> int32x2_t { + static_assert!(N >= 1 && N <= 32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v2i32")] + fn _vrshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t; + } + unsafe { _vrshrn_n_s64(a, const { int64x2_t([-N as i64; 2]) }) } +} +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(rshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vrshrn_n_s16(a: int16x8_t) -> int8x8_t { + static_assert!(N >= 1 && N <= 8); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.rshrn.v8i8" + )] + fn _vrshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t; + } + unsafe { _vrshrn_n_s16(a, N) } +} +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(rshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vrshrn_n_s32(a: int32x4_t) -> int16x4_t { + static_assert!(N >= 1 && N <= 16); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.rshrn.v4i16" + )] + fn _vrshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t; + } + unsafe { _vrshrn_n_s32(a, N) } +} +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(rshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vrshrn_n_s64(a: int64x2_t) -> int32x2_t { + static_assert!(N >= 1 && N <= 32); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.rshrn.v2i32" + )] + fn _vrshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t; + } + unsafe { _vrshrn_n_s64(a, N) } +} +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))] +#[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rshrn, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -53785,28 +52459,21 @@ pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); + unsafe { transmute(vrshrn_n_s16::(transmute(a))) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rshrn, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -53815,20 +52482,21 @@ pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t { - unsafe { transmute(a) } +pub fn vrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + unsafe { transmute(vrshrn_n_s32::(transmute(a))) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rshrn, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -53837,71 +52505,79 @@ pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + unsafe { transmute(vrshrn_n_s64::(transmute(a))) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Reciprocal square-root estimate."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(frsqrte) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t { - unsafe { transmute(a) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vrsqrte_f16(a: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frsqrte.v4f16" + )] + fn _vrsqrte_f16(a: float16x4_t) -> float16x4_t; + } + unsafe { _vrsqrte_f16(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Reciprocal square-root estimate."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(frsqrte) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +#[cfg(not(target_arch = "arm64ec"))] +pub fn vrsqrteq_f16(a: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v8f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frsqrte.v8f16" + )] + fn _vrsqrteq_f16(a: float16x8_t) -> float16x8_t; } + unsafe { _vrsqrteq_f16(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Reciprocal square-root estimate."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(frsqrte) )] #[cfg_attr( not(target_arch = "arm"), @@ -53911,19 +52587,26 @@ pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t { - unsafe { transmute(a) } +pub fn vrsqrte_f32(a: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frsqrte.v2f32" + )] + fn _vrsqrte_f32(a: float32x2_t) -> float32x2_t; + } + unsafe { _vrsqrte_f32(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Reciprocal square-root estimate."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(frsqrte) )] #[cfg_attr( not(target_arch = "arm"), @@ -53933,27 +52616,26 @@ pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) +pub fn vrsqrteq_f32(a: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frsqrte.v4f32" + )] + fn _vrsqrteq_f32(a: float32x4_t) -> float32x4_t; } + unsafe { _vrsqrteq_f32(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned reciprocal square root estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ursqrte) )] #[cfg_attr( not(target_arch = "arm"), @@ -53963,19 +52645,26 @@ pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t { - unsafe { transmute(a) } +pub fn vrsqrte_u32(a: uint32x2_t) -> uint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ursqrte.v2i32" + )] + fn _vrsqrte_u32(a: uint32x2_t) -> uint32x2_t; + } + unsafe { _vrsqrte_u32(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned reciprocal square root estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ursqrte) )] #[cfg_attr( not(target_arch = "arm"), @@ -53985,71 +52674,86 @@ pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ursqrte.v4i32" + )] + fn _vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t; } + unsafe { _vrsqrteq_u32(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Floating-point reciprocal square root step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(frsqrts) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t { - unsafe { transmute(a) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v4f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frsqrts.v4f16" + )] + fn _vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { _vrsqrts_f16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Floating-point reciprocal square root step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(frsqrts) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +#[cfg(not(target_arch = "arm64ec"))] +pub fn vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v8f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frsqrts.v8f16" + )] + fn _vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; } + unsafe { _vrsqrtsq_f16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Floating-point reciprocal square root step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(frsqrts) )] #[cfg_attr( not(target_arch = "arm"), @@ -54059,19 +52763,26 @@ pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t { - unsafe { transmute(a) } +pub fn vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frsqrts.v2f32" + )] + fn _vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + unsafe { _vrsqrts_f32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Floating-point reciprocal square root step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(frsqrts) )] #[cfg_attr( not(target_arch = "arm"), @@ -54081,24 +52792,28 @@ pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frsqrts.v4f32" + )] + fn _vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; } + unsafe { _vrsqrtsq_f32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srsra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54107,20 +52822,21 @@ pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t { - unsafe { transmute(a) } +pub fn vrsra_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + static_assert!(N >= 1 && N <= 8); + unsafe { simd_add(a, vrshr_n_s8::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srsra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54129,24 +52845,21 @@ pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vrsraq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + static_assert!(N >= 1 && N <= 8); + unsafe { simd_add(a, vrshrq_n_s8::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srsra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54155,20 +52868,21 @@ pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t { - unsafe { transmute(a) } +pub fn vrsra_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + static_assert!(N >= 1 && N <= 16); + unsafe { simd_add(a, vrshr_n_s16::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srsra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54177,24 +52891,21 @@ pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vrsraq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + static_assert!(N >= 1 && N <= 16); + unsafe { simd_add(a, vrshrq_n_s16::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srsra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54203,20 +52914,21 @@ pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t { - unsafe { transmute(a) } +pub fn vrsra_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + static_assert!(N >= 1 && N <= 32); + unsafe { simd_add(a, vrshr_n_s32::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srsra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54225,21 +52937,21 @@ pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vrsraq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + static_assert!(N >= 1 && N <= 32); + unsafe { simd_add(a, vrshrq_n_s32::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srsra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54248,20 +52960,21 @@ pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t { - unsafe { transmute(a) } +pub fn vrsra_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + static_assert!(N >= 1 && N <= 64); + unsafe { simd_add(a, vrshr_n_s64::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(srsra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54270,24 +52983,21 @@ pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vrsraq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + static_assert!(N >= 1 && N <= 64); + unsafe { simd_add(a, vrshrq_n_s64::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ursra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54296,20 +53006,21 @@ pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t { - unsafe { transmute(a) } +pub fn vrsra_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); + unsafe { simd_add(a, vrshr_n_u8::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ursra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54318,24 +53029,21 @@ pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vrsraq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + static_assert!(N >= 1 && N <= 8); + unsafe { simd_add(a, vrshrq_n_u8::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ursra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54344,20 +53052,21 @@ pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t { - unsafe { transmute(a) } +pub fn vrsra_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + unsafe { simd_add(a, vrshr_n_u16::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ursra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54366,24 +53075,21 @@ pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vrsraq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + static_assert!(N >= 1 && N <= 16); + unsafe { simd_add(a, vrshrq_n_u16::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ursra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54392,20 +53098,21 @@ pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t { - unsafe { transmute(a) } +pub fn vrsra_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + unsafe { simd_add(a, vrshr_n_u32::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ursra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54414,21 +53121,21 @@ pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vrsraq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + static_assert!(N >= 1 && N <= 32); + unsafe { simd_add(a, vrshrq_n_u32::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ursra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54437,20 +53144,21 @@ pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t { - unsafe { transmute(a) } +pub fn vrsra_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + static_assert!(N >= 1 && N <= 64); + unsafe { simd_add(a, vrshr_n_u64::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ursra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54459,23 +53167,19 @@ pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vrsraq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + static_assert!(N >= 1 && N <= 64); + unsafe { simd_add(a, vrshrq_n_u64::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rsubhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -54485,19 +53189,26 @@ pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t { - unsafe { transmute(a) } +pub fn vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.rsubhn.v8i8" + )] + fn _vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t; + } + unsafe { _vrsubhn_s16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rsubhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -54507,24 +53218,26 @@ pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.rsubhn.v4i16" + )] + fn _vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t; } + unsafe { _vrsubhn_s32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rsubhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -54534,19 +53247,26 @@ pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t { - unsafe { transmute(a) } +pub fn vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.rsubhn.v2i32" + )] + fn _vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t; + } + unsafe { _vrsubhn_s64(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rsubhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -54556,28 +53276,18 @@ pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { + unsafe { transmute(vrsubhn_s16(transmute(a), transmute(b))) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rsubhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -54587,19 +53297,18 @@ pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t { - unsafe { transmute(a) } +pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { + unsafe { transmute(vrsubhn_s32(transmute(a), transmute(b))) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rsubhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -54609,74 +53318,101 @@ pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { + unsafe { transmute(vrsubhn_s64(transmute(a), transmute(b))) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f16)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(nop, LANE = 0) )] -pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t { - unsafe { transmute(a) } +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vset_lane_f16(a: f16, b: float16x4_t) -> float16x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f16)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vset_lane_f16(a: f16, b: float16x4_t) -> float16x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f16)"] +#[inline] +#[cfg(target_endian = "little")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vsetq_lane_f16(a: f16, b: float16x8_t) -> float16x8_t { + static_assert_uimm_bits!(LANE, 3); + unsafe { simd_insert!(b, LANE as u32, a) } +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) )] -pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vsetq_lane_f16(a: f16, b: float16x8_t) -> float16x8_t { + static_assert_uimm_bits!(LANE, 3); unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54685,20 +53421,22 @@ pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t { - unsafe { transmute(a) } +pub fn vset_lane_f32(a: f32, b: float32x2_t) -> float32x2_t { + static_assert_uimm_bits!(LANE, 1); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54707,25 +53445,26 @@ pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vset_lane_f32(a: f32, b: float32x2_t) -> float32x2_t { + static_assert_uimm_bits!(LANE, 1); unsafe { - let ret_val: int64x2_t = transmute(a); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = simd_insert!(b, LANE as u32, a); simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54734,20 +53473,22 @@ pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t { - unsafe { transmute(a) } +pub fn vsetq_lane_f32(a: f32, b: float32x4_t) -> float32x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54756,29 +53497,26 @@ pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vsetq_lane_f32(a: f32, b: float32x4_t) -> float32x4_t { + static_assert_uimm_bits!(LANE, 2); unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54787,20 +53525,22 @@ pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t { - unsafe { transmute(a) } +pub fn vset_lane_s8(a: i8, b: int8x8_t) -> int8x8_t { + static_assert_uimm_bits!(LANE, 3); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54809,25 +53549,26 @@ pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vset_lane_s8(a: i8, b: int8x8_t) -> int8x8_t { + static_assert_uimm_bits!(LANE, 3); unsafe { - let ret_val: uint16x8_t = transmute(a); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_insert!(b, LANE as u32, a); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54836,20 +53577,22 @@ pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t { - unsafe { transmute(a) } +pub fn vsetq_lane_s8(a: i8, b: int8x16_t) -> int8x16_t { + static_assert_uimm_bits!(LANE, 4); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54858,25 +53601,31 @@ pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vsetq_lane_s8(a: i8, b: int8x16_t) -> int8x16_t { + static_assert_uimm_bits!(LANE, 4); unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54885,20 +53634,22 @@ pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t { - unsafe { transmute(a) } +pub fn vset_lane_s16(a: i16, b: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54907,25 +53658,26 @@ pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vset_lane_s16(a: i16, b: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(LANE, 2); unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x4_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54934,20 +53686,22 @@ pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t { - unsafe { transmute(a) } +pub fn vsetq_lane_s16(a: i16, b: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(LANE, 3); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54956,25 +53710,26 @@ pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vsetq_lane_s16(a: i16, b: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(LANE, 3); unsafe { - let ret_val: poly16x8_t = transmute(a); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = simd_insert!(b, LANE as u32, a); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -54983,20 +53738,22 @@ pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t { - unsafe { transmute(a) } +pub fn vset_lane_s32(a: i32, b: int32x2_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55005,24 +53762,26 @@ pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vset_lane_s32(a: i32, b: int32x2_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); unsafe { - let ret_val: float32x2_t = transmute(a); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x2_t = simd_insert!(b, LANE as u32, a); simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55031,20 +53790,22 @@ pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t { - unsafe { transmute(a) } +pub fn vsetq_lane_s32(a: i32, b: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55053,24 +53814,26 @@ pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vsetq_lane_s32(a: i32, b: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int32x4_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s64)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55079,20 +53842,22 @@ pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t { - unsafe { transmute(a) } +pub fn vsetq_lane_s64(a: i64, b: int64x2_t) -> int64x2_t { + static_assert_uimm_bits!(LANE, 1); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s64)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55101,24 +53866,26 @@ pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vsetq_lane_s64(a: i64, b: int64x2_t) -> int64x2_t { + static_assert_uimm_bits!(LANE, 1); unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let b: int64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int64x2_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55127,20 +53894,22 @@ pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t { - unsafe { transmute(a) } +pub fn vset_lane_u8(a: u8, b: uint8x8_t) -> uint8x8_t { + static_assert_uimm_bits!(LANE, 3); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55149,24 +53918,26 @@ pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vset_lane_u8(a: u8, b: uint8x8_t) -> uint8x8_t { + static_assert_uimm_bits!(LANE, 3); unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55175,20 +53946,22 @@ pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t { - unsafe { transmute(a) } +pub fn vsetq_lane_u8(a: u8, b: uint8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(LANE, 4); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55197,21 +53970,31 @@ pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vsetq_lane_u8(a: u8, b: uint8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(LANE, 4); + unsafe { + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55220,20 +54003,22 @@ pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t { - unsafe { transmute(a) } +pub fn vset_lane_u16(a: u16, b: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55242,24 +54027,26 @@ pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vset_lane_u16(a: u16, b: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(LANE, 2); unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55268,20 +54055,22 @@ pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t { - unsafe { transmute(a) } +pub fn vsetq_lane_u16(a: u16, b: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(LANE, 3); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55290,24 +54079,26 @@ pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vsetq_lane_u16(a: u16, b: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(LANE, 3); unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55316,20 +54107,22 @@ pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t { - unsafe { transmute(a) } +pub fn vset_lane_u32(a: u32, b: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 1); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55338,24 +54131,26 @@ pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vset_lane_u32(a: u32, b: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 1); unsafe { - let ret_val: uint32x2_t = transmute(a); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint32x2_t = simd_insert!(b, LANE as u32, a); simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55364,20 +54159,22 @@ pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t { - unsafe { transmute(a) } +pub fn vsetq_lane_u32(a: u32, b: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55386,21 +54183,26 @@ pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vsetq_lane_u32(a: u32, b: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u64)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55409,20 +54211,22 @@ pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t { - unsafe { transmute(a) } +pub fn vsetq_lane_u64(a: u64, b: uint64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 1); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u64)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55431,24 +54235,26 @@ pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vsetq_lane_u64(a: u64, b: uint64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 1); unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint64x2_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55457,20 +54263,22 @@ pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t { - unsafe { transmute(a) } +pub fn vset_lane_p8(a: p8, b: poly8x8_t) -> poly8x8_t { + static_assert_uimm_bits!(LANE, 3); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55479,24 +54287,26 @@ pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vset_lane_p8(a: p8, b: poly8x8_t) -> poly8x8_t { + static_assert_uimm_bits!(LANE, 3); unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55505,20 +54315,22 @@ pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t { - unsafe { transmute(a) } +pub fn vsetq_lane_p8(a: p8, b: poly8x16_t) -> poly8x16_t { + static_assert_uimm_bits!(LANE, 4); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55527,10 +54339,12 @@ pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vsetq_lane_p8(a: p8, b: poly8x16_t) -> poly8x16_t { + static_assert_uimm_bits!(LANE, 4); unsafe { - let ret_val: int8x16_t = transmute(a); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = simd_insert!(b, LANE as u32, a); simd_shuffle!( ret_val, ret_val, @@ -55538,17 +54352,18 @@ pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t { ) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55557,20 +54372,22 @@ pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t { - unsafe { transmute(a) } +pub fn vset_lane_p16(a: p16, b: poly16x4_t) -> poly16x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55579,24 +54396,26 @@ pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vset_lane_p16(a: p16, b: poly16x4_t) -> poly16x4_t { + static_assert_uimm_bits!(LANE, 2); unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55605,20 +54424,22 @@ pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t { - unsafe { transmute(a) } +pub fn vsetq_lane_p16(a: p16, b: poly16x8_t) -> poly16x8_t { + static_assert_uimm_bits!(LANE, 3); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55627,46 +54448,25 @@ pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vsetq_lane_p16(a: p16, b: poly16x8_t) -> poly16x8_t { + static_assert_uimm_bits!(LANE, 3); unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p64)"] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55675,24 +54475,21 @@ pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vset_lane_p64(a: p64, b: poly64x1_t) -> poly64x1_t { + static_assert!(LANE == 0); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55701,20 +54498,21 @@ pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t { - unsafe { transmute(a) } +pub fn vset_lane_s64(a: i64, b: int64x1_t) -> int64x1_t { + static_assert!(LANE == 0); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55723,28 +54521,22 @@ pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vset_lane_u64(a: u64, b: uint64x1_t) -> uint64x1_t { + static_assert!(LANE == 0); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p64)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55753,20 +54545,22 @@ pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t { - unsafe { transmute(a) } +pub fn vsetq_lane_p64(a: p64, b: poly64x2_t) -> poly64x2_t { + static_assert_uimm_bits!(LANE, 1); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p64)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -55775,509 +54569,809 @@ pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vsetq_lane_p64(a: p64, b: poly64x2_t) -> poly64x2_t { + static_assert_uimm_bits!(LANE, 1); unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: poly64x2_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"] -#[inline(always)] +#[doc = "SHA1 hash update accelerator, choose."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1cq_u32)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "sha2")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(test, assert_instr(sha1c))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t { - unsafe { transmute(a) } +pub fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha1c" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1c")] + fn _vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t; + } + unsafe { _vsha1cq_u32(hash_abcd, hash_e, wk) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"] -#[inline(always)] +#[doc = "SHA1 hash update accelerator, choose."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1cq_u32)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "sha2")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(test, assert_instr(sha1c))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha1c" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1c")] + fn _vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t; + } unsafe { - let ret_val: uint32x4_t = transmute(a); + let hash_abcd: uint32x4_t = simd_shuffle!(hash_abcd, hash_abcd, [3, 2, 1, 0]); + let wk: uint32x4_t = simd_shuffle!(wk, wk, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsha1cq_u32(hash_abcd, hash_e, wk); simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] +#[doc = "SHA1 fixed rotate."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1h_u32)"] +#[inline] +#[target_feature(enable = "sha2")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(test, assert_instr(sha1h))] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vsha1h_u32(hash_e: u32) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha1h" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1h")] + fn _vsha1h_u32(hash_e: u32) -> u32; } + unsafe { _vsha1h_u32(hash_e) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"] -#[inline(always)] +#[doc = "SHA1 hash update accelerator, majority"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1mq_u32)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "sha2")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(test, assert_instr(sha1m))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t { - unsafe { transmute(a) } +pub fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha1m" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1m")] + fn _vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t; + } + unsafe { _vsha1mq_u32(hash_abcd, hash_e, wk) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"] -#[inline(always)] +#[doc = "SHA1 hash update accelerator, majority"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1mq_u32)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "sha2")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(test, assert_instr(sha1m))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha1m" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1m")] + fn _vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t; + } unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + let hash_abcd: uint32x4_t = simd_shuffle!(hash_abcd, hash_abcd, [3, 2, 1, 0]); + let wk: uint32x4_t = simd_shuffle!(wk, wk, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsha1mq_u32(hash_abcd, hash_e, wk); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"] -#[inline(always)] +#[doc = "SHA1 hash update accelerator, parity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1pq_u32)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(test, assert_instr(sha1p))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t { - unsafe { transmute(a) } +pub fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha1p" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1p")] + fn _vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t; + } + unsafe { _vsha1pq_u32(hash_abcd, hash_e, wk) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"] -#[inline(always)] +#[doc = "SHA1 hash update accelerator, parity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1pq_u32)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(test, assert_instr(sha1p))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t { +pub fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha1p" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1p")] + fn _vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t; + } unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + let hash_abcd: uint32x4_t = simd_shuffle!(hash_abcd, hash_abcd, [3, 2, 1, 0]); + let wk: uint32x4_t = simd_shuffle!(wk, wk, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsha1pq_u32(hash_abcd, hash_e, wk); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"] -#[inline(always)] +#[doc = "SHA1 schedule update accelerator, first part."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su0q_u32)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(test, assert_instr(sha1su0))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t { - unsafe { transmute(a) } +pub fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha1su0" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su0")] + fn _vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t; + } + unsafe { _vsha1su0q_u32(w0_3, w4_7, w8_11) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"] -#[inline(always)] +#[doc = "SHA1 schedule update accelerator, first part."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su0q_u32)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(test, assert_instr(sha1su0))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t { +pub fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha1su0" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su0")] + fn _vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t; + } unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let w0_3: uint32x4_t = simd_shuffle!(w0_3, w0_3, [3, 2, 1, 0]); + let w4_7: uint32x4_t = simd_shuffle!(w4_7, w4_7, [3, 2, 1, 0]); + let w8_11: uint32x4_t = simd_shuffle!(w8_11, w8_11, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsha1su0q_u32(w0_3, w4_7, w8_11); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"] -#[inline(always)] +#[doc = "SHA1 schedule update accelerator, second part."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su1q_u32)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(test, assert_instr(sha1su1))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t { - unsafe { transmute(a) } +pub fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha1su1" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su1")] + fn _vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t; + } + unsafe { _vsha1su1q_u32(tw0_3, w12_15) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"] -#[inline(always)] +#[doc = "SHA1 schedule update accelerator, second part."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su1q_u32)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(test, assert_instr(sha1su1))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t { +pub fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha1su1" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su1")] + fn _vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t; + } unsafe { - let ret_val: int32x4_t = transmute(a); + let tw0_3: uint32x4_t = simd_shuffle!(tw0_3, tw0_3, [3, 2, 1, 0]); + let w12_15: uint32x4_t = simd_shuffle!(w12_15, w12_15, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsha1su1q_u32(tw0_3, w12_15); simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"] -#[inline(always)] +#[doc = "SHA1 schedule update accelerator, upper part."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256h2q_u32)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(test, assert_instr(sha256h2))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t { - unsafe { transmute(a) } +pub fn vsha256h2q_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha256h2" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h2")] + fn _vsha256h2q_u32( + hash_abcd: uint32x4_t, + hash_efgh: uint32x4_t, + wk: uint32x4_t, + ) -> uint32x4_t; + } + unsafe { _vsha256h2q_u32(hash_abcd, hash_efgh, wk) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"] -#[inline(always)] +#[doc = "SHA1 schedule update accelerator, upper part."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256h2q_u32)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(test, assert_instr(sha256h2))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t { +pub fn vsha256h2q_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha256h2" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h2")] + fn _vsha256h2q_u32( + hash_abcd: uint32x4_t, + hash_efgh: uint32x4_t, + wk: uint32x4_t, + ) -> uint32x4_t; + } unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + let hash_abcd: uint32x4_t = simd_shuffle!(hash_abcd, hash_abcd, [3, 2, 1, 0]); + let hash_efgh: uint32x4_t = simd_shuffle!(hash_efgh, hash_efgh, [3, 2, 1, 0]); + let wk: uint32x4_t = simd_shuffle!(wk, wk, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsha256h2q_u32(hash_abcd, hash_efgh, wk); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"] -#[inline(always)] +#[doc = "SHA1 schedule update accelerator, first part."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256hq_u32)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(test, assert_instr(sha256h))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t { - unsafe { transmute(a) } +pub fn vsha256hq_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha256h" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h")] + fn _vsha256hq_u32( + hash_abcd: uint32x4_t, + hash_efgh: uint32x4_t, + wk: uint32x4_t, + ) -> uint32x4_t; + } + unsafe { _vsha256hq_u32(hash_abcd, hash_efgh, wk) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"] -#[inline(always)] +#[doc = "SHA1 schedule update accelerator, first part."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256hq_u32)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(test, assert_instr(sha256h))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t { +pub fn vsha256hq_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha256h" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h")] + fn _vsha256hq_u32( + hash_abcd: uint32x4_t, + hash_efgh: uint32x4_t, + wk: uint32x4_t, + ) -> uint32x4_t; + } unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + let hash_abcd: uint32x4_t = simd_shuffle!(hash_abcd, hash_abcd, [3, 2, 1, 0]); + let hash_efgh: uint32x4_t = simd_shuffle!(hash_efgh, hash_efgh, [3, 2, 1, 0]); + let wk: uint32x4_t = simd_shuffle!(wk, wk, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsha256hq_u32(hash_abcd, hash_efgh, wk); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"] -#[inline(always)] +#[doc = "SHA256 schedule update accelerator, first part."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su0q_u32)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(test, assert_instr(sha256su0))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t { - unsafe { transmute(a) } +pub fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha256su0" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su0")] + fn _vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t; + } + unsafe { _vsha256su0q_u32(w0_3, w4_7) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"] -#[inline(always)] +#[doc = "SHA256 schedule update accelerator, first part."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su0q_u32)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(test, assert_instr(sha256su0))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] +pub fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha256su0" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su0")] + fn _vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t; + } + unsafe { + let w0_3: uint32x4_t = simd_shuffle!(w0_3, w0_3, [3, 2, 1, 0]); + let w4_7: uint32x4_t = simd_shuffle!(w4_7, w4_7, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsha256su0q_u32(w0_3, w4_7); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "SHA256 schedule update accelerator, second part."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su1q_u32)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "sha2")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(test, assert_instr(sha256su1))] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t { - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t { - unsafe { transmute(a) } +pub fn vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha256su1" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su1")] + fn _vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t) + -> uint32x4_t; + } + unsafe { _vsha256su1q_u32(tw0_3, w8_11, w12_15) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"] -#[inline(always)] +#[doc = "SHA256 schedule update accelerator, second part."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su1q_u32)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(test, assert_instr(sha256su1))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t { +pub fn vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha256su1" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su1")] + fn _vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t) + -> uint32x4_t; + } unsafe { - let ret_val: uint32x4_t = transmute(a); + let tw0_3: uint32x4_t = simd_shuffle!(tw0_3, tw0_3, [3, 2, 1, 0]); + let w8_11: uint32x4_t = simd_shuffle!(w8_11, w8_11, [3, 2, 1, 0]); + let w12_15: uint32x4_t = simd_shuffle!(w12_15, w12_15, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsha256su1q_u32(tw0_3, w8_11, w12_15); simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[rustc_legacy_const_generics(2)] +fn vshiftlins_v16i8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v16i8")] + fn _vshiftlins_v16i8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t; + } + unsafe { _vshiftlins_v16i8(a, b, const { int8x16_t([N as i8; 16]) }) } +} +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[rustc_legacy_const_generics(2)] +fn vshiftlins_v1i64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v1i64")] + fn _vshiftlins_v1i64(a: int64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t; + } + unsafe { _vshiftlins_v1i64(a, b, const { int64x1_t([N as i64; 1]) }) } +} +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[rustc_legacy_const_generics(2)] +fn vshiftlins_v2i32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i32")] + fn _vshiftlins_v2i32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t; + } + unsafe { _vshiftlins_v2i32(a, b, const { int32x2_t([N; 2]) }) } +} +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[rustc_legacy_const_generics(2)] +fn vshiftlins_v2i64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i64")] + fn _vshiftlins_v2i64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t; + } + unsafe { _vshiftlins_v2i64(a, b, const { int64x2_t([N as i64; 2]) }) } +} +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[rustc_legacy_const_generics(2)] +fn vshiftlins_v4i16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i16")] + fn _vshiftlins_v4i16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t; + } + unsafe { _vshiftlins_v4i16(a, b, const { int16x4_t([N as i16; 4]) }) } +} +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[rustc_legacy_const_generics(2)] +fn vshiftlins_v4i32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i32")] + fn _vshiftlins_v4i32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t; + } + unsafe { _vshiftlins_v4i32(a, b, const { int32x4_t([N; 4]) }) } +} +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[rustc_legacy_const_generics(2)] +fn vshiftlins_v8i16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i16")] + fn _vshiftlins_v8i16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t; + } + unsafe { _vshiftlins_v8i16(a, b, const { int16x8_t([N as i16; 8]) }) } +} +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[rustc_legacy_const_generics(2)] +fn vshiftlins_v8i8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i8")] + fn _vshiftlins_v8i8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t; + } + unsafe { _vshiftlins_v8i8(a, b, const { int8x8_t([N as i8; 8]) }) } +} +#[doc = "Shift Right and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v16i8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[rustc_legacy_const_generics(2)] +fn vshiftrins_v16i8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v16i8")] + fn _vshiftrins_v16i8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t; + } + unsafe { _vshiftrins_v16i8(a, b, const { int8x16_t([-N as i8; 16]) }) } +} +#[doc = "Shift Right and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v1i64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[rustc_legacy_const_generics(2)] +fn vshiftrins_v1i64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v1i64")] + fn _vshiftrins_v1i64(a: int64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t; + } + unsafe { _vshiftrins_v1i64(a, b, const { int64x1_t([-N as i64; 1]) }) } +} +#[doc = "Shift Right and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v2i32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[rustc_legacy_const_generics(2)] +fn vshiftrins_v2i32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i32")] + fn _vshiftrins_v2i32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t; + } + unsafe { _vshiftrins_v2i32(a, b, const { int32x2_t([-N; 2]) }) } +} +#[doc = "Shift Right and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v2i64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[rustc_legacy_const_generics(2)] +fn vshiftrins_v2i64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i64")] + fn _vshiftrins_v2i64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t; + } + unsafe { _vshiftrins_v2i64(a, b, const { int64x2_t([-N as i64; 2]) }) } +} +#[doc = "Shift Right and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v4i16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[rustc_legacy_const_generics(2)] +fn vshiftrins_v4i16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i16")] + fn _vshiftrins_v4i16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t; + } + unsafe { _vshiftrins_v4i16(a, b, const { int16x4_t([-N as i16; 4]) }) } +} +#[doc = "Shift Right and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v4i32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[rustc_legacy_const_generics(2)] +fn vshiftrins_v4i32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i32")] + fn _vshiftrins_v4i32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t; + } + unsafe { _vshiftrins_v4i32(a, b, const { int32x4_t([-N; 4]) }) } +} +#[doc = "Shift Right and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v8i16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[rustc_legacy_const_generics(2)] +fn vshiftrins_v8i16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i16")] + fn _vshiftrins_v8i16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t; + } + unsafe { _vshiftrins_v8i16(a, b, const { int16x8_t([-N as i16; 8]) }) } +} +#[doc = "Shift Right and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v8i8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[rustc_legacy_const_generics(2)] +fn vshiftrins_v8i8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i8")] + fn _vshiftrins_v8i8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t; + } + unsafe { _vshiftrins_v8i8(a, b, const { int8x8_t([-N as i8; 8]) }) } +} +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(shl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -56286,20 +55380,21 @@ pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t { - unsafe { transmute(a) } +pub fn vshl_n_s8(a: int8x8_t) -> int8x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shl(a, vdup_n_s8(N as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(shl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -56308,23 +55403,21 @@ pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t { - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vshlq_n_s8(a: int8x16_t) -> int8x16_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shl(a, vdupq_n_s8(N as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(shl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -56333,20 +55426,21 @@ pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t { - unsafe { transmute(a) } +pub fn vshl_n_s16(a: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(N, 4); + unsafe { simd_shl(a, vdup_n_s16(N as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(shl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -56355,27 +55449,21 @@ pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t { - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vshlq_n_s16(a: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(N, 4); + unsafe { simd_shl(a, vdupq_n_s16(N as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(shl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -56384,20 +55472,21 @@ pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t { - unsafe { transmute(a) } +pub fn vshl_n_s32(a: int32x2_t) -> int32x2_t { + static_assert_uimm_bits!(N, 5); + unsafe { simd_shl(a, vdup_n_s32(N as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(shl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -56406,23 +55495,21 @@ pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t { - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vshlq_n_s32(a: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(N, 5); + unsafe { simd_shl(a, vdupq_n_s32(N as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(shl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -56431,20 +55518,21 @@ pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t { - unsafe { transmute(a) } +pub fn vshl_n_s64(a: int64x1_t) -> int64x1_t { + static_assert_uimm_bits!(N, 6); + unsafe { simd_shl(a, vdup_n_s64(N as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(shl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -56453,23 +55541,21 @@ pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t { - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vshlq_n_s64(a: int64x2_t) -> int64x2_t { + static_assert_uimm_bits!(N, 6); + unsafe { simd_shl(a, vdupq_n_s64(N as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(shl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -56478,20 +55564,21 @@ pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t { - unsafe { transmute(a) } +pub fn vshl_n_u8(a: uint8x8_t) -> uint8x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shl(a, vdup_n_u8(N as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(shl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -56500,21 +55587,21 @@ pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vshlq_n_u8(a: uint8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shl(a, vdupq_n_u8(N as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(shl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -56523,20 +55610,21 @@ pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 { - unsafe { transmute(a) } +pub fn vshl_n_u16(a: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(N, 4); + unsafe { simd_shl(a, vdup_n_u16(N as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(shl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -56545,22 +55633,21 @@ pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vshlq_n_u16(a: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(N, 4); + unsafe { simd_shl(a, vdupq_n_u16(N as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(shl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -56569,20 +55656,21 @@ pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t { - unsafe { transmute(a) } +pub fn vshl_n_u32(a: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(N, 5); + unsafe { simd_shl(a, vdup_n_u32(N as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(shl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -56591,25 +55679,21 @@ pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vshlq_n_u32(a: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(N, 5); + unsafe { simd_shl(a, vdupq_n_u32(N as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(shl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -56618,20 +55702,21 @@ pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t { - unsafe { transmute(a) } +pub fn vshl_n_u64(a: uint64x1_t) -> uint64x1_t { + static_assert_uimm_bits!(N, 6); + unsafe { simd_shl(a, vdup_n_u64(N as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(shl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -56640,20 +55725,19 @@ pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vshlq_n_u64(a: uint64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(N, 6); + unsafe { simd_shl(a, vdupq_n_u64(N as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Signed Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -56663,19 +55747,26 @@ pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 { - unsafe { transmute(a) } +pub fn vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sshl.v8i8" + )] + fn _vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + unsafe { _vshl_s8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Signed Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -56685,20 +55776,26 @@ pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sshl.v16i8" + )] + fn _vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + } + unsafe { _vshlq_s8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Signed Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -56708,19 +55805,26 @@ pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t { - unsafe { transmute(a) } +pub fn vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sshl.v4i16" + )] + fn _vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + unsafe { _vshl_s16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Signed Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -56730,23 +55834,26 @@ pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sshl.v8i16" + )] + fn _vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } + unsafe { _vshlq_s16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Signed Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -56756,19 +55863,26 @@ pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t { - unsafe { transmute(a) } +pub fn vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sshl.v2i32" + )] + fn _vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + unsafe { _vshl_s32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Signed Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -56778,20 +55892,26 @@ pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { transmute(a) } +pub fn vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sshl.v4i32" + )] + fn _vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + unsafe { _vshlq_s32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Signed Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -56801,19 +55921,26 @@ pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 { - unsafe { transmute(a) } +pub fn vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v1i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sshl.v1i64" + )] + fn _vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t; + } + unsafe { _vshl_s64(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Signed Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -56823,20 +55950,26 @@ pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v2i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sshl.v2i64" + )] + fn _vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; + } + unsafe { _vshlq_s64(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Unsigned Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ushl) )] #[cfg_attr( not(target_arch = "arm"), @@ -56846,19 +55979,26 @@ pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t { - unsafe { transmute(a) } +pub fn vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ushl.v8i8" + )] + fn _vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t; + } + unsafe { _vshl_u8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Unsigned Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ushl) )] #[cfg_attr( not(target_arch = "arm"), @@ -56868,23 +56008,26 @@ pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ushl.v16i8" + )] + fn _vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t; } + unsafe { _vshlq_u8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Unsigned Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ushl) )] #[cfg_attr( not(target_arch = "arm"), @@ -56894,19 +56037,26 @@ pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 { - unsafe { transmute(a) } +pub fn vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ushl.v4i16" + )] + fn _vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t; + } + unsafe { _vshl_u16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Unsigned Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ushl) )] #[cfg_attr( not(target_arch = "arm"), @@ -56916,20 +56066,26 @@ pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { transmute(a) } +pub fn vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ushl.v8i16" + )] + fn _vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t; + } + unsafe { _vshlq_u16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Unsigned Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ushl) )] #[cfg_attr( not(target_arch = "arm"), @@ -56939,19 +56095,26 @@ pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t { - unsafe { transmute(a) } +pub fn vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ushl.v2i32" + )] + fn _vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t; + } + unsafe { _vshl_u32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Unsigned Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ushl) )] #[cfg_attr( not(target_arch = "arm"), @@ -56961,20 +56124,26 @@ pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ushl.v4i32" + )] + fn _vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t; + } + unsafe { _vshlq_u32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Unsigned Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ushl) )] #[cfg_attr( not(target_arch = "arm"), @@ -56984,19 +56153,26 @@ pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 { - unsafe { transmute(a) } +pub fn vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v1i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ushl.v1i64" + )] + fn _vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t; + } + unsafe { _vshl_u64(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Unsigned Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ushl) )] #[cfg_attr( not(target_arch = "arm"), @@ -57006,22 +56182,28 @@ pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v2i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ushl.v2i64" + )] + fn _vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t; + } + unsafe { _vshlq_u64(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Signed shift left long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sshll, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57030,20 +56212,21 @@ pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t { - unsafe { transmute(a) } +pub fn vshll_n_s16(a: int16x4_t) -> int32x4_t { + static_assert!(N >= 0 && N <= 16); + unsafe { simd_shl(simd_cast(a), vdupq_n_s32(N as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Signed shift left long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sshll, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57052,25 +56235,21 @@ pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vshll_n_s32(a: int32x2_t) -> int64x2_t { + static_assert!(N >= 0 && N <= 32); + unsafe { simd_shl(simd_cast(a), vdupq_n_s64(N as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Signed shift left long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s8", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sshll, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57079,20 +56258,21 @@ pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t { - unsafe { transmute(a) } +pub fn vshll_n_s8(a: int8x8_t) -> int16x8_t { + static_assert!(N >= 0 && N <= 8); + unsafe { simd_shl(simd_cast(a), vdupq_n_s16(N as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Signed shift left long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ushll, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57101,21 +56281,21 @@ pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vshll_n_u16(a: uint16x4_t) -> uint32x4_t { + static_assert!(N >= 0 && N <= 16); + unsafe { simd_shl(simd_cast(a), vdupq_n_u32(N as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Signed shift left long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ushll, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57124,20 +56304,21 @@ pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 { - unsafe { transmute(a) } +pub fn vshll_n_u32(a: uint32x2_t) -> uint64x2_t { + static_assert!(N >= 0 && N <= 32); + unsafe { simd_shl(simd_cast(a), vdupq_n_u64(N as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Signed shift left long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u8", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ushll, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57146,21 +56327,21 @@ pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vshll_n_u8(a: uint8x8_t) -> uint16x8_t { + static_assert!(N >= 0 && N <= 8); + unsafe { simd_shl(simd_cast(a), vdupq_n_u16(N as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57169,20 +56350,22 @@ pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t { - unsafe { transmute(a) } +pub fn vshr_n_s8(a: int8x8_t) -> int8x8_t { + static_assert!(N >= 1 && N <= 8); + let n: i32 = if N == 8 { 7 } else { N }; + unsafe { simd_shr(a, vdup_n_s8(n as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57191,24 +56374,22 @@ pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vshrq_n_s8(a: int8x16_t) -> int8x16_t { + static_assert!(N >= 1 && N <= 8); + let n: i32 = if N == 8 { 7 } else { N }; + unsafe { simd_shr(a, vdupq_n_s8(n as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57217,20 +56398,22 @@ pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t { - unsafe { transmute(a) } +pub fn vshr_n_s16(a: int16x4_t) -> int16x4_t { + static_assert!(N >= 1 && N <= 16); + let n: i32 = if N == 16 { 15 } else { N }; + unsafe { simd_shr(a, vdup_n_s16(n as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57239,21 +56422,22 @@ pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { transmute(a) } +pub fn vshrq_n_s16(a: int16x8_t) -> int16x8_t { + static_assert!(N >= 1 && N <= 16); + let n: i32 = if N == 16 { 15 } else { N }; + unsafe { simd_shr(a, vdupq_n_s16(n as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57262,20 +56446,22 @@ pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 { - unsafe { transmute(a) } +pub fn vshr_n_s32(a: int32x2_t) -> int32x2_t { + static_assert!(N >= 1 && N <= 32); + let n: i32 = if N == 32 { 31 } else { N }; + unsafe { simd_shr(a, vdup_n_s32(n as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57284,21 +56470,22 @@ pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vshrq_n_s32(a: int32x4_t) -> int32x4_t { + static_assert!(N >= 1 && N <= 32); + let n: i32 = if N == 32 { 31 } else { N }; + unsafe { simd_shr(a, vdupq_n_s32(n as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57307,20 +56494,22 @@ pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t { - unsafe { transmute(a) } +pub fn vshr_n_s64(a: int64x1_t) -> int64x1_t { + static_assert!(N >= 1 && N <= 64); + let n: i32 = if N == 64 { 63 } else { N }; + unsafe { simd_shr(a, vdup_n_s64(n as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sshr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57329,24 +56518,22 @@ pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vshrq_n_s64(a: int64x2_t) -> int64x2_t { + static_assert!(N >= 1 && N <= 64); + let n: i32 = if N == 64 { 63 } else { N }; + unsafe { simd_shr(a, vdupq_n_s64(n as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ushr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57355,20 +56542,26 @@ pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 { - unsafe { transmute(a) } +pub fn vshr_n_u8(a: uint8x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); + let n: i32 = if N == 8 { + return vdup_n_u8(0); + } else { + N + }; + unsafe { simd_shr(a, vdup_n_u8(n as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ushr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57377,21 +56570,26 @@ pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { transmute(a) } +pub fn vshrq_n_u8(a: uint8x16_t) -> uint8x16_t { + static_assert!(N >= 1 && N <= 8); + let n: i32 = if N == 8 { + return vdupq_n_u8(0); + } else { + N + }; + unsafe { simd_shr(a, vdupq_n_u8(n as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ushr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57400,20 +56598,26 @@ pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t { - unsafe { transmute(a) } +pub fn vshr_n_u16(a: uint16x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + let n: i32 = if N == 16 { + return vdup_n_u16(0); + } else { + N + }; + unsafe { simd_shr(a, vdup_n_u16(n as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ushr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57422,21 +56626,26 @@ pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vshrq_n_u16(a: uint16x8_t) -> uint16x8_t { + static_assert!(N >= 1 && N <= 16); + let n: i32 = if N == 16 { + return vdupq_n_u16(0); + } else { + N + }; + unsafe { simd_shr(a, vdupq_n_u16(n as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ushr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57445,20 +56654,26 @@ pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 { - unsafe { transmute(a) } +pub fn vshr_n_u32(a: uint32x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + let n: i32 = if N == 32 { + return vdup_n_u32(0); + } else { + N + }; + unsafe { simd_shr(a, vdup_n_u32(n as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ushr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57467,22 +56682,26 @@ pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vshrq_n_u32(a: uint32x4_t) -> uint32x4_t { + static_assert!(N >= 1 && N <= 32); + let n: i32 = if N == 32 { + return vdupq_n_u32(0); + } else { + N + }; + unsafe { simd_shr(a, vdupq_n_u32(n as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ushr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57491,20 +56710,26 @@ pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t { - unsafe { transmute(a) } +pub fn vshr_n_u64(a: uint64x1_t) -> uint64x1_t { + static_assert!(N >= 1 && N <= 64); + let n: i32 = if N == 64 { + return vdup_n_u64(0); + } else { + N + }; + unsafe { simd_shr(a, vdup_n_u64(n as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ushr, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57513,25 +56738,26 @@ pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vshrq_n_u64(a: uint64x2_t) -> uint64x2_t { + static_assert!(N >= 1 && N <= 64); + let n: i32 = if N == 64 { + return vdupq_n_u64(0); + } else { + N + }; + unsafe { simd_shr(a, vdupq_n_u64(n as _)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(shrn, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57540,20 +56766,21 @@ pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t { - unsafe { transmute(a) } +pub fn vshrn_n_s16(a: int16x8_t) -> int8x8_t { + static_assert!(N >= 1 && N <= 8); + unsafe { simd_cast(simd_shr(a, vdupq_n_s16(N as _))) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(shrn, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57562,21 +56789,21 @@ pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vshrn_n_s32(a: int32x4_t) -> int16x4_t { + static_assert!(N >= 1 && N <= 16); + unsafe { simd_cast(simd_shr(a, vdupq_n_s32(N as _))) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(shrn, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57585,20 +56812,21 @@ pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 { - unsafe { transmute(a) } +pub fn vshrn_n_s64(a: int64x2_t) -> int32x2_t { + static_assert!(N >= 1 && N <= 32); + unsafe { simd_cast(simd_shr(a, vdupq_n_s64(N as _))) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(shrn, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57607,21 +56835,21 @@ pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vshrn_n_u16(a: uint16x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); + unsafe { simd_cast(simd_shr(a, vdupq_n_u16(N as _))) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(shrn, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57630,20 +56858,21 @@ pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t { - unsafe { transmute(a) } +pub fn vshrn_n_u32(a: uint32x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + unsafe { simd_cast(simd_shr(a, vdupq_n_u32(N as _))) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(shrn, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57652,24 +56881,261 @@ pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vshrn_n_u64(a: uint64x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + unsafe { simd_cast(simd_shr(a, vdupq_n_u64(N as _))) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Shift Left and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s8)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsli_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + static_assert_uimm_bits!(N, 3); + vshiftlins_v8i8::(a, b) +} +#[doc = "Shift Left and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s8)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsliq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + static_assert_uimm_bits!(N, 3); + vshiftlins_v16i8::(a, b) +} +#[doc = "Shift Left and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s16)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsli_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(N, 4); + vshiftlins_v4i16::(a, b) +} +#[doc = "Shift Left and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s16)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsliq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(N, 4); + vshiftlins_v8i16::(a, b) +} +#[doc = "Shift Left and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s32)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsli_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + static_assert!(N >= 0 && N <= 31); + vshiftlins_v2i32::(a, b) +} +#[doc = "Shift Left and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s32)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsliq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + static_assert!(N >= 0 && N <= 31); + vshiftlins_v4i32::(a, b) +} +#[doc = "Shift Left and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s64)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsli_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + static_assert!(N >= 0 && N <= 63); + vshiftlins_v1i64::(a, b) +} +#[doc = "Shift Left and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s64)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsliq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + static_assert!(N >= 0 && N <= 63); + vshiftlins_v2i64::(a, b) +} +#[doc = "Shift Left and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u8)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsli_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { transmute(vshiftlins_v8i8::(transmute(a), transmute(b))) } +} +#[doc = "Shift Left and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u8)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsliq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 3); + unsafe { transmute(vshiftlins_v16i8::(transmute(a), transmute(b))) } +} +#[doc = "Shift Left and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u16)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsli_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(N, 4); + unsafe { transmute(vshiftlins_v4i16::(transmute(a), transmute(b))) } +} +#[doc = "Shift Left and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u16)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsliq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(N, 4); + unsafe { transmute(vshiftlins_v8i16::(transmute(a), transmute(b))) } +} +#[doc = "Shift Left and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u32)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsli_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + static_assert!(N >= 0 && N <= 31); + unsafe { transmute(vshiftlins_v2i32::(transmute(a), transmute(b))) } +} +#[doc = "Shift Left and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u32)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsliq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + static_assert!(N >= 0 && N <= 31); + unsafe { transmute(vshiftlins_v4i32::(transmute(a), transmute(b))) } +} +#[doc = "Shift Left and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u64)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsli_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + static_assert!(N >= 0 && N <= 63); + unsafe { transmute(vshiftlins_v1i64::(transmute(a), transmute(b))) } +} +#[doc = "Shift Left and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u64)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsliq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + static_assert!(N >= 0 && N <= 63); + unsafe { transmute(vshiftlins_v2i64::(transmute(a), transmute(b))) } +} +#[doc = "Shift Left and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p8)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsli_n_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { transmute(vshiftlins_v8i8::(transmute(a), transmute(b))) } +} +#[doc = "Shift Left and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p8)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsliq_n_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + static_assert_uimm_bits!(N, 3); + unsafe { transmute(vshiftlins_v16i8::(transmute(a), transmute(b))) } +} +#[doc = "Shift Left and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p16)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsli_n_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + static_assert_uimm_bits!(N, 4); + unsafe { transmute(vshiftlins_v4i16::(transmute(a), transmute(b))) } +} +#[doc = "Shift Left and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p16)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsliq_n_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + static_assert_uimm_bits!(N, 4); + unsafe { transmute(vshiftlins_v8i16::(transmute(a), transmute(b))) } +} +#[doc = "Signed shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ssra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57678,20 +57144,21 @@ pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t { - unsafe { transmute(a) } +pub fn vsra_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + static_assert!(N >= 1 && N <= 8); + unsafe { simd_add(a, vshr_n_s8::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Signed shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ssra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57700,23 +57167,21 @@ pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t { - unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vsraq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + static_assert!(N >= 1 && N <= 8); + unsafe { simd_add(a, vshrq_n_s8::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Signed shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ssra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57725,20 +57190,21 @@ pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t { - unsafe { transmute(a) } +pub fn vsra_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + static_assert!(N >= 1 && N <= 16); + unsafe { simd_add(a, vshr_n_s16::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Signed shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ssra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57747,23 +57213,21 @@ pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t { - unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vsraq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + static_assert!(N >= 1 && N <= 16); + unsafe { simd_add(a, vshrq_n_s16::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Signed shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ssra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57772,20 +57236,21 @@ pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t { - unsafe { transmute(a) } +pub fn vsra_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + static_assert!(N >= 1 && N <= 32); + unsafe { simd_add(a, vshr_n_s32::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Signed shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ssra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57794,23 +57259,21 @@ pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t { - unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vsraq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + static_assert!(N >= 1 && N <= 32); + unsafe { simd_add(a, vshrq_n_s32::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Signed shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ssra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57819,20 +57282,21 @@ pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t { - unsafe { transmute(a) } +pub fn vsra_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + static_assert!(N >= 1 && N <= 64); + unsafe { simd_add(a, vshr_n_s64::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Signed shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ssra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57841,23 +57305,21 @@ pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t { - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vsraq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + static_assert!(N >= 1 && N <= 64); + unsafe { simd_add(a, vshrq_n_s64::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Unsigned shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(usra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57866,20 +57328,21 @@ pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t { - unsafe { transmute(a) } +pub fn vsra_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); + unsafe { simd_add(a, vshr_n_u8::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Unsigned shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(usra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57888,23 +57351,21 @@ pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t { - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vsraq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + static_assert!(N >= 1 && N <= 8); + unsafe { simd_add(a, vshrq_n_u8::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Unsigned shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(usra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57913,20 +57374,21 @@ pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t { - unsafe { transmute(a) } +pub fn vsra_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + unsafe { simd_add(a, vshr_n_u16::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Unsigned shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(usra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57935,45 +57397,21 @@ pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t { - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vsraq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + static_assert!(N >= 1 && N <= 16); + unsafe { simd_add(a, vshrq_n_u16::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Unsigned shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(usra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -57982,23 +57420,21 @@ pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t { - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vsra_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + unsafe { simd_add(a, vshr_n_u32::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Unsigned shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(usra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -58007,20 +57443,21 @@ pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t { - unsafe { transmute(a) } +pub fn vsraq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + static_assert!(N >= 1 && N <= 32); + unsafe { simd_add(a, vshrq_n_u32::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Unsigned shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(usra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -58029,23 +57466,21 @@ pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t { - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vsra_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + static_assert!(N >= 1 && N <= 64); + unsafe { simd_add(a, vshr_n_u64::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Unsigned shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(usra, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -58054,6952 +57489,169 @@ pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 { - unsafe { transmute(a) } +pub fn vsraq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + static_assert!(N >= 1 && N <= 64); + unsafe { simd_add(a, vshrq_n_u64::(b)) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { transmute(a) } +#[doc = "Shift Right and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsri_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + static_assert!(1 <= N && N <= 8); + vshiftrins_v8i8::(a, b) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t { - unsafe { transmute(a) } +#[doc = "Shift Right and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsriq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + static_assert!(1 <= N && N <= 8); + vshiftrins_v16i8::(a, b) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +#[doc = "Shift Right and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsri_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + static_assert!(1 <= N && N <= 16); + vshiftrins_v4i16::(a, b) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t { - unsafe { transmute(a) } +#[doc = "Shift Right and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsriq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + static_assert!(1 <= N && N <= 16); + vshiftrins_v8i16::(a, b) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +#[doc = "Shift Right and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsri_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + static_assert!(1 <= N && N <= 32); + vshiftrins_v2i32::(a, b) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t { - unsafe { transmute(a) } +#[doc = "Shift Right and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsriq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + static_assert!(1 <= N && N <= 32); + vshiftrins_v4i32::(a, b) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +#[doc = "Shift Right and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsri_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + static_assert!(1 <= N && N <= 64); + vshiftrins_v1i64::(a, b) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t { - unsafe { transmute(a) } +#[doc = "Shift Right and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsriq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + static_assert!(1 <= N && N <= 64); + vshiftrins_v2i64::(a, b) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +#[doc = "Shift Right and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsri_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + static_assert!(1 <= N && N <= 8); + unsafe { transmute(vshiftrins_v8i8::(transmute(a), transmute(b))) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t { - unsafe { transmute(a) } +#[doc = "Shift Right and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u8)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsriq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + static_assert!(1 <= N && N <= 8); + unsafe { transmute(vshiftrins_v16i8::(transmute(a), transmute(b))) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +#[doc = "Shift Right and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u16)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsri_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + static_assert!(1 <= N && N <= 16); + unsafe { transmute(vshiftrins_v4i16::(transmute(a), transmute(b))) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t { - unsafe { transmute(a) } +#[doc = "Shift Right and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u16)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsriq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + static_assert!(1 <= N && N <= 16); + unsafe { transmute(vshiftrins_v8i16::(transmute(a), transmute(b))) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_p8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev16) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev16_p8(a: poly8x8_t) -> poly8x8_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev16) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev16_s8(a: int8x8_t) -> int8x8_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev16) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev16_u8(a: uint8x8_t) -> uint8x8_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_p8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev16) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev16q_p8(a: poly8x16_t) -> poly8x16_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev16) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev16q_s8(a: int8x16_t) -> int8x16_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev16) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev16q_u8(a: uint8x16_t) -> uint8x16_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev32_p16(a: poly16x4_t) -> poly16x4_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev32_p8(a: poly8x8_t) -> poly8x8_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev32_s16(a: int16x4_t) -> int16x4_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev32_s8(a: int8x8_t) -> int8x8_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev32_u16(a: uint16x4_t) -> uint16x4_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev32_u8(a: uint8x8_t) -> uint8x8_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev32q_p16(a: poly16x8_t) -> poly16x8_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev32q_p8(a: poly8x16_t) -> poly8x16_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev32q_s16(a: int16x8_t) -> int16x8_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev32q_s8(a: int8x16_t) -> int8x16_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev32q_u16(a: uint16x8_t) -> uint16x8_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev32q_u8(a: uint8x16_t) -> uint8x16_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev64) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev64_f32(a: float32x2_t) -> float32x2_t { - unsafe { simd_shuffle!(a, a, [1, 0]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev64) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev64_p16(a: poly16x4_t) -> poly16x4_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev64) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev64_p8(a: poly8x8_t) -> poly8x8_t { - unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev64) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev64_s16(a: int16x4_t) -> int16x4_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev64) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev64_s32(a: int32x2_t) -> int32x2_t { - unsafe { simd_shuffle!(a, a, [1, 0]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev64) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev64_s8(a: int8x8_t) -> int8x8_t { - unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev64) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev64_u16(a: uint16x4_t) -> uint16x4_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev64) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev64_u32(a: uint32x2_t) -> uint32x2_t { - unsafe { simd_shuffle!(a, a, [1, 0]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev64) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev64_u8(a: uint8x8_t) -> uint8x8_t { - unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev64) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev64q_f32(a: float32x4_t) -> float32x4_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev64) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev64q_p16(a: poly16x8_t) -> poly16x8_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev64) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev64q_p8(a: poly8x16_t) -> poly8x16_t { - unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev64) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev64q_s16(a: int16x8_t) -> int16x8_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev64) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev64q_s32(a: int32x4_t) -> int32x4_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev64) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev64q_s8(a: int8x16_t) -> int8x16_t { - unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev64) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev64q_u16(a: uint16x8_t) -> uint16x8_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev64) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev64q_u32(a: uint32x4_t) -> uint32x4_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } -} -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev64) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrev64q_u8(a: uint8x16_t) -> uint8x16_t { - unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) } -} -#[doc = "Reverse elements in 64-bit doublewords"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev64) -)] -#[target_feature(enable = "neon,fp16")] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vrev64_f16(a: float16x4_t) -> float16x4_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) } -} -#[doc = "Reverse elements in 64-bit doublewords"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev64) -)] -#[target_feature(enable = "neon,fp16")] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vrev64q_f16(a: float16x8_t) -> float16x8_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } -} -#[doc = "Rounding halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srhadd) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.srhadd.v8i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v8i8")] - fn _vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; - } - unsafe { _vrhadd_s8(a, b) } -} -#[doc = "Rounding halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srhadd) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.srhadd.v16i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v16i8")] - fn _vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; - } - unsafe { _vrhaddq_s8(a, b) } -} -#[doc = "Rounding halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srhadd) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.srhadd.v4i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v4i16")] - fn _vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; - } - unsafe { _vrhadd_s16(a, b) } -} -#[doc = "Rounding halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srhadd) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.srhadd.v8i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v8i16")] - fn _vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; - } - unsafe { _vrhaddq_s16(a, b) } -} -#[doc = "Rounding halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srhadd) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.srhadd.v2i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v2i32")] - fn _vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; - } - unsafe { _vrhadd_s32(a, b) } -} -#[doc = "Rounding halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srhadd) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.srhadd.v4i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v4i32")] - fn _vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; - } - unsafe { _vrhaddq_s32(a, b) } -} -#[doc = "Rounding halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urhadd) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.urhadd.v8i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v8i8")] - fn _vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; - } - unsafe { _vrhadd_u8(a, b) } -} -#[doc = "Rounding halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urhadd) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.urhadd.v16i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v16i8")] - fn _vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; - } - unsafe { _vrhaddq_u8(a, b) } -} -#[doc = "Rounding halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urhadd) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.urhadd.v4i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v4i16")] - fn _vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; - } - unsafe { _vrhadd_u16(a, b) } -} -#[doc = "Rounding halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urhadd) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.urhadd.v8i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v8i16")] - fn _vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; - } - unsafe { _vrhaddq_u16(a, b) } -} -#[doc = "Rounding halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urhadd) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.urhadd.v2i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v2i32")] - fn _vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; - } - unsafe { _vrhadd_u32(a, b) } -} -#[doc = "Rounding halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urhadd) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.urhadd.v4i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v4i32")] - fn _vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; - } - unsafe { _vrhaddq_u32(a, b) } -} -#[doc = "Floating-point round to integral, to nearest with ties to even"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(frintn) -)] -#[target_feature(enable = "neon,fp16")] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vrndn_f16(a: float16x4_t) -> float16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec", target_arch = "arm"), - link_name = "llvm.roundeven.v4f16" - )] - fn _vrndn_f16(a: float16x4_t) -> float16x4_t; - } - unsafe { _vrndn_f16(a) } -} -#[doc = "Floating-point round to integral, to nearest with ties to even"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(frintn) -)] -#[target_feature(enable = "neon,fp16")] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vrndnq_f16(a: float16x8_t) -> float16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec", target_arch = "arm"), - link_name = "llvm.roundeven.v8f16" - )] - fn _vrndnq_f16(a: float16x8_t) -> float16x8_t; - } - unsafe { _vrndnq_f16(a) } -} -#[doc = "Floating-point round to integral, to nearest with ties to even"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(frintn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrndn_f32(a: float32x2_t) -> float32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec", target_arch = "arm"), - link_name = "llvm.roundeven.v2f32" - )] - fn _vrndn_f32(a: float32x2_t) -> float32x2_t; - } - unsafe { _vrndn_f32(a) } -} -#[doc = "Floating-point round to integral, to nearest with ties to even"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(frintn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrndnq_f32(a: float32x4_t) -> float32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec", target_arch = "arm"), - link_name = "llvm.roundeven.v4f32" - )] - fn _vrndnq_f32(a: float32x4_t) -> float32x4_t; - } - unsafe { _vrndnq_f32(a) } -} -#[doc = "Signed rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v8i8")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.srshl.v8i8" - )] - fn _vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; - } - unsafe { _vrshl_s8(a, b) } -} -#[doc = "Signed rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v16i8")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.srshl.v16i8" - )] - fn _vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; - } - unsafe { _vrshlq_s8(a, b) } -} -#[doc = "Signed rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v4i16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.srshl.v4i16" - )] - fn _vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; - } - unsafe { _vrshl_s16(a, b) } -} -#[doc = "Signed rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v8i16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.srshl.v8i16" - )] - fn _vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; - } - unsafe { _vrshlq_s16(a, b) } -} -#[doc = "Signed rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v2i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.srshl.v2i32" - )] - fn _vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; - } - unsafe { _vrshl_s32(a, b) } -} -#[doc = "Signed rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v4i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.srshl.v4i32" - )] - fn _vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; - } - unsafe { _vrshlq_s32(a, b) } -} -#[doc = "Signed rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v1i64")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.srshl.v1i64" - )] - fn _vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t; - } - unsafe { _vrshl_s64(a, b) } -} -#[doc = "Signed rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v2i64")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.srshl.v2i64" - )] - fn _vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; - } - unsafe { _vrshlq_s64(a, b) } -} -#[doc = "Unsigned rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v8i8")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.urshl.v8i8" - )] - fn _vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t; - } - unsafe { _vrshl_u8(a, b) } -} -#[doc = "Unsigned rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v16i8")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.urshl.v16i8" - )] - fn _vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t; - } - unsafe { _vrshlq_u8(a, b) } -} -#[doc = "Unsigned rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v4i16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.urshl.v4i16" - )] - fn _vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t; - } - unsafe { _vrshl_u16(a, b) } -} -#[doc = "Unsigned rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v8i16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.urshl.v8i16" - )] - fn _vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t; - } - unsafe { _vrshlq_u16(a, b) } -} -#[doc = "Unsigned rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v2i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.urshl.v2i32" - )] - fn _vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t; - } - unsafe { _vrshl_u32(a, b) } -} -#[doc = "Unsigned rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v4i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.urshl.v4i32" - )] - fn _vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t; - } - unsafe { _vrshlq_u32(a, b) } -} -#[doc = "Unsigned rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v1i64")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.urshl.v1i64" - )] - fn _vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t; - } - unsafe { _vrshl_u64(a, b) } -} -#[doc = "Unsigned rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v2i64")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.urshl.v2i64" - )] - fn _vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t; - } - unsafe { _vrshlq_u64(a, b) } -} -#[doc = "Signed rounding shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshr_n_s8(a: int8x8_t) -> int8x8_t { - static_assert!(N >= 1 && N <= 8); - vrshl_s8(a, vdup_n_s8(-N as _)) -} -#[doc = "Signed rounding shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshrq_n_s8(a: int8x16_t) -> int8x16_t { - static_assert!(N >= 1 && N <= 8); - vrshlq_s8(a, vdupq_n_s8(-N as _)) -} -#[doc = "Signed rounding shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshr_n_s16(a: int16x4_t) -> int16x4_t { - static_assert!(N >= 1 && N <= 16); - vrshl_s16(a, vdup_n_s16(-N as _)) -} -#[doc = "Signed rounding shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshrq_n_s16(a: int16x8_t) -> int16x8_t { - static_assert!(N >= 1 && N <= 16); - vrshlq_s16(a, vdupq_n_s16(-N as _)) -} -#[doc = "Signed rounding shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshr_n_s32(a: int32x2_t) -> int32x2_t { - static_assert!(N >= 1 && N <= 32); - vrshl_s32(a, vdup_n_s32(-N as _)) -} -#[doc = "Signed rounding shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshrq_n_s32(a: int32x4_t) -> int32x4_t { - static_assert!(N >= 1 && N <= 32); - vrshlq_s32(a, vdupq_n_s32(-N as _)) -} -#[doc = "Signed rounding shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshr_n_s64(a: int64x1_t) -> int64x1_t { - static_assert!(N >= 1 && N <= 64); - vrshl_s64(a, vdup_n_s64(-N as _)) -} -#[doc = "Signed rounding shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshrq_n_s64(a: int64x2_t) -> int64x2_t { - static_assert!(N >= 1 && N <= 64); - vrshlq_s64(a, vdupq_n_s64(-N as _)) -} -#[doc = "Unsigned rounding shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshr_n_u8(a: uint8x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - vrshl_u8(a, vdup_n_s8(-N as _)) -} -#[doc = "Unsigned rounding shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshrq_n_u8(a: uint8x16_t) -> uint8x16_t { - static_assert!(N >= 1 && N <= 8); - vrshlq_u8(a, vdupq_n_s8(-N as _)) -} -#[doc = "Unsigned rounding shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshr_n_u16(a: uint16x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - vrshl_u16(a, vdup_n_s16(-N as _)) -} -#[doc = "Unsigned rounding shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshrq_n_u16(a: uint16x8_t) -> uint16x8_t { - static_assert!(N >= 1 && N <= 16); - vrshlq_u16(a, vdupq_n_s16(-N as _)) -} -#[doc = "Unsigned rounding shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshr_n_u32(a: uint32x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - vrshl_u32(a, vdup_n_s32(-N as _)) -} -#[doc = "Unsigned rounding shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshrq_n_u32(a: uint32x4_t) -> uint32x4_t { - static_assert!(N >= 1 && N <= 32); - vrshlq_u32(a, vdupq_n_s32(-N as _)) -} -#[doc = "Unsigned rounding shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshr_n_u64(a: uint64x1_t) -> uint64x1_t { - static_assert!(N >= 1 && N <= 64); - vrshl_u64(a, vdup_n_s64(-N as _)) -} -#[doc = "Unsigned rounding shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshrq_n_u64(a: uint64x2_t) -> uint64x2_t { - static_assert!(N >= 1 && N <= 64); - vrshlq_u64(a, vdupq_n_s64(-N as _)) -} -#[doc = "Rounding shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vrshrn_n_s16(a: int16x8_t) -> int8x8_t { - static_assert!(N >= 1 && N <= 8); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v8i8")] - fn _vrshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t; - } - unsafe { _vrshrn_n_s16(a, const { int16x8_t([-N as i16; 8]) }) } -} -#[doc = "Rounding shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vrshrn_n_s32(a: int32x4_t) -> int16x4_t { - static_assert!(N >= 1 && N <= 16); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v4i16")] - fn _vrshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t; - } - unsafe { _vrshrn_n_s32(a, const { int32x4_t([-N; 4]) }) } -} -#[doc = "Rounding shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vrshrn_n_s64(a: int64x2_t) -> int32x2_t { - static_assert!(N >= 1 && N <= 32); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v2i32")] - fn _vrshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t; - } - unsafe { _vrshrn_n_s64(a, const { int64x2_t([-N as i64; 2]) }) } -} -#[doc = "Rounding shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(rshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vrshrn_n_s16(a: int16x8_t) -> int8x8_t { - static_assert!(N >= 1 && N <= 8); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.rshrn.v8i8" - )] - fn _vrshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t; - } - unsafe { _vrshrn_n_s16(a, N) } -} -#[doc = "Rounding shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(rshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vrshrn_n_s32(a: int32x4_t) -> int16x4_t { - static_assert!(N >= 1 && N <= 16); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.rshrn.v4i16" - )] - fn _vrshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t; - } - unsafe { _vrshrn_n_s32(a, N) } -} -#[doc = "Rounding shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(rshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vrshrn_n_s64(a: int64x2_t) -> int32x2_t { - static_assert!(N >= 1 && N <= 32); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.rshrn.v2i32" - )] - fn _vrshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t; - } - unsafe { _vrshrn_n_s64(a, N) } -} -#[doc = "Rounding shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rshrn, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - unsafe { transmute(vrshrn_n_s16::(transmute(a))) } -} -#[doc = "Rounding shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rshrn, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - unsafe { transmute(vrshrn_n_s32::(transmute(a))) } -} -#[doc = "Rounding shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rshrn, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - unsafe { transmute(vrshrn_n_s64::(transmute(a))) } -} -#[doc = "Reciprocal square-root estimate."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,fp16")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(frsqrte) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vrsqrte_f16(a: float16x4_t) -> float16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4f16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.frsqrte.v4f16" - )] - fn _vrsqrte_f16(a: float16x4_t) -> float16x4_t; - } - unsafe { _vrsqrte_f16(a) } -} -#[doc = "Reciprocal square-root estimate."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,fp16")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(frsqrte) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vrsqrteq_f16(a: float16x8_t) -> float16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v8f16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.frsqrte.v8f16" - )] - fn _vrsqrteq_f16(a: float16x8_t) -> float16x8_t; - } - unsafe { _vrsqrteq_f16(a) } -} -#[doc = "Reciprocal square-root estimate."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(frsqrte) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsqrte_f32(a: float32x2_t) -> float32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v2f32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.frsqrte.v2f32" - )] - fn _vrsqrte_f32(a: float32x2_t) -> float32x2_t; - } - unsafe { _vrsqrte_f32(a) } -} -#[doc = "Reciprocal square-root estimate."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(frsqrte) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsqrteq_f32(a: float32x4_t) -> float32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4f32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.frsqrte.v4f32" - )] - fn _vrsqrteq_f32(a: float32x4_t) -> float32x4_t; - } - unsafe { _vrsqrteq_f32(a) } -} -#[doc = "Unsigned reciprocal square root estimate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ursqrte) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsqrte_u32(a: uint32x2_t) -> uint32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v2i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ursqrte.v2i32" - )] - fn _vrsqrte_u32(a: uint32x2_t) -> uint32x2_t; - } - unsafe { _vrsqrte_u32(a) } -} -#[doc = "Unsigned reciprocal square root estimate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ursqrte) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ursqrte.v4i32" - )] - fn _vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t; - } - unsafe { _vrsqrteq_u32(a) } -} -#[doc = "Floating-point reciprocal square root step"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,fp16")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(frsqrts) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v4f16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.frsqrts.v4f16" - )] - fn _vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; - } - unsafe { _vrsqrts_f16(a, b) } -} -#[doc = "Floating-point reciprocal square root step"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,fp16")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(frsqrts) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v8f16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.frsqrts.v8f16" - )] - fn _vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; - } - unsafe { _vrsqrtsq_f16(a, b) } -} -#[doc = "Floating-point reciprocal square root step"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(frsqrts) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v2f32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.frsqrts.v2f32" - )] - fn _vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; - } - unsafe { _vrsqrts_f32(a, b) } -} -#[doc = "Floating-point reciprocal square root step"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(frsqrts) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v4f32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.frsqrts.v4f32" - )] - fn _vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; - } - unsafe { _vrsqrtsq_f32(a, b) } -} -#[doc = "Signed rounding shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srsra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsra_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - static_assert!(N >= 1 && N <= 8); - unsafe { simd_add(a, vrshr_n_s8::(b)) } -} -#[doc = "Signed rounding shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srsra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsraq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - static_assert!(N >= 1 && N <= 8); - unsafe { simd_add(a, vrshrq_n_s8::(b)) } -} -#[doc = "Signed rounding shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srsra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsra_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - static_assert!(N >= 1 && N <= 16); - unsafe { simd_add(a, vrshr_n_s16::(b)) } -} -#[doc = "Signed rounding shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srsra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsraq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - static_assert!(N >= 1 && N <= 16); - unsafe { simd_add(a, vrshrq_n_s16::(b)) } -} -#[doc = "Signed rounding shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srsra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsra_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - static_assert!(N >= 1 && N <= 32); - unsafe { simd_add(a, vrshr_n_s32::(b)) } -} -#[doc = "Signed rounding shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srsra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsraq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - static_assert!(N >= 1 && N <= 32); - unsafe { simd_add(a, vrshrq_n_s32::(b)) } -} -#[doc = "Signed rounding shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srsra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsra_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - static_assert!(N >= 1 && N <= 64); - unsafe { simd_add(a, vrshr_n_s64::(b)) } -} -#[doc = "Signed rounding shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(srsra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsraq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - static_assert!(N >= 1 && N <= 64); - unsafe { simd_add(a, vrshrq_n_s64::(b)) } -} -#[doc = "Unsigned rounding shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ursra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsra_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - unsafe { simd_add(a, vrshr_n_u8::(b)) } -} -#[doc = "Unsigned rounding shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ursra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsraq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - static_assert!(N >= 1 && N <= 8); - unsafe { simd_add(a, vrshrq_n_u8::(b)) } -} -#[doc = "Unsigned rounding shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ursra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsra_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - unsafe { simd_add(a, vrshr_n_u16::(b)) } -} -#[doc = "Unsigned rounding shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ursra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsraq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - static_assert!(N >= 1 && N <= 16); - unsafe { simd_add(a, vrshrq_n_u16::(b)) } -} -#[doc = "Unsigned rounding shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ursra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsra_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - unsafe { simd_add(a, vrshr_n_u32::(b)) } -} -#[doc = "Unsigned rounding shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ursra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsraq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - static_assert!(N >= 1 && N <= 32); - unsafe { simd_add(a, vrshrq_n_u32::(b)) } -} -#[doc = "Unsigned rounding shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ursra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsra_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - static_assert!(N >= 1 && N <= 64); - unsafe { simd_add(a, vrshr_n_u64::(b)) } -} -#[doc = "Unsigned rounding shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ursra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsraq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - static_assert!(N >= 1 && N <= 64); - unsafe { simd_add(a, vrshrq_n_u64::(b)) } -} -#[doc = "Rounding subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rsubhn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v8i8")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.rsubhn.v8i8" - )] - fn _vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t; - } - unsafe { _vrsubhn_s16(a, b) } -} -#[doc = "Rounding subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rsubhn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v4i16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.rsubhn.v4i16" - )] - fn _vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t; - } - unsafe { _vrsubhn_s32(a, b) } -} -#[doc = "Rounding subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rsubhn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v2i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.rsubhn.v2i32" - )] - fn _vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t; - } - unsafe { _vrsubhn_s64(a, b) } -} -#[doc = "Rounding subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rsubhn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { - unsafe { transmute(vrsubhn_s16(transmute(a), transmute(b))) } -} -#[doc = "Rounding subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rsubhn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vrsubhn_s16(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Rounding subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rsubhn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { - unsafe { transmute(vrsubhn_s32(transmute(a), transmute(b))) } -} -#[doc = "Rounding subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rsubhn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x4_t = transmute(vrsubhn_s32(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Rounding subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rsubhn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { - unsafe { transmute(vrsubhn_s64(transmute(a), transmute(b))) } -} -#[doc = "Rounding subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rsubhn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) }; - unsafe { - let ret_val: uint32x2_t = transmute(vrsubhn_s64(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vset_lane_f16(a: f16, b: float16x4_t) -> float16x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vsetq_lane_f16(a: f16, b: float16x8_t) -> float16x8_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vset_lane_f32(a: f32, b: float32x2_t) -> float32x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsetq_lane_f32(a: f32, b: float32x4_t) -> float32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vset_lane_s8(a: i8, b: int8x8_t) -> int8x8_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsetq_lane_s8(a: i8, b: int8x16_t) -> int8x16_t { - static_assert_uimm_bits!(LANE, 4); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vset_lane_s16(a: i16, b: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsetq_lane_s16(a: i16, b: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vset_lane_s32(a: i32, b: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsetq_lane_s32(a: i32, b: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsetq_lane_s64(a: i64, b: int64x2_t) -> int64x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vset_lane_u8(a: u8, b: uint8x8_t) -> uint8x8_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsetq_lane_u8(a: u8, b: uint8x16_t) -> uint8x16_t { - static_assert_uimm_bits!(LANE, 4); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vset_lane_u16(a: u16, b: uint16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsetq_lane_u16(a: u16, b: uint16x8_t) -> uint16x8_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vset_lane_u32(a: u32, b: uint32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsetq_lane_u32(a: u32, b: uint32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsetq_lane_u64(a: u64, b: uint64x2_t) -> uint64x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vset_lane_p8(a: p8, b: poly8x8_t) -> poly8x8_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsetq_lane_p8(a: p8, b: poly8x16_t) -> poly8x16_t { - static_assert_uimm_bits!(LANE, 4); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vset_lane_p16(a: p16, b: poly16x4_t) -> poly16x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsetq_lane_p16(a: p16, b: poly16x8_t) -> poly16x8_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p64)"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vset_lane_p64(a: p64, b: poly64x1_t) -> poly64x1_t { - static_assert!(LANE == 0); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vset_lane_s64(a: i64, b: int64x1_t) -> int64x1_t { - static_assert!(LANE == 0); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vset_lane_u64(a: u64, b: uint64x1_t) -> uint64x1_t { - static_assert!(LANE == 0); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p64)"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsetq_lane_p64(a: p64, b: poly64x2_t) -> poly64x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { simd_insert!(b, LANE as u32, a) } -} -#[doc = "SHA1 hash update accelerator, choose."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1cq_u32)"] -#[inline(always)] -#[target_feature(enable = "sha2")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(test, assert_instr(sha1c))] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") -)] -pub fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.crypto.sha1c" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1c")] - fn _vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t; - } - unsafe { _vsha1cq_u32(hash_abcd, hash_e, wk) } -} -#[doc = "SHA1 fixed rotate."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1h_u32)"] -#[inline(always)] -#[target_feature(enable = "sha2")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(test, assert_instr(sha1h))] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") -)] -pub fn vsha1h_u32(hash_e: u32) -> u32 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.crypto.sha1h" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1h")] - fn _vsha1h_u32(hash_e: u32) -> u32; - } - unsafe { _vsha1h_u32(hash_e) } -} -#[doc = "SHA1 hash update accelerator, majority"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1mq_u32)"] -#[inline(always)] -#[target_feature(enable = "sha2")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(test, assert_instr(sha1m))] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") -)] -pub fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.crypto.sha1m" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1m")] - fn _vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t; - } - unsafe { _vsha1mq_u32(hash_abcd, hash_e, wk) } -} -#[doc = "SHA1 hash update accelerator, parity"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1pq_u32)"] -#[inline(always)] -#[target_feature(enable = "sha2")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(test, assert_instr(sha1p))] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") -)] -pub fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.crypto.sha1p" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1p")] - fn _vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t; - } - unsafe { _vsha1pq_u32(hash_abcd, hash_e, wk) } -} -#[doc = "SHA1 schedule update accelerator, first part."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su0q_u32)"] -#[inline(always)] -#[target_feature(enable = "sha2")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(test, assert_instr(sha1su0))] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") -)] -pub fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.crypto.sha1su0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su0")] - fn _vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t; - } - unsafe { _vsha1su0q_u32(w0_3, w4_7, w8_11) } -} -#[doc = "SHA1 schedule update accelerator, second part."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su1q_u32)"] -#[inline(always)] -#[target_feature(enable = "sha2")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(test, assert_instr(sha1su1))] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") -)] -pub fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.crypto.sha1su1" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su1")] - fn _vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t; - } - unsafe { _vsha1su1q_u32(tw0_3, w12_15) } -} -#[doc = "SHA1 schedule update accelerator, upper part."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256h2q_u32)"] -#[inline(always)] -#[target_feature(enable = "sha2")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(test, assert_instr(sha256h2))] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") -)] -pub fn vsha256h2q_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.crypto.sha256h2" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h2")] - fn _vsha256h2q_u32( - hash_abcd: uint32x4_t, - hash_efgh: uint32x4_t, - wk: uint32x4_t, - ) -> uint32x4_t; - } - unsafe { _vsha256h2q_u32(hash_abcd, hash_efgh, wk) } -} -#[doc = "SHA1 schedule update accelerator, first part."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256hq_u32)"] -#[inline(always)] -#[target_feature(enable = "sha2")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(test, assert_instr(sha256h))] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") -)] -pub fn vsha256hq_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.crypto.sha256h" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h")] - fn _vsha256hq_u32( - hash_abcd: uint32x4_t, - hash_efgh: uint32x4_t, - wk: uint32x4_t, - ) -> uint32x4_t; - } - unsafe { _vsha256hq_u32(hash_abcd, hash_efgh, wk) } -} -#[doc = "SHA256 schedule update accelerator, first part."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su0q_u32)"] -#[inline(always)] -#[target_feature(enable = "sha2")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(test, assert_instr(sha256su0))] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") -)] -pub fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.crypto.sha256su0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su0")] - fn _vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t; - } - unsafe { _vsha256su0q_u32(w0_3, w4_7) } -} -#[doc = "SHA256 schedule update accelerator, second part."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su1q_u32)"] -#[inline(always)] -#[target_feature(enable = "sha2")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(test, assert_instr(sha256su1))] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") -)] -pub fn vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.crypto.sha256su1" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su1")] - fn _vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t) - -> uint32x4_t; - } - unsafe { _vsha256su1q_u32(tw0_3, w8_11, w12_15) } -} -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[rustc_legacy_const_generics(2)] -fn vshiftlins_v16i8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v16i8")] - fn _vshiftlins_v16i8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t; - } - unsafe { _vshiftlins_v16i8(a, b, const { int8x16_t([N as i8; 16]) }) } -} -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[rustc_legacy_const_generics(2)] -fn vshiftlins_v1i64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v1i64")] - fn _vshiftlins_v1i64(a: int64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t; - } - unsafe { _vshiftlins_v1i64(a, b, const { int64x1_t([N as i64; 1]) }) } -} -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[rustc_legacy_const_generics(2)] -fn vshiftlins_v2i32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i32")] - fn _vshiftlins_v2i32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t; - } - unsafe { _vshiftlins_v2i32(a, b, const { int32x2_t([N; 2]) }) } -} -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[rustc_legacy_const_generics(2)] -fn vshiftlins_v2i64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i64")] - fn _vshiftlins_v2i64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t; - } - unsafe { _vshiftlins_v2i64(a, b, const { int64x2_t([N as i64; 2]) }) } -} -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[rustc_legacy_const_generics(2)] -fn vshiftlins_v4i16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i16")] - fn _vshiftlins_v4i16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t; - } - unsafe { _vshiftlins_v4i16(a, b, const { int16x4_t([N as i16; 4]) }) } -} -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[rustc_legacy_const_generics(2)] -fn vshiftlins_v4i32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i32")] - fn _vshiftlins_v4i32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t; - } - unsafe { _vshiftlins_v4i32(a, b, const { int32x4_t([N; 4]) }) } -} -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[rustc_legacy_const_generics(2)] -fn vshiftlins_v8i16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i16")] - fn _vshiftlins_v8i16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t; - } - unsafe { _vshiftlins_v8i16(a, b, const { int16x8_t([N as i16; 8]) }) } -} -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[rustc_legacy_const_generics(2)] -fn vshiftlins_v8i8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i8")] - fn _vshiftlins_v8i8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t; - } - unsafe { _vshiftlins_v8i8(a, b, const { int8x8_t([N as i8; 8]) }) } -} -#[doc = "Shift Right and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v16i8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[rustc_legacy_const_generics(2)] -fn vshiftrins_v16i8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v16i8")] - fn _vshiftrins_v16i8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t; - } - unsafe { _vshiftrins_v16i8(a, b, const { int8x16_t([-N as i8; 16]) }) } -} -#[doc = "Shift Right and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v1i64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[rustc_legacy_const_generics(2)] -fn vshiftrins_v1i64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v1i64")] - fn _vshiftrins_v1i64(a: int64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t; - } - unsafe { _vshiftrins_v1i64(a, b, const { int64x1_t([-N as i64; 1]) }) } -} -#[doc = "Shift Right and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v2i32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[rustc_legacy_const_generics(2)] -fn vshiftrins_v2i32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i32")] - fn _vshiftrins_v2i32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t; - } - unsafe { _vshiftrins_v2i32(a, b, const { int32x2_t([-N; 2]) }) } -} -#[doc = "Shift Right and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v2i64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[rustc_legacy_const_generics(2)] -fn vshiftrins_v2i64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i64")] - fn _vshiftrins_v2i64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t; - } - unsafe { _vshiftrins_v2i64(a, b, const { int64x2_t([-N as i64; 2]) }) } -} -#[doc = "Shift Right and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v4i16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[rustc_legacy_const_generics(2)] -fn vshiftrins_v4i16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i16")] - fn _vshiftrins_v4i16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t; - } - unsafe { _vshiftrins_v4i16(a, b, const { int16x4_t([-N as i16; 4]) }) } -} -#[doc = "Shift Right and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v4i32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[rustc_legacy_const_generics(2)] -fn vshiftrins_v4i32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i32")] - fn _vshiftrins_v4i32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t; - } - unsafe { _vshiftrins_v4i32(a, b, const { int32x4_t([-N; 4]) }) } -} -#[doc = "Shift Right and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v8i16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[rustc_legacy_const_generics(2)] -fn vshiftrins_v8i16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i16")] - fn _vshiftrins_v8i16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t; - } - unsafe { _vshiftrins_v8i16(a, b, const { int16x8_t([-N as i16; 8]) }) } -} -#[doc = "Shift Right and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v8i8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[rustc_legacy_const_generics(2)] -fn vshiftrins_v8i8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i8")] - fn _vshiftrins_v8i8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t; - } - unsafe { _vshiftrins_v8i8(a, b, const { int8x8_t([-N as i8; 8]) }) } -} -#[doc = "Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shl, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshl_n_s8(a: int8x8_t) -> int8x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { simd_shl(a, vdup_n_s8(N as _)) } -} -#[doc = "Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shl, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshlq_n_s8(a: int8x16_t) -> int8x16_t { - static_assert_uimm_bits!(N, 3); - unsafe { simd_shl(a, vdupq_n_s8(N as _)) } -} -#[doc = "Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shl, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshl_n_s16(a: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(N, 4); - unsafe { simd_shl(a, vdup_n_s16(N as _)) } -} -#[doc = "Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shl, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshlq_n_s16(a: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(N, 4); - unsafe { simd_shl(a, vdupq_n_s16(N as _)) } -} -#[doc = "Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shl, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshl_n_s32(a: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(N, 5); - unsafe { simd_shl(a, vdup_n_s32(N as _)) } -} -#[doc = "Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shl, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshlq_n_s32(a: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(N, 5); - unsafe { simd_shl(a, vdupq_n_s32(N as _)) } -} -#[doc = "Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shl, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshl_n_s64(a: int64x1_t) -> int64x1_t { - static_assert_uimm_bits!(N, 6); - unsafe { simd_shl(a, vdup_n_s64(N as _)) } -} -#[doc = "Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shl, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshlq_n_s64(a: int64x2_t) -> int64x2_t { - static_assert_uimm_bits!(N, 6); - unsafe { simd_shl(a, vdupq_n_s64(N as _)) } -} -#[doc = "Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shl, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshl_n_u8(a: uint8x8_t) -> uint8x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { simd_shl(a, vdup_n_u8(N as _)) } -} -#[doc = "Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shl, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshlq_n_u8(a: uint8x16_t) -> uint8x16_t { - static_assert_uimm_bits!(N, 3); - unsafe { simd_shl(a, vdupq_n_u8(N as _)) } -} -#[doc = "Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shl, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshl_n_u16(a: uint16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(N, 4); - unsafe { simd_shl(a, vdup_n_u16(N as _)) } -} -#[doc = "Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shl, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshlq_n_u16(a: uint16x8_t) -> uint16x8_t { - static_assert_uimm_bits!(N, 4); - unsafe { simd_shl(a, vdupq_n_u16(N as _)) } -} -#[doc = "Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shl, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshl_n_u32(a: uint32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(N, 5); - unsafe { simd_shl(a, vdup_n_u32(N as _)) } -} -#[doc = "Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shl, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshlq_n_u32(a: uint32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(N, 5); - unsafe { simd_shl(a, vdupq_n_u32(N as _)) } -} -#[doc = "Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shl, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshl_n_u64(a: uint64x1_t) -> uint64x1_t { - static_assert_uimm_bits!(N, 6); - unsafe { simd_shl(a, vdup_n_u64(N as _)) } -} -#[doc = "Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shl, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshlq_n_u64(a: uint64x2_t) -> uint64x2_t { - static_assert_uimm_bits!(N, 6); - unsafe { simd_shl(a, vdupq_n_u64(N as _)) } -} -#[doc = "Signed Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v8i8")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sshl.v8i8" - )] - fn _vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; - } - unsafe { _vshl_s8(a, b) } -} -#[doc = "Signed Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v16i8")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sshl.v16i8" - )] - fn _vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; - } - unsafe { _vshlq_s8(a, b) } -} -#[doc = "Signed Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v4i16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sshl.v4i16" - )] - fn _vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; - } - unsafe { _vshl_s16(a, b) } -} -#[doc = "Signed Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v8i16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sshl.v8i16" - )] - fn _vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; - } - unsafe { _vshlq_s16(a, b) } -} -#[doc = "Signed Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v2i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sshl.v2i32" - )] - fn _vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; - } - unsafe { _vshl_s32(a, b) } -} -#[doc = "Signed Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v4i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sshl.v4i32" - )] - fn _vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; - } - unsafe { _vshlq_s32(a, b) } -} -#[doc = "Signed Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v1i64")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sshl.v1i64" - )] - fn _vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t; - } - unsafe { _vshl_s64(a, b) } -} -#[doc = "Signed Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sshl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v2i64")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sshl.v2i64" - )] - fn _vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; - } - unsafe { _vshlq_s64(a, b) } -} -#[doc = "Unsigned Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ushl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v8i8")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ushl.v8i8" - )] - fn _vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t; - } - unsafe { _vshl_u8(a, b) } -} -#[doc = "Unsigned Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ushl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v16i8")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ushl.v16i8" - )] - fn _vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t; - } - unsafe { _vshlq_u8(a, b) } -} -#[doc = "Unsigned Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ushl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v4i16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ushl.v4i16" - )] - fn _vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t; - } - unsafe { _vshl_u16(a, b) } -} -#[doc = "Unsigned Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ushl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v8i16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ushl.v8i16" - )] - fn _vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t; - } - unsafe { _vshlq_u16(a, b) } -} -#[doc = "Unsigned Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ushl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v2i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ushl.v2i32" - )] - fn _vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t; - } - unsafe { _vshl_u32(a, b) } -} -#[doc = "Unsigned Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ushl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v4i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ushl.v4i32" - )] - fn _vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t; - } - unsafe { _vshlq_u32(a, b) } -} -#[doc = "Unsigned Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ushl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v1i64")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ushl.v1i64" - )] - fn _vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t; - } - unsafe { _vshl_u64(a, b) } -} -#[doc = "Unsigned Shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ushl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v2i64")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ushl.v2i64" - )] - fn _vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t; - } - unsafe { _vshlq_u64(a, b) } -} -#[doc = "Signed shift left long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s16", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sshll, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshll_n_s16(a: int16x4_t) -> int32x4_t { - static_assert!(N >= 0 && N <= 16); - unsafe { simd_shl(simd_cast(a), vdupq_n_s32(N as _)) } -} -#[doc = "Signed shift left long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s32", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sshll, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshll_n_s32(a: int32x2_t) -> int64x2_t { - static_assert!(N >= 0 && N <= 32); - unsafe { simd_shl(simd_cast(a), vdupq_n_s64(N as _)) } -} -#[doc = "Signed shift left long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s8", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sshll, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshll_n_s8(a: int8x8_t) -> int16x8_t { - static_assert!(N >= 0 && N <= 8); - unsafe { simd_shl(simd_cast(a), vdupq_n_s16(N as _)) } -} -#[doc = "Signed shift left long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u16", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ushll, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshll_n_u16(a: uint16x4_t) -> uint32x4_t { - static_assert!(N >= 0 && N <= 16); - unsafe { simd_shl(simd_cast(a), vdupq_n_u32(N as _)) } -} -#[doc = "Signed shift left long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u32", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ushll, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshll_n_u32(a: uint32x2_t) -> uint64x2_t { - static_assert!(N >= 0 && N <= 32); - unsafe { simd_shl(simd_cast(a), vdupq_n_u64(N as _)) } -} -#[doc = "Signed shift left long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u8", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ushll, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshll_n_u8(a: uint8x8_t) -> uint16x8_t { - static_assert!(N >= 0 && N <= 8); - unsafe { simd_shl(simd_cast(a), vdupq_n_u16(N as _)) } -} -#[doc = "Shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshr_n_s8(a: int8x8_t) -> int8x8_t { - static_assert!(N >= 1 && N <= 8); - let n: i32 = if N == 8 { 7 } else { N }; - unsafe { simd_shr(a, vdup_n_s8(n as _)) } -} -#[doc = "Shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshrq_n_s8(a: int8x16_t) -> int8x16_t { - static_assert!(N >= 1 && N <= 8); - let n: i32 = if N == 8 { 7 } else { N }; - unsafe { simd_shr(a, vdupq_n_s8(n as _)) } -} -#[doc = "Shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshr_n_s16(a: int16x4_t) -> int16x4_t { - static_assert!(N >= 1 && N <= 16); - let n: i32 = if N == 16 { 15 } else { N }; - unsafe { simd_shr(a, vdup_n_s16(n as _)) } -} -#[doc = "Shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshrq_n_s16(a: int16x8_t) -> int16x8_t { - static_assert!(N >= 1 && N <= 16); - let n: i32 = if N == 16 { 15 } else { N }; - unsafe { simd_shr(a, vdupq_n_s16(n as _)) } -} -#[doc = "Shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshr_n_s32(a: int32x2_t) -> int32x2_t { - static_assert!(N >= 1 && N <= 32); - let n: i32 = if N == 32 { 31 } else { N }; - unsafe { simd_shr(a, vdup_n_s32(n as _)) } -} -#[doc = "Shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshrq_n_s32(a: int32x4_t) -> int32x4_t { - static_assert!(N >= 1 && N <= 32); - let n: i32 = if N == 32 { 31 } else { N }; - unsafe { simd_shr(a, vdupq_n_s32(n as _)) } -} -#[doc = "Shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshr_n_s64(a: int64x1_t) -> int64x1_t { - static_assert!(N >= 1 && N <= 64); - let n: i32 = if N == 64 { 63 } else { N }; - unsafe { simd_shr(a, vdup_n_s64(n as _)) } -} -#[doc = "Shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sshr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshrq_n_s64(a: int64x2_t) -> int64x2_t { - static_assert!(N >= 1 && N <= 64); - let n: i32 = if N == 64 { 63 } else { N }; - unsafe { simd_shr(a, vdupq_n_s64(n as _)) } -} -#[doc = "Shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ushr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshr_n_u8(a: uint8x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - let n: i32 = if N == 8 { - return vdup_n_u8(0); - } else { - N - }; - unsafe { simd_shr(a, vdup_n_u8(n as _)) } -} -#[doc = "Shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ushr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshrq_n_u8(a: uint8x16_t) -> uint8x16_t { - static_assert!(N >= 1 && N <= 8); - let n: i32 = if N == 8 { - return vdupq_n_u8(0); - } else { - N - }; - unsafe { simd_shr(a, vdupq_n_u8(n as _)) } -} -#[doc = "Shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ushr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshr_n_u16(a: uint16x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - let n: i32 = if N == 16 { - return vdup_n_u16(0); - } else { - N - }; - unsafe { simd_shr(a, vdup_n_u16(n as _)) } -} -#[doc = "Shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ushr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshrq_n_u16(a: uint16x8_t) -> uint16x8_t { - static_assert!(N >= 1 && N <= 16); - let n: i32 = if N == 16 { - return vdupq_n_u16(0); - } else { - N - }; - unsafe { simd_shr(a, vdupq_n_u16(n as _)) } -} -#[doc = "Shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ushr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshr_n_u32(a: uint32x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - let n: i32 = if N == 32 { - return vdup_n_u32(0); - } else { - N - }; - unsafe { simd_shr(a, vdup_n_u32(n as _)) } -} -#[doc = "Shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ushr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshrq_n_u32(a: uint32x4_t) -> uint32x4_t { - static_assert!(N >= 1 && N <= 32); - let n: i32 = if N == 32 { - return vdupq_n_u32(0); - } else { - N - }; - unsafe { simd_shr(a, vdupq_n_u32(n as _)) } -} -#[doc = "Shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ushr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshr_n_u64(a: uint64x1_t) -> uint64x1_t { - static_assert!(N >= 1 && N <= 64); - let n: i32 = if N == 64 { - return vdup_n_u64(0); - } else { - N - }; - unsafe { simd_shr(a, vdup_n_u64(n as _)) } -} -#[doc = "Shift right"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ushr, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshrq_n_u64(a: uint64x2_t) -> uint64x2_t { - static_assert!(N >= 1 && N <= 64); - let n: i32 = if N == 64 { - return vdupq_n_u64(0); - } else { - N - }; - unsafe { simd_shr(a, vdupq_n_u64(n as _)) } -} -#[doc = "Shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shrn, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshrn_n_s16(a: int16x8_t) -> int8x8_t { - static_assert!(N >= 1 && N <= 8); - unsafe { simd_cast(simd_shr(a, vdupq_n_s16(N as _))) } -} -#[doc = "Shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shrn, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshrn_n_s32(a: int32x4_t) -> int16x4_t { - static_assert!(N >= 1 && N <= 16); - unsafe { simd_cast(simd_shr(a, vdupq_n_s32(N as _))) } -} -#[doc = "Shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shrn, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshrn_n_s64(a: int64x2_t) -> int32x2_t { - static_assert!(N >= 1 && N <= 32); - unsafe { simd_cast(simd_shr(a, vdupq_n_s64(N as _))) } -} -#[doc = "Shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shrn, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshrn_n_u16(a: uint16x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - unsafe { simd_cast(simd_shr(a, vdupq_n_u16(N as _))) } -} -#[doc = "Shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shrn, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshrn_n_u32(a: uint32x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - unsafe { simd_cast(simd_shr(a, vdupq_n_u32(N as _))) } -} -#[doc = "Shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shrn, N = 2) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vshrn_n_u64(a: uint64x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - unsafe { simd_cast(simd_shr(a, vdupq_n_u64(N as _))) } -} -#[doc = "Shift Left and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s8)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsli_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - static_assert_uimm_bits!(N, 3); - vshiftlins_v8i8::(a, b) -} -#[doc = "Shift Left and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s8)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsliq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - static_assert_uimm_bits!(N, 3); - vshiftlins_v16i8::(a, b) -} -#[doc = "Shift Left and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s16)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsli_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(N, 4); - vshiftlins_v4i16::(a, b) -} -#[doc = "Shift Left and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s16)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsliq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(N, 4); - vshiftlins_v8i16::(a, b) -} -#[doc = "Shift Left and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s32)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsli_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - static_assert!(N >= 0 && N <= 31); - vshiftlins_v2i32::(a, b) -} -#[doc = "Shift Left and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s32)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsliq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - static_assert!(N >= 0 && N <= 31); - vshiftlins_v4i32::(a, b) -} -#[doc = "Shift Left and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s64)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsli_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - static_assert!(N >= 0 && N <= 63); - vshiftlins_v1i64::(a, b) -} -#[doc = "Shift Left and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s64)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsliq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - static_assert!(N >= 0 && N <= 63); - vshiftlins_v2i64::(a, b) -} -#[doc = "Shift Left and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u8)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsli_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { transmute(vshiftlins_v8i8::(transmute(a), transmute(b))) } -} -#[doc = "Shift Left and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u8)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsliq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - static_assert_uimm_bits!(N, 3); - unsafe { transmute(vshiftlins_v16i8::(transmute(a), transmute(b))) } -} -#[doc = "Shift Left and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u16)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsli_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(N, 4); - unsafe { transmute(vshiftlins_v4i16::(transmute(a), transmute(b))) } -} -#[doc = "Shift Left and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u16)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsliq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - static_assert_uimm_bits!(N, 4); - unsafe { transmute(vshiftlins_v8i16::(transmute(a), transmute(b))) } -} -#[doc = "Shift Left and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u32)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsli_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - static_assert!(N >= 0 && N <= 31); - unsafe { transmute(vshiftlins_v2i32::(transmute(a), transmute(b))) } -} -#[doc = "Shift Left and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u32)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsliq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - static_assert!(N >= 0 && N <= 31); - unsafe { transmute(vshiftlins_v4i32::(transmute(a), transmute(b))) } -} -#[doc = "Shift Left and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u64)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsli_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - static_assert!(N >= 0 && N <= 63); - unsafe { transmute(vshiftlins_v1i64::(transmute(a), transmute(b))) } -} -#[doc = "Shift Left and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u64)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsliq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - static_assert!(N >= 0 && N <= 63); - unsafe { transmute(vshiftlins_v2i64::(transmute(a), transmute(b))) } -} -#[doc = "Shift Left and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p8)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsli_n_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { transmute(vshiftlins_v8i8::(transmute(a), transmute(b))) } -} -#[doc = "Shift Left and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p8)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsliq_n_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { - static_assert_uimm_bits!(N, 3); - unsafe { transmute(vshiftlins_v16i8::(transmute(a), transmute(b))) } -} -#[doc = "Shift Left and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p16)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsli_n_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { - static_assert_uimm_bits!(N, 4); - unsafe { transmute(vshiftlins_v4i16::(transmute(a), transmute(b))) } -} -#[doc = "Shift Left and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p16)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsliq_n_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { - static_assert_uimm_bits!(N, 4); - unsafe { transmute(vshiftlins_v8i16::(transmute(a), transmute(b))) } -} -#[doc = "Signed shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ssra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsra_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - static_assert!(N >= 1 && N <= 8); - unsafe { simd_add(a, vshr_n_s8::(b)) } -} -#[doc = "Signed shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ssra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsraq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - static_assert!(N >= 1 && N <= 8); - unsafe { simd_add(a, vshrq_n_s8::(b)) } -} -#[doc = "Signed shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ssra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsra_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - static_assert!(N >= 1 && N <= 16); - unsafe { simd_add(a, vshr_n_s16::(b)) } -} -#[doc = "Signed shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ssra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsraq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - static_assert!(N >= 1 && N <= 16); - unsafe { simd_add(a, vshrq_n_s16::(b)) } -} -#[doc = "Signed shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ssra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsra_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - static_assert!(N >= 1 && N <= 32); - unsafe { simd_add(a, vshr_n_s32::(b)) } -} -#[doc = "Signed shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ssra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsraq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - static_assert!(N >= 1 && N <= 32); - unsafe { simd_add(a, vshrq_n_s32::(b)) } -} -#[doc = "Signed shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ssra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsra_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - static_assert!(N >= 1 && N <= 64); - unsafe { simd_add(a, vshr_n_s64::(b)) } -} -#[doc = "Signed shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ssra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsraq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - static_assert!(N >= 1 && N <= 64); - unsafe { simd_add(a, vshrq_n_s64::(b)) } -} -#[doc = "Unsigned shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsra_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - unsafe { simd_add(a, vshr_n_u8::(b)) } -} -#[doc = "Unsigned shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsraq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - static_assert!(N >= 1 && N <= 8); - unsafe { simd_add(a, vshrq_n_u8::(b)) } -} -#[doc = "Unsigned shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsra_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - unsafe { simd_add(a, vshr_n_u16::(b)) } -} -#[doc = "Unsigned shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsraq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - static_assert!(N >= 1 && N <= 16); - unsafe { simd_add(a, vshrq_n_u16::(b)) } -} -#[doc = "Unsigned shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsra_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - unsafe { simd_add(a, vshr_n_u32::(b)) } -} -#[doc = "Unsigned shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsraq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - static_assert!(N >= 1 && N <= 32); - unsafe { simd_add(a, vshrq_n_u32::(b)) } -} -#[doc = "Unsigned shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsra_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - static_assert!(N >= 1 && N <= 64); - unsafe { simd_add(a, vshr_n_u64::(b)) } -} -#[doc = "Unsigned shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usra, N = 2) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsraq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - static_assert!(N >= 1 && N <= 64); - unsafe { simd_add(a, vshrq_n_u64::(b)) } -} -#[doc = "Shift Right and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s8)"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsri_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - static_assert!(1 <= N && N <= 8); - vshiftrins_v8i8::(a, b) -} -#[doc = "Shift Right and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsriq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - static_assert!(1 <= N && N <= 8); - vshiftrins_v16i8::(a, b) -} -#[doc = "Shift Right and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsri_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - static_assert!(1 <= N && N <= 16); - vshiftrins_v4i16::(a, b) -} -#[doc = "Shift Right and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsriq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - static_assert!(1 <= N && N <= 16); - vshiftrins_v8i16::(a, b) -} -#[doc = "Shift Right and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsri_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - static_assert!(1 <= N && N <= 32); - vshiftrins_v2i32::(a, b) -} -#[doc = "Shift Right and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsriq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - static_assert!(1 <= N && N <= 32); - vshiftrins_v4i32::(a, b) -} -#[doc = "Shift Right and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsri_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - static_assert!(1 <= N && N <= 64); - vshiftrins_v1i64::(a, b) -} -#[doc = "Shift Right and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsriq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - static_assert!(1 <= N && N <= 64); - vshiftrins_v2i64::(a, b) -} -#[doc = "Shift Right and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsri_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - static_assert!(1 <= N && N <= 8); - unsafe { transmute(vshiftrins_v8i8::(transmute(a), transmute(b))) } -} -#[doc = "Shift Right and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u8)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsriq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - static_assert!(1 <= N && N <= 8); - unsafe { transmute(vshiftrins_v16i8::(transmute(a), transmute(b))) } -} -#[doc = "Shift Right and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u16)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsri_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - static_assert!(1 <= N && N <= 16); - unsafe { transmute(vshiftrins_v4i16::(transmute(a), transmute(b))) } -} -#[doc = "Shift Right and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u16)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsriq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - static_assert!(1 <= N && N <= 16); - unsafe { transmute(vshiftrins_v8i16::(transmute(a), transmute(b))) } -} -#[doc = "Shift Right and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u32)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))] -#[rustc_legacy_const_generics(2)] -pub fn vsri_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - static_assert!(1 <= N && N <= 32); - unsafe { transmute(vshiftrins_v2i32::(transmute(a), transmute(b))) } +#[doc = "Shift Right and Insert (immediate)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u32)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))] +#[rustc_legacy_const_generics(2)] +pub fn vsri_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + static_assert!(1 <= N && N <= 32); + unsafe { transmute(vshiftrins_v2i32::(transmute(a), transmute(b))) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -65011,7 +57663,7 @@ pub fn vsriq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u64)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -65023,7 +57675,7 @@ pub fn vsri_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u64)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -65035,7 +57687,7 @@ pub fn vsriq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p8)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -65047,7 +57699,7 @@ pub fn vsri_n_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p8)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -65059,7 +57711,7 @@ pub fn vsriq_n_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p16)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -65071,7 +57723,7 @@ pub fn vsri_n_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p16)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -65085,7 +57737,7 @@ pub fn vsriq_n_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[target_feature(enable = "neon,fp16")] @@ -65103,7 +57755,7 @@ pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[target_feature(enable = "neon,fp16")] @@ -65121,7 +57773,7 @@ pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(test, assert_instr(vst1))] @@ -65139,7 +57791,7 @@ pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(test, assert_instr(vst1))] @@ -65157,7 +57809,7 @@ pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] #[target_feature(enable = "neon,fp16")] @@ -65177,7 +57829,7 @@ pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] #[target_feature(enable = "neon,fp16")] @@ -65197,7 +57849,7 @@ pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(test, assert_instr(vst1))] @@ -65215,7 +57867,7 @@ pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(test, assert_instr(vst1))] @@ -65233,7 +57885,7 @@ pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] #[target_feature(enable = "neon,fp16")] @@ -65253,7 +57905,7 @@ pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] #[target_feature(enable = "neon,fp16")] @@ -65273,7 +57925,7 @@ pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65298,7 +57950,7 @@ pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65323,7 +57975,7 @@ pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] #[target_feature(enable = "neon,fp16")] @@ -65349,7 +58001,7 @@ pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] #[target_feature(enable = "neon,fp16")] @@ -65375,7 +58027,7 @@ pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65389,7 +58041,7 @@ pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65403,7 +58055,7 @@ pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65417,7 +58069,7 @@ pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65431,7 +58083,7 @@ pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65445,7 +58097,7 @@ pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65459,7 +58111,7 @@ pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65473,7 +58125,7 @@ pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65487,7 +58139,7 @@ pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65501,7 +58153,7 @@ pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65515,7 +58167,7 @@ pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65529,7 +58181,7 @@ pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65543,7 +58195,7 @@ pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65557,7 +58209,7 @@ pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65571,7 +58223,7 @@ pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65585,7 +58237,7 @@ pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65599,7 +58251,7 @@ pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65613,7 +58265,7 @@ pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65627,7 +58279,7 @@ pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65641,7 +58293,7 @@ pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65655,7 +58307,7 @@ pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65669,7 +58321,7 @@ pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65683,7 +58335,7 @@ pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65697,7 +58349,7 @@ pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65711,7 +58363,7 @@ pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst1))] @@ -65727,7 +58379,7 @@ pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst1))] @@ -65743,7 +58395,7 @@ pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -65762,7 +58414,7 @@ pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -65781,7 +58433,7 @@ pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -65800,7 +58452,7 @@ pub unsafe fn vst1_f32_x3(a: *mut f32, b: float32x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -65819,7 +58471,7 @@ pub unsafe fn vst1q_f32_x3(a: *mut f32, b: float32x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -65841,7 +58493,7 @@ pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -65863,7 +58515,7 @@ pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -65888,7 +58540,7 @@ pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -65913,7 +58565,7 @@ pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -65933,7 +58585,7 @@ pub unsafe fn vst1_lane_f16(a: *mut f16, b: float16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -65953,7 +58605,7 @@ pub unsafe fn vst1q_lane_f16(a: *mut f16, b: float16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -65978,7 +58630,7 @@ pub unsafe fn vst1_lane_f32(a: *mut f32, b: float32x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -66003,7 +58655,7 @@ pub unsafe fn vst1q_lane_f32(a: *mut f32, b: float32x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -66028,7 +58680,7 @@ pub unsafe fn vst1_lane_s8(a: *mut i8, b: int8x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -66053,7 +58705,7 @@ pub unsafe fn vst1q_lane_s8(a: *mut i8, b: int8x16_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -66078,7 +58730,7 @@ pub unsafe fn vst1_lane_s16(a: *mut i16, b: int16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -66103,7 +58755,7 @@ pub unsafe fn vst1q_lane_s16(a: *mut i16, b: int16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -66128,7 +58780,7 @@ pub unsafe fn vst1_lane_s32(a: *mut i32, b: int32x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -66153,7 +58805,7 @@ pub unsafe fn vst1q_lane_s32(a: *mut i32, b: int32x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -66178,7 +58830,7 @@ pub unsafe fn vst1q_lane_s64(a: *mut i64, b: int64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -66203,7 +58855,7 @@ pub unsafe fn vst1_lane_u8(a: *mut u8, b: uint8x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -66228,7 +58880,7 @@ pub unsafe fn vst1q_lane_u8(a: *mut u8, b: uint8x16_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -66253,7 +58905,7 @@ pub unsafe fn vst1_lane_u16(a: *mut u16, b: uint16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -66278,7 +58930,7 @@ pub unsafe fn vst1q_lane_u16(a: *mut u16, b: uint16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -66303,7 +58955,7 @@ pub unsafe fn vst1_lane_u32(a: *mut u32, b: uint32x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -66328,7 +58980,7 @@ pub unsafe fn vst1q_lane_u32(a: *mut u32, b: uint32x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -66353,7 +59005,7 @@ pub unsafe fn vst1q_lane_u64(a: *mut u64, b: uint64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -66378,7 +59030,7 @@ pub unsafe fn vst1_lane_p8(a: *mut p8, b: poly8x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -66403,7 +59055,7 @@ pub unsafe fn vst1q_lane_p8(a: *mut p8, b: poly8x16_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -66428,7 +59080,7 @@ pub unsafe fn vst1_lane_p16(a: *mut p16, b: poly16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -66453,7 +59105,7 @@ pub unsafe fn vst1q_lane_p16(a: *mut p16, b: poly16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,aes")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -66478,7 +59130,7 @@ pub unsafe fn vst1_lane_p64(a: *mut p64, b: poly64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -66503,7 +59155,7 @@ pub unsafe fn vst1_lane_s64(a: *mut i64, b: int64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -66528,7 +59180,7 @@ pub unsafe fn vst1_lane_u64(a: *mut u64, b: uint64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -66551,7 +59203,7 @@ pub unsafe fn vst1_p64_x2(a: *mut p64, b: poly64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -66574,7 +59226,7 @@ pub unsafe fn vst1_p64_x3(a: *mut p64, b: poly64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -66597,7 +59249,7 @@ pub unsafe fn vst1_p64_x4(a: *mut p64, b: poly64x1x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -66620,7 +59272,7 @@ pub unsafe fn vst1q_p64_x2(a: *mut p64, b: poly64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -66643,7 +59295,7 @@ pub unsafe fn vst1q_p64_x3(a: *mut p64, b: poly64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -66666,7 +59318,7 @@ pub unsafe fn vst1q_p64_x4(a: *mut p64, b: poly64x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -66685,7 +59337,7 @@ pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -66704,7 +59356,7 @@ pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -66723,7 +59375,7 @@ pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -66742,7 +59394,7 @@ pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -66761,7 +59413,7 @@ pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -66780,7 +59432,7 @@ pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -66799,7 +59451,7 @@ pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -66818,7 +59470,7 @@ pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -66834,7 +59486,7 @@ pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -66850,7 +59502,7 @@ pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -66866,7 +59518,7 @@ pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -66882,7 +59534,7 @@ pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -66898,7 +59550,7 @@ pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -66914,7 +59566,7 @@ pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -66930,7 +59582,7 @@ pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -66946,7 +59598,7 @@ pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -66965,7 +59617,7 @@ pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -66984,7 +59636,7 @@ pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -67003,7 +59655,7 @@ pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -67022,7 +59674,7 @@ pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -67041,7 +59693,7 @@ pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -67060,7 +59712,7 @@ pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -67079,7 +59731,7 @@ pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -67098,7 +59750,7 @@ pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67114,7 +59766,7 @@ pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67130,7 +59782,7 @@ pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67146,7 +59798,7 @@ pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67162,7 +59814,7 @@ pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67178,7 +59830,7 @@ pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67194,7 +59846,7 @@ pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67210,7 +59862,7 @@ pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67226,7 +59878,7 @@ pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -67245,7 +59897,7 @@ pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -67264,7 +59916,7 @@ pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -67283,7 +59935,7 @@ pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -67302,7 +59954,7 @@ pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -67321,7 +59973,7 @@ pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -67340,7 +59992,7 @@ pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -67359,7 +60011,7 @@ pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -67378,7 +60030,7 @@ pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67394,7 +60046,7 @@ pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67410,7 +60062,7 @@ pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67426,7 +60078,7 @@ pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67442,7 +60094,7 @@ pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67458,7 +60110,7 @@ pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67474,7 +60126,7 @@ pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67490,7 +60142,7 @@ pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67506,7 +60158,7 @@ pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -67529,7 +60181,7 @@ pub unsafe fn vst1_u8_x2(a: *mut u8, b: uint8x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -67552,7 +60204,7 @@ pub unsafe fn vst1_u8_x3(a: *mut u8, b: uint8x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -67575,7 +60227,7 @@ pub unsafe fn vst1_u8_x4(a: *mut u8, b: uint8x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -67598,7 +60250,7 @@ pub unsafe fn vst1q_u8_x2(a: *mut u8, b: uint8x16x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -67621,7 +60273,7 @@ pub unsafe fn vst1q_u8_x3(a: *mut u8, b: uint8x16x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -67644,7 +60296,7 @@ pub unsafe fn vst1q_u8_x4(a: *mut u8, b: uint8x16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -67667,7 +60319,7 @@ pub unsafe fn vst1_u16_x2(a: *mut u16, b: uint16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -67690,7 +60342,7 @@ pub unsafe fn vst1_u16_x3(a: *mut u16, b: uint16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -67713,7 +60365,7 @@ pub unsafe fn vst1_u16_x4(a: *mut u16, b: uint16x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -67736,7 +60388,7 @@ pub unsafe fn vst1q_u16_x2(a: *mut u16, b: uint16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -67759,7 +60411,7 @@ pub unsafe fn vst1q_u16_x3(a: *mut u16, b: uint16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -67782,7 +60434,7 @@ pub unsafe fn vst1q_u16_x4(a: *mut u16, b: uint16x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -67805,7 +60457,7 @@ pub unsafe fn vst1_u32_x2(a: *mut u32, b: uint32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -67828,7 +60480,7 @@ pub unsafe fn vst1_u32_x3(a: *mut u32, b: uint32x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -67851,7 +60503,7 @@ pub unsafe fn vst1_u32_x4(a: *mut u32, b: uint32x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -67874,7 +60526,7 @@ pub unsafe fn vst1q_u32_x2(a: *mut u32, b: uint32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -67897,7 +60549,7 @@ pub unsafe fn vst1q_u32_x3(a: *mut u32, b: uint32x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -67920,7 +60572,7 @@ pub unsafe fn vst1q_u32_x4(a: *mut u32, b: uint32x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -67943,7 +60595,7 @@ pub unsafe fn vst1_u64_x2(a: *mut u64, b: uint64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -67966,7 +60618,7 @@ pub unsafe fn vst1_u64_x3(a: *mut u64, b: uint64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -67989,7 +60641,7 @@ pub unsafe fn vst1_u64_x4(a: *mut u64, b: uint64x1x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -68012,7 +60664,7 @@ pub unsafe fn vst1q_u64_x2(a: *mut u64, b: uint64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -68035,7 +60687,7 @@ pub unsafe fn vst1q_u64_x3(a: *mut u64, b: uint64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -68058,7 +60710,7 @@ pub unsafe fn vst1q_u64_x4(a: *mut u64, b: uint64x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -68081,7 +60733,7 @@ pub unsafe fn vst1_p8_x2(a: *mut p8, b: poly8x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -68104,7 +60756,7 @@ pub unsafe fn vst1_p8_x3(a: *mut p8, b: poly8x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -68127,7 +60779,7 @@ pub unsafe fn vst1_p8_x4(a: *mut p8, b: poly8x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -68150,7 +60802,7 @@ pub unsafe fn vst1q_p8_x2(a: *mut p8, b: poly8x16x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -68173,7 +60825,7 @@ pub unsafe fn vst1q_p8_x3(a: *mut p8, b: poly8x16x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -68196,7 +60848,7 @@ pub unsafe fn vst1q_p8_x4(a: *mut p8, b: poly8x16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -68219,7 +60871,7 @@ pub unsafe fn vst1_p16_x2(a: *mut p16, b: poly16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -68242,7 +60894,7 @@ pub unsafe fn vst1_p16_x3(a: *mut p16, b: poly16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -68265,7 +60917,7 @@ pub unsafe fn vst1_p16_x4(a: *mut p16, b: poly16x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -68288,7 +60940,7 @@ pub unsafe fn vst1q_p16_x2(a: *mut p16, b: poly16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -68311,7 +60963,7 @@ pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -68330,7 +60982,7 @@ pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) { pub unsafe fn vst1q_p16_x4(a: *mut p16, b: poly16x8x4_t) { vst1q_s16_x4(transmute(a), transmute(b)) } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68344,7 +60996,7 @@ unsafe fn vst1_v1i64(addr: *const i8, val: int64x1_t) { } _vst1_v1i64(addr, val, ALIGN) } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68358,7 +61010,7 @@ unsafe fn vst1_v2f32(addr: *const i8, val: float32x2_t) { } _vst1_v2f32(addr, val, ALIGN) } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68372,7 +61024,7 @@ unsafe fn vst1_v2i32(addr: *const i8, val: int32x2_t) { } _vst1_v2i32(addr, val, ALIGN) } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68386,7 +61038,7 @@ unsafe fn vst1_v4i16(addr: *const i8, val: int16x4_t) { } _vst1_v4i16(addr, val, ALIGN) } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68400,7 +61052,7 @@ unsafe fn vst1_v8i8(addr: *const i8, val: int8x8_t) { } _vst1_v8i8(addr, val, ALIGN) } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68414,7 +61066,7 @@ unsafe fn vst1q_v16i8(addr: *const i8, val: int8x16_t) { } _vst1q_v16i8(addr, val, ALIGN) } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68428,7 +61080,7 @@ unsafe fn vst1q_v2i64(addr: *const i8, val: int64x2_t) { } _vst1q_v2i64(addr, val, ALIGN) } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68442,7 +61094,7 @@ unsafe fn vst1q_v4f32(addr: *const i8, val: float32x4_t) { } _vst1q_v4f32(addr, val, ALIGN) } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68456,7 +61108,7 @@ unsafe fn vst1q_v4i32(addr: *const i8, val: int32x4_t) { } _vst1q_v4i32(addr, val, ALIGN) } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68474,7 +61126,7 @@ unsafe fn vst1q_v8i16(addr: *const i8, val: int16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v4f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[target_feature(enable = "neon,fp16")] @@ -68492,7 +61144,7 @@ unsafe fn vst1_v4f16(addr: *const i8, val: float16x4_t, align: i32) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v8f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[target_feature(enable = "neon,fp16")] @@ -68510,7 +61162,7 @@ unsafe fn vst1q_v8f16(addr: *const i8, val: float16x8_t, align: i32) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,aes")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -68535,7 +61187,7 @@ pub unsafe fn vst1q_lane_p64(a: *mut p64, b: poly64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] @@ -68556,7 +61208,7 @@ pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] @@ -68577,7 +61229,7 @@ pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68596,7 +61248,7 @@ pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68615,159 +61267,103 @@ pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v2f32.p0" - )] - fn _vst2_f32(a: float32x2_t, b: float32x2_t, ptr: *mut i8); - } - _vst2_f32(b.0, b.1, a as _) + crate::core_arch::macros::interleaving_store!(f32, 2, 2, a, b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v4f32.p0" - )] - fn _vst2q_f32(a: float32x4_t, b: float32x4_t, ptr: *mut i8); - } - _vst2q_f32(b.0, b.1, a as _) + crate::core_arch::macros::interleaving_store!(f32, 4, 2, a, b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v8i8.p0" - )] - fn _vst2_s8(a: int8x8_t, b: int8x8_t, ptr: *mut i8); - } - _vst2_s8(b.0, b.1, a as _) + crate::core_arch::macros::interleaving_store!(i8, 8, 2, a, b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v16i8.p0" - )] - fn _vst2q_s8(a: int8x16_t, b: int8x16_t, ptr: *mut i8); - } - _vst2q_s8(b.0, b.1, a as _) + crate::core_arch::macros::interleaving_store!(i8, 16, 2, a, b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v4i16.p0" - )] - fn _vst2_s16(a: int16x4_t, b: int16x4_t, ptr: *mut i8); - } - _vst2_s16(b.0, b.1, a as _) + crate::core_arch::macros::interleaving_store!(i16, 4, 2, a, b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v8i16.p0" - )] - fn _vst2q_s16(a: int16x8_t, b: int16x8_t, ptr: *mut i8); - } - _vst2q_s16(b.0, b.1, a as _) + crate::core_arch::macros::interleaving_store!(i16, 8, 2, a, b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v2i32.p0" - )] - fn _vst2_s32(a: int32x2_t, b: int32x2_t, ptr: *mut i8); - } - _vst2_s32(b.0, b.1, a as _) + crate::core_arch::macros::interleaving_store!(i32, 2, 2, a, b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v4i32.p0" - )] - fn _vst2q_s32(a: int32x4_t, b: int32x4_t, ptr: *mut i8); - } - _vst2q_s32(b.0, b.1, a as _) + crate::core_arch::macros::interleaving_store!(i32, 4, 2, a, b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -68783,7 +61379,7 @@ pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -68799,7 +61395,7 @@ pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -68815,7 +61411,7 @@ pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -68831,7 +61427,7 @@ pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -68847,7 +61443,7 @@ pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -68863,7 +61459,7 @@ pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -68879,7 +61475,7 @@ pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -68895,7 +61491,7 @@ pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -68918,7 +61514,7 @@ pub unsafe fn vst2_lane_f16(a: *mut f16, b: float16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -68941,7 +61537,7 @@ pub unsafe fn vst2q_lane_f16(a: *mut f16, b: float16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68962,7 +61558,7 @@ pub unsafe fn vst2_lane_f16(a: *mut f16, b: float16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68972,7 +61568,7 @@ pub unsafe fn vst2_lane_f16(a: *mut f16, b: float16x4x2_t) { #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub unsafe fn vst2q_lane_f16(a: *mut f16, b: float16x8x2_t) { - static_assert_uimm_bits!(LANE, 1); + static_assert_uimm_bits!(LANE, 3); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0.v8f16")] fn _vst2q_lane_f16(ptr: *mut i8, a: float16x8_t, b: float16x8_t, n: i32, size: i32); @@ -68983,7 +61579,7 @@ pub unsafe fn vst2q_lane_f16(a: *mut f16, b: float16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -69004,7 +61600,7 @@ pub unsafe fn vst2_lane_f32(a: *mut f32, b: float32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -69025,7 +61621,7 @@ pub unsafe fn vst2q_lane_f32(a: *mut f32, b: float32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -69046,7 +61642,7 @@ pub unsafe fn vst2_lane_s8(a: *mut i8, b: int8x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -69067,7 +61663,7 @@ pub unsafe fn vst2_lane_s16(a: *mut i16, b: int16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -69088,7 +61684,7 @@ pub unsafe fn vst2q_lane_s16(a: *mut i16, b: int16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -69109,7 +61705,7 @@ pub unsafe fn vst2_lane_s32(a: *mut i32, b: int32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -69130,7 +61726,7 @@ pub unsafe fn vst2q_lane_s32(a: *mut i32, b: int32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst2, LANE = 0))] @@ -69148,7 +61744,7 @@ pub unsafe fn vst2_lane_f32(a: *mut f32, b: float32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst2, LANE = 0))] @@ -69166,7 +61762,7 @@ pub unsafe fn vst2q_lane_f32(a: *mut f32, b: float32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst2, LANE = 0))] @@ -69184,7 +61780,7 @@ pub unsafe fn vst2_lane_s8(a: *mut i8, b: int8x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst2, LANE = 0))] @@ -69202,7 +61798,7 @@ pub unsafe fn vst2_lane_s16(a: *mut i16, b: int16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst2, LANE = 0))] @@ -69220,7 +61816,7 @@ pub unsafe fn vst2q_lane_s16(a: *mut i16, b: int16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst2, LANE = 0))] @@ -69238,7 +61834,7 @@ pub unsafe fn vst2_lane_s32(a: *mut i32, b: int32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst2, LANE = 0))] @@ -69256,7 +61852,7 @@ pub unsafe fn vst2q_lane_s32(a: *mut i32, b: int32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] @@ -69281,7 +61877,7 @@ pub unsafe fn vst2_lane_u8(a: *mut u8, b: uint8x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] @@ -69306,7 +61902,7 @@ pub unsafe fn vst2_lane_u16(a: *mut u16, b: uint16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] @@ -69331,7 +61927,7 @@ pub unsafe fn vst2q_lane_u16(a: *mut u16, b: uint16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] @@ -69356,7 +61952,7 @@ pub unsafe fn vst2_lane_u32(a: *mut u32, b: uint32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] @@ -69381,7 +61977,7 @@ pub unsafe fn vst2q_lane_u32(a: *mut u32, b: uint32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] @@ -69406,7 +62002,7 @@ pub unsafe fn vst2_lane_p8(a: *mut p8, b: poly8x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] @@ -69431,7 +62027,7 @@ pub unsafe fn vst2_lane_p16(a: *mut p16, b: poly16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] @@ -69456,7 +62052,7 @@ pub unsafe fn vst2q_lane_p16(a: *mut p16, b: poly16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,aes")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -69479,42 +62075,31 @@ pub unsafe fn vst2_p64(a: *mut p64, b: poly64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v1i64.p0")] - fn _vst2_s64(ptr: *mut i8, a: int64x1_t, b: int64x1_t, size: i32); - } - _vst2_s64(a as _, b.0, b.1, 8) + core::ptr::write_unaligned(a.cast(), b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v1i64.p0" - )] - fn _vst2_s64(a: int64x1_t, b: int64x1_t, ptr: *mut i8); - } - _vst2_s64(b.0, b.1, a as _) + core::ptr::write_unaligned(a.cast(), b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -69537,7 +62122,7 @@ pub unsafe fn vst2_u64(a: *mut u64, b: uint64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] @@ -69560,7 +62145,7 @@ pub unsafe fn vst2_u8(a: *mut u8, b: uint8x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] @@ -69583,7 +62168,7 @@ pub unsafe fn vst2q_u8(a: *mut u8, b: uint8x16x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] @@ -69606,7 +62191,7 @@ pub unsafe fn vst2_u16(a: *mut u16, b: uint16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] @@ -69629,7 +62214,7 @@ pub unsafe fn vst2q_u16(a: *mut u16, b: uint16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] @@ -69652,7 +62237,7 @@ pub unsafe fn vst2_u32(a: *mut u32, b: uint32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] @@ -69675,7 +62260,7 @@ pub unsafe fn vst2q_u32(a: *mut u32, b: uint32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] @@ -69698,7 +62283,7 @@ pub unsafe fn vst2_p8(a: *mut p8, b: poly8x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] @@ -69721,7 +62306,7 @@ pub unsafe fn vst2q_p8(a: *mut p8, b: poly8x16x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] @@ -69744,7 +62329,7 @@ pub unsafe fn vst2_p16(a: *mut p16, b: poly16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] @@ -69767,7 +62352,7 @@ pub unsafe fn vst2q_p16(a: *mut p16, b: poly16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69786,7 +62371,7 @@ pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69805,7 +62390,7 @@ pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] @@ -69826,7 +62411,7 @@ pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] @@ -69847,287 +62432,199 @@ pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vst3))] pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v2f32")] - fn _vst3_f32(ptr: *mut i8, a: float32x2_t, b: float32x2_t, c: float32x2_t, size: i32); - } - _vst3_f32(a as _, b.0, b.1, b.2, 4) + crate::core_arch::macros::interleaving_store!(f32, 2, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vst3))] pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v4f32")] - fn _vst3q_f32(ptr: *mut i8, a: float32x4_t, b: float32x4_t, c: float32x4_t, size: i32); - } - _vst3q_f32(a as _, b.0, b.1, b.2, 4) + crate::core_arch::macros::interleaving_store!(f32, 4, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vst3))] pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v8i8")] - fn _vst3_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, size: i32); - } - _vst3_s8(a as _, b.0, b.1, b.2, 1) + crate::core_arch::macros::interleaving_store!(i8, 8, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vst3))] pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v16i8")] - fn _vst3q_s8(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t, size: i32); - } - _vst3q_s8(a as _, b.0, b.1, b.2, 1) + crate::core_arch::macros::interleaving_store!(i8, 16, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vst3))] pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v4i16")] - fn _vst3_s16(ptr: *mut i8, a: int16x4_t, b: int16x4_t, c: int16x4_t, size: i32); - } - _vst3_s16(a as _, b.0, b.1, b.2, 2) + crate::core_arch::macros::interleaving_store!(i16, 4, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vst3))] pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v8i16")] - fn _vst3q_s16(ptr: *mut i8, a: int16x8_t, b: int16x8_t, c: int16x8_t, size: i32); - } - _vst3q_s16(a as _, b.0, b.1, b.2, 2) + crate::core_arch::macros::interleaving_store!(i16, 8, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vst3))] pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v2i32")] - fn _vst3_s32(ptr: *mut i8, a: int32x2_t, b: int32x2_t, c: int32x2_t, size: i32); - } - _vst3_s32(a as _, b.0, b.1, b.2, 4) + crate::core_arch::macros::interleaving_store!(i32, 2, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vst3))] pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v4i32")] - fn _vst3q_s32(ptr: *mut i8, a: int32x4_t, b: int32x4_t, c: int32x4_t, size: i32); - } - _vst3q_s32(a as _, b.0, b.1, b.2, 4) + crate::core_arch::macros::interleaving_store!(i32, 4, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v2f32.p0" - )] - fn _vst3_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, ptr: *mut i8); - } - _vst3_f32(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(f32, 2, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v4f32.p0" - )] - fn _vst3q_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, ptr: *mut i8); - } - _vst3q_f32(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(f32, 4, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v8i8.p0" - )] - fn _vst3_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, ptr: *mut i8); - } - _vst3_s8(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(i8, 8, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v16i8.p0" - )] - fn _vst3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t, ptr: *mut i8); - } - _vst3q_s8(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(i8, 16, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v4i16.p0" - )] - fn _vst3_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, ptr: *mut i8); - } - _vst3_s16(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(i16, 4, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v8i16.p0" - )] - fn _vst3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, ptr: *mut i8); - } - _vst3q_s16(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(i16, 8, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v2i32.p0" - )] - fn _vst3_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, ptr: *mut i8); - } - _vst3_s32(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(i32, 2, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v4i32.p0" - )] - fn _vst3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, ptr: *mut i8); - } - _vst3q_s32(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(i32, 4, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70155,7 +62652,7 @@ pub unsafe fn vst3_lane_f16(a: *mut f16, b: float16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70183,7 +62680,7 @@ pub unsafe fn vst3q_lane_f16(a: *mut f16, b: float16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -70206,7 +62703,7 @@ pub unsafe fn vst3_lane_f16(a: *mut f16, b: float16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -70229,7 +62726,7 @@ pub unsafe fn vst3q_lane_f16(a: *mut f16, b: float16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst3, LANE = 0))] @@ -70254,7 +62751,7 @@ pub unsafe fn vst3_lane_f32(a: *mut f32, b: float32x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst3, LANE = 0))] @@ -70279,7 +62776,7 @@ pub unsafe fn vst3q_lane_f32(a: *mut f32, b: float32x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst3, LANE = 0))] @@ -70297,7 +62794,7 @@ pub unsafe fn vst3_lane_s8(a: *mut i8, b: int8x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst3, LANE = 0))] @@ -70322,7 +62819,7 @@ pub unsafe fn vst3_lane_s16(a: *mut i16, b: int16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst3, LANE = 0))] @@ -70347,7 +62844,7 @@ pub unsafe fn vst3q_lane_s16(a: *mut i16, b: int16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst3, LANE = 0))] @@ -70372,7 +62869,7 @@ pub unsafe fn vst3_lane_s32(a: *mut i32, b: int32x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst3, LANE = 0))] @@ -70397,7 +62894,7 @@ pub unsafe fn vst3q_lane_s32(a: *mut i32, b: int32x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -70418,7 +62915,7 @@ pub unsafe fn vst3_lane_f32(a: *mut f32, b: float32x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -70439,7 +62936,7 @@ pub unsafe fn vst3q_lane_f32(a: *mut f32, b: float32x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -70460,7 +62957,7 @@ pub unsafe fn vst3_lane_s8(a: *mut i8, b: int8x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -70481,7 +62978,7 @@ pub unsafe fn vst3_lane_s16(a: *mut i16, b: int16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -70502,7 +62999,7 @@ pub unsafe fn vst3q_lane_s16(a: *mut i16, b: int16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -70523,7 +63020,7 @@ pub unsafe fn vst3_lane_s32(a: *mut i32, b: int32x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -70544,7 +63041,7 @@ pub unsafe fn vst3q_lane_s32(a: *mut i32, b: int32x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] @@ -70569,7 +63066,7 @@ pub unsafe fn vst3_lane_u8(a: *mut u8, b: uint8x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] @@ -70594,7 +63091,7 @@ pub unsafe fn vst3_lane_u16(a: *mut u16, b: uint16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] @@ -70619,7 +63116,7 @@ pub unsafe fn vst3q_lane_u16(a: *mut u16, b: uint16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] @@ -70644,7 +63141,7 @@ pub unsafe fn vst3_lane_u32(a: *mut u32, b: uint32x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] @@ -70669,7 +63166,7 @@ pub unsafe fn vst3q_lane_u32(a: *mut u32, b: uint32x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] @@ -70694,7 +63191,7 @@ pub unsafe fn vst3_lane_p8(a: *mut p8, b: poly8x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] @@ -70719,7 +63216,7 @@ pub unsafe fn vst3_lane_p16(a: *mut p16, b: poly16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] @@ -70744,7 +63241,7 @@ pub unsafe fn vst3q_lane_p16(a: *mut p16, b: poly16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,aes")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -70767,42 +63264,31 @@ pub unsafe fn vst3_p64(a: *mut p64, b: poly64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v1i64.p0" - )] - fn _vst3_s64(a: int64x1_t, b: int64x1_t, c: int64x1_t, ptr: *mut i8); - } - _vst3_s64(b.0, b.1, b.2, a as _) + core::ptr::write_unaligned(a.cast(), b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v1i64")] - fn _vst3_s64(ptr: *mut i8, a: int64x1_t, b: int64x1_t, c: int64x1_t, size: i32); - } - _vst3_s64(a as _, b.0, b.1, b.2, 8) + core::ptr::write_unaligned(a.cast(), b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -70825,7 +63311,7 @@ pub unsafe fn vst3_u64(a: *mut u64, b: uint64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] @@ -70848,7 +63334,7 @@ pub unsafe fn vst3_u8(a: *mut u8, b: uint8x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] @@ -70871,7 +63357,7 @@ pub unsafe fn vst3q_u8(a: *mut u8, b: uint8x16x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] @@ -70894,7 +63380,7 @@ pub unsafe fn vst3_u16(a: *mut u16, b: uint16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] @@ -70917,7 +63403,7 @@ pub unsafe fn vst3q_u16(a: *mut u16, b: uint16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] @@ -70940,7 +63426,7 @@ pub unsafe fn vst3_u32(a: *mut u32, b: uint32x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] @@ -70963,7 +63449,7 @@ pub unsafe fn vst3q_u32(a: *mut u32, b: uint32x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] @@ -70986,7 +63472,7 @@ pub unsafe fn vst3_p8(a: *mut p8, b: poly8x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] @@ -71009,7 +63495,7 @@ pub unsafe fn vst3q_p8(a: *mut p8, b: poly8x16x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] @@ -71032,7 +63518,7 @@ pub unsafe fn vst3_p16(a: *mut p16, b: poly16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] @@ -71055,7 +63541,7 @@ pub unsafe fn vst3q_p16(a: *mut p16, b: poly16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71081,7 +63567,7 @@ pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71107,7 +63593,7 @@ pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] @@ -71128,7 +63614,7 @@ pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] @@ -71149,7 +63635,7 @@ pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -71172,7 +63658,7 @@ pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -71195,7 +63681,7 @@ pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -71211,7 +63697,7 @@ pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -71234,7 +63720,7 @@ pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -71257,7 +63743,7 @@ pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -71280,7 +63766,7 @@ pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -71303,7 +63789,7 @@ pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -71326,656 +63812,1353 @@ pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4))] pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) { + crate::core_arch::macros::interleaving_store!(f32, 2, 4, a, b) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st4))] +pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) { + crate::core_arch::macros::interleaving_store!(f32, 4, 4, a, b) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st4))] +pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) { + crate::core_arch::macros::interleaving_store!(i8, 8, 4, a, b) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st4))] +pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) { + crate::core_arch::macros::interleaving_store!(i8, 16, 4, a, b) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st4))] +pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) { + crate::core_arch::macros::interleaving_store!(i16, 4, 4, a, b) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st4))] +pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) { + crate::core_arch::macros::interleaving_store!(i16, 8, 4, a, b) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st4))] +pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) { + crate::core_arch::macros::interleaving_store!(i32, 2, 4, a, b) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st4))] +pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) { + crate::core_arch::macros::interleaving_store!(i32, 4, 4, a, b) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(test, assert_instr(vst4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vst4_lane_f16(a: *mut f16, b: float16x4x4_t) { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v4f16")] + fn _vst4_lane_f16( + ptr: *mut i8, + a: float16x4_t, + b: float16x4_t, + c: float16x4_t, + d: float16x4_t, + n: i32, + size: i32, + ); + } + _vst4_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(test, assert_instr(vst4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vst4q_lane_f16(a: *mut f16, b: float16x8x4_t) { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v8f16")] + fn _vst4q_lane_f16( + ptr: *mut i8, + a: float16x8_t, + b: float16x8_t, + c: float16x8_t, + d: float16x8_t, + n: i32, + size: i32, + ); + } + _vst4q_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vst4_lane_f16(a: *mut f16, b: float16x4x4_t) { + static_assert_uimm_bits!(LANE, 2); unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v2f32.p0" + link_name = "llvm.aarch64.neon.st4lane.v4f16.p0" )] - fn _vst4_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, d: float32x2_t, ptr: *mut i8); + fn _vst4_lane_f16( + a: float16x4_t, + b: float16x4_t, + c: float16x4_t, + d: float16x4_t, + n: i64, + ptr: *mut i8, + ); } - _vst4_f32(b.0, b.1, b.2, b.3, a as _) + _vst4_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(st4))] -pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) { +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vst4q_lane_f16(a: *mut f16, b: float16x8x4_t) { + static_assert_uimm_bits!(LANE, 3); unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v4f32.p0" + link_name = "llvm.aarch64.neon.st4lane.v8f16.p0" )] - fn _vst4q_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, d: float32x4_t, ptr: *mut i8); + fn _vst4q_lane_f16( + a: float16x8_t, + b: float16x8_t, + c: float16x8_t, + d: float16x8_t, + n: i64, + ptr: *mut i8, + ); } - _vst4q_f32(b.0, b.1, b.2, b.3, a as _) + _vst4q_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst4_lane_f32(a: *mut f32, b: float32x2x4_t) { + static_assert_uimm_bits!(LANE, 1); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v2f32")] + fn _vst4_lane_f32( + ptr: *mut i8, + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, + d: float32x2_t, + n: i32, + size: i32, + ); + } + _vst4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst4q_lane_f32(a: *mut f32, b: float32x4x4_t) { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v4f32")] + fn _vst4q_lane_f32( + ptr: *mut i8, + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, + d: float32x4_t, + n: i32, + size: i32, + ); + } + _vst4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst4_lane_s8(a: *mut i8, b: int8x8x4_t) { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v8i8")] + fn _vst4_lane_s8( + ptr: *mut i8, + a: int8x8_t, + b: int8x8_t, + c: int8x8_t, + d: int8x8_t, + n: i32, + size: i32, + ); + } + _vst4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst4_lane_s16(a: *mut i16, b: int16x4x4_t) { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v4i16")] + fn _vst4_lane_s16( + ptr: *mut i8, + a: int16x4_t, + b: int16x4_t, + c: int16x4_t, + d: int16x4_t, + n: i32, + size: i32, + ); + } + _vst4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst4q_lane_s16(a: *mut i16, b: int16x8x4_t) { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v8i16")] + fn _vst4q_lane_s16( + ptr: *mut i8, + a: int16x8_t, + b: int16x8_t, + c: int16x8_t, + d: int16x8_t, + n: i32, + size: i32, + ); + } + _vst4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst4_lane_s32(a: *mut i32, b: int32x2x4_t) { + static_assert_uimm_bits!(LANE, 1); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v2i32")] + fn _vst4_lane_s32( + ptr: *mut i8, + a: int32x2_t, + b: int32x2_t, + c: int32x2_t, + d: int32x2_t, + n: i32, + size: i32, + ); + } + _vst4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst4q_lane_s32(a: *mut i32, b: int32x4x4_t) { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v4i32")] + fn _vst4q_lane_s32( + ptr: *mut i8, + a: int32x4_t, + b: int32x4_t, + c: int32x4_t, + d: int32x4_t, + n: i32, + size: i32, + ); + } + _vst4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(st4))] -pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) { +pub unsafe fn vst4_lane_f32(a: *mut f32, b: float32x2x4_t) { + static_assert_uimm_bits!(LANE, 1); unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v8i8.p0" + link_name = "llvm.aarch64.neon.st4lane.v2f32.p0" )] - fn _vst4_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, ptr: *mut i8); + fn _vst4_lane_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, + d: float32x2_t, + n: i64, + ptr: *mut i8, + ); } - _vst4_s8(b.0, b.1, b.2, b.3, a as _) + _vst4_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(st4))] -pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) { +pub unsafe fn vst4q_lane_f32(a: *mut f32, b: float32x4x4_t) { + static_assert_uimm_bits!(LANE, 2); unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v16i8.p0" + link_name = "llvm.aarch64.neon.st4lane.v4f32.p0" )] - fn _vst4q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, ptr: *mut i8); + fn _vst4q_lane_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, + d: float32x4_t, + n: i64, + ptr: *mut i8, + ); } - _vst4q_s8(b.0, b.1, b.2, b.3, a as _) + _vst4q_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(st4))] -pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) { +pub unsafe fn vst4_lane_s8(a: *mut i8, b: int8x8x4_t) { + static_assert_uimm_bits!(LANE, 3); unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v4i16.p0" + link_name = "llvm.aarch64.neon.st4lane.v8i8.p0" )] - fn _vst4_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t, ptr: *mut i8); + fn _vst4_lane_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, n: i64, ptr: *mut i8); } - _vst4_s16(b.0, b.1, b.2, b.3, a as _) + _vst4_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(st4))] -pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) { +pub unsafe fn vst4_lane_s16(a: *mut i16, b: int16x4x4_t) { + static_assert_uimm_bits!(LANE, 2); unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v8i16.p0" + link_name = "llvm.aarch64.neon.st4lane.v4i16.p0" )] - fn _vst4q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t, ptr: *mut i8); + fn _vst4_lane_s16( + a: int16x4_t, + b: int16x4_t, + c: int16x4_t, + d: int16x4_t, + n: i64, + ptr: *mut i8, + ); } - _vst4q_s16(b.0, b.1, b.2, b.3, a as _) + _vst4_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(st4))] -pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) { +pub unsafe fn vst4q_lane_s16(a: *mut i16, b: int16x8x4_t) { + static_assert_uimm_bits!(LANE, 3); unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v2i32.p0" + link_name = "llvm.aarch64.neon.st4lane.v8i16.p0" )] - fn _vst4_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t, ptr: *mut i8); + fn _vst4q_lane_s16( + a: int16x8_t, + b: int16x8_t, + c: int16x8_t, + d: int16x8_t, + n: i64, + ptr: *mut i8, + ); } - _vst4_s32(b.0, b.1, b.2, b.3, a as _) + _vst4q_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(st4))] -pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) { +pub unsafe fn vst4_lane_s32(a: *mut i32, b: int32x2x4_t) { + static_assert_uimm_bits!(LANE, 1); unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v4i32.p0" + link_name = "llvm.aarch64.neon.st4lane.v2i32.p0" )] - fn _vst4q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t, ptr: *mut i8); + fn _vst4_lane_s32( + a: int32x2_t, + b: int32x2_t, + c: int32x2_t, + d: int32x2_t, + n: i64, + ptr: *mut i8, + ); } - _vst4q_s32(b.0, b.1, b.2, b.3, a as _) + _vst4_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(vst4, LANE = 0))] +#[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vst4_lane_f16(a: *mut f16, b: float16x4x4_t) { +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst4q_lane_s32(a: *mut i32, b: int32x4x4_t) { static_assert_uimm_bits!(LANE, 2); unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v4f16")] - fn _vst4_lane_f16( + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4lane.v4i32.p0" + )] + fn _vst4q_lane_s32( + a: int32x4_t, + b: int32x4_t, + c: int32x4_t, + d: int32x4_t, + n: i64, ptr: *mut i8, - a: float16x4_t, - b: float16x4_t, - c: float16x4_t, - d: float16x4_t, - n: i32, - size: i32, ); } - _vst4_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2) + _vst4q_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(vst4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] #[rustc_legacy_const_generics(2)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vst4q_lane_f16(a: *mut f16, b: float16x8x4_t) { +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_lane_u8(a: *mut u8, b: uint8x8x4_t) { static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v8f16")] - fn _vst4q_lane_f16( - ptr: *mut i8, - a: float16x8_t, - b: float16x8_t, - c: float16x8_t, - d: float16x8_t, - n: i32, - size: i32, - ); - } - _vst4q_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2) + vst4_lane_s8::(transmute(a), transmute(b)) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] #[rustc_legacy_const_generics(2)] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vst4_lane_f16(a: *mut f16, b: float16x4x4_t) { +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_lane_u16(a: *mut u16, b: uint16x4x4_t) { static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4lane.v4f16.p0" - )] - fn _vst4_lane_f16( - a: float16x4_t, - b: float16x4_t, - c: float16x4_t, - d: float16x4_t, - n: i64, - ptr: *mut i8, - ); - } - _vst4_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _) + vst4_lane_s16::(transmute(a), transmute(b)) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] #[rustc_legacy_const_generics(2)] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vst4q_lane_f16(a: *mut f16, b: float16x8x4_t) { +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_lane_u16(a: *mut u16, b: uint16x8x4_t) { static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4lane.v8f16.p0" - )] - fn _vst4q_lane_f16( - a: float16x8_t, - b: float16x8_t, - c: float16x8_t, - d: float16x8_t, - n: i64, - ptr: *mut i8, - ); - } - _vst4q_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _) + vst4q_lane_s16::(transmute(a), transmute(b)) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst4, LANE = 0))] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst4_lane_f32(a: *mut f32, b: float32x2x4_t) { +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_lane_u32(a: *mut u32, b: uint32x2x4_t) { static_assert_uimm_bits!(LANE, 1); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v2f32")] - fn _vst4_lane_f32( - ptr: *mut i8, - a: float32x2_t, - b: float32x2_t, - c: float32x2_t, - d: float32x2_t, - n: i32, - size: i32, - ); - } - _vst4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) + vst4_lane_s32::(transmute(a), transmute(b)) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst4, LANE = 0))] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst4q_lane_f32(a: *mut f32, b: float32x4x4_t) { +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_lane_u32(a: *mut u32, b: uint32x4x4_t) { static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v4f32")] - fn _vst4q_lane_f32( - ptr: *mut i8, - a: float32x4_t, - b: float32x4_t, - c: float32x4_t, - d: float32x4_t, - n: i32, - size: i32, - ); - } - _vst4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) + vst4q_lane_s32::(transmute(a), transmute(b)) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst4, LANE = 0))] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst4_lane_s8(a: *mut i8, b: int8x8x4_t) { +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_lane_p8(a: *mut p8, b: poly8x8x4_t) { static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v8i8")] - fn _vst4_lane_s8( - ptr: *mut i8, - a: int8x8_t, - b: int8x8_t, - c: int8x8_t, - d: int8x8_t, - n: i32, - size: i32, - ); - } - _vst4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1) + vst4_lane_s8::(transmute(a), transmute(b)) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst4, LANE = 0))] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst4_lane_s16(a: *mut i16, b: int16x4x4_t) { +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_lane_p16(a: *mut p16, b: poly16x4x4_t) { static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v4i16")] - fn _vst4_lane_s16( - ptr: *mut i8, - a: int16x4_t, - b: int16x4_t, - c: int16x4_t, - d: int16x4_t, - n: i32, - size: i32, - ); - } - _vst4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) + vst4_lane_s16::(transmute(a), transmute(b)) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_lane_p16(a: *mut p16, b: poly16x8x4_t) { + static_assert_uimm_bits!(LANE, 3); + vst4q_lane_s16::(transmute(a), transmute(b)) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_p64(a: *mut p64, b: poly64x1x4_t) { + vst4_s64(transmute(a), transmute(b)) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst4, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst4q_lane_s16(a: *mut i16, b: int16x8x4_t) { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v8i16")] - fn _vst4q_lane_s16( - ptr: *mut i8, - a: int16x8_t, - b: int16x8_t, - c: int16x8_t, - d: int16x8_t, - n: i32, - size: i32, - ); - } - _vst4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { + core::ptr::write_unaligned(a.cast(), b) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { + core::ptr::write_unaligned(a.cast(), b) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_u64(a: *mut u64, b: uint64x1x4_t) { + vst4_s64(transmute(a), transmute(b)) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_u8(a: *mut u8, b: uint8x8x4_t) { + vst4_s8(transmute(a), transmute(b)) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_u8(a: *mut u8, b: uint8x16x4_t) { + vst4q_s8(transmute(a), transmute(b)) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_u16(a: *mut u16, b: uint16x4x4_t) { + vst4_s16(transmute(a), transmute(b)) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst4_lane_s32(a: *mut i32, b: int32x2x4_t) { - static_assert_uimm_bits!(LANE, 1); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v2i32")] - fn _vst4_lane_s32( - ptr: *mut i8, - a: int32x2_t, - b: int32x2_t, - c: int32x2_t, - d: int32x2_t, - n: i32, - size: i32, - ); - } - _vst4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_u16(a: *mut u16, b: uint16x8x4_t) { + vst4q_s16(transmute(a), transmute(b)) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst4q_lane_s32(a: *mut i32, b: int32x4x4_t) { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v4i32")] - fn _vst4q_lane_s32( - ptr: *mut i8, - a: int32x4_t, - b: int32x4_t, - c: int32x4_t, - d: int32x4_t, - n: i32, - size: i32, - ); - } - _vst4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_u32(a: *mut u32, b: uint32x2x4_t) { + vst4_s32(transmute(a), transmute(b)) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4_lane_f32(a: *mut f32, b: float32x2x4_t) { - static_assert_uimm_bits!(LANE, 1); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4lane.v2f32.p0" - )] - fn _vst4_lane_f32( - a: float32x2_t, - b: float32x2_t, - c: float32x2_t, - d: float32x2_t, - n: i64, - ptr: *mut i8, - ); - } - _vst4_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_u32(a: *mut u32, b: uint32x4x4_t) { + vst4q_s32(transmute(a), transmute(b)) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_lane_f32(a: *mut f32, b: float32x4x4_t) { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4lane.v4f32.p0" - )] - fn _vst4q_lane_f32( - a: float32x4_t, - b: float32x4_t, - c: float32x4_t, - d: float32x4_t, - n: i64, - ptr: *mut i8, - ); - } - _vst4q_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_p8(a: *mut p8, b: poly8x8x4_t) { + vst4_s8(transmute(a), transmute(b)) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4_lane_s8(a: *mut i8, b: int8x8x4_t) { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4lane.v8i8.p0" - )] - fn _vst4_lane_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, n: i64, ptr: *mut i8); - } - _vst4_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_p8(a: *mut p8, b: poly8x16x4_t) { + vst4q_s8(transmute(a), transmute(b)) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4_lane_s16(a: *mut i16, b: int16x4x4_t) { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4lane.v4i16.p0" - )] - fn _vst4_lane_s16( - a: int16x4_t, - b: int16x4_t, - c: int16x4_t, - d: int16x4_t, - n: i64, - ptr: *mut i8, - ); - } - _vst4_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_p16(a: *mut p16, b: poly16x4x4_t) { + vst4_s16(transmute(a), transmute(b)) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_lane_s16(a: *mut i16, b: int16x8x4_t) { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4lane.v8i16.p0" - )] - fn _vst4q_lane_s16( - a: int16x8_t, - b: int16x8_t, - c: int16x8_t, - d: int16x8_t, - n: i64, - ptr: *mut i8, - ); - } - _vst4q_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) { + vst4q_s16(transmute(a), transmute(b)) } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"] +#[doc = "Store SIMD&FP register (immediate offset)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstrq_p128)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4_lane_s32(a: *mut i32, b: int32x2x4_t) { - static_assert_uimm_bits!(LANE, 1); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4lane.v2i32.p0" - )] - fn _vst4_lane_s32( - a: int32x2_t, - b: int32x2_t, - c: int32x2_t, - d: int32x2_t, - n: i64, - ptr: *mut i8, - ); - } - _vst4_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vstrq_p128(a: *mut p128, b: p128) { + *a = b +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fsub) +)] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "stdarch_neon_fp16", since = "1.94.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vsub_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { simd_sub(a, b) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fsub) +)] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "stdarch_neon_fp16", since = "1.94.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vsubq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { simd_sub(a, b) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { simd_sub(a, b) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsubq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { simd_sub(a, b) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { simd_sub(a, b) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { simd_sub(a, b) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_sub(a, b) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_sub(a, b) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { simd_sub(a, b) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { simd_sub(a, b) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_lane_s32(a: *mut i32, b: int32x4x4_t) { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4lane.v4i32.p0" - )] - fn _vst4q_lane_s32( - a: int32x4_t, - b: int32x4_t, - c: int32x4_t, - d: int32x4_t, - n: i64, - ptr: *mut i8, - ); - } - _vst4q_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_sub(a, b) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4, LANE = 0) + assert_instr(sub) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -71984,23 +65167,19 @@ pub unsafe fn vst4q_lane_s32(a: *mut i32, b: int32x4x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_lane_u8(a: *mut u8, b: uint8x8x4_t) { - static_assert_uimm_bits!(LANE, 3); - vst4_lane_s8::(transmute(a), transmute(b)) +pub fn vsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_sub(a, b) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4, LANE = 0) + assert_instr(sub) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -72009,23 +65188,19 @@ pub unsafe fn vst4_lane_u8(a: *mut u8, b: uint8x8x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_lane_u16(a: *mut u16, b: uint16x4x4_t) { - static_assert_uimm_bits!(LANE, 2); - vst4_lane_s16::(transmute(a), transmute(b)) +pub fn vsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + unsafe { simd_sub(a, b) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4, LANE = 0) + assert_instr(sub) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -72034,23 +65209,19 @@ pub unsafe fn vst4_lane_u16(a: *mut u16, b: uint16x4x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4q_lane_u16(a: *mut u16, b: uint16x8x4_t) { - static_assert_uimm_bits!(LANE, 3); - vst4q_lane_s16::(transmute(a), transmute(b)) +pub fn vsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { simd_sub(a, b) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4, LANE = 0) + assert_instr(sub) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -72059,23 +65230,19 @@ pub unsafe fn vst4q_lane_u16(a: *mut u16, b: uint16x8x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_lane_u32(a: *mut u32, b: uint32x2x4_t) { - static_assert_uimm_bits!(LANE, 1); - vst4_lane_s32::(transmute(a), transmute(b)) +pub fn vsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + unsafe { simd_sub(a, b) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4, LANE = 0) + assert_instr(sub) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -72084,23 +65251,19 @@ pub unsafe fn vst4_lane_u32(a: *mut u32, b: uint32x2x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4q_lane_u32(a: *mut u32, b: uint32x4x4_t) { - static_assert_uimm_bits!(LANE, 2); - vst4q_lane_s32::(transmute(a), transmute(b)) +pub fn vsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { simd_sub(a, b) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4, LANE = 0) + assert_instr(sub) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -72109,23 +65272,19 @@ pub unsafe fn vst4q_lane_u32(a: *mut u32, b: uint32x4x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_lane_p8(a: *mut p8, b: poly8x8x4_t) { - static_assert_uimm_bits!(LANE, 3); - vst4_lane_s8::(transmute(a), transmute(b)) +pub fn vsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { simd_sub(a, b) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4, LANE = 0) + assert_instr(sub) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -72134,23 +65293,19 @@ pub unsafe fn vst4_lane_p8(a: *mut p8, b: poly8x8x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_lane_p16(a: *mut p16, b: poly16x4x4_t) { - static_assert_uimm_bits!(LANE, 2); - vst4_lane_s16::(transmute(a), transmute(b)) +pub fn vsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { simd_sub(a, b) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4, LANE = 0) + assert_instr(sub) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -72159,21 +65314,18 @@ pub unsafe fn vst4_lane_p16(a: *mut p16, b: poly16x4x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4q_lane_p16(a: *mut p16, b: poly16x8x4_t) { - static_assert_uimm_bits!(LANE, 3); - vst4q_lane_s16::(transmute(a), transmute(b)) +pub fn vsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_sub(a, b) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sub) )] #[cfg_attr( not(target_arch = "arm"), @@ -72183,62 +65335,74 @@ pub unsafe fn vst4q_lane_p16(a: *mut p16, b: poly16x8x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_p64(a: *mut p64, b: poly64x1x4_t) { - vst4_s64(transmute(a), transmute(b)) +pub fn vsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { simd_sub(a, b) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v1i64")] - fn _vst4_s64( - ptr: *mut i8, - a: int64x1_t, - b: int64x1_t, - c: int64x1_t, - d: int64x1_t, - size: i32, - ); - } - _vst4_s64(a as _, b.0, b.1, b.2, b.3, 8) +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr( + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(subhn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t { + let d = vsubhn_s16(b, c); + vcombine_s8(a, d) } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v1i64.p0" - )] - fn _vst4_s64(a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t, ptr: *mut i8); - } - _vst4_s64(b.0, b.1, b.2, b.3, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr( + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(subhn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { + let d = vsubhn_s32(b, c); + vcombine_s16(a, d) } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(subhn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72248,20 +65412,23 @@ pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_u64(a: *mut u64, b: uint64x1x4_t) { - vst4_s64(transmute(a), transmute(b)) +pub fn vsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t { + let d = vsubhn_s64(b, c); + vcombine_s32(a, d) } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4) + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(subhn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72271,20 +65438,23 @@ pub unsafe fn vst4_u64(a: *mut u64, b: uint64x1x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_u8(a: *mut u8, b: uint8x8x4_t) { - vst4_s8(transmute(a), transmute(b)) +pub fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t { + let d = vsubhn_u16(b, c); + vcombine_u8(a, d) } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4) + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(subhn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72294,20 +65464,45 @@ pub unsafe fn vst4_u8(a: *mut u8, b: uint8x8x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4q_u8(a: *mut u8, b: uint8x16x4_t) { - vst4q_s8(transmute(a), transmute(b)) +pub fn vsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t { + let d = vsubhn_u32(b, c); + vcombine_u16(a, d) } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr( + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(subhn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t { + let d = vsubhn_u64(b, c); + vcombine_u32(a, d) +} +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4) + assert_instr(subhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -72317,20 +65512,19 @@ pub unsafe fn vst4q_u8(a: *mut u8, b: uint8x16x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_u16(a: *mut u16, b: uint16x4x4_t) { - vst4_s16(transmute(a), transmute(b)) +pub fn vsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { + let c: i16x8 = i16x8::new(8, 8, 8, 8, 8, 8, 8, 8); + unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4) + assert_instr(subhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -72340,20 +65534,19 @@ pub unsafe fn vst4_u16(a: *mut u16, b: uint16x4x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4q_u16(a: *mut u16, b: uint16x8x4_t) { - vst4q_s16(transmute(a), transmute(b)) +pub fn vsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { + let c: i32x4 = i32x4::new(16, 16, 16, 16); + unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4) + assert_instr(subhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -72363,20 +65556,19 @@ pub unsafe fn vst4q_u16(a: *mut u16, b: uint16x8x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_u32(a: *mut u32, b: uint32x2x4_t) { - vst4_s32(transmute(a), transmute(b)) +pub fn vsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { + let c: i64x2 = i64x2::new(32, 32); + unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4) + assert_instr(subhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -72386,20 +65578,19 @@ pub unsafe fn vst4_u32(a: *mut u32, b: uint32x2x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4q_u32(a: *mut u32, b: uint32x4x4_t) { - vst4q_s32(transmute(a), transmute(b)) +pub fn vsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { + let c: u16x8 = u16x8::new(8, 8, 8, 8, 8, 8, 8, 8); + unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4) + assert_instr(subhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -72409,20 +65600,19 @@ pub unsafe fn vst4q_u32(a: *mut u32, b: uint32x4x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_p8(a: *mut p8, b: poly8x8x4_t) { - vst4_s8(transmute(a), transmute(b)) +pub fn vsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { + let c: u32x4 = u32x4::new(16, 16, 16, 16); + unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4) + assert_instr(subhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -72432,20 +65622,19 @@ pub unsafe fn vst4_p8(a: *mut p8, b: poly8x8x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4q_p8(a: *mut p8, b: poly8x16x4_t) { - vst4q_s8(transmute(a), transmute(b)) +pub fn vsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { + let c: u64x2 = u64x2::new(32, 32); + unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Signed Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4) + assert_instr(ssubl) )] #[cfg_attr( not(target_arch = "arm"), @@ -72455,20 +65644,22 @@ pub unsafe fn vst4q_p8(a: *mut p8, b: poly8x16x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_p16(a: *mut p16, b: poly16x4x4_t) { - vst4_s16(transmute(a), transmute(b)) +pub fn vsubl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { + unsafe { + let c: int16x8_t = simd_cast(a); + let d: int16x8_t = simd_cast(b); + simd_sub(c, d) + } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Signed Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4) + assert_instr(ssubl) )] #[cfg_attr( not(target_arch = "arm"), @@ -72478,20 +65669,22 @@ pub unsafe fn vst4_p16(a: *mut p16, b: poly16x4x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) { - vst4q_s16(transmute(a), transmute(b)) +pub fn vsubl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { + unsafe { + let c: int32x4_t = simd_cast(a); + let d: int32x4_t = simd_cast(b); + simd_sub(c, d) + } } -#[doc = "Store SIMD&FP register (immediate offset)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstrq_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Signed Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ssubl) )] #[cfg_attr( not(target_arch = "arm"), @@ -72501,62 +65694,72 @@ pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vstrq_p128(a: *mut p128, b: p128) { - *a = b +pub fn vsubl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { + unsafe { + let c: int64x2_t = simd_cast(a); + let d: int64x2_t = simd_cast(b); + simd_sub(c, d) + } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))] +#[doc = "Unsigned Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fsub) + assert_instr(usubl) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vsub_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - unsafe { simd_sub(a, b) } +pub fn vsubl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { + unsafe { + let c: uint16x8_t = simd_cast(a); + let d: uint16x8_t = simd_cast(b); + simd_sub(c, d) + } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))] +#[doc = "Unsigned Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fsub) + assert_instr(usubl) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vsubq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - unsafe { simd_sub(a, b) } +pub fn vsubl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { + unsafe { + let c: uint32x4_t = simd_cast(a); + let d: uint32x4_t = simd_cast(b); + simd_sub(c, d) + } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f32)"] -#[inline(always)] +#[doc = "Unsigned Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fsub) + assert_instr(usubl) )] #[cfg_attr( not(target_arch = "arm"), @@ -72566,18 +65769,22 @@ pub fn vsubq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - unsafe { simd_sub(a, b) } +pub fn vsubl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { + unsafe { + let c: uint64x2_t = simd_cast(a); + let d: uint64x2_t = simd_cast(b); + simd_sub(c, d) + } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f32)"] -#[inline(always)] +#[doc = "Signed Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fsub) + assert_instr(ssubw) )] #[cfg_attr( not(target_arch = "arm"), @@ -72587,18 +65794,18 @@ pub fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - unsafe { simd_sub(a, b) } +pub fn vsubw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t { + unsafe { simd_sub(a, simd_cast(b)) } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s16)"] -#[inline(always)] +#[doc = "Signed Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) + assert_instr(ssubw) )] #[cfg_attr( not(target_arch = "arm"), @@ -72608,18 +65815,18 @@ pub fn vsubq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe { simd_sub(a, b) } +pub fn vsubw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t { + unsafe { simd_sub(a, simd_cast(b)) } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s16)"] -#[inline(always)] +#[doc = "Signed Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) + assert_instr(ssubw) )] #[cfg_attr( not(target_arch = "arm"), @@ -72629,18 +65836,18 @@ pub fn vsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe { simd_sub(a, b) } +pub fn vsubw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t { + unsafe { simd_sub(a, simd_cast(b)) } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u16)"] -#[inline(always)] +#[doc = "Unsigned Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) + assert_instr(usubw) )] #[cfg_attr( not(target_arch = "arm"), @@ -72650,18 +65857,18 @@ pub fn vsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - unsafe { simd_sub(a, b) } +pub fn vsubw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t { + unsafe { simd_sub(a, simd_cast(b)) } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u16)"] -#[inline(always)] +#[doc = "Unsigned Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) + assert_instr(usubw) )] #[cfg_attr( not(target_arch = "arm"), @@ -72671,18 +65878,18 @@ pub fn vsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - unsafe { simd_sub(a, b) } +pub fn vsubw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t { + unsafe { simd_sub(a, simd_cast(b)) } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s32)"] -#[inline(always)] +#[doc = "Unsigned Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) + assert_instr(usubw) )] #[cfg_attr( not(target_arch = "arm"), @@ -72692,337 +65899,750 @@ pub fn vsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe { simd_sub(a, b) } +pub fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t { + unsafe { simd_sub(a, simd_cast(b)) } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] +#[doc = "Dot product index form with signed and unsigned integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"] +#[inline] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(sudot, LANE = 0) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + unstable(feature = "stdarch_neon_i8mm", issue = "117223") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe { simd_sub(a, b) } +pub fn vsudot_lane_s32(a: int32x2_t, b: int8x8_t, c: uint8x8_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); + let c = vreinterpret_u32_u8(c); + let c = vdup_lane_u32::(c); + vusdot_s32(a, vreinterpret_u8_u32(c), b) } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] +#[doc = "Dot product index form with signed and unsigned integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"] +#[inline] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(sudot, LANE = 0) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + unstable(feature = "stdarch_neon_i8mm", issue = "117223") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - unsafe { simd_sub(a, b) } +pub fn vsudotq_lane_s32(a: int32x4_t, b: int8x16_t, c: uint8x8_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 1); + let c = vreinterpret_u32_u8(c); + let c = vdupq_lane_u32::(c); + vusdotq_s32(a, vreinterpretq_u8_u32(c), b) +} +#[doc = "Dot product index form with signed and unsigned integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_laneq_s32)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 1))] +#[cfg_attr( + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(sudot, LANE = 3) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub fn vsudot_laneq_s32(a: int32x2_t, b: int8x8_t, c: uint8x16_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + let c = vreinterpretq_u32_u8(c); + let c = vdup_laneq_u32::(c); + vusdot_s32(a, vreinterpret_u8_u32(c), b) +} +#[doc = "Dot product index form with signed and unsigned integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_laneq_s32)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 1))] +#[cfg_attr( + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(sudot, LANE = 3) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub fn vsudotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: uint8x16_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + let c = vreinterpretq_u32_u8(c); + let c = vdupq_laneq_u32::(c); + vusdotq_s32(a, vreinterpretq_u8_u32(c), b) +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +fn vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl1")] + fn _vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + unsafe { _vtbl1(a, b) } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + vtbl1(a, b) +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { transmute(vtbl1(transmute(a), transmute(b))) } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t { + unsafe { transmute(vtbl1(transmute(a), transmute(b))) } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +fn vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl2")] + fn _vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t; + } + unsafe { _vtbl2(a, b, c) } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t { + vtbl2(a.0, a.1, b) +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t { + unsafe { transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t { + unsafe { transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +fn vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl3")] + fn _vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t; + } + unsafe { _vtbl3(a, b, c, d) } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t { + vtbl3(a.0, a.1, a.2, b) +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + transmute(vtbl3( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(b), + )) + } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t { + unsafe { + transmute(vtbl3( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(b), + )) + } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +fn vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl4")] + fn _vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t; + } + unsafe { _vtbl4(a, b, c, d, e) } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t { + vtbl4(a.0, a.1, a.2, a.3, b) +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + transmute(vtbl4( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(a.3), + transmute(b), + )) + } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t { + unsafe { + transmute(vtbl4( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(a.3), + transmute(b), + )) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +fn vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx1")] + fn _vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t; + } + unsafe { _vtbx1(a, b, c) } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { + vtbx1(a, b, c) +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { + unsafe { transmute(vtbx1(transmute(a), transmute(b), transmute(c))) } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t { + unsafe { transmute(vtbx1(transmute(a), transmute(b), transmute(c))) } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +fn vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx2")] + fn _vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t; + } + unsafe { _vtbx2(a, b, c, d) } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_s8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t { + vtbx2(a, b.0, b.1, c) +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t { + unsafe { + transmute(vtbx2( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(c), + )) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t { + unsafe { + transmute(vtbx2( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(c), + )) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +fn vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx3")] + fn _vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t; + } + unsafe { _vtbx3(a, b, c, d, e) } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t { + vtbx3(a, b.0, b.1, b.2, c) +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t { + unsafe { + transmute(vtbx3( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(c), + )) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t { + unsafe { + transmute(vtbx3( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(c), + )) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +fn vtbx4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t, f: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx4")] + fn _vtbx4( + a: int8x8_t, + b: int8x8_t, + c: int8x8_t, + d: int8x8_t, + e: int8x8_t, + f: int8x8_t, + ) -> int8x8_t; + } + unsafe { _vtbx4(a, b, c, d, e, f) } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - unsafe { simd_sub(a, b) } +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t { + unsafe { + vtbx4( + a, + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + c, + ) + } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - unsafe { simd_sub(a, b) } +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t { + let mut b: int8x8x4_t = b; + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]); + b.1 = simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]); + b.2 = simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]); + b.3 = simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]); + let c: int8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = vtbx4( + a, + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + c, + ); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - unsafe { simd_sub(a, b) } +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t { + unsafe { + transmute(vtbx4( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + transmute(c), + )) + } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - unsafe { simd_sub(a, b) } +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t { + unsafe { + transmute(vtbx4( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + transmute(c), + )) + } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(trn1) )] -pub fn vsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - unsafe { simd_sub(a, b) } -} -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) + assert_instr(trn2) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe { simd_sub(a, b) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { + unsafe { + let a1: float16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: float16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) + } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(trn1) )] -pub fn vsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe { simd_sub(a, b) } -} -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) + assert_instr(trn2) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - unsafe { simd_sub(a, b) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a1: float16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: float16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + let mut ret_val: float16x4x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val + } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(trn1) )] -pub fn vsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - unsafe { simd_sub(a, b) } -} -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn2) + assert_instr(trn2) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t { - let d: int8x8_t = vsubhn_s16(b, c); - unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vtrnq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { + unsafe { + let a1: float16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: float16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) + } } -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(trn1) )] -pub fn vsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { - let d: int16x4_t = vsubhn_s32(b, c); - unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) } -} -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn2) + assert_instr(trn2) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t { - let d: int32x2_t = vsubhn_s64(b, c); - unsafe { simd_shuffle!(a, d, [0, 1, 2, 3]) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vtrnq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a1: float16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: float16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + let mut ret_val: float16x8x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val + } } -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u16)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(zip1) )] -pub fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t { - let d: uint8x8_t = vsubhn_u16(b, c); - unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } -} -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73032,41 +66652,27 @@ pub fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t { - let d: uint16x4_t = vsubhn_u32(b, c); - unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) } +pub fn vtrn_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { + unsafe { + let a1: float32x2_t = simd_shuffle!(a, b, [0, 2]); + let b1: float32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a1, b1)) + } } -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u64)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(zip1) )] -pub fn vsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t { - let d: uint32x2_t = vsubhn_u64(b, c); - unsafe { simd_shuffle!(a, d, [0, 1, 2, 3]) } -} -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73076,41 +66682,32 @@ pub fn vsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { - let c: i16x8 = i16x8::new(8, 8, 8, 8, 8, 8, 8, 8); - unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } +pub fn vtrn_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let a1: float32x2_t = simd_shuffle!(a, b, [0, 2]); + let b1: float32x2_t = simd_shuffle!(a, b, [1, 3]); + let mut ret_val: float32x2x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]); + ret_val + } } -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s32)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(zip1) )] -pub fn vsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { - let c: i32x4 = i32x4::new(16, 16, 16, 16); - unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } -} -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73120,41 +66717,27 @@ pub fn vsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { - let c: i64x2 = i64x2::new(32, 32); - unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } +pub fn vtrn_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { + unsafe { + let a1: int32x2_t = simd_shuffle!(a, b, [0, 2]); + let b1: int32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a1, b1)) + } } -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u16)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(zip1) )] -pub fn vsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { - let c: u16x8 = u16x8::new(8, 8, 8, 8, 8, 8, 8, 8); - unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } -} -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73164,41 +66747,32 @@ pub fn vsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { - let c: u32x4 = u32x4::new(16, 16, 16, 16); - unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } +pub fn vtrn_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let a1: int32x2_t = simd_shuffle!(a, b, [0, 2]); + let b1: int32x2_t = simd_shuffle!(a, b, [1, 3]); + let mut ret_val: int32x2x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]); + ret_val + } } -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u64)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(zip1) )] -pub fn vsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { - let c: u64x2 = u64x2::new(32, 32); - unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } -} -#[doc = "Signed Subtract Long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ssubl) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73208,22 +66782,27 @@ pub fn vsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { +pub fn vtrn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { unsafe { - let c: int16x8_t = simd_cast(a); - let d: int16x8_t = simd_cast(b); - simd_sub(c, d) + let a1: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + let b1: uint32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a1, b1)) } } -#[doc = "Signed Subtract Long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s16)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ssubl) + assert_instr(zip1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73233,22 +66812,32 @@ pub fn vsubl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { +pub fn vtrn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { unsafe { - let c: int32x4_t = simd_cast(a); - let d: int32x4_t = simd_cast(b); - simd_sub(c, d) + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let a1: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + let b1: uint32x2_t = simd_shuffle!(a, b, [1, 3]); + let mut ret_val: uint32x2x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]); + ret_val } } -#[doc = "Signed Subtract Long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s32)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ssubl) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73258,22 +66847,27 @@ pub fn vsubl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { +pub fn vtrnq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { unsafe { - let c: int64x2_t = simd_cast(a); - let d: int64x2_t = simd_cast(b); - simd_sub(c, d) + let a1: float32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: float32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) } } -#[doc = "Unsigned Subtract Long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usubl) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73283,22 +66877,32 @@ pub fn vsubl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { +pub fn vtrnq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { unsafe { - let c: uint16x8_t = simd_cast(a); - let d: uint16x8_t = simd_cast(b); - simd_sub(c, d) + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a1: float32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: float32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + let mut ret_val: float32x4x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Unsigned Subtract Long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u16)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usubl) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73308,22 +66912,27 @@ pub fn vsubl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { +pub fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { unsafe { - let c: uint32x4_t = simd_cast(a); - let d: uint32x4_t = simd_cast(b); - simd_sub(c, d) + let a1: int8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: int8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) } } -#[doc = "Unsigned Subtract Long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u32)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usubl) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73333,22 +66942,32 @@ pub fn vsubl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { +pub fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { unsafe { - let c: uint64x2_t = simd_cast(a); - let d: uint64x2_t = simd_cast(b); - simd_sub(c, d) + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a1: int8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: int8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + let mut ret_val: int8x8x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } -#[doc = "Signed Subtract Wide"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ssubw) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73358,18 +66977,35 @@ pub fn vsubl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t { - unsafe { simd_sub(a, simd_cast(b)) } +pub fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { + unsafe { + let a1: int8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + let b1: int8x16_t = simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + transmute((a1, b1)) + } } -#[doc = "Signed Subtract Wide"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s16)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ssubw) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73379,18 +67015,50 @@ pub fn vsubw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t { - unsafe { simd_sub(a, simd_cast(b)) } +pub fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let a1: int8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + let b1: int8x16_t = simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + let mut ret_val: int8x16x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!( + ret_val.0, + ret_val.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val.1 = simd_shuffle!( + ret_val.1, + ret_val.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val + } } -#[doc = "Signed Subtract Wide"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s32)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ssubw) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73400,18 +67068,27 @@ pub fn vsubw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t { - unsafe { simd_sub(a, simd_cast(b)) } +pub fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { + unsafe { + let a1: int16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: int16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) + } } -#[doc = "Unsigned Subtract Wide"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usubw) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73421,18 +67098,32 @@ pub fn vsubw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t { - unsafe { simd_sub(a, simd_cast(b)) } +pub fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a1: int16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: int16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + let mut ret_val: int16x4x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val + } } -#[doc = "Unsigned Subtract Wide"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u16)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usubw) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73442,18 +67133,27 @@ pub fn vsubw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t { - unsafe { simd_sub(a, simd_cast(b)) } +pub fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { + unsafe { + let a1: int16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: int16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) + } } -#[doc = "Unsigned Subtract Wide"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u32)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usubw) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73463,1264 +67163,1533 @@ pub fn vsubw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t { - unsafe { simd_sub(a, simd_cast(b)) } +pub fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a1: int16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: int16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + let mut ret_val: int16x8x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val + } } -#[doc = "Dot product index form with signed and unsigned integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s32)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sudot, LANE = 0) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsudot_lane_s32(a: int32x2_t, b: int8x8_t, c: uint8x8_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); +pub fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { unsafe { - let c: uint32x2_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vusdot_s32(a, transmute(c), b) + let a1: int32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: int32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) } } -#[doc = "Dot product index form with signed and unsigned integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s32)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sudot, LANE = 0) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsudot_lane_s32(a: int32x2_t, b: int8x8_t, c: uint8x8_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - let b: int8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { unsafe { - let c: uint32x2_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - let ret_val: int32x2_t = vusdot_s32(a, transmute(c), b); - simd_shuffle!(ret_val, ret_val, [1, 0]) + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a1: int32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: int32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + let mut ret_val: int32x4x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Dot product index form with signed and unsigned integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u8)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sudot, LANE = 0) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsudotq_lane_s32(a: int32x4_t, b: int8x16_t, c: uint8x8_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); +pub fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { unsafe { - let c: uint32x2_t = transmute(c); - let c: uint32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vusdotq_s32(a, transmute(c), b) + let a1: uint8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: uint8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) } } -#[doc = "Dot product index form with signed and unsigned integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u8)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sudot, LANE = 0) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsudotq_lane_s32(a: int32x4_t, b: int8x16_t, c: uint8x8_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - let b: int8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let c: uint32x2_t = transmute(c); - let c: uint32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - let ret_val: int32x4_t = vusdotq_s32(a, transmute(c), b); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Dot product index form with signed and unsigned integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_laneq_s32)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sudot, LANE = 3) -)] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub fn vsudot_laneq_s32(a: int32x2_t, b: int8x8_t, c: uint8x16_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: uint32x4_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vusdot_s32(a, transmute(c), b) - } -} -#[doc = "Dot product index form with signed and unsigned integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_laneq_s32)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sudot, LANE = 3) -)] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub fn vsudotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: uint8x16_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: uint32x4_t = transmute(c); - let c: uint32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vusdotq_s32(a, transmute(c), b) - } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -fn vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl1")] - fn _vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t; - } - unsafe { _vtbl1(a, b) } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - vtbl1(a, b) -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - unsafe { transmute(vtbl1(transmute(a), transmute(b))) } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vtbl1(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t { - unsafe { transmute(vtbl1(transmute(a), transmute(b))) } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(vtbl1(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -fn vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl2")] - fn _vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t; - } - unsafe { _vtbl2(a, b, c) } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t { - vtbl2(a.0, a.1, b) -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t { - unsafe { transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t { - let mut a: uint8x8x2_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t { - unsafe { transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t { - let mut a: poly8x8x2_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -fn vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl3")] - fn _vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t; +)] +pub fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a1: uint8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: uint8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + let mut ret_val: uint8x8x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } - unsafe { _vtbl3(a, b, c, d) } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t { - vtbl3(a.0, a.1, a.2, b) } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { unsafe { - transmute(vtbl3( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(b), - )) + let a1: uint8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + let b1: uint8x16_t = simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + transmute((a1, b1)) } } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { - let mut a: uint8x8x3_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { unsafe { - let ret_val: uint8x8_t = transmute(vtbl3( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(b), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let a1: uint8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + let b1: uint8x16_t = simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + let mut ret_val: uint8x16x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!( + ret_val.0, + ret_val.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val.1 = simd_shuffle!( + ret_val.1, + ret_val.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val } } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { unsafe { - transmute(vtbl3( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(b), - )) + let a1: uint16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: uint16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) } } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t { - let mut a: poly8x8x3_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { unsafe { - let ret_val: poly8x8_t = transmute(vtbl3( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(b), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a1: uint16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: uint16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + let mut ret_val: uint16x4x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -fn vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl4")] - fn _vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t; +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { + unsafe { + let a1: uint16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: uint16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) } - unsafe { _vtbl4(a, b, c, d, e) } } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t { - vtbl4(a.0, a.1, a.2, a.3, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a1: uint16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: uint16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + let mut ret_val: uint16x8x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val + } } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { unsafe { - transmute(vtbl4( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - transmute(b), - )) + let a1: uint32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: uint32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) } } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { - let mut a: uint8x8x4_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { unsafe { - let ret_val: uint8x8_t = transmute(vtbl4( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - transmute(b), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a1: uint32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: uint32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + let mut ret_val: uint32x4x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { unsafe { - transmute(vtbl4( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - transmute(b), - )) + let a1: poly8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: poly8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) } } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t { - let mut a: poly8x8x4_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { unsafe { - let ret_val: poly8x8_t = transmute(vtbl4( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - transmute(b), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1)"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -fn vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx1")] - fn _vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t; + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a1: poly8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: poly8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + let mut ret_val: poly8x8x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } - unsafe { _vtbx1(a, b, c) } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { - vtbx1(a, b, c) } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p8)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { - unsafe { transmute(vtbx1(transmute(a), transmute(b), transmute(c))) } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { unsafe { - let ret_val: uint8x8_t = transmute(vtbx1(transmute(a), transmute(b), transmute(c))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a1: poly8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + let b1: poly8x16_t = simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + transmute((a1, b1)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t { - unsafe { transmute(vtbx1(transmute(a), transmute(b), transmute(c))) } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p8)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: poly8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { unsafe { - let ret_val: poly8x8_t = transmute(vtbx1(transmute(a), transmute(b), transmute(c))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2)"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -fn vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx2")] - fn _vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t; + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let a1: poly8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + let b1: poly8x16_t = simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + let mut ret_val: poly8x16x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!( + ret_val.0, + ret_val.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val.1 = simd_shuffle!( + ret_val.1, + ret_val.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val } - unsafe { _vtbx2(a, b, c, d) } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_s8)"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t { - vtbx2(a, b.0, b.1, c) } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p16)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t { +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { unsafe { - transmute(vtbx2( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(c), - )) + let a1: poly16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: poly16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p16)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t { - let mut b: uint8x8x2_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { unsafe { - let ret_val: uint8x8_t = transmute(vtbx2( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(c), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a1: poly16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: poly16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + let mut ret_val: poly16x4x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p16)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t { +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrnq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { unsafe { - transmute(vtbx2( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(c), - )) + let a1: poly16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: poly16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p16)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t { - let mut b: poly8x8x2_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrnq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { unsafe { - let ret_val: poly8x8_t = transmute(vtbx2( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(c), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3)"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -fn vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx3")] - fn _vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t; + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a1: poly16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: poly16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + let mut ret_val: poly16x8x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } - unsafe { _vtbx3(a, b, c, d, e) } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t { - vtbx3(a, b.0, b.1, b.2, c) } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t { +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtst_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { unsafe { - transmute(vtbx3( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(c), - )) + let c: int8x8_t = simd_and(a, b); + let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t { - let mut b: uint8x8x3_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtstq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { unsafe { - let ret_val: uint8x8_t = transmute(vtbx3( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(c), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let c: int8x16_t = simd_and(a, b); + let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t { +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtst_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { unsafe { - transmute(vtbx3( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(c), - )) + let c: int16x4_t = simd_and(a, b); + let d: i16x4 = i16x4::new(0, 0, 0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t { - let mut b: poly8x8x3_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtstq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { unsafe { - let ret_val: poly8x8_t = transmute(vtbx3( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(c), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let c: int16x8_t = simd_and(a, b); + let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4)"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -fn vtbx4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t, f: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx4")] - fn _vtbx4( - a: int8x8_t, - b: int8x8_t, - c: int8x8_t, - d: int8x8_t, - e: int8x8_t, - f: int8x8_t, - ) -> int8x8_t; +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtst_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { + unsafe { + let c: int32x2_t = simd_and(a, b); + let d: i32x2 = i32x2::new(0, 0); + simd_ne(c, transmute(d)) } - unsafe { _vtbx4(a, b, c, d, e, f) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t { +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtstq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { unsafe { - vtbx4( - a, - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - ) + let c: int32x4_t = simd_and(a, b); + let d: i32x4 = i32x4::new(0, 0, 0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t { - let mut b: int8x8x4_t = b; - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtst_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t { unsafe { - let ret_val: int8x8_t = vtbx4( - a, - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - ); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let c: poly8x8_t = simd_and(a, b); + let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t { +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtstq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { unsafe { - transmute(vtbx4( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - transmute(c), - )) + let c: poly8x16_t = simd_and(a, b); + let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t { - let mut b: uint8x8x4_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtst_p16(a: poly16x4_t, b: poly16x4_t) -> uint16x4_t { unsafe { - let ret_val: uint8x8_t = transmute(vtbx4( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - transmute(c), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let c: poly16x4_t = simd_and(a, b); + let d: i16x4 = i16x4::new(0, 0, 0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t { +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtstq_p16(a: poly16x8_t, b: poly16x8_t) -> uint16x8_t { unsafe { - transmute(vtbx4( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - transmute(c), - )) + let c: poly16x8_t = simd_and(a, b); + let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t { - let mut b: poly8x8x4_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[doc = "Unsigned compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtst_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe { - let ret_val: poly8x8_t = transmute(vtbx4( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - transmute(c), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let c: uint8x8_t = simd_and(a, b); + let d: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f16)"] -#[inline(always)] +#[doc = "Unsigned compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u8)"] +#[inline] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] +pub fn vtstq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + let c: uint8x16_t = simd_and(a, b); + let d: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) + } +} +#[doc = "Unsigned compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(cmtst) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { +pub fn vtst_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe { - let a1: float16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: float16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) + let c: uint16x4_t = simd_and(a, b); + let d: u16x4 = u16x4::new(0, 0, 0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f16)"] -#[inline(always)] +#[doc = "Unsigned compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u16)"] +#[inline] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] +pub fn vtstq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { + let c: uint16x8_t = simd_and(a, b); + let d: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) + } +} +#[doc = "Unsigned compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(cmtst) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vtrnq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { +pub fn vtst_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe { - let a1: float16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: float16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) + let c: uint32x2_t = simd_and(a, b); + let d: u32x2 = u32x2::new(0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f32)"] -#[inline(always)] +#[doc = "Unsigned compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(zip1) + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtstq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { + let c: uint32x4_t = simd_and(a, b); + let d: u32x4 = u32x4::new(0, 0, 0, 0); + simd_ne(c, transmute(d)) + } +} +#[doc = "Dot product index form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"] +#[inline] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usdot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_i8mm", issue = "117223") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] +pub fn vusdot_lane_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); + let c = vreinterpret_s32_s8(c); + let c = vdup_lane_s32::(c); + vusdot_s32(a, b, vreinterpret_s8_s32(c)) +} +#[doc = "Dot product index form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"] +#[inline] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(zip2) + assert_instr(usdot, LANE = 0) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + unstable(feature = "stdarch_neon_i8mm", issue = "117223") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrn_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { +pub fn vusdotq_lane_s32(a: int32x4_t, b: uint8x16_t, c: int8x8_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 1); + let c = vreinterpret_s32_s8(c); + let c = vdupq_lane_s32::(c); + vusdotq_s32(a, b, vreinterpretq_s8_s32(c)) +} +#[doc = "Dot product index form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usdot, LANE = 3) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub fn vusdot_laneq_s32(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + let c = vreinterpretq_s32_s8(c); + let c = vdup_laneq_s32::(c); + vusdot_s32(a, b, vreinterpret_s8_s32(c)) +} +#[doc = "Dot product index form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usdot, LANE = 3) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub fn vusdotq_laneq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + let c = vreinterpretq_s32_s8(c); + let c = vdupq_laneq_s32::(c); + vusdotq_s32(a, b, vreinterpretq_s8_s32(c)) +} +#[doc = "Dot product vector form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_s32)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))] +#[cfg_attr( + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(usdot) +)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_i8mm", issue = "117223") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.usdot.v2i32.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v2i32.v8i8")] + fn _vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t; + } + unsafe { _vusdot_s32(a, b, c) } +} +#[doc = "Dot product vector form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))] +#[cfg_attr( + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(usdot) +)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_i8mm", issue = "117223") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.usdot.v2i32.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v2i32.v8i8")] + fn _vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t; + } unsafe { - let a1: float32x2_t = simd_shuffle!(a, b, [0, 2]); - let b1: float32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a1, b1)) + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let c: int8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int32x2_t = _vusdot_s32(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Dot product vector form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_s32)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))] +#[cfg_attr( + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(usdot) +)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_i8mm", issue = "117223") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.usdot.v4i32.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v4i32.v16i8")] + fn _vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t; + } + unsafe { _vusdotq_s32(a, b, c) } +} +#[doc = "Dot product vector form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))] +#[cfg_attr( + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(usdot) +)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_i8mm", issue = "117223") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.usdot.v4i32.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v4i32.v16i8")] + fn _vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t; + } + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let c: int8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int32x4_t = _vusdotq_s32(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unsigned and signed 8-bit integer matrix multiply-accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusmmlaq_s32)"] +#[inline] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usmmla) +)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_i8mm", issue = "117223") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.usmmla.v4i32.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usmmla.v4i32.v16i8")] + fn _vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t; + } + unsafe { _vusmmlaq_s32(a, b, c) } +} +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(zip1) + assert_instr(uzp1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(zip2) + assert_instr(uzp2) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrn_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { unsafe { - let a1: int32x2_t = simd_shuffle!(a, b, [0, 2]); - let b1: int32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a1, b1)) + let a0: float16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: float16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(zip1) + assert_instr(uzp1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(zip2) + assert_instr(uzp2) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { unsafe { - let a1: uint32x2_t = simd_shuffle!(a, b, [0, 2]); - let b1: uint32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a1, b1)) + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: float16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: float16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + let mut ret_val: float16x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(uzp1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(uzp2) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrnq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vuzpq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { unsafe { - let a1: float32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: float32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) + let a0: float16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: float16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(uzp1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(uzp2) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vuzpq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { unsafe { - let a1: int8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: int8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: float16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: float16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + let mut ret_val: float16x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s8)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -74730,34 +68699,27 @@ pub fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { +pub fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { unsafe { - let a1: int8x16_t = simd_shuffle!( - a, - b, - [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] - ); - let b1: int8x16_t = simd_shuffle!( - a, - b, - [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] - ); - transmute((a1, b1)) + let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a0, b0)) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -74767,26 +68729,32 @@ pub fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { +pub fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { unsafe { - let a1: int16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: int16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]); + let mut ret_val: float32x2x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]); + ret_val } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -74796,26 +68764,27 @@ pub fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { +pub fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { unsafe { - let a1: int16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: int16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) + let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a0, b0)) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -74825,26 +68794,32 @@ pub fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { +pub fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { unsafe { - let a1: int32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: int32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]); + let mut ret_val: int32x2x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]); + ret_val } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u8)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -74854,26 +68829,27 @@ pub fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { +pub fn vuzp_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { unsafe { - let a1: uint8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: uint8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) + let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a0, b0)) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u8)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -74883,34 +68859,32 @@ pub fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { +pub fn vuzp_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { unsafe { - let a1: uint8x16_t = simd_shuffle!( - a, - b, - [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] - ); - let b1: uint8x16_t = simd_shuffle!( - a, - b, - [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] - ); - transmute((a1, b1)) + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]); + let mut ret_val: uint32x2x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]); + ret_val } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(uzp1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -74920,26 +68894,27 @@ pub fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { +pub fn vuzpq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { unsafe { - let a1: uint16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: uint16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) + let a0: float32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: float32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(uzp1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -74949,26 +68924,32 @@ pub fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { +pub fn vuzpq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { unsafe { - let a1: uint16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: uint16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: float32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: float32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + let mut ret_val: float32x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(uzp1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -74978,26 +68959,27 @@ pub fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { +pub fn vuzp_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { unsafe { - let a1: uint32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: uint32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) + let a0: int8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: int8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p8)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(uzp1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -75007,26 +68989,32 @@ pub fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { +pub fn vuzp_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { unsafe { - let a1: poly8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: poly8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: int8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: int8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + let mut ret_val: int8x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p8)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(uzp1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -75036,34 +69024,35 @@ pub fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { +pub fn vuzpq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { unsafe { - let a1: poly8x16_t = simd_shuffle!( + let a0: int8x16_t = simd_shuffle!( a, b, - [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] ); - let b1: poly8x16_t = simd_shuffle!( + let b0: int8x16_t = simd_shuffle!( a, b, - [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] ); - transmute((a1, b1)) + transmute((a0, b0)) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(uzp1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -75073,26 +69062,50 @@ pub fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { +pub fn vuzpq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { unsafe { - let a1: poly16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: poly16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let a0: int8x16_t = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ); + let b0: int8x16_t = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ); + let mut ret_val: int8x16x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!( + ret_val.0, + ret_val.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val.1 = simd_shuffle!( + ret_val.1, + ret_val.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(uzp1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -75102,47 +69115,27 @@ pub fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrnq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { +pub fn vuzp_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { unsafe { - let a1: poly16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: poly16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) + let a0: int16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: int16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) } } -#[doc = "Signed compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s8)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(uzp1) )] -pub fn vtst_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { - unsafe { - let c: int8x8_t = simd_and(a, b); - let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) - } -} -#[doc = "Signed compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -75152,22 +69145,32 @@ pub fn vtst_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtstq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { +pub fn vuzp_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { unsafe { - let c: int8x16_t = simd_and(a, b); - let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: int16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: int16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + let mut ret_val: int16x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Signed compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -75177,22 +69180,27 @@ pub fn vtstq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtst_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { +pub fn vuzpq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { unsafe { - let c: int16x4_t = simd_and(a, b); - let d: i16x4 = i16x4::new(0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a0: int16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: int16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) } } -#[doc = "Signed compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -75202,22 +69210,32 @@ pub fn vtst_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtstq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { +pub fn vuzpq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { unsafe { - let c: int16x8_t = simd_and(a, b); - let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: int16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: int16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + let mut ret_val: int16x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } -#[doc = "Signed compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -75227,22 +69245,27 @@ pub fn vtstq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtst_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { +pub fn vuzpq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { unsafe { - let c: int32x2_t = simd_and(a, b); - let d: i32x2 = i32x2::new(0, 0); - simd_ne(c, transmute(d)) + let a0: int32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: int32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) } } -#[doc = "Signed compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -75252,22 +69275,32 @@ pub fn vtst_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtstq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { +pub fn vuzpq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { unsafe { - let c: int32x4_t = simd_and(a, b); - let d: i32x4 = i32x4::new(0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: int32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: int32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + let mut ret_val: int32x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Signed compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p8)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -75277,22 +69310,27 @@ pub fn vtstq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtst_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t { +pub fn vuzp_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { unsafe { - let c: poly8x8_t = simd_and(a, b); - let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a0: uint8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: uint8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) } } -#[doc = "Signed compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p8)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -75302,22 +69340,32 @@ pub fn vtst_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtstq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { +pub fn vuzp_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { unsafe { - let c: poly8x16_t = simd_and(a, b); - let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: uint8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: uint8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + let mut ret_val: uint8x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } -#[doc = "Signed compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -75327,22 +69375,35 @@ pub fn vtstq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtst_p16(a: poly16x4_t, b: poly16x4_t) -> uint16x4_t { +pub fn vuzpq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { unsafe { - let c: poly16x4_t = simd_and(a, b); - let d: i16x4 = i16x4::new(0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a0: uint8x16_t = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ); + let b0: uint8x16_t = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ); + transmute((a0, b0)) } } -#[doc = "Signed compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -75352,22 +69413,50 @@ pub fn vtst_p16(a: poly16x4_t, b: poly16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtstq_p16(a: poly16x8_t, b: poly16x8_t) -> uint16x8_t { +pub fn vuzpq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { unsafe { - let c: poly16x8_t = simd_and(a, b); - let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let a0: uint8x16_t = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ); + let b0: uint8x16_t = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ); + let mut ret_val: uint8x16x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!( + ret_val.0, + ret_val.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val.1 = simd_shuffle!( + ret_val.1, + ret_val.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val } } -#[doc = "Unsigned compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u8)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -75377,22 +69466,27 @@ pub fn vtstq_p16(a: poly16x8_t, b: poly16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtst_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vuzp_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { unsafe { - let c: uint8x8_t = simd_and(a, b); - let d: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a0: uint16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: uint16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) } } -#[doc = "Unsigned compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u8)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -75402,22 +69496,32 @@ pub fn vtst_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtstq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { +pub fn vuzp_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { unsafe { - let c: uint8x16_t = simd_and(a, b); - let d: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: uint16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: uint16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + let mut ret_val: uint16x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Unsigned compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -75427,22 +69531,27 @@ pub fn vtstq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtst_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vuzpq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { unsafe { - let c: uint16x4_t = simd_and(a, b); - let d: u16x4 = u16x4::new(0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a0: uint16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: uint16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) } } -#[doc = "Unsigned compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -75452,22 +69561,32 @@ pub fn vtst_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtstq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vuzpq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { unsafe { - let c: uint16x8_t = simd_and(a, b); - let d: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: uint16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: uint16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + let mut ret_val: uint16x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } -#[doc = "Unsigned compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -75477,22 +69596,27 @@ pub fn vtstq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtst_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vuzpq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { unsafe { - let c: uint32x2_t = simd_and(a, b); - let d: u32x2 = u32x2::new(0, 0); - simd_ne(c, transmute(d)) + let a0: uint32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: uint32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) } } -#[doc = "Unsigned compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -75502,323 +69626,274 @@ pub fn vtst_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtstq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vuzpq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { unsafe { - let c: uint32x4_t = simd_and(a, b); - let d: u32x4 = u32x4::new(0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: uint32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: uint32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + let mut ret_val: uint32x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Dot product index form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p8)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usdot, LANE = 0) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vusdot_lane_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); +pub fn vuzp_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { unsafe { - let c: int32x2_t = transmute(c); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vusdot_s32(a, b, transmute(c)) + let a0: poly8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: poly8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) } } -#[doc = "Dot product index form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p8)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usdot, LANE = 0) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vusdot_lane_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vuzp_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { unsafe { - let c: int32x2_t = transmute(c); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - let ret_val: int32x2_t = vusdot_s32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [1, 0]) + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: poly8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: poly8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + let mut ret_val: poly8x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } -#[doc = "Dot product index form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p8)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usdot, LANE = 0) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vusdotq_lane_s32(a: int32x4_t, b: uint8x16_t, c: int8x8_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); +pub fn vuzpq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { unsafe { - let c: int32x2_t = transmute(c); - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vusdotq_s32(a, b, transmute(c)) + let a0: poly8x16_t = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ); + let b0: poly8x16_t = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ); + transmute((a0, b0)) } } -#[doc = "Dot product index form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p8)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usdot, LANE = 0) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vusdotq_lane_s32(a: int32x4_t, b: uint8x16_t, c: int8x8_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vuzpq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { unsafe { - let c: int32x2_t = transmute(c); - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - let ret_val: int32x4_t = vusdotq_s32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let a0: poly8x16_t = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ); + let b0: poly8x16_t = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ); + let mut ret_val: poly8x16x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!( + ret_val.0, + ret_val.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val.1 = simd_shuffle!( + ret_val.1, + ret_val.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val } } -#[doc = "Dot product index form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p16)"] +#[inline] #[cfg(target_endian = "little")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usdot, LANE = 3) + assert_instr(uzp1) )] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub fn vusdot_laneq_s32(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: int32x4_t = transmute(c); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vusdot_s32(a, b, transmute(c)) - } -} -#[doc = "Dot product index form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usdot, LANE = 3) + assert_instr(uzp2) )] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub fn vusdot_laneq_s32(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: int8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let c: int32x4_t = transmute(c); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - let ret_val: int32x2_t = vusdot_s32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Dot product index form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usdot, LANE = 3) + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") )] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub fn vusdotq_laneq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vuzp_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { unsafe { - let c: int32x4_t = transmute(c); - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vusdotq_s32(a, b, transmute(c)) + let a0: poly16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: poly16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) } } -#[doc = "Dot product index form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p16)"] +#[inline] #[cfg(target_endian = "big")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usdot, LANE = 3) + assert_instr(uzp1) )] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub fn vusdotq_laneq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: int8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let c: int32x4_t = transmute(c); - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - let ret_val: int32x4_t = vusdotq_s32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Dot product vector form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_s32)"] -#[inline(always)] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usdot) + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.usdot.v2i32.v8i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v2i32.v8i8")] - fn _vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t; +pub fn vuzp_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { + unsafe { + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: poly16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: poly16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + let mut ret_val: poly16x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } - unsafe { _vusdot_s32(a, b, c) } } -#[doc = "Dot product vector form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p16)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usdot) -)] -#[cfg_attr( - not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(uzp1) )] -pub fn vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.usdot.v4i32.v16i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v4i32.v16i8")] - fn _vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t; - } - unsafe { _vusdotq_s32(a, b, c) } -} -#[doc = "Unsigned and signed 8-bit integer matrix multiply-accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusmmlaq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usmmla) + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.usmmla.v4i32.v16i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usmmla.v4i32.v16i8")] - fn _vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t; +pub fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { + unsafe { + let a0: poly16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: poly16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) } - unsafe { _vusmmlaq_s32(a, b, c) } } #[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( @@ -75829,59 +69904,63 @@ pub fn vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uzp2) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { +pub fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { unsafe { - let a0: float16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: float16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); - transmute((a0, b0)) + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: poly16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: poly16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + let mut ret_val: poly16x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f16)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vuzpq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { +pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { unsafe { - let a0: float16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: float16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + let a0: float16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: float16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); transmute((a0, b0)) } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -75890,27 +69969,34 @@ pub fn vuzpq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip2) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { unsafe { - let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a0, b0)) + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: float16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: float16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + let mut ret_val: float16x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -75919,27 +70005,29 @@ pub fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip2) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vzipq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { unsafe { - let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]); + let a0: float16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: float16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); transmute((a0, b0)) } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -75948,34 +70036,42 @@ pub fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip2) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzp_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vzipq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { unsafe { - let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a0, b0)) + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: float16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: float16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let mut ret_val: float16x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f32)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -75985,26 +70081,27 @@ pub fn vuzp_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzpq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { +pub fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { unsafe { - let a0: float32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: float32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]); transmute((a0, b0)) } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s8)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -76014,26 +70111,32 @@ pub fn vuzpq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzp_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { +pub fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { unsafe { - let a0: int8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: int8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); - transmute((a0, b0)) + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]); + let mut ret_val: float32x2x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]); + ret_val } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s8)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -76043,34 +70146,27 @@ pub fn vuzp_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzpq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { +pub fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { unsafe { - let a0: int8x16_t = simd_shuffle!( - a, - b, - [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] - ); - let b0: int8x16_t = simd_shuffle!( - a, - b, - [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] - ); + let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]); transmute((a0, b0)) } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s16)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -76080,26 +70176,32 @@ pub fn vuzpq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzp_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { +pub fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { unsafe { - let a0: int16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: int16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); - transmute((a0, b0)) + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]); + let mut ret_val: int32x2x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]); + ret_val } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s16)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -76109,26 +70211,27 @@ pub fn vuzp_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzpq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { +pub fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { unsafe { - let a0: int16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: int16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]); transmute((a0, b0)) } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s32)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -76138,26 +70241,32 @@ pub fn vuzpq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzpq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { +pub fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { unsafe { - let a0: int32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: int32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); - transmute((a0, b0)) + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]); + let mut ret_val: uint32x2x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]); + ret_val } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u8)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -76167,26 +70276,27 @@ pub fn vuzpq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzp_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { +pub fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { unsafe { - let a0: uint8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: uint8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + let a0: int8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: int8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); transmute((a0, b0)) } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u8)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -76196,34 +70306,32 @@ pub fn vuzp_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzpq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { +pub fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { unsafe { - let a0: uint8x16_t = simd_shuffle!( - a, - b, - [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] - ); - let b0: uint8x16_t = simd_shuffle!( - a, - b, - [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] - ); - transmute((a0, b0)) + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: int8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: int8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let mut ret_val: int8x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u16)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -76233,26 +70341,27 @@ pub fn vuzpq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzp_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { +pub fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { unsafe { - let a0: uint16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: uint16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + let a0: int16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: int16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); transmute((a0, b0)) } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u16)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -76262,26 +70371,32 @@ pub fn vuzp_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzpq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { +pub fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { unsafe { - let a0: uint16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: uint16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); - transmute((a0, b0)) + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: int16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: int16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + let mut ret_val: int16x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u32)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -76291,26 +70406,27 @@ pub fn vuzpq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzpq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { +pub fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { unsafe { - let a0: uint32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: uint32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + let a0: uint8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: uint8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); transmute((a0, b0)) } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p8)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -76320,26 +70436,32 @@ pub fn vuzpq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzp_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { +pub fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { unsafe { - let a0: poly8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: poly8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); - transmute((a0, b0)) + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: uint8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: uint8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let mut ret_val: uint8x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p8)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -76349,34 +70471,27 @@ pub fn vuzp_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzpq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { +pub fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { unsafe { - let a0: poly8x16_t = simd_shuffle!( - a, - b, - [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] - ); - let b0: poly8x16_t = simd_shuffle!( - a, - b, - [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] - ); + let a0: uint16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: uint16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); transmute((a0, b0)) } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p16)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -76386,26 +70501,32 @@ pub fn vuzpq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzp_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { +pub fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { unsafe { - let a0: poly16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: poly16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); - transmute((a0, b0)) + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: uint16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: uint16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + let mut ret_val: uint16x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p16)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -76415,18 +70536,20 @@ pub fn vuzp_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { +pub fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { unsafe { - let a0: poly16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: poly16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + let a0: poly8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: poly8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); transmute((a0, b0)) } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -76435,28 +70558,33 @@ pub fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip2) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { +pub fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { unsafe { - let a0: float16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: float16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); - transmute((a0, b0)) + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: poly8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: poly8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let mut ret_val: poly8x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p16)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -76465,29 +70593,28 @@ pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip2) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vzipq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { +pub fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { unsafe { - let a0: float16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: float16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let a0: poly16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: poly16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); transmute((a0, b0)) } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -76504,19 +70631,25 @@ pub fn vzipq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { +pub fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { unsafe { - let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a0, b0)) + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: poly16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: poly16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + let mut ret_val: poly16x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -76533,19 +70666,20 @@ pub fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { +pub fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { unsafe { - let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]); + let a0: float32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: float32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); transmute((a0, b0)) } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -76562,19 +70696,25 @@ pub fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { +pub fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { unsafe { - let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a0, b0)) + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: float32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: float32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + let mut ret_val: float32x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -76591,19 +70731,28 @@ pub fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { +pub fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { unsafe { - let a0: int8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: int8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let a0: int8x16_t = simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ); + let b0: int8x16_t = simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ); transmute((a0, b0)) } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -76620,19 +70769,43 @@ pub fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { +pub fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { unsafe { - let a0: int16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: int16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); - transmute((a0, b0)) + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let a0: int8x16_t = simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ); + let b0: int8x16_t = simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ); + let mut ret_val: int8x16x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!( + ret_val.0, + ret_val.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val.1 = simd_shuffle!( + ret_val.1, + ret_val.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -76649,19 +70822,20 @@ pub fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { +pub fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { unsafe { - let a0: uint8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: uint8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let a0: int16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: int16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); transmute((a0, b0)) } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -76678,19 +70852,25 @@ pub fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { +pub fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { unsafe { - let a0: uint16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: uint16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); - transmute((a0, b0)) + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: int16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: int16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let mut ret_val: int16x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -76707,19 +70887,20 @@ pub fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { +pub fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { unsafe { - let a0: poly8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: poly8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let a0: int32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: int32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); transmute((a0, b0)) } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -76736,16 +70917,22 @@ pub fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { +pub fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { unsafe { - let a0: poly16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: poly16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); - transmute((a0, b0)) + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: int32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: int32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + let mut ret_val: int32x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -76765,16 +70952,25 @@ pub fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { +pub fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { unsafe { - let a0: float32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: float32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + let a0: uint8x16_t = simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ); + let b0: uint8x16_t = simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ); transmute((a0, b0)) } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -76794,24 +70990,40 @@ pub fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { +pub fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { unsafe { - let a0: int8x16_t = simd_shuffle!( + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let a0: uint8x16_t = simd_shuffle!( a, b, [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] ); - let b0: int8x16_t = simd_shuffle!( + let b0: uint8x16_t = simd_shuffle!( a, b, [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] ); - transmute((a0, b0)) + let mut ret_val: uint8x16x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!( + ret_val.0, + ret_val.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val.1 = simd_shuffle!( + ret_val.1, + ret_val.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -76831,16 +71043,17 @@ pub fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { +pub fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { unsafe { - let a0: int16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: int16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let a0: uint16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: uint16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); transmute((a0, b0)) } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -76860,16 +71073,22 @@ pub fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { +pub fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { unsafe { - let a0: int32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: int32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); - transmute((a0, b0)) + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: uint16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: uint16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let mut ret_val: uint16x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -76889,24 +71108,17 @@ pub fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { +pub fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { unsafe { - let a0: uint8x16_t = simd_shuffle!( - a, - b, - [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] - ); - let b0: uint8x16_t = simd_shuffle!( - a, - b, - [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] - ); + let a0: uint32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: uint32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); transmute((a0, b0)) } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -76926,16 +71138,22 @@ pub fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { +pub fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { unsafe { - let a0: uint16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: uint16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); - transmute((a0, b0)) + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: uint32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: uint32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + let mut ret_val: uint32x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -76955,16 +71173,25 @@ pub fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { +pub fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { unsafe { - let a0: uint32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: uint32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + let a0: poly8x16_t = simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ); + let b0: poly8x16_t = simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ); transmute((a0, b0)) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -76986,6 +71213,10 @@ pub fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { )] pub fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); let a0: poly8x16_t = simd_shuffle!( a, b, @@ -76996,12 +71227,24 @@ pub fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { b, [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] ); - transmute((a0, b0)) + let mut ret_val: poly8x16x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!( + ret_val.0, + ret_val.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val.1 = simd_shuffle!( + ret_val.1, + ret_val.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -77028,3 +71271,38 @@ pub fn vzipq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { transmute((a0, b0)) } } +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vzipq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: poly16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: poly16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let mut ret_val: poly16x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val + } +} diff --git a/library/stdarch/crates/core_arch/src/arm_shared/neon/load_tests.rs b/library/stdarch/crates/core_arch/src/arm_shared/neon/load_tests.rs index cc821b4af2025..70a37f7c05dad 100644 --- a/library/stdarch/crates/core_arch/src/arm_shared/neon/load_tests.rs +++ b/library/stdarch/crates/core_arch/src/arm_shared/neon/load_tests.rs @@ -190,6 +190,24 @@ fn test_vld1q_p64() { assert_eq!(r, e) } +#[cfg(not(target_arch = "arm64ec"))] +#[simd_test(enable = "neon,fp16")] +fn test_vld1_f16() { + let a: [f16; 5] = [0., 1., 2., 3., 4.]; + let e = f16x4::new(1., 2., 3., 4.); + let r = unsafe { f16x4::from(vld1_f16(a[1..].as_ptr())) }; + assert_eq!(r, e) +} + +#[cfg(not(target_arch = "arm64ec"))] +#[simd_test(enable = "neon,fp16")] +fn test_vld1q_f16() { + let a: [f16; 9] = [0., 1., 2., 3., 4., 5., 6., 7., 8.]; + let e = f16x8::new(1., 2., 3., 4., 5., 6., 7., 8.); + let r = unsafe { f16x8::from(vld1q_f16(a[1..].as_ptr())) }; + assert_eq!(r, e) +} + #[simd_test(enable = "neon")] fn test_vld1_f32() { let a: [f32; 3] = [0., 1., 2.]; diff --git a/library/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs b/library/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs index 1ca8ce2b13954..3af59b1dfb7cb 100644 --- a/library/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs +++ b/library/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs @@ -7,7 +7,7 @@ mod generated; #[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] pub use self::generated::*; -use crate::{core_arch::simd::*, hint::unreachable_unchecked, intrinsics::simd::*, mem::transmute}; +use crate::{core_arch::simd::*, intrinsics::simd::*, mem::transmute}; #[cfg(test)] use stdarch_test::assert_instr; @@ -104,7 +104,7 @@ types! { } types! { - #![cfg_attr(not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION"))] + #![cfg_attr(not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "1.94.0"))] #![cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] /// Arm-specific 64-bit wide vector of four packed `f16`. @@ -750,7 +750,7 @@ pub struct uint32x4x4_t( #[derive(Copy, Clone, Debug)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -763,7 +763,7 @@ pub struct float16x4x2_t(pub float16x4_t, pub float16x4_t); #[derive(Copy, Clone, Debug)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -776,7 +776,7 @@ pub struct float16x4x3_t(pub float16x4_t, pub float16x4_t, pub float16x4_t); #[derive(Copy, Clone, Debug)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -794,7 +794,7 @@ pub struct float16x4x4_t( #[derive(Copy, Clone, Debug)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -807,7 +807,7 @@ pub struct float16x8x2_t(pub float16x8_t, pub float16x8_t); #[derive(Copy, Clone, Debug)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -820,7 +820,7 @@ pub struct float16x8x3_t(pub float16x8_t, pub float16x8_t, pub float16x8_t); #[derive(Copy, Clone, Debug)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -1663,235 +1663,6 @@ mod tests { assert_eq!(r, e) } - #[simd_test(enable = "neon")] - fn test_vget_lane_u8() { - let v = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r = vget_lane_u8::<1>(v.into()); - assert_eq!(r, 2); - } - - #[simd_test(enable = "neon")] - fn test_vgetq_lane_u32() { - let v = u32x4::new(1, 2, 3, 4); - let r = vgetq_lane_u32::<1>(v.into()); - assert_eq!(r, 2); - } - - #[simd_test(enable = "neon")] - fn test_vgetq_lane_s32() { - let v = i32x4::new(1, 2, 3, 4); - let r = vgetq_lane_s32::<1>(v.into()); - assert_eq!(r, 2); - } - - #[simd_test(enable = "neon")] - fn test_vget_lane_u64() { - let v = u64x1::new(1); - let r = vget_lane_u64::<0>(v.into()); - assert_eq!(r, 1); - } - - #[simd_test(enable = "neon")] - fn test_vgetq_lane_u16() { - let v = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r = vgetq_lane_u16::<1>(v.into()); - assert_eq!(r, 2); - } - - #[simd_test(enable = "neon")] - fn test_vget_lane_s8() { - let v = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r = vget_lane_s8::<2>(v.into()); - assert_eq!(r, 2); - let r = vget_lane_s8::<4>(v.into()); - assert_eq!(r, 4); - let r = vget_lane_s8::<5>(v.into()); - assert_eq!(r, 5); - } - - #[simd_test(enable = "neon")] - fn test_vget_lane_p8() { - let v = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r = vget_lane_p8::<2>(v.into()); - assert_eq!(r, 2); - let r = vget_lane_p8::<3>(v.into()); - assert_eq!(r, 3); - let r = vget_lane_p8::<5>(v.into()); - assert_eq!(r, 5); - } - - #[simd_test(enable = "neon")] - fn test_vget_lane_p16() { - let v = u16x4::new(0, 1, 2, 3); - let r = vget_lane_p16::<2>(v.into()); - assert_eq!(r, 2); - let r = vget_lane_p16::<3>(v.into()); - assert_eq!(r, 3); - let r = vget_lane_p16::<0>(v.into()); - assert_eq!(r, 0); - let r = vget_lane_p16::<1>(v.into()); - assert_eq!(r, 1); - } - - #[simd_test(enable = "neon")] - fn test_vget_lane_s16() { - let v = i16x4::new(0, 1, 2, 3); - let r = vget_lane_s16::<2>(v.into()); - assert_eq!(r, 2); - let r = vget_lane_s16::<3>(v.into()); - assert_eq!(r, 3); - let r = vget_lane_s16::<0>(v.into()); - assert_eq!(r, 0); - let r = vget_lane_s16::<1>(v.into()); - assert_eq!(r, 1); - } - - #[simd_test(enable = "neon")] - fn test_vget_lane_u16() { - let v = u16x4::new(0, 1, 2, 3); - let r = vget_lane_u16::<2>(v.into()); - assert_eq!(r, 2); - let r = vget_lane_u16::<3>(v.into()); - assert_eq!(r, 3); - let r = vget_lane_u16::<0>(v.into()); - assert_eq!(r, 0); - let r = vget_lane_u16::<1>(v.into()); - assert_eq!(r, 1); - } - - #[simd_test(enable = "neon")] - fn test_vget_lane_f32() { - let v = f32x2::new(0.0, 1.0); - let r = vget_lane_f32::<1>(v.into()); - assert_eq!(r, 1.0); - let r = vget_lane_f32::<0>(v.into()); - assert_eq!(r, 0.0); - } - - #[simd_test(enable = "neon")] - fn test_vget_lane_s32() { - let v = i32x2::new(0, 1); - let r = vget_lane_s32::<1>(v.into()); - assert_eq!(r, 1); - let r = vget_lane_s32::<0>(v.into()); - assert_eq!(r, 0); - } - - #[simd_test(enable = "neon")] - fn test_vget_lane_u32() { - let v = u32x2::new(0, 1); - let r = vget_lane_u32::<1>(v.into()); - assert_eq!(r, 1); - let r = vget_lane_u32::<0>(v.into()); - assert_eq!(r, 0); - } - - #[simd_test(enable = "neon")] - fn test_vget_lane_s64() { - let v = i64x1::new(1); - let r = vget_lane_s64::<0>(v.into()); - assert_eq!(r, 1); - } - - #[simd_test(enable = "neon")] - fn test_vget_lane_p64() { - let v = u64x1::new(1); - let r = vget_lane_p64::<0>(v.into()); - assert_eq!(r, 1); - } - - #[simd_test(enable = "neon")] - fn test_vgetq_lane_s8() { - let v = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let r = vgetq_lane_s8::<7>(v.into()); - assert_eq!(r, 7); - let r = vgetq_lane_s8::<13>(v.into()); - assert_eq!(r, 13); - let r = vgetq_lane_s8::<3>(v.into()); - assert_eq!(r, 3); - let r = vgetq_lane_s8::<0>(v.into()); - assert_eq!(r, 0); - } - - #[simd_test(enable = "neon")] - fn test_vgetq_lane_p8() { - let v = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let r = vgetq_lane_p8::<7>(v.into()); - assert_eq!(r, 7); - let r = vgetq_lane_p8::<13>(v.into()); - assert_eq!(r, 13); - let r = vgetq_lane_p8::<3>(v.into()); - assert_eq!(r, 3); - let r = vgetq_lane_p8::<0>(v.into()); - assert_eq!(r, 0); - } - - #[simd_test(enable = "neon")] - fn test_vgetq_lane_u8() { - let v = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let r = vgetq_lane_u8::<7>(v.into()); - assert_eq!(r, 7); - let r = vgetq_lane_u8::<13>(v.into()); - assert_eq!(r, 13); - let r = vgetq_lane_u8::<3>(v.into()); - assert_eq!(r, 3); - let r = vgetq_lane_u8::<0>(v.into()); - assert_eq!(r, 0); - } - - #[simd_test(enable = "neon")] - fn test_vgetq_lane_s16() { - let v = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r = vgetq_lane_s16::<3>(v.into()); - assert_eq!(r, 3); - let r = vgetq_lane_s16::<6>(v.into()); - assert_eq!(r, 6); - let r = vgetq_lane_s16::<0>(v.into()); - assert_eq!(r, 0); - } - - #[simd_test(enable = "neon")] - fn test_vgetq_lane_p16() { - let v = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r = vgetq_lane_p16::<3>(v.into()); - assert_eq!(r, 3); - let r = vgetq_lane_p16::<7>(v.into()); - assert_eq!(r, 7); - let r = vgetq_lane_p16::<1>(v.into()); - assert_eq!(r, 1); - } - - #[simd_test(enable = "neon")] - fn test_vgetq_lane_f32() { - let v = f32x4::new(0.0, 1.0, 2.0, 3.0); - let r = vgetq_lane_f32::<3>(v.into()); - assert_eq!(r, 3.0); - let r = vgetq_lane_f32::<0>(v.into()); - assert_eq!(r, 0.0); - let r = vgetq_lane_f32::<2>(v.into()); - assert_eq!(r, 2.0); - let r = vgetq_lane_f32::<1>(v.into()); - assert_eq!(r, 1.0); - } - - #[simd_test(enable = "neon")] - fn test_vgetq_lane_s64() { - let v = i64x2::new(0, 1); - let r = vgetq_lane_s64::<1>(v.into()); - assert_eq!(r, 1); - let r = vgetq_lane_s64::<0>(v.into()); - assert_eq!(r, 0); - } - - #[simd_test(enable = "neon")] - fn test_vgetq_lane_p64() { - let v = u64x2::new(0, 1); - let r = vgetq_lane_p64::<1>(v.into()); - assert_eq!(r, 1); - let r = vgetq_lane_p64::<0>(v.into()); - assert_eq!(r, 0); - } - #[simd_test(enable = "neon")] fn test_vext_s64() { let a: i64x1 = i64x1::new(0); @@ -1910,182 +1681,6 @@ mod tests { assert_eq!(r, e); } - #[simd_test(enable = "neon")] - fn test_vget_high_s8() { - let a = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e = i8x8::new(9, 10, 11, 12, 13, 14, 15, 16); - let r = i8x8::from(vget_high_s8(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_high_s16() { - let a = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e = i16x4::new(5, 6, 7, 8); - let r = i16x4::from(vget_high_s16(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_high_s32() { - let a = i32x4::new(1, 2, 3, 4); - let e = i32x2::new(3, 4); - let r = i32x2::from(vget_high_s32(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_high_s64() { - let a = i64x2::new(1, 2); - let e = i64x1::new(2); - let r = i64x1::from(vget_high_s64(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_high_u8() { - let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e = u8x8::new(9, 10, 11, 12, 13, 14, 15, 16); - let r = u8x8::from(vget_high_u8(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_high_u16() { - let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e = u16x4::new(5, 6, 7, 8); - let r = u16x4::from(vget_high_u16(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_high_u32() { - let a = u32x4::new(1, 2, 3, 4); - let e = u32x2::new(3, 4); - let r = u32x2::from(vget_high_u32(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_high_u64() { - let a = u64x2::new(1, 2); - let e = u64x1::new(2); - let r = u64x1::from(vget_high_u64(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_high_p8() { - let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e = u8x8::new(9, 10, 11, 12, 13, 14, 15, 16); - let r = u8x8::from(vget_high_p8(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_high_p16() { - let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e = u16x4::new(5, 6, 7, 8); - let r = u16x4::from(vget_high_p16(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_high_f32() { - let a = f32x4::new(1.0, 2.0, 3.0, 4.0); - let e = f32x2::new(3.0, 4.0); - let r = f32x2::from(vget_high_f32(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_s8() { - let a = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r = i8x8::from(vget_low_s8(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_s16() { - let a = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e = i16x4::new(1, 2, 3, 4); - let r = i16x4::from(vget_low_s16(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_s32() { - let a = i32x4::new(1, 2, 3, 4); - let e = i32x2::new(1, 2); - let r = i32x2::from(vget_low_s32(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_s64() { - let a = i64x2::new(1, 2); - let e = i64x1::new(1); - let r = i64x1::from(vget_low_s64(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_u8() { - let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r = u8x8::from(vget_low_u8(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_u16() { - let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e = u16x4::new(1, 2, 3, 4); - let r = u16x4::from(vget_low_u16(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_u32() { - let a = u32x4::new(1, 2, 3, 4); - let e = u32x2::new(1, 2); - let r = u32x2::from(vget_low_u32(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_u64() { - let a = u64x2::new(1, 2); - let e = u64x1::new(1); - let r = u64x1::from(vget_low_u64(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_p8() { - let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r = u8x8::from(vget_low_p8(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_p16() { - let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e = u16x4::new(1, 2, 3, 4); - let r = u16x4::from(vget_low_p16(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_f32() { - let a = f32x4::new(1.0, 2.0, 3.0, 4.0); - let e = f32x2::new(1.0, 2.0); - let r = f32x2::from(vget_low_f32(a.into())); - assert_eq!(r, e); - } - #[simd_test(enable = "neon")] fn test_vdupq_n_s8() { let v: i8 = 42; @@ -2469,13 +2064,6 @@ mod tests { assert_eq!(r, e); } - #[simd_test(enable = "neon")] - fn test_vgetq_lane_u64() { - let v = u64x2::new(1, 2); - let r = vgetq_lane_u64::<1>(v.into()); - assert_eq!(r, 2); - } - #[simd_test(enable = "neon")] fn test_vadd_s8() { test_ari_s8( @@ -2638,72 +2226,6 @@ mod tests { assert_eq!(r, e); } - #[simd_test(enable = "neon")] - fn test_vaddl_high_s8() { - let a = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let x = i8::MAX; - let b = i8x16::new(x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x); - let x = x as i16; - let e = i16x8::new(x + 8, x + 9, x + 10, x + 11, x + 12, x + 13, x + 14, x + 15); - let r = i16x8::from(vaddl_high_s8(a.into(), b.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vaddl_high_s16() { - let a = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let x = i16::MAX; - let b = i16x8::new(x, x, x, x, x, x, x, x); - let x = x as i32; - let e = i32x4::new(x + 4, x + 5, x + 6, x + 7); - let r = i32x4::from(vaddl_high_s16(a.into(), b.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vaddl_high_s32() { - let a = i32x4::new(0, 1, 2, 3); - let x = i32::MAX; - let b = i32x4::new(x, x, x, x); - let x = x as i64; - let e = i64x2::new(x + 2, x + 3); - let r = i64x2::from(vaddl_high_s32(a.into(), b.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vaddl_high_u8() { - let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let x = u8::MAX; - let b = u8x16::new(x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x); - let x = x as u16; - let e = u16x8::new(x + 8, x + 9, x + 10, x + 11, x + 12, x + 13, x + 14, x + 15); - let r = u16x8::from(vaddl_high_u8(a.into(), b.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vaddl_high_u16() { - let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let x = u16::MAX; - let b = u16x8::new(x, x, x, x, x, x, x, x); - let x = x as u32; - let e = u32x4::new(x + 4, x + 5, x + 6, x + 7); - let r = u32x4::from(vaddl_high_u16(a.into(), b.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vaddl_high_u32() { - let a = u32x4::new(0, 1, 2, 3); - let x = u32::MAX; - let b = u32x4::new(x, x, x, x); - let x = x as u64; - let e = u64x2::new(x + 2, x + 3); - let r = u64x2::from(vaddl_high_u32(a.into(), b.into())); - assert_eq!(r, e); - } - #[simd_test(enable = "neon")] fn test_vaddw_s8() { let x = i16::MAX; @@ -2794,96 +2316,6 @@ mod tests { assert_eq!(r, e); } - #[simd_test(enable = "neon")] - fn test_vaddw_high_s8() { - let x = i16::MAX; - let a = i16x8::new(x, 1, 2, 3, 4, 5, 6, 7); - let y = i8::MAX; - let b = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, y, y, y, y, y, y, y, y); - let y = y as i16; - let e = i16x8::new( - x.wrapping_add(y), - 1 + y, - 2 + y, - 3 + y, - 4 + y, - 5 + y, - 6 + y, - 7 + y, - ); - let r = i16x8::from(vaddw_high_s8(a.into(), b.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vaddw_high_s16() { - let x = i32::MAX; - let a = i32x4::new(x, 1, 2, 3); - let y = i16::MAX; - let b = i16x8::new(0, 0, 0, 0, y, y, y, y); - let y = y as i32; - let e = i32x4::new(x.wrapping_add(y), 1 + y, 2 + y, 3 + y); - let r = i32x4::from(vaddw_high_s16(a.into(), b.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vaddw_high_s32() { - let x = i64::MAX; - let a = i64x2::new(x, 1); - let y = i32::MAX; - let b = i32x4::new(0, 0, y, y); - let y = y as i64; - let e = i64x2::new(x.wrapping_add(y), 1 + y); - let r = i64x2::from(vaddw_high_s32(a.into(), b.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vaddw_high_u8() { - let x = u16::MAX; - let a = u16x8::new(x, 1, 2, 3, 4, 5, 6, 7); - let y = u8::MAX; - let b = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, y, y, y, y, y, y, y, y); - let y = y as u16; - let e = u16x8::new( - x.wrapping_add(y), - 1 + y, - 2 + y, - 3 + y, - 4 + y, - 5 + y, - 6 + y, - 7 + y, - ); - let r = u16x8::from(vaddw_high_u8(a.into(), b.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vaddw_high_u16() { - let x = u32::MAX; - let a = u32x4::new(x, 1, 2, 3); - let y = u16::MAX; - let b = u16x8::new(0, 0, 0, 0, y, y, y, y); - let y = y as u32; - let e = u32x4::new(x.wrapping_add(y), 1 + y, 2 + y, 3 + y); - let r = u32x4::from(vaddw_high_u16(a.into(), b.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vaddw_high_u32() { - let x = u64::MAX; - let a = u64x2::new(x, 1); - let y = u32::MAX; - let b = u32x4::new(0, 0, y, y); - let y = y as u64; - let e = u64x2::new(x.wrapping_add(y), 1 + y); - let r = u64x2::from(vaddw_high_u32(a.into(), b.into())); - assert_eq!(r, e); - } - #[simd_test(enable = "neon")] fn test_vmvn_s8() { let a = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); @@ -5766,54 +5198,151 @@ mod tests { assert_eq!(r, e); } - macro_rules! test_vcombine { - ($test_id:ident => $fn_id:ident ([$($a:expr),*], [$($b:expr),*])) => { - #[allow(unused_assignments)] - #[simd_test(enable = "neon")] - fn $test_id() { - let a = Simd::from_array([$($a),*]); - let b = Simd::from_array([$($b),*]); - let e = Simd::from_array([$($a),* $(, $b)*]); - let c = $fn_id(a.into(), b.into()); - let mut d = e; - d = c.into(); - assert_eq!(d, e); - } + #[cfg(not(target_arch = "arm64ec"))] + mod fp16 { + use super::*; + #[simd_test(enable = "neon,fp16")] + fn test_vld1_lane_f16() { + let a = f16x4::new(0., 1., 2., 3.); + let elem: f16 = 42.; + let e = f16x4::new(0., 1., 2., 42.); + let r = unsafe { f16x4::from(vld1_lane_f16::<3>(&elem, a.into())) }; + assert_eq!(r, e) } - } - test_vcombine!(test_vcombine_s8 => vcombine_s8([3_i8, -4, 5, -6, 7, 8, 9, 10], [13_i8, -14, 15, -16, 17, 18, 19, 110])); - test_vcombine!(test_vcombine_u8 => vcombine_u8([3_u8, 4, 5, 6, 7, 8, 9, 10], [13_u8, 14, 15, 16, 17, 18, 19, 110])); - test_vcombine!(test_vcombine_p8 => vcombine_p8([3_u8, 4, 5, 6, 7, 8, 9, 10], [13_u8, 14, 15, 16, 17, 18, 19, 110])); + #[simd_test(enable = "neon,fp16")] + fn test_vld1q_lane_f16() { + let a = f16x8::new(0., 1., 2., 3., 4., 5., 6., 7.); + let elem: f16 = 42.; + let e = f16x8::new(0., 1., 2., 3., 4., 5., 6., 42.); + let r = unsafe { f16x8::from(vld1q_lane_f16::<7>(&elem, a.into())) }; + assert_eq!(r, e) + } - test_vcombine!(test_vcombine_s16 => vcombine_s16([3_i16, -4, 5, -6], [13_i16, -14, 15, -16])); - test_vcombine!(test_vcombine_u16 => vcombine_u16([3_u16, 4, 5, 6], [13_u16, 14, 15, 16])); - test_vcombine!(test_vcombine_p16 => vcombine_p16([3_u16, 4, 5, 6], [13_u16, 14, 15, 16])); + #[simd_test(enable = "neon,fp16")] + fn test_vld1_dup_f16() { + let elem: f16 = 42.; + let e = f16x4::new(42., 42., 42., 42.); + let r = unsafe { f16x4::from(vld1_dup_f16(&elem)) }; + assert_eq!(r, e) + } - #[cfg(not(target_arch = "arm64ec"))] - mod fp16 { - use super::*; - #[cfg_attr(target_arch = "arm", simd_test(enable = "neon,fp16"))] - #[cfg_attr(not(target_arch = "arm"), simd_test(enable = "neon"))] - fn test_vcombine_f16() { - let a = f16x4::from_array([3_f16, 4., 5., 6.]); - let b = f16x4::from_array([13_f16, 14., 15., 16.]); - let e = f16x8::from_array([3_f16, 4., 5., 6., 13_f16, 14., 15., 16.]); - let c = f16x8::from(vcombine_f16(a.into(), b.into())); - assert_eq!(c, e); + #[simd_test(enable = "neon,fp16")] + fn test_vld1q_dup_f16() { + let elem: f16 = 42.; + let e = f16x8::new(42., 42., 42., 42., 42., 42., 42., 42.); + let r = unsafe { f16x8::from(vld1q_dup_f16(&elem)) }; + assert_eq!(r, e) } } - test_vcombine!(test_vcombine_s32 => vcombine_s32([3_i32, -4], [13_i32, -14])); - test_vcombine!(test_vcombine_u32 => vcombine_u32([3_u32, 4], [13_u32, 14])); - // note: poly32x4 does not exist, and neither does vcombine_p32 - test_vcombine!(test_vcombine_f32 => vcombine_f32([3_f32, -4.], [13_f32, -14.])); - - test_vcombine!(test_vcombine_s64 => vcombine_s64([-3_i64], [13_i64])); - test_vcombine!(test_vcombine_u64 => vcombine_u64([3_u64], [13_u64])); - test_vcombine!(test_vcombine_p64 => vcombine_p64([3_u64], [13_u64])); + macro_rules! lane_wide_store_load_roundtrip { + ($elem_ty:ty, $len:expr, $idx:expr, $vec_ty:ty, $store:ident, $load:ident) => { + let vals: [$elem_ty; $len] = crate::array::from_fn(|i| i as $elem_ty); + let a: $vec_ty = transmute(vals); + let mut tmp = [0 as $elem_ty; 4]; + $store::<$idx>(tmp.as_mut_ptr().cast(), a); + let r: $vec_ty = $load::<$idx>(tmp.as_ptr().cast(), a); + let out: [$elem_ty; $len] = transmute(r); + assert_eq!(out, vals); + }; + } + + macro_rules! lane_wide_store_load_roundtrip_neon { + ($( $name:ident $args:tt);* $(;)?) => { + $( + #[cfg_attr(miri, ignore)] // uses unsupported vendor intrinsics + #[simd_test(enable = "neon")] + unsafe fn $name() { + lane_wide_store_load_roundtrip! $args; + } + )* + }; + } + + macro_rules! lane_wide_store_load_roundtrip_fp16 { + ($( $name:ident $args:tt);* $(;)?) => { + $( + #[cfg_attr(miri, ignore)] // uses unsupported vendor intrinsics + #[simd_test(enable = "neon,fp16")] + #[cfg(not(target_arch = "arm64ec"))] + unsafe fn $name() { + lane_wide_store_load_roundtrip! $args; + } + )* + }; + } + + lane_wide_store_load_roundtrip_neon! { + test_vld2_lane_s8(i8, 16, 7, int8x8x2_t, vst2_lane_s8, vld2_lane_s8); + test_vld3_lane_s8(i8, 24, 7, int8x8x3_t, vst3_lane_s8, vld3_lane_s8); + test_vld4_lane_s8(i8, 32, 7, int8x8x4_t, vst4_lane_s8, vld4_lane_s8); + + test_vld2_lane_u8(u8, 16, 7, uint8x8x2_t, vst2_lane_u8, vld2_lane_u8); + test_vld3_lane_u8(u8, 24, 7, uint8x8x3_t, vst3_lane_u8, vld3_lane_u8); + test_vld4_lane_u8(u8, 32, 7, uint8x8x4_t, vst4_lane_u8, vld4_lane_u8); + + test_vld2_lane_s16(i16, 8, 3, int16x4x2_t, vst2_lane_s16, vld2_lane_s16); + test_vld3_lane_s16(i16, 12, 3, int16x4x3_t, vst3_lane_s16, vld3_lane_s16); + test_vld4_lane_s16(i16, 16, 3, int16x4x4_t, vst4_lane_s16, vld4_lane_s16); + test_vld2q_lane_s16(i16, 16, 7, int16x8x2_t, vst2q_lane_s16, vld2q_lane_s16); + test_vld3q_lane_s16(i16, 24, 7, int16x8x3_t, vst3q_lane_s16, vld3q_lane_s16); + test_vld4q_lane_s16(i16, 32, 7, int16x8x4_t, vst4q_lane_s16, vld4q_lane_s16); + + test_vld2_lane_u16(u16, 8, 3, uint16x4x2_t, vst2_lane_u16, vld2_lane_u16); + test_vld3_lane_u16(u16, 12, 3, uint16x4x3_t, vst3_lane_u16, vld3_lane_u16); + test_vld4_lane_u16(u16, 16, 3, uint16x4x4_t, vst4_lane_u16, vld4_lane_u16); + test_vld2q_lane_u16(u16, 16, 7, uint16x8x2_t, vst2q_lane_u16, vld2q_lane_u16); + test_vld3q_lane_u16(u16, 24, 7, uint16x8x3_t, vst3q_lane_u16, vld3q_lane_u16); + test_vld4q_lane_u16(u16, 32, 7, uint16x8x4_t, vst4q_lane_u16, vld4q_lane_u16); + + test_vld2_lane_s32(i32, 4, 1, int32x2x2_t, vst2_lane_s32, vld2_lane_s32); + test_vld3_lane_s32(i32, 6, 1, int32x2x3_t, vst3_lane_s32, vld3_lane_s32); + test_vld4_lane_s32(i32, 8, 1, int32x2x4_t, vst4_lane_s32, vld4_lane_s32); + test_vld2q_lane_s32(i32, 8, 3, int32x4x2_t, vst2q_lane_s32, vld2q_lane_s32); + test_vld3q_lane_s32(i32, 12, 3, int32x4x3_t, vst3q_lane_s32, vld3q_lane_s32); + test_vld4q_lane_s32(i32, 16, 3, int32x4x4_t, vst4q_lane_s32, vld4q_lane_s32); + + test_vld2_lane_u32(u32, 4, 1, uint32x2x2_t, vst2_lane_u32, vld2_lane_u32); + test_vld3_lane_u32(u32, 6, 1, uint32x2x3_t, vst3_lane_u32, vld3_lane_u32); + test_vld4_lane_u32(u32, 8, 1, uint32x2x4_t, vst4_lane_u32, vld4_lane_u32); + test_vld2q_lane_u32(u32, 8, 3, uint32x4x2_t, vst2q_lane_u32, vld2q_lane_u32); + test_vld3q_lane_u32(u32, 12, 3, uint32x4x3_t, vst3q_lane_u32, vld3q_lane_u32); + test_vld4q_lane_u32(u32, 16, 3, uint32x4x4_t, vst4q_lane_u32, vld4q_lane_u32); + + test_vld2_lane_f32(f32, 4, 1, float32x2x2_t, vst2_lane_f32, vld2_lane_f32); + test_vld3_lane_f32(f32, 6, 1, float32x2x3_t, vst3_lane_f32, vld3_lane_f32); + test_vld4_lane_f32(f32, 8, 1, float32x2x4_t, vst4_lane_f32, vld4_lane_f32); + test_vld2q_lane_f32(f32, 8, 3, float32x4x2_t, vst2q_lane_f32, vld2q_lane_f32); + test_vld3q_lane_f32(f32, 12, 3, float32x4x3_t, vst3q_lane_f32, vld3q_lane_f32); + test_vld4q_lane_f32(f32, 16, 3, float32x4x4_t, vst4q_lane_f32, vld4q_lane_f32); + } + + lane_wide_store_load_roundtrip_fp16! { + test_vld2_lane_f16(f16, 8, 3, float16x4x2_t, vst2_lane_f16, vld2_lane_f16); + test_vld3_lane_f16(f16, 12, 3, float16x4x3_t, vst3_lane_f16, vld3_lane_f16); + test_vld4_lane_f16(f16, 16, 3, float16x4x4_t, vst4_lane_f16, vld4_lane_f16); + test_vld2q_lane_f16(f16, 16, 7, float16x8x2_t, vst2q_lane_f16, vld2q_lane_f16); + test_vld3q_lane_f16(f16, 24, 7, float16x8x3_t, vst3q_lane_f16, vld3q_lane_f16); + test_vld4q_lane_f16(f16, 32, 7, float16x8x4_t, vst4q_lane_f16, vld4q_lane_f16); + } + + // FIXME: simd_test (which uses is_arm_feature_detected) does not support the v8 + // feature that we need on arm. #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - test_vcombine!(test_vcombine_f64 => vcombine_f64([-3_f64], [13_f64])); + #[simd_test(enable = "crc")] + fn crc32() { + assert_eq!(__crc32b(u32::MAX, u8::MAX), 16777215); + assert_eq!(__crc32h(u32::MAX, u16::MAX), 65535); + assert_eq!(__crc32w(u32::MAX, u32::MAX), 0); + + assert_eq!(__crc32cb(u32::MAX, u8::MAX), 16777215); + assert_eq!(__crc32ch(u32::MAX, u16::MAX), 65535); + assert_eq!(__crc32cw(u32::MAX, u32::MAX), 0); + + assert_eq!(__crc32d(u32::MAX, u64::MAX), 3736805603); + assert_eq!(__crc32cd(u32::MAX, u64::MAX), 3080238136); + } } #[cfg(all(test, target_arch = "arm"))] diff --git a/library/stdarch/crates/core_arch/src/arm_shared/neon/store_tests.rs b/library/stdarch/crates/core_arch/src/arm_shared/neon/store_tests.rs index 2b10b38f2dd8f..6eb60e4c78bc8 100644 --- a/library/stdarch/crates/core_arch/src/arm_shared/neon/store_tests.rs +++ b/library/stdarch/crates/core_arch/src/arm_shared/neon/store_tests.rs @@ -406,6 +406,44 @@ fn test_vst1q_p64() { assert_eq!(vals[2], 2); } +#[cfg(not(target_arch = "arm64ec"))] +#[simd_test(enable = "neon,fp16")] +fn test_vst1_f16() { + let mut vals = [0_f16; 5]; + let a = f16x4::new(1., 2., 3., 4.); + + unsafe { + vst1_f16(vals[1..].as_mut_ptr(), a.into()); + } + + assert_eq!(vals[0], 0.); + assert_eq!(vals[1], 1.); + assert_eq!(vals[2], 2.); + assert_eq!(vals[3], 3.); + assert_eq!(vals[4], 4.); +} + +#[cfg(not(target_arch = "arm64ec"))] +#[simd_test(enable = "neon,fp16")] +fn test_vst1q_f16() { + let mut vals = [0_f16; 9]; + let a = f16x8::new(1., 2., 3., 4., 5., 6., 7., 8.); + + unsafe { + vst1q_f16(vals[1..].as_mut_ptr(), a.into()); + } + + assert_eq!(vals[0], 0.); + assert_eq!(vals[1], 1.); + assert_eq!(vals[2], 2.); + assert_eq!(vals[3], 3.); + assert_eq!(vals[4], 4.); + assert_eq!(vals[5], 5.); + assert_eq!(vals[6], 6.); + assert_eq!(vals[7], 7.); + assert_eq!(vals[8], 8.); +} + #[simd_test(enable = "neon")] fn test_vst1_f32() { let mut vals = [0_f32; 3]; diff --git a/library/stdarch/crates/core_arch/src/core_arch_docs.md b/library/stdarch/crates/core_arch/src/core_arch_docs.md index 7075945754975..16be725b40bcb 100644 --- a/library/stdarch/crates/core_arch/src/core_arch_docs.md +++ b/library/stdarch/crates/core_arch/src/core_arch_docs.md @@ -31,11 +31,12 @@ ensure at least a few guarantees are upheld: typically done by ensuring that `#[cfg]` is used appropriately when using this module. * The CPU the program is currently running on supports the function being - called. For example it is unsafe to call an AVX2 function on a CPU that + called. For example, it is unsafe to call an AVX2 function on a CPU that doesn't actually support AVX2. As a result of the latter of these guarantees all intrinsics in this module -are `unsafe` and extra care needs to be taken when calling them! +are `unsafe` to call unless the caller enables the required target features, +and extra care needs to be taken when calling them! # CPU Feature Detection @@ -164,6 +165,25 @@ And with all that we should have a working program! This program will run across all machines and it'll use the optimized AVX2 implementation on machines where support is detected. +# Differences from pure hardware behavior + +While the intrinsics in this module exist to expose particular instructions of the underlying +hardware, not all of them behave *exactly* like their corresponding instructions. + +* Floating-point operations are subject to the usual [Rust semantics for NaN + values][nan]. +* Operations that read or write the floating-point status register generally cannot be meaningfully + used because Rust makes no guarantee about when and where floating-point operations can be + executed. In particular, it is generally undefined behavior to change the default rounding or + exception behavior. +* Some operations have special memory-model effects that are incompatible with the Rust Abstract + Machine, which means they are subject to more strict requirements than they would be in an + assembly program. Most notably, this applies to [non-temporal ("streaming") stores on + x86][non-temporal]. + +[nan]: ../../core/primitive.f32.html#nan-bit-patterns +[non-temporal]: ../../core/arch/x86/fn._mm_sfence.html#safety-of-non-temporal-stores + # Ergonomics It's important to note that using the `arch` module is not the easiest @@ -186,6 +206,7 @@ others at: * [`arm`] * [`aarch64`] * [`amdgpu`] +* [`hexagon`] * [`riscv32`] * [`riscv64`] * [`mips`] @@ -203,6 +224,7 @@ others at: [`arm`]: ../../core/arch/arm/index.html [`aarch64`]: ../../core/arch/aarch64/index.html [`amdgpu`]: ../../core/arch/amdgpu/index.html +[`hexagon`]: ../../core/arch/hexagon/index.html [`riscv32`]: ../../core/arch/riscv32/index.html [`riscv64`]: ../../core/arch/riscv64/index.html [`mips`]: ../../core/arch/mips/index.html diff --git a/library/stdarch/crates/core_arch/src/hexagon/mod.rs b/library/stdarch/crates/core_arch/src/hexagon/mod.rs new file mode 100644 index 0000000000000..c973f7dc62e1a --- /dev/null +++ b/library/stdarch/crates/core_arch/src/hexagon/mod.rs @@ -0,0 +1,38 @@ +//! Hexagon architecture intrinsics +//! +//! This module contains intrinsics for the Qualcomm Hexagon DSP architecture, +//! including scalar operations and the Hexagon Vector Extensions (HVX). +//! +//! ## Scalar Intrinsics +//! +//! The [`scalar`] module provides intrinsics for scalar DSP operations including +//! arithmetic, multiply, shift, saturate, compare, and floating-point operations. +//! +//! ## HVX Vector Intrinsics +//! +//! HVX is a wide SIMD architecture designed for high-performance signal processing, +//! machine learning, and image processing workloads. +//! +//! HVX supports two vector length modes: +//! - 64-byte mode (512-bit vectors): Use the [`v64`] module +//! - 128-byte mode (1024-bit vectors): Use the [`v128`] module +//! +//! Both modules are available unconditionally, but require the appropriate +//! target features to actually use the intrinsics: +//! - For 64-byte mode: `-C target-feature=+hvx-length64b` +//! - For 128-byte mode: `-C target-feature=+hvx-length128b` +//! +//! Note that HVX v66 and later default to 128-byte mode, while earlier versions +//! (v60-v65) default to 64-byte mode. + +/// Scalar intrinsics for Hexagon DSP operations +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub mod scalar; + +/// HVX intrinsics for 64-byte vector mode (512-bit vectors) +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub mod v64; + +/// HVX intrinsics for 128-byte vector mode (1024-bit vectors) +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub mod v128; diff --git a/library/stdarch/crates/core_arch/src/hexagon/scalar.rs b/library/stdarch/crates/core_arch/src/hexagon/scalar.rs new file mode 100644 index 0000000000000..a42c5c5e10f30 --- /dev/null +++ b/library/stdarch/crates/core_arch/src/hexagon/scalar.rs @@ -0,0 +1,12182 @@ +// This code is automatically generated. DO NOT MODIFY. +//! Hexagon scalar intrinsics +//! +//! This module provides intrinsics for scalar (non-HVX) Hexagon DSP operations, +//! including arithmetic, multiply, shift, saturate, compare, and floating-point +//! operations. +//! +//! [Hexagon V68 Programmer's Reference Manual](https://docs.qualcomm.com/doc/80-N2040-45) +//! +//! ## Naming Convention +//! +//! Function names preserve the original Q6 naming case because the convention +//! uses case to distinguish register types: +//! - `P` (uppercase) = 64-bit register pair (`Word64`) +//! - `p` (lowercase) = predicate register (`Byte`) +//! +//! For example, `Q6_P_and_PP` operates on 64-bit pairs while `Q6_p_and_pp` +//! operates on predicate registers. +//! +//! ## Architecture Versions +//! +//! Most scalar intrinsics are available on all Hexagon architectures. +//! Some intrinsics require specific architecture versions (v60, v62, v65, +//! v66, v67, v68, or v67+audio) and carry +//! `#[target_feature(enable = "v68")]` (or the appropriate version). +//! Enable these with `-C target-feature=+v68` or by setting the target CPU +//! via `-C target-cpu=hexagonv68`. +//! +//! Each version includes all features from previous versions. + +#![allow(non_snake_case)] + +#[cfg(test)] +use stdarch_test::assert_instr; + +// LLVM intrinsic declarations for Hexagon scalar operations +#[allow(improper_ctypes)] +unsafe extern "unadjusted" { + #[link_name = "llvm.hexagon.A2.abs"] + fn hexagon_A2_abs(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.absp"] + fn hexagon_A2_absp(_: i64) -> i64; + #[link_name = "llvm.hexagon.A2.abssat"] + fn hexagon_A2_abssat(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.add"] + fn hexagon_A2_add(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.h16.hh"] + fn hexagon_A2_addh_h16_hh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.h16.hl"] + fn hexagon_A2_addh_h16_hl(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.h16.lh"] + fn hexagon_A2_addh_h16_lh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.h16.ll"] + fn hexagon_A2_addh_h16_ll(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.h16.sat.hh"] + fn hexagon_A2_addh_h16_sat_hh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.h16.sat.hl"] + fn hexagon_A2_addh_h16_sat_hl(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.h16.sat.lh"] + fn hexagon_A2_addh_h16_sat_lh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.h16.sat.ll"] + fn hexagon_A2_addh_h16_sat_ll(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.l16.hl"] + fn hexagon_A2_addh_l16_hl(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.l16.ll"] + fn hexagon_A2_addh_l16_ll(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.l16.sat.hl"] + fn hexagon_A2_addh_l16_sat_hl(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.l16.sat.ll"] + fn hexagon_A2_addh_l16_sat_ll(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addi"] + fn hexagon_A2_addi(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addp"] + fn hexagon_A2_addp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.addpsat"] + fn hexagon_A2_addpsat(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.addsat"] + fn hexagon_A2_addsat(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addsp"] + fn hexagon_A2_addsp(_: i32, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.and"] + fn hexagon_A2_and(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.andir"] + fn hexagon_A2_andir(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.andp"] + fn hexagon_A2_andp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.aslh"] + fn hexagon_A2_aslh(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.asrh"] + fn hexagon_A2_asrh(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.combine.hh"] + fn hexagon_A2_combine_hh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.combine.hl"] + fn hexagon_A2_combine_hl(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.combine.lh"] + fn hexagon_A2_combine_lh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.combine.ll"] + fn hexagon_A2_combine_ll(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.combineii"] + fn hexagon_A2_combineii(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.A2.combinew"] + fn hexagon_A2_combinew(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.A2.max"] + fn hexagon_A2_max(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.maxp"] + fn hexagon_A2_maxp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.maxu"] + fn hexagon_A2_maxu(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.maxup"] + fn hexagon_A2_maxup(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.min"] + fn hexagon_A2_min(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.minp"] + fn hexagon_A2_minp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.minu"] + fn hexagon_A2_minu(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.minup"] + fn hexagon_A2_minup(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.neg"] + fn hexagon_A2_neg(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.negp"] + fn hexagon_A2_negp(_: i64) -> i64; + #[link_name = "llvm.hexagon.A2.negsat"] + fn hexagon_A2_negsat(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.not"] + fn hexagon_A2_not(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.notp"] + fn hexagon_A2_notp(_: i64) -> i64; + #[link_name = "llvm.hexagon.A2.or"] + fn hexagon_A2_or(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.orir"] + fn hexagon_A2_orir(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.orp"] + fn hexagon_A2_orp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.roundsat"] + fn hexagon_A2_roundsat(_: i64) -> i32; + #[link_name = "llvm.hexagon.A2.sat"] + fn hexagon_A2_sat(_: i64) -> i32; + #[link_name = "llvm.hexagon.A2.satb"] + fn hexagon_A2_satb(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.sath"] + fn hexagon_A2_sath(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.satub"] + fn hexagon_A2_satub(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.satuh"] + fn hexagon_A2_satuh(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.sub"] + fn hexagon_A2_sub(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.h16.hh"] + fn hexagon_A2_subh_h16_hh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.h16.hl"] + fn hexagon_A2_subh_h16_hl(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.h16.lh"] + fn hexagon_A2_subh_h16_lh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.h16.ll"] + fn hexagon_A2_subh_h16_ll(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.h16.sat.hh"] + fn hexagon_A2_subh_h16_sat_hh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.h16.sat.hl"] + fn hexagon_A2_subh_h16_sat_hl(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.h16.sat.lh"] + fn hexagon_A2_subh_h16_sat_lh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.h16.sat.ll"] + fn hexagon_A2_subh_h16_sat_ll(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.l16.hl"] + fn hexagon_A2_subh_l16_hl(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.l16.ll"] + fn hexagon_A2_subh_l16_ll(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.l16.sat.hl"] + fn hexagon_A2_subh_l16_sat_hl(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.l16.sat.ll"] + fn hexagon_A2_subh_l16_sat_ll(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subp"] + fn hexagon_A2_subp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.subri"] + fn hexagon_A2_subri(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subsat"] + fn hexagon_A2_subsat(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.svaddh"] + fn hexagon_A2_svaddh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.svaddhs"] + fn hexagon_A2_svaddhs(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.svadduhs"] + fn hexagon_A2_svadduhs(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.svavgh"] + fn hexagon_A2_svavgh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.svavghs"] + fn hexagon_A2_svavghs(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.svnavgh"] + fn hexagon_A2_svnavgh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.svsubh"] + fn hexagon_A2_svsubh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.svsubhs"] + fn hexagon_A2_svsubhs(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.svsubuhs"] + fn hexagon_A2_svsubuhs(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.swiz"] + fn hexagon_A2_swiz(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.sxtb"] + fn hexagon_A2_sxtb(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.sxth"] + fn hexagon_A2_sxth(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.sxtw"] + fn hexagon_A2_sxtw(_: i32) -> i64; + #[link_name = "llvm.hexagon.A2.tfr"] + fn hexagon_A2_tfr(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.tfrih"] + fn hexagon_A2_tfrih(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.tfril"] + fn hexagon_A2_tfril(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.tfrp"] + fn hexagon_A2_tfrp(_: i64) -> i64; + #[link_name = "llvm.hexagon.A2.tfrpi"] + fn hexagon_A2_tfrpi(_: i32) -> i64; + #[link_name = "llvm.hexagon.A2.tfrsi"] + fn hexagon_A2_tfrsi(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.vabsh"] + fn hexagon_A2_vabsh(_: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vabshsat"] + fn hexagon_A2_vabshsat(_: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vabsw"] + fn hexagon_A2_vabsw(_: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vabswsat"] + fn hexagon_A2_vabswsat(_: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vaddb.map"] + fn hexagon_A2_vaddb_map(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vaddh"] + fn hexagon_A2_vaddh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vaddhs"] + fn hexagon_A2_vaddhs(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vaddub"] + fn hexagon_A2_vaddub(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vaddubs"] + fn hexagon_A2_vaddubs(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vadduhs"] + fn hexagon_A2_vadduhs(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vaddw"] + fn hexagon_A2_vaddw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vaddws"] + fn hexagon_A2_vaddws(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavgh"] + fn hexagon_A2_vavgh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavghcr"] + fn hexagon_A2_vavghcr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavghr"] + fn hexagon_A2_vavghr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavgub"] + fn hexagon_A2_vavgub(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavgubr"] + fn hexagon_A2_vavgubr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavguh"] + fn hexagon_A2_vavguh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavguhr"] + fn hexagon_A2_vavguhr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavguw"] + fn hexagon_A2_vavguw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavguwr"] + fn hexagon_A2_vavguwr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavgw"] + fn hexagon_A2_vavgw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavgwcr"] + fn hexagon_A2_vavgwcr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavgwr"] + fn hexagon_A2_vavgwr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vcmpbeq"] + fn hexagon_A2_vcmpbeq(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.A2.vcmpbgtu"] + fn hexagon_A2_vcmpbgtu(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.A2.vcmpheq"] + fn hexagon_A2_vcmpheq(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.A2.vcmphgt"] + fn hexagon_A2_vcmphgt(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.A2.vcmphgtu"] + fn hexagon_A2_vcmphgtu(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.A2.vcmpweq"] + fn hexagon_A2_vcmpweq(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.A2.vcmpwgt"] + fn hexagon_A2_vcmpwgt(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.A2.vcmpwgtu"] + fn hexagon_A2_vcmpwgtu(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.A2.vconj"] + fn hexagon_A2_vconj(_: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vmaxb"] + fn hexagon_A2_vmaxb(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vmaxh"] + fn hexagon_A2_vmaxh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vmaxub"] + fn hexagon_A2_vmaxub(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vmaxuh"] + fn hexagon_A2_vmaxuh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vmaxuw"] + fn hexagon_A2_vmaxuw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vmaxw"] + fn hexagon_A2_vmaxw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vminb"] + fn hexagon_A2_vminb(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vminh"] + fn hexagon_A2_vminh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vminub"] + fn hexagon_A2_vminub(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vminuh"] + fn hexagon_A2_vminuh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vminuw"] + fn hexagon_A2_vminuw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vminw"] + fn hexagon_A2_vminw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vnavgh"] + fn hexagon_A2_vnavgh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vnavghcr"] + fn hexagon_A2_vnavghcr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vnavghr"] + fn hexagon_A2_vnavghr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vnavgw"] + fn hexagon_A2_vnavgw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vnavgwcr"] + fn hexagon_A2_vnavgwcr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vnavgwr"] + fn hexagon_A2_vnavgwr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vraddub"] + fn hexagon_A2_vraddub(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vraddub.acc"] + fn hexagon_A2_vraddub_acc(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vrsadub"] + fn hexagon_A2_vrsadub(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vrsadub.acc"] + fn hexagon_A2_vrsadub_acc(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vsubb.map"] + fn hexagon_A2_vsubb_map(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vsubh"] + fn hexagon_A2_vsubh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vsubhs"] + fn hexagon_A2_vsubhs(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vsubub"] + fn hexagon_A2_vsubub(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vsububs"] + fn hexagon_A2_vsububs(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vsubuhs"] + fn hexagon_A2_vsubuhs(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vsubw"] + fn hexagon_A2_vsubw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vsubws"] + fn hexagon_A2_vsubws(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.xor"] + fn hexagon_A2_xor(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.xorp"] + fn hexagon_A2_xorp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.zxtb"] + fn hexagon_A2_zxtb(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.zxth"] + fn hexagon_A2_zxth(_: i32) -> i32; + #[link_name = "llvm.hexagon.A4.andn"] + fn hexagon_A4_andn(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.andnp"] + fn hexagon_A4_andnp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A4.bitsplit"] + fn hexagon_A4_bitsplit(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.A4.bitspliti"] + fn hexagon_A4_bitspliti(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.A4.boundscheck"] + fn hexagon_A4_boundscheck(_: i32, _: i64) -> i32; + #[link_name = "llvm.hexagon.A4.cmpbeq"] + fn hexagon_A4_cmpbeq(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cmpbeqi"] + fn hexagon_A4_cmpbeqi(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cmpbgt"] + fn hexagon_A4_cmpbgt(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cmpbgti"] + fn hexagon_A4_cmpbgti(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cmpbgtu"] + fn hexagon_A4_cmpbgtu(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cmpbgtui"] + fn hexagon_A4_cmpbgtui(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cmpheq"] + fn hexagon_A4_cmpheq(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cmpheqi"] + fn hexagon_A4_cmpheqi(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cmphgt"] + fn hexagon_A4_cmphgt(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cmphgti"] + fn hexagon_A4_cmphgti(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cmphgtu"] + fn hexagon_A4_cmphgtu(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cmphgtui"] + fn hexagon_A4_cmphgtui(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.combineir"] + fn hexagon_A4_combineir(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.A4.combineri"] + fn hexagon_A4_combineri(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.A4.cround.ri"] + fn hexagon_A4_cround_ri(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cround.rr"] + fn hexagon_A4_cround_rr(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.modwrapu"] + fn hexagon_A4_modwrapu(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.orn"] + fn hexagon_A4_orn(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.ornp"] + fn hexagon_A4_ornp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A4.rcmpeq"] + fn hexagon_A4_rcmpeq(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.rcmpeqi"] + fn hexagon_A4_rcmpeqi(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.rcmpneq"] + fn hexagon_A4_rcmpneq(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.rcmpneqi"] + fn hexagon_A4_rcmpneqi(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.round.ri"] + fn hexagon_A4_round_ri(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.round.ri.sat"] + fn hexagon_A4_round_ri_sat(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.round.rr"] + fn hexagon_A4_round_rr(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.round.rr.sat"] + fn hexagon_A4_round_rr_sat(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.tlbmatch"] + fn hexagon_A4_tlbmatch(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.vcmpbeq.any"] + fn hexagon_A4_vcmpbeq_any(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.A4.vcmpbeqi"] + fn hexagon_A4_vcmpbeqi(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.vcmpbgt"] + fn hexagon_A4_vcmpbgt(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.A4.vcmpbgti"] + fn hexagon_A4_vcmpbgti(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.vcmpbgtui"] + fn hexagon_A4_vcmpbgtui(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.vcmpheqi"] + fn hexagon_A4_vcmpheqi(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.vcmphgti"] + fn hexagon_A4_vcmphgti(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.vcmphgtui"] + fn hexagon_A4_vcmphgtui(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.vcmpweqi"] + fn hexagon_A4_vcmpweqi(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.vcmpwgti"] + fn hexagon_A4_vcmpwgti(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.vcmpwgtui"] + fn hexagon_A4_vcmpwgtui(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.vrmaxh"] + fn hexagon_A4_vrmaxh(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.A4.vrmaxuh"] + fn hexagon_A4_vrmaxuh(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.A4.vrmaxuw"] + fn hexagon_A4_vrmaxuw(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.A4.vrmaxw"] + fn hexagon_A4_vrmaxw(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.A4.vrminh"] + fn hexagon_A4_vrminh(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.A4.vrminuh"] + fn hexagon_A4_vrminuh(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.A4.vrminuw"] + fn hexagon_A4_vrminuw(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.A4.vrminw"] + fn hexagon_A4_vrminw(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.A5.vaddhubs"] + fn hexagon_A5_vaddhubs(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.C2.all8"] + fn hexagon_C2_all8(_: i32) -> i32; + #[link_name = "llvm.hexagon.C2.and"] + fn hexagon_C2_and(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.andn"] + fn hexagon_C2_andn(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.any8"] + fn hexagon_C2_any8(_: i32) -> i32; + #[link_name = "llvm.hexagon.C2.bitsclr"] + fn hexagon_C2_bitsclr(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.bitsclri"] + fn hexagon_C2_bitsclri(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.bitsset"] + fn hexagon_C2_bitsset(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.cmpeq"] + fn hexagon_C2_cmpeq(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.cmpeqi"] + fn hexagon_C2_cmpeqi(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.cmpeqp"] + fn hexagon_C2_cmpeqp(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.C2.cmpgei"] + fn hexagon_C2_cmpgei(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.cmpgeui"] + fn hexagon_C2_cmpgeui(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.cmpgt"] + fn hexagon_C2_cmpgt(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.cmpgti"] + fn hexagon_C2_cmpgti(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.cmpgtp"] + fn hexagon_C2_cmpgtp(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.C2.cmpgtu"] + fn hexagon_C2_cmpgtu(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.cmpgtui"] + fn hexagon_C2_cmpgtui(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.cmpgtup"] + fn hexagon_C2_cmpgtup(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.C2.cmplt"] + fn hexagon_C2_cmplt(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.cmpltu"] + fn hexagon_C2_cmpltu(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.mask"] + fn hexagon_C2_mask(_: i32) -> i64; + #[link_name = "llvm.hexagon.C2.mux"] + fn hexagon_C2_mux(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.muxii"] + fn hexagon_C2_muxii(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.muxir"] + fn hexagon_C2_muxir(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.muxri"] + fn hexagon_C2_muxri(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.not"] + fn hexagon_C2_not(_: i32) -> i32; + #[link_name = "llvm.hexagon.C2.or"] + fn hexagon_C2_or(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.orn"] + fn hexagon_C2_orn(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.pxfer.map"] + fn hexagon_C2_pxfer_map(_: i32) -> i32; + #[link_name = "llvm.hexagon.C2.tfrpr"] + fn hexagon_C2_tfrpr(_: i32) -> i32; + #[link_name = "llvm.hexagon.C2.tfrrp"] + fn hexagon_C2_tfrrp(_: i32) -> i32; + #[link_name = "llvm.hexagon.C2.vitpack"] + fn hexagon_C2_vitpack(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.vmux"] + fn hexagon_C2_vmux(_: i32, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.C2.xor"] + fn hexagon_C2_xor(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.and.and"] + fn hexagon_C4_and_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.and.andn"] + fn hexagon_C4_and_andn(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.and.or"] + fn hexagon_C4_and_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.and.orn"] + fn hexagon_C4_and_orn(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.cmplte"] + fn hexagon_C4_cmplte(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.cmpltei"] + fn hexagon_C4_cmpltei(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.cmplteu"] + fn hexagon_C4_cmplteu(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.cmplteui"] + fn hexagon_C4_cmplteui(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.cmpneq"] + fn hexagon_C4_cmpneq(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.cmpneqi"] + fn hexagon_C4_cmpneqi(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.fastcorner9"] + fn hexagon_C4_fastcorner9(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.fastcorner9.not"] + fn hexagon_C4_fastcorner9_not(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.nbitsclr"] + fn hexagon_C4_nbitsclr(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.nbitsclri"] + fn hexagon_C4_nbitsclri(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.nbitsset"] + fn hexagon_C4_nbitsset(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.or.and"] + fn hexagon_C4_or_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.or.andn"] + fn hexagon_C4_or_andn(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.or.or"] + fn hexagon_C4_or_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.or.orn"] + fn hexagon_C4_or_orn(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.F2.conv.d2df"] + fn hexagon_F2_conv_d2df(_: i64) -> f64; + #[link_name = "llvm.hexagon.F2.conv.d2sf"] + fn hexagon_F2_conv_d2sf(_: i64) -> f32; + #[link_name = "llvm.hexagon.F2.conv.df2d"] + fn hexagon_F2_conv_df2d(_: f64) -> i64; + #[link_name = "llvm.hexagon.F2.conv.df2d.chop"] + fn hexagon_F2_conv_df2d_chop(_: f64) -> i64; + #[link_name = "llvm.hexagon.F2.conv.df2sf"] + fn hexagon_F2_conv_df2sf(_: f64) -> f32; + #[link_name = "llvm.hexagon.F2.conv.df2ud"] + fn hexagon_F2_conv_df2ud(_: f64) -> i64; + #[link_name = "llvm.hexagon.F2.conv.df2ud.chop"] + fn hexagon_F2_conv_df2ud_chop(_: f64) -> i64; + #[link_name = "llvm.hexagon.F2.conv.df2uw"] + fn hexagon_F2_conv_df2uw(_: f64) -> i32; + #[link_name = "llvm.hexagon.F2.conv.df2uw.chop"] + fn hexagon_F2_conv_df2uw_chop(_: f64) -> i32; + #[link_name = "llvm.hexagon.F2.conv.df2w"] + fn hexagon_F2_conv_df2w(_: f64) -> i32; + #[link_name = "llvm.hexagon.F2.conv.df2w.chop"] + fn hexagon_F2_conv_df2w_chop(_: f64) -> i32; + #[link_name = "llvm.hexagon.F2.conv.sf2d"] + fn hexagon_F2_conv_sf2d(_: f32) -> i64; + #[link_name = "llvm.hexagon.F2.conv.sf2d.chop"] + fn hexagon_F2_conv_sf2d_chop(_: f32) -> i64; + #[link_name = "llvm.hexagon.F2.conv.sf2df"] + fn hexagon_F2_conv_sf2df(_: f32) -> f64; + #[link_name = "llvm.hexagon.F2.conv.sf2ud"] + fn hexagon_F2_conv_sf2ud(_: f32) -> i64; + #[link_name = "llvm.hexagon.F2.conv.sf2ud.chop"] + fn hexagon_F2_conv_sf2ud_chop(_: f32) -> i64; + #[link_name = "llvm.hexagon.F2.conv.sf2uw"] + fn hexagon_F2_conv_sf2uw(_: f32) -> i32; + #[link_name = "llvm.hexagon.F2.conv.sf2uw.chop"] + fn hexagon_F2_conv_sf2uw_chop(_: f32) -> i32; + #[link_name = "llvm.hexagon.F2.conv.sf2w"] + fn hexagon_F2_conv_sf2w(_: f32) -> i32; + #[link_name = "llvm.hexagon.F2.conv.sf2w.chop"] + fn hexagon_F2_conv_sf2w_chop(_: f32) -> i32; + #[link_name = "llvm.hexagon.F2.conv.ud2df"] + fn hexagon_F2_conv_ud2df(_: i64) -> f64; + #[link_name = "llvm.hexagon.F2.conv.ud2sf"] + fn hexagon_F2_conv_ud2sf(_: i64) -> f32; + #[link_name = "llvm.hexagon.F2.conv.uw2df"] + fn hexagon_F2_conv_uw2df(_: i32) -> f64; + #[link_name = "llvm.hexagon.F2.conv.uw2sf"] + fn hexagon_F2_conv_uw2sf(_: i32) -> f32; + #[link_name = "llvm.hexagon.F2.conv.w2df"] + fn hexagon_F2_conv_w2df(_: i32) -> f64; + #[link_name = "llvm.hexagon.F2.conv.w2sf"] + fn hexagon_F2_conv_w2sf(_: i32) -> f32; + #[link_name = "llvm.hexagon.F2.dfclass"] + fn hexagon_F2_dfclass(_: f64, _: i32) -> i32; + #[link_name = "llvm.hexagon.F2.dfcmpeq"] + fn hexagon_F2_dfcmpeq(_: f64, _: f64) -> i32; + #[link_name = "llvm.hexagon.F2.dfcmpge"] + fn hexagon_F2_dfcmpge(_: f64, _: f64) -> i32; + #[link_name = "llvm.hexagon.F2.dfcmpgt"] + fn hexagon_F2_dfcmpgt(_: f64, _: f64) -> i32; + #[link_name = "llvm.hexagon.F2.dfcmpuo"] + fn hexagon_F2_dfcmpuo(_: f64, _: f64) -> i32; + #[link_name = "llvm.hexagon.F2.dfimm.n"] + fn hexagon_F2_dfimm_n(_: i32) -> f64; + #[link_name = "llvm.hexagon.F2.dfimm.p"] + fn hexagon_F2_dfimm_p(_: i32) -> f64; + #[link_name = "llvm.hexagon.F2.sfadd"] + fn hexagon_F2_sfadd(_: f32, _: f32) -> f32; + #[link_name = "llvm.hexagon.F2.sfclass"] + fn hexagon_F2_sfclass(_: f32, _: i32) -> i32; + #[link_name = "llvm.hexagon.F2.sfcmpeq"] + fn hexagon_F2_sfcmpeq(_: f32, _: f32) -> i32; + #[link_name = "llvm.hexagon.F2.sfcmpge"] + fn hexagon_F2_sfcmpge(_: f32, _: f32) -> i32; + #[link_name = "llvm.hexagon.F2.sfcmpgt"] + fn hexagon_F2_sfcmpgt(_: f32, _: f32) -> i32; + #[link_name = "llvm.hexagon.F2.sfcmpuo"] + fn hexagon_F2_sfcmpuo(_: f32, _: f32) -> i32; + #[link_name = "llvm.hexagon.F2.sffixupd"] + fn hexagon_F2_sffixupd(_: f32, _: f32) -> f32; + #[link_name = "llvm.hexagon.F2.sffixupn"] + fn hexagon_F2_sffixupn(_: f32, _: f32) -> f32; + #[link_name = "llvm.hexagon.F2.sffixupr"] + fn hexagon_F2_sffixupr(_: f32) -> f32; + #[link_name = "llvm.hexagon.F2.sffma"] + fn hexagon_F2_sffma(_: f32, _: f32, _: f32) -> f32; + #[link_name = "llvm.hexagon.F2.sffma.lib"] + fn hexagon_F2_sffma_lib(_: f32, _: f32, _: f32) -> f32; + #[link_name = "llvm.hexagon.F2.sffma.sc"] + fn hexagon_F2_sffma_sc(_: f32, _: f32, _: f32, _: i32) -> f32; + #[link_name = "llvm.hexagon.F2.sffms"] + fn hexagon_F2_sffms(_: f32, _: f32, _: f32) -> f32; + #[link_name = "llvm.hexagon.F2.sffms.lib"] + fn hexagon_F2_sffms_lib(_: f32, _: f32, _: f32) -> f32; + #[link_name = "llvm.hexagon.F2.sfimm.n"] + fn hexagon_F2_sfimm_n(_: i32) -> f32; + #[link_name = "llvm.hexagon.F2.sfimm.p"] + fn hexagon_F2_sfimm_p(_: i32) -> f32; + #[link_name = "llvm.hexagon.F2.sfmax"] + fn hexagon_F2_sfmax(_: f32, _: f32) -> f32; + #[link_name = "llvm.hexagon.F2.sfmin"] + fn hexagon_F2_sfmin(_: f32, _: f32) -> f32; + #[link_name = "llvm.hexagon.F2.sfmpy"] + fn hexagon_F2_sfmpy(_: f32, _: f32) -> f32; + #[link_name = "llvm.hexagon.F2.sfsub"] + fn hexagon_F2_sfsub(_: f32, _: f32) -> f32; + #[link_name = "llvm.hexagon.M2.acci"] + fn hexagon_M2_acci(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.accii"] + fn hexagon_M2_accii(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.cmaci.s0"] + fn hexagon_M2_cmaci_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cmacr.s0"] + fn hexagon_M2_cmacr_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cmacs.s0"] + fn hexagon_M2_cmacs_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cmacs.s1"] + fn hexagon_M2_cmacs_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cmacsc.s0"] + fn hexagon_M2_cmacsc_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cmacsc.s1"] + fn hexagon_M2_cmacsc_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cmpyi.s0"] + fn hexagon_M2_cmpyi_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cmpyr.s0"] + fn hexagon_M2_cmpyr_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cmpyrs.s0"] + fn hexagon_M2_cmpyrs_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.cmpyrs.s1"] + fn hexagon_M2_cmpyrs_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.cmpyrsc.s0"] + fn hexagon_M2_cmpyrsc_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.cmpyrsc.s1"] + fn hexagon_M2_cmpyrsc_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.cmpys.s0"] + fn hexagon_M2_cmpys_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cmpys.s1"] + fn hexagon_M2_cmpys_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cmpysc.s0"] + fn hexagon_M2_cmpysc_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cmpysc.s1"] + fn hexagon_M2_cmpysc_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cnacs.s0"] + fn hexagon_M2_cnacs_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cnacs.s1"] + fn hexagon_M2_cnacs_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cnacsc.s0"] + fn hexagon_M2_cnacsc_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cnacsc.s1"] + fn hexagon_M2_cnacsc_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.dpmpyss.acc.s0"] + fn hexagon_M2_dpmpyss_acc_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.dpmpyss.nac.s0"] + fn hexagon_M2_dpmpyss_nac_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.dpmpyss.rnd.s0"] + fn hexagon_M2_dpmpyss_rnd_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.dpmpyss.s0"] + fn hexagon_M2_dpmpyss_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.dpmpyuu.acc.s0"] + fn hexagon_M2_dpmpyuu_acc_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.dpmpyuu.nac.s0"] + fn hexagon_M2_dpmpyuu_nac_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.dpmpyuu.s0"] + fn hexagon_M2_dpmpyuu_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.hmmpyh.rs1"] + fn hexagon_M2_hmmpyh_rs1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.hmmpyh.s1"] + fn hexagon_M2_hmmpyh_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.hmmpyl.rs1"] + fn hexagon_M2_hmmpyl_rs1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.hmmpyl.s1"] + fn hexagon_M2_hmmpyl_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.maci"] + fn hexagon_M2_maci(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.macsin"] + fn hexagon_M2_macsin(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.macsip"] + fn hexagon_M2_macsip(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mmachs.rs0"] + fn hexagon_M2_mmachs_rs0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmachs.rs1"] + fn hexagon_M2_mmachs_rs1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmachs.s0"] + fn hexagon_M2_mmachs_s0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmachs.s1"] + fn hexagon_M2_mmachs_s1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmacls.rs0"] + fn hexagon_M2_mmacls_rs0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmacls.rs1"] + fn hexagon_M2_mmacls_rs1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmacls.s0"] + fn hexagon_M2_mmacls_s0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmacls.s1"] + fn hexagon_M2_mmacls_s1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmacuhs.rs0"] + fn hexagon_M2_mmacuhs_rs0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmacuhs.rs1"] + fn hexagon_M2_mmacuhs_rs1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmacuhs.s0"] + fn hexagon_M2_mmacuhs_s0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmacuhs.s1"] + fn hexagon_M2_mmacuhs_s1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmaculs.rs0"] + fn hexagon_M2_mmaculs_rs0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmaculs.rs1"] + fn hexagon_M2_mmaculs_rs1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmaculs.s0"] + fn hexagon_M2_mmaculs_s0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmaculs.s1"] + fn hexagon_M2_mmaculs_s1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyh.rs0"] + fn hexagon_M2_mmpyh_rs0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyh.rs1"] + fn hexagon_M2_mmpyh_rs1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyh.s0"] + fn hexagon_M2_mmpyh_s0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyh.s1"] + fn hexagon_M2_mmpyh_s1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyl.rs0"] + fn hexagon_M2_mmpyl_rs0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyl.rs1"] + fn hexagon_M2_mmpyl_rs1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyl.s0"] + fn hexagon_M2_mmpyl_s0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyl.s1"] + fn hexagon_M2_mmpyl_s1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyuh.rs0"] + fn hexagon_M2_mmpyuh_rs0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyuh.rs1"] + fn hexagon_M2_mmpyuh_rs1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyuh.s0"] + fn hexagon_M2_mmpyuh_s0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyuh.s1"] + fn hexagon_M2_mmpyuh_s1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyul.rs0"] + fn hexagon_M2_mmpyul_rs0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyul.rs1"] + fn hexagon_M2_mmpyul_rs1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyul.s0"] + fn hexagon_M2_mmpyul_s0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyul.s1"] + fn hexagon_M2_mmpyul_s1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mpy.acc.hh.s0"] + fn hexagon_M2_mpy_acc_hh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.hh.s1"] + fn hexagon_M2_mpy_acc_hh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.hl.s0"] + fn hexagon_M2_mpy_acc_hl_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.hl.s1"] + fn hexagon_M2_mpy_acc_hl_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.lh.s0"] + fn hexagon_M2_mpy_acc_lh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.lh.s1"] + fn hexagon_M2_mpy_acc_lh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.ll.s0"] + fn hexagon_M2_mpy_acc_ll_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.ll.s1"] + fn hexagon_M2_mpy_acc_ll_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.sat.hh.s0"] + fn hexagon_M2_mpy_acc_sat_hh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.sat.hh.s1"] + fn hexagon_M2_mpy_acc_sat_hh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.sat.hl.s0"] + fn hexagon_M2_mpy_acc_sat_hl_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.sat.hl.s1"] + fn hexagon_M2_mpy_acc_sat_hl_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.sat.lh.s0"] + fn hexagon_M2_mpy_acc_sat_lh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.sat.lh.s1"] + fn hexagon_M2_mpy_acc_sat_lh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.sat.ll.s0"] + fn hexagon_M2_mpy_acc_sat_ll_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.sat.ll.s1"] + fn hexagon_M2_mpy_acc_sat_ll_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.hh.s0"] + fn hexagon_M2_mpy_hh_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.hh.s1"] + fn hexagon_M2_mpy_hh_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.hl.s0"] + fn hexagon_M2_mpy_hl_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.hl.s1"] + fn hexagon_M2_mpy_hl_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.lh.s0"] + fn hexagon_M2_mpy_lh_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.lh.s1"] + fn hexagon_M2_mpy_lh_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.ll.s0"] + fn hexagon_M2_mpy_ll_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.ll.s1"] + fn hexagon_M2_mpy_ll_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.hh.s0"] + fn hexagon_M2_mpy_nac_hh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.hh.s1"] + fn hexagon_M2_mpy_nac_hh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.hl.s0"] + fn hexagon_M2_mpy_nac_hl_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.hl.s1"] + fn hexagon_M2_mpy_nac_hl_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.lh.s0"] + fn hexagon_M2_mpy_nac_lh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.lh.s1"] + fn hexagon_M2_mpy_nac_lh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.ll.s0"] + fn hexagon_M2_mpy_nac_ll_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.ll.s1"] + fn hexagon_M2_mpy_nac_ll_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.sat.hh.s0"] + fn hexagon_M2_mpy_nac_sat_hh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.sat.hh.s1"] + fn hexagon_M2_mpy_nac_sat_hh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.sat.hl.s0"] + fn hexagon_M2_mpy_nac_sat_hl_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.sat.hl.s1"] + fn hexagon_M2_mpy_nac_sat_hl_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.sat.lh.s0"] + fn hexagon_M2_mpy_nac_sat_lh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.sat.lh.s1"] + fn hexagon_M2_mpy_nac_sat_lh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.sat.ll.s0"] + fn hexagon_M2_mpy_nac_sat_ll_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.sat.ll.s1"] + fn hexagon_M2_mpy_nac_sat_ll_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.rnd.hh.s0"] + fn hexagon_M2_mpy_rnd_hh_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.rnd.hh.s1"] + fn hexagon_M2_mpy_rnd_hh_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.rnd.hl.s0"] + fn hexagon_M2_mpy_rnd_hl_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.rnd.hl.s1"] + fn hexagon_M2_mpy_rnd_hl_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.rnd.lh.s0"] + fn hexagon_M2_mpy_rnd_lh_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.rnd.lh.s1"] + fn hexagon_M2_mpy_rnd_lh_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.rnd.ll.s0"] + fn hexagon_M2_mpy_rnd_ll_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.rnd.ll.s1"] + fn hexagon_M2_mpy_rnd_ll_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.hh.s0"] + fn hexagon_M2_mpy_sat_hh_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.hh.s1"] + fn hexagon_M2_mpy_sat_hh_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.hl.s0"] + fn hexagon_M2_mpy_sat_hl_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.hl.s1"] + fn hexagon_M2_mpy_sat_hl_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.lh.s0"] + fn hexagon_M2_mpy_sat_lh_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.lh.s1"] + fn hexagon_M2_mpy_sat_lh_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.ll.s0"] + fn hexagon_M2_mpy_sat_ll_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.ll.s1"] + fn hexagon_M2_mpy_sat_ll_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.hh.s0"] + fn hexagon_M2_mpy_sat_rnd_hh_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.hh.s1"] + fn hexagon_M2_mpy_sat_rnd_hh_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.hl.s0"] + fn hexagon_M2_mpy_sat_rnd_hl_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.hl.s1"] + fn hexagon_M2_mpy_sat_rnd_hl_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.lh.s0"] + fn hexagon_M2_mpy_sat_rnd_lh_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.lh.s1"] + fn hexagon_M2_mpy_sat_rnd_lh_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.ll.s0"] + fn hexagon_M2_mpy_sat_rnd_ll_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.ll.s1"] + fn hexagon_M2_mpy_sat_rnd_ll_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.up"] + fn hexagon_M2_mpy_up(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.up.s1"] + fn hexagon_M2_mpy_up_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.up.s1.sat"] + fn hexagon_M2_mpy_up_s1_sat(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyd.acc.hh.s0"] + fn hexagon_M2_mpyd_acc_hh_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.acc.hh.s1"] + fn hexagon_M2_mpyd_acc_hh_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.acc.hl.s0"] + fn hexagon_M2_mpyd_acc_hl_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.acc.hl.s1"] + fn hexagon_M2_mpyd_acc_hl_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.acc.lh.s0"] + fn hexagon_M2_mpyd_acc_lh_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.acc.lh.s1"] + fn hexagon_M2_mpyd_acc_lh_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.acc.ll.s0"] + fn hexagon_M2_mpyd_acc_ll_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.acc.ll.s1"] + fn hexagon_M2_mpyd_acc_ll_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.hh.s0"] + fn hexagon_M2_mpyd_hh_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.hh.s1"] + fn hexagon_M2_mpyd_hh_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.hl.s0"] + fn hexagon_M2_mpyd_hl_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.hl.s1"] + fn hexagon_M2_mpyd_hl_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.lh.s0"] + fn hexagon_M2_mpyd_lh_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.lh.s1"] + fn hexagon_M2_mpyd_lh_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.ll.s0"] + fn hexagon_M2_mpyd_ll_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.ll.s1"] + fn hexagon_M2_mpyd_ll_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.nac.hh.s0"] + fn hexagon_M2_mpyd_nac_hh_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.nac.hh.s1"] + fn hexagon_M2_mpyd_nac_hh_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.nac.hl.s0"] + fn hexagon_M2_mpyd_nac_hl_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.nac.hl.s1"] + fn hexagon_M2_mpyd_nac_hl_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.nac.lh.s0"] + fn hexagon_M2_mpyd_nac_lh_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.nac.lh.s1"] + fn hexagon_M2_mpyd_nac_lh_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.nac.ll.s0"] + fn hexagon_M2_mpyd_nac_ll_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.nac.ll.s1"] + fn hexagon_M2_mpyd_nac_ll_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.rnd.hh.s0"] + fn hexagon_M2_mpyd_rnd_hh_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.rnd.hh.s1"] + fn hexagon_M2_mpyd_rnd_hh_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.rnd.hl.s0"] + fn hexagon_M2_mpyd_rnd_hl_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.rnd.hl.s1"] + fn hexagon_M2_mpyd_rnd_hl_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.rnd.lh.s0"] + fn hexagon_M2_mpyd_rnd_lh_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.rnd.lh.s1"] + fn hexagon_M2_mpyd_rnd_lh_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.rnd.ll.s0"] + fn hexagon_M2_mpyd_rnd_ll_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.rnd.ll.s1"] + fn hexagon_M2_mpyd_rnd_ll_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyi"] + fn hexagon_M2_mpyi(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpysmi"] + fn hexagon_M2_mpysmi(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpysu.up"] + fn hexagon_M2_mpysu_up(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.acc.hh.s0"] + fn hexagon_M2_mpyu_acc_hh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.acc.hh.s1"] + fn hexagon_M2_mpyu_acc_hh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.acc.hl.s0"] + fn hexagon_M2_mpyu_acc_hl_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.acc.hl.s1"] + fn hexagon_M2_mpyu_acc_hl_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.acc.lh.s0"] + fn hexagon_M2_mpyu_acc_lh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.acc.lh.s1"] + fn hexagon_M2_mpyu_acc_lh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.acc.ll.s0"] + fn hexagon_M2_mpyu_acc_ll_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.acc.ll.s1"] + fn hexagon_M2_mpyu_acc_ll_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.hh.s0"] + fn hexagon_M2_mpyu_hh_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.hh.s1"] + fn hexagon_M2_mpyu_hh_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.hl.s0"] + fn hexagon_M2_mpyu_hl_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.hl.s1"] + fn hexagon_M2_mpyu_hl_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.lh.s0"] + fn hexagon_M2_mpyu_lh_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.lh.s1"] + fn hexagon_M2_mpyu_lh_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.ll.s0"] + fn hexagon_M2_mpyu_ll_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.ll.s1"] + fn hexagon_M2_mpyu_ll_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.nac.hh.s0"] + fn hexagon_M2_mpyu_nac_hh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.nac.hh.s1"] + fn hexagon_M2_mpyu_nac_hh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.nac.hl.s0"] + fn hexagon_M2_mpyu_nac_hl_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.nac.hl.s1"] + fn hexagon_M2_mpyu_nac_hl_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.nac.lh.s0"] + fn hexagon_M2_mpyu_nac_lh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.nac.lh.s1"] + fn hexagon_M2_mpyu_nac_lh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.nac.ll.s0"] + fn hexagon_M2_mpyu_nac_ll_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.nac.ll.s1"] + fn hexagon_M2_mpyu_nac_ll_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.up"] + fn hexagon_M2_mpyu_up(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyud.acc.hh.s0"] + fn hexagon_M2_mpyud_acc_hh_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.acc.hh.s1"] + fn hexagon_M2_mpyud_acc_hh_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.acc.hl.s0"] + fn hexagon_M2_mpyud_acc_hl_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.acc.hl.s1"] + fn hexagon_M2_mpyud_acc_hl_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.acc.lh.s0"] + fn hexagon_M2_mpyud_acc_lh_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.acc.lh.s1"] + fn hexagon_M2_mpyud_acc_lh_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.acc.ll.s0"] + fn hexagon_M2_mpyud_acc_ll_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.acc.ll.s1"] + fn hexagon_M2_mpyud_acc_ll_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.hh.s0"] + fn hexagon_M2_mpyud_hh_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.hh.s1"] + fn hexagon_M2_mpyud_hh_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.hl.s0"] + fn hexagon_M2_mpyud_hl_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.hl.s1"] + fn hexagon_M2_mpyud_hl_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.lh.s0"] + fn hexagon_M2_mpyud_lh_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.lh.s1"] + fn hexagon_M2_mpyud_lh_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.ll.s0"] + fn hexagon_M2_mpyud_ll_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.ll.s1"] + fn hexagon_M2_mpyud_ll_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.nac.hh.s0"] + fn hexagon_M2_mpyud_nac_hh_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.nac.hh.s1"] + fn hexagon_M2_mpyud_nac_hh_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.nac.hl.s0"] + fn hexagon_M2_mpyud_nac_hl_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.nac.hl.s1"] + fn hexagon_M2_mpyud_nac_hl_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.nac.lh.s0"] + fn hexagon_M2_mpyud_nac_lh_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.nac.lh.s1"] + fn hexagon_M2_mpyud_nac_lh_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.nac.ll.s0"] + fn hexagon_M2_mpyud_nac_ll_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.nac.ll.s1"] + fn hexagon_M2_mpyud_nac_ll_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyui"] + fn hexagon_M2_mpyui(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.nacci"] + fn hexagon_M2_nacci(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.naccii"] + fn hexagon_M2_naccii(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.subacc"] + fn hexagon_M2_subacc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.vabsdiffh"] + fn hexagon_M2_vabsdiffh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vabsdiffw"] + fn hexagon_M2_vabsdiffw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vcmac.s0.sat.i"] + fn hexagon_M2_vcmac_s0_sat_i(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vcmac.s0.sat.r"] + fn hexagon_M2_vcmac_s0_sat_r(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vcmpy.s0.sat.i"] + fn hexagon_M2_vcmpy_s0_sat_i(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vcmpy.s0.sat.r"] + fn hexagon_M2_vcmpy_s0_sat_r(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vcmpy.s1.sat.i"] + fn hexagon_M2_vcmpy_s1_sat_i(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vcmpy.s1.sat.r"] + fn hexagon_M2_vcmpy_s1_sat_r(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vdmacs.s0"] + fn hexagon_M2_vdmacs_s0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vdmacs.s1"] + fn hexagon_M2_vdmacs_s1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vdmpyrs.s0"] + fn hexagon_M2_vdmpyrs_s0(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.M2.vdmpyrs.s1"] + fn hexagon_M2_vdmpyrs_s1(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.M2.vdmpys.s0"] + fn hexagon_M2_vdmpys_s0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vdmpys.s1"] + fn hexagon_M2_vdmpys_s1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vmac2"] + fn hexagon_M2_vmac2(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.vmac2es"] + fn hexagon_M2_vmac2es(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vmac2es.s0"] + fn hexagon_M2_vmac2es_s0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vmac2es.s1"] + fn hexagon_M2_vmac2es_s1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vmac2s.s0"] + fn hexagon_M2_vmac2s_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.vmac2s.s1"] + fn hexagon_M2_vmac2s_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.vmac2su.s0"] + fn hexagon_M2_vmac2su_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.vmac2su.s1"] + fn hexagon_M2_vmac2su_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.vmpy2es.s0"] + fn hexagon_M2_vmpy2es_s0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vmpy2es.s1"] + fn hexagon_M2_vmpy2es_s1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vmpy2s.s0"] + fn hexagon_M2_vmpy2s_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.vmpy2s.s0pack"] + fn hexagon_M2_vmpy2s_s0pack(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.vmpy2s.s1"] + fn hexagon_M2_vmpy2s_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.vmpy2s.s1pack"] + fn hexagon_M2_vmpy2s_s1pack(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.vmpy2su.s0"] + fn hexagon_M2_vmpy2su_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.vmpy2su.s1"] + fn hexagon_M2_vmpy2su_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.vraddh"] + fn hexagon_M2_vraddh(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.M2.vradduh"] + fn hexagon_M2_vradduh(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.M2.vrcmaci.s0"] + fn hexagon_M2_vrcmaci_s0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vrcmaci.s0c"] + fn hexagon_M2_vrcmaci_s0c(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vrcmacr.s0"] + fn hexagon_M2_vrcmacr_s0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vrcmacr.s0c"] + fn hexagon_M2_vrcmacr_s0c(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vrcmpyi.s0"] + fn hexagon_M2_vrcmpyi_s0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vrcmpyi.s0c"] + fn hexagon_M2_vrcmpyi_s0c(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vrcmpyr.s0"] + fn hexagon_M2_vrcmpyr_s0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vrcmpyr.s0c"] + fn hexagon_M2_vrcmpyr_s0c(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vrcmpys.acc.s1"] + fn hexagon_M2_vrcmpys_acc_s1(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.vrcmpys.s1"] + fn hexagon_M2_vrcmpys_s1(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.vrcmpys.s1rp"] + fn hexagon_M2_vrcmpys_s1rp(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.vrmac.s0"] + fn hexagon_M2_vrmac_s0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vrmpy.s0"] + fn hexagon_M2_vrmpy_s0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.xor.xacc"] + fn hexagon_M2_xor_xacc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.and.and"] + fn hexagon_M4_and_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.and.andn"] + fn hexagon_M4_and_andn(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.and.or"] + fn hexagon_M4_and_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.and.xor"] + fn hexagon_M4_and_xor(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.cmpyi.wh"] + fn hexagon_M4_cmpyi_wh(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.cmpyi.whc"] + fn hexagon_M4_cmpyi_whc(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.cmpyr.wh"] + fn hexagon_M4_cmpyr_wh(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.cmpyr.whc"] + fn hexagon_M4_cmpyr_whc(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.mac.up.s1.sat"] + fn hexagon_M4_mac_up_s1_sat(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.mpyri.addi"] + fn hexagon_M4_mpyri_addi(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.mpyri.addr"] + fn hexagon_M4_mpyri_addr(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.mpyri.addr.u2"] + fn hexagon_M4_mpyri_addr_u2(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.mpyrr.addi"] + fn hexagon_M4_mpyrr_addi(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.mpyrr.addr"] + fn hexagon_M4_mpyrr_addr(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.nac.up.s1.sat"] + fn hexagon_M4_nac_up_s1_sat(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.or.and"] + fn hexagon_M4_or_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.or.andn"] + fn hexagon_M4_or_andn(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.or.or"] + fn hexagon_M4_or_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.or.xor"] + fn hexagon_M4_or_xor(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.pmpyw"] + fn hexagon_M4_pmpyw(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M4.pmpyw.acc"] + fn hexagon_M4_pmpyw_acc(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M4.vpmpyh"] + fn hexagon_M4_vpmpyh(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M4.vpmpyh.acc"] + fn hexagon_M4_vpmpyh_acc(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M4.vrmpyeh.acc.s0"] + fn hexagon_M4_vrmpyeh_acc_s0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M4.vrmpyeh.acc.s1"] + fn hexagon_M4_vrmpyeh_acc_s1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M4.vrmpyeh.s0"] + fn hexagon_M4_vrmpyeh_s0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M4.vrmpyeh.s1"] + fn hexagon_M4_vrmpyeh_s1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M4.vrmpyoh.acc.s0"] + fn hexagon_M4_vrmpyoh_acc_s0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M4.vrmpyoh.acc.s1"] + fn hexagon_M4_vrmpyoh_acc_s1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M4.vrmpyoh.s0"] + fn hexagon_M4_vrmpyoh_s0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M4.vrmpyoh.s1"] + fn hexagon_M4_vrmpyoh_s1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M4.xor.and"] + fn hexagon_M4_xor_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.xor.andn"] + fn hexagon_M4_xor_andn(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.xor.or"] + fn hexagon_M4_xor_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.xor.xacc"] + fn hexagon_M4_xor_xacc(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M5.vdmacbsu"] + fn hexagon_M5_vdmacbsu(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M5.vdmpybsu"] + fn hexagon_M5_vdmpybsu(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M5.vmacbsu"] + fn hexagon_M5_vmacbsu(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M5.vmacbuu"] + fn hexagon_M5_vmacbuu(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M5.vmpybsu"] + fn hexagon_M5_vmpybsu(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M5.vmpybuu"] + fn hexagon_M5_vmpybuu(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M5.vrmacbsu"] + fn hexagon_M5_vrmacbsu(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M5.vrmacbuu"] + fn hexagon_M5_vrmacbuu(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M5.vrmpybsu"] + fn hexagon_M5_vrmpybsu(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M5.vrmpybuu"] + fn hexagon_M5_vrmpybuu(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S2.addasl.rrri"] + fn hexagon_S2_addasl_rrri(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.i.p"] + fn hexagon_S2_asl_i_p(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.i.p.acc"] + fn hexagon_S2_asl_i_p_acc(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.i.p.and"] + fn hexagon_S2_asl_i_p_and(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.i.p.nac"] + fn hexagon_S2_asl_i_p_nac(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.i.p.or"] + fn hexagon_S2_asl_i_p_or(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.i.p.xacc"] + fn hexagon_S2_asl_i_p_xacc(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.i.r"] + fn hexagon_S2_asl_i_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.i.r.acc"] + fn hexagon_S2_asl_i_r_acc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.i.r.and"] + fn hexagon_S2_asl_i_r_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.i.r.nac"] + fn hexagon_S2_asl_i_r_nac(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.i.r.or"] + fn hexagon_S2_asl_i_r_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.i.r.sat"] + fn hexagon_S2_asl_i_r_sat(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.i.r.xacc"] + fn hexagon_S2_asl_i_r_xacc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.i.vh"] + fn hexagon_S2_asl_i_vh(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.i.vw"] + fn hexagon_S2_asl_i_vw(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.r.p"] + fn hexagon_S2_asl_r_p(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.r.p.acc"] + fn hexagon_S2_asl_r_p_acc(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.r.p.and"] + fn hexagon_S2_asl_r_p_and(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.r.p.nac"] + fn hexagon_S2_asl_r_p_nac(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.r.p.or"] + fn hexagon_S2_asl_r_p_or(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.r.p.xor"] + fn hexagon_S2_asl_r_p_xor(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.r.r"] + fn hexagon_S2_asl_r_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.r.r.acc"] + fn hexagon_S2_asl_r_r_acc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.r.r.and"] + fn hexagon_S2_asl_r_r_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.r.r.nac"] + fn hexagon_S2_asl_r_r_nac(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.r.r.or"] + fn hexagon_S2_asl_r_r_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.r.r.sat"] + fn hexagon_S2_asl_r_r_sat(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.r.vh"] + fn hexagon_S2_asl_r_vh(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.r.vw"] + fn hexagon_S2_asl_r_vw(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.i.p"] + fn hexagon_S2_asr_i_p(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.i.p.acc"] + fn hexagon_S2_asr_i_p_acc(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.i.p.and"] + fn hexagon_S2_asr_i_p_and(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.i.p.nac"] + fn hexagon_S2_asr_i_p_nac(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.i.p.or"] + fn hexagon_S2_asr_i_p_or(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.i.p.rnd"] + fn hexagon_S2_asr_i_p_rnd(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.i.p.rnd.goodsyntax"] + fn hexagon_S2_asr_i_p_rnd_goodsyntax(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.i.r"] + fn hexagon_S2_asr_i_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.i.r.acc"] + fn hexagon_S2_asr_i_r_acc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.i.r.and"] + fn hexagon_S2_asr_i_r_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.i.r.nac"] + fn hexagon_S2_asr_i_r_nac(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.i.r.or"] + fn hexagon_S2_asr_i_r_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.i.r.rnd"] + fn hexagon_S2_asr_i_r_rnd(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.i.r.rnd.goodsyntax"] + fn hexagon_S2_asr_i_r_rnd_goodsyntax(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.i.svw.trun"] + fn hexagon_S2_asr_i_svw_trun(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.i.vh"] + fn hexagon_S2_asr_i_vh(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.i.vw"] + fn hexagon_S2_asr_i_vw(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.r.p"] + fn hexagon_S2_asr_r_p(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.r.p.acc"] + fn hexagon_S2_asr_r_p_acc(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.r.p.and"] + fn hexagon_S2_asr_r_p_and(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.r.p.nac"] + fn hexagon_S2_asr_r_p_nac(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.r.p.or"] + fn hexagon_S2_asr_r_p_or(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.r.p.xor"] + fn hexagon_S2_asr_r_p_xor(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.r.r"] + fn hexagon_S2_asr_r_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.r.r.acc"] + fn hexagon_S2_asr_r_r_acc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.r.r.and"] + fn hexagon_S2_asr_r_r_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.r.r.nac"] + fn hexagon_S2_asr_r_r_nac(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.r.r.or"] + fn hexagon_S2_asr_r_r_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.r.r.sat"] + fn hexagon_S2_asr_r_r_sat(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.r.svw.trun"] + fn hexagon_S2_asr_r_svw_trun(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.r.vh"] + fn hexagon_S2_asr_r_vh(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.r.vw"] + fn hexagon_S2_asr_r_vw(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.brev"] + fn hexagon_S2_brev(_: i32) -> i32; + #[link_name = "llvm.hexagon.S2.brevp"] + fn hexagon_S2_brevp(_: i64) -> i64; + #[link_name = "llvm.hexagon.S2.cl0"] + fn hexagon_S2_cl0(_: i32) -> i32; + #[link_name = "llvm.hexagon.S2.cl0p"] + fn hexagon_S2_cl0p(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.cl1"] + fn hexagon_S2_cl1(_: i32) -> i32; + #[link_name = "llvm.hexagon.S2.cl1p"] + fn hexagon_S2_cl1p(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.clb"] + fn hexagon_S2_clb(_: i32) -> i32; + #[link_name = "llvm.hexagon.S2.clbnorm"] + fn hexagon_S2_clbnorm(_: i32) -> i32; + #[link_name = "llvm.hexagon.S2.clbp"] + fn hexagon_S2_clbp(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.clrbit.i"] + fn hexagon_S2_clrbit_i(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.clrbit.r"] + fn hexagon_S2_clrbit_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.ct0"] + fn hexagon_S2_ct0(_: i32) -> i32; + #[link_name = "llvm.hexagon.S2.ct0p"] + fn hexagon_S2_ct0p(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.ct1"] + fn hexagon_S2_ct1(_: i32) -> i32; + #[link_name = "llvm.hexagon.S2.ct1p"] + fn hexagon_S2_ct1p(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.deinterleave"] + fn hexagon_S2_deinterleave(_: i64) -> i64; + #[link_name = "llvm.hexagon.S2.extractu"] + fn hexagon_S2_extractu(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.extractu.rp"] + fn hexagon_S2_extractu_rp(_: i32, _: i64) -> i32; + #[link_name = "llvm.hexagon.S2.extractup"] + fn hexagon_S2_extractup(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.extractup.rp"] + fn hexagon_S2_extractup_rp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S2.insert"] + fn hexagon_S2_insert(_: i32, _: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.insert.rp"] + fn hexagon_S2_insert_rp(_: i32, _: i32, _: i64) -> i32; + #[link_name = "llvm.hexagon.S2.insertp"] + fn hexagon_S2_insertp(_: i64, _: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.insertp.rp"] + fn hexagon_S2_insertp_rp(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S2.interleave"] + fn hexagon_S2_interleave(_: i64) -> i64; + #[link_name = "llvm.hexagon.S2.lfsp"] + fn hexagon_S2_lfsp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S2.lsl.r.p"] + fn hexagon_S2_lsl_r_p(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsl.r.p.acc"] + fn hexagon_S2_lsl_r_p_acc(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsl.r.p.and"] + fn hexagon_S2_lsl_r_p_and(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsl.r.p.nac"] + fn hexagon_S2_lsl_r_p_nac(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsl.r.p.or"] + fn hexagon_S2_lsl_r_p_or(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsl.r.p.xor"] + fn hexagon_S2_lsl_r_p_xor(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsl.r.r"] + fn hexagon_S2_lsl_r_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsl.r.r.acc"] + fn hexagon_S2_lsl_r_r_acc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsl.r.r.and"] + fn hexagon_S2_lsl_r_r_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsl.r.r.nac"] + fn hexagon_S2_lsl_r_r_nac(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsl.r.r.or"] + fn hexagon_S2_lsl_r_r_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsl.r.vh"] + fn hexagon_S2_lsl_r_vh(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsl.r.vw"] + fn hexagon_S2_lsl_r_vw(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.i.p"] + fn hexagon_S2_lsr_i_p(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.i.p.acc"] + fn hexagon_S2_lsr_i_p_acc(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.i.p.and"] + fn hexagon_S2_lsr_i_p_and(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.i.p.nac"] + fn hexagon_S2_lsr_i_p_nac(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.i.p.or"] + fn hexagon_S2_lsr_i_p_or(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.i.p.xacc"] + fn hexagon_S2_lsr_i_p_xacc(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.i.r"] + fn hexagon_S2_lsr_i_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsr.i.r.acc"] + fn hexagon_S2_lsr_i_r_acc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsr.i.r.and"] + fn hexagon_S2_lsr_i_r_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsr.i.r.nac"] + fn hexagon_S2_lsr_i_r_nac(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsr.i.r.or"] + fn hexagon_S2_lsr_i_r_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsr.i.r.xacc"] + fn hexagon_S2_lsr_i_r_xacc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsr.i.vh"] + fn hexagon_S2_lsr_i_vh(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.i.vw"] + fn hexagon_S2_lsr_i_vw(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.r.p"] + fn hexagon_S2_lsr_r_p(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.r.p.acc"] + fn hexagon_S2_lsr_r_p_acc(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.r.p.and"] + fn hexagon_S2_lsr_r_p_and(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.r.p.nac"] + fn hexagon_S2_lsr_r_p_nac(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.r.p.or"] + fn hexagon_S2_lsr_r_p_or(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.r.p.xor"] + fn hexagon_S2_lsr_r_p_xor(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.r.r"] + fn hexagon_S2_lsr_r_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsr.r.r.acc"] + fn hexagon_S2_lsr_r_r_acc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsr.r.r.and"] + fn hexagon_S2_lsr_r_r_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsr.r.r.nac"] + fn hexagon_S2_lsr_r_r_nac(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsr.r.r.or"] + fn hexagon_S2_lsr_r_r_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsr.r.vh"] + fn hexagon_S2_lsr_r_vh(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.r.vw"] + fn hexagon_S2_lsr_r_vw(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.packhl"] + fn hexagon_S2_packhl(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.parityp"] + fn hexagon_S2_parityp(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.S2.setbit.i"] + fn hexagon_S2_setbit_i(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.setbit.r"] + fn hexagon_S2_setbit_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.shuffeb"] + fn hexagon_S2_shuffeb(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S2.shuffeh"] + fn hexagon_S2_shuffeh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S2.shuffob"] + fn hexagon_S2_shuffob(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S2.shuffoh"] + fn hexagon_S2_shuffoh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S2.svsathb"] + fn hexagon_S2_svsathb(_: i32) -> i32; + #[link_name = "llvm.hexagon.S2.svsathub"] + fn hexagon_S2_svsathub(_: i32) -> i32; + #[link_name = "llvm.hexagon.S2.tableidxb.goodsyntax"] + fn hexagon_S2_tableidxb_goodsyntax(_: i32, _: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.tableidxd.goodsyntax"] + fn hexagon_S2_tableidxd_goodsyntax(_: i32, _: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.tableidxh.goodsyntax"] + fn hexagon_S2_tableidxh_goodsyntax(_: i32, _: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.tableidxw.goodsyntax"] + fn hexagon_S2_tableidxw_goodsyntax(_: i32, _: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.togglebit.i"] + fn hexagon_S2_togglebit_i(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.togglebit.r"] + fn hexagon_S2_togglebit_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.tstbit.i"] + fn hexagon_S2_tstbit_i(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.tstbit.r"] + fn hexagon_S2_tstbit_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.valignib"] + fn hexagon_S2_valignib(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.valignrb"] + fn hexagon_S2_valignrb(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.vcnegh"] + fn hexagon_S2_vcnegh(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.vcrotate"] + fn hexagon_S2_vcrotate(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.vrcnegh"] + fn hexagon_S2_vrcnegh(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.vrndpackwh"] + fn hexagon_S2_vrndpackwh(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.vrndpackwhs"] + fn hexagon_S2_vrndpackwhs(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.vsathb"] + fn hexagon_S2_vsathb(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.vsathb.nopack"] + fn hexagon_S2_vsathb_nopack(_: i64) -> i64; + #[link_name = "llvm.hexagon.S2.vsathub"] + fn hexagon_S2_vsathub(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.vsathub.nopack"] + fn hexagon_S2_vsathub_nopack(_: i64) -> i64; + #[link_name = "llvm.hexagon.S2.vsatwh"] + fn hexagon_S2_vsatwh(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.vsatwh.nopack"] + fn hexagon_S2_vsatwh_nopack(_: i64) -> i64; + #[link_name = "llvm.hexagon.S2.vsatwuh"] + fn hexagon_S2_vsatwuh(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.vsatwuh.nopack"] + fn hexagon_S2_vsatwuh_nopack(_: i64) -> i64; + #[link_name = "llvm.hexagon.S2.vsplatrb"] + fn hexagon_S2_vsplatrb(_: i32) -> i32; + #[link_name = "llvm.hexagon.S2.vsplatrh"] + fn hexagon_S2_vsplatrh(_: i32) -> i64; + #[link_name = "llvm.hexagon.S2.vspliceib"] + fn hexagon_S2_vspliceib(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.vsplicerb"] + fn hexagon_S2_vsplicerb(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.vsxtbh"] + fn hexagon_S2_vsxtbh(_: i32) -> i64; + #[link_name = "llvm.hexagon.S2.vsxthw"] + fn hexagon_S2_vsxthw(_: i32) -> i64; + #[link_name = "llvm.hexagon.S2.vtrunehb"] + fn hexagon_S2_vtrunehb(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.vtrunewh"] + fn hexagon_S2_vtrunewh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S2.vtrunohb"] + fn hexagon_S2_vtrunohb(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.vtrunowh"] + fn hexagon_S2_vtrunowh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S2.vzxtbh"] + fn hexagon_S2_vzxtbh(_: i32) -> i64; + #[link_name = "llvm.hexagon.S2.vzxthw"] + fn hexagon_S2_vzxthw(_: i32) -> i64; + #[link_name = "llvm.hexagon.S4.addaddi"] + fn hexagon_S4_addaddi(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.addi.asl.ri"] + fn hexagon_S4_addi_asl_ri(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.addi.lsr.ri"] + fn hexagon_S4_addi_lsr_ri(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.andi.asl.ri"] + fn hexagon_S4_andi_asl_ri(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.andi.lsr.ri"] + fn hexagon_S4_andi_lsr_ri(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.clbaddi"] + fn hexagon_S4_clbaddi(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.clbpaddi"] + fn hexagon_S4_clbpaddi(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.clbpnorm"] + fn hexagon_S4_clbpnorm(_: i64) -> i32; + #[link_name = "llvm.hexagon.S4.extract"] + fn hexagon_S4_extract(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.extract.rp"] + fn hexagon_S4_extract_rp(_: i32, _: i64) -> i32; + #[link_name = "llvm.hexagon.S4.extractp"] + fn hexagon_S4_extractp(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.S4.extractp.rp"] + fn hexagon_S4_extractp_rp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S4.lsli"] + fn hexagon_S4_lsli(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.ntstbit.i"] + fn hexagon_S4_ntstbit_i(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.ntstbit.r"] + fn hexagon_S4_ntstbit_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.or.andi"] + fn hexagon_S4_or_andi(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.or.andix"] + fn hexagon_S4_or_andix(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.or.ori"] + fn hexagon_S4_or_ori(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.ori.asl.ri"] + fn hexagon_S4_ori_asl_ri(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.ori.lsr.ri"] + fn hexagon_S4_ori_lsr_ri(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.parity"] + fn hexagon_S4_parity(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.subaddi"] + fn hexagon_S4_subaddi(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.subi.asl.ri"] + fn hexagon_S4_subi_asl_ri(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.subi.lsr.ri"] + fn hexagon_S4_subi_lsr_ri(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.vrcrotate"] + fn hexagon_S4_vrcrotate(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.S4.vrcrotate.acc"] + fn hexagon_S4_vrcrotate_acc(_: i64, _: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.S4.vxaddsubh"] + fn hexagon_S4_vxaddsubh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S4.vxaddsubhr"] + fn hexagon_S4_vxaddsubhr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S4.vxaddsubw"] + fn hexagon_S4_vxaddsubw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S4.vxsubaddh"] + fn hexagon_S4_vxsubaddh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S4.vxsubaddhr"] + fn hexagon_S4_vxsubaddhr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S4.vxsubaddw"] + fn hexagon_S4_vxsubaddw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax"] + fn hexagon_S5_asrhub_rnd_sat_goodsyntax(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.S5.asrhub.sat"] + fn hexagon_S5_asrhub_sat(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.S5.popcountp"] + fn hexagon_S5_popcountp(_: i64) -> i32; + #[link_name = "llvm.hexagon.S5.vasrhrnd.goodsyntax"] + fn hexagon_S5_vasrhrnd_goodsyntax(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.Y2.dccleana"] + fn hexagon_Y2_dccleana(_: i32); + #[link_name = "llvm.hexagon.Y2.dccleaninva"] + fn hexagon_Y2_dccleaninva(_: i32); + #[link_name = "llvm.hexagon.Y2.dcfetch"] + fn hexagon_Y2_dcfetch(_: i32); + #[link_name = "llvm.hexagon.Y2.dcinva"] + fn hexagon_Y2_dcinva(_: i32); + #[link_name = "llvm.hexagon.Y2.dczeroa"] + fn hexagon_Y2_dczeroa(_: i32); + #[link_name = "llvm.hexagon.Y4.l2fetch"] + fn hexagon_Y4_l2fetch(_: i32, _: i32); + #[link_name = "llvm.hexagon.Y5.l2fetch"] + fn hexagon_Y5_l2fetch(_: i32, _: i64); + #[link_name = "llvm.hexagon.S6.rol.i.p"] + fn hexagon_S6_rol_i_p(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S6.rol.i.p.acc"] + fn hexagon_S6_rol_i_p_acc(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S6.rol.i.p.and"] + fn hexagon_S6_rol_i_p_and(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S6.rol.i.p.nac"] + fn hexagon_S6_rol_i_p_nac(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S6.rol.i.p.or"] + fn hexagon_S6_rol_i_p_or(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S6.rol.i.p.xacc"] + fn hexagon_S6_rol_i_p_xacc(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S6.rol.i.r"] + fn hexagon_S6_rol_i_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S6.rol.i.r.acc"] + fn hexagon_S6_rol_i_r_acc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S6.rol.i.r.and"] + fn hexagon_S6_rol_i_r_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S6.rol.i.r.nac"] + fn hexagon_S6_rol_i_r_nac(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S6.rol.i.r.or"] + fn hexagon_S6_rol_i_r_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S6.rol.i.r.xacc"] + fn hexagon_S6_rol_i_r_xacc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M6.vabsdiffb"] + fn hexagon_M6_vabsdiffb(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M6.vabsdiffub"] + fn hexagon_M6_vabsdiffub(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S6.vsplatrbp"] + fn hexagon_S6_vsplatrbp(_: i32) -> i64; + #[link_name = "llvm.hexagon.S6.vtrunehb.ppp"] + fn hexagon_S6_vtrunehb_ppp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S6.vtrunohb.ppp"] + fn hexagon_S6_vtrunohb_ppp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A6.vcmpbeq.notany"] + fn hexagon_A6_vcmpbeq_notany(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.F2.dfadd"] + fn hexagon_F2_dfadd(_: f64, _: f64) -> f64; + #[link_name = "llvm.hexagon.F2.dfsub"] + fn hexagon_F2_dfsub(_: f64, _: f64) -> f64; + #[link_name = "llvm.hexagon.M2.mnaci"] + fn hexagon_M2_mnaci(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.mask"] + fn hexagon_S2_mask(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A7.clip"] + fn hexagon_A7_clip(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A7.croundd.ri"] + fn hexagon_A7_croundd_ri(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.A7.croundd.rr"] + fn hexagon_A7_croundd_rr(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.A7.vclip"] + fn hexagon_A7_vclip(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.F2.dfmax"] + fn hexagon_F2_dfmax(_: f64, _: f64) -> f64; + #[link_name = "llvm.hexagon.F2.dfmin"] + fn hexagon_F2_dfmin(_: f64, _: f64) -> f64; + #[link_name = "llvm.hexagon.F2.dfmpyfix"] + fn hexagon_F2_dfmpyfix(_: f64, _: f64) -> f64; + #[link_name = "llvm.hexagon.F2.dfmpyhh"] + fn hexagon_F2_dfmpyhh(_: f64, _: f64, _: f64) -> f64; + #[link_name = "llvm.hexagon.F2.dfmpylh"] + fn hexagon_F2_dfmpylh(_: f64, _: f64, _: f64) -> f64; + #[link_name = "llvm.hexagon.F2.dfmpyll"] + fn hexagon_F2_dfmpyll(_: f64, _: f64) -> f64; + #[link_name = "llvm.hexagon.M7.dcmpyiw"] + fn hexagon_M7_dcmpyiw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M7.dcmpyiw.acc"] + fn hexagon_M7_dcmpyiw_acc(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M7.dcmpyiwc"] + fn hexagon_M7_dcmpyiwc(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M7.dcmpyiwc.acc"] + fn hexagon_M7_dcmpyiwc_acc(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M7.dcmpyrw"] + fn hexagon_M7_dcmpyrw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M7.dcmpyrw.acc"] + fn hexagon_M7_dcmpyrw_acc(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M7.dcmpyrwc"] + fn hexagon_M7_dcmpyrwc(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M7.dcmpyrwc.acc"] + fn hexagon_M7_dcmpyrwc_acc(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M7.vdmpy"] + fn hexagon_M7_vdmpy(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M7.vdmpy.acc"] + fn hexagon_M7_vdmpy_acc(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M7.wcmpyiw"] + fn hexagon_M7_wcmpyiw(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.M7.wcmpyiw.rnd"] + fn hexagon_M7_wcmpyiw_rnd(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.M7.wcmpyiwc"] + fn hexagon_M7_wcmpyiwc(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.M7.wcmpyiwc.rnd"] + fn hexagon_M7_wcmpyiwc_rnd(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.M7.wcmpyrw"] + fn hexagon_M7_wcmpyrw(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.M7.wcmpyrw.rnd"] + fn hexagon_M7_wcmpyrw_rnd(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.M7.wcmpyrwc"] + fn hexagon_M7_wcmpyrwc(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.M7.wcmpyrwc.rnd"] + fn hexagon_M7_wcmpyrwc_rnd(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.Y6.dmlink"] + fn hexagon_Y6_dmlink(_: i32, _: i32); + #[link_name = "llvm.hexagon.Y6.dmpause"] + fn hexagon_Y6_dmpause() -> i32; + #[link_name = "llvm.hexagon.Y6.dmpoll"] + fn hexagon_Y6_dmpoll() -> i32; + #[link_name = "llvm.hexagon.Y6.dmresume"] + fn hexagon_Y6_dmresume(_: i32); + #[link_name = "llvm.hexagon.Y6.dmstart"] + fn hexagon_Y6_dmstart(_: i32); + #[link_name = "llvm.hexagon.Y6.dmwait"] + fn hexagon_Y6_dmwait() -> i32; +} + +/// `Rd32=abs(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(abs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_abs_R(rs: i32) -> i32 { + hexagon_A2_abs(rs) +} + +/// `Rdd32=abs(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(abs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_abs_P(rss: i64) -> i64 { + hexagon_A2_absp(rss) +} + +/// `Rd32=abs(Rs32):sat` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(abs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_abs_R_sat(rs: i32) -> i32 { + hexagon_A2_abssat(rs) +} + +/// `Rd32=add(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RR(rs: i32, rt: i32) -> i32 { + hexagon_A2_add(rs, rt) +} + +/// `Rd32=add(Rt32.h,Rs32.h):<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RhRh_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_h16_hh(rt, rs) +} + +/// `Rd32=add(Rt32.h,Rs32.l):<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RhRl_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_h16_hl(rt, rs) +} + +/// `Rd32=add(Rt32.l,Rs32.h):<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RlRh_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_h16_lh(rt, rs) +} + +/// `Rd32=add(Rt32.l,Rs32.l):<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RlRl_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_h16_ll(rt, rs) +} + +/// `Rd32=add(Rt32.h,Rs32.h):sat:<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RhRh_sat_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_h16_sat_hh(rt, rs) +} + +/// `Rd32=add(Rt32.h,Rs32.l):sat:<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RhRl_sat_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_h16_sat_hl(rt, rs) +} + +/// `Rd32=add(Rt32.l,Rs32.h):sat:<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RlRh_sat_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_h16_sat_lh(rt, rs) +} + +/// `Rd32=add(Rt32.l,Rs32.l):sat:<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RlRl_sat_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_h16_sat_ll(rt, rs) +} + +/// `Rd32=add(Rt32.l,Rs32.h)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RlRh(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_l16_hl(rt, rs) +} + +/// `Rd32=add(Rt32.l,Rs32.l)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RlRl(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_l16_ll(rt, rs) +} + +/// `Rd32=add(Rt32.l,Rs32.h):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RlRh_sat(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_l16_sat_hl(rt, rs) +} + +/// `Rd32=add(Rt32.l,Rs32.l):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RlRl_sat(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_l16_sat_ll(rt, rs) +} + +/// `Rd32=add(Rs32,#s16)` +/// +/// Instruction Type: ALU32_ADDI +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(add, IS16 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS16, 16); + hexagon_A2_addi(rs, IS16) +} + +/// `Rdd32=add(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_add_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_addp(rss, rtt) +} + +/// `Rdd32=add(Rss32,Rtt32):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_add_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_A2_addpsat(rss, rtt) +} + +/// `Rd32=add(Rs32,Rt32):sat` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RR_sat(rs: i32, rt: i32) -> i32 { + hexagon_A2_addsat(rs, rt) +} + +/// `Rdd32=add(Rs32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_add_RP(rs: i32, rtt: i64) -> i64 { + hexagon_A2_addsp(rs, rtt) +} + +/// `Rd32=and(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_and_RR(rs: i32, rt: i32) -> i32 { + hexagon_A2_and(rs, rt) +} + +/// `Rd32=and(Rs32,#s10)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(and, IS10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_and_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS10, 10); + hexagon_A2_andir(rs, IS10) +} + +/// `Rdd32=and(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_and_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_andp(rss, rtt) +} + +/// `Rd32=aslh(Rs32)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(aslh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_aslh_R(rs: i32) -> i32 { + hexagon_A2_aslh(rs) +} + +/// `Rd32=asrh(Rs32)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(asrh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asrh_R(rs: i32) -> i32 { + hexagon_A2_asrh(rs) +} + +/// `Rd32=combine(Rt32.h,Rs32.h)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(combine))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_combine_RhRh(rt: i32, rs: i32) -> i32 { + hexagon_A2_combine_hh(rt, rs) +} + +/// `Rd32=combine(Rt32.h,Rs32.l)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(combine))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_combine_RhRl(rt: i32, rs: i32) -> i32 { + hexagon_A2_combine_hl(rt, rs) +} + +/// `Rd32=combine(Rt32.l,Rs32.h)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(combine))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_combine_RlRh(rt: i32, rs: i32) -> i32 { + hexagon_A2_combine_lh(rt, rs) +} + +/// `Rd32=combine(Rt32.l,Rs32.l)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(combine))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_combine_RlRl(rt: i32, rs: i32) -> i32 { + hexagon_A2_combine_ll(rt, rs) +} + +/// `Rdd32=combine(#s8,#S8)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(0, 1)] +#[cfg_attr(test, assert_instr(combine, IS8 = 0, IS8_2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_combine_II() -> i64 { + static_assert_simm_bits!(IS8, 8); + static_assert_simm_bits!(IS8_2, 8); + hexagon_A2_combineii(IS8, IS8_2) +} + +/// `Rdd32=combine(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(combine))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_combine_RR(rs: i32, rt: i32) -> i64 { + hexagon_A2_combinew(rs, rt) +} + +/// `Rd32=max(Rs32,Rt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(max))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_max_RR(rs: i32, rt: i32) -> i32 { + hexagon_A2_max(rs, rt) +} + +/// `Rdd32=max(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(max))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_max_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_maxp(rss, rtt) +} + +/// `Rd32=maxu(Rs32,Rt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(maxu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_maxu_RR(rs: i32, rt: i32) -> i32 { + hexagon_A2_maxu(rs, rt) +} + +/// `Rdd32=maxu(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(maxu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_maxu_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_maxup(rss, rtt) +} + +/// `Rd32=min(Rt32,Rs32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(min))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_min_RR(rt: i32, rs: i32) -> i32 { + hexagon_A2_min(rt, rs) +} + +/// `Rdd32=min(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(min))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_min_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_minp(rtt, rss) +} + +/// `Rd32=minu(Rt32,Rs32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(minu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_minu_RR(rt: i32, rs: i32) -> i32 { + hexagon_A2_minu(rt, rs) +} + +/// `Rdd32=minu(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(minu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_minu_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_minup(rtt, rss) +} + +/// `Rd32=neg(Rs32)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(neg))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_neg_R(rs: i32) -> i32 { + hexagon_A2_neg(rs) +} + +/// `Rdd32=neg(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(neg))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_neg_P(rss: i64) -> i64 { + hexagon_A2_negp(rss) +} + +/// `Rd32=neg(Rs32):sat` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(neg))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_neg_R_sat(rs: i32) -> i32 { + hexagon_A2_negsat(rs) +} + +/// `Rd32=not(Rs32)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(not))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_not_R(rs: i32) -> i32 { + hexagon_A2_not(rs) +} + +/// `Rdd32=not(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(not))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_not_P(rss: i64) -> i64 { + hexagon_A2_notp(rss) +} + +/// `Rd32=or(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_or_RR(rs: i32, rt: i32) -> i32 { + hexagon_A2_or(rs, rt) +} + +/// `Rd32=or(Rs32,#s10)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(or, IS10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_or_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS10, 10); + hexagon_A2_orir(rs, IS10) +} + +/// `Rdd32=or(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_or_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_orp(rss, rtt) +} + +/// `Rd32=round(Rss32):sat` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(round))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_round_P_sat(rss: i64) -> i32 { + hexagon_A2_roundsat(rss) +} + +/// `Rd32=sat(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sat_P(rss: i64) -> i32 { + hexagon_A2_sat(rss) +} + +/// `Rd32=satb(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(satb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_satb_R(rs: i32) -> i32 { + hexagon_A2_satb(rs) +} + +/// `Rd32=sath(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sath))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sath_R(rs: i32) -> i32 { + hexagon_A2_sath(rs) +} + +/// `Rd32=satub(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(satub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_satub_R(rs: i32) -> i32 { + hexagon_A2_satub(rs) +} + +/// `Rd32=satuh(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(satuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_satuh_R(rs: i32) -> i32 { + hexagon_A2_satuh(rs) +} + +/// `Rd32=sub(Rt32,Rs32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RR(rt: i32, rs: i32) -> i32 { + hexagon_A2_sub(rt, rs) +} + +/// `Rd32=sub(Rt32.h,Rs32.h):<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RhRh_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_h16_hh(rt, rs) +} + +/// `Rd32=sub(Rt32.h,Rs32.l):<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RhRl_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_h16_hl(rt, rs) +} + +/// `Rd32=sub(Rt32.l,Rs32.h):<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RlRh_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_h16_lh(rt, rs) +} + +/// `Rd32=sub(Rt32.l,Rs32.l):<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RlRl_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_h16_ll(rt, rs) +} + +/// `Rd32=sub(Rt32.h,Rs32.h):sat:<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RhRh_sat_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_h16_sat_hh(rt, rs) +} + +/// `Rd32=sub(Rt32.h,Rs32.l):sat:<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RhRl_sat_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_h16_sat_hl(rt, rs) +} + +/// `Rd32=sub(Rt32.l,Rs32.h):sat:<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RlRh_sat_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_h16_sat_lh(rt, rs) +} + +/// `Rd32=sub(Rt32.l,Rs32.l):sat:<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RlRl_sat_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_h16_sat_ll(rt, rs) +} + +/// `Rd32=sub(Rt32.l,Rs32.h)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RlRh(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_l16_hl(rt, rs) +} + +/// `Rd32=sub(Rt32.l,Rs32.l)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RlRl(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_l16_ll(rt, rs) +} + +/// `Rd32=sub(Rt32.l,Rs32.h):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RlRh_sat(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_l16_sat_hl(rt, rs) +} + +/// `Rd32=sub(Rt32.l,Rs32.l):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RlRl_sat(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_l16_sat_ll(rt, rs) +} + +/// `Rdd32=sub(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_sub_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_subp(rtt, rss) +} + +/// `Rd32=sub(#s10,Rs32)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(0)] +#[cfg_attr(test, assert_instr(sub, IS10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_IR(rs: i32) -> i32 { + static_assert_simm_bits!(IS10, 10); + hexagon_A2_subri(IS10, rs) +} + +/// `Rd32=sub(Rt32,Rs32):sat` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RR_sat(rt: i32, rs: i32) -> i32 { + hexagon_A2_subsat(rt, rs) +} + +/// `Rd32=vaddh(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaddh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vaddh_RR(rs: i32, rt: i32) -> i32 { + hexagon_A2_svaddh(rs, rt) +} + +/// `Rd32=vaddh(Rs32,Rt32):sat` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaddh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vaddh_RR_sat(rs: i32, rt: i32) -> i32 { + hexagon_A2_svaddhs(rs, rt) +} + +/// `Rd32=vadduh(Rs32,Rt32):sat` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vadduh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vadduh_RR_sat(rs: i32, rt: i32) -> i32 { + hexagon_A2_svadduhs(rs, rt) +} + +/// `Rd32=vavgh(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vavgh_RR(rs: i32, rt: i32) -> i32 { + hexagon_A2_svavgh(rs, rt) +} + +/// `Rd32=vavgh(Rs32,Rt32):rnd` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vavgh_RR_rnd(rs: i32, rt: i32) -> i32 { + hexagon_A2_svavghs(rs, rt) +} + +/// `Rd32=vnavgh(Rt32,Rs32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vnavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vnavgh_RR(rt: i32, rs: i32) -> i32 { + hexagon_A2_svnavgh(rt, rs) +} + +/// `Rd32=vsubh(Rt32,Rs32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vsubh_RR(rt: i32, rs: i32) -> i32 { + hexagon_A2_svsubh(rt, rs) +} + +/// `Rd32=vsubh(Rt32,Rs32):sat` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vsubh_RR_sat(rt: i32, rs: i32) -> i32 { + hexagon_A2_svsubhs(rt, rs) +} + +/// `Rd32=vsubuh(Rt32,Rs32):sat` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsubuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vsubuh_RR_sat(rt: i32, rs: i32) -> i32 { + hexagon_A2_svsubuhs(rt, rs) +} + +/// `Rd32=swiz(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(swiz))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_swiz_R(rs: i32) -> i32 { + hexagon_A2_swiz(rs) +} + +/// `Rd32=sxtb(Rs32)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(sxtb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sxtb_R(rs: i32) -> i32 { + hexagon_A2_sxtb(rs) +} + +/// `Rd32=sxth(Rs32)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(sxth))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sxth_R(rs: i32) -> i32 { + hexagon_A2_sxth(rs) +} + +/// `Rdd32=sxtw(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sxtw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_sxtw_R(rs: i32) -> i64 { + hexagon_A2_sxtw(rs) +} + +/// `Rd32=Rs32` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_equals_R(rs: i32) -> i32 { + hexagon_A2_tfr(rs) +} + +/// `Rx32.h=#u16` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Rh_equals_I(rx: i32) -> i32 { + static_assert_uimm_bits!(IU16, 16); + hexagon_A2_tfrih(rx, IU16 as i32) +} + +/// `Rx32.l=#u16` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Rl_equals_I(rx: i32) -> i32 { + static_assert_uimm_bits!(IU16, 16); + hexagon_A2_tfril(rx, IU16 as i32) +} + +/// `Rdd32=Rss32` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_equals_P(rss: i64) -> i64 { + hexagon_A2_tfrp(rss) +} + +/// `Rdd32=#s8` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(0)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_equals_I() -> i64 { + static_assert_simm_bits!(IS8, 8); + hexagon_A2_tfrpi(IS8) +} + +/// `Rd32=#s16` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(0)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_equals_I() -> i32 { + static_assert_simm_bits!(IS16, 16); + hexagon_A2_tfrsi(IS16) +} + +/// `Rdd32=vabsh(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vabsh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vabsh_P(rss: i64) -> i64 { + hexagon_A2_vabsh(rss) +} + +/// `Rdd32=vabsh(Rss32):sat` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vabsh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vabsh_P_sat(rss: i64) -> i64 { + hexagon_A2_vabshsat(rss) +} + +/// `Rdd32=vabsw(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vabsw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vabsw_P(rss: i64) -> i64 { + hexagon_A2_vabsw(rss) +} + +/// `Rdd32=vabsw(Rss32):sat` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vabsw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vabsw_P_sat(rss: i64) -> i64 { + hexagon_A2_vabswsat(rss) +} + +/// `Rdd32=vaddb(Rss32,Rtt32)` +/// +/// Instruction Type: MAPPING +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaddb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vaddb_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vaddb_map(rss, rtt) +} + +/// `Rdd32=vaddh(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaddh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vaddh_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vaddh(rss, rtt) +} + +/// `Rdd32=vaddh(Rss32,Rtt32):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaddh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vaddh_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vaddhs(rss, rtt) +} + +/// `Rdd32=vaddub(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaddub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vaddub_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vaddub(rss, rtt) +} + +/// `Rdd32=vaddub(Rss32,Rtt32):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaddub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vaddub_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vaddubs(rss, rtt) +} + +/// `Rdd32=vadduh(Rss32,Rtt32):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vadduh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vadduh_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vadduhs(rss, rtt) +} + +/// `Rdd32=vaddw(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaddw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vaddw_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vaddw(rss, rtt) +} + +/// `Rdd32=vaddw(Rss32,Rtt32):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaddw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vaddw_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vaddws(rss, rtt) +} + +/// `Rdd32=vavgh(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavgh_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavgh(rss, rtt) +} + +/// `Rdd32=vavgh(Rss32,Rtt32):crnd` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavgh_PP_crnd(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavghcr(rss, rtt) +} + +/// `Rdd32=vavgh(Rss32,Rtt32):rnd` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavgh_PP_rnd(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavghr(rss, rtt) +} + +/// `Rdd32=vavgub(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavgub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavgub_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavgub(rss, rtt) +} + +/// `Rdd32=vavgub(Rss32,Rtt32):rnd` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavgub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavgub_PP_rnd(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavgubr(rss, rtt) +} + +/// `Rdd32=vavguh(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavguh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavguh_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavguh(rss, rtt) +} + +/// `Rdd32=vavguh(Rss32,Rtt32):rnd` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavguh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavguh_PP_rnd(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavguhr(rss, rtt) +} + +/// `Rdd32=vavguw(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavguw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavguw_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavguw(rss, rtt) +} + +/// `Rdd32=vavguw(Rss32,Rtt32):rnd` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavguw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavguw_PP_rnd(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavguwr(rss, rtt) +} + +/// `Rdd32=vavgw(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavgw_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavgw(rss, rtt) +} + +/// `Rdd32=vavgw(Rss32,Rtt32):crnd` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavgw_PP_crnd(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavgwcr(rss, rtt) +} + +/// `Rdd32=vavgw(Rss32,Rtt32):rnd` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavgw_PP_rnd(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavgwr(rss, rtt) +} + +/// `Pd4=vcmpb.eq(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpb_eq_PP(rss: i64, rtt: i64) -> i32 { + hexagon_A2_vcmpbeq(rss, rtt) +} + +/// `Pd4=vcmpb.gtu(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpb_gtu_PP(rss: i64, rtt: i64) -> i32 { + hexagon_A2_vcmpbgtu(rss, rtt) +} + +/// `Pd4=vcmph.eq(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmph))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmph_eq_PP(rss: i64, rtt: i64) -> i32 { + hexagon_A2_vcmpheq(rss, rtt) +} + +/// `Pd4=vcmph.gt(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmph))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmph_gt_PP(rss: i64, rtt: i64) -> i32 { + hexagon_A2_vcmphgt(rss, rtt) +} + +/// `Pd4=vcmph.gtu(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmph))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmph_gtu_PP(rss: i64, rtt: i64) -> i32 { + hexagon_A2_vcmphgtu(rss, rtt) +} + +/// `Pd4=vcmpw.eq(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpw_eq_PP(rss: i64, rtt: i64) -> i32 { + hexagon_A2_vcmpweq(rss, rtt) +} + +/// `Pd4=vcmpw.gt(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpw_gt_PP(rss: i64, rtt: i64) -> i32 { + hexagon_A2_vcmpwgt(rss, rtt) +} + +/// `Pd4=vcmpw.gtu(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpw_gtu_PP(rss: i64, rtt: i64) -> i32 { + hexagon_A2_vcmpwgtu(rss, rtt) +} + +/// `Rdd32=vconj(Rss32):sat` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vconj))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vconj_P_sat(rss: i64) -> i64 { + hexagon_A2_vconj(rss) +} + +/// `Rdd32=vmaxb(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmaxb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmaxb_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vmaxb(rtt, rss) +} + +/// `Rdd32=vmaxh(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmaxh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmaxh_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vmaxh(rtt, rss) +} + +/// `Rdd32=vmaxub(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmaxub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmaxub_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vmaxub(rtt, rss) +} + +/// `Rdd32=vmaxuh(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmaxuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmaxuh_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vmaxuh(rtt, rss) +} + +/// `Rdd32=vmaxuw(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmaxuw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmaxuw_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vmaxuw(rtt, rss) +} + +/// `Rdd32=vmaxw(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmaxw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmaxw_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vmaxw(rtt, rss) +} + +/// `Rdd32=vminb(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vminb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vminb_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vminb(rtt, rss) +} + +/// `Rdd32=vminh(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vminh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vminh_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vminh(rtt, rss) +} + +/// `Rdd32=vminub(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vminub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vminub_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vminub(rtt, rss) +} + +/// `Rdd32=vminuh(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vminuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vminuh_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vminuh(rtt, rss) +} + +/// `Rdd32=vminuw(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vminuw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vminuw_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vminuw(rtt, rss) +} + +/// `Rdd32=vminw(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vminw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vminw_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vminw(rtt, rss) +} + +/// `Rdd32=vnavgh(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vnavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vnavgh_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vnavgh(rtt, rss) +} + +/// `Rdd32=vnavgh(Rtt32,Rss32):crnd:sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vnavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vnavgh_PP_crnd_sat(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vnavghcr(rtt, rss) +} + +/// `Rdd32=vnavgh(Rtt32,Rss32):rnd:sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vnavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vnavgh_PP_rnd_sat(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vnavghr(rtt, rss) +} + +/// `Rdd32=vnavgw(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vnavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vnavgw_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vnavgw(rtt, rss) +} + +/// `Rdd32=vnavgw(Rtt32,Rss32):crnd:sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vnavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vnavgw_PP_crnd_sat(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vnavgwcr(rtt, rss) +} + +/// `Rdd32=vnavgw(Rtt32,Rss32):rnd:sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vnavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vnavgw_PP_rnd_sat(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vnavgwr(rtt, rss) +} + +/// `Rdd32=vraddub(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vraddub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vraddub_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vraddub(rss, rtt) +} + +/// `Rxx32+=vraddub(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vraddub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vraddubacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_A2_vraddub_acc(rxx, rss, rtt) +} + +/// `Rdd32=vrsadub(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrsadub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrsadub_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vrsadub(rss, rtt) +} + +/// `Rxx32+=vrsadub(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrsadub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrsadubacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_A2_vrsadub_acc(rxx, rss, rtt) +} + +/// `Rdd32=vsubb(Rss32,Rtt32)` +/// +/// Instruction Type: MAPPING +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsubb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsubb_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vsubb_map(rss, rtt) +} + +/// `Rdd32=vsubh(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsubh_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vsubh(rtt, rss) +} + +/// `Rdd32=vsubh(Rtt32,Rss32):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsubh_PP_sat(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vsubhs(rtt, rss) +} + +/// `Rdd32=vsubub(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsubub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsubub_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vsubub(rtt, rss) +} + +/// `Rdd32=vsubub(Rtt32,Rss32):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsubub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsubub_PP_sat(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vsububs(rtt, rss) +} + +/// `Rdd32=vsubuh(Rtt32,Rss32):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsubuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsubuh_PP_sat(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vsubuhs(rtt, rss) +} + +/// `Rdd32=vsubw(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsubw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsubw_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vsubw(rtt, rss) +} + +/// `Rdd32=vsubw(Rtt32,Rss32):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsubw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsubw_PP_sat(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vsubws(rtt, rss) +} + +/// `Rd32=xor(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(xor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_xor_RR(rs: i32, rt: i32) -> i32 { + hexagon_A2_xor(rs, rt) +} + +/// `Rdd32=xor(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(xor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_xor_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_xorp(rss, rtt) +} + +/// `Rd32=zxtb(Rs32)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(zxtb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_zxtb_R(rs: i32) -> i32 { + hexagon_A2_zxtb(rs) +} + +/// `Rd32=zxth(Rs32)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(zxth))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_zxth_R(rs: i32) -> i32 { + hexagon_A2_zxth(rs) +} + +/// `Rd32=and(Rt32,~Rs32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_and_RnR(rt: i32, rs: i32) -> i32 { + hexagon_A4_andn(rt, rs) +} + +/// `Rdd32=and(Rtt32,~Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_and_PnP(rtt: i64, rss: i64) -> i64 { + hexagon_A4_andnp(rtt, rss) +} + +/// `Rdd32=bitsplit(Rs32,Rt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(bitsplit))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_bitsplit_RR(rs: i32, rt: i32) -> i64 { + hexagon_A4_bitsplit(rs, rt) +} + +/// `Rdd32=bitsplit(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(bitsplit, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_bitsplit_RI(rs: i32) -> i64 { + static_assert_uimm_bits!(IU5, 5); + hexagon_A4_bitspliti(rs, IU5 as i32) +} + +/// `Pd4=boundscheck(Rs32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(boundscheck))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_boundscheck_RP(rs: i32, rtt: i64) -> i32 { + hexagon_A4_boundscheck(rs, rtt) +} + +/// `Pd4=cmpb.eq(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmpb_eq_RR(rs: i32, rt: i32) -> i32 { + hexagon_A4_cmpbeq(rs, rt) +} + +/// `Pd4=cmpb.eq(Rs32,#u8)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmpb, IU8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmpb_eq_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + hexagon_A4_cmpbeqi(rs, IU8 as i32) +} + +/// `Pd4=cmpb.gt(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmpb_gt_RR(rs: i32, rt: i32) -> i32 { + hexagon_A4_cmpbgt(rs, rt) +} + +/// `Pd4=cmpb.gt(Rs32,#s8)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmpb, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmpb_gt_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_cmpbgti(rs, IS8) +} + +/// `Pd4=cmpb.gtu(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmpb_gtu_RR(rs: i32, rt: i32) -> i32 { + hexagon_A4_cmpbgtu(rs, rt) +} + +/// `Pd4=cmpb.gtu(Rs32,#u7)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmpb, IU7 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmpb_gtu_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU7, 7); + hexagon_A4_cmpbgtui(rs, IU7 as i32) +} + +/// `Pd4=cmph.eq(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmph))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmph_eq_RR(rs: i32, rt: i32) -> i32 { + hexagon_A4_cmpheq(rs, rt) +} + +/// `Pd4=cmph.eq(Rs32,#s8)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmph, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmph_eq_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_cmpheqi(rs, IS8) +} + +/// `Pd4=cmph.gt(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmph))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmph_gt_RR(rs: i32, rt: i32) -> i32 { + hexagon_A4_cmphgt(rs, rt) +} + +/// `Pd4=cmph.gt(Rs32,#s8)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmph, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmph_gt_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_cmphgti(rs, IS8) +} + +/// `Pd4=cmph.gtu(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmph))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmph_gtu_RR(rs: i32, rt: i32) -> i32 { + hexagon_A4_cmphgtu(rs, rt) +} + +/// `Pd4=cmph.gtu(Rs32,#u7)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmph, IU7 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmph_gtu_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU7, 7); + hexagon_A4_cmphgtui(rs, IU7 as i32) +} + +/// `Rdd32=combine(#s8,Rs32)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(0)] +#[cfg_attr(test, assert_instr(combine, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_combine_IR(rs: i32) -> i64 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_combineir(IS8, rs) +} + +/// `Rdd32=combine(Rs32,#s8)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(combine, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_combine_RI(rs: i32) -> i64 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_combineri(rs, IS8) +} + +/// `Rd32=cround(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cround, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cround_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_A4_cround_ri(rs, IU5 as i32) +} + +/// `Rd32=cround(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cround))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cround_RR(rs: i32, rt: i32) -> i32 { + hexagon_A4_cround_rr(rs, rt) +} + +/// `Rd32=modwrap(Rs32,Rt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(modwrap))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_modwrap_RR(rs: i32, rt: i32) -> i32 { + hexagon_A4_modwrapu(rs, rt) +} + +/// `Rd32=or(Rt32,~Rs32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_or_RnR(rt: i32, rs: i32) -> i32 { + hexagon_A4_orn(rt, rs) +} + +/// `Rdd32=or(Rtt32,~Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_or_PnP(rtt: i64, rss: i64) -> i64 { + hexagon_A4_ornp(rtt, rss) +} + +/// `Rd32=cmp.eq(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmp_eq_RR(rs: i32, rt: i32) -> i32 { + hexagon_A4_rcmpeq(rs, rt) +} + +/// `Rd32=cmp.eq(Rs32,#s8)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmp, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmp_eq_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_rcmpeqi(rs, IS8) +} + +/// `Rd32=!cmp.eq(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_not_cmp_eq_RR(rs: i32, rt: i32) -> i32 { + hexagon_A4_rcmpneq(rs, rt) +} + +/// `Rd32=!cmp.eq(Rs32,#s8)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_not_cmp_eq_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_rcmpneqi(rs, IS8) +} + +/// `Rd32=round(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(round, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_round_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_A4_round_ri(rs, IU5 as i32) +} + +/// `Rd32=round(Rs32,#u5):sat` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(round, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_round_RI_sat(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_A4_round_ri_sat(rs, IU5 as i32) +} + +/// `Rd32=round(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(round))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_round_RR(rs: i32, rt: i32) -> i32 { + hexagon_A4_round_rr(rs, rt) +} + +/// `Rd32=round(Rs32,Rt32):sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(round))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_round_RR_sat(rs: i32, rt: i32) -> i32 { + hexagon_A4_round_rr_sat(rs, rt) +} + +/// `Pd4=tlbmatch(Rss32,Rt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(tlbmatch))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_tlbmatch_PR(rss: i64, rt: i32) -> i32 { + hexagon_A4_tlbmatch(rss, rt) +} + +/// `Pd4=any8(vcmpb.eq(Rss32,Rtt32))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(any8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_any8_vcmpb_eq_PP(rss: i64, rtt: i64) -> i32 { + hexagon_A4_vcmpbeq_any(rss, rtt) +} + +/// `Pd4=vcmpb.eq(Rss32,#u8)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vcmpb, IU8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpb_eq_PI(rss: i64) -> i32 { + static_assert_uimm_bits!(IU8, 8); + hexagon_A4_vcmpbeqi(rss, IU8 as i32) +} + +/// `Pd4=vcmpb.gt(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpb_gt_PP(rss: i64, rtt: i64) -> i32 { + hexagon_A4_vcmpbgt(rss, rtt) +} + +/// `Pd4=vcmpb.gt(Rss32,#s8)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vcmpb, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpb_gt_PI(rss: i64) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_vcmpbgti(rss, IS8) +} + +/// `Pd4=vcmpb.gtu(Rss32,#u7)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vcmpb, IU7 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpb_gtu_PI(rss: i64) -> i32 { + static_assert_uimm_bits!(IU7, 7); + hexagon_A4_vcmpbgtui(rss, IU7 as i32) +} + +/// `Pd4=vcmph.eq(Rss32,#s8)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vcmph, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmph_eq_PI(rss: i64) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_vcmpheqi(rss, IS8) +} + +/// `Pd4=vcmph.gt(Rss32,#s8)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vcmph, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmph_gt_PI(rss: i64) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_vcmphgti(rss, IS8) +} + +/// `Pd4=vcmph.gtu(Rss32,#u7)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vcmph, IU7 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmph_gtu_PI(rss: i64) -> i32 { + static_assert_uimm_bits!(IU7, 7); + hexagon_A4_vcmphgtui(rss, IU7 as i32) +} + +/// `Pd4=vcmpw.eq(Rss32,#s8)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vcmpw, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpw_eq_PI(rss: i64) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_vcmpweqi(rss, IS8) +} + +/// `Pd4=vcmpw.gt(Rss32,#s8)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vcmpw, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpw_gt_PI(rss: i64) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_vcmpwgti(rss, IS8) +} + +/// `Pd4=vcmpw.gtu(Rss32,#u7)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vcmpw, IU7 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpw_gtu_PI(rss: i64) -> i32 { + static_assert_uimm_bits!(IU7, 7); + hexagon_A4_vcmpwgtui(rss, IU7 as i32) +} + +/// `Rxx32=vrmaxh(Rss32,Ru32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmaxh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmaxh_PR(rxx: i64, rss: i64, ru: i32) -> i64 { + hexagon_A4_vrmaxh(rxx, rss, ru) +} + +/// `Rxx32=vrmaxuh(Rss32,Ru32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmaxuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmaxuh_PR(rxx: i64, rss: i64, ru: i32) -> i64 { + hexagon_A4_vrmaxuh(rxx, rss, ru) +} + +/// `Rxx32=vrmaxuw(Rss32,Ru32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmaxuw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmaxuw_PR(rxx: i64, rss: i64, ru: i32) -> i64 { + hexagon_A4_vrmaxuw(rxx, rss, ru) +} + +/// `Rxx32=vrmaxw(Rss32,Ru32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmaxw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmaxw_PR(rxx: i64, rss: i64, ru: i32) -> i64 { + hexagon_A4_vrmaxw(rxx, rss, ru) +} + +/// `Rxx32=vrminh(Rss32,Ru32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrminh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrminh_PR(rxx: i64, rss: i64, ru: i32) -> i64 { + hexagon_A4_vrminh(rxx, rss, ru) +} + +/// `Rxx32=vrminuh(Rss32,Ru32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrminuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrminuh_PR(rxx: i64, rss: i64, ru: i32) -> i64 { + hexagon_A4_vrminuh(rxx, rss, ru) +} + +/// `Rxx32=vrminuw(Rss32,Ru32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrminuw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrminuw_PR(rxx: i64, rss: i64, ru: i32) -> i64 { + hexagon_A4_vrminuw(rxx, rss, ru) +} + +/// `Rxx32=vrminw(Rss32,Ru32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrminw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrminw_PR(rxx: i64, rss: i64, ru: i32) -> i64 { + hexagon_A4_vrminw(rxx, rss, ru) +} + +/// `Rd32=vaddhub(Rss32,Rtt32):sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaddhub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vaddhub_PP_sat(rss: i64, rtt: i64) -> i32 { + hexagon_A5_vaddhubs(rss, rtt) +} + +/// `Pd4=all8(Ps4)` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(all8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_all8_p(ps: i32) -> i32 { + hexagon_C2_all8(ps) +} + +/// `Pd4=and(Pt4,Ps4)` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_and_pp(pt: i32, ps: i32) -> i32 { + hexagon_C2_and(pt, ps) +} + +/// `Pd4=and(Pt4,!Ps4)` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_and_pnp(pt: i32, ps: i32) -> i32 { + hexagon_C2_andn(pt, ps) +} + +/// `Pd4=any8(Ps4)` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(any8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_any8_p(ps: i32) -> i32 { + hexagon_C2_any8(ps) +} + +/// `Pd4=bitsclr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(bitsclr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_bitsclr_RR(rs: i32, rt: i32) -> i32 { + hexagon_C2_bitsclr(rs, rt) +} + +/// `Pd4=bitsclr(Rs32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(bitsclr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_bitsclr_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU6, 6); + hexagon_C2_bitsclri(rs, IU6 as i32) +} + +/// `Pd4=bitsset(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(bitsset))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_bitsset_RR(rs: i32, rt: i32) -> i32 { + hexagon_C2_bitsset(rs, rt) +} + +/// `Pd4=cmp.eq(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_eq_RR(rs: i32, rt: i32) -> i32 { + hexagon_C2_cmpeq(rs, rt) +} + +/// `Pd4=cmp.eq(Rs32,#s10)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmp, IS10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_eq_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS10, 10); + hexagon_C2_cmpeqi(rs, IS10) +} + +/// `Pd4=cmp.eq(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_eq_PP(rss: i64, rtt: i64) -> i32 { + hexagon_C2_cmpeqp(rss, rtt) +} + +/// `Pd4=cmp.ge(Rs32,#s8)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmp, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_ge_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_C2_cmpgei(rs, IS8) +} + +/// `Pd4=cmp.geu(Rs32,#u8)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmp, IU8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_geu_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + hexagon_C2_cmpgeui(rs, IU8 as i32) +} + +/// `Pd4=cmp.gt(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_gt_RR(rs: i32, rt: i32) -> i32 { + hexagon_C2_cmpgt(rs, rt) +} + +/// `Pd4=cmp.gt(Rs32,#s10)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmp, IS10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_gt_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS10, 10); + hexagon_C2_cmpgti(rs, IS10) +} + +/// `Pd4=cmp.gt(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_gt_PP(rss: i64, rtt: i64) -> i32 { + hexagon_C2_cmpgtp(rss, rtt) +} + +/// `Pd4=cmp.gtu(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_gtu_RR(rs: i32, rt: i32) -> i32 { + hexagon_C2_cmpgtu(rs, rt) +} + +/// `Pd4=cmp.gtu(Rs32,#u9)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmp, IU9 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_gtu_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU9, 9); + hexagon_C2_cmpgtui(rs, IU9 as i32) +} + +/// `Pd4=cmp.gtu(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_gtu_PP(rss: i64, rtt: i64) -> i32 { + hexagon_C2_cmpgtup(rss, rtt) +} + +/// `Pd4=cmp.lt(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_lt_RR(rs: i32, rt: i32) -> i32 { + hexagon_C2_cmplt(rs, rt) +} + +/// `Pd4=cmp.ltu(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_ltu_RR(rs: i32, rt: i32) -> i32 { + hexagon_C2_cmpltu(rs, rt) +} + +/// `Rdd32=mask(Pt4)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mask))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mask_p(pt: i32) -> i64 { + hexagon_C2_mask(pt) +} + +/// `Rd32=mux(Pu4,Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(mux))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mux_pRR(pu: i32, rs: i32, rt: i32) -> i32 { + hexagon_C2_mux(pu, rs, rt) +} + +/// `Rd32=mux(Pu4,#s8,#S8)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1, 2)] +#[cfg_attr(test, assert_instr(mux, IS8 = 0, IS8_2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mux_pII(pu: i32) -> i32 { + static_assert_simm_bits!(IS8, 8); + static_assert_simm_bits!(IS8_2, 8); + hexagon_C2_muxii(pu, IS8, IS8_2) +} + +/// `Rd32=mux(Pu4,Rs32,#s8)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(mux, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mux_pRI(pu: i32, rs: i32) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_C2_muxir(pu, rs, IS8) +} + +/// `Rd32=mux(Pu4,#s8,Rs32)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(mux, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mux_pIR(pu: i32, rs: i32) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_C2_muxri(pu, IS8, rs) +} + +/// `Pd4=not(Ps4)` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(not))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_p(ps: i32) -> i32 { + hexagon_C2_not(ps) +} + +/// `Pd4=or(Pt4,Ps4)` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_or_pp(pt: i32, ps: i32) -> i32 { + hexagon_C2_or(pt, ps) +} + +/// `Pd4=or(Pt4,!Ps4)` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_or_pnp(pt: i32, ps: i32) -> i32 { + hexagon_C2_orn(pt, ps) +} + +/// `Pd4=Ps4` +/// +/// Instruction Type: MAPPING +/// Execution Slots: SLOT0123 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_equals_p(ps: i32) -> i32 { + hexagon_C2_pxfer_map(ps) +} + +/// `Rd32=Ps4` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_equals_p(ps: i32) -> i32 { + hexagon_C2_tfrpr(ps) +} + +/// `Pd4=Rs32` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_equals_R(rs: i32) -> i32 { + hexagon_C2_tfrrp(rs) +} + +/// `Rd32=vitpack(Ps4,Pt4)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vitpack))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vitpack_pp(ps: i32, pt: i32) -> i32 { + hexagon_C2_vitpack(ps, pt) +} + +/// `Rdd32=vmux(Pu4,Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmux))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmux_pPP(pu: i32, rss: i64, rtt: i64) -> i64 { + hexagon_C2_vmux(pu, rss, rtt) +} + +/// `Pd4=xor(Ps4,Pt4)` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(xor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_xor_pp(ps: i32, pt: i32) -> i32 { + hexagon_C2_xor(ps, pt) +} + +/// `Pd4=and(Ps4,and(Pt4,Pu4))` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_and_and_ppp(ps: i32, pt: i32, pu: i32) -> i32 { + hexagon_C4_and_and(ps, pt, pu) +} + +/// `Pd4=and(Ps4,and(Pt4,!Pu4))` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_and_and_ppnp(ps: i32, pt: i32, pu: i32) -> i32 { + hexagon_C4_and_andn(ps, pt, pu) +} + +/// `Pd4=and(Ps4,or(Pt4,Pu4))` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_and_or_ppp(ps: i32, pt: i32, pu: i32) -> i32 { + hexagon_C4_and_or(ps, pt, pu) +} + +/// `Pd4=and(Ps4,or(Pt4,!Pu4))` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_and_or_ppnp(ps: i32, pt: i32, pu: i32) -> i32 { + hexagon_C4_and_orn(ps, pt, pu) +} + +/// `Pd4=!cmp.gt(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_cmp_gt_RR(rs: i32, rt: i32) -> i32 { + hexagon_C4_cmplte(rs, rt) +} + +/// `Pd4=!cmp.gt(Rs32,#s10)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_cmp_gt_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS10, 10); + hexagon_C4_cmpltei(rs, IS10) +} + +/// `Pd4=!cmp.gtu(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_cmp_gtu_RR(rs: i32, rt: i32) -> i32 { + hexagon_C4_cmplteu(rs, rt) +} + +/// `Pd4=!cmp.gtu(Rs32,#u9)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_cmp_gtu_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU9, 9); + hexagon_C4_cmplteui(rs, IU9 as i32) +} + +/// `Pd4=!cmp.eq(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_cmp_eq_RR(rs: i32, rt: i32) -> i32 { + hexagon_C4_cmpneq(rs, rt) +} + +/// `Pd4=!cmp.eq(Rs32,#s10)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_cmp_eq_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS10, 10); + hexagon_C4_cmpneqi(rs, IS10) +} + +/// `Pd4=fastcorner9(Ps4,Pt4)` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(fastcorner9))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_fastcorner9_pp(ps: i32, pt: i32) -> i32 { + hexagon_C4_fastcorner9(ps, pt) +} + +/// `Pd4=!fastcorner9(Ps4,Pt4)` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_fastcorner9_pp(ps: i32, pt: i32) -> i32 { + hexagon_C4_fastcorner9_not(ps, pt) +} + +/// `Pd4=!bitsclr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_bitsclr_RR(rs: i32, rt: i32) -> i32 { + hexagon_C4_nbitsclr(rs, rt) +} + +/// `Pd4=!bitsclr(Rs32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_bitsclr_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU6, 6); + hexagon_C4_nbitsclri(rs, IU6 as i32) +} + +/// `Pd4=!bitsset(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_bitsset_RR(rs: i32, rt: i32) -> i32 { + hexagon_C4_nbitsset(rs, rt) +} + +/// `Pd4=or(Ps4,and(Pt4,Pu4))` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_or_and_ppp(ps: i32, pt: i32, pu: i32) -> i32 { + hexagon_C4_or_and(ps, pt, pu) +} + +/// `Pd4=or(Ps4,and(Pt4,!Pu4))` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_or_and_ppnp(ps: i32, pt: i32, pu: i32) -> i32 { + hexagon_C4_or_andn(ps, pt, pu) +} + +/// `Pd4=or(Ps4,or(Pt4,Pu4))` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_or_or_ppp(ps: i32, pt: i32, pu: i32) -> i32 { + hexagon_C4_or_or(ps, pt, pu) +} + +/// `Pd4=or(Ps4,or(Pt4,!Pu4))` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_or_or_ppnp(ps: i32, pt: i32, pu: i32) -> i32 { + hexagon_C4_or_orn(ps, pt, pu) +} + +/// `Rdd32=convert_d2df(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_d2df))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_d2df_P(rss: i64) -> f64 { + hexagon_F2_conv_d2df(rss) +} + +/// `Rd32=convert_d2sf(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_d2sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_d2sf_P(rss: i64) -> f32 { + hexagon_F2_conv_d2sf(rss) +} + +/// `Rdd32=convert_df2d(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_df2d))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_df2d_P(rss: f64) -> i64 { + hexagon_F2_conv_df2d(rss) +} + +/// `Rdd32=convert_df2d(Rss32):chop` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_df2d))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_df2d_P_chop(rss: f64) -> i64 { + hexagon_F2_conv_df2d_chop(rss) +} + +/// `Rd32=convert_df2sf(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_df2sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_df2sf_P(rss: f64) -> f32 { + hexagon_F2_conv_df2sf(rss) +} + +/// `Rdd32=convert_df2ud(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_df2ud))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_df2ud_P(rss: f64) -> i64 { + hexagon_F2_conv_df2ud(rss) +} + +/// `Rdd32=convert_df2ud(Rss32):chop` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_df2ud))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_df2ud_P_chop(rss: f64) -> i64 { + hexagon_F2_conv_df2ud_chop(rss) +} + +/// `Rd32=convert_df2uw(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_df2uw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_df2uw_P(rss: f64) -> i32 { + hexagon_F2_conv_df2uw(rss) +} + +/// `Rd32=convert_df2uw(Rss32):chop` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_df2uw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_df2uw_P_chop(rss: f64) -> i32 { + hexagon_F2_conv_df2uw_chop(rss) +} + +/// `Rd32=convert_df2w(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_df2w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_df2w_P(rss: f64) -> i32 { + hexagon_F2_conv_df2w(rss) +} + +/// `Rd32=convert_df2w(Rss32):chop` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_df2w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_df2w_P_chop(rss: f64) -> i32 { + hexagon_F2_conv_df2w_chop(rss) +} + +/// `Rdd32=convert_sf2d(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_sf2d))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_sf2d_R(rs: f32) -> i64 { + hexagon_F2_conv_sf2d(rs) +} + +/// `Rdd32=convert_sf2d(Rs32):chop` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_sf2d))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_sf2d_R_chop(rs: f32) -> i64 { + hexagon_F2_conv_sf2d_chop(rs) +} + +/// `Rdd32=convert_sf2df(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_sf2df))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_sf2df_R(rs: f32) -> f64 { + hexagon_F2_conv_sf2df(rs) +} + +/// `Rdd32=convert_sf2ud(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_sf2ud))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_sf2ud_R(rs: f32) -> i64 { + hexagon_F2_conv_sf2ud(rs) +} + +/// `Rdd32=convert_sf2ud(Rs32):chop` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_sf2ud))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_sf2ud_R_chop(rs: f32) -> i64 { + hexagon_F2_conv_sf2ud_chop(rs) +} + +/// `Rd32=convert_sf2uw(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_sf2uw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_sf2uw_R(rs: f32) -> i32 { + hexagon_F2_conv_sf2uw(rs) +} + +/// `Rd32=convert_sf2uw(Rs32):chop` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_sf2uw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_sf2uw_R_chop(rs: f32) -> i32 { + hexagon_F2_conv_sf2uw_chop(rs) +} + +/// `Rd32=convert_sf2w(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_sf2w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_sf2w_R(rs: f32) -> i32 { + hexagon_F2_conv_sf2w(rs) +} + +/// `Rd32=convert_sf2w(Rs32):chop` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_sf2w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_sf2w_R_chop(rs: f32) -> i32 { + hexagon_F2_conv_sf2w_chop(rs) +} + +/// `Rdd32=convert_ud2df(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_ud2df))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_ud2df_P(rss: i64) -> f64 { + hexagon_F2_conv_ud2df(rss) +} + +/// `Rd32=convert_ud2sf(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_ud2sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_ud2sf_P(rss: i64) -> f32 { + hexagon_F2_conv_ud2sf(rss) +} + +/// `Rdd32=convert_uw2df(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_uw2df))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_uw2df_R(rs: i32) -> f64 { + hexagon_F2_conv_uw2df(rs) +} + +/// `Rd32=convert_uw2sf(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_uw2sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_uw2sf_R(rs: i32) -> f32 { + hexagon_F2_conv_uw2sf(rs) +} + +/// `Rdd32=convert_w2df(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_w2df))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_w2df_R(rs: i32) -> f64 { + hexagon_F2_conv_w2df(rs) +} + +/// `Rd32=convert_w2sf(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_w2sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_w2sf_R(rs: i32) -> f32 { + hexagon_F2_conv_w2sf(rs) +} + +/// `Pd4=dfclass(Rss32,#u5)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(dfclass, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_dfclass_PI(rss: f64) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_F2_dfclass(rss, IU5 as i32) +} + +/// `Pd4=dfcmp.eq(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(dfcmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_dfcmp_eq_PP(rss: f64, rtt: f64) -> i32 { + hexagon_F2_dfcmpeq(rss, rtt) +} + +/// `Pd4=dfcmp.ge(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(dfcmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_dfcmp_ge_PP(rss: f64, rtt: f64) -> i32 { + hexagon_F2_dfcmpge(rss, rtt) +} + +/// `Pd4=dfcmp.gt(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(dfcmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_dfcmp_gt_PP(rss: f64, rtt: f64) -> i32 { + hexagon_F2_dfcmpgt(rss, rtt) +} + +/// `Pd4=dfcmp.uo(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(dfcmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_dfcmp_uo_PP(rss: f64, rtt: f64) -> i32 { + hexagon_F2_dfcmpuo(rss, rtt) +} + +/// `Rdd32=dfmake(#u10):neg` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0)] +#[cfg_attr(test, assert_instr(dfmake, IU10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_dfmake_I_neg() -> f64 { + static_assert_uimm_bits!(IU10, 10); + hexagon_F2_dfimm_n(IU10 as i32) +} + +/// `Rdd32=dfmake(#u10):pos` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0)] +#[cfg_attr(test, assert_instr(dfmake, IU10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_dfmake_I_pos() -> f64 { + static_assert_uimm_bits!(IU10, 10); + hexagon_F2_dfimm_p(IU10 as i32) +} + +/// `Rd32=sfadd(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfadd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfadd_RR(rs: f32, rt: f32) -> f32 { + hexagon_F2_sfadd(rs, rt) +} + +/// `Pd4=sfclass(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(sfclass, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_sfclass_RI(rs: f32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_F2_sfclass(rs, IU5 as i32) +} + +/// `Pd4=sfcmp.eq(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfcmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_sfcmp_eq_RR(rs: f32, rt: f32) -> i32 { + hexagon_F2_sfcmpeq(rs, rt) +} + +/// `Pd4=sfcmp.ge(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfcmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_sfcmp_ge_RR(rs: f32, rt: f32) -> i32 { + hexagon_F2_sfcmpge(rs, rt) +} + +/// `Pd4=sfcmp.gt(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfcmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_sfcmp_gt_RR(rs: f32, rt: f32) -> i32 { + hexagon_F2_sfcmpgt(rs, rt) +} + +/// `Pd4=sfcmp.uo(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfcmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_sfcmp_uo_RR(rs: f32, rt: f32) -> i32 { + hexagon_F2_sfcmpuo(rs, rt) +} + +/// `Rd32=sffixupd(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sffixupd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sffixupd_RR(rs: f32, rt: f32) -> f32 { + hexagon_F2_sffixupd(rs, rt) +} + +/// `Rd32=sffixupn(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sffixupn))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sffixupn_RR(rs: f32, rt: f32) -> f32 { + hexagon_F2_sffixupn(rs, rt) +} + +/// `Rd32=sffixupr(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sffixupr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sffixupr_R(rs: f32) -> f32 { + hexagon_F2_sffixupr(rs) +} + +/// `Rx32+=sfmpy(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfmpyacc_RR(rx: f32, rs: f32, rt: f32) -> f32 { + hexagon_F2_sffma(rx, rs, rt) +} + +/// `Rx32+=sfmpy(Rs32,Rt32):lib` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfmpyacc_RR_lib(rx: f32, rs: f32, rt: f32) -> f32 { + hexagon_F2_sffma_lib(rx, rs, rt) +} + +/// `Rx32+=sfmpy(Rs32,Rt32,Pu4):scale` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfmpyacc_RRp_scale(rx: f32, rs: f32, rt: f32, pu: i32) -> f32 { + hexagon_F2_sffma_sc(rx, rs, rt, pu) +} + +/// `Rx32-=sfmpy(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfmpynac_RR(rx: f32, rs: f32, rt: f32) -> f32 { + hexagon_F2_sffms(rx, rs, rt) +} + +/// `Rx32-=sfmpy(Rs32,Rt32):lib` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfmpynac_RR_lib(rx: f32, rs: f32, rt: f32) -> f32 { + hexagon_F2_sffms_lib(rx, rs, rt) +} + +/// `Rd32=sfmake(#u10):neg` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0)] +#[cfg_attr(test, assert_instr(sfmake, IU10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfmake_I_neg() -> f32 { + static_assert_uimm_bits!(IU10, 10); + hexagon_F2_sfimm_n(IU10 as i32) +} + +/// `Rd32=sfmake(#u10):pos` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0)] +#[cfg_attr(test, assert_instr(sfmake, IU10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfmake_I_pos() -> f32 { + static_assert_uimm_bits!(IU10, 10); + hexagon_F2_sfimm_p(IU10 as i32) +} + +/// `Rd32=sfmax(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfmax))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfmax_RR(rs: f32, rt: f32) -> f32 { + hexagon_F2_sfmax(rs, rt) +} + +/// `Rd32=sfmin(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfmin))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfmin_RR(rs: f32, rt: f32) -> f32 { + hexagon_F2_sfmin(rs, rt) +} + +/// `Rd32=sfmpy(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfmpy_RR(rs: f32, rt: f32) -> f32 { + hexagon_F2_sfmpy(rs, rt) +} + +/// `Rd32=sfsub(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfsub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfsub_RR(rs: f32, rt: f32) -> f32 { + hexagon_F2_sfsub(rs, rt) +} + +/// `Rx32+=add(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_addacc_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_acci(rx, rs, rt) +} + +/// `Rx32+=add(Rs32,#s8)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(add, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_addacc_RI(rx: i32, rs: i32) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_M2_accii(rx, rs, IS8) +} + +/// `Rxx32+=cmpyi(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyiacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_cmaci_s0(rxx, rs, rt) +} + +/// `Rxx32+=cmpyr(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpyr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyracc_RR(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_cmacr_s0(rxx, rs, rt) +} + +/// `Rxx32+=cmpy(Rs32,Rt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyacc_RR_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_cmacs_s0(rxx, rs, rt) +} + +/// `Rxx32+=cmpy(Rs32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyacc_RR_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_cmacs_s1(rxx, rs, rt) +} + +/// `Rxx32+=cmpy(Rs32,Rt32*):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyacc_RR_conj_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_cmacsc_s0(rxx, rs, rt) +} + +/// `Rxx32+=cmpy(Rs32,Rt32*):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyacc_RR_conj_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_cmacsc_s1(rxx, rs, rt) +} + +/// `Rdd32=cmpyi(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyi_RR(rs: i32, rt: i32) -> i64 { + hexagon_M2_cmpyi_s0(rs, rt) +} + +/// `Rdd32=cmpyr(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpyr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyr_RR(rs: i32, rt: i32) -> i64 { + hexagon_M2_cmpyr_s0(rs, rt) +} + +/// `Rd32=cmpy(Rs32,Rt32):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpy_RR_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_cmpyrs_s0(rs, rt) +} + +/// `Rd32=cmpy(Rs32,Rt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpy_RR_s1_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_cmpyrs_s1(rs, rt) +} + +/// `Rd32=cmpy(Rs32,Rt32*):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpy_RR_conj_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_cmpyrsc_s0(rs, rt) +} + +/// `Rd32=cmpy(Rs32,Rt32*):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpy_RR_conj_s1_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_cmpyrsc_s1(rs, rt) +} + +/// `Rdd32=cmpy(Rs32,Rt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpy_RR_sat(rs: i32, rt: i32) -> i64 { + hexagon_M2_cmpys_s0(rs, rt) +} + +/// `Rdd32=cmpy(Rs32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpy_RR_s1_sat(rs: i32, rt: i32) -> i64 { + hexagon_M2_cmpys_s1(rs, rt) +} + +/// `Rdd32=cmpy(Rs32,Rt32*):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpy_RR_conj_sat(rs: i32, rt: i32) -> i64 { + hexagon_M2_cmpysc_s0(rs, rt) +} + +/// `Rdd32=cmpy(Rs32,Rt32*):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpy_RR_conj_s1_sat(rs: i32, rt: i32) -> i64 { + hexagon_M2_cmpysc_s1(rs, rt) +} + +/// `Rxx32-=cmpy(Rs32,Rt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpynac_RR_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_cnacs_s0(rxx, rs, rt) +} + +/// `Rxx32-=cmpy(Rs32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpynac_RR_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_cnacs_s1(rxx, rs, rt) +} + +/// `Rxx32-=cmpy(Rs32,Rt32*):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpynac_RR_conj_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_cnacsc_s0(rxx, rs, rt) +} + +/// `Rxx32-=cmpy(Rs32,Rt32*):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpynac_RR_conj_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_cnacsc_s1(rxx, rs, rt) +} + +/// `Rxx32+=mpy(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_dpmpyss_acc_s0(rxx, rs, rt) +} + +/// `Rxx32-=mpy(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpynac_RR(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_dpmpyss_nac_s0(rxx, rs, rt) +} + +/// `Rd32=mpy(Rs32,Rt32):rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RR_rnd(rs: i32, rt: i32) -> i32 { + hexagon_M2_dpmpyss_rnd_s0(rs, rt) +} + +/// `Rdd32=mpy(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RR(rs: i32, rt: i32) -> i64 { + hexagon_M2_dpmpyss_s0(rs, rt) +} + +/// `Rxx32+=mpyu(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyuacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_dpmpyuu_acc_s0(rxx, rs, rt) +} + +/// `Rxx32-=mpyu(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyunac_RR(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_dpmpyuu_nac_s0(rxx, rs, rt) +} + +/// `Rdd32=mpyu(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyu_RR(rs: i32, rt: i32) -> i64 { + hexagon_M2_dpmpyuu_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32,Rt32.h):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RRh_s1_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_hmmpyh_rs1(rs, rt) +} + +/// `Rd32=mpy(Rs32,Rt32.h):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RRh_s1_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_hmmpyh_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32,Rt32.l):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RRl_s1_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_hmmpyl_rs1(rs, rt) +} + +/// `Rd32=mpy(Rs32,Rt32.l):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RRl_s1_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_hmmpyl_s1(rs, rt) +} + +/// `Rx32+=mpyi(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyiacc_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_maci(rx, rs, rt) +} + +/// `Rx32-=mpyi(Rs32,#u8)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(mpyi, IU8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyinac_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + hexagon_M2_macsin(rx, rs, IU8 as i32) +} + +/// `Rx32+=mpyi(Rs32,#u8)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(mpyi, IU8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyiacc_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + hexagon_M2_macsip(rx, rs, IU8 as i32) +} + +/// `Rxx32+=vmpywoh(Rss32,Rtt32):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywohacc_PP_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmachs_rs0(rxx, rss, rtt) +} + +/// `Rxx32+=vmpywoh(Rss32,Rtt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywohacc_PP_s1_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmachs_rs1(rxx, rss, rtt) +} + +/// `Rxx32+=vmpywoh(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywohacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmachs_s0(rxx, rss, rtt) +} + +/// `Rxx32+=vmpywoh(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywohacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmachs_s1(rxx, rss, rtt) +} + +/// `Rxx32+=vmpyweh(Rss32,Rtt32):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywehacc_PP_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmacls_rs0(rxx, rss, rtt) +} + +/// `Rxx32+=vmpyweh(Rss32,Rtt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywehacc_PP_s1_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmacls_rs1(rxx, rss, rtt) +} + +/// `Rxx32+=vmpyweh(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywehacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmacls_s0(rxx, rss, rtt) +} + +/// `Rxx32+=vmpyweh(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywehacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmacls_s1(rxx, rss, rtt) +} + +/// `Rxx32+=vmpywouh(Rss32,Rtt32):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywouh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywouhacc_PP_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmacuhs_rs0(rxx, rss, rtt) +} + +/// `Rxx32+=vmpywouh(Rss32,Rtt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywouh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywouhacc_PP_s1_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmacuhs_rs1(rxx, rss, rtt) +} + +/// `Rxx32+=vmpywouh(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywouh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywouhacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmacuhs_s0(rxx, rss, rtt) +} + +/// `Rxx32+=vmpywouh(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywouh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywouhacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmacuhs_s1(rxx, rss, rtt) +} + +/// `Rxx32+=vmpyweuh(Rss32,Rtt32):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweuhacc_PP_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmaculs_rs0(rxx, rss, rtt) +} + +/// `Rxx32+=vmpyweuh(Rss32,Rtt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweuhacc_PP_s1_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmaculs_rs1(rxx, rss, rtt) +} + +/// `Rxx32+=vmpyweuh(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweuhacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmaculs_s0(rxx, rss, rtt) +} + +/// `Rxx32+=vmpyweuh(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweuhacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmaculs_s1(rxx, rss, rtt) +} + +/// `Rdd32=vmpywoh(Rss32,Rtt32):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywoh_PP_rnd_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyh_rs0(rss, rtt) +} + +/// `Rdd32=vmpywoh(Rss32,Rtt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywoh_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyh_rs1(rss, rtt) +} + +/// `Rdd32=vmpywoh(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywoh_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyh_s0(rss, rtt) +} + +/// `Rdd32=vmpywoh(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywoh_PP_s1_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyh_s1(rss, rtt) +} + +/// `Rdd32=vmpyweh(Rss32,Rtt32):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweh_PP_rnd_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyl_rs0(rss, rtt) +} + +/// `Rdd32=vmpyweh(Rss32,Rtt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweh_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyl_rs1(rss, rtt) +} + +/// `Rdd32=vmpyweh(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweh_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyl_s0(rss, rtt) +} + +/// `Rdd32=vmpyweh(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweh_PP_s1_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyl_s1(rss, rtt) +} + +/// `Rdd32=vmpywouh(Rss32,Rtt32):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywouh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywouh_PP_rnd_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyuh_rs0(rss, rtt) +} + +/// `Rdd32=vmpywouh(Rss32,Rtt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywouh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywouh_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyuh_rs1(rss, rtt) +} + +/// `Rdd32=vmpywouh(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywouh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywouh_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyuh_s0(rss, rtt) +} + +/// `Rdd32=vmpywouh(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywouh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywouh_PP_s1_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyuh_s1(rss, rtt) +} + +/// `Rdd32=vmpyweuh(Rss32,Rtt32):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweuh_PP_rnd_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyul_rs0(rss, rtt) +} + +/// `Rdd32=vmpyweuh(Rss32,Rtt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweuh_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyul_rs1(rss, rtt) +} + +/// `Rdd32=vmpyweuh(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweuh_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyul_s0(rss, rtt) +} + +/// `Rdd32=vmpyweuh(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweuh_PP_s1_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyul_s1(rss, rtt) +} + +/// `Rx32+=mpy(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RhRh(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_hh_s0(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RhRh_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_hh_s1(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RhRl(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_hl_s0(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RhRl_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_hl_s1(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RlRh(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_lh_s0(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RlRh_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_lh_s1(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RlRl(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_ll_s0(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RlRl_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_ll_s1(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.h,Rt32.h):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RhRh_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_sat_hh_s0(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.h,Rt32.h):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RhRh_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_sat_hh_s1(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.h,Rt32.l):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RhRl_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_sat_hl_s0(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.h,Rt32.l):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RhRl_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_sat_hl_s1(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.l,Rt32.h):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RlRh_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_sat_lh_s0(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.l,Rt32.h):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RlRh_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_sat_lh_s1(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.l,Rt32.l):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RlRl_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_sat_ll_s0(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.l,Rt32.l):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RlRl_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_sat_ll_s1(rx, rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRh(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_hh_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRh_s1(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_hh_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRl(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_hl_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRl_s1(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_hl_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRh(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_lh_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRh_s1(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_lh_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRl(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_ll_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRl_s1(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_ll_s1(rs, rt) +} + +/// `Rx32-=mpy(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RhRh(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_hh_s0(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RhRh_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_hh_s1(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RhRl(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_hl_s0(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RhRl_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_hl_s1(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RlRh(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_lh_s0(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RlRh_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_lh_s1(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RlRl(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_ll_s0(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RlRl_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_ll_s1(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.h,Rt32.h):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RhRh_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_sat_hh_s0(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.h,Rt32.h):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RhRh_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_sat_hh_s1(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.h,Rt32.l):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RhRl_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_sat_hl_s0(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.h,Rt32.l):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RhRl_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_sat_hl_s1(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.l,Rt32.h):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RlRh_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_sat_lh_s0(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.l,Rt32.h):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RlRh_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_sat_lh_s1(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.l,Rt32.l):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RlRl_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_sat_ll_s0(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.l,Rt32.l):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RlRl_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_sat_ll_s1(rx, rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.h):rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRh_rnd(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_rnd_hh_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.h):<<1:rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRh_s1_rnd(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_rnd_hh_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.l):rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRl_rnd(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_rnd_hl_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.l):<<1:rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRl_s1_rnd(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_rnd_hl_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.h):rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRh_rnd(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_rnd_lh_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.h):<<1:rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRh_s1_rnd(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_rnd_lh_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.l):rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRl_rnd(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_rnd_ll_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.l):<<1:rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRl_s1_rnd(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_rnd_ll_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.h):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRh_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_hh_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.h):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRh_s1_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_hh_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.l):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRl_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_hl_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.l):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRl_s1_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_hl_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.h):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRh_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_lh_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.h):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRh_s1_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_lh_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.l):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRl_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_ll_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.l):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRl_s1_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_ll_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.h):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRh_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_rnd_hh_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.h):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRh_s1_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_rnd_hh_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.l):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRl_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_rnd_hl_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.l):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRl_s1_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_rnd_hl_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.h):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRh_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_rnd_lh_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.h):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRh_s1_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_rnd_lh_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.l):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRl_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_rnd_ll_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.l):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRl_s1_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_rnd_ll_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RR(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_up(rs, rt) +} + +/// `Rd32=mpy(Rs32,Rt32):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RR_s1(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_up_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RR_s1_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_up_s1_sat(rs, rt) +} + +/// `Rxx32+=mpy(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyacc_RhRh(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_acc_hh_s0(rxx, rs, rt) +} + +/// `Rxx32+=mpy(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyacc_RhRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_acc_hh_s1(rxx, rs, rt) +} + +/// `Rxx32+=mpy(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyacc_RhRl(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_acc_hl_s0(rxx, rs, rt) +} + +/// `Rxx32+=mpy(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyacc_RhRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_acc_hl_s1(rxx, rs, rt) +} + +/// `Rxx32+=mpy(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyacc_RlRh(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_acc_lh_s0(rxx, rs, rt) +} + +/// `Rxx32+=mpy(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyacc_RlRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_acc_lh_s1(rxx, rs, rt) +} + +/// `Rxx32+=mpy(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyacc_RlRl(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_acc_ll_s0(rxx, rs, rt) +} + +/// `Rxx32+=mpy(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyacc_RlRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_acc_ll_s1(rxx, rs, rt) +} + +/// `Rdd32=mpy(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RhRh(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_hh_s0(rs, rt) +} + +/// `Rdd32=mpy(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RhRh_s1(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_hh_s1(rs, rt) +} + +/// `Rdd32=mpy(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RhRl(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_hl_s0(rs, rt) +} + +/// `Rdd32=mpy(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RhRl_s1(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_hl_s1(rs, rt) +} + +/// `Rdd32=mpy(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RlRh(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_lh_s0(rs, rt) +} + +/// `Rdd32=mpy(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RlRh_s1(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_lh_s1(rs, rt) +} + +/// `Rdd32=mpy(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RlRl(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_ll_s0(rs, rt) +} + +/// `Rdd32=mpy(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RlRl_s1(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_ll_s1(rs, rt) +} + +/// `Rxx32-=mpy(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpynac_RhRh(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_nac_hh_s0(rxx, rs, rt) +} + +/// `Rxx32-=mpy(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpynac_RhRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_nac_hh_s1(rxx, rs, rt) +} + +/// `Rxx32-=mpy(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpynac_RhRl(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_nac_hl_s0(rxx, rs, rt) +} + +/// `Rxx32-=mpy(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpynac_RhRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_nac_hl_s1(rxx, rs, rt) +} + +/// `Rxx32-=mpy(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpynac_RlRh(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_nac_lh_s0(rxx, rs, rt) +} + +/// `Rxx32-=mpy(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpynac_RlRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_nac_lh_s1(rxx, rs, rt) +} + +/// `Rxx32-=mpy(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpynac_RlRl(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_nac_ll_s0(rxx, rs, rt) +} + +/// `Rxx32-=mpy(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpynac_RlRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_nac_ll_s1(rxx, rs, rt) +} + +/// `Rdd32=mpy(Rs32.h,Rt32.h):rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RhRh_rnd(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_rnd_hh_s0(rs, rt) +} + +/// `Rdd32=mpy(Rs32.h,Rt32.h):<<1:rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RhRh_s1_rnd(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_rnd_hh_s1(rs, rt) +} + +/// `Rdd32=mpy(Rs32.h,Rt32.l):rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RhRl_rnd(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_rnd_hl_s0(rs, rt) +} + +/// `Rdd32=mpy(Rs32.h,Rt32.l):<<1:rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RhRl_s1_rnd(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_rnd_hl_s1(rs, rt) +} + +/// `Rdd32=mpy(Rs32.l,Rt32.h):rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RlRh_rnd(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_rnd_lh_s0(rs, rt) +} + +/// `Rdd32=mpy(Rs32.l,Rt32.h):<<1:rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RlRh_s1_rnd(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_rnd_lh_s1(rs, rt) +} + +/// `Rdd32=mpy(Rs32.l,Rt32.l):rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RlRl_rnd(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_rnd_ll_s0(rs, rt) +} + +/// `Rdd32=mpy(Rs32.l,Rt32.l):<<1:rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RlRl_s1_rnd(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_rnd_ll_s1(rs, rt) +} + +/// `Rd32=mpyi(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyi_RR(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyi(rs, rt) +} + +/// `Rd32=mpyi(Rs32,#m9)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyi_RI(rs: i32, im9: i32) -> i32 { + hexagon_M2_mpysmi(rs, im9) +} + +/// `Rd32=mpysu(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpysu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpysu_RR(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpysu_up(rs, rt) +} + +/// `Rx32+=mpyu(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyuacc_RhRh(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_acc_hh_s0(rx, rs, rt) +} + +/// `Rx32+=mpyu(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyuacc_RhRh_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_acc_hh_s1(rx, rs, rt) +} + +/// `Rx32+=mpyu(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyuacc_RhRl(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_acc_hl_s0(rx, rs, rt) +} + +/// `Rx32+=mpyu(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyuacc_RhRl_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_acc_hl_s1(rx, rs, rt) +} + +/// `Rx32+=mpyu(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyuacc_RlRh(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_acc_lh_s0(rx, rs, rt) +} + +/// `Rx32+=mpyu(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyuacc_RlRh_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_acc_lh_s1(rx, rs, rt) +} + +/// `Rx32+=mpyu(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyuacc_RlRl(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_acc_ll_s0(rx, rs, rt) +} + +/// `Rx32+=mpyu(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyuacc_RlRl_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_acc_ll_s1(rx, rs, rt) +} + +/// `Rd32=mpyu(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyu_RhRh(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_hh_s0(rs, rt) +} + +/// `Rd32=mpyu(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyu_RhRh_s1(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_hh_s1(rs, rt) +} + +/// `Rd32=mpyu(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyu_RhRl(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_hl_s0(rs, rt) +} + +/// `Rd32=mpyu(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyu_RhRl_s1(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_hl_s1(rs, rt) +} + +/// `Rd32=mpyu(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyu_RlRh(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_lh_s0(rs, rt) +} + +/// `Rd32=mpyu(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyu_RlRh_s1(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_lh_s1(rs, rt) +} + +/// `Rd32=mpyu(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyu_RlRl(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_ll_s0(rs, rt) +} + +/// `Rd32=mpyu(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyu_RlRl_s1(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_ll_s1(rs, rt) +} + +/// `Rx32-=mpyu(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyunac_RhRh(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_nac_hh_s0(rx, rs, rt) +} + +/// `Rx32-=mpyu(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyunac_RhRh_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_nac_hh_s1(rx, rs, rt) +} + +/// `Rx32-=mpyu(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyunac_RhRl(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_nac_hl_s0(rx, rs, rt) +} + +/// `Rx32-=mpyu(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyunac_RhRl_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_nac_hl_s1(rx, rs, rt) +} + +/// `Rx32-=mpyu(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyunac_RlRh(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_nac_lh_s0(rx, rs, rt) +} + +/// `Rx32-=mpyu(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyunac_RlRh_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_nac_lh_s1(rx, rs, rt) +} + +/// `Rx32-=mpyu(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyunac_RlRl(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_nac_ll_s0(rx, rs, rt) +} + +/// `Rx32-=mpyu(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyunac_RlRl_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_nac_ll_s1(rx, rs, rt) +} + +/// `Rd32=mpyu(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyu_RR(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_up(rs, rt) +} + +/// `Rxx32+=mpyu(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyuacc_RhRh(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_acc_hh_s0(rxx, rs, rt) +} + +/// `Rxx32+=mpyu(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyuacc_RhRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_acc_hh_s1(rxx, rs, rt) +} + +/// `Rxx32+=mpyu(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyuacc_RhRl(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_acc_hl_s0(rxx, rs, rt) +} + +/// `Rxx32+=mpyu(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyuacc_RhRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_acc_hl_s1(rxx, rs, rt) +} + +/// `Rxx32+=mpyu(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyuacc_RlRh(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_acc_lh_s0(rxx, rs, rt) +} + +/// `Rxx32+=mpyu(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyuacc_RlRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_acc_lh_s1(rxx, rs, rt) +} + +/// `Rxx32+=mpyu(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyuacc_RlRl(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_acc_ll_s0(rxx, rs, rt) +} + +/// `Rxx32+=mpyu(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyuacc_RlRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_acc_ll_s1(rxx, rs, rt) +} + +/// `Rdd32=mpyu(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyu_RhRh(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_hh_s0(rs, rt) +} + +/// `Rdd32=mpyu(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyu_RhRh_s1(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_hh_s1(rs, rt) +} + +/// `Rdd32=mpyu(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyu_RhRl(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_hl_s0(rs, rt) +} + +/// `Rdd32=mpyu(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyu_RhRl_s1(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_hl_s1(rs, rt) +} + +/// `Rdd32=mpyu(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyu_RlRh(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_lh_s0(rs, rt) +} + +/// `Rdd32=mpyu(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyu_RlRh_s1(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_lh_s1(rs, rt) +} + +/// `Rdd32=mpyu(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyu_RlRl(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_ll_s0(rs, rt) +} + +/// `Rdd32=mpyu(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyu_RlRl_s1(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_ll_s1(rs, rt) +} + +/// `Rxx32-=mpyu(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyunac_RhRh(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_nac_hh_s0(rxx, rs, rt) +} + +/// `Rxx32-=mpyu(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyunac_RhRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_nac_hh_s1(rxx, rs, rt) +} + +/// `Rxx32-=mpyu(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyunac_RhRl(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_nac_hl_s0(rxx, rs, rt) +} + +/// `Rxx32-=mpyu(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyunac_RhRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_nac_hl_s1(rxx, rs, rt) +} + +/// `Rxx32-=mpyu(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyunac_RlRh(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_nac_lh_s0(rxx, rs, rt) +} + +/// `Rxx32-=mpyu(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyunac_RlRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_nac_lh_s1(rxx, rs, rt) +} + +/// `Rxx32-=mpyu(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyunac_RlRl(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_nac_ll_s0(rxx, rs, rt) +} + +/// `Rxx32-=mpyu(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyunac_RlRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_nac_ll_s1(rxx, rs, rt) +} + +/// `Rd32=mpyui(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyui))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyui_RR(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyui(rs, rt) +} + +/// `Rx32-=add(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_addnac_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_nacci(rx, rs, rt) +} + +/// `Rx32-=add(Rs32,#s8)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(add, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_addnac_RI(rx: i32, rs: i32) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_M2_naccii(rx, rs, IS8) +} + +/// `Rx32+=sub(Rt32,Rs32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_subacc_RR(rx: i32, rt: i32, rs: i32) -> i32 { + hexagon_M2_subacc(rx, rt, rs) +} + +/// `Rdd32=vabsdiffh(Rtt32,Rss32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vabsdiffh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vabsdiffh_PP(rtt: i64, rss: i64) -> i64 { + hexagon_M2_vabsdiffh(rtt, rss) +} + +/// `Rdd32=vabsdiffw(Rtt32,Rss32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vabsdiffw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vabsdiffw_PP(rtt: i64, rss: i64) -> i64 { + hexagon_M2_vabsdiffw(rtt, rss) +} + +/// `Rxx32+=vcmpyi(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vcmpyiacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vcmac_s0_sat_i(rxx, rss, rtt) +} + +/// `Rxx32+=vcmpyr(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpyr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vcmpyracc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vcmac_s0_sat_r(rxx, rss, rtt) +} + +/// `Rdd32=vcmpyi(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vcmpyi_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vcmpy_s0_sat_i(rss, rtt) +} + +/// `Rdd32=vcmpyr(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpyr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vcmpyr_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vcmpy_s0_sat_r(rss, rtt) +} + +/// `Rdd32=vcmpyi(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vcmpyi_PP_s1_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vcmpy_s1_sat_i(rss, rtt) +} + +/// `Rdd32=vcmpyr(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpyr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vcmpyr_PP_s1_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vcmpy_s1_sat_r(rss, rtt) +} + +/// `Rxx32+=vdmpy(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vdmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vdmpyacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vdmacs_s0(rxx, rss, rtt) +} + +/// `Rxx32+=vdmpy(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vdmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vdmpyacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vdmacs_s1(rxx, rss, rtt) +} + +/// `Rd32=vdmpy(Rss32,Rtt32):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vdmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vdmpy_PP_rnd_sat(rss: i64, rtt: i64) -> i32 { + hexagon_M2_vdmpyrs_s0(rss, rtt) +} + +/// `Rd32=vdmpy(Rss32,Rtt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vdmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vdmpy_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i32 { + hexagon_M2_vdmpyrs_s1(rss, rtt) +} + +/// `Rdd32=vdmpy(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vdmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vdmpy_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vdmpys_s0(rss, rtt) +} + +/// `Rdd32=vdmpy(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vdmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vdmpy_PP_s1_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vdmpys_s1(rss, rtt) +} + +/// `Rxx32+=vmpyh(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyhacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_vmac2(rxx, rs, rt) +} + +/// `Rxx32+=vmpyeh(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyehacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vmac2es(rxx, rss, rtt) +} + +/// `Rxx32+=vmpyeh(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyehacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vmac2es_s0(rxx, rss, rtt) +} + +/// `Rxx32+=vmpyeh(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyehacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vmac2es_s1(rxx, rss, rtt) +} + +/// `Rxx32+=vmpyh(Rs32,Rt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyhacc_RR_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_vmac2s_s0(rxx, rs, rt) +} + +/// `Rxx32+=vmpyh(Rs32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyhacc_RR_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_vmac2s_s1(rxx, rs, rt) +} + +/// `Rxx32+=vmpyhsu(Rs32,Rt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyhsu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyhsuacc_RR_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_vmac2su_s0(rxx, rs, rt) +} + +/// `Rxx32+=vmpyhsu(Rs32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyhsu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyhsuacc_RR_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_vmac2su_s1(rxx, rs, rt) +} + +/// `Rdd32=vmpyeh(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyeh_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vmpy2es_s0(rss, rtt) +} + +/// `Rdd32=vmpyeh(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyeh_PP_s1_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vmpy2es_s1(rss, rtt) +} + +/// `Rdd32=vmpyh(Rs32,Rt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyh_RR_sat(rs: i32, rt: i32) -> i64 { + hexagon_M2_vmpy2s_s0(rs, rt) +} + +/// `Rd32=vmpyh(Rs32,Rt32):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vmpyh_RR_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_vmpy2s_s0pack(rs, rt) +} + +/// `Rdd32=vmpyh(Rs32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyh_RR_s1_sat(rs: i32, rt: i32) -> i64 { + hexagon_M2_vmpy2s_s1(rs, rt) +} + +/// `Rd32=vmpyh(Rs32,Rt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vmpyh_RR_s1_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_vmpy2s_s1pack(rs, rt) +} + +/// `Rdd32=vmpyhsu(Rs32,Rt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyhsu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyhsu_RR_sat(rs: i32, rt: i32) -> i64 { + hexagon_M2_vmpy2su_s0(rs, rt) +} + +/// `Rdd32=vmpyhsu(Rs32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyhsu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyhsu_RR_s1_sat(rs: i32, rt: i32) -> i64 { + hexagon_M2_vmpy2su_s1(rs, rt) +} + +/// `Rd32=vraddh(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vraddh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vraddh_PP(rss: i64, rtt: i64) -> i32 { + hexagon_M2_vraddh(rss, rtt) +} + +/// `Rd32=vradduh(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vradduh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vradduh_PP(rss: i64, rtt: i64) -> i32 { + hexagon_M2_vradduh(rss, rtt) +} + +/// `Rxx32+=vrcmpyi(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcmpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcmpyiacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vrcmaci_s0(rxx, rss, rtt) +} + +/// `Rxx32+=vrcmpyi(Rss32,Rtt32*)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcmpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcmpyiacc_PP_conj(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vrcmaci_s0c(rxx, rss, rtt) +} + +/// `Rxx32+=vrcmpyr(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcmpyr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcmpyracc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vrcmacr_s0(rxx, rss, rtt) +} + +/// `Rxx32+=vrcmpyr(Rss32,Rtt32*)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcmpyr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcmpyracc_PP_conj(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vrcmacr_s0c(rxx, rss, rtt) +} + +/// `Rdd32=vrcmpyi(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcmpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcmpyi_PP(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vrcmpyi_s0(rss, rtt) +} + +/// `Rdd32=vrcmpyi(Rss32,Rtt32*)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcmpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcmpyi_PP_conj(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vrcmpyi_s0c(rss, rtt) +} + +/// `Rdd32=vrcmpyr(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcmpyr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcmpyr_PP(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vrcmpyr_s0(rss, rtt) +} + +/// `Rdd32=vrcmpyr(Rss32,Rtt32*)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcmpyr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcmpyr_PP_conj(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vrcmpyr_s0c(rss, rtt) +} + +/// `Rxx32+=vrcmpys(Rss32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcmpys))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcmpysacc_PR_s1_sat(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_M2_vrcmpys_acc_s1(rxx, rss, rt) +} + +/// `Rdd32=vrcmpys(Rss32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcmpys))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcmpys_PR_s1_sat(rss: i64, rt: i32) -> i64 { + hexagon_M2_vrcmpys_s1(rss, rt) +} + +/// `Rd32=vrcmpys(Rss32,Rt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcmpys))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vrcmpys_PR_s1_rnd_sat(rss: i64, rt: i32) -> i32 { + hexagon_M2_vrcmpys_s1rp(rss, rt) +} + +/// `Rxx32+=vrmpyh(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpyhacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vrmac_s0(rxx, rss, rtt) +} + +/// `Rdd32=vrmpyh(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpyh_PP(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vrmpy_s0(rss, rtt) +} + +/// `Rx32^=xor(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(xor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_xorxacc_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_xor_xacc(rx, rs, rt) +} + +/// `Rx32&=and(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_andand_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_and_and(rx, rs, rt) +} + +/// `Rx32&=and(Rs32,~Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_andand_RnR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_and_andn(rx, rs, rt) +} + +/// `Rx32&=or(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_orand_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_and_or(rx, rs, rt) +} + +/// `Rx32&=xor(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(xor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_xorand_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_and_xor(rx, rs, rt) +} + +/// `Rd32=cmpyiwh(Rss32,Rt32):<<1:rnd:sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpyiwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyiwh_PR_s1_rnd_sat(rss: i64, rt: i32) -> i32 { + hexagon_M4_cmpyi_wh(rss, rt) +} + +/// `Rd32=cmpyiwh(Rss32,Rt32*):<<1:rnd:sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpyiwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyiwh_PR_conj_s1_rnd_sat(rss: i64, rt: i32) -> i32 { + hexagon_M4_cmpyi_whc(rss, rt) +} + +/// `Rd32=cmpyrwh(Rss32,Rt32):<<1:rnd:sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpyrwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyrwh_PR_s1_rnd_sat(rss: i64, rt: i32) -> i32 { + hexagon_M4_cmpyr_wh(rss, rt) +} + +/// `Rd32=cmpyrwh(Rss32,Rt32*):<<1:rnd:sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpyrwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyrwh_PR_conj_s1_rnd_sat(rss: i64, rt: i32) -> i32 { + hexagon_M4_cmpyr_whc(rss, rt) +} + +/// `Rx32+=mpy(Rs32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RR_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_mac_up_s1_sat(rx, rs, rt) +} + +/// `Rd32=add(#u6,mpyi(Rs32,#U6))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0, 2)] +#[cfg_attr(test, assert_instr(add, IU6 = 0, IU6_2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_mpyi_IRI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU6, 6); + static_assert_uimm_bits!(IU6_2, 6); + hexagon_M4_mpyri_addi(IU6 as i32, rs, IU6_2 as i32) +} + +/// `Rd32=add(Ru32,mpyi(Rs32,#u6))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(add, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_mpyi_RRI(ru: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU6, 6); + hexagon_M4_mpyri_addr(ru, rs, IU6 as i32) +} + +/// `Rd32=add(Ru32,mpyi(#u6:2,Rs32))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(add, IU6_2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_mpyi_RIR(ru: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU6_2, 6); + hexagon_M4_mpyri_addr_u2(ru, IU6_2 as i32, rs) +} + +/// `Rd32=add(#u6,mpyi(Rs32,Rt32))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0)] +#[cfg_attr(test, assert_instr(add, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_mpyi_IRR(rs: i32, rt: i32) -> i32 { + static_assert_uimm_bits!(IU6, 6); + hexagon_M4_mpyrr_addi(IU6 as i32, rs, rt) +} + +/// `Ry32=add(Ru32,mpyi(Ry32,Rs32))` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_mpyi_RRR(ru: i32, ry: i32, rs: i32) -> i32 { + hexagon_M4_mpyrr_addr(ru, ry, rs) +} + +/// `Rx32-=mpy(Rs32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RR_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_nac_up_s1_sat(rx, rs, rt) +} + +/// `Rx32|=and(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_andor_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_or_and(rx, rs, rt) +} + +/// `Rx32|=and(Rs32,~Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_andor_RnR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_or_andn(rx, rs, rt) +} + +/// `Rx32|=or(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_oror_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_or_or(rx, rs, rt) +} + +/// `Rx32|=xor(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(xor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_xoror_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_or_xor(rx, rs, rt) +} + +/// `Rdd32=pmpyw(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(pmpyw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_pmpyw_RR(rs: i32, rt: i32) -> i64 { + hexagon_M4_pmpyw(rs, rt) +} + +/// `Rxx32^=pmpyw(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(pmpyw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_pmpywxacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M4_pmpyw_acc(rxx, rs, rt) +} + +/// `Rdd32=vpmpyh(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vpmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vpmpyh_RR(rs: i32, rt: i32) -> i64 { + hexagon_M4_vpmpyh(rs, rt) +} + +/// `Rxx32^=vpmpyh(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vpmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vpmpyhxacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M4_vpmpyh_acc(rxx, rs, rt) +} + +/// `Rxx32+=vrmpyweh(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpywehacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M4_vrmpyeh_acc_s0(rxx, rss, rtt) +} + +/// `Rxx32+=vrmpyweh(Rss32,Rtt32):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpywehacc_PP_s1(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M4_vrmpyeh_acc_s1(rxx, rss, rtt) +} + +/// `Rdd32=vrmpyweh(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpyweh_PP(rss: i64, rtt: i64) -> i64 { + hexagon_M4_vrmpyeh_s0(rss, rtt) +} + +/// `Rdd32=vrmpyweh(Rss32,Rtt32):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpyweh_PP_s1(rss: i64, rtt: i64) -> i64 { + hexagon_M4_vrmpyeh_s1(rss, rtt) +} + +/// `Rxx32+=vrmpywoh(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpywohacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M4_vrmpyoh_acc_s0(rxx, rss, rtt) +} + +/// `Rxx32+=vrmpywoh(Rss32,Rtt32):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpywohacc_PP_s1(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M4_vrmpyoh_acc_s1(rxx, rss, rtt) +} + +/// `Rdd32=vrmpywoh(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpywoh_PP(rss: i64, rtt: i64) -> i64 { + hexagon_M4_vrmpyoh_s0(rss, rtt) +} + +/// `Rdd32=vrmpywoh(Rss32,Rtt32):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpywoh_PP_s1(rss: i64, rtt: i64) -> i64 { + hexagon_M4_vrmpyoh_s1(rss, rtt) +} + +/// `Rx32^=and(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_andxacc_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_xor_and(rx, rs, rt) +} + +/// `Rx32^=and(Rs32,~Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_andxacc_RnR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_xor_andn(rx, rs, rt) +} + +/// `Rx32^=or(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_orxacc_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_xor_or(rx, rs, rt) +} + +/// `Rxx32^=xor(Rss32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(xor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_xorxacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M4_xor_xacc(rxx, rss, rtt) +} + +/// `Rxx32+=vdmpybsu(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vdmpybsu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vdmpybsuacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M5_vdmacbsu(rxx, rss, rtt) +} + +/// `Rdd32=vdmpybsu(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vdmpybsu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vdmpybsu_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M5_vdmpybsu(rss, rtt) +} + +/// `Rxx32+=vmpybsu(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpybsu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpybsuacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M5_vmacbsu(rxx, rs, rt) +} + +/// `Rxx32+=vmpybu(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpybu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpybuacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M5_vmacbuu(rxx, rs, rt) +} + +/// `Rdd32=vmpybsu(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpybsu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpybsu_RR(rs: i32, rt: i32) -> i64 { + hexagon_M5_vmpybsu(rs, rt) +} + +/// `Rdd32=vmpybu(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpybu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpybu_RR(rs: i32, rt: i32) -> i64 { + hexagon_M5_vmpybuu(rs, rt) +} + +/// `Rxx32+=vrmpybsu(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpybsu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpybsuacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M5_vrmacbsu(rxx, rss, rtt) +} + +/// `Rxx32+=vrmpybu(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpybu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpybuacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M5_vrmacbuu(rxx, rss, rtt) +} + +/// `Rdd32=vrmpybsu(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpybsu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpybsu_PP(rss: i64, rtt: i64) -> i64 { + hexagon_M5_vrmpybsu(rss, rtt) +} + +/// `Rdd32=vrmpybu(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpybu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpybu_PP(rss: i64, rtt: i64) -> i64 { + hexagon_M5_vrmpybuu(rss, rtt) +} + +/// `Rd32=addasl(Rt32,Rs32,#u3)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(addasl, IU3 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_addasl_RRI(rt: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU3, 3); + hexagon_S2_addasl_rrri(rt, rs, IU3 as i32) +} + +/// `Rdd32=asl(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(asl, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asl_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asl_i_p(rss, IU6 as i32) +} + +/// `Rxx32+=asl(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asl, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_aslacc_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asl_i_p_acc(rxx, rss, IU6 as i32) +} + +/// `Rxx32&=asl(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asl, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asland_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asl_i_p_and(rxx, rss, IU6 as i32) +} + +/// `Rxx32-=asl(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asl, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_aslnac_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asl_i_p_nac(rxx, rss, IU6 as i32) +} + +/// `Rxx32|=asl(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asl, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_aslor_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asl_i_p_or(rxx, rss, IU6 as i32) +} + +/// `Rxx32^=asl(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asl, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_aslxacc_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asl_i_p_xacc(rxx, rss, IU6 as i32) +} + +/// `Rd32=asl(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(asl, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asl_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asl_i_r(rs, IU5 as i32) +} + +/// `Rx32+=asl(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asl, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_aslacc_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asl_i_r_acc(rx, rs, IU5 as i32) +} + +/// `Rx32&=asl(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asl, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asland_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asl_i_r_and(rx, rs, IU5 as i32) +} + +/// `Rx32-=asl(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asl, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_aslnac_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asl_i_r_nac(rx, rs, IU5 as i32) +} + +/// `Rx32|=asl(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asl, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_aslor_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asl_i_r_or(rx, rs, IU5 as i32) +} + +/// `Rd32=asl(Rs32,#u5):sat` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(asl, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asl_RI_sat(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asl_i_r_sat(rs, IU5 as i32) +} + +/// `Rx32^=asl(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asl, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_aslxacc_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asl_i_r_xacc(rx, rs, IU5 as i32) +} + +/// `Rdd32=vaslh(Rss32,#u4)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vaslh, IU4 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vaslh_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU4, 4); + hexagon_S2_asl_i_vh(rss, IU4 as i32) +} + +/// `Rdd32=vaslw(Rss32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vaslw, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vaslw_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asl_i_vw(rss, IU5 as i32) +} + +/// `Rdd32=asl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asl_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_asl_r_p(rss, rt) +} + +/// `Rxx32+=asl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_aslacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_asl_r_p_acc(rxx, rss, rt) +} + +/// `Rxx32&=asl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asland_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_asl_r_p_and(rxx, rss, rt) +} + +/// `Rxx32-=asl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_aslnac_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_asl_r_p_nac(rxx, rss, rt) +} + +/// `Rxx32|=asl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_aslor_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_asl_r_p_or(rxx, rss, rt) +} + +/// `Rxx32^=asl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_aslxacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_asl_r_p_xor(rxx, rss, rt) +} + +/// `Rd32=asl(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asl_RR(rs: i32, rt: i32) -> i32 { + hexagon_S2_asl_r_r(rs, rt) +} + +/// `Rx32+=asl(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_aslacc_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_asl_r_r_acc(rx, rs, rt) +} + +/// `Rx32&=asl(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asland_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_asl_r_r_and(rx, rs, rt) +} + +/// `Rx32-=asl(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_aslnac_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_asl_r_r_nac(rx, rs, rt) +} + +/// `Rx32|=asl(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_aslor_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_asl_r_r_or(rx, rs, rt) +} + +/// `Rd32=asl(Rs32,Rt32):sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asl_RR_sat(rs: i32, rt: i32) -> i32 { + hexagon_S2_asl_r_r_sat(rs, rt) +} + +/// `Rdd32=vaslh(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaslh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vaslh_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_asl_r_vh(rss, rt) +} + +/// `Rdd32=vaslw(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaslw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vaslw_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_asl_r_vw(rss, rt) +} + +/// `Rdd32=asr(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(asr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asr_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asr_i_p(rss, IU6 as i32) +} + +/// `Rxx32+=asr(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asracc_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asr_i_p_acc(rxx, rss, IU6 as i32) +} + +/// `Rxx32&=asr(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asrand_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asr_i_p_and(rxx, rss, IU6 as i32) +} + +/// `Rxx32-=asr(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asrnac_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asr_i_p_nac(rxx, rss, IU6 as i32) +} + +/// `Rxx32|=asr(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asror_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asr_i_p_or(rxx, rss, IU6 as i32) +} + +/// `Rdd32=asr(Rss32,#u6):rnd` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(asr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asr_PI_rnd(rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asr_i_p_rnd(rss, IU6 as i32) +} + +/// `Rdd32=asrrnd(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(asrrnd, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asrrnd_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asr_i_p_rnd_goodsyntax(rss, IU6 as i32) +} + +/// `Rd32=asr(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(asr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asr_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asr_i_r(rs, IU5 as i32) +} + +/// `Rx32+=asr(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asracc_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asr_i_r_acc(rx, rs, IU5 as i32) +} + +/// `Rx32&=asr(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asrand_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asr_i_r_and(rx, rs, IU5 as i32) +} + +/// `Rx32-=asr(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asrnac_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asr_i_r_nac(rx, rs, IU5 as i32) +} + +/// `Rx32|=asr(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asror_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asr_i_r_or(rx, rs, IU5 as i32) +} + +/// `Rd32=asr(Rs32,#u5):rnd` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(asr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asr_RI_rnd(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asr_i_r_rnd(rs, IU5 as i32) +} + +/// `Rd32=asrrnd(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(asrrnd, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asrrnd_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asr_i_r_rnd_goodsyntax(rs, IU5 as i32) +} + +/// `Rd32=vasrw(Rss32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vasrw, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vasrw_PI(rss: i64) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asr_i_svw_trun(rss, IU5 as i32) +} + +/// `Rdd32=vasrh(Rss32,#u4)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vasrh, IU4 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vasrh_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU4, 4); + hexagon_S2_asr_i_vh(rss, IU4 as i32) +} + +/// `Rdd32=vasrw(Rss32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vasrw, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vasrw_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asr_i_vw(rss, IU5 as i32) +} + +/// `Rdd32=asr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asr_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_asr_r_p(rss, rt) +} + +/// `Rxx32+=asr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asracc_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_asr_r_p_acc(rxx, rss, rt) +} + +/// `Rxx32&=asr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asrand_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_asr_r_p_and(rxx, rss, rt) +} + +/// `Rxx32-=asr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asrnac_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_asr_r_p_nac(rxx, rss, rt) +} + +/// `Rxx32|=asr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asror_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_asr_r_p_or(rxx, rss, rt) +} + +/// `Rxx32^=asr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asrxacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_asr_r_p_xor(rxx, rss, rt) +} + +/// `Rd32=asr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asr_RR(rs: i32, rt: i32) -> i32 { + hexagon_S2_asr_r_r(rs, rt) +} + +/// `Rx32+=asr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asracc_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_asr_r_r_acc(rx, rs, rt) +} + +/// `Rx32&=asr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asrand_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_asr_r_r_and(rx, rs, rt) +} + +/// `Rx32-=asr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asrnac_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_asr_r_r_nac(rx, rs, rt) +} + +/// `Rx32|=asr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asror_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_asr_r_r_or(rx, rs, rt) +} + +/// `Rd32=asr(Rs32,Rt32):sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asr_RR_sat(rs: i32, rt: i32) -> i32 { + hexagon_S2_asr_r_r_sat(rs, rt) +} + +/// `Rd32=vasrw(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vasrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vasrw_PR(rss: i64, rt: i32) -> i32 { + hexagon_S2_asr_r_svw_trun(rss, rt) +} + +/// `Rdd32=vasrh(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vasrh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vasrh_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_asr_r_vh(rss, rt) +} + +/// `Rdd32=vasrw(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vasrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vasrw_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_asr_r_vw(rss, rt) +} + +/// `Rd32=brev(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(brev))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_brev_R(rs: i32) -> i32 { + hexagon_S2_brev(rs) +} + +/// `Rdd32=brev(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(brev))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_brev_P(rss: i64) -> i64 { + hexagon_S2_brevp(rss) +} + +/// `Rd32=cl0(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cl0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cl0_R(rs: i32) -> i32 { + hexagon_S2_cl0(rs) +} + +/// `Rd32=cl0(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cl0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cl0_P(rss: i64) -> i32 { + hexagon_S2_cl0p(rss) +} + +/// `Rd32=cl1(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cl1))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cl1_R(rs: i32) -> i32 { + hexagon_S2_cl1(rs) +} + +/// `Rd32=cl1(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cl1))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cl1_P(rss: i64) -> i32 { + hexagon_S2_cl1p(rss) +} + +/// `Rd32=clb(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(clb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_clb_R(rs: i32) -> i32 { + hexagon_S2_clb(rs) +} + +/// `Rd32=normamt(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(normamt))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_normamt_R(rs: i32) -> i32 { + hexagon_S2_clbnorm(rs) +} + +/// `Rd32=clb(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(clb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_clb_P(rss: i64) -> i32 { + hexagon_S2_clbp(rss) +} + +/// `Rd32=clrbit(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(clrbit, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_clrbit_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_clrbit_i(rs, IU5 as i32) +} + +/// `Rd32=clrbit(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(clrbit))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_clrbit_RR(rs: i32, rt: i32) -> i32 { + hexagon_S2_clrbit_r(rs, rt) +} + +/// `Rd32=ct0(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(ct0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_ct0_R(rs: i32) -> i32 { + hexagon_S2_ct0(rs) +} + +/// `Rd32=ct0(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(ct0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_ct0_P(rss: i64) -> i32 { + hexagon_S2_ct0p(rss) +} + +/// `Rd32=ct1(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(ct1))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_ct1_R(rs: i32) -> i32 { + hexagon_S2_ct1(rs) +} + +/// `Rd32=ct1(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(ct1))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_ct1_P(rss: i64) -> i32 { + hexagon_S2_ct1p(rss) +} + +/// `Rdd32=deinterleave(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(deinterleave))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_deinterleave_P(rss: i64) -> i64 { + hexagon_S2_deinterleave(rss) +} + +/// `Rd32=extractu(Rs32,#u5,#U5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1, 2)] +#[cfg_attr(test, assert_instr(extractu, IU5 = 0, IU5_2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_extractu_RII(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + static_assert_uimm_bits!(IU5_2, 5); + hexagon_S2_extractu(rs, IU5 as i32, IU5_2 as i32) +} + +/// `Rd32=extractu(Rs32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(extractu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_extractu_RP(rs: i32, rtt: i64) -> i32 { + hexagon_S2_extractu_rp(rs, rtt) +} + +/// `Rdd32=extractu(Rss32,#u6,#U6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1, 2)] +#[cfg_attr(test, assert_instr(extractu, IU6 = 0, IU6_2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_extractu_PII(rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + static_assert_uimm_bits!(IU6_2, 6); + hexagon_S2_extractup(rss, IU6 as i32, IU6_2 as i32) +} + +/// `Rdd32=extractu(Rss32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(extractu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_extractu_PP(rss: i64, rtt: i64) -> i64 { + hexagon_S2_extractup_rp(rss, rtt) +} + +/// `Rx32=insert(Rs32,#u5,#U5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2, 3)] +#[cfg_attr(test, assert_instr(insert, IU5 = 0, IU5_2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_insert_RII(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + static_assert_uimm_bits!(IU5_2, 5); + hexagon_S2_insert(rx, rs, IU5 as i32, IU5_2 as i32) +} + +/// `Rx32=insert(Rs32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(insert))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_insert_RP(rx: i32, rs: i32, rtt: i64) -> i32 { + hexagon_S2_insert_rp(rx, rs, rtt) +} + +/// `Rxx32=insert(Rss32,#u6,#U6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2, 3)] +#[cfg_attr(test, assert_instr(insert, IU6 = 0, IU6_2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_insert_PII(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + static_assert_uimm_bits!(IU6_2, 6); + hexagon_S2_insertp(rxx, rss, IU6 as i32, IU6_2 as i32) +} + +/// `Rxx32=insert(Rss32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(insert))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_insert_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_S2_insertp_rp(rxx, rss, rtt) +} + +/// `Rdd32=interleave(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(interleave))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_interleave_P(rss: i64) -> i64 { + hexagon_S2_interleave(rss) +} + +/// `Rdd32=lfs(Rss32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lfs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lfs_PP(rss: i64, rtt: i64) -> i64 { + hexagon_S2_lfsp(rss, rtt) +} + +/// `Rdd32=lsl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsl_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_lsl_r_p(rss, rt) +} + +/// `Rxx32+=lsl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lslacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_lsl_r_p_acc(rxx, rss, rt) +} + +/// `Rxx32&=lsl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsland_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_lsl_r_p_and(rxx, rss, rt) +} + +/// `Rxx32-=lsl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lslnac_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_lsl_r_p_nac(rxx, rss, rt) +} + +/// `Rxx32|=lsl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lslor_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_lsl_r_p_or(rxx, rss, rt) +} + +/// `Rxx32^=lsl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lslxacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_lsl_r_p_xor(rxx, rss, rt) +} + +/// `Rd32=lsl(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsl_RR(rs: i32, rt: i32) -> i32 { + hexagon_S2_lsl_r_r(rs, rt) +} + +/// `Rx32+=lsl(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lslacc_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_lsl_r_r_acc(rx, rs, rt) +} + +/// `Rx32&=lsl(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsland_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_lsl_r_r_and(rx, rs, rt) +} + +/// `Rx32-=lsl(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lslnac_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_lsl_r_r_nac(rx, rs, rt) +} + +/// `Rx32|=lsl(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lslor_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_lsl_r_r_or(rx, rs, rt) +} + +/// `Rdd32=vlslh(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vlslh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vlslh_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_lsl_r_vh(rss, rt) +} + +/// `Rdd32=vlslw(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vlslw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vlslw_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_lsl_r_vw(rss, rt) +} + +/// `Rdd32=lsr(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(lsr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsr_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_lsr_i_p(rss, IU6 as i32) +} + +/// `Rxx32+=lsr(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(lsr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsracc_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_lsr_i_p_acc(rxx, rss, IU6 as i32) +} + +/// `Rxx32&=lsr(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(lsr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsrand_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_lsr_i_p_and(rxx, rss, IU6 as i32) +} + +/// `Rxx32-=lsr(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(lsr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsrnac_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_lsr_i_p_nac(rxx, rss, IU6 as i32) +} + +/// `Rxx32|=lsr(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(lsr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsror_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_lsr_i_p_or(rxx, rss, IU6 as i32) +} + +/// `Rxx32^=lsr(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(lsr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsrxacc_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_lsr_i_p_xacc(rxx, rss, IU6 as i32) +} + +/// `Rd32=lsr(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(lsr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsr_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_lsr_i_r(rs, IU5 as i32) +} + +/// `Rx32+=lsr(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(lsr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsracc_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_lsr_i_r_acc(rx, rs, IU5 as i32) +} + +/// `Rx32&=lsr(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(lsr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsrand_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_lsr_i_r_and(rx, rs, IU5 as i32) +} + +/// `Rx32-=lsr(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(lsr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsrnac_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_lsr_i_r_nac(rx, rs, IU5 as i32) +} + +/// `Rx32|=lsr(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(lsr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsror_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_lsr_i_r_or(rx, rs, IU5 as i32) +} + +/// `Rx32^=lsr(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(lsr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsrxacc_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_lsr_i_r_xacc(rx, rs, IU5 as i32) +} + +/// `Rdd32=vlsrh(Rss32,#u4)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vlsrh, IU4 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vlsrh_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU4, 4); + hexagon_S2_lsr_i_vh(rss, IU4 as i32) +} + +/// `Rdd32=vlsrw(Rss32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vlsrw, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vlsrw_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_lsr_i_vw(rss, IU5 as i32) +} + +/// `Rdd32=lsr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsr_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_lsr_r_p(rss, rt) +} + +/// `Rxx32+=lsr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsracc_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_lsr_r_p_acc(rxx, rss, rt) +} + +/// `Rxx32&=lsr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsrand_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_lsr_r_p_and(rxx, rss, rt) +} + +/// `Rxx32-=lsr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsrnac_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_lsr_r_p_nac(rxx, rss, rt) +} + +/// `Rxx32|=lsr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsror_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_lsr_r_p_or(rxx, rss, rt) +} + +/// `Rxx32^=lsr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsrxacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_lsr_r_p_xor(rxx, rss, rt) +} + +/// `Rd32=lsr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsr_RR(rs: i32, rt: i32) -> i32 { + hexagon_S2_lsr_r_r(rs, rt) +} + +/// `Rx32+=lsr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsracc_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_lsr_r_r_acc(rx, rs, rt) +} + +/// `Rx32&=lsr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsrand_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_lsr_r_r_and(rx, rs, rt) +} + +/// `Rx32-=lsr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsrnac_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_lsr_r_r_nac(rx, rs, rt) +} + +/// `Rx32|=lsr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsror_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_lsr_r_r_or(rx, rs, rt) +} + +/// `Rdd32=vlsrh(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vlsrh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vlsrh_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_lsr_r_vh(rss, rt) +} + +/// `Rdd32=vlsrw(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vlsrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vlsrw_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_lsr_r_vw(rss, rt) +} + +/// `Rdd32=packhl(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(packhl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_packhl_RR(rs: i32, rt: i32) -> i64 { + hexagon_S2_packhl(rs, rt) +} + +/// `Rd32=parity(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(parity))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_parity_PP(rss: i64, rtt: i64) -> i32 { + hexagon_S2_parityp(rss, rtt) +} + +/// `Rd32=setbit(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(setbit, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_setbit_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_setbit_i(rs, IU5 as i32) +} + +/// `Rd32=setbit(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(setbit))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_setbit_RR(rs: i32, rt: i32) -> i32 { + hexagon_S2_setbit_r(rs, rt) +} + +/// `Rdd32=shuffeb(Rss32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(shuffeb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_shuffeb_PP(rss: i64, rtt: i64) -> i64 { + hexagon_S2_shuffeb(rss, rtt) +} + +/// `Rdd32=shuffeh(Rss32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(shuffeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_shuffeh_PP(rss: i64, rtt: i64) -> i64 { + hexagon_S2_shuffeh(rss, rtt) +} + +/// `Rdd32=shuffob(Rtt32,Rss32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(shuffob))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_shuffob_PP(rtt: i64, rss: i64) -> i64 { + hexagon_S2_shuffob(rtt, rss) +} + +/// `Rdd32=shuffoh(Rtt32,Rss32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(shuffoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_shuffoh_PP(rtt: i64, rss: i64) -> i64 { + hexagon_S2_shuffoh(rtt, rss) +} + +/// `Rd32=vsathb(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsathb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vsathb_R(rs: i32) -> i32 { + hexagon_S2_svsathb(rs) +} + +/// `Rd32=vsathub(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsathub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vsathub_R(rs: i32) -> i32 { + hexagon_S2_svsathub(rs) +} + +/// `Rx32=tableidxb(Rs32,#u4,#U5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(2, 3)] +#[cfg_attr(test, assert_instr(tableidxb, IU4 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_tableidxb_RII(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU4, 4); + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_tableidxb_goodsyntax(rx, rs, IU4 as i32, IU5 as i32) +} + +/// `Rx32=tableidxd(Rs32,#u4,#U5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(2, 3)] +#[cfg_attr(test, assert_instr(tableidxd, IU4 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_tableidxd_RII(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU4, 4); + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_tableidxd_goodsyntax(rx, rs, IU4 as i32, IU5 as i32) +} + +/// `Rx32=tableidxh(Rs32,#u4,#U5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(2, 3)] +#[cfg_attr(test, assert_instr(tableidxh, IU4 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_tableidxh_RII(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU4, 4); + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_tableidxh_goodsyntax(rx, rs, IU4 as i32, IU5 as i32) +} + +/// `Rx32=tableidxw(Rs32,#u4,#U5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(2, 3)] +#[cfg_attr(test, assert_instr(tableidxw, IU4 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_tableidxw_RII(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU4, 4); + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_tableidxw_goodsyntax(rx, rs, IU4 as i32, IU5 as i32) +} + +/// `Rd32=togglebit(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(togglebit, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_togglebit_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_togglebit_i(rs, IU5 as i32) +} + +/// `Rd32=togglebit(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(togglebit))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_togglebit_RR(rs: i32, rt: i32) -> i32 { + hexagon_S2_togglebit_r(rs, rt) +} + +/// `Pd4=tstbit(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(tstbit, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_tstbit_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_tstbit_i(rs, IU5 as i32) +} + +/// `Pd4=tstbit(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(tstbit))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_tstbit_RR(rs: i32, rt: i32) -> i32 { + hexagon_S2_tstbit_r(rs, rt) +} + +/// `Rdd32=valignb(Rtt32,Rss32,#u3)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(valignb, IU3 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_valignb_PPI(rtt: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU3, 3); + hexagon_S2_valignib(rtt, rss, IU3 as i32) +} + +/// `Rdd32=valignb(Rtt32,Rss32,Pu4)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(valignb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_valignb_PPp(rtt: i64, rss: i64, pu: i32) -> i64 { + hexagon_S2_valignrb(rtt, rss, pu) +} + +/// `Rdd32=vcnegh(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcnegh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vcnegh_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_vcnegh(rss, rt) +} + +/// `Rdd32=vcrotate(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcrotate))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vcrotate_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_vcrotate(rss, rt) +} + +/// `Rxx32+=vrcnegh(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcnegh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcneghacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_vrcnegh(rxx, rss, rt) +} + +/// `Rd32=vrndwh(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrndwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vrndwh_P(rss: i64) -> i32 { + hexagon_S2_vrndpackwh(rss) +} + +/// `Rd32=vrndwh(Rss32):sat` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrndwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vrndwh_P_sat(rss: i64) -> i32 { + hexagon_S2_vrndpackwhs(rss) +} + +/// `Rd32=vsathb(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsathb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vsathb_P(rss: i64) -> i32 { + hexagon_S2_vsathb(rss) +} + +/// `Rdd32=vsathb(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsathb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsathb_P(rss: i64) -> i64 { + hexagon_S2_vsathb_nopack(rss) +} + +/// `Rd32=vsathub(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsathub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vsathub_P(rss: i64) -> i32 { + hexagon_S2_vsathub(rss) +} + +/// `Rdd32=vsathub(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsathub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsathub_P(rss: i64) -> i64 { + hexagon_S2_vsathub_nopack(rss) +} + +/// `Rd32=vsatwh(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsatwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vsatwh_P(rss: i64) -> i32 { + hexagon_S2_vsatwh(rss) +} + +/// `Rdd32=vsatwh(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsatwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsatwh_P(rss: i64) -> i64 { + hexagon_S2_vsatwh_nopack(rss) +} + +/// `Rd32=vsatwuh(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsatwuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vsatwuh_P(rss: i64) -> i32 { + hexagon_S2_vsatwuh(rss) +} + +/// `Rdd32=vsatwuh(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsatwuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsatwuh_P(rss: i64) -> i64 { + hexagon_S2_vsatwuh_nopack(rss) +} + +/// `Rd32=vsplatb(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsplatb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vsplatb_R(rs: i32) -> i32 { + hexagon_S2_vsplatrb(rs) +} + +/// `Rdd32=vsplath(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsplath))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsplath_R(rs: i32) -> i64 { + hexagon_S2_vsplatrh(rs) +} + +/// `Rdd32=vspliceb(Rss32,Rtt32,#u3)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vspliceb, IU3 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vspliceb_PPI(rss: i64, rtt: i64) -> i64 { + static_assert_uimm_bits!(IU3, 3); + hexagon_S2_vspliceib(rss, rtt, IU3 as i32) +} + +/// `Rdd32=vspliceb(Rss32,Rtt32,Pu4)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vspliceb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vspliceb_PPp(rss: i64, rtt: i64, pu: i32) -> i64 { + hexagon_S2_vsplicerb(rss, rtt, pu) +} + +/// `Rdd32=vsxtbh(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsxtbh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsxtbh_R(rs: i32) -> i64 { + hexagon_S2_vsxtbh(rs) +} + +/// `Rdd32=vsxthw(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsxthw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsxthw_R(rs: i32) -> i64 { + hexagon_S2_vsxthw(rs) +} + +/// `Rd32=vtrunehb(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vtrunehb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vtrunehb_P(rss: i64) -> i32 { + hexagon_S2_vtrunehb(rss) +} + +/// `Rdd32=vtrunewh(Rss32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vtrunewh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vtrunewh_PP(rss: i64, rtt: i64) -> i64 { + hexagon_S2_vtrunewh(rss, rtt) +} + +/// `Rd32=vtrunohb(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vtrunohb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vtrunohb_P(rss: i64) -> i32 { + hexagon_S2_vtrunohb(rss) +} + +/// `Rdd32=vtrunowh(Rss32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vtrunowh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vtrunowh_PP(rss: i64, rtt: i64) -> i64 { + hexagon_S2_vtrunowh(rss, rtt) +} + +/// `Rdd32=vzxtbh(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vzxtbh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vzxtbh_R(rs: i32) -> i64 { + hexagon_S2_vzxtbh(rs) +} + +/// `Rdd32=vzxthw(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vzxthw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vzxthw_R(rs: i32) -> i64 { + hexagon_S2_vzxthw(rs) +} + +/// `Rd32=add(Rs32,add(Ru32,#s6))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(add, IS6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_add_RRI(rs: i32, ru: i32) -> i32 { + static_assert_simm_bits!(IS6, 6); + hexagon_S4_addaddi(rs, ru, IS6) +} + +/// `Rx32=add(#u8,asl(Rx32,#U5))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0, 2)] +#[cfg_attr(test, assert_instr(add, IU8 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_asl_IRI(rx: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + static_assert_uimm_bits!(IU5, 5); + hexagon_S4_addi_asl_ri(IU8 as i32, rx, IU5 as i32) +} + +/// `Rx32=add(#u8,lsr(Rx32,#U5))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0, 2)] +#[cfg_attr(test, assert_instr(add, IU8 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_lsr_IRI(rx: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + static_assert_uimm_bits!(IU5, 5); + hexagon_S4_addi_lsr_ri(IU8 as i32, rx, IU5 as i32) +} + +/// `Rx32=and(#u8,asl(Rx32,#U5))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0, 2)] +#[cfg_attr(test, assert_instr(and, IU8 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_and_asl_IRI(rx: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + static_assert_uimm_bits!(IU5, 5); + hexagon_S4_andi_asl_ri(IU8 as i32, rx, IU5 as i32) +} + +/// `Rx32=and(#u8,lsr(Rx32,#U5))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0, 2)] +#[cfg_attr(test, assert_instr(and, IU8 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_and_lsr_IRI(rx: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + static_assert_uimm_bits!(IU5, 5); + hexagon_S4_andi_lsr_ri(IU8 as i32, rx, IU5 as i32) +} + +/// `Rd32=add(clb(Rs32),#s6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(add, IS6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_clb_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS6, 6); + hexagon_S4_clbaddi(rs, IS6) +} + +/// `Rd32=add(clb(Rss32),#s6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(add, IS6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_clb_PI(rss: i64) -> i32 { + static_assert_simm_bits!(IS6, 6); + hexagon_S4_clbpaddi(rss, IS6) +} + +/// `Rd32=normamt(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(normamt))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_normamt_P(rss: i64) -> i32 { + hexagon_S4_clbpnorm(rss) +} + +/// `Rd32=extract(Rs32,#u5,#U5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1, 2)] +#[cfg_attr(test, assert_instr(extract, IU5 = 0, IU5_2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_extract_RII(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + static_assert_uimm_bits!(IU5_2, 5); + hexagon_S4_extract(rs, IU5 as i32, IU5_2 as i32) +} + +/// `Rd32=extract(Rs32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(extract))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_extract_RP(rs: i32, rtt: i64) -> i32 { + hexagon_S4_extract_rp(rs, rtt) +} + +/// `Rdd32=extract(Rss32,#u6,#U6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1, 2)] +#[cfg_attr(test, assert_instr(extract, IU6 = 0, IU6_2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_extract_PII(rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + static_assert_uimm_bits!(IU6_2, 6); + hexagon_S4_extractp(rss, IU6 as i32, IU6_2 as i32) +} + +/// `Rdd32=extract(Rss32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(extract))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_extract_PP(rss: i64, rtt: i64) -> i64 { + hexagon_S4_extractp_rp(rss, rtt) +} + +/// `Rd32=lsl(#s6,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0)] +#[cfg_attr(test, assert_instr(lsl, IS6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsl_IR(rt: i32) -> i32 { + static_assert_simm_bits!(IS6, 6); + hexagon_S4_lsli(IS6, rt) +} + +/// `Pd4=!tstbit(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_tstbit_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S4_ntstbit_i(rs, IU5 as i32) +} + +/// `Pd4=!tstbit(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_tstbit_RR(rs: i32, rt: i32) -> i32 { + hexagon_S4_ntstbit_r(rs, rt) +} + +/// `Rx32|=and(Rs32,#s10)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(and, IS10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_andor_RI(rx: i32, rs: i32) -> i32 { + static_assert_simm_bits!(IS10, 10); + hexagon_S4_or_andi(rx, rs, IS10) +} + +/// `Rx32=or(Ru32,and(Rx32,#s10))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(or, IS10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_or_and_RRI(ru: i32, rx: i32) -> i32 { + static_assert_simm_bits!(IS10, 10); + hexagon_S4_or_andix(ru, rx, IS10) +} + +/// `Rx32|=or(Rs32,#s10)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(or, IS10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_oror_RI(rx: i32, rs: i32) -> i32 { + static_assert_simm_bits!(IS10, 10); + hexagon_S4_or_ori(rx, rs, IS10) +} + +/// `Rx32=or(#u8,asl(Rx32,#U5))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0, 2)] +#[cfg_attr(test, assert_instr(or, IU8 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_or_asl_IRI(rx: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + static_assert_uimm_bits!(IU5, 5); + hexagon_S4_ori_asl_ri(IU8 as i32, rx, IU5 as i32) +} + +/// `Rx32=or(#u8,lsr(Rx32,#U5))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0, 2)] +#[cfg_attr(test, assert_instr(or, IU8 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_or_lsr_IRI(rx: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + static_assert_uimm_bits!(IU5, 5); + hexagon_S4_ori_lsr_ri(IU8 as i32, rx, IU5 as i32) +} + +/// `Rd32=parity(Rs32,Rt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(parity))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_parity_RR(rs: i32, rt: i32) -> i32 { + hexagon_S4_parity(rs, rt) +} + +/// `Rd32=add(Rs32,sub(#s6,Ru32))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(add, IS6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_sub_RIR(rs: i32, ru: i32) -> i32 { + static_assert_simm_bits!(IS6, 6); + hexagon_S4_subaddi(rs, IS6, ru) +} + +/// `Rx32=sub(#u8,asl(Rx32,#U5))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0, 2)] +#[cfg_attr(test, assert_instr(sub, IU8 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_asl_IRI(rx: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + static_assert_uimm_bits!(IU5, 5); + hexagon_S4_subi_asl_ri(IU8 as i32, rx, IU5 as i32) +} + +/// `Rx32=sub(#u8,lsr(Rx32,#U5))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0, 2)] +#[cfg_attr(test, assert_instr(sub, IU8 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_lsr_IRI(rx: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + static_assert_uimm_bits!(IU5, 5); + hexagon_S4_subi_lsr_ri(IU8 as i32, rx, IU5 as i32) +} + +/// `Rdd32=vrcrotate(Rss32,Rt32,#u2)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vrcrotate, IU2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcrotate_PRI(rss: i64, rt: i32) -> i64 { + static_assert_uimm_bits!(IU2, 2); + hexagon_S4_vrcrotate(rss, rt, IU2 as i32) +} + +/// `Rxx32+=vrcrotate(Rss32,Rt32,#u2)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(vrcrotate, IU2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcrotateacc_PRI(rxx: i64, rss: i64, rt: i32) -> i64 { + static_assert_uimm_bits!(IU2, 2); + hexagon_S4_vrcrotate_acc(rxx, rss, rt, IU2 as i32) +} + +/// `Rdd32=vxaddsubh(Rss32,Rtt32):sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vxaddsubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vxaddsubh_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_S4_vxaddsubh(rss, rtt) +} + +/// `Rdd32=vxaddsubh(Rss32,Rtt32):rnd:>>1:sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vxaddsubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vxaddsubh_PP_rnd_rs1_sat(rss: i64, rtt: i64) -> i64 { + hexagon_S4_vxaddsubhr(rss, rtt) +} + +/// `Rdd32=vxaddsubw(Rss32,Rtt32):sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vxaddsubw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vxaddsubw_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_S4_vxaddsubw(rss, rtt) +} + +/// `Rdd32=vxsubaddh(Rss32,Rtt32):sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vxsubaddh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vxsubaddh_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_S4_vxsubaddh(rss, rtt) +} + +/// `Rdd32=vxsubaddh(Rss32,Rtt32):rnd:>>1:sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vxsubaddh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vxsubaddh_PP_rnd_rs1_sat(rss: i64, rtt: i64) -> i64 { + hexagon_S4_vxsubaddhr(rss, rtt) +} + +/// `Rdd32=vxsubaddw(Rss32,Rtt32):sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vxsubaddw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vxsubaddw_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_S4_vxsubaddw(rss, rtt) +} + +/// `Rd32=vasrhub(Rss32,#u4):rnd:sat` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vasrhub, IU4 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vasrhub_PI_rnd_sat(rss: i64) -> i32 { + static_assert_uimm_bits!(IU4, 4); + hexagon_S5_asrhub_rnd_sat_goodsyntax(rss, IU4 as i32) +} + +/// `Rd32=vasrhub(Rss32,#u4):sat` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vasrhub, IU4 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vasrhub_PI_sat(rss: i64) -> i32 { + static_assert_uimm_bits!(IU4, 4); + hexagon_S5_asrhub_sat(rss, IU4 as i32) +} + +/// `Rd32=popcount(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(popcount))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_popcount_P(rss: i64) -> i32 { + hexagon_S5_popcountp(rss) +} + +/// `Rdd32=vasrh(Rss32,#u4):rnd` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vasrh, IU4 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vasrh_PI_rnd(rss: i64) -> i64 { + static_assert_uimm_bits!(IU4, 4); + hexagon_S5_vasrhrnd_goodsyntax(rss, IU4 as i32) +} + +/// `dccleana(Rs32)` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(test, assert_instr(dccleana))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_dccleana_A(rs: i32) { + hexagon_Y2_dccleana(rs) +} + +/// `dccleaninva(Rs32)` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(test, assert_instr(dccleaninva))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_dccleaninva_A(rs: i32) { + hexagon_Y2_dccleaninva(rs) +} + +/// `dcfetch(Rs32)` +/// +/// Instruction Type: MAPPING +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(dcfetch))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_dcfetch_A(rs: i32) { + hexagon_Y2_dcfetch(rs) +} + +/// `dcinva(Rs32)` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(test, assert_instr(dcinva))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_dcinva_A(rs: i32) { + hexagon_Y2_dcinva(rs) +} + +/// `dczeroa(Rs32)` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(test, assert_instr(dczeroa))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_dczeroa_A(rs: i32) { + hexagon_Y2_dczeroa(rs) +} + +/// `l2fetch(Rs32,Rt32)` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(test, assert_instr(l2fetch))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_l2fetch_AR(rs: i32, rt: i32) { + hexagon_Y4_l2fetch(rs, rt) +} + +/// `l2fetch(Rs32,Rtt32)` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(test, assert_instr(l2fetch))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_l2fetch_AP(rs: i32, rtt: i64) { + hexagon_Y5_l2fetch(rs, rtt) +} + +/// `Rdd32=rol(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(rol, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_rol_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S6_rol_i_p(rss, IU6 as i32) +} + +/// `Rxx32+=rol(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(rol, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_rolacc_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S6_rol_i_p_acc(rxx, rss, IU6 as i32) +} + +/// `Rxx32&=rol(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(rol, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_roland_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S6_rol_i_p_and(rxx, rss, IU6 as i32) +} + +/// `Rxx32-=rol(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(rol, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_rolnac_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S6_rol_i_p_nac(rxx, rss, IU6 as i32) +} + +/// `Rxx32|=rol(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(rol, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_rolor_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S6_rol_i_p_or(rxx, rss, IU6 as i32) +} + +/// `Rxx32^=rol(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(rol, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_rolxacc_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S6_rol_i_p_xacc(rxx, rss, IU6 as i32) +} + +/// `Rd32=rol(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(rol, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_rol_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S6_rol_i_r(rs, IU5 as i32) +} + +/// `Rx32+=rol(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(rol, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_rolacc_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S6_rol_i_r_acc(rx, rs, IU5 as i32) +} + +/// `Rx32&=rol(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(rol, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_roland_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S6_rol_i_r_and(rx, rs, IU5 as i32) +} + +/// `Rx32-=rol(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(rol, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_rolnac_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S6_rol_i_r_nac(rx, rs, IU5 as i32) +} + +/// `Rx32|=rol(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(rol, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_rolor_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S6_rol_i_r_or(rx, rs, IU5 as i32) +} + +/// `Rx32^=rol(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(rol, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_rolxacc_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S6_rol_i_r_xacc(rx, rs, IU5 as i32) +} + +/// `Rdd32=vabsdiffb(Rtt32,Rss32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +/// Requires: V62 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))] +#[cfg_attr(test, assert_instr(vabsdiffb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vabsdiffb_PP(rtt: i64, rss: i64) -> i64 { + hexagon_M6_vabsdiffb(rtt, rss) +} + +/// `Rdd32=vabsdiffub(Rtt32,Rss32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +/// Requires: V62 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))] +#[cfg_attr(test, assert_instr(vabsdiffub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vabsdiffub_PP(rtt: i64, rss: i64) -> i64 { + hexagon_M6_vabsdiffub(rtt, rss) +} + +/// `Rdd32=vsplatb(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V62 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))] +#[cfg_attr(test, assert_instr(vsplatb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsplatb_R(rs: i32) -> i64 { + hexagon_S6_vsplatrbp(rs) +} + +/// `Rdd32=vtrunehb(Rss32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +/// Requires: V62 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))] +#[cfg_attr(test, assert_instr(vtrunehb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vtrunehb_PP(rss: i64, rtt: i64) -> i64 { + hexagon_S6_vtrunehb_ppp(rss, rtt) +} + +/// `Rdd32=vtrunohb(Rss32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +/// Requires: V62 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))] +#[cfg_attr(test, assert_instr(vtrunohb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vtrunohb_PP(rss: i64, rtt: i64) -> i64 { + hexagon_S6_vtrunohb_ppp(rss, rtt) +} + +/// `Pd4=!any8(vcmpb.eq(Rss32,Rtt32))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +/// Requires: V65 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_any8_vcmpb_eq_PP(rss: i64, rtt: i64) -> i32 { + hexagon_A6_vcmpbeq_notany(rss, rtt) +} + +/// `Rdd32=dfadd(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +/// Requires: V66 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v66"))] +#[cfg_attr(test, assert_instr(dfadd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_dfadd_PP(rss: f64, rtt: f64) -> f64 { + hexagon_F2_dfadd(rss, rtt) +} + +/// `Rdd32=dfsub(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +/// Requires: V66 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v66"))] +#[cfg_attr(test, assert_instr(dfsub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_dfsub_PP(rss: f64, rtt: f64) -> f64 { + hexagon_F2_dfsub(rss, rtt) +} + +/// `Rx32-=mpyi(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +/// Requires: V66 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v66"))] +#[cfg_attr(test, assert_instr(mpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyinac_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mnaci(rx, rs, rt) +} + +/// `Rd32=mask(#u5,#U5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V66 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v66"))] +#[rustc_legacy_const_generics(0, 1)] +#[cfg_attr(test, assert_instr(mask, IU5 = 0, IU5_2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mask_II() -> i32 { + static_assert_uimm_bits!(IU5, 5); + static_assert_uimm_bits!(IU5_2, 5); + hexagon_S2_mask(IU5 as i32, IU5_2 as i32) +} + +/// `Rd32=clip(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(clip, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_clip_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_A7_clip(rs, IU5 as i32) +} + +/// `Rdd32=cround(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cround, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cround_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_A7_croundd_ri(rss, IU6 as i32) +} + +/// `Rdd32=cround(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cround))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cround_PR(rss: i64, rt: i32) -> i64 { + hexagon_A7_croundd_rr(rss, rt) +} + +/// `Rdd32=vclip(Rss32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vclip, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vclip_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU5, 5); + hexagon_A7_vclip(rss, IU5 as i32) +} + +/// `Rdd32=dfmax(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +/// Requires: V67 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))] +#[cfg_attr(test, assert_instr(dfmax))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_dfmax_PP(rss: f64, rtt: f64) -> f64 { + hexagon_F2_dfmax(rss, rtt) +} + +/// `Rdd32=dfmin(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +/// Requires: V67 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))] +#[cfg_attr(test, assert_instr(dfmin))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_dfmin_PP(rss: f64, rtt: f64) -> f64 { + hexagon_F2_dfmin(rss, rtt) +} + +/// `Rdd32=dfmpyfix(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +/// Requires: V67 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))] +#[cfg_attr(test, assert_instr(dfmpyfix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_dfmpyfix_PP(rss: f64, rtt: f64) -> f64 { + hexagon_F2_dfmpyfix(rss, rtt) +} + +/// `Rxx32+=dfmpyhh(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +/// Requires: V67 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))] +#[cfg_attr(test, assert_instr(dfmpyhh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_dfmpyhhacc_PP(rxx: f64, rss: f64, rtt: f64) -> f64 { + hexagon_F2_dfmpyhh(rxx, rss, rtt) +} + +/// `Rxx32+=dfmpylh(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +/// Requires: V67 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))] +#[cfg_attr(test, assert_instr(dfmpylh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_dfmpylhacc_PP(rxx: f64, rss: f64, rtt: f64) -> f64 { + hexagon_F2_dfmpylh(rxx, rss, rtt) +} + +/// `Rdd32=dfmpyll(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +/// Requires: V67 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))] +#[cfg_attr(test, assert_instr(dfmpyll))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_dfmpyll_PP(rss: f64, rtt: f64) -> f64 { + hexagon_F2_dfmpyll(rss, rtt) +} + +/// `Rdd32=cmpyiw(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyiw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyiw_PP(rss: i64, rtt: i64) -> i64 { + hexagon_M7_dcmpyiw(rss, rtt) +} + +/// `Rxx32+=cmpyiw(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyiw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyiwacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M7_dcmpyiw_acc(rxx, rss, rtt) +} + +/// `Rdd32=cmpyiw(Rss32,Rtt32*)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyiw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyiw_PP_conj(rss: i64, rtt: i64) -> i64 { + hexagon_M7_dcmpyiwc(rss, rtt) +} + +/// `Rxx32+=cmpyiw(Rss32,Rtt32*)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyiw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyiwacc_PP_conj(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M7_dcmpyiwc_acc(rxx, rss, rtt) +} + +/// `Rdd32=cmpyrw(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyrw_PP(rss: i64, rtt: i64) -> i64 { + hexagon_M7_dcmpyrw(rss, rtt) +} + +/// `Rxx32+=cmpyrw(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyrwacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M7_dcmpyrw_acc(rxx, rss, rtt) +} + +/// `Rdd32=cmpyrw(Rss32,Rtt32*)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyrw_PP_conj(rss: i64, rtt: i64) -> i64 { + hexagon_M7_dcmpyrwc(rss, rtt) +} + +/// `Rxx32+=cmpyrw(Rss32,Rtt32*)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyrwacc_PP_conj(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M7_dcmpyrwc_acc(rxx, rss, rtt) +} + +/// `Rdd32=vdmpyw(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(vdmpyw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vdmpyw_PP(rss: i64, rtt: i64) -> i64 { + hexagon_M7_vdmpy(rss, rtt) +} + +/// `Rxx32+=vdmpyw(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(vdmpyw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vdmpywacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M7_vdmpy_acc(rxx, rss, rtt) +} + +/// `Rd32=cmpyiw(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyiw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyiw_PP_s1_sat(rss: i64, rtt: i64) -> i32 { + hexagon_M7_wcmpyiw(rss, rtt) +} + +/// `Rd32=cmpyiw(Rss32,Rtt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyiw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyiw_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i32 { + hexagon_M7_wcmpyiw_rnd(rss, rtt) +} + +/// `Rd32=cmpyiw(Rss32,Rtt32*):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyiw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyiw_PP_conj_s1_sat(rss: i64, rtt: i64) -> i32 { + hexagon_M7_wcmpyiwc(rss, rtt) +} + +/// `Rd32=cmpyiw(Rss32,Rtt32*):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyiw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyiw_PP_conj_s1_rnd_sat(rss: i64, rtt: i64) -> i32 { + hexagon_M7_wcmpyiwc_rnd(rss, rtt) +} + +/// `Rd32=cmpyrw(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyrw_PP_s1_sat(rss: i64, rtt: i64) -> i32 { + hexagon_M7_wcmpyrw(rss, rtt) +} + +/// `Rd32=cmpyrw(Rss32,Rtt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyrw_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i32 { + hexagon_M7_wcmpyrw_rnd(rss, rtt) +} + +/// `Rd32=cmpyrw(Rss32,Rtt32*):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyrw_PP_conj_s1_sat(rss: i64, rtt: i64) -> i32 { + hexagon_M7_wcmpyrwc(rss, rtt) +} + +/// `Rd32=cmpyrw(Rss32,Rtt32*):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyrw_PP_conj_s1_rnd_sat(rss: i64, rtt: i64) -> i32 { + hexagon_M7_wcmpyrwc_rnd(rss, rtt) +} + +/// `dmlink(Rs32,Rt32)` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +/// Requires: V68 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))] +#[cfg_attr(test, assert_instr(dmlink))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_dmlink_AA(rs: i32, rt: i32) { + hexagon_Y6_dmlink(rs, rt) +} + +/// `Rd32=dmpause` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +/// Requires: V68 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))] +#[cfg_attr(test, assert_instr(dmpause))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_dmpause() -> i32 { + hexagon_Y6_dmpause() +} + +/// `Rd32=dmpoll` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +/// Requires: V68 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))] +#[cfg_attr(test, assert_instr(dmpoll))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_dmpoll() -> i32 { + hexagon_Y6_dmpoll() +} + +/// `dmresume(Rs32)` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +/// Requires: V68 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))] +#[cfg_attr(test, assert_instr(dmresume))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_dmresume_A(rs: i32) { + hexagon_Y6_dmresume(rs) +} + +/// `dmstart(Rs32)` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +/// Requires: V68 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))] +#[cfg_attr(test, assert_instr(dmstart))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_dmstart_A(rs: i32) { + hexagon_Y6_dmstart(rs) +} + +/// `Rd32=dmwait` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +/// Requires: V68 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))] +#[cfg_attr(test, assert_instr(dmwait))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_dmwait() -> i32 { + hexagon_Y6_dmwait() +} diff --git a/library/stdarch/crates/core_arch/src/hexagon/v128.rs b/library/stdarch/crates/core_arch/src/hexagon/v128.rs new file mode 100644 index 0000000000000..1a1826ddda316 --- /dev/null +++ b/library/stdarch/crates/core_arch/src/hexagon/v128.rs @@ -0,0 +1,7503 @@ +// This code is automatically generated. DO NOT MODIFY. +//! Hexagon HVX 128-byte vector mode intrinsics +//! +//! This module provides intrinsics for the Hexagon Vector Extensions (HVX) +//! in 128-byte vector mode (1024-bit vectors). +//! +//! HVX is a wide vector extension designed for high-performance signal processing. +//! [Hexagon HVX Programmer's Reference Manual](https://docs.qualcomm.com/doc/80-N2040-61) +//! +//! ## Vector Types +//! +//! In 128-byte mode: +//! - `HvxVector` is 1024 bits (128 bytes) containing 32 x 32-bit values +//! - `HvxVectorPair` is 2048 bits (256 bytes) +//! - `HvxVectorPred` is 1024 bits (128 bytes) for predicate operations +//! +//! To use this module, compile with `-C target-feature=+hvx-length128b`. +//! +//! ## Naming Convention +//! +//! Function names preserve the original Q6 naming case because the convention +//! uses case to distinguish register types: +//! - `W` (uppercase) = vector pair (`HvxVectorPair`) +//! - `V` (uppercase) = vector (`HvxVector`) +//! - `Q` (uppercase) = predicate (`HvxVectorPred`) +//! - `R` = scalar register (`i32`) +//! +//! For example, `Q6_W_vcombine_VV` operates on a vector pair while +//! `Q6_V_hi_W` extracts a vector from a pair. +//! +//! ## Architecture Versions +//! +//! Different intrinsics require different HVX architecture versions. Use the +//! appropriate target feature to enable the required version: +//! - HVX v60: `-C target-feature=+hvxv60` (basic HVX operations) +//! - HVX v62: `-C target-feature=+hvxv62` +//! - HVX v65: `-C target-feature=+hvxv65` (includes floating-point support) +//! - HVX v66: `-C target-feature=+hvxv66` +//! - HVX v68: `-C target-feature=+hvxv68` +//! - HVX v69: `-C target-feature=+hvxv69` +//! - HVX v73: `-C target-feature=+hvxv73` +//! - HVX v79: `-C target-feature=+hvxv79` +//! +//! Each version includes all features from previous versions. + +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] + +#[cfg(test)] +use stdarch_test::assert_instr; + +use crate::intrinsics::simd::{simd_add, simd_and, simd_or, simd_sub, simd_xor}; + +// HVX type definitions for 128-byte vector mode +types! { + #![unstable(feature = "stdarch_hexagon", issue = "151523")] + + /// HVX vector type (1024 bits / 128 bytes) + /// + /// This type represents a single HVX vector register containing 32 x 32-bit values. + pub struct HvxVector(32 x i32); + + /// HVX vector pair type (2048 bits / 256 bytes) + /// + /// This type represents a pair of HVX vector registers, often used for + /// operations that produce double-width results. + pub struct HvxVectorPair(64 x i32); + + /// HVX vector predicate type (1024 bits / 128 bytes) + /// + /// This type represents a predicate vector used for conditional operations. + /// Each bit corresponds to a lane in the vector. + pub struct HvxVectorPred(32 x i32); +} + +// LLVM intrinsic declarations for 128-byte vector mode +#[allow(improper_ctypes)] +unsafe extern "unadjusted" { + #[link_name = "llvm.hexagon.V6.extractw.128B"] + fn extractw(_: HvxVector, _: i32) -> i32; + #[link_name = "llvm.hexagon.V6.get.qfext.128B"] + fn get_qfext(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.hi.128B"] + fn hi(_: HvxVectorPair) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lo.128B"] + fn lo(_: HvxVectorPair) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lvsplatb.128B"] + fn lvsplatb(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lvsplath.128B"] + fn lvsplath(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lvsplatw.128B"] + fn lvsplatw(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.and.128B"] + fn pred_and(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.and.n.128B"] + fn pred_and_n(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.not.128B"] + fn pred_not(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.or.128B"] + fn pred_or(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.or.n.128B"] + fn pred_or_n(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.scalar2.128B"] + fn pred_scalar2(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.scalar2v2.128B"] + fn pred_scalar2v2(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.xor.128B"] + fn pred_xor(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.set.qfext.128B"] + fn set_qfext(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.shuffeqh.128B"] + fn shuffeqh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.shuffeqw.128B"] + fn shuffeqw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.v6mpyhubs10.128B"] + fn v6mpyhubs10(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.v6mpyhubs10.vxx.128B"] + fn v6mpyhubs10_vxx( + _: HvxVectorPair, + _: HvxVectorPair, + _: HvxVectorPair, + _: i32, + ) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.v6mpyvubs10.128B"] + fn v6mpyvubs10(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.v6mpyvubs10.vxx.128B"] + fn v6mpyvubs10_vxx( + _: HvxVectorPair, + _: HvxVectorPair, + _: HvxVectorPair, + _: i32, + ) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vS32b.nqpred.ai.128B"] + fn vS32b_nqpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vS32b.nt.nqpred.ai.128B"] + fn vS32b_nt_nqpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vS32b.nt.qpred.ai.128B"] + fn vS32b_nt_qpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vS32b.qpred.ai.128B"] + fn vS32b_qpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vabs.f8.128B"] + fn vabs_f8(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabs.hf.128B"] + fn vabs_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabs.sf.128B"] + fn vabs_sf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsb.128B"] + fn vabsb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsb.sat.128B"] + fn vabsb_sat(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffh.128B"] + fn vabsdiffh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffub.128B"] + fn vabsdiffub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffuh.128B"] + fn vabsdiffuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffw.128B"] + fn vabsdiffw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsh.128B"] + fn vabsh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsh.sat.128B"] + fn vabsh_sat(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsw.128B"] + fn vabsw(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsw.sat.128B"] + fn vabsw_sat(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.hf.128B"] + fn vadd_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.hf.hf.128B"] + fn vadd_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf16.128B"] + fn vadd_qf16(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf16.mix.128B"] + fn vadd_qf16_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf32.128B"] + fn vadd_qf32(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf32.mix.128B"] + fn vadd_qf32_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.sf.128B"] + fn vadd_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.sf.hf.128B"] + fn vadd_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadd.sf.sf.128B"] + fn vadd_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddb.128B"] + fn vaddb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddb.dv.128B"] + fn vaddb_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddbnq.128B"] + fn vaddbnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddbq.128B"] + fn vaddbq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddbsat.128B"] + fn vaddbsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddbsat.dv.128B"] + fn vaddbsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddcarrysat.128B"] + fn vaddcarrysat(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddclbh.128B"] + fn vaddclbh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddclbw.128B"] + fn vaddclbw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddh.128B"] + fn vaddh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddh.dv.128B"] + fn vaddh_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddhnq.128B"] + fn vaddhnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddhq.128B"] + fn vaddhq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddhsat.128B"] + fn vaddhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddhsat.dv.128B"] + fn vaddhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddhw.128B"] + fn vaddhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddhw.acc.128B"] + fn vaddhw_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddubh.128B"] + fn vaddubh(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddubh.acc.128B"] + fn vaddubh_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddubsat.128B"] + fn vaddubsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddubsat.dv.128B"] + fn vaddubsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddububb.sat.128B"] + fn vaddububb_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadduhsat.128B"] + fn vadduhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadduhsat.dv.128B"] + fn vadduhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadduhw.128B"] + fn vadduhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadduhw.acc.128B"] + fn vadduhw_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadduwsat.128B"] + fn vadduwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadduwsat.dv.128B"] + fn vadduwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddw.128B"] + fn vaddw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddw.dv.128B"] + fn vaddw_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddwnq.128B"] + fn vaddwnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddwq.128B"] + fn vaddwq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddwsat.128B"] + fn vaddwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddwsat.dv.128B"] + fn vaddwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.valignb.128B"] + fn valignb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.valignbi.128B"] + fn valignbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vand.128B"] + fn vand(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandnqrt.128B"] + fn vandnqrt(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandnqrt.acc.128B"] + fn vandnqrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandqrt.128B"] + fn vandqrt(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandqrt.acc.128B"] + fn vandqrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvnqv.128B"] + fn vandvnqv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvqv.128B"] + fn vandvqv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvrt.128B"] + fn vandvrt(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvrt.acc.128B"] + fn vandvrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslh.128B"] + fn vaslh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslh.acc.128B"] + fn vaslh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslhv.128B"] + fn vaslhv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslw.128B"] + fn vaslw(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslw.acc.128B"] + fn vaslw_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslwv.128B"] + fn vaslwv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasr.into.128B"] + fn vasr_into(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vasrh.128B"] + fn vasrh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrh.acc.128B"] + fn vasrh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhbrndsat.128B"] + fn vasrhbrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhbsat.128B"] + fn vasrhbsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhubrndsat.128B"] + fn vasrhubrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhubsat.128B"] + fn vasrhubsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhv.128B"] + fn vasrhv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruhubrndsat.128B"] + fn vasruhubrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruhubsat.128B"] + fn vasruhubsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruwuhrndsat.128B"] + fn vasruwuhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruwuhsat.128B"] + fn vasruwuhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvuhubrndsat.128B"] + fn vasrvuhubrndsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvuhubsat.128B"] + fn vasrvuhubsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvwuhrndsat.128B"] + fn vasrvwuhrndsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvwuhsat.128B"] + fn vasrvwuhsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrw.128B"] + fn vasrw(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrw.acc.128B"] + fn vasrw_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwh.128B"] + fn vasrwh(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwhrndsat.128B"] + fn vasrwhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwhsat.128B"] + fn vasrwhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwuhrndsat.128B"] + fn vasrwuhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwuhsat.128B"] + fn vasrwuhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwv.128B"] + fn vasrwv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vassign.128B"] + fn vassign(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vassign.fp.128B"] + fn vassign_fp(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vassignp.128B"] + fn vassignp(_: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vavgb.128B"] + fn vavgb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgbrnd.128B"] + fn vavgbrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgh.128B"] + fn vavgh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavghrnd.128B"] + fn vavghrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgub.128B"] + fn vavgub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgubrnd.128B"] + fn vavgubrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguh.128B"] + fn vavguh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguhrnd.128B"] + fn vavguhrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguw.128B"] + fn vavguw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguwrnd.128B"] + fn vavguwrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgw.128B"] + fn vavgw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgwrnd.128B"] + fn vavgwrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcl0h.128B"] + fn vcl0h(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcl0w.128B"] + fn vcl0w(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcombine.128B"] + fn vcombine(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vconv.h.hf.128B"] + fn vconv_h_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.hf.h.128B"] + fn vconv_hf_h(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.hf.qf16.128B"] + fn vconv_hf_qf16(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.hf.qf32.128B"] + fn vconv_hf_qf32(_: HvxVectorPair) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.sf.qf32.128B"] + fn vconv_sf_qf32(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.sf.w.128B"] + fn vconv_sf_w(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.w.sf.128B"] + fn vconv_w_sf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt2.hf.b.128B"] + fn vcvt2_hf_b(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt2.hf.ub.128B"] + fn vcvt2_hf_ub(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.b.hf.128B"] + fn vcvt_b_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.h.hf.128B"] + fn vcvt_h_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.hf.b.128B"] + fn vcvt_hf_b(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.hf.f8.128B"] + fn vcvt_hf_f8(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.hf.h.128B"] + fn vcvt_hf_h(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.hf.sf.128B"] + fn vcvt_hf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.hf.ub.128B"] + fn vcvt_hf_ub(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.hf.uh.128B"] + fn vcvt_hf_uh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.sf.hf.128B"] + fn vcvt_sf_hf(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.ub.hf.128B"] + fn vcvt_ub_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.uh.hf.128B"] + fn vcvt_uh_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vd0.128B"] + fn vd0() -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdd0.128B"] + fn vdd0() -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdealb.128B"] + fn vdealb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdealb4w.128B"] + fn vdealb4w(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdealh.128B"] + fn vdealh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdealvdd.128B"] + fn vdealvdd(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdelta.128B"] + fn vdelta(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpy.sf.hf.128B"] + fn vdmpy_sf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpy.sf.hf.acc.128B"] + fn vdmpy_sf_hf_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpybus.128B"] + fn vdmpybus(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpybus.acc.128B"] + fn vdmpybus_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpybus.dv.128B"] + fn vdmpybus_dv(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpybus.dv.acc.128B"] + fn vdmpybus_dv_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpyhb.128B"] + fn vdmpyhb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhb.acc.128B"] + fn vdmpyhb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhb.dv.128B"] + fn vdmpyhb_dv(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpyhb.dv.acc.128B"] + fn vdmpyhb_dv_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpyhisat.128B"] + fn vdmpyhisat(_: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhisat.acc.128B"] + fn vdmpyhisat_acc(_: HvxVector, _: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsat.128B"] + fn vdmpyhsat(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsat.acc.128B"] + fn vdmpyhsat_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsuisat.128B"] + fn vdmpyhsuisat(_: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsuisat.acc.128B"] + fn vdmpyhsuisat_acc(_: HvxVector, _: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsusat.128B"] + fn vdmpyhsusat(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsusat.acc.128B"] + fn vdmpyhsusat_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhvsat.128B"] + fn vdmpyhvsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhvsat.acc.128B"] + fn vdmpyhvsat_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdsaduh.128B"] + fn vdsaduh(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdsaduh.acc.128B"] + fn vdsaduh_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.veqb.128B"] + fn veqb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqb.and.128B"] + fn veqb_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqb.or.128B"] + fn veqb_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqb.xor.128B"] + fn veqb_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh.128B"] + fn veqh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh.and.128B"] + fn veqh_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh.or.128B"] + fn veqh_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh.xor.128B"] + fn veqh_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw.128B"] + fn veqw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw.and.128B"] + fn veqw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw.or.128B"] + fn veqw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw.xor.128B"] + fn veqw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmax.f8.128B"] + fn vfmax_f8(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmax.hf.128B"] + fn vfmax_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmax.sf.128B"] + fn vfmax_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmin.f8.128B"] + fn vfmin_f8(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmin.hf.128B"] + fn vfmin_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmin.sf.128B"] + fn vfmin_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfneg.f8.128B"] + fn vfneg_f8(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfneg.hf.128B"] + fn vfneg_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfneg.sf.128B"] + fn vfneg_sf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgathermh.128B"] + fn vgathermh(_: *mut HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgathermhq.128B"] + fn vgathermhq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgathermhw.128B"] + fn vgathermhw(_: *mut HvxVector, _: i32, _: i32, _: HvxVectorPair) -> (); + #[link_name = "llvm.hexagon.V6.vgathermhwq.128B"] + fn vgathermhwq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVectorPair) -> (); + #[link_name = "llvm.hexagon.V6.vgathermw.128B"] + fn vgathermw(_: *mut HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgathermwq.128B"] + fn vgathermwq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgtb.128B"] + fn vgtb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtb.and.128B"] + fn vgtb_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtb.or.128B"] + fn vgtb_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtb.xor.128B"] + fn vgtb_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth.128B"] + fn vgth(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth.and.128B"] + fn vgth_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth.or.128B"] + fn vgth_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth.xor.128B"] + fn vgth_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf.128B"] + fn vgthf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf.and.128B"] + fn vgthf_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf.or.128B"] + fn vgthf_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf.xor.128B"] + fn vgthf_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf.128B"] + fn vgtsf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf.and.128B"] + fn vgtsf_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf.or.128B"] + fn vgtsf_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf.xor.128B"] + fn vgtsf_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub.128B"] + fn vgtub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub.and.128B"] + fn vgtub_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub.or.128B"] + fn vgtub_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub.xor.128B"] + fn vgtub_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh.128B"] + fn vgtuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh.and.128B"] + fn vgtuh_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh.or.128B"] + fn vgtuh_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh.xor.128B"] + fn vgtuh_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw.128B"] + fn vgtuw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw.and.128B"] + fn vgtuw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw.or.128B"] + fn vgtuw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw.xor.128B"] + fn vgtuw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw.128B"] + fn vgtw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw.and.128B"] + fn vgtw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw.or.128B"] + fn vgtw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw.xor.128B"] + fn vgtw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vinsertwr.128B"] + fn vinsertwr(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlalignb.128B"] + fn vlalignb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlalignbi.128B"] + fn vlalignbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrb.128B"] + fn vlsrb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrh.128B"] + fn vlsrh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrhv.128B"] + fn vlsrhv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrw.128B"] + fn vlsrw(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrwv.128B"] + fn vlsrwv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb.128B"] + fn vlutvvb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb.nm.128B"] + fn vlutvvb_nm(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb.oracc.128B"] + fn vlutvvb_oracc(_: HvxVector, _: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb.oracci.128B"] + fn vlutvvb_oracci(_: HvxVector, _: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvbi.128B"] + fn vlutvvbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvwh.128B"] + fn vlutvwh(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwh.nm.128B"] + fn vlutvwh_nm(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwh.oracc.128B"] + fn vlutvwh_oracc(_: HvxVectorPair, _: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwh.oracci.128B"] + fn vlutvwh_oracci(_: HvxVectorPair, _: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwhi.128B"] + fn vlutvwhi(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmax.hf.128B"] + fn vmax_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmax.sf.128B"] + fn vmax_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxb.128B"] + fn vmaxb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxh.128B"] + fn vmaxh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxub.128B"] + fn vmaxub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxuh.128B"] + fn vmaxuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxw.128B"] + fn vmaxw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmin.hf.128B"] + fn vmin_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmin.sf.128B"] + fn vmin_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminb.128B"] + fn vminb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminh.128B"] + fn vminh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminub.128B"] + fn vminub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminuh.128B"] + fn vminuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminw.128B"] + fn vminw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpabus.128B"] + fn vmpabus(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabus.acc.128B"] + fn vmpabus_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabusv.128B"] + fn vmpabusv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabuu.128B"] + fn vmpabuu(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabuu.acc.128B"] + fn vmpabuu_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabuuv.128B"] + fn vmpabuuv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpahb.128B"] + fn vmpahb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpahb.acc.128B"] + fn vmpahb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpauhb.128B"] + fn vmpauhb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpauhb.acc.128B"] + fn vmpauhb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.hf.hf.128B"] + fn vmpy_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.hf.hf.acc.128B"] + fn vmpy_hf_hf_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf16.128B"] + fn vmpy_qf16(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf16.hf.128B"] + fn vmpy_qf16_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf16.mix.hf.128B"] + fn vmpy_qf16_mix_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.128B"] + fn vmpy_qf32(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.hf.128B"] + fn vmpy_qf32_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.mix.hf.128B"] + fn vmpy_qf32_mix_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.qf16.128B"] + fn vmpy_qf32_qf16(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.sf.128B"] + fn vmpy_qf32_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.sf.hf.128B"] + fn vmpy_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.sf.hf.acc.128B"] + fn vmpy_sf_hf_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.sf.sf.128B"] + fn vmpy_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpybus.128B"] + fn vmpybus(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybus.acc.128B"] + fn vmpybus_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybusv.128B"] + fn vmpybusv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybusv.acc.128B"] + fn vmpybusv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybv.128B"] + fn vmpybv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybv.acc.128B"] + fn vmpybv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyewuh.128B"] + fn vmpyewuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyewuh.64.128B"] + fn vmpyewuh_64(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyh.128B"] + fn vmpyh(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyh.acc.128B"] + fn vmpyh_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhsat.acc.128B"] + fn vmpyhsat_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhsrs.128B"] + fn vmpyhsrs(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyhss.128B"] + fn vmpyhss(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyhus.128B"] + fn vmpyhus(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhus.acc.128B"] + fn vmpyhus_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhv.128B"] + fn vmpyhv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhv.acc.128B"] + fn vmpyhv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhvsrs.128B"] + fn vmpyhvsrs(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyieoh.128B"] + fn vmpyieoh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiewh.acc.128B"] + fn vmpyiewh_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiewuh.128B"] + fn vmpyiewuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiewuh.acc.128B"] + fn vmpyiewuh_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyih.128B"] + fn vmpyih(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyih.acc.128B"] + fn vmpyih_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyihb.128B"] + fn vmpyihb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyihb.acc.128B"] + fn vmpyihb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiowh.128B"] + fn vmpyiowh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwb.128B"] + fn vmpyiwb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwb.acc.128B"] + fn vmpyiwb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwh.128B"] + fn vmpyiwh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwh.acc.128B"] + fn vmpyiwh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwub.128B"] + fn vmpyiwub(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwub.acc.128B"] + fn vmpyiwub_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh.128B"] + fn vmpyowh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh.64.acc.128B"] + fn vmpyowh_64_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyowh.rnd.128B"] + fn vmpyowh_rnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh.rnd.sacc.128B"] + fn vmpyowh_rnd_sacc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh.sacc.128B"] + fn vmpyowh_sacc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyub.128B"] + fn vmpyub(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyub.acc.128B"] + fn vmpyub_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyubv.128B"] + fn vmpyubv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyubv.acc.128B"] + fn vmpyubv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuh.128B"] + fn vmpyuh(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuh.acc.128B"] + fn vmpyuh_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuhe.128B"] + fn vmpyuhe(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyuhe.acc.128B"] + fn vmpyuhe_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyuhv.128B"] + fn vmpyuhv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuhv.acc.128B"] + fn vmpyuhv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuhvs.128B"] + fn vmpyuhvs(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmux.128B"] + fn vmux(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgb.128B"] + fn vnavgb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgh.128B"] + fn vnavgh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgub.128B"] + fn vnavgub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgw.128B"] + fn vnavgw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnormamth.128B"] + fn vnormamth(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnormamtw.128B"] + fn vnormamtw(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnot.128B"] + fn vnot(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vor.128B"] + fn vor(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackeb.128B"] + fn vpackeb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackeh.128B"] + fn vpackeh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackhb.sat.128B"] + fn vpackhb_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackhub.sat.128B"] + fn vpackhub_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackob.128B"] + fn vpackob(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackoh.128B"] + fn vpackoh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackwh.sat.128B"] + fn vpackwh_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackwuh.sat.128B"] + fn vpackwuh_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpopcounth.128B"] + fn vpopcounth(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vprefixqb.128B"] + fn vprefixqb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vprefixqh.128B"] + fn vprefixqh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vprefixqw.128B"] + fn vprefixqw(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrdelta.128B"] + fn vrdelta(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybus.128B"] + fn vrmpybus(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybus.acc.128B"] + fn vrmpybus_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybusi.128B"] + fn vrmpybusi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpybusi.acc.128B"] + fn vrmpybusi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpybusv.128B"] + fn vrmpybusv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybusv.acc.128B"] + fn vrmpybusv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybv.128B"] + fn vrmpybv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybv.acc.128B"] + fn vrmpybv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyub.128B"] + fn vrmpyub(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyub.acc.128B"] + fn vrmpyub_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyubi.128B"] + fn vrmpyubi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpyubi.acc.128B"] + fn vrmpyubi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpyubv.128B"] + fn vrmpyubv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyubv.acc.128B"] + fn vrmpyubv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vror.128B"] + fn vror(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrotr.128B"] + fn vrotr(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundhb.128B"] + fn vroundhb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundhub.128B"] + fn vroundhub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrounduhub.128B"] + fn vrounduhub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrounduwuh.128B"] + fn vrounduwuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundwh.128B"] + fn vroundwh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundwuh.128B"] + fn vroundwuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrsadubi.128B"] + fn vrsadubi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrsadubi.acc.128B"] + fn vrsadubi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsatdw.128B"] + fn vsatdw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsathub.128B"] + fn vsathub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsatuwuh.128B"] + fn vsatuwuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsatwh.128B"] + fn vsatwh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsb.128B"] + fn vsb(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vscattermh.128B"] + fn vscattermh(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermh.add.128B"] + fn vscattermh_add(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhq.128B"] + fn vscattermhq(_: HvxVector, _: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhw.128B"] + fn vscattermhw(_: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhw.add.128B"] + fn vscattermhw_add(_: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhwq.128B"] + fn vscattermhwq(_: HvxVector, _: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermw.128B"] + fn vscattermw(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermw.add.128B"] + fn vscattermw_add(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermwq.128B"] + fn vscattermwq(_: HvxVector, _: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vsh.128B"] + fn vsh(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufeh.128B"] + fn vshufeh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffb.128B"] + fn vshuffb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffeb.128B"] + fn vshuffeb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffh.128B"] + fn vshuffh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffob.128B"] + fn vshuffob(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffvdd.128B"] + fn vshuffvdd(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufoeb.128B"] + fn vshufoeb(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufoeh.128B"] + fn vshufoeh(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufoh.128B"] + fn vshufoh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.hf.128B"] + fn vsub_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.hf.hf.128B"] + fn vsub_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf16.128B"] + fn vsub_qf16(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf16.mix.128B"] + fn vsub_qf16_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf32.128B"] + fn vsub_qf32(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf32.mix.128B"] + fn vsub_qf32_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.sf.128B"] + fn vsub_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.sf.hf.128B"] + fn vsub_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsub.sf.sf.128B"] + fn vsub_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubb.128B"] + fn vsubb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubb.dv.128B"] + fn vsubb_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubbnq.128B"] + fn vsubbnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubbq.128B"] + fn vsubbq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubbsat.128B"] + fn vsubbsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubbsat.dv.128B"] + fn vsubbsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubh.128B"] + fn vsubh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubh.dv.128B"] + fn vsubh_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubhnq.128B"] + fn vsubhnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubhq.128B"] + fn vsubhq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubhsat.128B"] + fn vsubhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubhsat.dv.128B"] + fn vsubhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubhw.128B"] + fn vsubhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsububh.128B"] + fn vsububh(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsububsat.128B"] + fn vsububsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsububsat.dv.128B"] + fn vsububsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubububb.sat.128B"] + fn vsubububb_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubuhsat.128B"] + fn vsubuhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubuhsat.dv.128B"] + fn vsubuhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubuhw.128B"] + fn vsubuhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubuwsat.128B"] + fn vsubuwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubuwsat.dv.128B"] + fn vsubuwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubw.128B"] + fn vsubw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubw.dv.128B"] + fn vsubw_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubwnq.128B"] + fn vsubwnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubwq.128B"] + fn vsubwq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubwsat.128B"] + fn vsubwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubwsat.dv.128B"] + fn vsubwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vswap.128B"] + fn vswap(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyb.128B"] + fn vtmpyb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyb.acc.128B"] + fn vtmpyb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpybus.128B"] + fn vtmpybus(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpybus.acc.128B"] + fn vtmpybus_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyhb.128B"] + fn vtmpyhb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyhb.acc.128B"] + fn vtmpyhb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackb.128B"] + fn vunpackb(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackh.128B"] + fn vunpackh(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackob.128B"] + fn vunpackob(_: HvxVectorPair, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackoh.128B"] + fn vunpackoh(_: HvxVectorPair, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackub.128B"] + fn vunpackub(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackuh.128B"] + fn vunpackuh(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vxor.128B"] + fn vxor(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vzb.128B"] + fn vzb(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vzh.128B"] + fn vzh(_: HvxVector) -> HvxVectorPair; +} + +/// `Rd32=vextract(Vu32,Rs32)` +/// +/// Instruction Type: LD +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(extractw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vextract_VR(vu: HvxVector, rs: i32) -> i32 { + extractw(vu, rs) +} + +/// `Vd32=hi(Vss32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(hi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_hi_W(vss: HvxVectorPair) -> HvxVector { + hi(vss) +} + +/// `Vd32=lo(Vss32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(lo))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_lo_W(vss: HvxVectorPair) -> HvxVector { + lo(vss) +} + +/// `Vd32=vsplat(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(lvsplatw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vsplat_R(rt: i32) -> HvxVector { + lvsplatw(rt) +} + +/// `Vd32.uh=vabsdiff(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vabsdiff_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffh(vu, vv) +} + +/// `Vd32.ub=vabsdiff(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vabsdiff_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffub(vu, vv) +} + +/// `Vd32.uh=vabsdiff(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vabsdiff_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffuh(vu, vv) +} + +/// `Vd32.uw=vabsdiff(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vabsdiff_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffw(vu, vv) +} + +/// `Vd32.h=vabs(Vu32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vabs_Vh(vu: HvxVector) -> HvxVector { + vabsh(vu) +} + +/// `Vd32.h=vabs(Vu32.h):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsh_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vabs_Vh_sat(vu: HvxVector) -> HvxVector { + vabsh_sat(vu) +} + +/// `Vd32.w=vabs(Vu32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vabs_Vw(vu: HvxVector) -> HvxVector { + vabsw(vu) +} + +/// `Vd32.w=vabs(Vu32.w):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsw_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vabs_Vw_sat(vu: HvxVector) -> HvxVector { + vabsw_sat(vu) +} + +/// `Vd32.b=vadd(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vadd_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddb(vu, vv) +} + +/// `Vdd32.b=vadd(Vuu32.b,Vvv32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddb_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wb_vadd_WbWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddb_dv(vuu, vvv) +} + +/// `Vd32.h=vadd(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vadd_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddh(vu, vv) +} + +/// `Vdd32.h=vadd(Vuu32.h,Vvv32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddh_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vadd_WhWh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddh_dv(vuu, vvv) +} + +/// `Vd32.h=vadd(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vadd_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddhsat(vu, vv) +} + +/// `Vdd32.h=vadd(Vuu32.h,Vvv32.h):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vadd_WhWh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vadd(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vadd_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vaddhw(vu, vv) +} + +/// `Vdd32.h=vadd(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vadd_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vaddubh(vu, vv) +} + +/// `Vd32.ub=vadd(Vu32.ub,Vv32.ub):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vadd_VubVub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddubsat(vu, vv) +} + +/// `Vdd32.ub=vadd(Vuu32.ub,Vvv32.ub):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddubsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wub_vadd_WubWub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddubsat_dv(vuu, vvv) +} + +/// `Vd32.uh=vadd(Vu32.uh,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vadduhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vadd_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadduhsat(vu, vv) +} + +/// `Vdd32.uh=vadd(Vuu32.uh,Vvv32.uh):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vadduhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuh_vadd_WuhWuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vadduhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vadd(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vadduhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vadd_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vadduhw(vu, vv) +} + +/// `Vd32.w=vadd(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vadd_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_add(vu, vv) +} + +/// `Vdd32.w=vadd(Vuu32.w,Vvv32.w)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddw_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vadd_WwWw(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddw_dv(vuu, vvv) +} + +/// `Vd32.w=vadd(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vadd_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddwsat(vu, vv) +} + +/// `Vdd32.w=vadd(Vuu32.w,Vvv32.w):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vadd_WwWw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddwsat_dv(vuu, vvv) +} + +/// `Vd32=valign(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(valignb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_valign_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + valignb(vu, vv, rt) +} + +/// `Vd32=valign(Vu32,Vv32,#u3)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(valignbi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_valign_VVI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { + valignbi(vu, vv, iu3) +} + +/// `Vd32=vand(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vand))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vand_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_and(vu, vv) +} + +/// `Vd32.h=vasl(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vasl_VhR(vu: HvxVector, rt: i32) -> HvxVector { + vaslh(vu, rt) +} + +/// `Vd32.h=vasl(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vasl_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaslhv(vu, vv) +} + +/// `Vd32.w=vasl(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vasl_VwR(vu: HvxVector, rt: i32) -> HvxVector { + vaslw(vu, rt) +} + +/// `Vx32.w+=vasl(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vaslacc_VwVwR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vaslw_acc(vx, vu, rt) +} + +/// `Vd32.w=vasl(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslwv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vasl_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaslwv(vu, vv) +} + +/// `Vd32.h=vasr(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vasr_VhR(vu: HvxVector, rt: i32) -> HvxVector { + vasrh(vu, rt) +} + +/// `Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhbrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vasr_VhVhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhbrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhubrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vasr_VhVhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhubrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vasr_VhVhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhubsat(vu, vv, rt) +} + +/// `Vd32.h=vasr(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vasr_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vasrhv(vu, vv) +} + +/// `Vd32.w=vasr(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vasr_VwR(vu: HvxVector, rt: i32) -> HvxVector { + vasrw(vu, rt) +} + +/// `Vx32.w+=vasr(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vasracc_VwVwR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vasrw_acc(vx, vu, rt) +} + +/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vasr_VwVwR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwh(vu, vv, rt) +} + +/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vasr_VwVwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwhrndsat(vu, vv, rt) +} + +/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vasr_VwVwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwhsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vasr_VwVwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwuhsat(vu, vv, rt) +} + +/// `Vd32.w=vasr(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vasr_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vasrwv(vu, vv) +} + +/// `Vd32=Vu32` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vassign))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_equals_V(vu: HvxVector) -> HvxVector { + vassign(vu) +} + +/// `Vdd32=Vuu32` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vassignp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_W_equals_W(vuu: HvxVectorPair) -> HvxVectorPair { + vassignp(vuu) +} + +/// `Vd32.h=vavg(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vavg_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgh(vu, vv) +} + +/// `Vd32.h=vavg(Vu32.h,Vv32.h):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavghrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vavg_VhVh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavghrnd(vu, vv) +} + +/// `Vd32.ub=vavg(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vavg_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgub(vu, vv) +} + +/// `Vd32.ub=vavg(Vu32.ub,Vv32.ub):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgubrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vavg_VubVub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgubrnd(vu, vv) +} + +/// `Vd32.uh=vavg(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavguh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vavg_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguh(vu, vv) +} + +/// `Vd32.uh=vavg(Vu32.uh,Vv32.uh):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavguhrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vavg_VuhVuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguhrnd(vu, vv) +} + +/// `Vd32.w=vavg(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vavg_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgw(vu, vv) +} + +/// `Vd32.w=vavg(Vu32.w,Vv32.w):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgwrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vavg_VwVw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgwrnd(vu, vv) +} + +/// `Vd32.uh=vcl0(Vu32.uh)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vcl0h))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vcl0_Vuh(vu: HvxVector) -> HvxVector { + vcl0h(vu) +} + +/// `Vd32.uw=vcl0(Vu32.uw)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vcl0w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vcl0_Vuw(vu: HvxVector) -> HvxVector { + vcl0w(vu) +} + +/// `Vdd32=vcombine(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vcombine))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_W_vcombine_VV(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vcombine(vu, vv) +} + +/// `Vd32=#0` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vd0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vzero() -> HvxVector { + vd0() +} + +/// `Vd32.b=vdeal(Vu32.b)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vdeal_Vb(vu: HvxVector) -> HvxVector { + vdealb(vu) +} + +/// `Vd32.b=vdeale(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealb4w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vdeale_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdealb4w(vu, vv) +} + +/// `Vd32.h=vdeal(Vu32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vdeal_Vh(vu: HvxVector) -> HvxVector { + vdealh(vu) +} + +/// `Vdd32=vdeal(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealvdd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_W_vdeal_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vdealvdd(vu, vv, rt) +} + +/// `Vd32=vdelta(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdelta))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vdelta_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdelta(vu, vv) +} + +/// `Vd32.h=vdmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vdmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVector { + vdmpybus(vu, rt) +} + +/// `Vx32.h+=vdmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vdmpyacc_VhVubRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpybus_acc(vx, vu, rt) +} + +/// `Vdd32.h=vdmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vdmpy_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vdmpybus_dv(vuu, rt) +} + +/// `Vxx32.h+=vdmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus_dv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vdmpyacc_WhWubRb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vdmpybus_dv_acc(vxx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpy_VhRb(vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhb(vu, rt) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpyacc_VwVhRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhb_acc(vx, vu, rt) +} + +/// `Vdd32.w=vdmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vdmpy_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vdmpyhb_dv(vuu, rt) +} + +/// `Vxx32.w+=vdmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb_dv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vdmpyacc_WwWhRb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vdmpyhb_dv_acc(vxx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vuu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhisat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpy_WhRh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhisat(vuu, rt) +} + +/// `Vx32.w+=vdmpy(Vuu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhisat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpyacc_VwWhRh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhisat_acc(vx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpy_VhRh_sat(vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsat(vu, rt) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpyacc_VwVhRh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsat_acc(vx, vu, rt) +} + +/// `Vd32.w=vdmpy(Vuu32.h,Rt32.uh,#1):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsuisat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpy_WhRuh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhsuisat(vuu, rt) +} + +/// `Vx32.w+=vdmpy(Vuu32.h,Rt32.uh,#1):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsuisat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpyacc_VwWhRuh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhsuisat_acc(vx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Rt32.uh):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsusat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpy_VhRuh_sat(vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsusat(vu, rt) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Rt32.uh):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsusat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpyacc_VwVhRuh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsusat_acc(vx, vu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhvsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpy_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpyhvsat(vu, vv) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhvsat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpyacc_VwVhVh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpyhvsat_acc(vx, vu, vv) +} + +/// `Vdd32.uw=vdsad(Vuu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdsaduh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vdsad_WuhRuh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vdsaduh(vuu, rt) +} + +/// `Vxx32.uw+=vdsad(Vuu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdsaduh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vdsadacc_WuwWuhRuh( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vdsaduh_acc(vxx, vuu, rt) +} + +/// `Vx32.w=vinsert(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vinsertwr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vinsert_VwR(vx: HvxVector, rt: i32) -> HvxVector { + vinsertwr(vx, rt) +} + +/// `Vd32=vlalign(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlalignb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vlalign_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vlalignb(vu, vv, rt) +} + +/// `Vd32=vlalign(Vu32,Vv32,#u3)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlalignbi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vlalign_VVI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { + vlalignbi(vu, vv, iu3) +} + +/// `Vd32.uh=vlsr(Vu32.uh,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vlsr_VuhR(vu: HvxVector, rt: i32) -> HvxVector { + vlsrh(vu, rt) +} + +/// `Vd32.h=vlsr(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vlsr_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vlsrhv(vu, vv) +} + +/// `Vd32.uw=vlsr(Vu32.uw,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vlsr_VuwR(vu: HvxVector, rt: i32) -> HvxVector { + vlsrw(vu, rt) +} + +/// `Vd32.w=vlsr(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrwv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vlsr_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vlsrwv(vu, vv) +} + +/// `Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvvb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vlut32_VbVbR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vlutvvb(vu, vv, rt) +} + +/// `Vx32.b|=vlut32(Vu32.b,Vv32.b,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvvb_oracc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vlut32or_VbVbVbR( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, + rt: i32, +) -> HvxVector { + vlutvvb_oracc(vx, vu, vv, rt) +} + +/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vlut16_VbVhR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vlutvwh(vu, vv, rt) +} + +/// `Vxx32.h|=vlut16(Vu32.b,Vv32.h,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvwh_oracc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vlut16or_WhVbVhR( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, + rt: i32, +) -> HvxVectorPair { + vlutvwh_oracc(vxx, vu, vv, rt) +} + +/// `Vd32.h=vmax(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vmax_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxh(vu, vv) +} + +/// `Vd32.ub=vmax(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vmax_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxub(vu, vv) +} + +/// `Vd32.uh=vmax(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vmax_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxuh(vu, vv) +} + +/// `Vd32.w=vmax(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmax_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxw(vu, vv) +} + +/// `Vd32.h=vmin(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vmin_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminh(vu, vv) +} + +/// `Vd32.ub=vmin(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vmin_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminub(vu, vv) +} + +/// `Vd32.uh=vmin(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vmin_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminuh(vu, vv) +} + +/// `Vd32.w=vmin(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmin_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminw(vu, vv) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpa_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpabus(vuu, rt) +} + +/// `Vxx32.h+=vmpa(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpaacc_WhWubRb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpabus_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Vvv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabusv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpa_WubWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vmpabusv(vuu, vvv) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Vvv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabuuv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpa_WubWub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vmpabuuv(vuu, vvv) +} + +/// `Vdd32.w=vmpa(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpahb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vmpa_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpahb(vuu, rt) +} + +/// `Vxx32.w+=vmpa(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpahb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vmpaacc_WwWhRb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpahb_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpybus(vu, rt) +} + +/// `Vxx32.h+=vmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpyacc_WhVubRb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpybus_acc(vxx, vu, rt) +} + +/// `Vdd32.h=vmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybusv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpy_VubVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpybusv(vu, vv) +} + +/// `Vxx32.h+=vmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybusv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpyacc_WhVubVb( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpybusv_acc(vxx, vu, vv) +} + +/// `Vdd32.h=vmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpy_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpybv(vu, vv) +} + +/// `Vxx32.h+=vmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpyacc_WhVbVb( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpybv_acc(vxx, vu, vv) +} + +/// `Vd32.w=vmpye(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyewuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpye_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyewuh(vu, vv) +} + +/// `Vdd32.w=vmpy(Vu32.h,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vmpy_VhRh(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyh(vu, rt) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhsat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vmpyacc_WwVhRh_sat( + vxx: HvxVectorPair, + vu: HvxVector, + rt: i32, +) -> HvxVectorPair { + vmpyhsat_acc(vxx, vu, rt) +} + +/// `Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:rnd:sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhsrs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vmpy_VhRh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector { + vmpyhsrs(vu, rt) +} + +/// `Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhss))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vmpy_VhRh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector { + vmpyhss(vu, rt) +} + +/// `Vdd32.w=vmpy(Vu32.h,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vmpy_VhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyhus(vu, vv) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vmpyacc_WwVhVuh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyhus_acc(vxx, vu, vv) +} + +/// `Vdd32.w=vmpy(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vmpy_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyhv(vu, vv) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vmpyacc_WwVhVh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyhv_acc(vxx, vu, vv) +} + +/// `Vd32.h=vmpy(Vu32.h,Vv32.h):<<1:rnd:sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhvsrs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vmpy_VhVh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyhvsrs(vu, vv) +} + +/// `Vd32.w=vmpyieo(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyieoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyieo_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyieoh(vu, vv) +} + +/// `Vx32.w+=vmpyie(Vu32.w,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiewh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyieacc_VwVwVh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiewh_acc(vx, vu, vv) +} + +/// `Vd32.w=vmpyie(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiewuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyie_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiewuh(vu, vv) +} + +/// `Vx32.w+=vmpyie(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiewuh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyieacc_VwVwVuh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiewuh_acc(vx, vu, vv) +} + +/// `Vd32.h=vmpyi(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyih))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vmpyi_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyih(vu, vv) +} + +/// `Vx32.h+=vmpyi(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyih_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vmpyiacc_VhVhVh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyih_acc(vx, vu, vv) +} + +/// `Vd32.h=vmpyi(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyihb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vmpyi_VhRb(vu: HvxVector, rt: i32) -> HvxVector { + vmpyihb(vu, rt) +} + +/// `Vx32.h+=vmpyi(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyihb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vmpyiacc_VhVhRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyihb_acc(vx, vu, rt) +} + +/// `Vd32.w=vmpyio(Vu32.w,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiowh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyio_VwVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiowh(vu, vv) +} + +/// `Vd32.w=vmpyi(Vu32.w,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyi_VwRb(vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwb(vu, rt) +} + +/// `Vx32.w+=vmpyi(Vu32.w,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyiacc_VwVwRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwb_acc(vx, vu, rt) +} + +/// `Vd32.w=vmpyi(Vu32.w,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyi_VwRh(vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwh(vu, rt) +} + +/// `Vx32.w+=vmpyi(Vu32.w,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyiacc_VwVwRh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwh_acc(vx, vu, rt) +} + +/// `Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyo_VwVh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyowh(vu, vv) +} + +/// `Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh_rnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyo_VwVh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyowh_rnd(vu, vv) +} + +/// `Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat:shift` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh_rnd_sacc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, +) -> HvxVector { + vmpyowh_rnd_sacc(vx, vu, vv) +} + +/// `Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:sat:shift` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh_sacc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, +) -> HvxVector { + vmpyowh_sacc(vx, vu, vv) +} + +/// `Vdd32.uh=vmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuh_vmpy_VubRub(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyub(vu, rt) +} + +/// `Vxx32.uh+=vmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyub_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuh_vmpyacc_WuhVubRub( + vxx: HvxVectorPair, + vu: HvxVector, + rt: i32, +) -> HvxVectorPair { + vmpyub_acc(vxx, vu, rt) +} + +/// `Vdd32.uh=vmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyubv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuh_vmpy_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyubv(vu, vv) +} + +/// `Vxx32.uh+=vmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyubv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuh_vmpyacc_WuhVubVub( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyubv_acc(vxx, vu, vv) +} + +/// `Vdd32.uw=vmpy(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vmpy_VuhRuh(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyuh(vu, rt) +} + +/// `Vxx32.uw+=vmpy(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vmpyacc_WuwVuhRuh( + vxx: HvxVectorPair, + vu: HvxVector, + rt: i32, +) -> HvxVectorPair { + vmpyuh_acc(vxx, vu, rt) +} + +/// `Vdd32.uw=vmpy(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vmpy_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyuhv(vu, vv) +} + +/// `Vxx32.uw+=vmpy(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuhv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vmpyacc_WuwVuhVuh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyuhv_acc(vxx, vu, vv) +} + +/// `Vd32.h=vnavg(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vnavg_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgh(vu, vv) +} + +/// `Vd32.b=vnavg(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnavgub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vnavg_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgub(vu, vv) +} + +/// `Vd32.w=vnavg(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vnavg_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgw(vu, vv) +} + +/// `Vd32.h=vnormamt(Vu32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnormamth))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vnormamt_Vh(vu: HvxVector) -> HvxVector { + vnormamth(vu) +} + +/// `Vd32.w=vnormamt(Vu32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnormamtw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vnormamt_Vw(vu: HvxVector) -> HvxVector { + vnormamtw(vu) +} + +/// `Vd32=vnot(Vu32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnot))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vnot_V(vu: HvxVector) -> HvxVector { + vnot(vu) +} + +/// `Vd32=vor(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vor_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_or(vu, vv) +} + +/// `Vd32.b=vpacke(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackeb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vpacke_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackeb(vu, vv) +} + +/// `Vd32.h=vpacke(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vpacke_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackeh(vu, vv) +} + +/// `Vd32.b=vpack(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackhb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vpack_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackhb_sat(vu, vv) +} + +/// `Vd32.ub=vpack(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackhub_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vpack_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackhub_sat(vu, vv) +} + +/// `Vd32.b=vpacko(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackob))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vpacko_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackob(vu, vv) +} + +/// `Vd32.h=vpacko(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vpacko_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackoh(vu, vv) +} + +/// `Vd32.h=vpack(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackwh_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vpack_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackwh_sat(vu, vv) +} + +/// `Vd32.uh=vpack(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackwuh_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vpack_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackwuh_sat(vu, vv) +} + +/// `Vd32.h=vpopcount(Vu32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpopcounth))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vpopcount_Vh(vu: HvxVector) -> HvxVector { + vpopcounth(vu) +} + +/// `Vd32=vrdelta(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrdelta))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vrdelta_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrdelta(vu, vv) +} + +/// `Vd32.w=vrmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vrmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVector { + vrmpybus(vu, rt) +} + +/// `Vx32.w+=vrmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vrmpyacc_VwVubRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vrmpybus_acc(vx, vu, rt) +} + +/// `Vdd32.w=vrmpy(Vuu32.ub,Rt32.b,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vrmpy_WubRbI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { + vrmpybusi(vuu, rt, iu1) +} + +/// `Vxx32.w+=vrmpy(Vuu32.ub,Rt32.b,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusi_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vrmpyacc_WwWubRbI( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, + iu1: i32, +) -> HvxVectorPair { + vrmpybusi_acc(vxx, vuu, rt, iu1) +} + +/// `Vd32.w=vrmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vrmpy_VubVb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybusv(vu, vv) +} + +/// `Vx32.w+=vrmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vrmpyacc_VwVubVb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybusv_acc(vx, vu, vv) +} + +/// `Vd32.w=vrmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vrmpy_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybv(vu, vv) +} + +/// `Vx32.w+=vrmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vrmpyacc_VwVbVb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybv_acc(vx, vu, vv) +} + +/// `Vd32.uw=vrmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vrmpy_VubRub(vu: HvxVector, rt: i32) -> HvxVector { + vrmpyub(vu, rt) +} + +/// `Vx32.uw+=vrmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyub_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vrmpyacc_VuwVubRub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vrmpyub_acc(vx, vu, rt) +} + +/// `Vdd32.uw=vrmpy(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vrmpy_WubRubI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { + vrmpyubi(vuu, rt, iu1) +} + +/// `Vxx32.uw+=vrmpy(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubi_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vrmpyacc_WuwWubRubI( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, + iu1: i32, +) -> HvxVectorPair { + vrmpyubi_acc(vxx, vuu, rt, iu1) +} + +/// `Vd32.uw=vrmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vrmpy_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpyubv(vu, vv) +} + +/// `Vx32.uw+=vrmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vrmpyacc_VuwVubVub(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpyubv_acc(vx, vu, vv) +} + +/// `Vd32=vror(Vu32,Rt32)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vror))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vror_VR(vu: HvxVector, rt: i32) -> HvxVector { + vror(vu, rt) +} + +/// `Vd32.b=vround(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vround_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundhb(vu, vv) +} + +/// `Vd32.ub=vround(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundhub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vround_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundhub(vu, vv) +} + +/// `Vd32.h=vround(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vround_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundwh(vu, vv) +} + +/// `Vd32.uh=vround(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundwuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vround_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundwuh(vu, vv) +} + +/// `Vdd32.uw=vrsad(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrsadubi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vrsad_WubRubI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { + vrsadubi(vuu, rt, iu1) +} + +/// `Vxx32.uw+=vrsad(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrsadubi_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vrsadacc_WuwWubRubI( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, + iu1: i32, +) -> HvxVectorPair { + vrsadubi_acc(vxx, vuu, rt, iu1) +} + +/// `Vd32.ub=vsat(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsathub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vsat_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsathub(vu, vv) +} + +/// `Vd32.h=vsat(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsatwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vsat_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsatwh(vu, vv) +} + +/// `Vdd32.h=vsxt(Vu32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vsxt_Vb(vu: HvxVector) -> HvxVectorPair { + vsb(vu) +} + +/// `Vdd32.w=vsxt(Vu32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vsxt_Vh(vu: HvxVector) -> HvxVectorPair { + vsh(vu) +} + +/// `Vd32.h=vshuffe(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vshuffe_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshufeh(vu, vv) +} + +/// `Vd32.b=vshuff(Vu32.b)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vshuff_Vb(vu: HvxVector) -> HvxVector { + vshuffb(vu) +} + +/// `Vd32.b=vshuffe(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffeb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vshuffe_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshuffeb(vu, vv) +} + +/// `Vd32.h=vshuff(Vu32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vshuff_Vh(vu: HvxVector) -> HvxVector { + vshuffh(vu) +} + +/// `Vd32.b=vshuffo(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffob))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vshuffo_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshuffob(vu, vv) +} + +/// `Vdd32=vshuff(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffvdd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_W_vshuff_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vshuffvdd(vu, vv, rt) +} + +/// `Vdd32.b=vshuffoe(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufoeb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wb_vshuffoe_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vshufoeb(vu, vv) +} + +/// `Vdd32.h=vshuffoe(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufoeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vshuffoe_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vshufoeh(vu, vv) +} + +/// `Vd32.h=vshuffo(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vshuffo_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshufoh(vu, vv) +} + +/// `Vd32.b=vsub(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vsub_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubb(vu, vv) +} + +/// `Vdd32.b=vsub(Vuu32.b,Vvv32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubb_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wb_vsub_WbWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubb_dv(vuu, vvv) +} + +/// `Vd32.h=vsub(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vsub_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubh(vu, vv) +} + +/// `Vdd32.h=vsub(Vuu32.h,Vvv32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubh_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vsub_WhWh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubh_dv(vuu, vvv) +} + +/// `Vd32.h=vsub(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vsub_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubhsat(vu, vv) +} + +/// `Vdd32.h=vsub(Vuu32.h,Vvv32.h):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vsub_WhWh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vsub(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vsub_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsubhw(vu, vv) +} + +/// `Vdd32.h=vsub(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsububh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vsub_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsububh(vu, vv) +} + +/// `Vd32.ub=vsub(Vu32.ub,Vv32.ub):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsububsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vsub_VubVub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsububsat(vu, vv) +} + +/// `Vdd32.ub=vsub(Vuu32.ub,Vvv32.ub):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsububsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wub_vsub_WubWub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsububsat_dv(vuu, vvv) +} + +/// `Vd32.uh=vsub(Vu32.uh,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vsub_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubuhsat(vu, vv) +} + +/// `Vdd32.uh=vsub(Vuu32.uh,Vvv32.uh):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubuhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuh_vsub_WuhWuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubuhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vsub(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubuhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vsub_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsubuhw(vu, vv) +} + +/// `Vd32.w=vsub(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vsub_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_sub(vu, vv) +} + +/// `Vdd32.w=vsub(Vuu32.w,Vvv32.w)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubw_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vsub_WwWw(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubw_dv(vuu, vvv) +} + +/// `Vd32.w=vsub(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vsub_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubwsat(vu, vv) +} + +/// `Vdd32.w=vsub(Vuu32.w,Vvv32.w):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vsub_WwWw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubwsat_dv(vuu, vvv) +} + +/// `Vdd32.h=vtmpy(Vuu32.b,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vtmpy_WbRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vtmpyb(vuu, rt) +} + +/// `Vxx32.h+=vtmpy(Vuu32.b,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vtmpyacc_WhWbRb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vtmpyb_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vtmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vtmpy_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vtmpybus(vuu, rt) +} + +/// `Vxx32.h+=vtmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vtmpyacc_WhWubRb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vtmpybus_acc(vxx, vuu, rt) +} + +/// `Vdd32.w=vtmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vtmpy_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vtmpyhb(vuu, rt) +} + +/// `Vxx32.w+=vtmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyhb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vtmpyacc_WwWhRb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vtmpyhb_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vunpack(Vu32.b)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vunpack_Vb(vu: HvxVector) -> HvxVectorPair { + vunpackb(vu) +} + +/// `Vdd32.w=vunpack(Vu32.h)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vunpack_Vh(vu: HvxVector) -> HvxVectorPair { + vunpackh(vu) +} + +/// `Vxx32.h|=vunpacko(Vu32.b)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackob))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vunpackoor_WhVb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { + vunpackob(vxx, vu) +} + +/// `Vxx32.w|=vunpacko(Vu32.h)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vunpackoor_WwVh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { + vunpackoh(vxx, vu) +} + +/// `Vdd32.uh=vunpack(Vu32.ub)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuh_vunpack_Vub(vu: HvxVector) -> HvxVectorPair { + vunpackub(vu) +} + +/// `Vdd32.uw=vunpack(Vu32.uh)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vunpack_Vuh(vu: HvxVector) -> HvxVectorPair { + vunpackuh(vu) +} + +/// `Vd32=vxor(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vxor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vxor_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_xor(vu, vv) +} + +/// `Vdd32.uh=vzxt(Vu32.ub)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vzb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuh_vzxt_Vub(vu: HvxVector) -> HvxVectorPair { + vzb(vu) +} + +/// `Vdd32.uw=vzxt(Vu32.uh)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vzh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vzxt_Vuh(vu: HvxVector) -> HvxVectorPair { + vzh(vu) +} + +/// `Vd32.b=vsplat(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(lvsplatb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vsplat_R(rt: i32) -> HvxVector { + lvsplatb(rt) +} + +/// `Vd32.h=vsplat(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(lvsplath))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vsplat_R(rt: i32) -> HvxVector { + lvsplath(rt) +} + +/// `Vd32.b=vadd(Vu32.b,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddbsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vadd_VbVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddbsat(vu, vv) +} + +/// `Vdd32.b=vadd(Vuu32.b,Vvv32.b):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddbsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wb_vadd_WbWb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddbsat_dv(vuu, vvv) +} + +/// `Vd32.h=vadd(vclb(Vu32.h),Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddclbh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vadd_vclb_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddclbh(vu, vv) +} + +/// `Vd32.w=vadd(vclb(Vu32.w),Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddclbw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vadd_vclb_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddclbw(vu, vv) +} + +/// `Vxx32.w+=vadd(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddhw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vaddacc_WwVhVh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vaddhw_acc(vxx, vu, vv) +} + +/// `Vxx32.h+=vadd(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddubh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vaddacc_WhVubVub( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vaddubh_acc(vxx, vu, vv) +} + +/// `Vd32.ub=vadd(Vu32.ub,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddububb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vadd_VubVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddububb_sat(vu, vv) +} + +/// `Vxx32.w+=vadd(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vadduhw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vaddacc_WwVuhVuh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vadduhw_acc(vxx, vu, vv) +} + +/// `Vd32.uw=vadd(Vu32.uw,Vv32.uw):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vadduwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vadd_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadduwsat(vu, vv) +} + +/// `Vdd32.uw=vadd(Vuu32.uw,Vvv32.uw):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vadduwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vadd_WuwWuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vadduwsat_dv(vuu, vvv) +} + +/// `Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vasrhbsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vasr_VhVhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhbsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vasruwuhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vasr_VuwVuwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruwuhrndsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vasrwuhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vasr_VwVwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwuhrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vlsr(Vu32.ub,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlsrb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vlsr_VubR(vu: HvxVector, rt: i32) -> HvxVector { + vlsrb(vu, rt) +} + +/// `Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8):nomatch` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvvb_nm))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vlut32_VbVbR_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vlutvvb_nm(vu, vv, rt) +} + +/// `Vx32.b|=vlut32(Vu32.b,Vv32.b,#u3)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvvb_oracci))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vlut32or_VbVbVbI( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, + iu3: i32, +) -> HvxVector { + vlutvvb_oracci(vx, vu, vv, iu3) +} + +/// `Vd32.b=vlut32(Vu32.b,Vv32.b,#u3)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvvbi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vlut32_VbVbI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { + vlutvvbi(vu, vv, iu3) +} + +/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8):nomatch` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvwh_nm))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vlut16_VbVhR_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vlutvwh_nm(vu, vv, rt) +} + +/// `Vxx32.h|=vlut16(Vu32.b,Vv32.h,#u3)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvwh_oracci))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vlut16or_WhVbVhI( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, + iu3: i32, +) -> HvxVectorPair { + vlutvwh_oracci(vxx, vu, vv, iu3) +} + +/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,#u3)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvwhi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vlut16_VbVhI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVectorPair { + vlutvwhi(vu, vv, iu3) +} + +/// `Vd32.b=vmax(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmaxb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vmax_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxb(vu, vv) +} + +/// `Vd32.b=vmin(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vminb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vmin_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminb(vu, vv) +} + +/// `Vdd32.w=vmpa(Vuu32.uh,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpauhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vmpa_WuhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpauhb(vuu, rt) +} + +/// `Vxx32.w+=vmpa(Vuu32.uh,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpauhb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vmpaacc_WwWuhRb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpauhb_acc(vxx, vuu, rt) +} + +/// `Vdd32=vmpye(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyewuh_64))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_W_vmpye_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyewuh_64(vu, vv) +} + +/// `Vd32.w=vmpyi(Vu32.w,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyiwub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyi_VwRub(vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwub(vu, rt) +} + +/// `Vx32.w+=vmpyi(Vu32.w,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyiwub_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyiacc_VwVwRub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwub_acc(vx, vu, rt) +} + +/// `Vxx32+=vmpyo(Vu32.w,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyowh_64_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_W_vmpyoacc_WVwVh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyowh_64_acc(vxx, vu, vv) +} + +/// `Vd32.ub=vround(Vu32.uh,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vrounduhub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vround_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrounduhub(vu, vv) +} + +/// `Vd32.uh=vround(Vu32.uw,Vv32.uw):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vrounduwuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vround_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrounduwuh(vu, vv) +} + +/// `Vd32.uh=vsat(Vu32.uw,Vv32.uw)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsatuwuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vsat_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsatuwuh(vu, vv) +} + +/// `Vd32.b=vsub(Vu32.b,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubbsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vsub_VbVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubbsat(vu, vv) +} + +/// `Vdd32.b=vsub(Vuu32.b,Vvv32.b):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubbsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wb_vsub_WbWb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubbsat_dv(vuu, vvv) +} + +/// `Vd32.ub=vsub(Vu32.ub,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubububb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vsub_VubVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubububb_sat(vu, vv) +} + +/// `Vd32.uw=vsub(Vu32.uw,Vv32.uw):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubuwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vsub_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubuwsat(vu, vv) +} + +/// `Vdd32.uw=vsub(Vuu32.uw,Vvv32.uw):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubuwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vsub_WuwWuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubuwsat_dv(vuu, vvv) +} + +/// `Vd32.b=vabs(Vu32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vabsb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vabs_Vb(vu: HvxVector) -> HvxVector { + vabsb(vu) +} + +/// `Vd32.b=vabs(Vu32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vabsb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vabs_Vb_sat(vu: HvxVector) -> HvxVector { + vabsb_sat(vu) +} + +/// `Vx32.h+=vasl(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vaslh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vaslacc_VhVhR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vaslh_acc(vx, vu, rt) +} + +/// `Vx32.h+=vasr(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasrh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vasracc_VhVhR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vasrh_acc(vx, vu, rt) +} + +/// `Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasruhubrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vasr_VuhVuhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruhubrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasruhubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vasr_VuhVuhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruhubsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasruwuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vasr_VuwVuwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruwuhsat(vu, vv, rt) +} + +/// `Vd32.b=vavg(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavgb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vavg_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgb(vu, vv) +} + +/// `Vd32.b=vavg(Vu32.b,Vv32.b):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavgbrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vavg_VbVb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgbrnd(vu, vv) +} + +/// `Vd32.uw=vavg(Vu32.uw,Vv32.uw)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavguw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vavg_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguw(vu, vv) +} + +/// `Vd32.uw=vavg(Vu32.uw,Vv32.uw):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavguwrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vavg_VuwVuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguwrnd(vu, vv) +} + +/// `Vdd32=#0` +/// +/// Instruction Type: MAPPING +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vdd0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_W_vzero() -> HvxVectorPair { + vdd0() +} + +/// `vtmp.h=vgather(Rt32,Mu2,Vv32.h).h` +/// +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vgathermh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vgather_ARMVh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { + vgathermh(rs, rt, mu, vv) +} + +/// `vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h` +/// +/// Instruction Type: CVI_GATHER_DV +/// Execution Slots: SLOT01 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vgathermhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vgather_ARMWw(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVectorPair) { + vgathermhw(rs, rt, mu, vvv) +} + +/// `vtmp.w=vgather(Rt32,Mu2,Vv32.w).w` +/// +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vgathermw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vgather_ARMVw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { + vgathermw(rs, rt, mu, vv) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpabuu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpa_WubRub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpabuu(vuu, rt) +} + +/// `Vxx32.h+=vmpa(Vuu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpabuu_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpaacc_WhWubRub( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpabuu_acc(vxx, vuu, rt) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpyh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vmpyacc_WwVhRh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyh_acc(vxx, vu, rt) +} + +/// `Vd32.uw=vmpye(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpyuhe))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vmpye_VuhRuh(vu: HvxVector, rt: i32) -> HvxVector { + vmpyuhe(vu, rt) +} + +/// `Vx32.uw+=vmpye(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpyuhe_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vmpyeacc_VuwVuhRuh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyuhe_acc(vx, vu, rt) +} + +/// `Vd32.b=vnavg(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vnavgb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vnavg_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgb(vu, vv) +} + +/// `vscatter(Rt32,Mu2,Vv32.h).h=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vscatter_RMVhV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermh(rt, mu, vv, vw) +} + +/// `vscatter(Rt32,Mu2,Vv32.h).h+=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermh_add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vscatteracc_RMVhV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermh_add(rt, mu, vv, vw) +} + +/// `vscatter(Rt32,Mu2,Vvv32.w).h=Vw32` +/// +/// Instruction Type: CVI_SCATTER_DV +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vscatter_RMWwV(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { + vscattermhw(rt, mu, vvv, vw) +} + +/// `vscatter(Rt32,Mu2,Vvv32.w).h+=Vw32` +/// +/// Instruction Type: CVI_SCATTER_DV +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermhw_add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vscatteracc_RMWwV(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { + vscattermhw_add(rt, mu, vvv, vw) +} + +/// `vscatter(Rt32,Mu2,Vv32.w).w=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vscatter_RMVwV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermw(rt, mu, vv, vw) +} + +/// `vscatter(Rt32,Mu2,Vv32.w).w+=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermw_add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vscatteracc_RMVwV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermw_add(rt, mu, vv, vw) +} + +/// `Vxx32.w=vasrinto(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[cfg_attr(test, assert_instr(vasr_into))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vasrinto_WwVwVw( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vasr_into(vxx, vu, vv) +} + +/// `Vd32.uw=vrotr(Vu32.uw,Vv32.uw)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[cfg_attr(test, assert_instr(vrotr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vrotr_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrotr(vu, vv) +} + +/// `Vd32.w=vsatdw(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[cfg_attr(test, assert_instr(vsatdw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vsatdw_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsatdw(vu, vv) +} + +/// `Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):h` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyhubs10))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_v6mpy_WubWbI_h( + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyhubs10(vuu, vvv, iu2) +} + +/// `Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):h` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyhubs10_vxx))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_v6mpyacc_WwWubWbI_h( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyhubs10_vxx(vxx, vuu, vvv, iu2) +} + +/// `Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):v` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyvubs10))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_v6mpy_WubWbI_v( + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyvubs10(vuu, vvv, iu2) +} + +/// `Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):v` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyvubs10_vxx))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_v6mpyacc_WwWubWbI_v( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyvubs10_vxx(vxx, vuu, vvv, iu2) +} + +/// `Vd32.hf=vabs(Vu32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vabs_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vabs_Vhf(vu: HvxVector) -> HvxVector { + vabs_hf(vu) +} + +/// `Vd32.sf=vabs(Vu32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vabs_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_vabs_Vsf(vu: HvxVector) -> HvxVector { + vabs_sf(vu) +} + +/// `Vd32.qf16=vadd(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf16_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_hf(vu, vv) +} + +/// `Vd32.hf=vadd(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_hf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_hf_hf(vu, vv) +} + +/// `Vd32.qf16=vadd(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf16_vadd_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf16(vu, vv) +} + +/// `Vd32.qf16=vadd(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf16_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf16_vadd_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf16_mix(vu, vv) +} + +/// `Vd32.qf32=vadd(Vu32.qf32,Vv32.qf32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf32_vadd_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf32(vu, vv) +} + +/// `Vd32.qf32=vadd(Vu32.qf32,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf32_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf32_vadd_Vqf32Vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf32_mix(vu, vv) +} + +/// `Vd32.qf32=vadd(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf32_vadd_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_sf(vu, vv) +} + +/// `Vdd32.sf=vadd(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wsf_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vadd_sf_hf(vu, vv) +} + +/// `Vd32.sf=vadd(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_sf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_vadd_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_sf_sf(vu, vv) +} + +/// `Vd32.w=vfmv(Vu32.w)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vassign_fp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vfmv_Vw(vu: HvxVector) -> HvxVector { + vassign_fp(vu) +} + +/// `Vd32.hf=Vu32.qf16` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vconv_hf_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_equals_Vqf16(vu: HvxVector) -> HvxVector { + vconv_hf_qf16(vu) +} + +/// `Vd32.hf=Vuu32.qf32` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vconv_hf_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_equals_Wqf32(vuu: HvxVectorPair) -> HvxVector { + vconv_hf_qf32(vuu) +} + +/// `Vd32.sf=Vu32.qf32` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vconv_sf_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_equals_Vqf32(vu: HvxVector) -> HvxVector { + vconv_sf_qf32(vu) +} + +/// `Vd32.b=vcvt(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_b_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vcvt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vcvt_b_hf(vu, vv) +} + +/// `Vd32.h=vcvt(Vu32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_h_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vcvt_Vhf(vu: HvxVector) -> HvxVector { + vcvt_h_hf(vu) +} + +/// `Vdd32.hf=vcvt(Vu32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_b))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Whf_vcvt_Vb(vu: HvxVector) -> HvxVectorPair { + vcvt_hf_b(vu) +} + +/// `Vd32.hf=vcvt(Vu32.h)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_h))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vcvt_Vh(vu: HvxVector) -> HvxVector { + vcvt_hf_h(vu) +} + +/// `Vd32.hf=vcvt(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vcvt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vcvt_hf_sf(vu, vv) +} + +/// `Vdd32.hf=vcvt(Vu32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_ub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Whf_vcvt_Vub(vu: HvxVector) -> HvxVectorPair { + vcvt_hf_ub(vu) +} + +/// `Vd32.hf=vcvt(Vu32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_uh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vcvt_Vuh(vu: HvxVector) -> HvxVector { + vcvt_hf_uh(vu) +} + +/// `Vdd32.sf=vcvt(Vu32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wsf_vcvt_Vhf(vu: HvxVector) -> HvxVectorPair { + vcvt_sf_hf(vu) +} + +/// `Vd32.ub=vcvt(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_ub_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vcvt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vcvt_ub_hf(vu, vv) +} + +/// `Vd32.uh=vcvt(Vu32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_uh_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vcvt_Vhf(vu: HvxVector) -> HvxVector { + vcvt_uh_hf(vu) +} + +/// `Vd32.sf=vdmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vdmpy_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_vdmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpy_sf_hf(vu, vv) +} + +/// `Vx32.sf+=vdmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vdmpy_sf_hf_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_vdmpyacc_VsfVhfVhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpy_sf_hf_acc(vx, vu, vv) +} + +/// `Vd32.hf=vfmax(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmax_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vfmax_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmax_hf(vu, vv) +} + +/// `Vd32.sf=vfmax(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmax_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_vfmax_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmax_sf(vu, vv) +} + +/// `Vd32.hf=vfmin(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmin_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vfmin_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmin_hf(vu, vv) +} + +/// `Vd32.sf=vfmin(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmin_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_vfmin_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmin_sf(vu, vv) +} + +/// `Vd32.hf=vfneg(Vu32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfneg_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vfneg_Vhf(vu: HvxVector) -> HvxVector { + vfneg_hf(vu) +} + +/// `Vd32.sf=vfneg(Vu32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfneg_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_vfneg_Vsf(vu: HvxVector) -> HvxVector { + vfneg_sf(vu) +} + +/// `Vd32.hf=vmax(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmax_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vmax_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmax_hf(vu, vv) +} + +/// `Vd32.sf=vmax(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmax_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_vmax_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmax_sf(vu, vv) +} + +/// `Vd32.hf=vmin(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmin_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vmin_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmin_hf(vu, vv) +} + +/// `Vd32.sf=vmin(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmin_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_vmin_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmin_sf(vu, vv) +} + +/// `Vd32.hf=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_hf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_hf_hf(vu, vv) +} + +/// `Vx32.hf+=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_hf_hf_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vmpyacc_VhfVhfVhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_hf_hf_acc(vx, vu, vv) +} + +/// `Vd32.qf16=vmpy(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf16_vmpy_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf16(vu, vv) +} + +/// `Vd32.qf16=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf16_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf16_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf16_hf(vu, vv) +} + +/// `Vd32.qf16=vmpy(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf16_mix_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf16_vmpy_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf16_mix_hf(vu, vv) +} + +/// `Vd32.qf32=vmpy(Vu32.qf32,Vv32.qf32)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf32_vmpy_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf32(vu, vv) +} + +/// `Vdd32.qf32=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wqf32_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_qf32_hf(vu, vv) +} + +/// `Vdd32.qf32=vmpy(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_mix_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wqf32_vmpy_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_qf32_mix_hf(vu, vv) +} + +/// `Vdd32.qf32=vmpy(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wqf32_vmpy_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_qf32_qf16(vu, vv) +} + +/// `Vd32.qf32=vmpy(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf32_vmpy_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf32_sf(vu, vv) +} + +/// `Vdd32.sf=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wsf_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_sf_hf(vu, vv) +} + +/// `Vxx32.sf+=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_sf_hf_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wsf_vmpyacc_WsfVhfVhf( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpy_sf_hf_acc(vxx, vu, vv) +} + +/// `Vd32.sf=vmpy(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_sf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_vmpy_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_sf_sf(vu, vv) +} + +/// `Vd32.qf16=vsub(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf16_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_hf(vu, vv) +} + +/// `Vd32.hf=vsub(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_hf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_hf_hf(vu, vv) +} + +/// `Vd32.qf16=vsub(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf16_vsub_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf16(vu, vv) +} + +/// `Vd32.qf16=vsub(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf16_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf16_vsub_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf16_mix(vu, vv) +} + +/// `Vd32.qf32=vsub(Vu32.qf32,Vv32.qf32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf32_vsub_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf32(vu, vv) +} + +/// `Vd32.qf32=vsub(Vu32.qf32,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf32_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf32_vsub_Vqf32Vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf32_mix(vu, vv) +} + +/// `Vd32.qf32=vsub(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf32_vsub_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_sf(vu, vv) +} + +/// `Vdd32.sf=vsub(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wsf_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsub_sf_hf(vu, vv) +} + +/// `Vd32.sf=vsub(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_sf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_vsub_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_sf_sf(vu, vv) +} + +/// `Vd32.ub=vasr(Vuu32.uh,Vv32.ub):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvuhubrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vasr_WuhVub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvuhubrndsat(vuu, vv) +} + +/// `Vd32.ub=vasr(Vuu32.uh,Vv32.ub):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvuhubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vasr_WuhVub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvuhubsat(vuu, vv) +} + +/// `Vd32.uh=vasr(Vuu32.w,Vv32.uh):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvwuhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vasr_WwVuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvwuhrndsat(vuu, vv) +} + +/// `Vd32.uh=vasr(Vuu32.w,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvwuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vasr_WwVuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvwuhsat(vuu, vv) +} + +/// `Vd32.uh=vmpy(Vu32.uh,Vv32.uh):>>16` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vmpyuhvs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vmpy_VuhVuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyuhvs(vu, vv) +} + +/// `Vd32.h=Vu32.hf` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_h_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_equals_Vhf(vu: HvxVector) -> HvxVector { + vconv_h_hf(vu) +} + +/// `Vd32.hf=Vu32.h` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_hf_h))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_equals_Vh(vu: HvxVector) -> HvxVector { + vconv_hf_h(vu) +} + +/// `Vd32.sf=Vu32.w` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_sf_w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_equals_Vw(vu: HvxVector) -> HvxVector { + vconv_sf_w(vu) +} + +/// `Vd32.w=Vu32.sf` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_w_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_equals_Vsf(vu: HvxVector) -> HvxVector { + vconv_w_sf(vu) +} + +/// `Vd32=vgetqfext(Vu32.x,Rt32)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(get_qfext))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vgetqfext_VR(vu: HvxVector, rt: i32) -> HvxVector { + get_qfext(vu, rt) +} + +/// `Vd32.x=vsetqfext(Vu32,Rt32)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(set_qfext))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vsetqfext_VR(vu: HvxVector, rt: i32) -> HvxVector { + set_qfext(vu, rt) +} + +/// `Vd32.f8=vabs(Vu32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vabs_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vabs_V(vu: HvxVector) -> HvxVector { + vabs_f8(vu) +} + +/// `Vdd32.hf=vcvt2(Vu32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vcvt2_hf_b))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Whf_vcvt2_Vb(vu: HvxVector) -> HvxVectorPair { + vcvt2_hf_b(vu) +} + +/// `Vdd32.hf=vcvt2(Vu32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vcvt2_hf_ub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Whf_vcvt2_Vub(vu: HvxVector) -> HvxVectorPair { + vcvt2_hf_ub(vu) +} + +/// `Vdd32.hf=vcvt(Vu32.f8)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vcvt_hf_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Whf_vcvt_V(vu: HvxVector) -> HvxVectorPair { + vcvt_hf_f8(vu) +} + +/// `Vd32.f8=vfmax(Vu32.f8,Vv32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vfmax_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vfmax_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmax_f8(vu, vv) +} + +/// `Vd32.f8=vfmin(Vu32.f8,Vv32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vfmin_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vfmin_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmin_f8(vu, vv) +} + +/// `Vd32.f8=vfneg(Vu32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vfneg_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vfneg_V(vu: HvxVector) -> HvxVector { + vfneg_f8(vu) +} + +/// `Qd4=and(Qs4,Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_and_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_and( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=and(Qs4,!Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_and_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_and_n( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=not(Qs4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_not_Q(qs: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_not(vandvrt( + core::mem::transmute::(qs), + -1, + )), + -1, + )) +} + +/// `Qd4=or(Qs4,Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_or_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_or( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=or(Qs4,!Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_or_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_or_n( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=vsetq(Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vsetq_R(rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt(pred_scalar2(rt), -1)) +} + +/// `Qd4=xor(Qs4,Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_xor_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_xor( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `if (!Qv4) vmem(Rt32+#s4)=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vmem_QnRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_nqpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (!Qv4) vmem(Rt32+#s4):nt=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vmem_QnRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_nt_nqpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (Qv4) vmem(Rt32+#s4):nt=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vmem_QRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_nt_qpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (Qv4) vmem(Rt32+#s4)=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vmem_QRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_qpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (!Qv4) Vx32.b+=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_condacc_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddbnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.b+=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_condacc_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddbq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.h+=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_condacc_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddhnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.h+=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_condacc_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddhq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.w+=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_condacc_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddwnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.w+=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_condacc_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddwq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `Vd32=vand(Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vand_QR(qu: HvxVectorPred, rt: i32) -> HvxVector { + vandvrt(core::mem::transmute::(qu), rt) +} + +/// `Vx32|=vand(Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vandor_VQR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { + vandvrt_acc(vx, core::mem::transmute::(qu), rt) +} + +/// `Qd4=vand(Vu32,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vand_VR(vu: HvxVector, rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vu, rt)) +} + +/// `Qx4|=vand(Vu32,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vandor_QVR(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt_acc( + core::mem::transmute::(qx), + vu, + rt, + )) +} + +/// `Qd4=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eq_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(veqb(vu, vv), -1)) +} + +/// `Qx4&=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eqand_QVbVb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqb_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eqor_QVbVb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqb_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eqxacc_QVbVb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqb_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eq_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(veqh(vu, vv), -1)) +} + +/// `Qx4&=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eqand_QVhVh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqh_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eqor_QVhVh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqh_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eqxacc_QVhVh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqh_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eq_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(veqw(vu, vv), -1)) +} + +/// `Qx4&=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eqand_QVwVw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqw_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eqor_QVwVw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqw_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eqxacc_QVwVw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqw_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gt_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtb(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtand_QVbVb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtb_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtor_QVbVb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtb_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtxacc_QVbVb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtb_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gt_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgth(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtand_QVhVh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgth_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtor_QVhVh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgth_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtxacc_QVhVh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgth_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gt_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtub(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtand_QVubVub( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtub_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtor_QVubVub( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtub_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtxacc_QVubVub( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtub_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gt_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtuh(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtand_QVuhVuh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuh_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtor_QVuhVuh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuh_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtxacc_QVuhVuh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuh_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gt_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtuw(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtand_QVuwVuw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuw_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtor_QVuwVuw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuw_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtxacc_QVuwVuw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuw_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gt_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtw(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtand_QVwVw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtw_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtor_QVwVw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtw_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtxacc_QVwVw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtw_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Vd32=vmux(Qt4,Vu32,Vv32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vmux_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmux( + vandvrt(core::mem::transmute::(qt), -1), + vu, + vv, + ) +} + +/// `if (!Qv4) Vx32.b-=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_condnac_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubbnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.b-=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_condnac_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubbq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.h-=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_condnac_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubhnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.h-=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_condnac_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubhq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.w-=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_condnac_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubwnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.w-=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_condnac_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubwq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `Vdd32=vswap(Qt4,Vu32,Vv32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_W_vswap_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vswap( + vandvrt(core::mem::transmute::(qt), -1), + vu, + vv, + ) +} + +/// `Qd4=vsetq2(Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vsetq2_R(rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt(pred_scalar2v2(rt), -1)) +} + +/// `Qd4.b=vshuffe(Qs4.h,Qt4.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Qb_vshuffe_QhQh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + shuffeqh( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4.h=vshuffe(Qs4.w,Qt4.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Qh_vshuffe_QwQw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + shuffeqw( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Vd32=vand(!Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vand_QnR(qu: HvxVectorPred, rt: i32) -> HvxVector { + vandnqrt( + vandvrt(core::mem::transmute::(qu), -1), + rt, + ) +} + +/// `Vx32|=vand(!Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vandor_VQnR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { + vandnqrt_acc( + vx, + vandvrt(core::mem::transmute::(qu), -1), + rt, + ) +} + +/// `Vd32=vand(!Qv4,Vu32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vand_QnV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { + vandvnqv( + vandvrt(core::mem::transmute::(qv), -1), + vu, + ) +} + +/// `Vd32=vand(Qv4,Vu32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vand_QV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { + vandvqv( + vandvrt(core::mem::transmute::(qv), -1), + vu, + ) +} + +/// `if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vv32.h).h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vgather_AQRMVh( + rs: *mut HvxVector, + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, +) { + vgathermhq( + rs, + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + ) +} + +/// `if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_GATHER_DV +/// Execution Slots: SLOT01 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vgather_AQRMWw( + rs: *mut HvxVector, + qs: HvxVectorPred, + rt: i32, + mu: i32, + vvv: HvxVectorPair, +) { + vgathermhwq( + rs, + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vvv, + ) +} + +/// `if (Qs4) vtmp.w=vgather(Rt32,Mu2,Vv32.w).w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vgather_AQRMVw( + rs: *mut HvxVector, + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, +) { + vgathermwq( + rs, + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + ) +} + +/// `Vd32.b=prefixsum(Qv4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_prefixsum_Q(qv: HvxVectorPred) -> HvxVector { + vprefixqb(vandvrt( + core::mem::transmute::(qv), + -1, + )) +} + +/// `Vd32.h=prefixsum(Qv4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_prefixsum_Q(qv: HvxVectorPred) -> HvxVector { + vprefixqh(vandvrt( + core::mem::transmute::(qv), + -1, + )) +} + +/// `Vd32.w=prefixsum(Qv4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_prefixsum_Q(qv: HvxVectorPred) -> HvxVector { + vprefixqw(vandvrt( + core::mem::transmute::(qv), + -1, + )) +} + +/// `if (Qs4) vscatter(Rt32,Mu2,Vv32.h).h=Vw32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vscatter_QRMVhV( + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, + vw: HvxVector, +) { + vscattermhq( + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + vw, + ) +} + +/// `if (Qs4) vscatter(Rt32,Mu2,Vvv32.w).h=Vw32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_SCATTER_DV +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vscatter_QRMWwV( + qs: HvxVectorPred, + rt: i32, + mu: i32, + vvv: HvxVectorPair, + vw: HvxVector, +) { + vscattermhwq( + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vvv, + vw, + ) +} + +/// `if (Qs4) vscatter(Rt32,Mu2,Vv32.w).w=Vw32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vscatter_QRMVwV( + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, + vw: HvxVector, +) { + vscattermwq( + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + vw, + ) +} + +/// `Vd32.w=vadd(Vu32.w,Vv32.w,Qs4):carry:sat` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vadd_VwVwQ_carry_sat( + vu: HvxVector, + vv: HvxVector, + qs: HvxVectorPred, +) -> HvxVector { + vaddcarrysat( + vu, + vv, + vandvrt(core::mem::transmute::(qs), -1), + ) +} + +/// `Qd4=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgthf(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtand_QVhfVhf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgthf_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtor_QVhfVhf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgthf_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtxacc_QVhfVhf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgthf_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtsf(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtand_QVsfVsf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtsf_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtor_QVsfVsf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtsf_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtxacc_QVsfVsf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtsf_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} diff --git a/library/stdarch/crates/core_arch/src/hexagon/v64.rs b/library/stdarch/crates/core_arch/src/hexagon/v64.rs new file mode 100644 index 0000000000000..3ac8b47079333 --- /dev/null +++ b/library/stdarch/crates/core_arch/src/hexagon/v64.rs @@ -0,0 +1,7503 @@ +// This code is automatically generated. DO NOT MODIFY. +//! Hexagon HVX 64-byte vector mode intrinsics +//! +//! This module provides intrinsics for the Hexagon Vector Extensions (HVX) +//! in 64-byte vector mode (512-bit vectors). +//! +//! HVX is a wide vector extension designed for high-performance signal processing. +//! [Hexagon HVX Programmer's Reference Manual](https://docs.qualcomm.com/doc/80-N2040-61) +//! +//! ## Vector Types +//! +//! In 64-byte mode: +//! - `HvxVector` is 512 bits (64 bytes) containing 16 x 32-bit values +//! - `HvxVectorPair` is 1024 bits (128 bytes) +//! - `HvxVectorPred` is 512 bits (64 bytes) for predicate operations +//! +//! To use this module, compile with `-C target-feature=+hvx-length64b`. +//! +//! ## Naming Convention +//! +//! Function names preserve the original Q6 naming case because the convention +//! uses case to distinguish register types: +//! - `W` (uppercase) = vector pair (`HvxVectorPair`) +//! - `V` (uppercase) = vector (`HvxVector`) +//! - `Q` (uppercase) = predicate (`HvxVectorPred`) +//! - `R` = scalar register (`i32`) +//! +//! For example, `Q6_W_vcombine_VV` operates on a vector pair while +//! `Q6_V_hi_W` extracts a vector from a pair. +//! +//! ## Architecture Versions +//! +//! Different intrinsics require different HVX architecture versions. Use the +//! appropriate target feature to enable the required version: +//! - HVX v60: `-C target-feature=+hvxv60` (basic HVX operations) +//! - HVX v62: `-C target-feature=+hvxv62` +//! - HVX v65: `-C target-feature=+hvxv65` (includes floating-point support) +//! - HVX v66: `-C target-feature=+hvxv66` +//! - HVX v68: `-C target-feature=+hvxv68` +//! - HVX v69: `-C target-feature=+hvxv69` +//! - HVX v73: `-C target-feature=+hvxv73` +//! - HVX v79: `-C target-feature=+hvxv79` +//! +//! Each version includes all features from previous versions. + +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] + +#[cfg(test)] +use stdarch_test::assert_instr; + +use crate::intrinsics::simd::{simd_add, simd_and, simd_or, simd_sub, simd_xor}; + +// HVX type definitions for 64-byte vector mode +types! { + #![unstable(feature = "stdarch_hexagon", issue = "151523")] + + /// HVX vector type (512 bits / 64 bytes) + /// + /// This type represents a single HVX vector register containing 16 x 32-bit values. + pub struct HvxVector(16 x i32); + + /// HVX vector pair type (1024 bits / 128 bytes) + /// + /// This type represents a pair of HVX vector registers, often used for + /// operations that produce double-width results. + pub struct HvxVectorPair(32 x i32); + + /// HVX vector predicate type (512 bits / 64 bytes) + /// + /// This type represents a predicate vector used for conditional operations. + /// Each bit corresponds to a lane in the vector. + pub struct HvxVectorPred(16 x i32); +} + +// LLVM intrinsic declarations for 64-byte vector mode +#[allow(improper_ctypes)] +unsafe extern "unadjusted" { + #[link_name = "llvm.hexagon.V6.extractw"] + fn extractw(_: HvxVector, _: i32) -> i32; + #[link_name = "llvm.hexagon.V6.get.qfext"] + fn get_qfext(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.hi"] + fn hi(_: HvxVectorPair) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lo"] + fn lo(_: HvxVectorPair) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lvsplatb"] + fn lvsplatb(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lvsplath"] + fn lvsplath(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lvsplatw"] + fn lvsplatw(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.and"] + fn pred_and(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.and.n"] + fn pred_and_n(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.not"] + fn pred_not(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.or"] + fn pred_or(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.or.n"] + fn pred_or_n(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.scalar2"] + fn pred_scalar2(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.scalar2v2"] + fn pred_scalar2v2(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.xor"] + fn pred_xor(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.set.qfext"] + fn set_qfext(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.shuffeqh"] + fn shuffeqh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.shuffeqw"] + fn shuffeqw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.v6mpyhubs10"] + fn v6mpyhubs10(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.v6mpyhubs10.vxx"] + fn v6mpyhubs10_vxx( + _: HvxVectorPair, + _: HvxVectorPair, + _: HvxVectorPair, + _: i32, + ) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.v6mpyvubs10"] + fn v6mpyvubs10(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.v6mpyvubs10.vxx"] + fn v6mpyvubs10_vxx( + _: HvxVectorPair, + _: HvxVectorPair, + _: HvxVectorPair, + _: i32, + ) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vS32b.nqpred.ai"] + fn vS32b_nqpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vS32b.nt.nqpred.ai"] + fn vS32b_nt_nqpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vS32b.nt.qpred.ai"] + fn vS32b_nt_qpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vS32b.qpred.ai"] + fn vS32b_qpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vabs.f8"] + fn vabs_f8(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabs.hf"] + fn vabs_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabs.sf"] + fn vabs_sf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsb"] + fn vabsb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsb.sat"] + fn vabsb_sat(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffh"] + fn vabsdiffh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffub"] + fn vabsdiffub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffuh"] + fn vabsdiffuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffw"] + fn vabsdiffw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsh"] + fn vabsh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsh.sat"] + fn vabsh_sat(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsw"] + fn vabsw(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsw.sat"] + fn vabsw_sat(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.hf"] + fn vadd_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.hf.hf"] + fn vadd_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf16"] + fn vadd_qf16(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf16.mix"] + fn vadd_qf16_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf32"] + fn vadd_qf32(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf32.mix"] + fn vadd_qf32_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.sf"] + fn vadd_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.sf.hf"] + fn vadd_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadd.sf.sf"] + fn vadd_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddb"] + fn vaddb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddb.dv"] + fn vaddb_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddbnq"] + fn vaddbnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddbq"] + fn vaddbq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddbsat"] + fn vaddbsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddbsat.dv"] + fn vaddbsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddcarrysat"] + fn vaddcarrysat(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddclbh"] + fn vaddclbh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddclbw"] + fn vaddclbw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddh"] + fn vaddh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddh.dv"] + fn vaddh_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddhnq"] + fn vaddhnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddhq"] + fn vaddhq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddhsat"] + fn vaddhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddhsat.dv"] + fn vaddhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddhw"] + fn vaddhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddhw.acc"] + fn vaddhw_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddubh"] + fn vaddubh(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddubh.acc"] + fn vaddubh_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddubsat"] + fn vaddubsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddubsat.dv"] + fn vaddubsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddububb.sat"] + fn vaddububb_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadduhsat"] + fn vadduhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadduhsat.dv"] + fn vadduhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadduhw"] + fn vadduhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadduhw.acc"] + fn vadduhw_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadduwsat"] + fn vadduwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadduwsat.dv"] + fn vadduwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddw"] + fn vaddw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddw.dv"] + fn vaddw_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddwnq"] + fn vaddwnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddwq"] + fn vaddwq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddwsat"] + fn vaddwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddwsat.dv"] + fn vaddwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.valignb"] + fn valignb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.valignbi"] + fn valignbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vand"] + fn vand(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandnqrt"] + fn vandnqrt(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandnqrt.acc"] + fn vandnqrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandqrt"] + fn vandqrt(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandqrt.acc"] + fn vandqrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvnqv"] + fn vandvnqv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvqv"] + fn vandvqv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvrt"] + fn vandvrt(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvrt.acc"] + fn vandvrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslh"] + fn vaslh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslh.acc"] + fn vaslh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslhv"] + fn vaslhv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslw"] + fn vaslw(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslw.acc"] + fn vaslw_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslwv"] + fn vaslwv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasr.into"] + fn vasr_into(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vasrh"] + fn vasrh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrh.acc"] + fn vasrh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhbrndsat"] + fn vasrhbrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhbsat"] + fn vasrhbsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhubrndsat"] + fn vasrhubrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhubsat"] + fn vasrhubsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhv"] + fn vasrhv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruhubrndsat"] + fn vasruhubrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruhubsat"] + fn vasruhubsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruwuhrndsat"] + fn vasruwuhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruwuhsat"] + fn vasruwuhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvuhubrndsat"] + fn vasrvuhubrndsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvuhubsat"] + fn vasrvuhubsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvwuhrndsat"] + fn vasrvwuhrndsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvwuhsat"] + fn vasrvwuhsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrw"] + fn vasrw(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrw.acc"] + fn vasrw_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwh"] + fn vasrwh(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwhrndsat"] + fn vasrwhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwhsat"] + fn vasrwhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwuhrndsat"] + fn vasrwuhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwuhsat"] + fn vasrwuhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwv"] + fn vasrwv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vassign"] + fn vassign(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vassign.fp"] + fn vassign_fp(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vassignp"] + fn vassignp(_: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vavgb"] + fn vavgb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgbrnd"] + fn vavgbrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgh"] + fn vavgh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavghrnd"] + fn vavghrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgub"] + fn vavgub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgubrnd"] + fn vavgubrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguh"] + fn vavguh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguhrnd"] + fn vavguhrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguw"] + fn vavguw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguwrnd"] + fn vavguwrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgw"] + fn vavgw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgwrnd"] + fn vavgwrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcl0h"] + fn vcl0h(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcl0w"] + fn vcl0w(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcombine"] + fn vcombine(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vconv.h.hf"] + fn vconv_h_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.hf.h"] + fn vconv_hf_h(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.hf.qf16"] + fn vconv_hf_qf16(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.hf.qf32"] + fn vconv_hf_qf32(_: HvxVectorPair) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.sf.qf32"] + fn vconv_sf_qf32(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.sf.w"] + fn vconv_sf_w(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.w.sf"] + fn vconv_w_sf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt2.hf.b"] + fn vcvt2_hf_b(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt2.hf.ub"] + fn vcvt2_hf_ub(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.b.hf"] + fn vcvt_b_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.h.hf"] + fn vcvt_h_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.hf.b"] + fn vcvt_hf_b(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.hf.f8"] + fn vcvt_hf_f8(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.hf.h"] + fn vcvt_hf_h(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.hf.sf"] + fn vcvt_hf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.hf.ub"] + fn vcvt_hf_ub(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.hf.uh"] + fn vcvt_hf_uh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.sf.hf"] + fn vcvt_sf_hf(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.ub.hf"] + fn vcvt_ub_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.uh.hf"] + fn vcvt_uh_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vd0"] + fn vd0() -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdd0"] + fn vdd0() -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdealb"] + fn vdealb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdealb4w"] + fn vdealb4w(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdealh"] + fn vdealh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdealvdd"] + fn vdealvdd(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdelta"] + fn vdelta(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpy.sf.hf"] + fn vdmpy_sf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpy.sf.hf.acc"] + fn vdmpy_sf_hf_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpybus"] + fn vdmpybus(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpybus.acc"] + fn vdmpybus_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpybus.dv"] + fn vdmpybus_dv(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpybus.dv.acc"] + fn vdmpybus_dv_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpyhb"] + fn vdmpyhb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhb.acc"] + fn vdmpyhb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhb.dv"] + fn vdmpyhb_dv(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpyhb.dv.acc"] + fn vdmpyhb_dv_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpyhisat"] + fn vdmpyhisat(_: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhisat.acc"] + fn vdmpyhisat_acc(_: HvxVector, _: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsat"] + fn vdmpyhsat(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsat.acc"] + fn vdmpyhsat_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsuisat"] + fn vdmpyhsuisat(_: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsuisat.acc"] + fn vdmpyhsuisat_acc(_: HvxVector, _: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsusat"] + fn vdmpyhsusat(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsusat.acc"] + fn vdmpyhsusat_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhvsat"] + fn vdmpyhvsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhvsat.acc"] + fn vdmpyhvsat_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdsaduh"] + fn vdsaduh(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdsaduh.acc"] + fn vdsaduh_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.veqb"] + fn veqb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqb.and"] + fn veqb_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqb.or"] + fn veqb_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqb.xor"] + fn veqb_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh"] + fn veqh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh.and"] + fn veqh_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh.or"] + fn veqh_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh.xor"] + fn veqh_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw"] + fn veqw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw.and"] + fn veqw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw.or"] + fn veqw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw.xor"] + fn veqw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmax.f8"] + fn vfmax_f8(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmax.hf"] + fn vfmax_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmax.sf"] + fn vfmax_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmin.f8"] + fn vfmin_f8(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmin.hf"] + fn vfmin_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmin.sf"] + fn vfmin_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfneg.f8"] + fn vfneg_f8(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfneg.hf"] + fn vfneg_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfneg.sf"] + fn vfneg_sf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgathermh"] + fn vgathermh(_: *mut HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgathermhq"] + fn vgathermhq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgathermhw"] + fn vgathermhw(_: *mut HvxVector, _: i32, _: i32, _: HvxVectorPair) -> (); + #[link_name = "llvm.hexagon.V6.vgathermhwq"] + fn vgathermhwq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVectorPair) -> (); + #[link_name = "llvm.hexagon.V6.vgathermw"] + fn vgathermw(_: *mut HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgathermwq"] + fn vgathermwq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgtb"] + fn vgtb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtb.and"] + fn vgtb_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtb.or"] + fn vgtb_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtb.xor"] + fn vgtb_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth"] + fn vgth(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth.and"] + fn vgth_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth.or"] + fn vgth_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth.xor"] + fn vgth_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf"] + fn vgthf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf.and"] + fn vgthf_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf.or"] + fn vgthf_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf.xor"] + fn vgthf_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf"] + fn vgtsf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf.and"] + fn vgtsf_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf.or"] + fn vgtsf_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf.xor"] + fn vgtsf_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub"] + fn vgtub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub.and"] + fn vgtub_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub.or"] + fn vgtub_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub.xor"] + fn vgtub_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh"] + fn vgtuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh.and"] + fn vgtuh_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh.or"] + fn vgtuh_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh.xor"] + fn vgtuh_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw"] + fn vgtuw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw.and"] + fn vgtuw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw.or"] + fn vgtuw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw.xor"] + fn vgtuw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw"] + fn vgtw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw.and"] + fn vgtw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw.or"] + fn vgtw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw.xor"] + fn vgtw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vinsertwr"] + fn vinsertwr(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlalignb"] + fn vlalignb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlalignbi"] + fn vlalignbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrb"] + fn vlsrb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrh"] + fn vlsrh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrhv"] + fn vlsrhv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrw"] + fn vlsrw(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrwv"] + fn vlsrwv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb"] + fn vlutvvb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb.nm"] + fn vlutvvb_nm(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb.oracc"] + fn vlutvvb_oracc(_: HvxVector, _: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb.oracci"] + fn vlutvvb_oracci(_: HvxVector, _: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvbi"] + fn vlutvvbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvwh"] + fn vlutvwh(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwh.nm"] + fn vlutvwh_nm(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwh.oracc"] + fn vlutvwh_oracc(_: HvxVectorPair, _: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwh.oracci"] + fn vlutvwh_oracci(_: HvxVectorPair, _: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwhi"] + fn vlutvwhi(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmax.hf"] + fn vmax_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmax.sf"] + fn vmax_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxb"] + fn vmaxb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxh"] + fn vmaxh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxub"] + fn vmaxub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxuh"] + fn vmaxuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxw"] + fn vmaxw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmin.hf"] + fn vmin_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmin.sf"] + fn vmin_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminb"] + fn vminb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminh"] + fn vminh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminub"] + fn vminub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminuh"] + fn vminuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminw"] + fn vminw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpabus"] + fn vmpabus(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabus.acc"] + fn vmpabus_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabusv"] + fn vmpabusv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabuu"] + fn vmpabuu(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabuu.acc"] + fn vmpabuu_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabuuv"] + fn vmpabuuv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpahb"] + fn vmpahb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpahb.acc"] + fn vmpahb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpauhb"] + fn vmpauhb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpauhb.acc"] + fn vmpauhb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.hf.hf"] + fn vmpy_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.hf.hf.acc"] + fn vmpy_hf_hf_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf16"] + fn vmpy_qf16(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf16.hf"] + fn vmpy_qf16_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf16.mix.hf"] + fn vmpy_qf16_mix_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf32"] + fn vmpy_qf32(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.hf"] + fn vmpy_qf32_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.mix.hf"] + fn vmpy_qf32_mix_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.qf16"] + fn vmpy_qf32_qf16(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.sf"] + fn vmpy_qf32_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.sf.hf"] + fn vmpy_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.sf.hf.acc"] + fn vmpy_sf_hf_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.sf.sf"] + fn vmpy_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpybus"] + fn vmpybus(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybus.acc"] + fn vmpybus_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybusv"] + fn vmpybusv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybusv.acc"] + fn vmpybusv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybv"] + fn vmpybv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybv.acc"] + fn vmpybv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyewuh"] + fn vmpyewuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyewuh.64"] + fn vmpyewuh_64(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyh"] + fn vmpyh(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyh.acc"] + fn vmpyh_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhsat.acc"] + fn vmpyhsat_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhsrs"] + fn vmpyhsrs(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyhss"] + fn vmpyhss(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyhus"] + fn vmpyhus(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhus.acc"] + fn vmpyhus_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhv"] + fn vmpyhv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhv.acc"] + fn vmpyhv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhvsrs"] + fn vmpyhvsrs(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyieoh"] + fn vmpyieoh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiewh.acc"] + fn vmpyiewh_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiewuh"] + fn vmpyiewuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiewuh.acc"] + fn vmpyiewuh_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyih"] + fn vmpyih(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyih.acc"] + fn vmpyih_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyihb"] + fn vmpyihb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyihb.acc"] + fn vmpyihb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiowh"] + fn vmpyiowh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwb"] + fn vmpyiwb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwb.acc"] + fn vmpyiwb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwh"] + fn vmpyiwh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwh.acc"] + fn vmpyiwh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwub"] + fn vmpyiwub(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwub.acc"] + fn vmpyiwub_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh"] + fn vmpyowh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh.64.acc"] + fn vmpyowh_64_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyowh.rnd"] + fn vmpyowh_rnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh.rnd.sacc"] + fn vmpyowh_rnd_sacc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh.sacc"] + fn vmpyowh_sacc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyub"] + fn vmpyub(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyub.acc"] + fn vmpyub_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyubv"] + fn vmpyubv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyubv.acc"] + fn vmpyubv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuh"] + fn vmpyuh(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuh.acc"] + fn vmpyuh_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuhe"] + fn vmpyuhe(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyuhe.acc"] + fn vmpyuhe_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyuhv"] + fn vmpyuhv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuhv.acc"] + fn vmpyuhv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuhvs"] + fn vmpyuhvs(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmux"] + fn vmux(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgb"] + fn vnavgb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgh"] + fn vnavgh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgub"] + fn vnavgub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgw"] + fn vnavgw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnormamth"] + fn vnormamth(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnormamtw"] + fn vnormamtw(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnot"] + fn vnot(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vor"] + fn vor(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackeb"] + fn vpackeb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackeh"] + fn vpackeh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackhb.sat"] + fn vpackhb_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackhub.sat"] + fn vpackhub_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackob"] + fn vpackob(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackoh"] + fn vpackoh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackwh.sat"] + fn vpackwh_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackwuh.sat"] + fn vpackwuh_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpopcounth"] + fn vpopcounth(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vprefixqb"] + fn vprefixqb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vprefixqh"] + fn vprefixqh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vprefixqw"] + fn vprefixqw(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrdelta"] + fn vrdelta(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybus"] + fn vrmpybus(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybus.acc"] + fn vrmpybus_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybusi"] + fn vrmpybusi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpybusi.acc"] + fn vrmpybusi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpybusv"] + fn vrmpybusv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybusv.acc"] + fn vrmpybusv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybv"] + fn vrmpybv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybv.acc"] + fn vrmpybv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyub"] + fn vrmpyub(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyub.acc"] + fn vrmpyub_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyubi"] + fn vrmpyubi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpyubi.acc"] + fn vrmpyubi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpyubv"] + fn vrmpyubv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyubv.acc"] + fn vrmpyubv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vror"] + fn vror(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrotr"] + fn vrotr(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundhb"] + fn vroundhb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundhub"] + fn vroundhub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrounduhub"] + fn vrounduhub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrounduwuh"] + fn vrounduwuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundwh"] + fn vroundwh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundwuh"] + fn vroundwuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrsadubi"] + fn vrsadubi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrsadubi.acc"] + fn vrsadubi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsatdw"] + fn vsatdw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsathub"] + fn vsathub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsatuwuh"] + fn vsatuwuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsatwh"] + fn vsatwh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsb"] + fn vsb(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vscattermh"] + fn vscattermh(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermh.add"] + fn vscattermh_add(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhq"] + fn vscattermhq(_: HvxVector, _: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhw"] + fn vscattermhw(_: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhw.add"] + fn vscattermhw_add(_: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhwq"] + fn vscattermhwq(_: HvxVector, _: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermw"] + fn vscattermw(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermw.add"] + fn vscattermw_add(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermwq"] + fn vscattermwq(_: HvxVector, _: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vsh"] + fn vsh(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufeh"] + fn vshufeh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffb"] + fn vshuffb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffeb"] + fn vshuffeb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffh"] + fn vshuffh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffob"] + fn vshuffob(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffvdd"] + fn vshuffvdd(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufoeb"] + fn vshufoeb(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufoeh"] + fn vshufoeh(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufoh"] + fn vshufoh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.hf"] + fn vsub_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.hf.hf"] + fn vsub_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf16"] + fn vsub_qf16(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf16.mix"] + fn vsub_qf16_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf32"] + fn vsub_qf32(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf32.mix"] + fn vsub_qf32_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.sf"] + fn vsub_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.sf.hf"] + fn vsub_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsub.sf.sf"] + fn vsub_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubb"] + fn vsubb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubb.dv"] + fn vsubb_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubbnq"] + fn vsubbnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubbq"] + fn vsubbq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubbsat"] + fn vsubbsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubbsat.dv"] + fn vsubbsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubh"] + fn vsubh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubh.dv"] + fn vsubh_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubhnq"] + fn vsubhnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubhq"] + fn vsubhq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubhsat"] + fn vsubhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubhsat.dv"] + fn vsubhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubhw"] + fn vsubhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsububh"] + fn vsububh(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsububsat"] + fn vsububsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsububsat.dv"] + fn vsububsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubububb.sat"] + fn vsubububb_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubuhsat"] + fn vsubuhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubuhsat.dv"] + fn vsubuhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubuhw"] + fn vsubuhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubuwsat"] + fn vsubuwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubuwsat.dv"] + fn vsubuwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubw"] + fn vsubw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubw.dv"] + fn vsubw_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubwnq"] + fn vsubwnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubwq"] + fn vsubwq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubwsat"] + fn vsubwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubwsat.dv"] + fn vsubwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vswap"] + fn vswap(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyb"] + fn vtmpyb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyb.acc"] + fn vtmpyb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpybus"] + fn vtmpybus(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpybus.acc"] + fn vtmpybus_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyhb"] + fn vtmpyhb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyhb.acc"] + fn vtmpyhb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackb"] + fn vunpackb(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackh"] + fn vunpackh(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackob"] + fn vunpackob(_: HvxVectorPair, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackoh"] + fn vunpackoh(_: HvxVectorPair, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackub"] + fn vunpackub(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackuh"] + fn vunpackuh(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vxor"] + fn vxor(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vzb"] + fn vzb(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vzh"] + fn vzh(_: HvxVector) -> HvxVectorPair; +} + +/// `Rd32=vextract(Vu32,Rs32)` +/// +/// Instruction Type: LD +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(extractw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vextract_VR(vu: HvxVector, rs: i32) -> i32 { + extractw(vu, rs) +} + +/// `Vd32=hi(Vss32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(hi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_hi_W(vss: HvxVectorPair) -> HvxVector { + hi(vss) +} + +/// `Vd32=lo(Vss32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(lo))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_lo_W(vss: HvxVectorPair) -> HvxVector { + lo(vss) +} + +/// `Vd32=vsplat(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(lvsplatw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vsplat_R(rt: i32) -> HvxVector { + lvsplatw(rt) +} + +/// `Vd32.uh=vabsdiff(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vabsdiff_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffh(vu, vv) +} + +/// `Vd32.ub=vabsdiff(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vabsdiff_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffub(vu, vv) +} + +/// `Vd32.uh=vabsdiff(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vabsdiff_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffuh(vu, vv) +} + +/// `Vd32.uw=vabsdiff(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vabsdiff_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffw(vu, vv) +} + +/// `Vd32.h=vabs(Vu32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vabs_Vh(vu: HvxVector) -> HvxVector { + vabsh(vu) +} + +/// `Vd32.h=vabs(Vu32.h):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsh_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vabs_Vh_sat(vu: HvxVector) -> HvxVector { + vabsh_sat(vu) +} + +/// `Vd32.w=vabs(Vu32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vabs_Vw(vu: HvxVector) -> HvxVector { + vabsw(vu) +} + +/// `Vd32.w=vabs(Vu32.w):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsw_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vabs_Vw_sat(vu: HvxVector) -> HvxVector { + vabsw_sat(vu) +} + +/// `Vd32.b=vadd(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vadd_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddb(vu, vv) +} + +/// `Vdd32.b=vadd(Vuu32.b,Vvv32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddb_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wb_vadd_WbWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddb_dv(vuu, vvv) +} + +/// `Vd32.h=vadd(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vadd_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddh(vu, vv) +} + +/// `Vdd32.h=vadd(Vuu32.h,Vvv32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddh_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vadd_WhWh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddh_dv(vuu, vvv) +} + +/// `Vd32.h=vadd(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vadd_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddhsat(vu, vv) +} + +/// `Vdd32.h=vadd(Vuu32.h,Vvv32.h):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vadd_WhWh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vadd(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vadd_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vaddhw(vu, vv) +} + +/// `Vdd32.h=vadd(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vadd_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vaddubh(vu, vv) +} + +/// `Vd32.ub=vadd(Vu32.ub,Vv32.ub):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vadd_VubVub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddubsat(vu, vv) +} + +/// `Vdd32.ub=vadd(Vuu32.ub,Vvv32.ub):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddubsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wub_vadd_WubWub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddubsat_dv(vuu, vvv) +} + +/// `Vd32.uh=vadd(Vu32.uh,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vadduhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vadd_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadduhsat(vu, vv) +} + +/// `Vdd32.uh=vadd(Vuu32.uh,Vvv32.uh):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vadduhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuh_vadd_WuhWuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vadduhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vadd(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vadduhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vadd_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vadduhw(vu, vv) +} + +/// `Vd32.w=vadd(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vadd_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_add(vu, vv) +} + +/// `Vdd32.w=vadd(Vuu32.w,Vvv32.w)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddw_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vadd_WwWw(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddw_dv(vuu, vvv) +} + +/// `Vd32.w=vadd(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vadd_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddwsat(vu, vv) +} + +/// `Vdd32.w=vadd(Vuu32.w,Vvv32.w):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vadd_WwWw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddwsat_dv(vuu, vvv) +} + +/// `Vd32=valign(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(valignb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_valign_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + valignb(vu, vv, rt) +} + +/// `Vd32=valign(Vu32,Vv32,#u3)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(valignbi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_valign_VVI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { + valignbi(vu, vv, iu3) +} + +/// `Vd32=vand(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vand))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vand_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_and(vu, vv) +} + +/// `Vd32.h=vasl(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vasl_VhR(vu: HvxVector, rt: i32) -> HvxVector { + vaslh(vu, rt) +} + +/// `Vd32.h=vasl(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vasl_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaslhv(vu, vv) +} + +/// `Vd32.w=vasl(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vasl_VwR(vu: HvxVector, rt: i32) -> HvxVector { + vaslw(vu, rt) +} + +/// `Vx32.w+=vasl(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vaslacc_VwVwR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vaslw_acc(vx, vu, rt) +} + +/// `Vd32.w=vasl(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslwv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vasl_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaslwv(vu, vv) +} + +/// `Vd32.h=vasr(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vasr_VhR(vu: HvxVector, rt: i32) -> HvxVector { + vasrh(vu, rt) +} + +/// `Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhbrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vasr_VhVhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhbrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhubrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vasr_VhVhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhubrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vasr_VhVhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhubsat(vu, vv, rt) +} + +/// `Vd32.h=vasr(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vasr_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vasrhv(vu, vv) +} + +/// `Vd32.w=vasr(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vasr_VwR(vu: HvxVector, rt: i32) -> HvxVector { + vasrw(vu, rt) +} + +/// `Vx32.w+=vasr(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vasracc_VwVwR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vasrw_acc(vx, vu, rt) +} + +/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vasr_VwVwR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwh(vu, vv, rt) +} + +/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vasr_VwVwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwhrndsat(vu, vv, rt) +} + +/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vasr_VwVwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwhsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vasr_VwVwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwuhsat(vu, vv, rt) +} + +/// `Vd32.w=vasr(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vasr_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vasrwv(vu, vv) +} + +/// `Vd32=Vu32` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vassign))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_equals_V(vu: HvxVector) -> HvxVector { + vassign(vu) +} + +/// `Vdd32=Vuu32` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vassignp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_W_equals_W(vuu: HvxVectorPair) -> HvxVectorPair { + vassignp(vuu) +} + +/// `Vd32.h=vavg(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vavg_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgh(vu, vv) +} + +/// `Vd32.h=vavg(Vu32.h,Vv32.h):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavghrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vavg_VhVh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavghrnd(vu, vv) +} + +/// `Vd32.ub=vavg(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vavg_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgub(vu, vv) +} + +/// `Vd32.ub=vavg(Vu32.ub,Vv32.ub):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgubrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vavg_VubVub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgubrnd(vu, vv) +} + +/// `Vd32.uh=vavg(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavguh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vavg_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguh(vu, vv) +} + +/// `Vd32.uh=vavg(Vu32.uh,Vv32.uh):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavguhrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vavg_VuhVuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguhrnd(vu, vv) +} + +/// `Vd32.w=vavg(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vavg_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgw(vu, vv) +} + +/// `Vd32.w=vavg(Vu32.w,Vv32.w):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgwrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vavg_VwVw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgwrnd(vu, vv) +} + +/// `Vd32.uh=vcl0(Vu32.uh)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vcl0h))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vcl0_Vuh(vu: HvxVector) -> HvxVector { + vcl0h(vu) +} + +/// `Vd32.uw=vcl0(Vu32.uw)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vcl0w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vcl0_Vuw(vu: HvxVector) -> HvxVector { + vcl0w(vu) +} + +/// `Vdd32=vcombine(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vcombine))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_W_vcombine_VV(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vcombine(vu, vv) +} + +/// `Vd32=#0` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vd0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vzero() -> HvxVector { + vd0() +} + +/// `Vd32.b=vdeal(Vu32.b)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vdeal_Vb(vu: HvxVector) -> HvxVector { + vdealb(vu) +} + +/// `Vd32.b=vdeale(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealb4w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vdeale_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdealb4w(vu, vv) +} + +/// `Vd32.h=vdeal(Vu32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vdeal_Vh(vu: HvxVector) -> HvxVector { + vdealh(vu) +} + +/// `Vdd32=vdeal(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealvdd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_W_vdeal_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vdealvdd(vu, vv, rt) +} + +/// `Vd32=vdelta(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdelta))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vdelta_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdelta(vu, vv) +} + +/// `Vd32.h=vdmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vdmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVector { + vdmpybus(vu, rt) +} + +/// `Vx32.h+=vdmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vdmpyacc_VhVubRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpybus_acc(vx, vu, rt) +} + +/// `Vdd32.h=vdmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vdmpy_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vdmpybus_dv(vuu, rt) +} + +/// `Vxx32.h+=vdmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus_dv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vdmpyacc_WhWubRb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vdmpybus_dv_acc(vxx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpy_VhRb(vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhb(vu, rt) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpyacc_VwVhRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhb_acc(vx, vu, rt) +} + +/// `Vdd32.w=vdmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vdmpy_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vdmpyhb_dv(vuu, rt) +} + +/// `Vxx32.w+=vdmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb_dv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vdmpyacc_WwWhRb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vdmpyhb_dv_acc(vxx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vuu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhisat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpy_WhRh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhisat(vuu, rt) +} + +/// `Vx32.w+=vdmpy(Vuu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhisat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpyacc_VwWhRh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhisat_acc(vx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpy_VhRh_sat(vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsat(vu, rt) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpyacc_VwVhRh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsat_acc(vx, vu, rt) +} + +/// `Vd32.w=vdmpy(Vuu32.h,Rt32.uh,#1):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsuisat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpy_WhRuh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhsuisat(vuu, rt) +} + +/// `Vx32.w+=vdmpy(Vuu32.h,Rt32.uh,#1):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsuisat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpyacc_VwWhRuh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhsuisat_acc(vx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Rt32.uh):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsusat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpy_VhRuh_sat(vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsusat(vu, rt) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Rt32.uh):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsusat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpyacc_VwVhRuh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsusat_acc(vx, vu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhvsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpy_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpyhvsat(vu, vv) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhvsat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vdmpyacc_VwVhVh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpyhvsat_acc(vx, vu, vv) +} + +/// `Vdd32.uw=vdsad(Vuu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdsaduh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vdsad_WuhRuh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vdsaduh(vuu, rt) +} + +/// `Vxx32.uw+=vdsad(Vuu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdsaduh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vdsadacc_WuwWuhRuh( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vdsaduh_acc(vxx, vuu, rt) +} + +/// `Vx32.w=vinsert(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vinsertwr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vinsert_VwR(vx: HvxVector, rt: i32) -> HvxVector { + vinsertwr(vx, rt) +} + +/// `Vd32=vlalign(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlalignb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vlalign_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vlalignb(vu, vv, rt) +} + +/// `Vd32=vlalign(Vu32,Vv32,#u3)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlalignbi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vlalign_VVI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { + vlalignbi(vu, vv, iu3) +} + +/// `Vd32.uh=vlsr(Vu32.uh,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vlsr_VuhR(vu: HvxVector, rt: i32) -> HvxVector { + vlsrh(vu, rt) +} + +/// `Vd32.h=vlsr(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vlsr_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vlsrhv(vu, vv) +} + +/// `Vd32.uw=vlsr(Vu32.uw,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vlsr_VuwR(vu: HvxVector, rt: i32) -> HvxVector { + vlsrw(vu, rt) +} + +/// `Vd32.w=vlsr(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrwv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vlsr_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vlsrwv(vu, vv) +} + +/// `Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvvb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vlut32_VbVbR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vlutvvb(vu, vv, rt) +} + +/// `Vx32.b|=vlut32(Vu32.b,Vv32.b,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvvb_oracc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vlut32or_VbVbVbR( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, + rt: i32, +) -> HvxVector { + vlutvvb_oracc(vx, vu, vv, rt) +} + +/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vlut16_VbVhR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vlutvwh(vu, vv, rt) +} + +/// `Vxx32.h|=vlut16(Vu32.b,Vv32.h,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvwh_oracc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vlut16or_WhVbVhR( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, + rt: i32, +) -> HvxVectorPair { + vlutvwh_oracc(vxx, vu, vv, rt) +} + +/// `Vd32.h=vmax(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vmax_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxh(vu, vv) +} + +/// `Vd32.ub=vmax(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vmax_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxub(vu, vv) +} + +/// `Vd32.uh=vmax(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vmax_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxuh(vu, vv) +} + +/// `Vd32.w=vmax(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmax_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxw(vu, vv) +} + +/// `Vd32.h=vmin(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vmin_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminh(vu, vv) +} + +/// `Vd32.ub=vmin(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vmin_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminub(vu, vv) +} + +/// `Vd32.uh=vmin(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vmin_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminuh(vu, vv) +} + +/// `Vd32.w=vmin(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmin_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminw(vu, vv) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpa_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpabus(vuu, rt) +} + +/// `Vxx32.h+=vmpa(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpaacc_WhWubRb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpabus_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Vvv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabusv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpa_WubWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vmpabusv(vuu, vvv) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Vvv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabuuv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpa_WubWub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vmpabuuv(vuu, vvv) +} + +/// `Vdd32.w=vmpa(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpahb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vmpa_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpahb(vuu, rt) +} + +/// `Vxx32.w+=vmpa(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpahb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vmpaacc_WwWhRb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpahb_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpybus(vu, rt) +} + +/// `Vxx32.h+=vmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpyacc_WhVubRb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpybus_acc(vxx, vu, rt) +} + +/// `Vdd32.h=vmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybusv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpy_VubVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpybusv(vu, vv) +} + +/// `Vxx32.h+=vmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybusv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpyacc_WhVubVb( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpybusv_acc(vxx, vu, vv) +} + +/// `Vdd32.h=vmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpy_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpybv(vu, vv) +} + +/// `Vxx32.h+=vmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpyacc_WhVbVb( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpybv_acc(vxx, vu, vv) +} + +/// `Vd32.w=vmpye(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyewuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpye_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyewuh(vu, vv) +} + +/// `Vdd32.w=vmpy(Vu32.h,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vmpy_VhRh(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyh(vu, rt) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhsat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vmpyacc_WwVhRh_sat( + vxx: HvxVectorPair, + vu: HvxVector, + rt: i32, +) -> HvxVectorPair { + vmpyhsat_acc(vxx, vu, rt) +} + +/// `Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:rnd:sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhsrs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vmpy_VhRh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector { + vmpyhsrs(vu, rt) +} + +/// `Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhss))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vmpy_VhRh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector { + vmpyhss(vu, rt) +} + +/// `Vdd32.w=vmpy(Vu32.h,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vmpy_VhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyhus(vu, vv) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vmpyacc_WwVhVuh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyhus_acc(vxx, vu, vv) +} + +/// `Vdd32.w=vmpy(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vmpy_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyhv(vu, vv) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vmpyacc_WwVhVh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyhv_acc(vxx, vu, vv) +} + +/// `Vd32.h=vmpy(Vu32.h,Vv32.h):<<1:rnd:sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhvsrs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vmpy_VhVh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyhvsrs(vu, vv) +} + +/// `Vd32.w=vmpyieo(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyieoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyieo_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyieoh(vu, vv) +} + +/// `Vx32.w+=vmpyie(Vu32.w,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiewh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyieacc_VwVwVh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiewh_acc(vx, vu, vv) +} + +/// `Vd32.w=vmpyie(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiewuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyie_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiewuh(vu, vv) +} + +/// `Vx32.w+=vmpyie(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiewuh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyieacc_VwVwVuh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiewuh_acc(vx, vu, vv) +} + +/// `Vd32.h=vmpyi(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyih))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vmpyi_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyih(vu, vv) +} + +/// `Vx32.h+=vmpyi(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyih_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vmpyiacc_VhVhVh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyih_acc(vx, vu, vv) +} + +/// `Vd32.h=vmpyi(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyihb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vmpyi_VhRb(vu: HvxVector, rt: i32) -> HvxVector { + vmpyihb(vu, rt) +} + +/// `Vx32.h+=vmpyi(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyihb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vmpyiacc_VhVhRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyihb_acc(vx, vu, rt) +} + +/// `Vd32.w=vmpyio(Vu32.w,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiowh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyio_VwVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiowh(vu, vv) +} + +/// `Vd32.w=vmpyi(Vu32.w,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyi_VwRb(vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwb(vu, rt) +} + +/// `Vx32.w+=vmpyi(Vu32.w,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyiacc_VwVwRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwb_acc(vx, vu, rt) +} + +/// `Vd32.w=vmpyi(Vu32.w,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyi_VwRh(vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwh(vu, rt) +} + +/// `Vx32.w+=vmpyi(Vu32.w,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyiacc_VwVwRh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwh_acc(vx, vu, rt) +} + +/// `Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyo_VwVh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyowh(vu, vv) +} + +/// `Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh_rnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyo_VwVh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyowh_rnd(vu, vv) +} + +/// `Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat:shift` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh_rnd_sacc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, +) -> HvxVector { + vmpyowh_rnd_sacc(vx, vu, vv) +} + +/// `Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:sat:shift` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh_sacc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, +) -> HvxVector { + vmpyowh_sacc(vx, vu, vv) +} + +/// `Vdd32.uh=vmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuh_vmpy_VubRub(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyub(vu, rt) +} + +/// `Vxx32.uh+=vmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyub_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuh_vmpyacc_WuhVubRub( + vxx: HvxVectorPair, + vu: HvxVector, + rt: i32, +) -> HvxVectorPair { + vmpyub_acc(vxx, vu, rt) +} + +/// `Vdd32.uh=vmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyubv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuh_vmpy_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyubv(vu, vv) +} + +/// `Vxx32.uh+=vmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyubv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuh_vmpyacc_WuhVubVub( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyubv_acc(vxx, vu, vv) +} + +/// `Vdd32.uw=vmpy(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vmpy_VuhRuh(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyuh(vu, rt) +} + +/// `Vxx32.uw+=vmpy(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vmpyacc_WuwVuhRuh( + vxx: HvxVectorPair, + vu: HvxVector, + rt: i32, +) -> HvxVectorPair { + vmpyuh_acc(vxx, vu, rt) +} + +/// `Vdd32.uw=vmpy(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vmpy_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyuhv(vu, vv) +} + +/// `Vxx32.uw+=vmpy(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuhv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vmpyacc_WuwVuhVuh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyuhv_acc(vxx, vu, vv) +} + +/// `Vd32.h=vnavg(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vnavg_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgh(vu, vv) +} + +/// `Vd32.b=vnavg(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnavgub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vnavg_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgub(vu, vv) +} + +/// `Vd32.w=vnavg(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vnavg_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgw(vu, vv) +} + +/// `Vd32.h=vnormamt(Vu32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnormamth))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vnormamt_Vh(vu: HvxVector) -> HvxVector { + vnormamth(vu) +} + +/// `Vd32.w=vnormamt(Vu32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnormamtw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vnormamt_Vw(vu: HvxVector) -> HvxVector { + vnormamtw(vu) +} + +/// `Vd32=vnot(Vu32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnot))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vnot_V(vu: HvxVector) -> HvxVector { + vnot(vu) +} + +/// `Vd32=vor(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vor_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_or(vu, vv) +} + +/// `Vd32.b=vpacke(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackeb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vpacke_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackeb(vu, vv) +} + +/// `Vd32.h=vpacke(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vpacke_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackeh(vu, vv) +} + +/// `Vd32.b=vpack(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackhb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vpack_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackhb_sat(vu, vv) +} + +/// `Vd32.ub=vpack(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackhub_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vpack_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackhub_sat(vu, vv) +} + +/// `Vd32.b=vpacko(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackob))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vpacko_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackob(vu, vv) +} + +/// `Vd32.h=vpacko(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vpacko_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackoh(vu, vv) +} + +/// `Vd32.h=vpack(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackwh_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vpack_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackwh_sat(vu, vv) +} + +/// `Vd32.uh=vpack(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackwuh_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vpack_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackwuh_sat(vu, vv) +} + +/// `Vd32.h=vpopcount(Vu32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpopcounth))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vpopcount_Vh(vu: HvxVector) -> HvxVector { + vpopcounth(vu) +} + +/// `Vd32=vrdelta(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrdelta))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vrdelta_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrdelta(vu, vv) +} + +/// `Vd32.w=vrmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vrmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVector { + vrmpybus(vu, rt) +} + +/// `Vx32.w+=vrmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vrmpyacc_VwVubRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vrmpybus_acc(vx, vu, rt) +} + +/// `Vdd32.w=vrmpy(Vuu32.ub,Rt32.b,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vrmpy_WubRbI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { + vrmpybusi(vuu, rt, iu1) +} + +/// `Vxx32.w+=vrmpy(Vuu32.ub,Rt32.b,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusi_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vrmpyacc_WwWubRbI( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, + iu1: i32, +) -> HvxVectorPair { + vrmpybusi_acc(vxx, vuu, rt, iu1) +} + +/// `Vd32.w=vrmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vrmpy_VubVb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybusv(vu, vv) +} + +/// `Vx32.w+=vrmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vrmpyacc_VwVubVb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybusv_acc(vx, vu, vv) +} + +/// `Vd32.w=vrmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vrmpy_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybv(vu, vv) +} + +/// `Vx32.w+=vrmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vrmpyacc_VwVbVb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybv_acc(vx, vu, vv) +} + +/// `Vd32.uw=vrmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vrmpy_VubRub(vu: HvxVector, rt: i32) -> HvxVector { + vrmpyub(vu, rt) +} + +/// `Vx32.uw+=vrmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyub_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vrmpyacc_VuwVubRub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vrmpyub_acc(vx, vu, rt) +} + +/// `Vdd32.uw=vrmpy(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vrmpy_WubRubI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { + vrmpyubi(vuu, rt, iu1) +} + +/// `Vxx32.uw+=vrmpy(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubi_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vrmpyacc_WuwWubRubI( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, + iu1: i32, +) -> HvxVectorPair { + vrmpyubi_acc(vxx, vuu, rt, iu1) +} + +/// `Vd32.uw=vrmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vrmpy_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpyubv(vu, vv) +} + +/// `Vx32.uw+=vrmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vrmpyacc_VuwVubVub(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpyubv_acc(vx, vu, vv) +} + +/// `Vd32=vror(Vu32,Rt32)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vror))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vror_VR(vu: HvxVector, rt: i32) -> HvxVector { + vror(vu, rt) +} + +/// `Vd32.b=vround(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vround_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundhb(vu, vv) +} + +/// `Vd32.ub=vround(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundhub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vround_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundhub(vu, vv) +} + +/// `Vd32.h=vround(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vround_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundwh(vu, vv) +} + +/// `Vd32.uh=vround(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundwuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vround_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundwuh(vu, vv) +} + +/// `Vdd32.uw=vrsad(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrsadubi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vrsad_WubRubI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { + vrsadubi(vuu, rt, iu1) +} + +/// `Vxx32.uw+=vrsad(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrsadubi_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vrsadacc_WuwWubRubI( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, + iu1: i32, +) -> HvxVectorPair { + vrsadubi_acc(vxx, vuu, rt, iu1) +} + +/// `Vd32.ub=vsat(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsathub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vsat_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsathub(vu, vv) +} + +/// `Vd32.h=vsat(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsatwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vsat_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsatwh(vu, vv) +} + +/// `Vdd32.h=vsxt(Vu32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vsxt_Vb(vu: HvxVector) -> HvxVectorPair { + vsb(vu) +} + +/// `Vdd32.w=vsxt(Vu32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vsxt_Vh(vu: HvxVector) -> HvxVectorPair { + vsh(vu) +} + +/// `Vd32.h=vshuffe(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vshuffe_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshufeh(vu, vv) +} + +/// `Vd32.b=vshuff(Vu32.b)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vshuff_Vb(vu: HvxVector) -> HvxVector { + vshuffb(vu) +} + +/// `Vd32.b=vshuffe(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffeb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vshuffe_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshuffeb(vu, vv) +} + +/// `Vd32.h=vshuff(Vu32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vshuff_Vh(vu: HvxVector) -> HvxVector { + vshuffh(vu) +} + +/// `Vd32.b=vshuffo(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffob))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vshuffo_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshuffob(vu, vv) +} + +/// `Vdd32=vshuff(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffvdd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_W_vshuff_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vshuffvdd(vu, vv, rt) +} + +/// `Vdd32.b=vshuffoe(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufoeb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wb_vshuffoe_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vshufoeb(vu, vv) +} + +/// `Vdd32.h=vshuffoe(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufoeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vshuffoe_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vshufoeh(vu, vv) +} + +/// `Vd32.h=vshuffo(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vshuffo_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshufoh(vu, vv) +} + +/// `Vd32.b=vsub(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vsub_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubb(vu, vv) +} + +/// `Vdd32.b=vsub(Vuu32.b,Vvv32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubb_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wb_vsub_WbWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubb_dv(vuu, vvv) +} + +/// `Vd32.h=vsub(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vsub_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubh(vu, vv) +} + +/// `Vdd32.h=vsub(Vuu32.h,Vvv32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubh_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vsub_WhWh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubh_dv(vuu, vvv) +} + +/// `Vd32.h=vsub(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vsub_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubhsat(vu, vv) +} + +/// `Vdd32.h=vsub(Vuu32.h,Vvv32.h):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vsub_WhWh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vsub(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vsub_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsubhw(vu, vv) +} + +/// `Vdd32.h=vsub(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsububh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vsub_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsububh(vu, vv) +} + +/// `Vd32.ub=vsub(Vu32.ub,Vv32.ub):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsububsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vsub_VubVub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsububsat(vu, vv) +} + +/// `Vdd32.ub=vsub(Vuu32.ub,Vvv32.ub):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsububsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wub_vsub_WubWub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsububsat_dv(vuu, vvv) +} + +/// `Vd32.uh=vsub(Vu32.uh,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vsub_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubuhsat(vu, vv) +} + +/// `Vdd32.uh=vsub(Vuu32.uh,Vvv32.uh):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubuhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuh_vsub_WuhWuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubuhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vsub(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubuhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vsub_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsubuhw(vu, vv) +} + +/// `Vd32.w=vsub(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vsub_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_sub(vu, vv) +} + +/// `Vdd32.w=vsub(Vuu32.w,Vvv32.w)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubw_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vsub_WwWw(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubw_dv(vuu, vvv) +} + +/// `Vd32.w=vsub(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vsub_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubwsat(vu, vv) +} + +/// `Vdd32.w=vsub(Vuu32.w,Vvv32.w):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vsub_WwWw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubwsat_dv(vuu, vvv) +} + +/// `Vdd32.h=vtmpy(Vuu32.b,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vtmpy_WbRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vtmpyb(vuu, rt) +} + +/// `Vxx32.h+=vtmpy(Vuu32.b,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vtmpyacc_WhWbRb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vtmpyb_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vtmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vtmpy_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vtmpybus(vuu, rt) +} + +/// `Vxx32.h+=vtmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vtmpyacc_WhWubRb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vtmpybus_acc(vxx, vuu, rt) +} + +/// `Vdd32.w=vtmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vtmpy_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vtmpyhb(vuu, rt) +} + +/// `Vxx32.w+=vtmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyhb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vtmpyacc_WwWhRb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vtmpyhb_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vunpack(Vu32.b)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vunpack_Vb(vu: HvxVector) -> HvxVectorPair { + vunpackb(vu) +} + +/// `Vdd32.w=vunpack(Vu32.h)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vunpack_Vh(vu: HvxVector) -> HvxVectorPair { + vunpackh(vu) +} + +/// `Vxx32.h|=vunpacko(Vu32.b)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackob))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vunpackoor_WhVb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { + vunpackob(vxx, vu) +} + +/// `Vxx32.w|=vunpacko(Vu32.h)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vunpackoor_WwVh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { + vunpackoh(vxx, vu) +} + +/// `Vdd32.uh=vunpack(Vu32.ub)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuh_vunpack_Vub(vu: HvxVector) -> HvxVectorPair { + vunpackub(vu) +} + +/// `Vdd32.uw=vunpack(Vu32.uh)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vunpack_Vuh(vu: HvxVector) -> HvxVectorPair { + vunpackuh(vu) +} + +/// `Vd32=vxor(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vxor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vxor_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_xor(vu, vv) +} + +/// `Vdd32.uh=vzxt(Vu32.ub)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vzb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuh_vzxt_Vub(vu: HvxVector) -> HvxVectorPair { + vzb(vu) +} + +/// `Vdd32.uw=vzxt(Vu32.uh)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vzh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vzxt_Vuh(vu: HvxVector) -> HvxVectorPair { + vzh(vu) +} + +/// `Vd32.b=vsplat(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(lvsplatb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vsplat_R(rt: i32) -> HvxVector { + lvsplatb(rt) +} + +/// `Vd32.h=vsplat(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(lvsplath))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vsplat_R(rt: i32) -> HvxVector { + lvsplath(rt) +} + +/// `Vd32.b=vadd(Vu32.b,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddbsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vadd_VbVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddbsat(vu, vv) +} + +/// `Vdd32.b=vadd(Vuu32.b,Vvv32.b):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddbsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wb_vadd_WbWb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddbsat_dv(vuu, vvv) +} + +/// `Vd32.h=vadd(vclb(Vu32.h),Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddclbh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vadd_vclb_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddclbh(vu, vv) +} + +/// `Vd32.w=vadd(vclb(Vu32.w),Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddclbw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vadd_vclb_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddclbw(vu, vv) +} + +/// `Vxx32.w+=vadd(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddhw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vaddacc_WwVhVh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vaddhw_acc(vxx, vu, vv) +} + +/// `Vxx32.h+=vadd(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddubh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vaddacc_WhVubVub( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vaddubh_acc(vxx, vu, vv) +} + +/// `Vd32.ub=vadd(Vu32.ub,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddububb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vadd_VubVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddububb_sat(vu, vv) +} + +/// `Vxx32.w+=vadd(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vadduhw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vaddacc_WwVuhVuh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vadduhw_acc(vxx, vu, vv) +} + +/// `Vd32.uw=vadd(Vu32.uw,Vv32.uw):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vadduwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vadd_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadduwsat(vu, vv) +} + +/// `Vdd32.uw=vadd(Vuu32.uw,Vvv32.uw):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vadduwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vadd_WuwWuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vadduwsat_dv(vuu, vvv) +} + +/// `Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vasrhbsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vasr_VhVhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhbsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vasruwuhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vasr_VuwVuwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruwuhrndsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vasrwuhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vasr_VwVwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwuhrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vlsr(Vu32.ub,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlsrb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vlsr_VubR(vu: HvxVector, rt: i32) -> HvxVector { + vlsrb(vu, rt) +} + +/// `Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8):nomatch` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvvb_nm))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vlut32_VbVbR_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vlutvvb_nm(vu, vv, rt) +} + +/// `Vx32.b|=vlut32(Vu32.b,Vv32.b,#u3)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvvb_oracci))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vlut32or_VbVbVbI( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, + iu3: i32, +) -> HvxVector { + vlutvvb_oracci(vx, vu, vv, iu3) +} + +/// `Vd32.b=vlut32(Vu32.b,Vv32.b,#u3)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvvbi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vlut32_VbVbI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { + vlutvvbi(vu, vv, iu3) +} + +/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8):nomatch` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvwh_nm))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vlut16_VbVhR_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vlutvwh_nm(vu, vv, rt) +} + +/// `Vxx32.h|=vlut16(Vu32.b,Vv32.h,#u3)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvwh_oracci))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vlut16or_WhVbVhI( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, + iu3: i32, +) -> HvxVectorPair { + vlutvwh_oracci(vxx, vu, vv, iu3) +} + +/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,#u3)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvwhi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vlut16_VbVhI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVectorPair { + vlutvwhi(vu, vv, iu3) +} + +/// `Vd32.b=vmax(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmaxb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vmax_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxb(vu, vv) +} + +/// `Vd32.b=vmin(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vminb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vmin_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminb(vu, vv) +} + +/// `Vdd32.w=vmpa(Vuu32.uh,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpauhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vmpa_WuhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpauhb(vuu, rt) +} + +/// `Vxx32.w+=vmpa(Vuu32.uh,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpauhb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vmpaacc_WwWuhRb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpauhb_acc(vxx, vuu, rt) +} + +/// `Vdd32=vmpye(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyewuh_64))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_W_vmpye_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyewuh_64(vu, vv) +} + +/// `Vd32.w=vmpyi(Vu32.w,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyiwub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyi_VwRub(vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwub(vu, rt) +} + +/// `Vx32.w+=vmpyi(Vu32.w,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyiwub_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vmpyiacc_VwVwRub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwub_acc(vx, vu, rt) +} + +/// `Vxx32+=vmpyo(Vu32.w,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyowh_64_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_W_vmpyoacc_WVwVh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyowh_64_acc(vxx, vu, vv) +} + +/// `Vd32.ub=vround(Vu32.uh,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vrounduhub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vround_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrounduhub(vu, vv) +} + +/// `Vd32.uh=vround(Vu32.uw,Vv32.uw):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vrounduwuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vround_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrounduwuh(vu, vv) +} + +/// `Vd32.uh=vsat(Vu32.uw,Vv32.uw)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsatuwuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vsat_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsatuwuh(vu, vv) +} + +/// `Vd32.b=vsub(Vu32.b,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubbsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vsub_VbVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubbsat(vu, vv) +} + +/// `Vdd32.b=vsub(Vuu32.b,Vvv32.b):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubbsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wb_vsub_WbWb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubbsat_dv(vuu, vvv) +} + +/// `Vd32.ub=vsub(Vu32.ub,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubububb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vsub_VubVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubububb_sat(vu, vv) +} + +/// `Vd32.uw=vsub(Vu32.uw,Vv32.uw):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubuwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vsub_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubuwsat(vu, vv) +} + +/// `Vdd32.uw=vsub(Vuu32.uw,Vvv32.uw):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubuwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wuw_vsub_WuwWuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubuwsat_dv(vuu, vvv) +} + +/// `Vd32.b=vabs(Vu32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vabsb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vabs_Vb(vu: HvxVector) -> HvxVector { + vabsb(vu) +} + +/// `Vd32.b=vabs(Vu32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vabsb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vabs_Vb_sat(vu: HvxVector) -> HvxVector { + vabsb_sat(vu) +} + +/// `Vx32.h+=vasl(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vaslh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vaslacc_VhVhR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vaslh_acc(vx, vu, rt) +} + +/// `Vx32.h+=vasr(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasrh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vasracc_VhVhR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vasrh_acc(vx, vu, rt) +} + +/// `Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasruhubrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vasr_VuhVuhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruhubrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasruhubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vasr_VuhVuhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruhubsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasruwuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vasr_VuwVuwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruwuhsat(vu, vv, rt) +} + +/// `Vd32.b=vavg(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavgb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vavg_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgb(vu, vv) +} + +/// `Vd32.b=vavg(Vu32.b,Vv32.b):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavgbrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vavg_VbVb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgbrnd(vu, vv) +} + +/// `Vd32.uw=vavg(Vu32.uw,Vv32.uw)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavguw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vavg_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguw(vu, vv) +} + +/// `Vd32.uw=vavg(Vu32.uw,Vv32.uw):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavguwrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vavg_VuwVuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguwrnd(vu, vv) +} + +/// `Vdd32=#0` +/// +/// Instruction Type: MAPPING +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vdd0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_W_vzero() -> HvxVectorPair { + vdd0() +} + +/// `vtmp.h=vgather(Rt32,Mu2,Vv32.h).h` +/// +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vgathermh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vgather_ARMVh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { + vgathermh(rs, rt, mu, vv) +} + +/// `vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h` +/// +/// Instruction Type: CVI_GATHER_DV +/// Execution Slots: SLOT01 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vgathermhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vgather_ARMWw(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVectorPair) { + vgathermhw(rs, rt, mu, vvv) +} + +/// `vtmp.w=vgather(Rt32,Mu2,Vv32.w).w` +/// +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vgathermw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vgather_ARMVw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { + vgathermw(rs, rt, mu, vv) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpabuu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpa_WubRub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpabuu(vuu, rt) +} + +/// `Vxx32.h+=vmpa(Vuu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpabuu_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wh_vmpaacc_WhWubRub( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpabuu_acc(vxx, vuu, rt) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpyh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vmpyacc_WwVhRh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyh_acc(vxx, vu, rt) +} + +/// `Vd32.uw=vmpye(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpyuhe))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vmpye_VuhRuh(vu: HvxVector, rt: i32) -> HvxVector { + vmpyuhe(vu, rt) +} + +/// `Vx32.uw+=vmpye(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpyuhe_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vmpyeacc_VuwVuhRuh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyuhe_acc(vx, vu, rt) +} + +/// `Vd32.b=vnavg(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vnavgb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vnavg_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgb(vu, vv) +} + +/// `vscatter(Rt32,Mu2,Vv32.h).h=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vscatter_RMVhV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermh(rt, mu, vv, vw) +} + +/// `vscatter(Rt32,Mu2,Vv32.h).h+=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermh_add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vscatteracc_RMVhV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermh_add(rt, mu, vv, vw) +} + +/// `vscatter(Rt32,Mu2,Vvv32.w).h=Vw32` +/// +/// Instruction Type: CVI_SCATTER_DV +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vscatter_RMWwV(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { + vscattermhw(rt, mu, vvv, vw) +} + +/// `vscatter(Rt32,Mu2,Vvv32.w).h+=Vw32` +/// +/// Instruction Type: CVI_SCATTER_DV +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermhw_add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vscatteracc_RMWwV(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { + vscattermhw_add(rt, mu, vvv, vw) +} + +/// `vscatter(Rt32,Mu2,Vv32.w).w=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vscatter_RMVwV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermw(rt, mu, vv, vw) +} + +/// `vscatter(Rt32,Mu2,Vv32.w).w+=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermw_add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vscatteracc_RMVwV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermw_add(rt, mu, vv, vw) +} + +/// `Vxx32.w=vasrinto(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[cfg_attr(test, assert_instr(vasr_into))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_vasrinto_WwVwVw( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vasr_into(vxx, vu, vv) +} + +/// `Vd32.uw=vrotr(Vu32.uw,Vv32.uw)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[cfg_attr(test, assert_instr(vrotr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuw_vrotr_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrotr(vu, vv) +} + +/// `Vd32.w=vsatdw(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[cfg_attr(test, assert_instr(vsatdw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vsatdw_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsatdw(vu, vv) +} + +/// `Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):h` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyhubs10))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_v6mpy_WubWbI_h( + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyhubs10(vuu, vvv, iu2) +} + +/// `Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):h` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyhubs10_vxx))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_v6mpyacc_WwWubWbI_h( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyhubs10_vxx(vxx, vuu, vvv, iu2) +} + +/// `Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):v` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyvubs10))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_v6mpy_WubWbI_v( + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyvubs10(vuu, vvv, iu2) +} + +/// `Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):v` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyvubs10_vxx))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Ww_v6mpyacc_WwWubWbI_v( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyvubs10_vxx(vxx, vuu, vvv, iu2) +} + +/// `Vd32.hf=vabs(Vu32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vabs_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vabs_Vhf(vu: HvxVector) -> HvxVector { + vabs_hf(vu) +} + +/// `Vd32.sf=vabs(Vu32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vabs_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_vabs_Vsf(vu: HvxVector) -> HvxVector { + vabs_sf(vu) +} + +/// `Vd32.qf16=vadd(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf16_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_hf(vu, vv) +} + +/// `Vd32.hf=vadd(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_hf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_hf_hf(vu, vv) +} + +/// `Vd32.qf16=vadd(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf16_vadd_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf16(vu, vv) +} + +/// `Vd32.qf16=vadd(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf16_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf16_vadd_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf16_mix(vu, vv) +} + +/// `Vd32.qf32=vadd(Vu32.qf32,Vv32.qf32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf32_vadd_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf32(vu, vv) +} + +/// `Vd32.qf32=vadd(Vu32.qf32,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf32_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf32_vadd_Vqf32Vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf32_mix(vu, vv) +} + +/// `Vd32.qf32=vadd(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf32_vadd_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_sf(vu, vv) +} + +/// `Vdd32.sf=vadd(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wsf_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vadd_sf_hf(vu, vv) +} + +/// `Vd32.sf=vadd(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_sf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_vadd_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_sf_sf(vu, vv) +} + +/// `Vd32.w=vfmv(Vu32.w)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vassign_fp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vfmv_Vw(vu: HvxVector) -> HvxVector { + vassign_fp(vu) +} + +/// `Vd32.hf=Vu32.qf16` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vconv_hf_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_equals_Vqf16(vu: HvxVector) -> HvxVector { + vconv_hf_qf16(vu) +} + +/// `Vd32.hf=Vuu32.qf32` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vconv_hf_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_equals_Wqf32(vuu: HvxVectorPair) -> HvxVector { + vconv_hf_qf32(vuu) +} + +/// `Vd32.sf=Vu32.qf32` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vconv_sf_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_equals_Vqf32(vu: HvxVector) -> HvxVector { + vconv_sf_qf32(vu) +} + +/// `Vd32.b=vcvt(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_b_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_vcvt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vcvt_b_hf(vu, vv) +} + +/// `Vd32.h=vcvt(Vu32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_h_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_vcvt_Vhf(vu: HvxVector) -> HvxVector { + vcvt_h_hf(vu) +} + +/// `Vdd32.hf=vcvt(Vu32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_b))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Whf_vcvt_Vb(vu: HvxVector) -> HvxVectorPair { + vcvt_hf_b(vu) +} + +/// `Vd32.hf=vcvt(Vu32.h)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_h))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vcvt_Vh(vu: HvxVector) -> HvxVector { + vcvt_hf_h(vu) +} + +/// `Vd32.hf=vcvt(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vcvt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vcvt_hf_sf(vu, vv) +} + +/// `Vdd32.hf=vcvt(Vu32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_ub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Whf_vcvt_Vub(vu: HvxVector) -> HvxVectorPair { + vcvt_hf_ub(vu) +} + +/// `Vd32.hf=vcvt(Vu32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_uh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vcvt_Vuh(vu: HvxVector) -> HvxVector { + vcvt_hf_uh(vu) +} + +/// `Vdd32.sf=vcvt(Vu32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wsf_vcvt_Vhf(vu: HvxVector) -> HvxVectorPair { + vcvt_sf_hf(vu) +} + +/// `Vd32.ub=vcvt(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_ub_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vcvt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vcvt_ub_hf(vu, vv) +} + +/// `Vd32.uh=vcvt(Vu32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_uh_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vcvt_Vhf(vu: HvxVector) -> HvxVector { + vcvt_uh_hf(vu) +} + +/// `Vd32.sf=vdmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vdmpy_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_vdmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpy_sf_hf(vu, vv) +} + +/// `Vx32.sf+=vdmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vdmpy_sf_hf_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_vdmpyacc_VsfVhfVhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpy_sf_hf_acc(vx, vu, vv) +} + +/// `Vd32.hf=vfmax(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmax_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vfmax_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmax_hf(vu, vv) +} + +/// `Vd32.sf=vfmax(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmax_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_vfmax_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmax_sf(vu, vv) +} + +/// `Vd32.hf=vfmin(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmin_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vfmin_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmin_hf(vu, vv) +} + +/// `Vd32.sf=vfmin(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmin_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_vfmin_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmin_sf(vu, vv) +} + +/// `Vd32.hf=vfneg(Vu32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfneg_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vfneg_Vhf(vu: HvxVector) -> HvxVector { + vfneg_hf(vu) +} + +/// `Vd32.sf=vfneg(Vu32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfneg_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_vfneg_Vsf(vu: HvxVector) -> HvxVector { + vfneg_sf(vu) +} + +/// `Vd32.hf=vmax(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmax_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vmax_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmax_hf(vu, vv) +} + +/// `Vd32.sf=vmax(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmax_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_vmax_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmax_sf(vu, vv) +} + +/// `Vd32.hf=vmin(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmin_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vmin_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmin_hf(vu, vv) +} + +/// `Vd32.sf=vmin(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmin_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_vmin_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmin_sf(vu, vv) +} + +/// `Vd32.hf=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_hf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_hf_hf(vu, vv) +} + +/// `Vx32.hf+=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_hf_hf_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vmpyacc_VhfVhfVhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_hf_hf_acc(vx, vu, vv) +} + +/// `Vd32.qf16=vmpy(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf16_vmpy_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf16(vu, vv) +} + +/// `Vd32.qf16=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf16_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf16_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf16_hf(vu, vv) +} + +/// `Vd32.qf16=vmpy(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf16_mix_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf16_vmpy_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf16_mix_hf(vu, vv) +} + +/// `Vd32.qf32=vmpy(Vu32.qf32,Vv32.qf32)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf32_vmpy_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf32(vu, vv) +} + +/// `Vdd32.qf32=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wqf32_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_qf32_hf(vu, vv) +} + +/// `Vdd32.qf32=vmpy(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_mix_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wqf32_vmpy_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_qf32_mix_hf(vu, vv) +} + +/// `Vdd32.qf32=vmpy(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wqf32_vmpy_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_qf32_qf16(vu, vv) +} + +/// `Vd32.qf32=vmpy(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf32_vmpy_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf32_sf(vu, vv) +} + +/// `Vdd32.sf=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wsf_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_sf_hf(vu, vv) +} + +/// `Vxx32.sf+=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_sf_hf_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wsf_vmpyacc_WsfVhfVhf( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpy_sf_hf_acc(vxx, vu, vv) +} + +/// `Vd32.sf=vmpy(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_sf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_vmpy_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_sf_sf(vu, vv) +} + +/// `Vd32.qf16=vsub(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf16_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_hf(vu, vv) +} + +/// `Vd32.hf=vsub(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_hf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_hf_hf(vu, vv) +} + +/// `Vd32.qf16=vsub(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf16_vsub_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf16(vu, vv) +} + +/// `Vd32.qf16=vsub(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf16_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf16_vsub_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf16_mix(vu, vv) +} + +/// `Vd32.qf32=vsub(Vu32.qf32,Vv32.qf32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf32_vsub_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf32(vu, vv) +} + +/// `Vd32.qf32=vsub(Vu32.qf32,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf32_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf32_vsub_Vqf32Vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf32_mix(vu, vv) +} + +/// `Vd32.qf32=vsub(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vqf32_vsub_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_sf(vu, vv) +} + +/// `Vdd32.sf=vsub(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Wsf_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsub_sf_hf(vu, vv) +} + +/// `Vd32.sf=vsub(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_sf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_vsub_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_sf_sf(vu, vv) +} + +/// `Vd32.ub=vasr(Vuu32.uh,Vv32.ub):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvuhubrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vasr_WuhVub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvuhubrndsat(vuu, vv) +} + +/// `Vd32.ub=vasr(Vuu32.uh,Vv32.ub):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvuhubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vub_vasr_WuhVub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvuhubsat(vuu, vv) +} + +/// `Vd32.uh=vasr(Vuu32.w,Vv32.uh):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvwuhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vasr_WwVuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvwuhrndsat(vuu, vv) +} + +/// `Vd32.uh=vasr(Vuu32.w,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvwuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vasr_WwVuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvwuhsat(vuu, vv) +} + +/// `Vd32.uh=vmpy(Vu32.uh,Vv32.uh):>>16` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vmpyuhvs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vuh_vmpy_VuhVuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyuhvs(vu, vv) +} + +/// `Vd32.h=Vu32.hf` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_h_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_equals_Vhf(vu: HvxVector) -> HvxVector { + vconv_h_hf(vu) +} + +/// `Vd32.hf=Vu32.h` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_hf_h))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vhf_equals_Vh(vu: HvxVector) -> HvxVector { + vconv_hf_h(vu) +} + +/// `Vd32.sf=Vu32.w` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_sf_w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vsf_equals_Vw(vu: HvxVector) -> HvxVector { + vconv_sf_w(vu) +} + +/// `Vd32.w=Vu32.sf` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_w_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_equals_Vsf(vu: HvxVector) -> HvxVector { + vconv_w_sf(vu) +} + +/// `Vd32=vgetqfext(Vu32.x,Rt32)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(get_qfext))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vgetqfext_VR(vu: HvxVector, rt: i32) -> HvxVector { + get_qfext(vu, rt) +} + +/// `Vd32.x=vsetqfext(Vu32,Rt32)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(set_qfext))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vsetqfext_VR(vu: HvxVector, rt: i32) -> HvxVector { + set_qfext(vu, rt) +} + +/// `Vd32.f8=vabs(Vu32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vabs_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vabs_V(vu: HvxVector) -> HvxVector { + vabs_f8(vu) +} + +/// `Vdd32.hf=vcvt2(Vu32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vcvt2_hf_b))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Whf_vcvt2_Vb(vu: HvxVector) -> HvxVectorPair { + vcvt2_hf_b(vu) +} + +/// `Vdd32.hf=vcvt2(Vu32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vcvt2_hf_ub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Whf_vcvt2_Vub(vu: HvxVector) -> HvxVectorPair { + vcvt2_hf_ub(vu) +} + +/// `Vdd32.hf=vcvt(Vu32.f8)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vcvt_hf_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Whf_vcvt_V(vu: HvxVector) -> HvxVectorPair { + vcvt_hf_f8(vu) +} + +/// `Vd32.f8=vfmax(Vu32.f8,Vv32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vfmax_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vfmax_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmax_f8(vu, vv) +} + +/// `Vd32.f8=vfmin(Vu32.f8,Vv32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vfmin_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vfmin_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmin_f8(vu, vv) +} + +/// `Vd32.f8=vfneg(Vu32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vfneg_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vfneg_V(vu: HvxVector) -> HvxVector { + vfneg_f8(vu) +} + +/// `Qd4=and(Qs4,Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_and_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_and( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=and(Qs4,!Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_and_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_and_n( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=not(Qs4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_not_Q(qs: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_not(vandvrt( + core::mem::transmute::(qs), + -1, + )), + -1, + )) +} + +/// `Qd4=or(Qs4,Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_or_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_or( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=or(Qs4,!Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_or_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_or_n( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=vsetq(Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vsetq_R(rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt(pred_scalar2(rt), -1)) +} + +/// `Qd4=xor(Qs4,Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_xor_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_xor( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `if (!Qv4) vmem(Rt32+#s4)=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vmem_QnRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_nqpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (!Qv4) vmem(Rt32+#s4):nt=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vmem_QnRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_nt_nqpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (Qv4) vmem(Rt32+#s4):nt=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vmem_QRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_nt_qpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (Qv4) vmem(Rt32+#s4)=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vmem_QRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_qpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (!Qv4) Vx32.b+=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_condacc_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddbnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.b+=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_condacc_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddbq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.h+=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_condacc_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddhnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.h+=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_condacc_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddhq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.w+=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_condacc_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddwnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.w+=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_condacc_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddwq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `Vd32=vand(Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vand_QR(qu: HvxVectorPred, rt: i32) -> HvxVector { + vandvrt(core::mem::transmute::(qu), rt) +} + +/// `Vx32|=vand(Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vandor_VQR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { + vandvrt_acc(vx, core::mem::transmute::(qu), rt) +} + +/// `Qd4=vand(Vu32,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vand_VR(vu: HvxVector, rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vu, rt)) +} + +/// `Qx4|=vand(Vu32,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vandor_QVR(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt_acc( + core::mem::transmute::(qx), + vu, + rt, + )) +} + +/// `Qd4=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eq_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(veqb(vu, vv), -1)) +} + +/// `Qx4&=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eqand_QVbVb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqb_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eqor_QVbVb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqb_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eqxacc_QVbVb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqb_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eq_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(veqh(vu, vv), -1)) +} + +/// `Qx4&=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eqand_QVhVh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqh_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eqor_QVhVh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqh_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eqxacc_QVhVh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqh_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eq_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(veqw(vu, vv), -1)) +} + +/// `Qx4&=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eqand_QVwVw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqw_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eqor_QVwVw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqw_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_eqxacc_QVwVw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqw_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gt_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtb(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtand_QVbVb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtb_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtor_QVbVb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtb_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtxacc_QVbVb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtb_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gt_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgth(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtand_QVhVh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgth_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtor_QVhVh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgth_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtxacc_QVhVh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgth_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gt_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtub(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtand_QVubVub( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtub_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtor_QVubVub( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtub_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtxacc_QVubVub( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtub_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gt_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtuh(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtand_QVuhVuh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuh_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtor_QVuhVuh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuh_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtxacc_QVuhVuh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuh_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gt_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtuw(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtand_QVuwVuw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuw_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtor_QVuwVuw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuw_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtxacc_QVuwVuw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuw_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gt_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtw(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtand_QVwVw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtw_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtor_QVwVw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtw_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtxacc_QVwVw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtw_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Vd32=vmux(Qt4,Vu32,Vv32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vmux_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmux( + vandvrt(core::mem::transmute::(qt), -1), + vu, + vv, + ) +} + +/// `if (!Qv4) Vx32.b-=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_condnac_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubbnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.b-=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_condnac_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubbq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.h-=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_condnac_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubhnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.h-=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_condnac_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubhq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.w-=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_condnac_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubwnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.w-=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_condnac_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubwq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `Vdd32=vswap(Qt4,Vu32,Vv32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_W_vswap_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vswap( + vandvrt(core::mem::transmute::(qt), -1), + vu, + vv, + ) +} + +/// `Qd4=vsetq2(Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vsetq2_R(rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt(pred_scalar2v2(rt), -1)) +} + +/// `Qd4.b=vshuffe(Qs4.h,Qt4.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Qb_vshuffe_QhQh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + shuffeqh( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4.h=vshuffe(Qs4.w,Qt4.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Qh_vshuffe_QwQw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + shuffeqw( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Vd32=vand(!Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vand_QnR(qu: HvxVectorPred, rt: i32) -> HvxVector { + vandnqrt( + vandvrt(core::mem::transmute::(qu), -1), + rt, + ) +} + +/// `Vx32|=vand(!Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vandor_VQnR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { + vandnqrt_acc( + vx, + vandvrt(core::mem::transmute::(qu), -1), + rt, + ) +} + +/// `Vd32=vand(!Qv4,Vu32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vand_QnV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { + vandvnqv( + vandvrt(core::mem::transmute::(qv), -1), + vu, + ) +} + +/// `Vd32=vand(Qv4,Vu32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_V_vand_QV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { + vandvqv( + vandvrt(core::mem::transmute::(qv), -1), + vu, + ) +} + +/// `if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vv32.h).h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vgather_AQRMVh( + rs: *mut HvxVector, + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, +) { + vgathermhq( + rs, + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + ) +} + +/// `if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_GATHER_DV +/// Execution Slots: SLOT01 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vgather_AQRMWw( + rs: *mut HvxVector, + qs: HvxVectorPred, + rt: i32, + mu: i32, + vvv: HvxVectorPair, +) { + vgathermhwq( + rs, + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vvv, + ) +} + +/// `if (Qs4) vtmp.w=vgather(Rt32,Mu2,Vv32.w).w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vgather_AQRMVw( + rs: *mut HvxVector, + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, +) { + vgathermwq( + rs, + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + ) +} + +/// `Vd32.b=prefixsum(Qv4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vb_prefixsum_Q(qv: HvxVectorPred) -> HvxVector { + vprefixqb(vandvrt( + core::mem::transmute::(qv), + -1, + )) +} + +/// `Vd32.h=prefixsum(Qv4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vh_prefixsum_Q(qv: HvxVectorPred) -> HvxVector { + vprefixqh(vandvrt( + core::mem::transmute::(qv), + -1, + )) +} + +/// `Vd32.w=prefixsum(Qv4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_prefixsum_Q(qv: HvxVectorPred) -> HvxVector { + vprefixqw(vandvrt( + core::mem::transmute::(qv), + -1, + )) +} + +/// `if (Qs4) vscatter(Rt32,Mu2,Vv32.h).h=Vw32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vscatter_QRMVhV( + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, + vw: HvxVector, +) { + vscattermhq( + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + vw, + ) +} + +/// `if (Qs4) vscatter(Rt32,Mu2,Vvv32.w).h=Vw32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_SCATTER_DV +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vscatter_QRMWwV( + qs: HvxVectorPred, + rt: i32, + mu: i32, + vvv: HvxVectorPair, + vw: HvxVector, +) { + vscattermhwq( + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vvv, + vw, + ) +} + +/// `if (Qs4) vscatter(Rt32,Mu2,Vv32.w).w=Vw32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_vscatter_QRMVwV( + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, + vw: HvxVector, +) { + vscattermwq( + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + vw, + ) +} + +/// `Vd32.w=vadd(Vu32.w,Vv32.w,Qs4):carry:sat` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Vw_vadd_VwVwQ_carry_sat( + vu: HvxVector, + vv: HvxVector, + qs: HvxVectorPred, +) -> HvxVector { + vaddcarrysat( + vu, + vv, + vandvrt(core::mem::transmute::(qs), -1), + ) +} + +/// `Qd4=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgthf(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtand_QVhfVhf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgthf_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtor_QVhfVhf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgthf_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtxacc_QVhfVhf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgthf_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtsf(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtand_QVsfVsf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtsf_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtor_QVsfVsf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtsf_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Q_vcmp_gtxacc_QVsfVsf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtsf_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} diff --git a/library/stdarch/crates/core_arch/src/lib.rs b/library/stdarch/crates/core_arch/src/lib.rs index 039a4c4411f2e..57eca221e1aba 100644 --- a/library/stdarch/crates/core_arch/src/lib.rs +++ b/library/stdarch/crates/core_arch/src/lib.rs @@ -23,6 +23,7 @@ mips_target_feature, powerpc_target_feature, loongarch_target_feature, + hexagon_target_feature, wasm_target_feature, abi_unadjusted, rtm_target_feature, @@ -32,13 +33,15 @@ x86_amx_intrinsics, f16, aarch64_unstable_target_feature, - target_feature_inline_always, funnel_shifts, avx10_target_feature, const_trait_impl, const_cmp, const_eval_select, - maybe_uninit_as_bytes + maybe_uninit_as_bytes, + movrs_target_feature, + clflushopt_target_feature, + min_adt_const_params )] #![cfg_attr(test, feature(test, abi_vectorcall, stdarch_internal))] #![deny(clippy::missing_inline_in_public_items)] @@ -57,7 +60,9 @@ clippy::shadow_reuse, clippy::similar_names, clippy::unusual_byte_groupings, - clippy::wrong_self_convention + clippy::wrong_self_convention, + clippy::zero_prefixed_literal, + clippy::tabs_in_doc_comments )] #![cfg_attr(test, allow(unused_imports))] #![no_std] @@ -68,7 +73,11 @@ )] #![cfg_attr( test, - feature(stdarch_arm_feature_detection, stdarch_powerpc_feature_detection,) + feature( + stdarch_arm_feature_detection, + stdarch_mips_feature_detection, + stdarch_powerpc_feature_detection, + ) )] #[cfg(test)] diff --git a/library/stdarch/crates/core_arch/src/loongarch32/mod.rs b/library/stdarch/crates/core_arch/src/loongarch32/mod.rs index 4e3f3d27182e4..6cc1116113e1d 100644 --- a/library/stdarch/crates/core_arch/src/loongarch32/mod.rs +++ b/library/stdarch/crates/core_arch/src/loongarch32/mod.rs @@ -15,7 +15,7 @@ unsafe extern "unadjusted" { } /// Generates the cache operation instruction -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn cacop(b: i32) { static_assert_uimm_bits!(IMM5, 5); @@ -24,7 +24,7 @@ pub unsafe fn cacop(b: i32) { } /// Reads the CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn csrrd() -> i32 { static_assert_uimm_bits!(IMM14, 14); @@ -32,7 +32,7 @@ pub unsafe fn csrrd() -> i32 { } /// Writes the CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn csrwr(a: i32) -> i32 { static_assert_uimm_bits!(IMM14, 14); @@ -40,7 +40,7 @@ pub unsafe fn csrwr(a: i32) -> i32 { } /// Exchanges the CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn csrxchg(a: i32, b: i32) -> i32 { static_assert_uimm_bits!(IMM14, 14); diff --git a/library/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs b/library/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs index cda0ebec67799..711ade40391a9 100644 --- a/library/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs +++ b/library/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs @@ -7,42 +7,10 @@ // ``` use crate::mem::transmute; -use super::types::*; +use super::super::*; #[allow(improper_ctypes)] unsafe extern "unadjusted" { - #[link_name = "llvm.loongarch.lasx.xvsll.b"] - fn __lasx_xvsll_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvsll.h"] - fn __lasx_xvsll_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvsll.w"] - fn __lasx_xvsll_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvsll.d"] - fn __lasx_xvsll_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvslli.b"] - fn __lasx_xvslli_b(a: __v32i8, b: u32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvslli.h"] - fn __lasx_xvslli_h(a: __v16i16, b: u32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvslli.w"] - fn __lasx_xvslli_w(a: __v8i32, b: u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvslli.d"] - fn __lasx_xvslli_d(a: __v4i64, b: u32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvsra.b"] - fn __lasx_xvsra_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvsra.h"] - fn __lasx_xvsra_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvsra.w"] - fn __lasx_xvsra_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvsra.d"] - fn __lasx_xvsra_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvsrai.b"] - fn __lasx_xvsrai_b(a: __v32i8, b: u32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvsrai.h"] - fn __lasx_xvsrai_h(a: __v16i16, b: u32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvsrai.w"] - fn __lasx_xvsrai_w(a: __v8i32, b: u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvsrai.d"] - fn __lasx_xvsrai_d(a: __v4i64, b: u32) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvsrar.b"] fn __lasx_xvsrar_b(a: __v32i8, b: __v32i8) -> __v32i8; #[link_name = "llvm.loongarch.lasx.xvsrar.h"] @@ -59,22 +27,6 @@ unsafe extern "unadjusted" { fn __lasx_xvsrari_w(a: __v8i32, b: u32) -> __v8i32; #[link_name = "llvm.loongarch.lasx.xvsrari.d"] fn __lasx_xvsrari_d(a: __v4i64, b: u32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvsrl.b"] - fn __lasx_xvsrl_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvsrl.h"] - fn __lasx_xvsrl_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvsrl.w"] - fn __lasx_xvsrl_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvsrl.d"] - fn __lasx_xvsrl_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvsrli.b"] - fn __lasx_xvsrli_b(a: __v32i8, b: u32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvsrli.h"] - fn __lasx_xvsrli_h(a: __v16i16, b: u32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvsrli.w"] - fn __lasx_xvsrli_w(a: __v8i32, b: u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvsrli.d"] - fn __lasx_xvsrli_d(a: __v4i64, b: u32) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvsrlr.b"] fn __lasx_xvsrlr_b(a: __v32i8, b: __v32i8) -> __v32i8; #[link_name = "llvm.loongarch.lasx.xvsrlr.h"] @@ -91,14 +43,6 @@ unsafe extern "unadjusted" { fn __lasx_xvsrlri_w(a: __v8i32, b: u32) -> __v8i32; #[link_name = "llvm.loongarch.lasx.xvsrlri.d"] fn __lasx_xvsrlri_d(a: __v4i64, b: u32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvbitclr.b"] - fn __lasx_xvbitclr_b(a: __v32u8, b: __v32u8) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvbitclr.h"] - fn __lasx_xvbitclr_h(a: __v16u16, b: __v16u16) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvbitclr.w"] - fn __lasx_xvbitclr_w(a: __v8u32, b: __v8u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvbitclr.d"] - fn __lasx_xvbitclr_d(a: __v4u64, b: __v4u64) -> __v4u64; #[link_name = "llvm.loongarch.lasx.xvbitclri.b"] fn __lasx_xvbitclri_b(a: __v32u8, b: u32) -> __v32u8; #[link_name = "llvm.loongarch.lasx.xvbitclri.h"] @@ -107,14 +51,6 @@ unsafe extern "unadjusted" { fn __lasx_xvbitclri_w(a: __v8u32, b: u32) -> __v8u32; #[link_name = "llvm.loongarch.lasx.xvbitclri.d"] fn __lasx_xvbitclri_d(a: __v4u64, b: u32) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvbitset.b"] - fn __lasx_xvbitset_b(a: __v32u8, b: __v32u8) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvbitset.h"] - fn __lasx_xvbitset_h(a: __v16u16, b: __v16u16) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvbitset.w"] - fn __lasx_xvbitset_w(a: __v8u32, b: __v8u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvbitset.d"] - fn __lasx_xvbitset_d(a: __v4u64, b: __v4u64) -> __v4u64; #[link_name = "llvm.loongarch.lasx.xvbitseti.b"] fn __lasx_xvbitseti_b(a: __v32u8, b: u32) -> __v32u8; #[link_name = "llvm.loongarch.lasx.xvbitseti.h"] @@ -123,14 +59,6 @@ unsafe extern "unadjusted" { fn __lasx_xvbitseti_w(a: __v8u32, b: u32) -> __v8u32; #[link_name = "llvm.loongarch.lasx.xvbitseti.d"] fn __lasx_xvbitseti_d(a: __v4u64, b: u32) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvbitrev.b"] - fn __lasx_xvbitrev_b(a: __v32u8, b: __v32u8) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvbitrev.h"] - fn __lasx_xvbitrev_h(a: __v16u16, b: __v16u16) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvbitrev.w"] - fn __lasx_xvbitrev_w(a: __v8u32, b: __v8u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvbitrev.d"] - fn __lasx_xvbitrev_d(a: __v4u64, b: __v4u64) -> __v4u64; #[link_name = "llvm.loongarch.lasx.xvbitrevi.b"] fn __lasx_xvbitrevi_b(a: __v32u8, b: u32) -> __v32u8; #[link_name = "llvm.loongarch.lasx.xvbitrevi.h"] @@ -139,30 +67,6 @@ unsafe extern "unadjusted" { fn __lasx_xvbitrevi_w(a: __v8u32, b: u32) -> __v8u32; #[link_name = "llvm.loongarch.lasx.xvbitrevi.d"] fn __lasx_xvbitrevi_d(a: __v4u64, b: u32) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvadd.b"] - fn __lasx_xvadd_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvadd.h"] - fn __lasx_xvadd_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvadd.w"] - fn __lasx_xvadd_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvadd.d"] - fn __lasx_xvadd_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvaddi.bu"] - fn __lasx_xvaddi_bu(a: __v32i8, b: u32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvaddi.hu"] - fn __lasx_xvaddi_hu(a: __v16i16, b: u32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvaddi.wu"] - fn __lasx_xvaddi_wu(a: __v8i32, b: u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvaddi.du"] - fn __lasx_xvaddi_du(a: __v4i64, b: u32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvsub.b"] - fn __lasx_xvsub_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvsub.h"] - fn __lasx_xvsub_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvsub.w"] - fn __lasx_xvsub_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvsub.d"] - fn __lasx_xvsub_d(a: __v4i64, b: __v4i64) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvsubi.bu"] fn __lasx_xvsubi_bu(a: __v32i8, b: u32) -> __v32i8; #[link_name = "llvm.loongarch.lasx.xvsubi.hu"] @@ -171,150 +75,6 @@ unsafe extern "unadjusted" { fn __lasx_xvsubi_wu(a: __v8i32, b: u32) -> __v8i32; #[link_name = "llvm.loongarch.lasx.xvsubi.du"] fn __lasx_xvsubi_du(a: __v4i64, b: u32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvmax.b"] - fn __lasx_xvmax_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvmax.h"] - fn __lasx_xvmax_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvmax.w"] - fn __lasx_xvmax_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvmax.d"] - fn __lasx_xvmax_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvmaxi.b"] - fn __lasx_xvmaxi_b(a: __v32i8, b: i32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvmaxi.h"] - fn __lasx_xvmaxi_h(a: __v16i16, b: i32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvmaxi.w"] - fn __lasx_xvmaxi_w(a: __v8i32, b: i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvmaxi.d"] - fn __lasx_xvmaxi_d(a: __v4i64, b: i32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvmax.bu"] - fn __lasx_xvmax_bu(a: __v32u8, b: __v32u8) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvmax.hu"] - fn __lasx_xvmax_hu(a: __v16u16, b: __v16u16) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvmax.wu"] - fn __lasx_xvmax_wu(a: __v8u32, b: __v8u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvmax.du"] - fn __lasx_xvmax_du(a: __v4u64, b: __v4u64) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvmaxi.bu"] - fn __lasx_xvmaxi_bu(a: __v32u8, b: u32) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvmaxi.hu"] - fn __lasx_xvmaxi_hu(a: __v16u16, b: u32) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvmaxi.wu"] - fn __lasx_xvmaxi_wu(a: __v8u32, b: u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvmaxi.du"] - fn __lasx_xvmaxi_du(a: __v4u64, b: u32) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvmin.b"] - fn __lasx_xvmin_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvmin.h"] - fn __lasx_xvmin_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvmin.w"] - fn __lasx_xvmin_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvmin.d"] - fn __lasx_xvmin_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvmini.b"] - fn __lasx_xvmini_b(a: __v32i8, b: i32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvmini.h"] - fn __lasx_xvmini_h(a: __v16i16, b: i32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvmini.w"] - fn __lasx_xvmini_w(a: __v8i32, b: i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvmini.d"] - fn __lasx_xvmini_d(a: __v4i64, b: i32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvmin.bu"] - fn __lasx_xvmin_bu(a: __v32u8, b: __v32u8) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvmin.hu"] - fn __lasx_xvmin_hu(a: __v16u16, b: __v16u16) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvmin.wu"] - fn __lasx_xvmin_wu(a: __v8u32, b: __v8u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvmin.du"] - fn __lasx_xvmin_du(a: __v4u64, b: __v4u64) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvmini.bu"] - fn __lasx_xvmini_bu(a: __v32u8, b: u32) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvmini.hu"] - fn __lasx_xvmini_hu(a: __v16u16, b: u32) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvmini.wu"] - fn __lasx_xvmini_wu(a: __v8u32, b: u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvmini.du"] - fn __lasx_xvmini_du(a: __v4u64, b: u32) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvseq.b"] - fn __lasx_xvseq_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvseq.h"] - fn __lasx_xvseq_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvseq.w"] - fn __lasx_xvseq_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvseq.d"] - fn __lasx_xvseq_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvseqi.b"] - fn __lasx_xvseqi_b(a: __v32i8, b: i32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvseqi.h"] - fn __lasx_xvseqi_h(a: __v16i16, b: i32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvseqi.w"] - fn __lasx_xvseqi_w(a: __v8i32, b: i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvseqi.d"] - fn __lasx_xvseqi_d(a: __v4i64, b: i32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvslt.b"] - fn __lasx_xvslt_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvslt.h"] - fn __lasx_xvslt_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvslt.w"] - fn __lasx_xvslt_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvslt.d"] - fn __lasx_xvslt_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvslti.b"] - fn __lasx_xvslti_b(a: __v32i8, b: i32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvslti.h"] - fn __lasx_xvslti_h(a: __v16i16, b: i32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvslti.w"] - fn __lasx_xvslti_w(a: __v8i32, b: i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvslti.d"] - fn __lasx_xvslti_d(a: __v4i64, b: i32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvslt.bu"] - fn __lasx_xvslt_bu(a: __v32u8, b: __v32u8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvslt.hu"] - fn __lasx_xvslt_hu(a: __v16u16, b: __v16u16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvslt.wu"] - fn __lasx_xvslt_wu(a: __v8u32, b: __v8u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvslt.du"] - fn __lasx_xvslt_du(a: __v4u64, b: __v4u64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvslti.bu"] - fn __lasx_xvslti_bu(a: __v32u8, b: u32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvslti.hu"] - fn __lasx_xvslti_hu(a: __v16u16, b: u32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvslti.wu"] - fn __lasx_xvslti_wu(a: __v8u32, b: u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvslti.du"] - fn __lasx_xvslti_du(a: __v4u64, b: u32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvsle.b"] - fn __lasx_xvsle_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvsle.h"] - fn __lasx_xvsle_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvsle.w"] - fn __lasx_xvsle_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvsle.d"] - fn __lasx_xvsle_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvslei.b"] - fn __lasx_xvslei_b(a: __v32i8, b: i32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvslei.h"] - fn __lasx_xvslei_h(a: __v16i16, b: i32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvslei.w"] - fn __lasx_xvslei_w(a: __v8i32, b: i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvslei.d"] - fn __lasx_xvslei_d(a: __v4i64, b: i32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvsle.bu"] - fn __lasx_xvsle_bu(a: __v32u8, b: __v32u8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvsle.hu"] - fn __lasx_xvsle_hu(a: __v16u16, b: __v16u16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvsle.wu"] - fn __lasx_xvsle_wu(a: __v8u32, b: __v8u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvsle.du"] - fn __lasx_xvsle_du(a: __v4u64, b: __v4u64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvslei.bu"] - fn __lasx_xvslei_bu(a: __v32u8, b: u32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvslei.hu"] - fn __lasx_xvslei_hu(a: __v16u16, b: u32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvslei.wu"] - fn __lasx_xvslei_wu(a: __v8u32, b: u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvslei.du"] - fn __lasx_xvslei_du(a: __v4u64, b: u32) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvsat.b"] fn __lasx_xvsat_b(a: __v32i8, b: u32) -> __v32i8; #[link_name = "llvm.loongarch.lasx.xvsat.h"] @@ -331,30 +91,6 @@ unsafe extern "unadjusted" { fn __lasx_xvsat_wu(a: __v8u32, b: u32) -> __v8u32; #[link_name = "llvm.loongarch.lasx.xvsat.du"] fn __lasx_xvsat_du(a: __v4u64, b: u32) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvadda.b"] - fn __lasx_xvadda_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvadda.h"] - fn __lasx_xvadda_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvadda.w"] - fn __lasx_xvadda_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvadda.d"] - fn __lasx_xvadda_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvsadd.b"] - fn __lasx_xvsadd_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvsadd.h"] - fn __lasx_xvsadd_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvsadd.w"] - fn __lasx_xvsadd_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvsadd.d"] - fn __lasx_xvsadd_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvsadd.bu"] - fn __lasx_xvsadd_bu(a: __v32u8, b: __v32u8) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvsadd.hu"] - fn __lasx_xvsadd_hu(a: __v16u16, b: __v16u16) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvsadd.wu"] - fn __lasx_xvsadd_wu(a: __v8u32, b: __v8u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvsadd.du"] - fn __lasx_xvsadd_du(a: __v4u64, b: __v4u64) -> __v4u64; #[link_name = "llvm.loongarch.lasx.xvavg.b"] fn __lasx_xvavg_b(a: __v32i8, b: __v32i8) -> __v32i8; #[link_name = "llvm.loongarch.lasx.xvavg.h"] @@ -387,78 +123,6 @@ unsafe extern "unadjusted" { fn __lasx_xvavgr_wu(a: __v8u32, b: __v8u32) -> __v8u32; #[link_name = "llvm.loongarch.lasx.xvavgr.du"] fn __lasx_xvavgr_du(a: __v4u64, b: __v4u64) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvssub.b"] - fn __lasx_xvssub_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvssub.h"] - fn __lasx_xvssub_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvssub.w"] - fn __lasx_xvssub_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvssub.d"] - fn __lasx_xvssub_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvssub.bu"] - fn __lasx_xvssub_bu(a: __v32u8, b: __v32u8) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvssub.hu"] - fn __lasx_xvssub_hu(a: __v16u16, b: __v16u16) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvssub.wu"] - fn __lasx_xvssub_wu(a: __v8u32, b: __v8u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvssub.du"] - fn __lasx_xvssub_du(a: __v4u64, b: __v4u64) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvabsd.b"] - fn __lasx_xvabsd_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvabsd.h"] - fn __lasx_xvabsd_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvabsd.w"] - fn __lasx_xvabsd_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvabsd.d"] - fn __lasx_xvabsd_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvabsd.bu"] - fn __lasx_xvabsd_bu(a: __v32u8, b: __v32u8) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvabsd.hu"] - fn __lasx_xvabsd_hu(a: __v16u16, b: __v16u16) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvabsd.wu"] - fn __lasx_xvabsd_wu(a: __v8u32, b: __v8u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvabsd.du"] - fn __lasx_xvabsd_du(a: __v4u64, b: __v4u64) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvmul.b"] - fn __lasx_xvmul_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvmul.h"] - fn __lasx_xvmul_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvmul.w"] - fn __lasx_xvmul_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvmul.d"] - fn __lasx_xvmul_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvmadd.b"] - fn __lasx_xvmadd_b(a: __v32i8, b: __v32i8, c: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvmadd.h"] - fn __lasx_xvmadd_h(a: __v16i16, b: __v16i16, c: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvmadd.w"] - fn __lasx_xvmadd_w(a: __v8i32, b: __v8i32, c: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvmadd.d"] - fn __lasx_xvmadd_d(a: __v4i64, b: __v4i64, c: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvmsub.b"] - fn __lasx_xvmsub_b(a: __v32i8, b: __v32i8, c: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvmsub.h"] - fn __lasx_xvmsub_h(a: __v16i16, b: __v16i16, c: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvmsub.w"] - fn __lasx_xvmsub_w(a: __v8i32, b: __v8i32, c: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvmsub.d"] - fn __lasx_xvmsub_d(a: __v4i64, b: __v4i64, c: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvdiv.b"] - fn __lasx_xvdiv_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvdiv.h"] - fn __lasx_xvdiv_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvdiv.w"] - fn __lasx_xvdiv_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvdiv.d"] - fn __lasx_xvdiv_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvdiv.bu"] - fn __lasx_xvdiv_bu(a: __v32u8, b: __v32u8) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvdiv.hu"] - fn __lasx_xvdiv_hu(a: __v16u16, b: __v16u16) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvdiv.wu"] - fn __lasx_xvdiv_wu(a: __v8u32, b: __v8u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvdiv.du"] - fn __lasx_xvdiv_du(a: __v4u64, b: __v4u64) -> __v4u64; #[link_name = "llvm.loongarch.lasx.xvhaddw.h.b"] fn __lasx_xvhaddw_h_b(a: __v32i8, b: __v32i8) -> __v16i16; #[link_name = "llvm.loongarch.lasx.xvhaddw.w.h"] @@ -483,78 +147,6 @@ unsafe extern "unadjusted" { fn __lasx_xvhsubw_wu_hu(a: __v16u16, b: __v16u16) -> __v8i32; #[link_name = "llvm.loongarch.lasx.xvhsubw.du.wu"] fn __lasx_xvhsubw_du_wu(a: __v8u32, b: __v8u32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvmod.b"] - fn __lasx_xvmod_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvmod.h"] - fn __lasx_xvmod_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvmod.w"] - fn __lasx_xvmod_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvmod.d"] - fn __lasx_xvmod_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvmod.bu"] - fn __lasx_xvmod_bu(a: __v32u8, b: __v32u8) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvmod.hu"] - fn __lasx_xvmod_hu(a: __v16u16, b: __v16u16) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvmod.wu"] - fn __lasx_xvmod_wu(a: __v8u32, b: __v8u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvmod.du"] - fn __lasx_xvmod_du(a: __v4u64, b: __v4u64) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvrepl128vei.b"] - fn __lasx_xvrepl128vei_b(a: __v32i8, b: u32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvrepl128vei.h"] - fn __lasx_xvrepl128vei_h(a: __v16i16, b: u32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvrepl128vei.w"] - fn __lasx_xvrepl128vei_w(a: __v8i32, b: u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvrepl128vei.d"] - fn __lasx_xvrepl128vei_d(a: __v4i64, b: u32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvpickev.b"] - fn __lasx_xvpickev_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvpickev.h"] - fn __lasx_xvpickev_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvpickev.w"] - fn __lasx_xvpickev_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvpickev.d"] - fn __lasx_xvpickev_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvpickod.b"] - fn __lasx_xvpickod_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvpickod.h"] - fn __lasx_xvpickod_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvpickod.w"] - fn __lasx_xvpickod_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvpickod.d"] - fn __lasx_xvpickod_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvilvh.b"] - fn __lasx_xvilvh_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvilvh.h"] - fn __lasx_xvilvh_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvilvh.w"] - fn __lasx_xvilvh_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvilvh.d"] - fn __lasx_xvilvh_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvilvl.b"] - fn __lasx_xvilvl_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvilvl.h"] - fn __lasx_xvilvl_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvilvl.w"] - fn __lasx_xvilvl_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvilvl.d"] - fn __lasx_xvilvl_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvpackev.b"] - fn __lasx_xvpackev_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvpackev.h"] - fn __lasx_xvpackev_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvpackev.w"] - fn __lasx_xvpackev_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvpackev.d"] - fn __lasx_xvpackev_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvpackod.b"] - fn __lasx_xvpackod_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvpackod.h"] - fn __lasx_xvpackod_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvpackod.w"] - fn __lasx_xvpackod_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvpackod.d"] - fn __lasx_xvpackod_d(a: __v4i64, b: __v4i64) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvshuf.b"] fn __lasx_xvshuf_b(a: __v32i8, b: __v32i8, c: __v32i8) -> __v32i8; #[link_name = "llvm.loongarch.lasx.xvshuf.h"] @@ -563,48 +155,18 @@ unsafe extern "unadjusted" { fn __lasx_xvshuf_w(a: __v8i32, b: __v8i32, c: __v8i32) -> __v8i32; #[link_name = "llvm.loongarch.lasx.xvshuf.d"] fn __lasx_xvshuf_d(a: __v4i64, b: __v4i64, c: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvand.v"] - fn __lasx_xvand_v(a: __v32u8, b: __v32u8) -> __v32u8; #[link_name = "llvm.loongarch.lasx.xvandi.b"] fn __lasx_xvandi_b(a: __v32u8, b: u32) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvor.v"] - fn __lasx_xvor_v(a: __v32u8, b: __v32u8) -> __v32u8; #[link_name = "llvm.loongarch.lasx.xvori.b"] fn __lasx_xvori_b(a: __v32u8, b: u32) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvnor.v"] - fn __lasx_xvnor_v(a: __v32u8, b: __v32u8) -> __v32u8; #[link_name = "llvm.loongarch.lasx.xvnori.b"] fn __lasx_xvnori_b(a: __v32u8, b: u32) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvxor.v"] - fn __lasx_xvxor_v(a: __v32u8, b: __v32u8) -> __v32u8; #[link_name = "llvm.loongarch.lasx.xvxori.b"] fn __lasx_xvxori_b(a: __v32u8, b: u32) -> __v32u8; #[link_name = "llvm.loongarch.lasx.xvbitsel.v"] fn __lasx_xvbitsel_v(a: __v32u8, b: __v32u8, c: __v32u8) -> __v32u8; #[link_name = "llvm.loongarch.lasx.xvbitseli.b"] fn __lasx_xvbitseli_b(a: __v32u8, b: __v32u8, c: u32) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvshuf4i.b"] - fn __lasx_xvshuf4i_b(a: __v32i8, b: u32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvshuf4i.h"] - fn __lasx_xvshuf4i_h(a: __v16i16, b: u32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvshuf4i.w"] - fn __lasx_xvshuf4i_w(a: __v8i32, b: u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvreplgr2vr.b"] - fn __lasx_xvreplgr2vr_b(a: i32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvreplgr2vr.h"] - fn __lasx_xvreplgr2vr_h(a: i32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvreplgr2vr.w"] - fn __lasx_xvreplgr2vr_w(a: i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvreplgr2vr.d"] - fn __lasx_xvreplgr2vr_d(a: i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvpcnt.b"] - fn __lasx_xvpcnt_b(a: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvpcnt.h"] - fn __lasx_xvpcnt_h(a: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvpcnt.w"] - fn __lasx_xvpcnt_w(a: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvpcnt.d"] - fn __lasx_xvpcnt_d(a: __v4i64) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvclo.b"] fn __lasx_xvclo_b(a: __v32i8) -> __v32i8; #[link_name = "llvm.loongarch.lasx.xvclo.h"] @@ -613,30 +175,6 @@ unsafe extern "unadjusted" { fn __lasx_xvclo_w(a: __v8i32) -> __v8i32; #[link_name = "llvm.loongarch.lasx.xvclo.d"] fn __lasx_xvclo_d(a: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvclz.b"] - fn __lasx_xvclz_b(a: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvclz.h"] - fn __lasx_xvclz_h(a: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvclz.w"] - fn __lasx_xvclz_w(a: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvclz.d"] - fn __lasx_xvclz_d(a: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvfadd.s"] - fn __lasx_xvfadd_s(a: __v8f32, b: __v8f32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvfadd.d"] - fn __lasx_xvfadd_d(a: __v4f64, b: __v4f64) -> __v4f64; - #[link_name = "llvm.loongarch.lasx.xvfsub.s"] - fn __lasx_xvfsub_s(a: __v8f32, b: __v8f32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvfsub.d"] - fn __lasx_xvfsub_d(a: __v4f64, b: __v4f64) -> __v4f64; - #[link_name = "llvm.loongarch.lasx.xvfmul.s"] - fn __lasx_xvfmul_s(a: __v8f32, b: __v8f32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvfmul.d"] - fn __lasx_xvfmul_d(a: __v4f64, b: __v4f64) -> __v4f64; - #[link_name = "llvm.loongarch.lasx.xvfdiv.s"] - fn __lasx_xvfdiv_s(a: __v8f32, b: __v8f32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvfdiv.d"] - fn __lasx_xvfdiv_d(a: __v4f64, b: __v4f64) -> __v4f64; #[link_name = "llvm.loongarch.lasx.xvfcvt.h.s"] fn __lasx_xvfcvt_h_s(a: __v8f32, b: __v8f32) -> __v16i16; #[link_name = "llvm.loongarch.lasx.xvfcvt.s.d"] @@ -661,14 +199,6 @@ unsafe extern "unadjusted" { fn __lasx_xvfclass_s(a: __v8f32) -> __v8i32; #[link_name = "llvm.loongarch.lasx.xvfclass.d"] fn __lasx_xvfclass_d(a: __v4f64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvfsqrt.s"] - fn __lasx_xvfsqrt_s(a: __v8f32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvfsqrt.d"] - fn __lasx_xvfsqrt_d(a: __v4f64) -> __v4f64; - #[link_name = "llvm.loongarch.lasx.xvfrecip.s"] - fn __lasx_xvfrecip_s(a: __v8f32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvfrecip.d"] - fn __lasx_xvfrecip_d(a: __v4f64) -> __v4f64; #[link_name = "llvm.loongarch.lasx.xvfrecipe.s"] fn __lasx_xvfrecipe_s(a: __v8f32) -> __v8f32; #[link_name = "llvm.loongarch.lasx.xvfrecipe.d"] @@ -681,10 +211,6 @@ unsafe extern "unadjusted" { fn __lasx_xvfrint_s(a: __v8f32) -> __v8f32; #[link_name = "llvm.loongarch.lasx.xvfrint.d"] fn __lasx_xvfrint_d(a: __v4f64) -> __v4f64; - #[link_name = "llvm.loongarch.lasx.xvfrsqrt.s"] - fn __lasx_xvfrsqrt_s(a: __v8f32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvfrsqrt.d"] - fn __lasx_xvfrsqrt_d(a: __v4f64) -> __v4f64; #[link_name = "llvm.loongarch.lasx.xvflogb.s"] fn __lasx_xvflogb_s(a: __v8f32) -> __v8f32; #[link_name = "llvm.loongarch.lasx.xvflogb.d"] @@ -731,32 +257,6 @@ unsafe extern "unadjusted" { fn __lasx_xvreplve_d(a: __v4i64, b: i32) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvpermi.w"] fn __lasx_xvpermi_w(a: __v8i32, b: __v8i32, c: u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvandn.v"] - fn __lasx_xvandn_v(a: __v32u8, b: __v32u8) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvneg.b"] - fn __lasx_xvneg_b(a: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvneg.h"] - fn __lasx_xvneg_h(a: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvneg.w"] - fn __lasx_xvneg_w(a: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvneg.d"] - fn __lasx_xvneg_d(a: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvmuh.b"] - fn __lasx_xvmuh_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvmuh.h"] - fn __lasx_xvmuh_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvmuh.w"] - fn __lasx_xvmuh_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvmuh.d"] - fn __lasx_xvmuh_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvmuh.bu"] - fn __lasx_xvmuh_bu(a: __v32u8, b: __v32u8) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvmuh.hu"] - fn __lasx_xvmuh_hu(a: __v16u16, b: __v16u16) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvmuh.wu"] - fn __lasx_xvmuh_wu(a: __v8u32, b: __v8u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvmuh.du"] - fn __lasx_xvmuh_du(a: __v4u64, b: __v4u64) -> __v4u64; #[link_name = "llvm.loongarch.lasx.xvsllwil.h.b"] fn __lasx_xvsllwil_h_b(a: __v32i8, b: u32) -> __v16i16; #[link_name = "llvm.loongarch.lasx.xvsllwil.w.h"] @@ -839,10 +339,6 @@ unsafe extern "unadjusted" { fn __lasx_xvfrstp_h(a: __v16i16, b: __v16i16, c: __v16i16) -> __v16i16; #[link_name = "llvm.loongarch.lasx.xvshuf4i.d"] fn __lasx_xvshuf4i_d(a: __v4i64, b: __v4i64, c: u32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvbsrl.v"] - fn __lasx_xvbsrl_v(a: __v32i8, b: u32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvbsll.v"] - fn __lasx_xvbsll_v(a: __v32i8, b: u32) -> __v32i8; #[link_name = "llvm.loongarch.lasx.xvextrins.b"] fn __lasx_xvextrins_b(a: __v32i8, b: __v32i8, c: u32) -> __v32i8; #[link_name = "llvm.loongarch.lasx.xvextrins.h"] @@ -867,22 +363,6 @@ unsafe extern "unadjusted" { fn __lasx_xvsigncov_w(a: __v8i32, b: __v8i32) -> __v8i32; #[link_name = "llvm.loongarch.lasx.xvsigncov.d"] fn __lasx_xvsigncov_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvfmadd.s"] - fn __lasx_xvfmadd_s(a: __v8f32, b: __v8f32, c: __v8f32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvfmadd.d"] - fn __lasx_xvfmadd_d(a: __v4f64, b: __v4f64, c: __v4f64) -> __v4f64; - #[link_name = "llvm.loongarch.lasx.xvfmsub.s"] - fn __lasx_xvfmsub_s(a: __v8f32, b: __v8f32, c: __v8f32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvfmsub.d"] - fn __lasx_xvfmsub_d(a: __v4f64, b: __v4f64, c: __v4f64) -> __v4f64; - #[link_name = "llvm.loongarch.lasx.xvfnmadd.s"] - fn __lasx_xvfnmadd_s(a: __v8f32, b: __v8f32, c: __v8f32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvfnmadd.d"] - fn __lasx_xvfnmadd_d(a: __v4f64, b: __v4f64, c: __v4f64) -> __v4f64; - #[link_name = "llvm.loongarch.lasx.xvfnmsub.s"] - fn __lasx_xvfnmsub_s(a: __v8f32, b: __v8f32, c: __v8f32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvfnmsub.d"] - fn __lasx_xvfnmsub_d(a: __v4f64, b: __v4f64, c: __v4f64) -> __v4f64; #[link_name = "llvm.loongarch.lasx.xvftintrne.w.s"] fn __lasx_xvftintrne_w_s(a: __v8f32) -> __v8i32; #[link_name = "llvm.loongarch.lasx.xvftintrne.l.d"] @@ -935,22 +415,6 @@ unsafe extern "unadjusted" { fn __lasx_xvfrintrne_s(a: __v8f32) -> __v8f32; #[link_name = "llvm.loongarch.lasx.xvfrintrne.d"] fn __lasx_xvfrintrne_d(a: __v4f64) -> __v4f64; - #[link_name = "llvm.loongarch.lasx.xvfrintrz.s"] - fn __lasx_xvfrintrz_s(a: __v8f32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvfrintrz.d"] - fn __lasx_xvfrintrz_d(a: __v4f64) -> __v4f64; - #[link_name = "llvm.loongarch.lasx.xvfrintrp.s"] - fn __lasx_xvfrintrp_s(a: __v8f32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvfrintrp.d"] - fn __lasx_xvfrintrp_d(a: __v4f64) -> __v4f64; - #[link_name = "llvm.loongarch.lasx.xvfrintrm.s"] - fn __lasx_xvfrintrm_s(a: __v8f32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvfrintrm.d"] - fn __lasx_xvfrintrm_d(a: __v4f64) -> __v4f64; - #[link_name = "llvm.loongarch.lasx.xvld"] - fn __lasx_xvld(a: *const i8, b: i32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvst"] - fn __lasx_xvst(a: __v32i8, b: *mut i8, c: i32); #[link_name = "llvm.loongarch.lasx.xvstelm.b"] fn __lasx_xvstelm_b(a: __v32i8, b: *mut i8, c: i32, d: u32); #[link_name = "llvm.loongarch.lasx.xvstelm.h"] @@ -979,30 +443,8 @@ unsafe extern "unadjusted" { fn __lasx_xvssrln_h_w(a: __v8i32, b: __v8i32) -> __v16i16; #[link_name = "llvm.loongarch.lasx.xvssrln.w.d"] fn __lasx_xvssrln_w_d(a: __v4i64, b: __v4i64) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvorn.v"] - fn __lasx_xvorn_v(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvldi"] - fn __lasx_xvldi(a: i32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvldx"] - fn __lasx_xvldx(a: *const i8, b: i64) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvstx"] - fn __lasx_xvstx(a: __v32i8, b: *mut i8, c: i64); #[link_name = "llvm.loongarch.lasx.xvextl.qu.du"] fn __lasx_xvextl_qu_du(a: __v4u64) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvinsgr2vr.w"] - fn __lasx_xvinsgr2vr_w(a: __v8i32, b: i32, c: u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvinsgr2vr.d"] - fn __lasx_xvinsgr2vr_d(a: __v4i64, b: i64, c: u32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvreplve0.b"] - fn __lasx_xvreplve0_b(a: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvreplve0.h"] - fn __lasx_xvreplve0_h(a: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvreplve0.w"] - fn __lasx_xvreplve0_w(a: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvreplve0.d"] - fn __lasx_xvreplve0_d(a: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvreplve0.q"] - fn __lasx_xvreplve0_q(a: __v32i8) -> __v32i8; #[link_name = "llvm.loongarch.lasx.vext2xv.h.b"] fn __lasx_vext2xv_h_b(a: __v32i8) -> __v16i16; #[link_name = "llvm.loongarch.lasx.vext2xv.w.h"] @@ -1041,14 +483,6 @@ unsafe extern "unadjusted" { fn __lasx_xvldrepl_w(a: *const i8, b: i32) -> __v8i32; #[link_name = "llvm.loongarch.lasx.xvldrepl.d"] fn __lasx_xvldrepl_d(a: *const i8, b: i32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvpickve2gr.w"] - fn __lasx_xvpickve2gr_w(a: __v8i32, b: u32) -> i32; - #[link_name = "llvm.loongarch.lasx.xvpickve2gr.wu"] - fn __lasx_xvpickve2gr_wu(a: __v8i32, b: u32) -> u32; - #[link_name = "llvm.loongarch.lasx.xvpickve2gr.d"] - fn __lasx_xvpickve2gr_d(a: __v4i64, b: u32) -> i64; - #[link_name = "llvm.loongarch.lasx.xvpickve2gr.du"] - fn __lasx_xvpickve2gr_du(a: __v4i64, b: u32) -> u64; #[link_name = "llvm.loongarch.lasx.xvaddwev.q.d"] fn __lasx_xvaddwev_q_d(a: __v4i64, b: __v4i64) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvaddwev.d.w"] @@ -1225,14 +659,6 @@ unsafe extern "unadjusted" { fn __lasx_xvmaddwod_w_hu_h(a: __v8i32, b: __v16u16, c: __v16i16) -> __v8i32; #[link_name = "llvm.loongarch.lasx.xvmaddwod.h.bu.b"] fn __lasx_xvmaddwod_h_bu_b(a: __v16i16, b: __v32u8, c: __v32i8) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvrotr.b"] - fn __lasx_xvrotr_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvrotr.h"] - fn __lasx_xvrotr_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvrotr.w"] - fn __lasx_xvrotr_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvrotr.d"] - fn __lasx_xvrotr_d(a: __v4i64, b: __v4i64) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvadd.q"] fn __lasx_xvadd_q(a: __v4i64, b: __v4i64) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvsub.q"] @@ -1265,14 +691,6 @@ unsafe extern "unadjusted" { fn __lasx_xvexth_du_wu(a: __v8u32) -> __v4u64; #[link_name = "llvm.loongarch.lasx.xvexth.qu.du"] fn __lasx_xvexth_qu_du(a: __v4u64) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvrotri.b"] - fn __lasx_xvrotri_b(a: __v32i8, b: u32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvrotri.h"] - fn __lasx_xvrotri_h(a: __v16i16, b: u32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvrotri.w"] - fn __lasx_xvrotri_w(a: __v8i32, b: u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvrotri.d"] - fn __lasx_xvrotri_d(a: __v4i64, b: u32) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvextl.q.d"] fn __lasx_xvextl_q_d(a: __v4i64) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvsrlni.b.h"] @@ -1483,142 +901,42 @@ unsafe extern "unadjusted" { fn __lasx_xvpickve_d_f(a: __v4f64, b: u32) -> __v4f64; #[link_name = "llvm.loongarch.lasx.xvpickve.w.f"] fn __lasx_xvpickve_w_f(a: __v8f32, b: u32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvrepli.b"] - fn __lasx_xvrepli_b(a: i32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvrepli.d"] - fn __lasx_xvrepli_d(a: i32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvrepli.h"] - fn __lasx_xvrepli_h(a: i32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvrepli.w"] - fn __lasx_xvrepli_w(a: i32) -> __v8i32; -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsll_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsll_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsll_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsll_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsll_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsll_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsll_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsll_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslli_b(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvslli_b(transmute(a), IMM3)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslli_h(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lasx_xvslli_h(transmute(a), IMM4)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslli_w(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvslli_w(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslli_d(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lasx_xvslli_d(transmute(a), IMM6)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsra_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsra_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsra_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsra_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsra_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsra_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsra_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsra_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrai_b(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvsrai_b(transmute(a), IMM3)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrai_h(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lasx_xvsrai_h(transmute(a), IMM4)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrai_w(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvsrai_w(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrai_d(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lasx_xvsrai_d(transmute(a), IMM6)) } + #[link_name = "llvm.loongarch.lasx.cast.128.s"] + fn __lasx_cast_128_s(a: __v4f32) -> __v8f32; + #[link_name = "llvm.loongarch.lasx.cast.128.d"] + fn __lasx_cast_128_d(a: __v2f64) -> __v4f64; + #[link_name = "llvm.loongarch.lasx.cast.128"] + fn __lasx_cast_128(a: __v2i64) -> __v4i64; + #[link_name = "llvm.loongarch.lasx.concat.128.s"] + fn __lasx_concat_128_s(a: __v4f32, b: __v4f32) -> __v8f32; + #[link_name = "llvm.loongarch.lasx.concat.128.d"] + fn __lasx_concat_128_d(a: __v2f64, b: __v2f64) -> __v4f64; + #[link_name = "llvm.loongarch.lasx.concat.128"] + fn __lasx_concat_128(a: __v2i64, b: __v2i64) -> __v4i64; + #[link_name = "llvm.loongarch.lasx.extract.128.lo.s"] + fn __lasx_extract_128_lo_s(a: __v8f32) -> __v4f32; + #[link_name = "llvm.loongarch.lasx.extract.128.hi.s"] + fn __lasx_extract_128_hi_s(a: __v8f32) -> __v4f32; + #[link_name = "llvm.loongarch.lasx.extract.128.lo.d"] + fn __lasx_extract_128_lo_d(a: __v4f64) -> __v2f64; + #[link_name = "llvm.loongarch.lasx.extract.128.hi.d"] + fn __lasx_extract_128_hi_d(a: __v4f64) -> __v2f64; + #[link_name = "llvm.loongarch.lasx.extract.128.lo"] + fn __lasx_extract_128_lo(a: __v4i64) -> __v2i64; + #[link_name = "llvm.loongarch.lasx.extract.128.hi"] + fn __lasx_extract_128_hi(a: __v4i64) -> __v2i64; + #[link_name = "llvm.loongarch.lasx.insert.128.lo.s"] + fn __lasx_insert_128_lo_s(a: __v8f32, b: __v4f32) -> __v8f32; + #[link_name = "llvm.loongarch.lasx.insert.128.hi.s"] + fn __lasx_insert_128_hi_s(a: __v8f32, b: __v4f32) -> __v8f32; + #[link_name = "llvm.loongarch.lasx.insert.128.lo.d"] + fn __lasx_insert_128_lo_d(a: __v4f64, b: __v2f64) -> __v4f64; + #[link_name = "llvm.loongarch.lasx.insert.128.hi.d"] + fn __lasx_insert_128_hi_d(a: __v4f64, b: __v2f64) -> __v4f64; + #[link_name = "llvm.loongarch.lasx.insert.128.lo"] + fn __lasx_insert_128_lo(a: __v4i64, b: __v2i64) -> __v4i64; + #[link_name = "llvm.loongarch.lasx.insert.128.hi"] + fn __lasx_insert_128_hi(a: __v4i64, b: __v2i64) -> __v4i64; } #[inline] @@ -1685,70 +1003,6 @@ pub fn lasx_xvsrari_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsrari_d(transmute(a), IMM6)) } } -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrl_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsrl_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrl_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsrl_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrl_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsrl_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrl_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsrl_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrli_b(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvsrli_b(transmute(a), IMM3)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrli_h(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lasx_xvsrli_h(transmute(a), IMM4)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrli_w(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvsrli_w(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrli_d(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lasx_xvsrli_d(transmute(a), IMM6)) } -} - #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1813,34 +1067,6 @@ pub fn lasx_xvsrlri_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsrlri_d(transmute(a), IMM6)) } } -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitclr_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitclr_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitclr_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitclr_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitclr_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitclr_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitclr_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitclr_d(transmute(a), transmute(b))) } -} - #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] @@ -1877,34 +1103,6 @@ pub fn lasx_xvbitclri_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvbitclri_d(transmute(a), IMM6)) } } -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitset_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitset_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitset_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitset_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitset_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitset_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitset_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitset_d(transmute(a), transmute(b))) } -} - #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] @@ -1941,34 +1139,6 @@ pub fn lasx_xvbitseti_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvbitseti_d(transmute(a), IMM6)) } } -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitrev_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitrev_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitrev_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitrev_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitrev_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitrev_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitrev_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitrev_d(transmute(a), transmute(b))) } -} - #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] @@ -2007,1873 +1177,414 @@ pub fn lasx_xvbitrevi_d(a: m256i) -> m256i { #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvadd_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvadd_b(transmute(a), transmute(b))) } +pub fn lasx_xvsubi_bu(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM5, 5); + unsafe { transmute(__lasx_xvsubi_bu(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvadd_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvadd_h(transmute(a), transmute(b))) } +pub fn lasx_xvsubi_hu(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM5, 5); + unsafe { transmute(__lasx_xvsubi_hu(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvadd_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvadd_w(transmute(a), transmute(b))) } +pub fn lasx_xvsubi_wu(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM5, 5); + unsafe { transmute(__lasx_xvsubi_wu(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvadd_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvadd_d(transmute(a), transmute(b))) } +pub fn lasx_xvsubi_du(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM5, 5); + unsafe { transmute(__lasx_xvsubi_du(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvaddi_bu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvaddi_bu(transmute(a), IMM5)) } +pub fn lasx_xvsat_b(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM3, 3); + unsafe { transmute(__lasx_xvsat_b(transmute(a), IMM3)) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvaddi_hu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvaddi_hu(transmute(a), IMM5)) } +pub fn lasx_xvsat_h(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM4, 4); + unsafe { transmute(__lasx_xvsat_h(transmute(a), IMM4)) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvaddi_wu(a: m256i) -> m256i { +pub fn lasx_xvsat_w(a: m256i) -> m256i { static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvaddi_wu(transmute(a), IMM5)) } + unsafe { transmute(__lasx_xvsat_w(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvaddi_du(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvaddi_du(transmute(a), IMM5)) } +pub fn lasx_xvsat_d(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM6, 6); + unsafe { transmute(__lasx_xvsat_d(transmute(a), IMM6)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsub_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsub_b(transmute(a), transmute(b))) } +pub fn lasx_xvsat_bu(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM3, 3); + unsafe { transmute(__lasx_xvsat_bu(transmute(a), IMM3)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsub_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsub_h(transmute(a), transmute(b))) } +pub fn lasx_xvsat_hu(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM4, 4); + unsafe { transmute(__lasx_xvsat_hu(transmute(a), IMM4)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsub_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsub_w(transmute(a), transmute(b))) } +pub fn lasx_xvsat_wu(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM5, 5); + unsafe { transmute(__lasx_xvsat_wu(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsub_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsub_d(transmute(a), transmute(b))) } +pub fn lasx_xvsat_du(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM6, 6); + unsafe { transmute(__lasx_xvsat_du(transmute(a), IMM6)) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsubi_bu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvsubi_bu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsubi_hu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvsubi_hu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsubi_wu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvsubi_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsubi_du(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvsubi_du(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmax_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmax_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmax_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmax_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmax_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmax_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmax_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmax_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmaxi_b(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvmaxi_b(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmaxi_h(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvmaxi_h(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmaxi_w(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvmaxi_w(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmaxi_d(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvmaxi_d(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmax_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmax_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmax_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmax_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmax_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmax_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmax_du(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmax_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmaxi_bu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvmaxi_bu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmaxi_hu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvmaxi_hu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmaxi_wu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvmaxi_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmaxi_du(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvmaxi_du(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmin_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmin_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmin_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmin_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmin_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmin_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmin_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmin_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmini_b(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvmini_b(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmini_h(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvmini_h(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmini_w(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvmini_w(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmini_d(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvmini_d(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmin_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmin_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmin_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmin_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmin_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmin_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmin_du(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmin_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmini_bu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvmini_bu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmini_hu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvmini_hu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmini_wu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvmini_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmini_du(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvmini_du(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvseq_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvseq_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvseq_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvseq_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvseq_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvseq_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvseq_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvseq_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvseqi_b(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvseqi_b(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvseqi_h(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvseqi_h(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvseqi_w(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvseqi_w(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvseqi_d(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvseqi_d(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslt_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvslt_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslt_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvslt_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslt_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvslt_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslt_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvslt_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslti_b(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvslti_b(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslti_h(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvslti_h(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslti_w(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvslti_w(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslti_d(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvslti_d(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslt_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvslt_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslt_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvslt_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslt_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvslt_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslt_du(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvslt_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslti_bu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvslti_bu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslti_hu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvslti_hu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslti_wu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvslti_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslti_du(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvslti_du(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsle_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsle_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsle_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsle_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsle_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsle_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsle_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsle_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslei_b(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvslei_b(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslei_h(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvslei_h(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslei_w(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvslei_w(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslei_d(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvslei_d(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsle_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsle_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsle_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsle_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsle_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsle_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsle_du(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsle_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslei_bu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvslei_bu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslei_hu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvslei_hu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslei_wu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvslei_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslei_du(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvslei_du(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsat_b(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvsat_b(transmute(a), IMM3)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsat_h(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lasx_xvsat_h(transmute(a), IMM4)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsat_w(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvsat_w(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsat_d(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lasx_xvsat_d(transmute(a), IMM6)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsat_bu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvsat_bu(transmute(a), IMM3)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsat_hu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lasx_xvsat_hu(transmute(a), IMM4)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsat_wu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvsat_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsat_du(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lasx_xvsat_du(transmute(a), IMM6)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvadda_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvadda_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvadda_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvadda_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvadda_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvadda_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvadda_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvadda_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsadd_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsadd_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsadd_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsadd_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsadd_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsadd_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsadd_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsadd_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsadd_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsadd_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsadd_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsadd_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsadd_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsadd_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsadd_du(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsadd_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavg_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavg_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavg_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavg_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavg_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavg_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavg_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavg_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavg_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavg_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavg_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavg_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavg_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavg_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavg_du(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavg_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavgr_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavgr_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavgr_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavgr_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavgr_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavgr_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavgr_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavgr_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavgr_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavgr_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavgr_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavgr_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavgr_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavgr_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavgr_du(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavgr_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvssub_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvssub_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvssub_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvssub_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvssub_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvssub_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvssub_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvssub_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvssub_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvssub_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvssub_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvssub_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvssub_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvssub_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvssub_du(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvssub_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvabsd_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvabsd_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvabsd_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvabsd_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvabsd_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvabsd_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvabsd_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvabsd_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvabsd_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvabsd_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvabsd_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvabsd_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvabsd_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvabsd_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvabsd_du(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvabsd_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmul_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmul_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmul_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmul_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmul_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmul_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmul_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmul_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmadd_b(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvmadd_b(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmadd_h(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvmadd_h(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmadd_w(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvmadd_w(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmadd_d(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvmadd_d(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmsub_b(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvmsub_b(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmsub_h(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvmsub_h(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmsub_w(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvmsub_w(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmsub_d(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvmsub_d(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvdiv_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvdiv_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvdiv_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvdiv_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvdiv_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvdiv_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvdiv_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvdiv_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvdiv_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvdiv_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvdiv_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvdiv_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvdiv_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvdiv_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvdiv_du(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvdiv_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhaddw_h_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhaddw_h_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhaddw_w_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhaddw_w_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhaddw_d_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhaddw_d_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhaddw_hu_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhaddw_hu_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhaddw_wu_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhaddw_wu_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhaddw_du_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhaddw_du_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhsubw_h_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhsubw_h_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhsubw_w_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhsubw_w_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhsubw_d_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhsubw_d_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhsubw_hu_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhsubw_hu_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhsubw_wu_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhsubw_wu_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhsubw_du_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhsubw_du_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmod_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmod_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmod_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmod_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmod_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmod_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmod_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmod_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmod_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmod_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmod_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmod_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmod_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmod_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmod_du(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmod_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrepl128vei_b(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lasx_xvrepl128vei_b(transmute(a), IMM4)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrepl128vei_h(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvrepl128vei_h(transmute(a), IMM3)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrepl128vei_w(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM2, 2); - unsafe { transmute(__lasx_xvrepl128vei_w(transmute(a), IMM2)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrepl128vei_d(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM1, 1); - unsafe { transmute(__lasx_xvrepl128vei_d(transmute(a), IMM1)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickev_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpickev_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickev_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpickev_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickev_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpickev_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickev_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpickev_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickod_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpickod_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickod_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpickod_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickod_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpickod_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickod_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpickod_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvilvh_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvilvh_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvilvh_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvilvh_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvilvh_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvilvh_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvilvh_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvilvh_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvilvl_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvilvl_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvilvl_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvilvl_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvilvl_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvilvl_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvilvl_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvilvl_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpackev_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpackev_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpackev_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpackev_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpackev_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpackev_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpackev_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpackev_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpackod_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpackod_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpackod_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpackod_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpackod_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpackod_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpackod_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpackod_d(transmute(a), transmute(b))) } +pub fn lasx_xvavg_b(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavg_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvshuf_b(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvshuf_b(transmute(a), transmute(b), transmute(c))) } +pub fn lasx_xvavg_h(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavg_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvshuf_h(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvshuf_h(transmute(a), transmute(b), transmute(c))) } +pub fn lasx_xvavg_w(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavg_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvshuf_w(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvshuf_w(transmute(a), transmute(b), transmute(c))) } +pub fn lasx_xvavg_d(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavg_d(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvshuf_d(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvshuf_d(transmute(a), transmute(b), transmute(c))) } +pub fn lasx_xvavg_bu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavg_bu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvand_v(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvand_v(transmute(a), transmute(b))) } +pub fn lasx_xvavg_hu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavg_hu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvandi_b(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lasx_xvandi_b(transmute(a), IMM8)) } +pub fn lasx_xvavg_wu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavg_wu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvor_v(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvor_v(transmute(a), transmute(b))) } +pub fn lasx_xvavg_du(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavg_du(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvori_b(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lasx_xvori_b(transmute(a), IMM8)) } +pub fn lasx_xvavgr_b(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavgr_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvnor_v(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvnor_v(transmute(a), transmute(b))) } +pub fn lasx_xvavgr_h(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavgr_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvnori_b(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lasx_xvnori_b(transmute(a), IMM8)) } +pub fn lasx_xvavgr_w(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavgr_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvxor_v(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvxor_v(transmute(a), transmute(b))) } +pub fn lasx_xvavgr_d(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavgr_d(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvxori_b(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lasx_xvxori_b(transmute(a), IMM8)) } +pub fn lasx_xvavgr_bu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavgr_bu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitsel_v(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitsel_v(transmute(a), transmute(b), transmute(c))) } +pub fn lasx_xvavgr_hu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavgr_hu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitseli_b(a: m256i, b: m256i) -> m256i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lasx_xvbitseli_b(transmute(a), transmute(b), IMM8)) } +pub fn lasx_xvavgr_wu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavgr_wu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvshuf4i_b(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lasx_xvshuf4i_b(transmute(a), IMM8)) } +pub fn lasx_xvavgr_du(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavgr_du(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvshuf4i_h(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lasx_xvshuf4i_h(transmute(a), IMM8)) } +pub fn lasx_xvhaddw_h_b(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhaddw_h_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvshuf4i_w(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lasx_xvshuf4i_w(transmute(a), IMM8)) } +pub fn lasx_xvhaddw_w_h(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhaddw_w_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvreplgr2vr_b(a: i32) -> m256i { - unsafe { transmute(__lasx_xvreplgr2vr_b(transmute(a))) } +pub fn lasx_xvhaddw_d_w(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhaddw_d_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvreplgr2vr_h(a: i32) -> m256i { - unsafe { transmute(__lasx_xvreplgr2vr_h(transmute(a))) } +pub fn lasx_xvhaddw_hu_bu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhaddw_hu_bu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvreplgr2vr_w(a: i32) -> m256i { - unsafe { transmute(__lasx_xvreplgr2vr_w(transmute(a))) } +pub fn lasx_xvhaddw_wu_hu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhaddw_wu_hu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvreplgr2vr_d(a: i64) -> m256i { - unsafe { transmute(__lasx_xvreplgr2vr_d(transmute(a))) } +pub fn lasx_xvhaddw_du_wu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhaddw_du_wu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpcnt_b(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvpcnt_b(transmute(a))) } +pub fn lasx_xvhsubw_h_b(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhsubw_h_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpcnt_h(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvpcnt_h(transmute(a))) } +pub fn lasx_xvhsubw_w_h(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhsubw_w_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpcnt_w(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvpcnt_w(transmute(a))) } +pub fn lasx_xvhsubw_d_w(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhsubw_d_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpcnt_d(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvpcnt_d(transmute(a))) } +pub fn lasx_xvhsubw_hu_bu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhsubw_hu_bu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvclo_b(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvclo_b(transmute(a))) } +pub fn lasx_xvhsubw_wu_hu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhsubw_wu_hu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvclo_h(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvclo_h(transmute(a))) } +pub fn lasx_xvhsubw_du_wu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhsubw_du_wu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvclo_w(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvclo_w(transmute(a))) } +pub fn lasx_xvshuf_b(a: m256i, b: m256i, c: m256i) -> m256i { + unsafe { transmute(__lasx_xvshuf_b(transmute(a), transmute(b), transmute(c))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvclo_d(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvclo_d(transmute(a))) } +pub fn lasx_xvshuf_h(a: m256i, b: m256i, c: m256i) -> m256i { + unsafe { transmute(__lasx_xvshuf_h(transmute(a), transmute(b), transmute(c))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvclz_b(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvclz_b(transmute(a))) } +pub fn lasx_xvshuf_w(a: m256i, b: m256i, c: m256i) -> m256i { + unsafe { transmute(__lasx_xvshuf_w(transmute(a), transmute(b), transmute(c))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvclz_h(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvclz_h(transmute(a))) } +pub fn lasx_xvshuf_d(a: m256i, b: m256i, c: m256i) -> m256i { + unsafe { transmute(__lasx_xvshuf_d(transmute(a), transmute(b), transmute(c))) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvclz_w(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvclz_w(transmute(a))) } +pub fn lasx_xvandi_b(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lasx_xvandi_b(transmute(a), IMM8)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvclz_d(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvclz_d(transmute(a))) } +pub fn lasx_xvori_b(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lasx_xvori_b(transmute(a), IMM8)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfadd_s(a: m256, b: m256) -> m256 { - unsafe { transmute(__lasx_xvfadd_s(transmute(a), transmute(b))) } +pub fn lasx_xvnori_b(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lasx_xvnori_b(transmute(a), IMM8)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfadd_d(a: m256d, b: m256d) -> m256d { - unsafe { transmute(__lasx_xvfadd_d(transmute(a), transmute(b))) } +pub fn lasx_xvxori_b(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lasx_xvxori_b(transmute(a), IMM8)) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfsub_s(a: m256, b: m256) -> m256 { - unsafe { transmute(__lasx_xvfsub_s(transmute(a), transmute(b))) } +pub fn lasx_xvbitsel_v(a: m256i, b: m256i, c: m256i) -> m256i { + unsafe { transmute(__lasx_xvbitsel_v(transmute(a), transmute(b), transmute(c))) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfsub_d(a: m256d, b: m256d) -> m256d { - unsafe { transmute(__lasx_xvfsub_d(transmute(a), transmute(b))) } +pub fn lasx_xvbitseli_b(a: m256i, b: m256i) -> m256i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lasx_xvbitseli_b(transmute(a), transmute(b), IMM8)) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfmul_s(a: m256, b: m256) -> m256 { - unsafe { transmute(__lasx_xvfmul_s(transmute(a), transmute(b))) } +pub fn lasx_xvclo_b(a: m256i) -> m256i { + unsafe { transmute(__lasx_xvclo_b(transmute(a))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfmul_d(a: m256d, b: m256d) -> m256d { - unsafe { transmute(__lasx_xvfmul_d(transmute(a), transmute(b))) } +pub fn lasx_xvclo_h(a: m256i) -> m256i { + unsafe { transmute(__lasx_xvclo_h(transmute(a))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfdiv_s(a: m256, b: m256) -> m256 { - unsafe { transmute(__lasx_xvfdiv_s(transmute(a), transmute(b))) } +pub fn lasx_xvclo_w(a: m256i) -> m256i { + unsafe { transmute(__lasx_xvclo_w(transmute(a))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfdiv_d(a: m256d, b: m256d) -> m256d { - unsafe { transmute(__lasx_xvfdiv_d(transmute(a), transmute(b))) } +pub fn lasx_xvclo_d(a: m256i) -> m256i { + unsafe { transmute(__lasx_xvclo_d(transmute(a))) } } #[inline] @@ -3960,34 +1671,6 @@ pub fn lasx_xvfclass_d(a: m256d) -> m256i { unsafe { transmute(__lasx_xvfclass_d(transmute(a))) } } -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfsqrt_s(a: m256) -> m256 { - unsafe { transmute(__lasx_xvfsqrt_s(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfsqrt_d(a: m256d) -> m256d { - unsafe { transmute(__lasx_xvfsqrt_d(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfrecip_s(a: m256) -> m256 { - unsafe { transmute(__lasx_xvfrecip_s(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfrecip_d(a: m256d) -> m256d { - unsafe { transmute(__lasx_xvfrecip_d(transmute(a))) } -} - #[inline] #[target_feature(enable = "lasx,frecipe")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4030,20 +1713,6 @@ pub fn lasx_xvfrint_d(a: m256d) -> m256d { unsafe { transmute(__lasx_xvfrint_d(transmute(a))) } } -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfrsqrt_s(a: m256) -> m256 { - unsafe { transmute(__lasx_xvfrsqrt_s(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfrsqrt_d(a: m256d) -> m256d { - unsafe { transmute(__lasx_xvfrsqrt_d(transmute(a))) } -} - #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4207,97 +1876,6 @@ pub fn lasx_xvpermi_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvpermi_w(transmute(a), transmute(b), IMM8)) } } -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvandn_v(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvandn_v(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvneg_b(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvneg_b(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvneg_h(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvneg_h(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvneg_w(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvneg_w(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvneg_d(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvneg_d(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmuh_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmuh_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmuh_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmuh_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmuh_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmuh_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmuh_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmuh_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmuh_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmuh_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmuh_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmuh_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmuh_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmuh_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmuh_du(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmuh_du(transmute(a), transmute(b))) } -} - #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] @@ -4603,24 +2181,6 @@ pub fn lasx_xvshuf4i_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvshuf4i_d(transmute(a), transmute(b), IMM8)) } } -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbsrl_v(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvbsrl_v(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbsll_v(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvbsll_v(transmute(a), IMM5)) } -} - #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] @@ -4703,70 +2263,14 @@ pub fn lasx_xvsigncov_h(a: m256i, b: m256i) -> m256i { #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsigncov_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsigncov_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsigncov_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsigncov_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfmadd_s(a: m256, b: m256, c: m256) -> m256 { - unsafe { transmute(__lasx_xvfmadd_s(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfmadd_d(a: m256d, b: m256d, c: m256d) -> m256d { - unsafe { transmute(__lasx_xvfmadd_d(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfmsub_s(a: m256, b: m256, c: m256) -> m256 { - unsafe { transmute(__lasx_xvfmsub_s(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfmsub_d(a: m256d, b: m256d, c: m256d) -> m256d { - unsafe { transmute(__lasx_xvfmsub_d(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfnmadd_s(a: m256, b: m256, c: m256) -> m256 { - unsafe { transmute(__lasx_xvfnmadd_s(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfnmadd_d(a: m256d, b: m256d, c: m256d) -> m256d { - unsafe { transmute(__lasx_xvfnmadd_d(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfnmsub_s(a: m256, b: m256, c: m256) -> m256 { - unsafe { transmute(__lasx_xvfnmsub_s(transmute(a), transmute(b), transmute(c))) } + unsafe { transmute(__lasx_xvsigncov_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfnmsub_d(a: m256d, b: m256d, c: m256d) -> m256d { - unsafe { transmute(__lasx_xvfnmsub_d(transmute(a), transmute(b), transmute(c))) } +pub fn lasx_xvsigncov_d(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvsigncov_d(transmute(a), transmute(b))) } } #[inline] @@ -4951,66 +2455,6 @@ pub fn lasx_xvfrintrne_d(a: m256d) -> m256d { unsafe { transmute(__lasx_xvfrintrne_d(transmute(a))) } } -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfrintrz_s(a: m256) -> m256 { - unsafe { transmute(__lasx_xvfrintrz_s(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfrintrz_d(a: m256d) -> m256d { - unsafe { transmute(__lasx_xvfrintrz_d(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfrintrp_s(a: m256) -> m256 { - unsafe { transmute(__lasx_xvfrintrp_s(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfrintrp_d(a: m256d) -> m256d { - unsafe { transmute(__lasx_xvfrintrp_d(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfrintrm_s(a: m256) -> m256 { - unsafe { transmute(__lasx_xvfrintrm_s(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfrintrm_d(a: m256d) -> m256d { - unsafe { transmute(__lasx_xvfrintrm_d(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn lasx_xvld(mem_addr: *const i8) -> m256i { - static_assert_simm_bits!(IMM_S12, 12); - transmute(__lasx_xvld(mem_addr, IMM_S12)) -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn lasx_xvst(a: m256i, mem_addr: *mut i8) { - static_assert_simm_bits!(IMM_S12, 12); - transmute(__lasx_xvst(transmute(a), mem_addr, IMM_S12)) -} - #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2, 3)] @@ -5018,7 +2462,7 @@ pub unsafe fn lasx_xvst(a: m256i, mem_addr: *mut i8) { pub unsafe fn lasx_xvstelm_b(a: m256i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM4, 4); - transmute(__lasx_xvstelm_b(transmute(a), mem_addr, IMM_S8, IMM4)) + __lasx_xvstelm_b(transmute(a), mem_addr, IMM_S8, IMM4) } #[inline] @@ -5028,7 +2472,7 @@ pub unsafe fn lasx_xvstelm_b(a: m256i, mem_a pub unsafe fn lasx_xvstelm_h(a: m256i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM3, 3); - transmute(__lasx_xvstelm_h(transmute(a), mem_addr, IMM_S8, IMM3)) + __lasx_xvstelm_h(transmute(a), mem_addr, IMM_S8, IMM3) } #[inline] @@ -5038,7 +2482,7 @@ pub unsafe fn lasx_xvstelm_h(a: m256i, mem_a pub unsafe fn lasx_xvstelm_w(a: m256i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM2, 2); - transmute(__lasx_xvstelm_w(transmute(a), mem_addr, IMM_S8, IMM2)) + __lasx_xvstelm_w(transmute(a), mem_addr, IMM_S8, IMM2) } #[inline] @@ -5048,7 +2492,7 @@ pub unsafe fn lasx_xvstelm_w(a: m256i, mem_a pub unsafe fn lasx_xvstelm_d(a: m256i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM1, 1); - transmute(__lasx_xvstelm_d(transmute(a), mem_addr, IMM_S8, IMM1)) + __lasx_xvstelm_d(transmute(a), mem_addr, IMM_S8, IMM1) } #[inline] @@ -5129,36 +2573,6 @@ pub fn lasx_xvssrln_w_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrln_w_d(transmute(a), transmute(b))) } } -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvorn_v(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvorn_v(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(0)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvldi() -> m256i { - static_assert_simm_bits!(IMM_S13, 13); - unsafe { transmute(__lasx_xvldi(IMM_S13)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn lasx_xvldx(mem_addr: *const i8, b: i64) -> m256i { - transmute(__lasx_xvldx(mem_addr, transmute(b))) -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn lasx_xvstx(a: m256i, mem_addr: *mut i8, b: i64) { - transmute(__lasx_xvstx(transmute(a), mem_addr, transmute(b))) -} - #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5166,59 +2580,6 @@ pub fn lasx_xvextl_qu_du(a: m256i) -> m256i { unsafe { transmute(__lasx_xvextl_qu_du(transmute(a))) } } -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvinsgr2vr_w(a: m256i, b: i32) -> m256i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvinsgr2vr_w(transmute(a), transmute(b), IMM3)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvinsgr2vr_d(a: m256i, b: i64) -> m256i { - static_assert_uimm_bits!(IMM2, 2); - unsafe { transmute(__lasx_xvinsgr2vr_d(transmute(a), transmute(b), IMM2)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvreplve0_b(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvreplve0_b(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvreplve0_h(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvreplve0_h(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvreplve0_w(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvreplve0_w(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvreplve0_d(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvreplve0_d(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvreplve0_q(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvreplve0_q(transmute(a))) } -} - #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5364,42 +2725,6 @@ pub unsafe fn lasx_xvldrepl_d(mem_addr: *const i8) -> m256i { transmute(__lasx_xvldrepl_d(mem_addr, IMM_S9)) } -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickve2gr_w(a: m256i) -> i32 { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvpickve2gr_w(transmute(a), IMM3)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickve2gr_wu(a: m256i) -> u32 { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvpickve2gr_wu(transmute(a), IMM3)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickve2gr_d(a: m256i) -> i64 { - static_assert_uimm_bits!(IMM2, 2); - unsafe { transmute(__lasx_xvpickve2gr_d(transmute(a), IMM2)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickve2gr_du(a: m256i) -> u64 { - static_assert_uimm_bits!(IMM2, 2); - unsafe { transmute(__lasx_xvpickve2gr_du(transmute(a), IMM2)) } -} - #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6016,34 +3341,6 @@ pub fn lasx_xvmaddwod_h_bu_b(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwod_h_bu_b(transmute(a), transmute(b), transmute(c))) } } -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrotr_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvrotr_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrotr_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvrotr_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrotr_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvrotr_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrotr_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvrotr_d(transmute(a), transmute(b))) } -} - #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6156,42 +3453,6 @@ pub fn lasx_xvexth_qu_du(a: m256i) -> m256i { unsafe { transmute(__lasx_xvexth_qu_du(transmute(a))) } } -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrotri_b(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvrotri_b(transmute(a), IMM3)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrotri_h(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lasx_xvrotri_h(transmute(a), IMM4)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrotri_w(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvrotri_w(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrotri_d(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lasx_xvrotri_d(transmute(a), IMM6)) } -} - #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -7029,36 +4290,126 @@ pub fn lasx_xvpickve_w_f(a: m256) -> m256 { #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrepli_b() -> m256i { - static_assert_simm_bits!(IMM_S10, 10); - unsafe { transmute(__lasx_xvrepli_b(IMM_S10)) } +pub fn lasx_cast_128_s(a: m128) -> m256 { + unsafe { transmute(__lasx_cast_128_s(transmute(a))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrepli_d() -> m256i { - static_assert_simm_bits!(IMM_S10, 10); - unsafe { transmute(__lasx_xvrepli_d(IMM_S10)) } +pub fn lasx_cast_128_d(a: m128d) -> m256d { + unsafe { transmute(__lasx_cast_128_d(transmute(a))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrepli_h() -> m256i { - static_assert_simm_bits!(IMM_S10, 10); - unsafe { transmute(__lasx_xvrepli_h(IMM_S10)) } +pub fn lasx_cast_128(a: m128i) -> m256i { + unsafe { transmute(__lasx_cast_128(transmute(a))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrepli_w() -> m256i { - static_assert_simm_bits!(IMM_S10, 10); - unsafe { transmute(__lasx_xvrepli_w(IMM_S10)) } +pub fn lasx_concat_128_s(a: m128, b: m128) -> m256 { + unsafe { transmute(__lasx_concat_128_s(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_concat_128_d(a: m128d, b: m128d) -> m256d { + unsafe { transmute(__lasx_concat_128_d(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_concat_128(a: m128i, b: m128i) -> m256i { + unsafe { transmute(__lasx_concat_128(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_extract_128_lo_s(a: m256) -> m128 { + unsafe { transmute(__lasx_extract_128_lo_s(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_extract_128_hi_s(a: m256) -> m128 { + unsafe { transmute(__lasx_extract_128_hi_s(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_extract_128_lo_d(a: m256d) -> m128d { + unsafe { transmute(__lasx_extract_128_lo_d(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_extract_128_hi_d(a: m256d) -> m128d { + unsafe { transmute(__lasx_extract_128_hi_d(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_extract_128_lo(a: m256i) -> m128i { + unsafe { transmute(__lasx_extract_128_lo(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_extract_128_hi(a: m256i) -> m128i { + unsafe { transmute(__lasx_extract_128_hi(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_insert_128_lo_s(a: m256, b: m128) -> m256 { + unsafe { transmute(__lasx_insert_128_lo_s(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_insert_128_hi_s(a: m256, b: m128) -> m256 { + unsafe { transmute(__lasx_insert_128_hi_s(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_insert_128_lo_d(a: m256d, b: m128d) -> m256d { + unsafe { transmute(__lasx_insert_128_lo_d(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_insert_128_hi_d(a: m256d, b: m128d) -> m256d { + unsafe { transmute(__lasx_insert_128_hi_d(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_insert_128_lo(a: m256i, b: m128i) -> m256i { + unsafe { transmute(__lasx_insert_128_lo(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_insert_128_hi(a: m256i, b: m128i) -> m256i { + unsafe { transmute(__lasx_insert_128_hi(transmute(a), transmute(b))) } } diff --git a/library/stdarch/crates/core_arch/src/loongarch64/lasx/mod.rs b/library/stdarch/crates/core_arch/src/loongarch64/lasx/mod.rs index c3a244e740e9f..cc449e94924f0 100644 --- a/library/stdarch/crates/core_arch/src/loongarch64/lasx/mod.rs +++ b/library/stdarch/crates/core_arch/src/loongarch64/lasx/mod.rs @@ -16,6 +16,13 @@ mod generated; #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub use self::generated::*; +#[rustfmt::skip] +mod portable; + +#[rustfmt::skip] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub use self::portable::*; + #[rustfmt::skip] #[cfg(test)] mod tests; diff --git a/library/stdarch/crates/core_arch/src/loongarch64/lasx/portable.rs b/library/stdarch/crates/core_arch/src/loongarch64/lasx/portable.rs new file mode 100644 index 0000000000000..73ea74d9dc3bb --- /dev/null +++ b/library/stdarch/crates/core_arch/src/loongarch64/lasx/portable.rs @@ -0,0 +1,1257 @@ +//! LoongArch64 LASX intrinsics - intrinsics::simd implementation + +use super::super::{simd::*, *}; +use crate::core_arch::simd::*; +use crate::intrinsics::simd::*; +use crate::mem::transmute; + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_pickev_b(a: T, b: T) -> T { + simd_shuffle!( + b, + a, + [ + 0, 2, 4, 6, 8, 10, 12, 14, 32, 34, 36, 38, 40, 42, 44, 46, + 16, 18, 20, 22, 24, 26, 28, 30, 48, 50, 52, 54, 56, 58, 60, 62 + ] + ) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_pickev_h(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 2, 4, 6, 16, 18, 20, 22, 8, 10, 12, 14, 24, 26, 28, 30]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_pickev_w(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 2, 8, 10, 4, 6, 12, 14]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_pickev_d(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 4, 2, 6]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_pickod_b(a: T, b: T) -> T { + simd_shuffle!( + b, + a, + [ + 1, 3, 5, 7, 9, 11, 13, 15, 33, 35, 37, 39, 41, 43, 45, 47, + 17, 19, 21, 23, 25, 27, 29, 31, 49, 51, 53, 55, 57, 59, 61, 63 + ] + ) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_pickod_h(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 3, 5, 7, 17, 19, 21, 23, 9, 11, 13, 15, 25, 27, 29, 31]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_pickod_w(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 3, 9, 11, 5, 7, 13, 15]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_pickod_d(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 5, 3, 7]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_ilvh_b(a: T, b: T) -> T { + simd_shuffle!( + b, + a, + [ + 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47, + 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63 + ] + ) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_ilvh_h(a: T, b: T) -> T { + simd_shuffle!(b, a, [4, 20, 5, 21, 6, 22, 7, 23, 12, 28, 13, 29, 14, 30, 15, 31]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_ilvh_w(a: T, b: T) -> T { + simd_shuffle!(b, a, [2, 10, 3, 11, 6, 14, 7, 15]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_ilvh_d(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 5, 3, 7]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_ilvl_b(a: T, b: T) -> T { + simd_shuffle!( + b, + a, + [ + 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39, + 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55 + ] + ) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_ilvl_h(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 16, 1, 17, 2, 18, 3, 19, 8, 24, 9, 25, 10, 26, 11, 27]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_ilvl_w(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 8, 1, 9, 4, 12, 5, 13]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_ilvl_d(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 4, 2, 6]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_replvei_b(a: T) -> T { + simd_shuffle!( + a, + a, + [ + I, I, I, I, I, I, I, I, I, I, I, I, I, I, I, I, + I + 16, I + 16, I + 16, I + 16, I + 16, I + 16, I + 16, I + 16, + I + 16, I + 16, I + 16, I + 16, I + 16, I + 16, I + 16, I + 16 + ] + ) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_replvei_h(a: T) -> T { + simd_shuffle!( + a, + a, + [ + I, I, I, I, I, I, I, I, + I + 8, I + 8, I + 8, I + 8, I + 8, I + 8, I + 8, I + 8 + ] + ) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_replvei_w(a: T) -> T { + simd_shuffle!(a, a, [I, I, I, I, I + 4, I + 4, I + 4, I + 4]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_replvei_d(a: T) -> T { + simd_shuffle!(a, a, [I, I, I + 2, I + 2]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_replve0_b(a: T) -> T { + simd_shuffle!( + a, + a, + [ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + ] + ) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_replve0_h(a: T) -> T { + simd_shuffle!(a, a, [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_replve0_w(a: T) -> T { + simd_shuffle!(a, a, [0, 0, 0, 0, 0, 0, 0, 0]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_replve0_d(a: T) -> T { + simd_shuffle!(a, a, [0, 0, 0, 0]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_replve0_q(a: T) -> T { + simd_shuffle!(a, a, [0, 1, 0, 1]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_packev_b(a: T, b: T) -> T { + simd_shuffle!( + b, + a, + [ + 0, 32, 2, 34, 4, 36, 6, 38, 8, 40, 10, 42, 12, 44, 14, 46, + 16, 48, 18, 50, 20, 52, 22, 54, 24, 56, 26, 58, 28, 60, 30, 62 + ] + ) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_packev_h(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_packev_w(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 8, 2, 10, 4, 12, 6, 14]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_packev_d(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 4, 2, 6]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_packod_b(a: T, b: T) -> T { + simd_shuffle!( + b, + a, + [ + 1, 33, 3, 35, 5, 37, 7, 39, 9, 41, 11, 43, 13, 45, 15, 47, + 17, 49, 19, 51, 21, 53, 23, 55, 25, 57, 27, 59, 29, 61, 31, 63 + ] + ) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_packod_h(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_packod_w(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 9, 3, 11, 5, 13, 7, 15]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_packod_d(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 5, 3, 7]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_shuf4i_b(a: T) -> T { + simd_shuffle!( + a, + a, + [ + ((I >> 0) & 3) + 0, ((I >> 2) & 3) + 0, ((I >> 4) & 3) + 0, ((I >> 6) & 3) + 0, + ((I >> 0) & 3) + 4, ((I >> 2) & 3) + 4, ((I >> 4) & 3) + 4, ((I >> 6) & 3) + 4, + ((I >> 0) & 3) + 8, ((I >> 2) & 3) + 8, ((I >> 4) & 3) + 8, ((I >> 6) & 3) + 8, + ((I >> 0) & 3) + 12, ((I >> 2) & 3) + 12, ((I >> 4) & 3) + 12, ((I >> 6) & 3) + 12, + ((I >> 0) & 3) + 16, ((I >> 2) & 3) + 16, ((I >> 4) & 3) + 16, ((I >> 6) & 3) + 16, + ((I >> 0) & 3) + 20, ((I >> 2) & 3) + 20, ((I >> 4) & 3) + 20, ((I >> 6) & 3) + 20, + ((I >> 0) & 3) + 24, ((I >> 2) & 3) + 24, ((I >> 4) & 3) + 24, ((I >> 6) & 3) + 24, + ((I >> 0) & 3) + 28, ((I >> 2) & 3) + 28, ((I >> 4) & 3) + 28, ((I >> 6) & 3) + 28 + ] + ) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_shuf4i_h(a: T) -> T { + simd_shuffle!( + a, + a, + [ + ((I >> 0) & 3) + 0, ((I >> 2) & 3) + 0, ((I >> 4) & 3) + 0, ((I >> 6) & 3) + 0, + ((I >> 0) & 3) + 4, ((I >> 2) & 3) + 4, ((I >> 4) & 3) + 4, ((I >> 6) & 3) + 4, + ((I >> 0) & 3) + 8, ((I >> 2) & 3) + 8, ((I >> 4) & 3) + 8, ((I >> 6) & 3) + 8, + ((I >> 0) & 3) + 12, ((I >> 2) & 3) + 12, ((I >> 4) & 3) + 12, ((I >> 6) & 3) + 12, + ] + ) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_shuf4i_w(a: T) -> T { + simd_shuffle!( + a, + a, + [ + ((I >> 0) & 3) + 0, ((I >> 2) & 3) + 0, ((I >> 4) & 3) + 0, ((I >> 6) & 3) + 0, + ((I >> 0) & 3) + 4, ((I >> 2) & 3) + 4, ((I >> 4) & 3) + 4, ((I >> 6) & 3) + 4 + ] + ) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_bsll(a: T) -> T { + let z = simd_ext_splat(0); + match I & 0xf { + 0 => simd_shuffle!( + a, + z, + [ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 + ] + ), + 1 => simd_shuffle!( + a, + z, + [ + 32, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, + 32, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 + ] + ), + 2 => simd_shuffle!( + a, + z, + [ + 32, 32, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, + 32, 32, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, + ] + ), + 3 => simd_shuffle!( + a, + z, + [ + 32, 32, 32, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, + 32, 32, 32, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, + ] + ), + 4 => simd_shuffle!( + a, + z, + [ + 32, 32, 32, 32, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, + 32, 32, 32, 32, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, + ] + ), + 5 => simd_shuffle!( + a, + z, + [ + 32, 32, 32, 32, 32, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, + 32, 32, 32, 32, 32, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, + ] + ), + 6 => simd_shuffle!( + a, + z, + [ + 32, 32, 32, 32, 32, 32, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, + 32, 32, 32, 32, 32, 32, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, + ] + ), + 7 => simd_shuffle!( + a, + z, + [ + 32, 32, 32, 32, 32, 32, 32, 0, 1, 2, 3, 4, 5, 6, 7, 8, + 32, 32, 32, 32, 32, 32, 32, 16, 17, 18, 19, 20, 21, 22, 23, 24, + ] + ), + 8 => simd_shuffle!( + a, + z, + [ + 32, 32, 32, 32, 32, 32, 32, 32, 0, 1, 2, 3, 4, 5, 6, 7, + 32, 32, 32, 32, 32, 32, 32, 32, 16, 17, 18, 19, 20, 21, 22, 23, + ] + ), + 9 => simd_shuffle!( + a, + z, + [ + 32, 32, 32, 32, 32, 32, 32, 32, 32, 0, 1, 2, 3, 4, 5, 6, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 16, 17, 18, 19, 20, 21, 22, + ] + ), + 10 => simd_shuffle!( + a, + z, + [ + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 0, 1, 2, 3, 4, 5, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 16, 17, 18, 19, 20, 21, + ] + ), + 11 => simd_shuffle!( + a, + z, + [ + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 0, 1, 2, 3, 4, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 16, 17, 18, 19, 20, + ] + ), + 12 => simd_shuffle!( + a, + z, + [ + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 0, 1, 2, 3, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 16, 17, 18, 19, + ] + ), + 13 => simd_shuffle!( + a, + z, + [ + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 0, 1, 2, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 16, 17, 18, + ] + ), + 14 => simd_shuffle!( + a, + z, + [ + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 0, 1, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 16, 17, + ] + ), + 15 => simd_shuffle!( + a, + z, + [ + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 0, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 16, + ] + ), + _ => unreachable!(), + } +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_bsrl(a: T) -> T { + let z = simd_ext_splat(0); + match I & 0xf { + 0 => simd_shuffle!( + a, + z, + [ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 + ] + ), + 1 => simd_shuffle!( + a, + z, + [ + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 32, + 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 + ] + ), + 2 => simd_shuffle!( + a, + z, + [ + 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 32, 32, + 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 32 + ] + ), + 3 => simd_shuffle!( + a, + z, + [ + 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 32, 32, 32, + 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 32, 32 + ] + ), + 4 => simd_shuffle!( + a, + z, + [ + 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 32, 32, 32, 32, + 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 32, 32, 32 + ] + ), + 5 => simd_shuffle!( + a, + z, + [ + 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 32, 32, 32, 32, 32, + 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 32, 32, 32, 32 + ] + ), + 6 => simd_shuffle!( + a, + z, + [ + 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 32, 32, 32, 32, 32, 32, + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 32, 32, 32, 32, 32 + ] + ), + 7 => simd_shuffle!( + a, + z, + [ + 7, 8, 9, 10, 11, 12, 13, 14, 15, 32, 32, 32, 32, 32, 32, 32, + 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 32, 32, 32, 32, 32, 32 + ] + ), + 8 => simd_shuffle!( + a, + z, + [ + 8, 9, 10, 11, 12, 13, 14, 15, 32, 32, 32, 32, 32, 32, 32, 32, + 24, 25, 26, 27, 28, 29, 30, 31, 32, 32, 32, 32, 32, 32, 32, 32 + ] + ), + 9 => simd_shuffle!( + a, + z, + [ + 9, 10, 11, 12, 13, 14, 15, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 25, 26, 27, 28, 29, 30, 31, 32, 32, 32, 32, 32, 32, 32, 32, 32 + ] + ), + 10 => simd_shuffle!( + a, + z, + [ + 10, 11, 12, 13, 14, 15, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 26, 27, 28, 29, 30, 31, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32 + ] + ), + 11 => simd_shuffle!( + a, + z, + [ + 11, 12, 13, 14, 15, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 27, 28, 29, 30, 31, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32 + ] + ), + 12 => simd_shuffle!( + a, + z, + [ + 12, 13, 14, 15, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 28, 29, 30, 31, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32 + ] + ), + 13 => simd_shuffle!( + a, + z, + [ + 13, 14, 15, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 29, 30, 31, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32 + ] + ), + 14 => simd_shuffle!( + a, + z, + [ + 14, 15, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 30, 31, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32 + ] + ), + 15 => simd_shuffle!( + a, + z, + [ + 15, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 31, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32 + ] + ), + _ => unreachable!(), + } +} + +impl_vv!("lasx", lasx_xvpcnt_b, simd_ctpop, m256i, i8x32); +impl_vv!("lasx", lasx_xvpcnt_h, simd_ctpop, m256i, i16x16); +impl_vv!("lasx", lasx_xvpcnt_w, simd_ctpop, m256i, i32x8); +impl_vv!("lasx", lasx_xvpcnt_d, simd_ctpop, m256i, i64x4); +impl_vv!("lasx", lasx_xvclz_b, simd_ctlz, m256i, i8x32); +impl_vv!("lasx", lasx_xvclz_h, simd_ctlz, m256i, i16x16); +impl_vv!("lasx", lasx_xvclz_w, simd_ctlz, m256i, i32x8); +impl_vv!("lasx", lasx_xvclz_d, simd_ctlz, m256i, i64x4); +impl_vv!("lasx", lasx_xvneg_b, simd_neg, m256i, i8x32); +impl_vv!("lasx", lasx_xvneg_h, simd_neg, m256i, i16x16); +impl_vv!("lasx", lasx_xvneg_w, simd_neg, m256i, i32x8); +impl_vv!("lasx", lasx_xvneg_d, simd_neg, m256i, i64x4); +impl_vv!("lasx", lasx_xvfsqrt_s, simd_fsqrt, m256, f32x8); +impl_vv!("lasx", lasx_xvfsqrt_d, simd_fsqrt, m256d, f64x4); +impl_vv!("lasx", lasx_xvfrsqrt_s, simd_ext_frsqrt_s, m256, f32x8); +impl_vv!("lasx", lasx_xvfrsqrt_d, simd_ext_frsqrt_d, m256d, f64x4); +impl_vv!("lasx", lasx_xvfrecip_s, simd_ext_frecip_s, m256, f32x8); +impl_vv!("lasx", lasx_xvfrecip_d, simd_ext_frecip_d, m256d, f64x4); +impl_vv!("lasx", lasx_xvfrintrp_s, simd_ceil, m256, f32x8); +impl_vv!("lasx", lasx_xvfrintrp_d, simd_ceil, m256d, f64x4); +impl_vv!("lasx", lasx_xvfrintrm_s, simd_floor, m256, f32x8); +impl_vv!("lasx", lasx_xvfrintrm_d, simd_floor, m256d, f64x4); +impl_vv!("lasx", lasx_xvfrintrz_s, simd_trunc, m256, f32x8); +impl_vv!("lasx", lasx_xvfrintrz_d, simd_trunc, m256d, f64x4); +impl_vv!("lasx", lasx_xvreplve0_b, simd_ext_replve0_b, m256i, i8x32); +impl_vv!("lasx", lasx_xvreplve0_h, simd_ext_replve0_h, m256i, i16x16); +impl_vv!("lasx", lasx_xvreplve0_w, simd_ext_replve0_w, m256i, i32x8); +impl_vv!("lasx", lasx_xvreplve0_d, simd_ext_replve0_d, m256i, i64x4); +impl_vv!("lasx", lasx_xvreplve0_q, simd_ext_replve0_q, m256i, i64x4); + +impl_gv!("lasx", lasx_xvreplgr2vr_b, simd_ext_splat, m256i, i8x32, i32); +impl_gv!("lasx", lasx_xvreplgr2vr_h, simd_ext_splat, m256i, i16x16, i32); +impl_gv!("lasx", lasx_xvreplgr2vr_w, simd_ext_splat, m256i, i32x8, i32); +impl_gv!("lasx", lasx_xvreplgr2vr_d, simd_ext_splat, m256i, i64x4, i64); + +impl_ggv!("lasx", lasx_xvldx, simd_ext_ldx, m256i, i8x32, *const i8, i64, unsafe); + +impl_gsv!("lasx", lasx_xvld, simd_ext_ld, m256i, i8x32, *const i8, 12, const, unsafe); + +impl_sv!("lasx", lasx_xvrepli_b, simd_ext_splat, m256i, i8x32, 10); +impl_sv!("lasx", lasx_xvrepli_h, simd_ext_splat, m256i, i16x16, 10); +impl_sv!("lasx", lasx_xvrepli_w, simd_ext_splat, m256i, i32x8, 10); +impl_sv!("lasx", lasx_xvrepli_d, simd_ext_splat, m256i, i64x4, 10); +impl_sv!("lasx", lasx_xvldi, simd_ext_ldi, m256i, i64x4, 13, const); + +impl_vvv!("lasx", lasx_xvadd_b, simd_add, m256i, i8x32); +impl_vvv!("lasx", lasx_xvadd_h, simd_add, m256i, i16x16); +impl_vvv!("lasx", lasx_xvadd_w, simd_add, m256i, i32x8); +impl_vvv!("lasx", lasx_xvadd_d, simd_add, m256i, i64x4); +impl_vvv!("lasx", lasx_xvsub_b, simd_sub, m256i, i8x32); +impl_vvv!("lasx", lasx_xvsub_h, simd_sub, m256i, i16x16); +impl_vvv!("lasx", lasx_xvsub_w, simd_sub, m256i, i32x8); +impl_vvv!("lasx", lasx_xvsub_d, simd_sub, m256i, i64x4); +impl_vvv!("lasx", lasx_xvmax_b, simd_imax, m256i, i8x32); +impl_vvv!("lasx", lasx_xvmax_h, simd_imax, m256i, i16x16); +impl_vvv!("lasx", lasx_xvmax_w, simd_imax, m256i, i32x8); +impl_vvv!("lasx", lasx_xvmax_d, simd_imax, m256i, i64x4); +impl_vvv!("lasx", lasx_xvmax_bu, simd_imax, m256i, u8x32); +impl_vvv!("lasx", lasx_xvmax_hu, simd_imax, m256i, u16x16); +impl_vvv!("lasx", lasx_xvmax_wu, simd_imax, m256i, u32x8); +impl_vvv!("lasx", lasx_xvmax_du, simd_imax, m256i, u64x4); +impl_vvv!("lasx", lasx_xvmin_b, simd_imin, m256i, i8x32); +impl_vvv!("lasx", lasx_xvmin_h, simd_imin, m256i, i16x16); +impl_vvv!("lasx", lasx_xvmin_w, simd_imin, m256i, i32x8); +impl_vvv!("lasx", lasx_xvmin_d, simd_imin, m256i, i64x4); +impl_vvv!("lasx", lasx_xvmin_bu, simd_imin, m256i, u8x32); +impl_vvv!("lasx", lasx_xvmin_hu, simd_imin, m256i, u16x16); +impl_vvv!("lasx", lasx_xvmin_wu, simd_imin, m256i, u32x8); +impl_vvv!("lasx", lasx_xvmin_du, simd_imin, m256i, u64x4); +impl_vvv!("lasx", lasx_xvseq_b, simd_eq, m256i, i8x32); +impl_vvv!("lasx", lasx_xvseq_h, simd_eq, m256i, i16x16); +impl_vvv!("lasx", lasx_xvseq_w, simd_eq, m256i, i32x8); +impl_vvv!("lasx", lasx_xvseq_d, simd_eq, m256i, i64x4); +impl_vvv!("lasx", lasx_xvslt_b, simd_lt, m256i, i8x32); +impl_vvv!("lasx", lasx_xvslt_h, simd_lt, m256i, i16x16); +impl_vvv!("lasx", lasx_xvslt_w, simd_lt, m256i, i32x8); +impl_vvv!("lasx", lasx_xvslt_d, simd_lt, m256i, i64x4); +impl_vvv!("lasx", lasx_xvslt_bu, simd_lt, m256i, u8x32); +impl_vvv!("lasx", lasx_xvslt_hu, simd_lt, m256i, u16x16); +impl_vvv!("lasx", lasx_xvslt_wu, simd_lt, m256i, u32x8); +impl_vvv!("lasx", lasx_xvslt_du, simd_lt, m256i, u64x4); +impl_vvv!("lasx", lasx_xvsle_b, simd_le, m256i, i8x32); +impl_vvv!("lasx", lasx_xvsle_h, simd_le, m256i, i16x16); +impl_vvv!("lasx", lasx_xvsle_w, simd_le, m256i, i32x8); +impl_vvv!("lasx", lasx_xvsle_d, simd_le, m256i, i64x4); +impl_vvv!("lasx", lasx_xvsle_bu, simd_le, m256i, u8x32); +impl_vvv!("lasx", lasx_xvsle_hu, simd_le, m256i, u16x16); +impl_vvv!("lasx", lasx_xvsle_wu, simd_le, m256i, u32x8); +impl_vvv!("lasx", lasx_xvsle_du, simd_le, m256i, u64x4); +impl_vvv!("lasx", lasx_xvmul_b, simd_mul, m256i, i8x32); +impl_vvv!("lasx", lasx_xvmul_h, simd_mul, m256i, i16x16); +impl_vvv!("lasx", lasx_xvmul_w, simd_mul, m256i, i32x8); +impl_vvv!("lasx", lasx_xvmul_d, simd_mul, m256i, i64x4); +impl_vvv!("lasx", lasx_xvdiv_b, simd_div, m256i, i8x32); +impl_vvv!("lasx", lasx_xvdiv_h, simd_div, m256i, i16x16); +impl_vvv!("lasx", lasx_xvdiv_w, simd_div, m256i, i32x8); +impl_vvv!("lasx", lasx_xvdiv_d, simd_div, m256i, i64x4); +impl_vvv!("lasx", lasx_xvdiv_bu, simd_div, m256i, u8x32); +impl_vvv!("lasx", lasx_xvdiv_hu, simd_div, m256i, u16x16); +impl_vvv!("lasx", lasx_xvdiv_wu, simd_div, m256i, u32x8); +impl_vvv!("lasx", lasx_xvdiv_du, simd_div, m256i, u64x4); +impl_vvv!("lasx", lasx_xvmod_b, simd_rem, m256i, i8x32); +impl_vvv!("lasx", lasx_xvmod_h, simd_rem, m256i, i16x16); +impl_vvv!("lasx", lasx_xvmod_w, simd_rem, m256i, i32x8); +impl_vvv!("lasx", lasx_xvmod_d, simd_rem, m256i, i64x4); +impl_vvv!("lasx", lasx_xvmod_bu, simd_rem, m256i, u8x32); +impl_vvv!("lasx", lasx_xvmod_hu, simd_rem, m256i, u16x16); +impl_vvv!("lasx", lasx_xvmod_wu, simd_rem, m256i, u32x8); +impl_vvv!("lasx", lasx_xvmod_du, simd_rem, m256i, u64x4); +impl_vvv!("lasx", lasx_xvand_v, simd_and, m256i, u8x32); +impl_vvv!("lasx", lasx_xvandn_v, simd_ext_andn, m256i, u8x32); +impl_vvv!("lasx", lasx_xvor_v, simd_or, m256i, u8x32); +impl_vvv!("lasx", lasx_xvorn_v, simd_ext_orn, m256i, u8x32); +impl_vvv!("lasx", lasx_xvnor_v, simd_ext_nor, m256i, u8x32); +impl_vvv!("lasx", lasx_xvxor_v, simd_xor, m256i, u8x32); +impl_vvv!("lasx", lasx_xvfadd_s, simd_add, m256, f32x8); +impl_vvv!("lasx", lasx_xvfadd_d, simd_add, m256d, f64x4); +impl_vvv!("lasx", lasx_xvfsub_s, simd_sub, m256, f32x8); +impl_vvv!("lasx", lasx_xvfsub_d, simd_sub, m256d, f64x4); +impl_vvv!("lasx", lasx_xvfmul_s, simd_mul, m256, f32x8); +impl_vvv!("lasx", lasx_xvfmul_d, simd_mul, m256d, f64x4); +impl_vvv!("lasx", lasx_xvfdiv_s, simd_div, m256, f32x8); +impl_vvv!("lasx", lasx_xvfdiv_d, simd_div, m256d, f64x4); +impl_vvv!("lasx", lasx_xvsll_b, simd_ext_shl, m256i, i8x32); +impl_vvv!("lasx", lasx_xvsll_h, simd_ext_shl, m256i, i16x16); +impl_vvv!("lasx", lasx_xvsll_w, simd_ext_shl, m256i, i32x8); +impl_vvv!("lasx", lasx_xvsll_d, simd_ext_shl, m256i, i64x4); +impl_vvv!("lasx", lasx_xvsra_b, simd_ext_shr, m256i, i8x32); +impl_vvv!("lasx", lasx_xvsra_h, simd_ext_shr, m256i, i16x16); +impl_vvv!("lasx", lasx_xvsra_w, simd_ext_shr, m256i, i32x8); +impl_vvv!("lasx", lasx_xvsra_d, simd_ext_shr, m256i, i64x4); +impl_vvv!("lasx", lasx_xvsrl_b, simd_ext_shr, m256i, u8x32); +impl_vvv!("lasx", lasx_xvsrl_h, simd_ext_shr, m256i, u16x16); +impl_vvv!("lasx", lasx_xvsrl_w, simd_ext_shr, m256i, u32x8); +impl_vvv!("lasx", lasx_xvsrl_d, simd_ext_shr, m256i, u64x4); +impl_vvv!("lasx", lasx_xvrotr_b, simd_ext_rotr, m256i, u8x32); +impl_vvv!("lasx", lasx_xvrotr_h, simd_ext_rotr, m256i, u16x16); +impl_vvv!("lasx", lasx_xvrotr_w, simd_ext_rotr, m256i, u32x8); +impl_vvv!("lasx", lasx_xvrotr_d, simd_ext_rotr, m256i, u64x4); +impl_vvv!("lasx", lasx_xvbitclr_b, simd_ext_bitclr, m256i, u8x32); +impl_vvv!("lasx", lasx_xvbitclr_h, simd_ext_bitclr, m256i, u16x16); +impl_vvv!("lasx", lasx_xvbitclr_w, simd_ext_bitclr, m256i, u32x8); +impl_vvv!("lasx", lasx_xvbitclr_d, simd_ext_bitclr, m256i, u64x4); +impl_vvv!("lasx", lasx_xvbitset_b, simd_ext_bitset, m256i, u8x32); +impl_vvv!("lasx", lasx_xvbitset_h, simd_ext_bitset, m256i, u16x16); +impl_vvv!("lasx", lasx_xvbitset_w, simd_ext_bitset, m256i, u32x8); +impl_vvv!("lasx", lasx_xvbitset_d, simd_ext_bitset, m256i, u64x4); +impl_vvv!("lasx", lasx_xvbitrev_b, simd_ext_bitrev, m256i, u8x32); +impl_vvv!("lasx", lasx_xvbitrev_h, simd_ext_bitrev, m256i, u16x16); +impl_vvv!("lasx", lasx_xvbitrev_w, simd_ext_bitrev, m256i, u32x8); +impl_vvv!("lasx", lasx_xvbitrev_d, simd_ext_bitrev, m256i, u64x4); +impl_vvv!("lasx", lasx_xvsadd_b, simd_saturating_add, m256i, i8x32); +impl_vvv!("lasx", lasx_xvsadd_h, simd_saturating_add, m256i, i16x16); +impl_vvv!("lasx", lasx_xvsadd_w, simd_saturating_add, m256i, i32x8); +impl_vvv!("lasx", lasx_xvsadd_d, simd_saturating_add, m256i, i64x4); +impl_vvv!("lasx", lasx_xvsadd_bu, simd_saturating_add, m256i, u8x32); +impl_vvv!("lasx", lasx_xvsadd_hu, simd_saturating_add, m256i, u16x16); +impl_vvv!("lasx", lasx_xvsadd_wu, simd_saturating_add, m256i, u32x8); +impl_vvv!("lasx", lasx_xvsadd_du, simd_saturating_add, m256i, u64x4); +impl_vvv!("lasx", lasx_xvssub_b, simd_saturating_sub, m256i, i8x32); +impl_vvv!("lasx", lasx_xvssub_h, simd_saturating_sub, m256i, i16x16); +impl_vvv!("lasx", lasx_xvssub_w, simd_saturating_sub, m256i, i32x8); +impl_vvv!("lasx", lasx_xvssub_d, simd_saturating_sub, m256i, i64x4); +impl_vvv!("lasx", lasx_xvssub_bu, simd_saturating_sub, m256i, u8x32); +impl_vvv!("lasx", lasx_xvssub_hu, simd_saturating_sub, m256i, u16x16); +impl_vvv!("lasx", lasx_xvssub_wu, simd_saturating_sub, m256i, u32x8); +impl_vvv!("lasx", lasx_xvssub_du, simd_saturating_sub, m256i, u64x4); +impl_vvv!("lasx", lasx_xvadda_b, simd_ext_adda, m256i, i8x32); +impl_vvv!("lasx", lasx_xvadda_h, simd_ext_adda, m256i, i16x16); +impl_vvv!("lasx", lasx_xvadda_w, simd_ext_adda, m256i, i32x8); +impl_vvv!("lasx", lasx_xvadda_d, simd_ext_adda, m256i, i64x4); +impl_vvv!("lasx", lasx_xvabsd_b, simd_ext_absd, m256i, i8x32); +impl_vvv!("lasx", lasx_xvabsd_h, simd_ext_absd, m256i, i16x16); +impl_vvv!("lasx", lasx_xvabsd_w, simd_ext_absd, m256i, i32x8); +impl_vvv!("lasx", lasx_xvabsd_d, simd_ext_absd, m256i, i64x4); +impl_vvv!("lasx", lasx_xvabsd_bu, simd_ext_absd, m256i, u8x32); +impl_vvv!("lasx", lasx_xvabsd_hu, simd_ext_absd, m256i, u16x16); +impl_vvv!("lasx", lasx_xvabsd_wu, simd_ext_absd, m256i, u32x8); +impl_vvv!("lasx", lasx_xvabsd_du, simd_ext_absd, m256i, u64x4); +impl_vvv!("lasx", lasx_xvmuh_b, simd_ext_muh, m256i, i8x32, i16x32); +impl_vvv!("lasx", lasx_xvmuh_h, simd_ext_muh, m256i, i16x16, i32x16); +impl_vvv!("lasx", lasx_xvmuh_w, simd_ext_muh, m256i, i32x8, i64x8); +impl_vvv!("lasx", lasx_xvmuh_d, simd_ext_muh, m256i, i64x4, i128x4); +impl_vvv!("lasx", lasx_xvmuh_bu, simd_ext_muh, m256i, u8x32, u16x32); +impl_vvv!("lasx", lasx_xvmuh_hu, simd_ext_muh, m256i, u16x16, u32x16); +impl_vvv!("lasx", lasx_xvmuh_wu, simd_ext_muh, m256i, u32x8, u64x8); +impl_vvv!("lasx", lasx_xvmuh_du, simd_ext_muh, m256i, u64x4, u128x4); +impl_vvv!("lasx", lasx_xvpickev_b, simd_ext_pickev_b, m256i, i8x32); +impl_vvv!("lasx", lasx_xvpickev_h, simd_ext_pickev_h, m256i, i16x16); +impl_vvv!("lasx", lasx_xvpickev_w, simd_ext_pickev_w, m256i, i32x8); +impl_vvv!("lasx", lasx_xvpickev_d, simd_ext_pickev_d, m256i, i64x4); +impl_vvv!("lasx", lasx_xvpickod_b, simd_ext_pickod_b, m256i, i8x32); +impl_vvv!("lasx", lasx_xvpickod_h, simd_ext_pickod_h, m256i, i16x16); +impl_vvv!("lasx", lasx_xvpickod_w, simd_ext_pickod_w, m256i, i32x8); +impl_vvv!("lasx", lasx_xvpickod_d, simd_ext_pickod_d, m256i, i64x4); +impl_vvv!("lasx", lasx_xvilvh_b, simd_ext_ilvh_b, m256i, i8x32); +impl_vvv!("lasx", lasx_xvilvh_h, simd_ext_ilvh_h, m256i, i16x16); +impl_vvv!("lasx", lasx_xvilvh_w, simd_ext_ilvh_w, m256i, i32x8); +impl_vvv!("lasx", lasx_xvilvh_d, simd_ext_ilvh_d, m256i, i64x4); +impl_vvv!("lasx", lasx_xvilvl_b, simd_ext_ilvl_b, m256i, i8x32); +impl_vvv!("lasx", lasx_xvilvl_h, simd_ext_ilvl_h, m256i, i16x16); +impl_vvv!("lasx", lasx_xvilvl_w, simd_ext_ilvl_w, m256i, i32x8); +impl_vvv!("lasx", lasx_xvilvl_d, simd_ext_ilvl_d, m256i, i64x4); +impl_vvv!("lasx", lasx_xvpackev_b, simd_ext_packev_b, m256i, i8x32); +impl_vvv!("lasx", lasx_xvpackev_h, simd_ext_packev_h, m256i, i16x16); +impl_vvv!("lasx", lasx_xvpackev_w, simd_ext_packev_w, m256i, i32x8); +impl_vvv!("lasx", lasx_xvpackev_d, simd_ext_packev_d, m256i, i64x4); +impl_vvv!("lasx", lasx_xvpackod_b, simd_ext_packod_b, m256i, i8x32); +impl_vvv!("lasx", lasx_xvpackod_h, simd_ext_packod_h, m256i, i16x16); +impl_vvv!("lasx", lasx_xvpackod_w, simd_ext_packod_w, m256i, i32x8); +impl_vvv!("lasx", lasx_xvpackod_d, simd_ext_packod_d, m256i, i64x4); + +impl_vgg!("lasx", lasx_xvstx, simd_ext_stx, m256i, i8x32, *mut i8, i64, unsafe); + +impl_vgs!("lasx", lasx_xvst, simd_ext_st, m256i, i8x32, *mut i8, 12, const, unsafe); + +impl_vuv!("lasx", lasx_xvslli_b, simd_shl, m256i, i8x32); +impl_vuv!("lasx", lasx_xvslli_h, simd_shl, m256i, i16x16); +impl_vuv!("lasx", lasx_xvslli_w, simd_shl, m256i, i32x8); +impl_vuv!("lasx", lasx_xvslli_d, simd_shl, m256i, i64x4); +impl_vuv!("lasx", lasx_xvsrai_b, simd_shr, m256i, i8x32); +impl_vuv!("lasx", lasx_xvsrai_h, simd_shr, m256i, i16x16); +impl_vuv!("lasx", lasx_xvsrai_w, simd_shr, m256i, i32x8); +impl_vuv!("lasx", lasx_xvsrai_d, simd_shr, m256i, i64x4); +impl_vuv!("lasx", lasx_xvsrli_b, simd_shr, m256i, u8x32); +impl_vuv!("lasx", lasx_xvsrli_h, simd_shr, m256i, u16x16); +impl_vuv!("lasx", lasx_xvsrli_w, simd_shr, m256i, u32x8); +impl_vuv!("lasx", lasx_xvsrli_d, simd_shr, m256i, u64x4); +impl_vuv!("lasx", lasx_xvrotri_b, simd_ext_rotr, m256i, u8x32); +impl_vuv!("lasx", lasx_xvrotri_h, simd_ext_rotr, m256i, u16x16); +impl_vuv!("lasx", lasx_xvrotri_w, simd_ext_rotr, m256i, u32x8); +impl_vuv!("lasx", lasx_xvrotri_d, simd_ext_rotr, m256i, u64x4); +impl_vuv!("lasx", lasx_xvaddi_bu, simd_add, m256i, u8x32, 5); +impl_vuv!("lasx", lasx_xvaddi_hu, simd_add, m256i, u16x16, 5); +impl_vuv!("lasx", lasx_xvaddi_wu, simd_add, m256i, u32x8, 5); +impl_vuv!("lasx", lasx_xvaddi_du, simd_add, m256i, u64x4, 5); +impl_vuv!("lasx", lasx_xvslti_bu, simd_lt, m256i, u8x32, 5); +impl_vuv!("lasx", lasx_xvslti_hu, simd_lt, m256i, u16x16, 5); +impl_vuv!("lasx", lasx_xvslti_wu, simd_lt, m256i, u32x8, 5); +impl_vuv!("lasx", lasx_xvslti_du, simd_lt, m256i, u64x4, 5); +impl_vuv!("lasx", lasx_xvslei_bu, simd_le, m256i, u8x32, 5); +impl_vuv!("lasx", lasx_xvslei_hu, simd_le, m256i, u16x16, 5); +impl_vuv!("lasx", lasx_xvslei_wu, simd_le, m256i, u32x8, 5); +impl_vuv!("lasx", lasx_xvslei_du, simd_le, m256i, u64x4, 5); +impl_vuv!("lasx", lasx_xvmaxi_bu, simd_imax, m256i, u8x32, 5); +impl_vuv!("lasx", lasx_xvmaxi_hu, simd_imax, m256i, u16x16, 5); +impl_vuv!("lasx", lasx_xvmaxi_wu, simd_imax, m256i, u32x8, 5); +impl_vuv!("lasx", lasx_xvmaxi_du, simd_imax, m256i, u64x4, 5); +impl_vuv!("lasx", lasx_xvmini_bu, simd_imin, m256i, u8x32, 5); +impl_vuv!("lasx", lasx_xvmini_hu, simd_imin, m256i, u16x16, 5); +impl_vuv!("lasx", lasx_xvmini_wu, simd_imin, m256i, u32x8, 5); +impl_vuv!("lasx", lasx_xvmini_du, simd_imin, m256i, u64x4, 5); +impl_vuv!("lasx", lasx_xvrepl128vei_b, simd_ext_replvei_b, m256i, i8x32, 4, const); +impl_vuv!("lasx", lasx_xvrepl128vei_h, simd_ext_replvei_h, m256i, i16x16, 3, const); +impl_vuv!("lasx", lasx_xvrepl128vei_w, simd_ext_replvei_w, m256i, i32x8, 2, const); +impl_vuv!("lasx", lasx_xvrepl128vei_d, simd_ext_replvei_d, m256i, i64x4, 1, const); +impl_vuv!("lasx", lasx_xvshuf4i_b, simd_ext_shuf4i_b, m256i, i8x32, 8, const); +impl_vuv!("lasx", lasx_xvshuf4i_h, simd_ext_shuf4i_h, m256i, i16x16, 8, const); +impl_vuv!("lasx", lasx_xvshuf4i_w, simd_ext_shuf4i_w, m256i, i32x8, 8, const); +impl_vuv!("lasx", lasx_xvbsll_v, simd_ext_bsll, m256i, i8x32, 5, const); +impl_vuv!("lasx", lasx_xvbsrl_v, simd_ext_bsrl, m256i, i8x32, 5, const); + +impl_vug!("lasx", lasx_xvpickve2gr_w, simd_extract, m256i, i32x8, i32, 3); +impl_vug!("lasx", lasx_xvpickve2gr_d, simd_extract, m256i, i64x4, i64, 2); +impl_vug!("lasx", lasx_xvpickve2gr_wu, simd_extract, m256i, u32x8, u32, 3); +impl_vug!("lasx", lasx_xvpickve2gr_du, simd_extract, m256i, u64x4, u64, 2); + +impl_vsv!("lasx", lasx_xvseqi_b, simd_eq, m256i, i8x32, 5); +impl_vsv!("lasx", lasx_xvseqi_h, simd_eq, m256i, i16x16, 5); +impl_vsv!("lasx", lasx_xvseqi_w, simd_eq, m256i, i32x8, 5); +impl_vsv!("lasx", lasx_xvseqi_d, simd_eq, m256i, i64x4, 5); +impl_vsv!("lasx", lasx_xvslti_b, simd_lt, m256i, i8x32, 5); +impl_vsv!("lasx", lasx_xvslti_h, simd_lt, m256i, i16x16, 5); +impl_vsv!("lasx", lasx_xvslti_w, simd_lt, m256i, i32x8, 5); +impl_vsv!("lasx", lasx_xvslti_d, simd_lt, m256i, i64x4, 5); +impl_vsv!("lasx", lasx_xvslei_b, simd_le, m256i, i8x32, 5); +impl_vsv!("lasx", lasx_xvslei_h, simd_le, m256i, i16x16, 5); +impl_vsv!("lasx", lasx_xvslei_w, simd_le, m256i, i32x8, 5); +impl_vsv!("lasx", lasx_xvslei_d, simd_le, m256i, i64x4, 5); +impl_vsv!("lasx", lasx_xvmaxi_b, simd_imax, m256i, i8x32, 5); +impl_vsv!("lasx", lasx_xvmaxi_h, simd_imax, m256i, i16x16, 5); +impl_vsv!("lasx", lasx_xvmaxi_w, simd_imax, m256i, i32x8, 5); +impl_vsv!("lasx", lasx_xvmaxi_d, simd_imax, m256i, i64x4, 5); +impl_vsv!("lasx", lasx_xvmini_b, simd_imin, m256i, i8x32, 5); +impl_vsv!("lasx", lasx_xvmini_h, simd_imin, m256i, i16x16, 5); +impl_vsv!("lasx", lasx_xvmini_w, simd_imin, m256i, i32x8, 5); +impl_vsv!("lasx", lasx_xvmini_d, simd_imin, m256i, i64x4, 5); + +impl_vvvv!("lasx", lasx_xvmadd_b, simd_ext_madd, m256i, i8x32); +impl_vvvv!("lasx", lasx_xvmadd_h, simd_ext_madd, m256i, i16x16); +impl_vvvv!("lasx", lasx_xvmadd_w, simd_ext_madd, m256i, i32x8); +impl_vvvv!("lasx", lasx_xvmadd_d, simd_ext_madd, m256i, i64x4); +impl_vvvv!("lasx", lasx_xvmsub_b, simd_ext_msub, m256i, i8x32); +impl_vvvv!("lasx", lasx_xvmsub_h, simd_ext_msub, m256i, i16x16); +impl_vvvv!("lasx", lasx_xvmsub_w, simd_ext_msub, m256i, i32x8); +impl_vvvv!("lasx", lasx_xvmsub_d, simd_ext_msub, m256i, i64x4); +impl_vvvv!("lasx", lasx_xvfmadd_s, simd_fma, m256, f32x8); +impl_vvvv!("lasx", lasx_xvfmadd_d, simd_fma, m256d, f64x4); +impl_vvvv!("lasx", lasx_xvfmsub_s, simd_ext_fmsub, m256, f32x8); +impl_vvvv!("lasx", lasx_xvfmsub_d, simd_ext_fmsub, m256d, f64x4); +impl_vvvv!("lasx", lasx_xvfnmadd_s, simd_ext_fnmadd, m256, f32x8); +impl_vvvv!("lasx", lasx_xvfnmadd_d, simd_ext_fnmadd, m256d, f64x4); +impl_vvvv!("lasx", lasx_xvfnmsub_s, simd_ext_fnmsub, m256, f32x8); +impl_vvvv!("lasx", lasx_xvfnmsub_d, simd_ext_fnmsub, m256d, f64x4); + +impl_vugv!("lasx", lasx_xvinsgr2vr_w, simd_insert, m256i, i32x8, i32, 3); +impl_vugv!("lasx", lasx_xvinsgr2vr_d, simd_insert, m256i, i64x4, i64, 2); + +#[cfg(test)] +mod tests { + use crate::{ + core_arch::{loongarch64::*, simd::*}, + mem::transmute, + }; + use std::hint::black_box; + use stdarch_test::simd_test; + + #[simd_test(enable = "lasx")] + unsafe fn xvldi() { + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvldi::<0>())); + let r = i8x32::new( + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + ); + assert_eq!(r, transmute(lasx_xvldi::<255>())); + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvldi::<1024>())); + let r = i8x32::new( + 0, -2, 0, -2, 0, -2, 0, -2, 0, -2, 0, -2, 0, -2, 0, -2, 0, -2, 0, -2, 0, -2, 0, -2, 0, + -2, 0, -2, 0, -2, 0, -2, + ); + assert_eq!(r, transmute(lasx_xvldi::<1536>())); + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvldi::<2048>())); + let r = i8x32::new( + 0, -2, -1, -1, 0, -2, -1, -1, 0, -2, -1, -1, 0, -2, -1, -1, 0, -2, -1, -1, 0, -2, -1, + -1, 0, -2, -1, -1, 0, -2, -1, -1, + ); + assert_eq!(r, transmute(lasx_xvldi::<2560>())); + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvldi::<3072>())); + let r = i8x32::new( + 0, -2, -1, -1, -1, -1, -1, -1, 0, -2, -1, -1, -1, -1, -1, -1, 0, -2, -1, -1, -1, -1, + -1, -1, 0, -2, -1, -1, -1, -1, -1, -1, + ); + assert_eq!(r, transmute(lasx_xvldi::<3584>())); + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvldi::<-4096>())); + let r = i8x32::new( + -128, 0, 0, 0, -128, 0, 0, 0, -128, 0, 0, 0, -128, 0, 0, 0, -128, 0, 0, 0, -128, 0, 0, + 0, -128, 0, 0, 0, -128, 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvldi::<-3968>())); + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvldi::<-3840>())); + let r = i8x32::new( + 0, -128, 0, 0, 0, -128, 0, 0, 0, -128, 0, 0, 0, -128, 0, 0, 0, -128, 0, 0, 0, -128, 0, + 0, 0, -128, 0, 0, 0, -128, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvldi::<-3712>())); + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvldi::<-3584>())); + let r = i8x32::new( + 0, 0, -128, 0, 0, 0, -128, 0, 0, 0, -128, 0, 0, 0, -128, 0, 0, 0, -128, 0, 0, 0, -128, + 0, 0, 0, -128, 0, 0, 0, -128, 0, + ); + assert_eq!(r, transmute(lasx_xvldi::<-3456>())); + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvldi::<-3328>())); + let r = i8x32::new( + 0, 0, 0, -128, 0, 0, 0, -128, 0, 0, 0, -128, 0, 0, 0, -128, 0, 0, 0, -128, 0, 0, 0, + -128, 0, 0, 0, -128, 0, 0, 0, -128, + ); + assert_eq!(r, transmute(lasx_xvldi::<-3200>())); + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvldi::<-3072>())); + let r = i8x32::new( + -128, 0, -128, 0, -128, 0, -128, 0, -128, 0, -128, 0, -128, 0, -128, 0, -128, 0, -128, + 0, -128, 0, -128, 0, -128, 0, -128, 0, -128, 0, -128, 0, + ); + assert_eq!(r, transmute(lasx_xvldi::<-2944>())); + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvldi::<-2816>())); + let r = i8x32::new( + 0, -128, 0, -128, 0, -128, 0, -128, 0, -128, 0, -128, 0, -128, 0, -128, 0, -128, 0, + -128, 0, -128, 0, -128, 0, -128, 0, -128, 0, -128, 0, -128, + ); + assert_eq!(r, transmute(lasx_xvldi::<-2688>())); + let r = i8x32::new( + -1, 0, 0, 0, -1, 0, 0, 0, -1, 0, 0, 0, -1, 0, 0, 0, -1, 0, 0, 0, -1, 0, 0, 0, -1, 0, 0, + 0, -1, 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvldi::<-2560>())); + let r = i8x32::new( + -1, -128, 0, 0, -1, -128, 0, 0, -1, -128, 0, 0, -1, -128, 0, 0, -1, -128, 0, 0, -1, + -128, 0, 0, -1, -128, 0, 0, -1, -128, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvldi::<-2432>())); + let r = i8x32::new( + -1, -1, 0, 0, -1, -1, 0, 0, -1, -1, 0, 0, -1, -1, 0, 0, -1, -1, 0, 0, -1, -1, 0, 0, -1, + -1, 0, 0, -1, -1, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvldi::<-2304>())); + let r = i8x32::new( + -1, -1, -128, 0, -1, -1, -128, 0, -1, -1, -128, 0, -1, -1, -128, 0, -1, -1, -128, 0, + -1, -1, -128, 0, -1, -1, -128, 0, -1, -1, -128, 0, + ); + assert_eq!(r, transmute(lasx_xvldi::<-2176>())); + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvldi::<-2048>())); + let r = i8x32::new( + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + ); + assert_eq!(r, transmute(lasx_xvldi::<-1793>())); + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvldi::<-1792>())); + let r = i8x32::new( + 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, + -1, 0, -1, 0, -1, 0, -1, + ); + assert_eq!(r, transmute(lasx_xvldi::<-1622>())); + let r = i8x32::new( + 0, 0, 0, 64, 0, 0, 0, 64, 0, 0, 0, 64, 0, 0, 0, 64, 0, 0, 0, 64, 0, 0, 0, 64, 0, 0, 0, + 64, 0, 0, 0, 64, + ); + assert_eq!(r, transmute(lasx_xvldi::<-1536>())); + let r = i8x32::new( + 0, 0, 80, -63, 0, 0, 80, -63, 0, 0, 80, -63, 0, 0, 80, -63, 0, 0, 80, -63, 0, 0, 80, + -63, 0, 0, 80, -63, 0, 0, 80, -63, + ); + assert_eq!(r, transmute(lasx_xvldi::<-1366>())); + let r = i8x32::new( + 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 64, + 0, 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvldi::<-1280>())); + let r = i8x32::new( + 0, 0, 80, -63, 0, 0, 0, 0, 0, 0, 80, -63, 0, 0, 0, 0, 0, 0, 80, -63, 0, 0, 0, 0, 0, 0, + 80, -63, 0, 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvldi::<-1110>())); + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 64, 0, 0, 0, 0, + 0, 0, 0, 64, + ); + assert_eq!(r, transmute(lasx_xvldi::<-1024>())); + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 42, -64, 0, 0, 0, 0, 0, 0, 42, -64, 0, 0, 0, 0, 0, 0, 42, -64, 0, 0, + 0, 0, 0, 0, 42, -64, + ); + assert_eq!(r, transmute(lasx_xvldi::<-854>())); + } + + #[simd_test(enable = "lasx")] + unsafe fn xvbsll_v() { + let a = i8x32::new( + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 25, 26, 27, 28, 29, 30, 31, 32, + ); + let r = i8x32::new( + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 25, 26, 27, 28, 29, 30, 31, 32, + ); + assert_eq!(r, transmute(lasx_xvbsll_v::<0>(black_box(transmute(a))))); + let r = i8x32::new( + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + ); + assert_eq!(r, transmute(lasx_xvbsll_v::<1>(black_box(transmute(a))))); + let r = i8x32::new( + 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0, 0, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, + ); + assert_eq!(r, transmute(lasx_xvbsll_v::<2>(black_box(transmute(a))))); + let r = i8x32::new( + 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 0, 0, 0, 17, 18, 19, 20, 21, 22, + 23, 24, 25, 26, 27, 28, 29, + ); + assert_eq!(r, transmute(lasx_xvbsll_v::<3>(black_box(transmute(a))))); + let r = i8x32::new( + 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 0, 0, 0, 0, 17, 18, 19, 20, 21, 22, + 23, 24, 25, 26, 27, 28, + ); + assert_eq!(r, transmute(lasx_xvbsll_v::<4>(black_box(transmute(a))))); + let r = i8x32::new( + 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 0, 0, 0, 0, 0, 17, 18, 19, 20, 21, + 22, 23, 24, 25, 26, 27, + ); + assert_eq!(r, transmute(lasx_xvbsll_v::<5>(black_box(transmute(a))))); + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 0, 0, 0, 0, 0, 0, 17, 18, 19, 20, 21, + 22, 23, 24, 25, 26, + ); + assert_eq!(r, transmute(lasx_xvbsll_v::<6>(black_box(transmute(a))))); + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 0, 0, 17, 18, 19, 20, + 21, 22, 23, 24, 25, + ); + assert_eq!(r, transmute(lasx_xvbsll_v::<7>(black_box(transmute(a))))); + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 0, 17, 18, 19, 20, + 21, 22, 23, 24, + ); + assert_eq!(r, transmute(lasx_xvbsll_v::<8>(black_box(transmute(a))))); + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, 18, 19, + 20, 21, 22, 23, + ); + assert_eq!(r, transmute(lasx_xvbsll_v::<9>(black_box(transmute(a))))); + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, 18, + 19, 20, 21, 22, + ); + assert_eq!(r, transmute(lasx_xvbsll_v::<10>(black_box(transmute(a))))); + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, + 18, 19, 20, 21, + ); + assert_eq!(r, transmute(lasx_xvbsll_v::<11>(black_box(transmute(a))))); + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, + 18, 19, 20, + ); + assert_eq!(r, transmute(lasx_xvbsll_v::<12>(black_box(transmute(a))))); + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 17, 18, 19, + ); + assert_eq!(r, transmute(lasx_xvbsll_v::<13>(black_box(transmute(a))))); + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 17, 18, + ); + assert_eq!(r, transmute(lasx_xvbsll_v::<14>(black_box(transmute(a))))); + let r = i8x32::new( + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 17, + ); + assert_eq!(r, transmute(lasx_xvbsll_v::<15>(black_box(transmute(a))))); + } + + #[simd_test(enable = "lasx")] + unsafe fn xvbsrl_v() { + let a = i8x32::new( + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 25, 26, 27, 28, 29, 30, 31, 32, + ); + let r = i8x32::new( + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 25, 26, 27, 28, 29, 30, 31, 32, + ); + assert_eq!(r, transmute(lasx_xvbsrl_v::<0>(black_box(transmute(a))))); + let r = i8x32::new( + 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 0, 18, 19, 20, 21, 22, 23, 24, 25, + 26, 27, 28, 29, 30, 31, 32, 0, + ); + assert_eq!(r, transmute(lasx_xvbsrl_v::<1>(black_box(transmute(a))))); + let r = i8x32::new( + 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 0, 0, 19, 20, 21, 22, 23, 24, 25, 26, + 27, 28, 29, 30, 31, 32, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvbsrl_v::<2>(black_box(transmute(a))))); + let r = i8x32::new( + 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 0, 0, 0, 20, 21, 22, 23, 24, 25, 26, 27, + 28, 29, 30, 31, 32, 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvbsrl_v::<3>(black_box(transmute(a))))); + let r = i8x32::new( + 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 0, 0, 0, 0, 21, 22, 23, 24, 25, 26, 27, 28, + 29, 30, 31, 32, 0, 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvbsrl_v::<4>(black_box(transmute(a))))); + let r = i8x32::new( + 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 0, 0, 0, 0, 0, 22, 23, 24, 25, 26, 27, 28, 29, + 30, 31, 32, 0, 0, 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvbsrl_v::<5>(black_box(transmute(a))))); + let r = i8x32::new( + 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 23, 24, 25, 26, 27, 28, 29, 30, + 31, 32, 0, 0, 0, 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvbsrl_v::<6>(black_box(transmute(a))))); + let r = i8x32::new( + 8, 9, 10, 11, 12, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 24, 25, 26, 27, 28, 29, 30, 31, + 32, 0, 0, 0, 0, 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvbsrl_v::<7>(black_box(transmute(a))))); + let r = i8x32::new( + 9, 10, 11, 12, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0, 25, 26, 27, 28, 29, 30, 31, 32, + 0, 0, 0, 0, 0, 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvbsrl_v::<8>(black_box(transmute(a))))); + let r = i8x32::new( + 10, 11, 12, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 26, 27, 28, 29, 30, 31, 32, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvbsrl_v::<9>(black_box(transmute(a))))); + let r = i8x32::new( + 11, 12, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 27, 28, 29, 30, 31, 32, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvbsrl_v::<10>(black_box(transmute(a))))); + let r = i8x32::new( + 12, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 28, 29, 30, 31, 32, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvbsrl_v::<11>(black_box(transmute(a))))); + let r = i8x32::new( + 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 29, 30, 31, 32, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvbsrl_v::<12>(black_box(transmute(a))))); + let r = i8x32::new( + 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 30, 31, 32, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvbsrl_v::<13>(black_box(transmute(a))))); + let r = i8x32::new( + 15, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvbsrl_v::<14>(black_box(transmute(a))))); + let r = i8x32::new( + 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, + ); + assert_eq!(r, transmute(lasx_xvbsrl_v::<15>(black_box(transmute(a))))); + } +} diff --git a/library/stdarch/crates/core_arch/src/loongarch64/lasx/tests.rs b/library/stdarch/crates/core_arch/src/loongarch64/lasx/tests.rs index 54771d7b51109..a4c4a35be0152 100644 --- a/library/stdarch/crates/core_arch/src/loongarch64/lasx/tests.rs +++ b/library/stdarch/crates/core_arch/src/loongarch64/lasx/tests.rs @@ -1,10 +1,11 @@ -// This code is automatically generated. DO NOT MODIFY. +// Auto-generated tests. DO NOT MODIFY. // See crates/stdarch-gen-loongarch/README.md use crate::{ core_arch::{loongarch64::*, simd::*}, mem::transmute, }; +use std::hint::black_box; use stdarch_test::simd_test; #[simd_test(enable = "lasx")] @@ -24,7 +25,13 @@ unsafe fn test_lasx_xvsll_b() { 2882304449461665880, ); - assert_eq!(r, transmute(lasx_xvsll_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsll_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -44,7 +51,13 @@ unsafe fn test_lasx_xvsll_h() { 7061899947028838480, ); - assert_eq!(r, transmute(lasx_xvsll_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsll_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -76,7 +89,13 @@ unsafe fn test_lasx_xvsll_w() { 3598939055443673088, ); - assert_eq!(r, transmute(lasx_xvsll_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsll_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -100,7 +119,13 @@ unsafe fn test_lasx_xvsll_d() { -289787284616642560, ); - assert_eq!(r, transmute(lasx_xvsll_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsll_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -116,7 +141,7 @@ unsafe fn test_lasx_xvslli_b() { 5775955139904200724, ); - assert_eq!(r, transmute(lasx_xvslli_b::<2>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslli_b::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -132,7 +157,7 @@ unsafe fn test_lasx_xvslli_h() { -9223160928474759168, ); - assert_eq!(r, transmute(lasx_xvslli_h::<14>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslli_h::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -154,7 +179,7 @@ unsafe fn test_lasx_xvslli_w() { -1585267064908546048, ); - assert_eq!(r, transmute(lasx_xvslli_w::<24>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslli_w::<24>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -172,7 +197,7 @@ unsafe fn test_lasx_xvslli_d() { -2305843009213693952, ); - assert_eq!(r, transmute(lasx_xvslli_d::<61>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslli_d::<61>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -192,7 +217,13 @@ unsafe fn test_lasx_xvsra_b() { -505532365968836077, ); - assert_eq!(r, transmute(lasx_xvsra_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsra_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -212,7 +243,13 @@ unsafe fn test_lasx_xvsra_h() { 8725659825471543, ); - assert_eq!(r, transmute(lasx_xvsra_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsra_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -244,7 +281,13 @@ unsafe fn test_lasx_xvsra_w() { -36696200575105, ); - assert_eq!(r, transmute(lasx_xvsra_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsra_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -263,7 +306,13 @@ unsafe fn test_lasx_xvsra_d() { ); let r = i64x4::new(1, -129761412875, -1, 8464978396185); - assert_eq!(r, transmute(lasx_xvsra_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsra_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -279,7 +328,7 @@ unsafe fn test_lasx_xvsrai_b() { -218421283493247239, ); - assert_eq!(r, transmute(lasx_xvsrai_b::<4>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrai_b::<4>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -290,7 +339,7 @@ unsafe fn test_lasx_xvsrai_h() { ); let r = i64x4::new(-281474976710658, 8589803520, -4295098367, 562941363552256); - assert_eq!(r, transmute(lasx_xvsrai_h::<14>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrai_h::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -307,7 +356,7 @@ unsafe fn test_lasx_xvsrai_w() { ); let r = i64x4::new(68719476730, -16, 17179869169, -25769803773); - assert_eq!(r, transmute(lasx_xvsrai_w::<27>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrai_w::<27>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -320,7 +369,7 @@ unsafe fn test_lasx_xvsrai_d() { ); let r = i64x4::new(-2, 2, -6, -8); - assert_eq!(r, transmute(lasx_xvsrai_d::<60>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrai_d::<60>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -340,7 +389,13 @@ unsafe fn test_lasx_xvsrar_b() { 302862676776648704, ); - assert_eq!(r, transmute(lasx_xvsrar_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrar_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -360,7 +415,13 @@ unsafe fn test_lasx_xvsrar_h() { -2251658079567874, ); - assert_eq!(r, transmute(lasx_xvsrar_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrar_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -392,7 +453,13 @@ unsafe fn test_lasx_xvsrar_w() { -1668156707832192, ); - assert_eq!(r, transmute(lasx_xvsrar_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrar_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -411,7 +478,13 @@ unsafe fn test_lasx_xvsrar_d() { ); let r = i64x4::new(19951225, 505, -1907248091287715676, 362); - assert_eq!(r, transmute(lasx_xvsrar_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrar_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -427,7 +500,7 @@ unsafe fn test_lasx_xvsrari_b() { 790117907428411639, ); - assert_eq!(r, transmute(lasx_xvsrari_b::<3>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrari_b::<3>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -443,7 +516,7 @@ unsafe fn test_lasx_xvsrari_h() { -24488623625338826, ); - assert_eq!(r, transmute(lasx_xvsrari_h::<8>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrari_h::<8>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -460,7 +533,7 @@ unsafe fn test_lasx_xvsrari_w() { ); let r = i64x4::new(-1, 4294967294, -2, -1); - assert_eq!(r, transmute(lasx_xvsrari_w::<29>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrari_w::<29>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -473,7 +546,7 @@ unsafe fn test_lasx_xvsrari_d() { ); let r = i64x4::new(-3228, 4782, -4328, -2120); - assert_eq!(r, transmute(lasx_xvsrari_d::<50>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrari_d::<50>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -493,7 +566,13 @@ unsafe fn test_lasx_xvsrl_b() { 3996105849293766692, ); - assert_eq!(r, transmute(lasx_xvsrl_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrl_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -513,7 +592,13 @@ unsafe fn test_lasx_xvsrl_h() { 12385032119328029, ); - assert_eq!(r, transmute(lasx_xvsrl_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrl_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -540,7 +625,13 @@ unsafe fn test_lasx_xvsrl_w() { ); let r = i64x4::new(3152506611213, 910538585043, 150899, 25769803779); - assert_eq!(r, transmute(lasx_xvsrl_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrl_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -559,7 +650,13 @@ unsafe fn test_lasx_xvsrl_d() { ); let r = i64x4::new(22, 8215, 774027732, 338970735904462); - assert_eq!(r, transmute(lasx_xvsrl_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrl_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -575,7 +672,7 @@ unsafe fn test_lasx_xvsrli_b() { 3694315145030590091, ); - assert_eq!(r, transmute(lasx_xvsrli_b::<0>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrli_b::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -586,7 +683,7 @@ unsafe fn test_lasx_xvsrli_h() { ); let r = i64x4::new(7036883009470493, 73014771737, 38655688722, 3096241924866048); - assert_eq!(r, transmute(lasx_xvsrli_h::<11>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrli_h::<11>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -608,7 +705,7 @@ unsafe fn test_lasx_xvsrli_w() { 11669426172998, ); - assert_eq!(r, transmute(lasx_xvsrli_w::<17>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrli_w::<17>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -621,7 +718,7 @@ unsafe fn test_lasx_xvsrli_d() { ); let r = i64x4::new(16617962184, 1898365962, 5054169972, 27969530398); - assert_eq!(r, transmute(lasx_xvsrli_d::<29>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrli_d::<29>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -641,7 +738,13 @@ unsafe fn test_lasx_xvsrlr_b() { 150872911094481483, ); - assert_eq!(r, transmute(lasx_xvsrlr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrlr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -661,7 +764,13 @@ unsafe fn test_lasx_xvsrlr_h() { 565118914199555, ); - assert_eq!(r, transmute(lasx_xvsrlr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrlr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -693,7 +802,13 @@ unsafe fn test_lasx_xvsrlr_w() { 7085854838990307330, ); - assert_eq!(r, transmute(lasx_xvsrlr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrlr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -712,7 +827,13 @@ unsafe fn test_lasx_xvsrlr_d() { ); let r = i64x4::new(1801, 481878, 1923591164085, 6280495597); - assert_eq!(r, transmute(lasx_xvsrlr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrlr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -728,7 +849,7 @@ unsafe fn test_lasx_xvsrlri_b() { 2893318883870770962, ); - assert_eq!(r, transmute(lasx_xvsrlri_b::<2>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrlri_b::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -744,7 +865,7 @@ unsafe fn test_lasx_xvsrlri_h() { 32932658182619167, ); - assert_eq!(r, transmute(lasx_xvsrlri_h::<9>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrlri_h::<9>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -761,7 +882,7 @@ unsafe fn test_lasx_xvsrlri_w() { ); let r = i64x4::new(8589934592, 8589934594, 4294967296, 8589934593); - assert_eq!(r, transmute(lasx_xvsrlri_w::<31>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrlri_w::<31>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -779,7 +900,7 @@ unsafe fn test_lasx_xvsrlri_d() { 197693428197319479, ); - assert_eq!(r, transmute(lasx_xvsrlri_d::<6>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrlri_d::<6>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -799,7 +920,13 @@ unsafe fn test_lasx_xvbitclr_b() { 2031321085346416701, ); - assert_eq!(r, transmute(lasx_xvbitclr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitclr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -819,7 +946,13 @@ unsafe fn test_lasx_xvbitclr_h() { -8417099780160452424, ); - assert_eq!(r, transmute(lasx_xvbitclr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitclr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -839,7 +972,13 @@ unsafe fn test_lasx_xvbitclr_w() { 436221668492520778, ); - assert_eq!(r, transmute(lasx_xvbitclr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitclr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -863,7 +1002,13 @@ unsafe fn test_lasx_xvbitclr_d() { 3668272799860684125, ); - assert_eq!(r, transmute(lasx_xvbitclr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitclr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -879,7 +1024,7 @@ unsafe fn test_lasx_xvbitclri_b() { 3065582154070828979, ); - assert_eq!(r, transmute(lasx_xvbitclri_b::<6>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvbitclri_b::<6>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -895,7 +1040,7 @@ unsafe fn test_lasx_xvbitclri_h() { 7727381349517352021, ); - assert_eq!(r, transmute(lasx_xvbitclri_h::<1>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvbitclri_h::<1>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -911,7 +1056,10 @@ unsafe fn test_lasx_xvbitclri_w() { -5611395396043530126, ); - assert_eq!(r, transmute(lasx_xvbitclri_w::<30>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitclri_w::<30>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -929,7 +1077,10 @@ unsafe fn test_lasx_xvbitclri_d() { -63139220754952887, ); - assert_eq!(r, transmute(lasx_xvbitclri_d::<46>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitclri_d::<46>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -949,7 +1100,13 @@ unsafe fn test_lasx_xvbitset_b() { -7702318388235109826, ); - assert_eq!(r, transmute(lasx_xvbitset_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitset_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -969,7 +1126,13 @@ unsafe fn test_lasx_xvbitset_h() { 1674099372676878223, ); - assert_eq!(r, transmute(lasx_xvbitset_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitset_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -989,7 +1152,13 @@ unsafe fn test_lasx_xvbitset_w() { -4953617511697867204, ); - assert_eq!(r, transmute(lasx_xvbitset_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitset_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1013,7 +1182,13 @@ unsafe fn test_lasx_xvbitset_d() { 8641001130845153939, ); - assert_eq!(r, transmute(lasx_xvbitset_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitset_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1029,7 +1204,7 @@ unsafe fn test_lasx_xvbitseti_b() { -3539275497407339017, ); - assert_eq!(r, transmute(lasx_xvbitseti_b::<7>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvbitseti_b::<7>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1045,7 +1220,10 @@ unsafe fn test_lasx_xvbitseti_h() { -1050847327214912781, ); - assert_eq!(r, transmute(lasx_xvbitseti_h::<13>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitseti_h::<13>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -1061,7 +1239,10 @@ unsafe fn test_lasx_xvbitseti_w() { -1933536090599238411, ); - assert_eq!(r, transmute(lasx_xvbitseti_w::<29>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitseti_w::<29>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -1079,7 +1260,10 @@ unsafe fn test_lasx_xvbitseti_d() { 7640056937583456779, ); - assert_eq!(r, transmute(lasx_xvbitseti_d::<17>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitseti_d::<17>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -1099,7 +1283,13 @@ unsafe fn test_lasx_xvbitrev_b() { 8353346322052154032, ); - assert_eq!(r, transmute(lasx_xvbitrev_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitrev_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1119,7 +1309,13 @@ unsafe fn test_lasx_xvbitrev_h() { 1161012008856358603, ); - assert_eq!(r, transmute(lasx_xvbitrev_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitrev_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1139,7 +1335,13 @@ unsafe fn test_lasx_xvbitrev_w() { 2239715596821320928, ); - assert_eq!(r, transmute(lasx_xvbitrev_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitrev_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1163,7 +1365,13 @@ unsafe fn test_lasx_xvbitrev_d() { -7824300689033275105, ); - assert_eq!(r, transmute(lasx_xvbitrev_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitrev_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1179,7 +1387,7 @@ unsafe fn test_lasx_xvbitrevi_b() { -468434338938596352, ); - assert_eq!(r, transmute(lasx_xvbitrevi_b::<5>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvbitrevi_b::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1195,7 +1403,10 @@ unsafe fn test_lasx_xvbitrevi_h() { 4180481285432101679, ); - assert_eq!(r, transmute(lasx_xvbitrevi_h::<11>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitrevi_h::<11>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -1211,7 +1422,10 @@ unsafe fn test_lasx_xvbitrevi_w() { -7201777846932221130, ); - assert_eq!(r, transmute(lasx_xvbitrevi_w::<30>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitrevi_w::<30>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -1229,7 +1443,10 @@ unsafe fn test_lasx_xvbitrevi_d() { -1340750007927221124, ); - assert_eq!(r, transmute(lasx_xvbitrevi_d::<25>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitrevi_d::<25>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -1249,7 +1466,13 @@ unsafe fn test_lasx_xvadd_b() { 39834845715162790, ); - assert_eq!(r, transmute(lasx_xvadd_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadd_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1269,7 +1492,13 @@ unsafe fn test_lasx_xvadd_h() { 3485514723534807729, ); - assert_eq!(r, transmute(lasx_xvadd_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadd_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1301,7 +1530,13 @@ unsafe fn test_lasx_xvadd_w() { 449408456544649458, ); - assert_eq!(r, transmute(lasx_xvadd_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadd_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1325,7 +1560,13 @@ unsafe fn test_lasx_xvadd_d() { -3333036084724254699, ); - assert_eq!(r, transmute(lasx_xvadd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadd_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1341,7 +1582,7 @@ unsafe fn test_lasx_xvaddi_bu() { 1765491911008659808, ); - assert_eq!(r, transmute(lasx_xvaddi_bu::<3>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvaddi_bu::<3>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1357,7 +1598,7 @@ unsafe fn test_lasx_xvaddi_hu() { 4257614802810591100, ); - assert_eq!(r, transmute(lasx_xvaddi_hu::<1>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvaddi_hu::<1>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1379,7 +1620,7 @@ unsafe fn test_lasx_xvaddi_wu() { 8831113348648816385, ); - assert_eq!(r, transmute(lasx_xvaddi_wu::<18>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvaddi_wu::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1397,7 +1638,7 @@ unsafe fn test_lasx_xvaddi_du() { -4546559236496052074, ); - assert_eq!(r, transmute(lasx_xvaddi_du::<24>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvaddi_du::<24>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1417,7 +1658,13 @@ unsafe fn test_lasx_xvsub_b() { -7947080804470620196, ); - assert_eq!(r, transmute(lasx_xvsub_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsub_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1437,7 +1684,13 @@ unsafe fn test_lasx_xvsub_h() { -2694318201466204009, ); - assert_eq!(r, transmute(lasx_xvsub_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsub_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1469,7 +1722,13 @@ unsafe fn test_lasx_xvsub_w() { -4928352995773315889, ); - assert_eq!(r, transmute(lasx_xvsub_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsub_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1493,7 +1752,13 @@ unsafe fn test_lasx_xvsub_d() { -1297126209654251318, ); - assert_eq!(r, transmute(lasx_xvsub_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsub_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1509,7 +1774,7 @@ unsafe fn test_lasx_xvsubi_bu() { 6185872108420092159, ); - assert_eq!(r, transmute(lasx_xvsubi_bu::<13>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsubi_bu::<13>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1525,7 +1790,7 @@ unsafe fn test_lasx_xvsubi_hu() { 1522443898558080492, ); - assert_eq!(r, transmute(lasx_xvsubi_hu::<7>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsubi_hu::<7>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1547,7 +1812,7 @@ unsafe fn test_lasx_xvsubi_wu() { 1285045436848317605, ); - assert_eq!(r, transmute(lasx_xvsubi_wu::<26>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsubi_wu::<26>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1565,7 +1830,7 @@ unsafe fn test_lasx_xvsubi_du() { 4145748346670499010, ); - assert_eq!(r, transmute(lasx_xvsubi_du::<12>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsubi_du::<12>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1585,7 +1850,13 @@ unsafe fn test_lasx_xvmax_b() { 8535488153625188193, ); - assert_eq!(r, transmute(lasx_xvmax_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1605,7 +1876,13 @@ unsafe fn test_lasx_xvmax_h() { -4332902052436023459, ); - assert_eq!(r, transmute(lasx_xvmax_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1637,7 +1914,13 @@ unsafe fn test_lasx_xvmax_w() { 6702174376295843649, ); - assert_eq!(r, transmute(lasx_xvmax_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1661,7 +1944,13 @@ unsafe fn test_lasx_xvmax_d() { -880822478913123851, ); - assert_eq!(r, transmute(lasx_xvmax_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1677,7 +1966,7 @@ unsafe fn test_lasx_xvmaxi_b() { 5914634738497113077, ); - assert_eq!(r, transmute(lasx_xvmaxi_b::<-11>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_b::<-11>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1693,7 +1982,7 @@ unsafe fn test_lasx_xvmaxi_h() { 4406209242478280693, ); - assert_eq!(r, transmute(lasx_xvmaxi_h::<-11>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_h::<-11>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1715,7 +2004,7 @@ unsafe fn test_lasx_xvmaxi_w() { 22981864337, ); - assert_eq!(r, transmute(lasx_xvmaxi_w::<5>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_w::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1733,7 +2022,7 @@ unsafe fn test_lasx_xvmaxi_d() { 2429249725865673045, ); - assert_eq!(r, transmute(lasx_xvmaxi_d::<-3>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_d::<-3>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1753,7 +2042,13 @@ unsafe fn test_lasx_xvmax_bu() { 4233495576175936231, ); - assert_eq!(r, transmute(lasx_xvmax_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1773,7 +2068,13 @@ unsafe fn test_lasx_xvmax_hu() { -1573457187787184228, ); - assert_eq!(r, transmute(lasx_xvmax_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1793,7 +2094,13 @@ unsafe fn test_lasx_xvmax_wu() { -7315994376096540525, ); - assert_eq!(r, transmute(lasx_xvmax_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1817,7 +2124,13 @@ unsafe fn test_lasx_xvmax_du() { 5141420152487342561, ); - assert_eq!(r, transmute(lasx_xvmax_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1833,7 +2146,7 @@ unsafe fn test_lasx_xvmaxi_bu() { -8478920119441971628, ); - assert_eq!(r, transmute(lasx_xvmaxi_bu::<10>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_bu::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1849,7 +2162,7 @@ unsafe fn test_lasx_xvmaxi_hu() { 2580949584734723198, ); - assert_eq!(r, transmute(lasx_xvmaxi_hu::<15>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_hu::<15>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1865,7 +2178,7 @@ unsafe fn test_lasx_xvmaxi_wu() { 6328395255824707620, ); - assert_eq!(r, transmute(lasx_xvmaxi_wu::<12>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_wu::<12>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1883,7 +2196,7 @@ unsafe fn test_lasx_xvmaxi_du() { 3280369825537805033, ); - assert_eq!(r, transmute(lasx_xvmaxi_du::<18>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_du::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1903,7 +2216,13 @@ unsafe fn test_lasx_xvmin_b() { -433018640497265418, ); - assert_eq!(r, transmute(lasx_xvmin_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1923,7 +2242,13 @@ unsafe fn test_lasx_xvmin_h() { -1753422264687927210, ); - assert_eq!(r, transmute(lasx_xvmin_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1949,7 +2274,13 @@ unsafe fn test_lasx_xvmin_w() { -710046880263550629, ); - assert_eq!(r, transmute(lasx_xvmin_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1973,7 +2304,13 @@ unsafe fn test_lasx_xvmin_d() { -3792381296290037631, ); - assert_eq!(r, transmute(lasx_xvmin_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1989,7 +2326,7 @@ unsafe fn test_lasx_xvmini_b() { -1088282380739546975, ); - assert_eq!(r, transmute(lasx_xvmini_b::<-16>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_b::<-16>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2005,7 +2342,7 @@ unsafe fn test_lasx_xvmini_h() { 2439077560844296, ); - assert_eq!(r, transmute(lasx_xvmini_h::<8>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_h::<8>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2027,7 +2364,7 @@ unsafe fn test_lasx_xvmini_w() { -3162971646443594334, ); - assert_eq!(r, transmute(lasx_xvmini_w::<-16>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_w::<-16>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2040,7 +2377,7 @@ unsafe fn test_lasx_xvmini_d() { ); let r = i64x4::new(-8, -8, -8, -8); - assert_eq!(r, transmute(lasx_xvmini_d::<-8>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_d::<-8>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2060,7 +2397,13 @@ unsafe fn test_lasx_xvmin_bu() { 481055128827070653, ); - assert_eq!(r, transmute(lasx_xvmin_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2080,7 +2423,13 @@ unsafe fn test_lasx_xvmin_hu() { 4690886800975071114, ); - assert_eq!(r, transmute(lasx_xvmin_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2100,7 +2449,13 @@ unsafe fn test_lasx_xvmin_wu() { 841320412252129092, ); - assert_eq!(r, transmute(lasx_xvmin_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2124,7 +2479,13 @@ unsafe fn test_lasx_xvmin_du() { 168959420679376173, ); - assert_eq!(r, transmute(lasx_xvmin_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2140,7 +2501,7 @@ unsafe fn test_lasx_xvmini_bu() { 1803156197610166553, ); - assert_eq!(r, transmute(lasx_xvmini_bu::<25>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_bu::<25>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2156,7 +2517,7 @@ unsafe fn test_lasx_xvmini_hu() { 7881419608817692, ); - assert_eq!(r, transmute(lasx_xvmini_hu::<28>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_hu::<28>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2167,7 +2528,7 @@ unsafe fn test_lasx_xvmini_wu() { ); let r = i64x4::new(94489280534, 94489280534, 94489280534, 94489280534); - assert_eq!(r, transmute(lasx_xvmini_wu::<22>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_wu::<22>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2180,7 +2541,7 @@ unsafe fn test_lasx_xvmini_du() { ); let r = i64x4::new(18, 18, 18, 18); - assert_eq!(r, transmute(lasx_xvmini_du::<18>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_du::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2195,7 +2556,13 @@ unsafe fn test_lasx_xvseq_b() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseq_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvseq_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2210,7 +2577,13 @@ unsafe fn test_lasx_xvseq_h() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseq_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvseq_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2237,7 +2610,13 @@ unsafe fn test_lasx_xvseq_w() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseq_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvseq_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2256,7 +2635,13 @@ unsafe fn test_lasx_xvseq_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvseq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2267,7 +2652,7 @@ unsafe fn test_lasx_xvseqi_b() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseqi_b::<-14>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvseqi_b::<-14>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2278,7 +2663,7 @@ unsafe fn test_lasx_xvseqi_h() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseqi_h::<-8>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvseqi_h::<-8>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2295,7 +2680,7 @@ unsafe fn test_lasx_xvseqi_w() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseqi_w::<-11>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvseqi_w::<-11>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2308,7 +2693,7 @@ unsafe fn test_lasx_xvseqi_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseqi_d::<-2>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvseqi_d::<-2>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2328,7 +2713,13 @@ unsafe fn test_lasx_xvslt_b() { 71776119077994495, ); - assert_eq!(r, transmute(lasx_xvslt_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2348,7 +2739,13 @@ unsafe fn test_lasx_xvslt_h() { -281470681743361, ); - assert_eq!(r, transmute(lasx_xvslt_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2375,7 +2772,13 @@ unsafe fn test_lasx_xvslt_w() { ); let r = i64x4::new(4294967295, 0, -1, 0); - assert_eq!(r, transmute(lasx_xvslt_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2394,7 +2797,13 @@ unsafe fn test_lasx_xvslt_d() { ); let r = i64x4::new(0, 0, -1, 0); - assert_eq!(r, transmute(lasx_xvslt_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2410,7 +2819,7 @@ unsafe fn test_lasx_xvslti_b() { 71777218556067840, ); - assert_eq!(r, transmute(lasx_xvslti_b::<-16>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_b::<-16>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2421,7 +2830,7 @@ unsafe fn test_lasx_xvslti_h() { ); let r = i64x4::new(4294967295, -1, -281470681743361, 65535); - assert_eq!(r, transmute(lasx_xvslti_h::<-4>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_h::<-4>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2438,7 +2847,7 @@ unsafe fn test_lasx_xvslti_w() { ); let r = i64x4::new(-1, 0, -4294967296, -1); - assert_eq!(r, transmute(lasx_xvslti_w::<-4>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_w::<-4>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2451,7 +2860,7 @@ unsafe fn test_lasx_xvslti_d() { ); let r = i64x4::new(-1, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslti_d::<1>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_d::<1>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2466,7 +2875,13 @@ unsafe fn test_lasx_xvslt_bu() { ); let r = i64x4::new(-1095216660481, 280375465083135, -1099494915841, 16711680); - assert_eq!(r, transmute(lasx_xvslt_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2481,7 +2896,13 @@ unsafe fn test_lasx_xvslt_hu() { ); let r = i64x4::new(-281470681808896, 4294901760, -65536, 281470681808895); - assert_eq!(r, transmute(lasx_xvslt_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2496,7 +2917,13 @@ unsafe fn test_lasx_xvslt_wu() { ); let r = i64x4::new(-1, -1, -4294967296, -1); - assert_eq!(r, transmute(lasx_xvslt_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2515,7 +2942,13 @@ unsafe fn test_lasx_xvslt_du() { ); let r = i64x4::new(-1, -1, 0, -1); - assert_eq!(r, transmute(lasx_xvslt_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2526,7 +2959,7 @@ unsafe fn test_lasx_xvslti_bu() { ); let r = i64x4::new(16711680, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslti_bu::<7>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_bu::<7>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2537,7 +2970,7 @@ unsafe fn test_lasx_xvslti_hu() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslti_hu::<13>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_hu::<13>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2548,7 +2981,7 @@ unsafe fn test_lasx_xvslti_wu() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslti_wu::<8>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_wu::<8>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2561,7 +2994,7 @@ unsafe fn test_lasx_xvslti_du() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslti_du::<2>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_du::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2581,7 +3014,13 @@ unsafe fn test_lasx_xvsle_b() { 1095216726015, ); - assert_eq!(r, transmute(lasx_xvsle_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2596,7 +3035,13 @@ unsafe fn test_lasx_xvsle_h() { ); let r = i64x4::new(-1, 4294901760, 4294901760, -281470681743361); - assert_eq!(r, transmute(lasx_xvsle_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2623,7 +3068,13 @@ unsafe fn test_lasx_xvsle_w() { ); let r = i64x4::new(-4294967296, 0, -1, -4294967296); - assert_eq!(r, transmute(lasx_xvsle_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2642,7 +3093,13 @@ unsafe fn test_lasx_xvsle_d() { ); let r = i64x4::new(-1, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvsle_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2658,7 +3115,7 @@ unsafe fn test_lasx_xvslei_b() { 280375465148415, ); - assert_eq!(r, transmute(lasx_xvslei_b::<-14>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_b::<-14>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2669,7 +3126,7 @@ unsafe fn test_lasx_xvslei_h() { ); let r = i64x4::new(-65536, -4294901761, 281474976710655, -65536); - assert_eq!(r, transmute(lasx_xvslei_h::<-15>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_h::<-15>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2680,7 +3137,7 @@ unsafe fn test_lasx_xvslei_w() { ); let r = i64x4::new(-4294967296, 0, -1, 0); - assert_eq!(r, transmute(lasx_xvslei_w::<-3>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_w::<-3>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2693,7 +3150,7 @@ unsafe fn test_lasx_xvslei_d() { ); let r = i64x4::new(-1, 0, -1, -1); - assert_eq!(r, transmute(lasx_xvslei_d::<6>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_d::<6>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2713,7 +3170,13 @@ unsafe fn test_lasx_xvsle_bu() { 281474976710655, ); - assert_eq!(r, transmute(lasx_xvsle_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2728,7 +3191,13 @@ unsafe fn test_lasx_xvsle_hu() { ); let r = i64x4::new(281474976645120, -4294967296, 281470681808895, 0); - assert_eq!(r, transmute(lasx_xvsle_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2743,7 +3212,13 @@ unsafe fn test_lasx_xvsle_wu() { ); let r = i64x4::new(-4294967296, -1, 0, 0); - assert_eq!(r, transmute(lasx_xvsle_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2762,7 +3237,13 @@ unsafe fn test_lasx_xvsle_du() { ); let r = i64x4::new(0, -1, 0, -1); - assert_eq!(r, transmute(lasx_xvsle_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2773,7 +3254,7 @@ unsafe fn test_lasx_xvslei_bu() { ); let r = i64x4::new(72056494526365440, 280375465082880, 71776119077928960, 0); - assert_eq!(r, transmute(lasx_xvslei_bu::<29>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_bu::<29>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2784,7 +3265,7 @@ unsafe fn test_lasx_xvslei_hu() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslei_hu::<30>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_hu::<30>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2795,7 +3276,7 @@ unsafe fn test_lasx_xvslei_wu() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslei_wu::<31>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_wu::<31>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2808,7 +3289,7 @@ unsafe fn test_lasx_xvslei_du() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslei_du::<5>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_du::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2824,7 +3305,7 @@ unsafe fn test_lasx_xvsat_b() { 1985954429852520914, ); - assert_eq!(r, transmute(lasx_xvsat_b::<7>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_b::<7>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2840,7 +3321,7 @@ unsafe fn test_lasx_xvsat_h() { 1152903912689234618, ); - assert_eq!(r, transmute(lasx_xvsat_h::<12>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_h::<12>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2857,7 +3338,7 @@ unsafe fn test_lasx_xvsat_w() { ); let r = i64x4::new(-34359738361, 34359738360, -30064771080, -34359738361); - assert_eq!(r, transmute(lasx_xvsat_w::<3>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_w::<3>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2875,7 +3356,7 @@ unsafe fn test_lasx_xvsat_d() { 6102033771404793023, ); - assert_eq!(r, transmute(lasx_xvsat_d::<63>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_d::<63>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2891,7 +3372,7 @@ unsafe fn test_lasx_xvsat_bu() { 2539795165049929535, ); - assert_eq!(r, transmute(lasx_xvsat_bu::<5>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_bu::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2907,7 +3388,7 @@ unsafe fn test_lasx_xvsat_hu() { 1970354902204423, ); - assert_eq!(r, transmute(lasx_xvsat_hu::<2>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_hu::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2918,7 +3399,7 @@ unsafe fn test_lasx_xvsat_wu() { ); let r = i64x4::new(270582939711, 270582939711, 270582939711, 270582939711); - assert_eq!(r, transmute(lasx_xvsat_wu::<5>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_wu::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2931,7 +3412,7 @@ unsafe fn test_lasx_xvsat_du() { ); let r = i64x4::new(8796093022207, 8796093022207, 8796093022207, 8796093022207); - assert_eq!(r, transmute(lasx_xvsat_du::<42>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_du::<42>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2951,7 +3432,13 @@ unsafe fn test_lasx_xvadda_b() { -6512388827583513148, ); - assert_eq!(r, transmute(lasx_xvadda_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadda_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2971,7 +3458,13 @@ unsafe fn test_lasx_xvadda_h() { 4288196905584441792, ); - assert_eq!(r, transmute(lasx_xvadda_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadda_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2997,7 +3490,13 @@ unsafe fn test_lasx_xvadda_w() { 7114837115730115925, ); - assert_eq!(r, transmute(lasx_xvadda_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadda_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3021,7 +3520,13 @@ unsafe fn test_lasx_xvadda_d() { -3532969990801796507, ); - assert_eq!(r, transmute(lasx_xvadda_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadda_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3041,7 +3546,13 @@ unsafe fn test_lasx_xvsadd_b() { 3530119333939728429, ); - assert_eq!(r, transmute(lasx_xvsadd_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3061,7 +3572,13 @@ unsafe fn test_lasx_xvsadd_h() { -5137195089227040637, ); - assert_eq!(r, transmute(lasx_xvsadd_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3093,7 +3610,13 @@ unsafe fn test_lasx_xvsadd_w() { 6493388403303310332, ); - assert_eq!(r, transmute(lasx_xvsadd_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3117,7 +3640,13 @@ unsafe fn test_lasx_xvsadd_d() { -1670245304326307655, ); - assert_eq!(r, transmute(lasx_xvsadd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3137,7 +3666,13 @@ unsafe fn test_lasx_xvsadd_bu() { -380207497217, ); - assert_eq!(r, transmute(lasx_xvsadd_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3157,7 +3692,13 @@ unsafe fn test_lasx_xvsadd_hu() { -2766274561, ); - assert_eq!(r, transmute(lasx_xvsadd_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3177,7 +3718,13 @@ unsafe fn test_lasx_xvsadd_wu() { 9110967605937569791, ); - assert_eq!(r, transmute(lasx_xvsadd_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3196,7 +3743,13 @@ unsafe fn test_lasx_xvsadd_du() { ); let r = i64x4::new(-1, -7683287700352967836, -3264735658191843562, -1); - assert_eq!(r, transmute(lasx_xvsadd_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3216,7 +3769,13 @@ unsafe fn test_lasx_xvavg_b() { -2451086284962613015, ); - assert_eq!(r, transmute(lasx_xvavg_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3236,7 +3795,13 @@ unsafe fn test_lasx_xvavg_h() { -6082277202109387491, ); - assert_eq!(r, transmute(lasx_xvavg_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3268,7 +3833,13 @@ unsafe fn test_lasx_xvavg_w() { -97541447405991454, ); - assert_eq!(r, transmute(lasx_xvavg_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3292,7 +3863,13 @@ unsafe fn test_lasx_xvavg_d() { 743619511763122382, ); - assert_eq!(r, transmute(lasx_xvavg_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3312,7 +3889,13 @@ unsafe fn test_lasx_xvavg_bu() { 5794025379951354001, ); - assert_eq!(r, transmute(lasx_xvavg_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3332,7 +3915,13 @@ unsafe fn test_lasx_xvavg_hu() { -3939723307751543404, ); - assert_eq!(r, transmute(lasx_xvavg_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3351,7 +3940,13 @@ unsafe fn test_lasx_xvavg_wu() { 6180173283312674740, ); - assert_eq!(r, transmute(lasx_xvavg_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3375,7 +3970,13 @@ unsafe fn test_lasx_xvavg_du() { -9048945872629561085, ); - assert_eq!(r, transmute(lasx_xvavg_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3395,7 +3996,13 @@ unsafe fn test_lasx_xvavgr_b() { -1577916506278329386, ); - assert_eq!(r, transmute(lasx_xvavgr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3415,7 +4022,13 @@ unsafe fn test_lasx_xvavgr_h() { 1044782302812228671, ); - assert_eq!(r, transmute(lasx_xvavgr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3447,7 +4060,13 @@ unsafe fn test_lasx_xvavgr_w() { 4983380877656540978, ); - assert_eq!(r, transmute(lasx_xvavgr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3471,7 +4090,13 @@ unsafe fn test_lasx_xvavgr_d() { 229317404291257478, ); - assert_eq!(r, transmute(lasx_xvavgr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3491,7 +4116,13 @@ unsafe fn test_lasx_xvavgr_bu() { 8511681618342279077, ); - assert_eq!(r, transmute(lasx_xvavgr_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3511,7 +4142,13 @@ unsafe fn test_lasx_xvavgr_hu() { -4835281559523879916, ); - assert_eq!(r, transmute(lasx_xvavgr_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3531,7 +4168,13 @@ unsafe fn test_lasx_xvavgr_wu() { 2489338192049926342, ); - assert_eq!(r, transmute(lasx_xvavgr_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3555,7 +4198,13 @@ unsafe fn test_lasx_xvavgr_du() { 6414723233875186966, ); - assert_eq!(r, transmute(lasx_xvavgr_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3575,7 +4224,13 @@ unsafe fn test_lasx_xvssub_b() { -4561472970538678093, ); - assert_eq!(r, transmute(lasx_xvssub_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3595,7 +4250,13 @@ unsafe fn test_lasx_xvssub_h() { 8048307602867637285, ); - assert_eq!(r, transmute(lasx_xvssub_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3627,7 +4288,13 @@ unsafe fn test_lasx_xvssub_w() { 4655436811119524629, ); - assert_eq!(r, transmute(lasx_xvssub_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3651,7 +4318,13 @@ unsafe fn test_lasx_xvssub_d() { -9223372036854775808, ); - assert_eq!(r, transmute(lasx_xvssub_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3671,7 +4344,13 @@ unsafe fn test_lasx_xvssub_bu() { 864691185841012929, ); - assert_eq!(r, transmute(lasx_xvssub_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3691,7 +4370,13 @@ unsafe fn test_lasx_xvssub_hu() { 188750927758467, ); - assert_eq!(r, transmute(lasx_xvssub_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3711,7 +4396,13 @@ unsafe fn test_lasx_xvssub_wu() { 3974517532346153551, ); - assert_eq!(r, transmute(lasx_xvssub_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3730,7 +4421,13 @@ unsafe fn test_lasx_xvssub_du() { ); let r = i64x4::new(1075384133325788465, 0, 8236940487074099359, 0); - assert_eq!(r, transmute(lasx_xvssub_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3750,7 +4447,13 @@ unsafe fn test_lasx_xvabsd_b() { 4109603046844106624, ); - assert_eq!(r, transmute(lasx_xvabsd_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3770,7 +4473,13 @@ unsafe fn test_lasx_xvabsd_h() { 5513891007581016946, ); - assert_eq!(r, transmute(lasx_xvabsd_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3802,7 +4511,13 @@ unsafe fn test_lasx_xvabsd_w() { -7014776540975538355, ); - assert_eq!(r, transmute(lasx_xvabsd_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3826,7 +4541,13 @@ unsafe fn test_lasx_xvabsd_d() { 4722306005291245989, ); - assert_eq!(r, transmute(lasx_xvabsd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3846,7 +4567,13 @@ unsafe fn test_lasx_xvabsd_bu() { 1887319547440621943, ); - assert_eq!(r, transmute(lasx_xvabsd_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3866,7 +4593,13 @@ unsafe fn test_lasx_xvabsd_hu() { 1864011964690965056, ); - assert_eq!(r, transmute(lasx_xvabsd_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3886,7 +4619,13 @@ unsafe fn test_lasx_xvabsd_wu() { 1525979489064328670, ); - assert_eq!(r, transmute(lasx_xvabsd_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3910,7 +4649,13 @@ unsafe fn test_lasx_xvabsd_du() { 2127486190004927946, ); - assert_eq!(r, transmute(lasx_xvabsd_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3930,7 +4675,13 @@ unsafe fn test_lasx_xvmul_b() { -9159357540886189840, ); - assert_eq!(r, transmute(lasx_xvmul_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmul_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3950,7 +4701,13 @@ unsafe fn test_lasx_xvmul_h() { -7534790044979024262, ); - assert_eq!(r, transmute(lasx_xvmul_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmul_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3982,7 +4739,13 @@ unsafe fn test_lasx_xvmul_w() { 1142495638330554240, ); - assert_eq!(r, transmute(lasx_xvmul_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmul_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4006,7 +4769,13 @@ unsafe fn test_lasx_xvmul_d() { -3668010491661410128, ); - assert_eq!(r, transmute(lasx_xvmul_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmul_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4032,7 +4801,11 @@ unsafe fn test_lasx_xvmadd_b() { assert_eq!( r, - transmute(lasx_xvmadd_b(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmadd_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4059,7 +4832,11 @@ unsafe fn test_lasx_xvmadd_h() { assert_eq!( r, - transmute(lasx_xvmadd_h(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmadd_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4104,7 +4881,11 @@ unsafe fn test_lasx_xvmadd_w() { assert_eq!( r, - transmute(lasx_xvmadd_w(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmadd_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4137,7 +4918,11 @@ unsafe fn test_lasx_xvmadd_d() { assert_eq!( r, - transmute(lasx_xvmadd_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmadd_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4164,7 +4949,11 @@ unsafe fn test_lasx_xvmsub_b() { assert_eq!( r, - transmute(lasx_xvmsub_b(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmsub_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4191,7 +4980,11 @@ unsafe fn test_lasx_xvmsub_h() { assert_eq!( r, - transmute(lasx_xvmsub_h(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmsub_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4236,7 +5029,11 @@ unsafe fn test_lasx_xvmsub_w() { assert_eq!( r, - transmute(lasx_xvmsub_w(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmsub_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4269,7 +5066,11 @@ unsafe fn test_lasx_xvmsub_d() { assert_eq!( r, - transmute(lasx_xvmsub_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmsub_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4285,7 +5086,13 @@ unsafe fn test_lasx_xvdiv_b() { ); let r = i64x4::new(67174400, 843334041468931, 16515072, 1090921824000); - assert_eq!(r, transmute(lasx_xvdiv_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4305,7 +5112,13 @@ unsafe fn test_lasx_xvdiv_h() { -281470681939967, ); - assert_eq!(r, transmute(lasx_xvdiv_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4332,7 +5145,13 @@ unsafe fn test_lasx_xvdiv_w() { ); let r = i64x4::new(-25769803778, 4294967295, 34359738365, 1); - assert_eq!(r, transmute(lasx_xvdiv_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4351,7 +5170,13 @@ unsafe fn test_lasx_xvdiv_d() { ); let r = i64x4::new(-3, 0, -3, 0); - assert_eq!(r, transmute(lasx_xvdiv_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4371,7 +5196,13 @@ unsafe fn test_lasx_xvdiv_bu() { 144118486677848127, ); - assert_eq!(r, transmute(lasx_xvdiv_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4386,7 +5217,13 @@ unsafe fn test_lasx_xvdiv_hu() { ); let r = i64x4::new(4295098372, 38654705665, 281474976776212, 283467841601537); - assert_eq!(r, transmute(lasx_xvdiv_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4401,7 +5238,13 @@ unsafe fn test_lasx_xvdiv_wu() { ); let r = i64x4::new(0, 1, 46, 4294967299); - assert_eq!(r, transmute(lasx_xvdiv_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4420,7 +5263,13 @@ unsafe fn test_lasx_xvdiv_du() { ); let r = i64x4::new(0, 0, 1, 6); - assert_eq!(r, transmute(lasx_xvdiv_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4440,7 +5289,13 @@ unsafe fn test_lasx_xvhaddw_h_b() { -18859072538017839, ); - assert_eq!(r, transmute(lasx_xvhaddw_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4460,7 +5315,13 @@ unsafe fn test_lasx_xvhaddw_w_h() { -36597416302335, ); - assert_eq!(r, transmute(lasx_xvhaddw_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4487,7 +5348,13 @@ unsafe fn test_lasx_xvhaddw_d_w() { ); let r = i64x4::new(1043954543, 64421064, -1003667433, -119821715); - assert_eq!(r, transmute(lasx_xvhaddw_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4507,7 +5374,13 @@ unsafe fn test_lasx_xvhaddw_hu_bu() { 56014362196705476, ); - assert_eq!(r, transmute(lasx_xvhaddw_hu_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_hu_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4527,7 +5400,13 @@ unsafe fn test_lasx_xvhaddw_wu_hu() { 392255068231306, ); - assert_eq!(r, transmute(lasx_xvhaddw_wu_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_wu_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4542,7 +5421,13 @@ unsafe fn test_lasx_xvhaddw_du_wu() { ); let r = i64x4::new(2983569336, 4514288382, 2479696956, 1680431840); - assert_eq!(r, transmute(lasx_xvhaddw_du_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_du_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4562,7 +5447,13 @@ unsafe fn test_lasx_xvhsubw_h_b() { -21955597927907350, ); - assert_eq!(r, transmute(lasx_xvhsubw_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4582,7 +5473,13 @@ unsafe fn test_lasx_xvhsubw_w_h() { -108800111503156, ); - assert_eq!(r, transmute(lasx_xvhsubw_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4603,7 +5500,13 @@ unsafe fn test_lasx_xvhsubw_d_w() { ); let r = i64x4::new(2748898148, -45146293, 958916832, 1285325893); - assert_eq!(r, transmute(lasx_xvhsubw_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4623,7 +5526,13 @@ unsafe fn test_lasx_xvhsubw_hu_bu() { 9289103727198239, ); - assert_eq!(r, transmute(lasx_xvhsubw_hu_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_hu_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4643,7 +5552,13 @@ unsafe fn test_lasx_xvhsubw_wu_hu() { 32018981198856, ); - assert_eq!(r, transmute(lasx_xvhsubw_wu_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_wu_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4658,7 +5573,13 @@ unsafe fn test_lasx_xvhsubw_du_wu() { ); let r = i64x4::new(-1056733131, -2613149992, 384615677, -1588276541); - assert_eq!(r, transmute(lasx_xvhsubw_du_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_du_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4678,7 +5599,13 @@ unsafe fn test_lasx_xvmod_b() { -48385121157714142, ); - assert_eq!(r, transmute(lasx_xvmod_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmod_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4698,7 +5625,13 @@ unsafe fn test_lasx_xvmod_h() { -194216204870745003, ); - assert_eq!(r, transmute(lasx_xvmod_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmod_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4724,7 +5657,13 @@ unsafe fn test_lasx_xvmod_w() { 807808928635455307, ); - assert_eq!(r, transmute(lasx_xvmod_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmod_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4748,7 +5687,13 @@ unsafe fn test_lasx_xvmod_d() { -3048989907394276239, ); - assert_eq!(r, transmute(lasx_xvmod_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmod_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4768,7 +5713,13 @@ unsafe fn test_lasx_xvmod_bu() { 5417620637589803790, ); - assert_eq!(r, transmute(lasx_xvmod_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmod_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4788,7 +5739,13 @@ unsafe fn test_lasx_xvmod_hu() { 129490854556368167, ); - assert_eq!(r, transmute(lasx_xvmod_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmod_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4808,7 +5765,13 @@ unsafe fn test_lasx_xvmod_wu() { 480682694340619302, ); - assert_eq!(r, transmute(lasx_xvmod_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmod_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4832,7 +5795,13 @@ unsafe fn test_lasx_xvmod_du() { 150087784552479859, ); - assert_eq!(r, transmute(lasx_xvmod_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmod_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4848,7 +5817,10 @@ unsafe fn test_lasx_xvrepl128vei_b() { 8970181431921507452, ); - assert_eq!(r, transmute(lasx_xvrepl128vei_b::<8>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvrepl128vei_b::<8>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -4864,7 +5836,10 @@ unsafe fn test_lasx_xvrepl128vei_h() { -3904680457625679409, ); - assert_eq!(r, transmute(lasx_xvrepl128vei_h::<3>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvrepl128vei_h::<3>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -4886,7 +5861,10 @@ unsafe fn test_lasx_xvrepl128vei_w() { -1327396365108239351, ); - assert_eq!(r, transmute(lasx_xvrepl128vei_w::<1>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvrepl128vei_w::<1>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -4904,7 +5882,10 @@ unsafe fn test_lasx_xvrepl128vei_d() { 4427502889722976813, ); - assert_eq!(r, transmute(lasx_xvrepl128vei_d::<0>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvrepl128vei_d::<0>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -4924,7 +5905,13 @@ unsafe fn test_lasx_xvpickev_b() { 4502896606534087725, ); - assert_eq!(r, transmute(lasx_xvpickev_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickev_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4944,7 +5931,13 @@ unsafe fn test_lasx_xvpickev_h() { -2117051360895385090, ); - assert_eq!(r, transmute(lasx_xvpickev_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickev_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4976,7 +5969,13 @@ unsafe fn test_lasx_xvpickev_w() { -4454806063744691677, ); - assert_eq!(r, transmute(lasx_xvpickev_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickev_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5000,7 +5999,13 @@ unsafe fn test_lasx_xvpickev_d() { 1952973857169882715, ); - assert_eq!(r, transmute(lasx_xvpickev_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickev_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5020,7 +6025,13 @@ unsafe fn test_lasx_xvpickod_b() { 4092165317489988560, ); - assert_eq!(r, transmute(lasx_xvpickod_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickod_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5040,7 +6051,13 @@ unsafe fn test_lasx_xvpickod_h() { 5912677724127371711, ); - assert_eq!(r, transmute(lasx_xvpickod_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickod_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5072,7 +6089,13 @@ unsafe fn test_lasx_xvpickod_w() { 14200989743342145, ); - assert_eq!(r, transmute(lasx_xvpickod_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickod_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5096,7 +6119,13 @@ unsafe fn test_lasx_xvpickod_d() { 3923084493864153244, ); - assert_eq!(r, transmute(lasx_xvpickod_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickod_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5116,7 +6145,13 @@ unsafe fn test_lasx_xvilvh_b() { 6070396101995813657, ); - assert_eq!(r, transmute(lasx_xvilvh_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvh_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5136,7 +6171,13 @@ unsafe fn test_lasx_xvilvh_h() { 6944594579025051980, ); - assert_eq!(r, transmute(lasx_xvilvh_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvh_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5168,7 +6209,13 @@ unsafe fn test_lasx_xvilvh_w() { 2557948893958412086, ); - assert_eq!(r, transmute(lasx_xvilvh_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvh_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5192,7 +6239,13 @@ unsafe fn test_lasx_xvilvh_d() { -1576924492614617443, ); - assert_eq!(r, transmute(lasx_xvilvh_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvh_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5212,7 +6265,13 @@ unsafe fn test_lasx_xvilvl_b() { -1661662459983806644, ); - assert_eq!(r, transmute(lasx_xvilvl_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvl_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5232,7 +6291,13 @@ unsafe fn test_lasx_xvilvl_h() { -894657396213105965, ); - assert_eq!(r, transmute(lasx_xvilvl_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvl_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5264,7 +6329,13 @@ unsafe fn test_lasx_xvilvl_w() { 6940426927105417163, ); - assert_eq!(r, transmute(lasx_xvilvl_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvl_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5288,7 +6359,13 @@ unsafe fn test_lasx_xvilvl_d() { -2688716944239585727, ); - assert_eq!(r, transmute(lasx_xvilvl_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvl_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5308,7 +6385,13 @@ unsafe fn test_lasx_xvpackev_b() { -9004682544879989266, ); - assert_eq!(r, transmute(lasx_xvpackev_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackev_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5328,7 +6411,13 @@ unsafe fn test_lasx_xvpackev_h() { -5280992525495869891, ); - assert_eq!(r, transmute(lasx_xvpackev_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackev_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5360,7 +6449,13 @@ unsafe fn test_lasx_xvpackev_w() { 338692385926626324, ); - assert_eq!(r, transmute(lasx_xvpackev_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackev_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5384,7 +6479,13 @@ unsafe fn test_lasx_xvpackev_d() { -3601691172781761847, ); - assert_eq!(r, transmute(lasx_xvpackev_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackev_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5404,7 +6505,13 @@ unsafe fn test_lasx_xvpackod_b() { 3700670962761760653, ); - assert_eq!(r, transmute(lasx_xvpackod_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackod_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5424,7 +6531,13 @@ unsafe fn test_lasx_xvpackod_h() { -5523279134117035742, ); - assert_eq!(r, transmute(lasx_xvpackod_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackod_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5456,7 +6569,13 @@ unsafe fn test_lasx_xvpackod_w() { -7292079267755798519, ); - assert_eq!(r, transmute(lasx_xvpackod_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackod_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5480,7 +6599,13 @@ unsafe fn test_lasx_xvpackod_d() { -8628096693516187272, ); - assert_eq!(r, transmute(lasx_xvpackod_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackod_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5506,7 +6631,11 @@ unsafe fn test_lasx_xvshuf_b() { assert_eq!( r, - transmute(lasx_xvshuf_b(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvshuf_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5530,7 +6659,11 @@ unsafe fn test_lasx_xvshuf_h() { assert_eq!( r, - transmute(lasx_xvshuf_h(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvshuf_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5566,7 +6699,11 @@ unsafe fn test_lasx_xvshuf_w() { assert_eq!( r, - transmute(lasx_xvshuf_w(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvshuf_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5594,7 +6731,11 @@ unsafe fn test_lasx_xvshuf_d() { assert_eq!( r, - transmute(lasx_xvshuf_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvshuf_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5615,7 +6756,13 @@ unsafe fn test_lasx_xvand_v() { -7998109804568426495, ); - assert_eq!(r, transmute(lasx_xvand_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvand_v( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5631,7 +6778,7 @@ unsafe fn test_lasx_xvandi_b() { 793492300495455493, ); - assert_eq!(r, transmute(lasx_xvandi_b::<47>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvandi_b::<47>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5651,7 +6798,13 @@ unsafe fn test_lasx_xvor_v() { -198266276987019378, ); - assert_eq!(r, transmute(lasx_xvor_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvor_v( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5667,7 +6820,7 @@ unsafe fn test_lasx_xvori_b() { 8466485259632311926, ); - assert_eq!(r, transmute(lasx_xvori_b::<116>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvori_b::<116>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5687,7 +6840,13 @@ unsafe fn test_lasx_xvnor_v() { -8601510250130767824, ); - assert_eq!(r, transmute(lasx_xvnor_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvnor_v( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5703,7 +6862,7 @@ unsafe fn test_lasx_xvnori_b() { 6053994920729270286, ); - assert_eq!(r, transmute(lasx_xvnori_b::<161>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvnori_b::<161>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5723,7 +6882,13 @@ unsafe fn test_lasx_xvxor_v() { 4786489823605581252, ); - assert_eq!(r, transmute(lasx_xvxor_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvxor_v( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5739,7 +6904,7 @@ unsafe fn test_lasx_xvxori_b() { 1979210996964535887, ); - assert_eq!(r, transmute(lasx_xvxori_b::<179>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvxori_b::<179>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5765,7 +6930,11 @@ unsafe fn test_lasx_xvbitsel_v() { assert_eq!( r, - transmute(lasx_xvbitsel_v(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvbitsel_v( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5788,7 +6957,10 @@ unsafe fn test_lasx_xvbitseli_b() { assert_eq!( r, - transmute(lasx_xvbitseli_b::<156>(transmute(a), transmute(b))) + transmute(lasx_xvbitseli_b::<156>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5805,7 +6977,10 @@ unsafe fn test_lasx_xvshuf4i_b() { 1357573681433480718, ); - assert_eq!(r, transmute(lasx_xvshuf4i_b::<117>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvshuf4i_b::<117>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -5821,7 +6996,10 @@ unsafe fn test_lasx_xvshuf4i_h() { 4406041774853078309, ); - assert_eq!(r, transmute(lasx_xvshuf4i_h::<125>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvshuf4i_h::<125>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -5843,7 +7021,7 @@ unsafe fn test_lasx_xvshuf4i_w() { -206225345846487261, ); - assert_eq!(r, transmute(lasx_xvshuf4i_w::<10>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvshuf4i_w::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5855,7 +7033,7 @@ unsafe fn test_lasx_xvreplgr2vr_b() { 8463800222054970741, ); - assert_eq!(r, transmute(lasx_xvreplgr2vr_b(-139770763))); + assert_eq!(r, transmute(lasx_xvreplgr2vr_b(black_box(-139770763)))); } #[simd_test(enable = "lasx")] @@ -5867,7 +7045,7 @@ unsafe fn test_lasx_xvreplgr2vr_h() { -1100020993973555013, ); - assert_eq!(r, transmute(lasx_xvreplgr2vr_h(-111546181))); + assert_eq!(r, transmute(lasx_xvreplgr2vr_h(black_box(-111546181)))); } #[simd_test(enable = "lasx")] @@ -5879,7 +7057,7 @@ unsafe fn test_lasx_xvreplgr2vr_w() { -8112237653938959659, ); - assert_eq!(r, transmute(lasx_xvreplgr2vr_w(-1888777515))); + assert_eq!(r, transmute(lasx_xvreplgr2vr_w(black_box(-1888777515)))); } #[simd_test(enable = "lasx")] @@ -5891,7 +7069,10 @@ unsafe fn test_lasx_xvreplgr2vr_d() { -1472556476011894783, ); - assert_eq!(r, transmute(lasx_xvreplgr2vr_d(-1472556476011894783))); + assert_eq!( + r, + transmute(lasx_xvreplgr2vr_d(black_box(-1472556476011894783))) + ); } #[simd_test(enable = "lasx")] @@ -5907,7 +7088,7 @@ unsafe fn test_lasx_xvpcnt_b() { 288795538114413315, ); - assert_eq!(r, transmute(lasx_xvpcnt_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvpcnt_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5923,7 +7104,7 @@ unsafe fn test_lasx_xvpcnt_h() { 2251829878980617, ); - assert_eq!(r, transmute(lasx_xvpcnt_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvpcnt_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5940,7 +7121,7 @@ unsafe fn test_lasx_xvpcnt_w() { ); let r = i64x4::new(77309411341, 60129542155, 73014444046, 55834574863); - assert_eq!(r, transmute(lasx_xvpcnt_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvpcnt_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5953,7 +7134,7 @@ unsafe fn test_lasx_xvpcnt_d() { ); let r = i64x4::new(33, 31, 29, 33); - assert_eq!(r, transmute(lasx_xvpcnt_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvpcnt_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5964,7 +7145,7 @@ unsafe fn test_lasx_xvclo_b() { ); let r = i64x4::new(2207613190657, 8589934592, 1103806726660, 3298568503554); - assert_eq!(r, transmute(lasx_xvclo_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclo_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5980,7 +7161,7 @@ unsafe fn test_lasx_xvclo_h() { 281479271677953, ); - assert_eq!(r, transmute(lasx_xvclo_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclo_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5997,7 +7178,7 @@ unsafe fn test_lasx_xvclo_w() { ); let r = i64x4::new(4294967299, 1, 1, 8589934593); - assert_eq!(r, transmute(lasx_xvclo_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclo_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6010,7 +7191,7 @@ unsafe fn test_lasx_xvclo_d() { ); let r = i64x4::new(2, 0, 1, 0); - assert_eq!(r, transmute(lasx_xvclo_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclo_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6021,7 +7202,7 @@ unsafe fn test_lasx_xvclz_b() { ); let r = i64x4::new(65538, 72621643502977024, 216173885920575744, 3302846693380); - assert_eq!(r, transmute(lasx_xvclz_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclz_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6037,7 +7218,7 @@ unsafe fn test_lasx_xvclz_h() { 17179934721, ); - assert_eq!(r, transmute(lasx_xvclz_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclz_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6054,7 +7235,7 @@ unsafe fn test_lasx_xvclz_w() { ); let r = i64x4::new(8589934592, 0, 3, 4294967296); - assert_eq!(r, transmute(lasx_xvclz_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclz_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6067,7 +7248,7 @@ unsafe fn test_lasx_xvclz_d() { ); let r = i64x4::new(0, 0, 0, 1); - assert_eq!(r, transmute(lasx_xvclz_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclz_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6087,7 +7268,13 @@ unsafe fn test_lasx_xvfadd_s() { 4545553165339792015, ); - assert_eq!(r, transmute(lasx_xvfadd_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfadd_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6111,7 +7298,13 @@ unsafe fn test_lasx_xvfadd_d() { 4607242424158867483, ); - assert_eq!(r, transmute(lasx_xvfadd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfadd_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6131,7 +7324,13 @@ unsafe fn test_lasx_xvfsub_s() { -4716328899074058446, ); - assert_eq!(r, transmute(lasx_xvfsub_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfsub_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6155,7 +7354,13 @@ unsafe fn test_lasx_xvfsub_d() { 4602885236169716939, ); - assert_eq!(r, transmute(lasx_xvfsub_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfsub_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6175,7 +7380,13 @@ unsafe fn test_lasx_xvfmul_s() { 4412217640780718091, ); - assert_eq!(r, transmute(lasx_xvfmul_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmul_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6199,7 +7410,13 @@ unsafe fn test_lasx_xvfmul_d() { 4604645288864682176, ); - assert_eq!(r, transmute(lasx_xvfmul_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmul_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6219,7 +7436,13 @@ unsafe fn test_lasx_xvfdiv_s() { 4544549637634302505, ); - assert_eq!(r, transmute(lasx_xvfdiv_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfdiv_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6243,7 +7466,13 @@ unsafe fn test_lasx_xvfdiv_d() { 4608170208670026319, ); - assert_eq!(r, transmute(lasx_xvfdiv_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfdiv_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6263,7 +7492,13 @@ unsafe fn test_lasx_xvfcvt_h_s() { 4182498428240214789, ); - assert_eq!(r, transmute(lasx_xvfcvt_h_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcvt_h_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6287,7 +7522,13 @@ unsafe fn test_lasx_xvfcvt_s_d() { 4509540616169896248, ); - assert_eq!(r, transmute(lasx_xvfcvt_s_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcvt_s_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6307,7 +7548,13 @@ unsafe fn test_lasx_xvfmin_s() { 4470137692837414470, ); - assert_eq!(r, transmute(lasx_xvfmin_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmin_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6331,7 +7578,13 @@ unsafe fn test_lasx_xvfmin_d() { 4596668800324369880, ); - assert_eq!(r, transmute(lasx_xvfmin_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmin_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6351,7 +7604,13 @@ unsafe fn test_lasx_xvfmina_s() { 4561809912873379512, ); - assert_eq!(r, transmute(lasx_xvfmina_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmina_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6375,7 +7634,13 @@ unsafe fn test_lasx_xvfmina_d() { 4597161583916257152, ); - assert_eq!(r, transmute(lasx_xvfmina_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmina_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6395,7 +7660,13 @@ unsafe fn test_lasx_xvfmax_s() { 4574742780979947531, ); - assert_eq!(r, transmute(lasx_xvfmax_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmax_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6419,7 +7690,13 @@ unsafe fn test_lasx_xvfmax_d() { 4602928137069840177, ); - assert_eq!(r, transmute(lasx_xvfmax_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmax_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6439,7 +7716,13 @@ unsafe fn test_lasx_xvfmaxa_s() { 4527767521076114844, ); - assert_eq!(r, transmute(lasx_xvfmaxa_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmaxa_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6463,7 +7746,13 @@ unsafe fn test_lasx_xvfmaxa_d() { 4596362093665607644, ); - assert_eq!(r, transmute(lasx_xvfmaxa_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmaxa_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6474,7 +7763,7 @@ unsafe fn test_lasx_xvfclass_s() { ); let r = i64x4::new(549755814016, 549755814016, 549755814016, 549755814016); - assert_eq!(r, transmute(lasx_xvfclass_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfclass_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6487,7 +7776,7 @@ unsafe fn test_lasx_xvfclass_d() { ); let r = i64x4::new(128, 128, 128, 128); - assert_eq!(r, transmute(lasx_xvfclass_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfclass_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6503,7 +7792,7 @@ unsafe fn test_lasx_xvfsqrt_s() { 4566109703441416989, ); - assert_eq!(r, transmute(lasx_xvfsqrt_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfsqrt_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6521,7 +7810,7 @@ unsafe fn test_lasx_xvfsqrt_d() { 4601138545884238765, ); - assert_eq!(r, transmute(lasx_xvfsqrt_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfsqrt_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6537,7 +7826,7 @@ unsafe fn test_lasx_xvfrecip_s() { 4585242601638738136, ); - assert_eq!(r, transmute(lasx_xvfrecip_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrecip_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6555,7 +7844,7 @@ unsafe fn test_lasx_xvfrecip_d() { 4611482062367896141, ); - assert_eq!(r, transmute(lasx_xvfrecip_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrecip_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx,frecipe")] @@ -6571,7 +7860,7 @@ unsafe fn test_lasx_xvfrecipe_s() { 4728509413412007938, ); - assert_eq!(r, transmute(lasx_xvfrecipe_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrecipe_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx,frecipe")] @@ -6589,7 +7878,7 @@ unsafe fn test_lasx_xvfrecipe_d() { 4611499011256352768, ); - assert_eq!(r, transmute(lasx_xvfrecipe_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrecipe_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx,frecipe")] @@ -6605,7 +7894,7 @@ unsafe fn test_lasx_xvfrsqrte_s() { 4612427253546066334, ); - assert_eq!(r, transmute(lasx_xvfrsqrte_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrsqrte_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx,frecipe")] @@ -6623,7 +7912,7 @@ unsafe fn test_lasx_xvfrsqrte_d() { 4612346183891812352, ); - assert_eq!(r, transmute(lasx_xvfrsqrte_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrsqrte_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6634,7 +7923,7 @@ unsafe fn test_lasx_xvfrint_s() { ); let r = i64x4::new(0, 4575657222473777152, 1065353216, 4575657222473777152); - assert_eq!(r, transmute(lasx_xvfrint_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrint_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6652,7 +7941,7 @@ unsafe fn test_lasx_xvfrint_d() { 0, ); - assert_eq!(r, transmute(lasx_xvfrint_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrint_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6668,7 +7957,7 @@ unsafe fn test_lasx_xvfrsqrt_s() { 4651901116840286347, ); - assert_eq!(r, transmute(lasx_xvfrsqrt_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrsqrt_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6686,7 +7975,7 @@ unsafe fn test_lasx_xvfrsqrt_d() { 4612495411087822923, ); - assert_eq!(r, transmute(lasx_xvfrsqrt_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrsqrt_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6702,7 +7991,7 @@ unsafe fn test_lasx_xvflogb_s() { -4575657218195587072, ); - assert_eq!(r, transmute(lasx_xvflogb_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvflogb_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6720,7 +8009,7 @@ unsafe fn test_lasx_xvflogb_d() { -4616189618054758400, ); - assert_eq!(r, transmute(lasx_xvflogb_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvflogb_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6736,7 +8025,7 @@ unsafe fn test_lasx_xvfcvth_s_h() { 4931511963987271680, ); - assert_eq!(r, transmute(lasx_xvfcvth_s_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfcvth_s_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6752,7 +8041,7 @@ unsafe fn test_lasx_xvfcvth_d_s() { 4605684912954015744, ); - assert_eq!(r, transmute(lasx_xvfcvth_d_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfcvth_d_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6768,7 +8057,7 @@ unsafe fn test_lasx_xvfcvtl_s_h() { 4719033540912152576, ); - assert_eq!(r, transmute(lasx_xvfcvtl_s_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfcvtl_s_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6784,7 +8073,7 @@ unsafe fn test_lasx_xvfcvtl_d_s() { 4598772185639682048, ); - assert_eq!(r, transmute(lasx_xvfcvtl_d_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfcvtl_d_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6795,7 +8084,7 @@ unsafe fn test_lasx_xvftint_w_s() { ); let r = i64x4::new(0, 0, 1, 0); - assert_eq!(r, transmute(lasx_xvftint_w_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftint_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6808,7 +8097,7 @@ unsafe fn test_lasx_xvftint_l_d() { ); let r = i64x4::new(0, 0, 1, 1); - assert_eq!(r, transmute(lasx_xvftint_l_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftint_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6819,7 +8108,7 @@ unsafe fn test_lasx_xvftint_wu_s() { ); let r = i64x4::new(1, 4294967297, 1, 4294967297); - assert_eq!(r, transmute(lasx_xvftint_wu_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftint_wu_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6832,7 +8121,7 @@ unsafe fn test_lasx_xvftint_lu_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftint_lu_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftint_lu_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6843,7 +8132,7 @@ unsafe fn test_lasx_xvftintrz_w_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrz_w_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrz_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6856,7 +8145,7 @@ unsafe fn test_lasx_xvftintrz_l_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrz_l_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrz_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6867,7 +8156,7 @@ unsafe fn test_lasx_xvftintrz_wu_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrz_wu_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrz_wu_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6880,7 +8169,7 @@ unsafe fn test_lasx_xvftintrz_lu_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrz_lu_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrz_lu_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6902,7 +8191,7 @@ unsafe fn test_lasx_xvffint_s_w() { 5669248528000103797, ); - assert_eq!(r, transmute(lasx_xvffint_s_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvffint_s_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6920,7 +8209,7 @@ unsafe fn test_lasx_xvffint_d_l() { -4362160337941248997, ); - assert_eq!(r, transmute(lasx_xvffint_d_l(transmute(a)))); + assert_eq!(r, transmute(lasx_xvffint_d_l(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6936,7 +8225,7 @@ unsafe fn test_lasx_xvffint_s_wu() { 5723492283472660471, ); - assert_eq!(r, transmute(lasx_xvffint_s_wu(transmute(a)))); + assert_eq!(r, transmute(lasx_xvffint_s_wu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6954,7 +8243,7 @@ unsafe fn test_lasx_xvffint_d_lu() { 4892265567869239358, ); - assert_eq!(r, transmute(lasx_xvffint_d_lu(transmute(a)))); + assert_eq!(r, transmute(lasx_xvffint_d_lu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6970,7 +8259,7 @@ unsafe fn test_lasx_xvreplve_b() { -5280832617179597130, ); - assert_eq!(r, transmute(lasx_xvreplve_b(transmute(a), 5))); + assert_eq!(r, transmute(lasx_xvreplve_b(black_box(transmute(a)), 5))); } #[simd_test(enable = "lasx")] @@ -6986,7 +8275,7 @@ unsafe fn test_lasx_xvreplve_h() { -8907411554322709406, ); - assert_eq!(r, transmute(lasx_xvreplve_h(transmute(a), -5))); + assert_eq!(r, transmute(lasx_xvreplve_h(black_box(transmute(a)), -5))); } #[simd_test(enable = "lasx")] @@ -7008,7 +8297,7 @@ unsafe fn test_lasx_xvreplve_w() { -2569718735257041300, ); - assert_eq!(r, transmute(lasx_xvreplve_w(transmute(a), 1))); + assert_eq!(r, transmute(lasx_xvreplve_w(black_box(transmute(a)), 1))); } #[simd_test(enable = "lasx")] @@ -7026,7 +8315,7 @@ unsafe fn test_lasx_xvreplve_d() { -7945890434069746992, ); - assert_eq!(r, transmute(lasx_xvreplve_d(transmute(a), -6))); + assert_eq!(r, transmute(lasx_xvreplve_d(black_box(transmute(a)), -6))); } #[simd_test(enable = "lasx")] @@ -7060,7 +8349,10 @@ unsafe fn test_lasx_xvpermi_w() { assert_eq!( r, - transmute(lasx_xvpermi_w::<217>(transmute(a), transmute(b))) + transmute(lasx_xvpermi_w::<217>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -7081,7 +8373,13 @@ unsafe fn test_lasx_xvandn_v() { 5350223724150917, ); - assert_eq!(r, transmute(lasx_xvandn_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvandn_v( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7097,7 +8395,7 @@ unsafe fn test_lasx_xvneg_b() { -5388239603749330053, ); - assert_eq!(r, transmute(lasx_xvneg_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvneg_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -7113,7 +8411,7 @@ unsafe fn test_lasx_xvneg_h() { 5510114370614593991, ); - assert_eq!(r, transmute(lasx_xvneg_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvneg_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -7135,7 +8433,7 @@ unsafe fn test_lasx_xvneg_w() { -6240794077010148150, ); - assert_eq!(r, transmute(lasx_xvneg_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvneg_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -7153,7 +8451,7 @@ unsafe fn test_lasx_xvneg_d() { -906750919774206543, ); - assert_eq!(r, transmute(lasx_xvneg_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvneg_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -7173,7 +8471,13 @@ unsafe fn test_lasx_xvmuh_b() { 131228860074087168, ); - assert_eq!(r, transmute(lasx_xvmuh_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmuh_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7193,7 +8497,13 @@ unsafe fn test_lasx_xvmuh_h() { -14890625691814142, ); - assert_eq!(r, transmute(lasx_xvmuh_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmuh_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7225,7 +8535,13 @@ unsafe fn test_lasx_xvmuh_w() { 15710306989437773, ); - assert_eq!(r, transmute(lasx_xvmuh_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmuh_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7249,7 +8565,13 @@ unsafe fn test_lasx_xvmuh_d() { 273863514955286020, ); - assert_eq!(r, transmute(lasx_xvmuh_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmuh_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7269,7 +8591,13 @@ unsafe fn test_lasx_xvmuh_bu() { 442221464076014683, ); - assert_eq!(r, transmute(lasx_xvmuh_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmuh_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7289,7 +8617,13 @@ unsafe fn test_lasx_xvmuh_hu() { 108786773599653576, ); - assert_eq!(r, transmute(lasx_xvmuh_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmuh_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7309,7 +8643,13 @@ unsafe fn test_lasx_xvmuh_wu() { 3278999485098399815, ); - assert_eq!(r, transmute(lasx_xvmuh_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmuh_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7333,7 +8673,13 @@ unsafe fn test_lasx_xvmuh_du() { 1569823798457591419, ); - assert_eq!(r, transmute(lasx_xvmuh_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmuh_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7349,7 +8695,10 @@ unsafe fn test_lasx_xvsllwil_h_b() { 283732621893107440, ); - assert_eq!(r, transmute(lasx_xvsllwil_h_b::<4>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvsllwil_h_b::<4>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -7365,7 +8714,10 @@ unsafe fn test_lasx_xvsllwil_w_h() { -19087521822982144, ); - assert_eq!(r, transmute(lasx_xvsllwil_w_h::<11>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvsllwil_w_h::<11>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -7387,7 +8739,10 @@ unsafe fn test_lasx_xvsllwil_d_w() { -21769464725504, ); - assert_eq!(r, transmute(lasx_xvsllwil_d_w::<14>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvsllwil_d_w::<14>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -7403,7 +8758,10 @@ unsafe fn test_lasx_xvsllwil_hu_bu() { 180156217344131904, ); - assert_eq!(r, transmute(lasx_xvsllwil_hu_bu::<5>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvsllwil_hu_bu::<5>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -7419,7 +8777,10 @@ unsafe fn test_lasx_xvsllwil_wu_hu() { 3493526673607606272, ); - assert_eq!(r, transmute(lasx_xvsllwil_wu_hu::<14>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvsllwil_wu_hu::<14>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -7435,7 +8796,10 @@ unsafe fn test_lasx_xvsllwil_du_wu() { 147522340803051520, ); - assert_eq!(r, transmute(lasx_xvsllwil_du_wu::<28>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvsllwil_du_wu::<28>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -7450,7 +8814,13 @@ unsafe fn test_lasx_xvsran_b_h() { ); let r = i64x4::new(-5107013816536599300, 0, -576745268203292981, 0); - assert_eq!(r, transmute(lasx_xvsran_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsran_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7477,7 +8847,13 @@ unsafe fn test_lasx_xvsran_h_w() { ); let r = i64x4::new(-7492863874014043255, 0, -5145548381371170633, 0); - assert_eq!(r, transmute(lasx_xvsran_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsran_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7496,7 +8872,13 @@ unsafe fn test_lasx_xvsran_w_d() { ); let r = i64x4::new(58054624080, 0, 1863787881113495402, 0); - assert_eq!(r, transmute(lasx_xvsran_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsran_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7511,7 +8893,13 @@ unsafe fn test_lasx_xvssran_b_h() { ); let r = i64x4::new(179865806513864501, 0, -9222296776751415043, 0); - assert_eq!(r, transmute(lasx_xvssran_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssran_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7538,7 +8926,13 @@ unsafe fn test_lasx_xvssran_h_w() { ); let r = i64x4::new(281015415144451, 0, 281472829161978, 0); - assert_eq!(r, transmute(lasx_xvssran_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssran_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7557,7 +8951,13 @@ unsafe fn test_lasx_xvssran_w_d() { ); let r = i64x4::new(-109363692856335914, 0, -713658208354305, 0); - assert_eq!(r, transmute(lasx_xvssran_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssran_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7572,7 +8972,13 @@ unsafe fn test_lasx_xvssran_bu_h() { ); let r = i64x4::new(144116287595479055, 0, 71776131929997312, 0); - assert_eq!(r, transmute(lasx_xvssran_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssran_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7587,7 +8993,13 @@ unsafe fn test_lasx_xvssran_hu_w() { ); let r = i64x4::new(254837589540863, 0, 281470681765343, 0); - assert_eq!(r, transmute(lasx_xvssran_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssran_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7606,7 +9018,13 @@ unsafe fn test_lasx_xvssran_wu_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvssran_wu_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssran_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7621,7 +9039,13 @@ unsafe fn test_lasx_xvsrarn_b_h() { ); let r = i64x4::new(-7204067930850651184, 0, -5909457163402939758, 0); - assert_eq!(r, transmute(lasx_xvsrarn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrarn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7648,7 +9072,13 @@ unsafe fn test_lasx_xvsrarn_h_w() { ); let r = i64x4::new(4021320339558432771, 0, -5499970420202995712, 0); - assert_eq!(r, transmute(lasx_xvsrarn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrarn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7667,7 +9097,13 @@ unsafe fn test_lasx_xvsrarn_w_d() { ); let r = i64x4::new(-69752906595470, 0, -7240468610764767136, 0); - assert_eq!(r, transmute(lasx_xvsrarn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrarn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7682,7 +9118,13 @@ unsafe fn test_lasx_xvssrarn_b_h() { ); let r = i64x4::new(142413695971000447, 0, -141179869986524, 0); - assert_eq!(r, transmute(lasx_xvssrarn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrarn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7709,7 +9151,13 @@ unsafe fn test_lasx_xvssrarn_h_w() { ); let r = i64x4::new(-10414028872220672, 0, 9223104806137135104, 0); - assert_eq!(r, transmute(lasx_xvssrarn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrarn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7728,7 +9176,13 @@ unsafe fn test_lasx_xvssrarn_w_d() { ); let r = i64x4::new(2147483648, 0, 326062786704572415, 0); - assert_eq!(r, transmute(lasx_xvssrarn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrarn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7743,7 +9197,13 @@ unsafe fn test_lasx_xvssrarn_bu_h() { ); let r = i64x4::new(4286578689, 0, 8163878114427135, 0); - assert_eq!(r, transmute(lasx_xvssrarn_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrarn_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7758,7 +9218,13 @@ unsafe fn test_lasx_xvssrarn_hu_w() { ); let r = i64x4::new(-281474976710656, 0, 2199023255552, 0); - assert_eq!(r, transmute(lasx_xvssrarn_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrarn_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7777,7 +9243,13 @@ unsafe fn test_lasx_xvssrarn_wu_d() { ); let r = i64x4::new(-3539373509, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvssrarn_wu_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrarn_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7792,7 +9264,13 @@ unsafe fn test_lasx_xvsrln_b_h() { ); let r = i64x4::new(776589499955319005, 0, 285495199351976, 0); - assert_eq!(r, transmute(lasx_xvsrln_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrln_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7819,7 +9297,13 @@ unsafe fn test_lasx_xvsrln_h_w() { ); let r = i64x4::new(-6090306652816735409, 0, -1175228277373752196, 0); - assert_eq!(r, transmute(lasx_xvsrln_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrln_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7838,7 +9322,13 @@ unsafe fn test_lasx_xvsrln_w_d() { ); let r = i64x4::new(262796920316080678, 0, 1866060245111069, 0); - assert_eq!(r, transmute(lasx_xvsrln_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrln_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7853,7 +9343,13 @@ unsafe fn test_lasx_xvssrln_bu_h() { ); let r = i64x4::new(-996419305685, 0, -71773920038018305, 0); - assert_eq!(r, transmute(lasx_xvssrln_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrln_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7867,7 +9363,13 @@ unsafe fn test_lasx_xvssrln_hu_w() { ); let r = i64x4::new(2319476961249468, 0, 208855326080470286, 0); - assert_eq!(r, transmute(lasx_xvssrln_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrln_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7886,7 +9388,13 @@ unsafe fn test_lasx_xvssrln_wu_d() { ); let r = i64x4::new(-1, 0, -1, 0); - assert_eq!(r, transmute(lasx_xvssrln_wu_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrln_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7901,7 +9409,13 @@ unsafe fn test_lasx_xvsrlrn_b_h() { ); let r = i64x4::new(-6693460433276960310, 0, -6122543899663285619, 0); - assert_eq!(r, transmute(lasx_xvsrlrn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrlrn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7928,7 +9442,13 @@ unsafe fn test_lasx_xvsrlrn_h_w() { ); let r = i64x4::new(390723813551243448, 0, 6015496732136052023, 0); - assert_eq!(r, transmute(lasx_xvsrlrn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrlrn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7947,7 +9467,13 @@ unsafe fn test_lasx_xvsrlrn_w_d() { ); let r = i64x4::new(4295025675, 0, -3281590872273059757, 0); - assert_eq!(r, transmute(lasx_xvsrlrn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrlrn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7962,7 +9488,13 @@ unsafe fn test_lasx_xvssrlrn_bu_h() { ); let r = i64x4::new(-258385232527491, 0, 4034951496335359804, 0); - assert_eq!(r, transmute(lasx_xvssrlrn_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrlrn_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7977,7 +9509,13 @@ unsafe fn test_lasx_xvssrlrn_hu_w() { ); let r = i64x4::new(-3854303052, 0, -4029743103, 0); - assert_eq!(r, transmute(lasx_xvssrlrn_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrlrn_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7996,9 +9534,15 @@ unsafe fn test_lasx_xvssrlrn_wu_d() { ); let r = i64x4::new(-3223981555, 0, 35952127557763071, 0); - assert_eq!(r, transmute(lasx_xvssrlrn_wu_d(transmute(a), transmute(b)))); -} - + assert_eq!( + r, + transmute(lasx_xvssrlrn_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); +} + #[simd_test(enable = "lasx")] unsafe fn test_lasx_xvfrstpi_b() { let a = i8x32::new( @@ -8018,7 +9562,10 @@ unsafe fn test_lasx_xvfrstpi_b() { assert_eq!( r, - transmute(lasx_xvfrstpi_b::<24>(transmute(a), transmute(b))) + transmute(lasx_xvfrstpi_b::<24>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8041,7 +9588,10 @@ unsafe fn test_lasx_xvfrstpi_h() { assert_eq!( r, - transmute(lasx_xvfrstpi_h::<10>(transmute(a), transmute(b))) + transmute(lasx_xvfrstpi_h::<10>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8068,7 +9618,11 @@ unsafe fn test_lasx_xvfrstp_b() { assert_eq!( r, - transmute(lasx_xvfrstp_b(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfrstp_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8095,7 +9649,11 @@ unsafe fn test_lasx_xvfrstp_h() { assert_eq!( r, - transmute(lasx_xvfrstp_h(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfrstp_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8122,7 +9680,10 @@ unsafe fn test_lasx_xvshuf4i_d() { assert_eq!( r, - transmute(lasx_xvshuf4i_d::<115>(transmute(a), transmute(b))) + transmute(lasx_xvshuf4i_d::<115>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8139,7 +9700,7 @@ unsafe fn test_lasx_xvbsrl_v() { 8842437361645499941, ); - assert_eq!(r, transmute(lasx_xvbsrl_v::<0>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvbsrl_v::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8155,7 +9716,7 @@ unsafe fn test_lasx_xvbsll_v() { 5030360181484275352, ); - assert_eq!(r, transmute(lasx_xvbsll_v::<0>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvbsll_v::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8177,7 +9738,10 @@ unsafe fn test_lasx_xvextrins_b() { assert_eq!( r, - transmute(lasx_xvextrins_b::<69>(transmute(a), transmute(b))) + transmute(lasx_xvextrins_b::<69>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8200,7 +9764,10 @@ unsafe fn test_lasx_xvextrins_h() { assert_eq!( r, - transmute(lasx_xvextrins_h::<190>(transmute(a), transmute(b))) + transmute(lasx_xvextrins_h::<190>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8235,7 +9802,10 @@ unsafe fn test_lasx_xvextrins_w() { assert_eq!( r, - transmute(lasx_xvextrins_w::<133>(transmute(a), transmute(b))) + transmute(lasx_xvextrins_w::<133>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8262,7 +9832,10 @@ unsafe fn test_lasx_xvextrins_d() { assert_eq!( r, - transmute(lasx_xvextrins_d::<210>(transmute(a), transmute(b))) + transmute(lasx_xvextrins_d::<210>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8274,7 +9847,7 @@ unsafe fn test_lasx_xvmskltz_b() { ); let r = i64x4::new(5684, 0, 36244, 0); - assert_eq!(r, transmute(lasx_xvmskltz_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmskltz_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8285,7 +9858,7 @@ unsafe fn test_lasx_xvmskltz_h() { ); let r = i64x4::new(225, 0, 96, 0); - assert_eq!(r, transmute(lasx_xvmskltz_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmskltz_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8302,7 +9875,7 @@ unsafe fn test_lasx_xvmskltz_w() { ); let r = i64x4::new(13, 0, 10, 0); - assert_eq!(r, transmute(lasx_xvmskltz_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmskltz_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8315,7 +9888,7 @@ unsafe fn test_lasx_xvmskltz_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvmskltz_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmskltz_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8335,7 +9908,13 @@ unsafe fn test_lasx_xvsigncov_b() { -6215157037026399088, ); - assert_eq!(r, transmute(lasx_xvsigncov_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsigncov_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8355,7 +9934,13 @@ unsafe fn test_lasx_xvsigncov_h() { 2866604565619890601, ); - assert_eq!(r, transmute(lasx_xvsigncov_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsigncov_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8387,7 +9972,13 @@ unsafe fn test_lasx_xvsigncov_w() { -180354238538399451, ); - assert_eq!(r, transmute(lasx_xvsigncov_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsigncov_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8411,7 +10002,13 @@ unsafe fn test_lasx_xvsigncov_d() { 293290471183495768, ); - assert_eq!(r, transmute(lasx_xvsigncov_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsigncov_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8437,7 +10034,11 @@ unsafe fn test_lasx_xvfmadd_s() { assert_eq!( r, - transmute(lasx_xvfmadd_s(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfmadd_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8470,7 +10071,11 @@ unsafe fn test_lasx_xvfmadd_d() { assert_eq!( r, - transmute(lasx_xvfmadd_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfmadd_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8497,7 +10102,11 @@ unsafe fn test_lasx_xvfmsub_s() { assert_eq!( r, - transmute(lasx_xvfmsub_s(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfmsub_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8530,7 +10139,11 @@ unsafe fn test_lasx_xvfmsub_d() { assert_eq!( r, - transmute(lasx_xvfmsub_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfmsub_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8557,7 +10170,11 @@ unsafe fn test_lasx_xvfnmadd_s() { assert_eq!( r, - transmute(lasx_xvfnmadd_s(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfnmadd_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8590,7 +10207,11 @@ unsafe fn test_lasx_xvfnmadd_d() { assert_eq!( r, - transmute(lasx_xvfnmadd_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfnmadd_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8617,7 +10238,11 @@ unsafe fn test_lasx_xvfnmsub_s() { assert_eq!( r, - transmute(lasx_xvfnmsub_s(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfnmsub_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8650,7 +10275,11 @@ unsafe fn test_lasx_xvfnmsub_d() { assert_eq!( r, - transmute(lasx_xvfnmsub_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfnmsub_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8662,7 +10291,7 @@ unsafe fn test_lasx_xvftintrne_w_s() { ); let r = i64x4::new(1, 0, 1, 4294967297); - assert_eq!(r, transmute(lasx_xvftintrne_w_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrne_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8675,7 +10304,7 @@ unsafe fn test_lasx_xvftintrne_l_d() { ); let r = i64x4::new(0, 1, 1, 0); - assert_eq!(r, transmute(lasx_xvftintrne_l_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrne_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8686,7 +10315,7 @@ unsafe fn test_lasx_xvftintrp_w_s() { ); let r = i64x4::new(4294967297, 4294967297, 4294967297, 4294967297); - assert_eq!(r, transmute(lasx_xvftintrp_w_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrp_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8699,7 +10328,7 @@ unsafe fn test_lasx_xvftintrp_l_d() { ); let r = i64x4::new(1, 1, 1, 1); - assert_eq!(r, transmute(lasx_xvftintrp_l_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrp_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8710,7 +10339,7 @@ unsafe fn test_lasx_xvftintrm_w_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrm_w_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrm_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8723,7 +10352,7 @@ unsafe fn test_lasx_xvftintrm_l_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrm_l_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrm_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8742,7 +10371,13 @@ unsafe fn test_lasx_xvftint_w_d() { ); let r = i64x4::new(0, 0, 4294967297, 4294967296); - assert_eq!(r, transmute(lasx_xvftint_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvftint_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8766,7 +10401,13 @@ unsafe fn test_lasx_xvffint_s_l() { -2383622820954443903, ); - assert_eq!(r, transmute(lasx_xvffint_s_l(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvffint_s_l( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8785,7 +10426,13 @@ unsafe fn test_lasx_xvftintrz_w_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrz_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvftintrz_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8804,7 +10451,13 @@ unsafe fn test_lasx_xvftintrp_w_d() { ); let r = i64x4::new(4294967297, 4294967297, 4294967297, 4294967297); - assert_eq!(r, transmute(lasx_xvftintrp_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvftintrp_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8823,7 +10476,13 @@ unsafe fn test_lasx_xvftintrm_w_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrm_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvftintrm_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8844,7 +10503,10 @@ unsafe fn test_lasx_xvftintrne_w_d() { assert_eq!( r, - transmute(lasx_xvftintrne_w_d(transmute(a), transmute(b))) + transmute(lasx_xvftintrne_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8856,7 +10518,7 @@ unsafe fn test_lasx_xvftinth_l_s() { ); let r = i64x4::new(0, 1, 0, 1); - assert_eq!(r, transmute(lasx_xvftinth_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftinth_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8867,7 +10529,7 @@ unsafe fn test_lasx_xvftintl_l_s() { ); let r = i64x4::new(0, 0, 0, 1); - assert_eq!(r, transmute(lasx_xvftintl_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintl_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8889,7 +10551,7 @@ unsafe fn test_lasx_xvffinth_d_w() { -4485741486683455488, ); - assert_eq!(r, transmute(lasx_xvffinth_d_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvffinth_d_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8911,7 +10573,7 @@ unsafe fn test_lasx_xvffintl_d_w() { -4489746915386195968, ); - assert_eq!(r, transmute(lasx_xvffintl_d_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvffintl_d_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8922,7 +10584,7 @@ unsafe fn test_lasx_xvftintrzh_l_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrzh_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrzh_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8933,7 +10595,7 @@ unsafe fn test_lasx_xvftintrzl_l_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrzl_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrzl_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8944,7 +10606,7 @@ unsafe fn test_lasx_xvftintrph_l_s() { ); let r = i64x4::new(1, 1, 1, 1); - assert_eq!(r, transmute(lasx_xvftintrph_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrph_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8955,7 +10617,7 @@ unsafe fn test_lasx_xvftintrpl_l_s() { ); let r = i64x4::new(1, 1, 1, 1); - assert_eq!(r, transmute(lasx_xvftintrpl_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrpl_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8966,7 +10628,7 @@ unsafe fn test_lasx_xvftintrmh_l_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrmh_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrmh_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8977,7 +10639,7 @@ unsafe fn test_lasx_xvftintrml_l_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrml_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrml_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8988,7 +10650,7 @@ unsafe fn test_lasx_xvftintrneh_l_s() { ); let r = i64x4::new(1, 0, 0, 1); - assert_eq!(r, transmute(lasx_xvftintrneh_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrneh_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8999,7 +10661,7 @@ unsafe fn test_lasx_xvftintrnel_l_s() { ); let r = i64x4::new(0, 1, 1, 0); - assert_eq!(r, transmute(lasx_xvftintrnel_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrnel_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9015,7 +10677,7 @@ unsafe fn test_lasx_xvfrintrne_s() { 1065353216, ); - assert_eq!(r, transmute(lasx_xvfrintrne_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrne_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9028,7 +10690,7 @@ unsafe fn test_lasx_xvfrintrne_d() { ); let r = i64x4::new(0, 0, 4607182418800017408, 0); - assert_eq!(r, transmute(lasx_xvfrintrne_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrne_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9039,7 +10701,7 @@ unsafe fn test_lasx_xvfrintrz_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfrintrz_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrz_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9052,7 +10714,7 @@ unsafe fn test_lasx_xvfrintrz_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfrintrz_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrz_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9068,7 +10730,7 @@ unsafe fn test_lasx_xvfrintrp_s() { 4575657222473777152, ); - assert_eq!(r, transmute(lasx_xvfrintrp_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrp_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9086,7 +10748,7 @@ unsafe fn test_lasx_xvfrintrp_d() { 4607182418800017408, ); - assert_eq!(r, transmute(lasx_xvfrintrp_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrp_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9097,7 +10759,7 @@ unsafe fn test_lasx_xvfrintrm_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfrintrm_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrm_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9110,7 +10772,7 @@ unsafe fn test_lasx_xvfrintrm_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfrintrm_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrm_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9146,7 +10808,7 @@ unsafe fn test_lasx_xvst() { -1239470096778490055, ); - lasx_xvst::<0>(transmute(a), o.as_mut_ptr()); + lasx_xvst::<0>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -9167,7 +10829,7 @@ unsafe fn test_lasx_xvstelm_b() { -1243134694581333281, ); - lasx_xvstelm_b::<0, 9>(transmute(a), o.as_mut_ptr()); + lasx_xvstelm_b::<0, 9>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -9188,7 +10850,7 @@ unsafe fn test_lasx_xvstelm_h() { 4649151313692342074, ); - lasx_xvstelm_h::<0, 6>(transmute(a), o.as_mut_ptr()); + lasx_xvstelm_h::<0, 6>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -9215,7 +10877,7 @@ unsafe fn test_lasx_xvstelm_w() { 5471549130760739388, ); - lasx_xvstelm_w::<0, 3>(transmute(a), o.as_mut_ptr()); + lasx_xvstelm_w::<0, 3>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -9238,7 +10900,7 @@ unsafe fn test_lasx_xvstelm_d() { -4006899083251152793, ); - lasx_xvstelm_d::<0, 0>(transmute(a), o.as_mut_ptr()); + lasx_xvstelm_d::<0, 0>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -9273,7 +10935,10 @@ unsafe fn test_lasx_xvinsve0_w() { assert_eq!( r, - transmute(lasx_xvinsve0_w::<5>(transmute(a), transmute(b))) + transmute(lasx_xvinsve0_w::<5>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -9300,7 +10965,10 @@ unsafe fn test_lasx_xvinsve0_d() { assert_eq!( r, - transmute(lasx_xvinsve0_d::<3>(transmute(a), transmute(b))) + transmute(lasx_xvinsve0_d::<3>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -9318,7 +10986,7 @@ unsafe fn test_lasx_xvpickve_w() { ); let r = i64x4::new(1138467779, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvpickve_w::<2>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvpickve_w::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9331,7 +10999,7 @@ unsafe fn test_lasx_xvpickve_d() { ); let r = i64x4::new(8402618222187512066, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvpickve_d::<0>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvpickve_d::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9346,7 +11014,13 @@ unsafe fn test_lasx_xvssrlrn_b_h() { ); let r = i64x4::new(3463408299017240959, 0, 35748968851799935, 0); - assert_eq!(r, transmute(lasx_xvssrlrn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrlrn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9373,7 +11047,13 @@ unsafe fn test_lasx_xvssrlrn_h_w() { ); let r = i64x4::new(422210317549567, 0, 11259106657337343, 0); - assert_eq!(r, transmute(lasx_xvssrlrn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrlrn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9392,7 +11072,13 @@ unsafe fn test_lasx_xvssrlrn_w_d() { ); let r = i64x4::new(33428474336875, 0, 9223372034707292159, 0); - assert_eq!(r, transmute(lasx_xvssrlrn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrlrn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9407,7 +11093,13 @@ unsafe fn test_lasx_xvssrln_b_h() { ); let r = i64x4::new(657383790217428863, 0, 941881790371430152, 0); - assert_eq!(r, transmute(lasx_xvssrln_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrln_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9434,7 +11126,13 @@ unsafe fn test_lasx_xvssrln_h_w() { ); let r = i64x4::new(9223103287866884105, 0, 1696871892814295669, 0); - assert_eq!(r, transmute(lasx_xvssrln_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrln_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9453,7 +11151,13 @@ unsafe fn test_lasx_xvssrln_w_d() { ); let r = i64x4::new(3937140138060021759, 0, 9223372034707292159, 0); - assert_eq!(r, transmute(lasx_xvssrln_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrln_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9473,7 +11177,13 @@ unsafe fn test_lasx_xvorn_v() { -126121887133672977, ); - assert_eq!(r, transmute(lasx_xvorn_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvorn_v( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9521,7 +11231,7 @@ unsafe fn test_lasx_xvstx() { -4162173646616256791, ); - lasx_xvstx(transmute(a), o.as_mut_ptr(), 0); + lasx_xvstx(black_box(transmute(a)), o.as_mut_ptr(), 0); assert_eq!(r, transmute(o)); } @@ -9535,7 +11245,7 @@ unsafe fn test_lasx_xvextl_qu_du() { ); let r = i64x4::new(-5083351180651141737, 0, 4121325568380818738, 0); - assert_eq!(r, transmute(lasx_xvextl_qu_du(transmute(a)))); + assert_eq!(r, transmute(lasx_xvextl_qu_du(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9559,7 +11269,7 @@ unsafe fn test_lasx_xvinsgr2vr_w() { assert_eq!( r, - transmute(lasx_xvinsgr2vr_w::<4>(transmute(a), -596457645)) + transmute(lasx_xvinsgr2vr_w::<4>(black_box(transmute(a)), -596457645)) ); } @@ -9580,7 +11290,7 @@ unsafe fn test_lasx_xvinsgr2vr_d() { assert_eq!( r, - transmute(lasx_xvinsgr2vr_d::<3>(transmute(a), -1262509914)) + transmute(lasx_xvinsgr2vr_d::<3>(black_box(transmute(a)), -1262509914)) ); } @@ -9597,7 +11307,7 @@ unsafe fn test_lasx_xvreplve0_b() { 3472328296227680304, ); - assert_eq!(r, transmute(lasx_xvreplve0_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvreplve0_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9613,7 +11323,7 @@ unsafe fn test_lasx_xvreplve0_h() { 115969459958317468, ); - assert_eq!(r, transmute(lasx_xvreplve0_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvreplve0_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9635,7 +11345,7 @@ unsafe fn test_lasx_xvreplve0_w() { 5341799334363128369, ); - assert_eq!(r, transmute(lasx_xvreplve0_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvreplve0_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9653,7 +11363,7 @@ unsafe fn test_lasx_xvreplve0_d() { -7669512117913941619, ); - assert_eq!(r, transmute(lasx_xvreplve0_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvreplve0_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9669,7 +11379,7 @@ unsafe fn test_lasx_xvreplve0_q() { -7451765666000961269, ); - assert_eq!(r, transmute(lasx_xvreplve0_q(transmute(a)))); + assert_eq!(r, transmute(lasx_xvreplve0_q(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9685,7 +11395,7 @@ unsafe fn test_lasx_vext2xv_h_b() { 24207148650070059, ); - assert_eq!(r, transmute(lasx_vext2xv_h_b(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_h_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9701,7 +11411,7 @@ unsafe fn test_lasx_vext2xv_w_h() { -34359738358622, ); - assert_eq!(r, transmute(lasx_vext2xv_w_h(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_w_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9718,7 +11428,7 @@ unsafe fn test_lasx_vext2xv_d_w() { ); let r = i64x4::new(-585251458, -2113345963, -1846838006, -474453663); - assert_eq!(r, transmute(lasx_vext2xv_d_w(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_d_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9729,7 +11439,7 @@ unsafe fn test_lasx_vext2xv_w_b() { ); let r = i64x4::new(-240518168540, -528280977282, 30064770965, -489626271740); - assert_eq!(r, transmute(lasx_vext2xv_w_b(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_w_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9740,7 +11450,7 @@ unsafe fn test_lasx_vext2xv_d_h() { ); let r = i64x4::new(28568, -25911, 12053, -2728); - assert_eq!(r, transmute(lasx_vext2xv_d_h(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_d_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9751,7 +11461,7 @@ unsafe fn test_lasx_vext2xv_d_b() { ); let r = i64x4::new(18, 112, -36, -67); - assert_eq!(r, transmute(lasx_vext2xv_d_b(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_d_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9767,7 +11477,7 @@ unsafe fn test_lasx_vext2xv_hu_bu() { 16888898041348298, ); - assert_eq!(r, transmute(lasx_vext2xv_hu_bu(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_hu_bu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9783,7 +11493,7 @@ unsafe fn test_lasx_vext2xv_wu_hu() { 225172250484459, ); - assert_eq!(r, transmute(lasx_vext2xv_wu_hu(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_wu_hu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9800,7 +11510,7 @@ unsafe fn test_lasx_vext2xv_du_wu() { ); let r = i64x4::new(4027501046, 3358638690, 2495633600, 1035808674); - assert_eq!(r, transmute(lasx_vext2xv_du_wu(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_du_wu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9811,7 +11521,7 @@ unsafe fn test_lasx_vext2xv_wu_bu() { ); let r = i64x4::new(987842478134, 481036337184, 266287972487, 979252543649); - assert_eq!(r, transmute(lasx_vext2xv_wu_bu(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_wu_bu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9822,7 +11532,7 @@ unsafe fn test_lasx_vext2xv_du_hu() { ); let r = i64x4::new(61301, 41410, 35355, 19598); - assert_eq!(r, transmute(lasx_vext2xv_du_hu(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_du_hu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9833,7 +11543,7 @@ unsafe fn test_lasx_vext2xv_du_bu() { ); let r = i64x4::new(69, 25, 36, 204); - assert_eq!(r, transmute(lasx_vext2xv_du_bu(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_du_bu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9855,7 +11565,10 @@ unsafe fn test_lasx_xvpermi_q() { assert_eq!( r, - transmute(lasx_xvpermi_q::<49>(transmute(a), transmute(b))) + transmute(lasx_xvpermi_q::<49>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -9874,7 +11587,7 @@ unsafe fn test_lasx_xvpermi_d() { 1609032298240495217, ); - assert_eq!(r, transmute(lasx_xvpermi_d::<137>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvpermi_d::<137>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9900,7 +11613,13 @@ unsafe fn test_lasx_xvperm_w() { -3042141963630030871, ); - assert_eq!(r, transmute(lasx_xvperm_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvperm_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9981,7 +11700,10 @@ unsafe fn test_lasx_xvpickve2gr_w() { ); let r: i32 = 1367768596; - assert_eq!(r, transmute(lasx_xvpickve2gr_w::<4>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvpickve2gr_w::<4>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -9998,7 +11720,10 @@ unsafe fn test_lasx_xvpickve2gr_wu() { ); let r: u32 = 3194994707; - assert_eq!(r, transmute(lasx_xvpickve2gr_wu::<7>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvpickve2gr_wu::<7>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -10011,7 +11736,10 @@ unsafe fn test_lasx_xvpickve2gr_d() { ); let r: i64 = 6739870851682505277; - assert_eq!(r, transmute(lasx_xvpickve2gr_d::<2>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvpickve2gr_d::<2>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -10024,7 +11752,10 @@ unsafe fn test_lasx_xvpickve2gr_du() { ); let r: u64 = 9525833175373449635; - assert_eq!(r, transmute(lasx_xvpickve2gr_du::<3>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvpickve2gr_du::<3>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -10043,7 +11774,13 @@ unsafe fn test_lasx_xvaddwev_q_d() { ); let r = i64x4::new(-7472750192138786681, -1, -7758725841623301722, -1); - assert_eq!(r, transmute(lasx_xvaddwev_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10070,7 +11807,13 @@ unsafe fn test_lasx_xvaddwev_d_w() { ); let r = i64x4::new(614980351, -1946929141, -3309402607, -619077207); - assert_eq!(r, transmute(lasx_xvaddwev_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10090,7 +11833,13 @@ unsafe fn test_lasx_xvaddwev_w_h() { -232787227420502, ); - assert_eq!(r, transmute(lasx_xvaddwev_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10110,7 +11859,13 @@ unsafe fn test_lasx_xvaddwev_h_b() { -10414449598922739, ); - assert_eq!(r, transmute(lasx_xvaddwev_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10129,7 +11884,13 @@ unsafe fn test_lasx_xvaddwev_q_du() { ); let r = i64x4::new(4866121314102936184, 1, 898239984703082844, 1); - assert_eq!(r, transmute(lasx_xvaddwev_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10144,7 +11905,13 @@ unsafe fn test_lasx_xvaddwev_d_wu() { ); let r = i64x4::new(4001409528, 3398767892, 6021892971, 4349349069); - assert_eq!(r, transmute(lasx_xvaddwev_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10164,7 +11931,13 @@ unsafe fn test_lasx_xvaddwev_w_hu() { 376479653317006, ); - assert_eq!(r, transmute(lasx_xvaddwev_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10184,7 +11957,13 @@ unsafe fn test_lasx_xvaddwev_h_bu() { 68962872563859917, ); - assert_eq!(r, transmute(lasx_xvaddwev_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10203,7 +11982,13 @@ unsafe fn test_lasx_xvsubwev_q_d() { ); let r = i64x4::new(8183582659207736591, -1, 5496584216395980167, -1); - assert_eq!(r, transmute(lasx_xvsubwev_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10230,7 +12015,13 @@ unsafe fn test_lasx_xvsubwev_d_w() { ); let r = i64x4::new(-1945765730, 1700549847, -1218066002, -827282692); - assert_eq!(r, transmute(lasx_xvsubwev_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10250,7 +12041,13 @@ unsafe fn test_lasx_xvsubwev_w_h() { 217514323726817, ); - assert_eq!(r, transmute(lasx_xvsubwev_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10270,7 +12067,13 @@ unsafe fn test_lasx_xvsubwev_h_b() { -5910188531122352, ); - assert_eq!(r, transmute(lasx_xvsubwev_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10289,7 +12092,13 @@ unsafe fn test_lasx_xvsubwev_q_du() { ); let r = i64x4::new(-7180841769120666233, -1, -3901807980557405007, -1); - assert_eq!(r, transmute(lasx_xvsubwev_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10304,7 +12113,13 @@ unsafe fn test_lasx_xvsubwev_d_wu() { ); let r = i64x4::new(-2531041484, -1085343469, -1900376905, 1600829569); - assert_eq!(r, transmute(lasx_xvsubwev_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10324,7 +12139,13 @@ unsafe fn test_lasx_xvsubwev_w_hu() { -117029268872947, ); - assert_eq!(r, transmute(lasx_xvsubwev_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10344,7 +12165,13 @@ unsafe fn test_lasx_xvsubwev_h_bu() { -7035942402260810, ); - assert_eq!(r, transmute(lasx_xvsubwev_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10368,7 +12195,13 @@ unsafe fn test_lasx_xvmulwev_q_d() { -2723954123981949807, ); - assert_eq!(r, transmute(lasx_xvmulwev_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10400,7 +12233,13 @@ unsafe fn test_lasx_xvmulwev_d_w() { 904288373202150940, ); - assert_eq!(r, transmute(lasx_xvmulwev_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10420,7 +12259,13 @@ unsafe fn test_lasx_xvmulwev_w_h() { -218736636965849761, ); - assert_eq!(r, transmute(lasx_xvmulwev_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10440,7 +12285,13 @@ unsafe fn test_lasx_xvmulwev_h_b() { -532018857412992924, ); - assert_eq!(r, transmute(lasx_xvmulwev_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10464,7 +12315,13 @@ unsafe fn test_lasx_xvmulwev_q_du() { 1973424773030267173, ); - assert_eq!(r, transmute(lasx_xvmulwev_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10484,7 +12341,13 @@ unsafe fn test_lasx_xvmulwev_d_wu() { 312983850752328844, ); - assert_eq!(r, transmute(lasx_xvmulwev_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10504,7 +12367,13 @@ unsafe fn test_lasx_xvmulwev_w_hu() { -4803214827614038190, ); - assert_eq!(r, transmute(lasx_xvmulwev_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10524,7 +12393,13 @@ unsafe fn test_lasx_xvmulwev_h_bu() { 4458585836433706972, ); - assert_eq!(r, transmute(lasx_xvmulwev_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10543,7 +12418,13 @@ unsafe fn test_lasx_xvaddwod_q_d() { ); let r = i64x4::new(-3813723879058076957, 0, 200103109406722390, 0); - assert_eq!(r, transmute(lasx_xvaddwod_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10570,7 +12451,13 @@ unsafe fn test_lasx_xvaddwod_d_w() { ); let r = i64x4::new(3142724184, -2585235328, -785720463, 926940003); - assert_eq!(r, transmute(lasx_xvaddwod_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10590,7 +12477,13 @@ unsafe fn test_lasx_xvaddwod_w_h() { -148498494282599, ); - assert_eq!(r, transmute(lasx_xvaddwod_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10610,7 +12503,13 @@ unsafe fn test_lasx_xvaddwod_h_b() { -9570449863999416, ); - assert_eq!(r, transmute(lasx_xvaddwod_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10629,7 +12528,13 @@ unsafe fn test_lasx_xvaddwod_q_du() { ); let r = i64x4::new(751645223963476143, 1, -1275901335613508018, 0); - assert_eq!(r, transmute(lasx_xvaddwod_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10644,7 +12549,13 @@ unsafe fn test_lasx_xvaddwod_d_wu() { ); let r = i64x4::new(4757884041, 1673456593, 2162927615, 5143136401); - assert_eq!(r, transmute(lasx_xvaddwod_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10664,7 +12575,13 @@ unsafe fn test_lasx_xvaddwod_w_hu() { 248416613500221, ); - assert_eq!(r, transmute(lasx_xvaddwod_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10684,7 +12601,13 @@ unsafe fn test_lasx_xvaddwod_h_bu() { 83880238860075230, ); - assert_eq!(r, transmute(lasx_xvaddwod_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10703,7 +12626,13 @@ unsafe fn test_lasx_xvsubwod_q_d() { ); let r = i64x4::new(1764856097736252489, 0, 7683656878360999333, -1); - assert_eq!(r, transmute(lasx_xvsubwod_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10730,7 +12659,13 @@ unsafe fn test_lasx_xvsubwod_d_w() { ); let r = i64x4::new(-959924898, 7572903, 2106559810, 3976421257); - assert_eq!(r, transmute(lasx_xvsubwod_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10750,7 +12685,13 @@ unsafe fn test_lasx_xvsubwod_w_h() { -17665200524651, ); - assert_eq!(r, transmute(lasx_xvsubwod_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10770,7 +12711,13 @@ unsafe fn test_lasx_xvsubwod_h_b() { -3939721971105776, ); - assert_eq!(r, transmute(lasx_xvsubwod_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10789,7 +12736,13 @@ unsafe fn test_lasx_xvsubwod_q_du() { ); let r = i64x4::new(-6069526046627127478, -1, -1804068722113556285, -1); - assert_eq!(r, transmute(lasx_xvsubwod_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwod_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10804,8 +12757,14 @@ unsafe fn test_lasx_xvsubwod_d_wu() { ); let r = i64x4::new(762157671, -772219478, -1655146846, -1402401592); - assert_eq!(r, transmute(lasx_xvsubwod_d_wu(transmute(a), transmute(b)))); -} + assert_eq!( + r, + transmute(lasx_xvsubwod_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); +} #[simd_test(enable = "lasx")] unsafe fn test_lasx_xvsubwod_w_hu() { @@ -10824,7 +12783,13 @@ unsafe fn test_lasx_xvsubwod_w_hu() { 164866614644743, ); - assert_eq!(r, transmute(lasx_xvsubwod_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwod_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10844,7 +12809,13 @@ unsafe fn test_lasx_xvsubwod_h_bu() { -280740536975491, ); - assert_eq!(r, transmute(lasx_xvsubwod_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwod_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10868,7 +12839,13 @@ unsafe fn test_lasx_xvmulwod_q_d() { -113061080830775254, ); - assert_eq!(r, transmute(lasx_xvmulwod_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10900,7 +12877,13 @@ unsafe fn test_lasx_xvmulwod_d_w() { -1334126209007208500, ); - assert_eq!(r, transmute(lasx_xvmulwod_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10920,7 +12903,13 @@ unsafe fn test_lasx_xvmulwod_w_h() { 337273560374881751, ); - assert_eq!(r, transmute(lasx_xvmulwod_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10940,7 +12929,13 @@ unsafe fn test_lasx_xvmulwod_h_b() { -797714991416606612, ); - assert_eq!(r, transmute(lasx_xvmulwod_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10964,7 +12959,13 @@ unsafe fn test_lasx_xvmulwod_q_du() { -6864651532066967840, ); - assert_eq!(r, transmute(lasx_xvmulwod_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10984,7 +12985,13 @@ unsafe fn test_lasx_xvmulwod_d_wu() { 170736982952013264, ); - assert_eq!(r, transmute(lasx_xvmulwod_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -11004,7 +13011,13 @@ unsafe fn test_lasx_xvmulwod_w_hu() { 648970298882764352, ); - assert_eq!(r, transmute(lasx_xvmulwod_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -11024,7 +13037,13 @@ unsafe fn test_lasx_xvmulwod_h_bu() { 861263883582730760, ); - assert_eq!(r, transmute(lasx_xvmulwod_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -11047,7 +13066,10 @@ unsafe fn test_lasx_xvaddwev_d_wu_w() { assert_eq!( r, - transmute(lasx_xvaddwev_d_wu_w(transmute(a), transmute(b))) + transmute(lasx_xvaddwev_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11070,7 +13092,10 @@ unsafe fn test_lasx_xvaddwev_w_hu_h() { assert_eq!( r, - transmute(lasx_xvaddwev_w_hu_h(transmute(a), transmute(b))) + transmute(lasx_xvaddwev_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11093,7 +13118,10 @@ unsafe fn test_lasx_xvaddwev_h_bu_b() { assert_eq!( r, - transmute(lasx_xvaddwev_h_bu_b(transmute(a), transmute(b))) + transmute(lasx_xvaddwev_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11122,7 +13150,10 @@ unsafe fn test_lasx_xvmulwev_d_wu_w() { assert_eq!( r, - transmute(lasx_xvmulwev_d_wu_w(transmute(a), transmute(b))) + transmute(lasx_xvmulwev_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11145,7 +13176,10 @@ unsafe fn test_lasx_xvmulwev_w_hu_h() { assert_eq!( r, - transmute(lasx_xvmulwev_w_hu_h(transmute(a), transmute(b))) + transmute(lasx_xvmulwev_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11168,7 +13202,10 @@ unsafe fn test_lasx_xvmulwev_h_bu_b() { assert_eq!( r, - transmute(lasx_xvmulwev_h_bu_b(transmute(a), transmute(b))) + transmute(lasx_xvmulwev_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11192,7 +13229,10 @@ unsafe fn test_lasx_xvaddwod_d_wu_w() { assert_eq!( r, - transmute(lasx_xvaddwod_d_wu_w(transmute(a), transmute(b))) + transmute(lasx_xvaddwod_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11215,7 +13255,10 @@ unsafe fn test_lasx_xvaddwod_w_hu_h() { assert_eq!( r, - transmute(lasx_xvaddwod_w_hu_h(transmute(a), transmute(b))) + transmute(lasx_xvaddwod_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11238,7 +13281,10 @@ unsafe fn test_lasx_xvaddwod_h_bu_b() { assert_eq!( r, - transmute(lasx_xvaddwod_h_bu_b(transmute(a), transmute(b))) + transmute(lasx_xvaddwod_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11267,7 +13313,10 @@ unsafe fn test_lasx_xvmulwod_d_wu_w() { assert_eq!( r, - transmute(lasx_xvmulwod_d_wu_w(transmute(a), transmute(b))) + transmute(lasx_xvmulwod_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11290,7 +13339,10 @@ unsafe fn test_lasx_xvmulwod_w_hu_h() { assert_eq!( r, - transmute(lasx_xvmulwod_w_hu_h(transmute(a), transmute(b))) + transmute(lasx_xvmulwod_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11313,7 +13365,10 @@ unsafe fn test_lasx_xvmulwod_h_bu_b() { assert_eq!( r, - transmute(lasx_xvmulwod_h_bu_b(transmute(a), transmute(b))) + transmute(lasx_xvmulwod_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11333,7 +13388,13 @@ unsafe fn test_lasx_xvhaddw_q_d() { ); let r = i64x4::new(7070440900316630840, -1, 4582440905924999074, 0); - assert_eq!(r, transmute(lasx_xvhaddw_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -11352,7 +13413,13 @@ unsafe fn test_lasx_xvhaddw_qu_du() { ); let r = i64x4::new(-6342973196760799579, 0, -6232960347008472572, 1); - assert_eq!(r, transmute(lasx_xvhaddw_qu_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_qu_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -11371,7 +13438,13 @@ unsafe fn test_lasx_xvhsubw_q_d() { ); let r = i64x4::new(5317548498597883842, 0, 6155348192460751216, -1); - assert_eq!(r, transmute(lasx_xvhsubw_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -11390,7 +13463,13 @@ unsafe fn test_lasx_xvhsubw_qu_du() { ); let r = i64x4::new(11053881530518619, 0, -1215853579082277290, -1); - assert_eq!(r, transmute(lasx_xvhsubw_qu_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_qu_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -11422,7 +13501,11 @@ unsafe fn test_lasx_xvmaddwev_q_d() { assert_eq!( r, - transmute(lasx_xvmaddwev_q_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11463,7 +13546,11 @@ unsafe fn test_lasx_xvmaddwev_d_w() { assert_eq!( r, - transmute(lasx_xvmaddwev_d_w(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11496,7 +13583,11 @@ unsafe fn test_lasx_xvmaddwev_w_h() { assert_eq!( r, - transmute(lasx_xvmaddwev_w_h(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11523,7 +13614,11 @@ unsafe fn test_lasx_xvmaddwev_h_b() { assert_eq!( r, - transmute(lasx_xvmaddwev_h_b(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11557,9 +13652,9 @@ unsafe fn test_lasx_xvmaddwev_q_du() { assert_eq!( r, transmute(lasx_xvmaddwev_q_du( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11590,9 +13685,9 @@ unsafe fn test_lasx_xvmaddwev_d_wu() { assert_eq!( r, transmute(lasx_xvmaddwev_d_wu( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11621,9 +13716,9 @@ unsafe fn test_lasx_xvmaddwev_w_hu() { assert_eq!( r, transmute(lasx_xvmaddwev_w_hu( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11652,9 +13747,9 @@ unsafe fn test_lasx_xvmaddwev_h_bu() { assert_eq!( r, transmute(lasx_xvmaddwev_h_bu( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11688,7 +13783,11 @@ unsafe fn test_lasx_xvmaddwod_q_d() { assert_eq!( r, - transmute(lasx_xvmaddwod_q_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11729,7 +13828,11 @@ unsafe fn test_lasx_xvmaddwod_d_w() { assert_eq!( r, - transmute(lasx_xvmaddwod_d_w(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11762,7 +13865,11 @@ unsafe fn test_lasx_xvmaddwod_w_h() { assert_eq!( r, - transmute(lasx_xvmaddwod_w_h(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11789,7 +13896,11 @@ unsafe fn test_lasx_xvmaddwod_h_b() { assert_eq!( r, - transmute(lasx_xvmaddwod_h_b(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11823,9 +13934,9 @@ unsafe fn test_lasx_xvmaddwod_q_du() { assert_eq!( r, transmute(lasx_xvmaddwod_q_du( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11856,9 +13967,9 @@ unsafe fn test_lasx_xvmaddwod_d_wu() { assert_eq!( r, transmute(lasx_xvmaddwod_d_wu( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11887,9 +13998,9 @@ unsafe fn test_lasx_xvmaddwod_w_hu() { assert_eq!( r, transmute(lasx_xvmaddwod_w_hu( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11918,9 +14029,9 @@ unsafe fn test_lasx_xvmaddwod_h_bu() { assert_eq!( r, transmute(lasx_xvmaddwod_h_bu( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11955,9 +14066,9 @@ unsafe fn test_lasx_xvmaddwev_q_du_d() { assert_eq!( r, transmute(lasx_xvmaddwev_q_du_d( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11994,9 +14105,9 @@ unsafe fn test_lasx_xvmaddwev_d_wu_w() { assert_eq!( r, transmute(lasx_xvmaddwev_d_wu_w( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -12031,9 +14142,9 @@ unsafe fn test_lasx_xvmaddwev_w_hu_h() { assert_eq!( r, transmute(lasx_xvmaddwev_w_hu_h( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -12062,9 +14173,9 @@ unsafe fn test_lasx_xvmaddwev_h_bu_b() { assert_eq!( r, transmute(lasx_xvmaddwev_h_bu_b( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -12099,9 +14210,9 @@ unsafe fn test_lasx_xvmaddwod_q_du_d() { assert_eq!( r, transmute(lasx_xvmaddwod_q_du_d( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -12138,9 +14249,9 @@ unsafe fn test_lasx_xvmaddwod_d_wu_w() { assert_eq!( r, transmute(lasx_xvmaddwod_d_wu_w( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -12169,9 +14280,9 @@ unsafe fn test_lasx_xvmaddwod_w_hu_h() { assert_eq!( r, transmute(lasx_xvmaddwod_w_hu_h( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -12200,9 +14311,9 @@ unsafe fn test_lasx_xvmaddwod_h_bu_b() { assert_eq!( r, transmute(lasx_xvmaddwod_h_bu_b( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -12224,7 +14335,13 @@ unsafe fn test_lasx_xvrotr_b() { 5842271601646106402, ); - assert_eq!(r, transmute(lasx_xvrotr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvrotr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -12244,7 +14361,13 @@ unsafe fn test_lasx_xvrotr_h() { 8109266518466894464, ); - assert_eq!(r, transmute(lasx_xvrotr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvrotr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -12264,7 +14387,13 @@ unsafe fn test_lasx_xvrotr_w() { 8567937817891640092, ); - assert_eq!(r, transmute(lasx_xvrotr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvrotr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -12288,7 +14417,13 @@ unsafe fn test_lasx_xvrotr_d() { 4254025119287920211, ); - assert_eq!(r, transmute(lasx_xvrotr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvrotr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -12312,7 +14447,13 @@ unsafe fn test_lasx_xvadd_q() { 1706530784161666452, ); - assert_eq!(r, transmute(lasx_xvadd_q(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadd_q( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -12336,7 +14477,13 @@ unsafe fn test_lasx_xvsub_q() { 1242748497994781383, ); - assert_eq!(r, transmute(lasx_xvsub_q(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsub_q( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -12357,7 +14504,10 @@ unsafe fn test_lasx_xvaddwev_q_du_d() { assert_eq!( r, - transmute(lasx_xvaddwev_q_du_d(transmute(a), transmute(b))) + transmute(lasx_xvaddwev_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12379,7 +14529,10 @@ unsafe fn test_lasx_xvaddwod_q_du_d() { assert_eq!( r, - transmute(lasx_xvaddwod_q_du_d(transmute(a), transmute(b))) + transmute(lasx_xvaddwod_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12406,7 +14559,10 @@ unsafe fn test_lasx_xvmulwev_q_du_d() { assert_eq!( r, - transmute(lasx_xvmulwev_q_du_d(transmute(a), transmute(b))) + transmute(lasx_xvmulwev_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12433,7 +14589,10 @@ unsafe fn test_lasx_xvmulwod_q_du_d() { assert_eq!( r, - transmute(lasx_xvmulwod_q_du_d(transmute(a), transmute(b))) + transmute(lasx_xvmulwod_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12445,7 +14604,7 @@ unsafe fn test_lasx_xvmskgez_b() { ); let r = i64x4::new(13289, 0, 4927, 0); - assert_eq!(r, transmute(lasx_xvmskgez_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmskgez_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12456,7 +14615,7 @@ unsafe fn test_lasx_xvmsknz_b() { ); let r = i64x4::new(65535, 0, 65535, 0); - assert_eq!(r, transmute(lasx_xvmsknz_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmsknz_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12472,7 +14631,7 @@ unsafe fn test_lasx_xvexth_h_b() { -1689051729887256, ); - assert_eq!(r, transmute(lasx_xvexth_h_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_h_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12488,7 +14647,7 @@ unsafe fn test_lasx_xvexth_w_h() { -117171002791439, ); - assert_eq!(r, transmute(lasx_xvexth_w_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_w_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12505,7 +14664,7 @@ unsafe fn test_lasx_xvexth_d_w() { ); let r = i64x4::new(78514216, -1063299454, -1487536177, 1875317589); - assert_eq!(r, transmute(lasx_xvexth_d_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_d_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12518,7 +14677,7 @@ unsafe fn test_lasx_xvexth_q_d() { ); let r = i64x4::new(5196480214883180720, 0, 7776492634988202392, 0); - assert_eq!(r, transmute(lasx_xvexth_q_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_q_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12534,7 +14693,7 @@ unsafe fn test_lasx_xvexth_hu_bu() { 11259067788754993, ); - assert_eq!(r, transmute(lasx_xvexth_hu_bu(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_hu_bu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12550,7 +14709,7 @@ unsafe fn test_lasx_xvexth_wu_hu() { 211376815493177, ); - assert_eq!(r, transmute(lasx_xvexth_wu_hu(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_wu_hu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12561,7 +14720,7 @@ unsafe fn test_lasx_xvexth_du_wu() { ); let r = i64x4::new(3486710391, 717721410, 1954296323, 1406265475); - assert_eq!(r, transmute(lasx_xvexth_du_wu(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_du_wu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12574,7 +14733,7 @@ unsafe fn test_lasx_xvexth_qu_du() { ); let r = i64x4::new(6305760528044738869, 0, 3857202168052068182, 0); - assert_eq!(r, transmute(lasx_xvexth_qu_du(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_qu_du(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12590,7 +14749,7 @@ unsafe fn test_lasx_xvrotri_b() { -3500418816657076903, ); - assert_eq!(r, transmute(lasx_xvrotri_b::<4>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvrotri_b::<4>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12606,7 +14765,7 @@ unsafe fn test_lasx_xvrotri_h() { 4779464405959485451, ); - assert_eq!(r, transmute(lasx_xvrotri_h::<15>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvrotri_h::<15>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12628,7 +14787,7 @@ unsafe fn test_lasx_xvrotri_w() { -1679179889808014898, ); - assert_eq!(r, transmute(lasx_xvrotri_w::<11>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvrotri_w::<11>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12646,7 +14805,7 @@ unsafe fn test_lasx_xvrotri_d() { -7958311692822812825, ); - assert_eq!(r, transmute(lasx_xvrotri_d::<16>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvrotri_d::<16>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12659,7 +14818,7 @@ unsafe fn test_lasx_xvextl_q_d() { ); let r = i64x4::new(-4167783494125842132, -1, 7476993593286219399, 0); - assert_eq!(r, transmute(lasx_xvextl_q_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvextl_q_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12681,7 +14840,10 @@ unsafe fn test_lasx_xvsrlni_b_h() { assert_eq!( r, - transmute(lasx_xvsrlni_b_h::<4>(transmute(a), transmute(b))) + transmute(lasx_xvsrlni_b_h::<4>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12704,7 +14866,10 @@ unsafe fn test_lasx_xvsrlni_h_w() { assert_eq!( r, - transmute(lasx_xvsrlni_h_w::<16>(transmute(a), transmute(b))) + transmute(lasx_xvsrlni_h_w::<16>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12739,7 +14904,10 @@ unsafe fn test_lasx_xvsrlni_w_d() { assert_eq!( r, - transmute(lasx_xvsrlni_w_d::<26>(transmute(a), transmute(b))) + transmute(lasx_xvsrlni_w_d::<26>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12761,7 +14929,10 @@ unsafe fn test_lasx_xvsrlni_d_q() { assert_eq!( r, - transmute(lasx_xvsrlni_d_q::<102>(transmute(a), transmute(b))) + transmute(lasx_xvsrlni_d_q::<102>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12784,7 +14955,10 @@ unsafe fn test_lasx_xvsrlrni_b_h() { assert_eq!( r, - transmute(lasx_xvsrlrni_b_h::<8>(transmute(a), transmute(b))) + transmute(lasx_xvsrlrni_b_h::<8>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12807,7 +14981,10 @@ unsafe fn test_lasx_xvsrlrni_h_w() { assert_eq!( r, - transmute(lasx_xvsrlrni_h_w::<5>(transmute(a), transmute(b))) + transmute(lasx_xvsrlrni_h_w::<5>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12842,7 +15019,10 @@ unsafe fn test_lasx_xvsrlrni_w_d() { assert_eq!( r, - transmute(lasx_xvsrlrni_w_d::<43>(transmute(a), transmute(b))) + transmute(lasx_xvsrlrni_w_d::<43>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12864,7 +15044,10 @@ unsafe fn test_lasx_xvsrlrni_d_q() { assert_eq!( r, - transmute(lasx_xvsrlrni_d_q::<126>(transmute(a), transmute(b))) + transmute(lasx_xvsrlrni_d_q::<126>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12887,7 +15070,10 @@ unsafe fn test_lasx_xvssrlni_b_h() { assert_eq!( r, - transmute(lasx_xvssrlni_b_h::<4>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_b_h::<4>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12905,7 +15091,10 @@ unsafe fn test_lasx_xvssrlni_h_w() { assert_eq!( r, - transmute(lasx_xvssrlni_h_w::<31>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_h_w::<31>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12940,7 +15129,10 @@ unsafe fn test_lasx_xvssrlni_w_d() { assert_eq!( r, - transmute(lasx_xvssrlni_w_d::<14>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_w_d::<14>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12967,7 +15159,10 @@ unsafe fn test_lasx_xvssrlni_d_q() { assert_eq!( r, - transmute(lasx_xvssrlni_d_q::<35>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_d_q::<35>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12990,7 +15185,10 @@ unsafe fn test_lasx_xvssrlni_bu_h() { assert_eq!( r, - transmute(lasx_xvssrlni_bu_h::<11>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_bu_h::<11>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13008,7 +15206,10 @@ unsafe fn test_lasx_xvssrlni_hu_w() { assert_eq!( r, - transmute(lasx_xvssrlni_hu_w::<31>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_hu_w::<31>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13032,7 +15233,10 @@ unsafe fn test_lasx_xvssrlni_wu_d() { assert_eq!( r, - transmute(lasx_xvssrlni_wu_d::<24>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_wu_d::<24>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13054,7 +15258,10 @@ unsafe fn test_lasx_xvssrlni_du_q() { assert_eq!( r, - transmute(lasx_xvssrlni_du_q::<109>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_du_q::<109>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13077,7 +15284,10 @@ unsafe fn test_lasx_xvssrlrni_b_h() { assert_eq!( r, - transmute(lasx_xvssrlrni_b_h::<7>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_b_h::<7>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13100,7 +15310,10 @@ unsafe fn test_lasx_xvssrlrni_h_w() { assert_eq!( r, - transmute(lasx_xvssrlrni_h_w::<11>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_h_w::<11>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13135,7 +15348,10 @@ unsafe fn test_lasx_xvssrlrni_w_d() { assert_eq!( r, - transmute(lasx_xvssrlrni_w_d::<27>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_w_d::<27>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13157,7 +15373,10 @@ unsafe fn test_lasx_xvssrlrni_d_q() { assert_eq!( r, - transmute(lasx_xvssrlrni_d_q::<94>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_d_q::<94>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13175,7 +15394,10 @@ unsafe fn test_lasx_xvssrlrni_bu_h() { assert_eq!( r, - transmute(lasx_xvssrlrni_bu_h::<4>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_bu_h::<4>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13198,7 +15420,10 @@ unsafe fn test_lasx_xvssrlrni_hu_w() { assert_eq!( r, - transmute(lasx_xvssrlrni_hu_w::<16>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_hu_w::<16>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13227,7 +15452,10 @@ unsafe fn test_lasx_xvssrlrni_wu_d() { assert_eq!( r, - transmute(lasx_xvssrlrni_wu_d::<50>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_wu_d::<50>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13249,7 +15477,10 @@ unsafe fn test_lasx_xvssrlrni_du_q() { assert_eq!( r, - transmute(lasx_xvssrlrni_du_q::<53>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_du_q::<53>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13272,7 +15503,10 @@ unsafe fn test_lasx_xvsrani_b_h() { assert_eq!( r, - transmute(lasx_xvsrani_b_h::<8>(transmute(a), transmute(b))) + transmute(lasx_xvsrani_b_h::<8>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13295,7 +15529,10 @@ unsafe fn test_lasx_xvsrani_h_w() { assert_eq!( r, - transmute(lasx_xvsrani_h_w::<0>(transmute(a), transmute(b))) + transmute(lasx_xvsrani_h_w::<0>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13330,7 +15567,10 @@ unsafe fn test_lasx_xvsrani_w_d() { assert_eq!( r, - transmute(lasx_xvsrani_w_d::<28>(transmute(a), transmute(b))) + transmute(lasx_xvsrani_w_d::<28>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13357,7 +15597,10 @@ unsafe fn test_lasx_xvsrani_d_q() { assert_eq!( r, - transmute(lasx_xvsrani_d_q::<66>(transmute(a), transmute(b))) + transmute(lasx_xvsrani_d_q::<66>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13380,7 +15623,10 @@ unsafe fn test_lasx_xvsrarni_b_h() { assert_eq!( r, - transmute(lasx_xvsrarni_b_h::<4>(transmute(a), transmute(b))) + transmute(lasx_xvsrarni_b_h::<4>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13403,7 +15649,10 @@ unsafe fn test_lasx_xvsrarni_h_w() { assert_eq!( r, - transmute(lasx_xvsrarni_h_w::<9>(transmute(a), transmute(b))) + transmute(lasx_xvsrarni_h_w::<9>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13427,7 +15676,10 @@ unsafe fn test_lasx_xvsrarni_w_d() { assert_eq!( r, - transmute(lasx_xvsrarni_w_d::<63>(transmute(a), transmute(b))) + transmute(lasx_xvsrarni_w_d::<63>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13449,7 +15701,10 @@ unsafe fn test_lasx_xvsrarni_d_q() { assert_eq!( r, - transmute(lasx_xvsrarni_d_q::<102>(transmute(a), transmute(b))) + transmute(lasx_xvsrarni_d_q::<102>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13472,7 +15727,10 @@ unsafe fn test_lasx_xvssrani_b_h() { assert_eq!( r, - transmute(lasx_xvssrani_b_h::<5>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_b_h::<5>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13495,7 +15753,10 @@ unsafe fn test_lasx_xvssrani_h_w() { assert_eq!( r, - transmute(lasx_xvssrani_h_w::<0>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_h_w::<0>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13530,7 +15791,10 @@ unsafe fn test_lasx_xvssrani_w_d() { assert_eq!( r, - transmute(lasx_xvssrani_w_d::<45>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_w_d::<45>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13557,7 +15821,10 @@ unsafe fn test_lasx_xvssrani_d_q() { assert_eq!( r, - transmute(lasx_xvssrani_d_q::<73>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_d_q::<73>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13575,7 +15842,10 @@ unsafe fn test_lasx_xvssrani_bu_h() { assert_eq!( r, - transmute(lasx_xvssrani_bu_h::<12>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_bu_h::<12>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13593,7 +15863,10 @@ unsafe fn test_lasx_xvssrani_hu_w() { assert_eq!( r, - transmute(lasx_xvssrani_hu_w::<9>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_hu_w::<9>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13617,7 +15890,10 @@ unsafe fn test_lasx_xvssrani_wu_d() { assert_eq!( r, - transmute(lasx_xvssrani_wu_d::<42>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_wu_d::<42>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13639,7 +15915,10 @@ unsafe fn test_lasx_xvssrani_du_q() { assert_eq!( r, - transmute(lasx_xvssrani_du_q::<115>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_du_q::<115>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13662,7 +15941,10 @@ unsafe fn test_lasx_xvssrarni_b_h() { assert_eq!( r, - transmute(lasx_xvssrarni_b_h::<6>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_b_h::<6>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13685,7 +15967,10 @@ unsafe fn test_lasx_xvssrarni_h_w() { assert_eq!( r, - transmute(lasx_xvssrarni_h_w::<25>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_h_w::<25>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13715,7 +16000,10 @@ unsafe fn test_lasx_xvssrarni_w_d() { assert_eq!( r, - transmute(lasx_xvssrarni_w_d::<61>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_w_d::<61>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13737,7 +16025,10 @@ unsafe fn test_lasx_xvssrarni_d_q() { assert_eq!( r, - transmute(lasx_xvssrarni_d_q::<123>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_d_q::<123>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13760,7 +16051,10 @@ unsafe fn test_lasx_xvssrarni_bu_h() { assert_eq!( r, - transmute(lasx_xvssrarni_bu_h::<10>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_bu_h::<10>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13778,7 +16072,10 @@ unsafe fn test_lasx_xvssrarni_hu_w() { assert_eq!( r, - transmute(lasx_xvssrarni_hu_w::<30>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_hu_w::<30>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13802,7 +16099,10 @@ unsafe fn test_lasx_xvssrarni_wu_d() { assert_eq!( r, - transmute(lasx_xvssrarni_wu_d::<61>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_wu_d::<61>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13824,7 +16124,10 @@ unsafe fn test_lasx_xvssrarni_du_q() { assert_eq!( r, - transmute(lasx_xvssrarni_du_q::<15>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_du_q::<15>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13836,7 +16139,7 @@ unsafe fn test_lasx_xbnz_b() { ); let r: i32 = 1; - assert_eq!(r, transmute(lasx_xbnz_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xbnz_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13849,7 +16152,7 @@ unsafe fn test_lasx_xbnz_d() { ); let r: i32 = 1; - assert_eq!(r, transmute(lasx_xbnz_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xbnz_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13860,7 +16163,7 @@ unsafe fn test_lasx_xbnz_h() { ); let r: i32 = 1; - assert_eq!(r, transmute(lasx_xbnz_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xbnz_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13871,7 +16174,7 @@ unsafe fn test_lasx_xbnz_v() { ); let r: i32 = 1; - assert_eq!(r, transmute(lasx_xbnz_v(transmute(a)))); + assert_eq!(r, transmute(lasx_xbnz_v(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13882,7 +16185,7 @@ unsafe fn test_lasx_xbnz_w() { ); let r: i32 = 1; - assert_eq!(r, transmute(lasx_xbnz_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xbnz_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13893,7 +16196,7 @@ unsafe fn test_lasx_xbz_b() { ); let r: i32 = 0; - assert_eq!(r, transmute(lasx_xbz_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xbz_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13906,7 +16209,7 @@ unsafe fn test_lasx_xbz_d() { ); let r: i32 = 0; - assert_eq!(r, transmute(lasx_xbz_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xbz_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13917,7 +16220,7 @@ unsafe fn test_lasx_xbz_h() { ); let r: i32 = 0; - assert_eq!(r, transmute(lasx_xbz_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xbz_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13928,7 +16231,7 @@ unsafe fn test_lasx_xbz_v() { ); let r: i32 = 0; - assert_eq!(r, transmute(lasx_xbz_v(transmute(a)))); + assert_eq!(r, transmute(lasx_xbz_v(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13939,7 +16242,7 @@ unsafe fn test_lasx_xbz_w() { ); let r: i32 = 0; - assert_eq!(r, transmute(lasx_xbz_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xbz_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13958,7 +16261,13 @@ unsafe fn test_lasx_xvfcmp_caf_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_caf_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_caf_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -13973,7 +16282,13 @@ unsafe fn test_lasx_xvfcmp_caf_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_caf_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_caf_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -13992,7 +16307,13 @@ unsafe fn test_lasx_xvfcmp_ceq_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_ceq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_ceq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14007,7 +16328,13 @@ unsafe fn test_lasx_xvfcmp_ceq_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_ceq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_ceq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14026,7 +16353,13 @@ unsafe fn test_lasx_xvfcmp_cle_d() { ); let r = i64x4::new(-1, -1, -1, 0); - assert_eq!(r, transmute(lasx_xvfcmp_cle_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cle_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14041,7 +16374,13 @@ unsafe fn test_lasx_xvfcmp_cle_s() { ); let r = i64x4::new(0, -1, -1, -4294967296); - assert_eq!(r, transmute(lasx_xvfcmp_cle_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cle_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14060,7 +16399,13 @@ unsafe fn test_lasx_xvfcmp_clt_d() { ); let r = i64x4::new(0, -1, 0, -1); - assert_eq!(r, transmute(lasx_xvfcmp_clt_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_clt_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14075,7 +16420,13 @@ unsafe fn test_lasx_xvfcmp_clt_s() { ); let r = i64x4::new(-1, 4294967295, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_clt_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_clt_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14094,7 +16445,13 @@ unsafe fn test_lasx_xvfcmp_cne_d() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cne_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cne_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14109,7 +16466,13 @@ unsafe fn test_lasx_xvfcmp_cne_s() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cne_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cne_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14128,7 +16491,13 @@ unsafe fn test_lasx_xvfcmp_cor_d() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cor_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cor_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14143,7 +16512,13 @@ unsafe fn test_lasx_xvfcmp_cor_s() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cor_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cor_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14162,7 +16537,13 @@ unsafe fn test_lasx_xvfcmp_cueq_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_cueq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cueq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14177,7 +16558,13 @@ unsafe fn test_lasx_xvfcmp_cueq_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_cueq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cueq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14196,7 +16583,13 @@ unsafe fn test_lasx_xvfcmp_cule_d() { ); let r = i64x4::new(0, -1, -1, 0); - assert_eq!(r, transmute(lasx_xvfcmp_cule_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cule_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14211,7 +16604,13 @@ unsafe fn test_lasx_xvfcmp_cule_s() { ); let r = i64x4::new(-4294967296, 4294967295, 4294967295, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cule_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cule_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14230,7 +16629,13 @@ unsafe fn test_lasx_xvfcmp_cult_d() { ); let r = i64x4::new(0, -1, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_cult_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cult_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14245,7 +16650,13 @@ unsafe fn test_lasx_xvfcmp_cult_s() { ); let r = i64x4::new(-1, 0, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cult_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cult_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14264,7 +16675,13 @@ unsafe fn test_lasx_xvfcmp_cun_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_cun_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cun_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14283,7 +16700,13 @@ unsafe fn test_lasx_xvfcmp_cune_d() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cune_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cune_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14298,7 +16721,13 @@ unsafe fn test_lasx_xvfcmp_cune_s() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cune_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cune_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14313,7 +16742,13 @@ unsafe fn test_lasx_xvfcmp_cun_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_cun_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cun_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14332,7 +16767,13 @@ unsafe fn test_lasx_xvfcmp_saf_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_saf_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_saf_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14347,7 +16788,13 @@ unsafe fn test_lasx_xvfcmp_saf_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_saf_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_saf_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14366,7 +16813,13 @@ unsafe fn test_lasx_xvfcmp_seq_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_seq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_seq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14381,7 +16834,13 @@ unsafe fn test_lasx_xvfcmp_seq_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_seq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_seq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14400,7 +16859,13 @@ unsafe fn test_lasx_xvfcmp_sle_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sle_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sle_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14415,7 +16880,13 @@ unsafe fn test_lasx_xvfcmp_sle_s() { ); let r = i64x4::new(0, 4294967295, -1, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sle_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sle_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14434,7 +16905,13 @@ unsafe fn test_lasx_xvfcmp_slt_d() { ); let r = i64x4::new(0, -1, -1, 0); - assert_eq!(r, transmute(lasx_xvfcmp_slt_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_slt_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14449,7 +16926,13 @@ unsafe fn test_lasx_xvfcmp_slt_s() { ); let r = i64x4::new(0, -4294967296, 4294967295, -1); - assert_eq!(r, transmute(lasx_xvfcmp_slt_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_slt_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14468,7 +16951,13 @@ unsafe fn test_lasx_xvfcmp_sne_d() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_sne_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sne_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14483,7 +16972,13 @@ unsafe fn test_lasx_xvfcmp_sne_s() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_sne_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sne_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14502,7 +16997,13 @@ unsafe fn test_lasx_xvfcmp_sor_d() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_sor_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sor_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14517,7 +17018,13 @@ unsafe fn test_lasx_xvfcmp_sor_s() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_sor_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sor_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14536,7 +17043,13 @@ unsafe fn test_lasx_xvfcmp_sueq_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sueq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sueq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14551,7 +17064,13 @@ unsafe fn test_lasx_xvfcmp_sueq_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sueq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sueq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14570,7 +17089,13 @@ unsafe fn test_lasx_xvfcmp_sule_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sule_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sule_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14585,7 +17110,13 @@ unsafe fn test_lasx_xvfcmp_sule_s() { ); let r = i64x4::new(0, 4294967295, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sule_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sule_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14604,7 +17135,13 @@ unsafe fn test_lasx_xvfcmp_sult_d() { ); let r = i64x4::new(0, -1, 0, -1); - assert_eq!(r, transmute(lasx_xvfcmp_sult_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sult_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14619,7 +17156,13 @@ unsafe fn test_lasx_xvfcmp_sult_s() { ); let r = i64x4::new(-1, 4294967295, -1, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sult_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sult_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14638,7 +17181,13 @@ unsafe fn test_lasx_xvfcmp_sun_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sun_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sun_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14657,7 +17206,13 @@ unsafe fn test_lasx_xvfcmp_sune_d() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_sune_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sune_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14672,7 +17227,13 @@ unsafe fn test_lasx_xvfcmp_sune_s() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_sune_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sune_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14687,7 +17248,13 @@ unsafe fn test_lasx_xvfcmp_sun_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sun_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sun_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14700,7 +17267,10 @@ unsafe fn test_lasx_xvpickve_d_f() { ); let r = i64x4::new(4605596490350167974, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvpickve_d_f::<1>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvpickve_d_f::<1>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -14711,7 +17281,10 @@ unsafe fn test_lasx_xvpickve_w_f() { ); let r = i64x4::new(1040565756, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvpickve_w_f::<1>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvpickve_w_f::<1>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -14756,3 +17329,326 @@ unsafe fn test_lasx_xvrepli_w() { assert_eq!(r, transmute(lasx_xvrepli_w::<-388>())); } + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_cast_128_s() { + let a = u32x4::new(1031165056, 1051966120, 1060984374, 1062536919); + let r = i64x4::new(4518160082931176576, 4563561318958585398, 1966080, 1966080); + + assert_eq!( + r.as_array()[0..2], + transmute::<_, i64x4>(lasx_cast_128_s(black_box(transmute(a)))).as_array()[0..2] + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_cast_128_d() { + let a = u64x2::new(4604694967937271251, 4600904075476555984); + let r = i64x4::new( + 4604694967937271251, + 4600904075476555984, + 2910860781861170785, + 8314045306847701346, + ); + + assert_eq!( + r.as_array()[0..2], + transmute::<_, i64x4>(lasx_cast_128_d(black_box(transmute(a)))).as_array()[0..2] + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_cast_128() { + let a = i64x2::new(-5333716211868108402, 2442107533729495827); + let r = i64x4::new( + -5333716211868108402, + 2442107533729495827, + -1115824375586394527, + 8314045306157170687, + ); + + assert_eq!( + r.as_array()[0..2], + transmute::<_, i64x4>(lasx_cast_128(black_box(transmute(a)))).as_array()[0..2] + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_concat_128_s() { + let a = u32x4::new(1032255272, 1059413818, 1058434362, 1041454056); + let b = u32x4::new(1047296252, 1059191602, 1051282752, 1026847376); + let r = i64x4::new( + 4550147702272751400, + 4473011111864986938, + 4549193291835144444, + 4410275898954698048, + ); + + assert_eq!( + r, + transmute(lasx_concat_128_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_concat_128_d() { + let a = u64x2::new(4602341404117999960, 4599751584045405722); + let b = u64x2::new(4595947342927040984, 4600308396523102002); + let r = i64x4::new( + 4602341404117999960, + 4599751584045405722, + 4595947342927040984, + 4600308396523102002, + ); + + assert_eq!( + r, + transmute(lasx_concat_128_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_concat_128() { + let a = i64x2::new(3302609705743394573, 8438855426868306143); + let b = i64x2::new(8632034656150002181, 7751541408133090748); + let r = i64x4::new( + 3302609705743394573, + 8438855426868306143, + 8632034656150002181, + 7751541408133090748, + ); + + assert_eq!( + r, + transmute(lasx_concat_128( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_extract_128_lo_s() { + let a = u32x8::new( + 1038279272, 1053426270, 1062315532, 1055361088, 1061380448, 1052007748, 1063816577, + 1061671114, + ); + let r = i64x2::new(4524431379435545192, 4532741359493293580); + + assert_eq!(r, transmute(lasx_extract_128_lo_s(black_box(transmute(a))))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_extract_128_hi_s() { + let a = u32x8::new( + 1059517342, 1052723820, 1053176244, 1060336354, 1058221022, 1064684502, 1061072013, + 1059238420, + ); + let r = i64x2::new(4572785117706267614, 4549394373627784333); + + assert_eq!(r, transmute(lasx_extract_128_hi_s(black_box(transmute(a))))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_extract_128_lo_d() { + let a = u64x4::new( + 4606487981487128637, + 4592443779247846248, + 4605637448543526041, + 4604126872543611047, + ); + let r = i64x2::new(4606487981487128637, 4592443779247846248); + + assert_eq!(r, transmute(lasx_extract_128_lo_d(black_box(transmute(a))))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_extract_128_hi_d() { + let a = u64x4::new( + 4595075050683709816, + 4603388454656549851, + 4603881047625519227, + 4604218419306666352, + ); + let r = i64x2::new(4603881047625519227, 4604218419306666352); + + assert_eq!(r, transmute(lasx_extract_128_hi_d(black_box(transmute(a))))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_extract_128_lo() { + let a = i64x4::new( + 1690990426210778543, + -1056924033489771427, + 1791197928200737608, + 2648792885519901423, + ); + let r = i64x2::new(1690990426210778543, -1056924033489771427); + + assert_eq!(r, transmute(lasx_extract_128_lo(black_box(transmute(a))))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_extract_128_hi() { + let a = i64x4::new( + 1400282616691463341, + 6677577875527300174, + -1903780563362068813, + -7449796170151383489, + ); + let r = i64x2::new(-1903780563362068813, -7449796170151383489); + + assert_eq!(r, transmute(lasx_extract_128_hi(black_box(transmute(a))))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_insert_128_lo_s() { + let a = u32x8::new( + 1063338913, 1017815328, 1065051130, 1040694156, 1059596680, 1048796526, 1058020845, + 1057822131, + ); + let b = u32x4::new(1052930766, 1021556992, 1050709482, 1059704809); + let r = i64x4::new( + 4387553872693064398, + 4551397499119635946, + 4504546780388010376, + 4543311458688048621, + ); + + assert_eq!( + r, + transmute(lasx_insert_128_lo_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_insert_128_hi_s() { + let a = u32x8::new( + 1018863744, 1064221149, 1048659080, 1057450774, 1049935896, 1034170664, 1059759433, + 1057849762, + ); + let b = u32x4::new(1060332648, 1063149600, 1051087106, 1060582348); + let r = i64x4::new( + 4570795031685406848, + 4541716492508546184, + 4566192763815814248, + 4555166500425978114, + ); + + assert_eq!( + r, + transmute(lasx_insert_128_hi_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_insert_128_lo_d() { + let a = u64x4::new( + 4601319519422109044, + 4601506273633970188, + 4605118087882201940, + 4605125059076454256, + ); + let b = u64x2::new(4587489919640425888, 4591909120489567808); + let r = i64x4::new( + 4587489919640425888, + 4591909120489567808, + 4605118087882201940, + 4605125059076454256, + ); + + assert_eq!( + r, + transmute(lasx_insert_128_lo_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_insert_128_hi_d() { + let a = u64x4::new( + 4604690660177752777, + 4593824994203592700, + 4599958775071728504, + 4604125324674373728, + ); + let b = u64x2::new(4601718173474385938, 4591758028383494760); + let r = i64x4::new( + 4604690660177752777, + 4593824994203592700, + 4601718173474385938, + 4591758028383494760, + ); + + assert_eq!( + r, + transmute(lasx_insert_128_hi_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_insert_128_lo() { + let a = i64x4::new( + 8159968186698006293, + 5648210958959948409, + 603295919044368378, + -4396186135186039276, + ); + let b = i64x2::new(-6258666140812668387, 5822982556977506382); + let r = i64x4::new( + -6258666140812668387, + 5822982556977506382, + 603295919044368378, + -4396186135186039276, + ); + + assert_eq!( + r, + transmute(lasx_insert_128_lo( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_insert_128_hi() { + let a = i64x4::new( + 2981835982487038158, + 5258378092714202875, + 5115371338527125146, + -6993491475145500537, + ); + let b = i64x2::new(1176776599938765863, -7502655081590988207); + let r = i64x4::new( + 2981835982487038158, + 5258378092714202875, + 1176776599938765863, + -7502655081590988207, + ); + + assert_eq!( + r, + transmute(lasx_insert_128_hi( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); +} diff --git a/library/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs b/library/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs index 764e69ca05444..1542633a34b35 100644 --- a/library/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs +++ b/library/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs @@ -7,42 +7,10 @@ // ``` use crate::mem::transmute; -use super::types::*; +use super::super::*; #[allow(improper_ctypes)] unsafe extern "unadjusted" { - #[link_name = "llvm.loongarch.lsx.vsll.b"] - fn __lsx_vsll_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vsll.h"] - fn __lsx_vsll_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vsll.w"] - fn __lsx_vsll_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vsll.d"] - fn __lsx_vsll_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vslli.b"] - fn __lsx_vslli_b(a: __v16i8, b: u32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vslli.h"] - fn __lsx_vslli_h(a: __v8i16, b: u32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vslli.w"] - fn __lsx_vslli_w(a: __v4i32, b: u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vslli.d"] - fn __lsx_vslli_d(a: __v2i64, b: u32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vsra.b"] - fn __lsx_vsra_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vsra.h"] - fn __lsx_vsra_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vsra.w"] - fn __lsx_vsra_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vsra.d"] - fn __lsx_vsra_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vsrai.b"] - fn __lsx_vsrai_b(a: __v16i8, b: u32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vsrai.h"] - fn __lsx_vsrai_h(a: __v8i16, b: u32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vsrai.w"] - fn __lsx_vsrai_w(a: __v4i32, b: u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vsrai.d"] - fn __lsx_vsrai_d(a: __v2i64, b: u32) -> __v2i64; #[link_name = "llvm.loongarch.lsx.vsrar.b"] fn __lsx_vsrar_b(a: __v16i8, b: __v16i8) -> __v16i8; #[link_name = "llvm.loongarch.lsx.vsrar.h"] @@ -59,22 +27,6 @@ unsafe extern "unadjusted" { fn __lsx_vsrari_w(a: __v4i32, b: u32) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vsrari.d"] fn __lsx_vsrari_d(a: __v2i64, b: u32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vsrl.b"] - fn __lsx_vsrl_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vsrl.h"] - fn __lsx_vsrl_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vsrl.w"] - fn __lsx_vsrl_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vsrl.d"] - fn __lsx_vsrl_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vsrli.b"] - fn __lsx_vsrli_b(a: __v16i8, b: u32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vsrli.h"] - fn __lsx_vsrli_h(a: __v8i16, b: u32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vsrli.w"] - fn __lsx_vsrli_w(a: __v4i32, b: u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vsrli.d"] - fn __lsx_vsrli_d(a: __v2i64, b: u32) -> __v2i64; #[link_name = "llvm.loongarch.lsx.vsrlr.b"] fn __lsx_vsrlr_b(a: __v16i8, b: __v16i8) -> __v16i8; #[link_name = "llvm.loongarch.lsx.vsrlr.h"] @@ -91,14 +43,6 @@ unsafe extern "unadjusted" { fn __lsx_vsrlri_w(a: __v4i32, b: u32) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vsrlri.d"] fn __lsx_vsrlri_d(a: __v2i64, b: u32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vbitclr.b"] - fn __lsx_vbitclr_b(a: __v16u8, b: __v16u8) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vbitclr.h"] - fn __lsx_vbitclr_h(a: __v8u16, b: __v8u16) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vbitclr.w"] - fn __lsx_vbitclr_w(a: __v4u32, b: __v4u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vbitclr.d"] - fn __lsx_vbitclr_d(a: __v2u64, b: __v2u64) -> __v2u64; #[link_name = "llvm.loongarch.lsx.vbitclri.b"] fn __lsx_vbitclri_b(a: __v16u8, b: u32) -> __v16u8; #[link_name = "llvm.loongarch.lsx.vbitclri.h"] @@ -107,14 +51,6 @@ unsafe extern "unadjusted" { fn __lsx_vbitclri_w(a: __v4u32, b: u32) -> __v4u32; #[link_name = "llvm.loongarch.lsx.vbitclri.d"] fn __lsx_vbitclri_d(a: __v2u64, b: u32) -> __v2u64; - #[link_name = "llvm.loongarch.lsx.vbitset.b"] - fn __lsx_vbitset_b(a: __v16u8, b: __v16u8) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vbitset.h"] - fn __lsx_vbitset_h(a: __v8u16, b: __v8u16) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vbitset.w"] - fn __lsx_vbitset_w(a: __v4u32, b: __v4u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vbitset.d"] - fn __lsx_vbitset_d(a: __v2u64, b: __v2u64) -> __v2u64; #[link_name = "llvm.loongarch.lsx.vbitseti.b"] fn __lsx_vbitseti_b(a: __v16u8, b: u32) -> __v16u8; #[link_name = "llvm.loongarch.lsx.vbitseti.h"] @@ -123,14 +59,6 @@ unsafe extern "unadjusted" { fn __lsx_vbitseti_w(a: __v4u32, b: u32) -> __v4u32; #[link_name = "llvm.loongarch.lsx.vbitseti.d"] fn __lsx_vbitseti_d(a: __v2u64, b: u32) -> __v2u64; - #[link_name = "llvm.loongarch.lsx.vbitrev.b"] - fn __lsx_vbitrev_b(a: __v16u8, b: __v16u8) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vbitrev.h"] - fn __lsx_vbitrev_h(a: __v8u16, b: __v8u16) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vbitrev.w"] - fn __lsx_vbitrev_w(a: __v4u32, b: __v4u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vbitrev.d"] - fn __lsx_vbitrev_d(a: __v2u64, b: __v2u64) -> __v2u64; #[link_name = "llvm.loongarch.lsx.vbitrevi.b"] fn __lsx_vbitrevi_b(a: __v16u8, b: u32) -> __v16u8; #[link_name = "llvm.loongarch.lsx.vbitrevi.h"] @@ -139,30 +67,6 @@ unsafe extern "unadjusted" { fn __lsx_vbitrevi_w(a: __v4u32, b: u32) -> __v4u32; #[link_name = "llvm.loongarch.lsx.vbitrevi.d"] fn __lsx_vbitrevi_d(a: __v2u64, b: u32) -> __v2u64; - #[link_name = "llvm.loongarch.lsx.vadd.b"] - fn __lsx_vadd_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vadd.h"] - fn __lsx_vadd_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vadd.w"] - fn __lsx_vadd_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vadd.d"] - fn __lsx_vadd_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vaddi.bu"] - fn __lsx_vaddi_bu(a: __v16i8, b: u32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vaddi.hu"] - fn __lsx_vaddi_hu(a: __v8i16, b: u32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vaddi.wu"] - fn __lsx_vaddi_wu(a: __v4i32, b: u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vaddi.du"] - fn __lsx_vaddi_du(a: __v2i64, b: u32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vsub.b"] - fn __lsx_vsub_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vsub.h"] - fn __lsx_vsub_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vsub.w"] - fn __lsx_vsub_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vsub.d"] - fn __lsx_vsub_d(a: __v2i64, b: __v2i64) -> __v2i64; #[link_name = "llvm.loongarch.lsx.vsubi.bu"] fn __lsx_vsubi_bu(a: __v16i8, b: u32) -> __v16i8; #[link_name = "llvm.loongarch.lsx.vsubi.hu"] @@ -171,150 +75,6 @@ unsafe extern "unadjusted" { fn __lsx_vsubi_wu(a: __v4i32, b: u32) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vsubi.du"] fn __lsx_vsubi_du(a: __v2i64, b: u32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vmax.b"] - fn __lsx_vmax_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vmax.h"] - fn __lsx_vmax_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vmax.w"] - fn __lsx_vmax_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vmax.d"] - fn __lsx_vmax_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vmaxi.b"] - fn __lsx_vmaxi_b(a: __v16i8, b: i32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vmaxi.h"] - fn __lsx_vmaxi_h(a: __v8i16, b: i32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vmaxi.w"] - fn __lsx_vmaxi_w(a: __v4i32, b: i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vmaxi.d"] - fn __lsx_vmaxi_d(a: __v2i64, b: i32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vmax.bu"] - fn __lsx_vmax_bu(a: __v16u8, b: __v16u8) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vmax.hu"] - fn __lsx_vmax_hu(a: __v8u16, b: __v8u16) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vmax.wu"] - fn __lsx_vmax_wu(a: __v4u32, b: __v4u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vmax.du"] - fn __lsx_vmax_du(a: __v2u64, b: __v2u64) -> __v2u64; - #[link_name = "llvm.loongarch.lsx.vmaxi.bu"] - fn __lsx_vmaxi_bu(a: __v16u8, b: u32) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vmaxi.hu"] - fn __lsx_vmaxi_hu(a: __v8u16, b: u32) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vmaxi.wu"] - fn __lsx_vmaxi_wu(a: __v4u32, b: u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vmaxi.du"] - fn __lsx_vmaxi_du(a: __v2u64, b: u32) -> __v2u64; - #[link_name = "llvm.loongarch.lsx.vmin.b"] - fn __lsx_vmin_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vmin.h"] - fn __lsx_vmin_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vmin.w"] - fn __lsx_vmin_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vmin.d"] - fn __lsx_vmin_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vmini.b"] - fn __lsx_vmini_b(a: __v16i8, b: i32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vmini.h"] - fn __lsx_vmini_h(a: __v8i16, b: i32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vmini.w"] - fn __lsx_vmini_w(a: __v4i32, b: i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vmini.d"] - fn __lsx_vmini_d(a: __v2i64, b: i32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vmin.bu"] - fn __lsx_vmin_bu(a: __v16u8, b: __v16u8) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vmin.hu"] - fn __lsx_vmin_hu(a: __v8u16, b: __v8u16) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vmin.wu"] - fn __lsx_vmin_wu(a: __v4u32, b: __v4u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vmin.du"] - fn __lsx_vmin_du(a: __v2u64, b: __v2u64) -> __v2u64; - #[link_name = "llvm.loongarch.lsx.vmini.bu"] - fn __lsx_vmini_bu(a: __v16u8, b: u32) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vmini.hu"] - fn __lsx_vmini_hu(a: __v8u16, b: u32) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vmini.wu"] - fn __lsx_vmini_wu(a: __v4u32, b: u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vmini.du"] - fn __lsx_vmini_du(a: __v2u64, b: u32) -> __v2u64; - #[link_name = "llvm.loongarch.lsx.vseq.b"] - fn __lsx_vseq_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vseq.h"] - fn __lsx_vseq_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vseq.w"] - fn __lsx_vseq_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vseq.d"] - fn __lsx_vseq_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vseqi.b"] - fn __lsx_vseqi_b(a: __v16i8, b: i32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vseqi.h"] - fn __lsx_vseqi_h(a: __v8i16, b: i32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vseqi.w"] - fn __lsx_vseqi_w(a: __v4i32, b: i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vseqi.d"] - fn __lsx_vseqi_d(a: __v2i64, b: i32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vslti.b"] - fn __lsx_vslti_b(a: __v16i8, b: i32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vslt.b"] - fn __lsx_vslt_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vslt.h"] - fn __lsx_vslt_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vslt.w"] - fn __lsx_vslt_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vslt.d"] - fn __lsx_vslt_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vslti.h"] - fn __lsx_vslti_h(a: __v8i16, b: i32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vslti.w"] - fn __lsx_vslti_w(a: __v4i32, b: i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vslti.d"] - fn __lsx_vslti_d(a: __v2i64, b: i32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vslt.bu"] - fn __lsx_vslt_bu(a: __v16u8, b: __v16u8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vslt.hu"] - fn __lsx_vslt_hu(a: __v8u16, b: __v8u16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vslt.wu"] - fn __lsx_vslt_wu(a: __v4u32, b: __v4u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vslt.du"] - fn __lsx_vslt_du(a: __v2u64, b: __v2u64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vslti.bu"] - fn __lsx_vslti_bu(a: __v16u8, b: u32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vslti.hu"] - fn __lsx_vslti_hu(a: __v8u16, b: u32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vslti.wu"] - fn __lsx_vslti_wu(a: __v4u32, b: u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vslti.du"] - fn __lsx_vslti_du(a: __v2u64, b: u32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vsle.b"] - fn __lsx_vsle_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vsle.h"] - fn __lsx_vsle_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vsle.w"] - fn __lsx_vsle_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vsle.d"] - fn __lsx_vsle_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vslei.b"] - fn __lsx_vslei_b(a: __v16i8, b: i32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vslei.h"] - fn __lsx_vslei_h(a: __v8i16, b: i32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vslei.w"] - fn __lsx_vslei_w(a: __v4i32, b: i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vslei.d"] - fn __lsx_vslei_d(a: __v2i64, b: i32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vsle.bu"] - fn __lsx_vsle_bu(a: __v16u8, b: __v16u8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vsle.hu"] - fn __lsx_vsle_hu(a: __v8u16, b: __v8u16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vsle.wu"] - fn __lsx_vsle_wu(a: __v4u32, b: __v4u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vsle.du"] - fn __lsx_vsle_du(a: __v2u64, b: __v2u64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vslei.bu"] - fn __lsx_vslei_bu(a: __v16u8, b: u32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vslei.hu"] - fn __lsx_vslei_hu(a: __v8u16, b: u32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vslei.wu"] - fn __lsx_vslei_wu(a: __v4u32, b: u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vslei.du"] - fn __lsx_vslei_du(a: __v2u64, b: u32) -> __v2i64; #[link_name = "llvm.loongarch.lsx.vsat.b"] fn __lsx_vsat_b(a: __v16i8, b: u32) -> __v16i8; #[link_name = "llvm.loongarch.lsx.vsat.h"] @@ -331,30 +91,6 @@ unsafe extern "unadjusted" { fn __lsx_vsat_wu(a: __v4u32, b: u32) -> __v4u32; #[link_name = "llvm.loongarch.lsx.vsat.du"] fn __lsx_vsat_du(a: __v2u64, b: u32) -> __v2u64; - #[link_name = "llvm.loongarch.lsx.vadda.b"] - fn __lsx_vadda_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vadda.h"] - fn __lsx_vadda_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vadda.w"] - fn __lsx_vadda_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vadda.d"] - fn __lsx_vadda_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vsadd.b"] - fn __lsx_vsadd_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vsadd.h"] - fn __lsx_vsadd_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vsadd.w"] - fn __lsx_vsadd_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vsadd.d"] - fn __lsx_vsadd_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vsadd.bu"] - fn __lsx_vsadd_bu(a: __v16u8, b: __v16u8) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vsadd.hu"] - fn __lsx_vsadd_hu(a: __v8u16, b: __v8u16) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vsadd.wu"] - fn __lsx_vsadd_wu(a: __v4u32, b: __v4u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vsadd.du"] - fn __lsx_vsadd_du(a: __v2u64, b: __v2u64) -> __v2u64; #[link_name = "llvm.loongarch.lsx.vavg.b"] fn __lsx_vavg_b(a: __v16i8, b: __v16i8) -> __v16i8; #[link_name = "llvm.loongarch.lsx.vavg.h"] @@ -387,78 +123,6 @@ unsafe extern "unadjusted" { fn __lsx_vavgr_wu(a: __v4u32, b: __v4u32) -> __v4u32; #[link_name = "llvm.loongarch.lsx.vavgr.du"] fn __lsx_vavgr_du(a: __v2u64, b: __v2u64) -> __v2u64; - #[link_name = "llvm.loongarch.lsx.vssub.b"] - fn __lsx_vssub_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vssub.h"] - fn __lsx_vssub_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vssub.w"] - fn __lsx_vssub_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vssub.d"] - fn __lsx_vssub_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vssub.bu"] - fn __lsx_vssub_bu(a: __v16u8, b: __v16u8) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vssub.hu"] - fn __lsx_vssub_hu(a: __v8u16, b: __v8u16) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vssub.wu"] - fn __lsx_vssub_wu(a: __v4u32, b: __v4u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vssub.du"] - fn __lsx_vssub_du(a: __v2u64, b: __v2u64) -> __v2u64; - #[link_name = "llvm.loongarch.lsx.vabsd.b"] - fn __lsx_vabsd_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vabsd.h"] - fn __lsx_vabsd_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vabsd.w"] - fn __lsx_vabsd_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vabsd.d"] - fn __lsx_vabsd_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vabsd.bu"] - fn __lsx_vabsd_bu(a: __v16u8, b: __v16u8) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vabsd.hu"] - fn __lsx_vabsd_hu(a: __v8u16, b: __v8u16) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vabsd.wu"] - fn __lsx_vabsd_wu(a: __v4u32, b: __v4u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vabsd.du"] - fn __lsx_vabsd_du(a: __v2u64, b: __v2u64) -> __v2u64; - #[link_name = "llvm.loongarch.lsx.vmul.b"] - fn __lsx_vmul_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vmul.h"] - fn __lsx_vmul_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vmul.w"] - fn __lsx_vmul_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vmul.d"] - fn __lsx_vmul_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vmadd.b"] - fn __lsx_vmadd_b(a: __v16i8, b: __v16i8, c: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vmadd.h"] - fn __lsx_vmadd_h(a: __v8i16, b: __v8i16, c: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vmadd.w"] - fn __lsx_vmadd_w(a: __v4i32, b: __v4i32, c: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vmadd.d"] - fn __lsx_vmadd_d(a: __v2i64, b: __v2i64, c: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vmsub.b"] - fn __lsx_vmsub_b(a: __v16i8, b: __v16i8, c: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vmsub.h"] - fn __lsx_vmsub_h(a: __v8i16, b: __v8i16, c: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vmsub.w"] - fn __lsx_vmsub_w(a: __v4i32, b: __v4i32, c: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vmsub.d"] - fn __lsx_vmsub_d(a: __v2i64, b: __v2i64, c: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vdiv.b"] - fn __lsx_vdiv_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vdiv.h"] - fn __lsx_vdiv_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vdiv.w"] - fn __lsx_vdiv_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vdiv.d"] - fn __lsx_vdiv_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vdiv.bu"] - fn __lsx_vdiv_bu(a: __v16u8, b: __v16u8) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vdiv.hu"] - fn __lsx_vdiv_hu(a: __v8u16, b: __v8u16) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vdiv.wu"] - fn __lsx_vdiv_wu(a: __v4u32, b: __v4u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vdiv.du"] - fn __lsx_vdiv_du(a: __v2u64, b: __v2u64) -> __v2u64; #[link_name = "llvm.loongarch.lsx.vhaddw.h.b"] fn __lsx_vhaddw_h_b(a: __v16i8, b: __v16i8) -> __v8i16; #[link_name = "llvm.loongarch.lsx.vhaddw.w.h"] @@ -483,22 +147,6 @@ unsafe extern "unadjusted" { fn __lsx_vhsubw_wu_hu(a: __v8u16, b: __v8u16) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vhsubw.du.wu"] fn __lsx_vhsubw_du_wu(a: __v4u32, b: __v4u32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vmod.b"] - fn __lsx_vmod_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vmod.h"] - fn __lsx_vmod_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vmod.w"] - fn __lsx_vmod_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vmod.d"] - fn __lsx_vmod_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vmod.bu"] - fn __lsx_vmod_bu(a: __v16u8, b: __v16u8) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vmod.hu"] - fn __lsx_vmod_hu(a: __v8u16, b: __v8u16) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vmod.wu"] - fn __lsx_vmod_wu(a: __v4u32, b: __v4u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vmod.du"] - fn __lsx_vmod_du(a: __v2u64, b: __v2u64) -> __v2u64; #[link_name = "llvm.loongarch.lsx.vreplve.b"] fn __lsx_vreplve_b(a: __v16i8, b: i32) -> __v16i8; #[link_name = "llvm.loongarch.lsx.vreplve.h"] @@ -507,110 +155,24 @@ unsafe extern "unadjusted" { fn __lsx_vreplve_w(a: __v4i32, b: i32) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vreplve.d"] fn __lsx_vreplve_d(a: __v2i64, b: i32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vreplvei.b"] - fn __lsx_vreplvei_b(a: __v16i8, b: u32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vreplvei.h"] - fn __lsx_vreplvei_h(a: __v8i16, b: u32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vreplvei.w"] - fn __lsx_vreplvei_w(a: __v4i32, b: u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vreplvei.d"] - fn __lsx_vreplvei_d(a: __v2i64, b: u32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vpickev.b"] - fn __lsx_vpickev_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vpickev.h"] - fn __lsx_vpickev_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vpickev.w"] - fn __lsx_vpickev_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vpickev.d"] - fn __lsx_vpickev_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vpickod.b"] - fn __lsx_vpickod_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vpickod.h"] - fn __lsx_vpickod_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vpickod.w"] - fn __lsx_vpickod_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vpickod.d"] - fn __lsx_vpickod_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vilvh.b"] - fn __lsx_vilvh_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vilvh.h"] - fn __lsx_vilvh_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vilvh.w"] - fn __lsx_vilvh_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vilvh.d"] - fn __lsx_vilvh_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vilvl.b"] - fn __lsx_vilvl_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vilvl.h"] - fn __lsx_vilvl_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vilvl.w"] - fn __lsx_vilvl_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vilvl.d"] - fn __lsx_vilvl_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vpackev.b"] - fn __lsx_vpackev_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vpackev.h"] - fn __lsx_vpackev_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vpackev.w"] - fn __lsx_vpackev_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vpackev.d"] - fn __lsx_vpackev_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vpackod.b"] - fn __lsx_vpackod_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vpackod.h"] - fn __lsx_vpackod_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vpackod.w"] - fn __lsx_vpackod_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vpackod.d"] - fn __lsx_vpackod_d(a: __v2i64, b: __v2i64) -> __v2i64; #[link_name = "llvm.loongarch.lsx.vshuf.h"] fn __lsx_vshuf_h(a: __v8i16, b: __v8i16, c: __v8i16) -> __v8i16; #[link_name = "llvm.loongarch.lsx.vshuf.w"] fn __lsx_vshuf_w(a: __v4i32, b: __v4i32, c: __v4i32) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vshuf.d"] fn __lsx_vshuf_d(a: __v2i64, b: __v2i64, c: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vand.v"] - fn __lsx_vand_v(a: __v16u8, b: __v16u8) -> __v16u8; #[link_name = "llvm.loongarch.lsx.vandi.b"] fn __lsx_vandi_b(a: __v16u8, b: u32) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vor.v"] - fn __lsx_vor_v(a: __v16u8, b: __v16u8) -> __v16u8; #[link_name = "llvm.loongarch.lsx.vori.b"] fn __lsx_vori_b(a: __v16u8, b: u32) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vnor.v"] - fn __lsx_vnor_v(a: __v16u8, b: __v16u8) -> __v16u8; #[link_name = "llvm.loongarch.lsx.vnori.b"] fn __lsx_vnori_b(a: __v16u8, b: u32) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vxor.v"] - fn __lsx_vxor_v(a: __v16u8, b: __v16u8) -> __v16u8; #[link_name = "llvm.loongarch.lsx.vxori.b"] fn __lsx_vxori_b(a: __v16u8, b: u32) -> __v16u8; #[link_name = "llvm.loongarch.lsx.vbitsel.v"] fn __lsx_vbitsel_v(a: __v16u8, b: __v16u8, c: __v16u8) -> __v16u8; #[link_name = "llvm.loongarch.lsx.vbitseli.b"] fn __lsx_vbitseli_b(a: __v16u8, b: __v16u8, c: u32) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vshuf4i.b"] - fn __lsx_vshuf4i_b(a: __v16i8, b: u32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vshuf4i.h"] - fn __lsx_vshuf4i_h(a: __v8i16, b: u32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vshuf4i.w"] - fn __lsx_vshuf4i_w(a: __v4i32, b: u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vreplgr2vr.b"] - fn __lsx_vreplgr2vr_b(a: i32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vreplgr2vr.h"] - fn __lsx_vreplgr2vr_h(a: i32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vreplgr2vr.w"] - fn __lsx_vreplgr2vr_w(a: i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vreplgr2vr.d"] - fn __lsx_vreplgr2vr_d(a: i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vpcnt.b"] - fn __lsx_vpcnt_b(a: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vpcnt.h"] - fn __lsx_vpcnt_h(a: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vpcnt.w"] - fn __lsx_vpcnt_w(a: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vpcnt.d"] - fn __lsx_vpcnt_d(a: __v2i64) -> __v2i64; #[link_name = "llvm.loongarch.lsx.vclo.b"] fn __lsx_vclo_b(a: __v16i8) -> __v16i8; #[link_name = "llvm.loongarch.lsx.vclo.h"] @@ -619,54 +181,6 @@ unsafe extern "unadjusted" { fn __lsx_vclo_w(a: __v4i32) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vclo.d"] fn __lsx_vclo_d(a: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vclz.b"] - fn __lsx_vclz_b(a: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vclz.h"] - fn __lsx_vclz_h(a: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vclz.w"] - fn __lsx_vclz_w(a: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vclz.d"] - fn __lsx_vclz_d(a: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vpickve2gr.b"] - fn __lsx_vpickve2gr_b(a: __v16i8, b: u32) -> i32; - #[link_name = "llvm.loongarch.lsx.vpickve2gr.h"] - fn __lsx_vpickve2gr_h(a: __v8i16, b: u32) -> i32; - #[link_name = "llvm.loongarch.lsx.vpickve2gr.w"] - fn __lsx_vpickve2gr_w(a: __v4i32, b: u32) -> i32; - #[link_name = "llvm.loongarch.lsx.vpickve2gr.d"] - fn __lsx_vpickve2gr_d(a: __v2i64, b: u32) -> i64; - #[link_name = "llvm.loongarch.lsx.vpickve2gr.bu"] - fn __lsx_vpickve2gr_bu(a: __v16i8, b: u32) -> u32; - #[link_name = "llvm.loongarch.lsx.vpickve2gr.hu"] - fn __lsx_vpickve2gr_hu(a: __v8i16, b: u32) -> u32; - #[link_name = "llvm.loongarch.lsx.vpickve2gr.wu"] - fn __lsx_vpickve2gr_wu(a: __v4i32, b: u32) -> u32; - #[link_name = "llvm.loongarch.lsx.vpickve2gr.du"] - fn __lsx_vpickve2gr_du(a: __v2i64, b: u32) -> u64; - #[link_name = "llvm.loongarch.lsx.vinsgr2vr.b"] - fn __lsx_vinsgr2vr_b(a: __v16i8, b: i32, c: u32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vinsgr2vr.h"] - fn __lsx_vinsgr2vr_h(a: __v8i16, b: i32, c: u32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vinsgr2vr.w"] - fn __lsx_vinsgr2vr_w(a: __v4i32, b: i32, c: u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vinsgr2vr.d"] - fn __lsx_vinsgr2vr_d(a: __v2i64, b: i64, c: u32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vfadd.s"] - fn __lsx_vfadd_s(a: __v4f32, b: __v4f32) -> __v4f32; - #[link_name = "llvm.loongarch.lsx.vfadd.d"] - fn __lsx_vfadd_d(a: __v2f64, b: __v2f64) -> __v2f64; - #[link_name = "llvm.loongarch.lsx.vfsub.s"] - fn __lsx_vfsub_s(a: __v4f32, b: __v4f32) -> __v4f32; - #[link_name = "llvm.loongarch.lsx.vfsub.d"] - fn __lsx_vfsub_d(a: __v2f64, b: __v2f64) -> __v2f64; - #[link_name = "llvm.loongarch.lsx.vfmul.s"] - fn __lsx_vfmul_s(a: __v4f32, b: __v4f32) -> __v4f32; - #[link_name = "llvm.loongarch.lsx.vfmul.d"] - fn __lsx_vfmul_d(a: __v2f64, b: __v2f64) -> __v2f64; - #[link_name = "llvm.loongarch.lsx.vfdiv.s"] - fn __lsx_vfdiv_s(a: __v4f32, b: __v4f32) -> __v4f32; - #[link_name = "llvm.loongarch.lsx.vfdiv.d"] - fn __lsx_vfdiv_d(a: __v2f64, b: __v2f64) -> __v2f64; #[link_name = "llvm.loongarch.lsx.vfcvt.h.s"] fn __lsx_vfcvt_h_s(a: __v4f32, b: __v4f32) -> __v8i16; #[link_name = "llvm.loongarch.lsx.vfcvt.s.d"] @@ -691,14 +205,6 @@ unsafe extern "unadjusted" { fn __lsx_vfclass_s(a: __v4f32) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vfclass.d"] fn __lsx_vfclass_d(a: __v2f64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vfsqrt.s"] - fn __lsx_vfsqrt_s(a: __v4f32) -> __v4f32; - #[link_name = "llvm.loongarch.lsx.vfsqrt.d"] - fn __lsx_vfsqrt_d(a: __v2f64) -> __v2f64; - #[link_name = "llvm.loongarch.lsx.vfrecip.s"] - fn __lsx_vfrecip_s(a: __v4f32) -> __v4f32; - #[link_name = "llvm.loongarch.lsx.vfrecip.d"] - fn __lsx_vfrecip_d(a: __v2f64) -> __v2f64; #[link_name = "llvm.loongarch.lsx.vfrecipe.s"] fn __lsx_vfrecipe_s(a: __v4f32) -> __v4f32; #[link_name = "llvm.loongarch.lsx.vfrecipe.d"] @@ -711,10 +217,6 @@ unsafe extern "unadjusted" { fn __lsx_vfrint_s(a: __v4f32) -> __v4f32; #[link_name = "llvm.loongarch.lsx.vfrint.d"] fn __lsx_vfrint_d(a: __v2f64) -> __v2f64; - #[link_name = "llvm.loongarch.lsx.vfrsqrt.s"] - fn __lsx_vfrsqrt_s(a: __v4f32) -> __v4f32; - #[link_name = "llvm.loongarch.lsx.vfrsqrt.d"] - fn __lsx_vfrsqrt_d(a: __v2f64) -> __v2f64; #[link_name = "llvm.loongarch.lsx.vflogb.s"] fn __lsx_vflogb_s(a: __v4f32) -> __v4f32; #[link_name = "llvm.loongarch.lsx.vflogb.d"] @@ -751,32 +253,6 @@ unsafe extern "unadjusted" { fn __lsx_vffint_s_wu(a: __v4u32) -> __v4f32; #[link_name = "llvm.loongarch.lsx.vffint.d.lu"] fn __lsx_vffint_d_lu(a: __v2u64) -> __v2f64; - #[link_name = "llvm.loongarch.lsx.vandn.v"] - fn __lsx_vandn_v(a: __v16u8, b: __v16u8) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vneg.b"] - fn __lsx_vneg_b(a: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vneg.h"] - fn __lsx_vneg_h(a: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vneg.w"] - fn __lsx_vneg_w(a: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vneg.d"] - fn __lsx_vneg_d(a: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vmuh.b"] - fn __lsx_vmuh_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vmuh.h"] - fn __lsx_vmuh_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vmuh.w"] - fn __lsx_vmuh_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vmuh.d"] - fn __lsx_vmuh_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vmuh.bu"] - fn __lsx_vmuh_bu(a: __v16u8, b: __v16u8) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vmuh.hu"] - fn __lsx_vmuh_hu(a: __v8u16, b: __v8u16) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vmuh.wu"] - fn __lsx_vmuh_wu(a: __v4u32, b: __v4u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vmuh.du"] - fn __lsx_vmuh_du(a: __v2u64, b: __v2u64) -> __v2u64; #[link_name = "llvm.loongarch.lsx.vsllwil.h.b"] fn __lsx_vsllwil_h_b(a: __v16i8, b: u32) -> __v8i16; #[link_name = "llvm.loongarch.lsx.vsllwil.w.h"] @@ -857,12 +333,6 @@ unsafe extern "unadjusted" { fn __lsx_vfrstp_b(a: __v16i8, b: __v16i8, c: __v16i8) -> __v16i8; #[link_name = "llvm.loongarch.lsx.vfrstp.h"] fn __lsx_vfrstp_h(a: __v8i16, b: __v8i16, c: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vshuf4i.d"] - fn __lsx_vshuf4i_d(a: __v2i64, b: __v2i64, c: u32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vbsrl.v"] - fn __lsx_vbsrl_v(a: __v16i8, b: u32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vbsll.v"] - fn __lsx_vbsll_v(a: __v16i8, b: u32) -> __v16i8; #[link_name = "llvm.loongarch.lsx.vextrins.b"] fn __lsx_vextrins_b(a: __v16i8, b: __v16i8, c: u32) -> __v16i8; #[link_name = "llvm.loongarch.lsx.vextrins.h"] @@ -887,22 +357,6 @@ unsafe extern "unadjusted" { fn __lsx_vsigncov_w(a: __v4i32, b: __v4i32) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vsigncov.d"] fn __lsx_vsigncov_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vfmadd.s"] - fn __lsx_vfmadd_s(a: __v4f32, b: __v4f32, c: __v4f32) -> __v4f32; - #[link_name = "llvm.loongarch.lsx.vfmadd.d"] - fn __lsx_vfmadd_d(a: __v2f64, b: __v2f64, c: __v2f64) -> __v2f64; - #[link_name = "llvm.loongarch.lsx.vfmsub.s"] - fn __lsx_vfmsub_s(a: __v4f32, b: __v4f32, c: __v4f32) -> __v4f32; - #[link_name = "llvm.loongarch.lsx.vfmsub.d"] - fn __lsx_vfmsub_d(a: __v2f64, b: __v2f64, c: __v2f64) -> __v2f64; - #[link_name = "llvm.loongarch.lsx.vfnmadd.s"] - fn __lsx_vfnmadd_s(a: __v4f32, b: __v4f32, c: __v4f32) -> __v4f32; - #[link_name = "llvm.loongarch.lsx.vfnmadd.d"] - fn __lsx_vfnmadd_d(a: __v2f64, b: __v2f64, c: __v2f64) -> __v2f64; - #[link_name = "llvm.loongarch.lsx.vfnmsub.s"] - fn __lsx_vfnmsub_s(a: __v4f32, b: __v4f32, c: __v4f32) -> __v4f32; - #[link_name = "llvm.loongarch.lsx.vfnmsub.d"] - fn __lsx_vfnmsub_d(a: __v2f64, b: __v2f64, c: __v2f64) -> __v2f64; #[link_name = "llvm.loongarch.lsx.vftintrne.w.s"] fn __lsx_vftintrne_w_s(a: __v4f32) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vftintrne.l.d"] @@ -955,18 +409,6 @@ unsafe extern "unadjusted" { fn __lsx_vfrintrne_s(a: __v4f32) -> __v4f32; #[link_name = "llvm.loongarch.lsx.vfrintrne.d"] fn __lsx_vfrintrne_d(a: __v2f64) -> __v2f64; - #[link_name = "llvm.loongarch.lsx.vfrintrz.s"] - fn __lsx_vfrintrz_s(a: __v4f32) -> __v4f32; - #[link_name = "llvm.loongarch.lsx.vfrintrz.d"] - fn __lsx_vfrintrz_d(a: __v2f64) -> __v2f64; - #[link_name = "llvm.loongarch.lsx.vfrintrp.s"] - fn __lsx_vfrintrp_s(a: __v4f32) -> __v4f32; - #[link_name = "llvm.loongarch.lsx.vfrintrp.d"] - fn __lsx_vfrintrp_d(a: __v2f64) -> __v2f64; - #[link_name = "llvm.loongarch.lsx.vfrintrm.s"] - fn __lsx_vfrintrm_s(a: __v4f32) -> __v4f32; - #[link_name = "llvm.loongarch.lsx.vfrintrm.d"] - fn __lsx_vfrintrm_d(a: __v2f64) -> __v2f64; #[link_name = "llvm.loongarch.lsx.vstelm.b"] fn __lsx_vstelm_b(a: __v16i8, b: *mut i8, c: i32, d: u32); #[link_name = "llvm.loongarch.lsx.vstelm.h"] @@ -1159,14 +601,6 @@ unsafe extern "unadjusted" { fn __lsx_vmaddwev_q_du_d(a: __v2i64, b: __v2u64, c: __v2i64) -> __v2i64; #[link_name = "llvm.loongarch.lsx.vmaddwod.q.du.d"] fn __lsx_vmaddwod_q_du_d(a: __v2i64, b: __v2u64, c: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vrotr.b"] - fn __lsx_vrotr_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vrotr.h"] - fn __lsx_vrotr_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vrotr.w"] - fn __lsx_vrotr_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vrotr.d"] - fn __lsx_vrotr_d(a: __v2i64, b: __v2i64) -> __v2i64; #[link_name = "llvm.loongarch.lsx.vadd.q"] fn __lsx_vadd_q(a: __v2i64, b: __v2i64) -> __v2i64; #[link_name = "llvm.loongarch.lsx.vsub.q"] @@ -1199,14 +633,6 @@ unsafe extern "unadjusted" { fn __lsx_vexth_du_wu(a: __v4u32) -> __v2u64; #[link_name = "llvm.loongarch.lsx.vexth.qu.du"] fn __lsx_vexth_qu_du(a: __v2u64) -> __v2u64; - #[link_name = "llvm.loongarch.lsx.vrotri.b"] - fn __lsx_vrotri_b(a: __v16i8, b: u32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vrotri.h"] - fn __lsx_vrotri_h(a: __v8i16, b: u32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vrotri.w"] - fn __lsx_vrotri_w(a: __v4i32, b: u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vrotri.d"] - fn __lsx_vrotri_d(a: __v2i64, b: u32) -> __v2i64; #[link_name = "llvm.loongarch.lsx.vextl.q.d"] fn __lsx_vextl_q_d(a: __v2i64) -> __v2i64; #[link_name = "llvm.loongarch.lsx.vsrlni.b.h"] @@ -1307,10 +733,6 @@ unsafe extern "unadjusted" { fn __lsx_vssrarni_du_q(a: __v2u64, b: __v2i64, c: u32) -> __v2u64; #[link_name = "llvm.loongarch.lsx.vpermi.w"] fn __lsx_vpermi_w(a: __v4i32, b: __v4i32, c: u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vld"] - fn __lsx_vld(a: *const i8, b: i32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vst"] - fn __lsx_vst(a: __v16i8, b: *mut i8, c: i32); #[link_name = "llvm.loongarch.lsx.vssrlrn.b.h"] fn __lsx_vssrlrn_b_h(a: __v8i16, b: __v8i16) -> __v16i8; #[link_name = "llvm.loongarch.lsx.vssrlrn.h.w"] @@ -1323,16 +745,8 @@ unsafe extern "unadjusted" { fn __lsx_vssrln_h_w(a: __v4i32, b: __v4i32) -> __v8i16; #[link_name = "llvm.loongarch.lsx.vssrln.w.d"] fn __lsx_vssrln_w_d(a: __v2i64, b: __v2i64) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vorn.v"] - fn __lsx_vorn_v(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vldi"] - fn __lsx_vldi(a: i32) -> __v2i64; #[link_name = "llvm.loongarch.lsx.vshuf.b"] fn __lsx_vshuf_b(a: __v16i8, b: __v16i8, c: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vldx"] - fn __lsx_vldx(a: *const i8, b: i64) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vstx"] - fn __lsx_vstx(a: __v16i8, b: *mut i8, c: i64); #[link_name = "llvm.loongarch.lsx.vextl.qu.du"] fn __lsx_vextl_qu_du(a: __v2u64) -> __v2u64; #[link_name = "llvm.loongarch.lsx.bnz.b"] @@ -1443,2526 +857,675 @@ unsafe extern "unadjusted" { fn __lsx_vfcmp_sune_s(a: __v4f32, b: __v4f32) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vfcmp.sun.s"] fn __lsx_vfcmp_sun_s(a: __v4f32, b: __v4f32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vrepli.b"] - fn __lsx_vrepli_b(a: i32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vrepli.d"] - fn __lsx_vrepli_d(a: i32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vrepli.h"] - fn __lsx_vrepli_h(a: i32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vrepli.w"] - fn __lsx_vrepli_w(a: i32) -> __v4i32; } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsll_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsll_b(transmute(a), transmute(b))) } +pub fn lsx_vsrar_b(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vsrar_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsll_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsll_h(transmute(a), transmute(b))) } +pub fn lsx_vsrar_h(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vsrar_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsll_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsll_w(transmute(a), transmute(b))) } +pub fn lsx_vsrar_w(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vsrar_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsll_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsll_d(transmute(a), transmute(b))) } +pub fn lsx_vsrar_d(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vsrar_d(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslli_b(a: m128i) -> m128i { +pub fn lsx_vsrari_b(a: m128i) -> m128i { static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vslli_b(transmute(a), IMM3)) } + unsafe { transmute(__lsx_vsrari_b(transmute(a), IMM3)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslli_h(a: m128i) -> m128i { +pub fn lsx_vsrari_h(a: m128i) -> m128i { static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vslli_h(transmute(a), IMM4)) } + unsafe { transmute(__lsx_vsrari_h(transmute(a), IMM4)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslli_w(a: m128i) -> m128i { +pub fn lsx_vsrari_w(a: m128i) -> m128i { static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vslli_w(transmute(a), IMM5)) } + unsafe { transmute(__lsx_vsrari_w(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslli_d(a: m128i) -> m128i { +pub fn lsx_vsrari_d(a: m128i) -> m128i { static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lsx_vslli_d(transmute(a), IMM6)) } + unsafe { transmute(__lsx_vsrari_d(transmute(a), IMM6)) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsra_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsra_b(transmute(a), transmute(b))) } +pub fn lsx_vsrlr_b(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vsrlr_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsra_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsra_h(transmute(a), transmute(b))) } +pub fn lsx_vsrlr_h(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vsrlr_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsra_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsra_w(transmute(a), transmute(b))) } +pub fn lsx_vsrlr_w(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vsrlr_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsra_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsra_d(transmute(a), transmute(b))) } +pub fn lsx_vsrlr_d(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vsrlr_d(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrai_b(a: m128i) -> m128i { +pub fn lsx_vsrlri_b(a: m128i) -> m128i { static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vsrai_b(transmute(a), IMM3)) } + unsafe { transmute(__lsx_vsrlri_b(transmute(a), IMM3)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrai_h(a: m128i) -> m128i { +pub fn lsx_vsrlri_h(a: m128i) -> m128i { static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vsrai_h(transmute(a), IMM4)) } + unsafe { transmute(__lsx_vsrlri_h(transmute(a), IMM4)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrai_w(a: m128i) -> m128i { +pub fn lsx_vsrlri_w(a: m128i) -> m128i { static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vsrai_w(transmute(a), IMM5)) } + unsafe { transmute(__lsx_vsrlri_w(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrai_d(a: m128i) -> m128i { +pub fn lsx_vsrlri_d(a: m128i) -> m128i { static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lsx_vsrai_d(transmute(a), IMM6)) } + unsafe { transmute(__lsx_vsrlri_d(transmute(a), IMM6)) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrar_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrar_b(transmute(a), transmute(b))) } +pub fn lsx_vbitclri_b(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM3, 3); + unsafe { transmute(__lsx_vbitclri_b(transmute(a), IMM3)) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrar_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrar_h(transmute(a), transmute(b))) } +pub fn lsx_vbitclri_h(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM4, 4); + unsafe { transmute(__lsx_vbitclri_h(transmute(a), IMM4)) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrar_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrar_w(transmute(a), transmute(b))) } +pub fn lsx_vbitclri_w(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM5, 5); + unsafe { transmute(__lsx_vbitclri_w(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrar_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrar_d(transmute(a), transmute(b))) } +pub fn lsx_vbitclri_d(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM6, 6); + unsafe { transmute(__lsx_vbitclri_d(transmute(a), IMM6)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrari_b(a: m128i) -> m128i { +pub fn lsx_vbitseti_b(a: m128i) -> m128i { static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vsrari_b(transmute(a), IMM3)) } + unsafe { transmute(__lsx_vbitseti_b(transmute(a), IMM3)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrari_h(a: m128i) -> m128i { +pub fn lsx_vbitseti_h(a: m128i) -> m128i { static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vsrari_h(transmute(a), IMM4)) } + unsafe { transmute(__lsx_vbitseti_h(transmute(a), IMM4)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrari_w(a: m128i) -> m128i { +pub fn lsx_vbitseti_w(a: m128i) -> m128i { static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vsrari_w(transmute(a), IMM5)) } + unsafe { transmute(__lsx_vbitseti_w(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrari_d(a: m128i) -> m128i { +pub fn lsx_vbitseti_d(a: m128i) -> m128i { static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lsx_vsrari_d(transmute(a), IMM6)) } + unsafe { transmute(__lsx_vbitseti_d(transmute(a), IMM6)) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrl_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrl_b(transmute(a), transmute(b))) } +pub fn lsx_vbitrevi_b(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM3, 3); + unsafe { transmute(__lsx_vbitrevi_b(transmute(a), IMM3)) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrl_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrl_h(transmute(a), transmute(b))) } +pub fn lsx_vbitrevi_h(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM4, 4); + unsafe { transmute(__lsx_vbitrevi_h(transmute(a), IMM4)) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrl_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrl_w(transmute(a), transmute(b))) } +pub fn lsx_vbitrevi_w(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM5, 5); + unsafe { transmute(__lsx_vbitrevi_w(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrl_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrl_d(transmute(a), transmute(b))) } +pub fn lsx_vbitrevi_d(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM6, 6); + unsafe { transmute(__lsx_vbitrevi_d(transmute(a), IMM6)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrli_b(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vsrli_b(transmute(a), IMM3)) } +pub fn lsx_vsubi_bu(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM5, 5); + unsafe { transmute(__lsx_vsubi_bu(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrli_h(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vsrli_h(transmute(a), IMM4)) } +pub fn lsx_vsubi_hu(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM5, 5); + unsafe { transmute(__lsx_vsubi_hu(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrli_w(a: m128i) -> m128i { +pub fn lsx_vsubi_wu(a: m128i) -> m128i { static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vsrli_w(transmute(a), IMM5)) } + unsafe { transmute(__lsx_vsubi_wu(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrli_d(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lsx_vsrli_d(transmute(a), IMM6)) } +pub fn lsx_vsubi_du(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM5, 5); + unsafe { transmute(__lsx_vsubi_du(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrlr_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrlr_b(transmute(a), transmute(b))) } +pub fn lsx_vsat_b(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM3, 3); + unsafe { transmute(__lsx_vsat_b(transmute(a), IMM3)) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrlr_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrlr_h(transmute(a), transmute(b))) } +pub fn lsx_vsat_h(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM4, 4); + unsafe { transmute(__lsx_vsat_h(transmute(a), IMM4)) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrlr_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrlr_w(transmute(a), transmute(b))) } +pub fn lsx_vsat_w(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM5, 5); + unsafe { transmute(__lsx_vsat_w(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrlr_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrlr_d(transmute(a), transmute(b))) } +pub fn lsx_vsat_d(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM6, 6); + unsafe { transmute(__lsx_vsat_d(transmute(a), IMM6)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrlri_b(a: m128i) -> m128i { +pub fn lsx_vsat_bu(a: m128i) -> m128i { static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vsrlri_b(transmute(a), IMM3)) } + unsafe { transmute(__lsx_vsat_bu(transmute(a), IMM3)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrlri_h(a: m128i) -> m128i { +pub fn lsx_vsat_hu(a: m128i) -> m128i { static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vsrlri_h(transmute(a), IMM4)) } + unsafe { transmute(__lsx_vsat_hu(transmute(a), IMM4)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrlri_w(a: m128i) -> m128i { +pub fn lsx_vsat_wu(a: m128i) -> m128i { static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vsrlri_w(transmute(a), IMM5)) } + unsafe { transmute(__lsx_vsat_wu(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrlri_d(a: m128i) -> m128i { +pub fn lsx_vsat_du(a: m128i) -> m128i { static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lsx_vsrlri_d(transmute(a), IMM6)) } + unsafe { transmute(__lsx_vsat_du(transmute(a), IMM6)) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitclr_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitclr_b(transmute(a), transmute(b))) } +pub fn lsx_vavg_b(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavg_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitclr_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitclr_h(transmute(a), transmute(b))) } +pub fn lsx_vavg_h(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavg_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitclr_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitclr_w(transmute(a), transmute(b))) } +pub fn lsx_vavg_w(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavg_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitclr_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitclr_d(transmute(a), transmute(b))) } +pub fn lsx_vavg_d(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavg_d(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitclri_b(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vbitclri_b(transmute(a), IMM3)) } +pub fn lsx_vavg_bu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavg_bu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitclri_h(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vbitclri_h(transmute(a), IMM4)) } +pub fn lsx_vavg_hu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavg_hu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitclri_w(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vbitclri_w(transmute(a), IMM5)) } +pub fn lsx_vavg_wu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavg_wu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitclri_d(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lsx_vbitclri_d(transmute(a), IMM6)) } +pub fn lsx_vavg_du(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavg_du(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitset_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitset_b(transmute(a), transmute(b))) } +pub fn lsx_vavgr_b(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavgr_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitset_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitset_h(transmute(a), transmute(b))) } +pub fn lsx_vavgr_h(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavgr_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitset_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitset_w(transmute(a), transmute(b))) } +pub fn lsx_vavgr_w(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavgr_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitset_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitset_d(transmute(a), transmute(b))) } +pub fn lsx_vavgr_d(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavgr_d(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitseti_b(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vbitseti_b(transmute(a), IMM3)) } +pub fn lsx_vavgr_bu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavgr_bu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitseti_h(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vbitseti_h(transmute(a), IMM4)) } +pub fn lsx_vavgr_hu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavgr_hu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitseti_w(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vbitseti_w(transmute(a), IMM5)) } +pub fn lsx_vavgr_wu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavgr_wu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitseti_d(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lsx_vbitseti_d(transmute(a), IMM6)) } +pub fn lsx_vavgr_du(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavgr_du(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitrev_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitrev_b(transmute(a), transmute(b))) } +pub fn lsx_vhaddw_h_b(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhaddw_h_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitrev_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitrev_h(transmute(a), transmute(b))) } +pub fn lsx_vhaddw_w_h(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhaddw_w_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitrev_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitrev_w(transmute(a), transmute(b))) } +pub fn lsx_vhaddw_d_w(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhaddw_d_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitrev_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitrev_d(transmute(a), transmute(b))) } +pub fn lsx_vhaddw_hu_bu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhaddw_hu_bu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitrevi_b(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vbitrevi_b(transmute(a), IMM3)) } +pub fn lsx_vhaddw_wu_hu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhaddw_wu_hu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitrevi_h(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vbitrevi_h(transmute(a), IMM4)) } +pub fn lsx_vhaddw_du_wu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhaddw_du_wu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitrevi_w(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vbitrevi_w(transmute(a), IMM5)) } +pub fn lsx_vhsubw_h_b(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhsubw_h_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitrevi_d(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lsx_vbitrevi_d(transmute(a), IMM6)) } +pub fn lsx_vhsubw_w_h(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhsubw_w_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vadd_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vadd_b(transmute(a), transmute(b))) } +pub fn lsx_vhsubw_d_w(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhsubw_d_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vadd_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vadd_h(transmute(a), transmute(b))) } +pub fn lsx_vhsubw_hu_bu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhsubw_hu_bu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vadd_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vadd_w(transmute(a), transmute(b))) } +pub fn lsx_vhsubw_wu_hu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhsubw_wu_hu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vadd_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vadd_d(transmute(a), transmute(b))) } +pub fn lsx_vhsubw_du_wu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhsubw_du_wu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vaddi_bu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vaddi_bu(transmute(a), IMM5)) } +pub fn lsx_vreplve_b(a: m128i, b: i32) -> m128i { + unsafe { transmute(__lsx_vreplve_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vaddi_hu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vaddi_hu(transmute(a), IMM5)) } +pub fn lsx_vreplve_h(a: m128i, b: i32) -> m128i { + unsafe { transmute(__lsx_vreplve_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vaddi_wu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vaddi_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vaddi_du(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vaddi_du(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsub_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsub_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsub_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsub_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsub_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsub_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsub_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsub_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsubi_bu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vsubi_bu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsubi_hu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vsubi_hu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsubi_wu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vsubi_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsubi_du(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vsubi_du(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmax_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmax_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmax_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmax_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmax_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmax_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmax_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmax_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmaxi_b(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vmaxi_b(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmaxi_h(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vmaxi_h(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmaxi_w(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vmaxi_w(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmaxi_d(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vmaxi_d(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmax_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmax_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmax_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmax_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmax_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmax_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmax_du(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmax_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmaxi_bu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vmaxi_bu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmaxi_hu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vmaxi_hu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmaxi_wu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vmaxi_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmaxi_du(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vmaxi_du(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmin_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmin_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmin_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmin_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmin_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmin_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmin_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmin_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmini_b(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vmini_b(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmini_h(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vmini_h(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmini_w(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vmini_w(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmini_d(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vmini_d(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmin_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmin_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmin_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmin_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmin_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmin_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmin_du(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmin_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmini_bu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vmini_bu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmini_hu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vmini_hu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmini_wu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vmini_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmini_du(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vmini_du(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vseq_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vseq_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vseq_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vseq_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vseq_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vseq_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vseq_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vseq_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vseqi_b(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vseqi_b(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vseqi_h(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vseqi_h(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vseqi_w(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vseqi_w(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vseqi_d(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vseqi_d(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslti_b(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vslti_b(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslt_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vslt_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslt_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vslt_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslt_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vslt_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslt_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vslt_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslti_h(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vslti_h(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslti_w(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vslti_w(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslti_d(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vslti_d(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslt_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vslt_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslt_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vslt_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslt_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vslt_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslt_du(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vslt_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslti_bu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vslti_bu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslti_hu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vslti_hu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslti_wu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vslti_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslti_du(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vslti_du(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsle_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsle_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsle_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsle_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsle_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsle_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsle_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsle_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslei_b(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vslei_b(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslei_h(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vslei_h(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslei_w(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vslei_w(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslei_d(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vslei_d(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsle_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsle_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsle_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsle_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsle_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsle_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsle_du(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsle_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslei_bu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vslei_bu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslei_hu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vslei_hu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslei_wu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vslei_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslei_du(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vslei_du(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsat_b(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vsat_b(transmute(a), IMM3)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsat_h(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vsat_h(transmute(a), IMM4)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsat_w(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vsat_w(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsat_d(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lsx_vsat_d(transmute(a), IMM6)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsat_bu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vsat_bu(transmute(a), IMM3)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsat_hu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vsat_hu(transmute(a), IMM4)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsat_wu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vsat_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsat_du(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lsx_vsat_du(transmute(a), IMM6)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vadda_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vadda_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vadda_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vadda_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vadda_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vadda_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vadda_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vadda_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsadd_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsadd_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsadd_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsadd_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsadd_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsadd_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsadd_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsadd_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsadd_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsadd_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsadd_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsadd_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsadd_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsadd_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsadd_du(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsadd_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavg_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavg_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavg_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavg_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavg_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavg_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavg_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavg_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavg_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavg_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavg_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavg_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavg_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavg_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavg_du(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavg_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavgr_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavgr_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavgr_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavgr_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavgr_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavgr_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavgr_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavgr_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavgr_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavgr_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavgr_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavgr_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavgr_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavgr_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavgr_du(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavgr_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vssub_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vssub_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vssub_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vssub_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vssub_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vssub_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vssub_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vssub_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vssub_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vssub_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vssub_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vssub_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vssub_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vssub_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vssub_du(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vssub_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vabsd_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vabsd_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vabsd_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vabsd_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vabsd_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vabsd_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vabsd_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vabsd_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vabsd_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vabsd_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vabsd_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vabsd_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vabsd_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vabsd_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vabsd_du(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vabsd_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmul_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmul_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmul_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmul_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmul_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmul_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmul_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmul_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmadd_b(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vmadd_b(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmadd_h(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vmadd_h(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmadd_w(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vmadd_w(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmadd_d(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vmadd_d(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmsub_b(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vmsub_b(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmsub_h(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vmsub_h(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmsub_w(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vmsub_w(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmsub_d(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vmsub_d(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vdiv_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vdiv_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vdiv_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vdiv_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vdiv_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vdiv_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vdiv_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vdiv_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vdiv_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vdiv_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vdiv_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vdiv_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vdiv_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vdiv_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vdiv_du(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vdiv_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhaddw_h_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhaddw_h_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhaddw_w_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhaddw_w_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhaddw_d_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhaddw_d_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhaddw_hu_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhaddw_hu_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhaddw_wu_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhaddw_wu_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhaddw_du_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhaddw_du_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhsubw_h_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhsubw_h_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhsubw_w_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhsubw_w_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhsubw_d_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhsubw_d_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhsubw_hu_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhsubw_hu_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhsubw_wu_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhsubw_wu_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhsubw_du_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhsubw_du_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmod_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmod_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmod_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmod_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmod_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmod_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmod_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmod_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmod_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmod_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmod_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmod_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmod_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmod_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmod_du(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmod_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplve_b(a: m128i, b: i32) -> m128i { - unsafe { transmute(__lsx_vreplve_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplve_h(a: m128i, b: i32) -> m128i { - unsafe { transmute(__lsx_vreplve_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplve_w(a: m128i, b: i32) -> m128i { - unsafe { transmute(__lsx_vreplve_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplve_d(a: m128i, b: i32) -> m128i { - unsafe { transmute(__lsx_vreplve_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplvei_b(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vreplvei_b(transmute(a), IMM4)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplvei_h(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vreplvei_h(transmute(a), IMM3)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplvei_w(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM2, 2); - unsafe { transmute(__lsx_vreplvei_w(transmute(a), IMM2)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplvei_d(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM1, 1); - unsafe { transmute(__lsx_vreplvei_d(transmute(a), IMM1)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickev_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpickev_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickev_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpickev_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickev_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpickev_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickev_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpickev_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickod_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpickod_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickod_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpickod_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickod_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpickod_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickod_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpickod_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vilvh_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vilvh_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vilvh_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vilvh_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vilvh_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vilvh_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vilvh_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vilvh_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vilvl_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vilvl_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vilvl_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vilvl_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vilvl_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vilvl_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vilvl_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vilvl_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpackev_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpackev_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpackev_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpackev_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpackev_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpackev_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpackev_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpackev_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpackod_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpackod_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpackod_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpackod_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpackod_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpackod_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpackod_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpackod_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vshuf_h(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vshuf_h(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vshuf_w(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vshuf_w(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vshuf_d(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vshuf_d(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vand_v(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vand_v(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vandi_b(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lsx_vandi_b(transmute(a), IMM8)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vor_v(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vor_v(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vori_b(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lsx_vori_b(transmute(a), IMM8)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vnor_v(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vnor_v(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vnori_b(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lsx_vnori_b(transmute(a), IMM8)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vxor_v(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vxor_v(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vxori_b(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lsx_vxori_b(transmute(a), IMM8)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitsel_v(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vbitsel_v(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitseli_b(a: m128i, b: m128i) -> m128i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lsx_vbitseli_b(transmute(a), transmute(b), IMM8)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vshuf4i_b(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lsx_vshuf4i_b(transmute(a), IMM8)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vshuf4i_h(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lsx_vshuf4i_h(transmute(a), IMM8)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vshuf4i_w(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lsx_vshuf4i_w(transmute(a), IMM8)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplgr2vr_b(a: i32) -> m128i { - unsafe { transmute(__lsx_vreplgr2vr_b(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplgr2vr_h(a: i32) -> m128i { - unsafe { transmute(__lsx_vreplgr2vr_h(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplgr2vr_w(a: i32) -> m128i { - unsafe { transmute(__lsx_vreplgr2vr_w(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplgr2vr_d(a: i64) -> m128i { - unsafe { transmute(__lsx_vreplgr2vr_d(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpcnt_b(a: m128i) -> m128i { - unsafe { transmute(__lsx_vpcnt_b(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpcnt_h(a: m128i) -> m128i { - unsafe { transmute(__lsx_vpcnt_h(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpcnt_w(a: m128i) -> m128i { - unsafe { transmute(__lsx_vpcnt_w(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpcnt_d(a: m128i) -> m128i { - unsafe { transmute(__lsx_vpcnt_d(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vclo_b(a: m128i) -> m128i { - unsafe { transmute(__lsx_vclo_b(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vclo_h(a: m128i) -> m128i { - unsafe { transmute(__lsx_vclo_h(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vclo_w(a: m128i) -> m128i { - unsafe { transmute(__lsx_vclo_w(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vclo_d(a: m128i) -> m128i { - unsafe { transmute(__lsx_vclo_d(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vclz_b(a: m128i) -> m128i { - unsafe { transmute(__lsx_vclz_b(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vclz_h(a: m128i) -> m128i { - unsafe { transmute(__lsx_vclz_h(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vclz_w(a: m128i) -> m128i { - unsafe { transmute(__lsx_vclz_w(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vclz_d(a: m128i) -> m128i { - unsafe { transmute(__lsx_vclz_d(transmute(a))) } +pub fn lsx_vreplve_w(a: m128i, b: i32) -> m128i { + unsafe { transmute(__lsx_vreplve_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickve2gr_b(a: m128i) -> i32 { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vpickve2gr_b(transmute(a), IMM4)) } +pub fn lsx_vreplve_d(a: m128i, b: i32) -> m128i { + unsafe { transmute(__lsx_vreplve_d(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickve2gr_h(a: m128i) -> i32 { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vpickve2gr_h(transmute(a), IMM3)) } +pub fn lsx_vshuf_h(a: m128i, b: m128i, c: m128i) -> m128i { + unsafe { transmute(__lsx_vshuf_h(transmute(a), transmute(b), transmute(c))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickve2gr_w(a: m128i) -> i32 { - static_assert_uimm_bits!(IMM2, 2); - unsafe { transmute(__lsx_vpickve2gr_w(transmute(a), IMM2)) } +pub fn lsx_vshuf_w(a: m128i, b: m128i, c: m128i) -> m128i { + unsafe { transmute(__lsx_vshuf_w(transmute(a), transmute(b), transmute(c))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickve2gr_d(a: m128i) -> i64 { - static_assert_uimm_bits!(IMM1, 1); - unsafe { transmute(__lsx_vpickve2gr_d(transmute(a), IMM1)) } +pub fn lsx_vshuf_d(a: m128i, b: m128i, c: m128i) -> m128i { + unsafe { transmute(__lsx_vshuf_d(transmute(a), transmute(b), transmute(c))) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickve2gr_bu(a: m128i) -> u32 { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vpickve2gr_bu(transmute(a), IMM4)) } +pub fn lsx_vandi_b(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lsx_vandi_b(transmute(a), IMM8)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickve2gr_hu(a: m128i) -> u32 { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vpickve2gr_hu(transmute(a), IMM3)) } +pub fn lsx_vori_b(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lsx_vori_b(transmute(a), IMM8)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickve2gr_wu(a: m128i) -> u32 { - static_assert_uimm_bits!(IMM2, 2); - unsafe { transmute(__lsx_vpickve2gr_wu(transmute(a), IMM2)) } +pub fn lsx_vnori_b(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lsx_vnori_b(transmute(a), IMM8)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickve2gr_du(a: m128i) -> u64 { - static_assert_uimm_bits!(IMM1, 1); - unsafe { transmute(__lsx_vpickve2gr_du(transmute(a), IMM1)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vinsgr2vr_b(a: m128i, b: i32) -> m128i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vinsgr2vr_b(transmute(a), transmute(b), IMM4)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vinsgr2vr_h(a: m128i, b: i32) -> m128i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vinsgr2vr_h(transmute(a), transmute(b), IMM3)) } +pub fn lsx_vxori_b(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lsx_vxori_b(transmute(a), IMM8)) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vinsgr2vr_w(a: m128i, b: i32) -> m128i { - static_assert_uimm_bits!(IMM2, 2); - unsafe { transmute(__lsx_vinsgr2vr_w(transmute(a), transmute(b), IMM2)) } +pub fn lsx_vbitsel_v(a: m128i, b: m128i, c: m128i) -> m128i { + unsafe { transmute(__lsx_vbitsel_v(transmute(a), transmute(b), transmute(c))) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vinsgr2vr_d(a: m128i, b: i64) -> m128i { - static_assert_uimm_bits!(IMM1, 1); - unsafe { transmute(__lsx_vinsgr2vr_d(transmute(a), transmute(b), IMM1)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfadd_s(a: m128, b: m128) -> m128 { - unsafe { transmute(__lsx_vfadd_s(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfadd_d(a: m128d, b: m128d) -> m128d { - unsafe { transmute(__lsx_vfadd_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfsub_s(a: m128, b: m128) -> m128 { - unsafe { transmute(__lsx_vfsub_s(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfsub_d(a: m128d, b: m128d) -> m128d { - unsafe { transmute(__lsx_vfsub_d(transmute(a), transmute(b))) } +pub fn lsx_vbitseli_b(a: m128i, b: m128i) -> m128i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lsx_vbitseli_b(transmute(a), transmute(b), IMM8)) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfmul_s(a: m128, b: m128) -> m128 { - unsafe { transmute(__lsx_vfmul_s(transmute(a), transmute(b))) } +pub fn lsx_vclo_b(a: m128i) -> m128i { + unsafe { transmute(__lsx_vclo_b(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfmul_d(a: m128d, b: m128d) -> m128d { - unsafe { transmute(__lsx_vfmul_d(transmute(a), transmute(b))) } +pub fn lsx_vclo_h(a: m128i) -> m128i { + unsafe { transmute(__lsx_vclo_h(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfdiv_s(a: m128, b: m128) -> m128 { - unsafe { transmute(__lsx_vfdiv_s(transmute(a), transmute(b))) } +pub fn lsx_vclo_w(a: m128i) -> m128i { + unsafe { transmute(__lsx_vclo_w(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfdiv_d(a: m128d, b: m128d) -> m128d { - unsafe { transmute(__lsx_vfdiv_d(transmute(a), transmute(b))) } +pub fn lsx_vclo_d(a: m128i) -> m128i { + unsafe { transmute(__lsx_vclo_d(transmute(a))) } } #[inline] @@ -4049,34 +1612,6 @@ pub fn lsx_vfclass_d(a: m128d) -> m128i { unsafe { transmute(__lsx_vfclass_d(transmute(a))) } } -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfsqrt_s(a: m128) -> m128 { - unsafe { transmute(__lsx_vfsqrt_s(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfsqrt_d(a: m128d) -> m128d { - unsafe { transmute(__lsx_vfsqrt_d(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfrecip_s(a: m128) -> m128 { - unsafe { transmute(__lsx_vfrecip_s(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfrecip_d(a: m128d) -> m128d { - unsafe { transmute(__lsx_vfrecip_d(transmute(a))) } -} - #[inline] #[target_feature(enable = "lsx,frecipe")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4099,255 +1634,150 @@ pub fn lsx_vfrsqrte_s(a: m128) -> m128 { } #[inline] -#[target_feature(enable = "lsx,frecipe")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfrsqrte_d(a: m128d) -> m128d { - unsafe { transmute(__lsx_vfrsqrte_d(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfrint_s(a: m128) -> m128 { - unsafe { transmute(__lsx_vfrint_s(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfrint_d(a: m128d) -> m128d { - unsafe { transmute(__lsx_vfrint_d(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfrsqrt_s(a: m128) -> m128 { - unsafe { transmute(__lsx_vfrsqrt_s(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfrsqrt_d(a: m128d) -> m128d { - unsafe { transmute(__lsx_vfrsqrt_d(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vflogb_s(a: m128) -> m128 { - unsafe { transmute(__lsx_vflogb_s(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vflogb_d(a: m128d) -> m128d { - unsafe { transmute(__lsx_vflogb_d(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfcvth_s_h(a: m128i) -> m128 { - unsafe { transmute(__lsx_vfcvth_s_h(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfcvth_d_s(a: m128) -> m128d { - unsafe { transmute(__lsx_vfcvth_d_s(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfcvtl_s_h(a: m128i) -> m128 { - unsafe { transmute(__lsx_vfcvtl_s_h(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfcvtl_d_s(a: m128) -> m128d { - unsafe { transmute(__lsx_vfcvtl_d_s(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vftint_w_s(a: m128) -> m128i { - unsafe { transmute(__lsx_vftint_w_s(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vftint_l_d(a: m128d) -> m128i { - unsafe { transmute(__lsx_vftint_l_d(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vftint_wu_s(a: m128) -> m128i { - unsafe { transmute(__lsx_vftint_wu_s(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vftint_lu_d(a: m128d) -> m128i { - unsafe { transmute(__lsx_vftint_lu_d(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] +#[target_feature(enable = "lsx,frecipe")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vftintrz_w_s(a: m128) -> m128i { - unsafe { transmute(__lsx_vftintrz_w_s(transmute(a))) } +pub fn lsx_vfrsqrte_d(a: m128d) -> m128d { + unsafe { transmute(__lsx_vfrsqrte_d(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vftintrz_l_d(a: m128d) -> m128i { - unsafe { transmute(__lsx_vftintrz_l_d(transmute(a))) } +pub fn lsx_vfrint_s(a: m128) -> m128 { + unsafe { transmute(__lsx_vfrint_s(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vftintrz_wu_s(a: m128) -> m128i { - unsafe { transmute(__lsx_vftintrz_wu_s(transmute(a))) } +pub fn lsx_vfrint_d(a: m128d) -> m128d { + unsafe { transmute(__lsx_vfrint_d(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vftintrz_lu_d(a: m128d) -> m128i { - unsafe { transmute(__lsx_vftintrz_lu_d(transmute(a))) } +pub fn lsx_vflogb_s(a: m128) -> m128 { + unsafe { transmute(__lsx_vflogb_s(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vffint_s_w(a: m128i) -> m128 { - unsafe { transmute(__lsx_vffint_s_w(transmute(a))) } +pub fn lsx_vflogb_d(a: m128d) -> m128d { + unsafe { transmute(__lsx_vflogb_d(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vffint_d_l(a: m128i) -> m128d { - unsafe { transmute(__lsx_vffint_d_l(transmute(a))) } +pub fn lsx_vfcvth_s_h(a: m128i) -> m128 { + unsafe { transmute(__lsx_vfcvth_s_h(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vffint_s_wu(a: m128i) -> m128 { - unsafe { transmute(__lsx_vffint_s_wu(transmute(a))) } +pub fn lsx_vfcvth_d_s(a: m128) -> m128d { + unsafe { transmute(__lsx_vfcvth_d_s(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vffint_d_lu(a: m128i) -> m128d { - unsafe { transmute(__lsx_vffint_d_lu(transmute(a))) } +pub fn lsx_vfcvtl_s_h(a: m128i) -> m128 { + unsafe { transmute(__lsx_vfcvtl_s_h(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vandn_v(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vandn_v(transmute(a), transmute(b))) } +pub fn lsx_vfcvtl_d_s(a: m128) -> m128d { + unsafe { transmute(__lsx_vfcvtl_d_s(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vneg_b(a: m128i) -> m128i { - unsafe { transmute(__lsx_vneg_b(transmute(a))) } +pub fn lsx_vftint_w_s(a: m128) -> m128i { + unsafe { transmute(__lsx_vftint_w_s(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vneg_h(a: m128i) -> m128i { - unsafe { transmute(__lsx_vneg_h(transmute(a))) } +pub fn lsx_vftint_l_d(a: m128d) -> m128i { + unsafe { transmute(__lsx_vftint_l_d(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vneg_w(a: m128i) -> m128i { - unsafe { transmute(__lsx_vneg_w(transmute(a))) } +pub fn lsx_vftint_wu_s(a: m128) -> m128i { + unsafe { transmute(__lsx_vftint_wu_s(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vneg_d(a: m128i) -> m128i { - unsafe { transmute(__lsx_vneg_d(transmute(a))) } +pub fn lsx_vftint_lu_d(a: m128d) -> m128i { + unsafe { transmute(__lsx_vftint_lu_d(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmuh_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmuh_b(transmute(a), transmute(b))) } +pub fn lsx_vftintrz_w_s(a: m128) -> m128i { + unsafe { transmute(__lsx_vftintrz_w_s(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmuh_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmuh_h(transmute(a), transmute(b))) } +pub fn lsx_vftintrz_l_d(a: m128d) -> m128i { + unsafe { transmute(__lsx_vftintrz_l_d(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmuh_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmuh_w(transmute(a), transmute(b))) } +pub fn lsx_vftintrz_wu_s(a: m128) -> m128i { + unsafe { transmute(__lsx_vftintrz_wu_s(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmuh_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmuh_d(transmute(a), transmute(b))) } +pub fn lsx_vftintrz_lu_d(a: m128d) -> m128i { + unsafe { transmute(__lsx_vftintrz_lu_d(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmuh_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmuh_bu(transmute(a), transmute(b))) } +pub fn lsx_vffint_s_w(a: m128i) -> m128 { + unsafe { transmute(__lsx_vffint_s_w(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmuh_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmuh_hu(transmute(a), transmute(b))) } +pub fn lsx_vffint_d_l(a: m128i) -> m128d { + unsafe { transmute(__lsx_vffint_d_l(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmuh_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmuh_wu(transmute(a), transmute(b))) } +pub fn lsx_vffint_s_wu(a: m128i) -> m128 { + unsafe { transmute(__lsx_vffint_s_wu(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmuh_du(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmuh_du(transmute(a), transmute(b))) } +pub fn lsx_vffint_d_lu(a: m128i) -> m128d { + unsafe { transmute(__lsx_vffint_d_lu(transmute(a))) } } #[inline] @@ -4646,33 +2076,6 @@ pub fn lsx_vfrstp_h(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vfrstp_h(transmute(a), transmute(b), transmute(c))) } } -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vshuf4i_d(a: m128i, b: m128i) -> m128i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lsx_vshuf4i_d(transmute(a), transmute(b), IMM8)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbsrl_v(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vbsrl_v(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbsll_v(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vbsll_v(transmute(a), IMM5)) } -} - #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] @@ -4765,62 +2168,6 @@ pub fn lsx_vsigncov_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsigncov_d(transmute(a), transmute(b))) } } -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfmadd_s(a: m128, b: m128, c: m128) -> m128 { - unsafe { transmute(__lsx_vfmadd_s(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfmadd_d(a: m128d, b: m128d, c: m128d) -> m128d { - unsafe { transmute(__lsx_vfmadd_d(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfmsub_s(a: m128, b: m128, c: m128) -> m128 { - unsafe { transmute(__lsx_vfmsub_s(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfmsub_d(a: m128d, b: m128d, c: m128d) -> m128d { - unsafe { transmute(__lsx_vfmsub_d(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfnmadd_s(a: m128, b: m128, c: m128) -> m128 { - unsafe { transmute(__lsx_vfnmadd_s(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfnmadd_d(a: m128d, b: m128d, c: m128d) -> m128d { - unsafe { transmute(__lsx_vfnmadd_d(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfnmsub_s(a: m128, b: m128, c: m128) -> m128 { - unsafe { transmute(__lsx_vfnmsub_s(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfnmsub_d(a: m128d, b: m128d, c: m128d) -> m128d { - unsafe { transmute(__lsx_vfnmsub_d(transmute(a), transmute(b), transmute(c))) } -} - #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5003,48 +2350,6 @@ pub fn lsx_vfrintrne_d(a: m128d) -> m128d { unsafe { transmute(__lsx_vfrintrne_d(transmute(a))) } } -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfrintrz_s(a: m128) -> m128 { - unsafe { transmute(__lsx_vfrintrz_s(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfrintrz_d(a: m128d) -> m128d { - unsafe { transmute(__lsx_vfrintrz_d(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfrintrp_s(a: m128) -> m128 { - unsafe { transmute(__lsx_vfrintrp_s(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfrintrp_d(a: m128d) -> m128d { - unsafe { transmute(__lsx_vfrintrp_d(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfrintrm_s(a: m128) -> m128 { - unsafe { transmute(__lsx_vfrintrm_s(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfrintrm_d(a: m128d) -> m128d { - unsafe { transmute(__lsx_vfrintrm_d(transmute(a))) } -} - #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2, 3)] @@ -5052,7 +2357,7 @@ pub fn lsx_vfrintrm_d(a: m128d) -> m128d { pub unsafe fn lsx_vstelm_b(a: m128i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM4, 4); - transmute(__lsx_vstelm_b(transmute(a), mem_addr, IMM_S8, IMM4)) + __lsx_vstelm_b(transmute(a), mem_addr, IMM_S8, IMM4) } #[inline] @@ -5062,7 +2367,7 @@ pub unsafe fn lsx_vstelm_b(a: m128i, mem_add pub unsafe fn lsx_vstelm_h(a: m128i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM3, 3); - transmute(__lsx_vstelm_h(transmute(a), mem_addr, IMM_S8, IMM3)) + __lsx_vstelm_h(transmute(a), mem_addr, IMM_S8, IMM3) } #[inline] @@ -5072,7 +2377,7 @@ pub unsafe fn lsx_vstelm_h(a: m128i, mem_add pub unsafe fn lsx_vstelm_w(a: m128i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM2, 2); - transmute(__lsx_vstelm_w(transmute(a), mem_addr, IMM_S8, IMM2)) + __lsx_vstelm_w(transmute(a), mem_addr, IMM_S8, IMM2) } #[inline] @@ -5082,7 +2387,7 @@ pub unsafe fn lsx_vstelm_w(a: m128i, mem_add pub unsafe fn lsx_vstelm_d(a: m128i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM1, 1); - transmute(__lsx_vstelm_d(transmute(a), mem_addr, IMM_S8, IMM1)) + __lsx_vstelm_d(transmute(a), mem_addr, IMM_S8, IMM1) } #[inline] @@ -5729,34 +3034,6 @@ pub fn lsx_vmaddwod_q_du_d(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwod_q_du_d(transmute(a), transmute(b), transmute(c))) } } -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vrotr_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vrotr_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vrotr_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vrotr_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vrotr_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vrotr_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vrotr_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vrotr_d(transmute(a), transmute(b))) } -} - #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5877,42 +3154,6 @@ pub fn lsx_vexth_qu_du(a: m128i) -> m128i { unsafe { transmute(__lsx_vexth_qu_du(transmute(a))) } } -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vrotri_b(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vrotri_b(transmute(a), IMM3)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vrotri_h(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vrotri_h(transmute(a), IMM4)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vrotri_w(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vrotri_w(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vrotri_d(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lsx_vrotri_d(transmute(a), IMM6)) } -} - #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6361,24 +3602,6 @@ pub fn lsx_vpermi_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vpermi_w(transmute(a), transmute(b), IMM8)) } } -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn lsx_vld(mem_addr: *const i8) -> m128i { - static_assert_simm_bits!(IMM_S12, 12); - transmute(__lsx_vld(mem_addr, IMM_S12)) -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn lsx_vst(a: m128i, mem_addr: *mut i8) { - static_assert_simm_bits!(IMM_S12, 12); - transmute(__lsx_vst(transmute(a), mem_addr, IMM_S12)) -} - #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6421,22 +3644,6 @@ pub fn lsx_vssrln_w_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrln_w_d(transmute(a), transmute(b))) } } -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vorn_v(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vorn_v(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(0)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vldi() -> m128i { - static_assert_simm_bits!(IMM_S13, 13); - unsafe { transmute(__lsx_vldi(IMM_S13)) } -} - #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6444,20 +3651,6 @@ pub fn lsx_vshuf_b(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vshuf_b(transmute(a), transmute(b), transmute(c))) } } -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn lsx_vldx(mem_addr: *const i8, b: i64) -> m128i { - transmute(__lsx_vldx(mem_addr, transmute(b))) -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn lsx_vstx(a: m128i, mem_addr: *mut i8, b: i64) { - transmute(__lsx_vstx(transmute(a), mem_addr, transmute(b))) -} - #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6842,39 +4035,3 @@ pub fn lsx_vfcmp_sune_s(a: m128, b: m128) -> m128i { pub fn lsx_vfcmp_sun_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_sun_s(transmute(a), transmute(b))) } } - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(0)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vrepli_b() -> m128i { - static_assert_simm_bits!(IMM_S10, 10); - unsafe { transmute(__lsx_vrepli_b(IMM_S10)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(0)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vrepli_d() -> m128i { - static_assert_simm_bits!(IMM_S10, 10); - unsafe { transmute(__lsx_vrepli_d(IMM_S10)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(0)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vrepli_h() -> m128i { - static_assert_simm_bits!(IMM_S10, 10); - unsafe { transmute(__lsx_vrepli_h(IMM_S10)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(0)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vrepli_w() -> m128i { - static_assert_simm_bits!(IMM_S10, 10); - unsafe { transmute(__lsx_vrepli_w(IMM_S10)) } -} diff --git a/library/stdarch/crates/core_arch/src/loongarch64/lsx/mod.rs b/library/stdarch/crates/core_arch/src/loongarch64/lsx/mod.rs index 67a08985a9637..0d353746ea859 100644 --- a/library/stdarch/crates/core_arch/src/loongarch64/lsx/mod.rs +++ b/library/stdarch/crates/core_arch/src/loongarch64/lsx/mod.rs @@ -16,6 +16,13 @@ mod generated; #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub use self::generated::*; +#[rustfmt::skip] +mod portable; + +#[rustfmt::skip] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub use self::portable::*; + #[rustfmt::skip] #[cfg(test)] mod tests; diff --git a/library/stdarch/crates/core_arch/src/loongarch64/lsx/portable.rs b/library/stdarch/crates/core_arch/src/loongarch64/lsx/portable.rs new file mode 100644 index 0000000000000..31467bf013e27 --- /dev/null +++ b/library/stdarch/crates/core_arch/src/loongarch64/lsx/portable.rs @@ -0,0 +1,743 @@ +//! LoongArch64 LSX intrinsics - intrinsics::simd implementation + +use super::super::{simd::*, *}; +use crate::core_arch::simd::*; +use crate::intrinsics::simd::*; +use crate::mem::transmute; + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_pickev_b(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_pickev_h(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 2, 4, 6, 8, 10, 12, 14]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_pickev_w(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 2, 4, 6]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_pickev_d(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 2]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_pickod_b(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_pickod_h(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 3, 5, 7, 9, 11, 13, 15]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_pickod_w(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 3, 5, 7]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_pickod_d(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 3]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_ilvh_b(a: T, b: T) -> T { + simd_shuffle!(b, a, [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_ilvh_h(a: T, b: T) -> T { + simd_shuffle!(b, a, [4, 12, 5, 13, 6, 14, 7, 15]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_ilvh_w(a: T, b: T) -> T { + simd_shuffle!(b, a, [2, 6, 3, 7]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_ilvh_d(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 3]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_ilvl_b(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_ilvl_h(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 8, 1, 9, 2, 10, 3, 11]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_ilvl_w(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 4, 1, 5]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_ilvl_d(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 2]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_replvei_b(a: T) -> T { + simd_shuffle!(a, a, [I, I, I, I, I, I, I, I, I, I, I, I, I, I, I, I]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_replvei_h(a: T) -> T { + simd_shuffle!(a, a, [I, I, I, I, I, I, I, I]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_replvei_w(a: T) -> T { + simd_shuffle!(a, a, [I, I, I, I]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_replvei_d(a: T) -> T { + simd_shuffle!(a, a, [I, I]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_packev_b(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_packev_h(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 8, 2, 10, 4, 12, 6, 14]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_packev_w(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 4, 2, 6]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_packev_d(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 2]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_packod_b(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_packod_h(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 9, 3, 11, 5, 13, 7, 15]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_packod_w(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 5, 3, 7]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_packod_d(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 3]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_shuf4i_b(a: T) -> T { + simd_shuffle!( + a, + a, + [ + ((I >> 0) & 3) + 0, ((I >> 2) & 3) + 0, ((I >> 4) & 3) + 0, ((I >> 6) & 3) + 0, + ((I >> 0) & 3) + 4, ((I >> 2) & 3) + 4, ((I >> 4) & 3) + 4, ((I >> 6) & 3) + 4, + ((I >> 0) & 3) + 8, ((I >> 2) & 3) + 8, ((I >> 4) & 3) + 8, ((I >> 6) & 3) + 8, + ((I >> 0) & 3) + 12, ((I >> 2) & 3) + 12, ((I >> 4) & 3) + 12, ((I >> 6) & 3) + 12 + ] + ) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_shuf4i_h(a: T) -> T { + simd_shuffle!( + a, + a, + [ + ((I >> 0) & 3) + 0, ((I >> 2) & 3) + 0, ((I >> 4) & 3) + 0, ((I >> 6) & 3) + 0, + ((I >> 0) & 3) + 4, ((I >> 2) & 3) + 4, ((I >> 4) & 3) + 4, ((I >> 6) & 3) + 4 + ] + ) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_shuf4i_w(a: T) -> T { + simd_shuffle!(a, a, [((I >> 0) & 3), ((I >> 2) & 3), ((I >> 4) & 3), ((I >> 6) & 3)]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_ext_shuf4i_d(a: T, b: T) -> T { + simd_shuffle!(a, b, [((I >> 0) & 3), ((I >> 2) & 3)]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_bsll(a: T) -> T { + let z = simd_ext_splat(0); + match I & 0xf { + 0 => simd_shuffle!(a, z, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + 1 => simd_shuffle!(a, z, [16, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14]), + 2 => simd_shuffle!(a, z, [16, 16, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13]), + 3 => simd_shuffle!(a, z, [16, 16, 16, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12]), + 4 => simd_shuffle!(a, z, [16, 16, 16, 16, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11]), + 5 => simd_shuffle!(a, z, [16, 16, 16, 16, 16, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10]), + 6 => simd_shuffle!(a, z, [16, 16, 16, 16, 16, 16, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9]), + 7 => simd_shuffle!(a, z, [16, 16, 16, 16, 16, 16, 16, 0, 1, 2, 3, 4, 5, 6, 7, 8]), + 8 => simd_shuffle!(a, z, [16, 16, 16, 16, 16, 16, 16, 16, 0, 1, 2, 3, 4, 5, 6, 7]), + 9 => simd_shuffle!(a, z, [16, 16, 16, 16, 16, 16, 16, 16, 16, 0, 1, 2, 3, 4, 5, 6]), + 10 => simd_shuffle!(a, z, [16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 0, 1, 2, 3, 4, 5]), + 11 => simd_shuffle!(a, z, [16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 0, 1, 2, 3, 4]), + 12 => simd_shuffle!(a, z, [16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 0, 1, 2, 3]), + 13 => simd_shuffle!(a, z, [16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 0, 1, 2]), + 14 => simd_shuffle!(a, z, [16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 0, 1]), + 15 => simd_shuffle!(a, z, [16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 0]), + _ => unreachable!(), + } +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_bsrl(a: T) -> T { + let z = simd_ext_splat(0); + match I & 0xf { + 0 => simd_shuffle!(a, z, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + 1 => simd_shuffle!(a, z, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), + 2 => simd_shuffle!(a, z, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16]), + 3 => simd_shuffle!(a, z, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16, 16]), + 4 => simd_shuffle!(a, z, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16, 16, 16]), + 5 => simd_shuffle!(a, z, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16, 16, 16, 16]), + 6 => simd_shuffle!(a, z, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16, 16, 16, 16, 16]), + 7 => simd_shuffle!(a, z, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16]), + 8 => simd_shuffle!(a, z, [8, 9, 10, 11, 12, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16, 16]), + 9 => simd_shuffle!(a, z, [9, 10, 11, 12, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16, 16, 16]), + 10 => simd_shuffle!(a, z, [10, 11, 12, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16]), + 11 => simd_shuffle!(a, z, [11, 12, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16]), + 12 => simd_shuffle!(a, z, [12, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16]), + 13 => simd_shuffle!(a, z, [13, 14, 15, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16]), + 14 => simd_shuffle!(a, z, [14, 15, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16]), + 15 => simd_shuffle!(a, z, [15, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16]), + _ => unreachable!(), + } +} + +impl_vv!("lsx", lsx_vpcnt_b, simd_ctpop, m128i, i8x16); +impl_vv!("lsx", lsx_vpcnt_h, simd_ctpop, m128i, i16x8); +impl_vv!("lsx", lsx_vpcnt_w, simd_ctpop, m128i, i32x4); +impl_vv!("lsx", lsx_vpcnt_d, simd_ctpop, m128i, i64x2); +impl_vv!("lsx", lsx_vclz_b, simd_ctlz, m128i, i8x16); +impl_vv!("lsx", lsx_vclz_h, simd_ctlz, m128i, i16x8); +impl_vv!("lsx", lsx_vclz_w, simd_ctlz, m128i, i32x4); +impl_vv!("lsx", lsx_vclz_d, simd_ctlz, m128i, i64x2); +impl_vv!("lsx", lsx_vneg_b, simd_neg, m128i, i8x16); +impl_vv!("lsx", lsx_vneg_h, simd_neg, m128i, i16x8); +impl_vv!("lsx", lsx_vneg_w, simd_neg, m128i, i32x4); +impl_vv!("lsx", lsx_vneg_d, simd_neg, m128i, i64x2); +impl_vv!("lsx", lsx_vfsqrt_s, simd_fsqrt, m128, f32x4); +impl_vv!("lsx", lsx_vfsqrt_d, simd_fsqrt, m128d, f64x2); +impl_vv!("lsx", lsx_vfrsqrt_s, simd_ext_frsqrt_s, m128, f32x4); +impl_vv!("lsx", lsx_vfrsqrt_d, simd_ext_frsqrt_d, m128d, f64x2); +impl_vv!("lsx", lsx_vfrecip_s, simd_ext_frecip_s, m128, f32x4); +impl_vv!("lsx", lsx_vfrecip_d, simd_ext_frecip_d, m128d, f64x2); +impl_vv!("lsx", lsx_vfrintrp_s, simd_ceil, m128, f32x4); +impl_vv!("lsx", lsx_vfrintrp_d, simd_ceil, m128d, f64x2); +impl_vv!("lsx", lsx_vfrintrm_s, simd_floor, m128, f32x4); +impl_vv!("lsx", lsx_vfrintrm_d, simd_floor, m128d, f64x2); +impl_vv!("lsx", lsx_vfrintrz_s, simd_trunc, m128, f32x4); +impl_vv!("lsx", lsx_vfrintrz_d, simd_trunc, m128d, f64x2); + +impl_gv!("lsx", lsx_vreplgr2vr_b, simd_ext_splat, m128i, i8x16, i32); +impl_gv!("lsx", lsx_vreplgr2vr_h, simd_ext_splat, m128i, i16x8, i32); +impl_gv!("lsx", lsx_vreplgr2vr_w, simd_ext_splat, m128i, i32x4, i32); +impl_gv!("lsx", lsx_vreplgr2vr_d, simd_ext_splat, m128i, i64x2, i64); + +impl_ggv!("lsx", lsx_vldx, simd_ext_ldx, m128i, i8x16, *const i8, i64, unsafe); + +impl_gsv!("lsx", lsx_vld, simd_ext_ld, m128i, i8x16, *const i8, 12, const, unsafe); + +impl_sv!("lsx", lsx_vrepli_b, simd_ext_splat, m128i, i8x16, 10); +impl_sv!("lsx", lsx_vrepli_h, simd_ext_splat, m128i, i16x8, 10); +impl_sv!("lsx", lsx_vrepli_w, simd_ext_splat, m128i, i32x4, 10); +impl_sv!("lsx", lsx_vrepli_d, simd_ext_splat, m128i, i64x2, 10); +impl_sv!("lsx", lsx_vldi, simd_ext_ldi, m128i, i64x2, 13, const); + +impl_vvv!("lsx", lsx_vadd_b, simd_add, m128i, i8x16); +impl_vvv!("lsx", lsx_vadd_h, simd_add, m128i, i16x8); +impl_vvv!("lsx", lsx_vadd_w, simd_add, m128i, i32x4); +impl_vvv!("lsx", lsx_vadd_d, simd_add, m128i, i64x2); +impl_vvv!("lsx", lsx_vsub_b, simd_sub, m128i, i8x16); +impl_vvv!("lsx", lsx_vsub_h, simd_sub, m128i, i16x8); +impl_vvv!("lsx", lsx_vsub_w, simd_sub, m128i, i32x4); +impl_vvv!("lsx", lsx_vsub_d, simd_sub, m128i, i64x2); +impl_vvv!("lsx", lsx_vmax_b, simd_imax, m128i, i8x16); +impl_vvv!("lsx", lsx_vmax_h, simd_imax, m128i, i16x8); +impl_vvv!("lsx", lsx_vmax_w, simd_imax, m128i, i32x4); +impl_vvv!("lsx", lsx_vmax_d, simd_imax, m128i, i64x2); +impl_vvv!("lsx", lsx_vmax_bu, simd_imax, m128i, u8x16); +impl_vvv!("lsx", lsx_vmax_hu, simd_imax, m128i, u16x8); +impl_vvv!("lsx", lsx_vmax_wu, simd_imax, m128i, u32x4); +impl_vvv!("lsx", lsx_vmax_du, simd_imax, m128i, u64x2); +impl_vvv!("lsx", lsx_vmin_b, simd_imin, m128i, i8x16); +impl_vvv!("lsx", lsx_vmin_h, simd_imin, m128i, i16x8); +impl_vvv!("lsx", lsx_vmin_w, simd_imin, m128i, i32x4); +impl_vvv!("lsx", lsx_vmin_d, simd_imin, m128i, i64x2); +impl_vvv!("lsx", lsx_vmin_bu, simd_imin, m128i, u8x16); +impl_vvv!("lsx", lsx_vmin_hu, simd_imin, m128i, u16x8); +impl_vvv!("lsx", lsx_vmin_wu, simd_imin, m128i, u32x4); +impl_vvv!("lsx", lsx_vmin_du, simd_imin, m128i, u64x2); +impl_vvv!("lsx", lsx_vseq_b, simd_eq, m128i, i8x16); +impl_vvv!("lsx", lsx_vseq_h, simd_eq, m128i, i16x8); +impl_vvv!("lsx", lsx_vseq_w, simd_eq, m128i, i32x4); +impl_vvv!("lsx", lsx_vseq_d, simd_eq, m128i, i64x2); +impl_vvv!("lsx", lsx_vslt_b, simd_lt, m128i, i8x16); +impl_vvv!("lsx", lsx_vslt_h, simd_lt, m128i, i16x8); +impl_vvv!("lsx", lsx_vslt_w, simd_lt, m128i, i32x4); +impl_vvv!("lsx", lsx_vslt_d, simd_lt, m128i, i64x2); +impl_vvv!("lsx", lsx_vslt_bu, simd_lt, m128i, u8x16); +impl_vvv!("lsx", lsx_vslt_hu, simd_lt, m128i, u16x8); +impl_vvv!("lsx", lsx_vslt_wu, simd_lt, m128i, u32x4); +impl_vvv!("lsx", lsx_vslt_du, simd_lt, m128i, u64x2); +impl_vvv!("lsx", lsx_vsle_b, simd_le, m128i, i8x16); +impl_vvv!("lsx", lsx_vsle_h, simd_le, m128i, i16x8); +impl_vvv!("lsx", lsx_vsle_w, simd_le, m128i, i32x4); +impl_vvv!("lsx", lsx_vsle_d, simd_le, m128i, i64x2); +impl_vvv!("lsx", lsx_vsle_bu, simd_le, m128i, u8x16); +impl_vvv!("lsx", lsx_vsle_hu, simd_le, m128i, u16x8); +impl_vvv!("lsx", lsx_vsle_wu, simd_le, m128i, u32x4); +impl_vvv!("lsx", lsx_vsle_du, simd_le, m128i, u64x2); +impl_vvv!("lsx", lsx_vmul_b, simd_mul, m128i, i8x16); +impl_vvv!("lsx", lsx_vmul_h, simd_mul, m128i, i16x8); +impl_vvv!("lsx", lsx_vmul_w, simd_mul, m128i, i32x4); +impl_vvv!("lsx", lsx_vmul_d, simd_mul, m128i, i64x2); +impl_vvv!("lsx", lsx_vdiv_b, simd_div, m128i, i8x16); +impl_vvv!("lsx", lsx_vdiv_h, simd_div, m128i, i16x8); +impl_vvv!("lsx", lsx_vdiv_w, simd_div, m128i, i32x4); +impl_vvv!("lsx", lsx_vdiv_d, simd_div, m128i, i64x2); +impl_vvv!("lsx", lsx_vdiv_bu, simd_div, m128i, u8x16); +impl_vvv!("lsx", lsx_vdiv_hu, simd_div, m128i, u16x8); +impl_vvv!("lsx", lsx_vdiv_wu, simd_div, m128i, u32x4); +impl_vvv!("lsx", lsx_vdiv_du, simd_div, m128i, u64x2); +impl_vvv!("lsx", lsx_vmod_b, simd_rem, m128i, i8x16); +impl_vvv!("lsx", lsx_vmod_h, simd_rem, m128i, i16x8); +impl_vvv!("lsx", lsx_vmod_w, simd_rem, m128i, i32x4); +impl_vvv!("lsx", lsx_vmod_d, simd_rem, m128i, i64x2); +impl_vvv!("lsx", lsx_vmod_bu, simd_rem, m128i, u8x16); +impl_vvv!("lsx", lsx_vmod_hu, simd_rem, m128i, u16x8); +impl_vvv!("lsx", lsx_vmod_wu, simd_rem, m128i, u32x4); +impl_vvv!("lsx", lsx_vmod_du, simd_rem, m128i, u64x2); +impl_vvv!("lsx", lsx_vand_v, simd_and, m128i, u8x16); +impl_vvv!("lsx", lsx_vandn_v, simd_ext_andn, m128i, u8x16); +impl_vvv!("lsx", lsx_vor_v, simd_or, m128i, u8x16); +impl_vvv!("lsx", lsx_vorn_v, simd_ext_orn, m128i, u8x16); +impl_vvv!("lsx", lsx_vnor_v, simd_ext_nor, m128i, u8x16); +impl_vvv!("lsx", lsx_vxor_v, simd_xor, m128i, u8x16); +impl_vvv!("lsx", lsx_vfadd_s, simd_add, m128, f32x4); +impl_vvv!("lsx", lsx_vfadd_d, simd_add, m128d, f64x2); +impl_vvv!("lsx", lsx_vfsub_s, simd_sub, m128, f32x4); +impl_vvv!("lsx", lsx_vfsub_d, simd_sub, m128d, f64x2); +impl_vvv!("lsx", lsx_vfmul_s, simd_mul, m128, f32x4); +impl_vvv!("lsx", lsx_vfmul_d, simd_mul, m128d, f64x2); +impl_vvv!("lsx", lsx_vfdiv_s, simd_div, m128, f32x4); +impl_vvv!("lsx", lsx_vfdiv_d, simd_div, m128d, f64x2); +impl_vvv!("lsx", lsx_vsll_b, simd_ext_shl, m128i, i8x16); +impl_vvv!("lsx", lsx_vsll_h, simd_ext_shl, m128i, i16x8); +impl_vvv!("lsx", lsx_vsll_w, simd_ext_shl, m128i, i32x4); +impl_vvv!("lsx", lsx_vsll_d, simd_ext_shl, m128i, i64x2); +impl_vvv!("lsx", lsx_vsra_b, simd_ext_shr, m128i, i8x16); +impl_vvv!("lsx", lsx_vsra_h, simd_ext_shr, m128i, i16x8); +impl_vvv!("lsx", lsx_vsra_w, simd_ext_shr, m128i, i32x4); +impl_vvv!("lsx", lsx_vsra_d, simd_ext_shr, m128i, i64x2); +impl_vvv!("lsx", lsx_vsrl_b, simd_ext_shr, m128i, u8x16); +impl_vvv!("lsx", lsx_vsrl_h, simd_ext_shr, m128i, u16x8); +impl_vvv!("lsx", lsx_vsrl_w, simd_ext_shr, m128i, u32x4); +impl_vvv!("lsx", lsx_vsrl_d, simd_ext_shr, m128i, u64x2); +impl_vvv!("lsx", lsx_vrotr_b, simd_ext_rotr, m128i, u8x16); +impl_vvv!("lsx", lsx_vrotr_h, simd_ext_rotr, m128i, u16x8); +impl_vvv!("lsx", lsx_vrotr_w, simd_ext_rotr, m128i, u32x4); +impl_vvv!("lsx", lsx_vrotr_d, simd_ext_rotr, m128i, u64x2); +impl_vvv!("lsx", lsx_vbitclr_b, simd_ext_bitclr, m128i, u8x16); +impl_vvv!("lsx", lsx_vbitclr_h, simd_ext_bitclr, m128i, u16x8); +impl_vvv!("lsx", lsx_vbitclr_w, simd_ext_bitclr, m128i, u32x4); +impl_vvv!("lsx", lsx_vbitclr_d, simd_ext_bitclr, m128i, u64x2); +impl_vvv!("lsx", lsx_vbitset_b, simd_ext_bitset, m128i, u8x16); +impl_vvv!("lsx", lsx_vbitset_h, simd_ext_bitset, m128i, u16x8); +impl_vvv!("lsx", lsx_vbitset_w, simd_ext_bitset, m128i, u32x4); +impl_vvv!("lsx", lsx_vbitset_d, simd_ext_bitset, m128i, u64x2); +impl_vvv!("lsx", lsx_vbitrev_b, simd_ext_bitrev, m128i, u8x16); +impl_vvv!("lsx", lsx_vbitrev_h, simd_ext_bitrev, m128i, u16x8); +impl_vvv!("lsx", lsx_vbitrev_w, simd_ext_bitrev, m128i, u32x4); +impl_vvv!("lsx", lsx_vbitrev_d, simd_ext_bitrev, m128i, u64x2); +impl_vvv!("lsx", lsx_vsadd_b, simd_saturating_add, m128i, i8x16); +impl_vvv!("lsx", lsx_vsadd_h, simd_saturating_add, m128i, i16x8); +impl_vvv!("lsx", lsx_vsadd_w, simd_saturating_add, m128i, i32x4); +impl_vvv!("lsx", lsx_vsadd_d, simd_saturating_add, m128i, i64x2); +impl_vvv!("lsx", lsx_vsadd_bu, simd_saturating_add, m128i, u8x16); +impl_vvv!("lsx", lsx_vsadd_hu, simd_saturating_add, m128i, u16x8); +impl_vvv!("lsx", lsx_vsadd_wu, simd_saturating_add, m128i, u32x4); +impl_vvv!("lsx", lsx_vsadd_du, simd_saturating_add, m128i, u64x2); +impl_vvv!("lsx", lsx_vssub_b, simd_saturating_sub, m128i, i8x16); +impl_vvv!("lsx", lsx_vssub_h, simd_saturating_sub, m128i, i16x8); +impl_vvv!("lsx", lsx_vssub_w, simd_saturating_sub, m128i, i32x4); +impl_vvv!("lsx", lsx_vssub_d, simd_saturating_sub, m128i, i64x2); +impl_vvv!("lsx", lsx_vssub_bu, simd_saturating_sub, m128i, u8x16); +impl_vvv!("lsx", lsx_vssub_hu, simd_saturating_sub, m128i, u16x8); +impl_vvv!("lsx", lsx_vssub_wu, simd_saturating_sub, m128i, u32x4); +impl_vvv!("lsx", lsx_vssub_du, simd_saturating_sub, m128i, u64x2); +impl_vvv!("lsx", lsx_vadda_b, simd_ext_adda, m128i, i8x16); +impl_vvv!("lsx", lsx_vadda_h, simd_ext_adda, m128i, i16x8); +impl_vvv!("lsx", lsx_vadda_w, simd_ext_adda, m128i, i32x4); +impl_vvv!("lsx", lsx_vadda_d, simd_ext_adda, m128i, i64x2); +impl_vvv!("lsx", lsx_vabsd_b, simd_ext_absd, m128i, i8x16); +impl_vvv!("lsx", lsx_vabsd_h, simd_ext_absd, m128i, i16x8); +impl_vvv!("lsx", lsx_vabsd_w, simd_ext_absd, m128i, i32x4); +impl_vvv!("lsx", lsx_vabsd_d, simd_ext_absd, m128i, i64x2); +impl_vvv!("lsx", lsx_vabsd_bu, simd_ext_absd, m128i, u8x16); +impl_vvv!("lsx", lsx_vabsd_hu, simd_ext_absd, m128i, u16x8); +impl_vvv!("lsx", lsx_vabsd_wu, simd_ext_absd, m128i, u32x4); +impl_vvv!("lsx", lsx_vabsd_du, simd_ext_absd, m128i, u64x2); +impl_vvv!("lsx", lsx_vmuh_b, simd_ext_muh, m128i, i8x16, i16x16); +impl_vvv!("lsx", lsx_vmuh_h, simd_ext_muh, m128i, i16x8, i32x8); +impl_vvv!("lsx", lsx_vmuh_w, simd_ext_muh, m128i, i32x4, i64x4); +impl_vvv!("lsx", lsx_vmuh_d, simd_ext_muh, m128i, i64x2, i128x2); +impl_vvv!("lsx", lsx_vmuh_bu, simd_ext_muh, m128i, u8x16, u16x16); +impl_vvv!("lsx", lsx_vmuh_hu, simd_ext_muh, m128i, u16x8, u32x8); +impl_vvv!("lsx", lsx_vmuh_wu, simd_ext_muh, m128i, u32x4, u64x4); +impl_vvv!("lsx", lsx_vmuh_du, simd_ext_muh, m128i, u64x2, u128x2); +impl_vvv!("lsx", lsx_vpickev_b, simd_ext_pickev_b, m128i, i8x16); +impl_vvv!("lsx", lsx_vpickev_h, simd_ext_pickev_h, m128i, i16x8); +impl_vvv!("lsx", lsx_vpickev_w, simd_ext_pickev_w, m128i, i32x4); +impl_vvv!("lsx", lsx_vpickev_d, simd_ext_pickev_d, m128i, i64x2); +impl_vvv!("lsx", lsx_vpickod_b, simd_ext_pickod_b, m128i, i8x16); +impl_vvv!("lsx", lsx_vpickod_h, simd_ext_pickod_h, m128i, i16x8); +impl_vvv!("lsx", lsx_vpickod_w, simd_ext_pickod_w, m128i, i32x4); +impl_vvv!("lsx", lsx_vpickod_d, simd_ext_pickod_d, m128i, i64x2); +impl_vvv!("lsx", lsx_vilvh_b, simd_ext_ilvh_b, m128i, i8x16); +impl_vvv!("lsx", lsx_vilvh_h, simd_ext_ilvh_h, m128i, i16x8); +impl_vvv!("lsx", lsx_vilvh_w, simd_ext_ilvh_w, m128i, i32x4); +impl_vvv!("lsx", lsx_vilvh_d, simd_ext_ilvh_d, m128i, i64x2); +impl_vvv!("lsx", lsx_vilvl_b, simd_ext_ilvl_b, m128i, i8x16); +impl_vvv!("lsx", lsx_vilvl_h, simd_ext_ilvl_h, m128i, i16x8); +impl_vvv!("lsx", lsx_vilvl_w, simd_ext_ilvl_w, m128i, i32x4); +impl_vvv!("lsx", lsx_vilvl_d, simd_ext_ilvl_d, m128i, i64x2); +impl_vvv!("lsx", lsx_vpackev_b, simd_ext_packev_b, m128i, i8x16); +impl_vvv!("lsx", lsx_vpackev_h, simd_ext_packev_h, m128i, i16x8); +impl_vvv!("lsx", lsx_vpackev_w, simd_ext_packev_w, m128i, i32x4); +impl_vvv!("lsx", lsx_vpackev_d, simd_ext_packev_d, m128i, i64x2); +impl_vvv!("lsx", lsx_vpackod_b, simd_ext_packod_b, m128i, i8x16); +impl_vvv!("lsx", lsx_vpackod_h, simd_ext_packod_h, m128i, i16x8); +impl_vvv!("lsx", lsx_vpackod_w, simd_ext_packod_w, m128i, i32x4); +impl_vvv!("lsx", lsx_vpackod_d, simd_ext_packod_d, m128i, i64x2); + +impl_vgg!("lsx", lsx_vstx, simd_ext_stx, m128i, i8x16, *mut i8, i64, unsafe); + +impl_vgs!("lsx", lsx_vst, simd_ext_st, m128i, i8x16, *mut i8, 12, const, unsafe); + +impl_vuv!("lsx", lsx_vslli_b, simd_shl, m128i, i8x16); +impl_vuv!("lsx", lsx_vslli_h, simd_shl, m128i, i16x8); +impl_vuv!("lsx", lsx_vslli_w, simd_shl, m128i, i32x4); +impl_vuv!("lsx", lsx_vslli_d, simd_shl, m128i, i64x2); +impl_vuv!("lsx", lsx_vsrai_b, simd_shr, m128i, i8x16); +impl_vuv!("lsx", lsx_vsrai_h, simd_shr, m128i, i16x8); +impl_vuv!("lsx", lsx_vsrai_w, simd_shr, m128i, i32x4); +impl_vuv!("lsx", lsx_vsrai_d, simd_shr, m128i, i64x2); +impl_vuv!("lsx", lsx_vsrli_b, simd_shr, m128i, u8x16); +impl_vuv!("lsx", lsx_vsrli_h, simd_shr, m128i, u16x8); +impl_vuv!("lsx", lsx_vsrli_w, simd_shr, m128i, u32x4); +impl_vuv!("lsx", lsx_vsrli_d, simd_shr, m128i, u64x2); +impl_vuv!("lsx", lsx_vrotri_b, simd_ext_rotr, m128i, u8x16); +impl_vuv!("lsx", lsx_vrotri_h, simd_ext_rotr, m128i, u16x8); +impl_vuv!("lsx", lsx_vrotri_w, simd_ext_rotr, m128i, u32x4); +impl_vuv!("lsx", lsx_vrotri_d, simd_ext_rotr, m128i, u64x2); +impl_vuv!("lsx", lsx_vaddi_bu, simd_add, m128i, u8x16, 5); +impl_vuv!("lsx", lsx_vaddi_hu, simd_add, m128i, u16x8, 5); +impl_vuv!("lsx", lsx_vaddi_wu, simd_add, m128i, u32x4, 5); +impl_vuv!("lsx", lsx_vaddi_du, simd_add, m128i, u64x2, 5); +impl_vuv!("lsx", lsx_vslti_bu, simd_lt, m128i, u8x16, 5); +impl_vuv!("lsx", lsx_vslti_hu, simd_lt, m128i, u16x8, 5); +impl_vuv!("lsx", lsx_vslti_wu, simd_lt, m128i, u32x4, 5); +impl_vuv!("lsx", lsx_vslti_du, simd_lt, m128i, u64x2, 5); +impl_vuv!("lsx", lsx_vslei_bu, simd_le, m128i, u8x16, 5); +impl_vuv!("lsx", lsx_vslei_hu, simd_le, m128i, u16x8, 5); +impl_vuv!("lsx", lsx_vslei_wu, simd_le, m128i, u32x4, 5); +impl_vuv!("lsx", lsx_vslei_du, simd_le, m128i, u64x2, 5); +impl_vuv!("lsx", lsx_vmaxi_bu, simd_imax, m128i, u8x16, 5); +impl_vuv!("lsx", lsx_vmaxi_hu, simd_imax, m128i, u16x8, 5); +impl_vuv!("lsx", lsx_vmaxi_wu, simd_imax, m128i, u32x4, 5); +impl_vuv!("lsx", lsx_vmaxi_du, simd_imax, m128i, u64x2, 5); +impl_vuv!("lsx", lsx_vmini_bu, simd_imin, m128i, u8x16, 5); +impl_vuv!("lsx", lsx_vmini_hu, simd_imin, m128i, u16x8, 5); +impl_vuv!("lsx", lsx_vmini_wu, simd_imin, m128i, u32x4, 5); +impl_vuv!("lsx", lsx_vmini_du, simd_imin, m128i, u64x2, 5); +impl_vuv!("lsx", lsx_vreplvei_b, simd_ext_replvei_b, m128i, i8x16, 4, const); +impl_vuv!("lsx", lsx_vreplvei_h, simd_ext_replvei_h, m128i, i16x8, 3, const); +impl_vuv!("lsx", lsx_vreplvei_w, simd_ext_replvei_w, m128i, i32x4, 2, const); +impl_vuv!("lsx", lsx_vreplvei_d, simd_ext_replvei_d, m128i, i64x2, 1, const); +impl_vuv!("lsx", lsx_vshuf4i_b, simd_ext_shuf4i_b, m128i, i8x16, 8, const); +impl_vuv!("lsx", lsx_vshuf4i_h, simd_ext_shuf4i_h, m128i, i16x8, 8, const); +impl_vuv!("lsx", lsx_vshuf4i_w, simd_ext_shuf4i_w, m128i, i32x4, 8, const); +impl_vuv!("lsx", lsx_vbsll_v, simd_ext_bsll, m128i, i8x16, 5, const); +impl_vuv!("lsx", lsx_vbsrl_v, simd_ext_bsrl, m128i, i8x16, 5, const); + +impl_vug!("lsx", lsx_vpickve2gr_b, simd_extract, m128i, i8x16, i32, 4); +impl_vug!("lsx", lsx_vpickve2gr_h, simd_extract, m128i, i16x8, i32, 3); +impl_vug!("lsx", lsx_vpickve2gr_w, simd_extract, m128i, i32x4, i32, 2); +impl_vug!("lsx", lsx_vpickve2gr_d, simd_extract, m128i, i64x2, i64, 1); +impl_vug!("lsx", lsx_vpickve2gr_bu, simd_extract, m128i, u8x16, u32, 4); +impl_vug!("lsx", lsx_vpickve2gr_hu, simd_extract, m128i, u16x8, u32, 3); +impl_vug!("lsx", lsx_vpickve2gr_wu, simd_extract, m128i, u32x4, u32, 2); +impl_vug!("lsx", lsx_vpickve2gr_du, simd_extract, m128i, u64x2, u64, 1); + +impl_vsv!("lsx", lsx_vseqi_b, simd_eq, m128i, i8x16, 5); +impl_vsv!("lsx", lsx_vseqi_h, simd_eq, m128i, i16x8, 5); +impl_vsv!("lsx", lsx_vseqi_w, simd_eq, m128i, i32x4, 5); +impl_vsv!("lsx", lsx_vseqi_d, simd_eq, m128i, i64x2, 5); +impl_vsv!("lsx", lsx_vslti_b, simd_lt, m128i, i8x16, 5); +impl_vsv!("lsx", lsx_vslti_h, simd_lt, m128i, i16x8, 5); +impl_vsv!("lsx", lsx_vslti_w, simd_lt, m128i, i32x4, 5); +impl_vsv!("lsx", lsx_vslti_d, simd_lt, m128i, i64x2, 5); +impl_vsv!("lsx", lsx_vslei_b, simd_le, m128i, i8x16, 5); +impl_vsv!("lsx", lsx_vslei_h, simd_le, m128i, i16x8, 5); +impl_vsv!("lsx", lsx_vslei_w, simd_le, m128i, i32x4, 5); +impl_vsv!("lsx", lsx_vslei_d, simd_le, m128i, i64x2, 5); +impl_vsv!("lsx", lsx_vmaxi_b, simd_imax, m128i, i8x16, 5); +impl_vsv!("lsx", lsx_vmaxi_h, simd_imax, m128i, i16x8, 5); +impl_vsv!("lsx", lsx_vmaxi_w, simd_imax, m128i, i32x4, 5); +impl_vsv!("lsx", lsx_vmaxi_d, simd_imax, m128i, i64x2, 5); +impl_vsv!("lsx", lsx_vmini_b, simd_imin, m128i, i8x16, 5); +impl_vsv!("lsx", lsx_vmini_h, simd_imin, m128i, i16x8, 5); +impl_vsv!("lsx", lsx_vmini_w, simd_imin, m128i, i32x4, 5); +impl_vsv!("lsx", lsx_vmini_d, simd_imin, m128i, i64x2, 5); + +impl_vvvv!("lsx", lsx_vmadd_b, simd_ext_madd, m128i, i8x16); +impl_vvvv!("lsx", lsx_vmadd_h, simd_ext_madd, m128i, i16x8); +impl_vvvv!("lsx", lsx_vmadd_w, simd_ext_madd, m128i, i32x4); +impl_vvvv!("lsx", lsx_vmadd_d, simd_ext_madd, m128i, i64x2); +impl_vvvv!("lsx", lsx_vmsub_b, simd_ext_msub, m128i, i8x16); +impl_vvvv!("lsx", lsx_vmsub_h, simd_ext_msub, m128i, i16x8); +impl_vvvv!("lsx", lsx_vmsub_w, simd_ext_msub, m128i, i32x4); +impl_vvvv!("lsx", lsx_vmsub_d, simd_ext_msub, m128i, i64x2); +impl_vvvv!("lsx", lsx_vfmadd_s, simd_fma, m128, f32x4); +impl_vvvv!("lsx", lsx_vfmadd_d, simd_fma, m128d, f64x2); +impl_vvvv!("lsx", lsx_vfmsub_s, simd_ext_fmsub, m128, f32x4); +impl_vvvv!("lsx", lsx_vfmsub_d, simd_ext_fmsub, m128d, f64x2); +impl_vvvv!("lsx", lsx_vfnmadd_s, simd_ext_fnmadd, m128, f32x4); +impl_vvvv!("lsx", lsx_vfnmadd_d, simd_ext_fnmadd, m128d, f64x2); +impl_vvvv!("lsx", lsx_vfnmsub_s, simd_ext_fnmsub, m128, f32x4); +impl_vvvv!("lsx", lsx_vfnmsub_d, simd_ext_fnmsub, m128d, f64x2); + +impl_vvuv!("lsx", lsx_vshuf4i_d, simd_ext_shuf4i_d, m128i, i64x2, 8, const); + +impl_vugv!("lsx", lsx_vinsgr2vr_b, simd_insert, m128i, i8x16, i32, 4); +impl_vugv!("lsx", lsx_vinsgr2vr_h, simd_insert, m128i, i16x8, i32, 3); +impl_vugv!("lsx", lsx_vinsgr2vr_w, simd_insert, m128i, i32x4, i32, 2); +impl_vugv!("lsx", lsx_vinsgr2vr_d, simd_insert, m128i, i64x2, i64, 1); + +#[cfg(test)] +mod tests { + use crate::{ + core_arch::{loongarch64::*, simd::*}, + mem::transmute, + }; + use std::hint::black_box; + use stdarch_test::simd_test; + + #[simd_test(enable = "lsx")] + unsafe fn vldi() { + let r = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vldi::<0>())); + let r = i8x16::new( + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + ); + assert_eq!(r, transmute(lsx_vldi::<255>())); + let r = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vldi::<1024>())); + let r = i8x16::new(0, -2, 0, -2, 0, -2, 0, -2, 0, -2, 0, -2, 0, -2, 0, -2); + assert_eq!(r, transmute(lsx_vldi::<1536>())); + let r = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vldi::<2048>())); + let r = i8x16::new(0, -2, -1, -1, 0, -2, -1, -1, 0, -2, -1, -1, 0, -2, -1, -1); + assert_eq!(r, transmute(lsx_vldi::<2560>())); + let r = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vldi::<3072>())); + let r = i8x16::new(0, -2, -1, -1, -1, -1, -1, -1, 0, -2, -1, -1, -1, -1, -1, -1); + assert_eq!(r, transmute(lsx_vldi::<3584>())); + let r = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vldi::<-4096>())); + let r = i8x16::new(-128, 0, 0, 0, -128, 0, 0, 0, -128, 0, 0, 0, -128, 0, 0, 0); + assert_eq!(r, transmute(lsx_vldi::<-3968>())); + let r = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vldi::<-3840>())); + let r = i8x16::new(0, -128, 0, 0, 0, -128, 0, 0, 0, -128, 0, 0, 0, -128, 0, 0); + assert_eq!(r, transmute(lsx_vldi::<-3712>())); + let r = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vldi::<-3584>())); + let r = i8x16::new(0, 0, -128, 0, 0, 0, -128, 0, 0, 0, -128, 0, 0, 0, -128, 0); + assert_eq!(r, transmute(lsx_vldi::<-3456>())); + let r = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vldi::<-3328>())); + let r = i8x16::new(0, 0, 0, -128, 0, 0, 0, -128, 0, 0, 0, -128, 0, 0, 0, -128); + assert_eq!(r, transmute(lsx_vldi::<-3200>())); + let r = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vldi::<-3072>())); + let r = i8x16::new( + -128, 0, -128, 0, -128, 0, -128, 0, -128, 0, -128, 0, -128, 0, -128, 0, + ); + assert_eq!(r, transmute(lsx_vldi::<-2944>())); + let r = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vldi::<-2816>())); + let r = i8x16::new( + 0, -128, 0, -128, 0, -128, 0, -128, 0, -128, 0, -128, 0, -128, 0, -128, + ); + assert_eq!(r, transmute(lsx_vldi::<-2688>())); + let r = i8x16::new(-1, 0, 0, 0, -1, 0, 0, 0, -1, 0, 0, 0, -1, 0, 0, 0); + assert_eq!(r, transmute(lsx_vldi::<-2560>())); + let r = i8x16::new( + -1, -128, 0, 0, -1, -128, 0, 0, -1, -128, 0, 0, -1, -128, 0, 0, + ); + assert_eq!(r, transmute(lsx_vldi::<-2432>())); + let r = i8x16::new(-1, -1, 0, 0, -1, -1, 0, 0, -1, -1, 0, 0, -1, -1, 0, 0); + assert_eq!(r, transmute(lsx_vldi::<-2304>())); + let r = i8x16::new( + -1, -1, -128, 0, -1, -1, -128, 0, -1, -1, -128, 0, -1, -1, -128, 0, + ); + assert_eq!(r, transmute(lsx_vldi::<-2176>())); + let r = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vldi::<-2048>())); + let r = i8x16::new( + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + ); + assert_eq!(r, transmute(lsx_vldi::<-1793>())); + let r = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vldi::<-1792>())); + let r = i8x16::new(0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1); + assert_eq!(r, transmute(lsx_vldi::<-1622>())); + let r = i8x16::new(0, 0, 0, 64, 0, 0, 0, 64, 0, 0, 0, 64, 0, 0, 0, 64); + assert_eq!(r, transmute(lsx_vldi::<-1536>())); + let r = i8x16::new(0, 0, 80, -63, 0, 0, 80, -63, 0, 0, 80, -63, 0, 0, 80, -63); + assert_eq!(r, transmute(lsx_vldi::<-1366>())); + let r = i8x16::new(0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 64, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vldi::<-1280>())); + let r = i8x16::new(0, 0, 80, -63, 0, 0, 0, 0, 0, 0, 80, -63, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vldi::<-1110>())); + let r = i8x16::new(0, 0, 0, 0, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 64); + assert_eq!(r, transmute(lsx_vldi::<-1024>())); + let r = i8x16::new(0, 0, 0, 0, 0, 0, 42, -64, 0, 0, 0, 0, 0, 0, 42, -64); + assert_eq!(r, transmute(lsx_vldi::<-854>())); + } + + #[simd_test(enable = "lsx")] + unsafe fn vbsll_v() { + let a = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); + let r = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); + assert_eq!(r, transmute(lsx_vbsll_v::<0>(black_box(transmute(a))))); + let r = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); + assert_eq!(r, transmute(lsx_vbsll_v::<1>(black_box(transmute(a))))); + let r = i8x16::new(0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14); + assert_eq!(r, transmute(lsx_vbsll_v::<2>(black_box(transmute(a))))); + let r = i8x16::new(0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13); + assert_eq!(r, transmute(lsx_vbsll_v::<3>(black_box(transmute(a))))); + let r = i8x16::new(0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12); + assert_eq!(r, transmute(lsx_vbsll_v::<4>(black_box(transmute(a))))); + let r = i8x16::new(0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11); + assert_eq!(r, transmute(lsx_vbsll_v::<5>(black_box(transmute(a))))); + let r = i8x16::new(0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10); + assert_eq!(r, transmute(lsx_vbsll_v::<6>(black_box(transmute(a))))); + let r = i8x16::new(0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9); + assert_eq!(r, transmute(lsx_vbsll_v::<7>(black_box(transmute(a))))); + let r = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8); + assert_eq!(r, transmute(lsx_vbsll_v::<8>(black_box(transmute(a))))); + let r = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7); + assert_eq!(r, transmute(lsx_vbsll_v::<9>(black_box(transmute(a))))); + let r = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6); + assert_eq!(r, transmute(lsx_vbsll_v::<10>(black_box(transmute(a))))); + let r = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5); + assert_eq!(r, transmute(lsx_vbsll_v::<11>(black_box(transmute(a))))); + let r = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4); + assert_eq!(r, transmute(lsx_vbsll_v::<12>(black_box(transmute(a))))); + let r = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3); + assert_eq!(r, transmute(lsx_vbsll_v::<13>(black_box(transmute(a))))); + let r = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2); + assert_eq!(r, transmute(lsx_vbsll_v::<14>(black_box(transmute(a))))); + let r = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1); + assert_eq!(r, transmute(lsx_vbsll_v::<15>(black_box(transmute(a))))); + } + + #[simd_test(enable = "lsx")] + unsafe fn vbsrl_v() { + let a = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); + let r = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); + assert_eq!(r, transmute(lsx_vbsrl_v::<0>(black_box(transmute(a))))); + let r = i8x16::new(2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 0); + assert_eq!(r, transmute(lsx_vbsrl_v::<1>(black_box(transmute(a))))); + let r = i8x16::new(3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 0, 0); + assert_eq!(r, transmute(lsx_vbsrl_v::<2>(black_box(transmute(a))))); + let r = i8x16::new(4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 0, 0, 0); + assert_eq!(r, transmute(lsx_vbsrl_v::<3>(black_box(transmute(a))))); + let r = i8x16::new(5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vbsrl_v::<4>(black_box(transmute(a))))); + let r = i8x16::new(6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 0, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vbsrl_v::<5>(black_box(transmute(a))))); + let r = i8x16::new(7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vbsrl_v::<6>(black_box(transmute(a))))); + let r = i8x16::new(8, 9, 10, 11, 12, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vbsrl_v::<7>(black_box(transmute(a))))); + let r = i8x16::new(9, 10, 11, 12, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vbsrl_v::<8>(black_box(transmute(a))))); + let r = i8x16::new(10, 11, 12, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vbsrl_v::<9>(black_box(transmute(a))))); + let r = i8x16::new(11, 12, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vbsrl_v::<10>(black_box(transmute(a))))); + let r = i8x16::new(12, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vbsrl_v::<11>(black_box(transmute(a))))); + let r = i8x16::new(13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vbsrl_v::<12>(black_box(transmute(a))))); + let r = i8x16::new(14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vbsrl_v::<13>(black_box(transmute(a))))); + let r = i8x16::new(15, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vbsrl_v::<14>(black_box(transmute(a))))); + let r = i8x16::new(16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + assert_eq!(r, transmute(lsx_vbsrl_v::<15>(black_box(transmute(a))))); + } +} diff --git a/library/stdarch/crates/core_arch/src/loongarch64/lsx/tests.rs b/library/stdarch/crates/core_arch/src/loongarch64/lsx/tests.rs index 5670bd4378a84..a08a9992e1d35 100644 --- a/library/stdarch/crates/core_arch/src/loongarch64/lsx/tests.rs +++ b/library/stdarch/crates/core_arch/src/loongarch64/lsx/tests.rs @@ -1,10 +1,11 @@ -// This code is automatically generated. DO NOT MODIFY. +// Auto-generated tests. DO NOT MODIFY. // See crates/stdarch-gen-loongarch/README.md use crate::{ core_arch::{loongarch64::*, simd::*}, mem::transmute, }; +use std::hint::black_box; use stdarch_test::simd_test; #[simd_test(enable = "lsx")] @@ -17,7 +18,10 @@ unsafe fn test_lsx_vsll_b() { ); let r = i64x2::new(70990221811840, -3257029622096690968); - assert_eq!(r, transmute(lsx_vsll_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsll_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -26,7 +30,10 @@ unsafe fn test_lsx_vsll_h() { let b = i16x8::new(-10317, -20778, -9962, -8975, 25298, 12929, -13803, -18669); let r = i64x2::new(-5063658964307128392, -3539825456407336052); - assert_eq!(r, transmute(lsx_vsll_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsll_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -35,7 +42,10 @@ unsafe fn test_lsx_vsll_w() { let b = i32x4::new(82237029, -819106294, -96895338, -456101700); let r = i64x2::new(-7163824029380778240, 2305843009528266752); - assert_eq!(r, transmute(lsx_vsll_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsll_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -44,7 +54,10 @@ unsafe fn test_lsx_vsll_d() { let b = i64x2::new(8592669249977019309, -1379694176202045825); let r = i64x2::new(1790743801833193472, 0); - assert_eq!(r, transmute(lsx_vsll_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsll_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -54,7 +67,7 @@ unsafe fn test_lsx_vslli_b() { ); let r = i64x2::new(-2780807324588213414, -3708578564830607166); - assert_eq!(r, transmute(lsx_vslli_b::<0>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslli_b::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -62,7 +75,7 @@ unsafe fn test_lsx_vslli_h() { let a = i16x8::new(18469, -14840, 23655, -3474, 7467, 2798, -15418, 26847); let r = i64x2::new(-7241759886206301888, 4017476402818337472); - assert_eq!(r, transmute(lsx_vslli_h::<6>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslli_h::<6>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -70,7 +83,7 @@ unsafe fn test_lsx_vslli_w() { let a = i32x4::new(20701902, -1777432355, 6349179, 1747667894); let r = i64x2::new(4189319625752393728, -5967594959501136896); - assert_eq!(r, transmute(lsx_vslli_w::<10>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslli_w::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -78,7 +91,7 @@ unsafe fn test_lsx_vslli_d() { let a = i64x2::new(-5896889635782282086, -8807609320972692839); let r = i64x2::new(-4233027607937510592, -5142337165482896608); - assert_eq!(r, transmute(lsx_vslli_d::<5>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslli_d::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -91,7 +104,10 @@ unsafe fn test_lsx_vsra_b() { ); let r = i64x2::new(-1080315035391229440, 720022881735668484); - assert_eq!(r, transmute(lsx_vsra_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsra_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -100,7 +116,10 @@ unsafe fn test_lsx_vsra_h() { let b = i16x8::new(14017, 3796, 23987, -27244, -13363, 21333, -10262, 23633); let r = i64x2::new(164116464290576704, -1935703552267190275); - assert_eq!(r, transmute(lsx_vsra_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsra_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -109,7 +128,10 @@ unsafe fn test_lsx_vsra_w() { let b = i32x4::new(-670772992, 2044335288, -1224858031, 520588790); let r = i64x2::new(-210763200496, 1619202657181); - assert_eq!(r, transmute(lsx_vsra_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsra_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -118,7 +140,10 @@ unsafe fn test_lsx_vsra_d() { let b = i64x2::new(4251079558060308329, 4657697142994416829); let r = i64x2::new(-623956, 3); - assert_eq!(r, transmute(lsx_vsra_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsra_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -128,7 +153,7 @@ unsafe fn test_lsx_vsrai_b() { ); let r = i64x2::new(-2018743940785760257, -2093355901512246518); - assert_eq!(r, transmute(lsx_vsrai_b::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrai_b::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -136,7 +161,7 @@ unsafe fn test_lsx_vsrai_h() { let a = i16x8::new(-22502, -7299, 19084, -21578, -28082, 20851, 23456, 15524); let r = i64x2::new(-1688828385492998, 844446405361657); - assert_eq!(r, transmute(lsx_vsrai_h::<12>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrai_h::<12>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -144,7 +169,7 @@ unsafe fn test_lsx_vsrai_w() { let a = i32x4::new(743537539, 1831641900, -1639033567, -984629971); let r = i64x2::new(30008936499988, -16131897170029); - assert_eq!(r, transmute(lsx_vsrai_w::<18>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrai_w::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -152,7 +177,7 @@ unsafe fn test_lsx_vsrai_d() { let a = i64x2::new(-8375997486414293750, 1714581574012370587); let r = i64x2::new(-476121, 97462); - assert_eq!(r, transmute(lsx_vsrai_d::<44>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrai_d::<44>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -165,7 +190,13 @@ unsafe fn test_lsx_vsrar_b() { ); let r = i64x2::new(139917463134404866, 143840305941130491); - assert_eq!(r, transmute(lsx_vsrar_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrar_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -174,7 +205,13 @@ unsafe fn test_lsx_vsrar_h() { let b = i16x8::new(-26450, 2176, 31587, 2222, 13726, 30172, 1067, -14273); let r = i64x2::new(-287115463426050, 42950131714); - assert_eq!(r, transmute(lsx_vsrar_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrar_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -183,7 +220,13 @@ unsafe fn test_lsx_vsrar_w() { let b = i32x4::new(-1532076758, 940127488, 1781366421, 1497262222); let r = i64x2::new(7179867468326627830, 560544771735247); - assert_eq!(r, transmute(lsx_vsrar_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrar_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -192,7 +235,13 @@ unsafe fn test_lsx_vsrar_d() { let b = i64x2::new(3571440266112779495, -725943254065719378); let r = i64x2::new(-890187, -17811); - assert_eq!(r, transmute(lsx_vsrar_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrar_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -202,7 +251,7 @@ unsafe fn test_lsx_vsrari_b() { ); let r = i64x2::new(867219992078845182, -503291487652282122); - assert_eq!(r, transmute(lsx_vsrari_b::<3>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrari_b::<3>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -210,7 +259,7 @@ unsafe fn test_lsx_vsrari_h() { let a = i16x8::new(29939, -1699, 12357, 30805, -30883, 31936, 15701, -11818); let r = i64x2::new(4222154715365391, -1688815499411471); - assert_eq!(r, transmute(lsx_vsrari_h::<11>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrari_h::<11>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -218,7 +267,7 @@ unsafe fn test_lsx_vsrari_w() { let a = i32x4::new(588196178, -1058764534, 1325397591, 1169671026); let r = i64x2::new(-4294967295, 4294967297); - assert_eq!(r, transmute(lsx_vsrari_w::<30>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrari_w::<30>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -226,7 +275,7 @@ unsafe fn test_lsx_vsrari_d() { let a = i64x2::new(-2795326946470057100, 6746045132217841338); let r = i64x2::new(-174707934154378569, 421627820763615084); - assert_eq!(r, transmute(lsx_vsrari_d::<4>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrari_d::<4>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -239,7 +288,10 @@ unsafe fn test_lsx_vsrl_b() { ); let r = i64x2::new(1300161376517358116, 72917012339034650); - assert_eq!(r, transmute(lsx_vsrl_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrl_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -248,7 +300,10 @@ unsafe fn test_lsx_vsrl_h() { let b = i16x8::new(16605, -13577, -26644, -17739, 11000, -29283, -15971, 20169); let r = i64x2::new(468374382728249347, 20829178341621860); - assert_eq!(r, transmute(lsx_vsrl_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrl_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -257,7 +312,10 @@ unsafe fn test_lsx_vsrl_w() { let b = i32x4::new(1777885221, -1725401090, 1849724045, -1051851102); let r = i64x2::new(12953227061, 1599606693325790121); - assert_eq!(r, transmute(lsx_vsrl_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrl_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -266,7 +324,10 @@ unsafe fn test_lsx_vsrl_d() { let b = i64x2::new(-7903128394835365398, 7601347629202818185); let r = i64x2::new(649044, 1572171616025062); - assert_eq!(r, transmute(lsx_vsrl_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrl_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -276,7 +337,7 @@ unsafe fn test_lsx_vsrli_b() { ); let r = i64x2::new(1952909805632365845, 3971107439766933248); - assert_eq!(r, transmute(lsx_vsrli_b::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrli_b::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -284,7 +345,7 @@ unsafe fn test_lsx_vsrli_h() { let a = i16x8::new(29545, 354, 27695, 20915, -32766, -24491, 10641, 20310); let r = i64x2::new(11259230996660281, 10977609996304448); - assert_eq!(r, transmute(lsx_vsrli_h::<9>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrli_h::<9>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -292,7 +353,7 @@ unsafe fn test_lsx_vsrli_w() { let a = i32x4::new(627703601, 922874410, -234412645, -1216101872); let r = i64x2::new(3870813506329215, 12913695352717769); - assert_eq!(r, transmute(lsx_vsrli_w::<10>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrli_w::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -300,7 +361,7 @@ unsafe fn test_lsx_vsrli_d() { let a = i64x2::new(1407685950714554203, -6076144426076800688); let r = i64x2::new(9, 85); - assert_eq!(r, transmute(lsx_vsrli_d::<57>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrli_d::<57>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -313,7 +374,13 @@ unsafe fn test_lsx_vsrlr_b() { ); let r = i64x2::new(3317746744565237249, 144420860932066826); - assert_eq!(r, transmute(lsx_vsrlr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrlr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -322,7 +389,13 @@ unsafe fn test_lsx_vsrlr_h() { let b = i16x8::new(19500, -26403, -1282, 12290, -18989, 25105, -24347, 6707); let r = i64x2::new(1991716935204929539, 311033695131730530); - assert_eq!(r, transmute(lsx_vsrlr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrlr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -331,7 +404,13 @@ unsafe fn test_lsx_vsrlr_w() { let b = i32x4::new(1830015593, -1452673200, 962662328, -252736055); let r = i64x2::new(7864089021084, 20473000998469780); - assert_eq!(r, transmute(lsx_vsrlr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrlr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -340,7 +419,13 @@ unsafe fn test_lsx_vsrlr_d() { let b = i64x2::new(-1543621369665313706, 8544381131364512650); let r = i64x2::new(1428972826343, 4256393046182047); - assert_eq!(r, transmute(lsx_vsrlr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrlr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -350,7 +435,7 @@ unsafe fn test_lsx_vsrlri_b() { ); let r = i64x2::new(93866580842851436, 1896906350202744602); - assert_eq!(r, transmute(lsx_vsrlri_b::<1>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrlri_b::<1>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -358,7 +443,7 @@ unsafe fn test_lsx_vsrlri_h() { let a = i16x8::new(-18045, 1968, 22966, 3692, 2010, -17108, 3373, -30706); let r = i64x2::new(1039304252363684227, -8642956144778934310); - assert_eq!(r, transmute(lsx_vsrlri_h::<0>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrlri_h::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -366,7 +451,7 @@ unsafe fn test_lsx_vsrlri_w() { let a = i32x4::new(1306456564, -1401620667, -839707416, -1634862919); let r = i64x2::new(1553353645217275455, 1428132662790218397); - assert_eq!(r, transmute(lsx_vsrlri_w::<3>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrlri_w::<3>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -374,7 +459,7 @@ unsafe fn test_lsx_vsrlri_d() { let a = i64x2::new(-3683179565838693027, 6160461828074490983); let r = i64x2::new(205, 85); - assert_eq!(r, transmute(lsx_vsrlri_d::<56>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrlri_d::<56>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -387,7 +472,13 @@ unsafe fn test_lsx_vbitclr_b() { ); let r = i64x2::new(-7325372782311046420, -5316383129963115396); - assert_eq!(r, transmute(lsx_vbitclr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitclr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -396,7 +487,13 @@ unsafe fn test_lsx_vbitclr_h() { let b = u16x8::new(26587, 57597, 34751, 38678, 23919, 45729, 62569, 5978); let r = i64x2::new(-5495443997997256700, -3317648531059028099); - assert_eq!(r, transmute(lsx_vbitclr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitclr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -405,7 +502,13 @@ unsafe fn test_lsx_vbitclr_w() { let b = u32x4::new(1968231094, 2827365864, 4097273355, 4016923215); let r = i64x2::new(-7626667807832507452, 546969093373761021); - assert_eq!(r, transmute(lsx_vbitclr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitclr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -414,7 +517,13 @@ unsafe fn test_lsx_vbitclr_d() { let b = u64x2::new(5723204188033770667, 2981956604140378920); let r = i64x2::new(-1242851545812588193, -5509634528458855560); - assert_eq!(r, transmute(lsx_vbitclr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitclr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -424,7 +533,7 @@ unsafe fn test_lsx_vbitclri_b() { ); let r = i64x2::new(7503621968728299154, -6865556469255070542); - assert_eq!(r, transmute(lsx_vbitclri_b::<0>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitclri_b::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -432,7 +541,7 @@ unsafe fn test_lsx_vbitclri_h() { let a = u16x8::new(17366, 58985, 22108, 45942, 27326, 19605, 9632, 32322); let r = i64x2::new(-5515130134779575338, 8809640793386347198); - assert_eq!(r, transmute(lsx_vbitclri_h::<10>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitclri_h::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -440,7 +549,7 @@ unsafe fn test_lsx_vbitclri_w() { let a = u32x4::new(718858183, 3771164920, 1842485081, 896350597); let r = i64x2::new(-2249714073768237625, 3849796501707560281); - assert_eq!(r, transmute(lsx_vbitclri_w::<9>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitclri_w::<9>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -448,7 +557,7 @@ unsafe fn test_lsx_vbitclri_d() { let a = u64x2::new(10838658690401820648, 3833745076866321369); let r = i64x2::new(-7608085933063544856, 3833744527110507481); - assert_eq!(r, transmute(lsx_vbitclri_d::<39>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitclri_d::<39>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -461,7 +570,13 @@ unsafe fn test_lsx_vbitset_b() { ); let r = i64x2::new(-7941579666116909337, -8620998056061183460); - assert_eq!(r, transmute(lsx_vbitset_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitset_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -470,7 +585,13 @@ unsafe fn test_lsx_vbitset_h() { let b = u16x8::new(64512, 23847, 57770, 47705, 8024, 31966, 14493, 50266); let r = i64x2::new(8218739538452480967, 9190693790629616954); - assert_eq!(r, transmute(lsx_vbitset_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitset_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -479,7 +600,13 @@ unsafe fn test_lsx_vbitset_w() { let b = u32x4::new(3259082048, 1303228302, 1429001720, 209615081); let r = i64x2::new(5472281065241838073, -4235320193476931022); - assert_eq!(r, transmute(lsx_vbitset_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitset_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -488,7 +615,13 @@ unsafe fn test_lsx_vbitset_d() { let b = u64x2::new(12687331714071910183, 1753585392879336372); let r = i64x2::new(8117422612773760492, 5031452210401715131); - assert_eq!(r, transmute(lsx_vbitset_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitset_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -498,7 +631,7 @@ unsafe fn test_lsx_vbitseti_b() { ); let r = i64x2::new(6185254145054243811, 5860546440891134157); - assert_eq!(r, transmute(lsx_vbitseti_b::<6>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitseti_b::<6>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -506,7 +639,7 @@ unsafe fn test_lsx_vbitseti_h() { let a = u16x8::new(15222, 59961, 52253, 2908, 61562, 41309, 63627, 4191); let r = i64x2::new(819316619673811830, 1179934905985921146); - assert_eq!(r, transmute(lsx_vbitseti_h::<1>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitseti_h::<1>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -514,7 +647,7 @@ unsafe fn test_lsx_vbitseti_w() { let a = u32x4::new(3788412756, 1863556832, 1913138259, 1199998627); let r = i64x2::new(8012922850722617172, 5162962059379878995); - assert_eq!(r, transmute(lsx_vbitseti_w::<21>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitseti_w::<21>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -522,7 +655,7 @@ unsafe fn test_lsx_vbitseti_d() { let a = u64x2::new(10744510173660993785, 16946223211744108759); let r = i64x2::new(-7702233900048557831, -1500520861831225129); - assert_eq!(r, transmute(lsx_vbitseti_d::<27>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitseti_d::<27>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -535,7 +668,13 @@ unsafe fn test_lsx_vbitrev_b() { ); let r = i64x2::new(7553563628828981794, -3550669970358088907); - assert_eq!(r, transmute(lsx_vbitrev_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitrev_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -544,7 +683,13 @@ unsafe fn test_lsx_vbitrev_h() { let b = u16x8::new(21347, 23131, 57157, 13786, 34463, 33445, 23964, 48087); let r = i64x2::new(-2253077037977362312, -1686202867067838120); - assert_eq!(r, transmute(lsx_vbitrev_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitrev_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -553,7 +698,13 @@ unsafe fn test_lsx_vbitrev_w() { let b = u32x4::new(3330530584, 4153020036, 822570638, 2652744506); let r = i64x2::new(4583672484591007782, 3195058299616182309); - assert_eq!(r, transmute(lsx_vbitrev_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitrev_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -562,7 +713,13 @@ unsafe fn test_lsx_vbitrev_d() { let b = u64x2::new(10942298949673565895, 12884740754463765660); let r = i64x2::new(-2430080033105247697, -384636561250515393); - assert_eq!(r, transmute(lsx_vbitrev_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitrev_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -572,7 +729,7 @@ unsafe fn test_lsx_vbitrevi_b() { ); let r = i64x2::new(8727320563398842300, 7658903196653594166); - assert_eq!(r, transmute(lsx_vbitrevi_b::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitrevi_b::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -580,7 +737,7 @@ unsafe fn test_lsx_vbitrevi_h() { let a = u16x8::new(15083, 24599, 61212, 12408, 48399, 59833, 45416, 58826); let r = i64x2::new(8104420064785562347, -6500117680329458417); - assert_eq!(r, transmute(lsx_vbitrevi_h::<14>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitrevi_h::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -588,7 +745,7 @@ unsafe fn test_lsx_vbitrevi_w() { let a = u32x4::new(1200613355, 1418062686, 3847355950, 3312937419); let r = i64x2::new(6099540060505368555, -4226793400815190482); - assert_eq!(r, transmute(lsx_vbitrevi_w::<21>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitrevi_w::<21>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -596,7 +753,7 @@ unsafe fn test_lsx_vbitrevi_d() { let a = u64x2::new(295858379748270823, 1326723086853575042); let r = i64x2::new(295858379748254439, 1326723086853591426); - assert_eq!(r, transmute(lsx_vbitrevi_d::<14>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitrevi_d::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -609,7 +766,10 @@ unsafe fn test_lsx_vadd_b() { ); let r = i64x2::new(5228548393274527852, 1107461330348121713); - assert_eq!(r, transmute(lsx_vadd_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadd_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -618,7 +778,10 @@ unsafe fn test_lsx_vadd_h() { let b = i16x8::new(-25040, 15453, -28080, -31322, -24429, -12453, -18073, 27019); let r = i64x2::new(1938006946753467667, 3264410328302682781); - assert_eq!(r, transmute(lsx_vadd_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadd_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -627,7 +790,10 @@ unsafe fn test_lsx_vadd_w() { let b = i32x4::new(-1169804484, 389773725, -731843701, -1825112934); let r = i64x2::new(-2841313158179161935, -1386205072290870384); - assert_eq!(r, transmute(lsx_vadd_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadd_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -636,7 +802,10 @@ unsafe fn test_lsx_vadd_d() { let b = i64x2::new(7093939531558864473, 4047047970310912233); let r = i64x2::new(-204689461315224217, -5456447511965942904); - assert_eq!(r, transmute(lsx_vadd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadd_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -646,7 +815,7 @@ unsafe fn test_lsx_vaddi_bu() { ); let r = i64x2::new(-7790681010872578420, 298548864442153210); - assert_eq!(r, transmute(lsx_vaddi_bu::<10>(transmute(a)))); + assert_eq!(r, transmute(lsx_vaddi_bu::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -654,7 +823,7 @@ unsafe fn test_lsx_vaddi_hu() { let a = i16x8::new(-16986, -28417, 11657, 16608, -30167, 18602, 8897, -854); let r = i64x2::new(4681541984598867390, -233585914045887935); - assert_eq!(r, transmute(lsx_vaddi_hu::<24>(transmute(a)))); + assert_eq!(r, transmute(lsx_vaddi_hu::<24>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -662,7 +831,7 @@ unsafe fn test_lsx_vaddi_wu() { let a = i32x4::new(1142343549, 56714754, -180143297, 408668191); let r = i64x2::new(243588023362963327, 1755216527965240129); - assert_eq!(r, transmute(lsx_vaddi_wu::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vaddi_wu::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -670,7 +839,7 @@ unsafe fn test_lsx_vaddi_du() { let a = i64x2::new(4516502893749962130, 9158051921593642947); let r = i64x2::new(4516502893749962139, 9158051921593642956); - assert_eq!(r, transmute(lsx_vaddi_du::<9>(transmute(a)))); + assert_eq!(r, transmute(lsx_vaddi_du::<9>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -683,7 +852,10 @@ unsafe fn test_lsx_vsub_b() { ); let r = i64x2::new(-4051929421319416371, 8737463450488952169); - assert_eq!(r, transmute(lsx_vsub_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsub_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -692,7 +864,10 @@ unsafe fn test_lsx_vsub_h() { let b = i16x8::new(15368, 16207, 9677, 21447, -29583, -22036, 1845, 15671); let r = i64x2::new(-913983189443969573, 2742472381424198215); - assert_eq!(r, transmute(lsx_vsub_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsub_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -701,7 +876,10 @@ unsafe fn test_lsx_vsub_w() { let b = i32x4::new(617176389, -1376778690, 1463940361, 620446698); let r = i64x2::new(-7247543435452521192, -8067077040042720878); - assert_eq!(r, transmute(lsx_vsub_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsub_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -710,7 +888,10 @@ unsafe fn test_lsx_vsub_d() { let b = i64x2::new(1314101702815749241, 7673634401554993450); let r = i64x2::new(5925090640479842026, 5645651807574135757); - assert_eq!(r, transmute(lsx_vsub_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsub_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -720,7 +901,7 @@ unsafe fn test_lsx_vsubi_bu() { ); let r = i64x2::new(-8192169673836457574, 4758493248402185941); - assert_eq!(r, transmute(lsx_vsubi_bu::<19>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsubi_bu::<19>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -728,7 +909,7 @@ unsafe fn test_lsx_vsubi_hu() { let a = i16x8::new(13272, -26858, -235, 16054, 29698, 1377, 4604, -3878); let r = i64x2::new(4514576075959186376, -1096043853912116238); - assert_eq!(r, transmute(lsx_vsubi_hu::<16>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsubi_hu::<16>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -736,7 +917,7 @@ unsafe fn test_lsx_vsubi_wu() { let a = i32x4::new(1277091145, -2076591216, -1523555105, -945754023); let r = i64x2::new(-8918891362898748088, -4061982600368986914); - assert_eq!(r, transmute(lsx_vsubi_wu::<1>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsubi_wu::<1>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -744,7 +925,7 @@ unsafe fn test_lsx_vsubi_du() { let a = i64x2::new(-8248876128472283209, -2119651236628000925); let r = i64x2::new(-8248876128472283234, -2119651236628000950); - assert_eq!(r, transmute(lsx_vsubi_du::<25>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsubi_du::<25>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -757,7 +938,10 @@ unsafe fn test_lsx_vmax_b() { ); let r = i64x2::new(1260734548147228113, 7591133008682590587); - assert_eq!(r, transmute(lsx_vmax_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -766,7 +950,10 @@ unsafe fn test_lsx_vmax_h() { let b = i16x8::new(25637, -11569, -23103, 6983, -17125, 5183, -709, 5986); let r = i64x2::new(1965654441534120997, 1684966995419662474); - assert_eq!(r, transmute(lsx_vmax_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -775,7 +962,10 @@ unsafe fn test_lsx_vmax_w() { let b = i32x4::new(643859790, -389733899, -1309288060, 1934346522); let r = i64x2::new(-1673894349703707314, 8307955054730158361); - assert_eq!(r, transmute(lsx_vmax_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -784,7 +974,10 @@ unsafe fn test_lsx_vmax_d() { let b = i64x2::new(-6137495199657896371, 2160025776787809810); let r = i64x2::new(-990960773872867733, 6406870358170165030); - assert_eq!(r, transmute(lsx_vmax_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -794,7 +987,7 @@ unsafe fn test_lsx_vmaxi_b() { ); let r = i64x2::new(5908253215318699518, 1728939149412407162); - assert_eq!(r, transmute(lsx_vmaxi_b::<-2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_b::<-2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -802,7 +995,7 @@ unsafe fn test_lsx_vmaxi_h() { let a = i16x8::new(-14059, 19536, 15816, 28251, 23079, -10486, -11781, 25565); let r = i64x2::new(7952017497535807498, 7195907822558272039); - assert_eq!(r, transmute(lsx_vmaxi_h::<10>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_h::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -810,7 +1003,7 @@ unsafe fn test_lsx_vmaxi_w() { let a = i32x4::new(-1136628686, -168033999, -2082324641, -1789957469); let r = i64x2::new(55834574861, 55834574861); - assert_eq!(r, transmute(lsx_vmaxi_w::<13>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_w::<13>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -818,7 +1011,7 @@ unsafe fn test_lsx_vmaxi_d() { let a = i64x2::new(-490958606840895025, -602287987736508723); let r = i64x2::new(-5, -5); - assert_eq!(r, transmute(lsx_vmaxi_d::<-5>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_d::<-5>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -831,7 +1024,13 @@ unsafe fn test_lsx_vmax_bu() { ); let r = i64x2::new(-5712542810735052010, 4588590651995571688); - assert_eq!(r, transmute(lsx_vmax_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -840,7 +1039,13 @@ unsafe fn test_lsx_vmax_hu() { let b = u16x8::new(61508, 27224, 11696, 15294, 30725, 4809, 55995, 24012); let r = i64x2::new(6366821095949791300, 6759017637785204741); - assert_eq!(r, transmute(lsx_vmax_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -849,7 +1054,13 @@ unsafe fn test_lsx_vmax_wu() { let b = u32x4::new(2856502284, 546582019, 3814541188, 2370198139); let r = i64x2::new(2347551899043152908, -8266820577849948284); - assert_eq!(r, transmute(lsx_vmax_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -858,7 +1069,13 @@ unsafe fn test_lsx_vmax_du() { let b = u64x2::new(15559502733477870114, 3537017767853389449); let r = i64x2::new(-1341110034690820781, -6520089917898609068); - assert_eq!(r, transmute(lsx_vmax_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -868,7 +1085,7 @@ unsafe fn test_lsx_vmaxi_bu() { ); let r = i64x2::new(-1045930669804428840, -8076220938123067729); - assert_eq!(r, transmute(lsx_vmaxi_bu::<27>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_bu::<27>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -876,7 +1093,7 @@ unsafe fn test_lsx_vmaxi_hu() { let a = u16x8::new(56394, 18974, 59, 64239, 15178, 38205, 20044, 21066); let r = i64x2::new(-365072790147113910, 5929637950214978378); - assert_eq!(r, transmute(lsx_vmaxi_hu::<23>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_hu::<23>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -884,7 +1101,7 @@ unsafe fn test_lsx_vmaxi_wu() { let a = u32x4::new(2234002286, 3837532269, 3218694441, 2956128392); let r = i64x2::new(-1964668478775874706, -5750269304073789143); - assert_eq!(r, transmute(lsx_vmaxi_wu::<15>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_wu::<15>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -892,7 +1109,7 @@ unsafe fn test_lsx_vmaxi_du() { let a = u64x2::new(3145066433415682744, 697260191203805367); let r = i64x2::new(3145066433415682744, 697260191203805367); - assert_eq!(r, transmute(lsx_vmaxi_du::<15>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_du::<15>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -905,7 +1122,10 @@ unsafe fn test_lsx_vmin_b() { ); let r = i64x2::new(1870285769536668398, -8941449826914199819); - assert_eq!(r, transmute(lsx_vmin_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -914,7 +1134,10 @@ unsafe fn test_lsx_vmin_h() { let b = i16x8::new(-5519, 15267, -28304, -5842, 32145, 6582, -9646, -24918); let r = i64x2::new(-1644216902720689551, -7013553423522578637); - assert_eq!(r, transmute(lsx_vmin_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -923,7 +1146,10 @@ unsafe fn test_lsx_vmin_w() { let b = i32x4::new(-425011290, -2104111279, 175390640, 571448257); let r = i64x2::new(-9037089126579775578, 2454351575346593712); - assert_eq!(r, transmute(lsx_vmin_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -932,7 +1158,10 @@ unsafe fn test_lsx_vmin_d() { let b = i64x2::new(7269804448576860985, -2384075780126369706); let r = i64x2::new(5262417572890363865, -2384075780126369706); - assert_eq!(r, transmute(lsx_vmin_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -942,7 +1171,7 @@ unsafe fn test_lsx_vmini_b() { ); let r = i64x2::new(-1187557278141451540, -940475489144045070); - assert_eq!(r, transmute(lsx_vmini_b::<-14>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_b::<-14>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -950,7 +1179,7 @@ unsafe fn test_lsx_vmini_h() { let a = i16x8::new(26119, -26421, -26720, 11534, 11181, -13024, -9525, -1565); let r = i64x2::new(-677708916064259, -440267769697468419); - assert_eq!(r, transmute(lsx_vmini_h::<-3>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_h::<-3>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -958,7 +1187,7 @@ unsafe fn test_lsx_vmini_w() { let a = i32x4::new(1937226480, -56354461, -210581139, 118641668); let r = i64x2::new(-242040566978707451, 25559222637); - assert_eq!(r, transmute(lsx_vmini_w::<5>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_w::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -966,7 +1195,7 @@ unsafe fn test_lsx_vmini_d() { let a = i64x2::new(-6839357499730806877, 2982085289136510651); let r = i64x2::new(-6839357499730806877, 11); - assert_eq!(r, transmute(lsx_vmini_d::<11>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_d::<11>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -979,7 +1208,13 @@ unsafe fn test_lsx_vmin_bu() { ); let r = i64x2::new(3617816997909406996, 4784078933357220137); - assert_eq!(r, transmute(lsx_vmin_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -988,7 +1223,13 @@ unsafe fn test_lsx_vmin_hu() { let b = u16x8::new(30424, 14541, 7654, 46014, 42452, 14971, 14903, 13871); let r = i64x2::new(-5494921620712753448, 3904403410832303572); - assert_eq!(r, transmute(lsx_vmin_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -997,7 +1238,13 @@ unsafe fn test_lsx_vmin_wu() { let b = u32x4::new(1456829356, 2264966310, 1587887390, 645429404); let r = i64x2::new(-8718787844260924500, 2772098183187911585); - assert_eq!(r, transmute(lsx_vmin_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1006,7 +1253,13 @@ unsafe fn test_lsx_vmin_du() { let b = u64x2::new(15079551366517035256, 13891052596545854864); let r = i64x2::new(6641707046382446478, 5750385968612732680); - assert_eq!(r, transmute(lsx_vmin_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1016,7 +1269,7 @@ unsafe fn test_lsx_vmini_bu() { ); let r = i64x2::new(361700864190383365, 361700864190317829); - assert_eq!(r, transmute(lsx_vmini_bu::<5>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_bu::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1024,7 +1277,7 @@ unsafe fn test_lsx_vmini_hu() { let a = u16x8::new(51791, 41830, 16737, 31634, 36341, 58491, 48701, 8690); let r = i64x2::new(5066626891382802, 5066626891382802); - assert_eq!(r, transmute(lsx_vmini_hu::<18>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_hu::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1032,7 +1285,7 @@ unsafe fn test_lsx_vmini_wu() { let a = u32x4::new(1158888991, 2639721369, 556001789, 2902942998); let r = i64x2::new(77309411346, 77309411346); - assert_eq!(r, transmute(lsx_vmini_wu::<18>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_wu::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1040,7 +1293,7 @@ unsafe fn test_lsx_vmini_du() { let a = u64x2::new(17903595768445663391, 13119300660970895532); let r = i64x2::new(13, 13); - assert_eq!(r, transmute(lsx_vmini_du::<13>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_du::<13>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1053,7 +1306,10 @@ unsafe fn test_lsx_vseq_b() { ); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseq_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vseq_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1062,7 +1318,10 @@ unsafe fn test_lsx_vseq_h() { let b = i16x8::new(-7387, -24074, 15709, -4629, 30465, -9504, -21403, -30287); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseq_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vseq_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1071,7 +1330,10 @@ unsafe fn test_lsx_vseq_w() { let b = i32x4::new(-493722413, -522973881, -1254416384, -884207273); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseq_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vseq_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1080,7 +1342,10 @@ unsafe fn test_lsx_vseq_d() { let b = i64x2::new(3023654898382436999, 1783520577741396523); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vseq_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1090,7 +1355,7 @@ unsafe fn test_lsx_vseqi_b() { ); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseqi_b::<12>(transmute(a)))); + assert_eq!(r, transmute(lsx_vseqi_b::<12>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1098,7 +1363,7 @@ unsafe fn test_lsx_vseqi_h() { let a = i16x8::new(-3205, 25452, 20774, 22065, -8424, 16590, -15971, -14154); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseqi_h::<-1>(transmute(a)))); + assert_eq!(r, transmute(lsx_vseqi_h::<-1>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1106,7 +1371,7 @@ unsafe fn test_lsx_vseqi_w() { let a = i32x4::new(199798215, -798304779, -1812193878, -1830438161); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseqi_w::<11>(transmute(a)))); + assert_eq!(r, transmute(lsx_vseqi_w::<11>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1114,7 +1379,7 @@ unsafe fn test_lsx_vseqi_d() { let a = i64x2::new(-7376858177879278972, 1947027764115386661); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseqi_d::<3>(transmute(a)))); + assert_eq!(r, transmute(lsx_vseqi_d::<3>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1124,7 +1389,7 @@ unsafe fn test_lsx_vslti_b() { ); let r = i64x2::new(-1099511627776, 1095216660480); - assert_eq!(r, transmute(lsx_vslti_b::<-4>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_b::<-4>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1137,7 +1402,10 @@ unsafe fn test_lsx_vslt_b() { ); let r = i64x2::new(-72056494526365441, -280375465148416); - assert_eq!(r, transmute(lsx_vslt_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1146,7 +1414,10 @@ unsafe fn test_lsx_vslt_h() { let b = i16x8::new(-10624, 12762, 31216, 13253, 2299, -12591, -8652, -22348); let r = i64x2::new(-4294967296, 65535); - assert_eq!(r, transmute(lsx_vslt_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1155,7 +1426,10 @@ unsafe fn test_lsx_vslt_w() { let b = i32x4::new(-1849021639, -756143028, 54274044, 646446450); let r = i64x2::new(-4294967296, -1); - assert_eq!(r, transmute(lsx_vslt_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1164,7 +1438,10 @@ unsafe fn test_lsx_vslt_d() { let b = i64x2::new(1481173131774551907, 270656941607020532); let r = i64x2::new(-1, 0); - assert_eq!(r, transmute(lsx_vslt_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1172,7 +1449,7 @@ unsafe fn test_lsx_vslti_h() { let a = i16x8::new(-8902, 5527, 17224, -27356, 4424, 28839, 29975, 18805); let r = i64x2::new(-281474976645121, 0); - assert_eq!(r, transmute(lsx_vslti_h::<14>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_h::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1180,7 +1457,7 @@ unsafe fn test_lsx_vslti_w() { let a = i32x4::new(995282502, -1964668207, -996118772, 1812234755); let r = i64x2::new(-4294967296, 4294967295); - assert_eq!(r, transmute(lsx_vslti_w::<14>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_w::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1188,7 +1465,7 @@ unsafe fn test_lsx_vslti_d() { let a = i64x2::new(1441753618400573134, 3878439049744730841); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslti_d::<14>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_d::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1201,7 +1478,13 @@ unsafe fn test_lsx_vslt_bu() { ); let r = i64x2::new(-281474959998721, -72057589742960896); - assert_eq!(r, transmute(lsx_vslt_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1210,7 +1493,13 @@ unsafe fn test_lsx_vslt_hu() { let b = u16x8::new(513, 13075, 20319, 44422, 12609, 18638, 20227, 21354); let r = i64x2::new(281474976645120, -281474976645121); - assert_eq!(r, transmute(lsx_vslt_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1219,7 +1508,13 @@ unsafe fn test_lsx_vslt_wu() { let b = u32x4::new(1402243125, 1129899238, 2591537060, 4152171743); let r = i64x2::new(4294967295, -1); - assert_eq!(r, transmute(lsx_vslt_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1228,7 +1523,13 @@ unsafe fn test_lsx_vslt_du() { let b = u64x2::new(835355141719377733, 10472626544222695938); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslt_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1238,7 +1539,7 @@ unsafe fn test_lsx_vslti_bu() { ); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslti_bu::<7>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_bu::<7>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1246,7 +1547,7 @@ unsafe fn test_lsx_vslti_hu() { let a = u16x8::new(60550, 12178, 30950, 44771, 25514, 35987, 55940, 21614); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslti_hu::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_hu::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1254,7 +1555,7 @@ unsafe fn test_lsx_vslti_wu() { let a = u32x4::new(912580668, 18660032, 3405726641, 4033549497); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslti_wu::<8>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_wu::<8>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1262,7 +1563,7 @@ unsafe fn test_lsx_vslti_du() { let a = u64x2::new(17196150830761730262, 5893061291971214149); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslti_du::<14>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_du::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1275,7 +1576,10 @@ unsafe fn test_lsx_vsle_b() { ); let r = i64x2::new(281470681808895, 280375465148415); - assert_eq!(r, transmute(lsx_vsle_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1284,7 +1588,10 @@ unsafe fn test_lsx_vsle_h() { let b = i16x8::new(-30602, -9535, 10944, 3343, -1093, 6600, -19453, -4561); let r = i64x2::new(281470681743360, -281470681808896); - assert_eq!(r, transmute(lsx_vsle_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1293,7 +1600,10 @@ unsafe fn test_lsx_vsle_w() { let b = i32x4::new(-1810853975, 2021418524, 215198844, 1124361386); let r = i64x2::new(-4294967296, -4294967296); - assert_eq!(r, transmute(lsx_vsle_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1302,7 +1612,10 @@ unsafe fn test_lsx_vsle_d() { let b = i64x2::new(71694374951002423, -4307912969104303925); let r = i64x2::new(-1, 0); - assert_eq!(r, transmute(lsx_vsle_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1312,7 +1625,7 @@ unsafe fn test_lsx_vslei_b() { ); let r = i64x2::new(72056494526365440, 280375465082880); - assert_eq!(r, transmute(lsx_vslei_b::<3>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_b::<3>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1320,7 +1633,7 @@ unsafe fn test_lsx_vslei_h() { let a = i16x8::new(31276, -16628, -30006, -20587, 2104, -30062, 18261, -6449); let r = i64x2::new(-65536, -281470681808896); - assert_eq!(r, transmute(lsx_vslei_h::<-3>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_h::<-3>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1328,7 +1641,7 @@ unsafe fn test_lsx_vslei_w() { let a = i32x4::new(-1890390435, 1289536678, 1490122113, 2120063492); let r = i64x2::new(4294967295, 0); - assert_eq!(r, transmute(lsx_vslei_w::<-16>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_w::<-16>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1336,7 +1649,7 @@ unsafe fn test_lsx_vslei_d() { let a = i64x2::new(-123539898448811963, 8007480165241051883); let r = i64x2::new(-1, 0); - assert_eq!(r, transmute(lsx_vslei_d::<8>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_d::<8>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1349,7 +1662,13 @@ unsafe fn test_lsx_vsle_bu() { ); let r = i64x2::new(1095216660480, 72057594021150720); - assert_eq!(r, transmute(lsx_vsle_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1358,7 +1677,13 @@ unsafe fn test_lsx_vsle_hu() { let b = u16x8::new(50529, 35111, 24746, 62465, 21587, 30574, 11054, 11653); let r = i64x2::new(-4294967296, 281474976710655); - assert_eq!(r, transmute(lsx_vsle_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1367,7 +1692,13 @@ unsafe fn test_lsx_vsle_wu() { let b = u32x4::new(1321018603, 1091195011, 3525236625, 4061062671); let r = i64x2::new(0, -1); - assert_eq!(r, transmute(lsx_vsle_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1376,7 +1707,13 @@ unsafe fn test_lsx_vsle_du() { let b = u64x2::new(16044633718831874991, 3531311371811276914); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vsle_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1386,7 +1723,7 @@ unsafe fn test_lsx_vslei_bu() { ); let r = i64x2::new(71776119061217280, 280375465082880); - assert_eq!(r, transmute(lsx_vslei_bu::<18>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_bu::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1394,7 +1731,7 @@ unsafe fn test_lsx_vslei_hu() { let a = u16x8::new(1430, 10053, 35528, 28458, 2394, 22098, 40236, 20853); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslei_hu::<10>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_hu::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1402,7 +1739,7 @@ unsafe fn test_lsx_vslei_wu() { let a = u32x4::new(3289026584, 3653636092, 2919866047, 2895662832); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslei_wu::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_wu::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1410,7 +1747,7 @@ unsafe fn test_lsx_vslei_du() { let a = u64x2::new(17462377852989253439, 17741928456729041079); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslei_du::<12>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_du::<12>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1420,7 +1757,7 @@ unsafe fn test_lsx_vsat_b() { ); let r = i64x2::new(-2964542792447819074, 3186937137643144200); - assert_eq!(r, transmute(lsx_vsat_b::<7>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_b::<7>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1428,7 +1765,7 @@ unsafe fn test_lsx_vsat_h() { let a = i16x8::new(-22234, -8008, -23350, 13768, 26313, -27447, -3569, 6025); let r = i64x2::new(576451960371214336, 576451960371152895); - assert_eq!(r, transmute(lsx_vsat_h::<11>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_h::<11>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1436,7 +1773,7 @@ unsafe fn test_lsx_vsat_w() { let a = i32x4::new(-84179653, 874415975, 1823119516, 1667850968); let r = i64x2::new(137438953440, 133143986207); - assert_eq!(r, transmute(lsx_vsat_w::<5>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_w::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1444,7 +1781,7 @@ unsafe fn test_lsx_vsat_d() { let a = i64x2::new(6859869867233872152, 2514172105675226457); let r = i64x2::new(262143, 262143); - assert_eq!(r, transmute(lsx_vsat_d::<18>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_d::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1454,7 +1791,7 @@ unsafe fn test_lsx_vsat_bu() { ); let r = i64x2::new(2125538672170008439, 6577605268441825038); - assert_eq!(r, transmute(lsx_vsat_bu::<6>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_bu::<6>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1462,7 +1799,7 @@ unsafe fn test_lsx_vsat_hu() { let a = u16x8::new(36681, 34219, 6160, 8687, 4544, 20195, 35034, 916); let r = i64x2::new(287953294993589247, 257835472485549055); - assert_eq!(r, transmute(lsx_vsat_hu::<9>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_hu::<9>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1470,7 +1807,7 @@ unsafe fn test_lsx_vsat_wu() { let a = u32x4::new(1758000759, 4138051566, 2705324001, 3927640324); let r = i64x2::new(70364449226751, 70364449226751); - assert_eq!(r, transmute(lsx_vsat_wu::<13>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_wu::<13>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1478,7 +1815,7 @@ unsafe fn test_lsx_vsat_du() { let a = u64x2::new(1953136817312581670, 2606878300382729363); let r = i64x2::new(9007199254740991, 9007199254740991); - assert_eq!(r, transmute(lsx_vsat_du::<52>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_du::<52>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1491,7 +1828,13 @@ unsafe fn test_lsx_vadda_b() { ); let r = i64x2::new(8248499858970022011, 8535863472581999270); - assert_eq!(r, transmute(lsx_vadda_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadda_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1500,7 +1843,13 @@ unsafe fn test_lsx_vadda_h() { let b = i16x8::new(-21543, 21720, 14529, -19143, -28953, 13450, 8037, 29413); let r = i64x2::new(-8646732423142600033, 8924050915627474398); - assert_eq!(r, transmute(lsx_vadda_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadda_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1509,7 +1858,13 @@ unsafe fn test_lsx_vadda_w() { let b = i32x4::new(287041349, 249467792, 312776520, 1314435078); let r = i64x2::new(8345875378983299469, 6092442344252138029); - assert_eq!(r, transmute(lsx_vadda_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadda_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1518,7 +1873,13 @@ unsafe fn test_lsx_vadda_d() { let b = i64x2::new(-4324432602362661920, 6402427893748093984); let r = i64x2::new(6071741662385212188, -5328622052402301597); - assert_eq!(r, transmute(lsx_vadda_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadda_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1531,7 +1892,13 @@ unsafe fn test_lsx_vsadd_b() { ); let r = i64x2::new(-3422653801050278697, 1909270979770548186); - assert_eq!(r, transmute(lsx_vsadd_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1540,7 +1907,13 @@ unsafe fn test_lsx_vsadd_h() { let b = i16x8::new(26970, 17131, 15547, -7614, -8479, 22338, 3567, -22299); let r = i64x2::new(6720170624686097630, -304244782337649222); - assert_eq!(r, transmute(lsx_vsadd_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1549,7 +1922,13 @@ unsafe fn test_lsx_vsadd_w() { let b = i32x4::new(-1026388582, 222487110, 501504960, -1863994162); let r = i64x2::new(-6565289918505943040, -6915373914453178024); - assert_eq!(r, transmute(lsx_vsadd_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1558,7 +1937,13 @@ unsafe fn test_lsx_vsadd_d() { let b = i64x2::new(-6599608819082608284, -5088169537193133686); let r = i64x2::new(-8567396806692999839, -9223372036854775808); - assert_eq!(r, transmute(lsx_vsadd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1571,7 +1956,13 @@ unsafe fn test_lsx_vsadd_bu() { ); let r = i64x2::new(-5404438145481572386, -7318352348905473); - assert_eq!(r, transmute(lsx_vsadd_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1580,7 +1971,13 @@ unsafe fn test_lsx_vsadd_hu() { let b = u16x8::new(31219, 59227, 25607, 62798, 18845, 3238, 19902, 24978); let r = i64x2::new(-8740258447361, -136834913009665); - assert_eq!(r, transmute(lsx_vsadd_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1589,7 +1986,13 @@ unsafe fn test_lsx_vsadd_wu() { let b = u32x4::new(3676524021, 3894343575, 904432536, 1616820031); let r = i64x2::new(-1, -7583652642497232897); - assert_eq!(r, transmute(lsx_vsadd_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1598,7 +2001,13 @@ unsafe fn test_lsx_vsadd_du() { let b = u64x2::new(11054638512585704882, 3549000132135395099); let r = i64x2::new(-3651327027786652925, -623479558932885349); - assert_eq!(r, transmute(lsx_vsadd_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1611,7 +2020,10 @@ unsafe fn test_lsx_vavg_b() { ); let r = i64x2::new(-152206416164856247, 4369276355735447089); - assert_eq!(r, transmute(lsx_vavg_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1620,7 +2032,10 @@ unsafe fn test_lsx_vavg_h() { let b = i16x8::new(-3088, -25854, -32552, -8417, 7808, -12495, 22032, -5168); let r = i64x2::new(696836182083297626, -4337760619710117321); - assert_eq!(r, transmute(lsx_vavg_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1629,7 +2044,10 @@ unsafe fn test_lsx_vavg_w() { let b = i32x4::new(-324844828, -1580060766, -1909832882, 328273785); let r = i64x2::new(475428188150908257, 4521676108535152711); - assert_eq!(r, transmute(lsx_vavg_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1638,7 +2056,10 @@ unsafe fn test_lsx_vavg_d() { let b = i64x2::new(3169904420607189220, 5159962511251707672); let r = i64x2::new(2328313764472338215, 5669256157716045974); - assert_eq!(r, transmute(lsx_vavg_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1651,7 +2072,13 @@ unsafe fn test_lsx_vavg_bu() { ); let r = i64x2::new(-5663745084945885565, 2801126043194071837); - assert_eq!(r, transmute(lsx_vavg_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1660,7 +2087,13 @@ unsafe fn test_lsx_vavg_hu() { let b = u16x8::new(44835, 36733, 12115, 42874, 4819, 12201, 27397, 25394); let r = i64x2::new(-4196978047981735086, -6439149718662907396); - assert_eq!(r, transmute(lsx_vavg_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1669,7 +2102,13 @@ unsafe fn test_lsx_vavg_wu() { let b = u32x4::new(160886383, 26081142, 459122380, 2523086630); let r = i64x2::new(123816739188229069, -5586965600173345916); - assert_eq!(r, transmute(lsx_vavg_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1678,7 +2117,13 @@ unsafe fn test_lsx_vavg_du() { let b = u64x2::new(9749063966076740681, 5963120178993456389); let r = i64x2::new(-7770235857859936532, 7939635441364553211); - assert_eq!(r, transmute(lsx_vavg_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1691,7 +2136,13 @@ unsafe fn test_lsx_vavgr_b() { ); let r = i64x2::new(1883712581662731545, -1226681417271426582); - assert_eq!(r, transmute(lsx_vavgr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1700,7 +2151,13 @@ unsafe fn test_lsx_vavgr_h() { let b = i16x8::new(-9758, -8332, 20577, 31066, 31120, 14788, -22323, 16722); let r = i64x2::new(3801916629507170613, 3994084079587580569); - assert_eq!(r, transmute(lsx_vavgr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1709,7 +2166,13 @@ unsafe fn test_lsx_vavgr_w() { let b = i32x4::new(1278058715, -155858446, -195547847, -750518746); let r = i64x2::new(4040594005688324125, -5795079921582298726); - assert_eq!(r, transmute(lsx_vavgr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1718,7 +2181,13 @@ unsafe fn test_lsx_vavgr_d() { let b = i64x2::new(8758126674980055299, -7441643514470614533); let r = i64x2::new(3399991646978312393, -1904131665097658207); - assert_eq!(r, transmute(lsx_vavgr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1731,7 +2200,13 @@ unsafe fn test_lsx_vavgr_bu() { ); let r = i64x2::new(9122444831751176042, 6010164553039771699); - assert_eq!(r, transmute(lsx_vavgr_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1740,7 +2215,13 @@ unsafe fn test_lsx_vavgr_hu() { let b = u16x8::new(26111, 34713, 61420, 23702, 29204, 9543, 62786, 7043); let r = i64x2::new(7022187818705851223, 4754859411904311722); - assert_eq!(r, transmute(lsx_vavgr_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1749,7 +2230,13 @@ unsafe fn test_lsx_vavgr_wu() { let b = u32x4::new(1930150361, 3668628165, 2983921396, 2410913126); let r = i64x2::new(-5401180487351753235, 8140240017388800980); - assert_eq!(r, transmute(lsx_vavgr_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1758,7 +2245,13 @@ unsafe fn test_lsx_vavgr_du() { let b = u64x2::new(8650759135311802962, 11380630663742852932); let r = i64x2::new(6046550632940509412, 8095423581736830430); - assert_eq!(r, transmute(lsx_vavgr_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1771,7 +2264,13 @@ unsafe fn test_lsx_vssub_b() { ); let r = i64x2::new(628822736562549631, -9187601072510296593); - assert_eq!(r, transmute(lsx_vssub_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1780,7 +2279,13 @@ unsafe fn test_lsx_vssub_h() { let b = i16x8::new(-26027, 6118, -13204, 25080, 12458, 8441, 24701, 11617); let r = i64x2::new(-9223231300041015297, 1942699741282756937); - assert_eq!(r, transmute(lsx_vssub_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1789,7 +2294,13 @@ unsafe fn test_lsx_vssub_w() { let b = i32x4::new(-1808829767, 2144666490, 146236682, 1180114488); let r = i64x2::new(-9223372035405031217, -177933965588659662); - assert_eq!(r, transmute(lsx_vssub_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1798,7 +2309,13 @@ unsafe fn test_lsx_vssub_d() { let b = i64x2::new(-2293337525465880409, 5736255249834646932); let r = i64x2::new(2921430482628531027, -4208815595153969049); - assert_eq!(r, transmute(lsx_vssub_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1811,7 +2328,13 @@ unsafe fn test_lsx_vssub_bu() { ); let r = i64x2::new(1441151919413273782, 87960930222283); - assert_eq!(r, transmute(lsx_vssub_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1820,7 +2343,13 @@ unsafe fn test_lsx_vssub_hu() { let b = u16x8::new(50468, 33060, 15257, 59071, 59343, 21993, 42978, 20097); let r = i64x2::new(902801202201243247, -7922957643493867520); - assert_eq!(r, transmute(lsx_vssub_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1829,7 +2358,13 @@ unsafe fn test_lsx_vssub_wu() { let b = u32x4::new(31483972, 3489479082, 152079374, 1875131600); let r = i64x2::new(66202020638834260, 1378022115978010238); - assert_eq!(r, transmute(lsx_vssub_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1838,7 +2373,13 @@ unsafe fn test_lsx_vssub_du() { let b = u64x2::new(6460869225596371206, 16765308520486969885); let r = i64x2::new(8426906920692365065, 0); - assert_eq!(r, transmute(lsx_vssub_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1851,7 +2392,13 @@ unsafe fn test_lsx_vabsd_b() { ); let r = i64x2::new(4230359294854509733, 2116586434120326452); - assert_eq!(r, transmute(lsx_vabsd_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1860,7 +2407,13 @@ unsafe fn test_lsx_vabsd_h() { let b = i16x8::new(9346, 27961, 21592, 10762, -6831, 17219, 14968, -1750); let r = i64x2::new(4018377481144584593, 2994052849949411737); - assert_eq!(r, transmute(lsx_vabsd_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1869,7 +2422,13 @@ unsafe fn test_lsx_vabsd_w() { let b = i32x4::new(-638463360, -1154268425, 818053243, -1766966029); let r = i64x2::new(4346218292750542585, 1613133471209364690); - assert_eq!(r, transmute(lsx_vabsd_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1878,7 +2437,13 @@ unsafe fn test_lsx_vabsd_d() { let b = i64x2::new(-8533946706796471089, 1165272962517390961); let r = i64x2::new(7188249046367538699, 8146605509049538382); - assert_eq!(r, transmute(lsx_vabsd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1891,7 +2456,13 @@ unsafe fn test_lsx_vabsd_bu() { ); let r = i64x2::new(2316568964225934796, 5350198762417854927); - assert_eq!(r, transmute(lsx_vabsd_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1900,7 +2471,13 @@ unsafe fn test_lsx_vabsd_hu() { let b = u16x8::new(42102, 40052, 6807, 16289, 29686, 38061, 42843, 26642); let r = i64x2::new(-6889746235852116468, 1175584127230950722); - assert_eq!(r, transmute(lsx_vabsd_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1909,7 +2486,13 @@ unsafe fn test_lsx_vabsd_wu() { let b = u32x4::new(3008439409, 976530727, 1726048801, 4235308512); let r = i64x2::new(-5056055741505581388, 103751774096297765); - assert_eq!(r, transmute(lsx_vabsd_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1918,7 +2501,13 @@ unsafe fn test_lsx_vabsd_du() { let b = u64x2::new(305704565845198935, 18327726360649467511); let r = i64x2::new(-4540227154002526968, -1590034053554043722); - assert_eq!(r, transmute(lsx_vabsd_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1931,7 +2520,10 @@ unsafe fn test_lsx_vmul_b() { ); let r = i64x2::new(-836412611799730432, -7959044669412588992); - assert_eq!(r, transmute(lsx_vmul_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmul_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1940,7 +2532,10 @@ unsafe fn test_lsx_vmul_h() { let b = i16x8::new(-18582, -25667, 17674, 8424, -17121, -21798, 28934, -353); let r = i64x2::new(-7419436171490628650, 3947512047518358605); - assert_eq!(r, transmute(lsx_vmul_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmul_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1949,7 +2544,10 @@ unsafe fn test_lsx_vmul_w() { let b = i32x4::new(1754730718, 782084571, 894216679, -1895747372); let r = i64x2::new(6602438528086061106, 4680306660704041039); - assert_eq!(r, transmute(lsx_vmul_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmul_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1958,7 +2556,10 @@ unsafe fn test_lsx_vmul_d() { let b = i64x2::new(8096709215426138432, -5454415917204378153); let r = i64x2::new(-1062747544199352000, -649255846668983579); - assert_eq!(r, transmute(lsx_vmul_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmul_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1976,7 +2577,11 @@ unsafe fn test_lsx_vmadd_b() { assert_eq!( r, - transmute(lsx_vmadd_b(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmadd_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -1989,7 +2594,11 @@ unsafe fn test_lsx_vmadd_h() { assert_eq!( r, - transmute(lsx_vmadd_h(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmadd_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2002,7 +2611,11 @@ unsafe fn test_lsx_vmadd_w() { assert_eq!( r, - transmute(lsx_vmadd_w(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmadd_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2015,7 +2628,11 @@ unsafe fn test_lsx_vmadd_d() { assert_eq!( r, - transmute(lsx_vmadd_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmadd_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2034,7 +2651,11 @@ unsafe fn test_lsx_vmsub_b() { assert_eq!( r, - transmute(lsx_vmsub_b(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmsub_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2047,7 +2668,11 @@ unsafe fn test_lsx_vmsub_h() { assert_eq!( r, - transmute(lsx_vmsub_h(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmsub_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2060,7 +2685,11 @@ unsafe fn test_lsx_vmsub_w() { assert_eq!( r, - transmute(lsx_vmsub_w(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmsub_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2073,7 +2702,11 @@ unsafe fn test_lsx_vmsub_d() { assert_eq!( r, - transmute(lsx_vmsub_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmsub_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2087,7 +2720,10 @@ unsafe fn test_lsx_vdiv_b() { ); let r = i64x2::new(720575944674246657, 281475060530176); - assert_eq!(r, transmute(lsx_vdiv_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2096,7 +2732,10 @@ unsafe fn test_lsx_vdiv_h() { let b = i16x8::new(-11221, 24673, 19931, 3799, -3251, -21373, -13758, -31286); let r = i64x2::new(-1125904201744385, 281470681743353); - assert_eq!(r, transmute(lsx_vdiv_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2105,7 +2744,10 @@ unsafe fn test_lsx_vdiv_w() { let b = i32x4::new(-775731190, 1887886939, 1001718213, 1135075421); let r = i64x2::new(4294967295, 4294967297); - assert_eq!(r, transmute(lsx_vdiv_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2114,7 +2756,10 @@ unsafe fn test_lsx_vdiv_d() { let b = i64x2::new(-9175012156877545557, -6390704898809702209); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vdiv_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2127,7 +2772,13 @@ unsafe fn test_lsx_vdiv_bu() { ); let r = i64x2::new(261, 72058702139687425); - assert_eq!(r, transmute(lsx_vdiv_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2136,7 +2787,13 @@ unsafe fn test_lsx_vdiv_hu() { let b = u16x8::new(25282, 44917, 13706, 63351, 58837, 46710, 29092, 57823); let r = i64x2::new(4294967297, 0); - assert_eq!(r, transmute(lsx_vdiv_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2145,7 +2802,13 @@ unsafe fn test_lsx_vdiv_wu() { let b = u32x4::new(1130189258, 1211056894, 2357258312, 3855913706); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vdiv_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2154,7 +2817,13 @@ unsafe fn test_lsx_vdiv_du() { let b = u64x2::new(14945948123666054968, 10864054932328247404); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vdiv_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2167,7 +2836,13 @@ unsafe fn test_lsx_vhaddw_h_b() { ); let r = i64x2::new(13791943145684950, -562821104926904); - assert_eq!(r, transmute(lsx_vhaddw_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2178,7 +2853,13 @@ unsafe fn test_lsx_vhaddw_w_h() { ); let r = i64x2::new(56307021213062, 183021441324639); - assert_eq!(r, transmute(lsx_vhaddw_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2187,7 +2868,13 @@ unsafe fn test_lsx_vhaddw_d_w() { let b = i32x4::new(-1119468785, -1334232049, -1752131604, -2016112631); let r = i64x2::new(-2502031305, -1217615295); - assert_eq!(r, transmute(lsx_vhaddw_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2200,7 +2887,13 @@ unsafe fn test_lsx_vhaddw_hu_bu() { ); let r = i64x2::new(45601115212087520, 21110838012870921); - assert_eq!(r, transmute(lsx_vhaddw_hu_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_hu_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2209,7 +2902,13 @@ unsafe fn test_lsx_vhaddw_wu_hu() { let b = u16x8::new(40369, 53005, 64424, 35720, 9231, 19965, 20662, 8208); let r = i64x2::new(411432097222434, 312888367535410); - assert_eq!(r, transmute(lsx_vhaddw_wu_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_wu_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2218,7 +2917,13 @@ unsafe fn test_lsx_vhaddw_du_wu() { let b = u32x4::new(728838120, 1267673009, 2659634151, 2264611356); let r = i64x2::new(4172122985, 4839922613); - assert_eq!(r, transmute(lsx_vhaddw_du_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_du_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2231,7 +2936,13 @@ unsafe fn test_lsx_vhsubw_h_b() { ); let r = i64x2::new(-4503363402989617, -31243430355664844); - assert_eq!(r, transmute(lsx_vhsubw_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2240,7 +2951,13 @@ unsafe fn test_lsx_vhsubw_w_h() { let b = i16x8::new(-14204, -13312, 8240, -4455, -6362, -4711, -30790, -15773); let r = i64x2::new(70059506530916, 60275571046613); - assert_eq!(r, transmute(lsx_vhsubw_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2249,7 +2966,13 @@ unsafe fn test_lsx_vhsubw_d_w() { let b = i32x4::new(-1671723008, 870456702, 264823818, 13322401); let r = i64x2::new(-201438605, 449141316); - assert_eq!(r, transmute(lsx_vhsubw_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2262,7 +2985,13 @@ unsafe fn test_lsx_vhsubw_hu_bu() { ); let r = i64x2::new(-62206416523952172, 42783380429340790); - assert_eq!(r, transmute(lsx_vhsubw_hu_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_hu_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2271,7 +3000,13 @@ unsafe fn test_lsx_vhsubw_wu_hu() { let b = u16x8::new(5212, 32159, 36502, 59290, 7604, 229, 35511, 47443); let r = i64x2::new(24696062008394, -147484881944276); - assert_eq!(r, transmute(lsx_vhsubw_wu_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_wu_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2280,7 +3015,13 @@ unsafe fn test_lsx_vhsubw_du_wu() { let b = u32x4::new(1383087137, 2403951939, 360532131, 3513614550); let r = i64x2::new(-601935499, 31776736); - assert_eq!(r, transmute(lsx_vhsubw_du_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_du_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2293,7 +3034,10 @@ unsafe fn test_lsx_vmod_b() { ); let r = i64x2::new(2804691417388804007, -2461515231199824166); - assert_eq!(r, transmute(lsx_vmod_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2302,7 +3046,10 @@ unsafe fn test_lsx_vmod_h() { let b = i16x8::new(1550, 9221, -12080, 14553, -24847, 28286, 1074, 192); let r = i64x2::new(3930282117007147005, -10982007906888970); - assert_eq!(r, transmute(lsx_vmod_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2311,7 +3058,10 @@ unsafe fn test_lsx_vmod_w() { let b = i32x4::new(344507881, 1692387020, -1397506903, -1257953510); let r = i64x2::new(-5027973877095011085, 2553570821342119010); - assert_eq!(r, transmute(lsx_vmod_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2320,7 +3070,10 @@ unsafe fn test_lsx_vmod_d() { let b = i64x2::new(4636642606889723746, -259899475747531088); let r = i64x2::new(-1381676014874400835, -257849503742906530); - assert_eq!(r, transmute(lsx_vmod_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2333,7 +3086,13 @@ unsafe fn test_lsx_vmod_bu() { ); let r = i64x2::new(7287961163701724026, 4745974892933063220); - assert_eq!(r, transmute(lsx_vmod_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2342,7 +3101,13 @@ unsafe fn test_lsx_vmod_hu() { let b = u16x8::new(15317, 24954, 61354, 3720, 21471, 6193, 8193, 35745); let r = i64x2::new(315403234587388856, 7101062794264266609); - assert_eq!(r, transmute(lsx_vmod_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2351,7 +3116,13 @@ unsafe fn test_lsx_vmod_wu() { let b = u32x4::new(49228057, 2249712923, 358897384, 1782599598); let r = i64x2::new(1070413902953059662, 3340025749258890964); - assert_eq!(r, transmute(lsx_vmod_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2360,7 +3131,13 @@ unsafe fn test_lsx_vmod_du() { let b = u64x2::new(16850073055169051895, 16069565262862467484); let r = i64x2::new(7747010922784437137, 20234676239478699); - assert_eq!(r, transmute(lsx_vmod_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2370,7 +3147,7 @@ unsafe fn test_lsx_vreplve_b() { ); let r = i64x2::new(-2893606913523066921, -2893606913523066921); - assert_eq!(r, transmute(lsx_vreplve_b(transmute(a), -8))); + assert_eq!(r, transmute(lsx_vreplve_b(black_box(transmute(a)), -8))); } #[simd_test(enable = "lsx")] @@ -2378,7 +3155,7 @@ unsafe fn test_lsx_vreplve_h() { let a = i16x8::new(-29429, -23495, 8705, -7614, -25353, 11887, -25989, -12818); let r = i64x2::new(-3607719825936298514, -3607719825936298514); - assert_eq!(r, transmute(lsx_vreplve_h(transmute(a), 7))); + assert_eq!(r, transmute(lsx_vreplve_h(black_box(transmute(a)), 7))); } #[simd_test(enable = "lsx")] @@ -2386,7 +3163,7 @@ unsafe fn test_lsx_vreplve_w() { let a = i32x4::new(1584940676, 95787593, -1655264847, 682404402); let r = i64x2::new(411404579393346121, 411404579393346121); - assert_eq!(r, transmute(lsx_vreplve_w(transmute(a), -3))); + assert_eq!(r, transmute(lsx_vreplve_w(black_box(transmute(a)), -3))); } #[simd_test(enable = "lsx")] @@ -2394,7 +3171,7 @@ unsafe fn test_lsx_vreplve_d() { let a = i64x2::new(7614424214598615675, -7096892795239148002); let r = i64x2::new(7614424214598615675, 7614424214598615675); - assert_eq!(r, transmute(lsx_vreplve_d(transmute(a), 0))); + assert_eq!(r, transmute(lsx_vreplve_d(black_box(transmute(a)), 0))); } #[simd_test(enable = "lsx")] @@ -2404,7 +3181,7 @@ unsafe fn test_lsx_vreplvei_b() { ); let r = i64x2::new(-2097865012304223518, -2097865012304223518); - assert_eq!(r, transmute(lsx_vreplvei_b::<5>(transmute(a)))); + assert_eq!(r, transmute(lsx_vreplvei_b::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2412,7 +3189,7 @@ unsafe fn test_lsx_vreplvei_h() { let a = i16x8::new(-15455, -4410, 5029, 25863, -23170, 26570, 27423, -834); let r = i64x2::new(7719006069021698847, 7719006069021698847); - assert_eq!(r, transmute(lsx_vreplvei_h::<6>(transmute(a)))); + assert_eq!(r, transmute(lsx_vreplvei_h::<6>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2420,7 +3197,7 @@ unsafe fn test_lsx_vreplvei_w() { let a = i32x4::new(1843143434, 491125746, -328585251, -1996512058); let r = i64x2::new(7916240772710277898, 7916240772710277898); - assert_eq!(r, transmute(lsx_vreplvei_w::<0>(transmute(a)))); + assert_eq!(r, transmute(lsx_vreplvei_w::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2428,7 +3205,7 @@ unsafe fn test_lsx_vreplvei_d() { let a = i64x2::new(4333963848299154309, -8310246545782080694); let r = i64x2::new(-8310246545782080694, -8310246545782080694); - assert_eq!(r, transmute(lsx_vreplvei_d::<1>(transmute(a)))); + assert_eq!(r, transmute(lsx_vreplvei_d::<1>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2441,7 +3218,13 @@ unsafe fn test_lsx_vpickev_b() { ); let r = i64x2::new(3921750152141124833, -933322373843017127); - assert_eq!(r, transmute(lsx_vpickev_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickev_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2450,7 +3233,13 @@ unsafe fn test_lsx_vpickev_h() { let b = i16x8::new(-5248, -1786, -21768, 23214, -4223, 23538, -24936, -32316); let r = i64x2::new(-7018596679058658432, 139073165196191894); - assert_eq!(r, transmute(lsx_vpickev_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickev_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2459,7 +3248,13 @@ unsafe fn test_lsx_vpickev_w() { let b = i32x4::new(-1187277846, -787064901, -980229113, 1746235326); let r = i64x2::new(-4210051979814398998, -769258006856513132); - assert_eq!(r, transmute(lsx_vpickev_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickev_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2468,7 +3263,13 @@ unsafe fn test_lsx_vpickev_d() { let b = i64x2::new(6574352346370076190, -3979792156310826694); let r = i64x2::new(6574352346370076190, 1789073368466131160); - assert_eq!(r, transmute(lsx_vpickev_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickev_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2481,7 +3282,13 @@ unsafe fn test_lsx_vpickod_b() { ); let r = i64x2::new(8220640377280882872, -6083110277645985532); - assert_eq!(r, transmute(lsx_vpickod_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickod_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2490,7 +3297,13 @@ unsafe fn test_lsx_vpickod_h() { let b = i16x8::new(12047, 25024, -10709, -28077, 24357, 19934, 10289, 28546); let r = i64x2::new(8035070303515402688, 6167254016163165900); - assert_eq!(r, transmute(lsx_vpickod_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickod_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2499,7 +3312,13 @@ unsafe fn test_lsx_vpickod_w() { let b = i32x4::new(-99240403, 314407358, 543396756, 1976776696); let r = i64x2::new(8490191261129341374, -7045044594236590438); - assert_eq!(r, transmute(lsx_vpickod_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickod_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2508,7 +3327,13 @@ unsafe fn test_lsx_vpickod_d() { let b = i64x2::new(-4197243771252175958, -543692393753629390); let r = i64x2::new(-543692393753629390, -7578696032343374601); - assert_eq!(r, transmute(lsx_vpickod_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickod_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2521,7 +3346,13 @@ unsafe fn test_lsx_vilvh_b() { ); let r = i64x2::new(1211180715666052671, -2634368371891034045); - assert_eq!(r, transmute(lsx_vilvh_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvh_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2530,7 +3361,13 @@ unsafe fn test_lsx_vilvh_h() { let b = i16x8::new(23768, -31845, 28689, 14757, 9499, 7795, -13573, -10011); let r = i64x2::new(-4714953853167983333, 4564918175499275003); - assert_eq!(r, transmute(lsx_vilvh_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvh_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2539,7 +3376,13 @@ unsafe fn test_lsx_vilvh_w() { let b = i32x4::new(-737076987, 38515006, 602108871, -63099569); let r = i64x2::new(-5365723764939852857, -1200522227779556017); - assert_eq!(r, transmute(lsx_vilvh_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvh_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2548,7 +3391,13 @@ unsafe fn test_lsx_vilvh_d() { let b = i64x2::new(-2160658667838026389, 1449429407527660400); let r = i64x2::new(1449429407527660400, 5375050218784453679); - assert_eq!(r, transmute(lsx_vilvh_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvh_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2561,7 +3410,13 @@ unsafe fn test_lsx_vilvl_b() { ); let r = i64x2::new(6945744258789947856, 8515979671552484861); - assert_eq!(r, transmute(lsx_vilvl_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvl_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2570,7 +3425,13 @@ unsafe fn test_lsx_vilvl_h() { let b = i16x8::new(11601, 6788, 3174, -4208, -25999, -25660, -4591, 7133); let r = i64x2::new(-6560589601043632815, -2260825085889541018); - assert_eq!(r, transmute(lsx_vilvl_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvl_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2579,7 +3440,13 @@ unsafe fn test_lsx_vilvl_w() { let b = i32x4::new(486029703, 1245981961, 112180197, 1939621508); let r = i64x2::new(-4282490222245561977, 7435326725564935433); - assert_eq!(r, transmute(lsx_vilvl_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvl_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2588,7 +3455,13 @@ unsafe fn test_lsx_vilvl_d() { let b = i64x2::new(3142531875873363679, 736682102982019415); let r = i64x2::new(3142531875873363679, 7063413230460842607); - assert_eq!(r, transmute(lsx_vilvl_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvl_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2601,7 +3474,13 @@ unsafe fn test_lsx_vpackev_b() { ); let r = i64x2::new(-1928363389519380677, -1882898104368665381); - assert_eq!(r, transmute(lsx_vpackev_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackev_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2610,7 +3489,13 @@ unsafe fn test_lsx_vpackev_h() { let b = i16x8::new(-9444, 5210, -14402, 17972, 16606, 2450, 5123, 14727); let r = i64x2::new(7533052947329899292, 1461440082551914718); - assert_eq!(r, transmute(lsx_vpackev_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackev_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2619,7 +3504,13 @@ unsafe fn test_lsx_vpackev_w() { let b = i32x4::new(-872903277, 1255047449, -2110158279, 682925573); let r = i64x2::new(5636997704425442707, -8345976908349339079); - assert_eq!(r, transmute(lsx_vpackev_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackev_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2628,7 +3519,13 @@ unsafe fn test_lsx_vpackev_d() { let b = i64x2::new(-9119315954224042738, -4563700463464702181); let r = i64x2::new(-9119315954224042738, 7118943335298607169); - assert_eq!(r, transmute(lsx_vpackev_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackev_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2641,7 +3538,13 @@ unsafe fn test_lsx_vpackod_b() { ); let r = i64x2::new(4389351353151377653, -4315624792288929032); - assert_eq!(r, transmute(lsx_vpackod_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackod_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2650,7 +3553,13 @@ unsafe fn test_lsx_vpackod_h() { let b = i16x8::new(-23247, 17928, -13353, -20146, 5696, 22071, -10728, -30262); let r = i64x2::new(-4433598883325590008, -9178747487946648009); - assert_eq!(r, transmute(lsx_vpackod_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackod_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2659,7 +3568,13 @@ unsafe fn test_lsx_vpackod_w() { let b = i32x4::new(445270781, 793617340, -1461557030, -22199234); let r = i64x2::new(51238874735551420, 6731566319615689790); - assert_eq!(r, transmute(lsx_vpackod_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackod_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2668,7 +3583,13 @@ unsafe fn test_lsx_vpackod_d() { let b = i64x2::new(9039771682296134623, -6404442538060227683); let r = i64x2::new(-6404442538060227683, -4670773907187480618); - assert_eq!(r, transmute(lsx_vpackod_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackod_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2680,7 +3601,11 @@ unsafe fn test_lsx_vshuf_h() { assert_eq!( r, - transmute(lsx_vshuf_h(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vshuf_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2693,7 +3618,11 @@ unsafe fn test_lsx_vshuf_w() { assert_eq!( r, - transmute(lsx_vshuf_w(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vshuf_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2706,7 +3635,11 @@ unsafe fn test_lsx_vshuf_d() { assert_eq!( r, - transmute(lsx_vshuf_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vshuf_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2720,7 +3653,10 @@ unsafe fn test_lsx_vand_v() { ); let r = i64x2::new(244105884219744360, -9223116804091473582); - assert_eq!(r, transmute(lsx_vand_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vand_v(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2730,7 +3666,7 @@ unsafe fn test_lsx_vandi_b() { ); let r = i64x2::new(-8135737750142058361, -7666517314596397435); - assert_eq!(r, transmute(lsx_vandi_b::<159>(transmute(a)))); + assert_eq!(r, transmute(lsx_vandi_b::<159>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2743,7 +3679,10 @@ unsafe fn test_lsx_vor_v() { ); let r = i64x2::new(-2351582766212852737, -4924766118269159990); - assert_eq!(r, transmute(lsx_vor_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vor_v(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2753,7 +3692,7 @@ unsafe fn test_lsx_vori_b() { ); let r = i64x2::new(-589140355308650538, -3179554720060804109); - assert_eq!(r, transmute(lsx_vori_b::<210>(transmute(a)))); + assert_eq!(r, transmute(lsx_vori_b::<210>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2766,7 +3705,10 @@ unsafe fn test_lsx_vnor_v() { ); let r = i64x2::new(3036560889408918025, 7823034030269427744); - assert_eq!(r, transmute(lsx_vnor_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vnor_v(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2776,7 +3718,7 @@ unsafe fn test_lsx_vnori_b() { ); let r = i64x2::new(5227628601268782144, 596802560304890884); - assert_eq!(r, transmute(lsx_vnori_b::<51>(transmute(a)))); + assert_eq!(r, transmute(lsx_vnori_b::<51>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2789,7 +3731,10 @@ unsafe fn test_lsx_vxor_v() { ); let r = i64x2::new(8732028225622312747, 6858262329367852470); - assert_eq!(r, transmute(lsx_vxor_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vxor_v(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2799,7 +3744,7 @@ unsafe fn test_lsx_vxori_b() { ); let r = i64x2::new(3478586993001400570, 4687744515358339026); - assert_eq!(r, transmute(lsx_vxori_b::<225>(transmute(a)))); + assert_eq!(r, transmute(lsx_vxori_b::<225>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2817,7 +3762,11 @@ unsafe fn test_lsx_vbitsel_v() { assert_eq!( r, - transmute(lsx_vbitsel_v(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vbitsel_v( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2833,7 +3782,10 @@ unsafe fn test_lsx_vbitseli_b() { assert_eq!( r, - transmute(lsx_vbitseli_b::<65>(transmute(a), transmute(b))) + transmute(lsx_vbitseli_b::<65>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -2844,7 +3796,7 @@ unsafe fn test_lsx_vshuf4i_b() { ); let r = i64x2::new(3937170420478429898, -3347145886530736916); - assert_eq!(r, transmute(lsx_vshuf4i_b::<234>(transmute(a)))); + assert_eq!(r, transmute(lsx_vshuf4i_b::<234>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2852,7 +3804,7 @@ unsafe fn test_lsx_vshuf4i_h() { let a = i16x8::new(27707, -1094, -15784, -28387, 31634, -12323, -30387, -11480); let r = i64x2::new(-7989953385787032646, -3231104182470389795); - assert_eq!(r, transmute(lsx_vshuf4i_h::<209>(transmute(a)))); + assert_eq!(r, transmute(lsx_vshuf4i_h::<209>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2860,35 +3812,38 @@ unsafe fn test_lsx_vshuf4i_w() { let a = i32x4::new(768986805, -1036149600, -1196682940, -214444511); let r = i64x2::new(3302773179299516085, -5139714087882845884); - assert_eq!(r, transmute(lsx_vshuf4i_w::<160>(transmute(a)))); + assert_eq!(r, transmute(lsx_vshuf4i_w::<160>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] unsafe fn test_lsx_vreplgr2vr_b() { let r = i64x2::new(795741901218843403, 795741901218843403); - assert_eq!(r, transmute(lsx_vreplgr2vr_b(970839819))); + assert_eq!(r, transmute(lsx_vreplgr2vr_b(black_box(970839819)))); } #[simd_test(enable = "lsx")] unsafe fn test_lsx_vreplgr2vr_h() { let r = i64x2::new(-6504141532176800324, -6504141532176800324); - assert_eq!(r, transmute(lsx_vreplgr2vr_h(93693372))); + assert_eq!(r, transmute(lsx_vreplgr2vr_h(black_box(93693372)))); } #[simd_test(enable = "lsx")] unsafe fn test_lsx_vreplgr2vr_w() { let r = i64x2::new(-6737078705572473188, -6737078705572473188); - assert_eq!(r, transmute(lsx_vreplgr2vr_w(-1568598372))); + assert_eq!(r, transmute(lsx_vreplgr2vr_w(black_box(-1568598372)))); } #[simd_test(enable = "lsx")] unsafe fn test_lsx_vreplgr2vr_d() { let r = i64x2::new(5000134708087557572, 5000134708087557572); - assert_eq!(r, transmute(lsx_vreplgr2vr_d(5000134708087557572))); + assert_eq!( + r, + transmute(lsx_vreplgr2vr_d(black_box(5000134708087557572))) + ); } #[simd_test(enable = "lsx")] @@ -2898,7 +3853,7 @@ unsafe fn test_lsx_vpcnt_b() { ); let r = i64x2::new(217867142450840068, 145528077781566722); - assert_eq!(r, transmute(lsx_vpcnt_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vpcnt_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2906,7 +3861,7 @@ unsafe fn test_lsx_vpcnt_h() { let a = i16x8::new(-512, 10388, -21267, -27094, 1085, -26444, -29360, -11576); let r = i64x2::new(1970367786975239, 1970350607237126); - assert_eq!(r, transmute(lsx_vpcnt_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vpcnt_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2914,7 +3869,7 @@ unsafe fn test_lsx_vpcnt_w() { let a = i32x4::new(1399276601, -2094725994, -100739325, -1239551533); let r = i64x2::new(47244640271, 81604378645); - assert_eq!(r, transmute(lsx_vpcnt_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vpcnt_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2922,7 +3877,7 @@ unsafe fn test_lsx_vpcnt_d() { let a = i64x2::new(-4470823169399930539, 3184270543884128372); let r = i64x2::new(29, 25); - assert_eq!(r, transmute(lsx_vpcnt_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vpcnt_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2932,7 +3887,7 @@ unsafe fn test_lsx_vclo_b() { ); let r = i64x2::new(72057594071547904, 3311470116864); - assert_eq!(r, transmute(lsx_vclo_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vclo_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2940,7 +3895,7 @@ unsafe fn test_lsx_vclo_h() { let a = i16x8::new(-5432, 27872, -9150, 27393, 25236, 1028, -21312, -25189); let r = i64x2::new(8589934595, 281479271677952); - assert_eq!(r, transmute(lsx_vclo_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vclo_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2948,7 +3903,7 @@ unsafe fn test_lsx_vclo_w() { let a = i32x4::new(1214322611, -1755838761, -1222326743, -1511364419); let r = i64x2::new(4294967296, 4294967297); - assert_eq!(r, transmute(lsx_vclo_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vclo_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2956,7 +3911,7 @@ unsafe fn test_lsx_vclo_d() { let a = i64x2::new(-249299854527467825, -459308653408461862); let r = i64x2::new(6, 5); - assert_eq!(r, transmute(lsx_vclo_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vclo_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2966,7 +3921,7 @@ unsafe fn test_lsx_vclz_b() { ); let r = i64x2::new(144116287587483648, 72903118479688195); - assert_eq!(r, transmute(lsx_vclz_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vclz_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2974,7 +3929,7 @@ unsafe fn test_lsx_vclz_h() { let a = i16x8::new(1222, 32426, 3164, -10763, 10189, -4197, -21841, -28676); let r = i64x2::new(17179934725, 2); - assert_eq!(r, transmute(lsx_vclz_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vclz_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2982,7 +3937,7 @@ unsafe fn test_lsx_vclz_w() { let a = i32x4::new(-490443689, -1039971379, -217310592, -1921086575); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vclz_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vclz_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2990,7 +3945,7 @@ unsafe fn test_lsx_vclz_d() { let a = i64x2::new(4630351532137644314, -6587611980764816064); let r = i64x2::new(1, 0); - assert_eq!(r, transmute(lsx_vclz_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vclz_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3000,7 +3955,10 @@ unsafe fn test_lsx_vpickve2gr_b() { ); let r: i32 = 51; - assert_eq!(r, transmute(lsx_vpickve2gr_b::<15>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vpickve2gr_b::<15>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3008,7 +3966,7 @@ unsafe fn test_lsx_vpickve2gr_h() { let a = i16x8::new(-12924, 31013, 18171, 20404, 21226, 14128, -6255, 26521); let r: i32 = 21226; - assert_eq!(r, transmute(lsx_vpickve2gr_h::<4>(transmute(a)))); + assert_eq!(r, transmute(lsx_vpickve2gr_h::<4>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3016,7 +3974,7 @@ unsafe fn test_lsx_vpickve2gr_w() { let a = i32x4::new(-1559379275, 2065542381, -1882161334, 1502157419); let r: i32 = -1882161334; - assert_eq!(r, transmute(lsx_vpickve2gr_w::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vpickve2gr_w::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3024,7 +3982,7 @@ unsafe fn test_lsx_vpickve2gr_d() { let a = i64x2::new(-6941380853339482104, 8405634758774935528); let r: i64 = -6941380853339482104; - assert_eq!(r, transmute(lsx_vpickve2gr_d::<0>(transmute(a)))); + assert_eq!(r, transmute(lsx_vpickve2gr_d::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3034,7 +3992,10 @@ unsafe fn test_lsx_vpickve2gr_bu() { ); let r: u32 = 199; - assert_eq!(r, transmute(lsx_vpickve2gr_bu::<8>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vpickve2gr_bu::<8>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3042,7 +4003,10 @@ unsafe fn test_lsx_vpickve2gr_hu() { let a = i16x8::new(25003, 5139, -12977, 7550, -12177, 19294, -2216, 12693); let r: u32 = 25003; - assert_eq!(r, transmute(lsx_vpickve2gr_hu::<0>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vpickve2gr_hu::<0>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3050,7 +4014,10 @@ unsafe fn test_lsx_vpickve2gr_wu() { let a = i32x4::new(-295894883, 551663550, -710853968, 82692774); let r: u32 = 3999072413; - assert_eq!(r, transmute(lsx_vpickve2gr_wu::<0>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vpickve2gr_wu::<0>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3058,7 +4025,10 @@ unsafe fn test_lsx_vpickve2gr_du() { let a = i64x2::new(748282319555413922, -1352335765832355666); let r: u64 = 748282319555413922; - assert_eq!(r, transmute(lsx_vpickve2gr_du::<0>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vpickve2gr_du::<0>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3070,7 +4040,7 @@ unsafe fn test_lsx_vinsgr2vr_b() { assert_eq!( r, - transmute(lsx_vinsgr2vr_b::<14>(transmute(a), 1333652061)) + transmute(lsx_vinsgr2vr_b::<14>(black_box(transmute(a)), 1333652061)) ); } @@ -3079,7 +4049,10 @@ unsafe fn test_lsx_vinsgr2vr_h() { let a = i16x8::new(-20591, 7819, 25287, -11296, 4604, 28833, -1306, 6418); let r = i64x2::new(-3179432729573085295, 1806782266980897276); - assert_eq!(r, transmute(lsx_vinsgr2vr_h::<5>(transmute(a), -987420193))); + assert_eq!( + r, + transmute(lsx_vinsgr2vr_h::<5>(black_box(transmute(a)), -987420193)) + ); } #[simd_test(enable = "lsx")] @@ -3087,7 +4060,10 @@ unsafe fn test_lsx_vinsgr2vr_w() { let a = i32x4::new(1608179655, 886830932, -621638499, 2021214690); let r = i64x2::new(3808909851629379527, 8681050995079237782); - assert_eq!(r, transmute(lsx_vinsgr2vr_w::<2>(transmute(a), -960507754))); + assert_eq!( + r, + transmute(lsx_vinsgr2vr_w::<2>(black_box(transmute(a)), -960507754)) + ); } #[simd_test(enable = "lsx")] @@ -3095,7 +4071,10 @@ unsafe fn test_lsx_vinsgr2vr_d() { let a = i64x2::new(-6562091001143116290, -2425423285843953307); let r = i64x2::new(-6562091001143116290, -233659266); - assert_eq!(r, transmute(lsx_vinsgr2vr_d::<1>(transmute(a), -233659266))); + assert_eq!( + r, + transmute(lsx_vinsgr2vr_d::<1>(black_box(transmute(a)), -233659266)) + ); } #[simd_test(enable = "lsx")] @@ -3104,7 +4083,13 @@ unsafe fn test_lsx_vfadd_s() { let b = u32x4::new(1050272808, 1054022924, 1064036136, 1063113730); let r = i64x2::new(4588396142719948771, 4567018621615066847); - assert_eq!(r, transmute(lsx_vfadd_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfadd_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3113,7 +4098,13 @@ unsafe fn test_lsx_vfadd_d() { let b = u64x2::new(4605819027271079334, 4601207158507578498); let r = i64x2::new(4608685566198055604, 4608371493448991663); - assert_eq!(r, transmute(lsx_vfadd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfadd_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3122,7 +4113,13 @@ unsafe fn test_lsx_vfsub_s() { let b = u32x4::new(1063475462, 1045836432, 1065150677, 1042376676); let r = i64x2::new(4532926601401089072, 4475386505810184670); - assert_eq!(r, transmute(lsx_vfsub_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfsub_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3131,7 +4128,13 @@ unsafe fn test_lsx_vfsub_d() { let b = u64x2::new(4605973926398825814, 4600156145303017004); let r = i64x2::new(-4622342180736116526, 4603750919602422881); - assert_eq!(r, transmute(lsx_vfsub_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfsub_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3140,7 +4143,13 @@ unsafe fn test_lsx_vfmul_s() { let b = u32x4::new(1065241951, 1044285812, 1050678216, 1009264512); let r = i64x2::new(4471727895898079441, 4289440988347233543); - assert_eq!(r, transmute(lsx_vfmul_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmul_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3149,7 +4158,13 @@ unsafe fn test_lsx_vfmul_d() { let b = u64x2::new(4605208047666947899, 4599634375243914522); let r = i64x2::new(4591550625791030606, 4595475933048682142); - assert_eq!(r, transmute(lsx_vfmul_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmul_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3158,7 +4173,13 @@ unsafe fn test_lsx_vfdiv_s() { let b = u32x4::new(1055538538, 1042248668, 1061233585, 1063649172); let r = i64x2::new(4613180427594946541, 4523223175100126088); - assert_eq!(r, transmute(lsx_vfdiv_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfdiv_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3167,7 +4188,13 @@ unsafe fn test_lsx_vfdiv_d() { let b = u64x2::new(4606326032528596062, 4601783079746725386); let r = i64x2::new(4592460108638699314, 4612120084672695832); - assert_eq!(r, transmute(lsx_vfdiv_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfdiv_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3176,7 +4203,13 @@ unsafe fn test_lsx_vfcvt_h_s() { let b = u32x4::new(1049501482, 1043939972, 1042291392, 1041250232); let r = i64x2::new(3495410141992989809, 3873441386606634666); - assert_eq!(r, transmute(lsx_vfcvt_h_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcvt_h_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3185,7 +4218,13 @@ unsafe fn test_lsx_vfcvt_s_d() { let b = u64x2::new(4600251021237488420, 4593890179408150924); let r = i64x2::new(4469319308295208818, 4496796258465732597); - assert_eq!(r, transmute(lsx_vfcvt_s_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcvt_s_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3194,7 +4233,13 @@ unsafe fn test_lsx_vfmin_s() { let b = u32x4::new(1060093085, 1026130528, 1057322097, 1057646773); let r = i64x2::new(4407197060203522560, 4542558301798153756); - assert_eq!(r, transmute(lsx_vfmin_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmin_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3203,7 +4248,13 @@ unsafe fn test_lsx_vfmin_d() { let b = u64x2::new(4584808359801648672, 4602712060570539582); let r = i64x2::new(4584808359801648672, 4602712060570539582); - assert_eq!(r, transmute(lsx_vfmin_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmin_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3212,7 +4263,13 @@ unsafe fn test_lsx_vfmina_s() { let b = u32x4::new(1049119234, 1058336224, 1057046116, 1029386720); let r = i64x2::new(4519411155382848002, 4421182298393539560); - assert_eq!(r, transmute(lsx_vfmina_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmina_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3221,7 +4278,13 @@ unsafe fn test_lsx_vfmina_d() { let b = u64x2::new(4599088744110071826, 4598732503789588496); let r = i64x2::new(4599088744110071826, 4598732503789588496); - assert_eq!(r, transmute(lsx_vfmina_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmina_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3230,7 +4293,13 @@ unsafe fn test_lsx_vfmax_s() { let b = u32x4::new(1042175760, 1040826492, 1059132266, 1050815434); let r = i64x2::new(4557520760982391874, 4573984521684325226); - assert_eq!(r, transmute(lsx_vfmax_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmax_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3239,7 +4308,13 @@ unsafe fn test_lsx_vfmax_d() { let b = u64x2::new(4593616624275112016, 4605244843740986156); let r = i64x2::new(4606275407710467505, 4605244843740986156); - assert_eq!(r, transmute(lsx_vfmax_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmax_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3248,7 +4323,13 @@ unsafe fn test_lsx_vfmaxa_s() { let b = u32x4::new(1064739422, 1055122552, 1049654310, 1057411362); let r = i64x2::new(4531716855176798814, 4541547219258471462); - assert_eq!(r, transmute(lsx_vfmaxa_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmaxa_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3257,7 +4338,13 @@ unsafe fn test_lsx_vfmaxa_d() { let b = u64x2::new(4603647289310579471, 4603999027307573908); let r = i64x2::new(4603647289310579471, 4606304546706191737); - assert_eq!(r, transmute(lsx_vfmaxa_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmaxa_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3265,7 +4352,7 @@ unsafe fn test_lsx_vfclass_s() { let a = u32x4::new(1059786314, 1058231666, 1061513647, 1038650488); let r = i64x2::new(549755814016, 549755814016); - assert_eq!(r, transmute(lsx_vfclass_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfclass_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3273,7 +4360,7 @@ unsafe fn test_lsx_vfclass_d() { let a = u64x2::new(4601724705608768104, 4601126152607382566); let r = i64x2::new(128, 128); - assert_eq!(r, transmute(lsx_vfclass_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfclass_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3281,7 +4368,7 @@ unsafe fn test_lsx_vfsqrt_s() { let a = u32x4::new(1055398716, 1050305974, 995168768, 1064901995); let r = i64x2::new(4543169501430832482, 4574681629207255333); - assert_eq!(r, transmute(lsx_vfsqrt_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfsqrt_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3289,7 +4376,7 @@ unsafe fn test_lsx_vfsqrt_d() { let a = u64x2::new(4605784293613801157, 4602267946351406890); let r = i64x2::new(4606453893731357485, 4604397310232711799); - assert_eq!(r, transmute(lsx_vfsqrt_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfsqrt_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3297,7 +4384,7 @@ unsafe fn test_lsx_vfrecip_s() { let a = u32x4::new(1003452672, 1050811504, 1044295808, 1064402913); let r = i64x2::new(4632552602764963931, 4577820515916044016); - assert_eq!(r, transmute(lsx_vfrecip_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrecip_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3305,7 +4392,7 @@ unsafe fn test_lsx_vfrecip_d() { let a = u64x2::new(4598634931235673106, 4598630619264835010); let r = i64x2::new(4615355353482170689, 4615362460048142095); - assert_eq!(r, transmute(lsx_vfrecip_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrecip_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx,frecipe")] @@ -3313,7 +4400,7 @@ unsafe fn test_lsx_vfrecipe_s() { let a = u32x4::new(1057583779, 1062308847, 1060089100, 1048454688); let r = i64x2::new(4583644530211711115, 4647978179615164140); - assert_eq!(r, transmute(lsx_vfrecipe_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrecipe_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx,frecipe")] @@ -3321,7 +4408,7 @@ unsafe fn test_lsx_vfrecipe_d() { let a = u64x2::new(4605515926442181274, 4605369703273365674); let r = i64x2::new(4608204937770303488, 4608317161507651584); - assert_eq!(r, transmute(lsx_vfrecipe_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrecipe_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx,frecipe")] @@ -3329,7 +4416,7 @@ unsafe fn test_lsx_vfrsqrte_s() { let a = u32x4::new(1064377488, 1055815904, 1056897740, 1064016656); let r = i64x2::new(4592421282989204764, 4577184195020153336); - assert_eq!(r, transmute(lsx_vfrsqrte_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrsqrte_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx,frecipe")] @@ -3337,7 +4424,7 @@ unsafe fn test_lsx_vfrsqrte_d() { let a = u64x2::new(4602766865443628663, 4605323203937791867); let r = i64x2::new(4608986772678901760, 4607734355383549952); - assert_eq!(r, transmute(lsx_vfrsqrte_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrsqrte_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3345,7 +4432,7 @@ unsafe fn test_lsx_vfrint_s() { let a = u32x4::new(1062138521, 1056849108, 1034089720, 1038314384); let r = i64x2::new(1065353216, 0); - assert_eq!(r, transmute(lsx_vfrint_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrint_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3353,7 +4440,7 @@ unsafe fn test_lsx_vfrint_d() { let a = u64x2::new(4598620052333442366, 4603262362368837514); let r = i64x2::new(0, 4607182418800017408); - assert_eq!(r, transmute(lsx_vfrint_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrint_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3361,7 +4448,7 @@ unsafe fn test_lsx_vfrsqrt_s() { let a = u32x4::new(1058614029, 1050504950, 1013814976, 1062355001); let r = i64x2::new(4604601921912011494, 4579384257679777264); - assert_eq!(r, transmute(lsx_vfrsqrt_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrsqrt_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3369,7 +4456,7 @@ unsafe fn test_lsx_vfrsqrt_d() { let a = u64x2::new(4602924191185043139, 4606088351077917251); let r = i64x2::new(4608881149202581394, 4607483676176768181); - assert_eq!(r, transmute(lsx_vfrsqrt_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrsqrt_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3377,7 +4464,7 @@ unsafe fn test_lsx_vflogb_s() { let a = u32x4::new(1053488512, 1061429282, 1064965594, 1061326585); let r = i64x2::new(-4647714812225126400, -4647714812233515008); - assert_eq!(r, transmute(lsx_vflogb_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vflogb_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3385,7 +4472,7 @@ unsafe fn test_lsx_vflogb_d() { let a = u64x2::new(4589481276789128632, 4599408395082246526); let r = i64x2::new(-4607182418800017408, -4611686018427387904); - assert_eq!(r, transmute(lsx_vflogb_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vflogb_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3393,7 +4480,7 @@ unsafe fn test_lsx_vfcvth_s_h() { let a = i16x8::new(29550, -13884, 689, -1546, 24006, -19112, -12769, 1779); let r = i64x2::new(-4707668984349540352, 4097818267320836096); - assert_eq!(r, transmute(lsx_vfcvth_s_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vfcvth_s_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3401,7 +4488,7 @@ unsafe fn test_lsx_vfcvth_d_s() { let a = u32x4::new(1051543000, 1042275304, 1038283216, 1063876621); let r = i64x2::new(4592649323212177408, 4606389677895712768); - assert_eq!(r, transmute(lsx_vfcvth_d_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfcvth_d_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3409,7 +4496,7 @@ unsafe fn test_lsx_vfcvtl_s_h() { let a = i16x8::new(-21951, -13772, -17190, 9566, -19227, 9682, 13427, -30861); let r = i64x2::new(-4519784435355738112, 4371798972740354048); - assert_eq!(r, transmute(lsx_vfcvtl_s_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vfcvtl_s_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3417,7 +4504,7 @@ unsafe fn test_lsx_vfcvtl_d_s() { let a = u32x4::new(1059809930, 1051084496, 1062618346, 1058273673); let r = i64x2::new(4604206389789720576, 4599521958080544768); - assert_eq!(r, transmute(lsx_vfcvtl_d_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfcvtl_d_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3425,7 +4512,7 @@ unsafe fn test_lsx_vftint_w_s() { let a = u32x4::new(1064738153, 1040181800, 1064331056, 1050732566); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vftint_w_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftint_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3433,7 +4520,7 @@ unsafe fn test_lsx_vftint_l_d() { let a = u64x2::new(4602244632405616462, 4606437548563176328); let r = i64x2::new(0, 1); - assert_eq!(r, transmute(lsx_vftint_l_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vftint_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3441,7 +4528,7 @@ unsafe fn test_lsx_vftint_wu_s() { let a = u32x4::new(1051598962, 1051261298, 1059326008, 1057784192); let r = i64x2::new(0, 4294967297); - assert_eq!(r, transmute(lsx_vftint_wu_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftint_wu_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3449,7 +4536,7 @@ unsafe fn test_lsx_vftint_lu_d() { let a = u64x2::new(4605561240422589260, 4595241299507769712); let r = i64x2::new(1, 0); - assert_eq!(r, transmute(lsx_vftint_lu_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vftint_lu_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3457,7 +4544,7 @@ unsafe fn test_lsx_vftintrz_w_s() { let a = u32x4::new(1027659872, 1064207676, 1058472873, 1055740014); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrz_w_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrz_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3465,7 +4552,7 @@ unsafe fn test_lsx_vftintrz_l_d() { let a = u64x2::new(4605051539601556532, 4605129242354661923); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrz_l_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrz_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3473,7 +4560,7 @@ unsafe fn test_lsx_vftintrz_wu_s() { let a = u32x4::new(1060876751, 1053710034, 1057340881, 1055555596); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrz_wu_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrz_wu_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3481,7 +4568,7 @@ unsafe fn test_lsx_vftintrz_lu_d() { let a = u64x2::new(4598711097624940956, 4598268778109474002); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrz_lu_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrz_lu_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3489,7 +4576,7 @@ unsafe fn test_lsx_vffint_s_w() { let a = i32x4::new(81337967, 1396520141, 2124859806, 1655115736); let r = i64x2::new(5667351778062705614, 5676028806041521555); - assert_eq!(r, transmute(lsx_vffint_s_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vffint_s_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3497,7 +4584,7 @@ unsafe fn test_lsx_vffint_d_l() { let a = i64x2::new(-1543454772280682525, -7672333112582708041); let r = i64x2::new(-4344448119835677720, -4333977527979901593); - assert_eq!(r, transmute(lsx_vffint_d_l(transmute(a)))); + assert_eq!(r, transmute(lsx_vffint_d_l(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3505,7 +4592,7 @@ unsafe fn test_lsx_vffint_s_wu() { let a = u32x4::new(2224947834, 194720725, 2248289069, 1131100007); let r = i64x2::new(5564675890493038082, 5658445755393114667); - assert_eq!(r, transmute(lsx_vffint_s_wu(transmute(a)))); + assert_eq!(r, transmute(lsx_vffint_s_wu(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3513,7 +4600,7 @@ unsafe fn test_lsx_vffint_d_lu() { let a = u64x2::new(11793247389644223387, 1356636411353166515); let r = i64x2::new(4892164017273962878, 4878194157796724979); - assert_eq!(r, transmute(lsx_vffint_d_lu(transmute(a)))); + assert_eq!(r, transmute(lsx_vffint_d_lu(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3526,7 +4613,13 @@ unsafe fn test_lsx_vandn_v() { ); let r = i64x2::new(184648152262214664, 2315143230533931624); - assert_eq!(r, transmute(lsx_vandn_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vandn_v( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3536,7 +4629,7 @@ unsafe fn test_lsx_vneg_b() { ); let r = i64x2::new(-6195839201974406282, 3566844512212398771); - assert_eq!(r, transmute(lsx_vneg_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vneg_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3544,7 +4637,7 @@ unsafe fn test_lsx_vneg_h() { let a = i16x8::new(-6540, 25893, -2534, 29805, -28719, -16331, -20168, 14650); let r = i64x2::new(-8389350794815923828, -4123521786840387537); - assert_eq!(r, transmute(lsx_vneg_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vneg_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3552,7 +4645,7 @@ unsafe fn test_lsx_vneg_w() { let a = i32x4::new(-927815384, -898911982, 716171852, -2025175544); let r = i64x2::new(3860797565600356056, 8698062733717804468); - assert_eq!(r, transmute(lsx_vneg_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vneg_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3560,7 +4653,7 @@ unsafe fn test_lsx_vneg_d() { let a = i64x2::new(4241851098775470984, 2487122929432859927); let r = i64x2::new(-4241851098775470984, -2487122929432859927); - assert_eq!(r, transmute(lsx_vneg_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vneg_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3573,7 +4666,10 @@ unsafe fn test_lsx_vmuh_b() { ); let r = i64x2::new(931993372669836524, 2017024359980467698); - assert_eq!(r, transmute(lsx_vmuh_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -3582,7 +4678,10 @@ unsafe fn test_lsx_vmuh_h() { let b = i16x8::new(-446, -16863, 19467, -13578, -9673, -26572, -7864, 9855); let r = i64x2::new(-1422322400225984462, -842721997477184351); - assert_eq!(r, transmute(lsx_vmuh_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -3591,7 +4690,10 @@ unsafe fn test_lsx_vmuh_w() { let b = i32x4::new(-1684820454, 449222301, 1106076122, 431017950); let r = i64x2::new(-950505610786872114, 420439596918869732); - assert_eq!(r, transmute(lsx_vmuh_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -3600,7 +4702,10 @@ unsafe fn test_lsx_vmuh_d() { let b = i64x2::new(-1208434038665242614, -6078343251861677818); let r = i64x2::new(-121343209662433286, 284995587689374477); - assert_eq!(r, transmute(lsx_vmuh_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -3613,7 +4718,13 @@ unsafe fn test_lsx_vmuh_bu() { ); let r = i64x2::new(8725461799780227590, -3369022092985820632); - assert_eq!(r, transmute(lsx_vmuh_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3622,7 +4733,13 @@ unsafe fn test_lsx_vmuh_hu() { let b = u16x8::new(14769, 6489, 58866, 5997, 46648, 26325, 42186, 26942); let r = i64x2::new(1572068217944938757, 4366267597274655896); - assert_eq!(r, transmute(lsx_vmuh_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3631,7 +4748,13 @@ unsafe fn test_lsx_vmuh_wu() { let b = u32x4::new(1981234883, 1290836259, 1284878577, 702668871); let r = i64x2::new(4011887256539048298, 960560772888018584); - assert_eq!(r, transmute(lsx_vmuh_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3640,7 +4763,13 @@ unsafe fn test_lsx_vmuh_du() { let b = u64x2::new(14805542397189366587, 10025341254588295994); let r = i64x2::new(-9132083796568587258, 2493261783600858707); - assert_eq!(r, transmute(lsx_vmuh_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3650,7 +4779,7 @@ unsafe fn test_lsx_vsllwil_h_b() { ); let r = i64x2::new(-990777899147527584, 126109727303143360); - assert_eq!(r, transmute(lsx_vsllwil_h_b::<5>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsllwil_h_b::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3658,7 +4787,7 @@ unsafe fn test_lsx_vsllwil_w_h() { let a = i16x8::new(25135, -4241, 25399, -32451, 5597, -16847, 3192, -14694); let r = i64x2::new(-9326057613926912, -71360503652913664); - assert_eq!(r, transmute(lsx_vsllwil_w_h::<9>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsllwil_w_h::<9>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3666,7 +4795,7 @@ unsafe fn test_lsx_vsllwil_d_w() { let a = i32x4::new(1472328927, -2106442262, 379100488, -607174188); let r = i64x2::new(6030659284992, -8627987505152); - assert_eq!(r, transmute(lsx_vsllwil_d_w::<12>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsllwil_d_w::<12>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3676,7 +4805,10 @@ unsafe fn test_lsx_vsllwil_hu_bu() { ); let r = i64x2::new(6953679870551405312, 6809531147446388736); - assert_eq!(r, transmute(lsx_vsllwil_hu_bu::<7>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vsllwil_hu_bu::<7>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3684,7 +4816,10 @@ unsafe fn test_lsx_vsllwil_wu_hu() { let a = u16x8::new(370, 47410, 29611, 6206, 10390, 34658, 65264, 5264); let r = i64x2::new(52127846272954880, 6823569169558272); - assert_eq!(r, transmute(lsx_vsllwil_wu_hu::<8>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vsllwil_wu_hu::<8>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3692,7 +4827,10 @@ unsafe fn test_lsx_vsllwil_du_wu() { let a = u32x4::new(3249798491, 4098547305, 1101510259, 3478509641); let r = i64x2::new(13630642809995264, 17190553355550720); - assert_eq!(r, transmute(lsx_vsllwil_du_wu::<22>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vsllwil_du_wu::<22>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3701,7 +4839,13 @@ unsafe fn test_lsx_vsran_b_h() { let b = i16x8::new(-12507, -16997, -17826, 5682, -298, -28572, -8117, -13478); let r = i64x2::new(-864943573596831881, 0); - assert_eq!(r, transmute(lsx_vsran_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsran_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3710,7 +4854,13 @@ unsafe fn test_lsx_vsran_h_w() { let b = i32x4::new(-52337348, -677553123, -58200260, -1473338606); let r = i64x2::new(1267763303694925820, 0); - assert_eq!(r, transmute(lsx_vsran_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsran_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3719,7 +4869,13 @@ unsafe fn test_lsx_vsran_w_d() { let b = i64x2::new(-8585295495893484131, -2657141976436452013); let r = i64x2::new(-5882350952887806270, 0); - assert_eq!(r, transmute(lsx_vsran_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsran_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3728,7 +4884,13 @@ unsafe fn test_lsx_vssran_b_h() { let b = i16x8::new(9459, 15241, 22170, 28027, 5348, 14784, 22613, -9469); let r = i64x2::new(9187483431610086528, 0); - assert_eq!(r, transmute(lsx_vssran_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssran_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3737,7 +4899,13 @@ unsafe fn test_lsx_vssran_h_w() { let b = i32x4::new(2070726003, -944816867, -160621862, -1222036466); let r = i64x2::new(-5219109151313101350, 0); - assert_eq!(r, transmute(lsx_vssran_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssran_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3746,7 +4914,13 @@ unsafe fn test_lsx_vssran_w_d() { let b = i64x2::new(-7078666005882550400, -2564990402652718339); let r = i64x2::new(-15032385536, 0); - assert_eq!(r, transmute(lsx_vssran_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssran_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3755,7 +4929,13 @@ unsafe fn test_lsx_vssran_bu_h() { let b = u16x8::new(2372, 26267, 4722, 47876, 44857, 55242, 45998, 51450); let r = i64x2::new(47227865344, 0); - assert_eq!(r, transmute(lsx_vssran_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssran_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3764,7 +4944,13 @@ unsafe fn test_lsx_vssran_hu_w() { let b = u32x4::new(2085279153, 2679576985, 2935643238, 3797496208); let r = i64x2::new(281470684234479, 0); - assert_eq!(r, transmute(lsx_vssran_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssran_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3773,7 +4959,13 @@ unsafe fn test_lsx_vssran_wu_d() { let b = u64x2::new(3904652404244024971, 4230656884168675704); let r = i64x2::new(536870912000, 0); - assert_eq!(r, transmute(lsx_vssran_wu_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssran_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3782,7 +4974,13 @@ unsafe fn test_lsx_vsrarn_b_h() { let b = i16x8::new(-19071, -903, 11542, -25909, 24111, 14882, -27192, -8283); let r = i64x2::new(7076043428318610384, 0); - assert_eq!(r, transmute(lsx_vsrarn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrarn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3791,7 +4989,13 @@ unsafe fn test_lsx_vsrarn_h_w() { let b = i32x4::new(-1571698573, 1467958613, -1857488008, 424713310); let r = i64x2::new(498163119212, 0); - assert_eq!(r, transmute(lsx_vsrarn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrarn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3800,7 +5004,13 @@ unsafe fn test_lsx_vsrarn_w_d() { let b = i64x2::new(-8645668865455529235, -3129277582817496880); let r = i64x2::new(-8628090759335017621, 0); - assert_eq!(r, transmute(lsx_vsrarn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrarn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3809,7 +5019,13 @@ unsafe fn test_lsx_vssrarn_b_h() { let b = i16x8::new(24298, 2343, 24641, 20910, 3142, -1171, 25850, 15932); let r = i64x2::new(-148338468081139694, 0); - assert_eq!(r, transmute(lsx_vssrarn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrarn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3818,7 +5034,13 @@ unsafe fn test_lsx_vssrarn_h_w() { let b = i32x4::new(1911424854, -931292983, -1710824608, -1179580317); let r = i64x2::new(-9223231301513904204, 0); - assert_eq!(r, transmute(lsx_vssrarn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrarn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3827,7 +5049,13 @@ unsafe fn test_lsx_vssrarn_w_d() { let b = i64x2::new(2843689038926761304, -6830262024912907383); let r = i64x2::new(-9223372034707292161, 0); - assert_eq!(r, transmute(lsx_vssrarn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrarn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3836,7 +5064,13 @@ unsafe fn test_lsx_vssrarn_bu_h() { let b = u16x8::new(60210, 40155, 14296, 25577, 1550, 1674, 5330, 10645); let r = i64x2::new(10999415373897, 0); - assert_eq!(r, transmute(lsx_vssrarn_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrarn_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3845,7 +5079,13 @@ unsafe fn test_lsx_vssrarn_hu_w() { let b = u32x4::new(3570029841, 3229468238, 1070101998, 3159433736); let r = i64x2::new(281474976645120, 0); - assert_eq!(r, transmute(lsx_vssrarn_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrarn_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3854,7 +5094,13 @@ unsafe fn test_lsx_vssrarn_wu_d() { let b = u64x2::new(1112771813772164907, 646071836375127186); let r = i64x2::new(963446, 0); - assert_eq!(r, transmute(lsx_vssrarn_wu_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrarn_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3863,7 +5109,13 @@ unsafe fn test_lsx_vsrln_b_h() { let b = i16x8::new(-11667, 13077, -23656, 5150, -23771, -31329, 20729, 15169); let r = i64x2::new(23363148983015937, 0); - assert_eq!(r, transmute(lsx_vsrln_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrln_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3872,7 +5124,13 @@ unsafe fn test_lsx_vsrln_h_w() { let b = i32x4::new(1775989751, -1602688801, -801213995, -1801759515); let r = i64x2::new(-7033214568759295968, 0); - assert_eq!(r, transmute(lsx_vsrln_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrln_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3881,7 +5139,13 @@ unsafe fn test_lsx_vsrln_w_d() { let b = i64x2::new(-1428152872702150626, 3907864416256094744); let r = i64x2::new(-8718771486483115547, 0); - assert_eq!(r, transmute(lsx_vsrln_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrln_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3890,7 +5154,13 @@ unsafe fn test_lsx_vssrln_bu_h() { let b = u16x8::new(41072, 41125, 44619, 49581, 20733, 905, 47558, 7801); let r = i64x2::new(8862857593125412863, 0); - assert_eq!(r, transmute(lsx_vssrln_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrln_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3899,7 +5169,13 @@ unsafe fn test_lsx_vssrln_hu_w() { let b = u32x4::new(1325069171, 1380839173, 3495604120, 2839043866); let r = i64x2::new(16889194387279379, 0); - assert_eq!(r, transmute(lsx_vssrln_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrln_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3908,7 +5184,13 @@ unsafe fn test_lsx_vssrln_wu_d() { let b = u64x2::new(3908262745817581251, 17131627096934512209); let r = i64x2::new(-1, 0); - assert_eq!(r, transmute(lsx_vssrln_wu_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrln_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3917,7 +5199,13 @@ unsafe fn test_lsx_vsrlrn_b_h() { let b = i16x8::new(22830, -27866, -24616, -9547, 11336, 320, 19908, 7056); let r = i64x2::new(-4888418841542521598, 0); - assert_eq!(r, transmute(lsx_vsrlrn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrlrn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3926,7 +5214,13 @@ unsafe fn test_lsx_vsrlrn_h_w() { let b = i32x4::new(1387862348, 119424523, 185407104, 1890720739); let r = i64x2::new(2222313691660711041, 0); - assert_eq!(r, transmute(lsx_vsrlrn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrlrn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3935,7 +5229,13 @@ unsafe fn test_lsx_vsrlrn_w_d() { let b = i64x2::new(-8550351213501194562, 7071641301481388656); let r = i64x2::new(182866822561795, 0); - assert_eq!(r, transmute(lsx_vsrlrn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrlrn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3944,7 +5244,13 @@ unsafe fn test_lsx_vssrlrn_bu_h() { let b = u16x8::new(51122, 39148, 45511, 57479, 62603, 43668, 5537, 61004); let r = i64x2::new(432344477600776959, 0); - assert_eq!(r, transmute(lsx_vssrlrn_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrlrn_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3953,7 +5259,13 @@ unsafe fn test_lsx_vssrlrn_hu_w() { let b = u32x4::new(1618795892, 3678356443, 862445734, 2115250342); let r = i64x2::new(-4293983341, 0); - assert_eq!(r, transmute(lsx_vssrlrn_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrlrn_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3962,7 +5274,13 @@ unsafe fn test_lsx_vssrlrn_wu_d() { let b = u64x2::new(13406765083608623828, 7214649593148131096); let r = i64x2::new(-1, 0); - assert_eq!(r, transmute(lsx_vssrlrn_wu_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrlrn_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3977,7 +5295,10 @@ unsafe fn test_lsx_vfrstpi_b() { assert_eq!( r, - transmute(lsx_vfrstpi_b::<28>(transmute(a), transmute(b))) + transmute(lsx_vfrstpi_b::<28>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -3987,7 +5308,13 @@ unsafe fn test_lsx_vfrstpi_h() { let b = i16x8::new(9590, -8044, 15088, 4172, 1721, 27581, -19895, -25679); let r = i64x2::new(-4160352588467724069, 5959935604366651239); - assert_eq!(r, transmute(lsx_vfrstpi_h::<1>(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfrstpi_h::<1>( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4005,7 +5332,11 @@ unsafe fn test_lsx_vfrstp_b() { assert_eq!( r, - transmute(lsx_vfrstp_b(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfrstp_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4018,7 +5349,11 @@ unsafe fn test_lsx_vfrstp_h() { assert_eq!( r, - transmute(lsx_vfrstp_h(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfrstp_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4030,7 +5365,10 @@ unsafe fn test_lsx_vshuf4i_d() { assert_eq!( r, - transmute(lsx_vshuf4i_d::<153>(transmute(a), transmute(b))) + transmute(lsx_vshuf4i_d::<153>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -4041,7 +5379,7 @@ unsafe fn test_lsx_vbsrl_v() { ); let r = i64x2::new(4570595419764160432, 56); - assert_eq!(r, transmute(lsx_vbsrl_v::<7>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbsrl_v::<7>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4051,7 +5389,7 @@ unsafe fn test_lsx_vbsll_v() { ); let r = i64x2::new(0, -1801439850948198400); - assert_eq!(r, transmute(lsx_vbsll_v::<15>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbsll_v::<15>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4066,7 +5404,10 @@ unsafe fn test_lsx_vextrins_b() { assert_eq!( r, - transmute(lsx_vextrins_b::<21>(transmute(a), transmute(b))) + transmute(lsx_vextrins_b::<21>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -4078,7 +5419,10 @@ unsafe fn test_lsx_vextrins_h() { assert_eq!( r, - transmute(lsx_vextrins_h::<33>(transmute(a), transmute(b))) + transmute(lsx_vextrins_h::<33>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -4090,7 +5434,10 @@ unsafe fn test_lsx_vextrins_w() { assert_eq!( r, - transmute(lsx_vextrins_w::<57>(transmute(a), transmute(b))) + transmute(lsx_vextrins_w::<57>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -4102,7 +5449,10 @@ unsafe fn test_lsx_vextrins_d() { assert_eq!( r, - transmute(lsx_vextrins_d::<62>(transmute(a), transmute(b))) + transmute(lsx_vextrins_d::<62>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -4113,7 +5463,7 @@ unsafe fn test_lsx_vmskltz_b() { ); let r = i64x2::new(40038, 0); - assert_eq!(r, transmute(lsx_vmskltz_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vmskltz_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4121,7 +5471,7 @@ unsafe fn test_lsx_vmskltz_h() { let a = i16x8::new(16730, 29121, -23447, -8647, -22303, 21817, 30964, -27069); let r = i64x2::new(156, 0); - assert_eq!(r, transmute(lsx_vmskltz_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vmskltz_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4129,7 +5479,7 @@ unsafe fn test_lsx_vmskltz_w() { let a = i32x4::new(-657282776, -1247210048, 162595942, 949871015); let r = i64x2::new(3, 0); - assert_eq!(r, transmute(lsx_vmskltz_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vmskltz_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4137,7 +5487,7 @@ unsafe fn test_lsx_vmskltz_d() { let a = i64x2::new(7728638770319849738, 4250984610820351699); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vmskltz_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vmskltz_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4150,7 +5500,13 @@ unsafe fn test_lsx_vsigncov_b() { ); let r = i64x2::new(-9074694153930972472, 1986788453588057010); - assert_eq!(r, transmute(lsx_vsigncov_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsigncov_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4159,7 +5515,13 @@ unsafe fn test_lsx_vsigncov_h() { let b = i16x8::new(27367, 4727, -2962, 14937, 26207, -19075, -26630, 10708); let r = i64x2::new(-4204122973533661927, -3013866947575178847); - assert_eq!(r, transmute(lsx_vsigncov_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsigncov_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4168,7 +5530,13 @@ unsafe fn test_lsx_vsigncov_w() { let b = i32x4::new(-1719915889, 290419288, 202835952, -1715336967); let r = i64x2::new(-1247341342367689359, -7367316170792699888); - assert_eq!(r, transmute(lsx_vsigncov_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsigncov_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4177,7 +5545,13 @@ unsafe fn test_lsx_vsigncov_d() { let b = i64x2::new(-7146260093067324952, -4263419240070336957); let r = i64x2::new(-7146260093067324952, 4263419240070336957); - assert_eq!(r, transmute(lsx_vsigncov_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsigncov_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4189,7 +5563,11 @@ unsafe fn test_lsx_vfmadd_s() { assert_eq!( r, - transmute(lsx_vfmadd_s(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfmadd_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4202,7 +5580,11 @@ unsafe fn test_lsx_vfmadd_d() { assert_eq!( r, - transmute(lsx_vfmadd_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfmadd_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4215,7 +5597,11 @@ unsafe fn test_lsx_vfmsub_s() { assert_eq!( r, - transmute(lsx_vfmsub_s(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfmsub_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4228,7 +5614,11 @@ unsafe fn test_lsx_vfmsub_d() { assert_eq!( r, - transmute(lsx_vfmsub_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfmsub_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4241,7 +5631,11 @@ unsafe fn test_lsx_vfnmadd_s() { assert_eq!( r, - transmute(lsx_vfnmadd_s(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfnmadd_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4254,7 +5648,11 @@ unsafe fn test_lsx_vfnmadd_d() { assert_eq!( r, - transmute(lsx_vfnmadd_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfnmadd_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4267,7 +5665,11 @@ unsafe fn test_lsx_vfnmsub_s() { assert_eq!( r, - transmute(lsx_vfnmsub_s(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfnmsub_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4280,7 +5682,11 @@ unsafe fn test_lsx_vfnmsub_d() { assert_eq!( r, - transmute(lsx_vfnmsub_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfnmsub_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4289,7 +5695,7 @@ unsafe fn test_lsx_vftintrne_w_s() { let a = u32x4::new(1031214064, 1059673230, 1042813024, 1053602874); let r = i64x2::new(4294967296, 0); - assert_eq!(r, transmute(lsx_vftintrne_w_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrne_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4297,7 +5703,7 @@ unsafe fn test_lsx_vftintrne_l_d() { let a = u64x2::new(4606989588359571497, 4604713245380178790); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vftintrne_l_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrne_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4305,7 +5711,7 @@ unsafe fn test_lsx_vftintrp_w_s() { let a = u32x4::new(1061716225, 1050491008, 1064711040, 1065018777); let r = i64x2::new(4294967297, 4294967297); - assert_eq!(r, transmute(lsx_vftintrp_w_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrp_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4313,7 +5719,7 @@ unsafe fn test_lsx_vftintrp_l_d() { let a = u64x2::new(4587516915944025472, 4601504548481216392); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vftintrp_l_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrp_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4321,7 +5727,7 @@ unsafe fn test_lsx_vftintrm_w_s() { let a = u32x4::new(1045772456, 1065200707, 1061587478, 1035467272); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrm_w_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrm_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4329,7 +5735,7 @@ unsafe fn test_lsx_vftintrm_l_d() { let a = u64x2::new(4597123259408216804, 4594399417822716772); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrm_l_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrm_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4338,7 +5744,13 @@ unsafe fn test_lsx_vftint_w_d() { let b = u64x2::new(4606905060326467647, 4606985586417166381); let r = i64x2::new(4294967297, 0); - assert_eq!(r, transmute(lsx_vftint_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vftint_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4347,7 +5759,13 @@ unsafe fn test_lsx_vffint_s_l() { let b = i64x2::new(5814449889729512723, -111756032377486319); let r = i64x2::new(-2610252963668467161, 6669016150524087533); - assert_eq!(r, transmute(lsx_vffint_s_l(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vffint_s_l( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4356,7 +5774,13 @@ unsafe fn test_lsx_vftintrz_w_d() { let b = u64x2::new(4599106720144900270, 4600531579473237336); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrz_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vftintrz_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4365,7 +5789,13 @@ unsafe fn test_lsx_vftintrp_w_d() { let b = u64x2::new(4606104970322966899, 4595679410565085836); let r = i64x2::new(4294967297, 4294967297); - assert_eq!(r, transmute(lsx_vftintrp_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vftintrp_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4374,7 +5804,13 @@ unsafe fn test_lsx_vftintrm_w_d() { let b = u64x2::new(4606733822200032543, 4589510164179968984); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrm_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vftintrm_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4383,7 +5819,13 @@ unsafe fn test_lsx_vftintrne_w_d() { let b = u64x2::new(4599197176714081204, 4605745859931721980); let r = i64x2::new(4294967296, 0); - assert_eq!(r, transmute(lsx_vftintrne_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vftintrne_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4391,7 +5833,7 @@ unsafe fn test_lsx_vftintl_l_s() { let a = u32x4::new(1058856635, 1060563398, 1061422616, 1056124918); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vftintl_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintl_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4399,7 +5841,7 @@ unsafe fn test_lsx_vftinth_l_s() { let a = u32x4::new(1045383680, 1040752748, 1061879518, 1054801708); let r = i64x2::new(1, 0); - assert_eq!(r, transmute(lsx_vftinth_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftinth_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4407,7 +5849,7 @@ unsafe fn test_lsx_vffinth_d_w() { let a = i32x4::new(517100418, -188510766, 949226647, -87467194); let r = i64x2::new(4741245898611228672, -4497729803343888384); - assert_eq!(r, transmute(lsx_vffinth_d_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vffinth_d_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4415,7 +5857,7 @@ unsafe fn test_lsx_vffintl_d_w() { let a = i32x4::new(1273684401, -2137528906, -2109294912, -1646387998); let r = i64x2::new(4743129027571613696, -4476619782820462592); - assert_eq!(r, transmute(lsx_vffintl_d_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vffintl_d_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4423,7 +5865,7 @@ unsafe fn test_lsx_vftintrzl_l_s() { let a = u32x4::new(1031186688, 987838976, 1034565688, 1061017371); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrzl_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrzl_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4431,7 +5873,7 @@ unsafe fn test_lsx_vftintrzh_l_s() { let a = u32x4::new(1049433828, 1048953580, 1060964637, 1059899586); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrzh_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrzh_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4439,7 +5881,7 @@ unsafe fn test_lsx_vftintrpl_l_s() { let a = u32x4::new(1061834803, 1064858941, 1060475110, 1063896216); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vftintrpl_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrpl_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4447,7 +5889,7 @@ unsafe fn test_lsx_vftintrph_l_s() { let a = u32x4::new(1059691939, 1065187151, 1059017027, 1061117394); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vftintrph_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrph_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4455,7 +5897,7 @@ unsafe fn test_lsx_vftintrml_l_s() { let a = u32x4::new(1062985651, 1065211455, 1056421466, 1057373572); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrml_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrml_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4463,7 +5905,7 @@ unsafe fn test_lsx_vftintrmh_l_s() { let a = u32x4::new(1050224290, 1063763666, 1057677270, 1063622234); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrmh_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrmh_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4471,7 +5913,7 @@ unsafe fn test_lsx_vftintrnel_l_s() { let a = u32x4::new(1060174609, 1050974638, 1047193308, 1062040876); let r = i64x2::new(1, 0); - assert_eq!(r, transmute(lsx_vftintrnel_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrnel_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4479,7 +5921,7 @@ unsafe fn test_lsx_vftintrneh_l_s() { let a = u32x4::new(1055675382, 1036879184, 1064176794, 1063791852); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vftintrneh_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrneh_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4487,7 +5929,7 @@ unsafe fn test_lsx_vfrintrne_s() { let a = u32x4::new(1054667842, 1061395025, 1062986478, 1062529334); let r = i64x2::new(4575657221408423936, 4575657222473777152); - assert_eq!(r, transmute(lsx_vfrintrne_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrne_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4495,7 +5937,7 @@ unsafe fn test_lsx_vfrintrne_d() { let a = u64x2::new(4603260356641870565, 4601614335120512898); let r = i64x2::new(4607182418800017408, 0); - assert_eq!(r, transmute(lsx_vfrintrne_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrne_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4503,7 +5945,7 @@ unsafe fn test_lsx_vfrintrz_s() { let a = u32x4::new(1063039577, 1033416832, 1052369306, 1057885024); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfrintrz_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrz_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4511,7 +5953,7 @@ unsafe fn test_lsx_vfrintrz_d() { let a = u64x2::new(4601515428088814484, 4604735152905786794); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfrintrz_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrz_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4519,7 +5961,7 @@ unsafe fn test_lsx_vfrintrp_s() { let a = u32x4::new(1061968959, 1056597596, 1064869916, 1058742360); let r = i64x2::new(4575657222473777152, 4575657222473777152); - assert_eq!(r, transmute(lsx_vfrintrp_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrp_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4527,7 +5969,7 @@ unsafe fn test_lsx_vfrintrp_d() { let a = u64x2::new(4603531792479663401, 4587997630530425392); let r = i64x2::new(4607182418800017408, 4607182418800017408); - assert_eq!(r, transmute(lsx_vfrintrp_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrp_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4535,7 +5977,7 @@ unsafe fn test_lsx_vfrintrm_s() { let a = u32x4::new(1058024441, 1044087184, 1059777964, 1050835426); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfrintrm_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrm_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4543,7 +5985,7 @@ unsafe fn test_lsx_vfrintrm_d() { let a = u64x2::new(4589388034824743512, 4606800774570289382); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfrintrm_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrm_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4556,7 +5998,7 @@ unsafe fn test_lsx_vstelm_b() { ]; let r = i64x2::new(2624488095427530938, -2742340989646681128); - lsx_vstelm_b::<0, 0>(transmute(a), o.as_mut_ptr()); + lsx_vstelm_b::<0, 0>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -4568,7 +6010,7 @@ unsafe fn test_lsx_vstelm_h() { ]; let r = i64x2::new(-5777879910580360821, -8010388107109560809); - lsx_vstelm_h::<0, 1>(transmute(a), o.as_mut_ptr()); + lsx_vstelm_h::<0, 1>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -4580,7 +6022,7 @@ unsafe fn test_lsx_vstelm_w() { ]; let r = i64x2::new(-7107014201697162202, -4954294907532227136); - lsx_vstelm_w::<0, 3>(transmute(a), o.as_mut_ptr()); + lsx_vstelm_w::<0, 3>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -4592,7 +6034,7 @@ unsafe fn test_lsx_vstelm_d() { ]; let r = i64x2::new(2628828971609511929, -1577551211298588582); - lsx_vstelm_d::<0, 0>(transmute(a), o.as_mut_ptr()); + lsx_vstelm_d::<0, 0>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -4602,7 +6044,13 @@ unsafe fn test_lsx_vaddwev_d_w() { let b = i32x4::new(-2105551735, -1478351177, 1027048582, -607110700); let r = i64x2::new(-3995454036, 2115628395); - assert_eq!(r, transmute(lsx_vaddwev_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4611,7 +6059,13 @@ unsafe fn test_lsx_vaddwev_w_h() { let b = i16x8::new(-17479, -32614, 24343, 25426, -14077, -12419, 10115, 23013); let r = i64x2::new(57531086920254, -11304353922851); - assert_eq!(r, transmute(lsx_vaddwev_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4624,7 +6078,13 @@ unsafe fn test_lsx_vaddwev_h_b() { ); let r = i64x2::new(-6191796646052051, 32369798417022969); - assert_eq!(r, transmute(lsx_vaddwev_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4633,7 +6093,13 @@ unsafe fn test_lsx_vaddwod_d_w() { let b = i32x4::new(420515981, 473447119, 1471756335, 1044924117); let r = i64x2::new(126219465, 3020814787); - assert_eq!(r, transmute(lsx_vaddwod_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4642,7 +6108,13 @@ unsafe fn test_lsx_vaddwod_w_h() { let b = i16x8::new(-26581, -22301, 18214, -3616, -24489, 12150, -10765, -24232); let r = i64x2::new(-151719719748481, -112154480997307); - assert_eq!(r, transmute(lsx_vaddwod_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4655,7 +6127,13 @@ unsafe fn test_lsx_vaddwod_h_b() { ); let r = i64x2::new(-18014780768845678, 14636475441676413); - assert_eq!(r, transmute(lsx_vaddwod_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4664,7 +6142,13 @@ unsafe fn test_lsx_vaddwev_d_wu() { let b = u32x4::new(1482213353, 1001198416, 3345983326, 2244256337); let r = i64x2::new(4022160583, 4539965521); - assert_eq!(r, transmute(lsx_vaddwev_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4673,7 +6157,13 @@ unsafe fn test_lsx_vaddwev_w_hu() { let b = u16x8::new(28483, 24704, 9817, 62062, 47674, 8032, 29897, 62737); let r = i64x2::new(176725019407839, 226649719257774); - assert_eq!(r, transmute(lsx_vaddwev_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4686,7 +6176,13 @@ unsafe fn test_lsx_vaddwev_h_bu() { ); let r = i64x2::new(85006057160704351, 47850943627526421); - assert_eq!(r, transmute(lsx_vaddwev_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4695,7 +6191,13 @@ unsafe fn test_lsx_vaddwod_d_wu() { let b = u32x4::new(2782520439, 2496077290, 2678772394, 196273109); let r = i64x2::new(4147231270, 2289089430); - assert_eq!(r, transmute(lsx_vaddwod_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4704,7 +6206,13 @@ unsafe fn test_lsx_vaddwod_w_hu() { let b = u16x8::new(20353, 34039, 21222, 4948, 58293, 4766, 51360, 37497); let r = i64x2::new(82519206727777, 206875689791292); - assert_eq!(r, transmute(lsx_vaddwod_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4717,7 +6225,13 @@ unsafe fn test_lsx_vaddwod_h_bu() { ); let r = i64x2::new(73466429242409013, 32932877227196635); - assert_eq!(r, transmute(lsx_vaddwod_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4726,7 +6240,13 @@ unsafe fn test_lsx_vaddwev_d_wu_w() { let b = i32x4::new(-1308530150, 1427930358, 1723198474, 1987356336); let r = i64x2::new(2478528121, 3014708115); - assert_eq!(r, transmute(lsx_vaddwev_d_wu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4735,7 +6255,13 @@ unsafe fn test_lsx_vaddwev_w_hu_h() { let b = i16x8::new(-11621, -6593, 7431, -1189, -12361, -15174, 16182, -32434); let r = i64x2::new(64158221463769, 194716637325930); - assert_eq!(r, transmute(lsx_vaddwev_w_hu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4748,7 +6274,13 @@ unsafe fn test_lsx_vaddwev_h_bu_b() { ); let r = i64x2::new(71776235037065355, -7880749580746636); - assert_eq!(r, transmute(lsx_vaddwev_h_bu_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4757,7 +6289,13 @@ unsafe fn test_lsx_vaddwod_d_wu_w() { let b = i32x4::new(-1646368557, 586112311, 376247963, 1048800083); let r = i64x2::new(3497092601, 3306080422); - assert_eq!(r, transmute(lsx_vaddwod_d_wu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4766,7 +6304,13 @@ unsafe fn test_lsx_vaddwod_w_hu_h() { let b = i16x8::new(31700, 22725, 14068, -14860, -28839, -14513, -1195, 27082); let r = i64x2::new(-10273561712908, 369560461022726); - assert_eq!(r, transmute(lsx_vaddwod_w_hu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4779,7 +6323,13 @@ unsafe fn test_lsx_vaddwod_h_bu_b() { ); let r = i64x2::new(49259327819481212, 19140654913421439); - assert_eq!(r, transmute(lsx_vaddwod_h_bu_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4788,7 +6338,13 @@ unsafe fn test_lsx_vsubwev_d_w() { let b = i32x4::new(-2090701374, 629564229, -1170676885, 1069800209); let r = i64x2::new(4070621277, 63900397); - assert_eq!(r, transmute(lsx_vsubwev_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4797,7 +6353,13 @@ unsafe fn test_lsx_vsubwev_w_h() { let b = i16x8::new(-23957, 9416, -29569, -13210, 5333, 8420, 18648, -24201); let r = i64x2::new(228187317494294, -105188044063209); - assert_eq!(r, transmute(lsx_vsubwev_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4810,7 +6372,13 @@ unsafe fn test_lsx_vsubwev_h_b() { ); let r = i64x2::new(-41939247539617653, -14355228098887689); - assert_eq!(r, transmute(lsx_vsubwev_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4819,7 +6387,13 @@ unsafe fn test_lsx_vsubwod_d_w() { let b = i32x4::new(1436617964, -45524609, 502994793, -2039550077); let r = i64x2::new(-1037882987, 3497647797); - assert_eq!(r, transmute(lsx_vsubwod_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4828,7 +6402,13 @@ unsafe fn test_lsx_vsubwod_w_h() { let b = i16x8::new(-1276, 12669, 24115, 19617, -26739, 1910, -757, 23994); let r = i64x2::new(-158286724709540, -182411556002309); - assert_eq!(r, transmute(lsx_vsubwod_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4841,7 +6421,13 @@ unsafe fn test_lsx_vsubwod_h_b() { ); let r = i64x2::new(23925540523802608, 562958549909362); - assert_eq!(r, transmute(lsx_vsubwod_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4850,7 +6436,13 @@ unsafe fn test_lsx_vsubwev_d_wu() { let b = u32x4::new(1691253880, 1939268473, 1629937431, 2921768539); let r = i64x2::new(974418830, 1402878171); - assert_eq!(r, transmute(lsx_vsubwev_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4859,7 +6451,13 @@ unsafe fn test_lsx_vsubwev_w_hu() { let b = u16x8::new(15957, 42770, 43138, 30319, 50823, 18089, 64120, 18054); let r = i64x2::new(-41807211666923, -194858371266981); - assert_eq!(r, transmute(lsx_vsubwev_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4872,7 +6470,13 @@ unsafe fn test_lsx_vsubwev_h_bu() { ); let r = i64x2::new(-1407181617889293, 47851128289689387); - assert_eq!(r, transmute(lsx_vsubwev_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4881,7 +6485,13 @@ unsafe fn test_lsx_vsubwod_d_wu() { let b = u32x4::new(103354715, 19070238, 1662532733, 3761231766); let r = i64x2::new(3487028338, -1512426824); - assert_eq!(r, transmute(lsx_vsubwod_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4890,7 +6500,13 @@ unsafe fn test_lsx_vsubwod_w_hu() { let b = u16x8::new(21739, 45406, 21733, 63910, 6659, 16020, 1211, 637); let r = i64x2::new(-93999654264447, 232211701825972); - assert_eq!(r, transmute(lsx_vsubwod_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4903,7 +6519,13 @@ unsafe fn test_lsx_vsubwod_h_bu() { ); let r = i64x2::new(-14355150803107815, 14636020195655765); - assert_eq!(r, transmute(lsx_vsubwod_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4912,7 +6534,13 @@ unsafe fn test_lsx_vaddwev_q_d() { let b = i64x2::new(6738886902337351868, -5985538541381931477); let r = i64x2::new(5606769623790009521, 0); - assert_eq!(r, transmute(lsx_vaddwev_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4921,7 +6549,13 @@ unsafe fn test_lsx_vaddwod_q_d() { let b = i64x2::new(-1244049724346527963, -3275029038845457041); let r = i64x2::new(-4417812606654001824, -1); - assert_eq!(r, transmute(lsx_vaddwod_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4930,7 +6564,13 @@ unsafe fn test_lsx_vaddwev_q_du() { let b = u64x2::new(6745766838534849346, 15041258018068294402); let r = i64x2::new(5074243625310689089, 1); - assert_eq!(r, transmute(lsx_vaddwev_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4939,7 +6579,13 @@ unsafe fn test_lsx_vaddwod_q_du() { let b = u64x2::new(13496765248439164553, 4640846570780442359); let r = i64x2::new(-2107214925415534967, 0); - assert_eq!(r, transmute(lsx_vaddwod_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4948,7 +6594,13 @@ unsafe fn test_lsx_vsubwev_q_d() { let b = i64x2::new(8029026411722387723, -2105201823388787841); let r = i64x2::new(480269655671735476, 0); - assert_eq!(r, transmute(lsx_vsubwev_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4957,7 +6609,13 @@ unsafe fn test_lsx_vsubwod_q_d() { let b = i64x2::new(5758437127240728961, 2933507971643343184); let r = i64x2::new(-8752278892998837291, -1); - assert_eq!(r, transmute(lsx_vsubwod_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4966,7 +6624,13 @@ unsafe fn test_lsx_vsubwev_q_du() { let b = u64x2::new(1574118313456291324, 7787456577305510529); let r = i64x2::new(-4672772323591679948, 0); - assert_eq!(r, transmute(lsx_vsubwev_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4975,7 +6639,13 @@ unsafe fn test_lsx_vsubwod_q_du() { let b = u64x2::new(5627376085113520030, 12775637764770549815); let r = i64x2::new(6257163948134922640, -1); - assert_eq!(r, transmute(lsx_vsubwod_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4984,7 +6654,13 @@ unsafe fn test_lsx_vaddwev_q_du_d() { let b = i64x2::new(-1159499132550683978, -4257322329662100669); let r = i64x2::new(-8502520416635627524, 0); - assert_eq!(r, transmute(lsx_vaddwev_q_du_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4993,7 +6669,13 @@ unsafe fn test_lsx_vaddwod_q_du_d() { let b = i64x2::new(-3902573037873546881, 160140233311333524); let r = i64x2::new(286209858134078253, 0); - assert_eq!(r, transmute(lsx_vaddwod_q_du_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5002,7 +6684,13 @@ unsafe fn test_lsx_vmulwev_d_w() { let b = i32x4::new(8741677, -276509855, -1214560052, -1338519080); let r = i64x2::new(11251431313755612, -2205748716678689436); - assert_eq!(r, transmute(lsx_vmulwev_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5011,7 +6699,13 @@ unsafe fn test_lsx_vmulwev_w_h() { let b = i16x8::new(30661, -20472, 1422, -16868, 4256, 9713, -27765, -7287); let r = i64x2::new(-178740441125036345, 469367082934888736); - assert_eq!(r, transmute(lsx_vmulwev_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5024,7 +6718,13 @@ unsafe fn test_lsx_vmulwev_h_b() { ); let r = i64x2::new(38855607073696482, 823864071118590255); - assert_eq!(r, transmute(lsx_vmulwev_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5033,7 +6733,13 @@ unsafe fn test_lsx_vmulwod_d_w() { let b = i32x4::new(63312847, -1377579771, -2054819244, -1416520586); let r = i64x2::new(1549708311038418702, 2478205834807109862); - assert_eq!(r, transmute(lsx_vmulwod_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5042,7 +6748,13 @@ unsafe fn test_lsx_vmulwod_w_h() { let b = i16x8::new(23748, 11912, 4946, -23048, 22372, 24702, -24875, -27771); let r = i64x2::new(3222038736804363232, 360450672278114574); - assert_eq!(r, transmute(lsx_vmulwod_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5055,7 +6767,13 @@ unsafe fn test_lsx_vmulwod_h_b() { ); let r = i64x2::new(-351280556043402912, 951366355207905332); - assert_eq!(r, transmute(lsx_vmulwod_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5064,7 +6782,13 @@ unsafe fn test_lsx_vmulwev_d_wu() { let b = u32x4::new(1769900227, 2256955703, 2342391995, 2407560006); let r = i64x2::new(3651844205567962921, 7772247680216328210); - assert_eq!(r, transmute(lsx_vmulwev_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5073,7 +6797,13 @@ unsafe fn test_lsx_vmulwev_w_hu() { let b = u16x8::new(20499, 45056, 20580, 12771, 53914, 60742, 45402, 40547); let r = i64x2::new(4070644332601545987, 8033224333626513014); - assert_eq!(r, transmute(lsx_vmulwev_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5086,7 +6816,13 @@ unsafe fn test_lsx_vmulwev_h_bu() { ); let r = i64x2::new(271910110892810861, 1947809607093856504); - assert_eq!(r, transmute(lsx_vmulwev_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5095,7 +6831,13 @@ unsafe fn test_lsx_vmulwod_d_wu() { let b = u32x4::new(3750239707, 1422851626, 1277923597, 1377279439); let r = i64x2::new(2821622727533716246, 3005960862740149995); - assert_eq!(r, transmute(lsx_vmulwod_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5104,7 +6846,13 @@ unsafe fn test_lsx_vmulwod_w_hu() { let b = u16x8::new(38950, 5357, 36233, 17707, 61077, 61518, 5789, 13317); let r = i64x2::new(2460325445475503463, 3109522059894091248); - assert_eq!(r, transmute(lsx_vmulwod_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5117,7 +6865,13 @@ unsafe fn test_lsx_vmulwod_h_bu() { ); let r = i64x2::new(7364114643151226902, 6612146073643521312); - assert_eq!(r, transmute(lsx_vmulwod_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5126,7 +6880,13 @@ unsafe fn test_lsx_vmulwev_d_wu_w() { let b = i32x4::new(1254729285, 1938836163, -1902169358, -257980375); let r = i64x2::new(2295762833698990875, -6669027432954818262); - assert_eq!(r, transmute(lsx_vmulwev_d_wu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5135,7 +6895,13 @@ unsafe fn test_lsx_vmulwev_w_hu_h() { let b = i16x8::new(-30477, -10049, 16428, -30668, 21000, 24834, -3219, -9555); let r = i64x2::new(3369342936690107644, -701630285043265176); - assert_eq!(r, transmute(lsx_vmulwev_w_hu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5148,7 +6914,13 @@ unsafe fn test_lsx_vmulwev_h_bu_b() { ); let r = i64x2::new(-1134643098233554544, -1885853116779133038); - assert_eq!(r, transmute(lsx_vmulwev_h_bu_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5157,7 +6929,13 @@ unsafe fn test_lsx_vmulwod_d_wu_w() { let b = i32x4::new(1204047391, -1970001586, 608763444, -2082771896); let r = i64x2::new(-5967343163181744876, -3673352984882804288); - assert_eq!(r, transmute(lsx_vmulwod_d_wu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5166,7 +6944,13 @@ unsafe fn test_lsx_vmulwod_w_hu_h() { let b = i16x8::new(-3735, -12972, -4920, 7170, 11577, 9785, 4896, -537); let r = i64x2::new(1024392868267999948, -48053790042385565); - assert_eq!(r, transmute(lsx_vmulwod_w_hu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5179,7 +6963,13 @@ unsafe fn test_lsx_vmulwod_h_bu_b() { ); let r = i64x2::new(1905300476090387090, -3940634277386171400); - assert_eq!(r, transmute(lsx_vmulwod_h_bu_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5188,7 +6978,13 @@ unsafe fn test_lsx_vmulwev_q_d() { let b = i64x2::new(7023560313675997328, 4368639658790376608); let r = i64x2::new(-1409563343912029488, -2779799970834089134); - assert_eq!(r, transmute(lsx_vmulwev_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5197,7 +6993,13 @@ unsafe fn test_lsx_vmulwod_q_d() { let b = i64x2::new(1734538850547798281, 6505001633960390309); let r = i64x2::new(655114704133495137, -1013080750363369114); - assert_eq!(r, transmute(lsx_vmulwod_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5206,7 +7008,13 @@ unsafe fn test_lsx_vmulwev_q_du() { let b = u64x2::new(15048173707940873365, 13594773395779002998); let r = i64x2::new(-4049323972691826149, 6179334620527225413); - assert_eq!(r, transmute(lsx_vmulwev_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5215,7 +7023,13 @@ unsafe fn test_lsx_vmulwod_q_du() { let b = u64x2::new(16172423495582959833, 11676106279348566952); let r = i64x2::new(-66293137947075128, 3694303051148166412); - assert_eq!(r, transmute(lsx_vmulwod_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5224,7 +7038,13 @@ unsafe fn test_lsx_vmulwev_q_du_d() { let b = i64x2::new(-7071166739782294817, 8496829998090419991); let r = i64x2::new(5234431817964974175, -5931105679667820544); - assert_eq!(r, transmute(lsx_vmulwev_q_du_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5233,7 +7053,13 @@ unsafe fn test_lsx_vmulwod_q_du_d() { let b = i64x2::new(-9085162554263782091, -3351642387065053502); let r = i64x2::new(-3119502026085414102, -1153233394465180223); - assert_eq!(r, transmute(lsx_vmulwod_q_du_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5242,7 +7068,13 @@ unsafe fn test_lsx_vhaddw_q_d() { let b = i64x2::new(9222966760421493517, -8347454331188625422); let r = i64x2::new(6438946365641244151, 0); - assert_eq!(r, transmute(lsx_vhaddw_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5251,7 +7083,13 @@ unsafe fn test_lsx_vhaddw_qu_du() { let b = u64x2::new(2141387370256045519, 12417156199252644485); let r = i64x2::new(5083013417816990364, 0); - assert_eq!(r, transmute(lsx_vhaddw_qu_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_qu_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5260,7 +7098,13 @@ unsafe fn test_lsx_vhsubw_q_d() { let b = i64x2::new(-3245503809142406078, 8660213762027125085); let r = i64x2::new(817818278178354941, 0); - assert_eq!(r, transmute(lsx_vhsubw_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5269,7 +7113,13 @@ unsafe fn test_lsx_vhsubw_qu_du() { let b = u64x2::new(3098179646743711521, 11374525358855478565); let r = i64x2::new(-8990580109137044958, 0); - assert_eq!(r, transmute(lsx_vhsubw_qu_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_qu_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5281,7 +7131,11 @@ unsafe fn test_lsx_vmaddwev_d_w() { assert_eq!( r, - transmute(lsx_vmaddwev_d_w(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5294,7 +7148,11 @@ unsafe fn test_lsx_vmaddwev_w_h() { assert_eq!( r, - transmute(lsx_vmaddwev_w_h(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5311,7 +7169,11 @@ unsafe fn test_lsx_vmaddwev_h_b() { assert_eq!( r, - transmute(lsx_vmaddwev_h_b(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5324,7 +7186,11 @@ unsafe fn test_lsx_vmaddwev_d_wu() { assert_eq!( r, - transmute(lsx_vmaddwev_d_wu(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_d_wu( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5337,7 +7203,11 @@ unsafe fn test_lsx_vmaddwev_w_hu() { assert_eq!( r, - transmute(lsx_vmaddwev_w_hu(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_w_hu( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5354,7 +7224,11 @@ unsafe fn test_lsx_vmaddwev_h_bu() { assert_eq!( r, - transmute(lsx_vmaddwev_h_bu(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_h_bu( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5367,7 +7241,11 @@ unsafe fn test_lsx_vmaddwod_d_w() { assert_eq!( r, - transmute(lsx_vmaddwod_d_w(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5380,7 +7258,11 @@ unsafe fn test_lsx_vmaddwod_w_h() { assert_eq!( r, - transmute(lsx_vmaddwod_w_h(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5397,7 +7279,11 @@ unsafe fn test_lsx_vmaddwod_h_b() { assert_eq!( r, - transmute(lsx_vmaddwod_h_b(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5410,7 +7296,11 @@ unsafe fn test_lsx_vmaddwod_d_wu() { assert_eq!( r, - transmute(lsx_vmaddwod_d_wu(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_d_wu( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5423,7 +7313,11 @@ unsafe fn test_lsx_vmaddwod_w_hu() { assert_eq!( r, - transmute(lsx_vmaddwod_w_hu(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_w_hu( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5440,7 +7334,11 @@ unsafe fn test_lsx_vmaddwod_h_bu() { assert_eq!( r, - transmute(lsx_vmaddwod_h_bu(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_h_bu( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5454,9 +7352,9 @@ unsafe fn test_lsx_vmaddwev_d_wu_w() { assert_eq!( r, transmute(lsx_vmaddwev_d_wu_w( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5471,9 +7369,9 @@ unsafe fn test_lsx_vmaddwev_w_hu_h() { assert_eq!( r, transmute(lsx_vmaddwev_w_hu_h( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5492,9 +7390,9 @@ unsafe fn test_lsx_vmaddwev_h_bu_b() { assert_eq!( r, transmute(lsx_vmaddwev_h_bu_b( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5509,9 +7407,9 @@ unsafe fn test_lsx_vmaddwod_d_wu_w() { assert_eq!( r, transmute(lsx_vmaddwod_d_wu_w( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5526,9 +7424,9 @@ unsafe fn test_lsx_vmaddwod_w_hu_h() { assert_eq!( r, transmute(lsx_vmaddwod_w_hu_h( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5547,9 +7445,9 @@ unsafe fn test_lsx_vmaddwod_h_bu_b() { assert_eq!( r, transmute(lsx_vmaddwod_h_bu_b( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5563,7 +7461,11 @@ unsafe fn test_lsx_vmaddwev_q_d() { assert_eq!( r, - transmute(lsx_vmaddwev_q_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5576,7 +7478,11 @@ unsafe fn test_lsx_vmaddwod_q_d() { assert_eq!( r, - transmute(lsx_vmaddwod_q_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5589,7 +7495,11 @@ unsafe fn test_lsx_vmaddwev_q_du() { assert_eq!( r, - transmute(lsx_vmaddwev_q_du(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_q_du( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5602,7 +7512,11 @@ unsafe fn test_lsx_vmaddwod_q_du() { assert_eq!( r, - transmute(lsx_vmaddwod_q_du(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_q_du( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5616,9 +7530,9 @@ unsafe fn test_lsx_vmaddwev_q_du_d() { assert_eq!( r, transmute(lsx_vmaddwev_q_du_d( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5633,9 +7547,9 @@ unsafe fn test_lsx_vmaddwod_q_du_d() { assert_eq!( r, transmute(lsx_vmaddwod_q_du_d( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5650,7 +7564,13 @@ unsafe fn test_lsx_vrotr_b() { ); let r = i64x2::new(2841128540244802403, -8694309599374351908); - assert_eq!(r, transmute(lsx_vrotr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vrotr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5659,7 +7579,13 @@ unsafe fn test_lsx_vrotr_h() { let b = i16x8::new(-6485, 1418, 8263, -29872, -6491, 3930, -20621, 32531); let r = i64x2::new(2742461657407651598, 3308267577913279393); - assert_eq!(r, transmute(lsx_vrotr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vrotr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5668,7 +7594,13 @@ unsafe fn test_lsx_vrotr_w() { let b = i32x4::new(1956224189, -1858012941, -1889446514, -2130978943); let r = i64x2::new(6458469860191573231, -8548346292466177157); - assert_eq!(r, transmute(lsx_vrotr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vrotr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5677,7 +7609,13 @@ unsafe fn test_lsx_vrotr_d() { let b = i64x2::new(4553458262651691654, -5062393334123159235); let r = i64x2::new(-3594618648537251961, 7897385285240526033); - assert_eq!(r, transmute(lsx_vrotr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vrotr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5686,7 +7624,10 @@ unsafe fn test_lsx_vadd_q() { let b = i64x2::new(114135477458514099, 3481307531297359399); let r = i64x2::new(2537705118259771652, 4159381110985057604); - assert_eq!(r, transmute(lsx_vadd_q(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadd_q(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -5695,7 +7636,10 @@ unsafe fn test_lsx_vsub_q() { let b = i64x2::new(-8526086848853095438, -1323481969747305966); let r = i64x2::new(-2027679534337857341, -1789445478164204527); - assert_eq!(r, transmute(lsx_vsub_q(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsub_q(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -5745,7 +7689,7 @@ unsafe fn test_lsx_vmskgez_b() { ); let r = i64x2::new(24930, 0); - assert_eq!(r, transmute(lsx_vmskgez_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vmskgez_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5755,7 +7699,7 @@ unsafe fn test_lsx_vmsknz_b() { ); let r = i64x2::new(65535, 0); - assert_eq!(r, transmute(lsx_vmsknz_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vmsknz_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5765,7 +7709,7 @@ unsafe fn test_lsx_vexth_h_b() { ); let r = i64x2::new(-3377613816397739, 32088276197572514); - assert_eq!(r, transmute(lsx_vexth_h_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_h_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5773,7 +7717,7 @@ unsafe fn test_lsx_vexth_w_h() { let a = i16x8::new(14576, -26514, 14165, -15781, 10106, 1864, 23348, 30478); let r = i64x2::new(8005819049850, 130902013270836); - assert_eq!(r, transmute(lsx_vexth_w_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_w_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5781,7 +7725,7 @@ unsafe fn test_lsx_vexth_d_w() { let a = i32x4::new(863783254, 799653326, -1122161877, -652869192); let r = i64x2::new(-1122161877, -652869192); - assert_eq!(r, transmute(lsx_vexth_d_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_d_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5789,7 +7733,7 @@ unsafe fn test_lsx_vexth_q_d() { let a = i64x2::new(2924262436748867523, 1959694872821330818); let r = i64x2::new(1959694872821330818, 0); - assert_eq!(r, transmute(lsx_vexth_q_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_q_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5799,7 +7743,7 @@ unsafe fn test_lsx_vexth_hu_bu() { ); let r = i64x2::new(61080980486815914, 60235902725652628); - assert_eq!(r, transmute(lsx_vexth_hu_bu(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_hu_bu(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5807,7 +7751,7 @@ unsafe fn test_lsx_vexth_wu_hu() { let a = u16x8::new(58875, 18924, 17611, 30197, 33869, 53931, 4693, 53025); let r = i64x2::new(231631881274445, 227740640875093); - assert_eq!(r, transmute(lsx_vexth_wu_hu(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_wu_hu(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5815,7 +7759,7 @@ unsafe fn test_lsx_vexth_du_wu() { let a = u32x4::new(3499742961, 2840979237, 2082263829, 1096292547); let r = i64x2::new(2082263829, 1096292547); - assert_eq!(r, transmute(lsx_vexth_du_wu(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_du_wu(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5823,7 +7767,7 @@ unsafe fn test_lsx_vexth_qu_du() { let a = u64x2::new(14170556367894986991, 14238702840099699193); let r = i64x2::new(-4208041233609852423, 0); - assert_eq!(r, transmute(lsx_vexth_qu_du(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_qu_du(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5833,7 +7777,7 @@ unsafe fn test_lsx_vrotri_b() { ); let r = i64x2::new(-2919654548887155519, -96080239582005205); - assert_eq!(r, transmute(lsx_vrotri_b::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vrotri_b::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5841,7 +7785,7 @@ unsafe fn test_lsx_vrotri_h() { let a = i16x8::new(-14120, -16812, -19570, -990, 24476, -7640, 20329, 8879); let r = i64x2::new(-556925602567188047, 4998607264501841720); - assert_eq!(r, transmute(lsx_vrotri_h::<15>(transmute(a)))); + assert_eq!(r, transmute(lsx_vrotri_h::<15>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5849,7 +7793,7 @@ unsafe fn test_lsx_vrotri_w() { let a = i32x4::new(-1760224525, -1644621284, 1835781046, -1487934110); let r = i64x2::new(2845787365010917052, -6209343103231659283); - assert_eq!(r, transmute(lsx_vrotri_w::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vrotri_w::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5857,7 +7801,7 @@ unsafe fn test_lsx_vrotri_d() { let a = i64x2::new(8884634342417174882, 244175985366916345); let r = i64x2::new(-3963790888197019724, 4020656082573561910); - assert_eq!(r, transmute(lsx_vrotri_d::<52>(transmute(a)))); + assert_eq!(r, transmute(lsx_vrotri_d::<52>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5865,7 +7809,7 @@ unsafe fn test_lsx_vextl_q_d() { let a = i64x2::new(-5110246490938885255, 377414780188285171); let r = i64x2::new(-5110246490938885255, -1); - assert_eq!(r, transmute(lsx_vextl_q_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vextl_q_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5880,7 +7824,10 @@ unsafe fn test_lsx_vsrlni_b_h() { assert_eq!( r, - transmute(lsx_vsrlni_b_h::<14>(transmute(a), transmute(b))) + transmute(lsx_vsrlni_b_h::<14>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5892,7 +7839,10 @@ unsafe fn test_lsx_vsrlni_h_w() { assert_eq!( r, - transmute(lsx_vsrlni_h_w::<26>(transmute(a), transmute(b))) + transmute(lsx_vsrlni_h_w::<26>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5904,7 +7854,10 @@ unsafe fn test_lsx_vsrlni_w_d() { assert_eq!( r, - transmute(lsx_vsrlni_w_d::<18>(transmute(a), transmute(b))) + transmute(lsx_vsrlni_w_d::<18>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5916,7 +7869,10 @@ unsafe fn test_lsx_vsrlni_d_q() { assert_eq!( r, - transmute(lsx_vsrlni_d_q::<74>(transmute(a), transmute(b))) + transmute(lsx_vsrlni_d_q::<74>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5932,7 +7888,10 @@ unsafe fn test_lsx_vsrlrni_b_h() { assert_eq!( r, - transmute(lsx_vsrlrni_b_h::<6>(transmute(a), transmute(b))) + transmute(lsx_vsrlrni_b_h::<6>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5944,7 +7903,10 @@ unsafe fn test_lsx_vsrlrni_h_w() { assert_eq!( r, - transmute(lsx_vsrlrni_h_w::<6>(transmute(a), transmute(b))) + transmute(lsx_vsrlrni_h_w::<6>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5956,7 +7918,10 @@ unsafe fn test_lsx_vsrlrni_w_d() { assert_eq!( r, - transmute(lsx_vsrlrni_w_d::<52>(transmute(a), transmute(b))) + transmute(lsx_vsrlrni_w_d::<52>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5968,7 +7933,10 @@ unsafe fn test_lsx_vsrlrni_d_q() { assert_eq!( r, - transmute(lsx_vsrlrni_d_q::<101>(transmute(a), transmute(b))) + transmute(lsx_vsrlrni_d_q::<101>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5984,7 +7952,10 @@ unsafe fn test_lsx_vssrlni_b_h() { assert_eq!( r, - transmute(lsx_vssrlni_b_h::<13>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_b_h::<13>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5996,7 +7967,10 @@ unsafe fn test_lsx_vssrlni_h_w() { assert_eq!( r, - transmute(lsx_vssrlni_h_w::<23>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_h_w::<23>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6008,7 +7982,10 @@ unsafe fn test_lsx_vssrlni_w_d() { assert_eq!( r, - transmute(lsx_vssrlni_w_d::<12>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_w_d::<12>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6020,7 +7997,10 @@ unsafe fn test_lsx_vssrlni_d_q() { assert_eq!( r, - transmute(lsx_vssrlni_d_q::<88>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_d_q::<88>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6036,7 +8016,10 @@ unsafe fn test_lsx_vssrlni_bu_h() { assert_eq!( r, - transmute(lsx_vssrlni_bu_h::<13>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_bu_h::<13>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6048,7 +8031,10 @@ unsafe fn test_lsx_vssrlni_hu_w() { assert_eq!( r, - transmute(lsx_vssrlni_hu_w::<9>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_hu_w::<9>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6060,7 +8046,10 @@ unsafe fn test_lsx_vssrlni_wu_d() { assert_eq!( r, - transmute(lsx_vssrlni_wu_d::<59>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_wu_d::<59>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6072,7 +8061,10 @@ unsafe fn test_lsx_vssrlni_du_q() { assert_eq!( r, - transmute(lsx_vssrlni_du_q::<6>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_du_q::<6>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6088,7 +8080,10 @@ unsafe fn test_lsx_vssrlrni_b_h() { assert_eq!( r, - transmute(lsx_vssrlrni_b_h::<0>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_b_h::<0>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6100,7 +8095,10 @@ unsafe fn test_lsx_vssrlrni_h_w() { assert_eq!( r, - transmute(lsx_vssrlrni_h_w::<28>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_h_w::<28>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6112,7 +8110,10 @@ unsafe fn test_lsx_vssrlrni_w_d() { assert_eq!( r, - transmute(lsx_vssrlrni_w_d::<1>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_w_d::<1>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6124,7 +8125,10 @@ unsafe fn test_lsx_vssrlrni_d_q() { assert_eq!( r, - transmute(lsx_vssrlrni_d_q::<60>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_d_q::<60>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6140,7 +8144,10 @@ unsafe fn test_lsx_vssrlrni_bu_h() { assert_eq!( r, - transmute(lsx_vssrlrni_bu_h::<13>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_bu_h::<13>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6152,7 +8159,10 @@ unsafe fn test_lsx_vssrlrni_hu_w() { assert_eq!( r, - transmute(lsx_vssrlrni_hu_w::<25>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_hu_w::<25>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6164,7 +8174,10 @@ unsafe fn test_lsx_vssrlrni_wu_d() { assert_eq!( r, - transmute(lsx_vssrlrni_wu_d::<36>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_wu_d::<36>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6176,7 +8189,10 @@ unsafe fn test_lsx_vssrlrni_du_q() { assert_eq!( r, - transmute(lsx_vssrlrni_du_q::<38>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_du_q::<38>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6192,7 +8208,10 @@ unsafe fn test_lsx_vsrani_b_h() { assert_eq!( r, - transmute(lsx_vsrani_b_h::<5>(transmute(a), transmute(b))) + transmute(lsx_vsrani_b_h::<5>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6204,7 +8223,10 @@ unsafe fn test_lsx_vsrani_h_w() { assert_eq!( r, - transmute(lsx_vsrani_h_w::<4>(transmute(a), transmute(b))) + transmute(lsx_vsrani_h_w::<4>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6216,7 +8238,10 @@ unsafe fn test_lsx_vsrani_w_d() { assert_eq!( r, - transmute(lsx_vsrani_w_d::<24>(transmute(a), transmute(b))) + transmute(lsx_vsrani_w_d::<24>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6228,7 +8253,10 @@ unsafe fn test_lsx_vsrani_d_q() { assert_eq!( r, - transmute(lsx_vsrani_d_q::<81>(transmute(a), transmute(b))) + transmute(lsx_vsrani_d_q::<81>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6244,7 +8272,10 @@ unsafe fn test_lsx_vsrarni_b_h() { assert_eq!( r, - transmute(lsx_vsrarni_b_h::<3>(transmute(a), transmute(b))) + transmute(lsx_vsrarni_b_h::<3>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6256,7 +8287,10 @@ unsafe fn test_lsx_vsrarni_h_w() { assert_eq!( r, - transmute(lsx_vsrarni_h_w::<15>(transmute(a), transmute(b))) + transmute(lsx_vsrarni_h_w::<15>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6268,7 +8302,10 @@ unsafe fn test_lsx_vsrarni_w_d() { assert_eq!( r, - transmute(lsx_vsrarni_w_d::<59>(transmute(a), transmute(b))) + transmute(lsx_vsrarni_w_d::<59>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6280,7 +8317,10 @@ unsafe fn test_lsx_vsrarni_d_q() { assert_eq!( r, - transmute(lsx_vsrarni_d_q::<0>(transmute(a), transmute(b))) + transmute(lsx_vsrarni_d_q::<0>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6296,7 +8336,10 @@ unsafe fn test_lsx_vssrani_b_h() { assert_eq!( r, - transmute(lsx_vssrani_b_h::<0>(transmute(a), transmute(b))) + transmute(lsx_vssrani_b_h::<0>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6308,7 +8351,10 @@ unsafe fn test_lsx_vssrani_h_w() { assert_eq!( r, - transmute(lsx_vssrani_h_w::<28>(transmute(a), transmute(b))) + transmute(lsx_vssrani_h_w::<28>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6320,7 +8366,10 @@ unsafe fn test_lsx_vssrani_w_d() { assert_eq!( r, - transmute(lsx_vssrani_w_d::<49>(transmute(a), transmute(b))) + transmute(lsx_vssrani_w_d::<49>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6332,7 +8381,10 @@ unsafe fn test_lsx_vssrani_d_q() { assert_eq!( r, - transmute(lsx_vssrani_d_q::<80>(transmute(a), transmute(b))) + transmute(lsx_vssrani_d_q::<80>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6348,7 +8400,10 @@ unsafe fn test_lsx_vssrani_bu_h() { assert_eq!( r, - transmute(lsx_vssrani_bu_h::<14>(transmute(a), transmute(b))) + transmute(lsx_vssrani_bu_h::<14>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6360,7 +8415,10 @@ unsafe fn test_lsx_vssrani_hu_w() { assert_eq!( r, - transmute(lsx_vssrani_hu_w::<23>(transmute(a), transmute(b))) + transmute(lsx_vssrani_hu_w::<23>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6372,7 +8430,10 @@ unsafe fn test_lsx_vssrani_wu_d() { assert_eq!( r, - transmute(lsx_vssrani_wu_d::<13>(transmute(a), transmute(b))) + transmute(lsx_vssrani_wu_d::<13>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6384,7 +8445,10 @@ unsafe fn test_lsx_vssrani_du_q() { assert_eq!( r, - transmute(lsx_vssrani_du_q::<33>(transmute(a), transmute(b))) + transmute(lsx_vssrani_du_q::<33>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6400,7 +8464,10 @@ unsafe fn test_lsx_vssrarni_b_h() { assert_eq!( r, - transmute(lsx_vssrarni_b_h::<2>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_b_h::<2>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6412,7 +8479,10 @@ unsafe fn test_lsx_vssrarni_h_w() { assert_eq!( r, - transmute(lsx_vssrarni_h_w::<29>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_h_w::<29>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6424,7 +8494,10 @@ unsafe fn test_lsx_vssrarni_w_d() { assert_eq!( r, - transmute(lsx_vssrarni_w_d::<18>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_w_d::<18>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6436,7 +8509,10 @@ unsafe fn test_lsx_vssrarni_d_q() { assert_eq!( r, - transmute(lsx_vssrarni_d_q::<70>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_d_q::<70>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6452,7 +8528,10 @@ unsafe fn test_lsx_vssrarni_bu_h() { assert_eq!( r, - transmute(lsx_vssrarni_bu_h::<14>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_bu_h::<14>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6464,7 +8543,10 @@ unsafe fn test_lsx_vssrarni_hu_w() { assert_eq!( r, - transmute(lsx_vssrarni_hu_w::<13>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_hu_w::<13>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6476,7 +8558,10 @@ unsafe fn test_lsx_vssrarni_wu_d() { assert_eq!( r, - transmute(lsx_vssrarni_wu_d::<15>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_wu_d::<15>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6488,7 +8573,10 @@ unsafe fn test_lsx_vssrarni_du_q() { assert_eq!( r, - transmute(lsx_vssrarni_du_q::<126>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_du_q::<126>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6500,7 +8588,10 @@ unsafe fn test_lsx_vpermi_w() { assert_eq!( r, - transmute(lsx_vpermi_w::<158>(transmute(a), transmute(b))) + transmute(lsx_vpermi_w::<158>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6524,7 +8615,7 @@ unsafe fn test_lsx_vst() { ]; let r = i64x2::new(4153633675232462821, -2083384694265299697); - lsx_vst::<0>(transmute(a), o.as_mut_ptr()); + lsx_vst::<0>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -6534,7 +8625,13 @@ unsafe fn test_lsx_vssrlrn_b_h() { let b = i16x8::new(17437, 9775, -20467, -31838, 5913, 4238, -7458, 2822); let r = i64x2::new(5981906731171643399, 0); - assert_eq!(r, transmute(lsx_vssrlrn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrlrn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6543,7 +8640,13 @@ unsafe fn test_lsx_vssrlrn_h_w() { let b = i32x4::new(-2116426818, 1641049288, 712377342, -1572394121); let r = i64x2::new(31243728857268226, 0); - assert_eq!(r, transmute(lsx_vssrlrn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrlrn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6552,7 +8655,13 @@ unsafe fn test_lsx_vssrlrn_w_d() { let b = i64x2::new(-3890929847852895653, -7819301294522132056); let r = i64x2::new(66519777023098879, 0); - assert_eq!(r, transmute(lsx_vssrlrn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrlrn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6561,7 +8670,13 @@ unsafe fn test_lsx_vssrln_b_h() { let b = i16x8::new(-14062, -29610, -24609, -8884, -1818, 32133, 29934, -6498); let r = i64x2::new(140183437672319, 0); - assert_eq!(r, transmute(lsx_vssrln_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrln_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6570,7 +8685,13 @@ unsafe fn test_lsx_vssrln_h_w() { let b = i32x4::new(-1437891045, 1546371535, -1800954476, -1892390372); let r = i64x2::new(2820489990832156, 0); - assert_eq!(r, transmute(lsx_vssrln_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrln_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6579,7 +8700,13 @@ unsafe fn test_lsx_vssrln_w_d() { let b = i64x2::new(2034490755997557661, -3470252066162700534); let r = i64x2::new(9223372034707292159, 0); - assert_eq!(r, transmute(lsx_vssrln_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrln_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6592,7 +8719,10 @@ unsafe fn test_lsx_vorn_v() { ); let r = i64x2::new(-883973744907789059, -2901520201165080862); - assert_eq!(r, transmute(lsx_vorn_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vorn_v(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -6615,7 +8745,11 @@ unsafe fn test_lsx_vshuf_b() { assert_eq!( r, - transmute(lsx_vshuf_b(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vshuf_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -6639,7 +8773,7 @@ unsafe fn test_lsx_vstx() { ]; let r = i64x2::new(-1493444417618012559, 7191635320606490850); - lsx_vstx(transmute(a), o.as_mut_ptr(), 0); + lsx_vstx(black_box(transmute(a)), o.as_mut_ptr(), 0); assert_eq!(r, transmute(o)); } @@ -6648,7 +8782,7 @@ unsafe fn test_lsx_vextl_qu_du() { let a = u64x2::new(14708598110732796778, 2132245682694336458); let r = i64x2::new(-3738145962976754838, 0); - assert_eq!(r, transmute(lsx_vextl_qu_du(transmute(a)))); + assert_eq!(r, transmute(lsx_vextl_qu_du(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6658,7 +8792,7 @@ unsafe fn test_lsx_bnz_b() { ); let r: i32 = 1; - assert_eq!(r, transmute(lsx_bnz_b(transmute(a)))); + assert_eq!(r, transmute(lsx_bnz_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6666,7 +8800,7 @@ unsafe fn test_lsx_bnz_d() { let a = u64x2::new(2935166648440262530, 9853932033129373129); let r: i32 = 1; - assert_eq!(r, transmute(lsx_bnz_d(transmute(a)))); + assert_eq!(r, transmute(lsx_bnz_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6674,7 +8808,7 @@ unsafe fn test_lsx_bnz_h() { let a = u16x8::new(55695, 60003, 59560, 35123, 25693, 41352, 61626, 42007); let r: i32 = 1; - assert_eq!(r, transmute(lsx_bnz_h(transmute(a)))); + assert_eq!(r, transmute(lsx_bnz_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6684,7 +8818,7 @@ unsafe fn test_lsx_bnz_v() { ); let r: i32 = 1; - assert_eq!(r, transmute(lsx_bnz_v(transmute(a)))); + assert_eq!(r, transmute(lsx_bnz_v(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6692,7 +8826,7 @@ unsafe fn test_lsx_bnz_w() { let a = u32x4::new(1172712391, 4211490091, 1954893853, 1606462106); let r: i32 = 1; - assert_eq!(r, transmute(lsx_bnz_w(transmute(a)))); + assert_eq!(r, transmute(lsx_bnz_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6702,7 +8836,7 @@ unsafe fn test_lsx_bz_b() { ); let r: i32 = 0; - assert_eq!(r, transmute(lsx_bz_b(transmute(a)))); + assert_eq!(r, transmute(lsx_bz_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6710,7 +8844,7 @@ unsafe fn test_lsx_bz_d() { let a = u64x2::new(6051854163594201075, 9957257179760945130); let r: i32 = 0; - assert_eq!(r, transmute(lsx_bz_d(transmute(a)))); + assert_eq!(r, transmute(lsx_bz_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6718,7 +8852,7 @@ unsafe fn test_lsx_bz_h() { let a = u16x8::new(19470, 29377, 53886, 60432, 20799, 41755, 54479, 52192); let r: i32 = 0; - assert_eq!(r, transmute(lsx_bz_h(transmute(a)))); + assert_eq!(r, transmute(lsx_bz_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6728,7 +8862,7 @@ unsafe fn test_lsx_bz_v() { ); let r: i32 = 0; - assert_eq!(r, transmute(lsx_bz_v(transmute(a)))); + assert_eq!(r, transmute(lsx_bz_v(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6736,7 +8870,7 @@ unsafe fn test_lsx_bz_w() { let a = u32x4::new(840335855, 1404686204, 628335401, 1171808080); let r: i32 = 0; - assert_eq!(r, transmute(lsx_bz_w(transmute(a)))); + assert_eq!(r, transmute(lsx_bz_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6745,7 +8879,13 @@ unsafe fn test_lsx_vfcmp_caf_d() { let b = u64x2::new(4594845432849836188, 4605165420863530034); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_caf_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_caf_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6754,7 +8894,13 @@ unsafe fn test_lsx_vfcmp_caf_s() { let b = u32x4::new(1058412800, 1058762495, 1028487696, 1027290752); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_caf_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_caf_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6763,7 +8909,13 @@ unsafe fn test_lsx_vfcmp_ceq_d() { let b = u64x2::new(4605937250150464526, 4596769502461699132); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_ceq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_ceq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6772,7 +8924,13 @@ unsafe fn test_lsx_vfcmp_ceq_s() { let b = u32x4::new(1057471620, 1064008655, 1062698831, 1064822930); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_ceq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_ceq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6781,7 +8939,13 @@ unsafe fn test_lsx_vfcmp_cle_d() { let b = u64x2::new(4596931282408842596, 4592481315209481584); let r = i64x2::new(-1, 0); - assert_eq!(r, transmute(lsx_vfcmp_cle_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cle_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6790,7 +8954,13 @@ unsafe fn test_lsx_vfcmp_cle_s() { let b = u32x4::new(1021993344, 1043028808, 1064182329, 1054794412); let r = i64x2::new(-4294967296, -1); - assert_eq!(r, transmute(lsx_vfcmp_cle_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cle_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6799,7 +8969,13 @@ unsafe fn test_lsx_vfcmp_clt_d() { let b = u64x2::new(4603056125735978454, 4595932368389116476); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_clt_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_clt_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6808,7 +8984,13 @@ unsafe fn test_lsx_vfcmp_clt_s() { let b = u32x4::new(1040327468, 1040072248, 1063314103, 1061361061); let r = i64x2::new(0, -1); - assert_eq!(r, transmute(lsx_vfcmp_clt_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_clt_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6817,7 +8999,13 @@ unsafe fn test_lsx_vfcmp_cne_d() { let b = u64x2::new(4602354759349431170, 4598595124838935466); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_cne_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cne_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6826,7 +9014,13 @@ unsafe fn test_lsx_vfcmp_cne_s() { let b = u32x4::new(1063262940, 1058010357, 1052721962, 1061295988); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_cne_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cne_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6835,7 +9029,13 @@ unsafe fn test_lsx_vfcmp_cor_d() { let b = u64x2::new(4606863361114437050, 4600753700959452152); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_cor_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cor_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6844,7 +9044,13 @@ unsafe fn test_lsx_vfcmp_cor_s() { let b = u32x4::new(1053615382, 1065255138, 1051565294, 1041776832); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_cor_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cor_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6853,7 +9059,13 @@ unsafe fn test_lsx_vfcmp_cueq_d() { let b = u64x2::new(4603317345052528721, 4586734343919602352); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_cueq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cueq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6862,7 +9074,13 @@ unsafe fn test_lsx_vfcmp_cueq_s() { let b = u32x4::new(1057082822, 1059761998, 1052599998, 1054369118); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_cueq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cueq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6871,7 +9089,13 @@ unsafe fn test_lsx_vfcmp_cule_d() { let b = u64x2::new(4604253448175093958, 4599648167588382448); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_cule_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cule_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6880,7 +9104,13 @@ unsafe fn test_lsx_vfcmp_cule_s() { let b = u32x4::new(1051100696, 1062219104, 1064568294, 1032521352); let r = i64x2::new(-4294967296, 4294967295); - assert_eq!(r, transmute(lsx_vfcmp_cule_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cule_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6889,7 +9119,13 @@ unsafe fn test_lsx_vfcmp_cult_d() { let b = u64x2::new(4602944708025910986, 4606429728449082215); let r = i64x2::new(0, -1); - assert_eq!(r, transmute(lsx_vfcmp_cult_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cult_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6898,7 +9134,13 @@ unsafe fn test_lsx_vfcmp_cult_s() { let b = u32x4::new(1030808384, 1044268840, 1050761328, 1037308928); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_cult_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cult_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6907,7 +9149,13 @@ unsafe fn test_lsx_vfcmp_cun_d() { let b = u64x2::new(4599145506416791474, 4602762942707610466); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_cun_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cun_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6916,7 +9164,13 @@ unsafe fn test_lsx_vfcmp_cune_d() { let b = u64x2::new(4602895209237804084, 4598685577984089858); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_cune_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cune_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6925,7 +9179,13 @@ unsafe fn test_lsx_vfcmp_cune_s() { let b = u32x4::new(1049955876, 1032474200, 1023410112, 1050347912); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_cune_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cune_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6934,7 +9194,13 @@ unsafe fn test_lsx_vfcmp_cun_s() { let b = u32x4::new(1053288920, 1059911123, 1058695573, 1062913175); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_cun_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cun_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6943,7 +9209,13 @@ unsafe fn test_lsx_vfcmp_saf_d() { let b = u64x2::new(4589118818065931376, 4603302333347826011); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_saf_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_saf_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6952,7 +9224,13 @@ unsafe fn test_lsx_vfcmp_saf_s() { let b = u32x4::new(1044756936, 1054667546, 1059141760, 1062203553); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_saf_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_saf_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6961,7 +9239,13 @@ unsafe fn test_lsx_vfcmp_seq_d() { let b = u64x2::new(4594167956310606988, 4596272126122589228); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_seq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_seq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6970,7 +9254,13 @@ unsafe fn test_lsx_vfcmp_seq_s() { let b = u32x4::new(1057231588, 1051495460, 1057998997, 1049117328); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_seq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_seq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6979,7 +9269,13 @@ unsafe fn test_lsx_vfcmp_sle_d() { let b = u64x2::new(4603919005855163252, 4594682846653946884); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_sle_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sle_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6988,7 +9284,13 @@ unsafe fn test_lsx_vfcmp_sle_s() { let b = u32x4::new(1045989468, 1052518900, 1046184640, 1032417352); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_sle_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sle_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6997,7 +9299,13 @@ unsafe fn test_lsx_vfcmp_slt_d() { let b = u64x2::new(4600564867142526828, 4585131890265864544); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_slt_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_slt_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7006,7 +9314,13 @@ unsafe fn test_lsx_vfcmp_slt_s() { let b = u32x4::new(1063435026, 1062439603, 1060665555, 1059252630); let r = i64x2::new(-1, -4294967296); - assert_eq!(r, transmute(lsx_vfcmp_slt_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_slt_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7015,7 +9329,13 @@ unsafe fn test_lsx_vfcmp_sne_d() { let b = u64x2::new(4606789952952688555, 4605380358192261377); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_sne_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sne_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7024,7 +9344,13 @@ unsafe fn test_lsx_vfcmp_sne_s() { let b = u32x4::new(1055803760, 1063372602, 1062608900, 1054634370); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_sne_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sne_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7033,7 +9359,13 @@ unsafe fn test_lsx_vfcmp_sor_d() { let b = u64x2::new(4606380175568635560, 4602092067387067462); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_sor_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sor_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7042,7 +9374,13 @@ unsafe fn test_lsx_vfcmp_sor_s() { let b = u32x4::new(1064534350, 1035771168, 1059142426, 1034677600); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_sor_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sor_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7051,7 +9389,13 @@ unsafe fn test_lsx_vfcmp_sueq_d() { let b = u64x2::new(4602917609947054533, 4605983209212177197); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_sueq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sueq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7060,7 +9404,13 @@ unsafe fn test_lsx_vfcmp_sueq_s() { let b = u32x4::new(1064871165, 1059796257, 1055456352, 1058662692); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_sueq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sueq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7069,7 +9419,13 @@ unsafe fn test_lsx_vfcmp_sule_d() { let b = u64x2::new(4594044173266256632, 4601549551994738386); let r = i64x2::new(0, -1); - assert_eq!(r, transmute(lsx_vfcmp_sule_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sule_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7078,7 +9434,13 @@ unsafe fn test_lsx_vfcmp_sule_s() { let b = u32x4::new(1061061244, 1051874412, 1041025316, 1056018690); let r = i64x2::new(4294967295, -1); - assert_eq!(r, transmute(lsx_vfcmp_sule_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sule_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7087,7 +9449,13 @@ unsafe fn test_lsx_vfcmp_sult_d() { let b = u64x2::new(4603848042095479627, 4605032971316970060); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_sult_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sult_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7096,7 +9464,13 @@ unsafe fn test_lsx_vfcmp_sult_s() { let b = u32x4::new(1053631630, 1064026599, 1058029398, 1041182304); let r = i64x2::new(-4294967296, 4294967295); - assert_eq!(r, transmute(lsx_vfcmp_sult_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sult_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7105,7 +9479,13 @@ unsafe fn test_lsx_vfcmp_sun_d() { let b = u64x2::new(4560681020073292800, 4604624347352815433); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_sun_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sun_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7114,7 +9494,13 @@ unsafe fn test_lsx_vfcmp_sune_d() { let b = u64x2::new(4593947987798339484, 4603656097008761637); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_sune_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sune_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7123,7 +9509,13 @@ unsafe fn test_lsx_vfcmp_sune_s() { let b = u32x4::new(1049327168, 1034635272, 1042258196, 1062844003); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_sune_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sune_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7132,7 +9524,13 @@ unsafe fn test_lsx_vfcmp_sun_s() { let b = u32x4::new(1057442863, 1064573466, 1058086753, 1015993248); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_sun_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sun_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] diff --git a/library/stdarch/crates/core_arch/src/loongarch64/mod.rs b/library/stdarch/crates/core_arch/src/loongarch64/mod.rs index ab968aff20bbe..44c8f1d28e0d8 100644 --- a/library/stdarch/crates/core_arch/src/loongarch64/mod.rs +++ b/library/stdarch/crates/core_arch/src/loongarch64/mod.rs @@ -2,6 +2,7 @@ mod lasx; mod lsx; +mod simd; #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub use self::lasx::*; @@ -11,7 +12,7 @@ pub use self::lsx::*; use crate::arch::asm; /// Reads the 64-bit stable counter value and the counter ID -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn rdtime_d() -> (i64, isize) { let (val, tid): (i64, isize); @@ -21,8 +22,20 @@ pub fn rdtime_d() -> (i64, isize) { #[allow(improper_ctypes)] unsafe extern "unadjusted" { + #[link_name = "llvm.loongarch.crc.w.b.w"] + fn __crc_w_b_w(a: i32, b: i32) -> i32; + #[link_name = "llvm.loongarch.crc.w.h.w"] + fn __crc_w_h_w(a: i32, b: i32) -> i32; + #[link_name = "llvm.loongarch.crc.w.w.w"] + fn __crc_w_w_w(a: i32, b: i32) -> i32; #[link_name = "llvm.loongarch.crc.w.d.w"] fn __crc_w_d_w(a: i64, b: i32) -> i32; + #[link_name = "llvm.loongarch.crcc.w.b.w"] + fn __crcc_w_b_w(a: i32, b: i32) -> i32; + #[link_name = "llvm.loongarch.crcc.w.h.w"] + fn __crcc_w_h_w(a: i32, b: i32) -> i32; + #[link_name = "llvm.loongarch.crcc.w.w.w"] + fn __crcc_w_w_w(a: i32, b: i32) -> i32; #[link_name = "llvm.loongarch.crcc.w.d.w"] fn __crcc_w_d_w(a: i64, b: i32) -> i32; #[link_name = "llvm.loongarch.cacop.d"] @@ -48,21 +61,63 @@ unsafe extern "unadjusted" { } /// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] +#[inline(always)] +#[stable(feature = "stdarch_loongarch_crc", since = "1.98.0")] +pub fn crc_w_b_w(a: i8, b: i32) -> i32 { + unsafe { __crc_w_b_w(a as i32, b) } +} + +/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) +#[inline(always)] +#[stable(feature = "stdarch_loongarch_crc", since = "1.98.0")] +pub fn crc_w_h_w(a: i16, b: i32) -> i32 { + unsafe { __crc_w_h_w(a as i32, b) } +} + +/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) +#[inline(always)] +#[stable(feature = "stdarch_loongarch_crc", since = "1.98.0")] +pub fn crc_w_w_w(a: i32, b: i32) -> i32 { + unsafe { __crc_w_w_w(a, b) } +} + +/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) +#[inline(always)] +#[stable(feature = "stdarch_loongarch_crc", since = "1.98.0")] pub fn crc_w_d_w(a: i64, b: i32) -> i32 { unsafe { __crc_w_d_w(a, b) } } /// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] +#[inline(always)] +#[stable(feature = "stdarch_loongarch_crc", since = "1.98.0")] +pub fn crcc_w_b_w(a: i8, b: i32) -> i32 { + unsafe { __crcc_w_b_w(a as i32, b) } +} + +/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) +#[inline(always)] +#[stable(feature = "stdarch_loongarch_crc", since = "1.98.0")] +pub fn crcc_w_h_w(a: i16, b: i32) -> i32 { + unsafe { __crcc_w_h_w(a as i32, b) } +} + +/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) +#[inline(always)] +#[stable(feature = "stdarch_loongarch_crc", since = "1.98.0")] +pub fn crcc_w_w_w(a: i32, b: i32) -> i32 { + unsafe { __crcc_w_w_w(a, b) } +} + +/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) +#[inline(always)] +#[stable(feature = "stdarch_loongarch_crc", since = "1.98.0")] pub fn crcc_w_d_w(a: i64, b: i32) -> i32 { unsafe { __crcc_w_d_w(a, b) } } /// Generates the cache operation instruction -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn cacop(b: i64) { static_assert_uimm_bits!(IMM5, 5); @@ -71,7 +126,7 @@ pub unsafe fn cacop(b: i64) { } /// Reads the CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn csrrd() -> i64 { static_assert_uimm_bits!(IMM14, 14); @@ -79,7 +134,7 @@ pub unsafe fn csrrd() -> i64 { } /// Writes the CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn csrwr(a: i64) -> i64 { static_assert_uimm_bits!(IMM14, 14); @@ -87,7 +142,7 @@ pub unsafe fn csrwr(a: i64) -> i64 { } /// Exchanges the CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn csrxchg(a: i64, b: i64) -> i64 { static_assert_uimm_bits!(IMM14, 14); @@ -95,35 +150,35 @@ pub unsafe fn csrxchg(a: i64, b: i64) -> i64 { } /// Reads the 64-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrrd_d(a: i32) -> i64 { __iocsrrd_d(a) } /// Writes the 64-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrwr_d(a: i64, b: i32) { __iocsrwr_d(a, b) } -/// Generates the less-than-or-equal asseration instruction -#[inline] +/// Generates the less-than-or-equal assertion instruction +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn asrtle(a: i64, b: i64) { __asrtle(a, b); } -/// Generates the greater-than asseration instruction -#[inline] +/// Generates the greater-than assertion instruction +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn asrtgt(a: i64, b: i64) { __asrtgt(a, b); } /// Loads the page table directory entry -#[inline] +#[inline(always)] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn lddir(a: i64) -> i64 { @@ -132,10 +187,28 @@ pub unsafe fn lddir(a: i64) -> i64 { } /// Loads the page table entry -#[inline] +#[inline(always)] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn ldpte(a: i64) { static_assert_uimm_bits!(IMM8, 8); __ldpte(a, IMM8) } + +#[cfg(test)] +mod tests { + use super::*; + + #[test] + fn crc32() { + assert_eq!(crc_w_b_w(-1, -1), 16777215); + assert_eq!(crc_w_h_w(-1, -1), 65535); + assert_eq!(crc_w_w_w(-1, -1), 0); + assert_eq!(crc_w_d_w(-1, -1), 3736805603u32.cast_signed()); + + assert_eq!(crcc_w_b_w(-1, -1), 16777215); + assert_eq!(crcc_w_h_w(-1, -1), 65535); + assert_eq!(crcc_w_w_w(-1, -1), 0); + assert_eq!(crcc_w_d_w(-1, -1), 3080238136u32.cast_signed()); + } +} diff --git a/library/stdarch/crates/core_arch/src/loongarch64/simd.rs b/library/stdarch/crates/core_arch/src/loongarch64/simd.rs new file mode 100644 index 0000000000000..1d83333e2f532 --- /dev/null +++ b/library/stdarch/crates/core_arch/src/loongarch64/simd.rs @@ -0,0 +1,604 @@ +//! LoongArch64 SIMD helpers + +use crate::intrinsics::simd::*; + +// Internal extension trait for concrete `Simd` types. +// +// Provides a small set of helper functionality (`Elem` and `splat`) +// so generic and macro-based code can operate on different SIMD +// vector types in a uniform way. +pub(super) const trait SimdExt: Sized { + type Elem; + + unsafe fn splat(v: i64) -> Self; +} + +#[rustfmt::skip] // FIXME: https://github.com/rust-lang/stdarch/pull/2133#issuecomment-4524350350 +macro_rules! impl_simd_ext { + ($v:ident, $e:ty) => { + #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] + const impl SimdExt for crate::core_arch::simd::$v { + type Elem = $e; + + #[inline(always)] + unsafe fn splat(v: i64) -> Self { + simd_splat(v as Self::Elem) + } + } + }; +} + +impl_simd_ext!(i8x16, i8); +impl_simd_ext!(i8x32, i8); +impl_simd_ext!(u8x16, u8); +impl_simd_ext!(u8x32, u8); +impl_simd_ext!(i16x8, i16); +impl_simd_ext!(i16x16, i16); +impl_simd_ext!(i16x32, i16); +impl_simd_ext!(u16x8, u16); +impl_simd_ext!(u16x16, u16); +impl_simd_ext!(u16x32, u16); +impl_simd_ext!(i32x4, i32); +impl_simd_ext!(i32x8, i32); +impl_simd_ext!(i32x16, i32); +impl_simd_ext!(u32x4, u32); +impl_simd_ext!(u32x8, u32); +impl_simd_ext!(u32x16, u32); +impl_simd_ext!(i64x2, i64); +impl_simd_ext!(i64x4, i64); +impl_simd_ext!(i64x8, i64); +impl_simd_ext!(u64x2, u64); +impl_simd_ext!(u64x4, u64); +impl_simd_ext!(u64x8, u64); +impl_simd_ext!(i128x2, i128); +impl_simd_ext!(u128x2, u128); +impl_simd_ext!(i128x4, i128); +impl_simd_ext!(u128x4, u128); + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_abs(a: T) -> T { + let m: T = simd_lt(a, simd_ext_splat(0)); + simd_select(m, simd_neg(a), a) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_absd(a: T, b: T) -> T { + let m: T = simd_gt(a, b); + simd_select(m, simd_sub(a, b), simd_sub(b, a)) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_adda(a: T, b: T) -> T { + simd_add(simd_ext_abs(a), simd_ext_abs(b)) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_andn(a: T, b: T) -> T { + simd_and(simd_ext_not(a), b) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_bitclr(a: T, b: T) -> T { + simd_ext_andn(simd_ext_shl(simd_ext_splat(1), b), a) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_bitrev(a: T, b: T) -> T { + simd_xor(simd_ext_shl(simd_ext_splat(1), b), a) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_bitset(a: T, b: T) -> T { + simd_or(simd_ext_shl(simd_ext_splat(1), b), a) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_fmsub(a: T, b: T, c: T) -> T { + simd_fma(a, b, simd_neg(c)) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_fnmadd(a: T, b: T, c: T) -> T { + simd_neg(simd_fma(a, b, c)) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_fnmsub(a: T, b: T, c: T) -> T { + simd_neg(simd_ext_fmsub(a, b, c)) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_frecip_s(a: T) -> T { + simd_div(simd_splat(1.0f32), a) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_frecip_d(a: T) -> T { + simd_div(simd_splat(1.0f64), a) +} + +#[inline(always)] +pub(super) unsafe fn simd_ext_frsqrt_s(a: T) -> T { + simd_ext_frecip_s(simd_fsqrt(a)) +} + +#[inline(always)] +pub(super) unsafe fn simd_ext_frsqrt_d(a: T) -> T { + simd_ext_frecip_d(simd_fsqrt(a)) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_ld(a: *const i8) -> T { + let a = a.offset(I as isize) as *const T; + core::ptr::read_unaligned(a) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_ldi() -> T { + use crate::core_arch::simd::{i8x8, i16x4, i32x2}; + use crate::mem::transmute; + + #[inline(always)] + const fn sext(v: i32, bits: u32) -> i64 { + ((v as i64) << (64 - bits)) >> (64 - bits) + } + + #[inline(always)] + const fn expand_u8(imm: i32) -> u64 { + let mut v = imm as u64; + v = (v | (v << 28)) & 0x0000000f0000000f; + v = (v | (v << 14)) & 0x0003000300030003; + v = (v | (v << 7)) & 0x0101010101010101; + v.wrapping_mul(0xff) + } + + #[inline(always)] + const fn fp32_imm(imm: i32) -> i32 { + ((imm & 0x80) << 24) + | ((!imm & 0x40) << 24) + | (((imm & 0x40) >> 6).wrapping_mul(0x1f) << 25) + | ((imm & 0x3f) << 19) + } + + #[inline(always)] + const fn fp64_imm(imm: i32) -> i64 { + ((((imm & 0x80) << 24) + | ((!imm & 0x40) << 24) + | (((imm & 0x40) >> 6).wrapping_mul(0xff) << 22) + | ((imm & 0x3f) << 16)) as i64) + << 32 + } + + let imm8 = I & 0xff; + let imm10 = I & 0x3ff; + + let r = if (I & 0x1000) == 0 { + match (I >> 10) & 3 { + 0 => transmute(i8x8::splat(imm8 as i8)), + 1 => transmute(i16x4::splat(sext(imm10, 10) as i16)), + 2 => transmute(i32x2::splat(sext(imm10, 10) as i32)), + 3 => sext(imm10, 10), + _ => unreachable!(), + } + } else { + match (I >> 8) & 0xf { + 0..=3 => transmute(i32x2::splat(imm8 << (8 * ((I >> 8) & 3)))), + 4..=5 => transmute(i16x4::splat((imm8 as i16) << (8 * ((I >> 8) & 1)))), + 6 => transmute(i32x2::splat((imm8 << 8) | 0xff)), + 7 => transmute(i32x2::splat((imm8 << 16) | 0xffff)), + 8 => transmute(i8x8::splat(imm8 as i8)), + 9 => expand_u8(imm8) as i64, + 10 => transmute(i32x2::splat(fp32_imm(I))), + 11 => transmute(i32x2::from_array([fp32_imm(I), 0])), + 12 => fp64_imm(I), + _ => unreachable!(), + } + }; + + simd_ext_splat(r) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_ldx(a: *const i8, b: i64) -> T { + let a = a.offset(b as isize) as *const T; + core::ptr::read_unaligned(a) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_madd(a: T, b: T, c: T) -> T { + simd_add(a, simd_mul(b, c)) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_msub(a: T, b: T, c: T) -> T { + simd_sub(a, simd_mul(b, c)) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_muh(a: T, b: T) -> T { + let a: W = simd_cast(a); + let b: W = simd_cast(b); + let p = simd_mul(a, b); + simd_cast(simd_shr( + p, + simd_ext_splat((size_of::() * 8 / 2) as i64), + )) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_nor(a: T, b: T) -> T { + simd_ext_not(simd_or(a, b)) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_not(a: T) -> T { + simd_xor(a, simd_ext_splat(!0)) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_orn(a: T, b: T) -> T { + simd_or(a, simd_ext_not(b)) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_rotr(a: T, b: T) -> T { + let m = (size_of::() * 8 - 1) as i64; + let r = simd_and(b, simd_ext_splat(m)); + let l = simd_and(simd_sub(simd_ext_splat(m + 1), r), simd_ext_splat(m)); + simd_or(simd_shr(a, r), simd_shl(a, l)) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_shl(a: T, b: T) -> T { + let m = (size_of::() * 8 - 1) as i64; + simd_shl(a, simd_and(b, simd_ext_splat(m))) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_shr(a: T, b: T) -> T { + let m = (size_of::() * 8 - 1) as i64; + simd_shr(a, simd_and(b, simd_ext_splat(m))) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_splat(a: i64) -> T { + T::splat(a) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_st(a: T, b: *mut i8) { + let b = b.offset(I as isize) as *mut T; + core::ptr::write_unaligned(b, a); +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_ext_stx(a: T, b: *mut i8, c: i64) { + let b = b.offset(c as isize) as *mut T; + core::ptr::write_unaligned(b, a); +} + +macro_rules! impl_vv { + ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ty) => { + #[inline] + #[target_feature(enable = $ft)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name(a: $oty) -> $oty { + unsafe { + let a: $ity = transmute(a); + let r: $ity = $op(a); + transmute(r) + } + } + }; +} + +pub(super) use impl_vv; + +macro_rules! impl_gv { + ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $gty:ty) => { + #[inline] + #[target_feature(enable = $ft)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name(a: $gty) -> $oty { + unsafe { + let r: $ity = $op(a.into()); + transmute(r) + } + } + }; +} + +pub(super) use impl_gv; + +macro_rules! impl_ggv { + ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $gty:ty, $xty:ty, unsafe) => { + #[inline] + #[target_feature(enable = $ft)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub unsafe fn $name(a: $gty, b: $xty) -> $oty { + let r: $ity = $op(a, b); + transmute(r) + } + }; +} + +pub(super) use impl_ggv; + +macro_rules! impl_gsv { + ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $gty:ty, $ibs:expr, const, unsafe) => { + #[inline] + #[target_feature(enable = $ft)] + #[rustc_legacy_const_generics(1)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub unsafe fn $name(a: $gty) -> $oty { + static_assert_simm_bits!(IMM, $ibs); + let r: $ity = $op::(a); + transmute(r) + } + }; +} + +pub(super) use impl_gsv; + +macro_rules! impl_sv { + ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $ibs:expr) => { + #[inline] + #[target_feature(enable = $ft)] + #[rustc_legacy_const_generics(0)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name() -> $oty { + static_assert_simm_bits!(IMM, $ibs); + unsafe { + let r: $ity = $op(IMM.into()); + transmute(r) + } + } + }; + ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $ibs:expr, const) => { + #[inline] + #[target_feature(enable = $ft)] + #[rustc_legacy_const_generics(0)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name() -> $oty { + static_assert_simm_bits!(IMM, $ibs); + unsafe { + let r: $ity = $op::(); + transmute(r) + } + } + }; +} + +pub(super) use impl_sv; + +macro_rules! impl_vvv { + ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ty) => { + #[inline] + #[target_feature(enable = $ft)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name(a: $oty, b: $oty) -> $oty { + unsafe { + let a: $ity = transmute(a); + let b: $ity = transmute(b); + let r: $ity = $op(a, b); + transmute(r) + } + } + }; + ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ty, $wty:ty) => { + #[inline] + #[target_feature(enable = $ft)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name(a: $oty, b: $oty) -> $oty { + unsafe { + let a: $ity = transmute(a); + let b: $ity = transmute(b); + let r: $ity = $op::<$ity, $wty>(a, b); + transmute(r) + } + } + }; +} + +pub(super) use impl_vvv; + +macro_rules! impl_vgg { + ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $gty:ty, $xty:ty, unsafe) => { + #[inline] + #[target_feature(enable = $ft)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub unsafe fn $name(a: $oty, b: $gty, c: $xty) { + $op(a, b, c); + } + }; +} + +pub(super) use impl_vgg; + +macro_rules! impl_vgs { + ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $gty:ty, $ibs:expr, const, unsafe) => { + #[inline] + #[target_feature(enable = $ft)] + #[rustc_legacy_const_generics(2)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub unsafe fn $name(a: $oty, b: $gty) { + static_assert_simm_bits!(IMM, $ibs); + $op::(a, b); + } + }; +} + +pub(super) use impl_vgs; + +macro_rules! impl_vuv { + ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident) => { + #[inline] + #[target_feature(enable = $ft)] + #[rustc_legacy_const_generics(1)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name(a: $oty) -> $oty { + static_assert_uimm_bits!(IMM, (size_of::<<$ity as SimdExt>::Elem>() * 8).ilog2()); + unsafe { + let a: $ity = transmute(a); + let b: $ity = simd_ext_splat(IMM.into()); + let r: $ity = $op(a, b); + transmute(r) + } + } + }; + ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $ibs:expr) => { + #[inline] + #[target_feature(enable = $ft)] + #[rustc_legacy_const_generics(1)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name(a: $oty) -> $oty { + static_assert_uimm_bits!(IMM, $ibs); + unsafe { + let a: $ity = transmute(a); + let b: $ity = simd_ext_splat(IMM.into()); + let r: $ity = $op(a, b); + transmute(r) + } + } + }; + ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $ibs:expr, const) => { + #[inline] + #[target_feature(enable = $ft)] + #[rustc_legacy_const_generics(1)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name(a: $oty) -> $oty { + static_assert_uimm_bits!(IMM, $ibs); + unsafe { + let a: $ity = transmute(a); + let r: $ity = $op::(a); + transmute(r) + } + } + }; +} + +pub(super) use impl_vuv; + +macro_rules! impl_vug { + ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $gty:ty, $ibs:expr) => { + #[inline] + #[target_feature(enable = $ft)] + #[rustc_legacy_const_generics(1)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name(a: $oty) -> $gty { + static_assert_uimm_bits!(IMM, $ibs); + unsafe { + let a: $ity = transmute(a); + let r: <$ity as SimdExt>::Elem = $op(a, IMM); + r as $gty + } + } + }; +} + +pub(super) use impl_vug; + +macro_rules! impl_vsv { + ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $ibs:expr) => { + #[inline] + #[target_feature(enable = $ft)] + #[rustc_legacy_const_generics(1)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name(a: $oty) -> $oty { + static_assert_simm_bits!(IMM, $ibs); + unsafe { + let a: $ity = transmute(a); + let b: $ity = simd_ext_splat(IMM.into()); + let r: $ity = $op(a, b); + transmute(r) + } + } + }; +} + +pub(super) use impl_vsv; + +macro_rules! impl_vvvv { + ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ty) => { + #[inline] + #[target_feature(enable = $ft)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name(a: $oty, b: $oty, c: $oty) -> $oty { + unsafe { + let a: $ity = transmute(a); + let b: $ity = transmute(b); + let c: $ity = transmute(c); + let r: $ity = $op(a, b, c); + transmute(r) + } + } + }; +} + +pub(super) use impl_vvvv; + +macro_rules! impl_vvuv { + ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $ibs:expr, const) => { + #[inline] + #[target_feature(enable = $ft)] + #[rustc_legacy_const_generics(2)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name(a: $oty, b: $oty) -> $oty { + static_assert_uimm_bits!(IMM, $ibs); + unsafe { + let a: $ity = transmute(a); + let b: $ity = transmute(b); + let r: $ity = $op::(a, b); + transmute(r) + } + } + }; +} + +pub(super) use impl_vvuv; + +macro_rules! impl_vugv { + ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $gty:ty, $ibs:expr) => { + #[inline] + #[target_feature(enable = $ft)] + #[rustc_legacy_const_generics(2)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name(a: $oty, b: $gty) -> $oty { + static_assert_uimm_bits!(IMM, $ibs); + unsafe { + let a: $ity = transmute(a); + let r: $ity = $op(a, IMM, b as <$ity as SimdExt>::Elem); + transmute(r) + } + } + }; +} + +pub(super) use impl_vugv; diff --git a/library/stdarch/crates/core_arch/src/loongarch_shared/mod.rs b/library/stdarch/crates/core_arch/src/loongarch_shared/mod.rs index 8991fe857682b..4f24ff2932210 100644 --- a/library/stdarch/crates/core_arch/src/loongarch_shared/mod.rs +++ b/library/stdarch/crates/core_arch/src/loongarch_shared/mod.rs @@ -3,7 +3,7 @@ use crate::arch::asm; /// Reads the lower 32-bit stable counter value and the counter ID -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn rdtimel_w() -> (i32, isize) { let (val, tid): (i32, isize); @@ -12,7 +12,7 @@ pub fn rdtimel_w() -> (i32, isize) { } /// Reads the upper 32-bit stable counter value and the counter ID -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn rdtimeh_w() -> (i32, isize) { let (val, tid): (i32, isize); @@ -22,18 +22,6 @@ pub fn rdtimeh_w() -> (i32, isize) { #[allow(improper_ctypes)] unsafe extern "unadjusted" { - #[link_name = "llvm.loongarch.crc.w.b.w"] - fn __crc_w_b_w(a: i32, b: i32) -> i32; - #[link_name = "llvm.loongarch.crc.w.h.w"] - fn __crc_w_h_w(a: i32, b: i32) -> i32; - #[link_name = "llvm.loongarch.crc.w.w.w"] - fn __crc_w_w_w(a: i32, b: i32) -> i32; - #[link_name = "llvm.loongarch.crcc.w.b.w"] - fn __crcc_w_b_w(a: i32, b: i32) -> i32; - #[link_name = "llvm.loongarch.crcc.w.h.w"] - fn __crcc_w_h_w(a: i32, b: i32) -> i32; - #[link_name = "llvm.loongarch.crcc.w.w.w"] - fn __crcc_w_w_w(a: i32, b: i32) -> i32; #[link_name = "llvm.loongarch.dbar"] fn __dbar(a: i32); #[link_name = "llvm.loongarch.ibar"] @@ -70,50 +58,8 @@ unsafe extern "unadjusted" { fn __frsqrte_d(a: f64) -> f64; } -/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn crc_w_b_w(a: i32, b: i32) -> i32 { - unsafe { __crc_w_b_w(a, b) } -} - -/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn crc_w_h_w(a: i32, b: i32) -> i32 { - unsafe { __crc_w_h_w(a, b) } -} - -/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn crc_w_w_w(a: i32, b: i32) -> i32 { - unsafe { __crc_w_w_w(a, b) } -} - -/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn crcc_w_b_w(a: i32, b: i32) -> i32 { - unsafe { __crcc_w_b_w(a, b) } -} - -/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn crcc_w_h_w(a: i32, b: i32) -> i32 { - unsafe { __crcc_w_h_w(a, b) } -} - -/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn crcc_w_w_w(a: i32, b: i32) -> i32 { - unsafe { __crcc_w_w_w(a, b) } -} - /// Generates the memory barrier instruction -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn dbar() { static_assert_uimm_bits!(IMM15, 15); @@ -121,7 +67,7 @@ pub fn dbar() { } /// Generates the instruction-fetch barrier instruction -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn ibar() { static_assert_uimm_bits!(IMM15, 15); @@ -129,7 +75,7 @@ pub fn ibar() { } /// Moves data from a GPR to the FCSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn movgr2fcsr(a: i32) { static_assert_uimm_bits!(IMM2, 2); @@ -137,7 +83,7 @@ pub unsafe fn movgr2fcsr(a: i32) { } /// Moves data from a FCSR to the GPR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn movfcsr2gr() -> i32 { static_assert_uimm_bits!(IMM2, 2); @@ -145,49 +91,49 @@ pub fn movfcsr2gr() -> i32 { } /// Reads the 8-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrrd_b(a: i32) -> i32 { __iocsrrd_b(a) } /// Reads the 16-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrrd_h(a: i32) -> i32 { __iocsrrd_h(a) } /// Reads the 32-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrrd_w(a: i32) -> i32 { __iocsrrd_w(a) } /// Writes the 8-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrwr_b(a: i32, b: i32) { __iocsrwr_b(a, b) } /// Writes the 16-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrwr_h(a: i32, b: i32) { __iocsrwr_h(a, b) } /// Writes the 32-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrwr_w(a: i32, b: i32) { __iocsrwr_w(a, b) } /// Generates the breakpoint instruction -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn brk() { static_assert_uimm_bits!(IMM15, 15); @@ -195,14 +141,14 @@ pub unsafe fn brk() { } /// Reads the CPU configuration register -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn cpucfg(a: i32) -> i32 { unsafe { __cpucfg(a) } } /// Generates the syscall instruction -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn syscall() { static_assert_uimm_bits!(IMM15, 15); diff --git a/library/stdarch/crates/core_arch/src/macros.rs b/library/stdarch/crates/core_arch/src/macros.rs index 353829633f018..6a2b62cf3079b 100644 --- a/library/stdarch/crates/core_arch/src/macros.rs +++ b/library/stdarch/crates/core_arch/src/macros.rs @@ -14,6 +14,22 @@ macro_rules! static_assert { }; } +#[allow(unused_macros)] +macro_rules! static_assert_range { + ($imm:ident, $min:literal..=$max:literal) => { + static_assert!( + $min <= $imm && $imm <= $max, + concat!( + stringify!($imm), + " is not in range ", + stringify!($min), + "-", + stringify!($max), + ) + ) + }; +} + #[allow(unused_macros)] macro_rules! static_assert_uimm_bits { ($imm:ident, $bits:expr) => { @@ -26,7 +42,7 @@ macro_rules! static_assert_uimm_bits { stringify!($imm), " doesn't fit in ", stringify!($bits), - " bits", + " bits (unsigned)", ) ) } @@ -42,7 +58,7 @@ macro_rules! static_assert_simm_bits { stringify!($imm), " doesn't fit in ", stringify!($bits), - " bits", + " bits (signed)", ) ) }; @@ -186,3 +202,177 @@ macro_rules! simd_masked_store { $crate::intrinsics::simd::simd_masked_store::<_, _, _, { $align }>($mask, $ptr, $default) }; } + +/// The first N indices `[0, 1, 2, ...]`. +pub(crate) const fn identity() -> [u32; N] { + let mut out = [0u32; N]; + let mut i = 0usize; + while i < N { + out[i] = i as u32; + i += 1; + } + out +} + +/// The first N even indices `[0, 2, 4, ...]`. +pub(crate) const fn even() -> [u32; N] { + let mut out = [0u32; N]; + let mut i = 0usize; + while i < N { + out[i] = (2 * i) as u32; + i += 1; + } + out +} + +/// The first N odd indices `[1, 3, 5, ...]`. +pub(crate) const fn odd() -> [u32; N] { + let mut out = [0u32; N]; + let mut i = 0usize; + while i < N { + out[i] = (2 * i + 1) as u32; + i += 1; + } + out +} + +/// Multiples of N offset by K `[K, K+N, K+2N, ...]`. +pub(crate) const fn deinterleave_mask() +-> [u32; LANES] { + let mut out = [0u32; LANES]; + let mut i = 0usize; + while i < LANES { + out[i] = (i * N + K) as u32; + i += 1; + } + out +} + +#[allow(unused)] +macro_rules! deinterleaving_load { + ($elem:ty, $lanes:literal, 2, $ptr:expr) => {{ + use $crate::core_arch::macros::deinterleave_mask; + use $crate::core_arch::simd::Simd; + use $crate::mem::transmute; + + type V = Simd<$elem, $lanes>; + type W = Simd<$elem, { $lanes * 2 }>; + + let w: W = $crate::ptr::read_unaligned($ptr as *const W); + + let v0: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 2, 0>()); + let v1: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 2, 1>()); + + transmute((v0, v1)) + }}; + + // N = 3 + ($elem:ty, $lanes:literal, 3, $ptr:expr) => {{ + use $crate::core_arch::macros::deinterleave_mask; + use $crate::core_arch::simd::Simd; + use $crate::mem::transmute; + + type V = Simd<$elem, $lanes>; + type Arr = [$elem; { $lanes * 3 }]; + + // NOTE: copy_nonoverlapping requires both pointers to be aligned to at least align_of::<$elem>(), + // passing a pointer that is not sufficiently aligned is an UB. + let arr: Arr = $crate::ptr::read_unaligned($ptr as *const [$elem; { $lanes * 3 }]); + // NOTE: repr(simd) adds padding to make the total size a power of two. + // Hence reading a W from ptr might read out of bounds. + type W = Simd<$elem, { $lanes * 3 }>; + let w: W = W::from_array(arr); + + let v0: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 3, 0>()); + let v1: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 3, 1>()); + let v2: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 3, 2>()); + + transmute((v0, v1, v2)) + }}; + + // N = 4 + ($elem:ty, $lanes:literal, 4, $ptr:expr) => {{ + use $crate::core_arch::macros::deinterleave_mask; + use $crate::core_arch::simd::Simd; + use $crate::mem::transmute; + + type V = Simd<$elem, $lanes>; + type W = Simd<$elem, { $lanes * 4 }>; + + let w: W = $crate::ptr::read_unaligned($ptr as *const W); + + let v0: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 4, 0>()); + let v1: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 4, 1>()); + let v2: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 4, 2>()); + let v3: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 4, 3>()); + + transmute((v0, v1, v2, v3)) + }}; +} + +#[allow(unused)] +pub(crate) use deinterleaving_load; + +pub(crate) const fn interleave_mask() +-> [u32; LANES] { + let mut out = [0u32; LANES]; + let mut j = 0usize; + while j < LANES { + out[j] = ((j % K) * N + j / K) as u32; + j += 1; + } + out +} + +#[allow(unused)] +macro_rules! interleaving_store { + ($elem:ty, $lanes:literal, 2, $ptr:expr, $v:expr) => {{ + use $crate::core_arch::macros::interleave_mask; + use $crate::core_arch::simd::Simd; + + type W = Simd<$elem, { $lanes * 2 }>; + let w: W = simd_shuffle!($v.0, $v.1, interleave_mask::<{ $lanes * 2 }, $lanes, 2>()); + $crate::ptr::write_unaligned($ptr as *mut W, w); + }}; + + // N = 3 + ($elem:ty, $lanes:literal, 3, $ptr:expr, $v:expr) => {{ + use $crate::core_arch::macros::{identity, interleave_mask}; + use $crate::core_arch::simd::Simd; + + let v0v1: Simd<$elem, { $lanes * 2 }> = + simd_shuffle!($v.0, $v.1, identity::<{ $lanes * 2 }>()); + let v2v2: Simd<$elem, { $lanes * 2 }> = + simd_shuffle!($v.2, $v.2, identity::<{ $lanes * 2 }>()); + + // NOTE: repr(simd) adds padding to make the total size a power of two. + // Hence writing W to ptr might write out of bounds. + type W = Simd<$elem, { $lanes * 3 }>; + + let w: W = simd_shuffle!(v0v1, v2v2, interleave_mask::<{ $lanes * 3 }, $lanes, 3>()); + + let arr: [$elem; { $lanes * 3 }] = $crate::mem::transmute_copy(&w); + + // NOTE: copy_nonoverlapping requires both pointers to be aligned to at least align_of::<$elem>(), + // passing a pointer that is not sufficiently aligned is an UB. + $ptr.cast::<[$elem; { $lanes * 3 }]>().write_unaligned(arr); + }}; + + // N = 4 + ($elem:ty, $lanes:literal, 4, $ptr:expr, $v:expr) => {{ + use $crate::core_arch::macros::{identity, interleave_mask}; + use $crate::core_arch::simd::Simd; + + let v0v1: Simd<$elem, { $lanes * 2 }> = + simd_shuffle!($v.0, $v.1, identity::<{ $lanes * 2 }>()); + let v2v3: Simd<$elem, { $lanes * 2 }> = + simd_shuffle!($v.2, $v.3, identity::<{ $lanes * 2 }>()); + + type W = Simd<$elem, { $lanes * 4 }>; + let w: W = simd_shuffle!(v0v1, v2v3, interleave_mask::<{ $lanes * 4 }, $lanes, 4>()); + $crate::ptr::write_unaligned($ptr as *mut W, w); + }}; +} + +#[allow(unused)] +pub(crate) use interleaving_store; diff --git a/library/stdarch/crates/core_arch/src/mips/msa.rs b/library/stdarch/crates/core_arch/src/mips/msa.rs index 563e121a7badb..dab64319ccc3b 100644 --- a/library/stdarch/crates/core_arch/src/mips/msa.rs +++ b/library/stdarch/crates/core_arch/src/mips/msa.rs @@ -45,7 +45,7 @@ types! { } #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.mips.add.a.b"] fn msa_add_a_b(a: v16i8, b: v16i8) -> v16i8; #[link_name = "llvm.mips.add.a.h"] @@ -1407,7 +1407,7 @@ pub unsafe fn __msa_addv_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(addvi.b, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(addvi.b, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_addvi_b(a: v16i8) -> v16i8 { @@ -1423,7 +1423,7 @@ pub unsafe fn __msa_addvi_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(addvi.h, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(addvi.h, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_addvi_h(a: v8i16) -> v8i16 { @@ -1439,7 +1439,7 @@ pub unsafe fn __msa_addvi_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(addvi.w, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(addvi.w, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_addvi_w(a: v4i32) -> v4i32 { @@ -1455,7 +1455,7 @@ pub unsafe fn __msa_addvi_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(addvi.d, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(addvi.d, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_addvi_d(a: v2i64) -> v2i64 { @@ -1486,7 +1486,7 @@ pub unsafe fn __msa_and_v(a: v16u8, b: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(andi.b, imm8 = 0b10010111))] +#[cfg_attr(test, assert_instr(andi.b, IMM8 = 0b10010111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_andi_b(a: v16u8) -> v16u8 { @@ -1938,7 +1938,7 @@ pub unsafe fn __msa_bclr_d(a: v2u64, b: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bclri.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(bclri.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bclri_b(a: v16u8) -> v16u8 { @@ -1954,7 +1954,7 @@ pub unsafe fn __msa_bclri_b(a: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bclri.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(bclri.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bclri_h(a: v8u16) -> v8u16 { @@ -1970,7 +1970,7 @@ pub unsafe fn __msa_bclri_h(a: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bclri.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(bclri.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bclri_w(a: v4u32) -> v4u32 { @@ -1986,7 +1986,7 @@ pub unsafe fn __msa_bclri_w(a: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bclri.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(bclri.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bclri_d(a: v2u64) -> v2u64 { @@ -2062,7 +2062,7 @@ pub unsafe fn __msa_binsl_d(a: v2u64, b: v2u64, c: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsli.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(binsli.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsli_b(a: v16u8, b: v16u8) -> v16u8 { @@ -2078,7 +2078,7 @@ pub unsafe fn __msa_binsli_b(a: v16u8, b: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsli.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(binsli.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsli_h(a: v8u16, b: v8u16) -> v8u16 { @@ -2094,7 +2094,7 @@ pub unsafe fn __msa_binsli_h(a: v8u16, b: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsli.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(binsli.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsli_w(a: v4u32, b: v4u32) -> v4u32 { @@ -2110,7 +2110,7 @@ pub unsafe fn __msa_binsli_w(a: v4u32, b: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsli.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(binsli.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsli_d(a: v2u64, b: v2u64) -> v2u64 { @@ -2186,7 +2186,7 @@ pub unsafe fn __msa_binsr_d(a: v2u64, b: v2u64, c: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsri.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(binsri.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsri_b(a: v16u8, b: v16u8) -> v16u8 { @@ -2202,7 +2202,7 @@ pub unsafe fn __msa_binsri_b(a: v16u8, b: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsri.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(binsri.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsri_h(a: v8u16, b: v8u16) -> v8u16 { @@ -2218,7 +2218,7 @@ pub unsafe fn __msa_binsri_h(a: v8u16, b: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsri.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(binsri.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsri_w(a: v4u32, b: v4u32) -> v4u32 { @@ -2234,7 +2234,7 @@ pub unsafe fn __msa_binsri_w(a: v4u32, b: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsri.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(binsri.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsri_d(a: v2u64, b: v2u64) -> v2u64 { @@ -2265,7 +2265,7 @@ pub unsafe fn __msa_bmnz_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bmnzi.b, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(bmnzi.b, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bmnzi_b(a: v16u8, b: v16u8) -> v16u8 { @@ -2296,7 +2296,7 @@ pub unsafe fn __msa_bmz_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bmzi.b, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(bmzi.b, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bmzi_b(a: v16u8, b: v16u8) -> v16u8 { @@ -2372,7 +2372,7 @@ pub unsafe fn __msa_bneg_d(a: v2u64, b: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bnegi.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(bnegi.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bnegi_b(a: v16u8) -> v16u8 { @@ -2388,7 +2388,7 @@ pub unsafe fn __msa_bnegi_b(a: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bnegi.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(bnegi.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bnegi_h(a: v8u16) -> v8u16 { @@ -2404,7 +2404,7 @@ pub unsafe fn __msa_bnegi_h(a: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bnegi.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(bnegi.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bnegi_w(a: v4u32) -> v4u32 { @@ -2420,7 +2420,7 @@ pub unsafe fn __msa_bnegi_w(a: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bnegi.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(bnegi.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bnegi_d(a: v2u64) -> v2u64 { @@ -2512,7 +2512,7 @@ pub unsafe fn __msa_bsel_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bseli.b, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(bseli.b, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bseli_b(a: v16u8, b: v16u8) -> v16u8 { @@ -2588,7 +2588,7 @@ pub unsafe fn __msa_bset_d(a: v2u64, b: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bseti.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(bseti.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bseti_b(a: v16u8) -> v16u8 { @@ -2604,7 +2604,7 @@ pub unsafe fn __msa_bseti_b(a: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bseti.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(bseti.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bseti_h(a: v8u16) -> v8u16 { @@ -2620,7 +2620,7 @@ pub unsafe fn __msa_bseti_h(a: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bseti.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(bseti.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bseti_w(a: v4u32) -> v4u32 { @@ -2636,7 +2636,7 @@ pub unsafe fn __msa_bseti_w(a: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bseti.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(bseti.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bseti_d(a: v2u64) -> v2u64 { @@ -2769,7 +2769,7 @@ pub unsafe fn __msa_ceq_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ceqi.b, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(ceqi.b, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ceqi_b(a: v16i8) -> v16i8 { @@ -2785,7 +2785,7 @@ pub unsafe fn __msa_ceqi_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ceqi.h, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(ceqi.h, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ceqi_h(a: v8i16) -> v8i16 { @@ -2801,7 +2801,7 @@ pub unsafe fn __msa_ceqi_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ceqi.w, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(ceqi.w, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ceqi_w(a: v4i32) -> v4i32 { @@ -2817,7 +2817,7 @@ pub unsafe fn __msa_ceqi_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ceqi.d, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(ceqi.d, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ceqi_d(a: v2i64) -> v2i64 { @@ -2832,7 +2832,7 @@ pub unsafe fn __msa_ceqi_d(a: v2i64) -> v2i64 { /// Can not be tested in user mode #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(cfcmsa, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(cfcmsa, IMM5 = 0b11111))] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_cfcmsa() -> i32 { @@ -2969,7 +2969,7 @@ pub unsafe fn __msa_cle_u_d(a: v2u64, b: v2u64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_s.b, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(clei_s.b, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_s_b(a: v16i8) -> v16i8 { @@ -2986,7 +2986,7 @@ pub unsafe fn __msa_clei_s_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_s.h, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(clei_s.h, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_s_h(a: v8i16) -> v8i16 { @@ -3003,7 +3003,7 @@ pub unsafe fn __msa_clei_s_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_s.w, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(clei_s.w, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_s_w(a: v4i32) -> v4i32 { @@ -3020,7 +3020,7 @@ pub unsafe fn __msa_clei_s_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_s.d, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(clei_s.d, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_s_d(a: v2i64) -> v2i64 { @@ -3037,7 +3037,7 @@ pub unsafe fn __msa_clei_s_d(a: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_u.b, imm5 = 0b111))] +#[cfg_attr(test, assert_instr(clei_u.b, IMM5 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_u_b(a: v16u8) -> v16i8 { @@ -3054,7 +3054,7 @@ pub unsafe fn __msa_clei_u_b(a: v16u8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_u.h, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(clei_u.h, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_u_h(a: v8u16) -> v8i16 { @@ -3071,7 +3071,7 @@ pub unsafe fn __msa_clei_u_h(a: v8u16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_u.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(clei_u.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_u_w(a: v4u32) -> v4i32 { @@ -3088,7 +3088,7 @@ pub unsafe fn __msa_clei_u_w(a: v4u32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_u.d, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(clei_u.d, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_u_d(a: v2u64) -> v2i64 { @@ -3225,7 +3225,7 @@ pub unsafe fn __msa_clt_u_d(a: v2u64, b: v2u64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_s.b, imm_s5 = 0b111))] +#[cfg_attr(test, assert_instr(clti_s.b, IMM_S5 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_s_b(a: v16i8) -> v16i8 { @@ -3242,7 +3242,7 @@ pub unsafe fn __msa_clti_s_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_s.h, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(clti_s.h, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_s_h(a: v8i16) -> v8i16 { @@ -3259,7 +3259,7 @@ pub unsafe fn __msa_clti_s_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_s.w, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(clti_s.w, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_s_w(a: v4i32) -> v4i32 { @@ -3276,7 +3276,7 @@ pub unsafe fn __msa_clti_s_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_s.d, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(clti_s.d, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_s_d(a: v2i64) -> v2i64 { @@ -3293,7 +3293,7 @@ pub unsafe fn __msa_clti_s_d(a: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_u.b, imm5 = 0b111))] +#[cfg_attr(test, assert_instr(clti_u.b, IMM5 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_u_b(a: v16u8) -> v16i8 { @@ -3310,7 +3310,7 @@ pub unsafe fn __msa_clti_u_b(a: v16u8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_u.h, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(clti_u.h, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_u_h(a: v8u16) -> v8i16 { @@ -3327,7 +3327,7 @@ pub unsafe fn __msa_clti_u_h(a: v8u16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_u.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(clti_u.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_u_w(a: v4u32) -> v4i32 { @@ -3344,7 +3344,7 @@ pub unsafe fn __msa_clti_u_w(a: v4u32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_u.d, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(clti_u.d, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_u_d(a: v2u64) -> v2i64 { @@ -3359,7 +3359,7 @@ pub unsafe fn __msa_clti_u_d(a: v2u64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_s.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(copy_s.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_s_b(a: v16i8) -> i32 { @@ -3374,7 +3374,7 @@ pub unsafe fn __msa_copy_s_b(a: v16i8) -> i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_s.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(copy_s.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_s_h(a: v8i16) -> i32 { @@ -3389,7 +3389,7 @@ pub unsafe fn __msa_copy_s_h(a: v8i16) -> i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_s.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(copy_s.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_s_w(a: v4i32) -> i32 { @@ -3404,7 +3404,7 @@ pub unsafe fn __msa_copy_s_w(a: v4i32) -> i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_s.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(copy_s.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_s_d(a: v2i64) -> i64 { @@ -3419,7 +3419,7 @@ pub unsafe fn __msa_copy_s_d(a: v2i64) -> i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_u.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(copy_u.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_u_b(a: v16i8) -> u32 { @@ -3434,7 +3434,7 @@ pub unsafe fn __msa_copy_u_b(a: v16i8) -> u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_u.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(copy_u.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_u_h(a: v8i16) -> u32 { @@ -3449,7 +3449,7 @@ pub unsafe fn __msa_copy_u_h(a: v8i16) -> u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_u.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(copy_u.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_u_w(a: v4i32) -> u32 { @@ -3464,7 +3464,7 @@ pub unsafe fn __msa_copy_u_w(a: v4i32) -> u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_u.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(copy_u.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_u_d(a: v2i64) -> u64 { @@ -3481,7 +3481,7 @@ pub unsafe fn __msa_copy_u_d(a: v2i64) -> u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ctcmsa, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(ctcmsa, IMM5 = 0b1))] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ctcmsa(a: i32) -> () { @@ -5855,7 +5855,7 @@ pub unsafe fn __msa_ilvr_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insert.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(insert.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insert_b(a: v16i8, c: i32) -> v16i8 { @@ -5871,7 +5871,7 @@ pub unsafe fn __msa_insert_b(a: v16i8, c: i32) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insert.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(insert.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insert_h(a: v8i16, c: i32) -> v8i16 { @@ -5887,7 +5887,7 @@ pub unsafe fn __msa_insert_h(a: v8i16, c: i32) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insert.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(insert.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insert_w(a: v4i32, c: i32) -> v4i32 { @@ -5903,7 +5903,7 @@ pub unsafe fn __msa_insert_w(a: v4i32, c: i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insert.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(insert.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insert_d(a: v2i64, c: i64) -> v2i64 { @@ -5919,7 +5919,7 @@ pub unsafe fn __msa_insert_d(a: v2i64, c: i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insve.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(insve.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insve_b(a: v16i8, c: v16i8) -> v16i8 { @@ -5935,7 +5935,7 @@ pub unsafe fn __msa_insve_b(a: v16i8, c: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insve.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(insve.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insve_h(a: v8i16, c: v8i16) -> v8i16 { @@ -5951,7 +5951,7 @@ pub unsafe fn __msa_insve_h(a: v8i16, c: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insve.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(insve.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insve_w(a: v4i32, c: v4i32) -> v4i32 { @@ -5967,7 +5967,7 @@ pub unsafe fn __msa_insve_w(a: v4i32, c: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insve.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(insve.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insve_d(a: v2i64, c: v2i64) -> v2i64 { @@ -5983,7 +5983,7 @@ pub unsafe fn __msa_insve_d(a: v2i64, c: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ld.b, imm_s10 = 0b1111111111))] +#[cfg_attr(test, assert_instr(ld.b, IMM_S10 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ld_b(mem_addr: *mut u8) -> v16i8 { @@ -5999,7 +5999,7 @@ pub unsafe fn __msa_ld_b(mem_addr: *mut u8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ld.h, imm_s11 = 0b11111111111))] +#[cfg_attr(test, assert_instr(ld.h, IMM_S11 = -2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ld_h(mem_addr: *mut u8) -> v8i16 { @@ -6016,7 +6016,7 @@ pub unsafe fn __msa_ld_h(mem_addr: *mut u8) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ld.w, imm_s12 = 0b111111111111))] +#[cfg_attr(test, assert_instr(ld.w, IMM_S12 = -4))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ld_w(mem_addr: *mut u8) -> v4i32 { @@ -6033,7 +6033,7 @@ pub unsafe fn __msa_ld_w(mem_addr: *mut u8) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ld.d, imm_s13 = 0b1111111111111))] +#[cfg_attr(test, assert_instr(ld.d, IMM_S13 = -8))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ld_d(mem_addr: *mut u8) -> v2i64 { @@ -6050,7 +6050,7 @@ pub unsafe fn __msa_ld_d(mem_addr: *mut u8) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ldi.b, imm_s10 = 0b1111111111))] +#[cfg_attr(test, assert_instr(ldi.b, IMM_S10 = -1))] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ldi_b() -> v16i8 { @@ -6066,7 +6066,7 @@ pub unsafe fn __msa_ldi_b() -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ldi.h, imm_s10 = 0b1111111111))] +#[cfg_attr(test, assert_instr(ldi.h, IMM_S10 = -1))] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ldi_h() -> v8i16 { @@ -6082,7 +6082,7 @@ pub unsafe fn __msa_ldi_h() -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ldi.w, imm_s10 = 0b1111111111))] +#[cfg_attr(test, assert_instr(ldi.w, IMM_S10 = -1))] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ldi_w() -> v4i32 { @@ -6098,7 +6098,7 @@ pub unsafe fn __msa_ldi_w() -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ldi.d, imm_s10 = 0b1111111111))] +#[cfg_attr(test, assert_instr(ldi.d, IMM_S10 = -1))] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ldi_d() -> v2i64 { @@ -6410,7 +6410,7 @@ pub unsafe fn __msa_max_u_d(a: v2u64, b: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_s.b, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_s.b, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_s_b(a: v16i8) -> v16i8 { @@ -6426,7 +6426,7 @@ pub unsafe fn __msa_maxi_s_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_s.h, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_s.h, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_s_h(a: v8i16) -> v8i16 { @@ -6442,7 +6442,7 @@ pub unsafe fn __msa_maxi_s_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_s.w, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_s.w, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_s_w(a: v4i32) -> v4i32 { @@ -6458,7 +6458,7 @@ pub unsafe fn __msa_maxi_s_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_s.d, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_s.d, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_s_d(a: v2i64) -> v2i64 { @@ -6474,7 +6474,7 @@ pub unsafe fn __msa_maxi_s_d(a: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_u.b, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_u.b, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_u_b(a: v16u8) -> v16u8 { @@ -6490,7 +6490,7 @@ pub unsafe fn __msa_maxi_u_b(a: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_u.h, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_u.h, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_u_h(a: v8u16) -> v8u16 { @@ -6506,7 +6506,7 @@ pub unsafe fn __msa_maxi_u_h(a: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_u.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_u.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_u_w(a: v4u32) -> v4u32 { @@ -6522,7 +6522,7 @@ pub unsafe fn __msa_maxi_u_w(a: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_u.d, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_u.d, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_u_d(a: v2u64) -> v2u64 { @@ -6654,7 +6654,7 @@ pub unsafe fn __msa_min_s_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_s.b, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_s.b, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_s_b(a: v16i8) -> v16i8 { @@ -6670,7 +6670,7 @@ pub unsafe fn __msa_mini_s_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_s.h, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_s.h, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_s_h(a: v8i16) -> v8i16 { @@ -6686,7 +6686,7 @@ pub unsafe fn __msa_mini_s_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_s.w, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_s.w, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_s_w(a: v4i32) -> v4i32 { @@ -6702,7 +6702,7 @@ pub unsafe fn __msa_mini_s_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_s.d, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_s.d, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_s_d(a: v2i64) -> v2i64 { @@ -6774,7 +6774,7 @@ pub unsafe fn __msa_min_u_d(a: v2u64, b: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_u.b, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_u.b, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_u_b(a: v16u8) -> v16u8 { @@ -6790,7 +6790,7 @@ pub unsafe fn __msa_mini_u_b(a: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_u.h, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_u.h, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_u_h(a: v8u16) -> v8u16 { @@ -6806,7 +6806,7 @@ pub unsafe fn __msa_mini_u_h(a: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_u.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_u.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_u_w(a: v4u32) -> v4u32 { @@ -6822,7 +6822,7 @@ pub unsafe fn __msa_mini_u_w(a: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_u.d, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_u.d, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_u_d(a: v2u64) -> v2u64 { @@ -7343,7 +7343,7 @@ pub unsafe fn __msa_nor_v(a: v16u8, b: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(nori.b, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(nori.b, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_nori_b(a: v16u8) -> v16u8 { @@ -7375,7 +7375,7 @@ pub unsafe fn __msa_or_v(a: v16u8, b: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ori.b, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(ori.b, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ori_b(a: v16u8) -> v16u8 { @@ -7555,7 +7555,7 @@ pub unsafe fn __msa_pcnt_d(a: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_s.b, imm4 = 0b111))] +#[cfg_attr(test, assert_instr(sat_s.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_s_b(a: v16i8) -> v16i8 { @@ -7571,7 +7571,7 @@ pub unsafe fn __msa_sat_s_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_s.h, imm3 = 0b1111))] +#[cfg_attr(test, assert_instr(sat_s.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_s_h(a: v8i16) -> v8i16 { @@ -7587,7 +7587,7 @@ pub unsafe fn __msa_sat_s_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_s.w, imm2 = 0b11111))] +#[cfg_attr(test, assert_instr(sat_s.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_s_w(a: v4i32) -> v4i32 { @@ -7603,7 +7603,7 @@ pub unsafe fn __msa_sat_s_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_s.d, imm1 = 0b111111))] +#[cfg_attr(test, assert_instr(sat_s.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_s_d(a: v2i64) -> v2i64 { @@ -7619,7 +7619,7 @@ pub unsafe fn __msa_sat_s_d(a: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_u.b, imm4 = 0b111))] +#[cfg_attr(test, assert_instr(sat_u.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_u_b(a: v16u8) -> v16u8 { @@ -7635,7 +7635,7 @@ pub unsafe fn __msa_sat_u_b(a: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_u.h, imm3 = 0b1111))] +#[cfg_attr(test, assert_instr(sat_u.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_u_h(a: v8u16) -> v8u16 { @@ -7651,7 +7651,7 @@ pub unsafe fn __msa_sat_u_h(a: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_u.w, imm2 = 0b11111))] +#[cfg_attr(test, assert_instr(sat_u.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_u_w(a: v4u32) -> v4u32 { @@ -7667,7 +7667,7 @@ pub unsafe fn __msa_sat_u_w(a: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_u.d, imm1 = 0b111111))] +#[cfg_attr(test, assert_instr(sat_u.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_u_d(a: v2u64) -> v2u64 { @@ -7684,7 +7684,7 @@ pub unsafe fn __msa_sat_u_d(a: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(shf.b, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(shf.b, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_shf_b(a: v16i8) -> v16i8 { @@ -7701,7 +7701,7 @@ pub unsafe fn __msa_shf_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(shf.h, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(shf.h, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_shf_h(a: v8i16) -> v8i16 { @@ -7718,7 +7718,7 @@ pub unsafe fn __msa_shf_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(shf.w, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(shf.w, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_shf_w(a: v4i32) -> v4i32 { @@ -7823,7 +7823,7 @@ pub unsafe fn __msa_sld_d(a: v2i64, b: v2i64, c: i32) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sldi.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(sldi.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sldi_b(a: v16i8, b: v16i8) -> v16i8 { @@ -7844,7 +7844,7 @@ pub unsafe fn __msa_sldi_b(a: v16i8, b: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sldi.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(sldi.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sldi_h(a: v8i16, b: v8i16) -> v8i16 { @@ -7865,7 +7865,7 @@ pub unsafe fn __msa_sldi_h(a: v8i16, b: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sldi.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(sldi.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sldi_w(a: v4i32, b: v4i32) -> v4i32 { @@ -7886,7 +7886,7 @@ pub unsafe fn __msa_sldi_w(a: v4i32, b: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sldi.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(sldi.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sldi_d(a: v2i64, b: v2i64) -> v2i64 { @@ -7962,7 +7962,7 @@ pub unsafe fn __msa_sll_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(slli.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(slli.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_slli_b(a: v16i8) -> v16i8 { @@ -7978,7 +7978,7 @@ pub unsafe fn __msa_slli_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(slli.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(slli.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_slli_h(a: v8i16) -> v8i16 { @@ -7994,7 +7994,7 @@ pub unsafe fn __msa_slli_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(slli.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(slli.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_slli_w(a: v4i32) -> v4i32 { @@ -8010,7 +8010,7 @@ pub unsafe fn __msa_slli_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(slli.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(slli.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_slli_d(a: v2i64) -> v2i64 { @@ -8085,7 +8085,7 @@ pub unsafe fn __msa_splat_d(a: v2i64, b: i32) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(splati.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(splati.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_splati_b(a: v16i8) -> v16i8 { @@ -8100,7 +8100,7 @@ pub unsafe fn __msa_splati_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(splati.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(splati.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_splati_h(a: v8i16) -> v8i16 { @@ -8115,7 +8115,7 @@ pub unsafe fn __msa_splati_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(splati.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(splati.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_splati_w(a: v4i32) -> v4i32 { @@ -8130,7 +8130,7 @@ pub unsafe fn __msa_splati_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(splati.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(splati.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_splati_d(a: v2i64) -> v2i64 { @@ -8206,7 +8206,7 @@ pub unsafe fn __msa_sra_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srai.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(srai.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srai_b(a: v16i8) -> v16i8 { @@ -8222,7 +8222,7 @@ pub unsafe fn __msa_srai_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srai.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(srai.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srai_h(a: v8i16) -> v8i16 { @@ -8238,7 +8238,7 @@ pub unsafe fn __msa_srai_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srai.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(srai.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srai_w(a: v4i32) -> v4i32 { @@ -8254,7 +8254,7 @@ pub unsafe fn __msa_srai_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srai.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(srai.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srai_d(a: v2i64) -> v2i64 { @@ -8335,7 +8335,7 @@ pub unsafe fn __msa_srar_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srari.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(srari.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srari_b(a: v16i8) -> v16i8 { @@ -8352,7 +8352,7 @@ pub unsafe fn __msa_srari_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srari.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(srari.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srari_h(a: v8i16) -> v8i16 { @@ -8369,7 +8369,7 @@ pub unsafe fn __msa_srari_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srari.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(srari.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srari_w(a: v4i32) -> v4i32 { @@ -8386,7 +8386,7 @@ pub unsafe fn __msa_srari_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srari.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(srari.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srari_d(a: v2i64) -> v2i64 { @@ -8462,7 +8462,7 @@ pub unsafe fn __msa_srl_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srli.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(srli.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srli_b(a: v16i8) -> v16i8 { @@ -8478,7 +8478,7 @@ pub unsafe fn __msa_srli_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srli.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(srli.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srli_h(a: v8i16) -> v8i16 { @@ -8494,7 +8494,7 @@ pub unsafe fn __msa_srli_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srli.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(srli.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srli_w(a: v4i32) -> v4i32 { @@ -8510,7 +8510,7 @@ pub unsafe fn __msa_srli_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srli.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(srli.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srli_d(a: v2i64) -> v2i64 { @@ -8591,7 +8591,7 @@ pub unsafe fn __msa_srlr_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srlri.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(srlri.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srlri_b(a: v16i8) -> v16i8 { @@ -8608,7 +8608,7 @@ pub unsafe fn __msa_srlri_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srlri.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(srlri.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srlri_h(a: v8i16) -> v8i16 { @@ -8625,7 +8625,7 @@ pub unsafe fn __msa_srlri_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srlri.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(srlri.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srlri_w(a: v4i32) -> v4i32 { @@ -8642,7 +8642,7 @@ pub unsafe fn __msa_srlri_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srlri.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(srlri.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srlri_d(a: v2i64) -> v2i64 { @@ -8658,7 +8658,7 @@ pub unsafe fn __msa_srlri_d(a: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(st.b, imm_s10 = 0b1111111111))] +#[cfg_attr(test, assert_instr(st.b, IMM_S10 = -1))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_st_b(a: v16i8, mem_addr: *mut u8) -> () { @@ -8674,7 +8674,7 @@ pub unsafe fn __msa_st_b(a: v16i8, mem_addr: *mut u8) -> () /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(st.h, imm_s11 = 0b11111111111))] +#[cfg_attr(test, assert_instr(st.h, IMM_S11 = -2))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_st_h(a: v8i16, mem_addr: *mut u8) -> () { @@ -8691,7 +8691,7 @@ pub unsafe fn __msa_st_h(a: v8i16, mem_addr: *mut u8) -> () /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(st.w, imm_s12 = 0b111111111111))] +#[cfg_attr(test, assert_instr(st.w, IMM_S12 = -4))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_st_w(a: v4i32, mem_addr: *mut u8) -> () { @@ -8708,7 +8708,7 @@ pub unsafe fn __msa_st_w(a: v4i32, mem_addr: *mut u8) -> () /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(st.d, imm_s13 = 0b1111111111111))] +#[cfg_attr(test, assert_instr(st.d, IMM_S13 = -8))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_st_d(a: v2i64, mem_addr: *mut u8) -> () { @@ -9021,7 +9021,7 @@ pub unsafe fn __msa_subv_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(subvi.b, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(subvi.b, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_subvi_b(a: v16i8) -> v16i8 { @@ -9037,7 +9037,7 @@ pub unsafe fn __msa_subvi_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(subvi.h, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(subvi.h, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_subvi_h(a: v8i16) -> v8i16 { @@ -9053,7 +9053,7 @@ pub unsafe fn __msa_subvi_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(subvi.w, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(subvi.w, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_subvi_w(a: v4i32) -> v4i32 { @@ -9069,7 +9069,7 @@ pub unsafe fn __msa_subvi_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(subvi.d, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(subvi.d, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_subvi_d(a: v2i64) -> v2i64 { @@ -9173,7 +9173,7 @@ pub unsafe fn __msa_xor_v(a: v16u8, b: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(xori.b, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(xori.b, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_xori_b(a: v16u8) -> v16u8 { @@ -9187,7 +9187,6 @@ mod tests { core_arch::{mips::msa::*, simd::*}, mem, }; - use std::{f32, f64}; use stdarch_test::simd_test; #[simd_test(enable = "msa")] @@ -9603,7 +9602,7 @@ mod tests { 103, -126, 103, -126 ); - assert_eq!(r, mem::transmute(__msa_addvi_b(mem::transmute(a), 67))); + assert_eq!(r, mem::transmute(__msa_addvi_b::<3>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -9619,7 +9618,7 @@ mod tests { -32766, 3279, -97, -124 ); - assert_eq!(r, mem::transmute(__msa_addvi_h(mem::transmute(a), 67))); + assert_eq!(r, mem::transmute(__msa_addvi_h::<3>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -9629,7 +9628,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(103, -2147483646, 103, -2147483645); - assert_eq!(r, mem::transmute(__msa_addvi_w(mem::transmute(a), 67))); + assert_eq!(r, mem::transmute(__msa_addvi_w::<3>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -9639,7 +9638,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(117, -9223372036854775791); - assert_eq!(r, mem::transmute(__msa_addvi_d(mem::transmute(a), 17))); + assert_eq!(r, mem::transmute(__msa_addvi_d::<17>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -9689,7 +9688,7 @@ mod tests { 4, 5, 4, 5 ); - assert_eq!(r, mem::transmute(__msa_andi_b(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_andi_b::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10234,7 +10233,7 @@ mod tests { 247, 147, 55, 1 ); - assert_eq!(r, mem::transmute(__msa_bclri_b(mem::transmute(a), 3))); + assert_eq!(r, mem::transmute(__msa_bclri_b::<3>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10244,7 +10243,7 @@ mod tests { #[rustfmt::skip] let r = u16x8::new(107, 1155, 155, 1, 107, 1155, 155, 1); - assert_eq!(r, mem::transmute(__msa_bclri_h(mem::transmute(a), 11))); + assert_eq!(r, mem::transmute(__msa_bclri_h::<11>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10254,7 +10253,7 @@ mod tests { #[rustfmt::skip] let r = u32x4::new(202722547, 102722547, 2722547, 1); - assert_eq!(r, mem::transmute(__msa_bclri_w(mem::transmute(a), 23))); + assert_eq!(r, mem::transmute(__msa_bclri_w::<23>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10264,7 +10263,7 @@ mod tests { #[rustfmt::skip] let r = u64x2::new(73672157683, 11110973672157683); - assert_eq!(r, mem::transmute(__msa_bclri_d(mem::transmute(a), 37))); + assert_eq!(r, mem::transmute(__msa_bclri_d::<37>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10409,7 +10408,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_binsli_b(mem::transmute(a), mem::transmute(b), 5)) + mem::transmute(__msa_binsli_b::<5>(mem::transmute(a), mem::transmute(b))) ); } @@ -10433,7 +10432,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_binsli_h(mem::transmute(a), mem::transmute(b), 13)) + mem::transmute(__msa_binsli_h::<13>(mem::transmute(a), mem::transmute(b))) ); } @@ -10448,7 +10447,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_binsli_w(mem::transmute(a), mem::transmute(b), 17)) + mem::transmute(__msa_binsli_w::<17>(mem::transmute(a), mem::transmute(b))) ); } @@ -10463,7 +10462,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_binsli_d(mem::transmute(a), mem::transmute(b), 48)) + mem::transmute(__msa_binsli_d::<48>(mem::transmute(a), mem::transmute(b))) ); } @@ -10609,7 +10608,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_binsri_b(mem::transmute(a), mem::transmute(b), 5)) + mem::transmute(__msa_binsri_b::<5>(mem::transmute(a), mem::transmute(b))) ); } @@ -10633,7 +10632,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_binsri_h(mem::transmute(a), mem::transmute(b), 13)) + mem::transmute(__msa_binsri_h::<13>(mem::transmute(a), mem::transmute(b))) ); } @@ -10648,7 +10647,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_binsri_w(mem::transmute(a), mem::transmute(b), 17)) + mem::transmute(__msa_binsri_w::<17>(mem::transmute(a), mem::transmute(b))) ); } @@ -10663,7 +10662,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_binsri_d(mem::transmute(a), mem::transmute(b), 48)) + mem::transmute(__msa_binsri_d::<48>(mem::transmute(a), mem::transmute(b))) ); } @@ -10734,7 +10733,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_bmnzi_b(mem::transmute(a), mem::transmute(b), 7)) + mem::transmute(__msa_bmnzi_b::<7>(mem::transmute(a), mem::transmute(b))) ); } @@ -10805,7 +10804,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_bmzi_b(mem::transmute(a), mem::transmute(b), 7)) + mem::transmute(__msa_bmzi_b::<7>(mem::transmute(a), mem::transmute(b))) ); } @@ -10901,7 +10900,7 @@ mod tests { 34, 116, 111, 239 ); - assert_eq!(r, mem::transmute(__msa_bnegi_b(mem::transmute(a), 4))); + assert_eq!(r, mem::transmute(__msa_bnegi_b::<4>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10917,7 +10916,7 @@ mod tests { 30719, 1228, 2148, 2175 ); - assert_eq!(r, mem::transmute(__msa_bnegi_h(mem::transmute(a), 11))); + assert_eq!(r, mem::transmute(__msa_bnegi_h::<11>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10927,7 +10926,7 @@ mod tests { #[rustfmt::skip] let r = u32x4::new(16777316, 2130706431, 16777316, 2164260864); - assert_eq!(r, mem::transmute(__msa_bnegi_w(mem::transmute(a), 24))); + assert_eq!(r, mem::transmute(__msa_bnegi_w::<24>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10937,7 +10936,7 @@ mod tests { #[rustfmt::skip] let r = u64x2::new(4398046511204, 9223376434901286912); - assert_eq!(r, mem::transmute(__msa_bnegi_d(mem::transmute(a), 42))); + assert_eq!(r, mem::transmute(__msa_bnegi_d::<42>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11066,7 +11065,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_bseli_b(mem::transmute(a), mem::transmute(b), 121)) + mem::transmute(__msa_bseli_b::<121>(mem::transmute(a), mem::transmute(b))) ); } @@ -11162,7 +11161,7 @@ mod tests { 255, 159, 55, 5 ); - assert_eq!(r, mem::transmute(__msa_bseti_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_bseti_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11172,7 +11171,7 @@ mod tests { #[rustfmt::skip] let r = u16x8::new(255, 159, 55, 5, 255, 159, 55, 5); - assert_eq!(r, mem::transmute(__msa_bseti_h(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_bseti_h::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11182,7 +11181,7 @@ mod tests { #[rustfmt::skip] let r = u32x4::new(255, 159, 55, 5); - assert_eq!(r, mem::transmute(__msa_bseti_w(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_bseti_w::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11192,7 +11191,7 @@ mod tests { #[rustfmt::skip] let r = u64x2::new(255, 159); - assert_eq!(r, mem::transmute(__msa_bseti_d(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_bseti_d::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11342,7 +11341,7 @@ mod tests { 0, 0, -1, 0 ); - assert_eq!(r, mem::transmute(__msa_ceqi_b(mem::transmute(a), -4))); + assert_eq!(r, mem::transmute(__msa_ceqi_b::<-4>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11355,7 +11354,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(0, 0, 0, -1, 0, 0, 0, -1); - assert_eq!(r, mem::transmute(__msa_ceqi_h(mem::transmute(a), -11))); + assert_eq!(r, mem::transmute(__msa_ceqi_h::<-11>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11365,7 +11364,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(0, 0, -1, 0); - assert_eq!(r, mem::transmute(__msa_ceqi_w(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_ceqi_w::<5>(mem::transmute(a)))); } // FIXME: https://reviews.llvm.org/D59884 @@ -11552,7 +11551,7 @@ mod tests { #[rustfmt::skip] let r = i8x16::new(-1, -1, 0, -1, -1, -1, 0, -1, -1, -1, 0, -1, -1, -1, 0, -1); - assert_eq!(r, mem::transmute(__msa_clei_s_b(mem::transmute(a), -2))); + assert_eq!(r, mem::transmute(__msa_clei_s_b::<-2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11565,7 +11564,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(0, 0, 0, -1, 0, 0, 0, -1); - assert_eq!(r, mem::transmute(__msa_clei_s_h(mem::transmute(a), -1))); + assert_eq!(r, mem::transmute(__msa_clei_s_h::<-1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11575,7 +11574,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(0, 0, -1, 0); - assert_eq!(r, mem::transmute(__msa_clei_s_w(mem::transmute(a), 6))); + assert_eq!(r, mem::transmute(__msa_clei_s_w::<6>(mem::transmute(a)))); } // FIXME: https://reviews.llvm.org/D59884 @@ -11608,7 +11607,7 @@ mod tests { -1, 0, 0, 0 ); - assert_eq!(r, mem::transmute(__msa_clei_u_b(mem::transmute(a), 25))); + assert_eq!(r, mem::transmute(__msa_clei_u_b::<25>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11621,7 +11620,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(-1, 0, -1, 0, -1, 0, -1, 0); - assert_eq!(r, mem::transmute(__msa_clei_u_h(mem::transmute(a), 25))); + assert_eq!(r, mem::transmute(__msa_clei_u_h::<25>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11631,7 +11630,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(-1, 0, -1, 0); - assert_eq!(r, mem::transmute(__msa_clei_u_w(mem::transmute(a), 31))); + assert_eq!(r, mem::transmute(__msa_clei_u_w::<31>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11641,7 +11640,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(-1, 0); - assert_eq!(r, mem::transmute(__msa_clei_u_d(mem::transmute(a), 25))); + assert_eq!(r, mem::transmute(__msa_clei_u_d::<25>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11811,7 +11810,7 @@ mod tests { 0, -1, 0, 0 ); - assert_eq!(r, mem::transmute(__msa_clti_s_b(mem::transmute(a), -5))); + assert_eq!(r, mem::transmute(__msa_clti_s_b::<-5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11824,7 +11823,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(-1, 0, 0, 0, -1, 0, 0, 0); - assert_eq!(r, mem::transmute(__msa_clti_s_h(mem::transmute(a), 15))); + assert_eq!(r, mem::transmute(__msa_clti_s_h::<15>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11834,7 +11833,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(-1, 0, -1, 0); - assert_eq!(r, mem::transmute(__msa_clti_s_w(mem::transmute(a), -10))); + assert_eq!(r, mem::transmute(__msa_clti_s_w::<-10>(mem::transmute(a)))); } // FIXME: https://reviews.llvm.org/D59884 @@ -11867,7 +11866,7 @@ mod tests { -1, 0, 0, 0 ); - assert_eq!(r, mem::transmute(__msa_clti_u_b(mem::transmute(a), 50))); + assert_eq!(r, mem::transmute(__msa_clti_u_b::<3>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11880,7 +11879,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - assert_eq!(r, mem::transmute(__msa_clti_u_h(mem::transmute(a), 30))); + assert_eq!(r, mem::transmute(__msa_clti_u_h::<30>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11890,7 +11889,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(0, 0, 0, 0); - assert_eq!(r, mem::transmute(__msa_clti_u_w(mem::transmute(a), 10))); + assert_eq!(r, mem::transmute(__msa_clti_u_w::<10>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11900,7 +11899,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(-1, 0); - assert_eq!(r, mem::transmute(__msa_clti_u_d(mem::transmute(a), 10))); + assert_eq!(r, mem::transmute(__msa_clti_u_d::<10>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11915,7 +11914,7 @@ mod tests { #[rustfmt::skip] let r = -100 as i32; - assert_eq!(r, mem::transmute(__msa_copy_s_b(mem::transmute(a), 12))); + assert_eq!(r, mem::transmute(__msa_copy_s_b::<12>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11928,7 +11927,7 @@ mod tests { #[rustfmt::skip] let r = 32767 as i32; - assert_eq!(r, mem::transmute(__msa_copy_s_h(mem::transmute(a), 4))); + assert_eq!(r, mem::transmute(__msa_copy_s_h::<4>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11937,7 +11936,7 @@ mod tests { let a = i32x4::new(100, 2147483647, 5, -2147483647); let r = 2147483647 as i32; - assert_eq!(r, mem::transmute(__msa_copy_s_w(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_copy_s_w::<1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11947,7 +11946,7 @@ mod tests { #[rustfmt::skip] let r = 9223372036854775807 as i64; - assert_eq!(r, mem::transmute(__msa_copy_s_d(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_copy_s_d::<1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11962,7 +11961,7 @@ mod tests { #[rustfmt::skip] let r = 100 as u32; - assert_eq!(r, mem::transmute(__msa_copy_u_b(mem::transmute(a), 12))); + assert_eq!(r, mem::transmute(__msa_copy_u_b::<12>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11975,7 +11974,7 @@ mod tests { #[rustfmt::skip] let r = 32767 as u32; - assert_eq!(r, mem::transmute(__msa_copy_u_h(mem::transmute(a), 4))); + assert_eq!(r, mem::transmute(__msa_copy_u_h::<4>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11985,7 +11984,7 @@ mod tests { #[rustfmt::skip] let r = 2147483647 as u32; - assert_eq!(r, mem::transmute(__msa_copy_u_w(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_copy_u_w::<1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11995,7 +11994,7 @@ mod tests { #[rustfmt::skip] let r = 9223372036854775807 as u64; - assert_eq!(r, mem::transmute(__msa_copy_u_d(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_copy_u_d::<1>(mem::transmute(a)))); } // Can not be tested in user mode @@ -14619,7 +14618,10 @@ mod tests { 5, 127, 4, 127 ); - assert_eq!(r, mem::transmute(__msa_insert_b(mem::transmute(a), 12, 5))); + assert_eq!( + r, + mem::transmute(__msa_insert_b::<12>(mem::transmute(a), 5)) + ); } #[simd_test(enable = "msa")] @@ -14635,7 +14637,7 @@ mod tests { 5, 3276, 100, 11 ); - assert_eq!(r, mem::transmute(__msa_insert_h(mem::transmute(a), 4, 5))); + assert_eq!(r, mem::transmute(__msa_insert_h::<4>(mem::transmute(a), 5))); } #[simd_test(enable = "msa")] @@ -14645,7 +14647,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(100, 7, 5, -2147483647); - assert_eq!(r, mem::transmute(__msa_insert_w(mem::transmute(a), 1, 7))); + assert_eq!(r, mem::transmute(__msa_insert_w::<1>(mem::transmute(a), 7))); } #[simd_test(enable = "msa")] @@ -14655,7 +14657,10 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(3, 100); - assert_eq!(r, mem::transmute(__msa_insert_d(mem::transmute(a), 1, 100))); + assert_eq!( + r, + mem::transmute(__msa_insert_d::<1>(mem::transmute(a), 100)) + ); } #[simd_test(enable = "msa")] @@ -14684,7 +14689,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_insve_b(mem::transmute(a), 12, mem::transmute(b))) + mem::transmute(__msa_insve_b::<12>(mem::transmute(a), mem::transmute(b))) ); } @@ -14708,7 +14713,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_insve_h(mem::transmute(a), 4, mem::transmute(b))) + mem::transmute(__msa_insve_h::<4>(mem::transmute(a), mem::transmute(b))) ); } @@ -14723,7 +14728,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_insve_w(mem::transmute(a), 3, mem::transmute(b))) + mem::transmute(__msa_insve_w::<3>(mem::transmute(a), mem::transmute(b))) ); } @@ -14738,7 +14743,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_insve_d(mem::transmute(a), 1, mem::transmute(b))) + mem::transmute(__msa_insve_d::<1>(mem::transmute(a), mem::transmute(b))) ); } @@ -14760,7 +14765,7 @@ mod tests { 25, 26, 27, 28 ); - assert_eq!(r, mem::transmute(__msa_ld_b(p, 9))); + assert_eq!(r, mem::transmute(__msa_ld_b::<9>(p))); } #[simd_test(enable = "msa")] @@ -14774,7 +14779,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(3, 4, 5, 6, 7, 8, 9, 10); - assert_eq!(r, mem::transmute(__msa_ld_h(p, -2))); + assert_eq!(r, mem::transmute(__msa_ld_h::<-2>(p))); } #[simd_test(enable = "msa")] @@ -14785,7 +14790,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(2, 3, 4, 5); - assert_eq!(r, mem::transmute(__msa_ld_w(p, -4))); + assert_eq!(r, mem::transmute(__msa_ld_w::<-4>(p))); } #[simd_test(enable = "msa")] @@ -14796,7 +14801,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(0, 1); - assert_eq!(r, mem::transmute(__msa_ld_d(p, -32))); + assert_eq!(r, mem::transmute(__msa_ld_d::<-32>(p))); } #[simd_test(enable = "msa")] @@ -14809,7 +14814,7 @@ mod tests { -20, -20, -20, -20 ); - assert_eq!(r, mem::transmute(__msa_ldi_b(-20))); + assert_eq!(r, mem::transmute(__msa_ldi_b::<-20>())); } #[simd_test(enable = "msa")] @@ -14820,7 +14825,7 @@ mod tests { 255, 255, 255, 255 ); - assert_eq!(r, mem::transmute(__msa_ldi_h(255))); + assert_eq!(r, mem::transmute(__msa_ldi_h::<255>())); } #[simd_test(enable = "msa")] @@ -14828,7 +14833,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(-509, -509, -509, -509); - assert_eq!(r, mem::transmute(__msa_ldi_w(-509))); + assert_eq!(r, mem::transmute(__msa_ldi_w::<-509>())); } // FIXME: https://reviews.llvm.org/D59884 @@ -15289,7 +15294,7 @@ mod tests { 1, -16, -6, 8 ); - assert_eq!(r, mem::transmute(__msa_maxi_s_b(mem::transmute(a), -16))); + assert_eq!(r, mem::transmute(__msa_maxi_s_b::<-16>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15299,7 +15304,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(15, 15, 15, 15, 15, 15, 15, 15); - assert_eq!(r, mem::transmute(__msa_maxi_s_h(mem::transmute(a), 15))); + assert_eq!(r, mem::transmute(__msa_maxi_s_h::<15>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15309,7 +15314,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(1, 3, -5, -5); - assert_eq!(r, mem::transmute(__msa_maxi_s_w(mem::transmute(a), -5))); + assert_eq!(r, mem::transmute(__msa_maxi_s_w::<-5>(mem::transmute(a)))); } // FIXME: https://reviews.llvm.org/D59884 @@ -15342,7 +15347,7 @@ mod tests { 5, 5, 6, 8 ); - assert_eq!(r, mem::transmute(__msa_maxi_u_b(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_maxi_u_b::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15352,7 +15357,7 @@ mod tests { #[rustfmt::skip] let r = u16x8::new(5, 5, 6, 8, 5, 5, 6, 8); - assert_eq!(r, mem::transmute(__msa_maxi_u_h(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_maxi_u_h::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15362,7 +15367,7 @@ mod tests { #[rustfmt::skip] let r = u32x4::new(5, 5, 6, 8); - assert_eq!(r, mem::transmute(__msa_maxi_u_w(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_maxi_u_w::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15372,7 +15377,7 @@ mod tests { #[rustfmt::skip] let r = u64x2::new(5, 8); - assert_eq!(r, mem::transmute(__msa_maxi_u_d(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_maxi_u_d::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15542,7 +15547,7 @@ mod tests { -10, -10, -10, -10 ); - assert_eq!(r, mem::transmute(__msa_mini_s_b(mem::transmute(a), -10))); + assert_eq!(r, mem::transmute(__msa_mini_s_b::<-10>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15552,7 +15557,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(-3, -3, -3, -4, -3, -3, -3, -4); - assert_eq!(r, mem::transmute(__msa_mini_s_h(mem::transmute(a), -3))); + assert_eq!(r, mem::transmute(__msa_mini_s_h::<-3>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15562,7 +15567,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(-3, -3, -3, -4); - assert_eq!(r, mem::transmute(__msa_mini_s_w(mem::transmute(a), -3))); + assert_eq!(r, mem::transmute(__msa_mini_s_w::<-3>(mem::transmute(a)))); } // FIXME: https://reviews.llvm.org/D59884 @@ -15670,7 +15675,7 @@ mod tests { 1, 3, 5, 5 ); - assert_eq!(r, mem::transmute(__msa_mini_u_b(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_mini_u_b::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15680,7 +15685,7 @@ mod tests { #[rustfmt::skip] let r = u16x8::new(1, 3, 5, 5, 1, 3, 5, 5); - assert_eq!(r, mem::transmute(__msa_mini_u_h(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_mini_u_h::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15690,7 +15695,7 @@ mod tests { #[rustfmt::skip] let r = u32x4::new(1, 3, 5, 5); - assert_eq!(r, mem::transmute(__msa_mini_u_w(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_mini_u_w::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15700,7 +15705,7 @@ mod tests { #[rustfmt::skip] let r = u64x2::new(1, 5); - assert_eq!(r, mem::transmute(__msa_mini_u_d(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_mini_u_d::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16394,7 +16399,7 @@ mod tests { 242, 241, 240, 235 ); - assert_eq!(r, mem::transmute(__msa_nori_b(mem::transmute(a), 4))); + assert_eq!(r, mem::transmute(__msa_nori_b::<4>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16444,7 +16449,7 @@ mod tests { 13, 14, 15, 20 ); - assert_eq!(r, mem::transmute(__msa_ori_b(mem::transmute(a), 4))); + assert_eq!(r, mem::transmute(__msa_ori_b::<4>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16670,7 +16675,7 @@ mod tests { 3, 3, 3, 1 ); - assert_eq!(r, mem::transmute(__msa_sat_s_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_sat_s_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16683,7 +16688,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(127, 127, 127, 1, 127, 127, 127, 1); - assert_eq!(r, mem::transmute(__msa_sat_s_h(mem::transmute(a), 7))); + assert_eq!(r, mem::transmute(__msa_sat_s_h::<7>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16693,7 +16698,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(131071, 131071, 131071, 1); - assert_eq!(r, mem::transmute(__msa_sat_s_w(mem::transmute(a), 17))); + assert_eq!(r, mem::transmute(__msa_sat_s_w::<17>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16703,7 +16708,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(137438953471, 1); - assert_eq!(r, mem::transmute(__msa_sat_s_d(mem::transmute(a), 37))); + assert_eq!(r, mem::transmute(__msa_sat_s_d::<37>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16723,7 +16728,7 @@ mod tests { 7, 7, 7, 1 ); - assert_eq!(r, mem::transmute(__msa_sat_u_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_sat_u_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16736,7 +16741,7 @@ mod tests { #[rustfmt::skip] let r = u16x8::new(255, 255, 155, 1, 255, 255, 155, 1); - assert_eq!(r, mem::transmute(__msa_sat_u_h(mem::transmute(a), 7))); + assert_eq!(r, mem::transmute(__msa_sat_u_h::<7>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16746,7 +16751,7 @@ mod tests { #[rustfmt::skip] let r = u32x4::new(262143, 262143, 262143, 1); - assert_eq!(r, mem::transmute(__msa_sat_u_w(mem::transmute(a), 17))); + assert_eq!(r, mem::transmute(__msa_sat_u_w::<17>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16756,7 +16761,7 @@ mod tests { #[rustfmt::skip] let r = u64x2::new(274877906943, 1); - assert_eq!(r, mem::transmute(__msa_sat_u_d(mem::transmute(a), 37))); + assert_eq!(r, mem::transmute(__msa_sat_u_d::<37>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16776,7 +16781,7 @@ mod tests { 11, 3, 4, 12 ); - assert_eq!(r, mem::transmute(__msa_shf_b(mem::transmute(a), 120))); + assert_eq!(r, mem::transmute(__msa_shf_b::<120>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16789,7 +16794,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(11, 14, 12, 13, 11, 14, 12, 13); - assert_eq!(r, mem::transmute(__msa_shf_h(mem::transmute(a), 156))); + assert_eq!(r, mem::transmute(__msa_shf_h::<156>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16799,7 +16804,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(1, 3, 2, 4); - assert_eq!(r, mem::transmute(__msa_shf_w(mem::transmute(a), 216))); + assert_eq!(r, mem::transmute(__msa_shf_w::<216>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16903,7 +16908,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_sldi_b(mem::transmute(a), mem::transmute(b), 5)) + mem::transmute(__msa_sldi_b::<5>(mem::transmute(a), mem::transmute(b))) ); } @@ -16918,7 +16923,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_sldi_h(mem::transmute(a), mem::transmute(b), 2)) + mem::transmute(__msa_sldi_h::<2>(mem::transmute(a), mem::transmute(b))) ); } @@ -16933,7 +16938,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_sldi_w(mem::transmute(a), mem::transmute(b), 4)) + mem::transmute(__msa_sldi_w::<0>(mem::transmute(a), mem::transmute(b))) ); } @@ -16948,7 +16953,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_sldi_d(mem::transmute(a), mem::transmute(b), 2)) + mem::transmute(__msa_sldi_d::<0>(mem::transmute(a), mem::transmute(b))) ); } @@ -17044,7 +17049,7 @@ mod tests { 4, 8, 12, 16 ); - assert_eq!(r, mem::transmute(__msa_slli_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_slli_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17057,7 +17062,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(4, 8, 12, 16, 4, 8, 12, 16); - assert_eq!(r, mem::transmute(__msa_slli_h(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_slli_h::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17067,7 +17072,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(4, 8, 12, 16); - assert_eq!(r, mem::transmute(__msa_slli_w(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_slli_w::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17077,7 +17082,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(2, 4); - assert_eq!(r, mem::transmute(__msa_slli_d(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_slli_d::<1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17150,7 +17155,7 @@ mod tests { 3, 3, 3, 3 ); - assert_eq!(r, mem::transmute(__msa_splati_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_splati_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17163,7 +17168,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(3, 3, 3, 3, 3, 3, 3, 3); - assert_eq!(r, mem::transmute(__msa_splati_h(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_splati_h::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17173,7 +17178,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(3, 3, 3, 3); - assert_eq!(r, mem::transmute(__msa_splati_w(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_splati_w::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17183,7 +17188,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(2, 2); - assert_eq!(r, mem::transmute(__msa_splati_d(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_splati_d::<1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17287,7 +17292,7 @@ mod tests { 31, 31, 13, 0 ); - assert_eq!(r, mem::transmute(__msa_srai_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srai_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17300,7 +17305,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(8191, 31, 13, 0, 8191, 31, 13, 0); - assert_eq!(r, mem::transmute(__msa_srai_h(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srai_h::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17309,7 +17314,7 @@ mod tests { let a = i32x4::new(i32::MAX, 125, 55, 1); let r = i32x4::new(536870911, 31, 13, 0); - assert_eq!(r, mem::transmute(__msa_srai_w(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srai_w::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17319,7 +17324,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(2305843009213693951, 13); - assert_eq!(r, mem::transmute(__msa_srai_d(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srai_d::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17423,7 +17428,7 @@ mod tests { 31, 32, 14, 0 ); - assert_eq!(r, mem::transmute(__msa_srari_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srari_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17433,7 +17438,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(539, 289, 39, 0, 539, 289, 39, 0); - assert_eq!(r, mem::transmute(__msa_srari_h(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srari_h::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17443,7 +17448,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(52777789, 27777789, 2777789, 0); - assert_eq!(r, mem::transmute(__msa_srari_w(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srari_w::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17453,7 +17458,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(52777777789, 27777777789); - assert_eq!(r, mem::transmute(__msa_srari_d(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srari_d::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17554,7 +17559,7 @@ mod tests { 6, 12, 25, 31 ); - assert_eq!(r, mem::transmute(__msa_srli_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srli_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17570,7 +17575,7 @@ mod tests { 8191, 819, 25, 31 ); - assert_eq!(r, mem::transmute(__msa_srli_h(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srli_h::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17580,7 +17585,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(25, 536870911, 25, 536870911); - assert_eq!(r, mem::transmute(__msa_srli_w(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srli_w::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17590,7 +17595,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(50, 4611686018427387903); - assert_eq!(r, mem::transmute(__msa_srli_d(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_srli_d::<1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17690,7 +17695,7 @@ mod tests { 6, 13, 25, 32 ); - assert_eq!(r, mem::transmute(__msa_srlri_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srlri_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17702,7 +17707,7 @@ mod tests { ); let r = i16x8::new(8192, 819, 25, 32, 8192, 819, 25, 32); - assert_eq!(r, mem::transmute(__msa_srlri_h(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srlri_h::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17712,7 +17717,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(25, 38, 50, 536870912); - assert_eq!(r, mem::transmute(__msa_srlri_w(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srlri_w::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17722,7 +17727,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(50, 4611686018427387904); - assert_eq!(r, mem::transmute(__msa_srlri_d(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_srlri_d::<1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17748,7 +17753,7 @@ mod tests { 21, 22, 23, 24, 25, 26, 27, 28 ]; - __msa_st_b(mem::transmute(a), arr.as_mut_ptr() as *mut u8, 0); + __msa_st_b::<0>(mem::transmute(a), arr.as_mut_ptr() as *mut u8); assert_eq!(arr, r); } @@ -17759,7 +17764,7 @@ mod tests { let mut arr: [i16; 8] = [0, 0, 0, 0, 0, 0, 0, 0]; #[rustfmt::skip] let r : [i16; 8] = [13, 14, 15, 16, 17, 18, 19, 20]; - __msa_st_h(mem::transmute(a), arr.as_mut_ptr() as *mut u8, 0); + __msa_st_h::<0>(mem::transmute(a), arr.as_mut_ptr() as *mut u8); assert_eq!(arr, r); } @@ -17770,7 +17775,7 @@ mod tests { let mut arr: [i32; 4] = [0, 0, 0, 0]; #[rustfmt::skip] let r : [i32; 4] = [13, 14, 15, 16]; - __msa_st_w(mem::transmute(a), arr.as_mut_ptr() as *mut u8, 0); + __msa_st_w::<0>(mem::transmute(a), arr.as_mut_ptr() as *mut u8); assert_eq!(arr, r); } @@ -17781,7 +17786,7 @@ mod tests { let mut arr: [i64; 2] = [0, 0]; #[rustfmt::skip] let r : [i64; 2] = [13, 14]; - __msa_st_d(mem::transmute(a), arr.as_mut_ptr() as *mut u8, 0); + __msa_st_d::<0>(mem::transmute(a), arr.as_mut_ptr() as *mut u8); assert_eq!(arr, r); } @@ -18195,7 +18200,7 @@ mod tests { 95, 122, 45, 123 ); - assert_eq!(r, mem::transmute(__msa_subvi_b(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_subvi_b::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -18211,7 +18216,7 @@ mod tests { 32762, 3271, -105, 32763 ); - assert_eq!(r, mem::transmute(__msa_subvi_h(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_subvi_h::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -18221,7 +18226,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(95, 145, 195, 2147483642); - assert_eq!(r, mem::transmute(__msa_subvi_w(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_subvi_w::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -18231,7 +18236,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(95, 9223372036854775802); - assert_eq!(r, mem::transmute(__msa_subvi_d(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_subvi_d::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -18393,6 +18398,6 @@ mod tests { 9, 10, 11, 20 ); - assert_eq!(r, mem::transmute(__msa_xori_b(mem::transmute(a), 4))); + assert_eq!(r, mem::transmute(__msa_xori_b::<4>(mem::transmute(a)))); } } diff --git a/library/stdarch/crates/core_arch/src/mod.rs b/library/stdarch/crates/core_arch/src/mod.rs index 3577175ae31c7..2483d07b230f9 100644 --- a/library/stdarch/crates/core_arch/src/mod.rs +++ b/library/stdarch/crates/core_arch/src/mod.rs @@ -320,6 +320,19 @@ pub mod arch { pub mod s390x { pub use crate::core_arch::s390x::*; } + + /// Platform-specific intrinsics for the `hexagon` platform. + /// + /// This module provides intrinsics for the Qualcomm Hexagon DSP architecture, + /// including the Hexagon Vector Extensions (HVX). + /// + /// See the [module documentation](../index.html) for more details. + #[cfg(any(target_arch = "hexagon", doc))] + #[doc(cfg(target_arch = "hexagon"))] + #[unstable(feature = "stdarch_hexagon", issue = "151523")] + pub mod hexagon { + pub use crate::core_arch::hexagon::*; + } } #[cfg(any(target_arch = "x86", target_arch = "x86_64", doc))] @@ -379,3 +392,7 @@ mod loongarch64; #[cfg(any(target_arch = "s390x", doc))] #[doc(cfg(target_arch = "s390x"))] mod s390x; + +#[cfg(any(target_arch = "hexagon", doc))] +#[doc(cfg(target_arch = "hexagon"))] +mod hexagon; diff --git a/library/stdarch/crates/core_arch/src/nvptx/mod.rs b/library/stdarch/crates/core_arch/src/nvptx/mod.rs index 5471ef819801e..53d53d1e1ef60 100644 --- a/library/stdarch/crates/core_arch/src/nvptx/mod.rs +++ b/library/stdarch/crates/core_arch/src/nvptx/mod.rs @@ -19,9 +19,9 @@ mod packed; pub use packed::*; #[allow(improper_ctypes)] -unsafe extern "C" { - #[link_name = "llvm.nvvm.barrier0"] - fn syncthreads() -> (); +unsafe extern "unadjusted" { + #[link_name = "llvm.nvvm.barrier.cta.sync.aligned.all"] + fn syncthreads(a: u32) -> (); #[link_name = "llvm.nvvm.read.ptx.sreg.ntid.x"] fn block_dim_x() -> u32; #[link_name = "llvm.nvvm.read.ptx.sreg.ntid.y"] @@ -49,10 +49,12 @@ unsafe extern "C" { } /// Synchronizes all threads in the block. +/// +#[doc = include_str!("../amdgpu/intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_nvptx", issue = "111199")] pub unsafe fn _syncthreads() -> () { - syncthreads() + syncthreads(0) } /// x-th thread-block dimension. @@ -155,10 +157,13 @@ unsafe extern "C" { /// * `format`: A pointer to the format specifier input (uses common `printf` format). /// * `valist`: A pointer to the valist input. /// - /// ``` + /// ```ignore (available only for nvptx) + /// # use std::mem::transmute; /// #[repr(C)] /// struct PrintArgs(f32, f32, f32, i32); /// + /// let a = 0.1f32; + /// let b = 0.2f32; /// vprintf( /// "int(%f + %f) = int(%f) = %d\n".as_ptr(), /// transmute(&PrintArgs(a, b, a + b, (a + b) as i32)), diff --git a/library/stdarch/crates/core_arch/src/nvptx/packed.rs b/library/stdarch/crates/core_arch/src/nvptx/packed.rs index 856aeea4b686c..7e6c14bc993d9 100644 --- a/library/stdarch/crates/core_arch/src/nvptx/packed.rs +++ b/library/stdarch/crates/core_arch/src/nvptx/packed.rs @@ -7,7 +7,7 @@ use crate::intrinsics::simd::*; #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.minimum.v2f16"] fn llvm_f16x2_minimum(a: f16x2, b: f16x2) -> f16x2; #[link_name = "llvm.maximum.v2f16"] @@ -99,7 +99,7 @@ pub unsafe fn f16x2_neg(a: f16x2) -> f16x2 { #[cfg_attr(test, assert_instr(min.f16x2))] #[unstable(feature = "stdarch_nvptx", issue = "111199")] pub unsafe fn f16x2_min(a: f16x2, b: f16x2) -> f16x2 { - simd_fmin(a, b) + simd_minimum_number_nsz(a, b) } /// Find the minimum of two values, NaNs pass through. @@ -123,7 +123,7 @@ pub unsafe fn f16x2_min_nan(a: f16x2, b: f16x2) -> f16x2 { #[cfg_attr(test, assert_instr(max.f16x2))] #[unstable(feature = "stdarch_nvptx", issue = "111199")] pub unsafe fn f16x2_max(a: f16x2, b: f16x2) -> f16x2 { - simd_fmax(a, b) + simd_maximum_number_nsz(a, b) } /// Find the maximum of two values, NaNs pass through. diff --git a/library/stdarch/crates/core_arch/src/powerpc/altivec.rs b/library/stdarch/crates/core_arch/src/powerpc/altivec.rs index fb1a9d8ed9e2c..ccfed88a93c2a 100644 --- a/library/stdarch/crates/core_arch/src/powerpc/altivec.rs +++ b/library/stdarch/crates/core_arch/src/powerpc/altivec.rs @@ -47,8 +47,56 @@ types! { pub struct vector_float(4 x f32); } +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for vector_bool_char { + #[inline] + fn from(value: m8x16) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for m8x16 { + #[inline] + fn from(value: vector_bool_char) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for vector_bool_short { + #[inline] + fn from(value: m16x8) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for m16x8 { + #[inline] + fn from(value: vector_bool_short) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for vector_bool_int { + #[inline] + fn from(value: m32x4) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for m32x4 { + #[inline] + fn from(value: vector_bool_int) -> Self { + unsafe { transmute(value) } + } +} + #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.ppc.altivec.lvx"] fn lvx(p: *const i8) -> vector_unsigned_int; @@ -129,8 +177,6 @@ unsafe extern "C" { b: vector_signed_short, c: vector_signed_int, ) -> vector_signed_int; - #[link_name = "llvm.ppc.altivec.vnmsubfp"] - fn vnmsubfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float; #[link_name = "llvm.ppc.altivec.vsum2sws"] fn vsum2sws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int; #[link_name = "llvm.ppc.altivec.vsum4ubs"] @@ -1881,9 +1927,9 @@ mod sealed { #[inline] #[target_feature(enable = "altivec")] - #[cfg_attr(test, assert_instr(vnmsubfp))] - unsafe fn vec_vnmsubfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float { - vnmsubfp(a, b, c) + #[cfg_attr(test, assert_instr(xvnmsubasp))] + pub unsafe fn vec_vnmsubfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float { + simd_neg(simd_fma(a, b, simd_neg(c))) } #[inline] @@ -3249,7 +3295,7 @@ mod sealed { unsafe fn vec_round(self) -> Self; } - test_impl! { vec_vrfin(a: vector_float) -> vector_float [vrfin, xvrspic] } + test_impl! { vec_vrfin(a: vector_float) -> vector_float [vrfin, vrfin] } #[unstable(feature = "stdarch_powerpc", issue = "111145")] impl VectorRound for vector_float { @@ -4281,7 +4327,7 @@ pub unsafe fn vec_madd(a: vector_float, b: vector_float, c: vector_float) -> vec #[target_feature(enable = "altivec")] #[unstable(feature = "stdarch_powerpc", issue = "111145")] pub unsafe fn vec_nmsub(a: vector_float, b: vector_float, c: vector_float) -> vector_float { - vnmsubfp(a, b, c) + sealed::vec_vnmsubfp(a, b, c) } /// Vector Select @@ -4653,22 +4699,22 @@ mod tests { }; { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: s_t_l!($ty) = transmute($ty::new($($a),+)); - let b: s_t_l!($ty) = transmute($ty::new($($b),+)); + fn $name() { + let a: s_t_l!($ty) = $ty::from_array([$($a),+]).into(); + let b: s_t_l!($ty) = $ty::from_array([$($b),+]).into(); - let d = $ty_out::new($($d),+); - let r : $ty_out = transmute($fn(a, b)); + let d = $ty_out::from_array([$($d),+]); + let r = $ty_out::from(unsafe { $fn(a, b) }); assert_eq!(d, r); } }; { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], $d:expr } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: s_t_l!($ty) = transmute($ty::new($($a),+)); - let b: s_t_l!($ty) = transmute($ty::new($($b),+)); + fn $name() { + let a: s_t_l!($ty) = $ty::from_array([$($a),+]).into(); + let b: s_t_l!($ty) = $ty::from_array([$($b),+]).into(); - let r : $ty_out = transmute($fn(a, b)); + let r = $ty_out::from(unsafe { $fn(a, b) }); assert_eq!($d, r); } } @@ -4677,12 +4723,12 @@ mod tests { macro_rules! test_vec_1 { { $name: ident, $fn:ident, f32x4, [$($a:expr),+], ~[$($d:expr),+] } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: vector_float = transmute(f32x4::new($($a),+)); + fn $name() { + let a = vector_float::from(f32x4::new($($a),+)); - let d: vector_float = transmute(f32x4::new($($d),+)); - let r = transmute(vec_cmple(vec_abs(vec_sub($fn(a), d)), vec_splats(f32::EPSILON))); - let e = m32x4::new(true, true, true, true); + let d = vector_float::from(f32x4::new($($d),+)); + let r = m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub($fn(a), d)), vec_splats(f32::EPSILON)) }); + let e = m32x4::splat(true); assert_eq!(e, r); } }; @@ -4691,18 +4737,18 @@ mod tests { }; { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($d:expr),+] } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: s_t_l!($ty) = transmute($ty::new($($a),+)); + fn $name() { + let a: s_t_l!($ty) = $ty::new($($a),+).into(); let d = $ty_out::new($($d),+); - let r : $ty_out = transmute($fn(a)); + let r = $ty_out::from(unsafe { $fn(a) }); assert_eq!(d, r); } } } #[simd_test(enable = "altivec")] - unsafe fn test_vec_ld() { + fn test_vec_ld() { let pat = [ u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15), u8x16::new( @@ -4711,14 +4757,14 @@ mod tests { ]; for off in 0..16 { - let v: u8x16 = transmute(vec_ld(0, (pat.as_ptr() as *const u8).offset(off))); + let v = u8x16::from(unsafe { vec_ld(0, (pat.as_ptr() as *const u8).offset(off)) }); assert_eq!( v, u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15) ); } for off in 16..32 { - let v: u8x16 = transmute(vec_ld(0, (pat.as_ptr() as *const u8).offset(off))); + let v = u8x16::from(unsafe { vec_ld(0, (pat.as_ptr() as *const u8).offset(off)) }); assert_eq!( v, u8x16::new( @@ -4729,7 +4775,7 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn test_vec_xl() { + fn test_vec_xl() { let pat = [ u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15), u8x16::new( @@ -4738,7 +4784,7 @@ mod tests { ]; for off in 0..16 { - let val: u8x16 = transmute(vec_xl(0, (pat.as_ptr() as *const u8).offset(off))); + let val = u8x16::from(unsafe { vec_xl(0, (pat.as_ptr() as *const u8).offset(off)) }); for i in 0..16 { let v = val.extract_dyn(i); assert_eq!(off as usize + i, v as usize); @@ -4747,14 +4793,16 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn test_vec_xst() { - let v: vector_unsigned_char = transmute(u8x16::new( + fn test_vec_xst() { + let v = vector_unsigned_char::from(u8x16::new( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, )); for off in 0..16 { let mut buf = [0u8; 32]; - vec_xst(v, 0, (buf.as_mut_ptr() as *mut u8).offset(off)); + unsafe { + vec_xst(v, 0, (buf.as_mut_ptr() as *mut u8).offset(off)); + } for i in 0..16 { assert_eq!(i as u8, buf[off as usize..][i]); } @@ -4762,7 +4810,7 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn test_vec_ldl() { + fn test_vec_ldl() { let pat = [ u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15), u8x16::new( @@ -4771,14 +4819,14 @@ mod tests { ]; for off in 0..16 { - let v: u8x16 = transmute(vec_ldl(0, (pat.as_ptr() as *const u8).offset(off))); + let v = u8x16::from(unsafe { vec_ldl(0, (pat.as_ptr() as *const u8).offset(off)) }); assert_eq!( v, u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15) ); } for off in 16..32 { - let v: u8x16 = transmute(vec_ldl(0, (pat.as_ptr() as *const u8).offset(off))); + let v = u8x16::from(unsafe { vec_ldl(0, (pat.as_ptr() as *const u8).offset(off)) }); assert_eq!( v, u8x16::new( @@ -4789,30 +4837,30 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn test_vec_lde_u8() { + fn test_vec_lde_u8() { let pat = [u8x16::new( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, )]; for off in 0..16 { - let v: u8x16 = transmute(vec_lde(off, pat.as_ptr() as *const u8)); + let v = u8x16::from(unsafe { vec_lde(off, pat.as_ptr() as *const u8) }); assert_eq!(off as u8, v.extract_dyn(off as _)); } } #[simd_test(enable = "altivec")] - unsafe fn test_vec_lde_u16() { + fn test_vec_lde_u16() { let pat = [u16x8::new(0, 1, 2, 3, 4, 5, 6, 7)]; for off in 0..8 { - let v: u16x8 = transmute(vec_lde(off * 2, pat.as_ptr() as *const u16)); + let v = u16x8::from(unsafe { vec_lde(off * 2, pat.as_ptr() as *const u16) }); assert_eq!(off as u16, v.extract_dyn(off as _)); } } #[simd_test(enable = "altivec")] - unsafe fn test_vec_lde_u32() { + fn test_vec_lde_u32() { let pat = [u32x4::new(0, 1, 2, 3)]; for off in 0..4 { - let v: u32x4 = transmute(vec_lde(off * 4, pat.as_ptr() as *const u32)); + let v = u32x4::from(unsafe { vec_lde(off * 4, pat.as_ptr() as *const u32) }); assert_eq!(off as u32, v.extract_dyn(off as _)); } } @@ -5818,9 +5866,9 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn test_vec_cmpb() { - let a: vector_float = transmute(f32x4::new(0.1, 0.5, 0.6, 0.9)); - let b: vector_float = transmute(f32x4::new(-0.1, 0.5, -0.6, 0.9)); + fn test_vec_cmpb() { + let a = vector_float::from(f32x4::new(0.1, 0.5, 0.6, 0.9)); + let b = vector_float::from(f32x4::new(-0.1, 0.5, -0.6, 0.9)); let d = i32x4::new( -0b10000000000000000000000000000000, 0, @@ -5828,15 +5876,15 @@ mod tests { 0, ); - assert_eq!(d, transmute(vec_cmpb(a, b))); + assert_eq!(d, i32x4::from(unsafe { vec_cmpb(a, b) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_ceil() { - let a: vector_float = transmute(f32x4::new(0.1, 0.5, 0.6, 0.9)); + fn test_vec_ceil() { + let a = vector_float::from(f32x4::new(0.1, 0.5, 0.6, 0.9)); let d = f32x4::new(1.0, 1.0, 1.0, 1.0); - assert_eq!(d, transmute(vec_ceil(a))); + assert_eq!(d, f32x4::from(unsafe { vec_ceil(a) })); } test_vec_2! { test_vec_andc, vec_andc, i32x4, @@ -5926,11 +5974,11 @@ mod tests { macro_rules! test_vec_abs { { $name: ident, $ty: ident, $a: expr, $d: expr } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a = vec_splats($a); - let a: s_t_l!($ty) = vec_abs(a); + fn $name() { + let a = unsafe { vec_splats($a) }; + let a: s_t_l!($ty) = unsafe { vec_abs(a) }; let d = $ty::splat($d); - assert_eq!(d, transmute(a)); + assert_eq!(d, $ty::from(a)); } } } @@ -5943,11 +5991,11 @@ mod tests { macro_rules! test_vec_abss { { $name: ident, $ty: ident, $a: expr, $d: expr } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a = vec_splats($a); - let a: s_t_l!($ty) = vec_abss(a); + fn $name() { + let a = unsafe { vec_splats($a) }; + let a: s_t_l!($ty) = unsafe { vec_abss(a) }; let d = $ty::splat($d); - assert_eq!(d, transmute(a)); + assert_eq!(d, $ty::from(a)); } } } @@ -5959,10 +6007,10 @@ mod tests { macro_rules! test_vec_splats { { $name: ident, $ty: ident, $a: expr } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: s_t_l!($ty) = vec_splats($a); + fn $name() { + let a: s_t_l!($ty) = unsafe { vec_splats($a) }; let d = $ty::splat($a); - assert_eq!(d, transmute(a)); + assert_eq!(d, $ty::from(a)); } } } @@ -5978,10 +6026,10 @@ mod tests { macro_rules! test_vec_splat { { $name: ident, $fun: ident, $ty: ident, $a: expr, $b: expr} => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a = $fun::<$a>(); + fn $name() { + let a = unsafe { $fun::<$a>() }; let d = $ty::splat($b); - assert_eq!(d, transmute(a)); + assert_eq!(d, $ty::from(a)); } } } @@ -6073,12 +6121,12 @@ mod tests { macro_rules! test_vec_min { { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: s_t_l!($ty) = transmute($ty::new($($a),+)); - let b: s_t_l!($ty) = transmute($ty::new($($b),+)); + fn $name() { + let a: s_t_l!($ty) = $ty::new($($a),+).into(); + let b: s_t_l!($ty) = $ty::new($($b),+).into(); let d = $ty::new($($d),+); - let r : $ty = transmute(vec_min(a, b)); + let r = $ty::from(unsafe { vec_min(a, b) }); assert_eq!(d, r); } } @@ -6117,12 +6165,12 @@ mod tests { macro_rules! test_vec_max { { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: s_t_l!($ty) = transmute($ty::new($($a),+)); - let b: s_t_l!($ty) = transmute($ty::new($($b),+)); + fn $name() { + let a: s_t_l!($ty) = $ty::new($($a),+).into(); + let b: s_t_l!($ty) = $ty::new($($b),+).into(); let d = $ty::new($($d),+); - let r : $ty = transmute(vec_max(a, b)); + let r = $ty::from(unsafe { vec_max(a, b) }); assert_eq!(d, r); } } @@ -6163,13 +6211,13 @@ mod tests { $shorttype:ident, $longtype:ident, [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: $longtype = transmute($shorttype::new($($a),+)); - let b: $longtype = transmute($shorttype::new($($b),+)); - let c: vector_unsigned_char = transmute(u8x16::new($($c),+)); - let d = $shorttype::new($($d),+); + fn $name() { + let a = $longtype::from($shorttype::from_array([$($a),+])); + let b = $longtype::from($shorttype::from_array([$($b),+])); + let c = vector_unsigned_char::from(u8x16::from_array([$($c),+])); + let d = $shorttype::from_array([$($d),+]); - let r: $shorttype = transmute(vec_perm(a, b, c)); + let r = $shorttype::from(unsafe { vec_perm(a, b, c) }); assert_eq!(d, r); } } @@ -6249,8 +6297,8 @@ mod tests { [0.0, 1.0, 1.0, 1.1]} #[simd_test(enable = "altivec")] - unsafe fn test_vec_madds() { - let a: vector_signed_short = transmute(i16x8::new( + fn test_vec_madds() { + let a = vector_signed_short::from(i16x8::new( 0 * 256, 1 * 256, 2 * 256, @@ -6260,19 +6308,19 @@ mod tests { 6 * 256, 7 * 256, )); - let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); - let c: vector_signed_short = transmute(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); + let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); + let c = vector_signed_short::from(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); let d = i16x8::new(0, 3, 6, 9, 12, 15, 18, 21); - assert_eq!(d, transmute(vec_madds(a, b, c))); + assert_eq!(d, i16x8::from(unsafe { vec_madds(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_madd_float() { - let a: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4)); - let b: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4)); - let c: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4)); + fn test_vec_madd_float() { + let a = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4)); + let b = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4)); + let c = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4)); let d = f32x4::new( 0.1 * 0.1 + 0.1, 0.2 * 0.2 + 0.2, @@ -6280,26 +6328,26 @@ mod tests { 0.4 * 0.4 + 0.4, ); - assert_eq!(d, transmute(vec_madd(a, b, c))); + assert_eq!(d, f32x4::from(unsafe { vec_madd(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_nmsub_float() { - let a: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4)); - let b: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4)); - let c: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4)); + fn test_vec_nmsub_float() { + let a = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4)); + let b = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4)); + let c = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4)); let d = f32x4::new( -(0.1 * 0.1 - 0.1), -(0.2 * 0.2 - 0.2), -(0.3 * 0.3 - 0.3), -(0.4 * 0.4 - 0.4), ); - assert_eq!(d, transmute(vec_nmsub(a, b, c))); + assert_eq!(d, f32x4::from(unsafe { vec_nmsub(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mradds() { - let a: vector_signed_short = transmute(i16x8::new( + fn test_vec_mradds() { + let a = vector_signed_short::from(i16x8::new( 0 * 256, 1 * 256, 2 * 256, @@ -6309,25 +6357,25 @@ mod tests { 6 * 256, 7 * 256, )); - let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); - let c: vector_signed_short = transmute(i16x8::new(0, 1, 2, 3, 4, 5, 6, i16::MAX - 1)); + let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); + let c = vector_signed_short::from(i16x8::new(0, 1, 2, 3, 4, 5, 6, i16::MAX - 1)); let d = i16x8::new(0, 3, 6, 9, 12, 15, 18, i16::MAX); - assert_eq!(d, transmute(vec_mradds(a, b, c))); + assert_eq!(d, i16x8::from(unsafe { vec_mradds(a, b, c) })); } macro_rules! test_vec_mladd { {$name:ident, $sa:ident, $la:ident, $sbc:ident, $lbc:ident, $sd:ident, [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: $la = transmute($sa::new($($a),+)); - let b: $lbc = transmute($sbc::new($($b),+)); - let c = transmute($sbc::new($($c),+)); + fn $name() { + let a = $la::from($sa::new($($a),+)); + let b = $lbc::from($sbc::new($($b),+)); + let c = $sbc::new($($c),+).into(); let d = $sd::new($($d),+); - assert_eq!(d, transmute(vec_mladd(a, b, c))); + assert_eq!(d, $sd::from(unsafe { vec_mladd(a, b, c) })); } } } @@ -6335,24 +6383,24 @@ mod tests { test_vec_mladd! { test_vec_mladd_u16x8_u16x8, u16x8, vector_unsigned_short, u16x8, vector_unsigned_short, u16x8, [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56] } - test_vec_mladd! { test_vec_mladd_u16x8_i16x8, u16x8, vector_unsigned_short, i16x8, vector_unsigned_short, i16x8, + test_vec_mladd! { test_vec_mladd_u16x8_i16x8, u16x8, vector_unsigned_short, i16x8, vector_signed_short, i16x8, [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56] } test_vec_mladd! { test_vec_mladd_i16x8_u16x8, i16x8, vector_signed_short, u16x8, vector_unsigned_short, i16x8, [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56] } - test_vec_mladd! { test_vec_mladd_i16x8_i16x8, i16x8, vector_signed_short, i16x8, vector_unsigned_short, i16x8, + test_vec_mladd! { test_vec_mladd_i16x8_i16x8, i16x8, vector_signed_short, i16x8, vector_signed_short, i16x8, [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56] } #[simd_test(enable = "altivec")] - unsafe fn test_vec_msum_unsigned_char() { - let a: vector_unsigned_char = - transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); - let b: vector_unsigned_char = transmute(u8x16::new( + fn test_vec_msum_unsigned_char() { + let a = + vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); + let b = vector_unsigned_char::from(u8x16::new( 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, )); - let c: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3)); + let c = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3)); let d = u32x4::new( (0 + 1 + 2 + 3) * 255 + 0, (4 + 5 + 6 + 7) * 255 + 1, @@ -6360,17 +6408,17 @@ mod tests { (4 + 5 + 6 + 7) * 255 + 3, ); - assert_eq!(d, transmute(vec_msum(a, b, c))); + assert_eq!(d, u32x4::from(unsafe { vec_msum(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_msum_signed_char() { - let a: vector_signed_char = transmute(i8x16::new( + fn test_vec_msum_signed_char() { + let a = vector_signed_char::from(i8x16::new( 0, -1, 2, -3, 1, -1, 1, -1, 0, 1, 2, 3, 4, -5, -6, -7, )); - let b: vector_unsigned_char = - transmute(i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1)); - let c: vector_signed_int = transmute(u32x4::new(0, 1, 2, 3)); + let b = + vector_unsigned_char::from(u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1)); + let c = vector_signed_int::from(i32x4::new(0, 1, 2, 3)); let d = i32x4::new( (0 - 1 + 2 - 3) + 0, (0) + 1, @@ -6378,11 +6426,12 @@ mod tests { (4 - 5 - 6 - 7) + 3, ); - assert_eq!(d, transmute(vec_msum(a, b, c))); + assert_eq!(d, i32x4::from(unsafe { vec_msum(a, b, c) })); } + #[simd_test(enable = "altivec")] - unsafe fn test_vec_msum_unsigned_short() { - let a: vector_unsigned_short = transmute(u16x8::new( + fn test_vec_msum_unsigned_short() { + let a = vector_unsigned_short::from(u16x8::new( 0 * 256, 1 * 256, 2 * 256, @@ -6392,9 +6441,8 @@ mod tests { 6 * 256, 7 * 256, )); - let b: vector_unsigned_short = - transmute(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); - let c: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3)); + let b = vector_unsigned_short::from(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); + let c = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3)); let d = u32x4::new( (0 + 1) * 256 * 256 + 0, (2 + 3) * 256 * 256 + 1, @@ -6402,12 +6450,12 @@ mod tests { (6 + 7) * 256 * 256 + 3, ); - assert_eq!(d, transmute(vec_msum(a, b, c))); + assert_eq!(d, u32x4::from(unsafe { vec_msum(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_msum_signed_short() { - let a: vector_signed_short = transmute(i16x8::new( + fn test_vec_msum_signed_short() { + let a = vector_signed_short::from(i16x8::new( 0 * 256, -1 * 256, 2 * 256, @@ -6417,8 +6465,8 @@ mod tests { 6 * 256, -7 * 256, )); - let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); - let c: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3)); + let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); + let c = vector_signed_int::from(i32x4::new(0, 1, 2, 3)); let d = i32x4::new( (0 - 1) * 256 * 256 + 0, (2 - 3) * 256 * 256 + 1, @@ -6426,12 +6474,12 @@ mod tests { (6 - 7) * 256 * 256 + 3, ); - assert_eq!(d, transmute(vec_msum(a, b, c))); + assert_eq!(d, i32x4::from(unsafe { vec_msum(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_msums_unsigned() { - let a: vector_unsigned_short = transmute(u16x8::new( + fn test_vec_msums_unsigned() { + let a = vector_unsigned_short::from(u16x8::new( 0 * 256, 1 * 256, 2 * 256, @@ -6441,9 +6489,8 @@ mod tests { 6 * 256, 7 * 256, )); - let b: vector_unsigned_short = - transmute(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); - let c: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3)); + let b = vector_unsigned_short::from(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); + let c = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3)); let d = u32x4::new( (0 + 1) * 256 * 256 + 0, (2 + 3) * 256 * 256 + 1, @@ -6451,12 +6498,12 @@ mod tests { (6 + 7) * 256 * 256 + 3, ); - assert_eq!(d, transmute(vec_msums(a, b, c))); + assert_eq!(d, u32x4::from(unsafe { vec_msums(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_msums_signed() { - let a: vector_signed_short = transmute(i16x8::new( + fn test_vec_msums_signed() { + let a = vector_signed_short::from(i16x8::new( 0 * 256, -1 * 256, 2 * 256, @@ -6466,8 +6513,8 @@ mod tests { 6 * 256, -7 * 256, )); - let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); - let c: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3)); + let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); + let c = vector_signed_int::from(i32x4::new(0, 1, 2, 3)); let d = i32x4::new( (0 - 1) * 256 * 256 + 0, (2 - 3) * 256 * 256 + 1, @@ -6475,23 +6522,23 @@ mod tests { (6 - 7) * 256 * 256 + 3, ); - assert_eq!(d, transmute(vec_msums(a, b, c))); + assert_eq!(d, i32x4::from(unsafe { vec_msums(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_sum2s() { - let a: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3)); - let b: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3)); + fn test_vec_sum2s() { + let a = vector_signed_int::from(i32x4::new(0, 1, 2, 3)); + let b = vector_signed_int::from(i32x4::new(0, 1, 2, 3)); let d = i32x4::new(0, 0 + 1 + 1, 0, 2 + 3 + 3); - assert_eq!(d, transmute(vec_sum2s(a, b))); + assert_eq!(d, i32x4::from(unsafe { vec_sum2s(a, b) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_sum4s_unsigned_char() { - let a: vector_unsigned_char = - transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); - let b: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3)); + fn test_vec_sum4s_unsigned_char() { + let a = + vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); + let b = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3)); let d = u32x4::new( 0 + 1 + 2 + 3 + 0, 4 + 5 + 6 + 7 + 1, @@ -6499,13 +6546,13 @@ mod tests { 4 + 5 + 6 + 7 + 3, ); - assert_eq!(d, transmute(vec_sum4s(a, b))); + assert_eq!(d, u32x4::from(unsafe { vec_sum4s(a, b) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_sum4s_signed_char() { - let a: vector_signed_char = - transmute(i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); - let b: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3)); + fn test_vec_sum4s_signed_char() { + let a = + vector_signed_char::from(i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); + let b = vector_signed_int::from(i32x4::new(0, 1, 2, 3)); let d = i32x4::new( 0 + 1 + 2 + 3 + 0, 4 + 5 + 6 + 7 + 1, @@ -6513,110 +6560,111 @@ mod tests { 4 + 5 + 6 + 7 + 3, ); - assert_eq!(d, transmute(vec_sum4s(a, b))); + assert_eq!(d, i32x4::from(unsafe { vec_sum4s(a, b) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_sum4s_signed_short() { - let a: vector_signed_short = transmute(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); - let b: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3)); + fn test_vec_sum4s_signed_short() { + let a = vector_signed_short::from(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); + let b = vector_signed_int::from(i32x4::new(0, 1, 2, 3)); let d = i32x4::new(0 + 1 + 0, 2 + 3 + 1, 4 + 5 + 2, 6 + 7 + 3); - assert_eq!(d, transmute(vec_sum4s(a, b))); + assert_eq!(d, i32x4::from(unsafe { vec_sum4s(a, b) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mule_unsigned_char() { - let a: vector_unsigned_char = - transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); + fn test_vec_mule_unsigned_char() { + let a = + vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); let d = u16x8::new(0 * 0, 2 * 2, 4 * 4, 6 * 6, 0 * 0, 2 * 2, 4 * 4, 6 * 6); - assert_eq!(d, transmute(vec_mule(a, a))); + assert_eq!(d, u16x8::from(unsafe { vec_mule(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mule_signed_char() { - let a: vector_signed_char = transmute(i8x16::new( + fn test_vec_mule_signed_char() { + let a = vector_signed_char::from(i8x16::new( 0, 1, -2, 3, -4, 5, -6, 7, 0, 1, 2, 3, 4, 5, 6, 7, )); let d = i16x8::new(0 * 0, 2 * 2, 4 * 4, 6 * 6, 0 * 0, 2 * 2, 4 * 4, 6 * 6); - assert_eq!(d, transmute(vec_mule(a, a))); + assert_eq!(d, i16x8::from(unsafe { vec_mule(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mule_unsigned_short() { - let a: vector_unsigned_short = transmute(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); + fn test_vec_mule_unsigned_short() { + let a = vector_unsigned_short::from(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); let d = u32x4::new(0 * 0, 2 * 2, 4 * 4, 6 * 6); - assert_eq!(d, transmute(vec_mule(a, a))); + assert_eq!(d, u32x4::from(unsafe { vec_mule(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mule_signed_short() { - let a: vector_signed_short = transmute(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7)); + fn test_vec_mule_signed_short() { + let a = vector_signed_short::from(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7)); let d = i32x4::new(0 * 0, 2 * 2, 4 * 4, 6 * 6); - assert_eq!(d, transmute(vec_mule(a, a))); + assert_eq!(d, i32x4::from(unsafe { vec_mule(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mulo_unsigned_char() { - let a: vector_unsigned_char = - transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); + fn test_vec_mulo_unsigned_char() { + let a = + vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); let d = u16x8::new(1 * 1, 3 * 3, 5 * 5, 7 * 7, 1 * 1, 3 * 3, 5 * 5, 7 * 7); - assert_eq!(d, transmute(vec_mulo(a, a))); + assert_eq!(d, u16x8::from(unsafe { vec_mulo(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mulo_signed_char() { - let a: vector_signed_char = transmute(i8x16::new( + fn test_vec_mulo_signed_char() { + let a = vector_signed_char::from(i8x16::new( 0, 1, -2, 3, -4, 5, -6, 7, 0, 1, 2, 3, 4, 5, 6, 7, )); let d = i16x8::new(1 * 1, 3 * 3, 5 * 5, 7 * 7, 1 * 1, 3 * 3, 5 * 5, 7 * 7); - assert_eq!(d, transmute(vec_mulo(a, a))); + assert_eq!(d, i16x8::from(unsafe { vec_mulo(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mulo_unsigned_short() { - let a: vector_unsigned_short = transmute(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); + fn test_vec_mulo_unsigned_short() { + let a = vector_unsigned_short::from(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); let d = u32x4::new(1 * 1, 3 * 3, 5 * 5, 7 * 7); - assert_eq!(d, transmute(vec_mulo(a, a))); + assert_eq!(d, u32x4::from(unsafe { vec_mulo(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mulo_signed_short() { - let a: vector_signed_short = transmute(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7)); + fn test_vec_mulo_signed_short() { + let a = vector_signed_short::from(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7)); let d = i32x4::new(1 * 1, 3 * 3, 5 * 5, 7 * 7); - assert_eq!(d, transmute(vec_mulo(a, a))); + assert_eq!(d, i32x4::from(unsafe { vec_mulo(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn vec_add_i32x4_i32x4() { + fn vec_add_i32x4_i32x4() { let x = i32x4::new(1, 2, 3, 4); let y = i32x4::new(4, 3, 2, 1); - let x: vector_signed_int = transmute(x); - let y: vector_signed_int = transmute(y); - let z = vec_add(x, y); - assert_eq!(i32x4::splat(5), transmute(z)); + let x = vector_signed_int::from(x); + let y = vector_signed_int::from(y); + let z = unsafe { vec_add(x, y) }; + assert_eq!(i32x4::splat(5), i32x4::from(z)); } #[simd_test(enable = "altivec")] - unsafe fn vec_ctf_u32() { - let v: vector_unsigned_int = transmute(u32x4::new(u32::MIN, u32::MAX, u32::MAX, 42)); - let v2 = vec_ctf::<1, _>(v); - let r2: vector_float = transmute(f32x4::new(0.0, 2147483600.0, 2147483600.0, 21.0)); - let v4 = vec_ctf::<2, _>(v); - let r4: vector_float = transmute(f32x4::new(0.0, 1073741800.0, 1073741800.0, 10.5)); - let v8 = vec_ctf::<3, _>(v); - let r8: vector_float = transmute(f32x4::new(0.0, 536870900.0, 536870900.0, 5.25)); + fn vec_ctf_u32() { + let v = vector_unsigned_int::from(u32x4::new(u32::MIN, u32::MAX, u32::MAX, 42)); + let v2 = unsafe { vec_ctf::<1, _>(v) }; + let r2 = vector_float::from(f32x4::new(0.0, 2147483600.0, 2147483600.0, 21.0)); + let v4 = unsafe { vec_ctf::<2, _>(v) }; + let r4 = vector_float::from(f32x4::new(0.0, 1073741800.0, 1073741800.0, 10.5)); + let v8 = unsafe { vec_ctf::<3, _>(v) }; + let r8 = vector_float::from(f32x4::new(0.0, 536870900.0, 536870900.0, 5.25)); let check = |a, b| { - let r = transmute(vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON))); - let e = m32x4::new(true, true, true, true); + let r = + m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)) }); + let e = m32x4::splat(true); assert_eq!(e, r); }; @@ -6626,26 +6674,32 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn test_vec_ctu() { + fn test_vec_ctu() { let v = u32x4::new(u32::MIN, u32::MAX, u32::MAX, 42); - let v2: u32x4 = transmute(vec_ctu::<1>(transmute(f32x4::new( - 0.0, - 2147483600.0, - 2147483600.0, - 21.0, - )))); - let v4: u32x4 = transmute(vec_ctu::<2>(transmute(f32x4::new( - 0.0, - 1073741800.0, - 1073741800.0, - 10.5, - )))); - let v8: u32x4 = transmute(vec_ctu::<3>(transmute(f32x4::new( - 0.0, - 536870900.0, - 536870900.0, - 5.25, - )))); + let v2 = u32x4::from(unsafe { + vec_ctu::<1>(vector_float::from(f32x4::new( + 0.0, + 2147483600.0, + 2147483600.0, + 21.0, + ))) + }); + let v4 = u32x4::from(unsafe { + vec_ctu::<2>(vector_float::from(f32x4::new( + 0.0, + 1073741800.0, + 1073741800.0, + 10.5, + ))) + }); + let v8 = u32x4::from(unsafe { + vec_ctu::<3>(vector_float::from(f32x4::new( + 0.0, + 536870900.0, + 536870900.0, + 5.25, + ))) + }); assert_eq!(v2, v); assert_eq!(v4, v); @@ -6653,20 +6707,20 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn vec_ctf_i32() { - let v: vector_signed_int = transmute(i32x4::new(i32::MIN, i32::MAX, i32::MAX - 42, 42)); - let v2 = vec_ctf::<1, _>(v); - let r2: vector_float = - transmute(f32x4::new(-1073741800.0, 1073741800.0, 1073741800.0, 21.0)); - let v4 = vec_ctf::<2, _>(v); - let r4: vector_float = transmute(f32x4::new(-536870900.0, 536870900.0, 536870900.0, 10.5)); - let v8 = vec_ctf::<3, _>(v); - let r8: vector_float = transmute(f32x4::new(-268435460.0, 268435460.0, 268435460.0, 5.25)); + fn vec_ctf_i32() { + let v = vector_signed_int::from(i32x4::new(i32::MIN, i32::MAX, i32::MAX - 42, 42)); + let v2 = unsafe { vec_ctf::<1, _>(v) }; + let r2 = vector_float::from(f32x4::new(-1073741800.0, 1073741800.0, 1073741800.0, 21.0)); + let v4 = unsafe { vec_ctf::<2, _>(v) }; + let r4 = vector_float::from(f32x4::new(-536870900.0, 536870900.0, 536870900.0, 10.5)); + let v8 = unsafe { vec_ctf::<3, _>(v) }; + let r8 = vector_float::from(f32x4::new(-268435460.0, 268435460.0, 268435460.0, 5.25)); let check = |a, b| { - let r = transmute(vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON))); + let r = + m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)) }); println!("{:?} {:?}", a, b); - let e = m32x4::new(true, true, true, true); + let e = m32x4::splat(true); assert_eq!(e, r); }; @@ -6676,26 +6730,32 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn test_vec_cts() { + fn test_vec_cts() { let v = i32x4::new(i32::MIN, i32::MAX, i32::MAX, 42); - let v2: i32x4 = transmute(vec_cts::<1>(transmute(f32x4::new( - -1073741800.0, - 1073741800.0, - 1073741800.0, - 21.0, - )))); - let v4: i32x4 = transmute(vec_cts::<2>(transmute(f32x4::new( - -536870900.0, - 536870900.0, - 536870900.0, - 10.5, - )))); - let v8: i32x4 = transmute(vec_cts::<3>(transmute(f32x4::new( - -268435460.0, - 268435460.0, - 268435460.0, - 5.25, - )))); + let v2 = i32x4::from(unsafe { + vec_cts::<1>(transmute(f32x4::new( + -1073741800.0, + 1073741800.0, + 1073741800.0, + 21.0, + ))) + }); + let v4 = i32x4::from(unsafe { + vec_cts::<2>(transmute(f32x4::new( + -536870900.0, + 536870900.0, + 536870900.0, + 10.5, + ))) + }); + let v8 = i32x4::from(unsafe { + vec_cts::<3>(transmute(f32x4::new( + -268435460.0, + 268435460.0, + 268435460.0, + 5.25, + ))) + }); assert_eq!(v2, v); assert_eq!(v4, v); diff --git a/library/stdarch/crates/core_arch/src/powerpc/vsx.rs b/library/stdarch/crates/core_arch/src/powerpc/vsx.rs index ca9fcaabe8b22..60cb2ad44cd4e 100644 --- a/library/stdarch/crates/core_arch/src/powerpc/vsx.rs +++ b/library/stdarch/crates/core_arch/src/powerpc/vsx.rs @@ -9,6 +9,7 @@ #![allow(non_camel_case_types)] use crate::core_arch::powerpc::*; +use crate::core_arch::simd::*; #[cfg(test)] use stdarch_test::assert_instr; @@ -34,8 +35,24 @@ types! { // pub struct vector_unsigned___int128 = i128x1; } +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for vector_bool_long { + #[inline] + fn from(value: m64x2) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for m64x2 { + #[inline] + fn from(value: vector_bool_long) -> Self { + unsafe { transmute(value) } + } +} + #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.ppc.altivec.vperm"] fn vperm( a: vector_signed_int, @@ -46,7 +63,6 @@ unsafe extern "C" { mod sealed { use super::*; - use crate::core_arch::simd::*; #[unstable(feature = "stdarch_powerpc", issue = "111145")] pub trait VectorPermDI { @@ -221,14 +237,16 @@ mod tests { macro_rules! test_vec_xxpermdi { {$name:ident, $shorttype:ident, $longtype:ident, [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => { #[simd_test(enable = "vsx")] - unsafe fn $name() { - let a: $longtype = transmute($shorttype::new($($a),+, $($b),+)); - let b = transmute($shorttype::new($($c),+, $($d),+)); - - assert_eq!($shorttype::new($($a),+, $($c),+), transmute(vec_xxpermdi::<_, 0>(a, b))); - assert_eq!($shorttype::new($($b),+, $($c),+), transmute(vec_xxpermdi::<_, 1>(a, b))); - assert_eq!($shorttype::new($($a),+, $($d),+), transmute(vec_xxpermdi::<_, 2>(a, b))); - assert_eq!($shorttype::new($($b),+, $($d),+), transmute(vec_xxpermdi::<_, 3>(a, b))); + fn $name() { + let a = $longtype::from($shorttype::from_array([$($a),+, $($b),+])); + let b = $longtype::from($shorttype::from_array([$($c),+, $($d),+])); + + unsafe { + assert_eq!($shorttype::from_array([$($a),+, $($c),+]), $shorttype::from(vec_xxpermdi::<_, 0>(a, b))); + assert_eq!($shorttype::from_array([$($b),+, $($c),+]), $shorttype::from(vec_xxpermdi::<_, 1>(a, b))); + assert_eq!($shorttype::from_array([$($a),+, $($d),+]), $shorttype::from(vec_xxpermdi::<_, 2>(a, b))); + assert_eq!($shorttype::from_array([$($b),+, $($d),+]), $shorttype::from(vec_xxpermdi::<_, 3>(a, b))); + } } } } diff --git a/library/stdarch/crates/core_arch/src/powerpc64/vsx.rs b/library/stdarch/crates/core_arch/src/powerpc64/vsx.rs index 7b42be8653c55..9032e7795980f 100644 --- a/library/stdarch/crates/core_arch/src/powerpc64/vsx.rs +++ b/library/stdarch/crates/core_arch/src/powerpc64/vsx.rs @@ -17,7 +17,7 @@ use stdarch_test::assert_instr; use crate::mem::transmute; #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.ppc.vsx.lxvl"] fn lxvl(a: *const u8, l: usize) -> vector_signed_int; diff --git a/library/stdarch/crates/core_arch/src/s390x/mod.rs b/library/stdarch/crates/core_arch/src/s390x/mod.rs index 7d3b3f2d99aae..5b85020072d87 100644 --- a/library/stdarch/crates/core_arch/src/s390x/mod.rs +++ b/library/stdarch/crates/core_arch/src/s390x/mod.rs @@ -2,6 +2,11 @@ pub(crate) mod macros; +/// the float and vector registers overlap therefore we cannot use any vector +/// extensions if softfloat is enabled. + +#[cfg(not(target_abi = "softfloat"))] mod vector; +#[cfg(not(target_abi = "softfloat"))] #[unstable(feature = "stdarch_s390x", issue = "130869")] pub use self::vector::*; diff --git a/library/stdarch/crates/core_arch/src/s390x/vector.rs b/library/stdarch/crates/core_arch/src/s390x/vector.rs index e1f841030c000..fc5af1b14d0cd 100644 --- a/library/stdarch/crates/core_arch/src/s390x/vector.rs +++ b/library/stdarch/crates/core_arch/src/s390x/vector.rs @@ -51,6 +51,54 @@ types! { pub struct vector_double(2 x f64); } +#[unstable(feature = "stdarch_s390x", issue = "135681")] +impl From for vector_bool_char { + #[inline] + fn from(value: m8x16) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_s390x", issue = "135681")] +impl From for m8x16 { + #[inline] + fn from(value: vector_bool_char) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_s390x", issue = "135681")] +impl From for vector_bool_short { + #[inline] + fn from(value: m16x8) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_s390x", issue = "135681")] +impl From for m16x8 { + #[inline] + fn from(value: vector_bool_short) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_s390x", issue = "135681")] +impl From for vector_bool_int { + #[inline] + fn from(value: m32x4) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_s390x", issue = "135681")] +impl From for m32x4 { + #[inline] + fn from(value: vector_bool_int) -> Self { + unsafe { transmute(value) } + } +} + #[repr(C, packed)] struct PackedTuple { x: T, @@ -287,6 +335,20 @@ unsafe extern "unadjusted" { #[link_name = "llvm.s390.vcfn"] fn vcfn(a: vector_signed_short, immarg: i32) -> vector_signed_short; #[link_name = "llvm.s390.vcnf"] fn vcnf(a: vector_signed_short, immarg: i32) -> vector_signed_short; #[link_name = "llvm.s390.vcrnfs"] fn vcrnfs(a: vector_float, b: vector_float, immarg: i32) -> vector_signed_short; + + // These are the intrinsics we'd like to use (with mode 0). However, they require + // "vector-enhancements-1" and don't have a fallback, whereas `vec_min`/`vec_max` should be + // available with just "vector". Therefore, we cannot use them. + // #[link_name = "llvm.s390.vfmaxsb"] fn vfmaxsb(a: vector_float, b: vector_float, mode: i32) -> vector_float; + // #[link_name = "llvm.s390.vfmaxdb"] fn vfmaxdb(a: vector_double, b: vector_double, mode: i32) -> vector_double; + // #[link_name = "llvm.s390.vfminsb"] fn vfminsb(a: vector_float, b: vector_float, mode: i32) -> vector_float; + // #[link_name = "llvm.s390.vfmindb"] fn vfmindb(a: vector_double, b: vector_double, mode: i32) -> vector_double; + // Instead, we use "portable" LLVM intrinsics -- even though those have the wrong semantics + // (https://github.com/rust-lang/stdarch/issues/2060), they usually do the right thing. + #[link_name = "llvm.minnum.v4f32"] fn minnum_v4f32(a: vector_float, b: vector_float) -> vector_float; + #[link_name = "llvm.minnum.v2f64"] fn minnum_v2f64(a: vector_double, b: vector_double) -> vector_double; + #[link_name = "llvm.maxnum.v4f32"] fn maxnum_v4f32(a: vector_float, b: vector_float) -> vector_float; + #[link_name = "llvm.maxnum.v2f64"] fn maxnum_v2f64(a: vector_double, b: vector_double) -> vector_double; } #[repr(simd)] @@ -732,8 +794,8 @@ mod sealed { impl_max!(vec_vmxslg, vector_unsigned_long_long, vmxlg); } - test_impl! { vec_vfmaxsb (a: vector_float, b: vector_float) -> vector_float [simd_fmax, "vector-enhancements-1" vfmaxsb ] } - test_impl! { vec_vfmaxdb (a: vector_double, b: vector_double) -> vector_double [simd_fmax, "vector-enhancements-1" vfmaxdb] } + test_impl! { vec_vfmaxsb (a: vector_float, b: vector_float) -> vector_float [maxnum_v4f32, "vector-enhancements-1" vfmaxsb] } + test_impl! { vec_vfmaxdb (a: vector_double, b: vector_double) -> vector_double [maxnum_v2f64, "vector-enhancements-1" vfmaxdb] } impl_vec_trait!([VectorMax vec_max] vec_vfmaxsb (vector_float, vector_float) -> vector_float); impl_vec_trait!([VectorMax vec_max] vec_vfmaxdb (vector_double, vector_double) -> vector_double); @@ -779,8 +841,8 @@ mod sealed { impl_min!(vec_vmnslg, vector_unsigned_long_long, vmnlg); } - test_impl! { vec_vfminsb (a: vector_float, b: vector_float) -> vector_float [simd_fmin, "vector-enhancements-1" vfminsb] } - test_impl! { vec_vfmindb (a: vector_double, b: vector_double) -> vector_double [simd_fmin, "vector-enhancements-1" vfmindb] } + test_impl! { vec_vfminsb (a: vector_float, b: vector_float) -> vector_float [minnum_v4f32, "vector-enhancements-1" vfminsb] } + test_impl! { vec_vfmindb (a: vector_double, b: vector_double) -> vector_double [minnum_v2f64, "vector-enhancements-1" vfmindb] } impl_vec_trait!([VectorMin vec_min] vec_vfminsb (vector_float, vector_float) -> vector_float); impl_vec_trait!([VectorMin vec_min] vec_vfmindb (vector_double, vector_double) -> vector_double); @@ -6051,27 +6113,16 @@ mod tests { } macro_rules! test_vec_1 { - { $name: ident, $fn:ident, f32x4, [$($a:expr),+], ~[$($d:expr),+] } => { - #[simd_test(enable = "vector")] - unsafe fn $name() { - let a: vector_float = transmute(f32x4::new($($a),+)); - - let d: vector_float = transmute(f32x4::new($($d),+)); - let r = transmute(vec_cmple(vec_abs(vec_sub($fn(a), d)), vec_splats(f32::EPSILON))); - let e = m32x4::new(true, true, true, true); - assert_eq!(e, r); - } - }; { $name: ident, $fn:ident, $ty: ident, [$($a:expr),+], [$($d:expr),+] } => { test_vec_1! { $name, $fn, $ty -> $ty, [$($a),+], [$($d),+] } }; { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($d:expr),+] } => { #[simd_test(enable = "vector")] - unsafe fn $name() { - let a: s_t_l!($ty) = transmute($ty::new($($a),+)); + fn $name() { + let a: s_t_l!($ty) = $ty::new($($a),+).into(); let d = $ty_out::new($($d),+); - let r : $ty_out = transmute($fn(a)); + let r = $ty_out::from(unsafe { $fn(a) }); assert_eq!(d, r); } } @@ -6086,35 +6137,23 @@ mod tests { }; { $name: ident, $fn:ident, $ty1: ident, $ty2: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => { #[simd_test(enable = "vector")] - unsafe fn $name() { - let a: s_t_l!($ty1) = transmute($ty1::new($($a),+)); - let b: s_t_l!($ty2) = transmute($ty2::new($($b),+)); + fn $name() { + let a: s_t_l!($ty1) = $ty1::new($($a),+).into(); + let b: s_t_l!($ty2) = $ty2::new($($b),+).into(); let d = $ty_out::new($($d),+); - let r : $ty_out = transmute($fn(a, b)); + let r = $ty_out::from(unsafe { $fn(a, b) }); assert_eq!(d, r); } }; - { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], $d:expr } => { - #[simd_test(enable = "vector")] - unsafe fn $name() { - let a: s_t_l!($ty) = transmute($ty::new($($a),+)); - let b: s_t_l!($ty) = transmute($ty::new($($b),+)); - - let r : $ty_out = transmute($fn(a, b)); - assert_eq!($d, r); - } - } } #[simd_test(enable = "vector")] - unsafe fn vec_add_i32x4_i32x4() { - let x = i32x4::new(1, 2, 3, 4); - let y = i32x4::new(4, 3, 2, 1); - let x: vector_signed_int = transmute(x); - let y: vector_signed_int = transmute(y); - let z = vec_add(x, y); - assert_eq!(i32x4::splat(5), transmute(z)); + fn vec_add_i32x4_i32x4() { + let x = vector_signed_int::from(i32x4::new(1, 2, 3, 4)); + let y = vector_signed_int::from(i32x4::new(4, 3, 2, 1)); + let z = unsafe { vec_add(x, y) }; + assert_eq!(i32x4::splat(5), i32x4::from(z)); } macro_rules! test_vec_sub { @@ -6232,11 +6271,11 @@ mod tests { macro_rules! test_vec_abs { { $name: ident, $ty: ident, $a: expr, $d: expr } => { #[simd_test(enable = "vector")] - unsafe fn $name() { - let a: s_t_l!($ty) = vec_splats($a); - let a: s_t_l!($ty) = vec_abs(a); + fn $name() { + let a: s_t_l!($ty) = unsafe { vec_splats($a) }; + let a: s_t_l!($ty) = unsafe { vec_abs(a) }; let d = $ty::splat($d); - assert_eq!(d, transmute(a)); + assert_eq!(d, $ty::from(a)); } } } @@ -6386,7 +6425,7 @@ mod tests { [0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 16], [4, 2, 1, 8] } - test_vec_2! { test_vec_sral_pos, vec_sral, u32x4, u8x16 -> i32x4, + test_vec_2! { test_vec_sral_pos, vec_sral, u32x4, u8x16 -> u32x4, [0b1000, 0b1000, 0b1000, 0b1000], [0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 16], [4, 2, 1, 8] } @@ -6423,13 +6462,13 @@ mod tests { $shorttype:ident, $longtype:ident, [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => { #[simd_test(enable = "vector")] - unsafe fn $name() { - let a: $longtype = transmute($shorttype::new($($a),+)); - let b: $longtype = transmute($shorttype::new($($b),+)); - let c: vector_unsigned_char = transmute(u8x16::new($($c),+)); - let d = $shorttype::new($($d),+); + fn $name() { + let a = $longtype::from($shorttype::from_array([$($a),+])); + let b = $longtype::from($shorttype::from_array([$($b),+])); + let c = vector_unsigned_char::from(u8x16::from_array([$($c),+])); + let d = $shorttype::from_array([$($d),+]); - let r: $shorttype = transmute(vec_perm(a, b, c)); + let r = $shorttype::from(unsafe { vec_perm(a, b, c) }); assert_eq!(d, r); } } @@ -6512,46 +6551,46 @@ mod tests { [core::f32::consts::PI, 1.0, 25.0, 2.0], [core::f32::consts::PI.sqrt(), 1.0, 5.0, core::f32::consts::SQRT_2] } - test_vec_2! { test_vec_find_any_eq, vec_find_any_eq, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_eq, vec_find_any_eq, i32x4, i32x4 -> i32x4, [1, -2, 3, -4], [-5, 3, -7, 8], - [0, 0, 0xFFFFFFFF, 0] + [0, 0, !0, 0] } - test_vec_2! { test_vec_find_any_ne, vec_find_any_ne, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_ne, vec_find_any_ne, i32x4, i32x4 -> i32x4, [1, -2, 3, -4], [-5, 3, -7, 8], - [0xFFFFFFFF, 0xFFFFFFFF, 0, 0xFFFFFFFF] + [!0, !0, 0, !0] } - test_vec_2! { test_vec_find_any_eq_idx_1, vec_find_any_eq_idx, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_eq_idx_1, vec_find_any_eq_idx, i32x4, i32x4 -> i32x4, [1, 2, 3, 4], [5, 3, 7, 8], [0, 8, 0, 0] } - test_vec_2! { test_vec_find_any_eq_idx_2, vec_find_any_eq_idx, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_eq_idx_2, vec_find_any_eq_idx, i32x4, i32x4 -> i32x4, [1, 2, 3, 4], [5, 6, 7, 8], [0, 16, 0, 0] } - test_vec_2! { test_vec_find_any_ne_idx_1, vec_find_any_ne_idx, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_ne_idx_1, vec_find_any_ne_idx, i32x4, i32x4 -> i32x4, [1, 2, 3, 4], [1, 5, 3, 4], [0, 4, 0, 0] } - test_vec_2! { test_vec_find_any_ne_idx_2, vec_find_any_ne_idx, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_ne_idx_2, vec_find_any_ne_idx, i32x4, i32x4 -> i32x4, [1, 2, 3, 4], [1, 2, 3, 4], [0, 16, 0, 0] } - test_vec_2! { test_vec_find_any_eq_or_0_idx_1, vec_find_any_eq_or_0_idx, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_eq_or_0_idx_1, vec_find_any_eq_or_0_idx, i32x4, i32x4 -> i32x4, [1, 2, 0, 4], [5, 6, 7, 8], [0, 8, 0, 0] } - test_vec_2! { test_vec_find_any_ne_or_0_idx_1, vec_find_any_ne_or_0_idx, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_ne_or_0_idx_1, vec_find_any_ne_or_0_idx, i32x4, i32x4 -> i32x4, [1, 2, 0, 4], [1, 2, 3, 4], [0, 8, 0, 0] @@ -7452,6 +7491,30 @@ mod tests { [0, !0, !0, !0] } + test_vec_2! { test_vec_max_f32, vec_max, f32x4, f32x4 -> f32x4, + [1.0, f32::NAN, f32::INFINITY, 2.0], + [-10.0, -10.0, 5.0, f32::NAN], + [1.0, -10.0, f32::INFINITY, 2.0] + } + + test_vec_2! { test_vec_min_f32, vec_min, f32x4, f32x4 -> f32x4, + [1.0, f32::NAN, f32::INFINITY, 2.0], + [-10.0, -10.0, 5.0, f32::NAN], + [-10.0, -10.0, 5.0, 2.0] + } + + test_vec_2! { test_vec_max_f64, vec_max, f64x2, f64x2 -> f64x2, + [f64::NAN, 2.0], + [-10.0, f64::NAN], + [-10.0, 2.0] + } + + test_vec_2! { test_vec_min_f64, vec_min, f64x2, f64x2 -> f64x2, + [f64::NAN, 2.0], + [-10.0, f64::NAN], + [-10.0, 2.0] + } + #[simd_test(enable = "vector")] fn test_vec_meadd() { let a = vector_unsigned_short([1, 0, 2, 0, 3, 0, 4, 0]); diff --git a/library/stdarch/crates/core_arch/src/simd.rs b/library/stdarch/crates/core_arch/src/simd.rs index 313c474792036..08ee17548a01d 100644 --- a/library/stdarch/crates/core_arch/src/simd.rs +++ b/library/stdarch/crates/core_arch/src/simd.rs @@ -20,17 +20,21 @@ pub(crate) const unsafe fn simd_imin(a: T, b: T) -> T { pub(crate) unsafe trait SimdElement: Copy + const PartialEq + crate::fmt::Debug { + // SAFETY: all bits patterns of types implementing this trait must be valid + const ZERO: Self = unsafe { crate::mem::zeroed() }; } unsafe impl SimdElement for u8 {} unsafe impl SimdElement for u16 {} unsafe impl SimdElement for u32 {} unsafe impl SimdElement for u64 {} +unsafe impl SimdElement for u128 {} unsafe impl SimdElement for i8 {} unsafe impl SimdElement for i16 {} unsafe impl SimdElement for i32 {} unsafe impl SimdElement for i64 {} +unsafe impl SimdElement for i128 {} unsafe impl SimdElement for f16 {} unsafe impl SimdElement for f32 {} @@ -42,8 +46,7 @@ pub(crate) struct Simd([T; N]); impl Simd { /// A value of this type where all elements are zeroed out. - // SAFETY: `T` implements `SimdElement`, so it is zeroable. - pub(crate) const ZERO: Self = unsafe { crate::mem::zeroed() }; + pub(crate) const ZERO: Self = Self::splat(T::ZERO); #[inline(always)] pub(crate) const fn from_array(elements: [T; N]) -> Self { @@ -86,7 +89,8 @@ impl Clone for Simd { } #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] -impl const crate::cmp::PartialEq for Simd { +#[rustfmt::skip] // FIXME: https://github.com/rust-lang/stdarch/pull/2133#issuecomment-4524350350 +const impl crate::cmp::PartialEq for Simd { #[inline] fn eq(&self, other: &Self) -> bool { self.as_array() == other.as_array() @@ -100,6 +104,103 @@ impl crate::fmt::Debug for Simd { } } +impl Simd { + #[inline] + pub(crate) const fn new(x0: T) -> Self { + Self([x0]) + } +} + +impl Simd { + #[inline] + pub(crate) const fn new(x0: T, x1: T) -> Self { + Self([x0, x1]) + } +} + +impl Simd { + #[inline] + pub(crate) const fn new(x0: T, x1: T, x2: T, x3: T) -> Self { + Self([x0, x1, x2, x3]) + } +} + +impl Simd { + #[inline] + pub(crate) const fn new(x0: T, x1: T, x2: T, x3: T, x4: T, x5: T, x6: T, x7: T) -> Self { + Self([x0, x1, x2, x3, x4, x5, x6, x7]) + } +} + +impl Simd { + #[inline] + pub(crate) const fn new( + x0: T, + x1: T, + x2: T, + x3: T, + x4: T, + x5: T, + x6: T, + x7: T, + x8: T, + x9: T, + x10: T, + x11: T, + x12: T, + x13: T, + x14: T, + x15: T, + ) -> Self { + Self([ + x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, + ]) + } +} + +impl Simd { + #[inline] + pub(crate) const fn new( + x0: T, + x1: T, + x2: T, + x3: T, + x4: T, + x5: T, + x6: T, + x7: T, + x8: T, + x9: T, + x10: T, + x11: T, + x12: T, + x13: T, + x14: T, + x15: T, + x16: T, + x17: T, + x18: T, + x19: T, + x20: T, + x21: T, + x22: T, + x23: T, + x24: T, + x25: T, + x26: T, + x27: T, + x28: T, + x29: T, + x30: T, + x31: T, + ) -> Self { + Self([ + x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, + x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31, + ]) + } +} + impl Simd { #[inline] pub(crate) const fn to_bits(self) -> Simd { @@ -142,19 +243,6 @@ impl Simd { } } -macro_rules! simd_ty { - ($id:ident [$elem_type:ty ; $len:literal]: $($param_name:ident),*) => { - pub(crate) type $id = Simd<$elem_type, $len>; - - impl $id { - #[inline(always)] - pub(crate) const fn new($($param_name: $elem_type),*) -> Self { - Self([$($param_name),*]) - } - } - } -} - #[repr(simd)] #[derive(Copy)] pub(crate) struct SimdM([T; N]); @@ -163,7 +251,6 @@ impl SimdM { #[inline(always)] const fn bool_to_internal(x: bool) -> T { // SAFETY: `T` implements `SimdElement`, so all bit patterns are valid. - let zeros = const { unsafe { crate::mem::zeroed::() } }; let ones = const { // Ideally, this would be `transmute([0xFFu8; size_of::()])`, but // `size_of::()` is not allowed to use a generic parameter there. @@ -175,13 +262,24 @@ impl SimdM { } unsafe { r.assume_init() } }; - [zeros, ones][x as usize] + [T::ZERO, ones][x as usize] + } + + #[inline] + pub(crate) const fn from_array(elements: [bool; N]) -> Self { + let mut internal = [T::ZERO; N]; + let mut i = 0; + while i < N { + internal[i] = Self::bool_to_internal(elements[i]); + i += 1; + } + Self(internal) } #[inline] #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] pub(crate) const fn splat(value: bool) -> Self { - unsafe { crate::intrinsics::simd::simd_splat(value) } + unsafe { crate::intrinsics::simd::simd_splat(Self::bool_to_internal(value)) } } #[inline] @@ -204,7 +302,8 @@ impl Clone for SimdM { } #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] -impl const crate::cmp::PartialEq for SimdM { +#[rustfmt::skip] // FIXME: https://github.com/rust-lang/stdarch/pull/2133#issuecomment-4524350350 +const impl crate::cmp::PartialEq for SimdM { #[inline] fn eq(&self, other: &Self) -> bool { self.as_array() == other.as_array() @@ -218,897 +317,102 @@ impl crate::fmt::Debug for SimdM { } } -macro_rules! simd_m_ty { - ($id:ident [$elem_type:ident ; $len:literal]: $($param_name:ident),*) => { - pub(crate) type $id = SimdM<$elem_type, $len>; - - impl $id { - #[inline(always)] - pub(crate) const fn new($($param_name: bool),*) -> Self { - Self([$(Self::bool_to_internal($param_name)),*]) - } - } - } -} - // 16-bit wide types: -simd_ty!(u8x2[u8;2]: x0, x1); -simd_ty!(i8x2[i8;2]: x0, x1); +pub(crate) type u8x2 = Simd; +pub(crate) type i8x2 = Simd; // 32-bit wide types: -simd_ty!(u8x4[u8;4]: x0, x1, x2, x3); -simd_ty!(u16x2[u16;2]: x0, x1); +pub(crate) type u8x4 = Simd; +pub(crate) type u16x2 = Simd; -simd_ty!(i8x4[i8;4]: x0, x1, x2, x3); -simd_ty!(i16x2[i16;2]: x0, x1); +pub(crate) type i8x4 = Simd; +pub(crate) type i16x2 = Simd; // 64-bit wide types: -simd_ty!( - u8x8[u8;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(u16x4[u16;4]: x0, x1, x2, x3); -simd_ty!(u32x2[u32;2]: x0, x1); -simd_ty!(u64x1[u64;1]: x1); +pub(crate) type u8x8 = Simd; +pub(crate) type u16x4 = Simd; +pub(crate) type u32x2 = Simd; +pub(crate) type u64x1 = Simd; -simd_ty!( - i8x8[i8;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(i16x4[i16;4]: x0, x1, x2, x3); -simd_ty!(i32x2[i32;2]: x0, x1); -simd_ty!(i64x1[i64;1]: x1); +pub(crate) type i8x8 = Simd; +pub(crate) type i16x4 = Simd; +pub(crate) type i32x2 = Simd; +pub(crate) type i64x1 = Simd; -simd_ty!(f32x2[f32;2]: x0, x1); -simd_ty!(f64x1[f64;1]: x1); +pub(crate) type f16x4 = Simd; +pub(crate) type f32x2 = Simd; +pub(crate) type f64x1 = Simd; // 128-bit wide types: -simd_ty!( - u8x16[u8;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); -simd_ty!( - u16x8[u16;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(u32x4[u32;4]: x0, x1, x2, x3); -simd_ty!(u64x2[u64;2]: x0, x1); - -simd_ty!( - i8x16[i8;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); -simd_ty!( - i16x8[i16;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(i32x4[i32;4]: x0, x1, x2, x3); -simd_ty!(i64x2[i64;2]: x0, x1); +pub(crate) type u8x16 = Simd; +pub(crate) type u16x8 = Simd; +pub(crate) type u32x4 = Simd; +pub(crate) type u64x2 = Simd; -simd_ty!(f16x4[f16;4]: x0, x1, x2, x3); +pub(crate) type i8x16 = Simd; +pub(crate) type i16x8 = Simd; +pub(crate) type i32x4 = Simd; +pub(crate) type i64x2 = Simd; -simd_ty!( - f16x8[f16;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(f32x4[f32;4]: x0, x1, x2, x3); -simd_ty!(f64x2[f64;2]: x0, x1); +pub(crate) type f16x8 = Simd; +pub(crate) type f32x4 = Simd; +pub(crate) type f64x2 = Simd; -simd_m_ty!( - m8x16[i8;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); -simd_m_ty!( - m16x8[i16;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_m_ty!(m32x4[i32;4]: x0, x1, x2, x3); -simd_m_ty!(m64x2[i64;2]: x0, x1); +pub(crate) type m8x16 = SimdM; +pub(crate) type m16x8 = SimdM; +pub(crate) type m32x4 = SimdM; +pub(crate) type m64x2 = SimdM; // 256-bit wide types: -simd_ty!( - u8x32[u8;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); -simd_ty!( - u16x16[u16;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); -simd_ty!( - u32x8[u32;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(u64x4[u64;4]: x0, x1, x2, x3); +pub(crate) type u8x32 = Simd; +pub(crate) type u16x16 = Simd; +pub(crate) type u32x8 = Simd; +pub(crate) type u64x4 = Simd; +pub(crate) type u128x2 = Simd; -simd_ty!( - i8x32[i8;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); -simd_ty!( - i16x16[i16;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); -simd_ty!( - i32x8[i32;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(i64x4[i64;4]: x0, x1, x2, x3); +pub(crate) type i8x32 = Simd; +pub(crate) type i16x16 = Simd; +pub(crate) type i32x8 = Simd; +pub(crate) type i64x4 = Simd; +pub(crate) type i128x2 = Simd; -simd_ty!( - f16x16[f16;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); -simd_ty!( - f32x8[f32;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(f64x4[f64;4]: x0, x1, x2, x3); +pub(crate) type f16x16 = Simd; +pub(crate) type f32x8 = Simd; +pub(crate) type f64x4 = Simd; -simd_m_ty!( - m8x32[i8;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); -simd_m_ty!( - m16x16[i16;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); -simd_m_ty!( - m32x8[i32;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); +pub(crate) type m8x32 = SimdM; +pub(crate) type m16x16 = SimdM; +pub(crate) type m32x8 = SimdM; // 512-bit wide types: -simd_ty!( - i8x64[i8;64]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31, - x32, - x33, - x34, - x35, - x36, - x37, - x38, - x39, - x40, - x41, - x42, - x43, - x44, - x45, - x46, - x47, - x48, - x49, - x50, - x51, - x52, - x53, - x54, - x55, - x56, - x57, - x58, - x59, - x60, - x61, - x62, - x63 -); - -simd_ty!( - u8x64[u8;64]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31, - x32, - x33, - x34, - x35, - x36, - x37, - x38, - x39, - x40, - x41, - x42, - x43, - x44, - x45, - x46, - x47, - x48, - x49, - x50, - x51, - x52, - x53, - x54, - x55, - x56, - x57, - x58, - x59, - x60, - x61, - x62, - x63 -); +pub(crate) type u8x64 = Simd; +pub(crate) type u16x32 = Simd; +pub(crate) type u32x16 = Simd; +pub(crate) type u64x8 = Simd; +pub(crate) type u128x4 = Simd; -simd_ty!( - i16x32[i16;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); +pub(crate) type i8x64 = Simd; +pub(crate) type i16x32 = Simd; +pub(crate) type i32x16 = Simd; +pub(crate) type i64x8 = Simd; +pub(crate) type i128x4 = Simd; -simd_ty!( - u16x32[u16;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); +pub(crate) type f16x32 = Simd; +pub(crate) type f32x16 = Simd; +pub(crate) type f64x8 = Simd; -simd_ty!( - i32x16[i32;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); - -simd_ty!( - u32x16[u32;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); - -simd_ty!( - f16x32[f16;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); -simd_ty!( - f32x16[f32;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); - -simd_ty!( - i64x8[i64;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); - -simd_ty!( - u64x8[u64;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); +// 1024-bit wide types: -simd_ty!( - f64x8[f64;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); +pub(crate) type u16x64 = Simd; +pub(crate) type u32x32 = Simd; -// 1024-bit wide types: -simd_ty!( - u16x64[u16;64]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31, - x32, - x33, - x34, - x35, - x36, - x37, - x38, - x39, - x40, - x41, - x42, - x43, - x44, - x45, - x46, - x47, - x48, - x49, - x50, - x51, - x52, - x53, - x54, - x55, - x56, - x57, - x58, - x59, - x60, - x61, - x62, - x63 -); -simd_ty!( - i32x32[i32;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); -simd_ty!( - u32x32[u32;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); +pub(crate) type i32x32 = Simd; /// Used to continue `Debug`ging SIMD types as `MySimd(1, 2, 3, 4)`, as they /// were before moving to array-based simd. diff --git a/library/stdarch/crates/core_arch/src/wasm32/memory.rs b/library/stdarch/crates/core_arch/src/wasm32/memory.rs index 90e9075e5136b..9d7b7287ede1b 100644 --- a/library/stdarch/crates/core_arch/src/wasm32/memory.rs +++ b/library/stdarch/crates/core_arch/src/wasm32/memory.rs @@ -2,9 +2,11 @@ use stdarch_test::assert_instr; unsafe extern "unadjusted" { - #[link_name = "llvm.wasm.memory.grow"] + #[cfg_attr(target_pointer_width = "32", link_name = "llvm.wasm.memory.grow.i32")] + #[cfg_attr(target_pointer_width = "64", link_name = "llvm.wasm.memory.grow.i64")] fn llvm_memory_grow(mem: u32, pages: usize) -> usize; - #[link_name = "llvm.wasm.memory.size"] + #[cfg_attr(target_pointer_width = "32", link_name = "llvm.wasm.memory.size.i32")] + #[cfg_attr(target_pointer_width = "64", link_name = "llvm.wasm.memory.size.i64")] fn llvm_memory_size(mem: u32) -> usize; } diff --git a/library/stdarch/crates/core_arch/src/wasm32/simd128.rs b/library/stdarch/crates/core_arch/src/wasm32/simd128.rs index c864d6a516e08..b52702f44e622 100644 --- a/library/stdarch/crates/core_arch/src/wasm32/simd128.rs +++ b/library/stdarch/crates/core_arch/src/wasm32/simd128.rs @@ -86,10 +86,6 @@ unsafe extern "unadjusted" { fn llvm_i8x16_all_true(x: simd::i8x16) -> i32; #[link_name = "llvm.wasm.bitmask.v16i8"] fn llvm_bitmask_i8x16(a: simd::i8x16) -> i32; - #[link_name = "llvm.wasm.narrow.signed.v16i8.v8i16"] - fn llvm_narrow_i8x16_s(a: simd::i16x8, b: simd::i16x8) -> simd::i8x16; - #[link_name = "llvm.wasm.narrow.unsigned.v16i8.v8i16"] - fn llvm_narrow_i8x16_u(a: simd::i16x8, b: simd::i16x8) -> simd::i8x16; #[link_name = "llvm.wasm.avgr.unsigned.v16i8"] fn llvm_avgr_u_i8x16(a: simd::i8x16, b: simd::i8x16) -> simd::i8x16; @@ -103,10 +99,6 @@ unsafe extern "unadjusted" { fn llvm_i16x8_all_true(x: simd::i16x8) -> i32; #[link_name = "llvm.wasm.bitmask.v8i16"] fn llvm_bitmask_i16x8(a: simd::i16x8) -> i32; - #[link_name = "llvm.wasm.narrow.signed.v8i16.v4i32"] - fn llvm_narrow_i16x8_s(a: simd::i32x4, b: simd::i32x4) -> simd::i16x8; - #[link_name = "llvm.wasm.narrow.unsigned.v8i16.v4i32"] - fn llvm_narrow_i16x8_u(a: simd::i32x4, b: simd::i32x4) -> simd::i16x8; #[link_name = "llvm.wasm.avgr.unsigned.v8i16"] fn llvm_avgr_u_i16x8(a: simd::i16x8, b: simd::i16x8) -> simd::i16x8; @@ -2281,7 +2273,23 @@ pub use i8x16_bitmask as u8x16_bitmask; #[doc(alias("i8x16.narrow_i16x8_s"))] #[stable(feature = "wasm_simd", since = "1.54.0")] pub fn i8x16_narrow_i16x8(a: v128, b: v128) -> v128 { - unsafe { llvm_narrow_i8x16_s(a.as_i16x8(), b.as_i16x8()).v128() } + unsafe { + let v: simd::i16x16 = simd_shuffle!( + a.as_i16x8(), + b.as_i16x8(), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ); + + let max = simd_splat(i16::from(i8::MAX)); + let min = simd_splat(i16::from(i8::MIN)); + + let v = simd_select(simd_gt::<_, simd::i16x16>(v, max), max, v); + let v = simd_select(simd_lt::<_, simd::i16x16>(v, min), min, v); + + let v: simd::i8x16 = simd_cast(v); + + v.v128() + } } /// Converts two input vectors into a smaller lane vector by narrowing each @@ -2295,7 +2303,23 @@ pub fn i8x16_narrow_i16x8(a: v128, b: v128) -> v128 { #[doc(alias("i8x16.narrow_i16x8_u"))] #[stable(feature = "wasm_simd", since = "1.54.0")] pub fn u8x16_narrow_i16x8(a: v128, b: v128) -> v128 { - unsafe { llvm_narrow_i8x16_u(a.as_i16x8(), b.as_i16x8()).v128() } + unsafe { + let v: simd::i16x16 = simd_shuffle!( + a.as_i16x8(), + b.as_i16x8(), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ); + + let max = simd_splat(i16::from(u8::MAX)); + let min = simd_splat(i16::from(u8::MIN)); + + let v = simd_select(simd_gt::<_, simd::i16x16>(v, max), max, v); + let v = simd_select(simd_lt::<_, simd::i16x16>(v, min), min, v); + + let v: simd::u8x16 = simd_cast(v); + + v.v128() + } } /// Shifts each lane to the left by the specified number of bits. @@ -2593,7 +2617,19 @@ pub use i16x8_bitmask as u16x8_bitmask; #[doc(alias("i16x8.narrow_i32x4_s"))] #[stable(feature = "wasm_simd", since = "1.54.0")] pub fn i16x8_narrow_i32x4(a: v128, b: v128) -> v128 { - unsafe { llvm_narrow_i16x8_s(a.as_i32x4(), b.as_i32x4()).v128() } + unsafe { + let v: simd::i32x8 = simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]); + + let max = simd_splat(i32::from(i16::MAX)); + let min = simd_splat(i32::from(i16::MIN)); + + let v = simd_select(simd_gt::<_, simd::i32x8>(v, max), max, v); + let v = simd_select(simd_lt::<_, simd::i32x8>(v, min), min, v); + + let v: simd::i16x8 = simd_cast(v); + + v.v128() + } } /// Converts two input vectors into a smaller lane vector by narrowing each @@ -2607,7 +2643,19 @@ pub fn i16x8_narrow_i32x4(a: v128, b: v128) -> v128 { #[doc(alias("i16x8.narrow_i32x4_u"))] #[stable(feature = "wasm_simd", since = "1.54.0")] pub fn u16x8_narrow_i32x4(a: v128, b: v128) -> v128 { - unsafe { llvm_narrow_i16x8_u(a.as_i32x4(), b.as_i32x4()).v128() } + unsafe { + let v: simd::i32x8 = simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]); + + let max = simd_splat(i32::from(u16::MAX)); + let min = simd_splat(i32::from(u16::MIN)); + + let v = simd_select(simd_gt::<_, simd::i32x8>(v, max), max, v); + let v = simd_select(simd_lt::<_, simd::i32x8>(v, min), min, v); + + let v: simd::u16x8 = simd_cast(v); + + v.v128() + } } /// Converts low half of the smaller lane vector to a larger lane @@ -4275,7 +4323,7 @@ mod tests { let vec = i64x2_load_extend_i32x2(arr.as_ptr()); compare_bytes(vec, i64x2(-1, 1)); let vec = i64x2_load_extend_u32x2(arr.as_ptr() as *const u32); - compare_bytes(vec, i64x2(u32::max_value().into(), 1)); + compare_bytes(vec, i64x2(u32::MAX.into(), 1)); } } diff --git a/library/stdarch/crates/core_arch/src/x86/aes.rs b/library/stdarch/crates/core_arch/src/x86/aes.rs index d07ab4dc2a01e..ecb09a6a9099f 100644 --- a/library/stdarch/crates/core_arch/src/x86/aes.rs +++ b/library/stdarch/crates/core_arch/src/x86/aes.rs @@ -13,7 +13,7 @@ use crate::core_arch::x86::__m128i; use stdarch_test::assert_instr; #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.aesni.aesdec"] fn aesdec(a: __m128i, round_key: __m128i) -> __m128i; #[link_name = "llvm.x86.aesni.aesdeclast"] diff --git a/library/stdarch/crates/core_arch/src/x86/avx.rs b/library/stdarch/crates/core_arch/src/x86/avx.rs index 7b4b210bacf4c..f5ddff6457aea 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx.rs @@ -1097,6 +1097,9 @@ pub const fn _mm256_cvtsi256_si32(a: __m256i) -> i32 { /// Zeroes the contents of all XMM or YMM registers. /// +/// This operation is purely a performance hint for the CPU and has no effect on the Abstract +/// Machine state. +/// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_zeroall) #[inline] #[target_feature(enable = "avx")] @@ -1109,6 +1112,9 @@ pub fn _mm256_zeroall() { /// Zeroes the upper 128 bits of all YMM registers; /// the lower 128-bits of the registers are unmodified. /// +/// This operation is purely a performance hint for the CPU and has no effect on the Abstract +/// Machine state. +/// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_zeroupper) #[inline] #[target_feature(enable = "avx")] @@ -2426,7 +2432,6 @@ pub const fn _mm256_setzero_si256() -> __m256i { #[inline] #[target_feature(enable = "avx")] // This intrinsic has no corresponding instruction. -#[cfg_attr(test, assert_instr(vinsertf128))] #[stable(feature = "simd_x86", since = "1.27.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_set_pd(a: f64, b: f64, c: f64, d: f64) -> __m256d { @@ -3287,7 +3292,7 @@ pub const fn _mm256_cvtss_f32(a: __m256) -> f32 { // LLVM intrinsics used in the above functions #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.avx.round.pd.256"] fn roundpd256(a: __m256d, b: i32) -> __m256d; #[link_name = "llvm.x86.avx.round.ps.256"] @@ -4008,13 +4013,11 @@ mod tests { } #[simd_test(enable = "avx")] - #[cfg_attr(miri, ignore)] // Register-level operation not supported by Miri fn test_mm256_zeroall() { _mm256_zeroall(); } #[simd_test(enable = "avx")] - #[cfg_attr(miri, ignore)] // Register-level operation not supported by Miri fn test_mm256_zeroupper() { _mm256_zeroupper(); } @@ -4485,7 +4488,7 @@ mod tests { } #[simd_test(enable = "avx")] - #[cfg_attr(miri, ignore)] // Non-temporal store, which is not supported by Miri + #[cfg_attr(miri, ignore)] // Inline asm (for non-temporal store), which is not supported by Miri fn test_mm256_stream_si256() { let a = _mm256_setr_epi64x(1, 2, 3, 4); let mut r = _mm256_undefined_si256(); @@ -4497,7 +4500,7 @@ mod tests { } #[simd_test(enable = "avx")] - #[cfg_attr(miri, ignore)] // Non-temporal store, which is not supported by Miri + #[cfg_attr(miri, ignore)] // Inline asm (for non-temporal store), which is not supported by Miri fn test_mm256_stream_pd() { #[repr(align(32))] struct Memory { @@ -4516,7 +4519,7 @@ mod tests { } #[simd_test(enable = "avx")] - #[cfg_attr(miri, ignore)] // Non-temporal store, which is not supported by Miri + #[cfg_attr(miri, ignore)] // Inline asm (for non-temporal store), which is not supported by Miri fn test_mm256_stream_ps() { #[repr(align(32))] struct Memory { diff --git a/library/stdarch/crates/core_arch/src/x86/avx2.rs b/library/stdarch/crates/core_arch/src/x86/avx2.rs index 6a39a0aaf8feb..6925ba8e27028 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx2.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx2.rs @@ -991,7 +991,21 @@ pub const fn _mm256_hadd_epi32(a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vphaddsw))] #[stable(feature = "simd_x86", since = "1.27.0")] pub fn _mm256_hadds_epi16(a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(phaddsw(a.as_i16x16(), b.as_i16x16())) } + let a = a.as_i16x16(); + let b = b.as_i16x16(); + unsafe { + let even: i16x16 = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 16, 18, 20, 22, 8, 10, 12, 14, 24, 26, 28, 30] + ); + let odd: i16x16 = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 17, 19, 21, 23, 9, 11, 13, 15, 25, 27, 29, 31] + ); + simd_saturating_add(even, odd).as_m256i() + } } /// Horizontally subtract adjacent pairs of 16-bit integers in `a` and `b`. @@ -1047,7 +1061,21 @@ pub const fn _mm256_hsub_epi32(a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vphsubsw))] #[stable(feature = "simd_x86", since = "1.27.0")] pub fn _mm256_hsubs_epi16(a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(phsubsw(a.as_i16x16(), b.as_i16x16())) } + let a = a.as_i16x16(); + let b = b.as_i16x16(); + unsafe { + let even: i16x16 = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 16, 18, 20, 22, 8, 10, 12, 14, 24, 26, 28, 30] + ); + let odd: i16x16 = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 17, 19, 21, 23, 9, 11, 13, 15, 25, 27, 29, 31] + ); + simd_saturating_sub(even, odd).as_m256i() + } } /// Returns values from `slice` at offsets determined by `offsets * scale`, @@ -2287,7 +2315,7 @@ pub const fn _mm256_or_si256(a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(simd_or(a.as_i32x8(), b.as_i32x8())) } } -/// Converts packed 16-bit integers from `a` and `b` to packed 8-bit integers +/// Converts packed signed 16-bit integers from `a` and `b` to packed 8-bit integers /// using signed saturation /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_packs_epi16) @@ -2295,11 +2323,33 @@ pub const fn _mm256_or_si256(a: __m256i, b: __m256i) -> __m256i { #[target_feature(enable = "avx2")] #[cfg_attr(test, assert_instr(vpacksswb))] #[stable(feature = "simd_x86", since = "1.27.0")] -pub fn _mm256_packs_epi16(a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(packsswb(a.as_i16x16(), b.as_i16x16())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm256_packs_epi16(a: __m256i, b: __m256i) -> __m256i { + unsafe { + let max = simd_splat(i8::MAX as i16); + let min = simd_splat(i8::MIN as i16); + + let clamped_a = simd_imax(simd_imin(a.as_i16x16(), max), min) + .as_m256i() + .as_i8x32(); + let clamped_b = simd_imax(simd_imin(b.as_i16x16(), max), min) + .as_m256i() + .as_i8x32(); + + #[rustfmt::skip] + const IDXS: [u32; 32] = [ + 00, 02, 04, 06, 08, 10, 12, 14, // a-lo i16 to i8 conversions + 32, 34, 36, 38, 40, 42, 44, 46, // b-lo + 16, 18, 20, 22, 24, 26, 28, 30, // a-hi + 48, 50, 52, 54, 56, 58, 60, 62, // b-hi + ]; + let result: i8x32 = simd_shuffle!(clamped_a, clamped_b, IDXS); + + result.as_m256i() + } } -/// Converts packed 32-bit integers from `a` and `b` to packed 16-bit integers +/// Converts packed signed 32-bit integers from `a` and `b` to packed 16-bit integers /// using signed saturation /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_packs_epi32) @@ -2307,11 +2357,33 @@ pub fn _mm256_packs_epi16(a: __m256i, b: __m256i) -> __m256i { #[target_feature(enable = "avx2")] #[cfg_attr(test, assert_instr(vpackssdw))] #[stable(feature = "simd_x86", since = "1.27.0")] -pub fn _mm256_packs_epi32(a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(packssdw(a.as_i32x8(), b.as_i32x8())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm256_packs_epi32(a: __m256i, b: __m256i) -> __m256i { + unsafe { + let max = simd_splat(i16::MAX as i32); + let min = simd_splat(i16::MIN as i32); + + let clamped_a = simd_imax(simd_imin(a.as_i32x8(), max), min) + .as_m256i() + .as_i16x16(); + let clamped_b = simd_imax(simd_imin(b.as_i32x8(), max), min) + .as_m256i() + .as_i16x16(); + + #[rustfmt::skip] + const IDXS: [u32; 16] = [ + 00, 02, 04, 06, // a-lo i32 to i16 conversions + 16, 18, 20, 22, // b-lo + 08, 10, 12, 14, // a-hi + 24, 26, 28, 30, // b-hi + ]; + let result: i16x16 = simd_shuffle!(clamped_a, clamped_b, IDXS); + + result.as_m256i() + } } -/// Converts packed 16-bit integers from `a` and `b` to packed 8-bit integers +/// Converts packed signed 16-bit integers from `a` and `b` to packed 8-bit integers /// using unsigned saturation /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_packus_epi16) @@ -2319,11 +2391,33 @@ pub fn _mm256_packs_epi32(a: __m256i, b: __m256i) -> __m256i { #[target_feature(enable = "avx2")] #[cfg_attr(test, assert_instr(vpackuswb))] #[stable(feature = "simd_x86", since = "1.27.0")] -pub fn _mm256_packus_epi16(a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(packuswb(a.as_i16x16(), b.as_i16x16())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm256_packus_epi16(a: __m256i, b: __m256i) -> __m256i { + unsafe { + let max = simd_splat(u8::MAX as i16); + let min = simd_splat(u8::MIN as i16); + + let clamped_a = simd_imax(simd_imin(a.as_i16x16(), max), min) + .as_m256i() + .as_i8x32(); + let clamped_b = simd_imax(simd_imin(b.as_i16x16(), max), min) + .as_m256i() + .as_i8x32(); + + #[rustfmt::skip] + const IDXS: [u32; 32] = [ + 00, 02, 04, 06, 08, 10, 12, 14, // a-lo i16 to u8 conversions + 32, 34, 36, 38, 40, 42, 44, 46, // b-lo + 16, 18, 20, 22, 24, 26, 28, 30, // a-hi + 48, 50, 52, 54, 56, 58, 60, 62, // b-hi + ]; + let result: i8x32 = simd_shuffle!(clamped_a, clamped_b, IDXS); + + result.as_m256i() + } } -/// Converts packed 32-bit integers from `a` and `b` to packed 16-bit integers +/// Converts packed signed 32-bit integers from `a` and `b` to packed 16-bit integers /// using unsigned saturation /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_packus_epi32) @@ -2331,8 +2425,30 @@ pub fn _mm256_packus_epi16(a: __m256i, b: __m256i) -> __m256i { #[target_feature(enable = "avx2")] #[cfg_attr(test, assert_instr(vpackusdw))] #[stable(feature = "simd_x86", since = "1.27.0")] -pub fn _mm256_packus_epi32(a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(packusdw(a.as_i32x8(), b.as_i32x8())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm256_packus_epi32(a: __m256i, b: __m256i) -> __m256i { + unsafe { + let max = simd_splat(u16::MAX as i32); + let min = simd_splat(u16::MIN as i32); + + let clamped_a = simd_imax(simd_imin(a.as_i32x8(), max), min) + .as_m256i() + .as_i16x16(); + let clamped_b = simd_imax(simd_imin(b.as_i32x8(), max), min) + .as_m256i() + .as_i16x16(); + + #[rustfmt::skip] + const IDXS: [u32; 16] = [ + 00, 02, 04, 06, // a-lo i32 to u16 conversions + 16, 18, 20, 22, // b-lo + 08, 10, 12, 14, // a-hi + 24, 26, 28, 30, // b-hi + ]; + let result: i16x16 = simd_shuffle!(clamped_a, clamped_b, IDXS); + + result.as_m256i() + } } /// Permutes packed 32-bit integers from `a` according to the content of `b`. @@ -3790,11 +3906,7 @@ pub const fn _mm256_extract_epi16(a: __m256i) -> i32 { } #[allow(improper_ctypes)] -unsafe extern "C" { - #[link_name = "llvm.x86.avx2.phadd.sw"] - fn phaddsw(a: i16x16, b: i16x16) -> i16x16; - #[link_name = "llvm.x86.avx2.phsub.sw"] - fn phsubsw(a: i16x16, b: i16x16) -> i16x16; +unsafe extern "unadjusted" { #[link_name = "llvm.x86.avx2.pmadd.wd"] fn pmaddwd(a: i16x16, b: i16x16) -> i32x8; #[link_name = "llvm.x86.avx2.pmadd.ub.sw"] @@ -3803,14 +3915,6 @@ unsafe extern "C" { fn mpsadbw(a: u8x32, b: u8x32, imm8: i8) -> u16x16; #[link_name = "llvm.x86.avx2.pmul.hr.sw"] fn pmulhrsw(a: i16x16, b: i16x16) -> i16x16; - #[link_name = "llvm.x86.avx2.packsswb"] - fn packsswb(a: i16x16, b: i16x16) -> i8x32; - #[link_name = "llvm.x86.avx2.packssdw"] - fn packssdw(a: i32x8, b: i32x8) -> i16x16; - #[link_name = "llvm.x86.avx2.packuswb"] - fn packuswb(a: i16x16, b: i16x16) -> u8x32; - #[link_name = "llvm.x86.avx2.packusdw"] - fn packusdw(a: i32x8, b: i32x8) -> u16x16; #[link_name = "llvm.x86.avx2.psad.bw"] fn psadbw(a: u8x32, b: u8x32) -> u64x4; #[link_name = "llvm.x86.avx2.psign.b"] @@ -4653,6 +4757,26 @@ mod tests { assert_eq_m256i(r, e); } + #[target_feature(enable = "avx2")] + #[cfg_attr(test, assert_instr(vpmaddwd))] + unsafe fn test_mm256_madd_epi16_mul_one(v: __m256i) -> __m256i { + // This is a trick used in the adler32 algorithm to get a widening addition. The + // multiplication by 1 is trivial, but must not be optimized out because then the vpmaddwd + // instruction is no longer selected. The assert_instr verifies that this is the case. + let one_v = _mm256_set1_epi16(1); + _mm256_madd_epi16(v, one_v) + } + + #[target_feature(enable = "avx2")] + #[cfg_attr(test, assert_instr(vpmaddwd))] + unsafe fn test_mm256_madd_epi16_shl(v: __m256i) -> __m256i { + // This is a trick used in the base64 algorithm to get a widening addition. Instead of a + // multiplication, a vector shl is used. In LLVM 22 that breaks the pattern recognition + // for the automatic optimization to vpmaddwd. + let shift_value = _mm256_set1_epi32(12i32); + _mm256_madd_epi16(v, shift_value) + } + #[simd_test(enable = "avx2")] const fn test_mm256_inserti128_si256() { let a = _mm256_setr_epi64x(1, 2, 3, 4); @@ -4944,7 +5068,7 @@ mod tests { } #[simd_test(enable = "avx2")] - fn test_mm256_packs_epi16() { + const fn test_mm256_packs_epi16() { let a = _mm256_set1_epi16(2); let b = _mm256_set1_epi16(4); let r = _mm256_packs_epi16(a, b); @@ -4960,7 +5084,7 @@ mod tests { } #[simd_test(enable = "avx2")] - fn test_mm256_packs_epi32() { + const fn test_mm256_packs_epi32() { let a = _mm256_set1_epi32(2); let b = _mm256_set1_epi32(4); let r = _mm256_packs_epi32(a, b); @@ -4970,7 +5094,7 @@ mod tests { } #[simd_test(enable = "avx2")] - fn test_mm256_packus_epi16() { + const fn test_mm256_packus_epi16() { let a = _mm256_set1_epi16(2); let b = _mm256_set1_epi16(4); let r = _mm256_packus_epi16(a, b); @@ -4986,7 +5110,7 @@ mod tests { } #[simd_test(enable = "avx2")] - fn test_mm256_packus_epi32() { + const fn test_mm256_packus_epi32() { let a = _mm256_set1_epi32(2); let b = _mm256_set1_epi32(4); let r = _mm256_packus_epi32(a, b); diff --git a/library/stdarch/crates/core_arch/src/x86/avx512bf16.rs b/library/stdarch/crates/core_arch/src/x86/avx512bf16.rs index 66eef063eed8b..230a4f3754cad 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512bf16.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512bf16.rs @@ -2,7 +2,6 @@ //! //! [AVX512BF16 intrinsics]: https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769&avx512techs=AVX512_BF16 -use crate::arch::asm; use crate::core_arch::{simd::*, x86::*}; use crate::intrinsics::simd::*; @@ -10,13 +9,15 @@ use crate::intrinsics::simd::*; use stdarch_test::assert_instr; #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.avx512bf16.cvtne2ps2bf16.128"] fn cvtne2ps2bf16(a: f32x4, b: f32x4) -> i16x8; #[link_name = "llvm.x86.avx512bf16.cvtne2ps2bf16.256"] fn cvtne2ps2bf16_256(a: f32x8, b: f32x8) -> i16x16; #[link_name = "llvm.x86.avx512bf16.cvtne2ps2bf16.512"] fn cvtne2ps2bf16_512(a: f32x16, b: f32x16) -> i16x32; + #[link_name = "llvm.x86.avx512bf16.mask.cvtneps2bf16.128"] + fn cvtneps2bf16_128(a: f32x4, src: i16x8, k: __mmask8) -> i16x8; #[link_name = "llvm.x86.avx512bf16.cvtneps2bf16.256"] fn cvtneps2bf16_256(a: f32x8) -> i16x8; #[link_name = "llvm.x86.avx512bf16.cvtneps2bf16.512"] @@ -519,16 +520,7 @@ pub fn _mm_cvtsbh_ss(a: bf16) -> f32 { #[cfg_attr(test, assert_instr("vcvtneps2bf16"))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_cvtneps_pbh(a: __m128) -> __m128bh { - unsafe { - let mut dst: __m128bh; - asm!( - "vcvtneps2bf16 {dst}, {src}", - dst = lateout(xmm_reg) dst, - src = in(xmm_reg) a, - options(pure, nomem, nostack, preserves_flags) - ); - dst - } + _mm_mask_cvtneps_pbh(__m128bh::splat(0), !0, a) } /// Converts packed single-precision (32-bit) floating-point elements in a to packed BF16 (16-bit) @@ -541,17 +533,7 @@ pub fn _mm_cvtneps_pbh(a: __m128) -> __m128bh { #[cfg_attr(test, assert_instr("vcvtneps2bf16"))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_cvtneps_pbh(src: __m128bh, k: __mmask8, a: __m128) -> __m128bh { - unsafe { - let mut dst = src; - asm!( - "vcvtneps2bf16 {dst}{{{k}}},{src}", - dst = inlateout(xmm_reg) dst, - src = in(xmm_reg) a, - k = in(kreg) k, - options(pure, nomem, nostack, preserves_flags) - ); - dst - } + unsafe { cvtneps2bf16_128(a.as_f32x4(), src.as_i16x8(), k).as_m128bh() } } /// Converts packed single-precision (32-bit) floating-point elements in a to packed BF16 (16-bit) @@ -564,17 +546,7 @@ pub fn _mm_mask_cvtneps_pbh(src: __m128bh, k: __mmask8, a: __m128) -> __m128bh { #[cfg_attr(test, assert_instr("vcvtneps2bf16"))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_cvtneps_pbh(k: __mmask8, a: __m128) -> __m128bh { - unsafe { - let mut dst: __m128bh; - asm!( - "vcvtneps2bf16 {dst}{{{k}}}{{z}},{src}", - dst = lateout(xmm_reg) dst, - src = in(xmm_reg) a, - k = in(kreg) k, - options(pure, nomem, nostack, preserves_flags) - ); - dst - } + _mm_mask_cvtneps_pbh(__m128bh::splat(0), k, a) } /// Converts a single-precision (32-bit) floating-point element in a to a BF16 (16-bit) floating-point diff --git a/library/stdarch/crates/core_arch/src/x86/avx512bitalg.rs b/library/stdarch/crates/core_arch/src/x86/avx512bitalg.rs index 6dd4e6b33a3ba..344130fb6e720 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512bitalg.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512bitalg.rs @@ -27,13 +27,13 @@ use crate::mem::transmute; use stdarch_test::assert_instr; #[allow(improper_ctypes)] -unsafe extern "C" { - #[link_name = "llvm.x86.avx512.mask.vpshufbitqmb.512"] - fn bitshuffle_512(data: i8x64, indices: i8x64, mask: __mmask64) -> __mmask64; - #[link_name = "llvm.x86.avx512.mask.vpshufbitqmb.256"] - fn bitshuffle_256(data: i8x32, indices: i8x32, mask: __mmask32) -> __mmask32; - #[link_name = "llvm.x86.avx512.mask.vpshufbitqmb.128"] - fn bitshuffle_128(data: i8x16, indices: i8x16, mask: __mmask16) -> __mmask16; +unsafe extern "unadjusted" { + #[link_name = "llvm.x86.avx512.vpshufbitqmb.512"] + fn bitshuffle_512(data: i8x64, indices: i8x64) -> __mmask64; + #[link_name = "llvm.x86.avx512.vpshufbitqmb.256"] + fn bitshuffle_256(data: i8x32, indices: i8x32) -> __mmask32; + #[link_name = "llvm.x86.avx512.vpshufbitqmb.128"] + fn bitshuffle_128(data: i8x16, indices: i8x16) -> __mmask16; } /// For each packed 16-bit integer maps the value to the number of logical 1 bits. @@ -370,7 +370,7 @@ pub const fn _mm_mask_popcnt_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufbitqmb))] pub fn _mm512_bitshuffle_epi64_mask(b: __m512i, c: __m512i) -> __mmask64 { - unsafe { bitshuffle_512(b.as_i8x64(), c.as_i8x64(), !0) } + unsafe { bitshuffle_512(b.as_i8x64(), c.as_i8x64()) } } /// Considers the input `b` as packed 64-bit integers and `c` as packed 8-bit integers. @@ -386,7 +386,7 @@ pub fn _mm512_bitshuffle_epi64_mask(b: __m512i, c: __m512i) -> __mmask64 { #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufbitqmb))] pub fn _mm512_mask_bitshuffle_epi64_mask(k: __mmask64, b: __m512i, c: __m512i) -> __mmask64 { - unsafe { bitshuffle_512(b.as_i8x64(), c.as_i8x64(), k) } + _mm512_bitshuffle_epi64_mask(b, c) & k } /// Considers the input `b` as packed 64-bit integers and `c` as packed 8-bit integers. @@ -399,7 +399,7 @@ pub fn _mm512_mask_bitshuffle_epi64_mask(k: __mmask64, b: __m512i, c: __m512i) - #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufbitqmb))] pub fn _mm256_bitshuffle_epi64_mask(b: __m256i, c: __m256i) -> __mmask32 { - unsafe { bitshuffle_256(b.as_i8x32(), c.as_i8x32(), !0) } + unsafe { bitshuffle_256(b.as_i8x32(), c.as_i8x32()) } } /// Considers the input `b` as packed 64-bit integers and `c` as packed 8-bit integers. @@ -415,7 +415,7 @@ pub fn _mm256_bitshuffle_epi64_mask(b: __m256i, c: __m256i) -> __mmask32 { #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufbitqmb))] pub fn _mm256_mask_bitshuffle_epi64_mask(k: __mmask32, b: __m256i, c: __m256i) -> __mmask32 { - unsafe { bitshuffle_256(b.as_i8x32(), c.as_i8x32(), k) } + _mm256_bitshuffle_epi64_mask(b, c) & k } /// Considers the input `b` as packed 64-bit integers and `c` as packed 8-bit integers. @@ -428,7 +428,7 @@ pub fn _mm256_mask_bitshuffle_epi64_mask(k: __mmask32, b: __m256i, c: __m256i) - #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufbitqmb))] pub fn _mm_bitshuffle_epi64_mask(b: __m128i, c: __m128i) -> __mmask16 { - unsafe { bitshuffle_128(b.as_i8x16(), c.as_i8x16(), !0) } + unsafe { bitshuffle_128(b.as_i8x16(), c.as_i8x16()) } } /// Considers the input `b` as packed 64-bit integers and `c` as packed 8-bit integers. @@ -444,7 +444,7 @@ pub fn _mm_bitshuffle_epi64_mask(b: __m128i, c: __m128i) -> __mmask16 { #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufbitqmb))] pub fn _mm_mask_bitshuffle_epi64_mask(k: __mmask16, b: __m128i, c: __m128i) -> __mmask16 { - unsafe { bitshuffle_128(b.as_i8x16(), c.as_i8x16(), k) } + _mm_bitshuffle_epi64_mask(b, c) & k } #[cfg(test)] diff --git a/library/stdarch/crates/core_arch/src/x86/avx512bw.rs b/library/stdarch/crates/core_arch/src/x86/avx512bw.rs index 8e074fdcfa486..50d57b4964489 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512bw.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512bw.rs @@ -6523,8 +6523,34 @@ pub fn _mm_maskz_maddubs_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackssdw))] -pub fn _mm512_packs_epi32(a: __m512i, b: __m512i) -> __m512i { - unsafe { transmute(vpackssdw(a.as_i32x16(), b.as_i32x16())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_packs_epi32(a: __m512i, b: __m512i) -> __m512i { + unsafe { + let max = simd_splat(i16::MAX as i32); + let min = simd_splat(i16::MIN as i32); + + let clamped_a = simd_imax(simd_imin(a.as_i32x16(), max), min) + .as_m512i() + .as_i16x32(); + let clamped_b = simd_imax(simd_imin(b.as_i32x16(), max), min) + .as_m512i() + .as_i16x32(); + + #[rustfmt::skip] + const IDXS: [u32; 32] = [ + 00, 02, 04, 06, + 32, 34, 36, 38, + 08, 10, 12, 14, + 40, 42, 44, 46, + 16, 18, 20, 22, + 48, 50, 52, 54, + 24, 26, 28, 30, + 56, 58, 60, 62, + ]; + let result: i16x32 = simd_shuffle!(clamped_a, clamped_b, IDXS); + + result.as_m512i() + } } /// Convert packed signed 32-bit integers from a and b to packed 16-bit integers using signed saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -6534,7 +6560,13 @@ pub fn _mm512_packs_epi32(a: __m512i, b: __m512i) -> __m512i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackssdw))] -pub fn _mm512_mask_packs_epi32(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_mask_packs_epi32( + src: __m512i, + k: __mmask32, + a: __m512i, + b: __m512i, +) -> __m512i { unsafe { let pack = _mm512_packs_epi32(a, b).as_i16x32(); transmute(simd_select_bitmask(k, pack, src.as_i16x32())) @@ -6548,7 +6580,8 @@ pub fn _mm512_mask_packs_epi32(src: __m512i, k: __mmask32, a: __m512i, b: __m512 #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackssdw))] -pub fn _mm512_maskz_packs_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_maskz_packs_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { let pack = _mm512_packs_epi32(a, b).as_i16x32(); transmute(simd_select_bitmask(k, pack, i16x32::ZERO)) @@ -6562,7 +6595,13 @@ pub fn _mm512_maskz_packs_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512i #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackssdw))] -pub fn _mm256_mask_packs_epi32(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm256_mask_packs_epi32( + src: __m256i, + k: __mmask16, + a: __m256i, + b: __m256i, +) -> __m256i { unsafe { let pack = _mm256_packs_epi32(a, b).as_i16x16(); transmute(simd_select_bitmask(k, pack, src.as_i16x16())) @@ -6590,7 +6629,8 @@ pub fn _mm256_maskz_packs_epi32(k: __mmask16, a: __m256i, b: __m256i) -> __m256i #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackssdw))] -pub fn _mm_mask_packs_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_mask_packs_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { let pack = _mm_packs_epi32(a, b).as_i16x8(); transmute(simd_select_bitmask(k, pack, src.as_i16x8())) @@ -6604,7 +6644,8 @@ pub fn _mm_mask_packs_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) - #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackssdw))] -pub fn _mm_maskz_packs_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_maskz_packs_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { let pack = _mm_packs_epi32(a, b).as_i16x8(); transmute(simd_select_bitmask(k, pack, i16x8::ZERO)) @@ -6618,8 +6659,34 @@ pub fn _mm_maskz_packs_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpacksswb))] -pub fn _mm512_packs_epi16(a: __m512i, b: __m512i) -> __m512i { - unsafe { transmute(vpacksswb(a.as_i16x32(), b.as_i16x32())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_packs_epi16(a: __m512i, b: __m512i) -> __m512i { + unsafe { + let max = simd_splat(i8::MAX as i16); + let min = simd_splat(i8::MIN as i16); + + let clamped_a = simd_imax(simd_imin(a.as_i16x32(), max), min) + .as_m512i() + .as_i8x64(); + let clamped_b = simd_imax(simd_imin(b.as_i16x32(), max), min) + .as_m512i() + .as_i8x64(); + + #[rustfmt::skip] + const IDXS: [u32; 64] = [ + 000, 002, 004, 006, 008, 010, 012, 014, + 064, 066, 068, 070, 072, 074, 076, 078, + 016, 018, 020, 022, 024, 026, 028, 030, + 080, 082, 084, 086, 088, 090, 092, 094, + 032, 034, 036, 038, 040, 042, 044, 046, + 096, 098, 100, 102, 104, 106, 108, 110, + 048, 050, 052, 054, 056, 058, 060, 062, + 112, 114, 116, 118, 120, 122, 124, 126, + ]; + let result: i8x64 = simd_shuffle!(clamped_a, clamped_b, IDXS); + + result.as_m512i() + } } /// Convert packed signed 16-bit integers from a and b to packed 8-bit integers using signed saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -6629,7 +6696,13 @@ pub fn _mm512_packs_epi16(a: __m512i, b: __m512i) -> __m512i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpacksswb))] -pub fn _mm512_mask_packs_epi16(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_mask_packs_epi16( + src: __m512i, + k: __mmask64, + a: __m512i, + b: __m512i, +) -> __m512i { unsafe { let pack = _mm512_packs_epi16(a, b).as_i8x64(); transmute(simd_select_bitmask(k, pack, src.as_i8x64())) @@ -6643,7 +6716,8 @@ pub fn _mm512_mask_packs_epi16(src: __m512i, k: __mmask64, a: __m512i, b: __m512 #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpacksswb))] -pub fn _mm512_maskz_packs_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_maskz_packs_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { let pack = _mm512_packs_epi16(a, b).as_i8x64(); transmute(simd_select_bitmask(k, pack, i8x64::ZERO)) @@ -6657,7 +6731,13 @@ pub fn _mm512_maskz_packs_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512i #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpacksswb))] -pub fn _mm256_mask_packs_epi16(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm256_mask_packs_epi16( + src: __m256i, + k: __mmask32, + a: __m256i, + b: __m256i, +) -> __m256i { unsafe { let pack = _mm256_packs_epi16(a, b).as_i8x32(); transmute(simd_select_bitmask(k, pack, src.as_i8x32())) @@ -6671,7 +6751,8 @@ pub fn _mm256_mask_packs_epi16(src: __m256i, k: __mmask32, a: __m256i, b: __m256 #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpacksswb))] -pub fn _mm256_maskz_packs_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm256_maskz_packs_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { let pack = _mm256_packs_epi16(a, b).as_i8x32(); transmute(simd_select_bitmask(k, pack, i8x32::ZERO)) @@ -6685,7 +6766,8 @@ pub fn _mm256_maskz_packs_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256i #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpacksswb))] -pub fn _mm_mask_packs_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_mask_packs_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { let pack = _mm_packs_epi16(a, b).as_i8x16(); transmute(simd_select_bitmask(k, pack, src.as_i8x16())) @@ -6699,7 +6781,8 @@ pub fn _mm_mask_packs_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpacksswb))] -pub fn _mm_maskz_packs_epi16(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_maskz_packs_epi16(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { let pack = _mm_packs_epi16(a, b).as_i8x16(); transmute(simd_select_bitmask(k, pack, i8x16::ZERO)) @@ -6713,8 +6796,34 @@ pub fn _mm_maskz_packs_epi16(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackusdw))] -pub fn _mm512_packus_epi32(a: __m512i, b: __m512i) -> __m512i { - unsafe { transmute(vpackusdw(a.as_i32x16(), b.as_i32x16())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_packus_epi32(a: __m512i, b: __m512i) -> __m512i { + unsafe { + let max = simd_splat(u16::MAX as i32); + let min = simd_splat(u16::MIN as i32); + + let clamped_a = simd_imax(simd_imin(a.as_i32x16(), max), min) + .as_m512i() + .as_i16x32(); + let clamped_b = simd_imax(simd_imin(b.as_i32x16(), max), min) + .as_m512i() + .as_i16x32(); + + #[rustfmt::skip] + const IDXS: [u32; 32] = [ + 00, 02, 04, 06, + 32, 34, 36, 38, + 08, 10, 12, 14, + 40, 42, 44, 46, + 16, 18, 20, 22, + 48, 50, 52, 54, + 24, 26, 28, 30, + 56, 58, 60, 62, + ]; + let result: i16x32 = simd_shuffle!(clamped_a, clamped_b, IDXS); + + result.as_m512i() + } } /// Convert packed signed 32-bit integers from a and b to packed 16-bit integers using unsigned saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -6724,7 +6833,13 @@ pub fn _mm512_packus_epi32(a: __m512i, b: __m512i) -> __m512i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackusdw))] -pub fn _mm512_mask_packus_epi32(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_mask_packus_epi32( + src: __m512i, + k: __mmask32, + a: __m512i, + b: __m512i, +) -> __m512i { unsafe { let pack = _mm512_packus_epi32(a, b).as_i16x32(); transmute(simd_select_bitmask(k, pack, src.as_i16x32())) @@ -6738,7 +6853,8 @@ pub fn _mm512_mask_packus_epi32(src: __m512i, k: __mmask32, a: __m512i, b: __m51 #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackusdw))] -pub fn _mm512_maskz_packus_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_maskz_packus_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { let pack = _mm512_packus_epi32(a, b).as_i16x32(); transmute(simd_select_bitmask(k, pack, i16x32::ZERO)) @@ -6752,7 +6868,13 @@ pub fn _mm512_maskz_packus_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512 #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackusdw))] -pub fn _mm256_mask_packus_epi32(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm256_mask_packus_epi32( + src: __m256i, + k: __mmask16, + a: __m256i, + b: __m256i, +) -> __m256i { unsafe { let pack = _mm256_packus_epi32(a, b).as_i16x16(); transmute(simd_select_bitmask(k, pack, src.as_i16x16())) @@ -6766,7 +6888,8 @@ pub fn _mm256_mask_packus_epi32(src: __m256i, k: __mmask16, a: __m256i, b: __m25 #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackusdw))] -pub fn _mm256_maskz_packus_epi32(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm256_maskz_packus_epi32(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { let pack = _mm256_packus_epi32(a, b).as_i16x16(); transmute(simd_select_bitmask(k, pack, i16x16::ZERO)) @@ -6780,7 +6903,8 @@ pub fn _mm256_maskz_packus_epi32(k: __mmask16, a: __m256i, b: __m256i) -> __m256 #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackusdw))] -pub fn _mm_mask_packus_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_mask_packus_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { let pack = _mm_packus_epi32(a, b).as_i16x8(); transmute(simd_select_bitmask(k, pack, src.as_i16x8())) @@ -6794,7 +6918,8 @@ pub fn _mm_mask_packus_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackusdw))] -pub fn _mm_maskz_packus_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_maskz_packus_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { let pack = _mm_packus_epi32(a, b).as_i16x8(); transmute(simd_select_bitmask(k, pack, i16x8::ZERO)) @@ -6808,8 +6933,34 @@ pub fn _mm_maskz_packus_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackuswb))] -pub fn _mm512_packus_epi16(a: __m512i, b: __m512i) -> __m512i { - unsafe { transmute(vpackuswb(a.as_i16x32(), b.as_i16x32())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_packus_epi16(a: __m512i, b: __m512i) -> __m512i { + unsafe { + let max = simd_splat(u8::MAX as i16); + let min = simd_splat(u8::MIN as i16); + + let clamped_a = simd_imax(simd_imin(a.as_i16x32(), max), min) + .as_m512i() + .as_i8x64(); + let clamped_b = simd_imax(simd_imin(b.as_i16x32(), max), min) + .as_m512i() + .as_i8x64(); + + #[rustfmt::skip] + const IDXS: [u32; 64] = [ + 000, 002, 004, 006, 008, 010, 012, 014, + 064, 066, 068, 070, 072, 074, 076, 078, + 016, 018, 020, 022, 024, 026, 028, 030, + 080, 082, 084, 086, 088, 090, 092, 094, + 032, 034, 036, 038, 040, 042, 044, 046, + 096, 098, 100, 102, 104, 106, 108, 110, + 048, 050, 052, 054, 056, 058, 060, 062, + 112, 114, 116, 118, 120, 122, 124, 126, + ]; + let result: i8x64 = simd_shuffle!(clamped_a, clamped_b, IDXS); + + result.as_m512i() + } } /// Convert packed signed 16-bit integers from a and b to packed 8-bit integers using unsigned saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -6819,7 +6970,13 @@ pub fn _mm512_packus_epi16(a: __m512i, b: __m512i) -> __m512i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackuswb))] -pub fn _mm512_mask_packus_epi16(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_mask_packus_epi16( + src: __m512i, + k: __mmask64, + a: __m512i, + b: __m512i, +) -> __m512i { unsafe { let pack = _mm512_packus_epi16(a, b).as_i8x64(); transmute(simd_select_bitmask(k, pack, src.as_i8x64())) @@ -6833,7 +6990,8 @@ pub fn _mm512_mask_packus_epi16(src: __m512i, k: __mmask64, a: __m512i, b: __m51 #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackuswb))] -pub fn _mm512_maskz_packus_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_maskz_packus_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { let pack = _mm512_packus_epi16(a, b).as_i8x64(); transmute(simd_select_bitmask(k, pack, i8x64::ZERO)) @@ -6847,7 +7005,13 @@ pub fn _mm512_maskz_packus_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512 #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackuswb))] -pub fn _mm256_mask_packus_epi16(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm256_mask_packus_epi16( + src: __m256i, + k: __mmask32, + a: __m256i, + b: __m256i, +) -> __m256i { unsafe { let pack = _mm256_packus_epi16(a, b).as_i8x32(); transmute(simd_select_bitmask(k, pack, src.as_i8x32())) @@ -6861,7 +7025,8 @@ pub fn _mm256_mask_packus_epi16(src: __m256i, k: __mmask32, a: __m256i, b: __m25 #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackuswb))] -pub fn _mm256_maskz_packus_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm256_maskz_packus_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { let pack = _mm256_packus_epi16(a, b).as_i8x32(); transmute(simd_select_bitmask(k, pack, i8x32::ZERO)) @@ -6875,7 +7040,8 @@ pub fn _mm256_maskz_packus_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256 #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackuswb))] -pub fn _mm_mask_packus_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_mask_packus_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { let pack = _mm_packus_epi16(a, b).as_i8x16(); transmute(simd_select_bitmask(k, pack, src.as_i8x16())) @@ -6889,7 +7055,8 @@ pub fn _mm_mask_packus_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackuswb))] -pub fn _mm_maskz_packus_epi16(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_maskz_packus_epi16(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { let pack = _mm_packus_epi16(a, b).as_i8x16(); transmute(simd_select_bitmask(k, pack, i8x16::ZERO)) @@ -11586,7 +11753,7 @@ pub const fn _mm_maskz_cvtepi16_epi8(k: __mmask8, a: __m128i) -> __m128i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_cvtsepi16_epi8(a: __m512i) -> __m256i { unsafe { simd_cast::<_, i8x32>(simd_imax( @@ -11604,7 +11771,7 @@ pub const fn _mm512_cvtsepi16_epi8(a: __m512i) -> __m256i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_cvtsepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m256i { unsafe { simd_select_bitmask(k, _mm512_cvtsepi16_epi8(a).as_i8x32(), src.as_i8x32()).as_m256i() @@ -11618,7 +11785,7 @@ pub const fn _mm512_mask_cvtsepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_cvtsepi16_epi8(k: __mmask32, a: __m512i) -> __m256i { unsafe { simd_select_bitmask(k, _mm512_cvtsepi16_epi8(a).as_i8x32(), i8x32::ZERO).as_m256i() } } @@ -11630,7 +11797,7 @@ pub const fn _mm512_maskz_cvtsepi16_epi8(k: __mmask32, a: __m512i) -> __m256i { #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_cvtsepi16_epi8(a: __m256i) -> __m128i { unsafe { simd_cast::<_, i8x16>(simd_imax( @@ -11648,7 +11815,7 @@ pub const fn _mm256_cvtsepi16_epi8(a: __m256i) -> __m128i { #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_cvtsepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m128i { unsafe { simd_select_bitmask(k, _mm256_cvtsepi16_epi8(a).as_i8x16(), src.as_i8x16()).as_m128i() @@ -11662,7 +11829,7 @@ pub const fn _mm256_mask_cvtsepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_cvtsepi16_epi8(k: __mmask16, a: __m256i) -> __m128i { unsafe { simd_select_bitmask(k, _mm256_cvtsepi16_epi8(a).as_i8x16(), i8x16::ZERO).as_m128i() } } @@ -11707,7 +11874,7 @@ pub fn _mm_maskz_cvtsepi16_epi8(k: __mmask8, a: __m128i) -> __m128i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_cvtusepi16_epi8(a: __m512i) -> __m256i { unsafe { simd_cast::<_, u8x32>(simd_imin(a.as_u16x32(), u16x32::splat(u8::MAX as _))).as_m256i() @@ -11721,7 +11888,7 @@ pub const fn _mm512_cvtusepi16_epi8(a: __m512i) -> __m256i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_cvtusepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m256i { unsafe { simd_select_bitmask(k, _mm512_cvtusepi16_epi8(a).as_u8x32(), src.as_u8x32()).as_m256i() @@ -11735,7 +11902,7 @@ pub const fn _mm512_mask_cvtusepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_cvtusepi16_epi8(k: __mmask32, a: __m512i) -> __m256i { unsafe { simd_select_bitmask(k, _mm512_cvtusepi16_epi8(a).as_u8x32(), u8x32::ZERO).as_m256i() } } @@ -11747,7 +11914,7 @@ pub const fn _mm512_maskz_cvtusepi16_epi8(k: __mmask32, a: __m512i) -> __m256i { #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_cvtusepi16_epi8(a: __m256i) -> __m128i { unsafe { simd_cast::<_, u8x16>(simd_imin(a.as_u16x16(), u16x16::splat(u8::MAX as _))).as_m128i() @@ -11761,7 +11928,7 @@ pub const fn _mm256_cvtusepi16_epi8(a: __m256i) -> __m128i { #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_cvtusepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m128i { unsafe { simd_select_bitmask(k, _mm256_cvtusepi16_epi8(a).as_u8x16(), src.as_u8x16()).as_m128i() @@ -11775,7 +11942,7 @@ pub const fn _mm256_mask_cvtusepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_cvtusepi16_epi8(k: __mmask16, a: __m256i) -> __m128i { unsafe { simd_select_bitmask(k, _mm256_cvtusepi16_epi8(a).as_u8x16(), u8x16::ZERO).as_m128i() } } @@ -12476,7 +12643,14 @@ pub unsafe fn _mm512_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32, #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] pub unsafe fn _mm256_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, a: __m256i) { - vpmovswbmem256(mem_addr, a.as_i16x16(), k); + let mask = simd_select_bitmask(k, i16x16::splat(!0), i16x16::ZERO); + + let max = simd_splat(i16::from(i8::MAX)); + let min = simd_splat(i16::from(i8::MIN)); + + let v = simd_imax(simd_imin(a.as_i16x16(), max), min); + let truncated: i8x16 = simd_cast(v); + simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, truncated); } /// Convert packed signed 16-bit integers in a to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr. @@ -12487,7 +12661,14 @@ pub unsafe fn _mm256_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] pub unsafe fn _mm_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) { - vpmovswbmem128(mem_addr, a.as_i16x8(), k); + let mask = simd_select_bitmask(k, i16x8::splat(!0), i16x8::ZERO); + + let max = simd_splat(i16::from(i8::MAX)); + let min = simd_splat(i16::from(i8::MIN)); + + let v = simd_imax(simd_imin(a.as_i16x8(), max), min); + let truncated: i8x8 = simd_cast(v); + simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, truncated); } /// Convert packed 16-bit integers in a to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr. @@ -12497,7 +12678,7 @@ pub unsafe fn _mm_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovwb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const unsafe fn _mm512_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32, a: __m512i) { let result = _mm512_cvtepi16_epi8(a).as_i8x32(); let mask = simd_select_bitmask(k, i8x32::splat(!0), i8x32::ZERO); @@ -12511,7 +12692,7 @@ pub const unsafe fn _mm512_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mma #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovwb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const unsafe fn _mm256_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, a: __m256i) { let result = _mm256_cvtepi16_epi8(a).as_i8x16(); let mask = simd_select_bitmask(k, i8x16::splat(!0), i8x16::ZERO); @@ -12525,7 +12706,7 @@ pub const unsafe fn _mm256_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mma #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovwb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const unsafe fn _mm_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) { let result: i8x8 = simd_shuffle!( _mm_cvtepi16_epi8(a).as_i8x16(), @@ -12555,7 +12736,12 @@ pub unsafe fn _mm512_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32 #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] pub unsafe fn _mm256_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, a: __m256i) { - vpmovuswbmem256(mem_addr, a.as_i16x16(), k); + let mask = simd_select_bitmask(k, i16x16::splat(!0), i16x16::ZERO); + let mem_addr = mem_addr.cast::(); + let max = simd_splat(u16::from(u8::MAX)); + + let truncated: u8x16 = simd_cast(simd_imin(a.as_u16x16(), max)); + simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, truncated); } /// Convert packed unsigned 16-bit integers in a to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr. @@ -12566,11 +12752,19 @@ pub unsafe fn _mm256_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16 #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] pub unsafe fn _mm_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) { - vpmovuswbmem128(mem_addr, a.as_i16x8(), k); + let mask = simd_select_bitmask(k, i16x8::splat(!0), i16x8::ZERO); + let mem_addr = mem_addr.cast::(); + let max = simd_splat(u16::from(u8::MAX)); + + let v = a.as_u16x8(); + let v = simd_imin(v, max); + + let truncated: u8x8 = simd_cast(v); + simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, truncated); } #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.avx512.pmul.hr.sw.512"] fn vpmulhrsw(a: i16x32, b: i16x32) -> i16x32; @@ -12579,15 +12773,6 @@ unsafe extern "C" { #[link_name = "llvm.x86.avx512.pmaddubs.w.512"] fn vpmaddubsw(a: u8x64, b: i8x64) -> i16x32; - #[link_name = "llvm.x86.avx512.packssdw.512"] - fn vpackssdw(a: i32x16, b: i32x16) -> i16x32; - #[link_name = "llvm.x86.avx512.packsswb.512"] - fn vpacksswb(a: i16x32, b: i16x32) -> i8x64; - #[link_name = "llvm.x86.avx512.packusdw.512"] - fn vpackusdw(a: i32x16, b: i32x16) -> u16x32; - #[link_name = "llvm.x86.avx512.packuswb.512"] - fn vpackuswb(a: i16x32, b: i16x32) -> u8x64; - #[link_name = "llvm.x86.avx512.psll.w.512"] fn vpsllw(a: i16x32, count: i16x8) -> i16x32; @@ -12632,17 +12817,9 @@ unsafe extern "C" { #[link_name = "llvm.x86.avx512.mask.pmovs.wb.mem.512"] fn vpmovswbmem(mem_addr: *mut i8, a: i16x32, mask: u32); - #[link_name = "llvm.x86.avx512.mask.pmovs.wb.mem.256"] - fn vpmovswbmem256(mem_addr: *mut i8, a: i16x16, mask: u16); - #[link_name = "llvm.x86.avx512.mask.pmovs.wb.mem.128"] - fn vpmovswbmem128(mem_addr: *mut i8, a: i16x8, mask: u8); #[link_name = "llvm.x86.avx512.mask.pmovus.wb.mem.512"] fn vpmovuswbmem(mem_addr: *mut i8, a: i16x32, mask: u32); - #[link_name = "llvm.x86.avx512.mask.pmovus.wb.mem.256"] - fn vpmovuswbmem256(mem_addr: *mut i8, a: i16x16, mask: u16); - #[link_name = "llvm.x86.avx512.mask.pmovus.wb.mem.128"] - fn vpmovuswbmem128(mem_addr: *mut i8, a: i16x8, mask: u8); } #[cfg(test)] @@ -17683,7 +17860,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_packs_epi32() { + const fn test_mm512_packs_epi32() { let a = _mm512_set1_epi32(i32::MAX); let b = _mm512_set1_epi32(1); let r = _mm512_packs_epi32(a, b); @@ -17694,7 +17871,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_mask_packs_epi32() { + const fn test_mm512_mask_packs_epi32() { let a = _mm512_set1_epi32(i32::MAX); let b = _mm512_set1_epi32(1 << 16 | 1); let r = _mm512_mask_packs_epi32(a, 0, a, b); @@ -17707,7 +17884,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_maskz_packs_epi32() { + const fn test_mm512_maskz_packs_epi32() { let a = _mm512_set1_epi32(i32::MAX); let b = _mm512_set1_epi32(1); let r = _mm512_maskz_packs_epi32(0, a, b); @@ -17720,7 +17897,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm256_mask_packs_epi32() { + const fn test_mm256_mask_packs_epi32() { let a = _mm256_set1_epi32(i32::MAX); let b = _mm256_set1_epi32(1 << 16 | 1); let r = _mm256_mask_packs_epi32(a, 0, a, b); @@ -17744,7 +17921,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm_mask_packs_epi32() { + const fn test_mm_mask_packs_epi32() { let a = _mm_set1_epi32(i32::MAX); let b = _mm_set1_epi32(1 << 16 | 1); let r = _mm_mask_packs_epi32(a, 0, a, b); @@ -17755,7 +17932,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm_maskz_packs_epi32() { + const fn test_mm_maskz_packs_epi32() { let a = _mm_set1_epi32(i32::MAX); let b = _mm_set1_epi32(1); let r = _mm_maskz_packs_epi32(0, a, b); @@ -17766,7 +17943,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_packs_epi16() { + const fn test_mm512_packs_epi16() { let a = _mm512_set1_epi16(i16::MAX); let b = _mm512_set1_epi16(1); let r = _mm512_packs_epi16(a, b); @@ -17779,7 +17956,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_mask_packs_epi16() { + const fn test_mm512_mask_packs_epi16() { let a = _mm512_set1_epi16(i16::MAX); let b = _mm512_set1_epi16(1 << 8 | 1); let r = _mm512_mask_packs_epi16(a, 0, a, b); @@ -17799,7 +17976,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_maskz_packs_epi16() { + const fn test_mm512_maskz_packs_epi16() { let a = _mm512_set1_epi16(i16::MAX); let b = _mm512_set1_epi16(1); let r = _mm512_maskz_packs_epi16(0, a, b); @@ -17818,7 +17995,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm256_mask_packs_epi16() { + const fn test_mm256_mask_packs_epi16() { let a = _mm256_set1_epi16(i16::MAX); let b = _mm256_set1_epi16(1 << 8 | 1); let r = _mm256_mask_packs_epi16(a, 0, a, b); @@ -17831,7 +18008,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm256_maskz_packs_epi16() { + const fn test_mm256_maskz_packs_epi16() { let a = _mm256_set1_epi16(i16::MAX); let b = _mm256_set1_epi16(1); let r = _mm256_maskz_packs_epi16(0, a, b); @@ -17844,7 +18021,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm_mask_packs_epi16() { + const fn test_mm_mask_packs_epi16() { let a = _mm_set1_epi16(i16::MAX); let b = _mm_set1_epi16(1 << 8 | 1); let r = _mm_mask_packs_epi16(a, 0, a, b); @@ -17856,7 +18033,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm_maskz_packs_epi16() { + const fn test_mm_maskz_packs_epi16() { let a = _mm_set1_epi16(i16::MAX); let b = _mm_set1_epi16(1); let r = _mm_maskz_packs_epi16(0, a, b); @@ -17868,7 +18045,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_packus_epi32() { + const fn test_mm512_packus_epi32() { let a = _mm512_set1_epi32(-1); let b = _mm512_set1_epi32(1); let r = _mm512_packus_epi32(a, b); @@ -17879,7 +18056,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_mask_packus_epi32() { + const fn test_mm512_mask_packus_epi32() { let a = _mm512_set1_epi32(-1); let b = _mm512_set1_epi32(1 << 16 | 1); let r = _mm512_mask_packus_epi32(a, 0, a, b); @@ -17892,7 +18069,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_maskz_packus_epi32() { + const fn test_mm512_maskz_packus_epi32() { let a = _mm512_set1_epi32(-1); let b = _mm512_set1_epi32(1); let r = _mm512_maskz_packus_epi32(0, a, b); @@ -17905,7 +18082,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm256_mask_packus_epi32() { + const fn test_mm256_mask_packus_epi32() { let a = _mm256_set1_epi32(-1); let b = _mm256_set1_epi32(1 << 16 | 1); let r = _mm256_mask_packus_epi32(a, 0, a, b); @@ -17916,7 +18093,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm256_maskz_packus_epi32() { + const fn test_mm256_maskz_packus_epi32() { let a = _mm256_set1_epi32(-1); let b = _mm256_set1_epi32(1); let r = _mm256_maskz_packus_epi32(0, a, b); @@ -17927,7 +18104,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm_mask_packus_epi32() { + const fn test_mm_mask_packus_epi32() { let a = _mm_set1_epi32(-1); let b = _mm_set1_epi32(1 << 16 | 1); let r = _mm_mask_packus_epi32(a, 0, a, b); @@ -17938,7 +18115,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm_maskz_packus_epi32() { + const fn test_mm_maskz_packus_epi32() { let a = _mm_set1_epi32(-1); let b = _mm_set1_epi32(1); let r = _mm_maskz_packus_epi32(0, a, b); @@ -17949,7 +18126,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_packus_epi16() { + const fn test_mm512_packus_epi16() { let a = _mm512_set1_epi16(-1); let b = _mm512_set1_epi16(1); let r = _mm512_packus_epi16(a, b); @@ -17962,7 +18139,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_mask_packus_epi16() { + const fn test_mm512_mask_packus_epi16() { let a = _mm512_set1_epi16(-1); let b = _mm512_set1_epi16(1 << 8 | 1); let r = _mm512_mask_packus_epi16(a, 0, a, b); @@ -17982,7 +18159,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_maskz_packus_epi16() { + const fn test_mm512_maskz_packus_epi16() { let a = _mm512_set1_epi16(-1); let b = _mm512_set1_epi16(1); let r = _mm512_maskz_packus_epi16(0, a, b); @@ -18001,7 +18178,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm256_mask_packus_epi16() { + const fn test_mm256_mask_packus_epi16() { let a = _mm256_set1_epi16(-1); let b = _mm256_set1_epi16(1 << 8 | 1); let r = _mm256_mask_packus_epi16(a, 0, a, b); @@ -18014,7 +18191,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm256_maskz_packus_epi16() { + const fn test_mm256_maskz_packus_epi16() { let a = _mm256_set1_epi16(-1); let b = _mm256_set1_epi16(1); let r = _mm256_maskz_packus_epi16(0, a, b); @@ -18027,7 +18204,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm_mask_packus_epi16() { + const fn test_mm_mask_packus_epi16() { let a = _mm_set1_epi16(-1); let b = _mm_set1_epi16(1 << 8 | 1); let r = _mm_mask_packus_epi16(a, 0, a, b); @@ -18038,7 +18215,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm_maskz_packus_epi16() { + const fn test_mm_maskz_packus_epi16() { let a = _mm_set1_epi16(-1); let b = _mm_set1_epi16(1); let r = _mm_maskz_packus_epi16(0, a, b); diff --git a/library/stdarch/crates/core_arch/src/x86/avx512cd.rs b/library/stdarch/crates/core_arch/src/x86/avx512cd.rs index 4082433e70759..378bc3617ed63 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512cd.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512cd.rs @@ -563,7 +563,7 @@ pub const fn _mm_maskz_lzcnt_epi64(k: __mmask8, a: __m128i) -> __m128i { } #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.avx512.conflict.d.512"] fn vpconflictd(a: i32x16) -> i32x16; #[link_name = "llvm.x86.avx512.conflict.d.256"] diff --git a/library/stdarch/crates/core_arch/src/x86/avx512dq.rs b/library/stdarch/crates/core_arch/src/x86/avx512dq.rs index 9e1a4c0b29558..5fe40b7541549 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512dq.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512dq.rs @@ -6865,7 +6865,7 @@ pub fn _mm_maskz_reduce_ss(k: __mmask8, a: __m128, b: __m128) - #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_fpclass_pd_mask(a: __m128d) -> __mmask8 { static_assert_uimm_bits!(IMM8, 8); - _mm_mask_fpclass_pd_mask::(0xff, a) + unsafe { vfpclasspd_128(a.as_f64x2(), IMM8) } } /// Test packed double-precision (64-bit) floating-point elements in a for special categories specified @@ -6889,10 +6889,7 @@ pub fn _mm_fpclass_pd_mask(a: __m128d) -> __mmask8 { #[rustc_legacy_const_generics(2)] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_fpclass_pd_mask(k1: __mmask8, a: __m128d) -> __mmask8 { - unsafe { - static_assert_uimm_bits!(IMM8, 8); - transmute(vfpclasspd_128(a.as_f64x2(), IMM8, k1)) - } + _mm_fpclass_pd_mask::(a) & k1 } /// Test packed double-precision (64-bit) floating-point elements in a for special categories specified @@ -6916,7 +6913,7 @@ pub fn _mm_mask_fpclass_pd_mask(k1: __mmask8, a: __m128d) -> __ #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_fpclass_pd_mask(a: __m256d) -> __mmask8 { static_assert_uimm_bits!(IMM8, 8); - _mm256_mask_fpclass_pd_mask::(0xff, a) + unsafe { vfpclasspd_256(a.as_f64x4(), IMM8) } } /// Test packed double-precision (64-bit) floating-point elements in a for special categories specified @@ -6940,10 +6937,7 @@ pub fn _mm256_fpclass_pd_mask(a: __m256d) -> __mmask8 { #[rustc_legacy_const_generics(2)] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_fpclass_pd_mask(k1: __mmask8, a: __m256d) -> __mmask8 { - unsafe { - static_assert_uimm_bits!(IMM8, 8); - transmute(vfpclasspd_256(a.as_f64x4(), IMM8, k1)) - } + _mm256_fpclass_pd_mask::(a) & k1 } /// Test packed double-precision (64-bit) floating-point elements in a for special categories specified @@ -6967,7 +6961,7 @@ pub fn _mm256_mask_fpclass_pd_mask(k1: __mmask8, a: __m256d) -> #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_fpclass_pd_mask(a: __m512d) -> __mmask8 { static_assert_uimm_bits!(IMM8, 8); - _mm512_mask_fpclass_pd_mask::(0xff, a) + unsafe { vfpclasspd_512(a.as_f64x8(), IMM8) } } /// Test packed double-precision (64-bit) floating-point elements in a for special categories specified @@ -6991,10 +6985,7 @@ pub fn _mm512_fpclass_pd_mask(a: __m512d) -> __mmask8 { #[rustc_legacy_const_generics(2)] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_fpclass_pd_mask(k1: __mmask8, a: __m512d) -> __mmask8 { - unsafe { - static_assert_uimm_bits!(IMM8, 8); - transmute(vfpclasspd_512(a.as_f64x8(), IMM8, k1)) - } + _mm512_fpclass_pd_mask::(a) & k1 } /// Test packed single-precision (32-bit) floating-point elements in a for special categories specified @@ -7018,7 +7009,7 @@ pub fn _mm512_mask_fpclass_pd_mask(k1: __mmask8, a: __m512d) -> #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_fpclass_ps_mask(a: __m128) -> __mmask8 { static_assert_uimm_bits!(IMM8, 8); - _mm_mask_fpclass_ps_mask::(0xff, a) + unsafe { vfpclassps_128(a.as_f32x4(), IMM8) } } /// Test packed single-precision (32-bit) floating-point elements in a for special categories specified @@ -7042,10 +7033,7 @@ pub fn _mm_fpclass_ps_mask(a: __m128) -> __mmask8 { #[rustc_legacy_const_generics(2)] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_fpclass_ps_mask(k1: __mmask8, a: __m128) -> __mmask8 { - unsafe { - static_assert_uimm_bits!(IMM8, 8); - transmute(vfpclassps_128(a.as_f32x4(), IMM8, k1)) - } + _mm_fpclass_ps_mask::(a) & k1 } /// Test packed single-precision (32-bit) floating-point elements in a for special categories specified @@ -7069,7 +7057,7 @@ pub fn _mm_mask_fpclass_ps_mask(k1: __mmask8, a: __m128) -> __m #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_fpclass_ps_mask(a: __m256) -> __mmask8 { static_assert_uimm_bits!(IMM8, 8); - _mm256_mask_fpclass_ps_mask::(0xff, a) + unsafe { vfpclassps_256(a.as_f32x8(), IMM8) } } /// Test packed single-precision (32-bit) floating-point elements in a for special categories specified @@ -7093,10 +7081,7 @@ pub fn _mm256_fpclass_ps_mask(a: __m256) -> __mmask8 { #[rustc_legacy_const_generics(2)] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_fpclass_ps_mask(k1: __mmask8, a: __m256) -> __mmask8 { - unsafe { - static_assert_uimm_bits!(IMM8, 8); - transmute(vfpclassps_256(a.as_f32x8(), IMM8, k1)) - } + _mm256_fpclass_ps_mask::(a) & k1 } /// Test packed single-precision (32-bit) floating-point elements in a for special categories specified @@ -7120,7 +7105,7 @@ pub fn _mm256_mask_fpclass_ps_mask(k1: __mmask8, a: __m256) -> #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_fpclass_ps_mask(a: __m512) -> __mmask16 { static_assert_uimm_bits!(IMM8, 8); - _mm512_mask_fpclass_ps_mask::(0xffff, a) + unsafe { vfpclassps_512(a.as_f32x16(), IMM8) } } /// Test packed single-precision (32-bit) floating-point elements in a for special categories specified @@ -7144,10 +7129,7 @@ pub fn _mm512_fpclass_ps_mask(a: __m512) -> __mmask16 { #[rustc_legacy_const_generics(2)] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_fpclass_ps_mask(k1: __mmask16, a: __m512) -> __mmask16 { - unsafe { - static_assert_uimm_bits!(IMM8, 8); - transmute(vfpclassps_512(a.as_f32x16(), IMM8, k1)) - } + _mm512_fpclass_ps_mask::(a) & k1 } /// Test the lower double-precision (64-bit) floating-point element in a for special categories specified @@ -7253,7 +7235,7 @@ pub fn _mm_mask_fpclass_ss_mask(k1: __mmask8, a: __m128) -> __m } #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.avx512.sitofp.round.v2f64.v2i64"] fn vcvtqq2pd_128(a: i64x2, rounding: i32) -> f64x2; #[link_name = "llvm.x86.avx512.sitofp.round.v4f64.v4i64"] @@ -7377,19 +7359,19 @@ unsafe extern "C" { #[link_name = "llvm.x86.avx512.mask.reduce.ss"] fn vreducess(a: f32x4, b: f32x4, src: f32x4, k: __mmask8, imm8: i32, sae: i32) -> f32x4; - #[link_name = "llvm.x86.avx512.mask.fpclass.pd.128"] - fn vfpclasspd_128(a: f64x2, imm8: i32, k: __mmask8) -> __mmask8; - #[link_name = "llvm.x86.avx512.mask.fpclass.pd.256"] - fn vfpclasspd_256(a: f64x4, imm8: i32, k: __mmask8) -> __mmask8; - #[link_name = "llvm.x86.avx512.mask.fpclass.pd.512"] - fn vfpclasspd_512(a: f64x8, imm8: i32, k: __mmask8) -> __mmask8; - - #[link_name = "llvm.x86.avx512.mask.fpclass.ps.128"] - fn vfpclassps_128(a: f32x4, imm8: i32, k: __mmask8) -> __mmask8; - #[link_name = "llvm.x86.avx512.mask.fpclass.ps.256"] - fn vfpclassps_256(a: f32x8, imm8: i32, k: __mmask8) -> __mmask8; - #[link_name = "llvm.x86.avx512.mask.fpclass.ps.512"] - fn vfpclassps_512(a: f32x16, imm8: i32, k: __mmask16) -> __mmask16; + #[link_name = "llvm.x86.avx512.fpclass.pd.128"] + fn vfpclasspd_128(a: f64x2, imm8: i32) -> __mmask8; + #[link_name = "llvm.x86.avx512.fpclass.pd.256"] + fn vfpclasspd_256(a: f64x4, imm8: i32) -> __mmask8; + #[link_name = "llvm.x86.avx512.fpclass.pd.512"] + fn vfpclasspd_512(a: f64x8, imm8: i32) -> __mmask8; + + #[link_name = "llvm.x86.avx512.fpclass.ps.128"] + fn vfpclassps_128(a: f32x4, imm8: i32) -> __mmask8; + #[link_name = "llvm.x86.avx512.fpclass.ps.256"] + fn vfpclassps_256(a: f32x8, imm8: i32) -> __mmask8; + #[link_name = "llvm.x86.avx512.fpclass.ps.512"] + fn vfpclassps_512(a: f32x16, imm8: i32) -> __mmask16; #[link_name = "llvm.x86.avx512.mask.fpclass.sd"] fn vfpclasssd(a: f64x2, imm8: i32, k: __mmask8) -> __mmask8; diff --git a/library/stdarch/crates/core_arch/src/x86/avx512f.rs b/library/stdarch/crates/core_arch/src/x86/avx512f.rs index 3730496e1ec34..76e7297bcda40 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512f.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512f.rs @@ -15529,17 +15529,17 @@ pub fn _mm512_maskz_cvt_roundps_ph(k: __mmask16, a: __m512) /// Convert packed single-precision (32-bit) floating-point elements in a to packed half-precision (16-bit) floating-point elements, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).\ /// Rounding is done according to the imm8\[2:0\] parameter, which can be one of: -/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions -/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions -/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions -/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions +/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest +/// * [`_MM_FROUND_TO_NEG_INF`] : round down +/// * [`_MM_FROUND_TO_POS_INF`] : round up +/// * [`_MM_FROUND_TO_ZERO`] : truncate /// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`] /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvt_roundps_ph&expand=1352) #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] -#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))] +#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_cvt_roundps_ph( src: __m128i, @@ -15547,7 +15547,7 @@ pub fn _mm256_mask_cvt_roundps_ph( a: __m256, ) -> __m128i { unsafe { - static_assert_uimm_bits!(IMM8, 8); + static_assert_round_mode!(IMM8); let a = a.as_f32x8(); let src = src.as_i16x8(); let r = vcvtps2ph256(a, IMM8, src, k); @@ -15557,21 +15557,21 @@ pub fn _mm256_mask_cvt_roundps_ph( /// Convert packed single-precision (32-bit) floating-point elements in a to packed half-precision (16-bit) floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).\ /// Rounding is done according to the imm8\[2:0\] parameter, which can be one of:\ -/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions -/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions -/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions -/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions +/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest +/// * [`_MM_FROUND_TO_NEG_INF`] : round down +/// * [`_MM_FROUND_TO_POS_INF`] : round up +/// * [`_MM_FROUND_TO_ZERO`] : truncate /// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`] /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvt_roundps_ph&expand=1353) #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] -#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))] +#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_cvt_roundps_ph(k: __mmask8, a: __m256) -> __m128i { unsafe { - static_assert_uimm_bits!(IMM8, 8); + static_assert_round_mode!(IMM8); let a = a.as_f32x8(); let r = vcvtps2ph256(a, IMM8, i16x8::ZERO, k); transmute(r) @@ -15580,21 +15580,21 @@ pub fn _mm256_maskz_cvt_roundps_ph(k: __mmask8, a: __m256) -> _ /// Convert packed single-precision (32-bit) floating-point elements in a to packed half-precision (16-bit) floating-point elements, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).\ /// Rounding is done according to the imm8\[2:0\] parameter, which can be one of:\ -/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions -/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions -/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions -/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions +/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest +/// * [`_MM_FROUND_TO_NEG_INF`] : round down +/// * [`_MM_FROUND_TO_POS_INF`] : round up +/// * [`_MM_FROUND_TO_ZERO`] : truncate /// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`] /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvt_roundps_ph&expand=1350) #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] -#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))] +#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_cvt_roundps_ph(src: __m128i, k: __mmask8, a: __m128) -> __m128i { unsafe { - static_assert_uimm_bits!(IMM8, 8); + static_assert_round_mode!(IMM8); let a = a.as_f32x4(); let src = src.as_i16x8(); let r = vcvtps2ph128(a, IMM8, src, k); @@ -15604,21 +15604,21 @@ pub fn _mm_mask_cvt_roundps_ph(src: __m128i, k: __mmask8, a: __ /// Convert packed single-precision (32-bit) floating-point elements in a to packed half-precision (16-bit) floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).\ /// Rounding is done according to the imm8\[2:0\] parameter, which can be one of:\ -/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions -/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions -/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions -/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions +/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest +/// * [`_MM_FROUND_TO_NEG_INF`] : round down +/// * [`_MM_FROUND_TO_POS_INF`] : round up +/// * [`_MM_FROUND_TO_ZERO`] : truncate /// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`] /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvt_roundps_ph&expand=1351) #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] -#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))] +#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_cvt_roundps_ph(k: __mmask8, a: __m128) -> __m128i { unsafe { - static_assert_uimm_bits!(IMM8, 8); + static_assert_round_mode!(IMM8); let a = a.as_f32x4(); let r = vcvtps2ph128(a, IMM8, i16x8::ZERO, k); transmute(r) @@ -15722,11 +15722,11 @@ pub fn _mm512_maskz_cvtps_ph(k: __mmask16, a: __m512) -> __ #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] -#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))] +#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_cvtps_ph(src: __m128i, k: __mmask8, a: __m256) -> __m128i { unsafe { - static_assert_uimm_bits!(IMM8, 8); + static_assert_round_mode!(IMM8); let a = a.as_f32x8(); let src = src.as_i16x8(); let r = vcvtps2ph256(a, IMM8, src, k); @@ -15746,11 +15746,11 @@ pub fn _mm256_mask_cvtps_ph(src: __m128i, k: __mmask8, a: __m25 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] -#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))] +#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_cvtps_ph(k: __mmask8, a: __m256) -> __m128i { unsafe { - static_assert_uimm_bits!(IMM8, 8); + static_assert_round_mode!(IMM8); let a = a.as_f32x8(); let r = vcvtps2ph256(a, IMM8, i16x8::ZERO, k); transmute(r) @@ -15769,11 +15769,11 @@ pub fn _mm256_maskz_cvtps_ph(k: __mmask8, a: __m256) -> __m128i #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] -#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))] +#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_cvtps_ph(src: __m128i, k: __mmask8, a: __m128) -> __m128i { unsafe { - static_assert_uimm_bits!(IMM8, 8); + static_assert_round_mode!(IMM8); let a = a.as_f32x4(); let src = src.as_i16x8(); let r = vcvtps2ph128(a, IMM8, src, k); @@ -15793,11 +15793,11 @@ pub fn _mm_mask_cvtps_ph(src: __m128i, k: __mmask8, a: __m128) #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] -#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))] +#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_cvtps_ph(k: __mmask8, a: __m128) -> __m128i { unsafe { - static_assert_uimm_bits!(IMM8, 8); + static_assert_round_mode!(IMM8); let a = a.as_f32x4(); let r = vcvtps2ph128(a, IMM8, i16x8::ZERO, k); transmute(r) @@ -16242,7 +16242,7 @@ pub fn _mm512_maskz_cvttps_epi32(k: __mmask16, a: __m512) -> __m512i { #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2dq))] pub fn _mm256_mask_cvttps_epi32(src: __m256i, k: __mmask8, a: __m256) -> __m256i { - unsafe { transmute(vcvttps2dq256(a.as_f32x8(), src.as_i32x8(), k)) } + unsafe { simd_select_bitmask(k, _mm256_cvttps_epi32(a).as_i32x8(), src.as_i32x8()).as_m256i() } } /// Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set). @@ -16253,7 +16253,7 @@ pub fn _mm256_mask_cvttps_epi32(src: __m256i, k: __mmask8, a: __m256) -> __m256i #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2dq))] pub fn _mm256_maskz_cvttps_epi32(k: __mmask8, a: __m256) -> __m256i { - unsafe { transmute(vcvttps2dq256(a.as_f32x8(), i32x8::ZERO, k)) } + _mm256_mask_cvttps_epi32(_mm256_setzero_si256(), k, a) } /// Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -16264,7 +16264,7 @@ pub fn _mm256_maskz_cvttps_epi32(k: __mmask8, a: __m256) -> __m256i { #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2dq))] pub fn _mm_mask_cvttps_epi32(src: __m128i, k: __mmask8, a: __m128) -> __m128i { - unsafe { transmute(vcvttps2dq128(a.as_f32x4(), src.as_i32x4(), k)) } + unsafe { simd_select_bitmask(k, _mm_cvttps_epi32(a).as_i32x4(), src.as_i32x4()).as_m128i() } } /// Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set). @@ -16275,7 +16275,7 @@ pub fn _mm_mask_cvttps_epi32(src: __m128i, k: __mmask8, a: __m128) -> __m128i { #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2dq))] pub fn _mm_maskz_cvttps_epi32(k: __mmask8, a: __m128) -> __m128i { - unsafe { transmute(vcvttps2dq128(a.as_f32x4(), i32x4::ZERO, k)) } + _mm_mask_cvttps_epi32(_mm_setzero_si128(), k, a) } /// Convert packed single-precision (32-bit) floating-point elements in a to packed unsigned 32-bit integers with truncation, and store the results in dst. @@ -16478,7 +16478,7 @@ pub fn _mm512_maskz_cvttpd_epi32(k: __mmask8, a: __m512d) -> __m256i { #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2dq))] pub fn _mm256_mask_cvttpd_epi32(src: __m128i, k: __mmask8, a: __m256d) -> __m128i { - unsafe { transmute(vcvttpd2dq256(a.as_f64x4(), src.as_i32x4(), k)) } + unsafe { simd_select_bitmask(k, _mm256_cvttpd_epi32(a).as_i32x4(), src.as_i32x4()).as_m128i() } } /// Convert packed double-precision (64-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set). @@ -16489,7 +16489,7 @@ pub fn _mm256_mask_cvttpd_epi32(src: __m128i, k: __mmask8, a: __m256d) -> __m128 #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2dq))] pub fn _mm256_maskz_cvttpd_epi32(k: __mmask8, a: __m256d) -> __m128i { - unsafe { transmute(vcvttpd2dq256(a.as_f64x4(), i32x4::ZERO, k)) } + _mm256_mask_cvttpd_epi32(_mm_setzero_si128(), k, a) } /// Convert packed double-precision (64-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -16807,12 +16807,12 @@ pub const fn _mm512_set_epi8( e0: i8, ) -> __m512i { unsafe { - let r = i8x64::new( + let r = i8x64::from_array([ e0, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13, e14, e15, e16, e17, e18, e19, e20, e21, e22, e23, e24, e25, e26, e27, e28, e29, e30, e31, e32, e33, e34, e35, e36, e37, e38, e39, e40, e41, e42, e43, e44, e45, e46, e47, e48, e49, e50, e51, e52, e53, e54, e55, e56, e57, e58, e59, e60, e61, e62, e63, - ); + ]); transmute(r) } } @@ -42633,7 +42633,7 @@ pub fn _mm_mask3_fnmsub_round_sd( } } -/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst. imm8 is used to set the required flags reporting. +/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst, and copy the upper 3 packed elements from b to the upper elements of dst. imm8 is used to set the required flags reporting. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fixupimm_ss&expand=2517) #[inline] @@ -42649,12 +42649,12 @@ pub fn _mm_fixupimm_ss(a: __m128, b: __m128, c: __m128i) -> __m let c = c.as_i32x4(); let r = vfixupimmss(a, b, c, IMM8, 0b11111111, _MM_FROUND_CUR_DIRECTION); let fixupimm: f32 = simd_extract!(r, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } -/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper 3 packed elements from a to the upper elements of dst. imm8 is used to set the required flags reporting. +/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper 3 packed elements from b to the upper elements of dst. imm8 is used to set the required flags reporting. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fixupimm_ss&expand=2518) #[inline] @@ -42675,12 +42675,12 @@ pub fn _mm_mask_fixupimm_ss( let c = c.as_i32x4(); let fixupimm = vfixupimmss(a, b, c, IMM8, k, _MM_FROUND_CUR_DIRECTION); let fixupimm: f32 = simd_extract!(fixupimm, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } -/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from a to the upper elements of dst. imm8 is used to set the required flags reporting. +/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from b to the upper elements of dst. imm8 is used to set the required flags reporting. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fixupimm_ss&expand=2519) #[inline] @@ -42701,12 +42701,12 @@ pub fn _mm_maskz_fixupimm_ss( let c = c.as_i32x4(); let fixupimm = vfixupimmssz(a, b, c, IMM8, k, _MM_FROUND_CUR_DIRECTION); let fixupimm: f32 = simd_extract!(fixupimm, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } -/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst. imm8 is used to set the required flags reporting. +/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst, and copy the upper element from b to the upper element of dst. imm8 is used to set the required flags reporting. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fixupimm_sd&expand=2514) #[inline] @@ -42722,12 +42722,12 @@ pub fn _mm_fixupimm_sd(a: __m128d, b: __m128d, c: __m128i) -> _ let c = c.as_i64x2(); let fixupimm = vfixupimmsd(a, b, c, IMM8, 0b11111111, _MM_FROUND_CUR_DIRECTION); let fixupimm: f64 = simd_extract!(fixupimm, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } -/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper element from a to the upper element of dst. imm8 is used to set the required flags reporting. +/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper element from b to the upper element of dst. imm8 is used to set the required flags reporting. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fixupimm_sd&expand=2515) #[inline] @@ -42748,12 +42748,12 @@ pub fn _mm_mask_fixupimm_sd( let c = c.as_i64x2(); let fixupimm = vfixupimmsd(a, b, c, IMM8, k, _MM_FROUND_CUR_DIRECTION); let fixupimm: f64 = simd_extract!(fixupimm, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } -/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper element from a to the upper element of dst. imm8 is used to set the required flags reporting. +/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper element from b to the upper element of dst. imm8 is used to set the required flags reporting. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fixupimm_sd&expand=2516) #[inline] @@ -42774,12 +42774,12 @@ pub fn _mm_maskz_fixupimm_sd( let c = c.as_i64x2(); let fixupimm = vfixupimmsdz(a, b, c, IMM8, k, _MM_FROUND_CUR_DIRECTION); let fixupimm: f64 = simd_extract!(fixupimm, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } -/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst. imm8 is used to set the required flags reporting.\ +/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst, and copy the upper 3 packed elements from b to the upper elements of dst. imm8 is used to set the required flags reporting.\ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fixupimm_round_ss&expand=2511) @@ -42801,12 +42801,12 @@ pub fn _mm_fixupimm_round_ss( let c = c.as_i32x4(); let r = vfixupimmss(a, b, c, IMM8, 0b11111111, SAE); let fixupimm: f32 = simd_extract!(r, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } -/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper 3 packed elements from a to the upper elements of dst. imm8 is used to set the required flags reporting.\ +/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper 3 packed elements from b to the upper elements of dst. imm8 is used to set the required flags reporting.\ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fixupimm_round_ss&expand=2512) @@ -42829,12 +42829,12 @@ pub fn _mm_mask_fixupimm_round_ss( let c = c.as_i32x4(); let r = vfixupimmss(a, b, c, IMM8, k, SAE); let fixupimm: f32 = simd_extract!(r, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } -/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from a to the upper elements of dst. imm8 is used to set the required flags reporting.\ +/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from b to the upper elements of dst. imm8 is used to set the required flags reporting.\ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fixupimm_round_ss&expand=2513) @@ -42857,12 +42857,12 @@ pub fn _mm_maskz_fixupimm_round_ss( let c = c.as_i32x4(); let r = vfixupimmssz(a, b, c, IMM8, k, SAE); let fixupimm: f32 = simd_extract!(r, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } -/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst. imm8 is used to set the required flags reporting.\ +/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst, and copy the upper element from b to the upper element of dst. imm8 is used to set the required flags reporting.\ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fixupimm_round_sd&expand=2508) @@ -42884,12 +42884,12 @@ pub fn _mm_fixupimm_round_sd( let c = c.as_i64x2(); let r = vfixupimmsd(a, b, c, IMM8, 0b11111111, SAE); let fixupimm: f64 = simd_extract!(r, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } -/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper element from a to the upper element of dst. imm8 is used to set the required flags reporting.\ +/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper element from b to the upper element of dst. imm8 is used to set the required flags reporting.\ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fixupimm_round_sd&expand=2509) @@ -42912,12 +42912,12 @@ pub fn _mm_mask_fixupimm_round_sd( let c = c.as_i64x2(); let r = vfixupimmsd(a, b, c, IMM8, k, SAE); let fixupimm: f64 = simd_extract!(r, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } -/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper element from a to the upper element of dst. imm8 is used to set the required flags reporting.\ +/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper element from b to the upper element of dst. imm8 is used to set the required flags reporting.\ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fixupimm_round_sd&expand=2510) @@ -42940,7 +42940,7 @@ pub fn _mm_maskz_fixupimm_round_sd( let c = c.as_i64x2(); let r = vfixupimmsdz(a, b, c, IMM8, k, SAE); let fixupimm: f64 = simd_extract!(r, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } @@ -44215,7 +44215,7 @@ pub const _MM_PERM_DDDC: _MM_PERM_ENUM = 0xFE; pub const _MM_PERM_DDDD: _MM_PERM_ENUM = 0xFF; #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.avx512.sqrt.ps.512"] fn vsqrtps(a: f32x16, rounding: i32) -> f32x16; #[link_name = "llvm.x86.avx512.sqrt.pd.512"] @@ -44430,10 +44430,6 @@ unsafe extern "C" { #[link_name = "llvm.x86.avx512.mask.cvttps2dq.512"] fn vcvttps2dq(a: f32x16, src: i32x16, mask: u16, rounding: i32) -> i32x16; - #[link_name = "llvm.x86.avx512.mask.cvttps2dq.256"] - fn vcvttps2dq256(a: f32x8, src: i32x8, mask: u8) -> i32x8; - #[link_name = "llvm.x86.avx512.mask.cvttps2dq.128"] - fn vcvttps2dq128(a: f32x4, src: i32x4, mask: u8) -> i32x4; #[link_name = "llvm.x86.avx512.mask.cvttps2udq.512"] fn vcvttps2udq(a: f32x16, src: u32x16, mask: u16, rounding: i32) -> u32x16; @@ -44444,8 +44440,6 @@ unsafe extern "C" { #[link_name = "llvm.x86.avx512.mask.cvttpd2dq.512"] fn vcvttpd2dq(a: f64x8, src: i32x8, mask: u8, rounding: i32) -> i32x8; - #[link_name = "llvm.x86.avx512.mask.cvttpd2dq.256"] - fn vcvttpd2dq256(a: f64x4, src: i32x4, mask: u8) -> i32x4; #[link_name = "llvm.x86.avx512.mask.cvttpd2dq.128"] fn vcvttpd2dq128(a: f64x2, src: i32x4, mask: u8) -> i32x4; @@ -50948,9 +50942,9 @@ mod tests { fn test_mm256_mask_cvt_roundps_ph() { let a = _mm256_set1_ps(1.); let src = _mm_set1_epi16(0); - let r = _mm256_mask_cvt_roundps_ph::<_MM_FROUND_NO_EXC>(src, 0, a); + let r = _mm256_mask_cvt_roundps_ph::<_MM_FROUND_CUR_DIRECTION>(src, 0, a); assert_eq_m128i(r, src); - let r = _mm256_mask_cvt_roundps_ph::<_MM_FROUND_NO_EXC>(src, 0b11111111, a); + let r = _mm256_mask_cvt_roundps_ph::<_MM_FROUND_CUR_DIRECTION>(src, 0b11111111, a); let e = _mm_setr_epi64x(4323521613979991040, 4323521613979991040); assert_eq_m128i(r, e); } @@ -50958,9 +50952,9 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] fn test_mm256_maskz_cvt_roundps_ph() { let a = _mm256_set1_ps(1.); - let r = _mm256_maskz_cvt_roundps_ph::<_MM_FROUND_NO_EXC>(0, a); + let r = _mm256_maskz_cvt_roundps_ph::<_MM_FROUND_CUR_DIRECTION>(0, a); assert_eq_m128i(r, _mm_setzero_si128()); - let r = _mm256_maskz_cvt_roundps_ph::<_MM_FROUND_NO_EXC>(0b11111111, a); + let r = _mm256_maskz_cvt_roundps_ph::<_MM_FROUND_CUR_DIRECTION>(0b11111111, a); let e = _mm_setr_epi64x(4323521613979991040, 4323521613979991040); assert_eq_m128i(r, e); } @@ -50969,9 +50963,9 @@ mod tests { fn test_mm_mask_cvt_roundps_ph() { let a = _mm_set1_ps(1.); let src = _mm_set1_epi16(0); - let r = _mm_mask_cvt_roundps_ph::<_MM_FROUND_NO_EXC>(src, 0, a); + let r = _mm_mask_cvt_roundps_ph::<_MM_FROUND_CUR_DIRECTION>(src, 0, a); assert_eq_m128i(r, src); - let r = _mm_mask_cvt_roundps_ph::<_MM_FROUND_NO_EXC>(src, 0b00001111, a); + let r = _mm_mask_cvt_roundps_ph::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a); let e = _mm_setr_epi64x(4323521613979991040, 0); assert_eq_m128i(r, e); } @@ -50979,9 +50973,9 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] fn test_mm_maskz_cvt_roundps_ph() { let a = _mm_set1_ps(1.); - let r = _mm_maskz_cvt_roundps_ph::<_MM_FROUND_NO_EXC>(0, a); + let r = _mm_maskz_cvt_roundps_ph::<_MM_FROUND_CUR_DIRECTION>(0, a); assert_eq_m128i(r, _mm_setzero_si128()); - let r = _mm_maskz_cvt_roundps_ph::<_MM_FROUND_NO_EXC>(0b00001111, a); + let r = _mm_maskz_cvt_roundps_ph::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a); let e = _mm_setr_epi64x(4323521613979991040, 0); assert_eq_m128i(r, e); } @@ -51024,9 +51018,9 @@ mod tests { fn test_mm256_mask_cvtps_ph() { let a = _mm256_set1_ps(1.); let src = _mm_set1_epi16(0); - let r = _mm256_mask_cvtps_ph::<_MM_FROUND_NO_EXC>(src, 0, a); + let r = _mm256_mask_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(src, 0, a); assert_eq_m128i(r, src); - let r = _mm256_mask_cvtps_ph::<_MM_FROUND_NO_EXC>(src, 0b11111111, a); + let r = _mm256_mask_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(src, 0b11111111, a); let e = _mm_setr_epi64x(4323521613979991040, 4323521613979991040); assert_eq_m128i(r, e); } @@ -51034,9 +51028,9 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] fn test_mm256_maskz_cvtps_ph() { let a = _mm256_set1_ps(1.); - let r = _mm256_maskz_cvtps_ph::<_MM_FROUND_NO_EXC>(0, a); + let r = _mm256_maskz_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(0, a); assert_eq_m128i(r, _mm_setzero_si128()); - let r = _mm256_maskz_cvtps_ph::<_MM_FROUND_NO_EXC>(0b11111111, a); + let r = _mm256_maskz_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(0b11111111, a); let e = _mm_setr_epi64x(4323521613979991040, 4323521613979991040); assert_eq_m128i(r, e); } @@ -51045,9 +51039,9 @@ mod tests { fn test_mm_mask_cvtps_ph() { let a = _mm_set1_ps(1.); let src = _mm_set1_epi16(0); - let r = _mm_mask_cvtps_ph::<_MM_FROUND_NO_EXC>(src, 0, a); + let r = _mm_mask_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(src, 0, a); assert_eq_m128i(r, src); - let r = _mm_mask_cvtps_ph::<_MM_FROUND_NO_EXC>(src, 0b00001111, a); + let r = _mm_mask_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a); let e = _mm_setr_epi64x(4323521613979991040, 0); assert_eq_m128i(r, e); } @@ -51055,9 +51049,9 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] fn test_mm_maskz_cvtps_ph() { let a = _mm_set1_ps(1.); - let r = _mm_maskz_cvtps_ph::<_MM_FROUND_NO_EXC>(0, a); + let r = _mm_maskz_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(0, a); assert_eq_m128i(r, _mm_setzero_si128()); - let r = _mm_maskz_cvtps_ph::<_MM_FROUND_NO_EXC>(0b00001111, a); + let r = _mm_maskz_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a); let e = _mm_setr_epi64x(4323521613979991040, 0); assert_eq_m128i(r, e); } @@ -58252,7 +58246,7 @@ mod tests { } #[simd_test(enable = "avx512f")] - #[cfg_attr(miri, ignore)] + #[cfg_attr(miri, ignore)] // Inline asm (for non-temporal store), which is not supported by Miri fn test_mm512_stream_ps() { #[repr(align(64))] struct Memory { @@ -58271,7 +58265,7 @@ mod tests { } #[simd_test(enable = "avx512f")] - #[cfg_attr(miri, ignore)] + #[cfg_attr(miri, ignore)] // Inline asm (for non-temporal store), which is not supported by Miri fn test_mm512_stream_pd() { #[repr(align(64))] struct Memory { @@ -58290,7 +58284,7 @@ mod tests { } #[simd_test(enable = "avx512f")] - #[cfg_attr(miri, ignore)] + #[cfg_attr(miri, ignore)] // Inline asm (for non-temporal store), which is not supported by Miri fn test_mm512_stream_si512() { #[repr(align(64))] struct Memory { @@ -61836,7 +61830,7 @@ mod tests { let b = _mm_set1_ps(f32::MAX); let c = _mm_set1_epi32(i32::MAX); let r = _mm_fixupimm_ss::<5>(a, b, c); - let e = _mm_set_ps(0., 0., 0., -0.0); + let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, -0.0); assert_eq_m128(r, e); } @@ -61846,7 +61840,7 @@ mod tests { let b = _mm_set1_ps(f32::MAX); let c = _mm_set1_epi32(i32::MAX); let r = _mm_mask_fixupimm_ss::<5>(a, 0b11111111, b, c); - let e = _mm_set_ps(0., 0., 0., -0.0); + let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, -0.0); assert_eq_m128(r, e); } @@ -61856,10 +61850,10 @@ mod tests { let b = _mm_set1_ps(f32::MAX); let c = _mm_set1_epi32(i32::MAX); let r = _mm_maskz_fixupimm_ss::<5>(0b00000000, a, b, c); - let e = _mm_set_ps(0., 0., 0., 0.0); + let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, 0.0); assert_eq_m128(r, e); let r = _mm_maskz_fixupimm_ss::<5>(0b11111111, a, b, c); - let e = _mm_set_ps(0., 0., 0., -0.0); + let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, -0.0); assert_eq_m128(r, e); } @@ -61869,7 +61863,7 @@ mod tests { let b = _mm_set1_pd(f64::MAX); let c = _mm_set1_epi64x(i32::MAX as i64); let r = _mm_fixupimm_sd::<5>(a, b, c); - let e = _mm_set_pd(0., -0.0); + let e = _mm_set_pd(f64::MAX, -0.0); assert_eq_m128d(r, e); } @@ -61879,7 +61873,7 @@ mod tests { let b = _mm_set1_pd(f64::MAX); let c = _mm_set1_epi64x(i32::MAX as i64); let r = _mm_mask_fixupimm_sd::<5>(a, 0b11111111, b, c); - let e = _mm_set_pd(0., -0.0); + let e = _mm_set_pd(f64::MAX, -0.0); assert_eq_m128d(r, e); } @@ -61889,10 +61883,10 @@ mod tests { let b = _mm_set1_pd(f64::MAX); let c = _mm_set1_epi64x(i32::MAX as i64); let r = _mm_maskz_fixupimm_sd::<5>(0b00000000, a, b, c); - let e = _mm_set_pd(0., 0.0); + let e = _mm_set_pd(f64::MAX, 0.0); assert_eq_m128d(r, e); let r = _mm_maskz_fixupimm_sd::<5>(0b11111111, a, b, c); - let e = _mm_set_pd(0., -0.0); + let e = _mm_set_pd(f64::MAX, -0.0); assert_eq_m128d(r, e); } @@ -61902,7 +61896,7 @@ mod tests { let b = _mm_set1_ps(f32::MAX); let c = _mm_set1_epi32(i32::MAX); let r = _mm_fixupimm_round_ss::<5, _MM_FROUND_CUR_DIRECTION>(a, b, c); - let e = _mm_set_ps(1., 0., 0., -0.0); + let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, -0.0); assert_eq_m128(r, e); } @@ -61912,7 +61906,7 @@ mod tests { let b = _mm_set1_ps(f32::MAX); let c = _mm_set1_epi32(i32::MAX); let r = _mm_mask_fixupimm_round_ss::<5, _MM_FROUND_CUR_DIRECTION>(a, 0b11111111, b, c); - let e = _mm_set_ps(0., 0., 0., -0.0); + let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, -0.0); assert_eq_m128(r, e); } @@ -61922,10 +61916,10 @@ mod tests { let b = _mm_set1_ps(f32::MAX); let c = _mm_set1_epi32(i32::MAX); let r = _mm_maskz_fixupimm_round_ss::<5, _MM_FROUND_CUR_DIRECTION>(0b00000000, a, b, c); - let e = _mm_set_ps(0., 0., 0., 0.0); + let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, 0.0); assert_eq_m128(r, e); let r = _mm_maskz_fixupimm_round_ss::<5, _MM_FROUND_CUR_DIRECTION>(0b11111111, a, b, c); - let e = _mm_set_ps(0., 0., 0., -0.0); + let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, -0.0); assert_eq_m128(r, e); } @@ -61935,7 +61929,7 @@ mod tests { let b = _mm_set1_pd(f64::MAX); let c = _mm_set1_epi64x(i32::MAX as i64); let r = _mm_fixupimm_round_sd::<5, _MM_FROUND_CUR_DIRECTION>(a, b, c); - let e = _mm_set_pd(0., -0.0); + let e = _mm_set_pd(f64::MAX, -0.0); assert_eq_m128d(r, e); } @@ -61945,7 +61939,7 @@ mod tests { let b = _mm_set1_pd(f64::MAX); let c = _mm_set1_epi64x(i32::MAX as i64); let r = _mm_mask_fixupimm_round_sd::<5, _MM_FROUND_CUR_DIRECTION>(a, 0b11111111, b, c); - let e = _mm_set_pd(0., -0.0); + let e = _mm_set_pd(f64::MAX, -0.0); assert_eq_m128d(r, e); } @@ -61955,10 +61949,10 @@ mod tests { let b = _mm_set1_pd(f64::MAX); let c = _mm_set1_epi64x(i32::MAX as i64); let r = _mm_maskz_fixupimm_round_sd::<5, _MM_FROUND_CUR_DIRECTION>(0b00000000, a, b, c); - let e = _mm_set_pd(0., 0.0); + let e = _mm_set_pd(f64::MAX, 0.0); assert_eq_m128d(r, e); let r = _mm_maskz_fixupimm_round_sd::<5, _MM_FROUND_CUR_DIRECTION>(0b11111111, a, b, c); - let e = _mm_set_pd(0., -0.0); + let e = _mm_set_pd(f64::MAX, -0.0); assert_eq_m128d(r, e); } diff --git a/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs b/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs index 27f06691c5500..6523e98d0ca8d 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs @@ -247,7 +247,7 @@ pub const fn _mm512_setr_ph( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setzero_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_setzero_ph() -> __m128h { unsafe { transmute(f16x8::ZERO) } @@ -258,7 +258,7 @@ pub const fn _mm_setzero_ph() -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setzero_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_setzero_ph() -> __m256h { f16x16::ZERO.as_m256h() @@ -269,7 +269,7 @@ pub const fn _mm256_setzero_ph() -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setzero_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_setzero_ph() -> __m512h { f16x32::ZERO.as_m512h() @@ -283,7 +283,7 @@ pub const fn _mm512_setzero_ph() -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_undefined_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_undefined_ph() -> __m128h { f16x8::ZERO.as_m128h() @@ -297,7 +297,7 @@ pub const fn _mm_undefined_ph() -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_undefined_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_undefined_ph() -> __m256h { f16x16::ZERO.as_m256h() @@ -311,7 +311,7 @@ pub const fn _mm256_undefined_ph() -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_undefined_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_undefined_ph() -> __m512h { f16x32::ZERO.as_m512h() @@ -323,7 +323,7 @@ pub const fn _mm512_undefined_ph() -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castpd_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_castpd_ph(a: __m128d) -> __m128h { unsafe { transmute(a) } @@ -335,7 +335,7 @@ pub const fn _mm_castpd_ph(a: __m128d) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castpd_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castpd_ph(a: __m256d) -> __m256h { unsafe { transmute(a) } @@ -347,7 +347,7 @@ pub const fn _mm256_castpd_ph(a: __m256d) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castpd_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castpd_ph(a: __m512d) -> __m512h { unsafe { transmute(a) } @@ -359,7 +359,7 @@ pub const fn _mm512_castpd_ph(a: __m512d) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castph_pd) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_castph_pd(a: __m128h) -> __m128d { unsafe { transmute(a) } @@ -371,7 +371,7 @@ pub const fn _mm_castph_pd(a: __m128h) -> __m128d { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph_pd) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castph_pd(a: __m256h) -> __m256d { unsafe { transmute(a) } @@ -383,7 +383,7 @@ pub const fn _mm256_castph_pd(a: __m256h) -> __m256d { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph_pd) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castph_pd(a: __m512h) -> __m512d { unsafe { transmute(a) } @@ -395,7 +395,7 @@ pub const fn _mm512_castph_pd(a: __m512h) -> __m512d { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castps_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_castps_ph(a: __m128) -> __m128h { unsafe { transmute(a) } @@ -407,7 +407,7 @@ pub const fn _mm_castps_ph(a: __m128) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castps_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castps_ph(a: __m256) -> __m256h { unsafe { transmute(a) } @@ -419,7 +419,7 @@ pub const fn _mm256_castps_ph(a: __m256) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castps_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castps_ph(a: __m512) -> __m512h { unsafe { transmute(a) } @@ -431,7 +431,7 @@ pub const fn _mm512_castps_ph(a: __m512) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castph_ps) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_castph_ps(a: __m128h) -> __m128 { unsafe { transmute(a) } @@ -443,7 +443,7 @@ pub const fn _mm_castph_ps(a: __m128h) -> __m128 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph_ps) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castph_ps(a: __m256h) -> __m256 { unsafe { transmute(a) } @@ -455,7 +455,7 @@ pub const fn _mm256_castph_ps(a: __m256h) -> __m256 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph_ps) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castph_ps(a: __m512h) -> __m512 { unsafe { transmute(a) } @@ -467,7 +467,7 @@ pub const fn _mm512_castph_ps(a: __m512h) -> __m512 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castsi128_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_castsi128_ph(a: __m128i) -> __m128h { unsafe { transmute(a) } @@ -479,7 +479,7 @@ pub const fn _mm_castsi128_ph(a: __m128i) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castsi256_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castsi256_ph(a: __m256i) -> __m256h { unsafe { transmute(a) } @@ -491,7 +491,7 @@ pub const fn _mm256_castsi256_ph(a: __m256i) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castsi512_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castsi512_ph(a: __m512i) -> __m512h { unsafe { transmute(a) } @@ -503,7 +503,7 @@ pub const fn _mm512_castsi512_ph(a: __m512i) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castph_si128) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_castph_si128(a: __m128h) -> __m128i { unsafe { transmute(a) } @@ -515,7 +515,7 @@ pub const fn _mm_castph_si128(a: __m128h) -> __m128i { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph_si256) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castph_si256(a: __m256h) -> __m256i { unsafe { transmute(a) } @@ -527,7 +527,7 @@ pub const fn _mm256_castph_si256(a: __m256h) -> __m256i { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph_si512) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castph_si512(a: __m512h) -> __m512i { unsafe { transmute(a) } @@ -539,7 +539,7 @@ pub const fn _mm512_castph_si512(a: __m512h) -> __m512i { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph256_ph128) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castph256_ph128(a: __m256h) -> __m128h { unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) } @@ -551,7 +551,7 @@ pub const fn _mm256_castph256_ph128(a: __m256h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph512_ph128) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castph512_ph128(a: __m512h) -> __m128h { unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) } @@ -563,7 +563,7 @@ pub const fn _mm512_castph512_ph128(a: __m512h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph512_ph256) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castph512_ph256(a: __m512h) -> __m256h { unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } @@ -576,7 +576,7 @@ pub const fn _mm512_castph512_ph256(a: __m512h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph128_ph256) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castph128_ph256(a: __m128h) -> __m256h { unsafe { @@ -595,7 +595,7 @@ pub const fn _mm256_castph128_ph256(a: __m128h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph128_ph512) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castph128_ph512(a: __m128h) -> __m512h { unsafe { @@ -617,7 +617,7 @@ pub const fn _mm512_castph128_ph512(a: __m128h) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph256_ph512) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castph256_ph512(a: __m256h) -> __m512h { unsafe { @@ -639,7 +639,7 @@ pub const fn _mm512_castph256_ph512(a: __m256h) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_zextph128_ph256) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_zextph128_ph256(a: __m128h) -> __m256h { unsafe { @@ -658,7 +658,7 @@ pub const fn _mm256_zextph128_ph256(a: __m128h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextph256_ph512) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_zextph256_ph512(a: __m256h) -> __m512h { unsafe { @@ -680,7 +680,7 @@ pub const fn _mm512_zextph256_ph512(a: __m256h) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextph128_ph512) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_zextph128_ph512(a: __m128h) -> __m512h { unsafe { @@ -695,34 +695,6 @@ pub const fn _mm512_zextph128_ph512(a: __m128h) -> __m512h { } } -macro_rules! cmp_asm { // FIXME: use LLVM intrinsics - ($mask_type: ty, $reg: ident, $a: expr, $b: expr) => {{ - let dst: $mask_type; - asm!( - "vcmpph {k}, {a}, {b}, {imm8}", - k = lateout(kreg) dst, - a = in($reg) $a, - b = in($reg) $b, - imm8 = const IMM5, - options(pure, nomem, nostack) - ); - dst - }}; - ($mask_type: ty, $mask: expr, $reg: ident, $a: expr, $b: expr) => {{ - let dst: $mask_type; - asm!( - "vcmpph {k} {{ {mask} }}, {a}, {b}, {imm8}", - k = lateout(kreg) dst, - mask = in(kreg) $mask, - a = in($reg) $a, - b = in($reg) $b, - imm8 = const IMM5, - options(pure, nomem, nostack) - ); - dst - }}; -} - /// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison /// operand specified by imm8, and store the results in mask vector k. /// @@ -730,12 +702,9 @@ macro_rules! cmp_asm { // FIXME: use LLVM intrinsics #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cmp_ph_mask(a: __m128h, b: __m128h) -> __mmask8 { - unsafe { - static_assert_uimm_bits!(IMM5, 5); - cmp_asm!(__mmask8, xmm_reg, a, b) - } + _mm_mask_cmp_ph_mask::(!0, a, b) } /// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison @@ -746,11 +715,11 @@ pub fn _mm_cmp_ph_mask(a: __m128h, b: __m128h) -> __mmask8 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cmp_ph_mask(k1: __mmask8, a: __m128h, b: __m128h) -> __mmask8 { unsafe { static_assert_uimm_bits!(IMM5, 5); - cmp_asm!(__mmask8, k1, xmm_reg, a, b) + vcmpph_128(a, b, IMM5, k1) } } @@ -761,12 +730,9 @@ pub fn _mm_mask_cmp_ph_mask(k1: __mmask8, a: __m128h, b: __m128 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cmp_ph_mask(a: __m256h, b: __m256h) -> __mmask16 { - unsafe { - static_assert_uimm_bits!(IMM5, 5); - cmp_asm!(__mmask16, ymm_reg, a, b) - } + _mm256_mask_cmp_ph_mask::(!0, a, b) } /// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison @@ -777,7 +743,7 @@ pub fn _mm256_cmp_ph_mask(a: __m256h, b: __m256h) -> __mmask16 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cmp_ph_mask( k1: __mmask16, a: __m256h, @@ -785,7 +751,7 @@ pub fn _mm256_mask_cmp_ph_mask( ) -> __mmask16 { unsafe { static_assert_uimm_bits!(IMM5, 5); - cmp_asm!(__mmask16, k1, ymm_reg, a, b) + vcmpph_256(a, b, IMM5, k1) } } @@ -796,12 +762,9 @@ pub fn _mm256_mask_cmp_ph_mask( #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cmp_ph_mask(a: __m512h, b: __m512h) -> __mmask32 { - unsafe { - static_assert_uimm_bits!(IMM5, 5); - cmp_asm!(__mmask32, zmm_reg, a, b) - } + _mm512_mask_cmp_ph_mask::(!0, a, b) } /// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison @@ -812,16 +775,13 @@ pub fn _mm512_cmp_ph_mask(a: __m512h, b: __m512h) -> __mmask32 #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cmp_ph_mask( k1: __mmask32, a: __m512h, b: __m512h, ) -> __mmask32 { - unsafe { - static_assert_uimm_bits!(IMM5, 5); - cmp_asm!(__mmask32, k1, zmm_reg, a, b) - } + _mm512_mask_cmp_round_ph_mask::(k1, a, b) } /// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison @@ -833,29 +793,12 @@ pub fn _mm512_mask_cmp_ph_mask( #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(2, 3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cmp_round_ph_mask( a: __m512h, b: __m512h, ) -> __mmask32 { - unsafe { - static_assert_uimm_bits!(IMM5, 5); - static_assert_sae!(SAE); - if SAE == _MM_FROUND_NO_EXC { - let dst: __mmask32; - asm!( - "vcmpph {k}, {a}, {b}, {{sae}}, {imm8}", - k = lateout(kreg) dst, - a = in(zmm_reg) a, - b = in(zmm_reg) b, - imm8 = const IMM5, - options(pure, nomem, nostack) - ); - dst - } else { - cmp_asm!(__mmask32, zmm_reg, a, b) - } - } + _mm512_mask_cmp_round_ph_mask::(!0, a, b) } /// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison @@ -868,7 +811,7 @@ pub fn _mm512_cmp_round_ph_mask( #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(3, 4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cmp_round_ph_mask( k1: __mmask32, a: __m512h, @@ -877,21 +820,7 @@ pub fn _mm512_mask_cmp_round_ph_mask( unsafe { static_assert_uimm_bits!(IMM5, 5); static_assert_sae!(SAE); - if SAE == _MM_FROUND_NO_EXC { - let dst: __mmask32; - asm!( - "vcmpph {k} {{{k1}}}, {a}, {b}, {{sae}}, {imm8}", - k = lateout(kreg) dst, - k1 = in(kreg) k1, - a = in(zmm_reg) a, - b = in(zmm_reg) b, - imm8 = const IMM5, - options(pure, nomem, nostack) - ); - dst - } else { - cmp_asm!(__mmask32, k1, zmm_reg, a, b) - } + vcmpph_512(a, b, IMM5, k1, SAE) } } @@ -903,7 +832,7 @@ pub fn _mm512_mask_cmp_round_ph_mask( #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(2, 3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cmp_round_sh_mask(a: __m128h, b: __m128h) -> __mmask8 { static_assert_uimm_bits!(IMM5, 5); static_assert_sae!(SAE); @@ -918,7 +847,7 @@ pub fn _mm_cmp_round_sh_mask(a: __m128h, b: __m #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(3, 4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cmp_round_sh_mask( k1: __mmask8, a: __m128h, @@ -938,7 +867,7 @@ pub fn _mm_mask_cmp_round_sh_mask( #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cmp_sh_mask(a: __m128h, b: __m128h) -> __mmask8 { static_assert_uimm_bits!(IMM5, 5); _mm_cmp_round_sh_mask::(a, b) @@ -951,7 +880,7 @@ pub fn _mm_cmp_sh_mask(a: __m128h, b: __m128h) -> __mmask8 { #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cmp_sh_mask(k1: __mmask8, a: __m128h, b: __m128h) -> __mmask8 { static_assert_uimm_bits!(IMM5, 5); _mm_mask_cmp_round_sh_mask::(k1, a, b) @@ -965,7 +894,7 @@ pub fn _mm_mask_cmp_sh_mask(k1: __mmask8, a: __m128h, b: __m128 #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(2, 3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comi_round_sh(a: __m128h, b: __m128h) -> i32 { unsafe { static_assert_uimm_bits!(IMM5, 5); @@ -981,7 +910,7 @@ pub fn _mm_comi_round_sh(a: __m128h, b: __m128h #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comi_sh(a: __m128h, b: __m128h) -> i32 { static_assert_uimm_bits!(IMM5, 5); _mm_comi_round_sh::(a, b) @@ -993,7 +922,7 @@ pub fn _mm_comi_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comieq_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comieq_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_EQ_OS>(a, b) } @@ -1004,7 +933,7 @@ pub fn _mm_comieq_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comige_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comige_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_GE_OS>(a, b) } @@ -1015,7 +944,7 @@ pub fn _mm_comige_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comigt_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comigt_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_GT_OS>(a, b) } @@ -1026,7 +955,7 @@ pub fn _mm_comigt_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comile_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comile_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_LE_OS>(a, b) } @@ -1037,7 +966,7 @@ pub fn _mm_comile_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comilt_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comilt_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_LT_OS>(a, b) } @@ -1048,7 +977,7 @@ pub fn _mm_comilt_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comineq_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comineq_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_NEQ_US>(a, b) } @@ -1059,7 +988,7 @@ pub fn _mm_comineq_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomieq_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_ucomieq_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_EQ_OQ>(a, b) } @@ -1070,7 +999,7 @@ pub fn _mm_ucomieq_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomige_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_ucomige_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_GE_OQ>(a, b) } @@ -1081,7 +1010,7 @@ pub fn _mm_ucomige_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomigt_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_ucomigt_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_GT_OQ>(a, b) } @@ -1092,7 +1021,7 @@ pub fn _mm_ucomigt_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomile_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_ucomile_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_LE_OQ>(a, b) } @@ -1103,7 +1032,7 @@ pub fn _mm_ucomile_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomilt_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_ucomilt_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_LT_OQ>(a, b) } @@ -1114,7 +1043,7 @@ pub fn _mm_ucomilt_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomineq_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_ucomineq_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_NEQ_UQ>(a, b) } @@ -1248,7 +1177,7 @@ pub const unsafe fn _mm512_loadu_ph(mem_addr: *const f16) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_move_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_move_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1267,7 +1196,7 @@ pub const fn _mm_mask_move_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_move_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_move_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1285,7 +1214,7 @@ pub const fn _mm_maskz_move_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_move_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_move_sh(a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1399,7 +1328,7 @@ pub const unsafe fn _mm512_storeu_ph(mem_addr: *mut f16, a: __m512h) { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_add_ph(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_add(a, b) } @@ -1412,7 +1341,7 @@ pub const fn _mm_add_ph(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_add_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1428,7 +1357,7 @@ pub const fn _mm_mask_add_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_add_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1443,7 +1372,7 @@ pub const fn _mm_maskz_add_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_add_ph(a: __m256h, b: __m256h) -> __m256h { unsafe { simd_add(a, b) } @@ -1456,7 +1385,7 @@ pub const fn _mm256_add_ph(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_add_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -1472,7 +1401,7 @@ pub const fn _mm256_mask_add_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_add_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -1487,7 +1416,7 @@ pub const fn _mm256_maskz_add_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_add_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { simd_add(a, b) } @@ -1500,7 +1429,7 @@ pub const fn _mm512_add_ph(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_add_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -1516,7 +1445,7 @@ pub const fn _mm512_mask_add_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_add_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -1539,7 +1468,7 @@ pub const fn _mm512_maskz_add_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_add_round_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -1562,7 +1491,7 @@ pub fn _mm512_add_round_ph(a: __m512h, b: __m512h) -> __m51 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_add_round_ph( src: __m512h, k: __mmask32, @@ -1590,7 +1519,7 @@ pub fn _mm512_mask_add_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_add_round_ph( k: __mmask32, a: __m512h, @@ -1618,7 +1547,7 @@ pub fn _mm512_maskz_add_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_add_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_add_round_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -1640,7 +1569,7 @@ pub fn _mm_add_round_sh(a: __m128h, b: __m128h) -> __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_add_round_sh( src: __m128h, k: __mmask8, @@ -1669,7 +1598,7 @@ pub fn _mm_mask_add_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_add_round_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_add_round_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -1682,7 +1611,7 @@ pub fn _mm_maskz_add_round_sh(k: __mmask8, a: __m128h, b: _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_add_sh(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) + _mm_cvtsh_h(b)) } @@ -1696,7 +1625,7 @@ pub const fn _mm_add_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_add_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1719,7 +1648,7 @@ pub const fn _mm_mask_add_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_add_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1739,7 +1668,7 @@ pub const fn _mm_maskz_add_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_sub_ph(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_sub(a, b) } @@ -1752,7 +1681,7 @@ pub const fn _mm_sub_ph(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_sub_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1768,7 +1697,7 @@ pub const fn _mm_mask_sub_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_sub_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1783,7 +1712,7 @@ pub const fn _mm_maskz_sub_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_sub_ph(a: __m256h, b: __m256h) -> __m256h { unsafe { simd_sub(a, b) } @@ -1796,7 +1725,7 @@ pub const fn _mm256_sub_ph(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_sub_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -1812,7 +1741,7 @@ pub const fn _mm256_mask_sub_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_sub_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -1827,7 +1756,7 @@ pub const fn _mm256_maskz_sub_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_sub_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { simd_sub(a, b) } @@ -1840,7 +1769,7 @@ pub const fn _mm512_sub_ph(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_sub_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -1856,7 +1785,7 @@ pub const fn _mm512_mask_sub_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_sub_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -1879,7 +1808,7 @@ pub const fn _mm512_maskz_sub_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_sub_round_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -1902,7 +1831,7 @@ pub fn _mm512_sub_round_ph(a: __m512h, b: __m512h) -> __m51 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_sub_round_ph( src: __m512h, k: __mmask32, @@ -1931,7 +1860,7 @@ pub fn _mm512_mask_sub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_sub_round_ph( k: __mmask32, a: __m512h, @@ -1959,7 +1888,7 @@ pub fn _mm512_maskz_sub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_sub_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_sub_round_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -1981,7 +1910,7 @@ pub fn _mm_sub_round_sh(a: __m128h, b: __m128h) -> __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_sub_round_sh( src: __m128h, k: __mmask8, @@ -2010,7 +1939,7 @@ pub fn _mm_mask_sub_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_sub_round_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_sub_round_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -2023,7 +1952,7 @@ pub fn _mm_maskz_sub_round_sh(k: __mmask8, a: __m128h, b: _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_sub_sh(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) - _mm_cvtsh_h(b)) } @@ -2037,7 +1966,7 @@ pub const fn _mm_sub_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_sub_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2060,7 +1989,7 @@ pub const fn _mm_mask_sub_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_sub_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2080,7 +2009,7 @@ pub const fn _mm_maskz_sub_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mul_ph(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_mul(a, b) } @@ -2093,7 +2022,7 @@ pub const fn _mm_mul_ph(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_mul_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2109,7 +2038,7 @@ pub const fn _mm_mask_mul_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_mul_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2124,7 +2053,7 @@ pub const fn _mm_maskz_mul_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mul_ph(a: __m256h, b: __m256h) -> __m256h { unsafe { simd_mul(a, b) } @@ -2137,7 +2066,7 @@ pub const fn _mm256_mul_ph(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_mul_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -2153,7 +2082,7 @@ pub const fn _mm256_mask_mul_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_mul_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -2168,7 +2097,7 @@ pub const fn _mm256_maskz_mul_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mul_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { simd_mul(a, b) } @@ -2181,7 +2110,7 @@ pub const fn _mm512_mul_ph(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_mul_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -2197,7 +2126,7 @@ pub const fn _mm512_mask_mul_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_mul_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -2220,7 +2149,7 @@ pub const fn _mm512_maskz_mul_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mul_round_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -2243,7 +2172,7 @@ pub fn _mm512_mul_round_ph(a: __m512h, b: __m512h) -> __m51 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_mul_round_ph( src: __m512h, k: __mmask32, @@ -2272,7 +2201,7 @@ pub fn _mm512_mask_mul_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_mul_round_ph( k: __mmask32, a: __m512h, @@ -2300,7 +2229,7 @@ pub fn _mm512_maskz_mul_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mul_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_mul_round_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -2322,7 +2251,7 @@ pub fn _mm_mul_round_sh(a: __m128h, b: __m128h) -> __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_mul_round_sh( src: __m128h, k: __mmask8, @@ -2351,7 +2280,7 @@ pub fn _mm_mask_mul_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_mul_round_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_mul_round_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -2364,7 +2293,7 @@ pub fn _mm_maskz_mul_round_sh(k: __mmask8, a: __m128h, b: _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mul_sh(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) * _mm_cvtsh_h(b)) } @@ -2378,7 +2307,7 @@ pub const fn _mm_mul_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_mul_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2401,7 +2330,7 @@ pub const fn _mm_mask_mul_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_mul_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2421,7 +2350,7 @@ pub const fn _mm_maskz_mul_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_div_ph(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_div(a, b) } @@ -2434,7 +2363,7 @@ pub const fn _mm_div_ph(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_div_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2450,7 +2379,7 @@ pub const fn _mm_mask_div_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_div_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2465,7 +2394,7 @@ pub const fn _mm_maskz_div_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_div_ph(a: __m256h, b: __m256h) -> __m256h { unsafe { simd_div(a, b) } @@ -2478,7 +2407,7 @@ pub const fn _mm256_div_ph(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_div_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -2494,7 +2423,7 @@ pub const fn _mm256_mask_div_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_div_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -2509,7 +2438,7 @@ pub const fn _mm256_maskz_div_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_div_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { simd_div(a, b) } @@ -2522,7 +2451,7 @@ pub const fn _mm512_div_ph(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_div_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -2538,7 +2467,7 @@ pub const fn _mm512_mask_div_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_div_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -2561,7 +2490,7 @@ pub const fn _mm512_maskz_div_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_div_round_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -2584,7 +2513,7 @@ pub fn _mm512_div_round_ph(a: __m512h, b: __m512h) -> __m51 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_div_round_ph( src: __m512h, k: __mmask32, @@ -2613,7 +2542,7 @@ pub fn _mm512_mask_div_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_div_round_ph( k: __mmask32, a: __m512h, @@ -2641,7 +2570,7 @@ pub fn _mm512_maskz_div_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_div_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_div_round_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -2663,7 +2592,7 @@ pub fn _mm_div_round_sh(a: __m128h, b: __m128h) -> __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_div_round_sh( src: __m128h, k: __mmask8, @@ -2692,7 +2621,7 @@ pub fn _mm_mask_div_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_div_round_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_div_round_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -2705,7 +2634,7 @@ pub fn _mm_maskz_div_round_sh(k: __mmask8, a: __m128h, b: _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_div_sh(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) / _mm_cvtsh_h(b)) } @@ -2719,7 +2648,7 @@ pub const fn _mm_div_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_div_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2742,7 +2671,7 @@ pub const fn _mm_mask_div_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_div_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2764,7 +2693,7 @@ pub const fn _mm_maskz_div_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mul_pch(a: __m128h, b: __m128h) -> __m128h { _mm_mask_mul_pch(_mm_undefined_ph(), 0xff, a, b) } @@ -2777,7 +2706,7 @@ pub fn _mm_mul_pch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_mul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { transmute(vfmulcph_128(transmute(a), transmute(b), transmute(src), k)) } } @@ -2790,7 +2719,7 @@ pub fn _mm_mask_mul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_mul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_mul_pch(_mm_setzero_ph(), k, a, b) } @@ -2803,7 +2732,7 @@ pub fn _mm_maskz_mul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mul_pch(a: __m256h, b: __m256h) -> __m256h { _mm256_mask_mul_pch(_mm256_undefined_ph(), 0xff, a, b) } @@ -2816,7 +2745,7 @@ pub fn _mm256_mul_pch(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_mul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h { unsafe { transmute(vfmulcph_256(transmute(a), transmute(b), transmute(src), k)) } } @@ -2829,7 +2758,7 @@ pub fn _mm256_mask_mul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_mul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { _mm256_mask_mul_pch(_mm256_setzero_ph(), k, a, b) } @@ -2842,7 +2771,7 @@ pub fn _mm256_maskz_mul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mul_pch(a: __m512h, b: __m512h) -> __m512h { _mm512_mask_mul_pch(_mm512_undefined_ph(), 0xffff, a, b) } @@ -2855,7 +2784,7 @@ pub fn _mm512_mul_pch(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_mul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_mul_round_pch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -2868,7 +2797,7 @@ pub fn _mm512_mask_mul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) - #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_mul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_mul_pch(_mm512_setzero_ph(), k, a, b) } @@ -2890,7 +2819,7 @@ pub fn _mm512_maskz_mul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mul_round_pch(a: __m512h, b: __m512h) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mask_mul_round_pch::(_mm512_undefined_ph(), 0xffff, a, b) @@ -2913,7 +2842,7 @@ pub fn _mm512_mul_round_pch(a: __m512h, b: __m512h) -> __m5 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_mul_round_pch( src: __m512h, k: __mmask16, @@ -2949,7 +2878,7 @@ pub fn _mm512_mask_mul_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_mul_round_pch( k: __mmask16, a: __m512h, @@ -2968,7 +2897,7 @@ pub fn _mm512_maskz_mul_round_pch( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mul_sch(a: __m128h, b: __m128h) -> __m128h { _mm_mask_mul_sch(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -2982,7 +2911,7 @@ pub fn _mm_mul_sch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_mul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_mul_round_sch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -2996,7 +2925,7 @@ pub fn _mm_mask_mul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_mul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_mul_sch(f16x8::ZERO.as_m128h(), k, a, b) } @@ -3019,7 +2948,7 @@ pub fn _mm_maskz_mul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mul_round_sch(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_mul_round_sch::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -3043,7 +2972,7 @@ pub fn _mm_mul_round_sch(a: __m128h, b: __m128h) -> __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_mul_round_sch( src: __m128h, k: __mmask8, @@ -3080,7 +3009,7 @@ pub fn _mm_mask_mul_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_mul_round_sch( k: __mmask8, a: __m128h, @@ -3098,7 +3027,7 @@ pub fn _mm_maskz_mul_round_sch( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmul_pch(a: __m128h, b: __m128h) -> __m128h { _mm_mul_pch(a, b) } @@ -3111,7 +3040,7 @@ pub fn _mm_fmul_pch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_mul_pch(src, k, a, b) } @@ -3124,7 +3053,7 @@ pub fn _mm_mask_fmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_maskz_mul_pch(k, a, b) } @@ -3137,7 +3066,7 @@ pub fn _mm_maskz_fmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_fmul_pch(a: __m256h, b: __m256h) -> __m256h { _mm256_mul_pch(a, b) } @@ -3150,7 +3079,7 @@ pub fn _mm256_fmul_pch(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_fmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h { _mm256_mask_mul_pch(src, k, a, b) } @@ -3163,7 +3092,7 @@ pub fn _mm256_mask_fmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) - #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_fmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { _mm256_maskz_mul_pch(k, a, b) } @@ -3175,7 +3104,7 @@ pub fn _mm256_maskz_fmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmul_pch(a: __m512h, b: __m512h) -> __m512h { _mm512_mul_pch(a, b) } @@ -3188,7 +3117,7 @@ pub fn _mm512_fmul_pch(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_mul_pch(src, k, a, b) } @@ -3201,7 +3130,7 @@ pub fn _mm512_mask_fmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_maskz_mul_pch(k, a, b) } @@ -3221,7 +3150,7 @@ pub fn _mm512_maskz_fmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmul_round_pch(a: __m512h, b: __m512h) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mul_round_pch::(a, b) @@ -3243,7 +3172,7 @@ pub fn _mm512_fmul_round_pch(a: __m512h, b: __m512h) -> __m #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmul_round_pch( src: __m512h, k: __mmask16, @@ -3270,7 +3199,7 @@ pub fn _mm512_mask_fmul_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmul_round_pch( k: __mmask16, a: __m512h, @@ -3288,7 +3217,7 @@ pub fn _mm512_maskz_fmul_round_pch( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmul_sch(a: __m128h, b: __m128h) -> __m128h { _mm_mul_sch(a, b) } @@ -3301,7 +3230,7 @@ pub fn _mm_fmul_sch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_mul_sch(src, k, a, b) } @@ -3314,7 +3243,7 @@ pub fn _mm_mask_fmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_maskz_mul_sch(k, a, b) } @@ -3335,7 +3264,7 @@ pub fn _mm_maskz_fmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmul_round_sch(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mul_round_sch::(a, b) @@ -3358,7 +3287,7 @@ pub fn _mm_fmul_round_sch(a: __m128h, b: __m128h) -> __m128 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmul_round_sch( src: __m128h, k: __mmask8, @@ -3386,7 +3315,7 @@ pub fn _mm_mask_fmul_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmul_round_sch( k: __mmask8, a: __m128h, @@ -3405,7 +3334,7 @@ pub fn _mm_maskz_fmul_round_sch( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cmul_pch(a: __m128h, b: __m128h) -> __m128h { _mm_mask_cmul_pch(_mm_undefined_ph(), 0xff, a, b) } @@ -3419,7 +3348,7 @@ pub fn _mm_cmul_pch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { transmute(vfcmulcph_128(transmute(a), transmute(b), transmute(src), k)) } } @@ -3433,7 +3362,7 @@ pub fn _mm_mask_cmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_cmul_pch(_mm_setzero_ph(), k, a, b) } @@ -3447,7 +3376,7 @@ pub fn _mm_maskz_cmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cmul_pch(a: __m256h, b: __m256h) -> __m256h { _mm256_mask_cmul_pch(_mm256_undefined_ph(), 0xff, a, b) } @@ -3461,7 +3390,7 @@ pub fn _mm256_cmul_pch(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h { unsafe { transmute(vfcmulcph_256(transmute(a), transmute(b), transmute(src), k)) } } @@ -3475,7 +3404,7 @@ pub fn _mm256_mask_cmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) - #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { _mm256_mask_cmul_pch(_mm256_setzero_ph(), k, a, b) } @@ -3489,7 +3418,7 @@ pub fn _mm256_maskz_cmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cmul_pch(a: __m512h, b: __m512h) -> __m512h { _mm512_mask_cmul_pch(_mm512_undefined_ph(), 0xffff, a, b) } @@ -3503,7 +3432,7 @@ pub fn _mm512_cmul_pch(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_cmul_round_pch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -3517,7 +3446,7 @@ pub fn _mm512_mask_cmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_cmul_pch(_mm512_setzero_ph(), k, a, b) } @@ -3540,7 +3469,7 @@ pub fn _mm512_maskz_cmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cmul_round_pch(a: __m512h, b: __m512h) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mask_cmul_round_pch::(_mm512_undefined_ph(), 0xffff, a, b) @@ -3564,7 +3493,7 @@ pub fn _mm512_cmul_round_pch(a: __m512h, b: __m512h) -> __m #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cmul_round_pch( src: __m512h, k: __mmask16, @@ -3601,7 +3530,7 @@ pub fn _mm512_mask_cmul_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cmul_round_pch( k: __mmask16, a: __m512h, @@ -3619,7 +3548,7 @@ pub fn _mm512_maskz_cmul_round_pch( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cmul_sch(a: __m128h, b: __m128h) -> __m128h { _mm_mask_cmul_sch(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -3633,7 +3562,7 @@ pub fn _mm_cmul_sch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_cmul_round_sch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -3647,7 +3576,7 @@ pub fn _mm_mask_cmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_cmul_sch(f16x8::ZERO.as_m128h(), k, a, b) } @@ -3669,7 +3598,7 @@ pub fn _mm_maskz_cmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cmul_round_sch(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_cmul_round_sch::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -3693,7 +3622,7 @@ pub fn _mm_cmul_round_sch(a: __m128h, b: __m128h) -> __m128 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cmul_round_sch( src: __m128h, k: __mmask8, @@ -3730,7 +3659,7 @@ pub fn _mm_mask_cmul_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cmul_round_sch( k: __mmask8, a: __m128h, @@ -3749,7 +3678,7 @@ pub fn _mm_maskz_cmul_round_sch( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fcmul_pch(a: __m128h, b: __m128h) -> __m128h { _mm_cmul_pch(a, b) } @@ -3763,7 +3692,7 @@ pub fn _mm_fcmul_pch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fcmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_cmul_pch(src, k, a, b) } @@ -3777,7 +3706,7 @@ pub fn _mm_mask_fcmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fcmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_maskz_cmul_pch(k, a, b) } @@ -3791,7 +3720,7 @@ pub fn _mm_maskz_fcmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_fcmul_pch(a: __m256h, b: __m256h) -> __m256h { _mm256_cmul_pch(a, b) } @@ -3805,7 +3734,7 @@ pub fn _mm256_fcmul_pch(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_fcmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h { _mm256_mask_cmul_pch(src, k, a, b) } @@ -3819,7 +3748,7 @@ pub fn _mm256_mask_fcmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_fcmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { _mm256_maskz_cmul_pch(k, a, b) } @@ -3833,7 +3762,7 @@ pub fn _mm256_maskz_fcmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fcmul_pch(a: __m512h, b: __m512h) -> __m512h { _mm512_cmul_pch(a, b) } @@ -3847,7 +3776,7 @@ pub fn _mm512_fcmul_pch(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fcmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_cmul_pch(src, k, a, b) } @@ -3861,7 +3790,7 @@ pub fn _mm512_mask_fcmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fcmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_maskz_cmul_pch(k, a, b) } @@ -3883,7 +3812,7 @@ pub fn _mm512_maskz_fcmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fcmul_round_pch(a: __m512h, b: __m512h) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_cmul_round_pch::(a, b) @@ -3907,7 +3836,7 @@ pub fn _mm512_fcmul_round_pch(a: __m512h, b: __m512h) -> __ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fcmul_round_pch( src: __m512h, k: __mmask16, @@ -3936,7 +3865,7 @@ pub fn _mm512_mask_fcmul_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fcmul_round_pch( k: __mmask16, a: __m512h, @@ -3955,7 +3884,7 @@ pub fn _mm512_maskz_fcmul_round_pch( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fcmul_sch(a: __m128h, b: __m128h) -> __m128h { _mm_cmul_sch(a, b) } @@ -3969,7 +3898,7 @@ pub fn _mm_fcmul_sch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fcmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_cmul_sch(src, k, a, b) } @@ -3983,7 +3912,7 @@ pub fn _mm_mask_fcmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fcmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_maskz_cmul_sch(k, a, b) } @@ -4005,7 +3934,7 @@ pub fn _mm_maskz_fcmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fcmul_round_sch(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_cmul_round_sch::(a, b) @@ -4029,7 +3958,7 @@ pub fn _mm_fcmul_round_sch(a: __m128h, b: __m128h) -> __m12 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fcmul_round_sch( src: __m128h, k: __mmask8, @@ -4058,7 +3987,7 @@ pub fn _mm_mask_fcmul_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fcmul_round_sch( k: __mmask8, a: __m128h, @@ -4074,7 +4003,7 @@ pub fn _mm_maskz_fcmul_round_sch( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_abs_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_abs_ph(v2: __m128h) -> __m128h { unsafe { transmute(_mm_and_si128(transmute(v2), _mm_set1_epi16(i16::MAX))) } @@ -4086,7 +4015,7 @@ pub const fn _mm_abs_ph(v2: __m128h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_abs_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_abs_ph(v2: __m256h) -> __m256h { unsafe { transmute(_mm256_and_si256(transmute(v2), _mm256_set1_epi16(i16::MAX))) } @@ -4098,7 +4027,7 @@ pub const fn _mm256_abs_ph(v2: __m256h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_abs_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_abs_ph(v2: __m512h) -> __m512h { unsafe { transmute(_mm512_and_si512(transmute(v2), _mm512_set1_epi16(i16::MAX))) } @@ -4112,7 +4041,7 @@ pub const fn _mm512_abs_ph(v2: __m512h) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_conj_pch) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_conj_pch(a: __m128h) -> __m128h { unsafe { transmute(_mm_xor_si128(transmute(a), _mm_set1_epi32(i32::MIN))) } @@ -4126,7 +4055,7 @@ pub const fn _mm_conj_pch(a: __m128h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_conj_pch) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_conj_pch(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { unsafe { @@ -4143,7 +4072,7 @@ pub const fn _mm_mask_conj_pch(src: __m128h, k: __mmask8, a: __m128h) -> __m128h /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_conj_pch) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_conj_pch(k: __mmask8, a: __m128h) -> __m128h { _mm_mask_conj_pch(_mm_setzero_ph(), k, a) @@ -4156,7 +4085,7 @@ pub const fn _mm_maskz_conj_pch(k: __mmask8, a: __m128h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_conj_pch) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_conj_pch(a: __m256h) -> __m256h { unsafe { transmute(_mm256_xor_si256(transmute(a), _mm256_set1_epi32(i32::MIN))) } @@ -4170,7 +4099,7 @@ pub const fn _mm256_conj_pch(a: __m256h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_conj_pch) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_conj_pch(src: __m256h, k: __mmask8, a: __m256h) -> __m256h { unsafe { @@ -4187,7 +4116,7 @@ pub const fn _mm256_mask_conj_pch(src: __m256h, k: __mmask8, a: __m256h) -> __m2 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_conj_pch) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_conj_pch(k: __mmask8, a: __m256h) -> __m256h { _mm256_mask_conj_pch(_mm256_setzero_ph(), k, a) @@ -4200,7 +4129,7 @@ pub const fn _mm256_maskz_conj_pch(k: __mmask8, a: __m256h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_conj_pch) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_conj_pch(a: __m512h) -> __m512h { unsafe { transmute(_mm512_xor_si512(transmute(a), _mm512_set1_epi32(i32::MIN))) } @@ -4214,7 +4143,7 @@ pub const fn _mm512_conj_pch(a: __m512h) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_conj_pch) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_conj_pch(src: __m512h, k: __mmask16, a: __m512h) -> __m512h { unsafe { @@ -4231,7 +4160,7 @@ pub const fn _mm512_mask_conj_pch(src: __m512h, k: __mmask16, a: __m512h) -> __m /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_conj_pch) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_conj_pch(k: __mmask16, a: __m512h) -> __m512h { _mm512_mask_conj_pch(_mm512_setzero_ph(), k, a) @@ -4245,7 +4174,7 @@ pub const fn _mm512_maskz_conj_pch(k: __mmask16, a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmadd_pch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { _mm_mask3_fmadd_pch(a, b, c, 0xff) } @@ -4259,7 +4188,7 @@ pub fn _mm_fmadd_pch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmadd_pch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { let r: __m128 = transmute(_mm_mask3_fmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does @@ -4276,7 +4205,7 @@ pub fn _mm_mask_fmadd_pch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fmadd_pch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { transmute(vfmaddcph_mask3_128( @@ -4297,7 +4226,7 @@ pub fn _mm_mask3_fmadd_pch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> _ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmadd_pch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { transmute(vfmaddcph_maskz_128( @@ -4317,7 +4246,7 @@ pub fn _mm_maskz_fmadd_pch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_fmadd_pch(a: __m256h, b: __m256h, c: __m256h) -> __m256h { _mm256_mask3_fmadd_pch(a, b, c, 0xff) } @@ -4331,7 +4260,7 @@ pub fn _mm256_fmadd_pch(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_fmadd_pch(a: __m256h, k: __mmask8, b: __m256h, c: __m256h) -> __m256h { unsafe { let r: __m256 = transmute(_mm256_mask3_fmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does @@ -4348,7 +4277,7 @@ pub fn _mm256_mask_fmadd_pch(a: __m256h, k: __mmask8, b: __m256h, c: __m256h) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask3_fmadd_pch(a: __m256h, b: __m256h, c: __m256h, k: __mmask8) -> __m256h { unsafe { transmute(vfmaddcph_mask3_256( @@ -4369,7 +4298,7 @@ pub fn _mm256_mask3_fmadd_pch(a: __m256h, b: __m256h, c: __m256h, k: __mmask8) - #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_fmadd_pch(k: __mmask8, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { transmute(vfmaddcph_maskz_256( @@ -4389,7 +4318,7 @@ pub fn _mm256_maskz_fmadd_pch(k: __mmask8, a: __m256h, b: __m256h, c: __m256h) - #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmadd_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h { _mm512_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c) } @@ -4403,7 +4332,7 @@ pub fn _mm512_fmadd_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmadd_pch(a: __m512h, k: __mmask16, b: __m512h, c: __m512h) -> __m512h { _mm512_mask_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c) } @@ -4417,7 +4346,7 @@ pub fn _mm512_mask_fmadd_pch(a: __m512h, k: __mmask16, b: __m512h, c: __m512h) - #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fmadd_pch(a: __m512h, b: __m512h, c: __m512h, k: __mmask16) -> __m512h { _mm512_mask3_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k) } @@ -4431,7 +4360,7 @@ pub fn _mm512_mask3_fmadd_pch(a: __m512h, b: __m512h, c: __m512h, k: __mmask16) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmadd_pch(k: __mmask16, a: __m512h, b: __m512h, c: __m512h) -> __m512h { _mm512_maskz_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c) } @@ -4453,7 +4382,7 @@ pub fn _mm512_maskz_fmadd_pch(k: __mmask16, a: __m512h, b: __m512h, c: __m512h) #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmadd_round_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mask3_fmadd_round_pch::(a, b, c, 0xffff) @@ -4477,7 +4406,7 @@ pub fn _mm512_fmadd_round_pch(a: __m512h, b: __m512h, c: __ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmadd_round_pch( a: __m512h, k: __mmask16, @@ -4509,7 +4438,7 @@ pub fn _mm512_mask_fmadd_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fmadd_round_pch( a: __m512h, b: __m512h, @@ -4546,7 +4475,7 @@ pub fn _mm512_mask3_fmadd_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmadd_round_pch( k: __mmask16, a: __m512h, @@ -4574,7 +4503,7 @@ pub fn _mm512_maskz_fmadd_round_pch( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmadd_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { _mm_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c) } @@ -4589,7 +4518,7 @@ pub fn _mm_fmadd_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmadd_sch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { _mm_mask_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c) } @@ -4604,7 +4533,7 @@ pub fn _mm_mask_fmadd_sch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fmadd_sch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { _mm_mask3_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k) } @@ -4619,7 +4548,7 @@ pub fn _mm_mask3_fmadd_sch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmadd_sch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { _mm_maskz_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c) } @@ -4641,7 +4570,7 @@ pub fn _mm_maskz_fmadd_sch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> _ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmadd_round_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -4674,7 +4603,7 @@ pub fn _mm_fmadd_round_sch(a: __m128h, b: __m128h, c: __m12 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmadd_round_sch( a: __m128h, k: __mmask8, @@ -4708,7 +4637,7 @@ pub fn _mm_mask_fmadd_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fmadd_round_sch( a: __m128h, b: __m128h, @@ -4742,7 +4671,7 @@ pub fn _mm_mask3_fmadd_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmadd_round_sch( k: __mmask8, a: __m128h, @@ -4770,7 +4699,7 @@ pub fn _mm_maskz_fmadd_round_sch( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fcmadd_pch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { _mm_mask3_fcmadd_pch(a, b, c, 0xff) } @@ -4785,7 +4714,7 @@ pub fn _mm_fcmadd_pch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fcmadd_pch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { let r: __m128 = transmute(_mm_mask3_fcmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does @@ -4803,7 +4732,7 @@ pub fn _mm_mask_fcmadd_pch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fcmadd_pch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { transmute(vfcmaddcph_mask3_128( @@ -4825,7 +4754,7 @@ pub fn _mm_mask3_fcmadd_pch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fcmadd_pch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { transmute(vfcmaddcph_maskz_128( @@ -4846,7 +4775,7 @@ pub fn _mm_maskz_fcmadd_pch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_fcmadd_pch(a: __m256h, b: __m256h, c: __m256h) -> __m256h { _mm256_mask3_fcmadd_pch(a, b, c, 0xff) } @@ -4861,7 +4790,7 @@ pub fn _mm256_fcmadd_pch(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_fcmadd_pch(a: __m256h, k: __mmask8, b: __m256h, c: __m256h) -> __m256h { unsafe { let r: __m256 = transmute(_mm256_mask3_fcmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does @@ -4879,7 +4808,7 @@ pub fn _mm256_mask_fcmadd_pch(a: __m256h, k: __mmask8, b: __m256h, c: __m256h) - #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask3_fcmadd_pch(a: __m256h, b: __m256h, c: __m256h, k: __mmask8) -> __m256h { unsafe { transmute(vfcmaddcph_mask3_256( @@ -4901,7 +4830,7 @@ pub fn _mm256_mask3_fcmadd_pch(a: __m256h, b: __m256h, c: __m256h, k: __mmask8) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_fcmadd_pch(k: __mmask8, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { transmute(vfcmaddcph_maskz_256( @@ -4922,7 +4851,7 @@ pub fn _mm256_maskz_fcmadd_pch(k: __mmask8, a: __m256h, b: __m256h, c: __m256h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fcmadd_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h { _mm512_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c) } @@ -4937,7 +4866,7 @@ pub fn _mm512_fcmadd_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fcmadd_pch(a: __m512h, k: __mmask16, b: __m512h, c: __m512h) -> __m512h { _mm512_mask_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c) } @@ -4952,7 +4881,7 @@ pub fn _mm512_mask_fcmadd_pch(a: __m512h, k: __mmask16, b: __m512h, c: __m512h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fcmadd_pch(a: __m512h, b: __m512h, c: __m512h, k: __mmask16) -> __m512h { _mm512_mask3_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k) } @@ -4967,7 +4896,7 @@ pub fn _mm512_mask3_fcmadd_pch(a: __m512h, b: __m512h, c: __m512h, k: __mmask16) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fcmadd_pch(k: __mmask16, a: __m512h, b: __m512h, c: __m512h) -> __m512h { _mm512_maskz_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c) } @@ -4990,7 +4919,7 @@ pub fn _mm512_maskz_fcmadd_pch(k: __mmask16, a: __m512h, b: __m512h, c: __m512h) #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fcmadd_round_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mask3_fcmadd_round_pch::(a, b, c, 0xffff) @@ -5015,7 +4944,7 @@ pub fn _mm512_fcmadd_round_pch(a: __m512h, b: __m512h, c: _ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fcmadd_round_pch( a: __m512h, k: __mmask16, @@ -5048,7 +4977,7 @@ pub fn _mm512_mask_fcmadd_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fcmadd_round_pch( a: __m512h, b: __m512h, @@ -5086,7 +5015,7 @@ pub fn _mm512_mask3_fcmadd_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fcmadd_round_pch( k: __mmask16, a: __m512h, @@ -5115,7 +5044,7 @@ pub fn _mm512_maskz_fcmadd_round_pch( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fcmadd_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { _mm_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c) } @@ -5131,7 +5060,7 @@ pub fn _mm_fcmadd_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fcmadd_sch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { _mm_mask_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c) } @@ -5147,7 +5076,7 @@ pub fn _mm_mask_fcmadd_sch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fcmadd_sch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { _mm_mask3_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k) } @@ -5163,7 +5092,7 @@ pub fn _mm_mask3_fcmadd_sch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fcmadd_sch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { _mm_maskz_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c) } @@ -5187,7 +5116,7 @@ pub fn _mm_maskz_fcmadd_sch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fcmadd_round_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -5221,7 +5150,7 @@ pub fn _mm_fcmadd_round_sch(a: __m128h, b: __m128h, c: __m1 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fcmadd_round_sch( a: __m128h, k: __mmask8, @@ -5256,7 +5185,7 @@ pub fn _mm_mask_fcmadd_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fcmadd_round_sch( a: __m128h, b: __m128h, @@ -5291,7 +5220,7 @@ pub fn _mm_mask3_fcmadd_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fcmadd_round_sch( k: __mmask8, a: __m128h, @@ -5317,7 +5246,7 @@ pub fn _mm_maskz_fcmadd_round_sch( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_fma(a, b, c) } @@ -5331,7 +5260,7 @@ pub const fn _mm_fmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmadd_ph(a, b, c), a) } @@ -5345,7 +5274,7 @@ pub const fn _mm_mask_fmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmadd_ph(a, b, c), c) } @@ -5359,7 +5288,7 @@ pub const fn _mm_mask3_fmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmadd_ph(a, b, c), _mm_setzero_ph()) } @@ -5372,7 +5301,7 @@ pub const fn _mm_maskz_fmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_fmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_fma(a, b, c) } @@ -5386,7 +5315,7 @@ pub const fn _mm256_fmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_fmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmadd_ph(a, b, c), a) } @@ -5400,7 +5329,7 @@ pub const fn _mm256_mask_fmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask3_fmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmadd_ph(a, b, c), c) } @@ -5414,7 +5343,7 @@ pub const fn _mm256_mask3_fmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmas #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_fmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmadd_ph(a, b, c), _mm256_setzero_ph()) } @@ -5427,7 +5356,7 @@ pub const fn _mm256_maskz_fmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m2 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_fmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_fma(a, b, c) } @@ -5441,7 +5370,7 @@ pub const fn _mm512_fmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_fmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmadd_ph(a, b, c), a) } @@ -5455,7 +5384,7 @@ pub const fn _mm512_mask_fmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask3_fmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmadd_ph(a, b, c), c) } @@ -5469,7 +5398,7 @@ pub const fn _mm512_mask3_fmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmas #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_fmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmadd_ph(a, b, c), _mm512_setzero_ph()) } @@ -5491,7 +5420,7 @@ pub const fn _mm512_maskz_fmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m5 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmadd_round_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -5516,7 +5445,7 @@ pub fn _mm512_fmadd_round_ph(a: __m512h, b: __m512h, c: __m #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmadd_round_ph( a: __m512h, k: __mmask32, @@ -5546,7 +5475,7 @@ pub fn _mm512_mask_fmadd_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fmadd_round_ph( a: __m512h, b: __m512h, @@ -5576,7 +5505,7 @@ pub fn _mm512_mask3_fmadd_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmadd_round_ph( k: __mmask32, a: __m512h, @@ -5601,7 +5530,7 @@ pub fn _mm512_maskz_fmadd_round_ph( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -5622,7 +5551,7 @@ pub const fn _mm_fmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -5645,7 +5574,7 @@ pub const fn _mm_mask_fmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { @@ -5668,7 +5597,7 @@ pub const fn _mm_mask3_fmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -5700,7 +5629,7 @@ pub const fn _mm_maskz_fmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmadd_round_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -5730,7 +5659,7 @@ pub fn _mm_fmadd_round_sh(a: __m128h, b: __m128h, c: __m128 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmadd_round_sh( a: __m128h, k: __mmask8, @@ -5767,7 +5696,7 @@ pub fn _mm_mask_fmadd_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fmadd_round_sh( a: __m128h, b: __m128h, @@ -5804,7 +5733,7 @@ pub fn _mm_mask3_fmadd_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmadd_round_sh( k: __mmask8, a: __m128h, @@ -5832,7 +5761,7 @@ pub fn _mm_maskz_fmadd_round_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_fma(a, b, simd_neg(c)) } @@ -5846,7 +5775,7 @@ pub const fn _mm_fmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmsub_ph(a, b, c), a) } @@ -5860,7 +5789,7 @@ pub const fn _mm_mask_fmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmsub_ph(a, b, c), c) } @@ -5874,7 +5803,7 @@ pub const fn _mm_mask3_fmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmsub_ph(a, b, c), _mm_setzero_ph()) } @@ -5887,7 +5816,7 @@ pub const fn _mm_maskz_fmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_fmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_fma(a, b, simd_neg(c)) } @@ -5901,7 +5830,7 @@ pub const fn _mm256_fmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_fmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmsub_ph(a, b, c), a) } @@ -5915,7 +5844,7 @@ pub const fn _mm256_mask_fmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask3_fmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmsub_ph(a, b, c), c) } @@ -5929,7 +5858,7 @@ pub const fn _mm256_mask3_fmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmas #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_fmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmsub_ph(a, b, c), _mm256_setzero_ph()) } @@ -5942,7 +5871,7 @@ pub const fn _mm256_maskz_fmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m2 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_fmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_fma(a, b, simd_neg(c)) } @@ -5956,7 +5885,7 @@ pub const fn _mm512_fmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_fmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmsub_ph(a, b, c), a) } @@ -5970,7 +5899,7 @@ pub const fn _mm512_mask_fmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask3_fmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmsub_ph(a, b, c), c) } @@ -5984,7 +5913,7 @@ pub const fn _mm512_mask3_fmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmas #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_fmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmsub_ph(a, b, c), _mm512_setzero_ph()) } @@ -6006,7 +5935,7 @@ pub const fn _mm512_maskz_fmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m5 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmsub_round_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -6031,7 +5960,7 @@ pub fn _mm512_fmsub_round_ph(a: __m512h, b: __m512h, c: __m #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmsub_round_ph( a: __m512h, k: __mmask32, @@ -6061,7 +5990,7 @@ pub fn _mm512_mask_fmsub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fmsub_round_ph( a: __m512h, b: __m512h, @@ -6091,7 +6020,7 @@ pub fn _mm512_mask3_fmsub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmsub_round_ph( k: __mmask32, a: __m512h, @@ -6116,7 +6045,7 @@ pub fn _mm512_maskz_fmsub_round_ph( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -6137,7 +6066,7 @@ pub const fn _mm_fmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -6160,7 +6089,7 @@ pub const fn _mm_mask_fmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { @@ -6183,7 +6112,7 @@ pub const fn _mm_mask3_fmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -6215,7 +6144,7 @@ pub const fn _mm_maskz_fmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmsub_round_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -6245,7 +6174,7 @@ pub fn _mm_fmsub_round_sh(a: __m128h, b: __m128h, c: __m128 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmsub_round_sh( a: __m128h, k: __mmask8, @@ -6282,7 +6211,7 @@ pub fn _mm_mask_fmsub_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fmsub_round_sh( a: __m128h, b: __m128h, @@ -6311,7 +6240,7 @@ pub fn _mm_mask3_fmsub_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmsub_round_sh( k: __mmask8, a: __m128h, @@ -6338,7 +6267,7 @@ pub fn _mm_maskz_fmsub_round_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_fma(simd_neg(a), b, c) } @@ -6352,7 +6281,7 @@ pub const fn _mm_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fnmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fnmadd_ph(a, b, c), a) } @@ -6366,7 +6295,7 @@ pub const fn _mm_mask_fnmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fnmadd_ph(a, b, c), c) } @@ -6380,7 +6309,7 @@ pub const fn _mm_mask3_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fnmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fnmadd_ph(a, b, c), _mm_setzero_ph()) } @@ -6393,7 +6322,7 @@ pub const fn _mm_maskz_fnmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_fma(simd_neg(a), b, c) } @@ -6407,7 +6336,7 @@ pub const fn _mm256_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_fnmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fnmadd_ph(a, b, c), a) } @@ -6421,7 +6350,7 @@ pub const fn _mm256_mask_fnmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m2 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask3_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fnmadd_ph(a, b, c), c) } @@ -6435,7 +6364,7 @@ pub const fn _mm256_mask3_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mma #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_fnmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fnmadd_ph(a, b, c), _mm256_setzero_ph()) } @@ -6448,7 +6377,7 @@ pub const fn _mm256_maskz_fnmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_fma(simd_neg(a), b, c) } @@ -6462,7 +6391,7 @@ pub const fn _mm512_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_fnmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fnmadd_ph(a, b, c), a) } @@ -6476,7 +6405,7 @@ pub const fn _mm512_mask_fnmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m5 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask3_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fnmadd_ph(a, b, c), c) } @@ -6490,7 +6419,7 @@ pub const fn _mm512_mask3_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mma #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_fnmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fnmadd_ph(a, b, c), _mm512_setzero_ph()) } @@ -6512,7 +6441,7 @@ pub const fn _mm512_maskz_fnmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fnmadd_round_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -6537,7 +6466,7 @@ pub fn _mm512_fnmadd_round_ph(a: __m512h, b: __m512h, c: __ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fnmadd_round_ph( a: __m512h, k: __mmask32, @@ -6567,7 +6496,7 @@ pub fn _mm512_mask_fnmadd_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fnmadd_round_ph( a: __m512h, b: __m512h, @@ -6597,7 +6526,7 @@ pub fn _mm512_mask3_fnmadd_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fnmadd_round_ph( k: __mmask32, a: __m512h, @@ -6622,7 +6551,7 @@ pub fn _mm512_maskz_fnmadd_round_ph( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -6643,7 +6572,7 @@ pub const fn _mm_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fnmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -6666,7 +6595,7 @@ pub const fn _mm_mask_fnmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { @@ -6689,7 +6618,7 @@ pub const fn _mm_mask3_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fnmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -6721,7 +6650,7 @@ pub const fn _mm_maskz_fnmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fnmadd_round_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -6751,7 +6680,7 @@ pub fn _mm_fnmadd_round_sh(a: __m128h, b: __m128h, c: __m12 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fnmadd_round_sh( a: __m128h, k: __mmask8, @@ -6788,7 +6717,7 @@ pub fn _mm_mask_fnmadd_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fnmadd_round_sh( a: __m128h, b: __m128h, @@ -6825,7 +6754,7 @@ pub fn _mm_mask3_fnmadd_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fnmadd_round_sh( k: __mmask8, a: __m128h, @@ -6852,7 +6781,7 @@ pub fn _mm_maskz_fnmadd_round_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) } @@ -6866,7 +6795,7 @@ pub const fn _mm_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fnmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fnmsub_ph(a, b, c), a) } @@ -6880,7 +6809,7 @@ pub const fn _mm_mask_fnmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fnmsub_ph(a, b, c), c) } @@ -6894,7 +6823,7 @@ pub const fn _mm_mask3_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fnmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fnmsub_ph(a, b, c), _mm_setzero_ph()) } @@ -6907,7 +6836,7 @@ pub const fn _mm_maskz_fnmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) } @@ -6921,7 +6850,7 @@ pub const fn _mm256_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_fnmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fnmsub_ph(a, b, c), a) } @@ -6935,7 +6864,7 @@ pub const fn _mm256_mask_fnmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m2 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask3_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fnmsub_ph(a, b, c), c) } @@ -6949,7 +6878,7 @@ pub const fn _mm256_mask3_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mma #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_fnmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fnmsub_ph(a, b, c), _mm256_setzero_ph()) } @@ -6962,7 +6891,7 @@ pub const fn _mm256_maskz_fnmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) } @@ -6976,7 +6905,7 @@ pub const fn _mm512_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_fnmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fnmsub_ph(a, b, c), a) } @@ -6990,7 +6919,7 @@ pub const fn _mm512_mask_fnmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m5 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask3_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fnmsub_ph(a, b, c), c) } @@ -7004,7 +6933,7 @@ pub const fn _mm512_mask3_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mma #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_fnmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fnmsub_ph(a, b, c), _mm512_setzero_ph()) } @@ -7026,7 +6955,7 @@ pub const fn _mm512_maskz_fnmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fnmsub_round_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -7051,7 +6980,7 @@ pub fn _mm512_fnmsub_round_ph(a: __m512h, b: __m512h, c: __ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fnmsub_round_ph( a: __m512h, k: __mmask32, @@ -7081,7 +7010,7 @@ pub fn _mm512_mask_fnmsub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fnmsub_round_ph( a: __m512h, b: __m512h, @@ -7111,7 +7040,7 @@ pub fn _mm512_mask3_fnmsub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fnmsub_round_ph( k: __mmask32, a: __m512h, @@ -7136,7 +7065,7 @@ pub fn _mm512_maskz_fnmsub_round_ph( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -7157,7 +7086,7 @@ pub const fn _mm_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fnmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -7180,7 +7109,7 @@ pub const fn _mm_mask_fnmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { @@ -7203,7 +7132,7 @@ pub const fn _mm_mask3_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fnmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -7235,7 +7164,7 @@ pub const fn _mm_maskz_fnmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fnmsub_round_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -7265,7 +7194,7 @@ pub fn _mm_fnmsub_round_sh(a: __m128h, b: __m128h, c: __m12 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fnmsub_round_sh( a: __m128h, k: __mmask8, @@ -7302,7 +7231,7 @@ pub fn _mm_mask_fnmsub_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fnmsub_round_sh( a: __m128h, b: __m128h, @@ -7339,7 +7268,7 @@ pub fn _mm_mask3_fnmsub_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fnmsub_round_sh( k: __mmask8, a: __m128h, @@ -7366,7 +7295,7 @@ pub fn _mm_maskz_fnmsub_round_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -7384,7 +7313,7 @@ pub const fn _mm_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fmaddsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmaddsub_ph(a, b, c), a) } @@ -7398,7 +7327,7 @@ pub const fn _mm_mask_fmaddsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmaddsub_ph(a, b, c), c) } @@ -7412,7 +7341,7 @@ pub const fn _mm_mask3_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmas #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fmaddsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmaddsub_ph(a, b, c), _mm_setzero_ph()) } @@ -7425,7 +7354,7 @@ pub const fn _mm_maskz_fmaddsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m12 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { @@ -7447,7 +7376,7 @@ pub const fn _mm256_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_fmaddsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ph(a, b, c), a) } @@ -7461,7 +7390,7 @@ pub const fn _mm256_mask_fmaddsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask3_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ph(a, b, c), c) } @@ -7475,7 +7404,7 @@ pub const fn _mm256_mask3_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __m #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_fmaddsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ph(a, b, c), _mm256_setzero_ph()) } @@ -7488,7 +7417,7 @@ pub const fn _mm256_maskz_fmaddsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { @@ -7513,7 +7442,7 @@ pub const fn _mm512_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_fmaddsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ph(a, b, c), a) } @@ -7527,7 +7456,7 @@ pub const fn _mm512_mask_fmaddsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask3_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ph(a, b, c), c) } @@ -7541,7 +7470,7 @@ pub const fn _mm512_mask3_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __m #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_fmaddsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ph(a, b, c), _mm512_setzero_ph()) } @@ -7563,7 +7492,7 @@ pub const fn _mm512_maskz_fmaddsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: _ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmaddsub_round_ph( a: __m512h, b: __m512h, @@ -7592,7 +7521,7 @@ pub fn _mm512_fmaddsub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmaddsub_round_ph( a: __m512h, k: __mmask32, @@ -7622,7 +7551,7 @@ pub fn _mm512_mask_fmaddsub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fmaddsub_round_ph( a: __m512h, b: __m512h, @@ -7652,7 +7581,7 @@ pub fn _mm512_mask3_fmaddsub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmaddsub_round_ph( k: __mmask32, a: __m512h, @@ -7676,7 +7605,7 @@ pub fn _mm512_maskz_fmaddsub_round_ph( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { _mm_fmaddsub_ph(a, b, unsafe { simd_neg(c) }) @@ -7690,7 +7619,7 @@ pub const fn _mm_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fmsubadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmsubadd_ph(a, b, c), a) } @@ -7704,7 +7633,7 @@ pub const fn _mm_mask_fmsubadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmsubadd_ph(a, b, c), c) } @@ -7718,7 +7647,7 @@ pub const fn _mm_mask3_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmas #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fmsubadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmsubadd_ph(a, b, c), _mm_setzero_ph()) } @@ -7731,7 +7660,7 @@ pub const fn _mm_maskz_fmsubadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m12 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { _mm256_fmaddsub_ph(a, b, unsafe { simd_neg(c) }) @@ -7745,7 +7674,7 @@ pub const fn _mm256_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_fmsubadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ph(a, b, c), a) } @@ -7759,7 +7688,7 @@ pub const fn _mm256_mask_fmsubadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask3_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ph(a, b, c), c) } @@ -7773,7 +7702,7 @@ pub const fn _mm256_mask3_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __m #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_fmsubadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ph(a, b, c), _mm256_setzero_ph()) } @@ -7786,7 +7715,7 @@ pub const fn _mm256_maskz_fmsubadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { _mm512_fmaddsub_ph(a, b, unsafe { simd_neg(c) }) @@ -7800,7 +7729,7 @@ pub const fn _mm512_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_fmsubadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ph(a, b, c), a) } @@ -7814,7 +7743,7 @@ pub const fn _mm512_mask_fmsubadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask3_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ph(a, b, c), c) } @@ -7828,7 +7757,7 @@ pub const fn _mm512_mask3_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __m #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_fmsubadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ph(a, b, c), _mm512_setzero_ph()) } @@ -7850,7 +7779,7 @@ pub const fn _mm512_maskz_fmsubadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: _ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmsubadd_round_ph( a: __m512h, b: __m512h, @@ -7879,7 +7808,7 @@ pub fn _mm512_fmsubadd_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmsubadd_round_ph( a: __m512h, k: __mmask32, @@ -7909,7 +7838,7 @@ pub fn _mm512_mask_fmsubadd_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fmsubadd_round_ph( a: __m512h, b: __m512h, @@ -7939,7 +7868,7 @@ pub fn _mm512_mask3_fmsubadd_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmsubadd_round_ph( k: __mmask32, a: __m512h, @@ -7963,7 +7892,7 @@ pub fn _mm512_maskz_fmsubadd_round_ph( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_rcp_ph(a: __m128h) -> __m128h { _mm_mask_rcp_ph(_mm_undefined_ph(), 0xff, a) } @@ -7976,7 +7905,7 @@ pub fn _mm_rcp_ph(a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_rcp_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { unsafe { vrcpph_128(a, src, k) } } @@ -7989,7 +7918,7 @@ pub fn _mm_mask_rcp_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_rcp_ph(k: __mmask8, a: __m128h) -> __m128h { _mm_mask_rcp_ph(_mm_setzero_ph(), k, a) } @@ -8001,7 +7930,7 @@ pub fn _mm_maskz_rcp_ph(k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_rcp_ph(a: __m256h) -> __m256h { _mm256_mask_rcp_ph(_mm256_undefined_ph(), 0xffff, a) } @@ -8014,7 +7943,7 @@ pub fn _mm256_rcp_ph(a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_rcp_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { unsafe { vrcpph_256(a, src, k) } } @@ -8027,7 +7956,7 @@ pub fn _mm256_mask_rcp_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_rcp_ph(k: __mmask16, a: __m256h) -> __m256h { _mm256_mask_rcp_ph(_mm256_setzero_ph(), k, a) } @@ -8039,7 +7968,7 @@ pub fn _mm256_maskz_rcp_ph(k: __mmask16, a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_rcp_ph(a: __m512h) -> __m512h { _mm512_mask_rcp_ph(_mm512_undefined_ph(), 0xffffffff, a) } @@ -8052,7 +7981,7 @@ pub fn _mm512_rcp_ph(a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_rcp_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { unsafe { vrcpph_512(a, src, k) } } @@ -8065,7 +7994,7 @@ pub fn _mm512_mask_rcp_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_rcp_ph(k: __mmask32, a: __m512h) -> __m512h { _mm512_mask_rcp_ph(_mm512_setzero_ph(), k, a) } @@ -8079,7 +8008,7 @@ pub fn _mm512_maskz_rcp_ph(k: __mmask32, a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrcpsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_rcp_sh(a: __m128h, b: __m128h) -> __m128h { _mm_mask_rcp_sh(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -8093,7 +8022,7 @@ pub fn _mm_rcp_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrcpsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_rcp_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { vrcpsh(a, b, src, k) } } @@ -8107,7 +8036,7 @@ pub fn _mm_mask_rcp_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrcpsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_rcp_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_rcp_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -8120,7 +8049,7 @@ pub fn _mm_maskz_rcp_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_rsqrt_ph(a: __m128h) -> __m128h { _mm_mask_rsqrt_ph(_mm_undefined_ph(), 0xff, a) } @@ -8134,7 +8063,7 @@ pub fn _mm_rsqrt_ph(a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_rsqrt_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { unsafe { vrsqrtph_128(a, src, k) } } @@ -8148,7 +8077,7 @@ pub fn _mm_mask_rsqrt_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_rsqrt_ph(k: __mmask8, a: __m128h) -> __m128h { _mm_mask_rsqrt_ph(_mm_setzero_ph(), k, a) } @@ -8161,7 +8090,7 @@ pub fn _mm_maskz_rsqrt_ph(k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_rsqrt_ph(a: __m256h) -> __m256h { _mm256_mask_rsqrt_ph(_mm256_undefined_ph(), 0xffff, a) } @@ -8175,7 +8104,7 @@ pub fn _mm256_rsqrt_ph(a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_rsqrt_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { unsafe { vrsqrtph_256(a, src, k) } } @@ -8189,7 +8118,7 @@ pub fn _mm256_mask_rsqrt_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_rsqrt_ph(k: __mmask16, a: __m256h) -> __m256h { _mm256_mask_rsqrt_ph(_mm256_setzero_ph(), k, a) } @@ -8202,7 +8131,7 @@ pub fn _mm256_maskz_rsqrt_ph(k: __mmask16, a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_rsqrt_ph(a: __m512h) -> __m512h { _mm512_mask_rsqrt_ph(_mm512_undefined_ph(), 0xffffffff, a) } @@ -8216,7 +8145,7 @@ pub fn _mm512_rsqrt_ph(a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_rsqrt_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { unsafe { vrsqrtph_512(a, src, k) } } @@ -8230,7 +8159,7 @@ pub fn _mm512_mask_rsqrt_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_rsqrt_ph(k: __mmask32, a: __m512h) -> __m512h { _mm512_mask_rsqrt_ph(_mm512_setzero_ph(), k, a) } @@ -8244,7 +8173,7 @@ pub fn _mm512_maskz_rsqrt_ph(k: __mmask32, a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrsqrtsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_rsqrt_sh(a: __m128h, b: __m128h) -> __m128h { _mm_mask_rsqrt_sh(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -8258,7 +8187,7 @@ pub fn _mm_rsqrt_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrsqrtsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_rsqrt_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { vrsqrtsh(a, b, src, k) } } @@ -8272,7 +8201,7 @@ pub fn _mm_mask_rsqrt_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrsqrtsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_rsqrt_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_rsqrt_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -8284,7 +8213,7 @@ pub fn _mm_maskz_rsqrt_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_sqrt_ph(a: __m128h) -> __m128h { unsafe { simd_fsqrt(a) } } @@ -8296,7 +8225,7 @@ pub fn _mm_sqrt_ph(a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_sqrt_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_sqrt_ph(a), src) } } @@ -8308,7 +8237,7 @@ pub fn _mm_mask_sqrt_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_sqrt_ph(k: __mmask8, a: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_sqrt_ph(a), _mm_setzero_ph()) } } @@ -8320,7 +8249,7 @@ pub fn _mm_maskz_sqrt_ph(k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_sqrt_ph(a: __m256h) -> __m256h { unsafe { simd_fsqrt(a) } } @@ -8332,7 +8261,7 @@ pub fn _mm256_sqrt_ph(a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_sqrt_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_sqrt_ph(a), src) } } @@ -8344,7 +8273,7 @@ pub fn _mm256_mask_sqrt_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_sqrt_ph(k: __mmask16, a: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_sqrt_ph(a), _mm256_setzero_ph()) } } @@ -8356,7 +8285,7 @@ pub fn _mm256_maskz_sqrt_ph(k: __mmask16, a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_sqrt_ph(a: __m512h) -> __m512h { unsafe { simd_fsqrt(a) } } @@ -8368,7 +8297,7 @@ pub fn _mm512_sqrt_ph(a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_sqrt_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_sqrt_ph(a), src) } } @@ -8380,7 +8309,7 @@ pub fn _mm512_mask_sqrt_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_sqrt_ph(k: __mmask32, a: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_sqrt_ph(a), _mm512_setzero_ph()) } } @@ -8400,7 +8329,7 @@ pub fn _mm512_maskz_sqrt_ph(k: __mmask32, a: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_sqrt_round_ph(a: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -8423,7 +8352,7 @@ pub fn _mm512_sqrt_round_ph(a: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_sqrt_round_ph( src: __m512h, k: __mmask32, @@ -8450,7 +8379,7 @@ pub fn _mm512_mask_sqrt_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_sqrt_round_ph(k: __mmask32, a: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -8466,7 +8395,7 @@ pub fn _mm512_maskz_sqrt_round_ph(k: __mmask32, a: __m512h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_sqrt_sh(a: __m128h, b: __m128h) -> __m128h { _mm_mask_sqrt_sh(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -8479,7 +8408,7 @@ pub fn _mm_sqrt_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_sqrt_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_sqrt_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -8492,7 +8421,7 @@ pub fn _mm_mask_sqrt_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_sqrt_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_sqrt_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -8513,7 +8442,7 @@ pub fn _mm_maskz_sqrt_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_sqrt_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_sqrt_round_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -8535,7 +8464,7 @@ pub fn _mm_sqrt_round_sh(a: __m128h, b: __m128h) -> __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_sqrt_round_sh( src: __m128h, k: __mmask8, @@ -8564,7 +8493,7 @@ pub fn _mm_mask_sqrt_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_sqrt_round_sh( k: __mmask8, a: __m128h, @@ -8582,7 +8511,7 @@ pub fn _mm_maskz_sqrt_round_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_max_ph(a: __m128h, b: __m128h) -> __m128h { unsafe { vmaxph_128(a, b) } } @@ -8596,7 +8525,7 @@ pub fn _mm_max_ph(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_max_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_max_ph(a, b), src) } } @@ -8610,7 +8539,7 @@ pub fn _mm_mask_max_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_max_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_max_ph(a, b), _mm_setzero_ph()) } } @@ -8623,7 +8552,7 @@ pub fn _mm_maskz_max_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_max_ph(a: __m256h, b: __m256h) -> __m256h { unsafe { vmaxph_256(a, b) } } @@ -8637,7 +8566,7 @@ pub fn _mm256_max_ph(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_max_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_max_ph(a, b), src) } } @@ -8651,7 +8580,7 @@ pub fn _mm256_mask_max_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_max_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_max_ph(a, b), _mm256_setzero_ph()) } } @@ -8664,7 +8593,7 @@ pub fn _mm256_maskz_max_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_max_ph(a: __m512h, b: __m512h) -> __m512h { _mm512_max_round_ph::<_MM_FROUND_CUR_DIRECTION>(a, b) } @@ -8678,7 +8607,7 @@ pub fn _mm512_max_ph(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_max_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_max_ph(a, b), src) } } @@ -8692,7 +8621,7 @@ pub fn _mm512_mask_max_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_max_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_max_ph(a, b), _mm512_setzero_ph()) } } @@ -8707,7 +8636,7 @@ pub fn _mm512_maskz_max_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmaxph, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_max_round_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_sae!(SAE); @@ -8725,7 +8654,7 @@ pub fn _mm512_max_round_ph(a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmaxph, SAE = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_max_round_ph( src: __m512h, k: __mmask32, @@ -8748,7 +8677,7 @@ pub fn _mm512_mask_max_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmaxph, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_max_round_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_sae!(SAE); @@ -8765,7 +8694,7 @@ pub fn _mm512_maskz_max_round_ph(k: __mmask32, a: __m512h, b: __ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_max_sh(a: __m128h, b: __m128h) -> __m128h { _mm_mask_max_sh(_mm_undefined_ph(), 0xff, a, b) } @@ -8779,7 +8708,7 @@ pub fn _mm_max_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_max_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_max_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -8793,7 +8722,7 @@ pub fn _mm_mask_max_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_max_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_max_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -8808,7 +8737,7 @@ pub fn _mm_maskz_max_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxsh, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_max_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_sae!(SAE); _mm_mask_max_round_sh::(_mm_undefined_ph(), 0xff, a, b) @@ -8825,7 +8754,7 @@ pub fn _mm_max_round_sh(a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxsh, SAE = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_max_round_sh( src: __m128h, k: __mmask8, @@ -8849,7 +8778,7 @@ pub fn _mm_mask_max_round_sh( #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxsh, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_max_round_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_sae!(SAE); _mm_mask_max_round_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -8863,7 +8792,7 @@ pub fn _mm_maskz_max_round_sh(k: __mmask8, a: __m128h, b: __m128 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_min_ph(a: __m128h, b: __m128h) -> __m128h { unsafe { vminph_128(a, b) } } @@ -8877,7 +8806,7 @@ pub fn _mm_min_ph(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_min_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_min_ph(a, b), src) } } @@ -8891,7 +8820,7 @@ pub fn _mm_mask_min_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_min_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_min_ph(a, b), _mm_setzero_ph()) } } @@ -8904,7 +8833,7 @@ pub fn _mm_maskz_min_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_min_ph(a: __m256h, b: __m256h) -> __m256h { unsafe { vminph_256(a, b) } } @@ -8918,7 +8847,7 @@ pub fn _mm256_min_ph(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_min_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_min_ph(a, b), src) } } @@ -8932,7 +8861,7 @@ pub fn _mm256_mask_min_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_min_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_min_ph(a, b), _mm256_setzero_ph()) } } @@ -8945,7 +8874,7 @@ pub fn _mm256_maskz_min_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_min_ph(a: __m512h, b: __m512h) -> __m512h { _mm512_min_round_ph::<_MM_FROUND_CUR_DIRECTION>(a, b) } @@ -8959,7 +8888,7 @@ pub fn _mm512_min_ph(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_min_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_min_ph(a, b), src) } } @@ -8973,7 +8902,7 @@ pub fn _mm512_mask_min_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_min_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_min_ph(a, b), _mm512_setzero_ph()) } } @@ -8987,7 +8916,7 @@ pub fn _mm512_maskz_min_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vminph, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_min_round_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_sae!(SAE); @@ -9005,7 +8934,7 @@ pub fn _mm512_min_round_ph(a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vminph, SAE = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_min_round_ph( src: __m512h, k: __mmask32, @@ -9028,7 +8957,7 @@ pub fn _mm512_mask_min_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vminph, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_min_round_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_sae!(SAE); @@ -9045,7 +8974,7 @@ pub fn _mm512_maskz_min_round_ph(k: __mmask32, a: __m512h, b: __ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_min_sh(a: __m128h, b: __m128h) -> __m128h { _mm_mask_min_sh(_mm_undefined_ph(), 0xff, a, b) } @@ -9059,7 +8988,7 @@ pub fn _mm_min_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_min_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_min_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -9073,7 +9002,7 @@ pub fn _mm_mask_min_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_min_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_min_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -9088,7 +9017,7 @@ pub fn _mm_maskz_min_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminsh, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_min_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_sae!(SAE); _mm_mask_min_round_sh::(_mm_undefined_ph(), 0xff, a, b) @@ -9105,7 +9034,7 @@ pub fn _mm_min_round_sh(a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminsh, SAE = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_min_round_sh( src: __m128h, k: __mmask8, @@ -9129,7 +9058,7 @@ pub fn _mm_mask_min_round_sh( #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminsh, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_min_round_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_sae!(SAE); _mm_mask_min_round_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -9143,7 +9072,7 @@ pub fn _mm_maskz_min_round_sh(k: __mmask8, a: __m128h, b: __m128 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_getexp_ph(a: __m128h) -> __m128h { _mm_mask_getexp_ph(_mm_undefined_ph(), 0xff, a) } @@ -9157,7 +9086,7 @@ pub fn _mm_getexp_ph(a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_getexp_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { unsafe { vgetexpph_128(a, src, k) } } @@ -9171,7 +9100,7 @@ pub fn _mm_mask_getexp_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_getexp_ph(k: __mmask8, a: __m128h) -> __m128h { _mm_mask_getexp_ph(_mm_setzero_ph(), k, a) } @@ -9184,7 +9113,7 @@ pub fn _mm_maskz_getexp_ph(k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_getexp_ph(a: __m256h) -> __m256h { _mm256_mask_getexp_ph(_mm256_undefined_ph(), 0xffff, a) } @@ -9198,7 +9127,7 @@ pub fn _mm256_getexp_ph(a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_getexp_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { unsafe { vgetexpph_256(a, src, k) } } @@ -9212,7 +9141,7 @@ pub fn _mm256_mask_getexp_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_getexp_ph(k: __mmask16, a: __m256h) -> __m256h { _mm256_mask_getexp_ph(_mm256_setzero_ph(), k, a) } @@ -9225,7 +9154,7 @@ pub fn _mm256_maskz_getexp_ph(k: __mmask16, a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_getexp_ph(a: __m512h) -> __m512h { _mm512_mask_getexp_ph(_mm512_undefined_ph(), 0xffffffff, a) } @@ -9239,7 +9168,7 @@ pub fn _mm512_getexp_ph(a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_getexp_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { _mm512_mask_getexp_round_ph::<_MM_FROUND_CUR_DIRECTION>(src, k, a) } @@ -9253,7 +9182,7 @@ pub fn _mm512_mask_getexp_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_getexp_ph(k: __mmask32, a: __m512h) -> __m512h { _mm512_mask_getexp_ph(_mm512_setzero_ph(), k, a) } @@ -9268,7 +9197,7 @@ pub fn _mm512_maskz_getexp_ph(k: __mmask32, a: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpph, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_getexp_round_ph(a: __m512h) -> __m512h { static_assert_sae!(SAE); _mm512_mask_getexp_round_ph::(_mm512_undefined_ph(), 0xffffffff, a) @@ -9284,7 +9213,7 @@ pub fn _mm512_getexp_round_ph(a: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpph, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_getexp_round_ph( src: __m512h, k: __mmask32, @@ -9306,7 +9235,7 @@ pub fn _mm512_mask_getexp_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpph, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_getexp_round_ph(k: __mmask32, a: __m512h) -> __m512h { static_assert_sae!(SAE); _mm512_mask_getexp_round_ph::(_mm512_setzero_ph(), k, a) @@ -9321,7 +9250,7 @@ pub fn _mm512_maskz_getexp_round_ph(k: __mmask32, a: __m512h) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_getexp_sh(a: __m128h, b: __m128h) -> __m128h { _mm_mask_getexp_sh(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -9336,7 +9265,7 @@ pub fn _mm_getexp_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_getexp_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_getexp_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -9351,7 +9280,7 @@ pub fn _mm_mask_getexp_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_getexp_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_getexp_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -9367,7 +9296,7 @@ pub fn _mm_maskz_getexp_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpsh, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_getexp_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_sae!(SAE); _mm_mask_getexp_round_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -9384,7 +9313,7 @@ pub fn _mm_getexp_round_sh(a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpsh, SAE = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_getexp_round_sh( src: __m128h, k: __mmask8, @@ -9408,7 +9337,7 @@ pub fn _mm_mask_getexp_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpsh, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_getexp_round_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_sae!(SAE); _mm_mask_getexp_round_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -9436,7 +9365,7 @@ pub fn _mm_maskz_getexp_round_sh(k: __mmask8, a: __m128h, b: __m #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))] #[rustc_legacy_const_generics(1, 2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_getmant_ph( a: __m128h, ) -> __m128h { @@ -9468,7 +9397,7 @@ pub fn _mm_getmant_ph( a: __m256h, ) -> __m256h { @@ -9574,7 +9503,7 @@ pub fn _mm256_getmant_ph( a: __m512h, ) -> __m512h { @@ -9680,7 +9609,7 @@ pub fn _mm512_getmant_ph( a: __m128h, b: __m128h, @@ -9911,7 +9840,7 @@ pub fn _mm_getmant_sh(a: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_roundscale_ph::(_mm_undefined_ph(), 0xff, a) @@ -10131,7 +10060,7 @@ pub fn _mm_roundscale_ph(a: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_roundscale_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -10156,7 +10085,7 @@ pub fn _mm_mask_roundscale_ph(src: __m128h, k: __mmask8, a: __m #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_roundscale_ph(k: __mmask8, a: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_roundscale_ph::(_mm_setzero_ph(), k, a) @@ -10178,7 +10107,7 @@ pub fn _mm_maskz_roundscale_ph(k: __mmask8, a: __m128h) -> __m1 #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_roundscale_ph(a: __m256h) -> __m256h { static_assert_uimm_bits!(IMM8, 8); _mm256_mask_roundscale_ph::(_mm256_undefined_ph(), 0xffff, a) @@ -10201,7 +10130,7 @@ pub fn _mm256_roundscale_ph(a: __m256h) -> __m256h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_roundscale_ph( src: __m256h, k: __mmask16, @@ -10230,7 +10159,7 @@ pub fn _mm256_mask_roundscale_ph( #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_roundscale_ph(k: __mmask16, a: __m256h) -> __m256h { static_assert_uimm_bits!(IMM8, 8); _mm256_mask_roundscale_ph::(_mm256_setzero_ph(), k, a) @@ -10252,7 +10181,7 @@ pub fn _mm256_maskz_roundscale_ph(k: __mmask16, a: __m256h) -> #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_roundscale_ph(a: __m512h) -> __m512h { static_assert_uimm_bits!(IMM8, 8); _mm512_mask_roundscale_ph::(_mm512_undefined_ph(), 0xffffffff, a) @@ -10275,7 +10204,7 @@ pub fn _mm512_roundscale_ph(a: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_roundscale_ph( src: __m512h, k: __mmask32, @@ -10302,7 +10231,7 @@ pub fn _mm512_mask_roundscale_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_roundscale_ph(k: __mmask32, a: __m512h) -> __m512h { static_assert_uimm_bits!(IMM8, 8); _mm512_mask_roundscale_ph::(_mm512_setzero_ph(), k, a) @@ -10325,7 +10254,7 @@ pub fn _mm512_maskz_roundscale_ph(k: __mmask32, a: __m512h) -> #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(1, 2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_roundscale_round_ph(a: __m512h) -> __m512h { static_assert_uimm_bits!(IMM8, 8); static_assert_sae!(SAE); @@ -10350,7 +10279,7 @@ pub fn _mm512_roundscale_round_ph(a: __m512h) - #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_roundscale_round_ph( src: __m512h, k: __mmask32, @@ -10380,7 +10309,7 @@ pub fn _mm512_mask_roundscale_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_roundscale_round_ph( k: __mmask32, a: __m512h, @@ -10407,7 +10336,7 @@ pub fn _mm512_maskz_roundscale_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_roundscale_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_roundscale_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -10430,7 +10359,7 @@ pub fn _mm_roundscale_sh(a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_roundscale_sh( src: __m128h, k: __mmask8, @@ -10458,7 +10387,7 @@ pub fn _mm_mask_roundscale_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_roundscale_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_roundscale_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -10483,7 +10412,7 @@ pub fn _mm_maskz_roundscale_sh(k: __mmask8, a: __m128h, b: __m1 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_roundscale_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); static_assert_sae!(SAE); @@ -10509,7 +10438,7 @@ pub fn _mm_roundscale_round_sh(a: __m128h, b: _ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(4, 5)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_roundscale_round_sh( src: __m128h, k: __mmask8, @@ -10542,7 +10471,7 @@ pub fn _mm_mask_roundscale_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_roundscale_round_sh( k: __mmask8, a: __m128h, @@ -10560,7 +10489,7 @@ pub fn _mm_maskz_roundscale_round_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_scalef_ph(a: __m128h, b: __m128h) -> __m128h { _mm_mask_scalef_ph(_mm_undefined_ph(), 0xff, a, b) } @@ -10572,7 +10501,7 @@ pub fn _mm_scalef_ph(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_scalef_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { vscalefph_128(a, b, src, k) } } @@ -10584,7 +10513,7 @@ pub fn _mm_mask_scalef_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_scalef_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_scalef_ph(_mm_setzero_ph(), k, a, b) } @@ -10596,7 +10525,7 @@ pub fn _mm_maskz_scalef_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_scalef_ph(a: __m256h, b: __m256h) -> __m256h { _mm256_mask_scalef_ph(_mm256_undefined_ph(), 0xffff, a, b) } @@ -10608,7 +10537,7 @@ pub fn _mm256_scalef_ph(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_scalef_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { vscalefph_256(a, b, src, k) } } @@ -10620,7 +10549,7 @@ pub fn _mm256_mask_scalef_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_scalef_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { _mm256_mask_scalef_ph(_mm256_setzero_ph(), k, a, b) } @@ -10632,7 +10561,7 @@ pub fn _mm256_maskz_scalef_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_scalef_ph(a: __m512h, b: __m512h) -> __m512h { _mm512_mask_scalef_ph(_mm512_undefined_ph(), 0xffffffff, a, b) } @@ -10644,7 +10573,7 @@ pub fn _mm512_scalef_ph(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_scalef_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_scalef_round_ph::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -10656,7 +10585,7 @@ pub fn _mm512_mask_scalef_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_scalef_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_scalef_ph(_mm512_setzero_ph(), k, a, b) } @@ -10677,7 +10606,7 @@ pub fn _mm512_maskz_scalef_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_scalef_round_ph(a: __m512h, b: __m512h) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mask_scalef_round_ph::(_mm512_undefined_ph(), 0xffffffff, a, b) @@ -10699,7 +10628,7 @@ pub fn _mm512_scalef_round_ph(a: __m512h, b: __m512h) -> __ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_scalef_round_ph( src: __m512h, k: __mmask32, @@ -10728,7 +10657,7 @@ pub fn _mm512_mask_scalef_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_scalef_round_ph( k: __mmask32, a: __m512h, @@ -10746,7 +10675,7 @@ pub fn _mm512_maskz_scalef_round_ph( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_scalef_sh(a: __m128h, b: __m128h) -> __m128h { _mm_mask_scalef_sh(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -10759,7 +10688,7 @@ pub fn _mm_scalef_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_scalef_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_scalef_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -10772,7 +10701,7 @@ pub fn _mm_mask_scalef_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_scalef_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_scalef_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -10794,7 +10723,7 @@ pub fn _mm_maskz_scalef_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_scalef_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_scalef_round_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -10817,7 +10746,7 @@ pub fn _mm_scalef_round_sh(a: __m128h, b: __m128h) -> __m12 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_scalef_round_sh( src: __m128h, k: __mmask8, @@ -10847,7 +10776,7 @@ pub fn _mm_mask_scalef_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_scalef_round_sh( k: __mmask8, a: __m128h, @@ -10873,7 +10802,7 @@ pub fn _mm_maskz_scalef_round_sh( #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_reduce_ph(a: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_reduce_ph::(_mm_undefined_ph(), 0xff, a) @@ -10896,7 +10825,7 @@ pub fn _mm_reduce_ph(a: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_reduce_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -10921,7 +10850,7 @@ pub fn _mm_mask_reduce_ph(src: __m128h, k: __mmask8, a: __m128h #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_reduce_ph(k: __mmask8, a: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_reduce_ph::(_mm_setzero_ph(), k, a) @@ -10943,7 +10872,7 @@ pub fn _mm_maskz_reduce_ph(k: __mmask8, a: __m128h) -> __m128h #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_reduce_ph(a: __m256h) -> __m256h { static_assert_uimm_bits!(IMM8, 8); _mm256_mask_reduce_ph::(_mm256_undefined_ph(), 0xffff, a) @@ -10966,7 +10895,7 @@ pub fn _mm256_reduce_ph(a: __m256h) -> __m256h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_reduce_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -10991,7 +10920,7 @@ pub fn _mm256_mask_reduce_ph(src: __m256h, k: __mmask16, a: __m #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_reduce_ph(k: __mmask16, a: __m256h) -> __m256h { static_assert_uimm_bits!(IMM8, 8); _mm256_mask_reduce_ph::(_mm256_setzero_ph(), k, a) @@ -11013,7 +10942,7 @@ pub fn _mm256_maskz_reduce_ph(k: __mmask16, a: __m256h) -> __m2 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_reduce_ph(a: __m512h) -> __m512h { static_assert_uimm_bits!(IMM8, 8); _mm512_mask_reduce_ph::(_mm512_undefined_ph(), 0xffffffff, a) @@ -11036,7 +10965,7 @@ pub fn _mm512_reduce_ph(a: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_reduce_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { static_assert_uimm_bits!(IMM8, 8); _mm512_mask_reduce_round_ph::(src, k, a) @@ -11059,7 +10988,7 @@ pub fn _mm512_mask_reduce_ph(src: __m512h, k: __mmask32, a: __m #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_reduce_ph(k: __mmask32, a: __m512h) -> __m512h { static_assert_uimm_bits!(IMM8, 8); _mm512_mask_reduce_ph::(_mm512_setzero_ph(), k, a) @@ -11083,7 +11012,7 @@ pub fn _mm512_maskz_reduce_ph(k: __mmask32, a: __m512h) -> __m5 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(1, 2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_reduce_round_ph(a: __m512h) -> __m512h { static_assert_uimm_bits!(IMM8, 8); static_assert_sae!(SAE); @@ -11109,7 +11038,7 @@ pub fn _mm512_reduce_round_ph(a: __m512h) -> __ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_reduce_round_ph( src: __m512h, k: __mmask32, @@ -11141,7 +11070,7 @@ pub fn _mm512_mask_reduce_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_reduce_round_ph( k: __mmask32, a: __m512h, @@ -11168,7 +11097,7 @@ pub fn _mm512_maskz_reduce_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_reduce_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_reduce_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -11192,7 +11121,7 @@ pub fn _mm_reduce_sh(a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_reduce_sh( src: __m128h, k: __mmask8, @@ -11221,7 +11150,7 @@ pub fn _mm_mask_reduce_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_reduce_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_reduce_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -11246,7 +11175,7 @@ pub fn _mm_maskz_reduce_sh(k: __mmask8, a: __m128h, b: __m128h) #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_reduce_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); static_assert_sae!(SAE); @@ -11273,7 +11202,7 @@ pub fn _mm_reduce_round_sh(a: __m128h, b: __m12 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(4, 5)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_reduce_round_sh( src: __m128h, k: __mmask8, @@ -11307,7 +11236,7 @@ pub fn _mm_mask_reduce_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_reduce_round_sh( k: __mmask8, a: __m128h, @@ -11538,32 +11467,6 @@ pub fn _mm512_reduce_max_ph(a: __m512h) -> f16 { } } -macro_rules! fpclass_asm { // FIXME: use LLVM intrinsics - ($mask_type: ty, $reg: ident, $a: expr) => {{ - let dst: $mask_type; - asm!( - "vfpclassph {k}, {src}, {imm8}", - k = lateout(kreg) dst, - src = in($reg) $a, - imm8 = const IMM8, - options(pure, nomem, nostack) - ); - dst - }}; - ($mask_type: ty, $mask: expr, $reg: ident, $a: expr) => {{ - let dst: $mask_type; - asm!( - "vfpclassph {k} {{ {mask} }}, {src}, {imm8}", - k = lateout(kreg) dst, - mask = in(kreg) $mask, - src = in($reg) $a, - imm8 = const IMM8, - options(pure, nomem, nostack) - ); - dst - }}; -} - /// Test packed half-precision (16-bit) floating-point elements in a for special categories specified /// by imm8, and store the results in mask vector k. /// imm can be a combination of: @@ -11582,11 +11485,11 @@ macro_rules! fpclass_asm { // FIXME: use LLVM intrinsics #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fpclass_ph_mask(a: __m128h) -> __mmask8 { unsafe { static_assert_uimm_bits!(IMM8, 8); - fpclass_asm!(__mmask8, xmm_reg, a) + vfpclassph_128(a, IMM8) } } @@ -11609,12 +11512,9 @@ pub fn _mm_fpclass_ph_mask(a: __m128h) -> __mmask8 { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fpclass_ph_mask(k1: __mmask8, a: __m128h) -> __mmask8 { - unsafe { - static_assert_uimm_bits!(IMM8, 8); - fpclass_asm!(__mmask8, k1, xmm_reg, a) - } + _mm_fpclass_ph_mask::(a) & k1 } /// Test packed half-precision (16-bit) floating-point elements in a for special categories specified @@ -11635,11 +11535,11 @@ pub fn _mm_mask_fpclass_ph_mask(k1: __mmask8, a: __m128h) -> __ #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_fpclass_ph_mask(a: __m256h) -> __mmask16 { unsafe { static_assert_uimm_bits!(IMM8, 8); - fpclass_asm!(__mmask16, ymm_reg, a) + vfpclassph_256(a, IMM8) } } @@ -11662,12 +11562,9 @@ pub fn _mm256_fpclass_ph_mask(a: __m256h) -> __mmask16 { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_fpclass_ph_mask(k1: __mmask16, a: __m256h) -> __mmask16 { - unsafe { - static_assert_uimm_bits!(IMM8, 8); - fpclass_asm!(__mmask16, k1, ymm_reg, a) - } + _mm256_fpclass_ph_mask::(a) & k1 } /// Test packed half-precision (16-bit) floating-point elements in a for special categories specified @@ -11688,11 +11585,11 @@ pub fn _mm256_mask_fpclass_ph_mask(k1: __mmask16, a: __m256h) - #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fpclass_ph_mask(a: __m512h) -> __mmask32 { unsafe { static_assert_uimm_bits!(IMM8, 8); - fpclass_asm!(__mmask32, zmm_reg, a) + vfpclassph_512(a, IMM8) } } @@ -11715,12 +11612,9 @@ pub fn _mm512_fpclass_ph_mask(a: __m512h) -> __mmask32 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fpclass_ph_mask(k1: __mmask32, a: __m512h) -> __mmask32 { - unsafe { - static_assert_uimm_bits!(IMM8, 8); - fpclass_asm!(__mmask32, k1, zmm_reg, a) - } + _mm512_fpclass_ph_mask::(a) & k1 } /// Test the lower half-precision (16-bit) floating-point element in a for special categories specified @@ -11741,7 +11635,7 @@ pub fn _mm512_mask_fpclass_ph_mask(k1: __mmask32, a: __m512h) - #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfpclasssh, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fpclass_sh_mask(a: __m128h) -> __mmask8 { _mm_mask_fpclass_sh_mask::(0xff, a) } @@ -11765,7 +11659,7 @@ pub fn _mm_fpclass_sh_mask(a: __m128h) -> __mmask8 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfpclasssh, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fpclass_sh_mask(k1: __mmask8, a: __m128h) -> __mmask8 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -11779,7 +11673,7 @@ pub fn _mm_mask_fpclass_sh_mask(k1: __mmask8, a: __m128h) -> __ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_blend_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_blend_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, b, a) } @@ -11791,7 +11685,7 @@ pub const fn _mm_mask_blend_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_blend_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_blend_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, b, a) } @@ -11803,7 +11697,7 @@ pub const fn _mm256_mask_blend_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m25 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_blend_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_blend_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, b, a) } @@ -11815,7 +11709,7 @@ pub const fn _mm512_mask_blend_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m51 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_permutex2var_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_permutex2var_ph(a: __m128h, idx: __m128i, b: __m128h) -> __m128h { _mm_castsi128_ph(_mm_permutex2var_epi16( _mm_castph_si128(a), @@ -11830,7 +11724,7 @@ pub fn _mm_permutex2var_ph(a: __m128h, idx: __m128i, b: __m128h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permutex2var_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_permutex2var_ph(a: __m256h, idx: __m256i, b: __m256h) -> __m256h { _mm256_castsi256_ph(_mm256_permutex2var_epi16( _mm256_castph_si256(a), @@ -11845,7 +11739,7 @@ pub fn _mm256_permutex2var_ph(a: __m256h, idx: __m256i, b: __m256h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutex2var_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_permutex2var_ph(a: __m512h, idx: __m512i, b: __m512h) -> __m512h { _mm512_castsi512_ph(_mm512_permutex2var_epi16( _mm512_castph_si512(a), @@ -11860,7 +11754,7 @@ pub fn _mm512_permutex2var_ph(a: __m512h, idx: __m512i, b: __m512h) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_permutexvar_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_permutexvar_ph(idx: __m128i, a: __m128h) -> __m128h { _mm_castsi128_ph(_mm_permutexvar_epi16(idx, _mm_castph_si128(a))) } @@ -11871,7 +11765,7 @@ pub fn _mm_permutexvar_ph(idx: __m128i, a: __m128h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permutexvar_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_permutexvar_ph(idx: __m256i, a: __m256h) -> __m256h { _mm256_castsi256_ph(_mm256_permutexvar_epi16(idx, _mm256_castph_si256(a))) } @@ -11882,7 +11776,7 @@ pub fn _mm256_permutexvar_ph(idx: __m256i, a: __m256h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutexvar_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_permutexvar_ph(idx: __m512i, a: __m512h) -> __m512h { _mm512_castsi512_ph(_mm512_permutexvar_epi16(idx, _mm512_castph_si512(a))) } @@ -11894,7 +11788,7 @@ pub fn _mm512_permutexvar_ph(idx: __m512i, a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtepi16_ph(a: __m128i) -> __m128h { unsafe { vcvtw2ph_128(a.as_i16x8(), _MM_FROUND_CUR_DIRECTION) } } @@ -11907,7 +11801,7 @@ pub fn _mm_cvtepi16_ph(a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtepi16_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { unsafe { simd_select_bitmask(k, _mm_cvtepi16_ph(a), src) } } @@ -11919,7 +11813,7 @@ pub fn _mm_mask_cvtepi16_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtepi16_ph(k: __mmask8, a: __m128i) -> __m128h { _mm_mask_cvtepi16_ph(_mm_setzero_ph(), k, a) } @@ -11931,7 +11825,7 @@ pub fn _mm_maskz_cvtepi16_ph(k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtepi16_ph(a: __m256i) -> __m256h { unsafe { vcvtw2ph_256(a.as_i16x16(), _MM_FROUND_CUR_DIRECTION) } } @@ -11944,7 +11838,7 @@ pub fn _mm256_cvtepi16_ph(a: __m256i) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtepi16_ph(src: __m256h, k: __mmask16, a: __m256i) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_cvtepi16_ph(a), src) } } @@ -11956,7 +11850,7 @@ pub fn _mm256_mask_cvtepi16_ph(src: __m256h, k: __mmask16, a: __m256i) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtepi16_ph(k: __mmask16, a: __m256i) -> __m256h { _mm256_mask_cvtepi16_ph(_mm256_setzero_ph(), k, a) } @@ -11968,7 +11862,7 @@ pub fn _mm256_maskz_cvtepi16_ph(k: __mmask16, a: __m256i) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtepi16_ph(a: __m512i) -> __m512h { unsafe { vcvtw2ph_512(a.as_i16x32(), _MM_FROUND_CUR_DIRECTION) } } @@ -11981,7 +11875,7 @@ pub fn _mm512_cvtepi16_ph(a: __m512i) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtepi16_ph(src: __m512h, k: __mmask32, a: __m512i) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_cvtepi16_ph(a), src) } } @@ -11993,7 +11887,7 @@ pub fn _mm512_mask_cvtepi16_ph(src: __m512h, k: __mmask32, a: __m512i) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtepi16_ph(k: __mmask32, a: __m512i) -> __m512h { _mm512_mask_cvtepi16_ph(_mm512_setzero_ph(), k, a) } @@ -12014,7 +11908,7 @@ pub fn _mm512_maskz_cvtepi16_ph(k: __mmask32, a: __m512i) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtw2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundepi16_ph(a: __m512i) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -12039,7 +11933,7 @@ pub fn _mm512_cvt_roundepi16_ph(a: __m512i) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtw2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundepi16_ph( src: __m512h, k: __mmask32, @@ -12067,7 +11961,7 @@ pub fn _mm512_mask_cvt_roundepi16_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtw2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundepi16_ph(k: __mmask32, a: __m512i) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundepi16_ph::(_mm512_setzero_ph(), k, a) @@ -12080,7 +11974,7 @@ pub fn _mm512_maskz_cvt_roundepi16_ph(k: __mmask32, a: __m5 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtepu16_ph(a: __m128i) -> __m128h { unsafe { vcvtuw2ph_128(a.as_u16x8(), _MM_FROUND_CUR_DIRECTION) } } @@ -12093,7 +11987,7 @@ pub fn _mm_cvtepu16_ph(a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtepu16_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { unsafe { simd_select_bitmask(k, _mm_cvtepu16_ph(a), src) } } @@ -12105,7 +11999,7 @@ pub fn _mm_mask_cvtepu16_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtepu16_ph(k: __mmask8, a: __m128i) -> __m128h { _mm_mask_cvtepu16_ph(_mm_setzero_ph(), k, a) } @@ -12117,7 +12011,7 @@ pub fn _mm_maskz_cvtepu16_ph(k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtepu16_ph(a: __m256i) -> __m256h { unsafe { vcvtuw2ph_256(a.as_u16x16(), _MM_FROUND_CUR_DIRECTION) } } @@ -12130,7 +12024,7 @@ pub fn _mm256_cvtepu16_ph(a: __m256i) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtepu16_ph(src: __m256h, k: __mmask16, a: __m256i) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_cvtepu16_ph(a), src) } } @@ -12142,7 +12036,7 @@ pub fn _mm256_mask_cvtepu16_ph(src: __m256h, k: __mmask16, a: __m256i) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtepu16_ph(k: __mmask16, a: __m256i) -> __m256h { _mm256_mask_cvtepu16_ph(_mm256_setzero_ph(), k, a) } @@ -12154,7 +12048,7 @@ pub fn _mm256_maskz_cvtepu16_ph(k: __mmask16, a: __m256i) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtepu16_ph(a: __m512i) -> __m512h { unsafe { vcvtuw2ph_512(a.as_u16x32(), _MM_FROUND_CUR_DIRECTION) } } @@ -12167,7 +12061,7 @@ pub fn _mm512_cvtepu16_ph(a: __m512i) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtepu16_ph(src: __m512h, k: __mmask32, a: __m512i) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_cvtepu16_ph(a), src) } } @@ -12179,7 +12073,7 @@ pub fn _mm512_mask_cvtepu16_ph(src: __m512h, k: __mmask32, a: __m512i) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtepu16_ph(k: __mmask32, a: __m512i) -> __m512h { _mm512_mask_cvtepu16_ph(_mm512_setzero_ph(), k, a) } @@ -12200,7 +12094,7 @@ pub fn _mm512_maskz_cvtepu16_ph(k: __mmask32, a: __m512i) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuw2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundepu16_ph(a: __m512i) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -12225,7 +12119,7 @@ pub fn _mm512_cvt_roundepu16_ph(a: __m512i) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuw2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundepu16_ph( src: __m512h, k: __mmask32, @@ -12253,7 +12147,7 @@ pub fn _mm512_mask_cvt_roundepu16_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuw2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundepu16_ph(k: __mmask32, a: __m512i) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundepu16_ph::(_mm512_setzero_ph(), k, a) @@ -12266,7 +12160,7 @@ pub fn _mm512_maskz_cvt_roundepu16_ph(k: __mmask32, a: __m5 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtepi32_ph(a: __m128i) -> __m128h { _mm_mask_cvtepi32_ph(_mm_setzero_ph(), 0xff, a) } @@ -12279,7 +12173,7 @@ pub fn _mm_cvtepi32_ph(a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtepi32_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { unsafe { vcvtdq2ph_128(a.as_i32x4(), src, k) } } @@ -12292,7 +12186,7 @@ pub fn _mm_mask_cvtepi32_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtepi32_ph(k: __mmask8, a: __m128i) -> __m128h { _mm_mask_cvtepi32_ph(_mm_setzero_ph(), k, a) } @@ -12304,7 +12198,7 @@ pub fn _mm_maskz_cvtepi32_ph(k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtepi32_ph(a: __m256i) -> __m128h { unsafe { vcvtdq2ph_256(a.as_i32x8(), _MM_FROUND_CUR_DIRECTION) } } @@ -12317,7 +12211,7 @@ pub fn _mm256_cvtepi32_ph(a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtepi32_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h { unsafe { simd_select_bitmask(k, _mm256_cvtepi32_ph(a), src) } } @@ -12329,7 +12223,7 @@ pub fn _mm256_mask_cvtepi32_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtepi32_ph(k: __mmask8, a: __m256i) -> __m128h { _mm256_mask_cvtepi32_ph(_mm_setzero_ph(), k, a) } @@ -12341,7 +12235,7 @@ pub fn _mm256_maskz_cvtepi32_ph(k: __mmask8, a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtepi32_ph(a: __m512i) -> __m256h { unsafe { vcvtdq2ph_512(a.as_i32x16(), _MM_FROUND_CUR_DIRECTION) } } @@ -12354,7 +12248,7 @@ pub fn _mm512_cvtepi32_ph(a: __m512i) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtepi32_ph(src: __m256h, k: __mmask16, a: __m512i) -> __m256h { unsafe { simd_select_bitmask(k, _mm512_cvtepi32_ph(a), src) } } @@ -12366,7 +12260,7 @@ pub fn _mm512_mask_cvtepi32_ph(src: __m256h, k: __mmask16, a: __m512i) -> __m256 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtepi32_ph(k: __mmask16, a: __m512i) -> __m256h { _mm512_mask_cvtepi32_ph(f16x16::ZERO.as_m256h(), k, a) } @@ -12387,7 +12281,7 @@ pub fn _mm512_maskz_cvtepi32_ph(k: __mmask16, a: __m512i) -> __m256h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtdq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundepi32_ph(a: __m512i) -> __m256h { unsafe { static_assert_rounding!(ROUNDING); @@ -12412,7 +12306,7 @@ pub fn _mm512_cvt_roundepi32_ph(a: __m512i) -> __m256h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtdq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundepi32_ph( src: __m256h, k: __mmask16, @@ -12440,7 +12334,7 @@ pub fn _mm512_mask_cvt_roundepi32_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtdq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundepi32_ph(k: __mmask16, a: __m512i) -> __m256h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundepi32_ph::(f16x16::ZERO.as_m256h(), k, a) @@ -12454,7 +12348,7 @@ pub fn _mm512_maskz_cvt_roundepi32_ph(k: __mmask16, a: __m5 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsi2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvti32_sh(a: __m128h, b: i32) -> __m128h { unsafe { vcvtsi2sh(a, b, _MM_FROUND_CUR_DIRECTION) } } @@ -12476,7 +12370,7 @@ pub fn _mm_cvti32_sh(a: __m128h, b: i32) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsi2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundi32_sh(a: __m128h, b: i32) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -12491,7 +12385,7 @@ pub fn _mm_cvt_roundi32_sh(a: __m128h, b: i32) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtepu32_ph(a: __m128i) -> __m128h { _mm_mask_cvtepu32_ph(_mm_setzero_ph(), 0xff, a) } @@ -12504,7 +12398,7 @@ pub fn _mm_cvtepu32_ph(a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtepu32_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { unsafe { vcvtudq2ph_128(a.as_u32x4(), src, k) } } @@ -12517,7 +12411,7 @@ pub fn _mm_mask_cvtepu32_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtepu32_ph(k: __mmask8, a: __m128i) -> __m128h { _mm_mask_cvtepu32_ph(_mm_setzero_ph(), k, a) } @@ -12529,7 +12423,7 @@ pub fn _mm_maskz_cvtepu32_ph(k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtepu32_ph(a: __m256i) -> __m128h { unsafe { vcvtudq2ph_256(a.as_u32x8(), _MM_FROUND_CUR_DIRECTION) } } @@ -12542,7 +12436,7 @@ pub fn _mm256_cvtepu32_ph(a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtepu32_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h { unsafe { simd_select_bitmask(k, _mm256_cvtepu32_ph(a), src) } } @@ -12554,7 +12448,7 @@ pub fn _mm256_mask_cvtepu32_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtepu32_ph(k: __mmask8, a: __m256i) -> __m128h { _mm256_mask_cvtepu32_ph(_mm_setzero_ph(), k, a) } @@ -12566,7 +12460,7 @@ pub fn _mm256_maskz_cvtepu32_ph(k: __mmask8, a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtepu32_ph(a: __m512i) -> __m256h { unsafe { vcvtudq2ph_512(a.as_u32x16(), _MM_FROUND_CUR_DIRECTION) } } @@ -12579,7 +12473,7 @@ pub fn _mm512_cvtepu32_ph(a: __m512i) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtepu32_ph(src: __m256h, k: __mmask16, a: __m512i) -> __m256h { unsafe { simd_select_bitmask(k, _mm512_cvtepu32_ph(a), src) } } @@ -12591,7 +12485,7 @@ pub fn _mm512_mask_cvtepu32_ph(src: __m256h, k: __mmask16, a: __m512i) -> __m256 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtepu32_ph(k: __mmask16, a: __m512i) -> __m256h { _mm512_mask_cvtepu32_ph(f16x16::ZERO.as_m256h(), k, a) } @@ -12612,7 +12506,7 @@ pub fn _mm512_maskz_cvtepu32_ph(k: __mmask16, a: __m512i) -> __m256h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtudq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundepu32_ph(a: __m512i) -> __m256h { unsafe { static_assert_rounding!(ROUNDING); @@ -12637,7 +12531,7 @@ pub fn _mm512_cvt_roundepu32_ph(a: __m512i) -> __m256h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtudq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundepu32_ph( src: __m256h, k: __mmask16, @@ -12665,7 +12559,7 @@ pub fn _mm512_mask_cvt_roundepu32_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtudq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundepu32_ph(k: __mmask16, a: __m512i) -> __m256h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundepu32_ph::(f16x16::ZERO.as_m256h(), k, a) @@ -12679,7 +12573,7 @@ pub fn _mm512_maskz_cvt_roundepu32_ph(k: __mmask16, a: __m5 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtusi2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtu32_sh(a: __m128h, b: u32) -> __m128h { unsafe { vcvtusi2sh(a, b, _MM_FROUND_CUR_DIRECTION) } } @@ -12701,7 +12595,7 @@ pub fn _mm_cvtu32_sh(a: __m128h, b: u32) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtusi2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundu32_sh(a: __m128h, b: u32) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -12716,7 +12610,7 @@ pub fn _mm_cvt_roundu32_sh(a: __m128h, b: u32) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtepi64_ph(a: __m128i) -> __m128h { _mm_mask_cvtepi64_ph(_mm_setzero_ph(), 0xff, a) } @@ -12729,7 +12623,7 @@ pub fn _mm_cvtepi64_ph(a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { unsafe { vcvtqq2ph_128(a.as_i64x2(), src, k) } } @@ -12742,7 +12636,7 @@ pub fn _mm_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtepi64_ph(k: __mmask8, a: __m128i) -> __m128h { _mm_mask_cvtepi64_ph(_mm_setzero_ph(), k, a) } @@ -12754,7 +12648,7 @@ pub fn _mm_maskz_cvtepi64_ph(k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtepi64_ph(a: __m256i) -> __m128h { _mm256_mask_cvtepi64_ph(_mm_setzero_ph(), 0xff, a) } @@ -12767,7 +12661,7 @@ pub fn _mm256_cvtepi64_ph(a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h { unsafe { vcvtqq2ph_256(a.as_i64x4(), src, k) } } @@ -12780,7 +12674,7 @@ pub fn _mm256_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtepi64_ph(k: __mmask8, a: __m256i) -> __m128h { _mm256_mask_cvtepi64_ph(_mm_setzero_ph(), k, a) } @@ -12792,7 +12686,7 @@ pub fn _mm256_maskz_cvtepi64_ph(k: __mmask8, a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtepi64_ph(a: __m512i) -> __m128h { unsafe { vcvtqq2ph_512(a.as_i64x8(), _MM_FROUND_CUR_DIRECTION) } } @@ -12805,7 +12699,7 @@ pub fn _mm512_cvtepi64_ph(a: __m512i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m512i) -> __m128h { unsafe { simd_select_bitmask(k, _mm512_cvtepi64_ph(a), src) } } @@ -12817,7 +12711,7 @@ pub fn _mm512_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m512i) -> __m128h #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtepi64_ph(k: __mmask8, a: __m512i) -> __m128h { _mm512_mask_cvtepi64_ph(f16x8::ZERO.as_m128h(), k, a) } @@ -12838,7 +12732,7 @@ pub fn _mm512_maskz_cvtepi64_ph(k: __mmask8, a: __m512i) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtqq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundepi64_ph(a: __m512i) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -12863,7 +12757,7 @@ pub fn _mm512_cvt_roundepi64_ph(a: __m512i) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtqq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundepi64_ph( src: __m128h, k: __mmask8, @@ -12891,7 +12785,7 @@ pub fn _mm512_mask_cvt_roundepi64_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtqq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundepi64_ph(k: __mmask8, a: __m512i) -> __m128h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundepi64_ph::(f16x8::ZERO.as_m128h(), k, a) @@ -12904,7 +12798,7 @@ pub fn _mm512_maskz_cvt_roundepi64_ph(k: __mmask8, a: __m51 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtepu64_ph(a: __m128i) -> __m128h { _mm_mask_cvtepu64_ph(_mm_setzero_ph(), 0xff, a) } @@ -12917,7 +12811,7 @@ pub fn _mm_cvtepu64_ph(a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { unsafe { vcvtuqq2ph_128(a.as_u64x2(), src, k) } } @@ -12930,7 +12824,7 @@ pub fn _mm_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtepu64_ph(k: __mmask8, a: __m128i) -> __m128h { _mm_mask_cvtepu64_ph(_mm_setzero_ph(), k, a) } @@ -12942,7 +12836,7 @@ pub fn _mm_maskz_cvtepu64_ph(k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtepu64_ph(a: __m256i) -> __m128h { _mm256_mask_cvtepu64_ph(_mm_setzero_ph(), 0xff, a) } @@ -12955,7 +12849,7 @@ pub fn _mm256_cvtepu64_ph(a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h { unsafe { vcvtuqq2ph_256(a.as_u64x4(), src, k) } } @@ -12968,7 +12862,7 @@ pub fn _mm256_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtepu64_ph(k: __mmask8, a: __m256i) -> __m128h { _mm256_mask_cvtepu64_ph(_mm_setzero_ph(), k, a) } @@ -12980,7 +12874,7 @@ pub fn _mm256_maskz_cvtepu64_ph(k: __mmask8, a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtepu64_ph(a: __m512i) -> __m128h { unsafe { vcvtuqq2ph_512(a.as_u64x8(), _MM_FROUND_CUR_DIRECTION) } } @@ -12993,7 +12887,7 @@ pub fn _mm512_cvtepu64_ph(a: __m512i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m512i) -> __m128h { unsafe { simd_select_bitmask(k, _mm512_cvtepu64_ph(a), src) } } @@ -13005,7 +12899,7 @@ pub fn _mm512_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m512i) -> __m128h #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtepu64_ph(k: __mmask8, a: __m512i) -> __m128h { _mm512_mask_cvtepu64_ph(f16x8::ZERO.as_m128h(), k, a) } @@ -13026,7 +12920,7 @@ pub fn _mm512_maskz_cvtepu64_ph(k: __mmask8, a: __m512i) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuqq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundepu64_ph(a: __m512i) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -13051,7 +12945,7 @@ pub fn _mm512_cvt_roundepu64_ph(a: __m512i) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuqq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundepu64_ph( src: __m128h, k: __mmask8, @@ -13079,7 +12973,7 @@ pub fn _mm512_mask_cvt_roundepu64_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuqq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundepu64_ph(k: __mmask8, a: __m512i) -> __m128h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundepu64_ph::(f16x8::ZERO.as_m128h(), k, a) @@ -13092,7 +12986,7 @@ pub fn _mm512_maskz_cvt_roundepu64_ph(k: __mmask8, a: __m51 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtxps_ph(a: __m128) -> __m128h { _mm_mask_cvtxps_ph(_mm_setzero_ph(), 0xff, a) } @@ -13105,7 +12999,7 @@ pub fn _mm_cvtxps_ph(a: __m128) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtxps_ph(src: __m128h, k: __mmask8, a: __m128) -> __m128h { unsafe { vcvtps2phx_128(a, src, k) } } @@ -13118,7 +13012,7 @@ pub fn _mm_mask_cvtxps_ph(src: __m128h, k: __mmask8, a: __m128) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtxps_ph(k: __mmask8, a: __m128) -> __m128h { _mm_mask_cvtxps_ph(_mm_setzero_ph(), k, a) } @@ -13130,7 +13024,7 @@ pub fn _mm_maskz_cvtxps_ph(k: __mmask8, a: __m128) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtxps_ph(a: __m256) -> __m128h { _mm256_mask_cvtxps_ph(_mm_setzero_ph(), 0xff, a) } @@ -13143,7 +13037,7 @@ pub fn _mm256_cvtxps_ph(a: __m256) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtxps_ph(src: __m128h, k: __mmask8, a: __m256) -> __m128h { unsafe { vcvtps2phx_256(a, src, k) } } @@ -13156,7 +13050,7 @@ pub fn _mm256_mask_cvtxps_ph(src: __m128h, k: __mmask8, a: __m256) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtxps_ph(k: __mmask8, a: __m256) -> __m128h { _mm256_mask_cvtxps_ph(_mm_setzero_ph(), k, a) } @@ -13168,7 +13062,7 @@ pub fn _mm256_maskz_cvtxps_ph(k: __mmask8, a: __m256) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtxps_ph(a: __m512) -> __m256h { _mm512_mask_cvtxps_ph(f16x16::ZERO.as_m256h(), 0xffff, a) } @@ -13181,7 +13075,7 @@ pub fn _mm512_cvtxps_ph(a: __m512) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtxps_ph(src: __m256h, k: __mmask16, a: __m512) -> __m256h { unsafe { vcvtps2phx_512(a, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -13194,7 +13088,7 @@ pub fn _mm512_mask_cvtxps_ph(src: __m256h, k: __mmask16, a: __m512) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtxps_ph(k: __mmask16, a: __m512) -> __m256h { _mm512_mask_cvtxps_ph(f16x16::ZERO.as_m256h(), k, a) } @@ -13215,7 +13109,7 @@ pub fn _mm512_maskz_cvtxps_ph(k: __mmask16, a: __m512) -> __m256h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtps2phx, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtx_roundps_ph(a: __m512) -> __m256h { static_assert_rounding!(ROUNDING); _mm512_mask_cvtx_roundps_ph::(f16x16::ZERO.as_m256h(), 0xffff, a) @@ -13238,7 +13132,7 @@ pub fn _mm512_cvtx_roundps_ph(a: __m512) -> __m256h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtps2phx, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtx_roundps_ph( src: __m256h, k: __mmask16, @@ -13267,7 +13161,7 @@ pub fn _mm512_mask_cvtx_roundps_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtps2phx, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtx_roundps_ph(k: __mmask16, a: __m512) -> __m256h { static_assert_rounding!(ROUNDING); _mm512_mask_cvtx_roundps_ph::(f16x16::ZERO.as_m256h(), k, a) @@ -13281,7 +13175,7 @@ pub fn _mm512_maskz_cvtx_roundps_ph(k: __mmask16, a: __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtss2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtss_sh(a: __m128h, b: __m128) -> __m128h { _mm_mask_cvtss_sh(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -13295,7 +13189,7 @@ pub fn _mm_cvtss_sh(a: __m128h, b: __m128) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtss2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtss_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128) -> __m128h { unsafe { vcvtss2sh(a, b, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -13309,7 +13203,7 @@ pub fn _mm_mask_cvtss_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128) -> __ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtss2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtss_sh(k: __mmask8, a: __m128h, b: __m128) -> __m128h { _mm_mask_cvtss_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -13331,7 +13225,7 @@ pub fn _mm_maskz_cvtss_sh(k: __mmask8, a: __m128h, b: __m128) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtss2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundss_sh(a: __m128h, b: __m128) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_cvt_roundss_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -13355,7 +13249,7 @@ pub fn _mm_cvt_roundss_sh(a: __m128h, b: __m128) -> __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtss2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvt_roundss_sh( src: __m128h, k: __mmask8, @@ -13386,7 +13280,7 @@ pub fn _mm_mask_cvt_roundss_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtss2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvt_roundss_sh( k: __mmask8, a: __m128h, @@ -13403,7 +13297,7 @@ pub fn _mm_maskz_cvt_roundss_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtpd_ph(a: __m128d) -> __m128h { _mm_mask_cvtpd_ph(_mm_setzero_ph(), 0xff, a) } @@ -13416,7 +13310,7 @@ pub fn _mm_cvtpd_ph(a: __m128d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m128d) -> __m128h { unsafe { vcvtpd2ph_128(a, src, k) } } @@ -13429,7 +13323,7 @@ pub fn _mm_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m128d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtpd_ph(k: __mmask8, a: __m128d) -> __m128h { _mm_mask_cvtpd_ph(_mm_setzero_ph(), k, a) } @@ -13441,7 +13335,7 @@ pub fn _mm_maskz_cvtpd_ph(k: __mmask8, a: __m128d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtpd_ph(a: __m256d) -> __m128h { _mm256_mask_cvtpd_ph(_mm_setzero_ph(), 0xff, a) } @@ -13454,7 +13348,7 @@ pub fn _mm256_cvtpd_ph(a: __m256d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m256d) -> __m128h { unsafe { vcvtpd2ph_256(a, src, k) } } @@ -13467,7 +13361,7 @@ pub fn _mm256_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m256d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtpd_ph(k: __mmask8, a: __m256d) -> __m128h { _mm256_mask_cvtpd_ph(_mm_setzero_ph(), k, a) } @@ -13479,7 +13373,7 @@ pub fn _mm256_maskz_cvtpd_ph(k: __mmask8, a: __m256d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtpd_ph(a: __m512d) -> __m128h { _mm512_mask_cvtpd_ph(f16x8::ZERO.as_m128h(), 0xff, a) } @@ -13492,7 +13386,7 @@ pub fn _mm512_cvtpd_ph(a: __m512d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m512d) -> __m128h { unsafe { vcvtpd2ph_512(a, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -13505,7 +13399,7 @@ pub fn _mm512_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m512d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtpd_ph(k: __mmask8, a: __m512d) -> __m128h { _mm512_mask_cvtpd_ph(f16x8::ZERO.as_m128h(), k, a) } @@ -13526,7 +13420,7 @@ pub fn _mm512_maskz_cvtpd_ph(k: __mmask8, a: __m512d) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtpd2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundpd_ph(a: __m512d) -> __m128h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundpd_ph::(f16x8::ZERO.as_m128h(), 0xff, a) @@ -13549,7 +13443,7 @@ pub fn _mm512_cvt_roundpd_ph(a: __m512d) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtpd2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundpd_ph( src: __m128h, k: __mmask8, @@ -13578,7 +13472,7 @@ pub fn _mm512_mask_cvt_roundpd_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtpd2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundpd_ph(k: __mmask8, a: __m512d) -> __m128h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundpd_ph::(f16x8::ZERO.as_m128h(), k, a) @@ -13592,7 +13486,7 @@ pub fn _mm512_maskz_cvt_roundpd_ph(k: __mmask8, a: __m512d) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsd2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtsd_sh(a: __m128h, b: __m128d) -> __m128h { _mm_mask_cvtsd_sh(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -13606,7 +13500,7 @@ pub fn _mm_cvtsd_sh(a: __m128h, b: __m128d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsd2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtsd_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128d) -> __m128h { unsafe { vcvtsd2sh(a, b, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -13620,7 +13514,7 @@ pub fn _mm_mask_cvtsd_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128d) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsd2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtsd_sh(k: __mmask8, a: __m128h, b: __m128d) -> __m128h { _mm_mask_cvtsd_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -13642,7 +13536,7 @@ pub fn _mm_maskz_cvtsd_sh(k: __mmask8, a: __m128h, b: __m128d) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsd2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundsd_sh(a: __m128h, b: __m128d) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_cvt_roundsd_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -13666,7 +13560,7 @@ pub fn _mm_cvt_roundsd_sh(a: __m128h, b: __m128d) -> __m128 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsd2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvt_roundsd_sh( src: __m128h, k: __mmask8, @@ -13697,7 +13591,7 @@ pub fn _mm_mask_cvt_roundsd_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsd2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvt_roundsd_sh( k: __mmask8, a: __m128h, @@ -13714,7 +13608,7 @@ pub fn _mm_maskz_cvt_roundsd_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtph_epi16(a: __m128h) -> __m128i { _mm_mask_cvtph_epi16(_mm_undefined_si128(), 0xff, a) } @@ -13727,7 +13621,7 @@ pub fn _mm_cvtph_epi16(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtph_epi16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvtph2w_128(a, src.as_i16x8(), k)) } } @@ -13739,7 +13633,7 @@ pub fn _mm_mask_cvtph_epi16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtph_epi16(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvtph_epi16(_mm_setzero_si128(), k, a) } @@ -13751,7 +13645,7 @@ pub fn _mm_maskz_cvtph_epi16(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtph_epi16(a: __m256h) -> __m256i { _mm256_mask_cvtph_epi16(_mm256_undefined_si256(), 0xffff, a) } @@ -13764,7 +13658,7 @@ pub fn _mm256_cvtph_epi16(a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtph_epi16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i { unsafe { transmute(vcvtph2w_256(a, src.as_i16x16(), k)) } } @@ -13776,7 +13670,7 @@ pub fn _mm256_mask_cvtph_epi16(src: __m256i, k: __mmask16, a: __m256h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtph_epi16(k: __mmask16, a: __m256h) -> __m256i { _mm256_mask_cvtph_epi16(_mm256_setzero_si256(), k, a) } @@ -13788,7 +13682,7 @@ pub fn _mm256_maskz_cvtph_epi16(k: __mmask16, a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtph_epi16(a: __m512h) -> __m512i { _mm512_mask_cvtph_epi16(_mm512_undefined_epi32(), 0xffffffff, a) } @@ -13801,7 +13695,7 @@ pub fn _mm512_cvtph_epi16(a: __m512h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtph_epi16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i { unsafe { transmute(vcvtph2w_512( @@ -13820,7 +13714,7 @@ pub fn _mm512_mask_cvtph_epi16(src: __m512i, k: __mmask32, a: __m512h) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtph_epi16(k: __mmask32, a: __m512h) -> __m512i { _mm512_mask_cvtph_epi16(_mm512_setzero_si512(), k, a) } @@ -13841,7 +13735,7 @@ pub fn _mm512_maskz_cvtph_epi16(k: __mmask32, a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2w, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundph_epi16(a: __m512h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epi16::(_mm512_undefined_epi32(), 0xffffffff, a) @@ -13864,7 +13758,7 @@ pub fn _mm512_cvt_roundph_epi16(a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2w, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundph_epi16( src: __m512i, k: __mmask32, @@ -13892,7 +13786,7 @@ pub fn _mm512_mask_cvt_roundph_epi16( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2w, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundph_epi16(k: __mmask32, a: __m512h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epi16::(_mm512_setzero_si512(), k, a) @@ -13905,7 +13799,7 @@ pub fn _mm512_maskz_cvt_roundph_epi16(k: __mmask32, a: __m5 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtph_epu16(a: __m128h) -> __m128i { _mm_mask_cvtph_epu16(_mm_undefined_si128(), 0xff, a) } @@ -13918,7 +13812,7 @@ pub fn _mm_cvtph_epu16(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtph_epu16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvtph2uw_128(a, src.as_u16x8(), k)) } } @@ -13930,7 +13824,7 @@ pub fn _mm_mask_cvtph_epu16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtph_epu16(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvtph_epu16(_mm_setzero_si128(), k, a) } @@ -13942,7 +13836,7 @@ pub fn _mm_maskz_cvtph_epu16(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtph_epu16(a: __m256h) -> __m256i { _mm256_mask_cvtph_epu16(_mm256_undefined_si256(), 0xffff, a) } @@ -13955,7 +13849,7 @@ pub fn _mm256_cvtph_epu16(a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtph_epu16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i { unsafe { transmute(vcvtph2uw_256(a, src.as_u16x16(), k)) } } @@ -13967,7 +13861,7 @@ pub fn _mm256_mask_cvtph_epu16(src: __m256i, k: __mmask16, a: __m256h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtph_epu16(k: __mmask16, a: __m256h) -> __m256i { _mm256_mask_cvtph_epu16(_mm256_setzero_si256(), k, a) } @@ -13979,7 +13873,7 @@ pub fn _mm256_maskz_cvtph_epu16(k: __mmask16, a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtph_epu16(a: __m512h) -> __m512i { _mm512_mask_cvtph_epu16(_mm512_undefined_epi32(), 0xffffffff, a) } @@ -13992,7 +13886,7 @@ pub fn _mm512_cvtph_epu16(a: __m512h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtph_epu16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i { unsafe { transmute(vcvtph2uw_512( @@ -14011,7 +13905,7 @@ pub fn _mm512_mask_cvtph_epu16(src: __m512i, k: __mmask32, a: __m512h) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtph_epu16(k: __mmask32, a: __m512h) -> __m512i { _mm512_mask_cvtph_epu16(_mm512_setzero_si512(), k, a) } @@ -14026,7 +13920,7 @@ pub fn _mm512_maskz_cvtph_epu16(k: __mmask32, a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uw, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundph_epu16(a: __m512h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvt_roundph_epu16::(_mm512_undefined_epi32(), 0xffffffff, a) @@ -14043,7 +13937,7 @@ pub fn _mm512_cvt_roundph_epu16(a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uw, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundph_epu16( src: __m512i, k: __mmask32, @@ -14065,7 +13959,7 @@ pub fn _mm512_mask_cvt_roundph_epu16( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uw, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundph_epu16(k: __mmask32, a: __m512h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvt_roundph_epu16::(_mm512_setzero_si512(), k, a) @@ -14078,7 +13972,7 @@ pub fn _mm512_maskz_cvt_roundph_epu16(k: __mmask32, a: __m512h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttph_epi16(a: __m128h) -> __m128i { _mm_mask_cvttph_epi16(_mm_undefined_si128(), 0xff, a) } @@ -14091,7 +13985,7 @@ pub fn _mm_cvttph_epi16(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvttph_epi16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvttph2w_128(a, src.as_i16x8(), k)) } } @@ -14104,7 +13998,7 @@ pub fn _mm_mask_cvttph_epi16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvttph_epi16(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvttph_epi16(_mm_setzero_si128(), k, a) } @@ -14116,7 +14010,7 @@ pub fn _mm_maskz_cvttph_epi16(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvttph_epi16(a: __m256h) -> __m256i { _mm256_mask_cvttph_epi16(_mm256_undefined_si256(), 0xffff, a) } @@ -14129,7 +14023,7 @@ pub fn _mm256_cvttph_epi16(a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvttph_epi16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i { unsafe { transmute(vcvttph2w_256(a, src.as_i16x16(), k)) } } @@ -14142,7 +14036,7 @@ pub fn _mm256_mask_cvttph_epi16(src: __m256i, k: __mmask16, a: __m256h) -> __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvttph_epi16(k: __mmask16, a: __m256h) -> __m256i { _mm256_mask_cvttph_epi16(_mm256_setzero_si256(), k, a) } @@ -14154,7 +14048,7 @@ pub fn _mm256_maskz_cvttph_epi16(k: __mmask16, a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvttph_epi16(a: __m512h) -> __m512i { _mm512_mask_cvttph_epi16(_mm512_undefined_epi32(), 0xffffffff, a) } @@ -14167,7 +14061,7 @@ pub fn _mm512_cvttph_epi16(a: __m512h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvttph_epi16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i { unsafe { transmute(vcvttph2w_512( @@ -14187,7 +14081,7 @@ pub fn _mm512_mask_cvttph_epi16(src: __m512i, k: __mmask32, a: __m512h) -> __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvttph_epi16(k: __mmask32, a: __m512h) -> __m512i { _mm512_mask_cvttph_epi16(_mm512_setzero_si512(), k, a) } @@ -14202,7 +14096,7 @@ pub fn _mm512_maskz_cvttph_epi16(k: __mmask32, a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2w, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtt_roundph_epi16(a: __m512h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epi16::(_mm512_undefined_epi32(), 0xffffffff, a) @@ -14219,7 +14113,7 @@ pub fn _mm512_cvtt_roundph_epi16(a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2w, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtt_roundph_epi16( src: __m512i, k: __mmask32, @@ -14242,7 +14136,7 @@ pub fn _mm512_mask_cvtt_roundph_epi16( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2w, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtt_roundph_epi16(k: __mmask32, a: __m512h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epi16::(_mm512_setzero_si512(), k, a) @@ -14255,7 +14149,7 @@ pub fn _mm512_maskz_cvtt_roundph_epi16(k: __mmask32, a: __m512h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttph_epu16(a: __m128h) -> __m128i { _mm_mask_cvttph_epu16(_mm_undefined_si128(), 0xff, a) } @@ -14268,7 +14162,7 @@ pub fn _mm_cvttph_epu16(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvttph_epu16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvttph2uw_128(a, src.as_u16x8(), k)) } } @@ -14281,7 +14175,7 @@ pub fn _mm_mask_cvttph_epu16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvttph_epu16(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvttph_epu16(_mm_setzero_si128(), k, a) } @@ -14293,7 +14187,7 @@ pub fn _mm_maskz_cvttph_epu16(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvttph_epu16(a: __m256h) -> __m256i { _mm256_mask_cvttph_epu16(_mm256_undefined_si256(), 0xffff, a) } @@ -14306,7 +14200,7 @@ pub fn _mm256_cvttph_epu16(a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvttph_epu16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i { unsafe { transmute(vcvttph2uw_256(a, src.as_u16x16(), k)) } } @@ -14319,7 +14213,7 @@ pub fn _mm256_mask_cvttph_epu16(src: __m256i, k: __mmask16, a: __m256h) -> __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvttph_epu16(k: __mmask16, a: __m256h) -> __m256i { _mm256_mask_cvttph_epu16(_mm256_setzero_si256(), k, a) } @@ -14331,7 +14225,7 @@ pub fn _mm256_maskz_cvttph_epu16(k: __mmask16, a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvttph_epu16(a: __m512h) -> __m512i { _mm512_mask_cvttph_epu16(_mm512_undefined_epi32(), 0xffffffff, a) } @@ -14344,7 +14238,7 @@ pub fn _mm512_cvttph_epu16(a: __m512h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvttph_epu16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i { unsafe { transmute(vcvttph2uw_512( @@ -14364,7 +14258,7 @@ pub fn _mm512_mask_cvttph_epu16(src: __m512i, k: __mmask32, a: __m512h) -> __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvttph_epu16(k: __mmask32, a: __m512h) -> __m512i { _mm512_mask_cvttph_epu16(_mm512_setzero_si512(), k, a) } @@ -14379,7 +14273,7 @@ pub fn _mm512_maskz_cvttph_epu16(k: __mmask32, a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uw, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtt_roundph_epu16(a: __m512h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epu16::(_mm512_undefined_epi32(), 0xffffffff, a) @@ -14396,7 +14290,7 @@ pub fn _mm512_cvtt_roundph_epu16(a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uw, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtt_roundph_epu16( src: __m512i, k: __mmask32, @@ -14419,7 +14313,7 @@ pub fn _mm512_mask_cvtt_roundph_epu16( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uw, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtt_roundph_epu16(k: __mmask32, a: __m512h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epu16::(_mm512_setzero_si512(), k, a) @@ -14432,7 +14326,7 @@ pub fn _mm512_maskz_cvtt_roundph_epu16(k: __mmask32, a: __m512h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtph_epi32(a: __m128h) -> __m128i { _mm_mask_cvtph_epi32(_mm_undefined_si128(), 0xff, a) } @@ -14444,7 +14338,7 @@ pub fn _mm_cvtph_epi32(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtph_epi32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvtph2dq_128(a, src.as_i32x4(), k)) } } @@ -14456,7 +14350,7 @@ pub fn _mm_mask_cvtph_epi32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtph_epi32(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvtph_epi32(_mm_setzero_si128(), k, a) } @@ -14468,7 +14362,7 @@ pub fn _mm_maskz_cvtph_epi32(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtph_epi32(a: __m128h) -> __m256i { _mm256_mask_cvtph_epi32(_mm256_undefined_si256(), 0xff, a) } @@ -14480,7 +14374,7 @@ pub fn _mm256_cvtph_epi32(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtph_epi32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvtph2dq_256(a, src.as_i32x8(), k)) } } @@ -14492,7 +14386,7 @@ pub fn _mm256_mask_cvtph_epi32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtph_epi32(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvtph_epi32(_mm256_setzero_si256(), k, a) } @@ -14504,7 +14398,7 @@ pub fn _mm256_maskz_cvtph_epi32(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtph_epi32(a: __m256h) -> __m512i { _mm512_mask_cvtph_epi32(_mm512_undefined_epi32(), 0xffff, a) } @@ -14516,7 +14410,7 @@ pub fn _mm512_cvtph_epi32(a: __m256h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtph_epi32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i { unsafe { transmute(vcvtph2dq_512( @@ -14535,7 +14429,7 @@ pub fn _mm512_mask_cvtph_epi32(src: __m512i, k: __mmask16, a: __m256h) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtph_epi32(k: __mmask16, a: __m256h) -> __m512i { _mm512_mask_cvtph_epi32(_mm512_setzero_si512(), k, a) } @@ -14556,7 +14450,7 @@ pub fn _mm512_maskz_cvtph_epi32(k: __mmask16, a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2dq, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundph_epi32(a: __m256h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epi32::(_mm512_undefined_epi32(), 0xffff, a) @@ -14578,7 +14472,7 @@ pub fn _mm512_cvt_roundph_epi32(a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2dq, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundph_epi32( src: __m512i, k: __mmask16, @@ -14606,7 +14500,7 @@ pub fn _mm512_mask_cvt_roundph_epi32( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2dq, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundph_epi32(k: __mmask16, a: __m256h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epi32::(_mm512_setzero_si512(), k, a) @@ -14619,7 +14513,7 @@ pub fn _mm512_maskz_cvt_roundph_epi32(k: __mmask16, a: __m2 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2si))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtsh_i32(a: __m128h) -> i32 { unsafe { vcvtsh2si32(a, _MM_FROUND_CUR_DIRECTION) } } @@ -14640,7 +14534,7 @@ pub fn _mm_cvtsh_i32(a: __m128h) -> i32 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2si, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundsh_i32(a: __m128h) -> i32 { unsafe { static_assert_rounding!(ROUNDING); @@ -14655,7 +14549,7 @@ pub fn _mm_cvt_roundsh_i32(a: __m128h) -> i32 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtph_epu32(a: __m128h) -> __m128i { _mm_mask_cvtph_epu32(_mm_undefined_si128(), 0xff, a) } @@ -14667,7 +14561,7 @@ pub fn _mm_cvtph_epu32(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtph_epu32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvtph2udq_128(a, src.as_u32x4(), k)) } } @@ -14679,7 +14573,7 @@ pub fn _mm_mask_cvtph_epu32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtph_epu32(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvtph_epu32(_mm_setzero_si128(), k, a) } @@ -14691,7 +14585,7 @@ pub fn _mm_maskz_cvtph_epu32(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtph_epu32(a: __m128h) -> __m256i { _mm256_mask_cvtph_epu32(_mm256_undefined_si256(), 0xff, a) } @@ -14703,7 +14597,7 @@ pub fn _mm256_cvtph_epu32(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtph_epu32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvtph2udq_256(a, src.as_u32x8(), k)) } } @@ -14715,7 +14609,7 @@ pub fn _mm256_mask_cvtph_epu32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtph_epu32(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvtph_epu32(_mm256_setzero_si256(), k, a) } @@ -14727,7 +14621,7 @@ pub fn _mm256_maskz_cvtph_epu32(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtph_epu32(a: __m256h) -> __m512i { _mm512_mask_cvtph_epu32(_mm512_undefined_epi32(), 0xffff, a) } @@ -14739,7 +14633,7 @@ pub fn _mm512_cvtph_epu32(a: __m256h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtph_epu32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i { unsafe { transmute(vcvtph2udq_512( @@ -14758,7 +14652,7 @@ pub fn _mm512_mask_cvtph_epu32(src: __m512i, k: __mmask16, a: __m256h) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtph_epu32(k: __mmask16, a: __m256h) -> __m512i { _mm512_mask_cvtph_epu32(_mm512_setzero_si512(), k, a) } @@ -14779,7 +14673,7 @@ pub fn _mm512_maskz_cvtph_epu32(k: __mmask16, a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2udq, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundph_epu32(a: __m256h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epu32::(_mm512_undefined_epi32(), 0xffff, a) @@ -14801,7 +14695,7 @@ pub fn _mm512_cvt_roundph_epu32(a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2udq, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundph_epu32( src: __m512i, k: __mmask16, @@ -14829,7 +14723,7 @@ pub fn _mm512_mask_cvt_roundph_epu32( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2udq, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundph_epu32(k: __mmask16, a: __m256h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epu32::(_mm512_setzero_si512(), k, a) @@ -14842,7 +14736,7 @@ pub fn _mm512_maskz_cvt_roundph_epu32(k: __mmask16, a: __m2 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2usi))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtsh_u32(a: __m128h) -> u32 { unsafe { vcvtsh2usi32(a, _MM_FROUND_CUR_DIRECTION) } } @@ -14857,7 +14751,7 @@ pub fn _mm_cvtsh_u32(a: __m128h) -> u32 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2usi, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundsh_u32(a: __m128h) -> u32 { unsafe { static_assert_rounding!(SAE); @@ -14872,7 +14766,7 @@ pub fn _mm_cvt_roundsh_u32(a: __m128h) -> u32 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttph_epi32(a: __m128h) -> __m128i { _mm_mask_cvttph_epi32(_mm_undefined_si128(), 0xff, a) } @@ -14884,7 +14778,7 @@ pub fn _mm_cvttph_epi32(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvttph_epi32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvttph2dq_128(a, src.as_i32x4(), k)) } } @@ -14896,7 +14790,7 @@ pub fn _mm_mask_cvttph_epi32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvttph_epi32(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvttph_epi32(_mm_setzero_si128(), k, a) } @@ -14908,7 +14802,7 @@ pub fn _mm_maskz_cvttph_epi32(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvttph_epi32(a: __m128h) -> __m256i { _mm256_mask_cvttph_epi32(_mm256_undefined_si256(), 0xff, a) } @@ -14920,7 +14814,7 @@ pub fn _mm256_cvttph_epi32(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvttph_epi32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvttph2dq_256(a, src.as_i32x8(), k)) } } @@ -14932,7 +14826,7 @@ pub fn _mm256_mask_cvttph_epi32(src: __m256i, k: __mmask8, a: __m128h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvttph_epi32(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvttph_epi32(_mm256_setzero_si256(), k, a) } @@ -14944,7 +14838,7 @@ pub fn _mm256_maskz_cvttph_epi32(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvttph_epi32(a: __m256h) -> __m512i { _mm512_mask_cvttph_epi32(_mm512_undefined_epi32(), 0xffff, a) } @@ -14956,7 +14850,7 @@ pub fn _mm512_cvttph_epi32(a: __m256h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvttph_epi32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i { unsafe { transmute(vcvttph2dq_512( @@ -14975,7 +14869,7 @@ pub fn _mm512_mask_cvttph_epi32(src: __m512i, k: __mmask16, a: __m256h) -> __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvttph_epi32(k: __mmask16, a: __m256h) -> __m512i { _mm512_mask_cvttph_epi32(_mm512_setzero_si512(), k, a) } @@ -14990,7 +14884,7 @@ pub fn _mm512_maskz_cvttph_epi32(k: __mmask16, a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2dq, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtt_roundph_epi32(a: __m256h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epi32::(_mm512_undefined_epi32(), 0xffff, a) @@ -15006,7 +14900,7 @@ pub fn _mm512_cvtt_roundph_epi32(a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2dq, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtt_roundph_epi32( src: __m512i, k: __mmask16, @@ -15028,7 +14922,7 @@ pub fn _mm512_mask_cvtt_roundph_epi32( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2dq, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtt_roundph_epi32(k: __mmask16, a: __m256h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epi32::(_mm512_setzero_si512(), k, a) @@ -15041,7 +14935,7 @@ pub fn _mm512_maskz_cvtt_roundph_epi32(k: __mmask16, a: __m256h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2si))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttsh_i32(a: __m128h) -> i32 { unsafe { vcvttsh2si32(a, _MM_FROUND_CUR_DIRECTION) } } @@ -15056,7 +14950,7 @@ pub fn _mm_cvttsh_i32(a: __m128h) -> i32 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2si, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtt_roundsh_i32(a: __m128h) -> i32 { unsafe { static_assert_sae!(SAE); @@ -15071,7 +14965,7 @@ pub fn _mm_cvtt_roundsh_i32(a: __m128h) -> i32 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttph_epu32(a: __m128h) -> __m128i { _mm_mask_cvttph_epu32(_mm_undefined_si128(), 0xff, a) } @@ -15083,7 +14977,7 @@ pub fn _mm_cvttph_epu32(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvttph_epu32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvttph2udq_128(a, src.as_u32x4(), k)) } } @@ -15095,7 +14989,7 @@ pub fn _mm_mask_cvttph_epu32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvttph_epu32(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvttph_epu32(_mm_setzero_si128(), k, a) } @@ -15107,7 +15001,7 @@ pub fn _mm_maskz_cvttph_epu32(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvttph_epu32(a: __m128h) -> __m256i { _mm256_mask_cvttph_epu32(_mm256_undefined_si256(), 0xff, a) } @@ -15119,7 +15013,7 @@ pub fn _mm256_cvttph_epu32(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvttph_epu32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvttph2udq_256(a, src.as_u32x8(), k)) } } @@ -15131,7 +15025,7 @@ pub fn _mm256_mask_cvttph_epu32(src: __m256i, k: __mmask8, a: __m128h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvttph_epu32(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvttph_epu32(_mm256_setzero_si256(), k, a) } @@ -15143,7 +15037,7 @@ pub fn _mm256_maskz_cvttph_epu32(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvttph_epu32(a: __m256h) -> __m512i { _mm512_mask_cvttph_epu32(_mm512_undefined_epi32(), 0xffff, a) } @@ -15155,7 +15049,7 @@ pub fn _mm512_cvttph_epu32(a: __m256h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvttph_epu32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i { unsafe { transmute(vcvttph2udq_512( @@ -15174,7 +15068,7 @@ pub fn _mm512_mask_cvttph_epu32(src: __m512i, k: __mmask16, a: __m256h) -> __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvttph_epu32(k: __mmask16, a: __m256h) -> __m512i { _mm512_mask_cvttph_epu32(_mm512_setzero_si512(), k, a) } @@ -15189,7 +15083,7 @@ pub fn _mm512_maskz_cvttph_epu32(k: __mmask16, a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2udq, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtt_roundph_epu32(a: __m256h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epu32::(_mm512_undefined_epi32(), 0xffff, a) @@ -15205,7 +15099,7 @@ pub fn _mm512_cvtt_roundph_epu32(a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2udq, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtt_roundph_epu32( src: __m512i, k: __mmask16, @@ -15227,7 +15121,7 @@ pub fn _mm512_mask_cvtt_roundph_epu32( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2udq, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtt_roundph_epu32(k: __mmask16, a: __m256h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epu32::(_mm512_setzero_si512(), k, a) @@ -15240,7 +15134,7 @@ pub fn _mm512_maskz_cvtt_roundph_epu32(k: __mmask16, a: __m256h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2usi))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttsh_u32(a: __m128h) -> u32 { unsafe { vcvttsh2usi32(a, _MM_FROUND_CUR_DIRECTION) } } @@ -15255,7 +15149,7 @@ pub fn _mm_cvttsh_u32(a: __m128h) -> u32 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2usi, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtt_roundsh_u32(a: __m128h) -> u32 { unsafe { static_assert_sae!(SAE); @@ -15270,7 +15164,7 @@ pub fn _mm_cvtt_roundsh_u32(a: __m128h) -> u32 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtph_epi64(a: __m128h) -> __m128i { _mm_mask_cvtph_epi64(_mm_undefined_si128(), 0xff, a) } @@ -15282,7 +15176,7 @@ pub fn _mm_cvtph_epi64(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtph_epi64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvtph2qq_128(a, src.as_i64x2(), k)) } } @@ -15294,7 +15188,7 @@ pub fn _mm_mask_cvtph_epi64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvtph_epi64(_mm_setzero_si128(), k, a) } @@ -15306,7 +15200,7 @@ pub fn _mm_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtph_epi64(a: __m128h) -> __m256i { _mm256_mask_cvtph_epi64(_mm256_undefined_si256(), 0xff, a) } @@ -15318,7 +15212,7 @@ pub fn _mm256_cvtph_epi64(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtph_epi64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvtph2qq_256(a, src.as_i64x4(), k)) } } @@ -15330,7 +15224,7 @@ pub fn _mm256_mask_cvtph_epi64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvtph_epi64(_mm256_setzero_si256(), k, a) } @@ -15342,7 +15236,7 @@ pub fn _mm256_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtph_epi64(a: __m128h) -> __m512i { _mm512_mask_cvtph_epi64(_mm512_undefined_epi32(), 0xff, a) } @@ -15354,7 +15248,7 @@ pub fn _mm512_cvtph_epi64(a: __m128h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtph_epi64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i { unsafe { transmute(vcvtph2qq_512( @@ -15373,7 +15267,7 @@ pub fn _mm512_mask_cvtph_epi64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m512i { _mm512_mask_cvtph_epi64(_mm512_setzero_si512(), k, a) } @@ -15394,7 +15288,7 @@ pub fn _mm512_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2qq, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundph_epi64(a: __m128h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epi64::(_mm512_undefined_epi32(), 0xff, a) @@ -15416,7 +15310,7 @@ pub fn _mm512_cvt_roundph_epi64(a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2qq, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundph_epi64( src: __m512i, k: __mmask8, @@ -15444,7 +15338,7 @@ pub fn _mm512_mask_cvt_roundph_epi64( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2qq, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundph_epi64(k: __mmask8, a: __m128h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epi64::(_mm512_setzero_si512(), k, a) @@ -15457,7 +15351,7 @@ pub fn _mm512_maskz_cvt_roundph_epi64(k: __mmask8, a: __m12 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtph_epu64(a: __m128h) -> __m128i { _mm_mask_cvtph_epu64(_mm_undefined_si128(), 0xff, a) } @@ -15469,7 +15363,7 @@ pub fn _mm_cvtph_epu64(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtph_epu64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvtph2uqq_128(a, src.as_u64x2(), k)) } } @@ -15481,7 +15375,7 @@ pub fn _mm_mask_cvtph_epu64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvtph_epu64(_mm_setzero_si128(), k, a) } @@ -15493,7 +15387,7 @@ pub fn _mm_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtph_epu64(a: __m128h) -> __m256i { _mm256_mask_cvtph_epu64(_mm256_undefined_si256(), 0xff, a) } @@ -15505,7 +15399,7 @@ pub fn _mm256_cvtph_epu64(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtph_epu64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvtph2uqq_256(a, src.as_u64x4(), k)) } } @@ -15517,7 +15411,7 @@ pub fn _mm256_mask_cvtph_epu64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvtph_epu64(_mm256_setzero_si256(), k, a) } @@ -15529,7 +15423,7 @@ pub fn _mm256_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtph_epu64(a: __m128h) -> __m512i { _mm512_mask_cvtph_epu64(_mm512_undefined_epi32(), 0xff, a) } @@ -15541,7 +15435,7 @@ pub fn _mm512_cvtph_epu64(a: __m128h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtph_epu64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i { unsafe { transmute(vcvtph2uqq_512( @@ -15560,7 +15454,7 @@ pub fn _mm512_mask_cvtph_epu64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m512i { _mm512_mask_cvtph_epu64(_mm512_setzero_si512(), k, a) } @@ -15581,7 +15475,7 @@ pub fn _mm512_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uqq, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundph_epu64(a: __m128h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epu64::(_mm512_undefined_epi32(), 0xff, a) @@ -15603,7 +15497,7 @@ pub fn _mm512_cvt_roundph_epu64(a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uqq, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundph_epu64( src: __m512i, k: __mmask8, @@ -15631,7 +15525,7 @@ pub fn _mm512_mask_cvt_roundph_epu64( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uqq, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundph_epu64(k: __mmask8, a: __m128h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epu64::(_mm512_setzero_si512(), k, a) @@ -15644,7 +15538,7 @@ pub fn _mm512_maskz_cvt_roundph_epu64(k: __mmask8, a: __m12 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttph_epi64(a: __m128h) -> __m128i { _mm_mask_cvttph_epi64(_mm_undefined_si128(), 0xff, a) } @@ -15656,7 +15550,7 @@ pub fn _mm_cvttph_epi64(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvttph_epi64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvttph2qq_128(a, src.as_i64x2(), k)) } } @@ -15668,7 +15562,7 @@ pub fn _mm_mask_cvttph_epi64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvttph_epi64(_mm_setzero_si128(), k, a) } @@ -15680,7 +15574,7 @@ pub fn _mm_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvttph_epi64(a: __m128h) -> __m256i { _mm256_mask_cvttph_epi64(_mm256_undefined_si256(), 0xff, a) } @@ -15692,7 +15586,7 @@ pub fn _mm256_cvttph_epi64(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvttph_epi64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvttph2qq_256(a, src.as_i64x4(), k)) } } @@ -15704,7 +15598,7 @@ pub fn _mm256_mask_cvttph_epi64(src: __m256i, k: __mmask8, a: __m128h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvttph_epi64(_mm256_setzero_si256(), k, a) } @@ -15716,7 +15610,7 @@ pub fn _mm256_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvttph_epi64(a: __m128h) -> __m512i { _mm512_mask_cvttph_epi64(_mm512_undefined_epi32(), 0xff, a) } @@ -15728,7 +15622,7 @@ pub fn _mm512_cvttph_epi64(a: __m128h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvttph_epi64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i { unsafe { transmute(vcvttph2qq_512( @@ -15747,7 +15641,7 @@ pub fn _mm512_mask_cvttph_epi64(src: __m512i, k: __mmask8, a: __m128h) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m512i { _mm512_mask_cvttph_epi64(_mm512_setzero_si512(), k, a) } @@ -15762,7 +15656,7 @@ pub fn _mm512_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2qq, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtt_roundph_epi64(a: __m128h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epi64::(_mm512_undefined_epi32(), 0xff, a) @@ -15778,7 +15672,7 @@ pub fn _mm512_cvtt_roundph_epi64(a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2qq, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtt_roundph_epi64( src: __m512i, k: __mmask8, @@ -15800,7 +15694,7 @@ pub fn _mm512_mask_cvtt_roundph_epi64( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2qq, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtt_roundph_epi64(k: __mmask8, a: __m128h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epi64::(_mm512_setzero_si512(), k, a) @@ -15813,7 +15707,7 @@ pub fn _mm512_maskz_cvtt_roundph_epi64(k: __mmask8, a: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttph_epu64(a: __m128h) -> __m128i { _mm_mask_cvttph_epu64(_mm_undefined_si128(), 0xff, a) } @@ -15825,7 +15719,7 @@ pub fn _mm_cvttph_epu64(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvttph_epu64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvttph2uqq_128(a, src.as_u64x2(), k)) } } @@ -15837,7 +15731,7 @@ pub fn _mm_mask_cvttph_epu64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvttph_epu64(_mm_setzero_si128(), k, a) } @@ -15849,7 +15743,7 @@ pub fn _mm_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvttph_epu64(a: __m128h) -> __m256i { _mm256_mask_cvttph_epu64(_mm256_undefined_si256(), 0xff, a) } @@ -15861,7 +15755,7 @@ pub fn _mm256_cvttph_epu64(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvttph_epu64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvttph2uqq_256(a, src.as_u64x4(), k)) } } @@ -15873,7 +15767,7 @@ pub fn _mm256_mask_cvttph_epu64(src: __m256i, k: __mmask8, a: __m128h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvttph_epu64(_mm256_setzero_si256(), k, a) } @@ -15885,7 +15779,7 @@ pub fn _mm256_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvttph_epu64(a: __m128h) -> __m512i { _mm512_mask_cvttph_epu64(_mm512_undefined_epi32(), 0xff, a) } @@ -15897,7 +15791,7 @@ pub fn _mm512_cvttph_epu64(a: __m128h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvttph_epu64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i { unsafe { transmute(vcvttph2uqq_512( @@ -15916,7 +15810,7 @@ pub fn _mm512_mask_cvttph_epu64(src: __m512i, k: __mmask8, a: __m128h) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m512i { _mm512_mask_cvttph_epu64(_mm512_setzero_si512(), k, a) } @@ -15931,7 +15825,7 @@ pub fn _mm512_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uqq, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtt_roundph_epu64(a: __m128h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epu64::(_mm512_undefined_epi32(), 0xff, a) @@ -15947,7 +15841,7 @@ pub fn _mm512_cvtt_roundph_epu64(a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uqq, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtt_roundph_epu64( src: __m512i, k: __mmask8, @@ -15969,7 +15863,7 @@ pub fn _mm512_mask_cvtt_roundph_epu64( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uqq, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtt_roundph_epu64(k: __mmask8, a: __m128h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epu64::(_mm512_setzero_si512(), k, a) @@ -15982,7 +15876,7 @@ pub fn _mm512_maskz_cvtt_roundph_epu64(k: __mmask8, a: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtxph_ps(a: __m128h) -> __m128 { _mm_mask_cvtxph_ps(_mm_setzero_ps(), 0xff, a) } @@ -15995,7 +15889,7 @@ pub fn _mm_cvtxph_ps(a: __m128h) -> __m128 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtxph_ps(src: __m128, k: __mmask8, a: __m128h) -> __m128 { unsafe { vcvtph2psx_128(a, src, k) } } @@ -16008,7 +15902,7 @@ pub fn _mm_mask_cvtxph_ps(src: __m128, k: __mmask8, a: __m128h) -> __m128 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtxph_ps(k: __mmask8, a: __m128h) -> __m128 { _mm_mask_cvtxph_ps(_mm_setzero_ps(), k, a) } @@ -16020,7 +15914,7 @@ pub fn _mm_maskz_cvtxph_ps(k: __mmask8, a: __m128h) -> __m128 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtxph_ps(a: __m128h) -> __m256 { _mm256_mask_cvtxph_ps(_mm256_setzero_ps(), 0xff, a) } @@ -16033,7 +15927,7 @@ pub fn _mm256_cvtxph_ps(a: __m128h) -> __m256 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtxph_ps(src: __m256, k: __mmask8, a: __m128h) -> __m256 { unsafe { vcvtph2psx_256(a, src, k) } } @@ -16046,7 +15940,7 @@ pub fn _mm256_mask_cvtxph_ps(src: __m256, k: __mmask8, a: __m128h) -> __m256 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtxph_ps(k: __mmask8, a: __m128h) -> __m256 { _mm256_mask_cvtxph_ps(_mm256_setzero_ps(), k, a) } @@ -16058,7 +15952,7 @@ pub fn _mm256_maskz_cvtxph_ps(k: __mmask8, a: __m128h) -> __m256 { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtxph_ps(a: __m256h) -> __m512 { _mm512_mask_cvtxph_ps(_mm512_setzero_ps(), 0xffff, a) } @@ -16071,7 +15965,7 @@ pub fn _mm512_cvtxph_ps(a: __m256h) -> __m512 { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtxph_ps(src: __m512, k: __mmask16, a: __m256h) -> __m512 { unsafe { vcvtph2psx_512(a, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -16084,7 +15978,7 @@ pub fn _mm512_mask_cvtxph_ps(src: __m512, k: __mmask16, a: __m256h) -> __m512 { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtxph_ps(k: __mmask16, a: __m256h) -> __m512 { _mm512_mask_cvtxph_ps(_mm512_setzero_ps(), k, a) } @@ -16099,7 +15993,7 @@ pub fn _mm512_maskz_cvtxph_ps(k: __mmask16, a: __m256h) -> __m512 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2psx, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtx_roundph_ps(a: __m256h) -> __m512 { static_assert_sae!(SAE); _mm512_mask_cvtx_roundph_ps::(_mm512_setzero_ps(), 0xffff, a) @@ -16116,7 +16010,7 @@ pub fn _mm512_cvtx_roundph_ps(a: __m256h) -> __m512 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2psx, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtx_roundph_ps( src: __m512, k: __mmask16, @@ -16139,7 +16033,7 @@ pub fn _mm512_mask_cvtx_roundph_ps( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2psx, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtx_roundph_ps(k: __mmask16, a: __m256h) -> __m512 { static_assert_sae!(SAE); _mm512_mask_cvtx_roundph_ps::(_mm512_setzero_ps(), k, a) @@ -16153,7 +16047,7 @@ pub fn _mm512_maskz_cvtx_roundph_ps(k: __mmask16, a: __m256h) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2ss))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtsh_ss(a: __m128, b: __m128h) -> __m128 { _mm_mask_cvtsh_ss(a, 0xff, a, b) } @@ -16167,7 +16061,7 @@ pub fn _mm_cvtsh_ss(a: __m128, b: __m128h) -> __m128 { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2ss))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtsh_ss(src: __m128, k: __mmask8, a: __m128, b: __m128h) -> __m128 { unsafe { vcvtsh2ss(a, b, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -16181,7 +16075,7 @@ pub fn _mm_mask_cvtsh_ss(src: __m128, k: __mmask8, a: __m128, b: __m128h) -> __m #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2ss))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtsh_ss(k: __mmask8, a: __m128, b: __m128h) -> __m128 { _mm_mask_cvtsh_ss(_mm_set_ss(0.0), k, a, b) } @@ -16197,7 +16091,7 @@ pub fn _mm_maskz_cvtsh_ss(k: __mmask8, a: __m128, b: __m128h) -> __m128 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2ss, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundsh_ss(a: __m128, b: __m128h) -> __m128 { static_assert_sae!(SAE); _mm_mask_cvt_roundsh_ss::(_mm_undefined_ps(), 0xff, a, b) @@ -16215,7 +16109,7 @@ pub fn _mm_cvt_roundsh_ss(a: __m128, b: __m128h) -> __m128 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2ss, SAE = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvt_roundsh_ss( src: __m128, k: __mmask8, @@ -16240,7 +16134,7 @@ pub fn _mm_mask_cvt_roundsh_ss( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2ss, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvt_roundsh_ss(k: __mmask8, a: __m128, b: __m128h) -> __m128 { static_assert_sae!(SAE); _mm_mask_cvt_roundsh_ss::(_mm_set_ss(0.0), k, a, b) @@ -16253,7 +16147,7 @@ pub fn _mm_maskz_cvt_roundsh_ss(k: __mmask8, a: __m128, b: __m12 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtph_pd(a: __m128h) -> __m128d { _mm_mask_cvtph_pd(_mm_setzero_pd(), 0xff, a) } @@ -16266,7 +16160,7 @@ pub fn _mm_cvtph_pd(a: __m128h) -> __m128d { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtph_pd(src: __m128d, k: __mmask8, a: __m128h) -> __m128d { unsafe { vcvtph2pd_128(a, src, k) } } @@ -16279,7 +16173,7 @@ pub fn _mm_mask_cvtph_pd(src: __m128d, k: __mmask8, a: __m128h) -> __m128d { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m128d { _mm_mask_cvtph_pd(_mm_setzero_pd(), k, a) } @@ -16291,7 +16185,7 @@ pub fn _mm_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m128d { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtph_pd(a: __m128h) -> __m256d { _mm256_mask_cvtph_pd(_mm256_setzero_pd(), 0xff, a) } @@ -16304,7 +16198,7 @@ pub fn _mm256_cvtph_pd(a: __m128h) -> __m256d { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtph_pd(src: __m256d, k: __mmask8, a: __m128h) -> __m256d { unsafe { vcvtph2pd_256(a, src, k) } } @@ -16317,7 +16211,7 @@ pub fn _mm256_mask_cvtph_pd(src: __m256d, k: __mmask8, a: __m128h) -> __m256d { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m256d { _mm256_mask_cvtph_pd(_mm256_setzero_pd(), k, a) } @@ -16329,7 +16223,7 @@ pub fn _mm256_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m256d { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtph_pd(a: __m128h) -> __m512d { _mm512_mask_cvtph_pd(_mm512_setzero_pd(), 0xff, a) } @@ -16342,7 +16236,7 @@ pub fn _mm512_cvtph_pd(a: __m128h) -> __m512d { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtph_pd(src: __m512d, k: __mmask8, a: __m128h) -> __m512d { unsafe { vcvtph2pd_512(a, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -16355,7 +16249,7 @@ pub fn _mm512_mask_cvtph_pd(src: __m512d, k: __mmask8, a: __m128h) -> __m512d { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m512d { _mm512_mask_cvtph_pd(_mm512_setzero_pd(), k, a) } @@ -16370,7 +16264,7 @@ pub fn _mm512_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m512d { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2pd, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundph_pd(a: __m128h) -> __m512d { static_assert_sae!(SAE); _mm512_mask_cvt_roundph_pd::(_mm512_setzero_pd(), 0xff, a) @@ -16387,7 +16281,7 @@ pub fn _mm512_cvt_roundph_pd(a: __m128h) -> __m512d { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2pd, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundph_pd( src: __m512d, k: __mmask8, @@ -16410,7 +16304,7 @@ pub fn _mm512_mask_cvt_roundph_pd( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2pd, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundph_pd(k: __mmask8, a: __m128h) -> __m512d { static_assert_sae!(SAE); _mm512_mask_cvt_roundph_pd::(_mm512_setzero_pd(), k, a) @@ -16424,7 +16318,7 @@ pub fn _mm512_maskz_cvt_roundph_pd(k: __mmask8, a: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2sd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtsh_sd(a: __m128d, b: __m128h) -> __m128d { _mm_mask_cvtsh_sd(a, 0xff, a, b) } @@ -16438,7 +16332,7 @@ pub fn _mm_cvtsh_sd(a: __m128d, b: __m128h) -> __m128d { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2sd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtsh_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128h) -> __m128d { unsafe { vcvtsh2sd(a, b, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -16451,7 +16345,7 @@ pub fn _mm_mask_cvtsh_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2sd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtsh_sd(k: __mmask8, a: __m128d, b: __m128h) -> __m128d { _mm_mask_cvtsh_sd(_mm_set_sd(0.0), k, a, b) } @@ -16467,7 +16361,7 @@ pub fn _mm_maskz_cvtsh_sd(k: __mmask8, a: __m128d, b: __m128h) -> __m128d { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2sd, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundsh_sd(a: __m128d, b: __m128h) -> __m128d { static_assert_sae!(SAE); _mm_mask_cvt_roundsh_sd::(a, 0xff, a, b) @@ -16485,7 +16379,7 @@ pub fn _mm_cvt_roundsh_sd(a: __m128d, b: __m128h) -> __m128d { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2sd, SAE = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvt_roundsh_sd( src: __m128d, k: __mmask8, @@ -16509,7 +16403,7 @@ pub fn _mm_mask_cvt_roundsh_sd( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2sd, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvt_roundsh_sd(k: __mmask8, a: __m128d, b: __m128h) -> __m128d { static_assert_sae!(SAE); _mm_mask_cvt_roundsh_sd::(_mm_set_sd(0.0), k, a, b) @@ -16553,7 +16447,7 @@ pub const fn _mm512_cvtsh_h(a: __m512h) -> f16 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi128_si16) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_cvtsi128_si16(a: __m128i) -> i16 { unsafe { simd_extract!(a.as_i16x8(), 0) } @@ -16564,18 +16458,25 @@ pub const fn _mm_cvtsi128_si16(a: __m128i) -> i16 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi16_si128) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_cvtsi16_si128(a: i16) -> __m128i { unsafe { transmute(simd_insert!(i16x8::ZERO, 0, a)) } } #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { + #[link_name = "llvm.x86.avx512fp16.mask.cmp.ph.128"] + fn vcmpph_128(a: __m128h, b: __m128h, imm5: i32, mask: __mmask8) -> __mmask8; + #[link_name = "llvm.x86.avx512fp16.mask.cmp.ph.256"] + fn vcmpph_256(a: __m256h, b: __m256h, imm5: i32, mask: __mmask16) -> __mmask16; + #[link_name = "llvm.x86.avx512fp16.mask.cmp.ph.512"] + fn vcmpph_512(a: __m512h, b: __m512h, imm5: i32, mask: __mmask32, sae: i32) -> __mmask32; + #[link_name = "llvm.x86.avx512fp16.mask.cmp.sh"] - fn vcmpsh(a: __m128h, b: __m128h, imm8: i32, mask: __mmask8, sae: i32) -> __mmask8; + fn vcmpsh(a: __m128h, b: __m128h, imm5: i32, mask: __mmask8, sae: i32) -> __mmask8; #[link_name = "llvm.x86.avx512fp16.vcomi.sh"] - fn vcomish(a: __m128h, b: __m128h, imm8: i32, sae: i32) -> i32; + fn vcomish(a: __m128h, b: __m128h, imm5: i32, sae: i32) -> i32; #[link_name = "llvm.x86.avx512fp16.add.ph.512"] fn vaddph(a: __m512h, b: __m512h, rounding: i32) -> __m512h; @@ -16758,6 +16659,13 @@ unsafe extern "C" { fn vreducesh(a: __m128h, b: __m128h, src: __m128h, k: __mmask8, imm8: i32, sae: i32) -> __m128h; + #[link_name = "llvm.x86.avx512fp16.fpclass.ph.128"] + fn vfpclassph_128(a: __m128h, imm8: i32) -> __mmask8; + #[link_name = "llvm.x86.avx512fp16.fpclass.ph.256"] + fn vfpclassph_256(a: __m256h, imm8: i32) -> __mmask16; + #[link_name = "llvm.x86.avx512fp16.fpclass.ph.512"] + fn vfpclassph_512(a: __m512h, imm8: i32) -> __mmask32; + #[link_name = "llvm.x86.avx512fp16.mask.fpclass.sh"] fn vfpclasssh(a: __m128h, imm8: i32, k: __mmask8) -> __mmask8; diff --git a/library/stdarch/crates/core_arch/src/x86/avx512ifma.rs b/library/stdarch/crates/core_arch/src/x86/avx512ifma.rs index 5ce28565d1085..262215e62c43d 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512ifma.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512ifma.rs @@ -347,7 +347,7 @@ pub fn _mm_maskz_madd52lo_epu64(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) } #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.avx512.vpmadd52l.uq.128"] fn vpmadd52luq_128(z: __m128i, x: __m128i, y: __m128i) -> __m128i; #[link_name = "llvm.x86.avx512.vpmadd52h.uq.128"] diff --git a/library/stdarch/crates/core_arch/src/x86/avx512vbmi.rs b/library/stdarch/crates/core_arch/src/x86/avx512vbmi.rs index d9ad14ef00ddb..3d0662269ee37 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512vbmi.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512vbmi.rs @@ -453,7 +453,7 @@ pub fn _mm_maskz_multishift_epi64_epi8(k: __mmask16, a: __m128i, b: __m128i) -> } #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.avx512.vpermi2var.qi.512"] fn vpermi2b(a: i8x64, idx: i8x64, b: i8x64) -> i8x64; #[link_name = "llvm.x86.avx512.vpermi2var.qi.256"] @@ -737,15 +737,35 @@ mod tests { } #[simd_test(enable = "avx512vbmi")] - fn test_mm512_permutexvar_epi8() { - let idx = _mm512_set1_epi8(1); - #[rustfmt::skip] - let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, - 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, - 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, - 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63); + unsafe fn test_mm512_permutexvar_epi8() { + #[rustfmt::skip] + let idx_arr: [u8; 64] = [ + 34, 58, 27, 72, 19, 38, 53, 0, 44, 15, 29, 81, 20, 35, 62, 6, + 24, 49, 10, 68, 22, 57, 40, 13, 52, 1, 30, 95, 16, 33, 4, 55, + 26, 47, 11, 74, 21, 59, 36, 8, 50, 3, 28, 99, 14, 45, 61, 2, + 18, 39, 7, 64, 23, 54, 9,127, 12, 31, 88, 5, 42, 17, 0, 63, + ]; + + #[rustfmt::skip] + let a_arr: [i8; 64] = [ + -93, -94, -95, -96, -97, -98, -99, -100, + -101, -102, -103, -104, -105, -106, -107, -108, + -109, -110, -111, -112, -113, -114, -115, -116, + -117, -118, -119, -120, -121, -122, -123, -124, + -125, -126, -127, -128, 127, 126, 125, 124, + 123, 122, 121, 120, 119, 118, 117, 116, + 115, 114, 113, 112, 111, 110, 109, 108, + 107, 106, 105, 104, 103, 102, 101, 100, + ]; + + let idx = transmute(idx_arr); + let a = transmute(a_arr); + let r = _mm512_permutexvar_epi8(idx, a); - let e = _mm512_set1_epi8(62); + + let e_arr = std::array::from_fn(|i| a_arr[(idx_arr[i] & 0b0011_1111) as usize]); + let e = transmute::<[i8; 64], _>(e_arr); + assert_eq_m512i(r, e); } @@ -789,13 +809,30 @@ mod tests { } #[simd_test(enable = "avx512vbmi,avx512vl")] - fn test_mm256_permutexvar_epi8() { - let idx = _mm256_set1_epi8(1); + unsafe fn test_mm256_permutexvar_epi8() { #[rustfmt::skip] - let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, - 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31); + let idx_arr: [u8; 32] = [ + 26, 47, 11, 42, 21, 59, 36, 8, + 18, 3, 28, 31, 14, 45, 29, 2, + 24, 17, 10, 30, 22, 25, 12, 13, + 20, 1, 6, 15, 16, 9, 0, 63, + ]; + + #[rustfmt::skip] + let a_arr: [i8; 32] = [ + -93, -94, -95, -96, -97, -98, -99, -100, + -101, -102, -103, -104, -105, -106, -107, -108, + -109, -110, -111, -112, -113, -114, -115, -116, + -117, -118, -119, -120, -121, -122, -123, -124, + ]; + + let idx = transmute(idx_arr); + let a = transmute(a_arr); let r = _mm256_permutexvar_epi8(idx, a); - let e = _mm256_set1_epi8(30); + + let e_arr = std::array::from_fn(|i| a_arr[(idx_arr[i] & 0b0001_1111) as usize]); + let e = transmute::<[i8; 32], _>(e_arr); + assert_eq_m256i(r, e); } @@ -826,11 +863,30 @@ mod tests { } #[simd_test(enable = "avx512vbmi,avx512vl")] - fn test_mm_permutexvar_epi8() { - let idx = _mm_set1_epi8(1); - let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); + unsafe fn test_mm_permutexvar_epi8() { + #[rustfmt::skip] + let idx_arr: [u8; 16] = [ + 14, 3, 12, 7, + 8, 1, 10, 15, + 4, 9, 2, 13, + 6, 11, 0, 31, + ]; + + #[rustfmt::skip] + let a_arr: [i8; 16] = [ + -93, -94, -95, -96, + -97, -98, -99, -100, + -101, -102, -103, -104, + -105, -106, -107, -108, + ]; + + let idx = transmute(idx_arr); + let a = transmute(a_arr); let r = _mm_permutexvar_epi8(idx, a); - let e = _mm_set1_epi8(14); + + let e_arr = std::array::from_fn(|i| a_arr[(idx_arr[i] & 0b0000_1111) as usize]); + let e = transmute::<[i8; 16], _>(e_arr); + assert_eq_m128i(r, e); } diff --git a/library/stdarch/crates/core_arch/src/x86/avx512vbmi2.rs b/library/stdarch/crates/core_arch/src/x86/avx512vbmi2.rs index 78a50b90c8614..0a4accc2f70fb 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512vbmi2.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512vbmi2.rs @@ -2383,7 +2383,7 @@ pub const fn _mm_maskz_shrdi_epi16( } #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.avx512.mask.compress.store.w.512"] fn vcompressstorew(mem: *mut i8, data: i16x32, mask: u32); #[link_name = "llvm.x86.avx512.mask.compress.store.w.256"] diff --git a/library/stdarch/crates/core_arch/src/x86/avx512vnni.rs b/library/stdarch/crates/core_arch/src/x86/avx512vnni.rs index 49b790b151049..b9084aec59344 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512vnni.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512vnni.rs @@ -12,7 +12,7 @@ use stdarch_test::assert_instr; #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssd))] pub fn _mm512_dpwssd_epi32(src: __m512i, a: __m512i, b: __m512i) -> __m512i { - unsafe { transmute(vpdpwssd(src.as_i32x16(), a.as_i32x16(), b.as_i32x16())) } + unsafe { transmute(vpdpwssd(src.as_i32x16(), a.as_i16x32(), b.as_i16x32())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -51,7 +51,7 @@ pub fn _mm512_maskz_dpwssd_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m5 #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssd))] pub fn _mm256_dpwssd_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpwssd256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpwssd256(src.as_i32x8(), a.as_i16x16(), b.as_i16x16())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst. @@ -62,7 +62,7 @@ pub fn _mm256_dpwssd_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssd))] pub fn _mm256_dpwssd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpwssd256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpwssd256(src.as_i32x8(), a.as_i16x16(), b.as_i16x16())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -101,7 +101,7 @@ pub fn _mm256_maskz_dpwssd_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m25 #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssd))] pub fn _mm_dpwssd_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpwssd128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpwssd128(src.as_i32x4(), a.as_i16x8(), b.as_i16x8())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst. @@ -112,7 +112,7 @@ pub fn _mm_dpwssd_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssd))] pub fn _mm_dpwssd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpwssd128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpwssd128(src.as_i32x4(), a.as_i16x8(), b.as_i16x8())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -151,7 +151,7 @@ pub fn _mm_maskz_dpwssd_epi32(k: __mmask8, src: __m128i, a: __m128i, b: __m128i) #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssds))] pub fn _mm512_dpwssds_epi32(src: __m512i, a: __m512i, b: __m512i) -> __m512i { - unsafe { transmute(vpdpwssds(src.as_i32x16(), a.as_i32x16(), b.as_i32x16())) } + unsafe { transmute(vpdpwssds(src.as_i32x16(), a.as_i16x32(), b.as_i16x32())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -190,7 +190,7 @@ pub fn _mm512_maskz_dpwssds_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssds))] pub fn _mm256_dpwssds_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpwssds256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpwssds256(src.as_i32x8(), a.as_i16x16(), b.as_i16x16())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst. @@ -201,7 +201,7 @@ pub fn _mm256_dpwssds_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssds))] pub fn _mm256_dpwssds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpwssds256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpwssds256(src.as_i32x8(), a.as_i16x16(), b.as_i16x16())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -240,7 +240,7 @@ pub fn _mm256_maskz_dpwssds_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m2 #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssds))] pub fn _mm_dpwssds_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpwssds128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpwssds128(src.as_i32x4(), a.as_i16x8(), b.as_i16x8())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst. @@ -251,7 +251,7 @@ pub fn _mm_dpwssds_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssds))] pub fn _mm_dpwssds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpwssds128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpwssds128(src.as_i32x4(), a.as_i16x8(), b.as_i16x8())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -290,7 +290,7 @@ pub fn _mm_maskz_dpwssds_epi32(k: __mmask8, src: __m128i, a: __m128i, b: __m128i #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusd))] pub fn _mm512_dpbusd_epi32(src: __m512i, a: __m512i, b: __m512i) -> __m512i { - unsafe { transmute(vpdpbusd(src.as_i32x16(), a.as_i32x16(), b.as_i32x16())) } + unsafe { transmute(vpdpbusd(src.as_i32x16(), a.as_u8x64(), b.as_i8x64())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -329,7 +329,7 @@ pub fn _mm512_maskz_dpbusd_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m5 #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusd))] pub fn _mm256_dpbusd_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpbusd256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpbusd256(src.as_i32x8(), a.as_u8x32(), b.as_i8x32())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst. @@ -340,7 +340,7 @@ pub fn _mm256_dpbusd_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusd))] pub fn _mm256_dpbusd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpbusd256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpbusd256(src.as_i32x8(), a.as_u8x32(), b.as_i8x32())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -379,7 +379,7 @@ pub fn _mm256_maskz_dpbusd_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m25 #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusd))] pub fn _mm_dpbusd_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpbusd128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpbusd128(src.as_i32x4(), a.as_u8x16(), b.as_i8x16())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst. @@ -390,7 +390,7 @@ pub fn _mm_dpbusd_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusd))] pub fn _mm_dpbusd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpbusd128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpbusd128(src.as_i32x4(), a.as_u8x16(), b.as_i8x16())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -429,7 +429,7 @@ pub fn _mm_maskz_dpbusd_epi32(k: __mmask8, src: __m128i, a: __m128i, b: __m128i) #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusds))] pub fn _mm512_dpbusds_epi32(src: __m512i, a: __m512i, b: __m512i) -> __m512i { - unsafe { transmute(vpdpbusds(src.as_i32x16(), a.as_i32x16(), b.as_i32x16())) } + unsafe { transmute(vpdpbusds(src.as_i32x16(), a.as_u8x64(), b.as_i8x64())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -468,7 +468,7 @@ pub fn _mm512_maskz_dpbusds_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusds))] pub fn _mm256_dpbusds_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpbusds256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpbusds256(src.as_i32x8(), a.as_u8x32(), b.as_i8x32())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst. @@ -479,7 +479,7 @@ pub fn _mm256_dpbusds_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusds))] pub fn _mm256_dpbusds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpbusds256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpbusds256(src.as_i32x8(), a.as_u8x32(), b.as_i8x32())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -518,7 +518,7 @@ pub fn _mm256_maskz_dpbusds_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m2 #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusds))] pub fn _mm_dpbusds_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpbusds128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpbusds128(src.as_i32x4(), a.as_u8x16(), b.as_i8x16())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst. @@ -529,7 +529,7 @@ pub fn _mm_dpbusds_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusds))] pub fn _mm_dpbusds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpbusds128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpbusds128(src.as_i32x4(), a.as_u8x16(), b.as_i8x16())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -570,7 +570,7 @@ pub fn _mm_maskz_dpbusds_epi32(k: __mmask8, src: __m128i, a: __m128i, b: __m128i #[cfg_attr(test, assert_instr(vpdpbssd))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpbssd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpbssd_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpbssd_128(src.as_i32x4(), a.as_i8x16(), b.as_i8x16())) } } /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding signed 8-bit @@ -583,7 +583,7 @@ pub fn _mm_dpbssd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpbssd))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpbssd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpbssd_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpbssd_256(src.as_i32x8(), a.as_i8x32(), b.as_i8x32())) } } /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding signed 8-bit @@ -596,7 +596,7 @@ pub fn _mm256_dpbssd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vpdpbssds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpbssds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpbssds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpbssds_128(src.as_i32x4(), a.as_i8x16(), b.as_i8x16())) } } /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding signed 8-bit @@ -609,7 +609,7 @@ pub fn _mm_dpbssds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpbssds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpbssds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpbssds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpbssds_256(src.as_i32x8(), a.as_i8x32(), b.as_i8x32())) } } /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding unsigned 8-bit @@ -622,7 +622,7 @@ pub fn _mm256_dpbssds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vpdpbsud))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpbsud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpbsud_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpbsud_128(src.as_i32x4(), a.as_i8x16(), b.as_u8x16())) } } /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding unsigned 8-bit @@ -635,7 +635,7 @@ pub fn _mm_dpbsud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpbsud))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpbsud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpbsud_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpbsud_256(src.as_i32x8(), a.as_i8x32(), b.as_u8x32())) } } /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding unsigned 8-bit @@ -648,7 +648,7 @@ pub fn _mm256_dpbsud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vpdpbsuds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpbsuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpbsuds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpbsuds_128(src.as_i32x4(), a.as_i8x16(), b.as_u8x16())) } } /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding unsigned 8-bit @@ -661,7 +661,7 @@ pub fn _mm_dpbsuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpbsuds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpbsuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpbsuds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpbsuds_256(src.as_i32x8(), a.as_i8x32(), b.as_u8x32())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding unsigned 8-bit @@ -674,7 +674,7 @@ pub fn _mm256_dpbsuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vpdpbuud))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpbuud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpbuud_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpbuud_128(src.as_i32x4(), a.as_u8x16(), b.as_u8x16())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding unsigned 8-bit @@ -687,7 +687,7 @@ pub fn _mm_dpbuud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpbuud))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpbuud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpbuud_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpbuud_256(src.as_i32x8(), a.as_u8x32(), b.as_u8x32())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding unsigned 8-bit @@ -700,7 +700,7 @@ pub fn _mm256_dpbuud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vpdpbuuds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpbuuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpbuuds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpbuuds_128(src.as_i32x4(), a.as_u8x16(), b.as_u8x16())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding unsigned 8-bit @@ -713,7 +713,7 @@ pub fn _mm_dpbuuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpbuuds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpbuuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpbuuds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpbuuds_256(src.as_i32x8(), a.as_u8x32(), b.as_u8x32())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding unsigned 16-bit @@ -726,7 +726,7 @@ pub fn _mm256_dpbuuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vpdpwsud))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpwsud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpwsud_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpwsud_128(src.as_i32x4(), a.as_i16x8(), b.as_u16x8())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding unsigned 16-bit @@ -739,7 +739,7 @@ pub fn _mm_dpwsud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpwsud))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpwsud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpwsud_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpwsud_256(src.as_i32x8(), a.as_i16x16(), b.as_u16x16())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding unsigned 16-bit @@ -752,7 +752,7 @@ pub fn _mm256_dpwsud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vpdpwsuds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpwsuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpwsuds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpwsuds_128(src.as_i32x4(), a.as_i16x8(), b.as_u16x8())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding unsigned 16-bit @@ -765,7 +765,7 @@ pub fn _mm_dpwsuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpwsuds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpwsuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpwsuds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpwsuds_256(src.as_i32x8(), a.as_i16x16(), b.as_u16x16())) } } /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding signed 16-bit @@ -778,7 +778,7 @@ pub fn _mm256_dpwsuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vpdpwusd))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpwusd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpwusd_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpwusd_128(src.as_i32x4(), a.as_u16x8(), b.as_i16x8())) } } /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding signed 16-bit @@ -791,7 +791,7 @@ pub fn _mm_dpwusd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpwusd))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpwusd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpwusd_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpwusd_256(src.as_i32x8(), a.as_u16x16(), b.as_i16x16())) } } /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding signed 16-bit @@ -804,7 +804,7 @@ pub fn _mm256_dpwusd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vpdpwusds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpwusds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpwusds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpwusds_128(src.as_i32x4(), a.as_u16x8(), b.as_i16x8())) } } /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding signed 16-bit @@ -817,7 +817,7 @@ pub fn _mm_dpwusds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpwusds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpwusds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpwusds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpwusds_256(src.as_i32x8(), a.as_u16x16(), b.as_i16x16())) } } /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding unsigned 16-bit @@ -830,7 +830,7 @@ pub fn _mm256_dpwusds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vpdpwuud))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpwuud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpwuud_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpwuud_128(src.as_i32x4(), a.as_u16x8(), b.as_u16x8())) } } /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding unsigned 16-bit @@ -843,7 +843,7 @@ pub fn _mm_dpwuud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpwuud))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpwuud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpwuud_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpwuud_256(src.as_i32x8(), a.as_u16x16(), b.as_u16x16())) } } /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding unsigned 16-bit @@ -856,7 +856,7 @@ pub fn _mm256_dpwuud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vpdpwuuds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpwuuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpwuuds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpwuuds_128(src.as_i32x4(), a.as_u16x8(), b.as_u16x8())) } } /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding unsigned 16-bit @@ -869,98 +869,98 @@ pub fn _mm_dpwuuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpwuuds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpwuuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpwuuds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpwuuds_256(src.as_i32x8(), a.as_u16x16(), b.as_u16x16())) } } #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.avx512.vpdpwssd.512"] - fn vpdpwssd(src: i32x16, a: i32x16, b: i32x16) -> i32x16; + fn vpdpwssd(src: i32x16, a: i16x32, b: i16x32) -> i32x16; #[link_name = "llvm.x86.avx512.vpdpwssd.256"] - fn vpdpwssd256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpwssd256(src: i32x8, a: i16x16, b: i16x16) -> i32x8; #[link_name = "llvm.x86.avx512.vpdpwssd.128"] - fn vpdpwssd128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpwssd128(src: i32x4, a: i16x8, b: i16x8) -> i32x4; #[link_name = "llvm.x86.avx512.vpdpwssds.512"] - fn vpdpwssds(src: i32x16, a: i32x16, b: i32x16) -> i32x16; + fn vpdpwssds(src: i32x16, a: i16x32, b: i16x32) -> i32x16; #[link_name = "llvm.x86.avx512.vpdpwssds.256"] - fn vpdpwssds256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpwssds256(src: i32x8, a: i16x16, b: i16x16) -> i32x8; #[link_name = "llvm.x86.avx512.vpdpwssds.128"] - fn vpdpwssds128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpwssds128(src: i32x4, a: i16x8, b: i16x8) -> i32x4; #[link_name = "llvm.x86.avx512.vpdpbusd.512"] - fn vpdpbusd(src: i32x16, a: i32x16, b: i32x16) -> i32x16; + fn vpdpbusd(src: i32x16, a: u8x64, b: i8x64) -> i32x16; #[link_name = "llvm.x86.avx512.vpdpbusd.256"] - fn vpdpbusd256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpbusd256(src: i32x8, a: u8x32, b: i8x32) -> i32x8; #[link_name = "llvm.x86.avx512.vpdpbusd.128"] - fn vpdpbusd128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpbusd128(src: i32x4, a: u8x16, b: i8x16) -> i32x4; #[link_name = "llvm.x86.avx512.vpdpbusds.512"] - fn vpdpbusds(src: i32x16, a: i32x16, b: i32x16) -> i32x16; + fn vpdpbusds(src: i32x16, a: u8x64, b: i8x64) -> i32x16; #[link_name = "llvm.x86.avx512.vpdpbusds.256"] - fn vpdpbusds256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpbusds256(src: i32x8, a: u8x32, b: i8x32) -> i32x8; #[link_name = "llvm.x86.avx512.vpdpbusds.128"] - fn vpdpbusds128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpbusds128(src: i32x4, a: u8x16, b: i8x16) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpbssd.128"] - fn vpdpbssd_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpbssd_128(src: i32x4, a: i8x16, b: i8x16) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpbssd.256"] - fn vpdpbssd_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpbssd_256(src: i32x8, a: i8x32, b: i8x32) -> i32x8; #[link_name = "llvm.x86.avx2.vpdpbssds.128"] - fn vpdpbssds_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpbssds_128(src: i32x4, a: i8x16, b: i8x16) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpbssds.256"] - fn vpdpbssds_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpbssds_256(src: i32x8, a: i8x32, b: i8x32) -> i32x8; #[link_name = "llvm.x86.avx2.vpdpbsud.128"] - fn vpdpbsud_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpbsud_128(src: i32x4, a: i8x16, b: u8x16) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpbsud.256"] - fn vpdpbsud_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpbsud_256(src: i32x8, a: i8x32, b: u8x32) -> i32x8; #[link_name = "llvm.x86.avx2.vpdpbsuds.128"] - fn vpdpbsuds_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpbsuds_128(src: i32x4, a: i8x16, b: u8x16) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpbsuds.256"] - fn vpdpbsuds_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpbsuds_256(src: i32x8, a: i8x32, b: u8x32) -> i32x8; #[link_name = "llvm.x86.avx2.vpdpbuud.128"] - fn vpdpbuud_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpbuud_128(src: i32x4, a: u8x16, b: u8x16) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpbuud.256"] - fn vpdpbuud_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpbuud_256(src: i32x8, a: u8x32, b: u8x32) -> i32x8; #[link_name = "llvm.x86.avx2.vpdpbuuds.128"] - fn vpdpbuuds_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpbuuds_128(src: i32x4, a: u8x16, b: u8x16) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpbuuds.256"] - fn vpdpbuuds_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpbuuds_256(src: i32x8, a: u8x32, b: u8x32) -> i32x8; #[link_name = "llvm.x86.avx2.vpdpwsud.128"] - fn vpdpwsud_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpwsud_128(src: i32x4, a: i16x8, b: u16x8) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpwsud.256"] - fn vpdpwsud_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpwsud_256(src: i32x8, a: i16x16, b: u16x16) -> i32x8; #[link_name = "llvm.x86.avx2.vpdpwsuds.128"] - fn vpdpwsuds_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpwsuds_128(src: i32x4, a: i16x8, b: u16x8) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpwsuds.256"] - fn vpdpwsuds_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpwsuds_256(src: i32x8, a: i16x16, b: u16x16) -> i32x8; #[link_name = "llvm.x86.avx2.vpdpwusd.128"] - fn vpdpwusd_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpwusd_128(src: i32x4, a: u16x8, b: i16x8) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpwusd.256"] - fn vpdpwusd_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpwusd_256(src: i32x8, a: u16x16, b: i16x16) -> i32x8; #[link_name = "llvm.x86.avx2.vpdpwusds.128"] - fn vpdpwusds_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpwusds_128(src: i32x4, a: u16x8, b: i16x8) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpwusds.256"] - fn vpdpwusds_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpwusds_256(src: i32x8, a: u16x16, b: i16x16) -> i32x8; #[link_name = "llvm.x86.avx2.vpdpwuud.128"] - fn vpdpwuud_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpwuud_128(src: i32x4, a: u16x8, b: u16x8) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpwuud.256"] - fn vpdpwuud_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpwuud_256(src: i32x8, a: u16x16, b: u16x16) -> i32x8; #[link_name = "llvm.x86.avx2.vpdpwuuds.128"] - fn vpdpwuuds_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpwuuds_128(src: i32x4, a: u16x8, b: u16x8) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpwuuds.256"] - fn vpdpwuuds_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpwuuds_256(src: i32x8, a: u16x16, b: u16x16) -> i32x8; } #[cfg(test)] diff --git a/library/stdarch/crates/core_arch/src/x86/avx512vp2intersect.rs b/library/stdarch/crates/core_arch/src/x86/avx512vp2intersect.rs new file mode 100644 index 0000000000000..30fcfce63ccf4 --- /dev/null +++ b/library/stdarch/crates/core_arch/src/x86/avx512vp2intersect.rs @@ -0,0 +1,244 @@ +//! Vector Pair Intersection to a Pair of Mask Registers (VP2INTERSECT) + +use crate::core_arch::{simd::*, x86::*}; + +#[cfg(test)] +use stdarch_test::assert_instr; + +/// Compute intersection of packed 32-bit integer vectors a and b, +/// and store indication of match in the corresponding bit of two mask registers +/// specified by k1 and k2. A match in corresponding elements of a and b is +/// indicated by a set bit in the corresponding bit of the mask registers. +/// +/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_2intersect_epi32&expand=0) +#[inline] +#[target_feature(enable = "avx512vp2intersect,avx512vl")] +#[unstable(feature = "stdarch_x86_avx512vp2intersect", issue = "111137")] +#[cfg_attr(test, assert_instr(vp2intersectd))] +pub unsafe fn _mm_2intersect_epi32(a: __m128i, b: __m128i, k1: *mut __mmask8, k2: *mut __mmask8) { + (*k1, *k2) = vp2intersectd_128(a.as_i32x4(), b.as_i32x4()); +} + +/// Compute intersection of packed 64-bit integer vectors a and b, +/// and store indication of match in the corresponding bit of two mask registers +/// specified by k1 and k2. A match in corresponding elements of a and b is +/// indicated by a set bit in the corresponding bit of the mask registers. +/// +/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_2intersect_epi64&expand=0) +#[inline] +#[target_feature(enable = "avx512vp2intersect,avx512vl")] +#[unstable(feature = "stdarch_x86_avx512vp2intersect", issue = "111137")] +#[cfg_attr(test, assert_instr(vp2intersectq))] +pub unsafe fn _mm_2intersect_epi64(a: __m128i, b: __m128i, k1: *mut __mmask8, k2: *mut __mmask8) { + (*k1, *k2) = vp2intersectq_128(a.as_i64x2(), b.as_i64x2()); +} + +/// Compute intersection of packed 32-bit integer vectors a and b, +/// and store indication of match in the corresponding bit of two mask registers +/// specified by k1 and k2. A match in corresponding elements of a and b is +/// indicated by a set bit in the corresponding bit of the mask registers. +/// +/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_2intersect_epi32&expand=0) +#[inline] +#[target_feature(enable = "avx512vp2intersect,avx512vl")] +#[unstable(feature = "stdarch_x86_avx512vp2intersect", issue = "111137")] +#[cfg_attr(test, assert_instr(vp2intersectd))] +pub unsafe fn _mm256_2intersect_epi32( + a: __m256i, + b: __m256i, + k1: *mut __mmask8, + k2: *mut __mmask8, +) { + (*k1, *k2) = vp2intersectd_256(a.as_i32x8(), b.as_i32x8()); +} + +/// Compute intersection of packed 64-bit integer vectors a and b, +/// and store indication of match in the corresponding bit of two mask registers +/// specified by k1 and k2. A match in corresponding elements of a and b is +/// indicated by a set bit in the corresponding bit of the mask registers. +/// +/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_2intersect_epi64&expand=0) +#[inline] +#[target_feature(enable = "avx512vp2intersect,avx512vl")] +#[unstable(feature = "stdarch_x86_avx512vp2intersect", issue = "111137")] +#[cfg_attr(test, assert_instr(vp2intersectq))] +pub unsafe fn _mm256_2intersect_epi64( + a: __m256i, + b: __m256i, + k1: *mut __mmask8, + k2: *mut __mmask8, +) { + (*k1, *k2) = vp2intersectq_256(a.as_i64x4(), b.as_i64x4()); +} + +/// Compute intersection of packed 32-bit integer vectors a and b, +/// and store indication of match in the corresponding bit of two mask registers +/// specified by k1 and k2. A match in corresponding elements of a and b is +/// indicated by a set bit in the corresponding bit of the mask registers. +/// +/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_2intersect_epi32&expand=0) +#[inline] +#[target_feature(enable = "avx512vp2intersect,avx512f")] +#[unstable(feature = "stdarch_x86_avx512vp2intersect", issue = "111137")] +#[cfg_attr(test, assert_instr(vp2intersectd))] +pub unsafe fn _mm512_2intersect_epi32( + a: __m512i, + b: __m512i, + k1: *mut __mmask16, + k2: *mut __mmask16, +) { + (*k1, *k2) = vp2intersectd_512(a.as_i32x16(), b.as_i32x16()); +} + +/// Compute intersection of packed 64-bit integer vectors a and b, +/// and store indication of match in the corresponding bit of two mask registers +/// specified by k1 and k2. A match in corresponding elements of a and b is +/// indicated by a set bit in the corresponding bit of the mask registers. +/// +/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_2intersect_epi64&expand=0) +#[inline] +#[target_feature(enable = "avx512vp2intersect,avx512f")] +#[unstable(feature = "stdarch_x86_avx512vp2intersect", issue = "111137")] +#[cfg_attr(test, assert_instr(vp2intersectq))] +pub unsafe fn _mm512_2intersect_epi64( + a: __m512i, + b: __m512i, + k1: *mut __mmask8, + k2: *mut __mmask8, +) { + (*k1, *k2) = vp2intersectq_512(a.as_i64x8(), b.as_i64x8()); +} + +#[allow(improper_ctypes)] +unsafe extern "unadjusted" { + #[link_name = "llvm.x86.avx512.vp2intersect.d.128"] + fn vp2intersectd_128(a: i32x4, b: i32x4) -> (u8, u8); + #[link_name = "llvm.x86.avx512.vp2intersect.q.128"] + fn vp2intersectq_128(a: i64x2, b: i64x2) -> (u8, u8); + + #[link_name = "llvm.x86.avx512.vp2intersect.d.256"] + fn vp2intersectd_256(a: i32x8, b: i32x8) -> (u8, u8); + #[link_name = "llvm.x86.avx512.vp2intersect.q.256"] + fn vp2intersectq_256(a: i64x4, b: i64x4) -> (u8, u8); + + #[link_name = "llvm.x86.avx512.vp2intersect.d.512"] + fn vp2intersectd_512(a: i32x16, b: i32x16) -> (u16, u16); + #[link_name = "llvm.x86.avx512.vp2intersect.q.512"] + fn vp2intersectq_512(a: i64x8, b: i64x8) -> (u8, u8); +} + +#[cfg(test)] +mod tests { + use crate::core_arch::x86::*; + use stdarch_test::simd_test; + + #[simd_test(enable = "avx512vp2intersect,avx512vl")] + unsafe fn test_mm_2intersect_epi32() { + let mut k1 = 0; + let mut k2 = 0; + + let a = _mm_set_epi32(1, 2, 3, 4); + let b = _mm_set_epi32(3, 4, 5, 6); + _mm_2intersect_epi32(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b0011); + assert_eq!(k2, 0b1100); + + let a = _mm_set_epi32(1, 2, 3, 4); + let b = _mm_set_epi32(2, 3, 4, 5); + _mm_2intersect_epi32(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b0111); + assert_eq!(k2, 0b1110); + } + + #[simd_test(enable = "avx512vp2intersect,avx512vl")] + unsafe fn test_mm_2intersect_epi64() { + let mut k1 = 0; + let mut k2 = 0; + + let a = _mm_set_epi64x(1, 2); + let b = _mm_set_epi64x(2, 3); + _mm_2intersect_epi64(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b01); + assert_eq!(k2, 0b10); + + let a = _mm_set_epi64x(1, 2); + let b = _mm_set_epi64x(2, 2); + _mm_2intersect_epi64(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b01); + assert_eq!(k2, 0b11); + } + + #[simd_test(enable = "avx512vp2intersect,avx512vl")] + unsafe fn test_mm256_2intersect_epi32() { + let mut k1 = 0; + let mut k2 = 0; + + let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8); + let b = _mm256_set_epi32(5, 6, 7, 8, 9, 10, 11, 12); + _mm256_2intersect_epi32(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b00001111); + assert_eq!(k2, 0b11110000); + + let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8); + let b = _mm256_set_epi32(2, 3, 4, 5, 6, 7, 8, 9); + _mm256_2intersect_epi32(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b01111111); + assert_eq!(k2, 0b11111110); + } + + #[simd_test(enable = "avx512vp2intersect,avx512vl")] + unsafe fn test_mm256_2intersect_epi64() { + let mut k1 = 0; + let mut k2 = 0; + + let a = _mm256_set_epi64x(1, 2, 3, 4); + let b = _mm256_set_epi64x(3, 4, 5, 6); + _mm256_2intersect_epi64(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b0011); + assert_eq!(k2, 0b1100); + + let a = _mm256_set_epi64x(1, 2, 3, 4); + let b = _mm256_set_epi64x(2, 3, 4, 5); + _mm256_2intersect_epi64(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b0111); + assert_eq!(k2, 0b1110); + } + + #[simd_test(enable = "avx512vp2intersect,avx512f")] + unsafe fn test_mm512_2intersect_epi32() { + let mut k1 = 0; + let mut k2 = 0; + + let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); + let b = _mm512_set_epi32( + 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + ); + _mm512_2intersect_epi32(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b0000000011111111); + assert_eq!(k2, 0b1111111100000000); + + let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); + let b = _mm512_set_epi32(2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17); + _mm512_2intersect_epi32(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b0111111111111111); + assert_eq!(k2, 0b1111111111111110); + } + + #[simd_test(enable = "avx512vp2intersect,avx512f")] + unsafe fn test_mm512_2intersect_epi64() { + let mut k1 = 0; + let mut k2 = 0; + + let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8); + let b = _mm512_set_epi64(5, 6, 7, 8, 9, 10, 11, 12); + _mm512_2intersect_epi64(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b00001111); + assert_eq!(k2, 0b11110000); + + let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8); + let b = _mm512_set_epi64(2, 3, 4, 5, 6, 7, 8, 9); + _mm512_2intersect_epi64(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b01111111); + assert_eq!(k2, 0b11111110); + } +} diff --git a/library/stdarch/crates/core_arch/src/x86/avxneconvert.rs b/library/stdarch/crates/core_arch/src/x86/avxneconvert.rs index 91b6be2b09d78..b17d3de48b595 100644 --- a/library/stdarch/crates/core_arch/src/x86/avxneconvert.rs +++ b/library/stdarch/crates/core_arch/src/x86/avxneconvert.rs @@ -1,4 +1,3 @@ -use crate::arch::asm; use crate::core_arch::x86::*; #[cfg(test)] @@ -87,7 +86,7 @@ pub unsafe fn _mm256_cvtneebf16_ps(a: *const __m256bh) -> __m256 { #[inline] #[target_feature(enable = "avxneconvert")] #[cfg_attr(test, assert_instr(vcvtneeph2ps))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub unsafe fn _mm_cvtneeph_ps(a: *const __m128h) -> __m128 { transmute(cvtneeph2ps_128(a)) } @@ -99,7 +98,7 @@ pub unsafe fn _mm_cvtneeph_ps(a: *const __m128h) -> __m128 { #[inline] #[target_feature(enable = "avxneconvert")] #[cfg_attr(test, assert_instr(vcvtneeph2ps))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub unsafe fn _mm256_cvtneeph_ps(a: *const __m256h) -> __m256 { transmute(cvtneeph2ps_256(a)) } @@ -135,7 +134,7 @@ pub unsafe fn _mm256_cvtneobf16_ps(a: *const __m256bh) -> __m256 { #[inline] #[target_feature(enable = "avxneconvert")] #[cfg_attr(test, assert_instr(vcvtneoph2ps))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub unsafe fn _mm_cvtneoph_ps(a: *const __m128h) -> __m128 { transmute(cvtneoph2ps_128(a)) } @@ -147,7 +146,7 @@ pub unsafe fn _mm_cvtneoph_ps(a: *const __m128h) -> __m128 { #[inline] #[target_feature(enable = "avxneconvert")] #[cfg_attr(test, assert_instr(vcvtneoph2ps))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub unsafe fn _mm256_cvtneoph_ps(a: *const __m256h) -> __m256 { transmute(cvtneoph2ps_256(a)) } @@ -161,16 +160,7 @@ pub unsafe fn _mm256_cvtneoph_ps(a: *const __m256h) -> __m256 { #[cfg_attr(test, assert_instr(vcvtneps2bf16))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_cvtneps_avx_pbh(a: __m128) -> __m128bh { - unsafe { - let mut dst: __m128bh; - asm!( - "{{vex}}vcvtneps2bf16 {dst},{src}", - dst = lateout(xmm_reg) dst, - src = in(xmm_reg) a, - options(pure, nomem, nostack, preserves_flags) - ); - dst - } + unsafe { vcvtneps2bf16_128(a) } } /// Convert packed single precision (32-bit) floating-point elements in a to packed BF16 (16-bit) floating-point @@ -182,20 +172,11 @@ pub fn _mm_cvtneps_avx_pbh(a: __m128) -> __m128bh { #[cfg_attr(test, assert_instr(vcvtneps2bf16))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_cvtneps_avx_pbh(a: __m256) -> __m128bh { - unsafe { - let mut dst: __m128bh; - asm!( - "{{vex}}vcvtneps2bf16 {dst},{src}", - dst = lateout(xmm_reg) dst, - src = in(ymm_reg) a, - options(pure, nomem, nostack, preserves_flags) - ); - dst - } + unsafe { vcvtneps2bf16_256(a) } } #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.vbcstnebf162ps128"] fn bcstnebf162ps_128(a: *const bf16) -> __m128; #[link_name = "llvm.x86.vbcstnebf162ps256"] @@ -222,6 +203,11 @@ unsafe extern "C" { fn cvtneoph2ps_128(a: *const __m128h) -> __m128; #[link_name = "llvm.x86.vcvtneoph2ps256"] fn cvtneoph2ps_256(a: *const __m256h) -> __m256; + + #[link_name = "llvm.x86.vcvtneps2bf16128"] + fn vcvtneps2bf16_128(a: __m128) -> __m128bh; + #[link_name = "llvm.x86.vcvtneps2bf16256"] + fn vcvtneps2bf16_256(a: __m256) -> __m128bh; } #[cfg(test)] diff --git a/library/stdarch/crates/core_arch/src/x86/bmi1.rs b/library/stdarch/crates/core_arch/src/x86/bmi1.rs index 432051abd1cfa..ccacd34f3ca01 100644 --- a/library/stdarch/crates/core_arch/src/x86/bmi1.rs +++ b/library/stdarch/crates/core_arch/src/x86/bmi1.rs @@ -60,7 +60,7 @@ pub const fn _andn_u32(a: u32, b: u32) -> u32 { #[stable(feature = "simd_x86", since = "1.27.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _blsi_u32(x: u32) -> u32 { - x & x.wrapping_neg() + x.isolate_lowest_one() } /// Gets mask up to lowest set bit. @@ -131,7 +131,7 @@ pub const fn _mm_tzcnt_32(x: u32) -> i32 { x.trailing_zeros() as i32 } -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.bmi.bextr.32"] fn x86_bmi_bextr_32(x: u32, y: u32) -> u32; } diff --git a/library/stdarch/crates/core_arch/src/x86/bmi2.rs b/library/stdarch/crates/core_arch/src/x86/bmi2.rs index 5320640d96873..dae4133d63bec 100644 --- a/library/stdarch/crates/core_arch/src/x86/bmi2.rs +++ b/library/stdarch/crates/core_arch/src/x86/bmi2.rs @@ -67,7 +67,7 @@ pub fn _pext_u32(a: u32, mask: u32) -> u32 { unsafe { x86_bmi2_pext_32(a, mask) } } -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.bmi.bzhi.32"] fn x86_bmi2_bzhi_32(x: u32, y: u32) -> u32; #[link_name = "llvm.x86.bmi.pdep.32"] diff --git a/library/stdarch/crates/core_arch/src/x86/clflushopt.rs b/library/stdarch/crates/core_arch/src/x86/clflushopt.rs new file mode 100644 index 0000000000000..07d5a9c27fb56 --- /dev/null +++ b/library/stdarch/crates/core_arch/src/x86/clflushopt.rs @@ -0,0 +1,51 @@ +//! `CLFLUSHOPT` cache-line flush. + +#[cfg(test)] +use stdarch_test::assert_instr; + +#[allow(improper_ctypes)] +unsafe extern "unadjusted" { + #[link_name = "llvm.x86.clflushopt"] + fn clflushopt(p: *const u8); +} + +/// Invalidates from every level of the cache hierarchy the cache line that +/// contains `p`. +/// +/// Unlike [`_mm_clflush`], `CLFLUSHOPT` is only ordered with respect to older +/// writes to the flushed cache line and with respect to fence/locked +/// operations; it is *not* serialized against other `CLFLUSHOPT`/`CLFLUSH` +/// instructions or unrelated stores. This makes flushing a range of lines +/// substantially faster, but a fence (e.g. [`_mm_sfence`] or [`_mm_mfence`]) is +/// required afterward to order the flushes against subsequent operations. +/// +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_clflushopt) +/// +/// # Safety +/// +/// Unlike the prefetch intrinsics, `CLFLUSHOPT` is subject to all the +/// permission checking and faults associated with a byte load, so `p` must +/// point to a byte that is valid for reads. +/// +/// [`_mm_clflush`]: crate::arch::x86::_mm_clflush +/// [`_mm_sfence`]: crate::arch::x86::_mm_sfence +/// [`_mm_mfence`]: crate::arch::x86::_mm_mfence +#[inline] +#[target_feature(enable = "clflushopt")] +#[cfg_attr(test, assert_instr(clflushopt))] +#[unstable(feature = "simd_x86_clflushopt", issue = "157096")] +pub unsafe fn _mm_clflushopt(p: *const u8) { + clflushopt(p); +} + +#[cfg(test)] +mod tests { + use crate::core_arch::x86::*; + use stdarch_test::simd_test; + + #[simd_test(enable = "clflushopt")] + unsafe fn test_mm_clflushopt() { + let x = 0_u8; + _mm_clflushopt(core::ptr::addr_of!(x)); + } +} diff --git a/library/stdarch/crates/core_arch/src/x86/f16c.rs b/library/stdarch/crates/core_arch/src/x86/f16c.rs index a0bb992bb9d4c..62a9f002ab1f3 100644 --- a/library/stdarch/crates/core_arch/src/x86/f16c.rs +++ b/library/stdarch/crates/core_arch/src/x86/f16c.rs @@ -56,10 +56,10 @@ pub const fn _mm256_cvtph_ps(a: __m128i) -> __m256 { /// /// Rounding is done according to the `imm_rounding` parameter, which can be one of: /// -/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions -/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions -/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions -/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions +/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest +/// * [`_MM_FROUND_TO_NEG_INF`] : round down +/// * [`_MM_FROUND_TO_POS_INF`] : round up +/// * [`_MM_FROUND_TO_ZERO`] : truncate /// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`] /// /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtps_ph) @@ -69,7 +69,7 @@ pub const fn _mm256_cvtph_ps(a: __m128i) -> __m256 { #[rustc_legacy_const_generics(1)] #[stable(feature = "x86_f16c_intrinsics", since = "1.68.0")] pub fn _mm_cvtps_ph(a: __m128) -> __m128i { - static_assert_uimm_bits!(IMM_ROUNDING, 3); + static_assert_round_mode!(IMM_ROUNDING); unsafe { let a = a.as_f32x4(); let r = llvm_vcvtps2ph_128(a, IMM_ROUNDING); @@ -82,10 +82,10 @@ pub fn _mm_cvtps_ph(a: __m128) -> __m128i { /// /// Rounding is done according to the `imm_rounding` parameter, which can be one of: /// -/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions -/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions -/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions -/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions +/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest +/// * [`_MM_FROUND_TO_NEG_INF`] : round down +/// * [`_MM_FROUND_TO_POS_INF`] : round up +/// * [`_MM_FROUND_TO_ZERO`] : truncate /// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`] /// /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtps_ph) @@ -95,7 +95,7 @@ pub fn _mm_cvtps_ph(a: __m128) -> __m128i { #[rustc_legacy_const_generics(1)] #[stable(feature = "x86_f16c_intrinsics", since = "1.68.0")] pub fn _mm256_cvtps_ph(a: __m256) -> __m128i { - static_assert_uimm_bits!(IMM_ROUNDING, 3); + static_assert_round_mode!(IMM_ROUNDING); unsafe { let a = a.as_f32x8(); let r = llvm_vcvtps2ph_256(a, IMM_ROUNDING); diff --git a/library/stdarch/crates/core_arch/src/x86/fxsr.rs b/library/stdarch/crates/core_arch/src/x86/fxsr.rs index 08619efe7c9ef..74a95e192a3af 100644 --- a/library/stdarch/crates/core_arch/src/x86/fxsr.rs +++ b/library/stdarch/crates/core_arch/src/x86/fxsr.rs @@ -4,7 +4,7 @@ use stdarch_test::assert_instr; #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.fxsave"] fn fxsave(p: *mut u8); #[link_name = "llvm.x86.fxrstor"] diff --git a/library/stdarch/crates/core_arch/src/x86/gfni.rs b/library/stdarch/crates/core_arch/src/x86/gfni.rs index e9ee27a7b823b..8cebd04a4b836 100644 --- a/library/stdarch/crates/core_arch/src/x86/gfni.rs +++ b/library/stdarch/crates/core_arch/src/x86/gfni.rs @@ -23,7 +23,7 @@ use crate::mem::transmute; use stdarch_test::assert_instr; #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.vgf2p8affineinvqb.512"] fn vgf2p8affineinvqb_512(x: i8x64, a: i8x64, imm8: u8) -> i8x64; #[link_name = "llvm.x86.vgf2p8affineinvqb.256"] diff --git a/library/stdarch/crates/core_arch/src/x86/macros.rs b/library/stdarch/crates/core_arch/src/x86/macros.rs index 9b9c24a447ec7..739abbeb01c37 100644 --- a/library/stdarch/crates/core_arch/src/x86/macros.rs +++ b/library/stdarch/crates/core_arch/src/x86/macros.rs @@ -1,5 +1,14 @@ //! Utility macros. +// Helper macro used to trigger const eval errors when the const generic immediate value `imm` is +// not a round number. +#[allow(unused)] +macro_rules! static_assert_round_mode { + ($imm:ident) => { + static_assert!($imm >= 0 && $imm < 5, "Invalid IMM value") + }; +} + // Helper macro used to trigger const eval errors when the const generic immediate value `imm` is // not a round number. #[allow(unused)] diff --git a/library/stdarch/crates/core_arch/src/x86/mod.rs b/library/stdarch/crates/core_arch/src/x86/mod.rs index c40fbd3ca3178..e6875a628fbf0 100644 --- a/library/stdarch/crates/core_arch/src/x86/mod.rs +++ b/library/stdarch/crates/core_arch/src/x86/mod.rs @@ -40,12 +40,12 @@ types! { /// # Examples /// /// ``` + /// # #[cfg(any(target_arch = "x86", target_arch = "x86_64"))] { /// #[cfg(target_arch = "x86")] /// use std::arch::x86::*; /// #[cfg(target_arch = "x86_64")] /// use std::arch::x86_64::*; /// - /// # fn main() { /// # #[target_feature(enable = "sse2")] /// # #[allow(unused_unsafe)] // temporary, to unstick CI /// # unsafe fn foo() { unsafe { @@ -56,6 +56,7 @@ types! { /// # if is_x86_feature_detected!("sse2") { unsafe { foo() } } /// # } /// ``` + #[doc(cfg(any(target_arch = "x86", target_arch = "x86_64")))] pub struct __m128i(2 x i64); /// 128-bit wide set of four `f32` types, x86-specific @@ -83,12 +84,12 @@ types! { /// # Examples /// /// ``` + /// # #[cfg(any(target_arch = "x86", target_arch = "x86_64"))] { /// #[cfg(target_arch = "x86")] /// use std::arch::x86::*; /// #[cfg(target_arch = "x86_64")] /// use std::arch::x86_64::*; /// - /// # fn main() { /// # #[target_feature(enable = "sse")] /// # #[allow(unused_unsafe)] // temporary, to unstick CI /// # unsafe fn foo() { unsafe { @@ -99,6 +100,7 @@ types! { /// # if is_x86_feature_detected!("sse") { unsafe { foo() } } /// # } /// ``` + #[doc(cfg(any(target_arch = "x86", target_arch = "x86_64")))] pub struct __m128(4 x f32); /// 128-bit wide set of two `f64` types, x86-specific @@ -126,12 +128,12 @@ types! { /// # Examples /// /// ``` + /// # #[cfg(any(target_arch = "x86", target_arch = "x86_64"))] { /// #[cfg(target_arch = "x86")] /// use std::arch::x86::*; /// #[cfg(target_arch = "x86_64")] /// use std::arch::x86_64::*; /// - /// # fn main() { /// # #[target_feature(enable = "sse2")] /// # #[allow(unused_unsafe)] // temporary, to unstick CI /// # unsafe fn foo() { unsafe { @@ -142,6 +144,7 @@ types! { /// # if is_x86_feature_detected!("sse2") { unsafe { foo() } } /// # } /// ``` + #[doc(cfg(any(target_arch = "x86", target_arch = "x86_64")))] pub struct __m128d(2 x f64); /// 256-bit wide integer vector type, x86-specific @@ -173,12 +176,12 @@ types! { /// # Examples /// /// ``` + /// # #[cfg(any(target_arch = "x86", target_arch = "x86_64"))] { /// #[cfg(target_arch = "x86")] /// use std::arch::x86::*; /// #[cfg(target_arch = "x86_64")] /// use std::arch::x86_64::*; /// - /// # fn main() { /// # #[target_feature(enable = "avx")] /// # #[allow(unused_unsafe)] // temporary, to unstick CI /// # unsafe fn foo() { unsafe { @@ -189,6 +192,7 @@ types! { /// # if is_x86_feature_detected!("avx") { unsafe { foo() } } /// # } /// ``` + #[doc(cfg(any(target_arch = "x86", target_arch = "x86_64")))] pub struct __m256i(4 x i64); /// 256-bit wide set of eight `f32` types, x86-specific @@ -216,12 +220,12 @@ types! { /// # Examples /// /// ``` + /// # #[cfg(any(target_arch = "x86", target_arch = "x86_64"))] { /// #[cfg(target_arch = "x86")] /// use std::arch::x86::*; /// #[cfg(target_arch = "x86_64")] /// use std::arch::x86_64::*; /// - /// # fn main() { /// # #[target_feature(enable = "avx")] /// # #[allow(unused_unsafe)] // temporary, to unstick CI /// # unsafe fn foo() { unsafe { @@ -232,6 +236,7 @@ types! { /// # if is_x86_feature_detected!("avx") { unsafe { foo() } } /// # } /// ``` + #[doc(cfg(any(target_arch = "x86", target_arch = "x86_64")))] pub struct __m256(8 x f32); /// 256-bit wide set of four `f64` types, x86-specific @@ -259,12 +264,12 @@ types! { /// # Examples /// /// ``` + /// # #[cfg(any(target_arch = "x86", target_arch = "x86_64"))] { /// #[cfg(target_arch = "x86")] /// use std::arch::x86::*; /// #[cfg(target_arch = "x86_64")] /// use std::arch::x86_64::*; /// - /// # fn main() { /// # #[target_feature(enable = "avx")] /// # #[allow(unused_unsafe)] // temporary, to unstick CI /// # unsafe fn foo() { unsafe { @@ -275,6 +280,7 @@ types! { /// # if is_x86_feature_detected!("avx") { unsafe { foo() } } /// # } /// ``` + #[doc(cfg(any(target_arch = "x86", target_arch = "x86_64")))] pub struct __m256d(4 x f64); } @@ -401,7 +407,7 @@ types! { } types! { - #![stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] + #![stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] /// 128-bit wide set of 8 `f16` types, x86-specific /// @@ -692,6 +698,10 @@ mod adx; #[stable(feature = "simd_x86_adx", since = "1.33.0")] pub use self::adx::*; +mod clflushopt; +#[unstable(feature = "simd_x86_clflushopt", issue = "157096")] +pub use self::clflushopt::*; + #[cfg(test)] use stdarch_test::assert_instr; @@ -768,9 +778,17 @@ mod avxneconvert; pub use self::avxneconvert::*; mod avx512fp16; -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub use self::avx512fp16::*; mod kl; #[stable(feature = "keylocker_x86", since = "1.89.0")] pub use self::kl::*; + +mod movrs; +#[unstable(feature = "movrs_target_feature", issue = "137976")] +pub use self::movrs::*; + +mod avx512vp2intersect; +#[unstable(feature = "stdarch_x86_avx512vp2intersect", issue = "111137")] +pub use self::avx512vp2intersect::*; diff --git a/library/stdarch/crates/core_arch/src/x86/movrs.rs b/library/stdarch/crates/core_arch/src/x86/movrs.rs new file mode 100644 index 0000000000000..d5f4d146c44aa --- /dev/null +++ b/library/stdarch/crates/core_arch/src/x86/movrs.rs @@ -0,0 +1,23 @@ +//! Read-shared move intrinsics + +#[cfg(test)] +use stdarch_test::assert_instr; + +unsafe extern "unadjusted" { + #[link_name = "llvm.x86.prefetchrs"] + fn prefetchrs(p: *const u8); +} + +/// Prefetches the cache line that contains address `p`, with an indication that the source memory +/// location is likely to become read-shared by multiple processors, i.e., read in the future by at +/// least one other processor before it is written, assuming it is ever written in the future. +/// +/// Note: this intrinsic is safe to use even though it takes a raw pointer argument. In general, this +/// cannot change the behavior of the program, including not trapping on invalid pointers. +#[inline] +#[target_feature(enable = "movrs")] +#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(prefetchrst2))] +#[unstable(feature = "movrs_target_feature", issue = "137976")] +pub fn _m_prefetchrs(p: *const u8) { + unsafe { prefetchrs(p) } +} diff --git a/library/stdarch/crates/core_arch/src/x86/pclmulqdq.rs b/library/stdarch/crates/core_arch/src/x86/pclmulqdq.rs index 0f2769257f958..454785c5e0c89 100644 --- a/library/stdarch/crates/core_arch/src/x86/pclmulqdq.rs +++ b/library/stdarch/crates/core_arch/src/x86/pclmulqdq.rs @@ -11,7 +11,7 @@ use crate::core_arch::x86::__m128i; use stdarch_test::assert_instr; #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.pclmulqdq"] fn pclmulqdq(a: __m128i, round_key: __m128i, imm8: u8) -> __m128i; } diff --git a/library/stdarch/crates/core_arch/src/x86/rtm.rs b/library/stdarch/crates/core_arch/src/x86/rtm.rs index c88bd6592d784..f09b95d76bdb3 100644 --- a/library/stdarch/crates/core_arch/src/x86/rtm.rs +++ b/library/stdarch/crates/core_arch/src/x86/rtm.rs @@ -16,7 +16,7 @@ #[cfg(test)] use stdarch_test::assert_instr; -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.xbegin"] fn x86_xbegin() -> i32; #[link_name = "llvm.x86.xend"] diff --git a/library/stdarch/crates/core_arch/src/x86/sha.rs b/library/stdarch/crates/core_arch/src/x86/sha.rs index f8a3295d19589..f7d8c3c0b2408 100644 --- a/library/stdarch/crates/core_arch/src/x86/sha.rs +++ b/library/stdarch/crates/core_arch/src/x86/sha.rs @@ -1,7 +1,7 @@ use crate::core_arch::{simd::*, x86::*}; #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.sha1msg1"] fn sha1msg1(a: i32x4, b: i32x4) -> i32x4; #[link_name = "llvm.x86.sha1msg2"] diff --git a/library/stdarch/crates/core_arch/src/x86/sse.rs b/library/stdarch/crates/core_arch/src/x86/sse.rs index b83274e60e72a..e31175d48cf94 100644 --- a/library/stdarch/crates/core_arch/src/x86/sse.rs +++ b/library/stdarch/crates/core_arch/src/x86/sse.rs @@ -208,7 +208,7 @@ pub fn _mm_min_ss(a: __m128, b: __m128) -> __m128 { #[cfg_attr(test, assert_instr(minps))] #[stable(feature = "simd_x86", since = "1.27.0")] pub fn _mm_min_ps(a: __m128, b: __m128) -> __m128 { - // See the `test_mm_min_ps` test why this can't be implemented using `simd_fmin`. + // See the `test_mm_min_ps` test why this can't be implemented using `simd_minimum_number_nsz`. unsafe { minps(a, b) } } @@ -234,7 +234,7 @@ pub fn _mm_max_ss(a: __m128, b: __m128) -> __m128 { #[cfg_attr(test, assert_instr(maxps))] #[stable(feature = "simd_x86", since = "1.27.0")] pub fn _mm_max_ps(a: __m128, b: __m128) -> __m128 { - // See the `test_mm_min_ps` test why this can't be implemented using `simd_fmax`. + // See the `test_mm_min_ps` test why this can't be implemented using `simd_maximum_number_nsz`. unsafe { maxps(a, b) } } @@ -968,7 +968,7 @@ pub const fn _mm_set_ps1(a: f32) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set_ps) #[inline] #[target_feature(enable = "sse")] -#[cfg_attr(test, assert_instr(unpcklps))] +// This intrinsic has no corresponding instruction. #[stable(feature = "simd_x86", since = "1.27.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_set_ps(a: f32, b: f32, c: f32, d: f32) -> __m128 { @@ -1987,7 +1987,7 @@ pub const fn _MM_TRANSPOSE4_PS( } #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.sse.rcp.ss"] fn rcpss(a: __m128) -> __m128; #[link_name = "llvm.x86.sse.rcp.ps"] @@ -2040,7 +2040,7 @@ unsafe extern "C" { fn stmxcsr(p: *mut i8); #[link_name = "llvm.x86.sse.ldmxcsr"] fn ldmxcsr(p: *const i8); - #[link_name = "llvm.prefetch"] + #[link_name = "llvm.prefetch.p0"] fn prefetch(p: *const i8, rw: i32, loc: i32, ty: i32); #[link_name = "llvm.x86.sse.cmp.ss"] fn cmpss(a: __m128, b: __m128, imm8: i8) -> __m128; @@ -2227,11 +2227,11 @@ mod tests { let r = _mm_min_ps(a, b); assert_eq_m128(r, _mm_setr_ps(-100.0, 5.0, 0.0, -10.0)); - // `_mm_min_ps` can **not** be implemented using the `simd_min` rust intrinsic. `simd_min` - // is lowered by the llvm codegen backend to `llvm.minnum.v*` llvm intrinsic. This intrinsic - // doesn't specify how -0.0 is handled. Unfortunately it happens to behave different from - // the `minps` x86 instruction on x86. The `llvm.minnum.v*` llvm intrinsic equals - // `r1` to `a` and `r2` to `b`. + // `_mm_min_ps` can **not** be implemented using the `simd_minimum_number_nsz` rust + // intrinsic. That intrinsic is lowered by the llvm codegen backend to `llvm.minimumnum.v*` + // llvm intrinsic with the `nsz` attribute. The `nsz` attribute means -0.0 is handled + // non-deterministically. The `minps` x86 instruction however has a deterministic semantics + // for signed zeros. let a = _mm_setr_ps(-0.0, 0.0, 0.0, 0.0); let b = _mm_setr_ps(0.0, 0.0, 0.0, 0.0); let r1 = _mm_min_ps(a, b).as_f32x4().to_bits(); @@ -2816,14 +2816,32 @@ mod tests { let aa = &[3.0f32, 12.0, 23.0, NAN]; let bb = &[3.0f32, 47.5, 1.5, NAN]; - let ee = &[1i32, 0, 1, 0]; + let ee = &[0i32, 0, 1, 0]; for i in 0..4 { let a = _mm_setr_ps(aa[i], 1.0, 2.0, 3.0); let b = _mm_setr_ps(bb[i], 0.0, 2.0, 4.0); - let r = _mm_comige_ss(a, b); + let r = _mm_comigt_ss(a, b); + + assert_eq!( + ee[i], r, + "_mm_comigt_ss({:?}, {:?}) = {}, expected: {} (i={})", + a, b, r, ee[i], i + ); + } + } + + #[simd_test(enable = "sse")] + fn test_mm_comige_ss() { + let aa = &[3.0f32, 23.0, 12.0, NAN]; + let bb = &[3.0f32, 1.5, 47.5, NAN]; + let ee = &[1i32, 1, 0, 0]; + for i in 0..4 { + let a = _mm_setr_ps(aa[i], 1.0, 2.0, 3.0); + let b = _mm_setr_ps(bb[i], 0.0, 2.0, 4.0); + let r = _mm_comige_ss(a, b); assert_eq!( ee[i], r, "_mm_comige_ss({:?}, {:?}) = {}, expected: {} (i={})", @@ -2979,66 +2997,87 @@ mod tests { } } + macro_rules! test_mm_cvtss_si32_impl { + ($alias:ident) => { + let inputs = &[42.0f32, -3.1, 4.0e10, 4.0e-20, NAN, 2147483500.1]; + let result = &[42i32, -3, i32::MIN, 0, i32::MIN, 2147483520]; + for i in 0..inputs.len() { + let x = _mm_setr_ps(inputs[i], 1.0, 3.0, 4.0); + let e = result[i]; + let r = $alias(x); + assert_eq!(e, r, "TestCase #{} f({:?}) = {}, expected: {}", i, x, r, e); + } + }; + } + #[simd_test(enable = "sse")] fn test_mm_cvtss_si32() { - let inputs = &[42.0f32, -3.1, 4.0e10, 4.0e-20, NAN, 2147483500.1]; - let result = &[42i32, -3, i32::MIN, 0, i32::MIN, 2147483520]; - for i in 0..inputs.len() { - let x = _mm_setr_ps(inputs[i], 1.0, 3.0, 4.0); - let e = result[i]; - let r = _mm_cvtss_si32(x); - assert_eq!( - e, r, - "TestCase #{} _mm_cvtss_si32({:?}) = {}, expected: {}", - i, x, r, e - ); - } + test_mm_cvtss_si32_impl!(_mm_cvtss_si32); + } + + #[simd_test(enable = "sse")] + fn test_mm_cvt_ss2si() { + test_mm_cvtss_si32_impl!(_mm_cvt_ss2si); + } + + macro_rules! test_cvttss_si32_impl { + ($alias:ident) => { + let inputs = &[ + (42.0f32, 42i32), + (-31.4, -31), + (-33.5, -33), + (-34.5, -34), + (10.999, 10), + (-5.99, -5), + (4.0e10, i32::MIN), + (4.0e-10, 0), + (NAN, i32::MIN), + (2147483500.1, 2147483520), + ]; + for (i, &(xi, e)) in inputs.iter().enumerate() { + let x = _mm_setr_ps(xi, 1.0, 3.0, 4.0); + let r = $alias(x); + assert_eq!(e, r, "TestCase #{} f({:?}) = {}, expected: {}", i, x, r, e); + } + }; } #[simd_test(enable = "sse")] fn test_mm_cvttss_si32() { - let inputs = &[ - (42.0f32, 42i32), - (-31.4, -31), - (-33.5, -33), - (-34.5, -34), - (10.999, 10), - (-5.99, -5), - (4.0e10, i32::MIN), - (4.0e-10, 0), - (NAN, i32::MIN), - (2147483500.1, 2147483520), - ]; - for (i, &(xi, e)) in inputs.iter().enumerate() { - let x = _mm_setr_ps(xi, 1.0, 3.0, 4.0); - let r = _mm_cvttss_si32(x); - assert_eq!( - e, r, - "TestCase #{} _mm_cvttss_si32({:?}) = {}, expected: {}", - i, x, r, e - ); - } + test_cvttss_si32_impl!(_mm_cvttss_si32); } #[simd_test(enable = "sse")] - const fn test_mm_cvtsi32_ss() { - let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0); + fn test_mm_cvtt_ss2si() { + test_cvttss_si32_impl!(_mm_cvtt_ss2si); + } - let r = _mm_cvtsi32_ss(a, 4555); - let e = _mm_setr_ps(4555.0, 6.0, 7.0, 8.0); - assert_eq_m128(e, r); + macro_rules! test_mm_cvtsi32_ss_impl { + ($alias:ident) => { + let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0); - let r = _mm_cvtsi32_ss(a, 322223333); - let e = _mm_setr_ps(322223333.0, 6.0, 7.0, 8.0); - assert_eq_m128(e, r); + let r = $alias(a, 4555); + assert_eq_m128(_mm_setr_ps(4555.0, 6.0, 7.0, 8.0), r); - let r = _mm_cvtsi32_ss(a, -432); - let e = _mm_setr_ps(-432.0, 6.0, 7.0, 8.0); - assert_eq_m128(e, r); + let r = $alias(a, 322223333); + assert_eq_m128(_mm_setr_ps(322223333.0, 6.0, 7.0, 8.0), r); - let r = _mm_cvtsi32_ss(a, -322223333); - let e = _mm_setr_ps(-322223333.0, 6.0, 7.0, 8.0); - assert_eq_m128(e, r); + let r = $alias(a, -432); + assert_eq_m128(_mm_setr_ps(-432.0, 6.0, 7.0, 8.0), r); + + let r = $alias(a, -322223333); + assert_eq_m128(_mm_setr_ps(-322223333.0, 6.0, 7.0, 8.0), r); + }; + } + + #[simd_test(enable = "sse")] + const fn test_mm_cvtsi32_ss() { + test_mm_cvtsi32_ss_impl!(_mm_cvtsi32_ss); + } + + #[simd_test(enable = "sse")] + fn test_mm_cvt_si2ss() { + test_mm_cvtsi32_ss_impl!(_mm_cvt_si2ss); } #[simd_test(enable = "sse")] @@ -3053,18 +3092,24 @@ mod tests { assert_eq_m128(r, _mm_setr_ps(4.25, 0.0, 0.0, 0.0)); } + macro_rules! test_mm_set1_ps_impl { + ($alias:ident) => { + let r = $alias(black_box(4.25)); + assert_eq!(get_m128(r, 0), 4.25); + assert_eq!(get_m128(r, 1), 4.25); + assert_eq!(get_m128(r, 2), 4.25); + assert_eq!(get_m128(r, 3), 4.25); + }; + } + #[simd_test(enable = "sse")] const fn test_mm_set1_ps() { - let r1 = _mm_set1_ps(black_box(4.25)); - let r2 = _mm_set_ps1(black_box(4.25)); - assert_eq!(get_m128(r1, 0), 4.25); - assert_eq!(get_m128(r1, 1), 4.25); - assert_eq!(get_m128(r1, 2), 4.25); - assert_eq!(get_m128(r1, 3), 4.25); - assert_eq!(get_m128(r2, 0), 4.25); - assert_eq!(get_m128(r2, 1), 4.25); - assert_eq!(get_m128(r2, 2), 4.25); - assert_eq!(get_m128(r2, 3), 4.25); + test_mm_set1_ps_impl!(_mm_set1_ps); + } + + #[simd_test(enable = "sse")] + const fn test_mm_set_ps1() { + test_mm_set1_ps_impl!(_mm_set_ps1); } #[simd_test(enable = "sse")] @@ -3153,11 +3198,22 @@ mod tests { assert_eq_m128(r, _mm_setr_ps(42.0, 0.0, 0.0, 0.0)); } + macro_rules! test_mm_load1_ps_impl { + ($alias:ident) => { + let a = 42.0f32; + let r = unsafe { $alias(ptr::addr_of!(a)) }; + assert_eq_m128(r, _mm_setr_ps(42.0, 42.0, 42.0, 42.0)); + }; + } + #[simd_test(enable = "sse")] const fn test_mm_load1_ps() { - let a = 42.0f32; - let r = unsafe { _mm_load1_ps(ptr::addr_of!(a)) }; - assert_eq_m128(r, _mm_setr_ps(42.0, 42.0, 42.0, 42.0)); + test_mm_load1_ps_impl!(_mm_load1_ps); + } + + #[simd_test(enable = "sse")] + const fn test_mm_load_ps1() { + test_mm_load1_ps_impl!(_mm_load_ps1); } #[simd_test(enable = "sse")] @@ -3209,19 +3265,24 @@ mod tests { assert_eq!(vals[2], 0.0); } + macro_rules! test_mm_store1_ps_impl { + ($alias:ident) => { + let mut vals = Memory { data: [0.0f32; 4] }; + let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); + let p = vals.data.as_mut_ptr(); + unsafe { $alias(p, *black_box(&a)) }; + assert_eq!(vals.data, [1.0, 1.0, 1.0, 1.0]); + }; + } + #[simd_test(enable = "sse")] const fn test_mm_store1_ps() { - let mut vals = Memory { data: [0.0f32; 4] }; - let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); - - // guaranteed to be aligned to 16 bytes - let p = vals.data.as_mut_ptr(); - - unsafe { - _mm_store1_ps(p, *black_box(&a)); - } + test_mm_store1_ps_impl!(_mm_store1_ps); + } - assert_eq!(vals.data, [1.0, 1.0, 1.0, 1.0]); + #[simd_test(enable = "sse")] + const fn test_mm_store_ps1() { + test_mm_store1_ps_impl!(_mm_store_ps1); } #[simd_test(enable = "sse")] diff --git a/library/stdarch/crates/core_arch/src/x86/sse2.rs b/library/stdarch/crates/core_arch/src/x86/sse2.rs index f339a003df4d1..66ebec22e11de 100644 --- a/library/stdarch/crates/core_arch/src/x86/sse2.rs +++ b/library/stdarch/crates/core_arch/src/x86/sse2.rs @@ -29,6 +29,12 @@ pub fn _mm_pause() { /// the cache hierarchy. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_clflush) +/// +/// # Safety +/// +/// Unlike the prefetch intrinsics, `CLFLUSH` is subject to all the permission +/// checking and faults associated with a byte load, so `p` must point to a +/// byte that is valid for reads. #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(clflush))] @@ -1439,7 +1445,7 @@ pub unsafe fn _mm_stream_si128(mem_addr: *mut __m128i, a: __m128i) { ); } -/// Stores a 32-bit integer value in the specified memory location. +/// Stores a 32-bit integer value in a 4-byte aligned memory location. /// To minimize caching, the data is flagged as non-temporal (unlikely to be /// used again soon). /// @@ -1484,7 +1490,7 @@ pub const fn _mm_move_epi64(a: __m128i) -> __m128i { } } -/// Converts packed 16-bit integers from `a` and `b` to packed 8-bit integers +/// Converts packed signed 16-bit integers from `a` and `b` to packed 8-bit integers /// using signed saturation. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packs_epi16) @@ -1492,11 +1498,29 @@ pub const fn _mm_move_epi64(a: __m128i) -> __m128i { #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(packsswb))] #[stable(feature = "simd_x86", since = "1.27.0")] -pub fn _mm_packs_epi16(a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(packsswb(a.as_i16x8(), b.as_i16x8())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_packs_epi16(a: __m128i, b: __m128i) -> __m128i { + unsafe { + let max = simd_splat(i8::MAX as i16); + let min = simd_splat(i8::MIN as i16); + + let clamped_a = simd_imax(simd_imin(a.as_i16x8(), max), min) + .as_m128i() + .as_i8x16(); + let clamped_b = simd_imax(simd_imin(b.as_i16x8(), max), min) + .as_m128i() + .as_i8x16(); + + // Shuffle the low i8 of each i16 from two concatenated vectors into + // the low bits of the result register. + const IDXS: [u32; 16] = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]; + let result: i8x16 = simd_shuffle!(clamped_a, clamped_b, IDXS); + + result.as_m128i() + } } -/// Converts packed 32-bit integers from `a` and `b` to packed 16-bit integers +/// Converts packed signed 32-bit integers from `a` and `b` to packed 16-bit integers /// using signed saturation. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packs_epi32) @@ -1504,11 +1528,25 @@ pub fn _mm_packs_epi16(a: __m128i, b: __m128i) -> __m128i { #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(packssdw))] #[stable(feature = "simd_x86", since = "1.27.0")] -pub fn _mm_packs_epi32(a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(packssdw(a.as_i32x4(), b.as_i32x4())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_packs_epi32(a: __m128i, b: __m128i) -> __m128i { + unsafe { + let max = simd_splat(i16::MAX as i32); + let min = simd_splat(i16::MIN as i32); + + let clamped_a = simd_imax(simd_imin(a.as_i32x4(), max), min); + let clamped_b = simd_imax(simd_imin(b.as_i32x4(), max), min); + + let clamped_a: i16x4 = simd_cast(clamped_a); + let clamped_b: i16x4 = simd_cast(clamped_b); + + let a: i64 = transmute(clamped_a); + let b: i64 = transmute(clamped_b); + i64x2::new(a, b).as_m128i() + } } -/// Converts packed 16-bit integers from `a` and `b` to packed 8-bit integers +/// Converts packed signed 16-bit integers from `a` and `b` to packed 8-bit integers /// using unsigned saturation. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packus_epi16) @@ -1516,8 +1554,28 @@ pub fn _mm_packs_epi32(a: __m128i, b: __m128i) -> __m128i { #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(packuswb))] #[stable(feature = "simd_x86", since = "1.27.0")] -pub fn _mm_packus_epi16(a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(packuswb(a.as_i16x8(), b.as_i16x8())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_packus_epi16(a: __m128i, b: __m128i) -> __m128i { + unsafe { + let max = simd_splat(u8::MAX as i16); + let min = simd_splat(u8::MIN as i16); + + let clamped_a = simd_imax(simd_imin(a.as_i16x8(), max), min) + .as_m128i() + .as_i8x16(); + let clamped_b = simd_imax(simd_imin(b.as_i16x8(), max), min) + .as_m128i() + .as_i8x16(); + + // Shuffle the low bytes of each i16 from two concatenated vectors into + // the low bits of the result register. + // Without `simd_shuffle`, this intrinsic will cause the AVX-512BW + // `_mm_mask_packus_epi16` and `_mm_maskz_packus_epi16` tests to fail. + const IDXS: [u32; 16] = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]; + let result: i8x16 = simd_shuffle!(clamped_a, clamped_b, IDXS); + + result.as_m128i() + } } /// Returns the `imm8` element of `a`. @@ -3184,7 +3242,7 @@ pub const fn _mm_unpacklo_pd(a: __m128d, b: __m128d) -> __m128d { } #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.sse2.pause"] fn pause(); #[link_name = "llvm.x86.sse2.clflush"] @@ -3217,12 +3275,6 @@ unsafe extern "C" { fn cvtps2dq(a: __m128) -> i32x4; #[link_name = "llvm.x86.sse2.maskmov.dqu"] fn maskmovdqu(a: i8x16, mask: i8x16, mem_addr: *mut i8); - #[link_name = "llvm.x86.sse2.packsswb.128"] - fn packsswb(a: i16x8, b: i16x8) -> i8x16; - #[link_name = "llvm.x86.sse2.packssdw.128"] - fn packssdw(a: i32x4, b: i32x4) -> i16x8; - #[link_name = "llvm.x86.sse2.packuswb.128"] - fn packuswb(a: i16x8, b: i16x8) -> u8x16; #[link_name = "llvm.x86.sse2.max.sd"] fn maxsd(a: __m128d, b: __m128d) -> __m128d; #[link_name = "llvm.x86.sse2.max.pd"] @@ -3280,7 +3332,7 @@ mod tests { core_arch::{simd::*, x86::*}, hint::black_box, }; - use std::{boxed, f32, f64, mem, ptr}; + use std::{boxed, mem, ptr}; use stdarch_test::simd_test; const NAN: f64 = f64::NAN; @@ -4286,7 +4338,7 @@ mod tests { } #[simd_test(enable = "sse2")] - fn test_mm_packs_epi16() { + const fn test_mm_packs_epi16() { let a = _mm_setr_epi16(0x80, -0x81, 0, 0, 0, 0, 0, 0); let b = _mm_setr_epi16(0, 0, 0, 0, 0, 0, -0x81, 0x80); let r = _mm_packs_epi16(a, b); @@ -4300,7 +4352,7 @@ mod tests { } #[simd_test(enable = "sse2")] - fn test_mm_packs_epi32() { + const fn test_mm_packs_epi32() { let a = _mm_setr_epi32(0x8000, -0x8001, 0, 0); let b = _mm_setr_epi32(0, 0, -0x8001, 0x8000); let r = _mm_packs_epi32(a, b); @@ -4311,7 +4363,7 @@ mod tests { } #[simd_test(enable = "sse2")] - fn test_mm_packus_epi16() { + const fn test_mm_packus_epi16() { let a = _mm_setr_epi16(0x100, -1, 0, 0, 0, 0, 0, 0); let b = _mm_setr_epi16(0, 0, 0, 0, 0, 0, -1, 0x100); let r = _mm_packus_epi16(a, b); diff --git a/library/stdarch/crates/core_arch/src/x86/sse3.rs b/library/stdarch/crates/core_arch/src/x86/sse3.rs index e4c75702544d9..2f6fa35cb616a 100644 --- a/library/stdarch/crates/core_arch/src/x86/sse3.rs +++ b/library/stdarch/crates/core_arch/src/x86/sse3.rs @@ -178,7 +178,7 @@ pub const fn _mm_moveldup_ps(a: __m128) -> __m128 { } #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.sse3.ldu.dq"] fn lddqu(mem_addr: *const i8) -> i8x16; } diff --git a/library/stdarch/crates/core_arch/src/x86/sse41.rs b/library/stdarch/crates/core_arch/src/x86/sse41.rs index 7ad4306f36f21..d981166ff08c9 100644 --- a/library/stdarch/crates/core_arch/src/x86/sse41.rs +++ b/library/stdarch/crates/core_arch/src/x86/sse41.rs @@ -418,7 +418,7 @@ pub const fn _mm_min_epu32(a: __m128i, b: __m128i) -> __m128i { unsafe { simd_imin(a.as_u32x4(), b.as_u32x4()).as_m128i() } } -/// Converts packed 32-bit integers from `a` and `b` to packed 16-bit integers +/// Converts packed signed 32-bit integers from `a` and `b` to packed 16-bit integers /// using unsigned saturation /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packus_epi32) @@ -426,8 +426,26 @@ pub const fn _mm_min_epu32(a: __m128i, b: __m128i) -> __m128i { #[target_feature(enable = "sse4.1")] #[cfg_attr(test, assert_instr(packusdw))] #[stable(feature = "simd_x86", since = "1.27.0")] -pub fn _mm_packus_epi32(a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(packusdw(a.as_i32x4(), b.as_i32x4())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_packus_epi32(a: __m128i, b: __m128i) -> __m128i { + unsafe { + let max = simd_splat(u16::MAX as i32); + let min = simd_splat(u16::MIN as i32); + + let clamped_a = simd_imax(simd_imin(a.as_i32x4(), max), min) + .as_m128i() + .as_i16x8(); + let clamped_b = simd_imax(simd_imin(b.as_i32x4(), max), min) + .as_m128i() + .as_i16x8(); + + // Shuffle the low u16 of each i32 from two concatenated vectors into + // the low bits of the result register. + const IDXS: [u32; 8] = [0, 2, 4, 6, 8, 10, 12, 14]; + let result: i16x8 = simd_shuffle!(clamped_a, clamped_b, IDXS); + + result.as_m128i() + } } /// Compares packed 64-bit integers in `a` and `b` for equality @@ -1163,11 +1181,9 @@ pub unsafe fn _mm_stream_load_si128(mem_addr: *const __m128i) -> __m128i { } #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.sse41.insertps"] fn insertps(a: __m128, b: __m128, imm8: u8) -> __m128; - #[link_name = "llvm.x86.sse41.packusdw"] - fn packusdw(a: i32x4, b: i32x4) -> u16x8; #[link_name = "llvm.x86.sse41.dppd"] fn dppd(a: __m128d, b: __m128d, imm8: u8) -> __m128d; #[link_name = "llvm.x86.sse41.dpps"] @@ -1455,7 +1471,7 @@ mod tests { } #[simd_test(enable = "sse4.1")] - fn test_mm_packus_epi32() { + const fn test_mm_packus_epi32() { let a = _mm_setr_epi32(1, 2, 3, 4); let b = _mm_setr_epi32(-1, -2, -3, -4); let r = _mm_packus_epi32(a, b); diff --git a/library/stdarch/crates/core_arch/src/x86/sse42.rs b/library/stdarch/crates/core_arch/src/x86/sse42.rs index 55e22592637f1..0534fe9379a18 100644 --- a/library/stdarch/crates/core_arch/src/x86/sse42.rs +++ b/library/stdarch/crates/core_arch/src/x86/sse42.rs @@ -569,7 +569,7 @@ pub const fn _mm_cmpgt_epi64(a: __m128i, b: __m128i) -> __m128i { } #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { // SSE 4.2 string and text comparison ops #[link_name = "llvm.x86.sse42.pcmpestrm128"] fn pcmpestrm128(a: i8x16, la: i32, b: i8x16, lb: i32, imm8: i8) -> u8x16; diff --git a/library/stdarch/crates/core_arch/src/x86/sse4a.rs b/library/stdarch/crates/core_arch/src/x86/sse4a.rs index f36b879a030e3..1f8d16cb87eab 100644 --- a/library/stdarch/crates/core_arch/src/x86/sse4a.rs +++ b/library/stdarch/crates/core_arch/src/x86/sse4a.rs @@ -6,7 +6,7 @@ use crate::core_arch::{simd::*, x86::*}; use stdarch_test::assert_instr; #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.sse4a.extrq"] fn extrq(x: i64x2, y: i8x16) -> i64x2; #[link_name = "llvm.x86.sse4a.extrqi"] @@ -28,6 +28,11 @@ unsafe extern "C" { /// /// If `length == 0 && index > 0` or `length + index > 64` the result is /// undefined. +/// +/// The extracted bits are saved in the least-significant bit positions of the lower +/// quadword of the destination; the remaining bits in the lower quadword of the +/// destination register are cleared to 0. The upper quadword of the destination +/// register is undefined. #[inline] #[target_feature(enable = "sse4a")] #[cfg_attr(test, assert_instr(extrq))] @@ -43,7 +48,10 @@ pub fn _mm_extract_si64(x: __m128i, y: __m128i) -> __m128i { /// and index are both zero, bits `[63:0]` of parameter `x` are extracted. It is a compile-time error /// for `len + idx` to be greater than 64 or for `len` to be zero and `idx` to be non-zero. /// -/// Returns a 128-bit integer vector whose lower 64 bits contain the extracted bits. +/// The extracted bits are saved in the least-significant bit positions of the lower +/// quadword of the destination; the remaining bits in the lower quadword of the +/// destination register are cleared to 0. The upper quadword of the destination +/// register is undefined. #[inline] #[target_feature(enable = "sse4a")] #[cfg_attr(test, assert_instr(extrq, LEN = 5, IDX = 5))] @@ -66,6 +74,8 @@ pub fn _mm_extracti_si64(x: __m128i) -> __m128i /// /// If the `length` is zero it is interpreted as `64`. If `index + length > 64` /// or `index > 0 && length == 0` the result is undefined. +/// +/// The upper 64 bits of the destination are undefined. #[inline] #[target_feature(enable = "sse4a")] #[cfg_attr(test, assert_instr(insertq))] @@ -80,6 +90,8 @@ pub fn _mm_insert_si64(x: __m128i, y: __m128i) -> __m128i { /// `idx` specifies the index of the LSB. `len` specifies the number of bits to insert. If length and index /// are both zero, bits `[63:0]` of parameter `x` are replaced with bits `[63:0]` of parameter `y`. It is a /// compile-time error for `len + idx` to be greater than 64 or for `len` to be zero and `idx` to be non-zero. +/// +/// The upper 64 bits of the destination are undefined. #[inline] #[target_feature(enable = "sse4a")] #[cfg_attr(test, assert_instr(insertq, LEN = 5, IDX = 5))] @@ -150,6 +162,11 @@ mod tests { use crate::core_arch::x86::*; use stdarch_test::simd_test; + // Normally this requires SSE2, but for tests it does not matter whether we use the instruction. + fn _mm_cvtsi128_si64(a: __m128i) -> i64 { + unsafe { simd_extract!(a.as_i64x2(), 0) } + } + #[simd_test(enable = "sse4a")] fn test_mm_extract_si64() { let b = 0b0110_0000_0000_i64; @@ -160,7 +177,11 @@ mod tests { let y = _mm_setr_epi64x(v, 0); let e = _mm_setr_epi64x(0b0110_i64, 0); let r = _mm_extract_si64(x, y); - assert_eq_m128i(r, e); + + // The upper quadword of the destination register is undefined. + let r = _mm_cvtsi128_si64(r); + let e = _mm_cvtsi128_si64(e); + assert_eq!(r, e); } #[simd_test(enable = "sse4a")] @@ -168,7 +189,11 @@ mod tests { let a = _mm_setr_epi64x(0x0123456789abcdef, 0); let r = _mm_extracti_si64::<8, 8>(a); let e = _mm_setr_epi64x(0xcd, 0); - assert_eq_m128i(r, e); + + // The upper quadword of the destination register is undefined. + let r = _mm_cvtsi128_si64(r); + let e = _mm_cvtsi128_si64(e); + assert_eq!(r, e); } #[simd_test(enable = "sse4a")] @@ -185,7 +210,11 @@ mod tests { // ^idx: 2^3 = 8 ^length = 2^2 = 4 let y = _mm_setr_epi64x(i, v); let r = _mm_insert_si64(x, y); - assert_eq_m128i(r, expected); + + // The upper quadword of the destination register is undefined. + let r = _mm_cvtsi128_si64(r); + let expected = _mm_cvtsi128_si64(expected); + assert_eq!(r, expected); } #[simd_test(enable = "sse4a")] @@ -194,7 +223,11 @@ mod tests { let b = _mm_setr_epi64x(0x0011223344556677, 0); let r = _mm_inserti_si64::<8, 8>(a, b); let e = _mm_setr_epi64x(0x0123456789ab77ef, 0); - assert_eq_m128i(r, e); + + // The upper quadword of the destination register is undefined. + let r = _mm_cvtsi128_si64(r); + let e = _mm_cvtsi128_si64(e); + assert_eq!(r, e); } #[repr(align(16))] diff --git a/library/stdarch/crates/core_arch/src/x86/ssse3.rs b/library/stdarch/crates/core_arch/src/x86/ssse3.rs index 4426a3274c380..b0152c81596bd 100644 --- a/library/stdarch/crates/core_arch/src/x86/ssse3.rs +++ b/library/stdarch/crates/core_arch/src/x86/ssse3.rs @@ -188,7 +188,13 @@ pub const fn _mm_hadd_epi16(a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(phaddsw))] #[stable(feature = "simd_x86", since = "1.27.0")] pub fn _mm_hadds_epi16(a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(phaddsw128(a.as_i16x8(), b.as_i16x8())) } + let a = a.as_i16x8(); + let b = b.as_i16x8(); + unsafe { + let even: i16x8 = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let odd: i16x8 = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + simd_saturating_add(even, odd).as_m128i() + } } /// Horizontally adds the adjacent pairs of values contained in 2 packed @@ -240,7 +246,13 @@ pub const fn _mm_hsub_epi16(a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(phsubsw))] #[stable(feature = "simd_x86", since = "1.27.0")] pub fn _mm_hsubs_epi16(a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(phsubsw128(a.as_i16x8(), b.as_i16x8())) } + let a = a.as_i16x8(); + let b = b.as_i16x8(); + unsafe { + let even: i16x8 = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let odd: i16x8 = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + simd_saturating_sub(even, odd).as_m128i() + } } /// Horizontally subtract the adjacent pairs of values contained in 2 @@ -333,16 +345,10 @@ pub fn _mm_sign_epi32(a: __m128i, b: __m128i) -> __m128i { } #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.ssse3.pshuf.b.128"] fn pshufb128(a: u8x16, b: u8x16) -> u8x16; - #[link_name = "llvm.x86.ssse3.phadd.sw.128"] - fn phaddsw128(a: i16x8, b: i16x8) -> i16x8; - - #[link_name = "llvm.x86.ssse3.phsub.sw.128"] - fn phsubsw128(a: i16x8, b: i16x8) -> i16x8; - #[link_name = "llvm.x86.ssse3.pmadd.ub.sw.128"] fn pmaddubsw128(a: u8x16, b: i8x16) -> i16x8; diff --git a/library/stdarch/crates/core_arch/src/x86/tbm.rs b/library/stdarch/crates/core_arch/src/x86/tbm.rs index 0ba4572dcd029..2a44579408364 100644 --- a/library/stdarch/crates/core_arch/src/x86/tbm.rs +++ b/library/stdarch/crates/core_arch/src/x86/tbm.rs @@ -13,7 +13,7 @@ #[cfg(test)] use stdarch_test::assert_instr; -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.tbm.bextri.u32"] fn bextri_u32(a: u32, control: u32) -> u32; } diff --git a/library/stdarch/crates/core_arch/src/x86/vaes.rs b/library/stdarch/crates/core_arch/src/x86/vaes.rs index 864b1d56d1057..72dd387f900d5 100644 --- a/library/stdarch/crates/core_arch/src/x86/vaes.rs +++ b/library/stdarch/crates/core_arch/src/x86/vaes.rs @@ -14,7 +14,7 @@ use crate::core_arch::x86::__m512i; use stdarch_test::assert_instr; #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.aesni.aesenc.256"] fn aesenc_256(a: __m256i, round_key: __m256i) -> __m256i; #[link_name = "llvm.x86.aesni.aesenclast.256"] diff --git a/library/stdarch/crates/core_arch/src/x86/vpclmulqdq.rs b/library/stdarch/crates/core_arch/src/x86/vpclmulqdq.rs index ad44e59f3ada1..4c39ae6ee7aa3 100644 --- a/library/stdarch/crates/core_arch/src/x86/vpclmulqdq.rs +++ b/library/stdarch/crates/core_arch/src/x86/vpclmulqdq.rs @@ -12,7 +12,7 @@ use crate::core_arch::x86::__m512i; use stdarch_test::assert_instr; #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.pclmulqdq.256"] fn pclmulqdq_256(a: __m256i, round_key: __m256i, imm8: u8) -> __m256i; #[link_name = "llvm.x86.pclmulqdq.512"] diff --git a/library/stdarch/crates/core_arch/src/x86/xsave.rs b/library/stdarch/crates/core_arch/src/x86/xsave.rs index e22d3580ff463..395e2c64be3a0 100644 --- a/library/stdarch/crates/core_arch/src/x86/xsave.rs +++ b/library/stdarch/crates/core_arch/src/x86/xsave.rs @@ -5,7 +5,7 @@ use stdarch_test::assert_instr; #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.xsave"] fn xsave(p: *mut u8, hi: u32, lo: u32); #[link_name = "llvm.x86.xrstor"] diff --git a/library/stdarch/crates/core_arch/src/x86_64/amx.rs b/library/stdarch/crates/core_arch/src/x86_64/amx.rs index 4e20e014cf20a..f97acf1d3f746 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/amx.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/amx.rs @@ -1,14 +1,34 @@ +use crate::core_arch::x86_64::{__tile1024i, Tile}; use crate::core_arch::{simd::*, x86::*}; #[cfg(test)] use stdarch_test::assert_instr; -/// Load tile configuration from a 64-byte memory location specified by mem_addr. +/// Load tile configuration from a 64-byte memory location specified by `mem_addr`. /// The tile configuration format is specified below, and includes the tile type pallette, /// the number of bytes per row, and the number of rows. If the specified pallette_id is zero, /// that signifies the init state for both the tile config and the tile data, and the tiles are zeroed. /// Any invalid configurations will result in #GP fault. /// +/// ```intel +/// // format of memory payload. each field is a byte. +/// 0: palette +/// 1: start_row +/// 2-15: reserved, must be zero +/// 16-17: tile0.colsb +/// 18-19: tile1.colsb +/// 20-21: tile2.colsb +/// ... +/// 30-31: tile7.colsb +/// 32-47: reserved, must be zero +/// 48: tile0.rows +/// 49: tile1.rows +/// 50: tile2.rows +/// ... +/// 55: tile7.rows +/// 56-63: reserved, must be zero +/// ``` +/// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_tile_loadconfig&ig_expand=6875) #[inline] #[target_feature(enable = "amx-tile")] @@ -18,8 +38,8 @@ pub unsafe fn _tile_loadconfig(mem_addr: *const u8) { ldtilecfg(mem_addr); } -/// Stores the current tile configuration to a 64-byte memory location specified by mem_addr. -/// The tile configuration format is specified below, and includes the tile type pallette, +/// Stores the current tile configuration to a 64-byte memory location specified by `mem_addr`. +/// The tile configuration format is as specified in [`_tile_loadconfig`], and includes the tile type pallette, /// the number of bytes per row, and the number of rows. If tiles are not configured, all zeroes will be stored to memory. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_tile_storeconfig&ig_expand=6879) @@ -31,7 +51,7 @@ pub unsafe fn _tile_storeconfig(mem_addr: *mut u8) { sttilecfg(mem_addr); } -/// Load tile rows from memory specifieid by base address and stride into destination tile dst using the tile configuration previously configured via _tile_loadconfig. +/// Load tile rows from memory specified by base address and stride into destination tile dst using the tile configuration previously configured via [`_tile_loadconfig`]. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_tile_loadd&ig_expand=6877) #[inline] @@ -41,7 +61,19 @@ pub unsafe fn _tile_storeconfig(mem_addr: *mut u8) { #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] pub unsafe fn _tile_loadd(base: *const u8, stride: usize) { static_assert_uimm_bits!(DST, 3); - tileloadd64(DST as i8, base, stride); + tileloadd64(DST as i8, base, stride as u64); +} + +/// Load tile rows from memory specified by base address and stride into destination tile dst. The shape +/// of the tile is specified in the struct of [`__tile1024i`]. The register of the tile is allocated by the compiler. +/// +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=__tile_loadd&ig_expand=6877) +#[inline] +#[target_feature(enable = "amx-tile")] +#[cfg_attr(test, assert_instr(tileloadd))] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn __tile_loadd(dst: *mut __tile1024i, base: *const u8, stride: usize) { + (*dst).tile = tileloadd64_internal((*dst).rows, (*dst).colsb, base, stride as u64); } /// Release the tile configuration to return to the init state, which releases all storage it currently holds. @@ -55,7 +87,7 @@ pub unsafe fn _tile_release() { tilerelease(); } -/// Store the tile specified by src to memory specifieid by base address and stride using the tile configuration previously configured via _tile_loadconfig. +/// Store the tile specified by src to memory specified by base address and stride using the tile configuration previously configured via [`_tile_loadconfig`]. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_tile_stored&ig_expand=6881) #[inline] @@ -65,11 +97,23 @@ pub unsafe fn _tile_release() { #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] pub unsafe fn _tile_stored(base: *mut u8, stride: usize) { static_assert_uimm_bits!(DST, 3); - tilestored64(DST as i8, base, stride); + tilestored64(DST as i8, base, stride as u64); } -/// Load tile rows from memory specifieid by base address and stride into destination tile dst using the tile configuration -/// previously configured via _tile_loadconfig. This intrinsic provides a hint to the implementation that the data will +/// Store the tile specified by src to memory specified by base address and stride. The shape of the tile +/// is specified in the struct of [`__tile1024i`]. The register of the tile is allocated by the compiler. +/// +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=__tile_stored&ig_expand=6881) +#[inline] +#[target_feature(enable = "amx-tile")] +#[cfg_attr(test, assert_instr(tilestored))] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn __tile_stored(base: *mut u8, stride: usize, src: __tile1024i) { + tilestored64_internal(src.rows, src.colsb, base, stride as u64, src.tile); +} + +/// Load tile rows from memory specified by base address and stride into destination tile dst using the tile configuration +/// previously configured via [`_tile_loadconfig`]. This intrinsic provides a hint to the implementation that the data will /// likely not be reused in the near future and the data caching can be optimized accordingly. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_tile_stream_loadd&ig_expand=6883) @@ -80,10 +124,24 @@ pub unsafe fn _tile_stored(base: *mut u8, stride: usize) { #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] pub unsafe fn _tile_stream_loadd(base: *const u8, stride: usize) { static_assert_uimm_bits!(DST, 3); - tileloaddt164(DST as i8, base, stride); + tileloaddt164(DST as i8, base, stride as u64); +} + +/// Load tile rows from memory specified by base address and stride into destination tile dst. The shape +/// of the tile is specified in the struct of [`__tile1024i`]. The register of the tile is allocated by the compiler. +/// This intrinsic provides a hint to the implementation that the data will likely not be reused in the +/// near future and the data caching can be optimized accordingly. +/// +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=__tile_stream_loadd&ig_expand=6883) +#[inline] +#[target_feature(enable = "amx-tile")] +#[cfg_attr(test, assert_instr(tileloaddt1))] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn __tile_stream_loadd(dst: *mut __tile1024i, base: *const u8, stride: usize) { + (*dst).tile = tileloaddt164_internal((*dst).rows, (*dst).colsb, base, stride as u64); } -/// Zero the tile specified by tdest. +/// Zero the tile specified by `tdest`. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_tile_zero&ig_expand=6885) #[inline] @@ -96,6 +154,18 @@ pub unsafe fn _tile_zero() { tilezero(DST as i8); } +/// Zero the tile specified by `dst`. The shape of the tile is specified in the struct of [`__tile1024i`]. +/// The register of the tile is allocated by the compiler. +/// +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=__tile_zero&ig_expand=6885) +#[inline] +#[target_feature(enable = "amx-tile")] +#[cfg_attr(test, assert_instr(tilezero))] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn __tile_zero(dst: *mut __tile1024i) { + (*dst).tile = tilezero_internal((*dst).rows, (*dst).colsb); +} + /// Compute dot-product of BF16 (16-bit) floating-point pairs in tiles a and b, /// accumulating the intermediate single-precision (32-bit) floating-point elements /// with elements in dst, and store the 32-bit result back to tile dst. @@ -113,6 +183,20 @@ pub unsafe fn _tile_dpbf16ps() { tdpbf16ps(DST as i8, A as i8, B as i8); } +/// Compute dot-product of FP16 (16-bit) floating-point pairs in tiles a and b, +/// accumulating the intermediate single-precision (32-bit) floating-point elements +/// with elements in dst, and store the 32-bit result back to tile dst. The shape of the tile +/// is specified in the struct of [`__tile1024i`]. The register of the tile is allocated by the compiler. +/// +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=__tile_dpbf16ps&ig_expand=6864) +#[inline] +#[target_feature(enable = "amx-bf16")] +#[cfg_attr(test, assert_instr(tdpbf16ps))] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn __tile_dpbf16ps(dst: *mut __tile1024i, a: __tile1024i, b: __tile1024i) { + (*dst).tile = tdpbf16ps_internal(a.rows, b.colsb, a.colsb, (*dst).tile, a.tile, b.tile); +} + /// Compute dot-product of bytes in tiles with a source/destination accumulator. /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding /// signed 8-bit integers in b, producing 4 intermediate 32-bit results. @@ -131,6 +215,21 @@ pub unsafe fn _tile_dpbssd() { tdpbssd(DST as i8, A as i8, B as i8); } +/// Compute dot-product of bytes in tiles with a source/destination accumulator. +/// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding +/// signed 8-bit integers in b, producing 4 intermediate 32-bit results. +/// Sum these 4 results with the corresponding 32-bit integer in dst, and store the 32-bit result back to tile dst. +/// The shape of the tile is specified in the struct of [`__tile1024i`]. The register of the tile is allocated by the compiler. +/// +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=__tile_dpbssd&ig_expand=6866) +#[inline] +#[target_feature(enable = "amx-int8")] +#[cfg_attr(test, assert_instr(tdpbssd))] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn __tile_dpbssd(dst: *mut __tile1024i, a: __tile1024i, b: __tile1024i) { + (*dst).tile = tdpbssd_internal(a.rows, b.colsb, a.colsb, (*dst).tile, a.tile, b.tile); +} + /// Compute dot-product of bytes in tiles with a source/destination accumulator. /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding /// unsigned 8-bit integers in b, producing 4 intermediate 32-bit results. @@ -149,6 +248,21 @@ pub unsafe fn _tile_dpbsud() { tdpbsud(DST as i8, A as i8, B as i8); } +/// Compute dot-product of bytes in tiles with a source/destination accumulator. +/// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding +/// unsigned 8-bit integers in b, producing 4 intermediate 32-bit results. +/// Sum these 4 results with the corresponding 32-bit integer in dst, and store the 32-bit result back to tile dst. +/// The shape of the tile is specified in the struct of [`__tile1024i`]. The register of the tile is allocated by the compiler. +/// +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=__tile_dpbsud&ig_expand=6868) +#[inline] +#[target_feature(enable = "amx-int8")] +#[cfg_attr(test, assert_instr(tdpbsud))] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn __tile_dpbsud(dst: *mut __tile1024i, a: __tile1024i, b: __tile1024i) { + (*dst).tile = tdpbsud_internal(a.rows, b.colsb, a.colsb, (*dst).tile, a.tile, b.tile); +} + /// Compute dot-product of bytes in tiles with a source/destination accumulator. /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding /// signed 8-bit integers in b, producing 4 intermediate 32-bit results. @@ -167,6 +281,21 @@ pub unsafe fn _tile_dpbusd() { tdpbusd(DST as i8, A as i8, B as i8); } +/// Compute dot-product of bytes in tiles with a source/destination accumulator. +/// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding +/// signed 8-bit integers in b, producing 4 intermediate 32-bit results. +/// Sum these 4 results with the corresponding 32-bit integer in dst, and store the 32-bit result back to tile dst. +/// The shape of the tile is specified in the struct of [`__tile1024i`]. The register of the tile is allocated by the compiler. +/// +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=__tile_dpbusd&ig_expand=6870) +#[inline] +#[target_feature(enable = "amx-int8")] +#[cfg_attr(test, assert_instr(tdpbusd))] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn __tile_dpbusd(dst: *mut __tile1024i, a: __tile1024i, b: __tile1024i) { + (*dst).tile = tdpbusd_internal(a.rows, b.colsb, a.colsb, (*dst).tile, a.tile, b.tile); +} + /// Compute dot-product of bytes in tiles with a source/destination accumulator. /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding /// unsigned 8-bit integers in b, producing 4 intermediate 32-bit results. @@ -185,6 +314,21 @@ pub unsafe fn _tile_dpbuud() { tdpbuud(DST as i8, A as i8, B as i8); } +/// Compute dot-product of bytes in tiles with a source/destination accumulator. +/// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding +/// unsigned 8-bit integers in b, producing 4 intermediate 32-bit results. +/// Sum these 4 results with the corresponding 32-bit integer in dst, and store the 32-bit result back to tile dst. +/// The shape of the tile is specified in the struct of [`__tile1024i`]. The register of the tile is allocated by the compiler. +/// +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=__tile_dpbuud&ig_expand=6872) +#[inline] +#[target_feature(enable = "amx-int8")] +#[cfg_attr(test, assert_instr(tdpbuud))] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn __tile_dpbuud(dst: *mut __tile1024i, a: __tile1024i, b: __tile1024i) { + (*dst).tile = tdpbuud_internal(a.rows, b.colsb, a.colsb, (*dst).tile, a.tile, b.tile); +} + /// Compute dot-product of FP16 (16-bit) floating-point pairs in tiles a and b, /// accumulating the intermediate single-precision (32-bit) floating-point elements /// with elements in dst, and store the 32-bit result back to tile dst. @@ -202,6 +346,20 @@ pub unsafe fn _tile_dpfp16ps() { tdpfp16ps(DST as i8, A as i8, B as i8); } +/// Compute dot-product of FP16 (16-bit) floating-point pairs in tiles a and b, +/// accumulating the intermediate single-precision (32-bit) floating-point elements +/// with elements in dst, and store the 32-bit result back to tile dst. +/// The shape of the tile is specified in the struct of [`__tile1024i`]. The register of the tile is allocated by the compiler. +/// +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=__tile_dpfp16ps&ig_expand=6874) +#[inline] +#[target_feature(enable = "amx-fp16")] +#[cfg_attr(test, assert_instr(tdpfp16ps))] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn __tile_dpfp16ps(dst: *mut __tile1024i, a: __tile1024i, b: __tile1024i) { + (*dst).tile = tdpfp16ps_internal(a.rows, b.colsb, a.colsb, (*dst).tile, a.tile, b.tile); +} + /// Perform matrix multiplication of two tiles containing complex elements and accumulate the results into a packed single precision tile. /// Each dword element in input tiles a and b is interpreted as a complex number with FP16 real part and FP16 imaginary part. /// Calculates the imaginary part of the result. For each possible combination of (row of a, column of b), @@ -223,6 +381,24 @@ pub unsafe fn _tile_cmmimfp16ps() { tcmmimfp16ps(DST as i8, A as i8, B as i8); } +/// Perform matrix multiplication of two tiles containing complex elements and accumulate the results into a packed single precision tile. +/// Each dword element in input tiles a and b is interpreted as a complex number with FP16 real part and FP16 imaginary part. +/// Calculates the imaginary part of the result. For each possible combination of (row of a, column of b), +/// it performs a set of multiplication and accumulations on all corresponding complex numbers (one from a and one from b). +/// The imaginary part of the a element is multiplied with the real part of the corresponding b element, and the real part of +/// the a element is multiplied with the imaginary part of the corresponding b elements. The two accumulated results are added, +/// and then accumulated into the corresponding row and column of dst. +/// The shape of the tile is specified in the struct of [`__tile1024i`]. The register of the tile is allocated by the compiler. +/// +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=__tile_cmmimfp16ps&ig_expand=6860) +#[inline] +#[target_feature(enable = "amx-complex")] +#[cfg_attr(test, assert_instr(tcmmimfp16ps))] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn __tile_cmmimfp16ps(dst: *mut __tile1024i, a: __tile1024i, b: __tile1024i) { + (*dst).tile = tcmmimfp16ps_internal(a.rows, b.colsb, a.colsb, (*dst).tile, a.tile, b.tile); +} + /// Perform matrix multiplication of two tiles containing complex elements and accumulate the results into a packed single precision tile. /// Each dword element in input tiles a and b is interpreted as a complex number with FP16 real part and FP16 imaginary part. /// Calculates the real part of the result. For each possible combination of (row of a, column of b), @@ -244,6 +420,24 @@ pub unsafe fn _tile_cmmrlfp16ps() { tcmmrlfp16ps(DST as i8, A as i8, B as i8); } +/// Perform matrix multiplication of two tiles containing complex elements and accumulate the results into a packed single precision tile. +/// Each dword element in input tiles a and b is interpreted as a complex number with FP16 real part and FP16 imaginary part. +/// Calculates the real part of the result. For each possible combination of (row of a, column of b), +/// it performs a set of multiplication and accumulations on all corresponding complex numbers (one from a and one from b). +/// The real part of the a element is multiplied with the real part of the corresponding b element, and the negated imaginary part of +/// the a element is multiplied with the imaginary part of the corresponding b elements. +/// The two accumulated results are added, and then accumulated into the corresponding row and column of dst. +/// The shape of the tile is specified in the struct of [`__tile1024i`]. The register of the tile is allocated by the compiler. +/// +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=__tile_cmmrlfp16ps&ig_expand=6862) +#[inline] +#[target_feature(enable = "amx-complex")] +#[cfg_attr(test, assert_instr(tcmmrlfp16ps))] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn __tile_cmmrlfp16ps(dst: *mut __tile1024i, a: __tile1024i, b: __tile1024i) { + (*dst).tile = tcmmrlfp16ps_internal(a.rows, b.colsb, a.colsb, (*dst).tile, a.tile, b.tile); +} + /// Compute dot-product of BF8 (8-bit E5M2) floating-point elements in tile a and BF8 (8-bit E5M2) /// floating-point elements in tile b, accumulating the intermediate single-precision /// (32-bit) floating-point elements with elements in dst, and store the 32-bit result @@ -252,7 +446,7 @@ pub unsafe fn _tile_cmmrlfp16ps() { #[rustc_legacy_const_generics(0, 1, 2)] #[target_feature(enable = "amx-fp8")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tdpbf8ps, DST = 0, A = 1, B = 2) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] @@ -263,6 +457,19 @@ pub unsafe fn _tile_dpbf8ps() { tdpbf8ps(DST as i8, A as i8, B as i8); } +/// Compute dot-product of BF8 (8-bit E5M2) floating-point elements in tile a and BF8 (8-bit E5M2) +/// floating-point elements in tile b, accumulating the intermediate single-precision +/// (32-bit) floating-point elements with elements in dst, and store the 32-bit result +/// back to tile dst. +/// The shape of the tile is specified in the struct of [`__tile1024i`]. The register of the tile is allocated by the compiler. +#[inline] +#[target_feature(enable = "amx-fp8")] +#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(tdpbf8ps))] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn __tile_dpbf8ps(dst: *mut __tile1024i, a: __tile1024i, b: __tile1024i) { + (*dst).tile = tdpbf8ps_internal(a.rows, b.colsb, a.colsb, (*dst).tile, a.tile, b.tile); +} + /// Compute dot-product of BF8 (8-bit E5M2) floating-point elements in tile a and HF8 /// (8-bit E4M3) floating-point elements in tile b, accumulating the intermediate single-precision /// (32-bit) floating-point elements with elements in dst, and store the 32-bit result @@ -271,7 +478,7 @@ pub unsafe fn _tile_dpbf8ps() { #[rustc_legacy_const_generics(0, 1, 2)] #[target_feature(enable = "amx-fp8")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tdpbhf8ps, DST = 0, A = 1, B = 2) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] @@ -282,6 +489,19 @@ pub unsafe fn _tile_dpbhf8ps() { tdpbhf8ps(DST as i8, A as i8, B as i8); } +/// Compute dot-product of BF8 (8-bit E5M2) floating-point elements in tile a and HF8 +/// (8-bit E4M3) floating-point elements in tile b, accumulating the intermediate single-precision +/// (32-bit) floating-point elements with elements in dst, and store the 32-bit result +/// back to tile dst. +/// The shape of the tile is specified in the struct of [`__tile1024i`]. The register of the tile is allocated by the compiler. +#[inline] +#[target_feature(enable = "amx-fp8")] +#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(tdpbhf8ps))] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn __tile_dpbhf8ps(dst: *mut __tile1024i, a: __tile1024i, b: __tile1024i) { + (*dst).tile = tdpbhf8ps_internal(a.rows, b.colsb, a.colsb, (*dst).tile, a.tile, b.tile); +} + /// Compute dot-product of HF8 (8-bit E4M3) floating-point elements in tile a and BF8 /// (8-bit E5M2) floating-point elements in tile b, accumulating the intermediate single-precision /// (32-bit) floating-point elements with elements in dst, and store the 32-bit result @@ -290,7 +510,7 @@ pub unsafe fn _tile_dpbhf8ps() { #[rustc_legacy_const_generics(0, 1, 2)] #[target_feature(enable = "amx-fp8")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tdphbf8ps, DST = 0, A = 1, B = 2) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] @@ -301,6 +521,19 @@ pub unsafe fn _tile_dphbf8ps() { tdphbf8ps(DST as i8, A as i8, B as i8); } +/// Compute dot-product of HF8 (8-bit E4M3) floating-point elements in tile a and BF8 +/// (8-bit E5M2) floating-point elements in tile b, accumulating the intermediate single-precision +/// (32-bit) floating-point elements with elements in dst, and store the 32-bit result +/// back to tile dst. +/// The shape of the tile is specified in the struct of [`__tile1024i`]. The register of the tile is allocated by the compiler. +#[inline] +#[target_feature(enable = "amx-fp8")] +#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(tdphbf8ps))] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn __tile_dphbf8ps(dst: *mut __tile1024i, a: __tile1024i, b: __tile1024i) { + (*dst).tile = tdphbf8ps_internal(a.rows, b.colsb, a.colsb, (*dst).tile, a.tile, b.tile); +} + /// Compute dot-product of HF8 (8-bit E4M3) floating-point elements in tile a and HF8 (8-bit E4M3) /// floating-point elements in tile b, accumulating the intermediate single-precision /// (32-bit) floating-point elements with elements in dst, and store the 32-bit result @@ -309,7 +542,7 @@ pub unsafe fn _tile_dphbf8ps() { #[rustc_legacy_const_generics(0, 1, 2)] #[target_feature(enable = "amx-fp8")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tdphf8ps, DST = 0, A = 1, B = 2) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] @@ -320,8 +553,21 @@ pub unsafe fn _tile_dphf8ps() { tdphf8ps(DST as i8, A as i8, B as i8); } +/// Compute dot-product of HF8 (8-bit E4M3) floating-point elements in tile a and HF8 (8-bit E4M3) +/// floating-point elements in tile b, accumulating the intermediate single-precision +/// (32-bit) floating-point elements with elements in dst, and store the 32-bit result +/// back to tile dst. +/// The shape of the tile is specified in the struct of [`__tile1024i`]. The register of the tile is allocated by the compiler. +#[inline] +#[target_feature(enable = "amx-fp8")] +#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(tdphf8ps))] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn __tile_dphf8ps(dst: *mut __tile1024i, a: __tile1024i, b: __tile1024i) { + (*dst).tile = tdphf8ps_internal(a.rows, b.colsb, a.colsb, (*dst).tile, a.tile, b.tile); +} + /// Load tile rows from memory specified by base address and stride into destination tile dst -/// using the tile configuration previously configured via _tile_loadconfig. +/// using the tile configuration previously configured via [`_tile_loadconfig`]. /// Additionally, this intrinsic indicates the source memory location is likely to become /// read-shared by multiple processors, i.e., read in the future by at least one other processor /// before it is written, assuming it is ever written in the future. @@ -329,17 +575,30 @@ pub unsafe fn _tile_dphf8ps() { #[rustc_legacy_const_generics(0)] #[target_feature(enable = "amx-movrs")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tileloaddrs, DST = 0) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] pub unsafe fn _tile_loaddrs(base: *const u8, stride: usize) { static_assert_uimm_bits!(DST, 3); - tileloaddrs64(DST as i8, base, stride); + tileloaddrs64(DST as i8, base, stride as u64); +} + +/// Load tile rows from memory specified by base address and stride into destination tile dst. +/// The shape of the tile is specified in the struct of [`__tile1024i`]. The register of the tile is allocated by the compiler. +/// Additionally, this intrinsic indicates the source memory location is likely to become +/// read-shared by multiple processors, i.e., read in the future by at least one other processor +/// before it is written, assuming it is ever written in the future. +#[inline] +#[target_feature(enable = "amx-movrs")] +#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(tileloaddrs))] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn __tile_loaddrs(dst: *mut __tile1024i, base: *const u8, stride: usize) { + (*dst).tile = tileloaddrs64_internal((*dst).rows, (*dst).colsb, base, stride as u64); } /// Load tile rows from memory specified by base address and stride into destination tile dst -/// using the tile configuration previously configured via _tile_loadconfig. +/// using the tile configuration previously configured via [`_tile_loadconfig`]. /// Provides a hint to the implementation that the data would be reused but does not need /// to be resident in the nearest cache levels. /// Additionally, this intrinsic indicates the source memory location is likely to become @@ -349,38 +608,28 @@ pub unsafe fn _tile_loaddrs(base: *const u8, stride: usize) { #[rustc_legacy_const_generics(0)] #[target_feature(enable = "amx-movrs")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tileloaddrst1, DST = 0) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] pub unsafe fn _tile_stream_loaddrs(base: *const u8, stride: usize) { static_assert_uimm_bits!(DST, 3); - tileloaddrst164(DST as i8, base, stride); + tileloaddrst164(DST as i8, base, stride as u64); } -/// Perform matrix multiplication of two tiles a and b, containing packed single precision (32-bit) -/// floating-point elements, which are converted to TF32 (tensor-float32) format, and accumulate the -/// results into a packed single precision tile. -/// For each possible combination of (row of a, column of b), it performs -/// - convert to TF32 -/// - multiply the corresponding elements of a and b -/// - accumulate the results into the corresponding row and column of dst using round-to-nearest-even -/// rounding mode. -/// Output FP32 denormals are always flushed to zero, input single precision denormals are always -/// handled and *not* treated as zero. +/// Load tile rows from memory specified by base address and stride into destination tile dst. +/// The shape of the tile is specified in the struct of [`__tile1024i`]. The register of the tile is allocated by the compiler. +/// Provides a hint to the implementation that the data would be reused but does not need +/// to be resident in the nearest cache levels. +/// Additionally, this intrinsic indicates the source memory location is likely to become +/// read-shared by multiple processors, i.e., read in the future by at least one other processor +/// before it is written, assuming it is ever written in the future. #[inline] -#[rustc_legacy_const_generics(0, 1, 2)] -#[target_feature(enable = "amx-tf32")] -#[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), - assert_instr(tmmultf32ps, DST = 0, A = 1, B = 2) -)] +#[target_feature(enable = "amx-movrs")] +#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(tileloaddrst1))] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] -pub unsafe fn _tile_mmultf32ps() { - static_assert_uimm_bits!(DST, 3); - static_assert_uimm_bits!(A, 3); - static_assert_uimm_bits!(B, 3); - tmmultf32ps(DST as i8, A as i8, B as i8); +pub unsafe fn __tile_stream_loaddrs(dst: *mut __tile1024i, base: *const u8, stride: usize) { + (*dst).tile = tileloaddrst164_internal((*dst).rows, (*dst).colsb, base, stride as u64); } /// Moves a row from a tile register to a zmm register, converting the packed 32-bit signed integer @@ -389,7 +638,7 @@ pub unsafe fn _tile_mmultf32ps() { #[rustc_legacy_const_generics(0)] #[target_feature(enable = "amx-avx512,avx10.2")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tcvtrowd2ps, TILE = 0) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] @@ -398,6 +647,33 @@ pub unsafe fn _tile_cvtrowd2ps(row: u32) -> __m512 { tcvtrowd2ps(TILE as i8, row).as_m512() } +/// Moves a row from a tile register to a zmm register, converting the packed 32-bit signed integer +/// elements to packed single-precision (32-bit) floating-point elements. +#[inline] +#[rustc_legacy_const_generics(0, 1)] +#[target_feature(enable = "amx-avx512,avx10.2")] +#[cfg_attr( + all(test, not(target_vendor = "apple")), + assert_instr(tcvtrowd2ps, TILE = 0, ROW = 0) +)] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn _tile_cvtrowd2psi() -> __m512 { + static_assert_uimm_bits!(TILE, 3); + static_assert_uimm_bits!(ROW, 6); + tcvtrowd2psi(TILE as i8, ROW as u32).as_m512() +} + +/// Moves a row from a tile register to a zmm register, converting the packed 32-bit signed integer +/// elements to packed single-precision (32-bit) floating-point elements. +/// The shape of the tile is specified in the struct of [`__tile1024i`]. The register of the tile is allocated by the compiler. +#[inline] +#[target_feature(enable = "amx-avx512,avx10.2")] +#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(tcvtrowd2ps))] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn __tile_cvtrowd2ps(src: __tile1024i, row: u32) -> __m512 { + tcvtrowd2ps_internal(src.rows, src.colsb, src.tile, row).as_m512() +} + /// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit) /// floating-point elements to packed half-precision (16-bit) floating-point elements. The resulting /// 16-bit elements are placed in the high 16-bits within each 32-bit element of the returned vector. @@ -405,7 +681,7 @@ pub unsafe fn _tile_cvtrowd2ps(row: u32) -> __m512 { #[rustc_legacy_const_generics(0)] #[target_feature(enable = "amx-avx512,avx10.2")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tcvtrowps2phh, TILE = 0) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] @@ -414,6 +690,35 @@ pub unsafe fn _tile_cvtrowps2phh(row: u32) -> __m512h { tcvtrowps2phh(TILE as i8, row).as_m512h() } +/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit) +/// floating-point elements to packed half-precision (16-bit) floating-point elements. The resulting +/// 16-bit elements are placed in the high 16-bits within each 32-bit element of the returned vector. +#[inline] +#[rustc_legacy_const_generics(0, 1)] +#[target_feature(enable = "amx-avx512,avx10.2")] +#[cfg_attr( + all(test, not(target_vendor = "apple")), + assert_instr(tcvtrowps2phh, TILE = 0, ROW = 0) +)] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn _tile_cvtrowps2phhi() -> __m512h { + static_assert_uimm_bits!(TILE, 3); + static_assert_uimm_bits!(ROW, 6); + tcvtrowps2phhi(TILE as i8, ROW as u32).as_m512h() +} + +/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit) +/// floating-point elements to packed half-precision (16-bit) floating-point elements. The resulting +/// 16-bit elements are placed in the high 16-bits within each 32-bit element of the returned vector. +/// The shape of the tile is specified in the struct of [`__tile1024i`]. The register of the tile is allocated by the compiler. +#[inline] +#[target_feature(enable = "amx-avx512,avx10.2")] +#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(tcvtrowps2phh))] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn __tile_cvtrowps2phh(src: __tile1024i, row: u32) -> __m512h { + tcvtrowps2phh_internal(src.rows, src.colsb, src.tile, row).as_m512h() +} + /// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit) /// floating-point elements to packed half-precision (16-bit) floating-point elements. The resulting /// 16-bit elements are placed in the low 16-bits within each 32-bit element of the returned vector. @@ -421,7 +726,7 @@ pub unsafe fn _tile_cvtrowps2phh(row: u32) -> __m512h { #[rustc_legacy_const_generics(0)] #[target_feature(enable = "amx-avx512,avx10.2")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tcvtrowps2phl, TILE = 0) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] @@ -430,81 +735,312 @@ pub unsafe fn _tile_cvtrowps2phl(row: u32) -> __m512h { tcvtrowps2phl(TILE as i8, row).as_m512h() } -/// Moves one row of tile data into a zmm vector register +/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit) +/// floating-point elements to packed half-precision (16-bit) floating-point elements. The resulting +/// 16-bit elements are placed in the low 16-bits within each 32-bit element of the returned vector. +#[inline] +#[rustc_legacy_const_generics(0, 1)] +#[target_feature(enable = "amx-avx512,avx10.2")] +#[cfg_attr( + all(test, not(target_vendor = "apple")), + assert_instr(tcvtrowps2phl, TILE = 0, ROW = 0) +)] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn _tile_cvtrowps2phli() -> __m512h { + static_assert_uimm_bits!(TILE, 3); + static_assert_uimm_bits!(ROW, 6); + tcvtrowps2phli(TILE as i8, ROW as u32).as_m512h() +} + +/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit) +/// floating-point elements to packed half-precision (16-bit) floating-point elements. The resulting +/// 16-bit elements are placed in the low 16-bits within each 32-bit element of the returned vector. +/// The shape of the tile is specified in the struct of [`__tile1024i`]. The register of the tile is allocated by the compiler. +#[inline] +#[target_feature(enable = "amx-avx512,avx10.2")] +#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(tcvtrowps2phl))] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn __tile_cvtrowps2phl(src: __tile1024i, row: u32) -> __m512h { + tcvtrowps2phl_internal(src.rows, src.colsb, src.tile, row).as_m512h() +} + +/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit) +/// floating-point elements to packed BF16 (16-bit) floating-point elements. The resulting +/// 16-bit elements are placed in the high 16-bits within each 32-bit element of the returned vector. #[inline] #[rustc_legacy_const_generics(0)] #[target_feature(enable = "amx-avx512,avx10.2")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), - assert_instr(tilemovrow, TILE = 0) + all(test, not(target_vendor = "apple")), + assert_instr(tcvtrowps2bf16h, TILE = 0) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] -pub unsafe fn _tile_movrow(row: u32) -> __m512i { +pub unsafe fn _tile_cvtrowps2bf16h(row: u32) -> __m512bh { static_assert_uimm_bits!(TILE, 3); - tilemovrow(TILE as i8, row).as_m512i() + tcvtrowps2bf16h(TILE as i8, row).as_m512bh() } -#[allow(improper_ctypes)] -unsafe extern "C" { - #[link_name = "llvm.x86.ldtilecfg"] - fn ldtilecfg(mem_addr: *const u8); - #[link_name = "llvm.x86.sttilecfg"] - fn sttilecfg(mem_addr: *mut u8); - #[link_name = "llvm.x86.tileloadd64"] - fn tileloadd64(dst: i8, base: *const u8, stride: usize); - #[link_name = "llvm.x86.tileloaddt164"] - fn tileloaddt164(dst: i8, base: *const u8, stride: usize); - #[link_name = "llvm.x86.tilerelease"] - fn tilerelease(); - #[link_name = "llvm.x86.tilestored64"] - fn tilestored64(dst: i8, base: *mut u8, stride: usize); - #[link_name = "llvm.x86.tilezero"] - fn tilezero(dst: i8); - #[link_name = "llvm.x86.tdpbf16ps"] - fn tdpbf16ps(dst: i8, a: i8, b: i8); - #[link_name = "llvm.x86.tdpbuud"] - fn tdpbuud(dst: i8, a: i8, b: i8); - #[link_name = "llvm.x86.tdpbusd"] - fn tdpbusd(dst: i8, a: i8, b: i8); - #[link_name = "llvm.x86.tdpbsud"] - fn tdpbsud(dst: i8, a: i8, b: i8); - #[link_name = "llvm.x86.tdpbssd"] - fn tdpbssd(dst: i8, a: i8, b: i8); - #[link_name = "llvm.x86.tdpfp16ps"] - fn tdpfp16ps(dst: i8, a: i8, b: i8); - #[link_name = "llvm.x86.tcmmimfp16ps"] - fn tcmmimfp16ps(dst: i8, a: i8, b: i8); - #[link_name = "llvm.x86.tcmmrlfp16ps"] - fn tcmmrlfp16ps(dst: i8, a: i8, b: i8); - #[link_name = "llvm.x86.tdpbf8ps"] - fn tdpbf8ps(dst: i8, a: i8, b: i8); +/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit) +/// floating-point elements to packed BF16 (16-bit) floating-point elements. The resulting +/// 16-bit elements are placed in the high 16-bits within each 32-bit element of the returned vector. +#[inline] +#[rustc_legacy_const_generics(0, 1)] +#[target_feature(enable = "amx-avx512,avx10.2")] +#[cfg_attr( + all(test, not(target_vendor = "apple")), + assert_instr(tcvtrowps2bf16h, TILE = 0, ROW = 0) +)] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn _tile_cvtrowps2bf16hi() -> __m512bh { + static_assert_uimm_bits!(TILE, 3); + static_assert_uimm_bits!(ROW, 6); + tcvtrowps2bf16hi(TILE as i8, ROW as u32).as_m512bh() +} + +/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit) +/// floating-point elements to packed BF16 (16-bit) floating-point elements. The resulting +/// 16-bit elements are placed in the high 16-bits within each 32-bit element of the returned vector. +/// The shape of the tile is specified in the struct of [`__tile1024i`]. The register of the tile is allocated by the compiler. +#[inline] +#[target_feature(enable = "amx-avx512,avx10.2")] +#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(tcvtrowps2bf16h))] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn __tile_cvtrowps2bf16h(src: __tile1024i, row: u32) -> __m512bh { + tcvtrowps2bf16h_internal(src.rows, src.colsb, src.tile, row).as_m512bh() +} + +/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit) +/// floating-point elements to packed BF16 (16-bit) floating-point elements. The resulting +/// 16-bit elements are placed in the low 16-bits within each 32-bit element of the returned vector. +#[inline] +#[rustc_legacy_const_generics(0)] +#[target_feature(enable = "amx-avx512,avx10.2")] +#[cfg_attr( + all(test, not(target_vendor = "apple")), + assert_instr(tcvtrowps2bf16l, TILE = 0) +)] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn _tile_cvtrowps2bf16l(row: u32) -> __m512bh { + static_assert_uimm_bits!(TILE, 3); + tcvtrowps2bf16l(TILE as i8, row).as_m512bh() +} + +/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit) +/// floating-point elements to packed BF16 (16-bit) floating-point elements. The resulting +/// 16-bit elements are placed in the low 16-bits within each 32-bit element of the returned vector. +#[inline] +#[rustc_legacy_const_generics(0, 1)] +#[target_feature(enable = "amx-avx512,avx10.2")] +#[cfg_attr( + all(test, not(target_vendor = "apple")), + assert_instr(tcvtrowps2bf16l, TILE = 0, ROW = 0) +)] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn _tile_cvtrowps2bf16li() -> __m512bh { + static_assert_uimm_bits!(TILE, 3); + static_assert_uimm_bits!(ROW, 6); + tcvtrowps2bf16li(TILE as i8, ROW as u32).as_m512bh() +} + +/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit) +/// floating-point elements to packed BF16 (16-bit) floating-point elements. The resulting +/// 16-bit elements are placed in the low 16-bits within each 32-bit element of the returned vector. +/// The shape of the tile is specified in the struct of [`__tile1024i`]. The register of the tile is allocated by the compiler. +#[inline] +#[target_feature(enable = "amx-avx512,avx10.2")] +#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(tcvtrowps2bf16l))] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn __tile_cvtrowps2bf16l(src: __tile1024i, row: u32) -> __m512bh { + tcvtrowps2bf16l_internal(src.rows, src.colsb, src.tile, row).as_m512bh() +} + +/// Moves one row of tile data into a zmm vector register +#[inline] +#[rustc_legacy_const_generics(0)] +#[target_feature(enable = "amx-avx512,avx10.2")] +#[cfg_attr( + all(test, not(target_vendor = "apple")), + assert_instr(tilemovrow, TILE = 0) +)] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn _tile_movrow(row: u32) -> __m512i { + static_assert_uimm_bits!(TILE, 3); + tilemovrow(TILE as i8, row).as_m512i() +} + +/// Moves one row of tile data into a zmm vector register +#[inline] +#[rustc_legacy_const_generics(0, 1)] +#[target_feature(enable = "amx-avx512,avx10.2")] +#[cfg_attr( + all(test, not(target_vendor = "apple")), + assert_instr(tilemovrow, TILE = 0, ROW = 0) +)] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn _tile_movrowi() -> __m512i { + static_assert_uimm_bits!(TILE, 3); + static_assert_uimm_bits!(ROW, 6); + tilemovrowi(TILE as i8, ROW as u32).as_m512i() +} + +/// Moves one row of tile data into a zmm vector register +/// The shape of the tile is specified in the struct of [`__tile1024i`]. The register of the tile is allocated by the compiler. +#[inline] +#[target_feature(enable = "amx-avx512,avx10.2")] +#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(tilemovrow))] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn __tile_movrow(src: __tile1024i, row: u32) -> __m512i { + tilemovrow_internal(src.rows, src.colsb, src.tile, row).as_m512i() +} + +#[allow(improper_ctypes)] +unsafe extern "unadjusted" { + #[link_name = "llvm.x86.ldtilecfg"] + fn ldtilecfg(mem_addr: *const u8); + #[link_name = "llvm.x86.sttilecfg"] + fn sttilecfg(mem_addr: *mut u8); + + #[link_name = "llvm.x86.tileloadd64"] + fn tileloadd64(dst: i8, base: *const u8, stride: u64); + #[link_name = "llvm.x86.tileloadd64.internal"] + fn tileloadd64_internal(rows: u16, colsb: u16, base: *const u8, stride: u64) -> Tile; + + #[link_name = "llvm.x86.tileloaddt164"] + fn tileloaddt164(dst: i8, base: *const u8, stride: u64); + #[link_name = "llvm.x86.tileloaddt164.internal"] + fn tileloaddt164_internal(rows: u16, colsb: u16, base: *const u8, stride: u64) -> Tile; + + #[link_name = "llvm.x86.tilerelease"] + fn tilerelease(); + + #[link_name = "llvm.x86.tilestored64"] + fn tilestored64(dst: i8, base: *mut u8, stride: u64); + #[link_name = "llvm.x86.tilestored64.internal"] + fn tilestored64_internal(rows: u16, colsb: u16, base: *mut u8, stride: u64, src: Tile); + + #[link_name = "llvm.x86.tilezero"] + fn tilezero(dst: i8); + #[link_name = "llvm.x86.tilezero.internal"] + fn tilezero_internal(rows: u16, colsb: u16) -> Tile; + + #[link_name = "llvm.x86.tdpbf16ps"] + fn tdpbf16ps(dst: i8, a: i8, b: i8); + #[link_name = "llvm.x86.tdpbf16ps.internal"] + fn tdpbf16ps_internal(m: u16, n: u16, k: u16, dst: Tile, a: Tile, b: Tile) -> Tile; + + #[link_name = "llvm.x86.tdpbuud"] + fn tdpbuud(dst: i8, a: i8, b: i8); + #[link_name = "llvm.x86.tdpbuud.internal"] + fn tdpbuud_internal(m: u16, n: u16, k: u16, dst: Tile, a: Tile, b: Tile) -> Tile; + + #[link_name = "llvm.x86.tdpbusd"] + fn tdpbusd(dst: i8, a: i8, b: i8); + #[link_name = "llvm.x86.tdpbusd.internal"] + fn tdpbusd_internal(m: u16, n: u16, k: u16, dst: Tile, a: Tile, b: Tile) -> Tile; + + #[link_name = "llvm.x86.tdpbsud"] + fn tdpbsud(dst: i8, a: i8, b: i8); + #[link_name = "llvm.x86.tdpbsud.internal"] + fn tdpbsud_internal(m: u16, n: u16, k: u16, dst: Tile, a: Tile, b: Tile) -> Tile; + + #[link_name = "llvm.x86.tdpbssd"] + fn tdpbssd(dst: i8, a: i8, b: i8); + #[link_name = "llvm.x86.tdpbssd.internal"] + fn tdpbssd_internal(m: u16, n: u16, k: u16, dst: Tile, a: Tile, b: Tile) -> Tile; + + #[link_name = "llvm.x86.tdpfp16ps"] + fn tdpfp16ps(dst: i8, a: i8, b: i8); + #[link_name = "llvm.x86.tdpfp16ps.internal"] + fn tdpfp16ps_internal(m: u16, n: u16, k: u16, dst: Tile, a: Tile, b: Tile) -> Tile; + + #[link_name = "llvm.x86.tcmmimfp16ps"] + fn tcmmimfp16ps(dst: i8, a: i8, b: i8); + #[link_name = "llvm.x86.tcmmimfp16ps.internal"] + fn tcmmimfp16ps_internal(m: u16, n: u16, k: u16, dst: Tile, a: Tile, b: Tile) -> Tile; + + #[link_name = "llvm.x86.tcmmrlfp16ps"] + fn tcmmrlfp16ps(dst: i8, a: i8, b: i8); + #[link_name = "llvm.x86.tcmmrlfp16ps.internal"] + fn tcmmrlfp16ps_internal(m: u16, n: u16, k: u16, dst: Tile, a: Tile, b: Tile) -> Tile; + + #[link_name = "llvm.x86.tdpbf8ps"] + fn tdpbf8ps(dst: i8, a: i8, b: i8); + #[link_name = "llvm.x86.tdpbf8ps.internal"] + fn tdpbf8ps_internal(m: u16, n: u16, k: u16, dst: Tile, a: Tile, b: Tile) -> Tile; + #[link_name = "llvm.x86.tdpbhf8ps"] fn tdpbhf8ps(dst: i8, a: i8, b: i8); + #[link_name = "llvm.x86.tdpbhf8ps.internal"] + fn tdpbhf8ps_internal(m: u16, n: u16, k: u16, dst: Tile, a: Tile, b: Tile) -> Tile; + #[link_name = "llvm.x86.tdphbf8ps"] fn tdphbf8ps(dst: i8, a: i8, b: i8); + #[link_name = "llvm.x86.tdphbf8ps.internal"] + fn tdphbf8ps_internal(m: u16, n: u16, k: u16, dst: Tile, a: Tile, b: Tile) -> Tile; + #[link_name = "llvm.x86.tdphf8ps"] fn tdphf8ps(dst: i8, a: i8, b: i8); + #[link_name = "llvm.x86.tdphf8ps.internal"] + fn tdphf8ps_internal(m: u16, n: u16, k: u16, dst: Tile, a: Tile, b: Tile) -> Tile; + #[link_name = "llvm.x86.tileloaddrs64"] - fn tileloaddrs64(dst: i8, base: *const u8, stride: usize); + fn tileloaddrs64(dst: i8, base: *const u8, stride: u64); + #[link_name = "llvm.x86.tileloaddrs64.internal"] + fn tileloaddrs64_internal(rows: u16, colsb: u16, base: *const u8, stride: u64) -> Tile; + #[link_name = "llvm.x86.tileloaddrst164"] - fn tileloaddrst164(dst: i8, base: *const u8, stride: usize); - #[link_name = "llvm.x86.tmmultf32ps"] - fn tmmultf32ps(dst: i8, a: i8, b: i8); + fn tileloaddrst164(dst: i8, base: *const u8, stride: u64); + #[link_name = "llvm.x86.tileloaddrst164.internal"] + fn tileloaddrst164_internal(rows: u16, colsb: u16, base: *const u8, stride: u64) -> Tile; + #[link_name = "llvm.x86.tcvtrowd2ps"] fn tcvtrowd2ps(tile: i8, row: u32) -> f32x16; + #[link_name = "llvm.x86.tcvtrowd2psi"] + fn tcvtrowd2psi(tile: i8, row: u32) -> f32x16; + #[link_name = "llvm.x86.tcvtrowd2ps.internal"] + fn tcvtrowd2ps_internal(rows: u16, colsb: u16, src: Tile, row: u32) -> f32x16; + #[link_name = "llvm.x86.tcvtrowps2phh"] fn tcvtrowps2phh(tile: i8, row: u32) -> f16x32; + #[link_name = "llvm.x86.tcvtrowps2phhi"] + fn tcvtrowps2phhi(tile: i8, row: u32) -> f16x32; + #[link_name = "llvm.x86.tcvtrowps2phh.internal"] + fn tcvtrowps2phh_internal(rows: u16, colsb: u16, src: Tile, row: u32) -> f16x32; + #[link_name = "llvm.x86.tcvtrowps2phl"] fn tcvtrowps2phl(tile: i8, row: u32) -> f16x32; + #[link_name = "llvm.x86.tcvtrowps2phli"] + fn tcvtrowps2phli(tile: i8, row: u32) -> f16x32; + #[link_name = "llvm.x86.tcvtrowps2phl.internal"] + fn tcvtrowps2phl_internal(rows: u16, colsb: u16, src: Tile, row: u32) -> f16x32; + + #[link_name = "llvm.x86.tcvtrowps2bf16h"] + fn tcvtrowps2bf16h(tile: i8, row: u32) -> u16x32; + #[link_name = "llvm.x86.tcvtrowps2bf16hi"] + fn tcvtrowps2bf16hi(tile: i8, row: u32) -> u16x32; + #[link_name = "llvm.x86.tcvtrowps2bf16h.internal"] + fn tcvtrowps2bf16h_internal(rows: u16, colsb: u16, src: Tile, row: u32) -> u16x32; + + #[link_name = "llvm.x86.tcvtrowps2bf16l"] + fn tcvtrowps2bf16l(tile: i8, row: u32) -> u16x32; + #[link_name = "llvm.x86.tcvtrowps2bf16li"] + fn tcvtrowps2bf16li(tile: i8, row: u32) -> u16x32; + #[link_name = "llvm.x86.tcvtrowps2bf16l.internal"] + fn tcvtrowps2bf16l_internal(rows: u16, colsb: u16, src: Tile, row: u32) -> u16x32; + #[link_name = "llvm.x86.tilemovrow"] fn tilemovrow(tile: i8, row: u32) -> i32x16; + #[link_name = "llvm.x86.tilemovrowi"] + fn tilemovrowi(tile: i8, row: u32) -> i32x16; + #[link_name = "llvm.x86.tilemovrow.internal"] + fn tilemovrow_internal(rows: u16, colsb: u16, src: Tile, row: u32) -> i32x16; } #[cfg(test)] mod tests { use crate::core_arch::x86::_mm_cvtness_sbh; use crate::core_arch::x86_64::*; - use core::{array, mem::transmute}; + use core::array; use stdarch_test::simd_test; #[cfg(target_os = "linux")] use syscalls::{Sysno, syscall}; @@ -557,19 +1093,23 @@ mod tests { #[cfg(target_os = "linux")] #[target_feature(enable = "amx-tile")] #[inline] - unsafe fn _init_amx() { + fn _init_amx() { let mut ret: usize; let mut xfeatures: usize = 0; - ret = syscall!(Sysno::arch_prctl, 0x1022, &mut xfeatures as *mut usize) - .expect("arch_prctl ARCH_GET_XCOMP_PERM syscall failed"); + ret = unsafe { + syscall!(Sysno::arch_prctl, 0x1022, &raw mut xfeatures) + .expect("arch_prctl ARCH_GET_XCOMP_PERM syscall failed") + }; if ret != 0 { panic!("Failed to get XFEATURES"); } else { match 0b11 & (xfeatures >> 17) { 0 => panic!("AMX is not available"), 1 => { - ret = syscall!(Sysno::arch_prctl, 0x1023, 18) - .expect("arch_prctl ARCH_REQ_XCOMP_PERM syscall failed"); + ret = unsafe { + syscall!(Sysno::arch_prctl, 0x1023, 18) + .expect("arch_prctl ARCH_REQ_XCOMP_PERM syscall failed") + }; if ret != 0 { panic!("Failed to enable AMX"); } @@ -580,6 +1120,18 @@ mod tests { } } + impl __tile1024i { + #[inline] + #[target_feature(enable = "amx-tile")] + fn zeroed(rows: u16, colsb: u16) -> Self { + Self { + rows, + colsb, + tile: unsafe { super::tilezero_internal(rows, colsb) }, + } + } + } + #[simd_test(enable = "amx-tile")] fn test_tile_loadconfig() { unsafe { @@ -612,12 +1164,26 @@ mod tests { _tile_loadconfig(config.as_ptr()); _tile_zero::<0>(); let mut out = [[1_i8; 64]; 16]; - _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); + _tile_stored::<0>(out.as_mut_ptr().cast(), 64); _tile_release(); assert_eq!(out, [[0; 64]; 16]); } } + #[simd_test(enable = "amx-tile")] + fn test__tile_zero() { + unsafe { + _init_amx(); + + let tile = __tile1024i::zeroed(16, 64); + + let mut out = [[1_i8; 64]; 16]; + __tile_stored(out.as_mut_ptr().cast(), 64, tile); + + assert_eq!(out, [[0; 64]; 16]); + } + } + #[simd_test(enable = "amx-tile")] fn test_tile_stored() { unsafe { @@ -629,12 +1195,26 @@ mod tests { _tile_loadconfig(config.as_ptr()); _tile_zero::<0>(); let mut out = [[1_i8; 64]; 16]; - _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); + _tile_stored::<0>(out.as_mut_ptr().cast(), 64); _tile_release(); assert_eq!(out, [[0; 64]; 16]); } } + #[simd_test(enable = "amx-tile")] + fn test__tile_stored() { + unsafe { + _init_amx(); + + let tile = __tile1024i::zeroed(16, 64); + + let mut out = [[1_i8; 64]; 16]; + __tile_stored(out.as_mut_ptr().cast(), 64, tile); + + assert_eq!(out, [[0; 64]; 16]); + } + } + #[simd_test(enable = "amx-tile")] fn test_tile_loadd() { unsafe { @@ -646,14 +1226,30 @@ mod tests { _tile_loadconfig(config.as_ptr()); _tile_zero::<0>(); let mat = [1_i8; 1024]; - _tile_loadd::<0>(&mat as *const i8 as *const u8, 64); + _tile_loadd::<0>(mat.as_ptr().cast(), 64); let mut out = [[0_i8; 64]; 16]; - _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); + _tile_stored::<0>(out.as_mut_ptr().cast(), 64); _tile_release(); assert_eq!(out, [[1; 64]; 16]); } } + #[simd_test(enable = "amx-tile")] + fn test__tile_loadd() { + unsafe { + _init_amx(); + + let mut tile = __tile1024i::zeroed(16, 64); + + let mat = [1_i8; 1024]; + __tile_loadd(&mut tile, mat.as_ptr().cast(), 64); + let mut out = [[0_i8; 64]; 16]; + __tile_stored(out.as_mut_ptr().cast(), 64, tile); + + assert_eq!(out, [[1; 64]; 16]); + } + } + #[simd_test(enable = "amx-tile")] fn test_tile_stream_loadd() { unsafe { @@ -665,14 +1261,30 @@ mod tests { _tile_loadconfig(config.as_ptr()); _tile_zero::<0>(); let mat = [1_i8; 1024]; - _tile_stream_loadd::<0>(&mat as *const i8 as *const u8, 64); + _tile_stream_loadd::<0>(mat.as_ptr().cast(), 64); let mut out = [[0_i8; 64]; 16]; - _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); + _tile_stored::<0>(out.as_mut_ptr().cast(), 64); _tile_release(); assert_eq!(out, [[1; 64]; 16]); } } + #[simd_test(enable = "amx-tile")] + fn test__tile_stream_loadd() { + unsafe { + _init_amx(); + + let mut tile = __tile1024i::zeroed(16, 64); + + let mat = [1_i8; 1024]; + __tile_stream_loadd(&mut tile, mat.as_ptr().cast(), 64); + let mut out = [[0_i8; 64]; 16]; + __tile_stored(out.as_mut_ptr().cast(), 64, tile); + + assert_eq!(out, [[1; 64]; 16]); + } + } + #[simd_test(enable = "amx-tile")] fn test_tile_release() { unsafe { @@ -680,14 +1292,15 @@ mod tests { } } - #[simd_test(enable = "amx-bf16,avx512f")] + const BF16_1: u16 = 0x3f80; + const BF16_2: u16 = 0x4000; + + #[simd_test(enable = "amx-bf16")] fn test_tile_dpbf16ps() { unsafe { _init_amx(); - let bf16_1: u16 = _mm_cvtness_sbh(1.0).to_bits(); - let bf16_2: u16 = _mm_cvtness_sbh(2.0).to_bits(); - let ones: [u8; 1024] = transmute([bf16_1; 512]); - let twos: [u8; 1024] = transmute([bf16_2; 512]); + let ones = [BF16_1; 512]; + let twos = [BF16_2; 512]; let mut res = [[0f32; 16]; 16]; let mut config = __tilecfg::default(); config.palette = 1; @@ -697,15 +1310,36 @@ mod tests { }); _tile_loadconfig(config.as_ptr()); _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const u8, 64); - _tile_loadd::<2>(&twos as *const u8, 64); + _tile_loadd::<1>(ones.as_ptr().cast(), 64); + _tile_loadd::<2>(twos.as_ptr().cast(), 64); _tile_dpbf16ps::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64); + _tile_stored::<0>(res.as_mut_ptr().cast(), 64); _tile_release(); assert_eq!(res, [[64f32; 16]; 16]); } } + #[simd_test(enable = "amx-bf16")] + fn test__tile_dpbf16ps() { + unsafe { + _init_amx(); + let ones = [BF16_1; 512]; + let twos = [BF16_2; 512]; + let mut res = [[0f32; 16]; 16]; + + let mut a = __tile1024i::zeroed(16, 64); + let mut b = __tile1024i::zeroed(16, 64); + let mut c = __tile1024i::zeroed(16, 64); + + __tile_loadd(&mut a, ones.as_ptr().cast(), 64); + __tile_loadd(&mut b, twos.as_ptr().cast(), 64); + __tile_dpbf16ps(&mut c, a, b); + __tile_stored(res.as_mut_ptr().cast(), 64, c); + + assert_eq!(res, [[64f32; 16]; 16]); + } + } + #[simd_test(enable = "amx-int8")] fn test_tile_dpbssd() { unsafe { @@ -721,15 +1355,36 @@ mod tests { }); _tile_loadconfig(config.as_ptr()); _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const i8 as *const u8, 64); - _tile_loadd::<2>(&twos as *const i8 as *const u8, 64); + _tile_loadd::<1>(ones.as_ptr().cast(), 64); + _tile_loadd::<2>(twos.as_ptr().cast(), 64); _tile_dpbssd::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64); + _tile_stored::<0>(res.as_mut_ptr().cast(), 64); _tile_release(); assert_eq!(res, [[128_i32; 16]; 16]); } } + #[simd_test(enable = "amx-int8")] + fn test__tile_dpbssd() { + unsafe { + _init_amx(); + let ones = [-1_i8; 1024]; + let twos = [-2_i8; 1024]; + let mut res = [[0_i32; 16]; 16]; + + let mut a = __tile1024i::zeroed(16, 64); + let mut b = __tile1024i::zeroed(16, 64); + let mut c = __tile1024i::zeroed(16, 64); + + __tile_loadd(&mut a, ones.as_ptr().cast(), 64); + __tile_loadd(&mut b, twos.as_ptr().cast(), 64); + __tile_dpbssd(&mut c, a, b); + __tile_stored(res.as_mut_ptr().cast(), 64, c); + + assert_eq!(res, [[128_i32; 16]; 16]); + } + } + #[simd_test(enable = "amx-int8")] fn test_tile_dpbsud() { unsafe { @@ -745,15 +1400,36 @@ mod tests { }); _tile_loadconfig(config.as_ptr()); _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const i8 as *const u8, 64); - _tile_loadd::<2>(&twos as *const u8, 64); + _tile_loadd::<1>(ones.as_ptr().cast(), 64); + _tile_loadd::<2>(twos.as_ptr(), 64); _tile_dpbsud::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64); + _tile_stored::<0>(res.as_mut_ptr().cast(), 64); _tile_release(); assert_eq!(res, [[-128_i32; 16]; 16]); } } + #[simd_test(enable = "amx-int8")] + fn test__tile_dpbsud() { + unsafe { + _init_amx(); + let ones = [-1_i8; 1024]; + let twos = [2_u8; 1024]; + let mut res = [[0_i32; 16]; 16]; + + let mut a = __tile1024i::zeroed(16, 64); + let mut b = __tile1024i::zeroed(16, 64); + let mut c = __tile1024i::zeroed(16, 64); + + __tile_loadd(&mut a, ones.as_ptr().cast(), 64); + __tile_loadd(&mut b, twos.as_ptr(), 64); + __tile_dpbsud(&mut c, a, b); + __tile_stored(res.as_mut_ptr().cast(), 64, c); + + assert_eq!(res, [[-128_i32; 16]; 16]); + } + } + #[simd_test(enable = "amx-int8")] fn test_tile_dpbusd() { unsafe { @@ -769,15 +1445,36 @@ mod tests { }); _tile_loadconfig(config.as_ptr()); _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const u8, 64); - _tile_loadd::<2>(&twos as *const i8 as *const u8, 64); + _tile_loadd::<1>(ones.as_ptr(), 64); + _tile_loadd::<2>(twos.as_ptr().cast(), 64); _tile_dpbusd::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64); + _tile_stored::<0>(res.as_mut_ptr().cast(), 64); _tile_release(); assert_eq!(res, [[-128_i32; 16]; 16]); } } + #[simd_test(enable = "amx-int8")] + fn test__tile_dpbusd() { + unsafe { + _init_amx(); + let ones = [1_u8; 1024]; + let twos = [-2_i8; 1024]; + let mut res = [[0_i32; 16]; 16]; + + let mut a = __tile1024i::zeroed(16, 64); + let mut b = __tile1024i::zeroed(16, 64); + let mut c = __tile1024i::zeroed(16, 64); + + __tile_loadd(&mut a, ones.as_ptr(), 64); + __tile_loadd(&mut b, twos.as_ptr().cast(), 64); + __tile_dpbusd(&mut c, a, b); + __tile_stored(res.as_mut_ptr().cast(), 64, c); + + assert_eq!(res, [[-128_i32; 16]; 16]); + } + } + #[simd_test(enable = "amx-int8")] fn test_tile_dpbuud() { unsafe { @@ -793,15 +1490,36 @@ mod tests { }); _tile_loadconfig(config.as_ptr()); _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const u8, 64); - _tile_loadd::<2>(&twos as *const u8, 64); + _tile_loadd::<1>(ones.as_ptr(), 64); + _tile_loadd::<2>(twos.as_ptr(), 64); _tile_dpbuud::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64); + _tile_stored::<0>(res.as_mut_ptr().cast(), 64); _tile_release(); assert_eq!(res, [[128_i32; 16]; 16]); } } + #[simd_test(enable = "amx-int8")] + fn test__tile_dpbuud() { + unsafe { + _init_amx(); + let ones = [1_u8; 1024]; + let twos = [2_u8; 1024]; + let mut res = [[0_i32; 16]; 16]; + + let mut a = __tile1024i::zeroed(16, 64); + let mut b = __tile1024i::zeroed(16, 64); + let mut c = __tile1024i::zeroed(16, 64); + + __tile_loadd(&mut a, ones.as_ptr(), 64); + __tile_loadd(&mut b, twos.as_ptr(), 64); + __tile_dpbuud(&mut c, a, b); + __tile_stored(res.as_mut_ptr().cast(), 64, c); + + assert_eq!(res, [[128_i32; 16]; 16]); + } + } + #[simd_test(enable = "amx-fp16")] fn test_tile_dpfp16ps() { unsafe { @@ -817,39 +1535,81 @@ mod tests { }); _tile_loadconfig(config.as_ptr()); _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const f16 as *const u8, 64); - _tile_loadd::<2>(&twos as *const f16 as *const u8, 64); + _tile_loadd::<1>(ones.as_ptr().cast(), 64); + _tile_loadd::<2>(twos.as_ptr().cast(), 64); _tile_dpfp16ps::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64); + _tile_stored::<0>(res.as_mut_ptr().cast(), 64); _tile_release(); assert_eq!(res, [[64f32; 16]; 16]); } } - #[simd_test(enable = "amx-complex")] - fn test_tile_cmmimfp16ps() { + #[simd_test(enable = "amx-fp16")] + fn test__tile_dpfp16ps() { unsafe { _init_amx(); let ones = [1f16; 512]; let twos = [2f16; 512]; let mut res = [[0f32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; + + let mut a = __tile1024i::zeroed(16, 64); + let mut b = __tile1024i::zeroed(16, 64); + let mut c = __tile1024i::zeroed(16, 64); + + __tile_loadd(&mut a, ones.as_ptr().cast(), 64); + __tile_loadd(&mut b, twos.as_ptr().cast(), 64); + __tile_dpfp16ps(&mut c, a, b); + __tile_stored(res.as_mut_ptr().cast(), 64, c); + + assert_eq!(res, [[64f32; 16]; 16]); + } + } + + #[simd_test(enable = "amx-complex")] + fn test_tile_cmmimfp16ps() { + unsafe { + _init_amx(); + let ones = [1f16; 512]; + let twos = [2f16; 512]; + let mut res = [[0f32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; }); _tile_loadconfig(config.as_ptr()); _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const f16 as *const u8, 64); - _tile_loadd::<2>(&twos as *const f16 as *const u8, 64); + _tile_loadd::<1>(ones.as_ptr().cast(), 64); + _tile_loadd::<2>(twos.as_ptr().cast(), 64); _tile_cmmimfp16ps::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64); + _tile_stored::<0>(res.as_mut_ptr().cast(), 64); _tile_release(); assert_eq!(res, [[64f32; 16]; 16]); } } + #[simd_test(enable = "amx-complex")] + fn test__tile_cmmimfp16ps() { + unsafe { + _init_amx(); + let ones = [1f16; 512]; + let twos = [2f16; 512]; + let mut res = [[0f32; 16]; 16]; + + let mut a = __tile1024i::zeroed(16, 64); + let mut b = __tile1024i::zeroed(16, 64); + let mut c = __tile1024i::zeroed(16, 64); + + __tile_loadd(&mut a, ones.as_ptr().cast(), 64); + __tile_loadd(&mut b, twos.as_ptr().cast(), 64); + __tile_cmmimfp16ps(&mut c, a, b); + __tile_stored(res.as_mut_ptr().cast(), 64, c); + + assert_eq!(res, [[64f32; 16]; 16]); + } + } + #[simd_test(enable = "amx-complex")] fn test_tile_cmmrlfp16ps() { unsafe { @@ -865,15 +1625,36 @@ mod tests { }); _tile_loadconfig(config.as_ptr()); _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const f16 as *const u8, 64); - _tile_loadd::<2>(&twos as *const f16 as *const u8, 64); + _tile_loadd::<1>(ones.as_ptr().cast(), 64); + _tile_loadd::<2>(twos.as_ptr().cast(), 64); _tile_cmmrlfp16ps::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64); + _tile_stored::<0>(res.as_mut_ptr().cast(), 64); _tile_release(); assert_eq!(res, [[0f32; 16]; 16]); } } + #[simd_test(enable = "amx-complex")] + fn test__tile_cmmrlfp16ps() { + unsafe { + _init_amx(); + let ones = [1f16; 512]; + let twos = [2f16; 512]; + let mut res = [[0f32; 16]; 16]; + + let mut a = __tile1024i::zeroed(16, 64); + let mut b = __tile1024i::zeroed(16, 64); + let mut c = __tile1024i::zeroed(16, 64); + + __tile_loadd(&mut a, ones.as_ptr().cast(), 64); + __tile_loadd(&mut b, twos.as_ptr().cast(), 64); + __tile_cmmrlfp16ps(&mut c, a, b); + __tile_stored(res.as_mut_ptr().cast(), 64, c); + + assert_eq!(res, [[0f32; 16]; 16]); + } + } + const BF8_ONE: u8 = 0x3c; const BF8_TWO: u8 = 0x40; const HF8_ONE: u8 = 0x38; @@ -894,8 +1675,8 @@ mod tests { }); _tile_loadconfig(config.as_ptr()); _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const u8, 64); - _tile_loadd::<2>(&twos as *const u8, 64); + _tile_loadd::<1>(ones.as_ptr(), 64); + _tile_loadd::<2>(twos.as_ptr(), 64); _tile_dpbf8ps::<0, 1, 2>(); _tile_stored::<0>(res.as_mut_ptr().cast(), 64); _tile_release(); @@ -903,6 +1684,27 @@ mod tests { } } + #[simd_test(enable = "amx-fp8")] + fn test__tile_dpbf8ps() { + unsafe { + _init_amx(); + let ones = [BF8_ONE; 1024]; + let twos = [BF8_TWO; 1024]; + let mut res = [[0.0_f32; 16]; 16]; + + let mut a = __tile1024i::zeroed(16, 64); + let mut b = __tile1024i::zeroed(16, 64); + let mut c = __tile1024i::zeroed(16, 64); + + __tile_loadd(&mut a, ones.as_ptr(), 64); + __tile_loadd(&mut b, twos.as_ptr(), 64); + __tile_dpbf8ps(&mut c, a, b); + __tile_stored(res.as_mut_ptr().cast(), 64, c); + + assert_eq!(res, [[128.0_f32; 16]; 16]); + } + } + #[simd_test(enable = "amx-fp8")] fn test_tile_dpbhf8ps() { unsafe { @@ -918,8 +1720,8 @@ mod tests { }); _tile_loadconfig(config.as_ptr()); _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const u8, 64); - _tile_loadd::<2>(&twos as *const u8, 64); + _tile_loadd::<1>(ones.as_ptr(), 64); + _tile_loadd::<2>(twos.as_ptr(), 64); _tile_dpbhf8ps::<0, 1, 2>(); _tile_stored::<0>(res.as_mut_ptr().cast(), 64); _tile_release(); @@ -927,6 +1729,27 @@ mod tests { } } + #[simd_test(enable = "amx-fp8")] + fn test__tile_dpbhf8ps() { + unsafe { + _init_amx(); + let ones = [BF8_ONE; 1024]; + let twos = [HF8_TWO; 1024]; + let mut res = [[0.0_f32; 16]; 16]; + + let mut a = __tile1024i::zeroed(16, 64); + let mut b = __tile1024i::zeroed(16, 64); + let mut c = __tile1024i::zeroed(16, 64); + + __tile_loadd(&mut a, ones.as_ptr(), 64); + __tile_loadd(&mut b, twos.as_ptr(), 64); + __tile_dpbhf8ps(&mut c, a, b); + __tile_stored(res.as_mut_ptr().cast(), 64, c); + + assert_eq!(res, [[128.0_f32; 16]; 16]); + } + } + #[simd_test(enable = "amx-fp8")] fn test_tile_dphbf8ps() { unsafe { @@ -942,8 +1765,8 @@ mod tests { }); _tile_loadconfig(config.as_ptr()); _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const u8, 64); - _tile_loadd::<2>(&twos as *const u8, 64); + _tile_loadd::<1>(ones.as_ptr(), 64); + _tile_loadd::<2>(twos.as_ptr(), 64); _tile_dphbf8ps::<0, 1, 2>(); _tile_stored::<0>(res.as_mut_ptr().cast(), 64); _tile_release(); @@ -951,6 +1774,27 @@ mod tests { } } + #[simd_test(enable = "amx-fp8")] + fn test__tile_dphbf8ps() { + unsafe { + _init_amx(); + let ones = [HF8_ONE; 1024]; + let twos = [BF8_TWO; 1024]; + let mut res = [[0.0_f32; 16]; 16]; + + let mut a = __tile1024i::zeroed(16, 64); + let mut b = __tile1024i::zeroed(16, 64); + let mut c = __tile1024i::zeroed(16, 64); + + __tile_loadd(&mut a, ones.as_ptr(), 64); + __tile_loadd(&mut b, twos.as_ptr(), 64); + __tile_dphbf8ps(&mut c, a, b); + __tile_stored(res.as_mut_ptr().cast(), 64, c); + + assert_eq!(res, [[128.0_f32; 16]; 16]); + } + } + #[simd_test(enable = "amx-fp8")] fn test_tile_dphf8ps() { unsafe { @@ -966,8 +1810,8 @@ mod tests { }); _tile_loadconfig(config.as_ptr()); _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const u8, 64); - _tile_loadd::<2>(&twos as *const u8, 64); + _tile_loadd::<1>(ones.as_ptr(), 64); + _tile_loadd::<2>(twos.as_ptr(), 64); _tile_dphf8ps::<0, 1, 2>(); _tile_stored::<0>(res.as_mut_ptr().cast(), 64); _tile_release(); @@ -975,6 +1819,27 @@ mod tests { } } + #[simd_test(enable = "amx-fp8")] + fn test__tile_dphf8ps() { + unsafe { + _init_amx(); + let ones = [HF8_ONE; 1024]; + let twos = [HF8_TWO; 1024]; + let mut res = [[0.0_f32; 16]; 16]; + + let mut a = __tile1024i::zeroed(16, 64); + let mut b = __tile1024i::zeroed(16, 64); + let mut c = __tile1024i::zeroed(16, 64); + + __tile_loadd(&mut a, ones.as_ptr(), 64); + __tile_loadd(&mut b, twos.as_ptr(), 64); + __tile_dphf8ps(&mut c, a, b); + __tile_stored(res.as_mut_ptr().cast(), 64, c); + + assert_eq!(res, [[128.0_f32; 16]; 16]); + } + } + #[simd_test(enable = "amx-movrs")] fn test_tile_loaddrs() { unsafe { @@ -986,14 +1851,30 @@ mod tests { _tile_loadconfig(config.as_ptr()); _tile_zero::<0>(); let mat = [1_i8; 1024]; - _tile_loaddrs::<0>(&mat as *const i8 as *const u8, 64); + _tile_loaddrs::<0>(mat.as_ptr().cast(), 64); let mut out = [[0_i8; 64]; 16]; - _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); + _tile_stored::<0>(out.as_mut_ptr().cast(), 64); _tile_release(); assert_eq!(out, [[1; 64]; 16]); } } + #[simd_test(enable = "amx-movrs")] + fn test__tile_loaddrs() { + unsafe { + _init_amx(); + + let mut tile = __tile1024i::zeroed(16, 64); + + let mat = [1_i8; 1024]; + __tile_loaddrs(&mut tile, mat.as_ptr().cast(), 64); + let mut out = [[0_i8; 64]; 16]; + __tile_stored(out.as_mut_ptr().cast(), 64, tile); + + assert_eq!(out, [[1; 64]; 16]); + } + } + #[simd_test(enable = "amx-movrs")] fn test_tile_stream_loaddrs() { unsafe { @@ -1005,14 +1886,30 @@ mod tests { _tile_loadconfig(config.as_ptr()); _tile_zero::<0>(); let mat = [1_i8; 1024]; - _tile_stream_loaddrs::<0>(&mat as *const i8 as *const u8, 64); + _tile_stream_loaddrs::<0>(mat.as_ptr().cast(), 64); let mut out = [[0_i8; 64]; 16]; - _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); + _tile_stored::<0>(out.as_mut_ptr().cast(), 64); _tile_release(); assert_eq!(out, [[1; 64]; 16]); } } + #[simd_test(enable = "amx-movrs")] + fn test__tile_stream_loaddrs() { + unsafe { + _init_amx(); + + let mut tile = __tile1024i::zeroed(16, 64); + + let mat = [1_i8; 1024]; + __tile_stream_loaddrs(&mut tile, mat.as_ptr().cast(), 64); + let mut out = [[0_i8; 64]; 16]; + __tile_stored(out.as_mut_ptr().cast(), 64, tile); + + assert_eq!(out, [[1; 64]; 16]); + } + } + #[simd_test(enable = "amx-avx512,avx10.2")] fn test_tile_movrow() { unsafe { @@ -1032,6 +1929,66 @@ mod tests { } } + macro_rules! wrap_imm4 { + ($name:ident :: <$TILE:literal>, $row:expr) => { + match $row { + 0 => $name::<$TILE, 0>(), + 1 => $name::<$TILE, 1>(), + 2 => $name::<$TILE, 2>(), + 3 => $name::<$TILE, 3>(), + 4 => $name::<$TILE, 4>(), + 5 => $name::<$TILE, 5>(), + 6 => $name::<$TILE, 6>(), + 7 => $name::<$TILE, 7>(), + 8 => $name::<$TILE, 8>(), + 9 => $name::<$TILE, 9>(), + 10 => $name::<$TILE, 10>(), + 11 => $name::<$TILE, 11>(), + 12 => $name::<$TILE, 12>(), + 13 => $name::<$TILE, 13>(), + 14 => $name::<$TILE, 14>(), + 15 => $name::<$TILE, 15>(), + _ => panic!("row index out of range"), + } + }; + } + + #[simd_test(enable = "amx-avx512,avx10.2")] + fn test_tile_movrowi() { + unsafe { + _init_amx(); + let array: [[u8; 64]; 16] = array::from_fn(|i| [i as _; _]); + + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + + for i in 0..16 { + let row = wrap_imm4!(_tile_movrowi::<0>, i); + assert_eq!(*row.as_u8x64().as_array(), [i as _; _]); + } + } + } + + #[simd_test(enable = "amx-avx512,avx10.2")] + fn test__tile_movrow() { + unsafe { + _init_amx(); + let array: [[u8; 64]; 16] = array::from_fn(|i| [i as _; _]); + + let mut tile = __tile1024i::zeroed(16, 64); + __tile_loadd(&mut tile, array.as_ptr().cast(), 64); + + for i in 0..16 { + let row = __tile_movrow(tile, i); + assert_eq!(*row.as_u8x64().as_array(), [i as _; _]); + } + } + } + #[simd_test(enable = "amx-avx512,avx10.2")] fn test_tile_cvtrowd2ps() { unsafe { @@ -1051,6 +2008,42 @@ mod tests { } } + #[simd_test(enable = "amx-avx512,avx10.2")] + fn test_tile_cvtrowd2psi() { + unsafe { + _init_amx(); + let array: [[u32; 16]; 16] = array::from_fn(|i| [i as _; _]); + + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + + for i in 0..16 { + let row = wrap_imm4!(_tile_cvtrowd2psi::<0>, i); + assert_eq!(*row.as_f32x16().as_array(), [i as _; _]); + } + } + } + + #[simd_test(enable = "amx-avx512,avx10.2")] + fn test__tile_cvtrowd2ps() { + unsafe { + _init_amx(); + let array: [[u32; 16]; 16] = array::from_fn(|i| [i as _; _]); + + let mut tile = __tile1024i::zeroed(16, 64); + __tile_loadd(&mut tile, array.as_ptr().cast(), 64); + + for i in 0..16 { + let row = __tile_cvtrowd2ps(tile, i); + assert_eq!(*row.as_f32x16().as_array(), [i as _; _]); + } + } + } + #[simd_test(enable = "amx-avx512,avx10.2")] fn test_tile_cvtrowps2phh() { unsafe { @@ -1073,6 +2066,47 @@ mod tests { } } + #[simd_test(enable = "amx-avx512,avx10.2")] + fn test_tile_cvtrowps2phhi() { + unsafe { + _init_amx(); + let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); + + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + for i in 0..16 { + let row = wrap_imm4!(_tile_cvtrowps2phhi::<0>, i); + assert_eq!( + *row.as_f16x32().as_array(), + array::from_fn(|j| if j & 1 == 0 { 0.0 } else { i as _ }) + ); + } + } + } + + #[simd_test(enable = "amx-avx512,avx10.2")] + fn test__tile_cvtrowps2phh() { + unsafe { + _init_amx(); + let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); + + let mut tile = __tile1024i::zeroed(16, 64); + __tile_loadd(&mut tile, array.as_ptr().cast(), 64); + + for i in 0..16 { + let row = __tile_cvtrowps2phh(tile, i); + assert_eq!( + *row.as_f16x32().as_array(), + array::from_fn(|j| if j & 1 == 0 { 0.0 } else { i as _ }) + ); + } + } + } + #[simd_test(enable = "amx-avx512,avx10.2")] fn test_tile_cvtrowps2phl() { unsafe { @@ -1095,30 +2129,194 @@ mod tests { } } - #[simd_test(enable = "amx-tf32")] - fn test_tile_mmultf32ps() { + #[simd_test(enable = "amx-avx512,avx10.2")] + fn test_tile_cvtrowps2phli() { unsafe { _init_amx(); - let a: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); - let b: [[f32; 16]; 16] = [array::from_fn(|j| j as _); _]; - let mut res = [[0.0; 16]; 16]; + let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); let mut config = __tilecfg::default(); config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); + config.colsb[0] = 64; + config.rows[0] = 16; _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(a.as_ptr().cast(), 64); - _tile_loadd::<2>(b.as_ptr().cast(), 64); - _tile_mmultf32ps::<0, 1, 2>(); - _tile_stored::<0>(res.as_mut_ptr().cast(), 64); - _tile_release(); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + for i in 0..16 { + let row = wrap_imm4!(_tile_cvtrowps2phli::<0>, i); + assert_eq!( + *row.as_f16x32().as_array(), + array::from_fn(|j| if j & 1 == 0 { i as _ } else { 0.0 }) + ); + } + } + } + + #[simd_test(enable = "amx-avx512,avx10.2")] + fn test__tile_cvtrowps2phl() { + unsafe { + _init_amx(); + let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); + + let mut tile = __tile1024i::zeroed(16, 64); + __tile_loadd(&mut tile, array.as_ptr().cast(), 64); + + for i in 0..16 { + let row = __tile_cvtrowps2phl(tile, i); + assert_eq!( + *row.as_f16x32().as_array(), + array::from_fn(|j| if j & 1 == 0 { i as _ } else { 0.0 }) + ); + } + } + } - let expected = array::from_fn(|i| array::from_fn(|j| 16.0 * i as f32 * j as f32)); - assert_eq!(res, expected); + #[simd_test(enable = "amx-avx512,avx10.2")] + fn test_tile_cvtrowps2bf16h() { + unsafe { + _init_amx(); + let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); + + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + for i in 0..16 { + let row = _tile_cvtrowps2bf16h::<0>(i); + assert_eq!( + *row.as_u16x32().as_array(), + array::from_fn(|j| if j & 1 == 0 { + 0 + } else { + _mm_cvtness_sbh(i as _).to_bits() + }) + ); + } + } + } + + #[simd_test(enable = "amx-avx512,avx10.2")] + fn test_tile_cvtrowps2bf16hi() { + unsafe { + _init_amx(); + let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); + + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + for i in 0..16 { + let row = wrap_imm4!(_tile_cvtrowps2bf16hi::<0>, i); + assert_eq!( + *row.as_u16x32().as_array(), + array::from_fn(|j| if j & 1 == 0 { + 0 + } else { + _mm_cvtness_sbh(i as _).to_bits() + }) + ); + } + } + } + + #[simd_test(enable = "amx-avx512,avx10.2")] + fn test__tile_cvtrowps2bf16h() { + unsafe { + _init_amx(); + let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); + + let mut tile = __tile1024i::zeroed(16, 64); + __tile_loadd(&mut tile, array.as_ptr().cast(), 64); + + for i in 0..16 { + let row = __tile_cvtrowps2bf16h(tile, i); + assert_eq!( + *row.as_u16x32().as_array(), + array::from_fn(|j| if j & 1 == 0 { + 0 + } else { + _mm_cvtness_sbh(i as _).to_bits() + }) + ); + } + } + } + + #[simd_test(enable = "amx-avx512,avx10.2")] + fn test_tile_cvtrowps2bf16l() { + unsafe { + _init_amx(); + let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); + + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + for i in 0..16 { + let row = _tile_cvtrowps2bf16l::<0>(i); + assert_eq!( + *row.as_u16x32().as_array(), + array::from_fn(|j| if j & 1 == 0 { + _mm_cvtness_sbh(i as _).to_bits() + } else { + 0 + }) + ); + } + } + } + + #[simd_test(enable = "amx-avx512,avx10.2")] + fn test_tile_cvtrowps2bf16li() { + unsafe { + _init_amx(); + let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); + + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + for i in 0..16 { + let row = wrap_imm4!(_tile_cvtrowps2bf16li::<0>, i); + assert_eq!( + *row.as_u16x32().as_array(), + array::from_fn(|j| if j & 1 == 0 { + _mm_cvtness_sbh(i as _).to_bits() + } else { + 0 + }) + ); + } + } + } + + #[simd_test(enable = "amx-avx512,avx10.2")] + fn test__tile_cvtrowps2bf16l() { + unsafe { + _init_amx(); + let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); + + let mut tile = __tile1024i::zeroed(16, 64); + __tile_loadd(&mut tile, array.as_ptr().cast(), 64); + + for i in 0..16 { + let row = __tile_cvtrowps2bf16l(tile, i); + assert_eq!( + *row.as_u16x32().as_array(), + array::from_fn(|j| if j & 1 == 0 { + _mm_cvtness_sbh(i as _).to_bits() + } else { + 0 + }) + ); + } } } } diff --git a/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs b/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs index 0fd9b09363d4b..e26bfc5c1ca4f 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs @@ -527,7 +527,7 @@ pub fn _mm_cvtt_roundss_u64(a: __m128) -> u64 { } #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.avx512.vcvtss2si64"] fn vcvtss2si64(a: f32x4, rounding: i32) -> i64; #[link_name = "llvm.x86.avx512.vcvtss2usi64"] diff --git a/library/stdarch/crates/core_arch/src/x86_64/avx512fp16.rs b/library/stdarch/crates/core_arch/src/x86_64/avx512fp16.rs index 87e3651ba7441..5baf1c9036e19 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/avx512fp16.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/avx512fp16.rs @@ -10,7 +10,7 @@ use stdarch_test::assert_instr; #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsi2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvti64_sh(a: __m128h, b: i64) -> __m128h { unsafe { vcvtsi642sh(a, b, _MM_FROUND_CUR_DIRECTION) } } @@ -32,7 +32,7 @@ pub fn _mm_cvti64_sh(a: __m128h, b: i64) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsi2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundi64_sh(a: __m128h, b: i64) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -48,7 +48,7 @@ pub fn _mm_cvt_roundi64_sh(a: __m128h, b: i64) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtusi2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtu64_sh(a: __m128h, b: u64) -> __m128h { unsafe { vcvtusi642sh(a, b, _MM_FROUND_CUR_DIRECTION) } } @@ -70,7 +70,7 @@ pub fn _mm_cvtu64_sh(a: __m128h, b: u64) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtusi2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundu64_sh(a: __m128h, b: u64) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -85,7 +85,7 @@ pub fn _mm_cvt_roundu64_sh(a: __m128h, b: u64) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2si))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtsh_i64(a: __m128h) -> i64 { unsafe { vcvtsh2si64(a, _MM_FROUND_CUR_DIRECTION) } } @@ -106,7 +106,7 @@ pub fn _mm_cvtsh_i64(a: __m128h) -> i64 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2si, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundsh_i64(a: __m128h) -> i64 { unsafe { static_assert_rounding!(ROUNDING); @@ -121,7 +121,7 @@ pub fn _mm_cvt_roundsh_i64(a: __m128h) -> i64 { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2usi))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtsh_u64(a: __m128h) -> u64 { unsafe { vcvtsh2usi64(a, _MM_FROUND_CUR_DIRECTION) } } @@ -142,7 +142,7 @@ pub fn _mm_cvtsh_u64(a: __m128h) -> u64 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2usi, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundsh_u64(a: __m128h) -> u64 { unsafe { static_assert_rounding!(ROUNDING); @@ -157,7 +157,7 @@ pub fn _mm_cvt_roundsh_u64(a: __m128h) -> u64 { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2si))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttsh_i64(a: __m128h) -> i64 { unsafe { vcvttsh2si64(a, _MM_FROUND_CUR_DIRECTION) } } @@ -172,7 +172,7 @@ pub fn _mm_cvttsh_i64(a: __m128h) -> i64 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2si, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtt_roundsh_i64(a: __m128h) -> i64 { unsafe { static_assert_sae!(SAE); @@ -187,7 +187,7 @@ pub fn _mm_cvtt_roundsh_i64(a: __m128h) -> i64 { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2usi))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttsh_u64(a: __m128h) -> u64 { unsafe { vcvttsh2usi64(a, _MM_FROUND_CUR_DIRECTION) } } @@ -202,7 +202,7 @@ pub fn _mm_cvttsh_u64(a: __m128h) -> u64 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2usi, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtt_roundsh_u64(a: __m128h) -> u64 { unsafe { static_assert_sae!(SAE); @@ -211,7 +211,7 @@ pub fn _mm_cvtt_roundsh_u64(a: __m128h) -> u64 { } #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.avx512fp16.vcvtsi642sh"] fn vcvtsi642sh(a: __m128h, b: i64, rounding: i32) -> __m128h; #[link_name = "llvm.x86.avx512fp16.vcvtusi642sh"] diff --git a/library/stdarch/crates/core_arch/src/x86_64/bmi.rs b/library/stdarch/crates/core_arch/src/x86_64/bmi.rs index 8d2b22089ac10..d7f96bbc6708a 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/bmi.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/bmi.rs @@ -63,7 +63,7 @@ pub const fn _andn_u64(a: u64, b: u64) -> u64 { #[stable(feature = "simd_x86", since = "1.27.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _blsi_u64(x: u64) -> u64 { - x & x.wrapping_neg() + x.isolate_lowest_one() } /// Gets mask up to lowest set bit. @@ -122,7 +122,7 @@ pub const fn _mm_tzcnt_64(x: u64) -> i64 { x.trailing_zeros() as i64 } -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.bmi.bextr.64"] fn x86_bmi_bextr_64(x: u64, y: u64) -> u64; } diff --git a/library/stdarch/crates/core_arch/src/x86_64/bmi2.rs b/library/stdarch/crates/core_arch/src/x86_64/bmi2.rs index 6151eee8bdbb5..81ab9e05add96 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/bmi2.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/bmi2.rs @@ -69,7 +69,7 @@ pub fn _pext_u64(a: u64, mask: u64) -> u64 { unsafe { x86_bmi2_pext_64(a, mask) } } -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.bmi.bzhi.64"] fn x86_bmi2_bzhi_64(x: u64, y: u64) -> u64; #[link_name = "llvm.x86.bmi.pdep.64"] diff --git a/library/stdarch/crates/core_arch/src/x86_64/fxsr.rs b/library/stdarch/crates/core_arch/src/x86_64/fxsr.rs index 28bf1951167a5..f50dacb4bee4f 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/fxsr.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/fxsr.rs @@ -4,7 +4,7 @@ use stdarch_test::assert_instr; #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.fxsave64"] fn fxsave64(p: *mut u8); #[link_name = "llvm.x86.fxrstor64"] diff --git a/library/stdarch/crates/core_arch/src/x86_64/mod.rs b/library/stdarch/crates/core_arch/src/x86_64/mod.rs index c6dc7a85e7852..6f1177ad94636 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/mod.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/mod.rs @@ -3,6 +3,43 @@ #[macro_use] mod macros; +// Any 1024-byte vector should work +type Tile = crate::core_arch::simd::Simd; + +/// A tile register, used by AMX instructions. +/// +/// This type is the same as the `__tile1024i` type defined by Intel, representing a 1024-byte tile register. +/// Usage of this type typically corresponds to the `amx-tile` and up target features for x86_64. +/// +/// This struct contains the tile configuration information as well as the tile itself. +/// The tile configuration information consists of the row count and the size of each column in bytes, +/// with `row * colsb` never exceeding 1024. +/// +/// The typical usage pattern looks like +/// ```ignore +/// let tile = MaybeUninit::uninit(); +/// let tile_ptr = tile.as_mut_ptr(); +/// +/// (*tile_ptr).rows = rows; +/// (*tile_ptr).colsb = colsb; +/// __tile_zero(tile_ptr); +/// +/// let tile = tile.assume_init(); +/// ``` +/// Most intrinsics using `__tile1024i` (except for the store intrinsics) have a destination parameter +/// of type `*mut __tile1024i`, and it expects the `rows` and `colsb` fields of the destination +/// to be initialized. After the function call, the whole struct can be assumed to be initialized. +/// Moreover, for dot-product intrinsics, it is UB if the shape of two operands are not compatible +/// as a matrix product or if the shape of the destination doesn't match the expected shape. +#[derive(Copy, Clone, Debug)] +#[allow(non_camel_case_types)] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub struct __tile1024i { + pub rows: u16, + pub colsb: u16, + tile: Tile, +} + mod fxsr; #[stable(feature = "simd_x86", since = "1.27.0")] pub use self::fxsr::*; @@ -75,9 +112,13 @@ mod bt; pub use self::bt::*; mod avx512fp16; -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub use self::avx512fp16::*; mod amx; #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] pub use self::amx::*; + +mod movrs; +#[unstable(feature = "movrs_target_feature", issue = "137976")] +pub use self::movrs::*; diff --git a/library/stdarch/crates/core_arch/src/x86_64/movrs.rs b/library/stdarch/crates/core_arch/src/x86_64/movrs.rs new file mode 100644 index 0000000000000..fc669bbb1ca59 --- /dev/null +++ b/library/stdarch/crates/core_arch/src/x86_64/movrs.rs @@ -0,0 +1,94 @@ +//! Read-shared Move instructions + +#[cfg(test)] +use stdarch_test::assert_instr; + +unsafe extern "unadjusted" { + #[link_name = "llvm.x86.movrsqi"] + fn movrsqi(src: *const i8) -> i8; + #[link_name = "llvm.x86.movrshi"] + fn movrshi(src: *const i16) -> i16; + #[link_name = "llvm.x86.movrssi"] + fn movrssi(src: *const i32) -> i32; + #[link_name = "llvm.x86.movrsdi"] + fn movrsdi(src: *const i64) -> i64; +} + +/// Moves a byte from the source to the destination, with an indication that the source memory +/// location is likely to become read-shared by multiple processors, i.e., read in the future by at +/// least one other processor before it is written, assuming it is ever written in the future. +#[inline] +#[target_feature(enable = "movrs")] +#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(movrs))] +#[unstable(feature = "movrs_target_feature", issue = "137976")] +pub unsafe fn _movrs_i8(src: *const i8) -> i8 { + movrsqi(src) +} + +/// Moves a 16-bit word from the source to the destination, with an indication that the source memory +/// location is likely to become read-shared by multiple processors, i.e., read in the future by at +/// least one other processor before it is written, assuming it is ever written in the future. +#[inline] +#[target_feature(enable = "movrs")] +#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(movrs))] +#[unstable(feature = "movrs_target_feature", issue = "137976")] +pub unsafe fn _movrs_i16(src: *const i16) -> i16 { + movrshi(src) +} + +/// Moves a 32-bit doubleword from the source to the destination, with an indication that the source +/// memory location is likely to become read-shared by multiple processors, i.e., read in the future +/// by at least one other processor before it is written, assuming it is ever written in the future. +#[inline] +#[target_feature(enable = "movrs")] +#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(movrs))] +#[unstable(feature = "movrs_target_feature", issue = "137976")] +pub unsafe fn _movrs_i32(src: *const i32) -> i32 { + movrssi(src) +} + +/// Moves a 64-bit quadword from the source to the destination, with an indication that the source +/// memory location is likely to become read-shared by multiple processors, i.e., read in the future +/// by at least one other processor before it is written, assuming it is ever written in the future. +#[inline] +#[target_feature(enable = "movrs")] +#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(movrs))] +#[unstable(feature = "movrs_target_feature", issue = "137976")] +pub unsafe fn _movrs_i64(src: *const i64) -> i64 { + movrsdi(src) +} + +#[cfg(test)] +mod tests { + use stdarch_test::simd_test; + + use super::*; + + #[simd_test(enable = "movrs")] + fn test_movrs_i8() { + let x: i8 = 42; + let y = unsafe { _movrs_i8(&x) }; + assert_eq!(x, y); + } + + #[simd_test(enable = "movrs")] + fn test_movrs_i16() { + let x: i16 = 42; + let y = unsafe { _movrs_i16(&x) }; + assert_eq!(x, y); + } + + #[simd_test(enable = "movrs")] + fn test_movrs_i32() { + let x: i32 = 42; + let y = unsafe { _movrs_i32(&x) }; + assert_eq!(x, y); + } + + #[simd_test(enable = "movrs")] + fn test_movrs_i64() { + let x: i64 = 42; + let y = unsafe { _movrs_i64(&x) }; + assert_eq!(x, y); + } +} diff --git a/library/stdarch/crates/core_arch/src/x86_64/sse.rs b/library/stdarch/crates/core_arch/src/x86_64/sse.rs index 81e1070b55691..521652c126914 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/sse.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/sse.rs @@ -6,7 +6,7 @@ use crate::core_arch::x86::*; use stdarch_test::assert_instr; #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.sse.cvtss2si64"] fn cvtss2si64(a: __m128) -> i64; #[link_name = "llvm.x86.sse.cvttss2si64"] diff --git a/library/stdarch/crates/core_arch/src/x86_64/sse2.rs b/library/stdarch/crates/core_arch/src/x86_64/sse2.rs index 08dabf053d428..ba1d811fe5b20 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/sse2.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/sse2.rs @@ -6,7 +6,7 @@ use crate::core_arch::x86::*; use stdarch_test::assert_instr; #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.sse2.cvtsd2si64"] fn cvtsd2si64(a: __m128d) -> i64; #[link_name = "llvm.x86.sse2.cvttsd2si64"] @@ -59,7 +59,7 @@ pub fn _mm_cvttsd_si64x(a: __m128d) -> i64 { _mm_cvttsd_si64(a) } -/// Stores a 64-bit integer value in the specified memory location. +/// Stores a 64-bit integer value in an 8-byte aligned memory location. /// To minimize caching, the data is flagged as non-temporal (unlikely to be /// used again soon). /// diff --git a/library/stdarch/crates/core_arch/src/x86_64/sse42.rs b/library/stdarch/crates/core_arch/src/x86_64/sse42.rs index cd32c149aff5b..307e6167aabae 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/sse42.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/sse42.rs @@ -4,7 +4,7 @@ use stdarch_test::assert_instr; #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.sse42.crc32.64.64"] fn crc32_64_64(crc: u64, v: u64) -> u64; } diff --git a/library/stdarch/crates/core_arch/src/x86_64/tbm.rs b/library/stdarch/crates/core_arch/src/x86_64/tbm.rs index fe12538b07a06..b4ec50a66fa0b 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/tbm.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/tbm.rs @@ -13,7 +13,7 @@ #[cfg(test)] use stdarch_test::assert_instr; -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.tbm.bextri.u64"] fn bextri_u64(a: u64, control: u64) -> u64; } diff --git a/library/stdarch/crates/core_arch/src/x86_64/xsave.rs b/library/stdarch/crates/core_arch/src/x86_64/xsave.rs index 30a7123315e5f..c307d40073433 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/xsave.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/xsave.rs @@ -6,7 +6,7 @@ use stdarch_test::assert_instr; #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { #[link_name = "llvm.x86.xsave64"] fn xsave64(p: *mut u8, hi: u32, lo: u32); #[link_name = "llvm.x86.xrstor64"] diff --git a/library/stdarch/crates/intrinsic-test/Cargo.toml b/library/stdarch/crates/intrinsic-test/Cargo.toml index 2c0f53897e797..e5c9e44e6d32a 100644 --- a/library/stdarch/crates/intrinsic-test/Cargo.toml +++ b/library/stdarch/crates/intrinsic-test/Cargo.toml @@ -18,7 +18,7 @@ log = "0.4.11" pretty_env_logger = "0.5.0" rayon = "1.5.0" diff = "0.1.12" -itertools = "0.14.0" +itertools = "0.15.0" quick-xml = { version = "0.37.5", features = ["serialize", "overlapped-lists"] } serde-xml-rs = "0.8.0" regex = "1.11.1" diff --git a/library/stdarch/crates/intrinsic-test/missing_aarch64_be.txt b/library/stdarch/crates/intrinsic-test/missing_aarch64_be.txt deleted file mode 100644 index f3c4ffa3d0640..0000000000000 --- a/library/stdarch/crates/intrinsic-test/missing_aarch64_be.txt +++ /dev/null @@ -1,129 +0,0 @@ -# Bad LLVM codegen for BE in O2 in clang, and release in rust (https://github.com/llvm/llvm-project/issues/166190) -vcmla_lane_f16 -vcmla_laneq_f16 -vcmla_rot180_lane_f16 -vcmla_rot180_laneq_f16 -vcmla_rot270_lane_f16 -vcmla_rot270_laneq_f16 -vcmla_rot90_lane_f16 -vcmla_rot90_laneq_f16 -vcmlaq_lane_f16 -vcmlaq_laneq_f16 -vcmlaq_laneq_f32 -vcmlaq_rot180_lane_f16 -vcmlaq_rot180_laneq_f16 -vcmlaq_rot180_laneq_f32 -vcmlaq_rot270_lane_f16 -vcmlaq_rot270_laneq_f16 -vcmlaq_rot270_laneq_f32 -vcmlaq_rot90_lane_f16 -vcmlaq_rot90_laneq_f16 -vcmlaq_rot90_laneq_f32 -# Bad codegen for BE in O2 in clang, correct in rust. Same cause as above issue. -vdot_lane_s32 -vdot_lane_u32 -vdot_laneq_s32 -vdot_laneq_u32 -vdotq_lane_s32 -vdotq_lane_u32 -vdotq_laneq_s32 -vdotq_laneq_u32 -vsudot_lane_s32 -vsudot_laneq_s32 -vsudotq_lane_s32 -vsudotq_laneq_s32 -vusdot_lane_s32 -vusdot_laneq_s32 -vusdotq_lane_s32 -vusdotq_laneq_s32 - -# Below are in common to missing_aarch64.txt -# Not supported by qemu (will throw illegal instruction) -vamax_f16 -vamaxq_f16 -vamin_f16 -vaminq_f16 -vscale_f16 -vscale_f32 -vscaleq_f16 -vscaleq_f32 -vscaleq_f64 -vluti2_lane_p16 -vluti2_lane_p8 -vluti2_lane_s16 -vluti2_lane_s8 -vluti2_lane_u16 -vluti2_lane_u8 -vluti2q_lane_p16 -vluti2q_lane_p8 -vluti2q_lane_s16 -vluti2q_lane_s8 -vluti2q_lane_u16 -vluti2_laneq_f16 -vluti2_lane_f16 -vluti2_laneq_f16 -vluti2_laneq_p16 -vluti2_laneq_p8 -vluti2_laneq_s16 -vluti2_laneq_s8 -vluti2_laneq_u16 -vluti2_laneq_u8 -vluti2q_lane_f16 -vluti2q_laneq_f16 -vluti2q_laneq_p16 -vluti2q_laneq_p8 -vluti2q_laneq_s16 -vluti2q_laneq_s8 -vluti2q_laneq_u16 -vluti2q_laneq_u8 -vluti2q_lane_u8 - -# Not implemented in stdarch yet -vbfdot_f32 -vbfdot_lane_f32 -vbfdot_laneq_f32 -vbfdotq_f32 -vbfdotq_lane_f32 -vbfdotq_laneq_f32 -vbfmlalbq_f32 -vbfmlalbq_lane_f32 -vbfmlalbq_laneq_f32 -vbfmlaltq_f32 -vbfmlaltq_lane_f32 -vbfmlaltq_laneq_f32 -vbfmmlaq_f32 - - -# Implemented in stdarch, but missing in Clang. -vrnd32xq_f64 -vrnd32zq_f64 -vrnd64xq_f64 -vrnd64zq_f64 -vamin_f32 -vaminq_f32 -vaminq_f64 -vamax_f32 -vamaxq_f32 -vamaxq_f64 -# LLVM select error, and missing in Clang. -vrnd32x_f64 -vrnd32z_f64 -vrnd64x_f64 -vrnd64z_f64 -vluti4q_lane_f16_x2 -vluti4q_lane_p16_x2 -vluti4q_lane_p8 -vluti4q_lane_s16_x2 -vluti4q_lane_s8 -vluti4q_lane_u16_x2 -vluti4q_lane_u8 -vluti4q_laneq_f16_x2 -vluti4q_laneq_p16_x2 -vluti4q_laneq_p8 -vluti4q_laneq_s16_x2 -vluti4q_laneq_s8 -vluti4q_laneq_u16_x2 -vluti4q_laneq_u8 - -# Broken in Clang -vcvth_s16_f16 diff --git a/library/stdarch/crates/intrinsic-test/missing_aarch64_be_clang.txt b/library/stdarch/crates/intrinsic-test/missing_aarch64_be_clang.txt new file mode 100644 index 0000000000000..001538b3ea504 --- /dev/null +++ b/library/stdarch/crates/intrinsic-test/missing_aarch64_be_clang.txt @@ -0,0 +1,31 @@ +# Bad LLVM codegen for BE in O2 in clang, and release in rust (https://github.com/llvm/llvm-project/issues/166190) +vcmla_laneq_f16 +vcmla_rot180_laneq_f16 +vcmla_rot270_laneq_f16 +vcmla_rot90_laneq_f16 +vcmlaq_lane_f16 +vcmlaq_laneq_f16 +vcmlaq_rot180_lane_f16 +vcmlaq_rot180_laneq_f16 +vcmlaq_rot270_lane_f16 +vcmlaq_rot270_laneq_f16 +vcmlaq_rot90_lane_f16 +vcmlaq_rot90_laneq_f16 + +# Bad codegen for BE in O2 in clang, correct in rust. Same cause as above issue. +vdot_lane_s32 +vdot_lane_u32 +vdot_laneq_s32 +vdot_laneq_u32 +vdotq_lane_s32 +vdotq_lane_u32 +vdotq_laneq_s32 +vdotq_laneq_u32 +vsudot_lane_s32 +vsudot_laneq_s32 +vsudotq_lane_s32 +vsudotq_laneq_s32 +vusdot_lane_s32 +vusdot_laneq_s32 +vusdotq_lane_s32 +vusdotq_laneq_s32 diff --git a/library/stdarch/crates/intrinsic-test/missing_aarch64.txt b/library/stdarch/crates/intrinsic-test/missing_aarch64_be_common.txt similarity index 69% rename from library/stdarch/crates/intrinsic-test/missing_aarch64.txt rename to library/stdarch/crates/intrinsic-test/missing_aarch64_be_common.txt index 3c1ac59e910e9..327c8207a0ff5 100644 --- a/library/stdarch/crates/intrinsic-test/missing_aarch64.txt +++ b/library/stdarch/crates/intrinsic-test/missing_aarch64_be_common.txt @@ -1,8 +1,14 @@ # Not supported by qemu (will throw illegal instruction) -vamax_f16 -vamaxq_f16 vamin_f16 vaminq_f16 +vamin_f32 +vaminq_f32 +vaminq_f64 +vamax_f16 +vamaxq_f16 +vamax_f32 +vamaxq_f32 +vamaxq_f64 vscale_f16 vscale_f32 vscaleq_f16 @@ -37,39 +43,6 @@ vluti2q_laneq_s8 vluti2q_laneq_u16 vluti2q_laneq_u8 vluti2q_lane_u8 - -# Not implemented in stdarch yet -vbfdot_f32 -vbfdot_lane_f32 -vbfdot_laneq_f32 -vbfdotq_f32 -vbfdotq_lane_f32 -vbfdotq_laneq_f32 -vbfmlalbq_f32 -vbfmlalbq_lane_f32 -vbfmlalbq_laneq_f32 -vbfmlaltq_f32 -vbfmlaltq_lane_f32 -vbfmlaltq_laneq_f32 -vbfmmlaq_f32 - - -# Implemented in stdarch, but missing in Clang. -vrnd32xq_f64 -vrnd32zq_f64 -vrnd64xq_f64 -vrnd64zq_f64 -vamin_f32 -vaminq_f32 -vaminq_f64 -vamax_f32 -vamaxq_f32 -vamaxq_f64 -# LLVM select error, and missing in Clang. -vrnd32x_f64 -vrnd32z_f64 -vrnd64x_f64 -vrnd64z_f64 vluti4q_lane_f16_x2 vluti4q_lane_p16_x2 vluti4q_lane_p8 @@ -85,5 +58,24 @@ vluti4q_laneq_s8 vluti4q_laneq_u16_x2 vluti4q_laneq_u8 -# Broken in Clang -vcvth_s16_f16 +# Not implemented in stdarch yet +vcvtad_s32_f64 +vcvtad_u32_f64 +vcvtd_s32_f64 +vcvtd_u32_f64 +vcvtmd_s32_f64 +vcvtmd_u32_f64 +vcvtnd_s32_f64 +vcvtnd_u32_f64 +vcvtpd_s32_f64 +vcvtpd_u32_f64 +vcvts_s64_f32 +vcvts_u64_f32 +vcvtas_s64_f32 +vcvtas_u64_f32 +vcvtms_s64_f32 +vcvtms_u64_f32 +vcvtns_s64_f32 +vcvtns_u64_f32 +vcvtps_s64_f32 +vcvtps_u64_f32 diff --git a/library/stdarch/crates/intrinsic-test/missing_aarch64_be_gcc.txt b/library/stdarch/crates/intrinsic-test/missing_aarch64_be_gcc.txt new file mode 100644 index 0000000000000..eccd8a8a14dff --- /dev/null +++ b/library/stdarch/crates/intrinsic-test/missing_aarch64_be_gcc.txt @@ -0,0 +1,20 @@ +# Broken in LLVM llvm/llvm-project#196999 +vmull_p64 +vmull_high_p64 + +# Broken in LLVM llvm/llvm-project#197083 +vcvth_n_s32_f16 +vcvth_n_u32_f16 +vcvth_n_s64_f16 +vcvth_n_u64_f16 +vcvth_n_f16_s32 +vcvth_n_f16_u32 +vcvth_n_f16_s64 +vcvth_n_f16_u64 + +# Broken in GCC https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125279 +vmaxh_f16 +vminh_f16 + +# Rounding errors +vfms_n_f64 diff --git a/library/stdarch/crates/intrinsic-test/missing_aarch64_clang.txt b/library/stdarch/crates/intrinsic-test/missing_aarch64_clang.txt new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/library/stdarch/crates/intrinsic-test/missing_aarch64_common.txt b/library/stdarch/crates/intrinsic-test/missing_aarch64_common.txt new file mode 100644 index 0000000000000..327c8207a0ff5 --- /dev/null +++ b/library/stdarch/crates/intrinsic-test/missing_aarch64_common.txt @@ -0,0 +1,81 @@ +# Not supported by qemu (will throw illegal instruction) +vamin_f16 +vaminq_f16 +vamin_f32 +vaminq_f32 +vaminq_f64 +vamax_f16 +vamaxq_f16 +vamax_f32 +vamaxq_f32 +vamaxq_f64 +vscale_f16 +vscale_f32 +vscaleq_f16 +vscaleq_f32 +vscaleq_f64 +vluti2_lane_p16 +vluti2_lane_p8 +vluti2_lane_s16 +vluti2_lane_s8 +vluti2_lane_u16 +vluti2_lane_u8 +vluti2q_lane_p16 +vluti2q_lane_p8 +vluti2q_lane_s16 +vluti2q_lane_s8 +vluti2q_lane_u16 +vluti2_laneq_f16 +vluti2_lane_f16 +vluti2_laneq_f16 +vluti2_laneq_p16 +vluti2_laneq_p8 +vluti2_laneq_s16 +vluti2_laneq_s8 +vluti2_laneq_u16 +vluti2_laneq_u8 +vluti2q_lane_f16 +vluti2q_laneq_f16 +vluti2q_laneq_p16 +vluti2q_laneq_p8 +vluti2q_laneq_s16 +vluti2q_laneq_s8 +vluti2q_laneq_u16 +vluti2q_laneq_u8 +vluti2q_lane_u8 +vluti4q_lane_f16_x2 +vluti4q_lane_p16_x2 +vluti4q_lane_p8 +vluti4q_lane_s16_x2 +vluti4q_lane_s8 +vluti4q_lane_u16_x2 +vluti4q_lane_u8 +vluti4q_laneq_f16_x2 +vluti4q_laneq_p16_x2 +vluti4q_laneq_p8 +vluti4q_laneq_s16_x2 +vluti4q_laneq_s8 +vluti4q_laneq_u16_x2 +vluti4q_laneq_u8 + +# Not implemented in stdarch yet +vcvtad_s32_f64 +vcvtad_u32_f64 +vcvtd_s32_f64 +vcvtd_u32_f64 +vcvtmd_s32_f64 +vcvtmd_u32_f64 +vcvtnd_s32_f64 +vcvtnd_u32_f64 +vcvtpd_s32_f64 +vcvtpd_u32_f64 +vcvts_s64_f32 +vcvts_u64_f32 +vcvtas_s64_f32 +vcvtas_u64_f32 +vcvtms_s64_f32 +vcvtms_u64_f32 +vcvtns_s64_f32 +vcvtns_u64_f32 +vcvtps_s64_f32 +vcvtps_u64_f32 diff --git a/library/stdarch/crates/intrinsic-test/missing_aarch64_gcc.txt b/library/stdarch/crates/intrinsic-test/missing_aarch64_gcc.txt new file mode 100644 index 0000000000000..a7e90142e4bcd --- /dev/null +++ b/library/stdarch/crates/intrinsic-test/missing_aarch64_gcc.txt @@ -0,0 +1,19 @@ +# Broken in GCC https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123584, fixed in GCC 16 +vxarq_u64 + +# Broken in LLVM llvm/llvm-project#197083 +vcvth_n_s32_f16 +vcvth_n_u32_f16 +vcvth_n_s64_f16 +vcvth_n_u64_f16 +vcvth_n_f16_s32 +vcvth_n_f16_u32 +vcvth_n_f16_s64 +vcvth_n_f16_u64 + +# Broken in GCC https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125279 +vmaxh_f16 +vminh_f16 + +# Rounding errors +vfms_n_f64 diff --git a/library/stdarch/crates/intrinsic-test/missing_arm_clang.txt b/library/stdarch/crates/intrinsic-test/missing_arm_clang.txt new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/library/stdarch/crates/intrinsic-test/missing_arm.txt b/library/stdarch/crates/intrinsic-test/missing_arm_common.txt similarity index 95% rename from library/stdarch/crates/intrinsic-test/missing_arm.txt rename to library/stdarch/crates/intrinsic-test/missing_arm_common.txt index 04c09a27d90d4..165b45d50cf1f 100644 --- a/library/stdarch/crates/intrinsic-test/missing_arm.txt +++ b/library/stdarch/crates/intrinsic-test/missing_arm_common.txt @@ -1,18 +1,3 @@ -# Not implemented in stdarch yet -vbfdot_f32 -vbfdot_lane_f32 -vbfdot_laneq_f32 -vbfdotq_f32 -vbfdotq_lane_f32 -vbfdotq_laneq_f32 -vbfmlalbq_f32 -vbfmlalbq_lane_f32 -vbfmlalbq_laneq_f32 -vbfmlaltq_f32 -vbfmlaltq_lane_f32 -vbfmlaltq_laneq_f32 -vbfmmlaq_f32 - # Implemented in Clang and stdarch for A64 only even though CSV claims A32 support vaddq_p64 vbsl_p64 @@ -134,18 +119,6 @@ vcvth_f16_u32 vcvth_u32_f16 vcvth_n_f16_u32 vcvth_n_u32_f16 -vcvtah_s32_f16 -vcvtah_u32_f16 -vcvtmh_s32_f16 -vcvtmh_u32_f16 -vcvtpq_s16_f16 -vcvtpq_u16_f16 -vcvtp_s16_f16 -vcvtp_u16_f16 -vcvtph_s32_f16 -vcvtph_u32_f16 -vcvtnh_u32_f16 -vcvtnh_s32_f16 vfmlsl_low_f16 vfmlslq_low_f16 vfmlsl_high_f16 @@ -318,3 +291,25 @@ vcvta_s16_f16 vcvta_u16_f16 vceqz_f16 vceqzq_f16 +vcvtah_s32_f16 +vcvtah_u32_f16 +vcvtmh_s32_f16 +vcvtmh_u32_f16 +vcvtpq_s16_f16 +vcvtpq_u16_f16 +vcvtp_s16_f16 +vcvtp_u16_f16 +vcvtph_s32_f16 +vcvtph_u32_f16 +vcvtnh_u32_f16 +vcvtnh_s32_f16 + +# Missing in Clang +vusdot_laneq_s32 +vsudot_laneq_s32 +vusdotq_laneq_s32 +vsudotq_laneq_s32 +vdot_laneq_s32 +vdot_laneq_u32 +vdotq_laneq_s32 +vdotq_laneq_u32 diff --git a/library/stdarch/crates/intrinsic-test/missing_x86_clang.txt b/library/stdarch/crates/intrinsic-test/missing_x86_clang.txt new file mode 100644 index 0000000000000..b1531830c1a19 --- /dev/null +++ b/library/stdarch/crates/intrinsic-test/missing_x86_clang.txt @@ -0,0 +1,24 @@ +# not present in Clang +_bswap +_bswap64 +_mm_cvtsd_si64x +_mm_cvtsi128_si64x +_mm_cvtsi64x_sd +_mm_cvtsi64x_si128 +_mm_cvttsd_si64x +_popcnt32 +_popcnt64 + +# Clang bug +_mm512_mask_reduce_max_pd +_mm512_mask_reduce_max_ps +_mm512_mask_reduce_min_pd +_mm512_mask_reduce_min_ps + +# Rounding errors in release mode +_mm_maskz_fmadd_sd +_mm_maskz_fmadd_ss +_mm_maskz_fmsub_sd +_mm_maskz_fmsub_ss +_mm_maskz_fnmadd_sd +_mm_maskz_fnmadd_ss diff --git a/library/stdarch/crates/intrinsic-test/missing_x86.txt b/library/stdarch/crates/intrinsic-test/missing_x86_common.txt similarity index 52% rename from library/stdarch/crates/intrinsic-test/missing_x86.txt rename to library/stdarch/crates/intrinsic-test/missing_x86_common.txt index f88a125bfdff8..f9b71bbe8c2ca 100644 --- a/library/stdarch/crates/intrinsic-test/missing_x86.txt +++ b/library/stdarch/crates/intrinsic-test/missing_x86_common.txt @@ -1,19 +1,22 @@ -# Are defined under a similar name - -#__bswap_64 -_bswap64 - -# not present in Clang and Rust +# not present in Rust _bit_scan_forward _bit_scan_reverse _castf32_u32 _castf64_u64 _castu32_f32 _castu64_f64 +_cvtsh_ss +_cvtss_sh _lrotl _lrotr _may_i_use_cpu_feature _may_i_use_cpu_feature_ext +_mm256_set1_pch +_mm512_set1_pch +_mm_malloc +_mm_popcnt_u32 +_mm_popcnt_u64 +_mm_set1_pch _rdpmc _rotl _rotl64 @@ -21,47 +24,25 @@ _rotr _rotr64 _rotwl _rotwr -_urdmsr - -# not present in Clang -_bswap -_mm_cvtsd_si64x -_mm_cvtsi128_si64x -_mm_cvtsi64x_sd -_mm_cvtsi64x_si128 -_mm_cvttsd_si64x -_popcnt32 -_popcnt64 - -# not present in Rust -_cvtsh_ss -_cvtss_sh -_mm256_set1_pch -_mm512_set1_pch -_mm_malloc -_mm_popcnt_u32 -_mm_popcnt_u64 -_mm_set1_pch _tpause _umwait - -# IMM8 must be an even number in the range `0..=62` -_mm_sm3rnds2_epi32 +_urdmsr # SDE ERROR: Cannot execute XGETBV with ECX != 0 _xgetbv # top bits are undefined, unclear how to test these +_mm256_castph128_ph256 +_mm256_castps128_ps256 +_mm256_castpd128_pd256 _mm256_castsi128_si256 + +_mm512_castph128_ph512 +_mm512_castps128_ps512 +_mm512_castpd128_pd512 _mm512_castsi128_si512 -_mm512_castsi256_si512 -# Clang bug -_mm256_extract_epi16 -_mm256_extract_epi8 -_mm512_mask_reduce_max_pd -_mm512_mask_reduce_max_ps -_mm512_mask_reduce_min_pd -_mm512_mask_reduce_min_ps -_mm_extract_epi16 -_mm_extract_epi8 +_mm512_castph256_ph512 +_mm512_castps256_ps512 +_mm512_castpd256_pd512 +_mm512_castsi256_si512 diff --git a/library/stdarch/crates/intrinsic-test/missing_x86_gcc.txt b/library/stdarch/crates/intrinsic-test/missing_x86_gcc.txt new file mode 100644 index 0000000000000..5b71b0698eafc --- /dev/null +++ b/library/stdarch/crates/intrinsic-test/missing_x86_gcc.txt @@ -0,0 +1,33 @@ +# not present in GCC +_bextr2_u32 +_bextr2_u64 +_mm512_cvtepi32lo_pd +_mm512_mask_cvtepi32lo_pd +_mm512_cvtepu32lo_pd +_mm512_mask_cvtepu32lo_pd +_mm512_cvtpd_pslo +_mm512_mask_cvtpd_pslo +_mm512_cvtpslo_pd +_mm512_mask_cvtpslo_pd +_mm512_permutevar_epi32 +_mm512_mask_permutevar_epi32 +_mm_tzcnt_32 +_mm_tzcnt_64 + +# GCC bug +_mm512_reduce_max_pd +_mm512_reduce_max_ps +_mm512_reduce_min_pd +_mm512_reduce_min_ps +_mm512_mask_reduce_max_pd +_mm512_mask_reduce_max_ps +_mm512_mask_reduce_min_pd +_mm512_mask_reduce_min_ps + +# Rounding errors in release mode +_mm_maskz_fmadd_sd +_mm_maskz_fmadd_ss +_mm_maskz_fmsub_sd +_mm_maskz_fmsub_ss +_mm_maskz_fnmadd_sd +_mm_maskz_fnmadd_ss diff --git a/library/stdarch/crates/intrinsic-test/missing_x86_icx.txt b/library/stdarch/crates/intrinsic-test/missing_x86_icx.txt new file mode 100644 index 0000000000000..6d3133c85db9c --- /dev/null +++ b/library/stdarch/crates/intrinsic-test/missing_x86_icx.txt @@ -0,0 +1,20 @@ +# not present in ICX +_mm_cvtsd_si64x +_mm_cvtsi128_si64x +_mm_cvtsi64x_sd +_mm_cvtsi64x_si128 +_mm_cvttsd_si64x + +# ICX bug +_mm512_mask_reduce_max_pd +_mm512_mask_reduce_max_ps +_mm512_mask_reduce_min_pd +_mm512_mask_reduce_min_ps + +# Rounding errors in release mode +_mm_maskz_fmadd_sd +_mm_maskz_fmadd_ss +_mm_maskz_fmsub_sd +_mm_maskz_fmsub_ss +_mm_maskz_fnmadd_sd +_mm_maskz_fnmadd_ss diff --git a/library/stdarch/crates/intrinsic-test/src/arm/argument.rs b/library/stdarch/crates/intrinsic-test/src/arm/argument.rs deleted file mode 100644 index c43609bb2db0d..0000000000000 --- a/library/stdarch/crates/intrinsic-test/src/arm/argument.rs +++ /dev/null @@ -1,15 +0,0 @@ -use crate::arm::intrinsic::ArmIntrinsicType; -use crate::common::argument::Argument; - -// This functionality is present due to the nature -// of how intrinsics are defined in the JSON source -// of ARM intrinsics. -impl Argument { - pub fn type_and_name_from_c(arg: &str) -> (&str, &str) { - let split_index = arg - .rfind([' ', '*']) - .expect("Couldn't split type and argname"); - - (arg[..split_index + 1].trim_end(), &arg[split_index + 1..]) - } -} diff --git a/library/stdarch/crates/intrinsic-test/src/arm/compile.rs b/library/stdarch/crates/intrinsic-test/src/arm/compile.rs deleted file mode 100644 index 7da35f9a1114b..0000000000000 --- a/library/stdarch/crates/intrinsic-test/src/arm/compile.rs +++ /dev/null @@ -1,51 +0,0 @@ -use crate::common::cli::ProcessedCli; -use crate::common::compile_c::{CompilationCommandBuilder, CppCompilation}; - -pub fn build_cpp_compilation(config: &ProcessedCli) -> Option { - let cpp_compiler = config.cpp_compiler.as_ref()?; - - // -ffp-contract=off emulates Rust's approach of not fusing separate mul-add operations - let mut command = CompilationCommandBuilder::new() - .add_arch_flags(["armv8.6-a", "crypto", "crc", "dotprod", "fp16"]) - .set_compiler(cpp_compiler) - .set_target(&config.target) - .set_opt_level("2") - .set_cxx_toolchain_dir(config.cxx_toolchain_dir.as_deref()) - .set_project_root("c_programs") - .add_extra_flags(["-ffp-contract=off", "-Wno-narrowing"]); - - if !config.target.contains("v7") { - command = command.add_arch_flags(["faminmax", "lut", "sha3"]); - } - - if !cpp_compiler.contains("clang") { - command = command.add_extra_flag("-flax-vector-conversions"); - } - - let mut cpp_compiler = command.into_cpp_compilation(); - - if config.target.contains("aarch64_be") { - let Some(ref cxx_toolchain_dir) = config.cxx_toolchain_dir else { - panic!( - "target `{}` must specify `cxx_toolchain_dir`", - config.target - ) - }; - - cpp_compiler.command_mut().args([ - &format!("--sysroot={cxx_toolchain_dir}/aarch64_be-none-linux-gnu/libc"), - "--include-directory", - &format!("{cxx_toolchain_dir}/aarch64_be-none-linux-gnu/include/c++/14.3.1"), - "--include-directory", - &format!("{cxx_toolchain_dir}/aarch64_be-none-linux-gnu/include/c++/14.3.1/aarch64_be-none-linux-gnu"), - "-L", - &format!("{cxx_toolchain_dir}/lib/gcc/aarch64_be-none-linux-gnu/14.3.1"), - "-L", - &format!("{cxx_toolchain_dir}/aarch64_be-none-linux-gnu/libc/usr/lib"), - "-B", - &format!("{cxx_toolchain_dir}/lib/gcc/aarch64_be-none-linux-gnu/14.3.1"), - ]); - } - - Some(cpp_compiler) -} diff --git a/library/stdarch/crates/intrinsic-test/src/arm/config.rs b/library/stdarch/crates/intrinsic-test/src/arm/config.rs deleted file mode 100644 index 85cb21c2d6c4e..0000000000000 --- a/library/stdarch/crates/intrinsic-test/src/arm/config.rs +++ /dev/null @@ -1,70 +0,0 @@ -pub const NOTICE: &str = "\ -// This is a transient test file, not intended for distribution. Some aspects of the -// test are derived from a JSON specification, published under the same license as the -// `intrinsic-test` crate.\n"; - -pub const PLATFORM_C_FORWARD_DECLARATIONS: &str = r#" -#ifdef __aarch64__ -std::ostream& operator<<(std::ostream& os, poly128_t value); -#endif - -std::ostream& operator<<(std::ostream& os, float16_t value); -std::ostream& operator<<(std::ostream& os, uint8_t value); - -// T1 is the `To` type, T2 is the `From` type -template T1 cast(T2 x) { - static_assert(sizeof(T1) == sizeof(T2), "sizeof T1 and T2 must be the same"); - T1 ret{}; - memcpy(&ret, &x, sizeof(T1)); - return ret; -} -"#; - -pub const PLATFORM_C_DEFINITIONS: &str = r#" -#ifdef __aarch64__ -std::ostream& operator<<(std::ostream& os, poly128_t value) { - std::stringstream temp; - do { - int n = value % 10; - value /= 10; - temp << n; - } while (value != 0); - std::string tempstr(temp.str()); - std::string res(tempstr.rbegin(), tempstr.rend()); - os << res; - return os; -} - -#endif - -std::ostream& operator<<(std::ostream& os, float16_t value) { - os << static_cast(value); - return os; -} - -std::ostream& operator<<(std::ostream& os, uint8_t value) { - os << (unsigned int) value; - return os; -} -"#; - -pub const PLATFORM_RUST_DEFINITIONS: &str = ""; - -pub const PLATFORM_RUST_CFGS: &str = r#" -#![cfg_attr(target_arch = "arm", feature(stdarch_arm_neon_intrinsics))] -#![cfg_attr(target_arch = "arm", feature(stdarch_aarch32_crc32))] -#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_fcma))] -#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_dotprod))] -#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_i8mm))] -#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_sm4))] -#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_ftts))] -#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_aarch64_jscvt))] -#![feature(fmt_helpers_for_derive)] -#![feature(stdarch_neon_f16)] - -#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] -use core_arch::arch::aarch64::*; - -#[cfg(target_arch = "arm")] -use core_arch::arch::arm::*; -"#; diff --git a/library/stdarch/crates/intrinsic-test/src/arm/intrinsic.rs b/library/stdarch/crates/intrinsic-test/src/arm/intrinsic.rs index 29343bee4c300..bcbee3503b9ad 100644 --- a/library/stdarch/crates/intrinsic-test/src/arm/intrinsic.rs +++ b/library/stdarch/crates/intrinsic-test/src/arm/intrinsic.rs @@ -2,21 +2,18 @@ use crate::common::intrinsic_helpers::IntrinsicType; use std::ops::{Deref, DerefMut}; #[derive(Debug, Clone, PartialEq)] -pub struct ArmIntrinsicType { - pub data: IntrinsicType, - pub target: String, -} +pub struct ArmType(pub IntrinsicType); -impl Deref for ArmIntrinsicType { +impl Deref for ArmType { type Target = IntrinsicType; fn deref(&self) -> &Self::Target { - &self.data + &self.0 } } -impl DerefMut for ArmIntrinsicType { +impl DerefMut for ArmType { fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.data + &mut self.0 } } diff --git a/library/stdarch/crates/intrinsic-test/src/arm/json_parser.rs b/library/stdarch/crates/intrinsic-test/src/arm/json_parser.rs index 65c179ef0d083..013c20f2db594 100644 --- a/library/stdarch/crates/intrinsic-test/src/arm/json_parser.rs +++ b/library/stdarch/crates/intrinsic-test/src/arm/json_parser.rs @@ -1,8 +1,10 @@ -use super::intrinsic::ArmIntrinsicType; +use super::intrinsic::ArmType; +use crate::arm::Arm; +use crate::arm::types::parse_intrinsic_type; use crate::common::argument::{Argument, ArgumentList}; use crate::common::constraint::Constraint; use crate::common::intrinsic::Intrinsic; -use crate::common::intrinsic_helpers::IntrinsicType; +use crate::common::intrinsic_helpers::{IntrinsicType, TypeKind}; use serde::Deserialize; use serde_json::Value; use std::collections::HashMap; @@ -12,6 +14,8 @@ use std::path::Path; #[serde(deny_unknown_fields)] struct ReturnType { value: String, + #[serde(rename = "element_bit_size")] + _element_bit_size: Option, } #[derive(Deserialize, Debug)] @@ -50,57 +54,78 @@ struct JsonIntrinsic { args_prep: Option>, #[serde(rename = "Architectures")] architectures: Vec, + #[serde(rename = "instructions")] + _instructions: Option>>, } -pub fn get_neon_intrinsics( - filename: &Path, - target: &str, -) -> Result>, Box> { +pub fn get_intrinsics(filename: &Path) -> Result>, Box> { let file = std::fs::File::open(filename)?; let reader = std::io::BufReader::new(file); let json: Vec = serde_json::from_reader(reader).expect("Couldn't parse JSON"); let parsed = json .into_iter() - .filter_map(|intr| { - if intr.simd_isa == "Neon" { - Some(json_to_intrinsic(intr, target).expect("Couldn't parse JSON")) - } else { - None - } - }) + .map(|intr| json_to_intrinsic(intr).expect("Couldn't parse JSON")) .collect(); Ok(parsed) } fn json_to_intrinsic( mut intr: JsonIntrinsic, - target: &str, -) -> Result, Box> { +) -> Result, Box> { let name = intr.name.replace(['[', ']'], ""); - let results = ArmIntrinsicType::from_c(&intr.return_type.value, target)?; + let result_ty = ArmType(parse_intrinsic_type(&intr.return_type.value)?); let args = intr .arguments .into_iter() .enumerate() .map(|(i, arg)| { - let (type_name, arg_name) = Argument::::type_and_name_from_c(&arg); + let (type_name, arg_name) = { + let split_index = arg + .rfind([' ', '*']) + .expect("Couldn't split type and argname"); + + (arg[..split_index + 1].trim_end(), &arg[split_index + 1..]) + }; + + let arg_ty = parse_intrinsic_type(type_name) + .unwrap_or_else(|_| panic!("Failed to parse argument '{arg}'")); + let metadata = intr.args_prep.as_mut(); let metadata = metadata.and_then(|a| a.remove(arg_name)); let arg_prep: Option = metadata.and_then(|a| a.try_into().ok()); - let constraint: Option = arg_prep.and_then(|a| a.try_into().ok()); - let ty = ArmIntrinsicType::from_c(type_name, target) - .unwrap_or_else(|_| panic!("Failed to parse argument '{arg}'")); - - let mut arg = - Argument::::new(i, String::from(arg_name), ty, constraint); + let constraint: Option = + arg_prep.and_then(|a| a.try_into().ok()).or_else(|| { + if arg_ty.kind() == TypeKind::SvPattern { + Some(Constraint::SvPattern) + } else if arg_ty.kind() == TypeKind::SvPrefetchOp { + Some(Constraint::SvPrefetchOp) + } else if arg_name == "imm_rotation" { + if name.starts_with("svcadd_") || name.starts_with("svqcadd_") { + Some(Constraint::SvImmRotationAdd) + } else { + Some(Constraint::SvImmRotation) + } + } else { + None + } + }); + + let is_predicate = arg_name == "pg"; + let mut arg = Argument::::new( + i, + String::from(arg_name), + ArmType(arg_ty), + constraint, + is_predicate, + ); // The JSON doesn't list immediates as const let IntrinsicType { ref mut constant, .. - } = arg.ty.data; + } = *arg.ty; if arg.name.starts_with("imm") { *constant = true } @@ -108,13 +133,14 @@ fn json_to_intrinsic( }) .collect(); - let arguments = ArgumentList:: { args }; + let arguments = ArgumentList:: { args }; Ok(Intrinsic { name, arguments, - results, + results: result_ty, arch_tags: intr.architectures, + extension: intr.simd_isa, }) } diff --git a/library/stdarch/crates/intrinsic-test/src/arm/mod.rs b/library/stdarch/crates/intrinsic-test/src/arm/mod.rs index 99c8da854c506..9c2d0f336a7aa 100644 --- a/library/stdarch/crates/intrinsic-test/src/arm/mod.rs +++ b/library/stdarch/crates/intrinsic-test/src/arm/mod.rs @@ -1,51 +1,62 @@ -mod argument; -mod compile; -mod config; mod intrinsic; mod json_parser; mod types; -use crate::common::SupportedArchitectureTest; -use crate::common::cli::ProcessedCli; -use crate::common::compile_c::CppCompilation; +use crate::common::argument::Argument; +use crate::common::cli::{CcArgStyle, ProcessedCli}; use crate::common::intrinsic::Intrinsic; -use crate::common::intrinsic_helpers::TypeKind; -use intrinsic::ArmIntrinsicType; -use json_parser::get_neon_intrinsics; +use crate::common::intrinsic_helpers::{SimdLen, TypeDefinition, TypeKind}; +use crate::common::values::test_values_array_name; +use crate::common::{PASSES, PREDICATE_LOCAL, SupportedArchitecture}; +use intrinsic::ArmType; +use json_parser::get_intrinsics; -pub struct ArmArchitectureTest { - intrinsics: Vec>, - cli_options: ProcessedCli, -} - -impl SupportedArchitectureTest for ArmArchitectureTest { - type IntrinsicImpl = ArmIntrinsicType; +#[derive(PartialEq)] +pub struct Arm(Vec>); - fn cli_options(&self) -> &ProcessedCli { - &self.cli_options - } +impl SupportedArchitecture for Arm { + type Type = ArmType; - fn intrinsics(&self) -> &[Intrinsic] { - &self.intrinsics + fn intrinsics(&self) -> &[Intrinsic] { + &self.0 } - const NOTICE: &str = config::NOTICE; - - const PLATFORM_C_HEADERS: &[&str] = &["arm_neon.h", "arm_acle.h", "arm_fp16.h"]; - const PLATFORM_C_DEFINITIONS: &str = config::PLATFORM_C_DEFINITIONS; - const PLATFORM_C_FORWARD_DECLARATIONS: &str = config::PLATFORM_C_FORWARD_DECLARATIONS; + const NOTICE: &str = r#" +// This is a transient test file, not intended for distribution. Some aspects of the +// test are derived from a JSON specification, published under the same license as the +// `intrinsic-test` crate. +"#; - const PLATFORM_RUST_DEFINITIONS: &str = config::PLATFORM_RUST_DEFINITIONS; - const PLATFORM_RUST_CFGS: &str = config::PLATFORM_RUST_CFGS; + const C_PRELUDE: &str = r#" +#include +#include +#include +#ifdef __ARM_FEATURE_SVE +#include +#endif +"#; + const RUST_PRELUDE: &str = RUST_PRELUDE; - fn cpp_compilation(&self) -> Option { - compile::build_cpp_compilation(&self.cli_options) + fn c_compiler_flags(&self, cli_options: &ProcessedCli) -> Vec<&str> { + // GCC uses an extra `-` in the arch name + let big_endian = cli_options.target.starts_with("aarch64_be"); + let a32 = cli_options.target.starts_with("armv7"); + match cli_options.cc_arg_style { + CcArgStyle::Clang if !a32 && !big_endian => vec![ + "-march=armv8.6a+crypto+crc+dotprod+fp16+sve2-aes+sve2-sm4+sve2-sha3+sve2-bitperm+\ + f32mm+f64mm+sve2p1", + ], + CcArgStyle::Clang => vec!["-march=armv8.6a+crypto+crc+dotprod+fp16"], + // SVE tests aren't run under GCC so there are no target features added for SVE + CcArgStyle::Gcc => vec!["-march=armv8.6-a+crypto+crc+dotprod+fp16+sha3+sm4"], + } } - fn create(cli_options: ProcessedCli) -> Self { - let a32 = cli_options.target.contains("v7"); - let mut intrinsics = get_neon_intrinsics(&cli_options.filename, &cli_options.target) - .expect("Error parsing input file"); + fn create(cli_options: &ProcessedCli) -> Self { + let big_endian = cli_options.target.starts_with("aarch64_be"); + let a32 = cli_options.target.starts_with("armv7"); + let mut intrinsics = + get_intrinsics(&cli_options.filename).expect("Error parsing input file"); intrinsics.sort_by(|a, b| a.name.cmp(&b.name)); intrinsics.dedup(); @@ -55,22 +66,254 @@ impl SupportedArchitectureTest for ArmArchitectureTest { let intrinsics = intrinsics .into_iter() - // Not sure how we would compare intrinsic that returns void. + // Skip intrinsics that don't return a value. .filter(|i| i.results.kind() != TypeKind::Void) + // Skip bfloat intrinsics - not currently supported .filter(|i| i.results.kind() != TypeKind::BFloat) .filter(|i| !i.arguments.iter().any(|a| a.ty.kind() == TypeKind::BFloat)) + // Skip SVE intrinsics that have `f16` - not yet implemented! + .filter(|i| { + let has_f16_arg = i + .arguments + .iter() + .any(|a| a.ty.kind() == TypeKind::Float && a.ty.bit_len == Some(16)); + let has_sve_arg = i + .arguments + .iter() + .any(|a| a.ty.num_lanes() == SimdLen::Scalable); + !(has_f16_arg && has_sve_arg) + }) + .filter(|i| { + let has_f16_ret = + i.results.kind() == TypeKind::Float && i.results.bit_len == Some(16); + let has_sve_ret = i.results.num_lanes() == SimdLen::Scalable; + !(has_f16_ret && has_sve_ret) + }) + // Skip `svqcvtn{u,}n*_x2` intrinsics - not yet implemented! + .filter(|i| !(i.name.starts_with("svqcvtn") && i.name.ends_with("_x2"))) + // Skip `svqrshr{u,}n*_x2` intrinsics - not yet implemented! + .filter(|i| !(i.name.starts_with("svqrshrn") && i.name.ends_with("_x2"))) + .filter(|i| !(i.name.starts_with("svqrshrun") && i.name.ends_with("_x2"))) + // Skip `svclamp*` intrinsics - not yet implemented! + .filter(|i| !i.name.starts_with("svclamp")) + // Skip `svdot{_lane,}_{s,u}32_{s,u}16` intrinsics - not yet implemented! + .filter(|i| { + i.name != "svdot_lane_u32_u16" + && i.name != "svdot_lane_s32_s16" + && i.name != "svdot_u32_u16" + && i.name != "svdot_s32_s16" + }) + // Skip `svrevd*` intrinsics - not yet implemented! + .filter(|i| !i.name.starts_with("svrevd")) + // Skip `svpsel_lane_b*` intrinsics - not yet implemented! + .filter(|i| !i.name.starts_with("svpsel_lane_b")) + // Skip `svundef*` intrinsics - to avoid undefined behaviour in Rust, these return + // zeroed vectors in Rust, which are inherently going to be different than the + // undefined vectors returned by the C intrinsics. + .filter(|i| !i.name.starts_with("svundef")) + // These load intrinsics expect each element in the scalable vector `bases` argument to + // be able to be cast to a pointer, which we don't support generating tests for yet. + .filter(|i| !(i.name.starts_with("svld") && i.name.contains("_gather_"))) // Skip pointers for now, we would probably need to look at the return // type to work out how many elements we need to point to. .filter(|i| !i.arguments.iter().any(|a| a.is_ptr())) + // Skip intrinsics with 128-bit elements (e.g. `p128`) .filter(|i| !i.arguments.iter().any(|a| a.ty.inner_size() == 128)) + // Skip intrinsics from `--skip` .filter(|i| !cli_options.skip.contains(&i.name)) + // Skip A64-specific intrinsics on A32 .filter(|i| !(a32 && i.arch_tags == vec!["A64".to_string()])) + // Skip SVE intrinsics on big endian + .filter(|i| !(big_endian && (i.extension == "SVE" || i.extension == "SVE2"))) + // Skip SVE intrinsics when testing against GCC as our wrappers run into ICEs + // See + .filter(|i| { + !(matches!(cli_options.cc_arg_style, CcArgStyle::Gcc) + && (i.extension == "SVE" || i.extension == "SVE2")) + }) .take(sample_size) .collect::>(); - Self { - intrinsics, - cli_options, + Self(intrinsics) + } + + fn predicate_function(size: u32) -> String { + format!("svptrue_b{size}()") + } + + fn load_call(arg: &Argument, idx: usize) -> String { + let name = arg.generate_name(); + let load = arg.ty.load_function(); + let ptr = format!( + "{vals_name}.as_ptr().add((i+{idx}) % {PASSES}) as _", + vals_name = test_values_array_name(&arg.ty) + ); + + match arg.ty.num_lanes() { + // If the load is of a `svbool_t`, then we load a `svint8_t` and + SimdLen::Scalable if matches!(arg.ty.kind(), TypeKind::Bool) => { + format!( + r#" +let {name} = {load}({PREDICATE_LOCAL}, {ptr}); +let {name} = svcmpne_n_s8({PREDICATE_LOCAL}, {name}, 0); + "# + ) + } + // If this load is of a scalable vector, then prepend an additional argument + // containing the predicate for the load. + SimdLen::Scalable => format!("let {name} = {load}({PREDICATE_LOCAL}, {ptr});"), + SimdLen::Fixed(..) => format!("let {name} = {load}({ptr});"), } } } + +const RUST_PRELUDE: &str = r#" +#![cfg_attr(target_arch = "arm", feature(stdarch_arm_neon_intrinsics))] +#![cfg_attr(target_arch = "arm", feature(stdarch_aarch32_crc32))] +#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_fcma))] +#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_i8mm))] +#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_sm4))] +#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_ftts))] +#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_feat_lut))] +#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_fp8))] +#![cfg_attr(all(any(target_arch = "aarch64", target_arch = "arm64ec"), target_endian = "little"), feature(stdarch_aarch64_sve))] +#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(faminmax))] +#![feature(stdarch_neon_f16)] + +#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] +use core_arch::arch::aarch64::*; + +#[cfg(target_arch = "arm")] +use core_arch::arch::arm::*; + +#[cfg(all(any(target_arch = "aarch64", target_arch = "arm64ec"), target_endian = "little"))] +const fn svpattern_from_i32(value: i32) -> svpattern { + match value { + 0 => svpattern::SV_POW2, + 1 => svpattern::SV_VL1, + 2 => svpattern::SV_VL2, + 3 => svpattern::SV_VL3, + 4 => svpattern::SV_VL4, + 5 => svpattern::SV_VL5, + 6 => svpattern::SV_VL6, + 7 => svpattern::SV_VL7, + 8 => svpattern::SV_VL8, + 9 => svpattern::SV_VL16, + 10 => svpattern::SV_VL32, + 11 => svpattern::SV_VL64, + 12 => svpattern::SV_VL128, + 13 => svpattern::SV_VL256, + 29 => svpattern::SV_MUL4, + 30 => svpattern::SV_MUL3, + 31 => svpattern::SV_ALL, + _ => unreachable!(), + } +} + +#[cfg(all(any(target_arch = "aarch64", target_arch = "arm64ec"), target_endian = "little"))] +const fn svprfop_from_i32(value: i32) -> svprfop { + match value { + 0 => svprfop::SV_PLDL1KEEP, + 1 => svprfop::SV_PLDL1STRM, + 2 => svprfop::SV_PLDL2KEEP, + 3 => svprfop::SV_PLDL2STRM, + 4 => svprfop::SV_PLDL3KEEP, + 5 => svprfop::SV_PLDL3STRM, + 8 => svprfop::SV_PSTL1KEEP, + 9 => svprfop::SV_PSTL1STRM, + 10 => svprfop::SV_PSTL2KEEP, + 11 => svprfop::SV_PSTL2STRM, + 12 => svprfop::SV_PSTL3KEEP, + 13 => svprfop::SV_PSTL3STRM, + _ => unreachable!(), + } +} + +#[cfg(all(any(target_arch = "aarch64", target_arch = "arm64ec"), target_endian = "little"))] +fn svint8_to_slice(a: &svint8_t) -> &[i8] { + unsafe { + core::slice::from_raw_parts(core::ptr::from_ref(a).cast(), svcntb() as usize) + } +} + +#[cfg(all(any(target_arch = "aarch64", target_arch = "arm64ec"), target_endian = "little"))] +fn svuint8_to_slice(a: &svuint8_t) -> &[u8] { + unsafe { + core::slice::from_raw_parts(core::ptr::from_ref(a).cast(), svcntb() as usize) + } +} + +#[cfg(all(any(target_arch = "aarch64", target_arch = "arm64ec"), target_endian = "little"))] +fn svint16_to_slice(a: &svint16_t) -> &[i16] { + unsafe { + core::slice::from_raw_parts(core::ptr::from_ref(a).cast(), svcnth() as usize) + } +} + +#[cfg(all(any(target_arch = "aarch64", target_arch = "arm64ec"), target_endian = "little"))] +fn svuint16_to_slice(a: &svuint16_t) -> &[u16] { + unsafe { + core::slice::from_raw_parts(core::ptr::from_ref(a).cast(), svcnth() as usize) + } +} + +#[cfg(all(any(target_arch = "aarch64", target_arch = "arm64ec"), target_endian = "little"))] +fn svint32_to_slice(a: &svint32_t) -> &[i32] { + unsafe { + core::slice::from_raw_parts(core::ptr::from_ref(a).cast(), svcntw() as usize) + } +} + +#[cfg(all(any(target_arch = "aarch64", target_arch = "arm64ec"), target_endian = "little"))] +fn svuint32_to_slice(a: &svuint32_t) -> &[u32] { + unsafe { + core::slice::from_raw_parts(core::ptr::from_ref(a).cast(), svcntw() as usize) + } +} + +#[cfg(all(any(target_arch = "aarch64", target_arch = "arm64ec"), target_endian = "little"))] +fn svint64_to_slice(a: &svint64_t) -> &[i64] { + unsafe { + core::slice::from_raw_parts(core::ptr::from_ref(a).cast(), svcntd() as usize) + } +} + +#[cfg(all(any(target_arch = "aarch64", target_arch = "arm64ec"), target_endian = "little"))] +fn svuint64_to_slice(a: &svuint64_t) -> &[u64] { + unsafe { + core::slice::from_raw_parts(core::ptr::from_ref(a).cast(), svcntd() as usize) + } +} + +#[cfg(all(any(target_arch = "aarch64", target_arch = "arm64ec"), target_endian = "little"))] +fn svfloat32_to_slice(a: &svfloat32_t) -> &[NanEqF32] { + unsafe { + core::slice::from_raw_parts(core::ptr::from_ref(a).cast(), svcntw() as usize) + } +} + +#[cfg(all(any(target_arch = "aarch64", target_arch = "arm64ec"), target_endian = "little"))] +fn svfloat64_to_slice(a: &svfloat64_t) -> &[NanEqF64] { + unsafe { + core::slice::from_raw_parts(core::ptr::from_ref(a).cast(), svcntd() as usize) + } +} + +#[repr(transparent)] +#[derive(Copy,Clone,PartialEq,Eq)] +struct b8(u8); + +impl std::fmt::Debug for b8 { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + write!(f, "{:08b}", self.0) + } +} + +#[cfg(all(any(target_arch = "aarch64", target_arch = "arm64ec"), target_endian = "little"))] +fn svbool_to_slice(a: &svbool_t) -> &[b8] { + unsafe { + core::slice::from_raw_parts(core::ptr::from_ref(a).cast(), svcntd() as usize) + } +} + +"#; diff --git a/library/stdarch/crates/intrinsic-test/src/arm/types.rs b/library/stdarch/crates/intrinsic-test/src/arm/types.rs index 4be8d1e48b49a..cced3bc40c0e1 100644 --- a/library/stdarch/crates/intrinsic-test/src/arm/types.rs +++ b/library/stdarch/crates/intrinsic-test/src/arm/types.rs @@ -1,239 +1,265 @@ -use super::intrinsic::ArmIntrinsicType; -use crate::common::cli::Language; -use crate::common::indentation::Indentation; -use crate::common::intrinsic_helpers::{IntrinsicType, IntrinsicTypeDefinition, Sign, TypeKind}; +use super::intrinsic::ArmType; +use crate::common::intrinsic_helpers::{ + IntrinsicType, Sign, SimdLen, TypeDefinition, TypeKind, default_fixed_vector_comparison, +}; +use itertools::Itertools; -impl IntrinsicTypeDefinition for ArmIntrinsicType { +impl TypeDefinition for ArmType { /// Gets a string containing the typename for this type in C format. fn c_type(&self) -> String { let prefix = self.kind.c_prefix(); - let const_prefix = if self.constant { "const " } else { "" }; - - if let (Some(bit_len), simd_len, vec_len) = (self.bit_len, self.simd_len, self.vec_len) { - match (simd_len, vec_len) { - (None, None) => format!("{const_prefix}{prefix}{bit_len}_t"), - (Some(simd), None) => format!("{prefix}{bit_len}x{simd}_t"), - (Some(simd), Some(vec)) => format!("{prefix}{bit_len}x{simd}x{vec}_t"), - (None, Some(_)) => todo!("{self:#?}"), // Likely an invalid case + + match (self.bit_len, self.simd_len, self.vec_len) { + // e.g. `bool` + (Some(_), None, None) if matches!(self.kind, TypeKind::Bool) => { + format!("{prefix}") } - } else { - todo!("{self:#?}") + // e.g. `float32_t`, `int64_t` + (Some(bit_len), None, None) => format!("{prefix}{bit_len}_t"), + // e.g. `float32x2_t`, `int64x2_t` + (Some(bit_len), Some(SimdLen::Fixed(simd)), None) => { + format!("{prefix}{bit_len}x{simd}_t") + } + // e.g. `float32x2x3_t`, `int64x2x3_t` + (Some(bit_len), Some(SimdLen::Fixed(simd)), Some(vec)) => { + format!("{prefix}{bit_len}x{simd}x{vec}_t") + } + // e.g. `svbool_t` + (Some(_), Some(SimdLen::Scalable), None) if matches!(self.kind, TypeKind::Bool) => { + format!("sv{prefix}_t") + } + // e.g. `svfloat32_t`, `svint64_t` + (Some(bit_len), Some(SimdLen::Scalable), None) => format!("sv{prefix}{bit_len}_t"), + // e.g. `svfloat32x3_t`, `svint64x3_t` + (Some(bit_len), Some(SimdLen::Scalable), Some(vec)) => { + format!("sv{prefix}{bit_len}x{vec}_t") + } + _ => todo!("{self:#?}"), } } - fn c_single_vector_type(&self) -> String { - if let (Some(bit_len), Some(simd_len)) = (self.bit_len, self.simd_len) { - format!( - "{prefix}{bit_len}x{simd_len}_t", - prefix = self.kind.c_prefix() - ) - } else { - unreachable!("Shouldn't be called on this type") - } - } + fn rust_type(&self) -> String { + let rust_prefix = self.kind.rust_prefix(); + let c_prefix = self.kind.c_prefix(); - /// Determines the load function for this type. - fn get_load_function(&self, language: Language) -> String { - if let IntrinsicType { - kind: k, - bit_len: Some(bl), - simd_len, - vec_len, - .. - } = &self.data - { - let quad = if simd_len.unwrap_or(1) * bl > 64 { - "q" - } else { - "" - }; - - let choose_workaround = language == Language::C && self.target.contains("v7"); - format!( - "vld{len}{quad}_{type}{size}", - type = match k { - TypeKind::Int(Sign::Unsigned) => "u", - TypeKind::Int(Sign::Signed) => "s", - TypeKind::Float => "f", - // The ACLE doesn't support 64-bit polynomial loads on Armv7 - // if armv7 and bl == 64, use "s", else "p" - TypeKind::Poly => if choose_workaround && *bl == 64 {"s"} else {"p"}, - x => todo!("get_load_function TypeKind: {x:#?}"), - }, - size = bl, - quad = quad, - len = vec_len.unwrap_or(1), - ) - } else { - todo!("get_load_function IntrinsicType: {self:#?}") + match (self.bit_len, self.simd_len, self.vec_len) { + // e.g. `svpattern` + (None, _, _) => format!("{rust_prefix}"), + // e.g. `bool` + (Some(_), None, None) if matches!(self.kind, TypeKind::Bool) => { + format!("{rust_prefix}") + } + // e.g. `i32` + (Some(bit_len), None, None) => format!("{rust_prefix}{bit_len}"), + // e.g. `int32x2_t` + (Some(bit_len), Some(SimdLen::Fixed(simd)), None) => { + format!("{c_prefix}{bit_len}x{simd}_t") + } + // e.g. `int32x2x3_t` + (Some(bit_len), Some(SimdLen::Fixed(simd)), Some(vec)) => { + format!("{c_prefix}{bit_len}x{simd}x{vec}_t") + } + // e.g. `svbool_t` + (Some(_), Some(SimdLen::Scalable), None) if matches!(self.kind, TypeKind::Bool) => { + format!("sv{c_prefix}_t") + } + // e.g. `svint32_t` + (Some(bit_len), Some(SimdLen::Scalable), None) => format!("sv{c_prefix}{bit_len}_t"), + // e.g. `svint32x3_t` + (Some(bit_len), Some(SimdLen::Scalable), Some(vec)) => { + format!("sv{c_prefix}{bit_len}x{vec}_t") + } + (Some(_), None, Some(_)) => todo!("{self:#?}"), } } - /// Determines the get lane function for this type. - fn get_lane_function(&self) -> String { - if let IntrinsicType { - kind: k, - bit_len: Some(bl), - simd_len, - .. - } = &self.data - { - let quad = if (simd_len.unwrap_or(1) * bl) > 64 { - "q" - } else { - "" - }; - format!( - "vget{quad}_lane_{type}{size}", - type = match k { - TypeKind::Int(Sign::Unsigned) => "u", - TypeKind::Int(Sign::Signed) => "s", - TypeKind::Float => "f", - TypeKind::Poly => "p", - x => todo!("get_load_function TypeKind: {x:#?}"), - }, - size = bl, - quad = quad, - ) + fn rust_scalar_type_for_test_value_array(&self) -> String { + if self.kind() == TypeKind::Bool && self.num_lanes() == SimdLen::Scalable { + let mut ty = self.clone(); + ty.kind = TypeKind::Int(Sign::Signed); + ty.rust_scalar_type() } else { - todo!("get_lane_function IntrinsicType: {self:#?}") + self.rust_scalar_type() } } - /// Generates a std::cout for the intrinsics results that will match the - /// rust debug output format for the return type. The generated line assumes - /// there is an int i in scope which is the current pass number. - fn print_result_c(&self, indentation: Indentation, additional: &str) -> String { - let lanes = if self.num_vectors() > 1 { - (0..self.num_vectors()) - .map(|vector| { + /// Determines the load function for this type. + fn load_function(&self) -> String { + if let Some(bl) = self.bit_len { + match self.num_lanes() { + SimdLen::Scalable => { + format!( + "svld{len}_{type}{bl}", + len = self.num_vectors(), + type = self.rust_intrinsic_name_prefix(), + ) + } + SimdLen::Fixed(num_lanes) => { format!( - r#""{ty}(" << {lanes} << ")""#, - ty = self.c_single_vector_type(), - lanes = (0..self.num_lanes()) - .map(move |idx| -> std::string::String { - let lane_fn = self.get_lane_function(); - let final_cast = self.generate_final_type_cast(); - format!( - "{final_cast}{lane_fn}(__return_value.val[{vector}], {idx})" - ) - }) - .collect::>() - .join(r#" << ", " << "#) + "vld{len}{quad}_{type}{bl}", + quad = if num_lanes * bl > 64 { "q" } else { "" }, + len = self.num_vectors(), + type = self.rust_intrinsic_name_prefix(), ) - }) - .collect::>() - .join(r#" << ", " << "#) - } else if self.num_lanes() > 1 { - (0..self.num_lanes()) - .map(|idx| -> std::string::String { - let lane_fn = self.get_lane_function(); - let final_cast = self.generate_final_type_cast(); - format!("{final_cast}{lane_fn}(__return_value, {idx})") - }) - .collect::>() - .join(r#" << ", " << "#) + } + } } else { + todo!("load_function IntrinsicType: {self:#?}") + } + } + + fn comparison_function(&self) -> String { + if let SimdLen::Fixed(num_lanes) = self.num_lanes() { + return default_fixed_vector_comparison(self, num_lanes); + } + + // Returns `of` when `num_vectors == 1` otherwise returns the appropriate `svget` invocation + // for `of`. + let get = |num_vectors: u32, idx: u32, from: &'static str| -> String { + if num_vectors == 1 { + return from.to_string(); + } + format!( - "{promote}cast<{cast}>(__return_value)", - cast = match self.kind() { - TypeKind::Float if self.inner_size() == 16 => "float16_t".to_string(), - TypeKind::Float if self.inner_size() == 32 => "float".to_string(), - TypeKind::Float if self.inner_size() == 64 => "double".to_string(), - TypeKind::Int(Sign::Signed) => format!("int{}_t", self.inner_size()), - TypeKind::Int(Sign::Unsigned) => format!("uint{}_t", self.inner_size()), - TypeKind::Poly => format!("poly{}_t", self.inner_size()), - ty => todo!("print_result_c - Unknown type: {ty:#?}"), - }, - promote = self.generate_final_type_cast(), + "svget{num_vectors}_{ty}{bl}::<{idx}>({from})", + ty = self.rust_intrinsic_name_prefix(), + bl = self.inner_size(), ) }; - format!( - r#"{indentation}std::cout << "Result {additional}-" << i+1 << ": {ty}" << std::fixed << std::setprecision(150) << {lanes} << "{close}" << std::endl;"#, - ty = if self.is_simd() { - format!("{}(", self.c_type()) - } else { - String::from("") - }, - close = if self.is_simd() { ")" } else { "" }, - ) + let prefix = match self.kind { + TypeKind::Bool => "svbool".to_owned(), + kind => format!("sv{}{}", kind.c_prefix(), self.inner_size()), + }; + + let n = self.num_vectors(); + (0..n) + .format_with("\n", |i, fmt| { + fmt(&format_args!( + r#" +assert_eq!( + {prefix}_to_slice(&{rust_return_value}), + {prefix}_to_slice(&{c_return_value}), + "{{id}}-({i_plus_one}/{n})" +); +"#, + rust_return_value = get(n, i, "__rust_return_value"), + c_return_value = get(n, i, "__c_return_value"), + i_plus_one = i + 1, // so that the output is "1/2" and "2/2" + )) + }) + .to_string() } } -impl ArmIntrinsicType { - pub fn from_c(s: &str, target: &str) -> Result { - const CONST_STR: &str = "const"; - if let Some(s) = s.strip_suffix('*') { - let (s, constant) = match s.trim().strip_suffix(CONST_STR) { - Some(stripped) => (stripped, true), - None => (s, false), - }; - let s = s.trim_end(); - let temp_return = ArmIntrinsicType::from_c(s, target); - temp_return.map(|mut op| { - op.ptr = true; - op.ptr_constant = constant; - op - }) - } else { - // [const ]TYPE[{bitlen}[x{simdlen}[x{vec_len}]]][_t] - let (mut s, constant) = match s.strip_prefix(CONST_STR) { - Some(stripped) => (stripped.trim(), true), - None => (s, false), - }; - s = s.strip_suffix("_t").unwrap_or(s); - let mut parts = s.split('x'); // [[{bitlen}], [{simdlen}], [{vec_len}] ] - let start = parts.next().ok_or("Impossible to parse type")?; - if let Some(digit_start) = start.find(|c: char| c.is_ascii_digit()) { - let (arg_kind, bit_len) = start.split_at(digit_start); - let arg_kind = arg_kind.parse::()?; - let bit_len = bit_len.parse::().map_err(|err| err.to_string())?; - let simd_len = match parts.next() { - Some(part) => Some( - part.parse::() - .map_err(|_| "Couldn't parse simd_len: {part}")?, - ), - None => None, - }; - let vec_len = match parts.next() { - Some(part) => Some( - part.parse::() - .map_err(|_| "Couldn't parse vec_len: {part}")?, - ), - None => None, - }; - Ok(ArmIntrinsicType { - data: IntrinsicType { - ptr: false, - ptr_constant: false, - constant, - kind: arg_kind, - bit_len: Some(bit_len), - simd_len, - vec_len, - }, - target: target.to_string(), - }) - } else { - let kind = start.parse::()?; - let bit_len = match kind { - TypeKind::Int(_) => Some(32), - _ => None, - }; - Ok(ArmIntrinsicType { - data: IntrinsicType { - ptr: false, - ptr_constant: false, - constant, - kind: start.parse::()?, - bit_len, - simd_len: None, - vec_len: None, - }, - target: target.to_string(), - }) - } +impl ArmType { + /// Returns the Rust prefix for the name of an intrinsic with this type kind (i.e. `s` for + /// `i16`, or `u` for `u16`). For type kinds without any bit length at the end (e.g. `bool`), + /// returns the whole type name. + pub fn rust_intrinsic_name_prefix(&self) -> &str { + match self.kind() { + TypeKind::Char(Sign::Signed) => "s", + TypeKind::Int(Sign::Signed) => "s", + TypeKind::Poly => "p", + TypeKind::Bool => "s", + _ => self.kind.rust_prefix(), } } } + +pub fn parse_intrinsic_type(s: &str) -> Result { + const CONST_STR: &str = "const"; + const ENUM_STR: &str = "enum "; + + // Recurse to handle pointers.. + if let Some(s) = s.strip_suffix('*') { + let s = s.trim(); + let (s, constant) = if s.ends_with(CONST_STR) || s.starts_with(CONST_STR) { + ( + s.trim_start_matches(CONST_STR).trim_end_matches(CONST_STR), + true, + ) + } else { + (s, false) + }; + + let mut ty = parse_intrinsic_type(s.trim())?; + ty.ptr = true; + ty.ptr_constant = constant; + return Ok(ty); + } + + // [const ][sv]TYPE[{element_bits}[x{num_lanes}[x{num_vecs}]]][_t] + // | [enum ]TYPE + let (mut s, constant) = match (s.strip_prefix(CONST_STR), s.strip_prefix(ENUM_STR)) { + (Some(const_strip), _) => (const_strip, true), + (_, Some(enum_strip)) => (enum_strip, true), + (None, None) => (s, false), + }; + s = s.trim(); + s = s.strip_suffix("_t").unwrap_or(s); + + // Consider the following types as examples: + // A) `svuint32x3_t` + // B) `float16x4x2_t` + // C) `svbool_t` + + let sve = s.starts_with("sv"); + + let mut parts = s.split('x'); + let start = parts.next().ok_or("failed to parse type")?; + + // Continuing the previous examples.. + // A) kind=TypeKind::Int(Sign::Unsigned), bit_len=Some(32) + // B) kind=TypeKind::Float, bit_len=Some(16) + // C) kind=TypeKind::Bool, bit_len=None + let (kind, bit_len) = if let Some(digit_start) = start.find(|c: char| c.is_ascii_digit()) { + let (element_kind, element_bits) = start.split_at(digit_start); + let element_kind = element_kind.parse::()?; + let element_bits = element_bits.parse::().map_err(|err| err.to_string())?; + (element_kind, Some(element_bits)) + } else { + let element_kind = start.parse::()?; + (element_kind, None) + }; + + let bit_len = match (bit_len, kind) { + (None, TypeKind::SvPattern | TypeKind::SvPrefetchOp | TypeKind::Int(_)) => Some(32), + (None, TypeKind::Bool) => Some(8), + _ => bit_len, + }; + + // Continuing the previous examples.. + // A) second_len=Some(3) + // B) second_len=Some(4) + // C) second_len=None + let second_len = parts.next().map(|part| { + part.parse::() + .expect("failed to parse second part of type") + }); + + // Continuing the previous examples.. + // A) third_len=None + // B) third_len=Some(2) + // C) third_len=None + let third_len = parts.next().map(|part| { + part.parse::() + .expect("failed to parse third part of type") + }); + + let (simd_len, vec_len) = if sve { + (Some(SimdLen::Scalable), second_len) + } else { + (second_len.map(SimdLen::Fixed), third_len) + }; + + Ok(IntrinsicType { + ptr: false, + ptr_constant: false, + constant, + kind, + bit_len, + simd_len, + vec_len, + }) +} diff --git a/library/stdarch/crates/intrinsic-test/src/common/argument.rs b/library/stdarch/crates/intrinsic-test/src/common/argument.rs index 385cf32d3bff9..10d9224183377 100644 --- a/library/stdarch/crates/intrinsic-test/src/common/argument.rs +++ b/library/stdarch/crates/intrinsic-test/src/common/argument.rs @@ -1,41 +1,60 @@ -use super::cli::Language; +use itertools::Itertools; + +use crate::common::SupportedArchitecture; +use crate::common::intrinsic_helpers::TypeKind; +use crate::common::values::test_values_array_name; + use super::constraint::Constraint; -use super::indentation::Indentation; -use super::intrinsic_helpers::IntrinsicTypeDefinition; +use super::intrinsic_helpers::TypeDefinition; +use super::{PASSES, PREDICATE_LOCAL}; /// An argument for the intrinsic. #[derive(Debug, PartialEq, Clone)] -pub struct Argument { +pub struct Argument { /// The argument's index in the intrinsic function call. pub pos: usize, /// The argument name. pub name: String, /// The type of the argument. - pub ty: T, + pub ty: A::Type, /// Any constraints that are on this argument pub constraint: Option, + /// Is the argument a predicate for a scalable intrinsic? + pub is_predicate: bool, } -impl Argument +impl Argument where - T: IntrinsicTypeDefinition, + A: SupportedArchitecture, { - pub fn new(pos: usize, name: String, ty: T, constraint: Option) -> Self { + pub fn new( + pos: usize, + name: String, + ty: A::Type, + constraint: Option, + is_predicate: bool, + ) -> Self { Argument { pos, name, ty, constraint, + is_predicate, } } pub fn to_c_type(&self) -> String { - let prefix = if self.ty.constant { "const " } else { "" }; - format!("{prefix}{}", self.ty.c_type()) + self.ty.c_type() } + /// Generates local variable name for the value passed to this argument pub fn generate_name(&self) -> String { - format!("{}_val", self.name) + // The same predicate is used for scalable intrinsic invocations + if self.is_predicate { + format!("{PREDICATE_LOCAL}") + } else { + format!("{}_val", self.name) + } } pub fn is_simd(&self) -> bool { @@ -50,170 +69,146 @@ where self.constraint.is_some() } - /// The binding keyword (e.g. "const" or "let") for the array of possible test inputs. - fn rust_vals_array_binding(&self) -> impl std::fmt::Display { - if self.ty.is_rust_vals_array_const() { - "const" - } else { - "let" - } - } - - /// The name (e.g. "A_VALS" or "a_vals") for the array of possible test inputs. - pub(crate) fn rust_vals_array_name(&self) -> impl std::fmt::Display { - if self.ty.is_rust_vals_array_const() { - let loads = crate::common::gen_rust::PASSES; - format!( - "{}_{ty}_{load_size}", - self.name.to_uppercase(), - ty = self.ty.rust_scalar_type(), - load_size = self.ty.num_lanes() * self.ty.num_vectors() + loads - 1, - ) - } else { - format!("{}_vals", self.name.to_lowercase()) - } - } - - fn as_call_param_c(&self) -> String { - self.ty.as_call_param_c(&self.generate_name()) + /// Should this argument be passed by reference in C wrapper function declarations? + /// + /// SIMD types and `f16` are currently passed by reference. + pub(crate) fn pass_by_ref(&self) -> bool { + self.is_simd() || (self.ty.kind() == TypeKind::Float && self.ty.inner_size() == 16) } } +/// Arguments of an intrinsic - including parameters that end up being const generics. #[derive(Debug, PartialEq, Clone)] -pub struct ArgumentList { - pub args: Vec>, +pub struct ArgumentList { + pub args: Vec>, } -impl ArgumentList +impl ArgumentList where - T: IntrinsicTypeDefinition, + A: SupportedArchitecture, { - /// Converts the argument list into the call parameters for a C function call. - /// e.g. this would generate something like `a, &b, c` - pub fn as_call_param_c(&self) -> String { + /// Returns a string with the arguments in `self` as a parameter list for a wrapper fn + /// definition in C (e.g. `$ty1 $arg1, $ty2 $arg2`). + /// + /// Skips arguments with constraints - which correspond to arguments that must take immediates - + /// as a different C definition will be generated for each value of these being tested. + pub fn as_non_imm_arglist_c(&self) -> String { self.iter() - .map(|arg| arg.as_call_param_c()) - .collect::>() - .join(", ") + .filter(|arg| !arg.has_constraint()) + .format_with("", |arg, fmt| { + if arg.pass_by_ref() { + fmt(&format_args!(", const {}* {}", arg.to_c_type(), arg.name)) + } else { + fmt(&format_args!(", {} {}", arg.to_c_type(), arg.name)) + } + }) + .to_string() } - /// Converts the argument list into the call parameters for a Rust function. - /// e.g. this would generate something like `a, b, c` - pub fn as_call_param_rust(&self) -> String { + /// Returns a string with the arguments in `self` as a parameter list for a Rust declaration of + /// a C wrapper fn (e.g. `$arg1: $ty1, $arg2: $ty2`). + /// + /// Skips arguments with constraints - which correspond to arguments that must take immediates - + /// as a different C definition will be generated for each value of these being tested. + pub fn as_non_imm_arglist_rust(&self) -> String { self.iter() - .filter(|a| !a.has_constraint()) - .map(|arg| arg.generate_name() + " as _") - .collect::>() - .join(", ") - } - - /// Creates a line for each argument that initializes an array for C from which `loads` argument - /// values can be loaded as a sliding window. - /// e.g `const int32x2_t a_vals = {0x3effffff, 0x3effffff, 0x3f7fffff}`, if loads=2. - pub fn gen_arglists_c( - &self, - w: &mut impl std::io::Write, - indentation: Indentation, - loads: u32, - ) -> std::io::Result<()> { - for arg in self.iter().filter(|&arg| !arg.has_constraint()) { - // Setting the variables on an aligned boundary to make it easier to pick - // functions (of a specific architecture) that would help load the values. - writeln!( - w, - "{indentation}alignas(64) const {ty} {name}_vals[] = {values};", - ty = arg.ty.c_scalar_type(), - name = arg.generate_name(), - values = arg.ty.populate_random(indentation, loads, &Language::C) - )? - } - - Ok(()) + .filter(|arg| !arg.has_constraint()) + .format_with("", |arg, fmt| { + if arg.pass_by_ref() { + fmt(&format_args!( + ", {}: *const {}", + arg.name, + arg.ty.rust_type() + )) + } else { + fmt(&format_args!(", {}: {}", arg.name, arg.ty.rust_type())) + } + }) + .to_string() } - /// Creates a line for each argument that initializes an array for Rust from which `loads` argument - /// values can be loaded as a sliding window, e.g `const A_VALS: [u32; 20] = [...];` - pub fn gen_arglists_rust( - &self, - w: &mut impl std::io::Write, - indentation: Indentation, - loads: u32, - ) -> std::io::Result<()> { - for arg in self.iter().filter(|&arg| !arg.has_constraint()) { - // Constants are defined globally. - if arg.ty.is_rust_vals_array_const() { - continue; - } - - Self::gen_arg_rust(arg, w, indentation, loads)?; - } - - Ok(()) + /// Returns a string with the arguments in `self` being passed to an intrinsic call in C + /// (e.g. `$arg1, 2 /* imm_args[0] */, $arg3` where `$arg2` has a constraint). + pub fn as_call_params_c(&self, imm_args: &[i64]) -> String { + let mut imm_args = imm_args.iter(); + self.iter() + .format_with(", ", |arg, fmt| { + if arg.has_constraint() { + fmt(&imm_args.next().unwrap()) + } else { + if arg.pass_by_ref() { + fmt(&"*")?; + } + fmt(&arg.name) + } + }) + .to_string() } - pub fn gen_arg_rust( - arg: &Argument, - w: &mut impl std::io::Write, - indentation: Indentation, - loads: u32, - ) -> std::io::Result<()> { - writeln!( - w, - "{indentation}{bind} {name}: [{ty}; {load_size}] = {values};\n", - bind = arg.rust_vals_array_binding(), - name = arg.rust_vals_array_name(), - ty = arg.ty.rust_scalar_type(), - load_size = arg.ty.num_lanes() * arg.ty.num_vectors() + loads - 1, - values = arg.ty.populate_random(indentation, loads, &Language::Rust) - ) + /// Returns a string with the arguments in `self` being passed to an intrinsic call in Rust. + /// (e.g. `$arg1, $arg3` where `$arg2` has a constraint and so corresponds to a const generic + /// parameter). + pub fn as_call_param_rust(&self) -> String { + self.iter() + .filter(|a| !a.has_constraint()) + .map(|arg| arg.generate_name()) + .join(", ") } - /// Creates a line for each argument that initializes the argument from an array `[arg]_vals` at - /// an offset `i` using a load intrinsic, in C. - /// e.g `uint8x8_t a = vld1_u8(&a_vals[i]);` - /// - /// ARM-specific - pub fn load_values_c(&self, indentation: Indentation) -> String { + /// Returns a string with the arguments in `self` being passed to the declaration of a C wrapper + /// fn from Rust (e.g. `$arg1, $arg3` (where `$arg2` has a constraint and so corresponds to a + /// const generic parameter). + pub fn as_c_call_param_rust(&self) -> String { self.iter() - .filter(|&arg| !arg.has_constraint()) + .filter(|a| !a.has_constraint()) .map(|arg| { - format!( - "{indentation}{ty} {name} = cast<{ty}>({load}(&{name}_vals[i]));\n", - ty = arg.to_c_type(), - name = arg.generate_name(), - load = if arg.is_simd() { - arg.ty.get_load_function(Language::C) - } else { - "*".to_string() - } - ) + if arg.pass_by_ref() { + format!(", &raw const {}", arg.generate_name()) + } else { + format!(", {}", arg.generate_name()) + } }) - .collect() + .join("") } - /// Creates a line for each argument that initializes the argument from array `[ARG]_VALS` at - /// an offset `i` using a load intrinsic, in Rust. - /// e.g `let a = vld1_u8(A_VALS.as_ptr().offset(i));` - pub fn load_values_rust(&self, indentation: Indentation) -> String { + /// Returns a string defining a local variable for each argument and loading a value into each + /// using a load intrinsic. + /// + /// e.g. + /// ```rust,ignore + /// let a = vld1_u8(I16_23.as_ptr().offset((i + 0 /* idx */) % 20 /* PASSES */)); + /// ```` + /// + /// The generator will have already generated arrays of appropriate length with values that can + /// be used for testing (see the `gen_args_rust` function). + /// + /// Each load is assumed to have a variable `i` in scope which comes from a loop which repeats + /// the testing of the intrinsic for different values - each subsequent `i` shifts the window + /// of values being loaded along the pre-prepared array. + /// + /// Each subsequent argument's first window is started one element further into the array + /// then the previous. + pub fn load_values_rust(&self) -> String { self.iter() .filter(|&arg| !arg.has_constraint()) - .map(|arg| { - let load = if arg.is_simd() { - arg.ty.get_load_function(Language::Rust) + .filter(|&arg| !arg.is_predicate) + .enumerate() + .map(|(idx, arg)| { + if arg.is_simd() { + A::load_call(arg, idx) } else { - "*".to_string() - }; - let typecast = if load.len() > 2 { "as _" } else { "" }; - format!( - "{indentation}let {name} = {load}({vals_name}.as_ptr().offset(i){typecast});\n", - name = arg.generate_name(), - vals_name = arg.rust_vals_array_name(), - ) + format!( + "let {name} = {vals_name}[(i+{idx}) % {PASSES}];", + name = arg.generate_name(), + vals_name = test_values_array_name(&arg.ty), + ) + } }) .collect() } - pub fn iter(&self) -> std::slice::Iter<'_, Argument> { + /// Returns an iterator over the contained arguments + pub fn iter(&self) -> std::slice::Iter<'_, Argument> { self.args.iter() } } diff --git a/library/stdarch/crates/intrinsic-test/src/common/cli.rs b/library/stdarch/crates/intrinsic-test/src/common/cli.rs index bed8259de8b6d..3ea87df51fda2 100644 --- a/library/stdarch/crates/intrinsic-test/src/common/cli.rs +++ b/library/stdarch/crates/intrinsic-test/src/common/cli.rs @@ -1,12 +1,6 @@ use itertools::Itertools; use std::path::PathBuf; -#[derive(Debug, PartialEq)] -pub enum Language { - Rust, - C, -} - /// Intrinsic test tool #[derive(clap::Parser)] #[command( @@ -17,104 +11,62 @@ pub struct Cli { /// The input file containing the intrinsics pub input: PathBuf, - /// The rust toolchain to use for building the rust code - #[arg(long)] - pub toolchain: Option, - - /// The C++ compiler to use for compiling the c++ code - #[arg(long, default_value_t = String::from("clang++"))] - pub cppcompiler: String, - - /// Run the C programs under emulation with this command - #[arg(long)] - pub runner: Option, - /// Filename for a list of intrinsics to skip (one per line) #[arg(long)] - pub skip: Option, - - /// Regenerate test programs, but don't build or run them - #[arg(long)] - pub generate_only: bool, + pub skip: Vec, /// Pass a target the test suite - #[arg(long, default_value_t = String::from("armv7-unknown-linux-gnueabihf"))] + #[arg(long)] pub target: String, - /// Pass a profile (release, dev) - #[arg(long, default_value_t = String::from("release"))] - pub profile: String, - - /// Set the linker - #[arg(long)] - pub linker: Option, + /// Percentage of intrinsics to test (used to limit testing to keep CI times manageable) + #[arg(long, default_value_t = 100u8)] + pub sample_percentage: u8, - /// Set the sysroot for the C++ compiler + /// Argument style of the C compiler #[arg(long)] - pub cxx_toolchain_dir: Option, + pub cc_arg_style: CcArgStyle, +} - #[arg(long, default_value_t = 100u8)] - pub sample_percentage: u8, +#[derive(Copy, Clone, clap::ValueEnum)] +pub enum CcArgStyle { + Gcc, + Clang, } pub struct ProcessedCli { pub filename: PathBuf, - pub toolchain: Option, - pub cpp_compiler: Option, - pub runner: String, pub target: String, - pub profile: String, - pub linker: Option, - pub cxx_toolchain_dir: Option, pub skip: Vec, pub sample_percentage: u8, + pub cc_arg_style: CcArgStyle, } impl ProcessedCli { pub fn new(cli_options: Cli) -> Self { let filename = cli_options.input; - let runner = cli_options.runner.unwrap_or_default(); let target = cli_options.target; - let profile = cli_options.profile; - let linker = cli_options.linker; - let cxx_toolchain_dir = cli_options.cxx_toolchain_dir; let sample_percentage = cli_options.sample_percentage; - let skip = if let Some(filename) = cli_options.skip { - let data = std::fs::read_to_string(&filename).expect("Failed to open file"); - data.lines() - .map(str::trim) - .filter(|s| !s.contains('#')) - .map(String::from) - .collect_vec() - } else { - Default::default() - }; - - let (toolchain, cpp_compiler) = if cli_options.generate_only { - (None, None) - } else { - ( - Some( - cli_options - .toolchain - .map_or_else(String::new, |t| format!("+{t}")), - ), - Some(cli_options.cppcompiler), - ) - }; + let skip = cli_options + .skip + .iter() + .flat_map(|filename| { + std::fs::read_to_string(&filename) + .expect("Failed to open file") + .lines() + .map(|line| line.trim().to_owned()) + .filter(|line| !line.contains('#')) + .collect_vec() + }) + .collect_vec(); Self { - toolchain, - cpp_compiler, - runner, target, - profile, - linker, - cxx_toolchain_dir, skip, filename, sample_percentage, + cc_arg_style: cli_options.cc_arg_style, } } } diff --git a/library/stdarch/crates/intrinsic-test/src/common/compare.rs b/library/stdarch/crates/intrinsic-test/src/common/compare.rs deleted file mode 100644 index 5214349171591..0000000000000 --- a/library/stdarch/crates/intrinsic-test/src/common/compare.rs +++ /dev/null @@ -1,129 +0,0 @@ -use itertools::Itertools; -use rayon::prelude::*; -use std::{collections::HashMap, process::Command}; - -pub const INTRINSIC_DELIMITER: &str = "############"; -fn runner_command(runner: &str) -> Command { - let mut it = runner.split_whitespace(); - let mut cmd = Command::new(it.next().unwrap()); - cmd.args(it); - - cmd -} - -pub fn compare_outputs( - intrinsic_name_list: &Vec, - runner: &str, - target: &str, - profile: &str, -) -> bool { - let profile_dir = match profile { - "dev" => "debug", - _ => "release", - }; - - let (c, rust) = rayon::join( - || { - runner_command(runner) - .arg("./intrinsic-test-programs") - .current_dir("c_programs") - .output() - }, - || { - runner_command(runner) - .arg(format!( - "./target/{target}/{profile_dir}/intrinsic-test-programs" - )) - .current_dir("rust_programs") - .output() - }, - ); - let (c, rust) = match (c, rust) { - (Ok(c), Ok(rust)) => (c, rust), - failure => panic!("Failed to run: {failure:#?}"), - }; - - if !c.status.success() { - error!( - "Failed to run C program.\nstdout: {stdout}\nstderr: {stderr}", - stdout = std::str::from_utf8(&c.stdout).unwrap_or(""), - stderr = std::str::from_utf8(&c.stderr).unwrap_or(""), - ); - } - - if !rust.status.success() { - error!( - "Failed to run Rust program.\nstdout: {stdout}\nstderr: {stderr}", - stdout = std::str::from_utf8(&rust.stdout).unwrap_or(""), - stderr = std::str::from_utf8(&rust.stderr).unwrap_or(""), - ); - } - - info!("Completed running C++ and Rust test binaries"); - let c = std::str::from_utf8(&c.stdout) - .unwrap() - .to_lowercase() - .replace("-nan", "nan"); - let rust = std::str::from_utf8(&rust.stdout) - .unwrap() - .to_lowercase() - .replace("-nan", "nan"); - - let c_output_map = c - .split(INTRINSIC_DELIMITER) - .filter_map(|output| output.trim().split_once("\n")) - .collect::>(); - let rust_output_map = rust - .split(INTRINSIC_DELIMITER) - .filter_map(|output| output.trim().split_once("\n")) - .collect::>(); - - let intrinsics = c_output_map - .keys() - .chain(rust_output_map.keys()) - .unique() - .collect_vec(); - - info!("Comparing outputs"); - let intrinsics_diff_count = intrinsics - .par_iter() - .filter_map(|&&intrinsic| { - let c_output = c_output_map.get(intrinsic).unwrap(); - let rust_output = rust_output_map.get(intrinsic).unwrap(); - if rust_output.eq(c_output) { - None - } else { - let diff = diff::lines(c_output, rust_output); - let diffs = diff - .into_iter() - .filter_map(|diff| match diff { - diff::Result::Left(_) | diff::Result::Right(_) => Some(diff), - diff::Result::Both(_, _) => None, - }) - .collect_vec(); - if diffs.len() > 0 { - Some((intrinsic, diffs)) - } else { - None - } - } - }) - .inspect(|(intrinsic, diffs)| { - println!("Difference for intrinsic: {intrinsic}"); - diffs.into_iter().for_each(|diff| match diff { - diff::Result::Left(c) => println!("C: {c}"), - diff::Result::Right(rust) => println!("Rust: {rust}"), - _ => (), - }); - println!("****************************************************************"); - }) - .count(); - - println!( - "{} differences found (tested {} intrinsics)", - intrinsics_diff_count, - intrinsic_name_list.len() - ); - - intrinsics_diff_count == 0 -} diff --git a/library/stdarch/crates/intrinsic-test/src/common/compile_c.rs b/library/stdarch/crates/intrinsic-test/src/common/compile_c.rs deleted file mode 100644 index fa78b332a7857..0000000000000 --- a/library/stdarch/crates/intrinsic-test/src/common/compile_c.rs +++ /dev/null @@ -1,136 +0,0 @@ -#[derive(Clone)] -pub struct CompilationCommandBuilder { - compiler: String, - target: Option, - cxx_toolchain_dir: Option, - arch_flags: Vec, - optimization: String, - project_root: Option, - extra_flags: Vec, -} - -impl CompilationCommandBuilder { - pub fn new() -> Self { - Self { - compiler: String::new(), - target: None, - cxx_toolchain_dir: None, - arch_flags: Vec::new(), - optimization: "2".to_string(), - project_root: None, - extra_flags: Vec::new(), - } - } - - pub fn set_compiler(mut self, compiler: &str) -> Self { - self.compiler = compiler.to_string(); - self - } - - pub fn set_target(mut self, target: &str) -> Self { - self.target = Some(target.to_string()); - self - } - - pub fn set_cxx_toolchain_dir(mut self, path: Option<&str>) -> Self { - self.cxx_toolchain_dir = path.map(|p| p.to_string()); - self - } - - pub fn add_arch_flags<'a>(mut self, flags: impl IntoIterator) -> Self { - self.arch_flags - .extend(flags.into_iter().map(|s| s.to_owned())); - - self - } - - pub fn set_opt_level(mut self, optimization: &str) -> Self { - self.optimization = optimization.to_string(); - self - } - - /// Sets the root path of all the generated test files. - pub fn set_project_root(mut self, path: &str) -> Self { - self.project_root = Some(path.to_string()); - self - } - - pub fn add_extra_flags<'a>(mut self, flags: impl IntoIterator) -> Self { - self.extra_flags - .extend(flags.into_iter().map(|s| s.to_owned())); - - self - } - - pub fn add_extra_flag(self, flag: &str) -> Self { - self.add_extra_flags([flag]) - } -} - -impl CompilationCommandBuilder { - pub fn into_cpp_compilation(self) -> CppCompilation { - let mut cpp_compiler = std::process::Command::new(self.compiler); - - if let Some(project_root) = self.project_root { - cpp_compiler.current_dir(project_root); - } - - let flags = std::env::var("CPPFLAGS").unwrap_or("".into()); - cpp_compiler.args(flags.split_whitespace()); - - cpp_compiler.arg(format!("-march={}", self.arch_flags.join("+"))); - - cpp_compiler.arg(format!("-O{}", self.optimization)); - - cpp_compiler.args(self.extra_flags); - - if let Some(target) = &self.target { - cpp_compiler.arg(format!("--target={target}")); - } - - CppCompilation(cpp_compiler) - } -} - -pub struct CppCompilation(std::process::Command); - -fn clone_command(command: &std::process::Command) -> std::process::Command { - let mut cmd = std::process::Command::new(command.get_program()); - if let Some(current_dir) = command.get_current_dir() { - cmd.current_dir(current_dir); - } - cmd.args(command.get_args()); - - for (key, val) in command.get_envs() { - cmd.env(key, val.unwrap_or_default()); - } - - cmd -} - -impl CppCompilation { - pub fn command_mut(&mut self) -> &mut std::process::Command { - &mut self.0 - } - - pub fn compile_object_file( - &self, - input: &str, - output: &str, - ) -> std::io::Result { - let mut cmd = clone_command(&self.0); - cmd.args([input, "-v", "-c", "-o", output]); - cmd.output() - } - - pub fn link_executable( - &self, - inputs: impl Iterator, - output: &str, - ) -> std::io::Result { - let mut cmd = clone_command(&self.0); - cmd.args(inputs); - cmd.args(["-o", output]); - cmd.output() - } -} diff --git a/library/stdarch/crates/intrinsic-test/src/common/constraint.rs b/library/stdarch/crates/intrinsic-test/src/common/constraint.rs index 5984e0fcc22f9..c7d37da2adcbb 100644 --- a/library/stdarch/crates/intrinsic-test/src/common/constraint.rs +++ b/library/stdarch/crates/intrinsic-test/src/common/constraint.rs @@ -1,24 +1,76 @@ -use serde::Deserialize; use std::ops::Range; -/// Describes the values to test for a const generic parameter. +use serde::Deserialize; + +/// Describes the values to test for a const generic parameter #[derive(Debug, PartialEq, Clone, Deserialize)] pub enum Constraint { - /// Test a single value. + /// Test a single value Equal(i64), /// Test a range of values, e.g. `0..16`. Range(Range), /// Test discrete values, e.g. `vec![1, 2, 4, 8]`. Set(Vec), + /// Values of `core::arch::aarch64::svpattern` + SvPattern, + /// Values of `core::arch::aarch64::svprfop` + SvPrefetchOp, + // Values of the `imm_rotation` argument in SVE intrinsics where arguments contain complex + // pairs and `imm_rotation` corresponds to the rotation. + SvImmRotation, + // Values of the `imm_rotation` argument in SVE intrinsics where arguments contain complex + // pairs and `imm_rotation` corresponds to the rotation (this variant is specifically for + // `svcadd` and `svqcadd` where only 90 and 270 are valid arguments). + SvImmRotationAdd, +} + +/// Workaround to enable the `Constraint::into_iter` to return an iterator that implements `Clone`, +/// so that it can be used with `Itertools::multi_cartesian_product`. +/// +/// With the different iterator types, returning `Box + '_>` would the +/// idiomatic approach, but this can't be made to implement `Clone`. Given the limited number +/// of iterator types used and their relative lack of complexity, wrapping them all in an enum isn't +/// too bad. +#[derive(Clone)] +pub enum ConstraintIterator<'a> { + Once(std::iter::Once), + Range(std::ops::Range), + Copied(std::iter::Copied>), + Chain(std::iter::Chain, std::ops::RangeInclusive>), + StepBy(std::iter::StepBy>), +} + +impl<'a> Iterator for ConstraintIterator<'a> { + type Item = i64; + + fn next(&mut self) -> Option { + match self { + ConstraintIterator::Once(once) => once.next(), + ConstraintIterator::Range(range) => range.next(), + ConstraintIterator::Copied(copied) => copied.next(), + ConstraintIterator::Chain(chain) => chain.next(), + ConstraintIterator::StepBy(step_by) => step_by.next(), + } + } } -impl Constraint { - /// Iterate over the values of this constraint. - pub fn iter<'a>(&'a self) -> impl Iterator + 'a { +impl<'a> IntoIterator for &'a Constraint { + type Item = i64; + type IntoIter = ConstraintIterator<'a>; + + fn into_iter(self) -> Self::IntoIter { match self { - Constraint::Equal(i) => std::slice::Iter::default().copied().chain(*i..*i + 1), - Constraint::Range(range) => std::slice::Iter::default().copied().chain(range.clone()), - Constraint::Set(items) => items.iter().copied().chain(std::ops::Range::default()), + Constraint::Equal(i) => ConstraintIterator::Once(std::iter::once(*i)), + Constraint::Range(range) => ConstraintIterator::Range(range.clone()), + Constraint::Set(items) => ConstraintIterator::Copied(items.iter().copied()), + // These values are discriminants of the `svpattern` enum + Constraint::SvPattern => ConstraintIterator::Chain((0..=13).chain(29..=31)), + // These values are discriminants of the `svprfop` enum + Constraint::SvPrefetchOp => ConstraintIterator::Chain((0..=5).chain(8..=14)), + // Valid rotations for intrinsics operating on complex pairs: 0, 90, 180, 270 + Constraint::SvImmRotation => ConstraintIterator::StepBy((0..=270).step_by(90)), + // Valid rotations for `svcadd` and `svqcadd`: 0, 270 + Constraint::SvImmRotationAdd => ConstraintIterator::StepBy((90..=270).step_by(180)), } } } diff --git a/library/stdarch/crates/intrinsic-test/src/common/gen_c.rs b/library/stdarch/crates/intrinsic-test/src/common/gen_c.rs index a95b4c36b7bf0..bbff7a91b6c41 100644 --- a/library/stdarch/crates/intrinsic-test/src/common/gen_c.rs +++ b/library/stdarch/crates/intrinsic-test/src/common/gen_c.rs @@ -1,166 +1,53 @@ -use crate::common::intrinsic::Intrinsic; - -use super::argument::Argument; -use super::compare::INTRINSIC_DELIMITER; -use super::indentation::Indentation; -use super::intrinsic_helpers::IntrinsicTypeDefinition; - -// The number of times each intrinsic will be called. -const PASSES: u32 = 20; -const COMMON_HEADERS: [&str; 7] = [ - "iostream", - "string", - "cstring", - "iomanip", - "sstream", - "type_traits", - "cassert", -]; - -pub fn generate_c_test_loop( +use itertools::Itertools; + +use crate::common::{SupportedArchitecture, intrinsic::Intrinsic}; + +use super::intrinsic_helpers::TypeDefinition; + +/// Generates a C source file containing wrapper functions around each specialisation of each +/// intrinsic (that is, intrinsics with specific values for the the immediate arguments). Each +/// wrapper function is invoked via FFI from the Rust binary doing the testing. +/// +/// e.g. +/// ```c +/// void __crc32cd_wrapper(uint32_t* __dst, uint32_t a, uint64_t b) { +/// *__dst = __crc32cd(a, b); +/// } +/// ``` +pub fn write_wrapper_c( w: &mut impl std::io::Write, - intrinsic: &Intrinsic, - indentation: Indentation, - additional: &str, - passes: u32, + intrinsics: &[Intrinsic], ) -> std::io::Result<()> { - let body_indentation = indentation.nested(); - writeln!( + write!( w, - "{indentation}for (int i=0; i<{passes}; i++) {{\n\ - {loaded_args}\ - {body_indentation}auto __return_value = {intrinsic_call}({args});\n\ - {print_result}\n\ - {indentation}}}", - loaded_args = intrinsic.arguments.load_values_c(body_indentation), - intrinsic_call = intrinsic.name, - args = intrinsic.arguments.as_call_param_c(), - print_result = intrinsic - .results - .print_result_c(body_indentation, additional) + r#" +{notice} +#include +#include +{prelude} + +{intrinsics} +"#, + notice = A::NOTICE, + prelude = A::C_PRELUDE, + intrinsics = intrinsics.iter().format_with("", |intrinsic, fmt| { + fmt(&intrinsic + .specializations() + .format_with("\n", |imm_values, fmt| { + fmt(&format_args!( + " +void {name}_wrapper{imm_arglist}({return_ty}* __dst{arglist}) {{ + *__dst = {name}({params}); +}}", + return_ty = intrinsic.results.c_type(), + name = intrinsic.name, + imm_arglist = imm_values + .iter() + .format_with("", |i, fmt| fmt(&format_args!("_{i}"))), + arglist = intrinsic.arguments.as_non_imm_arglist_c(), + params = intrinsic.arguments.as_call_params_c(&imm_values) + )) + })) + }), ) } - -pub fn generate_c_constraint_blocks<'a, T: IntrinsicTypeDefinition + 'a>( - w: &mut impl std::io::Write, - intrinsic: &Intrinsic, - indentation: Indentation, - constraints: &mut (impl Iterator> + Clone), - name: String, -) -> std::io::Result<()> { - let Some(current) = constraints.next() else { - return generate_c_test_loop(w, intrinsic, indentation, &name, PASSES); - }; - - let body_indentation = indentation.nested(); - for i in current.constraint.iter().flat_map(|c| c.iter()) { - let ty = current.ty.c_type(); - - writeln!(w, "{indentation}{{")?; - - // TODO: Move to actually specifying the enum value - // instead of typecasting integers, for better clarity - // of generated code. - writeln!( - w, - "{body_indentation}const {ty} {} = ({ty}){i};", - current.generate_name() - )?; - - generate_c_constraint_blocks( - w, - intrinsic, - body_indentation, - &mut constraints.clone(), - format!("{name}-{i}"), - )?; - - writeln!(w, "{indentation}}}")?; - } - - Ok(()) -} - -// Compiles C test programs using specified compiler -pub fn create_c_test_function( - w: &mut impl std::io::Write, - intrinsic: &Intrinsic, -) -> std::io::Result<()> { - let indentation = Indentation::default(); - - writeln!(w, "int run_{}() {{", intrinsic.name)?; - - // Define the arrays of arguments. - let arguments = &intrinsic.arguments; - arguments.gen_arglists_c(w, indentation.nested(), PASSES)?; - - generate_c_constraint_blocks( - w, - intrinsic, - indentation.nested(), - &mut arguments.iter().rev().filter(|&i| i.has_constraint()), - Default::default(), - )?; - - writeln!(w, " return 0;")?; - writeln!(w, "}}")?; - - Ok(()) -} - -pub fn write_mod_cpp( - w: &mut impl std::io::Write, - notice: &str, - platform_headers: &[&str], - forward_declarations: &str, - intrinsics: &[Intrinsic], -) -> std::io::Result<()> { - write!(w, "{notice}")?; - - for header in COMMON_HEADERS.iter().chain(platform_headers.iter()) { - writeln!(w, "#include <{header}>")?; - } - - writeln!(w, "{}", forward_declarations)?; - - for intrinsic in intrinsics { - create_c_test_function(w, intrinsic)?; - } - - Ok(()) -} - -pub fn write_main_cpp<'a>( - w: &mut impl std::io::Write, - arch_specific_definitions: &str, - arch_specific_headers: &[&str], - intrinsics: impl Iterator + Clone, -) -> std::io::Result<()> { - for header in COMMON_HEADERS.iter().chain(arch_specific_headers.iter()) { - writeln!(w, "#include <{header}>")?; - } - - // NOTE: It's assumed that this value contains the required `ifdef`s. - writeln!(w, "{arch_specific_definitions }")?; - - for intrinsic in intrinsics.clone() { - writeln!(w, "extern int run_{intrinsic}(void);")?; - } - - writeln!(w, "int main(int argc, char **argv) {{")?; - - for intrinsic in intrinsics { - writeln!( - w, - " std::cout << \"{INTRINSIC_DELIMITER}\" << std::endl;" - )?; - writeln!(w, " std::cout << \"{intrinsic}\" << std::endl;")?; - writeln!(w, " run_{intrinsic}();\n")?; - } - - writeln!(w, " return 0;")?; - - writeln!(w, "}}")?; - - Ok(()) -} diff --git a/library/stdarch/crates/intrinsic-test/src/common/gen_rust.rs b/library/stdarch/crates/intrinsic-test/src/common/gen_rust.rs index 82b97701bb14a..44128d43b99a0 100644 --- a/library/stdarch/crates/intrinsic-test/src/common/gen_rust.rs +++ b/library/stdarch/crates/intrinsic-test/src/common/gen_rust.rs @@ -1,322 +1,340 @@ -use itertools::Itertools; use std::process::Command; -use super::compare::INTRINSIC_DELIMITER; -use super::indentation::Indentation; -use super::intrinsic_helpers::IntrinsicTypeDefinition; -use crate::common::argument::ArgumentList; -use crate::common::intrinsic::Intrinsic; +use itertools::Itertools; -// The number of times each intrinsic will be called. -pub(crate) const PASSES: u32 = 20; +use super::intrinsic_helpers::TypeDefinition; +use crate::common::cli::{CcArgStyle, ProcessedCli}; +use crate::common::intrinsic::Intrinsic; +use crate::common::intrinsic_helpers::TypeKind; +use crate::common::values::{test_values_array_name, test_values_array_static}; +use crate::common::{PASSES, PREDICATE_LOCAL, SupportedArchitecture}; + +/// Rust definitions that are included verbatim in the generated source. In particular, defines +/// a wrapper around float types that defines `NaN`s to be equal reflexively to enable +/// comparison of results that use floats types. +const COMMON_RUST_DEFINITIONS: &str = r#" +macro_rules! wrap_partialeq { + ($($wrapper:ident ($inner:ty)),*) => {$( + #[derive(Debug, Copy, Clone)] + #[repr(transparent)] + pub struct $wrapper($inner); + + impl PartialEq for $wrapper { + fn eq(&self, other: &Self) -> bool { + self.0 == other.0 || (self.0.is_nan() && other.0.is_nan()) + } + } -macro_rules! concatln { - ($($lines:expr),* $(,)?) => { - concat!($( $lines, "\n" ),*) - }; + impl Eq for $wrapper {} + )*} } -fn write_cargo_toml_header(w: &mut impl std::io::Write, name: &str) -> std::io::Result<()> { - writeln!( - w, - concatln!( - "[package]", - "name = \"{name}\"", - "version = \"{version}\"", - "authors = [{authors}]", - "license = \"{license}\"", - "edition = \"2018\"", - ), - name = name, - version = env!("CARGO_PKG_VERSION"), - authors = env!("CARGO_PKG_AUTHORS") - .split(":") - .format_with(", ", |author, fmt| fmt(&format_args!("\"{author}\""))), - license = env!("CARGO_PKG_LICENSE"), - ) +wrap_partialeq!(NanEqF16(f16), NanEqF32(f32), NanEqF64(f64)); +"#; + +/// Run rustfmt on the generated source code +pub fn run_rustfmt(source_path: &str) { + let output = Command::new("rustfmt") + .args([source_path]) + .output() + .expect("failed to run rustfmt on generated sources"); + + if !output.status.success() { + panic!( + "failed to run rustfmt on generated sources:\nstdout:{stdout}\nstderr:{stderr}", + stdout = String::from_utf8_lossy(&output.stdout), + stderr = String::from_utf8_lossy(&output.stderr) + ); + } } +/// Writes a `Cargo.toml` containing a workspace with `module_count` members to `w`. +/// +/// e.g. +/// ```toml +/// [workspace] +/// members = [ "mod_0", "mod_1" ] +/// ``` pub fn write_bin_cargo_toml( w: &mut impl std::io::Write, module_count: usize, ) -> std::io::Result<()> { - write_cargo_toml_header(w, "intrinsic-test-programs")?; - - writeln!(w, "[dependencies]")?; - writeln!(w, "core_arch = {{ path = \"../crates/core_arch\" }}")?; - - for i in 0..module_count { - writeln!(w, "mod_{i} = {{ path = \"mod_{i}/\" }}")?; - } - - Ok(()) + write!( + w, + r#" +[workspace] +members = [{members}] +"#, + members = (0..module_count).format_with(",", |i, fmt| fmt(&format_args!("\"mod_{i}\""))) + ) } +/// Writes a `Cargo.toml` for a crate with name `name` to `w` that will contain a single Rust source +/// file with a subset of the testing being generated. pub fn write_lib_cargo_toml(w: &mut impl std::io::Write, name: &str) -> std::io::Result<()> { - write_cargo_toml_header(w, name)?; - - writeln!(w, "[dependencies]")?; - writeln!(w, "core_arch = {{ path = \"../../crates/core_arch\" }}")?; - - Ok(()) -} - -pub fn write_main_rs<'a>( - w: &mut impl std::io::Write, - chunk_count: usize, - cfg: &str, - definitions: &str, - intrinsics: impl Iterator + Clone, -) -> std::io::Result<()> { - writeln!(w, "#![feature(simd_ffi)]")?; - writeln!(w, "#![feature(f16)]")?; - writeln!(w, "#![allow(unused)]")?; - - // Cargo will spam the logs if these warnings are not silenced. - writeln!(w, "#![allow(non_upper_case_globals)]")?; - writeln!(w, "#![allow(non_camel_case_types)]")?; - writeln!(w, "#![allow(non_snake_case)]")?; - - writeln!(w, "{cfg}")?; - writeln!(w, "{definitions}")?; - - for module in 0..chunk_count { - writeln!(w, "use mod_{module}::*;")?; - } - - writeln!(w, "fn main() {{")?; - - for binary in intrinsics { - writeln!(w, " println!(\"{INTRINSIC_DELIMITER}\");")?; - writeln!(w, " println!(\"{binary}\");")?; - writeln!(w, " run_{binary}();\n")?; - } - - writeln!(w, "}}")?; - - Ok(()) + write!( + w, + r#" +[package] +name = "{name}" +version = "{version}" +authors = [{authors}] +license = "{license}" +edition = "2018" + +[dependencies] +core_arch = {{ path = "../../crates/core_arch" }} + +[build-dependencies] +cc = "1" +"#, + version = env!("CARGO_PKG_VERSION"), + authors = env!("CARGO_PKG_AUTHORS") + .split(":") + .format_with(", ", |author, fmt| fmt(&format_args!("\"{author}\""))), + license = env!("CARGO_PKG_LICENSE"), + ) } -pub fn write_lib_rs( +/// Writes a Rust source file into `w` with common definitions, static arrays with test values, +/// declarations of C wrapper functions for FFI and Rust test functions. +pub fn write_lib_rs( w: &mut impl std::io::Write, - notice: &str, - cfg: &str, - definitions: &str, - intrinsics: &[Intrinsic], + i: usize, + intrinsics: &[Intrinsic], ) -> std::io::Result<()> { - write!(w, "{notice}")?; - - writeln!(w, "#![feature(simd_ffi)]")?; - writeln!(w, "#![feature(f16)]")?; - writeln!(w, "#![allow(unused)]")?; - - // Cargo will spam the logs if these warnings are not silenced. - writeln!(w, "#![allow(non_upper_case_globals)]")?; - writeln!(w, "#![allow(non_camel_case_types)]")?; - writeln!(w, "#![allow(non_snake_case)]")?; - - writeln!(w, "{cfg}")?; - - writeln!(w, "{definitions}")?; + writeln!( + w, + r#" +{notice} +#![feature(simd_ffi)] +#![feature(f16)] +#![allow(unused)] + +// Cargo will spam the logs if these warnings are not silenced. +#![allow(non_upper_case_globals)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] + +{prelude} +{COMMON_RUST_DEFINITIONS} +"#, + notice = A::NOTICE, + prelude = A::RUST_PRELUDE, + )?; let mut seen = std::collections::HashSet::new(); for intrinsic in intrinsics { for arg in &intrinsic.arguments.args { - if !arg.has_constraint() && arg.ty.is_rust_vals_array_const() { - let name = arg.rust_vals_array_name().to_string(); + // Skip arguments with constraints as these correspond to generic instantiatons, and + // predicates for scalable intrinsics as the same predicate is used for all intrinsics + // under test. + if !arg.has_constraint() && !arg.is_predicate { + let name = test_values_array_name(&arg.ty); if seen.insert(name) { - ArgumentList::gen_arg_rust(arg, w, Indentation::default(), PASSES)?; + test_values_array_static(w, &arg.ty)?; } } } } + write_bindings_rust(w, i, intrinsics)?; + for intrinsic in intrinsics { - crate::common::gen_rust::create_rust_test_module(w, intrinsic)?; + create_rust_test(w, intrinsic)?; } Ok(()) } -pub fn compile_rust_programs( - toolchain: Option<&str>, - target: &str, - profile: &str, - linker: Option<&str>, -) -> bool { - /* If there has been a linker explicitly set from the command line then - * we want to set it via setting it in the RUSTFLAGS*/ - - // This is done because `toolchain` is None when - // the --generate-only flag is passed - if toolchain.is_none() { - return true; - } - - trace!("Building cargo command"); - - let mut cargo_command = Command::new("cargo"); - cargo_command.current_dir("rust_programs"); - - // Do not use the target directory of the workspace please. - cargo_command.env("CARGO_TARGET_DIR", "target"); - - if toolchain.is_some_and(|val| !val.is_empty()) { - cargo_command.arg(toolchain.unwrap()); - } - cargo_command.args(["build", "--target", target, "--profile", profile]); - - let mut rust_flags = "-Cdebuginfo=0".to_string(); - if let Some(linker) = linker { - rust_flags.push_str(" -C linker="); - rust_flags.push_str(linker); - rust_flags.push_str(" -C link-args=-static"); - - cargo_command.env("CPPFLAGS", "-fuse-ld=lld"); - } - - cargo_command.env("RUSTFLAGS", rust_flags); - - trace!("running cargo"); - - if log::log_enabled!(log::Level::Trace) { - cargo_command.stdout(std::process::Stdio::inherit()); - cargo_command.stderr(std::process::Stdio::inherit()); - } - - let output = cargo_command.output(); - trace!("cargo is done"); - - if let Ok(output) = output { - if output.status.success() { - true - } else { - error!( - "Failed to compile code for rust intrinsics\n\nstdout:\n{}\n\nstderr:\n{}", - std::str::from_utf8(&output.stdout).unwrap_or(""), - std::str::from_utf8(&output.stderr).unwrap_or("") - ); - false - } - } else { - error!("Command failed: {output:#?}"); - false - } -} - -pub fn generate_rust_test_loop( +/// Writes the body of an intrinsic test to `w` for `intrinsic`. +/// +/// Each specialisation of the intrinsic (i.e. specific instantiations of the immediate arguments +/// of the intrinsic) is added to an array of specialisations. Each specialisation is tested +/// (first loop) `PASSES` number of times (second loop). For a given iteration of a given +/// specialisation, test values are loaded for each argument and passed to the Rust intrinsic +/// and the C wrapper function, and the results are compared. +fn generate_rust_test_loop( w: &mut impl std::io::Write, - intrinsic: &Intrinsic, - indentation: Indentation, - specializations: &[Vec], - passes: u32, + intrinsic: &Intrinsic, ) -> std::io::Result<()> { let intrinsic_name = &intrinsic.name; // Each function (and each specialization) has its own type. Erase that type with a cast. - let mut coerce = String::from("unsafe fn("); + let mut coerce = String::from("fn("); + let mut c_coerce = String::from("fn(_, "); for _ in intrinsic.arguments.iter().filter(|a| !a.has_constraint()) { coerce += "_, "; + c_coerce += "_, "; } coerce += ") -> _"; + c_coerce += ")"; - match specializations { - [] => { - writeln!(w, " let specializations = [(\"\", {intrinsic_name})];")?; - } - [const_args] if const_args.is_empty() => { - writeln!(w, " let specializations = [(\"\", {intrinsic_name})];")?; - } - _ => { - writeln!(w, " let specializations = [")?; + write!( + w, + r#" +let specializations = [{specializations}]; +for (id, rust, c) in specializations {{ + for i in 0..{PASSES} {{ + unsafe {{ + {predicate} + {loaded_args} + let __rust_return_value = rust({rust_args}); + + let mut __c_return_value = std::mem::MaybeUninit::uninit(); + c(__c_return_value.as_mut_ptr(){c_args}); + let __c_return_value = __c_return_value.assume_init(); + + {comparison} + }} + }} +}} +"#, + specializations = intrinsic + .specializations() + .format_with(",", |imm_values, fmt| { + if imm_values.is_empty() { + fmt(&format_args!( + "(\"\", {intrinsic_name}, {intrinsic_name}_wrapper)" + )) + } else { + let constraint_args = intrinsic.arguments.iter().filter(|a| a.has_constraint()); + fmt(&format_args!( + r#" + ( + "{const_args}", + {intrinsic_name}::<{const_args}> as unsafe {coerce}, + {intrinsic_name}_wrapper_{c_const_args} as unsafe extern "C" {c_coerce} + ) + "#, + const_args = imm_values + .iter() + .zip(constraint_args) + .map(|(imm_val, arg)| { + match arg.ty.kind() { + TypeKind::SvPattern | TypeKind::SvPrefetchOp => { + format!("{{ {}_from_i32({imm_val}) }}", arg.ty.kind()) + } + _ => imm_val.to_string(), + } + }) + .join(","), + c_const_args = imm_values.iter().join("_"), + )) + } + }), + loaded_args = intrinsic.arguments.load_values_rust(), + rust_args = intrinsic.arguments.as_call_param_rust(), + c_args = intrinsic.arguments.as_c_call_param_rust(), + predicate = if intrinsic.has_scalable_argument_or_result() { + format!( + "let {PREDICATE_LOCAL} = {pred};", + pred = A::predicate_function(intrinsic.results.inner_size()), + ) + } else { + "".to_string() + }, + comparison = intrinsic.results.comparison_function(), + ) +} - for specialization in specializations { - let mut specialization: Vec<_> = - specialization.iter().map(|d| d.to_string()).collect(); +/// Writes a test function for an given intrinsic to `w`, with a body generated by +/// `generate_rust_test_loop`. +fn create_rust_test( + w: &mut impl std::io::Write, + intrinsic: &Intrinsic, +) -> std::io::Result<()> { + trace!("generating `{}`", intrinsic.name); - let const_args = specialization.join(","); + write!( + w, + r#" +#[test] +fn test_{intrinsic_name}() {{ +"#, + intrinsic_name = intrinsic.name, + )?; - // The identifier is reversed. - specialization.reverse(); - let id = specialization.join("-"); + generate_rust_test_loop(w, intrinsic)?; - writeln!( - w, - " (\"-{id}\", {intrinsic_name}::<{const_args}> as {coerce})," - )?; - } + writeln!(w, "}}")?; - writeln!(w, " ];")?; - } - } + Ok(()) +} +/// Writes an `extern "C"` block with function declarations for each of the C wrapper functions into +/// `w`. +pub fn write_bindings_rust( + w: &mut impl std::io::Write, + i: usize, + intrinsics: &[Intrinsic], +) -> std::io::Result<()> { write!( w, - concatln!( - " for (id, f) in specializations {{", - " for i in 0..{passes} {{", - " unsafe {{", - "{loaded_args}", - " let __return_value = f({args});", - " println!(\"Result {{id}}-{{}}: {{:?}}\", i + 1, {return_value});", - " }}", - " }}", - " }}", - ), - loaded_args = intrinsic.arguments.load_values_rust(indentation.nest_by(4)), - args = intrinsic.arguments.as_call_param_rust(), - return_value = intrinsic.results.print_result_rust(), - passes = passes, + r#" +#[allow(improper_ctypes)] +#[link(name = "wrapper_{i}")] +unsafe extern "C" {{ + {definitions} +}} +"#, + definitions = intrinsics.iter().format_with("", |intrinsic, fmt| { + fmt(&intrinsic + .specializations() + .format_with("\n", |imm_values, fmt| { + fmt(&format_args!( + "fn {name}_wrapper{imm_arglist}(__dst: *mut {return_ty}{arglist});", + return_ty = intrinsic.results.rust_type(), + name = intrinsic.name, + imm_arglist = imm_values + .iter() + .format_with("", |i, fmt| fmt(&format_args!("_{i}"))), + arglist = intrinsic.arguments.as_non_imm_arglist_rust(), + )) + })) + }) ) } -/// Generate the specializations (unique sequences of const-generic arguments) for this intrinsic. -fn generate_rust_specializations( - constraints: &mut impl Iterator>, -) -> Vec> { - let mut specializations = vec![vec![]]; - - for constraint in constraints { - specializations = constraint - .flat_map(|right| { - specializations.iter().map(move |left| { - let mut left = left.clone(); - left.push(i32::try_from(right).unwrap()); - left - }) - }) - .collect(); - } - - specializations -} - -// Top-level function to create complete test program -pub fn create_rust_test_module( +/// Writes a `build.rs` into `w` for each test crate that compiles the corresponding C source code +/// with wrapper functions. +pub fn write_build_rs( w: &mut impl std::io::Write, - intrinsic: &Intrinsic, + i: usize, + arch_flags: &[&str], + cli_options: &ProcessedCli, ) -> std::io::Result<()> { - trace!("generating `{}`", intrinsic.name); - let indentation = Indentation::default(); - - writeln!(w, "pub fn run_{}() {{", intrinsic.name)?; + const COMMON_FLAGS: &[&str] = &["-ffp-contract=off", "-Wno-narrowing"]; + const CLANG_FLAGS: &[&str] = &["-ffp-model=strict"]; + const GCC_FLAGS: &[&str] = &[ + "-flax-vector-conversions", + "-fno-fast-math", + "-frounding-math", + "-fexcess-precision=standard", + "-ftrapping-math", + "-fsignaling-nans", + ]; - // Define the arrays of arguments. - let arguments = &intrinsic.arguments; - arguments.gen_arglists_rust(w, indentation.nested(), PASSES)?; - - // Define any const generics as `const` items, then generate the actual test loop. - let specializations = generate_rust_specializations( - &mut arguments + write!( + w, + r#" +fn main() {{ + cc::Build::new() + .file("../../c_programs/wrapper_{i}.c") + .opt_level(2) + .flags(&[{flags}]) + .compile("wrapper_{i}"); +}} +"#, + flags = COMMON_FLAGS .iter() - .filter_map(|i| i.constraint.as_ref().map(|v| v.iter())), - ); - - generate_rust_test_loop(w, intrinsic, indentation, &specializations, PASSES)?; - - writeln!(w, "}}")?; - - Ok(()) + .chain(match cli_options.cc_arg_style { + CcArgStyle::Gcc => GCC_FLAGS, + CcArgStyle::Clang => CLANG_FLAGS, + }) + .chain(arch_flags) + .format_with(",", |flag, fmt| fmt(&format_args!("\"{flag}\""))), + ) } diff --git a/library/stdarch/crates/intrinsic-test/src/common/indentation.rs b/library/stdarch/crates/intrinsic-test/src/common/indentation.rs deleted file mode 100644 index 9c2cc886e6544..0000000000000 --- a/library/stdarch/crates/intrinsic-test/src/common/indentation.rs +++ /dev/null @@ -1,26 +0,0 @@ -//! Basic code formatting tools. -//! -//! We don't need perfect formatting for the generated tests, but simple indentation can make -//! debugging a lot easier. - -#[derive(Copy, Clone, Debug, Default)] -pub struct Indentation(u32); - -impl Indentation { - pub fn nested(self) -> Self { - Self(self.0 + 1) - } - - pub fn nest_by(&self, additional_levels: u32) -> Self { - Self(self.0 + additional_levels) - } -} - -impl std::fmt::Display for Indentation { - fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { - for _ in 0..self.0 { - write!(f, " ")?; - } - Ok(()) - } -} diff --git a/library/stdarch/crates/intrinsic-test/src/common/intrinsic.rs b/library/stdarch/crates/intrinsic-test/src/common/intrinsic.rs index 81f6d6d8b5b2c..d5d903d941e4b 100644 --- a/library/stdarch/crates/intrinsic-test/src/common/intrinsic.rs +++ b/library/stdarch/crates/intrinsic-test/src/common/intrinsic.rs @@ -1,18 +1,48 @@ use super::argument::ArgumentList; -use super::intrinsic_helpers::IntrinsicTypeDefinition; +use crate::common::{SupportedArchitecture, intrinsic_helpers::SimdLen}; +use itertools::Itertools; /// An intrinsic #[derive(Debug, PartialEq, Clone)] -pub struct Intrinsic { +pub struct Intrinsic { /// The function name of this intrinsic. pub name: String, /// Any arguments for this intrinsic. - pub arguments: ArgumentList, + pub arguments: ArgumentList, /// The return type of this intrinsic. - pub results: T, + pub results: A::Type, /// Any architecture-specific tags. pub arch_tags: Vec, + + /// Specific extension that the intrinsic is from + pub extension: String, +} + +impl Intrinsic { + /// Invokes `f` for "specialisation" of the intrinsic - a specific instantiation of the + /// constant generics of the intrinsic. `f` takes a slice where the `i`th element corresponds + /// to the value of the `i`th const generic argument of the intrinsic. + /// + /// For an intrinsic with three arguments with constraints `Equal(0)`, `Range(1..2)`, + /// `Set([3, 4])` respectively, this would produce four calls to `f`: `f(0, 1, 3)`, + /// `f(0, 1, 4)`, `f(0, 2, 3)`, `f(0, 2, 4)`. + pub fn specializations(&self) -> impl Iterator> { + self.arguments + .iter() + .filter_map(|arg| arg.constraint.as_ref()) + .map(|constraint| constraint.into_iter()) + .multi_cartesian_product() + } + + /// Returns `true` if this intrinsic has any argument or result types that are scalable vectors + pub fn has_scalable_argument_or_result(&self) -> bool { + self.results.num_lanes() == SimdLen::Scalable + || self + .arguments + .iter() + .any(|a| a.ty.num_lanes() == SimdLen::Scalable) + } } diff --git a/library/stdarch/crates/intrinsic-test/src/common/intrinsic_helpers.rs b/library/stdarch/crates/intrinsic-test/src/common/intrinsic_helpers.rs index a14d7ef05f539..bc47a90d3fe16 100644 --- a/library/stdarch/crates/intrinsic-test/src/common/intrinsic_helpers.rs +++ b/library/stdarch/crates/intrinsic-test/src/common/intrinsic_helpers.rs @@ -1,14 +1,8 @@ use std::cmp; use std::fmt; -use std::ops::Deref; +use std::ops::DerefMut; use std::str::FromStr; -use itertools::Itertools as _; - -use super::cli::Language; -use super::indentation::Indentation; -use super::values::value_for_array; - #[derive(Debug, PartialEq, Copy, Clone)] pub enum Sign { Signed, @@ -17,6 +11,7 @@ pub enum Sign { #[derive(Debug, PartialEq, Copy, Clone)] pub enum TypeKind { + Bool, BFloat, Float, Int(Sign), @@ -25,6 +20,8 @@ pub enum TypeKind { Void, Mask, Vector, + SvPattern, + SvPrefetchOp, } impl FromStr for TypeKind { @@ -32,17 +29,22 @@ impl FromStr for TypeKind { fn from_str(s: &str) -> Result { match s { - "bfloat" | "BF16" => Ok(Self::BFloat), - "float" | "double" | "FP16" | "FP32" | "FP64" => Ok(Self::Float), - "int" | "long" | "short" | "SI8" | "SI16" | "SI32" | "SI64" => { + "svbool" | "bool" => Ok(Self::Bool), + "svbfloat" | "bfloat" | "BF16" => Ok(Self::BFloat), + "svfloat" | "float" | "double" | "FP16" | "FP32" | "FP64" => Ok(Self::Float), + "svint" | "int" | "long" | "short" | "SI8" | "SI16" | "SI32" | "SI64" => { Ok(Self::Int(Sign::Signed)) } "poly" => Ok(Self::Poly), "char" => Ok(Self::Char(Sign::Signed)), - "uint" | "unsigned" | "UI8" | "UI16" | "UI32" | "UI64" => Ok(Self::Int(Sign::Unsigned)), + "svuint" | "uint" | "unsigned" | "UI8" | "UI16" | "UI32" | "UI64" => { + Ok(Self::Int(Sign::Unsigned)) + } "void" => Ok(Self::Void), "MASK" => Ok(Self::Mask), "M128" | "M256" | "M512" => Ok(Self::Vector), + "svpattern" => Ok(Self::SvPattern), + "svprfop" => Ok(Self::SvPrefetchOp), _ => Err(format!("Impossible to parse argument kind {s}")), } } @@ -54,6 +56,7 @@ impl fmt::Display for TypeKind { f, "{}", match self { + Self::Bool => "bool", Self::BFloat => "bfloat", Self::Float => "float", Self::Int(Sign::Signed) => "int", @@ -64,15 +67,18 @@ impl fmt::Display for TypeKind { Self::Char(Sign::Unsigned) => "unsigned char", Self::Mask => "mask", Self::Vector => "vector", + Self::SvPattern => "svpattern", + Self::SvPrefetchOp => "svprfop", } ) } } impl TypeKind { - /// Gets the type part of a c typedef for a type that's in the form of {type}{size}_t. + /// Returns the type component of a C typedef for a type of the form of `{type}{size}_t` pub fn c_prefix(&self) -> &str { match self { + Self::Bool => "bool", Self::Float => "float", Self::Int(Sign::Signed) => "int", Self::Int(Sign::Unsigned) => "uint", @@ -84,9 +90,13 @@ impl TypeKind { } } - /// Gets the rust prefix for the type kind i.e. i, u, f. + /// Returns the Rust prefix for this type kind (i.e. `i` for `i16`, or `u` for `u16`). For type + /// kinds without any bit length at the end (e.g. `bool`), returns the whole type name. pub fn rust_prefix(&self) -> &str { match self { + Self::Bool => "bool", + Self::SvPattern => "svpattern", + Self::SvPrefetchOp => "svprfop", Self::BFloat => "bf", Self::Float => "f", Self::Int(Sign::Signed) => "i", @@ -94,42 +104,75 @@ impl TypeKind { Self::Poly => "u", Self::Char(Sign::Unsigned) => "u", Self::Char(Sign::Signed) => "i", - _ => unreachable!("Unused type kind: {self:#?}"), + Self::Mask => "u", + _ => unreachable!("type kind without Rust prefix: {self:#?}"), + } + } +} + +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SimdLen { + Scalable, + Fixed(u32), +} + +impl SimdLen { + pub fn expect_fixed(&self) -> u32 { + match self { + SimdLen::Fixed(lanes) => *lanes, + SimdLen::Scalable => panic!("`expect_fixed` with scalable length"), + } + } +} + +impl std::fmt::Display for SimdLen { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self { + Self::Scalable => unimplemented!(), + Self::Fixed(len) => ::fmt(len, f), } } } #[derive(Debug, PartialEq, Clone)] pub struct IntrinsicType { + /// Is this an immediate? pub constant: bool, - /// whether this object is a const pointer + /// Is this is a const pointer to the type? pub ptr_constant: bool, + /// Is this is a pointer to the type? pub ptr: bool, + /// Element type (e.g. `TypeKind::Int(Sign::Unsigned)` for `uint64x2_t`). pub kind: TypeKind, - /// The bit length of this type (e.g. 32 for u32). - pub bit_len: Option, - /// Length of the SIMD vector (i.e. 4 for uint32x4_t), A value of `None` - /// means this is not a simd type. A `None` can be assumed to be 1, - /// although in some places a distinction is needed between `u64` and - /// `uint64x1_t` this signals that. - pub simd_len: Option, + /// Number of bits of this type (e.g. 32 for `u32`). + pub bit_len: Option, - /// The number of rows for SIMD matrices (i.e. 2 for uint8x8x2_t). - /// A value of `None` represents a type that does not contain any - /// rows encoded in the type (e.g. uint8x8_t). - /// A value of `None` can be assumed to be 1 though. + /// Length of a SIMD vector (i.e. `Fixed(4)` for `uint32x4_t`). + /// + /// A value of `None` means this is not a SIMD type. The number of lanes of a type with + /// `simd_len=None` can be assumed to be one, though it is important to maintain a distinction + /// between `simd_len=None` and `simd_len=Some(Fixed(1))` so as to differentiate between `u64` + /// and `uint64x1_t`. A value of `Some(Scalable)` indicates that this is a scalable vector. + pub simd_len: Option, + + /// Number of rows of a SIMD matrix (i.e. 2 for `uint8x8x2_t`). + /// + /// A value of `None` means this is not a SIMD matrix (e.g. `uint8x8_t`). The number of rows of + /// a type with `vec_len=None` can be assumed to be one. pub vec_len: Option, } impl IntrinsicType { + /// Returns the element type pub fn kind(&self) -> TypeKind { self.kind } + /// Returns the number of bits of the type (with a minimum of `8`) pub fn inner_size(&self) -> u32 { if let Some(bl) = self.bit_len { cmp::max(bl, 8) @@ -138,255 +181,99 @@ impl IntrinsicType { } } - pub fn num_lanes(&self) -> u32 { - self.simd_len.unwrap_or(1) + /// Returns the number of lanes of the type + pub fn num_lanes(&self) -> SimdLen { + self.simd_len.unwrap_or(SimdLen::Fixed(1)) } + /// Returns the number of vectors of the type pub fn num_vectors(&self) -> u32 { self.vec_len.unwrap_or(1) } + /// Returns `true` if this represents a SIMD vector pub fn is_simd(&self) -> bool { self.simd_len.is_some() || self.vec_len.is_some() } + /// Returns `true` if this is a pointer pub fn is_ptr(&self) -> bool { self.ptr } +} - pub fn c_scalar_type(&self) -> String { - match self.kind() { - TypeKind::Char(_) => String::from("char"), - TypeKind::Vector => String::from("int32_t"), - _ => format!( - "{prefix}{bits}_t", - prefix = self.kind().c_prefix(), - bits = self.inner_size() - ), - } - } - - pub fn c_promotion(&self) -> &str { - match *self { - IntrinsicType { - kind, - bit_len: Some(8), - .. - } => match kind { - TypeKind::Int(Sign::Signed) => "int", - TypeKind::Int(Sign::Unsigned) => "unsigned int", - TypeKind::Poly => "uint8_t", - _ => "", - }, - IntrinsicType { - kind: TypeKind::Poly, - bit_len: Some(bit_len), - .. - } => match bit_len { - 8 => unreachable!("handled above"), - 16 => "uint16_t", - 32 => "uint32_t", - 64 => "uint64_t", - 128 => "", - _ => panic!("invalid bit_len"), - }, - IntrinsicType { - kind: TypeKind::Float, - bit_len: Some(bit_len), - .. - } => match bit_len { - 16 => "float16_t", - 32 => "float", - 64 => "double", - 128 => "", - _ => panic!("invalid bit_len"), - }, - IntrinsicType { - kind: TypeKind::Char(_), - .. - } => "char", - _ => "", - } - } - - pub fn populate_random( - &self, - indentation: Indentation, - loads: u32, - language: &Language, - ) -> String { - match self { - IntrinsicType { - bit_len: Some(bit_len @ (1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 16 | 32 | 64)), - kind: - kind @ (TypeKind::Int(_) | TypeKind::Poly | TypeKind::Char(_) | TypeKind::Mask), - simd_len, - vec_len, - .. - } => { - let (prefix, suffix) = match language { - Language::Rust => ('[', ']'), - Language::C => ('{', '}'), - }; - let body_indentation = indentation.nested(); - format!( - "{prefix}\n{body}\n{indentation}{suffix}", - body = (0..(simd_len.unwrap_or(1) * vec_len.unwrap_or(1) + loads - 1)) - .format_with(",\n", |i, fmt| { - let src = value_for_array(*bit_len, i); - assert!(src == 0 || src.ilog2() < *bit_len); - if *kind == TypeKind::Int(Sign::Signed) && (src >> (*bit_len - 1)) != 0 - { - // `src` is a two's complement representation of a negative value. - let mask = !0u64 >> (64 - *bit_len); - let ones_compl = src ^ mask; - let twos_compl = ones_compl + 1; - if (twos_compl == src) && (language == &Language::C) { - // `src` is INT*_MIN. C requires `-0x7fffffff - 1` to avoid - // undefined literal overflow behaviour. - fmt(&format_args!("{body_indentation}-{ones_compl:#x} - 1")) - } else { - fmt(&format_args!("{body_indentation}-{twos_compl:#x}")) - } - } else { - fmt(&format_args!("{body_indentation}{src:#x}")) - } - }) - ) - } - IntrinsicType { - kind: TypeKind::Float, - bit_len: Some(bit_len @ (16 | 32 | 64)), - simd_len, - vec_len, - .. - } => { - let (prefix, cast_prefix, cast_suffix, suffix) = match (language, bit_len) { - (&Language::Rust, 16) => ('[', "f16::from_bits(", ")", ']'), - (&Language::Rust, 32) => ('[', "f32::from_bits(", ")", ']'), - (&Language::Rust, 64) => ('[', "f64::from_bits(", ")", ']'), - (&Language::C, 16) => ('{', "cast(", ")", '}'), - (&Language::C, 32) => ('{', "cast(", ")", '}'), - (&Language::C, 64) => ('{', "cast(", ")", '}'), - _ => unreachable!(), - }; - format!( - "{prefix}\n{body}\n{indentation}{suffix}", - body = (0..(simd_len.unwrap_or(1) * vec_len.unwrap_or(1) + loads - 1)) - .format_with(",\n", |i, fmt| fmt(&format_args!( - "{indentation}{cast_prefix}{src:#x}{cast_suffix}", - indentation = indentation.nested(), - src = value_for_array(*bit_len, i) - ))) - ) - } - IntrinsicType { - kind: TypeKind::Vector, - bit_len: Some(128 | 256 | 512), - simd_len, - vec_len, - .. - } => { - let (prefix, suffix) = match language { - Language::Rust => ('[', ']'), - Language::C => ('{', '}'), - }; - let body_indentation = indentation.nested(); - let effective_bit_len = 32; - format!( - "{prefix}\n{body}\n{indentation}{suffix}", - body = (0..(vec_len.unwrap_or(1) * simd_len.unwrap_or(1) + loads - 1)) - .format_with(",\n", |i, fmt| { - let src = value_for_array(effective_bit_len, i); - assert!(src == 0 || src.ilog2() < effective_bit_len); - if (src >> (effective_bit_len - 1)) != 0 { - // `src` is a two's complement representation of a negative value. - let mask = !0u64 >> (64 - effective_bit_len); - let ones_compl = src ^ mask; - let twos_compl = ones_compl + 1; - if (twos_compl == src) && (language == &Language::C) { - // `src` is INT*_MIN. C requires `-0x7fffffff - 1` to avoid - // undefined literal overflow behaviour. - fmt(&format_args!("{body_indentation}-{ones_compl:#x} - 1")) - } else { - fmt(&format_args!("{body_indentation}-{twos_compl:#x}")) - } - } else { - fmt(&format_args!("{body_indentation}{src:#x}")) - } - }) - ) +pub trait TypeDefinition: Clone + DerefMut { + /// Determines the load function for this type. + fn load_function(&self) -> String; + + /// Determines the comparison function for this type. + fn comparison_function(&self) -> String { + match self.simd_len { + Some(SimdLen::Scalable) => unimplemented!("architecture-specific"), + Some(SimdLen::Fixed(_)) | None => { + default_fixed_vector_comparison(self, self.num_lanes().expect_fixed()) } - _ => unimplemented!("populate random: {self:#?}"), - } - } - - pub fn is_rust_vals_array_const(&self) -> bool { - match self { - // Floats have to be loaded at runtime for stable NaN conversion. - IntrinsicType { - kind: TypeKind::Float, - .. - } => false, - IntrinsicType { - kind: TypeKind::Int(_) | TypeKind::Poly, - .. - } => true, - _ => true, } } - pub fn as_call_param_c(&self, name: &String) -> String { - if self.ptr { - format!("&{name}") - } else { - name.clone() - } - } -} - -pub trait IntrinsicTypeDefinition: Deref { - /// Determines the load function for this type. - /// can be implemented in an `impl` block - fn get_load_function(&self, _language: Language) -> String; - - /// can be implemented in an `impl` block - fn get_lane_function(&self) -> String; - - /// Gets a string containing the typename for this type in C format. - /// can be directly defined in `impl` blocks + /// Gets a string containing the typename for this type in C. fn c_type(&self) -> String; - /// can be directly defined in `impl` blocks - fn c_single_vector_type(&self) -> String; + /// Gets a string containing the typename for this type in Rust. + fn rust_type(&self) -> String; - /// Generates a std::cout for the intrinsics results that will match the - /// rust debug output format for the return type. The generated line assumes - /// there is an int i in scope which is the current pass number. - fn print_result_c(&self, indentation: Indentation, additional: &str) -> String; - - /// Generates a std::cout for the intrinsics results that will match the - /// rust debug output format for the return type. The generated line assumes - /// there is an int i in scope which is the current pass number. - fn print_result_rust(&self) -> String { - String::from("format_args!(\"{__return_value:.150?}\")") - } - - /// To enable architecture-specific logic + /// Gets a string containing the name of the scalar type corresponding to this type if it is a + /// vector. fn rust_scalar_type(&self) -> String { - format!( - "{prefix}{bits}", - prefix = self.kind().rust_prefix(), - bits = self.inner_size() - ) + let mut ty = self.clone(); + ty.simd_len = None; + ty.vec_len = None; + ty.rust_type() } - fn generate_final_type_cast(&self) -> String { - let type_data = self.c_promotion(); - if type_data.len() > 2 { - format!("({type_data})") - } else { - String::new() - } + /// Gets a string containing the name of the scalar type corresponding to this type that should + /// be used as the element type for the test value array. + fn rust_scalar_type_for_test_value_array(&self) -> String { + self.rust_scalar_type() } } + +/// Returns the default comparison between results of an intrinsic - casting the vectors to arrays +/// and using `assert_eq` - using `NanEqF*` where required for floats. +pub(crate) fn default_fixed_vector_comparison( + ty: &Ty, + num_lanes: u32, +) -> String { + let (cast_prefix, cast_suffix) = if ty.is_simd() { + ( + format!( + "std::mem::transmute::<_, [{}; {}]>(", + ty.rust_scalar_type().replace("f", "NanEqF"), + num_lanes * ty.num_vectors() + ), + ")", + ) + } else if ty.kind == TypeKind::Float { + ( + match ty.inner_size() { + 16 => format!("NanEqF16("), + 32 => format!("NanEqF32("), + 64 => format!("NanEqF64("), + _ => unimplemented!(), + }, + ")", + ) + } else { + ("".to_string(), "") + }; + + format!( + r#" +assert_eq!( + {cast_prefix}__rust_return_value{cast_suffix}, + {cast_prefix}__c_return_value{cast_suffix}, + "{{id}}" +); +"#, + ) +} diff --git a/library/stdarch/crates/intrinsic-test/src/common/mod.rs b/library/stdarch/crates/intrinsic-test/src/common/mod.rs index a1062b3a87dbc..46b6bc4102bed 100644 --- a/library/stdarch/crates/intrinsic-test/src/common/mod.rs +++ b/library/stdarch/crates/intrinsic-test/src/common/mod.rs @@ -1,172 +1,94 @@ -use std::fs::File; +use std::{fs::File, io}; use rayon::prelude::*; use cli::ProcessedCli; use crate::common::{ - compile_c::CppCompilation, - gen_c::{write_main_cpp, write_mod_cpp}, + argument::Argument, + gen_c::write_wrapper_c, gen_rust::{ - compile_rust_programs, write_bin_cargo_toml, write_lib_cargo_toml, write_lib_rs, - write_main_rs, + run_rustfmt, write_bin_cargo_toml, write_build_rs, write_lib_cargo_toml, write_lib_rs, }, intrinsic::Intrinsic, - intrinsic_helpers::IntrinsicTypeDefinition, + intrinsic_helpers::TypeDefinition, + values::test_values_array_name, }; pub mod argument; pub mod cli; -pub mod compare; -pub mod compile_c; pub mod constraint; -pub mod gen_c; -pub mod gen_rust; -pub mod indentation; pub mod intrinsic; pub mod intrinsic_helpers; pub mod values; +mod gen_c; +mod gen_rust; + +/// Many scalable intrinsics take a predicate argument and for the purposes of intrinsic testing, +/// a predicate that enables all lanes is used for all of these intrinsic calls (i.e. loading inputs, +/// result comparison, and the intrinsic under test). This constant defines the name of the local +/// variable that contains that predicate. +pub const PREDICATE_LOCAL: &'static str = "__pred"; + +// The number of times each intrinsic will be called - influences the generation of the +// test arrays to minimise repeated testing of the same test values. +pub(crate) const PASSES: u32 = 20; + /// Architectures must support this trait /// to be successfully tested. -pub trait SupportedArchitectureTest { - type IntrinsicImpl: IntrinsicTypeDefinition + Sync; +pub trait SupportedArchitecture: Sized { + type Type: TypeDefinition + std::fmt::Debug + PartialEq + Sync; - fn cli_options(&self) -> &ProcessedCli; - fn intrinsics(&self) -> &[Intrinsic]; + fn intrinsics(&self) -> &[Intrinsic]; - fn create(cli_options: ProcessedCli) -> Self; + fn create(cli_options: &ProcessedCli) -> Self; const NOTICE: &str; - const PLATFORM_C_HEADERS: &[&str]; - const PLATFORM_C_DEFINITIONS: &str; - const PLATFORM_C_FORWARD_DECLARATIONS: &str; - - const PLATFORM_RUST_CFGS: &str; - const PLATFORM_RUST_DEFINITIONS: &str; - - fn cpp_compilation(&self) -> Option; + const C_PRELUDE: &str; + const RUST_PRELUDE: &str; - fn build_c_file(&self) -> bool { - let (chunk_size, chunk_count) = manual_chunk(self.intrinsics().len(), 400); + fn c_compiler_flags(&self, cli_options: &ProcessedCli) -> Vec<&str>; - let cpp_compiler_wrapped = self.cpp_compilation(); + fn generate_c_file(&self) { + let (max_chunk_size, _chunk_count) = manual_chunk(self.intrinsics().len()); std::fs::create_dir_all("c_programs").unwrap(); self.intrinsics() - .par_chunks(chunk_size) + .par_chunks(max_chunk_size) .enumerate() .map(|(i, chunk)| { - let c_filename = format!("c_programs/mod_{i}.cpp"); + let c_filename = format!("c_programs/wrapper_{i}.c"); let mut file = File::create(&c_filename).unwrap(); - let mod_file_write_result = write_mod_cpp( - &mut file, - Self::NOTICE, - Self::PLATFORM_C_HEADERS, - Self::PLATFORM_C_FORWARD_DECLARATIONS, - chunk, - ); - - if let Err(error) = mod_file_write_result { - return Err(format!("Error writing to mod_{i}.cpp: {error:?}")); - } - - // compile this cpp file into a .o file. - // - // This is done because `cpp_compiler_wrapped` is None when - // the --generate-only flag is passed - trace!("compiling mod_{i}.cpp"); - if let Some(cpp_compiler) = cpp_compiler_wrapped.as_ref() { - let compile_output = cpp_compiler - .compile_object_file(&format!("mod_{i}.cpp"), &format!("mod_{i}.o")) - .map_err(|e| format!("Error compiling mod_{i}.cpp: {e:?}"))?; - - assert!( - compile_output.status.success(), - "{}", - String::from_utf8_lossy(&compile_output.stderr) - ); - - trace!("finished compiling mod_{i}.cpp"); - } - Ok(()) + write_wrapper_c(&mut file, chunk) }) - .collect::>() + .collect::>() .unwrap(); - - let mut file = File::create("c_programs/main.cpp").unwrap(); - write_main_cpp( - &mut file, - Self::PLATFORM_C_DEFINITIONS, - Self::PLATFORM_C_HEADERS, - self.intrinsics().iter().map(|i| i.name.as_str()), - ) - .unwrap(); - - // This is done because `cpp_compiler_wrapped` is None when - // the --generate-only flag is passed - if let Some(cpp_compiler) = cpp_compiler_wrapped.as_ref() { - // compile this cpp file into a .o file - trace!("compiling main.cpp"); - let output = cpp_compiler - .compile_object_file("main.cpp", "intrinsic-test-programs.o") - .unwrap(); - assert!(output.status.success(), "{output:?}"); - - let object_files = (0..chunk_count) - .map(|i| format!("mod_{i}.o")) - .chain(["intrinsic-test-programs.o".to_owned()]); - - let output = cpp_compiler - .link_executable(object_files, "intrinsic-test-programs") - .unwrap(); - assert!(output.status.success(), "{output:?}"); - } - - true } - fn build_rust_file(&self) -> bool { - std::fs::create_dir_all("rust_programs/src").unwrap(); + fn generate_rust_file(&self, cli_options: &ProcessedCli) { + let arch_flags = self.c_compiler_flags(cli_options); - let (chunk_size, chunk_count) = manual_chunk(self.intrinsics().len(), 400); + std::fs::create_dir_all("rust_programs").unwrap(); + + let (max_chunk_size, chunk_count) = manual_chunk(self.intrinsics().len()); let mut cargo = File::create("rust_programs/Cargo.toml").unwrap(); write_bin_cargo_toml(&mut cargo, chunk_count).unwrap(); - let mut main_rs = File::create("rust_programs/src/main.rs").unwrap(); - write_main_rs( - &mut main_rs, - chunk_count, - Self::PLATFORM_RUST_CFGS, - "", - self.intrinsics().iter().map(|i| i.name.as_str()), - ) - .unwrap(); - - let target = &self.cli_options().target; - let profile = &self.cli_options().profile; - let toolchain = self.cli_options().toolchain.as_deref(); - let linker = self.cli_options().linker.as_deref(); - self.intrinsics() - .par_chunks(chunk_size) + .chunks(max_chunk_size) .enumerate() .map(|(i, chunk)| { std::fs::create_dir_all(format!("rust_programs/mod_{i}/src"))?; let rust_filename = format!("rust_programs/mod_{i}/src/lib.rs"); trace!("generating `{rust_filename}`"); - let mut file = File::create(rust_filename)?; + let mut file = File::create(&rust_filename)?; - write_lib_rs( - &mut file, - Self::NOTICE, - Self::PLATFORM_RUST_CFGS, - Self::PLATFORM_RUST_DEFINITIONS, - chunk, - )?; + write_lib_rs(&mut file, i, chunk)?; + run_rustfmt(&rust_filename); let toml_filename = format!("rust_programs/mod_{i}/Cargo.toml"); trace!("generating `{toml_filename}`"); @@ -174,41 +96,36 @@ pub trait SupportedArchitectureTest { write_lib_cargo_toml(&mut file, &format!("mod_{i}"))?; + let build_rs_filename = format!("rust_programs/mod_{i}/build.rs"); + trace!("generating `{build_rs_filename}`"); + let mut file = File::create(&build_rs_filename).unwrap(); + + write_build_rs(&mut file, i, &arch_flags, &cli_options).unwrap(); + run_rustfmt(&build_rs_filename); + Ok(()) }) .collect::>() .unwrap(); - - compile_rust_programs(toolchain, target, profile, linker) } - fn compare_outputs(&self) -> bool { - if self.cli_options().toolchain.is_some() { - let intrinsics_name_list = self - .intrinsics() - .iter() - .map(|i| i.name.clone()) - .collect::>(); - - compare::compare_outputs( - &intrinsics_name_list, - &self.cli_options().runner, - &self.cli_options().target, - &self.cli_options().profile, - ) - } else { - true - } + /// Return a call to a intrinsic to generate a predicate, if reqd. + fn predicate_function(_: u32) -> String; + + /// Return a call loading `arg`. Can assume that `arg.is_simd()` holds. + fn load_call(arg: &Argument, idx: usize) -> String { + format!( + "let {name} = {load}({vals_name}.as_ptr().add((i+{idx}) % {PASSES}) as _);\n", + name = arg.generate_name(), + vals_name = test_values_array_name(&arg.ty), + load = arg.ty.load_function(), + ) } } -// pub fn chunk_info(intrinsic_count: usize) -> (usize, usize) { -// let available_parallelism = std::thread::available_parallelism().unwrap().get(); -// let chunk_size = intrinsic_count.div_ceil(Ord::min(available_parallelism, intrinsic_count)); - -// (chunk_size, intrinsic_count.div_ceil(chunk_size)) -// } - -pub fn manual_chunk(intrinsic_count: usize, chunk_size: usize) -> (usize, usize) { - (chunk_size, intrinsic_count.div_ceil(chunk_size)) +pub fn manual_chunk(intrinsic_count: usize) -> (usize, usize) { + let ncores = std::thread::available_parallelism().unwrap().into(); + let max_intrinsics_per_chunk = intrinsic_count.div_ceil(ncores); + let number_of_chunks = intrinsic_count.div_ceil(max_intrinsics_per_chunk); + (max_intrinsics_per_chunk, number_of_chunks) } diff --git a/library/stdarch/crates/intrinsic-test/src/common/values.rs b/library/stdarch/crates/intrinsic-test/src/common/values.rs index 6c94ef2c22e1d..d1f333fd19363 100644 --- a/library/stdarch/crates/intrinsic-test/src/common/values.rs +++ b/library/stdarch/crates/intrinsic-test/src/common/values.rs @@ -1,145 +1,361 @@ -/// Get a single value for an argument values array in a determistic way. -/// * `bits`: The number of bits for the type, only 8, 16, 32, 64 are valid values -/// * `index`: The position in the array we are generating for -pub fn value_for_array(bits: u32, index: u32) -> u64 { +use itertools::Itertools as _; + +use crate::common::{ + PASSES, + intrinsic_helpers::{IntrinsicType, Sign, SimdLen, TypeDefinition, TypeKind}, +}; + +/// Maximum size of a SVE vector +pub const MAX_SVE_BITS: u32 = 2048; + +/// Writes a string defining a static variable with test values used for all intrinsics with +/// arguments of type `ty` to `w`. +/// +/// e.g. +/// ```rust,ignore +/// static U8_20: [u8; 20] = [ +/// 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0xf0, +/// 0x80, 0x3b, 0xff, +/// ]; +/// ``` +pub fn test_values_array_static( + w: &mut impl std::io::Write, + ty: &T, +) -> std::io::Result<()> { + writeln!( + w, + "static {name}: [{ty}; {load_size}] = {values};", + name = test_values_array_name(ty), + ty = ty.rust_scalar_type_for_test_value_array(), + load_size = test_values_array_length(&ty), + values = test_values_array(&ty) + ) +} + +/// Returns a string with the name of the static variable containing test values for intrinsic +/// arguments of this type. +pub fn test_values_array_name(ty: &T) -> String { + format!( + "{ty}_{load_size}", + ty = ty.rust_scalar_type().to_uppercase(), + load_size = test_values_array_length(&ty), + ) +} + +/// Returns the elements used in the test value arrays in `gen_arg_rust`. Uses the +/// `test_values_array_length` fn to determine the number of values that +/// `test_values_array_static` expects and `ArgumentList::load_values_rust` needs. +/// +/// Each value in the array starts as a bit pattern from `bit_pattern_for_test_values_array` +/// which is then printed as a hex value in the generated code (and if identified as a negative +/// value, with the appropriate minus and corrected hex pattern). Calls to `fN::from_bits` are +/// generated for floats. +/// +/// An exception to the above is when `ty` is a boolean, where this function returns +/// `[true, false]` - as there are only ever two values for a boolean. This only works because the +/// generated accesses to the test value array is always modulo the length of the test value array. +pub fn test_values_array(ty: &IntrinsicType) -> String { + let (bit_len, kind) = match ty { + IntrinsicType { + kind: TypeKind::Bool, + .. + } => (1, TypeKind::Bool), + IntrinsicType { + kind: TypeKind::Float, + bit_len: Some(bit_len), + .. + } => (*bit_len, TypeKind::Float), + IntrinsicType { + kind: TypeKind::Vector, + .. + } => (32, TypeKind::Vector), + IntrinsicType { + kind, + bit_len: Some(bit_len), + .. + } => (*bit_len, *kind), + _ => unimplemented!(), + }; + + format!( + "[{}]", + (0..test_values_array_length(ty)).format_with(",", |i, fmt| { + let src = bit_pattern_for_test_values_array(bit_len, i); + assert!(src == 0 || src.ilog2() < bit_len); + match kind { + TypeKind::Bool if ty.num_lanes() != SimdLen::Scalable => { + fmt(&format_args!("{}", if src == 1 { true } else { false })) + } + TypeKind::Float => fmt(&format_args!("f{bit_len}::from_bits({src:#x})")), + TypeKind::Vector | TypeKind::Int(Sign::Signed) if (src >> (bit_len - 1)) != 0 => { + // `src` is a two's complement representation of a negative value. + let mask = !0u64 >> (64 - bit_len); + let ones_compl = src ^ mask; + let twos_compl = ones_compl + 1; + fmt(&format_args!("-{twos_compl:#x}")) + } + _ => fmt(&format_args!("{src:#x}")), + } + }) + ) +} + +/// Returns the number of values that need to be in an array of test values such that there can be +/// `num_loads` distinct windows for a given vector of type `ty`. +/// +/// For example, vectors of type `uint32x2x2_t` load four values (`2 x 2`) and so to support +/// `num_loads=10` distinct windows, the total length of the array of test values must be +/// `(2 x 2) + 10 - 1`: +/// +/// ```text +/// [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xA, 0xB, 0xC, 0xD] +/// ^^^^^^^^^^^^^^^^^^ first window +/// ^^^^^^^^^^^^^^^^^^ second window +/// 10th window ^^^^^^^^^^^^^^^^^^ +/// ``` +/// +/// For scalable vectors (only SVE is currently supported), assume that the length of the vector is +/// the maximum supported by the architecture. +pub fn test_values_array_length(ty: &IntrinsicType) -> u32 { + let IntrinsicType { + simd_len, vec_len, .. + } = ty; + + let simd_len = simd_len.map_or(1, |v| { + if let SimdLen::Fixed(n) = v { + n + } else { + MAX_SVE_BITS / ty.inner_size() + } + }); + let vec_len = vec_len.unwrap_or(1); + + (simd_len * vec_len) + PASSES - 1 +} + +/// Returns a bit pattern for a value being output into a array of test values. Bit patterns come +/// from one of many constant arrays of test values. The specific constant array used depends on +/// the number of bits - `bits` - of the type having test values generated for it. This function +/// is called repeatedly with incrementing values of `index` to produce an entire array of test +/// values. +/// +/// Each constant array of bit patterns should ideally be at least the length of the largest array +/// of test values that will be requested (e.g. 51 for a `poly8x8x4` when `PASSES=20`: +/// `(8 * 4) + 20 - 1`), otherwise values will be repeated. +pub fn bit_pattern_for_test_values_array(bits: u32, index: u32) -> u64 { let index = index as usize; match bits { - 1 => VALUES_8[index % 2].into(), - 2 => VALUES_8[index % 4].into(), - 3 => VALUES_8[index % 8].into(), - 4 => VALUES_8[index % 16].into(), - 5 => VALUES_5[index % VALUES_5.len()].into(), - 6 => VALUES_6[index % VALUES_6.len()].into(), - 7 => VALUES_7[index % VALUES_7.len()].into(), - 8 => VALUES_8[index % VALUES_8.len()].into(), - 16 => VALUES_16[index % VALUES_16.len()].into(), - 32 => VALUES_32[index % VALUES_32.len()].into(), - 64 => VALUES_64[index % VALUES_64.len()], - _ => unimplemented!("value_for_array(bits: {bits}, ..)"), + 1 => BIT_PATTERNS_1[index % BIT_PATTERNS_1.len()].into(), + bits @ (2 | 3 | 4 | 5 | 6 | 7 | 8) => BIT_PATTERNS_8[index % (1 << bits)].into(), + 16 => BIT_PATTERNS_16[index % BIT_PATTERNS_16.len()].into(), + 32 => BIT_PATTERNS_32[index % BIT_PATTERNS_32.len()].into(), + 64 => BIT_PATTERNS_64[index % BIT_PATTERNS_64.len()], + _ => unimplemented!("bit_pattern_for_test_values_array(bits: {bits}, ..)"), } } -pub const VALUES_5: &[u8] = &[ - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x019, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, - 0x1f, -]; +// Contains every possible 1-bit value in order +pub const BIT_PATTERNS_1: &[u8] = &[0x0, 0x1]; -pub const VALUES_6: &[u8] = &[ - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x039, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, - 0x3f, +// Contains every possible 8-bit value in order +pub const BIT_PATTERNS_8: &[u8] = &[ + 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x10, 0x11, + 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, + 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, + 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, 0x40, 0x41, + 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x50, 0x51, + 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x60, 0x61, + 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, + 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, 0x80, 0x81, + 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, 0x90, 0x91, + 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, + 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, 0xb0, 0xb1, + 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, 0xc0, 0xc1, + 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 0xd0, 0xd1, + 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, 0xe0, 0xe1, + 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, 0xf0, 0xf1, + 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, ]; -pub const VALUES_7: &[u8] = &[ - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x079, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, - 0x7f, -]; +#[rustfmt::skip] +pub const BIT_PATTERNS_16: &[u16] = &[ + // Simple values: + // 0.0 + 0x0000, + // The smallest normal value + 0x0400, + // The value just below 0.5 + 0x37ff, + // 0.5 + 0x3800, + // The value just above 0.5 + 0x3801, + // The value just below 1.0 + 0x3bff, + // 1.0 + 0x3c00, + // The value just above 1.0 + 0x3c01, + // 1.5 + 0x3e00, + // 10 + 0x4900, + // The largest finite value + 0x7bff, + // Infinity. + 0x7c00, -pub const VALUES_8: &[u8] = &[ - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0xf0, 0x80, 0x3b, 0xff, -]; + // NaNs: + // Quiet NaNs + 0x7f23, + 0x7e00, + // Signalling NaNs + 0x7d23, + 0x7c01, -pub const VALUES_16: &[u16] = &[ - 0x0000, // 0.0 - 0x0400, // The smallest normal value. - 0x37ff, // The value just below 0.5. - 0x3800, // 0.5 - 0x3801, // The value just above 0.5. - 0x3bff, // The value just below 1.0. - 0x3c00, // 1.0 - 0x3c01, // The value just above 1.0. - 0x3e00, // 1.5 - 0x4900, // 10 - 0x7bff, // The largest finite value. - 0x7c00, // Infinity. - // NaNs. - // - Quiet NaNs - 0x7f23, 0x7e00, // - Signalling NaNs - 0x7d23, 0x7c01, // Subnormals. - // - A recognisable bit pattern. - 0x0012, // - The largest subnormal value. - 0x03ff, // - The smallest subnormal value. - 0x0001, // The same values again, but negated. + // Subnormals: + // A recognisable bit pattern + 0x0012, + // The largest subnormal value + 0x03ff, + // The smallest subnormal value + 0x0001, + + // Other values: + // Above values, negated 0x8000, 0x8400, 0xb7ff, 0xb800, 0xb801, 0xbbff, 0xbc00, 0xbc01, 0xbe00, 0xc900, 0xfbff, 0xfc00, 0xff23, 0xfe00, 0xfd23, 0xfc01, 0x8012, 0x83ff, 0x8001, + // Random values + 0xfc00, 0xc000, 0x5140, 0x5800, 0x63d2, 0x5630, 0x3560, 0x9191, 0x4178, 0x6212, 0x67d0, 0x3312, + 0x4cef, 0x4973, 0x3ecc, 0x5166, 0x4d80, 0x6248, 0x46fd, 0x39c4, 0x39c5, 0x4866, 0x6050, 0x498e, + 0x4a0f, + // Previous values in a different order + 0x3555, 0xfc00, 0xc000, 0x9191, 0x5140, 0x5800, 0x8001, 0x83ff, 0x63d2, 0x5630, 0x3560, 0x4178, + 0x7d23, 0x7c01, 0x0012, 0xb800, 0x03ff, 0x0001, 0x7e00, 0x7f23, 0x8000, 0x8400, 0xb7ff, 0xb801, + 0x3312, 0x4cef, 0x4973, 0x39c4, 0x3ecc, 0x5166, 0x67d0, 0x6212, 0x4d80, 0x6248, 0x46fd, 0x39c5, + 0xbc01, 0xbe00, 0xc900, 0xfc01, 0xfbff, 0xfc00, 0xbc00, 0xbbff, 0xff23, 0xfe00, 0xfd23, 0x8012, + 0x37ff, 0x3800, 0x3801, 0x7bff, 0x3bff, 0x3c00, 0x0400, 0x0000, 0x3c01, 0x3e00, 0x4900, 0x7c00, + 0x498e, 0x4a0f, 0x6050, 0x4866, + + // Specific values: + // As close to 1/3 as possible. + 0x3555, ]; -pub const VALUES_32: &[u32] = &[ - // Simple values. - 0x00000000, // 0.0 - 0x00800000, // The smallest normal value. - 0x3effffff, // The value just below 0.5. - 0x3f000000, // 0.5 - 0x3f000001, // The value just above 0.5. - 0x3f7fffff, // The value just below 1.0. - 0x3f800000, // 1.0 - 0x3f800001, // The value just above 1.0. - 0x3fc00000, // 1.5 - 0x41200000, // 10 - 0x7f8fffff, // The largest finite value. - 0x7f800000, // Infinity. - // NaNs. - // - Quiet NaNs - 0x7fd23456, 0x7fc00000, // - Signalling NaNs - 0x7f923456, 0x7f800001, // Subnormals. - // - A recognisable bit pattern. - 0x00123456, // - The largest subnormal value. - 0x007fffff, // - The smallest subnormal value. - 0x00000001, // The same values again, but negated. +#[rustfmt::skip] +pub const BIT_PATTERNS_32: &[u32] = &[ + // Simple values: + // 0.0 + 0x00000000, + // The smallest normal value + 0x00800000, + // The value just below 0.5 + 0x3effffff, + // 0.5 + 0x3f000000, + // The value just above 0.5 + 0x3f000001, + // The value just below 1.0 + 0x3f7fffff, + // 1.0 + 0x3f800000, + // The value just above 1.0 + 0x3f800001, + // 1.5 + 0x3fc00000, + // 10 + 0x41200000, + // The largest finite value + 0x7f8fffff, + // Infinity + 0x7f800000, + + // NaNs: + // Quiet NaNs + 0x7fd23456, + 0x7fc00000, + // Signalling NaNs + 0x7f923456, + 0x7f800001, + + // Subnormals: + // A recognisable bit pattern + 0x00123456, + // The largest subnormal value + 0x007fffff, + // The smallest subnormal value + 0x00000001, + + // Other values: + // Above values, negated 0x80000000, 0x80800000, 0xbeffffff, 0xbf000000, 0xbf000001, 0xbf7fffff, 0xbf800000, 0xbf800001, 0xbfc00000, 0xc1200000, 0xff8fffff, 0xff800000, 0xffd23456, 0xffc00000, 0xff923456, 0xff800001, - 0x80123456, 0x807fffff, 0x80000001, + 0x80123456, 0x807fffff, 0x80000001, 0x80123456, 0x807fffff, 0x80000001, + // Random values + 0x4205cccd, 0x4229178D, 0x42C6A0C5, 0x3B3302F7, 0x3F9DF45E, 0x41DAA3D7, 0x47C3501D, 0xC3889333, + 0xC2C675C3, 0xC69C449A, 0xC341FD71, 0xC502DFD7, 0xBBB43958, 0x3EE24DD3, 0x42B1C28F, 0x42F06666, + 0x45D379C3, 0x44637148, 0x3CBBECAB, 0x4113EDFA, 0x444B22F2, 0x1FD93A96, 0x9921055F, 0xFF626925, + + // Specific values: + // Approximately Pi + 0x40490fdb, + // Approximately 1/3 + 0x3eaaaaab, ]; -pub const VALUES_64: &[u64] = &[ - // Simple values. - 0x0000000000000000, // 0.0 - 0x0010000000000000, // The smallest normal value. - 0x3fdfffffffffffff, // The value just below 0.5. - 0x3fe0000000000000, // 0.5 - 0x3fe0000000000001, // The value just above 0.5. - 0x3fefffffffffffff, // The value just below 1.0. - 0x3ff0000000000000, // 1.0 - 0x3ff0000000000001, // The value just above 1.0. - 0x3ff8000000000000, // 1.5 - 0x4024000000000000, // 10 - 0x7fefffffffffffff, // The largest finite value. - 0x7ff0000000000000, // Infinity. - // NaNs. - // - Quiet NaNs - 0x7ff923456789abcd, - 0x7ff8000000000000, - // - Signalling NaNs - 0x7ff123456789abcd, +#[rustfmt::skip] +pub const BIT_PATTERNS_64: &[u64] = &[ + // Simple values: + // 0.0 + 0x0000000000000000, + // The smallest normal value + 0x0010000000000000, + // The value just below 0.5 + 0x3fdfffffffffffff, + // 0.5 + 0x3fe0000000000000, + // The value just above 0.5 + 0x3fe0000000000001, + // The value just below 1.0 + 0x3fefffffffffffff, + // 1.0 + 0x3ff0000000000000, + // The value just above 1.0 + 0x3ff0000000000001, + // 1.5 + 0x3ff8000000000000, + // 10 + 0x4024000000000000, + // The largest finite value + 0x7fefffffffffffff, + // Infinity 0x7ff0000000000000, - // Subnormals. - // - A recognisable bit pattern. + + // NaNs: + // Quiet NaNs + 0x7ff923456789abcd, 0x7ff8000000000000, + // Signalling NaNs + 0x7ff123456789abcd, 0x7ff0000000000000, + + // Subnormals: + // A recognisable bit pattern 0x000123456789abcd, - // - The largest subnormal value. + // The largest subnormal value 0x000fffffffffffff, - // - The smallest subnormal value. + // The smallest subnormal value 0x0000000000000001, - // The same values again, but negated. - 0x8000000000000000, - 0x8010000000000000, - 0xbfdfffffffffffff, - 0xbfe0000000000000, - 0xbfe0000000000001, - 0xbfefffffffffffff, - 0xbff0000000000000, - 0xbff0000000000001, - 0xbff8000000000000, - 0xc024000000000000, - 0xffefffffffffffff, - 0xfff0000000000000, - 0xfff923456789abcd, - 0xfff8000000000000, - 0xfff123456789abcd, - 0xfff0000000000000, - 0x800123456789abcd, - 0x800fffffffffffff, - 0x8000000000000001, + + // Other values: + // Above values, negated + 0x8000000000000000, 0x8010000000000000, 0xbfdfffffffffffff, 0xbfe0000000000000, + 0xbfe0000000000001, 0xbfefffffffffffff, 0xbff0000000000000, 0xbff0000000000001, + 0xbff8000000000000, 0xc024000000000000, 0xffefffffffffffff, 0xfff0000000000000, + 0xfff923456789abcd, 0xfff8000000000000, 0xfff123456789abcd, 0xfff0000000000000, + 0x800123456789abcd, 0x800fffffffffffff, 0x8000000000000001, + + // Specific values: + // Pi + 0x400921FB54442D18, + // Approximately 1/3 + 0x3fd5555555555555, ]; diff --git a/library/stdarch/crates/intrinsic-test/src/main.rs b/library/stdarch/crates/intrinsic-test/src/main.rs index e5c846877ce6d..e25eb48a456d1 100644 --- a/library/stdarch/crates/intrinsic-test/src/main.rs +++ b/library/stdarch/crates/intrinsic-test/src/main.rs @@ -5,37 +5,31 @@ mod arm; mod common; mod x86; -use arm::ArmArchitectureTest; -use common::SupportedArchitectureTest; +use arm::Arm; +use common::SupportedArchitecture; use common::cli::{Cli, ProcessedCli}; -use x86::X86ArchitectureTest; +use x86::X86; fn main() { pretty_env_logger::init(); let args: Cli = clap::Parser::parse(); let processed_cli_options = ProcessedCli::new(args); - match processed_cli_options.target.as_str() { - "aarch64-unknown-linux-gnu" - | "armv7-unknown-linux-gnueabihf" - | "aarch64_be-unknown-linux-gnu" => run(ArmArchitectureTest::create(processed_cli_options)), - - "x86_64-unknown-linux-gnu" => run(X86ArchitectureTest::create(processed_cli_options)), - _ => std::process::exit(0), + if processed_cli_options.target.starts_with("arm") + | processed_cli_options.target.starts_with("aarch64") + { + run(Arm::create(&processed_cli_options), processed_cli_options) + } else if processed_cli_options.target.starts_with("x86") { + run(X86::create(&processed_cli_options), processed_cli_options) + } else { + unimplemented!("Unsupported target {}", processed_cli_options.target) } } -fn run(test_environment: impl SupportedArchitectureTest) { +fn run(test_environment: impl SupportedArchitecture, processed_cli_options: ProcessedCli) { info!("building C binaries"); - if !test_environment.build_c_file() { - std::process::exit(2); - } + test_environment.generate_c_file(); + info!("building Rust binaries"); - if !test_environment.build_rust_file() { - std::process::exit(3); - } - info!("Running binaries"); - if !test_environment.compare_outputs() { - std::process::exit(1); - } + test_environment.generate_rust_file(&processed_cli_options); } diff --git a/library/stdarch/crates/intrinsic-test/src/x86/compile.rs b/library/stdarch/crates/intrinsic-test/src/x86/compile.rs deleted file mode 100644 index 65cd291b1b377..0000000000000 --- a/library/stdarch/crates/intrinsic-test/src/x86/compile.rs +++ /dev/null @@ -1,59 +0,0 @@ -use crate::common::cli::ProcessedCli; -use crate::common::compile_c::{CompilationCommandBuilder, CppCompilation}; - -pub fn build_cpp_compilation(config: &ProcessedCli) -> Option { - let cpp_compiler = config.cpp_compiler.as_ref()?; - - // -ffp-contract=off emulates Rust's approach of not fusing separate mul-add operations - let mut command = CompilationCommandBuilder::new() - .add_arch_flags(["icelake-client"]) - .set_compiler(cpp_compiler) - .set_target(&config.target) - .set_opt_level("2") - .set_cxx_toolchain_dir(config.cxx_toolchain_dir.as_deref()) - .set_project_root("c_programs") - .add_extra_flags(vec![ - "-ffp-contract=off", - "-Wno-narrowing", - "-mavx", - "-mavx2", - "-mavx512f", - "-msse2", - "-mavx512vl", - "-mavx512bw", - "-mavx512dq", - "-mavx512cd", - "-mavx512fp16", - "-msha512", - "-msm3", - "-msm4", - "-mavxvnni", - "-mavxvnniint8", - "-mavxneconvert", - "-mavxifma", - "-mavxvnniint16", - "-mavx512bf16", - "-mavx512bitalg", - "-mavx512ifma", - "-mavx512vbmi", - "-mavx512vbmi2", - "-mavx512vnni", - "-mavx512vpopcntdq", - "-mavx512vp2intersect", - "-mbmi", - "-mbmi2", - "-mgfni", - "-mvaes", - "-mvpclmulqdq", - "-ferror-limit=1000", - "-std=c++23", - ]); - - if !cpp_compiler.contains("clang") { - command = command.add_extra_flag("-flax-vector-conversions"); - } - - let cpp_compiler = command.into_cpp_compilation(); - - Some(cpp_compiler) -} diff --git a/library/stdarch/crates/intrinsic-test/src/x86/config.rs b/library/stdarch/crates/intrinsic-test/src/x86/config.rs deleted file mode 100644 index 491dbb5147bbc..0000000000000 --- a/library/stdarch/crates/intrinsic-test/src/x86/config.rs +++ /dev/null @@ -1,334 +0,0 @@ -pub const NOTICE: &str = "\ -// This is a transient test file, not intended for distribution. Some aspects of the -// test are derived from an XML specification, published under the same license as the -// `intrinsic-test` crate.\n"; - -// Format f16 values (and vectors containing them) in a way that is consistent with C. -pub const PLATFORM_RUST_DEFINITIONS: &str = r#" -use core_arch::arch::x86_64::*; - -#[inline] -unsafe fn _mm_loadu_ph_to___m128i(mem_addr: *const f16) -> __m128i { - _mm_castph_si128(_mm_loadu_ph(mem_addr)) -} - -#[inline] -unsafe fn _mm256_loadu_ph_to___m256i(mem_addr: *const f16) -> __m256i { - _mm256_castph_si256(_mm256_loadu_ph(mem_addr)) -} - -#[inline] -unsafe fn _mm512_loadu_ph_to___mm512i(mem_addr: *const f16) -> __m512i { - _mm512_castph_si512(_mm512_loadu_ph(mem_addr)) -} - - -#[inline] -unsafe fn _mm_loadu_ps_to___m128h(mem_addr: *const f32) -> __m128h { - _mm_castps_ph(_mm_loadu_ps(mem_addr)) -} - -#[inline] -unsafe fn _mm256_loadu_ps_to___m256h(mem_addr: *const f32) -> __m256h { - _mm256_castps_ph(_mm256_loadu_ps(mem_addr)) -} - -#[inline] -unsafe fn _mm512_loadu_ps_to___m512h(mem_addr: *const f32) -> __m512h { - _mm512_castps_ph(_mm512_loadu_ps(mem_addr)) -} - -#[inline] -unsafe fn _mm_loadu_epi16_to___m128d(mem_addr: *const i16) -> __m128d { - _mm_castsi128_pd(_mm_loadu_epi16(mem_addr)) -} - -#[inline] -unsafe fn _mm256_loadu_epi16_to___m256d(mem_addr: *const i16) -> __m256d { - _mm256_castsi256_pd(_mm256_loadu_epi16(mem_addr)) -} - -#[inline] -unsafe fn _mm512_loadu_epi16_to___m512d(mem_addr: *const i16) -> __m512d { - _mm512_castsi512_pd(_mm512_loadu_epi16(mem_addr)) -} - -#[inline] -unsafe fn _mm_loadu_epi32_to___m128d(mem_addr: *const i32) -> __m128d { - _mm_castsi128_pd(_mm_loadu_epi32(mem_addr)) -} - -#[inline] -unsafe fn _mm256_loadu_epi32_to___m256d(mem_addr: *const i32) -> __m256d { - _mm256_castsi256_pd(_mm256_loadu_epi32(mem_addr)) -} - -#[inline] -unsafe fn _mm512_loadu_epi32_to___m512d(mem_addr: *const i32) -> __m512d { - _mm512_castsi512_pd(_mm512_loadu_epi32(mem_addr)) -} - -#[inline] -unsafe fn _mm_loadu_epi64_to___m128d(mem_addr: *const i64) -> __m128d { - _mm_castsi128_pd(_mm_loadu_epi64(mem_addr)) -} - -#[inline] -unsafe fn _mm256_loadu_epi64_to___m256d(mem_addr: *const i64) -> __m256d { - _mm256_castsi256_pd(_mm256_loadu_epi64(mem_addr)) -} - -#[inline] -unsafe fn _mm512_loadu_epi64_to___m512d(mem_addr: *const i64) -> __m512d { - _mm512_castsi512_pd(_mm512_loadu_epi64(mem_addr)) -} - -// === -#[inline] -unsafe fn _mm_loadu_epi16_to___m128(mem_addr: *const i16) -> __m128 { - _mm_castsi128_ps(_mm_loadu_epi16(mem_addr)) -} - -#[inline] -unsafe fn _mm256_loadu_epi16_to___m256(mem_addr: *const i16) -> __m256 { - _mm256_castsi256_ps(_mm256_loadu_epi16(mem_addr)) -} - -#[inline] -unsafe fn _mm512_loadu_epi16_to___m512(mem_addr: *const i16) -> __m512 { - _mm512_castsi512_ps(_mm512_loadu_epi16(mem_addr)) -} - -#[inline] -unsafe fn _mm_loadu_epi32_to___m128(mem_addr: *const i32) -> __m128 { - _mm_castsi128_ps(_mm_loadu_epi32(mem_addr)) -} - -#[inline] -unsafe fn _mm256_loadu_epi32_to___m256(mem_addr: *const i32) -> __m256 { - _mm256_castsi256_ps(_mm256_loadu_epi32(mem_addr)) -} - -#[inline] -unsafe fn _mm512_loadu_epi32_to___m512(mem_addr: *const i32) -> __m512 { - _mm512_castsi512_ps(_mm512_loadu_epi32(mem_addr)) -} - -#[inline] -unsafe fn _mm_loadu_epi64_to___m128(mem_addr: *const i64) -> __m128 { - _mm_castsi128_ps(_mm_loadu_epi64(mem_addr)) -} - -#[inline] -unsafe fn _mm256_loadu_epi64_to___m256(mem_addr: *const i64) -> __m256 { - _mm256_castsi256_ps(_mm256_loadu_epi64(mem_addr)) -} - -#[inline] -unsafe fn _mm512_loadu_epi64_to___m512(mem_addr: *const i64) -> __m512 { - _mm512_castsi512_ps(_mm512_loadu_epi64(mem_addr)) -} - -#[inline] -fn debug_simd_finish( - formatter: &mut core::fmt::Formatter<'_>, - type_name: &str, - array: &[T; N], -) -> core::fmt::Result { - core::fmt::Formatter::debug_tuple_fields_finish( - formatter, - type_name, - &core::array::from_fn::<&dyn core::fmt::Debug, N, _>(|i| &array[i]), - ) -} - -trait DebugAs { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result; -} - -impl DebugAs for T { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - write!(f, "{self}") - } -} - -macro_rules! impl_debug_as { - ($simd:ty, $name:expr, $bits:expr, [$($type:ty),+]) => { - $( - impl DebugAs<$type> for $simd { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - const ELEMENT_BITS: usize = core::mem::size_of::<$type>() * 8; - const NUM_ELEMENTS: usize = $bits / ELEMENT_BITS; - let array = unsafe { core::mem::transmute::<_, [$type; NUM_ELEMENTS]>(*self) }; - debug_simd_finish(f, $name, &array) - } - } - )+ - }; -} - -impl_debug_as!(__m128i, "__m128i", 128, [u8, i8, u16, i16, u32, i32, u64, i64, f16]); -impl_debug_as!(__m256i, "__m256i", 256, [u8, i8, u16, i16, u32, i32, u64, i64]); -impl_debug_as!(__m512i, "__m512i", 512, [u8, i8, u16, i16, u32, i32, u64, i64]); -impl_debug_as!(__m128h, "__m128h", 128, [f32]); -impl_debug_as!(__m256h, "__m256h", 256, [f32]); -impl_debug_as!(__m512h, "__m512h", 512, [f32]); - -fn debug_as(x: V) -> impl core::fmt::Debug -where V: DebugAs -{ - struct DebugWrapper(V, core::marker::PhantomData); - impl, T> core::fmt::Debug for DebugWrapper { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.0.fmt(f) - } - } - DebugWrapper(x, core::marker::PhantomData) -} - -"#; - -pub const PLATFORM_C_FORWARD_DECLARATIONS: &str = r#" -#ifndef X86_DECLARATIONS -#define X86_DECLARATIONS - typedef _Float16 float16_t; - typedef float float32_t; - typedef double float64_t; - - #define __int64 long long - #define __int32 int - - std::ostream& operator<<(std::ostream& os, _Float16 value); - std::ostream& operator<<(std::ostream& os, __m128i value); - std::ostream& operator<<(std::ostream& os, __m256i value); - std::ostream& operator<<(std::ostream& os, __m512i value); - std::ostream& operator<<(std::ostream& os, __mmask8 value); - - #define _mm512_extract_intrinsic_test_epi8(m, lane) \ - _mm_extract_epi8(_mm512_extracti64x2_epi64((m), (lane) / 16), (lane) % 16) - - #define _mm512_extract_intrinsic_test_epi16(m, lane) \ - _mm_extract_epi16(_mm512_extracti64x2_epi64((m), (lane) / 8), (lane) % 8) - - #define _mm512_extract_intrinsic_test_epi32(m, lane) \ - _mm_extract_epi32(_mm512_extracti64x2_epi64((m), (lane) / 4), (lane) % 4) - - #define _mm512_extract_intrinsic_test_epi64(m, lane) \ - _mm_extract_epi64(_mm512_extracti64x2_epi64((m), (lane) / 2), (lane) % 2) - - // Load f16 (__m128h) and cast to integer (__m128i) - #define _mm_loadu_ph_to___m128i(mem_addr) _mm_castph_si128(_mm_loadu_ph(mem_addr)) - #define _mm256_loadu_ph_to___m256i(mem_addr) _mm256_castph_si256(_mm256_loadu_ph(mem_addr)) - #define _mm512_loadu_ph_to___m512i(mem_addr) _mm512_castph_si512(_mm512_loadu_ph(mem_addr)) - - // Load f32 (__m128) and cast to f16 (__m128h) - #define _mm_loadu_ps_to___m128h(mem_addr) _mm_castps_ph(_mm_loadu_ps(mem_addr)) - #define _mm256_loadu_ps_to___m256h(mem_addr) _mm256_castps_ph(_mm256_loadu_ps(mem_addr)) - #define _mm512_loadu_ps_to___m512h(mem_addr) _mm512_castps_ph(_mm512_loadu_ps(mem_addr)) - - // Load integer types and cast to double (__m128d, __m256d, __m512d) - #define _mm_loadu_epi16_to___m128d(mem_addr) _mm_castsi128_pd(_mm_loadu_si128((__m128i const*)(mem_addr))) - #define _mm256_loadu_epi16_to___m256d(mem_addr) _mm256_castsi256_pd(_mm256_loadu_si256((__m256i const*)(mem_addr))) - #define _mm512_loadu_epi16_to___m512d(mem_addr) _mm512_castsi512_pd(_mm512_loadu_si512((__m512i const*)(mem_addr))) - - #define _mm_loadu_epi32_to___m128d(mem_addr) _mm_castsi128_pd(_mm_loadu_si128((__m128i const*)(mem_addr))) - #define _mm256_loadu_epi32_to___m256d(mem_addr) _mm256_castsi256_pd(_mm256_loadu_si256((__m256i const*)(mem_addr))) - #define _mm512_loadu_epi32_to___m512d(mem_addr) _mm512_castsi512_pd(_mm512_loadu_si512((__m512i const*)(mem_addr))) - - #define _mm_loadu_epi64_to___m128d(mem_addr) _mm_castsi128_pd(_mm_loadu_si128((__m128i const*)(mem_addr))) - #define _mm256_loadu_epi64_to___m256d(mem_addr) _mm256_castsi256_pd(_mm256_loadu_si256((__m256i const*)(mem_addr))) - #define _mm512_loadu_epi64_to___m512d(mem_addr) _mm512_castsi512_pd(_mm512_loadu_si512((__m512i const*)(mem_addr))) - - // Load integer types and cast to float (__m128, __m256, __m512) - #define _mm_loadu_epi16_to___m128(mem_addr) _mm_castsi128_ps(_mm_loadu_si128((__m128i const*)(mem_addr))) - #define _mm256_loadu_epi16_to___m256(mem_addr) _mm256_castsi256_ps(_mm256_loadu_si256((__m256i const*)(mem_addr))) - #define _mm512_loadu_epi16_to___m512(mem_addr) _mm512_castsi512_ps(_mm512_loadu_si512((__m512i const*)(mem_addr))) - - #define _mm_loadu_epi32_to___m128(mem_addr) _mm_castsi128_ps(_mm_loadu_si128((__m128i const*)(mem_addr))) - #define _mm256_loadu_epi32_to___m256(mem_addr) _mm256_castsi256_ps(_mm256_loadu_si256((__m256i const*)(mem_addr))) - #define _mm512_loadu_epi32_to___m512(mem_addr) _mm512_castsi512_ps(_mm512_loadu_si512((__m512i const*)(mem_addr))) - - #define _mm_loadu_epi64_to___m128(mem_addr) _mm_castsi128_ps(_mm_loadu_si128((__m128i const*)(mem_addr))) - #define _mm256_loadu_epi64_to___m256(mem_addr) _mm256_castsi256_ps(_mm256_loadu_si256((__m256i const*)(mem_addr))) - #define _mm512_loadu_epi64_to___m512(mem_addr) _mm512_castsi512_ps(_mm512_loadu_si512((__m512i const*)(mem_addr))) - - // T1 is the `To` type, T2 is the `From` type - template T1 cast(T2 x) { - if constexpr ((std::is_integral_v && std::is_integral_v) || (std::is_floating_point_v && std::is_floating_point_v)) { - return x; - } else if constexpr (sizeof(T1) <= sizeof(T2)) { - T1 ret{}; - std::memcpy(&ret, &x, sizeof(T1)); - return ret; - } else { - static_assert(sizeof(T1) == sizeof(T2) || std::is_convertible_v, - "T2 must either be convertible to T1, or have the same size as T1!"); - return T1{}; - } - } -#endif -"#; -pub const PLATFORM_C_DEFINITIONS: &str = r#" - -std::ostream& operator<<(std::ostream& os, _Float16 value) { - os << static_cast(value); - return os; -} - -std::ostream& operator<<(std::ostream& os, __m128i value) { - void* temp = malloc(sizeof(__m128i)); - _mm_storeu_si128((__m128i*)temp, value); - std::stringstream ss; - - ss << "0x"; - for(int i = 0; i < 16; i++) { - ss << std::setfill('0') << std::setw(2) << std::hex << ((char*)temp)[i]; - } - os << ss.str(); - return os; -} - -std::ostream& operator<<(std::ostream& os, __m256i value) { - void* temp = malloc(sizeof(__m256i)); - _mm256_storeu_si256((__m256i*)temp, value); - std::stringstream ss; - - ss << "0x"; - for(int i = 0; i < 32; i++) { - ss << std::setfill('0') << std::setw(2) << std::hex << ((char*)temp)[i]; - } - os << ss.str(); - return os; -} - -std::ostream& operator<<(std::ostream& os, __m512i value) { - void* temp = malloc(sizeof(__m512i)); - _mm512_storeu_si512((__m512i*)temp, value); - std::stringstream ss; - - ss << "0x"; - for(int i = 0; i < 64; i++) { - ss << std::setfill('0') << std::setw(2) << std::hex << ((char*)temp)[i]; - } - os << ss.str(); - return os; -} - -std::ostream& operator<<(std::ostream& os, __mmask8 value) { - os << static_cast(value); - return os; -} -"#; - -pub const PLATFORM_RUST_CFGS: &str = r#" -#![cfg_attr(target_arch = "x86", feature(avx))] -#![cfg_attr(target_arch = "x86", feature(sse))] -#![cfg_attr(target_arch = "x86", feature(sse2))] -#![cfg_attr(target_arch = "x86", feature(stdarch_x86_avx512_bf16))] -#![cfg_attr(target_arch = "x86", feature(stdarch_x86_avx512_f16))] -#![cfg_attr(target_arch = "x86", feature(stdarch_x86_rtm))] -#![cfg_attr(target_arch = "x86", feature(stdarch_x86_rtm))] -#![cfg_attr(target_arch = "x86_64", feature(x86_amx_intrinsics))] -#![cfg_attr(target_arch = "x86_64", feature(stdarch_x86_avx512_f16))] -#![feature(fmt_helpers_for_derive)] -"#; diff --git a/library/stdarch/crates/intrinsic-test/src/x86/constraint.rs b/library/stdarch/crates/intrinsic-test/src/x86/constraint.rs index 72f5da3b3faf3..cda9a7e7bf51d 100644 --- a/library/stdarch/crates/intrinsic-test/src/x86/constraint.rs +++ b/library/stdarch/crates/intrinsic-test/src/x86/constraint.rs @@ -1,29 +1,30 @@ use crate::common::constraint::Constraint; -pub fn map_constraints(imm_type: &String, imm_width: u32) -> Option { +pub fn map_constraints(fn_name: &str, imm_type: &String, imm_width: u32) -> Option { if imm_width > 0 { + if fn_name == "_mm_sm3rnds2_epi32" { + return Some(Constraint::Set((0..64).step_by(2).collect())); + } let max: i64 = 2i64.pow(imm_width); return Some(Constraint::Range(0..max)); } match imm_type.as_str() { - // Legal values for variables of `_MM_FROUND` type are: - // 8 => (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions - // 9 => (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions - // 10 => (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions - // 11 => (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions - // 4 => _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE + // _mm512_cvt{_round}ps_ph functions can accept a larger set of values for _MM_FROUND + "_MM_FROUND" + if fn_name.starts_with("_mm512") + && (fn_name.ends_with("cvtps_ph") || fn_name.ends_with("cvt_roundps_ph")) => + { + Some(Constraint::Set(vec![0, 1, 2, 3, 4, 8, 9, 10, 11, 12])) + } "_MM_FROUND" => Some(Constraint::Set(vec![4, 8, 9, 10, 11])), "_MM_INDEX_SCALE" => Some(Constraint::Set(vec![1, 2, 4, 8])), "_MM_CMPINT" => Some(Constraint::Range(0..8)), - "_MM_REDUCE" => Some(Constraint::Range(0..8)), - "_MM_FROUND_SAE" => Some(Constraint::Equal(8)), + "_MM_REDUCE" => Some(Constraint::Range(0..256)), + "_MM_FROUND_SAE" => Some(Constraint::Set(vec![4, 8])), "_MM_MANTISSA_NORM" => Some(Constraint::Range(0..4)), - "_MM_MANTISSA_NORM_ENUM" => Some(Constraint::Range(0..4)), "_MM_MANTISSA_SIGN" => Some(Constraint::Range(0..3)), "_MM_PERM" => Some(Constraint::Range(0..256)), - "_MM_PERM_ENUM" => Some(Constraint::Range(0..256)), - "_MM_CMPINT_ENUM" => Some(Constraint::Range(0..8)), - "_MM_ROUND_MODE" => Some(Constraint::Set(vec![0, 0x2, 0x4, 0x6])), + "_MM_ROUND_MODE" => Some(Constraint::Range(0..5)), "_CMP_" => Some(Constraint::Range(0..32)), _ => None, } diff --git a/library/stdarch/crates/intrinsic-test/src/x86/mod.rs b/library/stdarch/crates/intrinsic-test/src/x86/mod.rs index f2baf070714c1..36f4fee43741b 100644 --- a/library/stdarch/crates/intrinsic-test/src/x86/mod.rs +++ b/library/stdarch/crates/intrinsic-test/src/x86/mod.rs @@ -1,48 +1,78 @@ -mod compile; -mod config; mod constraint; mod intrinsic; mod types; mod xml_parser; -use crate::common::SupportedArchitectureTest; +use crate::common::SupportedArchitecture; use crate::common::cli::ProcessedCli; -use crate::common::compile_c::CppCompilation; use crate::common::intrinsic::Intrinsic; use crate::common::intrinsic_helpers::TypeKind; use intrinsic::X86IntrinsicType; use xml_parser::get_xml_intrinsics; -pub struct X86ArchitectureTest { - intrinsics: Vec>, - cli_options: ProcessedCli, +pub struct X86 { + intrinsics: Vec>, } -impl SupportedArchitectureTest for X86ArchitectureTest { - type IntrinsicImpl = X86IntrinsicType; +impl SupportedArchitecture for X86 { + type Type = X86IntrinsicType; - fn cli_options(&self) -> &ProcessedCli { - &self.cli_options - } - - fn intrinsics(&self) -> &[Intrinsic] { + fn intrinsics(&self) -> &[Intrinsic] { &self.intrinsics } - fn cpp_compilation(&self) -> Option { - compile::build_cpp_compilation(&self.cli_options) - } - - const NOTICE: &str = config::NOTICE; + const NOTICE: &str = r#" +// This is a transient test file, not intended for distribution. Some aspects of the +// test are derived from an XML specification, published under the same license as the +// `intrinsic-test` crate. +"#; - const PLATFORM_C_HEADERS: &[&str] = &["immintrin.h", "cstddef", "cstdint"]; - const PLATFORM_C_DEFINITIONS: &str = config::PLATFORM_C_DEFINITIONS; - const PLATFORM_C_FORWARD_DECLARATIONS: &str = config::PLATFORM_C_FORWARD_DECLARATIONS; + const C_PRELUDE: &str = r#" +#include +"#; + const RUST_PRELUDE: &str = RUST_PRELUDE; - const PLATFORM_RUST_DEFINITIONS: &str = config::PLATFORM_RUST_DEFINITIONS; - const PLATFORM_RUST_CFGS: &str = config::PLATFORM_RUST_CFGS; + fn c_compiler_flags(&self, _cli_options: &ProcessedCli) -> Vec<&str> { + vec![ + "-maes", + "-mf16c", + "-mfma", + "-mavx", + "-mavx2", + "-mavx512f", + "-msse2", + "-mavx512vl", + "-mavx512bw", + "-mavx512dq", + "-mavx512cd", + "-mavx512fp16", + "-msha", + "-msha512", + "-msm3", + "-msm4", + "-mavxvnni", + "-mavxvnniint8", + "-mavxneconvert", + "-mavxifma", + "-mavxvnniint16", + "-mavx512bf16", + "-mavx512bitalg", + "-mavx512ifma", + "-mavx512vbmi", + "-mavx512vbmi2", + "-mavx512vnni", + "-mavx512vpopcntdq", + "-mavx512vp2intersect", + "-mbmi", + "-mbmi2", + "-mgfni", + "-mvaes", + "-mvpclmulqdq", + "-mlzcnt", + ] + } - fn create(cli_options: ProcessedCli) -> Self { + fn create(cli_options: &ProcessedCli) -> Self { let mut intrinsics = get_xml_intrinsics(&cli_options.filename).expect("Error parsing input file"); @@ -67,9 +97,141 @@ impl SupportedArchitectureTest for X86ArchitectureTest { .take(sample_size) .collect::>(); - Self { - intrinsics: intrinsics, - cli_options: cli_options, - } + Self { intrinsics } + } + + fn predicate_function(_: u32) -> String { + unimplemented!("no scalable vectors on x86") } } + +const RUST_PRELUDE: &str = r#" +#![feature(stdarch_x86_avx512_bf16)] +#![feature(stdarch_x86_avx512_f16)] +#![feature(stdarch_x86_rtm)] +#![feature(x86_amx_intrinsics)] + +use core_arch::arch::x86_64::*; + +#[inline] +unsafe fn _mm_loadu_ph_to___m128i(mem_addr: *const f16) -> __m128i { + _mm_castph_si128(_mm_loadu_ph(mem_addr)) +} + +#[inline] +unsafe fn _mm256_loadu_ph_to___m256i(mem_addr: *const f16) -> __m256i { + _mm256_castph_si256(_mm256_loadu_ph(mem_addr)) +} + +#[inline] +unsafe fn _mm512_loadu_ph_to___mm512i(mem_addr: *const f16) -> __m512i { + _mm512_castph_si512(_mm512_loadu_ph(mem_addr)) +} + + +#[inline] +unsafe fn _mm_loadu_ps_to___m128h(mem_addr: *const f32) -> __m128h { + _mm_castps_ph(_mm_loadu_ps(mem_addr)) +} + +#[inline] +unsafe fn _mm256_loadu_ps_to___m256h(mem_addr: *const f32) -> __m256h { + _mm256_castps_ph(_mm256_loadu_ps(mem_addr)) +} + +#[inline] +unsafe fn _mm512_loadu_ps_to___m512h(mem_addr: *const f32) -> __m512h { + _mm512_castps_ph(_mm512_loadu_ps(mem_addr)) +} + +#[inline] +unsafe fn _mm_loadu_epi16_to___m128d(mem_addr: *const i16) -> __m128d { + _mm_castsi128_pd(_mm_loadu_epi16(mem_addr)) +} + +#[inline] +unsafe fn _mm256_loadu_epi16_to___m256d(mem_addr: *const i16) -> __m256d { + _mm256_castsi256_pd(_mm256_loadu_epi16(mem_addr)) +} + +#[inline] +unsafe fn _mm512_loadu_epi16_to___m512d(mem_addr: *const i16) -> __m512d { + _mm512_castsi512_pd(_mm512_loadu_epi16(mem_addr)) +} + +#[inline] +unsafe fn _mm_loadu_epi32_to___m128d(mem_addr: *const i32) -> __m128d { + _mm_castsi128_pd(_mm_loadu_epi32(mem_addr)) +} + +#[inline] +unsafe fn _mm256_loadu_epi32_to___m256d(mem_addr: *const i32) -> __m256d { + _mm256_castsi256_pd(_mm256_loadu_epi32(mem_addr)) +} + +#[inline] +unsafe fn _mm512_loadu_epi32_to___m512d(mem_addr: *const i32) -> __m512d { + _mm512_castsi512_pd(_mm512_loadu_epi32(mem_addr)) +} + +#[inline] +unsafe fn _mm_loadu_epi64_to___m128d(mem_addr: *const i64) -> __m128d { + _mm_castsi128_pd(_mm_loadu_epi64(mem_addr)) +} + +#[inline] +unsafe fn _mm256_loadu_epi64_to___m256d(mem_addr: *const i64) -> __m256d { + _mm256_castsi256_pd(_mm256_loadu_epi64(mem_addr)) +} + +#[inline] +unsafe fn _mm512_loadu_epi64_to___m512d(mem_addr: *const i64) -> __m512d { + _mm512_castsi512_pd(_mm512_loadu_epi64(mem_addr)) +} + +// === +#[inline] +unsafe fn _mm_loadu_epi16_to___m128(mem_addr: *const i16) -> __m128 { + _mm_castsi128_ps(_mm_loadu_epi16(mem_addr)) +} + +#[inline] +unsafe fn _mm256_loadu_epi16_to___m256(mem_addr: *const i16) -> __m256 { + _mm256_castsi256_ps(_mm256_loadu_epi16(mem_addr)) +} + +#[inline] +unsafe fn _mm512_loadu_epi16_to___m512(mem_addr: *const i16) -> __m512 { + _mm512_castsi512_ps(_mm512_loadu_epi16(mem_addr)) +} + +#[inline] +unsafe fn _mm_loadu_epi32_to___m128(mem_addr: *const i32) -> __m128 { + _mm_castsi128_ps(_mm_loadu_epi32(mem_addr)) +} + +#[inline] +unsafe fn _mm256_loadu_epi32_to___m256(mem_addr: *const i32) -> __m256 { + _mm256_castsi256_ps(_mm256_loadu_epi32(mem_addr)) +} + +#[inline] +unsafe fn _mm512_loadu_epi32_to___m512(mem_addr: *const i32) -> __m512 { + _mm512_castsi512_ps(_mm512_loadu_epi32(mem_addr)) +} + +#[inline] +unsafe fn _mm_loadu_epi64_to___m128(mem_addr: *const i64) -> __m128 { + _mm_castsi128_ps(_mm_loadu_epi64(mem_addr)) +} + +#[inline] +unsafe fn _mm256_loadu_epi64_to___m256(mem_addr: *const i64) -> __m256 { + _mm256_castsi256_ps(_mm256_loadu_epi64(mem_addr)) +} + +#[inline] +unsafe fn _mm512_loadu_epi64_to___m512(mem_addr: *const i64) -> __m512 { + _mm512_castsi512_ps(_mm512_loadu_epi64(mem_addr)) +} +"#; diff --git a/library/stdarch/crates/intrinsic-test/src/x86/types.rs b/library/stdarch/crates/intrinsic-test/src/x86/types.rs index 2391ee9c2df49..2cba54a73f767 100644 --- a/library/stdarch/crates/intrinsic-test/src/x86/types.rs +++ b/library/stdarch/crates/intrinsic-test/src/x86/types.rs @@ -1,15 +1,12 @@ use std::str::FromStr; use itertools::Itertools; -use regex::Regex; use super::intrinsic::X86IntrinsicType; -use crate::common::cli::Language; -use crate::common::indentation::Indentation; -use crate::common::intrinsic_helpers::{IntrinsicType, IntrinsicTypeDefinition, Sign, TypeKind}; +use crate::common::intrinsic_helpers::{IntrinsicType, Sign, SimdLen, TypeDefinition, TypeKind}; use crate::x86::xml_parser::Parameter; -impl IntrinsicTypeDefinition for X86IntrinsicType { +impl TypeDefinition for X86IntrinsicType { /// Gets a string containing the type in C format. /// This function assumes that this value is present in the metadata hashmap. fn c_type(&self) -> String { @@ -26,82 +23,32 @@ impl IntrinsicTypeDefinition for X86IntrinsicType { .replace("const ", "") } - fn c_single_vector_type(&self) -> String { - // matches __m128, __m256 and similar types - let re = Regex::new(r"__m\d+").unwrap(); - if re.is_match(self.param.type_data.as_str()) { - self.param.type_data.clone() - } else { - unreachable!("Shouldn't be called on this type") + fn rust_type(&self) -> String { + let type_data = &*self.param.type_data; + if type_data.starts_with("__m") { + return type_data.to_owned(); + } + match &*type_data.replace("const ", "") { + "_Float16" => "f16", + "__bfloat16" => "bf16", + "float" => "f32", + "double" => "f64", + "__int8" | "char" => "i8", + "unsigned char" => "u8", + "__int16" | "short" => "i16", + "unsigned short" => "u16", + "__int32" | "int" => "i32", + "unsigned __int32" | "unsigned int" | "unsigned long" => "u32", + "__int64" | "long long" => "i64", + "unsigned __int64" => "u64", + "size_t" => "usize", + _ => todo!("unknown type {type_data}"), } + .to_string() } - // fn rust_type(&self) -> String { - // // handling edge cases first - // // the general handling is implemented below - // if let Some(val) = self.metadata.get("type") { - // match val.as_str() { - // "__m128 const *" => { - // return "&__m128".to_string(); - // } - // "__m128d const *" => { - // return "&__m128d".to_string(); - // } - // "const void*" => { - // return "&__m128d".to_string(); - // } - // _ => {} - // } - // } - - // if self.kind() == TypeKind::Void && self.ptr { - // // this has been handled by default settings in - // // the from_param function of X86IntrinsicType - // unreachable!() - // } - - // // general handling cases - // let core_part = if self.kind() == TypeKind::Mask { - // // all types of __mmask are handled here - // format!("__mask{}", self.bit_len.unwrap()) - // } else if self.simd_len.is_some() { - // // all types of __m vector types are handled here - // let re = Regex::new(r"\__m\d+[a-z]*").unwrap(); - // let rust_type = self - // .metadata - // .get("type") - // .map(|val| re.find(val).unwrap().as_str()); - // rust_type.unwrap().to_string() - // } else { - // format!( - // "{}{}", - // self.kind.rust_prefix().to_string(), - // self.bit_len.unwrap() - // ) - // }; - - // // extracting "memsize" so that even vector types can be involved - // let memwidth = self - // .metadata - // .get("memwidth") - // .map(|n| str::parse::(n).unwrap()); - // let prefix_part = if self.ptr && self.constant && self.bit_len.eq(&memwidth) { - // "&" - // } else if self.ptr && self.bit_len.eq(&memwidth) { - // "&mut " - // } else if self.ptr && self.constant { - // "*const " - // } else if self.ptr { - // "*mut " - // } else { - // "" - // }; - - // return prefix_part.to_string() + core_part.as_str(); - // } - /// Determines the load function for this type. - fn get_load_function(&self, _language: Language) -> String { + fn load_function(&self) -> String { let type_value = self.param.type_data.clone(); if type_value.len() == 0 { unimplemented!("the value for key 'type' is not present!"); @@ -168,112 +115,16 @@ impl IntrinsicTypeDefinition for X86IntrinsicType { } } - /// Generates a std::cout for the intrinsics results that will match the - /// rust debug output format for the return type. The generated line assumes - /// there is an int i in scope which is the current pass number. - fn print_result_c(&self, indentation: Indentation, additional: &str) -> String { - let lanes = if self.num_lanes() > 1 { - (0..self.num_lanes()) - .map(|idx| -> std::string::String { - let cast_type = self.c_promotion(); - let lane_fn = self.get_lane_function(); - if cast_type.len() > 2 { - format!("cast<{cast_type}>({lane_fn}(__return_value, {idx}))") - } else { - format!("{lane_fn}(__return_value, {idx})") - } - }) - .collect::>() - .join(r#" << ", " << "#) - } else { + fn rust_scalar_type(&self) -> String { + if self.is_simd() { format!( - "{promote}cast<{cast}>(__return_value)", - cast = match self.kind() { - TypeKind::Void => "void".to_string(), - TypeKind::Float if self.inner_size() == 64 => "double".to_string(), - TypeKind::Float if self.inner_size() == 32 => "float".to_string(), - TypeKind::Mask => format!( - "__mmask{}", - self.bit_len.expect(format!("self: {self:#?}").as_str()) - ), - TypeKind::Vector => format!( - "__m{}i", - self.bit_len.expect(format!("self: {self:#?}").as_str()) - ), - _ => self.c_scalar_type(), - }, - promote = self.generate_final_type_cast(), + "{prefix}{bits}", + prefix = self.kind().rust_prefix(), + bits = self.inner_size() ) - }; - - format!( - r#"{indentation}std::cout << "Result {additional}-" << i+1 << ": {ty}" << std::fixed << std::setprecision(150) << {lanes} << "{close}" << std::endl;"#, - ty = if self.is_simd() { - format!("{}(", self.c_type()) - } else { - String::from("") - }, - close = if self.is_simd() { ")" } else { "" }, - ) - } - - /// Determines the get lane function for this type. - fn get_lane_function(&self) -> String { - let total_vector_bits: Option = self - .simd_len - .zip(self.bit_len) - .and_then(|(simd_len, bit_len)| Some(simd_len * bit_len)); - - match (self.bit_len, total_vector_bits) { - (Some(8), Some(128)) => String::from("(uint8_t)_mm_extract_epi8"), - (Some(16), Some(128)) => String::from("(uint16_t)_mm_extract_epi16"), - (Some(32), Some(128)) => String::from("(uint32_t)_mm_extract_epi32"), - (Some(64), Some(128)) => String::from("(uint64_t)_mm_extract_epi64"), - (Some(8), Some(256)) => String::from("(uint8_t)_mm256_extract_epi8"), - (Some(16), Some(256)) => String::from("(uint16_t)_mm256_extract_epi16"), - (Some(32), Some(256)) => String::from("(uint32_t)_mm256_extract_epi32"), - (Some(64), Some(256)) => String::from("(uint64_t)_mm256_extract_epi64"), - (Some(8), Some(512)) => String::from("(uint8_t)_mm512_extract_intrinsic_test_epi8"), - (Some(16), Some(512)) => String::from("(uint16_t)_mm512_extract_intrinsic_test_epi16"), - (Some(32), Some(512)) => String::from("(uint32_t)_mm512_extract_intrinsic_test_epi32"), - (Some(64), Some(512)) => String::from("(uint64_t)_mm512_extract_intrinsic_test_epi64"), - _ => unreachable!( - "invalid length for vector argument: {:?}, {:?}", - self.bit_len, self.simd_len - ), - } - } - - fn rust_scalar_type(&self) -> String { - let prefix = match self.data.kind { - TypeKind::Mask => String::from("__mmask"), - TypeKind::Vector => String::from("i"), - _ => self.kind().rust_prefix().to_string(), - }; - - let bits = if self.inner_size() >= 128 { - 32 } else { - self.inner_size() - }; - format!("{prefix}{bits}") - } - - fn print_result_rust(&self) -> String { - let return_value = match self.kind() { - // `_mm{256}_cvtps_ph` has return type __m128i but contains f16 values - TypeKind::Float if self.param.type_data == "__m128i" => { - "format_args!(\"{:.150?}\", debug_as::<_, f16>(__return_value))".to_string() - } - TypeKind::Int(_) - if ["__m128i", "__m256i", "__m512i"].contains(&self.param.type_data.as_str()) => - { - format!("debug_as::<_, u{}>(__return_value)", self.inner_size()) - } - _ => "format_args!(\"{__return_value:.150?}\")".to_string(), - }; - - return_value + self.rust_type().replace("__mmask", "u") + } } } @@ -336,7 +187,7 @@ impl X86IntrinsicType { Ok(num_bits) => self .data .bit_len - .and_then(|bit_len| Some(num_bits / bit_len)), + .and_then(|bit_len| Some(SimdLen::Fixed(num_bits / bit_len))), Err(_) => None, }; } @@ -446,7 +297,7 @@ impl X86IntrinsicType { // - _mm512_conj_pch if param.type_data == "__m512h" && param.etype == "FP32" { data.bit_len = Some(16); - data.simd_len = Some(32); + data.simd_len = Some(SimdLen::Fixed(32)); } let mut result = X86IntrinsicType { diff --git a/library/stdarch/crates/intrinsic-test/src/x86/xml_parser.rs b/library/stdarch/crates/intrinsic-test/src/x86/xml_parser.rs index 681b1a3c52743..2296dffb64a5b 100644 --- a/library/stdarch/crates/intrinsic-test/src/x86/xml_parser.rs +++ b/library/stdarch/crates/intrinsic-test/src/x86/xml_parser.rs @@ -1,6 +1,7 @@ use crate::common::argument::{Argument, ArgumentList}; use crate::common::intrinsic::Intrinsic; use crate::common::intrinsic_helpers::TypeKind; +use crate::x86::X86; use crate::x86::constraint::map_constraints; use regex::Regex; @@ -56,13 +57,13 @@ pub struct Parameter { pub fn get_xml_intrinsics( filename: &Path, -) -> Result>, Box> { +) -> Result>, Box> { let file = std::fs::File::open(filename)?; let reader = std::io::BufReader::new(file); let data: Data = quick_xml::de::from_reader(reader).expect("failed to deserialize the source XML file"); - let parsed_intrinsics: Vec> = data + let parsed_intrinsics: Vec> = data .intrinsics .into_iter() .filter(|intrinsic| { @@ -84,9 +85,7 @@ pub fn get_xml_intrinsics( Ok(parsed_intrinsics) } -fn xml_to_intrinsic( - intr: XMLIntrinsic, -) -> Result, Box> { +fn xml_to_intrinsic(intr: XMLIntrinsic) -> Result, Box> { let name = intr.name; let result = X86IntrinsicType::from_param(&intr.return_data); let args_check = intr.parameters.into_iter().enumerate().map(|(i, param)| { @@ -99,14 +98,14 @@ fn xml_to_intrinsic( } else { param.imm_width }; - let constraint = map_constraints(¶m.imm_type, effective_imm_width); - let arg = Argument::::new( + let constraint = map_constraints(&name, ¶m.imm_type, effective_imm_width); + Some(Argument::::new( i, param.var_name.clone(), ty.unwrap(), constraint, - ); - Some(arg) + false, + )) } }); @@ -125,8 +124,8 @@ fn xml_to_intrinsic( // if one of the args has etype="MASK" and type="__md", // then set the bit_len and simd_len accordingly let re = Regex::new(r"__m\d+").unwrap(); - let is_mask = |arg: &Argument| arg.ty.param.etype.as_str() == "MASK"; - let is_vector = |arg: &Argument| re.is_match(arg.ty.param.type_data.as_str()); + let is_mask = |arg: &Argument| arg.ty.param.etype.as_str() == "MASK"; + let is_vector = |arg: &Argument| re.is_match(arg.ty.param.type_data.as_str()); let pos = args_test.position(|arg| is_mask(arg) && is_vector(arg)); if let Some(index) = pos { args[index].ty.bit_len = args[0].ty.bit_len; @@ -134,7 +133,7 @@ fn xml_to_intrinsic( args.iter_mut().for_each(|arg| arg.ty.update_simd_len()); - let arguments = ArgumentList:: { args }; + let arguments = ArgumentList:: { args }; if let Err(message) = result { return Err(Box::from(message)); @@ -145,5 +144,6 @@ fn xml_to_intrinsic( arguments, results: result.unwrap(), arch_tags: intr.cpuid, + extension: intr.tech, }) } diff --git a/library/stdarch/crates/simd-test-macro/src/lib.rs b/library/stdarch/crates/simd-test-macro/src/lib.rs index 92bb40946e1ff..9219540a1065f 100644 --- a/library/stdarch/crates/simd-test-macro/src/lib.rs +++ b/library/stdarch/crates/simd-test-macro/src/lib.rs @@ -71,6 +71,7 @@ pub fn simd_test( "powerpc64" | "powerpc64le" => "is_powerpc64_feature_detected", "loongarch32" | "loongarch64" => "is_loongarch_feature_detected", "s390x" => "is_s390x_feature_detected", + "mips64" | "mips64el" => "is_mips64_feature_detected", t => panic!("unknown target: {t}"), }; let macro_test = Ident::new(macro_test, Span::call_site()); diff --git a/library/stdarch/crates/stdarch-gen-arm/Cargo.toml b/library/stdarch/crates/stdarch-gen-arm/Cargo.toml index de24335a52e86..cb284d5f2c57b 100644 --- a/library/stdarch/crates/stdarch-gen-arm/Cargo.toml +++ b/library/stdarch/crates/stdarch-gen-arm/Cargo.toml @@ -12,11 +12,12 @@ edition = "2024" # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html [dependencies] -itertools = "0.14.0" +itertools = "0.15.0" proc-macro2 = "1.0" quote = "1.0" regex = "1.5" serde = { version = "1.0", features = ["derive"] } +stdarch-gen-common = { path = "../stdarch-gen-common" } serde_with = { version = "3.2.0", default-features = false, features = ["macros"] } serde_yaml = "0.8" walkdir = "2.3.2" diff --git a/library/stdarch/crates/stdarch-gen-arm/README.md b/library/stdarch/crates/stdarch-gen-arm/README.md index 4da14bcbb6c9b..970721681c04a 100644 --- a/library/stdarch/crates/stdarch-gen-arm/README.md +++ b/library/stdarch/crates/stdarch-gen-arm/README.md @@ -1,11 +1,11 @@ # stdarch-gen-arm generator guide ## Running the generator -- Run: `cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec` -``` -$ cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec - Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.18s - Running `target/debug/stdarch-gen-arm crates/stdarch-gen-arm/spec` -``` + +Run: `cargo +nightly run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec crates/core_arch/src` + +NOTE: If you are running this from rust-lang/rust, you must be in the `library/stdarch` +working directory. + ## Input/Output ### Input files (intrinsic YAML definitions) - `crates/stdarch-gen-arm/spec//*.spec.yml` @@ -205,9 +205,6 @@ MatchKind: - `Array` - An array of expressions - Usage: `Array: [, ...]` -- `SvUndef` - - Returns the LLVM `undef` symbol - - Usage: `SvUndef` - `Multiply` - Simply `*` - Usage: `Multiply: [, ]` diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml index a9bc377924dd0..e5ce77ed8b33f 100644 --- a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml +++ b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml @@ -13,9 +13,9 @@ auto_llvm_sign_conversion: false neon-stable: &neon-stable FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] -# #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +# #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] neon-stable-fp16: &neon-stable-fp16 - FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "CURRENT_RUSTC_VERSION"']] + FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "1.94.0"']] # #[cfg(not(target_arch = "arm64ec"))] target-not-arm64ec: &target-not-arm64ec @@ -64,24 +64,36 @@ neon-unstable-feat-lut: &neon-unstable-feat-lut FnCall: [unstable, ['feature = "stdarch_neon_feat_lut"', 'issue = "138050"']] aarch64-stable-jscvt: &aarch64-stable-jscvt - FnCall: [stable, ['feature = "stdarch_aarch64_jscvt"', 'since = "CURRENT_RUSTC_VERSION"']] + FnCall: [stable, ['feature = "stdarch_aarch64_jscvt"', 'since = "1.95.0"']] # #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] neon-unstable-feat-lrcpc3: &neon-unstable-feat-lrcpc3 FnCall: [unstable, ['feature = "stdarch_neon_feat_lrcpc3"', 'issue = "none"']] +# #[cfg(target_has_atomic = "64")] +cfg-target-has-atomic-64: &cfg-target-has-atomic-64 + FnCall: [cfg, ['target_has_atomic = "64"']] + # #[unstable(feature = "stdarch_neon_fp8", issue = "none")] neon-unstable-fp8: &neon-unstable-fp8 FnCall: [unstable, ['feature = "stdarch_neon_fp8"', 'issue = "none"']] +# all(test, target_endian = "little") +all-test-little-endian: &all-test-little-endian + FnCall: [all, [test, 'target_endian = "little"']] + # #[cfg(target_endian = "little")] -little-endian: &little-endian +cfg-little-endian: &cfg-little-endian FnCall: [cfg, ['target_endian = "little"']] # #[cfg(target_endian = "big")] -big-endian: &big-endian +cfg-big-endian: &cfg-big-endian FnCall: [cfg, ['target_endian = "big"']] +# all(test, not(target_env = "msvc"), target_endian = "big") +cfg-test-not-msvc-little-endian: &cfg-test-not-msvc-little-endian + FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}, 'target_endian = "little"']] + intrinsics: - name: "vaddd_{type}" doc: Add @@ -170,12 +182,12 @@ intrinsics: - ['d_f64', 'f64'] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[1]}' - - FnCall: - "vabd_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - FnCall: ["vdup_n_{type[1]}", [b]] - - 0 + - - 0 - name: "vabd{type[0]}" doc: "Floating-point absolute difference" @@ -191,125 +203,28 @@ intrinsics: - ['h_f16', 'f16'] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[1]}' - - FnCall: - "vabd_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - FnCall: ["vdup_n_{type[1]}", [b]] - - 0 - - - name: "vabdl_high{neon_type[0].noq}" - doc: Signed Absolute difference Long - arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[1]}" - attr: [*neon-stable] - assert_instr: [sabdl2] - safety: safe - types: - - [int8x16_t, int16x8_t, int8x8_t, uint8x8_t] - compose: - - Let: - - c - - "{neon_type[2]}" - - FnCall: - - simd_shuffle! - - - a - - a - - [8, 9, 10, 11, 12, 13, 14, 15] - - Let: - - d - - "{neon_type[2]}" - - FnCall: - - simd_shuffle! - - - b - - b - - [8, 9, 10, 11, 12, 13, 14, 15] - - Let: - - e - - "{neon_type[3]}" - - FnCall: - - simd_cast - - - FnCall: - - "vabd_{neon_type[0]}" - - - c - - d - - FnCall: - - simd_cast - - - e + - - 0 - name: "vabdl_high{neon_type[0].noq}" doc: Signed Absolute difference Long arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] return_type: "{neon_type[1]}" attr: - - FnCall: - - stable - - - 'feature = "neon_intrinsics"' - - 'since = "1.59.0"' - assert_instr: [sabdl2] + - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sabdl2]]}]] safety: safe types: + - [int8x16_t, int16x8_t, int8x8_t, uint8x8_t] - [int16x8_t, int32x4_t, int16x4_t, uint16x4_t] - compose: - - Let: - - c - - "{neon_type[2]}" - - FnCall: - - simd_shuffle! - - - a - - a - - [4, 5, 6, 7] - - Let: - - d - - "{neon_type[2]}" - - FnCall: - - simd_shuffle! - - - b - - b - - [4, 5, 6, 7] - - Let: - - e - - "{neon_type[3]}" - - FnCall: - - simd_cast - - - FnCall: - - "vabd_{neon_type[0]}" - - - c - - d - - FnCall: - - simd_cast - - - e - - - name: "vabdl_high{neon_type[0].noq}" - doc: Signed Absolute difference Long - arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[1]}" - attr: - - FnCall: - - stable - - - 'feature = "neon_intrinsics"' - - 'since = "1.59.0"' - assert_instr: [sabdl2] - safety: safe - types: - [int32x4_t, int64x2_t, int32x2_t, uint32x2_t] compose: - - Let: - - c - - "{neon_type[2]}" - - FnCall: - - simd_shuffle! - - - a - - a - - [2, 3] - - Let: - - d - - "{neon_type[2]}" - - FnCall: - - simd_shuffle! - - - b - - b - - [2, 3] + - Let: [c, FnCall: ['vget_high_{neon_type[0]}', [a]]] + - Let: [d, FnCall: ['vget_high_{neon_type[0]}', [b]]] - Let: - e - "{neon_type[3]}" @@ -329,7 +244,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmeq]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [uint64x1_t, uint64x1_t] @@ -347,7 +262,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmeq]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, uint64x1_t] @@ -361,19 +276,19 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vceq_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - FnCall: ["vdup_n_{type[1]}", [b]] - - '0' + - - 0 - name: "vceq{type[0]}" @@ -390,12 +305,12 @@ intrinsics: - ["h_f16", "f16", "u16"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vceq_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - FnCall: ["vdup_n_{type[1]}", [b]] - - '0' + - - 0 - name: "vceqd_{type[0]}" doc: "Compare bitwise equal" @@ -403,7 +318,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i64", "u64", "s64"] @@ -422,7 +337,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmtst]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int64x1_t, uint64x1_t, 'i64x1', 'i64x1::new(0)'] @@ -440,7 +355,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tst]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i64", "u64", "s64"] @@ -459,7 +374,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [suqadd]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_s32", "i32", "u32"] @@ -477,19 +392,19 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [suqadd]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["b_s8", "i8", "u8", "s8"] - ["h_s16", "i16", "u16", "s16"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[3]}' - - FnCall: - "vuqadd_{type[3]}" - - FnCall: ["vdup_n_{type[3]}", [a]] - FnCall: ["vdup_n_{type[2]}", [b]] - - '0' + - - '0' - name: "vabs{neon_type.no}" doc: "Floating-point absolute value" @@ -497,7 +412,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fabs]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - float64x1_t @@ -511,7 +426,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmgt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int64x1_t, uint64x1_t] @@ -525,7 +440,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmhi]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - uint64x1_t @@ -539,7 +454,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmgt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, uint64x1_t] @@ -553,19 +468,19 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] compose: - FnCall: - - 'simd_extract!' + - 'vget_lane_{type[2]}' - - FnCall: - "vcgt_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - FnCall: ["vdup_n_{type[1]}", [b]] - - '0' + - - '0' - name: "vcgt{type[0]}" @@ -582,12 +497,12 @@ intrinsics: - ["h_f16", "f16", "u16"] compose: - FnCall: - - 'simd_extract!' + - 'vget_lane_{type[2]}' - - FnCall: - "vcgt_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - FnCall: ["vdup_n_{type[1]}", [b]] - - '0' + - - '0' - name: "vclt{neon_type[0].no}" doc: "Compare signed less than" @@ -595,7 +510,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmgt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int64x1_t, uint64x1_t] @@ -609,7 +524,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmge]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int64x1_t, uint64x1_t] @@ -623,7 +538,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmge]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, uint64x1_t] @@ -637,19 +552,19 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vcle_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - FnCall: ["vdup_n_{type[1]}", [b]] - - '0' + - - '0' - name: "vcle{type[0]}" @@ -666,12 +581,12 @@ intrinsics: - ["h_f16", "f16", "u16"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vcle_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - FnCall: ["vdup_n_{type[1]}", [b]] - - '0' + - - '0' - name: "vcge{neon_type[0].no}" doc: "Compare signed greater than or equal" @@ -679,7 +594,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmge]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int64x1_t, uint64x1_t] @@ -693,7 +608,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmge]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] @@ -714,7 +629,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i64", "u64"] @@ -731,7 +646,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmle]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] @@ -755,7 +670,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmle]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, uint32x2_t, f32x2, 'f32x2::new(0.0, 0.0)'] @@ -775,18 +690,18 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vclez_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - - '0' + - - '0' - name: "vclez{type[0]}" doc: "Floating-point compare less than or equal to zero" @@ -802,11 +717,11 @@ intrinsics: - ["h_f16", "f16", "u16"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vclez_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - - '0' + - - '0' - name: "vcltz{neon_type[0].no}" doc: "Compare signed less than zero" @@ -814,7 +729,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmlt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] @@ -838,7 +753,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmlt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, uint32x2_t, f32x2, 'f32x2::new(0.0, 0.0)'] @@ -858,18 +773,18 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vcltz_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - - '0' + - - '0' - name: "vcltz{type[0]}" doc: "Floating-point compare less than zero" @@ -885,11 +800,11 @@ intrinsics: - ["h_f16", "f16", "u16"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vcltz_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - - '0' + - - '0' - name: "vcltzd_s64" doc: "Compare less than zero" @@ -897,7 +812,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [asr]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i64", "u64"] @@ -914,7 +829,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facgt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, uint64x1_t] @@ -932,7 +847,7 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facgt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32", i32] @@ -971,7 +886,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facge]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, uint64x1_t] @@ -989,7 +904,7 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facge]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32", i32] @@ -1029,7 +944,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facgt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, uint64x1_t] @@ -1043,7 +958,7 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facgt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32"] @@ -1072,7 +987,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facge]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, uint64x1_t] @@ -1086,7 +1001,7 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facge]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32"] @@ -1115,7 +1030,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [scvtf]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int64x1_t, float64x1_t] @@ -1129,7 +1044,7 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [scvtf]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "i32", "f32", s32] @@ -1143,7 +1058,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ucvtf]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [uint64x1_t, float64x1_t] @@ -1157,7 +1072,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ucvtf]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["u32", "f32", "s_f32"] @@ -1172,7 +1087,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [scvtf, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -1310,7 +1225,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [scvtf, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -1336,7 +1251,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ucvtf, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -1361,7 +1276,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ucvtf, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -1385,7 +1300,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzs]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "i32", "s_s32_f32", "32"] @@ -1399,7 +1314,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzu]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "u32", "s_u32_f32"] @@ -1484,7 +1399,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, float64x2_t] @@ -1496,28 +1411,20 @@ intrinsics: arguments: ["a: {neon_type[0]}"] return_type: "{neon_type[1]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtl2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtl2]]}]] + - *neon-stable safety: safe types: - [float32x4_t, float64x2_t] compose: - - Let: - - b - - float32x2_t - - FnCall: - - simd_shuffle! - - - a - - a - - '[2, 3]' - - FnCall: [simd_cast, [b]] + - FnCall: [simd_cast, [{FnCall: ['vget_high_{neon_type[0]}', [a]]}]] - name: "vcvt_high_f16_f32" doc: "Floating-point convert to lower precision" arguments: ["a: {neon_type[1]}", "b: {neon_type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtn2]]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtn2]]}]] - *neon-stable-fp16 - *target-not-arm64ec safety: safe @@ -1534,7 +1441,7 @@ intrinsics: arguments: ["a: {neon_type[1]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtl2]]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtl2]]}]] - *neon-stable-fp16 - *target-not-arm64ec safety: safe @@ -1551,8 +1458,8 @@ intrinsics: arguments: ["a: {neon_type[0]}"] return_type: "{neon_type[1]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtn]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtn]]}]] + - *neon-stable safety: safe types: - [float64x2_t, float32x2_t] @@ -1564,25 +1471,24 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtn2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtn2]]}]] + - *neon-stable safety: safe types: - [float32x2_t, float64x2_t, float32x4_t] compose: - FnCall: - - simd_shuffle! + - vcombine_f32 - - a - - FnCall: [simd_cast, [b]] - - '[0, 1, 2, 3]' + - FnCall: [vcvt_f32_f64, [b]] - name: "vcvtx_f32_f64" doc: "Floating-point convert to lower precision narrow, rounding to odd" arguments: ["a: {neon_type[0]}"] return_type: "{neon_type[1]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtxn]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtxn]]}]] + - *neon-stable safety: safe types: - [float64x2_t, float32x2_t] @@ -1599,34 +1505,33 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtxn]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f64", "f32"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[1]}' - - FnCall: - vcvtx_f32_f64 - - FnCall: [vdupq_n_f64, [a]] - - '0' + - - '0' - name: "vcvtx_high_f32_f64" doc: "Floating-point convert to lower precision narrow, rounding to odd" arguments: ["a: {type[0]}", "b: {neon_type[1]}"] return_type: "{type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtxn2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtxn2]]}]] + - *neon-stable safety: safe types: - [float32x2_t, float64x2_t, float32x4_t] compose: - FnCall: - - simd_shuffle! + - vcombine_f32 - - a - FnCall: [vcvtx_f32_f64, [b]] - - '[0, 1, 2, 3]' - name: "vcvt{type[2]}" doc: "Floating-point convert to fixed-point, rounding toward zero" @@ -1635,7 +1540,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzs, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -1658,7 +1563,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzs, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -1752,7 +1657,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzu, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -1775,7 +1680,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzu, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -1797,7 +1702,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtas]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, int32x2_t, _s32_f32] @@ -1838,7 +1743,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtas]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "i32", 's_s32_f32'] @@ -1862,9 +1767,9 @@ intrinsics: - *target-not-arm64ec safety: safe types: + - ["f16", "u16", 'h_u16_f16'] - ["f16", "u32", 'h_u32_f16'] - ["f16", "u64", 'h_u64_f16'] - compose: - LLVMLink: name: "vcvta{type[2]}" @@ -1884,6 +1789,7 @@ intrinsics: - *target-not-arm64ec safety: safe types: + - ["f16", "i16", 'h_s16_f16'] - ["f16", "i32", 'h_s32_f16'] - ["f16", "i64", 'h_s64_f16'] compose: @@ -1894,44 +1800,13 @@ intrinsics: - link: "llvm.aarch64.neon.fcvtas.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - - name: "vcvta{type[2]}" - doc: "Floating-point convert to integer, rounding to nearest with ties to away" - arguments: ["a: {type[0]}"] - return_type: "{type[1]}" - attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtas]]}]] - - *neon-fp16 - - *neon-unstable-f16 - - *target-not-arm64ec - safety: safe - types: - - ["f16", "i16", 'h_s16_f16', 's32'] - compose: - - 'vcvtah_{type[3]}_f16(a) as i16' - - - name: "vcvta{type[2]}" - doc: "Floating-point convert to integer, rounding to nearest with ties to away" - arguments: ["a: {type[0]}"] - return_type: "{type[1]}" - attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtau]]}]] - - *neon-fp16 - - *neon-unstable-f16 - - *target-not-arm64ec - safety: safe - types: - - ["f16", "u16", 'h_u16_f16', 'u32'] - compose: - - 'vcvtah_{type[3]}_f16(a) as u16' - - name: "vcvta{type[2]}" doc: "Floating-point convert to integer, rounding to nearest with ties to away" arguments: ["a: {type[0]}"] return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtau]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "u32", 's_u32_f32'] @@ -1949,7 +1824,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtns]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, int32x2_t] @@ -1969,7 +1844,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtns]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "i32", 's_s32_f32'] @@ -2034,6 +1909,7 @@ intrinsics: - *target-not-arm64ec safety: safe types: + - ["f16", "i16", 'h'] - ["f16", "i32", 'h'] - ["f16", "i64", 'h'] compose: @@ -2044,22 +1920,6 @@ intrinsics: - link: "llvm.aarch64.neon.fcvtns.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - name: "vcvtn{type[2]}_{type[1]}_{type[0]}" - doc: "Floating-point convert to integer, rounding to nearest with ties to even" - arguments: ["a: {type[0]}"] - return_type: "{type[1]}" - attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtns]]}]] - - *neon-fp16 - - *neon-unstable-f16 - - *target-not-arm64ec - safety: safe - types: - - ["f16", "i16", 'h', 'i32'] - compose: - - 'vcvtnh_{type[3]}_f16(a) as i16' - - - name: "vcvtn{type[2]}_{type[1]}_{type[0]}" doc: "Floating-point convert to unsigned integer, rounding to nearest with ties to even" arguments: ["a: {type[0]}"] @@ -2071,6 +1931,7 @@ intrinsics: - *target-not-arm64ec safety: safe types: + - ["f16", "u16", 'h'] - ["f16", "u32", 'h'] - ["f16", "u64", 'h'] compose: @@ -2081,28 +1942,13 @@ intrinsics: - link: "llvm.aarch64.neon.fcvtnu.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - name: "vcvtn{type[2]}_{type[1]}_{type[0]}" - doc: "Floating-point convert to unsigned integer, rounding to nearest with ties to even" - arguments: ["a: {type[0]}"] - return_type: "{type[1]}" - attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtnu]]}]] - - *neon-fp16 - - *neon-unstable-f16 - - *target-not-arm64ec - safety: safe - types: - - ["f16", "u16", 'h', 'u32'] - compose: - - 'vcvtnh_{type[3]}_f16(a) as u16' - - name: "vcvtm{neon_type[1].no}_{neon_type[0]}" doc: "Floating-point convert to signed integer, rounding toward minus infinity" arguments: ["a: {neon_type[0]}"] return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtms]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, int32x2_t] @@ -2165,7 +2011,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtms]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "i32", 's_s32_f32'] @@ -2183,7 +2029,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtps]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, int32x2_t] @@ -2203,7 +2049,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtps]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "i32", 's_s32_f32'] @@ -2221,7 +2067,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtnu]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, uint32x2_t] @@ -2241,7 +2087,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtnu]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "u32", 's_u32_f32'] @@ -2259,7 +2105,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtmu]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, uint32x2_t] @@ -2279,7 +2125,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtmu]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "u32", s_u32_f32] @@ -2297,7 +2143,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtpu]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, uint32x2_t] @@ -2317,7 +2163,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtpu]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "u32", s_u32_f32, 'i32'] @@ -2386,6 +2232,7 @@ intrinsics: - *target-not-arm64ec safety: safe types: + - ["f16", "i16", 'h'] - ["f16", "i32", 'h'] - ["f16", "i64", 'h'] compose: @@ -2396,21 +2243,6 @@ intrinsics: - link: "llvm.aarch64.neon.fcvtps.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - name: "vcvtp{type[2]}_{type[1]}_{type[0]}" - doc: "Floating-point convert to integer, rounding to plus infinity" - arguments: ["a: {type[0]}"] - return_type: "{type[1]}" - attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtps]]}]] - - *neon-fp16 - - *neon-unstable-f16 - - *target-not-arm64ec - safety: safe - types: - - ["f16", "i16", 'h', 'i32'] - compose: - - 'vcvtph_{type[3]}_f16(a) as i16' - - name: "vcvtp{type[2]}_{type[1]}_{type[0]}" doc: "Floating-point convert to unsigned integer, rounding to plus infinity" arguments: ["a: {type[0]}"] @@ -2422,6 +2254,7 @@ intrinsics: - *target-not-arm64ec safety: safe types: + - ["f16", "u16", 'h'] - ["f16", "u32", 'h'] - ["f16", "u64", 'h'] compose: @@ -2432,21 +2265,6 @@ intrinsics: - link: "llvm.aarch64.neon.fcvtpu.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - name: "vcvtp{type[2]}_{type[1]}_{type[0]}" - doc: "Floating-point convert to unsigned integer, rounding to plus infinity" - arguments: ["a: {type[0]}"] - return_type: "{type[1]}" - attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtpu]]}]] - - *neon-fp16 - - *neon-unstable-f16 - - *target-not-arm64ec - safety: safe - types: - - ["f16", "u16", 'h', 'u32'] - compose: - - 'vcvtph_{type[3]}_f16(a) as u16' - - name: "vdup{neon_type.laneq_nox}" doc: "Set all vector lanes to the same value" arguments: ["a: {neon_type}"] @@ -2454,8 +2272,9 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [dup, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] + big_endian_inverse: true safety: safe types: - poly64x2_t @@ -2471,8 +2290,9 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [dup, 'N = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] + big_endian_inverse: true safety: safe types: - [poly64x1_t, poly64x2_t] @@ -2488,7 +2308,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -2505,7 +2325,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -2514,7 +2334,7 @@ intrinsics: - [float64x1_t, "f64"] compose: - FnCall: [static_assert!, ['N == 0']] - - FnCall: [simd_extract!, [a, 'N as u32']] + - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]] - name: "vdup_laneq_{neon_type[0]}" doc: "Set all vector lanes to the same value" @@ -2523,7 +2343,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -2532,8 +2352,8 @@ intrinsics: compose: - FnCall: [static_assert_uimm_bits!, [N, 1]] - FnCall: - - "transmute::<{type[2]}, _>" - - - FnCall: [simd_extract!, [a, 'N as u32']] + - transmute + - - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]] - name: "vdup{type[2]}" doc: "Set all vector lanes to the same value" @@ -2542,7 +2362,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -2554,7 +2374,7 @@ intrinsics: - [float64x2_t, "f64", d_laneq_f64] compose: - FnCall: [static_assert_uimm_bits!, [N, 1]] - - FnCall: [simd_extract!, [a, 'N as u32']] + - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]] - name: "vdup{type[2]}" doc: "Set all vector lanes to the same value" @@ -2563,7 +2383,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 4']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -2575,7 +2395,7 @@ intrinsics: - [poly16x8_t, "p16", h_laneq_p16] compose: - FnCall: [static_assert_uimm_bits!, [N, 3]] - - FnCall: [simd_extract!, [a, 'N as u32']] + - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]] - name: "vdup{type[2]}" @@ -2594,7 +2414,7 @@ intrinsics: - [float16x4_t, "f16", h_lane_f16] compose: - FnCall: [static_assert_uimm_bits!, [N, 2]] - - FnCall: [simd_extract!, [a, 'N as u32']] + - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]] - name: "vdup{type[2]}" @@ -2613,7 +2433,7 @@ intrinsics: - [float16x8_t, "f16", h_laneq_f16] compose: - FnCall: [static_assert_uimm_bits!, [N, 4]] - - FnCall: [simd_extract!, [a, 'N as u32']] + - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]] - name: "vdup{type[2]}" @@ -2623,7 +2443,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 8']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -2632,7 +2452,7 @@ intrinsics: - [poly8x16_t, "p8", b_laneq_p8] compose: - FnCall: [static_assert_uimm_bits!, [N, 4]] - - FnCall: [simd_extract!, [a, 'N as u32']] + - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]] - name: "vdup{type[2]}" doc: "Set all vector lanes to the same value" @@ -2641,7 +2461,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -2653,24 +2473,25 @@ intrinsics: - [float32x4_t, "f32", s_laneq_f32] compose: - FnCall: [static_assert_uimm_bits!, [N, 2]] - - FnCall: [simd_extract!, [a, 'N as u32']] + - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]] - - name: "vext{neon_type[0].no}" + - name: "vext{neon_type.no}" doc: "Extract vector from pair of vectors" - arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[0]}" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ext, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] + big_endian_inverse: true safety: safe types: - - [poly64x2_t, ' static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }'] - - [float64x2_t, ' static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }'] + - poly64x2_t + - float64x2_t compose: - - Identifier: ["{type[1]}", Symbol] - - Identifier: ["{type[2]}", Symbol] + - FnCall: [static_assert_uimm_bits!, [N, 1]] + - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1]']] - name: "vmla{neon_type.no}" doc: "Floating-point multiply-add to accumulator" @@ -2678,7 +2499,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - float64x1_t @@ -2691,16 +2512,16 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlal2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlal2]]}]] + - *neon-stable safety: safe types: - - [int16x8_t, int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [int32x4_t, int16x8_t, int16x4_t, '[4, 5, 6, 7]', '[4, 5, 6, 7]'] - - [int64x2_t, int32x4_t, int32x2_t, '[2, 3]', '[2, 3]'] + - [int16x8_t, int8x16_t, int8x8_t] + - [int32x4_t, int16x8_t, int16x4_t] + - [int64x2_t, int32x4_t, int32x2_t] compose: - - Let: [b, "{neon_type[2]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}] - - Let: [c, "{neon_type[2]}", {FnCall: [simd_shuffle!, [c, c, "{type[4]}"]]}] + - Let: [b, {FnCall: ['vget_high_{neon_type[1]}', [b]]}] + - Let: [c, {FnCall: ['vget_high_{neon_type[1]}', [c]]}] - FnCall: ["vmlal_{neon_type[2]}", [a, b, c]] - name: "vmlal_high_{neon_type[1]}" @@ -2708,22 +2529,16 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlal2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlal2]]}]] + - *neon-stable safety: safe types: - - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint32x4_t, uint16x8_t, uint16x4_t, '[4, 5, 6, 7]'] - - [uint64x2_t, uint32x4_t, uint32x2_t, '[2, 3]'] + - [uint16x8_t, uint8x16_t, uint8x8_t] + - [uint32x4_t, uint16x8_t, uint16x4_t] + - [uint64x2_t, uint32x4_t, uint32x2_t] compose: - - Let: - - b - - "{neon_type[2]}" - - FnCall: [simd_shuffle!, [b, b, "{type[3]}"]] - - Let: - - c - - "{neon_type[2]}" - - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]] + - Let: [b, {FnCall: ['vget_high_{neon_type[1]}', [b]]}] + - Let: [c, {FnCall: ['vget_high_{neon_type[1]}', [c]]}] - FnCall: ["vmlal_{neon_type[1]}", [a, b, c]] - name: "vmlsl_high_{neon_type[1]}" @@ -2731,22 +2546,16 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlsl2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlsl2]]}]] + - *neon-stable safety: safe types: - - [int16x8_t, int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [int32x4_t, int16x8_t, int16x4_t, '[4, 5, 6, 7]'] - - [int64x2_t, int32x4_t, int32x2_t, '[2, 3]'] + - [int16x8_t, int8x16_t, int8x8_t] + - [int32x4_t, int16x8_t, int16x4_t] + - [int64x2_t, int32x4_t, int32x2_t] compose: - - Let: - - b - - "{neon_type[2]}" - - FnCall: [simd_shuffle!, [b, b, "{type[3]}"]] - - Let: - - c - - "{neon_type[2]}" - - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]] + - Let: [b, {FnCall: ['vget_high_{neon_type[1]}', [b]]}] + - Let: [c, {FnCall: ['vget_high_{neon_type[1]}', [c]]}] - FnCall: ["vmlsl_{neon_type[1]}", [a, b, c]] - name: "vmlsl_high_{neon_type[1]}" @@ -2754,44 +2563,38 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlsl2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlsl2]]}]] + - *neon-stable safety: safe types: - - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint32x4_t, uint16x8_t, uint16x4_t, '[4, 5, 6, 7]'] - - [uint64x2_t, uint32x4_t, uint32x2_t, '[2, 3]'] + - [uint16x8_t, uint8x16_t, uint8x8_t] + - [uint32x4_t, uint16x8_t, uint16x4_t] + - [uint64x2_t, uint32x4_t, uint32x2_t] compose: - - Let: [b, "{neon_type[2]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}] - - Let: [c, "{neon_type[2]}", {FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]}] + - Let: [b, {FnCall: ['vget_high_{neon_type[1]}', [b]]}] + - Let: [c, {FnCall: ['vget_high_{neon_type[1]}', [c]]}] - FnCall: ["vmlsl_{neon_type[1]}", [a, b, c]] - name: "vmovn_high{neon_type[1].noq}" doc: Extract narrow arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" - attr: [*neon-stable] - assert_instr: [xtn2] + attr: + - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [xtn2]]}]] safety: safe types: - - [int8x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [int16x4_t, int32x4_t, int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [int32x2_t, int64x2_t, int32x4_t, '[0, 1, 2, 3]'] - - [uint8x8_t, uint16x8_t, uint8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, uint32x4_t, uint16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, uint64x2_t, uint32x4_t, '[0, 1, 2, 3]'] + - [int8x8_t, int16x8_t, int8x16_t] + - [int16x4_t, int32x4_t, int16x8_t] + - [int32x2_t, int64x2_t, int32x4_t] + - [uint8x8_t, uint16x8_t, uint8x16_t] + - [uint16x4_t, uint32x4_t, uint16x8_t] + - [uint32x2_t, uint64x2_t, uint32x4_t] compose: - - Let: - - c - - "{neon_type[0]}" - - FnCall: - - simd_cast - - - b - FnCall: - - simd_shuffle! + - 'vcombine_{neon_type[0]}' - - a - - c - - "{type[3]}" + - FnCall: ['simd_cast', [b]] - name: "vneg{neon_type.no}" doc: Negate @@ -2869,11 +2672,11 @@ intrinsics: - [i64, 'd_s64', 's64'] compose: - FnCall: - - 'simd_extract!' + - 'vget_lane_{type[2]}' - - FnCall: - 'vqneg_{type[2]}' - - FnCall: ['vdup_n_{type[2]}', [a]] - - 0 + - - 0 - name: "vqneg{neon_type[0].no}" doc: Signed saturating negate @@ -2950,12 +2753,12 @@ intrinsics: - "vdup_n_{type[2]}" - - b - FnCall: - - 'simd_extract!' + - 'vget_lane_{type[2]}' - - FnCall: - "vqsub_{type[2]}" - - a - b - - "0" + - - "0" - name: "vqsub{type[3]}" doc: Saturating subtract @@ -2981,12 +2784,12 @@ intrinsics: - "vdup_n_{type[2]}" - - b - FnCall: - - 'simd_extract!' + - 'vget_lane_{type[2]}' - - FnCall: - "vqsub_{type[2]}" - - a - b - - "0" + - - "0" - name: "vrbit{neon_type.no}" doc: Reverse bit order @@ -3435,12 +3238,12 @@ intrinsics: - "vdup_n_{type[0]}" - - b - FnCall: - - simd_extract! + - 'vget_lane_{type[0]}' - - FnCall: - "vqadd_{type[0]}" - - a - b - - "0" + - - "0" - name: "vqadd{type[2]}" doc: Saturating add @@ -3466,19 +3269,19 @@ intrinsics: - "vdup_n_{type[0]}" - - b - FnCall: - - simd_extract! + - 'vget_lane_{type[0]}' - - FnCall: - "vqadd_{type[0]}" - - a - b - - "0" + - - "0" - name: "vld1{neon_type[1].no}" doc: "Load multiple single-element structures to one, two, three, or four registers" - arguments: ["a: {type[0]}"] + arguments: ["ptr: {type[0]}"] return_type: "{neon_type[1]}" attr: [*neon-stable] - assert_instr: [ld1] + assert_instr: [ld] safety: unsafe: [neon] types: @@ -3489,11 +3292,12 @@ intrinsics: - ["*const f64", float64x1x4_t] - ["*const f64", float64x2x4_t] compose: - - LLVMLink: - name: "vld1{neon_type[1].no}" - links: - - link: "llvm.aarch64.neon.ld1x{neon_type[1].tuple}.v{neon_type[1].lane}f{neon_type[1].base}.p0" - arch: aarch64,arm64ec + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - ptr + - cast + - [] - name: "vld2{neon_type[1].lane_nox}" doc: Load multiple 2-element structures to two registers @@ -3694,16 +3498,12 @@ intrinsics: types: - ["*const f64", float64x1x2_t, f64, float64x1_t] compose: - - LLVMLink: - name: "vld2.{neon_type[1]}" - arguments: - - "ptr: *const {neon_type[3]}" - links: - - link: "llvm.aarch64.neon.ld2.v{neon_type[1].lane}{type[2]}.p0" - arch: aarch64,arm64ec - FnCall: - - "_vld2{neon_type[1].nox}" - - - "a as _" + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld2{neon_type[1].nox}" doc: Load multiple 2-element structures to two registers @@ -3820,7 +3620,7 @@ intrinsics: safety: unsafe: [neon] types: - - ['*const i8', int8x16x3_t, int8x16_t, i8, '3'] + - ['*const i8', int8x16x3_t, int8x16_t, i8, '4'] - ['*const i64', int64x2x3_t, int64x2_t, i64, '1'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[4]}']] @@ -4029,17 +3829,10 @@ intrinsics: unsafe: [neon] assert_instr: [ld3] types: - - ['*const i64', int64x2x3_t, '*const int64x2_t', i64] - - ['*const f64', float64x2x3_t, '*const float64x2_t', f64] + - ['*const i64', int64x2x3_t, i64, "2"] + - ['*const f64', float64x2x3_t, f64, "2"] compose: - - LLVMLink: - name: 'vld3{neon_type[1].nox}' - arguments: - - 'ptr: {type[2]}' - links: - - link: 'llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[3]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld3{neon_type[1].nox}', ['a as _']] + - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "3", a], [], true] - name: "vld3{neon_type[1].nox}" doc: Load multiple 3-element structures to three registers @@ -4052,14 +3845,12 @@ intrinsics: types: - ['*const f64', float64x1x3_t, '*const float64x1_t', f64] compose: - - LLVMLink: - name: 'vld3{neon_type[1].nox}' - arguments: - - 'ptr: {type[2]}' - links: - - link: 'llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[3]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld3{neon_type[1].nox}', ['a as _']] + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld3{neon_type[1].nox}" doc: Load multiple 3-element structures to three registers @@ -4173,17 +3964,11 @@ intrinsics: safety: unsafe: [neon] types: - - ['*const f64', float64x2x4_t, f64, '*const float64x2_t'] - - ['*const i64', int64x2x4_t, i64, '*const int64x2_t'] + - ['*const f64', float64x2x4_t, f64, "2"] + - ['*const i64', int64x2x4_t, i64, "2"] compose: - - LLVMLink: - name: 'vld4{neon_type[1].nox}' - arguments: - - 'ptr: {type[3]}' - links: - - link: 'llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld4{neon_type[1].nox}', ['a as _']] + - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "4", a], [], true] + - name: "vld4{neon_type[1].nox}" doc: Load multiple 4-element structures to four registers @@ -4197,14 +3982,12 @@ intrinsics: types: - ['*const f64', float64x1x4_t, f64, '*const float64x1_t'] compose: - - LLVMLink: - name: 'vld4{neon_type[1].nox}' - arguments: - - 'ptr: {type[3]}' - links: - - link: 'llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld4{neon_type[1].nox}', ['a as _']] + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld4{neon_type[1].nox}" doc: Load multiple 4-element structures to four registers @@ -4259,7 +4042,7 @@ intrinsics: safety: unsafe: [neon] types: - - ['*const i8', int8x16x4_t, int8x16_t, i8, '3'] + - ['*const i8', int8x16x4_t, int8x16_t, i8, '4'] - ['*const i64', int64x2x4_t, int64x2_t, i64, '1'] - ['*const f64', float64x2x4_t, float64x2_t, f64, '1'] compose: @@ -4418,6 +4201,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ["2"]] - *neon-unstable-feat-lrcpc3 + - *cfg-target-has-atomic-64 types: - ['*const i64', int64x1_t, 'static_assert!', 'LANE == 0'] - ['*const i64', int64x2_t,'static_assert_uimm_bits!', 'LANE, 1'] @@ -4448,6 +4232,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,rcpc3"']] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]] - *neon-unstable-feat-lrcpc3 + - *cfg-target-has-atomic-64 types: - ['*const u64', uint64x1_t,'static_assert!', 'LANE == 0',''] #- ['*const f64', float64x1_t,'static_assert!', 'LANE == 0',''] # Fails due to bad IR gen from rust @@ -4468,12 +4253,15 @@ intrinsics: doc: "Store-Release a single-element structure from one lane of one register." arguments: ["ptr: {type[0]}", "val: {neon_type[1]}"] static_defs: ["const LANE: i32"] - safety: safe + safety: + unsafe: + - pointer_write: ptr attr: - FnCall: [target_feature, ['enable = "neon,rcpc3"']] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ["2"]] - *neon-unstable-feat-lrcpc3 + - *cfg-target-has-atomic-64 types: - ['*mut i64', int64x1_t,'static_assert!', 'LANE == 0'] - ['*mut i64', int64x2_t,'static_assert_uimm_bits!', 'LANE, 1'] @@ -4486,7 +4274,7 @@ intrinsics: - Let: - "lane" - i64 - - FnCall: [simd_extract!, [val, 'LANE as u32']] + - FnCall: ['vget{neon_type[1].lane_nox}', [val], [LANE]] - MethodCall: - "(*atomic_dst)" - store @@ -4496,12 +4284,15 @@ intrinsics: doc: "Store-Release a single-element structure from one lane of one register." arguments: ["ptr: {type[0]}", "val: {neon_type[1]}"] static_defs: ["const LANE: i32"] - safety: safe + safety: + unsafe: + - pointer_write: ptr attr: - FnCall: [target_feature, ['enable = "neon,rcpc3"']] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ["2"]] - *neon-unstable-feat-lrcpc3 + - *cfg-target-has-atomic-64 types: - ['*mut u64', uint64x1_t, 'static_assert!', 'LANE == 0',''] - ['*mut f64', float64x1_t,'static_assert!', 'LANE == 0',''] @@ -4561,20 +4352,11 @@ intrinsics: unsafe: [neon] attr: - *neon-stable - assert_instr: [st1] + assert_instr: [stp] types: - - ['f64', float64x1x2_t, float64x1_t] + - ['f64', float64x1x2_t] compose: - - LLVMLink: - name: 'st2.{neon_type[1]}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st2.v{neon_type[1].lane}{type[0]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst2{neon_type[1].nox}', ['b.0', 'b.1', 'a as _']] + - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]] - name: "vst2{neon_type[1].nox}" doc: "Store multiple 2-element structures from two registers" @@ -4585,19 +4367,10 @@ intrinsics: - *neon-stable assert_instr: [st2] types: - - [i64, int64x2x2_t, int64x2_t] - - [f64, float64x2x2_t, float64x2_t] + - [i64, int64x2x2_t, "2"] + - [f64, float64x2x2_t, "2"] compose: - - LLVMLink: - name: 'st2.{neon_type[1]}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st2.v{neon_type[1].lane}{type[0]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst2{neon_type[1].nox}', ['b.0', 'b.1', 'a as _']] + - FnCall: ["crate::core_arch::macros::interleaving_store!", [{ Type: "{type[0]}" }, "{type[2]}", "2", a, b], [], true] - name: "vst2{neon_type[1].lane_nox}" doc: "Store multiple 2-element structures from two registers" @@ -4775,19 +4548,9 @@ intrinsics: safety: unsafe: [neon] types: - - [f64, float64x1x3_t, float64x1_t] + - [f64, float64x1x3_t] compose: - - LLVMLink: - name: 'st3.{neon_type[1].nox}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'c: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st3.v{neon_type[1].lane}{type[0]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst3{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'a as _']] + - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]] - name: "vst3{neon_type[1].lane_nox}" doc: "Store multiple 3-element structures from three registers" @@ -4854,20 +4617,10 @@ intrinsics: safety: unsafe: [neon] types: - - [i64, int64x2x3_t, int64x2_t] - - [f64, float64x2x3_t, float64x2_t] + - [i64, int64x2x3_t, "2"] + - [f64, float64x2x3_t, "2"] compose: - - LLVMLink: - name: 'st3.{neon_type[1].nox}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'c: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st3.v{neon_type[1].lane}{type[0]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst3{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'a as _']] + - FnCall: ["crate::core_arch::macros::interleaving_store!", [{ Type: "{type[0]}" }, "{type[2]}", "3", a, b], [], true] - name: "vst3{neon_type[1].nox}" doc: "Store multiple 3-element structures from three registers" @@ -4989,20 +4742,9 @@ intrinsics: safety: unsafe: [neon] types: - - [f64, float64x1x4_t, float64x1_t] + - [f64, float64x1x4_t] compose: - - LLVMLink: - name: 'st4.{neon_type[1].nox}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'c: {type[2]}' - - 'd: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st4.v{neon_type[1].lane}{type[0]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst4{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'a as _']] + - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]] - name: "vst4{neon_type[1].lane_nox}" doc: "Store multiple 4-element structures from four registers" @@ -5069,21 +4811,10 @@ intrinsics: safety: unsafe: [neon] types: - - [i64, int64x2x4_t, int64x2_t] - - [f64, float64x2x4_t, float64x2_t] + - [i64, int64x2x4_t, "2"] + - [f64, float64x2x4_t, "2"] compose: - - LLVMLink: - name: 'st4.{neon_type[1].nox}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'c: {type[2]}' - - 'd: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st4.v{neon_type[1].lane}{type[0]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst4{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'a as _']] + - FnCall: ["crate::core_arch::macros::interleaving_store!", [{ Type: "{type[0]}" }, "{type[2]}", "4", a, b], [], true] - name: "vst4{neon_type[1].nox}" doc: "Store multiple 4-element structures from four registers" @@ -5215,45 +4946,35 @@ intrinsics: - name: "vmull_high{neon_type[0].noq}" doc: Signed multiply long arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[3]}" - attr: [*neon-stable] - assert_instr: [smull2] + return_type: "{neon_type[1]}" + attr: + - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smull2]]}]] safety: safe types: - - [int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', int16x8_t] - - [int16x8_t, int16x4_t, '[4, 5, 6, 7]', int32x4_t] - - [int32x4_t, int32x2_t, '[2, 3]', int64x2_t] + - [int8x16_t, int16x8_t] + - [int16x8_t, int32x4_t] + - [int32x4_t, int64x2_t] compose: - - Let: - - a - - "{neon_type[1]}" - - FnCall: [simd_shuffle!, [a, a, "{type[2]}"]] - - Let: - - b - - "{neon_type[1]}" - - FnCall: [simd_shuffle!, [b, b, "{type[2]}"]] + - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}] + - Let: [b, {FnCall: ['vget_high_{neon_type[0]}', [b]]}] - FnCall: ["vmull_{neon_type[0]}", [a, b]] - name: "vmull_high{neon_type[0].noq}" doc: "Unsigned multiply long" arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[3]}" - attr: [*neon-stable] - assert_instr: [umull2] + return_type: "{neon_type[1]}" + attr: + - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umull2]]}]] safety: safe types: - - [uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', uint16x8_t] - - [uint16x8_t, uint16x4_t, '[4, 5, 6, 7]', uint32x4_t] - - [uint32x4_t, uint32x2_t, '[2, 3]', uint64x2_t] + - [uint8x16_t, uint16x8_t] + - [uint16x8_t, uint32x4_t] + - [uint32x4_t, uint64x2_t] compose: - - Let: - - a - - "{neon_type[1]}" - - FnCall: [simd_shuffle!, [a, a, "{type[2]}"]] - - Let: - - b - - "{neon_type[1]}" - - FnCall: [simd_shuffle!, [b, b, "{type[2]}"]] + - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}] + - Let: [b, {FnCall: ['vget_high_{neon_type[0]}', [b]]}] - FnCall: ["vmull_{neon_type[0]}", [a, b]] - name: "vmull_p64" @@ -5279,22 +5000,16 @@ intrinsics: - name: "vmull_high{neon_type[0].noq}" doc: "Polynomial multiply long" arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[3]}" + return_type: "{neon_type[1]}" attr: - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [pmull2]]}]] safety: safe - assert_instr: [pmull2] types: - - [poly8x16_t, poly8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', poly16x8_t] + - [poly8x16_t, poly16x8_t] compose: - - Let: - - a - - "{neon_type[1]}" - - FnCall: [simd_shuffle!, [a, a, "{type[2]}"]] - - Let: - - b - - "{neon_type[1]}" - - FnCall: [simd_shuffle!, [b, b, "{type[2]}"]] + - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}] + - Let: [b, {FnCall: ['vget_high_{neon_type[0]}', [b]]}] - FnCall: ["vmull_{neon_type[0]}", [a, b]] - name: "vmull_high{neon_type[0].noq}" @@ -5304,15 +5019,15 @@ intrinsics: attr: - *neon-aes - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [pmull2]]}]] safety: safe - assert_instr: [pmull2] types: - [poly64x2_t, "p128"] compose: - FnCall: - "vmull_{neon_type[0]}" - - - FnCall: [simd_extract!, [a, '1']] - - FnCall: [simd_extract!, [b, '1']] + - - FnCall: ['vget{neon_type[0].lane_nox}', [a], [1]] + - FnCall: ['vget{neon_type[0].lane_nox}', [b], [1]] - name: "vmulx{neon_type.no}" doc: Floating-point multiply extended @@ -5411,11 +5126,8 @@ intrinsics: - vmulx_f64 - - a - FnCall: - - 'transmute::' - - - FnCall: - - "simd_extract!" - - - b - - 'LANE as u32' + - 'transmute' + - - FnCall: ['vget{neon_type.lane_nox}', [b], [LANE]] - name: "vmulx{type[0]}" doc: Floating-point multiply extended @@ -5428,17 +5140,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - ["q_lane_f64", float64x2_t, float64x1_t, "q_f64", '[LANE as u32, LANE as u32]'] + - ["q_lane_f64", float64x2_t, float64x1_t, "q_f64", '[LANE as u32; 2]'] compose: - FnCall: [static_assert!, ['LANE == 0']] - FnCall: - "vmulx{type[3]}" - - a - - FnCall: - - "simd_shuffle!" - - - b - - b - - "{type[4]}" + - FnCall: ['vdup{type[0]}', [b], [LANE]] - name: "vmulx{type[0]}" doc: Floating-point multiply extended @@ -5451,16 +5159,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - ["d_lane_f64", "f64", float64x1_t, "d_f64", 'LANE as u32'] + - ["d_lane_f64", "f64", float64x1_t, "d_f64"] compose: - FnCall: [static_assert!, ['LANE == 0']] - FnCall: - "vmulx{type[3]}" - - a - - FnCall: - - "simd_extract!" - - - b - - "{type[4]}" + - FnCall: ['vget{neon_type[2].lane_nox}', [b], [LANE]] - name: "vmulx_laneq_f64" doc: Floating-point multiply extended @@ -5480,11 +5185,8 @@ intrinsics: - vmulx_f64 - - a - FnCall: - - 'transmute::' - - - FnCall: - - "simd_extract!" - - - b - - 'LANE as u32' + - 'transmute' + - - FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]] - name: "vmulx{type[0]}" doc: Floating-point multiply extended @@ -5497,21 +5199,17 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - ['_lane_f32', float32x2_t, float32x2_t, '1', '_f32', '[LANE as u32, LANE as u32]'] - - ['_laneq_f32', float32x2_t, float32x4_t, '2', '_f32', '[LANE as u32, LANE as u32]'] - - ['q_lane_f32', float32x4_t, float32x2_t, '1', 'q_f32', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - ['q_laneq_f32', float32x4_t, float32x4_t, '2', 'q_f32', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - ['q_laneq_f64', float64x2_t, float64x2_t, '1', 'q_f64', '[LANE as u32, LANE as u32]'] + - ['_lane_f32', float32x2_t, float32x2_t, '1', '_f32'] + - ['_laneq_f32', float32x2_t, float32x4_t, '2', '_f32'] + - ['q_lane_f32', float32x4_t, float32x2_t, '1', 'q_f32'] + - ['q_laneq_f32', float32x4_t, float32x4_t, '2', 'q_f32'] + - ['q_laneq_f64', float64x2_t, float64x2_t, '1', 'q_f64'] compose: - FnCall: [static_assert_uimm_bits!, ['LANE', "{type[3]}"]] - FnCall: - "vmulx{type[4]}" - - a - - FnCall: - - "simd_shuffle!" - - - b - - b - - "{type[5]}" + - FnCall: ['vdup{type[0]}', [b], [LANE]] - name: "vmulx{type[0]}" @@ -5527,20 +5225,16 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - ['_lane_f16', float16x4_t, float16x4_t, '2', '_f16', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - ['_laneq_f16', float16x4_t, float16x8_t, '3', '_f16', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - ['q_lane_f16', float16x8_t, float16x4_t, '2', 'q_f16', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - ['q_laneq_f16', float16x8_t, float16x8_t, '3', 'q_f16', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - ['_lane_f16', float16x4_t, float16x4_t, '2', '_f16'] + - ['_laneq_f16', float16x4_t, float16x8_t, '3', '_f16'] + - ['q_lane_f16', float16x8_t, float16x4_t, '2', 'q_f16'] + - ['q_laneq_f16', float16x8_t, float16x8_t, '3', 'q_f16'] compose: - FnCall: [static_assert_uimm_bits!, ['LANE', "{type[3]}"]] - FnCall: - "vmulx{type[4]}" - - a - - FnCall: - - "simd_shuffle!" - - - b - - b - - "{type[5]}" + - FnCall: ['vdup{type[0]}', [b], [LANE]] - name: "vmulx{type[0]}" @@ -5554,18 +5248,15 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - ['s_lane_f32', f32, float32x2_t, '1', 's_f32', 'LANE as u32'] - - ['s_laneq_f32', f32, float32x4_t, '2', 's_f32', 'LANE as u32'] - - ['d_laneq_f64', f64, float64x2_t, '1', 'd_f64', 'LANE as u32'] + - ['s_lane_f32', f32, float32x2_t, '1', 's_f32'] + - ['s_laneq_f32', f32, float32x4_t, '2', 's_f32'] + - ['d_laneq_f64', f64, float64x2_t, '1', 'd_f64'] compose: - FnCall: [static_assert_uimm_bits!, ['LANE', "{type[3]}"]] - FnCall: - "vmulx{type[4]}" - - a - - FnCall: - - "simd_extract!" - - - b - - "{type[5]}" + - FnCall: ['vget{neon_type[2].lane_nox}', [b], [LANE]] - name: "vmulx{type[0]}" @@ -5588,10 +5279,7 @@ intrinsics: - FnCall: - "vmulx{type[4]}" - - a - - FnCall: - - "simd_extract!" - - - b - - "{type[5]}" + - FnCall: ['vget{neon_type[2].lane_nox}', [b], [LANE]] - name: "vmulx{neon_type[0].N}" @@ -5885,18 +5573,18 @@ intrinsics: doc: Signed Subtract Wide arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[0]}" - attr: [*neon-stable] - assert_instr: [ssubw2] + attr: + - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [ssubw2]]}]] safety: safe types: - - [int16x8_t, int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [int32x4_t, int16x8_t, int16x4_t, '[4, 5, 6, 7]'] - - [int64x2_t, int32x4_t, int32x2_t, '[2, 3]'] + - [int16x8_t, int8x16_t] + - [int32x4_t, int16x8_t] + - [int64x2_t, int32x4_t] compose: - Let: - c - - "{neon_type[2]}" - - FnCall: [simd_shuffle!, [b, b, "{type[3]}"]] + - FnCall: ['vget_high_{neon_type[1]}', [b]] - FnCall: - simd_sub - - a @@ -5906,18 +5594,18 @@ intrinsics: doc: Unsigned Subtract Wide arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[0]}" - attr: [*neon-stable] - assert_instr: [usubw2] + attr: + - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [usubw2]]}]] safety: safe types: - - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint32x4_t, uint16x8_t, uint16x4_t, '[4, 5, 6, 7]'] - - [uint64x2_t, uint32x4_t, uint32x2_t, '[2, 3]'] + - [uint16x8_t, uint8x16_t] + - [uint32x4_t, uint16x8_t] + - [uint64x2_t, uint32x4_t] compose: - Let: - c - - "{neon_type[2]}" - - FnCall: [simd_shuffle!, [b, b, "{type[3]}"]] + - FnCall: ['vget_high_{neon_type[1]}', [b]] - FnCall: - simd_sub - - a @@ -5927,61 +5615,47 @@ intrinsics: doc: "Signed Subtract Long" arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] return_type: "{neon_type[1]}" - attr: [*neon-stable] - assert_instr: [ssubl2] + attr: + - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [ssubl2]]}]] safety: safe types: - - [int8x16_t, int16x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', int8x8_t] - - [int16x8_t, int32x4_t, '[4, 5, 6, 7]', int16x4_t] - - [int32x4_t, int64x2_t, '[2, 3]', int32x2_t] + - [int8x16_t, int16x8_t] + - [int32x4_t, int64x2_t] + - [int16x8_t, int32x4_t] compose: - Let: - c - - "{neon_type[3]}" - - FnCall: [simd_shuffle!, [a, a, "{type[2]}"]] - - Let: - - d - "{neon_type[1]}" - - FnCall: [simd_cast, [c]] - - Let: - - e - - "{neon_type[3]}" - - FnCall: [simd_shuffle!, [b, b, "{type[2]}"]] + - FnCall: [simd_cast, [{FnCall: ['vget_high_{neon_type[0]}', [a]]}]] - Let: - - f + - d - "{neon_type[1]}" - - FnCall: [simd_cast, [e]] - - FnCall: [simd_sub, [d, f]] + - FnCall: [simd_cast, [{FnCall: ['vget_high_{neon_type[0]}', [b]]}]] + - FnCall: [simd_sub, [c, d]] - name: "vsubl_high{neon_type[0].noq}" doc: "Unsigned Subtract Long" arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] return_type: "{neon_type[1]}" - attr: [*neon-stable] - assert_instr: [usubl2] + attr: + - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [usubl2]]}]] safety: safe types: - - [uint8x16_t, uint16x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', uint8x8_t] - - [uint16x8_t, uint32x4_t, '[4, 5, 6, 7]', uint16x4_t] - - [uint32x4_t, uint64x2_t, '[2, 3]', uint32x2_t] + - [uint8x16_t, uint16x8_t] + - [uint16x8_t, uint32x4_t] + - [uint32x4_t, uint64x2_t] compose: - Let: - c - - "{neon_type[3]}" - - FnCall: [simd_shuffle!, [a, a, "{type[2]}"]] - - Let: - - d - "{neon_type[1]}" - - FnCall: [simd_cast, [c]] - - Let: - - e - - "{neon_type[3]}" - - FnCall: [simd_shuffle!, [b, b, "{type[2]}"]] + - FnCall: [simd_cast, [{FnCall: ['vget_high_{neon_type[0]}', [a]]}]] - Let: - - f + - d - "{neon_type[1]}" - - FnCall: [simd_cast, [e]] - - FnCall: [simd_sub, [d, f]] + - FnCall: [simd_cast, [{FnCall: ['vget_high_{neon_type[0]}', [b]]}]] + - FnCall: [simd_sub, [c, d]] - name: "vbcax{neon_type.no}" doc: Bit clear and exclusive OR @@ -6034,6 +5708,7 @@ intrinsics: - *neon-unstable-fcma assert_instr: [fcadd] safety: safe + big_endian_inverse: true types: - float32x2_t - float32x4_t @@ -6054,6 +5729,7 @@ intrinsics: - *neon-unstable-fcma assert_instr: [fcadd] safety: safe + big_endian_inverse: true types: - float32x2_t - float32x4_t @@ -6076,6 +5752,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fcadd] safety: safe + big_endian_inverse: true types: - float16x4_t - float16x8_t @@ -6097,6 +5774,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fcadd] safety: safe + big_endian_inverse: true types: - float16x4_t - float16x8_t @@ -6116,6 +5794,7 @@ intrinsics: - *neon-unstable-fcma assert_instr: [fcmla] safety: safe + big_endian_inverse: true types: - float32x2_t - float32x4_t @@ -6138,6 +5817,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fcmla] safety: safe + big_endian_inverse: true types: - float16x4_t - float16x8_t @@ -6157,6 +5837,7 @@ intrinsics: - *neon-unstable-fcma assert_instr: [fcmla] safety: safe + big_endian_inverse: true types: - float32x2_t - float32x4_t @@ -6179,6 +5860,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fcmla] safety: safe + big_endian_inverse: true types: - float16x4_t - float16x8_t @@ -6198,6 +5880,7 @@ intrinsics: - *neon-unstable-fcma assert_instr: [fcmla] safety: safe + big_endian_inverse: true types: - float32x2_t - float32x4_t @@ -6221,6 +5904,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fcmla] safety: safe + big_endian_inverse: true types: - float16x4_t - float16x8_t @@ -6243,14 +5927,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float32x2_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float32x4_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float32x2_t, float32x4_t, ''] + - [float32x4_t, float32x4_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 1]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpretq_u64_f32, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u64', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}] - FnCall: ["vcmla{neon_type[0].no}", [a, b, c]] - name: "vcmla{neon_type[0].laneq_nox}" @@ -6267,14 +5950,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float16x4_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float16x8_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float16x4_t, float16x8_t, ''] + - [float16x8_t, float16x8_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 2]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpretq_u32_f16, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u32', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}] - FnCall: ["vcmla{neon_type[0].no}", [a, b, c]] - name: "vcmla{neon_type[0].rot90_laneq}" @@ -6289,14 +5971,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float32x2_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float32x4_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float32x2_t, float32x4_t, ''] + - [float32x4_t, float32x4_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 1]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpretq_u64_f32, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u64', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}] - FnCall: ["vcmla{neon_type[0].rot90}", [a, b, c]] - name: "vcmla{neon_type[0].rot90_laneq}" @@ -6313,14 +5994,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float16x4_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float16x8_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float16x4_t, float16x8_t, ''] + - [float16x8_t, float16x8_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 2]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpretq_u32_f16, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u32', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}] - FnCall: ["vcmla{neon_type[0].rot90}", [a, b, c]] - name: "vcmla{neon_type[0].rot90_lane}" @@ -6335,14 +6015,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float32x2_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float32x4_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float32x2_t, float32x2_t, ''] + - [float32x4_t, float32x2_t, 'q'] compose: - FnCall: [static_assert!, ['LANE == 0']] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpret_u64_f32, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_lane_u64', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}] - FnCall: ["vcmla{neon_type[0].rot90}", [a, b, c]] - name: "vcmla{neon_type[0].rot90_lane}" @@ -6359,14 +6038,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float16x4_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float16x8_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float16x4_t, float16x4_t, ''] + - [float16x8_t, float16x4_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 1]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpret_u32_f16, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_lane_u32', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}] - FnCall: ["vcmla{neon_type[0].rot90}", [a, b, c]] - name: "vcmla{neon_type.rot180}" @@ -6378,6 +6056,7 @@ intrinsics: - *neon-unstable-fcma assert_instr: [fcmla] safety: safe + big_endian_inverse: true types: - float32x2_t - float32x4_t @@ -6401,6 +6080,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fcmla] safety: safe + big_endian_inverse: true types: - float16x4_t - float16x8_t @@ -6424,14 +6104,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float32x2_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float32x4_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float32x2_t, float32x4_t, ''] + - [float32x4_t, float32x4_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 1]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpretq_u64_f32, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u64', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}] - FnCall: ["vcmla{neon_type[0].rot180}", [a, b, c]] - name: "vcmla{neon_type[0].rot180_laneq}" @@ -6448,19 +6127,16 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float16x4_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float16x8_t, float16x8_t, - '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]' - ] + - [float16x4_t, float16x8_t, ''] + - [float16x8_t, float16x8_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 2]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpretq_u32_f16, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u32', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}] - FnCall: ["vcmla{neon_type[0].rot180}", [a, b, c]] - - name: "vcmla{type[3]}" + - name: "vcmla{neon_type[0].rot180_lane}" doc: Floating-point complex multiply accumulate arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] return_type: "{neon_type[0]}" @@ -6472,17 +6148,16 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float32x2_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]', '_rot180_lane_f32'] - - [float32x4_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]', 'q_rot180_lane_f32'] + - [float32x2_t, float32x2_t, ''] + - [float32x4_t, float32x2_t, 'q'] compose: - FnCall: [static_assert!, ['LANE == 0']] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpret_u64_f32, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_lane_u64', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}] - FnCall: ["vcmla{neon_type[0].rot180}", [a, b, c]] - - name: "vcmla{type[3]}" + - name: "vcmla{neon_type[0].rot180_lane}" doc: Floating-point complex multiply accumulate arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] return_type: "{neon_type[0]}" @@ -6496,16 +6171,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float16x4_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]', '_rot180_lane_f16'] - - [float16x8_t, float16x4_t, - '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]', 'q_rot180_lane_f16' - ] + - [float16x4_t, float16x4_t, ''] + - [float16x8_t, float16x4_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 1]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpret_u32_f16, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_lane_u32', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}] - FnCall: ["vcmla{neon_type[0].rot180}", [a, b, c]] - name: "vcmla{neon_type[0].rot270_laneq}" @@ -6520,14 +6192,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float32x2_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float32x4_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float32x2_t, float32x4_t, ''] + - [float32x4_t, float32x4_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 1]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpretq_u64_f32, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u64', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}] - FnCall: ["vcmla{neon_type[0].rot270}", [a, b, c]] - name: "vcmla{neon_type[0].rot270_laneq}" @@ -6544,14 +6215,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float16x4_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float16x8_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float16x4_t, float16x8_t, ''] + - [float16x8_t, float16x8_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 2]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpretq_u32_f16, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u32', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}] - FnCall: ["vcmla{neon_type[0].rot270}", [a, b, c]] - name: "vcmla{neon_type[0].lane_nox}" @@ -6566,14 +6236,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float32x2_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float32x4_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float32x2_t, float32x2_t, ''] + - [float32x4_t, float32x2_t, 'q'] compose: - FnCall: [static_assert!, ['LANE == 0']] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpret_u64_f32, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_lane_u64', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}] - FnCall: ["vcmla{neon_type[0].no}", [a, b, c]] @@ -6591,14 +6260,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float16x4_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float16x8_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float16x4_t, float16x4_t, ''] + - [float16x8_t, float16x4_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 1]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpret_u32_f16, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_lane_u32', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}] - FnCall: ["vcmla{neon_type[0].no}", [a, b, c]] - name: "vcmla{neon_type[0].rot270_lane}" @@ -6613,11 +6281,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float32x2_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float32x4_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float32x2_t, float32x2_t, ''] + - [float32x4_t, float32x2_t, 'q'] compose: - FnCall: [static_assert!, ['LANE == 0']] - - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]}] + - Let: [c, {FnCall: [vreinterpret_u64_f32, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_lane_u64', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}] - FnCall: ["vcmla{neon_type[0].rot270}", [a, b, c]] - name: "vcmla{neon_type[0].rot270_lane}" @@ -6634,11 +6304,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float16x4_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float16x8_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float16x4_t, float16x4_t, ''] + - [float16x8_t, float16x4_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 1]] - - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]}] + - Let: [c, {FnCall: [vreinterpret_u32_f16, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_lane_u32', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}] - FnCall: ["vcmla{neon_type[0].rot270}", [a, b, c]] - name: "vmax{neon_type.no}" @@ -6679,6 +6351,7 @@ intrinsics: arch: aarch64,arm64ec + - name: "vmaxnm{neon_type.no}" doc: Floating-point Maximum Number (vector) arguments: ["a: {neon_type}", "b: {neon_type}"] @@ -6690,7 +6363,11 @@ intrinsics: - float64x1_t - float64x2_t compose: - - FnCall: [simd_fmax, [a, b]] + - LLVMLink: + name: "fmaxnm.{neon_type}" + links: + - link: "llvm.aarch64.neon.fmaxnm.{neon_type}" + arch: aarch64,arm64ec - name: "vmaxnmh_{type}" @@ -6706,7 +6383,11 @@ intrinsics: types: - f16 compose: - - FnCall: ["f16::max", [a, b]] + - LLVMLink: + name: "vmaxh.{neon_type}" + links: + - link: "llvm.aarch64.neon.fmaxnm.{type}" + arch: aarch64,arm64ec - name: "vminnmh_{type}" @@ -6722,7 +6403,11 @@ intrinsics: types: - f16 compose: - - FnCall: ["f16::min", [a, b]] + - LLVMLink: + name: "vminh.{neon_type}" + links: + - link: "llvm.aarch64.neon.fminnm.{type}" + arch: aarch64,arm64ec - name: "vmaxnmv{neon_type[0].no}" @@ -6736,7 +6421,11 @@ intrinsics: - [float32x2_t, f32] - [float64x2_t, f64] compose: - - FnCall: [simd_reduce_max, [a]] + - LLVMLink: + name: "fmaxnmv.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.fmaxnmv.{type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec - name: "vmaxnmv{neon_type[0].no}" doc: Floating-point maximum number across vector @@ -6748,7 +6437,11 @@ intrinsics: types: - [float32x4_t, f32] compose: - - FnCall: [simd_reduce_max, [a]] + - LLVMLink: + name: "fmaxnmv.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.fmaxnmv.{type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec - name: "vmaxnmv{neon_type[0].no}" @@ -6765,7 +6458,11 @@ intrinsics: - [float16x4_t, f16] - [float16x8_t, f16] compose: - - FnCall: [simd_reduce_max, [a]] + - LLVMLink: + name: "fmaxnmv.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.fmaxnmv.{type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec - name: "vminnmv{neon_type[0].no}" @@ -6782,7 +6479,11 @@ intrinsics: - [float16x4_t, f16] - [float16x8_t, f16] compose: - - FnCall: [simd_reduce_min, [a]] + - LLVMLink: + name: "fminnmv.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.fminnmv.{type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec - name: "vmaxv{neon_type[0].no}" @@ -6891,7 +6592,11 @@ intrinsics: - float64x1_t - float64x2_t compose: - - FnCall: [simd_fmin, [a, b]] + - LLVMLink: + name: "fminnm.{neon_type}" + links: + - link: "llvm.aarch64.neon.fminnm.{neon_type}" + arch: aarch64,arm64ec - name: "vminnmv{neon_type[0].no}" doc: "Floating-point minimum number across vector" @@ -6899,13 +6604,17 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fminnmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, "f32"] - [float64x2_t, "f64"] compose: - - FnCall: [simd_reduce_min, [a]] + - LLVMLink: + name: "vminnmv.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.fminnmv.{type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec - name: "vminnmv{neon_type[0].no}" doc: "Floating-point minimum number across vector" @@ -6913,86 +6622,94 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fminnmv]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x4_t, "f32"] compose: - - FnCall: [simd_reduce_min, [a]] + - LLVMLink: + name: "vminnmv.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.fminnmv.{type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec - name: "vmovl_high{neon_type[0].noq}" doc: Vector move arguments: ["a: {neon_type[0]}"] return_type: "{neon_type[1]}" - attr: [*neon-stable] - assert_instr: [sxtl2] + attr: + - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sxtl2]]}]] safety: safe types: - - [int8x16_t, int16x8_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [int16x8_t, int32x4_t, int16x4_t, '[4, 5, 6, 7]'] - - [int32x4_t, int64x2_t, int32x2_t, '[2, 3]'] + - [int8x16_t, int16x8_t] + - [int16x8_t, int32x4_t] + - [int32x4_t, int64x2_t] compose: - Let: - a - - "{neon_type[2]}" - - FnCall: [simd_shuffle!, [a, a, "{type[3]}"]] + - FnCall: ['vget_high_{neon_type[0]}', [a]] - FnCall: ["vmovl{neon_type[0].noq}", [a]] - name: "vmovl_high{neon_type[0].noq}" doc: Vector move arguments: ["a: {neon_type[0]}"] return_type: "{neon_type[1]}" - attr: [*neon-stable] - assert_instr: [uxtl2] + attr: + - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uxtl2]]}]] safety: safe types: - - [uint8x16_t, uint16x8_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x8_t, uint32x4_t, uint16x4_t, '[4, 5, 6, 7]'] - - [uint32x4_t, uint64x2_t, uint32x2_t, '[2, 3]'] + - [uint8x16_t, uint16x8_t] + - [uint16x8_t, uint32x4_t] + - [uint32x4_t, uint64x2_t] compose: - Let: - a - - "{neon_type[2]}" - - FnCall: [simd_shuffle!, [a, a, "{type[3]}"]] + - FnCall: ['vget_high_{neon_type[0]}', [a]] - FnCall: ["vmovl{neon_type[0].noq}", [a]] - - name: "vpadd{neon_type.no}" - doc: Floating-point add pairwise - arguments: ["a: {neon_type}", "b: {neon_type}"] - return_type: "{type}" + - name: "vpadd{neon_type[0].no}" + doc: "Floating-point add pairwise" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" attr: [*neon-stable] assert_instr: [faddp] safety: safe + big_endian_inverse: true types: - - float32x4_t - - float64x2_t + - [float32x4_t, "4"] + - [float64x2_t, "2"] compose: - - LLVMLink: - name: "faddp.{neon_type}" - links: - - link: "llvm.aarch64.neon.faddp.{neon_type}" - arch: aarch64,arm64ec - + - Let: + - even + - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::even::<{type[1]}>()"]] + - Let: + - odd + - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::odd::<{type[1]}>()"]] + - FnCall: [simd_add, [even, odd]] - - name: "vpadd{neon_type.no}" + - name: "vpadd{neon_type[0].no}" doc: Floating-point add pairwise - arguments: ["a: {neon_type}", "b: {neon_type}"] - return_type: "{type}" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" attr: - *neon-fp16 - *neon-stable-fp16 - *target-not-arm64ec assert_instr: [faddp] safety: safe + big_endian_inverse: true types: - - float16x8_t + - [float16x8_t, "8"] compose: - - LLVMLink: - name: "faddp.{neon_type}" - links: - - link: "llvm.aarch64.neon.faddp.{neon_type}" - arch: aarch64,arm64ec - + - Let: + - even + - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::even::<{type[1]}>()"]] + - Let: + - odd + - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::odd::<{type[1]}>()"]] + - FnCall: [simd_add, [even, odd]] - name: "vpmax{neon_type.no}" doc: Floating-point add pairwise @@ -7004,6 +6721,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fmaxp] safety: safe + big_endian_inverse: true types: - float16x4_t - float16x8_t @@ -7025,6 +6743,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fmaxnmp] safety: safe + big_endian_inverse: true types: - float16x4_t - float16x8_t @@ -7046,6 +6765,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fminp] safety: safe + big_endian_inverse: true types: - float16x4_t - float16x8_t @@ -7067,6 +6787,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fminnmp] safety: safe + big_endian_inverse: true types: - float16x4_t - float16x8_t @@ -7092,11 +6813,11 @@ intrinsics: - Let: - a1 - "{type[2]}" - - FnCall: [simd_extract!, [a, '0']] + - FnCall: ['vget{neon_type[1].lane_nox}', [a], [0]] - Let: - a2 - "{type[2]}" - - FnCall: [simd_extract!, [a, '1']] + - FnCall: ['vget{neon_type[1].lane_nox}', [a], [1]] - Identifier: ['a1 + a2', Symbol] - name: "vpmin{type[0]}" @@ -7106,6 +6827,7 @@ intrinsics: attr: [*neon-stable] assert_instr: [fminp] safety: safe + big_endian_inverse: true types: - ["s_f32", float32x2_t, f32] - ["qd_f64", float64x2_t, f64] @@ -7122,14 +6844,14 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i16", "i32"] compose: - Let: [a, int16x4_t, {FnCall: [vdup_n_s16, [a]]}] - Let: [b, int16x4_t, {FnCall: [vdup_n_s16, [b]]}] - - FnCall: [simd_extract!, [{FnCall: [vqdmull_s16, [a, b]]}, '0']] + - FnCall: ['vgetq_lane_{type[1]}', [{FnCall: [vqdmull_s16, [a, b]]}], ['0']] - name: "vqdmulls_s32" doc: "Signed saturating doubling multiply long" @@ -7137,7 +6859,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i32", "i64"] @@ -7153,15 +6875,15 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] return_type: "{neon_type[1]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmull2]]}]] + - *neon-stable safety: safe types: - - [int16x8_t, int32x4_t, int16x4_t, '[4, 5, 6, 7]'] - - [int32x4_t, int64x2_t, int32x2_t, '[2, 3]'] + - [int16x8_t, int32x4_t] + - [int32x4_t, int64x2_t] compose: - - Let: [a, "{neon_type[2]}", {FnCall: [simd_shuffle!, [a, a, '{type[3]}']]}] - - Let: [b, "{neon_type[2]}", {FnCall: [simd_shuffle!, [b, b, '{type[3]}']]}] + - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}] + - Let: [b, {FnCall: ['vget_high_{neon_type[0]}', [b]]}] - FnCall: ["vqdmull{neon_type[0].noq}", [a, b]] - name: "vqdmull_high_n_{type[1]}" @@ -7169,15 +6891,15 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmull2]]}]] + - *neon-stable safety: safe types: - - [int16x8_t, "i16", int32x4_t, int16x4_t, '[4, 5, 6, 7]'] - - [int32x4_t, "i32", int64x2_t, int32x2_t, '[2, 3]'] + - [int16x8_t, "i16", int32x4_t] + - [int32x4_t, "i32", int64x2_t] compose: - - Let: [a, "{neon_type[3]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}] - - Let: [b, "{neon_type[3]}", {FnCall: ["vdup_n{neon_type[0].noq}", [b]]}] + - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}] + - Let: [b, {FnCall: ["vdup_n{neon_type[0].noq}", [b]]}] - FnCall: ["vqdmull{neon_type[0].noq}", [a, b]] - name: "vqdmull{type[3]}" @@ -7187,7 +6909,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -7195,7 +6917,7 @@ intrinsics: - ["i32", int32x4_t, "i64", 's_laneq_s32', 's_s32'] compose: - FnCall: [static_assert_uimm_bits!, [N, 2]] - - Let: [b, "{type[0]}", {FnCall: [simd_extract!, [b, 'N as u32']]}] + - Let: [b, "{type[0]}", {FnCall: ['vget{neon_type[1].lane_nox}', [b], [N]]}] - FnCall: ["vqdmull{type[4]}", [a, b]] - name: "vqdmullh_laneq_s16" @@ -7205,14 +6927,14 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull, N = 4]]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - ["i16", int16x8_t, "i32"] compose: - FnCall: [static_assert_uimm_bits!, [N, 3]] - - Let: [b, "{type[0]}", {FnCall: [simd_extract!, [b, 'N as u32']]}] + - Let: [b, "{type[0]}", {FnCall: ['vget{neon_type[1].lane_nox}', [b], [N]]}] - FnCall: ["vqdmullh_s16", [a, b]] - name: "vqdmulls_lane_s32" @@ -7222,33 +6944,33 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - ["i32", int32x2_t, "i64"] compose: - FnCall: [static_assert_uimm_bits!, [N, 1]] - - Let: [b, "{type[0]}", {FnCall: [simd_extract!, [b, 'N as u32']]}] + - Let: [b, "{type[0]}", {FnCall: ['vget{neon_type[1].lane_nox}', [b], [N]]}] - FnCall: ["vqdmulls_s32", [a, b]] - - name: "vqdmull{type[6]}" + - name: "vqdmull{type[3]}" doc: "Signed saturating doubling multiply long" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmull2, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [int16x8_t, int16x4_t, int32x4_t, int16x4_t, '[4, 5, 6, 7]', '[N as u32, N as u32, N as u32, N as u32]', '_high_lane_s16'] - - [int32x4_t, int32x4_t, int64x2_t, int32x2_t, '[2, 3]', '[N as u32, N as u32]', '_high_laneq_s32'] + - [int16x8_t, int16x4_t, int32x4_t, '_high_lane_s16'] + - [int32x4_t, int32x4_t, int64x2_t, '_high_laneq_s32'] compose: - FnCall: [static_assert_uimm_bits!, [N, '2']] - - Let: [a, "{neon_type[3]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}] - - Let: [b, "{neon_type[3]}", {FnCall: [simd_shuffle!, [b, b, "{type[5]}"]]}] + - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}] + - Let: [b, {FnCall: ['vdup_lane{neon_type[1].nox}', [b], [N]]}] - FnCall: ["vqdmull{neon_type[0].noq}", [a, b]] - name: "vqdmull_high_lane_s32" @@ -7256,17 +6978,17 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2, 'N = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmull2, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [int32x4_t, int32x2_t, int64x2_t, int32x2_t, '[2, 3]', '[N as u32, N as u32]'] + - [int32x4_t, int32x2_t, int64x2_t] compose: - FnCall: [static_assert_uimm_bits!, [N, '1']] - - Let: [a, "{neon_type[3]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}] - - Let: [b, "{neon_type[3]}", {FnCall: [simd_shuffle!, [b, b, "{type[5]}"]]}] + - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}] + - Let: [b, {FnCall: ['vdup_lane{neon_type[1].nox}', [b], [N]]}] - FnCall: ["vqdmull{neon_type[0].noq}", [a, b]] - name: "vqdmull_high_laneq_s16" @@ -7274,17 +6996,17 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2, N = 4]]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmull2, N = 4]]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [int16x8_t, int16x8_t, int32x4_t, int16x4_t, '[4, 5, 6, 7]', '[N as u32, N as u32, N as u32, N as u32]'] + - [int16x8_t, int16x8_t, int32x4_t] compose: - FnCall: [static_assert_uimm_bits!, [N, '3']] - - Let: [a, "{neon_type[3]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}] - - Let: [b, "{neon_type[3]}", {FnCall: [simd_shuffle!, [b, b, "{type[5]}"]]}] + - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}] + - Let: [b, {FnCall: ['vdup_lane{neon_type[1].nox}', [b], [N]]}] - FnCall: ["vqdmull{neon_type[0].noq}", [a, b]] - name: "vqdmull_laneq_s16" @@ -7294,14 +7016,14 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull, 'N = 4']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [int16x4_t, int16x8_t, int32x4_t, '[N as u32, N as u32, N as u32, N as u32]'] + - [int16x4_t, int16x8_t, int32x4_t] compose: - FnCall: [static_assert_uimm_bits!, [N, '3']] - - Let: [b, "{neon_type[0]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}] + - Let: [b, {FnCall: ['vdup_lane{neon_type[1].nox}', [b], [N]]}] - FnCall: [vqdmull_s16, [a, b]] - name: "vqdmull_laneq_s32" @@ -7311,14 +7033,14 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [int32x2_t, int32x4_t, int64x2_t, '[N as u32, N as u32]'] + - [int32x2_t, int32x4_t, int64x2_t] compose: - FnCall: [static_assert_uimm_bits!, [N, '2']] - - Let: [b, "{neon_type[0]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}] + - Let: [b, {FnCall: ['vdup_lane{neon_type[1].nox}', [b], [N]]}] - FnCall: [vqdmull_s32, [a, b]] - name: "vqdmlal{type[4]}" @@ -7326,8 +7048,8 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal2]]}]] + - *neon-stable safety: safe types: - [int32x4_t, int16x8_t, int16x8_t, int32x4_t, _high_s16] @@ -7342,9 +7064,9 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal2, 'N = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal2, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -7361,14 +7083,14 @@ intrinsics: arguments: ["a: {type[0]}", "b: {type[1]}", "c: {type[1]}"] return_type: "{type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal]]}]] + - *neon-stable safety: safe types: - ["i32", "i16", "s16"] compose: - Let: [x, int32x4_t, {FnCall: [vqdmull_s16, [{FnCall: [vdup_n_s16, [b]]}, {FnCall: [vdup_n_s16, [c]]}]]}] - - FnCall: [vqadds_s32, [a, {FnCall: [simd_extract!, [x, 0]]}]] + - FnCall: [vqadds_s32, [a, {FnCall: ['vgetq_lane_s32', [x], [0]]}]] - name: "vqdmlals_s32" doc: "Signed saturating doubling multiply-add long" @@ -7376,7 +7098,7 @@ intrinsics: return_type: "{type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i64", "i32", "i32", "i64"] @@ -7389,9 +7111,9 @@ intrinsics: arguments: ["a: {type[0]}", "b: {type[1]}", "c: {neon_type[2]}"] return_type: "{type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -7401,16 +7123,16 @@ intrinsics: - ["i64", "i32", int32x4_t, "i64", s_laneq_s32, '2', s_s32] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[5]}"]] - - FnCall: ["vqdmlal{type[6]}", [a, b, {FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + - FnCall: ["vqdmlal{type[6]}", [a, b, {FnCall: ['vget{neon_type[2].lane_nox}', [c], [LANE]]}]] - name: "vqdmlal_laneq_s16" doc: "Vector widening saturating doubling multiply accumulate with scalar" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -7424,9 +7146,9 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal, 'N = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -7440,8 +7162,8 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl2]]}]] + - *neon-stable safety: safe types: - [int32x4_t, int16x8_t, int16x8_t, int32x4_t, _high_s16] @@ -7456,9 +7178,9 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl2, 'N = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl2, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -7475,14 +7197,14 @@ intrinsics: arguments: ["a: {type[0]}", "b: {type[1]}", "c: {type[1]}"] return_type: "{type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl]]}]] + - *neon-stable safety: safe types: - ["i32", "i16"] compose: - Let: [x, int32x4_t, {FnCall: [vqdmull_s16, [{FnCall: [vdup_n_s16, [b]]}, {FnCall: [vdup_n_s16, [c]]}]]}] - - FnCall: [vqsubs_s32, [a, {FnCall: [simd_extract!, [x, '0']]}]] + - FnCall: [vqsubs_s32, [a, {FnCall: ['vgetq_lane_s32', [x], [0]]}]] - name: "vqdmlsls_s32" doc: "Signed saturating doubling multiply-subtract long" @@ -7490,7 +7212,7 @@ intrinsics: return_type: "{type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i64", "i32", "i32", "i64"] @@ -7503,9 +7225,9 @@ intrinsics: arguments: ["a: {type[0]}", "b: {type[1]}", "c: {neon_type[2]}"] return_type: "{type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -7515,16 +7237,16 @@ intrinsics: - ["i64", "i32", int32x4_t, "i64", 's_laneq_s32', '2', 's_s32'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[5]}"]] - - FnCall: ["vqdmlsl{type[6]}", [a, b, {FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + - FnCall: ["vqdmlsl{type[6]}", [a, b, {FnCall: ['vget{neon_type[2].lane_nox}', [c], [LANE]]}]] - name: "vqdmlsl_laneq_s16" doc: "Vector widening saturating doubling multiply subtract with scalar" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -7538,9 +7260,9 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl, 'N = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -7555,7 +7277,7 @@ intrinsics: return_type: "{type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmulh]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i16", "i16", "i16", int16x4_t, 'h_s16'] @@ -7563,7 +7285,7 @@ intrinsics: compose: - Let: [a, "{neon_type[3]}", {FnCall: ["vdup_n{neon_type[3].no}", [a]]}] - Let: [b, "{neon_type[3]}", {FnCall: ["vdup_n{neon_type[3].no}", [b]]}] - - FnCall: [simd_extract!, [{FnCall: ["vqdmulh{neon_type[3].no}", [a, b]]}, '0']] + - FnCall: ['vget{neon_type[3].lane_nox}', [{FnCall: ["vqdmulh{neon_type[3].no}", [a, b]]}], ['0']] - name: "vqdmulhh{type[3]}" doc: "Signed saturating doubling multiply returning high half" @@ -7572,7 +7294,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmulh, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -7580,7 +7302,7 @@ intrinsics: - ["i16", int16x8_t, "i16", '_laneq_s16', '3'] compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[4]}"]] - - Let: [b, 'i16', {FnCall: [simd_extract!, [b, 'N as u32']]}] + - Let: [b, 'i16', {FnCall: ['vget{neon_type[1].lane_nox}', [b], [N]]}] - FnCall: ['vqdmulhh_s16', [a, b]] - name: "vqdmulhs{type[3]}" @@ -7590,7 +7312,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmulh, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -7598,7 +7320,7 @@ intrinsics: - ["i32", int32x4_t, "i32", "_laneq_s32", '2'] compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[4]}"]] - - Let: [b, 'i32', {FnCall: [simd_extract!, [b, 'N as u32']]}] + - Let: [b, 'i32', {FnCall: ['vget{neon_type[1].lane_nox}', [b], [N]]}] - FnCall: ['vqdmulhs_s32', [a, b]] - name: "vqmovn_high{neon_type[1].noq}" @@ -7606,30 +7328,30 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtn2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqxtn2]]}]] + - *neon-stable safety: safe types: - - [int8x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [int16x4_t, int32x4_t, int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [int32x2_t, int64x2_t, int32x4_t, '[0, 1, 2, 3]'] + - [int8x8_t, int16x8_t, int8x16_t] + - [int16x4_t, int32x4_t, int16x8_t] + - [int32x2_t, int64x2_t, int32x4_t] compose: - - FnCall: [simd_shuffle!, [a, {FnCall: ["vqmovn{neon_type[1].noq}", [b]]}, "{type[3]}"]] + - FnCall: ['vcombine_{neon_type[0]}', [a, {FnCall: ["vqmovn{neon_type[1].noq}", [b]]}]] - name: "vqmovn_high{neon_type[1].noq}" doc: "Signed saturating extract narrow" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqxtn2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uqxtn2]]}]] + - *neon-stable safety: safe types: - - [uint8x8_t, uint16x8_t, uint8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, uint32x4_t, uint16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, uint64x2_t, uint32x4_t, '[0, 1, 2, 3]'] + - [uint8x8_t, uint16x8_t, uint8x16_t] + - [uint16x4_t, uint32x4_t, uint16x8_t] + - [uint32x2_t, uint64x2_t, uint32x4_t] compose: - - FnCall: [simd_shuffle!, [a, {FnCall: ["vqmovn{neon_type[1].noq}", [b]]}, "{type[3]}"]] + - FnCall: ['vcombine_{neon_type[0]}', [a, {FnCall: ["vqmovn{neon_type[1].noq}", [b]]}]] - name: "vqmovn{type[2]}" doc: "Saturating extract narrow" @@ -7637,13 +7359,13 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtn]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i16", "i8", 'h_s16', s16] - ["i32", "i16", 's_s32', s32] compose: - - FnCall: [simd_extract!, [{FnCall: ["vqmovn_{type[3]}", [{FnCall: ["vdupq_n_{type[3]}", [a]]}]]}, '0']] + - FnCall: ['vget_lane_{type[1]}', [{FnCall: ["vqmovn_{type[3]}", [{FnCall: ["vdupq_n_{type[3]}", [a]]}]]}], ['0']] - name: "vqmovn{type[2]}" doc: "Saturating extract narrow" @@ -7651,13 +7373,13 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqxtn]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["u16", "u8", 'h_u16', 'u16'] - ["u32", "u16", 's_u32', 'u32'] compose: - - FnCall: [simd_extract!, [{FnCall: ["vqmovn_{type[3]}", [{FnCall: ["vdupq_n_{type[3]}", [a]]}]]}, '0']] + - FnCall: ['vget_lane_{type[1]}', [{FnCall: ["vqmovn_{type[3]}", [{FnCall: ["vdupq_n_{type[3]}", [a]]}]]}], ['0']] - name: "vqmovnd_s64" doc: "Saturating extract narrow" @@ -7665,7 +7387,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtn]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i64", "i32"] @@ -7682,7 +7404,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqxtn]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["u64", "u32"] @@ -7699,29 +7421,29 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtun]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i16", "u8", 'h_s16', s16] - ["i32", "u16", 's_s32', s32] - ["i64", "u32", 'd_s64', s64] compose: - - FnCall: [simd_extract!, [{FnCall: ["vqmovun_{type[3]}", [{FnCall: ["vdupq_n_{type[3]}", [a]]}]]}, '0']] + - FnCall: ['vget_lane_{type[1]}', [{FnCall: ["vqmovun_{type[3]}", [{FnCall: ["vdupq_n_{type[3]}", [a]]}]]}], ['0']] - name: "vqmovun_high_{neon_type[1]}" doc: "Signed saturating extract unsigned narrow" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtun2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqxtun2]]}]] + - *neon-stable safety: safe types: - - [uint8x8_t, int16x8_t, uint8x16_t, s16, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, int32x4_t, uint16x8_t, s32, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, int64x2_t, uint32x4_t, s64, '[0, 1, 2, 3]'] + - [uint8x8_t, int16x8_t, uint8x16_t, s16] + - [uint16x4_t, int32x4_t, uint16x8_t, s32] + - [uint32x2_t, int64x2_t, uint32x4_t, s64] compose: - - FnCall: [simd_shuffle!, [a, {FnCall: ["vqmovun_{type[3]}", [b]]}, "{type[4]}"]] + - FnCall: ['vcombine_{neon_type[0]}', [a, {FnCall: ["vqmovun_{type[3]}", [b]]}]] - name: "vqrdmulh{type[1]}" doc: "Signed saturating rounding doubling multiply returning high half" @@ -7729,13 +7451,13 @@ intrinsics: return_type: "{type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrdmulh]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i16", 'h_s16', 's16'] - ["i32", 's_s32', 's32'] compose: - - FnCall: [simd_extract!, [{FnCall: ["vqrdmulh_{type[2]}", [{FnCall: ["vdup_n_{type[2]}", [a]]}, {FnCall: ["vdup_n_{type[2]}", [b]]}]]}, '0']] + - FnCall: ['vget_lane_{type[2]}', [{FnCall: ["vqrdmulh_{type[2]}", [{FnCall: ["vdup_n_{type[2]}", [a]]}, {FnCall: ["vdup_n_{type[2]}", [b]]}]]}], ['0']] - name: "vqrdmulh{type[2]}" doc: "Signed saturating rounding doubling multiply returning high half" @@ -7744,7 +7466,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrdmulh, LANE = 1]]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -7754,7 +7476,7 @@ intrinsics: - ["i32", int32x4_t, 's_laneq_s32', 's_s32', '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[4]}"]] - - FnCall: ["vqrdmulh{type[3]}", [a, {FnCall: [simd_extract!, [b, 'LANE as u32']]}]] + - FnCall: ["vqrdmulh{type[3]}", [a, {FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]]}]] - name: "vqrdmlah{neon_type.no}" doc: "Signed saturating rounding doubling multiply accumulate returning high half" @@ -7793,7 +7515,7 @@ intrinsics: - Let: [a, "{neon_type[1]}", {FnCall: ["vdup_n_{type[2]}", [a]]}] - Let: [b, "{neon_type[1]}", {FnCall: ["vdup_n_{type[2]}", [b]]}] - Let: [c, "{neon_type[1]}", {FnCall: ["vdup_n_{type[2]}", [c]]}] - - FnCall: [simd_extract!, [{FnCall: ["vqrdmlah_{type[2]}", [a, b, c]]}, '0']] + - FnCall: ['vget_lane_{type[2]}', [{FnCall: ["vqrdmlah_{type[2]}", [a, b, c]]}], ['0']] - name: "vqrdmlah{type[0]}" doc: "Signed saturating rounding doubling multiply accumulate returning high half" @@ -7807,17 +7529,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_lane_s16, int16x8_t, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_s16, int16x8_t, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_lane_s32, int32x2_t, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [_laneq_s32, int32x2_t, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]'] - - [q_lane_s32, int32x4_t, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_s32, int32x4_t, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2'] + - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3'] + - [q_lane_s16, int16x8_t, int16x8_t, int16x4_t, '2'] + - [q_laneq_s16, int16x8_t, int16x8_t, int16x8_t, '3'] + - [_lane_s32, int32x2_t, int32x2_t, int32x2_t, '1'] + - [_laneq_s32, int32x2_t, int32x2_t, int32x4_t, '2'] + - [q_lane_s32, int32x4_t, int32x4_t, int32x2_t, '1'] + - [q_laneq_s32, int32x4_t, int32x4_t, int32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[4]}']] - - Let: [c, "{type[1]}", {FnCall: [simd_shuffle!, [c, c, "{type[5]}"]]}] + - Let: [c, {FnCall: ['vdup{type[0]}', [c], [LANE]]}] - FnCall: ["vqrdmlah{neon_type[2].no}", [a, b, c]] - name: "vqrdmlah{type[4]}" @@ -7838,7 +7560,7 @@ intrinsics: - ["i32", int32x4_t, '2', "s_s32", s_laneq_s32, s_s32] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[2]}"]] - - FnCall: ["vqrdmlah{type[5]}", [a, b, {FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + - FnCall: ["vqrdmlah{type[5]}", [a, b, {FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]] - name: "vqrdmlsh{neon_type.no}" doc: "Signed saturating rounding doubling multiply subtract returning high half" @@ -7877,7 +7599,7 @@ intrinsics: - Let: [a, "{neon_type[2]}", {FnCall: ["vdup_n_{type[3]}", [a]]}] - Let: [b, "{neon_type[2]}", {FnCall: ["vdup_n_{type[3]}", [b]]}] - Let: [c, "{neon_type[2]}", {FnCall: ["vdup_n_{type[3]}", [c]]}] - - FnCall: [simd_extract!, [{FnCall: ["vqrdmlsh_{type[3]}", [a, b, c]]}, '0']] + - FnCall: ['vget{neon_type[2].lane_nox}', [{FnCall: ["vqrdmlsh_{type[3]}", [a, b, c]]}], ['0']] - name: "vqrdmlsh{type[0]}" doc: "Signed saturating rounding doubling multiply subtract returning high half" @@ -7891,17 +7613,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_lane_s16, int16x8_t, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_s16, int16x8_t, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_lane_s32, int32x2_t, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [_laneq_s32, int32x2_t, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]'] - - [q_lane_s32, int32x4_t, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_s32, int32x4_t, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2'] + - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3'] + - [q_lane_s16, int16x8_t, int16x8_t, int16x4_t, '2'] + - [q_laneq_s16, int16x8_t, int16x8_t, int16x8_t, '3'] + - [_lane_s32, int32x2_t, int32x2_t, int32x2_t, '1'] + - [_laneq_s32, int32x2_t, int32x2_t, int32x4_t, '2'] + - [q_lane_s32, int32x4_t, int32x4_t, int32x2_t, '1'] + - [q_laneq_s32, int32x4_t, int32x4_t, int32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[4]}']] - - Let: [c, "{type[1]}", {FnCall: [simd_shuffle!, [c, c, "{type[5]}"]]}] + - Let: [c, {FnCall: ['vdup{type[0]}', [c], [LANE]]}] - FnCall: ["vqrdmlsh{neon_type[2].no}", [a, b, c]] - name: "vqrdmlsh{type[3]}" @@ -7922,7 +7644,7 @@ intrinsics: - ["i32", int32x4_t, '2', s_laneq_s32, s_s32] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[2]}"]] - - FnCall: ["vqrdmlsh{type[4]}", [a, b, {FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + - FnCall: ["vqrdmlsh{type[4]}", [a, b, {FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]] - name: "vqrshl{type[0]}" doc: "Signed saturating rounding shift left" @@ -7930,7 +7652,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ['s_s32', "i32"] @@ -7948,7 +7670,7 @@ intrinsics: return_type: "{type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i8", 'b_s8', int8x8_t, s8] @@ -7956,7 +7678,7 @@ intrinsics: compose: - Let: [a, "{neon_type[2]}", {FnCall: ["vdup_n_{type[3]}", [a]]}] - Let: [b, "{neon_type[2]}", {FnCall: ["vdup_n_{type[3]}", [b]]}] - - FnCall: [simd_extract!, [{FnCall: ["vqrshl_{type[3]}", [a, b]]}, '0']] + - FnCall: ['vget{neon_type[2].lane_nox}', [{FnCall: ["vqrshl_{type[3]}", [a, b]]}], ['0']] - name: "vqrshl{type[2]}" doc: "Unsigned signed saturating rounding shift left" @@ -7964,7 +7686,7 @@ intrinsics: return_type: "{type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqrshl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["u32", "i32", 's_u32'] @@ -7982,7 +7704,7 @@ intrinsics: return_type: "{type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqrshl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["u8", "i8", "b_u8", uint8x8_t, int8x8_t, s8] @@ -7990,7 +7712,7 @@ intrinsics: compose: - Let: [a, "{neon_type[3]}", {FnCall: ["vdup_n_{type[0]}", [a]]}] - Let: [b, "{neon_type[4]}", {FnCall: ["vdup_n_{type[5]}", [b]]}] - - FnCall: [simd_extract!, [{FnCall: ["vqrshl_{type[0]}", [a, b]]}, '0']] + - FnCall: ['vget{neon_type[3].lane_nox}', [{FnCall: ["vqrshl_{type[0]}", [a, b]]}], ['0']] - name: "vqrshrn{type[2]}" doc: "Signed saturating rounded shift right narrow" @@ -7999,7 +7721,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshrn, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -8009,25 +7731,25 @@ intrinsics: compose: - FnCall: [static_assert!, ["{type[3]}"]] - Let: [a, "{neon_type[4]}", {FnCall: ["vdup{type[5]}", [a]]}] - - FnCall: [simd_extract!, [{FnCall: ["vqrshrn_n{neon_type[4].noq}::", [a]]}, '0']] + - FnCall: ['vget_lane_{type[1]}', [{FnCall: ["vqrshrn_n{neon_type[4].noq}::", [a]]}], ['0']] - name: "vqrshrn{type[3]}" doc: "Signed saturating rounded shift right narrow" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshrn2, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqrshrn2, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [int8x8_t, int16x8_t, int8x16_t, '_high_n_s16', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]', 'N >= 1 && N <= 8'] - - [int16x4_t, int32x4_t, int16x8_t, '_high_n_s32', '[0, 1, 2, 3, 4, 5, 6, 7]', 'N >= 1 && N <= 16'] - - [int32x2_t, int64x2_t, int32x4_t, '_high_n_s64', '[0, 1, 2, 3]', 'N >= 1 && N <= 32'] + - [int8x8_t, int16x8_t, int8x16_t, '_high_n_s16', 'N >= 1 && N <= 8'] + - [int16x4_t, int32x4_t, int16x8_t, '_high_n_s32', 'N >= 1 && N <= 16'] + - [int32x2_t, int64x2_t, int32x4_t, '_high_n_s64', 'N >= 1 && N <= 32'] compose: - - FnCall: [static_assert!, ["{type[5]}"]] - - FnCall: [simd_shuffle!, [a, {FnCall: ["vqrshrn_n{neon_type[1].noq}::", [b]]}, "{type[4]}"]] + - FnCall: [static_assert!, ["{type[4]}"]] + - FnCall: ['vcombine_{neon_type[0]}', [a, {FnCall: ["vqrshrn_n{neon_type[1].noq}::", [b]]}]] - name: "vqrshrn{type[0]}" doc: "Unsigned saturating rounded shift right narrow" @@ -8036,7 +7758,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqrshrn, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -8046,31 +7768,30 @@ intrinsics: compose: - FnCall: [static_assert!, ['{type[3]}']] - Let: [a, "{neon_type[4]}", {FnCall: ["vdup{type[5]}", [a]]}] - - FnCall: [simd_extract!, [{FnCall: ["vqrshrn{type[6]}::", [a]]}, '0']] + - FnCall: ['vget_lane_{type[2]}', [{FnCall: ["vqrshrn{type[6]}::", [a]]}], ['0']] - name: "vqrshrn_high_n{neon_type[1].noq}" doc: "Unsigned saturating rounded shift right narrow" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqrshrn2, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uqrshrn2, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]'] + - [uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8'] + - [uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16'] + - [uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32'] compose: - FnCall: [static_assert!, ['{type[3]}']] - FnCall: - - simd_shuffle! + - 'vcombine_{neon_type[0]}' - - a - FnCall: - "vqrshrn_n{neon_type[1].noq}::" - - b - - "{type[4]}" - name: "vqrshrun{type[0]}" doc: "Signed saturating rounded shift right unsigned narrow" @@ -8079,7 +7800,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshrun, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -8093,35 +7814,34 @@ intrinsics: - "{neon_type[4]}" - FnCall: ["vdupq_n_{type[5]}", [a]] - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vqrshrun_n_{type[5]}::" - - a - - '0' + - - '0' - name: "vqrshrun_high_n{neon_type[1].noq}" doc: "Signed saturating rounded shift right unsigned narrow" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshrun2, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqrshrun2, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [uint8x8_t, int16x8_t, uint8x16_t, 'N >= 1 && N <= 8', s16, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, int32x4_t, uint16x8_t, 'N >= 1 && N <= 16', s32, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, int64x2_t, uint32x4_t, 'N >= 1 && N <= 32', s64, '[0, 1, 2, 3]'] + - [uint8x8_t, int16x8_t, uint8x16_t, 'N >= 1 && N <= 8'] + - [uint16x4_t, int32x4_t, uint16x8_t, 'N >= 1 && N <= 16'] + - [uint32x2_t, int64x2_t, uint32x4_t, 'N >= 1 && N <= 32'] compose: - FnCall: [static_assert!, ["{type[3]}"]] - FnCall: - - simd_shuffle! + - 'vcombine_{neon_type[0]}' - - a - FnCall: - - "vqrshrun_n_{type[4]}::" + - "vqrshrun_n_{neon_type[1]}::" - - b - - "{type[5]}" - name: "vqshld_{type}" doc: "Signed saturating shift left" @@ -8129,7 +7849,7 @@ intrinsics: return_type: "{type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - i64 @@ -8146,7 +7866,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [b_s8, "i8", int8x8_t] @@ -8160,7 +7880,7 @@ intrinsics: - "vqshl{neon_type[2].noq}" - - FnCall: ["vdup_n{neon_type[2].no}", [a]] - FnCall: ["vdup_n{neon_type[2].no}", [b]] - - FnCall: [simd_extract!, [c, '0']] + - FnCall: ['vget{neon_type[2].lane_nox}', [c], ['0']] - name: "vqshl{type[0]}" doc: "Signed saturating shift left" @@ -8169,7 +7889,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshl, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -8180,11 +7900,11 @@ intrinsics: compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[2]}"]] - FnCall: - - simd_extract! + - 'vget_lane_{type[1]}' - - FnCall: - "vqshl_n_{type[3]}::" - - FnCall: ["vdup_n_{type[3]}", [a]] - - '0' + - - '0' - name: "vqshld_{type[0]}" doc: "Unsigned saturating shift left" @@ -8192,7 +7912,7 @@ intrinsics: return_type: "{type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["u64", "i64"] @@ -8209,7 +7929,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [b_u8, "u8", "i8", uint8x8_t, int8x8_t] @@ -8223,7 +7943,7 @@ intrinsics: - "vqshl{neon_type[3].noq}" - - FnCall: ["vdup{neon_type[3].N}", [a]] - FnCall: ["vdup{neon_type[4].N}", [b]] - - FnCall: [simd_extract!, [c, '0']] + - FnCall: ['vget{neon_type[3].lane_nox}', [c], ['0']] - name: "vqshl{type[0]}" doc: "Unsigned saturating shift left" @@ -8232,7 +7952,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshl, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -8243,9 +7963,9 @@ intrinsics: compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[2]}"]] - FnCall: - - simd_extract! + - 'vget_lane_{type[1]}' - - FnCall: ["vqshl_n_{type[1]}::", [{FnCall: ["vdup_n_{type[1]}", [a]]}]] - - '0' + - - '0' - name: "vqshrnd_n_s64" doc: "Signed saturating shift right narrow" @@ -8254,7 +7974,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrn, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -8278,7 +7998,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrn, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -8287,33 +8007,32 @@ intrinsics: compose: - FnCall: [static_assert!, ["{type[3]}"]] - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vqshrn_n_{type[4]}::" - - FnCall: ["vdupq_n_{type[4]}", [a]] - - '0' + - - '0' - name: "vqshrn{type[0]}" doc: "Signed saturating shift right narrow" arguments: ["a: {neon_type[1]}", "b: {neon_type[2]}"] return_type: "{neon_type[3]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrn2, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqshrn2, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [_high_n_s16, int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]', s16] - - [_high_n_s32, int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]', s32] - - [_high_n_s64, int32x2_t, int64x2_t, int32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]', s64] + - [_high_n_s16, int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8'] + - [_high_n_s32, int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16'] + - [_high_n_s64, int32x2_t, int64x2_t, int32x4_t, 'N >= 1 && N <= 32'] compose: - FnCall: [static_assert!, ["{type[4]}"]] - FnCall: - - simd_shuffle! + - 'vcombine_{neon_type[1]}' - - a - - FnCall: ["vqshrn_n_{type[6]}::", [b]] - - "{type[5]}" + - FnCall: ["vqshrn_n_{neon_type[2]}::", [b]] - name: "vqshrnd_n_u64" doc: "Unsigned saturating shift right narrow" @@ -8322,7 +8041,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshrn, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -8346,7 +8065,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshrn, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -8355,33 +8074,32 @@ intrinsics: compose: - FnCall: [static_assert!, ["{type[3]}"]] - FnCall: - - "simd_extract!" + - 'vget_lane_{type[2]}' - - FnCall: - "vqshrn_n_{type[1]}::" - - FnCall: ["vdupq_n_{type[1]}", [a]] - - '0' + - - '0' - name: "vqshrn{type[0]}" doc: "Unsigned saturating shift right narrow" arguments: ["a: {neon_type[1]}", "b: {neon_type[2]}"] return_type: "{neon_type[3]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshrn2, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uqshrn2, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [_high_n_u16, uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [_high_n_u32, uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [_high_n_u64, uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]'] + - [_high_n_u16, uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8'] + - [_high_n_u32, uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16'] + - [_high_n_u64, uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32'] compose: - FnCall: [static_assert!, ["{type[4]}"]] - FnCall: - - simd_shuffle! + - 'vcombine_{neon_type[1]}' - - a - FnCall: ["vqshrn_n_{neon_type[2]}::", [b]] - - "{type[5]}" - name: "vqshrun{type[0]}" doc: "Signed saturating shift right unsigned narrow" @@ -8390,7 +8108,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrun, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -8400,33 +8118,32 @@ intrinsics: compose: - FnCall: [static_assert!, ["{type[3]}"]] - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vqshrun_n_{type[4]}::" - - FnCall: ["vdupq_n_{type[4]}", [a]] - - '0' + - - '0' - name: "vqshrun_high_n_{neon_type[1]}" doc: "Signed saturating shift right unsigned narrow" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrun2, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqshrun2, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [uint8x8_t, int16x8_t, uint8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, int32x4_t, uint16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, int64x2_t, uint32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]'] + - [uint8x8_t, int16x8_t, uint8x16_t, 'N >= 1 && N <= 8'] + - [uint16x4_t, int32x4_t, uint16x8_t, 'N >= 1 && N <= 16'] + - [uint32x2_t, int64x2_t, uint32x4_t, 'N >= 1 && N <= 32'] compose: - FnCall: [static_assert!, ["{type[3]}"]] - FnCall: - - simd_shuffle! + - 'vcombine_{neon_type[0]}' - - a - FnCall: ["vqshrun_n_{neon_type[1]}::", [b]] - - "{type[4]}" - name: "vsqadd{type[0]}" doc: "Unsigned saturating accumulate of signed value" @@ -8434,19 +8151,19 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [usqadd]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [b_u8, "u8", "i8", s8] - [h_u16, "u16", "i16", s16] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[1]}' - - FnCall: - "vsqadd_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - FnCall: ["vdup_n_{type[2]}", [b]] - - '0' + - - '0' - name: "vsqadd{type[0]}" doc: "Unsigned saturating accumulate of signed value" @@ -8454,7 +8171,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [usqadd]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [s_u32, "u32", "i32"] @@ -8472,7 +8189,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fsqrt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - float32x2_t @@ -8519,7 +8236,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frsqrts]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [_f64, float64x1_t, v1f64] @@ -8537,7 +8254,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frsqrts]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [s_f32, "f32"] @@ -8576,7 +8293,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecpe]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [_f64, float64x1_t, v1f64] @@ -8594,7 +8311,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecpe]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [s_f32, "f32"] @@ -8633,7 +8350,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecps]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [_f64, float64x1_t, v1f64] @@ -8651,7 +8368,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecps]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [s_f32, "f32"] @@ -8690,7 +8407,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecpx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [s_f32, "f32"] @@ -8722,7 +8439,6 @@ intrinsics: - link: "llvm.aarch64.neon.frecpx.{type[1]}" arch: aarch64,arm64ec - - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}" doc: Vector reinterpret cast operation arguments: ["a: {type[0]}"] @@ -8739,54 +8455,65 @@ intrinsics: - [poly64x2_t, uint64x2_t] - [int64x2_t, poly64x2_t] - [uint64x2_t, poly64x2_t] + - [float64x1_t, int64x1_t] + - [float64x2_t, int64x2_t] + - [float64x1_t, uint64x1_t] + - [float64x2_t, uint64x2_t] + - [float64x1_t, poly64x1_t] + - [float64x2_t, poly64x2_t] + - [int64x1_t, float64x1_t] + - [int64x2_t, float64x2_t] + - [uint64x1_t, float64x1_t] + - [uint64x2_t, float64x2_t] + - [poly64x1_t, float64x1_t] + - [poly64x2_t, float64x2_t] + compose: + - FnCall: [transmute, [a]] + + - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}" + doc: Vector reinterpret cast operation + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: [*neon-stable] + assert_instr: [nop] + safety: safe + types: - [float64x1_t, int8x8_t] - [float64x1_t, int16x4_t] - [float64x1_t, int32x2_t] - - [float64x1_t, int64x1_t] - [float64x2_t, int8x16_t] - [float64x2_t, int16x8_t] - [float64x2_t, int32x4_t] - - [float64x2_t, int64x2_t] - [float64x1_t, uint8x8_t] - [float64x1_t, uint16x4_t] - [float64x1_t, uint32x2_t] - - [float64x1_t, uint64x1_t] - [float64x2_t, uint8x16_t] - [float64x2_t, uint16x8_t] - [float64x2_t, uint32x4_t] - - [float64x2_t, uint64x2_t] - [float64x1_t, poly8x8_t] - [float64x1_t, poly16x4_t] - [float32x2_t, poly64x1_t] - - [float64x1_t, poly64x1_t] - [float64x2_t, poly8x16_t] - [float64x2_t, poly16x8_t] - [float32x4_t, poly64x2_t] - - [float64x2_t, poly64x2_t] - [float64x2_t, p128] - [int8x8_t, float64x1_t] - [int16x4_t, float64x1_t] - [int32x2_t, float64x1_t] - - [int64x1_t, float64x1_t] - [int8x16_t, float64x2_t] - [int16x8_t, float64x2_t] - [int32x4_t, float64x2_t] - - [int64x2_t, float64x2_t] - [poly8x8_t, float64x1_t] - [uint16x4_t, float64x1_t] - [uint32x2_t, float64x1_t] - - [uint64x1_t, float64x1_t] - [poly8x16_t, float64x2_t] - [uint16x8_t, float64x2_t] - [uint32x4_t, float64x2_t] - - [uint64x2_t, float64x2_t] - [uint8x8_t, float64x1_t] - [poly16x4_t, float64x1_t] - - [poly64x1_t, float64x1_t] - [poly64x1_t, float32x2_t] - [uint8x16_t, float64x2_t] - [poly16x8_t, float64x2_t] - - [poly64x2_t, float64x2_t] - [poly64x2_t, float32x4_t] - [p128, float64x2_t] - [float32x2_t, float64x1_t] @@ -8822,7 +8549,7 @@ intrinsics: return_type: "{type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [srshl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - "i64" @@ -8839,7 +8566,7 @@ intrinsics: return_type: "{type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [urshl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["u64", "i64"] @@ -8857,7 +8584,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [srshr, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -8873,7 +8600,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [urshr, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -8887,198 +8614,263 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [rshrn2, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [rshrn2, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [int32x2_t, int64x2_t, int32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]'] - - [uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]'] + - [int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8'] + - [int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16'] + - [int32x2_t, int64x2_t, int32x4_t, 'N >= 1 && N <= 32'] + - [uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8'] + - [uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16'] + - [uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32'] compose: - FnCall: [static_assert!, ["{type[3]}"]] - FnCall: - - simd_shuffle! + - 'vcombine_{neon_type[0]}' - - a - FnCall: ["vrshrn_n_{neon_type[1]}::", [b]] - - "{type[4]}" - name: "vrsubhn_high_{neon_type[1]}" doc: "Rounding subtract returning high narrow" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] return_type: "{neon_type[3]}" attr: - - *little-endian + - *cfg-little-endian - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [rsubhn2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [int8x8_t, int16x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [int16x4_t, int32x4_t, int32x4_t, int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [int32x2_t, int64x2_t, int64x2_t, int32x4_t, '[0, 1, 2, 3]'] - - [uint8x8_t, uint16x8_t, uint16x8_t, uint8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, uint32x4_t, uint32x4_t, uint16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, uint64x2_t, uint64x2_t, uint32x4_t, '[0, 1, 2, 3]'] + - [int8x8_t, int16x8_t, int16x8_t, int8x16_t] + - [int16x4_t, int32x4_t, int32x4_t, int16x8_t] + - [int32x2_t, int64x2_t, int64x2_t, int32x4_t] + - [uint8x8_t, uint16x8_t, uint16x8_t, uint8x16_t] + - [uint16x4_t, uint32x4_t, uint32x4_t, uint16x8_t] + - [uint32x2_t, uint64x2_t, uint64x2_t, uint32x4_t] compose: - - Let: - - x - - "{neon_type[0]}" - - FnCall: ["vrsubhn_{neon_type[1]}", [b, c]] - - FnCall: [simd_shuffle!, [a, x, "{type[4]}"]] + - FnCall: ['vcombine_{neon_type[0]}', [a, {FnCall: ["vrsubhn_{neon_type[1]}", [b, c]]}]] - name: "vrsubhn_high_{neon_type[1]}" doc: "Rounding subtract returning high narrow" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] return_type: "{neon_type[3]}" attr: - - *big-endian + - *cfg-big-endian - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [rsubhn]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [int8x8_t, int16x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [int16x4_t, int32x4_t, int32x4_t, int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [int32x2_t, int64x2_t, int64x2_t, int32x4_t, '[0, 1, 2, 3]'] - - [uint8x8_t, uint16x8_t, uint16x8_t, uint8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, uint32x4_t, uint32x4_t, uint16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, uint64x2_t, uint64x2_t, uint32x4_t, '[0, 1, 2, 3]'] + - [int8x8_t, int16x8_t, int16x8_t, int8x16_t] + - [int16x4_t, int32x4_t, int32x4_t, int16x8_t] + - [int32x2_t, int64x2_t, int64x2_t, int32x4_t] + - [uint8x8_t, uint16x8_t, uint16x8_t, uint8x16_t] + - [uint16x4_t, uint32x4_t, uint32x4_t, uint16x8_t] + - [uint32x2_t, uint64x2_t, uint64x2_t, uint32x4_t] compose: - - Let: - - x - - "{neon_type[0]}" - - FnCall: ["vrsubhn_{neon_type[1]}", [b, c]] - - FnCall: [simd_shuffle!, [a, x, "{type[4]}"]] + - FnCall: ['vcombine_{neon_type[0]}', [a, {FnCall: ["vrsubhn_{neon_type[1]}", [b, c]]}]] - name: "vcopy{neon_type[0].lane_nox}" doc: "Insert vector element from another vector element" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1', '3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE1: i32, const LANE2: i32'] safety: safe types: - - [int8x8_t, int8x8_t, int8x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [int16x4_t, int16x4_t, int16x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [int32x2_t, int32x2_t, int32x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint8x8_t, uint8x8_t, uint8x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint16x4_t, uint16x4_t, uint16x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint32x2_t, uint32x2_t, uint32x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [poly8x8_t, poly8x8_t, poly8x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [poly16x4_t, poly16x4_t, poly16x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [float32x2_t, float32x2_t, float32x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [int8x8_t, int8x8_t, int8x8_t, '3', '3'] + - [int16x4_t, int16x4_t, int16x4_t, '2', '2'] + - [int32x2_t, int32x2_t, int32x2_t, '1', '1'] + - [uint8x8_t, uint8x8_t, uint8x8_t, '3', '3'] + - [uint16x4_t, uint16x4_t, uint16x4_t, '2', '2'] + - [uint32x2_t, uint32x2_t, uint32x2_t, '1', '1'] + - [poly8x8_t, poly8x8_t, poly8x8_t, '3', '3'] + - [poly16x4_t, poly16x4_t, poly16x4_t, '2', '2'] + - [float32x2_t, float32x2_t, float32x2_t, '1', '1'] compose: - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']] - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']] - - Identifier: ["{type[5]}", Symbol] + - FnCall: ['vset{neon_type[0].lane_nox}', [{FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE2]]}, a], [LANE1]] - name: "vcopy{neon_type[0].lane_nox}" doc: "Insert vector element from another vector element" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1', '3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE1: i32, const LANE2: i32'] safety: safe types: - - [int8x16_t, int8x8_t, int8x16_t, '4', '3', ' let b: int8x16_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [int16x8_t, int16x4_t, int16x8_t, '3', '2', ' let b: int16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [int32x4_t, int32x2_t, int32x4_t, '2', '1', ' let b: int32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint8x16_t, uint8x8_t, uint8x16_t, '4', '3', ' let b: uint8x16_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint16x8_t, uint16x4_t, uint16x8_t, '3', '2', ' let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint32x4_t, uint32x2_t, uint32x4_t, '2', '1', ' let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [poly8x16_t, poly8x8_t, poly8x16_t, '4', '3', ' let b: poly8x16_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [poly16x8_t, poly16x4_t, poly16x8_t, '3', '2', ' let b: poly16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [int8x16_t, int8x8_t, int8x16_t, '4', '3'] + - [int16x8_t, int16x4_t, int16x8_t, '3', '2'] + - [int32x4_t, int32x2_t, int32x4_t, '2', '1'] + - [uint8x16_t, uint8x8_t, uint8x16_t, '4', '3'] + - [uint16x8_t, uint16x4_t, uint16x8_t, '3', '2'] + - [uint32x4_t, uint32x2_t, uint32x4_t, '2', '1'] + - [poly8x16_t, poly8x8_t, poly8x16_t, '4', '3'] + - [poly16x8_t, poly16x4_t, poly16x8_t, '3', '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']] - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']] - - Identifier: ["{type[5]}", Symbol] - - Identifier: ["{type[6]}", Symbol] + - Let: [b, '{neon_type[2]}', {FnCall: ['vcombine{neon_type[1].no}', [b, b]]}] + - FnCall: ['vset{neon_type[0].lane_nox}', [{FnCall: ['vget{neon_type[2].lane_nox}', [b], [LANE2]]}, a], [LANE1]] + + - name: "vcopy_lane_{neon_type[0]}" + doc: "Insert vector element from another vector element" + arguments: ["_a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE1 = {type[1]}', 'LANE2 = {type[1]}']]}]] + - FnCall: [rustc_legacy_const_generics, ['1', '3']] + - *neon-stable + static_defs: ['const LANE1: i32, const LANE2: i32'] + safety: safe + types: + - [float64x1_t, '0', 'b'] + - [poly64x1_t, '0', 'b'] + - [uint64x1_t, '0', 'b'] + - [int64x1_t, '0', 'b'] + compose: + - FnCall: [static_assert!, ['LANE1 == {type[1]}']] + - FnCall: [static_assert!, ['LANE2 == {type[1]}']] + - Identifier: ["{type[2]}", Symbol] + + - name: "vcopy_laneq_{neon_type[0]}" + doc: "Insert vector element from another vector element" + arguments: ["_a: {neon_type[1]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE1 = {type[2]}', 'LANE2 = {type[3]}']]}]] + - FnCall: [rustc_legacy_const_generics, ['1', '3']] + - *neon-stable + static_defs: ['const LANE1: i32, const LANE2: i32'] + safety: safe + types: + - [float64x2_t, float64x1_t, '0', '1'] + - [poly64x2_t, poly64x1_t, '0', '1'] + - [uint64x2_t, uint64x1_t, '0', '1'] + - [int64x2_t, int64x1_t, '0', '1'] + compose: + - FnCall: [static_assert!, ['LANE1 == {type[2]}']] + - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[3]}']] + - FnCall: [transmute, [{FnCall: ['vget{neon_type[0].lane_nox}', [b], [LANE2]]}]] - name: "vcopy{neon_type[0].laneq_nox}" doc: "Insert vector element from another vector element" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1', '3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE1: i32, const LANE2: i32'] safety: safe types: - - [int8x16_t, int8x16_t, int8x16_t, '4', '4', ' unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [int16x8_t, int16x8_t, int16x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [int32x4_t, int32x4_t, int32x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [int64x2_t, int64x2_t, int64x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint8x16_t, uint8x16_t, uint8x16_t, '4', '4', ' unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint16x8_t, uint16x8_t, uint16x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint32x4_t, uint32x4_t, uint32x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint64x2_t, uint64x2_t, uint64x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [poly8x16_t, poly8x16_t, poly8x16_t, '4', '4', ' unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [poly16x8_t, poly16x8_t, poly16x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [poly64x2_t, poly64x2_t, poly64x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [float32x4_t, float32x4_t, float32x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [float64x2_t, float64x2_t, float64x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [int8x16_t, int8x16_t, int8x16_t, '4', '4'] + - [int16x8_t, int16x8_t, int16x8_t, '3', '3'] + - [int32x4_t, int32x4_t, int32x4_t, '2', '2'] + - [int64x2_t, int64x2_t, int64x2_t, '1', '1'] + - [uint8x16_t, uint8x16_t, uint8x16_t, '4', '4'] + - [uint16x8_t, uint16x8_t, uint16x8_t, '3', '3'] + - [uint32x4_t, uint32x4_t, uint32x4_t, '2', '2'] + - [uint64x2_t, uint64x2_t, uint64x2_t, '1', '1'] + - [poly8x16_t, poly8x16_t, poly8x16_t, '4', '4'] + - [poly16x8_t, poly16x8_t, poly16x8_t, '3', '3'] + - [float32x4_t, float32x4_t, float32x4_t, '2', '2'] + - [float64x2_t, float64x2_t, float64x2_t, '1', '1'] compose: - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']] - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']] - - Identifier: ["{type[5]}", Symbol] + - FnCall: ['vset{neon_type[0].lane_nox}', [{FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE2]]}, a], [LANE1]] - name: "vcopy{neon_type[0].laneq_nox}" doc: "Insert vector element from another vector element" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1', '3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE1: i32, const LANE2: i32'] safety: safe + big_endian_inverse: true types: - - [int8x8_t, int8x16_t, int8x8_t, '3', '4', ' let a: int8x16_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [int16x4_t, int16x8_t, int16x4_t, '2', '3', ' let a: int16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [int32x2_t, int32x4_t, int32x2_t, '1', '2', ' let a: int32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint8x8_t, uint8x16_t, uint8x8_t, '3', '4', ' let a: uint8x16_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint16x4_t, uint16x8_t, uint16x4_t, '2', '3', ' let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint32x2_t, uint32x4_t, uint32x2_t, '1', '2', 'let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [poly8x8_t, poly8x16_t, poly8x8_t, '3', '4', ' let a: poly8x16_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [poly16x4_t, poly16x8_t, poly16x4_t, '2', '3', ' let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [float32x2_t, float32x4_t, float32x2_t, '1', '2', ' let a: float32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [poly64x2_t, poly64x2_t, poly64x2_t, '1', '1'] compose: - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']] - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']] - - Identifier: ["{type[5]}", Symbol] - - Identifier: ["{type[6]}", Symbol] + - FnCall: [simd_insert!, [a, LANE1 as u32, {FnCall: [simd_extract!, [b, LANE2 as u32, p64]]}]] - - name: "vcopyq_lane_{neon_type[0]}" + - name: "vcopy{neon_type[0].laneq_nox}" doc: "Insert vector element from another vector element" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] - return_type: "{neon_type[0]}" + return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 1', 'LANE2 = 0']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1', '3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE1: i32, const LANE2: i32'] safety: safe types: - - [int64x2_t, int64x1_t, ' let b: int64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint64x2_t, uint64x1_t, ' let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [poly64x2_t, poly64x1_t, ' let b: poly64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [float64x2_t, float64x1_t, ' let b: float64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [int8x8_t, int8x16_t, int8x8_t, '3', '4'] + - [int16x4_t, int16x8_t, int16x4_t, '2', '3'] + - [int32x2_t, int32x4_t, int32x2_t, '1', '2'] + - [uint8x8_t, uint8x16_t, uint8x8_t, '3', '4'] + - [uint16x4_t, uint16x8_t, uint16x4_t, '2', '3'] + - [uint32x2_t, uint32x4_t, uint32x2_t, '1', '2'] + - [poly8x8_t, poly8x16_t, poly8x8_t, '3', '4'] + - [poly16x4_t, poly16x8_t, poly16x4_t, '2', '3'] + - [float32x2_t, float32x4_t, float32x2_t, '1', '2'] compose: - - FnCall: [static_assert_uimm_bits!, [LANE1, '1']] - - FnCall: [static_assert!, ['LANE2 == 0']] - - Identifier: ['{type[2]}', Symbol] - - Identifier: ['{type[3]}', Symbol] - + - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']] + - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']] + - FnCall: ['vset{neon_type[0].lane_nox}', [{FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE2]]}, a], [LANE1]] + + - name: "vcopyq_lane_{neon_type[0]}" + doc: "Insert vector element from another vector element" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 1', 'LANE2 = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['1', '3']] + - *neon-stable + static_defs: ['const LANE1: i32, const LANE2: i32'] + safety: safe + types: + - [int64x2_t, int64x1_t] + - [uint64x2_t, uint64x1_t] + - [float64x2_t, float64x1_t] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE1, '1']] + - FnCall: [static_assert!, ['LANE2 == 0']] + - Let: [b, '{neon_type[0]}', {FnCall: ['vcombine{neon_type[1].no}', [b, b]]}] + - FnCall: ['vset{neon_type[0].lane_nox}', [{FnCall: ['vget{neon_type[0].lane_nox}', [b], [LANE2]]}, a], [LANE1]] + + - name: "vcopyq_lane_{neon_type[0]}" + doc: "Insert vector element from another vector element" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 1', 'LANE2 = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['1', '3']] + - *neon-stable + static_defs: ['const LANE1: i32, const LANE2: i32'] + safety: safe + big_endian_inverse: true + types: + - [poly64x2_t, poly64x1_t] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE1, '1']] + - FnCall: [static_assert!, ['LANE2 == 0']] + - Let: [b, '{neon_type[0]}', {FnCall: ['vcombine{neon_type[1].no}', [b, b]]}] + - FnCall: [simd_insert!, [a, LANE1 as u32, {FnCall: [simd_extract!, [b, LANE2 as u32, p64]]}]] + - name: "vcopyq_lane_f32" doc: "Insert vector element from another vector element" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] @@ -9086,16 +8878,15 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 1', 'LANE2 = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1', '3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE1: i32, const LANE2: i32'] safety: safe types: - - [float32x4_t, float32x2_t, ' let b: float32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [float32x4_t, float32x2_t] compose: - FnCall: [static_assert_uimm_bits!, [LANE1, 2]] - FnCall: [static_assert_uimm_bits!, [LANE2, 1]] - - Identifier: ["{type[2]}", Symbol] - - Identifier: ["{type[3]}", Symbol] + - FnCall: ['vset{neon_type[0].lane_nox}', [{FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE2]]}, a], [LANE1]] - name: "vcreate_f64" doc: "Insert vector element from another vector element" @@ -9103,7 +8894,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["u64", float64x1_t] @@ -9117,9 +8908,10 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe + big_endian_inverse: true types: - ["f64", float64x1_t, float64x1_t] compose: @@ -9133,9 +8925,10 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe + big_endian_inverse: true types: - ["f64", float64x2_t, float64x2_t] compose: @@ -9148,7 +8941,7 @@ intrinsics: return_type: "{type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sshl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - "i64" @@ -9166,7 +8959,7 @@ intrinsics: return_type: "{type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ushl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["u64", "i64"] @@ -9183,63 +8976,62 @@ intrinsics: arguments: ["a: {neon_type[0]}"] return_type: "{neon_type[1]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sshll2, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sshll2, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [int8x16_t, int16x8_t, int8x8_t, 'N >= 0 && N <= 8', '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [int16x8_t, int32x4_t, int16x4_t, 'N >= 0 && N <= 16', '[4, 5, 6, 7]'] - - [int32x4_t, int64x2_t, int32x2_t, 'N >= 0 && N <= 32', '[2, 3]'] + - [int8x16_t, int16x8_t, int8x8_t, 'N >= 0 && N <= 8'] + - [int16x8_t, int32x4_t, int16x4_t, 'N >= 0 && N <= 16'] + - [int32x4_t, int64x2_t, int32x2_t, 'N >= 0 && N <= 32'] compose: - FnCall: [static_assert!, ["{type[3]}"]] - - Let: [b, "{neon_type[2]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}] - - FnCall: ["vshll_n_{neon_type[2]}::", [b]] + - Let: [b, {FnCall: ['vget_high_{neon_type[0]}', [a]]}] + - FnCall: ["vshll_n_{neon_type[2]}", [b], [N]] - name: "vshll_high_n_{neon_type[0]}" doc: "Signed shift left long" arguments: ["a: {neon_type[0]}"] return_type: "{neon_type[1]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ushll2, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [ushll2, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [uint8x16_t, uint16x8_t, uint8x8_t, 'N >= 0 && N <= 8', '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x8_t, uint32x4_t, uint16x4_t, 'N >= 0 && N <= 16', '[4, 5, 6, 7]'] - - [uint32x4_t, uint64x2_t, uint32x2_t, 'N >= 0 && N <= 32', '[2, 3]'] + - [uint8x16_t, uint16x8_t, uint8x8_t, 'N >= 0 && N <= 8'] + - [uint16x8_t, uint32x4_t, uint16x4_t, 'N >= 0 && N <= 16'] + - [uint32x4_t, uint64x2_t, uint32x2_t, 'N >= 0 && N <= 32'] compose: - FnCall: [static_assert!, ["{type[3]}"]] - - Let: [b, "{neon_type[2]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}] - - FnCall: ["vshll_n_{neon_type[2]}::", [b]] + - Let: [b, "{neon_type[2]}", {FnCall: ['vget_high_{neon_type[0]}', [a]]}] + - FnCall: ["vshll_n_{neon_type[2]}", [b], [N]] - name: "vshrn_high_n_{neon_type[1]}" doc: "Shift right narrow" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [shrn2, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [shrn2, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [int32x2_t, int64x2_t, int32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]'] - - [uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]'] + - [int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8'] + - [int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16'] + - [int32x2_t, int64x2_t, int32x4_t, 'N >= 1 && N <= 32'] + - [uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8'] + - [uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16'] + - [uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32'] compose: - FnCall: [static_assert!, ["{type[3]}"]] - FnCall: - - simd_shuffle! + - 'vcombine_{neon_type[0]}' - - a - - FnCall: ["vshrn_n_{neon_type[1]}::", [b]] - - "{type[4]}" + - FnCall: ["vshrn_n_{neon_type[1]}", [b], [N]] - name: "vsm3partw1{neon_type.no}" doc: "SM3PARTW1" @@ -9250,6 +9042,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sm3partw1]]}]] - FnCall: [unstable, ['feature = "stdarch_neon_sm4"', 'issue = "117226"']] safety: safe + big_endian_inverse: true types: - uint32x4_t compose: @@ -9268,6 +9061,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sm3partw2]]}]] - FnCall: [unstable, ['feature = "stdarch_neon_sm4"', 'issue = "117226"']] safety: safe + big_endian_inverse: true types: - uint32x4_t compose: @@ -9286,6 +9080,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sm3ss1]]}]] - FnCall: [unstable, ['feature = "stdarch_neon_sm4"', 'issue = "117226"']] safety: safe + big_endian_inverse: true types: - uint32x4_t compose: @@ -9304,6 +9099,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sm4ekey]]}]] - FnCall: [unstable, ['feature = "stdarch_neon_sm4"', 'issue = "117226"']] safety: safe + big_endian_inverse: true types: - uint32x4_t compose: @@ -9322,6 +9118,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sm4e]]}]] - FnCall: [unstable, ['feature = "stdarch_neon_sm4"', 'issue = "117226"']] safety: safe + big_endian_inverse: true types: - uint32x4_t compose: @@ -9358,6 +9155,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sha512h]]}]] - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] safety: safe + big_endian_inverse: true types: - uint64x2_t compose: @@ -9376,6 +9174,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sha512h2]]}]] - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] safety: safe + big_endian_inverse: true types: - uint64x2_t compose: @@ -9394,6 +9193,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sha512su0]]}]] - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] safety: safe + big_endian_inverse: true types: - uint64x2_t compose: @@ -9412,6 +9212,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sha512su1]]}]] - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] safety: safe + big_endian_inverse: true types: - uint64x2_t compose: @@ -9432,6 +9233,7 @@ intrinsics: - FnCall: [unstable, ['feature = "stdarch_neon_sm4"', 'issue = "117226"']] static_defs: ["const IMM2: i32"] safety: safe + big_endian_inverse: true types: - ['1aq_u32', uint32x4_t, 'sm3tt1a', 'SM3TT1A'] - ['1bq_u32', uint32x4_t, 'sm3tt1b', 'SM3TT1B'] @@ -9534,7 +9336,7 @@ intrinsics: - transmute - - FnCall: - _vrnd32x_f64 - - - FnCall: [simd_extract!, [a, 0]] + - - FnCall: ['vget{neon_type.lane_nox}', [a], [0]] - name: "vrnd32z{neon_type.no}" doc: "Floating-point round to 32-bit integer toward zero" @@ -9578,7 +9380,7 @@ intrinsics: arch: aarch64,arm64ec - FnCall: - transmute - - - FnCall: [_vrnd32z_f64, [{FnCall: [simd_extract!, [a, 0]]}]] + - - FnCall: [_vrnd32z_f64, [{FnCall: ['vget{neon_type.lane_nox}', [a], [0]]}]] - name: "vrnd64x{neon_type.no}" doc: "Floating-point round to 64-bit integer, using current rounding mode" @@ -9622,7 +9424,7 @@ intrinsics: arch: aarch64,arm64ec - FnCall: - transmute - - - FnCall: [_vrnd64x_f64, [{FnCall: [simd_extract!, [a, 0]]}]] + - - FnCall: [_vrnd64x_f64, [{FnCall: ['vget{neon_type.lane_nox}', [a], [0]]}]] - name: "vrnd64z{neon_type.no}" doc: "Floating-point round to 64-bit integer toward zero" @@ -9666,7 +9468,7 @@ intrinsics: arch: aarch64,arm64ec - FnCall: - transmute - - - FnCall: [_vrnd64z_f64, [{FnCall: [simd_extract!, [a, 0]]}]] + - - FnCall: [_vrnd64z_f64, [{FnCall: ['vget{neon_type.lane_nox}', [a], [0]]}]] - name: "vtrn1{neon_type[0].no}" doc: Transpose vectors @@ -9674,8 +9476,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - *neon-stable - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn1]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [trn1]]}]] safety: safe + big_endian_inverse: true types: - [int8x8_t, '[0, 8, 2, 10, 4, 12, 6, 14]'] - [int8x16_t, '[0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]'] @@ -9704,8 +9507,9 @@ intrinsics: - *neon-fp16 - *neon-stable-fp16 - *target-not-arm64ec - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn1]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [trn1]]}]] safety: safe + big_endian_inverse: true types: - [float16x4_t, '[0, 4, 2, 6]'] - [float16x8_t, '[0, 8, 2, 10, 4, 12, 6, 14]'] @@ -9718,8 +9522,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - *neon-stable - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip1]]}]] safety: safe + big_endian_inverse: true types: - [int32x2_t, '[0, 2]'] - [int64x2_t, '[0, 2]'] @@ -9737,8 +9542,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - *neon-stable - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn2]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [trn2]]}]] safety: safe + big_endian_inverse: true types: - [int8x8_t, '[1, 9, 3, 11, 5, 13, 7, 15]'] - [int8x16_t, '[1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]'] @@ -9766,8 +9572,9 @@ intrinsics: - *neon-fp16 - *neon-stable-fp16 - *target-not-arm64ec - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn2]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [trn2]]}]] safety: safe + big_endian_inverse: true types: - [float16x4_t, '[1, 5, 3, 7]'] - [float16x8_t, '[1, 9, 3, 11, 5, 13, 7, 15]'] @@ -9780,8 +9587,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - *neon-stable - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip2]]}]] safety: safe + big_endian_inverse: true types: - [int32x2_t, '[1, 3]'] - [int64x2_t, '[1, 3]'] @@ -9799,8 +9607,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - *neon-stable - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip2]]}]] safety: safe + big_endian_inverse: true types: - [int8x8_t, '[4, 12, 5, 13, 6, 14, 7, 15]'] - [int8x16_t, '[8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]'] @@ -9835,8 +9644,9 @@ intrinsics: - *neon-fp16 - *neon-stable-fp16 - *target-not-arm64ec - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip2]]}]] safety: safe + big_endian_inverse: true types: - [float16x4_t, '[2, 6, 3, 7]'] - [float16x8_t, '[4, 12, 5, 13, 6, 14, 7, 15]'] @@ -9849,8 +9659,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - *neon-stable - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip1]]}]] safety: safe + big_endian_inverse: true types: - [int8x8_t, '[0, 8, 1, 9, 2, 10, 3, 11]'] - [int8x16_t, '[0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]'] @@ -9886,8 +9697,9 @@ intrinsics: - *neon-fp16 - *neon-stable-fp16 - *target-not-arm64ec - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip1]]}]] safety: safe + big_endian_inverse: true types: - [float16x4_t, '[0, 4, 1, 5]'] - [float16x8_t, '[0, 8, 1, 9, 2, 10, 3, 11]'] @@ -9900,8 +9712,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - *neon-stable - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip1]]}]] safety: safe + big_endian_inverse: true types: - [int32x2_t, '[0, 2]'] - [int64x2_t, '[0, 2]'] @@ -9919,8 +9732,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - *neon-stable - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp1]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [uzp1]]}]] safety: safe + big_endian_inverse: true types: - [int8x8_t, '[0, 2, 4, 6, 8, 10, 12, 14]'] - [int8x16_t, '[0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]'] @@ -9948,8 +9762,9 @@ intrinsics: - *neon-fp16 - *neon-stable-fp16 - *target-not-arm64ec - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp1]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [uzp1]]}]] safety: safe + big_endian_inverse: true types: - [float16x4_t, '[0, 2, 4, 6]'] - [float16x8_t, '[0, 2, 4, 6, 8, 10, 12, 14]'] @@ -9962,8 +9777,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - *neon-stable - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip2]]}]] safety: safe + big_endian_inverse: true types: - [int32x2_t, '[1, 3]'] - [int64x2_t, '[1, 3]'] @@ -9981,8 +9797,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - *neon-stable - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp2]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [uzp2]]}]] safety: safe + big_endian_inverse: true types: - [int8x8_t, '[1, 3, 5, 7, 9, 11, 13, 15]'] - [int8x16_t, '[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]'] @@ -10014,8 +9831,9 @@ intrinsics: - *neon-fp16 - *neon-stable-fp16 - *target-not-arm64ec - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp2]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [uzp2]]}]] safety: safe + big_endian_inverse: true types: - [float16x4_t, '[1, 3, 5, 7]'] - [float16x8_t, '[1, 3, 5, 7, 9, 11, 13, 15]'] @@ -10031,23 +9849,21 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uabal2]]}]] + - *neon-stable + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [uabal2]]}]] safety: safe types: - - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint32x4_t, uint16x8_t, uint16x4_t, '[4, 5, 6, 7]', '[4, 5, 6, 7]'] - - [uint64x2_t, uint32x4_t, uint32x2_t, '[2, 3]', '[2, 3]'] + - [uint16x8_t, uint8x16_t, uint8x8_t] + - [uint32x4_t, uint16x8_t, uint16x4_t] + - [uint64x2_t, uint32x4_t, uint32x2_t] compose: - Let: - d - - "{neon_type[2]}" - - FnCall: [simd_shuffle!, [b, b, "{type[3]}"]] + - FnCall: ['vget_high_{neon_type[1]}', [b]] - Let: - e - - "{neon_type[2]}" - - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] - - Let: [f, "{neon_type[2]}", {FnCall: ["vabd_{neon_type[2]}", [d, e]]}] + - FnCall: ['vget_high_{neon_type[1]}', [c]] + - Let: [f, {FnCall: ["vabd_{neon_type[2]}", [d, e]]}] - FnCall: - simd_add - - a @@ -10059,39 +9875,28 @@ intrinsics: return_type: "{neon_type[0]}" attr: - *neon-stable - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sabal2]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [sabal2]]}]] safety: safe types: - - [int16x8_t, int8x16_t, int8x16_t, '[8, 9, 10, 11, 12, 13, 14, 15]', int8x8_t, uint8x8_t] - - [int32x4_t, int16x8_t, int16x8_t, '[4, 5, 6, 7]', int16x4_t, uint16x4_t] - - [int64x2_t, int32x4_t, int32x4_t, '[2, 3]', int32x2_t, uint32x2_t] + - [int16x8_t, int8x16_t, int8x16_t, int8x8_t, uint8x8_t] + - [int32x4_t, int16x8_t, int16x8_t, int16x4_t, uint16x4_t] + - [int64x2_t, int32x4_t, int32x4_t, int32x2_t, uint32x2_t] compose: - Let: - d - - "{neon_type[4]}" - - FnCall: - - simd_shuffle! - - - b - - b - - "{type[3]}" + - FnCall: ['vget_high_{neon_type[1]}', [b]] - Let: - e - - "{neon_type[4]}" - - FnCall: - - simd_shuffle! - - - c - - c - - "{type[3]}" + - FnCall: ['vget_high_{neon_type[2]}', [c]] - Let: - f - - "{neon_type[4]}" - FnCall: - - "vabd{neon_type[4].no}" + - "vabd{neon_type[3].no}" - - d - e - Let: - f - - "{neon_type[5]}" + - "{neon_type[4]}" - FnCall: - simd_cast - - f @@ -10158,7 +9963,7 @@ intrinsics: attr: - *neon-stable - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sri, 'N = 2']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [bfxil, 'N = 2']]}]] safety: safe types: - i64 @@ -10184,8 +9989,9 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmaxnmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe + big_endian_inverse: true types: - float32x2_t - float64x2_t @@ -10202,7 +10008,7 @@ intrinsics: arguments: ["a: {type[0]}", "b: {neon_type[1]}"] attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st1]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: unsafe: [neon] types: @@ -10225,7 +10031,7 @@ intrinsics: arguments: ["a: {type[0]}", "b: {neon_type[1]}"] attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st1]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: unsafe: [neon] types: @@ -10249,7 +10055,7 @@ intrinsics: arguments: ["a: {type[0]}", "b: {neon_type[1]}"] attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st1]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: unsafe: [neon] types: @@ -10276,7 +10082,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmla, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -10291,7 +10097,7 @@ intrinsics: - "vfma{neon_type[0].no}" - - a - b - - FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + - FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]] - name: "vfma{type[3]}" @@ -10317,7 +10123,7 @@ intrinsics: - "vfma{neon_type[0].no}" - - a - b - - FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + - FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]] # vfms lane f16 @@ -10344,7 +10150,7 @@ intrinsics: - "vfms{neon_type[0].no}" - - a - b - - FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + - FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]] - name: "vfms{type[1]}" @@ -10370,7 +10176,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -10381,16 +10187,16 @@ intrinsics: - "vfma{neon_type.no}" - - a - b - - FnCall: ["vdup{neon_type.N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + - FnCall: ["vdup{neon_type.N}", [{FnCall: ['vget{neon_type.lane_nox}', [c], [LANE]]}]] - name: "vfma_laneq_f64" doc: "Floating-point fused multiply-add to accumulator" arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -10401,7 +10207,7 @@ intrinsics: - "vfma{neon_type[0].no}" - - a - b - - FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + - FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]] - name: "vfmaq_lane_f64" doc: "Floating-point fused multiply-add to accumulator" @@ -10410,7 +10216,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmla, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -10421,16 +10227,16 @@ intrinsics: - "vfma{neon_type[0].no}" - - a - b - - FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + - FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]] - name: "vfma{type[2]}" doc: "Floating-point fused multiply-add to accumulator" arguments: ["a: {type[0]}", "b: {type[0]}", "c: {neon_type[1]}"] return_type: "{type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -10439,7 +10245,7 @@ intrinsics: - ["f64", float64x2_t, "d_laneq_f64", '1'] compose: - FnCall: [static_assert_uimm_bits!, ['LANE', "{type[3]}"]] - - Let: [c, "{type[0]}", {FnCall: [simd_extract!, [c, 'LANE as u32']]}] + - Let: [c, "{type[0]}", {FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}] - FnCall: ["fma{type[0]}", [b, c, a]] - name: "vfmad_lane_f64" @@ -10449,14 +10255,14 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: - ["f64", float64x1_t] compose: - FnCall: [static_assert!, ['LANE == 0']] - - Let: [c, "{type[0]}", {FnCall: [simd_extract!, [c, 'LANE as u32']]}] + - Let: [c, "{type[0]}", {FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}] - FnCall: [fmaf64, [b, c, a]] @@ -10481,7 +10287,7 @@ intrinsics: arguments: ["a: {type[0]}", "b: {type[0]}", "v: {neon_type[1]}"] return_type: "{type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-fp16 - *neon-unstable-f16 @@ -10493,7 +10299,7 @@ intrinsics: - ["f16", float16x8_t, 'q_f16', '3'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - - Let: [c, "{type[0]}", {FnCall: [simd_extract!, [v, 'LANE as u32']]}] + - Let: [c, "{type[0]}", {FnCall: ['vget{neon_type[1].lane_nox}', [v], [LANE]]}] - FnCall: ["vfmah_{type[0]}", [a, b, c]] - name: "vfmsh_lane{type[2]}" @@ -10501,7 +10307,7 @@ intrinsics: arguments: ["a: {type[0]}", "b: {type[0]}", "v: {neon_type[1]}"] return_type: "{type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-fp16 - *neon-unstable-f16 @@ -10513,7 +10319,7 @@ intrinsics: - ["f16", float16x8_t, 'q_f16', '3'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - - Let: [c, "{type[0]}", {FnCall: [simd_extract!, [v, 'LANE as u32']]}] + - Let: [c, "{type[0]}", {FnCall: ['vget{neon_type[1].lane_nox}', [v], [LANE]]}] - FnCall: ["vfmsh_{type[0]}", [a, b, c]] - name: "vfms_f64" @@ -10522,7 +10328,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - float64x1_t @@ -10536,7 +10342,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmls]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - float64x2_t @@ -10550,7 +10356,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - float64x1_t @@ -10565,7 +10371,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmls, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -10576,7 +10382,7 @@ intrinsics: - [float64x2_t, float64x2_t, '1', q_laneq_f64] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[2]}']] - - FnCall: ["vfms{neon_type[0].no}", [a, b, {FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]]}]] + - FnCall: ["vfms{neon_type[0].no}", [a, b, {FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]]}]] - name: "vfms_lane_f64" doc: "Floating-point fused multiply-subtract to accumulator" @@ -10585,30 +10391,30 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: - float64x1_t compose: - FnCall: [static_assert!, ['LANE == 0']] - - FnCall: ["vfms{neon_type.no}", [a, b, {FnCall: ["vdup{neon_type.N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]]}]] + - FnCall: ["vfms{neon_type.no}", [a, b, {FnCall: ["vdup{neon_type.N}", [{FnCall: ['vget{neon_type.lane_nox}', [c], [LANE]]}]]}]] - name: "vfms_laneq_f64" doc: "Floating-point fused multiply-subtract to accumulator" arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: - [float64x1_t, float64x2_t] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '1']] - - FnCall: ["vfms{neon_type[0].no}", [a, b, {FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]]}]] + - FnCall: ["vfms{neon_type[0].no}", [a, b, {FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]]}]] - name: "vfmsq_lane_f64" doc: "Floating-point fused multiply-subtract to accumulator" @@ -10617,23 +10423,23 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmls, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: - [float64x2_t, float64x1_t] compose: - FnCall: [static_assert!, ['LANE == 0']] - - FnCall: ["vfms{neon_type[0].no}", [a, b, {FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]]}]] + - FnCall: ["vfms{neon_type[0].no}", [a, b, {FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]]}]] - name: "vfms{type[2]}" doc: "Floating-point fused multiply-subtract to accumulator" arguments: ["a: {type[0]}", "b: {type[0]}", "c: {neon_type[1]}"] return_type: "{type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -10651,7 +10457,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmeq]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, uint32x2_t, 'f32x2', 'f32x2::new(0.0, 0.0)'] @@ -10685,18 +10491,18 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "u32", "s_f32"] - ["f64", "u64", "d_f64"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[1]}' - - FnCall: - "vceqz_{type[0]}" - - FnCall: ["vdup_n_{type[0]}", [a]] - - '0' + - - '0' - name: "vceqz{type[2]}" doc: "Floating-point compare bitwise equal to zero" @@ -10712,11 +10518,11 @@ intrinsics: - ["f16", "u16", "h_f16"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[1]}' - - FnCall: - "vceqz_{type[0]}" - - FnCall: ["vdup_n_{type[0]}", [a]] - - '0' + - - '0' - name: "vceqzd_{type[2]}" doc: "Compare bitwise equal to zero" @@ -10724,7 +10530,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i64", "u64", "s64"] @@ -10742,7 +10548,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmeq]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] @@ -10770,7 +10576,7 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmeq]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [uint8x8_t, uint8x8_t, u8x8, 'u8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] @@ -10794,7 +10600,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmhs]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - uint64x1_t @@ -10808,19 +10614,19 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vcge_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - FnCall: ["vdup_n_{type[1]}", [b]] - - '0' + - - '0' - name: "vcge{type[0]}" @@ -10837,12 +10643,12 @@ intrinsics: - ["h_f16", "f16", "u16"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vcge_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - FnCall: ["vdup_n_{type[1]}", [b]] - - '0' + - - '0' - name: "vcge{neon_type[0].no}" doc: "Floating-point compare greater than or equal" @@ -10850,7 +10656,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmge]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, uint64x1_t] @@ -10864,7 +10670,7 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["d_s64", "i64", "u64", s64] @@ -10883,7 +10689,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmhi]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - uint64x1_t @@ -10897,7 +10703,7 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s64", "i64", "u64"] @@ -10916,7 +10722,7 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmtst]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [uint64x1_t, u64x1, 'u64x1::new(0)'] @@ -10932,7 +10738,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmge]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, uint32x2_t, f32x2, 'f32x2::new(0.0, 0.0)'] @@ -10952,18 +10758,18 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vcgez_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - - '0' + - - '0' - name: "vcgez{type[0]}" @@ -10980,11 +10786,11 @@ intrinsics: - ["h_f16", "f16", "u16"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vcgez_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - - '0' + - - '0' - name: "vclezd_s64" doc: "Compare less than or equal to zero" @@ -10992,7 +10798,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i64", "u64"] @@ -11007,7 +10813,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i64", "u64", 's64'] @@ -11026,7 +10832,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmgt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] @@ -11050,7 +10856,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i64", "u64"] @@ -11067,7 +10873,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmgt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, uint32x2_t, f32x2, 'f32x2::new(0.0, 0.0)'] @@ -11084,18 +10890,18 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] compose: - FnCall: - - "simd_extract!" + - 'vget_lane_{type[2]}' - - FnCall: - "vcgtz_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - - '0' + - - '0' - name: "vcgtz{type[0]}" doc: "Floating-point compare greater than zero" @@ -11111,11 +10917,11 @@ intrinsics: - ["h_f16", "f16", "u16"] compose: - FnCall: - - "simd_extract!" + - 'vget_lane_{type[2]}' - - FnCall: - "vcgtz_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - - '0' + - - '0' - name: "vcvt{neon_type[1].no}_{neon_type[0]}" doc: "Floating-point convert to unsigned fixed-point, rounding toward zero" @@ -11123,7 +10929,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzu]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, uint64x1_t] @@ -11141,7 +10947,7 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, "f64"] @@ -11159,7 +10965,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -11171,7 +10977,7 @@ intrinsics: - - a - FnCall: - "transmute::" - - - FnCall: [simd_extract!, [b, 'LANE as u32']] + - - FnCall: ['vget{neon_type.lane_nox}', [b], [LANE]] - name: "vmulq_lane_f64" doc: "Floating-point multiply" @@ -11180,7 +10986,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -11190,7 +10996,7 @@ intrinsics: - FnCall: - simd_mul - - a - - FnCall: ["simd_shuffle!", [b, b, '[LANE as u32, LANE as u32]']] + - FnCall: [vdupq_lane_f64, [b], [LANE]] - name: "vmuld_lane_f64" doc: "Floating-point multiply" @@ -11199,14 +11005,14 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: - ["f64", float64x1_t] compose: - FnCall: [static_assert!, ['LANE == 0']] - - Let: [b, '{type[0]}', {FnCall: [simd_extract!, [b, 'LANE as u32']]}] + - Let: [b, '{type[0]}', {FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]]}] - Identifier: ['a * b', Symbol] - name: "vmul_laneq_f64" @@ -11216,7 +11022,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -11228,7 +11034,7 @@ intrinsics: - - a - FnCall: - "transmute::" - - - FnCall: [simd_extract!, [b, 'LANE as u32']] + - - FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]] - name: "vmulq_laneq_f64" doc: "Floating-point multiply" @@ -11237,7 +11043,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -11247,7 +11053,7 @@ intrinsics: - FnCall: - simd_mul - - a - - FnCall: [simd_shuffle!, [b, b, '[LANE as u32, LANE as u32]']] + - FnCall: [vdupq_laneq_f64, [b], [LANE]] # vmulq_laneq_f16 @@ -11264,14 +11070,14 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [float16x4_t, float16x8_t, '_lane', "[LANE as u32, LANE as u32, LANE as u32, LANE as u32]"] - - [float16x8_t, float16x8_t, 'q_lane', "[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]"] + - [float16x4_t, float16x8_t, '_lane'] + - [float16x8_t, float16x8_t, 'q_lane'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '3']] - FnCall: - simd_mul - - a - - FnCall: [simd_shuffle!, [b, b, "{type[3]}"]] + - FnCall: ['vdup{neon_type[0].laneq_nox}', [b], [LANE]] - name: "vmul{type[1]}_{type[0]}" @@ -11297,7 +11103,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -11306,7 +11112,7 @@ intrinsics: - ["f64", float64x2_t, "d_laneq_f64", '1'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - - Let: [b, '{type[0]}', {FnCall: [simd_extract!, [b, 'LANE as u32']]}] + - Let: [b, '{type[0]}', {FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]]}] - Identifier: ['a * b', Symbol] @@ -11327,7 +11133,7 @@ intrinsics: - ["f16", float16x8_t, "h_laneq_f16", '3'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - - Let: [b, '{type[0]}', {FnCall: [simd_extract!, [b, 'LANE as u32']]}] + - Let: [b, '{type[0]}', {FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]]}] - Identifier: ['a * b', Symbol] @@ -11338,7 +11144,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [srshr, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -11353,8 +11159,8 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlsl2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlsl2]]}]] + - *neon-stable safety: safe types: - [int32x4_t, int16x8_t, "i16"] @@ -11367,8 +11173,8 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlsl2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlsl2]]}]] + - *neon-stable safety: safe types: - [uint32x4_t, uint16x8_t, "u16"] @@ -11381,46 +11187,46 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlsl2, 'LANE = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlsl2, 'LANE = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: - - [int32x4_t, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int32x4_t, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int64x2_t, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int64x2_t, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int32x4_t, int16x8_t, int16x4_t, '2'] + - [int32x4_t, int16x8_t, int16x8_t, '3'] + - [int64x2_t, int32x4_t, int32x2_t, '1'] + - [int64x2_t, int32x4_t, int32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: - "vmlsl_high_{neon_type[1]}" - - a - b - - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + - FnCall: ['vdupq_lane{neon_type[2].no}', [c], [LANE]] - name: "vmlsl_high_lane{neon_type[2].no}" doc: "Multiply-subtract long" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlsl2, 'LANE = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlsl2, 'LANE = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: - - [uint32x4_t, uint16x8_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint32x4_t, uint16x8_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint64x2_t, uint32x4_t, uint32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint64x2_t, uint32x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint32x4_t, uint16x8_t, uint16x4_t, '2'] + - [uint32x4_t, uint16x8_t, uint16x8_t, '3'] + - [uint64x2_t, uint32x4_t, uint32x2_t, '1'] + - [uint64x2_t, uint32x4_t, uint32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: - "vmlsl_high_{neon_type[1]}" - - a - b - - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + - FnCall: ['vdupq_lane{neon_type[2].no}', [c], [LANE]] - name: "vclt{neon_type[0].no}" doc: "Floating-point compare less than" @@ -11428,7 +11234,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmgt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, uint64x1_t] @@ -11442,19 +11248,19 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "u32", 's_f32'] - ["f64", "u64", 'd_f64'] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[1]}' - - FnCall: - "vclt_{type[0]}" - - FnCall: ["vdup_n_{type[0]}", [a]] - FnCall: ["vdup_n_{type[0]}", [b]] - - '0' + - - '0' - name: "vclt{type[2]}" @@ -11471,29 +11277,38 @@ intrinsics: - ["f16", "u16", 'h_f16'] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[1]}' - - FnCall: - "vclt_{type[0]}" - - FnCall: ["vdup_n_{type[0]}", [a]] - FnCall: ["vdup_n_{type[0]}", [b]] - - '0' + - - '0' - - name: "vabdl_high_{neon_type[0]}" - doc: "Unsigned Absolute difference Long" + - name: "vabdl_high{neon_type[0].noq}" + doc: Unsigned Absolute difference Long arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] return_type: "{neon_type[1]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uabdl2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uabdl2]]}]] safety: safe types: - - [uint8x16_t, uint16x8_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x8_t, uint32x4_t, uint16x4_t, '[4, 5, 6, 7]'] - - [uint32x4_t, uint64x2_t, uint32x2_t, '[2, 3]'] + - [uint8x16_t, uint16x8_t] + - [uint16x8_t, uint32x4_t] + - [uint32x4_t, uint64x2_t] compose: - - Let: [c, "{neon_type[2]}", {FnCall: [simd_shuffle!, [a, a, "{type[3]}"]]}] - - Let: [d, "{neon_type[2]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}] - - FnCall: [simd_cast, [{FnCall: ["vabd_{neon_type[0]}", [c, d]]}]] + - Let: + - c + - FnCall: ['vget_high_{neon_type[0]}', [a]] + - Let: + - d + - FnCall: ['vget_high_{neon_type[0]}', [b]] + - FnCall: + - simd_cast + - - FnCall: + - "vabd_{neon_type[0]}" + - - c + - d - name: "vfms_n_f64" doc: "Floating-point fused Multiply-subtract to accumulator(vector)" @@ -11501,7 +11316,7 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, "f64"] @@ -11518,7 +11333,7 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmls]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x2_t, "f64"] @@ -11559,8 +11374,9 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fminnmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe + big_endian_inverse: true types: - ['s_f32', float32x2_t, "f32"] - ['qd_f64', float64x2_t, "f64"] @@ -11577,8 +11393,9 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmaxnmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe + big_endian_inverse: true types: - ['s_f32', float32x2_t, "f32"] - ['qd_f64', float64x2_t, "f64"] @@ -11595,7 +11412,7 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s64", "i64", "u64"] @@ -11615,7 +11432,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmulh, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -11630,14 +11447,14 @@ intrinsics: - - a - FnCall: - "vdup{neon_type[0].N}" - - - FnCall: [simd_extract!, [b, 'LANE as u32']] + - - FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]] - name: "vqabs{type[2]}" doc: "Signed saturating absolute value" arguments: ["a: {type[0]}"] return_type: "{type[0]}" attr: - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sqabs]]}]] safety: safe types: @@ -11645,16 +11462,16 @@ intrinsics: - ["i16", "s16", 'h_s16'] compose: - FnCall: - - "simd_extract!" + - 'vget_lane_{type[0]}' - - FnCall: ["vqabs_{type[1]}", [{FnCall: ["vdup_n_{type[1]}", [a]]}]] - - '0' + - - '0' - name: "vqabs{type[1]}" doc: "Signed saturating absolute value" arguments: ["a: {type[0]}"] return_type: "{type[0]}" attr: - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sqabs]]}]] safety: safe types: @@ -11672,8 +11489,8 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smull2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smull2]]}]] + - *neon-stable safety: safe types: - [int16x8_t, "i16", int32x4_t] @@ -11689,8 +11506,8 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umull2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umull2]]}]] + - *neon-stable safety: safe types: - [uint16x8_t, "u16", uint32x4_t] @@ -11706,44 +11523,44 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smull2, 'LANE = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smull2, 'LANE = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: - - [int16x8_t, int16x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int16x8_t, int16x8_t, int32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int32x4_t, int32x2_t, int64x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int32x4_t, int32x4_t, int64x2_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int16x8_t, int16x4_t, int32x4_t, '2'] + - [int16x8_t, int16x8_t, int32x4_t, '3'] + - [int32x4_t, int32x2_t, int64x2_t, '1'] + - [int32x4_t, int32x4_t, int64x2_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] - FnCall: - "vmull_high_{neon_type[0]}" - - a - - FnCall: [simd_shuffle!, [b, b, '{type[4]}']] + - FnCall: ['vdupq_lane{neon_type[1].no}', [b], [LANE]] - name: "vmull_high_lane{neon_type[1].no}" doc: "Multiply long" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umull2, 'LANE = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umull2, 'LANE = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: - - [uint16x8_t, uint16x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint16x8_t, uint16x8_t, uint32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint32x4_t, uint32x2_t, uint64x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint32x4_t, uint32x4_t, uint64x2_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint16x8_t, uint16x4_t, uint32x4_t, '2'] + - [uint16x8_t, uint16x8_t, uint32x4_t, '3'] + - [uint32x4_t, uint32x2_t, uint64x2_t, '1'] + - [uint32x4_t, uint32x4_t, uint64x2_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] - FnCall: - "vmull_high_{neon_type[0]}" - - a - - FnCall: [simd_shuffle!, [b, b, '{type[4]}']] + - FnCall: ['vdupq_lane{neon_type[1].no}', [b], [LANE]] - name: "vrsqrte{neon_type.no}" doc: "Reciprocal square-root estimate." @@ -11751,7 +11568,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frsqrte]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - float64x1_t @@ -11769,7 +11586,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frsqrte]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32"] @@ -11808,8 +11625,9 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fminnmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe + big_endian_inverse: true types: - float32x2_t - float64x2_t @@ -11828,7 +11646,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshlu, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -11839,11 +11657,11 @@ intrinsics: compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]] - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vqshlu_n_{type[4]}::" - - FnCall: ["vdup_n_{type[4]}", [a]] - - '0' + - - '0' - name: "vcvta{neon_type[1].no}_{neon_type[0]}" doc: "Floating-point convert to unsigned integer, rounding to nearest with ties to away" @@ -11851,7 +11669,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtau]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, uint32x2_t] @@ -11893,7 +11711,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzs]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, int64x1_t] @@ -11916,6 +11734,7 @@ intrinsics: - *target-not-arm64ec safety: safe types: + - ["f16", "i16", 'h'] - ["f16", "i32", 'h'] - ["f16", "i64", 'h'] compose: @@ -11926,22 +11745,6 @@ intrinsics: - link: "llvm.aarch64.neon.fcvtms.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - name: "vcvtm{type[2]}_{type[1]}_{type[0]}" - doc: "Floating-point convert to integer, rounding towards minus infinity" - arguments: ["a: {type[0]}"] - return_type: "{type[1]}" - attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtms]]}]] - - *neon-fp16 - - *neon-unstable-f16 - - *target-not-arm64ec - safety: safe - types: - - ["f16", "i16", 'h', 'i32'] - compose: - - 'vcvtmh_{type[3]}_f16(a) as i16' - - - name: "vcvtm{type[2]}_{type[1]}_{type[0]}" doc: "Floating-point convert to unsigned integer, rounding towards minus infinity" arguments: ["a: {type[0]}"] @@ -11953,6 +11756,7 @@ intrinsics: - *target-not-arm64ec safety: safe types: + - ["f16", "u16", 'h'] - ["f16", "u32", 'h'] - ["f16", "u64", 'h'] compose: @@ -11963,28 +11767,13 @@ intrinsics: - link: "llvm.aarch64.neon.fcvtmu.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - name: "vcvtm{type[2]}_{type[1]}_{type[0]}" - doc: "Floating-point convert to integer, rounding towards minus infinity" - arguments: ["a: {type[0]}"] - return_type: "{type[1]}" - attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtmu]]}]] - - *neon-fp16 - - *neon-unstable-f16 - - *target-not-arm64ec - safety: safe - types: - - ["f16", "u16", 'h', 'u32'] - compose: - - 'vcvtmh_{type[3]}_f16(a) as u16' - - name: "vmlal_high_n_{neon_type[1]}" doc: "Multiply-add long" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlal2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlal2]]}]] + - *neon-stable safety: safe types: - [int32x4_t, int16x8_t, "i16"] @@ -12001,8 +11790,8 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlal2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlal2]]}]] + - *neon-stable safety: safe types: - [uint32x4_t, uint16x8_t, "u16"] @@ -12019,38 +11808,38 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlal2, 'LANE = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlal2, 'LANE = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: - - [int32x4_t, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int32x4_t, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int64x2_t, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int64x2_t, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int32x4_t, int16x8_t, int16x4_t, '2'] + - [int32x4_t, int16x8_t, int16x8_t, '3'] + - [int64x2_t, int32x4_t, int32x2_t, '1'] + - [int64x2_t, int32x4_t, int32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - - FnCall: ['vmlal_high_{neon_type[2]}', [a, b, {FnCall: [simd_shuffle!, [c, c, '{type[4]}']]}]] + - FnCall: ['vmlal_high_{neon_type[2]}', [a, b, {FnCall: ['vdupq_lane{neon_type[2].no}', [c], [LANE]]}]] - name: "vmlal_high_lane{neon_type[2].no}" doc: "Multiply-add long" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlal2, 'LANE = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlal2, 'LANE = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: - - [uint32x4_t, uint16x8_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint32x4_t, uint16x8_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint64x2_t, uint32x4_t, uint32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint64x2_t, uint32x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint32x4_t, uint16x8_t, uint16x4_t, '2'] + - [uint32x4_t, uint16x8_t, uint16x8_t, '3'] + - [uint64x2_t, uint32x4_t, uint32x2_t, '1'] + - [uint64x2_t, uint32x4_t, uint32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - - FnCall: ['vmlal_high_{neon_type[2]}', [a, b, {FnCall: [simd_shuffle!, [c, c, '{type[4]}']]}]] + - FnCall: ['vmlal_high_{neon_type[2]}', [a, b, {FnCall: ['vdupq_lane{neon_type[2].no}', [c], [LANE]]}]] - name: "vrsrad_n_u64" doc: "Unsigned rounding shift right and accumulate." @@ -12059,7 +11848,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [urshr, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -12075,7 +11864,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmhs]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - uint64x1_t @@ -12089,7 +11878,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld4r]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: unsafe: [neon] types: @@ -12112,7 +11901,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld4r]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: unsafe: [neon] types: @@ -12129,7 +11918,7 @@ intrinsics: attr: - FnCall: [target_feature, ['enable = "neon,aes"']] - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld4r]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: unsafe: [neon] types: @@ -12145,21 +11934,29 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [int8x8_t, int8x8x4_t] + - [int8x8_t, 'int8x8x4_t', 'int8x16x2', 'int8x8', 'i8x8::splat(32)'] compose: + - Let: + - x + - FnCall: + - '{type[2]}_t' + - - FnCall: ['vcombine{neon_type[0].no}', ['b.0', 'b.1']] + - FnCall: ['vcombine{neon_type[0].no}', ['b.2', 'b.3']] - FnCall: - - "vqtbx2" - - - FnCall: [transmute, [a]] - - FnCall: - - transmute - - - FnCall: ["vcombine{neon_type[0].noq}", ["b.0", "b.1"]] - - FnCall: - - transmute - - - FnCall: ["vcombine{neon_type[0].noq}", ["b.2", "b.3"]] - - FnCall: [transmute, [c]] + - simd_select + - - FnCall: + - "simd_lt::<{type[3]}_t, int8x8_t>" + - - c + - FnCall: [transmute, ["{type[4]}"]] + - FnCall: + - 'vqtbx2{neon_type[0].no}' + - - a + - x + - FnCall: ['vreinterpret_u8{neon_type[0].no}', [c]] + - a - name: "vtbx4{neon_type[0].no}" doc: "Extended table look-up" @@ -12167,24 +11964,30 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [uint8x8_t, uint8x8x4_t, uint8x8_t] - - [poly8x8_t, poly8x8x4_t, uint8x8_t] + - [uint8x8_t, 'uint8x8x4_t', 'uint8x8_t', 'uint8x16x2', 'uint8x8', 'u8x8::splat(32)'] + - [poly8x8_t, 'poly8x8x4_t', 'uint8x8_t', 'poly8x16x2', 'uint8x8', 'u8x8::splat(32)'] compose: + - Let: + - x + - FnCall: + - '{type[3]}_t' + - - FnCall: ['vcombine{neon_type[0].no}', ['b.0', 'b.1']] + - FnCall: ['vcombine{neon_type[0].no}', ['b.2', 'b.3']] - FnCall: - - transmute - - - FnCall: - - "vqtbx2" - - - FnCall: [transmute, [a]] - - FnCall: - - transmute - - - FnCall: ["vcombine{neon_type[0].noq}", ["b.0", "b.1"]] - - FnCall: - - transmute - - - FnCall: ["vcombine{neon_type[0].noq}", ["b.2", "b.3"]] - - c + - simd_select + - - FnCall: + - "simd_lt::<{type[4]}_t, int8x8_t>" + - - c + - FnCall: [transmute, ["{type[5]}"]] + - FnCall: + - 'vqtbx2{neon_type[0].no}' + - - a + - x + - c + - a - name: "vtbl1{neon_type[0].no}" doc: "Table look-up" @@ -12192,7 +11995,7 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int8x8_t, 'int8x8_t', 'unsafe {{ transmute(b) }}'] @@ -12207,26 +12010,21 @@ intrinsics: - 'unsafe {{ crate::mem::zeroed() }}' - Identifier: ['{type[2]}', Symbol] - - name: "vtbl2{neon_type[1].noq}" + - name: "vtbl2{neon_type[2].no}" doc: "Table look-up" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] - return_type: "{neon_type[1]}" + return_type: "{neon_type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [int8x8x2_t, 'int8x8_t'] + - ['int8x8x2_t', 'int8x8_t', 'int8x8_t'] compose: - FnCall: - - vqtbl1 - - - FnCall: - - transmute - - - FnCall: - - 'vcombine{neon_type[1].noq}' - - - 'a.0' - - 'a.1' - - FnCall: [transmute, [b]] + - 'vqtbl1{neon_type[2].noq}' + - - FnCall: ['vcombine{neon_type[2].noq}', ['a.0', 'a.1']] + - FnCall: ['vreinterpret_u8{neon_type[2].noq}', [b]] - name: "vtbl2{neon_type[2].no}" doc: "Table look-up" @@ -12234,127 +12032,107 @@ intrinsics: return_type: "{neon_type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [uint8x8x2_t, 'uint8x8_t', 'uint8x8_t'] - - [poly8x8x2_t, 'uint8x8_t', 'poly8x8_t'] + - ['uint8x8x2_t', 'uint8x8_t', 'uint8x8_t'] + - ['poly8x8x2_t', 'uint8x8_t', 'poly8x8_t'] compose: - FnCall: - - transmute - - - FnCall: - - vqtbl1 - - - FnCall: - - transmute - - - FnCall: - - 'vcombine{neon_type[2].noq}' - - - 'a.0' - - 'a.1' - - b + - 'vqtbl1{neon_type[2].noq}' + - - FnCall: ['vcombine{neon_type[2].noq}', ['a.0', 'a.1']] + - b - name: "vtbl3{neon_type[1].no}" doc: "Table look-up" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] - return_type: "{neon_type[1]}" + return_type: "{neon_type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [int8x8x3_t, 'int8x8_t', 'int8x16x2'] + - ['int8x8x3_t', 'int8x8_t', 'int8x8_t', 'int8x16x2'] compose: - Let: - - x - - FnCall: - - '{type[2]}_t' - - - FnCall: ['vcombine{neon_type[1].no}', ['a.0', 'a.1']] - - FnCall: ['vcombine{neon_type[1].no}', ['a.2', 'unsafe {{ crate::mem::zeroed() }}']] + - x + - FnCall: + - '{type[3]}_t' + - - FnCall: ['vcombine{neon_type[2].no}', ['a.0', 'a.1']] + - FnCall: ['vcombine{neon_type[2].no}', ['a.2', 'unsafe {{ crate::mem::zeroed() }}']] - FnCall: - - transmute - - - FnCall: - - vqtbl2 - - - FnCall: [transmute, ['x.0']] - - FnCall: [transmute, ['x.1']] - - FnCall: [transmute, [b]] + - 'vqtbl2{neon_type[2].no}' + - - x + - FnCall: ['vreinterpret_u8{neon_type[2].noq}', [b]] - - name: "vtbl3{neon_type[3].no}" + + - name: "vtbl3{neon_type[2].no}" doc: "Table look-up" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] - return_type: "{neon_type[3]}" + return_type: "{neon_type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [uint8x8x3_t, 'uint8x8_t', 'uint8x16x2', 'uint8x8_t'] - - [poly8x8x3_t, 'uint8x8_t', 'poly8x16x2', 'poly8x8_t'] - big_endian_inverse: true + - [uint8x8x3_t, 'uint8x8_t', 'uint8x8_t', 'uint8x16x2'] + - [poly8x8x3_t, 'uint8x8_t', 'poly8x8_t', 'poly8x16x2'] compose: - Let: - - x - - FnCall: - - '{type[2]}_t' - - - FnCall: ['vcombine{neon_type[3].no}', ['a.0', 'a.1']] - - FnCall: ['vcombine{neon_type[3].no}', ['a.2', 'unsafe {{ crate::mem::zeroed() }}']] - - FnCall: - - transmute - - - FnCall: - - vqtbl2 - - - FnCall: [transmute, ['x.0']] - - FnCall: [transmute, ['x.1']] - - b + - x + - FnCall: + - '{type[3]}_t' + - - FnCall: ['vcombine{neon_type[2].no}', ['a.0', 'a.1']] + - FnCall: ['vcombine{neon_type[2].no}', ['a.2', 'unsafe {{ crate::mem::zeroed() }}']] + - FnCall: + - 'vqtbl2{neon_type[2].no}' + - - x + - b - - name: "vtbl4{neon_type[1].no}" + - name: "vtbl4{neon_type[2].no}" doc: "Table look-up" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] - return_type: "{neon_type[1]}" + return_type: "{neon_type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [int8x8x4_t, 'int8x8_t', 'int8x16x2'] + - ['int8x8x4_t', 'int8x8_t', 'int8x8_t', 'int8x16x2'] compose: - Let: - - x - - FnCall: - - '{type[2]}_t' - - - FnCall: ['vcombine{neon_type[1].no}', ['a.0', 'a.1']] - - FnCall: ['vcombine{neon_type[1].no}', ['a.2', 'a.3']] + - x + - FnCall: + - '{type[3]}_t' + - - FnCall: ['vcombine{neon_type[1].no}', ['a.0', 'a.1']] + - FnCall: ['vcombine{neon_type[1].no}', ['a.2', 'a.3']] - FnCall: - - transmute - - - FnCall: - - 'vqtbl2' - - - FnCall: [transmute, ['x.0']] - - FnCall: [transmute, ['x.1']] - - FnCall: [transmute, [b]] + - 'vqtbl2{neon_type[2].no}' + - - x + - FnCall: ['vreinterpret_u8{neon_type[2].noq}', [b]] - - name: "vtbl4{neon_type[3].no}" + - name: "vtbl4{neon_type[2].no}" doc: "Table look-up" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] - return_type: "{neon_type[3]}" + return_type: "{neon_type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [uint8x8x4_t, 'uint8x8_t', 'uint8x16x2', 'uint8x8_t'] - - [poly8x8x4_t, 'uint8x8_t', 'poly8x16x2', 'poly8x8_t'] - big_endian_inverse: true + - [uint8x8x4_t, 'uint8x8_t', 'uint8x8_t', 'uint8x16x2'] + - [poly8x8x4_t, 'uint8x8_t', 'poly8x8_t', 'poly8x16x2'] compose: - Let: - - x - - FnCall: - - '{type[2]}_t' - - - FnCall: ['vcombine{neon_type[3].no}', ['a.0', 'a.1']] - - FnCall: ['vcombine{neon_type[3].no}', ['a.2', 'a.3']] - - FnCall: - - transmute - - - FnCall: - - 'vqtbl2' - - - FnCall: [transmute, ['x.0']] - - FnCall: [transmute, ['x.1']] - - b + - x + - FnCall: + - '{type[3]}_t' + - - FnCall: ['vcombine{neon_type[2].no}', ['a.0', 'a.1']] + - FnCall: ['vcombine{neon_type[2].no}', ['a.2', 'a.3']] + - FnCall: + - 'vqtbl2{neon_type[2].no}' + - - x + - b - name: "vqtbx1{neon_type[0].no}" doc: "Extended table look-up" @@ -12362,8 +12140,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe + big_endian_inverse: true types: - [int8x8_t, int8x16_t, uint8x8_t, vqtbx1] - [int8x16_t, int8x16_t, uint8x16_t, vqtbx1q] @@ -12376,14 +12155,14 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [uint8x8_t, "uint8x16_t", uint8x8_t, "vqtbx1", "_u8"] - [poly8x8_t, "poly8x16_t", uint8x8_t, "vqtbx1", "_p8"] - [uint8x16_t, "uint8x16_t", uint8x16_t, "vqtbx1q", "q_u8"] - [poly8x16_t, "poly8x16_t", uint8x16_t, "vqtbx1q", "q_p8"] - big_endian_inverse: false + big_endian_inverse: true compose: - FnCall: - transmute @@ -12399,29 +12178,48 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [int8x8_t, "int8x8_t", "transmute(c)", "i8x8::splat(8)", "int8x8"] - - [uint8x8_t, "uint8x8_t", "c", "u8x8::splat(8)", "uint8x8"] - - [poly8x8_t, "uint8x8_t", "c", "u8x8::splat(8)", "uint8x8"] + - [int8x8_t, "int8x8_t", "int8x8", "i8x8::splat(8)"] compose: - FnCall: - - simd_select - - - FnCall: - - "simd_lt::<{type[4]}_t, int8x8_t>" - - - c - - FnCall: [transmute, ["{type[3]}"]] - - FnCall: - - transmute - - - FnCall: - - "vqtbx1" - - - "transmute(a)" - - FnCall: - - transmute - - - FnCall: ["vcombine{neon_type[0].no}", [b, "crate::mem::zeroed()"]] - - "{type[2]}" - - a + - simd_select + - - FnCall: + - "simd_lt::<{type[2]}_t, int8x8_t>" + - - c + - FnCall: [transmute, ["{type[3]}"]] + - FnCall: + - 'vqtbx1{neon_type[0].no}' + - - a + - FnCall: ['vcombine{neon_type[0].no}', [b, 'crate::mem::zeroed()']] + - FnCall: ['vreinterpret_u8{neon_type[0].no}', [c]] + - a + + - name: "vtbx1{neon_type[0].no}" + doc: "Extended table look-up" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] + - *neon-stable + safety: safe + types: + - [uint8x8_t, "uint8x8_t", "uint8x8", "u8x8::splat(8)"] + - [poly8x8_t, "uint8x8_t", "uint8x8", "u8x8::splat(8)"] + compose: + - FnCall: + - simd_select + - - FnCall: + - "simd_lt::<{type[2]}_t, int8x8_t>" + - - c + - FnCall: [transmute, ["{type[3]}"]] + - FnCall: + - 'vqtbx1{neon_type[0].no}' + - - a + - FnCall: ['vcombine{neon_type[0].no}', [b, 'crate::mem::zeroed()']] + - c + - a - name: "vtbx2{neon_type[0].no}" doc: "Extended table look-up" @@ -12429,18 +12227,23 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [int8x8_t, 'int8x8x2_t'] + - [int8x8_t, 'int8x8x2_t', 'int8x8', 'i8x8::splat(16)'] compose: - FnCall: - - vqtbx1 - - - FnCall: [transmute, [a]] - - FnCall: - - transmute - - - FnCall: ["vcombine{neon_type[0].no}", ['b.0', 'b.1']] - - FnCall: [transmute, [c]] + - simd_select + - - FnCall: + - "simd_lt::<{type[2]}_t, int8x8_t>" + - - c + - FnCall: [transmute, ["{type[3]}"]] + - FnCall: + - 'vqtbx1{neon_type[0].no}' + - - a + - FnCall: ["vcombine{neon_type[0].no}", ['b.0', 'b.1']] + - FnCall: ['vreinterpret_u8{neon_type[0].no}', [c]] + - a - name: "vtbx2{neon_type[0].no}" doc: "Extended table look-up" @@ -12448,21 +12251,24 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [uint8x8_t, 'uint8x8x2_t', uint8x8_t] - - [poly8x8_t, 'poly8x8x2_t', uint8x8_t] + - [uint8x8_t, 'uint8x8x2_t', uint8x8_t, 'uint8x8', 'u8x8::splat(16)'] + - [poly8x8_t, 'poly8x8x2_t', uint8x8_t, 'uint8x8', 'u8x8::splat(16)'] compose: - FnCall: - - transmute - - - FnCall: - - vqtbx1 - - - FnCall: [transmute, [a]] - - FnCall: - - transmute - - - FnCall: ["vcombine{neon_type[0].no}", ['b.0', 'b.1']] - - c + - simd_select + - - FnCall: + - "simd_lt::<{type[3]}_t, int8x8_t>" + - - c + - FnCall: [transmute, ["{type[4]}"]] + - FnCall: + - 'vqtbx1{neon_type[0].no}' + - - a + - FnCall: ["vcombine{neon_type[0].no}", ['b.0', 'b.1']] + - c + - a - name: "vtbx3{neon_type[0].no}" doc: "Extended table look-up" @@ -12470,34 +12276,29 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [int8x8_t, 'int8x8x3_t', 'int8x16x2', 'i8x8::splat(24)', 'int8x8'] + - [int8x8_t, 'int8x8x3_t', 'int8x16x2', 'int8x8', 'i8x8::splat(24)'] compose: - Let: - - x - - FnCall: - - '{type[2]}_t' - - - FnCall: ['vcombine{neon_type[0].no}', ['b.0', 'b.1']] - - FnCall: ['vcombine{neon_type[0].no}', ['b.2', 'unsafe {{ crate::mem::zeroed() }}']] + - x + - FnCall: + - '{type[2]}_t' + - - FnCall: ['vcombine{neon_type[0].no}', ['b.0', 'b.1']] + - FnCall: ['vcombine{neon_type[0].no}', ['b.2', 'unsafe {{ crate::mem::zeroed() }}']] - FnCall: - - transmute - - - FnCall: - - simd_select - - - FnCall: - - 'simd_lt::<{type[4]}_t, int8x8_t>' - - - FnCall: [transmute, [c]] - - FnCall: [transmute, ['{type[3]}']] - - FnCall: - - transmute - - - FnCall: - - 'vqtbx2' - - - FnCall: [transmute, [a]] - - FnCall: [transmute, ['x.0']] - - FnCall: [transmute, ['x.1']] - - FnCall: [transmute, [c]] - - a + - simd_select + - - FnCall: + - "simd_lt::<{type[3]}_t, int8x8_t>" + - - c + - FnCall: [transmute, ["{type[4]}"]] + - FnCall: + - 'vqtbx2{neon_type[0].no}' + - - a + - x + - FnCall: ['vreinterpret_u8{neon_type[0].no}', [c]] + - a - name: "vtbx3{neon_type[0].no}" doc: "Extended table look-up" @@ -12505,12 +12306,11 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [uint8x8_t, 'uint8x8x3_t', 'uint8x16x2', 'u8x8::splat(24)', 'uint8x8'] - - [poly8x8_t, 'poly8x8x3_t', 'poly8x16x2', 'u8x8::splat(24)', 'poly8x8'] - big_endian_inverse: true + - [uint8x8_t, 'uint8x8x3_t', 'uint8x16x2', 'uint8x8', 'u8x8::splat(24)'] + - [poly8x8_t, 'poly8x8x3_t', 'poly8x16x2', 'uint8x8', 'u8x8::splat(24)'] compose: - Let: - x @@ -12519,22 +12319,17 @@ intrinsics: - - FnCall: ['vcombine{neon_type[0].no}', ['b.0', 'b.1']] - FnCall: ['vcombine{neon_type[0].no}', ['b.2', 'unsafe {{ crate::mem::zeroed() }}']] - FnCall: - - transmute - - - FnCall: - - simd_select - - - FnCall: - - 'simd_lt::<{type[4]}_t, int8x8_t>' - - - FnCall: [transmute, [c]] - - FnCall: [transmute, ['{type[3]}']] - - FnCall: - - transmute - - - FnCall: - - 'vqtbx2' - - - FnCall: [transmute, [a]] - - FnCall: [transmute, ['x.0']] - - FnCall: [transmute, ['x.1']] - - c - - a + - simd_select + - - FnCall: + - "simd_lt::<{type[3]}_t, int8x8_t>" + - - c + - FnCall: [transmute, ["{type[4]}"]] + - FnCall: + - 'vqtbx2{neon_type[0].no}' + - - a + - x + - c + - a - name: "vqtbl1{neon_type[3].no}" doc: "Table look-up" @@ -12542,8 +12337,9 @@ intrinsics: return_type: "{neon_type[3]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe + big_endian_inverse: true types: - ['int8x16_t', uint8x8_t, 'vqtbl1', 'int8x8_t'] - ['int8x16_t', uint8x16_t, 'vqtbl1q', 'int8x16_t'] @@ -12556,14 +12352,14 @@ intrinsics: return_type: "{neon_type[3]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ['uint8x16_t', uint8x8_t, 'vqtbl1', 'uint8x8_t'] - ['poly8x16_t', uint8x8_t, 'vqtbl1', 'poly8x8_t'] - ['uint8x16_t', uint8x16_t, 'vqtbl1q', 'uint8x16_t'] - ['poly8x16_t', uint8x16_t, 'vqtbl1q', 'poly8x16_t'] - big_endian_inverse: false + big_endian_inverse: true compose: - FnCall: - transmute @@ -12578,8 +12374,9 @@ intrinsics: return_type: "{neon_type[3]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe + big_endian_inverse: true types: - ['int8x16x2_t', uint8x8_t, 'vqtbl2', 'int8x8_t'] - ['int8x16x2_t', uint8x16_t, 'vqtbl2q', 'int8x16_t'] @@ -12592,7 +12389,8 @@ intrinsics: return_type: "{neon_type[3]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable + big_endian_inverse: true safety: safe types: - ['uint8x16x2_t', uint8x8_t, 'vqtbl2', 'uint8x8_t'] @@ -12614,8 +12412,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe + big_endian_inverse: true types: - [int8x8_t, 'int8x16x2_t', uint8x8_t, 'vqtbx2'] - [int8x16_t, 'int8x16x2_t', uint8x16_t, 'vqtbx2q'] @@ -12628,7 +12427,8 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable + big_endian_inverse: true safety: safe types: - [uint8x8_t, 'uint8x16x2_t', uint8x8_t, 'vqtbx2'] @@ -12651,7 +12451,8 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable + big_endian_inverse: true safety: safe types: - ['int8x8_t', 'int8x16x3_t', uint8x8_t, 'vqtbl3'] @@ -12665,7 +12466,8 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable + big_endian_inverse: true safety: safe types: - ['uint8x8_t', 'uint8x16x3_t', uint8x8_t, 'vqtbl3'] @@ -12688,8 +12490,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe + big_endian_inverse: true types: - [int8x8_t, 'int8x16x3_t', uint8x8_t, 'vqtbx3'] - [int8x16_t, 'int8x16x3_t', uint8x16_t, 'vqtbx3q'] @@ -12702,7 +12505,8 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable + big_endian_inverse: true safety: safe types: - [uint8x8_t, 'uint8x16x3_t', uint8x8_t, 'vqtbx3'] @@ -12726,7 +12530,8 @@ intrinsics: return_type: "{neon_type[3]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable + big_endian_inverse: true safety: safe types: - ['int8x16x4_t', uint8x8_t, 'vqtbl4', 'int8x8_t'] @@ -12740,7 +12545,8 @@ intrinsics: return_type: "{neon_type[3]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable + big_endian_inverse: true safety: safe types: - ['uint8x16x4_t', uint8x8_t, 'vqtbl4', 'uint8x8_t'] @@ -12764,8 +12570,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe + big_endian_inverse: true types: - [int8x8_t, 'int8x16x4_t', uint8x8_t, 'vqtbx4'] - [int8x16_t, 'int8x16x4_t', uint8x16_t, 'vqtbx4q'] @@ -12778,7 +12585,8 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable + big_endian_inverse: true safety: safe types: - [uint8x8_t, 'uint8x16x4_t', uint8x8_t, 'vqtbx4'] @@ -12804,7 +12612,7 @@ intrinsics: return_type: "{neon_type[3]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["vqtbl1", "int8x16_t", "uint8x8_t", "int8x8_t"] @@ -12823,7 +12631,7 @@ intrinsics: return_type: "{neon_type[3]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["vqtbl2", "int8x16_t", "uint8x8_t", "int8x8_t"] @@ -12842,7 +12650,7 @@ intrinsics: return_type: "{neon_type[3]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["vqtbl3", int8x16_t, uint8x8_t, int8x8_t] @@ -12861,7 +12669,7 @@ intrinsics: return_type: "{neon_type[3]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["vqtbl4", int8x16_t, uint8x8_t, int8x8_t] @@ -12880,7 +12688,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [vqtbx1, "int8x8_t", "int8x16_t", "uint8x8_t"] @@ -12899,7 +12707,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [vqtbx2, "int8x8_t", "int8x16_t", "uint8x8_t"] @@ -12918,7 +12726,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [vqtbx3, "int8x8_t", "int8x16_t", "uint8x8_t"] @@ -12937,7 +12745,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [vqtbx4, "int8x8_t", "int8x16_t", "uint8x8_t"] @@ -12956,7 +12764,7 @@ intrinsics: attr: - FnCall: [target_feature, ['enable = "{type[2]}"']] - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ldr]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: unsafe: [neon] types: @@ -13023,7 +12831,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "{type[2]}"']] - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [str]]}]] - FnCall: [allow, ['clippy::cast_ptr_alignment']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: unsafe: [neon] types: @@ -13217,26 +13025,6 @@ intrinsics: - link: "llvm.aarch64.neon.usqadd.{neon_type[1]}" arch: aarch64,arm64ec - - name: "vpadd{neon_type.no}" - doc: "Add Pairwise" - arguments: ["a: {neon_type}", "b: {neon_type}"] - return_type: "{neon_type}" - attr: - - *neon-stable - assert_instr: [addp] - safety: safe - types: - - int8x16_t - - int16x8_t - - int32x4_t - - int64x2_t - compose: - - LLVMLink: - name: "vpadd{neon_type.no}" - links: - - link: "llvm.aarch64.neon.addp.{neon_type}" - arch: aarch64,arm64ec - - name: "vpadd{neon_type[0].no}" doc: "Add Pairwise" arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] @@ -13245,18 +13033,24 @@ intrinsics: - *neon-stable assert_instr: [addp] safety: safe + big_endian_inverse: true types: - - [uint8x16_t, int8x16_t] - - [uint16x8_t, int16x8_t] - - [uint32x4_t, int32x4_t] - - [uint64x2_t, int64x2_t] + - [int8x16_t, "16"] + - [int16x8_t, "8"] + - [int32x4_t, "4"] + - [int64x2_t, "2"] + - [uint8x16_t, "16"] + - [uint16x8_t, "8"] + - [uint32x4_t, "4"] + - [uint64x2_t, "2"] compose: - - FnCall: - - transmute - - - FnCall: - - 'vpadd{neon_type[1].no}' - - - FnCall: [transmute, [a]] - - FnCall: [transmute, [b]] + - Let: + - even + - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::even::<{type[1]}>()"]] + - Let: + - odd + - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::odd::<{type[1]}>()"]] + - FnCall: [simd_add, [even, odd]] - name: "vpaddd_s64" doc: "Add pairwise" @@ -13388,7 +13182,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.saddlv.i32.{neon_type[0]}" arch: aarch64,arm64ec - - Identifier: ["unsafe {{ _vaddlv{neon_type[0].no}(a) as i16 }}", Symbol] + - Identifier: ["_vaddlv{neon_type[0].no}(a) as i16", UnsafeSymbol] - name: "vaddlv{neon_type[0].no}" doc: "Unsigned Add Long across Vector" @@ -13408,7 +13202,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.uaddlv.i32.{neon_type[0]}" arch: aarch64,arm64ec - - Identifier: ["unsafe {{ _vaddlv{neon_type[0].no}(a) as u16 }}", Symbol] + - Identifier: ["_vaddlv{neon_type[0].no}(a) as u16", UnsafeSymbol] - name: "vmaxv{neon_type[0].no}" doc: "Horizontal vector max." @@ -13528,6 +13322,7 @@ intrinsics: - *neon-stable assert_instr: ['sminp'] safety: safe + big_endian_inverse: true types: - int8x16_t - int16x8_t @@ -13547,6 +13342,7 @@ intrinsics: - *neon-stable assert_instr: ['uminp'] safety: safe + big_endian_inverse: true types: - uint8x16_t - uint16x8_t @@ -13566,6 +13362,7 @@ intrinsics: - *neon-stable assert_instr: ['fminp'] safety: safe + big_endian_inverse: true types: - float32x4_t - float64x2_t @@ -13584,6 +13381,7 @@ intrinsics: - *neon-stable assert_instr: ['smaxp'] safety: safe + big_endian_inverse: true types: - int8x16_t - int16x8_t @@ -13603,6 +13401,7 @@ intrinsics: - *neon-stable assert_instr: ['umaxp'] safety: safe + big_endian_inverse: true types: - uint8x16_t - uint16x8_t @@ -13622,6 +13421,7 @@ intrinsics: - *neon-stable assert_instr: ['fmaxp'] safety: safe + big_endian_inverse: true types: - float32x4_t - float64x2_t @@ -13714,26 +13514,17 @@ intrinsics: static_defs: ['const N: i32'] safety: safe types: - - [int8x8_t, 'N >= 1 && N <= 8'] - - [int8x16_t, 'N >= 1 && N <= 8'] - - [int16x4_t, 'N >= 1 && N <= 16'] - - [int16x8_t, 'N >= 1 && N <= 16'] - - [int32x2_t, 'N >= 1 && N <= 32'] - - [int32x4_t, 'N >= 1 && N <= 32'] - - [int64x1_t, 'N >= 1 && N <= 64'] - - [int64x2_t, 'N >= 1 && N <= 64'] + - [int8x8_t, u8, '8', 'N >= 1 && N <= 8'] + - [int8x16_t, u8, '16', 'N >= 1 && N <= 8'] + - [int16x4_t, u16, '4', 'N >= 1 && N <= 16'] + - [int16x8_t, u16, '8', 'N >= 1 && N <= 16'] + - [int32x2_t, u32, '2', 'N >= 1 && N <= 32'] + - [int32x4_t, u32, '4', 'N >= 1 && N <= 32'] + - [int64x1_t, u64, '1', 'N >= 1 && N <= 64'] + - [int64x2_t, u64, '2', 'N >= 1 && N <= 64'] compose: - - FnCall: ['static_assert!', ['{type[1]}']] - - LLVMLink: - name: "vsri{neon_type[0].N}" - arguments: - - "a: {neon_type[0]}" - - "b: {neon_type[0]}" - - "n: i32" - links: - - link: "llvm.aarch64.neon.vsri.{neon_type[0]}" - arch: aarch64,arm64ec - - FnCall: ["_vsri{neon_type[0].N}", [a, b, N], [], true] + - FnCall: ['static_assert!', ['{type[3]}']] + - FnCall: ["super::shift_right_and_insert!", ['{type[1]}', '{type[2]}', N, a, b], [], true] - name: "vsri{neon_type[0].N}" doc: "Shift Right and Insert (immediate)" @@ -13785,6 +13576,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fmlal2] safety: safe + big_endian_inverse: true types: - [float32x2_t, float16x4_t, '_high_'] - [float32x4_t, float16x8_t, 'q_high_'] @@ -13796,7 +13588,7 @@ intrinsics: arch: aarch64,arm64ec - - name: "vfmlal{type[3]}{neon_type[1]}" + - name: "vfmlal{type[3]}_high_{neon_type[1]}" doc: "Floating-point fused Multiply-Add Long to accumulator (by element)." arguments: ["r: {neon_type[0]}", "a: {neon_type[1]}", "b: {neon_type[2]}"] return_type: "{neon_type[0]}" @@ -13810,18 +13602,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [float32x2_t, float16x4_t, float16x4_t, '_lane_high_', '_high_', '2'] - - [float32x2_t, float16x4_t, float16x8_t, '_laneq_high_', '_high_', '3'] - - [float32x4_t, float16x8_t, float16x4_t, 'q_lane_high_', 'q_high_', '2'] - - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq_high_', 'q_high_', '3'] + - [float32x2_t, float16x4_t, float16x4_t, '_lane', '_high_', '2'] + - [float32x2_t, float16x4_t, float16x8_t, '_laneq', '_high_', '3'] + - [float32x4_t, float16x8_t, float16x4_t, 'q_lane', 'q_high_', '2'] + - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq', 'q_high_', '3'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[5]}"]] - FnCall: - "vfmlal{type[4]}{neon_type[1]}" - - r - a - - FnCall: ["vdup{neon_type[1].N}", [{FnCall: [simd_extract!, [b, 'LANE as u32']]}]] - + - FnCall: ["vdup{type[3]}_{neon_type[2]}", [b], [LANE]] - name: "vfmlal{type[2]}{neon_type[1]}" doc: "Floating-point fused Multiply-Add Long to accumulator (vector)." @@ -13834,6 +13625,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fmlal] safety: safe + big_endian_inverse: true types: - [float32x2_t, float16x4_t, '_low_'] - [float32x4_t, float16x8_t, 'q_low_'] @@ -13845,7 +13637,7 @@ intrinsics: arch: aarch64,arm64ec - - name: "vfmlal{type[3]}{neon_type[1]}" + - name: "vfmlal{type[3]}_low_{neon_type[1]}" doc: "Floating-point fused Multiply-Add Long to accumulator (by element)." arguments: ["r: {neon_type[0]}", "a: {neon_type[1]}", "b: {neon_type[2]}"] return_type: "{neon_type[0]}" @@ -13859,18 +13651,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [float32x2_t, float16x4_t, float16x4_t, '_lane_low_', '_low_', '2'] - - [float32x2_t, float16x4_t, float16x8_t, '_laneq_low_', '_low_', '3'] - - [float32x4_t, float16x8_t, float16x4_t, 'q_lane_low_', 'q_low_', '2'] - - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq_low_', 'q_low_', '3'] + - [float32x2_t, float16x4_t, float16x4_t, '_lane', '_low_', '2'] + - [float32x2_t, float16x4_t, float16x8_t, '_laneq', '_low_', '3'] + - [float32x4_t, float16x8_t, float16x4_t, 'q_lane', 'q_low_', '2'] + - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq', 'q_low_', '3'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[5]}"]] - FnCall: - "vfmlal{type[4]}{neon_type[1]}" - - r - a - - FnCall: ["vdup{neon_type[1].N}", [{FnCall: [simd_extract!, [b, 'LANE as u32']]}]] - + - FnCall: ["vdup{type[3]}_{neon_type[2]}", [b], [LANE]] - name: "vfmlsl{type[2]}{neon_type[1]}" doc: "Floating-point fused Multiply-Subtract Long from accumulator (vector)." @@ -13883,6 +13674,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fmlsl2] safety: safe + big_endian_inverse: true types: - [float32x2_t, float16x4_t, '_high_'] - [float32x4_t, float16x8_t, 'q_high_'] @@ -13893,7 +13685,7 @@ intrinsics: - link: "llvm.aarch64.neon.fmlsl2.{neon_type[0]}.{neon_type[1]}" arch: aarch64,arm64ec - - name: "vfmlsl{type[3]}{neon_type[1]}" + - name: "vfmlsl{type[3]}_high_{neon_type[1]}" doc: "Floating-point fused Multiply-Subtract Long from accumulator (by element)." arguments: ["r: {neon_type[0]}", "a: {neon_type[1]}", "b: {neon_type[2]}"] return_type: "{neon_type[0]}" @@ -13907,18 +13699,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [float32x2_t, float16x4_t, float16x4_t, '_lane_high_', '_high_', '2'] - - [float32x2_t, float16x4_t, float16x8_t, '_laneq_high_', '_high_', '3'] - - [float32x4_t, float16x8_t, float16x4_t, 'q_lane_high_', 'q_high_', '2'] - - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq_high_', 'q_high_', '3'] + - [float32x2_t, float16x4_t, float16x4_t, '_lane', '_high_', '2'] + - [float32x2_t, float16x4_t, float16x8_t, '_laneq', '_high_', '3'] + - [float32x4_t, float16x8_t, float16x4_t, 'q_lane', 'q_high_', '2'] + - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq', 'q_high_', '3'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[5]}"]] - FnCall: - "vfmlsl{type[4]}{neon_type[1]}" - - r - a - - FnCall: ["vdup{neon_type[1].N}", [{FnCall: [simd_extract!, [b, 'LANE as u32']]}]] - + - FnCall: ["vdup{type[3]}_{neon_type[2]}", [b], [LANE]] - name: "vfmlsl{type[2]}{neon_type[1]}" doc: "Floating-point fused Multiply-Subtract Long from accumulator (vector)." @@ -13931,6 +13722,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fmlsl] safety: safe + big_endian_inverse: true types: - [float32x2_t, float16x4_t, '_low_'] - [float32x4_t, float16x8_t, 'q_low_'] @@ -13941,7 +13733,7 @@ intrinsics: - link: "llvm.aarch64.neon.fmlsl.{neon_type[0]}.{neon_type[1]}" arch: aarch64,arm64ec - - name: "vfmlsl{type[3]}{neon_type[1]}" + - name: "vfmlsl{type[3]}_low_{neon_type[1]}" doc: "Floating-point fused Multiply-Subtract Long from accumulator (by element)." arguments: ["r: {neon_type[0]}", "a: {neon_type[1]}", "b: {neon_type[2]}"] return_type: "{neon_type[0]}" @@ -13955,17 +13747,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [float32x2_t, float16x4_t, float16x4_t, '_lane_low_', '_low_', '2'] - - [float32x2_t, float16x4_t, float16x8_t, '_laneq_low_', '_low_', '3'] - - [float32x4_t, float16x8_t, float16x4_t, 'q_lane_low_', 'q_low_', '2'] - - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq_low_', 'q_low_', '3'] + - [float32x2_t, float16x4_t, float16x4_t, '_lane', '_low_', '2'] + - [float32x2_t, float16x4_t, float16x8_t, '_laneq', '_low_', '3'] + - [float32x4_t, float16x8_t, float16x4_t, 'q_lane', 'q_low_', '2'] + - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq', 'q_low_', '3'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[5]}"]] - FnCall: - "vfmlsl{type[4]}{neon_type[1]}" - - r - a - - FnCall: ["vdup{neon_type[1].N}", [{FnCall: [simd_extract!, [b, 'LANE as u32']]}]] + - FnCall: ["vdup{type[3]}_{neon_type[2]}", [b], [LANE]] - name: "vamax{neon_type.no}" doc: "Multi-vector floating-point absolute maximum" @@ -14159,7 +13951,7 @@ intrinsics: - 'b: {neon_type[1]}' - 'n: i32' links: - - link: "llvm.aarch64.neon.vluti4q.lane.{neon_type[1]}" + - link: "llvm.aarch64.neon.vluti4q.lane.{neon_type[0]}" arch: aarch64,arm64ec - FnCall: ['_vluti4{neon_type[0].lane_nox}', [a, b, LANE]] @@ -14210,7 +14002,7 @@ intrinsics: - 'b: {neon_type[1]}' - 'n: i32' links: - - link: "llvm.aarch64.neon.vluti4q.laneq.{neon_type[1]}" + - link: "llvm.aarch64.neon.vluti4q.laneq.{neon_type[0]}" arch: aarch64,arm64ec - FnCall: ['_vluti4{neon_type[0].laneq_nox}', [a, b, LANE]] @@ -14383,3 +14175,49 @@ intrinsics: links: - link: "llvm.aarch64.fjcvtzs" arch: aarch64,arm64ec + + - name: "{type[0]}" + doc: "Duplicate vector element to vector or scalar" + arguments: ["a: {type[1]}"] + return_type: "{neon_type[2]}" + attr: + - *neon-stable + assert_instr: ['{type[3]}'] + safety: safe + big_endian_inverse: true + types: + - ['vget_high_f64', 'float64x2_t', 'float64x1_t', 'nop', 'float64x1_t([simd_extract!(a, 1)])'] + - ['vget_low_f64', 'float64x2_t', 'float64x1_t', 'nop', 'float64x1_t([simd_extract!(a, 0)])'] + compose: + - Identifier: ['{type[4]}', UnsafeSymbol] + + - name: "vcombine{neon_type[0].noq}" + doc: Join two smaller vectors into a single larger vector + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-stable + assert_instr: [mov] + safety: safe + big_endian_inverse: true + types: + - [float64x1_t, float64x2_t, '[0, 1]'] + compose: + - FnCall: [simd_shuffle!, [a, b, '{type[2]}']] + + - name: "vgetq_lane_{type[1]}" + doc: "Duplicate vector element to vector or scalar" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - *neon-stable + - FnCall: [rustc_legacy_const_generics, ['1']] + assert_instr: [['nop', 'IMM5 = 0']] + safety: safe + big_endian_inverse: true + static_defs: ["const IMM5: i32"] + types: + - ['float64x2_t', 'f64'] + compose: + - FnCall: [static_assert_uimm_bits!, [IMM5, "1"]] + - FnCall: ['simd_extract!', [a, 'IMM5 as u32'], [] , true] diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml index 52748a4cc056d..7a7656e4c14b3 100644 --- a/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml +++ b/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml @@ -10,9 +10,13 @@ auto_big_endian: true neon-stable: &neon-stable FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] -# #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +# #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] neon-stable-fp16: &neon-stable-fp16 - FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "CURRENT_RUSTC_VERSION"']] + FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "1.94.0"']] + +# #[stable(feature = "stdarch_neon_dotprod", since = "1.98.0")] +neon-stable-dotprod: &neon-stable-dotprod + FnCall: [stable, ['feature = "stdarch_neon_dotprod"', 'since = "1.98.0"']] # #[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] neon-cfg-arm-unstable: &neon-cfg-arm-unstable @@ -51,13 +55,29 @@ not-arm: ¬-arm neon-target-aarch64-arm64ec: &neon-target-aarch64-arm64ec FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]] +neon-target-aarch64-le: &neon-target-aarch64-le + FnCall: [all, [test, 'target_arch = "aarch64"', 'target_endian = "little"', {FnCall: [not, [windows]]}]] + +neon-target-aarch64-be: &neon-target-aarch64-be + FnCall: [all, [test, 'target_arch = "aarch64"', 'target_endian = "big"']] + +neon-target-arm64ec: &neon-target-arm64ec + FnCall: [all, [test, 'target_arch = "arm64ec"']] + +neon-target-aarch64-windows: &neon-target-aarch64-windows + FnCall: [all, [test, 'target_arch = "aarch64"', windows]] + # #[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] neon-not-arm-stable: &neon-not-arm-stable FnCall: [cfg_attr, [{ FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] -# #[cfg_attr(not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION"))] +# #[cfg_attr(not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "1.94.0"))] neon-not-arm-stable-fp16: &neon-not-arm-stable-fp16 - FnCall: [cfg_attr, [{ FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "CURRENT_RUSTC_VERSION"']]}]] + FnCall: [cfg_attr, [{ FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "1.94.0"']]}]] + +# #[cfg_attr(not(target_arch = "arm"), stable(feature = "stdarch_neon_dotprod", since = "1.98.0"))] +neon-not-arm-stable-dotprod: &neon-not-arm-stable-dotprod + FnCall: [cfg_attr, [{ FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "stdarch_neon_dotprod"', 'since = "1.98.0"']]}]] # #[cfg_attr(all(test, not(target_env = "msvc"))] msvc-disabled: &msvc-disabled @@ -104,6 +124,10 @@ aarch64-crc-stable: &aarch64-crc-stable neon-unstable-f16: &neon-unstable-f16 FnCall: [unstable, ['feature = "stdarch_neon_f16"', 'issue = "136306"']] +# all(target_endian = "little") +all-neon-target-aarch64-arm64ec-little-endian: &all-neon-target-aarch64-arm64ec-little-endian + FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}, 'target_endian = "little"']] + intrinsics: - name: "vand{neon_type.no}" doc: Vector bitwise and @@ -502,11 +526,11 @@ intrinsics: - ['h_f16', 'f16'] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[1]}' - - FnCall: - "vabs_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - - 0 + - - 0 - name: "vcgt{neon_type[0].no}" doc: "Compare signed greater than" @@ -1438,13 +1462,14 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - - [_lane_s8, int8x8_t, int8x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [q_lane_s8, int8x8_t, int8x16_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [_lane_u8, uint8x8_t, uint8x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [q_lane_u8, uint8x8_t, uint8x16_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [_lane_p8, poly8x8_t, poly8x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [q_lane_p8, poly8x8_t, poly8x16_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + - [_lane_s8, int8x8_t, int8x8_t, '3', '[N as u32; 8]'] + - [q_lane_s8, int8x8_t, int8x16_t, '3', '[N as u32; 16]'] + - [_lane_u8, uint8x8_t, uint8x8_t, '3', '[N as u32; 8]'] + - [q_lane_u8, uint8x8_t, uint8x16_t, '3', '[N as u32; 16]'] + - [_lane_p8, poly8x8_t, poly8x8_t, '3', '[N as u32; 8]'] + - [q_lane_p8, poly8x8_t, poly8x16_t, '3', '[N as u32; 16]'] compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]] - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]] @@ -1462,13 +1487,14 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - - [q_laneq_s8, int8x16_t, int8x16_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [_laneq_s8, int8x16_t, int8x8_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [q_laneq_u8, uint8x16_t, uint8x16_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [_laneq_u8, uint8x16_t, uint8x8_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [q_laneq_p8, poly8x16_t, poly8x16_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [_laneq_p8, poly8x16_t, poly8x8_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + - [q_laneq_s8, int8x16_t, int8x16_t, '4', '[N as u32; 16]'] + - [_laneq_s8, int8x16_t, int8x8_t, '4', '[N as u32; 8]'] + - [q_laneq_u8, uint8x16_t, uint8x16_t, '4', '[N as u32; 16]'] + - [_laneq_u8, uint8x16_t, uint8x8_t, '4', '[N as u32; 8]'] + - [q_laneq_p8, poly8x16_t, poly8x16_t, '4', '[N as u32; 16]'] + - [_laneq_p8, poly8x16_t, poly8x8_t, '4', '[N as u32; 8]'] compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]] - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]] @@ -1486,13 +1512,14 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - - [_lane_s16, int16x4_t, int16x4_t, '2', '[N as u32, N as u32, N as u32, N as u32]'] - - [q_lane_s16, int16x4_t, int16x8_t, '2', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [_lane_u16, uint16x4_t, uint16x4_t, '2', '[N as u32, N as u32, N as u32, N as u32]'] - - [q_lane_u16, uint16x4_t, uint16x8_t, '2', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [_lane_p16, poly16x4_t, poly16x4_t, '2', '[N as u32, N as u32, N as u32, N as u32]'] - - [q_lane_p16, poly16x4_t, poly16x8_t, '2', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + - [_lane_s16, int16x4_t, int16x4_t, '2', '[N as u32; 4]'] + - [q_lane_s16, int16x4_t, int16x8_t, '2', '[N as u32; 8]'] + - [_lane_u16, uint16x4_t, uint16x4_t, '2', '[N as u32; 4]'] + - [q_lane_u16, uint16x4_t, uint16x8_t, '2', '[N as u32; 8]'] + - [_lane_p16, poly16x4_t, poly16x4_t, '2', '[N as u32; 4]'] + - [q_lane_p16, poly16x4_t, poly16x8_t, '2', '[N as u32; 8]'] compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]] - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]] @@ -1510,13 +1537,14 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - - [q_laneq_s16, int16x8_t, int16x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [_laneq_s16, int16x8_t, int16x4_t, '3', '[N as u32, N as u32, N as u32, N as u32]'] - - [q_laneq_u16, uint16x8_t, uint16x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [_laneq_u16, uint16x8_t, uint16x4_t, '3', '[N as u32, N as u32, N as u32, N as u32]'] - - [q_laneq_p16, poly16x8_t, poly16x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [_laneq_p16, poly16x8_t, poly16x4_t, '3', '[N as u32, N as u32, N as u32, N as u32]'] + - [q_laneq_s16, int16x8_t, int16x8_t, '3', '[N as u32; 8]'] + - [_laneq_s16, int16x8_t, int16x4_t, '3', '[N as u32; 4]'] + - [q_laneq_u16, uint16x8_t, uint16x8_t, '3', '[N as u32; 8]'] + - [_laneq_u16, uint16x8_t, uint16x4_t, '3', '[N as u32; 4]'] + - [q_laneq_p16, poly16x8_t, poly16x8_t, '3', '[N as u32; 8]'] + - [_laneq_p16, poly16x8_t, poly16x4_t, '3', '[N as u32; 4]'] compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]] - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]] @@ -1537,9 +1565,10 @@ intrinsics: - *target-not-arm64ec static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - - [q_laneq_f16, float16x8_t, float16x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [_laneq_f16, float16x8_t, float16x4_t, '3', '[N as u32, N as u32, N as u32, N as u32]'] + - [q_laneq_f16, float16x8_t, float16x8_t, '3', '[N as u32; 8]'] + - [_laneq_f16, float16x8_t, float16x4_t, '3', '[N as u32; 4]'] compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]] - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]] @@ -1577,9 +1606,10 @@ intrinsics: - *target-not-arm64ec static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - - [_lane_f16, float16x4_t, float16x4_t, '2', '[N as u32, N as u32, N as u32, N as u32]'] - - [q_lane_f16, float16x4_t, float16x8_t, '2', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + - [_lane_f16, float16x4_t, float16x4_t, '2', '[N as u32; 4]'] + - [q_lane_f16, float16x4_t, float16x8_t, '2', '[N as u32; 8]'] compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]] - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]] @@ -1598,6 +1628,7 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - [_lane_s32, int32x2_t, int32x2_t, '1', '[N as u32, N as u32]'] - [q_lane_s32, int32x2_t, int32x4_t, '1', '[N as u32, N as u32, N as u32, N as u32]'] @@ -1622,6 +1653,7 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - [q_laneq_s32, int32x4_t, int32x4_t, '2', '[N as u32, N as u32, N as u32, N as u32]'] - [_laneq_s32, int32x4_t, int32x2_t, '2', '[N as u32, N as u32]'] @@ -1646,6 +1678,7 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - [q_laneq_s64, int64x2_t, '1', '[N as u32, N as u32]'] - [q_laneq_u64, uint64x2_t, '1', '[N as u32, N as u32]'] @@ -1666,6 +1699,7 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - [q_lane_s64, int64x1_t, int64x2_t] - [q_lane_u64, uint64x1_t, uint64x2_t] @@ -1712,13 +1746,13 @@ intrinsics: compose: - FnCall: [static_assert_uimm_bits!, [N, 1]] - FnCall: - - "transmute{type[3]}" - - - FnCall: [simd_extract!, [a, 'N as u32']] + - "transmute" + - - FnCall: ['vget{neon_type[1].lane_nox}', [a], [N]] - - name: "vext{neon_type[0].no}" + - name: "vext{neon_type.no}" doc: "Extract vector from pair of vectors" - arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[0]}" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vext.8"', 'N = 7']]}]] @@ -1728,21 +1762,22 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - - [int8x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }'] - - [int16x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }'] - - [uint8x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }'] - - [uint16x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }'] - - [poly8x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }'] - - [poly16x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }'] + - int8x8_t + - int16x8_t + - uint8x8_t + - uint16x8_t + - poly8x8_t + - poly16x8_t compose: - - Identifier: ["{type[1]}", Symbol] - - Identifier: ["{type[2]}", Symbol] + - FnCall: [static_assert_uimm_bits!, [N, 3]] + - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3, N as u32 + 4, N as u32 + 5, N as u32 + 6, N as u32 + 7]']] - - name: "vext{neon_type[0].no}" + - name: "vext{neon_type.no}" doc: "Extract vector from pair of vectors" - arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[0]}" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vext.8"', 'N = 15']]}]] @@ -1752,18 +1787,19 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - - [int8x16_t, ' static_assert_uimm_bits!(N, 4);', 'unsafe { match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), } }'] - - [uint8x16_t, ' static_assert_uimm_bits!(N, 4);', 'unsafe { match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), } }'] - - [poly8x16_t, ' static_assert_uimm_bits!(N, 4);', 'unsafe { match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), } }'] + - int8x16_t + - uint8x16_t + - poly8x16_t compose: - - Identifier: ["{type[1]}", Symbol] - - Identifier: ["{type[2]}", Symbol] + - FnCall: [static_assert_uimm_bits!, [N, 4]] + - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3, N as u32 + 4, N as u32 + 5, N as u32 + 6, N as u32 + 7, N as u32 + 8, N as u32 + 9, N as u32 + 10, N as u32 + 11, N as u32 + 12, N as u32 + 13, N as u32 + 14, N as u32 + 15]']] - - name: "vext{neon_type[0].no}" + - name: "vext{neon_type.no}" doc: "Extract vector from pair of vectors" - arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[0]}" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vext.8"', 'N = 3']]}]] @@ -1773,22 +1809,23 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - - [int16x4_t, 'static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }'] - - [int32x4_t, ' static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }'] - - [uint16x4_t, ' static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }'] - - [uint32x4_t, ' static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }'] - - [poly16x4_t, ' static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }'] - - [float32x4_t, ' static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }'] + - int16x4_t + - int32x4_t + - uint16x4_t + - uint32x4_t + - poly16x4_t + - float32x4_t compose: - - Identifier: ["{type[1]}", Symbol] - - Identifier: ["{type[2]}", Symbol] + - FnCall: [static_assert_uimm_bits!, [N, 2]] + - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]']] - - name: "vext{neon_type[0].no}" + - name: "vext{neon_type.no}" doc: "Extract vector from pair of vectors" - arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[0]}" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vext.8"', 'N = 3']]}]] @@ -1800,15 +1837,17 @@ intrinsics: - *target-not-arm64ec static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - - [float16x4_t, ' static_assert_uimm_bits!(N, 2); unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }'] + - float16x4_t compose: - - Identifier: ["{type[1]}", Symbol] + - FnCall: [static_assert_uimm_bits!, [N, 2]] + - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]']] - - name: "vext{neon_type[0].no}" + - name: "vext{neon_type.no}" doc: "Extract vector from pair of vectors" - arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[0]}" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vext.8"', 'N = 7']]}]] @@ -1820,17 +1859,19 @@ intrinsics: - *target-not-arm64ec static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - - [float16x8_t, ' static_assert_uimm_bits!(N, 3); unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }'] + - float16x8_t compose: - - Identifier: ["{type[1]}", Symbol] + - FnCall: [static_assert_uimm_bits!, [N, 3]] + - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3, N as u32 + 4, N as u32 + 5, N as u32 + 6, N as u32 + 7]']] - - name: "vext{neon_type[0].no}" + - name: "vext{neon_type.no}" doc: "Extract vector from pair of vectors" - arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[0]}" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vext.8"', 'N = 1']]}]] @@ -1840,18 +1881,19 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - - [int32x2_t, ' static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }'] - - [uint32x2_t, ' static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }'] - - [float32x2_t, ' static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }'] + - int32x2_t + - uint32x2_t + - float32x2_t compose: - - Identifier: ["{type[1]}", Symbol] - - Identifier: ["{type[2]}", Symbol] + - FnCall: [static_assert_uimm_bits!, [N, 1]] + - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1]']] - - name: "vext{neon_type[0].no}" + - name: "vext{neon_type.no}" doc: "Extract vector from pair of vectors" - arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[0]}" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vmov, 'N = 1']]}]] @@ -1861,12 +1903,13 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - - [int64x2_t, 'static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }'] - - [uint64x2_t, 'static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }'] + - int64x2_t + - uint64x2_t compose: - - Identifier: ["{type[1]}", Symbol] - - Identifier: ["{type[2]}", Symbol] + - FnCall: [static_assert_uimm_bits!, [N, 1]] + - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1]']] - name: "vmla{neon_type[0].no}" doc: "Multiply-add to accumulator" @@ -1986,17 +2029,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [int32x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int32x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int64x2_t, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [int64x2_t, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]'] + - [int32x4_t, int16x4_t, int16x4_t, '2'] + - [int32x4_t, int16x4_t, int16x8_t, '3'] + - [int64x2_t, int32x2_t, int32x2_t, '1'] + - [int64x2_t, int32x2_t, int32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] - FnCall: - "vmlal_{neon_type[1]}" - - a - b - - FnCall: [simd_shuffle!, [c, c, '{type[4]}']] + - FnCall: ['vdup_lane{neon_type[2].no}', [c], [LANE]] - name: "vmlal_lane{neon_type[2].no}" doc: "Vector widening multiply accumulate with scalar" @@ -2012,17 +2055,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [uint32x4_t, uint16x4_t, uint16x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint32x4_t, uint16x4_t, uint16x8_t, uint32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint64x2_t, uint32x2_t, uint32x2_t, uint64x2_t, '1', '[LANE as u32, LANE as u32]'] - - [uint64x2_t, uint32x2_t, uint32x4_t, uint64x2_t, '2', '[LANE as u32, LANE as u32]'] + - [uint32x4_t, uint16x4_t, uint16x4_t, '2'] + - [uint32x4_t, uint16x4_t, uint16x8_t, '3'] + - [uint64x2_t, uint32x2_t, uint32x2_t, '1'] + - [uint64x2_t, uint32x2_t, uint32x4_t, '2'] compose: - - FnCall: [static_assert_uimm_bits!, [LANE, "{type[4]}"]] + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] - FnCall: - "vmlal_{neon_type[1]}" - - a - b - - FnCall: [simd_shuffle!, [c, c, '{type[5]}']] + - FnCall: ['vdup_lane{neon_type[2].no}', [c], [LANE]] - name: "vmlal_{neon_type[1]}" doc: "Unsigned multiply-add long" @@ -2141,15 +2184,15 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [int32x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int32x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int32x4_t, int16x4_t, int16x4_t, '2'] + - [int32x4_t, int16x4_t, int16x8_t, '3'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: - "vmlsl_{neon_type[1]}" - - a - b - - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + - FnCall: ['vdup_lane{neon_type[2].no}', [c], [LANE]] - name: "vmlsl_lane{neon_type[2].no}" doc: "Vector widening multiply subtract with scalar" @@ -2165,15 +2208,15 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [int64x2_t, int32x2_t, int32x2_t, '[LANE as u32, LANE as u32]', '1'] - - [int64x2_t, int32x2_t, int32x4_t, '[LANE as u32, LANE as u32]', '2'] + - [int64x2_t, int32x2_t, int32x2_t, '1'] + - [int64x2_t, int32x2_t, int32x4_t, '2'] compose: - - FnCall: [static_assert_uimm_bits!, [LANE, "{type[4]}"]] + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] - FnCall: - "vmlsl_{neon_type[1]}" - - a - b - - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]] + - FnCall: ['vdup_lane{neon_type[2].no}', [c], [LANE]] - name: "vmlsl_lane{neon_type[2].no}" doc: "Vector widening multiply subtract with scalar" @@ -2189,17 +2232,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [uint32x4_t, uint16x4_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint32x4_t, uint16x4_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint64x2_t, uint32x2_t, uint32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [uint64x2_t, uint32x2_t, uint32x4_t, '2', '[LANE as u32, LANE as u32]'] + - [uint32x4_t, uint16x4_t, uint16x4_t, '2'] + - [uint32x4_t, uint16x4_t, uint16x8_t, '3'] + - [uint64x2_t, uint32x2_t, uint32x2_t, '1'] + - [uint64x2_t, uint32x2_t, uint32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] - FnCall: - "vmlsl_{neon_type[1]}" - - a - b - - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + - FnCall: ['vdup_lane{neon_type[2].no}', [c], [LANE]] - name: "vmlsl_{neon_type[1]}" doc: "Unsigned multiply-subtract long" @@ -2603,8 +2646,8 @@ intrinsics: return_type: "{neon_type[1]}" attr: - *neon-v7 - - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]] + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: @@ -2617,13 +2660,12 @@ intrinsics: - ["*const f32", float32x2x4_t] - ["*const f32", float32x4x4_t] compose: - - LLVMLink: - name: "vld1x{neon_type[1].tuple}.{neon_type[1]}" - links: - - link: "llvm.aarch64.neon.ld1x{neon_type[1].tuple}.v{neon_type[1].lane}f{neon_type[1].base}.p0" - arch: aarch64,arm64ec - - link: "llvm.arm.neon.vld1x{neon_type[1].tuple}.v{neon_type[1].lane}f{neon_type[1].base}.p0" - arch: arm + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld1{neon_type[1].no}" doc: "Load multiple single-element structures to one, two, three, or four registers" @@ -2631,8 +2673,8 @@ intrinsics: return_type: "{neon_type[1]}" attr: - *neon-v7 - - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]] + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: @@ -2663,13 +2705,12 @@ intrinsics: - ["*const i64", int64x2x3_t] - ["*const i64", int64x2x4_t] compose: - - LLVMLink: - name: "ld1x{neon_type[1].tuple}.{neon_type[1]}" - links: - - link: "llvm.aarch64.neon.ld1x{neon_type[1].tuple}.v{neon_type[1].lane}i{neon_type[1].base}.p0" - arch: aarch64,arm64ec - - link: "llvm.arm.neon.vld1x{neon_type[1].tuple}.v{neon_type[1].lane}i{neon_type[1].base}.p0" - arch: arm + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld1{neon_type[1].no}" doc: "Load multiple single-element structures to one, two, three, or four registers" @@ -2677,8 +2718,8 @@ intrinsics: return_type: "{neon_type[1]}" attr: - *neon-v7 - - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]] + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: @@ -2722,12 +2763,11 @@ intrinsics: - ["*const p16", poly16x8x4_t, int16x8x4_t] compose: - FnCall: - - transmute - - - FnCall: - - "vld1{neon_type[2].no}" - - - FnCall: - - transmute - - - a + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld1{neon_type[1].no}" doc: "Load multiple single-element structures to one, two, three, or four registers" @@ -2737,7 +2777,7 @@ intrinsics: - *neon-aes - *neon-v8 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: @@ -2750,12 +2790,11 @@ intrinsics: - ["*const p64", poly64x2x4_t, int64x2x4_t] compose: - FnCall: - - transmute - - - FnCall: - - "vld1{neon_type[2].no}" - - - FnCall: - - transmute - - - a + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld1{neon_type[1].no}" doc: "Load multiple single-element structures to one, two, three, or four registers" @@ -2764,8 +2803,8 @@ intrinsics: attr: - *neon-aes - *neon-v8 - - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]] + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: @@ -2774,12 +2813,11 @@ intrinsics: - ["*const p64", poly64x1x2_t, int64x1x2_t] compose: - FnCall: - - transmute - - - FnCall: - - "vld1{neon_type[2].no}" - - - FnCall: - - transmute - - - a + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld1{neon_type[1].no}" doc: "Load multiple single-element structures to one, two, three, or four registers" @@ -2788,7 +2826,7 @@ intrinsics: attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]] - *arm-fp16 - *neon-unstable-f16 - *target-not-arm64ec @@ -2802,13 +2840,12 @@ intrinsics: - ["*const f16", float16x4x4_t] - ["*const f16", float16x8x4_t] compose: - - LLVMLink: - name: "vld1x{neon_type[1].tuple}.{neon_type[1]}" - links: - - link: "llvm.aarch64.neon.ld1x{neon_type[1].tuple}.v{neon_type[1].lane}f{neon_type[1].base}.p0" - arch: aarch64,arm64ec - - link: "llvm.arm.neon.vld1x{neon_type[1].tuple}.v{neon_type[1].lane}f{neon_type[1].base}.p0" - arch: arm + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld1{type[2]}_{neon_type[1]}" doc: "Load one single-element structure to one lane of one register" @@ -3670,19 +3707,11 @@ intrinsics: safety: unsafe: [neon] types: - - ["*const f16", float16x4x3_t, f16] - - ["*const f16", float16x8x3_t, f16] + - ["*const f16", float16x4x3_t, f16, "4"] + - ["*const f16", float16x8x3_t, f16, "8"] compose: - - LLVMLink: - name: "vld3.{neon_type[1]}" - arguments: - - "ptr: {type[0]}" - links: - - link: "llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[2]}.p0" - arch: aarch64,arm64ec - - FnCall: - - "_vld3{neon_type[1].nox}" - - - "a as _" + - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "3", a], [], true] + - name: "vld3{neon_type[1].dup_nox}" doc: Load single 3-element structure and replicate to all lanes of two registers @@ -3876,23 +3905,17 @@ intrinsics: safety: unsafe: [neon] types: - - ['*const i8', int8x8x3_t, '*const int8x8_t', i8] - - ['*const i16', int16x4x3_t, '*const int16x4_t', i16] - - ['*const i32', int32x2x3_t, '*const int32x2_t', i32] - - ['*const i8', int8x16x3_t, '*const int8x16_t', i8] - - ['*const i16', int16x8x3_t, '*const int16x8_t', i16] - - ['*const i32', int32x4x3_t, '*const int32x4_t', i32] - - ['*const f32', float32x2x3_t, '*const float32x2_t', f32] - - ['*const f32', float32x4x3_t, '*const float32x4_t', f32] + - ['*const i8', int8x8x3_t, i8, "8"] + - ['*const i16', int16x4x3_t, i16, "4"] + - ['*const i32', int32x2x3_t, i32, "2"] + - ['*const i8', int8x16x3_t, i8, "16"] + - ['*const i16', int16x8x3_t, i16, "8"] + - ['*const i32', int32x4x3_t, i32, "4"] + - ['*const f32', float32x2x3_t, f32, "2"] + - ['*const f32', float32x4x3_t, f32, "4"] compose: - - LLVMLink: - name: 'vld3{neon_type[1].nox}' - arguments: - - 'ptr: {type[2]}' - links: - - link: 'llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[3]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld3{neon_type[1].nox}', ['a as _']] + - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "3", a], [], true] + - name: "vld3{neon_type[1].nox}" doc: Load multiple 3-element structures to three registers @@ -3907,14 +3930,12 @@ intrinsics: types: - ['*const i64', int64x1x3_t, '*const int64x1_t', i64] compose: - - LLVMLink: - name: "vld3{neon_type[1].nox}" - arguments: - - 'ptr: {type[2]}' - links: - - link: 'llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[3]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld3{neon_type[1].nox}', ['a as _']] + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld3{neon_type[1].nox}" doc: Load multiple 3-element structures to three registers @@ -4372,23 +4393,16 @@ intrinsics: safety: unsafe: [neon] types: - - ['*const i8', int8x8x4_t, i8, '*const int8x8_t'] - - ['*const i32', int32x4x4_t, i32, '*const int32x4_t'] - - ['*const i16', int16x4x4_t, i16, '*const int16x4_t'] - - ['*const i32', int32x2x4_t, i32, '*const int32x2_t'] - - ['*const i8', int8x16x4_t, i8, '*const int8x16_t'] - - ['*const i16', int16x8x4_t, i16, '*const int16x8_t'] - - ['*const f32', float32x2x4_t, f32, '*const float32x2_t'] - - ['*const f32', float32x4x4_t, f32, '*const float32x4_t'] + - ['*const i8', int8x8x4_t, i8, "8"] + - ['*const i32', int32x4x4_t, i32, "4"] + - ['*const i16', int16x4x4_t, i16, "4"] + - ['*const i32', int32x2x4_t, i32, "2"] + - ['*const i8', int8x16x4_t, i8, "16"] + - ['*const i16', int16x8x4_t, i16, "8"] + - ['*const f32', float32x2x4_t, f32, "2"] + - ['*const f32', float32x4x4_t, f32, "4"] compose: - - LLVMLink: - name: 'vld4{neon_type[1].nox}' - arguments: - - 'ptr: {type[3]}' - links: - - link: 'llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld4{neon_type[1].nox}', ['a as _']] + - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "4", a], [], true] - name: "vld4{neon_type[1].nox}" doc: Load multiple 4-element structures to four registers @@ -4401,14 +4415,12 @@ intrinsics: types: - ['*const i64', int64x1x4_t, i64, '*const int64x1_t'] compose: - - LLVMLink: - name: 'vld4{neon_type[1].nox}' - arguments: - - 'ptr: {type[3]}' - links: - - link: 'llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld4{neon_type[1].nox}', ['a as _']] + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld4{neon_type[1].lane_nox}" doc: Load multiple 4-element structures to four registers @@ -5071,17 +5083,7 @@ intrinsics: types: - [i64, int64x1x2_t, int64x1_t] compose: - - LLVMLink: - name: 'vst2.{neon_type[1]}' - arguments: - - 'ptr: *mut i8' - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'size: i32' - links: - - link: 'llvm.arm.neon.vst2.v{neon_type[1].lane}{type[0]}.p0' - arch: arm - - FnCall: ['_vst2{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', '8']] + - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]] - name: "vst2{neon_type[1].nox}" doc: "Store multiple 2-element structures from two registers" @@ -5114,16 +5116,7 @@ intrinsics: types: - [i64, int64x1x2_t, int64x1_t] compose: - - LLVMLink: - name: 'st2.{neon_type[1]}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st2.v{neon_type[1].lane}{type[0]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst2{neon_type[1].nox}', ['b.0', 'b.1', 'a as _']] + - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]] - name: "vst2{neon_type[1].nox}" doc: "Store multiple 2-element structures from two registers" @@ -5135,26 +5128,16 @@ intrinsics: safety: unsafe: [neon] types: - - [i8, int8x8x2_t, int8x8_t] - - [i16, int16x4x2_t, int16x4_t] - - [i32, int32x2x2_t, int32x2_t] - - [i8, int8x16x2_t, int8x16_t] - - [i16, int16x8x2_t, int16x8_t] - - [i32, int32x4x2_t, int32x4_t] - - [f32, float32x2x2_t, float32x2_t] - - [f32, float32x4x2_t, float32x4_t] + - [i8, int8x8x2_t, "8"] + - [i16, int16x4x2_t, "4"] + - [i32, int32x2x2_t, "2"] + - [i8, int8x16x2_t, "16"] + - [i16, int16x8x2_t, "8"] + - [i32, int32x4x2_t, "4"] + - [f32, float32x2x2_t, "2"] + - [f32, float32x4x2_t, "4"] compose: - - LLVMLink: - name: 'st2.{neon_type[1]}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st2.v{neon_type[1].lane}{type[0]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst2{neon_type[1].nox}', ['b.0', 'b.1', 'a as _']] - + - FnCall: ["crate::core_arch::macros::interleaving_store!", [{ Type: "{type[0]}" }, "{type[2]}", "2", a, b], [], true] - name: "vst2{neon_type[1].nox}" doc: "Store multiple 2-element structures from two registers" @@ -5419,7 +5402,7 @@ intrinsics: unsafe: [neon] types: - [f16, float16x4x2_t, '2', float16x4_t, '2'] - - [f16, float16x8x2_t, '1', float16x8_t, '2'] + - [f16, float16x8x2_t, '3', float16x8_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[2]}"]] - LLVMLink: @@ -5448,17 +5431,7 @@ intrinsics: types: - [i64, int64x1x3_t, int64x1_t] compose: - - LLVMLink: - name: 'st3.{neon_type[1].nox}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'c: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st3.v{neon_type[1].lane}{type[0]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst3{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'a as _']] + - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]] - name: "vst3{neon_type[1].nox}" doc: "Store multiple 3-element structures from three registers" @@ -5493,18 +5466,7 @@ intrinsics: types: - [i64, int64x1x3_t, int64x1_t] compose: - - LLVMLink: - name: 'vst3.{neon_type[1]}' - arguments: - - 'ptr: *mut i8' - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'c: {type[2]}' - - 'size: i32' - links: - - link: 'llvm.arm.neon.vst3.p0.v{neon_type[1].lane}{type[0]}' - arch: arm - - FnCall: ['_vst3{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', 'b.2', '8']] + - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]] - name: "vst3{neon_type[1].nox}" doc: "Store multiple 3-element structures from three registers" @@ -5593,27 +5555,16 @@ intrinsics: safety: unsafe: [neon] types: - - [i8, int8x8x3_t, int8x8_t, '1'] - - [i16, int16x4x3_t, int16x4_t, '2'] - - [i32, int32x2x3_t, int32x2_t, '4'] - - [i8, int8x16x3_t, int8x16_t, '1'] - - [i16, int16x8x3_t, int16x8_t, '2'] - - [i32, int32x4x3_t, int32x4_t, '4'] - - [f32, float32x2x3_t, float32x2_t, '4'] - - [f32, float32x4x3_t, float32x4_t, '4'] + - [i8, int8x8x3_t, '8'] + - [i16, int16x4x3_t, '4'] + - [i32, int32x2x3_t, '2'] + - [i8, int8x16x3_t, '16'] + - [i16, int16x8x3_t, '8'] + - [i32, int32x4x3_t, '4'] + - [f32, float32x2x3_t, '2'] + - [f32, float32x4x3_t, '4'] compose: - - LLVMLink: - name: 'vst3.{neon_type[1]}' - arguments: - - 'ptr: *mut i8' - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'c: {type[2]}' - - 'size: i32' - links: - - link: 'llvm.arm.neon.vst3.p0.v{neon_type[1].lane}{type[0]}' - arch: arm - - FnCall: ['_vst3{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', 'b.2', "{type[3]}"]] + - FnCall: ["crate::core_arch::macros::interleaving_store!", [{ Type: "{type[0]}" }, "{type[2]}", "3", a, b], [], true] - name: "vst3{neon_type[1].nox}" @@ -5725,27 +5676,16 @@ intrinsics: safety: unsafe: [neon] types: - - [i8, int8x8x3_t, int8x8_t] - - [i16, int16x4x3_t, int16x4_t] - - [i32, int32x2x3_t, int32x2_t] - - [i8, int8x16x3_t, int8x16_t] - - [i16, int16x8x3_t, int16x8_t] - - [i32, int32x4x3_t, int32x4_t] - - [f32, float32x2x3_t, float32x2_t] - - [f32, float32x4x3_t, float32x4_t] + - [i8, int8x8x3_t, "8"] + - [i16, int16x4x3_t, "4"] + - [i32, int32x2x3_t, "2"] + - [i8, int8x16x3_t, "16"] + - [i16, int16x8x3_t, "8"] + - [i32, int32x4x3_t, "4"] + - [f32, float32x2x3_t, "2"] + - [f32, float32x4x3_t, "4"] compose: - - LLVMLink: - name: 'vst3.{neon_type[1]}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'c: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st3.v{neon_type[1].lane}{type[0]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst3{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'a as _']] - + - FnCall: ["crate::core_arch::macros::interleaving_store!", [{ Type: "{type[0]}" }, "{type[2]}", "3", a, b], [], true] - name: "vst3{neon_type[1].nox}" doc: "Store multiple 3-element structures from three registers" @@ -5875,19 +5815,7 @@ intrinsics: types: - [i64, int64x1x4_t, int64x1_t] compose: - - LLVMLink: - name: 'vst4.{neon_type[1]}' - arguments: - - 'ptr: *mut i8' - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'c: {type[2]}' - - 'd: {type[2]}' - - 'size: i32' - links: - - link: 'llvm.arm.neon.vst4.p0.v{neon_type[1].lane}{type[0]}' - arch: arm - - FnCall: ['_vst4{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', 'b.2', 'b.3', '8']] + - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]] - name: "vst4{neon_type[1].nox}" doc: "Store multiple 4-element structures from four registers" @@ -5901,18 +5829,7 @@ intrinsics: types: - [i64, int64x1x4_t, int64x1_t] compose: - - LLVMLink: - name: 'vst4.{neon_type[1]}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'c: {type[2]}' - - 'd: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st4.{neon_type[2]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst4{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'a as _']] + - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]] - name: "vst4{neon_type[1].nox}" doc: "Store multiple 4-element structures from four registers" @@ -6136,27 +6053,16 @@ intrinsics: safety: unsafe: [neon] types: - - [i8, int8x8x4_t, int8x8_t] - - [i16, int16x4x4_t, int16x4_t] - - [i32, int32x2x4_t, int32x2_t] - - [i8, int8x16x4_t, int8x16_t] - - [i16, int16x8x4_t, int16x8_t] - - [i32, int32x4x4_t, int32x4_t] - - [f32, float32x2x4_t, float32x2_t] - - [f32, float32x4x4_t, float32x4_t] + - [i8, int8x8x4_t, "8"] + - [i16, int16x4x4_t, "4"] + - [i32, int32x2x4_t, "2"] + - [i8, int8x16x4_t, "16"] + - [i16, int16x8x4_t, "8"] + - [i32, int32x4x4_t, "4"] + - [f32, float32x2x4_t, "2"] + - [f32, float32x4x4_t, "4"] compose: - - LLVMLink: - name: 'vst4.{neon_type[1]}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'c: {type[2]}' - - 'd: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st4.v{neon_type[1].lane}{type[0]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst4{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'a as _']] + - FnCall: ["crate::core_arch::macros::interleaving_store!", [{ Type: "{type[0]}" }, "{type[2]}", "4", a, b], [], true] - name: "vst4{neon_type[1].nox}" @@ -6265,10 +6171,11 @@ intrinsics: - *neon-i8mm - *neon-v8 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vusdot]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [usdot]]}]] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [usdot]]}]] - *neon-unstable-i8mm - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - [int32x2_t, uint8x8_t, int8x8_t] - [int32x4_t, uint8x16_t, int8x16_t] @@ -6281,10 +6188,10 @@ intrinsics: - link: "llvm.arm.neon.usdot.v{neon_type[0].lane}i32.v{neon_type[1].lane}i8" arch: arm - - name: "vusdot{type[0]}" + - name: "vusdot{neon_type[0].lane_nox}" doc: "Dot product index form with unsigned and signed integers" - arguments: ["a: {neon_type[1]}", "b: {neon_type[2]}", "c: int8x8_t"] - return_type: "{neon_type[1]}" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: int8x8_t"] + return_type: "{neon_type[0]}" attr: - *neon-i8mm - *neon-v8 @@ -6294,22 +6201,19 @@ intrinsics: - *neon-unstable-i8mm - *neon-cfg-arm-unstable static_defs: ["const LANE: i32"] - big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure. safety: safe types: - - ['_lane_s32', int32x2_t, uint8x8_t, '[LANE as u32, LANE as u32]',''] - - ['q_lane_s32', int32x4_t, uint8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] + - [int32x2_t, uint8x8_t, ''] + - [int32x4_t, uint8x16_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '1']] - Let: - c - - int32x2_t - - FnCall: [transmute, [c]] #- FnCall: ['vreinterpret_s32_s8', [c]] + - FnCall: ['vreinterpret_s32_s8', [c]] - Let: - c - - "{type[1]}" - - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]] - - FnCall: ["vusdot{neon_type[1].no}", [a, b, {FnCall: [transmute, [c]]}]] #'vreinterpret{type[4]}_s8_s32' + - FnCall: ['vdup{neon_type[0].lane_nox}', [c], [LANE]] + - FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: ['vreinterpret{type[2]}_s8_s32', [c]]}]] - name: "vsudot{neon_type[0].lane_nox}" doc: "Dot product index form with signed and unsigned integers" @@ -6319,30 +6223,27 @@ intrinsics: - *neon-i8mm - *neon-v8 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsudot, 'LANE = 0']]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sudot, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sudot, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-unstable-i8mm - *neon-cfg-arm-unstable static_defs: ["const LANE: i32"] - big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure. safety: safe types: - - [int32x2_t, int8x8_t, uint8x8_t, '[LANE as u32, LANE as u32]', uint32x2_t,''] - - [int32x4_t, int8x16_t, uint8x8_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]', uint32x4_t,'q'] + - [int32x2_t, int8x8_t, uint8x8_t, uint32x2_t, ''] + - [int32x4_t, int8x16_t, uint8x8_t, uint32x4_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '1']] - Let: - c - - uint32x2_t - - FnCall: [transmute, [c]] #- FnCall: ['vreinterpret_u32_u8', [c]] + - FnCall: ['vreinterpret_u32_u8', [c]] - Let: - c - - "{type[4]}" - - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]] + - FnCall: ['vdup{neon_type[3].lane_nox}', [c], [LANE]] - FnCall: - "vusdot{neon_type[0].no}" - - a - - FnCall: [transmute, [c]] #- FnCall: ['vreinterpret{type[5]}_u8_u32', [c]] + - FnCall: ['vreinterpret{type[4]}_u8_u32', [c]] - b - name: "vmul{neon_type[1].no}" @@ -6424,20 +6325,20 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint16x4_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint16x8_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint32x2_t, uint32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [uint32x4_t, uint32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int16x4_t, int16x4_t, '2'] + - [int16x8_t, int16x4_t, '2'] + - [int32x2_t, int32x2_t, '1'] + - [int32x4_t, int32x2_t, '1'] + - [uint16x4_t, uint16x4_t, '2'] + - [uint16x8_t, uint16x4_t, '2'] + - [uint32x2_t, uint32x2_t, '1'] + - [uint32x4_t, uint32x2_t, '1'] compose: - FnCall: ["static_assert_uimm_bits!", [LANE, "{type[2]}"]] - FnCall: - simd_mul - - a - - FnCall: ["simd_shuffle!", [b, b, "{type[3]}"]] + - FnCall: ["vdup{neon_type[0].lane_nox}", [b], [LANE]] - name: "vmul{neon_type[0].lane_nox}" @@ -6456,14 +6357,14 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float16x4_t, float16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [float16x8_t, float16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [float16x4_t, float16x4_t, '2'] + - [float16x8_t, float16x4_t, '2'] compose: - FnCall: ["static_assert_uimm_bits!", [LANE, "{type[2]}"]] - FnCall: - simd_mul - - a - - FnCall: ["simd_shuffle!", [v, v, "{type[3]}"]] + - FnCall: ["vdup{neon_type[0].lane_nox}", [v], [LANE]] - name: "vmul{neon_type[0].laneq_nox}" @@ -6480,20 +6381,20 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]'] - - [int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint16x4_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint16x8_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint32x2_t, uint32x4_t, '2', '[LANE as u32, LANE as u32]'] - - [uint32x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int16x4_t, int16x8_t, '3'] + - [int16x8_t, int16x8_t, '3'] + - [int32x2_t, int32x4_t, '2'] + - [int32x4_t, int32x4_t, '2'] + - [uint16x4_t, uint16x8_t, '3'] + - [uint16x8_t, uint16x8_t, '3'] + - [uint32x2_t, uint32x4_t, '2'] + - [uint32x4_t, uint32x4_t, '2'] compose: - FnCall: ["static_assert_uimm_bits!", [LANE, "{type[2]}"]] - FnCall: - simd_mul - - a - - FnCall: ["simd_shuffle!", [b, b, "{type[3]}"]] + - FnCall: ["vdup{neon_type[0].laneq_nox}", [b], [LANE]] - name: "vmull{neon_type[1].no}" doc: Signed multiply long @@ -6511,13 +6412,10 @@ intrinsics: - ["s16", int16x4_t, int32x4_t] - ["s32", int32x2_t, int64x2_t] compose: - - LLVMLink: - name: "smull.{neon_type[1]}" - links: - - link: "llvm.aarch64.neon.smull.{neon_type[2]}" - arch: aarch64,arm64ec - - link: "llvm.arm.neon.vmulls.{neon_type[2]}" - arch: arm + - FnCall: + - simd_mul + - - FnCall: ['simd_cast', [a]] + - FnCall: ['simd_cast', [b]] - name: "vmull{neon_type[1].no}" doc: "Unsigned multiply long" @@ -6535,13 +6433,10 @@ intrinsics: - ["u16", uint16x4_t, uint32x4_t] - ["u32", uint32x2_t, uint64x2_t] compose: - - LLVMLink: - name: "smull.{neon_type[1]}" - links: - - link: "llvm.aarch64.neon.umull.{neon_type[2]}" - arch: aarch64,arm64ec - - link: "llvm.arm.neon.vmullu.{neon_type[2]}" - arch: arm + - FnCall: + - simd_mul + - - FnCall: ['simd_cast', [a]] + - FnCall: ['simd_cast', [b]] - name: "vmull{neon_type[1].no}" doc: "Polynomial multiply long" @@ -6930,23 +6825,22 @@ intrinsics: attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ["vsubhn"]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [subhn2]]}]] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [subhn2]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe types: - - [int8x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [int16x4_t, int32x4_t, int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [int32x2_t, int64x2_t, int32x4_t, '[0, 1, 2, 3]'] - - [uint8x8_t, uint16x8_t, uint8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, uint32x4_t, uint16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, uint64x2_t, uint32x4_t, '[0, 1, 2, 3]'] + - [int8x8_t, int16x8_t, int8x16_t] + - [int16x4_t, int32x4_t, int16x8_t] + - [int32x2_t, int64x2_t, int32x4_t] + - [uint8x8_t, uint16x8_t, uint8x16_t] + - [uint16x4_t, uint32x4_t, uint16x8_t] + - [uint32x2_t, uint64x2_t, uint32x4_t] compose: - Let: - d - - "{neon_type[0]}" - FnCall: ["vsubhn{neon_type[1].noq}", [b, c]] - - FnCall: [simd_shuffle!, [a, d, "{type[3]}"]] + - FnCall: ['vcombine_{neon_type[0]}', [a, d]] - name: "vhsub{neon_type[1].no}" doc: "Signed halving subtract" @@ -7100,7 +6994,6 @@ intrinsics: doc: "Dot product index form with unsigned and signed integers" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" - big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure. attr: - *neon-v8 - *neon-i8mm @@ -7111,14 +7004,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [int32x2_t, uint8x8_t, int8x16_t, '[LANE as u32, LANE as u32]',''] - - [int32x4_t, uint8x16_t, int8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] + - [int32x2_t, uint8x8_t, int8x16_t, ''] + - [int32x4_t, uint8x16_t, int8x16_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '2']] - - Let: [c, int32x4_t, {FnCall: [transmute, [c]]}] - - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]}] - - FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: [transmute, [c]]}]] - #- FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: ['vreinterpret{type[4]}_s8_s32', [c]]}]] + - Let: [c, {FnCall: [vreinterpretq_s32_s8, [c]]}] + - Let: [c, {FnCall: ['vdup{neon_type[0].laneq_nox}', [c], [LANE]]}] + - FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: ['vreinterpret{type[3]}_s8_s32', [c]]}]] - name: "vsudot{neon_type[0].laneq_nox}" doc: "Dot product index form with signed and unsigned integers" @@ -7128,28 +7020,26 @@ intrinsics: - *neon-v8 - *neon-i8mm - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsudot, 'LANE = 1']]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sudot, 'LANE = 3']]}]] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sudot, 'LANE = 3']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']] static_defs: ["const LANE: i32"] safety: safe types: - - [int32x2_t, int8x8_t, uint8x16_t, '[LANE as u32, LANE as u32]', uint32x2_t] - - [int32x4_t, int8x16_t, uint8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]', uint32x4_t] + - [int32x2_t, int8x8_t, uint8x16_t, uint32x2_t, ''] + - [int32x4_t, int8x16_t, uint8x16_t, uint32x4_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 2]] - Let: - c - - uint32x4_t - - FnCall: [transmute, [c]] + - FnCall: [vreinterpretq_u32_u8, [c]] - Let: - c - - "{type[4]}" - - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]] + - FnCall: ['vdup{neon_type[3].laneq_nox}', [c], [LANE]] - FnCall: - "vusdot{neon_type[0].no}" - - a - - FnCall: [transmute, [c]] + - FnCall: ['vreinterpret{type[4]}_u8_u32', [c]] - b - name: "vdot{neon_type[0].laneq_nox}" @@ -7157,70 +7047,62 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" static_defs: ["const LANE: i32"] - big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure. attr: - *neon-v8 - FnCall: [target_feature, ['enable = "neon,dotprod"']] - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsdot, 'LANE = 0']]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sdot, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']] + - *neon-not-arm-stable-dotprod + - *neon-cfg-arm-unstable safety: safe types: - - [int32x2_t, int8x8_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32]', ''] - - [int32x4_t, int8x16_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] + - [int32x2_t, int8x8_t, int8x16_t, ''] + - [int32x4_t, int8x16_t, int8x16_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '2']] - Let: - c - - "{neon_type[3]}" - - FnCall: [transmute, [c]] - #- FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]] + - FnCall: [vreinterpretq_s32_s8, [c]] - Let: - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, '{type[4]}']] + - FnCall: ['vdup{neon_type[0].laneq_nox}', [c], [LANE]] - FnCall: - "vdot{neon_type[0].no}" - - a - b - - FnCall: [transmute, [c]] - #- FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]] + - FnCall: ['vreinterpret{type[3]}_s8_s32', [c]] - name: "vdot{neon_type[0].laneq_nox}" doc: Dot product arithmetic (indexed) arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" static_defs: ["const LANE: i32"] - big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure. attr: - *neon-v8 - FnCall: [target_feature, ['enable = "neon,dotprod"']] - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vudot, 'LANE = 0']]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [udot, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']] + - *neon-not-arm-stable-dotprod + - *neon-cfg-arm-unstable safety: safe types: - - [uint32x2_t, uint8x8_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32]',''] - - [uint32x4_t, uint8x16_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] + - [uint32x2_t, uint8x8_t, uint8x16_t, ''] + - [uint32x4_t, uint8x16_t, uint8x16_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '2']] - Let: - c - - "{neon_type[3]}" - - FnCall: [transmute, [c]] - #- FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]] + - FnCall: ['vreinterpretq_u32_u8', [c]] - Let: - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, '{type[4]}']] + - FnCall: ['vdup{neon_type[0].laneq_nox}', [c], [LANE]] - FnCall: - "vdot{neon_type[0].no}" - - a - b - - FnCall: [transmute, [c]] - #- FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]] + - FnCall: ['vreinterpret{type[3]}_u8_u32', [c]] - name: "vdot{neon_type[0].no}" doc: Dot product arithmetic (vector) @@ -7231,9 +7113,10 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,dotprod"']] - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsdot]]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sdot]]}]] - - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]}]] + - *neon-not-arm-stable-dotprod - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - [int32x2_t, int8x8_t] - [int32x4_t, int8x16_t] @@ -7255,9 +7138,10 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,dotprod"']] - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vudot]]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [udot]]}]] - - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]}]] + - *neon-not-arm-stable-dotprod - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - [uint32x2_t, uint8x8_t] - [uint32x4_t, uint8x16_t] @@ -7281,28 +7165,25 @@ intrinsics: - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsdot, 'LANE = 0']]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sdot, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]}]] + - *neon-not-arm-stable-dotprod - *neon-cfg-arm-unstable - big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure. safety: safe types: - - [int32x2_t, int8x8_t, int8x8_t, int32x2_t, '[LANE as u32, LANE as u32]',''] - - [int32x4_t, int8x16_t, int8x8_t, int32x2_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] + - [int32x2_t, int8x8_t, int8x8_t, ''] + - [int32x4_t, int8x16_t, int8x8_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '1']] - Let: - c - - "{neon_type[3]}" - - FnCall: [transmute, [c]] + - FnCall: ['vreinterpret_s32_s8', [c]] - Let: - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, '{type[4]}']] + - FnCall: ['vdup{neon_type[0].lane_nox}', [c], [LANE]] - FnCall: - "vdot{neon_type[0].no}" - - a - b - - FnCall: [transmute, [c]] + - FnCall: ['vreinterpret{type[3]}_s8_s32', [c]] - name: "vdot{neon_type[0].lane_nox}" doc: Dot product arithmetic (indexed) @@ -7315,28 +7196,25 @@ intrinsics: - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vudot, 'LANE = 0']]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [udot, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]}]] + - *neon-not-arm-stable-dotprod - *neon-cfg-arm-unstable safety: safe - big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure. types: - - [uint32x2_t, uint8x8_t, uint8x8_t, uint32x2_t, '[LANE as u32, LANE as u32]',''] - - [uint32x4_t, uint8x16_t, uint8x8_t, uint32x2_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] + - [uint32x2_t, uint8x8_t, uint8x8_t, ''] + - [uint32x4_t, uint8x16_t, uint8x8_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '1']] - Let: - c - - "{neon_type[3]}" - - FnCall: [transmute, [c]] #- FnCall: ['vreinterpret_{neon_type[0]}_{neon_type[1]}', [c]] + - FnCall: ['vreinterpret_u32_u8', [c]] - Let: - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, '{type[4]}']] + - FnCall: ['vdup{neon_type[0].lane_nox}', [c], [LANE]] - FnCall: - "vdot{neon_type[0].no}" - - a - b - - FnCall: [transmute, [c]] #- FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]] + - FnCall: ['vreinterpret{type[3]}_u8_u32', [c]] - name: "vmax{neon_type.no}" doc: Maximum (vector) @@ -7447,7 +7325,13 @@ intrinsics: - float32x2_t - float32x4_t compose: - - FnCall: [simd_fmax, [a, b]] + - LLVMLink: + name: "fmaxnm.{neon_type}" + links: + - link: "llvm.arm.neon.vmaxnm.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.fmaxnm.{neon_type}" + arch: aarch64,arm64ec - name: "vmaxnm{neon_type.no}" @@ -7467,7 +7351,13 @@ intrinsics: - float16x4_t - float16x8_t compose: - - FnCall: [simd_fmax, [a, b]] + - LLVMLink: + name: "fmaxnm.{neon_type}" + links: + - link: "llvm.arm.neon.vmaxnm.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.fmaxnm.{neon_type}" + arch: aarch64,arm64ec - name: "vminnm{neon_type.no}" @@ -7487,7 +7377,13 @@ intrinsics: - float16x4_t - float16x8_t compose: - - FnCall: [simd_fmin, [a, b]] + - LLVMLink: + name: "fminnm.{neon_type}" + links: + - link: "llvm.arm.neon.vminnm.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.fminnm.{neon_type}" + arch: aarch64,arm64ec - name: "vmin{neon_type.no}" @@ -7600,7 +7496,13 @@ intrinsics: - float32x2_t - float32x4_t compose: - - FnCall: [simd_fmin, [a, b]] + - LLVMLink: + name: "fminnm.{neon_type}" + links: + - link: "llvm.arm.neon.vminnm.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.fminnm.{neon_type}" + arch: aarch64,arm64ec - name: "vpadd{neon_type.no}" doc: Floating-point add pairwise @@ -7613,6 +7515,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - float32x2_t compose: @@ -7637,6 +7540,7 @@ intrinsics: - *neon-cfg-arm-unstable - *target-not-arm64ec safety: safe + big_endian_inverse: true types: - float16x4_t compose: @@ -7703,10 +7607,10 @@ intrinsics: static_defs: ['const N: i32'] safety: safe types: - - [int16x4_t, int16x4_t, int32x4_t, '[N as u32, N as u32, N as u32, N as u32]'] + - [int16x4_t, int16x4_t, int32x4_t, '[N as u32; 4]'] compose: - FnCall: [static_assert_uimm_bits!, [N, '2']] - - Let: [b, "{neon_type[0]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}] + - Let: [b, {FnCall: ['vdup{neon_type[0].lane_nox}', [b], [N]]}] - FnCall: [vqdmull_s16, [a, b]] - name: "vqdmull_lane_s32" @@ -7723,10 +7627,10 @@ intrinsics: static_defs: ['const N: i32'] safety: safe types: - - [int32x2_t, int32x2_t, int64x2_t, '[N as u32, N as u32]'] + - [int32x2_t, int32x2_t, int64x2_t] compose: - FnCall: [static_assert_uimm_bits!, [N, '1']] - - Let: [b, "{neon_type[0]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}] + - Let: [b, {FnCall: ['vdup{neon_type[0].lane_nox}', [b], [N]]}] - FnCall: [vqdmull_s32, [a, b]] - name: "vqdmlal{neon_type[1].noq}" @@ -7770,7 +7674,7 @@ intrinsics: attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vqdmlal, N = 2]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqdmlal, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sqdmlal, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-not-arm-stable - *neon-cfg-arm-unstable @@ -7789,7 +7693,7 @@ intrinsics: attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vqdmlal, N = 1]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqdmlal, 'N = 1']]}]] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sqdmlal, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-not-arm-stable - *neon-cfg-arm-unstable @@ -7842,7 +7746,7 @@ intrinsics: attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vqdmlsl, N = 2]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqdmlsl, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sqdmlsl, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-not-arm-stable - *neon-cfg-arm-unstable @@ -7861,7 +7765,7 @@ intrinsics: attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vqdmlsl, N = 1]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqdmlsl, 'N = 1']]}]] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sqdmlsl, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-not-arm-stable - *neon-cfg-arm-unstable @@ -8348,9 +8252,9 @@ intrinsics: static_defs: ['const N: i32'] safety: safe types: - - [uint16x8_t, uint8x8_t, 'N >= 1 && N <= 8', 'const { uint16x8_t([-N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16]) }'] - - [uint32x4_t, uint16x4_t, 'N >= 1 && N <= 16', 'const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }'] - - [uint64x2_t, uint32x2_t, 'N >= 1 && N <= 32', 'const { uint64x2_t([-N as u64, -N as u64]) }'] + - [uint16x8_t, uint8x8_t, 'N >= 1 && N <= 8', 'const { uint16x8_t([-N as u16; 8]) }'] + - [uint32x4_t, uint16x4_t, 'N >= 1 && N <= 16', 'const { uint32x4_t([-N as u32; 4]) }'] + - [uint64x2_t, uint32x2_t, 'N >= 1 && N <= 32', 'const { uint64x2_t([-N as u64; 2]) }'] compose: - FnCall: [static_assert!, ["{type[2]}"]] - LLVMLink: @@ -8600,8 +8504,35 @@ intrinsics: arguments: ["a: {type[0]}"] return_type: "{type[1]}" attr: - - *neon-aes - - *neon-v8 + - *neon-aes + - *neon-v8 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] + - *neon-not-arm-stable + - *neon-cfg-arm-unstable + safety: safe + types: + - [p128, int64x2_t] + - [p128, uint64x2_t] + - [p128, poly64x2_t] + - [p128, int8x16_t] + - [p128, uint8x16_t] + - [p128, poly8x16_t] + - [poly64x2_t, p128] + - [p128, int32x4_t] + - [p128, uint32x4_t] + - [p128, int16x8_t] + - [p128, uint16x8_t] + - [p128, poly16x8_t] + compose: + - FnCall: [transmute, [a]] + + - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}" + doc: Vector reinterpret cast operation + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] - *neon-not-arm-stable @@ -8610,30 +8541,17 @@ intrinsics: types: - [poly64x1_t, int32x2_t] - [poly64x1_t, uint32x2_t] - - [poly64x2_t, int32x4_t] - - [poly64x2_t, uint32x4_t] - - [p128, int64x2_t] - - [p128, uint64x2_t] - - [p128, poly64x2_t] - [poly8x16_t, p128] - - [p128, int8x16_t] - - [p128, uint8x16_t] - - [p128, poly8x16_t] - [int32x2_t, poly64x1_t] - [uint32x2_t, poly64x1_t] - [int32x4_t, poly64x2_t] - [uint32x4_t, poly64x2_t] - [int64x2_t, p128] - [uint64x2_t, p128] - - [poly64x2_t, p128] - [poly64x1_t, int16x4_t] - [poly64x1_t, uint16x4_t] - [poly64x1_t, poly16x4_t] - - [poly64x2_t, int16x8_t] - - [poly64x2_t, uint16x8_t] - [poly64x2_t, poly16x8_t] - - [p128, int32x4_t] - - [p128, uint32x4_t] - [poly16x4_t, poly64x1_t] - [int16x4_t, poly64x1_t] - [uint16x4_t, poly64x1_t] @@ -8645,12 +8563,7 @@ intrinsics: - [poly64x1_t, int8x8_t] - [poly64x1_t, uint8x8_t] - [poly64x1_t, poly8x8_t] - - [poly64x2_t, int8x16_t] - - [poly64x2_t, uint8x16_t] - [poly64x2_t, poly8x16_t] - - [p128, int16x8_t] - - [p128, uint16x8_t] - - [p128, poly16x8_t] - [poly8x8_t, poly64x1_t] - [int8x8_t, poly64x1_t] - [uint8x8_t, poly64x1_t] @@ -8662,53 +8575,12 @@ intrinsics: - [poly16x8_t, p128] - [int8x16_t, p128] - [uint8x16_t, p128] - compose: - - FnCall: [transmute, [a]] - - - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}" - doc: Vector reinterpret cast operation - arguments: ["a: {type[0]}"] - return_type: "{type[1]}" - attr: - - *neon-v7 - - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] - - *neon-not-arm-stable - - *neon-cfg-arm-unstable - safety: safe - types: - - [uint8x8_t, int8x8_t] - - [poly8x8_t, int8x8_t] - - [poly16x4_t, int16x4_t] - - [uint16x4_t, int16x4_t] - - [uint32x2_t, int32x2_t] - - [uint64x1_t, int64x1_t] - - [uint8x16_t, int8x16_t] - - [poly8x16_t, int8x16_t] - - [poly16x8_t, int16x8_t] - - [uint16x8_t, int16x8_t] - - [uint32x4_t, int32x4_t] - - [uint64x2_t, int64x2_t] - - [poly8x8_t, uint8x8_t] - - [int8x8_t, uint8x8_t] - - [poly16x4_t, uint16x4_t] - - [int16x4_t, uint16x4_t] - - [int32x2_t, uint32x2_t] - - [int64x1_t, uint64x1_t] - - [poly8x16_t, uint8x16_t] - - [int8x16_t, uint8x16_t] - - [poly16x8_t, uint16x8_t] - - [int16x8_t, uint16x8_t] - - [int32x4_t, uint32x4_t] - - [int64x2_t, uint64x2_t] - - [int8x8_t, poly8x8_t] - - [uint8x8_t, poly8x8_t] - - [int16x4_t, poly16x4_t] - - [uint16x4_t, poly16x4_t] - - [int8x16_t, poly8x16_t] - - [uint8x16_t, poly8x16_t] - - [int16x8_t, poly16x8_t] - - [uint16x8_t, poly16x8_t] + - [poly64x2_t, int32x4_t] + - [poly64x2_t, uint32x4_t] + - [poly64x2_t, int16x8_t] + - [poly64x2_t, uint16x8_t] + - [poly64x2_t, int8x16_t] + - [poly64x2_t, uint8x16_t] - [int16x4_t, int8x8_t] - [uint16x4_t, int8x8_t] - [poly16x4_t, int8x8_t] @@ -8859,19 +8731,15 @@ intrinsics: - [uint8x16_t, uint64x2_t] - [float32x2_t, int8x8_t] - [float32x2_t, int16x4_t] - - [float32x2_t, int32x2_t] - [float32x2_t, int64x1_t] - [float32x4_t, int8x16_t] - [float32x4_t, int16x8_t] - - [float32x4_t, int32x4_t] - [float32x4_t, int64x2_t] - [float32x2_t, uint8x8_t] - [float32x2_t, uint16x4_t] - - [float32x2_t, uint32x2_t] - [float32x2_t, uint64x1_t] - [float32x4_t, uint8x16_t] - [float32x4_t, uint16x8_t] - - [float32x4_t, uint32x4_t] - [float32x4_t, uint64x2_t] - [float32x2_t, poly8x8_t] - [float32x2_t, poly16x4_t] @@ -8880,19 +8748,15 @@ intrinsics: - [float32x4_t, p128] - [int8x8_t, float32x2_t] - [int16x4_t, float32x2_t] - - [int32x2_t, float32x2_t] - [int64x1_t, float32x2_t] - [int8x16_t, float32x4_t] - [int16x8_t, float32x4_t] - - [int32x4_t, float32x4_t] - [int64x2_t, float32x4_t] - [uint8x8_t, float32x2_t] - [uint16x4_t, float32x2_t] - - [uint32x2_t, float32x2_t] - [uint64x1_t, float32x2_t] - [uint8x16_t, float32x4_t] - [uint16x8_t, float32x4_t] - - [uint32x4_t, float32x4_t] - [uint64x2_t, float32x4_t] - [poly8x8_t, float32x2_t] - [poly16x4_t, float32x2_t] @@ -8902,6 +8766,60 @@ intrinsics: compose: - FnCall: [transmute, [a]] + - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}" + doc: Vector reinterpret cast operation + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] + - *neon-not-arm-stable + - *neon-cfg-arm-unstable + safety: safe + types: + - [uint8x8_t, int8x8_t] + - [poly8x8_t, int8x8_t] + - [poly16x4_t, int16x4_t] + - [uint16x4_t, int16x4_t] + - [uint32x2_t, int32x2_t] + - [uint64x1_t, int64x1_t] + - [uint8x16_t, int8x16_t] + - [poly8x16_t, int8x16_t] + - [poly16x8_t, int16x8_t] + - [uint16x8_t, int16x8_t] + - [uint32x4_t, int32x4_t] + - [uint64x2_t, int64x2_t] + - [poly8x8_t, uint8x8_t] + - [int8x8_t, uint8x8_t] + - [poly16x4_t, uint16x4_t] + - [int16x4_t, uint16x4_t] + - [int32x2_t, uint32x2_t] + - [int64x1_t, uint64x1_t] + - [poly8x16_t, uint8x16_t] + - [int8x16_t, uint8x16_t] + - [poly16x8_t, uint16x8_t] + - [int16x8_t, uint16x8_t] + - [int32x4_t, uint32x4_t] + - [int64x2_t, uint64x2_t] + - [int8x8_t, poly8x8_t] + - [uint8x8_t, poly8x8_t] + - [int16x4_t, poly16x4_t] + - [uint16x4_t, poly16x4_t] + - [int8x16_t, poly8x16_t] + - [uint8x16_t, poly8x16_t] + - [int16x8_t, poly16x8_t] + - [uint16x8_t, poly16x8_t] + - [float32x2_t, int32x2_t] + - [float32x4_t, int32x4_t] + - [float32x2_t, uint32x2_t] + - [float32x4_t, uint32x4_t] + - [int32x2_t, float32x2_t] + - [int32x4_t, float32x4_t] + - [uint32x2_t, float32x2_t] + - [uint32x4_t, float32x4_t] + compose: + - FnCall: [transmute, [a]] - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}" doc: Vector reinterpret cast operation @@ -8918,54 +8836,73 @@ intrinsics: types: # non-q - [float32x2_t, float16x4_t] - - [poly16x4_t, float16x4_t] - [poly8x8_t, float16x4_t] - [int8x8_t, float16x4_t] - - [int16x4_t, float16x4_t] - [int32x2_t, float16x4_t] - [int64x1_t, float16x4_t] - [uint8x8_t, float16x4_t] - - [uint16x4_t, float16x4_t] - [uint32x2_t, float16x4_t] - [uint64x1_t, float16x4_t] - [float16x4_t, float32x2_t] - - [float16x4_t, poly16x4_t] - [float16x4_t, poly8x8_t] - [float16x4_t, int8x8_t] - - [float16x4_t, int16x4_t] - [float16x4_t, int32x2_t] - [float16x4_t, int64x1_t] - [float16x4_t, uint8x8_t] - - [float16x4_t, uint16x4_t] - [float16x4_t, uint32x2_t] - [float16x4_t, uint64x1_t] # q - [float32x4_t, float16x8_t] - - [poly16x8_t, float16x8_t] - [poly8x16_t, float16x8_t] - [int8x16_t, float16x8_t] - - [int16x8_t, float16x8_t] - [int32x4_t, float16x8_t] - [int64x2_t, float16x8_t] - [uint8x16_t, float16x8_t] - - [uint16x8_t, float16x8_t] - [uint32x4_t, float16x8_t] - [uint64x2_t, float16x8_t] - [float16x8_t, float32x4_t] - - [float16x8_t, poly16x8_t] - [float16x8_t, poly8x16_t] - [float16x8_t, int8x16_t] - - [float16x8_t, int16x8_t] - [float16x8_t, int32x4_t] - [float16x8_t, int64x2_t] - [float16x8_t, uint8x16_t] - - [float16x8_t, uint16x8_t] - [float16x8_t, uint32x4_t] - [float16x8_t, uint64x2_t] compose: - FnCall: [transmute, [a]] + - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}" + doc: Vector reinterpret cast operation + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] + - *neon-not-arm-stable-fp16 + - *neon-cfg-arm-unstable + - *target-not-arm64ec + safety: safe + types: + # non-q + - [poly16x4_t, float16x4_t] + - [int16x4_t, float16x4_t] + - [uint16x4_t, float16x4_t] + - [float16x4_t, poly16x4_t] + - [float16x4_t, int16x4_t] + - [float16x4_t, uint16x4_t] + # q + - [poly16x8_t, float16x8_t] + - [int16x8_t, float16x8_t] + - [uint16x8_t, float16x8_t] + - [float16x8_t, poly16x8_t] + - [float16x8_t, int16x8_t] + - [float16x8_t, uint16x8_t] + compose: + - FnCall: [transmute, [a]] + + - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}" doc: Vector reinterpret cast operation arguments: ["a: {type[0]}"] @@ -9002,6 +8939,7 @@ intrinsics: - *neon-cfg-arm-unstable - *target-not-arm64ec safety: safe + big_endian_inverse: true types: - [float16x4_t, "[3, 2, 1, 0]"] - [float16x8_t, "[3, 2, 1, 0, 7, 6, 5, 4]"] @@ -9354,6 +9292,7 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const LANE: i32'] safety: safe + big_endian_inverse: true types: - ["i8", int8x8_t, '3'] - ["i16", int16x4_t, '2'] @@ -9394,6 +9333,7 @@ intrinsics: - *target-not-arm64ec static_defs: ['const LANE: i32'] safety: safe + big_endian_inverse: true types: - ["f16", float16x4_t, '2'] - ["f16", float16x8_t, '3'] @@ -9415,6 +9355,7 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const LANE: i32'] safety: safe + big_endian_inverse: true types: - ["i64", int64x1_t, int64x1_t] - ["u64", uint64x1_t, uint64x1_t] @@ -9436,6 +9377,7 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const LANE: i32'] safety: safe + big_endian_inverse: true types: - ["p64", poly64x1_t, poly64x1_t] compose: @@ -9456,6 +9398,7 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const LANE: i32'] safety: safe + big_endian_inverse: true types: - ["p64", poly64x2_t, poly64x2_t] compose: @@ -9782,6 +9725,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - [int8x8_t, int8x8x2_t, '[0, 8, 2, 10, 4, 12, 6, 14]', '[1, 9, 3, 11, 5, 13, 7, 15]'] - [int16x4_t, int16x4x2_t, '[0, 4, 2, 6]', '[1, 5, 3, 7]'] @@ -9826,6 +9770,7 @@ intrinsics: - *neon-cfg-arm-unstable - *target-not-arm64ec safety: safe + big_endian_inverse: true types: - [float16x4_t, float16x4x2_t, '[0, 4, 2, 6]', '[1, 5, 3, 7]'] - [float16x8_t, float16x8x2_t, '[0, 8, 2, 10, 4, 12, 6, 14]', '[1, 9, 3, 11, 5, 13, 7, 15]'] @@ -9855,6 +9800,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - [int32x2_t, int32x2x2_t, '[0, 2]', '[1, 3]'] - [uint32x2_t, uint32x2x2_t, '[0, 2]', '[1, 3]'] @@ -9884,6 +9830,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - [int8x16_t, int8x16x2_t, '[0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]', '[8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]'] - [int16x8_t, int16x8x2_t, '[0, 8, 1, 9, 2, 10, 3, 11]', '[4, 12, 5, 13, 6, 14, 7, 15]'] @@ -9919,6 +9866,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - [int32x2_t, int32x2x2_t, '[0, 2]', '[1, 3]'] - [uint32x2_t, uint32x2x2_t, '[0, 2]', '[1, 3]'] @@ -9948,6 +9896,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - [int8x8_t, int8x8x2_t, '[0, 8, 1, 9, 2, 10, 3, 11]', '[4, 12, 5, 13, 6, 14, 7, 15]'] - [int16x4_t, int16x4x2_t, '[0, 4, 1, 5]', '[2, 6, 3, 7]'] @@ -9983,6 +9932,7 @@ intrinsics: - *neon-cfg-arm-unstable - *target-not-arm64ec safety: safe + big_endian_inverse: true types: - [float16x4_t, float16x4x2_t, '[0, 4, 1, 5]', '[2, 6, 3, 7]'] - [float16x8_t, float16x8x2_t, '[0, 8, 1, 9, 2, 10, 3, 11]', '[4, 12, 5, 13, 6, 14, 7, 15]'] @@ -10011,6 +9961,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - [int8x8_t, int8x8x2_t, '[0, 2, 4, 6, 8, 10, 12, 14]', '[1, 3, 5, 7, 9, 11, 13, 15]'] - [int16x4_t, int16x4x2_t, '[0, 2, 4, 6]', '[1, 3, 5, 7]'] @@ -10055,6 +10006,7 @@ intrinsics: - *neon-cfg-arm-unstable - *target-not-arm64ec safety: safe + big_endian_inverse: true types: - [float16x4_t, float16x4x2_t, '[0, 2, 4, 6]', '[1, 3, 5, 7]'] - [float16x8_t, float16x8x2_t, '[0, 2, 4, 6, 8, 10, 12, 14]', '[1, 3, 5, 7, 9, 11, 13, 15]'] @@ -10084,6 +10036,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - [float32x2_t, float32x2x2_t, '[0, 2]', '[1, 3]'] - [int32x2_t, int32x2x2_t, '[0, 2]', '[1, 3]'] @@ -10817,9 +10770,9 @@ intrinsics: static_defs: ['const N: i32'] safety: safe types: - - [uint16x8_t, uint8x8_t, '8', 'const { uint16x8_t([-N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16]) }'] - - [uint32x4_t, uint16x4_t, '16', 'const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }'] - - [uint64x2_t, uint32x2_t, '32', 'const { uint64x2_t([-N as u64, -N as u64]) }'] + - [uint16x8_t, uint8x8_t, '8', 'const { uint16x8_t([-N as u16; 8]) }'] + - [uint32x4_t, uint16x4_t, '16', 'const { uint32x4_t([-N as u32; 4]) }'] + - [uint64x2_t, uint32x2_t, '32', 'const { uint64x2_t([-N as u64; 2]) }'] compose: - FnCall: [static_assert!, ['N >= 1 && N <= {type[2]}']] - LLVMLink: @@ -11017,21 +10970,21 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [_lane_s16, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_laneq_s16, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_lane_s16, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_s16, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_lane_u16, uint16x4_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_laneq_u16, uint16x4_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_lane_u16, uint16x8_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_u16, uint16x8_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_s16, int16x4_t, int16x4_t, '2'] + - [_laneq_s16, int16x4_t, int16x8_t, '3'] + - [q_lane_s16, int16x8_t, int16x4_t, '2'] + - [q_laneq_s16, int16x8_t, int16x8_t, '3'] + - [_lane_u16, uint16x4_t, uint16x4_t, '2'] + - [_laneq_u16, uint16x4_t, uint16x8_t, '3'] + - [q_lane_u16, uint16x8_t, uint16x4_t, '2'] + - [q_laneq_u16, uint16x8_t, uint16x8_t, '3'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: - "vmla{neon_type[1].no}" - - a - b - - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + - FnCall: ['vdup{type[0]}', [c], [LANE]] - name: "vmla{type[0]}" doc: "Vector multiply accumulate with scalar" @@ -11047,21 +11000,21 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [_lane_s32, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [_laneq_s32, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]'] - - [q_lane_s32, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_s32, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_lane_u32, uint32x2_t, uint32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [_laneq_u32, uint32x2_t, uint32x4_t, '2', '[LANE as u32, LANE as u32]'] - - [q_lane_u32, uint32x4_t, uint32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_u32, uint32x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_s32, int32x2_t, int32x2_t, '1'] + - [_laneq_s32, int32x2_t, int32x4_t, '2'] + - [q_lane_s32, int32x4_t, int32x2_t, '1'] + - [q_laneq_s32, int32x4_t, int32x4_t, '2'] + - [_lane_u32, uint32x2_t, uint32x2_t, '1'] + - [_laneq_u32, uint32x2_t, uint32x4_t, '2'] + - [q_lane_u32, uint32x4_t, uint32x2_t, '1'] + - [q_laneq_u32, uint32x4_t, uint32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: - "vmla{neon_type[1].no}" - - a - b - - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + - FnCall: ['vdup{type[0]}', [c], [LANE]] - name: "vmla{type[0]}" doc: "Vector multiply accumulate with scalar" @@ -11077,17 +11030,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [_lane_f32, float32x2_t, float32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [_laneq_f32, float32x2_t, float32x4_t, '2', '[LANE as u32, LANE as u32]'] - - [q_lane_f32, float32x4_t, float32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_f32, float32x4_t, float32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_f32, float32x2_t, float32x2_t, '1'] + - [_laneq_f32, float32x2_t, float32x4_t, '2'] + - [q_lane_f32, float32x4_t, float32x2_t, '1'] + - [q_laneq_f32, float32x4_t, float32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: - "vmla{neon_type[1].no}" - - a - b - - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + - FnCall: ['vdup{type[0]}', [c], [LANE]] - name: "vmls{neon_type[0].N}" doc: "Vector multiply subtract with scalar" @@ -11166,21 +11119,21 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [_lane_s16, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_laneq_s16, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_lane_s16, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_s16, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_lane_u16, uint16x4_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_laneq_u16, uint16x4_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_lane_u16, uint16x8_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_u16, uint16x8_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_s16, int16x4_t, int16x4_t, '2'] + - [_laneq_s16, int16x4_t, int16x8_t, '3'] + - [q_lane_s16, int16x8_t, int16x4_t, '2'] + - [q_laneq_s16, int16x8_t, int16x8_t, '3'] + - [_lane_u16, uint16x4_t, uint16x4_t, '2'] + - [_laneq_u16, uint16x4_t, uint16x8_t, '3'] + - [q_lane_u16, uint16x8_t, uint16x4_t, '2'] + - [q_laneq_u16, uint16x8_t, uint16x8_t, '3'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: - "vmls{neon_type[1].no}" - - a - b - - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + - FnCall: ['vdup{type[0]}', [c], [LANE]] - name: "vmls{type[0]}" doc: "Vector multiply subtract with scalar" @@ -11196,21 +11149,21 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [_lane_s32, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [_laneq_s32, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]'] - - [q_lane_s32, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_s32, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_lane_u32, uint32x2_t, uint32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [_laneq_u32, uint32x2_t, uint32x4_t, '2', '[LANE as u32, LANE as u32]'] - - [q_lane_u32, uint32x4_t, uint32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_u32, uint32x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_s32, int32x2_t, int32x2_t, '1'] + - [_laneq_s32, int32x2_t, int32x4_t, '2'] + - [q_lane_s32, int32x4_t, int32x2_t, '1'] + - [q_laneq_s32, int32x4_t, int32x4_t, '2'] + - [_lane_u32, uint32x2_t, uint32x2_t, '1'] + - [_laneq_u32, uint32x2_t, uint32x4_t, '2'] + - [q_lane_u32, uint32x4_t, uint32x2_t, '1'] + - [q_laneq_u32, uint32x4_t, uint32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: - "vmls{neon_type[1].no}" - - a - b - - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + - FnCall: ['vdup{type[0]}', [c], [LANE]] - name: "vmls{type[0]}" doc: "Vector multiply subtract with scalar" @@ -11226,17 +11179,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [_lane_f32, float32x2_t, float32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [_laneq_f32, float32x2_t, float32x4_t, '2', '[LANE as u32, LANE as u32]'] - - [q_lane_f32, float32x4_t, float32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_f32, float32x4_t, float32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_f32, float32x2_t, float32x2_t, '1'] + - [_laneq_f32, float32x2_t, float32x4_t, '2'] + - [q_lane_f32, float32x4_t, float32x2_t, '1'] + - [q_laneq_f32, float32x4_t, float32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: - "vmls{neon_type[1].no}" - - a - b - - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + - FnCall: ['vdup{type[0]}', [c], [LANE]] - name: "vmul{neon_type[0].N}" doc: "Vector multiply by scalar" @@ -11321,16 +11274,16 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [float32x2_t, float32x2_t, '_lane_f32', '1', '[LANE as u32, LANE as u32]'] - - [float32x2_t, float32x4_t, '_laneq_f32', '2', '[LANE as u32, LANE as u32]'] - - [float32x4_t, float32x2_t, 'q_lane_f32', '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [float32x4_t, float32x4_t, 'q_laneq_f32', '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [float32x2_t, float32x2_t, '_lane_f32', '1'] + - [float32x2_t, float32x4_t, '_laneq_f32', '2'] + - [float32x4_t, float32x2_t, 'q_lane_f32', '1'] + - [float32x4_t, float32x4_t, 'q_laneq_f32', '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: - simd_mul - - a - - FnCall: [simd_shuffle!, [b, b, "{type[4]}"]] + - FnCall: ['vdup{type[2]}', [b], [LANE]] - name: "vqrdmulh{type[0]}" doc: "Vector rounding saturating doubling multiply high by scalar" @@ -11346,17 +11299,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [_lane_s16, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_laneq_s16, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_lane_s16, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_s16, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_lane_s32, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [_laneq_s32, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]'] - - [q_lane_s32, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_s32, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_s16, int16x4_t, int16x4_t, '2'] + - [_laneq_s16, int16x4_t, int16x8_t, '3'] + - [q_lane_s16, int16x8_t, int16x4_t, '2'] + - [q_laneq_s16, int16x8_t, int16x8_t, '3'] + - [_lane_s32, int32x2_t, int32x2_t, '1'] + - [_laneq_s32, int32x2_t, int32x4_t, '2'] + - [q_lane_s32, int32x4_t, int32x2_t, '1'] + - [q_laneq_s32, int32x4_t, int32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] - - Let: [b, "{neon_type[1]}", {FnCall: [simd_shuffle!, [b, b, '{type[4]}']]}] + - Let: [b, {FnCall: ['vdup{type[0]}', [b], [LANE]]}] - FnCall: ["vqrdmulh{neon_type[1].no}", [a, b]] - name: "vqrdmulh{neon_type[0].N}" @@ -11473,16 +11426,16 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [int16x4_t, int16x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int16x4_t, int16x8_t, int32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int32x2_t, int32x2_t, int64x2_t, '1', '[LANE as u32, LANE as u32]'] - - [int32x2_t, int32x4_t, int64x2_t, '2', '[LANE as u32, LANE as u32]'] + - [int16x4_t, int16x4_t, int32x4_t, '2'] + - [int16x4_t, int16x8_t, int32x4_t, '3'] + - [int32x2_t, int32x2_t, int64x2_t, '1'] + - [int32x2_t, int32x4_t, int64x2_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] - FnCall: - "vmull_{neon_type[0]}" - - a - - FnCall: [simd_shuffle!, [b, b, "{type[4]}"]] + - FnCall: ['vdup_lane{neon_type[1].nox}', [b], [LANE]] - name: "vmull_lane{neon_type[1].no}" doc: "Vector long multiply by scalar" @@ -11498,16 +11451,16 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [uint16x4_t, uint16x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint16x4_t, uint16x8_t, uint32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint32x2_t, uint32x2_t, uint64x2_t, '1', '[LANE as u32, LANE as u32]'] - - [uint32x2_t, uint32x4_t, uint64x2_t, '2', '[LANE as u32, LANE as u32]'] + - [uint16x4_t, uint16x4_t, uint32x4_t, '2'] + - [uint16x4_t, uint16x8_t, uint32x4_t, '3'] + - [uint32x2_t, uint32x2_t, uint64x2_t, '1'] + - [uint32x2_t, uint32x4_t, uint64x2_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] - FnCall: - "vmull_{neon_type[0]}" - - a - - FnCall: [simd_shuffle!, [b, b, "{type[4]}"]] + - FnCall: ['vdup_lane{neon_type[1].nox}', [b], [LANE]] - name: "vfms{neon_type[0].N}" doc: "Floating-point fused Multiply-subtract to accumulator(vector)" @@ -11577,7 +11530,7 @@ intrinsics: - - a - FnCall: - "vdup{neon_type[0].N}" - - - FnCall: [simd_extract!, [b, 'LANE as u32']] + - - FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]] - name: "vrecpe{neon_type.no}" doc: "Unsigned reciprocal estimate" @@ -12437,19 +12390,10 @@ intrinsics: safety: unsafe: [neon] types: - - ["*const f16", float16x4x4_t, f16] - - ["*const f16", float16x8x4_t, f16] + - ["*const f16", float16x4x4_t, f16, "4"] + - ["*const f16", float16x8x4_t, f16, "8"] compose: - - LLVMLink: - name: "vld4.{neon_type[1]}" - arguments: - - "ptr: {type[0]}" - links: - - link: "llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0" - arch: aarch64,arm64ec - - FnCall: - - "_vld4{neon_type[1].nox}" - - - "a as _" + - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "4", a], [], true] - name: "vld4{neon_type[1].dup_nox}" doc: Load single 4-element structure and replicate to all lanes of two registers @@ -12612,6 +12556,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - [float32x2_t, float32x4_t, '[0, 1, 2, 3]'] - [poly8x8_t, poly8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] @@ -12639,6 +12584,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - uint8x16_t compose: @@ -12661,6 +12607,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - uint8x16_t compose: @@ -12683,6 +12630,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [uint8x16_t, "aesmc"] compose: @@ -12705,6 +12653,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [uint8x16_t, "aesimc"] compose: @@ -12727,6 +12676,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [u32, "sha1h"] compose: @@ -12749,6 +12699,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [u32, "sha1c", "uint32x4_t"] compose: @@ -12771,6 +12722,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [u32, "sha1m", "uint32x4_t"] compose: @@ -12793,6 +12745,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [u32, "sha1p", "uint32x4_t"] compose: @@ -12815,6 +12768,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [uint32x4_t, "sha1su0"] compose: @@ -12837,6 +12791,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [uint32x4_t, "sha1su1"] compose: @@ -12859,6 +12814,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [uint32x4_t, "sha256h"] compose: @@ -12881,6 +12837,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [uint32x4_t, "sha256h2"] compose: @@ -12903,6 +12860,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [uint32x4_t, "sha256su0"] compose: @@ -12925,6 +12883,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [uint32x4_t, "sha256su1"] compose: @@ -13162,6 +13121,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - int8x8_t - int16x4_t @@ -13186,6 +13146,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - uint8x8_t - uint16x4_t @@ -13210,6 +13171,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - float32x2_t compose: @@ -13232,6 +13194,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - int8x8_t - int16x4_t @@ -13256,6 +13219,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - uint8x8_t - uint16x4_t @@ -13280,6 +13244,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - float32x2_t compose: @@ -13345,14 +13310,14 @@ intrinsics: attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"{type[3]}"']]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [raddhn2]]}]] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [raddhn2]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe types: - - [uint8x8_t , uint16x8_t, uint8x16_t, 'vraddhn.i16', int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, uint32x4_t, uint16x8_t, 'vraddhn.i32', int32x4_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, uint64x2_t, uint32x4_t, 'vraddhn.i64', int64x2_t, '[0, 1, 2, 3]'] + - [uint8x8_t , uint16x8_t, uint8x16_t, 'vraddhn.i16', int16x8_t] + - [uint16x4_t, uint32x4_t, uint16x8_t, 'vraddhn.i32', int32x4_t] + - [uint32x2_t, uint64x2_t, uint32x4_t, 'vraddhn.i64', int64x2_t] compose: - Let: - x @@ -13363,7 +13328,7 @@ intrinsics: - "vraddhn{neon_type[4].noq}" - - FnCall: [transmute, [b]] - FnCall: [transmute, [c]] - - FnCall: ["simd_shuffle!", [a, x, '{type[5]}']] + - FnCall: ['vcombine_{neon_type[0]}', [a, x]] - name: "vraddhn_high{neon_type[1].noq}" doc: "Rounding Add returning High Narrow (high half)." @@ -13372,14 +13337,14 @@ intrinsics: attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"{type[3]}"']]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [raddhn2]]}]] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [raddhn2]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe types: - - [int8x8_t , int16x8_t, int8x16_t, 'vraddhn.i16', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [int16x4_t, int32x4_t, int16x8_t, 'vraddhn.i32', '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [int32x2_t, int64x2_t, int32x4_t, 'vraddhn.i64', '[0, 1, 2, 3]'] + - [int8x8_t , int16x8_t, int8x16_t, 'vraddhn.i16'] + - [int16x4_t, int32x4_t, int16x8_t, 'vraddhn.i32'] + - [int32x2_t, int64x2_t, int32x4_t, 'vraddhn.i64'] compose: - Let: - x @@ -13387,7 +13352,7 @@ intrinsics: - "vraddhn{neon_type[1].noq}" - - b - c - - FnCall: ["simd_shuffle!", [a, x, '{type[4]}']] + - FnCall: ['vcombine_{neon_type[0]}', [a, x]] - name: "vpadd{neon_type.no}" doc: "Add pairwise." @@ -13400,6 +13365,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - int8x8_t - int16x4_t @@ -14250,6 +14216,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [nop] safety: safe + big_endian_inverse: true types: - [float16x4_t, float16x8_t] compose: @@ -14267,6 +14234,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [nop] safety: safe + big_endian_inverse: true types: - [float16x4_t, float16x8_t, 'low', "[0, 1, 2, 3]"] - [float16x4_t, float16x8_t, 'high', "[4, 5, 6, 7]"] @@ -14287,6 +14255,7 @@ intrinsics: - *target-not-arm64ec static_defs: ['const LANE: i32'] safety: safe + big_endian_inverse: true types: - [float16x4_t, f16, '_lane_f16', '2'] - [float16x8_t, f16, 'q_lane_f16', '3'] @@ -14441,7 +14410,6 @@ intrinsics: doc: "Load one single-element structure and Replicate to all lanes (of one register)." arguments: ["ptr: {type[1]}"] return_type: "{neon_type[2]}" - big_endian_inverse: false attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ['"{type[3]}"']] } ]] @@ -14597,26 +14565,26 @@ intrinsics: attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ['{type[3]}']] } ]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, { FnCall: [assert_instr, ['{type[4]}']]}] ] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, { FnCall: [assert_instr, ['{type[4]}']]}] ] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe types: - - ['vaddl_high_s8', 'int8x16_t', 'int16x8_t', 'vaddl', 'saddl2', 'int8x8_t', '[8, 9, 10, 11, 12, 13, 14, 15]'] - - ['vaddl_high_s16', 'int16x8_t', 'int32x4_t', 'vaddl', 'saddl2', 'int16x4_t', '[4, 5, 6, 7]'] - - ['vaddl_high_s32', 'int32x4_t', 'int64x2_t', 'vaddl', 'saddl2', 'int32x2_t', '[2, 3]'] - - ['vaddl_high_u8', 'uint8x16_t', 'uint16x8_t', 'vaddl', 'uaddl2', 'uint8x8_t', '[8, 9, 10, 11, 12, 13, 14, 15]'] - - ['vaddl_high_u16', 'uint16x8_t', 'uint32x4_t', 'vaddl', 'uaddl2', 'uint16x4_t', '[4, 5, 6, 7]'] - - ['vaddl_high_u32', 'uint32x4_t', 'uint64x2_t', 'vaddl', 'uaddl2', 'uint32x2_t', '[2, 3]'] + - ['vaddl_high_s8', 'int8x16_t', 'int16x8_t', 'vaddl', 'saddl2', 'int8x8_t'] + - ['vaddl_high_s16', 'int16x8_t', 'int32x4_t', 'vaddl', 'saddl2', 'int16x4_t'] + - ['vaddl_high_s32', 'int32x4_t', 'int64x2_t', 'vaddl', 'saddl2', 'int32x2_t'] + - ['vaddl_high_u8', 'uint8x16_t', 'uint16x8_t', 'vaddl', 'uaddl2', 'uint8x8_t'] + - ['vaddl_high_u16', 'uint16x8_t', 'uint32x4_t', 'vaddl', 'uaddl2', 'uint16x4_t'] + - ['vaddl_high_u32', 'uint32x4_t', 'uint64x2_t', 'vaddl', 'uaddl2', 'uint32x2_t'] compose: - Let: - a - '{neon_type[5]}' - - FnCall: ['simd_shuffle!', [a, a, '{type[6]}']] + - FnCall: ['vget_high_{neon_type[1]}', [a]] - Let: - b - '{neon_type[5]}' - - FnCall: ['simd_shuffle!', [b, b, '{type[6]}']] + - FnCall: ['vget_high_{neon_type[1]}', [b]] - Let: [a, '{neon_type[2]}', {FnCall: [simd_cast, [a]]}] - Let: [b, '{neon_type[2]}', {FnCall: [simd_cast, [b]]}] - FnCall: [simd_add, [a, b]] @@ -14653,22 +14621,21 @@ intrinsics: attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ['{type[3]}']] } ]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, { FnCall: [assert_instr, ['{type[4]}']]}] ] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, { FnCall: [assert_instr, ['{type[4]}']]}] ] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe types: - - ['vaddw_high_s8', 'int16x8_t', 'int8x16_t', 'vaddw', 'saddw2', 'int8x8_t', '[8, 9, 10, 11, 12, 13, 14, 15]'] - - ['vaddw_high_s16', 'int32x4_t', 'int16x8_t', 'vaddw', 'saddw2', 'int16x4_t', '[4, 5, 6, 7]'] - - ['vaddw_high_s32', 'int64x2_t', 'int32x4_t', 'vaddw', 'saddw2', 'int32x2_t', '[2, 3]'] - - ['vaddw_high_u8', 'uint16x8_t', 'uint8x16_t', 'vaddw', 'uaddw2', 'uint8x8_t', '[8, 9, 10, 11, 12, 13, 14, 15]'] - - ['vaddw_high_u16', 'uint32x4_t', 'uint16x8_t', 'vaddw', 'uaddw2', 'uint16x4_t', '[4, 5, 6, 7]'] - - ['vaddw_high_u32', 'uint64x2_t', 'uint32x4_t', 'vaddw', 'uaddw2', 'uint32x2_t', '[2, 3]'] + - ['vaddw_high_s8', 'int16x8_t', 'int8x16_t', 'vaddw', 'saddw2', 'int8x8_t'] + - ['vaddw_high_s16', 'int32x4_t', 'int16x8_t', 'vaddw', 'saddw2', 'int16x4_t'] + - ['vaddw_high_s32', 'int64x2_t', 'int32x4_t', 'vaddw', 'saddw2', 'int32x2_t'] + - ['vaddw_high_u8', 'uint16x8_t', 'uint8x16_t', 'vaddw', 'uaddw2', 'uint8x8_t'] + - ['vaddw_high_u16', 'uint32x4_t', 'uint16x8_t', 'vaddw', 'uaddw2', 'uint16x4_t'] + - ['vaddw_high_u32', 'uint64x2_t', 'uint32x4_t', 'vaddw', 'uaddw2', 'uint32x2_t'] compose: - Let: - b - - '{neon_type[5]}' - - FnCall: ['simd_shuffle!', [b, b, '{type[6]}']] + - FnCall: ['vget_high_{neon_type[2]}', [b]] - Let: - b - '{neon_type[1]}' @@ -14711,17 +14678,17 @@ intrinsics: attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ['vaddhn']] } ]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, { FnCall: [assert_instr, ['addhn2']]}] ] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, { FnCall: [assert_instr, ['addhn2']]}] ] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe types: - - ['vaddhn_high_s16', 'int8x8_t', 'int16x8_t', 'int8x16_t', 'int16x8_t::splat(8)', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - ['vaddhn_high_s32', 'int16x4_t', 'int32x4_t', 'int16x8_t', 'int32x4_t::splat(16)', '[0, 1, 2, 3, 4, 5, 6, 7]'] - - ['vaddhn_high_s64', 'int32x2_t', 'int64x2_t', 'int32x4_t', 'int64x2_t::splat(32)', '[0, 1, 2, 3]'] - - ['vaddhn_high_u16', 'uint8x8_t', 'uint16x8_t', 'uint8x16_t', 'uint16x8_t::splat(8)', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - ['vaddhn_high_u32', 'uint16x4_t', 'uint32x4_t', 'uint16x8_t', 'uint32x4_t::splat(16)', '[0, 1, 2, 3, 4, 5, 6, 7]'] - - ['vaddhn_high_u64', 'uint32x2_t', 'uint64x2_t', 'uint32x4_t', 'uint64x2_t::splat(32)', '[0, 1, 2, 3]'] + - ['vaddhn_high_s16', 'int8x8_t', 'int16x8_t', 'int8x16_t', 'int16x8_t::splat(8)'] + - ['vaddhn_high_s32', 'int16x4_t', 'int32x4_t', 'int16x8_t', 'int32x4_t::splat(16)'] + - ['vaddhn_high_s64', 'int32x2_t', 'int64x2_t', 'int32x4_t', 'int64x2_t::splat(32)'] + - ['vaddhn_high_u16', 'uint8x8_t', 'uint16x8_t', 'uint8x16_t', 'uint16x8_t::splat(8)'] + - ['vaddhn_high_u32', 'uint16x4_t', 'uint32x4_t', 'uint16x8_t', 'uint32x4_t::splat(16)'] + - ['vaddhn_high_u64', 'uint32x2_t', 'uint64x2_t', 'uint32x4_t', 'uint64x2_t::splat(32)'] compose: - Let: - x @@ -14734,7 +14701,7 @@ intrinsics: - - a - b - '{type[4]}' - - FnCall: ['simd_shuffle!', [r, x, '{type[5]}']] + - FnCall: ['vcombine_{neon_type[1]}', [r, x]] - name: "{type[0]}" doc: "Vector narrow integer." @@ -15040,6 +15007,7 @@ intrinsics: arguments: ["v: {neon_type[1]}"] return_type: "{type[2]}" safety: safe + big_endian_inverse: true static_defs: ['const IMM5: i32'] attr: - *neon-v7 @@ -15078,6 +15046,7 @@ intrinsics: arguments: ["v: {neon_type[1]}"] return_type: "{type[2]}" safety: safe + big_endian_inverse: true static_defs: ['const IMM5: i32'] attr: - *neon-v7 @@ -15119,16 +15088,21 @@ intrinsics: return_type: "{neon_type[2]}" attr: - *neon-v7 - - FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ['"{type[3]}"']]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, ['{type[4]}']]}]] + - FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ['vmov']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-le, {FnCall: [assert_instr, ['mov']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-be, {FnCall: [assert_instr, ['ext']]}]] + - FnCall: [cfg_attr, [*neon-target-arm64ec, {FnCall: [assert_instr, ['dup']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-windows, {FnCall: [assert_instr, ['dup']]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - - ['vget_high_s64', 'int64x2_t', 'int64x1_t', 'vmov', 'ext', 'unsafe { int64x1_t([simd_extract!(a, 1)]) }'] - - ['vget_high_u64', 'uint64x2_t', 'uint64x1_t', 'vmov', 'ext', 'unsafe { uint64x1_t([simd_extract!(a, 1)]) }'] + - ['vget_high_s64', 'int64x2_t', 'int64x1_t', 'int64x1_t([simd_extract!(a, 1)])'] + - ['vget_high_u64', 'uint64x2_t', 'uint64x1_t', 'uint64x1_t([simd_extract!(a, 1)])'] + - ['vget_high_p64', 'poly64x2_t', 'poly64x1_t', 'transmute(u64x1::new(simd_extract!(a, 1)))'] compose: - - Identifier: ['{type[5]}', Symbol] + - Identifier: ['{type[3]}', UnsafeSymbol] - name: "{type[0]}" doc: "Duplicate vector element to vector or scalar" @@ -15140,11 +15114,13 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - - ['vget_low_s64', 'int64x2_t', 'int64x1_t', 'unsafe { int64x1_t([simd_extract!(a, 0)]) }'] - - ['vget_low_u64', 'uint64x2_t', 'uint64x1_t', 'unsafe { uint64x1_t([simd_extract!(a, 0)]) }'] + - ['vget_low_s64', 'int64x2_t', 'int64x1_t', 'int64x1_t([simd_extract!(a, 0)])'] + - ['vget_low_u64', 'uint64x2_t', 'uint64x1_t', 'uint64x1_t([simd_extract!(a, 0)])'] + - ['vget_low_p64', 'poly64x2_t', 'poly64x1_t', 'transmute(u64x1::new(simd_extract!(a, 0)))'] compose: - - Identifier: ['{type[3]}', Symbol] + - Identifier: ['{type[3]}', UnsafeSymbol] - name: "{type[0]}" doc: "Duplicate vector element to vector or scalar" @@ -15152,23 +15128,27 @@ intrinsics: return_type: "{neon_type[2]}" attr: - *neon-v7 - - FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ['"{type[3]}"']]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, ['{type[4]}']]}]] + - FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ['vmov']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-le, {FnCall: [assert_instr, ['mov']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-be, {FnCall: [assert_instr, ['ext']]}]] + - FnCall: [cfg_attr, [*neon-target-arm64ec, {FnCall: [assert_instr, ['dup']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-windows, {FnCall: [assert_instr, ['dup']]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - - ['vget_high_s8', 'int8x16_t', 'int8x8_t', 'vmov', 'ext', '[8, 9, 10, 11, 12, 13, 14, 15]'] - - ['vget_high_u8', 'uint8x16_t', 'uint8x8_t', 'vmov', 'ext', '[8, 9, 10, 11, 12, 13, 14, 15]'] - - ['vget_high_p8', 'poly8x16_t', 'poly8x8_t', 'vmov', 'ext', '[8, 9, 10, 11, 12, 13, 14, 15]'] - - ['vget_high_s16', 'int16x8_t', 'int16x4_t', 'vmov', 'ext', '[4, 5, 6, 7]'] - - ['vget_high_u16', 'uint16x8_t', 'uint16x4_t', 'vmov', 'ext', '[4, 5, 6, 7]'] - - ['vget_high_p16', 'poly16x8_t', 'poly16x4_t', 'vmov', 'ext', '[4, 5, 6, 7]'] - - ['vget_high_s32', 'int32x4_t', 'int32x2_t', 'vmov', 'ext', '[2, 3]'] - - ['vget_high_u32', 'uint32x4_t', 'uint32x2_t', 'vmov', 'ext', '[2, 3]'] - - ['vget_high_f32', 'float32x4_t', 'float32x2_t', 'vmov', 'ext', '[2, 3]'] + - ['vget_high_s8', 'int8x16_t', 'int8x8_t', '[8, 9, 10, 11, 12, 13, 14, 15]'] + - ['vget_high_u8', 'uint8x16_t', 'uint8x8_t', '[8, 9, 10, 11, 12, 13, 14, 15]'] + - ['vget_high_p8', 'poly8x16_t', 'poly8x8_t', '[8, 9, 10, 11, 12, 13, 14, 15]'] + - ['vget_high_s16', 'int16x8_t', 'int16x4_t', '[4, 5, 6, 7]'] + - ['vget_high_u16', 'uint16x8_t', 'uint16x4_t', '[4, 5, 6, 7]'] + - ['vget_high_p16', 'poly16x8_t', 'poly16x4_t', '[4, 5, 6, 7]'] + - ['vget_high_s32', 'int32x4_t', 'int32x2_t', '[2, 3]'] + - ['vget_high_u32', 'uint32x4_t', 'uint32x2_t', '[2, 3]'] + - ['vget_high_f32', 'float32x4_t', 'float32x2_t', '[2, 3]'] compose: - - FnCall: ['simd_shuffle!', [a, a, '{type[5]}']] + - FnCall: ['simd_shuffle!', [a, a, '{type[3]}']] - name: "{type[0]}" doc: "Duplicate vector element to vector or scalar" @@ -15180,6 +15160,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - ['vget_low_s8', 'int8x16_t', 'int8x8_t', '[0, 1, 2, 3, 4, 5, 6, 7]'] - ['vget_low_u8', 'uint8x16_t', 'uint8x8_t','[0, 1, 2, 3, 4, 5, 6, 7]'] @@ -15332,6 +15313,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - ['vrev16_s8', 'int8x8_t', 'vrev16.8', 'rev16', '[1, 0, 3, 2, 5, 4, 7, 6]'] - ['vrev16q_s8', 'int8x16_t', 'vrev16.8', 'rev16', '[1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]'] diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml new file mode 100644 index 0000000000000..0b2d17d3b195f --- /dev/null +++ b/library/stdarch/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml @@ -0,0 +1,5257 @@ +arch_cfgs: + - arch_name: aarch64 + target_feature: [sve] + llvm_prefix: llvm.aarch64.sve + +uses_neon_types: true +auto_llvm_sign_conversion: true +generate_load_store_tests: true + +# `#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]` +sve-unstable: &sve-unstable + FnCall: [unstable, ['feature = "stdarch_aarch64_sve"', 'issue= "145052"']] + +intrinsics: + - name: svacge[{_n}_{type}] + attr: [*sve-unstable] + doc: Absolute compare greater than or equal to + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64] + assert_instr: [facge] + n_variant_op: op2 + compose: + - LLVMLink: { name: "facge.{sve_type}" } + + - name: svacgt[{_n}_{type}] + attr: [*sve-unstable] + doc: Absolute compare greater than + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64] + assert_instr: [facgt] + n_variant_op: op2 + compose: + - LLVMLink: { name: "facgt.{sve_type}" } + + - name: svacle[{_n}_{type}] + attr: [*sve-unstable] + doc: Absolute compare less than or equal to + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64] + assert_instr: [facge] + n_variant_op: op2 + compose: + - FnCall: ["svacge_{type}", [$pg, $op2, $op1]] + + - name: svaclt[{_n}_{type}] + attr: [*sve-unstable] + doc: Absolute compare less than + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64] + assert_instr: [facgt] + n_variant_op: op2 + compose: + - FnCall: ["svacgt_{type}", [$pg, $op2, $op1]] + + - name: svcadd[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Complex add with rotate + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + static_defs: ["const IMM_ROTATION: i32"] + constraints: [{ variable: IMM_ROTATION, any_values: [90, 270] }] + assert_instr: [[fcadd, "IMM_ROTATION = 90"]] + zeroing_method: { select: op1 } + compose: + - LLVMLink: + name: fcadd.{sve_type} + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$pg, $op1, $op2, $IMM_ROTATION]] + + - name: svcmla[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Complex multiply-add with rotate + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64] + static_defs: ["const IMM_ROTATION: i32"] + constraints: [{ variable: IMM_ROTATION, any_values: [0, 90, 180, 270] }] + assert_instr: [[fcmla, "IMM_ROTATION = 90"]] + zeroing_method: { select: op1 } + compose: + - LLVMLink: + name: fcmla.{sve_type} + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$pg, $op1, $op2, $op3, $IMM_ROTATION]] + + - name: svcmla_lane[_{type}] + attr: [*sve-unstable] + doc: Complex multiply-add with rotate + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [f32] + static_defs: ["const IMM_INDEX: i32", "const IMM_ROTATION: i32"] + constraints: + - variable: IMM_INDEX + range: { match_size: "{type}", default: [0, 1], halfword: [0, 3] } + - { variable: IMM_ROTATION, any_values: [0, 90, 180, 270] } + assert_instr: [[fcmla, "IMM_INDEX = 0, IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: fcmla.lane.{sve_type} + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "imm_index: i32" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX, $IMM_ROTATION]] + + - name: svadd[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Add + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + assert_instr: ["{type_kind.f}add"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.f}add.{sve_type}" } + + - name: svqsub[{_n}_{type}] + attr: [*sve-unstable] + doc: Saturating subtract + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.su}qsub"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}qsub.x.{sve_type}" } + + - name: svcnt[_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Count nonzero bits + arguments: + ["inactive: {sve_type[1]}", "pg: {predicate[0]}", "op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [f32, u32] + - [f64, u64] + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + - [u8, u8] + - [u16, u16] + - [u32, u32] + - [u64, u64] + zeroing_method: { drop: inactive } + assert_instr: [cnt] + compose: + - LLVMLink: { name: "cnt.{sve_type[0]}" } + + - name: svcls[_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Count leading sign bits + arguments: + ["inactive: {sve_type[1]}", "pg: {predicate[0]}", "op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: [[i8, u8], [i16, u16], [i32, u32], [i64, u64]] + zeroing_method: { drop: inactive } + assert_instr: [cls] + compose: + - LLVMLink: { name: "cls.{sve_type[0]}" } + + - name: svclz[_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Count leading zero bits + arguments: + ["inactive: {sve_type[1]}", "pg: {predicate[0]}", "op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + - [u8, u8] + - [u16, u16] + - [u32, u32] + - [u64, u64] + zeroing_method: { drop: inactive } + assert_instr: [clz] + compose: + - LLVMLink: { name: "clz.{sve_type[0]}" } + + - name: svext{size_literal[1]}[_{type[0]}]{_mxz} + attr: [*sve-unstable] + substitutions: + sign_or_zero: + match_kind: "{type[0]}" + default: Sign + unsigned: Zero + kind_literal: { match_kind: "{type[0]}", default: s, unsigned: u } + doc: "{sign_or_zero}-extend the low {size[1]} bits" + arguments: + ["inactive: {sve_type[0]}", "pg: {predicate[0]}", "op: {sve_type[0]}"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], i8] + - [[i32, i64, u32, u64], i16] + - [[i64, u64], i32] + zeroing_method: { drop: inactive } + assert_instr: ["{type_kind[0].su}xt{size_literal[1]}"] + compose: + - LLVMLink: + name: "{type_kind[0].su}xt{size_literal[1]}.{sve_type[0]}" + + - name: svsqrt[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Square root + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + zeroing_method: { drop: inactive } + assert_instr: [fsqrt] + compose: + - LLVMLink: { name: "fsqrt.{sve_type}" } + + - name: svcmpeq[{_n}_{type}] + attr: [*sve-unstable] + doc: Compare equal to + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [{ float: fcmeq, default: cmpeq }] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.f}cmpeq.{sve_type}" } + + - name: svcmpeq_wide[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Compare equal to + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{predicate[0]}" + types: + - [[i8, i16, i32], i64] + assert_instr: [cmpeq] + n_variant_op: op2 + compose: + - LLVMLink: { name: "cmpeq.wide.{sve_type[0]}" } + + - name: svcmpge[{_n}_{type}] + attr: [*sve-unstable] + doc: Compare greater than or equal to + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [{ float: fcmge, default: cmpge, unsigned: cmphs }] + n_variant_op: op2 + compose: + - MatchKind: + - "{type}" + - default: + LLVMLink: { name: "{type_kind.f}cmpge.{sve_type}" } + unsigned: + LLVMLink: { name: "cmphs.{sve_type}" } + + - name: svcmpge_wide[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Compare greater than or equal to + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{predicate[0]}" + n_variant_op: op2 + types: + - [[i8, i16, i32], i64] + - [[u8, u16, u32], u64] + assert_instr: [{ default: cmpge, unsigned: cmphs }] + compose: + - MatchKind: + - "{type[0]}" + - default: + LLVMLink: { name: "cmpge.wide.{sve_type[0]}" } + unsigned: + LLVMLink: { name: "cmphs.wide.{sve_type[0]}" } + + - name: svcmpgt[{_n}_{type}] + attr: [*sve-unstable] + doc: Compare greater than + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [{ float: fcmgt, default: cmpgt, unsigned: cmphi }] + n_variant_op: op2 + compose: + - MatchKind: + - "{type}" + - default: + LLVMLink: { name: "{type_kind.f}cmpgt.{sve_type}" } + unsigned: + LLVMLink: { name: "cmphi.{sve_type}" } + + - name: svcmpgt_wide[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Compare greater than + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{predicate[0]}" + types: + - [[i8, i16, i32], i64] + - [[u8, u16, u32], u64] + assert_instr: [{ default: cmpgt, unsigned: cmphi }] + n_variant_op: op2 + compose: + - MatchKind: + - "{type[0]}" + - default: + LLVMLink: { name: "cmpgt.wide.{sve_type[0]}" } + unsigned: + LLVMLink: { name: "cmphi.wide.{sve_type[0]}" } + + - name: svcmple[{_n}_{type}] + attr: [*sve-unstable] + doc: Compare less than or equal to + arguments: ["pg: svbool_t", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "svbool_t" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [{ float: fcmge, default: cmpge, unsigned: cmphs }] + n_variant_op: op2 + compose: + - FnCall: ["svcmpge_{type}", [$pg, $op2, $op1]] + + - name: svcmple_wide[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Compare less than or equal to + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{predicate[0]}" + types: + - [[i8, i16, i32], i64] + - [[u8, u16, u32], u64] + assert_instr: [{ default: cmple, unsigned: cmpls }] + n_variant_op: op2 + compose: + - MatchKind: + - "{type[0]}" + - default: + LLVMLink: { name: "cmple.wide.{sve_type[0]}" } + unsigned: + LLVMLink: { name: "cmpls.wide.{sve_type[0]}" } + + - name: svcmplt[{_n}_{type}] + attr: [*sve-unstable] + doc: Compare less than + arguments: ["pg: svbool_t", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "svbool_t" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [{ float: fcmgt, default: cmpgt, unsigned: cmphi }] + n_variant_op: op2 + compose: + - FnCall: ["svcmpgt_{type}", [$pg, $op2, $op1]] + + - name: svcmplt_wide[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Compare less than + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{predicate[0]}" + types: + - [[i8, i16, i32], i64] + - [[u8, u16, u32], u64] + assert_instr: [{ default: cmplt, unsigned: cmplo }] + n_variant_op: op2 + compose: + - MatchKind: + - "{type[0]}" + - default: + LLVMLink: { name: "cmplt.wide.{sve_type[0]}" } + unsigned: + LLVMLink: { name: "cmplo.wide.{sve_type[0]}" } + + - name: svcmpne[{_n}_{type}] + attr: [*sve-unstable] + doc: Compare not equal to + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [{ float: fcmne, default: cmpne }] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.f}cmpne.{sve_type}" } + + - name: svcmpne_wide[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Compare not equal to + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{predicate[0]}" + types: [[[i8, i16, i32], i64]] + assert_instr: [cmpne] + n_variant_op: op2 + compose: + - LLVMLink: { name: "cmpne.wide.{sve_type[0]}" } + + - name: svcmpuo[{_n}_{type}] + attr: [*sve-unstable] + doc: Compare unordered with + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64] + assert_instr: [fcmuo] + n_variant_op: op2 + compose: + - LLVMLink: { name: "fcmpuo.{sve_type}" } + + - name: svcnt{size_literal} + attr: [*sve-unstable] + doc: Count the number of {size}-bit elements in a vector + arguments: [] + return_type: u64 + types: [i8, i16, i32, i64] + assert_instr: + - default: { byte: rdvl, halfword: cnth, default: cntw, doubleword: cntd } + compose: + - FnCall: ["svcnt{size_literal}_pat", [], ["{{ svpattern::SV_ALL }}"]] + + - name: svcnt{size_literal}_pat + attr: [*sve-unstable] + doc: Count the number of {size}-bit elements in a vector + arguments: [] + static_defs: ["const PATTERN: svpattern"] + return_type: u64 + assert_instr: + - [rdvl, "PATTERN = {{ svpattern::SV_ALL }}"] + - ["cnt{size_literal}", "PATTERN = {{ svpattern::SV_MUL4 }}"] + types: [i8] + compose: + - LLVMLink: + name: cnt{size_literal} + arguments: ["pattern: svpattern"] + - FnCall: ["{llvm_link}", [$PATTERN]] + + - name: svcnt{size_literal}_pat + attr: [*sve-unstable] + doc: Count the number of {size}-bit elements in a vector + arguments: [] + static_defs: ["const PATTERN: svpattern"] + return_type: u64 + assert_instr: [["cnt{size_literal}", "PATTERN = {{ svpattern::SV_ALL }}"]] + types: [i16, i32, i64] + compose: + - LLVMLink: + name: cnt{size_literal} + arguments: ["pattern: svpattern"] + - FnCall: ["{llvm_link}", [$PATTERN]] + + - name: svlen[_{type}] + attr: [*sve-unstable] + doc: Count the number of elements in a full vector + arguments: ["_op: {sve_type}"] + return_type: "u64" + types: [i8, u8, i16, u16, i32, u32, f32, i64, u64, f64] + assert_instr: [{ default: { default: "cnt{size_literal}", byte: rdvl } }] + compose: + - FnCall: ["svcnt{size_literal}", []] + + - name: svdup[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a scalar value + arguments: ["op: {type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [mov] + compose: + - LLVMLink: { name: "dup.x.{sve_type}" } + + - name: svdup[_n]_{type}{_mxz} + attr: [*sve-unstable] + doc: Broadcast a scalar value + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { drop: inactive } + assert_instr: [mov] + compose: + - LLVMLink: { name: "dup.{sve_type}" } + + - name: svdup[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a scalar value + arguments: ["op: bool"] + return_type: "{predicate}" + types: [b8, b16, b32, b64] + assert_instr: [sbfx, whilelo] + compose: + - LLVMLink: { name: "dup.x.{sve_type}" } + + - name: svdup_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Broadcast a scalar value + arguments: ["data: {sve_type[0]}", "index: {type[1]}"] + return_type: "{sve_type[0]}" + types: + - [f32, u32] + - [f64, u64] + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + - [u8, u8] + - [u16, u16] + - [u32, u32] + - [u64, u64] + assert_instr: [tbl] + compose: + - FnCall: + - svtbl_{type[0]} + - - $data + - FnCall: ["svdup_n_{type[1]}", [$index]] + + - name: svdupq_lane[_{type}] + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + arguments: ["data: {sve_type}", "index: u64"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [tbl] + compose: + - LLVMLink: { name: "dupq.lane.{sve_type}" } + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + arguments: + - "x0: {type}" + - "x1: {type}" + - "x2: {type}" + - "x3: {type}" + - "x4: {type}" + - "x5: {type}" + - "x6: {type}" + - "x7: {type}" + - "x8: {type}" + - "x9: {type}" + - "x10: {type}" + - "x11: {type}" + - "x12: {type}" + - "x13: {type}" + - "x14: {type}" + - "x15: {type}" + return_type: "{sve_type}" + types: [i8, u8] + assert_instr: [] + compose: + - LLVMLink: + name: llvm.vector.insert.{sve_type}.{neon_type} + arguments: ["op0: {sve_type}", "op1: {neon_type}", "idx: i64"] + - Let: + - op + - FnCall: + - "{llvm_link}" + - - FnCall: ["svundef_{type}", [], [], true] + - FnCall: + - "crate::mem::transmute" + - - - $x0 + - $x1 + - $x2 + - $x3 + - $x4 + - $x5 + - $x6 + - $x7 + - $x8 + - $x9 + - $x10 + - $x11 + - $x12 + - $x13 + - $x14 + - $x15 + - 0 + - FnCall: ["svdupq_lane_{type}", [$op, 0]] + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + types: [b8] + arguments: + - "x0: bool" + - "x1: bool" + - "x2: bool" + - "x3: bool" + - "x4: bool" + - "x5: bool" + - "x6: bool" + - "x7: bool" + - "x8: bool" + - "x9: bool" + - "x10: bool" + - "x11: bool" + - "x12: bool" + - "x13: bool" + - "x14: bool" + - "x15: bool" + return_type: "svbool_t" + assert_instr: [] + compose: + - Let: + - op1 + - FnCall: + - svdupq_n_s8 + - - CastAs: [$x0, i8] + - CastAs: [$x1, i8] + - CastAs: [$x2, i8] + - CastAs: [$x3, i8] + - CastAs: [$x4, i8] + - CastAs: [$x5, i8] + - CastAs: [$x6, i8] + - CastAs: [$x7, i8] + - CastAs: [$x8, i8] + - CastAs: [$x9, i8] + - CastAs: [$x10, i8] + - CastAs: [$x11, i8] + - CastAs: [$x12, i8] + - CastAs: [$x13, i8] + - CastAs: [$x14, i8] + - CastAs: [$x15, i8] + - FnCall: + - svcmpne_wide_s8 + - - FnCall: [svptrue_b8, []] + - $op1 + - FnCall: [svdup_n_s64, [0]] + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + arguments: + - "x0: {type}" + - "x1: {type}" + - "x2: {type}" + - "x3: {type}" + - "x4: {type}" + - "x5: {type}" + - "x6: {type}" + - "x7: {type}" + return_type: "{sve_type}" + types: [i16, u16] + assert_instr: [] + compose: + - LLVMLink: + name: llvm.vector.insert.{sve_type}.{neon_type} + arguments: ["op0: {sve_type}", "op1: {neon_type}", "idx: i64"] + - Let: + - op + - FnCall: + - "{llvm_link}" + - - FnCall: ["svundef_{type}", [], [], true] + - FnCall: + - "crate::mem::transmute" + - - [$x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7] + - 0 + - FnCall: ["svdupq_lane_{type}", [$op, 0]] + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + types: [b16] + arguments: + - "x0: bool" + - "x1: bool" + - "x2: bool" + - "x3: bool" + - "x4: bool" + - "x5: bool" + - "x6: bool" + - "x7: bool" + return_type: svbool_t + assert_instr: [] + compose: + - Let: + - op1 + - FnCall: + - svdupq_n_s16 + - - CastAs: [$x0, i16] + - CastAs: [$x1, i16] + - CastAs: [$x2, i16] + - CastAs: [$x3, i16] + - CastAs: [$x4, i16] + - CastAs: [$x5, i16] + - CastAs: [$x6, i16] + - CastAs: [$x7, i16] + - FnCall: + - svcmpne_wide_s16 + - - FnCall: [svptrue_b16, []] + - $op1 + - FnCall: [svdup_n_s64, [0]] + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + arguments: ["x0: {type}", "x1: {type}", "x2: {type}", "x3: {type}"] + return_type: "{sve_type}" + types: [f32, i32, u32] + assert_instr: [] + compose: + - LLVMLink: + name: llvm.vector.insert.{sve_type}.{neon_type} + arguments: ["op0: {sve_type}", "op1: {neon_type}", "idx: i64"] + - Let: + - op + - FnCall: + - "{llvm_link}" + - - FnCall: ["svundef_{type}", [], [], true] + - FnCall: ["crate::mem::transmute", [[$x0, $x1, $x2, $x3]]] + - 0 + - FnCall: ["svdupq_lane_{type}", [$op, 0]] + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + types: [b32] + arguments: ["x0: bool", "x1: bool", "x2: bool", "x3: bool"] + return_type: "svbool_t" + assert_instr: [] + compose: + - Let: + - op1 + - FnCall: + - svdupq_n_s32 + - - CastAs: [$x0, i32] + - CastAs: [$x1, i32] + - CastAs: [$x2, i32] + - CastAs: [$x3, i32] + - FnCall: + - svcmpne_wide_s32 + - - FnCall: [svptrue_b32, []] + - $op1 + - FnCall: [svdup_n_s64, [0]] + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + arguments: ["x0: {type}", "x1: {type}"] + return_type: "{sve_type}" + types: [f64, i64, u64] + assert_instr: [] + compose: + - LLVMLink: + name: llvm.vector.insert.{sve_type}.{neon_type} + arguments: ["op0: {sve_type}", "op1: {neon_type}", "idx: i64"] + - Let: + - op + - FnCall: + - "{llvm_link}" + - - FnCall: ["svundef_{type}", [], [], true] + - FnCall: ["crate::mem::transmute", [[$x0, $x1]]] + - 0 + - FnCall: ["svdupq_lane_{type}", [$op, 0]] + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + types: [b64] + arguments: ["x0: bool", "x1: bool"] + return_type: "svbool_t" + assert_instr: [] + compose: + - Let: + - op1 + - FnCall: [svdupq_n_s64, [CastAs: [$x0, i64], CastAs: [$x1, i64]]] + - FnCall: + - svcmpne_s64 + - - FnCall: [svptrue_b64, []] + - $op1 + - FnCall: [svdup_n_s64, [0]] + + - name: svcreate2[_{type}] + attr: [*sve-unstable] + doc: Create a tuple of two vectors + arguments: ["x0: {sve_type}", "x1: {sve_type}"] + return_type: "{sve_type_x2}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_create2", [$x0, $x1], [], true] + + - name: svcreate3[_{type}] + attr: [*sve-unstable] + doc: Create a tuple of three vectors + arguments: ["x0: {sve_type}", "x1: {sve_type}", "x2: {sve_type}"] + return_type: "{sve_type_x3}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_create3", [$x0, $x1, $x2], [], true] + + - name: svcreate4[_{type}] + attr: [*sve-unstable] + doc: Create a tuple of four vectors + arguments: + ["x0: {sve_type}", "x1: {sve_type}", "x2: {sve_type}", "x3: {sve_type}"] + return_type: "{sve_type_x4}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_create4", [$x0, $x1, $x2, $x3], [], true] + + - name: svundef_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized vector + arguments: [] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["svdup_n_{type}", ["0"]] + + - name: svundef_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized vector + arguments: [] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [] + compose: + - FnCall: ["svdup_n_{type}", ["0{type}"]] + + - name: svundef2_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized tuple of two vectors + arguments: [] + return_type: "{sve_type_x2}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: + - "svcreate2_{type}" + - - FnCall: ["svdup_n_{type}", ["0"]] + - FnCall: ["svdup_n_{type}", ["0"]] + + - name: svundef2_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized tuple of two vectors + arguments: [] + return_type: "{sve_type_x2}" + types: [f32, f64] + assert_instr: [] + compose: + - FnCall: + - "svcreate2_{type}" + - - FnCall: ["svdup_n_{type}", ["0{type}"]] + - FnCall: ["svdup_n_{type}", ["0{type}"]] + + - name: svundef3_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized tuple of three vectors + arguments: [] + return_type: "{sve_type_x3}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: + - "svcreate3_{type}" + - - FnCall: ["svdup_n_{type}", ["0"]] + - FnCall: ["svdup_n_{type}", ["0"]] + - FnCall: ["svdup_n_{type}", ["0"]] + + - name: svundef3_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized tuple of three vectors + arguments: [] + return_type: "{sve_type_x3}" + types: [f32, f64] + assert_instr: [] + compose: + - FnCall: + - "svcreate3_{type}" + - - FnCall: ["svdup_n_{type}", ["0{type}"]] + - FnCall: ["svdup_n_{type}", ["0{type}"]] + - FnCall: ["svdup_n_{type}", ["0{type}"]] + + - name: svundef4_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized tuple of four vectors + arguments: [] + return_type: "{sve_type_x4}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: + - "svcreate4_{type}" + - - FnCall: ["svdup_n_{type}", ["0"]] + - FnCall: ["svdup_n_{type}", ["0"]] + - FnCall: ["svdup_n_{type}", ["0"]] + - FnCall: ["svdup_n_{type}", ["0"]] + + - name: svundef4_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized tuple of four vectors + arguments: [] + return_type: "{sve_type_x4}" + types: [f32, f64] + assert_instr: [] + compose: + - FnCall: + - "svcreate4_{type}" + - - FnCall: ["svdup_n_{type}", ["0{type}"]] + - FnCall: ["svdup_n_{type}", ["0{type}"]] + - FnCall: ["svdup_n_{type}", ["0{type}"]] + - FnCall: ["svdup_n_{type}", ["0{type}"]] + + - name: svindex_{type} + attr: [*sve-unstable] + doc: Create linear series + arguments: ["base: {type}", "step: {type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [index] + compose: + - LLVMLink: { name: "index.{sve_type}" } + + - name: svget2[_{type}] + attr: [*sve-unstable] + doc: Extract one vector from a tuple of two vectors + arguments: ["tuple: {sve_type_x2}"] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, range: [0, 1] }] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_get", [$tuple], ["_", "_", "{{IMM_INDEX}}"], true] + + - name: svget3[_{type}] + attr: [*sve-unstable] + doc: Extract one vector from a tuple of three vectors + arguments: ["tuple: {sve_type_x3}"] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, range: [0, 2] }] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_get", [$tuple], ["_", "_", "{{IMM_INDEX}}"], true] + + - name: svget4[_{type}] + attr: [*sve-unstable] + doc: Extract one vector from a tuple of four vectors + arguments: ["tuple: {sve_type_x4}"] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, range: [0, 3] }] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_get", [$tuple], ["_", "_", "{{IMM_INDEX}}"], true] + + - name: svset2[_{type}] + attr: [*sve-unstable] + doc: Change one vector in a tuple of two vectors + arguments: ["tuple: {sve_type_x2}", "x: {sve_type}"] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, range: [0, 1] }] + return_type: "{sve_type_x2}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_set", [$tuple, $x], ["_", "_", "{{IMM_INDEX}}"], true] + + - name: svset3[_{type}] + attr: [*sve-unstable] + doc: Change one vector in a tuple of three vectors + arguments: ["tuple: {sve_type_x3}", "x: {sve_type}"] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, range: [0, 2] }] + return_type: "{sve_type_x3}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_set", [$tuple, $x], ["_", "_", "{{IMM_INDEX}}"], true] + + - name: svset4[_{type}] + attr: [*sve-unstable] + doc: Change one vector in a tuple of four vectors + arguments: ["tuple: {sve_type_x4}", "x: {sve_type}"] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, range: [0, 3] }] + return_type: "{sve_type_x4}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_set", [$tuple, $x], ["_", "_", "{{IMM_INDEX}}"], true] + + - name: svzip1[_{type}] + attr: [*sve-unstable] + doc: Interleave elements from low halves of two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b8, f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [zip1] + compose: + - LLVMLink: { name: "zip1.{sve_type}" } + + - name: svzip1_{type} + attr: [*sve-unstable] + doc: Interleave elements from low halves of two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b16, b32, b64] + assert_instr: [zip1] + compose: + - LLVMLink: + name: "llvm.aarch64.sve.zip1.b{size}" + arguments: ["op1: svbool_t", "op2: svbool_t"] + return_type: "svbool_t" + + - name: svzip1q[_{type}] + attr: [*sve-unstable] + doc: Interleave quadwords from low halves of two inputs + target_features: [f64mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [zip1] + compose: + - LLVMLink: { name: "zip1q.{sve_type}" } + + - name: svzip2[_{type}] + attr: [*sve-unstable] + doc: Interleave elements from high halves of two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b8, f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [zip2] + compose: + - LLVMLink: { name: "zip2.{sve_type}" } + + - name: svzip2_{type} + attr: [*sve-unstable] + doc: Interleave elements from high halves of two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b16, b32, b64] + assert_instr: [zip2] + compose: + - LLVMLink: + name: "llvm.aarch64.sve.zip2.b{size}" + arguments: ["op1: svbool_t", "op2: svbool_t"] + return_type: "svbool_t" + + - name: svzip2q[_{type}] + attr: [*sve-unstable] + doc: Interleave quadwords from high halves of two inputs + target_features: [f64mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [zip2] + compose: + - LLVMLink: { name: "zip2q.{sve_type}" } + + - name: svuzp1[_{type}] + attr: [*sve-unstable] + doc: Concatenate even elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b8, f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [uzp1] + compose: + - LLVMLink: { name: "uzp1.{sve_type}" } + + - name: svuzp1_{type} + attr: [*sve-unstable] + doc: Concatenate even elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b16, b32, b64] + assert_instr: [uzp1] + compose: + - LLVMLink: + name: "llvm.aarch64.sve.uzp1.b{size}" + arguments: ["op1: svbool_t", "op2: svbool_t"] + return_type: "svbool_t" + + - name: svuzp1q[_{type}] + attr: [*sve-unstable] + doc: Concatenate even quadwords from two inputs + target_features: [f64mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [uzp1] + compose: + - LLVMLink: { name: "uzp1q.{sve_type}" } + + - name: svuzp2[_{type}] + attr: [*sve-unstable] + doc: Concatenate odd elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b8, f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [uzp2] + compose: + - LLVMLink: { name: "uzp2.{sve_type}" } + + - name: svuzp2_{type} + attr: [*sve-unstable] + doc: Concatenate odd elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b16, b32, b64] + assert_instr: [uzp2] + compose: + - LLVMLink: + name: "llvm.aarch64.sve.uzp2.b{size}" + arguments: ["op1: svbool_t", "op2: svbool_t"] + return_type: "svbool_t" + + - name: svuzp2q[_{type}] + attr: [*sve-unstable] + doc: Concatenate odd quadwords from two inputs + target_features: [f64mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [uzp2] + compose: + - LLVMLink: { name: "uzp2q.{sve_type}" } + + - name: svtrn1[_{type}] + attr: [*sve-unstable] + doc: Interleave even elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b8, f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [trn1] + compose: + - LLVMLink: { name: "trn1.{sve_type}" } + + - name: svtrn1_{type} + attr: [*sve-unstable] + doc: Interleave even elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b16, b32, b64] + assert_instr: [trn1] + compose: + - LLVMLink: + name: "llvm.aarch64.sve.trn1.b{size}" + arguments: ["op1: svbool_t", "op2: svbool_t"] + return_type: "svbool_t" + + - name: svtrn1q[_{type}] + attr: [*sve-unstable] + doc: Interleave even quadwords from two inputs + target_features: [f64mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [trn1] + compose: + - LLVMLink: { name: "trn1q.{sve_type}" } + + - name: svtrn2[_{type}] + attr: [*sve-unstable] + doc: Interleave odd elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b8, f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [trn2] + compose: + - LLVMLink: { name: "trn2.{sve_type}" } + + - name: svtrn2_{type} + attr: [*sve-unstable] + doc: Interleave odd elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b16, b32, b64] + assert_instr: [trn2] + compose: + - LLVMLink: + name: "llvm.aarch64.sve.trn2.b{size}" + arguments: ["op1: svbool_t", "op2: svbool_t"] + return_type: "svbool_t" + + - name: svtrn2q[_{type}] + attr: [*sve-unstable] + doc: Interleave odd quadwords from two inputs + target_features: [f64mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [trn2] + compose: + - LLVMLink: { name: "trn2q.{sve_type}" } + + - name: svrev[_{type}] + attr: [*sve-unstable] + doc: Reverse all elements + arguments: ["op: {sve_type}"] + return_type: "{sve_type}" + types: [b8, f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [rev] + compose: + - LLVMLink: { name: "llvm.vector.reverse.{sve_type}" } + + - name: svrev_{type} + attr: [*sve-unstable] + doc: Reverse all elements + arguments: ["op: {sve_type}"] + return_type: "{sve_type}" + types: [b16, b32, b64] + assert_instr: [rev] + compose: + - LLVMLink: + name: "llvm.aarch64.sve.rev.b{size}" + arguments: ["op: svbool_t"] + return_type: "svbool_t" + + - name: svrevb[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Reverse bytes within elements + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [i16, i32, i64, u16, u32, u64] + zeroing_method: { drop: "inactive" } + assert_instr: [revb] + compose: + - LLVMLink: { name: "revb.{sve_type}" } + + - name: svrevh[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Reverse halfwords within elements + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [i32, i64, u32, u64] + zeroing_method: { drop: "inactive" } + assert_instr: [revh] + compose: + - LLVMLink: { name: "revh.{sve_type}" } + + - name: svrevw[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Reverse words within elements + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [i64, u64] + zeroing_method: { drop: "inactive" } + assert_instr: [revw] + compose: + - LLVMLink: { name: "revw.{sve_type}" } + + - name: svrbit[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Reverse bits + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { drop: "inactive" } + assert_instr: [rbit] + compose: + - LLVMLink: { name: "rbit.{sve_type}" } + + - name: svext[_{type}] + attr: [*sve-unstable] + doc: Extract vector from pair of vectors + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM3: i32"] + constraints: [{ variable: IMM3, sve_max_elems_type: "{type}" }] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [[ext, "IMM3 = 1"]] + compose: + - LLVMLink: + name: ext.{sve_type} + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]] + + - name: svsplice[_{type}] + attr: [*sve-unstable] + doc: Splice two vectors under predicate control + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [splice] + compose: + - LLVMLink: { name: "splice.{sve_type}" } + + - name: svinsr[_n_{type}] + attr: [*sve-unstable] + doc: Insert scalar in shifted vector + arguments: ["op1: {sve_type}", "op2: {type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [insr] + compose: + - LLVMLink: { name: "insr.{sve_type}" } + + - name: svld1[_{type}] + attr: [*sve-unstable] + doc: Unextended load + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld1{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ld1.{sve_type}" } + + - name: svld1_vnum[_{type}] + attr: [*sve-unstable] + doc: Unextended load + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld1{size_literal}"] + test: { load: 0 } + compose: + - FnCall: + - "svld1_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svld1_gather_[{type[0]}]index[_{type[1]}] + attr: [*sve-unstable] + doc: Unextended load + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate[0]}", "base: *{type[1]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["ld1{size_literal[0]}"] + test: { load: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ld1.gather.{type_kind[0].su}xtw.index.{sve_type[1]}" + doubleword: + LLVMLink: + name: "ld1.gather.index.{sve_type[1]}" + + - name: svld1_gather_[{type[0]}]offset[_{type[1]}] + attr: [*sve-unstable] + doc: Unextended load + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate[0]}", "base: *{type[1]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["ld1{size_literal[0]}"] + test: { load: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ld1.gather.{type_kind[0].su}xtw.{sve_type[1]}" + doubleword: + LLVMLink: + name: "ld1.gather.{sve_type[1]}" + + - name: svld1_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Unextended load + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ld1{size_literal[0]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ld1.gather.scalar.offset.{sve_type[1]}.{sve_type[0]}" + + - name: svld1_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Unextended load + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ld1{size_literal[0]}"] + test: { load: 1 } + compose: + - FnCall: + - "svld1_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svld1_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Unextended load + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ld1{size_literal[0]}"] + test: { load: 1 } + compose: + - FnCall: + - "svld1_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[0]}"]] + + - name: svld1s{size_literal[2]}_gather_[{type[0]}]index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [i32, u32], i16] + - [[i64, u64], [i64, u64], [i16, i32]] + assert_instr: ["ld1s{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ld1.gather.{type_kind[0].su}xtw.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ld1.gather.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $indices]] + + - name: svld1u{size_literal[2]}_gather_[{type[0]}]index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [u32, i32], u16] + - [[i64, u64], [u64, i64], [u16, u32]] + assert_instr: ["ld1{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ld1.gather.{type_kind[0].su}xtw.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ld1.gather.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $indices]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svld1s{size_literal[2]}_gather_[{type[0]}]offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [i32, u32], [i8, i16]] + - [[i64, u64], [i64, u64], [i8, i16, i32]] + assert_instr: ["ld1s{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ld1.gather.{type_kind[0].su}xtw.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ld1.gather.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]] + + - name: svld1u{size_literal[2]}_gather_[{type[0]}]offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [u32, i32], [u8, u16]] + - [[i64, u64], [u64, i64], [u8, u16, u32]] + assert_instr: ["ld1{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ld1.gather.{type_kind[0].su}xtw.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ld1.gather.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svld1s{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["ld1s{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ld1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]] + + - name: svld1u{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [u32, i32], [u8, u16]] + - [u64, [u64, i64], [u8, u16, u32]] + assert_instr: ["ld1{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ld1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svld1s{size_literal[2]}_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["ld1s{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svld1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svld1u{size_literal[2]}_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [u8, u16]] + - [u64, [i64, u64], [u8, u16, u32]] + assert_instr: ["ld1{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svld1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svld1s{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], i16] + - [u64, [i64, u64], [i16, i32]] + assert_instr: ["ld1s{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svld1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + + - name: svld1u{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], u16] + - [u64, [i64, u64], [u16, u32]] + assert_instr: ["ld1{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svld1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + + - name: svldnt1[_{type}] + attr: [*sve-unstable] + doc: Unextended load, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ldnt1{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ldnt1.{sve_type}" } + + - name: svldnt1_vnum[_{type}] + attr: [*sve-unstable] + doc: Unextended load, non-temporal + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + - non_temporal + arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ldnt1{size_literal}"] + test: { load: 0 } + compose: + - FnCall: + - "svldnt1_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svld1s{size_literal[1]}_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and sign-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], i8] + - [[i32, i64, u32, u64], i16] + - [[i64, u64], i32] + assert_instr: ["ld1s{size_literal[1]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ld1.{sve_type[0] as {type[1]}}" + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0] as {type[1]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base]] + + - name: svld1u{size_literal[1]}_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and zero-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], u8] + - [[i32, i64, u32, u64], u16] + - [[i64, u64], u32] + assert_instr: ["ld1{size_literal[1]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ld1.{sve_type[0] as {type[1]}}" + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0] as {type[1]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base]] + - [Type: "{sve_type[0] as {type[1]}}", _] + + - name: svld1s{size_literal[1]}_vnum_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and sign-extend + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], i8] + - [[i32, i64, u32, u64], i16] + - [[i64, u64], i32] + assert_instr: ["ld1s{size_literal[1]}"] + test: { load: 1 } + compose: + - FnCall: + - "svld1s{size_literal[1]}_{type[0]}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: + [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svld1u{size_literal[1]}_vnum_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and zero-extend + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], u8] + - [[i32, i64, u32, u64], u16] + - [[i64, u64], u32] + assert_instr: ["ld1{size_literal[1]}"] + test: { load: 1 } + compose: + - FnCall: + - "svld1u{size_literal[1]}_{type[0]}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: + [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svld2[_{type}] + attr: [*sve-unstable] + doc: Load two-element tuples into two vectors + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type_x2}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld2{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ld2.sret.{sve_type}" } + + - name: svld2_vnum[_{type}] + attr: [*sve-unstable] + doc: Load two-element tuples into two vectors + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"] + return_type: "{sve_type_x2}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld2{size_literal}"] + test: { load: 0 } + compose: + - FnCall: + - "svld2_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svld3[_{type}] + attr: [*sve-unstable] + doc: Load three-element tuples into three vectors + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type_x3}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld3{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ld3.sret.{sve_type}" } + + - name: svld3_vnum[_{type}] + attr: [*sve-unstable] + doc: Load three-element tuples into three vectors + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"] + return_type: "{sve_type_x3}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld3{size_literal}"] + test: { load: 0 } + compose: + - FnCall: + - "svld3_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svld4[_{type}] + attr: [*sve-unstable] + doc: Load four-element tuples into four vectors + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type_x4}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld4{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ld4.sret.{sve_type}" } + + - name: svld4_vnum[_{type}] + attr: [*sve-unstable] + doc: Load four-element tuples into four vectors + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"] + return_type: "{sve_type_x4}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld4{size_literal}"] + test: { load: 0 } + compose: + - FnCall: + - "svld4_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svld1rq[_{type}] + attr: [*sve-unstable] + doc: Load and replicate 128 bits of data + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld1rq{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ld1rq.{sve_type}" } + + - name: svld1ro[_{type}] + attr: [*sve-unstable] + doc: Load and replicate 256 bits of data + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + target_features: [f64mm] + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld1ro{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ld1ro.{sve_type}" } + + - name: svldnf1[_{type}] + attr: [*sve-unstable] + doc: Unextended load, non-faulting + safety: + unsafe: + - pointer_offset: predicated_non_faulting + - dereference: predicated_non_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ldnf1{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ldnf1.{sve_type}" } + + - name: svldnf1_vnum[_{type}] + attr: [*sve-unstable] + doc: Unextended load, non-faulting + safety: + unsafe: + - pointer_offset_vnum: predicated_non_faulting + - dereference: predicated_non_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ldnf1{size_literal}"] + test: { load: 0 } + compose: + - FnCall: + - "svldnf1_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svldnf1s{size_literal[1]}_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and sign-extend, non-faulting + safety: + unsafe: + - pointer_offset: predicated_non_faulting + - dereference: predicated_non_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], i8] + - [[i32, i64, u32, u64], i16] + - [[i64, u64], i32] + assert_instr: ["ldnf1s{size_literal[1]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ldnf1.{sve_type[0] as {type[1]}}" + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0] as {type[1]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base]] + + - name: svldnf1u{size_literal[1]}_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and zero-extend, non-faulting + safety: + unsafe: + - pointer_offset: predicated_non_faulting + - dereference: predicated_non_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], u8] + - [[i32, i64, u32, u64], u16] + - [[i64, u64], u32] + assert_instr: ["ldnf1{size_literal[1]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ldnf1.{sve_type[0] as {type[1]}}" + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0] as {type[1]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base]] + - [Type: "{sve_type[0] as {type[1]}}", _] + + - name: svldnf1s{size_literal[1]}_vnum_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and sign-extend, non-faulting + safety: + unsafe: + - pointer_offset_vnum: predicated_non_faulting + - dereference: predicated_non_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], i8] + - [[i32, i64, u32, u64], i16] + - [[i64, u64], i32] + assert_instr: ["ldnf1s{size_literal[1]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldnf1s{size_literal[1]}_{type[0]}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: + [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svldnf1u{size_literal[1]}_vnum_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and zero-extend, non-faulting + safety: + unsafe: + - pointer_offset_vnum: predicated_non_faulting + - dereference: predicated_non_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], u8] + - [[i32, i64, u32, u64], u16] + - [[i64, u64], u32] + assert_instr: ["ldnf1{size_literal[1]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldnf1u{size_literal[1]}_{type[0]}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: + [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svldff1[_{type}] + attr: [*sve-unstable] + doc: Unextended load, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ldff1{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ldff1.{sve_type}" } + + - name: svldff1_vnum[_{type}] + attr: [*sve-unstable] + doc: Unextended load, first-faulting + safety: + unsafe: + - pointer_offset_vnum: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ldff1{size_literal}"] + test: { load: 0 } + compose: + - FnCall: + - "svldff1_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svldff1s{size_literal[1]}_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and sign-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], i8] + - [[i32, i64, u32, u64], i16] + - [[i64, u64], i32] + assert_instr: ["ldff1s{size_literal[1]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ldff1.{sve_type[0] as {type[1]}}" + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0] as {type[1]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base]] + + - name: svldff1u{size_literal[1]}_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and zero-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], u8] + - [[i32, i64, u32, u64], u16] + - [[i64, u64], u32] + assert_instr: ["ldff1{size_literal[1]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ldff1.{sve_type[0] as {type[1]}}" + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0] as {type[1]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base]] + - [Type: "{sve_type[0] as {type[1]}}", _] + + - name: svldff1s{size_literal[1]}_vnum_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and sign-extend, first-faulting + safety: + unsafe: + - pointer_offset_vnum: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], i8] + - [[i32, i64, u32, u64], i16] + - [[i64, u64], i32] + assert_instr: ["ldff1s{size_literal[1]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldff1s{size_literal[1]}_{type[0]}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: + [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svldff1u{size_literal[1]}_vnum_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and zero-extend, first-faulting + safety: + unsafe: + - pointer_offset_vnum: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], u8] + - [[i32, i64, u32, u64], u16] + - [[i64, u64], u32] + assert_instr: ["ldff1{size_literal[1]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldff1u{size_literal[1]}_{type[0]}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: + [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svldff1_gather_[{type[0]}]index[_{type[1]}] + attr: [*sve-unstable] + doc: Unextended load, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: + ["pg: {predicate[0]}", "base: *{type[1]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["ldff1{size_literal[0]}"] + test: { load: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldff1.gather.{type_kind[0].su}xtw.index.{sve_type[1]}" + doubleword: + LLVMLink: + name: "ldff1.gather.index.{sve_type[1]}" + + - name: svldff1_gather_[{type[0]}]offset[_{type[1]}] + attr: [*sve-unstable] + doc: Unextended load, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: + ["pg: {predicate[0]}", "base: *{type[1]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["ldff1{size_literal[0]}"] + test: { load: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldff1.gather.{type_kind[0].su}xtw.{sve_type[1]}" + doubleword: + LLVMLink: + name: "ldff1.gather.{sve_type[1]}" + + - name: svldff1_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Unextended load, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ldff1{size_literal[0]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ldff1.gather.scalar.offset.{sve_type[1]}.{sve_type[0]}" + + - name: svldff1_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Unextended load, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ldff1{size_literal[0]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldff1_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svldff1_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Unextended load, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ldff1{size_literal[0]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldff1_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[0]}"]] + + - name: svldff1s{size_literal[2]}_gather_[{type[0]}]index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [i32, u32], i16] + - [[i64, u64], [i64, u64], [i16, i32]] + assert_instr: ["ldff1s{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldff1.gather.{type_kind[0].su}xtw.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ldff1.gather.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $indices]] + + - name: svldff1u{size_literal[2]}_gather_[{type[0]}]index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [u32, i32], u16] + - [[i64, u64], [u64, i64], [u16, u32]] + assert_instr: ["ldff1{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldff1.gather.{type_kind[0].su}xtw.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ldff1.gather.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $indices]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svldff1s{size_literal[2]}_gather_[{type[0]}]offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [i32, u32], [i8, i16]] + - [[i64, u64], [i64, u64], [i8, i16, i32]] + assert_instr: ["ldff1s{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldff1.gather.{type_kind[0].su}xtw.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ldff1.gather.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]] + + - name: svldff1u{size_literal[2]}_gather_[{type[0]}]offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [u32, i32], [u8, u16]] + - [[i64, u64], [u64, i64], [u8, u16, u32]] + assert_instr: ["ldff1{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldff1.gather.{type_kind[0].su}xtw.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ldff1.gather.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svldff1s{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["ldff1s{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ldff1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]] + + - name: svldff1u{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [u32, i32], [u8, u16]] + - [u64, [u64, i64], [u8, u16, u32]] + assert_instr: ["ldff1{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ldff1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svldff1s{size_literal[2]}_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + doc: Load {size[2]}-bit data and sign-extend, first-faulting + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["ldff1s{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldff1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svldff1u{size_literal[2]}_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [u8, u16]] + - [u64, [i64, u64], [u8, u16, u32]] + assert_instr: ["ldff1{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldff1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svldff1s{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], i16] + - [u64, [i64, u64], [i16, i32]] + assert_instr: ["ldff1s{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldff1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + + - name: svldff1u{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], u16] + - [u64, [i64, u64], [u16, u32]] + assert_instr: ["ldff1{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldff1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + + - name: svrdffr_z + attr: [*sve-unstable] + doc: Read FFR, returning predicate of succesfully loaded elements + arguments: ["pg: svbool_t"] + return_type: svbool_t + assert_instr: [rdffr] + compose: + - LLVMLink: { name: "rdffr.z" } + + - name: svrdffr + attr: [*sve-unstable] + doc: Read FFR, returning predicate of succesfully loaded elements + arguments: [] + return_type: svbool_t + assert_instr: [rdffr] + compose: + - FnCall: [svrdffr_z, [FnCall: [svptrue_b8, []]]] + + - name: svsetffr + attr: [*sve-unstable] + doc: Initialize the first-fault register to all-true + arguments: [] + assert_instr: [setffr] + compose: + - LLVMLink: { name: "setffr" } + + - name: svwrffr + attr: [*sve-unstable] + doc: Write to the first-fault register + arguments: ["op: svbool_t"] + assert_instr: [wrffr] + compose: + - LLVMLink: { name: "wrffr" } + + - name: svqinc{size_literal[1]}[_n_{type[0]}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type[1]}" + default: word + byte: byte + halfword: halfword + doubleword: doubleword + doc: Saturating increment by number of {textual_size} elements + arguments: ["op: {type[0]}"] + static_defs: ["const IMM_FACTOR: i32"] + return_type: "{type[0]}" + types: + - [[i32, i64, u32, u64], [i8, i16, i32, i64]] + assert_instr: + - ["{type_kind[0].su}qinc{size_literal[1]}", "IMM_FACTOR = 1"] + compose: + - FnCall: + - "svqinc{size_literal[1]}_pat_n_{type[0]}" + - [$op] + - ["{{svpattern::SV_ALL}}", $IMM_FACTOR] + + - name: svqinc{size_literal[1]}_pat[_n_{type[0]}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type[1]}" + default: word + byte: byte + halfword: halfword + doubleword: doubleword + doc: Saturating increment by number of {textual_size} elements + arguments: ["op: {type[0]}"] + static_defs: ["const PATTERN: svpattern", "const IMM_FACTOR: i32"] + constraints: [{ variable: IMM_FACTOR, range: [1, 16] }] + return_type: "{type[0]}" + types: + - [[i32, i64, u32, u64], [i8, i16, i32, i64]] + assert_instr: + - - "{type_kind[0].su}qinc{size_literal[1]}" + - "PATTERN = {{svpattern::SV_ALL}}, IMM_FACTOR = 1" + compose: + - LLVMLink: + name: "{type_kind[0].su}qinc{size_literal[1]}.n{size[0]}" + arguments: ["op: {type[0]}", "pattern: svpattern", "imm_factor: i32"] + return_type: "{type[0]}" + - FnCall: ["{llvm_link}", [$op, $PATTERN, $IMM_FACTOR]] + + - name: svqinc{size_literal}[_{type}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type}" + default: word + halfword: halfword + doubleword: doubleword + doc: Saturating increment by number of {textual_size} elements + arguments: ["op: {sve_type}"] + static_defs: ["const IMM_FACTOR: i32"] + return_type: "{sve_type}" + types: [i16, u16, i32, u32, i64, u64] + assert_instr: [["{type_kind.su}qinc{size_literal}", "IMM_FACTOR = 1"]] + compose: + - FnCall: + - "svqinc{size_literal}_pat_{type}" + - [$op] + - ["{{svpattern::SV_ALL}}", $IMM_FACTOR] + + - name: svqinc{size_literal}_pat[_{type}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type}" + default: word + halfword: halfword + doubleword: doubleword + doc: Saturating increment by number of {textual_size} elements + arguments: ["op: {sve_type}"] + static_defs: ["const PATTERN: svpattern", "const IMM_FACTOR: i32"] + constraints: [{ variable: IMM_FACTOR, range: [1, 16] }] + return_type: "{sve_type}" + types: [i16, u16, i32, u32, i64, u64] + assert_instr: + - - "{type_kind.su}qinc{size_literal}" + - "PATTERN = {{svpattern::SV_ALL}}, IMM_FACTOR = 1" + compose: + - LLVMLink: + name: "{type_kind.su}qinc{size_literal}.{sve_type}" + arguments: ["op: {sve_type}", "pattern: svpattern", "imm_factor: i32"] + return_type: "{sve_type}" + - FnCall: ["{llvm_link}", [$op, $PATTERN, $IMM_FACTOR]] + + - name: svqdec{size_literal[1]}[_n_{type[0]}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type[1]}" + default: word + byte: byte + halfword: halfword + doubleword: doubleword + doc: Saturating decrement by number of {textual_size} elements + arguments: ["op: {type[0]}"] + static_defs: ["const IMM_FACTOR: i32"] + return_type: "{type[0]}" + types: + - [[i32, i64, u32, u64], [i8, i16, i32, i64]] + assert_instr: + - ["{type_kind[0].su}qdec{size_literal[1]}", "IMM_FACTOR = 1"] + compose: + - FnCall: + - "svqdec{size_literal[1]}_pat_n_{type[0]}" + - [$op] + - ["{{svpattern::SV_ALL}}", $IMM_FACTOR] + + - name: svqdec{size_literal[1]}_pat[_n_{type[0]}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type[1]}" + default: word + byte: byte + halfword: halfword + doubleword: doubleword + doc: Saturating decrement by number of {textual_size} elements + arguments: ["op: {type[0]}"] + static_defs: ["const PATTERN: svpattern", "const IMM_FACTOR: i32"] + constraints: [{ variable: IMM_FACTOR, range: [1, 16] }] + return_type: "{type[0]}" + types: + - [[i32, i64, u32, u64], [i8, i16, i32, i64]] + assert_instr: + - - "{type_kind[0].su}qdec{size_literal[1]}" + - "PATTERN = {{svpattern::SV_ALL}}, IMM_FACTOR = 1" + compose: + - LLVMLink: + name: "{type_kind[0].su}qdec{size_literal[1]}.n{size[0]}" + arguments: ["op: {type[0]}", "pattern: svpattern", "imm_factor: i32"] + return_type: "{type[0]}" + - FnCall: ["{llvm_link}", [$op, $PATTERN, $IMM_FACTOR]] + + - name: svqdec{size_literal}[_{type}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type}" + default: word + halfword: halfword + doubleword: doubleword + doc: Saturating decrement by number of {textual_size} elements + arguments: ["op: {sve_type}"] + static_defs: ["const IMM_FACTOR: i32"] + return_type: "{sve_type}" + types: [i16, u16, i32, u32, i64, u64] + assert_instr: [["{type_kind.su}qdec{size_literal}", "IMM_FACTOR = 1"]] + compose: + - FnCall: + - "svqdec{size_literal}_pat_{type}" + - [$op] + - ["{{svpattern::SV_ALL}}", $IMM_FACTOR] + + - name: svqdec{size_literal}_pat[_{type}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type}" + default: word + halfword: halfword + doubleword: doubleword + doc: Saturating decrement by number of {textual_size} elements + arguments: ["op: {sve_type}"] + static_defs: ["const PATTERN: svpattern", "const IMM_FACTOR: i32"] + constraints: [{ variable: IMM_FACTOR, range: [1, 16] }] + return_type: "{sve_type}" + types: [i16, u16, i32, u32, i64, u64] + assert_instr: + - - "{type_kind.su}qdec{size_literal}" + - "PATTERN = {{svpattern::SV_ALL}}, IMM_FACTOR = 1" + compose: + - LLVMLink: + name: "{type_kind.su}qdec{size_literal}.{sve_type}" + arguments: ["op: {sve_type}", "pattern: svpattern", "imm_factor: i32"] + return_type: "{sve_type}" + - FnCall: ["{llvm_link}", [$op, $PATTERN, $IMM_FACTOR]] + + - name: svst1[_{type}] + attr: [*sve-unstable] + doc: Non-truncating store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *mut {type}", "data: {sve_type}"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st1{size_literal}"] + test: { store: 0 } + compose: + - LLVMLink: + name: "st1.{sve_type}" + arguments: + - "data: {sve_type}" + - "pg: {predicate}" + - "ptr: *mut {type}" + - FnCall: ["{llvm_link}", [$data, $pg, $base]] + + - name: svst1_scatter_[{type[0]}]index[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "indices: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [[i32, u32], [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["st1{size_literal[0]}"] + test: { store: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "st1.scatter.{type_kind[0].su}xtw.index.{sve_type[1]}" + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "indices: {sve_type[0]}" + doubleword: + LLVMLink: + name: "st1.scatter.index.{sve_type[1]}" + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "indices: {sve_type[0]}" + - FnCall: ["{llvm_link}", [$data, $pg, $base, $indices]] + + - name: svst1_scatter_[{type[0]}]offset[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "offsets: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [[i32, u32], [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["st1{size_literal[0]}"] + test: { store: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "st1.scatter.{type_kind[0].su}xtw.{sve_type[1]}" + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "offsets: {sve_type[0]}" + doubleword: + LLVMLink: + name: "st1.scatter.{sve_type[1]}" + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "offsets: {sve_type[0]}" + - FnCall: ["{llvm_link}", [$data, $pg, $base, $offsets]] + + - name: svst1_scatter[_{type[0]}base]_offset[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + - "data: {sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["st1{size_literal[0]}"] + test: { store: 1 } + compose: + - LLVMLink: + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + name: "st1.scatter.scalar.offset.{sve_type[1]}.{sve_type[0]}" + - FnCall: ["{llvm_link}", [$data, $pg, $bases, $offset]] + + - name: svst1_scatter[_{type[0]}base_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: + ["pg: {predicate[0]}", "bases: {sve_type[0]}", "data: {sve_type[1]}"] + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["st1{size_literal[0]}"] + test: { store: 1 } + compose: + - FnCall: + - "svst1_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + - $data + + - name: svst1_scatter[_{type[0]}base]_index[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "index: i64" + - "data: {sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["st1{size_literal[0]}"] + test: { store: 1 } + compose: + - FnCall: + - "svst1_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[0]}"]] + - $data + + - name: svst1{size_literal[2]}_scatter_[{type[0]}]index[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "indices: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [[i32, u32], i32, i16] + - [[i32, u32], u32, u16] + - [[i64, u64], i64, [i16, i32]] + - [[i64, u64], u64, [u16, u32]] + assert_instr: ["st1{size_literal[2]}"] + test: { store: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "st1.scatter.{type_kind[0].su}xtw.index.{sve_type[1] as {type[2]}}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "indices: {sve_type[0]}" + doubleword: + LLVMLink: + name: "st1.scatter.index.{sve_type[1] as {type[2]}}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "indices: {sve_type[0]}" + - FnCall: + - "{llvm_link}" + - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $base, $indices] + + - name: svst1{size_literal[2]}_scatter_[{type[0]}]offset[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "offsets: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [[i32, u32], i32, [i8, i16]] + - [[i32, u32], u32, [u8, u16]] + - [[i64, u64], i64, [i8, i16, i32]] + - [[i64, u64], u64, [u8, u16, u32]] + assert_instr: ["st1{size_literal[2]}"] + test: { store: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "st1.scatter.{type_kind[0].su}xtw.{sve_type[1] as {type[2]}}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "offsets: {sve_type[0]}" + doubleword: + LLVMLink: + name: "st1.scatter.{sve_type[1] as {type[2]}}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "offsets: {sve_type[0]}" + - FnCall: + - "{llvm_link}" + - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $base, $offsets] + + - name: svst1{size_literal[2]}_scatter[_{type[0]}base]_offset[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + - "data: {sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["st1{size_literal[2]}"] + test: { store: 2 } + compose: + - LLVMLink: + name: "st1.scatter.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + - FnCall: + - "{llvm_link}" + - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $bases, $offset] + + - name: svst1{size_literal[2]}_scatter[_{type[0]}base_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: + ["pg: {predicate[0]}", "bases: {sve_type[0]}", "data: {sve_type[1]}"] + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["st1{size_literal[2]}"] + test: { store: 2 } + compose: + - FnCall: + - "svst1{size_literal[2]}_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + - $data + + - name: svst1{size_literal[2]}_scatter[_{type[0]}base]_index[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "index: i64" + - "data: {sve_type[1]}" + types: + - [u32, [i32, u32], i16] + - [u64, [i64, u64], [i16, i32]] + assert_instr: ["st1{size_literal[2]}"] + test: { store: 2 } + compose: + - FnCall: + - "svst1{size_literal[2]}_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + - $data + + - name: svstnt1[_{type}] + attr: [*sve-unstable] + doc: Non-truncating store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: ["pg: {predicate}", "base: *mut {type}", "data: {sve_type}"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["stnt1{size_literal}"] + test: { store: 0 } + compose: + - LLVMLink: + name: "stnt1.{sve_type}" + arguments: + - "data: {sve_type}" + - "pg: {predicate}" + - "ptr: *mut {type}" + - FnCall: ["{llvm_link}", [$data, $pg, $base]] + + - name: svstnt1_vnum[_{type}] + attr: [*sve-unstable] + doc: Non-truncating store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + ["pg: {predicate}", "base: *mut {type}", "vnum: i64", "data: {sve_type}"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["stnt1{size_literal}"] + test: { store: 0 } + compose: + - FnCall: + - "svstnt1_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + - $data + + - name: svst1{size_literal[1]}[_{type[0]}] + attr: [*sve-unstable] + doc: Truncate to {size[1]} bits and store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate[0]}", "base: *mut {type[1]}", "data: {sve_type[0]}"] + types: + - [[i16, i32, i64], i8] + - [[u16, u32, u64], u8] + - [[i32, i64], i16] + - [[u32, u64], u16] + - [i64, i32] + - [u64, u32] + assert_instr: ["st1{size_literal[1]}"] + test: { store: 1 } + compose: + - LLVMLink: + name: "st1.{sve_type[0] as {type[1]}}" + arguments: + - "data: {sve_type[0] as {type[1]}}" + - "pg: {predicate[0]}" + - "ptr: *mut {type[1]}" + - FnCall: + - "{llvm_link}" + - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $base] + + - name: svst1{size_literal[1]}_vnum[_{type[0]}] + attr: [*sve-unstable] + doc: Truncate to {size[1]} bits and store + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "vnum: i64" + - "data: {sve_type[0]}" + types: + - [[i16, i32, i64], i8] + - [[u16, u32, u64], u8] + - [[i32, i64], i16] + - [[u32, u64], u16] + - [i64, i32] + - [u64, u32] + assert_instr: ["st1{size_literal[1]}"] + test: { store: 1 } + compose: + - FnCall: + - "svst1{size_literal[1]}_{type[0]}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: + [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize] + - CastAs: [$vnum, isize] + - $data + + - name: svst1_vnum[_{type}] + attr: [*sve-unstable] + doc: Non-truncating store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate}", "base: *mut {type}", "vnum: i64", "data: {sve_type}"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st1{size_literal}"] + test: { store: 0 } + compose: + - FnCall: + - "svst1_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + - $data + + - name: svst2[_{type}] + attr: [*sve-unstable] + doc: Store two vectors into two-element tuples + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *mut {type}", "data: {sve_type_x2}"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st2{size_literal}"] + test: { store: 0 } + compose: + - LLVMLink: + name: "st2.{sve_type}" + arguments: + - "data0: {sve_type}" + - "data1: {sve_type}" + - "pg: {predicate}" + - "ptr: *mut {type}" + - FnCall: + - "{llvm_link}" + - - FnCall: ["svget2_{type}", ["$data"], [0]] + - FnCall: ["svget2_{type}", ["$data"], [1]] + - "$pg" + - "$base" + + - name: svst2_vnum[_{type}] + attr: [*sve-unstable] + doc: Store two vectors into two-element tuples + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + - "pg: {predicate}" + - "base: *mut {type}" + - "vnum: i64" + - "data: {sve_type_x2}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st2{size_literal}"] + test: { store: 0 } + compose: + - FnCall: + - "svst2_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + - $data + + - name: svst3[_{type}] + attr: [*sve-unstable] + doc: Store three vectors into three-element tuples + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *mut {type}", "data: {sve_type_x3}"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st3{size_literal}"] + test: { store: 0 } + compose: + - LLVMLink: + name: "st3.{sve_type}" + arguments: + - "data0: {sve_type}" + - "data1: {sve_type}" + - "data2: {sve_type}" + - "pg: {predicate}" + - "ptr: *mut {type}" + - FnCall: + - "{llvm_link}" + - - FnCall: ["svget3_{type}", ["$data"], [0]] + - FnCall: ["svget3_{type}", ["$data"], [1]] + - FnCall: ["svget3_{type}", ["$data"], [2]] + - "$pg" + - "$base" + + - name: svst3_vnum[_{type}] + attr: [*sve-unstable] + doc: Store three vectors into three-element tuples + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + arguments: + - "pg: {predicate}" + - "base: *mut {type}" + - "vnum: i64" + - "data: {sve_type_x3}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st3{size_literal}"] + test: { store: 0 } + compose: + - FnCall: + - "svst3_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + - $data + + - name: svst4[_{type}] + attr: [*sve-unstable] + doc: Store four vectors into four-element tuples + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *mut {type}", "data: {sve_type_x4}"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st4{size_literal}"] + test: { store: 0 } + compose: + - LLVMLink: + name: "st4.{sve_type}" + arguments: + - "data0: {sve_type}" + - "data1: {sve_type}" + - "data2: {sve_type}" + - "data3: {sve_type}" + - "pg: {predicate}" + - "ptr: *mut {type}" + - FnCall: + - "{llvm_link}" + - - FnCall: ["svget4_{type}", ["$data"], [0]] + - FnCall: ["svget4_{type}", ["$data"], [1]] + - FnCall: ["svget4_{type}", ["$data"], [2]] + - FnCall: ["svget4_{type}", ["$data"], [3]] + - "$pg" + - "$base" + + - name: svst4_vnum[_{type}] + attr: [*sve-unstable] + doc: Store four vectors into four-element tuples + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + arguments: + - "pg: {predicate}" + - "base: *mut {type}" + - "vnum: i64" + - "data: {sve_type_x4}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st4{size_literal}"] + test: { store: 0 } + compose: + - FnCall: + - "svst4_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + - $data + + - name: svtbl[_{type[0]}] + attr: [*sve-unstable] + doc: Table lookup in single-vector table + arguments: ["data: {sve_type[0]}", "indices: {sve_type[1]}"] + return_type: "{sve_type[0]}" + assert_instr: [tbl] + types: + - [f32, u32] + - [f64, u64] + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + - [u8, u8] + - [u16, u16] + - [u32, u32] + - [u64, u64] + compose: + - LLVMLink: { name: "tbl.{sve_type[0]}" } + + - name: svwhilele_{type[1]}[_{type[0]}] + attr: [*sve-unstable] + doc: While incrementing scalar is less than or equal to + arguments: ["op1: {type[0]}", "op2: {type[0]}"] + return_type: "{sve_type[1]}" + types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]] + assert_instr: [{ default: whilele, unsigned: whilels }] + compose: + - MatchKind: + - "{type[0]}" + - default: { LLVMLink: { name: "whilele.{sve_type[1]}.{type[0]}" } } + unsigned: { LLVMLink: { name: "whilels.{sve_type[1]}.{type[0]}" } } + + - name: svwhilelt_{type[1]}[_{type[0]}] + attr: [*sve-unstable] + doc: While incrementing scalar is less than + arguments: ["op1: {type[0]}", "op2: {type[0]}"] + return_type: "{sve_type[1]}" + types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]] + assert_instr: [{ default: whilelt, unsigned: whilelo }] + compose: + - MatchKind: + - "{type[0]}" + - default: { LLVMLink: { name: "whilelt.{sve_type[1]}.{type[0]}" } } + unsigned: { LLVMLink: { name: "whilelo.{sve_type[1]}.{type[0]}" } } + + - name: svmax[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Maximum + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64, f32, f64] + zeroing_method: { select: op1 } + assert_instr: ["{type_kind}max"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.fsu}max.{sve_type}" } + + - name: svmaxnm[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Maximum number + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + zeroing_method: { select: op1 } + assert_instr: [fmaxnm] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.f}maxnm.{sve_type}" } + + - name: svpfalse[_b] + attr: [*sve-unstable] + doc: Set all predicate elements to false + arguments: [] + return_type: "svbool_t" + # TODO: With current implementation, `pfalse` isn't generated, will need to add intrinsic to + # generate `zeroinitializer` + # assert_instr: [pfalse] + compose: + - FnCall: + - "svdupq_n_b8" + - - false + - false + - false + - false + - false + - false + - false + - false + - false + - false + - false + - false + - false + - false + - false + - false + + - name: svptrue_pat_{type} + attr: [*sve-unstable] + doc: Set predicate elements to true + arguments: [] + static_defs: ["const PATTERN: svpattern"] + return_type: "{predicate}" + types: [b8, b16, b32, b64] + assert_instr: [[ptrue, "PATTERN = {{svpattern::SV_ALL}}"]] + compose: + - LLVMLink: + name: ptrue.{sve_type} + arguments: ["pattern: svpattern"] + - FnCall: ["{llvm_link}", [$PATTERN]] + + - name: svptrue_{type} + attr: [*sve-unstable] + doc: Set predicate elements to true + arguments: [] + return_type: "svbool_t" + types: [b8, b16, b32, b64] + assert_instr: [ptrue] + compose: + - FnCall: ["svptrue_pat_{type}", [], ["{{svpattern::SV_ALL}}"]] + + - name: svptest_any + attr: [*sve-unstable] + doc: Test whether any active element is true + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: "bool" + assert_instr: [ptest] + compose: + - LLVMLink: { name: "ptest.any.nxv16i1" } + + - name: svptest_first + attr: [*sve-unstable] + doc: Test whether first active element is true + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: "bool" + assert_instr: [ptest] + compose: + - LLVMLink: { name: "ptest.first.nxv16i1" } + + - name: svptest_last + attr: [*sve-unstable] + doc: Test whether last active element is true + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: "bool" + assert_instr: [ptest] + compose: + - LLVMLink: { name: "ptest.last.nxv16i1" } + + - name: svpfirst[_b] + attr: [*sve-unstable] + doc: Set the first active predicate element to true + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: "svbool_t" + assert_instr: [pfirst] + compose: + - LLVMLink: { name: "pfirst.nxv16i1" } + + - name: svpnext_{type} + attr: [*sve-unstable] + doc: Find next active predicate + arguments: ["pg: {predicate}", "op: {predicate}"] + return_type: "{predicate}" + types: [b8, b16, b32, b64] + assert_instr: [pnext] + compose: + - LLVMLink: { name: "pnext.{sve_type}" } + + - name: svbrkn[_b]_z + attr: [*sve-unstable] + doc: Propagate break to next partition + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: "svbool_t" + assert_instr: [brkn] + compose: + - LLVMLink: { name: "brkn.z.nxv16i1" } + + - name: svbrkb[_b]_z + attr: [*sve-unstable] + doc: Break before first true condition + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: "svbool_t" + assert_instr: [brkb] + compose: + - LLVMLink: { name: "brkb.z.nxv16i1" } + + - name: svbrkb[_b]_m + attr: [*sve-unstable] + doc: Break before first true condition + arguments: ["inactive: svbool_t", "pg: svbool_t", "op: svbool_t"] + return_type: "svbool_t" + assert_instr: [brkb] + compose: + - LLVMLink: { name: "brkb.nxv16i1" } + + - name: svbrkpb[_b]_z + attr: [*sve-unstable] + doc: Break before first true condition, propagating from previous partition + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: "svbool_t" + assert_instr: [brkpb] + compose: + - LLVMLink: { name: "brkpb.z.nxv16i1" } + + - name: svbrka[_b]_z + attr: [*sve-unstable] + doc: Break after first true condition + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: "svbool_t" + assert_instr: [brka] + compose: + - LLVMLink: { name: "brka.z.nxv16i1" } + + - name: svbrka[_b]_m + attr: [*sve-unstable] + doc: Break after first true condition + arguments: ["inactive: svbool_t", "pg: svbool_t", "op: svbool_t"] + return_type: "svbool_t" + assert_instr: [brka] + compose: + - LLVMLink: { name: "brka.nxv16i1" } + + - name: svbrkpa[_b]_z + attr: [*sve-unstable] + doc: Break after first true condition, propagating from previous partition + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: "svbool_t" + assert_instr: [brkpa] + compose: + - LLVMLink: { name: "brkpa.z.nxv16i1" } + + - name: svsel[_b] + attr: [*sve-unstable] + doc: Conditionally select elements + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: "svbool_t" + assert_instr: [sel] + compose: + - FnCall: ["simd_select", [$pg, $op1, $op2]] + + - name: svsel[_{type}] + attr: [*sve-unstable] + doc: Conditionally select elements + arguments: ["pg: svbool_t", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [sel] + compose: + - FnCall: + - "simd_select" + - - MatchSize: + - "{type}" + - { default: { MethodCall: [$pg, sve_into, []] }, byte: $pg } + - $op1 + - $op2 + - - MatchSize: + - "{type}" + - byte: svbool_t + halfword: svbool8_t + default: svbool4_t + doubleword: svbool2_t + - _ + + - name: svsub[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Subtract + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64, f32, f64] + assert_instr: ["{type_kind.f}sub"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.f}sub.{sve_type}" } + + - name: svsubr[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Subtract reversed + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64, f32, f64] + assert_instr: ["{type_kind.f}subr"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.f}subr.{sve_type}" } + + - name: svcntp_{predicate} + attr: [*sve-unstable] + doc: Count set predicate bits + arguments: ["pg: {predicate}", "op: {predicate}"] + types: [b8, b16, b32, b64] + return_type: u64 + assert_instr: [cntp] + compose: + - LLVMLink: { name: "cntp.{predicate}" } + + - name: svcompact[_{type}] + attr: [*sve-unstable] + doc: Shuffle active elements of vector to the right and fill with zero + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i32, i64, u32, u64] + assert_instr: [compact] + compose: + - LLVMLink: { name: "compact.{sve_type}" } + + - name: svlasta[_{type}] + attr: [*sve-unstable] + doc: Extract element after last + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [lasta] + compose: + - LLVMLink: { name: "lasta.{sve_type}" } + + - name: svclasta[_{type}] + attr: [*sve-unstable] + doc: Conditionally extract element after last + arguments: ["pg: {predicate}", "fallback: {sve_type}", "data: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [clasta] + compose: + - LLVMLink: { name: "clasta.{sve_type}" } + + - name: svclasta[_n_{type}] + attr: [*sve-unstable] + doc: Conditionally extract element after last + arguments: ["pg: {predicate}", "fallback: {type}", "data: {sve_type}"] + return_type: "{type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [clasta] + compose: + - LLVMLink: { name: "clasta.n.{sve_type}" } + + - name: svlastb[_{type}] + attr: [*sve-unstable] + doc: Extract last element + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [lastb] + compose: + - LLVMLink: { name: "lastb.{sve_type}" } + + - name: svclastb[_{type}] + attr: [*sve-unstable] + doc: Conditionally extract last element + arguments: ["pg: {predicate}", "fallback: {sve_type}", "data: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [clastb] + compose: + - LLVMLink: { name: "clastb.{sve_type}" } + + - name: svclastb[_n_{type}] + attr: [*sve-unstable] + doc: Conditionally extract last element + arguments: ["pg: {predicate}", "fallback: {type}", "data: {sve_type}"] + return_type: "{type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [clastb] + compose: + - LLVMLink: { name: "clastb.n.{sve_type}" } + + - name: svqdecp[_{type}] + attr: [*sve-unstable] + doc: Saturating decrement by active element count + arguments: ["op: {sve_type}", "pg: {predicate}"] + return_type: "{sve_type}" + types: [i16, i32, i64, u16, u32, u64] + assert_instr: ["{type_kind.su}qdecp"] + compose: + - LLVMLink: { name: "{type_kind.su}qdecp.{sve_type}" } + + - name: svqdecp[_n_{type[0]}]_{type[1]} + attr: [*sve-unstable] + doc: Saturating decrement by active element count + arguments: ["op: {type[0]}", "pg: {sve_type[1]}"] + return_type: "{type[0]}" + types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]] + assert_instr: ["{type_kind[0].su}qdecp"] + compose: + - LLVMLink: { name: "{type_kind[0].su}qdecp.n{size[0]}.{sve_type[1]}" } + + - name: svqincp[_{type}] + attr: [*sve-unstable] + doc: Saturating increment by active element count + arguments: ["op: {sve_type}", "pg: {predicate}"] + return_type: "{sve_type}" + types: [i16, i32, i64, u16, u32, u64] + assert_instr: ["{type_kind.su}qincp"] + compose: + - LLVMLink: { name: "{type_kind.su}qincp.{sve_type}" } + + - name: svqincp[_n_{type[0]}]_{type[1]} + attr: [*sve-unstable] + doc: Saturating increment by active element count + arguments: ["op: {type[0]}", "pg: {sve_type[1]}"] + return_type: "{type[0]}" + types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]] + assert_instr: ["{type_kind[0].su}qincp"] + compose: + - LLVMLink: { name: "{type_kind[0].su}qincp.n{size[0]}.{sve_type[1]}" } + + - name: svtmad[_{type}] + attr: [*sve-unstable] + doc: Trigonometric multiply-add coefficient + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + static_defs: ["const IMM3: i32"] + constraints: [{ variable: IMM3, range: [0, 7] }] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [[ftmad, "IMM3 = 0"]] + compose: + - LLVMLink: + name: "ftmad.x.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"] + - FnCall: + - "{llvm_link}" + - [op1, op2, IMM3] + + - name: svtsmul[_{type[0]}] + attr: [*sve-unstable] + doc: Trigonometric starting value + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [f32, u32] + - [f64, u64] + assert_instr: [ftsmul] + compose: + - LLVMLink: + name: "ftsmul.x.{sve_type[0]}" + + - name: svtssel[_{type[0]}] + attr: [*sve-unstable] + doc: Trigonometric select coefficient + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [f32, u32] + - [f64, u64] + assert_instr: [ftssel] + compose: + - LLVMLink: + name: "ftssel.x.{sve_type[0]}" + + - name: svprf{size_literal} + attr: [*sve-unstable] + safety: + unsafe: + - pointer_offset: predicated + substitutions: + textual_size: + match_size: "{type}" + default: words + byte: bytes + halfword: halfwords + doubleword: doublewords + doc: Prefetch {textual_size} + arguments: ["pg: {predicate}", "base: *T"] + static_defs: ["const OP: svprfop", T] + types: [b8, b16, b32, b64] + assert_instr: + - ["prf{size_literal}", "OP = {{svprfop::SV_PLDL1KEEP}}, T = i64"] + test: { load: 0 } + compose: + - LLVMLink: + name: "prf.{sve_type}" + arguments: + ["pg: {predicate}", "base: *crate::ffi::c_void", "op: svprfop"] + - FnCall: + - "{llvm_link}" + - - $pg + - CastAs: [$base, "*const crate::ffi::c_void"] + - $OP + + - name: svprf{size_literal}_vnum + attr: [*sve-unstable] + safety: + unsafe: + - pointer_offset_vnum: predicated + substitutions: + textual_size: + match_size: "{type}" + default: words + byte: bytes + halfword: halfwords + doubleword: doublewords + doc: Prefetch {textual_size} + arguments: ["pg: {predicate}", "base: *T", "vnum: i64"] + static_defs: ["const OP: svprfop", T] + types: [b8, b16, b32, b64] + assert_instr: + - ["prf{size_literal}", "OP = {{svprfop::SV_PLDL1KEEP}}, T = i64"] + test: { load: 0 } + compose: + - FnCall: + - "svprf{size_literal}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + - - $OP + - _ + + - name: svprf{size_literal[1]}_gather_[{type[0]}]{index_or_offset} + attr: [*sve-unstable] + safety: + unsafe: + - pointer_offset: predicated + substitutions: + index_or_offset: + { match_size: "{type[1]}", default: "index", byte: "offset" } + indices_or_offsets: + { match_size: "{type[1]}", default: "indices", byte: "offsets" } + textual_size: + match_size: "{type[1]}" + default: words + byte: bytes + halfword: halfwords + doubleword: doublewords + doc: Prefetch {textual_size} + types: + - [[i32, u32, i64, u64], [i8, i16, i32, i64]] + arguments: + ["pg: {predicate[0]}", "base: *T", "{indices_or_offsets}: {sve_type[0]}"] + static_defs: ["const OP: svprfop", T] + assert_instr: + [["prf{size_literal[1]}", "OP = {{svprfop::SV_PLDL1KEEP}}, T = i64"]] + test: { load: 0 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "prf{size_literal[1]}.gather.{type_kind[0].su}xtw.index.{sve_type[0]}" + arguments: + - "pg: {predicate[0]}" + - "base: *crate::ffi::c_void" + - "{indices_or_offsets}: {sve_type[0]}" + - "op: svprfop" + doubleword: + LLVMLink: + name: "prf{size_literal[1]}.gather.index.{sve_type[0]}" + arguments: + - "pg: {predicate[0]}" + - "base: *crate::ffi::c_void" + - "{indices_or_offsets}: {sve_type[0]}" + - "op: svprfop" + - FnCall: + - "{llvm_link}" + - - $pg + - CastAs: [$base, "*const crate::ffi::c_void"] + - "${indices_or_offsets}" + - $OP + + - name: svprf{size_literal[1]}_gather[_{type[0]}base] + attr: [*sve-unstable] + safety: + unsafe: + - pointer_offset: predicated + - no_provenance: bases + substitutions: + textual_size: + match_size: "{type[1]}" + default: words + byte: bytes + halfword: halfwords + doubleword: doublewords + doc: Prefetch {textual_size} + types: + - [[u32, u64], [i8, i16, i32, i64]] + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + static_defs: ["const OP: svprfop"] + assert_instr: [["prf{size_literal[1]}", "OP = {{svprfop::SV_PLDL1KEEP}}"]] + test: { load: 0 } + compose: + - LLVMLink: + name: "prf{size_literal[1]}.gather.scalar.offset.{sve_type[0]}" + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "index: i64" + - "op: svprfop" + - FnCall: ["{llvm_link}", [$pg, $bases, 0, $OP]] + + - name: svprf{size_literal[1]}_gather[_{type[0]}base]_{index_or_offset} + attr: [*sve-unstable] + safety: + unsafe: + - pointer_offset: predicated + - no_provenance: bases + substitutions: + index_or_offset: + { match_size: "{type[1]}", default: "index", byte: "offset" } + textual_size: + match_size: "{type[1]}" + default: words + byte: bytes + halfword: halfwords + doubleword: doublewords + doc: Prefetch {textual_size} + types: + - [[u32, u64], [i8, i16, i32, i64]] + arguments: + ["pg: {predicate[0]}", "bases: {sve_type[0]}", "{index_or_offset}: i64"] + static_defs: ["const OP: svprfop"] + assert_instr: [["prfb", "OP = {{svprfop::SV_PLDL1KEEP}}"]] + test: { load: 0 } + compose: + - LLVMLink: + name: "prf{size_literal[1]}.gather.scalar.offset.{sve_type[0]}" + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "{index_or_offset}: i64" + - "op: svprfop" + - FnCall: + - "{llvm_link}" + - - $pg + - $bases + - MatchSize: + - "{type[1]}" + - byte: $offset + halfword: { MethodCall: [$index, unchecked_shl, [1]] } + default: { MethodCall: [$index, unchecked_shl, [2]] } + doubleword: { MethodCall: [$index, unchecked_shl, [3]] } + - $OP + + - name: svcvt_{type[0]}[_{type[1]}]{_mxz} + attr: [*sve-unstable] + doc: Floating-point convert + arguments: + ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [f32, [i64, u64]] + - [f64, [i32, u32]] + zeroing_method: { drop: inactive } + substitutions: + convert_from: { match_kind: "{type[1]}", default: s, unsigned: u } + assert_instr: ["{convert_from}cvtf"] + compose: + - LLVMLink: + name: "{convert_from}cvtf.{type[0]}{type[1]}" + + - name: svcvt_{type[0]}[_{type[1]}]{_mxz} + attr: [*sve-unstable] + doc: Floating-point convert + arguments: + ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [f32, [i32, u32]] + - [f64, [i64, u64]] + zeroing_method: { drop: inactive } + substitutions: + convert_from: { match_kind: "{type[1]}", default: s, unsigned: u } + assert_instr: ["{convert_from}cvtf"] + compose: + - LLVMLink: + name: "{convert_from}cvtf.{sve_type[0]}.{sve_type[1]}" + + - name: svcvt_{type[0]}[_{type[1]}]{_mxz} + attr: [*sve-unstable] + doc: Floating-point convert + arguments: + ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i32, u32], f64] + - [[i64, u64], f32] + zeroing_method: { drop: inactive } + substitutions: + convert_to: { match_kind: "{type[0]}", default: s, unsigned: u } + assert_instr: ["fcvtz{convert_to}"] + compose: + - LLVMLink: { name: "fcvtz{convert_to}.{type[0]}{type[1]}" } + + - name: svcvt_{type[0]}[_{type[1]}]{_mxz} + attr: [*sve-unstable] + doc: Floating-point convert + arguments: + ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i32, u32], f32] + - [[i64, u64], f64] + zeroing_method: { drop: inactive } + substitutions: + convert_to: { match_kind: "{type[0]}", default: s, unsigned: u } + assert_instr: ["fcvtz{convert_to}"] + compose: + - LLVMLink: { name: "fcvtz{convert_to}.{sve_type[0]}.{sve_type[1]}" } + + - name: svcvt_{type[0]}[_{type[1]}]{_mxz} + attr: [*sve-unstable] + doc: Floating-point convert + arguments: + ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f32, f64], [f64, f32]] + zeroing_method: { drop: inactive } + assert_instr: [fcvt] + compose: + - LLVMLink: { name: "fcvt.{type[0]}{type[1]}" } + + - name: svreinterpret_{type[0]}[_{type[1]}] + attr: [*sve-unstable] + doc: Reinterpret vector contents + arguments: ["op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + assert_instr: [] + types: + - - [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + - [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + compose: + - FnCall: ["crate::intrinsics::transmute_unchecked", [$op], [], true] + + - name: svrinta[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Round to nearest, ties away from zero + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frinta] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frinta.{sve_type}" } + + - name: svrinti[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Round using current rounding mode (inexact) + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frinti] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frinti.{sve_type}" } + + - name: svrintm[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Round towards -∞ + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frintm] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frintm.{sve_type}" } + + - name: svrintn[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Round to nearest, ties to even + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frintn] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frintn.{sve_type}" } + + - name: svrintp[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Round towards +∞ + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frintp] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frintp.{sve_type}" } + + - name: svrintx[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Round using current rounding mode (exact) + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frintx] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frintx.{sve_type}" } + + - name: svrintz[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Round towards zero + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frintz] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frintz.{sve_type}" } + + - name: svabd[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Absolute difference + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f64, f32, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind}abd"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind}abd.{sve_type}" } + + - name: svabs[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Absolute value + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64] + assert_instr: ["{type_kind.f}abs"] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "{type_kind.f}abs.{sve_type}" } + + - name: svand[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Bitwise AND + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [and] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op2 + zeroing_method: { select: op1 } + compose: + - LLVMLink: { name: "and.{sve_type}" } + + - name: svandv[_{type}] + attr: [*sve-unstable] + doc: Bitwise AND reduction to scalar + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + assert_instr: [andv] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + compose: + - LLVMLink: { name: "andv.{sve_type}" } + + - name: svand[_b]_z + attr: [*sve-unstable] + doc: Bitwise AND + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: svbool_t + assert_instr: [and] + compose: + - LLVMLink: { name: "and.z.nxv16i1" } + + - name: svmov[_b]_z + attr: [*sve-unstable] + doc: Move + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: svbool_t + assert_instr: [mov] + compose: + - FnCall: ["svand_b_z", [$pg, $op, $op]] + + - name: svbic[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Bitwise clear + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [bic] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op2 + zeroing_method: { select: op1 } + compose: + - LLVMLink: { name: "bic.{sve_type}" } + + - name: svbic[_b]_z + attr: [*sve-unstable] + doc: Bitwise clear + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: svbool_t + assert_instr: [bic] + compose: + - LLVMLink: { name: "bic.z.nxv16i1" } + + - name: sveor[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Bitwise exclusive OR + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [eor] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op2 + zeroing_method: { select: op1 } + compose: + - LLVMLink: { name: "eor.{sve_type}" } + + - name: sveorv[_{type}] + attr: [*sve-unstable] + doc: Bitwise exclusive OR reduction to scalar + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + assert_instr: [eorv] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + compose: + - LLVMLink: { name: "eorv.{sve_type}" } + + - name: sveor[_b]_z + attr: [*sve-unstable] + doc: Bitwise exclusive OR + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: svbool_t + assert_instr: [eor] + compose: + - LLVMLink: { name: "eor.z.nxv16i1" } + + - name: svnot[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Bitwise invert + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [not] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "not.{sve_type}" } + + - name: svnot[_b]_z + attr: [*sve-unstable] + doc: Bitwise invert + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: svbool_t + assert_instr: [not] + compose: + - FnCall: ["sveor_b_z", [$pg, $op, $pg]] + + - name: svcnot[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Logically invert boolean condition + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [cnot] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "cnot.{sve_type}" } + + - name: svnand[_b]_z + attr: [*sve-unstable] + doc: Bitwise NAND + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: svbool_t + assert_instr: [nand] + compose: + - LLVMLink: { name: "nand.z.nxv16i1" } + + - name: svnor[_b]_z + attr: [*sve-unstable] + doc: Bitwise NOR + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: svbool_t + assert_instr: [nor] + compose: + - LLVMLink: { name: "nor.z.nxv16i1" } + + - name: svorr[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Bitwise inclusive OR + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [orr] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op2 + zeroing_method: { select: op1 } + compose: + - LLVMLink: { name: "orr.{sve_type}" } + + - name: svorv[_{type}] + attr: [*sve-unstable] + doc: Bitwise inclusive OR reduction to scalar + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + assert_instr: [orv] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + compose: + - LLVMLink: { name: "orv.{sve_type}" } + + - name: svorr[_b]_z + attr: [*sve-unstable] + doc: Bitwise inclusive OR + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: svbool_t + assert_instr: [orr] + compose: + - LLVMLink: { name: "orr.z.nxv16i1" } + + - name: svorn[_b]_z + attr: [*sve-unstable] + doc: Bitwise inclusive OR, inverting second argument + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: svbool_t + assert_instr: [orn] + compose: + - LLVMLink: { name: "orn.z.nxv16i1" } + + - name: svlsl[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Logical shift left + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i8, u8], u8] + - [[i16, u16], u16] + - [[i32, u32], u32] + - [[i64, u64], u64] + assert_instr: [lsl] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "lsl.{sve_type[0]}" } + + - name: svlsl_wide[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Logical shift left + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i8, i16, i32, u8, u16, u32], u64] + assert_instr: [lsl] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "lsl.wide.{sve_type[0]}" } + + - name: svasr[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Arithmetic shift right + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + assert_instr: [asr] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "asr.{sve_type[0]}" } + + - name: svasr_wide[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Arithmetic shift right + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i8, i16, i32], u64] + assert_instr: [asr] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "asr.wide.{sve_type[0]}" } + + - name: svasrd[_n_{type}]{_mxz} + attr: [*sve-unstable] + doc: Arithmetic shift right for divide by immediate + arguments: ["pg: {predicate}", "op1: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size}"] }] + types: [i8, i16, i32, i64] + assert_instr: [[asrd, "IMM2 = 1"]] + zeroing_method: { select: op1 } + compose: + - LLVMLink: + name: "asrd.{sve_type}" + arguments: ["pg: {predicate}", "op1: {sve_type}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$pg, $op1, $IMM2]] + + - name: svlsr[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Logical shift right + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8, u16, u32, u64] + assert_instr: [lsr] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "lsr.{sve_type}" } + + - name: svlsr_wide[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Logical shift right + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[u8, u16, u32], u64] + assert_instr: [lsr] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "lsr.wide.{sve_type[0]}" } + + - name: svadda[_{type}] + attr: [*sve-unstable] + doc: Add reduction (strictly-ordered) + arguments: ["pg: {predicate}", "initial: {type}", "op: {sve_type}"] + return_type: "{type}" + assert_instr: [fadda] + types: [f32, f64] + compose: + - LLVMLink: { name: "fadda.{sve_type}" } + + - name: svaddv[_{type}] + attr: [*sve-unstable] + doc: Add reduction + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + types: [f32, f64, i64, u64] + assert_instr: [{ float: faddv, default: uaddv }] + compose: + - LLVMLink: { name: "{type_kind.fsu}addv.{sve_type}" } + + - name: svaddv[_{type[0]}] + attr: [*sve-unstable] + doc: Add reduction + arguments: ["pg: {predicate[0]}", "op: {sve_type[0]}"] + return_type: "{type[1]}" + types: + - [[i8, i16, i32], i64] + - [[u8, u16, u32], u64] + assert_instr: ["{type_kind[0].su}addv"] + compose: + - LLVMLink: { name: "{type_kind[0].su}addv.{sve_type[0]}" } + + - name: svmaxv[_{type}] + attr: [*sve-unstable] + doc: Maximum reduction to scalar + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.fsu}maxv"] + compose: + - LLVMLink: { name: "{type_kind.fsu}maxv.{sve_type}" } + + - name: svmaxnmv[_{type}] + attr: [*sve-unstable] + doc: Maximum number reduction to scalar + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + types: [f32, f64] + assert_instr: [fmaxnmv] + compose: + - LLVMLink: { name: "fmaxnmv.{sve_type}" } + + - name: svminv[_{type}] + attr: [*sve-unstable] + doc: Minimum reduction to scalar + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.fsu}minv"] + compose: + - LLVMLink: { name: "{type_kind.fsu}minv.{sve_type}" } + + - name: svminnmv[_{type}] + attr: [*sve-unstable] + doc: Minimum number reduction to scalar + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + types: [f32, f64] + assert_instr: [fminnmv] + compose: + - LLVMLink: { name: "fminnmv.{sve_type}" } + + - name: svmul[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Multiply + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: ["{type_kind.f}mul"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.f}mul.{sve_type}" } + + - name: svmulh[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Multiply, returning high-half + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: ["{type_kind.su}mulh"] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}mulh.{sve_type}" } + + - name: svmulx[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Multiply extended (∞×0=2) + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: ["fmulx"] + types: [f32, f64] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "fmulx.{sve_type}" } + + - name: svrecpe[_{type}] + attr: [*sve-unstable] + doc: Reciprocal estimate + arguments: ["op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frecpe] + compose: + - LLVMLink: { name: "frecpe.x.{sve_type}" } + + - name: svrecps[_{type}] + attr: [*sve-unstable] + doc: Reciprocal step + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frecps] + compose: + - LLVMLink: { name: "frecps.x.{sve_type}" } + + - name: svrecpx[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Reciprocal exponent + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frecpx] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frecpx.{sve_type}" } + + - name: svrsqrte[_{type}] + attr: [*sve-unstable] + doc: Reciprocal square root estimate + arguments: ["op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frsqrte] + compose: + - LLVMLink: { name: "frsqrte.x.{sve_type}" } + + - name: svrsqrts[_{type}] + attr: [*sve-unstable] + doc: Reciprocal square root step + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frsqrts] + compose: + - LLVMLink: { name: "frsqrts.x.{sve_type}" } + + - name: svmad[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Multiply-add, multiplicand first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: ["{type_kind.f}mad"] + compose: + - LLVMLink: { name: "{type_kind.f}mad.{sve_type}" } + + - name: svmla[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Multiply-add, addend first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: ["{type_kind.f}mla"] + compose: + - LLVMLink: { name: "{type_kind.f}mla.{sve_type}" } + + - name: svmla_lane[_{type}] + attr: [*sve-unstable] + doc: Multiply-add, addend first + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + types: [f32, f64] + assert_instr: [[fmla, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "fmla.lane.{sve_type}" + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svmls[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Multiply-subtract, minuend first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: ["{type_kind.f}mls"] + compose: + - LLVMLink: { name: "{type_kind.f}mls.{sve_type}" } + + - name: svmls_lane[_{type}] + attr: [*sve-unstable] + doc: Multiply-subtract, minuend first + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + types: [f32, f64] + assert_instr: [[fmls, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "fmls.lane.{sve_type}" + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svmsb[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Multiply-subtract, multiplicand first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: ["{type_kind.f}msb"] + compose: + - LLVMLink: { name: "{type_kind.f}msb.{sve_type}" } + + - name: svnmad[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Negated multiply-add, multiplicand first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: [fnmad] + compose: + - LLVMLink: { name: "fnmad.{sve_type}" } + + - name: svnmla[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Negated multiply-add, addend first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: [fnmla] + compose: + - LLVMLink: { name: "fnmla.{sve_type}" } + + - name: svnmls[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Negated multiply-subtract, minuend first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: [fnmls] + compose: + - LLVMLink: { name: "fnmls.{sve_type}" } + + - name: svnmsb[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Negated multiply-subtract, multiplicand first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: [fnmsb] + compose: + - LLVMLink: { name: "fnmsb.{sve_type}" } + + - name: svneg[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Negate + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64] + assert_instr: ["{type_kind.f}neg"] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "{type_kind.f}neg.{sve_type}" } + + - name: svqadd[{_n}_{type}] + attr: [*sve-unstable] + doc: Saturating add + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.su}qadd"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}qadd.x.{sve_type}" } + + - name: svadr{size_literal[2]}[_{type[0]}base]_[{type[1]}]{index_or_offset} + attr: [*sve-unstable] + substitutions: + index_or_offset: { match_size: "{type[2]}", default: index, byte: offset } + indices_or_offsets: + { match_size: "{type[2]}", default: indices, byte: offsets } + doc: Compute vector addresses for {size[2]}-bit data + arguments: ["bases: {sve_type[0]}", "{indices_or_offsets}: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [u32, [i32, u32], [i8, i16, i32, i64]] + - [u64, [i64, u64], [i8, i16, i32, i64]] + assert_instr: [adr] + compose: + - LLVMLink: { name: "adr{size_literal[2]}.{sve_type[0]}" } + + - name: svdot[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Dot product + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i32, i8] + - [i64, i16] + - [u32, u8] + - [u64, u16] + assert_instr: ["{type_kind[0].su}dot"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind[0].su}dot.{sve_type[0]}" } + + - name: svdot_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Dot product + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[0]}" }] + types: + - [i32, i8] + - [i64, i16] + - [u32, u8] + - [u64, u16] + assert_instr: [["{type_kind[0].su}dot", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}dot.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "imm_index: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svusdot[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Dot product (unsigned × signed) + target_features: [i8mm] + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[2]}"] + return_type: "{sve_type[0]}" + types: [[i32, u8, i8]] + assert_instr: [usdot] + n_variant_op: op3 + compose: + - LLVMLink: { name: "usdot.{sve_type[0]}" } + + - name: svusdot_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Dot product (unsigned × signed) + target_features: [i8mm] + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[2]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[0]}" }] + types: [[i32, u8, i8]] + assert_instr: [[usdot, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "usdot.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[2]}" + - "imm_index: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svsudot[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Dot product (signed × unsigned) + target_features: [i8mm] + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[2]}"] + return_type: "{sve_type[0]}" + types: [[i32, i8, u8]] + assert_instr: [usdot] + n_variant_op: op3 + compose: + - FnCall: ["svusdot_{type[0]}", [$op1, $op3, $op2]] + + - name: svsudot_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Dot product (signed × unsigned) + target_features: [i8mm] + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[2]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[0]}" }] + types: [[i32, i8, u8]] + assert_instr: [[sudot, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "sudot.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[2]}" + - "imm_index: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svdiv[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Divide + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i32, i64, u32, u64] + assert_instr: ["{type_kind.fsu}div"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.fsu}div.{sve_type}" } + + - name: svdivr[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Divide reversed + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i32, i64, u32, u64] + assert_instr: ["{type_kind.fsu}divr"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.fsu}divr.{sve_type}" } + + - name: svexpa[_{type[0]}] + attr: [*sve-unstable] + doc: Floating-point exponential accelerator + arguments: ["op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f32, u32], [f64, u64]] + assert_instr: [fexpa] + compose: + - LLVMLink: { name: "fexpa.x.{sve_type[0]}" } + + - name: svscale[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Adjust exponent + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f32, i32], [f64, i64]] + assert_instr: [fscale] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "fscale.{sve_type[0]}" } + + - name: svmmla[_{type}] + attr: [*sve-unstable] + doc: Matrix multiply-accumulate + target_features: [f32mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [f32] + assert_instr: [fmmla] + compose: + - LLVMLink: { name: "fmmla.{sve_type}.{sve_type}" } + + - name: svmmla[_{type}] + attr: [*sve-unstable] + doc: Matrix multiply-accumulate + target_features: [f64mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [f64] + assert_instr: [fmmla] + compose: + - LLVMLink: { name: "fmmla.{sve_type}.{sve_type}" } + + - name: svmmla[_{type[0]}] + attr: [*sve-unstable] + doc: Matrix multiply-accumulate + target_features: [i8mm] + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i32, i8], [u32, u8]] + assert_instr: ["{type_kind[0].su}mmla"] + compose: + - LLVMLink: { name: "{type_kind[0].su}mmla.{sve_type[0]}" } + + - name: svusmmla[_{type[0]}] + attr: [*sve-unstable] + doc: Matrix multiply-accumulate (unsigned × signed) + target_features: [i8mm] + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[2]}"] + return_type: "{sve_type[0]}" + types: [[i32, u8, i8]] + assert_instr: [usmmla] + compose: + - LLVMLink: { name: "usmmla.{sve_type[0]}" } + + - name: svmin[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Minimum + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + assert_instr: ["{type_kind.fsu}min"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.fsu}min.{sve_type}" } + + - name: svminnm[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Minimum number + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + zeroing_method: { select: op1 } + assert_instr: [fminnm] + n_variant_op: op2 + compose: + - LLVMLink: { name: "fminnm.{sve_type}" } diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/sve2/aarch64.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/sve2/aarch64.spec.yml new file mode 100644 index 0000000000000..269d7ff0eacbb --- /dev/null +++ b/library/stdarch/crates/stdarch-gen-arm/spec/sve2/aarch64.spec.yml @@ -0,0 +1,3206 @@ +arch_cfgs: + - arch_name: aarch64 + target_feature: [sve, sve2] + llvm_prefix: llvm.aarch64.sve + +auto_llvm_sign_conversion: true +generate_load_store_tests: true + +# `#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]` +sve-unstable: &sve-unstable + FnCall: [unstable, ['feature = "stdarch_aarch64_sve"', 'issue= "145052"']] + +# `#[cfg_attr(all(test, not(target_env = "msvc"))]` +msvc-disabled: &msvc-disabled + FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]] + +intrinsics: + - name: svbext[{_n}_{type}] + attr: [*sve-unstable] + target_features: [sve2-bitperm] + doc: Gather lower bits from positions selected by bitmask + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8, u16, u32, u64] + assert_instr: [bext] + n_variant_op: op2 + compose: + - LLVMLink: { name: "bext.x.{sve_type}" } + + - name: svbgrp[{_n}_{type}] + attr: [*sve-unstable] + target_features: [sve2-bitperm] + doc: Group bits to right or left as selected by bitmask + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8, u16, u32, u64] + assert_instr: [bgrp] + n_variant_op: op2 + compose: + - LLVMLink: { name: "bgrp.x.{sve_type}" } + + - name: svbdep[{_n}_{type}] + attr: [*sve-unstable] + target_features: [sve2-bitperm] + doc: Scatter lower bits into positions selected by bitmask + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8, u16, u32, u64] + assert_instr: [bdep] + n_variant_op: op2 + compose: + - LLVMLink: { name: "bdep.x.{sve_type}" } + + - name: svhistcnt[_{type[0]}]_z + attr: [*sve-unstable] + doc: Count matching elements + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: [[i32, u32], [i64, u64], [u32, u32], [u64, u64]] + assert_instr: [histcnt] + compose: + - LLVMLink: { name: "histcnt.{sve_type[0]}" } + + - name: svhistseg[_{type[0]}] + attr: [*sve-unstable] + doc: Count matching elements in 128-bit segments + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: [[i8, u8], [u8, u8]] + assert_instr: [histseg] + compose: + - LLVMLink: { name: "histseg.{sve_type[0]}" } + + - name: svmatch[_{type}] + attr: [*sve-unstable] + doc: Detect any matching elements + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [i8, i16, u8, u16] + assert_instr: [match] + compose: + - LLVMLink: { name: "match.{sve_type}" } + + - name: svnmatch[_{type}] + attr: [*sve-unstable] + doc: Detect no matching elements + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [i8, i16, u8, u16] + assert_instr: [nmatch] + compose: + - LLVMLink: { name: "nmatch.{sve_type}" } + + - name: svhadd[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Halving add + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + assert_instr: ["{type_kind.su}hadd"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}hadd.{sve_type}" } + + - name: svrhadd[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Rounding halving add + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + assert_instr: ["{type_kind.su}rhadd"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}rhadd.{sve_type}" } + + - name: svaddhnb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Add narrow high part (bottom) + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + return_type: "{sve_type[1]}" + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[0]}"] + assert_instr: [addhnb] + n_variant_op: op2 + compose: + - LLVMLink: { name: "addhnb.{sve_type[0]}" } + + - name: svaddhnt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Add narrow high part (top) + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + return_type: "{sve_type[1]}" + arguments: + ["even: {sve_type[1]}", "op1: {sve_type[0]}", "op2: {sve_type[0]}"] + assert_instr: [addhnt] + n_variant_op: op2 + compose: + - LLVMLink: { name: "addhnt.{sve_type[0]}" } + + - name: svraddhnb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Rounding add narrow high part (bottom) + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + return_type: "{sve_type[1]}" + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[0]}"] + assert_instr: [raddhnb] + n_variant_op: op2 + compose: + - LLVMLink: { name: "raddhnb.{sve_type[0]}" } + + - name: svraddhnt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Rounding add narrow high part (top) + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + return_type: "{sve_type[1]}" + arguments: + ["even: {sve_type[1]}", "op1: {sve_type[0]}", "op2: {sve_type[0]}"] + assert_instr: [raddhnt] + n_variant_op: op2 + compose: + - LLVMLink: { name: "raddhnt.{sve_type[0]}" } + + - name: svcadd[_{type}] + attr: [*sve-unstable] + doc: Complex add with rotate + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + static_defs: ["const IMM_ROTATION: i32"] + constraints: [{ variable: IMM_ROTATION, any_values: [90, 270] }] + assert_instr: [[cadd, "IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: cadd.x.{sve_type} + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm_rotation: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM_ROTATION]] + + - name: svcdot[_{type[0]}] + attr: [*sve-unstable] + doc: Complex dot product + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i32, i8], [i64, i16]] + static_defs: ["const IMM_ROTATION: i32"] + constraints: [{ variable: IMM_ROTATION, any_values: [0, 90, 180, 270] }] + assert_instr: [[cdot, "IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: cdot.{sve_type[0]} + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_ROTATION]] + + - name: svcdot_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Complex dot product + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i32, i8], [i64, i16]] + static_defs: ["const IMM_INDEX: i32", "const IMM_ROTATION: i32"] + constraints: + - { variable: IMM_INDEX, vec_max_elems_type: "{type[0]}" } + - { variable: IMM_ROTATION, any_values: [0, 90, 180, 270] } + assert_instr: [[cdot, "IMM_INDEX = 0, IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: cdot.lane.{sve_type[0]} + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "imm_index: i32" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX, $IMM_ROTATION]] + + - name: svcmla[_{type}] + attr: [*sve-unstable] + doc: Complex multiply-add with rotate + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + static_defs: ["const IMM_ROTATION: i32"] + constraints: [{ variable: IMM_ROTATION, any_values: [0, 90, 180, 270] }] + assert_instr: [[cmla, "IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: cmla.x.{sve_type} + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_ROTATION]] + + - name: svcmla_lane[_{type}] + attr: [*sve-unstable] + doc: Complex multiply-add with rotate + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [i16, i32, u16, u32] + static_defs: ["const IMM_INDEX: i32", "const IMM_ROTATION: i32"] + constraints: + - variable: IMM_INDEX + range: { match_size: "{type}", default: [0, 1], halfword: [0, 3] } + - { variable: IMM_ROTATION, any_values: [0, 90, 180, 270] } + assert_instr: [[cmla, "IMM_INDEX = 0, IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: cmla.lane.x.{sve_type} + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "imm_index: i32" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX, $IMM_ROTATION]] + + - name: svqrdcmlah[_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling complex multiply-add high with rotate + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + static_defs: ["const IMM_ROTATION: i32"] + constraints: [{ variable: IMM_ROTATION, any_values: [0, 90, 180, 270] }] + assert_instr: [[sqrdcmlah, "IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: sqrdcmlah.x.{sve_type} + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_ROTATION]] + + - name: svqrdcmlah_lane[_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling complex multiply-add high with rotate + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [i16, i32] + static_defs: ["const IMM_INDEX: i32", "const IMM_ROTATION: i32"] + constraints: + - variable: IMM_INDEX + range: { match_size: "{type}", default: [0, 1], halfword: [0, 3] } + - { variable: IMM_ROTATION, any_values: [0, 90, 180, 270] } + assert_instr: [[sqrdcmlah, "IMM_INDEX = 0, IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: sqrdcmlah.lane.x.{sve_type} + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "imm_index: i32" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX, $IMM_ROTATION]] + + - name: svqcadd[_{type}] + attr: [*sve-unstable] + doc: Saturating complex add with rotate + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + static_defs: ["const IMM_ROTATION: i32"] + constraints: [{ variable: "IMM_ROTATION", any_values: [90, 270] }] + assert_instr: [[sqcadd, "IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: "sqcadd.x.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm_rotation: i32"] + - FnCall: ["{llvm_link}", ["$op1", "$op2", "$IMM_ROTATION"]] + + - name: svsublb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract long (bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}sublb"] + n_variant_op: op2 + compose: + - LLVMLink: + name: "{type_kind[0].su}sublb.{sve_type[0]}" + + - name: svsublbt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract long (bottom - top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + assert_instr: [ssublbt] + n_variant_op: op2 + compose: + - LLVMLink: + name: "ssublbt.{sve_type[0]}" + + - name: svsublt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract long (top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}sublt"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}sublt.{sve_type[0]}" } + + - name: svsubltb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract long (top - bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + assert_instr: [ssubltb] + n_variant_op: op2 + compose: + - LLVMLink: + name: "ssubltb.{sve_type[0]}" + + - name: svsubwb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract wide (bottom) + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}subwb"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}subwb.{sve_type[0]}" } + + - name: svsubwt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract wide (top) + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}subwt"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}subwt.{sve_type[0]}" } + + - name: svrsubhnb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Rounding subtract narrow high part (bottom) + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [rsubhnb] + n_variant_op: op2 + compose: + - LLVMLink: { name: "rsubhnb.{sve_type[0]}" } + + - name: svrsubhnt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Rounding subtract narrow high part (top) + arguments: + ["even: {sve_type[1]}", "op1: {sve_type[0]}", "op2: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [rsubhnt] + n_variant_op: op2 + compose: + - LLVMLink: { name: "rsubhnt.{sve_type[0]}" } + + - name: svsubhnb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract narrow high part (bottom) + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [subhnb] + n_variant_op: op2 + compose: + - LLVMLink: { name: "subhnb.{sve_type[0]}" } + + - name: svsubhnt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract narrow high part (top) + arguments: + ["even: {sve_type[1]}", "op1: {sve_type[0]}", "op2: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [subhnt] + n_variant_op: op2 + compose: + - LLVMLink: { name: "subhnt.{sve_type[0]}" } + + - name: svsbclb[{_n}_{type}] + attr: [*sve-unstable] + doc: Subtract with borrow long (bottom) + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [u32, u64] + assert_instr: [sbclb] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sbclb.{sve_type}" } + + - name: svsbclt[{_n}_{type}] + attr: [*sve-unstable] + doc: Subtract with borrow long (top) + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [u32, u64] + assert_instr: [sbclt] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sbclt.{sve_type}" } + + - name: svqsub[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Saturating subtract + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + assert_instr: ["{type_kind.su}qsub"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}qsub.{sve_type}" } + + - name: svqsubr[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Saturating subtract reversed + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + assert_instr: ["{type_kind.su}qsubr"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}qsubr.{sve_type}" } + + - name: svhsub[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Halving subtract + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.su}hsub"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}hsub.{sve_type}" } + + - name: svhsubr[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Halving subtract reversed + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.su}hsub"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}hsubr.{sve_type}" } + + - name: svwhilege_{sve_type[1]}[_{type[0]}] + attr: [*sve-unstable] + doc: While decrementing scalar is greater than or equal to + arguments: ["op1: {type[0]}", "op2: {type[0]}"] + return_type: "{sve_type[1]}" + types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]] + assert_instr: [{ default: whilege, unsigned: whilehs }] + compose: + - MatchKind: + - "{type[0]}" + - default: { LLVMLink: { name: "whilege.{sve_type[1]}.{type[0]}" } } + unsigned: { LLVMLink: { name: "whilehs.{sve_type[1]}.{type[0]}" } } + + - name: svwhilegt_{sve_type[1]}[_{type[0]}] + attr: [*sve-unstable] + doc: While decrementing scalar is greater than + arguments: ["op1: {type[0]}", "op2: {type[0]}"] + return_type: "{sve_type[1]}" + types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]] + assert_instr: [{ default: whilegt, unsigned: whilehi }] + compose: + - MatchKind: + - "{type[0]}" + - default: { LLVMLink: { name: "whilegt.{sve_type[1]}.{type[0]}" } } + unsigned: { LLVMLink: { name: "whilehi.{sve_type[1]}.{type[0]}" } } + + - name: svwhilerw_{size}ptr + attr: [*sve-unstable] + safety: + unsafe: [] + visibility: private + static_defs: [T] + substitutions: + size_alt: + match_size: "{type}" + byte: b + halfword: h + default: s + doubleword: d + arguments: ["op1: *T", "op2: *T"] + return_type: "{predicate}" + types: [i8, i16, i32, i64] + assert_instr: [] + compose: + - Let: [op1, CastAs: [$op1, "*const crate::ffi::c_void"]] + - Let: [op2, CastAs: [$op2, "*const crate::ffi::c_void"]] + - LLVMLink: + name: "whilerw.{size_alt}.{predicate}.p0" + arguments: ["op1: *crate::ffi::c_void", "op2: *crate::ffi::c_void"] + + - name: svwhilerw[_{type}] + attr: [*sve-unstable] + doc: While free of read-after-write conflicts + # TODO: This might be safe even with unrelated pointers, but the LLVM builtin's guarantees don't + # seem to be documented, so we conservatively keep this unsafe for now. + safety: + unsafe: + - custom: "[`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints + must be met for at least the base pointers, `op1` and `op2`." + arguments: ["op1: *{type}", "op2: *{type}"] + return_type: "svbool_t" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [whilerw] + compose: + - FnCall: + - "svwhilerw_{size}ptr" + - - $op1 + - $op2 + - - Type: "{type}" + + - name: svwhilewr_{size}ptr + attr: [*sve-unstable] + safety: + unsafe: [] + visibility: private + static_defs: [T] + substitutions: + size_alt: + match_size: "{type}" + byte: b + halfword: h + default: s + doubleword: d + arguments: ["op1: *T", "op2: *T"] + return_type: "{predicate}" + types: [i8, i16, i32, i64] + assert_instr: [] + compose: + - Let: [op1, CastAs: [$op1, "*const crate::ffi::c_void"]] + - Let: [op2, CastAs: [$op2, "*const crate::ffi::c_void"]] + - LLVMLink: + name: "whilewr.{size_alt}.{predicate}.p0" + arguments: ["op1: *crate::ffi::c_void", "op2: *crate::ffi::c_void"] + + - name: svwhilewr[_{type}] + attr: [*sve-unstable] + doc: While free of write-after-read conflicts + # TODO: This might be safe even with unrelated pointers, but the LLVM builtin's guarantees don't + # seem to be documented, so we conservatively keep this unsafe for now. + safety: + unsafe: + - custom: "[`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints + must be met for at least the base pointers, `op1` and `op2`." + arguments: ["op1: *{type}", "op2: *{type}"] + return_type: "svbool_t" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [whilewr] + compose: + - FnCall: + - "svwhilewr_{size}ptr" + - - $op1 + - $op2 + - - Type: "{type}" + + - name: svtbl2[_{type[0]}] + attr: [*sve-unstable] + doc: Table lookup in two-vector table + arguments: ["data: {sve_type_x2[0]}", "indices: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [f32, u32] + - [f64, u64] + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + - [u8, u8] + - [u16, u16] + - [u32, u32] + - [u64, u64] + assert_instr: [tbl] + compose: + - LLVMLink: + name: "tbl2.{sve_type[0]}" + arguments: + - "data0: {sve_type[0]}" + - "data1: {sve_type[0]}" + - "indices: {sve_type[1]}" + - FnCall: + - "{llvm_link}" + - - FnCall: ["svget2_{type[0]}", ["$data"], [0]] + - FnCall: ["svget2_{type[0]}", ["$data"], [1]] + - $indices + + - name: svtbx[_{type[0]}] + attr: [*sve-unstable] + doc: Table lookup in single-vector table (merging) + arguments: + - "fallback: {sve_type[0]}" + - "data: {sve_type[0]}" + - "indices: {sve_type[1]}" + return_type: "{sve_type[0]}" + types: + - [f32, u32] + - [f64, u64] + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + - [u8, u8] + - [u16, u16] + - [u32, u32] + - [u64, u64] + assert_instr: [tbx] + compose: + - LLVMLink: { name: "tbx.{sve_type[0]}" } + + - name: svcvtlt_{type[0]}[_{type[1]}]_m + attr: [*sve-unstable] + doc: Up convert long (top) + arguments: + ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f64, f32]] + assert_instr: [fcvtlt] + compose: + - LLVMLink: { name: "fcvtlt.{type[0]}{type[1]}" } + + - name: svcvtlt_{type[0]}[_{type[1]}]_x + attr: [*sve-unstable] + doc: Up convert long (top) + arguments: ["pg: svbool_t", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f64, f32]] + assert_instr: [fcvtlt] + compose: + - FnCall: + - "svcvtlt_{type[0]}_{type[1]}_m" + - - FnCall: ["crate::intrinsics::transmute_unchecked", [$op], [], true] + - $pg + - $op + + - name: svcvtnt_{type[0]}[_{type[1]}]{_mx} + attr: [*sve-unstable] + doc: Down convert and narrow (top) + arguments: + ["even: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f32, f64]] + assert_instr: [fcvtnt] + compose: + - LLVMLink: { name: "fcvtnt.{type[0]}{type[1]}" } + + - name: svcvtx_{type[0]}[_{type[1]}]{_mxz} + attr: [*sve-unstable] + doc: Down convert, rounding to odd + arguments: + ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f32, f64]] + zeroing_method: { drop: inactive } + assert_instr: [fcvtx] + compose: + - LLVMLink: { name: "fcvtx.{type[0]}{type[1]}" } + + - name: svcvtxnt_{type[0]}[_{type[1]}]{_mx} + attr: [*sve-unstable] + doc: Down convert, rounding to odd (top) + arguments: + ["even: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f32, f64]] + assert_instr: [fcvtxnt] + compose: + - LLVMLink: { name: "fcvtxnt.{type[0]}{type[1]}" } + + - name: svldnt1_gather_[{type[0]}]index[_{type[1]}] + attr: [*sve-unstable] + doc: Unextended load, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + ["pg: {predicate[0]}", "base: *{type[1]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["ldnt1{size_literal[0]}"] + test: { load: 1 } + compose: + - LLVMLink: { name: "ldnt1.gather.index.{sve_type[1]}" } + + - name: svldnt1_gather_[{type[0]}]offset[_{type[1]}] + attr: [*sve-unstable] + doc: Unextended load, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + ["pg: {predicate[0]}", "base: *{type[1]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["ldnt1{size_literal[0]}"] + test: { load: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: { name: "ldnt1.gather.uxtw.{sve_type[1]}" } + doubleword: + LLVMLink: { name: "ldnt1.gather.{sve_type[1]}" } + + - name: svldnt1_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Unextended load, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ldnt1{size_literal[0]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ldnt1.gather.scalar.offset.{sve_type[1]}.{sve_type[0]}" + + - name: svldnt1_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Unextended load, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ldnt1{size_literal[0]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldnt1_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svldnt1_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Unextended load, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ldnt1{size_literal[0]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldnt1_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[0]}"]] + + - name: svldnt1s{size_literal[2]}_gather_[{type[0]}]index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i64, u64], [i64, u64], [i16, i32]] + assert_instr: ["ldnt1s{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ldnt1.gather.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base, $indices]] + + - name: svldnt1u{size_literal[2]}_gather_[{type[0]}]index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i64, u64], [u64, i64], [u16, u32]] + assert_instr: ["ldnt1{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ldnt1.gather.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base, $indices]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svldnt1s{size_literal[2]}_gather_[{type[0]}]offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [[i64, u64], [i64, u64], [i8, i16, i32]] + assert_instr: ["ldnt1s{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldnt1.gather.uxtw.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ldnt1.gather.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]] + + - name: svldnt1u{size_literal[2]}_gather_[{type[0]}]offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [u32, i32], [u8, u16]] + - [[i64, u64], [u64, i64], [u8, u16, u32]] + assert_instr: ["ldnt1{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldnt1.gather.uxtw.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ldnt1.gather.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svldnt1s{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["ldnt1s{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ldnt1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]] + + - name: svldnt1u{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [u32, i32], [u8, u16]] + - [u64, [u64, i64], [u8, u16, u32]] + assert_instr: ["ldnt1{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ldnt1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svldnt1s{size_literal[2]}_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["ldnt1s{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldnt1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svldnt1u{size_literal[2]}_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [u8, u16]] + - [u64, [i64, u64], [u8, u16, u32]] + assert_instr: ["ldnt1{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldnt1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svldnt1s{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], u16] + - [u64, [i64, u64], [u16, u32]] + assert_instr: ["ldnt1s{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldnt1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + + - name: svldnt1u{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], u16] + - [u64, [i64, u64], [u16, u32]] + assert_instr: ["ldnt1{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldnt1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + + - name: svstnt1_scatter_[{type[0]}]index[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "indices: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["stnt1{size_literal[0]}"] + test: { store: 1 } + compose: + - LLVMLink: + name: "stnt1.scatter.index.{sve_type[1]}" + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "indices: {sve_type[0]}" + - FnCall: ["{llvm_link}", [$data, $pg, $base, $indices]] + + - name: svstnt1_scatter_[{type[0]}]offset[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "offsets: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["stnt1{size_literal[0]}"] + test: { store: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "stnt1.scatter.uxtw.{sve_type[1]}" + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "offsets: {sve_type[0]}" + doubleword: + LLVMLink: + name: "stnt1.scatter.{sve_type[1]}" + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "offsets: {sve_type[0]}" + - FnCall: ["{llvm_link}", [$data, $pg, $base, $offsets]] + + - name: svstnt1_scatter[_{type[0]}base]_offset[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + - "data: {sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["stnt1{size_literal[0]}"] + test: { store: 1 } + compose: + - LLVMLink: + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + name: "stnt1.scatter.scalar.offset.{sve_type[1]}.{sve_type[0]}" + - FnCall: ["{llvm_link}", [$data, $pg, $bases, $offset]] + + - name: svstnt1_scatter[_{type[0]}base_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: + ["pg: {predicate[0]}", "bases: {sve_type[0]}", "data: {sve_type[1]}"] + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["stnt1{size_literal[0]}"] + test: { store: 1 } + compose: + - FnCall: + - "svstnt1_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + - $data + + - name: svstnt1_scatter[_{type[0]}base]_index[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "index: i64" + - "data: {sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["stnt1{size_literal[0]}"] + test: { store: 1 } + compose: + - FnCall: + - "svstnt1_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[0]}"]] + - $data + + - name: svstnt1{size_literal[2]}_scatter_[{type[0]}]index[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "indices: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [[i64, u64], i64, [i16, i32]] + - [[i64, u64], u64, [u16, u32]] + assert_instr: ["stnt1{size_literal[2]}"] + test: { store: 2 } + compose: + - LLVMLink: + name: "stnt1.scatter.index.{sve_type[1] as {type[2]}}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "indices: {sve_type[0]}" + - FnCall: + - "{llvm_link}" + - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $base, $indices] + + - name: svstnt1{size_literal[2]}_scatter_[{type[0]}]offset[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "offsets: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [u32, i32, [i8, i16]] + - [u32, u32, [u8, u16]] + - [[i64, u64], i64, [i8, i16, i32]] + - [[i64, u64], u64, [u8, u16, u32]] + assert_instr: ["stnt1{size_literal[2]}"] + test: { store: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "stnt1.scatter.uxtw.{sve_type[1] as {type[2]}}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "offsets: {sve_type[0]}" + doubleword: + LLVMLink: + name: "stnt1.scatter.{sve_type[1] as {type[2]}}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "offsets: {sve_type[0]}" + - FnCall: + - "{llvm_link}" + - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $base, $offsets] + + - name: svstnt1{size_literal[2]}_scatter[_{type[0]}base]_offset[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + - "data: {sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["stnt1{size_literal[2]}"] + test: { store: 2 } + compose: + - LLVMLink: + name: "stnt1.scatter.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + - FnCall: + - "{llvm_link}" + - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $bases, $offset] + + - name: svstnt1{size_literal[2]}_scatter[_{type[0]}base_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: + ["pg: {predicate[0]}", "bases: {sve_type[0]}", "data: {sve_type[1]}"] + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["stnt1{size_literal[2]}"] + test: { store: 2 } + compose: + - FnCall: + - "svstnt1{size_literal[2]}_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + - $data + + - name: svstnt1{size_literal[2]}_scatter[_{type[0]}base]_index[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "index: i64" + - "data: {sve_type[1]}" + types: + - [u32, [i32, u32], i16] + - [u64, [i64, u64], [i16, i32]] + assert_instr: ["stnt1{size_literal[2]}"] + test: { store: 2 } + compose: + - FnCall: + - "svstnt1{size_literal[2]}_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + - $data + + - name: svaba[{_n}_{type}] + attr: [*sve-unstable] + doc: Absolute difference and accumulate + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind}aba"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind}aba.{sve_type}" } + + - name: svqabs[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Saturating absolute value + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + assert_instr: [sqabs] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "sqabs.{sve_type}" } + + - name: svabdlb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Absolute difference long (bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}abdlb"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}abdlb.{sve_type[0]}" } + + - name: svabdlt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Absolute difference long (top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}abdlt"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}abdlt.{sve_type[0]}" } + + - name: svabalb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Absolute difference long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}abalb"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind[0].su}abalb.{sve_type[0]}" } + + - name: svabalt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Absolute difference long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}abalt"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind[0].su}abalt.{sve_type[0]}" } + + - name: svbcax[{_n}_{type}] + attr: [*sve-unstable] + doc: Bitwise clear and exclusive OR + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [bcax] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op3 + compose: + - LLVMLink: { name: "bcax.{sve_type}" } + + - name: sveorbt[{_n}_{type}] + attr: [*sve-unstable] + doc: Interleaving exclusive OR (bottom, top) + arguments: ["odd: {sve_type}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [eorbt] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op2 + compose: + - LLVMLink: { name: "eorbt.{sve_type}" } + + - name: sveortb[{_n}_{type}] + attr: [*sve-unstable] + doc: Interleaving exclusive OR (top, bottom) + arguments: ["even: {sve_type}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [eortb] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op2 + compose: + - LLVMLink: { name: "eortb.{sve_type}" } + + - name: sveor3[{_n}_{type}] + attr: [*sve-unstable] + doc: Bitwise exclusive OR of three vectors + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [eor3] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op3 + compose: + - LLVMLink: { name: "eor3.{sve_type}" } + + - name: svbsl[{_n}_{type}] + attr: [*sve-unstable] + doc: Bitwise select + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [bsl] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op3 + compose: + - LLVMLink: { name: "bsl.{sve_type}" } + + - name: svbsl1n[{_n}_{type}] + attr: [*sve-unstable] + doc: Bitwise select with first input inverted + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [bsl1n] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op3 + compose: + - LLVMLink: { name: "bsl1n.{sve_type}" } + + - name: svbsl2n[{_n}_{type}] + attr: [*sve-unstable] + doc: Bitwise select with second input inverted + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [bsl2n] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op3 + compose: + - LLVMLink: { name: "bsl2n.{sve_type}" } + + - name: svnbsl[{_n}_{type}] + attr: [*sve-unstable] + doc: Bitwise select + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [nbsl] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op3 + compose: + - LLVMLink: { name: "nbsl.{sve_type}" } + + - name: svxar[_n_{type}] + attr: [*sve-unstable] + doc: Bitwise exclusive OR and rotate right + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM3: i32"] + constraints: [{ variable: IMM3, range: ["1", "{size}"] }] + assert_instr: [[xar, "IMM3 = 1"]] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + compose: + - LLVMLink: + name: "xar.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]] + + - name: svrax1[_{type}] + attr: [*sve-unstable] + doc: Bitwise rotate left by 1 and exclusive OR + target_features: [sve2-sha3] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [rax1] + types: [i64, u64] + compose: + - LLVMLink: { name: "rax1" } + + - name: svshllb[_n_{type[0]}] + attr: [*sve-unstable] + doc: Shift left long (bottom) + arguments: ["op1: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["0", "{size_minus_one[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [["{type_kind[0].su}shllb", "IMM2 = 0"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}shllb.{sve_type[0]}" + arguments: ["op1: {sve_type[1]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svshllt[_n_{type[0]}] + attr: [*sve-unstable] + doc: Shift left long (top) + arguments: ["op1: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["0", "{size_minus_one[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [["{type_kind[0].su}shllt", "IMM2 = 0"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}shllt.{sve_type[0]}" + arguments: ["op1: {sve_type[1]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svrshl[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Rounding shift left + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i8, u8], i8] + - [[i16, u16], i16] + - [[i32, u32], i32] + - [[i64, u64], i64] + assert_instr: ["{type_kind[0].su}rshl"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}rshl.{sve_type[0]}" } + + - name: svqrshl[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Saturating rounding shift left + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i8, u8], i8] + - [[i16, u16], i16] + - [[i32, u32], i32] + - [[i64, u64], i64] + assert_instr: ["{type_kind[0].su}qrshl"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}qrshl.{sve_type[0]}" } + + - name: svqshl[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Saturating shift left + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i8, u8], i8] + - [[i16, u16], i16] + - [[i32, u32], i32] + - [[i64, u64], i64] + assert_instr: ["{type_kind[0].su}qshl"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}qshl.{sve_type[0]}" } + + - name: svqshlu[_n_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Saturating shift left unsigned + arguments: ["pg: {predicate[0]}", "op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["0", "{size_minus_one[1]}"] }] + types: + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + assert_instr: [[sqshlu, "IMM2 = 0"]] + zeroing_method: { select: op1 } + compose: + - LLVMLink: + name: "sqshlu.{sve_type[0]}" + arguments: ["pg: {predicate[0]}", "op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$pg, $op1, $IMM2]] + + - name: svsli[_n_{type}] + attr: [*sve-unstable] + doc: Shift left and insert + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM3: i32"] + constraints: [{ variable: IMM3, range: ["0", "{size_minus_one}"] }] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [[sli, "IMM3 = 0"]] + compose: + - LLVMLink: + name: "sli.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]] + + - name: svrshr[_n_{type}]{_mxz} + attr: [*sve-unstable] + doc: Rounding shift right + arguments: ["pg: {predicate}", "op1: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size}"] }] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [["{type_kind.su}rshr", "IMM2 = 1"]] + zeroing_method: { select: op1 } + compose: + - LLVMLink: + name: "{type_kind.su}rshr.{sve_type}" + arguments: ["pg: {predicate}", "op1: {sve_type}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$pg, $op1, $IMM2]] + + - name: svrsra[_n_{type}] + attr: [*sve-unstable] + doc: Rounding shift right and accumulate + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM3: i32"] + constraints: [{ variable: IMM3, range: ["1", "{size}"] }] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [["{type_kind.su}rsra", "IMM3 = 1"]] + compose: + - LLVMLink: + name: "{type_kind.su}rsra.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]] + + - name: svrshrnb[_n_{type[0]}] + attr: [*sve-unstable] + doc: Rounding shift right narrow (bottom) + arguments: ["op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [[rshrnb, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "rshrnb.{sve_type[0]}" + arguments: ["op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svrshrnt[_n_{type[0]}] + attr: [*sve-unstable] + doc: Rounding shift right narrow (top) + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [[rshrnt, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "rshrnt.{sve_type[0]}" + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]] + + - name: svqrshrnb[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating rounding shift right narrow (bottom) + arguments: ["op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [["{type_kind[0].su}qrshrnb", "IMM2 = 1"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}qrshrnb.{sve_type[0]}" + arguments: ["op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svqrshrnt[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating rounding shift right narrow (top) + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [["{type_kind[0].su}qrshrnt", "IMM2 = 1"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}qrshrnt.{sve_type[0]}" + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]] + + - name: svqrshrunb[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating rounding shift right unsigned narrow (bottom) + arguments: ["op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, u8] + - [i32, u16] + - [i64, u32] + assert_instr: [[sqrshrunb, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "sqrshrunb.{sve_type[0]}" + arguments: ["op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svqrshrunt[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating rounding shift right unsigned narrow (top) + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, u8] + - [i32, u16] + - [i64, u32] + assert_instr: [[sqrshrunt, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "sqrshrunt.{sve_type[0]}" + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]] + + - name: svqshrnb[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating shift right narrow (bottom) + arguments: ["op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [["{type_kind[0].su}qshrnb", "IMM2 = 1"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}qshrnb.{sve_type[0]}" + arguments: ["op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svqshrnt[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating shift right narrow (top) + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [["{type_kind[0].su}qshrnt", "IMM2 = 1"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}qshrnt.{sve_type[0]}" + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]] + + - name: svqshrunb[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating shift right unsigned narrow (bottom) + arguments: ["op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, u8] + - [i32, u16] + - [i64, u32] + assert_instr: [[sqshrunb, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "sqshrunb.{sve_type[0]}" + arguments: ["op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svqshrunt[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating shift right unsigned narrow (top) + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, u8] + - [i32, u16] + - [i64, u32] + assert_instr: [[sqshrunt, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "sqshrunt.{sve_type[0]}" + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]] + + - name: svsra[_n_{type}] + attr: [*sve-unstable] + doc: Shift right and accumulate + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM3: i32"] + constraints: [{ variable: IMM3, range: ["1", "{size}"] }] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [["{type_kind.su}sra", "IMM3 = 1"]] + compose: + - LLVMLink: + name: "{type_kind.su}sra.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]] + + - name: svsri[_n_{type}] + attr: [*sve-unstable] + doc: Shift right and insert + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM3: i32"] + constraints: [{ variable: IMM3, range: ["1", "{size}"] }] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [[sri, "IMM3 = 1"]] + compose: + - LLVMLink: + name: "sri.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]] + + - name: svshrnb[_n_{type[0]}] + attr: [*sve-unstable] + doc: Shift right narrow (bottom) + arguments: ["op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [[shrnb, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "shrnb.{sve_type[0]}" + arguments: ["op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svshrnt[_n_{type[0]}] + attr: [*sve-unstable] + doc: Shift right narrow (top) + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [[shrnt, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "shrnt.{sve_type[0]}" + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]] + + - name: svqxtnb[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating extract narrow (bottom) + arguments: ["op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}qxtnb"] + compose: + - LLVMLink: { name: "{type_kind[0].su}qxtnb.{sve_type[0]}" } + + - name: svqxtnt[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating extract narrow (top) + arguments: ["even: {sve_type[1]}", "op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}qxtnt"] + compose: + - LLVMLink: { name: "{type_kind[0].su}qxtnt.{sve_type[0]}" } + + - name: svqxtunb[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating extract unsigned narrow (bottom) + arguments: ["op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, u8] + - [i32, u16] + - [i64, u32] + assert_instr: [sqxtunb] + compose: + - LLVMLink: { name: "sqxtunb.{sve_type[0]}" } + + - name: svqxtunt[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating extract unsigned narrow (top) + arguments: ["even: {sve_type[1]}", "op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, u8] + - [i32, u16] + - [i64, u32] + assert_instr: [sqxtunt] + compose: + - LLVMLink: { name: "sqxtunt.{sve_type[0]}" } + + - name: svmovlb[_{type[0]}] + attr: [*sve-unstable] + doc: Move long (bottom) + arguments: ["op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}shllb"] + compose: + - FnCall: ["svshllb_n_{type[0]}", [$op], [0]] + + - name: svmovlt[_{type[0]}] + attr: [*sve-unstable] + doc: Move long (top) + arguments: ["op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}shllt"] + compose: + - FnCall: ["svshllt_n_{type[0]}", [$op], [0]] + + - name: svunpkhi[_{type[0]}] + attr: [*sve-unstable] + doc: Unpack and extend high half + arguments: ["op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}unpkhi"] + compose: + - LLVMLink: { name: "{type_kind[0].su}unpkhi.{sve_type[0]}" } + + - name: svunpkhi[_b] + attr: [*sve-unstable] + doc: Unpack and extend high half + arguments: ["op: svbool_t"] + return_type: "svbool8_t" + assert_instr: [punpkhi] + compose: + - LLVMLink: { name: "punpkhi.nxv16i1" } + + - name: svunpklo[_{type[0]}] + attr: [*sve-unstable] + doc: Unpack and extend low half + arguments: ["op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}unpklo"] + compose: + - LLVMLink: { name: "{type_kind[0].su}unpklo.{sve_type[0]}" } + + - name: svunpklo[_b] + attr: [*sve-unstable] + doc: Unpack and extend low half + arguments: ["op: svbool_t"] + return_type: "svbool8_t" + assert_instr: [punpklo] + compose: + - LLVMLink: { name: "punpklo.nxv16i1" } + + - name: svaddp[_{type}]{_mx} + attr: [*sve-unstable] + doc: Add pairwise + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.f}addp"] + compose: + - LLVMLink: { name: "{type_kind.f}addp.{sve_type}" } + + - name: svadalp[_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Add and accumulate long pairwise + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}adalp"] + zeroing_method: { select: op1 } + compose: + - LLVMLink: { name: "{type_kind[0].su}adalp.{sve_type[0]}" } + + - name: svmaxp[_{type}]{_mx} + attr: [*sve-unstable] + doc: Maximum pairwise + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.fsu}maxp"] + compose: + - LLVMLink: { name: "{type_kind.fsu}maxp.{sve_type}" } + + - name: svmaxnmp[_{type}]{_mx} + attr: [*sve-unstable] + doc: Maximum number pairwise + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: ["fmaxnmp"] + compose: + - LLVMLink: { name: "fmaxnmp.{sve_type}" } + + - name: svminp[_{type}]{_mx} + attr: [*sve-unstable] + doc: Minimum pairwise + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.fsu}minp"] + compose: + - LLVMLink: { name: "{type_kind.fsu}minp.{sve_type}" } + + - name: svminnmp[_{type}]{_mx} + attr: [*sve-unstable] + doc: Minimum number pairwise + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: ["fminnmp"] + compose: + - LLVMLink: { name: "fminnmp.{sve_type}" } + + - name: svmul_lane[_{type}] + attr: [*sve-unstable] + doc: Multiply + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + assert_instr: [["{type_kind.f}mul", "IMM_INDEX = 0"]] + types: [f32, f64, i16, i32, i64, u16, u32, u64] + compose: + - LLVMLink: + name: "{type_kind.f}mul.lane.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm_index: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, IMM_INDEX]] + + - name: svqdmulh[{_n}_{type}] + attr: [*sve-unstable] + doc: Saturating doubling multiply high + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + assert_instr: [sqdmulh] + n_variant_op: op2 + compose: + - LLVMLink: { name: "sqdmulh.{sve_type}" } + + - name: svqdmulh_lane[_{type}] + attr: [*sve-unstable] + doc: Saturating doubling multiply high + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + assert_instr: [["sqdmulh", "IMM_INDEX = 0"]] + types: [i16, i32, i64] + compose: + - LLVMLink: + name: "sqdmulh.lane.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm_index: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, IMM_INDEX]] + + - name: svqrdmulh[{_n}_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling multiply high + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + assert_instr: [sqrdmulh] + n_variant_op: op2 + compose: + - LLVMLink: { name: "sqrdmulh.{sve_type}" } + + - name: svqrdmulh_lane[_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling multiply high + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + assert_instr: [["sqrdmulh", "IMM_INDEX = 0"]] + types: [i16, i32, i64] + compose: + - LLVMLink: + name: "sqrdmulh.lane.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm_index: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, IMM_INDEX]] + + - name: svqdmullb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply long (bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: [sqdmullb] + n_variant_op: op2 + compose: + - LLVMLink: { name: "sqdmullb.{sve_type[0]}" } + + - name: svqdmullb_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply long (bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + assert_instr: [["sqdmullb", "IMM_INDEX = 0"]] + types: [[i32, i16], [i64, i32]] + compose: + - LLVMLink: + name: "sqdmullb.lane.{sve_type[0]}" + arguments: + ["op1: {sve_type[1]}", "op2: {sve_type[1]}", "imm_index: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, IMM_INDEX]] + + - name: svqdmullt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply long (top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: [sqdmullt] + n_variant_op: op2 + compose: + - LLVMLink: { name: "sqdmullt.{sve_type[0]}" } + + - name: svqdmullt_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply long (top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + assert_instr: [["sqdmullt", "IMM_INDEX = 0"]] + types: [[i32, i16], [i64, i32]] + compose: + - LLVMLink: + name: "sqdmullt.lane.{sve_type[0]}" + arguments: + ["op1: {sve_type[1]}", "op2: {sve_type[1]}", "imm_index: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, IMM_INDEX]] + + - name: svmullb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Multiply long (bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}mullb"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}mullb.{sve_type[0]}" } + + - name: svmullb_lane[_{type[0]}] + attr: + - *sve-unstable + # FIXME(arm-maintainers): MSVC disassembly of `[su]mullb` fails + - FnCall: [cfg_attr, [*msvc-disabled, {FnCall: [assert_instr, ["{type_kind[0].su}mullb", "IMM_INDEX = 0"]]}]] + doc: Multiply long (bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i32, i16] + - [i64, i32] + - [u32, u16] + - [u64, u32] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + compose: + - LLVMLink: + name: "{type_kind[0].su}mullb.lane.{sve_type[0]}" + arguments: + ["op1: {sve_type[1]}", "op2: {sve_type[1]}", "imm_index: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM_INDEX]] + + - name: svmullt[{_n}_{type[0]}] + attr: + - *sve-unstable + # FIXME(arm-maintainers): MSVC disassembly of `[su]mullt` fails + - FnCall: [cfg_attr, [*msvc-disabled, {FnCall: [assert_instr, ["{type_kind[0].su}mullt"]]}]] + doc: Multiply long (top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}mullt.{sve_type[0]}" } + + - name: svmullt_lane[_{type[0]}] + attr: + - *sve-unstable + # FIXME(arm-maintainers): MSVC disassembly of `[su]mullt` fails + - FnCall: [cfg_attr, [*msvc-disabled, {FnCall: [assert_instr, ["{type_kind[0].su}mullt", "IMM_INDEX = 0"]]}]] + doc: Multiply long (top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i32, i16] + - [i64, i32] + - [u32, u16] + - [u64, u32] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + compose: + - LLVMLink: + name: "{type_kind[0].su}mullt.lane.{sve_type[0]}" + arguments: + ["op1: {sve_type[1]}", "op2: {sve_type[1]}", "imm_index: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM_INDEX]] + + - name: svrecpe[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Reciprocal estimate + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [u32] + assert_instr: [urecpe] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "urecpe.{sve_type}" } + + - name: svrsqrte[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Reciprocal square root estimate + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [u32] + assert_instr: [ursqrte] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "ursqrte.{sve_type}" } + + - name: svmla_lane[_{type}] + attr: [*sve-unstable] + doc: Multiply-add, addend first + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + types: [i16, i32, i64, u16, u32, u64] + assert_instr: [[mla, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "mla.lane.{sve_type}" + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svmls_lane[_{type}] + attr: [*sve-unstable] + doc: Multiply-subtract, minuend first + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + types: [i16, i32, i64, u16, u32, u64] + assert_instr: [[mls, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "mls.lane.{sve_type}" + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svmlalb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-add long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + assert_instr: ["{type_kind[0].su}mlalb"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind[0].su}mlalb.{sve_type[0]}" } + + - name: svmlalb_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-add long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32], [u32, u16], [u64, u32]] + assert_instr: [["{type_kind[0].su}mlalb", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}mlalb.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svmlalt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-add long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + assert_instr: ["{type_kind[0].su}mlalt"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind[0].su}mlalt.{sve_type[0]}" } + + - name: svmlalt_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-add long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32], [u32, u16], [u64, u32]] + assert_instr: [["{type_kind[0].su}mlalt", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}mlalt.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svmlslb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-subtract long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + assert_instr: ["{type_kind[0].su}mlslb"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind[0].su}mlslb.{sve_type[0]}" } + + - name: svmlslb_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-subtract long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32], [u32, u16], [u64, u32]] + assert_instr: [["{type_kind[0].su}mlslb", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}mlslb.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svmlslt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-subtract long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + assert_instr: ["{type_kind[0].su}mlslt"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind[0].su}mlslt.{sve_type[0]}" } + + - name: svmlslt_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-subtract long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32], [u32, u16], [u64, u32]] + assert_instr: [["{type_kind[0].su}mlslt", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}mlslt.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svqrdmlah[{_n}_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling multiply-add high + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + assert_instr: [sqrdmlah] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqrdmlah.{sve_type}" } + + - name: svqrdmlah_lane[_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling multiply-add high + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + types: [i16, i32, i64] + assert_instr: [[sqrdmlah, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "sqrdmlah.lane.{sve_type}" + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svqrdmlsh[{_n}_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling multiply-subtract high + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + assert_instr: [sqrdmlsh] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqrdmlsh.{sve_type}" } + + - name: svqrdmlsh_lane[_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling multiply-subtract high + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + types: [i16, i32, i64] + assert_instr: [[sqrdmlsh, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "sqrdmlsh.lane.{sve_type}" + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svqdmlalb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-add long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: ["sqdmlalb"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqdmlalb.{sve_type[0]}" } + + - name: svqdmlalb_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-add long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32]] + assert_instr: [["sqdmlalb", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "sqdmlalb.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svqdmlalbt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-add long (bottom × top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: ["sqdmlalbt"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqdmlalbt.{sve_type[0]}" } + + - name: svqdmlalt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-add long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: ["sqdmlalt"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqdmlalt.{sve_type[0]}" } + + - name: svqdmlalt_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-add long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32]] + assert_instr: [["sqdmlalt", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "sqdmlalt.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svqdmlslb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-subtract long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: ["sqdmlslb"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqdmlslb.{sve_type[0]}" } + + - name: svqdmlslb_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-subtract long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32]] + assert_instr: [["sqdmlslb", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "sqdmlslb.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svqdmlslbt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-subtract long (bottom × top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: ["sqdmlslbt"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqdmlslbt.{sve_type[0]}" } + + - name: svqdmlslt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-subtract long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: ["sqdmlslt"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqdmlslt.{sve_type[0]}" } + + - name: svqdmlslt_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-subtract long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32]] + assert_instr: [["sqdmlslt", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "sqdmlslt.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svqneg[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Saturating negate + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + assert_instr: [sqneg] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "sqneg.{sve_type}" } + + - name: svadclb[{_n}_{type}] + attr: [*sve-unstable] + doc: Add with carry long (bottom) + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [u32, u64] + assert_instr: [adclb] + n_variant_op: op3 + compose: + - LLVMLink: { name: "adclb.{sve_type}" } + + - name: svadclt[{_n}_{type}] + attr: [*sve-unstable] + doc: Add with carry long (top) + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [u32, u64] + assert_instr: [adclt] + n_variant_op: op3 + compose: + - LLVMLink: { name: "adclt.{sve_type}" } + + - name: svqadd[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Saturating add + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.su}qadd"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}qadd.{sve_type}" } + + - name: svsqadd[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Saturating add with signed addend + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [u8, i8] + - [u16, i16] + - [u32, i32] + - [u64, i64] + assert_instr: [usqadd] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "usqadd.{sve_type[0]}" } + + - name: svuqadd[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Saturating add with unsigned addend + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + assert_instr: [suqadd] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "suqadd.{sve_type[0]}" } + + - name: svaddlb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Add long (bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}addlb"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}addlb.{sve_type[0]}" } + + - name: svaddlbt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Add long (bottom + top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + assert_instr: ["{type_kind[0].su}addlbt"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}addlbt.{sve_type[0]}" } + + - name: svaddlt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Add long (top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}addlt"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}addlt.{sve_type[0]}" } + + - name: svaddwb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Add wide (bottom) + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}addwb"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}addwb.{sve_type[0]}" } + + - name: svaddwt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Add wide (top) + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}addwt"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}addwt.{sve_type[0]}" } + + - name: svlogb[_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Base 2 logarithm as integer + arguments: + ["inactive: {sve_type[1]}", "pg: {predicate[0]}", "op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: [[f32, i32], [f64, i64]] + assert_instr: [flogb] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "flogb.{sve_type[0]}" } + + - name: svpmul[{_n}_{type}] + attr: [*sve-unstable] + doc: Polynomial multiply + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8] + assert_instr: [pmul] + n_variant_op: op2 + compose: + - LLVMLink: { name: "pmul.{sve_type}" } + + - name: svpmullb_pair[{_n}_{type}] + attr: [*sve-unstable] + doc: Polynomial multiply long (bottom) + target_features: [sve2-aes] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8, u32, u64] + assert_instr: [pmullb] + n_variant_op: op2 + compose: + - LLVMLink: { name: "pmullb.pair.{sve_type}" } + + - name: svpmullb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Polynomial multiply long (bottom) + target_features: [sve2-aes] + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[u16, u8], [u64, u32]] + assert_instr: [pmullb] + n_variant_op: op2 + compose: + - FnCall: + - "crate::intrinsics::transmute_unchecked" + - [FnCall: ["svpmullb_pair_{type[1]}", [$op1, $op2]]] + - [] + - true + + - name: svpmullt_pair[{_n}_{type}] + attr: [*sve-unstable] + doc: Polynomial multiply long (top) + target_features: [sve2-aes] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8, u32, u64] + assert_instr: [pmullt] + n_variant_op: op2 + compose: + - LLVMLink: { name: "pmullt.pair.{sve_type}" } + + - name: svpmullt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Polynomial multiply long (top) + target_features: [sve2-aes] + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[u16, u8], [u64, u32]] + assert_instr: [pmullt] + n_variant_op: op2 + compose: + - FnCall: + - "crate::intrinsics::transmute_unchecked" + - [FnCall: ["svpmullt_pair_{type[1]}", [$op1, $op2]]] + - [] + - true + + - name: svaesd[_{type}] + attr: [*sve-unstable] + doc: AES single round decryption + target_features: [sve2-aes] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8] + assert_instr: [aesd] + compose: + - LLVMLink: { name: "aesd" } + + - name: svaese[_{type}] + attr: [*sve-unstable] + doc: AES single round encryption + target_features: [sve2-aes] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8] + assert_instr: [aese] + compose: + - LLVMLink: { name: "aese" } + + - name: svaesmc[_{type}] + attr: [*sve-unstable] + doc: AES mix columns + target_features: [sve2-aes] + arguments: ["op: {sve_type}"] + return_type: "{sve_type}" + types: [u8] + assert_instr: [aesmc] + compose: + - LLVMLink: { name: "aesmc" } + + - name: svaesimc[_{type}] + attr: [*sve-unstable] + doc: AES inverse mix columns + target_features: [sve2-aes] + arguments: ["op: {sve_type}"] + return_type: "{sve_type}" + types: [u8] + assert_instr: [aesimc] + compose: + - LLVMLink: { name: "aesimc" } + + - name: svsm4e[_{type}] + attr: [*sve-unstable] + doc: SM4 encryption and decryption + target_features: [sve2-sm4] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u32] + assert_instr: [sm4e] + compose: + - LLVMLink: { name: "sm4e" } + + - name: svsm4ekey[_{type}] + attr: [*sve-unstable] + doc: SM4 key updates + target_features: [sve2-sm4] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u32] + assert_instr: [sm4ekey] + compose: + - LLVMLink: { name: "sm4ekey" } diff --git a/library/stdarch/crates/stdarch-gen-arm/src/big_endian.rs b/library/stdarch/crates/stdarch-gen-arm/src/big_endian.rs index b982ff53ec3d2..f024ca074eac6 100644 --- a/library/stdarch/crates/stdarch-gen-arm/src/big_endian.rs +++ b/library/stdarch/crates/stdarch-gen-arm/src/big_endian.rs @@ -15,9 +15,9 @@ fn create_single_wild_string(name: &str) -> WildString { /// Creates an Identifier with name `name` with no wildcards. This, for example, /// can be used to create variables, function names or arbitrary input. Is is /// extremely flexible. -pub fn create_symbol_identifier(arbitrary_string: &str) -> Expression { +pub fn create_symbol_identifier(arbitrary_string: &str, kind: IdentifierType) -> Expression { let identifier_name = create_single_wild_string(arbitrary_string); - Expression::Identifier(identifier_name, IdentifierType::Symbol) + Expression::Identifier(identifier_name, kind) } /// To compose the simd_shuffle! call we need: @@ -101,7 +101,6 @@ pub fn make_variable_mutable(variable_name: &str, type_kind: &TypeKind) -> Expre fn create_shuffle_internal( variable_name: &String, type_kind: &TypeKind, - fmt_tuple: fn(variable_name: &String, idx: u32, array_lanes: &String) -> String, fmt: fn(variable_name: &String, type_kind: &TypeKind, array_lanes: &String) -> String, ) -> Option { let TypeKind::Vector(vector_type) = type_kind else { @@ -120,14 +119,21 @@ fn create_shuffle_internal( /* .idx = simd_shuffle!(.idx, .idx, []) */ for idx in 0..tuple_count { - let formatted = fmt_tuple(variable_name, idx, &array_lanes); + let formatted = + create_assigned_tuple_shuffle_call_fmt(variable_name, idx, &array_lanes); string_builder += formatted.as_str(); } - Some(create_symbol_identifier(&string_builder)) + Some(create_symbol_identifier( + &string_builder, + IdentifierType::UnsafeSymbol, + )) } else { /* Generate a list of shuffles for each tuple */ let expression = fmt(variable_name, type_kind, &array_lanes); - Some(create_symbol_identifier(&expression)) + Some(create_symbol_identifier( + &expression, + IdentifierType::UnsafeSymbol, + )) } } @@ -137,7 +143,7 @@ fn create_assigned_tuple_shuffle_call_fmt( array_lanes: &String, ) -> String { format!( - "{variable_name}.{idx} = unsafe {{ simd_shuffle!({variable_name}.{idx}, {variable_name}.{idx}, {array_lanes}) }};\n" + "{variable_name}.{idx} = simd_shuffle!({variable_name}.{idx}, {variable_name}.{idx}, {array_lanes});\n" ) } @@ -147,7 +153,7 @@ fn create_assigned_shuffle_call_fmt( array_lanes: &String, ) -> String { format!( - "let {variable_name}: {type_kind} = unsafe {{ simd_shuffle!({variable_name}, {variable_name}, {array_lanes}) }}" + "let {variable_name}: {type_kind} = simd_shuffle!({variable_name}, {variable_name}, {array_lanes})" ) } @@ -165,20 +171,10 @@ pub fn create_assigned_shuffle_call( variable_name: &String, type_kind: &TypeKind, ) -> Option { - create_shuffle_internal( - variable_name, - type_kind, - create_assigned_tuple_shuffle_call_fmt, - create_assigned_shuffle_call_fmt, - ) + create_shuffle_internal(variable_name, type_kind, create_assigned_shuffle_call_fmt) } /// Create a `simd_shuffle!(<...>, [...])` call pub fn create_shuffle_call(variable_name: &String, type_kind: &TypeKind) -> Option { - create_shuffle_internal( - variable_name, - type_kind, - create_assigned_tuple_shuffle_call_fmt, - create_shuffle_call_fmt, - ) + create_shuffle_internal(variable_name, type_kind, create_shuffle_call_fmt) } diff --git a/library/stdarch/crates/stdarch-gen-arm/src/context.rs b/library/stdarch/crates/stdarch-gen-arm/src/context.rs index 9b8eb8e8b9bfe..85342a1804854 100644 --- a/library/stdarch/crates/stdarch-gen-arm/src/context.rs +++ b/library/stdarch/crates/stdarch-gen-arm/src/context.rs @@ -43,6 +43,10 @@ pub struct GlobalContext { /// Should all LLVM wrappers convert their arguments to a signed type #[serde(default)] pub auto_llvm_sign_conversion: bool, + + /// Should SVE load/store tests be generated? + #[serde(default)] + pub generate_load_store_tests: bool, } /// Context of an intrinsic group @@ -218,7 +222,7 @@ impl LocalContext { } => Ok(Expression::MacroCall( "static_assert_range".to_string(), format!( - "{variable}, {min}, {max}", + "{variable}, {min}..={max}", min = range.start(), max = range.end() ), @@ -246,7 +250,7 @@ impl LocalContext { |bitsize| Ok(higher_limit / bitsize - 1))?; Ok(Expression::MacroCall( "static_assert_range".to_string(), - format!("{variable}, 0, {max}"), + format!("{variable}, 0..={max}"), )) } else { Err(format!( diff --git a/library/stdarch/crates/stdarch-gen-arm/src/expression.rs b/library/stdarch/crates/stdarch-gen-arm/src/expression.rs index bf48f0dab7498..daaf7ee6897bd 100644 --- a/library/stdarch/crates/stdarch-gen-arm/src/expression.rs +++ b/library/stdarch/crates/stdarch-gen-arm/src/expression.rs @@ -23,6 +23,7 @@ use crate::{ pub enum IdentifierType { Variable, Symbol, + UnsafeSymbol, } #[derive(Debug, Clone, Serialize, Deserialize)] @@ -65,7 +66,11 @@ impl FnCall { } pub fn is_expected_call(&self, fn_call_name: &str) -> bool { - if let Expression::Identifier(fn_name, IdentifierType::Symbol) = self.0.as_ref() { + if let Expression::Identifier( + fn_name, + IdentifierType::Symbol | IdentifierType::UnsafeSymbol, + ) = self.0.as_ref() + { fn_name.to_string() == fn_call_name } else { false @@ -143,8 +148,6 @@ pub enum Expression { LLVMLink(LLVMLink), /// Casts the given expression to the specified (unchecked) type CastAs(Box, String), - /// Returns the LLVM `undef` symbol - SvUndef, /// Multiplication Multiply(Box, Box), /// Xor @@ -295,18 +298,20 @@ impl Expression { /// - An unnecessary `unsafe` is a warning, made into an error by the CI's `-D warnings`. /// /// This **panics** if it encounters an expression that shouldn't appear in a safe function at - /// all (such as `SvUndef`). + /// all. pub fn requires_unsafe_wrapper(&self, ctx_fn: &str) -> bool { match self { // The call will need to be unsafe, but the declaration does not. Self::LLVMLink(..) => false, - // Identifiers, literals and type names are never unsafe. - Self::Identifier(..) => false, + // literals and type names are never unsafe. Self::IntConstant(..) => false, Self::FloatConstant(..) => false, Self::BoolConstant(..) => false, Self::Type(..) => false, Self::ConvertConst(..) => false, + // Only unsafe `Symbol` identifiers are unsafe + Self::Identifier(_, IdentifierType::UnsafeSymbol) => true, + Self::Identifier(..) => false, // Nested structures that aren't inherently unsafe, but could contain other expressions // that might be. Self::Assign(_var, exp) => exp.requires_unsafe_wrapper(ctx_fn), @@ -347,9 +352,6 @@ impl Expression { }, // We only use macros to check const generics (using static assertions). Self::MacroCall(_name, _args) => false, - // Materialising uninitialised values is always unsafe, and we avoid it in safe - // functions. - Self::SvUndef => panic!("Refusing to wrap unsafe SvUndef in safe function '{ctx_fn}'."), // Variants that aren't tokenised. We shouldn't encounter these here. Self::MatchKind(..) => { unimplemented!("The unsafety of {self:?} cannot be determined in '{ctx_fn}'.") @@ -390,9 +392,7 @@ impl FromStr for Expression { static MACRO_RE: LazyLock = LazyLock::new(|| Regex::new(r"^(?P[\w\d_]+)!\((?P.*?)\);?$").unwrap()); - if s == "SvUndef" { - Ok(Expression::SvUndef) - } else if MACRO_RE.is_match(s) { + if MACRO_RE.is_match(s) { let c = MACRO_RE.captures(s).unwrap(); let ex = c["ex"].to_string(); let _: TokenStream = ex @@ -533,7 +533,6 @@ impl ToTokens for Expression { let ty: TokenStream = ty.parse().expect("invalid syntax"); tokens.append_all(quote! { #ex as #ty }) } - Self::SvUndef => tokens.append_all(quote! { simd_reinterpret(()) }), Self::Multiply(lhs, rhs) => tokens.append_all(quote! { #lhs * #rhs }), Self::Xor(lhs, rhs) => tokens.append_all(quote! { #lhs ^ #rhs }), Self::Type(ty) => ty.to_tokens(tokens), diff --git a/library/stdarch/crates/stdarch-gen-arm/src/fn_suffix.rs b/library/stdarch/crates/stdarch-gen-arm/src/fn_suffix.rs index 26c156ae178aa..6fba3dc74476e 100644 --- a/library/stdarch/crates/stdarch-gen-arm/src/fn_suffix.rs +++ b/library/stdarch/crates/stdarch-gen-arm/src/fn_suffix.rs @@ -188,7 +188,7 @@ impl FromStr for SuffixKind { "rot90_lane" => Ok(SuffixKind::Rot90Lane), "rot90_laneq" => Ok(SuffixKind::Rot90LaneQ), "rot180" => Ok(SuffixKind::Rot180), - "rot180_lane" => Ok(SuffixKind::Rot180LaneQ), + "rot180_lane" => Ok(SuffixKind::Rot180Lane), "rot180_laneq" => Ok(SuffixKind::Rot180LaneQ), "u" => Ok(SuffixKind::Unsigned), "nox" => Ok(SuffixKind::NoX), diff --git a/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs b/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs index ce427d54b3552..5359bd4df3211 100644 --- a/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs +++ b/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs @@ -550,7 +550,7 @@ impl LLVMLink { /// Alters all the unsigned types from the signature. This is required where /// a signed and unsigned variant require the same binding to an exposed - /// LLVM instrinsic. + /// LLVM intrinsic. pub fn sanitise_uints(&mut self) { let transform = |tk: &mut TypeKind| { if let Some(BaseType::Sized(BaseTypeKind::UInt, size)) = tk.base_type() { @@ -630,7 +630,7 @@ impl LLVMLink { match (scope, kind.base_type()) { (Argument, Some(Sized(Bool, bitsize))) if *bitsize != 8 => { - Ok(convert("into", arg)) + Ok(convert("sve_into", arg)) } (Argument, Some(Sized(UInt, _) | Unsized(UInt))) => { if ctx.global.auto_llvm_sign_conversion { @@ -647,27 +647,26 @@ impl LLVMLink { }) .try_collect()?; - let return_type_conversion = if !ctx.global.auto_llvm_sign_conversion { - None - } else { - self.signature - .as_ref() - .and_then(|sig| sig.return_type.as_ref()) - .and_then(|ty| { - if let Some(Sized(Bool, bitsize)) = ty.base_type() { - (*bitsize != 8).then_some(Bool) - } else if let Some(Sized(UInt, _) | Unsized(UInt)) = ty.base_type() { - Some(UInt) - } else { - None - } - }) - }; + let return_type_conversion = self + .signature + .as_ref() + .and_then(|sig| sig.return_type.as_ref()) + .and_then(|ty| { + if let Some(Sized(Bool, bitsize)) = ty.base_type() { + (*bitsize != 8).then_some(Bool) + } else if let Some(Sized(UInt, _) | Unsized(UInt)) = ty.base_type() { + Some(UInt) + } else { + None + } + }); let fn_call = Expression::FnCall(fn_call); match return_type_conversion { - Some(Bool) => Ok(convert("into", fn_call)), - Some(UInt) => Ok(convert("as_unsigned", fn_call)), + Some(Bool) => Ok(convert("sve_into", fn_call)), + Some(UInt) if ctx.global.auto_llvm_sign_conversion => { + Ok(convert("as_unsigned", fn_call)) + } _ => Ok(fn_call), } } @@ -807,6 +806,7 @@ pub enum UnsafetyComment { NonTemporal, Neon, NoProvenance(String), + PointerWrite(String), } #[derive(Debug, Clone, Default, Serialize, Deserialize)] @@ -872,8 +872,12 @@ impl fmt::Display for UnsafetyComment { Self::NoProvenance(arg) => write!( f, "Addresses passed in `{arg}` lack provenance, so this is similar to using a \ - `usize as ptr` cast (or [`core::ptr::from_exposed_addr`]) on each lane before \ - using it." + `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane \ + before using it." + ), + Self::PointerWrite(arg) => write!( + f, + "The pointer in `{arg}` must satisfy the requirements of [`core::ptr::write`]." ), Self::UnpredictableOnFault => write!( f, @@ -1055,23 +1059,8 @@ impl Intrinsic { /// Add a big endian implementation fn generate_big_endian(&self, variant: &mut Intrinsic) { - /* We can't always blindly reverse the bits only in certain conditions - * do we need a different order - thus this allows us to have the - * ability to do so without having to play codegolf with the yaml AST */ - let should_reverse = { - if let Some(should_reverse) = variant.big_endian_inverse { - should_reverse - } else if variant.compose.len() == 1 { - match &variant.compose[0] { - Expression::FnCall(fn_call) => fn_call.0.to_string() == "transmute", - _ => false, - } - } else { - false - } - }; - - if !should_reverse { + // We only reverse if it was specifically requested + if !variant.big_endian_inverse.unwrap_or(false) { return; } @@ -1139,7 +1128,7 @@ impl Intrinsic { } else { /* If we do not need to reorder anything then immediately add * the expressions from the big_endian_expressions and - * concatinate the compose vector */ + * concatenate the compose vector */ variant.big_endian_compose.extend(big_endian_expressions); variant .big_endian_compose @@ -1157,11 +1146,11 @@ impl Intrinsic { /* If we do not create a shuffle call we do not need modify the * return value and append to the big endian ast array. A bit confusing - * as in code we are making the final call before caputuring the return + * as in code we are making the final call before capturing the return * value of the intrinsic that has been called.*/ let ret_val_name = "ret_val".to_string(); if let Some(simd_shuffle_call) = create_shuffle_call(&ret_val_name, return_type) { - /* There is a possibility that the funcion arguments did not + /* There is a possibility that the function arguments did not * require big endian treatment, thus we need to now add the * original function body before appending the return value.*/ if variant.big_endian_compose.is_empty() { @@ -1187,9 +1176,10 @@ impl Intrinsic { * re-assigning each tuple however those generated calls do * not make the parent function return. So we add the return * value here */ - variant - .big_endian_compose - .push(create_symbol_identifier(&ret_val_name)); + variant.big_endian_compose.push(create_symbol_identifier( + &ret_val_name, + IdentifierType::Symbol, + )); } } } @@ -1614,6 +1604,7 @@ impl Intrinsic { (Some(BaseTypeKind::Float), Some(BaseTypeKind::Float)) => ex, (Some(BaseTypeKind::UInt), Some(BaseTypeKind::UInt)) => ex, (Some(BaseTypeKind::Poly), Some(BaseTypeKind::Poly)) => ex, + (Some(BaseTypeKind::Bool), Some(BaseTypeKind::Bool)) => ex, (None, None) => ex, _ => unreachable!( @@ -1695,8 +1686,8 @@ enum Endianness { NA, } -/// Based on the endianess will create the appropriate intrinsic, or simply -/// create the desired intrinsic without any endianess +/// Based on the endianness will create the appropriate intrinsic, or simply +/// create the desired intrinsic without any endianness fn create_tokens(intrinsic: &Intrinsic, endianness: Endianness, tokens: &mut TokenStream) { let signature = &intrinsic.signature; let fn_name = signature.fn_name().to_string(); @@ -1736,7 +1727,7 @@ fn create_tokens(intrinsic: &Intrinsic, endianness: Endianness, tokens: &mut Tok ); } - tokens.append_all(quote! { #[inline(always)] }); + tokens.append_all(quote! { #[inline] }); match endianness { Endianness::Little => tokens.append_all(quote! { #[cfg(target_endian = "little")] }), @@ -1811,9 +1802,8 @@ fn create_tokens(intrinsic: &Intrinsic, endianness: Endianness, tokens: &mut Tok body_current = &mut body_unsafe; } ex.to_tokens(body_current); - let is_last = matches!(pos, itertools::Position::Last | itertools::Position::Only); let is_llvm_link = matches!(ex, Expression::LLVMLink(_)); - if !is_last && !is_llvm_link { + if !pos.is_last && !is_llvm_link { body_current.append(Punct::new(';', Spacing::Alone)); } } diff --git a/library/stdarch/crates/stdarch-gen-arm/src/load_store_tests.rs b/library/stdarch/crates/stdarch-gen-arm/src/load_store_tests.rs index 0f4de83dacb4a..672047fc057b8 100644 --- a/library/stdarch/crates/stdarch-gen-arm/src/load_store_tests.rs +++ b/library/stdarch/crates/stdarch-gen-arm/src/load_store_tests.rs @@ -141,13 +141,6 @@ fn generate_single_test( } } - if fn_name.starts_with("svldff1") && fn_name.contains("gather") { - // TODO: We can remove this check when first-faulting gathers are fixed in CI's QEMU - // https://gitlab.com/qemu-project/qemu/-/issues/1612 - println!("Skipping test for {fn_name}"); - return Ok(quote!()); - } - let fn_ident = format_ident!("{fn_name}"); let test_name = format_ident!( "test_{fn_name}{}", @@ -310,12 +303,12 @@ fn generate_single_test( (None, quote!()) }; - let ptr = if chars.gather_bases_type.is_some() { - quote!() + let (ptr_arg, init_ptr) = if chars.gather_bases_type.is_some() { + (quote!(), quote!()) } else if chars.is_prf { - quote!(, I64_DATA.as_ptr()) + (quote!(,ptr), quote!(let ptr = I64_DATA.as_ptr();)) } else { - quote!(, #data_array.as_ptr()) + (quote!(,ptr), quote!(let ptr = #data_array.as_ptr();)) }; let tuple_len = &chars.tuple_len; @@ -327,18 +320,17 @@ fn generate_single_test( .map(|i| get_expected_range(i, &chars)) .collect() }; - let asserts: Vec<_> = - if *tuple_len > 1 { - let svget = format_ident!("svget{tuple_len}_{acle_type}"); - expecteds.iter().enumerate().map(|(i, expected)| { - quote! (#assert_fn(#svget::<{ #i as i32 }>(loaded), #expected);) + let asserts: Vec<_> = if *tuple_len > 1 { + let svget = format_ident!("svget{tuple_len}_{acle_type}"); + expecteds.iter().enumerate().map(|(i, expected)| { + quote! (#assert_fn(#svget::<{ #i as i32 }>(loaded), #expected, defined);) }).collect() - } else { - expecteds - .iter() - .map(|expected| quote! (#assert_fn(loaded, #expected);)) - .collect() - }; + } else { + expecteds + .iter() + .map(|expected| quote! (#assert_fn(loaded, #expected, defined);)) + .collect() + }; let function = if chars.is_prf { if fn_name.contains("gather") && fn_name.contains("base") && !fn_name.starts_with("svprf_") @@ -392,6 +384,7 @@ fn generate_single_test( } else { (quote!(), quote!()) }; + let args = quote!(#pred_fn() #store_ptr #vnum_arg #bases_arg #offset_arg #index_arg #offsets_arg #indices_arg); let call = if chars.uses_ffr { // Doing a normal load first maximises the number of elements our ff/nf test loads @@ -405,12 +398,14 @@ fn generate_single_test( svsetffr(); let _ = #non_ffr_fn_name(#args); let loaded = #function(#args); + let defined = svrdffr(); } } else { // Note that the FFR must be set for all tests as the assert functions mask against it quote! { svsetffr(); let loaded = #function(#args); + let defined = svrdffr(); } }; @@ -436,7 +431,7 @@ fn generate_single_test( } }) } else { - let args = quote!(#pred_fn() #ptr #vnum_arg #bases_arg #offset_arg #index_arg #offsets_arg #indices_arg); + let args = quote!(#pred_fn() #ptr_arg #vnum_arg #bases_arg #offset_arg #index_arg #offsets_arg #indices_arg); let call = if chars.uses_ffr { // Doing a normal load first maximises the number of elements our ff/nf test loads let non_ffr_fn_name = format_ident!( @@ -446,15 +441,19 @@ fn generate_single_test( .replace("svldnf1", "svld1") ); quote! { + #init_ptr svsetffr(); let _ = #non_ffr_fn_name(#args); let loaded = #function(#args); + let defined = svrdffr(); } } else { // Note that the FFR must be set for all tests as the assert functions mask against it quote! { + #init_ptr svsetffr(); let loaded = #function(#args); + let defined = svrdffr(); } }; Ok(quote! { @@ -722,80 +721,70 @@ static U64_DATA: LazyLock<[u64; {LEN_U64} * {NUM_VECS}]> = LazyLock::new(|| {{ }}); #[target_feature(enable = "sve")] -fn assert_vector_matches_f32(vector: svfloat32_t, expected: svfloat32_t) {{ - let defined = svrdffr(); +fn assert_vector_matches_f32(vector: svfloat32_t, expected: svfloat32_t, defined: svbool_t) {{ assert!(svptest_first(svptrue_b32(), defined)); let cmp = svcmpne_f32(defined, vector, expected); assert!(!svptest_any(defined, cmp)) }} #[target_feature(enable = "sve")] -fn assert_vector_matches_f64(vector: svfloat64_t, expected: svfloat64_t) {{ - let defined = svrdffr(); +fn assert_vector_matches_f64(vector: svfloat64_t, expected: svfloat64_t, defined: svbool_t) {{ assert!(svptest_first(svptrue_b64(), defined)); let cmp = svcmpne_f64(defined, vector, expected); assert!(!svptest_any(defined, cmp)) }} #[target_feature(enable = "sve")] -fn assert_vector_matches_i8(vector: svint8_t, expected: svint8_t) {{ - let defined = svrdffr(); +fn assert_vector_matches_i8(vector: svint8_t, expected: svint8_t, defined: svbool_t) {{ assert!(svptest_first(svptrue_b8(), defined)); let cmp = svcmpne_s8(defined, vector, expected); assert!(!svptest_any(defined, cmp)) }} #[target_feature(enable = "sve")] -fn assert_vector_matches_i16(vector: svint16_t, expected: svint16_t) {{ - let defined = svrdffr(); +fn assert_vector_matches_i16(vector: svint16_t, expected: svint16_t, defined: svbool_t) {{ assert!(svptest_first(svptrue_b16(), defined)); let cmp = svcmpne_s16(defined, vector, expected); assert!(!svptest_any(defined, cmp)) }} #[target_feature(enable = "sve")] -fn assert_vector_matches_i32(vector: svint32_t, expected: svint32_t) {{ - let defined = svrdffr(); +fn assert_vector_matches_i32(vector: svint32_t, expected: svint32_t, defined: svbool_t) {{ assert!(svptest_first(svptrue_b32(), defined)); let cmp = svcmpne_s32(defined, vector, expected); assert!(!svptest_any(defined, cmp)) }} #[target_feature(enable = "sve")] -fn assert_vector_matches_i64(vector: svint64_t, expected: svint64_t) {{ - let defined = svrdffr(); +fn assert_vector_matches_i64(vector: svint64_t, expected: svint64_t, defined: svbool_t) {{ assert!(svptest_first(svptrue_b64(), defined)); let cmp = svcmpne_s64(defined, vector, expected); assert!(!svptest_any(defined, cmp)) }} #[target_feature(enable = "sve")] -fn assert_vector_matches_u8(vector: svuint8_t, expected: svuint8_t) {{ - let defined = svrdffr(); +fn assert_vector_matches_u8(vector: svuint8_t, expected: svuint8_t, defined: svbool_t) {{ assert!(svptest_first(svptrue_b8(), defined)); let cmp = svcmpne_u8(defined, vector, expected); assert!(!svptest_any(defined, cmp)) }} #[target_feature(enable = "sve")] -fn assert_vector_matches_u16(vector: svuint16_t, expected: svuint16_t) {{ - let defined = svrdffr(); +fn assert_vector_matches_u16(vector: svuint16_t, expected: svuint16_t, defined: svbool_t) {{ assert!(svptest_first(svptrue_b16(), defined)); let cmp = svcmpne_u16(defined, vector, expected); assert!(!svptest_any(defined, cmp)) }} #[target_feature(enable = "sve")] -fn assert_vector_matches_u32(vector: svuint32_t, expected: svuint32_t) {{ - let defined = svrdffr(); +fn assert_vector_matches_u32(vector: svuint32_t, expected: svuint32_t, defined: svbool_t) {{ assert!(svptest_first(svptrue_b32(), defined)); let cmp = svcmpne_u32(defined, vector, expected); assert!(!svptest_any(defined, cmp)) }} #[target_feature(enable = "sve")] -fn assert_vector_matches_u64(vector: svuint64_t, expected: svuint64_t) {{ - let defined = svrdffr(); +fn assert_vector_matches_u64(vector: svuint64_t, expected: svuint64_t, defined: svbool_t) {{ assert!(svptest_first(svptrue_b64(), defined)); let cmp = svcmpne_u64(defined, vector, expected); assert!(!svptest_any(defined, cmp)) @@ -808,11 +797,11 @@ const MANUAL_TESTS: &str = "#[simd_test(enable = \"sve\")] unsafe fn test_ffr() { svsetffr(); let ffr = svrdffr(); - assert_vector_matches_u8(svdup_n_u8_z(ffr, 1), svindex_u8(1, 0)); + assert_vector_matches_u8(svdup_n_u8_z(ffr, 1), svindex_u8(1, 0), ffr); let pred = svdupq_n_b8(true, false, true, false, true, false, true, false, true, false, true, false, true, false, true, false); svwrffr(pred); let ffr = svrdffr_z(svptrue_b8()); - assert_vector_matches_u8(svdup_n_u8_z(ffr, 1), svdup_n_u8_z(pred, 1)); + assert_vector_matches_u8(svdup_n_u8_z(ffr, 1), svdup_n_u8_z(pred, 1), ffr); } "; diff --git a/library/stdarch/crates/stdarch-gen-arm/src/main.rs b/library/stdarch/crates/stdarch-gen-arm/src/main.rs index 9bf7d0981deb9..1ccdcd8531066 100644 --- a/library/stdarch/crates/stdarch-gen-arm/src/main.rs +++ b/library/stdarch/crates/stdarch-gen-arm/src/main.rs @@ -21,87 +21,91 @@ use std::fs::File; use std::io::Write; use std::path::{Path, PathBuf}; use std::process::{Command, Stdio}; +use stdarch_gen_common::{Mode, run_generator}; use walkdir::WalkDir; fn main() -> Result<(), String> { - parse_args() + let (in_path, out_base) = parse_args(); + let mode = Mode::from_env(); + + for filepath in WalkDir::new(&in_path) .into_iter() - .map(|(filepath, out)| { - File::open(&filepath) - .map(|f| (f, filepath, out)) - .map_err(|e| format!("could not read input file: {e}")) - }) - .map(|res| { - let (file, filepath, out) = res?; - serde_yaml::from_reader(file) - .map(|input: input::GeneratorInput| (input, filepath, out)) - .map_err(|e| format!("could not parse input file: {e}")) + .filter_map(Result::ok) + .filter(|f| f.file_type().is_file()) + .filter(|f| f.file_name().to_string_lossy().ends_with(".yml")) + .map(|f| f.into_path()) + { + // Directory the harness checks/blesses against. The committed output + // location for this spec file (`///`). + let committed = make_output_filepath(&filepath, &out_base) + .parent() + .expect("generated output path must have a parent directory") + .to_path_buf(); + + run_generator(&committed, mode, |scratch: &Path| { + generate_spec(&filepath, scratch) }) - .collect::, _>>()? - .into_iter() - .map(|(input, filepath, out)| { - let intrinsics = input.intrinsics.into_iter() - .map(|intrinsic| { - intrinsic.generate_variants(&input.ctx) - }) - .try_collect() - .map(|mut vv: Vec<_>| { - vv.sort_by_cached_key(|variants| { - variants.first().map_or_else(String::default, |variant| { - variant.signature.fn_name().to_string() - }) - }); - vv.into_iter().flatten().collect_vec() - })?; + .map_err(|e| e.to_string())?; + } + Ok(()) +} - if filepath.ends_with("sve.spec.yml") || filepath.ends_with("sve2.spec.yml") { - let loads = intrinsics.iter() - .filter_map(|i| { - if matches!(i.test, Test::Load(..)) { - Some(i.clone()) - } else { - None - } - }).collect(); - let stores = intrinsics.iter() - .filter_map(|i| { - if matches!(i.test, Test::Store(..)) { - Some(i.clone()) - } else { - None - } - }).collect(); - load_store_tests::generate_load_store_tests(loads, stores, out.as_ref().map(|o| make_tests_filepath(&filepath, o)).as_ref())?; - } +/// Generate the output files for a single spec file into `out_dir`. +fn generate_spec(filepath: &Path, out_dir: &Path) -> Result<(), String> { + let file = File::open(filepath).map_err(|e| format!("could not read input file: {e}"))?; + let input: input::GeneratorInput = + serde_yaml::from_reader(file).map_err(|e| format!("could not parse input file: {e}"))?; - Ok(( - input::GeneratorInput { - intrinsics, - ctx: input.ctx, - }, - filepath, - out, - )) - }) - .try_for_each( - |result: context::Result<(input::GeneratorInput, PathBuf, Option)>| -> context::Result { - let (generated, filepath, out) = result?; + let intrinsics = input + .intrinsics + .into_iter() + .map(|intrinsic| intrinsic.generate_variants(&input.ctx)) + .try_collect() + .map(|mut vv: Vec<_>| { + vv.sort_by_cached_key(|variants| { + variants.first().map_or_else(String::default, |variant| { + variant.signature.fn_name().to_string() + }) + }); + vv.into_iter().flatten().collect_vec() + })?; - let w = match out { - Some(out) => Box::new( - File::create(make_output_filepath(&filepath, &out)) - .map_err(|e| format!("could not create output file: {e}"))?, - ) as Box, - None => Box::new(std::io::stdout()) as Box, - }; + if input.ctx.generate_load_store_tests { + let loads = intrinsics + .iter() + .filter_map(|i| match i.test { + Test::Load(..) => Some(i.clone()), + _ => None, + }) + .collect(); + let stores = intrinsics + .iter() + .filter_map(|i| match i.test { + Test::Store(..) => Some(i.clone()), + _ => None, + }) + .collect(); + // Reuse make_tests_filepath to derive the correct leaf name + // (`ld_st_tests_.rs`), then write it into out_dir. + let tests_name = make_tests_filepath(filepath, Path::new("")) + .file_name() + .expect("load/store test path must have a file name") + .to_owned(); + let tests_path = out_dir.join(tests_name); + load_store_tests::generate_load_store_tests(loads, stores, Some(&tests_path))?; + } - generate_file(generated, w) - .map_err(|e| format!("could not generate output file: {e}")) - }, - ) + let generated = input::GeneratorInput { + intrinsics, + ctx: input.ctx, + }; + let out_file = File::create(out_dir.join("generated.rs")) + .map_err(|e| format!("could not create output file: {e}"))?; + generate_file(generated, Box::new(out_file) as Box) + .map_err(|e| format!("could not generate output file: {e}")) } -fn parse_args() -> Vec<(PathBuf, Option)> { +fn parse_args() -> (PathBuf, PathBuf) { let mut args_it = std::env::args().skip(1); assert!( 1 <= args_it.len() && args_it.len() <= 2, @@ -117,30 +121,26 @@ fn parse_args() -> Vec<(PathBuf, Option)> { "invalid path {in_path:#?} given" ); - let out_dir = if let Some(dir) = args_it.next() { + let out_base = if let Some(dir) = args_it.next() { let out_path = Path::new(dir.as_str()).to_path_buf(); assert!( out_path.exists() && out_path.is_dir(), "invalid path {out_path:#?} given" ); - Some(out_path) + out_path } else { std::env::current_exe() + .ok() .map(|mut f| { f.pop(); f.push("../../crates/core_arch/src/"); - f.exists().then_some(f) + f }) - .ok() - .flatten() + .filter(|f| f.exists()) + .expect("could not locate crates/core_arch/src; pass OUTPUT_DIR command-line argument explicitly") }; - WalkDir::new(in_path) - .into_iter() - .filter_map(Result::ok) - .filter(|f| f.file_type().is_file()) - .map(|f| (f.into_path(), out_dir.clone())) - .collect() + (in_path, out_base) } fn generate_file( @@ -165,7 +165,7 @@ use super::*;{uses_neon} "#, uses_neon = if generated_input.ctx.uses_neon_types { - "\nuse crate::core_arch::arch::aarch64::*;" + "\nuse crate::core_arch::arch::aarch64::*;\nuse super::{AsSigned, AsUnsigned};" } else { "" }, diff --git a/library/stdarch/crates/stdarch-gen-arm/src/typekinds.rs b/library/stdarch/crates/stdarch-gen-arm/src/typekinds.rs index bd47ff2bd1557..c3aa22294d9fc 100644 --- a/library/stdarch/crates/stdarch-gen-arm/src/typekinds.rs +++ b/library/stdarch/crates/stdarch-gen-arm/src/typekinds.rs @@ -289,9 +289,9 @@ impl TypeKind { ( BaseType::Sized(Float | Int | UInt, _), BaseType::Sized(Float | Int | UInt, _), - ) => Some(FnCall::new_expression( + ) => Some(FnCall::new_unsafe_expression( // Conversions between float and (u)int, or where the lane size changes. - "simd_reinterpret".parse().unwrap(), + "transmute_unchecked".parse().unwrap(), vec![expr.into()], )), _ => None, diff --git a/library/stdarch/crates/stdarch-gen-common/Cargo.toml b/library/stdarch/crates/stdarch-gen-common/Cargo.toml new file mode 100644 index 0000000000000..691be14971a0d --- /dev/null +++ b/library/stdarch/crates/stdarch-gen-common/Cargo.toml @@ -0,0 +1,7 @@ +[package] +name = "stdarch-gen-common" +version = "0.1.0" +edition = "2024" + +[dependencies] +tempfile = "3" \ No newline at end of file diff --git a/library/stdarch/crates/stdarch-gen-common/src/lib.rs b/library/stdarch/crates/stdarch-gen-common/src/lib.rs new file mode 100644 index 0000000000000..13d788594ca55 --- /dev/null +++ b/library/stdarch/crates/stdarch-gen-common/src/lib.rs @@ -0,0 +1,352 @@ +//! Shared check/bless harness for stdarch generators. + +use std::error::Error as StdError; +use std::fmt; +use std::fs; +use std::io; +use std::io::Read; +use std::path::{Path, PathBuf}; + +/// First-line marker identifying an auto-generated file. Generators emit this +/// as the first line of every file they produce; the harness uses it to +/// discover which files in `committed` are owned by the generator. +pub const GENERATED_MARKER: &str = "// This code is automatically generated. DO NOT MODIFY."; + +/// Controls what `run_generator` does with the generator's output. +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub enum Mode { + /// Verify that the `committed` matches the generator's output for owned files. + /// + /// Runs the generator into a temp directory, then compares each produced + /// file against the committed copy. Returns an error on the first mismatch. + Check, + /// Update the `committed` to match the generator's output for owned files. + /// + /// Runs the generator into a temp directory and copies each produced file + /// into `committed`. If the generator no longer produces an owned file, the + /// committed copy is deleted. Files in `committed` that are not owned + /// are left untouched. + Bless, +} + +impl Mode { + /// Read the mode from the `STDARCH_GEN_MODE` environment variable. + /// + /// Recognized values: + /// - `"check"` → [`Mode::Check`] + /// - `"bless"` → [`Mode::Bless`] + /// - unset → [`Mode::Bless`] + /// - any other value → panic + pub fn from_env() -> Self { + match std::env::var("STDARCH_GEN_MODE").as_deref() { + Ok("check") => Mode::Check, + Ok("bless") => Mode::Bless, + Ok(other) => panic!("unknown STDARCH_GEN_MODE value: {other:?}"), + Err(_) => Mode::Bless, + } + } +} + +#[derive(Debug)] +pub enum Error { + Io(io::Error), + Mismatch { path: PathBuf, kind: MismatchKind }, + Generator(Box), +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub enum MismatchKind { + /// Owned file produced by the generator but absent from the `committed`. + /// Means the `committed` needs to be regenerated. + MissingInCommitted, + /// Owned file present in the `committed` but the generator no longer + /// produces it. The file must be removed from the `committed` . + ExtraInCommitted, + /// Owned file exists on both sides but contents differ. + ContentsDiffer, +} + +impl fmt::Display for Error { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self { + Error::Io(e) => write!(f, "I/O error: {e}"), + Error::Mismatch { path, kind } => match kind { + MismatchKind::MissingInCommitted => { + write!(f, "{}: generated but not committed", path.display()) + } + MismatchKind::ExtraInCommitted => { + write!(f, "{}: committed but no longer generated", path.display()) + } + MismatchKind::ContentsDiffer => write!(f, "{}: contents differ", path.display()), + }, + Error::Generator(e) => write!(f, "generator failed: {e}"), + } + } +} + +impl StdError for Error { + fn source(&self) -> Option<&(dyn StdError + 'static)> { + match self { + Error::Io(e) => Some(e), + Error::Generator(e) => Some(&**e), + _ => None, + } + } +} + +impl From for Error { + fn from(e: io::Error) -> Self { + Error::Io(e) + } +} + +pub type Result = std::result::Result; + +/// Run a generator under the chosen `mode`, reconciling its output with `committed`. +/// +/// Arguments: +/// - `committed` — the directory holding the in-tree (committed) source files. +/// Files inside `committed` whose first line begins with [`GENERATED_MARKER`] +/// are treated as owned by the generator. Anything else is treated as +/// hand-written and is left untouched by `Bless` and ignored by `Check`. +/// So generated files coexist with hand-written files in the same directory. +/// - `mode` — what to do with the generator's output. +/// - `generate` — closure that writes the generator's output into the +/// directory it is given. Its error is wrapped in [`Error::Generator`]. +/// +/// Behavior per mode: +/// - [`Mode::Check`]: runs the generator into a temp dir and compares owned +/// files against the committed copies. Mismatch returns [`Error::Mismatch`]. +/// - [`Mode::Bless`]: runs the generator into a temp dir and copies owned +/// files into `committed`, or removes `committed`'s copy if the generator no +/// longer produces them. +pub fn run_generator(committed: &Path, mode: Mode, generate: F) -> Result<()> +where + F: FnOnce(&Path) -> std::result::Result<(), E>, + E: Into>, +{ + let scratch = tempfile::tempdir()?; + generate(scratch.path()).map_err(|e| Error::Generator(e.into()))?; + + let owned = discover_owned(committed)?; + let produced = discover_all(scratch.path())?; + + let mut names: Vec<&String> = owned.iter().chain(produced.iter()).collect(); + names.sort(); + names.dedup(); + + for name in names { + match mode { + Mode::Check => compare(scratch.path(), committed, name)?, + Mode::Bless => apply_bless(scratch.path(), committed, name)?, + } + } + Ok(()) +} + +/// Returns the names of files in `dir` whose first line begins with +/// [`GENERATED_MARKER`]. Files without the marker are skipped. +fn discover_owned(dir: &Path) -> Result> { + let mut out = Vec::new(); + for entry in fs::read_dir(dir)? { + let entry = entry?; + if !entry.file_type()?.is_file() { + continue; + } + let Ok(mut file) = fs::File::open(entry.path()) else { + continue; + }; + let mut buf = [0u8; GENERATED_MARKER.len()]; + if file.read_exact(&mut buf).is_err() { + continue; + } + if buf == *GENERATED_MARKER.as_bytes() + && let Some(name) = entry.file_name().to_str() + { + out.push(name.to_owned()); + } + } + out.sort(); + Ok(out) +} + +/// Returns every file name in `dir` (scratch dir — all files are generator output). +fn discover_all(dir: &Path) -> Result> { + let mut out = Vec::new(); + for entry in fs::read_dir(dir)? { + let entry = entry?; + if entry.file_type()?.is_file() + && let Some(name) = entry.file_name().to_str() + { + out.push(name.to_string()); + } + } + Ok(out) +} + +fn compare(generated_dir: &Path, committed_dir: &Path, filename: &str) -> Result<()> { + let rel_path = PathBuf::from(filename); + let gen_path = generated_dir.join(&rel_path); + let comm_path = committed_dir.join(&rel_path); + match (gen_path.exists(), comm_path.exists()) { + (true, false) => Err(Error::Mismatch { + path: rel_path, + kind: MismatchKind::MissingInCommitted, + }), + (false, true) => Err(Error::Mismatch { + path: rel_path, + kind: MismatchKind::ExtraInCommitted, + }), + (false, false) => Ok(()), + (true, true) => { + if fs::read(&gen_path)? != fs::read(&comm_path)? { + Err(Error::Mismatch { + path: rel_path, + kind: MismatchKind::ContentsDiffer, + }) + } else { + Ok(()) + } + } + } +} + +fn apply_bless(generated_dir: &Path, committed_dir: &Path, filename: &str) -> Result<()> { + fs::create_dir_all(committed_dir)?; + let rel_path = PathBuf::from(filename); + let from = generated_dir.join(&rel_path); + let to = committed_dir.join(&rel_path); + if from.exists() { + if let Some(parent) = to.parent() { + fs::create_dir_all(parent)?; + } + fs::copy(&from, &to)?; + } else if to.exists() { + fs::remove_file(&to)?; + } + Ok(()) +} + +// Skipped on iOS because these tests fail on the `x86_64-apple-ios-macabi` CI runner +// with `Os { code: 17, kind: AlreadyExists, message: "File exists" }`. +#[cfg(all(test, not(target_os = "ios")))] +mod tests { + use super::*; + + fn write_marker(p: &Path, body: &[u8]) { + if let Some(d) = p.parent() { + fs::create_dir_all(d).unwrap(); + } + let mut bytes = Vec::new(); + bytes.extend_from_slice(GENERATED_MARKER.as_bytes()); + bytes.push(b'\n'); + bytes.extend_from_slice(body); + fs::write(p, bytes).unwrap(); + } + + #[test] + fn check_fails_on_byte_diff() { + let tmp = tempfile::tempdir().unwrap(); + let committed = tmp.path().join("c"); + write_marker(&committed.join("a.txt"), b"hi"); + let e = run_generator( + &committed, + Mode::Check, + |out| -> std::result::Result<(), io::Error> { + write_marker(&out.join("a.txt"), b"HI"); + Ok(()) + }, + ) + .unwrap_err(); + assert!(matches!( + e, + Error::Mismatch { + kind: MismatchKind::ContentsDiffer, + .. + } + )); + } + + #[test] + fn check_fails_when_owned_file_missing_from_generated() { + let tmp = tempfile::tempdir().unwrap(); + let committed = tmp.path().join("c"); + write_marker(&committed.join("a.txt"), b"hi"); + let e = run_generator( + &committed, + Mode::Check, + |_| -> std::result::Result<(), io::Error> { Ok(()) }, + ) + .unwrap_err(); + assert!(matches!( + e, + Error::Mismatch { + kind: MismatchKind::ExtraInCommitted, + .. + } + )); + } + + #[test] + fn check_fails_when_owned_file_missing_from_committed() { + let tmp = tempfile::tempdir().unwrap(); + let committed = tmp.path().join("c"); + fs::create_dir_all(&committed).unwrap(); + let e = run_generator( + &committed, + Mode::Check, + |out| -> std::result::Result<(), io::Error> { + write_marker(&out.join("a.txt"), b"hi"); + Ok(()) + }, + ) + .unwrap_err(); + assert!(matches!( + e, + Error::Mismatch { + kind: MismatchKind::MissingInCommitted, + .. + } + )); + } + + #[test] + fn bless_deletes_files_no_longer_produced() { + let tmp = tempfile::tempdir().unwrap(); + let committed = tmp.path().join("c"); + write_marker(&committed.join("keep.txt"), b""); + write_marker(&committed.join("stale.txt"), b""); + run_generator( + &committed, + Mode::Bless, + |out| -> std::result::Result<(), io::Error> { + write_marker(&out.join("keep.txt"), b""); + Ok(()) + }, + ) + .unwrap(); + assert!(committed.join("keep.txt").exists()); + assert!(!committed.join("stale.txt").exists()); + } + + #[test] + fn bless_preserves_unowned_files() { + let tmp = tempfile::tempdir().unwrap(); + let committed = tmp.path().join("c"); + fs::create_dir_all(&committed).unwrap(); + fs::write(committed.join("mod.rs"), b"hand-written").unwrap(); + fs::write(committed.join("old.txt"), b"old").unwrap(); + run_generator( + &committed, + Mode::Bless, + |out| -> std::result::Result<(), io::Error> { + write_marker(&out.join("new.txt"), b"new"); + Ok(()) + }, + ) + .unwrap(); + assert_eq!(fs::read(committed.join("mod.rs")).unwrap(), b"hand-written"); + assert_eq!(fs::read(committed.join("old.txt")).unwrap(), b"old"); + assert!(committed.join("new.txt").exists()); + } +} diff --git a/library/stdarch/crates/stdarch-gen-hexagon/Cargo.toml b/library/stdarch/crates/stdarch-gen-hexagon/Cargo.toml new file mode 100644 index 0000000000000..c7dfce2c0fd7b --- /dev/null +++ b/library/stdarch/crates/stdarch-gen-hexagon/Cargo.toml @@ -0,0 +1,10 @@ +[package] +name = "stdarch-gen-hexagon" +version = "0.1.0" +authors = ["The Rust Project Developers"] +license = "MIT OR Apache-2.0" +edition = "2021" + +[dependencies] +regex = "1.10" +stdarch-gen-common = { path = "../stdarch-gen-common" } diff --git a/library/stdarch/crates/stdarch-gen-hexagon/hexagon_protos.h b/library/stdarch/crates/stdarch-gen-hexagon/hexagon_protos.h new file mode 100644 index 0000000000000..2642f3c8428d8 --- /dev/null +++ b/library/stdarch/crates/stdarch-gen-hexagon/hexagon_protos.h @@ -0,0 +1,8439 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// Automatically generated file, do not edit! +//===----------------------------------------------------------------------===// + + + +#ifndef __HEXAGON_PROTOS_H_ +#define __HEXAGON_PROTOS_H_ 1 + +/* ========================================================================== + Assembly Syntax: Rd32=abs(Rs32) + C Intrinsic Prototype: Word32 Q6_R_abs_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_abs_R __builtin_HEXAGON_A2_abs + +/* ========================================================================== + Assembly Syntax: Rdd32=abs(Rss32) + C Intrinsic Prototype: Word64 Q6_P_abs_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_abs_P __builtin_HEXAGON_A2_absp + +/* ========================================================================== + Assembly Syntax: Rd32=abs(Rs32):sat + C Intrinsic Prototype: Word32 Q6_R_abs_R_sat(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_abs_R_sat __builtin_HEXAGON_A2_abssat + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_add_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_add_RR __builtin_HEXAGON_A2_add + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.h,Rs32.h):<<16 + C Intrinsic Prototype: Word32 Q6_R_add_RhRh_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RhRh_s16 __builtin_HEXAGON_A2_addh_h16_hh + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.h,Rs32.l):<<16 + C Intrinsic Prototype: Word32 Q6_R_add_RhRl_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RhRl_s16 __builtin_HEXAGON_A2_addh_h16_hl + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.l,Rs32.h):<<16 + C Intrinsic Prototype: Word32 Q6_R_add_RlRh_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RlRh_s16 __builtin_HEXAGON_A2_addh_h16_lh + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.l,Rs32.l):<<16 + C Intrinsic Prototype: Word32 Q6_R_add_RlRl_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RlRl_s16 __builtin_HEXAGON_A2_addh_h16_ll + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.h,Rs32.h):sat:<<16 + C Intrinsic Prototype: Word32 Q6_R_add_RhRh_sat_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RhRh_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_hh + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.h,Rs32.l):sat:<<16 + C Intrinsic Prototype: Word32 Q6_R_add_RhRl_sat_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RhRl_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_hl + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.l,Rs32.h):sat:<<16 + C Intrinsic Prototype: Word32 Q6_R_add_RlRh_sat_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RlRh_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_lh + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.l,Rs32.l):sat:<<16 + C Intrinsic Prototype: Word32 Q6_R_add_RlRl_sat_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RlRl_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_ll + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.l,Rs32.h) + C Intrinsic Prototype: Word32 Q6_R_add_RlRh(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RlRh __builtin_HEXAGON_A2_addh_l16_hl + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.l,Rs32.l) + C Intrinsic Prototype: Word32 Q6_R_add_RlRl(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RlRl __builtin_HEXAGON_A2_addh_l16_ll + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.l,Rs32.h):sat + C Intrinsic Prototype: Word32 Q6_R_add_RlRh_sat(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RlRh_sat __builtin_HEXAGON_A2_addh_l16_sat_hl + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.l,Rs32.l):sat + C Intrinsic Prototype: Word32 Q6_R_add_RlRl_sat(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RlRl_sat __builtin_HEXAGON_A2_addh_l16_sat_ll + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rs32,#s16) + C Intrinsic Prototype: Word32 Q6_R_add_RI(Word32 Rs, Word32 Is16) + Instruction Type: ALU32_ADDI + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_add_RI __builtin_HEXAGON_A2_addi + +/* ========================================================================== + Assembly Syntax: Rdd32=add(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_add_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_add_PP __builtin_HEXAGON_A2_addp + +/* ========================================================================== + Assembly Syntax: Rdd32=add(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_add_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_add_PP_sat __builtin_HEXAGON_A2_addpsat + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rs32,Rt32):sat + C Intrinsic Prototype: Word32 Q6_R_add_RR_sat(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_add_RR_sat __builtin_HEXAGON_A2_addsat + +/* ========================================================================== + Assembly Syntax: Rdd32=add(Rs32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_add_RP(Word32 Rs, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_add_RP __builtin_HEXAGON_A2_addsp + +/* ========================================================================== + Assembly Syntax: Rd32=and(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_and_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_and_RR __builtin_HEXAGON_A2_and + +/* ========================================================================== + Assembly Syntax: Rd32=and(Rs32,#s10) + C Intrinsic Prototype: Word32 Q6_R_and_RI(Word32 Rs, Word32 Is10) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_and_RI __builtin_HEXAGON_A2_andir + +/* ========================================================================== + Assembly Syntax: Rdd32=and(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_and_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_and_PP __builtin_HEXAGON_A2_andp + +/* ========================================================================== + Assembly Syntax: Rd32=aslh(Rs32) + C Intrinsic Prototype: Word32 Q6_R_aslh_R(Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_aslh_R __builtin_HEXAGON_A2_aslh + +/* ========================================================================== + Assembly Syntax: Rd32=asrh(Rs32) + C Intrinsic Prototype: Word32 Q6_R_asrh_R(Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_asrh_R __builtin_HEXAGON_A2_asrh + +/* ========================================================================== + Assembly Syntax: Rd32=combine(Rt32.h,Rs32.h) + C Intrinsic Prototype: Word32 Q6_R_combine_RhRh(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_combine_RhRh __builtin_HEXAGON_A2_combine_hh + +/* ========================================================================== + Assembly Syntax: Rd32=combine(Rt32.h,Rs32.l) + C Intrinsic Prototype: Word32 Q6_R_combine_RhRl(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_combine_RhRl __builtin_HEXAGON_A2_combine_hl + +/* ========================================================================== + Assembly Syntax: Rd32=combine(Rt32.l,Rs32.h) + C Intrinsic Prototype: Word32 Q6_R_combine_RlRh(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_combine_RlRh __builtin_HEXAGON_A2_combine_lh + +/* ========================================================================== + Assembly Syntax: Rd32=combine(Rt32.l,Rs32.l) + C Intrinsic Prototype: Word32 Q6_R_combine_RlRl(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_combine_RlRl __builtin_HEXAGON_A2_combine_ll + +/* ========================================================================== + Assembly Syntax: Rdd32=combine(#s8,#S8) + C Intrinsic Prototype: Word64 Q6_P_combine_II(Word32 Is8, Word32 IS8) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_combine_II __builtin_HEXAGON_A2_combineii + +/* ========================================================================== + Assembly Syntax: Rdd32=combine(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_combine_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_combine_RR __builtin_HEXAGON_A2_combinew + +/* ========================================================================== + Assembly Syntax: Rd32=max(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_max_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_max_RR __builtin_HEXAGON_A2_max + +/* ========================================================================== + Assembly Syntax: Rdd32=max(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_max_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_max_PP __builtin_HEXAGON_A2_maxp + +/* ========================================================================== + Assembly Syntax: Rd32=maxu(Rs32,Rt32) + C Intrinsic Prototype: UWord32 Q6_R_maxu_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_maxu_RR __builtin_HEXAGON_A2_maxu + +/* ========================================================================== + Assembly Syntax: Rdd32=maxu(Rss32,Rtt32) + C Intrinsic Prototype: UWord64 Q6_P_maxu_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_maxu_PP __builtin_HEXAGON_A2_maxup + +/* ========================================================================== + Assembly Syntax: Rd32=min(Rt32,Rs32) + C Intrinsic Prototype: Word32 Q6_R_min_RR(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_min_RR __builtin_HEXAGON_A2_min + +/* ========================================================================== + Assembly Syntax: Rdd32=min(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_min_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_min_PP __builtin_HEXAGON_A2_minp + +/* ========================================================================== + Assembly Syntax: Rd32=minu(Rt32,Rs32) + C Intrinsic Prototype: UWord32 Q6_R_minu_RR(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_minu_RR __builtin_HEXAGON_A2_minu + +/* ========================================================================== + Assembly Syntax: Rdd32=minu(Rtt32,Rss32) + C Intrinsic Prototype: UWord64 Q6_P_minu_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_minu_PP __builtin_HEXAGON_A2_minup + +/* ========================================================================== + Assembly Syntax: Rd32=neg(Rs32) + C Intrinsic Prototype: Word32 Q6_R_neg_R(Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_neg_R __builtin_HEXAGON_A2_neg + +/* ========================================================================== + Assembly Syntax: Rdd32=neg(Rss32) + C Intrinsic Prototype: Word64 Q6_P_neg_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_neg_P __builtin_HEXAGON_A2_negp + +/* ========================================================================== + Assembly Syntax: Rd32=neg(Rs32):sat + C Intrinsic Prototype: Word32 Q6_R_neg_R_sat(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_neg_R_sat __builtin_HEXAGON_A2_negsat + +/* ========================================================================== + Assembly Syntax: Rd32=not(Rs32) + C Intrinsic Prototype: Word32 Q6_R_not_R(Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_not_R __builtin_HEXAGON_A2_not + +/* ========================================================================== + Assembly Syntax: Rdd32=not(Rss32) + C Intrinsic Prototype: Word64 Q6_P_not_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_not_P __builtin_HEXAGON_A2_notp + +/* ========================================================================== + Assembly Syntax: Rd32=or(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_or_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_or_RR __builtin_HEXAGON_A2_or + +/* ========================================================================== + Assembly Syntax: Rd32=or(Rs32,#s10) + C Intrinsic Prototype: Word32 Q6_R_or_RI(Word32 Rs, Word32 Is10) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_or_RI __builtin_HEXAGON_A2_orir + +/* ========================================================================== + Assembly Syntax: Rdd32=or(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_or_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_or_PP __builtin_HEXAGON_A2_orp + +/* ========================================================================== + Assembly Syntax: Rd32=round(Rss32):sat + C Intrinsic Prototype: Word32 Q6_R_round_P_sat(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_round_P_sat __builtin_HEXAGON_A2_roundsat + +/* ========================================================================== + Assembly Syntax: Rd32=sat(Rss32) + C Intrinsic Prototype: Word32 Q6_R_sat_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sat_P __builtin_HEXAGON_A2_sat + +/* ========================================================================== + Assembly Syntax: Rd32=satb(Rs32) + C Intrinsic Prototype: Word32 Q6_R_satb_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_satb_R __builtin_HEXAGON_A2_satb + +/* ========================================================================== + Assembly Syntax: Rd32=sath(Rs32) + C Intrinsic Prototype: Word32 Q6_R_sath_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sath_R __builtin_HEXAGON_A2_sath + +/* ========================================================================== + Assembly Syntax: Rd32=satub(Rs32) + C Intrinsic Prototype: Word32 Q6_R_satub_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_satub_R __builtin_HEXAGON_A2_satub + +/* ========================================================================== + Assembly Syntax: Rd32=satuh(Rs32) + C Intrinsic Prototype: Word32 Q6_R_satuh_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_satuh_R __builtin_HEXAGON_A2_satuh + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32,Rs32) + C Intrinsic Prototype: Word32 Q6_R_sub_RR(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_sub_RR __builtin_HEXAGON_A2_sub + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.h,Rs32.h):<<16 + C Intrinsic Prototype: Word32 Q6_R_sub_RhRh_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RhRh_s16 __builtin_HEXAGON_A2_subh_h16_hh + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.h,Rs32.l):<<16 + C Intrinsic Prototype: Word32 Q6_R_sub_RhRl_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RhRl_s16 __builtin_HEXAGON_A2_subh_h16_hl + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.l,Rs32.h):<<16 + C Intrinsic Prototype: Word32 Q6_R_sub_RlRh_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RlRh_s16 __builtin_HEXAGON_A2_subh_h16_lh + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.l,Rs32.l):<<16 + C Intrinsic Prototype: Word32 Q6_R_sub_RlRl_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RlRl_s16 __builtin_HEXAGON_A2_subh_h16_ll + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.h,Rs32.h):sat:<<16 + C Intrinsic Prototype: Word32 Q6_R_sub_RhRh_sat_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RhRh_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_hh + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.h,Rs32.l):sat:<<16 + C Intrinsic Prototype: Word32 Q6_R_sub_RhRl_sat_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RhRl_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_hl + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.l,Rs32.h):sat:<<16 + C Intrinsic Prototype: Word32 Q6_R_sub_RlRh_sat_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RlRh_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_lh + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.l,Rs32.l):sat:<<16 + C Intrinsic Prototype: Word32 Q6_R_sub_RlRl_sat_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RlRl_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_ll + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.l,Rs32.h) + C Intrinsic Prototype: Word32 Q6_R_sub_RlRh(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RlRh __builtin_HEXAGON_A2_subh_l16_hl + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.l,Rs32.l) + C Intrinsic Prototype: Word32 Q6_R_sub_RlRl(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RlRl __builtin_HEXAGON_A2_subh_l16_ll + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.l,Rs32.h):sat + C Intrinsic Prototype: Word32 Q6_R_sub_RlRh_sat(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RlRh_sat __builtin_HEXAGON_A2_subh_l16_sat_hl + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.l,Rs32.l):sat + C Intrinsic Prototype: Word32 Q6_R_sub_RlRl_sat(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RlRl_sat __builtin_HEXAGON_A2_subh_l16_sat_ll + +/* ========================================================================== + Assembly Syntax: Rdd32=sub(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_sub_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_sub_PP __builtin_HEXAGON_A2_subp + +/* ========================================================================== + Assembly Syntax: Rd32=sub(#s10,Rs32) + C Intrinsic Prototype: Word32 Q6_R_sub_IR(Word32 Is10, Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_sub_IR __builtin_HEXAGON_A2_subri + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32,Rs32):sat + C Intrinsic Prototype: Word32 Q6_R_sub_RR_sat(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_sub_RR_sat __builtin_HEXAGON_A2_subsat + +/* ========================================================================== + Assembly Syntax: Rd32=vaddh(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_vaddh_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_vaddh_RR __builtin_HEXAGON_A2_svaddh + +/* ========================================================================== + Assembly Syntax: Rd32=vaddh(Rs32,Rt32):sat + C Intrinsic Prototype: Word32 Q6_R_vaddh_RR_sat(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_vaddh_RR_sat __builtin_HEXAGON_A2_svaddhs + +/* ========================================================================== + Assembly Syntax: Rd32=vadduh(Rs32,Rt32):sat + C Intrinsic Prototype: Word32 Q6_R_vadduh_RR_sat(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_vadduh_RR_sat __builtin_HEXAGON_A2_svadduhs + +/* ========================================================================== + Assembly Syntax: Rd32=vavgh(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_vavgh_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_vavgh_RR __builtin_HEXAGON_A2_svavgh + +/* ========================================================================== + Assembly Syntax: Rd32=vavgh(Rs32,Rt32):rnd + C Intrinsic Prototype: Word32 Q6_R_vavgh_RR_rnd(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_vavgh_RR_rnd __builtin_HEXAGON_A2_svavghs + +/* ========================================================================== + Assembly Syntax: Rd32=vnavgh(Rt32,Rs32) + C Intrinsic Prototype: Word32 Q6_R_vnavgh_RR(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_vnavgh_RR __builtin_HEXAGON_A2_svnavgh + +/* ========================================================================== + Assembly Syntax: Rd32=vsubh(Rt32,Rs32) + C Intrinsic Prototype: Word32 Q6_R_vsubh_RR(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_vsubh_RR __builtin_HEXAGON_A2_svsubh + +/* ========================================================================== + Assembly Syntax: Rd32=vsubh(Rt32,Rs32):sat + C Intrinsic Prototype: Word32 Q6_R_vsubh_RR_sat(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_vsubh_RR_sat __builtin_HEXAGON_A2_svsubhs + +/* ========================================================================== + Assembly Syntax: Rd32=vsubuh(Rt32,Rs32):sat + C Intrinsic Prototype: Word32 Q6_R_vsubuh_RR_sat(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_vsubuh_RR_sat __builtin_HEXAGON_A2_svsubuhs + +/* ========================================================================== + Assembly Syntax: Rd32=swiz(Rs32) + C Intrinsic Prototype: Word32 Q6_R_swiz_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_swiz_R __builtin_HEXAGON_A2_swiz + +/* ========================================================================== + Assembly Syntax: Rd32=sxtb(Rs32) + C Intrinsic Prototype: Word32 Q6_R_sxtb_R(Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_sxtb_R __builtin_HEXAGON_A2_sxtb + +/* ========================================================================== + Assembly Syntax: Rd32=sxth(Rs32) + C Intrinsic Prototype: Word32 Q6_R_sxth_R(Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_sxth_R __builtin_HEXAGON_A2_sxth + +/* ========================================================================== + Assembly Syntax: Rdd32=sxtw(Rs32) + C Intrinsic Prototype: Word64 Q6_P_sxtw_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_sxtw_R __builtin_HEXAGON_A2_sxtw + +/* ========================================================================== + Assembly Syntax: Rd32=Rs32 + C Intrinsic Prototype: Word32 Q6_R_equals_R(Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_equals_R __builtin_HEXAGON_A2_tfr + +/* ========================================================================== + Assembly Syntax: Rx32.h=#u16 + C Intrinsic Prototype: Word32 Q6_Rh_equals_I(Word32 Rx, Word32 Iu16) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Rh_equals_I __builtin_HEXAGON_A2_tfrih + +/* ========================================================================== + Assembly Syntax: Rx32.l=#u16 + C Intrinsic Prototype: Word32 Q6_Rl_equals_I(Word32 Rx, Word32 Iu16) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Rl_equals_I __builtin_HEXAGON_A2_tfril + +/* ========================================================================== + Assembly Syntax: Rdd32=Rss32 + C Intrinsic Prototype: Word64 Q6_P_equals_P(Word64 Rss) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_equals_P __builtin_HEXAGON_A2_tfrp + +/* ========================================================================== + Assembly Syntax: Rdd32=#s8 + C Intrinsic Prototype: Word64 Q6_P_equals_I(Word32 Is8) + Instruction Type: ALU64 + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_equals_I __builtin_HEXAGON_A2_tfrpi + +/* ========================================================================== + Assembly Syntax: Rd32=#s16 + C Intrinsic Prototype: Word32 Q6_R_equals_I(Word32 Is16) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_equals_I __builtin_HEXAGON_A2_tfrsi + +/* ========================================================================== + Assembly Syntax: Rdd32=vabsh(Rss32) + C Intrinsic Prototype: Word64 Q6_P_vabsh_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vabsh_P __builtin_HEXAGON_A2_vabsh + +/* ========================================================================== + Assembly Syntax: Rdd32=vabsh(Rss32):sat + C Intrinsic Prototype: Word64 Q6_P_vabsh_P_sat(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vabsh_P_sat __builtin_HEXAGON_A2_vabshsat + +/* ========================================================================== + Assembly Syntax: Rdd32=vabsw(Rss32) + C Intrinsic Prototype: Word64 Q6_P_vabsw_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vabsw_P __builtin_HEXAGON_A2_vabsw + +/* ========================================================================== + Assembly Syntax: Rdd32=vabsw(Rss32):sat + C Intrinsic Prototype: Word64 Q6_P_vabsw_P_sat(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vabsw_P_sat __builtin_HEXAGON_A2_vabswsat + +/* ========================================================================== + Assembly Syntax: Rdd32=vaddb(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vaddb_PP(Word64 Rss, Word64 Rtt) + Instruction Type: MAPPING + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_vaddb_PP __builtin_HEXAGON_A2_vaddb_map + +/* ========================================================================== + Assembly Syntax: Rdd32=vaddh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vaddh_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vaddh_PP __builtin_HEXAGON_A2_vaddh + +/* ========================================================================== + Assembly Syntax: Rdd32=vaddh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vaddh_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vaddh_PP_sat __builtin_HEXAGON_A2_vaddhs + +/* ========================================================================== + Assembly Syntax: Rdd32=vaddub(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vaddub_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vaddub_PP __builtin_HEXAGON_A2_vaddub + +/* ========================================================================== + Assembly Syntax: Rdd32=vaddub(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vaddub_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vaddub_PP_sat __builtin_HEXAGON_A2_vaddubs + +/* ========================================================================== + Assembly Syntax: Rdd32=vadduh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vadduh_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vadduh_PP_sat __builtin_HEXAGON_A2_vadduhs + +/* ========================================================================== + Assembly Syntax: Rdd32=vaddw(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vaddw_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vaddw_PP __builtin_HEXAGON_A2_vaddw + +/* ========================================================================== + Assembly Syntax: Rdd32=vaddw(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vaddw_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vaddw_PP_sat __builtin_HEXAGON_A2_vaddws + +/* ========================================================================== + Assembly Syntax: Rdd32=vavgh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vavgh_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavgh_PP __builtin_HEXAGON_A2_vavgh + +/* ========================================================================== + Assembly Syntax: Rdd32=vavgh(Rss32,Rtt32):crnd + C Intrinsic Prototype: Word64 Q6_P_vavgh_PP_crnd(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavgh_PP_crnd __builtin_HEXAGON_A2_vavghcr + +/* ========================================================================== + Assembly Syntax: Rdd32=vavgh(Rss32,Rtt32):rnd + C Intrinsic Prototype: Word64 Q6_P_vavgh_PP_rnd(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavgh_PP_rnd __builtin_HEXAGON_A2_vavghr + +/* ========================================================================== + Assembly Syntax: Rdd32=vavgub(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vavgub_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavgub_PP __builtin_HEXAGON_A2_vavgub + +/* ========================================================================== + Assembly Syntax: Rdd32=vavgub(Rss32,Rtt32):rnd + C Intrinsic Prototype: Word64 Q6_P_vavgub_PP_rnd(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavgub_PP_rnd __builtin_HEXAGON_A2_vavgubr + +/* ========================================================================== + Assembly Syntax: Rdd32=vavguh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vavguh_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavguh_PP __builtin_HEXAGON_A2_vavguh + +/* ========================================================================== + Assembly Syntax: Rdd32=vavguh(Rss32,Rtt32):rnd + C Intrinsic Prototype: Word64 Q6_P_vavguh_PP_rnd(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavguh_PP_rnd __builtin_HEXAGON_A2_vavguhr + +/* ========================================================================== + Assembly Syntax: Rdd32=vavguw(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vavguw_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavguw_PP __builtin_HEXAGON_A2_vavguw + +/* ========================================================================== + Assembly Syntax: Rdd32=vavguw(Rss32,Rtt32):rnd + C Intrinsic Prototype: Word64 Q6_P_vavguw_PP_rnd(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavguw_PP_rnd __builtin_HEXAGON_A2_vavguwr + +/* ========================================================================== + Assembly Syntax: Rdd32=vavgw(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vavgw_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavgw_PP __builtin_HEXAGON_A2_vavgw + +/* ========================================================================== + Assembly Syntax: Rdd32=vavgw(Rss32,Rtt32):crnd + C Intrinsic Prototype: Word64 Q6_P_vavgw_PP_crnd(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavgw_PP_crnd __builtin_HEXAGON_A2_vavgwcr + +/* ========================================================================== + Assembly Syntax: Rdd32=vavgw(Rss32,Rtt32):rnd + C Intrinsic Prototype: Word64 Q6_P_vavgw_PP_rnd(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavgw_PP_rnd __builtin_HEXAGON_A2_vavgwr + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpb.eq(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_vcmpb_eq_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpb_eq_PP __builtin_HEXAGON_A2_vcmpbeq + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpb.gtu(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_vcmpb_gtu_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpb_gtu_PP __builtin_HEXAGON_A2_vcmpbgtu + +/* ========================================================================== + Assembly Syntax: Pd4=vcmph.eq(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_vcmph_eq_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmph_eq_PP __builtin_HEXAGON_A2_vcmpheq + +/* ========================================================================== + Assembly Syntax: Pd4=vcmph.gt(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_vcmph_gt_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmph_gt_PP __builtin_HEXAGON_A2_vcmphgt + +/* ========================================================================== + Assembly Syntax: Pd4=vcmph.gtu(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_vcmph_gtu_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmph_gtu_PP __builtin_HEXAGON_A2_vcmphgtu + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpw.eq(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_vcmpw_eq_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpw_eq_PP __builtin_HEXAGON_A2_vcmpweq + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpw.gt(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_vcmpw_gt_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpw_gt_PP __builtin_HEXAGON_A2_vcmpwgt + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpw.gtu(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_vcmpw_gtu_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpw_gtu_PP __builtin_HEXAGON_A2_vcmpwgtu + +/* ========================================================================== + Assembly Syntax: Rdd32=vconj(Rss32):sat + C Intrinsic Prototype: Word64 Q6_P_vconj_P_sat(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vconj_P_sat __builtin_HEXAGON_A2_vconj + +/* ========================================================================== + Assembly Syntax: Rdd32=vmaxb(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vmaxb_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmaxb_PP __builtin_HEXAGON_A2_vmaxb + +/* ========================================================================== + Assembly Syntax: Rdd32=vmaxh(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vmaxh_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmaxh_PP __builtin_HEXAGON_A2_vmaxh + +/* ========================================================================== + Assembly Syntax: Rdd32=vmaxub(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vmaxub_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmaxub_PP __builtin_HEXAGON_A2_vmaxub + +/* ========================================================================== + Assembly Syntax: Rdd32=vmaxuh(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vmaxuh_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmaxuh_PP __builtin_HEXAGON_A2_vmaxuh + +/* ========================================================================== + Assembly Syntax: Rdd32=vmaxuw(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vmaxuw_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmaxuw_PP __builtin_HEXAGON_A2_vmaxuw + +/* ========================================================================== + Assembly Syntax: Rdd32=vmaxw(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vmaxw_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmaxw_PP __builtin_HEXAGON_A2_vmaxw + +/* ========================================================================== + Assembly Syntax: Rdd32=vminb(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vminb_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vminb_PP __builtin_HEXAGON_A2_vminb + +/* ========================================================================== + Assembly Syntax: Rdd32=vminh(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vminh_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vminh_PP __builtin_HEXAGON_A2_vminh + +/* ========================================================================== + Assembly Syntax: Rdd32=vminub(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vminub_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vminub_PP __builtin_HEXAGON_A2_vminub + +/* ========================================================================== + Assembly Syntax: Rdd32=vminuh(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vminuh_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vminuh_PP __builtin_HEXAGON_A2_vminuh + +/* ========================================================================== + Assembly Syntax: Rdd32=vminuw(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vminuw_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vminuw_PP __builtin_HEXAGON_A2_vminuw + +/* ========================================================================== + Assembly Syntax: Rdd32=vminw(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vminw_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vminw_PP __builtin_HEXAGON_A2_vminw + +/* ========================================================================== + Assembly Syntax: Rdd32=vnavgh(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vnavgh_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vnavgh_PP __builtin_HEXAGON_A2_vnavgh + +/* ========================================================================== + Assembly Syntax: Rdd32=vnavgh(Rtt32,Rss32):crnd:sat + C Intrinsic Prototype: Word64 Q6_P_vnavgh_PP_crnd_sat(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vnavgh_PP_crnd_sat __builtin_HEXAGON_A2_vnavghcr + +/* ========================================================================== + Assembly Syntax: Rdd32=vnavgh(Rtt32,Rss32):rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vnavgh_PP_rnd_sat(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vnavgh_PP_rnd_sat __builtin_HEXAGON_A2_vnavghr + +/* ========================================================================== + Assembly Syntax: Rdd32=vnavgw(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vnavgw_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vnavgw_PP __builtin_HEXAGON_A2_vnavgw + +/* ========================================================================== + Assembly Syntax: Rdd32=vnavgw(Rtt32,Rss32):crnd:sat + C Intrinsic Prototype: Word64 Q6_P_vnavgw_PP_crnd_sat(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vnavgw_PP_crnd_sat __builtin_HEXAGON_A2_vnavgwcr + +/* ========================================================================== + Assembly Syntax: Rdd32=vnavgw(Rtt32,Rss32):rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vnavgw_PP_rnd_sat(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vnavgw_PP_rnd_sat __builtin_HEXAGON_A2_vnavgwr + +/* ========================================================================== + Assembly Syntax: Rdd32=vraddub(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vraddub_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vraddub_PP __builtin_HEXAGON_A2_vraddub + +/* ========================================================================== + Assembly Syntax: Rxx32+=vraddub(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vraddubacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vraddubacc_PP __builtin_HEXAGON_A2_vraddub_acc + +/* ========================================================================== + Assembly Syntax: Rdd32=vrsadub(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrsadub_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrsadub_PP __builtin_HEXAGON_A2_vrsadub + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrsadub(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrsadubacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrsadubacc_PP __builtin_HEXAGON_A2_vrsadub_acc + +/* ========================================================================== + Assembly Syntax: Rdd32=vsubb(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vsubb_PP(Word64 Rss, Word64 Rtt) + Instruction Type: MAPPING + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_vsubb_PP __builtin_HEXAGON_A2_vsubb_map + +/* ========================================================================== + Assembly Syntax: Rdd32=vsubh(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vsubh_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsubh_PP __builtin_HEXAGON_A2_vsubh + +/* ========================================================================== + Assembly Syntax: Rdd32=vsubh(Rtt32,Rss32):sat + C Intrinsic Prototype: Word64 Q6_P_vsubh_PP_sat(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsubh_PP_sat __builtin_HEXAGON_A2_vsubhs + +/* ========================================================================== + Assembly Syntax: Rdd32=vsubub(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vsubub_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsubub_PP __builtin_HEXAGON_A2_vsubub + +/* ========================================================================== + Assembly Syntax: Rdd32=vsubub(Rtt32,Rss32):sat + C Intrinsic Prototype: Word64 Q6_P_vsubub_PP_sat(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsubub_PP_sat __builtin_HEXAGON_A2_vsububs + +/* ========================================================================== + Assembly Syntax: Rdd32=vsubuh(Rtt32,Rss32):sat + C Intrinsic Prototype: Word64 Q6_P_vsubuh_PP_sat(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsubuh_PP_sat __builtin_HEXAGON_A2_vsubuhs + +/* ========================================================================== + Assembly Syntax: Rdd32=vsubw(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vsubw_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsubw_PP __builtin_HEXAGON_A2_vsubw + +/* ========================================================================== + Assembly Syntax: Rdd32=vsubw(Rtt32,Rss32):sat + C Intrinsic Prototype: Word64 Q6_P_vsubw_PP_sat(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsubw_PP_sat __builtin_HEXAGON_A2_vsubws + +/* ========================================================================== + Assembly Syntax: Rd32=xor(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_xor_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_xor_RR __builtin_HEXAGON_A2_xor + +/* ========================================================================== + Assembly Syntax: Rdd32=xor(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_xor_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_xor_PP __builtin_HEXAGON_A2_xorp + +/* ========================================================================== + Assembly Syntax: Rd32=zxtb(Rs32) + C Intrinsic Prototype: Word32 Q6_R_zxtb_R(Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_zxtb_R __builtin_HEXAGON_A2_zxtb + +/* ========================================================================== + Assembly Syntax: Rd32=zxth(Rs32) + C Intrinsic Prototype: Word32 Q6_R_zxth_R(Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_zxth_R __builtin_HEXAGON_A2_zxth + +/* ========================================================================== + Assembly Syntax: Rd32=and(Rt32,~Rs32) + C Intrinsic Prototype: Word32 Q6_R_and_RnR(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_and_RnR __builtin_HEXAGON_A4_andn + +/* ========================================================================== + Assembly Syntax: Rdd32=and(Rtt32,~Rss32) + C Intrinsic Prototype: Word64 Q6_P_and_PnP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_and_PnP __builtin_HEXAGON_A4_andnp + +/* ========================================================================== + Assembly Syntax: Rdd32=bitsplit(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_bitsplit_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_bitsplit_RR __builtin_HEXAGON_A4_bitsplit + +/* ========================================================================== + Assembly Syntax: Rdd32=bitsplit(Rs32,#u5) + C Intrinsic Prototype: Word64 Q6_P_bitsplit_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_bitsplit_RI __builtin_HEXAGON_A4_bitspliti + +/* ========================================================================== + Assembly Syntax: Pd4=boundscheck(Rs32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_boundscheck_RP(Word32 Rs, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_boundscheck_RP __builtin_HEXAGON_A4_boundscheck + +/* ========================================================================== + Assembly Syntax: Pd4=cmpb.eq(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_cmpb_eq_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmpb_eq_RR __builtin_HEXAGON_A4_cmpbeq + +/* ========================================================================== + Assembly Syntax: Pd4=cmpb.eq(Rs32,#u8) + C Intrinsic Prototype: Byte Q6_p_cmpb_eq_RI(Word32 Rs, Word32 Iu8) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmpb_eq_RI __builtin_HEXAGON_A4_cmpbeqi + +/* ========================================================================== + Assembly Syntax: Pd4=cmpb.gt(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_cmpb_gt_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmpb_gt_RR __builtin_HEXAGON_A4_cmpbgt + +/* ========================================================================== + Assembly Syntax: Pd4=cmpb.gt(Rs32,#s8) + C Intrinsic Prototype: Byte Q6_p_cmpb_gt_RI(Word32 Rs, Word32 Is8) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmpb_gt_RI __builtin_HEXAGON_A4_cmpbgti + +/* ========================================================================== + Assembly Syntax: Pd4=cmpb.gtu(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_cmpb_gtu_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmpb_gtu_RR __builtin_HEXAGON_A4_cmpbgtu + +/* ========================================================================== + Assembly Syntax: Pd4=cmpb.gtu(Rs32,#u7) + C Intrinsic Prototype: Byte Q6_p_cmpb_gtu_RI(Word32 Rs, Word32 Iu7) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmpb_gtu_RI __builtin_HEXAGON_A4_cmpbgtui + +/* ========================================================================== + Assembly Syntax: Pd4=cmph.eq(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_cmph_eq_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmph_eq_RR __builtin_HEXAGON_A4_cmpheq + +/* ========================================================================== + Assembly Syntax: Pd4=cmph.eq(Rs32,#s8) + C Intrinsic Prototype: Byte Q6_p_cmph_eq_RI(Word32 Rs, Word32 Is8) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmph_eq_RI __builtin_HEXAGON_A4_cmpheqi + +/* ========================================================================== + Assembly Syntax: Pd4=cmph.gt(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_cmph_gt_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmph_gt_RR __builtin_HEXAGON_A4_cmphgt + +/* ========================================================================== + Assembly Syntax: Pd4=cmph.gt(Rs32,#s8) + C Intrinsic Prototype: Byte Q6_p_cmph_gt_RI(Word32 Rs, Word32 Is8) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmph_gt_RI __builtin_HEXAGON_A4_cmphgti + +/* ========================================================================== + Assembly Syntax: Pd4=cmph.gtu(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_cmph_gtu_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmph_gtu_RR __builtin_HEXAGON_A4_cmphgtu + +/* ========================================================================== + Assembly Syntax: Pd4=cmph.gtu(Rs32,#u7) + C Intrinsic Prototype: Byte Q6_p_cmph_gtu_RI(Word32 Rs, Word32 Iu7) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmph_gtu_RI __builtin_HEXAGON_A4_cmphgtui + +/* ========================================================================== + Assembly Syntax: Rdd32=combine(#s8,Rs32) + C Intrinsic Prototype: Word64 Q6_P_combine_IR(Word32 Is8, Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_combine_IR __builtin_HEXAGON_A4_combineir + +/* ========================================================================== + Assembly Syntax: Rdd32=combine(Rs32,#s8) + C Intrinsic Prototype: Word64 Q6_P_combine_RI(Word32 Rs, Word32 Is8) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_combine_RI __builtin_HEXAGON_A4_combineri + +/* ========================================================================== + Assembly Syntax: Rd32=cround(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_cround_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cround_RI __builtin_HEXAGON_A4_cround_ri + +/* ========================================================================== + Assembly Syntax: Rd32=cround(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_cround_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cround_RR __builtin_HEXAGON_A4_cround_rr + +/* ========================================================================== + Assembly Syntax: Rd32=modwrap(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_modwrap_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_modwrap_RR __builtin_HEXAGON_A4_modwrapu + +/* ========================================================================== + Assembly Syntax: Rd32=or(Rt32,~Rs32) + C Intrinsic Prototype: Word32 Q6_R_or_RnR(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_or_RnR __builtin_HEXAGON_A4_orn + +/* ========================================================================== + Assembly Syntax: Rdd32=or(Rtt32,~Rss32) + C Intrinsic Prototype: Word64 Q6_P_or_PnP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_or_PnP __builtin_HEXAGON_A4_ornp + +/* ========================================================================== + Assembly Syntax: Rd32=cmp.eq(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_cmp_eq_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_cmp_eq_RR __builtin_HEXAGON_A4_rcmpeq + +/* ========================================================================== + Assembly Syntax: Rd32=cmp.eq(Rs32,#s8) + C Intrinsic Prototype: Word32 Q6_R_cmp_eq_RI(Word32 Rs, Word32 Is8) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_cmp_eq_RI __builtin_HEXAGON_A4_rcmpeqi + +/* ========================================================================== + Assembly Syntax: Rd32=!cmp.eq(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_not_cmp_eq_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_not_cmp_eq_RR __builtin_HEXAGON_A4_rcmpneq + +/* ========================================================================== + Assembly Syntax: Rd32=!cmp.eq(Rs32,#s8) + C Intrinsic Prototype: Word32 Q6_R_not_cmp_eq_RI(Word32 Rs, Word32 Is8) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_not_cmp_eq_RI __builtin_HEXAGON_A4_rcmpneqi + +/* ========================================================================== + Assembly Syntax: Rd32=round(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_round_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_round_RI __builtin_HEXAGON_A4_round_ri + +/* ========================================================================== + Assembly Syntax: Rd32=round(Rs32,#u5):sat + C Intrinsic Prototype: Word32 Q6_R_round_RI_sat(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_round_RI_sat __builtin_HEXAGON_A4_round_ri_sat + +/* ========================================================================== + Assembly Syntax: Rd32=round(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_round_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_round_RR __builtin_HEXAGON_A4_round_rr + +/* ========================================================================== + Assembly Syntax: Rd32=round(Rs32,Rt32):sat + C Intrinsic Prototype: Word32 Q6_R_round_RR_sat(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_round_RR_sat __builtin_HEXAGON_A4_round_rr_sat + +/* ========================================================================== + Assembly Syntax: Pd4=tlbmatch(Rss32,Rt32) + C Intrinsic Prototype: Byte Q6_p_tlbmatch_PR(Word64 Rss, Word32 Rt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_tlbmatch_PR __builtin_HEXAGON_A4_tlbmatch + +/* ========================================================================== + Assembly Syntax: Pd4=any8(vcmpb.eq(Rss32,Rtt32)) + C Intrinsic Prototype: Byte Q6_p_any8_vcmpb_eq_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_any8_vcmpb_eq_PP __builtin_HEXAGON_A4_vcmpbeq_any + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpb.eq(Rss32,#u8) + C Intrinsic Prototype: Byte Q6_p_vcmpb_eq_PI(Word64 Rss, Word32 Iu8) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpb_eq_PI __builtin_HEXAGON_A4_vcmpbeqi + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpb.gt(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_vcmpb_gt_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpb_gt_PP __builtin_HEXAGON_A4_vcmpbgt + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpb.gt(Rss32,#s8) + C Intrinsic Prototype: Byte Q6_p_vcmpb_gt_PI(Word64 Rss, Word32 Is8) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpb_gt_PI __builtin_HEXAGON_A4_vcmpbgti + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpb.gtu(Rss32,#u7) + C Intrinsic Prototype: Byte Q6_p_vcmpb_gtu_PI(Word64 Rss, Word32 Iu7) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpb_gtu_PI __builtin_HEXAGON_A4_vcmpbgtui + +/* ========================================================================== + Assembly Syntax: Pd4=vcmph.eq(Rss32,#s8) + C Intrinsic Prototype: Byte Q6_p_vcmph_eq_PI(Word64 Rss, Word32 Is8) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmph_eq_PI __builtin_HEXAGON_A4_vcmpheqi + +/* ========================================================================== + Assembly Syntax: Pd4=vcmph.gt(Rss32,#s8) + C Intrinsic Prototype: Byte Q6_p_vcmph_gt_PI(Word64 Rss, Word32 Is8) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmph_gt_PI __builtin_HEXAGON_A4_vcmphgti + +/* ========================================================================== + Assembly Syntax: Pd4=vcmph.gtu(Rss32,#u7) + C Intrinsic Prototype: Byte Q6_p_vcmph_gtu_PI(Word64 Rss, Word32 Iu7) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmph_gtu_PI __builtin_HEXAGON_A4_vcmphgtui + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpw.eq(Rss32,#s8) + C Intrinsic Prototype: Byte Q6_p_vcmpw_eq_PI(Word64 Rss, Word32 Is8) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpw_eq_PI __builtin_HEXAGON_A4_vcmpweqi + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpw.gt(Rss32,#s8) + C Intrinsic Prototype: Byte Q6_p_vcmpw_gt_PI(Word64 Rss, Word32 Is8) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpw_gt_PI __builtin_HEXAGON_A4_vcmpwgti + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpw.gtu(Rss32,#u7) + C Intrinsic Prototype: Byte Q6_p_vcmpw_gtu_PI(Word64 Rss, Word32 Iu7) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpw_gtu_PI __builtin_HEXAGON_A4_vcmpwgtui + +/* ========================================================================== + Assembly Syntax: Rxx32=vrmaxh(Rss32,Ru32) + C Intrinsic Prototype: Word64 Q6_P_vrmaxh_PR(Word64 Rxx, Word64 Rss, Word32 Ru) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmaxh_PR __builtin_HEXAGON_A4_vrmaxh + +/* ========================================================================== + Assembly Syntax: Rxx32=vrmaxuh(Rss32,Ru32) + C Intrinsic Prototype: Word64 Q6_P_vrmaxuh_PR(Word64 Rxx, Word64 Rss, Word32 Ru) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmaxuh_PR __builtin_HEXAGON_A4_vrmaxuh + +/* ========================================================================== + Assembly Syntax: Rxx32=vrmaxuw(Rss32,Ru32) + C Intrinsic Prototype: Word64 Q6_P_vrmaxuw_PR(Word64 Rxx, Word64 Rss, Word32 Ru) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmaxuw_PR __builtin_HEXAGON_A4_vrmaxuw + +/* ========================================================================== + Assembly Syntax: Rxx32=vrmaxw(Rss32,Ru32) + C Intrinsic Prototype: Word64 Q6_P_vrmaxw_PR(Word64 Rxx, Word64 Rss, Word32 Ru) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmaxw_PR __builtin_HEXAGON_A4_vrmaxw + +/* ========================================================================== + Assembly Syntax: Rxx32=vrminh(Rss32,Ru32) + C Intrinsic Prototype: Word64 Q6_P_vrminh_PR(Word64 Rxx, Word64 Rss, Word32 Ru) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrminh_PR __builtin_HEXAGON_A4_vrminh + +/* ========================================================================== + Assembly Syntax: Rxx32=vrminuh(Rss32,Ru32) + C Intrinsic Prototype: Word64 Q6_P_vrminuh_PR(Word64 Rxx, Word64 Rss, Word32 Ru) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrminuh_PR __builtin_HEXAGON_A4_vrminuh + +/* ========================================================================== + Assembly Syntax: Rxx32=vrminuw(Rss32,Ru32) + C Intrinsic Prototype: Word64 Q6_P_vrminuw_PR(Word64 Rxx, Word64 Rss, Word32 Ru) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrminuw_PR __builtin_HEXAGON_A4_vrminuw + +/* ========================================================================== + Assembly Syntax: Rxx32=vrminw(Rss32,Ru32) + C Intrinsic Prototype: Word64 Q6_P_vrminw_PR(Word64 Rxx, Word64 Rss, Word32 Ru) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrminw_PR __builtin_HEXAGON_A4_vrminw + +/* ========================================================================== + Assembly Syntax: Rd32=vaddhub(Rss32,Rtt32):sat + C Intrinsic Prototype: Word32 Q6_R_vaddhub_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vaddhub_PP_sat __builtin_HEXAGON_A5_vaddhubs + +/* ========================================================================== + Assembly Syntax: Pd4=all8(Ps4) + C Intrinsic Prototype: Byte Q6_p_all8_p(Byte Ps) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_all8_p __builtin_HEXAGON_C2_all8 + +/* ========================================================================== + Assembly Syntax: Pd4=and(Pt4,Ps4) + C Intrinsic Prototype: Byte Q6_p_and_pp(Byte Pt, Byte Ps) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_and_pp __builtin_HEXAGON_C2_and + +/* ========================================================================== + Assembly Syntax: Pd4=and(Pt4,!Ps4) + C Intrinsic Prototype: Byte Q6_p_and_pnp(Byte Pt, Byte Ps) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_and_pnp __builtin_HEXAGON_C2_andn + +/* ========================================================================== + Assembly Syntax: Pd4=any8(Ps4) + C Intrinsic Prototype: Byte Q6_p_any8_p(Byte Ps) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_any8_p __builtin_HEXAGON_C2_any8 + +/* ========================================================================== + Assembly Syntax: Pd4=bitsclr(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_bitsclr_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_bitsclr_RR __builtin_HEXAGON_C2_bitsclr + +/* ========================================================================== + Assembly Syntax: Pd4=bitsclr(Rs32,#u6) + C Intrinsic Prototype: Byte Q6_p_bitsclr_RI(Word32 Rs, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_bitsclr_RI __builtin_HEXAGON_C2_bitsclri + +/* ========================================================================== + Assembly Syntax: Pd4=bitsset(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_bitsset_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_bitsset_RR __builtin_HEXAGON_C2_bitsset + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.eq(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_cmp_eq_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_cmp_eq_RR __builtin_HEXAGON_C2_cmpeq + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.eq(Rs32,#s10) + C Intrinsic Prototype: Byte Q6_p_cmp_eq_RI(Word32 Rs, Word32 Is10) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_cmp_eq_RI __builtin_HEXAGON_C2_cmpeqi + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.eq(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_cmp_eq_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmp_eq_PP __builtin_HEXAGON_C2_cmpeqp + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.ge(Rs32,#s8) + C Intrinsic Prototype: Byte Q6_p_cmp_ge_RI(Word32 Rs, Word32 Is8) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_cmp_ge_RI __builtin_HEXAGON_C2_cmpgei + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.geu(Rs32,#u8) + C Intrinsic Prototype: Byte Q6_p_cmp_geu_RI(Word32 Rs, Word32 Iu8) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_cmp_geu_RI __builtin_HEXAGON_C2_cmpgeui + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.gt(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_cmp_gt_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_cmp_gt_RR __builtin_HEXAGON_C2_cmpgt + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.gt(Rs32,#s10) + C Intrinsic Prototype: Byte Q6_p_cmp_gt_RI(Word32 Rs, Word32 Is10) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_cmp_gt_RI __builtin_HEXAGON_C2_cmpgti + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.gt(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_cmp_gt_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmp_gt_PP __builtin_HEXAGON_C2_cmpgtp + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.gtu(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_cmp_gtu_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_cmp_gtu_RR __builtin_HEXAGON_C2_cmpgtu + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.gtu(Rs32,#u9) + C Intrinsic Prototype: Byte Q6_p_cmp_gtu_RI(Word32 Rs, Word32 Iu9) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_cmp_gtu_RI __builtin_HEXAGON_C2_cmpgtui + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.gtu(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_cmp_gtu_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmp_gtu_PP __builtin_HEXAGON_C2_cmpgtup + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.lt(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_cmp_lt_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_cmp_lt_RR __builtin_HEXAGON_C2_cmplt + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.ltu(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_cmp_ltu_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_cmp_ltu_RR __builtin_HEXAGON_C2_cmpltu + +/* ========================================================================== + Assembly Syntax: Rdd32=mask(Pt4) + C Intrinsic Prototype: Word64 Q6_P_mask_p(Byte Pt) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mask_p __builtin_HEXAGON_C2_mask + +/* ========================================================================== + Assembly Syntax: Rd32=mux(Pu4,Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_mux_pRR(Byte Pu, Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_mux_pRR __builtin_HEXAGON_C2_mux + +/* ========================================================================== + Assembly Syntax: Rd32=mux(Pu4,#s8,#S8) + C Intrinsic Prototype: Word32 Q6_R_mux_pII(Byte Pu, Word32 Is8, Word32 IS8) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_mux_pII __builtin_HEXAGON_C2_muxii + +/* ========================================================================== + Assembly Syntax: Rd32=mux(Pu4,Rs32,#s8) + C Intrinsic Prototype: Word32 Q6_R_mux_pRI(Byte Pu, Word32 Rs, Word32 Is8) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_mux_pRI __builtin_HEXAGON_C2_muxir + +/* ========================================================================== + Assembly Syntax: Rd32=mux(Pu4,#s8,Rs32) + C Intrinsic Prototype: Word32 Q6_R_mux_pIR(Byte Pu, Word32 Is8, Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_mux_pIR __builtin_HEXAGON_C2_muxri + +/* ========================================================================== + Assembly Syntax: Pd4=not(Ps4) + C Intrinsic Prototype: Byte Q6_p_not_p(Byte Ps) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_not_p __builtin_HEXAGON_C2_not + +/* ========================================================================== + Assembly Syntax: Pd4=or(Pt4,Ps4) + C Intrinsic Prototype: Byte Q6_p_or_pp(Byte Pt, Byte Ps) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_or_pp __builtin_HEXAGON_C2_or + +/* ========================================================================== + Assembly Syntax: Pd4=or(Pt4,!Ps4) + C Intrinsic Prototype: Byte Q6_p_or_pnp(Byte Pt, Byte Ps) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_or_pnp __builtin_HEXAGON_C2_orn + +/* ========================================================================== + Assembly Syntax: Pd4=Ps4 + C Intrinsic Prototype: Byte Q6_p_equals_p(Byte Ps) + Instruction Type: MAPPING + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_equals_p __builtin_HEXAGON_C2_pxfer_map + +/* ========================================================================== + Assembly Syntax: Rd32=Ps4 + C Intrinsic Prototype: Word32 Q6_R_equals_p(Byte Ps) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_equals_p __builtin_HEXAGON_C2_tfrpr + +/* ========================================================================== + Assembly Syntax: Pd4=Rs32 + C Intrinsic Prototype: Byte Q6_p_equals_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_equals_R __builtin_HEXAGON_C2_tfrrp + +/* ========================================================================== + Assembly Syntax: Rd32=vitpack(Ps4,Pt4) + C Intrinsic Prototype: Word32 Q6_R_vitpack_pp(Byte Ps, Byte Pt) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vitpack_pp __builtin_HEXAGON_C2_vitpack + +/* ========================================================================== + Assembly Syntax: Rdd32=vmux(Pu4,Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vmux_pPP(Byte Pu, Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmux_pPP __builtin_HEXAGON_C2_vmux + +/* ========================================================================== + Assembly Syntax: Pd4=xor(Ps4,Pt4) + C Intrinsic Prototype: Byte Q6_p_xor_pp(Byte Ps, Byte Pt) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_xor_pp __builtin_HEXAGON_C2_xor + +/* ========================================================================== + Assembly Syntax: Pd4=and(Ps4,and(Pt4,Pu4)) + C Intrinsic Prototype: Byte Q6_p_and_and_ppp(Byte Ps, Byte Pt, Byte Pu) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_and_and_ppp __builtin_HEXAGON_C4_and_and + +/* ========================================================================== + Assembly Syntax: Pd4=and(Ps4,and(Pt4,!Pu4)) + C Intrinsic Prototype: Byte Q6_p_and_and_ppnp(Byte Ps, Byte Pt, Byte Pu) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_and_and_ppnp __builtin_HEXAGON_C4_and_andn + +/* ========================================================================== + Assembly Syntax: Pd4=and(Ps4,or(Pt4,Pu4)) + C Intrinsic Prototype: Byte Q6_p_and_or_ppp(Byte Ps, Byte Pt, Byte Pu) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_and_or_ppp __builtin_HEXAGON_C4_and_or + +/* ========================================================================== + Assembly Syntax: Pd4=and(Ps4,or(Pt4,!Pu4)) + C Intrinsic Prototype: Byte Q6_p_and_or_ppnp(Byte Ps, Byte Pt, Byte Pu) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_and_or_ppnp __builtin_HEXAGON_C4_and_orn + +/* ========================================================================== + Assembly Syntax: Pd4=!cmp.gt(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_not_cmp_gt_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_not_cmp_gt_RR __builtin_HEXAGON_C4_cmplte + +/* ========================================================================== + Assembly Syntax: Pd4=!cmp.gt(Rs32,#s10) + C Intrinsic Prototype: Byte Q6_p_not_cmp_gt_RI(Word32 Rs, Word32 Is10) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_not_cmp_gt_RI __builtin_HEXAGON_C4_cmpltei + +/* ========================================================================== + Assembly Syntax: Pd4=!cmp.gtu(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_not_cmp_gtu_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_not_cmp_gtu_RR __builtin_HEXAGON_C4_cmplteu + +/* ========================================================================== + Assembly Syntax: Pd4=!cmp.gtu(Rs32,#u9) + C Intrinsic Prototype: Byte Q6_p_not_cmp_gtu_RI(Word32 Rs, Word32 Iu9) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_not_cmp_gtu_RI __builtin_HEXAGON_C4_cmplteui + +/* ========================================================================== + Assembly Syntax: Pd4=!cmp.eq(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_not_cmp_eq_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_not_cmp_eq_RR __builtin_HEXAGON_C4_cmpneq + +/* ========================================================================== + Assembly Syntax: Pd4=!cmp.eq(Rs32,#s10) + C Intrinsic Prototype: Byte Q6_p_not_cmp_eq_RI(Word32 Rs, Word32 Is10) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_not_cmp_eq_RI __builtin_HEXAGON_C4_cmpneqi + +/* ========================================================================== + Assembly Syntax: Pd4=fastcorner9(Ps4,Pt4) + C Intrinsic Prototype: Byte Q6_p_fastcorner9_pp(Byte Ps, Byte Pt) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_fastcorner9_pp __builtin_HEXAGON_C4_fastcorner9 + +/* ========================================================================== + Assembly Syntax: Pd4=!fastcorner9(Ps4,Pt4) + C Intrinsic Prototype: Byte Q6_p_not_fastcorner9_pp(Byte Ps, Byte Pt) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_not_fastcorner9_pp __builtin_HEXAGON_C4_fastcorner9_not + +/* ========================================================================== + Assembly Syntax: Pd4=!bitsclr(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_not_bitsclr_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_not_bitsclr_RR __builtin_HEXAGON_C4_nbitsclr + +/* ========================================================================== + Assembly Syntax: Pd4=!bitsclr(Rs32,#u6) + C Intrinsic Prototype: Byte Q6_p_not_bitsclr_RI(Word32 Rs, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_not_bitsclr_RI __builtin_HEXAGON_C4_nbitsclri + +/* ========================================================================== + Assembly Syntax: Pd4=!bitsset(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_not_bitsset_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_not_bitsset_RR __builtin_HEXAGON_C4_nbitsset + +/* ========================================================================== + Assembly Syntax: Pd4=or(Ps4,and(Pt4,Pu4)) + C Intrinsic Prototype: Byte Q6_p_or_and_ppp(Byte Ps, Byte Pt, Byte Pu) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_or_and_ppp __builtin_HEXAGON_C4_or_and + +/* ========================================================================== + Assembly Syntax: Pd4=or(Ps4,and(Pt4,!Pu4)) + C Intrinsic Prototype: Byte Q6_p_or_and_ppnp(Byte Ps, Byte Pt, Byte Pu) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_or_and_ppnp __builtin_HEXAGON_C4_or_andn + +/* ========================================================================== + Assembly Syntax: Pd4=or(Ps4,or(Pt4,Pu4)) + C Intrinsic Prototype: Byte Q6_p_or_or_ppp(Byte Ps, Byte Pt, Byte Pu) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_or_or_ppp __builtin_HEXAGON_C4_or_or + +/* ========================================================================== + Assembly Syntax: Pd4=or(Ps4,or(Pt4,!Pu4)) + C Intrinsic Prototype: Byte Q6_p_or_or_ppnp(Byte Ps, Byte Pt, Byte Pu) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_or_or_ppnp __builtin_HEXAGON_C4_or_orn + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_d2df(Rss32) + C Intrinsic Prototype: Float64 Q6_P_convert_d2df_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_d2df_P __builtin_HEXAGON_F2_conv_d2df + +/* ========================================================================== + Assembly Syntax: Rd32=convert_d2sf(Rss32) + C Intrinsic Prototype: Float32 Q6_R_convert_d2sf_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_d2sf_P __builtin_HEXAGON_F2_conv_d2sf + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_df2d(Rss32) + C Intrinsic Prototype: Word64 Q6_P_convert_df2d_P(Float64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_df2d_P __builtin_HEXAGON_F2_conv_df2d + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_df2d(Rss32):chop + C Intrinsic Prototype: Word64 Q6_P_convert_df2d_P_chop(Float64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_df2d_P_chop __builtin_HEXAGON_F2_conv_df2d_chop + +/* ========================================================================== + Assembly Syntax: Rd32=convert_df2sf(Rss32) + C Intrinsic Prototype: Float32 Q6_R_convert_df2sf_P(Float64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_df2sf_P __builtin_HEXAGON_F2_conv_df2sf + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_df2ud(Rss32) + C Intrinsic Prototype: Word64 Q6_P_convert_df2ud_P(Float64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_df2ud_P __builtin_HEXAGON_F2_conv_df2ud + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_df2ud(Rss32):chop + C Intrinsic Prototype: Word64 Q6_P_convert_df2ud_P_chop(Float64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_df2ud_P_chop __builtin_HEXAGON_F2_conv_df2ud_chop + +/* ========================================================================== + Assembly Syntax: Rd32=convert_df2uw(Rss32) + C Intrinsic Prototype: Word32 Q6_R_convert_df2uw_P(Float64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_df2uw_P __builtin_HEXAGON_F2_conv_df2uw + +/* ========================================================================== + Assembly Syntax: Rd32=convert_df2uw(Rss32):chop + C Intrinsic Prototype: Word32 Q6_R_convert_df2uw_P_chop(Float64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_df2uw_P_chop __builtin_HEXAGON_F2_conv_df2uw_chop + +/* ========================================================================== + Assembly Syntax: Rd32=convert_df2w(Rss32) + C Intrinsic Prototype: Word32 Q6_R_convert_df2w_P(Float64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_df2w_P __builtin_HEXAGON_F2_conv_df2w + +/* ========================================================================== + Assembly Syntax: Rd32=convert_df2w(Rss32):chop + C Intrinsic Prototype: Word32 Q6_R_convert_df2w_P_chop(Float64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_df2w_P_chop __builtin_HEXAGON_F2_conv_df2w_chop + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_sf2d(Rs32) + C Intrinsic Prototype: Word64 Q6_P_convert_sf2d_R(Float32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_sf2d_R __builtin_HEXAGON_F2_conv_sf2d + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_sf2d(Rs32):chop + C Intrinsic Prototype: Word64 Q6_P_convert_sf2d_R_chop(Float32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_sf2d_R_chop __builtin_HEXAGON_F2_conv_sf2d_chop + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_sf2df(Rs32) + C Intrinsic Prototype: Float64 Q6_P_convert_sf2df_R(Float32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_sf2df_R __builtin_HEXAGON_F2_conv_sf2df + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_sf2ud(Rs32) + C Intrinsic Prototype: Word64 Q6_P_convert_sf2ud_R(Float32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_sf2ud_R __builtin_HEXAGON_F2_conv_sf2ud + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_sf2ud(Rs32):chop + C Intrinsic Prototype: Word64 Q6_P_convert_sf2ud_R_chop(Float32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_sf2ud_R_chop __builtin_HEXAGON_F2_conv_sf2ud_chop + +/* ========================================================================== + Assembly Syntax: Rd32=convert_sf2uw(Rs32) + C Intrinsic Prototype: Word32 Q6_R_convert_sf2uw_R(Float32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_sf2uw_R __builtin_HEXAGON_F2_conv_sf2uw + +/* ========================================================================== + Assembly Syntax: Rd32=convert_sf2uw(Rs32):chop + C Intrinsic Prototype: Word32 Q6_R_convert_sf2uw_R_chop(Float32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_sf2uw_R_chop __builtin_HEXAGON_F2_conv_sf2uw_chop + +/* ========================================================================== + Assembly Syntax: Rd32=convert_sf2w(Rs32) + C Intrinsic Prototype: Word32 Q6_R_convert_sf2w_R(Float32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_sf2w_R __builtin_HEXAGON_F2_conv_sf2w + +/* ========================================================================== + Assembly Syntax: Rd32=convert_sf2w(Rs32):chop + C Intrinsic Prototype: Word32 Q6_R_convert_sf2w_R_chop(Float32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_sf2w_R_chop __builtin_HEXAGON_F2_conv_sf2w_chop + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_ud2df(Rss32) + C Intrinsic Prototype: Float64 Q6_P_convert_ud2df_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_ud2df_P __builtin_HEXAGON_F2_conv_ud2df + +/* ========================================================================== + Assembly Syntax: Rd32=convert_ud2sf(Rss32) + C Intrinsic Prototype: Float32 Q6_R_convert_ud2sf_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_ud2sf_P __builtin_HEXAGON_F2_conv_ud2sf + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_uw2df(Rs32) + C Intrinsic Prototype: Float64 Q6_P_convert_uw2df_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_uw2df_R __builtin_HEXAGON_F2_conv_uw2df + +/* ========================================================================== + Assembly Syntax: Rd32=convert_uw2sf(Rs32) + C Intrinsic Prototype: Float32 Q6_R_convert_uw2sf_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_uw2sf_R __builtin_HEXAGON_F2_conv_uw2sf + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_w2df(Rs32) + C Intrinsic Prototype: Float64 Q6_P_convert_w2df_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_w2df_R __builtin_HEXAGON_F2_conv_w2df + +/* ========================================================================== + Assembly Syntax: Rd32=convert_w2sf(Rs32) + C Intrinsic Prototype: Float32 Q6_R_convert_w2sf_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_w2sf_R __builtin_HEXAGON_F2_conv_w2sf + +/* ========================================================================== + Assembly Syntax: Pd4=dfclass(Rss32,#u5) + C Intrinsic Prototype: Byte Q6_p_dfclass_PI(Float64 Rss, Word32 Iu5) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_dfclass_PI __builtin_HEXAGON_F2_dfclass + +/* ========================================================================== + Assembly Syntax: Pd4=dfcmp.eq(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_dfcmp_eq_PP(Float64 Rss, Float64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_dfcmp_eq_PP __builtin_HEXAGON_F2_dfcmpeq + +/* ========================================================================== + Assembly Syntax: Pd4=dfcmp.ge(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_dfcmp_ge_PP(Float64 Rss, Float64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_dfcmp_ge_PP __builtin_HEXAGON_F2_dfcmpge + +/* ========================================================================== + Assembly Syntax: Pd4=dfcmp.gt(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_dfcmp_gt_PP(Float64 Rss, Float64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_dfcmp_gt_PP __builtin_HEXAGON_F2_dfcmpgt + +/* ========================================================================== + Assembly Syntax: Pd4=dfcmp.uo(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_dfcmp_uo_PP(Float64 Rss, Float64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_dfcmp_uo_PP __builtin_HEXAGON_F2_dfcmpuo + +/* ========================================================================== + Assembly Syntax: Rdd32=dfmake(#u10):neg + C Intrinsic Prototype: Float64 Q6_P_dfmake_I_neg(Word32 Iu10) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_dfmake_I_neg __builtin_HEXAGON_F2_dfimm_n + +/* ========================================================================== + Assembly Syntax: Rdd32=dfmake(#u10):pos + C Intrinsic Prototype: Float64 Q6_P_dfmake_I_pos(Word32 Iu10) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_dfmake_I_pos __builtin_HEXAGON_F2_dfimm_p + +/* ========================================================================== + Assembly Syntax: Rd32=sfadd(Rs32,Rt32) + C Intrinsic Prototype: Float32 Q6_R_sfadd_RR(Float32 Rs, Float32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfadd_RR __builtin_HEXAGON_F2_sfadd + +/* ========================================================================== + Assembly Syntax: Pd4=sfclass(Rs32,#u5) + C Intrinsic Prototype: Byte Q6_p_sfclass_RI(Float32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_sfclass_RI __builtin_HEXAGON_F2_sfclass + +/* ========================================================================== + Assembly Syntax: Pd4=sfcmp.eq(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_sfcmp_eq_RR(Float32 Rs, Float32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_sfcmp_eq_RR __builtin_HEXAGON_F2_sfcmpeq + +/* ========================================================================== + Assembly Syntax: Pd4=sfcmp.ge(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_sfcmp_ge_RR(Float32 Rs, Float32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_sfcmp_ge_RR __builtin_HEXAGON_F2_sfcmpge + +/* ========================================================================== + Assembly Syntax: Pd4=sfcmp.gt(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_sfcmp_gt_RR(Float32 Rs, Float32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_sfcmp_gt_RR __builtin_HEXAGON_F2_sfcmpgt + +/* ========================================================================== + Assembly Syntax: Pd4=sfcmp.uo(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_sfcmp_uo_RR(Float32 Rs, Float32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_sfcmp_uo_RR __builtin_HEXAGON_F2_sfcmpuo + +/* ========================================================================== + Assembly Syntax: Rd32=sffixupd(Rs32,Rt32) + C Intrinsic Prototype: Float32 Q6_R_sffixupd_RR(Float32 Rs, Float32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sffixupd_RR __builtin_HEXAGON_F2_sffixupd + +/* ========================================================================== + Assembly Syntax: Rd32=sffixupn(Rs32,Rt32) + C Intrinsic Prototype: Float32 Q6_R_sffixupn_RR(Float32 Rs, Float32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sffixupn_RR __builtin_HEXAGON_F2_sffixupn + +/* ========================================================================== + Assembly Syntax: Rd32=sffixupr(Rs32) + C Intrinsic Prototype: Float32 Q6_R_sffixupr_R(Float32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sffixupr_R __builtin_HEXAGON_F2_sffixupr + +/* ========================================================================== + Assembly Syntax: Rx32+=sfmpy(Rs32,Rt32) + C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RR(Float32 Rx, Float32 Rs, Float32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfmpyacc_RR __builtin_HEXAGON_F2_sffma + +/* ========================================================================== + Assembly Syntax: Rx32+=sfmpy(Rs32,Rt32):lib + C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RR_lib(Float32 Rx, Float32 Rs, Float32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfmpyacc_RR_lib __builtin_HEXAGON_F2_sffma_lib + +/* ========================================================================== + Assembly Syntax: Rx32+=sfmpy(Rs32,Rt32,Pu4):scale + C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RRp_scale(Float32 Rx, Float32 Rs, Float32 Rt, Byte Pu) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfmpyacc_RRp_scale __builtin_HEXAGON_F2_sffma_sc + +/* ========================================================================== + Assembly Syntax: Rx32-=sfmpy(Rs32,Rt32) + C Intrinsic Prototype: Float32 Q6_R_sfmpynac_RR(Float32 Rx, Float32 Rs, Float32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfmpynac_RR __builtin_HEXAGON_F2_sffms + +/* ========================================================================== + Assembly Syntax: Rx32-=sfmpy(Rs32,Rt32):lib + C Intrinsic Prototype: Float32 Q6_R_sfmpynac_RR_lib(Float32 Rx, Float32 Rs, Float32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfmpynac_RR_lib __builtin_HEXAGON_F2_sffms_lib + +/* ========================================================================== + Assembly Syntax: Rd32=sfmake(#u10):neg + C Intrinsic Prototype: Float32 Q6_R_sfmake_I_neg(Word32 Iu10) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfmake_I_neg __builtin_HEXAGON_F2_sfimm_n + +/* ========================================================================== + Assembly Syntax: Rd32=sfmake(#u10):pos + C Intrinsic Prototype: Float32 Q6_R_sfmake_I_pos(Word32 Iu10) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfmake_I_pos __builtin_HEXAGON_F2_sfimm_p + +/* ========================================================================== + Assembly Syntax: Rd32=sfmax(Rs32,Rt32) + C Intrinsic Prototype: Float32 Q6_R_sfmax_RR(Float32 Rs, Float32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfmax_RR __builtin_HEXAGON_F2_sfmax + +/* ========================================================================== + Assembly Syntax: Rd32=sfmin(Rs32,Rt32) + C Intrinsic Prototype: Float32 Q6_R_sfmin_RR(Float32 Rs, Float32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfmin_RR __builtin_HEXAGON_F2_sfmin + +/* ========================================================================== + Assembly Syntax: Rd32=sfmpy(Rs32,Rt32) + C Intrinsic Prototype: Float32 Q6_R_sfmpy_RR(Float32 Rs, Float32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfmpy_RR __builtin_HEXAGON_F2_sfmpy + +/* ========================================================================== + Assembly Syntax: Rd32=sfsub(Rs32,Rt32) + C Intrinsic Prototype: Float32 Q6_R_sfsub_RR(Float32 Rs, Float32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfsub_RR __builtin_HEXAGON_F2_sfsub + +/* ========================================================================== + Assembly Syntax: Rd32=memb(Rx32++#s4:0:circ(Mu2)) + C Intrinsic Prototype: Word32 Q6_R_memb_IM_circ(void** Rx, Word32 Is4_0, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_R_memb_IM_circ __builtin_HEXAGON_L2_loadrb_pci + +/* ========================================================================== + Assembly Syntax: Rd32=memb(Rx32++I:circ(Mu2)) + C Intrinsic Prototype: Word32 Q6_R_memb_M_circ(void** Rx, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_R_memb_M_circ __builtin_HEXAGON_L2_loadrb_pcr + +/* ========================================================================== + Assembly Syntax: Rdd32=memd(Rx32++#s4:3:circ(Mu2)) + C Intrinsic Prototype: Word64 Q6_P_memd_IM_circ(void** Rx, Word32 Is4_3, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_P_memd_IM_circ __builtin_HEXAGON_L2_loadrd_pci + +/* ========================================================================== + Assembly Syntax: Rdd32=memd(Rx32++I:circ(Mu2)) + C Intrinsic Prototype: Word64 Q6_P_memd_M_circ(void** Rx, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_P_memd_M_circ __builtin_HEXAGON_L2_loadrd_pcr + +/* ========================================================================== + Assembly Syntax: Rd32=memh(Rx32++#s4:1:circ(Mu2)) + C Intrinsic Prototype: Word32 Q6_R_memh_IM_circ(void** Rx, Word32 Is4_1, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_R_memh_IM_circ __builtin_HEXAGON_L2_loadrh_pci + +/* ========================================================================== + Assembly Syntax: Rd32=memh(Rx32++I:circ(Mu2)) + C Intrinsic Prototype: Word32 Q6_R_memh_M_circ(void** Rx, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_R_memh_M_circ __builtin_HEXAGON_L2_loadrh_pcr + +/* ========================================================================== + Assembly Syntax: Rd32=memw(Rx32++#s4:2:circ(Mu2)) + C Intrinsic Prototype: Word32 Q6_R_memw_IM_circ(void** Rx, Word32 Is4_2, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_R_memw_IM_circ __builtin_HEXAGON_L2_loadri_pci + +/* ========================================================================== + Assembly Syntax: Rd32=memw(Rx32++I:circ(Mu2)) + C Intrinsic Prototype: Word32 Q6_R_memw_M_circ(void** Rx, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_R_memw_M_circ __builtin_HEXAGON_L2_loadri_pcr + +/* ========================================================================== + Assembly Syntax: Rd32=memub(Rx32++#s4:0:circ(Mu2)) + C Intrinsic Prototype: Word32 Q6_R_memub_IM_circ(void** Rx, Word32 Is4_0, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_R_memub_IM_circ __builtin_HEXAGON_L2_loadrub_pci + +/* ========================================================================== + Assembly Syntax: Rd32=memub(Rx32++I:circ(Mu2)) + C Intrinsic Prototype: Word32 Q6_R_memub_M_circ(void** Rx, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_R_memub_M_circ __builtin_HEXAGON_L2_loadrub_pcr + +/* ========================================================================== + Assembly Syntax: Rd32=memuh(Rx32++#s4:1:circ(Mu2)) + C Intrinsic Prototype: Word32 Q6_R_memuh_IM_circ(void** Rx, Word32 Is4_1, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_R_memuh_IM_circ __builtin_HEXAGON_L2_loadruh_pci + +/* ========================================================================== + Assembly Syntax: Rd32=memuh(Rx32++I:circ(Mu2)) + C Intrinsic Prototype: Word32 Q6_R_memuh_M_circ(void** Rx, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_R_memuh_M_circ __builtin_HEXAGON_L2_loadruh_pcr + +/* ========================================================================== + Assembly Syntax: Rx32+=add(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_addacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_addacc_RR __builtin_HEXAGON_M2_acci + +/* ========================================================================== + Assembly Syntax: Rx32+=add(Rs32,#s8) + C Intrinsic Prototype: Word32 Q6_R_addacc_RI(Word32 Rx, Word32 Rs, Word32 Is8) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_addacc_RI __builtin_HEXAGON_M2_accii + +/* ========================================================================== + Assembly Syntax: Rxx32+=cmpyi(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_cmpyiacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpyiacc_RR __builtin_HEXAGON_M2_cmaci_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=cmpyr(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_cmpyracc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpyracc_RR __builtin_HEXAGON_M2_cmacr_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=cmpy(Rs32,Rt32):sat + C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpyacc_RR_sat __builtin_HEXAGON_M2_cmacs_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=cmpy(Rs32,Rt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpyacc_RR_s1_sat __builtin_HEXAGON_M2_cmacs_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=cmpy(Rs32,Rt32*):sat + C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_conj_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpyacc_RR_conj_sat __builtin_HEXAGON_M2_cmacsc_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=cmpy(Rs32,Rt32*):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_conj_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpyacc_RR_conj_s1_sat __builtin_HEXAGON_M2_cmacsc_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=cmpyi(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_cmpyi_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpyi_RR __builtin_HEXAGON_M2_cmpyi_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=cmpyr(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_cmpyr_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpyr_RR __builtin_HEXAGON_M2_cmpyr_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=cmpy(Rs32,Rt32):rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cmpy_RR_rnd_sat __builtin_HEXAGON_M2_cmpyrs_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=cmpy(Rs32,Rt32):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_s1_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cmpy_RR_s1_rnd_sat __builtin_HEXAGON_M2_cmpyrs_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=cmpy(Rs32,Rt32*):rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_conj_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cmpy_RR_conj_rnd_sat __builtin_HEXAGON_M2_cmpyrsc_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=cmpy(Rs32,Rt32*):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_conj_s1_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cmpy_RR_conj_s1_rnd_sat __builtin_HEXAGON_M2_cmpyrsc_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=cmpy(Rs32,Rt32):sat + C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpy_RR_sat __builtin_HEXAGON_M2_cmpys_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=cmpy(Rs32,Rt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_s1_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpy_RR_s1_sat __builtin_HEXAGON_M2_cmpys_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=cmpy(Rs32,Rt32*):sat + C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_conj_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpy_RR_conj_sat __builtin_HEXAGON_M2_cmpysc_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=cmpy(Rs32,Rt32*):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_conj_s1_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpy_RR_conj_s1_sat __builtin_HEXAGON_M2_cmpysc_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32-=cmpy(Rs32,Rt32):sat + C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpynac_RR_sat __builtin_HEXAGON_M2_cnacs_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=cmpy(Rs32,Rt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpynac_RR_s1_sat __builtin_HEXAGON_M2_cnacs_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32-=cmpy(Rs32,Rt32*):sat + C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_conj_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpynac_RR_conj_sat __builtin_HEXAGON_M2_cnacsc_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=cmpy(Rs32,Rt32*):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_conj_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpynac_RR_conj_s1_sat __builtin_HEXAGON_M2_cnacsc_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpy(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_mpyacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyacc_RR __builtin_HEXAGON_M2_dpmpyss_acc_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpy(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_mpynac_RR(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpynac_RR __builtin_HEXAGON_M2_dpmpyss_nac_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32,Rt32):rnd + C Intrinsic Prototype: Word32 Q6_R_mpy_RR_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RR_rnd __builtin_HEXAGON_M2_dpmpyss_rnd_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_mpy_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RR __builtin_HEXAGON_M2_dpmpyss_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpyu(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyuacc_RR __builtin_HEXAGON_M2_dpmpyuu_acc_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpyu(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_mpyunac_RR(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyunac_RR __builtin_HEXAGON_M2_dpmpyuu_nac_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpyu(Rs32,Rt32) + C Intrinsic Prototype: UWord64 Q6_P_mpyu_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyu_RR __builtin_HEXAGON_M2_dpmpyuu_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32,Rt32.h):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RRh_s1_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RRh_s1_rnd_sat __builtin_HEXAGON_M2_hmmpyh_rs1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32,Rt32.h):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RRh_s1_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RRh_s1_sat __builtin_HEXAGON_M2_hmmpyh_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32,Rt32.l):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RRl_s1_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RRl_s1_rnd_sat __builtin_HEXAGON_M2_hmmpyl_rs1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32,Rt32.l):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RRl_s1_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RRl_s1_sat __builtin_HEXAGON_M2_hmmpyl_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpyi(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_mpyiacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyiacc_RR __builtin_HEXAGON_M2_maci + +/* ========================================================================== + Assembly Syntax: Rx32-=mpyi(Rs32,#u8) + C Intrinsic Prototype: Word32 Q6_R_mpyinac_RI(Word32 Rx, Word32 Rs, Word32 Iu8) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyinac_RI __builtin_HEXAGON_M2_macsin + +/* ========================================================================== + Assembly Syntax: Rx32+=mpyi(Rs32,#u8) + C Intrinsic Prototype: Word32 Q6_R_mpyiacc_RI(Word32 Rx, Word32 Rs, Word32 Iu8) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyiacc_RI __builtin_HEXAGON_M2_macsip + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpywoh(Rss32,Rtt32):rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywohacc_PP_rnd_sat __builtin_HEXAGON_M2_mmachs_rs0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpywoh(Rss32,Rtt32):<<1:rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywohacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmachs_rs1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpywoh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywohacc_PP_sat __builtin_HEXAGON_M2_mmachs_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpywoh(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywohacc_PP_s1_sat __builtin_HEXAGON_M2_mmachs_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyweh(Rss32,Rtt32):rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywehacc_PP_rnd_sat __builtin_HEXAGON_M2_mmacls_rs0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyweh(Rss32,Rtt32):<<1:rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywehacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmacls_rs1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyweh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywehacc_PP_sat __builtin_HEXAGON_M2_mmacls_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyweh(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywehacc_PP_s1_sat __builtin_HEXAGON_M2_mmacls_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpywouh(Rss32,Rtt32):rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywouhacc_PP_rnd_sat __builtin_HEXAGON_M2_mmacuhs_rs0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpywouh(Rss32,Rtt32):<<1:rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywouhacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmacuhs_rs1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpywouh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywouhacc_PP_sat __builtin_HEXAGON_M2_mmacuhs_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpywouh(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywouhacc_PP_s1_sat __builtin_HEXAGON_M2_mmacuhs_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyweuh(Rss32,Rtt32):rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweuhacc_PP_rnd_sat __builtin_HEXAGON_M2_mmaculs_rs0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyweuh(Rss32,Rtt32):<<1:rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweuhacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmaculs_rs1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyweuh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweuhacc_PP_sat __builtin_HEXAGON_M2_mmaculs_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyweuh(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweuhacc_PP_s1_sat __builtin_HEXAGON_M2_mmaculs_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpywoh(Rss32,Rtt32):rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywoh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyh_rs0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpywoh(Rss32,Rtt32):<<1:rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywoh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyh_rs1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpywoh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywoh_PP_sat __builtin_HEXAGON_M2_mmpyh_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpywoh(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywoh_PP_s1_sat __builtin_HEXAGON_M2_mmpyh_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyweh(Rss32,Rtt32):rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyl_rs0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyweh(Rss32,Rtt32):<<1:rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyl_rs1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyweh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweh_PP_sat __builtin_HEXAGON_M2_mmpyl_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyweh(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweh_PP_s1_sat __builtin_HEXAGON_M2_mmpyl_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpywouh(Rss32,Rtt32):rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywouh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyuh_rs0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpywouh(Rss32,Rtt32):<<1:rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywouh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyuh_rs1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpywouh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywouh_PP_sat __builtin_HEXAGON_M2_mmpyuh_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpywouh(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywouh_PP_s1_sat __builtin_HEXAGON_M2_mmpyuh_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyweuh(Rss32,Rtt32):rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweuh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyul_rs0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyweuh(Rss32,Rtt32):<<1:rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweuh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyul_rs1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyweuh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweuh_PP_sat __builtin_HEXAGON_M2_mmpyul_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyweuh(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweuh_PP_s1_sat __builtin_HEXAGON_M2_mmpyul_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.h) + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RhRh __builtin_HEXAGON_M2_mpy_acc_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RhRh_s1 __builtin_HEXAGON_M2_mpy_acc_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.l) + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RhRl __builtin_HEXAGON_M2_mpy_acc_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RhRl_s1 __builtin_HEXAGON_M2_mpy_acc_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.h) + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RlRh __builtin_HEXAGON_M2_mpy_acc_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RlRh_s1 __builtin_HEXAGON_M2_mpy_acc_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.l) + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RlRl __builtin_HEXAGON_M2_mpy_acc_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RlRl_s1 __builtin_HEXAGON_M2_mpy_acc_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.h):sat + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RhRh_sat __builtin_HEXAGON_M2_mpy_acc_sat_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.h):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RhRh_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.l):sat + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RhRl_sat __builtin_HEXAGON_M2_mpy_acc_sat_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.l):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RhRl_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.h):sat + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RlRh_sat __builtin_HEXAGON_M2_mpy_acc_sat_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.h):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RlRh_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.l):sat + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RlRl_sat __builtin_HEXAGON_M2_mpy_acc_sat_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.l):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RlRl_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h) + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRh __builtin_HEXAGON_M2_mpy_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRh_s1 __builtin_HEXAGON_M2_mpy_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l) + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRl __builtin_HEXAGON_M2_mpy_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRl_s1 __builtin_HEXAGON_M2_mpy_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h) + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRh __builtin_HEXAGON_M2_mpy_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRh_s1 __builtin_HEXAGON_M2_mpy_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l) + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRl __builtin_HEXAGON_M2_mpy_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRl_s1 __builtin_HEXAGON_M2_mpy_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.h) + C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RhRh __builtin_HEXAGON_M2_mpy_nac_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RhRh_s1 __builtin_HEXAGON_M2_mpy_nac_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.l) + C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RhRl __builtin_HEXAGON_M2_mpy_nac_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RhRl_s1 __builtin_HEXAGON_M2_mpy_nac_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.h) + C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RlRh __builtin_HEXAGON_M2_mpy_nac_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RlRh_s1 __builtin_HEXAGON_M2_mpy_nac_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.l) + C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RlRl __builtin_HEXAGON_M2_mpy_nac_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RlRl_s1 __builtin_HEXAGON_M2_mpy_nac_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.h):sat + C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RhRh_sat __builtin_HEXAGON_M2_mpy_nac_sat_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.h):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RhRh_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.l):sat + C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RhRl_sat __builtin_HEXAGON_M2_mpy_nac_sat_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.l):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RhRl_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.h):sat + C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RlRh_sat __builtin_HEXAGON_M2_mpy_nac_sat_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.h):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RlRh_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.l):sat + C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RlRl_sat __builtin_HEXAGON_M2_mpy_nac_sat_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.l):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RlRl_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):rnd + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRh_rnd __builtin_HEXAGON_M2_mpy_rnd_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):<<1:rnd + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRh_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):rnd + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRl_rnd __builtin_HEXAGON_M2_mpy_rnd_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):<<1:rnd + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRl_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):rnd + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRh_rnd __builtin_HEXAGON_M2_mpy_rnd_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):<<1:rnd + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRh_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):rnd + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRl_rnd __builtin_HEXAGON_M2_mpy_rnd_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):<<1:rnd + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRl_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRh_sat __builtin_HEXAGON_M2_mpy_sat_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRh_s1_sat __builtin_HEXAGON_M2_mpy_sat_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRl_sat __builtin_HEXAGON_M2_mpy_sat_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRl_s1_sat __builtin_HEXAGON_M2_mpy_sat_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRh_sat __builtin_HEXAGON_M2_mpy_sat_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRh_s1_sat __builtin_HEXAGON_M2_mpy_sat_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRl_sat __builtin_HEXAGON_M2_mpy_sat_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRl_s1_sat __builtin_HEXAGON_M2_mpy_sat_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):rnd:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRh_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRh_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):rnd:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRl_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRl_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):rnd:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRh_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRh_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):rnd:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRl_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRl_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_mpy_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RR __builtin_HEXAGON_M2_mpy_up + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32,Rt32):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpy_RR_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RR_s1 __builtin_HEXAGON_M2_mpy_up_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32,Rt32):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RR_s1_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RR_s1_sat __builtin_HEXAGON_M2_mpy_up_s1_sat + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpy(Rs32.h,Rt32.h) + C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyacc_RhRh __builtin_HEXAGON_M2_mpyd_acc_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpy(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyacc_RhRh_s1 __builtin_HEXAGON_M2_mpyd_acc_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpy(Rs32.h,Rt32.l) + C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyacc_RhRl __builtin_HEXAGON_M2_mpyd_acc_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpy(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyacc_RhRl_s1 __builtin_HEXAGON_M2_mpyd_acc_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpy(Rs32.l,Rt32.h) + C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyacc_RlRh __builtin_HEXAGON_M2_mpyd_acc_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpy(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyacc_RlRh_s1 __builtin_HEXAGON_M2_mpyd_acc_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpy(Rs32.l,Rt32.l) + C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyacc_RlRl __builtin_HEXAGON_M2_mpyd_acc_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpy(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyacc_RlRl_s1 __builtin_HEXAGON_M2_mpyd_acc_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.h) + C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RhRh __builtin_HEXAGON_M2_mpyd_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RhRh_s1 __builtin_HEXAGON_M2_mpyd_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.l) + C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RhRl __builtin_HEXAGON_M2_mpyd_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RhRl_s1 __builtin_HEXAGON_M2_mpyd_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.h) + C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RlRh __builtin_HEXAGON_M2_mpyd_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RlRh_s1 __builtin_HEXAGON_M2_mpyd_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.l) + C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RlRl __builtin_HEXAGON_M2_mpyd_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RlRl_s1 __builtin_HEXAGON_M2_mpyd_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpy(Rs32.h,Rt32.h) + C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpynac_RhRh __builtin_HEXAGON_M2_mpyd_nac_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpy(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpynac_RhRh_s1 __builtin_HEXAGON_M2_mpyd_nac_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpy(Rs32.h,Rt32.l) + C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpynac_RhRl __builtin_HEXAGON_M2_mpyd_nac_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpy(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpynac_RhRl_s1 __builtin_HEXAGON_M2_mpyd_nac_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpy(Rs32.l,Rt32.h) + C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpynac_RlRh __builtin_HEXAGON_M2_mpyd_nac_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpy(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpynac_RlRh_s1 __builtin_HEXAGON_M2_mpyd_nac_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpy(Rs32.l,Rt32.l) + C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpynac_RlRl __builtin_HEXAGON_M2_mpyd_nac_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpy(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpynac_RlRl_s1 __builtin_HEXAGON_M2_mpyd_nac_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.h):rnd + C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RhRh_rnd __builtin_HEXAGON_M2_mpyd_rnd_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.h):<<1:rnd + C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh_s1_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RhRh_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.l):rnd + C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RhRl_rnd __builtin_HEXAGON_M2_mpyd_rnd_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.l):<<1:rnd + C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl_s1_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RhRl_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.h):rnd + C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RlRh_rnd __builtin_HEXAGON_M2_mpyd_rnd_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.h):<<1:rnd + C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh_s1_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RlRh_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.l):rnd + C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RlRl_rnd __builtin_HEXAGON_M2_mpyd_rnd_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.l):<<1:rnd + C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl_s1_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RlRl_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpyi(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_mpyi_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyi_RR __builtin_HEXAGON_M2_mpyi + +/* ========================================================================== + Assembly Syntax: Rd32=mpyi(Rs32,#m9) + C Intrinsic Prototype: Word32 Q6_R_mpyi_RI(Word32 Rs, Word32 Im9) + Instruction Type: M + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_mpyi_RI __builtin_HEXAGON_M2_mpysmi + +/* ========================================================================== + Assembly Syntax: Rd32=mpysu(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_mpysu_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpysu_RR __builtin_HEXAGON_M2_mpysu_up + +/* ========================================================================== + Assembly Syntax: Rx32+=mpyu(Rs32.h,Rt32.h) + C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRh(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyuacc_RhRh __builtin_HEXAGON_M2_mpyu_acc_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpyu(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyuacc_RhRh_s1 __builtin_HEXAGON_M2_mpyu_acc_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpyu(Rs32.h,Rt32.l) + C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRl(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyuacc_RhRl __builtin_HEXAGON_M2_mpyu_acc_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpyu(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyuacc_RhRl_s1 __builtin_HEXAGON_M2_mpyu_acc_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpyu(Rs32.l,Rt32.h) + C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRh(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyuacc_RlRh __builtin_HEXAGON_M2_mpyu_acc_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpyu(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyuacc_RlRh_s1 __builtin_HEXAGON_M2_mpyu_acc_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpyu(Rs32.l,Rt32.l) + C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRl(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyuacc_RlRl __builtin_HEXAGON_M2_mpyu_acc_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpyu(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyuacc_RlRl_s1 __builtin_HEXAGON_M2_mpyu_acc_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpyu(Rs32.h,Rt32.h) + C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRh(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyu_RhRh __builtin_HEXAGON_M2_mpyu_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpyu(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRh_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyu_RhRh_s1 __builtin_HEXAGON_M2_mpyu_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpyu(Rs32.h,Rt32.l) + C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRl(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyu_RhRl __builtin_HEXAGON_M2_mpyu_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpyu(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRl_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyu_RhRl_s1 __builtin_HEXAGON_M2_mpyu_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpyu(Rs32.l,Rt32.h) + C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRh(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyu_RlRh __builtin_HEXAGON_M2_mpyu_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpyu(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRh_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyu_RlRh_s1 __builtin_HEXAGON_M2_mpyu_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpyu(Rs32.l,Rt32.l) + C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRl(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyu_RlRl __builtin_HEXAGON_M2_mpyu_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpyu(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRl_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyu_RlRl_s1 __builtin_HEXAGON_M2_mpyu_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpyu(Rs32.h,Rt32.h) + C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRh(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyunac_RhRh __builtin_HEXAGON_M2_mpyu_nac_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpyu(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyunac_RhRh_s1 __builtin_HEXAGON_M2_mpyu_nac_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpyu(Rs32.h,Rt32.l) + C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRl(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyunac_RhRl __builtin_HEXAGON_M2_mpyu_nac_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpyu(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyunac_RhRl_s1 __builtin_HEXAGON_M2_mpyu_nac_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpyu(Rs32.l,Rt32.h) + C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRh(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyunac_RlRh __builtin_HEXAGON_M2_mpyu_nac_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpyu(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyunac_RlRh_s1 __builtin_HEXAGON_M2_mpyu_nac_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpyu(Rs32.l,Rt32.l) + C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRl(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyunac_RlRl __builtin_HEXAGON_M2_mpyu_nac_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpyu(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyunac_RlRl_s1 __builtin_HEXAGON_M2_mpyu_nac_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpyu(Rs32,Rt32) + C Intrinsic Prototype: UWord32 Q6_R_mpyu_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyu_RR __builtin_HEXAGON_M2_mpyu_up + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpyu(Rs32.h,Rt32.h) + C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyuacc_RhRh __builtin_HEXAGON_M2_mpyud_acc_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpyu(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyuacc_RhRh_s1 __builtin_HEXAGON_M2_mpyud_acc_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpyu(Rs32.h,Rt32.l) + C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyuacc_RhRl __builtin_HEXAGON_M2_mpyud_acc_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpyu(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyuacc_RhRl_s1 __builtin_HEXAGON_M2_mpyud_acc_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpyu(Rs32.l,Rt32.h) + C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyuacc_RlRh __builtin_HEXAGON_M2_mpyud_acc_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpyu(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyuacc_RlRh_s1 __builtin_HEXAGON_M2_mpyud_acc_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpyu(Rs32.l,Rt32.l) + C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyuacc_RlRl __builtin_HEXAGON_M2_mpyud_acc_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpyu(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyuacc_RlRl_s1 __builtin_HEXAGON_M2_mpyud_acc_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpyu(Rs32.h,Rt32.h) + C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRh(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyu_RhRh __builtin_HEXAGON_M2_mpyud_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpyu(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRh_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyu_RhRh_s1 __builtin_HEXAGON_M2_mpyud_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpyu(Rs32.h,Rt32.l) + C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRl(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyu_RhRl __builtin_HEXAGON_M2_mpyud_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpyu(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRl_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyu_RhRl_s1 __builtin_HEXAGON_M2_mpyud_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpyu(Rs32.l,Rt32.h) + C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRh(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyu_RlRh __builtin_HEXAGON_M2_mpyud_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpyu(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRh_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyu_RlRh_s1 __builtin_HEXAGON_M2_mpyud_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpyu(Rs32.l,Rt32.l) + C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRl(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyu_RlRl __builtin_HEXAGON_M2_mpyud_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpyu(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRl_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyu_RlRl_s1 __builtin_HEXAGON_M2_mpyud_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpyu(Rs32.h,Rt32.h) + C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyunac_RhRh __builtin_HEXAGON_M2_mpyud_nac_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpyu(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyunac_RhRh_s1 __builtin_HEXAGON_M2_mpyud_nac_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpyu(Rs32.h,Rt32.l) + C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyunac_RhRl __builtin_HEXAGON_M2_mpyud_nac_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpyu(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyunac_RhRl_s1 __builtin_HEXAGON_M2_mpyud_nac_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpyu(Rs32.l,Rt32.h) + C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyunac_RlRh __builtin_HEXAGON_M2_mpyud_nac_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpyu(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyunac_RlRh_s1 __builtin_HEXAGON_M2_mpyud_nac_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpyu(Rs32.l,Rt32.l) + C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyunac_RlRl __builtin_HEXAGON_M2_mpyud_nac_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpyu(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyunac_RlRl_s1 __builtin_HEXAGON_M2_mpyud_nac_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpyui(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_mpyui_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_mpyui_RR __builtin_HEXAGON_M2_mpyui + +/* ========================================================================== + Assembly Syntax: Rx32-=add(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_addnac_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_addnac_RR __builtin_HEXAGON_M2_nacci + +/* ========================================================================== + Assembly Syntax: Rx32-=add(Rs32,#s8) + C Intrinsic Prototype: Word32 Q6_R_addnac_RI(Word32 Rx, Word32 Rs, Word32 Is8) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_addnac_RI __builtin_HEXAGON_M2_naccii + +/* ========================================================================== + Assembly Syntax: Rx32+=sub(Rt32,Rs32) + C Intrinsic Prototype: Word32 Q6_R_subacc_RR(Word32 Rx, Word32 Rt, Word32 Rs) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_subacc_RR __builtin_HEXAGON_M2_subacc + +/* ========================================================================== + Assembly Syntax: Rdd32=vabsdiffh(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vabsdiffh_PP(Word64 Rtt, Word64 Rss) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vabsdiffh_PP __builtin_HEXAGON_M2_vabsdiffh + +/* ========================================================================== + Assembly Syntax: Rdd32=vabsdiffw(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vabsdiffw_PP(Word64 Rtt, Word64 Rss) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vabsdiffw_PP __builtin_HEXAGON_M2_vabsdiffw + +/* ========================================================================== + Assembly Syntax: Rxx32+=vcmpyi(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vcmpyiacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vcmpyiacc_PP_sat __builtin_HEXAGON_M2_vcmac_s0_sat_i + +/* ========================================================================== + Assembly Syntax: Rxx32+=vcmpyr(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vcmpyracc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vcmpyracc_PP_sat __builtin_HEXAGON_M2_vcmac_s0_sat_r + +/* ========================================================================== + Assembly Syntax: Rdd32=vcmpyi(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vcmpyi_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vcmpyi_PP_sat __builtin_HEXAGON_M2_vcmpy_s0_sat_i + +/* ========================================================================== + Assembly Syntax: Rdd32=vcmpyr(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vcmpyr_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vcmpyr_PP_sat __builtin_HEXAGON_M2_vcmpy_s0_sat_r + +/* ========================================================================== + Assembly Syntax: Rdd32=vcmpyi(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vcmpyi_PP_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vcmpyi_PP_s1_sat __builtin_HEXAGON_M2_vcmpy_s1_sat_i + +/* ========================================================================== + Assembly Syntax: Rdd32=vcmpyr(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vcmpyr_PP_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vcmpyr_PP_s1_sat __builtin_HEXAGON_M2_vcmpy_s1_sat_r + +/* ========================================================================== + Assembly Syntax: Rxx32+=vdmpy(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vdmpyacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vdmpyacc_PP_sat __builtin_HEXAGON_M2_vdmacs_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vdmpy(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vdmpyacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vdmpyacc_PP_s1_sat __builtin_HEXAGON_M2_vdmacs_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=vdmpy(Rss32,Rtt32):rnd:sat + C Intrinsic Prototype: Word32 Q6_R_vdmpy_PP_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vdmpy_PP_rnd_sat __builtin_HEXAGON_M2_vdmpyrs_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=vdmpy(Rss32,Rtt32):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_vdmpy_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vdmpy_PP_s1_rnd_sat __builtin_HEXAGON_M2_vdmpyrs_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vdmpy(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vdmpy_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vdmpy_PP_sat __builtin_HEXAGON_M2_vdmpys_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vdmpy(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vdmpy_PP_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vdmpy_PP_s1_sat __builtin_HEXAGON_M2_vdmpys_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyh(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyhacc_RR __builtin_HEXAGON_M2_vmac2 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyeh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyehacc_PP __builtin_HEXAGON_M2_vmac2es + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyeh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyehacc_PP_sat __builtin_HEXAGON_M2_vmac2es_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyeh(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyehacc_PP_s1_sat __builtin_HEXAGON_M2_vmac2es_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyh(Rs32,Rt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyhacc_RR_sat __builtin_HEXAGON_M2_vmac2s_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyh(Rs32,Rt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyhacc_RR_s1_sat __builtin_HEXAGON_M2_vmac2s_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyhsu(Rs32,Rt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpyhsuacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyhsuacc_RR_sat __builtin_HEXAGON_M2_vmac2su_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyhsu(Rs32,Rt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyhsuacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyhsuacc_RR_s1_sat __builtin_HEXAGON_M2_vmac2su_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyeh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpyeh_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyeh_PP_sat __builtin_HEXAGON_M2_vmpy2es_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyeh(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyeh_PP_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyeh_PP_s1_sat __builtin_HEXAGON_M2_vmpy2es_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyh(Rs32,Rt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpyh_RR_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyh_RR_sat __builtin_HEXAGON_M2_vmpy2s_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=vmpyh(Rs32,Rt32):rnd:sat + C Intrinsic Prototype: Word32 Q6_R_vmpyh_RR_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vmpyh_RR_rnd_sat __builtin_HEXAGON_M2_vmpy2s_s0pack + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyh(Rs32,Rt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyh_RR_s1_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyh_RR_s1_sat __builtin_HEXAGON_M2_vmpy2s_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=vmpyh(Rs32,Rt32):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_vmpyh_RR_s1_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vmpyh_RR_s1_rnd_sat __builtin_HEXAGON_M2_vmpy2s_s1pack + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyhsu(Rs32,Rt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpyhsu_RR_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyhsu_RR_sat __builtin_HEXAGON_M2_vmpy2su_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyhsu(Rs32,Rt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyhsu_RR_s1_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyhsu_RR_s1_sat __builtin_HEXAGON_M2_vmpy2su_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=vraddh(Rss32,Rtt32) + C Intrinsic Prototype: Word32 Q6_R_vraddh_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vraddh_PP __builtin_HEXAGON_M2_vraddh + +/* ========================================================================== + Assembly Syntax: Rd32=vradduh(Rss32,Rtt32) + C Intrinsic Prototype: Word32 Q6_R_vradduh_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vradduh_PP __builtin_HEXAGON_M2_vradduh + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrcmpyi(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrcmpyiacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrcmpyiacc_PP __builtin_HEXAGON_M2_vrcmaci_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrcmpyi(Rss32,Rtt32*) + C Intrinsic Prototype: Word64 Q6_P_vrcmpyiacc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrcmpyiacc_PP_conj __builtin_HEXAGON_M2_vrcmaci_s0c + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrcmpyr(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrcmpyracc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrcmpyracc_PP __builtin_HEXAGON_M2_vrcmacr_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrcmpyr(Rss32,Rtt32*) + C Intrinsic Prototype: Word64 Q6_P_vrcmpyracc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrcmpyracc_PP_conj __builtin_HEXAGON_M2_vrcmacr_s0c + +/* ========================================================================== + Assembly Syntax: Rdd32=vrcmpyi(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrcmpyi_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrcmpyi_PP __builtin_HEXAGON_M2_vrcmpyi_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vrcmpyi(Rss32,Rtt32*) + C Intrinsic Prototype: Word64 Q6_P_vrcmpyi_PP_conj(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrcmpyi_PP_conj __builtin_HEXAGON_M2_vrcmpyi_s0c + +/* ========================================================================== + Assembly Syntax: Rdd32=vrcmpyr(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrcmpyr_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrcmpyr_PP __builtin_HEXAGON_M2_vrcmpyr_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vrcmpyr(Rss32,Rtt32*) + C Intrinsic Prototype: Word64 Q6_P_vrcmpyr_PP_conj(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrcmpyr_PP_conj __builtin_HEXAGON_M2_vrcmpyr_s0c + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrcmpys(Rss32,Rt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vrcmpysacc_PR_s1_sat(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_vrcmpysacc_PR_s1_sat __builtin_HEXAGON_M2_vrcmpys_acc_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vrcmpys(Rss32,Rt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vrcmpys_PR_s1_sat(Word64 Rss, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_vrcmpys_PR_s1_sat __builtin_HEXAGON_M2_vrcmpys_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=vrcmpys(Rss32,Rt32):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_vrcmpys_PR_s1_rnd_sat(Word64 Rss, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_vrcmpys_PR_s1_rnd_sat __builtin_HEXAGON_M2_vrcmpys_s1rp + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrmpyh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrmpyhacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpyhacc_PP __builtin_HEXAGON_M2_vrmac_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vrmpyh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrmpyh_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpyh_PP __builtin_HEXAGON_M2_vrmpy_s0 + +/* ========================================================================== + Assembly Syntax: Rx32^=xor(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_xorxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_xorxacc_RR __builtin_HEXAGON_M2_xor_xacc + +/* ========================================================================== + Assembly Syntax: Rx32&=and(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_andand_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_andand_RR __builtin_HEXAGON_M4_and_and + +/* ========================================================================== + Assembly Syntax: Rx32&=and(Rs32,~Rt32) + C Intrinsic Prototype: Word32 Q6_R_andand_RnR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_andand_RnR __builtin_HEXAGON_M4_and_andn + +/* ========================================================================== + Assembly Syntax: Rx32&=or(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_orand_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_orand_RR __builtin_HEXAGON_M4_and_or + +/* ========================================================================== + Assembly Syntax: Rx32&=xor(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_xorand_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_xorand_RR __builtin_HEXAGON_M4_and_xor + +/* ========================================================================== + Assembly Syntax: Rd32=cmpyiwh(Rss32,Rt32):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyiwh_PR_s1_rnd_sat(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cmpyiwh_PR_s1_rnd_sat __builtin_HEXAGON_M4_cmpyi_wh + +/* ========================================================================== + Assembly Syntax: Rd32=cmpyiwh(Rss32,Rt32*):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyiwh_PR_conj_s1_rnd_sat(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cmpyiwh_PR_conj_s1_rnd_sat __builtin_HEXAGON_M4_cmpyi_whc + +/* ========================================================================== + Assembly Syntax: Rd32=cmpyrwh(Rss32,Rt32):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyrwh_PR_s1_rnd_sat(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cmpyrwh_PR_s1_rnd_sat __builtin_HEXAGON_M4_cmpyr_wh + +/* ========================================================================== + Assembly Syntax: Rd32=cmpyrwh(Rss32,Rt32*):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyrwh_PR_conj_s1_rnd_sat(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cmpyrwh_PR_conj_s1_rnd_sat __builtin_HEXAGON_M4_cmpyr_whc + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32,Rt32):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RR_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RR_s1_sat __builtin_HEXAGON_M4_mac_up_s1_sat + +/* ========================================================================== + Assembly Syntax: Rd32=add(#u6,mpyi(Rs32,#U6)) + C Intrinsic Prototype: Word32 Q6_R_add_mpyi_IRI(Word32 Iu6, Word32 Rs, Word32 IU6) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_mpyi_IRI __builtin_HEXAGON_M4_mpyri_addi + +/* ========================================================================== + Assembly Syntax: Rd32=add(Ru32,mpyi(Rs32,#u6)) + C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RRI(Word32 Ru, Word32 Rs, Word32 Iu6) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_mpyi_RRI __builtin_HEXAGON_M4_mpyri_addr + +/* ========================================================================== + Assembly Syntax: Rd32=add(Ru32,mpyi(#u6:2,Rs32)) + C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RIR(Word32 Ru, Word32 Iu6_2, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_mpyi_RIR __builtin_HEXAGON_M4_mpyri_addr_u2 + +/* ========================================================================== + Assembly Syntax: Rd32=add(#u6,mpyi(Rs32,Rt32)) + C Intrinsic Prototype: Word32 Q6_R_add_mpyi_IRR(Word32 Iu6, Word32 Rs, Word32 Rt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_mpyi_IRR __builtin_HEXAGON_M4_mpyrr_addi + +/* ========================================================================== + Assembly Syntax: Ry32=add(Ru32,mpyi(Ry32,Rs32)) + C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RRR(Word32 Ru, Word32 Ry, Word32 Rs) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_mpyi_RRR __builtin_HEXAGON_M4_mpyrr_addr + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32,Rt32):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpynac_RR_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RR_s1_sat __builtin_HEXAGON_M4_nac_up_s1_sat + +/* ========================================================================== + Assembly Syntax: Rx32|=and(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_andor_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_andor_RR __builtin_HEXAGON_M4_or_and + +/* ========================================================================== + Assembly Syntax: Rx32|=and(Rs32,~Rt32) + C Intrinsic Prototype: Word32 Q6_R_andor_RnR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_andor_RnR __builtin_HEXAGON_M4_or_andn + +/* ========================================================================== + Assembly Syntax: Rx32|=or(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_oror_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_oror_RR __builtin_HEXAGON_M4_or_or + +/* ========================================================================== + Assembly Syntax: Rx32|=xor(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_xoror_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_xoror_RR __builtin_HEXAGON_M4_or_xor + +/* ========================================================================== + Assembly Syntax: Rdd32=pmpyw(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_pmpyw_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_pmpyw_RR __builtin_HEXAGON_M4_pmpyw + +/* ========================================================================== + Assembly Syntax: Rxx32^=pmpyw(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_pmpywxacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_pmpywxacc_RR __builtin_HEXAGON_M4_pmpyw_acc + +/* ========================================================================== + Assembly Syntax: Rdd32=vpmpyh(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vpmpyh_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vpmpyh_RR __builtin_HEXAGON_M4_vpmpyh + +/* ========================================================================== + Assembly Syntax: Rxx32^=vpmpyh(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vpmpyhxacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vpmpyhxacc_RR __builtin_HEXAGON_M4_vpmpyh_acc + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrmpyweh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrmpywehacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpywehacc_PP __builtin_HEXAGON_M4_vrmpyeh_acc_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrmpyweh(Rss32,Rtt32):<<1 + C Intrinsic Prototype: Word64 Q6_P_vrmpywehacc_PP_s1(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpywehacc_PP_s1 __builtin_HEXAGON_M4_vrmpyeh_acc_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vrmpyweh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrmpyweh_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpyweh_PP __builtin_HEXAGON_M4_vrmpyeh_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vrmpyweh(Rss32,Rtt32):<<1 + C Intrinsic Prototype: Word64 Q6_P_vrmpyweh_PP_s1(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpyweh_PP_s1 __builtin_HEXAGON_M4_vrmpyeh_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrmpywoh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrmpywohacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpywohacc_PP __builtin_HEXAGON_M4_vrmpyoh_acc_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrmpywoh(Rss32,Rtt32):<<1 + C Intrinsic Prototype: Word64 Q6_P_vrmpywohacc_PP_s1(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpywohacc_PP_s1 __builtin_HEXAGON_M4_vrmpyoh_acc_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vrmpywoh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrmpywoh_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpywoh_PP __builtin_HEXAGON_M4_vrmpyoh_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vrmpywoh(Rss32,Rtt32):<<1 + C Intrinsic Prototype: Word64 Q6_P_vrmpywoh_PP_s1(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpywoh_PP_s1 __builtin_HEXAGON_M4_vrmpyoh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32^=and(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_andxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_andxacc_RR __builtin_HEXAGON_M4_xor_and + +/* ========================================================================== + Assembly Syntax: Rx32^=and(Rs32,~Rt32) + C Intrinsic Prototype: Word32 Q6_R_andxacc_RnR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_andxacc_RnR __builtin_HEXAGON_M4_xor_andn + +/* ========================================================================== + Assembly Syntax: Rx32^=or(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_orxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_orxacc_RR __builtin_HEXAGON_M4_xor_or + +/* ========================================================================== + Assembly Syntax: Rxx32^=xor(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_xorxacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_xorxacc_PP __builtin_HEXAGON_M4_xor_xacc + +/* ========================================================================== + Assembly Syntax: Rxx32+=vdmpybsu(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vdmpybsuacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vdmpybsuacc_PP_sat __builtin_HEXAGON_M5_vdmacbsu + +/* ========================================================================== + Assembly Syntax: Rdd32=vdmpybsu(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vdmpybsu_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vdmpybsu_PP_sat __builtin_HEXAGON_M5_vdmpybsu + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpybsu(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vmpybsuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpybsuacc_RR __builtin_HEXAGON_M5_vmacbsu + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpybu(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vmpybuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpybuacc_RR __builtin_HEXAGON_M5_vmacbuu + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpybsu(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vmpybsu_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpybsu_RR __builtin_HEXAGON_M5_vmpybsu + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpybu(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vmpybu_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpybu_RR __builtin_HEXAGON_M5_vmpybuu + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrmpybsu(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrmpybsuacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpybsuacc_PP __builtin_HEXAGON_M5_vrmacbsu + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrmpybu(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrmpybuacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpybuacc_PP __builtin_HEXAGON_M5_vrmacbuu + +/* ========================================================================== + Assembly Syntax: Rdd32=vrmpybsu(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrmpybsu_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpybsu_PP __builtin_HEXAGON_M5_vrmpybsu + +/* ========================================================================== + Assembly Syntax: Rdd32=vrmpybu(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrmpybu_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpybu_PP __builtin_HEXAGON_M5_vrmpybuu + +/* ========================================================================== + Assembly Syntax: Rd32=addasl(Rt32,Rs32,#u3) + C Intrinsic Prototype: Word32 Q6_R_addasl_RRI(Word32 Rt, Word32 Rs, Word32 Iu3) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_addasl_RRI __builtin_HEXAGON_S2_addasl_rrri + +/* ========================================================================== + Assembly Syntax: Rdd32=asl(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_asl_PI(Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asl_PI __builtin_HEXAGON_S2_asl_i_p + +/* ========================================================================== + Assembly Syntax: Rxx32+=asl(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_aslacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_aslacc_PI __builtin_HEXAGON_S2_asl_i_p_acc + +/* ========================================================================== + Assembly Syntax: Rxx32&=asl(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_asland_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asland_PI __builtin_HEXAGON_S2_asl_i_p_and + +/* ========================================================================== + Assembly Syntax: Rxx32-=asl(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_aslnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_aslnac_PI __builtin_HEXAGON_S2_asl_i_p_nac + +/* ========================================================================== + Assembly Syntax: Rxx32|=asl(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_aslor_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_aslor_PI __builtin_HEXAGON_S2_asl_i_p_or + +/* ========================================================================== + Assembly Syntax: Rxx32^=asl(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_aslxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_aslxacc_PI __builtin_HEXAGON_S2_asl_i_p_xacc + +/* ========================================================================== + Assembly Syntax: Rd32=asl(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_asl_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asl_RI __builtin_HEXAGON_S2_asl_i_r + +/* ========================================================================== + Assembly Syntax: Rx32+=asl(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_aslacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_aslacc_RI __builtin_HEXAGON_S2_asl_i_r_acc + +/* ========================================================================== + Assembly Syntax: Rx32&=asl(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_asland_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asland_RI __builtin_HEXAGON_S2_asl_i_r_and + +/* ========================================================================== + Assembly Syntax: Rx32-=asl(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_aslnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_aslnac_RI __builtin_HEXAGON_S2_asl_i_r_nac + +/* ========================================================================== + Assembly Syntax: Rx32|=asl(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_aslor_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_aslor_RI __builtin_HEXAGON_S2_asl_i_r_or + +/* ========================================================================== + Assembly Syntax: Rd32=asl(Rs32,#u5):sat + C Intrinsic Prototype: Word32 Q6_R_asl_RI_sat(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asl_RI_sat __builtin_HEXAGON_S2_asl_i_r_sat + +/* ========================================================================== + Assembly Syntax: Rx32^=asl(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_aslxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_aslxacc_RI __builtin_HEXAGON_S2_asl_i_r_xacc + +/* ========================================================================== + Assembly Syntax: Rdd32=vaslh(Rss32,#u4) + C Intrinsic Prototype: Word64 Q6_P_vaslh_PI(Word64 Rss, Word32 Iu4) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vaslh_PI __builtin_HEXAGON_S2_asl_i_vh + +/* ========================================================================== + Assembly Syntax: Rdd32=vaslw(Rss32,#u5) + C Intrinsic Prototype: Word64 Q6_P_vaslw_PI(Word64 Rss, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vaslw_PI __builtin_HEXAGON_S2_asl_i_vw + +/* ========================================================================== + Assembly Syntax: Rdd32=asl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_asl_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asl_PR __builtin_HEXAGON_S2_asl_r_p + +/* ========================================================================== + Assembly Syntax: Rxx32+=asl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_aslacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_aslacc_PR __builtin_HEXAGON_S2_asl_r_p_acc + +/* ========================================================================== + Assembly Syntax: Rxx32&=asl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_asland_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asland_PR __builtin_HEXAGON_S2_asl_r_p_and + +/* ========================================================================== + Assembly Syntax: Rxx32-=asl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_aslnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_aslnac_PR __builtin_HEXAGON_S2_asl_r_p_nac + +/* ========================================================================== + Assembly Syntax: Rxx32|=asl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_aslor_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_aslor_PR __builtin_HEXAGON_S2_asl_r_p_or + +/* ========================================================================== + Assembly Syntax: Rxx32^=asl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_aslxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_aslxacc_PR __builtin_HEXAGON_S2_asl_r_p_xor + +/* ========================================================================== + Assembly Syntax: Rd32=asl(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_asl_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asl_RR __builtin_HEXAGON_S2_asl_r_r + +/* ========================================================================== + Assembly Syntax: Rx32+=asl(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_aslacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_aslacc_RR __builtin_HEXAGON_S2_asl_r_r_acc + +/* ========================================================================== + Assembly Syntax: Rx32&=asl(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_asland_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asland_RR __builtin_HEXAGON_S2_asl_r_r_and + +/* ========================================================================== + Assembly Syntax: Rx32-=asl(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_aslnac_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_aslnac_RR __builtin_HEXAGON_S2_asl_r_r_nac + +/* ========================================================================== + Assembly Syntax: Rx32|=asl(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_aslor_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_aslor_RR __builtin_HEXAGON_S2_asl_r_r_or + +/* ========================================================================== + Assembly Syntax: Rd32=asl(Rs32,Rt32):sat + C Intrinsic Prototype: Word32 Q6_R_asl_RR_sat(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asl_RR_sat __builtin_HEXAGON_S2_asl_r_r_sat + +/* ========================================================================== + Assembly Syntax: Rdd32=vaslh(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vaslh_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vaslh_PR __builtin_HEXAGON_S2_asl_r_vh + +/* ========================================================================== + Assembly Syntax: Rdd32=vaslw(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vaslw_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vaslw_PR __builtin_HEXAGON_S2_asl_r_vw + +/* ========================================================================== + Assembly Syntax: Rdd32=asr(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_asr_PI(Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asr_PI __builtin_HEXAGON_S2_asr_i_p + +/* ========================================================================== + Assembly Syntax: Rxx32+=asr(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_asracc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asracc_PI __builtin_HEXAGON_S2_asr_i_p_acc + +/* ========================================================================== + Assembly Syntax: Rxx32&=asr(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_asrand_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asrand_PI __builtin_HEXAGON_S2_asr_i_p_and + +/* ========================================================================== + Assembly Syntax: Rxx32-=asr(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_asrnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asrnac_PI __builtin_HEXAGON_S2_asr_i_p_nac + +/* ========================================================================== + Assembly Syntax: Rxx32|=asr(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_asror_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asror_PI __builtin_HEXAGON_S2_asr_i_p_or + +/* ========================================================================== + Assembly Syntax: Rdd32=asr(Rss32,#u6):rnd + C Intrinsic Prototype: Word64 Q6_P_asr_PI_rnd(Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asr_PI_rnd __builtin_HEXAGON_S2_asr_i_p_rnd + +/* ========================================================================== + Assembly Syntax: Rdd32=asrrnd(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_asrrnd_PI(Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_asrrnd_PI __builtin_HEXAGON_S2_asr_i_p_rnd_goodsyntax + +/* ========================================================================== + Assembly Syntax: Rd32=asr(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_asr_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asr_RI __builtin_HEXAGON_S2_asr_i_r + +/* ========================================================================== + Assembly Syntax: Rx32+=asr(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_asracc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asracc_RI __builtin_HEXAGON_S2_asr_i_r_acc + +/* ========================================================================== + Assembly Syntax: Rx32&=asr(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_asrand_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asrand_RI __builtin_HEXAGON_S2_asr_i_r_and + +/* ========================================================================== + Assembly Syntax: Rx32-=asr(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_asrnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asrnac_RI __builtin_HEXAGON_S2_asr_i_r_nac + +/* ========================================================================== + Assembly Syntax: Rx32|=asr(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_asror_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asror_RI __builtin_HEXAGON_S2_asr_i_r_or + +/* ========================================================================== + Assembly Syntax: Rd32=asr(Rs32,#u5):rnd + C Intrinsic Prototype: Word32 Q6_R_asr_RI_rnd(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asr_RI_rnd __builtin_HEXAGON_S2_asr_i_r_rnd + +/* ========================================================================== + Assembly Syntax: Rd32=asrrnd(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_asrrnd_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_asrrnd_RI __builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax + +/* ========================================================================== + Assembly Syntax: Rd32=vasrw(Rss32,#u5) + C Intrinsic Prototype: Word32 Q6_R_vasrw_PI(Word64 Rss, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vasrw_PI __builtin_HEXAGON_S2_asr_i_svw_trun + +/* ========================================================================== + Assembly Syntax: Rdd32=vasrh(Rss32,#u4) + C Intrinsic Prototype: Word64 Q6_P_vasrh_PI(Word64 Rss, Word32 Iu4) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vasrh_PI __builtin_HEXAGON_S2_asr_i_vh + +/* ========================================================================== + Assembly Syntax: Rdd32=vasrw(Rss32,#u5) + C Intrinsic Prototype: Word64 Q6_P_vasrw_PI(Word64 Rss, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vasrw_PI __builtin_HEXAGON_S2_asr_i_vw + +/* ========================================================================== + Assembly Syntax: Rdd32=asr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_asr_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asr_PR __builtin_HEXAGON_S2_asr_r_p + +/* ========================================================================== + Assembly Syntax: Rxx32+=asr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_asracc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asracc_PR __builtin_HEXAGON_S2_asr_r_p_acc + +/* ========================================================================== + Assembly Syntax: Rxx32&=asr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_asrand_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asrand_PR __builtin_HEXAGON_S2_asr_r_p_and + +/* ========================================================================== + Assembly Syntax: Rxx32-=asr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_asrnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asrnac_PR __builtin_HEXAGON_S2_asr_r_p_nac + +/* ========================================================================== + Assembly Syntax: Rxx32|=asr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_asror_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asror_PR __builtin_HEXAGON_S2_asr_r_p_or + +/* ========================================================================== + Assembly Syntax: Rxx32^=asr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_asrxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asrxacc_PR __builtin_HEXAGON_S2_asr_r_p_xor + +/* ========================================================================== + Assembly Syntax: Rd32=asr(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_asr_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asr_RR __builtin_HEXAGON_S2_asr_r_r + +/* ========================================================================== + Assembly Syntax: Rx32+=asr(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_asracc_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asracc_RR __builtin_HEXAGON_S2_asr_r_r_acc + +/* ========================================================================== + Assembly Syntax: Rx32&=asr(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_asrand_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asrand_RR __builtin_HEXAGON_S2_asr_r_r_and + +/* ========================================================================== + Assembly Syntax: Rx32-=asr(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_asrnac_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asrnac_RR __builtin_HEXAGON_S2_asr_r_r_nac + +/* ========================================================================== + Assembly Syntax: Rx32|=asr(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_asror_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asror_RR __builtin_HEXAGON_S2_asr_r_r_or + +/* ========================================================================== + Assembly Syntax: Rd32=asr(Rs32,Rt32):sat + C Intrinsic Prototype: Word32 Q6_R_asr_RR_sat(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asr_RR_sat __builtin_HEXAGON_S2_asr_r_r_sat + +/* ========================================================================== + Assembly Syntax: Rd32=vasrw(Rss32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_vasrw_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vasrw_PR __builtin_HEXAGON_S2_asr_r_svw_trun + +/* ========================================================================== + Assembly Syntax: Rdd32=vasrh(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vasrh_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vasrh_PR __builtin_HEXAGON_S2_asr_r_vh + +/* ========================================================================== + Assembly Syntax: Rdd32=vasrw(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vasrw_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vasrw_PR __builtin_HEXAGON_S2_asr_r_vw + +/* ========================================================================== + Assembly Syntax: Rd32=brev(Rs32) + C Intrinsic Prototype: Word32 Q6_R_brev_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_brev_R __builtin_HEXAGON_S2_brev + +/* ========================================================================== + Assembly Syntax: Rdd32=brev(Rss32) + C Intrinsic Prototype: Word64 Q6_P_brev_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_brev_P __builtin_HEXAGON_S2_brevp + +/* ========================================================================== + Assembly Syntax: Rd32=cl0(Rs32) + C Intrinsic Prototype: Word32 Q6_R_cl0_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cl0_R __builtin_HEXAGON_S2_cl0 + +/* ========================================================================== + Assembly Syntax: Rd32=cl0(Rss32) + C Intrinsic Prototype: Word32 Q6_R_cl0_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cl0_P __builtin_HEXAGON_S2_cl0p + +/* ========================================================================== + Assembly Syntax: Rd32=cl1(Rs32) + C Intrinsic Prototype: Word32 Q6_R_cl1_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cl1_R __builtin_HEXAGON_S2_cl1 + +/* ========================================================================== + Assembly Syntax: Rd32=cl1(Rss32) + C Intrinsic Prototype: Word32 Q6_R_cl1_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cl1_P __builtin_HEXAGON_S2_cl1p + +/* ========================================================================== + Assembly Syntax: Rd32=clb(Rs32) + C Intrinsic Prototype: Word32 Q6_R_clb_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_clb_R __builtin_HEXAGON_S2_clb + +/* ========================================================================== + Assembly Syntax: Rd32=normamt(Rs32) + C Intrinsic Prototype: Word32 Q6_R_normamt_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_normamt_R __builtin_HEXAGON_S2_clbnorm + +/* ========================================================================== + Assembly Syntax: Rd32=clb(Rss32) + C Intrinsic Prototype: Word32 Q6_R_clb_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_clb_P __builtin_HEXAGON_S2_clbp + +/* ========================================================================== + Assembly Syntax: Rd32=clrbit(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_clrbit_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_clrbit_RI __builtin_HEXAGON_S2_clrbit_i + +/* ========================================================================== + Assembly Syntax: Rd32=clrbit(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_clrbit_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_clrbit_RR __builtin_HEXAGON_S2_clrbit_r + +/* ========================================================================== + Assembly Syntax: Rd32=ct0(Rs32) + C Intrinsic Prototype: Word32 Q6_R_ct0_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_ct0_R __builtin_HEXAGON_S2_ct0 + +/* ========================================================================== + Assembly Syntax: Rd32=ct0(Rss32) + C Intrinsic Prototype: Word32 Q6_R_ct0_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_ct0_P __builtin_HEXAGON_S2_ct0p + +/* ========================================================================== + Assembly Syntax: Rd32=ct1(Rs32) + C Intrinsic Prototype: Word32 Q6_R_ct1_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_ct1_R __builtin_HEXAGON_S2_ct1 + +/* ========================================================================== + Assembly Syntax: Rd32=ct1(Rss32) + C Intrinsic Prototype: Word32 Q6_R_ct1_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_ct1_P __builtin_HEXAGON_S2_ct1p + +/* ========================================================================== + Assembly Syntax: Rdd32=deinterleave(Rss32) + C Intrinsic Prototype: Word64 Q6_P_deinterleave_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_deinterleave_P __builtin_HEXAGON_S2_deinterleave + +/* ========================================================================== + Assembly Syntax: Rd32=extractu(Rs32,#u5,#U5) + C Intrinsic Prototype: Word32 Q6_R_extractu_RII(Word32 Rs, Word32 Iu5, Word32 IU5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_extractu_RII __builtin_HEXAGON_S2_extractu + +/* ========================================================================== + Assembly Syntax: Rd32=extractu(Rs32,Rtt32) + C Intrinsic Prototype: Word32 Q6_R_extractu_RP(Word32 Rs, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_extractu_RP __builtin_HEXAGON_S2_extractu_rp + +/* ========================================================================== + Assembly Syntax: Rdd32=extractu(Rss32,#u6,#U6) + C Intrinsic Prototype: Word64 Q6_P_extractu_PII(Word64 Rss, Word32 Iu6, Word32 IU6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_extractu_PII __builtin_HEXAGON_S2_extractup + +/* ========================================================================== + Assembly Syntax: Rdd32=extractu(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_extractu_PP(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_extractu_PP __builtin_HEXAGON_S2_extractup_rp + +/* ========================================================================== + Assembly Syntax: Rx32=insert(Rs32,#u5,#U5) + C Intrinsic Prototype: Word32 Q6_R_insert_RII(Word32 Rx, Word32 Rs, Word32 Iu5, Word32 IU5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_insert_RII __builtin_HEXAGON_S2_insert + +/* ========================================================================== + Assembly Syntax: Rx32=insert(Rs32,Rtt32) + C Intrinsic Prototype: Word32 Q6_R_insert_RP(Word32 Rx, Word32 Rs, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_insert_RP __builtin_HEXAGON_S2_insert_rp + +/* ========================================================================== + Assembly Syntax: Rxx32=insert(Rss32,#u6,#U6) + C Intrinsic Prototype: Word64 Q6_P_insert_PII(Word64 Rxx, Word64 Rss, Word32 Iu6, Word32 IU6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_insert_PII __builtin_HEXAGON_S2_insertp + +/* ========================================================================== + Assembly Syntax: Rxx32=insert(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_insert_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_insert_PP __builtin_HEXAGON_S2_insertp_rp + +/* ========================================================================== + Assembly Syntax: Rdd32=interleave(Rss32) + C Intrinsic Prototype: Word64 Q6_P_interleave_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_interleave_P __builtin_HEXAGON_S2_interleave + +/* ========================================================================== + Assembly Syntax: Rdd32=lfs(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_lfs_PP(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lfs_PP __builtin_HEXAGON_S2_lfsp + +/* ========================================================================== + Assembly Syntax: Rdd32=lsl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lsl_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsl_PR __builtin_HEXAGON_S2_lsl_r_p + +/* ========================================================================== + Assembly Syntax: Rxx32+=lsl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lslacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lslacc_PR __builtin_HEXAGON_S2_lsl_r_p_acc + +/* ========================================================================== + Assembly Syntax: Rxx32&=lsl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lsland_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsland_PR __builtin_HEXAGON_S2_lsl_r_p_and + +/* ========================================================================== + Assembly Syntax: Rxx32-=lsl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lslnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lslnac_PR __builtin_HEXAGON_S2_lsl_r_p_nac + +/* ========================================================================== + Assembly Syntax: Rxx32|=lsl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lslor_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lslor_PR __builtin_HEXAGON_S2_lsl_r_p_or + +/* ========================================================================== + Assembly Syntax: Rxx32^=lsl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lslxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lslxacc_PR __builtin_HEXAGON_S2_lsl_r_p_xor + +/* ========================================================================== + Assembly Syntax: Rd32=lsl(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_lsl_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsl_RR __builtin_HEXAGON_S2_lsl_r_r + +/* ========================================================================== + Assembly Syntax: Rx32+=lsl(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_lslacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lslacc_RR __builtin_HEXAGON_S2_lsl_r_r_acc + +/* ========================================================================== + Assembly Syntax: Rx32&=lsl(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_lsland_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsland_RR __builtin_HEXAGON_S2_lsl_r_r_and + +/* ========================================================================== + Assembly Syntax: Rx32-=lsl(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_lslnac_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lslnac_RR __builtin_HEXAGON_S2_lsl_r_r_nac + +/* ========================================================================== + Assembly Syntax: Rx32|=lsl(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_lslor_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lslor_RR __builtin_HEXAGON_S2_lsl_r_r_or + +/* ========================================================================== + Assembly Syntax: Rdd32=vlslh(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vlslh_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vlslh_PR __builtin_HEXAGON_S2_lsl_r_vh + +/* ========================================================================== + Assembly Syntax: Rdd32=vlslw(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vlslw_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vlslw_PR __builtin_HEXAGON_S2_lsl_r_vw + +/* ========================================================================== + Assembly Syntax: Rdd32=lsr(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_lsr_PI(Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsr_PI __builtin_HEXAGON_S2_lsr_i_p + +/* ========================================================================== + Assembly Syntax: Rxx32+=lsr(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_lsracc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsracc_PI __builtin_HEXAGON_S2_lsr_i_p_acc + +/* ========================================================================== + Assembly Syntax: Rxx32&=lsr(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_lsrand_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsrand_PI __builtin_HEXAGON_S2_lsr_i_p_and + +/* ========================================================================== + Assembly Syntax: Rxx32-=lsr(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_lsrnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsrnac_PI __builtin_HEXAGON_S2_lsr_i_p_nac + +/* ========================================================================== + Assembly Syntax: Rxx32|=lsr(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_lsror_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsror_PI __builtin_HEXAGON_S2_lsr_i_p_or + +/* ========================================================================== + Assembly Syntax: Rxx32^=lsr(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_lsrxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsrxacc_PI __builtin_HEXAGON_S2_lsr_i_p_xacc + +/* ========================================================================== + Assembly Syntax: Rd32=lsr(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_lsr_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsr_RI __builtin_HEXAGON_S2_lsr_i_r + +/* ========================================================================== + Assembly Syntax: Rx32+=lsr(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_lsracc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsracc_RI __builtin_HEXAGON_S2_lsr_i_r_acc + +/* ========================================================================== + Assembly Syntax: Rx32&=lsr(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_lsrand_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsrand_RI __builtin_HEXAGON_S2_lsr_i_r_and + +/* ========================================================================== + Assembly Syntax: Rx32-=lsr(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_lsrnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsrnac_RI __builtin_HEXAGON_S2_lsr_i_r_nac + +/* ========================================================================== + Assembly Syntax: Rx32|=lsr(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_lsror_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsror_RI __builtin_HEXAGON_S2_lsr_i_r_or + +/* ========================================================================== + Assembly Syntax: Rx32^=lsr(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_lsrxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsrxacc_RI __builtin_HEXAGON_S2_lsr_i_r_xacc + +/* ========================================================================== + Assembly Syntax: Rdd32=vlsrh(Rss32,#u4) + C Intrinsic Prototype: Word64 Q6_P_vlsrh_PI(Word64 Rss, Word32 Iu4) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vlsrh_PI __builtin_HEXAGON_S2_lsr_i_vh + +/* ========================================================================== + Assembly Syntax: Rdd32=vlsrw(Rss32,#u5) + C Intrinsic Prototype: Word64 Q6_P_vlsrw_PI(Word64 Rss, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vlsrw_PI __builtin_HEXAGON_S2_lsr_i_vw + +/* ========================================================================== + Assembly Syntax: Rdd32=lsr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lsr_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsr_PR __builtin_HEXAGON_S2_lsr_r_p + +/* ========================================================================== + Assembly Syntax: Rxx32+=lsr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lsracc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsracc_PR __builtin_HEXAGON_S2_lsr_r_p_acc + +/* ========================================================================== + Assembly Syntax: Rxx32&=lsr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lsrand_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsrand_PR __builtin_HEXAGON_S2_lsr_r_p_and + +/* ========================================================================== + Assembly Syntax: Rxx32-=lsr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lsrnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsrnac_PR __builtin_HEXAGON_S2_lsr_r_p_nac + +/* ========================================================================== + Assembly Syntax: Rxx32|=lsr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lsror_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsror_PR __builtin_HEXAGON_S2_lsr_r_p_or + +/* ========================================================================== + Assembly Syntax: Rxx32^=lsr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lsrxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsrxacc_PR __builtin_HEXAGON_S2_lsr_r_p_xor + +/* ========================================================================== + Assembly Syntax: Rd32=lsr(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_lsr_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsr_RR __builtin_HEXAGON_S2_lsr_r_r + +/* ========================================================================== + Assembly Syntax: Rx32+=lsr(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_lsracc_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsracc_RR __builtin_HEXAGON_S2_lsr_r_r_acc + +/* ========================================================================== + Assembly Syntax: Rx32&=lsr(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_lsrand_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsrand_RR __builtin_HEXAGON_S2_lsr_r_r_and + +/* ========================================================================== + Assembly Syntax: Rx32-=lsr(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_lsrnac_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsrnac_RR __builtin_HEXAGON_S2_lsr_r_r_nac + +/* ========================================================================== + Assembly Syntax: Rx32|=lsr(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_lsror_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsror_RR __builtin_HEXAGON_S2_lsr_r_r_or + +/* ========================================================================== + Assembly Syntax: Rdd32=vlsrh(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vlsrh_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vlsrh_PR __builtin_HEXAGON_S2_lsr_r_vh + +/* ========================================================================== + Assembly Syntax: Rdd32=vlsrw(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vlsrw_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vlsrw_PR __builtin_HEXAGON_S2_lsr_r_vw + +/* ========================================================================== + Assembly Syntax: Rdd32=packhl(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_packhl_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_packhl_RR __builtin_HEXAGON_S2_packhl + +/* ========================================================================== + Assembly Syntax: Rd32=parity(Rss32,Rtt32) + C Intrinsic Prototype: Word32 Q6_R_parity_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_parity_PP __builtin_HEXAGON_S2_parityp + +/* ========================================================================== + Assembly Syntax: Rd32=setbit(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_setbit_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_setbit_RI __builtin_HEXAGON_S2_setbit_i + +/* ========================================================================== + Assembly Syntax: Rd32=setbit(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_setbit_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_setbit_RR __builtin_HEXAGON_S2_setbit_r + +/* ========================================================================== + Assembly Syntax: Rdd32=shuffeb(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_shuffeb_PP(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_shuffeb_PP __builtin_HEXAGON_S2_shuffeb + +/* ========================================================================== + Assembly Syntax: Rdd32=shuffeh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_shuffeh_PP(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_shuffeh_PP __builtin_HEXAGON_S2_shuffeh + +/* ========================================================================== + Assembly Syntax: Rdd32=shuffob(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_shuffob_PP(Word64 Rtt, Word64 Rss) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_shuffob_PP __builtin_HEXAGON_S2_shuffob + +/* ========================================================================== + Assembly Syntax: Rdd32=shuffoh(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_shuffoh_PP(Word64 Rtt, Word64 Rss) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_shuffoh_PP __builtin_HEXAGON_S2_shuffoh + +/* ========================================================================== + Assembly Syntax: memb(Rx32++#s4:0:circ(Mu2))=Rt32 + C Intrinsic Prototype: void Q6_memb_IMR_circ(void** Rx, Word32 Is4_0, Word32 Mu, Word32 Rt, void* BaseAddress) + Instruction Type: ST + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_memb_IMR_circ __builtin_HEXAGON_S2_storerb_pci + +/* ========================================================================== + Assembly Syntax: memb(Rx32++I:circ(Mu2))=Rt32 + C Intrinsic Prototype: void Q6_memb_MR_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress) + Instruction Type: ST + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_memb_MR_circ __builtin_HEXAGON_S2_storerb_pcr + +/* ========================================================================== + Assembly Syntax: memd(Rx32++#s4:3:circ(Mu2))=Rtt32 + C Intrinsic Prototype: void Q6_memd_IMP_circ(void** Rx, Word32 Is4_3, Word32 Mu, Word64 Rtt, void* BaseAddress) + Instruction Type: ST + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_memd_IMP_circ __builtin_HEXAGON_S2_storerd_pci + +/* ========================================================================== + Assembly Syntax: memd(Rx32++I:circ(Mu2))=Rtt32 + C Intrinsic Prototype: void Q6_memd_MP_circ(void** Rx, Word32 Mu, Word64 Rtt, void* BaseAddress) + Instruction Type: ST + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_memd_MP_circ __builtin_HEXAGON_S2_storerd_pcr + +/* ========================================================================== + Assembly Syntax: memh(Rx32++#s4:1:circ(Mu2))=Rt32.h + C Intrinsic Prototype: void Q6_memh_IMRh_circ(void** Rx, Word32 Is4_1, Word32 Mu, Word32 Rt, void* BaseAddress) + Instruction Type: ST + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_memh_IMRh_circ __builtin_HEXAGON_S2_storerf_pci + +/* ========================================================================== + Assembly Syntax: memh(Rx32++I:circ(Mu2))=Rt32.h + C Intrinsic Prototype: void Q6_memh_MRh_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress) + Instruction Type: ST + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_memh_MRh_circ __builtin_HEXAGON_S2_storerf_pcr + +/* ========================================================================== + Assembly Syntax: memh(Rx32++#s4:1:circ(Mu2))=Rt32 + C Intrinsic Prototype: void Q6_memh_IMR_circ(void** Rx, Word32 Is4_1, Word32 Mu, Word32 Rt, void* BaseAddress) + Instruction Type: ST + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_memh_IMR_circ __builtin_HEXAGON_S2_storerh_pci + +/* ========================================================================== + Assembly Syntax: memh(Rx32++I:circ(Mu2))=Rt32 + C Intrinsic Prototype: void Q6_memh_MR_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress) + Instruction Type: ST + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_memh_MR_circ __builtin_HEXAGON_S2_storerh_pcr + +/* ========================================================================== + Assembly Syntax: memw(Rx32++#s4:2:circ(Mu2))=Rt32 + C Intrinsic Prototype: void Q6_memw_IMR_circ(void** Rx, Word32 Is4_2, Word32 Mu, Word32 Rt, void* BaseAddress) + Instruction Type: ST + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_memw_IMR_circ __builtin_HEXAGON_S2_storeri_pci + +/* ========================================================================== + Assembly Syntax: memw(Rx32++I:circ(Mu2))=Rt32 + C Intrinsic Prototype: void Q6_memw_MR_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress) + Instruction Type: ST + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_memw_MR_circ __builtin_HEXAGON_S2_storeri_pcr + +/* ========================================================================== + Assembly Syntax: Rd32=vsathb(Rs32) + C Intrinsic Prototype: Word32 Q6_R_vsathb_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vsathb_R __builtin_HEXAGON_S2_svsathb + +/* ========================================================================== + Assembly Syntax: Rd32=vsathub(Rs32) + C Intrinsic Prototype: Word32 Q6_R_vsathub_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vsathub_R __builtin_HEXAGON_S2_svsathub + +/* ========================================================================== + Assembly Syntax: Rx32=tableidxb(Rs32,#u4,#U5) + C Intrinsic Prototype: Word32 Q6_R_tableidxb_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5) + Instruction Type: S_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_tableidxb_RII __builtin_HEXAGON_S2_tableidxb_goodsyntax + +/* ========================================================================== + Assembly Syntax: Rx32=tableidxd(Rs32,#u4,#U5) + C Intrinsic Prototype: Word32 Q6_R_tableidxd_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5) + Instruction Type: S_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_tableidxd_RII __builtin_HEXAGON_S2_tableidxd_goodsyntax + +/* ========================================================================== + Assembly Syntax: Rx32=tableidxh(Rs32,#u4,#U5) + C Intrinsic Prototype: Word32 Q6_R_tableidxh_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5) + Instruction Type: S_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_tableidxh_RII __builtin_HEXAGON_S2_tableidxh_goodsyntax + +/* ========================================================================== + Assembly Syntax: Rx32=tableidxw(Rs32,#u4,#U5) + C Intrinsic Prototype: Word32 Q6_R_tableidxw_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5) + Instruction Type: S_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_tableidxw_RII __builtin_HEXAGON_S2_tableidxw_goodsyntax + +/* ========================================================================== + Assembly Syntax: Rd32=togglebit(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_togglebit_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_togglebit_RI __builtin_HEXAGON_S2_togglebit_i + +/* ========================================================================== + Assembly Syntax: Rd32=togglebit(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_togglebit_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_togglebit_RR __builtin_HEXAGON_S2_togglebit_r + +/* ========================================================================== + Assembly Syntax: Pd4=tstbit(Rs32,#u5) + C Intrinsic Prototype: Byte Q6_p_tstbit_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_tstbit_RI __builtin_HEXAGON_S2_tstbit_i + +/* ========================================================================== + Assembly Syntax: Pd4=tstbit(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_tstbit_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_tstbit_RR __builtin_HEXAGON_S2_tstbit_r + +/* ========================================================================== + Assembly Syntax: Rdd32=valignb(Rtt32,Rss32,#u3) + C Intrinsic Prototype: Word64 Q6_P_valignb_PPI(Word64 Rtt, Word64 Rss, Word32 Iu3) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_valignb_PPI __builtin_HEXAGON_S2_valignib + +/* ========================================================================== + Assembly Syntax: Rdd32=valignb(Rtt32,Rss32,Pu4) + C Intrinsic Prototype: Word64 Q6_P_valignb_PPp(Word64 Rtt, Word64 Rss, Byte Pu) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_valignb_PPp __builtin_HEXAGON_S2_valignrb + +/* ========================================================================== + Assembly Syntax: Rdd32=vcnegh(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vcnegh_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vcnegh_PR __builtin_HEXAGON_S2_vcnegh + +/* ========================================================================== + Assembly Syntax: Rdd32=vcrotate(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vcrotate_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vcrotate_PR __builtin_HEXAGON_S2_vcrotate + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrcnegh(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vrcneghacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrcneghacc_PR __builtin_HEXAGON_S2_vrcnegh + +/* ========================================================================== + Assembly Syntax: Rd32=vrndwh(Rss32) + C Intrinsic Prototype: Word32 Q6_R_vrndwh_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vrndwh_P __builtin_HEXAGON_S2_vrndpackwh + +/* ========================================================================== + Assembly Syntax: Rd32=vrndwh(Rss32):sat + C Intrinsic Prototype: Word32 Q6_R_vrndwh_P_sat(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vrndwh_P_sat __builtin_HEXAGON_S2_vrndpackwhs + +/* ========================================================================== + Assembly Syntax: Rd32=vsathb(Rss32) + C Intrinsic Prototype: Word32 Q6_R_vsathb_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vsathb_P __builtin_HEXAGON_S2_vsathb + +/* ========================================================================== + Assembly Syntax: Rdd32=vsathb(Rss32) + C Intrinsic Prototype: Word64 Q6_P_vsathb_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsathb_P __builtin_HEXAGON_S2_vsathb_nopack + +/* ========================================================================== + Assembly Syntax: Rd32=vsathub(Rss32) + C Intrinsic Prototype: Word32 Q6_R_vsathub_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vsathub_P __builtin_HEXAGON_S2_vsathub + +/* ========================================================================== + Assembly Syntax: Rdd32=vsathub(Rss32) + C Intrinsic Prototype: Word64 Q6_P_vsathub_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsathub_P __builtin_HEXAGON_S2_vsathub_nopack + +/* ========================================================================== + Assembly Syntax: Rd32=vsatwh(Rss32) + C Intrinsic Prototype: Word32 Q6_R_vsatwh_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vsatwh_P __builtin_HEXAGON_S2_vsatwh + +/* ========================================================================== + Assembly Syntax: Rdd32=vsatwh(Rss32) + C Intrinsic Prototype: Word64 Q6_P_vsatwh_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsatwh_P __builtin_HEXAGON_S2_vsatwh_nopack + +/* ========================================================================== + Assembly Syntax: Rd32=vsatwuh(Rss32) + C Intrinsic Prototype: Word32 Q6_R_vsatwuh_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vsatwuh_P __builtin_HEXAGON_S2_vsatwuh + +/* ========================================================================== + Assembly Syntax: Rdd32=vsatwuh(Rss32) + C Intrinsic Prototype: Word64 Q6_P_vsatwuh_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsatwuh_P __builtin_HEXAGON_S2_vsatwuh_nopack + +/* ========================================================================== + Assembly Syntax: Rd32=vsplatb(Rs32) + C Intrinsic Prototype: Word32 Q6_R_vsplatb_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vsplatb_R __builtin_HEXAGON_S2_vsplatrb + +/* ========================================================================== + Assembly Syntax: Rdd32=vsplath(Rs32) + C Intrinsic Prototype: Word64 Q6_P_vsplath_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsplath_R __builtin_HEXAGON_S2_vsplatrh + +/* ========================================================================== + Assembly Syntax: Rdd32=vspliceb(Rss32,Rtt32,#u3) + C Intrinsic Prototype: Word64 Q6_P_vspliceb_PPI(Word64 Rss, Word64 Rtt, Word32 Iu3) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vspliceb_PPI __builtin_HEXAGON_S2_vspliceib + +/* ========================================================================== + Assembly Syntax: Rdd32=vspliceb(Rss32,Rtt32,Pu4) + C Intrinsic Prototype: Word64 Q6_P_vspliceb_PPp(Word64 Rss, Word64 Rtt, Byte Pu) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vspliceb_PPp __builtin_HEXAGON_S2_vsplicerb + +/* ========================================================================== + Assembly Syntax: Rdd32=vsxtbh(Rs32) + C Intrinsic Prototype: Word64 Q6_P_vsxtbh_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsxtbh_R __builtin_HEXAGON_S2_vsxtbh + +/* ========================================================================== + Assembly Syntax: Rdd32=vsxthw(Rs32) + C Intrinsic Prototype: Word64 Q6_P_vsxthw_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsxthw_R __builtin_HEXAGON_S2_vsxthw + +/* ========================================================================== + Assembly Syntax: Rd32=vtrunehb(Rss32) + C Intrinsic Prototype: Word32 Q6_R_vtrunehb_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vtrunehb_P __builtin_HEXAGON_S2_vtrunehb + +/* ========================================================================== + Assembly Syntax: Rdd32=vtrunewh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vtrunewh_PP(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vtrunewh_PP __builtin_HEXAGON_S2_vtrunewh + +/* ========================================================================== + Assembly Syntax: Rd32=vtrunohb(Rss32) + C Intrinsic Prototype: Word32 Q6_R_vtrunohb_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vtrunohb_P __builtin_HEXAGON_S2_vtrunohb + +/* ========================================================================== + Assembly Syntax: Rdd32=vtrunowh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vtrunowh_PP(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vtrunowh_PP __builtin_HEXAGON_S2_vtrunowh + +/* ========================================================================== + Assembly Syntax: Rdd32=vzxtbh(Rs32) + C Intrinsic Prototype: Word64 Q6_P_vzxtbh_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vzxtbh_R __builtin_HEXAGON_S2_vzxtbh + +/* ========================================================================== + Assembly Syntax: Rdd32=vzxthw(Rs32) + C Intrinsic Prototype: Word64 Q6_P_vzxthw_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vzxthw_R __builtin_HEXAGON_S2_vzxthw + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rs32,add(Ru32,#s6)) + C Intrinsic Prototype: Word32 Q6_R_add_add_RRI(Word32 Rs, Word32 Ru, Word32 Is6) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_add_RRI __builtin_HEXAGON_S4_addaddi + +/* ========================================================================== + Assembly Syntax: Rx32=add(#u8,asl(Rx32,#U5)) + C Intrinsic Prototype: Word32 Q6_R_add_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_asl_IRI __builtin_HEXAGON_S4_addi_asl_ri + +/* ========================================================================== + Assembly Syntax: Rx32=add(#u8,lsr(Rx32,#U5)) + C Intrinsic Prototype: Word32 Q6_R_add_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_lsr_IRI __builtin_HEXAGON_S4_addi_lsr_ri + +/* ========================================================================== + Assembly Syntax: Rx32=and(#u8,asl(Rx32,#U5)) + C Intrinsic Prototype: Word32 Q6_R_and_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_and_asl_IRI __builtin_HEXAGON_S4_andi_asl_ri + +/* ========================================================================== + Assembly Syntax: Rx32=and(#u8,lsr(Rx32,#U5)) + C Intrinsic Prototype: Word32 Q6_R_and_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_and_lsr_IRI __builtin_HEXAGON_S4_andi_lsr_ri + +/* ========================================================================== + Assembly Syntax: Rd32=add(clb(Rs32),#s6) + C Intrinsic Prototype: Word32 Q6_R_add_clb_RI(Word32 Rs, Word32 Is6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_clb_RI __builtin_HEXAGON_S4_clbaddi + +/* ========================================================================== + Assembly Syntax: Rd32=add(clb(Rss32),#s6) + C Intrinsic Prototype: Word32 Q6_R_add_clb_PI(Word64 Rss, Word32 Is6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_clb_PI __builtin_HEXAGON_S4_clbpaddi + +/* ========================================================================== + Assembly Syntax: Rd32=normamt(Rss32) + C Intrinsic Prototype: Word32 Q6_R_normamt_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_normamt_P __builtin_HEXAGON_S4_clbpnorm + +/* ========================================================================== + Assembly Syntax: Rd32=extract(Rs32,#u5,#U5) + C Intrinsic Prototype: Word32 Q6_R_extract_RII(Word32 Rs, Word32 Iu5, Word32 IU5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_extract_RII __builtin_HEXAGON_S4_extract + +/* ========================================================================== + Assembly Syntax: Rd32=extract(Rs32,Rtt32) + C Intrinsic Prototype: Word32 Q6_R_extract_RP(Word32 Rs, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_extract_RP __builtin_HEXAGON_S4_extract_rp + +/* ========================================================================== + Assembly Syntax: Rdd32=extract(Rss32,#u6,#U6) + C Intrinsic Prototype: Word64 Q6_P_extract_PII(Word64 Rss, Word32 Iu6, Word32 IU6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_extract_PII __builtin_HEXAGON_S4_extractp + +/* ========================================================================== + Assembly Syntax: Rdd32=extract(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_extract_PP(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_extract_PP __builtin_HEXAGON_S4_extractp_rp + +/* ========================================================================== + Assembly Syntax: Rd32=lsl(#s6,Rt32) + C Intrinsic Prototype: Word32 Q6_R_lsl_IR(Word32 Is6, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsl_IR __builtin_HEXAGON_S4_lsli + +/* ========================================================================== + Assembly Syntax: Pd4=!tstbit(Rs32,#u5) + C Intrinsic Prototype: Byte Q6_p_not_tstbit_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_not_tstbit_RI __builtin_HEXAGON_S4_ntstbit_i + +/* ========================================================================== + Assembly Syntax: Pd4=!tstbit(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_not_tstbit_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_not_tstbit_RR __builtin_HEXAGON_S4_ntstbit_r + +/* ========================================================================== + Assembly Syntax: Rx32|=and(Rs32,#s10) + C Intrinsic Prototype: Word32 Q6_R_andor_RI(Word32 Rx, Word32 Rs, Word32 Is10) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_andor_RI __builtin_HEXAGON_S4_or_andi + +/* ========================================================================== + Assembly Syntax: Rx32=or(Ru32,and(Rx32,#s10)) + C Intrinsic Prototype: Word32 Q6_R_or_and_RRI(Word32 Ru, Word32 Rx, Word32 Is10) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_or_and_RRI __builtin_HEXAGON_S4_or_andix + +/* ========================================================================== + Assembly Syntax: Rx32|=or(Rs32,#s10) + C Intrinsic Prototype: Word32 Q6_R_oror_RI(Word32 Rx, Word32 Rs, Word32 Is10) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_oror_RI __builtin_HEXAGON_S4_or_ori + +/* ========================================================================== + Assembly Syntax: Rx32=or(#u8,asl(Rx32,#U5)) + C Intrinsic Prototype: Word32 Q6_R_or_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_or_asl_IRI __builtin_HEXAGON_S4_ori_asl_ri + +/* ========================================================================== + Assembly Syntax: Rx32=or(#u8,lsr(Rx32,#U5)) + C Intrinsic Prototype: Word32 Q6_R_or_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_or_lsr_IRI __builtin_HEXAGON_S4_ori_lsr_ri + +/* ========================================================================== + Assembly Syntax: Rd32=parity(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_parity_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_parity_RR __builtin_HEXAGON_S4_parity + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rs32,sub(#s6,Ru32)) + C Intrinsic Prototype: Word32 Q6_R_add_sub_RIR(Word32 Rs, Word32 Is6, Word32 Ru) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_sub_RIR __builtin_HEXAGON_S4_subaddi + +/* ========================================================================== + Assembly Syntax: Rx32=sub(#u8,asl(Rx32,#U5)) + C Intrinsic Prototype: Word32 Q6_R_sub_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_asl_IRI __builtin_HEXAGON_S4_subi_asl_ri + +/* ========================================================================== + Assembly Syntax: Rx32=sub(#u8,lsr(Rx32,#U5)) + C Intrinsic Prototype: Word32 Q6_R_sub_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_lsr_IRI __builtin_HEXAGON_S4_subi_lsr_ri + +/* ========================================================================== + Assembly Syntax: Rdd32=vrcrotate(Rss32,Rt32,#u2) + C Intrinsic Prototype: Word64 Q6_P_vrcrotate_PRI(Word64 Rss, Word32 Rt, Word32 Iu2) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrcrotate_PRI __builtin_HEXAGON_S4_vrcrotate + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrcrotate(Rss32,Rt32,#u2) + C Intrinsic Prototype: Word64 Q6_P_vrcrotateacc_PRI(Word64 Rxx, Word64 Rss, Word32 Rt, Word32 Iu2) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrcrotateacc_PRI __builtin_HEXAGON_S4_vrcrotate_acc + +/* ========================================================================== + Assembly Syntax: Rdd32=vxaddsubh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vxaddsubh_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vxaddsubh_PP_sat __builtin_HEXAGON_S4_vxaddsubh + +/* ========================================================================== + Assembly Syntax: Rdd32=vxaddsubh(Rss32,Rtt32):rnd:>>1:sat + C Intrinsic Prototype: Word64 Q6_P_vxaddsubh_PP_rnd_rs1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vxaddsubh_PP_rnd_rs1_sat __builtin_HEXAGON_S4_vxaddsubhr + +/* ========================================================================== + Assembly Syntax: Rdd32=vxaddsubw(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vxaddsubw_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vxaddsubw_PP_sat __builtin_HEXAGON_S4_vxaddsubw + +/* ========================================================================== + Assembly Syntax: Rdd32=vxsubaddh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vxsubaddh_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vxsubaddh_PP_sat __builtin_HEXAGON_S4_vxsubaddh + +/* ========================================================================== + Assembly Syntax: Rdd32=vxsubaddh(Rss32,Rtt32):rnd:>>1:sat + C Intrinsic Prototype: Word64 Q6_P_vxsubaddh_PP_rnd_rs1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vxsubaddh_PP_rnd_rs1_sat __builtin_HEXAGON_S4_vxsubaddhr + +/* ========================================================================== + Assembly Syntax: Rdd32=vxsubaddw(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vxsubaddw_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vxsubaddw_PP_sat __builtin_HEXAGON_S4_vxsubaddw + +/* ========================================================================== + Assembly Syntax: Rd32=vasrhub(Rss32,#u4):rnd:sat + C Intrinsic Prototype: Word32 Q6_R_vasrhub_PI_rnd_sat(Word64 Rss, Word32 Iu4) + Instruction Type: S_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_vasrhub_PI_rnd_sat __builtin_HEXAGON_S5_asrhub_rnd_sat_goodsyntax + +/* ========================================================================== + Assembly Syntax: Rd32=vasrhub(Rss32,#u4):sat + C Intrinsic Prototype: Word32 Q6_R_vasrhub_PI_sat(Word64 Rss, Word32 Iu4) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vasrhub_PI_sat __builtin_HEXAGON_S5_asrhub_sat + +/* ========================================================================== + Assembly Syntax: Rd32=popcount(Rss32) + C Intrinsic Prototype: Word32 Q6_R_popcount_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_popcount_P __builtin_HEXAGON_S5_popcountp + +/* ========================================================================== + Assembly Syntax: Rdd32=vasrh(Rss32,#u4):rnd + C Intrinsic Prototype: Word64 Q6_P_vasrh_PI_rnd(Word64 Rss, Word32 Iu4) + Instruction Type: S_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_vasrh_PI_rnd __builtin_HEXAGON_S5_vasrhrnd_goodsyntax + +/* ========================================================================== + Assembly Syntax: dccleana(Rs32) + C Intrinsic Prototype: void Q6_dccleana_A(Address Rs) + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_dccleana_A __builtin_HEXAGON_Y2_dccleana + +/* ========================================================================== + Assembly Syntax: dccleaninva(Rs32) + C Intrinsic Prototype: void Q6_dccleaninva_A(Address Rs) + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_dccleaninva_A __builtin_HEXAGON_Y2_dccleaninva + +/* ========================================================================== + Assembly Syntax: dcfetch(Rs32) + C Intrinsic Prototype: void Q6_dcfetch_A(Address Rs) + Instruction Type: MAPPING + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_dcfetch_A __builtin_HEXAGON_Y2_dcfetch + +/* ========================================================================== + Assembly Syntax: dcinva(Rs32) + C Intrinsic Prototype: void Q6_dcinva_A(Address Rs) + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_dcinva_A __builtin_HEXAGON_Y2_dcinva + +/* ========================================================================== + Assembly Syntax: dczeroa(Rs32) + C Intrinsic Prototype: void Q6_dczeroa_A(Address Rs) + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_dczeroa_A __builtin_HEXAGON_Y2_dczeroa + +/* ========================================================================== + Assembly Syntax: l2fetch(Rs32,Rt32) + C Intrinsic Prototype: void Q6_l2fetch_AR(Address Rs, Word32 Rt) + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_l2fetch_AR __builtin_HEXAGON_Y4_l2fetch + +/* ========================================================================== + Assembly Syntax: l2fetch(Rs32,Rtt32) + C Intrinsic Prototype: void Q6_l2fetch_AP(Address Rs, Word64 Rtt) + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_l2fetch_AP __builtin_HEXAGON_Y5_l2fetch + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rdd32=rol(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_rol_PI(Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_rol_PI __builtin_HEXAGON_S6_rol_i_p +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rxx32+=rol(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_rolacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_rolacc_PI __builtin_HEXAGON_S6_rol_i_p_acc +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rxx32&=rol(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_roland_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_roland_PI __builtin_HEXAGON_S6_rol_i_p_and +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rxx32-=rol(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_rolnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_rolnac_PI __builtin_HEXAGON_S6_rol_i_p_nac +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rxx32|=rol(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_rolor_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_rolor_PI __builtin_HEXAGON_S6_rol_i_p_or +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rxx32^=rol(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_rolxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_rolxacc_PI __builtin_HEXAGON_S6_rol_i_p_xacc +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rd32=rol(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_rol_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_rol_RI __builtin_HEXAGON_S6_rol_i_r +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rx32+=rol(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_rolacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_rolacc_RI __builtin_HEXAGON_S6_rol_i_r_acc +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rx32&=rol(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_roland_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_roland_RI __builtin_HEXAGON_S6_rol_i_r_and +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rx32-=rol(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_rolnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_rolnac_RI __builtin_HEXAGON_S6_rol_i_r_nac +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rx32|=rol(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_rolor_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_rolor_RI __builtin_HEXAGON_S6_rol_i_r_or +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rx32^=rol(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_rolxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_rolxacc_RI __builtin_HEXAGON_S6_rol_i_r_xacc +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Rdd32=vabsdiffb(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vabsdiffb_PP(Word64 Rtt, Word64 Rss) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vabsdiffb_PP __builtin_HEXAGON_M6_vabsdiffb +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HEXAGON_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Rdd32=vabsdiffub(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vabsdiffub_PP(Word64 Rtt, Word64 Rss) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vabsdiffub_PP __builtin_HEXAGON_M6_vabsdiffub +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HEXAGON_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Rdd32=vsplatb(Rs32) + C Intrinsic Prototype: Word64 Q6_P_vsplatb_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsplatb_R __builtin_HEXAGON_S6_vsplatrbp +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HEXAGON_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Rdd32=vtrunehb(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vtrunehb_PP(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vtrunehb_PP __builtin_HEXAGON_S6_vtrunehb_ppp +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HEXAGON_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Rdd32=vtrunohb(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vtrunohb_PP(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vtrunohb_PP __builtin_HEXAGON_S6_vtrunohb_ppp +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HEXAGON_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Pd4=!any8(vcmpb.eq(Rss32,Rtt32)) + C Intrinsic Prototype: Byte Q6_p_not_any8_vcmpb_eq_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_not_any8_vcmpb_eq_PP __builtin_HEXAGON_A6_vcmpbeq_notany +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HEXAGON_ARCH__ >= 66 +/* ========================================================================== + Assembly Syntax: Rdd32=dfadd(Rss32,Rtt32) + C Intrinsic Prototype: Float64 Q6_P_dfadd_PP(Float64 Rss, Float64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_dfadd_PP __builtin_HEXAGON_F2_dfadd +#endif /* __HEXAGON_ARCH___ >= 66 */ + +#if __HEXAGON_ARCH__ >= 66 +/* ========================================================================== + Assembly Syntax: Rdd32=dfsub(Rss32,Rtt32) + C Intrinsic Prototype: Float64 Q6_P_dfsub_PP(Float64 Rss, Float64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_dfsub_PP __builtin_HEXAGON_F2_dfsub +#endif /* __HEXAGON_ARCH___ >= 66 */ + +#if __HEXAGON_ARCH__ >= 66 +/* ========================================================================== + Assembly Syntax: Rx32-=mpyi(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_mpyinac_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyinac_RR __builtin_HEXAGON_M2_mnaci +#endif /* __HEXAGON_ARCH___ >= 66 */ + +#if __HEXAGON_ARCH__ >= 66 +/* ========================================================================== + Assembly Syntax: Rd32=mask(#u5,#U5) + C Intrinsic Prototype: Word32 Q6_R_mask_II(Word32 Iu5, Word32 IU5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mask_II __builtin_HEXAGON_S2_mask +#endif /* __HEXAGON_ARCH___ >= 66 */ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rd32=clip(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_clip_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_clip_RI __builtin_HEXAGON_A7_clip +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rdd32=cround(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_cround_PI(Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cround_PI __builtin_HEXAGON_A7_croundd_ri +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rdd32=cround(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_cround_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cround_PR __builtin_HEXAGON_A7_croundd_rr +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rdd32=vclip(Rss32,#u5) + C Intrinsic Prototype: Word64 Q6_P_vclip_PI(Word64 Rss, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vclip_PI __builtin_HEXAGON_A7_vclip +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 +/* ========================================================================== + Assembly Syntax: Rdd32=dfmax(Rss32,Rtt32) + C Intrinsic Prototype: Float64 Q6_P_dfmax_PP(Float64 Rss, Float64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_dfmax_PP __builtin_HEXAGON_F2_dfmax +#endif /* __HEXAGON_ARCH___ >= 67 */ + +#if __HEXAGON_ARCH__ >= 67 +/* ========================================================================== + Assembly Syntax: Rdd32=dfmin(Rss32,Rtt32) + C Intrinsic Prototype: Float64 Q6_P_dfmin_PP(Float64 Rss, Float64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_dfmin_PP __builtin_HEXAGON_F2_dfmin +#endif /* __HEXAGON_ARCH___ >= 67 */ + +#if __HEXAGON_ARCH__ >= 67 +/* ========================================================================== + Assembly Syntax: Rdd32=dfmpyfix(Rss32,Rtt32) + C Intrinsic Prototype: Float64 Q6_P_dfmpyfix_PP(Float64 Rss, Float64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_dfmpyfix_PP __builtin_HEXAGON_F2_dfmpyfix +#endif /* __HEXAGON_ARCH___ >= 67 */ + +#if __HEXAGON_ARCH__ >= 67 +/* ========================================================================== + Assembly Syntax: Rxx32+=dfmpyhh(Rss32,Rtt32) + C Intrinsic Prototype: Float64 Q6_P_dfmpyhhacc_PP(Float64 Rxx, Float64 Rss, Float64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_dfmpyhhacc_PP __builtin_HEXAGON_F2_dfmpyhh +#endif /* __HEXAGON_ARCH___ >= 67 */ + +#if __HEXAGON_ARCH__ >= 67 +/* ========================================================================== + Assembly Syntax: Rxx32+=dfmpylh(Rss32,Rtt32) + C Intrinsic Prototype: Float64 Q6_P_dfmpylhacc_PP(Float64 Rxx, Float64 Rss, Float64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_dfmpylhacc_PP __builtin_HEXAGON_F2_dfmpylh +#endif /* __HEXAGON_ARCH___ >= 67 */ + +#if __HEXAGON_ARCH__ >= 67 +/* ========================================================================== + Assembly Syntax: Rdd32=dfmpyll(Rss32,Rtt32) + C Intrinsic Prototype: Float64 Q6_P_dfmpyll_PP(Float64 Rss, Float64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_dfmpyll_PP __builtin_HEXAGON_F2_dfmpyll +#endif /* __HEXAGON_ARCH___ >= 67 */ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rdd32=cmpyiw(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_cmpyiw_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_P_cmpyiw_PP __builtin_HEXAGON_M7_dcmpyiw +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rxx32+=cmpyiw(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_cmpyiwacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_P_cmpyiwacc_PP __builtin_HEXAGON_M7_dcmpyiw_acc +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rdd32=cmpyiw(Rss32,Rtt32*) + C Intrinsic Prototype: Word64 Q6_P_cmpyiw_PP_conj(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_P_cmpyiw_PP_conj __builtin_HEXAGON_M7_dcmpyiwc +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rxx32+=cmpyiw(Rss32,Rtt32*) + C Intrinsic Prototype: Word64 Q6_P_cmpyiwacc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_P_cmpyiwacc_PP_conj __builtin_HEXAGON_M7_dcmpyiwc_acc +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rdd32=cmpyrw(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_cmpyrw_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_P_cmpyrw_PP __builtin_HEXAGON_M7_dcmpyrw +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rxx32+=cmpyrw(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_cmpyrwacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_P_cmpyrwacc_PP __builtin_HEXAGON_M7_dcmpyrw_acc +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rdd32=cmpyrw(Rss32,Rtt32*) + C Intrinsic Prototype: Word64 Q6_P_cmpyrw_PP_conj(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_P_cmpyrw_PP_conj __builtin_HEXAGON_M7_dcmpyrwc +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rxx32+=cmpyrw(Rss32,Rtt32*) + C Intrinsic Prototype: Word64 Q6_P_cmpyrwacc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_P_cmpyrwacc_PP_conj __builtin_HEXAGON_M7_dcmpyrwc_acc +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rdd32=vdmpyw(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vdmpyw_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_P_vdmpyw_PP __builtin_HEXAGON_M7_vdmpy +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rxx32+=vdmpyw(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vdmpywacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_P_vdmpywacc_PP __builtin_HEXAGON_M7_vdmpy_acc +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rd32=cmpyiw(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_R_cmpyiw_PP_s1_sat __builtin_HEXAGON_M7_wcmpyiw +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rd32=cmpyiw(Rss32,Rtt32):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_R_cmpyiw_PP_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyiw_rnd +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rd32=cmpyiw(Rss32,Rtt32*):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_conj_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_R_cmpyiw_PP_conj_s1_sat __builtin_HEXAGON_M7_wcmpyiwc +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rd32=cmpyiw(Rss32,Rtt32*):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_conj_s1_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_R_cmpyiw_PP_conj_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyiwc_rnd +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rd32=cmpyrw(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_R_cmpyrw_PP_s1_sat __builtin_HEXAGON_M7_wcmpyrw +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rd32=cmpyrw(Rss32,Rtt32):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_R_cmpyrw_PP_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyrw_rnd +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rd32=cmpyrw(Rss32,Rtt32*):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_conj_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_R_cmpyrw_PP_conj_s1_sat __builtin_HEXAGON_M7_wcmpyrwc +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rd32=cmpyrw(Rss32,Rtt32*):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_conj_s1_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_R_cmpyrw_PP_conj_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyrwc_rnd +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: dmlink(Rs32,Rt32) + C Intrinsic Prototype: void Q6_dmlink_AA(Address Rs, Address Rt) + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_dmlink_AA __builtin_HEXAGON_Y6_dmlink +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HEXAGON_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Rd32=dmpause + C Intrinsic Prototype: Word32 Q6_R_dmpause() + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_R_dmpause __builtin_HEXAGON_Y6_dmpause +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HEXAGON_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Rd32=dmpoll + C Intrinsic Prototype: Word32 Q6_R_dmpoll() + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_R_dmpoll __builtin_HEXAGON_Y6_dmpoll +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HEXAGON_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: dmresume(Rs32) + C Intrinsic Prototype: void Q6_dmresume_A(Address Rs) + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_dmresume_A __builtin_HEXAGON_Y6_dmresume +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HEXAGON_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: dmstart(Rs32) + C Intrinsic Prototype: void Q6_dmstart_A(Address Rs) + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_dmstart_A __builtin_HEXAGON_Y6_dmstart +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HEXAGON_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Rd32=dmwait + C Intrinsic Prototype: Word32 Q6_R_dmwait() + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_R_dmwait __builtin_HEXAGON_Y6_dmwait +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#include +#ifdef __HVX__ +#include +#endif /* __HVX__ */ +#endif diff --git a/library/stdarch/crates/stdarch-gen-hexagon/hvx_hexagon_protos.h b/library/stdarch/crates/stdarch-gen-hexagon/hvx_hexagon_protos.h new file mode 100644 index 0000000000000..19309a40d6dd1 --- /dev/null +++ b/library/stdarch/crates/stdarch-gen-hexagon/hvx_hexagon_protos.h @@ -0,0 +1,6003 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// Automatically generated file, do not edit! +//===----------------------------------------------------------------------===// + + +#ifndef _HVX_HEXAGON_PROTOS_H_ +#define _HVX_HEXAGON_PROTOS_H_ 1 + +#ifdef __HVX__ +#if __HVX_LENGTH__ == 128 +#define __BUILTIN_VECTOR_WRAP(a) a ## _128B +#else +#define __BUILTIN_VECTOR_WRAP(a) a +#endif + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rd32=vextract(Vu32,Rs32) + C Intrinsic Prototype: Word32 Q6_R_vextract_VR(HVX_Vector Vu, Word32 Rs) + Instruction Type: LD + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_R_vextract_VR(Vu,Rs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_extractw)(Vu,Rs) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=hi(Vss32) + C Intrinsic Prototype: HVX_Vector Q6_V_hi_W(HVX_VectorPair Vss) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_hi_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_hi)(Vss) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=lo(Vss32) + C Intrinsic Prototype: HVX_Vector Q6_V_lo_W(HVX_VectorPair Vss) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_lo_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lo)(Vss) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vsplat(Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vsplat_R(Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatw)(Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=and(Qs4,Qt4) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_and_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=and(Qs4,!Qt4) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_and_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=not(Qs4) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_not_Q(HVX_VectorPred Qs) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_not_Q(Qs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_not)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=or(Qs4,Qt4) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_or_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=or(Qs4,!Qt4) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_or_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vsetq(Rt32) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vsetq_R(Word32 Rt) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vsetq_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2)(Rt)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=xor(Qs4,Qt4) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_xor_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_xor_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) vmem(Rt32+#s4)=Vs32 + C Intrinsic Prototype: void Q6_vmem_QnRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) + Instruction Type: CVI_VM_ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vmem_QnRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) vmem(Rt32+#s4):nt=Vs32 + C Intrinsic Prototype: void Q6_vmem_QnRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) + Instruction Type: CVI_VM_ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vmem_QnRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) vmem(Rt32+#s4):nt=Vs32 + C Intrinsic Prototype: void Q6_vmem_QRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) + Instruction Type: CVI_VM_ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vmem_QRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) vmem(Rt32+#s4)=Vs32 + C Intrinsic Prototype: void Q6_vmem_QRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) + Instruction Type: CVI_VM_ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vmem_QRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vabsdiff(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuh_vabsdiff_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vabsdiff(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vabsdiff_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vub_vabsdiff_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vabsdiff(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuh_vabsdiff_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vabsdiff(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vabsdiff_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuw_vabsdiff_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vabs(Vu32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vabs_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vabs(Vu32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh_sat(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vabs_Vh_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh_sat)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vabs(Vu32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vabs_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vabs(Vu32.w):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw_sat(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vabs_Vw_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw_sat)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vadd(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vadd_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.b=vadd(Vuu32.b,Vvv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wb_vadd_WbWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) Vx32.b+=Vu32.b + C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_condacc_QnVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) Vx32.b+=Vu32.b + C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_condacc_QVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vadd(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vadd(Vuu32.h,Vvv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vadd_WhWh(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) Vx32.h+=Vu32.h + C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_condacc_QnVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) Vx32.h+=Vu32.h + C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_condacc_QVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vadd(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vadd_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vadd(Vuu32.h,Vvv32.h):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vadd_WhWh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vadd(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vadd(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vadd_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vadd(Vu32.ub,Vv32.ub):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vadd_VubVub_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.ub=vadd(Vuu32.ub,Vvv32.ub):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vadd_WubWub_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wub_vadd_WubWub_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vadd(Vu32.uh,Vv32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vadd_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vadd_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uh=vadd(Vuu32.uh,Vvv32.uh):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vadd_WuhWuh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuh_vadd_WuhWuh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vadd(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vadd_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vadd_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vadd(Vuu32.w,Vvv32.w) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vadd_WwWw(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) Vx32.w+=Vu32.w + C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QnVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_condacc_QnVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) Vx32.w+=Vu32.w + C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_condacc_QVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vadd_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vadd(Vuu32.w,Vvv32.w):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vadd_WwWw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=valign(Vu32,Vv32,Rt8) + C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_valign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignb)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=valign(Vu32,Vv32,#u3) + C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_valign_VVI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignbi)(Vu,Vv,Iu3) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vand(Vu32,Vv32) + C Intrinsic Prototype: HVX_Vector Q6_V_vand_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vand_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vand)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vand(Qu4,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vand_QR(HVX_VectorPred Qu, Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vand_QR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32|=vand(Qu4,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQR(HVX_Vector Vx, HVX_VectorPred Qu, Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vandor_VQR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt_acc)(Vx,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vand(Vu32,Rt32) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vand_VR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Q_vand_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)(Vu,Rt)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vand(Vu32,Rt32) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vandor_QVR(HVX_VectorPred Qx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Q_vandor_QVR(Qx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt_acc)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Rt)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vasl(Vu32.h,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasl_VhR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasl_VhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vasl(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasl_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasl_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslhv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vasl(Vu32.w,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vasl_VwR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vasl_VwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vasl(Vu32.w,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vaslacc_VwVwR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vaslacc_VwVwR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vasl(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vasl_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vasl_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslwv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vasr(Vu32.h,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VhR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasr_VhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vasr_VhVhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbrndsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vasr_VhVhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubrndsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vasr_VhVhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vasr(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasr_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vasr(Vu32.w,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vasr_VwR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vasr_VwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vasr(Vu32.w,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vasracc_VwVwR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vasracc_VwVwR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasr_VwVwR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwh)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasr_VwVwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhrndsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasr_VwVwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vasr_VwVwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vasr(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vasr_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vasr_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=Vu32 + C Intrinsic Prototype: HVX_Vector Q6_V_equals_V(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_equals_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassign)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32=Vuu32 + C Intrinsic Prototype: HVX_VectorPair Q6_W_equals_W(HVX_VectorPair Vuu) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_W_equals_W(Vuu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassignp)(Vuu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vavg(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vavg_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vavg(Vu32.h,Vv32.h):rnd + C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh_rnd(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vavg_VhVh_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavghrnd)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vavg(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vavg_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vavg(Vu32.ub,Vv32.ub):rnd + C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub_rnd(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vavg_VubVub_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgubrnd)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vavg(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vavg_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vavg(Vu32.uh,Vv32.uh):rnd + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh_rnd(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vavg_VuhVuh_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguhrnd)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vavg(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vavg_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vavg(Vu32.w,Vv32.w):rnd + C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw_rnd(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vavg_VwVw_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgwrnd)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vcl0(Vu32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vcl0_Vuh(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vcl0_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0h)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vcl0(Vu32.uw) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vcl0_Vuw(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuw_vcl0_Vuw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0w)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32=vcombine(Vu32,Vv32) + C Intrinsic Prototype: HVX_VectorPair Q6_W_vcombine_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_W_vcombine_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcombine)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=#0 + C Intrinsic Prototype: HVX_Vector Q6_V_vzero() + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vzero() __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vd0)() +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vdeal(Vu32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vdeal_Vb(HVX_Vector Vu) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vdeal_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vdeale(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vdeale_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vdeale_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb4w)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vdeal(Vu32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vdeal_Vh(HVX_Vector Vu) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vdeal_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32=vdeal(Vu32,Vv32,Rt8) + C Intrinsic Prototype: HVX_VectorPair Q6_W_vdeal_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_W_vdeal_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealvdd)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vdelta(Vu32,Vv32) + C Intrinsic Prototype: HVX_Vector Q6_V_vdelta_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vdelta_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdelta)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vdmpy(Vu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vdmpy_VubRb(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vdmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.h+=vdmpy(Vu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vdmpyacc_VhVubRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vdmpyacc_VhVubRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vdmpy(Vuu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpy_WubRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vdmpy_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vdmpy(Vuu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpyacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vdmpyacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRb(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpy_VhRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpyacc_VwVhRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vdmpy(Vuu32.h,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpy_WhRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vdmpy_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vdmpy(Vuu32.h,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpyacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vdmpyacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vdmpy(Vuu32.h,Rt32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRh_sat(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpy_WhRh_sat(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vdmpy(Vuu32.h,Rt32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRh_sat(HVX_Vector Vx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpyacc_VwWhRh_sat(Vx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat_acc)(Vx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRh_sat(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpy_VhRh_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpyacc_VwVhRh_sat(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vdmpy(Vuu32.h,Rt32.uh,#1):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRuh_sat(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpy_WhRuh_sat(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vdmpy(Vuu32.h,Rt32.uh,#1):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRuh_sat(HVX_Vector Vx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpyacc_VwWhRuh_sat(Vx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat_acc)(Vx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRuh_sat(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpy_VhRuh_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpyacc_VwVhRuh_sat(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpy_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhVh_sat(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpyacc_VwVhVh_sat(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vdsad(Vuu32.uh,Rt32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vdsad_WuhRuh(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vdsad_WuhRuh(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.uw+=vdsad(Vuu32.uh,Rt32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vdsadacc_WuwWuhRuh(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vdsadacc_WuwWuhRuh(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.eq(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eq_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.eq(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqand_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.eq(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqor_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.eq(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqxacc_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.eq(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eq_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.eq(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqand_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.eq(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqor_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.eq(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqxacc_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.eq(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eq_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.eq(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqand_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.eq(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqor_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.eq(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqxacc_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.uw,Vv32.uw) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.uw,Vv32.uw) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.uw,Vv32.uw) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.uw,Vv32.uw) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w=vinsert(Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vinsert_VwR(HVX_Vector Vx, Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vinsert_VwR(Vx,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vinsertwr)(Vx,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vlalign(Vu32,Vv32,Rt8) + C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vlalign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignb)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vlalign(Vu32,Vv32,#u3) + C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vlalign_VVI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignbi)(Vu,Vv,Iu3) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vlsr(Vu32.uh,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vlsr_VuhR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vlsr_VuhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrh)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vlsr(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vlsr_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vlsr_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrhv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vlsr(Vu32.uw,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vlsr_VuwR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuw_vlsr_VuwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrw)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vlsr(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vlsr_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vlsr_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrwv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vlut32_VbVbR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.b|=vlut32(Vu32.b,Vv32.b,Rt8) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbR(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vlut32or_VbVbVbR(Vx,Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracc)(Vx,Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vlut16_VbVhR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h|=vlut16(Vu32.b,Vv32.h,Rt8) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhR(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vlut16or_WhVbVhR(Vxx,Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracc)(Vxx,Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vmax(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmax_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vmax_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vmax(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vmax_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vmax_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vmax(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmax_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vmax_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmax(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmax_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vmax_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vmin(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmin_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vmin_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vmin(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vmin_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vmin_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vmin(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmin_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vmin_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmin(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmin_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vmin_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpa_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vmpa(Vuu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpaacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Vvv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpa_WubWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabusv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Vvv32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWub(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpa_WubWub(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuuv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vmpa(Vuu32.h,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WhRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpa_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vmpa(Vuu32.h,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpaacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vmpy(Vu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubRb(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vmpy(Vu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubRb(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpyacc_WhVubRb(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus_acc)(Vxx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vmpy(Vu32.ub,Vv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpy_VubVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vmpy(Vu32.ub,Vv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubVb(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpyacc_WhVubVb(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vmpy(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpy_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vmpy(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVbVb(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpyacc_WhVbVb(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpye(Vu32.w,Vv32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpye_VwVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpye_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Rt32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhRh(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpy_VhRh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Rt32.h):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh_sat(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpyacc_WwVhRh_sat(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsat_acc)(Vxx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_rnd_sat(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vmpy_VhRh_s1_rnd_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsrs)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_sat(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vmpy_VhRh_s1_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhss)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpy_VhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpyacc_WwVhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpy_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpyacc_WwVhVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vmpy(Vu32.h,Vv32.h):<<1:rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhVh_s1_rnd_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vmpy_VhVh_s1_rnd_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhvsrs)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyieo(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieo_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyieo_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyieoh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vmpyie(Vu32.w,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyieacc_VwVwVh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewh_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyie(Vu32.w,Vv32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyie_VwVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyie_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vmpyie(Vu32.w,Vv32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVuh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyieacc_VwVwVuh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vmpyi(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyi_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vmpyi_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.h+=vmpyi(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhVh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vmpyiacc_VhVhVh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vmpyi(Vu32.h,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyi_VhRb(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vmpyi_VhRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.h+=vmpyi(Vu32.h,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vmpyiacc_VhVhRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyio(Vu32.w,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyio_VwVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyio_VwVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiowh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRb(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyi_VwRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyiacc_VwVwRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRh(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyi_VwRh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRh(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyiacc_VwVwRh(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyo_VwVh_s1_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_rnd_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyo_VwVh_s1_rnd_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat:shift + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd_sacc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:sat:shift + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_sacc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uh=vmpy(Vu32.ub,Rt32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubRub(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuh_vmpy_VubRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.uh+=vmpy(Vu32.ub,Rt32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubRub(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuh_vmpyacc_WuhVubRub(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub_acc)(Vxx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uh=vmpy(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuh_vmpy_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.uh+=vmpy(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubVub(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuh_vmpyacc_WuhVubVub(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vmpy(Vu32.uh,Rt32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhRuh(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vmpy_VuhRuh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.uw+=vmpy(Vu32.uh,Rt32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhRuh(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vmpyacc_WuwVuhRuh(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh_acc)(Vxx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vmpy(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vmpy_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.uw+=vmpy(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vmpyacc_WuwVuhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vmux(Qt4,Vu32,Vv32) + C Intrinsic Prototype: HVX_Vector Q6_V_vmux_QVV(HVX_VectorPred Qt, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vmux_QVV(Qt,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmux)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1),Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vnavg(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vnavg_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vnavg_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vnavg(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vnavg_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vnavg(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vnavg_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vnavg_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vnormamt(Vu32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vnormamt_Vh(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vnormamt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamth)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vnormamt(Vu32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vnormamt_Vw(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vnormamt_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamtw)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vnot(Vu32) + C Intrinsic Prototype: HVX_Vector Q6_V_vnot_V(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vnot_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnot)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vor(Vu32,Vv32) + C Intrinsic Prototype: HVX_Vector Q6_V_vor_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vor_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vor)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vpacke(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacke_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vpacke_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vpacke(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacke_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vpacke_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vpack(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vb_vpack_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vpack_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhb_sat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vpack(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vpack_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vpack_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhub_sat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vpacko(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacko_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vpacko_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackob)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vpacko(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacko_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vpacko_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackoh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vpack(Vu32.w,Vv32.w):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vpack_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vpack_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwh_sat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vpack(Vu32.w,Vv32.w):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vpack_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vpack_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwuh_sat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vpopcount(Vu32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vpopcount_Vh(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vpopcount_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpopcounth)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vrdelta(Vu32,Vv32) + C Intrinsic Prototype: HVX_Vector Q6_V_vrdelta_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vrdelta_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrdelta)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vrmpy(Vu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VubRb(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vrmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vrmpy(Vu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vrmpyacc_VwVubRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vrmpy(Vuu32.ub,Rt32.b,#u1) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpy_WubRbI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vrmpy_WubRbI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi)(Vuu,Rt,Iu1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vrmpy(Vuu32.ub,Rt32.b,#u1) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpyacc_WwWubRbI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vrmpyacc_WwWubRbI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi_acc)(Vxx,Vuu,Rt,Iu1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vrmpy(Vu32.ub,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VubVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vrmpy_VubVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vrmpy(Vu32.ub,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vrmpyacc_VwVubVb(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vrmpy(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vrmpy_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vrmpy(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVbVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vrmpyacc_VwVbVb(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vrmpy(Vu32.ub,Rt32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubRub(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuw_vrmpy_VubRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.uw+=vrmpy(Vu32.ub,Rt32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubRub(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuw_vrmpyacc_VuwVubRub(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vrmpy(Vuu32.ub,Rt32.ub,#u1) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrmpy_WubRubI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vrmpy_WubRubI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi)(Vuu,Rt,Iu1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.uw+=vrmpy(Vuu32.ub,Rt32.ub,#u1) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrmpyacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vrmpyacc_WuwWubRubI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi_acc)(Vxx,Vuu,Rt,Iu1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vrmpy(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuw_vrmpy_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.uw+=vrmpy(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubVub(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuw_vrmpyacc_VuwVubVub(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vror(Vu32,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vror_VR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vror_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vror)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vround(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vb_vround_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vround_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vround(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vround_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vround(Vu32.w,Vv32.w):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vround_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vround_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vround(Vu32.w,Vv32.w):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vround_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vrsad(Vuu32.ub,Rt32.ub,#u1) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrsad_WubRubI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vrsad_WubRubI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi)(Vuu,Rt,Iu1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.uw+=vrsad(Vuu32.ub,Rt32.ub,#u1) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrsadacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vrsadacc_WuwWubRubI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi_acc)(Vxx,Vuu,Rt,Iu1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vsat(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vsat_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vsat_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsathub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vsat(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vsat_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vsat_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatwh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vsxt(Vu32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsxt_Vb(HVX_Vector Vu) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vsxt_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsb)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vsxt(Vu32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsxt_Vh(HVX_Vector Vu) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vsxt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vshuffe(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffe_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vshuffe_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufeh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vshuff(Vu32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuff_Vb(HVX_Vector Vu) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vshuff_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffb)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vshuffe(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffe_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vshuffe_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffeb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vshuff(Vu32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuff_Vh(HVX_Vector Vu) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vshuff_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vshuffo(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffo_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vshuffo_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffob)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32=vshuff(Vu32,Vv32,Rt8) + C Intrinsic Prototype: HVX_VectorPair Q6_W_vshuff_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_W_vshuff_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffvdd)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.b=vshuffoe(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vshuffoe_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wb_vshuffoe_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vshuffoe(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vshuffoe_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vshuffoe_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vshuffo(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffo_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vshuffo_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vsub(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vsub_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.b=vsub(Vuu32.b,Vvv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wb_vsub_WbWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) Vx32.b-=Vu32.b + C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_condnac_QnVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) Vx32.b-=Vu32.b + C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_condnac_QVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vsub(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vsub_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vsub(Vuu32.h,Vvv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vsub_WhWh(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) Vx32.h-=Vu32.h + C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_condnac_QnVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) Vx32.h-=Vu32.h + C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_condnac_QVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vsub(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vsub_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vsub(Vuu32.h,Vvv32.h):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vsub_WhWh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vsub(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vsub_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vsub(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vsub_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vsub(Vu32.ub,Vv32.ub):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vsub_VubVub_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.ub=vsub(Vuu32.ub,Vvv32.ub):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vsub_WubWub_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wub_vsub_WubWub_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vsub(Vu32.uh,Vv32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsub_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vsub_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uh=vsub(Vuu32.uh,Vvv32.uh):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vsub_WuhWuh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuh_vsub_WuhWuh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vsub(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vsub_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vsub_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vsub(Vuu32.w,Vvv32.w) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vsub_WwWw(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) Vx32.w-=Vu32.w + C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QnVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_condnac_QnVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) Vx32.w-=Vu32.w + C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_condnac_QVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vsub_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vsub(Vuu32.w,Vvv32.w):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vsub_WwWw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32=vswap(Qt4,Vu32,Vv32) + C Intrinsic Prototype: HVX_VectorPair Q6_W_vswap_QVV(HVX_VectorPred Qt, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_W_vswap_QVV(Qt,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vswap)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1),Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vtmpy(Vuu32.b,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WbRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vtmpy_WbRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vtmpy(Vuu32.b,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWbRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vtmpyacc_WhWbRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vtmpy(Vuu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WubRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vtmpy_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vtmpy(Vuu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vtmpyacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vtmpy(Vuu32.h,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpy_WhRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vtmpy_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vtmpy(Vuu32.h,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpyacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vtmpyacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vunpack(Vu32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vunpack_Vb(HVX_Vector Vu) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vunpack_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackb)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vunpack(Vu32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vunpack_Vh(HVX_Vector Vu) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vunpack_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h|=vunpacko(Vu32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vunpackoor_WhVb(HVX_VectorPair Vxx, HVX_Vector Vu) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vunpackoor_WhVb(Vxx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackob)(Vxx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w|=vunpacko(Vu32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vunpackoor_WwVh(HVX_VectorPair Vxx, HVX_Vector Vu) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vunpackoor_WwVh(Vxx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackoh)(Vxx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uh=vunpack(Vu32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vunpack_Vub(HVX_Vector Vu) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuh_vunpack_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackub)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vunpack(Vu32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vunpack_Vuh(HVX_Vector Vu) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuw_vunpack_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackuh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vxor(Vu32,Vv32) + C Intrinsic Prototype: HVX_Vector Q6_V_vxor_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vxor_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vxor)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uh=vzxt(Vu32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vzxt_Vub(HVX_Vector Vu) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuh_vzxt_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzb)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vzxt(Vu32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vzxt_Vuh(HVX_Vector Vu) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuw_vzxt_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vsplat(Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vsplat_R(Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vb_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatb)(Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.h=vsplat(Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vsplat_R(Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplath)(Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Qd4=vsetq2(Rt32) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vsetq2_R(Word32 Rt) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vsetq2_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2v2)(Rt)),-1) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Qd4.b=vshuffe(Qs4.h,Qt4.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Qb_vshuffe_QhQh(HVX_VectorPred Qs, HVX_VectorPred Qt) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Qb_vshuffe_QhQh(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqh)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Qd4.h=vshuffe(Qs4.w,Qt4.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Qh_vshuffe_QwQw(HVX_VectorPred Qs, HVX_VectorPred Qt) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Qh_vshuffe_QwQw(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqw)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vadd(Vu32.b,Vv32.b):sat + C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vadd_VbVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32.b=vadd(Vuu32.b,Vvv32.b):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wb_vadd_WbWb_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w,Qx4):carry + C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred* Qx) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vadd_VwVwQ_carry(Vu,Vv,Qx) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarry)(Vu,Vv,Qx) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.h=vadd(vclb(Vu32.h),Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_vclb_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vadd_vclb_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.w=vadd(vclb(Vu32.w),Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_vclb_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vadd_vclb_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vadd(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVhVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vaddacc_WwVhVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vadd(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vaddacc_WhVubVub(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vaddacc_WhVubVub(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vadd(Vu32.ub,Vv32.b):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVb_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vadd_VubVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddububb_sat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vadd(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVuhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vaddacc_WwVuhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vadd(Vu32.uw,Vv32.uw):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vadd_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuw_vadd_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vadd(Vuu32.uw,Vvv32.uw):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vadd_WuwWuw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuw_vadd_WuwWuw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32=vand(!Qu4,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vand_QnR(HVX_VectorPred Qu, Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vand_QnR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vx32|=vand(!Qu4,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQnR(HVX_Vector Vx, HVX_VectorPred Qu, Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vandor_VQnR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt_acc)(Vx,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32=vand(!Qv4,Vu32) + C Intrinsic Prototype: HVX_Vector Q6_V_vand_QnV(HVX_VectorPred Qv, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vand_QnV(Qv,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvnqv)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vu) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32=vand(Qv4,Vu32) + C Intrinsic Prototype: HVX_Vector Q6_V_vand_QV(HVX_VectorPred Qv, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vand_QV(Qv,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvqv)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vu) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):sat + C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vasr_VhVhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vasr_VuwVuwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhrndsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vasr_VwVwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhrndsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vlsr(Vu32.ub,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vlsr_VubR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vlsr_VubR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrb)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8):nomatch + C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR_nomatch(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vlut32_VbVbR_nomatch(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_nm)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vx32.b|=vlut32(Vu32.b,Vv32.b,#u3) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbI(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vlut32or_VbVbVbI(Vx,Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracci)(Vx,Vu,Vv,Iu3) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,#u3) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vlut32_VbVbI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvbi)(Vu,Vv,Iu3) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8):nomatch + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR_nomatch(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vlut16_VbVhR_nomatch(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_nm)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vxx32.h|=vlut16(Vu32.b,Vv32.h,#u3) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhI(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vlut16or_WhVbVhI(Vxx,Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracci)(Vxx,Vu,Vv,Iu3) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,#u3) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vlut16_VbVhI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwhi)(Vu,Vv,Iu3) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vmax(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vmax_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vmax_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vmin(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vmin_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vmin_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vmpa(Vuu32.uh,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WuhRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpa_WuhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vmpa(Vuu32.uh,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWuhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpaacc_WwWuhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32=vmpye(Vu32.w,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpye_VwVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_W_vmpye_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh_64)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRub(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyi_VwRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRub(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyiacc_VwVwRub(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vxx32+=vmpyo(Vu32.w,Vv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpyoacc_WVwVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_W_vmpyoacc_WVwVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_64_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vround(Vu32.uh,Vv32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vround_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduhub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vround(Vu32.uw,Vv32.uw):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vround_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduwuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vsat(Vu32.uw,Vv32.uw) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsat_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vsat_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatuwuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vsub(Vu32.b,Vv32.b):sat + C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vsub_VbVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32.b=vsub(Vuu32.b,Vvv32.b):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wb_vsub_WbWb_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w,Qx4):carry + C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVwQ_carry(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred* Qx) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vsub_VwVwQ_carry(Vu,Vv,Qx) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubcarry)(Vu,Vv,Qx) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vsub(Vu32.ub,Vv32.b):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVb_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vsub_VubVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubububb_sat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vsub(Vu32.uw,Vv32.uw):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vsub_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuw_vsub_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vsub(Vuu32.uw,Vvv32.uw):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vsub_WuwWuw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuw_vsub_WuwWuw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.b=vabs(Vu32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vabs_Vb(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vabs_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb)(Vu) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.b=vabs(Vu32.b):sat + C Intrinsic Prototype: HVX_Vector Q6_Vb_vabs_Vb_sat(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vabs_Vb_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb_sat)(Vu) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vx32.h+=vasl(Vu32.h,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vaslacc_VhVhR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vaslacc_VhVhR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vx32.h+=vasr(Vu32.h,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasracc_VhVhR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasracc_VhVhR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vasr_VuhVuhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubrndsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vasr_VuhVuhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vasr_VuwVuwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.b=vavg(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vavg_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.b=vavg(Vu32.b,Vv32.b):rnd + C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb_rnd(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vavg_VbVb_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgbrnd)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vavg(Vu32.uw,Vv32.uw) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuw_vavg_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vavg(Vu32.uw,Vv32.uw):rnd + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw_rnd(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuw_vavg_VuwVuw_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguwrnd)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vdd32=#0 + C Intrinsic Prototype: HVX_VectorPair Q6_W_vzero() + Instruction Type: MAPPING + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_W_vzero() __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdd0)() +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vtmp.h=vgather(Rt32,Mu2,Vv32.h).h + C Intrinsic Prototype: void Q6_vgather_ARMVh(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_Vector Vv) + Instruction Type: CVI_GATHER + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_vgather_ARMVh(Rs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermh)(Rs,Rt,Mu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vv32.h).h + C Intrinsic Prototype: void Q6_vgather_AQRMVh(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv) + Instruction Type: CVI_GATHER + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_vgather_AQRMVh(Rs,Qs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h + C Intrinsic Prototype: void Q6_vgather_ARMWw(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv) + Instruction Type: CVI_GATHER_DV + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_vgather_ARMWw(Rs,Rt,Mu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhw)(Rs,Rt,Mu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h + C Intrinsic Prototype: void Q6_vgather_AQRMWw(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv) + Instruction Type: CVI_GATHER_DV + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_vgather_AQRMWw(Rs,Qs,Rt,Mu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhwq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vtmp.w=vgather(Rt32,Mu2,Vv32.w).w + C Intrinsic Prototype: void Q6_vgather_ARMVw(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_Vector Vv) + Instruction Type: CVI_GATHER + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_vgather_ARMVw(Rs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermw)(Rs,Rt,Mu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: if (Qs4) vtmp.w=vgather(Rt32,Mu2,Vv32.w).w + C Intrinsic Prototype: void Q6_vgather_AQRMVw(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv) + Instruction Type: CVI_GATHER + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_vgather_AQRMVw(Rs,Qs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermwq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.h=vlut4(Vu32.uh,Rtt32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vlut4_VuhPh(HVX_Vector Vu, Word64 Rtt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT2 + ========================================================================== */ + +#define Q6_Vh_vlut4_VuhPh(Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlut4)(Vu,Rtt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Rt32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRub(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpa_WubRub(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vmpa(Vuu32.ub,Rt32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRub(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpaacc_WhWubRub(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vx32.h=vmpa(Vx32.h,Vu32.h,Rtt32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVhPh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT2 + ========================================================================== */ + +#define Q6_Vh_vmpa_VhVhVhPh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahhsat)(Vx,Vu,Rtt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vx32.h=vmpa(Vx32.h,Vu32.uh,Rtt32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVuhPuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT2 + ========================================================================== */ + +#define Q6_Vh_vmpa_VhVhVuhPuh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhuhsat)(Vx,Vu,Rtt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vx32.h=vmps(Vx32.h,Vu32.uh,Rtt32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmps_VhVhVuhPuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT2 + ========================================================================== */ + +#define Q6_Vh_vmps_VhVhVuhPuh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpsuhuhsat)(Vx,Vu,Rtt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Rt32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpyacc_WwVhRh(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh_acc)(Vxx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vmpye(Vu32.uh,Rt32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpye_VuhRuh(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuw_vmpye_VuhRuh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vx32.uw+=vmpye(Vu32.uh,Rt32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpyeacc_VuwVuhRuh(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuw_vmpyeacc_VuwVuhRuh(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.b=vnavg(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vnavg_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.b=prefixsum(Qv4) + C Intrinsic Prototype: HVX_Vector Q6_Vb_prefixsum_Q(HVX_VectorPred Qv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqb)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1)) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.h=prefixsum(Qv4) + C Intrinsic Prototype: HVX_Vector Q6_Vh_prefixsum_Q(HVX_VectorPred Qv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqh)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1)) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.w=prefixsum(Qv4) + C Intrinsic Prototype: HVX_Vector Q6_Vw_prefixsum_Q(HVX_VectorPred Qv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqw)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1)) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vscatter(Rt32,Mu2,Vv32.h).h=Vw32 + C Intrinsic Prototype: void Q6_vscatter_RMVhV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatter_RMVhV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh)(Rt,Mu,Vv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vscatter(Rt32,Mu2,Vv32.h).h+=Vw32 + C Intrinsic Prototype: void Q6_vscatteracc_RMVhV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatteracc_RMVhV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh_add)(Rt,Mu,Vv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vv32.h).h=Vw32 + C Intrinsic Prototype: void Q6_vscatter_QRMVhV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatter_QRMVhV(Qs,Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vscatter(Rt32,Mu2,Vvv32.w).h=Vw32 + C Intrinsic Prototype: void Q6_vscatter_RMWwV(Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER_DV + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatter_RMWwV(Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw)(Rt,Mu,Vvv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vscatter(Rt32,Mu2,Vvv32.w).h+=Vw32 + C Intrinsic Prototype: void Q6_vscatteracc_RMWwV(Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER_DV + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatteracc_RMWwV(Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw_add)(Rt,Mu,Vvv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vvv32.w).h=Vw32 + C Intrinsic Prototype: void Q6_vscatter_QRMWwV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER_DV + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatter_QRMWwV(Qs,Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vvv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vscatter(Rt32,Mu2,Vv32.w).w=Vw32 + C Intrinsic Prototype: void Q6_vscatter_RMVwV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatter_RMVwV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw)(Rt,Mu,Vv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vscatter(Rt32,Mu2,Vv32.w).w+=Vw32 + C Intrinsic Prototype: void Q6_vscatteracc_RMVwV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatteracc_RMVwV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw_add)(Rt,Mu,Vv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vv32.w).w=Vw32 + C Intrinsic Prototype: void Q6_vscatter_QRMVwV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatter_QRMVwV(Qs,Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 66 +/* ========================================================================== + Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w,Qs4):carry:sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry_sat(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred Qs) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vadd_VwVwQ_carry_sat(Vu,Vv,Qs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarrysat)(Vu,Vv,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1)) +#endif /* __HEXAGON_ARCH___ >= 66 */ + +#if __HVX_ARCH__ >= 66 +/* ========================================================================== + Assembly Syntax: Vxx32.w=vasrinto(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vasrinto_WwVwVw(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vasrinto_WwVwVw(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasr_into)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 66 */ + +#if __HVX_ARCH__ >= 66 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vrotr(Vu32.uw,Vv32.uw) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrotr_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuw_vrotr_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrotr)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 66 */ + +#if __HVX_ARCH__ >= 66 +/* ========================================================================== + Assembly Syntax: Vd32.w=vsatdw(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vsatdw_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vsatdw_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatdw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 66 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):h + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_h(HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_v6mpy_WubWbI_h(Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10)(Vuu,Vvv,Iu2) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):h + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpyacc_WwWubWbI_h(HVX_VectorPair Vxx, HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_v6mpyacc_WwWubWbI_h(Vxx,Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10_vxx)(Vxx,Vuu,Vvv,Iu2) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):v + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_v(HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_v6mpy_WubWbI_v(Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10)(Vuu,Vvv,Iu2) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):v + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpyacc_WwWubWbI_v(HVX_VectorPair Vxx, HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_v6mpyacc_WwWubWbI_v(Vxx,Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10_vxx)(Vxx,Vuu,Vvv,Iu2) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vabs(Vu32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vabs_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vabs_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vabs(Vu32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vabs_Vsf(HVX_Vector Vu) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vabs_Vsf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_sf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vadd(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vadd(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vadd(Vu32.qf16,Vv32.qf16) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vadd_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf16)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vadd(Vu32.qf16,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vadd_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf16_mix)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vadd(Vu32.qf32,Vv32.qf32) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vadd_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf32)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vadd(Vu32.qf32,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_Vqf32Vsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vadd_Vqf32Vsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf32_mix)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vadd(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vadd_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.sf=vadd(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vadd(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vadd_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vadd_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.w=vfmv(Vu32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vfmv_Vw(HVX_Vector Vu) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vfmv_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassign_fp)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=Vu32.qf16 + C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Vqf16(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vhf_equals_Vqf16(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_qf16)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=Vuu32.qf32 + C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Wqf32(HVX_VectorPair Vuu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vhf_equals_Wqf32(Vuu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_qf32)(Vuu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=Vu32.qf32 + C Intrinsic Prototype: HVX_Vector Q6_Vsf_equals_Vqf32(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vsf_equals_Vqf32(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_sf_qf32)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.b=vcvt(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vb_vcvt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_b_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.h=vcvt(Vu32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vcvt_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_h_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vcvt(Vu32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_Vb(HVX_Vector Vu) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vcvt_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_b)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vcvt(Vu32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_Vh(HVX_Vector Vu) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vcvt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_h)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vcvt(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vcvt_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vcvt(Vu32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_Vub(HVX_Vector Vu) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vcvt_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_ub)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vcvt(Vu32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_Vuh(HVX_Vector Vu) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vcvt_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_uh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.sf=vcvt(Vu32.hf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vcvt_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_sf_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vcvt(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vub_vcvt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_ub_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vcvt(Vu32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vcvt_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuh_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_uh_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vdmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vdmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vdmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpy_sf_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vx32.sf+=vdmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vdmpyacc_VsfVhfVhf(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vdmpyacc_VsfVhfVhf(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpy_sf_hf_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vfmax(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfmax_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vfmax_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vfmax(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfmax_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vfmax_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vfmin(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfmin_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vfmin_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vfmin(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfmin_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vfmin_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vfneg(Vu32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfneg_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vfneg_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vfneg(Vu32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfneg_Vsf(HVX_Vector Vu) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vfneg_Vsf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_sf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vmax(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmax_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vhf_vmax_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vmax(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmax_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vsf_vmax_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vmin(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmin_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vhf_vmin_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vmin(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmin_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vsf_vmin_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vx32.hf+=vmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmpyacc_VhfVhfVhf(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vmpyacc_VhfVhfVhf(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_hf_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vmpy(Vu32.qf16,Vv32.qf16) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf16_vmpy_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf16_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vmpy(Vu32.qf16,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf16_vmpy_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16_mix_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vmpy(Vu32.qf32,Vv32.qf32) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf32_vmpy_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.qf32=vmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wqf32_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.qf32=vmpy(Vu32.qf16,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wqf32_vmpy_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_mix_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.qf32=vmpy(Vu32.qf16,Vv32.qf16) + C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wqf32_vmpy_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_qf16)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vmpy(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf32_vmpy_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.sf=vmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vxx32.sf+=vmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpyacc_WsfVhfVhf(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vmpyacc_WsfVhfVhf(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_hf_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vmpy(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmpy_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vmpy_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vsub(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vsub(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vsub(Vu32.qf16,Vv32.qf16) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vsub_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf16)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vsub(Vu32.qf16,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vsub_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf16_mix)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vsub(Vu32.qf32,Vv32.qf32) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vsub_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf32)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vsub(Vu32.qf32,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_Vqf32Vsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vsub_Vqf32Vsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf32_mix)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vsub(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vsub_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.sf=vsub(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vsub(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vsub_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vsub_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 69 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vasr(Vuu32.uh,Vv32.ub):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_WuhVub_rnd_sat(HVX_VectorPair Vuu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vasr_WuhVub_rnd_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvuhubrndsat)(Vuu,Vv) +#endif /* __HEXAGON_ARCH___ >= 69 */ + +#if __HVX_ARCH__ >= 69 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vasr(Vuu32.uh,Vv32.ub):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_WuhVub_sat(HVX_VectorPair Vuu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vasr_WuhVub_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvuhubsat)(Vuu,Vv) +#endif /* __HEXAGON_ARCH___ >= 69 */ + +#if __HVX_ARCH__ >= 69 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vasr(Vuu32.w,Vv32.uh):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_WwVuh_rnd_sat(HVX_VectorPair Vuu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vasr_WwVuh_rnd_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvwuhrndsat)(Vuu,Vv) +#endif /* __HEXAGON_ARCH___ >= 69 */ + +#if __HVX_ARCH__ >= 69 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vasr(Vuu32.w,Vv32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_WwVuh_sat(HVX_VectorPair Vuu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vasr_WwVuh_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvwuhsat)(Vuu,Vv) +#endif /* __HEXAGON_ARCH___ >= 69 */ + +#if __HVX_ARCH__ >= 69 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vmpy(Vu32.uh,Vv32.uh):>>16 + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmpy_VuhVuh_rs16(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuh_vmpy_VuhVuh_rs16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhvs)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 69 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vdd32.sf=vadd(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vadd_VbfVbf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vadd_VbfVbf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_bf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vd32.h=Vu32.hf + C Intrinsic Prototype: HVX_Vector Q6_Vh_equals_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_equals_Vhf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_h_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vd32.hf=Vu32.h + C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Vh(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vhf_equals_Vh(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_h)(Vu) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vd32.sf=Vu32.w + C Intrinsic Prototype: HVX_Vector Q6_Vsf_equals_Vw(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vsf_equals_Vw(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_sf_w)(Vu) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vd32.w=Vu32.sf + C Intrinsic Prototype: HVX_Vector Q6_Vw_equals_Vsf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_equals_Vsf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_w_sf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vd32.bf=vcvt(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vbf_vcvt_VsfVsf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vbf_vcvt_VsfVsf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_bf_sf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbfVbf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VbfVbf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt) \ + ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf)(Vu, Vv)), -1) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbfVbf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVbfVbf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt) \ + ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf_and)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbfVbf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVbfVbf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt) \ + ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf_or)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbfVbf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVbfVbf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt) \ + ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf_xor)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vd32.bf=vmax(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmax_VbfVbf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_LATE Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vbf_vmax_VbfVbf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_bf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vd32.bf=vmin(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmin_VbfVbf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_LATE Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vbf_vmin_VbfVbf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_bf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vdd32.sf=vmpy(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpy_VbfVbf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vmpy_VbfVbf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_bf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vxx32.sf+=vmpy(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpyacc_WsfVbfVbf(HVX_VectorPair + Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution + Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vmpyacc_WsfVbfVbf(Vxx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_bf_acc)(Vxx, Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vdd32.sf=vsub(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vsub_VbfVbf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vsub_VbfVbf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_bf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32=vgetqfext(Vu32.x,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vgetqfext_VR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vgetqfext_VR(Vu, Rt) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_get_qfext)(Vu, Rt) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vx32|=vgetqfext(Vu32.x,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vgetqfextor_VVR(HVX_Vector Vx, + HVX_Vector Vu, Word32 Rt) Instruction Type: CVI_VX Execution Slots: + SLOT23 + ========================================================================== */ + +#define Q6_V_vgetqfextor_VVR(Vx, Vu, Rt) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_get_qfext_oracc)(Vx, Vu, Rt) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.x=vsetqfext(Vu32,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vsetqfext_VR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vsetqfext_VR(Vu, Rt) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_set_qfext)(Vu, Rt) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.f8=vabs(Vu32.f8) + C Intrinsic Prototype: HVX_Vector Q6_V_vabs_V(HVX_Vector Vu) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vabs_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_f8)(Vu) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vadd(Vu32.f8,Vv32.f8) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vadd_VV(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vadd_VV(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf_f8)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.b=vcvt2(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vcvt2_VhfVhf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vb_vcvt2_VhfVhf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_b_hf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vcvt2(Vu32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt2_Vb(HVX_Vector Vu) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vcvt2_Vb(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_hf_b)(Vu) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vcvt2(Vu32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt2_Vub(HVX_Vector Vu) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vcvt2_Vub(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_hf_ub)(Vu) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vcvt2(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vcvt2_VhfVhf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vub_vcvt2_VhfVhf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_ub_hf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.f8=vcvt(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_V_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector + Vv) Instruction Type: CVI_VX Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vcvt_VhfVhf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_f8_hf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vcvt(Vu32.f8) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_V(HVX_Vector Vu) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vcvt_V(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_f8)(Vu) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.f8=vfmax(Vu32.f8,Vv32.f8) + C Intrinsic Prototype: HVX_Vector Q6_V_vfmax_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vfmax_VV(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_f8)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.f8=vfmin(Vu32.f8,Vv32.f8) + C Intrinsic Prototype: HVX_Vector Q6_V_vfmin_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vfmin_VV(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_f8)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.f8=vfneg(Vu32.f8) + C Intrinsic Prototype: HVX_Vector Q6_V_vfneg_V(HVX_Vector Vu) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vfneg_V(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_f8)(Vu) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32=vmerge(Vu32.x,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_V_vmerge_VVw(HVX_Vector Vu, HVX_Vector + Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vmerge_VVw(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmerge_qf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vmpy(Vu32.f8,Vv32.f8) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpy_VV(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vmpy_VV(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_f8)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vxx32.hf+=vmpy(Vu32.f8,Vv32.f8) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpyacc_WhfVV(HVX_VectorPair + Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution + Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vmpyacc_WhfVV(Vxx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_f8_acc)(Vxx, Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vmpy(Vu32.hf,Rt32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_VhfRhf(HVX_Vector Vu, Word32 + Rt) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf16_vmpy_VhfRhf(Vu, Rt) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_rt_hf)(Vu, Rt) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vmpy(Vu32.qf16,Rt32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Rhf(HVX_Vector Vu, + Word32 Rt) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf16_vmpy_Vqf16Rhf(Vu, Rt) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_rt_qf16)(Vu, Rt) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vmpy(Vu32.sf,Rt32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_VsfRsf(HVX_Vector Vu, Word32 + Rt) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf32_vmpy_VsfRsf(Vu, Rt) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_rt_sf)(Vu, Rt) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vsub(Vu32.f8,Vv32.f8) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vsub_VV(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vsub_VV(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_f8)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vabs(Vu32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vabs_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vabs_Vhf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf16_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vabs(Vu32.qf16) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vabs_Vqf16(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vabs_Vqf16(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf16_qf16)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vabs(Vu32.qf32) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vabs_Vqf32(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vabs_Vqf32(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf32_qf32)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vabs(Vu32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vabs_Vsf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vabs_Vsf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf32_sf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32=valign4(Vu32,Vv32,Rt8) + C Intrinsic Prototype: HVX_Vector Q6_V_valign4_VVR(HVX_Vector Vu, HVX_Vector + Vv, Word32 Rt) Instruction Type: CVI_VA Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_valign4_VVR(Vu, Vv, Rt) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valign4)(Vu, Vv, Rt) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.bf=Vuu32.qf32 + C Intrinsic Prototype: HVX_Vector Q6_Vbf_equals_Wqf32(HVX_VectorPair Vuu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vbf_equals_Wqf32(Vuu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_bf_qf32)(Vuu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.f8=Vu32.qf16 + C Intrinsic Prototype: HVX_Vector Q6_V_equals_Vqf16(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_equals_Vqf16(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_f8_qf16)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.h=Vu32.hf:rnd + C Intrinsic Prototype: HVX_Vector Q6_Vh_equals_Vhf_rnd(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_equals_Vhf_rnd(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_h_hf_rnd)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vdd32.qf16=Vu32.f8 + C Intrinsic Prototype: HVX_VectorPair Q6_Wqf16_equals_V(HVX_Vector Vu) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wqf16_equals_V(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_f8)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=Vu32.hf + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_equals_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_equals_Vhf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=Vu32.qf16 + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_equals_Vqf16(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_equals_Vqf16(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_qf16)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=Vu32.qf32 + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_equals_Vqf32(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_equals_Vqf32(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf32_qf32)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=Vu32.sf + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_equals_Vsf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_equals_Vsf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf32_sf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.eq(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhfVhf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eq_VhfVhf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf)(Vu, Vv)), -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.eq(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhfVhf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqand_QVhfVhf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_and)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.eq(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhfVhf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqor_QVhfVhf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_or)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.eq(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhfVhf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqxacc_QVhfVhf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_xor)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.eq(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VsfVsf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eq_VsfVsf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf)(Vu, Vv)), -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.eq(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVsfVsf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqand_QVsfVsf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_and)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.eq(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVsfVsf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqor_QVsfVsf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_or)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.eq(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVsfVsf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqxacc_QVsfVsf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_xor)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.w=vilog2(Vu32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vilog2_Vhf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.w=vilog2(Vu32.qf16) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vqf16(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vilog2_Vqf16(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_qf16)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.w=vilog2(Vu32.qf32) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vqf32(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vilog2_Vqf32(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_qf32)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.w=vilog2(Vu32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vsf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vilog2_Vsf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_sf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vneg(Vu32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vneg_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vneg_Vhf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf16_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vneg(Vu32.qf16) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vneg_Vqf16(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vneg_Vqf16(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf16_qf16)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vneg(Vu32.qf32) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vneg_Vqf32(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vneg_Vqf32(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf32_qf32)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vneg(Vu32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vneg_Vsf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vneg_Vsf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf32_sf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vsub(Vu32.hf,Vv32.qf16) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVqf16(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vsub_VhfVqf16(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_mix)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vsub(Vu32.sf,Vv32.qf32) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVqf32(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vsub_VsfVqf32(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_mix)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#endif /* __HVX__ */ + +#endif diff --git a/library/stdarch/crates/stdarch-gen-hexagon/src/hvx.rs b/library/stdarch/crates/stdarch-gen-hexagon/src/hvx.rs new file mode 100644 index 0000000000000..4d4b03c3ac204 --- /dev/null +++ b/library/stdarch/crates/stdarch-gen-hexagon/src/hvx.rs @@ -0,0 +1,1648 @@ +//! Hexagon HVX Code Generator +//! +//! This generator creates v64.rs and v128.rs from scratch using the LLVM HVX +//! header file as the sole source of truth. It parses the C intrinsic prototypes +//! and generates Rust wrapper functions with appropriate attributes. +//! +//! The two generated files provide: +//! - v64.rs: 64-byte vector mode intrinsics (512-bit vectors) +//! - v128.rs: 128-byte vector mode intrinsics (1024-bit vectors) +//! +//! Both modules are available unconditionally, but require the appropriate +//! target features to actually use the intrinsics. +//! +//! Usage: +//! cd crates/stdarch-gen-hexagon +//! cargo run +//! # Output is written to ../core_arch/src/hexagon/v64.rs and v128.rs + +use regex::Regex; +use std::collections::{HashMap, HashSet}; +use std::fs::File; +use std::io::Write; +use std::path::Path; +use stdarch_gen_common::GENERATED_MARKER; + +/// Mappings from HVX intrinsics to architecture-independent SIMD intrinsics. +/// These intrinsics have equivalent semantics and can be lowered to the generic form. +fn get_simd_intrinsic_mappings() -> HashMap<&'static str, &'static str> { + let mut map = HashMap::new(); + // Bitwise operations (element-size independent) + map.insert("vxor", "simd_xor"); + map.insert("vand", "simd_and"); + map.insert("vor", "simd_or"); + // Word (32-bit) arithmetic operations + map.insert("vaddw", "simd_add"); + map.insert("vsubw", "simd_sub"); + map +} + +/// The tracking issue number for the stdarch_hexagon feature +const TRACKING_ISSUE: &str = "151523"; + +/// HVX vector length mode +#[derive(Debug, Clone, Copy, PartialEq)] +enum VectorMode { + /// 64-byte vectors (512 bits) + V64, + /// 128-byte vectors (1024 bits) + V128, +} + +impl VectorMode { + fn bytes(&self) -> u32 { + match self { + VectorMode::V64 => 64, + VectorMode::V128 => 128, + } + } + + fn bits(&self) -> u32 { + self.bytes() * 8 + } + + fn lanes(&self) -> u32 { + self.bytes() / 4 // 32-bit lanes + } + + fn target_feature(&self) -> &'static str { + match self { + VectorMode::V64 => "hvx-length64b", + VectorMode::V128 => "hvx-length128b", + } + } +} + +/// LLVM version the header file is from (for reference) +/// Source: https://github.com/llvm/llvm-project/blob/llvmorg-22.1.0-rc1/clang/lib/Headers/hvx_hexagon_protos.h +const LLVM_VERSION: &str = "22.1.0-rc1"; + +/// Maximum HVX architecture version supported by rustc +/// Check with: rustc --target=hexagon-unknown-linux-musl --print target-features +const MAX_SUPPORTED_ARCH: u32 = 79; + +/// Local header file path (checked into the repository) +const HEADER_FILE: &str = "hvx_hexagon_protos.h"; + +/// Intrinsic information parsed from the LLVM header +#[derive(Debug, Clone)] +struct IntrinsicInfo { + /// The Q6_* intrinsic name (e.g., "Q6_V_vadd_VV") + q6_name: String, + /// The LLVM builtin name without prefix (e.g., "V6_vaddb") + builtin_name: String, + /// The short instruction name for assert_instr (e.g., "vaddb") + instr_name: String, + /// The assembly syntax from the comment + asm_syntax: String, + /// Instruction type + instr_type: String, + /// Execution slots + exec_slots: String, + /// Minimum HVX architecture version required + min_arch: u32, + /// Return type + return_type: RustType, + /// Parameters (name, type) + params: Vec<(String, RustType)>, + /// Whether this is a compound intrinsic (multiple builtins) + is_compound: bool, + /// For compound intrinsics: the parsed expression tree + compound_expr: Option, +} + +/// Expression tree for compound intrinsics +#[derive(Debug, Clone)] +enum CompoundExpr { + /// A call to a builtin: (builtin_name without V6_ prefix, arguments) + BuiltinCall(String, Vec), + /// A parameter reference by name + Param(String), + /// An integer literal (like -1) + IntLiteral(i32), +} + +/// Rust type mappings +#[derive(Debug, Clone, PartialEq)] +enum RustType { + HvxVector, + HvxVectorPair, + HvxVectorPred, + I32, + MutPtrHvxVector, + Unit, +} + +impl RustType { + fn from_c_type(c_type: &str) -> Option { + match c_type.trim() { + "HVX_Vector" => Some(RustType::HvxVector), + "HVX_VectorPair" => Some(RustType::HvxVectorPair), + "HVX_VectorPred" => Some(RustType::HvxVectorPred), + "Word32" => Some(RustType::I32), + "HVX_Vector*" => Some(RustType::MutPtrHvxVector), + "void" => Some(RustType::Unit), + _ => None, + } + } + + fn to_rust_str(&self) -> &'static str { + match self { + RustType::HvxVector => "HvxVector", + RustType::HvxVectorPair => "HvxVectorPair", + RustType::HvxVectorPred => "HvxVectorPred", + RustType::I32 => "i32", + RustType::MutPtrHvxVector => "*mut HvxVector", + RustType::Unit => "()", + } + } + + fn to_extern_str(&self) -> &'static str { + match self { + RustType::HvxVector => "HvxVector", + RustType::HvxVectorPair => "HvxVectorPair", + RustType::HvxVectorPred => "HvxVectorPred", + RustType::I32 => "i32", + RustType::MutPtrHvxVector => "*mut HvxVector", + RustType::Unit => "()", + } + } +} + +/// Parse a compound macro expression into an expression tree +fn parse_compound_expr(expr: &str) -> Option { + let expr = expr.trim(); + + // Try to match an integer literal (like -1) + if let Ok(n) = expr.parse::() { + return Some(CompoundExpr::IntLiteral(n)); + } + + // Try to match a simple parameter name (Vu, Vv, Rt, Qs, Qt, Qx, Vx, etc.) + // These are typically short identifiers in the macro + if expr.len() <= 3 + && expr.chars().all(|c| c.is_ascii_alphanumeric() || c == '_') + && !expr.contains("__") + { + return Some(CompoundExpr::Param(expr.to_lowercase())); + } + + // Check if it's wrapped in extra parens first + if expr.starts_with('(') && expr.ends_with(')') { + // Check if these parens wrap the entire expression + let inner = &expr[1..expr.len() - 1]; + // Count depth: if after removing outer parens the expression is balanced, + // the outer parens were enclosing everything + if is_balanced_parens(inner) { + // But we also need to verify these aren't part of a function call + // If the inner expression is balanced and the whole thing starts with ( + // and ends with ), it's a paren wrapper + let result = parse_compound_expr(inner); + if result.is_some() { + return result; + } + } + } + + // Try to match __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_xxx)(args) + // The args portion may contain nested calls, so we need to find the matching paren + if expr.starts_with("__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_") { + // Find the end of the builtin name (after V6_) + let prefix = "__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_"; + let after_prefix = &expr[prefix.len()..]; + if let Some(paren_pos) = after_prefix.find(')') { + let builtin_name = &after_prefix[..paren_pos]; + let rest = &after_prefix[paren_pos + 1..]; // Skip the closing ) of the WRAP + // rest should now be "(args)" + if rest.starts_with('(') && rest.ends_with(')') { + let args_str = &rest[1..rest.len() - 1]; + let args = parse_compound_args(args_str)?; + return Some(CompoundExpr::BuiltinCall(builtin_name.to_string(), args)); + } + } + } + + // Try to match __builtin_HEXAGON_V6_xxx(args) without wrap + if expr.starts_with("__builtin_HEXAGON_V6_") { + let prefix = "__builtin_HEXAGON_V6_"; + let after_prefix = &expr[prefix.len()..]; + if let Some(paren_pos) = after_prefix.find('(') { + let builtin_name = &after_prefix[..paren_pos]; + let rest = &after_prefix[paren_pos..]; + if rest.starts_with('(') && rest.ends_with(')') { + let args_str = &rest[1..rest.len() - 1]; + let args = parse_compound_args(args_str)?; + return Some(CompoundExpr::BuiltinCall(builtin_name.to_string(), args)); + } + } + } + + None +} + +/// Check if parentheses are balanced in a string +fn is_balanced_parens(s: &str) -> bool { + let mut depth = 0; + for c in s.chars() { + match c { + '(' => depth += 1, + ')' => { + depth -= 1; + if depth < 0 { + return false; + } + } + _ => {} + } + } + depth == 0 +} + +/// Parse comma-separated arguments, respecting nested parentheses +fn parse_compound_args(args_str: &str) -> Option> { + let mut args = Vec::new(); + let mut current = String::new(); + let mut depth = 0; + + for c in args_str.chars() { + match c { + '(' => { + depth += 1; + current.push(c); + } + ')' => { + depth -= 1; + current.push(c); + } + ',' if depth == 0 => { + let arg = current.trim().to_string(); + if !arg.is_empty() { + args.push(parse_compound_expr(&arg)?); + } + current.clear(); + } + _ => current.push(c), + } + } + + // Don't forget the last argument + let arg = current.trim().to_string(); + if !arg.is_empty() { + args.push(parse_compound_expr(&arg)?); + } + + Some(args) +} + +/// Extract all builtin names used in a compound expression +fn collect_builtins_from_expr(expr: &CompoundExpr, builtins: &mut HashSet) { + match expr { + CompoundExpr::BuiltinCall(name, args) => { + builtins.insert(name.clone()); + for arg in args { + collect_builtins_from_expr(arg, builtins); + } + } + CompoundExpr::Param(_) | CompoundExpr::IntLiteral(_) => {} + } +} + +/// Read the local HVX header file +fn read_header(crate_dir: &Path) -> Result { + let header_path = crate_dir.join(HEADER_FILE); + println!("Reading HVX header from: {}", header_path.display()); + println!(" (LLVM version: {})", LLVM_VERSION); + + std::fs::read_to_string(&header_path).map_err(|e| { + format!( + "Failed to read header file {}: {}", + header_path.display(), + e + ) + }) +} + +/// Parse a C function prototype to extract return type and parameters +fn parse_prototype(prototype: &str) -> Option<(RustType, Vec<(String, RustType)>)> { + // Pattern: ReturnType FunctionName(ParamType1 Param1, ParamType2 Param2, ...) + let proto_re = Regex::new(r"(\w+(?:\*)?)\s+Q6_\w+\(([^)]*)\)").unwrap(); + + if let Some(caps) = proto_re.captures(prototype) { + let return_type_str = caps[1].trim(); + let params_str = &caps[2]; + + let return_type = RustType::from_c_type(return_type_str)?; + + let mut params = Vec::new(); + if !params_str.trim().is_empty() { + // Pattern: Type Name or Type* Name + let param_re = Regex::new(r"(\w+\*?)\s+(\w+)").unwrap(); + for param in params_str.split(',') { + let param = param.trim(); + if let Some(pcaps) = param_re.captures(param) { + let ptype_str = pcaps[1].trim(); + let pname = pcaps[2].to_lowercase(); + if let Some(ptype) = RustType::from_c_type(ptype_str) { + params.push((pname, ptype)); + } else { + return None; // Unknown type + } + } + } + } + + Some((return_type, params)) + } else { + None + } +} + +/// Parse the LLVM header file to extract intrinsic information +fn parse_header(content: &str) -> Vec { + let mut intrinsics = Vec::new(); + + let arch_re = Regex::new(r"#if __HVX_ARCH__ >= (\d+)").unwrap(); + + // Regex to extract the simple builtin name from a macro body + // Match: __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_xxx)(args) + let simple_builtin_re = + Regex::new(r"__BUILTIN_VECTOR_WRAP\(__builtin_HEXAGON_(\w+)\)\([^)]*\)\s*$").unwrap(); + + // Also handle builtins without VECTOR_WRAP + let simple_builtin_re2 = Regex::new(r"__builtin_HEXAGON_(\w+)\([^)]*\)\s*$").unwrap(); + + // Regex to extract Q6 name from #define + let q6_name_re = Regex::new(r"#define\s+(Q6_\w+)").unwrap(); + + // Regex to extract macro expression body + let macro_expr_re = Regex::new(r"#define\s+Q6_\w+\([^)]*\)\s+(.+)").unwrap(); + + let lines: Vec<&str> = content.lines().collect(); + let mut current_arch: u32 = 60; + let mut i = 0; + + while i < lines.len() { + // Track architecture version + if let Some(caps) = arch_re.captures(lines[i]) { + if let Ok(arch) = caps[1].parse() { + current_arch = arch; + } + } + + // Look for Assembly Syntax comment block + if lines[i].contains("Assembly Syntax:") { + let mut asm_syntax = String::new(); + let mut prototype = String::new(); + let mut instr_type = String::new(); + let mut exec_slots = String::new(); + + // Parse the comment block + let mut j = i; + while j < lines.len() && !lines[j].starts_with("#define") { + let line = lines[j]; + if line.contains("Assembly Syntax:") { + if let Some(pos) = line.find("Assembly Syntax:") { + asm_syntax = line[pos + 16..].trim().to_string(); + } + } else if line.contains("C Intrinsic Prototype:") { + if let Some(pos) = line.find("C Intrinsic Prototype:") { + prototype = line[pos + 22..].trim().to_string(); + } + } else if line.contains("Instruction Type:") { + if let Some(pos) = line.find("Instruction Type:") { + instr_type = line[pos + 17..].trim().to_string(); + } + } else if line.contains("Execution Slots:") { + if let Some(pos) = line.find("Execution Slots:") { + exec_slots = line[pos + 16..].trim().to_string(); + } + } + j += 1; + } + + // Now find the #define line + while j < lines.len() && !lines[j].starts_with("#define") { + j += 1; + } + + if j < lines.len() { + let define_line = lines[j]; + + // Extract Q6 name and check if it's simple or compound + if let Some(caps) = q6_name_re.captures(define_line) { + let q6_name = caps[1].to_string(); + + // Get the full macro body (handle line continuations) + let mut macro_body = define_line.to_string(); + let mut k = j; + while macro_body.trim_end().ends_with('\\') && k + 1 < lines.len() { + k += 1; + macro_body.push_str(lines[k]); + } + + // Try to extract simple builtin name + let builtin_name = simple_builtin_re + .captures(¯o_body) + .or_else(|| simple_builtin_re2.captures(¯o_body)) + .map(|bcaps| bcaps[1].to_string()); + + // Check if it's a compound intrinsic (multiple __builtin calls) + let builtin_count = macro_body.matches("__builtin_HEXAGON_").count(); + let is_compound = builtin_count > 1; + + // Parse prototype + if let Some((return_type, params)) = parse_prototype(&prototype) { + if is_compound { + // For compound intrinsics, parse the expression + // Extract the macro body after the parameter list + if let Some(expr_caps) = macro_expr_re.captures(¯o_body) { + let expr_str = expr_caps[1].trim().replace(['\n', '\\'], " "); + let expr_str = expr_str.trim(); + + if let Some(compound_expr) = parse_compound_expr(expr_str) { + // For compound intrinsics, we use the outermost builtin + // as the "primary" for the instruction name + let (primary_builtin, instr_name) = match &compound_expr { + CompoundExpr::BuiltinCall(name, _) => { + (name.clone(), name.clone()) + } + _ => continue, + }; + + intrinsics.push(IntrinsicInfo { + q6_name, + builtin_name: format!("V6_{}", primary_builtin), + instr_name, + asm_syntax, + instr_type, + exec_slots, + min_arch: current_arch, + return_type, + params, + is_compound: true, + compound_expr: Some(compound_expr), + }); + } + } + } else if let Some(builtin) = builtin_name { + // Extract short instruction name + let instr_name = builtin + .strip_prefix("V6_") + .map(|s| s.to_string()) + .unwrap_or_else(|| builtin.clone()); + + intrinsics.push(IntrinsicInfo { + q6_name, + builtin_name: builtin, + instr_name, + asm_syntax, + instr_type, + exec_slots, + min_arch: current_arch, + return_type, + params, + is_compound: false, + compound_expr: None, + }); + } + } + } + } + i = j; + } + i += 1; + } + + intrinsics +} + +/// Generate the module documentation +fn generate_module_doc(mode: VectorMode) -> String { + format!( + r#"//! Hexagon HVX {bytes}-byte vector mode intrinsics +//! +//! This module provides intrinsics for the Hexagon Vector Extensions (HVX) +//! in {bytes}-byte vector mode ({bits}-bit vectors). +//! +//! HVX is a wide vector extension designed for high-performance signal processing. +//! [Hexagon HVX Programmer's Reference Manual](https://docs.qualcomm.com/doc/80-N2040-61) +//! +//! ## Vector Types +//! +//! In {bytes}-byte mode: +//! - `HvxVector` is {bits} bits ({bytes} bytes) containing {lanes} x 32-bit values +//! - `HvxVectorPair` is {pair_bits} bits ({pair_bytes} bytes) +//! - `HvxVectorPred` is {bits} bits ({bytes} bytes) for predicate operations +//! +//! To use this module, compile with `-C target-feature=+{target_feature}`. +//! +//! ## Naming Convention +//! +//! Function names preserve the original Q6 naming case because the convention +//! uses case to distinguish register types: +//! - `W` (uppercase) = vector pair (`HvxVectorPair`) +//! - `V` (uppercase) = vector (`HvxVector`) +//! - `Q` (uppercase) = predicate (`HvxVectorPred`) +//! - `R` = scalar register (`i32`) +//! +//! For example, `Q6_W_vcombine_VV` operates on a vector pair while +//! `Q6_V_hi_W` extracts a vector from a pair. +//! +//! ## Architecture Versions +//! +//! Different intrinsics require different HVX architecture versions. Use the +//! appropriate target feature to enable the required version: +//! - HVX v60: `-C target-feature=+hvxv60` (basic HVX operations) +//! - HVX v62: `-C target-feature=+hvxv62` +//! - HVX v65: `-C target-feature=+hvxv65` (includes floating-point support) +//! - HVX v66: `-C target-feature=+hvxv66` +//! - HVX v68: `-C target-feature=+hvxv68` +//! - HVX v69: `-C target-feature=+hvxv69` +//! - HVX v73: `-C target-feature=+hvxv73` +//! - HVX v79: `-C target-feature=+hvxv79` +//! +//! Each version includes all features from previous versions. +"#, + bytes = mode.bytes(), + bits = mode.bits(), + lanes = mode.lanes(), + pair_bytes = mode.bytes() * 2, + pair_bits = mode.bits() * 2, + target_feature = mode.target_feature(), + ) +} + +/// Generate the type definitions for a specific vector mode +fn generate_types(mode: VectorMode) -> String { + let lanes = mode.lanes(); + let pair_lanes = lanes * 2; + let bits = mode.bits(); + let bytes = mode.bytes(); + let pair_bits = bits * 2; + let pair_bytes = bytes * 2; + + format!( + r#" +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] + +#[cfg(test)] +use stdarch_test::assert_instr; + +use crate::intrinsics::simd::{{simd_add, simd_and, simd_or, simd_sub, simd_xor}}; + +// HVX type definitions for {bytes}-byte vector mode +types! {{ + #![unstable(feature = "stdarch_hexagon", issue = "{TRACKING_ISSUE}")] + + /// HVX vector type ({bits} bits / {bytes} bytes) + /// + /// This type represents a single HVX vector register containing {lanes} x 32-bit values. + pub struct HvxVector({lanes} x i32); + + /// HVX vector pair type ({pair_bits} bits / {pair_bytes} bytes) + /// + /// This type represents a pair of HVX vector registers, often used for + /// operations that produce double-width results. + pub struct HvxVectorPair({pair_lanes} x i32); + + /// HVX vector predicate type ({bits} bits / {bytes} bytes) + /// + /// This type represents a predicate vector used for conditional operations. + /// Each bit corresponds to a lane in the vector. + pub struct HvxVectorPred({lanes} x i32); +}} +"#, + bytes = bytes, + bits = bits, + lanes = lanes, + pair_bits = pair_bits, + pair_bytes = pair_bytes, + pair_lanes = pair_lanes, + TRACKING_ISSUE = TRACKING_ISSUE, + ) +} + +/// Builtin signature information for extern declarations +struct BuiltinSignature { + /// The V6_ prefixed name + full_name: String, + /// The short name (without V6_) + short_name: String, + /// Return type + return_type: RustType, + /// Parameter types + param_types: Vec, +} + +/// Get known signatures for builtins used in compound operations +/// These are the helper builtins that don't have their own Q6_ wrapper +fn get_compound_helper_signatures() -> HashMap { + let mut map = HashMap::new(); + + // vandvrt: HVX_Vector -> i32 -> HVX_Vector + // Converts predicate to vector representation. LLVM uses HVX_Vector for both. + map.insert( + "vandvrt".to_string(), + BuiltinSignature { + full_name: "V6_vandvrt".to_string(), + short_name: "vandvrt".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::I32], + }, + ); + + // vandqrt: HVX_Vector -> i32 -> HVX_Vector + // Converts vector representation back to predicate. LLVM uses HVX_Vector for both. + map.insert( + "vandqrt".to_string(), + BuiltinSignature { + full_name: "V6_vandqrt".to_string(), + short_name: "vandqrt".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::I32], + }, + ); + + // vandvrt_acc: HVX_Vector -> HVX_Vector -> i32 -> HVX_Vector + map.insert( + "vandvrt_acc".to_string(), + BuiltinSignature { + full_name: "V6_vandvrt_acc".to_string(), + short_name: "vandvrt_acc".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector, RustType::I32], + }, + ); + + // vandqrt_acc: HVX_Vector -> HVX_Vector -> i32 -> HVX_Vector + map.insert( + "vandqrt_acc".to_string(), + BuiltinSignature { + full_name: "V6_vandqrt_acc".to_string(), + short_name: "vandqrt_acc".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector, RustType::I32], + }, + ); + + // pred_and: HVX_Vector -> HVX_Vector -> HVX_Vector + map.insert( + "pred_and".to_string(), + BuiltinSignature { + full_name: "V6_pred_and".to_string(), + short_name: "pred_and".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + // pred_and_n: HVX_Vector -> HVX_Vector -> HVX_Vector + map.insert( + "pred_and_n".to_string(), + BuiltinSignature { + full_name: "V6_pred_and_n".to_string(), + short_name: "pred_and_n".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + // pred_or: HVX_Vector -> HVX_Vector -> HVX_Vector + map.insert( + "pred_or".to_string(), + BuiltinSignature { + full_name: "V6_pred_or".to_string(), + short_name: "pred_or".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + // pred_or_n: HVX_Vector -> HVX_Vector -> HVX_Vector + map.insert( + "pred_or_n".to_string(), + BuiltinSignature { + full_name: "V6_pred_or_n".to_string(), + short_name: "pred_or_n".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + // pred_xor: HVX_Vector -> HVX_Vector -> HVX_Vector + map.insert( + "pred_xor".to_string(), + BuiltinSignature { + full_name: "V6_pred_xor".to_string(), + short_name: "pred_xor".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + // pred_not: HVX_Vector -> HVX_Vector + map.insert( + "pred_not".to_string(), + BuiltinSignature { + full_name: "V6_pred_not".to_string(), + short_name: "pred_not".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector], + }, + ); + + // pred_scalar2: i32 -> HVX_Vector + map.insert( + "pred_scalar2".to_string(), + BuiltinSignature { + full_name: "V6_pred_scalar2".to_string(), + short_name: "pred_scalar2".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::I32], + }, + ); + + // Conditional store operations + map.insert( + "vS32b_qpred_ai".to_string(), + BuiltinSignature { + full_name: "V6_vS32b_qpred_ai".to_string(), + short_name: "vS32b_qpred_ai".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::HvxVector, + RustType::MutPtrHvxVector, + RustType::HvxVector, + ], + }, + ); + + map.insert( + "vS32b_nqpred_ai".to_string(), + BuiltinSignature { + full_name: "V6_vS32b_nqpred_ai".to_string(), + short_name: "vS32b_nqpred_ai".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::HvxVector, + RustType::MutPtrHvxVector, + RustType::HvxVector, + ], + }, + ); + + map.insert( + "vS32b_nt_qpred_ai".to_string(), + BuiltinSignature { + full_name: "V6_vS32b_nt_qpred_ai".to_string(), + short_name: "vS32b_nt_qpred_ai".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::HvxVector, + RustType::MutPtrHvxVector, + RustType::HvxVector, + ], + }, + ); + + map.insert( + "vS32b_nt_nqpred_ai".to_string(), + BuiltinSignature { + full_name: "V6_vS32b_nt_nqpred_ai".to_string(), + short_name: "vS32b_nt_nqpred_ai".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::HvxVector, + RustType::MutPtrHvxVector, + RustType::HvxVector, + ], + }, + ); + + // Conditional accumulation operations + for (suffix, _elem) in [("b", "byte"), ("h", "halfword"), ("w", "word")] { + // vaddbq, vaddhq, vaddwq + map.insert( + format!("vadd{}q", suffix), + BuiltinSignature { + full_name: format!("V6_vadd{}q", suffix), + short_name: format!("vadd{}q", suffix), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + // vaddbnq, vaddhnq, vaddwnq + map.insert( + format!("vadd{}nq", suffix), + BuiltinSignature { + full_name: format!("V6_vadd{}nq", suffix), + short_name: format!("vadd{}nq", suffix), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + } + + // Comparison operations with accumulation + // veqb_and, veqb_or, veqb_xor, etc. + for elem in ["b", "h", "w", "ub", "uh", "uw"] { + for op in ["and", "or", "xor"] { + // veq*_and, veq*_or, veq*_xor + map.insert( + format!("veq{}_{}", elem, op), + BuiltinSignature { + full_name: format!("V6_veq{}_{}", elem, op), + short_name: format!("veq{}_{}", elem, op), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + // vgt*_and, vgt*_or, vgt*_xor + map.insert( + format!("vgt{}_{}", elem, op), + BuiltinSignature { + full_name: format!("V6_vgt{}_{}", elem, op), + short_name: format!("vgt{}_{}", elem, op), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + } + } + + // Floating-point comparison operations (hf = half-float, sf = single-float) + for elem in ["hf", "sf"] { + // Basic comparison: vgt* + map.insert( + format!("vgt{}", elem), + BuiltinSignature { + full_name: format!("V6_vgt{}", elem), + short_name: format!("vgt{}", elem), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + for op in ["and", "or", "xor"] { + // vgt*_and, vgt*_or, vgt*_xor + map.insert( + format!("vgt{}_{}", elem, op), + BuiltinSignature { + full_name: format!("V6_vgt{}_{}", elem, op), + short_name: format!("vgt{}_{}", elem, op), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + } + } + + // Prefix operations with predicate + for elem in ["b", "h", "w"] { + map.insert( + format!("vprefixq{}", elem), + BuiltinSignature { + full_name: format!("V6_vprefixq{}", elem), + short_name: format!("vprefixq{}", elem), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector], + }, + ); + } + + // Scatter operations with predicate + map.insert( + "vscattermhq".to_string(), + BuiltinSignature { + full_name: "V6_vscattermhq".to_string(), + short_name: "vscattermhq".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::HvxVector, + RustType::I32, + RustType::I32, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + + map.insert( + "vscattermhwq".to_string(), + BuiltinSignature { + full_name: "V6_vscattermhwq".to_string(), + short_name: "vscattermhwq".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::HvxVector, + RustType::I32, + RustType::I32, + RustType::HvxVectorPair, + RustType::HvxVector, + ], + }, + ); + + map.insert( + "vscattermwq".to_string(), + BuiltinSignature { + full_name: "V6_vscattermwq".to_string(), + short_name: "vscattermwq".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::HvxVector, + RustType::I32, + RustType::I32, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + + // Add with carry saturation + map.insert( + "vaddcarrysat".to_string(), + BuiltinSignature { + full_name: "V6_vaddcarrysat".to_string(), + short_name: "vaddcarrysat".to_string(), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + + // Gather operations with predicate + map.insert( + "vgathermhq".to_string(), + BuiltinSignature { + full_name: "V6_vgathermhq".to_string(), + short_name: "vgathermhq".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::MutPtrHvxVector, + RustType::HvxVector, + RustType::I32, + RustType::I32, + RustType::HvxVector, + ], + }, + ); + + map.insert( + "vgathermhwq".to_string(), + BuiltinSignature { + full_name: "V6_vgathermhwq".to_string(), + short_name: "vgathermhwq".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::MutPtrHvxVector, + RustType::HvxVector, + RustType::I32, + RustType::I32, + RustType::HvxVectorPair, + ], + }, + ); + + map.insert( + "vgathermwq".to_string(), + BuiltinSignature { + full_name: "V6_vgathermwq".to_string(), + short_name: "vgathermwq".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::MutPtrHvxVector, + RustType::HvxVector, + RustType::I32, + RustType::I32, + RustType::HvxVector, + ], + }, + ); + + // Basic comparison operations (without accumulation) + for elem in ["b", "h", "w", "ub", "uh", "uw"] { + // vgt* - greater than + map.insert( + format!("vgt{}", elem), + BuiltinSignature { + full_name: format!("V6_vgt{}", elem), + short_name: format!("vgt{}", elem), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + // veq* - equal + map.insert( + format!("veq{}", elem), + BuiltinSignature { + full_name: format!("V6_veq{}", elem), + short_name: format!("veq{}", elem), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + } + + // Conditional subtraction operations (vsub*q, vsub*nq) + for elem in ["b", "h", "w"] { + map.insert( + format!("vsub{}q", elem), + BuiltinSignature { + full_name: format!("V6_vsub{}q", elem), + short_name: format!("vsub{}q", elem), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + map.insert( + format!("vsub{}nq", elem), + BuiltinSignature { + full_name: format!("V6_vsub{}nq", elem), + short_name: format!("vsub{}nq", elem), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + } + + // vmux - vector mux (select based on predicate) + map.insert( + "vmux".to_string(), + BuiltinSignature { + full_name: "V6_vmux".to_string(), + short_name: "vmux".to_string(), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + + // vswap - vector swap based on predicate + map.insert( + "vswap".to_string(), + BuiltinSignature { + full_name: "V6_vswap".to_string(), + short_name: "vswap".to_string(), + return_type: RustType::HvxVectorPair, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + + // shuffeq operations - take vectors (internal pred representation) and return vector + for elem in ["h", "w"] { + map.insert( + format!("shuffeq{}", elem), + BuiltinSignature { + full_name: format!("V6_shuffeq{}", elem), + short_name: format!("shuffeq{}", elem), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + } + + // Predicate AND with vector operations + map.insert( + "vandvqv".to_string(), + BuiltinSignature { + full_name: "V6_vandvqv".to_string(), + short_name: "vandvqv".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + map.insert( + "vandvnqv".to_string(), + BuiltinSignature { + full_name: "V6_vandvnqv".to_string(), + short_name: "vandvnqv".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + // vandnqrt and vandnqrt_acc + map.insert( + "vandnqrt".to_string(), + BuiltinSignature { + full_name: "V6_vandnqrt".to_string(), + short_name: "vandnqrt".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::I32], + }, + ); + + map.insert( + "vandnqrt_acc".to_string(), + BuiltinSignature { + full_name: "V6_vandnqrt_acc".to_string(), + short_name: "vandnqrt_acc".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector, RustType::I32], + }, + ); + + // pred_scalar2v2 + map.insert( + "pred_scalar2v2".to_string(), + BuiltinSignature { + full_name: "V6_pred_scalar2v2".to_string(), + short_name: "pred_scalar2v2".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::I32], + }, + ); + + map +} + +/// Generate extern declarations for all intrinsics for a specific vector mode +fn generate_extern_block(intrinsics: &[IntrinsicInfo], mode: VectorMode) -> String { + let mut output = String::new(); + + // Collect unique builtins to avoid duplicates + let mut seen_builtins: HashSet = HashSet::new(); + let mut decls: Vec<(String, String, RustType, Vec)> = Vec::new(); + + // First, add simple intrinsics + for info in intrinsics.iter().filter(|i| !i.is_compound) { + if seen_builtins.contains(&info.builtin_name) { + continue; + } + seen_builtins.insert(info.builtin_name.clone()); + + let param_types: Vec = info.params.iter().map(|(_, t)| t.clone()).collect(); + decls.push(( + info.builtin_name.clone(), + info.instr_name.clone(), + info.return_type.clone(), + param_types, + )); + } + + // Then, collect all builtins used in compound expressions + let helper_sigs = get_compound_helper_signatures(); + let mut compound_builtins: HashSet = HashSet::new(); + + for info in intrinsics.iter().filter(|i| i.is_compound) { + if let Some(ref expr) = info.compound_expr { + collect_builtins_from_expr(expr, &mut compound_builtins); + } + } + + // Add compound helper builtins + let mut missing_builtins = Vec::new(); + for builtin_name in compound_builtins { + let full_name = format!("V6_{}", builtin_name); + if seen_builtins.contains(&full_name) { + continue; + } + seen_builtins.insert(full_name.clone()); + + if let Some(sig) = helper_sigs.get(&builtin_name) { + decls.push(( + sig.full_name.clone(), + sig.short_name.clone(), + sig.return_type.clone(), + sig.param_types.clone(), + )); + } else { + missing_builtins.push(builtin_name); + } + } + + // Report missing builtins (for development purposes) + if !missing_builtins.is_empty() { + eprintln!("Warning: Missing helper signatures for compound builtins:"); + for name in &missing_builtins { + eprintln!(" - {}", name); + } + } + + // Sort by builtin name for consistent output + decls.sort_by(|a, b| a.0.cmp(&b.0)); + + // Generate intrinsic declarations for the specified mode + output.push_str(&format!( + "// LLVM intrinsic declarations for {}-byte vector mode\n", + mode.bytes() + )); + output.push_str("#[allow(improper_ctypes)]\n"); + output.push_str("unsafe extern \"unadjusted\" {\n"); + + for (builtin_name, instr_name, return_type, param_types) in &decls { + let base_link = builtin_name.replace('_', "."); + // 128-byte mode uses .128B suffix, 64-byte mode doesn't + let link_name = if builtin_name.starts_with("V6_") && mode == VectorMode::V128 { + format!("llvm.hexagon.{}.128B", base_link) + } else { + format!("llvm.hexagon.{}", base_link) + }; + + let params_str = if param_types.is_empty() { + String::new() + } else { + param_types + .iter() + .map(|t| format!("_: {}", t.to_extern_str())) + .collect::>() + .join(", ") + }; + + let return_str = if *return_type == RustType::Unit { + " -> ()".to_string() + } else { + format!(" -> {}", return_type.to_extern_str()) + }; + + output.push_str(&format!( + " #[link_name = \"{}\"]\n fn {}({}){};\n", + link_name, instr_name, params_str, return_str + )); + } + + output.push_str("}\n"); + output +} + +/// Generate Rust code for a compound expression +/// `params` maps parameter names to their types in the function signature +/// Get the type of an expression +fn get_expr_type( + expr: &CompoundExpr, + params: &HashMap, + helper_sigs: &HashMap, +) -> Option { + match expr { + CompoundExpr::BuiltinCall(name, _) => { + helper_sigs.get(name).map(|sig| sig.return_type.clone()) + } + CompoundExpr::Param(name) => params.get(name).cloned(), + CompoundExpr::IntLiteral(_) => Some(RustType::I32), + } +} + +fn generate_compound_expr_code( + expr: &CompoundExpr, + params: &HashMap, + helper_sigs: &HashMap, +) -> String { + match expr { + CompoundExpr::BuiltinCall(name, args) => { + // Get the expected parameter types for this builtin + let expected_types = helper_sigs + .get(name) + .map(|sig| sig.param_types.clone()) + .unwrap_or_default(); + + let args_code: Vec = args + .iter() + .enumerate() + .map(|(i, arg)| { + let arg_code = generate_compound_expr_code(arg, params, helper_sigs); + + // Check if we need to transmute this argument + let expected_type = expected_types.get(i); + let actual_type = get_expr_type(arg, params, helper_sigs); + + // If the builtin expects HvxVector but the arg is HvxVectorPred, transmute + if expected_type == Some(&RustType::HvxVector) + && actual_type == Some(RustType::HvxVectorPred) + { + format!( + "core::mem::transmute::({})", + arg_code + ) + } else { + arg_code + } + }) + .collect(); + format!("{}({})", name, args_code.join(", ")) + } + CompoundExpr::Param(name) => name.clone(), + CompoundExpr::IntLiteral(n) => n.to_string(), + } +} + +/// Get the primary instruction name from a compound expression (innermost significant op) +fn get_compound_primary_instr(expr: &CompoundExpr) -> Option { + match expr { + CompoundExpr::BuiltinCall(name, args) => { + // For vandqrt wrapper, look inside + if name == "vandqrt" && !args.is_empty() { + if let Some(inner) = get_compound_primary_instr(&args[0]) { + return Some(inner); + } + } + // For store operations, use the store name + if name.starts_with("vS32b") { + return Some(name.clone()); + } + // For conditional accumulation, use the add name + if name.starts_with("vadd") && (name.ends_with("q") || name.ends_with("nq")) { + return Some(name.clone()); + } + // For predicate operations + if name.starts_with("pred_") { + return Some(name.clone()); + } + // For comparison operations with accumulation + if (name.starts_with("veq") || name.starts_with("vgt")) + && (name.ends_with("_and") || name.ends_with("_or") || name.ends_with("_xor")) + { + return Some(name.clone()); + } + Some(name.clone()) + } + _ => None, + } +} + +/// Get override implementations for specific compound intrinsics. +/// Some C macros rely on implicit type conversions that don't work with +/// our stricter Rust types, so we provide corrected implementations. +fn get_compound_overrides() -> HashMap<&'static str, &'static str> { + let mut map = HashMap::new(); + + // Q6_V_vand_QR: takes pred, returns vec + // Use transmute to convert pred to vec for LLVM, call vandvrt + map.insert( + "Q6_V_vand_QR", + "vandvrt(core::mem::transmute::(qu), rt)", + ); + + // Q6_V_vandor_VQR: takes vec and pred, returns vec + map.insert( + "Q6_V_vandor_VQR", + "vandvrt_acc(vx, core::mem::transmute::(qu), rt)", + ); + + // Q6_Q_vand_VR: takes vec, returns pred + map.insert( + "Q6_Q_vand_VR", + "core::mem::transmute::(vandqrt(vu, rt))", + ); + + // Q6_Q_vandor_QVR: takes pred and vec, returns pred + map.insert( + "Q6_Q_vandor_QVR", + "core::mem::transmute::(vandqrt_acc(core::mem::transmute::(qx), vu, rt))", + ); + + map +} + +/// Generate wrapper functions for all intrinsics +fn generate_functions(intrinsics: &[IntrinsicInfo]) -> String { + let mut output = String::new(); + let simd_mappings = get_simd_intrinsic_mappings(); + + // Generate simple intrinsics + for info in intrinsics.iter().filter(|i| !i.is_compound) { + let rust_name = &info.q6_name; + + // Generate doc comment + output.push_str(&format!("/// `{}`\n", info.asm_syntax)); + output.push_str("///\n"); + output.push_str(&format!("/// Instruction Type: {}\n", info.instr_type)); + output.push_str(&format!("/// Execution Slots: {}\n", info.exec_slots)); + + // Generate attributes + output.push_str("#[inline]\n"); + output.push_str(&format!( + "#[cfg_attr(target_arch = \"hexagon\", target_feature(enable = \"hvxv{}\"))]\n", + info.min_arch + )); + + // Check if we should use simd intrinsic instead + let use_simd = simd_mappings.get(info.instr_name.as_str()); + + // assert_instr uses the original instruction name + output.push_str(&format!( + "#[cfg_attr(test, assert_instr({}))]\n", + info.instr_name + )); + + output.push_str(&format!( + "#[unstable(feature = \"stdarch_hexagon\", issue = \"{}\")]\n", + TRACKING_ISSUE + )); + + // Generate function signature + let params_str = info + .params + .iter() + .map(|(name, ty)| format!("{}: {}", name, ty.to_rust_str())) + .collect::>() + .join(", "); + + let return_str = if info.return_type == RustType::Unit { + String::new() + } else { + format!(" -> {}", info.return_type.to_rust_str()) + }; + + output.push_str(&format!( + "pub unsafe fn {}({}){} {{\n", + rust_name, params_str, return_str + )); + + // Generate function body + let args_str = info + .params + .iter() + .map(|(name, _)| name.as_str()) + .collect::>() + .join(", "); + + if let Some(simd_fn) = use_simd { + // Use architecture-independent simd intrinsic + output.push_str(&format!(" {}({})\n", simd_fn, args_str)); + } else { + // Use the LLVM intrinsic + output.push_str(&format!(" {}({})\n", info.instr_name, args_str)); + } + + output.push_str("}\n\n"); + } + + // Generate compound intrinsics + let helper_sigs = get_compound_helper_signatures(); + let overrides = get_compound_overrides(); + for info in intrinsics.iter().filter(|i| i.is_compound) { + if let Some(ref compound_expr) = info.compound_expr { + let rust_name = &info.q6_name; + + // Get the primary instruction for assert_instr + let _primary_instr = get_compound_primary_instr(compound_expr) + .unwrap_or_else(|| info.instr_name.clone()); + + // Generate doc comment + output.push_str(&format!("/// `{}`\n", info.asm_syntax)); + output.push_str("///\n"); + output.push_str( + "/// This is a compound operation composed of multiple HVX instructions.\n", + ); + if !info.instr_type.is_empty() { + output.push_str(&format!("/// Instruction Type: {}\n", info.instr_type)); + } + if !info.exec_slots.is_empty() { + output.push_str(&format!("/// Execution Slots: {}\n", info.exec_slots)); + } + + // Generate attributes + output.push_str("#[inline]\n"); + output.push_str(&format!( + "#[cfg_attr(target_arch = \"hexagon\", target_feature(enable = \"hvxv{}\"))]\n", + info.min_arch + )); + + // For compound ops, we skip assert_instr since they emit multiple instructions + // output.push_str(&format!( + // "#[cfg_attr(test, assert_instr({}))]\n", + // primary_instr + // )); + + output.push_str(&format!( + "#[unstable(feature = \"stdarch_hexagon\", issue = \"{}\")]\n", + TRACKING_ISSUE + )); + + // Generate function signature + let params_str = info + .params + .iter() + .map(|(name, ty)| format!("{}: {}", name, ty.to_rust_str())) + .collect::>() + .join(", "); + + let return_str = if info.return_type == RustType::Unit { + String::new() + } else { + format!(" -> {}", info.return_type.to_rust_str()) + }; + + output.push_str(&format!( + "pub unsafe fn {}({}){} {{\n", + rust_name, params_str, return_str + )); + + // Check if we have an override for this intrinsic + let body = if let Some(override_body) = overrides.get(info.q6_name.as_str()) { + override_body.to_string() + } else { + // Build param type map for expression code generation + let param_types: HashMap = info.params.iter().cloned().collect(); + // Generate function body from compound expression + let expr_body = + generate_compound_expr_code(compound_expr, ¶m_types, &helper_sigs); + + // Check if we need to transmute the result + let expr_return_type = get_expr_type(compound_expr, ¶m_types, &helper_sigs); + if info.return_type == RustType::HvxVectorPred + && expr_return_type == Some(RustType::HvxVector) + { + format!( + "core::mem::transmute::({})", + expr_body + ) + } else { + expr_body + } + }; + output.push_str(&format!(" {}\n", body)); + + output.push_str("}\n\n"); + } + } + + output +} + +/// Generate a module file for a specific vector mode +fn generate_module_file( + intrinsics: &[IntrinsicInfo], + output_path: &Path, + mode: VectorMode, +) -> Result<(), String> { + let mut output = + File::create(output_path).map_err(|e| format!("Failed to create output: {}", e))?; + + writeln!(output, "{}", GENERATED_MARKER).map_err(|e| e.to_string())?; + writeln!(output, "{}", generate_module_doc(mode)).map_err(|e| e.to_string())?; + writeln!(output, "{}", generate_types(mode)).map_err(|e| e.to_string())?; + writeln!(output, "{}", generate_extern_block(intrinsics, mode)).map_err(|e| e.to_string())?; + writeln!(output, "{}", generate_functions(intrinsics)).map_err(|e| e.to_string())?; + + // Ensure file is flushed before running rustfmt + drop(output); + + // Run rustfmt on the generated file + let status = std::process::Command::new("rustfmt") + .arg(output_path) + .status() + .map_err(|e| format!("Failed to run rustfmt: {}", e))?; + + if !status.success() { + return Err("rustfmt failed".to_string()); + } + + Ok(()) +} + +/// Parse the HVX header in `crate_dir` and write `v64.rs` and `v128.rs` into `out_dir`. +pub fn generate(crate_dir: &std::path::Path, out_dir: &std::path::Path) -> Result<(), String> { + let header_content = read_header(crate_dir)?; + let all_intrinsics = parse_header(&header_content); + let intrinsics: Vec<_> = all_intrinsics + .into_iter() + .filter(|i| i.min_arch <= MAX_SUPPORTED_ARCH) + .collect(); + for (filename, vmode) in [("v64.rs", VectorMode::V64), ("v128.rs", VectorMode::V128)] { + let path = out_dir.join(filename); + generate_module_file(&intrinsics, &path, vmode)?; + } + Ok(()) +} diff --git a/library/stdarch/crates/stdarch-gen-hexagon/src/main.rs b/library/stdarch/crates/stdarch-gen-hexagon/src/main.rs new file mode 100644 index 0000000000000..88ef4fe11f332 --- /dev/null +++ b/library/stdarch/crates/stdarch-gen-hexagon/src/main.rs @@ -0,0 +1,35 @@ +//! Hexagon code generator. +//! +//! Single binary that produces every generated file under +//! `core_arch/src/hexagon/`: scalar.rs (scalar intrinsics) and +//! v64.rs / v128.rs (HVX intrinsics). +//! +//! Run in check or bless mode via `STDARCH_GEN_MODE`. + +mod hvx; +mod scalar; + +use std::path::PathBuf; +use stdarch_gen_common::{run_generator, Mode}; + +fn main() -> Result<(), String> { + let crate_dir = std::env::var("CARGO_MANIFEST_DIR") + .map(PathBuf::from) + .unwrap_or_else(|_| std::env::current_dir().unwrap()); + + let hexagon_dir = crate_dir.join("../core_arch/src/hexagon"); + // Either "check" to check the output versus the committed output, or "bless" + // to update the output. + let mode = Mode::from_env(); + + run_generator(&hexagon_dir, mode, |out_dir| -> Result<(), String> { + // Here scalar::generate writes scalar.rs . + scalar::generate(&crate_dir, out_dir)?; + // Here hvx::generate writes v64.rs and v128.rs . + hvx::generate(&crate_dir, out_dir)?; + Ok(()) + }) + .map_err(|e| e.to_string())?; + + Ok(()) +} diff --git a/library/stdarch/crates/stdarch-gen-hexagon/src/scalar.rs b/library/stdarch/crates/stdarch-gen-hexagon/src/scalar.rs new file mode 100644 index 0000000000000..4beee35df97ae --- /dev/null +++ b/library/stdarch/crates/stdarch-gen-hexagon/src/scalar.rs @@ -0,0 +1,664 @@ +//! Hexagon Scalar Code Generator +//! +//! This generator creates scalar.rs from the LLVM `hexagon_protos.h` header file. +//! It parses the C intrinsic prototypes and generates Rust wrapper functions +//! with appropriate attributes for all scalar (non-HVX) Hexagon intrinsics. +//! +//! The generated module provides ~901 scalar intrinsic wrappers covering: +//! - Arithmetic, multiply, shift, saturate operations +//! - Compare, floating-point, and other scalar operations +//! +//! Intrinsics with `void*`/`void**` parameters (circular-addressing) are skipped +//! because they have no corresponding LLVM intrinsic. +//! +//! Usage: +//! cd crates/stdarch-gen-hexagon-scalar +//! cargo run +//! # Output is written to ../core_arch/src/hexagon/scalar.rs + +use regex::Regex; +use std::collections::HashMap; +use std::fs::File; +use std::io::Write; +use std::path::Path; +use stdarch_gen_common::GENERATED_MARKER; + +/// Extract the instruction mnemonic from the assembly syntax string. +/// +/// Examples: +/// - `Rd32=abs(Rs32)` → Some("abs") +/// - `Rd32=add(Rs32,Rt32):sat` → Some("add") +/// - `Rx32+=mpy(Rs32,Rt32)` → Some("mpy") +/// - `Rd32=dmpause` → Some("dmpause") +/// - `dmlink(Rs32,Rt32)` → Some("dmlink") +/// - `Rd32=Rs32` → None (simple transfer) +/// - `Rx32.h=#u16` → None (immediate load) +/// - `Rdd32=#s8` → None (immediate load) +fn extract_instr_name(asm_syntax: &str) -> Option { + // Find the operator: +=, -=, or = + let after_op = if let Some(pos) = asm_syntax.find("+=") { + &asm_syntax[pos + 2..] + } else if let Some(pos) = asm_syntax.find("-=") { + &asm_syntax[pos + 2..] + } else if let Some(pos) = asm_syntax.find('=') { + &asm_syntax[pos + 1..] + } else { + // No assignment operator: try function-call-style syntax like "dmlink(Rs32,Rt32)". + // The mnemonic is the leading lowercase identifier. + return extract_leading_mnemonic(asm_syntax); + }; + + // After the operator, we expect a lowercase letter starting the mnemonic. + // Skip if it starts with uppercase (register name like Rs32) or # (immediate). + extract_leading_mnemonic(after_op) +} + +/// Extract a leading lowercase mnemonic from the given string. +/// +/// Returns `Some(mnemonic)` if the string starts with a lowercase ASCII letter, +/// collecting all subsequent alphanumeric/underscore characters. Returns `None` +/// if the string is empty or starts with an uppercase letter, `#`, etc. +fn extract_leading_mnemonic(s: &str) -> Option { + let first_char = s.chars().next()?; + if !first_char.is_ascii_lowercase() { + return None; + } + let mnemonic: String = s + .chars() + .take_while(|c| c.is_ascii_alphanumeric() || *c == '_') + .collect(); + if mnemonic.is_empty() { + None + } else { + Some(mnemonic) + } +} + +/// The tracking issue number for the stdarch_hexagon feature +const TRACKING_ISSUE: &str = "151523"; + +/// LLVM version the header file is from (for reference) +const LLVM_VERSION: &str = "22.1.0"; + +/// Local header file path (checked into the repository) +const HEADER_FILE: &str = "hexagon_protos.h"; + +/// Rust type representation for scalar intrinsics +#[derive(Debug, Clone, PartialEq)] +enum RustType { + I32, + I64, + F32, + F64, + Unit, +} + +impl RustType { + fn from_c_type(c_type: &str) -> Option { + match c_type.trim() { + "Word32" | "UWord32" | "Byte" | "Address" => Some(RustType::I32), + "Word64" | "UWord64" => Some(RustType::I64), + "Float32" => Some(RustType::F32), + "Float64" => Some(RustType::F64), + "void" => Some(RustType::Unit), + _ => None, + } + } + + fn to_rust_str(&self) -> &'static str { + match self { + RustType::I32 => "i32", + RustType::I64 => "i64", + RustType::F32 => "f32", + RustType::F64 => "f64", + RustType::Unit => "()", + } + } +} + +/// Information about an immediate operand parameter. +/// +/// Detected from C prototype parameter names like `Is16` (signed 16-bit), +/// `Iu5` (unsigned 5-bit), `IU5` (unsigned 5-bit secondary), `Iu6_2` +/// (unsigned 6-bit with 2-bit alignment). +#[derive(Debug, Clone)] +struct ImmediateInfo { + /// Whether this is a signed immediate + signed: bool, + /// Number of bits in the immediate field + bits: u32, +} + +/// Arch guard for an intrinsic +#[derive(Debug, Clone, PartialEq)] +enum ArchGuard { + /// No guard (base v5/v55 intrinsics) + None, + /// `#if __HEXAGON_ARCH__ >= N` + Arch(u32), + /// `#if __HEXAGON_ARCH__ >= N && defined __HEXAGON_AUDIO__` + ArchAudio(u32), +} + +impl ArchGuard { + /// Returns a doc comment describing the required architecture version, + /// or None if no specific version is needed. + fn requires_doc(&self) -> Option { + match self { + ArchGuard::None => Option::None, + ArchGuard::Arch(ver) => Some(format!("Requires: V{}", ver)), + ArchGuard::ArchAudio(ver) => Some(format!("Requires: V{}, Audio", ver)), + } + } + + /// Returns a `#[cfg_attr(target_arch = "hexagon", target_feature(enable = "..."))]` + /// attribute string, or None for base intrinsics that have no user-facing feature gate. + fn target_feature_attr(&self) -> Option { + match self { + ArchGuard::None => None, + ArchGuard::Arch(ver) => Some(format!( + "#[cfg_attr(target_arch = \"hexagon\", target_feature(enable = \"v{}\"))]", + ver + )), + ArchGuard::ArchAudio(ver) => Some(format!( + "#[cfg_attr(target_arch = \"hexagon\", target_feature(enable = \"v{},audio\"))]", + ver + )), + } + } +} + +/// Parsed scalar intrinsic information +#[derive(Debug, Clone)] +struct ScalarIntrinsic { + /// Q6 name (e.g., "Q6_R_add_RR") + q6_name: String, + /// Builtin suffix (e.g., "A2_add") - from __builtin_HEXAGON_A2_add + builtin_name: String, + /// Assembly syntax + asm_syntax: String, + /// Instruction type + instr_type: String, + /// Execution slots + exec_slots: String, + /// Return type + return_type: RustType, + /// Parameters (name, type, optional immediate info) + params: Vec<(String, RustType, Option)>, + /// Architecture guard + arch_guard: ArchGuard, +} + +impl ScalarIntrinsic { + /// Generate the LLVM link name: A2_add -> llvm.hexagon.A2.add + fn llvm_link_name(&self) -> String { + format!("llvm.hexagon.{}", self.builtin_name.replace('_', ".")) + } + + /// Generate the Rust function name: Q6_R_add_RR -> Q6_R_add_RR + /// + /// We preserve the original case because the Q6 naming convention uses + /// case to distinguish register types: + /// - `P` (uppercase) = 64-bit register pair (Word64) + /// - `p` (lowercase) = predicate register (Byte) + fn rust_fn_name(&self) -> String { + self.q6_name.clone() + } + + /// Generate the extern function name: A2_add -> hexagon_A2_add + fn extern_fn_name(&self) -> String { + format!("hexagon_{}", self.builtin_name) + } +} + +/// Read the local header file +fn read_header(crate_dir: &Path) -> Result { + let header_path = crate_dir.join(HEADER_FILE); + println!("Reading scalar header from: {}", header_path.display()); + println!(" (LLVM version: {})", LLVM_VERSION); + + std::fs::read_to_string(&header_path).map_err(|e| { + format!( + "Failed to read header file {}: {}", + header_path.display(), + e + ) + }) +} + +/// Detect whether a C parameter name represents an immediate operand. +/// +/// C prototype parameter names follow the pattern `I[usUS]\d+` for immediates: +/// - `Is16` → signed 16-bit +/// - `Iu5` → unsigned 5-bit +/// - `IS8` → signed 8-bit (secondary) +/// - `IU5` → unsigned 5-bit (secondary) +/// - `Iu6_2` → unsigned 6-bit (with alignment suffix) +fn detect_immediate(original_name: &str, imm_re: &Regex) -> Option { + imm_re.captures(original_name).map(|caps| { + let sign_char = &caps[1]; + let bits: u32 = caps[2].parse().unwrap(); + ImmediateInfo { + signed: sign_char == "s" || sign_char == "S", + bits, + } + }) +} + +/// Parse a C function prototype to extract return type and parameters +fn parse_prototype( + prototype: &str, + proto_re: &Regex, + param_re: &Regex, + imm_re: &Regex, +) -> Option<(RustType, Vec<(String, RustType, Option)>)> { + if let Some(caps) = proto_re.captures(prototype) { + let return_type_str = caps[1].trim(); + let params_str = &caps[2]; + + // Skip if return type is unknown + let return_type = RustType::from_c_type(return_type_str)?; + + let mut params = Vec::new(); + if !params_str.trim().is_empty() { + let mut name_counts: HashMap = HashMap::new(); + for param in params_str.split(',') { + let param = param.trim(); + if let Some(pcaps) = param_re.captures(param) { + let ptype_str = &pcaps[1]; + let original_name = &pcaps[2]; + let base_name = original_name.to_lowercase(); + + // Skip intrinsics with void* or void** params + if ptype_str.contains("void") { + return None; + } + + if let Some(ptype) = RustType::from_c_type(ptype_str) { + // Detect immediate operands from the original C name + let imm_info = detect_immediate(original_name, imm_re); + + // De-duplicate parameter names by appending a suffix + let count = name_counts.entry(base_name.clone()).or_insert(0); + *count += 1; + let pname = if *count > 1 { + format!("{}_{}", base_name, count) + } else { + base_name + }; + params.push((pname, ptype, imm_info)); + } else { + return None; // Unknown type + } + } + } + } + + Some((return_type, params)) + } else { + None + } +} + +/// Parse the header file to extract all scalar intrinsics +fn parse_header(content: &str) -> Vec { + let mut intrinsics = Vec::new(); + + // Pre-compile all regexes once + let arch_guard_re = Regex::new(r"#if __HEXAGON_ARCH__ >= (\d+)(.*)").unwrap(); + let q6_define_re = Regex::new(r"#define\s+(Q6_\w+)\s+__builtin_HEXAGON_(\w+)").unwrap(); + let proto_re = Regex::new(r"(\w+)\s+Q6_\w+\(([^)]*)\)").unwrap(); + let param_re = Regex::new(r"(\w+\*{0,2})\s+(\w+)").unwrap(); + let imm_re = Regex::new(r"^I([uUsS])(\d+)").unwrap(); + + let lines: Vec<&str> = content.lines().collect(); + let mut current_guard = ArchGuard::None; + let mut i = 0; + + while i < lines.len() { + let line = lines[i].trim(); + + // Track #if guards + if let Some(caps) = arch_guard_re.captures(line) { + let arch_ver: u32 = caps[1].parse().unwrap_or(0); + let rest = &caps[2]; + if rest.contains("__HEXAGON_AUDIO__") { + current_guard = ArchGuard::ArchAudio(arch_ver); + } else { + current_guard = ArchGuard::Arch(arch_ver); + } + i += 1; + continue; + } + + // Track #endif to reset guard + if line.starts_with("#endif") + && !line.contains("__HEXAGON_PROTOS_H_") + && !line.contains("__HVX__") + { + current_guard = ArchGuard::None; + i += 1; + continue; + } + + // Look for comment blocks with Assembly Syntax + if line.contains("Assembly Syntax:") { + let mut asm_syntax = String::new(); + let mut prototype = String::new(); + let mut instr_type = String::new(); + let mut exec_slots = String::new(); + + // Parse the comment block + let mut j = i; + while j < lines.len() && !lines[j].trim().starts_with("#define") { + let cline = lines[j]; + if cline.contains("Assembly Syntax:") { + if let Some(pos) = cline.find("Assembly Syntax:") { + asm_syntax = cline[pos + 16..].trim().to_string(); + } + } else if cline.contains("C Intrinsic Prototype:") { + if let Some(pos) = cline.find("C Intrinsic Prototype:") { + prototype = cline[pos + 22..].trim().to_string(); + } + } else if cline.contains("Instruction Type:") { + if let Some(pos) = cline.find("Instruction Type:") { + instr_type = cline[pos + 17..].trim().to_string(); + } + } else if cline.contains("Execution Slots:") { + if let Some(pos) = cline.find("Execution Slots:") { + exec_slots = cline[pos + 16..].trim().to_string(); + } + } + j += 1; + } + + // Find the #define line + while j < lines.len() && !lines[j].trim().starts_with("#define") { + j += 1; + } + + if j < lines.len() { + let define_line = lines[j]; + + if let Some(caps) = q6_define_re.captures(define_line) { + let q6_name = caps[1].to_string(); + let builtin_name = caps[2].to_string(); + + // Parse the C prototype + if let Some((return_type, params)) = + parse_prototype(&prototype, &proto_re, ¶m_re, &imm_re) + { + intrinsics.push(ScalarIntrinsic { + q6_name, + builtin_name, + asm_syntax, + instr_type, + exec_slots, + return_type, + params, + arch_guard: current_guard.clone(), + }); + } + } + } + i = j + 1; + continue; + } + + i += 1; + } + + intrinsics +} + +/// Generate the module documentation +fn generate_module_doc() -> String { + r#"//! Hexagon scalar intrinsics +//! +//! This module provides intrinsics for scalar (non-HVX) Hexagon DSP operations, +//! including arithmetic, multiply, shift, saturate, compare, and floating-point +//! operations. +//! +//! [Hexagon V68 Programmer's Reference Manual](https://docs.qualcomm.com/doc/80-N2040-45) +//! +//! ## Naming Convention +//! +//! Function names preserve the original Q6 naming case because the convention +//! uses case to distinguish register types: +//! - `P` (uppercase) = 64-bit register pair (`Word64`) +//! - `p` (lowercase) = predicate register (`Byte`) +//! +//! For example, `Q6_P_and_PP` operates on 64-bit pairs while `Q6_p_and_pp` +//! operates on predicate registers. +//! +//! ## Architecture Versions +//! +//! Most scalar intrinsics are available on all Hexagon architectures. +//! Some intrinsics require specific architecture versions (v60, v62, v65, +//! v66, v67, v68, or v67+audio) and carry +//! `#[target_feature(enable = "v68")]` (or the appropriate version). +//! Enable these with `-C target-feature=+v68` or by setting the target CPU +//! via `-C target-cpu=hexagonv68`. +//! +//! Each version includes all features from previous versions. + +#![allow(non_snake_case)] + +#[cfg(test)] +use stdarch_test::assert_instr; +"# + .to_string() +} + +/// Generate the extern block with LLVM intrinsic declarations +fn generate_extern_block(intrinsics: &[ScalarIntrinsic]) -> String { + let mut output = String::new(); + + output.push_str("// LLVM intrinsic declarations for Hexagon scalar operations\n"); + output.push_str("#[allow(improper_ctypes)]\n"); + output.push_str("unsafe extern \"unadjusted\" {\n"); + + for info in intrinsics { + let link_name = info.llvm_link_name(); + let fn_name = info.extern_fn_name(); + + let params_str = if info.params.is_empty() { + String::new() + } else { + info.params + .iter() + .map(|(_, t, _)| format!("_: {}", t.to_rust_str())) + .collect::>() + .join(", ") + }; + + let return_str = if info.return_type == RustType::Unit { + String::new() + } else { + format!(" -> {}", info.return_type.to_rust_str()) + }; + + output.push_str(&format!( + " #[link_name = \"{}\"]\n fn {}({}){return_str};\n", + link_name, fn_name, params_str + )); + } + + output.push_str("}\n"); + output +} + +/// Generate wrapper functions for all intrinsics +fn generate_functions(intrinsics: &[ScalarIntrinsic]) -> String { + let mut output = String::new(); + + for info in intrinsics { + let rust_name = info.rust_fn_name(); + let extern_name = info.extern_fn_name(); + + // Collect immediate parameter info: (original_index, const_name, ImmediateInfo) + let imm_params: Vec<(usize, String, &ImmediateInfo)> = info + .params + .iter() + .enumerate() + .filter_map(|(i, (name, _, imm))| imm.as_ref().map(|im| (i, name.to_uppercase(), im))) + .collect(); + + // Doc comment + output.push_str(&format!("/// `{}`\n", info.asm_syntax)); + output.push_str("///\n"); + output.push_str(&format!("/// Instruction Type: {}\n", info.instr_type)); + output.push_str(&format!("/// Execution Slots: {}\n", info.exec_slots)); + if let Some(req) = info.arch_guard.requires_doc() { + output.push_str(&format!("/// {}\n", req)); + } + + // Attributes + if let Some(tf_attr) = info.arch_guard.target_feature_attr() { + output.push_str("#[inline]\n"); // https://github.com/rust-lang/rust/issues/145574 + output.push_str(&format!("{}\n", tf_attr)); + } else { + output.push_str("#[inline(always)]\n"); + } + + // Immediate parameters become const generics but are passed as positional + // arguments at the call site: Q6_R_add_RI(rs, 42) rather than Q6_R_add_RI::<42>(rs). + // This matches the assembly syntax where the immediate is an operand. + if !imm_params.is_empty() { + let indices: Vec = imm_params.iter().map(|(i, _, _)| i.to_string()).collect(); + output.push_str(&format!( + "#[rustc_legacy_const_generics({})]\n", + indices.join(", ") + )); + } + + if let Some(instr) = extract_instr_name(&info.asm_syntax) { + if imm_params.is_empty() { + output.push_str(&format!("#[cfg_attr(test, assert_instr({}))]\n", instr)); + } else { + // Provide default values for const generics in assert_instr + let defaults: Vec = imm_params + .iter() + .map(|(_, name, _)| format!("{} = 0", name)) + .collect(); + output.push_str(&format!( + "#[cfg_attr(test, assert_instr({}, {}))]\n", + instr, + defaults.join(", ") + )); + } + } + + output.push_str(&format!( + "#[unstable(feature = \"stdarch_hexagon\", issue = \"{}\")]\n", + TRACKING_ISSUE + )); + + // Function signature: regular params exclude immediates, const generics added + let regular_params_str = info + .params + .iter() + .filter(|(_, _, imm)| imm.is_none()) + .map(|(name, ty, _)| format!("{}: {}", name, ty.to_rust_str())) + .collect::>() + .join(", "); + + let return_str = if info.return_type == RustType::Unit { + String::new() + } else { + format!(" -> {}", info.return_type.to_rust_str()) + }; + + if imm_params.is_empty() { + output.push_str(&format!( + "pub unsafe fn {}({}){} {{\n", + rust_name, regular_params_str, return_str + )); + } else { + let const_generics: Vec = imm_params + .iter() + .map(|(_, name, imm)| { + let ty = if imm.signed { "i32" } else { "u32" }; + format!("const {}: {}", name, ty) + }) + .collect(); + output.push_str(&format!( + "pub unsafe fn {}<{}>({}){} {{\n", + rust_name, + const_generics.join(", "), + regular_params_str, + return_str + )); + } + + // Function body: static assertions then call + for (_, const_name, imm_info) in &imm_params { + if imm_info.signed { + output.push_str(&format!( + " static_assert_simm_bits!({}, {});\n", + const_name, imm_info.bits + )); + } else { + output.push_str(&format!( + " static_assert_uimm_bits!({}, {});\n", + const_name, imm_info.bits + )); + } + } + + // Call args: use original order, using const generic names for immediates. + // Unsigned const generics (u32) need a cast to i32 for the extern call. + let args_str = info + .params + .iter() + .map(|(name, _, imm)| match imm { + Some(info) if !info.signed => format!("{} as i32", name.to_uppercase()), + Some(_) => name.to_uppercase(), + None => name.clone(), + }) + .collect::>() + .join(", "); + + output.push_str(&format!(" {}({})\n", extern_name, args_str)); + output.push_str("}\n\n"); + } + + output +} + +/// Generate the complete scalar.rs file +fn generate_scalar_file(intrinsics: &[ScalarIntrinsic], output_path: &Path) -> Result<(), String> { + let mut output = + File::create(output_path).map_err(|e| format!("Failed to create output: {}", e))?; + + writeln!(output, "{}", GENERATED_MARKER).map_err(|e| e.to_string())?; + writeln!(output, "{}", generate_module_doc()).map_err(|e| e.to_string())?; + writeln!(output, "").map_err(|e| e.to_string())?; + writeln!(output, "{}", generate_extern_block(intrinsics)).map_err(|e| e.to_string())?; + writeln!(output, "{}", generate_functions(intrinsics)).map_err(|e| e.to_string())?; + + // Flush before running rustfmt + drop(output); + + // Run rustfmt on the generated file + let status = std::process::Command::new("rustfmt") + .arg(output_path) + .status() + .map_err(|e| format!("Failed to run rustfmt: {}", e))?; + + if !status.success() { + return Err("rustfmt failed".to_string()); + } + + Ok(()) +} + +/// Parse the scalar header in `crate_dir` and write `scalar.rs` into `out_dir`. +pub fn generate(crate_dir: &std::path::Path, out_dir: &std::path::Path) -> Result<(), String> { + let header_content = read_header(crate_dir)?; + let intrinsics = parse_header(&header_content); + std::fs::create_dir_all(out_dir).map_err(|e| e.to_string())?; + let scalar_path = out_dir.join("scalar.rs"); + generate_scalar_file(&intrinsics, &scalar_path)?; + Ok(()) +} diff --git a/library/stdarch/crates/stdarch-gen-loongarch/Cargo.toml b/library/stdarch/crates/stdarch-gen-loongarch/Cargo.toml index d3ac607c5576c..a9ddc123b3688 100644 --- a/library/stdarch/crates/stdarch-gen-loongarch/Cargo.toml +++ b/library/stdarch/crates/stdarch-gen-loongarch/Cargo.toml @@ -7,4 +7,5 @@ edition = "2024" # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html [dependencies] -rand = "0.8.5" +rand = "0.9.3" +stdarch-gen-common = { path = "../stdarch-gen-common" } diff --git a/library/stdarch/crates/stdarch-gen-loongarch/lasx.spec b/library/stdarch/crates/stdarch-gen-loongarch/lasx.spec index e3bdfcb5e9faa..9eff3d01fa1f3 100644 --- a/library/stdarch/crates/stdarch-gen-loongarch/lasx.spec +++ b/library/stdarch/crates/stdarch-gen-loongarch/lasx.spec @@ -4,81 +4,97 @@ // ``` /// lasx_xvsll_b +impl = portable name = lasx_xvsll_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvsll_h +impl = portable name = lasx_xvsll_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvsll_w +impl = portable name = lasx_xvsll_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvsll_d +impl = portable name = lasx_xvsll_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvslli_b +impl = portable name = lasx_xvslli_b asm-fmts = xd, xj, ui3 data-types = V32QI, V32QI, UQI /// lasx_xvslli_h +impl = portable name = lasx_xvslli_h asm-fmts = xd, xj, ui4 data-types = V16HI, V16HI, UQI /// lasx_xvslli_w +impl = portable name = lasx_xvslli_w asm-fmts = xd, xj, ui5 data-types = V8SI, V8SI, UQI /// lasx_xvslli_d +impl = portable name = lasx_xvslli_d asm-fmts = xd, xj, ui6 data-types = V4DI, V4DI, UQI /// lasx_xvsra_b +impl = portable name = lasx_xvsra_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvsra_h +impl = portable name = lasx_xvsra_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvsra_w +impl = portable name = lasx_xvsra_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvsra_d +impl = portable name = lasx_xvsra_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvsrai_b +impl = portable name = lasx_xvsrai_b asm-fmts = xd, xj, ui3 data-types = V32QI, V32QI, UQI /// lasx_xvsrai_h +impl = portable name = lasx_xvsrai_h asm-fmts = xd, xj, ui4 data-types = V16HI, V16HI, UQI /// lasx_xvsrai_w +impl = portable name = lasx_xvsrai_w asm-fmts = xd, xj, ui5 data-types = V8SI, V8SI, UQI /// lasx_xvsrai_d +impl = portable name = lasx_xvsrai_d asm-fmts = xd, xj, ui6 data-types = V4DI, V4DI, UQI @@ -124,41 +140,49 @@ asm-fmts = xd, xj, ui6 data-types = V4DI, V4DI, UQI /// lasx_xvsrl_b +impl = portable name = lasx_xvsrl_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvsrl_h +impl = portable name = lasx_xvsrl_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvsrl_w +impl = portable name = lasx_xvsrl_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvsrl_d +impl = portable name = lasx_xvsrl_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvsrli_b +impl = portable name = lasx_xvsrli_b asm-fmts = xd, xj, ui3 data-types = V32QI, V32QI, UQI /// lasx_xvsrli_h +impl = portable name = lasx_xvsrli_h asm-fmts = xd, xj, ui4 data-types = V16HI, V16HI, UQI /// lasx_xvsrli_w +impl = portable name = lasx_xvsrli_w asm-fmts = xd, xj, ui5 data-types = V8SI, V8SI, UQI /// lasx_xvsrli_d +impl = portable name = lasx_xvsrli_d asm-fmts = xd, xj, ui6 data-types = V4DI, V4DI, UQI @@ -204,21 +228,25 @@ asm-fmts = xd, xj, ui6 data-types = V4DI, V4DI, UQI /// lasx_xvbitclr_b +impl = portable name = lasx_xvbitclr_b asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI /// lasx_xvbitclr_h +impl = portable name = lasx_xvbitclr_h asm-fmts = xd, xj, xk data-types = UV16HI, UV16HI, UV16HI /// lasx_xvbitclr_w +impl = portable name = lasx_xvbitclr_w asm-fmts = xd, xj, xk data-types = UV8SI, UV8SI, UV8SI /// lasx_xvbitclr_d +impl = portable name = lasx_xvbitclr_d asm-fmts = xd, xj, xk data-types = UV4DI, UV4DI, UV4DI @@ -244,21 +272,25 @@ asm-fmts = xd, xj, ui6 data-types = UV4DI, UV4DI, UQI /// lasx_xvbitset_b +impl = portable name = lasx_xvbitset_b asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI /// lasx_xvbitset_h +impl = portable name = lasx_xvbitset_h asm-fmts = xd, xj, xk data-types = UV16HI, UV16HI, UV16HI /// lasx_xvbitset_w +impl = portable name = lasx_xvbitset_w asm-fmts = xd, xj, xk data-types = UV8SI, UV8SI, UV8SI /// lasx_xvbitset_d +impl = portable name = lasx_xvbitset_d asm-fmts = xd, xj, xk data-types = UV4DI, UV4DI, UV4DI @@ -284,21 +316,25 @@ asm-fmts = xd, xj, ui6 data-types = UV4DI, UV4DI, UQI /// lasx_xvbitrev_b +impl = portable name = lasx_xvbitrev_b asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI /// lasx_xvbitrev_h +impl = portable name = lasx_xvbitrev_h asm-fmts = xd, xj, xk data-types = UV16HI, UV16HI, UV16HI /// lasx_xvbitrev_w +impl = portable name = lasx_xvbitrev_w asm-fmts = xd, xj, xk data-types = UV8SI, UV8SI, UV8SI /// lasx_xvbitrev_d +impl = portable name = lasx_xvbitrev_d asm-fmts = xd, xj, xk data-types = UV4DI, UV4DI, UV4DI @@ -324,61 +360,73 @@ asm-fmts = xd, xj, ui6 data-types = UV4DI, UV4DI, UQI /// lasx_xvadd_b +impl = portable name = lasx_xvadd_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvadd_h +impl = portable name = lasx_xvadd_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvadd_w +impl = portable name = lasx_xvadd_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvadd_d +impl = portable name = lasx_xvadd_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvaddi_bu +impl = portable name = lasx_xvaddi_bu asm-fmts = xd, xj, ui5 data-types = V32QI, V32QI, UQI /// lasx_xvaddi_hu +impl = portable name = lasx_xvaddi_hu asm-fmts = xd, xj, ui5 data-types = V16HI, V16HI, UQI /// lasx_xvaddi_wu +impl = portable name = lasx_xvaddi_wu asm-fmts = xd, xj, ui5 data-types = V8SI, V8SI, UQI /// lasx_xvaddi_du +impl = portable name = lasx_xvaddi_du asm-fmts = xd, xj, ui5 data-types = V4DI, V4DI, UQI /// lasx_xvsub_b +impl = portable name = lasx_xvsub_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvsub_h +impl = portable name = lasx_xvsub_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvsub_w +impl = portable name = lasx_xvsub_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvsub_d +impl = portable name = lasx_xvsub_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI @@ -404,361 +452,433 @@ asm-fmts = xd, xj, ui5 data-types = V4DI, V4DI, UQI /// lasx_xvmax_b +impl = portable name = lasx_xvmax_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvmax_h +impl = portable name = lasx_xvmax_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvmax_w +impl = portable name = lasx_xvmax_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvmax_d +impl = portable name = lasx_xvmax_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvmaxi_b +impl = portable name = lasx_xvmaxi_b asm-fmts = xd, xj, si5 data-types = V32QI, V32QI, QI /// lasx_xvmaxi_h +impl = portable name = lasx_xvmaxi_h asm-fmts = xd, xj, si5 data-types = V16HI, V16HI, QI /// lasx_xvmaxi_w +impl = portable name = lasx_xvmaxi_w asm-fmts = xd, xj, si5 data-types = V8SI, V8SI, QI /// lasx_xvmaxi_d +impl = portable name = lasx_xvmaxi_d asm-fmts = xd, xj, si5 data-types = V4DI, V4DI, QI /// lasx_xvmax_bu +impl = portable name = lasx_xvmax_bu asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI /// lasx_xvmax_hu +impl = portable name = lasx_xvmax_hu asm-fmts = xd, xj, xk data-types = UV16HI, UV16HI, UV16HI /// lasx_xvmax_wu +impl = portable name = lasx_xvmax_wu asm-fmts = xd, xj, xk data-types = UV8SI, UV8SI, UV8SI /// lasx_xvmax_du +impl = portable name = lasx_xvmax_du asm-fmts = xd, xj, xk data-types = UV4DI, UV4DI, UV4DI /// lasx_xvmaxi_bu +impl = portable name = lasx_xvmaxi_bu asm-fmts = xd, xj, ui5 data-types = UV32QI, UV32QI, UQI /// lasx_xvmaxi_hu +impl = portable name = lasx_xvmaxi_hu asm-fmts = xd, xj, ui5 data-types = UV16HI, UV16HI, UQI /// lasx_xvmaxi_wu +impl = portable name = lasx_xvmaxi_wu asm-fmts = xd, xj, ui5 data-types = UV8SI, UV8SI, UQI /// lasx_xvmaxi_du +impl = portable name = lasx_xvmaxi_du asm-fmts = xd, xj, ui5 data-types = UV4DI, UV4DI, UQI /// lasx_xvmin_b +impl = portable name = lasx_xvmin_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvmin_h +impl = portable name = lasx_xvmin_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvmin_w +impl = portable name = lasx_xvmin_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvmin_d +impl = portable name = lasx_xvmin_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvmini_b +impl = portable name = lasx_xvmini_b asm-fmts = xd, xj, si5 data-types = V32QI, V32QI, QI /// lasx_xvmini_h +impl = portable name = lasx_xvmini_h asm-fmts = xd, xj, si5 data-types = V16HI, V16HI, QI /// lasx_xvmini_w +impl = portable name = lasx_xvmini_w asm-fmts = xd, xj, si5 data-types = V8SI, V8SI, QI /// lasx_xvmini_d +impl = portable name = lasx_xvmini_d asm-fmts = xd, xj, si5 data-types = V4DI, V4DI, QI /// lasx_xvmin_bu +impl = portable name = lasx_xvmin_bu asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI /// lasx_xvmin_hu +impl = portable name = lasx_xvmin_hu asm-fmts = xd, xj, xk data-types = UV16HI, UV16HI, UV16HI /// lasx_xvmin_wu +impl = portable name = lasx_xvmin_wu asm-fmts = xd, xj, xk data-types = UV8SI, UV8SI, UV8SI /// lasx_xvmin_du +impl = portable name = lasx_xvmin_du asm-fmts = xd, xj, xk data-types = UV4DI, UV4DI, UV4DI /// lasx_xvmini_bu +impl = portable name = lasx_xvmini_bu asm-fmts = xd, xj, ui5 data-types = UV32QI, UV32QI, UQI /// lasx_xvmini_hu +impl = portable name = lasx_xvmini_hu asm-fmts = xd, xj, ui5 data-types = UV16HI, UV16HI, UQI /// lasx_xvmini_wu +impl = portable name = lasx_xvmini_wu asm-fmts = xd, xj, ui5 data-types = UV8SI, UV8SI, UQI /// lasx_xvmini_du +impl = portable name = lasx_xvmini_du asm-fmts = xd, xj, ui5 data-types = UV4DI, UV4DI, UQI /// lasx_xvseq_b +impl = portable name = lasx_xvseq_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvseq_h +impl = portable name = lasx_xvseq_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvseq_w +impl = portable name = lasx_xvseq_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvseq_d +impl = portable name = lasx_xvseq_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvseqi_b +impl = portable name = lasx_xvseqi_b asm-fmts = xd, xj, si5 data-types = V32QI, V32QI, QI /// lasx_xvseqi_h +impl = portable name = lasx_xvseqi_h asm-fmts = xd, xj, si5 data-types = V16HI, V16HI, QI /// lasx_xvseqi_w +impl = portable name = lasx_xvseqi_w asm-fmts = xd, xj, si5 data-types = V8SI, V8SI, QI /// lasx_xvseqi_d +impl = portable name = lasx_xvseqi_d asm-fmts = xd, xj, si5 data-types = V4DI, V4DI, QI /// lasx_xvslt_b +impl = portable name = lasx_xvslt_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvslt_h +impl = portable name = lasx_xvslt_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvslt_w +impl = portable name = lasx_xvslt_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvslt_d +impl = portable name = lasx_xvslt_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvslti_b +impl = portable name = lasx_xvslti_b asm-fmts = xd, xj, si5 data-types = V32QI, V32QI, QI /// lasx_xvslti_h +impl = portable name = lasx_xvslti_h asm-fmts = xd, xj, si5 data-types = V16HI, V16HI, QI /// lasx_xvslti_w +impl = portable name = lasx_xvslti_w asm-fmts = xd, xj, si5 data-types = V8SI, V8SI, QI /// lasx_xvslti_d +impl = portable name = lasx_xvslti_d asm-fmts = xd, xj, si5 data-types = V4DI, V4DI, QI /// lasx_xvslt_bu +impl = portable name = lasx_xvslt_bu asm-fmts = xd, xj, xk data-types = V32QI, UV32QI, UV32QI /// lasx_xvslt_hu +impl = portable name = lasx_xvslt_hu asm-fmts = xd, xj, xk data-types = V16HI, UV16HI, UV16HI /// lasx_xvslt_wu +impl = portable name = lasx_xvslt_wu asm-fmts = xd, xj, xk data-types = V8SI, UV8SI, UV8SI /// lasx_xvslt_du +impl = portable name = lasx_xvslt_du asm-fmts = xd, xj, xk data-types = V4DI, UV4DI, UV4DI /// lasx_xvslti_bu +impl = portable name = lasx_xvslti_bu asm-fmts = xd, xj, ui5 data-types = V32QI, UV32QI, UQI /// lasx_xvslti_hu +impl = portable name = lasx_xvslti_hu asm-fmts = xd, xj, ui5 data-types = V16HI, UV16HI, UQI /// lasx_xvslti_wu +impl = portable name = lasx_xvslti_wu asm-fmts = xd, xj, ui5 data-types = V8SI, UV8SI, UQI /// lasx_xvslti_du +impl = portable name = lasx_xvslti_du asm-fmts = xd, xj, ui5 data-types = V4DI, UV4DI, UQI /// lasx_xvsle_b +impl = portable name = lasx_xvsle_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvsle_h +impl = portable name = lasx_xvsle_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvsle_w +impl = portable name = lasx_xvsle_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvsle_d +impl = portable name = lasx_xvsle_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvslei_b +impl = portable name = lasx_xvslei_b asm-fmts = xd, xj, si5 data-types = V32QI, V32QI, QI /// lasx_xvslei_h +impl = portable name = lasx_xvslei_h asm-fmts = xd, xj, si5 data-types = V16HI, V16HI, QI /// lasx_xvslei_w +impl = portable name = lasx_xvslei_w asm-fmts = xd, xj, si5 data-types = V8SI, V8SI, QI /// lasx_xvslei_d +impl = portable name = lasx_xvslei_d asm-fmts = xd, xj, si5 data-types = V4DI, V4DI, QI /// lasx_xvsle_bu +impl = portable name = lasx_xvsle_bu asm-fmts = xd, xj, xk data-types = V32QI, UV32QI, UV32QI /// lasx_xvsle_hu +impl = portable name = lasx_xvsle_hu asm-fmts = xd, xj, xk data-types = V16HI, UV16HI, UV16HI /// lasx_xvsle_wu +impl = portable name = lasx_xvsle_wu asm-fmts = xd, xj, xk data-types = V8SI, UV8SI, UV8SI /// lasx_xvsle_du +impl = portable name = lasx_xvsle_du asm-fmts = xd, xj, xk data-types = V4DI, UV4DI, UV4DI /// lasx_xvslei_bu +impl = portable name = lasx_xvslei_bu asm-fmts = xd, xj, ui5 data-types = V32QI, UV32QI, UQI /// lasx_xvslei_hu +impl = portable name = lasx_xvslei_hu asm-fmts = xd, xj, ui5 data-types = V16HI, UV16HI, UQI /// lasx_xvslei_wu +impl = portable name = lasx_xvslei_wu asm-fmts = xd, xj, ui5 data-types = V8SI, UV8SI, UQI /// lasx_xvslei_du +impl = portable name = lasx_xvslei_du asm-fmts = xd, xj, ui5 data-types = V4DI, UV4DI, UQI @@ -804,61 +924,73 @@ asm-fmts = xd, xj, ui6 data-types = UV4DI, UV4DI, UQI /// lasx_xvadda_b +impl = portable name = lasx_xvadda_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvadda_h +impl = portable name = lasx_xvadda_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvadda_w +impl = portable name = lasx_xvadda_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvadda_d +impl = portable name = lasx_xvadda_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvsadd_b +impl = portable name = lasx_xvsadd_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvsadd_h +impl = portable name = lasx_xvsadd_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvsadd_w +impl = portable name = lasx_xvsadd_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvsadd_d +impl = portable name = lasx_xvsadd_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvsadd_bu +impl = portable name = lasx_xvsadd_bu asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI /// lasx_xvsadd_hu +impl = portable name = lasx_xvsadd_hu asm-fmts = xd, xj, xk data-types = UV16HI, UV16HI, UV16HI /// lasx_xvsadd_wu +impl = portable name = lasx_xvsadd_wu asm-fmts = xd, xj, xk data-types = UV8SI, UV8SI, UV8SI /// lasx_xvsadd_du +impl = portable name = lasx_xvsadd_du asm-fmts = xd, xj, xk data-types = UV4DI, UV4DI, UV4DI @@ -944,181 +1076,217 @@ asm-fmts = xd, xj, xk data-types = UV4DI, UV4DI, UV4DI /// lasx_xvssub_b +impl = portable name = lasx_xvssub_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvssub_h +impl = portable name = lasx_xvssub_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvssub_w +impl = portable name = lasx_xvssub_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvssub_d +impl = portable name = lasx_xvssub_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvssub_bu +impl = portable name = lasx_xvssub_bu asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI /// lasx_xvssub_hu +impl = portable name = lasx_xvssub_hu asm-fmts = xd, xj, xk data-types = UV16HI, UV16HI, UV16HI /// lasx_xvssub_wu +impl = portable name = lasx_xvssub_wu asm-fmts = xd, xj, xk data-types = UV8SI, UV8SI, UV8SI /// lasx_xvssub_du +impl = portable name = lasx_xvssub_du asm-fmts = xd, xj, xk data-types = UV4DI, UV4DI, UV4DI /// lasx_xvabsd_b +impl = portable name = lasx_xvabsd_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvabsd_h +impl = portable name = lasx_xvabsd_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvabsd_w +impl = portable name = lasx_xvabsd_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvabsd_d +impl = portable name = lasx_xvabsd_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvabsd_bu +impl = portable name = lasx_xvabsd_bu asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI /// lasx_xvabsd_hu +impl = portable name = lasx_xvabsd_hu asm-fmts = xd, xj, xk data-types = UV16HI, UV16HI, UV16HI /// lasx_xvabsd_wu +impl = portable name = lasx_xvabsd_wu asm-fmts = xd, xj, xk data-types = UV8SI, UV8SI, UV8SI /// lasx_xvabsd_du +impl = portable name = lasx_xvabsd_du asm-fmts = xd, xj, xk data-types = UV4DI, UV4DI, UV4DI /// lasx_xvmul_b +impl = portable name = lasx_xvmul_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvmul_h +impl = portable name = lasx_xvmul_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvmul_w +impl = portable name = lasx_xvmul_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvmul_d +impl = portable name = lasx_xvmul_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvmadd_b +impl = portable name = lasx_xvmadd_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI, V32QI /// lasx_xvmadd_h +impl = portable name = lasx_xvmadd_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI, V16HI /// lasx_xvmadd_w +impl = portable name = lasx_xvmadd_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI, V8SI /// lasx_xvmadd_d +impl = portable name = lasx_xvmadd_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI, V4DI /// lasx_xvmsub_b +impl = portable name = lasx_xvmsub_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI, V32QI /// lasx_xvmsub_h +impl = portable name = lasx_xvmsub_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI, V16HI /// lasx_xvmsub_w +impl = portable name = lasx_xvmsub_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI, V8SI /// lasx_xvmsub_d +impl = portable name = lasx_xvmsub_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI, V4DI /// lasx_xvdiv_b +impl = portable name = lasx_xvdiv_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvdiv_h +impl = portable name = lasx_xvdiv_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvdiv_w +impl = portable name = lasx_xvdiv_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvdiv_d +impl = portable name = lasx_xvdiv_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvdiv_bu +impl = portable name = lasx_xvdiv_bu asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI /// lasx_xvdiv_hu +impl = portable name = lasx_xvdiv_hu asm-fmts = xd, xj, xk data-types = UV16HI, UV16HI, UV16HI /// lasx_xvdiv_wu +impl = portable name = lasx_xvdiv_wu asm-fmts = xd, xj, xk data-types = UV8SI, UV8SI, UV8SI /// lasx_xvdiv_du +impl = portable name = lasx_xvdiv_du asm-fmts = xd, xj, xk data-types = UV4DI, UV4DI, UV4DI @@ -1184,181 +1352,217 @@ asm-fmts = xd, xj, xk data-types = V4DI, UV8SI, UV8SI /// lasx_xvmod_b +impl = portable name = lasx_xvmod_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvmod_h +impl = portable name = lasx_xvmod_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvmod_w +impl = portable name = lasx_xvmod_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvmod_d +impl = portable name = lasx_xvmod_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvmod_bu +impl = portable name = lasx_xvmod_bu asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI /// lasx_xvmod_hu +impl = portable name = lasx_xvmod_hu asm-fmts = xd, xj, xk data-types = UV16HI, UV16HI, UV16HI /// lasx_xvmod_wu +impl = portable name = lasx_xvmod_wu asm-fmts = xd, xj, xk data-types = UV8SI, UV8SI, UV8SI /// lasx_xvmod_du +impl = portable name = lasx_xvmod_du asm-fmts = xd, xj, xk data-types = UV4DI, UV4DI, UV4DI /// lasx_xvrepl128vei_b +impl = portable name = lasx_xvrepl128vei_b asm-fmts = xd, xj, ui4 data-types = V32QI, V32QI, UQI /// lasx_xvrepl128vei_h +impl = portable name = lasx_xvrepl128vei_h asm-fmts = xd, xj, ui3 data-types = V16HI, V16HI, UQI /// lasx_xvrepl128vei_w +impl = portable name = lasx_xvrepl128vei_w asm-fmts = xd, xj, ui2 data-types = V8SI, V8SI, UQI /// lasx_xvrepl128vei_d +impl = portable name = lasx_xvrepl128vei_d asm-fmts = xd, xj, ui1 data-types = V4DI, V4DI, UQI /// lasx_xvpickev_b +impl = portable name = lasx_xvpickev_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvpickev_h +impl = portable name = lasx_xvpickev_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvpickev_w +impl = portable name = lasx_xvpickev_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvpickev_d +impl = portable name = lasx_xvpickev_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvpickod_b +impl = portable name = lasx_xvpickod_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvpickod_h +impl = portable name = lasx_xvpickod_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvpickod_w +impl = portable name = lasx_xvpickod_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvpickod_d +impl = portable name = lasx_xvpickod_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvilvh_b +impl = portable name = lasx_xvilvh_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvilvh_h +impl = portable name = lasx_xvilvh_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvilvh_w +impl = portable name = lasx_xvilvh_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvilvh_d +impl = portable name = lasx_xvilvh_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvilvl_b +impl = portable name = lasx_xvilvl_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvilvl_h +impl = portable name = lasx_xvilvl_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvilvl_w +impl = portable name = lasx_xvilvl_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvilvl_d +impl = portable name = lasx_xvilvl_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvpackev_b +impl = portable name = lasx_xvpackev_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvpackev_h +impl = portable name = lasx_xvpackev_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvpackev_w +impl = portable name = lasx_xvpackev_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvpackev_d +impl = portable name = lasx_xvpackev_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvpackod_b +impl = portable name = lasx_xvpackod_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvpackod_h +impl = portable name = lasx_xvpackod_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvpackod_w +impl = portable name = lasx_xvpackod_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvpackod_d +impl = portable name = lasx_xvpackod_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI @@ -1384,6 +1588,7 @@ asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI, V4DI /// lasx_xvand_v +impl = portable name = lasx_xvand_v asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI @@ -1394,6 +1599,7 @@ asm-fmts = xd, xj, ui8 data-types = UV32QI, UV32QI, UQI /// lasx_xvor_v +impl = portable name = lasx_xvor_v asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI @@ -1404,6 +1610,7 @@ asm-fmts = xd, xj, ui8 data-types = UV32QI, UV32QI, UQI /// lasx_xvnor_v +impl = portable name = lasx_xvnor_v asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI @@ -1414,6 +1621,7 @@ asm-fmts = xd, xj, ui8 data-types = UV32QI, UV32QI, UQI /// lasx_xvxor_v +impl = portable name = lasx_xvxor_v asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI @@ -1434,56 +1642,67 @@ asm-fmts = xd, xj, ui8 data-types = UV32QI, UV32QI, UV32QI, USI /// lasx_xvshuf4i_b +impl = portable name = lasx_xvshuf4i_b asm-fmts = xd, xj, ui8 data-types = V32QI, V32QI, USI /// lasx_xvshuf4i_h +impl = portable name = lasx_xvshuf4i_h asm-fmts = xd, xj, ui8 data-types = V16HI, V16HI, USI /// lasx_xvshuf4i_w +impl = portable name = lasx_xvshuf4i_w asm-fmts = xd, xj, ui8 data-types = V8SI, V8SI, USI /// lasx_xvreplgr2vr_b +impl = portable name = lasx_xvreplgr2vr_b asm-fmts = xd, rj data-types = V32QI, SI /// lasx_xvreplgr2vr_h +impl = portable name = lasx_xvreplgr2vr_h asm-fmts = xd, rj data-types = V16HI, SI /// lasx_xvreplgr2vr_w +impl = portable name = lasx_xvreplgr2vr_w asm-fmts = xd, rj data-types = V8SI, SI /// lasx_xvreplgr2vr_d +impl = portable name = lasx_xvreplgr2vr_d asm-fmts = xd, rj data-types = V4DI, DI /// lasx_xvpcnt_b +impl = portable name = lasx_xvpcnt_b asm-fmts = xd, xj data-types = V32QI, V32QI /// lasx_xvpcnt_h +impl = portable name = lasx_xvpcnt_h asm-fmts = xd, xj data-types = V16HI, V16HI /// lasx_xvpcnt_w +impl = portable name = lasx_xvpcnt_w asm-fmts = xd, xj data-types = V8SI, V8SI /// lasx_xvpcnt_d +impl = portable name = lasx_xvpcnt_d asm-fmts = xd, xj data-types = V4DI, V4DI @@ -1509,61 +1728,73 @@ asm-fmts = xd, xj data-types = V4DI, V4DI /// lasx_xvclz_b +impl = portable name = lasx_xvclz_b asm-fmts = xd, xj data-types = V32QI, V32QI /// lasx_xvclz_h +impl = portable name = lasx_xvclz_h asm-fmts = xd, xj data-types = V16HI, V16HI /// lasx_xvclz_w +impl = portable name = lasx_xvclz_w asm-fmts = xd, xj data-types = V8SI, V8SI /// lasx_xvclz_d +impl = portable name = lasx_xvclz_d asm-fmts = xd, xj data-types = V4DI, V4DI /// lasx_xvfadd_s +impl = portable name = lasx_xvfadd_s asm-fmts = xd, xj, xk data-types = V8SF, V8SF, V8SF /// lasx_xvfadd_d +impl = portable name = lasx_xvfadd_d asm-fmts = xd, xj, xk data-types = V4DF, V4DF, V4DF /// lasx_xvfsub_s +impl = portable name = lasx_xvfsub_s asm-fmts = xd, xj, xk data-types = V8SF, V8SF, V8SF /// lasx_xvfsub_d +impl = portable name = lasx_xvfsub_d asm-fmts = xd, xj, xk data-types = V4DF, V4DF, V4DF /// lasx_xvfmul_s +impl = portable name = lasx_xvfmul_s asm-fmts = xd, xj, xk data-types = V8SF, V8SF, V8SF /// lasx_xvfmul_d +impl = portable name = lasx_xvfmul_d asm-fmts = xd, xj, xk data-types = V4DF, V4DF, V4DF /// lasx_xvfdiv_s +impl = portable name = lasx_xvfdiv_s asm-fmts = xd, xj, xk data-types = V8SF, V8SF, V8SF /// lasx_xvfdiv_d +impl = portable name = lasx_xvfdiv_d asm-fmts = xd, xj, xk data-types = V4DF, V4DF, V4DF @@ -1629,21 +1860,25 @@ asm-fmts = xd, xj data-types = V4DI, V4DF /// lasx_xvfsqrt_s +impl = portable name = lasx_xvfsqrt_s asm-fmts = xd, xj data-types = V8SF, V8SF /// lasx_xvfsqrt_d +impl = portable name = lasx_xvfsqrt_d asm-fmts = xd, xj data-types = V4DF, V4DF /// lasx_xvfrecip_s +impl = portable name = lasx_xvfrecip_s asm-fmts = xd, xj data-types = V8SF, V8SF /// lasx_xvfrecip_d +impl = portable name = lasx_xvfrecip_d asm-fmts = xd, xj data-types = V4DF, V4DF @@ -1679,11 +1914,13 @@ asm-fmts = xd, xj data-types = V4DF, V4DF /// lasx_xvfrsqrt_s +impl = portable name = lasx_xvfrsqrt_s asm-fmts = xd, xj data-types = V8SF, V8SF /// lasx_xvfrsqrt_d +impl = portable name = lasx_xvfrsqrt_d asm-fmts = xd, xj data-types = V4DF, V4DF @@ -1804,66 +2041,79 @@ asm-fmts = xd, xj, ui8 data-types = V8SI, V8SI, V8SI, USI /// lasx_xvandn_v +impl = portable name = lasx_xvandn_v asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI /// lasx_xvneg_b +impl = portable name = lasx_xvneg_b asm-fmts = xd, xj data-types = V32QI, V32QI /// lasx_xvneg_h +impl = portable name = lasx_xvneg_h asm-fmts = xd, xj data-types = V16HI, V16HI /// lasx_xvneg_w +impl = portable name = lasx_xvneg_w asm-fmts = xd, xj data-types = V8SI, V8SI /// lasx_xvneg_d +impl = portable name = lasx_xvneg_d asm-fmts = xd, xj data-types = V4DI, V4DI /// lasx_xvmuh_b +impl = portable name = lasx_xvmuh_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvmuh_h +impl = portable name = lasx_xvmuh_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvmuh_w +impl = portable name = lasx_xvmuh_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvmuh_d +impl = portable name = lasx_xvmuh_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvmuh_bu +impl = portable name = lasx_xvmuh_bu asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI /// lasx_xvmuh_hu +impl = portable name = lasx_xvmuh_hu asm-fmts = xd, xj, xk data-types = UV16HI, UV16HI, UV16HI /// lasx_xvmuh_wu +impl = portable name = lasx_xvmuh_wu asm-fmts = xd, xj, xk data-types = UV8SI, UV8SI, UV8SI /// lasx_xvmuh_du +impl = portable name = lasx_xvmuh_du asm-fmts = xd, xj, xk data-types = UV4DI, UV4DI, UV4DI @@ -2074,11 +2324,13 @@ asm-fmts = xd, xj, ui8 data-types = V4DI, V4DI, V4DI, USI /// lasx_xvbsrl_v +impl = portable name = lasx_xvbsrl_v asm-fmts = xd, xj, ui5 data-types = V32QI, V32QI, UQI /// lasx_xvbsll_v +impl = portable name = lasx_xvbsll_v asm-fmts = xd, xj, ui5 data-types = V32QI, V32QI, UQI @@ -2144,41 +2396,49 @@ asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvfmadd_s +impl = portable name = lasx_xvfmadd_s asm-fmts = xd, xj, xk, xa data-types = V8SF, V8SF, V8SF, V8SF /// lasx_xvfmadd_d +impl = portable name = lasx_xvfmadd_d asm-fmts = xd, xj, xk, xa data-types = V4DF, V4DF, V4DF, V4DF /// lasx_xvfmsub_s +impl = portable name = lasx_xvfmsub_s asm-fmts = xd, xj, xk, xa data-types = V8SF, V8SF, V8SF, V8SF /// lasx_xvfmsub_d +impl = portable name = lasx_xvfmsub_d asm-fmts = xd, xj, xk, xa data-types = V4DF, V4DF, V4DF, V4DF /// lasx_xvfnmadd_s +impl = portable name = lasx_xvfnmadd_s asm-fmts = xd, xj, xk, xa data-types = V8SF, V8SF, V8SF, V8SF /// lasx_xvfnmadd_d +impl = portable name = lasx_xvfnmadd_d asm-fmts = xd, xj, xk, xa data-types = V4DF, V4DF, V4DF, V4DF /// lasx_xvfnmsub_s +impl = portable name = lasx_xvfnmsub_s asm-fmts = xd, xj, xk, xa data-types = V8SF, V8SF, V8SF, V8SF /// lasx_xvfnmsub_d +impl = portable name = lasx_xvfnmsub_d asm-fmts = xd, xj, xk, xa data-types = V4DF, V4DF, V4DF, V4DF @@ -2314,41 +2574,49 @@ asm-fmts = xd, xj data-types = V4DF, V4DF /// lasx_xvfrintrz_s +impl = portable name = lasx_xvfrintrz_s asm-fmts = xd, xj data-types = V8SF, V8SF /// lasx_xvfrintrz_d +impl = portable name = lasx_xvfrintrz_d asm-fmts = xd, xj data-types = V4DF, V4DF /// lasx_xvfrintrp_s +impl = portable name = lasx_xvfrintrp_s asm-fmts = xd, xj data-types = V8SF, V8SF /// lasx_xvfrintrp_d +impl = portable name = lasx_xvfrintrp_d asm-fmts = xd, xj data-types = V4DF, V4DF /// lasx_xvfrintrm_s +impl = portable name = lasx_xvfrintrm_s asm-fmts = xd, xj data-types = V8SF, V8SF /// lasx_xvfrintrm_d +impl = portable name = lasx_xvfrintrm_d asm-fmts = xd, xj data-types = V4DF, V4DF /// lasx_xvld +impl = portable name = lasx_xvld asm-fmts = xd, rj, si12 data-types = V32QI, CVPOINTER, SI /// lasx_xvst +impl = portable name = lasx_xvst asm-fmts = xd, rj, si12 data-types = VOID, V32QI, CVPOINTER, SI @@ -2424,21 +2692,25 @@ asm-fmts = xd, xj, xk data-types = V8SI, V4DI, V4DI /// lasx_xvorn_v +impl = portable name = lasx_xvorn_v asm-fmts = xd, xj, xk -data-types = V32QI, V32QI, V32QI +data-types = UV32QI, UV32QI, UV32QI /// lasx_xvldi +impl = portable name = lasx_xvldi asm-fmts = xd, i13 data-types = V4DI, HI /// lasx_xvldx +impl = portable name = lasx_xvldx asm-fmts = xd, rj, rk data-types = V32QI, CVPOINTER, DI /// lasx_xvstx +impl = portable name = lasx_xvstx asm-fmts = xd, rj, rk data-types = VOID, V32QI, CVPOINTER, DI @@ -2449,36 +2721,43 @@ asm-fmts = xd, xj data-types = UV4DI, UV4DI /// lasx_xvinsgr2vr_w +impl = portable name = lasx_xvinsgr2vr_w asm-fmts = xd, rj, ui3 data-types = V8SI, V8SI, SI, UQI /// lasx_xvinsgr2vr_d +impl = portable name = lasx_xvinsgr2vr_d asm-fmts = xd, rj, ui2 data-types = V4DI, V4DI, DI, UQI /// lasx_xvreplve0_b +impl = portable name = lasx_xvreplve0_b asm-fmts = xd, xj data-types = V32QI, V32QI /// lasx_xvreplve0_h +impl = portable name = lasx_xvreplve0_h asm-fmts = xd, xj data-types = V16HI, V16HI /// lasx_xvreplve0_w +impl = portable name = lasx_xvreplve0_w asm-fmts = xd, xj data-types = V8SI, V8SI /// lasx_xvreplve0_d +impl = portable name = lasx_xvreplve0_d asm-fmts = xd, xj data-types = V4DI, V4DI /// lasx_xvreplve0_q +impl = portable name = lasx_xvreplve0_q asm-fmts = xd, xj data-types = V32QI, V32QI @@ -2579,21 +2858,25 @@ asm-fmts = xd, rj, si9 data-types = V4DI, CVPOINTER, SI /// lasx_xvpickve2gr_w +impl = portable name = lasx_xvpickve2gr_w asm-fmts = rd, xj, ui3 data-types = SI, V8SI, UQI /// lasx_xvpickve2gr_wu +impl = portable name = lasx_xvpickve2gr_wu asm-fmts = rd, xj, ui3 data-types = USI, V8SI, UQI /// lasx_xvpickve2gr_d +impl = portable name = lasx_xvpickve2gr_d asm-fmts = rd, xj, ui2 data-types = DI, V4DI, UQI /// lasx_xvpickve2gr_du +impl = portable name = lasx_xvpickve2gr_du asm-fmts = rd, xj, ui2 data-types = UDI, V4DI, UQI @@ -3039,21 +3322,25 @@ asm-fmts = xd, xj, xk data-types = V16HI, V16HI, UV32QI, V32QI /// lasx_xvrotr_b +impl = portable name = lasx_xvrotr_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvrotr_h +impl = portable name = lasx_xvrotr_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvrotr_w +impl = portable name = lasx_xvrotr_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvrotr_d +impl = portable name = lasx_xvrotr_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI @@ -3139,21 +3426,25 @@ asm-fmts = xd, xj data-types = UV4DI, UV4DI /// lasx_xvrotri_b +impl = portable name = lasx_xvrotri_b asm-fmts = xd, xj, ui3 data-types = V32QI, V32QI, UQI /// lasx_xvrotri_h +impl = portable name = lasx_xvrotri_h asm-fmts = xd, xj, ui4 data-types = V16HI, V16HI, UQI /// lasx_xvrotri_w +impl = portable name = lasx_xvrotri_w asm-fmts = xd, xj, ui5 data-types = V8SI, V8SI, UQI /// lasx_xvrotri_d +impl = portable name = lasx_xvrotri_d asm-fmts = xd, xj, ui6 data-types = V4DI, V4DI, UQI @@ -3684,22 +3975,116 @@ asm-fmts = xd, xj, ui3 data-types = V8SF, V8SF, UQI /// lasx_xvrepli_b +impl = portable name = lasx_xvrepli_b asm-fmts = xd, si10 data-types = V32QI, HI /// lasx_xvrepli_d +impl = portable name = lasx_xvrepli_d asm-fmts = xd, si10 data-types = V4DI, HI /// lasx_xvrepli_h +impl = portable name = lasx_xvrepli_h asm-fmts = xd, si10 data-types = V16HI, HI /// lasx_xvrepli_w +impl = portable name = lasx_xvrepli_w asm-fmts = xd, si10 data-types = V8SI, HI +/// lasx_cast_128_s +name = lasx_cast_128_s +asm-fmts = xd, vj +data-types = V8SF, V4SF + +/// lasx_cast_128_d +name = lasx_cast_128_d +asm-fmts = xd, vj +data-types = V4DF, V2DF + +/// lasx_cast_128 +name = lasx_cast_128 +asm-fmts = xd, vj +data-types = V4DI, V2DI + +/// lasx_concat_128_s +name = lasx_concat_128_s +asm-fmts = xd, vj, vk +data-types = V8SF, V4SF, V4SF + +/// lasx_concat_128_d +name = lasx_concat_128_d +asm-fmts = xd, vj, vk +data-types = V4DF, V2DF, V2DF + +/// lasx_concat_128 +name = lasx_concat_128 +asm-fmts = xd, vj, vk +data-types = V4DI, V2DI, V2DI + +/// lasx_extract_128_lo_s +name = lasx_extract_128_lo_s +asm-fmts = vd, xj +data-types = V4SF, V8SF + +/// lasx_extract_128_hi_s +name = lasx_extract_128_hi_s +asm-fmts = vd, xj +data-types = V4SF, V8SF + +/// lasx_extract_128_lo_d +name = lasx_extract_128_lo_d +asm-fmts = vd, xj +data-types = V2DF, V4DF + +/// lasx_extract_128_hi_d +name = lasx_extract_128_hi_d +asm-fmts = vd, xj +data-types = V2DF, V4DF + +/// lasx_extract_128_lo +name = lasx_extract_128_lo +asm-fmts = vd, xj +data-types = V2DI, V4DI + +/// lasx_extract_128_hi +name = lasx_extract_128_hi +asm-fmts = vd, xj +data-types = V2DI, V4DI + +/// lasx_insert_128_lo_s +name = lasx_insert_128_lo_s +asm-fmts = xd, xj, vk +data-types = V8SF, V8SF, V4SF + +/// lasx_insert_128_hi_s +name = lasx_insert_128_hi_s +asm-fmts = xd, xj, vk +data-types = V8SF, V8SF, V4SF + +/// lasx_insert_128_lo_d +name = lasx_insert_128_lo_d +asm-fmts = xd, xj, vk +data-types = V4DF, V4DF, V2DF + +/// lasx_insert_128_hi_d +name = lasx_insert_128_hi_d +asm-fmts = xd, xj, vk +data-types = V4DF, V4DF, V2DF + +/// lasx_insert_128_lo +name = lasx_insert_128_lo +asm-fmts = xd, xj, vk +data-types = V4DI, V4DI, V2DI + +/// lasx_insert_128_hi +name = lasx_insert_128_hi +asm-fmts = xd, xj, vk +data-types = V4DI, V4DI, V2DI + diff --git a/library/stdarch/crates/stdarch-gen-loongarch/lasxintrin.h b/library/stdarch/crates/stdarch-gen-loongarch/lasxintrin.h index c525b6106b897..02bb97918d95d 100644 --- a/library/stdarch/crates/stdarch-gen-loongarch/lasxintrin.h +++ b/library/stdarch/crates/stdarch-gen-loongarch/lasxintrin.h @@ -1,10 +1,10 @@ /* - * https://gcc.gnu.org/git/?p=gcc.git;a=blob_plain;f=gcc/config/loongarch/lasxintrin.h;hb=61f1001f2f4ab9128e5eb6e9a4adbbb0f9f0bc75 + * https://gcc.gnu.org/git/?p=gcc.git;a=blob_plain;f=gcc/config/loongarch/lasxintrin.h;hb=c2013267642fea4a6e89b826940c8aa80a76089d */ /* LARCH Loongson ASX intrinsics include file. - Copyright (C) 2018-2024 Free Software Foundation, Inc. + Copyright (C) 2018-2025 Free Software Foundation, Inc. This file is part of GCC. @@ -27,6 +27,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see . */ +#include + #ifndef _GCC_LOONGSON_ASXINTRIN_H #define _GCC_LOONGSON_ASXINTRIN_H 1 @@ -3568,11 +3570,11 @@ __m256i __lasx_xvssrln_w_d (__m256i _1, __m256i _2) } /* Assembly instruction format: xd, xj, xk. */ -/* Data types in instruction templates: V32QI, V32QI, V32QI. */ +/* Data types in instruction templates: UV32QI, UV32QI, UV32QI. */ extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __m256i __lasx_xvorn_v (__m256i _1, __m256i _2) { - return (__m256i)__builtin_lasx_xvorn_v ((v32i8)_1, (v32i8)_2); + return (__m256i)__builtin_lasx_xvorn_v ((v32u8)_1, (v32u8)_2); } /* Assembly instruction format: xd, i13. */ @@ -5372,5 +5374,159 @@ __m256i __lasx_xvfcmp_sun_s (__m256 _1, __m256 _2) #define __lasx_xvrepli_w(/*si10*/ _1) \ ((__m256i)__builtin_lasx_xvrepli_w ((_1))) +#if defined (__loongarch_asx_sx_conv) +/* Add builtin interfaces for 128 and 256 vector conversions. + For the assembly instruction format of some functions of the following vector + conversion, it is not described exactly in accordance with the format of the + generated assembly instruction. + In the front end of the Rust language, different built-in functions are called + by analyzing the format of assembly instructions. The data types of instructions + are all defined based on the interfaces of the defined functions, in the + following order: output, input... . */ +/* Assembly instruction format: xd, vj. */ +/* Data types in instruction templates: V8SF, V4SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256 __lasx_cast_128_s (__m128 _1) +{ + return (__m256)__builtin_lasx_cast_128_s ((v4f32)_1); +} + +/* Assembly instruction format: xd, vj. */ +/* Data types in instruction templates: V4DF, V2DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256d __lasx_cast_128_d (__m128d _1) +{ + return (__m256d)__builtin_lasx_cast_128_d ((v2f64)_1); +} + +/* Assembly instruction format: xd, vj. */ +/* Data types in instruction templates: V4DI, V2DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256i __lasx_cast_128 (__m128i _1) +{ + return (__m256i)__builtin_lasx_cast_128 ((v2i64)_1); +} + +/* Assembly instruction format: xd, vj, vk. */ +/* Data types in instruction templates: V8SF, V4SF, V4SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256 __lasx_concat_128_s (__m128 _1, __m128 _2) +{ + return (__m256)__builtin_lasx_concat_128_s ((v4f32)_1, (v4f32)_2); +} + +/* Assembly instruction format: xd, vj, vk. */ +/* Data types in instruction templates: V4DF, V2DF, V2DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256d __lasx_concat_128_d (__m128d _1, __m128d _2) +{ + return (__m256d)__builtin_lasx_concat_128_d ((v2f64)_1, (v2f64)_2); +} + +/* Assembly instruction format: xd, vj, vk. */ +/* Data types in instruction templates: V4DI, V2DI, V2DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256i __lasx_concat_128 (__m128i _1, __m128i _2) +{ + return (__m256i)__builtin_lasx_concat_128 ((v2i64)_1, (v2i64)_2); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V4SF, V8SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128 __lasx_extract_128_lo_s (__m256 _1) +{ + return (__m128)__builtin_lasx_extract_128_lo_s ((v8f32)_1); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V4SF, V8SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128 __lasx_extract_128_hi_s (__m256 _1) +{ + return (__m128)__builtin_lasx_extract_128_hi_s ((v8f32)_1); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V2DF, V4DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128d __lasx_extract_128_lo_d (__m256d _1) +{ + return (__m128d)__builtin_lasx_extract_128_lo_d ((v4f64)_1); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V2DF, V4DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128d __lasx_extract_128_hi_d (__m256d _1) +{ + return (__m128d)__builtin_lasx_extract_128_hi_d ((v4f64)_1); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V2DI, V4DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128i __lasx_extract_128_lo (__m256i _1) +{ + return (__m128i)__builtin_lasx_extract_128_lo ((v4i64)_1); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V2DI, V4DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128i __lasx_extract_128_hi (__m256i _1) +{ + return (__m128i)__builtin_lasx_extract_128_hi ((v4i64)_1); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V8SF, V8SF, V4SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256 __lasx_insert_128_lo_s (__m256 _1, __m128 _2) +{ + return (__m256)__builtin_lasx_insert_128_lo_s ((v8f32)_1, (v4f32)_2); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V8SF, V8SF, V4SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256 __lasx_insert_128_hi_s (__m256 _1, __m128 _2) +{ + return (__m256)__builtin_lasx_insert_128_hi_s ((v8f32)_1, (v4f32)_2); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V4DF, V4DF, V2DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256d __lasx_insert_128_lo_d (__m256d _1, __m128d _2) +{ + return (__m256d)__builtin_lasx_insert_128_lo_d ((v4f64)_1, (v2f64)_2); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V4DF, V4DF, V2DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256d __lasx_insert_128_hi_d (__m256d _1, __m128d _2) +{ + return (__m256d)__builtin_lasx_insert_128_hi_d ((v4f64)_1, (v2f64)_2); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V4DI, V4DI, V2DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256i __lasx_insert_128_lo (__m256i _1, __m128i _2) +{ + return (__m256i)__builtin_lasx_insert_128_lo ((v4i64)_1, (v2i64)_2); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V4DI, V4DI, V2DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256i __lasx_insert_128_hi (__m256i _1, __m128i _2) +{ + return (__m256i)__builtin_lasx_insert_128_hi ((v4i64)_1, (v2i64)_2); +} + +#endif /* defined(__loongarch_asx_sx_conv). */ #endif /* defined(__loongarch_asx). */ #endif /* _GCC_LOONGSON_ASXINTRIN_H. */ diff --git a/library/stdarch/crates/stdarch-gen-loongarch/lsx.spec b/library/stdarch/crates/stdarch-gen-loongarch/lsx.spec index dc835770d566e..ba2554b0cf9ff 100644 --- a/library/stdarch/crates/stdarch-gen-loongarch/lsx.spec +++ b/library/stdarch/crates/stdarch-gen-loongarch/lsx.spec @@ -4,81 +4,97 @@ // ``` /// lsx_vsll_b +impl = portable name = lsx_vsll_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vsll_h +impl = portable name = lsx_vsll_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vsll_w +impl = portable name = lsx_vsll_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vsll_d +impl = portable name = lsx_vsll_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vslli_b +impl = portable name = lsx_vslli_b asm-fmts = vd, vj, ui3 data-types = V16QI, V16QI, UQI /// lsx_vslli_h +impl = portable name = lsx_vslli_h asm-fmts = vd, vj, ui4 data-types = V8HI, V8HI, UQI /// lsx_vslli_w +impl = portable name = lsx_vslli_w asm-fmts = vd, vj, ui5 data-types = V4SI, V4SI, UQI /// lsx_vslli_d +impl = portable name = lsx_vslli_d asm-fmts = vd, vj, ui6 data-types = V2DI, V2DI, UQI /// lsx_vsra_b +impl = portable name = lsx_vsra_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vsra_h +impl = portable name = lsx_vsra_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vsra_w +impl = portable name = lsx_vsra_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vsra_d +impl = portable name = lsx_vsra_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vsrai_b +impl = portable name = lsx_vsrai_b asm-fmts = vd, vj, ui3 data-types = V16QI, V16QI, UQI /// lsx_vsrai_h +impl = portable name = lsx_vsrai_h asm-fmts = vd, vj, ui4 data-types = V8HI, V8HI, UQI /// lsx_vsrai_w +impl = portable name = lsx_vsrai_w asm-fmts = vd, vj, ui5 data-types = V4SI, V4SI, UQI /// lsx_vsrai_d +impl = portable name = lsx_vsrai_d asm-fmts = vd, vj, ui6 data-types = V2DI, V2DI, UQI @@ -124,41 +140,49 @@ asm-fmts = vd, vj, ui6 data-types = V2DI, V2DI, UQI /// lsx_vsrl_b +impl = portable name = lsx_vsrl_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vsrl_h +impl = portable name = lsx_vsrl_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vsrl_w +impl = portable name = lsx_vsrl_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vsrl_d +impl = portable name = lsx_vsrl_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vsrli_b +impl = portable name = lsx_vsrli_b asm-fmts = vd, vj, ui3 data-types = V16QI, V16QI, UQI /// lsx_vsrli_h +impl = portable name = lsx_vsrli_h asm-fmts = vd, vj, ui4 data-types = V8HI, V8HI, UQI /// lsx_vsrli_w +impl = portable name = lsx_vsrli_w asm-fmts = vd, vj, ui5 data-types = V4SI, V4SI, UQI /// lsx_vsrli_d +impl = portable name = lsx_vsrli_d asm-fmts = vd, vj, ui6 data-types = V2DI, V2DI, UQI @@ -204,21 +228,25 @@ asm-fmts = vd, vj, ui6 data-types = V2DI, V2DI, UQI /// lsx_vbitclr_b +impl = portable name = lsx_vbitclr_b asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI /// lsx_vbitclr_h +impl = portable name = lsx_vbitclr_h asm-fmts = vd, vj, vk data-types = UV8HI, UV8HI, UV8HI /// lsx_vbitclr_w +impl = portable name = lsx_vbitclr_w asm-fmts = vd, vj, vk data-types = UV4SI, UV4SI, UV4SI /// lsx_vbitclr_d +impl = portable name = lsx_vbitclr_d asm-fmts = vd, vj, vk data-types = UV2DI, UV2DI, UV2DI @@ -244,21 +272,25 @@ asm-fmts = vd, vj, ui6 data-types = UV2DI, UV2DI, UQI /// lsx_vbitset_b +impl = portable name = lsx_vbitset_b asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI /// lsx_vbitset_h +impl = portable name = lsx_vbitset_h asm-fmts = vd, vj, vk data-types = UV8HI, UV8HI, UV8HI /// lsx_vbitset_w +impl = portable name = lsx_vbitset_w asm-fmts = vd, vj, vk data-types = UV4SI, UV4SI, UV4SI /// lsx_vbitset_d +impl = portable name = lsx_vbitset_d asm-fmts = vd, vj, vk data-types = UV2DI, UV2DI, UV2DI @@ -284,21 +316,25 @@ asm-fmts = vd, vj, ui6 data-types = UV2DI, UV2DI, UQI /// lsx_vbitrev_b +impl = portable name = lsx_vbitrev_b asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI /// lsx_vbitrev_h +impl = portable name = lsx_vbitrev_h asm-fmts = vd, vj, vk data-types = UV8HI, UV8HI, UV8HI /// lsx_vbitrev_w +impl = portable name = lsx_vbitrev_w asm-fmts = vd, vj, vk data-types = UV4SI, UV4SI, UV4SI /// lsx_vbitrev_d +impl = portable name = lsx_vbitrev_d asm-fmts = vd, vj, vk data-types = UV2DI, UV2DI, UV2DI @@ -324,61 +360,73 @@ asm-fmts = vd, vj, ui6 data-types = UV2DI, UV2DI, UQI /// lsx_vadd_b +impl = portable name = lsx_vadd_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vadd_h +impl = portable name = lsx_vadd_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vadd_w +impl = portable name = lsx_vadd_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vadd_d +impl = portable name = lsx_vadd_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vaddi_bu +impl = portable name = lsx_vaddi_bu asm-fmts = vd, vj, ui5 data-types = V16QI, V16QI, UQI /// lsx_vaddi_hu +impl = portable name = lsx_vaddi_hu asm-fmts = vd, vj, ui5 data-types = V8HI, V8HI, UQI /// lsx_vaddi_wu +impl = portable name = lsx_vaddi_wu asm-fmts = vd, vj, ui5 data-types = V4SI, V4SI, UQI /// lsx_vaddi_du +impl = portable name = lsx_vaddi_du asm-fmts = vd, vj, ui5 data-types = V2DI, V2DI, UQI /// lsx_vsub_b +impl = portable name = lsx_vsub_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vsub_h +impl = portable name = lsx_vsub_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vsub_w +impl = portable name = lsx_vsub_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vsub_d +impl = portable name = lsx_vsub_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI @@ -404,361 +452,433 @@ asm-fmts = vd, vj, ui5 data-types = V2DI, V2DI, UQI /// lsx_vmax_b +impl = portable name = lsx_vmax_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vmax_h +impl = portable name = lsx_vmax_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vmax_w +impl = portable name = lsx_vmax_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vmax_d +impl = portable name = lsx_vmax_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vmaxi_b +impl = portable name = lsx_vmaxi_b asm-fmts = vd, vj, si5 data-types = V16QI, V16QI, QI /// lsx_vmaxi_h +impl = portable name = lsx_vmaxi_h asm-fmts = vd, vj, si5 data-types = V8HI, V8HI, QI /// lsx_vmaxi_w +impl = portable name = lsx_vmaxi_w asm-fmts = vd, vj, si5 data-types = V4SI, V4SI, QI /// lsx_vmaxi_d +impl = portable name = lsx_vmaxi_d asm-fmts = vd, vj, si5 data-types = V2DI, V2DI, QI /// lsx_vmax_bu +impl = portable name = lsx_vmax_bu asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI /// lsx_vmax_hu +impl = portable name = lsx_vmax_hu asm-fmts = vd, vj, vk data-types = UV8HI, UV8HI, UV8HI /// lsx_vmax_wu +impl = portable name = lsx_vmax_wu asm-fmts = vd, vj, vk data-types = UV4SI, UV4SI, UV4SI /// lsx_vmax_du +impl = portable name = lsx_vmax_du asm-fmts = vd, vj, vk data-types = UV2DI, UV2DI, UV2DI /// lsx_vmaxi_bu +impl = portable name = lsx_vmaxi_bu asm-fmts = vd, vj, ui5 data-types = UV16QI, UV16QI, UQI /// lsx_vmaxi_hu +impl = portable name = lsx_vmaxi_hu asm-fmts = vd, vj, ui5 data-types = UV8HI, UV8HI, UQI /// lsx_vmaxi_wu +impl = portable name = lsx_vmaxi_wu asm-fmts = vd, vj, ui5 data-types = UV4SI, UV4SI, UQI /// lsx_vmaxi_du +impl = portable name = lsx_vmaxi_du asm-fmts = vd, vj, ui5 data-types = UV2DI, UV2DI, UQI /// lsx_vmin_b +impl = portable name = lsx_vmin_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vmin_h +impl = portable name = lsx_vmin_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vmin_w +impl = portable name = lsx_vmin_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vmin_d +impl = portable name = lsx_vmin_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vmini_b +impl = portable name = lsx_vmini_b asm-fmts = vd, vj, si5 data-types = V16QI, V16QI, QI /// lsx_vmini_h +impl = portable name = lsx_vmini_h asm-fmts = vd, vj, si5 data-types = V8HI, V8HI, QI /// lsx_vmini_w +impl = portable name = lsx_vmini_w asm-fmts = vd, vj, si5 data-types = V4SI, V4SI, QI /// lsx_vmini_d +impl = portable name = lsx_vmini_d asm-fmts = vd, vj, si5 data-types = V2DI, V2DI, QI /// lsx_vmin_bu +impl = portable name = lsx_vmin_bu asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI /// lsx_vmin_hu +impl = portable name = lsx_vmin_hu asm-fmts = vd, vj, vk data-types = UV8HI, UV8HI, UV8HI /// lsx_vmin_wu +impl = portable name = lsx_vmin_wu asm-fmts = vd, vj, vk data-types = UV4SI, UV4SI, UV4SI /// lsx_vmin_du +impl = portable name = lsx_vmin_du asm-fmts = vd, vj, vk data-types = UV2DI, UV2DI, UV2DI /// lsx_vmini_bu +impl = portable name = lsx_vmini_bu asm-fmts = vd, vj, ui5 data-types = UV16QI, UV16QI, UQI /// lsx_vmini_hu +impl = portable name = lsx_vmini_hu asm-fmts = vd, vj, ui5 data-types = UV8HI, UV8HI, UQI /// lsx_vmini_wu +impl = portable name = lsx_vmini_wu asm-fmts = vd, vj, ui5 data-types = UV4SI, UV4SI, UQI /// lsx_vmini_du +impl = portable name = lsx_vmini_du asm-fmts = vd, vj, ui5 data-types = UV2DI, UV2DI, UQI /// lsx_vseq_b +impl = portable name = lsx_vseq_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vseq_h +impl = portable name = lsx_vseq_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vseq_w +impl = portable name = lsx_vseq_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vseq_d +impl = portable name = lsx_vseq_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vseqi_b +impl = portable name = lsx_vseqi_b asm-fmts = vd, vj, si5 data-types = V16QI, V16QI, QI /// lsx_vseqi_h +impl = portable name = lsx_vseqi_h asm-fmts = vd, vj, si5 data-types = V8HI, V8HI, QI /// lsx_vseqi_w +impl = portable name = lsx_vseqi_w asm-fmts = vd, vj, si5 data-types = V4SI, V4SI, QI /// lsx_vseqi_d +impl = portable name = lsx_vseqi_d asm-fmts = vd, vj, si5 data-types = V2DI, V2DI, QI /// lsx_vslti_b +impl = portable name = lsx_vslti_b asm-fmts = vd, vj, si5 data-types = V16QI, V16QI, QI /// lsx_vslt_b +impl = portable name = lsx_vslt_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vslt_h +impl = portable name = lsx_vslt_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vslt_w +impl = portable name = lsx_vslt_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vslt_d +impl = portable name = lsx_vslt_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vslti_h +impl = portable name = lsx_vslti_h asm-fmts = vd, vj, si5 data-types = V8HI, V8HI, QI /// lsx_vslti_w +impl = portable name = lsx_vslti_w asm-fmts = vd, vj, si5 data-types = V4SI, V4SI, QI /// lsx_vslti_d +impl = portable name = lsx_vslti_d asm-fmts = vd, vj, si5 data-types = V2DI, V2DI, QI /// lsx_vslt_bu +impl = portable name = lsx_vslt_bu asm-fmts = vd, vj, vk data-types = V16QI, UV16QI, UV16QI /// lsx_vslt_hu +impl = portable name = lsx_vslt_hu asm-fmts = vd, vj, vk data-types = V8HI, UV8HI, UV8HI /// lsx_vslt_wu +impl = portable name = lsx_vslt_wu asm-fmts = vd, vj, vk data-types = V4SI, UV4SI, UV4SI /// lsx_vslt_du +impl = portable name = lsx_vslt_du asm-fmts = vd, vj, vk data-types = V2DI, UV2DI, UV2DI /// lsx_vslti_bu +impl = portable name = lsx_vslti_bu asm-fmts = vd, vj, ui5 data-types = V16QI, UV16QI, UQI /// lsx_vslti_hu +impl = portable name = lsx_vslti_hu asm-fmts = vd, vj, ui5 data-types = V8HI, UV8HI, UQI /// lsx_vslti_wu +impl = portable name = lsx_vslti_wu asm-fmts = vd, vj, ui5 data-types = V4SI, UV4SI, UQI /// lsx_vslti_du +impl = portable name = lsx_vslti_du asm-fmts = vd, vj, ui5 data-types = V2DI, UV2DI, UQI /// lsx_vsle_b +impl = portable name = lsx_vsle_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vsle_h +impl = portable name = lsx_vsle_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vsle_w +impl = portable name = lsx_vsle_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vsle_d +impl = portable name = lsx_vsle_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vslei_b +impl = portable name = lsx_vslei_b asm-fmts = vd, vj, si5 data-types = V16QI, V16QI, QI /// lsx_vslei_h +impl = portable name = lsx_vslei_h asm-fmts = vd, vj, si5 data-types = V8HI, V8HI, QI /// lsx_vslei_w +impl = portable name = lsx_vslei_w asm-fmts = vd, vj, si5 data-types = V4SI, V4SI, QI /// lsx_vslei_d +impl = portable name = lsx_vslei_d asm-fmts = vd, vj, si5 data-types = V2DI, V2DI, QI /// lsx_vsle_bu +impl = portable name = lsx_vsle_bu asm-fmts = vd, vj, vk data-types = V16QI, UV16QI, UV16QI /// lsx_vsle_hu +impl = portable name = lsx_vsle_hu asm-fmts = vd, vj, vk data-types = V8HI, UV8HI, UV8HI /// lsx_vsle_wu +impl = portable name = lsx_vsle_wu asm-fmts = vd, vj, vk data-types = V4SI, UV4SI, UV4SI /// lsx_vsle_du +impl = portable name = lsx_vsle_du asm-fmts = vd, vj, vk data-types = V2DI, UV2DI, UV2DI /// lsx_vslei_bu +impl = portable name = lsx_vslei_bu asm-fmts = vd, vj, ui5 data-types = V16QI, UV16QI, UQI /// lsx_vslei_hu +impl = portable name = lsx_vslei_hu asm-fmts = vd, vj, ui5 data-types = V8HI, UV8HI, UQI /// lsx_vslei_wu +impl = portable name = lsx_vslei_wu asm-fmts = vd, vj, ui5 data-types = V4SI, UV4SI, UQI /// lsx_vslei_du +impl = portable name = lsx_vslei_du asm-fmts = vd, vj, ui5 data-types = V2DI, UV2DI, UQI @@ -804,61 +924,73 @@ asm-fmts = vd, vj, ui6 data-types = UV2DI, UV2DI, UQI /// lsx_vadda_b +impl = portable name = lsx_vadda_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vadda_h +impl = portable name = lsx_vadda_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vadda_w +impl = portable name = lsx_vadda_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vadda_d +impl = portable name = lsx_vadda_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vsadd_b +impl = portable name = lsx_vsadd_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vsadd_h +impl = portable name = lsx_vsadd_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vsadd_w +impl = portable name = lsx_vsadd_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vsadd_d +impl = portable name = lsx_vsadd_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vsadd_bu +impl = portable name = lsx_vsadd_bu asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI /// lsx_vsadd_hu +impl = portable name = lsx_vsadd_hu asm-fmts = vd, vj, vk data-types = UV8HI, UV8HI, UV8HI /// lsx_vsadd_wu +impl = portable name = lsx_vsadd_wu asm-fmts = vd, vj, vk data-types = UV4SI, UV4SI, UV4SI /// lsx_vsadd_du +impl = portable name = lsx_vsadd_du asm-fmts = vd, vj, vk data-types = UV2DI, UV2DI, UV2DI @@ -944,181 +1076,217 @@ asm-fmts = vd, vj, vk data-types = UV2DI, UV2DI, UV2DI /// lsx_vssub_b +impl = portable name = lsx_vssub_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vssub_h +impl = portable name = lsx_vssub_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vssub_w +impl = portable name = lsx_vssub_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vssub_d +impl = portable name = lsx_vssub_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vssub_bu +impl = portable name = lsx_vssub_bu asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI /// lsx_vssub_hu +impl = portable name = lsx_vssub_hu asm-fmts = vd, vj, vk data-types = UV8HI, UV8HI, UV8HI /// lsx_vssub_wu +impl = portable name = lsx_vssub_wu asm-fmts = vd, vj, vk data-types = UV4SI, UV4SI, UV4SI /// lsx_vssub_du +impl = portable name = lsx_vssub_du asm-fmts = vd, vj, vk data-types = UV2DI, UV2DI, UV2DI /// lsx_vabsd_b +impl = portable name = lsx_vabsd_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vabsd_h +impl = portable name = lsx_vabsd_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vabsd_w +impl = portable name = lsx_vabsd_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vabsd_d +impl = portable name = lsx_vabsd_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vabsd_bu +impl = portable name = lsx_vabsd_bu asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI /// lsx_vabsd_hu +impl = portable name = lsx_vabsd_hu asm-fmts = vd, vj, vk data-types = UV8HI, UV8HI, UV8HI /// lsx_vabsd_wu +impl = portable name = lsx_vabsd_wu asm-fmts = vd, vj, vk data-types = UV4SI, UV4SI, UV4SI /// lsx_vabsd_du +impl = portable name = lsx_vabsd_du asm-fmts = vd, vj, vk data-types = UV2DI, UV2DI, UV2DI /// lsx_vmul_b +impl = portable name = lsx_vmul_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vmul_h +impl = portable name = lsx_vmul_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vmul_w +impl = portable name = lsx_vmul_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vmul_d +impl = portable name = lsx_vmul_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vmadd_b +impl = portable name = lsx_vmadd_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI, V16QI /// lsx_vmadd_h +impl = portable name = lsx_vmadd_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI, V8HI /// lsx_vmadd_w +impl = portable name = lsx_vmadd_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI, V4SI /// lsx_vmadd_d +impl = portable name = lsx_vmadd_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI, V2DI /// lsx_vmsub_b +impl = portable name = lsx_vmsub_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI, V16QI /// lsx_vmsub_h +impl = portable name = lsx_vmsub_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI, V8HI /// lsx_vmsub_w +impl = portable name = lsx_vmsub_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI, V4SI /// lsx_vmsub_d +impl = portable name = lsx_vmsub_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI, V2DI /// lsx_vdiv_b +impl = portable name = lsx_vdiv_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vdiv_h +impl = portable name = lsx_vdiv_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vdiv_w +impl = portable name = lsx_vdiv_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vdiv_d +impl = portable name = lsx_vdiv_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vdiv_bu +impl = portable name = lsx_vdiv_bu asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI /// lsx_vdiv_hu +impl = portable name = lsx_vdiv_hu asm-fmts = vd, vj, vk data-types = UV8HI, UV8HI, UV8HI /// lsx_vdiv_wu +impl = portable name = lsx_vdiv_wu asm-fmts = vd, vj, vk data-types = UV4SI, UV4SI, UV4SI /// lsx_vdiv_du +impl = portable name = lsx_vdiv_du asm-fmts = vd, vj, vk data-types = UV2DI, UV2DI, UV2DI @@ -1184,41 +1352,49 @@ asm-fmts = vd, vj, vk data-types = V2DI, UV4SI, UV4SI /// lsx_vmod_b +impl = portable name = lsx_vmod_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vmod_h +impl = portable name = lsx_vmod_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vmod_w +impl = portable name = lsx_vmod_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vmod_d +impl = portable name = lsx_vmod_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vmod_bu +impl = portable name = lsx_vmod_bu asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI /// lsx_vmod_hu +impl = portable name = lsx_vmod_hu asm-fmts = vd, vj, vk data-types = UV8HI, UV8HI, UV8HI /// lsx_vmod_wu +impl = portable name = lsx_vmod_wu asm-fmts = vd, vj, vk data-types = UV4SI, UV4SI, UV4SI /// lsx_vmod_du +impl = portable name = lsx_vmod_du asm-fmts = vd, vj, vk data-types = UV2DI, UV2DI, UV2DI @@ -1244,141 +1420,169 @@ asm-fmts = vd, vj, rk data-types = V2DI, V2DI, SI /// lsx_vreplvei_b +impl = portable name = lsx_vreplvei_b asm-fmts = vd, vj, ui4 data-types = V16QI, V16QI, UQI /// lsx_vreplvei_h +impl = portable name = lsx_vreplvei_h asm-fmts = vd, vj, ui3 data-types = V8HI, V8HI, UQI /// lsx_vreplvei_w +impl = portable name = lsx_vreplvei_w asm-fmts = vd, vj, ui2 data-types = V4SI, V4SI, UQI /// lsx_vreplvei_d +impl = portable name = lsx_vreplvei_d asm-fmts = vd, vj, ui1 data-types = V2DI, V2DI, UQI /// lsx_vpickev_b +impl = portable name = lsx_vpickev_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vpickev_h +impl = portable name = lsx_vpickev_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vpickev_w +impl = portable name = lsx_vpickev_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vpickev_d +impl = portable name = lsx_vpickev_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vpickod_b +impl = portable name = lsx_vpickod_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vpickod_h +impl = portable name = lsx_vpickod_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vpickod_w +impl = portable name = lsx_vpickod_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vpickod_d +impl = portable name = lsx_vpickod_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vilvh_b +impl = portable name = lsx_vilvh_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vilvh_h +impl = portable name = lsx_vilvh_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vilvh_w +impl = portable name = lsx_vilvh_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vilvh_d +impl = portable name = lsx_vilvh_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vilvl_b +impl = portable name = lsx_vilvl_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vilvl_h +impl = portable name = lsx_vilvl_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vilvl_w +impl = portable name = lsx_vilvl_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vilvl_d +impl = portable name = lsx_vilvl_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vpackev_b +impl = portable name = lsx_vpackev_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vpackev_h +impl = portable name = lsx_vpackev_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vpackev_w +impl = portable name = lsx_vpackev_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vpackev_d +impl = portable name = lsx_vpackev_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vpackod_b +impl = portable name = lsx_vpackod_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vpackod_h +impl = portable name = lsx_vpackod_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vpackod_w +impl = portable name = lsx_vpackod_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vpackod_d +impl = portable name = lsx_vpackod_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI @@ -1399,6 +1603,7 @@ asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI, V2DI /// lsx_vand_v +impl = portable name = lsx_vand_v asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI @@ -1409,6 +1614,7 @@ asm-fmts = vd, vj, ui8 data-types = UV16QI, UV16QI, UQI /// lsx_vor_v +impl = portable name = lsx_vor_v asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI @@ -1419,6 +1625,7 @@ asm-fmts = vd, vj, ui8 data-types = UV16QI, UV16QI, UQI /// lsx_vnor_v +impl = portable name = lsx_vnor_v asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI @@ -1429,6 +1636,7 @@ asm-fmts = vd, vj, ui8 data-types = UV16QI, UV16QI, UQI /// lsx_vxor_v +impl = portable name = lsx_vxor_v asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI @@ -1449,56 +1657,67 @@ asm-fmts = vd, vj, ui8 data-types = UV16QI, UV16QI, UV16QI, USI /// lsx_vshuf4i_b +impl = portable name = lsx_vshuf4i_b asm-fmts = vd, vj, ui8 data-types = V16QI, V16QI, USI /// lsx_vshuf4i_h +impl = portable name = lsx_vshuf4i_h asm-fmts = vd, vj, ui8 data-types = V8HI, V8HI, USI /// lsx_vshuf4i_w +impl = portable name = lsx_vshuf4i_w asm-fmts = vd, vj, ui8 data-types = V4SI, V4SI, USI /// lsx_vreplgr2vr_b +impl = portable name = lsx_vreplgr2vr_b asm-fmts = vd, rj data-types = V16QI, SI /// lsx_vreplgr2vr_h +impl = portable name = lsx_vreplgr2vr_h asm-fmts = vd, rj data-types = V8HI, SI /// lsx_vreplgr2vr_w +impl = portable name = lsx_vreplgr2vr_w asm-fmts = vd, rj data-types = V4SI, SI /// lsx_vreplgr2vr_d +impl = portable name = lsx_vreplgr2vr_d asm-fmts = vd, rj data-types = V2DI, DI /// lsx_vpcnt_b +impl = portable name = lsx_vpcnt_b asm-fmts = vd, vj data-types = V16QI, V16QI /// lsx_vpcnt_h +impl = portable name = lsx_vpcnt_h asm-fmts = vd, vj data-types = V8HI, V8HI /// lsx_vpcnt_w +impl = portable name = lsx_vpcnt_w asm-fmts = vd, vj data-types = V4SI, V4SI /// lsx_vpcnt_d +impl = portable name = lsx_vpcnt_d asm-fmts = vd, vj data-types = V2DI, V2DI @@ -1524,121 +1743,145 @@ asm-fmts = vd, vj data-types = V2DI, V2DI /// lsx_vclz_b +impl = portable name = lsx_vclz_b asm-fmts = vd, vj data-types = V16QI, V16QI /// lsx_vclz_h +impl = portable name = lsx_vclz_h asm-fmts = vd, vj data-types = V8HI, V8HI /// lsx_vclz_w +impl = portable name = lsx_vclz_w asm-fmts = vd, vj data-types = V4SI, V4SI /// lsx_vclz_d +impl = portable name = lsx_vclz_d asm-fmts = vd, vj data-types = V2DI, V2DI /// lsx_vpickve2gr_b +impl = portable name = lsx_vpickve2gr_b asm-fmts = rd, vj, ui4 data-types = SI, V16QI, UQI /// lsx_vpickve2gr_h +impl = portable name = lsx_vpickve2gr_h asm-fmts = rd, vj, ui3 data-types = SI, V8HI, UQI /// lsx_vpickve2gr_w +impl = portable name = lsx_vpickve2gr_w asm-fmts = rd, vj, ui2 data-types = SI, V4SI, UQI /// lsx_vpickve2gr_d +impl = portable name = lsx_vpickve2gr_d asm-fmts = rd, vj, ui1 data-types = DI, V2DI, UQI /// lsx_vpickve2gr_bu +impl = portable name = lsx_vpickve2gr_bu asm-fmts = rd, vj, ui4 data-types = USI, V16QI, UQI /// lsx_vpickve2gr_hu +impl = portable name = lsx_vpickve2gr_hu asm-fmts = rd, vj, ui3 data-types = USI, V8HI, UQI /// lsx_vpickve2gr_wu +impl = portable name = lsx_vpickve2gr_wu asm-fmts = rd, vj, ui2 data-types = USI, V4SI, UQI /// lsx_vpickve2gr_du +impl = portable name = lsx_vpickve2gr_du asm-fmts = rd, vj, ui1 data-types = UDI, V2DI, UQI /// lsx_vinsgr2vr_b +impl = portable name = lsx_vinsgr2vr_b asm-fmts = vd, rj, ui4 data-types = V16QI, V16QI, SI, UQI /// lsx_vinsgr2vr_h +impl = portable name = lsx_vinsgr2vr_h asm-fmts = vd, rj, ui3 data-types = V8HI, V8HI, SI, UQI /// lsx_vinsgr2vr_w +impl = portable name = lsx_vinsgr2vr_w asm-fmts = vd, rj, ui2 data-types = V4SI, V4SI, SI, UQI /// lsx_vinsgr2vr_d +impl = portable name = lsx_vinsgr2vr_d asm-fmts = vd, rj, ui1 data-types = V2DI, V2DI, DI, UQI /// lsx_vfadd_s +impl = portable name = lsx_vfadd_s asm-fmts = vd, vj, vk data-types = V4SF, V4SF, V4SF /// lsx_vfadd_d +impl = portable name = lsx_vfadd_d asm-fmts = vd, vj, vk data-types = V2DF, V2DF, V2DF /// lsx_vfsub_s +impl = portable name = lsx_vfsub_s asm-fmts = vd, vj, vk data-types = V4SF, V4SF, V4SF /// lsx_vfsub_d +impl = portable name = lsx_vfsub_d asm-fmts = vd, vj, vk data-types = V2DF, V2DF, V2DF /// lsx_vfmul_s +impl = portable name = lsx_vfmul_s asm-fmts = vd, vj, vk data-types = V4SF, V4SF, V4SF /// lsx_vfmul_d +impl = portable name = lsx_vfmul_d asm-fmts = vd, vj, vk data-types = V2DF, V2DF, V2DF /// lsx_vfdiv_s +impl = portable name = lsx_vfdiv_s asm-fmts = vd, vj, vk data-types = V4SF, V4SF, V4SF /// lsx_vfdiv_d +impl = portable name = lsx_vfdiv_d asm-fmts = vd, vj, vk data-types = V2DF, V2DF, V2DF @@ -1704,21 +1947,25 @@ asm-fmts = vd, vj data-types = V2DI, V2DF /// lsx_vfsqrt_s +impl = portable name = lsx_vfsqrt_s asm-fmts = vd, vj data-types = V4SF, V4SF /// lsx_vfsqrt_d +impl = portable name = lsx_vfsqrt_d asm-fmts = vd, vj data-types = V2DF, V2DF /// lsx_vfrecip_s +impl = portable name = lsx_vfrecip_s asm-fmts = vd, vj data-types = V4SF, V4SF /// lsx_vfrecip_d +impl = portable name = lsx_vfrecip_d asm-fmts = vd, vj data-types = V2DF, V2DF @@ -1754,11 +2001,13 @@ asm-fmts = vd, vj data-types = V2DF, V2DF /// lsx_vfrsqrt_s +impl = portable name = lsx_vfrsqrt_s asm-fmts = vd, vj data-types = V4SF, V4SF /// lsx_vfrsqrt_d +impl = portable name = lsx_vfrsqrt_d asm-fmts = vd, vj data-types = V2DF, V2DF @@ -1854,66 +2103,79 @@ asm-fmts = vd, vj data-types = V2DF, UV2DI /// lsx_vandn_v +impl = portable name = lsx_vandn_v asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI /// lsx_vneg_b +impl = portable name = lsx_vneg_b asm-fmts = vd, vj data-types = V16QI, V16QI /// lsx_vneg_h +impl = portable name = lsx_vneg_h asm-fmts = vd, vj data-types = V8HI, V8HI /// lsx_vneg_w +impl = portable name = lsx_vneg_w asm-fmts = vd, vj data-types = V4SI, V4SI /// lsx_vneg_d +impl = portable name = lsx_vneg_d asm-fmts = vd, vj data-types = V2DI, V2DI /// lsx_vmuh_b +impl = portable name = lsx_vmuh_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vmuh_h +impl = portable name = lsx_vmuh_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vmuh_w +impl = portable name = lsx_vmuh_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vmuh_d +impl = portable name = lsx_vmuh_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vmuh_bu +impl = portable name = lsx_vmuh_bu asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI /// lsx_vmuh_hu +impl = portable name = lsx_vmuh_hu asm-fmts = vd, vj, vk data-types = UV8HI, UV8HI, UV8HI /// lsx_vmuh_wu +impl = portable name = lsx_vmuh_wu asm-fmts = vd, vj, vk data-types = UV4SI, UV4SI, UV4SI /// lsx_vmuh_du +impl = portable name = lsx_vmuh_du asm-fmts = vd, vj, vk data-types = UV2DI, UV2DI, UV2DI @@ -2119,16 +2381,19 @@ asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI, V8HI /// lsx_vshuf4i_d +impl = portable name = lsx_vshuf4i_d asm-fmts = vd, vj, ui8 data-types = V2DI, V2DI, V2DI, USI /// lsx_vbsrl_v +impl = portable name = lsx_vbsrl_v asm-fmts = vd, vj, ui5 data-types = V16QI, V16QI, UQI /// lsx_vbsll_v +impl = portable name = lsx_vbsll_v asm-fmts = vd, vj, ui5 data-types = V16QI, V16QI, UQI @@ -2194,41 +2459,49 @@ asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vfmadd_s +impl = portable name = lsx_vfmadd_s asm-fmts = vd, vj, vk, va data-types = V4SF, V4SF, V4SF, V4SF /// lsx_vfmadd_d +impl = portable name = lsx_vfmadd_d asm-fmts = vd, vj, vk, va data-types = V2DF, V2DF, V2DF, V2DF /// lsx_vfmsub_s +impl = portable name = lsx_vfmsub_s asm-fmts = vd, vj, vk, va data-types = V4SF, V4SF, V4SF, V4SF /// lsx_vfmsub_d +impl = portable name = lsx_vfmsub_d asm-fmts = vd, vj, vk, va data-types = V2DF, V2DF, V2DF, V2DF /// lsx_vfnmadd_s +impl = portable name = lsx_vfnmadd_s asm-fmts = vd, vj, vk, va data-types = V4SF, V4SF, V4SF, V4SF /// lsx_vfnmadd_d +impl = portable name = lsx_vfnmadd_d asm-fmts = vd, vj, vk, va data-types = V2DF, V2DF, V2DF, V2DF /// lsx_vfnmsub_s +impl = portable name = lsx_vfnmsub_s asm-fmts = vd, vj, vk, va data-types = V4SF, V4SF, V4SF, V4SF /// lsx_vfnmsub_d +impl = portable name = lsx_vfnmsub_d asm-fmts = vd, vj, vk, va data-types = V2DF, V2DF, V2DF, V2DF @@ -2364,31 +2637,37 @@ asm-fmts = vd, vj data-types = V2DF, V2DF /// lsx_vfrintrz_s +impl = portable name = lsx_vfrintrz_s asm-fmts = vd, vj data-types = V4SF, V4SF /// lsx_vfrintrz_d +impl = portable name = lsx_vfrintrz_d asm-fmts = vd, vj data-types = V2DF, V2DF /// lsx_vfrintrp_s +impl = portable name = lsx_vfrintrp_s asm-fmts = vd, vj data-types = V4SF, V4SF /// lsx_vfrintrp_d +impl = portable name = lsx_vfrintrp_d asm-fmts = vd, vj data-types = V2DF, V2DF /// lsx_vfrintrm_s +impl = portable name = lsx_vfrintrm_s asm-fmts = vd, vj data-types = V4SF, V4SF /// lsx_vfrintrm_d +impl = portable name = lsx_vfrintrm_d asm-fmts = vd, vj data-types = V2DF, V2DF @@ -2874,21 +3153,25 @@ asm-fmts = vd, vj, vk data-types = V2DI, V2DI, UV2DI, V2DI /// lsx_vrotr_b +impl = portable name = lsx_vrotr_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vrotr_h +impl = portable name = lsx_vrotr_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vrotr_w +impl = portable name = lsx_vrotr_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vrotr_d +impl = portable name = lsx_vrotr_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI @@ -2974,21 +3257,25 @@ asm-fmts = vd, vj data-types = UV2DI, UV2DI /// lsx_vrotri_b +impl = portable name = lsx_vrotri_b asm-fmts = vd, vj, ui3 data-types = V16QI, V16QI, UQI /// lsx_vrotri_h +impl = portable name = lsx_vrotri_h asm-fmts = vd, vj, ui4 data-types = V8HI, V8HI, UQI /// lsx_vrotri_w +impl = portable name = lsx_vrotri_w asm-fmts = vd, vj, ui5 data-types = V4SI, V4SI, UQI /// lsx_vrotri_d +impl = portable name = lsx_vrotri_d asm-fmts = vd, vj, ui6 data-types = V2DI, V2DI, UQI @@ -3244,11 +3531,13 @@ asm-fmts = vd, vj, ui8 data-types = V4SI, V4SI, V4SI, USI /// lsx_vld +impl = portable name = lsx_vld asm-fmts = vd, rj, si12 data-types = V16QI, CVPOINTER, SI /// lsx_vst +impl = portable name = lsx_vst asm-fmts = vd, rj, si12 data-types = VOID, V16QI, CVPOINTER, SI @@ -3284,11 +3573,13 @@ asm-fmts = vd, vj, vk data-types = V4SI, V2DI, V2DI /// lsx_vorn_v +impl = portable name = lsx_vorn_v asm-fmts = vd, vj, vk -data-types = V16QI, V16QI, V16QI +data-types = UV16QI, UV16QI, UV16QI /// lsx_vldi +impl = portable name = lsx_vldi asm-fmts = vd, i13 data-types = V2DI, HI @@ -3299,11 +3590,13 @@ asm-fmts = vd, vj, vk, va data-types = V16QI, V16QI, V16QI, V16QI /// lsx_vldx +impl = portable name = lsx_vldx asm-fmts = vd, rj, rk data-types = V16QI, CVPOINTER, DI /// lsx_vstx +impl = portable name = lsx_vstx asm-fmts = vd, rj, rk data-types = VOID, V16QI, CVPOINTER, DI @@ -3584,21 +3877,25 @@ asm-fmts = vd, vj, vk data-types = V4SI, V4SF, V4SF /// lsx_vrepli_b +impl = portable name = lsx_vrepli_b asm-fmts = vd, si10 data-types = V16QI, HI /// lsx_vrepli_d +impl = portable name = lsx_vrepli_d asm-fmts = vd, si10 data-types = V2DI, HI /// lsx_vrepli_h +impl = portable name = lsx_vrepli_h asm-fmts = vd, si10 data-types = V8HI, HI /// lsx_vrepli_w +impl = portable name = lsx_vrepli_w asm-fmts = vd, si10 data-types = V4SI, HI diff --git a/library/stdarch/crates/stdarch-gen-loongarch/lsxintrin.h b/library/stdarch/crates/stdarch-gen-loongarch/lsxintrin.h index 943f2df913e4d..66b7c7e2187ac 100644 --- a/library/stdarch/crates/stdarch-gen-loongarch/lsxintrin.h +++ b/library/stdarch/crates/stdarch-gen-loongarch/lsxintrin.h @@ -1,10 +1,10 @@ /* - * https://gcc.gnu.org/git/?p=gcc.git;a=blob_plain;f=gcc/config/loongarch/lsxintrin.h;hb=61f1001f2f4ab9128e5eb6e9a4adbbb0f9f0bc75 + * https://gcc.gnu.org/git/?p=gcc.git;a=blob_plain;f=gcc/config/loongarch/lsxintrin.h;hb=6441eb6dc020faae0672ea724dfdb38c6a9bf6a1 */ /* LARCH Loongson SX intrinsics include file. - Copyright (C) 2018-2024 Free Software Foundation, Inc. + Copyright (C) 2018-2025 Free Software Foundation, Inc. This file is part of GCC. @@ -4749,11 +4749,11 @@ __m128i __lsx_vssrln_w_d (__m128i _1, __m128i _2) } /* Assembly instruction format: vd, vj, vk. */ -/* Data types in instruction templates: V16QI, V16QI, V16QI. */ +/* Data types in instruction templates: UV16QI, UV16QI, UV16QI. */ extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __m128i __lsx_vorn_v (__m128i _1, __m128i _2) { - return (__m128i)__builtin_lsx_vorn_v ((v16i8)_1, (v16i8)_2); + return (__m128i)__builtin_lsx_vorn_v ((v16u8)_1, (v16u8)_2); } /* Assembly instruction format: vd, i13. */ diff --git a/library/stdarch/crates/stdarch-gen-loongarch/src/main.rs b/library/stdarch/crates/stdarch-gen-loongarch/src/main.rs index 5076064ffcdd3..10e4b4f7472ca 100644 --- a/library/stdarch/crates/stdarch-gen-loongarch/src/main.rs +++ b/library/stdarch/crates/stdarch-gen-loongarch/src/main.rs @@ -1,9 +1,12 @@ +use std::collections::HashSet; use std::env; use std::fmt; use std::fs::File; use std::io::prelude::*; use std::io::{self, BufReader}; +use std::path::Path; use std::path::PathBuf; +use stdarch_gen_common::{Mode, run_generator}; /// Complete lines of generated source. /// @@ -90,6 +93,14 @@ impl TargetFeature { } } +fn portable_intrinsics() -> HashSet<&'static str> { + include_str!("portable-intrinsics.txt") + .lines() + .map(str::trim) + .filter(|line| !line.is_empty() && !line.starts_with('#')) + .collect() +} + fn gen_spec(in_file: String, ext_name: &str) -> io::Result<()> { let f = File::open(in_file.clone()).unwrap_or_else(|_| panic!("Failed to open {in_file}")); let f = BufReader::new(f); @@ -105,6 +116,7 @@ fn gen_spec(in_file: String, ext_name: &str) -> io::Result<()> { let mut asm_fmts = String::new(); let mut data_types = String::new(); let fn_pat = format!("__{ext_name}_"); + let portable_intrinsics = portable_intrinsics(); for line in f.lines() { let line = line.unwrap(); if line.is_empty() { @@ -121,6 +133,9 @@ fn gen_spec(in_file: String, ext_name: &str) -> io::Result<()> { let e = line.find('(').unwrap(); let name = line.get(s + 2..e).unwrap().trim().to_string(); out.push_str(&format!("/// {name}\n")); + if portable_intrinsics.contains(name.as_str()) { + out.push_str("impl = portable\n"); + } out.push_str(&format!("name = {name}\n")); out.push_str(&format!("asm-fmts = {asm_fmts}\n")); out.push_str(&format!("data-types = {data_types}\n")); @@ -135,8 +150,8 @@ fn gen_spec(in_file: String, ext_name: &str) -> io::Result<()> { Ok(()) } -fn gen_bind(in_file: String, ext_name: &str) -> io::Result<()> { - let f = File::open(in_file.clone()).unwrap_or_else(|_| panic!("Failed to open {in_file}")); +fn gen_bind(in_file: &str, ext_name: &str, out_path: &Path) -> io::Result<()> { + let f = File::open(in_file).unwrap_or_else(|_| panic!("Failed to open {in_file}")); let f = BufReader::new(f); let target: TargetFeature = TargetFeature::new(ext_name); @@ -146,6 +161,7 @@ fn gen_bind(in_file: String, ext_name: &str) -> io::Result<()> { let mut link_function_str = String::new(); let mut function_str = String::new(); let mut out = String::new(); + let mut skip = false; out.push_str(&format!( r#"// This code is automatically generated. DO NOT MODIFY. @@ -157,7 +173,7 @@ fn gen_bind(in_file: String, ext_name: &str) -> io::Result<()> { // ``` use crate::mem::transmute; -use super::types::*; +use super::super::*; "# )); @@ -173,7 +189,9 @@ unsafe extern "unadjusted" { if line.is_empty() { continue; } - if let Some(name) = line.strip_prefix("name = ") { + if line.starts_with("impl = portable") { + skip = true; + } else if let Some(name) = line.strip_prefix("name = ") { current_name = Some(String::from(name)); } else if line.starts_with("asm-fmts = ") { asm_fmts = line[10..] @@ -210,6 +228,11 @@ unsafe extern "unadjusted" { panic!("DEBUG: line: {0} len: {1}", line, data_types.len()); } + if skip { + skip = false; + continue; + } + let (link_function, function) = gen_bind_body(¤t_name, &asm_fmts, &in_t, out_t, para_num, target); link_function_str.push_str(&link_function); @@ -220,13 +243,7 @@ unsafe extern "unadjusted" { out.push_str("}\n"); out.push_str(&function_str); - let out_path: PathBuf = - PathBuf::from(env::var("OUT_DIR").unwrap_or("crates/core_arch".to_string())) - .join("src") - .join("loongarch64") - .join(ext_name); - std::fs::create_dir_all(&out_path)?; - + std::fs::create_dir_all(out_path)?; let mut file = File::create(out_path.join("generated.rs"))?; file.write_all(out.as_bytes())?; Ok(()) @@ -571,21 +588,21 @@ fn gen_bind_body( } else if para_num == 3 && in_t[1] == "CVPOINTER" && in_t[2] == "SI" { call_params = match asm_fmts[2].as_str() { "si12" => format!( - "static_assert_simm_bits!(IMM_S12, 12);\n {unsafe_start}transmute(__{current_name}(transmute(a), mem_addr, IMM_S12)){unsafe_end}" + "static_assert_simm_bits!(IMM_S12, 12);\n {unsafe_start}__{current_name}(transmute(a), mem_addr, IMM_S12){unsafe_end}" ), _ => panic!("unsupported assembly format: {}", asm_fmts[2]), }; } else if para_num == 3 && in_t[1] == "CVPOINTER" && in_t[2] == "DI" { call_params = match asm_fmts[2].as_str() { "rk" => format!( - "{unsafe_start}transmute(__{current_name}(transmute(a), mem_addr, transmute(b))){unsafe_end}" + "{unsafe_start}__{current_name}(transmute(a), mem_addr, transmute(b)){unsafe_end}" ), _ => panic!("unsupported assembly format: {}", asm_fmts[2]), }; } else if para_num == 4 { call_params = match (asm_fmts[2].as_str(), current_name.chars().last().unwrap()) { ("si8", t) => format!( - "static_assert_simm_bits!(IMM_S8, 8);\n static_assert_uimm_bits!(IMM{0}, {0});\n {unsafe_start}transmute(__{current_name}(transmute(a), mem_addr, IMM_S8, IMM{0})){unsafe_end}", + "static_assert_simm_bits!(IMM_S8, 8);\n static_assert_uimm_bits!(IMM{0}, {0});\n {unsafe_start}__{current_name}(transmute(a), mem_addr, IMM_S8, IMM{0}){unsafe_end}", type_to_imm(t) ), (_, _) => panic!( @@ -841,12 +858,13 @@ union v4df out.push('\n'); out.push_str("int main(int argc, char *argv[])\n"); out.push_str("{\n"); - out.push_str(" printf(\"// This code is automatically generated. DO NOT MODIFY.\\n\");\n"); + out.push_str(" printf(\"// Auto-generated tests. DO NOT MODIFY.\\n\");\n"); out.push_str(" printf(\"// See crates/stdarch-gen-loongarch/README.md\\n\\n\");\n"); out.push_str(" printf(\"use crate::{\\n\");\n"); out.push_str(" printf(\" core_arch::{loongarch64::*, simd::*},\\n\");\n"); out.push_str(" printf(\" mem::transmute,\\n\");\n"); out.push_str(" printf(\"};\\n\");\n"); + out.push_str(" printf(\"use std::hint::black_box;\\n\");\n"); out.push_str(" printf(\"use stdarch_test::simd_test;\\n\");\n"); out.push_str(&call_function_str); out.push_str(" return 0;\n"); @@ -1323,10 +1341,10 @@ fn gen_test_body( _ => "unsupported parameter number".to_string(), }; let mut as_params = match para_num { - 1 => "(transmute(a))".to_string(), - 2 => "(transmute(a), transmute(b))".to_string(), - 3 => "(transmute(a), transmute(b), transmute(c))".to_string(), - 4 => "(transmute(a), transmute(b), transmute(c), transmute(d))".to_string(), + 1 => "(black_box(transmute(a)))".to_string(), + 2 => "(black_box(transmute(a)), black_box(transmute(b)))".to_string(), + 3 => "(black_box(transmute(a)), black_box(transmute(b)), black_box(transmute(c)))".to_string(), + 4 => "(black_box(transmute(a)), black_box(transmute(b)), black_box(transmute(c)), black_box(transmute(d)))".to_string(), _ => panic!("unsupported parameter number"), }; let mut as_args = String::new(); @@ -1356,9 +1374,9 @@ fn gen_test_body( { fn_params = "(a)".to_string(); if in_t[0] == "SI" { - as_params = "(%d)".to_string(); + as_params = "(black_box(%d))".to_string(); } else { - as_params = "(%ld)".to_string(); + as_params = "(black_box(%ld))".to_string(); } as_args = ", a".to_string(); } else if para_num == 2 && (in_t[1] == "UQI" || in_t[1] == "USI") { @@ -1370,7 +1388,7 @@ fn gen_test_body( ); let val = rand_u32(asm_fmts[2].get(2..).unwrap().parse::().unwrap()); fn_params = format!("(a.v, {val})"); - as_params = format!("::<{val}>(transmute(a))"); + as_params = format!("::<{val}>(black_box(transmute(a)))"); } else { panic!("unsupported assembly format: {}", asm_fmts[2]); } @@ -1383,13 +1401,13 @@ fn gen_test_body( ); let val = rand_i32(asm_fmts[2].get(2..).unwrap().parse::().unwrap()); fn_params = format!("(a.v, {val})"); - as_params = format!("::<{val}>(transmute(a))"); + as_params = format!("::<{val}>(black_box(transmute(a)))"); } else { panic!("unsupported assembly format: {}", asm_fmts[2]); } } else if para_num == 2 && in_t[1] == "SI" && asm_fmts[2].starts_with("rk") { fn_params = "(a.v, b)".to_string(); - as_params = "(transmute(a), %d)".to_string(); + as_params = "(black_box(transmute(a)), %d)".to_string(); as_args = ", b".to_string(); } else if para_num == 2 && in_t[0] == "CVPOINTER" && in_t[1] == "SI" { if asm_fmts[2].starts_with("si") { @@ -1441,7 +1459,7 @@ fn gen_test_body( let ival = rand_i32(32); let uval = rand_u32(asm_fmts[2].get(2..).unwrap().parse::().unwrap()); fn_params = format!("(a.v, {ival}, {uval})"); - as_params = format!("::<{uval}>(transmute(a), {ival})"); + as_params = format!("::<{uval}>(black_box(transmute(a)), {ival})"); } else { panic!("unsupported assembly format: {}", asm_fmts[2]); } @@ -1456,7 +1474,7 @@ fn gen_test_body( ); let val = rand_u32(asm_fmts[2].get(2..).unwrap().parse::().unwrap()); fn_params = format!("(a.v, b.v, {val})"); - as_params = format!("::<{val}>(transmute(a), transmute(b))"); + as_params = format!("::<{val}>(black_box(transmute(a)), black_box(transmute(b)))"); } else { panic!("unsupported assembly format: {}", asm_fmts[2]); } @@ -1478,7 +1496,7 @@ fn gen_test_body( type_to_ct(in_t[1]) ); fn_params = "(a.v, b, 0)".to_string(); - as_params = "::<0>(transmute(a), o.as_mut_ptr())".to_string(); + as_params = "::<0>(black_box(transmute(a)), o.as_mut_ptr())".to_string(); } else { panic!("unsupported assembly format: {}", asm_fmts[2]); } @@ -1500,7 +1518,7 @@ fn gen_test_body( type_to_ct(in_t[1]) ); fn_params = "(a.v, b, 0)".to_string(); - as_params = "(transmute(a), o.as_mut_ptr(), 0)".to_string(); + as_params = "(black_box(transmute(a)), o.as_mut_ptr(), 0)".to_string(); } else { panic!("unsupported assembly format: {}", asm_fmts[2]); } @@ -1524,7 +1542,7 @@ fn gen_test_body( ); let val = rand_u32(type_to_imm(t).try_into().unwrap()); fn_params = format!("(a.v, b, 0, {val})"); - as_params = format!("::<0, {val}>(transmute(a), o.as_mut_ptr())"); + as_params = format!("::<0, {val}>(black_box(transmute(a)), o.as_mut_ptr())"); } (_, _) => panic!( "unsupported assembly format: {} for {}", @@ -1551,6 +1569,10 @@ fn gen_test_body( format!( " printf(\"\\n {current_name}{as_params};\\n assert_eq!(r, transmute(o));\\n\"{as_args});" ) + } else if current_name.starts_with("lasx_cast_128") { + format!( + " printf(\"\\n assert_eq!(r.as_array()[0..2], transmute::<_, i64x4>({current_name}{as_params}).as_array()[0..2]);\\n\"{as_args});" + ) } else { format!( " printf(\"\\n assert_eq!(r, transmute({current_name}{as_params}));\\n\"{as_args});" @@ -1578,28 +1600,53 @@ static void {current_name}(void) (impl_function, call_function) } -pub fn main() -> io::Result<()> { +/// Runs the check/bless harness for `lsx`/`lasx` when invoked with +/// no args or a bare ext name. +pub fn main() -> Result<(), String> { let args: Vec = env::args().collect(); - let in_file = args.get(1).cloned().expect("Input file missing!"); - let in_file_path = PathBuf::from(&in_file); - let in_file_name = in_file_path + let arg_strs: Vec<&str> = args.iter().map(String::as_str).collect(); + let harness_exts: Option<&[&str]> = match arg_strs.as_slice() { + [_] => Some(&["lsx", "lasx"]), + [_, "lsx"] => Some(&["lsx"]), + [_, "lasx"] => Some(&["lasx"]), + _ => None, + }; + if let Some(exts) = harness_exts { + let crate_dir = + PathBuf::from(env::var("CARGO_MANIFEST_DIR").expect("CARGO_MANIFEST_DIR not set")); + let core_arch_src = crate_dir.join("../core_arch/src"); + let mode = Mode::from_env(); + for ext in exts { + let spec_rel = format!("crates/stdarch-gen-loongarch/{ext}.spec"); + let committed = core_arch_src.join("loongarch64").join(ext); + run_generator(&committed, mode, |out_dir| { + gen_bind(&spec_rel, ext, out_dir) + }) + .map_err(|e| e.to_string())?; + } + return Ok(()); + } + + let in_file = args[1].clone(); + let in_file_name = PathBuf::from(&in_file) .file_name() .unwrap() - .to_os_string() - .into_string() - .unwrap(); - + .to_string_lossy() + .into_owned(); let ext_name = if in_file_name.starts_with("lasx") { "lasx" } else { "lsx" }; - if in_file_name.ends_with(".h") { - gen_spec(in_file, ext_name) - } else if args.get(2).is_some() { - gen_test(in_file, ext_name) - } else { - gen_bind(in_file, ext_name) + return gen_spec(in_file, ext_name).map_err(|e| e.to_string()); + } + if let [_, _lsx_or_lasx, "test"] = arg_strs.as_slice() { + return gen_test(in_file, ext_name).map_err(|e| e.to_string()); } + let out_path = PathBuf::from(env::var("OUT_DIR").unwrap_or("crates/core_arch".to_string())) + .join("src") + .join("loongarch64") + .join(ext_name); + gen_bind(&in_file, ext_name, &out_path).map_err(|e| e.to_string()) } diff --git a/library/stdarch/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt b/library/stdarch/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt new file mode 100644 index 0000000000000..8b8c82b3bb247 --- /dev/null +++ b/library/stdarch/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt @@ -0,0 +1,595 @@ +# LSX intrinsics +lsx_vsll_b +lsx_vsll_h +lsx_vsll_w +lsx_vsll_d +lsx_vslli_b +lsx_vslli_h +lsx_vslli_w +lsx_vslli_d +lsx_vsra_b +lsx_vsra_h +lsx_vsra_w +lsx_vsra_d +lsx_vsrai_b +lsx_vsrai_h +lsx_vsrai_w +lsx_vsrai_d +lsx_vsrl_b +lsx_vsrl_h +lsx_vsrl_w +lsx_vsrl_d +lsx_vsrli_b +lsx_vsrli_h +lsx_vsrli_w +lsx_vsrli_d +lsx_vadd_b +lsx_vadd_h +lsx_vadd_w +lsx_vadd_d +lsx_vaddi_bu +lsx_vaddi_hu +lsx_vaddi_wu +lsx_vaddi_du +lsx_vsub_b +lsx_vsub_h +lsx_vsub_w +lsx_vsub_d +lsx_vmax_b +lsx_vmax_h +lsx_vmax_w +lsx_vmax_d +lsx_vmaxi_b +lsx_vmaxi_h +lsx_vmaxi_w +lsx_vmaxi_d +lsx_vmax_bu +lsx_vmax_hu +lsx_vmax_wu +lsx_vmax_du +lsx_vmaxi_bu +lsx_vmaxi_hu +lsx_vmaxi_wu +lsx_vmaxi_du +lsx_vmin_b +lsx_vmin_h +lsx_vmin_w +lsx_vmin_d +lsx_vmini_b +lsx_vmini_h +lsx_vmini_w +lsx_vmini_d +lsx_vmin_bu +lsx_vmin_hu +lsx_vmin_wu +lsx_vmin_du +lsx_vmini_bu +lsx_vmini_hu +lsx_vmini_wu +lsx_vmini_du +lsx_vseq_b +lsx_vseq_h +lsx_vseq_w +lsx_vseq_d +lsx_vseqi_b +lsx_vseqi_h +lsx_vseqi_w +lsx_vseqi_d +lsx_vslt_b +lsx_vslt_h +lsx_vslt_w +lsx_vslt_d +lsx_vslti_b +lsx_vslti_h +lsx_vslti_w +lsx_vslti_d +lsx_vslt_bu +lsx_vslt_hu +lsx_vslt_wu +lsx_vslt_du +lsx_vslti_bu +lsx_vslti_hu +lsx_vslti_wu +lsx_vslti_du +lsx_vsle_b +lsx_vsle_h +lsx_vsle_w +lsx_vsle_d +lsx_vslei_b +lsx_vslei_h +lsx_vslei_w +lsx_vslei_d +lsx_vsle_bu +lsx_vsle_hu +lsx_vsle_wu +lsx_vsle_du +lsx_vslei_bu +lsx_vslei_hu +lsx_vslei_wu +lsx_vslei_du +lsx_vmul_b +lsx_vmul_h +lsx_vmul_w +lsx_vmul_d +lsx_vdiv_b +lsx_vdiv_h +lsx_vdiv_w +lsx_vdiv_d +lsx_vdiv_bu +lsx_vdiv_hu +lsx_vdiv_wu +lsx_vdiv_du +lsx_vmod_b +lsx_vmod_h +lsx_vmod_w +lsx_vmod_d +lsx_vmod_bu +lsx_vmod_hu +lsx_vmod_wu +lsx_vmod_du +lsx_vmadd_b +lsx_vmadd_h +lsx_vmadd_w +lsx_vmadd_d +lsx_vmsub_b +lsx_vmsub_h +lsx_vmsub_w +lsx_vmsub_d +lsx_vand_v +lsx_vor_v +lsx_vnor_v +lsx_vxor_v +lsx_vpcnt_b +lsx_vpcnt_h +lsx_vpcnt_w +lsx_vpcnt_d +lsx_vclz_b +lsx_vclz_h +lsx_vclz_w +lsx_vclz_d +lsx_vreplgr2vr_b +lsx_vreplgr2vr_h +lsx_vreplgr2vr_w +lsx_vreplgr2vr_d +lsx_vpickve2gr_b +lsx_vpickve2gr_h +lsx_vpickve2gr_w +lsx_vpickve2gr_d +lsx_vpickve2gr_bu +lsx_vpickve2gr_hu +lsx_vpickve2gr_wu +lsx_vpickve2gr_du +lsx_vinsgr2vr_b +lsx_vinsgr2vr_h +lsx_vinsgr2vr_w +lsx_vinsgr2vr_d +lsx_vfadd_s +lsx_vfadd_d +lsx_vfsub_s +lsx_vfsub_d +lsx_vfmul_s +lsx_vfmul_d +lsx_vfdiv_s +lsx_vfdiv_d +lsx_vfsqrt_s +lsx_vfsqrt_d +lsx_vandn_v +lsx_vneg_b +lsx_vneg_h +lsx_vneg_w +lsx_vneg_d +lsx_vfmadd_s +lsx_vfmadd_d +lsx_vfmsub_s +lsx_vfmsub_d +lsx_vfnmadd_s +lsx_vfnmadd_d +lsx_vfnmsub_s +lsx_vfnmsub_d +lsx_vorn_v +lsx_vrepli_b +lsx_vrepli_h +lsx_vrepli_w +lsx_vrepli_d +lsx_vbitclr_b +lsx_vbitclr_h +lsx_vbitclr_w +lsx_vbitclr_d +lsx_vbitset_b +lsx_vbitset_h +lsx_vbitset_w +lsx_vbitset_d +lsx_vbitrev_b +lsx_vbitrev_h +lsx_vbitrev_w +lsx_vbitrev_d +lsx_vsadd_b +lsx_vsadd_h +lsx_vsadd_w +lsx_vsadd_d +lsx_vsadd_bu +lsx_vsadd_hu +lsx_vsadd_wu +lsx_vsadd_du +lsx_vssub_b +lsx_vssub_h +lsx_vssub_w +lsx_vssub_d +lsx_vssub_bu +lsx_vssub_hu +lsx_vssub_wu +lsx_vssub_du +lsx_vadda_b +lsx_vadda_h +lsx_vadda_w +lsx_vadda_d +lsx_vabsd_b +lsx_vabsd_h +lsx_vabsd_w +lsx_vabsd_d +lsx_vabsd_bu +lsx_vabsd_hu +lsx_vabsd_wu +lsx_vabsd_du +lsx_vpickev_b +lsx_vpickev_h +lsx_vpickev_w +lsx_vpickev_d +lsx_vpickod_b +lsx_vpickod_h +lsx_vpickod_w +lsx_vpickod_d +lsx_vilvh_b +lsx_vilvh_h +lsx_vilvh_w +lsx_vilvh_d +lsx_vilvl_b +lsx_vilvl_h +lsx_vilvl_w +lsx_vilvl_d +lsx_vreplvei_b +lsx_vreplvei_h +lsx_vreplvei_w +lsx_vreplvei_d +lsx_vpackev_b +lsx_vpackev_h +lsx_vpackev_w +lsx_vpackev_d +lsx_vpackod_b +lsx_vpackod_h +lsx_vpackod_w +lsx_vpackod_d +lsx_vshuf4i_b +lsx_vshuf4i_h +lsx_vshuf4i_w +lsx_vshuf4i_d +lsx_vld +lsx_vst +lsx_vldx +lsx_vstx +lsx_vrotr_b +lsx_vrotr_h +lsx_vrotr_w +lsx_vrotr_d +lsx_vrotri_b +lsx_vrotri_h +lsx_vrotri_w +lsx_vrotri_d +lsx_vfrecip_s +lsx_vfrecip_d +lsx_vfrsqrt_s +lsx_vfrsqrt_d +lsx_vfrintrp_s +lsx_vfrintrp_d +lsx_vfrintrm_s +lsx_vfrintrm_d +lsx_vfrintrz_s +lsx_vfrintrz_d +lsx_vmuh_b +lsx_vmuh_h +lsx_vmuh_w +lsx_vmuh_d +lsx_vmuh_bu +lsx_vmuh_hu +lsx_vmuh_wu +lsx_vmuh_du +lsx_vldi +lsx_vbsll_v +lsx_vbsrl_v + +# LASX intrinsics +lasx_xvsll_b +lasx_xvsll_h +lasx_xvsll_w +lasx_xvsll_d +lasx_xvslli_b +lasx_xvslli_h +lasx_xvslli_w +lasx_xvslli_d +lasx_xvsra_b +lasx_xvsra_h +lasx_xvsra_w +lasx_xvsra_d +lasx_xvsrai_b +lasx_xvsrai_h +lasx_xvsrai_w +lasx_xvsrai_d +lasx_xvsrl_b +lasx_xvsrl_h +lasx_xvsrl_w +lasx_xvsrl_d +lasx_xvsrli_b +lasx_xvsrli_h +lasx_xvsrli_w +lasx_xvsrli_d +lasx_xvadd_b +lasx_xvadd_h +lasx_xvadd_w +lasx_xvadd_d +lasx_xvaddi_bu +lasx_xvaddi_hu +lasx_xvaddi_wu +lasx_xvaddi_du +lasx_xvsub_b +lasx_xvsub_h +lasx_xvsub_w +lasx_xvsub_d +lasx_xvmax_b +lasx_xvmax_h +lasx_xvmax_w +lasx_xvmax_d +lasx_xvmaxi_b +lasx_xvmaxi_h +lasx_xvmaxi_w +lasx_xvmaxi_d +lasx_xvmax_bu +lasx_xvmax_hu +lasx_xvmax_wu +lasx_xvmax_du +lasx_xvmaxi_bu +lasx_xvmaxi_hu +lasx_xvmaxi_wu +lasx_xvmaxi_du +lasx_xvmin_b +lasx_xvmin_h +lasx_xvmin_w +lasx_xvmin_d +lasx_xvmini_b +lasx_xvmini_h +lasx_xvmini_w +lasx_xvmini_d +lasx_xvmin_bu +lasx_xvmin_hu +lasx_xvmin_wu +lasx_xvmin_du +lasx_xvmini_bu +lasx_xvmini_hu +lasx_xvmini_wu +lasx_xvmini_du +lasx_xvseq_b +lasx_xvseq_h +lasx_xvseq_w +lasx_xvseq_d +lasx_xvseqi_b +lasx_xvseqi_h +lasx_xvseqi_w +lasx_xvseqi_d +lasx_xvslt_b +lasx_xvslt_h +lasx_xvslt_w +lasx_xvslt_d +lasx_xvslti_b +lasx_xvslti_h +lasx_xvslti_w +lasx_xvslti_d +lasx_xvslt_bu +lasx_xvslt_hu +lasx_xvslt_wu +lasx_xvslt_du +lasx_xvslti_bu +lasx_xvslti_hu +lasx_xvslti_wu +lasx_xvslti_du +lasx_xvsle_b +lasx_xvsle_h +lasx_xvsle_w +lasx_xvsle_d +lasx_xvslei_b +lasx_xvslei_h +lasx_xvslei_w +lasx_xvslei_d +lasx_xvsle_bu +lasx_xvsle_hu +lasx_xvsle_wu +lasx_xvsle_du +lasx_xvslei_bu +lasx_xvslei_hu +lasx_xvslei_wu +lasx_xvslei_du +lasx_xvmul_b +lasx_xvmul_h +lasx_xvmul_w +lasx_xvmul_d +lasx_xvdiv_b +lasx_xvdiv_h +lasx_xvdiv_w +lasx_xvdiv_d +lasx_xvdiv_bu +lasx_xvdiv_hu +lasx_xvdiv_wu +lasx_xvdiv_du +lasx_xvmod_b +lasx_xvmod_h +lasx_xvmod_w +lasx_xvmod_d +lasx_xvmod_bu +lasx_xvmod_hu +lasx_xvmod_wu +lasx_xvmod_du +lasx_xvmadd_b +lasx_xvmadd_h +lasx_xvmadd_w +lasx_xvmadd_d +lasx_xvmsub_b +lasx_xvmsub_h +lasx_xvmsub_w +lasx_xvmsub_d +lasx_xvand_v +lasx_xvor_v +lasx_xvnor_v +lasx_xvxor_v +lasx_xvpcnt_b +lasx_xvpcnt_h +lasx_xvpcnt_w +lasx_xvpcnt_d +lasx_xvclz_b +lasx_xvclz_h +lasx_xvclz_w +lasx_xvclz_d +lasx_xvreplgr2vr_b +lasx_xvreplgr2vr_h +lasx_xvreplgr2vr_w +lasx_xvreplgr2vr_d +lasx_xvpickve2gr_w +lasx_xvpickve2gr_d +lasx_xvpickve2gr_wu +lasx_xvpickve2gr_du +lasx_xvinsgr2vr_w +lasx_xvinsgr2vr_d +lasx_xvfadd_s +lasx_xvfadd_d +lasx_xvfsub_s +lasx_xvfsub_d +lasx_xvfmul_s +lasx_xvfmul_d +lasx_xvfdiv_s +lasx_xvfdiv_d +lasx_xvfsqrt_s +lasx_xvfsqrt_d +lasx_xvandn_v +lasx_xvneg_b +lasx_xvneg_h +lasx_xvneg_w +lasx_xvneg_d +lasx_xvfmadd_s +lasx_xvfmadd_d +lasx_xvfmsub_s +lasx_xvfmsub_d +lasx_xvfnmadd_s +lasx_xvfnmadd_d +lasx_xvfnmsub_s +lasx_xvfnmsub_d +lasx_xvorn_v +lasx_xvrepli_b +lasx_xvrepli_h +lasx_xvrepli_w +lasx_xvrepli_d +lasx_xvbitclr_b +lasx_xvbitclr_h +lasx_xvbitclr_w +lasx_xvbitclr_d +lasx_xvbitset_b +lasx_xvbitset_h +lasx_xvbitset_w +lasx_xvbitset_d +lasx_xvbitrev_b +lasx_xvbitrev_h +lasx_xvbitrev_w +lasx_xvbitrev_d +lasx_xvsadd_b +lasx_xvsadd_h +lasx_xvsadd_w +lasx_xvsadd_d +lasx_xvsadd_bu +lasx_xvsadd_hu +lasx_xvsadd_wu +lasx_xvsadd_du +lasx_xvssub_b +lasx_xvssub_h +lasx_xvssub_w +lasx_xvssub_d +lasx_xvssub_bu +lasx_xvssub_hu +lasx_xvssub_wu +lasx_xvssub_du +lasx_xvadda_b +lasx_xvadda_h +lasx_xvadda_w +lasx_xvadda_d +lasx_xvabsd_b +lasx_xvabsd_h +lasx_xvabsd_w +lasx_xvabsd_d +lasx_xvabsd_bu +lasx_xvabsd_hu +lasx_xvabsd_wu +lasx_xvabsd_du +lasx_xvpickev_b +lasx_xvpickev_h +lasx_xvpickev_w +lasx_xvpickev_d +lasx_xvpickod_b +lasx_xvpickod_h +lasx_xvpickod_w +lasx_xvpickod_d +lasx_xvilvh_b +lasx_xvilvh_h +lasx_xvilvh_w +lasx_xvilvh_d +lasx_xvilvl_b +lasx_xvilvl_h +lasx_xvilvl_w +lasx_xvilvl_d +lasx_xvrepl128vei_b +lasx_xvrepl128vei_h +lasx_xvrepl128vei_w +lasx_xvrepl128vei_d +lasx_xvreplve0_b +lasx_xvreplve0_h +lasx_xvreplve0_w +lasx_xvreplve0_d +lasx_xvreplve0_q +lasx_xvpackev_b +lasx_xvpackev_h +lasx_xvpackev_w +lasx_xvpackev_d +lasx_xvpackod_b +lasx_xvpackod_h +lasx_xvpackod_w +lasx_xvpackod_d +lasx_xvshuf4i_b +lasx_xvshuf4i_h +lasx_xvshuf4i_w +lasx_xvld +lasx_xvst +lasx_xvldx +lasx_xvstx +lasx_xvrotr_b +lasx_xvrotr_h +lasx_xvrotr_w +lasx_xvrotr_d +lasx_xvrotri_b +lasx_xvrotri_h +lasx_xvrotri_w +lasx_xvrotri_d +lasx_xvfrecip_s +lasx_xvfrecip_d +lasx_xvfrsqrt_s +lasx_xvfrsqrt_d +lasx_xvfrintrp_s +lasx_xvfrintrp_d +lasx_xvfrintrm_s +lasx_xvfrintrm_d +lasx_xvfrintrz_s +lasx_xvfrintrz_d +lasx_xvmuh_b +lasx_xvmuh_h +lasx_xvmuh_w +lasx_xvmuh_d +lasx_xvmuh_bu +lasx_xvmuh_hu +lasx_xvmuh_wu +lasx_xvmuh_du +lasx_xvldi +lasx_xvbsll_v +lasx_xvbsrl_v diff --git a/library/stdarch/crates/stdarch-test/Cargo.toml b/library/stdarch/crates/stdarch-test/Cargo.toml index e88258bfd30d0..2f3d294e12975 100644 --- a/library/stdarch/crates/stdarch-test/Cargo.toml +++ b/library/stdarch/crates/stdarch-test/Cargo.toml @@ -7,8 +7,7 @@ edition = "2024" [dependencies] assert-instr-macro = { path = "../assert-instr-macro" } simd-test-macro = { path = "../simd-test-macro" } -rustc-demangle = "0.1.8" -cfg-if = "1.0" +rustc-demangle = "0.1.28" [target.'cfg(windows)'.dependencies] cc = "1.0" diff --git a/library/stdarch/crates/stdarch-test/src/disassembly.rs b/library/stdarch/crates/stdarch-test/src/disassembly.rs index 237e8d2dc28a0..85aab498619d2 100644 --- a/library/stdarch/crates/stdarch-test/src/disassembly.rs +++ b/library/stdarch/crates/stdarch-test/src/disassembly.rs @@ -158,16 +158,26 @@ fn parse(output: &str) -> HashSet { }; if cfg!(any(target_arch = "aarch64", target_arch = "arm64ec")) { - // Normalize [us]shll.* ..., #0 instructions to the preferred form: [us]xtl.* ... - // as neither LLVM objdump nor dumpbin does that. - // See https://developer.arm.com/documentation/ddi0602/latest/SIMD-FP-Instructions/UXTL--UXTL2--Unsigned-extend-Long--an-alias-of-USHLL--USHLL2- - // and https://developer.arm.com/documentation/ddi0602/latest/SIMD-FP-Instructions/SXTL--SXTL2--Signed-extend-Long--an-alias-of-SSHLL--SSHLL2- - // for details. + // Normalize `[us]shll{2}.* ..., #0` instructions to the preferred + // form: `[us]xtl{2}.* ...` as neither LLVM objdump nor dumpbin does that. + // + // SVE has `[us]shll[tb]` instructions that don't have an equivalent alias. + // + // See Arm documentation for details: + // + // - https://developer.arm.com/documentation/ddi0602/2026-03/SIMD-FP-Instructions/UXTL--UXTL2--Unsigned-extend-long--an-alias-of-USHLL--USHLL2-?lang=en + // - https://developer.arm.com/documentation/ddi0602/2026-03/SIMD-FP-Instructions/SXTL--SXTL2--Signed-extend-long--an-alias-of-SSHLL--SSHLL2-?lang=en fn is_shll(instr: &str) -> bool { if cfg!(target_env = "msvc") { - instr.starts_with("ushll") || instr.starts_with("sshll") + instr == "ushll" + || instr == "ushll2" + || instr == "sshll" + || instr == "sshll2" } else { - instr.starts_with("ushll.") || instr.starts_with("sshll.") + instr == "ushll." + || instr == "ushll2." + || instr == "sshll." + || instr == "sshll2." } } match (parts.first(), parts.last()) { @@ -188,8 +198,11 @@ fn parse(output: &str) -> HashSet { }; } + // When using vectorcall the `ret` can have an argument, so match only the first part. + let is_ret = matches!(parts.first().map(String::as_str), Some("ret" | "retq")); + instructions.push(parts.join(" ")); - if matches!(&**instructions.last().unwrap(), "ret" | "retq") { + if is_ret { cached_header = None; break; } diff --git a/library/stdarch/crates/stdarch-test/src/lib.rs b/library/stdarch/crates/stdarch-test/src/lib.rs index ecaf95f61766a..9ef25a7957c1d 100644 --- a/library/stdarch/crates/stdarch-test/src/lib.rs +++ b/library/stdarch/crates/stdarch-test/src/lib.rs @@ -6,18 +6,16 @@ #![deny(rust_2018_idioms)] #![allow(clippy::missing_docs_in_private_items, clippy::print_stdout)] -#[macro_use] -extern crate cfg_if; - pub use assert_instr_macro::*; pub use simd_test_macro::*; use std::{cmp, collections::HashSet, env, hash, hint::black_box, str, sync::LazyLock}; -cfg_if! { - if #[cfg(target_arch = "wasm32")] { +cfg_select! { + target_arch = "wasm32" => { pub mod wasm; use wasm::disassemble_myself; - } else { + } + _ => { mod disassembly; use crate::disassembly::disassemble_myself; } @@ -172,6 +170,10 @@ pub fn assert(shim_addr: usize, fnname: &str, expected: &str) { // vst1q_p64_x4_nop : #instructions = 33 >= 22 (limit) "nop" if fnname.contains("vst1q_p64") => 34, + // AMX intrinsics generate a lot of move instructions to load/store the tile registers + // due to Rust ABI + _ if fnname.contains("___tile") => 165, + // Original limit was 20 instructions, but ARM DSP Intrinsics // are exactly 20 instructions long. So, bump the limit to 22 // instead of adding here a long list of exceptions. diff --git a/library/stdarch/crates/stdarch-test/src/wasm.rs b/library/stdarch/crates/stdarch-test/src/wasm.rs index bf411c12148e2..feadaa1215980 100644 --- a/library/stdarch/crates/stdarch-test/src/wasm.rs +++ b/library/stdarch/crates/stdarch-test/src/wasm.rs @@ -2,6 +2,7 @@ use crate::Function; use std::collections::HashSet; +use std::path::Path; pub(crate) fn disassemble_myself() -> HashSet { // Use `std::env::args` to find the path to our executable. Assume the @@ -11,6 +12,27 @@ pub(crate) fn disassemble_myself() -> HashSet { let me = std::env::args() .next() .expect("failed to find current wasm file"); + let me = Path::new(&me); + let me = if me.exists() { + // Old build-dir layout + me.to_path_buf() + } else { + // Cargo's build-dir layout stores an artifact named + // `-.wasm` at `//out/-.wasm`. + // The build directory is mounted as the WASI working directory, so + // reconstruct that guest-visible path from the executable name. + let file_name = me + .file_name() + .and_then(|name| name.to_str()) + .expect("current wasm file has a file name"); + let stem = file_name + .strip_suffix(".wasm") + .expect("current wasm file does not have a .wasm extension"); + let (crate_name, hash) = stem + .rsplit_once('-') + .expect("current wasm file name does not contain an artifact hash"); + Path::new(crate_name).join(hash).join("out").join(file_name) + }; let output = wasmprinter::print_file(&me).unwrap(); let mut ret: HashSet = HashSet::new(); diff --git a/library/stdarch/crates/stdarch-verify/src/lib.rs b/library/stdarch/crates/stdarch-verify/src/lib.rs index c81f5f45bcce4..5412ab466ad58 100644 --- a/library/stdarch/crates/stdarch-verify/src/lib.rs +++ b/library/stdarch/crates/stdarch-verify/src/lib.rs @@ -120,6 +120,13 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream { ); } + // Newer intrinsics don't have `rustc_legacy_const_generics` - assume they belong at + // the end of the argument list + if required_const.is_empty() && legacy_const_generics.is_empty() { + legacy_const_generics = + (arguments.len()..(arguments.len() + const_arguments.len())).collect(); + } + // The list of required consts, used to verify the arguments, comes from either the // `rustc_args_required_const` or the `rustc_legacy_const_generics` attribute. let required_const = if required_const.is_empty() { @@ -136,14 +143,14 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream { arguments.insert(idx, ty); } - // strip leading underscore from fn name when building a test - // _mm_foo -> mm_foo such that the test name is test_mm_foo. - let test_name_string = format!("{name}"); - let mut test_name_id = test_name_string.as_str(); - while test_name_id.starts_with('_') { - test_name_id = &test_name_id[1..]; - } - let has_test = tests.contains(&format!("test_{test_name_id}")); + // Strip leading underscore from fn name when building a test + // `_mm_foo` -> `mm_foo` such that the test name is `test_mm_foo`. + let test_name = name.to_string(); + let test_name = test_name.trim_start_matches('_'); + let has_test = tests.contains(&format!("test_{test_name}")) + // SVE load/store tests start with `test` or `_with_` + || tests.iter().any(|t| t.starts_with(&format!("test_{test_name}")) + || t.ends_with(&format!("_with_{test_name}"))); let doc = find_doc(&f.attrs); @@ -195,6 +202,7 @@ fn to_type(t: &syn::Type) -> proc_macro2::TokenStream { "_MM_MANTISSA_NORM_ENUM" => quote! { &MM_MANTISSA_NORM_ENUM }, "_MM_MANTISSA_SIGN_ENUM" => quote! { &MM_MANTISSA_SIGN_ENUM }, "_MM_PERM_ENUM" => quote! { &MM_PERM_ENUM }, + "__tile1024i" => quote! { &TILE1024I }, "bool" => quote! { &BOOL }, "bf16" => quote! { &BF16 }, "f16" => quote! { &F16 }, @@ -347,6 +355,50 @@ fn to_type(t: &syn::Type) -> proc_macro2::TokenStream { "v4f32" => quote! { &v4f32 }, "v2f64" => quote! { &v2f64 }, + "svbool_t" => quote! { &SVBOOL }, + "svint8_t" => quote! { &SVI8 }, + "svint8x2_t" => quote! { &SVI8X2 }, + "svint8x3_t" => quote! { &SVI8X3 }, + "svint8x4_t" => quote! { &SVI8X4 }, + "svint16_t" => quote! { &SVI16 }, + "svint16x2_t" => quote! { &SVI16X2 }, + "svint16x3_t" => quote! { &SVI16X3 }, + "svint16x4_t" => quote! { &SVI16X4 }, + "svint32_t" => quote! { &SVI32 }, + "svint32x2_t" => quote! { &SVI32X2 }, + "svint32x3_t" => quote! { &SVI32X3 }, + "svint32x4_t" => quote! { &SVI32X4 }, + "svint64_t" => quote! { &SVI64 }, + "svint64x2_t" => quote! { &SVI64X2 }, + "svint64x3_t" => quote! { &SVI64X3 }, + "svint64x4_t" => quote! { &SVI64X4 }, + "svuint8_t" => quote! { &SVU8 }, + "svuint8x2_t" => quote! { &SVU8X2 }, + "svuint8x3_t" => quote! { &SVU8X3 }, + "svuint8x4_t" => quote! { &SVU8X4 }, + "svuint16_t" => quote! { &SVU16 }, + "svuint16x2_t" => quote! { &SVU16X2 }, + "svuint16x3_t" => quote! { &SVU16X3 }, + "svuint16x4_t" => quote! { &SVU16X4 }, + "svuint32_t" => quote! { &SVU32 }, + "svuint32x2_t" => quote! { &SVU32X2 }, + "svuint32x3_t" => quote! { &SVU32X3 }, + "svuint32x4_t" => quote! { &SVU32X4 }, + "svuint64_t" => quote! { &SVU64 }, + "svuint64x2_t" => quote! { &SVU64X2 }, + "svuint64x3_t" => quote! { &SVU64X3 }, + "svuint64x4_t" => quote! { &SVU64X4 }, + "svfloat32_t" => quote! { &SVF32 }, + "svfloat32x2_t" => quote! { &SVF32X2 }, + "svfloat32x3_t" => quote! { &SVF32X3 }, + "svfloat32x4_t" => quote! { &SVF32X4 }, + "svfloat64_t" => quote! { &SVF64 }, + "svfloat64x2_t" => quote! { &SVF64X2 }, + "svfloat64x3_t" => quote! { &SVF64X3 }, + "svfloat64x4_t" => quote! { &SVF64X4 }, + "svprfop" => quote! { &SVPRFOP }, + "svpattern" => quote! { &SVPATTERN }, + // Generic types "T" => quote! { &GENERICT }, "U" => quote! { &GENERICU }, diff --git a/library/stdarch/crates/stdarch-verify/tests/arm.rs b/library/stdarch/crates/stdarch-verify/tests/arm.rs index 86897908e062c..6ba9c17c4804c 100644 --- a/library/stdarch/crates/stdarch-verify/tests/arm.rs +++ b/library/stdarch/crates/stdarch-verify/tests/arm.rs @@ -16,6 +16,7 @@ struct Function { doc: &'static str, } +static BOOL: Type = Type::PrimBool; static F16: Type = Type::PrimFloat(16); static F32: Type = Type::PrimFloat(32); static F64: Type = Type::PrimFloat(64); @@ -28,6 +29,7 @@ static U32: Type = Type::PrimUnsigned(32); static U64: Type = Type::PrimUnsigned(64); static U8: Type = Type::PrimUnsigned(8); static NEVER: Type = Type::Never; +static VOID: Type = Type::Void; static GENERICT: Type = Type::GenericParam("T"); static GENERICU: Type = Type::GenericParam("U"); @@ -151,19 +153,78 @@ static U8X8X2: Type = Type::U(8, 8, 2); static U8X8X3: Type = Type::U(8, 8, 3); static U8X8X4: Type = Type::U(8, 8, 4); +static SVBOOL: Type = Type::Pred(1); +static SVBOOLX2: Type = Type::Pred(2); +static SVBOOLX3: Type = Type::Pred(3); +static SVBOOLX4: Type = Type::Pred(4); +static SVCOUNT: Type = Type::Pred(1); +static SVF16: Type = Type::SVF(16, 1); +static SVF16X2: Type = Type::SVF(16, 2); +static SVF16X3: Type = Type::SVF(16, 3); +static SVF16X4: Type = Type::SVF(16, 4); +static SVF32: Type = Type::SVF(32, 1); +static SVF32X2: Type = Type::SVF(32, 2); +static SVF32X3: Type = Type::SVF(32, 3); +static SVF32X4: Type = Type::SVF(32, 4); +static SVF64: Type = Type::SVF(64, 1); +static SVF64X2: Type = Type::SVF(64, 2); +static SVF64X3: Type = Type::SVF(64, 3); +static SVF64X4: Type = Type::SVF(64, 4); +static SVI8: Type = Type::SVI(8, 1); +static SVI8X2: Type = Type::SVI(8, 2); +static SVI8X3: Type = Type::SVI(8, 3); +static SVI8X4: Type = Type::SVI(8, 4); +static SVI16: Type = Type::SVI(16, 1); +static SVI16X2: Type = Type::SVI(16, 2); +static SVI16X3: Type = Type::SVI(16, 3); +static SVI16X4: Type = Type::SVI(16, 4); +static SVI32: Type = Type::SVI(32, 1); +static SVI32X2: Type = Type::SVI(32, 2); +static SVI32X3: Type = Type::SVI(32, 3); +static SVI32X4: Type = Type::SVI(32, 4); +static SVI64: Type = Type::SVI(64, 1); +static SVI64X2: Type = Type::SVI(64, 2); +static SVI64X3: Type = Type::SVI(64, 3); +static SVI64X4: Type = Type::SVI(64, 4); +static SVU8: Type = Type::SVU(8, 1); +static SVU8X2: Type = Type::SVU(8, 2); +static SVU8X3: Type = Type::SVU(8, 3); +static SVU8X4: Type = Type::SVU(8, 4); +static SVU16: Type = Type::SVU(16, 1); +static SVU16X2: Type = Type::SVU(16, 2); +static SVU16X3: Type = Type::SVU(16, 3); +static SVU16X4: Type = Type::SVU(16, 4); +static SVU32: Type = Type::SVU(32, 1); +static SVU32X2: Type = Type::SVU(32, 2); +static SVU32X3: Type = Type::SVU(32, 3); +static SVU32X4: Type = Type::SVU(32, 4); +static SVU64: Type = Type::SVU(64, 1); +static SVU64X2: Type = Type::SVU(64, 2); +static SVU64X3: Type = Type::SVU(64, 3); +static SVU64X4: Type = Type::SVU(64, 4); +static SVPRFOP: Type = Type::Enum("svprfop"); +static SVPATTERN: Type = Type::Enum("svpattern"); + #[derive(Debug, Copy, Clone, PartialEq)] enum Type { + Void, + PrimBool, PrimFloat(u8), PrimSigned(u8), PrimUnsigned(u8), PrimPoly(u8), MutPtr(&'static Type), ConstPtr(&'static Type), + Enum(&'static str), GenericParam(&'static str), I(u8, u8, u8), U(u8, u8, u8), P(u8, u8, u8), F(u8, u8, u8), + Pred(u8), + SVI(u8, u8), + SVU(u8, u8), + SVF(u8, u8), Never, } @@ -182,231 +243,20 @@ fn verify_all_signatures() { let mut all_valid = true; for rust in FUNCTIONS { + // Most SVE intrinsics just rely on the intrinsics test tool for validation if !rust.has_test { - let skip = [ - "vaddq_s64", - "vaddq_u64", - "vrsqrte_f32", - "vtbl1_s8", - "vtbl1_u8", - "vtbl1_p8", - "vtbl2_s8", - "vtbl2_u8", - "vtbl2_p8", - "vtbl3_s8", - "vtbl3_u8", - "vtbl3_p8", - "vtbl4_s8", - "vtbl4_u8", - "vtbl4_p8", - "vtbx1_s8", - "vtbx1_u8", - "vtbx1_p8", - "vtbx2_s8", - "vtbx2_u8", - "vtbx2_p8", - "vtbx3_s8", - "vtbx3_u8", - "vtbx3_p8", - "vtbx4_s8", - "vtbx4_u8", - "vtbx4_p8", - "udf", - "_clz_u8", - "_clz_u16", - "_clz_u32", - "_rbit_u32", - "_rev_u16", - "_rev_u32", - "__breakpoint", - "vpminq_f32", - "vpminq_f64", - "vpmaxq_f32", - "vpmaxq_f64", - "vcombine_s8", - "vcombine_s16", - "vcombine_s32", - "vcombine_s64", - "vcombine_u8", - "vcombine_u16", - "vcombine_u32", - "vcombine_u64", - "vcombine_p64", - "vcombine_f32", - "vcombine_p8", - "vcombine_p16", - "vcombine_f64", - "vtbl1_s8", - "vtbl1_u8", - "vtbl1_p8", - "vtbl2_s8", - "vtbl2_u8", - "vtbl2_p8", - "vtbl3_s8", - "vtbl3_u8", - "vtbl3_p8", - "vtbl4_s8", - "vtbl4_u8", - "vtbl4_p8", - "vtbx1_s8", - "vtbx1_u8", - "vtbx1_p8", - "vtbx2_s8", - "vtbx2_u8", - "vtbx2_p8", - "vtbx3_s8", - "vtbx3_u8", - "vtbx3_p8", - "vtbx4_s8", - "vtbx4_u8", - "vtbx4_p8", - "vqtbl1_s8", - "vqtbl1q_s8", - "vqtbl1_u8", - "vqtbl1q_u8", - "vqtbl1_p8", - "vqtbl1q_p8", - "vqtbx1_s8", - "vqtbx1q_s8", - "vqtbx1_u8", - "vqtbx1q_u8", - "vqtbx1_p8", - "vqtbx1q_p8", - "vqtbl2_s8", - "vqtbl2q_s8", - "vqtbl2_u8", - "vqtbl2q_u8", - "vqtbl2_p8", - "vqtbl2q_p8", - "vqtbx2_s8", - "vqtbx2q_s8", - "vqtbx2_u8", - "vqtbx2q_u8", - "vqtbx2_p8", - "vqtbx2q_p8", - "vqtbl3_s8", - "vqtbl3q_s8", - "vqtbl3_u8", - "vqtbl3q_u8", - "vqtbl3_p8", - "vqtbl3q_p8", - "vqtbx3_s8", - "vqtbx3q_s8", - "vqtbx3_u8", - "vqtbx3q_u8", - "vqtbx3_p8", - "vqtbx3q_p8", - "vqtbl4_s8", - "vqtbl4q_s8", - "vqtbl4_u8", - "vqtbl4q_u8", - "vqtbl4_p8", - "vqtbl4q_p8", - "vqtbx4_s8", - "vqtbx4q_s8", - "vqtbx4_u8", - "vqtbx4q_u8", - "vqtbx4_p8", - "vqtbx4q_p8", - "brk", - "_rev_u64", - "_clz_u64", - "_rbit_u64", - "_cls_u32", - "_cls_u64", - "_prefetch", - "vsli_n_s8", - "vsliq_n_s8", - "vsli_n_s16", - "vsliq_n_s16", - "vsli_n_s32", - "vsliq_n_s32", - "vsli_n_s64", - "vsliq_n_s64", - "vsli_n_u8", - "vsliq_n_u8", - "vsli_n_u16", - "vsliq_n_u16", - "vsli_n_u32", - "vsliq_n_u32", - "vsli_n_u64", - "vsliq_n_u64", - "vsli_n_p8", - "vsliq_n_p8", - "vsli_n_p16", - "vsliq_n_p16", - "vsli_n_p64", - "vsliq_n_p64", - "vsri_n_s8", - "vsriq_n_s8", - "vsri_n_s16", - "vsriq_n_s16", - "vsri_n_s32", - "vsriq_n_s32", - "vsri_n_s64", - "vsriq_n_s64", - "vsri_n_u8", - "vsriq_n_u8", - "vsri_n_u16", - "vsriq_n_u16", - "vsri_n_u32", - "vsriq_n_u32", - "vsri_n_u64", - "vsriq_n_u64", - "vsri_n_p8", - "vsriq_n_p8", - "vsri_n_p16", - "vsriq_n_p16", - "vsri_n_p64", - "vsriq_n_p64", - "__smulbb", - "__smultb", - "__smulbt", - "__smultt", - "__smulwb", - "__smulwt", - "__qadd", - "__qsub", - "__qdbl", - "__smlabb", - "__smlabt", - "__smlatb", - "__smlatt", - "__smlawb", - "__smlawt", - "__qadd8", - "__qsub8", - "__qsub16", - "__qadd16", - "__qasx", - "__qsax", - "__sadd16", - "__sadd8", - "__smlad", - "__smlsd", - "__sasx", - "__sel", - "__shadd8", - "__shadd16", - "__shsub8", - "__usub8", - "__ssub8", - "__shsub16", - "__smuad", - "__smuadx", - "__smusd", - "__smusdx", - "__usad8", - "__usada8", - "__ldrex", - "__strex", - "__ldrexb", - "__strexb", - "__ldrexh", - "__strexh", - "__clrex", - "__dbg", - ]; + if !SKIP_RUNTIME_TESTS.contains(&rust.name) + // Most run-time tests are handled by the intrinsic-test tool, except for + // load/stores (which have generated tests) + && (!rust.name.starts_with("sv") || rust.name.starts_with("svld") + || rust.name.starts_with("svst")) + // The load/store test generator can't handle these cases yet + && (!rust.name.contains("_u32base_") || rust.name.contains("index") || rust.name.contains("offset")) + && !(rust.name.starts_with("svldff1") && rust.name.contains("gather")) + { + println!("missing run-time test for `{}`", rust.name); + all_valid = false; + } } // Skip some intrinsics that aren't NEON and are located in different @@ -445,6 +295,7 @@ fn verify_all_signatures() { && !rust.file.ends_with("v7.rs\"") && !rust.file.ends_with("v8.rs\"") && !rust.file.ends_with("mte.rs\"") + && !rust.file.ends_with("rand.rs\"") && !rust.file.ends_with("ex.rs\"") && !skip_intrinsic_verify.contains(&rust.name) { @@ -478,12 +329,21 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> { let mut nconst = 0; let iter = rust.arguments.iter().zip(&arm.arguments).enumerate(); for (i, (rust_ty, (arm, arm_const))) in iter { - if *rust_ty != arm { - bail!("mismatched arguments: {rust_ty:?} != {arm:?}") + match (*rust_ty, arm) { + // SVE uses generic type parameters to handle void pointers + (Type::ConstPtr(Type::GenericParam("T")), Type::ConstPtr(Type::Void)) => (), + // SVE const generics use i32 over u64 for usability reasons + (Type::PrimSigned(32), Type::PrimUnsigned(64)) if rust.required_const.contains(&i) => { + () + } + // svset doesn't have its const argument last as we assumed when building the Function + _ if rust.name.starts_with("svset") => (), + (x, y) if x == y => (), + _ => bail!("mismatched arguments: {rust_ty:?} != {arm:?}"), } if *arm_const { nconst += 1; - if !rust.required_const.contains(&i) { + if !rust.required_const.contains(&i) && !rust.name.starts_with("svset") { bail!("argument const mismatch"); } } @@ -492,7 +352,10 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> { bail!("wrong number of const arguments"); } - if rust.instrs.is_empty() { + if rust.instrs.is_empty() + && arm.instruction != "" + && !SKIP_ASSERT_INSTR_TESTS.contains(&rust.name) + { bail!( "instruction not listed for `{}`, but arm lists {:?}", rust.name, @@ -531,7 +394,7 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> { Ok(()) } -#[derive(PartialEq)] +#[derive(Debug, PartialEq)] struct Intrinsic { name: String, ret: Option, @@ -546,7 +409,7 @@ struct JsonIntrinsic { arguments: Vec, return_type: ReturnType, #[serde(default)] - instructions: Vec>, + instructions: Option>>, } #[derive(Deserialize, Debug)] @@ -565,6 +428,8 @@ fn parse_intrinsics(intrinsics: Vec) -> HashMap Intrinsic { let name = intr.name; + // Remove '[' and ']' so that intrinsics of the form `svwhilerw[_s16]` becomes `svwhilerw_s16`. + let name = name.replace('[', "").replace(']', ""); let ret = if intr.return_type.value == "void" { None } else { @@ -573,18 +438,24 @@ fn parse_intrinsic(mut intr: JsonIntrinsic) -> Intrinsic { // This ignores multiple instructions and different optional sequences for now to mimic // the old HTML scraping behaviour - let instruction = intr.instructions.swap_remove(0).swap_remove(0); + let instruction = intr + .instructions + .map_or(String::new(), |mut i| i.swap_remove(0).swap_remove(0)); let arguments = intr .arguments .iter() .map(|s| { - let (ty, konst) = match s.strip_prefix("const") { - Some(stripped) => (stripped.trim_start(), true), - None => (s.as_str(), false), + let ty = if let Some(i) = s.find('*') { + &s[..i + 1] + } else { + s.rsplit_once(' ').unwrap().0.trim_start_matches("const ") }; - let ty = ty.rsplit_once(' ').unwrap().0; - (parse_ty(ty), konst) + let ty = parse_ty(ty); + let konst = s.contains("const") && !matches!(ty, Type::ConstPtr(_)) + || s.starts_with("enum") + || s.rsplit_once(" ").unwrap().1.starts_with("imm"); + (ty, konst) }) .collect::>(); @@ -597,18 +468,27 @@ fn parse_intrinsic(mut intr: JsonIntrinsic) -> Intrinsic { } fn parse_ty(s: &str) -> Type { - let suffix = " const *"; - if let Some(base) = s.strip_suffix(suffix) { - Type::ConstPtr(parse_ty_base(base)) - } else if let Some(base) = s.strip_suffix(" *") { - Type::MutPtr(parse_ty_base(base)) + if let Some(ty) = s.strip_suffix("*") { + let ty = ty.trim(); + if let Some(ty) = ty.strip_prefix("const") { + // SVE intrinsics are west-const (`const int8_t *`) + Type::ConstPtr(parse_ty_base(ty)) + } else if let Some(ty) = ty.strip_suffix("const") { + // Neon intrinsics are east-const (`int8_t const *`) + Type::ConstPtr(parse_ty_base(ty)) + } else { + Type::MutPtr(parse_ty_base(ty)) + } } else { *parse_ty_base(s) } } fn parse_ty_base(s: &str) -> &'static Type { + let s = s.trim(); match s { + "bool" => &BOOL, + "void" => &VOID, "float16_t" => &F16, "float16x4_t" => &F16X4, "float16x4x2_t" => &F16X4X2, @@ -738,7 +618,4655 @@ fn parse_ty_base(s: &str) -> &'static Type { "uint8x8x2_t" => &U8X8X2, "uint8x8x3_t" => &U8X8X3, "uint8x8x4_t" => &U8X8X4, + "svbool_t" => &SVBOOL, + "svboolx2_t" => &SVBOOLX2, + "svboolx3_t" => &SVBOOLX3, + "svboolx4_t" => &SVBOOLX4, + "svcount_t" => &SVCOUNT, + "svfloat16_t" => &SVF16, + "svfloat16x2_t" => &SVF16X2, + "svfloat16x3_t" => &SVF16X3, + "svfloat16x4_t" => &SVF16X4, + "svfloat32_t" => &SVF32, + "svfloat32x2_t" => &SVF32X2, + "svfloat32x3_t" => &SVF32X3, + "svfloat32x4_t" => &SVF32X4, + "svfloat64_t" => &SVF64, + "svfloat64x2_t" => &SVF64X2, + "svfloat64x3_t" => &SVF64X3, + "svfloat64x4_t" => &SVF64X4, + "svint8_t" => &SVI8, + "svint8x2_t" => &SVI8X2, + "svint8x3_t" => &SVI8X3, + "svint8x4_t" => &SVI8X4, + "svint16_t" => &SVI16, + "svint16x2_t" => &SVI16X2, + "svint16x3_t" => &SVI16X3, + "svint16x4_t" => &SVI16X4, + "svint32_t" => &SVI32, + "svint32x2_t" => &SVI32X2, + "svint32x3_t" => &SVI32X3, + "svint32x4_t" => &SVI32X4, + "svint64_t" => &SVI64, + "svint64x2_t" => &SVI64X2, + "svint64x3_t" => &SVI64X3, + "svint64x4_t" => &SVI64X4, + "svuint8_t" => &SVU8, + "svuint8x2_t" => &SVU8X2, + "svuint8x3_t" => &SVU8X3, + "svuint8x4_t" => &SVU8X4, + "svuint16_t" => &SVU16, + "svuint16x2_t" => &SVU16X2, + "svuint16x3_t" => &SVU16X3, + "svuint16x4_t" => &SVU16X4, + "svuint32_t" => &SVU32, + "svuint32x2_t" => &SVU32X2, + "svuint32x3_t" => &SVU32X3, + "svuint32x4_t" => &SVU32X4, + "svuint64_t" => &SVU64, + "svuint64x2_t" => &SVU64X2, + "svuint64x3_t" => &SVU64X3, + "svuint64x4_t" => &SVU64X4, + "enum svprfop" => &SVPRFOP, + "enum svpattern" => &SVPATTERN, _ => panic!("failed to parse json type {s:?}"), } } + +// FIXME(arm-maintainers): Some tests require new rustc intrinsics in order to generate +// the appropriate instruction, though they do have the correct behaviour - these will be fixed +// but are disabled for now. +static SKIP_ASSERT_INSTR_TESTS: &'static [&'static str] = &["svpfalse_b"]; + +// FIXME(arm-maintainers): With the advent of the `intrinsic-test` tool, new tests of this kind +// are no longer being added and just adding to this list indefinitely isn't the best solution for +// dealing with that. +static SKIP_RUNTIME_TESTS: &'static [&'static str] = &[ + "vaddq_s64", + "vaddq_u64", + "vrsqrte_f32", + "vtbl1_s8", + "vtbl1_u8", + "vtbl1_p8", + "vtbl2_s8", + "vtbl2_u8", + "vtbl2_p8", + "vtbl3_s8", + "vtbl3_u8", + "vtbl3_p8", + "vtbl4_s8", + "vtbl4_u8", + "vtbl4_p8", + "vtbx1_s8", + "vtbx1_u8", + "vtbx1_p8", + "vtbx2_s8", + "vtbx2_u8", + "vtbx2_p8", + "vtbx3_s8", + "vtbx3_u8", + "vtbx3_p8", + "vtbx4_s8", + "vtbx4_u8", + "vtbx4_p8", + "udf", + "_clz_u8", + "_clz_u16", + "_clz_u32", + "_rbit_u32", + "_rev_u16", + "_rev_u32", + "__breakpoint", + "vpminq_f32", + "vpminq_f64", + "vpmaxq_f32", + "vpmaxq_f64", + "vcombine_s8", + "vcombine_s16", + "vcombine_s32", + "vcombine_s64", + "vcombine_u8", + "vcombine_u16", + "vcombine_u32", + "vcombine_u64", + "vcombine_p64", + "vcombine_f32", + "vcombine_p8", + "vcombine_p16", + "vcombine_f64", + "vtbl1_s8", + "vtbl1_u8", + "vtbl1_p8", + "vtbl2_s8", + "vtbl2_u8", + "vtbl2_p8", + "vtbl3_s8", + "vtbl3_u8", + "vtbl3_p8", + "vtbl4_s8", + "vtbl4_u8", + "vtbl4_p8", + "vtbx1_s8", + "vtbx1_u8", + "vtbx1_p8", + "vtbx2_s8", + "vtbx2_u8", + "vtbx2_p8", + "vtbx3_s8", + "vtbx3_u8", + "vtbx3_p8", + "vtbx4_s8", + "vtbx4_u8", + "vtbx4_p8", + "vqtbl1_s8", + "vqtbl1q_s8", + "vqtbl1_u8", + "vqtbl1q_u8", + "vqtbl1_p8", + "vqtbl1q_p8", + "vqtbx1_s8", + "vqtbx1q_s8", + "vqtbx1_u8", + "vqtbx1q_u8", + "vqtbx1_p8", + "vqtbx1q_p8", + "vqtbl2_s8", + "vqtbl2q_s8", + "vqtbl2_u8", + "vqtbl2q_u8", + "vqtbl2_p8", + "vqtbl2q_p8", + "vqtbx2_s8", + "vqtbx2q_s8", + "vqtbx2_u8", + "vqtbx2q_u8", + "vqtbx2_p8", + "vqtbx2q_p8", + "vqtbl3_s8", + "vqtbl3q_s8", + "vqtbl3_u8", + "vqtbl3q_u8", + "vqtbl3_p8", + "vqtbl3q_p8", + "vqtbx3_s8", + "vqtbx3q_s8", + "vqtbx3_u8", + "vqtbx3q_u8", + "vqtbx3_p8", + "vqtbx3q_p8", + "vqtbl4_s8", + "vqtbl4q_s8", + "vqtbl4_u8", + "vqtbl4q_u8", + "vqtbl4_p8", + "vqtbl4q_p8", + "vqtbx4_s8", + "vqtbx4q_s8", + "vqtbx4_u8", + "vqtbx4q_u8", + "vqtbx4_p8", + "vqtbx4q_p8", + "brk", + "_rev_u64", + "_clz_u64", + "_rbit_u64", + "_cls_u32", + "_cls_u64", + "_prefetch", + "vsli_n_s8", + "vsliq_n_s8", + "vsli_n_s16", + "vsliq_n_s16", + "vsli_n_s32", + "vsliq_n_s32", + "vsli_n_s64", + "vsliq_n_s64", + "vsli_n_u8", + "vsliq_n_u8", + "vsli_n_u16", + "vsliq_n_u16", + "vsli_n_u32", + "vsliq_n_u32", + "vsli_n_u64", + "vsliq_n_u64", + "vsli_n_p8", + "vsliq_n_p8", + "vsli_n_p16", + "vsliq_n_p16", + "vsli_n_p64", + "vsliq_n_p64", + "vsri_n_s8", + "vsriq_n_s8", + "vsri_n_s16", + "vsriq_n_s16", + "vsri_n_s32", + "vsriq_n_s32", + "vsri_n_s64", + "vsriq_n_s64", + "vsri_n_u8", + "vsriq_n_u8", + "vsri_n_u16", + "vsriq_n_u16", + "vsri_n_u32", + "vsriq_n_u32", + "vsri_n_u64", + "vsriq_n_u64", + "vsri_n_p8", + "vsriq_n_p8", + "vsri_n_p16", + "vsriq_n_p16", + "vsri_n_p64", + "vsriq_n_p64", + "__smulbb", + "__smultb", + "__smulbt", + "__smultt", + "__smulwb", + "__smulwt", + "__qadd", + "__qsub", + "__qdbl", + "__smlabb", + "__smlabt", + "__smlatb", + "__smlatt", + "__smlawb", + "__smlawt", + "__qadd8", + "__qsub8", + "__qsub16", + "__qadd16", + "__qasx", + "__qsax", + "__sadd16", + "__sadd8", + "__smlad", + "__smlsd", + "__sasx", + "__sel", + "__shadd8", + "__shadd16", + "__shsub8", + "__usub8", + "__ssub8", + "__shsub16", + "__smuad", + "__smuadx", + "__smusd", + "__smusdx", + "__usad8", + "__usada8", + "__ldrex", + "__strex", + "__ldrexb", + "__strexb", + "__ldrexh", + "__strexh", + "__clrex", + "__dbg", + "__crc32cd", + "__crc32d", + "__jcvt", + "vabal_high_s8", + "vabal_high_s16", + "vabal_high_s32", + "vabal_high_u8", + "vabal_high_u16", + "vabal_high_u32", + "vabd_f64", + "vabdq_f64", + "vabdd_f64", + "vabds_f32", + "vabdh_f16", + "vabdl_high_s16", + "vabdl_high_s32", + "vabdl_high_s8", + "vabdl_high_u8", + "vabdl_high_u16", + "vabdl_high_u32", + "vabs_f64", + "vabsq_f64", + "vabs_s64", + "vabsq_s64", + "vabsd_s64", + "vaddlv_s16", + "vaddlvq_s16", + "vaddlvq_s32", + "vaddlv_s32", + "vaddlv_s8", + "vaddlvq_s8", + "vaddlv_u16", + "vaddlvq_u16", + "vaddlvq_u32", + "vaddlv_u32", + "vaddlv_u8", + "vaddlvq_u8", + "vaddv_f32", + "vaddvq_f32", + "vaddvq_f64", + "vaddv_s32", + "vaddv_s8", + "vaddvq_s8", + "vaddv_s16", + "vaddvq_s16", + "vaddvq_s32", + "vaddv_u32", + "vaddv_u8", + "vaddvq_u8", + "vaddv_u16", + "vaddvq_u16", + "vaddvq_u32", + "vaddvq_s64", + "vaddvq_u64", + "vamax_f16", + "vamaxq_f16", + "vamax_f32", + "vamaxq_f32", + "vamaxq_f64", + "vamin_f16", + "vaminq_f16", + "vamin_f32", + "vaminq_f32", + "vaminq_f64", + "vbcaxq_s8", + "vbcaxq_s16", + "vbcaxq_s32", + "vbcaxq_s64", + "vbcaxq_u8", + "vbcaxq_u16", + "vbcaxq_u32", + "vbcaxq_u64", + "vcadd_rot270_f16", + "vcaddq_rot270_f16", + "vcadd_rot270_f32", + "vcaddq_rot270_f32", + "vcaddq_rot270_f64", + "vcadd_rot90_f16", + "vcaddq_rot90_f16", + "vcadd_rot90_f32", + "vcaddq_rot90_f32", + "vcaddq_rot90_f64", + "vcage_f64", + "vcageq_f64", + "vcaged_f64", + "vcages_f32", + "vcageh_f16", + "vcagt_f64", + "vcagtq_f64", + "vcagtd_f64", + "vcagts_f32", + "vcagth_f16", + "vcale_f64", + "vcaleq_f64", + "vcaled_f64", + "vcales_f32", + "vcaleh_f16", + "vcalt_f64", + "vcaltq_f64", + "vcaltd_f64", + "vcalts_f32", + "vcalth_f16", + "vceq_f64", + "vceqq_f64", + "vceq_s64", + "vceqq_s64", + "vceq_u64", + "vceqq_u64", + "vceq_p64", + "vceqq_p64", + "vceqd_f64", + "vceqs_f32", + "vceqd_s64", + "vceqd_u64", + "vceqh_f16", + "vceqz_f16", + "vceqzq_f16", + "vceqz_f32", + "vceqzq_f32", + "vceqz_f64", + "vceqzq_f64", + "vceqz_s8", + "vceqzq_s8", + "vceqz_s16", + "vceqzq_s16", + "vceqz_s32", + "vceqzq_s32", + "vceqz_s64", + "vceqzq_s64", + "vceqz_p8", + "vceqzq_p8", + "vceqz_p64", + "vceqzq_p64", + "vceqz_u8", + "vceqzq_u8", + "vceqz_u16", + "vceqzq_u16", + "vceqz_u32", + "vceqzq_u32", + "vceqz_u64", + "vceqzq_u64", + "vceqzd_s64", + "vceqzd_u64", + "vceqzh_f16", + "vceqzs_f32", + "vceqzd_f64", + "vcge_f64", + "vcgeq_f64", + "vcge_s64", + "vcgeq_s64", + "vcge_u64", + "vcgeq_u64", + "vcged_f64", + "vcges_f32", + "vcged_s64", + "vcged_u64", + "vcgeh_f16", + "vcgez_f32", + "vcgezq_f32", + "vcgez_f64", + "vcgezq_f64", + "vcgez_s8", + "vcgezq_s8", + "vcgez_s16", + "vcgezq_s16", + "vcgez_s32", + "vcgezq_s32", + "vcgez_s64", + "vcgezq_s64", + "vcgezd_f64", + "vcgezs_f32", + "vcgezd_s64", + "vcgezh_f16", + "vcgt_f64", + "vcgtq_f64", + "vcgt_s64", + "vcgtq_s64", + "vcgt_u64", + "vcgtq_u64", + "vcgtd_f64", + "vcgts_f32", + "vcgtd_s64", + "vcgtd_u64", + "vcgth_f16", + "vcgtz_f32", + "vcgtzq_f32", + "vcgtz_f64", + "vcgtzq_f64", + "vcgtz_s8", + "vcgtzq_s8", + "vcgtz_s16", + "vcgtzq_s16", + "vcgtz_s32", + "vcgtzq_s32", + "vcgtz_s64", + "vcgtzq_s64", + "vcgtzd_f64", + "vcgtzs_f32", + "vcgtzd_s64", + "vcgtzh_f16", + "vcle_f64", + "vcleq_f64", + "vcle_s64", + "vcleq_s64", + "vcle_u64", + "vcleq_u64", + "vcled_f64", + "vcles_f32", + "vcled_u64", + "vcled_s64", + "vcleh_f16", + "vclez_f32", + "vclezq_f32", + "vclez_f64", + "vclezq_f64", + "vclez_s8", + "vclezq_s8", + "vclez_s16", + "vclezq_s16", + "vclez_s32", + "vclezq_s32", + "vclez_s64", + "vclezq_s64", + "vclezd_f64", + "vclezs_f32", + "vclezd_s64", + "vclezh_f16", + "vclt_f64", + "vcltq_f64", + "vclt_s64", + "vcltq_s64", + "vclt_u64", + "vcltq_u64", + "vcltd_u64", + "vcltd_s64", + "vclth_f16", + "vclts_f32", + "vcltd_f64", + "vcltz_f32", + "vcltzq_f32", + "vcltz_f64", + "vcltzq_f64", + "vcltz_s8", + "vcltzq_s8", + "vcltz_s16", + "vcltzq_s16", + "vcltz_s32", + "vcltzq_s32", + "vcltz_s64", + "vcltzq_s64", + "vcltzd_f64", + "vcltzs_f32", + "vcltzd_s64", + "vcltzh_f16", + "vcmla_f16", + "vcmlaq_f16", + "vcmla_f32", + "vcmlaq_f32", + "vcmlaq_f64", + "vcmla_lane_f16", + "vcmlaq_lane_f16", + "vcmla_lane_f32", + "vcmlaq_lane_f32", + "vcmla_laneq_f16", + "vcmlaq_laneq_f16", + "vcmla_laneq_f32", + "vcmlaq_laneq_f32", + "vcmla_rot180_f16", + "vcmlaq_rot180_f16", + "vcmla_rot180_f32", + "vcmlaq_rot180_f32", + "vcmlaq_rot180_f64", + "vcmla_rot180_lane_f16", + "vcmlaq_rot180_lane_f16", + "vcmla_rot180_lane_f32", + "vcmlaq_rot180_lane_f32", + "vcmla_rot180_laneq_f16", + "vcmlaq_rot180_laneq_f16", + "vcmla_rot180_laneq_f32", + "vcmlaq_rot180_laneq_f32", + "vcmla_rot270_f16", + "vcmlaq_rot270_f16", + "vcmla_rot270_f32", + "vcmlaq_rot270_f32", + "vcmlaq_rot270_f64", + "vcmla_rot270_lane_f16", + "vcmlaq_rot270_lane_f16", + "vcmla_rot270_lane_f32", + "vcmlaq_rot270_lane_f32", + "vcmla_rot270_laneq_f16", + "vcmlaq_rot270_laneq_f16", + "vcmla_rot270_laneq_f32", + "vcmlaq_rot270_laneq_f32", + "vcmla_rot90_f16", + "vcmlaq_rot90_f16", + "vcmla_rot90_f32", + "vcmlaq_rot90_f32", + "vcmlaq_rot90_f64", + "vcmla_rot90_lane_f16", + "vcmlaq_rot90_lane_f16", + "vcmla_rot90_lane_f32", + "vcmlaq_rot90_lane_f32", + "vcmla_rot90_laneq_f16", + "vcmlaq_rot90_laneq_f16", + "vcmla_rot90_laneq_f32", + "vcmlaq_rot90_laneq_f32", + "vcopy_lane_f32", + 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+ "vmulx_lane_f32", + "vmulx_laneq_f32", + "vmulxq_lane_f32", + "vmulxq_laneq_f32", + "vmulxq_laneq_f64", + "vmulx_lane_f64", + "vmulx_laneq_f64", + "vmulx_n_f16", + "vmulxq_n_f16", + "vmulxd_f64", + "vmulxs_f32", + "vmulxd_lane_f64", + "vmulxd_laneq_f64", + "vmulxs_lane_f32", + "vmulxs_laneq_f32", + "vmulxh_f16", + "vmulxh_lane_f16", + "vmulxh_laneq_f16", + "vmulxq_lane_f64", + "vneg_f64", + "vnegq_f64", + "vneg_s64", + "vnegq_s64", + "vnegd_s64", + "vnegh_f16", + "vpaddd_f64", + "vpadds_f32", + "vpaddd_s64", + "vpaddd_u64", + "vpaddq_f16", + "vpaddq_f32", + "vpaddq_f64", + "vpaddq_s8", + "vpaddq_s16", + "vpaddq_s32", + "vpaddq_s64", + "vpaddq_u8", + "vpaddq_u16", + "vpaddq_u32", + "vpaddq_u64", + "vpmax_f16", + "vpmaxq_f16", + "vpmaxnm_f16", + "vpmaxnmq_f16", + "vpmaxnm_f32", + "vpmaxnmq_f32", + "vpmaxnmq_f64", + "vpmaxnmqd_f64", + "vpmaxnms_f32", + "vpmaxq_s8", + "vpmaxq_s16", + "vpmaxq_s32", + "vpmaxq_u8", + "vpmaxq_u16", + "vpmaxq_u32", + "vpmaxqd_f64", + "vpmaxs_f32", + "vpmin_f16", + "vpminq_f16", + "vpminnm_f16", + "vpminnmq_f16", + "vpminnm_f32", + "vpminnmq_f32", + "vpminnmq_f64", + "vpminnmqd_f64", + "vpminnms_f32", + "vpminq_s8", + "vpminq_s16", + "vpminq_s32", + "vpminq_u8", + "vpminq_u16", + "vpminq_u32", + "vpminqd_f64", + "vpmins_f32", + "vqabs_s64", + "vqabsq_s64", + "vqabsb_s8", + "vqabsh_s16", + "vqabss_s32", + "vqabsd_s64", + "vqaddb_s8", + "vqaddh_s16", + "vqaddb_u8", + "vqaddh_u16", + "vqadds_s32", + "vqaddd_s64", + "vqadds_u32", + "vqaddd_u64", + "vqdmlal_high_lane_s16", + "vqdmlal_high_laneq_s16", + "vqdmlal_high_lane_s32", + "vqdmlal_high_laneq_s32", + "vqdmlal_high_n_s16", + "vqdmlal_high_s16", + "vqdmlal_high_n_s32", + "vqdmlal_high_s32", + "vqdmlal_laneq_s16", + "vqdmlal_laneq_s32", + "vqdmlalh_lane_s16", + "vqdmlalh_laneq_s16", + "vqdmlals_lane_s32", + "vqdmlals_laneq_s32", + "vqdmlalh_s16", + "vqdmlals_s32", + "vqdmlsl_high_lane_s16", + "vqdmlsl_high_laneq_s16", + "vqdmlsl_high_lane_s32", + "vqdmlsl_high_laneq_s32", + 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"vqshlb_u8", + "vqshlh_u16", + "vqshls_u32", + "vqshld_s64", + "vqshld_u64", + "vqshlub_n_s8", + "vqshlud_n_s64", + "vqshluh_n_s16", + "vqshlus_n_s32", + "vqshrn_high_n_s16", + "vqshrn_high_n_s32", + "vqshrn_high_n_s64", + "vqshrn_high_n_u16", + "vqshrn_high_n_u32", + "vqshrn_high_n_u64", + "vqshrnd_n_s64", + "vqshrnd_n_u64", + "vqshrnh_n_s16", + "vqshrns_n_s32", + "vqshrnh_n_u16", + "vqshrns_n_u32", + "vqshrun_high_n_s16", + "vqshrun_high_n_s32", + "vqshrun_high_n_s64", + "vqshrund_n_s64", + "vqshrunh_n_s16", + "vqshruns_n_s32", + "vqsubb_s8", + "vqsubh_s16", + "vqsubb_u8", + "vqsubh_u16", + "vqsubs_s32", + "vqsubd_s64", + "vqsubs_u32", + "vqsubd_u64", + "vrax1q_u64", + "vrbit_s8", + "vrbitq_s8", + "vrbit_u8", + "vrbit_u8", + "vrbitq_u8", + "vrbitq_u8", + "vrbit_p8", + "vrbit_p8", + "vrbitq_p8", + "vrbitq_p8", + "vrecpe_f64", + "vrecpeq_f64", + "vrecped_f64", + "vrecpes_f32", + "vrecpeh_f16", + "vrecps_f64", + "vrecpsq_f64", + "vrecpsd_f64", + "vrecpss_f32", + "vrecpsh_f16", + "vrecpxd_f64", + "vrecpxs_f32", + "vrecpxh_f16", + "vreinterpret_f64_f16", + "vreinterpret_f64_f16", + "vreinterpretq_f64_f16", + "vreinterpretq_f64_f16", + "vreinterpret_f16_f64", + "vreinterpret_f16_f64", + "vreinterpretq_f16_f64", + "vreinterpretq_f16_f64", + "vreinterpretq_f64_p128", + "vreinterpretq_f64_p128", + "vreinterpret_f64_f32", + "vreinterpret_f64_f32", + "vreinterpret_p64_f32", + "vreinterpret_p64_f32", + "vreinterpretq_f64_f32", + "vreinterpretq_f64_f32", + "vreinterpretq_p64_f32", + "vreinterpretq_p64_f32", + "vreinterpret_f32_f64", + "vreinterpret_f32_f64", + "vreinterpret_s8_f64", + "vreinterpret_s8_f64", + "vreinterpret_s16_f64", + "vreinterpret_s16_f64", + "vreinterpret_s32_f64", + "vreinterpret_s32_f64", + "vreinterpret_s64_f64", + "vreinterpret_u8_f64", + "vreinterpret_u8_f64", + "vreinterpret_u16_f64", + "vreinterpret_u16_f64", + "vreinterpret_u32_f64", + "vreinterpret_u32_f64", + "vreinterpret_u64_f64", + "vreinterpret_p8_f64", + "vreinterpret_p8_f64", + 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"vreinterpret_f64_s32", + "vreinterpret_f64_s32", + "vreinterpretq_f64_s32", + "vreinterpretq_f64_s32", + "vreinterpret_f64_s64", + "vreinterpret_p64_s64", + "vreinterpretq_f64_s64", + "vreinterpretq_f64_s64", + "vreinterpretq_p64_s64", + "vreinterpretq_p64_s64", + "vreinterpret_f64_u8", + "vreinterpret_f64_u8", + "vreinterpretq_f64_u8", + "vreinterpretq_f64_u8", + "vreinterpret_f64_u16", + "vreinterpret_f64_u16", + "vreinterpretq_f64_u16", + "vreinterpretq_f64_u16", + "vreinterpret_f64_u32", + "vreinterpret_f64_u32", + "vreinterpretq_f64_u32", + "vreinterpretq_f64_u32", + "vreinterpret_f64_u64", + "vreinterpret_p64_u64", + "vreinterpretq_f64_u64", + "vreinterpretq_f64_u64", + "vreinterpretq_p64_u64", + "vreinterpretq_p64_u64", + "vreinterpret_f64_p8", + "vreinterpret_f64_p8", + "vreinterpretq_f64_p8", + "vreinterpretq_f64_p8", + "vreinterpret_f64_p16", + "vreinterpret_f64_p16", + "vreinterpretq_f64_p16", + "vreinterpretq_f64_p16", + "vreinterpret_f32_p64", + "vreinterpret_f32_p64", + "vreinterpret_f64_p64", + "vreinterpret_s64_p64", + "vreinterpret_u64_p64", + "vreinterpretq_f32_p64", + "vreinterpretq_f32_p64", + "vreinterpretq_f64_p64", + "vreinterpretq_f64_p64", + "vreinterpretq_s64_p64", + "vreinterpretq_s64_p64", + "vreinterpretq_u64_p64", + "vreinterpretq_u64_p64", + "vrnd32x_f32", + "vrnd32xq_f32", + "vrnd32xq_f64", + "vrnd32x_f64", + "vrnd32z_f32", + "vrnd32zq_f32", + "vrnd32zq_f64", + "vrnd32z_f64", + "vrnd64x_f32", + "vrnd64xq_f32", + "vrnd64xq_f64", + "vrnd64x_f64", + "vrnd64z_f32", + "vrnd64zq_f32", + "vrnd64zq_f64", + "vrnd64z_f64", + "vrnd_f16", + "vrndq_f16", + "vrnd_f32", + "vrndq_f32", + "vrnd_f64", + "vrndq_f64", + "vrnda_f16", + "vrndaq_f16", + "vrnda_f32", + "vrndaq_f32", + "vrnda_f64", + "vrndaq_f64", + "vrndah_f16", + "vrndh_f16", + "vrndi_f16", + "vrndiq_f16", + "vrndi_f32", + "vrndiq_f32", + "vrndi_f64", + "vrndiq_f64", + "vrndih_f16", + "vrndm_f16", + "vrndmq_f16", + "vrndm_f32", + "vrndmq_f32", + "vrndm_f64", + "vrndmq_f64", + "vrndmh_f16", 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"vextq_s16", + "vext_u8", + "vextq_u16", + "vext_p8", + "vextq_p16", + "vextq_f16", + "vextq_f32", + "vext_s16", + "vextq_s32", + "vext_u16", + "vextq_u32", + "vext_p16", + "vextq_s64", + "vextq_u64", + "vextq_s8", + "vextq_u8", + "vextq_p8", + "vfma_f16", + "vfmaq_f16", + "vfma_f32", + "vfmaq_f32", + "vfma_n_f32", + "vfmaq_n_f32", + "vfms_f16", + "vfmsq_f16", + "vfms_f32", + "vfmsq_f32", + "vfms_n_f32", + "vfmsq_n_f32", + "vget_high_f16", + "vget_low_f16", + "vget_lane_f16", + "vgetq_lane_f16", + "vld1_dup_f16", + "vld1q_dup_f16", + "vld1_f16", + "vld1_f16", + "vld1q_f16", + "vld1q_f16", + "vld1_f16_x2", + "vld1_f16_x3", + "vld1_f16_x4", + "vld1q_f16_x2", + "vld1q_f16_x3", + "vld1q_f16_x4", + "vld1_f32_x2", + "vld1_f32_x3", + "vld1_f32_x4", + "vld1q_f32_x2", + "vld1q_f32_x3", + "vld1q_f32_x4", + "vld1_lane_f16", + "vld1q_lane_f16", + "vld1_p64_x2", + "vld1_p64_x3", + "vld1_p64_x4", + "vld1q_p64_x2", + "vld1q_p64_x3", + "vld1q_p64_x4", + "vld1_s8_x2", + "vld1_s8_x3", + "vld1_s8_x4", + "vld1q_s8_x2", + "vld1q_s8_x3", + "vld1q_s8_x4", + "vld1_s16_x2", + "vld1_s16_x3", + "vld1_s16_x4", + "vld1q_s16_x2", + "vld1q_s16_x3", + "vld1q_s16_x4", + "vld1_s32_x2", + "vld1_s32_x3", + "vld1_s32_x4", + "vld1q_s32_x2", + "vld1q_s32_x3", + "vld1q_s32_x4", + "vld1_s64_x2", + "vld1_s64_x3", + "vld1_s64_x4", + "vld1q_s64_x2", + "vld1q_s64_x3", + "vld1q_s64_x4", + "vld1_u8_x2", + "vld1_u8_x3", + "vld1_u8_x4", + "vld1q_u8_x2", + "vld1q_u8_x3", + "vld1q_u8_x4", + "vld1_u16_x2", + "vld1_u16_x3", + "vld1_u16_x4", + "vld1q_u16_x2", + "vld1q_u16_x3", + "vld1q_u16_x4", + "vld1_u32_x2", + "vld1_u32_x3", + "vld1_u32_x4", + "vld1q_u32_x2", + "vld1q_u32_x3", + "vld1q_u32_x4", + "vld1_u64_x2", + "vld1_u64_x3", + "vld1_u64_x4", + "vld1q_u64_x2", + "vld1q_u64_x3", + "vld1q_u64_x4", + "vld1_p8_x2", + "vld1_p8_x3", + "vld1_p8_x4", + "vld1q_p8_x2", + "vld1q_p8_x3", + "vld1q_p8_x4", + "vld1_p16_x2", + "vld1_p16_x3", + "vld1_p16_x4", + "vld1q_p16_x2", + "vld1q_p16_x3", + "vld1q_p16_x4", + "vld2_dup_f16", + "vld2q_dup_f16", + "vld2_dup_f16", + "vld2q_dup_f16", + "vld2_dup_f32", + "vld2q_dup_f32", + "vld2_dup_s8", + "vld2q_dup_s8", + "vld2_dup_s16", + "vld2q_dup_s16", + "vld2_dup_s32", + "vld2q_dup_s32", + "vld2_dup_f32", + "vld2q_dup_f32", + "vld2_dup_s8", + "vld2q_dup_s8", + "vld2_dup_s16", + "vld2q_dup_s16", + "vld2_dup_s32", + "vld2q_dup_s32", + "vld2_dup_p64", + "vld2_dup_s64", + "vld2_dup_s64", + "vld2_dup_u64", + "vld2_dup_u8", + "vld2_dup_u8", + "vld2q_dup_u8", + "vld2q_dup_u8", + "vld2_dup_u16", + "vld2_dup_u16", + "vld2q_dup_u16", + "vld2q_dup_u16", + "vld2_dup_u32", + "vld2_dup_u32", + "vld2q_dup_u32", + "vld2q_dup_u32", + "vld2_dup_p8", + "vld2_dup_p8", + "vld2q_dup_p8", + "vld2q_dup_p8", + "vld2_dup_p16", + "vld2_dup_p16", + "vld2q_dup_p16", + "vld2q_dup_p16", + "vld2_f16", + "vld2q_f16", + "vld2_f16", + "vld2q_f16", + "vld2_f32", + "vld2q_f32", + "vld2_s8", + "vld2q_s8", + "vld2_s16", + "vld2q_s16", + "vld2_s32", + "vld2q_s32", + "vld2_f32", + "vld2q_f32", + "vld2_s8", + "vld2q_s8", + "vld2_s16", + "vld2q_s16", + "vld2_s32", + "vld2q_s32", + "vld2_lane_f16", + "vld2q_lane_f16", + "vld2_lane_f16", + "vld2q_lane_f16", + "vld2_lane_f32", + "vld2q_lane_f32", + "vld2_lane_s8", + "vld2_lane_s16", + "vld2q_lane_s16", + "vld2_lane_s32", + "vld2q_lane_s32", + "vld2_lane_f32", + "vld2q_lane_f32", + "vld2q_lane_s16", + "vld2q_lane_s32", + "vld2_lane_s8", + "vld2_lane_s16", + "vld2_lane_s32", + "vld2_lane_u8", + "vld2_lane_u16", + "vld2q_lane_u16", + "vld2_lane_u32", + "vld2q_lane_u32", + "vld2_lane_p8", + "vld2_lane_p16", + "vld2q_lane_p16", + "vld2_p64", + "vld2_s64", + "vld2_s64", + "vld2_u64", + "vld2_u8", + "vld2q_u8", + "vld2_u16", + "vld2q_u16", + "vld2_u32", + "vld2q_u32", + "vld2_p8", + "vld2q_p8", + "vld2_p16", + "vld2q_p16", + "vld3_dup_f16", + "vld3q_dup_f16", + "vld3_dup_f16", + "vld3q_dup_f16", + "vld3_dup_f32", + "vld3q_dup_f32", + "vld3_dup_s8", + "vld3q_dup_s8", + "vld3_dup_s16", + "vld3q_dup_s16", + "vld3_dup_s32", + "vld3q_dup_s32", + "vld3_dup_s64", + "vld3_dup_f32", + "vld3q_dup_f32", + "vld3_dup_s8", + "vld3q_dup_s8", + "vld3_dup_s16", + "vld3q_dup_s16", + "vld3_dup_s32", + "vld3q_dup_s32", + "vld3_dup_p64", + "vld3_dup_s64", + "vld3_dup_u64", + "vld3_dup_u8", + "vld3_dup_u8", + "vld3q_dup_u8", + "vld3q_dup_u8", + "vld3_dup_u16", + "vld3_dup_u16", + "vld3q_dup_u16", + "vld3q_dup_u16", + "vld3_dup_u32", + "vld3_dup_u32", + "vld3q_dup_u32", + "vld3q_dup_u32", + "vld3_dup_p8", + "vld3_dup_p8", + "vld3q_dup_p8", + "vld3q_dup_p8", + "vld3_dup_p16", + "vld3_dup_p16", + "vld3q_dup_p16", + "vld3q_dup_p16", + "vld3_f16", + "vld3q_f16", + "vld3_f16", + "vld3q_f16", + "vld3_f32", + "vld3q_f32", + "vld3_s8", + "vld3q_s8", + "vld3_s16", + "vld3q_s16", + "vld3_s32", + "vld3q_s32", + "vld3_f32", + "vld3q_f32", + "vld3_s8", + "vld3q_s8", + "vld3_s16", + "vld3q_s16", + "vld3_s32", + "vld3q_s32", + "vld3_lane_f16", + "vld3q_lane_f16", + "vld3_lane_f16", + "vld3q_lane_f16", + "vld3_lane_f32", + "vld3q_lane_f32", + "vld3_lane_f32", + "vld3_lane_s8", + "vld3_lane_s16", + "vld3q_lane_s16", + "vld3_lane_s32", + "vld3q_lane_s32", + "vld3_lane_s8", + "vld3_lane_s16", + "vld3q_lane_s16", + "vld3_lane_s32", + "vld3q_lane_s32", + "vld3_lane_u8", + "vld3_lane_u16", + "vld3q_lane_u16", + "vld3_lane_u32", + "vld3q_lane_u32", + "vld3_lane_p8", + "vld3_lane_p16", + "vld3q_lane_p16", + "vld3_p64", + "vld3_s64", + "vld3_s64", + "vld3_u64", + "vld3_u8", + "vld3q_u8", + "vld3_u16", + "vld3q_u16", + "vld3_u32", + "vld3q_u32", + "vld3_p8", + "vld3q_p8", + "vld3_p16", + "vld3q_p16", + "vld3q_lane_f32", + "vld4_dup_f16", + "vld4q_dup_f16", + "vld4_dup_f16", + "vld4q_dup_f16", + "vld4_dup_f32", + "vld4q_dup_f32", + "vld4_dup_s8", + "vld4q_dup_s8", + "vld4_dup_s16", + "vld4q_dup_s16", + "vld4_dup_s32", + "vld4q_dup_s32", + "vld4_dup_f32", + "vld4q_dup_f32", + "vld4_dup_s8", + "vld4q_dup_s8", + "vld4_dup_s16", + "vld4q_dup_s16", + "vld4_dup_s32", + "vld4q_dup_s32", + "vld4_dup_s64", + "vld4_dup_p64", + "vld4_dup_s64", + "vld4_dup_u64", + "vld4_dup_u8", + "vld4_dup_u8", + "vld4q_dup_u8", + "vld4q_dup_u8", + "vld4_dup_u16", + "vld4_dup_u16", + "vld4q_dup_u16", + "vld4q_dup_u16", + "vld4_dup_u32", + "vld4_dup_u32", + "vld4q_dup_u32", + "vld4q_dup_u32", + "vld4_dup_p8", + "vld4_dup_p8", + "vld4q_dup_p8", + "vld4q_dup_p8", + "vld4_dup_p16", + "vld4_dup_p16", + "vld4q_dup_p16", + "vld4q_dup_p16", + "vld4_f16", + "vld4q_f16", + "vld4_f16", + "vld4q_f16", + "vld4_f32", + "vld4q_f32", + "vld4_s8", + "vld4q_s8", + "vld4_s16", + "vld4q_s16", + "vld4_s32", + "vld4q_s32", + "vld4_f32", + "vld4q_f32", + "vld4_s8", + "vld4q_s8", + "vld4_s16", + "vld4q_s16", + "vld4_s32", + "vld4q_s32", + "vld4_lane_f16", + "vld4q_lane_f16", + "vld4_lane_f16", + "vld4q_lane_f16", + "vld4_lane_f32", + "vld4q_lane_f32", + "vld4_lane_s8", + "vld4_lane_s16", + "vld4q_lane_s16", + "vld4_lane_s32", + "vld4q_lane_s32", + "vld4_lane_f32", + "vld4q_lane_f32", + "vld4_lane_s8", + "vld4_lane_s16", + "vld4q_lane_s16", + "vld4_lane_s32", + "vld4q_lane_s32", + "vld4_lane_u8", + "vld4_lane_u16", + "vld4q_lane_u16", + "vld4_lane_u32", + "vld4q_lane_u32", + "vld4_lane_p8", + "vld4_lane_p16", + "vld4q_lane_p16", + "vld4_p64", + "vld4_s64", + "vld4_s64", + "vld4_u64", + "vld4_u8", + "vld4q_u8", + "vld4_u16", + "vld4q_u16", + "vld4_u32", + "vld4q_u32", + "vld4_p8", + "vld4q_p8", + "vld4_p16", + "vld4q_p16", + "vmax_f16", + "vmaxq_f16", + "vmax_f32", + "vmaxq_f32", + "vmax_s8", + "vmaxq_s8", + "vmax_s16", + "vmaxq_s16", + "vmax_s32", + "vmaxq_s32", + "vmax_u8", + "vmaxq_u8", + "vmax_u16", + "vmaxq_u16", + "vmax_u32", + "vmaxq_u32", + "vmaxnm_f16", + "vmaxnmq_f16", + "vmaxnm_f32", + "vmaxnmq_f32", + "vmin_f16", + "vminq_f16", + "vmin_f32", + "vminq_f32", + "vmin_s8", + "vminq_s8", + "vmin_s16", + "vminq_s16", + "vmin_s32", + "vminq_s32", + "vmin_u8", + "vminq_u8", + "vmin_u16", + "vminq_u16", + "vmin_u32", + "vminq_u32", + "vminnm_f16", + "vminnmq_f16", + "vminnm_f32", + "vminnmq_f32", + "vmla_f32", + "vmlaq_f32", + "vmla_lane_f32", + "vmla_laneq_f32", + "vmlaq_lane_f32", + "vmlaq_laneq_f32", + "vmla_lane_s16", + "vmla_lane_u16", + "vmla_laneq_s16", + "vmla_laneq_u16", + "vmlaq_lane_s16", + "vmlaq_lane_u16", + "vmlaq_laneq_s16", + "vmlaq_laneq_u16", + "vmla_lane_s32", + "vmla_lane_u32", + "vmla_laneq_s32", + "vmla_laneq_u32", + "vmlaq_lane_s32", + "vmlaq_lane_u32", + "vmlaq_laneq_s32", + "vmlaq_laneq_u32", + "vmla_n_f32", + "vmlaq_n_f32", + "vmla_n_s16", + "vmlaq_n_s16", + "vmla_n_u16", + "vmlaq_n_u16", + "vmla_n_s32", + "vmlaq_n_s32", + "vmla_n_u32", + "vmlaq_n_u32", + "vmla_s8", + "vmlaq_s8", + "vmla_s16", + "vmlaq_s16", + "vmla_s32", + "vmlaq_s32", + "vmla_u8", + "vmlaq_u8", + "vmla_u16", + "vmlaq_u16", + "vmla_u32", + "vmlaq_u32", + "vmlal_lane_s16", + "vmlal_laneq_s16", + "vmlal_lane_s32", + "vmlal_laneq_s32", + "vmlal_lane_u16", + "vmlal_laneq_u16", + "vmlal_lane_u32", + "vmlal_laneq_u32", + "vmlal_n_s16", + "vmlal_n_s32", + "vmlal_n_u16", + "vmlal_n_u32", + "vmlal_s8", + "vmlal_s16", + "vmlal_s32", + "vmlal_u8", + "vmlal_u16", + "vmlal_u32", + "vmls_f32", + "vmlsq_f32", + "vmls_lane_f32", + "vmls_laneq_f32", + "vmlsq_lane_f32", + "vmlsq_laneq_f32", + "vmls_lane_s16", + "vmls_lane_u16", + "vmls_laneq_s16", + "vmls_laneq_u16", + "vmlsq_lane_s16", + "vmlsq_lane_u16", + "vmlsq_laneq_s16", + "vmlsq_laneq_u16", + "vmls_lane_s32", + "vmls_lane_u32", + "vmls_laneq_s32", + "vmls_laneq_u32", + "vmlsq_lane_s32", + "vmlsq_lane_u32", + "vmlsq_laneq_s32", + "vmlsq_laneq_u32", + "vmls_n_f32", + "vmlsq_n_f32", + "vmls_n_s16", + "vmlsq_n_s16", + "vmls_n_u16", + "vmlsq_n_u16", + "vmls_n_s32", + "vmlsq_n_s32", + "vmls_n_u32", + "vmlsq_n_u32", + "vmls_s8", + "vmlsq_s8", + "vmls_s16", + "vmlsq_s16", + "vmls_s32", + "vmlsq_s32", + "vmls_u8", + "vmlsq_u8", + "vmls_u16", + "vmlsq_u16", + "vmls_u32", + "vmlsq_u32", + "vmlsl_lane_s16", + "vmlsl_laneq_s16", + "vmlsl_lane_s32", + "vmlsl_laneq_s32", + "vmlsl_lane_u16", + "vmlsl_laneq_u16", + "vmlsl_lane_u32", + "vmlsl_laneq_u32", + "vmlsl_n_s16", + "vmlsl_n_s32", + "vmlsl_n_u16", + "vmlsl_n_u32", + "vmlsl_s8", + "vmlsl_s16", + "vmlsl_s32", + "vmlsl_u8", + "vmlsl_u16", + "vmlsl_u32", + "vmmlaq_s32", + "vmmlaq_u32", + "vmov_n_f16", + "vmovq_n_f16", + "vmul_f16", + "vmulq_f16", + "vmul_lane_f16", + "vmulq_lane_f16", + "vmul_lane_f32", + "vmul_laneq_f32", + "vmulq_lane_f32", + "vmulq_laneq_f32", + "vmul_lane_s16", + "vmulq_lane_s16", + "vmul_lane_s32", + "vmulq_lane_s32", + "vmul_lane_u16", + "vmulq_lane_u16", + "vmul_lane_u32", + "vmulq_lane_u32", + "vmul_laneq_s16", + "vmulq_laneq_s16", + "vmul_laneq_s32", + "vmulq_laneq_s32", + "vmul_laneq_u16", + "vmulq_laneq_u16", + "vmul_laneq_u32", + "vmulq_laneq_u32", + "vmul_n_f16", + "vmulq_n_f16", + "vmul_n_f32", + "vmulq_n_f32", + "vmul_n_s16", + "vmulq_n_s16", + "vmul_n_s32", + "vmulq_n_s32", + "vmul_n_u16", + "vmulq_n_u16", + "vmul_n_u32", + "vmulq_n_u32", + "vmul_p8", + "vmulq_p8", + "vmull_lane_s16", + "vmull_laneq_s16", + "vmull_lane_s32", + "vmull_laneq_s32", + "vmull_lane_u16", + "vmull_laneq_u16", + "vmull_lane_u32", + "vmull_laneq_u32", + "vmull_n_s16", + "vmull_n_s32", + "vmull_n_u16", + "vmull_n_u32", + "vmull_p8", + "vmull_s16", + "vmull_s32", + "vmull_s8", + "vmull_u8", + "vmull_u16", + "vmull_u32", + "vneg_f16", + "vnegq_f16", + "vneg_f32", + "vnegq_f32", + "vneg_s8", + "vnegq_s8", + "vneg_s16", + "vnegq_s16", + "vneg_s32", + "vnegq_s32", + "vpadal_s8", + "vpadalq_s8", + "vpadal_s16", + "vpadalq_s16", + "vpadal_s32", + "vpadalq_s32", + "vpadal_u8", + "vpadalq_u8", + "vpadal_u16", + "vpadalq_u16", + "vpadal_u32", + "vpadalq_u32", + "vpadd_f16", + "vpadd_f32", + "vpadd_s8", + "vpadd_s16", + "vpadd_s32", + "vpadd_u8", + "vpadd_u8", + "vpadd_u16", + "vpadd_u16", + "vpadd_u32", + "vpadd_u32", + "vpaddl_s8", + "vpaddlq_s8", + "vpaddl_s16", + "vpaddlq_s16", + "vpaddl_s32", + "vpaddlq_s32", + "vpaddl_u8", + "vpaddlq_u8", + "vpaddl_u16", + "vpaddlq_u16", + "vpaddl_u32", + "vpaddlq_u32", + "vpmax_f32", + "vpmax_s8", + "vpmax_s16", + "vpmax_s32", + "vpmax_u8", + "vpmax_u16", + "vpmax_u32", + "vpmin_f32", + "vpmin_s8", + "vpmin_s16", + "vpmin_s32", + "vpmin_u8", + "vpmin_u16", + "vpmin_u32", + "vqabs_s8", + "vqabsq_s8", + "vqabs_s16", + "vqabsq_s16", + "vqabs_s32", + "vqabsq_s32", + "vqadd_s64", + "vqaddq_s64", + "vqadd_u64", + "vqaddq_u64", + "vqdmlal_lane_s16", + "vqdmlal_lane_s32", + "vqdmlal_n_s16", + "vqdmlal_n_s32", + "vqdmlal_s16", + "vqdmlal_s32", + "vqdmlsl_lane_s16", + "vqdmlsl_lane_s32", + "vqdmlsl_n_s16", + "vqdmlsl_n_s32", + "vqdmlsl_s16", + "vqdmlsl_s32", + "vqdmulh_laneq_s16", + "vqdmulhq_laneq_s16", + "vqdmulh_laneq_s32", + "vqdmulhq_laneq_s32", + "vqdmulh_n_s16", + "vqdmulhq_n_s16", + "vqdmulh_n_s32", + "vqdmulhq_n_s32", + "vqdmulh_s16", + "vqdmulhq_s16", + "vqdmulh_s32", + "vqdmulhq_s32", + "vqdmull_lane_s16", + "vqdmull_lane_s32", + "vqdmull_n_s16", + "vqdmull_n_s32", + "vqdmull_s16", + "vqdmull_s32", + "vqmovn_s16", + "vqmovn_s32", + "vqmovn_s64", + "vqmovn_u16", + "vqmovn_u32", + "vqmovn_u64", + "vqmovun_s16", + "vqmovun_s32", + "vqmovun_s64", + "vqneg_s8", + "vqnegq_s8", + "vqneg_s16", + "vqnegq_s16", + "vqneg_s32", + "vqnegq_s32", + "vqrdmulh_lane_s16", + "vqrdmulh_lane_s32", + "vqrdmulh_laneq_s16", + "vqrdmulh_laneq_s32", + "vqrdmulhq_lane_s16", + "vqrdmulhq_lane_s32", + "vqrdmulhq_laneq_s16", + "vqrdmulhq_laneq_s32", + "vqrdmulh_n_s16", + "vqrdmulhq_n_s16", + "vqrdmulh_n_s32", + "vqrdmulhq_n_s32", + "vqrdmulh_s16", + "vqrdmulhq_s16", + "vqrdmulh_s32", + "vqrdmulhq_s32", + "vqrshl_s8", + "vqrshlq_s8", + "vqrshl_s16", + "vqrshlq_s16", + "vqrshl_s32", + "vqrshlq_s32", + "vqrshl_s64", + "vqrshlq_s64", + "vqrshl_u8", + "vqrshlq_u8", + "vqrshl_u16", + "vqrshlq_u16", + "vqrshl_u32", + "vqrshlq_u32", + "vqrshl_u64", + "vqrshlq_u64", + "vqrshrn_n_s16", + "vqrshrn_n_s32", + "vqrshrn_n_s64", + "vqrshrn_n_s16", + "vqrshrn_n_s32", + "vqrshrn_n_s64", + "vqrshrn_n_u16", + "vqrshrn_n_u32", + "vqrshrn_n_u64", + "vqrshrn_n_u16", + "vqrshrn_n_u32", + "vqrshrn_n_u64", + "vqrshrun_n_s16", + "vqrshrun_n_s32", + "vqrshrun_n_s64", + "vqrshrun_n_s16", + "vqrshrun_n_s32", + "vqrshrun_n_s64", + "vqshl_n_s8", + "vqshlq_n_s8", + "vqshl_n_s16", + "vqshlq_n_s16", + "vqshl_n_s32", + "vqshlq_n_s32", + "vqshl_n_s64", + "vqshlq_n_s64", + "vqshl_n_u8", + "vqshlq_n_u8", + "vqshl_n_u16", + "vqshlq_n_u16", + "vqshl_n_u32", + "vqshlq_n_u32", + "vqshl_n_u64", + "vqshlq_n_u64", + "vqshl_s8", + "vqshlq_s8", + "vqshl_s16", + "vqshlq_s16", + "vqshl_s32", + "vqshlq_s32", + "vqshl_s64", + "vqshlq_s64", + "vqshl_u8", + "vqshlq_u8", + "vqshl_u16", + "vqshlq_u16", + "vqshl_u32", + "vqshlq_u32", + "vqshl_u64", + "vqshlq_u64", + "vqshlu_n_s8", + "vqshluq_n_s8", + "vqshlu_n_s16", + "vqshluq_n_s16", + "vqshlu_n_s32", + "vqshluq_n_s32", + "vqshlu_n_s64", + "vqshluq_n_s64", + "vqshlu_n_s8", + "vqshluq_n_s8", + "vqshlu_n_s16", + "vqshluq_n_s16", + "vqshlu_n_s32", + "vqshluq_n_s32", + "vqshlu_n_s64", + "vqshluq_n_s64", + "vqshrn_n_s16", + "vqshrn_n_s32", + "vqshrn_n_s64", + "vqshrn_n_s16", + "vqshrn_n_s32", + "vqshrn_n_s64", + "vqshrn_n_u16", + "vqshrn_n_u32", + "vqshrn_n_u64", + "vqshrn_n_u16", + "vqshrn_n_u32", + "vqshrn_n_u64", + "vqshrun_n_s16", + "vqshrun_n_s32", + "vqshrun_n_s64", + "vqshrun_n_s16", + "vqshrun_n_s32", + "vqshrun_n_s64", + "vqsub_s64", + "vqsubq_s64", + "vqsub_u64", + "vqsubq_u64", + "vraddhn_high_s16", + "vraddhn_high_s32", + "vraddhn_high_s64", + "vraddhn_high_u16", + "vraddhn_high_u32", + "vraddhn_high_u64", + "vraddhn_s16", + "vraddhn_s32", + "vraddhn_s64", + "vraddhn_u16", + "vraddhn_u16", + "vraddhn_u32", + "vraddhn_u32", + "vraddhn_u64", + "vraddhn_u64", + "vrecpe_f16", + "vrecpeq_f16", + "vrecpe_f32", + "vrecpeq_f32", + "vrecpe_u32", + "vrecpeq_u32", + "vrecps_f16", + "vrecpsq_f16", + "vrecps_f32", + "vrecpsq_f32", + "vreinterpret_f32_f16", + "vreinterpret_f32_f16", + "vreinterpret_s8_f16", + "vreinterpret_s8_f16", + "vreinterpret_s16_f16", + "vreinterpret_s16_f16", + "vreinterpret_s32_f16", + "vreinterpret_s32_f16", + "vreinterpret_s64_f16", + "vreinterpret_s64_f16", + "vreinterpret_u8_f16", + "vreinterpret_u8_f16", + "vreinterpret_u16_f16", + "vreinterpret_u16_f16", + "vreinterpret_u32_f16", + "vreinterpret_u32_f16", + "vreinterpret_u64_f16", + "vreinterpret_u64_f16", + "vreinterpret_p8_f16", + "vreinterpret_p8_f16", + "vreinterpret_p16_f16", + "vreinterpret_p16_f16", + "vreinterpretq_f32_f16", + "vreinterpretq_f32_f16", + "vreinterpretq_s8_f16", + "vreinterpretq_s8_f16", + "vreinterpretq_s16_f16", + "vreinterpretq_s16_f16", + "vreinterpretq_s32_f16", + "vreinterpretq_s32_f16", + "vreinterpretq_s64_f16", + "vreinterpretq_s64_f16", + "vreinterpretq_u8_f16", + "vreinterpretq_u8_f16", + "vreinterpretq_u16_f16", + "vreinterpretq_u16_f16", + "vreinterpretq_u32_f16", + "vreinterpretq_u32_f16", + "vreinterpretq_u64_f16", + "vreinterpretq_u64_f16", + "vreinterpretq_p8_f16", + "vreinterpretq_p8_f16", + "vreinterpretq_p16_f16", + "vreinterpretq_p16_f16", + "vreinterpret_f16_f32", + "vreinterpret_f16_f32", + "vreinterpretq_f16_f32", + "vreinterpretq_f16_f32", + "vreinterpret_f16_s8", + "vreinterpret_f16_s8", + "vreinterpretq_f16_s8", + "vreinterpretq_f16_s8", + "vreinterpret_f16_s16", + "vreinterpret_f16_s16", + "vreinterpretq_f16_s16", + "vreinterpretq_f16_s16", + "vreinterpret_f16_s32", + "vreinterpret_f16_s32", + "vreinterpretq_f16_s32", + "vreinterpretq_f16_s32", + "vreinterpret_f16_s64", + "vreinterpret_f16_s64", + "vreinterpretq_f16_s64", + "vreinterpretq_f16_s64", + "vreinterpret_f16_u8", + "vreinterpret_f16_u8", + "vreinterpretq_f16_u8", + "vreinterpretq_f16_u8", + "vreinterpret_f16_u16", + "vreinterpret_f16_u16", + "vreinterpretq_f16_u16", + "vreinterpretq_f16_u16", + "vreinterpret_f16_u32", + "vreinterpret_f16_u32", + "vreinterpretq_f16_u32", + "vreinterpretq_f16_u32", + "vreinterpret_f16_u64", + "vreinterpret_f16_u64", + "vreinterpretq_f16_u64", + "vreinterpretq_f16_u64", + "vreinterpret_f16_p8", + "vreinterpret_f16_p8", + "vreinterpretq_f16_p8", + "vreinterpretq_f16_p8", + "vreinterpret_f16_p16", + "vreinterpret_f16_p16", + "vreinterpretq_f16_p16", + "vreinterpretq_f16_p16", + "vreinterpretq_f16_p128", + "vreinterpretq_f16_p128", + "vreinterpret_p64_f16", + "vreinterpret_p64_f16", + "vreinterpretq_p128_f16", + "vreinterpretq_p128_f16", + "vreinterpretq_p64_f16", + "vreinterpretq_p64_f16", + "vreinterpret_f16_p64", + "vreinterpret_f16_p64", + "vreinterpretq_f16_p64", + "vreinterpretq_f16_p64", + "vreinterpretq_f32_p128", + "vreinterpretq_f32_p128", + "vreinterpret_s8_f32", + "vreinterpret_s8_f32", + "vreinterpret_s16_f32", + "vreinterpret_s16_f32", + "vreinterpret_s32_f32", + "vreinterpret_s32_f32", + "vreinterpret_s64_f32", + "vreinterpret_s64_f32", + "vreinterpret_u8_f32", + "vreinterpret_u8_f32", + "vreinterpret_u16_f32", + "vreinterpret_u16_f32", + "vreinterpret_u32_f32", + "vreinterpret_u32_f32", + "vreinterpret_u64_f32", + "vreinterpret_u64_f32", + "vreinterpret_p8_f32", + "vreinterpret_p8_f32", + "vreinterpret_p16_f32", + "vreinterpret_p16_f32", + "vreinterpretq_p128_f32", + "vreinterpretq_p128_f32", + "vreinterpretq_s8_f32", + "vreinterpretq_s8_f32", + "vreinterpretq_s16_f32", + "vreinterpretq_s16_f32", + "vreinterpretq_s32_f32", + "vreinterpretq_s32_f32", + "vreinterpretq_s64_f32", + "vreinterpretq_s64_f32", + "vreinterpretq_u8_f32", + "vreinterpretq_u8_f32", + "vreinterpretq_u16_f32", + "vreinterpretq_u16_f32", + "vreinterpretq_u32_f32", + "vreinterpretq_u32_f32", + "vreinterpretq_u64_f32", + "vreinterpretq_u64_f32", + "vreinterpretq_p8_f32", + "vreinterpretq_p8_f32", + "vreinterpretq_p16_f32", + "vreinterpretq_p16_f32", + "vreinterpret_f32_s8", + "vreinterpret_f32_s8", + "vreinterpret_s16_s8", + "vreinterpret_s16_s8", + "vreinterpret_s32_s8", + "vreinterpret_s32_s8", + "vreinterpret_s64_s8", + "vreinterpret_s64_s8", + "vreinterpret_u8_s8", + "vreinterpret_u8_s8", + "vreinterpret_u16_s8", + "vreinterpret_u16_s8", + "vreinterpret_u32_s8", + "vreinterpret_u32_s8", + "vreinterpret_u64_s8", + "vreinterpret_u64_s8", + "vreinterpret_p8_s8", + "vreinterpret_p8_s8", + "vreinterpret_p16_s8", + "vreinterpret_p16_s8", + "vreinterpretq_f32_s8", + "vreinterpretq_f32_s8", + "vreinterpretq_s16_s8", + "vreinterpretq_s16_s8", + "vreinterpretq_s32_s8", + "vreinterpretq_s32_s8", + "vreinterpretq_s64_s8", + "vreinterpretq_s64_s8", + "vreinterpretq_u8_s8", + "vreinterpretq_u8_s8", + "vreinterpretq_u16_s8", + "vreinterpretq_u16_s8", + "vreinterpretq_u32_s8", + "vreinterpretq_u32_s8", + "vreinterpretq_u64_s8", + "vreinterpretq_u64_s8", + "vreinterpretq_p8_s8", + "vreinterpretq_p8_s8", + "vreinterpretq_p16_s8", + "vreinterpretq_p16_s8", + "vreinterpret_f32_s16", + "vreinterpret_f32_s16", + "vreinterpret_s8_s16", + "vreinterpret_s8_s16", + "vreinterpret_s32_s16", + "vreinterpret_s32_s16", + "vreinterpret_s64_s16", + "vreinterpret_s64_s16", + "vreinterpret_u8_s16", + "vreinterpret_u8_s16", + "vreinterpret_u16_s16", + "vreinterpret_u16_s16", + "vreinterpret_u32_s16", + "vreinterpret_u32_s16", + "vreinterpret_u64_s16", + "vreinterpret_u64_s16", + "vreinterpret_p8_s16", + "vreinterpret_p8_s16", + "vreinterpret_p16_s16", + "vreinterpret_p16_s16", + "vreinterpretq_f32_s16", + "vreinterpretq_f32_s16", + "vreinterpretq_s8_s16", + "vreinterpretq_s8_s16", + "vreinterpretq_s32_s16", + "vreinterpretq_s32_s16", + "vreinterpretq_s64_s16", + "vreinterpretq_s64_s16", + "vreinterpretq_u8_s16", + "vreinterpretq_u8_s16", + "vreinterpretq_u16_s16", + "vreinterpretq_u16_s16", + "vreinterpretq_u32_s16", + "vreinterpretq_u32_s16", + "vreinterpretq_u64_s16", + "vreinterpretq_u64_s16", + "vreinterpretq_p8_s16", + "vreinterpretq_p8_s16", + "vreinterpretq_p16_s16", + "vreinterpretq_p16_s16", + "vreinterpret_f32_s32", + "vreinterpret_f32_s32", + "vreinterpret_s8_s32", + "vreinterpret_s8_s32", + "vreinterpret_s16_s32", + "vreinterpret_s16_s32", + "vreinterpret_s64_s32", + "vreinterpret_s64_s32", + "vreinterpret_u8_s32", + "vreinterpret_u8_s32", + "vreinterpret_u16_s32", + "vreinterpret_u16_s32", + "vreinterpret_u32_s32", + "vreinterpret_u32_s32", + "vreinterpret_u64_s32", + "vreinterpret_u64_s32", + "vreinterpret_p8_s32", + "vreinterpret_p8_s32", + "vreinterpret_p16_s32", + "vreinterpret_p16_s32", + "vreinterpretq_f32_s32", + "vreinterpretq_f32_s32", + "vreinterpretq_s8_s32", + "vreinterpretq_s8_s32", + "vreinterpretq_s16_s32", + "vreinterpretq_s16_s32", + "vreinterpretq_s64_s32", + "vreinterpretq_s64_s32", + "vreinterpretq_u8_s32", + "vreinterpretq_u8_s32", + "vreinterpretq_u16_s32", + "vreinterpretq_u16_s32", + "vreinterpretq_u32_s32", + "vreinterpretq_u32_s32", + "vreinterpretq_u64_s32", + "vreinterpretq_u64_s32", + "vreinterpretq_p8_s32", + "vreinterpretq_p8_s32", + "vreinterpretq_p16_s32", + "vreinterpretq_p16_s32", + "vreinterpret_f32_s64", + "vreinterpret_f32_s64", + "vreinterpret_s8_s64", + "vreinterpret_s8_s64", + "vreinterpret_s16_s64", + "vreinterpret_s16_s64", + "vreinterpret_s32_s64", + "vreinterpret_s32_s64", + "vreinterpret_u8_s64", + "vreinterpret_u8_s64", + "vreinterpret_u16_s64", + "vreinterpret_u16_s64", + "vreinterpret_u32_s64", + "vreinterpret_u32_s64", + "vreinterpret_u64_s64", + "vreinterpret_p8_s64", + "vreinterpret_p8_s64", + "vreinterpret_p16_s64", + "vreinterpret_p16_s64", + "vreinterpretq_f32_s64", + "vreinterpretq_f32_s64", + "vreinterpretq_s8_s64", + "vreinterpretq_s8_s64", + "vreinterpretq_s16_s64", + "vreinterpretq_s16_s64", + "vreinterpretq_s32_s64", + "vreinterpretq_s32_s64", + "vreinterpretq_u8_s64", + "vreinterpretq_u8_s64", + "vreinterpretq_u16_s64", + "vreinterpretq_u16_s64", + "vreinterpretq_u32_s64", + "vreinterpretq_u32_s64", + "vreinterpretq_u64_s64", + "vreinterpretq_u64_s64", + "vreinterpretq_p8_s64", + "vreinterpretq_p8_s64", + "vreinterpretq_p16_s64", + "vreinterpretq_p16_s64", + "vreinterpret_f32_u8", + "vreinterpret_f32_u8", + "vreinterpret_s8_u8", + "vreinterpret_s8_u8", + "vreinterpret_s16_u8", + "vreinterpret_s16_u8", + "vreinterpret_s32_u8", + "vreinterpret_s32_u8", + "vreinterpret_s64_u8", + "vreinterpret_s64_u8", + "vreinterpret_u16_u8", + "vreinterpret_u16_u8", + "vreinterpret_u32_u8", + "vreinterpret_u32_u8", + "vreinterpret_u64_u8", + "vreinterpret_u64_u8", + "vreinterpret_p8_u8", + "vreinterpret_p8_u8", + "vreinterpret_p16_u8", + "vreinterpret_p16_u8", + "vreinterpretq_f32_u8", + "vreinterpretq_f32_u8", + "vreinterpretq_s8_u8", + "vreinterpretq_s8_u8", + "vreinterpretq_s16_u8", + "vreinterpretq_s16_u8", + "vreinterpretq_s32_u8", + "vreinterpretq_s32_u8", + "vreinterpretq_s64_u8", + "vreinterpretq_s64_u8", + "vreinterpretq_u16_u8", + "vreinterpretq_u16_u8", + "vreinterpretq_u32_u8", + "vreinterpretq_u32_u8", + "vreinterpretq_u64_u8", + "vreinterpretq_u64_u8", + "vreinterpretq_p8_u8", + "vreinterpretq_p8_u8", + "vreinterpretq_p16_u8", + "vreinterpretq_p16_u8", + "vreinterpret_f32_u16", + "vreinterpret_f32_u16", + "vreinterpret_s8_u16", + "vreinterpret_s8_u16", + "vreinterpret_s16_u16", + "vreinterpret_s16_u16", + "vreinterpret_s32_u16", + "vreinterpret_s32_u16", + "vreinterpret_s64_u16", + "vreinterpret_s64_u16", + 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"vgetq_lane_p64", + "vgetq_lane_p64", + "vgetq_lane_p8", + "vgetq_lane_p8", + "vgetq_lane_s16", + "vgetq_lane_s16", + "vgetq_lane_s32", + "vgetq_lane_s32", + "vgetq_lane_s64", + "vgetq_lane_s64", + "vgetq_lane_s8", + "vgetq_lane_s8", + "vgetq_lane_u16", + "vgetq_lane_u16", + "vgetq_lane_u32", + "vgetq_lane_u32", + "vgetq_lane_u8", + "vgetq_lane_u8", + "vget_lane_p64", + "vget_lane_s64", + "vget_lane_u64", + "vget_low_f32", + "vget_low_f32", + "vget_low_p16", + "vget_low_p16", + "vget_low_p8", + "vget_low_p8", + "vget_low_s16", + "vget_low_s16", + "vget_low_s32", + "vget_low_s32", + "vget_low_s8", + "vget_low_s8", + "vget_low_u16", + "vget_low_u16", + "vget_low_u32", + "vget_low_u32", + "vget_low_u8", + "vget_low_u8", + "vget_low_s64", + "vget_low_s64", + "vget_low_u64", + "vget_low_u64", + "vaddw_high_s16", + "vaddw_high_s32", + "vaddw_high_s8", + "vaddw_high_u16", + "vaddw_high_u32", + "vaddw_high_u8", + "vgetq_lane_u64", +]; diff --git a/library/stdarch/crates/stdarch-verify/tests/x86-intel.rs b/library/stdarch/crates/stdarch-verify/tests/x86-intel.rs index 4136463f197fd..be948df541b79 100644 --- a/library/stdarch/crates/stdarch-verify/tests/x86-intel.rs +++ b/library/stdarch/crates/stdarch-verify/tests/x86-intel.rs @@ -62,6 +62,7 @@ static MM_CMPINT_ENUM: Type = Type::MM_CMPINT_ENUM; static MM_MANTISSA_NORM_ENUM: Type = Type::MM_MANTISSA_NORM_ENUM; static MM_MANTISSA_SIGN_ENUM: Type = Type::MM_MANTISSA_SIGN_ENUM; static MM_PERM_ENUM: Type = Type::MM_PERM_ENUM; +static TILE1024I: Type = Type::TILE1024I; static TUPLE: Type = Type::Tuple; static CPUID: Type = Type::CpuidResult; @@ -102,6 +103,7 @@ enum Type { CpuidResult, Never, Ordering, + TILE1024I, } stdarch_verify::x86_functions!(static FUNCTIONS); @@ -211,9 +213,10 @@ fn verify_all_signatures() { "_rdseed64_step", // Prefetch "_mm_prefetch", + "_m_prefetchrs", // CMPXCHG "cmpxchg16b", - // Undefined + // Undefined, "_mm_undefined_ps", "_mm_undefined_pd", "_mm_undefined_si128", @@ -246,13 +249,9 @@ fn verify_all_signatures() { "_xend", "_xabort_code", // Aliases - "_mm_comige_ss", "_mm_cvt_ss2si", "_mm_cvtt_ss2si", "_mm_cvt_si2ss", - "_mm_set_ps1", - "_mm_load_ps1", - "_mm_store_ps1", "_mm_bslli_si128", "_mm_bsrli_si128", "_bextr2_u32", @@ -306,7 +305,7 @@ fn verify_all_signatures() { } // FIXME: these have not been added to Intrinsics Guide yet - if ["amx-avx512", "amx-fp8", "amx-movrs", "amx-tf32"] + if ["amx-avx512", "amx-fp8", "amx-movrs", "movrs"] .iter() .any(|f| feature.contains(f)) { @@ -664,12 +663,14 @@ fn matches(rust: &Function, intel: &Intrinsic) -> Result<(), String> { fn pointed_type(intrinsic: &Intrinsic) -> Result { Ok( if intrinsic.tech == "AMX" - || intrinsic - .cpuid - .iter() - .any(|cpuid| matches!(&**cpuid, "KEYLOCKER" | "KEYLOCKER_WIDE" | "XSAVE" | "FXSR")) + || intrinsic.cpuid.iter().any(|cpuid| { + matches!( + &**cpuid, + "KEYLOCKER" | "KEYLOCKER_WIDE" | "XSAVE" | "FXSR" | "CLFLUSHOPT" + ) + }) { - // AMX, KEYLOCKER and XSAVE intrinsics should take `*u8` + // AMX, KEYLOCKER, XSAVE and CLFLUSHOPT intrinsics should take `*u8` U8 } else if intrinsic.name == "_mm_clflush" { // Just a false match in the following logic @@ -777,6 +778,7 @@ fn equate( (&Type::MMASK32, "__mmask32") => {} (&Type::MMASK16, "__mmask16") => {} (&Type::MMASK8, "__mmask8") => {} + (&Type::TILE1024I, "__tile1024i") => {} (&Type::MutPtr(_type), "void*") | (&Type::ConstPtr(_type), "void const*") => { let pointed_type = pointed_type(intrinsic)?; @@ -815,6 +817,7 @@ fn equate( (&Type::MutPtr(&Type::M512BH), "__m512bh*") => {} (&Type::MutPtr(&Type::M512I), "__m512i*") => {} (&Type::MutPtr(&Type::M512D), "__m512d*") => {} + (&Type::MutPtr(&Type::TILE1024I), "__tile1024i*") => {} (&Type::ConstPtr(&Type::PrimFloat(16)), "_Float16 const*") => {} (&Type::ConstPtr(&Type::PrimFloat(32)), "float const*") => {} diff --git a/library/stdarch/examples/Cargo.toml b/library/stdarch/examples/Cargo.toml index 61451edee841c..8752f206526c7 100644 --- a/library/stdarch/examples/Cargo.toml +++ b/library/stdarch/examples/Cargo.toml @@ -13,7 +13,7 @@ default-run = "hex" [dependencies] core_arch = { path = "../crates/core_arch" } quickcheck = "1.0" -rand = "0.8" +rand = "0.9.3" [[bin]] name = "hex" @@ -23,6 +23,11 @@ path = "hex.rs" name = "connect5" path = "connect5.rs" +# Hexagon-only: requires --target hexagon-unknown-linux-musl +[[bin]] +name = "gaussian" +path = "gaussian.rs" + [[example]] name = "wasm" crate-type = ["cdylib"] diff --git a/library/stdarch/examples/connect5.rs b/library/stdarch/examples/connect5.rs index f24657b148394..2df294b16b71e 100644 --- a/library/stdarch/examples/connect5.rs +++ b/library/stdarch/examples/connect5.rs @@ -33,8 +33,8 @@ #![cfg_attr(target_arch = "x86_64", feature(stdarch_internal))] #![feature(stmt_expr_attributes)] +use rand::rng; use rand::seq::SliceRandom; -use rand::thread_rng; use std::cmp; use std::time::Instant; @@ -374,7 +374,7 @@ impl List { } pub fn shuffle(&mut self) { - let mut rng = thread_rng(); + let mut rng = rng(); let num = self.p_size as usize; self.p_move[..num].shuffle(&mut rng); diff --git a/library/stdarch/examples/gaussian.rs b/library/stdarch/examples/gaussian.rs new file mode 100644 index 0000000000000..f41f7539860b0 --- /dev/null +++ b/library/stdarch/examples/gaussian.rs @@ -0,0 +1,352 @@ +//! Hexagon HVX Gaussian 3x3 blur example +//! +//! This example demonstrates the use of Hexagon HVX intrinsics to implement +//! a 3x3 Gaussian blur filter on unsigned 8-bit images. +//! +//! The 3x3 Gaussian kernel is: +//! 1 2 1 +//! 2 4 2 / 16 +//! 1 2 1 +//! +//! This is a separable filter: `[1 2 1]^T * [1 2 1] / 16`. +//! +//! On Hexagon targets, this implementation uses `HvxVectorPair` for widening +//! arithmetic to achieve full precision in the Gaussian computation, avoiding +//! the approximation errors of byte-averaging approaches. On other targets, +//! it runs a reference implementation in pure Rust. +//! +//! # Building and Running (Hexagon) +//! +//! To build (requires Hexagon toolchain): +//! +//! RUSTFLAGS="-C target-feature=+hvxv62,+hvx-length128b \ +//! -C linker=hexagon-unknown-linux-musl-clang" \ +//! cargo +nightly build -p stdarch_examples --bin gaussian \ +//! --target hexagon-unknown-linux-musl \ +//! -Zbuild-std -Zbuild-std-features=llvm-libunwind +//! +//! To run under QEMU: +//! +//! qemu-hexagon -L /target/hexagon-unknown-linux-musl \ +//! target/hexagon-unknown-linux-musl/debug/gaussian +//! +//! # Building and Running (Other targets) +//! +//! cargo +nightly run -p stdarch_examples --bin gaussian + +#![cfg_attr(target_arch = "hexagon", feature(stdarch_hexagon))] +#![cfg_attr(target_arch = "hexagon", feature(hexagon_target_feature))] +#![allow( + unsafe_op_in_unsafe_fn, + clippy::unwrap_used, + clippy::print_stdout, + clippy::missing_docs_in_private_items, + clippy::cast_possible_wrap, + clippy::cast_ptr_alignment +)] + +/// Image width - must be multiple of HVX vector length on Hexagon +const WIDTH: usize = 256; +const HEIGHT: usize = 16; + +// ============================================================================ +// Hexagon HVX implementation +// ============================================================================ + +#[cfg(target_arch = "hexagon")] +mod hvx { + #[cfg(not(target_feature = "hvx-length128b"))] + use core_arch::arch::hexagon::v64::*; + #[cfg(target_feature = "hvx-length128b")] + use core_arch::arch::hexagon::v128::*; + + /// Vector length in bytes for HVX 128-byte mode + #[cfg(target_feature = "hvx-length128b")] + const VLEN: usize = 128; + + /// Vector length in bytes for HVX 64-byte mode + #[cfg(not(target_feature = "hvx-length128b"))] + const VLEN: usize = 64; + + /// Vertical 1-2-1 filter pass using HvxVectorPair widening arithmetic + /// + /// Computes: dst[x] = (row_above[x] + 2*center[x] + row_below[x] + 2) >> 2 + /// + /// Uses HvxVectorPair to widen u8 to u16 for precise arithmetic, avoiding + /// the rounding errors of byte-averaging approximations. + /// + /// # Safety + /// + /// - `src` must point to the center row with valid data at -stride and +stride + /// - `dst` must point to a valid output buffer for `width` bytes + /// - `width` must be a multiple of VLEN + /// - All pointers must be HVX-aligned (128-byte for 128B mode) + #[target_feature(enable = "hvxv62")] + unsafe fn vertical_121_pass(src: *const u8, stride: isize, width: usize, dst: *mut u8) { + let inp0 = src.offset(-stride) as *const HvxVector; + let inp1 = src as *const HvxVector; + let inp2 = src.offset(stride) as *const HvxVector; + let outp = dst as *mut HvxVector; + + let n_chunks = width / VLEN; + for i in 0..n_chunks { + let above = *inp0.add(i); + let center = *inp1.add(i); + let below = *inp2.add(i); + + // Widen above + below to 16-bit using HvxVectorPair + // Q6_Wh_vadd_VubVub: adds two u8 vectors, producing u16 results in a pair + let above_plus_below: HvxVectorPair = Q6_Wh_vadd_VubVub(above, below); + + // Widen center * 2 (add center to itself) + let center_x2: HvxVectorPair = Q6_Wh_vadd_VubVub(center, center); + + // Add them: (above + below) + (center * 2) = above + 2*center + below + let sum: HvxVectorPair = Q6_Wh_vadd_WhWh(above_plus_below, center_x2); + + // Extract high and low vectors from the pair (each contains u16 values) + let sum_lo = Q6_V_lo_W(sum); // Lower 64 elements as i16 + let sum_hi = Q6_V_hi_W(sum); // Upper 64 elements as i16 + + // Arithmetic right shift by 2 (divide by 4) with rounding + // Add 2 for rounding before shift: (sum + 2) >> 2 + let two = Q6_Vh_vsplat_R(2); + let sum_lo_rounded = Q6_Vh_vadd_VhVh(sum_lo, two); + let sum_hi_rounded = Q6_Vh_vadd_VhVh(sum_hi, two); + let shifted_lo = Q6_Vh_vasr_VhVh(sum_lo_rounded, two); + let shifted_hi = Q6_Vh_vasr_VhVh(sum_hi_rounded, two); + + // Pack back to u8 with saturation: takes hi and lo halfword vectors, + // saturates to u8, and interleaves them back to original order + let result = Q6_Vub_vsat_VhVh(shifted_hi, shifted_lo); + + *outp.add(i) = result; + } + } + + /// Horizontal 1-2-1 filter pass using HvxVectorPair widening arithmetic + /// + /// Computes: dst[x] = (src[x-1] + 2*src[x] + src[x+1] + 2) >> 2 + /// + /// Uses `valign` and `vlalign` to shift vectors by 1 byte for neighbor access, + /// then HvxVectorPair for precise widening arithmetic. + /// + /// # Safety + /// + /// - `src` and `dst` must point to valid buffers of `width` bytes + /// - `width` must be a multiple of VLEN + /// - All pointers must be HVX-aligned + #[target_feature(enable = "hvxv62")] + unsafe fn horizontal_121_pass(src: *const u8, width: usize, dst: *mut u8) { + let inp = src as *const HvxVector; + let outp = dst as *mut HvxVector; + + let n_chunks = width / VLEN; + let mut prev = Q6_V_vzero(); + + for i in 0..n_chunks { + let curr = *inp.add(i); + let next = if i + 1 < n_chunks { + *inp.add(i + 1) + } else { + Q6_V_vzero() + }; + + // Left neighbor (x-1): shift curr right by 1 byte, filling from prev + let left = Q6_V_vlalign_VVR(curr, prev, 1); + + // Right neighbor (x+1): shift curr left by 1 byte, filling from next + let right = Q6_V_valign_VVR(next, curr, 1); + + // Widen left + right to 16-bit + let left_plus_right: HvxVectorPair = Q6_Wh_vadd_VubVub(left, right); + + // Widen center * 2 + let center_x2: HvxVectorPair = Q6_Wh_vadd_VubVub(curr, curr); + + // Add: left + 2*center + right + let sum: HvxVectorPair = Q6_Wh_vadd_WhWh(left_plus_right, center_x2); + + // Extract high and low vectors + let sum_lo = Q6_V_lo_W(sum); + let sum_hi = Q6_V_hi_W(sum); + + // Arithmetic right shift by 2 with rounding + let two = Q6_Vh_vsplat_R(2); + let sum_lo_rounded = Q6_Vh_vadd_VhVh(sum_lo, two); + let sum_hi_rounded = Q6_Vh_vadd_VhVh(sum_hi, two); + let shifted_lo = Q6_Vh_vasr_VhVh(sum_lo_rounded, two); + let shifted_hi = Q6_Vh_vasr_VhVh(sum_hi_rounded, two); + + // Pack back to u8 with saturation + let result = Q6_Vub_vsat_VhVh(shifted_hi, shifted_lo); + + *outp.add(i) = result; + + prev = curr; + } + } + + /// Apply Gaussian 3x3 blur to an entire image using separable filtering + /// + /// Two-pass approach: + /// 1. Vertical pass: apply 1-2-1 filter across rows + /// 2. Horizontal pass: apply 1-2-1 filter across columns + /// + /// Combined effect: 3x3 Gaussian kernel [1 2 1; 2 4 2; 1 2 1] / 16 + /// + /// # Safety + /// + /// - `src` and `dst` must point to valid image buffers of `stride * height` bytes + /// - `tmp` must point to a valid temporary buffer of `width` bytes, HVX-aligned + /// - `width` must be a multiple of VLEN and >= VLEN + /// - `stride` must be >= `width` + /// - All buffers must be HVX-aligned (128-byte for 128B mode) + #[target_feature(enable = "hvxv62")] + pub unsafe fn gaussian3x3u8( + src: *const u8, + stride: usize, + width: usize, + height: usize, + dst: *mut u8, + tmp: *mut u8, + ) { + let stride_i = stride as isize; + + // Process interior rows (skip first and last which lack vertical neighbors) + for y in 1..height - 1 { + let row_src = src.offset(y as isize * stride_i); + let row_dst = dst.offset(y as isize * stride_i); + + // Pass 1: vertical 1-2-1 into tmp + vertical_121_pass(row_src, stride_i, width, tmp); + + // Pass 2: horizontal 1-2-1 from tmp into dst + horizontal_121_pass(tmp, width, row_dst); + } + } +} + +// ============================================================================ +// Reference implementation (works on all targets) +// ============================================================================ + +/// Reference implementation of Gaussian 3x3 blur +/// +/// Kernel: +/// 1 2 1 +/// 2 4 2 / 16 +/// 1 2 1 +fn gaussian3x3u8_reference(src: &[u8], stride: usize, width: usize, height: usize, dst: &mut [u8]) { + for y in 1..height - 1 { + for x in 1..width - 1 { + // Compute column sums (vertical 1-2-1 weights) + let mut col = [0u32; 3]; + for i in 0..3 { + col[i] = 1 * src[(y - 1) * stride + x - 1 + i] as u32 + + 2 * src[y * stride + x - 1 + i] as u32 + + 1 * src[(y + 1) * stride + x - 1 + i] as u32; + } + // Apply horizontal 1-2-1 weights and normalize + // (1*col[0] + 2*col[1] + 1*col[2] + 8) / 16 + dst[y * stride + x] = ((1 * col[0] + 2 * col[1] + 1 * col[2] + 8) >> 4) as u8; + } + } +} + +/// Generate deterministic test pattern +fn generate_test_pattern(buf: &mut [u8], width: usize, height: usize) { + for y in 0..height { + for x in 0..width { + buf[y * width + x] = ((x + y * 7) % 256) as u8; + } + } +} + +// ============================================================================ +// Main: runs HVX + reference on Hexagon, reference-only on other targets +// ============================================================================ + +#[cfg(target_arch = "hexagon")] +fn main() { + // Aligned buffers for HVX + #[repr(align(128))] + struct AlignedBuf([u8; N]); + + let mut src = AlignedBuf::<{ WIDTH * HEIGHT }>([0u8; WIDTH * HEIGHT]); + let mut dst_hvx = AlignedBuf::<{ WIDTH * HEIGHT }>([0u8; WIDTH * HEIGHT]); + let mut tmp = AlignedBuf::<{ WIDTH }>([0u8; WIDTH]); + let mut dst_ref = vec![0u8; WIDTH * HEIGHT]; + + // Generate test pattern + generate_test_pattern(&mut src.0, WIDTH, HEIGHT); + + // Run HVX implementation + unsafe { + hvx::gaussian3x3u8( + src.0.as_ptr(), + WIDTH, + WIDTH, + HEIGHT, + dst_hvx.0.as_mut_ptr(), + tmp.0.as_mut_ptr(), + ); + } + + // Run reference + gaussian3x3u8_reference(&src.0, WIDTH, WIDTH, HEIGHT, &mut dst_ref); + + // Verify HVX matches reference (allowing small rounding differences). + use core_arch::arch::hexagon::scalar::{Q6_R_abs_R, Q6_R_max_RR}; + let mut max_diff = 0i32; + for y in 1..HEIGHT - 1 { + for x in 1..WIDTH - 1 { + let idx = y * WIDTH + x; + let diff = unsafe { Q6_R_abs_R(dst_hvx.0[idx] as i32 - dst_ref[idx] as i32) }; + max_diff = unsafe { Q6_R_max_RR(max_diff, diff) }; + // Allow up to 1 LSB difference due to rounding + assert!( + diff <= 1, + "HVX differs from reference at ({}, {}): hvx={}, ref={}, diff={}", + x, + y, + dst_hvx.0[idx], + dst_ref[idx], + diff + ); + } + } + + println!( + "Gaussian 3x3 HVX test passed! Max difference from reference: {}", + max_diff + ); +} + +#[cfg(not(target_arch = "hexagon"))] +fn main() { + let mut src = vec![0u8; WIDTH * HEIGHT]; + let mut dst = vec![0u8; WIDTH * HEIGHT]; + + // Generate test pattern + generate_test_pattern(&mut src, WIDTH, HEIGHT); + + // Run reference implementation + gaussian3x3u8_reference(&src, WIDTH, WIDTH, HEIGHT, &mut dst); + + // Verify output is non-trivial (blurred values differ from input) + let mut changed = 0; + for y in 1..HEIGHT - 1 { + for x in 1..WIDTH - 1 { + let idx = y * WIDTH + x; + if src[idx] != dst[idx] { + changed += 1; + } + } + } + + println!( + "Gaussian 3x3 reference test passed! {} pixels changed by blur", + changed + ); +} diff --git a/library/stdarch/examples/hex.rs b/library/stdarch/examples/hex.rs index 621f55bc0951f..6417562074d9c 100644 --- a/library/stdarch/examples/hex.rs +++ b/library/stdarch/examples/hex.rs @@ -13,7 +13,6 @@ //! and you should see `746573740a` get printed out. #![allow(internal_features)] -#![feature(wasm_target_feature)] #![cfg_attr(test, feature(test))] #![cfg_attr( any(target_arch = "x86", target_arch = "x86_64"), @@ -355,9 +354,9 @@ mod benches { len: usize, f: for<'a> unsafe fn(&[u8], &'a mut [u8]) -> Result<&'a str, usize>, ) { - let mut rng = rand::thread_rng(); + let mut rng = rand::rng(); let input = std::iter::repeat(()) - .map(|()| rng.r#gen::()) + .map(|()| rng.r#random::()) .take(len) .collect::>(); let mut dst = vec![0; input.len() * 2]; diff --git a/library/stdarch/intrinsics_data/arm_intrinsics.json b/library/stdarch/intrinsics_data/arm_intrinsics.json index bce85d19a10f1..7f749fe4d8842 100644 --- a/library/stdarch/intrinsics_data/arm_intrinsics.json +++ b/library/stdarch/intrinsics_data/arm_intrinsics.json @@ -224,21 +224,25 @@ ] }, { - "SIMD_ISA": "Neon", - "name": "vscale_f16", + "SIMD_ISA": "SVE2", + "name": "svaba[_n_s16]", "arguments": [ - "float16x4_t a", - "int16x4_t b" + "svint16_t op1", + "svint16_t op2", + "int16_t op3" ], "return_type": { - "value": "float16x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ @@ -246,26 +250,34 @@ ], "instructions": [ [ - "FSCALE" + "SABA" + ], + [ + "MOVPRFX", + "SABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vscaleq_f16", + "SIMD_ISA": "SVE2", + "name": "svaba[_n_s32]", "arguments": [ - "float16x8_t a", - "int16x8_t b" + "svint32_t op1", + "svint32_t op2", + "int32_t op3" ], "return_type": { - "value": "float16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ @@ -273,26 +285,34 @@ ], "instructions": [ [ - "FSCALE" + "SABA" + ], + [ + "MOVPRFX", + "SABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vscale_f32", + "SIMD_ISA": "SVE2", + "name": "svaba[_n_s64]", "arguments": [ - "float32x2_t a", - "int32x2_t b" + "svint64_t op1", + "svint64_t op2", + "int64_t op3" ], "return_type": { - "value": "float32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" } }, "Architectures": [ @@ -300,26 +320,34 @@ ], "instructions": [ [ - "FSCALE" + "SABA" + ], + [ + "MOVPRFX", + "SABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vscaleq_f32", + "SIMD_ISA": "SVE2", + "name": "svaba[_n_s8]", "arguments": [ - "float32x4_t a", - "int32x4_t b" + "svint8_t op1", + "svint8_t op2", + "int8_t op3" ], "return_type": { - "value": "float32x4_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ @@ -327,26 +355,34 @@ ], "instructions": [ [ - "FSCALE" + "SABA" + ], + [ + "MOVPRFX", + "SABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vscaleq_f64", + "SIMD_ISA": "SVE2", + "name": "svaba[_n_u16]", "arguments": [ - "float64x2_t a", - "int64x2_t b" + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" ], "return_type": { - "value": "float64x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ @@ -354,228 +390,244 @@ ], "instructions": [ [ - "FSCALE" + "UABA" + ], + [ + "MOVPRFX", + "UABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaba_s16", + "SIMD_ISA": "SVE2", + "name": "svaba[_n_u32]", "arguments": [ - "int16x4_t a", - "int16x4_t b", - "int16x4_t c" + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" ], "return_type": { - "value": "int16x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.S" }, - "c": { - "register": "Vm.4H" + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABA" + "UABA" + ], + [ + "MOVPRFX", + "UABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaba_s32", + "SIMD_ISA": "SVE2", + "name": "svaba[_n_u64]", "arguments": [ - "int32x2_t a", - "int32x2_t b", - "int32x2_t c" + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" ], "return_type": { - "value": "int32x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.D" }, - "c": { - "register": "Vm.2S" + "op3": { + "register": "Zop3.D[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABA" + "UABA" + ], + [ + "MOVPRFX", + "UABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaba_s8", + "SIMD_ISA": "SVE2", + "name": "svaba[_n_u8]", "arguments": [ - "int8x8_t a", - "int8x8_t b", - "int8x8_t c" + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" ], "return_type": { - "value": "int8x8_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.B" }, - "c": { - "register": "Vm.8B" + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABA" + "UABA" + ], + [ + "MOVPRFX", + "UABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaba_u16", + "SIMD_ISA": "SVE2", + "name": "svaba[_s16]", "arguments": [ - "uint16x4_t a", - "uint16x4_t b", - "uint16x4_t c" + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" ], "return_type": { - "value": "uint16x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.H" }, - "c": { - "register": "Vm.4H" + "op3": { + "register": "Zop3.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABA" + "SABA" + ], + [ + "MOVPRFX", + "SABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaba_u32", + "SIMD_ISA": "SVE2", + "name": "svaba[_s32]", "arguments": [ - "uint32x2_t a", - "uint32x2_t b", - "uint32x2_t c" + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" ], "return_type": { - "value": "uint32x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.S" }, - "c": { - "register": "Vm.2S" + "op3": { + "register": "Zop3.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABA" + "SABA" + ], + [ + "MOVPRFX", + "SABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaba_u8", + "SIMD_ISA": "SVE2", + "name": "svaba[_s64]", "arguments": [ - "uint8x8_t a", - "uint8x8_t b", - "uint8x8_t c" + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" ], "return_type": { - "value": "uint8x8_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D" }, - "c": { - "register": "Vm.8B" + "op3": { + "register": "Zop3.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABA" + "SABA" + ], + [ + "MOVPRFX", + "SABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_high_s16", + "SIMD_ISA": "SVE2", + "name": "svaba[_s8]", "arguments": [ - "int32x4_t a", - "int16x8_t b", - "int16x8_t c" + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" ], "return_type": { - "value": "int32x4_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.B" }, - "c": { - "register": "Vm.8H" + "op3": { + "register": "Zop3.B" } }, "Architectures": [ @@ -583,30 +635,34 @@ ], "instructions": [ [ - "SABAL2" + "SABA" + ], + [ + "MOVPRFX", + "SABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_high_s32", + "SIMD_ISA": "SVE2", + "name": "svaba[_u16]", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32x4_t c" + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" ], "return_type": { - "value": "int64x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.4S" + "op2": { + "register": "Zop2.H" }, - "c": { - "register": "Vm.4S" + "op3": { + "register": "Zop3.H" } }, "Architectures": [ @@ -614,30 +670,34 @@ ], "instructions": [ [ - "SABAL2" + "UABA" + ], + [ + "MOVPRFX", + "UABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_high_s8", + "SIMD_ISA": "SVE2", + "name": "svaba[_u32]", "arguments": [ - "int16x8_t a", - "int8x16_t b", - "int8x16_t c" + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" ], "return_type": { - "value": "int16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.S" }, - "c": { - "register": "Vm.16B" + "op3": { + "register": "Zop3.S" } }, "Architectures": [ @@ -645,30 +705,34 @@ ], "instructions": [ [ - "SABAL2" + "UABA" + ], + [ + "MOVPRFX", + "UABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_high_u16", + "SIMD_ISA": "SVE2", + "name": "svaba[_u64]", "arguments": [ - "uint32x4_t a", - "uint16x8_t b", - "uint16x8_t c" + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.D" }, - "c": { - "register": "Vm.8H" + "op3": { + "register": "Zop3.D" } }, "Architectures": [ @@ -676,30 +740,34 @@ ], "instructions": [ [ - "UABAL2" + "UABA" + ], + [ + "MOVPRFX", + "UABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_high_u32", + "SIMD_ISA": "SVE2", + "name": "svaba[_u8]", "arguments": [ - "uint64x2_t a", - "uint32x4_t b", - "uint32x4_t c" + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vn.4S" + "op2": { + "register": "Zop2.B" }, - "c": { - "register": "Vm.4S" + "op3": { + "register": "Zop3.B" } }, "Architectures": [ @@ -707,30 +775,34 @@ ], "instructions": [ [ - "UABAL2" + "UABA" + ], + [ + "MOVPRFX", + "UABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_high_u8", + "SIMD_ISA": "SVE2", + "name": "svabalb[_n_s16]", "arguments": [ - "uint16x8_t a", - "uint8x16_t b", - "uint8x16_t c" + "svint16_t op1", + "svint8_t op2", + "int8_t op3" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.B" }, - "c": { - "register": "Vm.16B" + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ @@ -738,479 +810,524 @@ ], "instructions": [ [ - "UABAL2" + "SABALB" + ], + [ + "MOVPRFX", + "SABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_s16", + "SIMD_ISA": "SVE2", + "name": "svabalb[_n_s32]", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16x4_t c" + "svint32_t op1", + "svint16_t op2", + "int16_t op3" ], "return_type": { - "value": "int32x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.H" }, - "c": { - "register": "Vm.4H" + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABAL" + "SABALB" + ], + [ + "MOVPRFX", + "SABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_s32", + "SIMD_ISA": "SVE2", + "name": "svabalb[_n_s64]", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32x2_t c" + "svint64_t op1", + "svint32_t op2", + "int32_t op3" ], "return_type": { - "value": "int64x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.S" }, - "c": { - "register": "Vm.2S" + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABAL" + "SABALB" + ], + [ + "MOVPRFX", + "SABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_s8", + "SIMD_ISA": "SVE2", + "name": "svabalb[_n_u16]", "arguments": [ - "int16x8_t a", - "int8x8_t b", - "int8x8_t c" + "svuint16_t op1", + "svuint8_t op2", + "uint8_t op3" ], "return_type": { - "value": "int16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.B" }, - "c": { - "register": "Vm.8B" + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABAL" + "UABALB" + ], + [ + "MOVPRFX", + "UABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_u16", + "SIMD_ISA": "SVE2", + "name": "svabalb[_n_u32]", "arguments": [ - "uint32x4_t a", - "uint16x4_t b", - "uint16x4_t c" + "svuint32_t op1", + "svuint16_t op2", + "uint16_t op3" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.H" }, - "c": { - "register": "Vm.4H" + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABAL" + "UABALB" + ], + [ + "MOVPRFX", + "UABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_u32", + "SIMD_ISA": "SVE2", + "name": "svabalb[_n_u64]", "arguments": [ - "uint64x2_t a", - "uint32x2_t b", - "uint32x2_t c" + "svuint64_t op1", + "svuint32_t op2", + "uint32_t op3" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.S" }, - "c": { - "register": "Vm.2S" + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABAL" + "UABALB" + ], + [ + "MOVPRFX", + "UABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_u8", + "SIMD_ISA": "SVE2", + "name": "svabalb[_s16]", "arguments": [ - "uint16x8_t a", - "uint8x8_t b", - "uint8x8_t c" + "svint16_t op1", + "svint8_t op2", + "svint8_t op3" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.B" }, - "c": { - "register": "Vm.8B" + "op3": { + "register": "Zop3.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABAL" + "SABALB" + ], + [ + "MOVPRFX", + "SABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabaq_s16", + "SIMD_ISA": "SVE2", + "name": "svabalb[_s32]", "arguments": [ - "int16x8_t a", - "int16x8_t b", - "int16x8_t c" + "svint32_t op1", + "svint16_t op2", + "svint16_t op3" ], "return_type": { - "value": "int16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.H" }, - "c": { - "register": "Vm.8H" + "op3": { + "register": "Zop3.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABA" + "SABALB" + ], + [ + "MOVPRFX", + "SABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabaq_s32", + "SIMD_ISA": "SVE2", + "name": "svabalb[_s64]", "arguments": [ - "int32x4_t a", - "int32x4_t b", - "int32x4_t c" + "svint64_t op1", + "svint32_t op2", + "svint32_t op3" ], "return_type": { - "value": "int32x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.4S" + "op2": { + "register": "Zop2.S" }, - "c": { - "register": "Vm.4S" + "op3": { + "register": "Zop3.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABA" + "SABALB" + ], + [ + "MOVPRFX", + "SABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabaq_s8", + "SIMD_ISA": "SVE2", + "name": "svabalb[_u16]", "arguments": [ - "int8x16_t a", - "int8x16_t b", - "int8x16_t c" + "svuint16_t op1", + "svuint8_t op2", + "svuint8_t op3" ], "return_type": { - "value": "int8x16_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.B" }, - "c": { - "register": "Vm.16B" + "op3": { + "register": "Zop3.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABA" + "UABALB" + ], + [ + "MOVPRFX", + "UABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabaq_u16", + "SIMD_ISA": "SVE2", + "name": "svabalb[_u32]", "arguments": [ - "uint16x8_t a", - "uint16x8_t b", - "uint16x8_t c" + "svuint32_t op1", + "svuint16_t op2", + "svuint16_t op3" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.H" }, - "c": { - "register": "Vm.8H" + "op3": { + "register": "Zop3.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABA" + "UABALB" + ], + [ + "MOVPRFX", + "UABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabaq_u32", + "SIMD_ISA": "SVE2", + "name": "svabalb[_u64]", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t c" + "svuint64_t op1", + "svuint32_t op2", + "svuint32_t op3" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.4S" + "op2": { + "register": "Zop2.S" }, - "c": { - "register": "Vm.4S" + "op3": { + "register": "Zop3.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABA" + "UABALB" + ], + [ + "MOVPRFX", + "UABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabaq_u8", + "SIMD_ISA": "SVE2", + "name": "svabalt[_n_s16]", "arguments": [ - "uint8x16_t a", - "uint8x16_t b", - "uint8x16_t c" + "svint16_t op1", + "svint8_t op2", + "int8_t op3" ], "return_type": { - "value": "uint8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.B" }, - "c": { - "register": "Vm.16B" + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABA" + "SABALT" + ], + [ + "MOVPRFX", + "SABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabd_f16", + "SIMD_ISA": "SVE2", + "name": "svabalt[_n_s32]", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svint32_t op1", + "svint16_t op2", + "int16_t op3" ], "return_type": { - "value": "float16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FABD" + "SABALT" + ], + [ + "MOVPRFX", + "SABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabd_f32", + "SIMD_ISA": "SVE2", + "name": "svabalt[_n_s64]", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svint64_t op1", + "svint32_t op2", + "int32_t op3" ], "return_type": { - "value": "float32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FABD" + "SABALT" + ], + [ + "MOVPRFX", + "SABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabd_f64", + "SIMD_ISA": "SVE2", + "name": "svabalt[_n_u16]", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svuint16_t op1", + "svuint8_t op2", + "uint8_t op3" ], "return_type": { - "value": "float64x1_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ @@ -1218,200 +1335,244 @@ ], "instructions": [ [ - "FABD" + "UABALT" + ], + [ + "MOVPRFX", + "UABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabd_s16", + "SIMD_ISA": "SVE2", + "name": "svabalt[_n_u32]", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "svuint32_t op1", + "svuint16_t op2", + "uint16_t op3" ], "return_type": { - "value": "int16x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABD" + "UABALT" + ], + [ + "MOVPRFX", + "UABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabd_s32", + "SIMD_ISA": "SVE2", + "name": "svabalt[_n_u64]", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "svuint64_t op1", + "svuint32_t op2", + "uint32_t op3" ], "return_type": { - "value": "int32x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABD" + "UABALT" + ], + [ + "MOVPRFX", + "UABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabd_s8", + "SIMD_ISA": "SVE2", + "name": "svabalt[_s16]", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "svint16_t op1", + "svint8_t op2", + "svint8_t op3" ], "return_type": { - "value": "int8x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABD" + "SABALT" + ], + [ + "MOVPRFX", + "SABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabd_u16", + "SIMD_ISA": "SVE2", + "name": "svabalt[_s32]", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "svint32_t op1", + "svint16_t op2", + "svint16_t op3" ], "return_type": { - "value": "uint16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABD" + "SABALT" + ], + [ + "MOVPRFX", + "SABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabd_u32", + "SIMD_ISA": "SVE2", + "name": "svabalt[_s64]", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "svint64_t op1", + "svint32_t op2", + "svint32_t op3" ], "return_type": { - "value": "uint32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABD" + "SABALT" + ], + [ + "MOVPRFX", + "SABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabd_u8", + "SIMD_ISA": "SVE2", + "name": "svabalt[_u16]", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "svuint16_t op1", + "svuint8_t op2", + "svuint8_t op3" ], "return_type": { - "value": "uint8x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABD" + "UABALT" + ], + [ + "MOVPRFX", + "UABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdd_f64", + "SIMD_ISA": "SVE2", + "name": "svabalt[_u32]", "arguments": [ - "float64_t a", - "float64_t b" + "svuint32_t op1", + "svuint16_t op2", + "svuint16_t op3" ], "return_type": { - "value": "float64_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" } }, "Architectures": [ @@ -1419,26 +1580,34 @@ ], "instructions": [ [ - "FABD" + "UABALT" + ], + [ + "MOVPRFX", + "UABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdh_f16", + "SIMD_ISA": "SVE2", + "name": "svabalt[_u64]", "arguments": [ - "float16_t a", - "float16_t b" + "svuint64_t op1", + "svuint32_t op2", + "svuint32_t op3" ], "return_type": { - "value": "float16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Hm" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" } }, "Architectures": [ @@ -1446,26 +1615,34 @@ ], "instructions": [ [ - "FABD" + "UABALT" + ], + [ + "MOVPRFX", + "UABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_high_s16", + "SIMD_ISA": "SVE", + "name": "svabd[_f16]_m", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -1473,26 +1650,34 @@ ], "instructions": [ [ - "SABDL2" + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_high_s32", + "SIMD_ISA": "SVE", + "name": "svabd[_f16]_x", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -1500,26 +1685,37 @@ ], "instructions": [ [ - "SABDL2" + "FABD" + ], + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_high_s8", + "SIMD_ISA": "SVE", + "name": "svabd[_f16]_z", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -1527,26 +1723,35 @@ ], "instructions": [ [ - "SABDL2" + "MOVPRFX", + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_high_u16", + "SIMD_ISA": "SVE", + "name": "svabd[_f32]_m", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -1554,26 +1759,34 @@ ], "instructions": [ [ - "UABDL2" + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_high_u32", + "SIMD_ISA": "SVE", + "name": "svabd[_f32]_x", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -1581,26 +1794,37 @@ ], "instructions": [ [ - "UABDL2" + "FABD" + ], + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_high_u8", + "SIMD_ISA": "SVE", + "name": "svabd[_f32]_z", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -1608,257 +1832,326 @@ ], "instructions": [ [ - "UABDL2" + "MOVPRFX", + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_s16", + "SIMD_ISA": "SVE", + "name": "svabd[_f64]_m", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABDL" + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_s32", + "SIMD_ISA": "SVE", + "name": "svabd[_f64]_x", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABDL" + "FABD" + ], + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_s8", + "SIMD_ISA": "SVE", + "name": "svabd[_f64]_z", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABDL" + "MOVPRFX", + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_u16", + "SIMD_ISA": "SVE", + "name": "svabd[_n_f16]_m", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABDL" + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_u32", + "SIMD_ISA": "SVE", + "name": "svabd[_n_f16]_x", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABDL" + "FABD" + ], + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_u8", + "SIMD_ISA": "SVE", + "name": "svabd[_n_f16]_z", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABDL" + "MOVPRFX", + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdq_f16", + "SIMD_ISA": "SVE", + "name": "svabd[_n_f32]_m", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdq_f32", + "SIMD_ISA": "SVE", + "name": "svabd[_n_f32]_x", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ "FABD" + ], + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdq_f64", + "SIMD_ISA": "SVE", + "name": "svabd[_n_f32]_z", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -1866,200 +2159,253 @@ ], "instructions": [ [ + "MOVPRFX", + "FABD" + ], + [ + "MOVPRFX", "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdq_s16", + "SIMD_ISA": "SVE", + "name": "svabd[_n_f64]_m", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABD" + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdq_s32", + "SIMD_ISA": "SVE", + "name": "svabd[_n_f64]_x", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABD" + "FABD" + ], + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdq_s8", + "SIMD_ISA": "SVE", + "name": "svabd[_n_f64]_z", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "int8x16_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABD" + "MOVPRFX", + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdq_u16", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s16]_m", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABD" + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdq_u32", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s16]_x", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABD" + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdq_u8", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s16]_z", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABD" + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabds_f32", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s32]_m", "arguments": [ - "float32_t a", - "float32_t b" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "float32_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Sm" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -2067,71 +2413,108 @@ ], "instructions": [ [ - "FABD" + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabs_f16", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s32]_x", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "float16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FABS" + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabs_f32", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s32]_z", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FABS" + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabs_f64", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s64]_m", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "float64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -2139,72 +2522,108 @@ ], "instructions": [ [ - "FABS" + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabs_s16", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s64]_x", "arguments": [ - "int16x4_t a" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ABS" + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabs_s32", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s64]_z", "arguments": [ - "int32x2_t a" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ABS" - ] - ] + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] }, { - "SIMD_ISA": "Neon", - "name": "vabs_s64", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s8]_m", "arguments": [ - "int64x1_t a" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "int64x1_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -2212,47 +2631,72 @@ ], "instructions": [ [ - "ABS" + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabs_s8", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s8]_x", "arguments": [ - "int8x8_t a" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "int8x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ABS" + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabsd_s64", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s8]_z", "arguments": [ - "int64_t a" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "int64_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -2260,95 +2704,144 @@ ], "instructions": [ [ - "ABS" + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabsh_f16", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u16]_m", "arguments": [ - "float16_t a" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "float16_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FABS" + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabsq_f16", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u16]_x", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FABS" + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabsq_f32", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u16]_z", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FABS" + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabsq_f64", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u32]_m", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -2356,72 +2849,108 @@ ], "instructions": [ [ - "FABS" + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabsq_s16", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u32]_x", "arguments": [ - "int16x8_t a" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ABS" + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabsq_s32", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u32]_z", "arguments": [ - "int32x4_t a" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ABS" + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabsq_s64", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u64]_m", "arguments": [ - "int64x2_t a" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -2429,108 +2958,143 @@ ], "instructions": [ [ - "ABS" + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabsq_s8", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u64]_x", "arguments": [ - "int8x16_t a" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "int8x16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ABS" + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_f16", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u64]_z", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "float16x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FADD" + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_f32", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u8]_m", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FADD" + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_f64", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u8]_x", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "float64x1_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -2538,345 +3102,435 @@ ], "instructions": [ [ - "FADD" + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_p16", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u8]_z", "arguments": [ - "poly16x4_t a", - "poly16x4_t b" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "poly16x4_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "EOR" + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_p64", + "SIMD_ISA": "SVE", + "name": "svabd[_s16]_m", "arguments": [ - "poly64x1_t a", - "poly64x1_t b" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "poly64x1_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "EOR" + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_p8", + "SIMD_ISA": "SVE", + "name": "svabd[_s16]_x", "arguments": [ - "poly8x8_t a", - "poly8x8_t b" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "poly8x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "EOR" + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_s16", + "SIMD_ISA": "SVE", + "name": "svabd[_s16]_z", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_s32", + "SIMD_ISA": "SVE", + "name": "svabd[_s32]_m", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_s64", + "SIMD_ISA": "SVE", + "name": "svabd[_s32]_x", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "int64x1_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_s8", + "SIMD_ISA": "SVE", + "name": "svabd[_s32]_z", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "int8x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_u16", + "SIMD_ISA": "SVE", + "name": "svabd[_s64]_m", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_u32", + "SIMD_ISA": "SVE", + "name": "svabd[_s64]_x", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_u64", + "SIMD_ISA": "SVE", + "name": "svabd[_s64]_z", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_u8", + "SIMD_ISA": "SVE", + "name": "svabd[_s8]_m", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddd_s64", + "SIMD_ISA": "SVE", + "name": "svabd[_s8]_x", "arguments": [ - "int64_t a", - "int64_t b" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "int64_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -2884,26 +3538,37 @@ ], "instructions": [ [ - "ADD" + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddd_u64", + "SIMD_ISA": "SVE", + "name": "svabd[_s8]_z", "arguments": [ - "uint64_t a", - "uint64_t b" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -2911,58 +3576,70 @@ ], "instructions": [ [ - "ADD" + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddh_f16", + "SIMD_ISA": "SVE", + "name": "svabd[_u16]_m", "arguments": [ - "float16_t a", - "float16_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "float16_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Hm" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FADD" + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_high_s16", + "SIMD_ISA": "SVE", + "name": "svabd[_u16]_x", "arguments": [ - "int8x8_t r", - "int16x8_t a", - "int16x8_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "int8x16_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H|Ztied2.H" }, - "r": { - "register": "Vd.8B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -2970,30 +3647,37 @@ ], "instructions": [ [ - "ADDHN2" + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_high_s32", + "SIMD_ISA": "SVE", + "name": "svabd[_u16]_z", "arguments": [ - "int16x4_t r", - "int32x4_t a", - "int32x4_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.H" }, - "r": { - "register": "Vd.4H" + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -3001,30 +3685,35 @@ ], "instructions": [ [ - "ADDHN2" + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_high_s64", + "SIMD_ISA": "SVE", + "name": "svabd[_u32]_m", "arguments": [ - "int32x2_t r", - "int64x2_t a", - "int64x2_t b" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.S" }, - "r": { - "register": "Vd.2S" + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -3032,30 +3721,34 @@ ], "instructions": [ [ - "ADDHN2" + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_high_u16", + "SIMD_ISA": "SVE", + "name": "svabd[_u32]_x", "arguments": [ - "uint8x8_t r", - "uint16x8_t a", - "uint16x8_t b" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.S|Ztied2.S" }, - "r": { - "register": "Vd.8B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -3063,30 +3756,37 @@ ], "instructions": [ [ - "ADDHN2" + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_high_u32", + "SIMD_ISA": "SVE", + "name": "svabd[_u32]_z", "arguments": [ - "uint16x4_t r", - "uint32x4_t a", - "uint32x4_t b" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S" }, - "r": { - "register": "Vd.4H" + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -3094,30 +3794,35 @@ ], "instructions": [ [ - "ADDHN2" + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_high_u64", + "SIMD_ISA": "SVE", + "name": "svabd[_u64]_m", "arguments": [ - "uint32x2_t r", - "uint64x2_t a", - "uint64x2_t b" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.D" }, - "r": { - "register": "Vd.2S" + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -3125,200 +3830,240 @@ ], "instructions": [ [ - "ADDHN2" + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_s16", + "SIMD_ISA": "SVE", + "name": "svabd[_u64]_x", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int8x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDHN" + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_s32", + "SIMD_ISA": "SVE", + "name": "svabd[_u64]_z", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDHN" + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_s64", + "SIMD_ISA": "SVE", + "name": "svabd[_u8]_m", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDHN" + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_u16", + "SIMD_ISA": "SVE", + "name": "svabd[_u8]_x", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDHN" + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_u32", + "SIMD_ISA": "SVE", + "name": "svabd[_u8]_z", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDHN" + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_u64", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_n_s16]", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDHN" + "SABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_high_s16", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_n_s32]", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -3326,26 +4071,26 @@ ], "instructions": [ [ - "SADDL2" + "SABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_high_s32", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_n_s64]", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ @@ -3353,26 +4098,26 @@ ], "instructions": [ [ - "SADDL2" + "SABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_high_s8", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_n_u16]", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ @@ -3380,26 +4125,26 @@ ], "instructions": [ [ - "SADDL2" + "UABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_high_u16", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_n_u32]", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -3407,26 +4152,26 @@ ], "instructions": [ [ - "UADDL2" + "UABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_high_u32", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_n_u64]", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ @@ -3434,26 +4179,26 @@ ], "instructions": [ [ - "UADDL2" + "UABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_high_u8", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_s16]", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -3461,196 +4206,188 @@ ], "instructions": [ [ - "UADDL2" + "SABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_s16", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_s32]", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDL" + "SABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_s32", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_s64]", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDL" + "SABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_s8", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_u16]", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDL" + "UABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_u16", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_u32]", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDL" + "UABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_u32", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_u64]", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDL" + "UABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_u8", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_n_s16]", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDL" + "SABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlv_s16", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_n_s32]", "arguments": [ - "int16x4_t a" + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "int32_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -3658,22 +4395,26 @@ ], "instructions": [ [ - "SADDLV" + "SABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlv_s32", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_n_s64]", "arguments": [ - "int32x2_t a" + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "int64_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ @@ -3681,22 +4422,26 @@ ], "instructions": [ [ - "SADDLP" + "SABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlv_s8", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_n_u16]", "arguments": [ - "int8x8_t a" + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "int16_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ @@ -3704,22 +4449,26 @@ ], "instructions": [ [ - "SADDLV" + "UABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlv_u16", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_n_u32]", "arguments": [ - "uint16x4_t a" + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -3727,22 +4476,26 @@ ], "instructions": [ [ - "UADDLV" + "UABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlv_u32", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_n_u64]", "arguments": [ - "uint32x2_t a" + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ @@ -3750,22 +4503,26 @@ ], "instructions": [ [ - "UADDLP" + "UABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlv_u8", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_s16]", "arguments": [ - "uint8x8_t a" + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -3773,22 +4530,26 @@ ], "instructions": [ [ - "UADDLV" + "SABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlvq_s16", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_s32]", "arguments": [ - "int16x8_t a" + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "int32_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -3796,22 +4557,26 @@ ], "instructions": [ [ - "SADDLV" + "SABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlvq_s32", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_s64]", "arguments": [ - "int32x4_t a" + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "int64_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" } }, "Architectures": [ @@ -3819,22 +4584,26 @@ ], "instructions": [ [ - "SADDLV" + "SABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlvq_s8", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_u16]", "arguments": [ - "int8x16_t a" + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "int16_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -3842,22 +4611,26 @@ ], "instructions": [ [ - "SADDLV" + "UABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlvq_u16", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_u32]", "arguments": [ - "uint16x8_t a" + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -3865,22 +4638,26 @@ ], "instructions": [ [ - "UADDLV" + "UABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlvq_u32", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_u64]", "arguments": [ - "uint32x4_t a" + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" } }, "Architectures": [ @@ -3888,22 +4665,30 @@ ], "instructions": [ [ - "UADDLV" + "UABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlvq_u8", + "SIMD_ISA": "SVE", + "name": "svabs[_f16]_m", "arguments": [ - "uint8x16_t a" + "svfloat16_t inactive", + "svbool_t pg", + "svfloat16_t op" ], "return_type": { - "value": "uint16_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -3911,83 +4696,93 @@ ], "instructions": [ [ - "UADDLV" + "FABS" + ], + [ + "MOVPRFX", + "FABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_f16", + "SIMD_ISA": "SVE", + "name": "svabs[_f16]_x", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svbool_t pg", + "svfloat16_t op" ], "return_type": { - "value": "float16x8_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op": { + "register": "Zop.H|Ztied.H" }, - "b": { - "register": "Vm.8H" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FADD" + "FABS" + ], + [ + "MOVPRFX", + "FABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_f32", + "SIMD_ISA": "SVE", + "name": "svabs[_f16]_z", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svbool_t pg", + "svfloat16_t op" ], "return_type": { - "value": "float32x4_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op": { + "register": "Zop.H" }, - "b": { - "register": "Vm.4S" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FADD" + "MOVPRFX", + "FABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_f64", + "SIMD_ISA": "SVE", + "name": "svabs[_f32]_m", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svfloat32_t inactive", + "svbool_t pg", + "svfloat32_t op" ], "return_type": { - "value": "float64x2_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "inactive": { + "register": "Zinactive.S|Ztied.S" }, - "b": { - "register": "Vm.2D" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -3995,370 +4790,406 @@ ], "instructions": [ [ - "FADD" + "FABS" + ], + [ + "MOVPRFX", + "FABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_p128", + "SIMD_ISA": "SVE", + "name": "svabs[_f32]_x", "arguments": [ - "poly128_t a", - "poly128_t b" + "svbool_t pg", + "svfloat32_t op" ], "return_type": { - "value": "poly128_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op": { + "register": "Zop.S|Ztied.S" }, - "b": { - "register": "Vm.16B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "EOR" + "FABS" + ], + [ + "MOVPRFX", + "FABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_p16", + "SIMD_ISA": "SVE", + "name": "svabs[_f32]_z", "arguments": [ - "poly16x8_t a", - "poly16x8_t b" + "svbool_t pg", + "svfloat32_t op" ], "return_type": { - "value": "poly16x8_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op": { + "register": "Zop.S" }, - "b": { - "register": "Vm.16B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "EOR" + "MOVPRFX", + "FABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_p64", + "SIMD_ISA": "SVE", + "name": "svabs[_f64]_m", "arguments": [ - "poly64x2_t a", - "poly64x2_t b" + "svfloat64_t inactive", + "svbool_t pg", + "svfloat64_t op" ], "return_type": { - "value": "poly64x2_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "inactive": { + "register": "Zinactive.D|Ztied.D" }, - "b": { - "register": "Vm.16B" + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "EOR" + "FABS" + ], + [ + "MOVPRFX", + "FABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_p8", + "SIMD_ISA": "SVE", + "name": "svabs[_f64]_x", "arguments": [ - "poly8x16_t a", - "poly8x16_t b" + "svbool_t pg", + "svfloat64_t op" ], "return_type": { - "value": "poly8x16_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op": { + "register": "Zop.D|Ztied.D" }, - "b": { - "register": "Vm.16B" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "EOR" + "FABS" + ], + [ + "MOVPRFX", + "FABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_s16", + "SIMD_ISA": "SVE", + "name": "svabs[_f64]_z", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "svbool_t pg", + "svfloat64_t op" ], "return_type": { - "value": "int16x8_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op": { + "register": "Zop.D" }, - "b": { - "register": "Vm.8H" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "MOVPRFX", + "FABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_s32", + "SIMD_ISA": "SVE", + "name": "svabs[_s16]_m", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "svint16_t inactive", + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "int32x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "inactive": { + "register": "Zinactive.H|Ztied.H" }, - "b": { - "register": "Vm.4S" + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "ABS" + ], + [ + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_s64", + "SIMD_ISA": "SVE", + "name": "svabs[_s16]_x", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "int64x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op": { + "register": "Zop.H|Ztied.H" }, - "b": { - "register": "Vm.2D" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "ABS" + ], + [ + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_s8", + "SIMD_ISA": "SVE", + "name": "svabs[_s16]_z", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "int8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op": { + "register": "Zop.H" }, - "b": { - "register": "Vm.16B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_u16", + "SIMD_ISA": "SVE", + "name": "svabs[_s32]_m", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "svint32_t inactive", + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "uint16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "inactive": { + "register": "Zinactive.S|Ztied.S" }, - "b": { - "register": "Vm.8H" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "ABS" + ], + [ + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_u32", + "SIMD_ISA": "SVE", + "name": "svabs[_s32]_x", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "uint32x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op": { + "register": "Zop.S|Ztied.S" }, - "b": { - "register": "Vm.4S" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "ABS" + ], + [ + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_u64", + "SIMD_ISA": "SVE", + "name": "svabs[_s32]_z", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "uint64x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op": { + "register": "Zop.S" }, - "b": { - "register": "Vm.2D" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_u8", + "SIMD_ISA": "SVE", + "name": "svabs[_s64]_m", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "svint64_t inactive", + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "uint8x16_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "inactive": { + "register": "Zinactive.D|Ztied.D" }, - "b": { - "register": "Vm.16B" + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "ABS" + ], + [ + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddv_f32", + "SIMD_ISA": "SVE", + "name": "svabs[_s64]_x", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "float32_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -4366,22 +5197,30 @@ ], "instructions": [ [ - "FADDP" + "ABS" + ], + [ + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddv_s16", + "SIMD_ISA": "SVE", + "name": "svabs[_s64]_z", "arguments": [ - "int16x4_t a" + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "int16_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -4389,22 +5228,31 @@ ], "instructions": [ [ - "ADDV" + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddv_s32", + "SIMD_ISA": "SVE", + "name": "svabs[_s8]_m", "arguments": [ - "int32x2_t a" + "svint8_t inactive", + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "int32_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "inactive": { + "register": "Zinactive.B|Ztied.B" + }, + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -4412,22 +5260,30 @@ ], "instructions": [ [ - "ADDP" + "ABS" + ], + [ + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddv_s8", + "SIMD_ISA": "SVE", + "name": "svabs[_s8]_x", "arguments": [ - "int8x8_t a" + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "int8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op": { + "register": "Zop.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -4435,22 +5291,30 @@ ], "instructions": [ [ - "ADDV" + "ABS" + ], + [ + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddv_u16", + "SIMD_ISA": "SVE", + "name": "svabs[_s8]_z", "arguments": [ - "uint16x4_t a" + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "uint16_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -4458,22 +5322,31 @@ ], "instructions": [ [ - "ADDV" + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddv_u32", + "SIMD_ISA": "SVE", + "name": "svacge[_f16]", "arguments": [ - "uint32x2_t a" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -4481,22 +5354,30 @@ ], "instructions": [ [ - "ADDP" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddv_u8", + "SIMD_ISA": "SVE", + "name": "svacge[_f32]", "arguments": [ - "uint8x8_t a" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "uint8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -4504,22 +5385,30 @@ ], "instructions": [ [ - "ADDV" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddvq_f32", + "SIMD_ISA": "SVE", + "name": "svacge[_f64]", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "float32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -4527,23 +5416,30 @@ ], "instructions": [ [ - "FADDP", - "FADDP" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddvq_f64", + "SIMD_ISA": "SVE", + "name": "svacge[_n_f16]", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "float64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -4551,22 +5447,30 @@ ], "instructions": [ [ - "FADDP" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddvq_s16", + "SIMD_ISA": "SVE", + "name": "svacge[_n_f32]", "arguments": [ - "int16x8_t a" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "int16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -4574,22 +5478,30 @@ ], "instructions": [ [ - "ADDV" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddvq_s32", + "SIMD_ISA": "SVE", + "name": "svacge[_n_f64]", "arguments": [ - "int32x4_t a" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "int32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -4597,22 +5509,30 @@ ], "instructions": [ [ - "ADDV" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddvq_s64", + "SIMD_ISA": "SVE", + "name": "svacgt[_f16]", "arguments": [ - "int64x2_t a" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "int64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -4620,22 +5540,30 @@ ], "instructions": [ [ - "ADDP" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddvq_s8", + "SIMD_ISA": "SVE", + "name": "svacgt[_f32]", "arguments": [ - "int8x16_t a" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "int8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -4643,22 +5571,30 @@ ], "instructions": [ [ - "ADDV" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddvq_u16", + "SIMD_ISA": "SVE", + "name": "svacgt[_f64]", "arguments": [ - "uint16x8_t a" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -4666,22 +5602,30 @@ ], "instructions": [ [ - "ADDV" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddvq_u32", + "SIMD_ISA": "SVE", + "name": "svacgt[_n_f16]", "arguments": [ - "uint32x4_t a" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -4689,22 +5633,30 @@ ], "instructions": [ [ - "ADDV" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddvq_u64", + "SIMD_ISA": "SVE", + "name": "svacgt[_n_f32]", "arguments": [ - "uint64x2_t a" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -4712,22 +5664,30 @@ ], "instructions": [ [ - "ADDP" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddvq_u8", + "SIMD_ISA": "SVE", + "name": "svacgt[_n_f64]", "arguments": [ - "uint8x16_t a" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "uint8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -4735,26 +5695,30 @@ ], "instructions": [ [ - "ADDV" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_high_s16", + "SIMD_ISA": "SVE", + "name": "svacle[_f16]", "arguments": [ - "int32x4_t a", - "int16x8_t b" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -4762,26 +5726,30 @@ ], "instructions": [ [ - "SADDW2" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_high_s32", + "SIMD_ISA": "SVE", + "name": "svacle[_f32]", "arguments": [ - "int64x2_t a", - "int32x4_t b" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -4789,26 +5757,30 @@ ], "instructions": [ [ - "SADDW2" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_high_s8", + "SIMD_ISA": "SVE", + "name": "svacle[_f64]", "arguments": [ - "int16x8_t a", - "int8x16_t b" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -4816,26 +5788,30 @@ ], "instructions": [ [ - "SADDW2" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_high_u16", + "SIMD_ISA": "SVE", + "name": "svacle[_n_f16]", "arguments": [ - "uint32x4_t a", - "uint16x8_t b" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -4843,26 +5819,30 @@ ], "instructions": [ [ - "UADDW2" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_high_u32", + "SIMD_ISA": "SVE", + "name": "svacle[_n_f32]", "arguments": [ - "uint64x2_t a", - "uint32x4_t b" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -4870,26 +5850,30 @@ ], "instructions": [ [ - "UADDW2" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_high_u8", + "SIMD_ISA": "SVE", + "name": "svacle[_n_f64]", "arguments": [ - "uint16x8_t a", - "uint8x16_t b" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -4897,1518 +5881,1906 @@ ], "instructions": [ [ - "UADDW2" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_s16", + "SIMD_ISA": "SVE", + "name": "svaclt[_f16]", "arguments": [ - "int32x4_t a", - "int16x4_t b" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDW" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_s32", + "SIMD_ISA": "SVE", + "name": "svaclt[_f32]", "arguments": [ - "int64x2_t a", - "int32x2_t b" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDW" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_s8", + "SIMD_ISA": "SVE", + "name": "svaclt[_f64]", "arguments": [ - "int16x8_t a", - "int8x8_t b" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDW" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_u16", + "SIMD_ISA": "SVE", + "name": "svaclt[_n_f16]", "arguments": [ - "uint32x4_t a", - "uint16x4_t b" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDW" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_u32", + "SIMD_ISA": "SVE", + "name": "svaclt[_n_f32]", "arguments": [ - "uint64x2_t a", - "uint32x2_t b" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDW" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_u8", + "SIMD_ISA": "SVE", + "name": "svaclt[_n_f64]", "arguments": [ - "uint16x8_t a", - "uint8x8_t b" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDW" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaesdq_u8", + "SIMD_ISA": "SVE2", + "name": "svadalp[_s16]_m", "arguments": [ - "uint8x16_t data", - "uint8x16_t key" + "svbool_t pg", + "svint16_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "data": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "key": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "AESD" + "SADALP" + ], + [ + "MOVPRFX", + "SADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaeseq_u8", + "SIMD_ISA": "SVE2", + "name": "svadalp[_s16]_x", "arguments": [ - "uint8x16_t data", - "uint8x16_t key" + "svbool_t pg", + "svint16_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "data": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "key": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "AESE" + "SADALP" + ], + [ + "MOVPRFX", + "SADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaesimcq_u8", + "SIMD_ISA": "SVE2", + "name": "svadalp[_s16]_z", "arguments": [ - "uint8x16_t data" + "svbool_t pg", + "svint16_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "data": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "AESIMC" + "MOVPRFX", + "SADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaesmcq_u8", + "SIMD_ISA": "SVE2", + "name": "svadalp[_s32]_m", "arguments": [ - "uint8x16_t data" + "svbool_t pg", + "svint32_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "data": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "AESMC" + "SADALP" + ], + [ + "MOVPRFX", + "SADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vand_s16", + "SIMD_ISA": "SVE2", + "name": "svadalp[_s32]_x", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "svbool_t pg", + "svint32_t op1", + "svint16_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "SADALP" + ], + [ + "MOVPRFX", + "SADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vand_s32", + "SIMD_ISA": "SVE2", + "name": "svadalp[_s32]_z", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "svbool_t pg", + "svint32_t op1", + "svint16_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "MOVPRFX", + "SADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vand_s64", + "SIMD_ISA": "SVE2", + "name": "svadalp[_s64]_m", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "svbool_t pg", + "svint64_t op1", + "svint32_t op2" ], "return_type": { - "value": "int64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "SADALP" + ], + [ + "MOVPRFX", + "SADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vand_s8", + "SIMD_ISA": "SVE2", + "name": "svadalp[_s64]_x", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "svbool_t pg", + "svint64_t op1", + "svint32_t op2" ], "return_type": { - "value": "int8x8_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "SADALP" + ], + [ + "MOVPRFX", + "SADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vand_u16", + "SIMD_ISA": "SVE2", + "name": "svadalp[_s64]_z", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "svbool_t pg", + "svint64_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "MOVPRFX", + "SADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vand_u32", + "SIMD_ISA": "SVE2", + "name": "svadalp[_u16]_m", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "UADALP" + ], + [ + "MOVPRFX", + "UADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vand_u64", + "SIMD_ISA": "SVE2", + "name": "svadalp[_u16]_x", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "UADALP" + ], + [ + "MOVPRFX", + "UADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vand_u8", + "SIMD_ISA": "SVE2", + "name": "svadalp[_u16]_z", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "MOVPRFX", + "UADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vandq_s16", + "SIMD_ISA": "SVE2", + "name": "svadalp[_u32]_m", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "svbool_t pg", + "svuint32_t op1", + "svuint16_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "UADALP" + ], + [ + "MOVPRFX", + "UADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vandq_s32", + "SIMD_ISA": "SVE2", + "name": "svadalp[_u32]_x", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "svbool_t pg", + "svuint32_t op1", + "svuint16_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "UADALP" + ], + [ + "MOVPRFX", + "UADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vandq_s64", + "SIMD_ISA": "SVE2", + "name": "svadalp[_u32]_z", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "svbool_t pg", + "svuint32_t op1", + "svuint16_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "MOVPRFX", + "UADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vandq_s8", + "SIMD_ISA": "SVE2", + "name": "svadalp[_u64]_m", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "svbool_t pg", + "svuint64_t op1", + "svuint32_t op2" ], "return_type": { - "value": "int8x16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "UADALP" + ], + [ + "MOVPRFX", + "UADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vandq_u16", + "SIMD_ISA": "SVE2", + "name": "svadalp[_u64]_x", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "svbool_t pg", + "svuint64_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "UADALP" + ], + [ + "MOVPRFX", + "UADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vandq_u32", + "SIMD_ISA": "SVE2", + "name": "svadalp[_u64]_z", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "svbool_t pg", + "svuint64_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "MOVPRFX", + "UADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vandq_u64", + "SIMD_ISA": "SVE2", + "name": "svadclb[_n_u32]", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ - "v7", - "A32", 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"Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BIC" + "FADD" + ], + [ + "FSUB" + ], + [ + "FADD" + ], + [ + "FADD" + ], + [ + "FADD" + ], + [ + "MOVPRFX", + "FADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbicq_u8", + "SIMD_ISA": "SVE", + "name": "svadd[_n_f64]_z", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BIC" + "MOVPRFX", + "FADD" + ], + [ + "MOVPRFX", + "FSUB" + ], + [ + "MOVPRFX", + "FADD" + ], + [ + "MOVPRFX", + "FADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_f16", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s16]_m", "arguments": [ - "uint16x4_t a", - "float16x4_t b", - "float16x4_t c" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "float16x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.H[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_f32", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s16]_x", "arguments": [ - "uint32x2_t a", - "float32x2_t b", - "float32x2_t c" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_f64", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s16]_z", "arguments": [ - "uint64x1_t a", - "float64x1_t b", - "float64x1_t c" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "float64x1_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.H[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -6416,458 +7788,526 @@ ], "instructions": [ [ - "BSL" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_p16", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s32]_m", "arguments": [ - "uint16x4_t a", - "poly16x4_t b", - "poly16x4_t c" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "poly16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.S[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_p64", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s32]_x", "arguments": [ - "poly64x1_t a", - "poly64x1_t b", - "poly64x1_t c" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "poly64x1_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_p8", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s32]_z", "arguments": [ - "uint8x8_t a", - "poly8x8_t b", - "poly8x8_t c" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "poly8x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.S[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_s16", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s64]_m", "arguments": [ - "uint16x4_t a", - "int16x4_t b", - "int16x4_t c" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_s32", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s64]_x", "arguments": [ - "uint32x2_t a", - "int32x2_t b", - "int32x2_t c" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_s64", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s64]_z", "arguments": [ - "uint64x1_t a", - "int64x1_t b", - "int64x1_t c" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "int64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_s8", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s8]_m", "arguments": [ - "uint8x8_t a", - "int8x8_t b", - "int8x8_t c" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "int8x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.B[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_u16", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s8]_x", "arguments": [ - "uint16x4_t a", - "uint16x4_t b", - "uint16x4_t c" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_u32", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s8]_z", "arguments": [ - "uint32x2_t a", - "uint32x2_t b", - "uint32x2_t c" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.B[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_u64", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u16]_m", "arguments": [ - "uint64x1_t a", - "uint64x1_t b", - "uint64x1_t c" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.H[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_u8", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u16]_x", "arguments": [ - "uint8x8_t a", - "uint8x8_t b", - "uint8x8_t c" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_f16", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u16]_z", "arguments": [ - "uint16x8_t a", - "float16x8_t b", - "float16x8_t c" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.H[*]" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_f32", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u32]_m", "arguments": [ - "uint32x4_t a", - "float32x4_t b", - "float32x4_t c" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.S[*]" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_f64", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u32]_x", "arguments": [ - "uint64x2_t a", - "float64x2_t b", - "float64x2_t c" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -6875,556 +8315,665 @@ ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_p16", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u32]_z", "arguments": [ - "uint16x8_t a", - "poly16x8_t b", - "poly16x8_t c" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "poly16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.S[*]" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_p64", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u64]_m", "arguments": [ - "poly64x2_t a", - "poly64x2_t b", - "poly64x2_t c" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "poly64x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.D[*]" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_p8", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u64]_x", "arguments": [ - "uint8x16_t a", - "poly8x16_t b", - "poly8x16_t c" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "poly8x16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_s16", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u64]_z", "arguments": [ - "uint16x8_t a", - "int16x8_t b", - "int16x8_t c" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.D[*]" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_s32", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u8]_m", "arguments": [ - "uint32x4_t a", - "int32x4_t b", - "int32x4_t c" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.B[*]" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_s64", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u8]_x", "arguments": [ - "uint64x2_t a", - "int64x2_t b", - "int64x2_t c" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_s8", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u8]_z", "arguments": [ - "uint8x16_t a", - "int8x16_t b", - "int8x16_t c" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "int8x16_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.B[*]" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_u16", + "SIMD_ISA": "SVE", + "name": "svadd[_s16]_m", "arguments": [ - "uint16x8_t a", - "uint16x8_t b", - "uint16x8_t c" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.H" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_u32", + "SIMD_ISA": "SVE", + "name": "svadd[_s16]_x", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t c" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.H|Ztied2.H" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_u64", + "SIMD_ISA": "SVE", + "name": "svadd[_s16]_z", "arguments": [ - "uint64x2_t a", - "uint64x2_t b", - "uint64x2_t c" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.H" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_u8", + "SIMD_ISA": "SVE", + "name": "svadd[_s32]_m", "arguments": [ - "uint8x16_t a", - "uint8x16_t b", - "uint8x16_t c" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.S" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcadd_rot270_f16", + "SIMD_ISA": "SVE", + "name": "svadd[_s32]_x", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "float16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H " + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCADD" + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcadd_rot270_f32", + "SIMD_ISA": "SVE", + "name": "svadd[_s32]_z", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S " + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCADD" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcadd_rot90_f16", + "SIMD_ISA": "SVE", + "name": "svadd[_s64]_m", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "float16x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H " + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCADD" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcadd_rot90_f32", + "SIMD_ISA": "SVE", + "name": "svadd[_s64]_x", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S " + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCADD" + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaddq_rot270_f16", + "SIMD_ISA": "SVE", + "name": "svadd[_s64]_z", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H " + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCADD" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaddq_rot270_f32", + "SIMD_ISA": "SVE", + "name": "svadd[_s8]_m", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S " + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCADD" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaddq_rot270_f64", + "SIMD_ISA": "SVE", + "name": "svadd[_s8]_x", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D " + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -7432,82 +8981,107 @@ ], "instructions": [ [ - "FCADD" + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaddq_rot90_f16", + "SIMD_ISA": "SVE", + "name": "svadd[_s8]_z", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H " + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCADD" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaddq_rot90_f32", + "SIMD_ISA": "SVE", + "name": "svadd[_u16]_m", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S " + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCADD" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaddq_rot90_f64", + "SIMD_ISA": "SVE", + "name": "svadd[_u16]_x", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D " + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -7515,83 +9089,107 @@ ], "instructions": [ [ - "FCADD" + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcage_f16", + "SIMD_ISA": "SVE", + "name": "svadd[_u16]_z", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FACGE" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcage_f32", + "SIMD_ISA": "SVE", + "name": "svadd[_u32]_m", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FACGE" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcage_f64", + "SIMD_ISA": "SVE", + "name": "svadd[_u32]_x", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -7599,26 +9197,36 @@ ], "instructions": [ [ - "FACGE" + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaged_f64", + "SIMD_ISA": "SVE", + "name": "svadd[_u32]_z", "arguments": [ - "float64_t a", - "float64_t b" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -7626,26 +9234,35 @@ ], "instructions": [ [ - "FACGE" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcageh_f16", + "SIMD_ISA": "SVE", + "name": "svadd[_u64]_m", "arguments": [ - "float16_t a", - "float16_t b" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Hm" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -7653,83 +9270,107 @@ ], "instructions": [ [ - "FACGE" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcageq_f16", + "SIMD_ISA": "SVE", + "name": "svadd[_u64]_x", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FACGE" + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcageq_f32", + "SIMD_ISA": "SVE", + "name": "svadd[_u64]_z", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FACGE" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcageq_f64", + "SIMD_ISA": "SVE", + "name": "svadd[_u8]_m", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -7737,26 +9378,34 @@ ], "instructions": [ [ - "FACGE" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcages_f32", + "SIMD_ISA": "SVE", + "name": "svadd[_u8]_x", "arguments": [ - "float32_t a", - "float32_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Sm" + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -7764,83 +9413,103 @@ ], "instructions": [ [ - "FACGE" + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcagt_f16", + "SIMD_ISA": "SVE", + "name": "svadd[_u8]_z", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FACGT" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcagt_f32", + "SIMD_ISA": "SVE", + "name": "svadda[_f16]", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svbool_t pg", + "float16_t initial", + "svfloat16_t op" ], "return_type": { - "value": "uint32x2_t" + "value": "float16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "initial": { + "register": "Htied" }, - "b": { - "register": "Vm.2S" + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FACGT" + "FADDA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcagt_f64", + "SIMD_ISA": "SVE", + "name": "svadda[_f32]", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svbool_t pg", + "float32_t initial", + "svfloat32_t op" ], "return_type": { - "value": "uint64x1_t" + "value": "float32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "initial": { + "register": "Stied" }, - "b": { - "register": "Dm" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -7848,26 +9517,30 @@ ], "instructions": [ [ - "FACGT" + "FADDA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcagtd_f64", + "SIMD_ISA": "SVE", + "name": "svadda[_f64]", "arguments": [ - "float64_t a", - "float64_t b" + "svbool_t pg", + "float64_t initial", + "svfloat64_t op" ], "return_type": { - "value": "uint64_t" + "value": "float64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "initial": { + "register": "Dtied" }, - "b": { - "register": "Dm" + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -7875,26 +9548,26 @@ ], "instructions": [ [ - "FACGT" + "FADDA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcagth_f16", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_n_s16]", "arguments": [ - "float16_t a", - "float16_t b" + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Hm" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -7902,83 +9575,80 @@ ], "instructions": [ [ - "FACGT" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcagtq_f16", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_n_s32]", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FACGT" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcagtq_f32", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_n_s64]", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.D[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FACGT" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcagtq_f64", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_n_u16]", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -7986,26 +9656,26 @@ ], "instructions": [ [ - "FACGT" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcagts_f32", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_n_u32]", "arguments": [ - "float32_t a", - "float32_t b" + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Sm" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ @@ -8013,83 +9683,80 @@ ], "instructions": [ [ - "FACGT" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcale_f16", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_n_u64]", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.D[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FACGE" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcale_f32", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_s16]", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FACGE" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcale_f64", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_s32]", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ @@ -8097,26 +9764,26 @@ ], "instructions": [ [ - "FACGE" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaled_f64", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_s64]", "arguments": [ - "float64_t a", - "float64_t b" + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.D" } }, "Architectures": [ @@ -8124,26 +9791,26 @@ ], "instructions": [ [ - "FACGE" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaleh_f16", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_u16]", "arguments": [ - "float16_t a", - "float16_t b" + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Hm" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -8151,83 +9818,84 @@ ], "instructions": [ [ - "FACGE" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaleq_f16", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_u32]", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FACGE" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaleq_f32", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_u64]", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FACGE" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaleq_f64", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_n_s16]", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svint8_t even", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "even": { + "register": "Ztied.B" }, - "b": { - "register": "Vm.2D" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -8235,26 +9903,30 @@ ], "instructions": [ [ - "FACGE" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcales_f32", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_n_s32]", "arguments": [ - "float32_t a", - "float32_t b" + "svint16_t even", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "even": { + "register": "Ztied.H" }, - "b": { - "register": "Sm" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ @@ -8262,83 +9934,92 @@ ], "instructions": [ [ - "FACGE" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcalt_f16", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_n_s64]", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svint32_t even", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "even": { + "register": "Ztied.S" }, - "b": { - "register": "Vm.4H" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FACGT" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcalt_f32", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_n_u16]", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svuint8_t even", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "even": { + "register": "Ztied.B" }, - "b": { - "register": "Vm.2S" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FACGT" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcalt_f64", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_n_u32]", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svuint16_t even", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "even": { + "register": "Ztied.H" }, - "b": { - "register": "Dm" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ @@ -8346,26 +10027,30 @@ ], "instructions": [ [ - "FACGT" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaltd_f64", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_n_u64]", "arguments": [ - "float64_t a", - "float64_t b" + "svuint32_t even", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "even": { + "register": "Ztied.S" }, - "b": { - "register": "Dm" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" } }, "Architectures": [ @@ -8373,26 +10058,30 @@ ], "instructions": [ [ - "FACGT" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcalth_f16", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_s16]", "arguments": [ - "float16_t a", - "float16_t b" + "svint8_t even", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "even": { + "register": "Ztied.B" }, - "b": { - "register": "Hm" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -8400,83 +10089,92 @@ ], "instructions": [ [ - "FACGT" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaltq_f16", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_s32]", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svint16_t even", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "even": { + "register": "Ztied.H" }, - "b": { - "register": "Vm.8H" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FACGT" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaltq_f32", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_s64]", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svint32_t even", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "even": { + "register": "Ztied.S" }, - "b": { - "register": "Vm.4S" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FACGT" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaltq_f64", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_u16]", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svuint8_t even", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "even": { + "register": "Ztied.B" }, - "b": { - "register": "Vm.2D" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -8484,26 +10182,30 @@ ], "instructions": [ [ - "FACGT" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcalts_f32", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_u32]", "arguments": [ - "float32_t a", - "float32_t b" + "svuint16_t even", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "even": { + "register": "Ztied.H" }, - "b": { - "register": "Sm" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" } }, "Architectures": [ @@ -8511,83 +10213,84 @@ ], "instructions": [ [ - "FACGT" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_f16", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_u64]", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svuint32_t even", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "even": { + "register": "Ztied.S" }, - "b": { - "register": "Vm.4H" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMEQ" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_f32", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_n_s16]", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCMEQ" + "SADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_f64", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_n_s32]", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -8595,141 +10298,134 @@ ], "instructions": [ [ - "FCMEQ" + "SADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_p64", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_n_s64]", "arguments": [ - "poly64x1_t a", - "poly64x1_t b" + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "SADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_p8", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_n_u16]", "arguments": [ - "poly8x8_t a", - "poly8x8_t b" + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "UADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_s16", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_n_u32]", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "UADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_s32", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_n_u64]", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "UADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_s64", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_s16]", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -8737,113 +10433,107 @@ ], "instructions": [ [ - "CMEQ" + "SADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_s8", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_s32]", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "SADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_u16", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_s64]", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "SADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_u32", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_u16]", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "UADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_u64", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_u32]", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -8851,55 +10541,53 @@ ], "instructions": [ [ - "CMEQ" + "UADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_u8", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_u64]", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "UADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqd_f64", + "SIMD_ISA": "SVE2", + "name": "svaddlbt[_n_s16]", "arguments": [ - "float64_t a", - "float64_t b" + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ @@ -8907,26 +10595,26 @@ ], "instructions": [ [ - "FCMEQ" + "SADDLBT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqd_s64", + "SIMD_ISA": "SVE2", + "name": "svaddlbt[_n_s32]", "arguments": [ - "int64_t a", - "int64_t b" + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -8934,26 +10622,26 @@ ], "instructions": [ [ - "CMEQ" + "SADDLBT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqd_u64", + "SIMD_ISA": "SVE2", + "name": "svaddlbt[_n_s64]", "arguments": [ - "uint64_t a", - "uint64_t b" + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ @@ -8961,26 +10649,26 @@ ], "instructions": [ [ - "CMEQ" + "SADDLBT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqh_f16", + "SIMD_ISA": "SVE2", + "name": "svaddlbt[_s16]", "arguments": [ - "float16_t a", - "float16_t b" + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Hm" + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -8988,83 +10676,80 @@ ], "instructions": [ [ - "FCMEQ" + "SADDLBT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_f16", + "SIMD_ISA": "SVE2", + "name": "svaddlbt[_s32]", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMEQ" + "SADDLBT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_f32", + "SIMD_ISA": "SVE2", + "name": "svaddlbt[_s64]", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCMEQ" + "SADDLBT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_f64", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_n_s16]", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ @@ -9072,141 +10757,134 @@ ], "instructions": [ [ - "FCMEQ" + "SADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_p64", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_n_s32]", "arguments": [ - "poly64x2_t a", - "poly64x2_t b" + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "SADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_p8", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_n_s64]", "arguments": [ - "poly8x16_t a", - "poly8x16_t b" + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "SADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_s16", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_n_u16]", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "UADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_s32", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_n_u32]", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "UADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_s64", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_n_u64]", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ @@ -9214,113 +10892,107 @@ ], "instructions": [ [ - "CMEQ" + "UADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_s8", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_s16]", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "SADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_u16", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_s32]", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "SADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_u32", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_s64]", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "SADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_u64", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_u16]", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -9328,55 +11000,53 @@ ], "instructions": [ [ - "CMEQ" + "UADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_u8", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_u32]", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "UADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqs_f32", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_u64]", "arguments": [ - "float32_t a", - "float32_t b" + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Sm" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ @@ -9384,46 +11054,65 @@ ], "instructions": [ [ - "FCMEQ" + "UADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_f16", + "SIMD_ISA": "SVE2", + "name": "svaddp[_f16]_m", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMEQ" + "FADDP" + ], + [ + "MOVPRFX", + "FADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_f32", + "SIMD_ISA": "SVE2", + "name": "svaddp[_f16]_x", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -9431,22 +11120,34 @@ ], "instructions": [ [ - "FCMEQ" + "FADDP" + ], + [ + "MOVPRFX", + "FADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_f64", + "SIMD_ISA": "SVE2", + "name": "svaddp[_f32]_m", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -9454,46 +11155,69 @@ ], "instructions": [ [ - "FCMEQ" + "FADDP" + ], + [ + "MOVPRFX", + "FADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_p64", + "SIMD_ISA": "SVE2", + "name": "svaddp[_f32]_x", "arguments": [ - "poly64x1_t a" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "FADDP" + ], + [ + "MOVPRFX", + "FADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_p8", + "SIMD_ISA": "SVE2", + "name": "svaddp[_f64]_m", "arguments": [ - "poly8x8_t a" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -9501,22 +11225,34 @@ ], "instructions": [ [ - "CMEQ" + "FADDP" + ], + [ + "MOVPRFX", + "FADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_s16", + "SIMD_ISA": "SVE2", + "name": "svaddp[_f64]_x", "arguments": [ - "int16x4_t a" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -9524,22 +11260,34 @@ ], "instructions": [ [ - "CMEQ" + "FADDP" + ], + [ + "MOVPRFX", + "FADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_s32", + "SIMD_ISA": "SVE2", + "name": "svaddp[_s16]_m", "arguments": [ - "int32x2_t a" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -9547,22 +11295,34 @@ ], "instructions": [ [ - "CMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_s64", + "SIMD_ISA": "SVE2", + "name": "svaddp[_s16]_x", "arguments": [ - "int64x1_t a" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -9570,22 +11330,34 @@ ], "instructions": [ [ - "CMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_s8", + "SIMD_ISA": "SVE2", + "name": "svaddp[_s32]_m", "arguments": [ - "int8x8_t a" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -9593,22 +11365,34 @@ ], "instructions": [ [ - "CMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_u16", + "SIMD_ISA": "SVE2", + "name": "svaddp[_s32]_x", "arguments": [ - "uint16x4_t a" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -9616,22 +11400,34 @@ ], "instructions": [ [ - "CMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_u32", + "SIMD_ISA": "SVE2", + "name": "svaddp[_s64]_m", "arguments": [ - "uint32x2_t a" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -9639,22 +11435,34 @@ ], "instructions": [ [ - "CMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_u64", + "SIMD_ISA": "SVE2", + "name": "svaddp[_s64]_x", "arguments": [ - "uint64x1_t a" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -9662,22 +11470,34 @@ ], "instructions": [ [ - "CMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_u8", + "SIMD_ISA": "SVE2", + "name": "svaddp[_s8]_m", "arguments": [ - "uint8x8_t a" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -9685,22 +11505,34 @@ ], "instructions": [ [ - "CMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzd_f64", + "SIMD_ISA": "SVE2", + "name": "svaddp[_s8]_x", "arguments": [ - "float64_t a" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -9708,22 +11540,34 @@ ], "instructions": [ [ - "FCMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzd_s64", + "SIMD_ISA": "SVE2", + "name": "svaddp[_u16]_m", "arguments": [ - "int64_t a" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -9731,22 +11575,34 @@ ], "instructions": [ [ - "CMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzd_u64", + "SIMD_ISA": "SVE2", + "name": "svaddp[_u16]_x", "arguments": [ - "uint64_t a" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -9754,22 +11610,34 @@ ], "instructions": [ [ - "CMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzh_f16", + "SIMD_ISA": "SVE2", + "name": "svaddp[_u32]_m", "arguments": [ - "float16_t a" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -9777,46 +11645,69 @@ ], "instructions": [ [ - "FCMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_f16", + "SIMD_ISA": "SVE2", + "name": "svaddp[_u32]_x", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_f32", + "SIMD_ISA": "SVE2", + "name": "svaddp[_u64]_m", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -9824,22 +11715,34 @@ ], "instructions": [ [ - "FCMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_f64", + "SIMD_ISA": "SVE2", + "name": "svaddp[_u64]_x", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -9847,46 +11750,69 @@ ], "instructions": [ [ - "FCMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_p64", + "SIMD_ISA": "SVE2", + "name": "svaddp[_u8]_m", "arguments": [ - "poly64x2_t a" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_p8", + "SIMD_ISA": "SVE2", + "name": "svaddp[_u8]_x", "arguments": [ - "poly8x16_t a" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -9894,22 +11820,30 @@ ], "instructions": [ [ - "CMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_s16", + "SIMD_ISA": "SVE", + "name": "svaddv[_f16]", "arguments": [ - "int16x8_t a" + "svbool_t pg", + "svfloat16_t op" ], "return_type": { - "value": "uint16x8_t" + "value": "float16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -9917,22 +11851,26 @@ ], "instructions": [ [ - "CMEQ" + "FADDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_s32", + "SIMD_ISA": "SVE", + "name": "svaddv[_f32]", "arguments": [ - "int32x4_t a" + "svbool_t pg", + "svfloat32_t op" ], "return_type": { - "value": "uint32x4_t" + "value": "float32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -9940,22 +11878,26 @@ ], "instructions": [ [ - "CMEQ" + "FADDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_s64", + "SIMD_ISA": "SVE", + "name": "svaddv[_f64]", "arguments": [ - "int64x2_t a" + "svbool_t pg", + "svfloat64_t op" ], "return_type": { - "value": "uint64x2_t" + "value": "float64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -9963,22 +11905,26 @@ ], "instructions": [ [ - "CMEQ" + "FADDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_s8", + "SIMD_ISA": "SVE", + "name": "svaddv[_s16]", "arguments": [ - "int8x16_t a" + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "uint8x16_t" + "value": "int64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -9986,22 +11932,26 @@ ], "instructions": [ [ - "CMEQ" + "SADDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_u16", + "SIMD_ISA": "SVE", + "name": "svaddv[_s32]", "arguments": [ - "uint16x8_t a" + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "uint16x8_t" + "value": "int64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -10009,22 +11959,26 @@ ], "instructions": [ [ - "CMEQ" + "SADDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_u32", + "SIMD_ISA": "SVE", + "name": "svaddv[_s64]", "arguments": [ - "uint32x4_t a" + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "uint32x4_t" + "value": "int64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -10032,22 +11986,26 @@ ], "instructions": [ [ - "CMEQ" + "UADDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_u64", + "SIMD_ISA": "SVE", + "name": "svaddv[_s8]", "arguments": [ - "uint64x2_t a" + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "uint64x2_t" + "value": "int64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -10055,22 +12013,26 @@ ], "instructions": [ [ - "CMEQ" + "SADDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_u8", + "SIMD_ISA": "SVE", + "name": "svaddv[_u16]", "arguments": [ - "uint8x16_t a" + "svbool_t pg", + "svuint16_t op" ], "return_type": { - "value": "uint8x16_t" + "value": "uint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -10078,22 +12040,26 @@ ], "instructions": [ [ - "CMEQ" + "UADDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzs_f32", + "SIMD_ISA": "SVE", + "name": "svaddv[_u32]", "arguments": [ - "float32_t a" + "svbool_t pg", + "svuint32_t op" ], "return_type": { - "value": "uint32_t" + "value": "uint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -10101,83 +12067,80 @@ ], "instructions": [ [ - "FCMEQ" + "UADDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcge_f16", + "SIMD_ISA": "SVE", + "name": "svaddv[_u64]", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svbool_t pg", + "svuint64_t op" ], "return_type": { - "value": "uint16x4_t" + "value": "uint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op": { + "register": "Zop.D" }, - "b": { - "register": "Vm.4H" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGE" + "UADDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcge_f32", + "SIMD_ISA": "SVE", + "name": "svaddv[_u8]", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svbool_t pg", + "svuint8_t op" ], "return_type": { - "value": "uint32x2_t" + "value": "uint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op": { + "register": "Zop.B" }, - "b": { - "register": "Vm.2S" + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCMGE" + "UADDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcge_f64", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_n_s16]", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svint16_t op1", + "int8_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ @@ -10185,84 +12148,80 @@ ], "instructions": [ [ - "FCMGE" + "SADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcge_s16", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_n_s32]", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "svint32_t op1", + "int16_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "SADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcge_s32", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_n_s64]", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "svint64_t op1", + "int32_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "SADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcge_s64", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_n_u16]", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "svuint16_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ @@ -10270,113 +12229,107 @@ ], "instructions": [ [ - "CMGE" + "UADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcge_s8", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_n_u32]", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "svuint32_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "UADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcge_u16", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_n_u64]", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "svuint64_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "UADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcge_u32", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_s16]", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "svint16_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "SADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcge_u64", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_s32]", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "svint32_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -10384,55 +12337,53 @@ ], "instructions": [ [ - "CMHS" + "SADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcge_u8", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_s64]", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "svint64_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "SADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcged_f64", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_u16]", "arguments": [ - "float64_t a", - "float64_t b" + "svuint16_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -10440,26 +12391,26 @@ ], "instructions": [ [ - "FCMGE" + "UADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcged_s64", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_u32]", "arguments": [ - "int64_t a", - "int64_t b" + "svuint32_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -10467,26 +12418,26 @@ ], "instructions": [ [ - "CMGE" + "UADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcged_u64", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_u64]", "arguments": [ - "uint64_t a", - "uint64_t b" + "svuint64_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ @@ -10494,26 +12445,26 @@ ], "instructions": [ [ - "CMHS" + "UADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeh_f16", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_n_s16]", "arguments": [ - "float16_t a", - "float16_t b" + "svint16_t op1", + "int8_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Hm" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ @@ -10521,83 +12472,80 @@ ], "instructions": [ [ - "FCMGE" + "SADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeq_f16", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_n_s32]", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svint32_t op1", + "int16_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGE" + "SADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeq_f32", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_n_s64]", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svint64_t op1", + "int32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCMGE" + "SADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeq_f64", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_n_u16]", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svuint16_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ @@ -10605,84 +12553,80 @@ ], "instructions": [ [ - "FCMGE" + "UADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeq_s16", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_n_u32]", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "svuint32_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "UADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeq_s32", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_n_u64]", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "svuint64_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "UADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeq_s64", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_s16]", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "svint16_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -10690,113 +12634,107 @@ ], "instructions": [ [ - "CMGE" + "SADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeq_s8", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_s32]", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "svint32_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "SADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeq_u16", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_s64]", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "svint64_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "SADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeq_u32", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_u16]", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "svuint16_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "UADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeq_u64", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_u32]", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "svuint32_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -10804,55 +12742,53 @@ ], "instructions": [ [ - "CMHS" + "UADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeq_u8", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_u64]", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "svuint64_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "UADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcges_f32", + "SIMD_ISA": "SVE", + "name": "svadrb[_u32base]_[s32]offset", "arguments": [ - "float32_t a", - "float32_t b" + "svuint32_t bases", + "svint32_t offsets" ], "return_type": { - "value": "uint32_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "bases": { + "register": "Zbases.S" }, - "b": { - "register": "Sm" + "offsets": { + "register": "Zoffsets.S" } }, "Architectures": [ @@ -10860,46 +12796,53 @@ ], "instructions": [ [ - "FCMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgez_f16", + "SIMD_ISA": "SVE", + "name": "svadrb[_u32base]_[u32]offset", "arguments": [ - "float16x4_t a" + "svuint32_t bases", + "svuint32_t offsets" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "bases": { + "register": "Zbases.S" + }, + "offsets": { + "register": "Zoffsets.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgez_f32", + "SIMD_ISA": "SVE", + "name": "svadrb[_u64base]_[s64]offset", "arguments": [ - "float32x2_t a" + "svuint64_t bases", + "svint64_t offsets" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "bases": { + "register": "Zbases.D" + }, + "offsets": { + "register": "Zoffsets.D" } }, "Architectures": [ @@ -10907,22 +12850,26 @@ ], "instructions": [ [ - "FCMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgez_f64", + "SIMD_ISA": "SVE", + "name": "svadrb[_u64base]_[u64]offset", "arguments": [ - "float64x1_t a" + "svuint64_t bases", + "svuint64_t offsets" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "bases": { + "register": "Zbases.D" + }, + "offsets": { + "register": "Zoffsets.D" } }, "Architectures": [ @@ -10930,22 +12877,26 @@ ], "instructions": [ [ - "FCMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgez_s16", + "SIMD_ISA": "SVE", + "name": "svadrd[_u32base]_[s32]index", "arguments": [ - "int16x4_t a" + "svuint32_t bases", + "svint32_t indices" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "bases": { + "register": "Zbases.S" + }, + "indices": { + "register": "Zindices.S" } }, "Architectures": [ @@ -10953,22 +12904,26 @@ ], "instructions": [ [ - "CMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgez_s32", + "SIMD_ISA": "SVE", + "name": "svadrd[_u32base]_[u32]index", "arguments": [ - "int32x2_t a" + "svuint32_t bases", + "svuint32_t indices" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "bases": { + "register": "Zbases.S" + }, + "indices": { + "register": "Zindices.S" } }, "Architectures": [ @@ -10976,22 +12931,26 @@ ], "instructions": [ [ - "CMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgez_s64", + "SIMD_ISA": "SVE", + "name": "svadrd[_u64base]_[s64]index", "arguments": [ - "int64x1_t a" + "svuint64_t bases", + "svint64_t indices" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "bases": { + "register": "Zbases.D" + }, + "indices": { + "register": "Zindices.D" } }, "Architectures": [ @@ -10999,22 +12958,26 @@ ], "instructions": [ [ - "CMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgez_s8", + "SIMD_ISA": "SVE", + "name": "svadrd[_u64base]_[u64]index", "arguments": [ - "int8x8_t a" + "svuint64_t bases", + "svuint64_t indices" ], "return_type": { - "value": "uint8x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "bases": { + "register": "Zbases.D" + }, + "indices": { + "register": "Zindices.D" } }, "Architectures": [ @@ -11022,22 +12985,26 @@ ], "instructions": [ [ - "CMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgezd_f64", + "SIMD_ISA": "SVE", + "name": "svadrh[_u32base]_[s32]index", "arguments": [ - "float64_t a" + "svuint32_t bases", + "svint32_t indices" ], "return_type": { - "value": "uint64_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "bases": { + "register": "Zbases.S" + }, + "indices": { + "register": "Zindices.S" } }, "Architectures": [ @@ -11045,22 +13012,26 @@ ], "instructions": [ [ - "FCMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgezd_s64", + "SIMD_ISA": "SVE", + "name": "svadrh[_u32base]_[u32]index", "arguments": [ - "int64_t a" + "svuint32_t bases", + "svuint32_t indices" ], "return_type": { - "value": "uint64_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "bases": { + "register": "Zbases.S" + }, + "indices": { + "register": "Zindices.S" } }, "Architectures": [ @@ -11068,22 +13039,26 @@ ], "instructions": [ [ - "CMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgezh_f16", + "SIMD_ISA": "SVE", + "name": "svadrh[_u64base]_[s64]index", "arguments": [ - "float16_t a" + "svuint64_t bases", + "svint64_t indices" ], "return_type": { - "value": "uint16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "bases": { + "register": "Zbases.D" + }, + "indices": { + "register": "Zindices.D" } }, "Architectures": [ @@ -11091,46 +13066,53 @@ ], "instructions": [ [ - "FCMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgezq_f16", + "SIMD_ISA": "SVE", + "name": "svadrh[_u64base]_[u64]index", "arguments": [ - "float16x8_t a" + "svuint64_t bases", + "svuint64_t indices" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "bases": { + "register": "Zbases.D" + }, + "indices": { + "register": "Zindices.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgezq_f32", + "SIMD_ISA": "SVE", + "name": "svadrw[_u32base]_[s32]index", "arguments": [ - "float32x4_t a" + "svuint32_t bases", + "svint32_t indices" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "bases": { + "register": "Zbases.S" + }, + "indices": { + "register": "Zindices.S" } }, "Architectures": [ @@ -11138,22 +13120,26 @@ ], "instructions": [ [ - "FCMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgezq_f64", + "SIMD_ISA": "SVE", + "name": "svadrw[_u32base]_[u32]index", "arguments": [ - "float64x2_t a" + "svuint32_t bases", + "svuint32_t indices" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "bases": { + "register": "Zbases.S" + }, + "indices": { + "register": "Zindices.S" } }, "Architectures": [ @@ -11161,22 +13147,26 @@ ], "instructions": [ [ - "FCMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgezq_s16", + "SIMD_ISA": "SVE", + "name": "svadrw[_u64base]_[s64]index", "arguments": [ - "int16x8_t a" + "svuint64_t bases", + "svint64_t indices" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "bases": { + "register": "Zbases.D" + }, + "indices": { + "register": "Zindices.D" } }, "Architectures": [ @@ -11184,22 +13174,26 @@ ], "instructions": [ [ - "CMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgezq_s32", + "SIMD_ISA": "SVE", + "name": "svadrw[_u64base]_[u64]index", "arguments": [ - "int32x4_t a" + "svuint64_t bases", + "svuint64_t indices" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "bases": { + "register": "Zbases.D" + }, + "indices": { + "register": "Zindices.D" } }, "Architectures": [ @@ -11207,22 +13201,26 @@ ], "instructions": [ [ - "CMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgezq_s64", + "SIMD_ISA": "SVE2", + "name": "svaesd[_u8]", "arguments": [ - "int64x2_t a" + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" } }, "Architectures": [ @@ -11230,22 +13228,29 @@ ], "instructions": [ [ - "CMGE" + "AESD" + ], + [ + "AESD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgezq_s8", + "SIMD_ISA": "SVE2", + "name": "svaese[_u8]", "arguments": [ - "int8x16_t a" + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" } }, "Architectures": [ @@ -11253,22 +13258,25 @@ ], "instructions": [ [ - "CMGE" + "AESE" + ], + [ + "AESE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgezs_f32", + "SIMD_ISA": "SVE2", + "name": "svaesimc[_u8]", "arguments": [ - "float32_t a" + "svuint8_t op" ], "return_type": { - "value": "uint32_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op": { + "register": "Ztied.B" } }, "Architectures": [ @@ -11276,83 +13284,84 @@ ], "instructions": [ [ - "FCMGE" + "AESIMC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgt_f16", + "SIMD_ISA": "SVE2", + "name": "svaesmc[_u8]", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svuint8_t op" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "op": { + "register": "Ztied.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGT" + "AESMC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgt_f32", + "SIMD_ISA": "SVE", + "name": "svand[_b]_z", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svbool_t pg", + "svbool_t op1", + "svbool_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Pop1.B" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Pop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCMGT" + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgt_f64", + "SIMD_ISA": "SVE", + "name": "svand[_n_s16]_m", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Ztied1.H" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -11360,84 +13369,113 @@ ], "instructions": [ [ - "FCMGT" + "UXTB" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgt_s16", + "SIMD_ISA": "SVE", + "name": "svand[_n_s16]_x", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgt_s32", + "SIMD_ISA": "SVE", + "name": "svand[_n_s16]_z", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "MOVPRFX", + "UXTB" + ], + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgt_s64", + "SIMD_ISA": "SVE", + "name": "svand[_n_s32]_m", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Ztied1.S" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -11445,113 +13483,160 @@ ], "instructions": [ [ - "CMGT" + "UXTB" + ], + [ + "UXTH" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgt_s8", + "SIMD_ISA": "SVE", + "name": "svand[_n_s32]_x", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgt_u16", + "SIMD_ISA": "SVE", + "name": "svand[_n_s32]_z", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "MOVPRFX", + "UXTB" + ], + [ + "MOVPRFX", + "UXTH" + ], + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgt_u32", + "SIMD_ISA": "SVE", + "name": "svand[_n_s64]_m", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Ztied1.D" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "UXTB" + ], + [ + "UXTH" + ], + [ + "UXTW" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgt_u64", + "SIMD_ISA": "SVE", + "name": "svand[_n_s64]_x", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -11559,55 +13644,87 @@ ], "instructions": [ [ - "CMHI" + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgt_u8", + "SIMD_ISA": "SVE", + "name": "svand[_n_s64]_z", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "MOVPRFX", + "UXTB" + ], + [ + "MOVPRFX", + "UXTH" + ], + [ + "MOVPRFX", + "UXTW" + ], + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtd_f64", + "SIMD_ISA": "SVE", + "name": "svand[_n_s8]_m", "arguments": [ - "float64_t a", - "float64_t b" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -11615,26 +13732,34 @@ ], "instructions": [ [ - "FCMGT" + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtd_s64", + "SIMD_ISA": "SVE", + "name": "svand[_n_s8]_x", "arguments": [ - "int64_t a", - "int64_t b" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -11642,26 +13767,39 @@ ], "instructions": [ [ - "CMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtd_u64", + "SIMD_ISA": "SVE", + "name": "svand[_n_s8]_z", "arguments": [ - "uint64_t a", - "uint64_t b" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -11669,26 +13807,35 @@ ], "instructions": [ [ - "CMHI" + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgth_f16", + "SIMD_ISA": "SVE", + "name": "svand[_n_u16]_m", "arguments": [ - "float16_t a", - "float16_t b" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Ztied1.H" }, - "b": { - "register": "Hm" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -11696,83 +13843,113 @@ ], "instructions": [ [ - "FCMGT" + "UXTB" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtq_f16", + "SIMD_ISA": "SVE", + "name": "svand[_n_u16]_x", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtq_f32", + "SIMD_ISA": "SVE", + "name": "svand[_n_u16]_z", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCMGT" + "MOVPRFX", + "UXTB" + ], + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtq_f64", + "SIMD_ISA": "SVE", + "name": "svand[_n_u32]_m", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Ztied1.S" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -11780,84 +13957,120 @@ ], "instructions": [ [ - "FCMGT" + "UXTB" + ], + [ + "UXTH" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtq_s16", + "SIMD_ISA": "SVE", + "name": "svand[_n_u32]_x", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtq_s32", + "SIMD_ISA": "SVE", + "name": "svand[_n_u32]_z", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "MOVPRFX", + "UXTB" + ], + [ + "MOVPRFX", + "UXTH" + ], + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtq_s64", + "SIMD_ISA": "SVE", + "name": "svand[_n_u64]_m", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Ztied1.D" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -11865,113 +14078,162 @@ ], "instructions": [ [ - "CMGT" + "UXTB" + ], + [ + "UXTH" + ], + [ + "UXTW" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtq_s8", + "SIMD_ISA": "SVE", + "name": "svand[_n_u64]_x", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtq_u16", + "SIMD_ISA": "SVE", + "name": "svand[_n_u64]_z", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "MOVPRFX", + "UXTB" + ], + [ + "MOVPRFX", + "UXTH" + ], + [ + "MOVPRFX", + "UXTW" + ], + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtq_u32", + "SIMD_ISA": "SVE", + "name": "svand[_n_u8]_m", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtq_u64", + "SIMD_ISA": "SVE", + "name": "svand[_n_u8]_x", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -11979,55 +14241,75 @@ ], "instructions": [ [ - "CMHI" + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtq_u8", + "SIMD_ISA": "SVE", + "name": "svand[_n_u8]_z", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgts_f32", + "SIMD_ISA": "SVE", + "name": "svand[_s16]_m", "arguments": [ - "float32_t a", - "float32_t b" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Sm" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -12035,46 +14317,71 @@ ], "instructions": [ [ - "FCMGT" + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtz_f16", + "SIMD_ISA": "SVE", + "name": "svand[_s16]_x", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtz_f32", + "SIMD_ISA": "SVE", + "name": "svand[_s16]_z", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -12082,22 +14389,35 @@ ], "instructions": [ [ - "FCMGT" + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtz_f64", + "SIMD_ISA": "SVE", + "name": "svand[_s32]_m", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -12105,22 +14425,34 @@ ], "instructions": [ [ - "FCMGT" + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtz_s16", + "SIMD_ISA": "SVE", + "name": "svand[_s32]_x", "arguments": [ - "int16x4_t a" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -12128,22 +14460,36 @@ ], "instructions": [ [ - "CMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtz_s32", + "SIMD_ISA": "SVE", + "name": "svand[_s32]_z", "arguments": [ - "int32x2_t a" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -12151,22 +14497,35 @@ ], "instructions": [ [ - "CMGT" + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtz_s64", + "SIMD_ISA": "SVE", + "name": "svand[_s64]_m", "arguments": [ - "int64x1_t a" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -12174,22 +14533,34 @@ ], "instructions": [ [ - "CMGT" + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtz_s8", + "SIMD_ISA": "SVE", + "name": "svand[_s64]_x", "arguments": [ - "int8x8_t a" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -12197,22 +14568,36 @@ ], "instructions": [ [ - "CMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtzd_f64", + "SIMD_ISA": "SVE", + "name": "svand[_s64]_z", "arguments": [ - "float64_t a" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -12220,22 +14605,35 @@ ], "instructions": [ [ - "FCMGT" + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtzd_s64", + "SIMD_ISA": "SVE", + "name": "svand[_s8]_m", "arguments": [ - "int64_t a" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -12243,22 +14641,34 @@ ], "instructions": [ [ - "CMGT" + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtzh_f16", + "SIMD_ISA": "SVE", + "name": "svand[_s8]_x", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -12266,46 +14676,72 @@ ], "instructions": [ [ - "FCMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtzq_f16", + "SIMD_ISA": "SVE", + "name": "svand[_s8]_z", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGT" + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtzq_f32", + "SIMD_ISA": "SVE", + "name": "svand[_u16]_m", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -12313,22 +14749,34 @@ ], "instructions": [ [ - "FCMGT" + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtzq_f64", + "SIMD_ISA": "SVE", + "name": "svand[_u16]_x", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -12336,22 +14784,36 @@ ], "instructions": [ [ - "FCMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtzq_s16", + "SIMD_ISA": "SVE", + "name": "svand[_u16]_z", "arguments": [ - "int16x8_t a" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -12359,22 +14821,35 @@ ], "instructions": [ [ - "CMGT" + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtzq_s32", + "SIMD_ISA": "SVE", + "name": "svand[_u32]_m", "arguments": [ - "int32x4_t a" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -12382,22 +14857,34 @@ ], "instructions": [ [ - "CMGT" + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtzq_s64", + "SIMD_ISA": "SVE", + "name": "svand[_u32]_x", "arguments": [ - "int64x2_t a" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -12405,22 +14892,36 @@ ], "instructions": [ [ - "CMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtzq_s8", + "SIMD_ISA": "SVE", + "name": "svand[_u32]_z", "arguments": [ - "int8x16_t a" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -12428,22 +14929,35 @@ ], "instructions": [ [ - "CMGT" + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtzs_f32", + "SIMD_ISA": "SVE", + "name": "svand[_u64]_m", "arguments": [ - "float32_t a" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -12451,83 +14965,107 @@ ], "instructions": [ [ - "FCMGT" + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcle_f16", + "SIMD_ISA": "SVE", + "name": "svand[_u64]_x", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGE" + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcle_f32", + "SIMD_ISA": "SVE", + "name": "svand[_u64]_z", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCMGE" - ] - ] + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] }, { - "SIMD_ISA": "Neon", - "name": "vcle_f64", + "SIMD_ISA": "SVE", + "name": "svand[_u8]_m", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -12535,84 +15073,103 @@ ], "instructions": [ [ - "FCMGE" + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcle_s16", + "SIMD_ISA": "SVE", + "name": "svand[_u8]_x", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcle_s32", + "SIMD_ISA": "SVE", + "name": "svand[_u8]_z", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcle_s64", + "SIMD_ISA": "SVE", + "name": "svandv[_s16]", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "uint64x1_t" + "value": "int16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.H" }, - "b": { - "register": "Dm" + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -12620,113 +15177,107 @@ ], "instructions": [ [ - "CMGE" + "ANDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcle_s8", + "SIMD_ISA": "SVE", + "name": "svandv[_s32]", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "uint8x8_t" + "value": "int32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op": { + "register": "Zop.S" }, - "b": { - "register": "Vm.8B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "ANDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcle_u16", + "SIMD_ISA": "SVE", + "name": "svandv[_s64]", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "uint16x4_t" + "value": "int64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op": { + "register": "Zop.D" }, - "b": { - "register": "Vm.4H" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "ANDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcle_u32", + "SIMD_ISA": "SVE", + "name": "svandv[_s8]", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "uint32x2_t" + "value": "int8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op": { + "register": "Zop.B" }, - "b": { - "register": "Vm.2S" + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "ANDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcle_u64", + "SIMD_ISA": "SVE", + "name": "svandv[_u16]", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "svbool_t pg", + "svuint16_t op" ], "return_type": { - "value": "uint64x1_t" + "value": "uint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.H" }, - "b": { - "register": "Dm" + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -12734,55 +15285,53 @@ ], "instructions": [ [ - "CMHS" + "ANDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcle_u8", + "SIMD_ISA": "SVE", + "name": "svandv[_u32]", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "svbool_t pg", + "svuint32_t op" ], "return_type": { - "value": "uint8x8_t" + "value": "uint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op": { + "register": "Zop.S" }, - "b": { - "register": "Vm.8B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "ANDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcled_f64", + "SIMD_ISA": "SVE", + "name": "svandv[_u64]", "arguments": [ - "float64_t a", - "float64_t b" + "svbool_t pg", + "svuint64_t op" ], "return_type": { "value": "uint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.D" }, - "b": { - "register": "Dm" + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -12790,26 +15339,26 @@ ], "instructions": [ [ - "FCMGE" + "ANDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcled_s64", + "SIMD_ISA": "SVE", + "name": "svandv[_u8]", "arguments": [ - "int64_t a", - "int64_t b" + "svbool_t pg", + "svuint8_t op" ], "return_type": { - "value": "uint64_t" + "value": "uint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.B" }, - "b": { - "register": "Dm" + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -12817,26 +15366,30 @@ ], "instructions": [ [ - "CMGE" + "ANDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcled_u64", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s16]_m", "arguments": [ - "uint64_t a", - "uint64_t b" + "svbool_t pg", + "svint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Ztied1.H" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -12844,26 +15397,33 @@ ], "instructions": [ [ - "CMHS" + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleh_f16", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s16]_x", "arguments": [ - "float16_t a", - "float16_t b" + "svbool_t pg", + "svint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Hm" + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -12871,83 +15431,114 @@ ], "instructions": [ [ - "FCMGE" + "ASR" + ], + [ + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleq_f16", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s16]_z", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svbool_t pg", + "svint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGE" + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleq_f32", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s32]_m", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svbool_t pg", + "svint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Ztied1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCMGE" + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleq_f64", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s32]_x", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svbool_t pg", + "svint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -12955,84 +15546,114 @@ ], "instructions": [ [ - "FCMGE" + "ASR" + ], + [ + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleq_s16", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s32]_z", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "svbool_t pg", + "svint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleq_s32", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s64]_m", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "svbool_t pg", + "svint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Ztied1.D" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleq_s64", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s64]_x", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "svbool_t pg", + "svint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -13040,113 +15661,155 @@ ], "instructions": [ [ - "CMGE" + "ASR" + ], + [ + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleq_s8", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s64]_z", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "svbool_t pg", + "svint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleq_u16", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s8]_m", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "svbool_t pg", + "svint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Ztied1.B" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleq_u32", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s8]_x", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "svbool_t pg", + "svint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "ASR" + ], + [ + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleq_u64", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s8]_z", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "svbool_t pg", + "svint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -13154,55 +15817,74 @@ ], "instructions": [ [ - "CMHS" + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleq_u8", + "SIMD_ISA": "SVE", + "name": "svasr[_s16]_m", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "svbool_t pg", + "svint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "ASR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcles_f32", + "SIMD_ISA": "SVE", + "name": "svasr[_s16]_x", "arguments": [ - "float32_t a", - "float32_t b" + "svbool_t pg", + "svint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Sm" + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -13210,46 +15892,73 @@ ], "instructions": [ [ - "FCMGE" + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclez_f16", + "SIMD_ISA": "SVE", + "name": "svasr[_s16]_z", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "svint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLE" + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclez_f32", + "SIMD_ISA": "SVE", + "name": "svasr[_s32]_m", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -13257,22 +15966,34 @@ ], "instructions": [ [ - "CMLE" + "ASR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclez_f64", + "SIMD_ISA": "SVE", + "name": "svasr[_s32]_x", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -13280,22 +16001,37 @@ ], "instructions": [ [ - "FCMLE" + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclez_s16", + "SIMD_ISA": "SVE", + "name": "svasr[_s32]_z", "arguments": [ - "int16x4_t a" + "svbool_t pg", + "svint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -13303,22 +16039,35 @@ ], "instructions": [ [ - "CMLE" + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclez_s32", + "SIMD_ISA": "SVE", + "name": "svasr[_s64]_m", "arguments": [ - "int32x2_t a" + "svbool_t pg", + "svint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -13326,22 +16075,34 @@ ], "instructions": [ [ - "CMLE" + "ASR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclez_s64", + "SIMD_ISA": "SVE", + "name": "svasr[_s64]_x", "arguments": [ - "int64x1_t a" + "svbool_t pg", + "svint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -13349,22 +16110,37 @@ ], "instructions": [ [ - "CMLE" + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclez_s8", + "SIMD_ISA": "SVE", + "name": "svasr[_s64]_z", "arguments": [ - "int8x8_t a" + "svbool_t pg", + "svint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -13372,22 +16148,35 @@ ], "instructions": [ [ - "CMLE" + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclezd_f64", + "SIMD_ISA": "SVE", + "name": "svasr[_s8]_m", "arguments": [ - "float64_t a" + "svbool_t pg", + "svint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -13395,22 +16184,34 @@ ], "instructions": [ [ - "FCMLE" + "ASR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclezd_s64", + "SIMD_ISA": "SVE", + "name": "svasr[_s8]_x", "arguments": [ - "int64_t a" + "svbool_t pg", + "svint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -13418,22 +16219,37 @@ ], "instructions": [ [ - "CMLE" + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclezh_f16", + "SIMD_ISA": "SVE", + "name": "svasr[_s8]_z", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -13441,46 +16257,69 @@ ], "instructions": [ [ - "FCMLE" + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclezq_f16", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s16]_m", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svint16_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLE" + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclezq_f32", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s16]_x", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svint16_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -13488,22 +16327,36 @@ ], "instructions": [ [ - "FCMLE" + "ASR" + ], + [ + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclezq_f64", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s16]_z", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svint16_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -13511,22 +16364,35 @@ ], "instructions": [ [ - "FCMLE" + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclezq_s16", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s32]_m", "arguments": [ - "int16x8_t a" + "svbool_t pg", + "svint32_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -13534,22 +16400,33 @@ ], "instructions": [ [ - "CMLE" + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclezq_s32", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s32]_x", "arguments": [ - "int32x4_t a" + "svbool_t pg", + "svint32_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -13557,22 +16434,36 @@ ], "instructions": [ [ - "CMLE" + "ASR" + ], + [ + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclezq_s64", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s32]_z", "arguments": [ - "int64x2_t a" + "svbool_t pg", + "svint32_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -13580,22 +16471,35 @@ ], "instructions": [ [ - "CMLE" + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclezq_s8", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s8]_m", "arguments": [ - "int8x16_t a" + "svbool_t pg", + "svint8_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -13603,22 +16507,33 @@ ], "instructions": [ [ - "CMLE" + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclezs_f32", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s8]_x", "arguments": [ - "float32_t a" + "svbool_t pg", + "svint8_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -13626,383 +16541,517 @@ ], "instructions": [ [ - "FCMLE" + "ASR" + ], + [ + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcls_s16", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s8]_z", "arguments": [ - "int16x4_t a" + "svbool_t pg", + "svint8_t op1", + "uint64_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcls_s32", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s16]_m", "arguments": [ - "int32x2_t a" + "svbool_t pg", + "svint16_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "ASR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcls_s8", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s16]_x", "arguments": [ - "int8x8_t a" + "svbool_t pg", + "svint16_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int8x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcls_u16", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s16]_z", "arguments": [ - "uint16x4_t a" + "svbool_t pg", + "svint16_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcls_u32", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s32]_m", "arguments": [ - "uint32x2_t a" + "svbool_t pg", + "svint32_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "ASR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcls_u8", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s32]_x", "arguments": [ - "uint8x8_t a" + "svbool_t pg", + "svint32_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int8x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclsq_s16", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s32]_z", "arguments": [ - "int16x8_t a" + "svbool_t pg", + "svint32_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclsq_s32", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s8]_m", "arguments": [ - "int32x4_t a" + "svbool_t pg", + "svint8_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "ASR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclsq_s8", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s8]_x", "arguments": [ - "int8x16_t a" + "svbool_t pg", + "svint8_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int8x16_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclsq_u16", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s8]_z", "arguments": [ - "uint16x8_t a" + "svbool_t pg", + "svint8_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclsq_u32", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s16]_m", "arguments": [ - "uint32x4_t a" + "svbool_t pg", + "svint16_t op1", + "uint64_t imm2" ], "return_type": { - "value": "int32x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclsq_u8", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s16]_x", "arguments": [ - "uint8x16_t a" + "svbool_t pg", + "svint16_t op1", + "uint64_t imm2" ], "return_type": { - "value": "int8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclt_f16", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s16]_z", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svbool_t pg", + "svint16_t op1", + "uint64_t imm2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "imm2": { + "minimum": 1, + "maximum": 16 }, - "b": { - "register": "Vm.4H" + "op1": { + "register": "Zop1.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGT" + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclt_f32", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s32]_m", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svbool_t pg", + "svint32_t op1", + "uint64_t imm2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "imm2": { + "minimum": 1, + "maximum": 32 }, - "b": { - "register": "Vm.2S" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCMGT" + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclt_f64", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s32]_x", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svbool_t pg", + "svint32_t op1", + "uint64_t imm2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "imm2": { + "minimum": 1, + "maximum": 32 }, - "b": { - "register": "Dm" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -14010,84 +17059,104 @@ ], "instructions": [ [ - "FCMGT" + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclt_s16", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s32]_z", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "svbool_t pg", + "svint32_t op1", + "uint64_t imm2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "imm2": { + "minimum": 1, + "maximum": 32 }, - "b": { - "register": "Vm.4H" + "op1": { + "register": "Zop1.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclt_s32", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s64]_m", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "svbool_t pg", + "svint64_t op1", + "uint64_t imm2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "imm2": { + "minimum": 1, + "maximum": 64 }, - "b": { - "register": "Vm.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclt_s64", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s64]_x", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "svbool_t pg", + "svint64_t op1", + "uint64_t imm2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "imm2": { + "minimum": 1, + "maximum": 64 }, - "b": { - "register": "Dm" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -14095,113 +17164,140 @@ ], "instructions": [ [ - "CMGT" + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclt_s8", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s64]_z", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "svbool_t pg", + "svint64_t op1", + "uint64_t imm2" ], "return_type": { - "value": "uint8x8_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "imm2": { + "minimum": 1, + "maximum": 64 }, - "b": { - "register": "Vm.8B" + "op1": { + "register": "Zop1.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclt_u16", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s8]_m", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "svbool_t pg", + "svint8_t op1", + "uint64_t imm2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "imm2": { + "minimum": 1, + "maximum": 8 }, - "b": { - "register": "Vm.4H" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclt_u32", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s8]_x", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "svbool_t pg", + "svint8_t op1", + "uint64_t imm2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "imm2": { + "minimum": 1, + "maximum": 8 }, - "b": { - "register": "Vm.2S" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclt_u64", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s8]_z", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "svbool_t pg", + "svint8_t op1", + "uint64_t imm2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "imm2": { + "minimum": 1, + "maximum": 8 }, - "b": { - "register": "Dm" + "op1": { + "register": "Zop1.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -14209,55 +17305,66 @@ ], "instructions": [ [ - "CMHI" + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclt_u8", + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_s16]", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "svint16_t op1", + "svint16_t op2", + "int16_t op3" ], "return_type": { - "value": "uint8x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltd_f64", + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_s32]", "arguments": [ - "float64_t a", - "float64_t b" + "svint32_t op1", + "svint32_t op2", + "int32_t op3" ], "return_type": { - "value": "uint64_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ @@ -14265,26 +17372,34 @@ ], "instructions": [ [ - "FCMGT" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltd_s64", + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_s64]", "arguments": [ - "int64_t a", - "int64_t b" + "svint64_t op1", + "svint64_t op2", + "int64_t op3" ], "return_type": { - "value": "uint64_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" } }, "Architectures": [ @@ -14292,26 +17407,34 @@ ], "instructions": [ [ - "CMGT" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltd_u64", + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_s8]", "arguments": [ - "uint64_t a", - "uint64_t b" + "svint8_t op1", + "svint8_t op2", + "int8_t op3" ], "return_type": { - "value": "uint64_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ @@ -14319,26 +17442,34 @@ ], "instructions": [ [ - "CMHI" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclth_f16", + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_u16]", "arguments": [ - "float16_t a", - "float16_t b" + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" ], "return_type": { - "value": "uint16_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Hm" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ @@ -14346,83 +17477,104 @@ ], "instructions": [ [ - "FCMGT" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltq_f16", + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_u32]", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGT" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltq_f32", + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_u64]", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCMGT" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltq_f64", + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_u8]", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ @@ -14430,84 +17582,104 @@ ], "instructions": [ [ - "FCMGT" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltq_s16", + "SIMD_ISA": "SVE2", + "name": "svbcax[_s16]", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltq_s32", + "SIMD_ISA": "SVE2", + "name": "svbcax[_s32]", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" ], "return_type": { - "value": "uint32x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltq_s64", + "SIMD_ISA": "SVE2", + "name": "svbcax[_s64]", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" ], "return_type": { - "value": "uint64x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" } }, "Architectures": [ @@ -14515,113 +17687,139 @@ ], "instructions": [ [ - "CMGT" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltq_s8", + "SIMD_ISA": "SVE2", + "name": "svbcax[_s8]", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" ], "return_type": { - "value": "uint8x16_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltq_u16", + "SIMD_ISA": "SVE2", + "name": "svbcax[_u16]", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltq_u32", + "SIMD_ISA": "SVE2", + "name": "svbcax[_u32]", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltq_u64", + "SIMD_ISA": "SVE2", + "name": "svbcax[_u64]", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" } }, "Architectures": [ @@ -14629,55 +17827,65 @@ ], "instructions": [ [ - "CMHI" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltq_u8", + "SIMD_ISA": "SVE2", + "name": "svbcax[_u8]", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclts_f32", + "SIMD_ISA": "SVE2", + "name": "svbdep[_n_u16]", "arguments": [ - "float32_t a", - "float32_t b" + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Sm" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -14685,46 +17893,53 @@ ], "instructions": [ [ - "FCMGT" + "BDEP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltz_f16", + "SIMD_ISA": "SVE2", + "name": "svbdep[_n_u32]", "arguments": [ - "float16x4_t a" + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLT" + "BDEP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltz_f32", + "SIMD_ISA": "SVE2", + "name": "svbdep[_n_u64]", "arguments": [ - "float32x2_t a" + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" } }, "Architectures": [ @@ -14732,22 +17947,26 @@ ], "instructions": [ [ - "FCMLT" + "BDEP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltz_f64", + "SIMD_ISA": "SVE2", + "name": "svbdep[_n_u8]", "arguments": [ - "float64x1_t a" + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ @@ -14755,22 +17974,26 @@ ], "instructions": [ [ - "FCMLT" + "BDEP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltz_s16", + "SIMD_ISA": "SVE2", + "name": "svbdep[_u16]", "arguments": [ - "int16x4_t a" + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -14778,22 +18001,26 @@ ], "instructions": [ [ - "CMLT" + "BDEP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltz_s32", + "SIMD_ISA": "SVE2", + "name": "svbdep[_u32]", "arguments": [ - "int32x2_t a" + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" } }, "Architectures": [ @@ -14801,22 +18028,26 @@ ], "instructions": [ [ - "CMLT" + "BDEP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltz_s64", + "SIMD_ISA": "SVE2", + "name": "svbdep[_u64]", "arguments": [ - "int64x1_t a" + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" } }, "Architectures": [ @@ -14824,22 +18055,26 @@ ], "instructions": [ [ - "CMLT" + "BDEP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltz_s8", + "SIMD_ISA": "SVE2", + "name": "svbdep[_u8]", "arguments": [ - "int8x8_t a" + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -14847,22 +18082,26 @@ ], "instructions": [ [ - "CMLT" + "BDEP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltzd_f64", + "SIMD_ISA": "SVE2", + "name": "svbext[_n_u16]", "arguments": [ - "float64_t a" + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -14870,22 +18109,26 @@ ], "instructions": [ [ - "FCMLT" + "BEXT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltzd_s64", + "SIMD_ISA": "SVE2", + "name": "svbext[_n_u32]", "arguments": [ - "int64_t a" + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ @@ -14893,22 +18136,26 @@ ], "instructions": [ [ - "CMLT" + "BEXT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltzh_f16", + "SIMD_ISA": "SVE2", + "name": "svbext[_n_u64]", "arguments": [ - "float16_t a" + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" } }, "Architectures": [ @@ -14916,46 +18163,53 @@ ], "instructions": [ [ - "FCMLT" + "BEXT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltzq_f16", + "SIMD_ISA": "SVE2", + "name": "svbext[_n_u8]", "arguments": [ - "float16x8_t a" + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLT" + "BEXT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltzq_f32", + "SIMD_ISA": "SVE2", + "name": "svbext[_u16]", "arguments": [ - "float32x4_t a" + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -14963,22 +18217,26 @@ ], "instructions": [ [ - "FCMLT" + "BEXT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltzq_f64", + "SIMD_ISA": "SVE2", + "name": "svbext[_u32]", "arguments": [ - "float64x2_t a" + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" } }, "Architectures": [ @@ -14986,22 +18244,26 @@ ], "instructions": [ [ - "FCMLT" + "BEXT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltzq_s16", + "SIMD_ISA": "SVE2", + "name": "svbext[_u64]", "arguments": [ - "int16x8_t a" + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" } }, "Architectures": [ @@ -15009,22 +18271,26 @@ ], "instructions": [ [ - "CMLT" + "BEXT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltzq_s32", + "SIMD_ISA": "SVE2", + "name": "svbext[_u8]", "arguments": [ - "int32x4_t a" + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -15032,22 +18298,26 @@ ], "instructions": [ [ - "CMLT" + "BEXT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltzq_s64", + "SIMD_ISA": "SVE2", + "name": "svbgrp[_n_u16]", "arguments": [ - "int64x2_t a" + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -15055,22 +18325,26 @@ ], "instructions": [ [ - "CMLT" + "BGRP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltzq_s8", + "SIMD_ISA": "SVE2", + "name": "svbgrp[_n_u32]", "arguments": [ - "int8x16_t a" + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ @@ -15078,22 +18352,26 @@ ], "instructions": [ [ - "CMLT" + "BGRP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltzs_f32", + "SIMD_ISA": "SVE2", + "name": "svbgrp[_n_u64]", "arguments": [ - "float32_t a" + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" } }, "Architectures": [ @@ -15101,1138 +18379,1299 @@ ], "instructions": [ [ - "FCMLT" + "BGRP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclz_s16", + "SIMD_ISA": "SVE2", + "name": "svbgrp[_n_u8]", "arguments": [ - "int16x4_t a" + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "BGRP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclz_s32", + "SIMD_ISA": "SVE2", + "name": "svbgrp[_u16]", "arguments": [ - "int32x2_t a" + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "BGRP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclz_s8", + "SIMD_ISA": "SVE2", + "name": "svbgrp[_u32]", "arguments": [ - "int8x8_t a" + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "int8x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "BGRP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclz_u16", + "SIMD_ISA": "SVE2", + "name": "svbgrp[_u64]", "arguments": [ - "uint16x4_t a" + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "BGRP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclz_u32", + "SIMD_ISA": "SVE2", + "name": "svbgrp[_u8]", "arguments": [ - "uint32x2_t a" + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "BGRP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclz_u8", + "SIMD_ISA": "SVE", + "name": "svbic[_b]_z", "arguments": [ - "uint8x8_t a" + "svbool_t pg", + "svbool_t op1", + "svbool_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Pop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclzq_s16", + "SIMD_ISA": "SVE", + "name": "svbic[_n_s16]_m", "arguments": [ - "int16x8_t a" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "BIC" + ], + [ + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclzq_s32", + "SIMD_ISA": "SVE", + "name": "svbic[_n_s16]_x", "arguments": [ - "int32x4_t a" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "AND" + ], + [ + "BIC" + ], + [ + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclzq_s8", + "SIMD_ISA": "SVE", + "name": "svbic[_n_s16]_z", "arguments": [ - "int8x16_t a" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "int8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclzq_u16", + "SIMD_ISA": "SVE", + "name": "svbic[_n_s32]_m", "arguments": [ - "uint16x8_t a" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "BIC" + ], + [ + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclzq_u32", + "SIMD_ISA": "SVE", + "name": "svbic[_n_s32]_x", "arguments": [ - "uint32x4_t a" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "AND" + ], + [ + "BIC" + ], + [ + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclzq_u8", + "SIMD_ISA": "SVE", + "name": "svbic[_n_s32]_z", "arguments": [ - "uint8x16_t a" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmla_f16", + "SIMD_ISA": "SVE", + "name": "svbic[_n_s64]_m", "arguments": [ - "float16x4_t r", - "float16x4_t a", - "float16x4_t b" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "float16x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.4H" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BIC" + ], + [ + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmla_f32", + "SIMD_ISA": "SVE", + "name": "svbic[_n_s64]_x", "arguments": [ - "float32x2_t r", - "float32x2_t a", - "float32x2_t b" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "AND" + ], + [ + "BIC" + ], + [ + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmla_lane_f16", + "SIMD_ISA": "SVE", + "name": "svbic[_n_s64]_z", "arguments": [ - "float16x4_t r", - "float16x4_t a", - "float16x4_t b", - "const int lane" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "float16x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.D" }, - "r": { - "register": "Vd.4H" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmla_lane_f32", + "SIMD_ISA": "SVE", + "name": "svbic[_n_s8]_m", "arguments": [ - "float32x2_t r", - "float32x2_t a", - "float32x2_t b", - "const int lane" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "r": { - "register": "Vd.2S" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BIC" + ], + [ + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmla_laneq_f16", + "SIMD_ISA": "SVE", + "name": "svbic[_n_s8]_x", "arguments": [ - "float16x4_t r", - "float16x4_t a", - "float16x8_t b", - "const int lane" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "float16x4_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "r": { - "register": "Vd.4H" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "AND" + ], + [ + "BIC" + ], + [ + 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"vcmlaq_rot180_f16", + "SIMD_ISA": "SVE", + "name": "svbic[_u16]_x", "arguments": [ - "float16x8_t r", - "float16x8_t a", - "float16x8_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BIC" + ], + [ + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot180_f32", + "SIMD_ISA": "SVE", + "name": "svbic[_u16]_z", "arguments": [ - "float32x4_t r", - "float32x4_t a", - "float32x4_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.4S" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot180_f64", + "SIMD_ISA": "SVE", + "name": "svbic[_u32]_m", "arguments": [ - "float64x2_t r", - "float64x2_t a", - "float64x2_t b" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.2D" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -16455,214 +19913,236 @@ ], "instructions": [ [ - "FCMLA" + "BIC" + ], + [ + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot180_lane_f16", + "SIMD_ISA": "SVE", + "name": "svbic[_u32]_x", "arguments": [ - "float16x8_t r", - "float16x8_t a", - "float16x4_t b", - "const int lane" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "r": { - "register": "Vd.8H" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BIC" + ], + [ + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot180_lane_f32", + "SIMD_ISA": "SVE", + "name": "svbic[_u32]_z", "arguments": [ - "float32x4_t r", - "float32x4_t a", - "float32x2_t b", - "const int lane" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.S" }, - "r": { - "register": "Vd.4S" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot180_laneq_f16", + "SIMD_ISA": "SVE", + "name": "svbic[_u64]_m", "arguments": [ - "float16x8_t r", - "float16x8_t a", - "float16x8_t b", - "const int lane" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "r": { - "register": "Vd.8H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BIC" + ], + [ + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot180_laneq_f32", + "SIMD_ISA": "SVE", + "name": "svbic[_u64]_x", "arguments": [ - "float32x4_t r", - "float32x4_t a", - "float32x4_t b", - "const int lane" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "r": { - "register": "Vd.4S" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BIC" + ], + [ + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot270_f16", + "SIMD_ISA": "SVE", + "name": "svbic[_u64]_z", "arguments": [ - "float16x8_t r", - "float16x8_t a", - "float16x8_t b" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.8H" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot270_f32", + "SIMD_ISA": "SVE", + "name": "svbic[_u8]_m", "arguments": [ - "float32x4_t r", - "float32x4_t a", - "float32x4_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.4S" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BIC" + ], + [ + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot270_f64", + "SIMD_ISA": "SVE", + "name": "svbic[_u8]_x", "arguments": [ - "float64x2_t r", - "float64x2_t a", - "float64x2_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.2D" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -16670,214 +20150,212 @@ ], "instructions": [ [ - "FCMLA" + "BIC" + ], + [ + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot270_lane_f16", + "SIMD_ISA": "SVE", + "name": "svbic[_u8]_z", "arguments": [ - "float16x8_t r", - "float16x8_t a", - "float16x4_t b", - "const int lane" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.B" }, - "r": { - "register": "Vd.8H" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot270_lane_f32", + "SIMD_ISA": "SVE", + "name": "svbrka[_b]_m", "arguments": [ - "float32x4_t r", - "float32x4_t a", - "float32x2_t b", - "const int lane" + "svbool_t inactive", + "svbool_t pg", + "svbool_t op" ], "return_type": { - "value": "float32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 0 + "inactive": { + "register": "Ptied.B" }, - "r": { - "register": "Vd.4S" + "op": { + "register": "Pop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BRKA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot270_laneq_f16", + "SIMD_ISA": "SVE", + "name": "svbrka[_b]_z", "arguments": [ - "float16x8_t r", - "float16x8_t a", - "float16x8_t b", - "const int lane" + "svbool_t pg", + "svbool_t op" ], "return_type": { - "value": "float16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 3 + "op": { + "register": "Pop.B" }, - "r": { - "register": "Vd.8H" + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BRKA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot270_laneq_f32", + "SIMD_ISA": "SVE", + "name": "svbrkb[_b]_m", "arguments": [ - "float32x4_t r", - "float32x4_t a", - "float32x4_t b", - "const int lane" + "svbool_t inactive", + "svbool_t pg", + "svbool_t op" ], "return_type": { - "value": "float32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 1 + "inactive": { + "register": "Ptied.B" }, - "r": { - "register": "Vd.4S" + "op": { + "register": "Pop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BRKB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot90_f16", + "SIMD_ISA": "SVE", + "name": "svbrkb[_b]_z", "arguments": [ - "float16x8_t r", - "float16x8_t a", - "float16x8_t b" + "svbool_t pg", + "svbool_t op" ], "return_type": { - "value": "float16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.8H" + "op": { + "register": "Pop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BRKB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot90_f32", + "SIMD_ISA": "SVE", + "name": "svbrkn[_b]_z", "arguments": [ - "float32x4_t r", - "float32x4_t a", - "float32x4_t b" + "svbool_t pg", + "svbool_t op1", + "svbool_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.4S" + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Ptied2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BRKN" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot90_f64", + "SIMD_ISA": "SVE", + "name": "svbrkpa[_b]_z", "arguments": [ - "float64x2_t r", - "float64x2_t a", - "float64x2_t b" + "svbool_t pg", + "svbool_t op1", + "svbool_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.2D" + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Pop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -16885,368 +20363,446 @@ ], "instructions": [ [ - "FCMLA" + "BRKPA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot90_lane_f16", + "SIMD_ISA": "SVE", + "name": "svbrkpb[_b]_z", "arguments": [ - "float16x8_t r", - "float16x8_t a", - "float16x4_t b", - "const int lane" + "svbool_t pg", + "svbool_t op1", + "svbool_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Pop1.B" }, - "r": { - "register": "Vd.8H" + "op2": { + "register": "Pop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BRKPB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot90_lane_f32", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_s16]", "arguments": [ - "float32x4_t r", - "float32x4_t a", - "float32x2_t b", - "const int lane" + "svint16_t op1", + "svint16_t op2", + "int16_t op3" ], "return_type": { - "value": "float32x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "r": { - "register": "Vd.4S" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot90_laneq_f16", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_s32]", "arguments": [ - "float16x8_t r", - "float16x8_t a", - "float16x8_t b", - "const int lane" + "svint32_t op1", + "svint32_t op2", + "int32_t op3" ], "return_type": { - "value": "float16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "r": { - "register": "Vd.8H" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot90_laneq_f32", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_s64]", "arguments": [ - "float32x4_t r", - "float32x4_t a", - "float32x4_t b", - "const int lane" + "svint64_t op1", + "svint64_t op2", + "int64_t op3" ], "return_type": { - "value": "float32x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "r": { - "register": "Vd.4S" + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcnt_p8", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_s8]", "arguments": [ - "poly8x8_t a" + "svint8_t op1", + "svint8_t op2", + "int8_t op3" ], "return_type": { - "value": "poly8x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CNT" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcnt_s8", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_u16]", "arguments": [ - "int8x8_t a" + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" ], "return_type": { - "value": "int8x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CNT" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcnt_u8", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_u32]", "arguments": [ - "uint8x8_t a" + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" ], "return_type": { - "value": "uint8x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CNT" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcntq_p8", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_u64]", "arguments": [ - "poly8x16_t a" + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" ], "return_type": { - "value": "poly8x16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CNT" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcntq_s8", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_u8]", "arguments": [ - "int8x16_t a" + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" ], "return_type": { - "value": "int8x16_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CNT" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcntq_u8", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_s16]", "arguments": [ - "uint8x16_t a" + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" ], "return_type": { - "value": "uint8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CNT" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_f16", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_s32]", "arguments": [ - "float16x4_t low", - "float16x4_t high" + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" ], "return_type": { - "value": "float16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.4H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "low": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_f32", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_s64]", "arguments": [ - "float32x2_t low", - "float32x2_t high" + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" ], "return_type": { - "value": "float32x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "low": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_f64", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_s8]", "arguments": [ - "float64x1_t low", - "float64x1_t high" + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" ], "return_type": { - "value": "float64x2_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.1D" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "low": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" } }, "Architectures": [ @@ -17254,366 +20810,419 @@ ], "instructions": [ [ - "DUP", - "INS" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_p16", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_u16]", "arguments": [ - "poly16x4_t low", - "poly16x4_t high" + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" ], "return_type": { - "value": "poly16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.4H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "low": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_p64", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_u32]", "arguments": [ - "poly64x1_t low", - "poly64x1_t high" + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" ], "return_type": { - "value": "poly64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.1D" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "low": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_p8", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_u64]", "arguments": [ - "poly8x8_t low", - "poly8x8_t high" + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" ], "return_type": { - "value": "poly8x16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.8B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "low": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_s16", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_u8]", "arguments": [ - "int16x4_t low", - "int16x4_t high" + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" ], "return_type": { - "value": "int16x8_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.4H" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "low": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_s32", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_s16]", "arguments": [ - "int32x2_t low", - "int32x2_t high" + "svint16_t op1", + "svint16_t op2", + "int16_t op3" ], "return_type": { - "value": "int32x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.2S" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "low": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_s64", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_s32]", "arguments": [ - "int64x1_t low", - "int64x1_t high" + "svint32_t op1", + "svint32_t op2", + "int32_t op3" ], "return_type": { - "value": "int64x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.1D" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "low": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_s8", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_s64]", "arguments": [ - "int8x8_t low", - "int8x8_t high" + "svint64_t op1", + "svint64_t op2", + "int64_t op3" ], "return_type": { - "value": "int8x16_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.8B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "low": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_u16", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_s8]", "arguments": [ - "uint16x4_t low", - "uint16x4_t high" + "svint8_t op1", + "svint8_t op2", + "int8_t op3" ], "return_type": { - "value": "uint16x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.4H" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "low": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_u32", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_u16]", "arguments": [ - "uint32x2_t low", - "uint32x2_t high" + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.2S" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "low": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_u64", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_u32]", "arguments": [ - "uint64x1_t low", - "uint64x1_t high" + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.1D" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "low": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_u8", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_u64]", "arguments": [ - "uint8x8_t low", - "uint8x8_t high" + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.8B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "low": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_f32", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_u8]", "arguments": [ - "float32x2_t a", - "const int lane1", - "float32x2_t b", - "const int lane2" + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" ], "return_type": { - "value": "float32x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "lane1": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.B" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ @@ -17621,36 +21230,34 @@ ], "instructions": [ [ - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_f64", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_s16]", "arguments": [ - "float64x1_t a", - "const int lane1", - "float64x1_t b", - "const int lane2" + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" ], "return_type": { - "value": "float64x1_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "UNUSED" - }, - "b": { - "register": "Vn.1D" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "lane1": { - "minimum": 0, - "maximum": 0 + "op2": { + "register": "Zop2.H" }, - "lane2": { - "minimum": 0, - "maximum": 0 + "op3": { + "register": "Zop3.H" } }, "Architectures": [ @@ -17658,36 +21265,34 @@ ], "instructions": [ [ - "DUP" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_p16", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_s32]", "arguments": [ - "poly16x4_t a", - "const int lane1", - "poly16x4_t b", - "const int lane2" + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" ], "return_type": { - "value": "poly16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "lane1": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.S" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "op3": { + "register": "Zop3.S" } }, "Architectures": [ @@ -17695,74 +21300,69 @@ ], "instructions": [ [ - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_p64", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_s64]", "arguments": [ - "poly64x1_t a", - "const int lane1", - "poly64x1_t b", - "const int lane2" + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" ], "return_type": { - "value": "poly64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "UNUSED" - }, - "b": { - "register": "Vn.1D" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "lane1": { - "minimum": 0, - "maximum": 0 + "op2": { + "register": "Zop2.D" }, - "lane2": { - "minimum": 0, - "maximum": 0 + "op3": { + "register": "Zop3.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "DUP" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_p8", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_s8]", "arguments": [ - "poly8x8_t a", - "const int lane1", - "poly8x8_t b", - "const int lane2" + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" ], "return_type": { - "value": "poly8x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vn.8B" - }, - "lane1": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.B" }, - "lane2": { - "minimum": 0, - "maximum": 7 + "op3": { + "register": "Zop3.B" } }, "Architectures": [ @@ -17770,36 +21370,34 @@ ], "instructions": [ [ - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_s16", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_u16]", "arguments": [ - "int16x4_t a", - "const int lane1", - "int16x4_t b", - "const int lane2" + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" ], "return_type": { - "value": "int16x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.4H" - }, - "lane1": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.H" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "op3": { + "register": "Zop3.H" } }, "Architectures": [ @@ -17807,36 +21405,34 @@ ], "instructions": [ [ - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_s32", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_u32]", "arguments": [ - "int32x2_t a", - "const int lane1", - "int32x2_t b", - "const int lane2" + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" ], "return_type": { - "value": "int32x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.2S" - }, - "lane1": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.S" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op3": { + "register": "Zop3.S" } }, "Architectures": [ @@ -17844,36 +21440,34 @@ ], "instructions": [ [ - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_s64", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_u64]", "arguments": [ - "int64x1_t a", - "const int lane1", - "int64x1_t b", - "const int lane2" + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" ], "return_type": { - "value": "int64x1_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "UNUSED" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.1D" - }, - "lane1": { - "minimum": 0, - "maximum": 0 + "op2": { + "register": "Zop2.D" }, - "lane2": { - "minimum": 0, - "maximum": 0 + "op3": { + "register": "Zop3.D" } }, "Architectures": [ @@ -17881,36 +21475,34 @@ ], "instructions": [ [ - "DUP" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_s8", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_u8]", "arguments": [ - "int8x8_t a", - "const int lane1", - "int8x8_t b", - "const int lane2" + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" ], "return_type": { - "value": "int8x8_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vn.8B" - }, - "lane1": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.B" }, - "lane2": { - "minimum": 0, - "maximum": 7 + "op3": { + "register": "Zop3.B" } }, "Architectures": [ @@ -17918,36 +21510,34 @@ ], "instructions": [ [ - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_u16", + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_s16]", "arguments": [ - "uint16x4_t a", - "const int lane1", - "uint16x4_t b", - "const int lane2" + "svint16_t op1", + "svint16_t op2", + "int16_t op3" ], "return_type": { - "value": "uint16x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.4H" - }, - "lane1": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.H" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ @@ -17955,36 +21545,34 @@ ], "instructions": [ [ - "INS" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_u32", + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_s32]", "arguments": [ - "uint32x2_t a", - "const int lane1", - "uint32x2_t b", - "const int lane2" + "svint32_t op1", + "svint32_t op2", + "int32_t op3" ], "return_type": { - "value": "uint32x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "lane1": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.S" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ @@ -17992,36 +21580,34 @@ ], "instructions": [ [ - "INS" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_u64", + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_s64]", "arguments": [ - "uint64x1_t a", - "const int lane1", - "uint64x1_t b", - "const int lane2" + "svint64_t op1", + "svint64_t op2", + "int64_t op3" ], "return_type": { - "value": "uint64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "UNUSED" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.1D" - }, - "lane1": { - "minimum": 0, - "maximum": 0 + "op2": { + "register": "Zop2.D" }, - "lane2": { - "minimum": 0, - "maximum": 0 + "op3": { + "register": "Zop3.D[*]" } }, "Architectures": [ @@ -18029,36 +21615,34 @@ ], "instructions": [ [ - "DUP" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_u8", + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_s8]", "arguments": [ - "uint8x8_t a", - "const int lane1", - "uint8x8_t b", - "const int lane2" + "svint8_t op1", + "svint8_t op2", + "int8_t op3" ], "return_type": { - "value": "uint8x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" - }, - "b": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "lane1": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.B" }, - "lane2": { - "minimum": 0, - "maximum": 7 + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ @@ -18066,36 +21650,34 @@ ], "instructions": [ [ - "INS" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_f32", + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_u16]", "arguments": [ - "float32x2_t a", - "const int lane1", - "float32x4_t b", - "const int lane2" + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" ], "return_type": { - "value": "float32x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2S" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.4S" - }, - "lane1": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.H" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ @@ -18103,36 +21685,34 @@ ], "instructions": [ [ - "INS" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_f64", + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_u32]", "arguments": [ - "float64x1_t a", - "const int lane1", - "float64x2_t b", - "const int lane2" + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" ], "return_type": { - "value": "float64x1_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "UNUSED" - }, - "b": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "lane1": { - "minimum": 0, - "maximum": 0 + "op2": { + "register": "Zop2.S" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ @@ -18140,36 +21720,34 @@ ], "instructions": [ [ - "DUP" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_p16", + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_u64]", "arguments": [ - "poly16x4_t a", - "const int lane1", - "poly16x8_t b", - "const int lane2" + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" ], "return_type": { - "value": "poly16x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4H" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.8H" - }, - "lane1": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.D" }, - "lane2": { - "minimum": 0, - "maximum": 7 + "op3": { + "register": "Zop3.D[*]" } }, "Architectures": [ @@ -18177,74 +21755,69 @@ ], "instructions": [ [ - "INS" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_p64", + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_u8]", "arguments": [ - "poly64x1_t a", - "const int lane1", - "poly64x2_t b", - "const int lane2" + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" ], "return_type": { - "value": "poly64x1_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "UNUSED" - }, - "b": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "lane1": { - "minimum": 0, - "maximum": 0 + "op2": { + "register": "Zop2.B" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "DUP" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_p8", + "SIMD_ISA": "SVE2", + "name": "svbsl[_s16]", "arguments": [ - "poly8x8_t a", - "const int lane1", - "poly8x16_t b", - "const int lane2" + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" ], "return_type": { - "value": "poly8x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" - }, - "b": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "lane1": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.H" }, - "lane2": { - "minimum": 0, - "maximum": 15 + "op3": { + "register": "Zop3.H" } }, "Architectures": [ @@ -18252,36 +21825,34 @@ ], "instructions": [ [ - "INS" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_s16", + "SIMD_ISA": "SVE2", + "name": "svbsl[_s32]", "arguments": [ - "int16x4_t a", - "const int lane1", - "int16x8_t b", - "const int lane2" + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" ], "return_type": { - "value": "int16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "lane1": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.S" }, - "lane2": { - "minimum": 0, - "maximum": 7 + "op3": { + "register": "Zop3.S" } }, "Architectures": [ @@ -18289,36 +21860,34 @@ ], "instructions": [ [ - "INS" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_s32", + "SIMD_ISA": "SVE2", + "name": "svbsl[_s64]", "arguments": [ - "int32x2_t a", - "const int lane1", - "int32x4_t b", - "const int lane2" + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" ], "return_type": { - "value": "int32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "lane1": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.D" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "op3": { + "register": "Zop3.D" } }, "Architectures": [ @@ -18326,36 +21895,34 @@ ], "instructions": [ [ - "INS" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_s64", + "SIMD_ISA": "SVE2", + "name": "svbsl[_s8]", "arguments": [ - "int64x1_t a", - "const int lane1", - "int64x2_t b", - "const int lane2" + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" ], "return_type": { - "value": "int64x1_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "UNUSED" - }, - "b": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "lane1": { - "minimum": 0, - "maximum": 0 + "op2": { + "register": "Zop2.B" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op3": { + "register": "Zop3.B" } }, "Architectures": [ @@ -18363,36 +21930,34 @@ ], "instructions": [ [ - "DUP" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_s8", + "SIMD_ISA": "SVE2", + "name": "svbsl[_u16]", "arguments": [ - "int8x8_t a", - "const int lane1", - "int8x16_t b", - "const int lane2" + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" ], "return_type": { - "value": "int8x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" - }, - "b": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "lane1": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.H" }, - "lane2": { - "minimum": 0, - "maximum": 15 + "op3": { + "register": "Zop3.H" } }, "Architectures": [ @@ -18400,36 +21965,34 @@ ], "instructions": [ [ - "INS" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_u16", + "SIMD_ISA": "SVE2", + "name": "svbsl[_u32]", "arguments": [ - "uint16x4_t a", - "const int lane1", - "uint16x8_t b", - "const int lane2" + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "lane1": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.S" }, - "lane2": { - "minimum": 0, - "maximum": 7 + "op3": { + "register": "Zop3.S" } }, "Architectures": [ @@ -18437,36 +22000,34 @@ ], "instructions": [ [ - "INS" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_u32", + "SIMD_ISA": "SVE2", + "name": "svbsl[_u64]", "arguments": [ - "uint32x2_t a", - "const int lane1", - "uint32x4_t b", - "const int lane2" + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "lane1": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.D" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "op3": { + "register": "Zop3.D" } }, "Architectures": [ @@ -18474,36 +22035,34 @@ ], "instructions": [ [ - "INS" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_u64", + "SIMD_ISA": "SVE2", + "name": "svbsl[_u8]", "arguments": [ - "uint64x1_t a", - "const int lane1", - "uint64x2_t b", - "const int lane2" + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "UNUSED" - }, - "b": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "lane1": { - "minimum": 0, - "maximum": 0 + "op2": { + "register": "Zop2.B" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op3": { + "register": "Zop3.B" } }, "Architectures": [ @@ -18511,36 +22070,35 @@ ], "instructions": [ [ - "DUP" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_u8", + "SIMD_ISA": "SVE", + "name": "svcadd[_f16]_m", "arguments": [ - "uint8x8_t a", - "const int lane1", - "uint8x16_t b", - "const int lane2" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint8x8_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" - }, - "b": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "lane1": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.H" }, - "lane2": { - "minimum": 0, - "maximum": 15 + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -18548,36 +22106,35 @@ ], "instructions": [ [ - "INS" + "FCADD" + ], + [ + "MOVPRFX", + "FCADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_f32", + "SIMD_ISA": "SVE", + "name": "svcadd[_f16]_x", "arguments": [ - "float32x4_t a", - "const int lane1", - "float32x2_t b", - "const int lane2" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "float32x4_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "lane1": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.H" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -18585,36 +22142,35 @@ ], "instructions": [ [ - "INS" + "FCADD" + ], + [ + "MOVPRFX", + "FCADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_f64", + "SIMD_ISA": "SVE", + "name": "svcadd[_f16]_z", "arguments": [ - "float64x2_t a", - "const int lane1", - "float64x1_t b", - "const int lane2" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "float64x2_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.1D" + "op1": { + "register": "Zop1.H" }, - "lane1": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.H" }, - "lane2": { - "minimum": 0, - "maximum": 0 + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -18622,36 +22178,32 @@ ], "instructions": [ [ - "INS" + "MOVPRFX", + "FCADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_p16", + "SIMD_ISA": "SVE", + "name": "svcadd[_f32]_m", "arguments": [ - "poly16x8_t a", - "const int lane1", - "poly16x4_t b", - "const int lane2" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "poly16x8_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "lane1": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.S" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -18659,74 +22211,71 @@ ], "instructions": [ [ - "INS" + "FCADD" + ], + [ + "MOVPRFX", + "FCADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_p64", + "SIMD_ISA": "SVE", + "name": "svcadd[_f32]_x", "arguments": [ - "poly64x2_t a", - "const int lane1", - "poly64x1_t b", - "const int lane2" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "poly64x2_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.1D" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "lane1": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.S" }, - "lane2": { - "minimum": 0, - "maximum": 0 + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "INS" + "FCADD" + ], + [ + "MOVPRFX", + "FCADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_p8", + "SIMD_ISA": "SVE", + "name": "svcadd[_f32]_z", "arguments": [ - "poly8x16_t a", - "const int lane1", - "poly8x8_t b", - "const int lane2" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "poly8x16_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" - }, - "b": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S" }, - "lane1": { - "minimum": 0, - "maximum": 15 + "op2": { + "register": "Zop2.S" }, - "lane2": { - "minimum": 0, - "maximum": 7 + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -18734,36 +22283,32 @@ ], "instructions": [ [ - "INS" + "MOVPRFX", + "FCADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_s16", + "SIMD_ISA": "SVE", + "name": "svcadd[_f64]_m", "arguments": [ - "int16x8_t a", - "const int lane1", - "int16x4_t b", - "const int lane2" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "int16x8_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "lane1": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.D" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -18771,36 +22316,35 @@ ], "instructions": [ [ - "INS" + "FCADD" + ], + [ + "MOVPRFX", + "FCADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_s32", + "SIMD_ISA": "SVE", + "name": "svcadd[_f64]_x", "arguments": [ - "int32x4_t a", - "const int lane1", - "int32x2_t b", - "const int lane2" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "int32x4_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.2S" - }, - "lane1": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.D" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -18808,36 +22352,35 @@ ], "instructions": [ [ - "INS" + "FCADD" + ], + [ + "MOVPRFX", + "FCADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_s64", + "SIMD_ISA": "SVE", + "name": "svcadd[_f64]_z", "arguments": [ - "int64x2_t a", - "const int lane1", - "int64x1_t b", - "const int lane2" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "int64x2_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.1D" + "op1": { + "register": "Zop1.D" }, - "lane1": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.D" }, - "lane2": { - "minimum": 0, - "maximum": 0 + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -18845,36 +22388,28 @@ ], "instructions": [ [ - "INS" + "MOVPRFX", + "FCADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_s8", + "SIMD_ISA": "SVE2", + "name": "svcadd[_s16]", "arguments": [ - "int8x16_t a", - "const int lane1", - "int8x8_t b", - "const int lane2" + "svint16_t op1", + "svint16_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "int8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" - }, - "b": { - "register": "Vn.8B" - }, - "lane1": { - "minimum": 0, - "maximum": 15 + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "lane2": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -18882,36 +22417,31 @@ ], "instructions": [ [ - "INS" + "CADD" + ], + [ + "MOVPRFX", + "CADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_u16", + "SIMD_ISA": "SVE2", + "name": "svcadd[_s32]", "arguments": [ - "uint16x8_t a", - "const int lane1", - "uint16x4_t b", - "const int lane2" + "svint32_t op1", + "svint32_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.4H" - }, - "lane1": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.S" } }, "Architectures": [ @@ -18919,36 +22449,31 @@ ], "instructions": [ [ - "INS" + "CADD" + ], + [ + "MOVPRFX", + "CADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_u32", + "SIMD_ISA": "SVE2", + "name": "svcadd[_s64]", "arguments": [ - "uint32x4_t a", - "const int lane1", - "uint32x2_t b", - "const int lane2" + "svint64_t op1", + "svint64_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint32x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.2S" - }, - "lane1": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.D" } }, "Architectures": [ @@ -18956,36 +22481,31 @@ ], "instructions": [ [ - "INS" + "CADD" + ], + [ + "MOVPRFX", + "CADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_u64", + "SIMD_ISA": "SVE2", + "name": "svcadd[_s8]", "arguments": [ - "uint64x2_t a", - "const int lane1", - "uint64x1_t b", - "const int lane2" + "svint8_t op1", + "svint8_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint64x2_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.1D" - }, - "lane1": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "lane2": { - "minimum": 0, - "maximum": 0 + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -18993,36 +22513,31 @@ ], "instructions": [ [ - "INS" + "CADD" + ], + [ + "MOVPRFX", + "CADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_u8", + "SIMD_ISA": "SVE2", + "name": "svcadd[_u16]", "arguments": [ - "uint8x16_t a", - "const int lane1", - "uint8x8_t b", - "const int lane2" + "svuint16_t op1", + "svuint16_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" - }, - "b": { - "register": "Vn.8B" - }, - "lane1": { - "minimum": 0, - "maximum": 15 + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "lane2": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -19030,36 +22545,31 @@ ], "instructions": [ [ - "INS" + "CADD" + ], + [ + "MOVPRFX", + "CADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_f32", + "SIMD_ISA": "SVE2", + "name": "svcadd[_u32]", "arguments": [ - "float32x4_t a", - "const int lane1", - "float32x4_t b", - "const int lane2" + "svuint32_t op1", + "svuint32_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "float32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4S" - }, - "lane1": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.S" } }, "Architectures": [ @@ -19067,36 +22577,31 @@ ], "instructions": [ [ - "INS" + "CADD" + ], + [ + "MOVPRFX", + "CADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_f64", + "SIMD_ISA": "SVE2", + "name": "svcadd[_u64]", "arguments": [ - "float64x2_t a", - "const int lane1", - "float64x2_t b", - "const int lane2" + "svuint64_t op1", + "svuint64_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "float64x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.2D" - }, - "lane1": { - "minimum": 0, - "maximum": 1 - }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.D" } }, "Architectures": [ @@ -19104,36 +22609,31 @@ ], "instructions": [ [ - "INS" + "CADD" + ], + [ + "MOVPRFX", + "CADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_p16", + "SIMD_ISA": "SVE2", + "name": "svcadd[_u8]", "arguments": [ - "poly16x8_t a", - "const int lane1", - "poly16x8_t b", - "const int lane2" + "svuint8_t op1", + "svuint8_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "poly16x8_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "lane1": { - "minimum": 0, - "maximum": 7 - }, - "lane2": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -19141,74 +22641,71 @@ ], "instructions": [ [ - "INS" + "CADD" + ], + [ + "MOVPRFX", + "CADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_p64", + "SIMD_ISA": "SVE2", + "name": "svcdot[_s32]", "arguments": [ - "poly64x2_t a", - "const int lane1", - "poly64x2_t b", - "const int lane2" + "svint32_t op1", + "svint8_t op2", + "svint8_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "poly64x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "lane1": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.B" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op3": { + "register": "Zop3.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "INS" + "CDOT" + ], + [ + "MOVPRFX", + "CDOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_p8", + "SIMD_ISA": "SVE2", + "name": "svcdot[_s64]", "arguments": [ - "poly8x16_t a", - "const int lane1", - "poly8x16_t b", - "const int lane2" + "svint64_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "poly8x16_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" - }, - "b": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "lane1": { - "minimum": 0, - "maximum": 15 + "op2": { + "register": "Zop2.H" }, - "lane2": { - "minimum": 0, - "maximum": 15 + "op3": { + "register": "Zop3.H" } }, "Architectures": [ @@ -19216,36 +22713,40 @@ ], "instructions": [ [ - "INS" + "CDOT" + ], + [ + "MOVPRFX", + "CDOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_s16", + "SIMD_ISA": "SVE2", + "name": "svcdot_lane[_s32]", "arguments": [ - "int16x8_t a", - "const int lane1", - "int16x8_t b", - "const int lane2" + "svint32_t op1", + "svint8_t op2", + "svint8_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" ], "return_type": { - "value": "int16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" + "imm_index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "lane1": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.B" }, - "lane2": { - "minimum": 0, - "maximum": 7 + "op3": { + "register": "Zop3.B" } }, "Architectures": [ @@ -19253,36 +22754,40 @@ ], "instructions": [ [ - "INS" + "CDOT" + ], + [ + "MOVPRFX", + "CDOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_s32", + "SIMD_ISA": "SVE2", + "name": "svcdot_lane[_s64]", "arguments": [ - "int32x4_t a", - "const int lane1", - "int32x4_t b", - "const int lane2" + "svint64_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" ], "return_type": { - "value": "int32x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" + "imm_index": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "lane1": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.H" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "op3": { + "register": "Zop3.H" } }, "Architectures": [ @@ -19290,36 +22795,34 @@ ], "instructions": [ [ - "INS" + "CDOT" + ], + [ + "MOVPRFX", + "CDOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_s64", + "SIMD_ISA": "SVE2", + "name": "svclamp[_f16]", "arguments": [ - "int64x2_t a", - "const int lane1", - "int64x2_t b", - "const int lane2" + "svfloat16_t op", + "svfloat16_t min", + "svfloat16_t max" ], "return_type": { - "value": "int64x2_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.2D" + "max": { + "register": "Zreg3.H" }, - "lane1": { - "minimum": 0, - "maximum": 1 + "min": { + "register": "Zreg2.H" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op": { + "register": "Zreg1.H" } }, "Architectures": [ @@ -19327,36 +22830,30 @@ ], "instructions": [ [ - "INS" + "FCLAMP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_s8", + "SIMD_ISA": "SVE2", + "name": "svclamp[_f32]", "arguments": [ - "int8x16_t a", - "const int lane1", - "int8x16_t b", - "const int lane2" + "svfloat32_t op", + "svfloat32_t min", + "svfloat32_t max" ], "return_type": { - "value": "int8x16_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "max": { + "register": "Zreg3.S" }, - "b": { - "register": "Vn.16B" - }, - "lane1": { - "minimum": 0, - "maximum": 15 + "min": { + "register": "Zreg2.S" }, - "lane2": { - "minimum": 0, - "maximum": 15 + "op": { + "register": "Zreg1.S" } }, "Architectures": [ @@ -19364,36 +22861,30 @@ ], "instructions": [ [ - "INS" + "FCLAMP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_u16", + "SIMD_ISA": "SVE2", + "name": "svclamp[_f64]", "arguments": [ - "uint16x8_t a", - "const int lane1", - "uint16x8_t b", - "const int lane2" + "svfloat64_t op", + "svfloat64_t min", + "svfloat64_t max" ], "return_type": { - "value": "uint16x8_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.8H" + "max": { + "register": "Zreg3.D" }, - "lane1": { - "minimum": 0, - "maximum": 7 + "min": { + "register": "Zreg2.D" }, - "lane2": { - "minimum": 0, - "maximum": 7 + "op": { + "register": "Zreg1.D" } }, "Architectures": [ @@ -19401,36 +22892,30 @@ ], "instructions": [ [ - "INS" + "FCLAMP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_u32", + "SIMD_ISA": "SVE2", + "name": "svclamp[_s16]", "arguments": [ - "uint32x4_t a", - "const int lane1", - "uint32x4_t b", - "const int lane2" + "svint16_t op", + "svint16_t min", + "svint16_t max" ], "return_type": { - "value": "uint32x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4S" + "max": { + "register": "Zreg3.H" }, - "lane1": { - "minimum": 0, - "maximum": 3 + "min": { + "register": "Zreg2.H" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "op": { + "register": "Zreg1.H" } }, "Architectures": [ @@ -19438,36 +22923,30 @@ ], "instructions": [ [ - "INS" + "SCLAMP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_u64", + "SIMD_ISA": "SVE2", + "name": "svclamp[_s32]", "arguments": [ - "uint64x2_t a", - "const int lane1", - "uint64x2_t b", - "const int lane2" + "svint32_t op", + "svint32_t min", + "svint32_t max" ], "return_type": { - "value": "uint64x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.2D" + "max": { + "register": "Zreg3.S" }, - "lane1": { - "minimum": 0, - "maximum": 1 + "min": { + "register": "Zreg2.S" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op": { + "register": "Zreg1.S" } }, "Architectures": [ @@ -19475,36 +22954,30 @@ ], "instructions": [ [ - "INS" + "SCLAMP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_u8", + "SIMD_ISA": "SVE2", + "name": "svclamp[_s64]", "arguments": [ - "uint8x16_t a", - "const int lane1", - "uint8x16_t b", - "const int lane2" + "svint64_t op", + "svint64_t min", + "svint64_t max" ], "return_type": { - "value": "uint8x16_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "max": { + "register": "Zreg3.D" }, - "b": { - "register": "Vn.16B" - }, - "lane1": { - "minimum": 0, - "maximum": 15 + "min": { + "register": "Zreg2.D" }, - "lane2": { - "minimum": 0, - "maximum": 15 + "op": { + "register": "Zreg1.D" } }, "Architectures": [ @@ -19512,72 +22985,92 @@ ], "instructions": [ [ - "INS" + "SCLAMP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_f16", + "SIMD_ISA": "SVE2", + "name": "svclamp[_s8]", "arguments": [ - "uint64_t a" + "svint8_t op", + "svint8_t min", + "svint8_t max" ], "return_type": { - "value": "float16x4_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "max": { + "register": "Zreg3.B" + }, + "min": { + "register": "Zreg2.B" + }, + "op": { + "register": "Zreg1.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "SCLAMP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_f32", + "SIMD_ISA": "SVE2", + "name": "svclamp[_u16]", "arguments": [ - "uint64_t a" + "svuint16_t op", + "svuint16_t min", + "svuint16_t max" ], "return_type": { - "value": "float32x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "max": { + "register": "Zreg3.H" + }, + "min": { + "register": "Zreg2.H" + }, + "op": { + "register": "Zreg1.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "UCLAMP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_f64", + "SIMD_ISA": "SVE2", + "name": "svclamp[_u32]", "arguments": [ - "uint64_t a" + "svuint32_t op", + "svuint32_t min", + "svuint32_t max" ], "return_type": { - "value": "float64x1_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "max": { + "register": "Zreg3.S" + }, + "min": { + "register": "Zreg2.S" + }, + "op": { + "register": "Zreg1.S" } }, "Architectures": [ @@ -19585,394 +23078,537 @@ ], "instructions": [ [ - "INS" + "UCLAMP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_p16", + "SIMD_ISA": "SVE2", + "name": "svclamp[_u64]", "arguments": [ - "uint64_t a" + "svuint64_t op", + "svuint64_t min", + "svuint64_t max" ], "return_type": { - "value": "poly16x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "max": { + "register": "Zreg3.D" + }, + "min": { + "register": "Zreg2.D" + }, + "op": { + "register": "Zreg1.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "UCLAMP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_p64", + "SIMD_ISA": "SVE2", + "name": "svclamp[_u8]", "arguments": [ - "uint64_t a" + "svuint8_t op", + "svuint8_t min", + "svuint8_t max" ], "return_type": { - "value": "poly64x1_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "max": { + "register": "Zreg3.B" + }, + "min": { + "register": "Zreg2.B" + }, + "op": { + "register": "Zreg1.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "INS" + "UCLAMP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_p8", + "SIMD_ISA": "SVE", + "name": "svclasta[_f16]", "arguments": [ - "uint64_t a" + "svbool_t pg", + "svfloat16_t fallback", + "svfloat16_t data" ], "return_type": { - "value": "poly8x8_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Zfallback.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_s16", + "SIMD_ISA": "SVE", + "name": "svclasta[_f32]", "arguments": [ - "uint64_t a" + "svbool_t pg", + "svfloat32_t fallback", + "svfloat32_t data" ], "return_type": { - "value": "int16x4_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Zfallback.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_s32", + "SIMD_ISA": "SVE", + "name": "svclasta[_f64]", "arguments": [ - "uint64_t a" + "svbool_t pg", + "svfloat64_t fallback", + "svfloat64_t data" ], "return_type": { - "value": "int32x2_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Zfallback.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_s64", + "SIMD_ISA": "SVE", + "name": "svclasta[_n_f16]", "arguments": [ - "uint64_t a" + "svbool_t pg", + "float16_t fallback", + "svfloat16_t data" ], "return_type": { - "value": "int64x1_t" + "value": "float16_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Htied|Wtied" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "CLASTA" + ], + [ + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_s8", + "SIMD_ISA": "SVE", + "name": "svclasta[_n_f32]", "arguments": [ - "uint64_t a" + "svbool_t pg", + "float32_t fallback", + "svfloat32_t data" ], "return_type": { - "value": "int8x8_t" + "value": "float32_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Stied|Wtied" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "CLASTA" + ], + [ + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_u16", + "SIMD_ISA": "SVE", + "name": "svclasta[_n_f64]", "arguments": [ - "uint64_t a" + "svbool_t pg", + "float64_t fallback", + "svfloat64_t data" ], "return_type": { - "value": "uint16x4_t" + "value": "float64_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Dtied|Xtied" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "CLASTA" + ], + [ + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_u32", + "SIMD_ISA": "SVE", + "name": "svclasta[_n_s16]", "arguments": [ - "uint64_t a" + "svbool_t pg", + "int16_t fallback", + "svint16_t data" ], "return_type": { - "value": "uint32x2_t" + "value": "int16_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Htied|Wtied" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "CLASTA" + ], + [ + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_u64", + "SIMD_ISA": "SVE", + "name": "svclasta[_n_s32]", "arguments": [ - "uint64_t a" + "svbool_t pg", + "int32_t fallback", + "svint32_t data" ], "return_type": { - "value": "uint64x1_t" + "value": "int32_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Stied|Wtied" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "CLASTA" + ], + [ + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_u8", + "SIMD_ISA": "SVE", + "name": "svclasta[_n_s64]", "arguments": [ - "uint64_t a" + "svbool_t pg", + "int64_t fallback", + "svint64_t data" ], "return_type": { - "value": "uint8x8_t" + "value": "int64_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Dtied|Xtied" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "CLASTA" + ], + [ + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_f16_f32", + "SIMD_ISA": "SVE", + "name": "svclasta[_n_s8]", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "int8_t fallback", + "svint8_t data" ], "return_type": { - "value": "float16x4_t" + "value": "int8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "data": { + "register": "Zdata.B" + }, + "fallback": { + "register": "Btied|Wtied" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCVTN" + "CLASTA" + ], + [ + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_f16_s16", + "SIMD_ISA": "SVE", + "name": "svclasta[_n_u16]", "arguments": [ - "int16x4_t a" + "svbool_t pg", + "uint16_t fallback", + "svuint16_t data" ], "return_type": { - "value": "float16x4_t" + "value": "uint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Htied|Wtied" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SCVTF" + "CLASTA" + ], + [ + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_f16_u16", + "SIMD_ISA": "SVE", + "name": "svclasta[_n_u32]", "arguments": [ - "uint16x4_t a" + "svbool_t pg", + "uint32_t fallback", + "svuint32_t data" ], "return_type": { - "value": "float16x4_t" + "value": "uint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Stied|Wtied" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "UCVTF" + "CLASTA" + ], + [ + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_f32_f16", + "SIMD_ISA": "SVE", + "name": "svclasta[_n_u64]", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "uint64_t fallback", + "svuint64_t data" ], "return_type": { - "value": "float32x4_t" + "value": "uint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Dtied|Xtied" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCVTL" + "CLASTA" + ], + [ + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_f32_f64", + "SIMD_ISA": "SVE", + "name": "svclasta[_n_u8]", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "uint8_t fallback", + "svuint8_t data" ], "return_type": { - "value": "float32x2_t" + "value": "uint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "data": { + "register": "Zdata.B" + }, + "fallback": { + "register": "Btied|Wtied" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -19980,72 +23616,103 @@ ], "instructions": [ [ - "FCVTN" + "CLASTA" + ], + [ + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_f32_s32", + "SIMD_ISA": "SVE", + "name": "svclasta[_s16]", "arguments": [ - "int32x2_t a" + "svbool_t pg", + "svint16_t fallback", + "svint16_t data" ], "return_type": { - "value": "float32x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Zfallback.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SCVTF" + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_f32_u32", + "SIMD_ISA": "SVE", + "name": "svclasta[_s32]", "arguments": [ - "uint32x2_t a" + "svbool_t pg", + "svint32_t fallback", + "svint32_t data" ], "return_type": { - "value": "float32x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Zfallback.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UCVTF" + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_f64_f32", + "SIMD_ISA": "SVE", + "name": "svclasta[_s64]", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svint64_t fallback", + "svint64_t data" ], "return_type": { - "value": "float64x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Zfallback.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -20053,22 +23720,34 @@ ], "instructions": [ [ - "FCVTL" + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_f64_s64", + "SIMD_ISA": "SVE", + "name": "svclasta[_s8]", "arguments": [ - "int64x1_t a" + "svbool_t pg", + "svint8_t fallback", + "svint8_t data" ], "return_type": { - "value": "float64x1_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "data": { + "register": "Zdata.B" + }, + "fallback": { + "register": "Zfallback.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -20076,22 +23755,34 @@ ], "instructions": [ [ - "SCVTF" + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_f64_u64", + "SIMD_ISA": "SVE", + "name": "svclasta[_u16]", "arguments": [ - "uint64x1_t a" + "svbool_t pg", + "svuint16_t fallback", + "svuint16_t data" ], "return_type": { - "value": "float64x1_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Zfallback.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -20099,26 +23790,34 @@ ], "instructions": [ [ - "UCVTF" + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_high_f16_f32", + "SIMD_ISA": "SVE", + "name": "svclasta[_u32]", "arguments": [ - "float16x4_t r", - "float32x4_t a" + "svbool_t pg", + "svuint32_t fallback", + "svuint32_t data" ], "return_type": { - "value": "float16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "data": { + "register": "Zdata.S" }, - "r": { - "register": "Vd.4H" + "fallback": { + "register": "Zfallback.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -20126,22 +23825,34 @@ ], "instructions": [ [ - "FCVTN2" + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_high_f32_f16", + "SIMD_ISA": "SVE", + "name": "svclasta[_u64]", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svuint64_t fallback", + "svuint64_t data" ], "return_type": { - "value": "float32x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Zfallback.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -20149,26 +23860,34 @@ ], "instructions": [ [ - "FCVTL2" + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_high_f32_f64", + "SIMD_ISA": "SVE", + "name": "svclasta[_u8]", "arguments": [ - "float32x2_t r", - "float64x2_t a" + "svbool_t pg", + "svuint8_t fallback", + "svuint8_t data" ], "return_type": { - "value": "float32x4_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "data": { + "register": "Zdata.B" }, - "r": { - "register": "Vd.2S" + "fallback": { + "register": "Zfallback.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -20176,22 +23895,34 @@ ], "instructions": [ [ - "FCVTN2" + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_high_f64_f32", + "SIMD_ISA": "SVE", + "name": "svclastb[_f16]", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svfloat16_t fallback", + "svfloat16_t data" ], "return_type": { - "value": "float64x2_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Zfallback.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -20199,145 +23930,172 @@ ], "instructions": [ [ - "FCVTL2" + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_f16_s16", + "SIMD_ISA": "SVE", + "name": "svclastb[_f32]", "arguments": [ - "int16x4_t a", - "const int n" + "svbool_t pg", + "svfloat32_t fallback", + "svfloat32_t data" ], "return_type": { - "value": "float16x4_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "data": { + "register": "Zdata.S" }, - "n": { - "minimum": 1, - "maximum": 16 + "fallback": { + "register": "Zfallback.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SCVTF" + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_f16_u16", + "SIMD_ISA": "SVE", + "name": "svclastb[_f64]", "arguments": [ - "uint16x4_t a", - "const int n" + "svbool_t pg", + "svfloat64_t fallback", + "svfloat64_t data" ], "return_type": { - "value": "float16x4_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "data": { + "register": "Zdata.D" }, - "n": { - "minimum": 1, - "maximum": 16 + "fallback": { + "register": "Zfallback.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "UCVTF" + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_f32_s32", + "SIMD_ISA": "SVE", + "name": "svclastb[_n_f16]", "arguments": [ - "int32x2_t a", - "const int n" + "svbool_t pg", + "float16_t fallback", + "svfloat16_t data" ], "return_type": { - "value": "float32x2_t" + "value": "float16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "data": { + "register": "Zdata.H" }, - "n": { - "minimum": 1, - "maximum": 32 + "fallback": { + "register": "Htied|Wtied" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SCVTF" + "CLASTB" + ], + [ + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_f32_u32", + "SIMD_ISA": "SVE", + "name": "svclastb[_n_f32]", "arguments": [ - "uint32x2_t a", - "const int n" + "svbool_t pg", + "float32_t fallback", + "svfloat32_t data" ], "return_type": { - "value": "float32x2_t" + "value": "float32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "data": { + "register": "Zdata.S" }, - "n": { - "minimum": 1, - "maximum": 32 + "fallback": { + "register": "Stied|Wtied" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UCVTF" + "CLASTB" + ], + [ + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_f64_s64", + "SIMD_ISA": "SVE", + "name": "svclastb[_n_f64]", "arguments": [ - "int64x1_t a", - "const int n" + "svbool_t pg", + "float64_t fallback", + "svfloat64_t data" ], "return_type": { - "value": "float64x1_t" + "value": "float64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "data": { + "register": "Zdata.D" }, - "n": { - "minimum": 1, - "maximum": 64 + "fallback": { + "register": "Dtied|Xtied" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -20345,27 +24103,33 @@ ], "instructions": [ [ - "SCVTF" + "CLASTB" + ], + [ + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_f64_u64", + "SIMD_ISA": "SVE", + "name": "svclastb[_n_s16]", "arguments": [ - "uint64x1_t a", - "const int n" + "svbool_t pg", + "int16_t fallback", + "svint16_t data" ], "return_type": { - "value": "float64x1_t" + "value": "int16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "data": { + "register": "Zdata.H" }, - "n": { - "minimum": 1, - "maximum": 64 + "fallback": { + "register": "Htied|Wtied" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -20373,86 +24137,101 @@ ], "instructions": [ [ - "UCVTF" + "CLASTB" + ], + [ + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_s16_f16", + "SIMD_ISA": "SVE", + "name": "svclastb[_n_s32]", "arguments": [ - "float16x4_t a", - "const int n" + "svbool_t pg", + "int32_t fallback", + "svint32_t data" ], "return_type": { - "value": "int16x4_t" + "value": "int32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "data": { + "register": "Zdata.S" }, - "n": { - "minimum": 1, - "maximum": 16 + "fallback": { + "register": "Stied|Wtied" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "CLASTB" + ], + [ + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_s32_f32", + "SIMD_ISA": "SVE", + "name": "svclastb[_n_s64]", "arguments": [ - "float32x2_t a", - "const int n" + "svbool_t pg", + "int64_t fallback", + "svint64_t data" ], "return_type": { - "value": "int32x2_t" + "value": "int64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "data": { + "register": "Zdata.D" }, - "n": { - "minimum": 1, - "maximum": 32 + "fallback": { + "register": "Dtied|Xtied" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "CLASTB" + ], + [ + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_s64_f64", + "SIMD_ISA": "SVE", + "name": "svclastb[_n_s8]", "arguments": [ - "float64x1_t a", - "const int n" + "svbool_t pg", + "int8_t fallback", + "svint8_t data" ], "return_type": { - "value": "int64x1_t" + "value": "int8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "data": { + "register": "Zdata.B" }, - "n": { - "minimum": 1, - "maximum": 64 + "fallback": { + "register": "Btied|Wtied" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -20460,86 +24239,101 @@ ], "instructions": [ [ - "FCVTZS" + "CLASTB" + ], + [ + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_u16_f16", + "SIMD_ISA": "SVE", + "name": "svclastb[_n_u16]", "arguments": [ - "float16x4_t a", - "const int n" + "svbool_t pg", + "uint16_t fallback", + "svuint16_t data" ], "return_type": { - "value": "uint16x4_t" + "value": "uint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "data": { + "register": "Zdata.H" }, - "n": { - "minimum": 1, - "maximum": 16 + "fallback": { + "register": "Htied|Wtied" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZU" + "CLASTB" + ], + [ + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_u32_f32", + "SIMD_ISA": "SVE", + "name": "svclastb[_n_u32]", "arguments": [ - "float32x2_t a", - "const int n" + "svbool_t pg", + "uint32_t fallback", + "svuint32_t data" ], "return_type": { - "value": "uint32x2_t" + "value": "uint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "data": { + "register": "Zdata.S" }, - "n": { - "minimum": 1, - "maximum": 32 + "fallback": { + "register": "Stied|Wtied" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCVTZU" + "CLASTB" + ], + [ + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_u64_f64", + "SIMD_ISA": "SVE", + "name": "svclastb[_n_u64]", "arguments": [ - "float64x1_t a", - "const int n" + "svbool_t pg", + "uint64_t fallback", + "svuint64_t data" ], "return_type": { - "value": "uint64x1_t" + "value": "uint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "data": { + "register": "Zdata.D" }, - "n": { - "minimum": 1, - "maximum": 64 + "fallback": { + "register": "Dtied|Xtied" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -20547,71 +24341,102 @@ ], "instructions": [ [ - "FCVTZU" + "CLASTB" + ], + [ + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_s16_f16", + "SIMD_ISA": "SVE", + "name": "svclastb[_n_u8]", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "uint8_t fallback", + "svuint8_t data" ], "return_type": { - "value": "int16x4_t" + "value": "uint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "data": { + "register": "Zdata.B" + }, + "fallback": { + "register": "Btied|Wtied" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "CLASTB" + ], + [ + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_s32_f32", + "SIMD_ISA": "SVE", + "name": "svclastb[_s16]", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svint16_t fallback", + "svint16_t data" ], "return_type": { - "value": "int32x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Zfallback.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_s64_f64", + "SIMD_ISA": "SVE", + "name": "svclastb[_s32]", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svint32_t fallback", + "svint32_t data" ], "return_type": { - "value": "int64x1_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Zfallback.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -20619,71 +24444,104 @@ ], "instructions": [ [ - "FCVTZS" + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_u16_f16", + "SIMD_ISA": "SVE", + "name": "svclastb[_s64]", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "svint64_t fallback", + "svint64_t data" ], "return_type": { - "value": "uint16x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Zfallback.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_u32_f32", + "SIMD_ISA": "SVE", + "name": "svclastb[_s8]", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svint8_t fallback", + "svint8_t data" ], "return_type": { - "value": "uint32x2_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "data": { + "register": "Zdata.B" + }, + "fallback": { + "register": "Zfallback.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCVTZU" + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_u64_f64", + "SIMD_ISA": "SVE", + "name": "svclastb[_u16]", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svuint16_t fallback", + "svuint16_t data" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Zfallback.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -20691,70 +24549,104 @@ ], "instructions": [ [ - "FCVTZU" + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvta_s16_f16", + "SIMD_ISA": "SVE", + "name": "svclastb[_u32]", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "svuint32_t fallback", + "svuint32_t data" ], "return_type": { - "value": "int16x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Zfallback.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTAS" + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvta_s32_f32", + "SIMD_ISA": "SVE", + "name": "svclastb[_u64]", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svuint64_t fallback", + "svuint64_t data" ], "return_type": { - "value": "int32x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Zfallback.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTAS" + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvta_s64_f64", + "SIMD_ISA": "SVE", + "name": "svclastb[_u8]", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svuint8_t fallback", + "svuint8_t data" ], "return_type": { - "value": "int64x1_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "data": { + "register": "Zdata.B" + }, + "fallback": { + "register": "Zfallback.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -20762,70 +24654,96 @@ ], "instructions": [ [ - "FCVTAS" + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvta_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcls[_s16]_m", "arguments": [ - "float16x4_t a" + "svuint16_t inactive", + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTAU" + "CLS" + ], + [ + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvta_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcls[_s16]_x", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTAU" + "CLS" + ], + [ + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvta_u64_f64", + "SIMD_ISA": "SVE", + "name": "svcls[_s16]_z", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -20833,22 +24751,31 @@ ], "instructions": [ [ - "FCVTAU" + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtad_s64_f64", + "SIMD_ISA": "SVE", + "name": "svcls[_s32]_m", "arguments": [ - "float64_t a" + "svuint32_t inactive", + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "int64_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -20856,22 +24783,30 @@ ], "instructions": [ [ - "FCVTAS" + "CLS" + ], + [ + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtad_u64_f64", + "SIMD_ISA": "SVE", + "name": "svcls[_s32]_x", "arguments": [ - "float64_t a" + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "uint64_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -20879,22 +24814,30 @@ ], "instructions": [ [ - "FCVTAU" + "CLS" + ], + [ + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtah_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcls[_s32]_z", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "int16_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -20902,46 +24845,62 @@ ], "instructions": [ [ - "FCVTAS" + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtah_s32_f16", + "SIMD_ISA": "SVE", + "name": "svcls[_s64]_m", "arguments": [ - "float16_t a" + "svuint64_t inactive", + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "int32_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTAS" + "CLS" + ], + [ + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtah_s64_f16", + "SIMD_ISA": "SVE", + "name": "svcls[_s64]_x", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "int64_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -20949,22 +24908,30 @@ ], "instructions": [ [ - "FCVTAS" + "CLS" + ], + [ + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtah_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcls[_s64]_z", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "uint16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -20972,46 +24939,62 @@ ], "instructions": [ [ - "FCVTAU" + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtah_u32_f16", + "SIMD_ISA": "SVE", + "name": "svcls[_s8]_m", "arguments": [ - "float16_t a" + "svuint8_t inactive", + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "uint32_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "inactive": { + "register": "Zinactive.B|Ztied.B" + }, + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTAU" + "CLS" + ], + [ + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtah_u64_f16", + "SIMD_ISA": "SVE", + "name": "svcls[_s8]_x", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "uint64_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op": { + "register": "Zop.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -21019,70 +25002,93 @@ ], "instructions": [ [ - "FCVTAU" + "CLS" + ], + [ + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtaq_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcls[_s8]_z", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "int16x8_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTAS" + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtaq_s32_f32", + "SIMD_ISA": "SVE", + "name": "svclz[_s16]_m", "arguments": [ - "float32x4_t a" + "svuint16_t inactive", + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "int32x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTAS" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtaq_s64_f64", + "SIMD_ISA": "SVE", + "name": "svclz[_s16]_x", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "int64x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -21090,70 +25096,93 @@ ], "instructions": [ [ - "FCVTAS" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtaq_u16_f16", + "SIMD_ISA": "SVE", + "name": "svclz[_s16]_z", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTAU" + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtaq_u32_f32", + "SIMD_ISA": "SVE", + "name": "svclz[_s32]_m", "arguments": [ - "float32x4_t a" + "svuint32_t inactive", + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTAU" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtaq_u64_f64", + "SIMD_ISA": "SVE", + "name": "svclz[_s32]_x", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -21161,22 +25190,30 @@ ], "instructions": [ [ - "FCVTAU" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtas_s32_f32", + "SIMD_ISA": "SVE", + "name": "svclz[_s32]_z", "arguments": [ - "float32_t a" + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "int32_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -21184,22 +25221,31 @@ ], "instructions": [ [ - "FCVTAS" + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtas_u32_f32", + "SIMD_ISA": "SVE", + "name": "svclz[_s64]_m", "arguments": [ - "float32_t a" + "svuint64_t inactive", + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "uint32_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -21207,22 +25253,30 @@ ], "instructions": [ [ - "FCVTAU" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtd_f64_s64", + "SIMD_ISA": "SVE", + "name": "svclz[_s64]_x", "arguments": [ - "int64_t a" + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "float64_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -21230,22 +25284,30 @@ ], "instructions": [ [ - "SCVTF" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtd_f64_u64", + "SIMD_ISA": "SVE", + "name": "svclz[_s64]_z", "arguments": [ - "uint64_t a" + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "float64_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -21253,27 +25315,31 @@ ], "instructions": [ [ - "UCVTF" + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtd_n_f64_s64", + "SIMD_ISA": "SVE", + "name": "svclz[_s8]_m", "arguments": [ - "int64_t a", - "const int n" + "svuint8_t inactive", + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "float64_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "inactive": { + "register": "Zinactive.B|Ztied.B" }, - "n": { - "minimum": 1, - "maximum": 64 + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -21281,27 +25347,30 @@ ], "instructions": [ [ - "SCVTF" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtd_n_f64_u64", + "SIMD_ISA": "SVE", + "name": "svclz[_s8]_x", "arguments": [ - "uint64_t a", - "const int n" + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "float64_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.B|Ztied.B" }, - "n": { - "minimum": 1, - "maximum": 64 + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -21309,27 +25378,30 @@ ], "instructions": [ [ - "UCVTF" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtd_n_s64_f64", + "SIMD_ISA": "SVE", + "name": "svclz[_s8]_z", "arguments": [ - "float64_t a", - "const int n" + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "int64_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.B" }, - "n": { - "minimum": 1, - "maximum": 64 + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -21337,27 +25409,31 @@ ], "instructions": [ [ - "FCVTZS" + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtd_n_u64_f64", + "SIMD_ISA": "SVE", + "name": "svclz[_u16]_m", "arguments": [ - "float64_t a", - "const int n" + "svuint16_t inactive", + "svbool_t pg", + "svuint16_t op" ], "return_type": { - "value": "uint64_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "inactive": { + "register": "Zinactive.H|Ztied.H" }, - "n": { - "minimum": 1, - "maximum": 64 + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -21365,22 +25441,30 @@ ], "instructions": [ [ - "FCVTZU" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtd_s64_f64", + "SIMD_ISA": "SVE", + "name": "svclz[_u16]_x", "arguments": [ - "float64_t a" + "svbool_t pg", + "svuint16_t op" ], "return_type": { - "value": "int64_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -21388,22 +25472,30 @@ ], "instructions": [ [ - "FCVTZS" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtd_u64_f64", + "SIMD_ISA": "SVE", + "name": "svclz[_u16]_z", "arguments": [ - "float64_t a" + "svbool_t pg", + "svuint16_t op" ], "return_type": { - "value": "uint64_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -21411,22 +25503,31 @@ ], "instructions": [ [ - "FCVTZU" + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_f16_s16", + "SIMD_ISA": "SVE", + "name": "svclz[_u32]_m", "arguments": [ - "int16_t a" + "svuint32_t inactive", + "svbool_t pg", + "svuint32_t op" ], "return_type": { - "value": "float16_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -21434,46 +25535,61 @@ ], "instructions": [ [ - "SCVTF" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_f16_s32", + "SIMD_ISA": "SVE", + "name": "svclz[_u32]_x", "arguments": [ - "int32_t a" + "svbool_t pg", + "svuint32_t op" ], "return_type": { - "value": "float16_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SCVTF" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_f16_s64", + "SIMD_ISA": "SVE", + "name": "svclz[_u32]_z", "arguments": [ - "int64_t a" + "svbool_t pg", + "svuint32_t op" ], "return_type": { - "value": "float16_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -21481,22 +25597,31 @@ ], "instructions": [ [ - "SCVTF" + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_f16_u16", + "SIMD_ISA": "SVE", + "name": "svclz[_u64]_m", "arguments": [ - "uint16_t a" + "svuint64_t inactive", + "svbool_t pg", + "svuint64_t op" ], "return_type": { - "value": "float16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -21504,46 +25629,61 @@ ], "instructions": [ [ - "UCVTF" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_f16_u32", + "SIMD_ISA": "SVE", + "name": "svclz[_u64]_x", "arguments": [ - "uint32_t a" + "svbool_t pg", + "svuint64_t op" ], "return_type": { - "value": "float16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "UCVTF" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_f16_u64", + "SIMD_ISA": "SVE", + "name": "svclz[_u64]_z", "arguments": [ - "uint64_t a" + "svbool_t pg", + "svuint64_t op" ], "return_type": { - "value": "float16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -21551,27 +25691,31 @@ ], "instructions": [ [ - "UCVTF" + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_f16_s16", + "SIMD_ISA": "SVE", + "name": "svclz[_u8]_m", "arguments": [ - "int16_t a", - "const int n" + "svuint8_t inactive", + "svbool_t pg", + "svuint8_t op" ], "return_type": { - "value": "float16_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "inactive": { + "register": "Zinactive.B|Ztied.B" }, - "n": { - "minimum": 1, - "maximum": 16 + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -21579,56 +25723,61 @@ ], "instructions": [ [ - "SCVTF" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_f16_s32", + "SIMD_ISA": "SVE", + "name": "svclz[_u8]_x", "arguments": [ - "int32_t a", - "const int n" + "svbool_t pg", + "svuint8_t op" ], "return_type": { - "value": "float16_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op": { + "register": "Zop.B|Ztied.B" }, - "n": { - "minimum": 1, - "maximum": 16 + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SCVTF" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_f16_s64", + "SIMD_ISA": "SVE", + "name": "svclz[_u8]_z", "arguments": [ - "int64_t a", - "const int n" + "svbool_t pg", + "svuint8_t op" ], "return_type": { - "value": "float16_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op": { + "register": "Zop.B" }, - "n": { - "minimum": 1, - "maximum": 16 + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -21636,27 +25785,36 @@ ], "instructions": [ [ - "SCVTF" + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_f16_u16", + "SIMD_ISA": "SVE", + "name": "svcmla[_f16]_m", "arguments": [ - "uint16_t a", - "const int n" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "float16_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -21664,56 +25822,79 @@ ], "instructions": [ [ - "UCVTF" + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_f16_u32", + "SIMD_ISA": "SVE", + "name": "svcmla[_f16]_x", "arguments": [ - "uint32_t a", - "const int n" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "float16_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "UCVTF" + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_f16_u64", + "SIMD_ISA": "SVE", + "name": "svcmla[_f16]_z", "arguments": [ - "uint64_t a", - "const int n" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "float16_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -21721,27 +25902,36 @@ ], "instructions": [ [ - "UCVTF" + "MOVPRFX", + "FCMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcmla[_f32]_m", "arguments": [ - "float16_t a", - "const int n" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "int16_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -21749,56 +25939,79 @@ ], "instructions": [ [ - "FCVTZS" + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_s32_f16", + "SIMD_ISA": "SVE", + "name": "svcmla[_f32]_x", "arguments": [ - "float16_t a", - "const int n" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "int32_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_s64_f16", + "SIMD_ISA": "SVE", + "name": "svcmla[_f32]_z", "arguments": [ - "float16_t a", - "const int n" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "int64_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.S" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -21806,27 +26019,36 @@ ], "instructions": [ [ - "FCVTZS" + "MOVPRFX", + "FCMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmla[_f64]_m", "arguments": [ - "float16_t a", - "const int n" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint16_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -21834,56 +26056,79 @@ ], "instructions": [ [ - "FCVTZU" + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_u32_f16", + "SIMD_ISA": "SVE", + "name": "svcmla[_f64]_x", "arguments": [ - "float16_t a", - "const int n" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint32_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZU" + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_u64_f16", + "SIMD_ISA": "SVE", + "name": "svcmla[_f64]_z", "arguments": [ - "float16_t a", - "const int n" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint64_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.D" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -21891,22 +26136,32 @@ ], "instructions": [ [ - "FCVTZU" + "MOVPRFX", + "FCMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_s16_f16", + "SIMD_ISA": "SVE2", + "name": "svcmla[_s16]", "arguments": [ - "float16_t a" + "svint16_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "int16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" } }, "Architectures": [ @@ -21914,46 +26169,71 @@ ], "instructions": [ [ - "FCVTZS" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_s32_f16", + "SIMD_ISA": "SVE2", + "name": "svcmla[_s32]", "arguments": [ - "float16_t a" + "svint32_t op1", + "svint32_t op2", + "svint32_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "int32_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_s64_f16", + "SIMD_ISA": "SVE2", + "name": "svcmla[_s64]", "arguments": [ - "float16_t a" + "svint64_t op1", + "svint64_t op2", + "svint64_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "int64_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" } }, "Architectures": [ @@ -21961,22 +26241,35 @@ ], "instructions": [ [ - "FCVTZS" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_u16_f16", + "SIMD_ISA": "SVE2", + "name": "svcmla[_s8]", "arguments": [ - "float16_t a" + "svint8_t op1", + "svint8_t op2", + "svint8_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint16_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" } }, "Architectures": [ @@ -21984,46 +26277,71 @@ ], "instructions": [ [ - "FCVTZU" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_u32_f16", + "SIMD_ISA": "SVE2", + "name": "svcmla[_u16]", "arguments": [ - "float16_t a" + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint32_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZU" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_u64_f16", + "SIMD_ISA": "SVE2", + "name": "svcmla[_u32]", "arguments": [ - "float16_t a" + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint64_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" } }, "Architectures": [ @@ -22031,70 +26349,112 @@ ], "instructions": [ [ - "FCVTZU" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtm_s16_f16", + "SIMD_ISA": "SVE2", + "name": "svcmla[_u64]", "arguments": [ - "float16x4_t a" + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "int16x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTMS" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtm_s32_f32", + "SIMD_ISA": "SVE2", + "name": "svcmla[_u8]", "arguments": [ - "float32x2_t a" + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "int32x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTMS" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtm_s64_f64", + "SIMD_ISA": "SVE", + "name": "svcmla_lane[_f16]", "arguments": [ - "float64x1_t a" + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" ], "return_type": { - "value": "int64x1_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" } }, "Architectures": [ @@ -22102,70 +26462,122 @@ ], "instructions": [ [ - "FCVTMS" + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtm_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmla_lane[_f32]", "arguments": [ - "float16x4_t a" + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint16x4_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTMU" + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtm_u32_f32", + "SIMD_ISA": "SVE2", + "name": "svcmla_lane[_s16]", "arguments": [ - "float32x2_t a" + "svint16_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint32x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTMU" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtm_u64_f64", + "SIMD_ISA": "SVE2", + "name": "svcmla_lane[_s32]", "arguments": [ - "float64x1_t a" + "svint32_t op1", + "svint32_t op2", + "svint32_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint64x1_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" } }, "Architectures": [ @@ -22173,22 +26585,40 @@ ], "instructions": [ [ - "FCVTMU" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmd_s64_f64", + "SIMD_ISA": "SVE2", + "name": "svcmla_lane[_u16]", "arguments": [ - "float64_t a" + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" ], "return_type": { - "value": "int64_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" } }, "Architectures": [ @@ -22196,22 +26626,40 @@ ], "instructions": [ [ - "FCVTMS" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmd_u64_f64", + "SIMD_ISA": "SVE2", + "name": "svcmla_lane[_u32]", "arguments": [ - "float64_t a" + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint64_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" } }, "Architectures": [ @@ -22219,22 +26667,34 @@ ], "instructions": [ [ - "FCVTMU" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmh_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_f16]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "int16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -22242,46 +26702,61 @@ ], "instructions": [ [ - "FCVTMS" + "FCMEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmh_s32_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_f32]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "int32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTMS" + "FCMEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmh_s64_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_f64]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "int64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -22289,22 +26764,30 @@ ], "instructions": [ [ - "FCVTMS" + "FCMEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmh_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_f16]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -22312,46 +26795,67 @@ ], "instructions": [ [ - "FCVTMU" + "FCMEQ" + ], + [ + "FCMEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmh_u32_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_f32]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTMU" + "FCMEQ" + ], + [ + "FCMEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmh_u64_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_f64]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -22359,70 +26863,101 @@ ], "instructions": [ [ - "FCVTMU" + "FCMEQ" + ], + [ + "FCMEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmq_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_s16]", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTMS" + "CMPEQ" + ], + [ + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmq_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_s32]", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTMS" + "CMPEQ" + ], + [ + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmq_s64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_s64]", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -22430,70 +26965,101 @@ ], "instructions": [ [ - "FCVTMS" + "CMPEQ" + ], + [ + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmq_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_s8]", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTMU" + "CMPEQ" + ], + [ + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmq_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_u16]", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTMU" + "CMPEQ" + ], + [ + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmq_u64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_u32]", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -22501,22 +27067,33 @@ ], "instructions": [ [ - "FCVTMU" + "CMPEQ" + ], + [ + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtms_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_u64]", "arguments": [ - "float32_t a" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "int32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -22524,22 +27101,33 @@ ], "instructions": [ [ - "FCVTMS" + "CMPEQ" + ], + [ + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtms_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_u8]", "arguments": [ - "float32_t a" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -22547,70 +27135,95 @@ ], "instructions": [ [ - "FCVTMU" + "CMPEQ" + ], + [ + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtn_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_s16]", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTNS" + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtn_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_s32]", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTNS" + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtn_s64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_s64]", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "int64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -22618,70 +27231,92 @@ ], "instructions": [ [ - "FCVTNS" + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtn_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_s8]", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTNU" + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtn_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_u16]", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTNU" + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtn_u64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_u32]", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -22689,22 +27324,30 @@ ], "instructions": [ [ - "FCVTNU" + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnd_s64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_u64]", "arguments": [ - "float64_t a" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -22712,22 +27355,30 @@ ], "instructions": [ [ - "FCVTNS" + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnd_u64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_u8]", "arguments": [ - "float64_t a" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -22735,22 +27386,30 @@ ], "instructions": [ [ - "FCVTNU" + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnh_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq_wide[_n_s16]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint16_t op1", + "int64_t op2" ], "return_type": { - "value": "int16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -22758,46 +27417,67 @@ ], "instructions": [ [ - "FCVTNS" + "CMPEQ" + ], + [ + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnh_s32_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq_wide[_n_s32]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint32_t op1", + "int64_t op2" ], "return_type": { - "value": "int32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTNS" + "CMPEQ" + ], + [ + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnh_s64_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq_wide[_n_s8]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint8_t op1", + "int64_t op2" ], "return_type": { - "value": "int64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -22805,22 +27485,33 @@ ], "instructions": [ [ - "FCVTNS" + "CMPEQ" + ], + [ + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnh_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq_wide[_s16]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint16_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -22828,46 +27519,61 @@ ], "instructions": [ [ - "FCVTNU" + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnh_u32_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq_wide[_s32]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint32_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTNU" + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnh_u64_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq_wide[_s8]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint8_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -22875,70 +27581,92 @@ ], "instructions": [ [ - "FCVTNU" + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnq_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge[_f16]", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTNS" + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnq_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpge[_f32]", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTNS" + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnq_s64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpge[_f64]", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -22946,70 +27674,98 @@ ], "instructions": [ [ - "FCVTNS" + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnq_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_f16]", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTNU" + "FCMGE" + ], + [ + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnq_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_f32]", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTNU" + "FCMGE" + ], + [ + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnq_u64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_f64]", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -23017,22 +27773,33 @@ ], "instructions": [ [ - "FCVTNU" + "FCMGE" + ], + [ + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtns_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_s16]", "arguments": [ - "float32_t a" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "int32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -23040,22 +27807,33 @@ ], "instructions": [ [ - "FCVTNS" + "CMPGE" + ], + [ + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtns_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_s32]", "arguments": [ - "float32_t a" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -23063,70 +27841,101 @@ ], "instructions": [ [ - "FCVTNU" + "CMPGE" + ], + [ + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtp_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_s64]", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTPS" + "CMPGE" + ], + [ + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtp_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_s8]", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTPS" + "CMPGE" + ], + [ + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtp_s64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_u16]", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "int64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -23134,70 +27943,101 @@ ], "instructions": [ [ - "FCVTPS" + "CMPHS" + ], + [ + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtp_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_u32]", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTPU" + "CMPHS" + ], + [ + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtp_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_u64]", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTPU" + "CMPHS" + ], + [ + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtp_u64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_u8]", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -23205,22 +28045,33 @@ ], "instructions": [ [ - "FCVTPU" + "CMPHS" + ], + [ + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtpd_s64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpge[_s16]", "arguments": [ - "float64_t a" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "int64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -23228,22 +28079,30 @@ ], "instructions": [ [ - "FCVTPS" + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtpd_u64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpge[_s32]", "arguments": [ - "float64_t a" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -23251,22 +28110,30 @@ ], "instructions": [ [ - "FCVTPU" + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtph_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge[_s64]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "int16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -23274,46 +28141,61 @@ ], "instructions": [ [ - "FCVTPS" + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtph_s32_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge[_s8]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "int32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTPS" + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtph_s64_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge[_u16]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "int64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -23321,22 +28203,30 @@ ], "instructions": [ [ - "FCVTPS" + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtph_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge[_u32]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -23344,46 +28234,61 @@ ], "instructions": [ [ - "FCVTPU" + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtph_u32_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge[_u64]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTPU" + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtph_u64_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge[_u8]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -23391,70 +28296,98 @@ ], "instructions": [ [ - "FCVTPU" + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtpq_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_n_s16]", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svint16_t op1", + "int64_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTPS" + "CMPGE" + ], + [ + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtpq_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_n_s32]", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svint32_t op1", + "int64_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTPS" + "CMPGE" + ], + [ + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtpq_s64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_n_s8]", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svint8_t op1", + "int64_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -23462,70 +28395,101 @@ ], "instructions": [ [ - "FCVTPS" + "CMPGE" + ], + [ + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtpq_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_n_u16]", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svuint16_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTPU" + "CMPHS" + ], + [ + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtpq_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_n_u32]", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svuint32_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTPU" + "CMPHS" + ], + [ + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtpq_u64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_n_u8]", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svuint8_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -23533,22 +28497,33 @@ ], "instructions": [ [ - "FCVTPU" + "CMPHS" + ], + [ + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtps_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_s16]", "arguments": [ - "float32_t a" + "svbool_t pg", + "svint16_t op1", + "svint64_t op2" ], "return_type": { - "value": "int32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -23556,22 +28531,30 @@ ], "instructions": [ [ - "FCVTPS" + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtps_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_s32]", "arguments": [ - "float32_t a" + "svbool_t pg", + "svint32_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -23579,120 +28562,154 @@ ], "instructions": [ [ - "FCVTPU" + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_f16_s16", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_s8]", "arguments": [ - "int16x8_t a" + "svbool_t pg", + "svint8_t op1", + "svint64_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SCVTF" + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_f16_u16", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_u16]", "arguments": [ - "uint16x8_t a" + "svbool_t pg", + "svuint16_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "UCVTF" + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_f32_s32", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_u32]", "arguments": [ - "int32x4_t a" + "svbool_t pg", + "svuint32_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SCVTF" + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_f32_u32", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_u8]", "arguments": [ - "uint32x4_t a" + "svbool_t pg", + "svuint8_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UCVTF" + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_f64_s64", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_f16]", "arguments": [ - "int64x2_t a" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -23700,22 +28717,30 @@ ], "instructions": [ [ - "SCVTF" + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_f64_u64", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_f32]", "arguments": [ - "uint64x2_t a" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -23723,145 +28748,163 @@ ], "instructions": [ [ - "UCVTF" + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_f16_s16", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_f64]", "arguments": [ - "int16x8_t a", - "const int n" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SCVTF" + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_f16_u16", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_f16]", "arguments": [ - "uint16x8_t a", - "const int n" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "UCVTF" + "FCMGT" + ], + [ + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_f32_s32", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_f32]", "arguments": [ - "int32x4_t a", - "const int n" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" }, - "n": { - "minimum": 1, - "maximum": 32 + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SCVTF" + "FCMGT" + ], + [ + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_f32_u32", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_f64]", "arguments": [ - "uint32x4_t a", - "const int n" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D" }, - "n": { - "minimum": 1, - "maximum": 32 + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UCVTF" + "FCMGT" + ], + [ + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_f64_s64", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_s16]", "arguments": [ - "int64x2_t a", - "const int n" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" }, - "n": { - "minimum": 1, - "maximum": 64 + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -23869,27 +28912,33 @@ ], "instructions": [ [ - "SCVTF" + "CMPGT" + ], + [ + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_f64_u64", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_s32]", "arguments": [ - "uint64x2_t a", - "const int n" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" }, - "n": { - "minimum": 1, - "maximum": 64 + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -23897,86 +28946,101 @@ ], "instructions": [ [ - "UCVTF" + "CMPGT" + ], + [ + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_s64]", "arguments": [ - "float16x8_t a", - "const int n" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "CMPGT" + ], + [ + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_s8]", "arguments": [ - "float32x4_t a", - "const int n" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.B" }, - "n": { - "minimum": 1, - "maximum": 32 + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "CMPGT" + ], + [ + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_s64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_u16]", "arguments": [ - "float64x2_t a", - "const int n" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" }, - "n": { - "minimum": 1, - "maximum": 64 + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -23984,86 +29048,101 @@ ], "instructions": [ [ - "FCVTZS" + "CMPHI" + ], + [ + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_u32]", "arguments": [ - "float16x8_t a", - "const int n" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZU" + "CMPHI" + ], + [ + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_u64]", "arguments": [ - "float32x4_t a", - "const int n" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D" }, - "n": { - "minimum": 1, - "maximum": 32 + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCVTZU" + "CMPHI" + ], + [ + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_u64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_u8]", "arguments": [ - "float64x2_t a", - "const int n" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B" }, - "n": { - "minimum": 1, - "maximum": 64 + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -24071,71 +29150,95 @@ ], "instructions": [ [ - "FCVTZU" + "CMPHI" + ], + [ + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_s16]", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_s32]", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_s64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_s64]", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -24143,71 +29246,92 @@ ], "instructions": [ [ - "FCVTZS" + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_s8]", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_u16]", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCVTZU" + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_u64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_u32]", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -24215,22 +29339,30 @@ ], "instructions": [ [ - "FCVTZU" + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvts_f32_s32", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_u64]", "arguments": [ - "int32_t a" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -24238,22 +29370,30 @@ ], "instructions": [ [ - "SCVTF" + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvts_f32_u32", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_u8]", "arguments": [ - "uint32_t a" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "float32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -24261,27 +29401,30 @@ ], "instructions": [ [ - "UCVTF" + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvts_n_f32_s32", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_n_s16]", "arguments": [ - "int32_t a", - "const int n" + "svbool_t pg", + "svint16_t op1", + "int64_t op2" ], "return_type": { - "value": "float32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.H" }, - "n": { - "minimum": 1, - "maximum": 32 + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -24289,27 +29432,33 @@ ], "instructions": [ [ - "SCVTF" + "CMPGT" + ], + [ + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvts_n_f32_u32", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_n_s32]", "arguments": [ - "uint32_t a", - "const int n" + "svbool_t pg", + "svint32_t op1", + "int64_t op2" ], "return_type": { - "value": "float32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.S" }, - "n": { - "minimum": 1, - "maximum": 32 + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -24317,27 +29466,33 @@ ], "instructions": [ [ - "UCVTF" + "CMPGT" + ], + [ + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvts_n_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_n_s8]", "arguments": [ - "float32_t a", - "const int n" + "svbool_t pg", + "svint8_t op1", + "int64_t op2" ], "return_type": { - "value": "int32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.B" }, - "n": { - "minimum": 1, - "maximum": 32 + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -24345,27 +29500,33 @@ ], "instructions": [ [ - "FCVTZS" + "CMPGT" + ], + [ + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvts_n_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_n_u16]", "arguments": [ - "float32_t a", - "const int n" + "svbool_t pg", + "svuint16_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.H" }, - "n": { - "minimum": 1, - "maximum": 32 + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -24373,22 +29534,33 @@ ], "instructions": [ [ - "FCVTZU" + "CMPHI" + ], + [ + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvts_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_n_u32]", "arguments": [ - "float32_t a" + "svbool_t pg", + "svuint32_t op1", + "uint64_t op2" ], "return_type": { - "value": "int32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -24396,22 +29568,33 @@ ], "instructions": [ [ - "FCVTZS" + "CMPHI" + ], + [ + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvts_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_n_u8]", "arguments": [ - "float32_t a" + "svbool_t pg", + "svuint8_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -24419,22 +29602,33 @@ ], "instructions": [ [ - "FCVTZU" + "CMPHI" + ], + [ + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtx_f32_f64", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_s16]", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svint16_t op1", + "svint64_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -24442,26 +29636,30 @@ ], "instructions": [ [ - "FCVTXN" + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtx_high_f32_f64", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_s32]", "arguments": [ - "float32x2_t r", - "float64x2_t a" + "svbool_t pg", + "svint32_t op1", + "svint64_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" }, - "r": { - "register": "Vd.2S" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -24469,22 +29667,30 @@ ], "instructions": [ [ - "FCVTXN2" + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtxd_f32_f64", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_s8]", "arguments": [ - "float64_t a" + "svbool_t pg", + "svint8_t op1", + "svint64_t op2" ], "return_type": { - "value": "float32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -24492,26 +29698,30 @@ ], "instructions": [ [ - "FCVTXN" + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdiv_f16", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_u16]", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -24519,26 +29729,30 @@ ], "instructions": [ [ - "FDIV" + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdiv_f32", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_u32]", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svbool_t pg", + "svuint32_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -24546,26 +29760,30 @@ ], "instructions": [ [ - "FDIV" + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdiv_f64", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_u8]", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -24573,54 +29791,61 @@ ], "instructions": [ [ - "FDIV" + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdivh_f16", + "SIMD_ISA": "SVE", + "name": "svcmple[_f16]", "arguments": [ - "float16_t a", - "float16_t b" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "float16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Hm" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FDIV" + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdivq_f16", + "SIMD_ISA": "SVE", + "name": "svcmple[_f32]", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -24628,26 +29853,30 @@ ], "instructions": [ [ - "FDIV" + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdivq_f32", + "SIMD_ISA": "SVE", + "name": "svcmple[_f64]", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -24655,26 +29884,30 @@ ], "instructions": [ [ - "FDIV" + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdivq_f64", + "SIMD_ISA": "SVE", + "name": "svcmple[_n_f16]", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -24682,109 +29915,101 @@ ], "instructions": [ [ - "FDIV" + "FCMLE" + ], + [ + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdot_lane_s32", + "SIMD_ISA": "SVE", + "name": "svcmple[_n_f32]", "arguments": [ - "int32x2_t r", - "int8x8_t a", - "int8x8_t b", - "const int lane" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.4B" + "op1": { + "register": "Zop1.S" }, - "lane": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.S[*]" }, - "r": { - "register": "Vd.2S" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SDOT" + "FCMLE" + ], + [ + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdot_lane_u32", + "SIMD_ISA": "SVE", + "name": "svcmple[_n_f64]", "arguments": [ - "uint32x2_t r", - "uint8x8_t a", - "uint8x8_t b", - "const int lane" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.4B" - }, - "lane": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.D[*]" }, - "r": { - "register": "Vd.2S" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "UDOT" + "FCMLE" + ], + [ + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdot_laneq_s32", + "SIMD_ISA": "SVE", + "name": "svcmple[_n_s16]", "arguments": [ - "int32x2_t r", - "int8x8_t a", - "int8x16_t b", - "const int lane" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.4B" + "op1": { + "register": "Zop1.H" }, - "lane": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.H[*]" }, - "r": { - "register": "Vd.2S" + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -24792,35 +30017,33 @@ ], "instructions": [ [ - "SDOT" + "CMPLE" + ], + [ + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdot_laneq_u32", + "SIMD_ISA": "SVE", + "name": "svcmple[_n_s32]", "arguments": [ - "uint32x2_t r", - "uint8x8_t a", - "uint8x16_t b", - "const int lane" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.4B" + "op1": { + "register": "Zop1.S" }, - "lane": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.S[*]" }, - "r": { - "register": "Vd.2S" + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -24828,173 +30051,169 @@ ], "instructions": [ [ - "UDOT" + "CMPLE" + ], + [ + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdot_s32", + "SIMD_ISA": "SVE", + "name": "svcmple[_n_s64]", "arguments": [ - "int32x2_t r", - "int8x8_t a", - "int8x8_t b" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.D[*]" }, - "r": { - "register": "Vd.2S" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SDOT" + "CMPLE" + ], + [ + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdot_u32", + "SIMD_ISA": "SVE", + "name": "svcmple[_n_s8]", "arguments": [ - "uint32x2_t r", - "uint8x8_t a", - "uint8x8_t b" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.B[*]" }, - "r": { - "register": "Vd.2S" + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "UDOT" + "CMPLE" + ], + [ + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdotq_lane_s32", + "SIMD_ISA": "SVE", + "name": "svcmple[_n_u16]", "arguments": [ - "int32x4_t r", - "int8x16_t a", - "int8x8_t b", - "const int lane" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.4B" + "op1": { + "register": "Zop1.H" }, - "lane": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.H[*]" }, - "r": { - "register": "Vd.4S" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SDOT" + "CMPLS" + ], + [ + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdotq_lane_u32", + "SIMD_ISA": "SVE", + "name": "svcmple[_n_u32]", "arguments": [ - "uint32x4_t r", - "uint8x16_t a", - "uint8x8_t b", - "const int lane" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.4B" + "op1": { + "register": "Zop1.S" }, - "lane": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.S[*]" }, - "r": { - "register": "Vd.4S" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "UDOT" + "CMPLS" + ], + [ + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdotq_laneq_s32", + "SIMD_ISA": "SVE", + "name": "svcmple[_n_u64]", "arguments": [ - "int32x4_t r", - "int8x16_t a", - "int8x16_t b", - "const int lane" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.4B" + "op1": { + "register": "Zop1.D" }, - "lane": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.D[*]" }, - "r": { - "register": "Vd.4S" + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -25002,35 +30221,33 @@ ], "instructions": [ [ - "SDOT" + "CMPLS" + ], + [ + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdotq_laneq_u32", + "SIMD_ISA": "SVE", + "name": "svcmple[_n_u8]", "arguments": [ - "uint32x4_t r", - "uint8x16_t a", - "uint8x16_t b", - "const int lane" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.4B" + "op1": { + "register": "Zop1.B" }, - "lane": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.B[*]" }, - "r": { - "register": "Vd.4S" + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -25038,151 +30255,157 @@ ], "instructions": [ [ - "UDOT" + "CMPLS" + ], + [ + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdotq_s32", + "SIMD_ISA": "SVE", + "name": "svcmple[_s16]", "arguments": [ - "int32x4_t r", - "int8x16_t a", - "int8x16_t b" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.H" }, - "r": { - "register": "Vd.4S" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SDOT" + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdotq_u32", + "SIMD_ISA": "SVE", + "name": "svcmple[_s32]", "arguments": [ - "uint32x4_t r", - "uint8x16_t a", - "uint8x16_t b" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.S" }, - "r": { - "register": "Vd.4S" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "UDOT" + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_f16", + "SIMD_ISA": "SVE", + "name": "svcmple[_s64]", "arguments": [ - "float16x4_t vec", - "const int lane" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "float16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_f32", + "SIMD_ISA": "SVE", + "name": "svcmple[_s8]", "arguments": [ - "float32x2_t vec", - "const int lane" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_f64", + "SIMD_ISA": "SVE", + "name": "svcmple[_u16]", "arguments": [ - "float64x1_t vec", - "const int lane" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "float64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -25190,356 +30413,389 @@ ], "instructions": [ [ - "DUP" + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_p16", + "SIMD_ISA": "SVE", + "name": "svcmple[_u32]", "arguments": [ - "poly16x4_t vec", - "const int lane" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "poly16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_p64", + "SIMD_ISA": "SVE", + "name": "svcmple[_u64]", "arguments": [ - "poly64x1_t vec", - "const int lane" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "poly64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_p8", + "SIMD_ISA": "SVE", + "name": "svcmple[_u8]", "arguments": [ - "poly8x8_t vec", - "const int lane" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "poly8x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_s16", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_n_s16]", "arguments": [ - "int16x4_t vec", - "const int lane" + "svbool_t pg", + "svint16_t op1", + "int64_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLE" + ], + [ + "CMPLE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_s32", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_n_s32]", "arguments": [ - "int32x2_t vec", - "const int lane" + "svbool_t pg", + "svint32_t op1", + "int64_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLE" + ], + [ + "CMPLE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_s64", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_n_s8]", "arguments": [ - "int64x1_t vec", - "const int lane" + "svbool_t pg", + "svint8_t op1", + "int64_t op2" ], "return_type": { - "value": "int64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLE" + ], + [ + "CMPLE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_s8", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_n_u16]", "arguments": [ - "int8x8_t vec", - "const int lane" + "svbool_t pg", + "svuint16_t op1", + "uint64_t op2" ], "return_type": { - "value": "int8x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLS" + ], + [ + "CMPLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_u16", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_n_u32]", "arguments": [ - "uint16x4_t vec", - "const int lane" + "svbool_t pg", + "svuint32_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLS" + ], + [ + "CMPLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_u32", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_n_u8]", "arguments": [ - "uint32x2_t vec", - "const int lane" + "svbool_t pg", + "svuint8_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLS" + ], + [ + "CMPLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_u64", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_s16]", "arguments": [ - "uint64x1_t vec", - "const int lane" + "svbool_t pg", + "svint16_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_u8", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_s32]", "arguments": [ - "uint8x8_t vec", - "const int lane" + "svbool_t pg", + "svint32_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_f16", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_s8]", "arguments": [ - "float16x8_t vec", - "const int lane" + "svbool_t pg", + "svint8_t op1", + "svint64_t op2" ], "return_type": { - "value": "float16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -25547,27 +30803,30 @@ ], "instructions": [ [ - "DUP" + "CMPLE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_f32", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_u16]", "arguments": [ - "float32x4_t vec", - "const int lane" + "svbool_t pg", + "svuint16_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.4S" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -25575,27 +30834,30 @@ ], "instructions": [ [ - "DUP" + "CMPLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_f64", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_u32]", "arguments": [ - "float64x2_t vec", - "const int lane" + "svbool_t pg", + "svuint32_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.2D" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -25603,27 +30865,30 @@ ], "instructions": [ [ - "DUP" + "CMPLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_p16", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_u8]", "arguments": [ - "poly16x8_t vec", - "const int lane" + "svbool_t pg", + "svuint8_t op1", + "svuint64_t op2" ], "return_type": { - "value": "poly16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -25631,27 +30896,30 @@ ], "instructions": [ [ - "DUP" + "CMPLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_p64", + "SIMD_ISA": "SVE", + "name": "svcmplt[_f16]", "arguments": [ - "poly64x2_t vec", - "const int lane" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "poly64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.2D" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -25659,27 +30927,30 @@ ], "instructions": [ [ - "DUP" + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_p8", + "SIMD_ISA": "SVE", + "name": "svcmplt[_f32]", "arguments": [ - "poly8x16_t vec", - "const int lane" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "poly8x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -25687,27 +30958,30 @@ ], "instructions": [ [ - "DUP" + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_s16", + "SIMD_ISA": "SVE", + "name": "svcmplt[_f64]", "arguments": [ - "int16x8_t vec", - "const int lane" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -25715,27 +30989,30 @@ ], "instructions": [ [ - "DUP" + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_s32", + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_f16]", "arguments": [ - "int32x4_t vec", - "const int lane" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.4S" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -25743,27 +31020,33 @@ ], "instructions": [ [ - "DUP" + "FCMLT" + ], + [ + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_s64", + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_f32]", "arguments": [ - "int64x2_t vec", - "const int lane" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "int64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.2D" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -25771,27 +31054,33 @@ ], "instructions": [ [ - "DUP" + "FCMLT" + ], + [ + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_s8", + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_f64]", "arguments": [ - "int8x16_t vec", - "const int lane" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "int8x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -25799,27 +31088,33 @@ ], "instructions": [ [ - "DUP" + "FCMLT" + ], + [ + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_u16", + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_s16]", "arguments": [ - "uint16x8_t vec", - "const int lane" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -25827,27 +31122,33 @@ ], "instructions": [ [ - "DUP" + "CMPLT" + ], + [ + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_u32", + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_s32]", "arguments": [ - "uint32x4_t vec", - "const int lane" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.4S" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -25855,27 +31156,33 @@ ], "instructions": [ [ - "DUP" + "CMPLT" + ], + [ + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_u64", + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_s64]", "arguments": [ - "uint64x2_t vec", - "const int lane" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.2D" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -25883,27 +31190,33 @@ ], "instructions": [ [ - "DUP" + "CMPLT" + ], + [ + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_u8", + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_s8]", "arguments": [ - "uint8x16_t vec", - "const int lane" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -25911,72 +31224,101 @@ ], "instructions": [ [ - "DUP" + "CMPLT" + ], + [ + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_f16", + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_u16]", "arguments": [ - "float16_t value" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "float16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLO" + ], + [ + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_f32", + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_u32]", "arguments": [ - "float32_t value" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLO" + ], + [ + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_f64", + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_u64]", "arguments": [ - "float64_t value" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "float64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -25984,301 +31326,383 @@ ], "instructions": [ [ - "INS" + "CMPLO" + ], + [ + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_p16", + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_u8]", "arguments": [ - "poly16_t value" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "poly16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLO" + ], + [ + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_p64", + "SIMD_ISA": "SVE", + "name": "svcmplt[_s16]", "arguments": [ - "poly64_t value" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "poly64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "INS" + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_p8", + "SIMD_ISA": "SVE", + "name": "svcmplt[_s32]", "arguments": [ - "poly8_t value" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "poly8x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_s16", + "SIMD_ISA": "SVE", + "name": "svcmplt[_s64]", "arguments": [ - "int16_t value" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_s32", + "SIMD_ISA": "SVE", + "name": "svcmplt[_s8]", "arguments": [ - "int32_t value" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_s64", + "SIMD_ISA": "SVE", + "name": "svcmplt[_u16]", "arguments": [ - "int64_t value" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "int64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_s8", + "SIMD_ISA": "SVE", + "name": "svcmplt[_u32]", "arguments": [ - "int8_t value" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "int8x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_u16", + "SIMD_ISA": "SVE", + "name": "svcmplt[_u64]", "arguments": [ - "uint16_t value" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_u32", + "SIMD_ISA": "SVE", + "name": "svcmplt[_u8]", "arguments": [ - "uint32_t value" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_u64", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_n_s16]", "arguments": [ - "uint64_t value" + "svbool_t pg", + "svint16_t op1", + "int64_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "CMPLT" + ], + [ + "CMPLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_u8", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_n_s32]", "arguments": [ - "uint8_t value" + "svbool_t pg", + "svint32_t op1", + "int64_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLT" + ], + [ + "CMPLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupb_lane_p8", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_n_s8]", "arguments": [ - "poly8x8_t vec", - "const int lane" + "svbool_t pg", + "svint8_t op1", + "int64_t op2" ], "return_type": { - "value": "poly8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -26286,27 +31710,33 @@ ], "instructions": [ [ - "DUP" + "CMPLT" + ], + [ + "CMPLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupb_lane_s8", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_n_u16]", "arguments": [ - "int8x8_t vec", - "const int lane" + "svbool_t pg", + "svuint16_t op1", + "uint64_t op2" ], "return_type": { - "value": "int8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -26314,27 +31744,33 @@ ], "instructions": [ [ - "DUP" + "CMPLO" + ], + [ + "CMPLO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupb_lane_u8", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_n_u32]", "arguments": [ - "uint8x8_t vec", - "const int lane" + "svbool_t pg", + "svuint32_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -26342,27 +31778,33 @@ ], "instructions": [ [ - "DUP" + "CMPLO" + ], + [ + "CMPLO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupb_laneq_p8", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_n_u8]", "arguments": [ - "poly8x16_t vec", - "const int lane" + "svbool_t pg", + "svuint8_t op1", + "uint64_t op2" ], "return_type": { - "value": "poly8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -26370,27 +31812,33 @@ ], "instructions": [ [ - "DUP" + "CMPLO" + ], + [ + "CMPLO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupb_laneq_s8", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_s16]", "arguments": [ - "int8x16_t vec", - "const int lane" + "svbool_t pg", + "svint16_t op1", + "svint64_t op2" ], "return_type": { - "value": "int8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -26398,27 +31846,30 @@ ], "instructions": [ [ - "DUP" + "CMPLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupb_laneq_u8", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_s32]", "arguments": [ - "uint8x16_t vec", - "const int lane" + "svbool_t pg", + "svint32_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -26426,27 +31877,30 @@ ], "instructions": [ [ - "DUP" + "CMPLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupd_lane_f64", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_s8]", "arguments": [ - "float64x1_t vec", - "const int lane" + "svbool_t pg", + "svint8_t op1", + "svint64_t op2" ], "return_type": { - "value": "float64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -26454,27 +31908,30 @@ ], "instructions": [ [ - "DUP" + "CMPLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupd_lane_s64", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_u16]", "arguments": [ - "int64x1_t vec", - "const int lane" + "svbool_t pg", + "svuint16_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -26482,27 +31939,30 @@ ], "instructions": [ [ - "DUP" + "CMPLO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupd_lane_u64", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_u32]", "arguments": [ - "uint64x1_t vec", - "const int lane" + "svbool_t pg", + "svuint32_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -26510,27 +31970,30 @@ ], "instructions": [ [ - "DUP" + "CMPLO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupd_laneq_f64", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_u8]", "arguments": [ - "float64x2_t vec", - "const int lane" + "svbool_t pg", + "svuint8_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.2D" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -26538,27 +32001,30 @@ ], "instructions": [ [ - "DUP" + "CMPLO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupd_laneq_s64", + "SIMD_ISA": "SVE", + "name": "svcmpne[_f16]", "arguments": [ - "int64x2_t vec", - "const int lane" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "int64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.2D" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -26566,27 +32032,30 @@ ], "instructions": [ [ - "DUP" + "FCMNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupd_laneq_u64", + "SIMD_ISA": "SVE", + "name": "svcmpne[_f32]", "arguments": [ - "uint64x2_t vec", - "const int lane" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.2D" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -26594,27 +32063,30 @@ ], "instructions": [ [ - "DUP" + "FCMNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vduph_lane_f16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_f64]", "arguments": [ - "float16x4_t vec", - "const int lane" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "float16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -26622,27 +32094,30 @@ ], "instructions": [ [ - "DUP" + "FCMNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vduph_lane_p16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_f16]", "arguments": [ - "poly16x4_t vec", - "const int lane" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "poly16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -26650,27 +32125,33 @@ ], "instructions": [ [ - "DUP" + "FCMNE" + ], + [ + "FCMNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vduph_lane_s16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_f32]", "arguments": [ - "int16x4_t vec", - "const int lane" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "int16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -26678,27 +32159,33 @@ ], "instructions": [ [ - "DUP" + "FCMNE" + ], + [ + "FCMNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vduph_lane_u16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_f64]", "arguments": [ - "uint16x4_t vec", - "const int lane" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -26706,27 +32193,33 @@ ], "instructions": [ [ - "DUP" + "FCMNE" + ], + [ + "FCMNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vduph_laneq_f16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_s16]", "arguments": [ - "float16x8_t vec", - "const int lane" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "float16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -26734,27 +32227,33 @@ ], "instructions": [ [ - "DUP" + "CMPNE" + ], + [ + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vduph_laneq_p16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_s32]", "arguments": [ - "poly16x8_t vec", - "const int lane" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "poly16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -26762,27 +32261,33 @@ ], "instructions": [ [ - "DUP" + "CMPNE" + ], + [ + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vduph_laneq_s16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_s64]", "arguments": [ - "int16x8_t vec", - "const int lane" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "int16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -26790,27 +32295,33 @@ ], "instructions": [ [ - "DUP" + "CMPNE" + ], + [ + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vduph_laneq_u16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_s8]", "arguments": [ - "uint16x8_t vec", - "const int lane" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -26818,87 +32329,101 @@ ], "instructions": [ [ - "DUP" + "CMPNE" + ], + [ + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_f16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_u16]", "arguments": [ - "float16x4_t vec", - "const int lane" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" + ], + [ + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_f32", + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_u32]", "arguments": [ - "float32x2_t vec", - "const int lane" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" + ], + [ + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_f64", + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_u64]", "arguments": [ - "float64x1_t vec", - "const int lane" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -26906,356 +32431,383 @@ ], "instructions": [ [ - "DUP" + "CMPNE" + ], + [ + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_p16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_u8]", "arguments": [ - "poly16x4_t vec", - "const int lane" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "poly16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" + ], + [ + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_p64", + "SIMD_ISA": "SVE", + "name": "svcmpne[_s16]", "arguments": [ - "poly64x1_t vec", - "const int lane" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "poly64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_p8", + "SIMD_ISA": "SVE", + "name": "svcmpne[_s32]", "arguments": [ - "poly8x8_t vec", - "const int lane" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "poly8x16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_s16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_s64]", "arguments": [ - "int16x4_t vec", - "const int lane" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_s32", + "SIMD_ISA": "SVE", + "name": "svcmpne[_s8]", "arguments": [ - "int32x2_t vec", - "const int lane" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_s64", + "SIMD_ISA": "SVE", + "name": "svcmpne[_u16]", "arguments": [ - "int64x1_t vec", - "const int lane" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_s8", + "SIMD_ISA": "SVE", + "name": "svcmpne[_u32]", "arguments": [ - "int8x8_t vec", - "const int lane" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "int8x16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_u16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_u64]", "arguments": [ - "uint16x4_t vec", - "const int lane" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_u32", + "SIMD_ISA": "SVE", + "name": "svcmpne[_u8]", "arguments": [ - "uint32x2_t vec", - "const int lane" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_u64", + "SIMD_ISA": "SVE", + "name": "svcmpne_wide[_n_s16]", "arguments": [ - "uint64x1_t vec", - "const int lane" + "svbool_t pg", + "svint16_t op1", + "int64_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" + ], + [ + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_u8", + "SIMD_ISA": "SVE", + "name": "svcmpne_wide[_n_s32]", "arguments": [ - "uint8x8_t vec", - "const int lane" + "svbool_t pg", + "svint32_t op1", + "int64_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" + ], + [ + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_f16", + "SIMD_ISA": "SVE", + "name": "svcmpne_wide[_n_s8]", "arguments": [ - "float16x8_t vec", - "const int lane" + "svbool_t pg", + "svint8_t op1", + "int64_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -27263,27 +32815,33 @@ ], "instructions": [ [ - "DUP" + "CMPNE" + ], + [ + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_f32", + "SIMD_ISA": "SVE", + "name": "svcmpne_wide[_s16]", "arguments": [ - "float32x4_t vec", - "const int lane" + "svbool_t pg", + "svint16_t op1", + "svint64_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.4S" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -27291,27 +32849,30 @@ ], "instructions": [ [ - "DUP" + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_f64", + "SIMD_ISA": "SVE", + "name": "svcmpne_wide[_s32]", "arguments": [ - "float64x2_t vec", - "const int lane" + "svbool_t pg", + "svint32_t op1", + "svint64_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.2D" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -27319,27 +32880,30 @@ ], "instructions": [ [ - "DUP" + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_p16", + "SIMD_ISA": "SVE", + "name": "svcmpne_wide[_s8]", "arguments": [ - "poly16x8_t vec", - "const int lane" + "svbool_t pg", + "svint8_t op1", + "svint64_t op2" ], "return_type": { - "value": "poly16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -27347,27 +32911,30 @@ ], "instructions": [ [ - "DUP" + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_p64", + "SIMD_ISA": "SVE", + "name": "svcmpuo[_f16]", "arguments": [ - "poly64x2_t vec", - "const int lane" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "poly64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.2D" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -27375,27 +32942,30 @@ ], "instructions": [ [ - "DUP" + "FCMUO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_p8", + "SIMD_ISA": "SVE", + "name": "svcmpuo[_f32]", "arguments": [ - "poly8x16_t vec", - "const int lane" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "poly8x16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -27403,27 +32973,30 @@ ], "instructions": [ [ - "DUP" + "FCMUO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_s16", + "SIMD_ISA": "SVE", + "name": "svcmpuo[_f64]", "arguments": [ - "int16x8_t vec", - "const int lane" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -27431,27 +33004,30 @@ ], "instructions": [ [ - "DUP" + "FCMUO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_s32", + "SIMD_ISA": "SVE", + "name": "svcmpuo[_n_f16]", "arguments": [ - "int32x4_t vec", - "const int lane" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.4S" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -27459,27 +33035,30 @@ ], "instructions": [ [ - "DUP" + "FCMUO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_s64", + "SIMD_ISA": "SVE", + "name": "svcmpuo[_n_f32]", "arguments": [ - "int64x2_t vec", - "const int lane" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.2D" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -27487,27 +33066,30 @@ ], "instructions": [ [ - "DUP" + "FCMUO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_s8", + "SIMD_ISA": "SVE", + "name": "svcmpuo[_n_f64]", "arguments": [ - "int8x16_t vec", - "const int lane" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "int8x16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -27515,27 +33097,30 @@ ], "instructions": [ [ - "DUP" + "FCMUO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_u16", + "SIMD_ISA": "SVE", + "name": "svcnot[_s16]_m", "arguments": [ - "uint16x8_t vec", - "const int lane" + "svint16_t inactive", + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "inactive": { + "register": "Zinactive.H|Ztied.H" }, - "vec": { - "register": "Vn.8H" + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -27543,27 +33128,30 @@ ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_u32", + "SIMD_ISA": "SVE", + "name": "svcnot[_s16]_x", "arguments": [ - "uint32x4_t vec", - "const int lane" + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "uint32x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op": { + "register": "Zop.H|Ztied.H" }, - "vec": { - "register": "Vn.4S" + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -27571,27 +33159,30 @@ ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_u64", + "SIMD_ISA": "SVE", + "name": "svcnot[_s16]_z", "arguments": [ - "uint64x2_t vec", - "const int lane" + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "uint64x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op": { + "register": "Zop.H" }, - "vec": { - "register": "Vn.2D" + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -27599,27 +33190,31 @@ ], "instructions": [ [ - "DUP" + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_u8", + "SIMD_ISA": "SVE", + "name": "svcnot[_s32]_m", "arguments": [ - "uint8x16_t vec", - "const int lane" + "svint32_t inactive", + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "uint8x16_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 + "inactive": { + "register": "Zinactive.S|Ztied.S" }, - "vec": { - "register": "Vn.16B" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -27627,72 +33222,93 @@ ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_f16", + "SIMD_ISA": "SVE", + "name": "svcnot[_s32]_x", "arguments": [ - "float16_t value" + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "float16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_f32", + "SIMD_ISA": "SVE", + "name": "svcnot[_s32]_z", "arguments": [ - "float32_t value" + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "float32x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_f64", + "SIMD_ISA": "SVE", + "name": "svcnot[_s64]_m", "arguments": [ - "float64_t value" + "svint64_t inactive", + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "float64x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -27700,301 +33316,375 @@ ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_p16", + "SIMD_ISA": "SVE", + "name": "svcnot[_s64]_x", "arguments": [ - "poly16_t value" + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "poly16x8_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_p64", + "SIMD_ISA": "SVE", + "name": "svcnot[_s64]_z", "arguments": [ - "poly64_t value" + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "poly64x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "DUP" + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_p8", + "SIMD_ISA": "SVE", + "name": "svcnot[_s8]_m", "arguments": [ - "poly8_t value" + "svint8_t inactive", + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "poly8x16_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "inactive": { + "register": "Zinactive.B|Ztied.B" + }, + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_s16", + "SIMD_ISA": "SVE", + "name": "svcnot[_s8]_x", "arguments": [ - "int16_t value" + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "int16x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op": { + "register": "Zop.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_s32", + "SIMD_ISA": "SVE", + "name": "svcnot[_s8]_z", "arguments": [ - "int32_t value" + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "int32x4_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_s64", + "SIMD_ISA": "SVE", + "name": "svcnot[_u16]_m", "arguments": [ - "int64_t value" + "svuint16_t inactive", + "svbool_t pg", + "svuint16_t op" ], "return_type": { - "value": "int64x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_s8", + "SIMD_ISA": "SVE", + "name": "svcnot[_u16]_x", "arguments": [ - "int8_t value" + "svbool_t pg", + "svuint16_t op" ], "return_type": { - "value": "int8x16_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_u16", + "SIMD_ISA": "SVE", + "name": "svcnot[_u16]_z", "arguments": [ - "uint16_t value" + "svbool_t pg", + "svuint16_t op" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_u32", + "SIMD_ISA": "SVE", + "name": "svcnot[_u32]_m", "arguments": [ - "uint32_t value" + "svuint32_t inactive", + "svbool_t pg", + "svuint32_t op" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_u64", + "SIMD_ISA": "SVE", + "name": "svcnot[_u32]_x", "arguments": [ - "uint64_t value" + "svbool_t pg", + "svuint32_t op" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_u8", + "SIMD_ISA": "SVE", + "name": "svcnot[_u32]_z", "arguments": [ - "uint8_t value" + "svbool_t pg", + "svuint32_t op" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdups_lane_f32", + "SIMD_ISA": "SVE", + "name": "svcnot[_u64]_m", "arguments": [ - "float32x2_t vec", - "const int lane" + "svuint64_t inactive", + "svbool_t pg", + "svuint64_t op" ], "return_type": { - "value": "float32_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "inactive": { + "register": "Zinactive.D|Ztied.D" }, - "vec": { - "register": "Vn.2S" + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -28002,27 +33692,30 @@ ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdups_lane_s32", + "SIMD_ISA": "SVE", + "name": "svcnot[_u64]_x", "arguments": [ - "int32x2_t vec", - "const int lane" + "svbool_t pg", + "svuint64_t op" ], "return_type": { - "value": "int32_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op": { + "register": "Zop.D|Ztied.D" }, - "vec": { - "register": "Vn.2S" + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -28030,27 +33723,30 @@ ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdups_lane_u32", + "SIMD_ISA": "SVE", + "name": "svcnot[_u64]_z", "arguments": [ - "uint32x2_t vec", - "const int lane" + "svbool_t pg", + "svuint64_t op" ], "return_type": { - "value": "uint32_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op": { + "register": "Zop.D" }, - "vec": { - "register": "Vn.2S" + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -28058,27 +33754,31 @@ ], "instructions": [ [ - "DUP" + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdups_laneq_f32", + "SIMD_ISA": "SVE", + "name": "svcnot[_u8]_m", "arguments": [ - "float32x4_t vec", - "const int lane" + "svuint8_t inactive", + "svbool_t pg", + "svuint8_t op" ], "return_type": { - "value": "float32_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "inactive": { + "register": "Zinactive.B|Ztied.B" }, - "vec": { - "register": "Vn.4S" + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -28086,27 +33786,30 @@ ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdups_laneq_s32", + "SIMD_ISA": "SVE", + "name": "svcnot[_u8]_x", "arguments": [ - "int32x4_t vec", - "const int lane" + "svbool_t pg", + "svuint8_t op" ], "return_type": { - "value": "int32_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op": { + "register": "Zop.B|Ztied.B" }, - "vec": { - "register": "Vn.4S" + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -28114,27 +33817,30 @@ ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdups_laneq_u32", + "SIMD_ISA": "SVE", + "name": "svcnot[_u8]_z", "arguments": [ - "uint32x4_t vec", - "const int lane" + "svbool_t pg", + "svuint8_t op" ], "return_type": { - "value": "uint32_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op": { + "register": "Zop.B" }, - "vec": { - "register": "Vn.4S" + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -28142,779 +33848,845 @@ ], "instructions": [ [ - "DUP" + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "veor3q_s16", + "SIMD_ISA": "SVE", + "name": "svcnt[_f16]_m", "arguments": [ - "int16x8_t a", - "int16x8_t b", - "int16x8_t c" + "svuint16_t inactive", + "svbool_t pg", + "svfloat16_t op" ], "return_type": { - "value": "int16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" }, - "b": {}, - "c": {} + "pg": { + "register": "Pg.H" + } }, "Architectures": [ "A64" ], "instructions": [ [ - "EOR3" + "CNT" + ], + [ + "MOVPRFX", + "CNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "veor3q_s32", + "SIMD_ISA": "SVE", + "name": "svcnt[_f16]_x", "arguments": [ - "int32x4_t a", - "int32x4_t b", - "int32x4_t c" + "svbool_t pg", + "svfloat16_t op" ], "return_type": { - "value": "int32x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op": { + "register": "Zop.H|Ztied.H" }, - "b": {}, - "c": {} + "pg": { + "register": "Pg.H" + } }, "Architectures": [ "A64" ], "instructions": [ [ - "EOR3" + "CNT" + ], + [ + "MOVPRFX", + "CNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "veor3q_s64", + "SIMD_ISA": "SVE", + "name": "svcnt[_f16]_z", "arguments": [ - "int64x2_t a", - "int64x2_t b", - "int64x2_t c" + "svbool_t pg", + "svfloat16_t op" ], "return_type": { - "value": "int64x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op": { + "register": "Zop.H" }, - "b": {}, - "c": {} + "pg": { + "register": "Pg.H" + } }, "Architectures": [ "A64" ], "instructions": [ [ - "EOR3" + "MOVPRFX", + "CNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "veor3q_s8", + "SIMD_ISA": "SVE", + "name": "svcnt[_f32]_m", "arguments": [ - "int8x16_t a", - "int8x16_t b", - "int8x16_t c" + "svuint32_t inactive", + "svbool_t pg", + "svfloat32_t op" ], "return_type": { - "value": "int8x16_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" }, - "b": {}, - "c": {} + "pg": { + "register": "Pg.S" + } }, "Architectures": [ "A64" ], "instructions": [ [ - "EOR3" + "CNT" + ], + [ + "MOVPRFX", + "CNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "veor3q_u16", + "SIMD_ISA": "SVE", + "name": "svcnt[_f32]_x", "arguments": [ - "uint16x8_t a", - "uint16x8_t b", - "uint16x8_t c" + "svbool_t pg", + "svfloat32_t op" ], "return_type": { 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"veor_s16", + "SIMD_ISA": "SVE", + "name": "svcnt[_f64]_z", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "svbool_t pg", + "svfloat64_t op" ], "return_type": { - "value": "int16x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op": { + "register": "Zop.D" }, - "b": { - "register": "Vm.8B" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "EOR" + "MOVPRFX", + "CNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "veor_s32", + "SIMD_ISA": "SVE", + "name": "svcnt[_s16]_m", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "svuint16_t inactive", + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "int32x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "inactive": { + "register": "Zinactive.H|Ztied.H" }, - "b": { - "register": "Vm.8B" + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", 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[ - "EXT" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vextq_f16", + "name": "vdupq_laneq_u32", "arguments": [ - "float16x8_t a", - "float16x8_t b", - "const int n" + "uint32x4_t vec", + "const int lane" ], "return_type": { - "value": "float16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.16B" + "vec": { + "register": "Vn.4S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vdupq_laneq_u64", + "arguments": [ + "uint64x2_t vec", + "const int lane" + ], + "return_type": { + "value": "uint64x2_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 }, - "n": { + "vec": { + "register": "Vn.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vdupq_laneq_u8", + "arguments": [ + "uint8x16_t vec", + "const int lane" + ], + "return_type": { + "value": "uint8x16_t" + }, + "Arguments_Preparation": { + "lane": { "minimum": 0, - "maximum": 7 + "maximum": 15 + }, + "vec": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vdupq_n_f16", + "arguments": [ + "float16_t value" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "value": { + "register": "rn" } }, "Architectures": [ @@ -29329,31 +223572,22 @@ ], "instructions": [ [ - "EXT" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vextq_f32", + "name": "vdupq_n_f32", "arguments": [ - "float32x4_t a", - "float32x4_t b", - "const int n" + "float32_t value" ], "return_type": { "value": "float32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" - }, - "n": { - "minimum": 0, - "maximum": 3 + "value": { + "register": "rn" } }, "Architectures": [ @@ -29363,31 +223597,22 @@ ], "instructions": [ [ - "EXT" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vextq_f64", + "name": "vdupq_n_f64", "arguments": [ - "float64x2_t a", - "float64x2_t b", - "const int n" + "float64_t value" ], "return_type": { "value": "float64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" - }, - "n": { - "minimum": 0, - "maximum": 1 + "value": { + "register": "rn" } }, "Architectures": [ @@ -29395,31 +223620,22 @@ ], "instructions": [ [ - "EXT" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vextq_p16", + "name": "vdupq_n_p16", "arguments": [ - "poly16x8_t a", - "poly16x8_t b", - "const int n" + "poly16_t value" ], "return_type": { "value": "poly16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" - }, - "n": { - "minimum": 0, - "maximum": 7 + "value": { + "register": "rn" } }, "Architectures": [ @@ -29429,31 +223645,22 @@ ], "instructions": [ [ - "EXT" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vextq_p64", + "name": "vdupq_n_p64", "arguments": [ - "poly64x2_t a", - "poly64x2_t b", - "const int n" + "poly64_t value" ], "return_type": { "value": "poly64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" - }, - "n": { - "minimum": 0, - "maximum": 1 + "value": { + "register": "rn" } }, "Architectures": [ @@ -29462,31 +223669,22 @@ ], "instructions": [ [ - "EXT" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vextq_p8", + "name": "vdupq_n_p8", "arguments": [ - "poly8x16_t a", - "poly8x16_t b", - "const int n" + "poly8_t value" ], "return_type": { "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" - }, - "n": { - "minimum": 0, - "maximum": 15 + "value": { + "register": "rn" } }, "Architectures": [ @@ -29496,31 +223694,22 @@ ], "instructions": [ [ - "EXT" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vextq_s16", + "name": "vdupq_n_s16", "arguments": [ - "int16x8_t a", - "int16x8_t b", - "const int n" + "int16_t value" ], "return_type": { "value": "int16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" - }, - "n": { - "minimum": 0, - "maximum": 7 + "value": { + "register": "rn" } }, "Architectures": [ @@ -29530,31 +223719,22 @@ ], "instructions": [ [ - "EXT" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vextq_s32", + "name": "vdupq_n_s32", "arguments": [ - "int32x4_t a", - "int32x4_t b", - "const int n" + "int32_t value" ], "return_type": { "value": "int32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" - }, - "n": { - "minimum": 0, - "maximum": 3 + "value": { + "register": "rn" } }, "Architectures": [ @@ -29564,31 +223744,22 @@ ], "instructions": [ [ - "EXT" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vextq_s64", + "name": "vdupq_n_s64", "arguments": [ - "int64x2_t a", - "int64x2_t b", - "const int n" + "int64_t value" ], "return_type": { "value": "int64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" - }, - "n": { - "minimum": 0, - "maximum": 1 + "value": { + "register": "rn" } }, "Architectures": [ @@ -29598,31 +223769,22 @@ ], "instructions": [ [ - "EXT" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vextq_s8", + "name": "vdupq_n_s8", "arguments": [ - "int8x16_t a", - "int8x16_t b", - "const int n" + "int8_t value" ], "return_type": { "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" - }, - "n": { - "minimum": 0, - "maximum": 15 + "value": { + "register": "rn" } }, "Architectures": [ @@ -29632,31 +223794,22 @@ ], "instructions": [ [ - "EXT" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vextq_u16", + "name": "vdupq_n_u16", "arguments": [ - "uint16x8_t a", - "uint16x8_t b", - "const int n" + "uint16_t value" ], "return_type": { "value": "uint16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" - }, - "n": { - "minimum": 0, - "maximum": 7 + "value": { + "register": "rn" } }, "Architectures": [ @@ -29666,31 +223819,22 @@ ], "instructions": [ [ - "EXT" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vextq_u32", + "name": "vdupq_n_u32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "const int n" + "uint32_t value" ], "return_type": { "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" - }, - "n": { - "minimum": 0, - "maximum": 3 + "value": { + "register": "rn" } }, "Architectures": [ @@ -29700,31 +223844,22 @@ ], "instructions": [ [ - "EXT" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vextq_u64", + "name": "vdupq_n_u64", "arguments": [ - "uint64x2_t a", - "uint64x2_t b", - "const int n" + "uint64_t value" ], "return_type": { "value": "uint64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" - }, - "n": { - "minimum": 0, - "maximum": 1 + "value": { + "register": "rn" } }, "Architectures": [ @@ -29734,31 +223869,22 @@ ], "instructions": [ [ - "EXT" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vextq_u8", + "name": "vdupq_n_u8", "arguments": [ - "uint8x16_t a", - "uint8x16_t b", - "const int n" + "uint8_t value" ], "return_type": { "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" - }, - "n": { - "minimum": 0, - "maximum": 15 + "value": { + "register": "rn" } }, "Architectures": [ @@ -29768,95 +223894,83 @@ ], "instructions": [ [ - "EXT" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfma_f16", + "name": "vdups_lane_f32", "arguments": [ - "float16x4_t a", - "float16x4_t b", - "float16x4_t c" + "float32x2_t vec", + "const int lane" ], "return_type": { - "value": "float16x4_t" + "value": "float32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 1 }, - "c": { - "register": "Vm.4H" + "vec": { + "register": "Vn.2S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMLA" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfma_f32", + "name": "vdups_lane_s32", "arguments": [ - "float32x2_t a", - "float32x2_t b", - "float32x2_t c" + "int32x2_t vec", + "const int lane" ], "return_type": { - "value": "float32x2_t" + "value": "int32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2S" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { + "vec": { "register": "Vn.2S" - }, - "c": { - "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FMLA" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfma_f64", + "name": "vdups_lane_u32", "arguments": [ - "float64x1_t a", - "float64x1_t b", - "float64x1_t c" + "uint32x2_t vec", + "const int lane" ], "return_type": { - "value": "float64x1_t" + "value": "uint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Da" - }, - "b": { - "register": "Dn" + "lane": { + "minimum": 0, + "maximum": 1 }, - "c": { - "register": "Dm" + "vec": { + "register": "Vn.2S" } }, "Architectures": [ @@ -29864,35 +223978,27 @@ ], "instructions": [ [ - "FMADD" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfma_lane_f16", + "name": "vdups_laneq_f32", "arguments": [ - "float16x4_t a", - "float16x4_t b", - "float16x4_t v", + "float32x4_t vec", "const int lane" ], "return_type": { - "value": "float16x4_t" + "value": "float32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" - }, "lane": { "minimum": 0, "maximum": 3 }, - "v": { - "register": "Vm.4H" + "vec": { + "register": "Vn.4S" } }, "Architectures": [ @@ -29900,35 +224006,27 @@ ], "instructions": [ [ - "FMLA" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfma_lane_f32", + "name": "vdups_laneq_s32", "arguments": [ - "float32x2_t a", - "float32x2_t b", - "float32x2_t v", + "int32x4_t vec", "const int lane" ], "return_type": { - "value": "float32x2_t" + "value": "int32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.2S" - }, "lane": { "minimum": 0, - "maximum": 1 + "maximum": 3 }, - "v": { - "register": "Vm.2S" + "vec": { + "register": "Vn.4S" } }, "Architectures": [ @@ -29936,35 +224034,27 @@ ], "instructions": [ [ - "FMLA" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfma_lane_f64", + "name": "vdups_laneq_u32", "arguments": [ - "float64x1_t a", - "float64x1_t b", - "float64x1_t v", + "uint32x4_t vec", "const int lane" ], "return_type": { - "value": "float64x1_t" + "value": "uint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dd" - }, - "b": { - "register": "Dn" - }, "lane": { "minimum": 0, - "maximum": 0 + "maximum": 3 }, - "v": { - "register": "Vm.1D" + "vec": { + "register": "Vn.4S" } }, "Architectures": [ @@ -29972,35 +224062,30 @@ ], "instructions": [ [ - "FMLA" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfma_laneq_f16", + "name": "veor3q_s16", "arguments": [ - "float16x4_t a", - "float16x4_t b", - "float16x8_t v", - "const int lane" + "int16x8_t a", + "int16x8_t b", + "int16x8_t c" ], "return_type": { - "value": "float16x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.16B" }, "b": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 7 + "register": "Vm.16B" }, - "v": { - "register": "Vm.8H" + "c": { + "register": "Va.16B" } }, "Architectures": [ @@ -30008,35 +224093,30 @@ ], "instructions": [ [ - "FMLA" + "EOR3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfma_laneq_f32", + "name": "veor3q_s32", "arguments": [ - "float32x2_t a", - "float32x2_t b", - "float32x4_t v", - "const int lane" + "int32x4_t a", + "int32x4_t b", + "int32x4_t c" ], "return_type": { - "value": "float32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.16B" }, "b": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Vm.16B" }, - "v": { - "register": "Vm.4S" + "c": { + "register": "Va.16B" } }, "Architectures": [ @@ -30044,35 +224124,30 @@ ], "instructions": [ [ - "FMLA" + "EOR3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfma_laneq_f64", + "name": "veor3q_s64", "arguments": [ - "float64x1_t a", - "float64x1_t b", - "float64x2_t v", - "const int lane" + "int64x2_t a", + "int64x2_t b", + "int64x2_t c" ], "return_type": { - "value": "float64x1_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.16B" }, "b": { - "register": "Dn" - }, - "lane": { - "minimum": 0, - "maximum": 1 + "register": "Vm.16B" }, - "v": { - "register": "Vm.2D" + "c": { + "register": "Va.16B" } }, "Architectures": [ @@ -30080,30 +224155,30 @@ ], "instructions": [ [ - "FMLA" + "EOR3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfma_n_f16", + "name": "veor3q_s8", "arguments": [ - "float16x4_t a", - "float16x4_t b", - "float16_t n" + "int8x16_t a", + "int8x16_t b", + "int8x16_t c" ], "return_type": { - "value": "float16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H " + "register": "Vn.16B" }, "b": { - "register": "Vn.4H" + "register": "Vm.16B" }, - "n": { - "register": "Vm.H[0]" + "c": { + "register": "Va.16B" } }, "Architectures": [ @@ -30111,63 +224186,61 @@ ], "instructions": [ [ - "FMLA" + "EOR3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfma_n_f32", + "name": "veor3q_u16", "arguments": [ - "float32x2_t a", - "float32x2_t b", - "float32_t n" + "uint16x8_t a", + "uint16x8_t b", + "uint16x8_t c" ], "return_type": { - "value": "float32x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.16B" }, "b": { - "register": "Vn.2S" + "register": "Vm.16B" }, - "n": { - "register": "Vm.S[0]" + "c": { + "register": "Va.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FMLA" + "EOR3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfma_n_f64", + "name": "veor3q_u32", "arguments": [ - "float64x1_t a", - "float64x1_t b", - "float64_t n" + "uint32x4_t a", + "uint32x4_t b", + "uint32x4_t c" ], "return_type": { - "value": "float64x1_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Da" + "register": "Vn.16B" }, "b": { - "register": "Dn" + "register": "Vm.16B" }, - "n": { - "register": "Dm" + "c": { + "register": "Va.16B" } }, "Architectures": [ @@ -30175,35 +224248,30 @@ ], "instructions": [ [ - "FMADD" + "EOR3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmad_lane_f64", + "name": "veor3q_u64", "arguments": [ - "float64_t a", - "float64_t b", - "float64x1_t v", - "const int lane" + "uint64x2_t a", + "uint64x2_t b", + "uint64x2_t c" ], "return_type": { - "value": "float64_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.16B" }, "b": { - "register": "Dn" - }, - "lane": { - "minimum": 0, - "maximum": 0 + "register": "Vm.16B" }, - "v": { - "register": "Vm.1D" + "c": { + "register": "Va.16B" } }, "Architectures": [ @@ -30211,202 +224279,260 @@ ], "instructions": [ [ - "FMLA" + "EOR3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmad_laneq_f64", + "name": "veor3q_u8", "arguments": [ - "float64_t a", - "float64_t b", - "float64x2_t v", - "const int lane" + "uint8x16_t a", + "uint8x16_t b", + "uint8x16_t c" ], "return_type": { - "value": "float64_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.16B" }, "b": { - "register": "Dn" + "register": "Vm.16B" }, - "lane": { - "minimum": 0, - "maximum": 1 + "c": { + "register": "Va.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR3" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "veor_s16", + "arguments": [ + "int16x4_t a", + "int16x4_t b" + ], + "return_type": { + "value": "int16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8B" }, - "v": { - "register": "Vm.2D" + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMLA" + "EOR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmah_f16", + "name": "veor_s32", "arguments": [ - "float16_t a", - "float16_t b", - "float16_t c" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "float16_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Ha" + "register": "Vn.8B" }, "b": { - "register": "Hn" + "register": "Vm.8B" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "EOR" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "veor_s64", + "arguments": [ + "int64x1_t a", + "int64x1_t b" + ], + "return_type": { + "value": "int64x1_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8B" }, - "c": { - "register": "Hm" + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMADD" + "EOR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmah_lane_f16", + "name": "veor_s8", "arguments": [ - "float16_t a", - "float16_t b", - "float16x4_t v", - "const int lane" + "int8x8_t a", + "int8x8_t b" + ], + "return_type": { + "value": "int8x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "EOR" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "veor_u16", + "arguments": [ + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "float16_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Hd" + "register": "Vn.8B" }, "b": { - "register": "Hn" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMLA" + "EOR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmah_laneq_f16", + "name": "veor_u32", "arguments": [ - "float16_t a", - "float16_t b", - "float16x8_t v", - "const int lane" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "float16_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Hd" + "register": "Vn.8B" }, "b": { - "register": "Hn" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMLA" + "EOR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmaq_f16", + "name": "veor_u64", "arguments": [ - "float16x8_t a", - "float16x8_t b", - "float16x8_t c" + "uint64x1_t a", + "uint64x1_t b" ], "return_type": { - "value": "float16x8_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vn.8B" }, "b": { - "register": "Vn.8H" - }, - "c": { - "register": "Vm.8H" + "register": "Vm.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMLA" + "EOR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmaq_f32", + "name": "veor_u8", "arguments": [ - "float32x4_t a", - "float32x4_t b", - "float32x4_t c" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "float32x4_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.8B" }, "b": { - "register": "Vn.4S" - }, - "c": { - "register": "Vm.4S" + "register": "Vm.8B" } }, "Architectures": [ @@ -30416,308 +224542,263 @@ ], "instructions": [ [ - "FMLA" + "EOR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmaq_f64", + "name": "veorq_s16", "arguments": [ - "float64x2_t a", - "float64x2_t b", - "float64x2_t c" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "float64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.16B" }, "b": { - "register": "Vn.2D" - }, - "c": { - "register": "Vm.2D" + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMLA" + "EOR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmaq_lane_f16", + "name": "veorq_s32", "arguments": [ - "float16x8_t a", - "float16x8_t b", - "float16x4_t v", - "const int lane" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "float16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vn.16B" }, "b": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMLA" + "EOR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmaq_lane_f32", + "name": "veorq_s64", "arguments": [ - "float32x4_t a", - "float32x4_t b", - "float32x2_t v", - "const int lane" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "float32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.16B" }, "b": { - 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"vfmlal_lane_high_f16", + "name": "vext_p8", "arguments": [ - "float32x2_t r", - "float16x4_t a", - "float16x4_t b", - "const int lane" + "poly8x8_t a", + "poly8x8_t b", + "const int n" ], "return_type": { - "value": "float32x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 3 + "a": { + "register": "Vn.8B" }, - "r": { - "register": "Vd.2S" + "b": { + "register": "Vm.8B" + }, + "n": { + "minimum": 0, + "maximum": 7 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMLAL2" + "EXT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmlal_lane_low_f16", + "name": "vext_s16", "arguments": [ - "float32x2_t r", - "float16x4_t a", - "float16x4_t b", - "const int lane" + "int16x4_t a", + "int16x4_t b", + "const int n" ], "return_type": { - "value": "float32x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { + "a": { + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" + }, + "n": { "minimum": 0, "maximum": 3 - }, - "r": { - "register": "Vd.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMLAL" + "EXT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmlal_laneq_high_f16", + "name": "vext_s32", "arguments": [ - "float32x2_t r", - "float16x4_t a", - "float16x8_t b", - "const int lane" + "int32x2_t a", + "int32x2_t b", + "const int n" ], "return_type": { - "value": "float32x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 7 + "a": { + "register": "Vn.8B" }, - "r": { - "register": "Vd.2S" + "b": { + "register": "Vm.8B" + }, + "n": { + "minimum": 0, + "maximum": 1 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMLAL2" + "EXT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmlal_laneq_low_f16", + "name": "vext_s64", "arguments": [ - "float32x2_t r", - "float16x4_t a", - "float16x8_t b", - "const int lane" + "int64x1_t a", + "int64x1_t b", + "const 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+ "name": "vext_u16", "arguments": [ - "float32x4_t r", - "float16x8_t a", - "float16x8_t b" + "uint16x4_t a", + "uint16x4_t b", + "const int n" ], "return_type": { - "value": "float32x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.4S" + "a": { + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" + }, + "n": { + "minimum": 0, + "maximum": 3 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMLAL2" + "EXT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmlalq_lane_high_f16", + "name": "vext_u32", "arguments": [ - "float32x4_t r", - "float16x8_t a", - "float16x4_t b", - "const int lane" + "uint32x2_t a", + "uint32x2_t b", + "const int n" ], "return_type": { - "value": "float32x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 3 + "a": { + "register": "Vn.8B" }, - "r": { - "register": "Vd.4S" + "b": { + "register": "Vm.8B" + }, + "n": { + "minimum": 0, + "maximum": 1 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMLAL2" + "EXT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmlalq_lane_low_f16", + "name": "vext_u64", "arguments": [ - "float32x4_t r", - "float16x8_t a", - "float16x4_t b", - "const int lane" + "uint64x1_t a", + "uint64x1_t b", + "const int n" ], "return_type": { - "value": "float32x4_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 3 + "a": { + "register": "Vn.8B" }, - "r": { - "register": "Vd.4S" + "b": { + "register": "Vm.8B" + }, + "n": { + "minimum": 0, + "maximum": 0 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMLAL" + "EXT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmlalq_laneq_high_f16", + "name": "vext_u8", "arguments": [ - "float32x4_t r", - "float16x8_t a", - "float16x8_t b", - "const int lane" + "uint8x8_t a", + "uint8x8_t b", + "const int n" ], "return_type": { - "value": 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r", - "float16x8_t a", - "float16x8_t b" + "float32x4_t a", + "float32x4_t b", + "const int n" ], "return_type": { "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.4S" + "a": { + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" + }, + "n": { + "minimum": 0, + "maximum": 3 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMLAL" + "EXT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmlsl_high_f16", + "name": "vextq_f64", "arguments": [ - "float32x2_t r", - "float16x4_t a", - "float16x4_t b" + "float64x2_t a", + "float64x2_t b", + "const int n" ], "return_type": { - "value": "float32x2_t" + "value": "float64x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.2S" + "a": { + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" + }, + "n": { + "minimum": 0, + "maximum": 1 } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMLSL2" + "EXT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmlsl_lane_high_f16", + "name": "vextq_p16", "arguments": [ - "float32x2_t r", - "float16x4_t a", - "float16x4_t b", - "const int lane" + "poly16x8_t a", + "poly16x8_t b", + "const int n" ], "return_type": { - "value": "float32x2_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 3 + "a": { + "register": "Vn.16B" }, - "r": { - "register": "Vd.2S" + "b": { + "register": "Vm.16B" + }, + "n": { + "minimum": 0, + "maximum": 7 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMLSL2" + "EXT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmlsl_lane_low_f16", + "name": "vextq_p64", "arguments": [ - "float32x2_t r", - "float16x4_t a", - "float16x4_t b", - "const int lane" + "poly64x2_t a", + "poly64x2_t b", + "const int n" ], "return_type": { - "value": "float32x2_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 3 + "a": { + "register": "Vn.16B" }, - "r": { - "register": "Vd.2S" + "b": { + "register": "Vm.16B" + }, + "n": { + "minimum": 0, + "maximum": 1 } }, "Architectures": [ @@ -31300,295 +225414,319 @@ ], "instructions": [ [ - "FMLSL" + "EXT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmlsl_laneq_high_f16", + "name": "vextq_p8", "arguments": [ - "float32x2_t r", - "float16x4_t a", - "float16x8_t b", - "const int lane" + "poly8x16_t a", + "poly8x16_t b", + "const int n" ], "return_type": { - "value": "float32x2_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 7 + "a": { + "register": "Vn.16B" }, - "r": { - "register": "Vd.2S" + "b": { + "register": "Vm.16B" + }, + "n": { + "minimum": 0, + "maximum": 15 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMLSL2" + "EXT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmlsl_laneq_low_f16", + "name": "vextq_s16", "arguments": [ - "float32x2_t r", - "float16x4_t a", - "float16x8_t b", - "const int lane" + "int16x8_t a", + "int16x8_t b", + "const int n" ], "return_type": { - "value": "float32x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { + "a": { + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" + }, + "n": { "minimum": 0, "maximum": 7 - }, - "r": { - "register": "Vd.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMLSL" + "EXT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmlsl_low_f16", + "name": "vextq_s32", "arguments": [ - "float32x2_t r", - "float16x4_t a", - "float16x4_t b" + "int32x4_t a", + "int32x4_t b", + "const int n" ], "return_type": { - "value": "float32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.2S" + "a": { + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" + }, + "n": { + "minimum": 0, + "maximum": 3 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMLSL" + "EXT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmlslq_high_f16", + "name": "vextq_s64", "arguments": [ - "float32x4_t r", - "float16x8_t a", - "float16x8_t b" + "int64x2_t a", + "int64x2_t b", + "const int n" ], "return_type": { - "value": "float32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.4S" + "a": { + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" + }, + "n": { + "minimum": 0, + "maximum": 1 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMLSL2" + "EXT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmlslq_lane_high_f16", + "name": "vextq_s8", "arguments": [ - "float32x4_t r", - "float16x8_t a", - "float16x4_t b", - "const int lane" + "int8x16_t a", + "int8x16_t b", + "const int n" ], "return_type": { - "value": "float32x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 3 + "a": { + "register": "Vn.16B" }, - "r": { - "register": "Vd.4S" + "b": { + "register": "Vm.16B" + }, + "n": { + "minimum": 0, + "maximum": 15 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMLSL2" + "EXT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmlslq_lane_low_f16", + "name": "vextq_u16", "arguments": [ - "float32x4_t r", - "float16x8_t a", - "float16x4_t b", - "const int lane" + "uint16x8_t a", + "uint16x8_t b", + "const int n" ], "return_type": { - "value": "float32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 3 + "a": { + "register": "Vn.16B" }, - "r": { - "register": "Vd.4S" + "b": { + "register": "Vm.16B" + }, + "n": { + "minimum": 0, + "maximum": 7 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMLSL" + "EXT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmlslq_laneq_high_f16", + "name": "vextq_u32", "arguments": [ - "float32x4_t r", - "float16x8_t a", - "float16x8_t b", - "const int lane" + "uint32x4_t a", + "uint32x4_t b", + "const int n" ], "return_type": { - "value": "float32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 7 + "a": { + "register": "Vn.16B" }, - "r": { - "register": "Vd.4S" + "b": { + "register": "Vm.16B" + }, + "n": { + "minimum": 0, + "maximum": 3 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMLSL2" + "EXT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmlslq_laneq_low_f16", + "name": "vextq_u64", "arguments": [ - "float32x4_t r", - "float16x8_t a", - "float16x8_t b", - "const int lane" + "uint64x2_t a", + "uint64x2_t b", + "const int n" ], "return_type": { - "value": "float32x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 7 + "a": { + "register": "Vn.16B" }, - "r": { - "register": "Vd.4S" + "b": { + "register": "Vm.16B" + }, + "n": { + "minimum": 0, + "maximum": 1 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMLSL" + "EXT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmlslq_low_f16", + "name": "vextq_u8", "arguments": [ - "float32x4_t r", - "float16x8_t a", - "float16x8_t b" + "uint8x16_t a", + "uint8x16_t b", + "const int n" ], "return_type": { - "value": "float32x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.4S" + "a": { + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" + }, + "n": { + "minimum": 0, + "maximum": 15 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMLSL" + "EXT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfms_f16", + "name": "vfma_f16", "arguments": [ "float16x4_t a", "float16x4_t b", @@ -31614,13 +225752,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfms_f32", + "name": "vfma_f32", "arguments": [ "float32x2_t a", "float32x2_t b", @@ -31647,13 +225785,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfms_f64", + "name": "vfma_f64", "arguments": [ "float64x1_t a", "float64x1_t b", @@ -31678,13 +225816,13 @@ ], "instructions": [ [ - "FMSUB" + "FMADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfms_lane_f16", + "name": "vfma_lane_f16", "arguments": [ "float16x4_t a", "float16x4_t b", @@ -31714,13 +225852,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfms_lane_f32", + "name": "vfma_lane_f32", "arguments": [ "float32x2_t a", "float32x2_t b", @@ -31750,13 +225888,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfms_lane_f64", + "name": "vfma_lane_f64", "arguments": [ "float64x1_t a", "float64x1_t b", @@ -31786,13 +225924,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfms_laneq_f16", + "name": "vfma_laneq_f16", "arguments": [ "float16x4_t a", "float16x4_t b", @@ -31822,13 +225960,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfms_laneq_f32", + "name": "vfma_laneq_f32", "arguments": [ "float32x2_t a", "float32x2_t b", @@ -31858,13 +225996,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfms_laneq_f64", + "name": "vfma_laneq_f64", "arguments": [ "float64x1_t a", "float64x1_t b", @@ -31894,13 +226032,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfms_n_f16", + "name": "vfma_n_f16", "arguments": [ "float16x4_t a", "float16x4_t b", @@ -31911,7 +226049,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.4H " + "register": "Vd.4H" }, "b": { "register": "Vn.4H" @@ -31925,13 +226063,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfms_n_f32", + "name": "vfma_n_f32", "arguments": [ "float32x2_t a", "float32x2_t b", @@ -31952,17 +226090,19 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfms_n_f64", + "name": "vfma_n_f64", "arguments": [ "float64x1_t a", "float64x1_t b", @@ -31987,13 +226127,13 @@ ], "instructions": [ [ - "FMSUB" + "FMADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmsd_lane_f64", + "name": "vfmad_lane_f64", "arguments": [ "float64_t a", "float64_t b", @@ -32023,13 +226163,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmsd_laneq_f64", + "name": "vfmad_laneq_f64", "arguments": [ "float64_t a", "float64_t b", @@ -32059,13 +226199,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmsh_f16", + "name": "vfmah_f16", "arguments": [ "float16_t a", "float16_t b", @@ -32091,13 +226231,13 @@ ], "instructions": [ [ - "FMSUB" + "FMADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmsh_lane_f16", + "name": "vfmah_lane_f16", "arguments": [ "float16_t a", "float16_t b", @@ -32127,13 +226267,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmsh_laneq_f16", + "name": "vfmah_laneq_f16", "arguments": [ "float16_t a", "float16_t b", @@ -32163,13 +226303,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmsq_f16", + "name": "vfmaq_f16", "arguments": [ "float16x8_t a", "float16x8_t b", @@ -32195,13 +226335,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmsq_f32", + "name": "vfmaq_f32", "arguments": [ "float32x4_t a", "float32x4_t b", @@ -32228,13 +226368,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmsq_f64", + "name": "vfmaq_f64", "arguments": [ "float64x2_t a", "float64x2_t b", @@ -32259,13 +226399,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmsq_lane_f16", + "name": "vfmaq_lane_f16", "arguments": [ "float16x8_t a", "float16x8_t b", @@ -32295,13 +226435,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmsq_lane_f32", + "name": "vfmaq_lane_f32", "arguments": [ "float32x4_t a", "float32x4_t b", @@ -32331,13 +226471,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmsq_lane_f64", + "name": "vfmaq_lane_f64", "arguments": [ "float64x2_t a", "float64x2_t b", @@ -32367,13 +226507,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmsq_laneq_f16", + "name": "vfmaq_laneq_f16", "arguments": [ "float16x8_t a", "float16x8_t b", @@ -32403,13 +226543,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmsq_laneq_f32", + "name": "vfmaq_laneq_f32", "arguments": [ "float32x4_t a", "float32x4_t b", @@ -32439,13 +226579,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmsq_laneq_f64", + "name": "vfmaq_laneq_f64", "arguments": [ "float64x2_t a", "float64x2_t b", @@ -32475,13 +226615,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmsq_n_f16", + "name": "vfmaq_n_f16", "arguments": [ "float16x8_t a", "float16x8_t b", @@ -32492,7 +226632,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.8H " + "register": "Vd.8H" }, "b": { "register": "Vn.8H" @@ -32506,13 +226646,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmsq_n_f32", + "name": "vfmaq_n_f32", "arguments": [ "float32x4_t a", "float32x4_t b", @@ -32533,17 +226673,19 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmsq_n_f64", + "name": "vfmaq_n_f64", "arguments": [ "float64x2_t a", "float64x2_t b", @@ -32568,13 +226710,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmss_lane_f32", + "name": "vfmas_lane_f32", "arguments": [ "float32_t a", "float32_t b", @@ -32604,13 +226746,13 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vfmss_laneq_f32", + "name": "vfmas_laneq_f32", "arguments": [ "float32_t a", "float32_t b", @@ -32640,120 +226782,178 @@ ], "instructions": [ [ - "FMLS" + "FMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_high_f16", + "name": "vfmlal_high_f16", "arguments": [ - "float16x8_t a" + "float32x2_t r", + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "float16x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.2H" + }, + "b": { + "register": "Vd.2H" + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_high_f32", + "name": "vfmlal_lane_high_f16", "arguments": [ - "float32x4_t a" + "float32x2_t r", + "float16x4_t a", + "float16x4_t b", + "const int lane" ], "return_type": { "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_high_f64", + "name": "vfmlal_lane_low_f16", "arguments": [ - "float64x2_t a" + "float32x2_t r", + "float16x4_t a", + "float16x4_t b", + "const int lane" ], "return_type": { - "value": "float64x1_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_high_p16", + "name": "vfmlal_laneq_high_f16", "arguments": [ - "poly16x8_t a" + "float32x2_t r", + "float16x4_t a", + "float16x8_t b", + "const int lane" ], "return_type": { - "value": "poly16x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_high_p64", + "name": "vfmlal_laneq_low_f16", "arguments": [ - "poly64x2_t a" + "float32x2_t r", + "float16x4_t a", + "float16x8_t b", + "const int lane" ], "return_type": { - "value": "poly64x1_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ @@ -32762,370 +226962,666 @@ ], "instructions": [ [ - "DUP" + "FMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_high_p8", + "name": "vfmlal_low_f16", "arguments": [ - "poly8x16_t a" + "float32x2_t r", + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vd.2H" + }, + "b": { + "register": "Vd.2H" + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_high_s16", + "name": "vfmlalq_high_f16", + "arguments": [ + "float32x4_t r", + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vd.4H" + }, + "r": { + "register": "Vd.4S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLAL2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlalq_lane_high_f16", + "arguments": [ + "float32x4_t r", + "float16x8_t a", + "float16x4_t b", + "const int lane" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.4S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLAL2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlalq_lane_low_f16", + "arguments": [ + "float32x4_t r", + "float16x8_t a", + "float16x4_t b", + "const int lane" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.4S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLAL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlalq_laneq_high_f16", + "arguments": [ + "float32x4_t r", + "float16x8_t a", + "float16x8_t b", + "const int lane" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.4S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLAL2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlalq_laneq_low_f16", + "arguments": [ + "float32x4_t r", + "float16x8_t a", + "float16x8_t b", + "const int lane" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.4S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLAL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlalq_low_f16", "arguments": [ - "int16x8_t a" + "float32x4_t r", + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "int16x4_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.4H" + }, + "b": { + "register": "Vd.4H" + }, + "r": { + "register": "Vd.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_high_s32", + "name": "vfmlsl_high_f16", "arguments": [ - "int32x4_t a" + "float32x2_t r", + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "int32x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.2H" + }, + "b": { + "register": "Vd.2H" + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_high_s64", + "name": "vfmlsl_lane_high_f16", "arguments": [ - "int64x2_t a" + "float32x2_t r", + "float16x4_t a", + "float16x4_t b", + "const int lane" ], "return_type": { - "value": "int64x1_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_high_s8", + "name": "vfmlsl_lane_low_f16", "arguments": [ - "int8x16_t a" + "float32x2_t r", + "float16x4_t a", + "float16x4_t b", + "const int lane" ], "return_type": { - "value": "int8x8_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_high_u16", + "name": "vfmlsl_laneq_high_f16", "arguments": [ - "uint16x8_t a" + "float32x2_t r", + "float16x4_t a", + "float16x8_t b", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_high_u32", + "name": "vfmlsl_laneq_low_f16", "arguments": [ - "uint32x4_t a" + "float32x2_t r", + "float16x4_t a", + "float16x8_t b", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_high_u64", + "name": "vfmlsl_low_f16", "arguments": [ - "uint64x2_t a" + "float32x2_t r", + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "uint64x1_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.2H" + }, + "b": { + "register": "Vd.2H" + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_high_u8", + "name": "vfmlslq_high_f16", "arguments": [ - "uint8x16_t a" + "float32x4_t r", + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vd.4H" + }, + "b": { + "register": "Vd.4H" + }, + "r": { + "register": "Vd.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_lane_f16", + "name": "vfmlslq_lane_high_f16", "arguments": [ - "float16x4_t v", + "float32x4_t r", + "float16x8_t a", + "float16x4_t b", "const int lane" ], "return_type": { - "value": "float16_t" + "value": "float32x4_t" }, "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 }, - "v": { - "register": "Vn.4H" + "r": { + "register": "Vd.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_lane_f32", + "name": "vfmlslq_lane_low_f16", "arguments": [ - "float32x2_t v", + "float32x4_t r", + "float16x8_t a", + "float16x4_t b", "const int lane" ], "return_type": { - "value": "float32_t" + "value": "float32x4_t" }, "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, - "maximum": 1 + "maximum": 3 }, - "v": { - "register": "Vn.2S" + "r": { + "register": "Vd.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_lane_f64", + "name": "vfmlslq_laneq_high_f16", "arguments": [ - "float64x1_t v", + "float32x4_t r", + "float16x8_t a", + "float16x8_t b", "const int lane" ], "return_type": { - "value": "float64_t" + "value": "float32x4_t" }, "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, - "maximum": 0 + "maximum": 7 }, - "v": { - "register": "Vn.1D" + "r": { + "register": "Vd.4S" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_lane_p16", + "name": "vfmlslq_laneq_low_f16", "arguments": [ - "poly16x4_t v", + "float32x4_t r", + "float16x8_t a", + "float16x8_t b", "const int lane" ], "return_type": { - "value": "poly16_t" + "value": "float32x4_t" }, "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, - "v": { - "register": "Vn.4H" + "r": { + "register": "Vd.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "UMOV" + "FMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_lane_p64", + "name": "vfmlslq_low_f16", "arguments": [ - "poly64x1_t v", - "const int lane" + "float32x4_t r", + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "poly64_t" + "value": "float32x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "a": { + "register": "Vd.4H" }, - "v": { - "register": "Vn.1D" + "b": { + "register": "Vd.4H" + }, + "r": { + "register": "Vd.4S" } }, "Architectures": [ @@ -33134,57 +227630,62 @@ ], "instructions": [ [ - "UMOV" + "FMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_lane_p8", + "name": "vfms_f16", "arguments": [ - "poly8x8_t v", - "const int lane" + "float16x4_t a", + "float16x4_t b", + "float16x4_t c" ], "return_type": { - "value": "poly8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "a": { + "register": "Vd.4H" }, - "v": { - "register": "Vn.8B" + "b": { + "register": "Vn.4H" + }, + "c": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "UMOV" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_lane_s16", + "name": "vfms_f32", "arguments": [ - "int16x4_t v", - "const int lane" + "float32x2_t a", + "float32x2_t b", + "float32x2_t c" ], "return_type": { - "value": "int16_t" + "value": "float32x2_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "a": { + "register": "Vd.2S" }, - "v": { - "register": "Vn.4H" + "b": { + "register": "Vn.2S" + }, + "c": { + "register": "Vm.2S" } }, "Architectures": [ @@ -33194,282 +227695,339 @@ ], "instructions": [ [ - "SMOV" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_lane_s32", + "name": "vfms_f64", "arguments": [ - "int32x2_t v", - "const int lane" + "float64x1_t a", + "float64x1_t b", + "float64x1_t c" ], "return_type": { - "value": "int32_t" + "value": "float64x1_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "a": { + "register": "Da" }, - "v": { - "register": "Vn.2S" + "b": { + "register": "Dn" + }, + "c": { + "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMOV" + "FMSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_lane_s64", + "name": "vfms_lane_f16", "arguments": [ - "int64x1_t v", + "float16x4_t a", + "float16x4_t b", + "float16x4_t v", "const int lane" ], "return_type": { - "value": "int64_t" + "value": "float16x4_t" }, "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vn.4H" + }, "lane": { "minimum": 0, - "maximum": 0 + "maximum": 3 }, "v": { - "register": "Vn.1D" + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMOV" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_lane_s8", + "name": "vfms_lane_f32", "arguments": [ - "int8x8_t v", + "float32x2_t a", + "float32x2_t b", + "float32x2_t v", "const int lane" ], "return_type": { - "value": "int8_t" + "value": "float32x2_t" }, "Arguments_Preparation": { + "a": { + "register": "Vd.2S" + }, + "b": { + "register": "Vn.2S" + }, "lane": { "minimum": 0, - "maximum": 7 + "maximum": 1 }, "v": { - "register": "Vn.8B" + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMOV" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_lane_u16", + "name": "vfms_lane_f64", "arguments": [ - "uint16x4_t v", + "float64x1_t a", + "float64x1_t b", + "float64x1_t v", "const int lane" ], "return_type": { - "value": "uint16_t" + "value": "float64x1_t" }, "Arguments_Preparation": { + "a": { + "register": "Dd" + }, + "b": { + "register": "Dn" + }, "lane": { "minimum": 0, - "maximum": 3 + "maximum": 0 }, "v": { - "register": "Vn.4H" + "register": "Vm.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMOV" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_lane_u32", + "name": "vfms_laneq_f16", "arguments": [ - "uint32x2_t v", + "float16x4_t a", + "float16x4_t b", + "float16x8_t v", "const int lane" ], "return_type": { - "value": "uint32_t" + "value": "float16x4_t" }, "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vn.4H" + }, "lane": { "minimum": 0, - "maximum": 1 + "maximum": 7 }, "v": { - "register": "Vn.2S" + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMOV" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_lane_u64", + "name": "vfms_laneq_f32", "arguments": [ - "uint64x1_t v", + "float32x2_t a", + "float32x2_t b", + "float32x4_t v", "const int lane" ], "return_type": { - "value": "uint64_t" + "value": "float32x2_t" }, "Arguments_Preparation": { + "a": { + "register": "Vd.2S" + }, + "b": { + "register": "Vn.2S" + }, "lane": { "minimum": 0, - "maximum": 0 + "maximum": 3 }, "v": { - "register": "Vn.1D" + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMOV" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_lane_u8", + "name": "vfms_laneq_f64", "arguments": [ - "uint8x8_t v", + "float64x1_t a", + "float64x1_t b", + "float64x2_t v", "const int lane" ], "return_type": { - "value": "uint8_t" + "value": "float64x1_t" }, "Arguments_Preparation": { + "a": { + "register": "Dd" + }, + "b": { + "register": "Dn" + }, "lane": { "minimum": 0, - "maximum": 7 + "maximum": 1 }, "v": { - "register": "Vn.8B" + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMOV" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_low_f16", + "name": "vfms_n_f16", "arguments": [ - "float16x8_t a" + "float16x4_t a", + "float16x4_t b", + "float16_t n" ], "return_type": { "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.4H" + }, + "b": { + "register": "Vn.4H" + }, + "n": { + "register": "Vm.H[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_low_f32", + "name": "vfms_n_f32", "arguments": [ - "float32x4_t a" + "float32x2_t a", + "float32x2_t b", + "float32_t n" ], "return_type": { "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.2S" + }, + "b": { + "register": "Vn.2S" + }, + "n": { + "register": "Vm.S[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_low_f64", + "name": "vfms_n_f64", "arguments": [ - "float64x2_t a" + "float64x1_t a", + "float64x1_t b", + "float64_t n" ], "return_type": { "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Da" + }, + "b": { + "register": "Dn" + }, + "n": { + "register": "Dm" } }, "Architectures": [ @@ -33477,171 +228035,238 @@ ], "instructions": [ [ - "DUP" + "FMSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_low_p16", + "name": "vfmsd_lane_f64", "arguments": [ - "poly16x8_t a" + "float64_t a", + "float64_t b", + "float64x1_t v", + "const int lane" ], "return_type": { - "value": "poly16x4_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Dd" + }, + "b": { + "register": "Dn" + }, + "lane": { + "minimum": 0, + "maximum": 0 + }, + "v": { + "register": "Vm.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_low_p64", + "name": "vfmsd_laneq_f64", "arguments": [ - "poly64x2_t a" + "float64_t a", + "float64_t b", + "float64x2_t v", + "const int lane" ], "return_type": { - "value": "poly64x1_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Dd" + }, + "b": { + "register": "Dn" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_low_p8", + "name": "vfmsh_f16", "arguments": [ - "poly8x16_t a" + "float16_t a", + "float16_t b", + "float16_t c" ], "return_type": { - "value": "poly8x8_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Ha" + }, + "b": { + "register": "Hn" + }, + "c": { + "register": "Hm" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "DUP" + "FMSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_low_s16", + "name": "vfmsh_lane_f16", "arguments": [ - "int16x8_t a" + "float16_t a", + "float16_t b", + "float16x4_t v", + "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Hd" + }, + "b": { + "register": "Hn" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_low_s32", + "name": "vfmsh_laneq_f16", "arguments": [ - "int32x4_t a" + "float16_t a", + "float16_t b", + "float16x8_t v", + "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Hd" + }, + "b": { + "register": "Hn" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_low_s64", + "name": "vfmsq_f16", "arguments": [ - "int64x2_t a" + "float16x8_t a", + "float16x8_t b", + "float16x8_t c" ], "return_type": { - "value": "int64x1_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.8H" + }, + "b": { + "register": "Vn.8H" + }, + "c": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_low_s8", + "name": "vfmsq_f32", "arguments": [ - "int8x16_t a" + "float32x4_t a", + "float32x4_t b", + "float32x4_t c" ], "return_type": { - "value": "int8x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" } }, "Architectures": [ @@ -33651,187 +228276,246 @@ ], "instructions": [ [ - "DUP" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_low_u16", + "name": "vfmsq_f64", "arguments": [ - "uint16x8_t a" + "float64x2_t a", + "float64x2_t b", + "float64x2_t c" ], "return_type": { - "value": "uint16x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.2D" + }, + "c": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_low_u32", + "name": "vfmsq_lane_f16", "arguments": [ - "uint32x4_t a" + "float16x8_t a", + "float16x8_t b", + "float16x4_t v", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.8H" + }, + "b": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_low_u64", + "name": "vfmsq_lane_f32", "arguments": [ - "uint64x2_t a" + "float32x4_t a", + "float32x4_t b", + "float32x2_t v", + "const int lane" ], "return_type": { - "value": "uint64x1_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vget_low_u8", + "name": "vfmsq_lane_f64", "arguments": [ - "uint8x16_t a" + "float64x2_t a", + "float64x2_t b", + "float64x1_t v", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.2D" + }, + "lane": { + "minimum": 0, + "maximum": 0 + }, + "v": { + "register": "Vm.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vgetq_lane_f16", + "name": "vfmsq_laneq_f16", "arguments": [ + "float16x8_t a", + "float16x8_t b", "float16x8_t v", "const int lane" ], "return_type": { - "value": "float16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + }, + "b": { + "register": "Vn.8H" + }, "lane": { "minimum": 0, "maximum": 7 }, "v": { - "register": "Vn.8H" + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vgetq_lane_f32", + "name": "vfmsq_laneq_f32", "arguments": [ + "float32x4_t a", + "float32x4_t b", "float32x4_t v", "const int lane" ], "return_type": { - "value": "float32_t" + "value": "float32x4_t" }, "Arguments_Preparation": { + "a": { + "register": "Vd.4S" + }, + "b": { + "register": "Vn.4S" + }, "lane": { "minimum": 0, "maximum": 3 }, "v": { - "register": "Vn.4S" + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vgetq_lane_f64", + "name": "vfmsq_laneq_f64", "arguments": [ + "float64x2_t a", + "float64x2_t b", "float64x2_t v", "const int lane" ], "return_type": { - "value": "float64_t" + "value": "float64x2_t" }, "Arguments_Preparation": { + "a": { + "register": "Vd.2D" + }, + "b": { + "register": "Vn.2D" + }, "lane": { "minimum": 0, "maximum": 1 }, "v": { - "register": "Vn.2D" + "register": "Vm.2D" } }, "Architectures": [ @@ -33839,176 +228523,187 @@ ], "instructions": [ [ - "DUP" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vgetq_lane_p16", + "name": "vfmsq_n_f16", "arguments": [ - "poly16x8_t v", - "const int lane" + "float16x8_t a", + "float16x8_t b", + "float16_t n" ], "return_type": { - "value": "poly16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "a": { + "register": "Vd.8H" }, - "v": { + "b": { "register": "Vn.8H" + }, + "n": { + "register": "Vm.H[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMOV" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vgetq_lane_p64", + "name": "vfmsq_n_f32", "arguments": [ - "poly64x2_t v", - "const int lane" + "float32x4_t a", + "float32x4_t b", + "float32_t n" ], "return_type": { - "value": "poly64_t" + "value": "float32x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "a": { + "register": "Vd.4S" }, - "v": { - "register": "Vn.2D" + "b": { + "register": "Vn.4S" + }, + "n": { + "register": "Vm.S[0]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "UMOV" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vgetq_lane_p8", + "name": "vfmsq_n_f64", "arguments": [ - "poly8x16_t v", - "const int lane" + "float64x2_t a", + "float64x2_t b", + "float64_t n" ], "return_type": { - "value": "poly8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 + "a": { + "register": "Vd.2D" }, - "v": { - "register": "Vn.16B" + "b": { + "register": "Vn.2D" + }, + "n": { + "register": "Vm.D[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMOV" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vgetq_lane_s16", + "name": "vfmss_lane_f32", "arguments": [ - "int16x8_t v", + "float32_t a", + "float32_t b", + "float32x2_t v", "const int lane" ], "return_type": { - "value": "int16_t" + "value": "float32_t" }, "Arguments_Preparation": { + "a": { + "register": "Sd" + }, + "b": { + "register": "Sn" + }, "lane": { "minimum": 0, - "maximum": 7 + "maximum": 1 }, "v": { - "register": "Vn.8H" + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMOV" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vgetq_lane_s32", + "name": "vfmss_laneq_f32", "arguments": [ - "int32x4_t v", + "float32_t a", + "float32_t b", + "float32x4_t v", "const int lane" ], "return_type": { - "value": "int32_t" + "value": "float32_t" }, "Arguments_Preparation": { + "a": { + "register": "Sd" + }, + "b": { + "register": "Sn" + }, "lane": { "minimum": 0, "maximum": 3 }, "v": { - "register": "Vn.4S" + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMOV" + "FMLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vgetq_lane_s64", + "name": "vget_high_f16", "arguments": [ - "int64x2_t v", - "const int lane" + "float16x8_t a" ], "return_type": { - "value": "int64_t" + "value": "float16x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vn.2D" + "a": { + "register": "Vn.8H" } }, "Architectures": [ @@ -34018,27 +228713,22 @@ ], "instructions": [ [ - "UMOV" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vgetq_lane_s8", + "name": "vget_high_f32", "arguments": [ - "int8x16_t v", - "const int lane" + "float32x4_t a" ], "return_type": { - "value": "int8_t" + "value": "float32x2_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 - }, - "v": { - "register": "Vn.16B" + "a": { + "register": "Vn.4S" } }, "Architectures": [ @@ -34048,26 +228738,44 @@ ], "instructions": [ [ - "SMOV" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vgetq_lane_u16", + "name": "vget_high_f64", "arguments": [ - "uint16x8_t v", - "const int lane" + "float64x2_t a" ], "return_type": { - "value": "uint16_t" + "value": "float64x1_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { + "a": { + "register": "Vn.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vget_high_p16", + "arguments": [ + "poly16x8_t a" + ], + "return_type": { + "value": "poly16x4_t" + }, + "Arguments_Preparation": { + "a": { "register": "Vn.8H" } }, @@ -34078,57 +228786,46 @@ ], "instructions": [ [ - "UMOV" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vgetq_lane_u32", + "name": "vget_high_p64", "arguments": [ - "uint32x4_t v", - "const int lane" + "poly64x2_t a" ], "return_type": { - "value": "uint32_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vn.4S" + "a": { + "register": "Vn.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "UMOV" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vgetq_lane_u64", + "name": "vget_high_p8", "arguments": [ - "uint64x2_t v", - "const int lane" + "poly8x16_t a" ], "return_type": { - "value": "uint64_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vn.2D" + "a": { + "register": "Vn.16B" } }, "Architectures": [ @@ -34138,27 +228835,22 @@ ], "instructions": [ [ - "UMOV" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vgetq_lane_u8", + "name": "vget_high_s16", "arguments": [ - "uint8x16_t v", - "const int lane" + "int16x8_t a" ], "return_type": { - "value": "uint8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 - }, - "v": { - "register": "Vn.16B" + "a": { + "register": "Vn.8H" } }, "Architectures": [ @@ -34168,26 +228860,22 @@ ], "instructions": [ [ - "UMOV" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhadd_s16", + "name": "vget_high_s32", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "int32x4_t a" ], "return_type": { - "value": "int16x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "register": "Vn.4S" } }, "Architectures": [ @@ -34197,26 +228885,22 @@ ], "instructions": [ [ - "SHADD" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhadd_s32", + "name": "vget_high_s64", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "int64x2_t a" ], "return_type": { - "value": "int32x2_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" + "register": "Vn.2D" } }, "Architectures": [ @@ -34226,26 +228910,22 @@ ], "instructions": [ [ - "SHADD" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhadd_s8", + "name": "vget_high_s8", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "int8x16_t a" ], "return_type": { "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" + "register": "Vn.16B" } }, "Architectures": [ @@ -34255,26 +228935,22 @@ ], "instructions": [ [ - "SHADD" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhadd_u16", + "name": "vget_high_u16", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "uint16x8_t a" ], "return_type": { "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "register": "Vn.8H" } }, "Architectures": [ @@ -34284,26 +228960,22 @@ ], "instructions": [ [ - "UHADD" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhadd_u32", + "name": "vget_high_u32", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "uint32x4_t a" ], "return_type": { "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" + "register": "Vn.4S" } }, "Architectures": [ @@ -34313,26 +228985,22 @@ ], "instructions": [ [ - "UHADD" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhadd_u8", + "name": "vget_high_u64", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "uint64x2_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" + "register": "Vn.2D" } }, "Architectures": [ @@ -34342,26 +229010,22 @@ ], "instructions": [ [ - "UHADD" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhaddq_s16", + "name": "vget_high_u8", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "uint8x16_t a" ], "return_type": { - "value": "int16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Vn.16B" } }, "Architectures": [ @@ -34371,26 +229035,27 @@ ], "instructions": [ [ - "SHADD" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhaddq_s32", + "name": "vget_lane_f16", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "float16x4_t v", + "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "float16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.4S" + "v": { + "register": "Vn.4H" } }, "Architectures": [ @@ -34400,26 +229065,27 @@ ], "instructions": [ [ - "SHADD" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhaddq_s8", + "name": "vget_lane_f32", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "float32x2_t v", + "const int lane" ], "return_type": { - "value": "int8x16_t" + "value": "float32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.16B" + "v": { + "register": "Vn.2S" } }, "Architectures": [ @@ -34429,55 +229095,55 @@ ], "instructions": [ [ - "SHADD" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhaddq_u16", + "name": "vget_lane_f64", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "float64x1_t v", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "float64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "lane": { + "minimum": 0, + "maximum": 0 }, - "b": { - "register": "Vm.8H" + "v": { + "register": "Vn.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UHADD" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhaddq_u32", + "name": "vget_lane_p16", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "poly16x4_t v", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "poly16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.4S" + "v": { + "register": "Vn.4H" } }, "Architectures": [ @@ -34487,55 +229153,56 @@ ], "instructions": [ [ - "UHADD" + "UMOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhaddq_u8", + "name": "vget_lane_p64", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "poly64x1_t v", + "const int lane" ], "return_type": { - "value": "uint8x16_t" + "value": "poly64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 0 }, - "b": { - "register": "Vm.16B" + "v": { + "register": "Vn.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "UHADD" + "UMOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhsub_s16", + "name": "vget_lane_p8", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "poly8x8_t v", + "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "poly8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.4H" + "v": { + "register": "Vn.8B" } }, "Architectures": [ @@ -34545,26 +229212,27 @@ ], "instructions": [ [ - "SHSUB" + "UMOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhsub_s32", + "name": "vget_lane_s16", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "int16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.2S" + "v": { + "register": "Vn.4H" } }, "Architectures": [ @@ -34574,26 +229242,27 @@ ], "instructions": [ [ - "SHSUB" + "SMOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhsub_s8", + "name": "vget_lane_s32", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "int8x8_t" + "value": "int32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.8B" + "v": { + "register": "Vn.2S" } }, "Architectures": [ @@ -34603,26 +229272,27 @@ ], "instructions": [ [ - "SHSUB" + "SMOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhsub_u16", + "name": "vget_lane_s64", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "int64x1_t v", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "int64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 0 }, - "b": { - "register": "Vm.4H" + "v": { + "register": "Vn.1D" } }, "Architectures": [ @@ -34632,26 +229302,27 @@ ], "instructions": [ [ - "UHSUB" + "UMOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhsub_u32", + "name": "vget_lane_s8", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "int8x8_t v", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "int8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.2S" + "v": { + "register": "Vn.8B" } }, "Architectures": [ @@ -34661,26 +229332,27 @@ ], "instructions": [ [ - "UHSUB" + "SMOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhsub_u8", + "name": "vget_lane_u16", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "uint16x4_t v", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "uint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.8B" + "v": { + "register": "Vn.4H" } }, "Architectures": [ @@ -34690,26 +229362,27 @@ ], "instructions": [ [ - "UHSUB" + "UMOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhsubq_s16", + "name": "vget_lane_u32", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "uint32x2_t v", + "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "uint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.8H" + "v": { + "register": "Vn.2S" } }, "Architectures": [ @@ -34719,26 +229392,27 @@ ], "instructions": [ [ - "SHSUB" + "UMOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhsubq_s32", + "name": "vget_lane_u64", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "uint64x1_t v", + "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "uint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "lane": { + "minimum": 0, + "maximum": 0 }, - "b": { - "register": "Vm.4S" + "v": { + "register": "Vn.1D" } }, "Architectures": [ @@ -34748,26 +229422,27 @@ ], "instructions": [ [ - "SHSUB" + "UMOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhsubq_s8", + "name": "vget_lane_u8", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "uint8x8_t v", + "const int lane" ], "return_type": { - "value": "int8x16_t" + "value": "uint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.16B" + "v": { + "register": "Vn.8B" } }, "Architectures": [ @@ -34777,26 +229452,22 @@ ], "instructions": [ [ - "SHSUB" + "UMOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhsubq_u16", + "name": "vget_low_f16", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "float16x8_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" } }, "Architectures": [ @@ -34806,26 +229477,22 @@ ], "instructions": [ [ - "UHSUB" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhsubq_u32", + "name": "vget_low_f32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "float32x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" } }, "Architectures": [ @@ -34835,275 +229502,219 @@ ], "instructions": [ [ - "UHSUB" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vhsubq_u8", + "name": "vget_low_f64", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "float64x2_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UHSUB" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vldap1_lane_u64", + "name": "vget_low_p16", "arguments": [ - "uint64_t const * ptr", - "uint64x1_t src", - "const int lane" + "poly16x8_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.1D" + "a": { + "register": "Vn.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LDAP1" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vldap1_lane_s64", + "name": "vget_low_p64", "arguments": [ - "int64_t const * ptr", - "int64x1_t src", - "const int lane" + "poly64x2_t a" ], "return_type": { - "value": "int64x1_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.1D" + "a": { + "register": "Vn.2D" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "LDAP1" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vldap1q_lane_u64", + "name": "vget_low_p8", "arguments": [ - "uint64_t const * ptr", - "uint64x2_t src", - "const int lane" + "poly8x16_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.2D" + "a": { + "register": "Vn.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LDAP1" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vldap1q_lane_s64", + "name": "vget_low_s16", "arguments": [ - "int64_t const * ptr", - "int64x2_t src", - "const int lane" + "int16x8_t a" ], "return_type": { - "value": "int64x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.2D" + "a": { + "register": "Vn.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LDAP1" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vldap1_lane_p64", + "name": "vget_low_s32", "arguments": [ - "poly64_t const * ptr", - "poly64x1_t src", - "const int lane" + "int32x4_t a" ], "return_type": { - "value": "poly64x1_t" + "value": "int32x2_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.1D" + "a": { + "register": "Vn.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LDAP1" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vldap1q_lane_p64", + "name": "vget_low_s64", "arguments": [ - "poly64_t const * ptr", - "poly64x2_t src", - "const int lane" + "int64x2_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "int64x1_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.2D" + "a": { + "register": "Vn.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LDAP1" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vldap1q_lane_f64", + "name": "vget_low_s8", "arguments": [ - "float64_t const * ptr", - "float64x2_t src", - "const int lane" + "int8x16_t a" ], "return_type": { - "value": "float64x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.2D" + "a": { + "register": "Vn.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LDAP1" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_dup_f16", + "name": "vget_low_u16", "arguments": [ - "float16_t const * ptr" + "uint16x8_t a" ], "return_type": { - "value": "float16x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.8H" } }, "Architectures": [ @@ -35113,22 +229724,22 @@ ], "instructions": [ [ - "LD1R" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_dup_f32", + "name": "vget_low_u32", "arguments": [ - "float32_t const * ptr" + "uint32x4_t a" ], "return_type": { - "value": "float32x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.4S" } }, "Architectures": [ @@ -35138,45 +229749,47 @@ ], "instructions": [ [ - "LD1R" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_dup_f64", + "name": "vget_low_u64", "arguments": [ - "float64_t const * ptr" + "uint64x2_t a" ], "return_type": { - "value": "float64x1_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LD1" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_dup_p16", + "name": "vget_low_u8", "arguments": [ - "poly16_t const * ptr" + "uint8x16_t a" ], "return_type": { - "value": "poly16x4_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.16B" } }, "Architectures": [ @@ -35186,46 +229799,57 @@ ], "instructions": [ [ - "LD1R" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_dup_p64", + "name": "vgetq_lane_f16", "arguments": [ - "poly64_t const * ptr" + "float16x8_t v", + "const int lane" ], "return_type": { - "value": "poly64x1_t" + "value": "float16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vn.8H" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "LD1" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_dup_p8", + "name": "vgetq_lane_f32", "arguments": [ - "poly8_t const * ptr" + "float32x4_t v", + "const int lane" ], "return_type": { - "value": "poly8x8_t" + "value": "float32_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vn.4S" } }, "Architectures": [ @@ -35235,47 +229859,55 @@ ], "instructions": [ [ - "LD1R" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_dup_s16", + "name": "vgetq_lane_f64", "arguments": [ - "int16_t const * ptr" + "float64x2_t v", + "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "float64_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "LD1R" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_dup_s32", + "name": "vgetq_lane_p16", "arguments": [ - "int32_t const * ptr" + "poly16x8_t v", + "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "poly16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vn.8H" } }, "Architectures": [ @@ -35285,47 +229917,56 @@ ], "instructions": [ [ - "LD1R" + "UMOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_dup_s64", + "name": "vgetq_lane_p64", "arguments": [ - "int64_t const * ptr" + "poly64x2_t v", + "const int lane" ], "return_type": { - "value": "int64x1_t" + "value": "poly64_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vn.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "LD1" + "UMOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_dup_s8", + "name": "vgetq_lane_p8", "arguments": [ - "int8_t const * ptr" + "poly8x16_t v", + "const int lane" ], "return_type": { - "value": "int8x8_t" + "value": "poly8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "lane": { + "minimum": 0, + "maximum": 15 + }, + "v": { + "register": "Vn.16B" } }, "Architectures": [ @@ -35335,22 +229976,27 @@ ], "instructions": [ [ - "LD1R" + "UMOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_dup_u16", + "name": "vgetq_lane_s16", "arguments": [ - "uint16_t const * ptr" + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "int16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vn.8H" } }, "Architectures": [ @@ -35360,22 +230006,27 @@ ], "instructions": [ [ - "LD1R" + "SMOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_dup_u32", + "name": "vgetq_lane_s32", "arguments": [ - "uint32_t const * ptr" + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "int32_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vn.4S" } }, "Architectures": [ @@ -35385,22 +230036,27 @@ ], "instructions": [ [ - "LD1R" + "SMOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_dup_u64", + "name": "vgetq_lane_s64", "arguments": [ - "uint64_t const * ptr" + "int64x2_t v", + "const int lane" ], "return_type": { - "value": "uint64x1_t" + "value": "int64_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vn.2D" } }, "Architectures": [ @@ -35410,22 +230066,27 @@ ], "instructions": [ [ - "LD1" + "UMOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_dup_u8", + "name": "vgetq_lane_s8", "arguments": [ - "uint8_t const * ptr" + "int8x16_t v", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "int8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "lane": { + "minimum": 0, + "maximum": 15 + }, + "v": { + "register": "Vn.16B" } }, "Architectures": [ @@ -35435,22 +230096,27 @@ ], "instructions": [ [ - "LD1R" + "SMOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_f16", + "name": "vgetq_lane_u16", "arguments": [ - "float16_t const * ptr" + "uint16x8_t v", + "const int lane" ], "return_type": { - "value": "float16x4_t" + "value": "uint16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vn.8H" } }, "Architectures": [ @@ -35460,22 +230126,27 @@ ], "instructions": [ [ - "LD1" + "UMOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_f16_x2", + "name": "vgetq_lane_u32", "arguments": [ - "float16_t const * ptr" + "uint32x4_t v", + "const int lane" ], "return_type": { - "value": "float16x4x2_t" + "value": "uint32_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vn.4S" } }, "Architectures": [ @@ -35485,22 +230156,27 @@ ], "instructions": [ [ - "LD1" + "UMOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_f16_x3", + "name": "vgetq_lane_u64", "arguments": [ - "float16_t const * ptr" + "uint64x2_t v", + "const int lane" ], "return_type": { - "value": "float16x4x3_t" + "value": "uint64_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vn.2D" } }, "Architectures": [ @@ -35510,22 +230186,27 @@ ], "instructions": [ [ - "LD1" + "UMOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_f16_x4", + "name": "vgetq_lane_u8", "arguments": [ - "float16_t const * ptr" + "uint8x16_t v", + "const int lane" ], "return_type": { - "value": "float16x4x4_t" + "value": "uint8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "lane": { + "minimum": 0, + "maximum": 15 + }, + "v": { + "register": "Vn.16B" } }, "Architectures": [ @@ -35535,22 +230216,26 @@ ], "instructions": [ [ - "LD1" + "UMOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_f32", + "name": "vhadd_s16", "arguments": [ - "float32_t const * ptr" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "float32x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" } }, "Architectures": [ @@ -35560,22 +230245,26 @@ ], "instructions": [ [ - "LD1" + "SHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_f32_x2", + "name": "vhadd_s32", "arguments": [ - "float32_t const * ptr" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "float32x2x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" } }, "Architectures": [ @@ -35585,22 +230274,26 @@ ], "instructions": [ [ - "LD1" + "SHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_f32_x3", + "name": "vhadd_s8", "arguments": [ - "float32_t const * ptr" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "float32x2x3_t" + "value": "int8x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" } }, "Architectures": [ @@ -35610,22 +230303,26 @@ ], "instructions": [ [ - "LD1" + "SHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_f32_x4", + "name": "vhadd_u16", "arguments": [ - "float32_t const * ptr" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "float32x2x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" } }, "Architectures": [ @@ -35635,123 +230332,142 @@ ], "instructions": [ [ - "LD1" + "UHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_f64", + "name": "vhadd_u32", "arguments": [ - "float64_t const * ptr" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "float64x1_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LD1" + "UHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_f64_x2", + "name": "vhadd_u8", "arguments": [ - "float64_t const * ptr" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "float64x1x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LD1" + "UHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_f64_x3", + "name": "vhaddq_s16", "arguments": [ - "float64_t const * ptr" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "float64x1x3_t" + "value": "int16x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LD1" + "SHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_f64_x4", + "name": "vhaddq_s32", "arguments": [ - "float64_t const * ptr" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "float64x1x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LD1" + "SHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_lane_f16", + "name": "vhaddq_s8", "arguments": [ - "float16_t const * ptr", - "float16x4_t src", - "const int lane" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "float16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.16B" }, - "src": { - "register": "Vt.4H" + "b": { + "register": "Vm.16B" } }, "Architectures": [ @@ -35761,31 +230477,26 @@ ], "instructions": [ [ - "LD1" + "SHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_lane_f32", + "name": "vhaddq_u16", "arguments": [ - "float32_t const * ptr", - "float32x2_t src", - "const int lane" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "float32x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.8H" }, - "src": { - "register": "Vt.2S" + "b": { + "register": "Vm.8H" } }, "Architectures": [ @@ -35795,63 +230506,55 @@ ], "instructions": [ [ - "LD1" + "UHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_lane_f64", + "name": "vhaddq_u32", "arguments": [ - "float64_t const * ptr", - "float64x1_t src", - "const int lane" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "float64x1_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.4S" }, - "src": { - "register": "Vt.1D" + "b": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LD1" + "UHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_lane_p16", + "name": "vhaddq_u8", "arguments": [ - "poly16_t const * ptr", - "poly16x4_t src", - "const int lane" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "poly16x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.16B" }, - "src": { - "register": "Vt.4H" + "b": { + "register": "Vm.16B" } }, "Architectures": [ @@ -35861,64 +230564,55 @@ ], "instructions": [ [ - "LD1" + "UHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_lane_p64", + "name": "vhsub_s16", "arguments": [ - "poly64_t const * ptr", - "poly64x1_t src", - "const int lane" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "poly64x1_t" + "value": "int16x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.4H" }, - "src": { - "register": "Vt.1D" + "b": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "LD1" + "SHSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_lane_p8", + "name": "vhsub_s32", "arguments": [ - "poly8_t const * ptr", - "poly8x8_t src", - "const int lane" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.2S" }, - "src": { - "register": "Vt.8B" + "b": { + "register": "Vm.2S" } }, "Architectures": [ @@ -35928,31 +230622,26 @@ ], "instructions": [ [ - "LD1" + "SHSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_lane_s16", + "name": "vhsub_s8", "arguments": [ - "int16_t const * ptr", - "int16x4_t src", - "const int lane" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "int16x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.8B" }, - "src": { - "register": "Vt.4H" + "b": { + "register": "Vm.8B" } }, "Architectures": [ @@ -35962,31 +230651,26 @@ ], "instructions": [ [ - "LD1" + "SHSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_lane_s32", + "name": "vhsub_u16", "arguments": [ - "int32_t const * ptr", - "int32x2_t src", - "const int lane" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "int32x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.4H" }, - "src": { - "register": "Vt.2S" + "b": { + "register": "Vm.4H" } }, "Architectures": [ @@ -35996,31 +230680,26 @@ ], "instructions": [ [ - "LD1" + "UHSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_lane_s64", + "name": "vhsub_u32", "arguments": [ - "int64_t const * ptr", - "int64x1_t src", - "const int lane" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "int64x1_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.2S" }, - "src": { - "register": "Vt.1D" + "b": { + "register": "Vm.2S" } }, "Architectures": [ @@ -36030,31 +230709,26 @@ ], "instructions": [ [ - "LD1" + "UHSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_lane_s8", + "name": "vhsub_u8", "arguments": [ - "int8_t const * ptr", - "int8x8_t src", - "const int lane" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "int8x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.8B" }, - "src": { - "register": "Vt.8B" + "b": { + "register": "Vm.8B" } }, "Architectures": [ @@ -36064,31 +230738,26 @@ ], "instructions": [ [ - "LD1" + "UHSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_lane_u16", + "name": "vhsubq_s16", "arguments": [ - "uint16_t const * ptr", - "uint16x4_t src", - "const int lane" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.8H" }, - "src": { - "register": "Vt.4H" + "b": { + "register": "Vm.8H" } }, "Architectures": [ @@ -36098,31 +230767,26 @@ ], "instructions": [ [ - "LD1" + "SHSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_lane_u32", + "name": "vhsubq_s32", "arguments": [ - "uint32_t const * ptr", - "uint32x2_t src", - "const int lane" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.4S" }, - "src": { - "register": "Vt.2S" + "b": { + "register": "Vm.4S" } }, "Architectures": [ @@ -36132,31 +230796,26 @@ ], "instructions": [ [ - "LD1" + "SHSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_lane_u64", + "name": "vhsubq_s8", "arguments": [ - "uint64_t const * ptr", - "uint64x1_t src", - "const int lane" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "uint64x1_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.16B" }, - "src": { - "register": "Vt.1D" + "b": { + "register": "Vm.16B" } }, "Architectures": [ @@ -36166,31 +230825,26 @@ ], "instructions": [ [ - "LD1" + "SHSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_lane_u8", + "name": "vhsubq_u16", "arguments": [ - "uint8_t const * ptr", - "uint8x8_t src", - "const int lane" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.8H" }, - "src": { - "register": "Vt.8B" + "b": { + "register": "Vm.8H" } }, "Architectures": [ @@ -36200,22 +230854,26 @@ ], "instructions": [ [ - "LD1" + "UHSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_p16", + "name": "vhsubq_u32", "arguments": [ - "poly16_t const * ptr" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "poly16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" } }, "Architectures": [ @@ -36225,22 +230883,26 @@ ], "instructions": [ [ - "LD1" + "UHSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_p16_x2", + "name": "vhsubq_u8", "arguments": [ - "poly16_t const * ptr" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "poly16x4x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" } }, "Architectures": [ @@ -36250,18 +230912,18 @@ ], "instructions": [ [ - "LD1" + "UHSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_p16_x3", + "name": "vld1_dup_f16", "arguments": [ - "poly16_t const * ptr" + "float16_t const * ptr" ], "return_type": { - "value": "poly16x4x3_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "ptr": { @@ -36275,18 +230937,18 @@ ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_p16_x4", + "name": "vld1_dup_f32", "arguments": [ - "poly16_t const * ptr" + "float32_t const * ptr" ], "return_type": { - "value": "poly16x4x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "ptr": { @@ -36300,18 +230962,18 @@ ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_p64", + "name": "vld1_dup_f64", "arguments": [ - "poly64_t const * ptr" + "float64_t const * ptr" ], "return_type": { - "value": "poly64x1_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "ptr": { @@ -36319,7 +230981,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -36330,12 +230991,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_p64_x2", + "name": "vld1_dup_p16", "arguments": [ - "poly64_t const * ptr" + "poly16_t const * ptr" ], "return_type": { - "value": "poly64x1x2_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "ptr": { @@ -36343,23 +231004,24 @@ } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_p64_x3", + "name": "vld1_dup_p64", "arguments": [ "poly64_t const * ptr" ], "return_type": { - "value": "poly64x1x3_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "ptr": { @@ -36378,12 +231040,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_p64_x4", + "name": "vld1_dup_p8", "arguments": [ - "poly64_t const * ptr" + "poly8_t const * ptr" ], "return_type": { - "value": "poly64x1x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "ptr": { @@ -36391,23 +231053,24 @@ } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_p8", + "name": "vld1_dup_s16", "arguments": [ - "poly8_t const * ptr" + "int16_t const * ptr" ], "return_type": { - "value": "poly8x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "ptr": { @@ -36421,18 +231084,18 @@ ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_p8_x2", + "name": "vld1_dup_s32", "arguments": [ - "poly8_t const * ptr" + "int32_t const * ptr" ], "return_type": { - "value": "poly8x8x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "ptr": { @@ -36446,18 +231109,18 @@ ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_p8_x3", + "name": "vld1_dup_s64", "arguments": [ - "poly8_t const * ptr" + "int64_t const * ptr" ], "return_type": { - "value": "poly8x8x3_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "ptr": { @@ -36477,12 +231140,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_p8_x4", + "name": "vld1_dup_s8", "arguments": [ - "poly8_t const * ptr" + "int8_t const * ptr" ], "return_type": { - "value": "poly8x8x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "ptr": { @@ -36496,18 +231159,18 @@ ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_s16", + "name": "vld1_dup_u16", "arguments": [ - "int16_t const * ptr" + "uint16_t const * ptr" ], "return_type": { - "value": "int16x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "ptr": { @@ -36521,18 +231184,18 @@ ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_s16_x2", + "name": "vld1_dup_u32", "arguments": [ - "int16_t const * ptr" + "uint32_t const * ptr" ], "return_type": { - "value": "int16x4x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "ptr": { @@ -36546,18 +231209,18 @@ ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_s16_x3", + "name": "vld1_dup_u64", "arguments": [ - "int16_t const * ptr" + "uint64_t const * ptr" ], "return_type": { - "value": "int16x4x3_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "ptr": { @@ -36577,12 +231240,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_s16_x4", + "name": "vld1_dup_u8", "arguments": [ - "int16_t const * ptr" + "uint8_t const * ptr" ], "return_type": { - "value": "int16x4x4_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "ptr": { @@ -36596,18 +231259,18 @@ ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1_s32", + "name": "vld1_f16", "arguments": [ - "int32_t const * ptr" + "float16_t const * ptr" ], "return_type": { - "value": "int32x2_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "ptr": { @@ -36627,12 +231290,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_s32_x2", + "name": "vld1_f16_x2", "arguments": [ - "int32_t const * ptr" + "float16_t const * ptr" ], "return_type": { - "value": "int32x2x2_t" + "value": "float16x4x2_t" }, "Arguments_Preparation": { "ptr": { @@ -36652,12 +231315,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_s32_x3", + "name": "vld1_f16_x3", "arguments": [ - "int32_t const * ptr" + "float16_t const * ptr" ], "return_type": { - "value": "int32x2x3_t" + "value": "float16x4x3_t" }, "Arguments_Preparation": { "ptr": { @@ -36677,12 +231340,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_s32_x4", + "name": "vld1_f16_x4", "arguments": [ - "int32_t const * ptr" + "float16_t const * ptr" ], "return_type": { - "value": "int32x2x4_t" + "value": "float16x4x4_t" }, "Arguments_Preparation": { "ptr": { @@ -36702,12 +231365,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_s64", + "name": "vld1_f32", "arguments": [ - "int64_t const * ptr" + "float32_t const * ptr" ], "return_type": { - "value": "int64x1_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "ptr": { @@ -36727,12 +231390,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_s64_x2", + "name": "vld1_f32_x2", "arguments": [ - "int64_t const * ptr" + "float32_t const * ptr" ], "return_type": { - "value": "int64x1x2_t" + "value": "float32x2x2_t" }, "Arguments_Preparation": { "ptr": { @@ -36752,12 +231415,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_s64_x3", + "name": "vld1_f32_x3", "arguments": [ - "int64_t const * ptr" + "float32_t const * ptr" ], "return_type": { - "value": "int64x1x3_t" + "value": "float32x2x3_t" }, "Arguments_Preparation": { "ptr": { @@ -36777,12 +231440,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_s64_x4", + "name": "vld1_f32_x4", "arguments": [ - "int64_t const * ptr" + "float32_t const * ptr" ], "return_type": { - "value": "int64x1x4_t" + "value": "float32x2x4_t" }, "Arguments_Preparation": { "ptr": { @@ -36802,12 +231465,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_s8", + "name": "vld1_f64", "arguments": [ - "int8_t const * ptr" + "float64_t const * ptr" ], "return_type": { - "value": "int8x8_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "ptr": { @@ -36815,8 +231478,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -36827,12 +231488,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_s8_x2", + "name": "vld1_f64_x2", "arguments": [ - "int8_t const * ptr" + "float64_t const * ptr" ], "return_type": { - "value": "int8x8x2_t" + "value": "float64x1x2_t" }, "Arguments_Preparation": { "ptr": { @@ -36840,8 +231501,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -36852,12 +231511,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_s8_x3", + "name": "vld1_f64_x3", "arguments": [ - "int8_t const * ptr" + "float64_t const * ptr" ], "return_type": { - "value": "int8x8x3_t" + "value": "float64x1x3_t" }, "Arguments_Preparation": { "ptr": { @@ -36865,8 +231524,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -36877,12 +231534,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_s8_x4", + "name": "vld1_f64_x4", "arguments": [ - "int8_t const * ptr" + "float64_t const * ptr" ], "return_type": { - "value": "int8x8x4_t" + "value": "float64x1x4_t" }, "Arguments_Preparation": { "ptr": { @@ -36890,8 +231547,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -36902,16 +231557,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_u16", + "name": "vld1_lane_f16", "arguments": [ - "uint16_t const * ptr" + "float16_t const * ptr", + "float16x4_t src", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.4H" } }, "Architectures": [ @@ -36927,16 +231591,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_u16_x2", + "name": "vld1_lane_f32", "arguments": [ - "uint16_t const * ptr" + "float32_t const * ptr", + "float32x2_t src", + "const int lane" ], "return_type": { - "value": "uint16x4x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.2S" } }, "Architectures": [ @@ -36952,21 +231625,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_u16_x3", + "name": "vld1_lane_f64", "arguments": [ - "uint16_t const * ptr" + "float64_t const * ptr", + "float64x1_t src", + "const int lane" ], "return_type": { - "value": "uint16x4x3_t" + "value": "float64x1_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -36977,16 +231657,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_u16_x4", + "name": "vld1_lane_p16", "arguments": [ - "uint16_t const * ptr" + "poly16_t const * ptr", + "poly16x4_t src", + "const int lane" ], "return_type": { - "value": "uint16x4x4_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.4H" } }, "Architectures": [ @@ -37002,20 +231691,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_u32", + "name": "vld1_lane_p64", "arguments": [ - "uint32_t const * ptr" + "poly64_t const * ptr", + "poly64x1_t src", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -37027,16 +231724,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_u32_x2", + "name": "vld1_lane_p8", "arguments": [ - "uint32_t const * ptr" + "poly8_t const * ptr", + "poly8x8_t src", + "const int lane" ], "return_type": { - "value": "uint32x2x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.8B" } }, "Architectures": [ @@ -37052,16 +231758,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_u32_x3", + "name": "vld1_lane_s16", "arguments": [ - "uint32_t const * ptr" + "int16_t const * ptr", + "int16x4_t src", + "const int lane" ], "return_type": { - "value": "uint32x2x3_t" + "value": "int16x4_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.4H" } }, "Architectures": [ @@ -37077,16 +231792,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_u32_x4", + "name": "vld1_lane_s32", "arguments": [ - "uint32_t const * ptr" + "int32_t const * ptr", + "int32x2_t src", + "const int lane" ], "return_type": { - "value": "uint32x2x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.2S" } }, "Architectures": [ @@ -37102,16 +231826,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_u64", + "name": "vld1_lane_s64", "arguments": [ - "uint64_t const * ptr" + "int64_t const * ptr", + "int64x1_t src", + "const int lane" ], "return_type": { - "value": "uint64x1_t" + "value": "int64x1_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.1D" } }, "Architectures": [ @@ -37127,16 +231860,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_u64_x2", + "name": "vld1_lane_s8", "arguments": [ - "uint64_t const * ptr" + "int8_t const * ptr", + "int8x8_t src", + "const int lane" ], "return_type": { - "value": "uint64x1x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.8B" } }, "Architectures": [ @@ -37152,16 +231894,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_u64_x3", + "name": "vld1_lane_u16", "arguments": [ - "uint64_t const * ptr" + "uint16_t const * ptr", + "uint16x4_t src", + "const int lane" ], "return_type": { - "value": "uint64x1x3_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.4H" } }, "Architectures": [ @@ -37177,16 +231928,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_u64_x4", + "name": "vld1_lane_u32", "arguments": [ - "uint64_t const * ptr" + "uint32_t const * ptr", + "uint32x2_t src", + "const int lane" ], "return_type": { - "value": "uint64x1x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.2S" } }, "Architectures": [ @@ -37202,16 +231962,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_u8", + "name": "vld1_lane_u64", "arguments": [ - "uint8_t const * ptr" + "uint64_t const * ptr", + "uint64x1_t src", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.1D" } }, "Architectures": [ @@ -37227,16 +231996,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_u8_x2", + "name": "vld1_lane_u8", "arguments": [ - "uint8_t const * ptr" + "uint8_t const * ptr", + "uint8x8_t src", + "const int lane" ], "return_type": { - "value": "uint8x8x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.8B" } }, "Architectures": [ @@ -37252,12 +232030,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_u8_x3", + "name": "vld1_p16", "arguments": [ - "uint8_t const * ptr" + "poly16_t const * ptr" ], "return_type": { - "value": "uint8x8x3_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "ptr": { @@ -37277,12 +232055,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1_u8_x4", + "name": "vld1_p16_x2", "arguments": [ - "uint8_t const * ptr" + "poly16_t const * ptr" ], "return_type": { - "value": "uint8x8x4_t" + "value": "poly16x4x2_t" }, "Arguments_Preparation": { "ptr": { @@ -37302,12 +232080,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_dup_f16", + "name": "vld1_p16_x3", "arguments": [ - "float16_t const * ptr" + "poly16_t const * ptr" ], "return_type": { - "value": "float16x8_t" + "value": "poly16x4x3_t" }, "Arguments_Preparation": { "ptr": { @@ -37321,18 +232099,18 @@ ], "instructions": [ [ - "LD1R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_dup_f32", + "name": "vld1_p16_x4", "arguments": [ - "float32_t const * ptr" + "poly16_t const * ptr" ], "return_type": { - "value": "float32x4_t" + "value": "poly16x4x4_t" }, "Arguments_Preparation": { "ptr": { @@ -37346,18 +232124,18 @@ ], "instructions": [ [ - "LD1R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_dup_f64", + "name": "vld1_p64", "arguments": [ - "float64_t const * ptr" + "poly64_t const * ptr" ], "return_type": { - "value": "float64x2_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "ptr": { @@ -37365,22 +232143,23 @@ } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "LD1R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_dup_p16", + "name": "vld1_p64_x2", "arguments": [ - "poly16_t const * ptr" + "poly64_t const * ptr" ], "return_type": { - "value": "poly16x8_t" + "value": "poly64x1x2_t" }, "Arguments_Preparation": { "ptr": { @@ -37388,24 +232167,23 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "LD1R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_dup_p64", + "name": "vld1_p64_x3", "arguments": [ "poly64_t const * ptr" ], "return_type": { - "value": "poly64x2_t" + "value": "poly64x1x3_t" }, "Arguments_Preparation": { "ptr": { @@ -37418,18 +232196,18 @@ ], "instructions": [ [ - "LD1R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_dup_p8", + "name": "vld1_p64_x4", "arguments": [ - "poly8_t const * ptr" + "poly64_t const * ptr" ], "return_type": { - "value": "poly8x16_t" + "value": "poly64x1x4_t" }, "Arguments_Preparation": { "ptr": { @@ -37437,24 +232215,23 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "LD1R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_dup_s16", + "name": "vld1_p8", "arguments": [ - "int16_t const * ptr" + "poly8_t const * ptr" ], "return_type": { - "value": "int16x8_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "ptr": { @@ -37468,18 +232245,18 @@ ], "instructions": [ [ - "LD1R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_dup_s32", + "name": "vld1_p8_x2", "arguments": [ - "int32_t const * ptr" + "poly8_t const * ptr" ], "return_type": { - "value": "int32x4_t" + "value": "poly8x8x2_t" }, "Arguments_Preparation": { "ptr": { @@ -37493,18 +232270,18 @@ ], "instructions": [ [ - "LD1R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_dup_s64", + "name": "vld1_p8_x3", "arguments": [ - "int64_t const * ptr" + "poly8_t const * ptr" ], "return_type": { - "value": "int64x2_t" + "value": "poly8x8x3_t" }, "Arguments_Preparation": { "ptr": { @@ -37518,18 +232295,18 @@ ], "instructions": [ [ - "LD1R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_dup_s8", + "name": "vld1_p8_x4", "arguments": [ - "int8_t const * ptr" + "poly8_t const * ptr" ], "return_type": { - "value": "int8x16_t" + "value": "poly8x8x4_t" }, "Arguments_Preparation": { "ptr": { @@ -37543,18 +232320,18 @@ ], "instructions": [ [ - "LD1R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_dup_u16", + "name": "vld1_s16", "arguments": [ - "uint16_t const * ptr" + "int16_t const * ptr" ], "return_type": { - "value": "uint16x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "ptr": { @@ -37568,18 +232345,18 @@ ], "instructions": [ [ - "LD1R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_dup_u32", + "name": "vld1_s16_x2", "arguments": [ - "uint32_t const * ptr" + "int16_t const * ptr" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x4x2_t" }, "Arguments_Preparation": { "ptr": { @@ -37593,18 +232370,18 @@ ], "instructions": [ [ - "LD1R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_dup_u64", + "name": "vld1_s16_x3", "arguments": [ - "uint64_t const * ptr" + "int16_t const * ptr" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x4x3_t" }, "Arguments_Preparation": { "ptr": { @@ -37618,18 +232395,18 @@ ], "instructions": [ [ - "LD1R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_dup_u8", + "name": "vld1_s16_x4", "arguments": [ - "uint8_t const * ptr" + "int16_t const * ptr" ], "return_type": { - "value": "uint8x16_t" + "value": "int16x4x4_t" }, "Arguments_Preparation": { "ptr": { @@ -37643,18 +232420,18 @@ ], "instructions": [ [ - "LD1R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_f16", + "name": "vld1_s32", "arguments": [ - "float16_t const * ptr" + "int32_t const * ptr" ], "return_type": { - "value": "float16x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "ptr": { @@ -37674,12 +232451,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_f16_x2", + "name": "vld1_s32_x2", "arguments": [ - "float16_t const * ptr" + "int32_t const * ptr" ], "return_type": { - "value": "float16x8x2_t" + "value": "int32x2x2_t" }, "Arguments_Preparation": { "ptr": { @@ -37699,12 +232476,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_f16_x3", + "name": "vld1_s32_x3", "arguments": [ - "float16_t const * ptr" + "int32_t const * ptr" ], "return_type": { - "value": "float16x8x3_t" + "value": "int32x2x3_t" }, "Arguments_Preparation": { "ptr": { @@ -37724,12 +232501,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_f16_x4", + "name": "vld1_s32_x4", "arguments": [ - "float16_t const * ptr" + "int32_t const * ptr" ], "return_type": { - "value": "float16x8x4_t" + "value": "int32x2x4_t" }, "Arguments_Preparation": { "ptr": { @@ -37749,12 +232526,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_f32", + "name": "vld1_s64", "arguments": [ - "float32_t const * ptr" + "int64_t const * ptr" ], "return_type": { - "value": "float32x4_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "ptr": { @@ -37774,12 +232551,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_f32_x2", + "name": "vld1_s64_x2", "arguments": [ - "float32_t const * ptr" + "int64_t const * ptr" ], "return_type": { - "value": "float32x4x2_t" + "value": "int64x1x2_t" }, "Arguments_Preparation": { "ptr": { @@ -37799,12 +232576,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_f32_x3", + "name": "vld1_s64_x3", "arguments": [ - "float32_t const * ptr" + "int64_t const * ptr" ], "return_type": { - "value": "float32x4x3_t" + "value": "int64x1x3_t" }, "Arguments_Preparation": { "ptr": { @@ -37824,12 +232601,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_f32_x4", + "name": "vld1_s64_x4", "arguments": [ - "float32_t const * ptr" + "int64_t const * ptr" ], "return_type": { - "value": "float32x4x4_t" + "value": "int64x1x4_t" }, "Arguments_Preparation": { "ptr": { @@ -37849,12 +232626,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_f64", + "name": "vld1_s8", "arguments": [ - "float64_t const * ptr" + "int8_t const * ptr" ], "return_type": { - "value": "float64x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "ptr": { @@ -37862,6 +232639,8 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -37872,12 +232651,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_f64_x2", + "name": "vld1_s8_x2", "arguments": [ - "float64_t const * ptr" + "int8_t const * ptr" ], "return_type": { - "value": "float64x2x2_t" + "value": "int8x8x2_t" }, "Arguments_Preparation": { "ptr": { @@ -37885,6 +232664,8 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -37895,12 +232676,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_f64_x3", + "name": "vld1_s8_x3", "arguments": [ - "float64_t const * ptr" + "int8_t const * ptr" ], "return_type": { - "value": "float64x2x3_t" + "value": "int8x8x3_t" }, "Arguments_Preparation": { "ptr": { @@ -37908,6 +232689,8 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -37918,12 +232701,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_f64_x4", + "name": "vld1_s8_x4", "arguments": [ - "float64_t const * ptr" + "int8_t const * ptr" ], "return_type": { - "value": "float64x2x4_t" + "value": "int8x8x4_t" }, "Arguments_Preparation": { "ptr": { @@ -37931,6 +232714,8 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -37941,25 +232726,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_lane_f16", + "name": "vld1_u16", "arguments": [ - "float16_t const * ptr", - "float16x8_t src", - "const int lane" + "uint16_t const * ptr" ], "return_type": { - "value": "float16x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt.8H" } }, "Architectures": [ @@ -37975,25 +232751,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_lane_f32", + "name": "vld1_u16_x2", "arguments": [ - "float32_t const * ptr", - "float32x4_t src", - "const int lane" + "uint16_t const * ptr" ], "return_type": { - "value": "float32x4_t" + "value": "uint16x4x2_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt.4S" } }, "Architectures": [ @@ -38009,28 +232776,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_lane_f64", + "name": "vld1_u16_x3", "arguments": [ - "float64_t const * ptr", - "float64x2_t src", - "const int lane" + "uint16_t const * ptr" ], "return_type": { - "value": "float64x2_t" + "value": "uint16x4x3_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -38041,25 +232801,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_lane_p16", + "name": "vld1_u16_x4", "arguments": [ - "poly16_t const * ptr", - "poly16x8_t src", - "const int lane" + "uint16_t const * ptr" ], "return_type": { - "value": "poly16x8_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, + "value": "uint16x4x4_t" + }, + "Arguments_Preparation": { "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt.8H" } }, "Architectures": [ @@ -38075,28 +232826,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_lane_p64", + "name": "vld1_u32", "arguments": [ - "poly64_t const * ptr", - "poly64x2_t src", - "const int lane" + "uint32_t const * ptr" ], "return_type": { - "value": "poly64x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt.2D" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -38108,25 +232851,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_lane_p8", + "name": "vld1_u32_x2", "arguments": [ - "poly8_t const * ptr", - "poly8x16_t src", - "const int lane" + "uint32_t const * ptr" ], "return_type": { - "value": "poly8x16_t" + "value": "uint32x2x2_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt.16B" } }, "Architectures": [ @@ -38142,25 +232876,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_lane_s16", + "name": "vld1_u32_x3", "arguments": [ - "int16_t const * ptr", - "int16x8_t src", - "const int lane" + "uint32_t const * ptr" ], "return_type": { - "value": "int16x8_t" + "value": "uint32x2x3_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt.8H" } }, "Architectures": [ @@ -38176,25 +232901,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_lane_s32", + "name": "vld1_u32_x4", "arguments": [ - "int32_t const * ptr", - "int32x4_t src", - "const int lane" + "uint32_t const * ptr" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x2x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt.4S" } }, "Architectures": [ @@ -38210,25 +232926,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_lane_s64", + "name": "vld1_u64", "arguments": [ - "int64_t const * ptr", - "int64x2_t src", - "const int lane" + "uint64_t const * ptr" ], "return_type": { - "value": "int64x2_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt.2D" } }, "Architectures": [ @@ -38244,25 +232951,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_lane_s8", + "name": "vld1_u64_x2", "arguments": [ - "int8_t const * ptr", - "int8x16_t src", - "const int lane" + "uint64_t const * ptr" ], "return_type": { - "value": "int8x16_t" + "value": "uint64x1x2_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt.16B" } }, "Architectures": [ @@ -38278,25 +232976,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_lane_u16", + "name": "vld1_u64_x3", "arguments": [ - "uint16_t const * ptr", - "uint16x8_t src", - "const int lane" + "uint64_t const * ptr" ], "return_type": { - "value": "uint16x8_t" + "value": "uint64x1x3_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt.8H" } }, "Architectures": [ @@ -38312,25 +233001,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_lane_u32", + "name": "vld1_u64_x4", "arguments": [ - "uint32_t const * ptr", - "uint32x4_t src", - "const int lane" + "uint64_t const * ptr" ], "return_type": { - "value": "uint32x4_t" + "value": "uint64x1x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt.4S" } }, "Architectures": [ @@ -38346,25 +233026,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_lane_u64", + "name": "vld1_u8", "arguments": [ - "uint64_t const * ptr", - "uint64x2_t src", - "const int lane" + "uint8_t const * ptr" ], "return_type": { - "value": "uint64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt.2D" } }, "Architectures": [ @@ -38380,25 +233051,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_lane_u8", + "name": "vld1_u8_x2", "arguments": [ - "uint8_t const * ptr", - "uint8x16_t src", - "const int lane" + "uint8_t const * ptr" ], "return_type": { - "value": "uint8x16_t" + "value": "uint8x8x2_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt.16B" } }, "Architectures": [ @@ -38414,12 +233076,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_p16", + "name": "vld1_u8_x3", "arguments": [ - "poly16_t const * ptr" + "uint8_t const * ptr" ], "return_type": { - "value": "poly16x8_t" + "value": "uint8x8x3_t" }, "Arguments_Preparation": { "ptr": { @@ -38439,12 +233101,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_p16_x2", + "name": "vld1_u8_x4", "arguments": [ - "poly16_t const * ptr" + "uint8_t const * ptr" ], "return_type": { - "value": "poly16x8x2_t" + "value": "uint8x8x4_t" }, "Arguments_Preparation": { "ptr": { @@ -38464,12 +233126,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_p16_x3", + "name": "vld1q_dup_f16", "arguments": [ - "poly16_t const * ptr" + "float16_t const * ptr" ], "return_type": { - "value": "poly16x8x3_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "ptr": { @@ -38483,18 +233145,18 @@ ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_p16_x4", + "name": "vld1q_dup_f32", "arguments": [ - "poly16_t const * ptr" + "float32_t const * ptr" ], "return_type": { - "value": "poly16x8x4_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "ptr": { @@ -38508,18 +233170,18 @@ ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_p64", + "name": "vld1q_dup_f64", "arguments": [ - "poly64_t const * ptr" + "float64_t const * ptr" ], "return_type": { - "value": "poly64x2_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "ptr": { @@ -38527,23 +233189,22 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_p64_x2", + "name": "vld1q_dup_p16", "arguments": [ - "poly64_t const * ptr" + "poly16_t const * ptr" ], "return_type": { - "value": "poly64x2x2_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "ptr": { @@ -38551,23 +233212,24 @@ } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_p64_x3", + "name": "vld1q_dup_p64", "arguments": [ "poly64_t const * ptr" ], "return_type": { - "value": "poly64x2x3_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "ptr": { @@ -38580,18 +233242,18 @@ ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_p64_x4", + "name": "vld1q_dup_p8", "arguments": [ - "poly64_t const * ptr" + "poly8_t const * ptr" ], "return_type": { - "value": "poly64x2x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "ptr": { @@ -38599,23 +233261,24 @@ } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_p8", + "name": "vld1q_dup_s16", "arguments": [ - "poly8_t const * ptr" + "int16_t const * ptr" ], "return_type": { - "value": "poly8x16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "ptr": { @@ -38629,18 +233292,18 @@ ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_p8_x2", + "name": "vld1q_dup_s32", "arguments": [ - "poly8_t const * ptr" + "int32_t const * ptr" ], "return_type": { - "value": "poly8x16x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "ptr": { @@ -38654,18 +233317,18 @@ ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_p8_x3", + "name": "vld1q_dup_s64", "arguments": [ - "poly8_t const * ptr" + "int64_t const * ptr" ], "return_type": { - "value": "poly8x16x3_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "ptr": { @@ -38679,18 +233342,18 @@ ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_p8_x4", + "name": "vld1q_dup_s8", "arguments": [ - "poly8_t const * ptr" + "int8_t const * ptr" ], "return_type": { - "value": "poly8x16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "ptr": { @@ -38704,18 +233367,18 @@ ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_s16", + "name": "vld1q_dup_u16", "arguments": [ - "int16_t const * ptr" + "uint16_t const * ptr" ], "return_type": { - "value": "int16x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "ptr": { @@ -38729,18 +233392,18 @@ ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_s16_x2", + "name": "vld1q_dup_u32", "arguments": [ - "int16_t const * ptr" + "uint32_t const * ptr" ], "return_type": { - "value": "int16x8x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "ptr": { @@ -38754,18 +233417,18 @@ ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_s16_x3", + "name": "vld1q_dup_u64", "arguments": [ - "int16_t const * ptr" + "uint64_t const * ptr" ], "return_type": { - "value": "int16x8x3_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "ptr": { @@ -38779,18 +233442,18 @@ ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_s16_x4", + "name": "vld1q_dup_u8", "arguments": [ - "int16_t const * ptr" + "uint8_t const * ptr" ], "return_type": { - "value": "int16x8x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "ptr": { @@ -38804,18 +233467,18 @@ ], "instructions": [ [ - "LD1" + "LD1R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld1q_s32", + "name": "vld1q_f16", "arguments": [ - "int32_t const * ptr" + "float16_t const * ptr" ], "return_type": { - "value": "int32x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "ptr": { @@ -38835,12 +233498,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_s32_x2", + "name": "vld1q_f16_x2", "arguments": [ - "int32_t const * ptr" + "float16_t const * ptr" ], "return_type": { - "value": "int32x4x2_t" + "value": "float16x8x2_t" }, "Arguments_Preparation": { "ptr": { @@ -38860,12 +233523,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_s32_x3", + "name": "vld1q_f16_x3", "arguments": [ - "int32_t const * ptr" + "float16_t const * ptr" ], "return_type": { - "value": "int32x4x3_t" + "value": "float16x8x3_t" }, "Arguments_Preparation": { "ptr": { @@ -38885,12 +233548,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_s32_x4", + "name": "vld1q_f16_x4", "arguments": [ - "int32_t const * ptr" + "float16_t const * ptr" ], "return_type": { - "value": "int32x4x4_t" + "value": "float16x8x4_t" }, "Arguments_Preparation": { "ptr": { @@ -38910,12 +233573,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_s64", + "name": "vld1q_f32", "arguments": [ - "int64_t const * ptr" + "float32_t const * ptr" ], "return_type": { - "value": "int64x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "ptr": { @@ -38935,12 +233598,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_s64_x2", + "name": "vld1q_f32_x2", "arguments": [ - "int64_t const * ptr" + "float32_t const * ptr" ], "return_type": { - "value": "int64x2x2_t" + "value": "float32x4x2_t" }, "Arguments_Preparation": { "ptr": { @@ -38960,12 +233623,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_s64_x3", + "name": "vld1q_f32_x3", "arguments": [ - "int64_t const * ptr" + "float32_t const * ptr" ], "return_type": { - "value": "int64x2x3_t" + "value": "float32x4x3_t" }, "Arguments_Preparation": { "ptr": { @@ -38985,12 +233648,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_s64_x4", + "name": "vld1q_f32_x4", "arguments": [ - "int64_t const * ptr" + "float32_t const * ptr" ], "return_type": { - "value": "int64x2x4_t" + "value": "float32x4x4_t" }, "Arguments_Preparation": { "ptr": { @@ -39010,12 +233673,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_s8", + "name": "vld1q_f64", "arguments": [ - "int8_t const * ptr" + "float64_t const * ptr" ], "return_type": { - "value": "int8x16_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "ptr": { @@ -39023,8 +233686,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -39035,12 +233696,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_s8_x2", + "name": "vld1q_f64_x2", "arguments": [ - "int8_t const * ptr" + "float64_t const * ptr" ], "return_type": { - "value": "int8x16x2_t" + "value": "float64x2x2_t" }, "Arguments_Preparation": { "ptr": { @@ -39048,8 +233709,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -39060,12 +233719,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_s8_x3", + "name": "vld1q_f64_x3", "arguments": [ - "int8_t const * ptr" + "float64_t const * ptr" ], "return_type": { - "value": "int8x16x3_t" + "value": "float64x2x3_t" }, "Arguments_Preparation": { "ptr": { @@ -39073,8 +233732,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -39085,12 +233742,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_s8_x4", + "name": "vld1q_f64_x4", "arguments": [ - "int8_t const * ptr" + "float64_t const * ptr" ], "return_type": { - "value": "int8x16x4_t" + "value": "float64x2x4_t" }, "Arguments_Preparation": { "ptr": { @@ -39098,8 +233755,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -39110,16 +233765,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_u16", + "name": "vld1q_lane_f16", "arguments": [ - "uint16_t const * ptr" + "float16_t const * ptr", + "float16x8_t src", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "float16x8_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.8H" } }, "Architectures": [ @@ -39135,16 +233799,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_u16_x2", + "name": "vld1q_lane_f32", "arguments": [ - "uint16_t const * ptr" + "float32_t const * ptr", + "float32x4_t src", + "const int lane" ], "return_type": { - "value": "uint16x8x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.4S" } }, "Architectures": [ @@ -39160,21 +233833,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_u16_x3", + "name": "vld1q_lane_f64", "arguments": [ - "uint16_t const * ptr" + "float64_t const * ptr", + "float64x2_t src", + "const int lane" ], "return_type": { - "value": "uint16x8x3_t" + "value": "float64x2_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -39185,16 +233865,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_u16_x4", + "name": "vld1q_lane_p16", "arguments": [ - "uint16_t const * ptr" + "poly16_t const * ptr", + "poly16x8_t src", + "const int lane" ], "return_type": { - "value": "uint16x8x4_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.8H" } }, "Architectures": [ @@ -39210,20 +233899,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_u32", + "name": "vld1q_lane_p64", "arguments": [ - "uint32_t const * ptr" + "poly64_t const * ptr", + "poly64x2_t src", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -39235,16 +233932,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_u32_x2", + "name": "vld1q_lane_p8", "arguments": [ - "uint32_t const * ptr" + "poly8_t const * ptr", + "poly8x16_t src", + "const int lane" ], "return_type": { - "value": "uint32x4x2_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 15 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.16B" } }, "Architectures": [ @@ -39260,16 +233966,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_u32_x3", + "name": "vld1q_lane_s16", "arguments": [ - "uint32_t const * ptr" + "int16_t const * ptr", + "int16x8_t src", + "const int lane" ], "return_type": { - "value": "uint32x4x3_t" + "value": "int16x8_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.8H" } }, "Architectures": [ @@ -39285,16 +234000,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_u32_x4", + "name": "vld1q_lane_s32", "arguments": [ - "uint32_t const * ptr" + "int32_t const * ptr", + "int32x4_t src", + "const int lane" ], "return_type": { - "value": "uint32x4x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.4S" } }, "Architectures": [ @@ -39310,16 +234034,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_u64", + "name": "vld1q_lane_s64", "arguments": [ - "uint64_t const * ptr" + "int64_t const * ptr", + "int64x2_t src", + "const int lane" ], "return_type": { - "value": "uint64x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.2D" } }, "Architectures": [ @@ -39335,16 +234068,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_u64_x2", + "name": "vld1q_lane_s8", "arguments": [ - "uint64_t const * ptr" + "int8_t const * ptr", + "int8x16_t src", + "const int lane" ], "return_type": { - "value": "uint64x2x2_t" + "value": "int8x16_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 15 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.16B" } }, "Architectures": [ @@ -39360,16 +234102,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_u64_x3", + "name": "vld1q_lane_u16", "arguments": [ - "uint64_t const * ptr" + "uint16_t const * ptr", + "uint16x8_t src", + "const int lane" ], "return_type": { - "value": "uint64x2x3_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.8H" } }, "Architectures": [ @@ -39385,16 +234136,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_u64_x4", + "name": "vld1q_lane_u32", "arguments": [ - "uint64_t const * ptr" + "uint32_t const * ptr", + "uint32x4_t src", + "const int lane" ], "return_type": { - "value": "uint64x2x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.4S" } }, "Architectures": [ @@ -39410,16 +234170,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_u8", + "name": "vld1q_lane_u64", "arguments": [ - "uint8_t const * ptr" + "uint64_t const * ptr", + "uint64x2_t src", + "const int lane" ], "return_type": { - "value": "uint8x16_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.2D" } }, "Architectures": [ @@ -39435,16 +234204,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_u8_x2", + "name": "vld1q_lane_u8", "arguments": [ - "uint8_t const * ptr" + "uint8_t const * ptr", + "uint8x16_t src", + "const int lane" ], "return_type": { - "value": "uint8x16x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 15 + }, "ptr": { "register": "Xn" + }, + "src": { + "register": "Vt.16B" } }, "Architectures": [ @@ -39460,12 +234238,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_u8_x3", + "name": "vld1q_p16", "arguments": [ - "uint8_t const * ptr" + "poly16_t const * ptr" ], "return_type": { - "value": "uint8x16x3_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "ptr": { @@ -39485,12 +234263,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld1q_u8_x4", + "name": "vld1q_p16_x2", "arguments": [ - "uint8_t const * ptr" + "poly16_t const * ptr" ], "return_type": { - "value": "uint8x16x4_t" + "value": "poly16x8x2_t" }, "Arguments_Preparation": { "ptr": { @@ -39510,12 +234288,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2_dup_f16", + "name": "vld1q_p16_x3", "arguments": [ - "float16_t const * ptr" + "poly16_t const * ptr" ], "return_type": { - "value": "float16x4x2_t" + "value": "poly16x8x3_t" }, "Arguments_Preparation": { "ptr": { @@ -39529,18 +234307,18 @@ ], "instructions": [ [ - "LD2R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_dup_f32", + "name": "vld1q_p16_x4", "arguments": [ - "float32_t const * ptr" + "poly16_t const * ptr" ], "return_type": { - "value": "float32x2x2_t" + "value": "poly16x8x4_t" }, "Arguments_Preparation": { "ptr": { @@ -39554,18 +234332,18 @@ ], "instructions": [ [ - "LD2R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_dup_f64", + "name": "vld1q_p64", "arguments": [ - "float64_t const * ptr" + "poly64_t const * ptr" ], "return_type": { - "value": "float64x1x2_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "ptr": { @@ -39573,22 +234351,23 @@ } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "LD2R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_dup_p16", + "name": "vld1q_p64_x2", "arguments": [ - "poly16_t const * ptr" + "poly64_t const * ptr" ], "return_type": { - "value": "poly16x4x2_t" + "value": "poly64x2x2_t" }, "Arguments_Preparation": { "ptr": { @@ -39596,24 +234375,23 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "LD2R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_dup_p64", + "name": "vld1q_p64_x3", "arguments": [ "poly64_t const * ptr" ], "return_type": { - "value": "poly64x1x2_t" + "value": "poly64x2x3_t" }, "Arguments_Preparation": { "ptr": { @@ -39626,18 +234404,18 @@ ], "instructions": [ [ - "LD2R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_dup_p8", + "name": "vld1q_p64_x4", "arguments": [ - "poly8_t const * ptr" + "poly64_t const * ptr" ], "return_type": { - "value": "poly8x8x2_t" + "value": "poly64x2x4_t" }, "Arguments_Preparation": { "ptr": { @@ -39645,24 +234423,23 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "LD2R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_dup_s16", + "name": "vld1q_p8", "arguments": [ - "int16_t const * ptr" + "poly8_t const * ptr" ], "return_type": { - "value": "int16x4x2_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "ptr": { @@ -39676,18 +234453,18 @@ ], "instructions": [ [ - "LD2R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_dup_s32", + "name": "vld1q_p8_x2", "arguments": [ - "int32_t const * ptr" + "poly8_t const * ptr" ], "return_type": { - "value": "int32x2x2_t" + "value": "poly8x16x2_t" }, "Arguments_Preparation": { "ptr": { @@ -39701,18 +234478,18 @@ ], "instructions": [ [ - "LD2R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_dup_s64", + "name": "vld1q_p8_x3", "arguments": [ - "int64_t const * ptr" + "poly8_t const * ptr" ], "return_type": { - "value": "int64x1x2_t" + "value": "poly8x16x3_t" }, "Arguments_Preparation": { "ptr": { @@ -39726,18 +234503,18 @@ ], "instructions": [ [ - "LD2R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_dup_s8", + "name": "vld1q_p8_x4", "arguments": [ - "int8_t const * ptr" + "poly8_t const * ptr" ], "return_type": { - "value": "int8x8x2_t" + "value": "poly8x16x4_t" }, "Arguments_Preparation": { "ptr": { @@ -39751,18 +234528,18 @@ ], "instructions": [ [ - "LD2R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_dup_u16", + "name": "vld1q_s16", "arguments": [ - "uint16_t const * ptr" + "int16_t const * ptr" ], "return_type": { - "value": "uint16x4x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "ptr": { @@ -39776,18 +234553,18 @@ ], "instructions": [ [ - "LD2R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_dup_u32", + "name": "vld1q_s16_x2", "arguments": [ - "uint32_t const * ptr" + "int16_t const * ptr" ], "return_type": { - "value": "uint32x2x2_t" + "value": "int16x8x2_t" }, "Arguments_Preparation": { "ptr": { @@ -39801,18 +234578,18 @@ ], "instructions": [ [ - "LD2R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_dup_u64", + "name": "vld1q_s16_x3", "arguments": [ - "uint64_t const * ptr" + "int16_t const * ptr" ], "return_type": { - "value": "uint64x1x2_t" + "value": "int16x8x3_t" }, "Arguments_Preparation": { "ptr": { @@ -39826,18 +234603,18 @@ ], "instructions": [ [ - "LD2R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_dup_u8", + "name": "vld1q_s16_x4", "arguments": [ - "uint8_t const * ptr" + "int16_t const * ptr" ], "return_type": { - "value": "uint8x8x2_t" + "value": "int16x8x4_t" }, "Arguments_Preparation": { "ptr": { @@ -39851,18 +234628,18 @@ ], "instructions": [ [ - "LD2R" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_f16", + "name": "vld1q_s32", "arguments": [ - "float16_t const * ptr" + "int32_t const * ptr" ], "return_type": { - "value": "float16x4x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "ptr": { @@ -39876,18 +234653,18 @@ ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_f32", + "name": "vld1q_s32_x2", "arguments": [ - "float32_t const * ptr" + "int32_t const * ptr" ], "return_type": { - "value": "float32x2x2_t" + "value": "int32x4x2_t" }, "Arguments_Preparation": { "ptr": { @@ -39901,18 +234678,18 @@ ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_f64", + "name": "vld1q_s32_x3", "arguments": [ - "float64_t const * ptr" + "int32_t const * ptr" ], "return_type": { - "value": "float64x1x2_t" + "value": "int32x4x3_t" }, "Arguments_Preparation": { "ptr": { @@ -39920,6 +234697,8 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -39930,25 +234709,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2_lane_f16", + "name": "vld1q_s32_x4", "arguments": [ - "float16_t const * ptr", - "float16x4x2_t src", - "const int lane" + "int32_t const * ptr" ], "return_type": { - "value": "float16x4x2_t" + "value": "int32x4x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt2.4H" } }, "Architectures": [ @@ -39958,31 +234728,22 @@ ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_lane_f32", + "name": "vld1q_s64", "arguments": [ - "float32_t const * ptr", - "float32x2x2_t src", - "const int lane" + "int64_t const * ptr" ], "return_type": { - "value": "float32x2x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt2.2S" } }, "Architectures": [ @@ -39992,63 +234753,47 @@ ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_lane_f64", + "name": "vld1q_s64_x2", "arguments": [ - "float64_t const * ptr", - "float64x1x2_t src", - "const int lane" + "int64_t const * ptr" ], "return_type": { - "value": "float64x1x2_t" + "value": "int64x2x2_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt2.1D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_lane_p16", + "name": "vld1q_s64_x3", "arguments": [ - "poly16_t const * ptr", - "poly16x4x2_t src", - "const int lane" + "int64_t const * ptr" ], "return_type": { - "value": "poly16x4x2_t" + "value": "int64x2x3_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt2.4H" } }, "Architectures": [ @@ -40058,63 +234803,47 @@ ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_lane_p64", + "name": "vld1q_s64_x4", "arguments": [ - "poly64_t const * ptr", - "poly64x1x2_t src", - "const int lane" + "int64_t const * ptr" ], "return_type": { - "value": "poly64x1x2_t" + "value": "int64x2x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt2.1D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_lane_p8", + "name": "vld1q_s8", "arguments": [ - "poly8_t const * ptr", - "poly8x8x2_t src", - "const int lane" + "int8_t const * ptr" ], "return_type": { - "value": "poly8x8x2_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt2.8B" } }, "Architectures": [ @@ -40124,31 +234853,22 @@ ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_lane_s16", + "name": "vld1q_s8_x2", "arguments": [ - "int16_t const * ptr", - "int16x4x2_t src", - "const int lane" + "int8_t const * ptr" ], "return_type": { - "value": "int16x4x2_t" + "value": "int8x16x2_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt2.4H" } }, "Architectures": [ @@ -40158,31 +234878,22 @@ ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_lane_s32", + "name": "vld1q_s8_x3", "arguments": [ - "int32_t const * ptr", - "int32x2x2_t src", - "const int lane" + "int8_t const * ptr" ], "return_type": { - "value": "int32x2x2_t" + "value": "int8x16x3_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt2.2S" } }, "Architectures": [ @@ -40192,63 +234903,47 @@ ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_lane_s64", + "name": "vld1q_s8_x4", "arguments": [ - "int64_t const * ptr", - "int64x1x2_t src", - "const int lane" + "int8_t const * ptr" ], "return_type": { - "value": "int64x1x2_t" + "value": "int8x16x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt2.1D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_lane_s8", + "name": "vld1q_u16", "arguments": [ - "int8_t const * ptr", - "int8x8x2_t src", - "const int lane" + "uint16_t const * ptr" ], "return_type": { - "value": "int8x8x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt2.8B" } }, "Architectures": [ @@ -40258,31 +234953,22 @@ ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_lane_u16", + "name": "vld1q_u16_x2", "arguments": [ - "uint16_t const * ptr", - "uint16x4x2_t src", - "const int lane" + "uint16_t const * ptr" ], "return_type": { - "value": "uint16x4x2_t" + "value": "uint16x8x2_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt2.4H" } }, "Architectures": [ @@ -40292,31 +234978,22 @@ ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_lane_u32", + "name": "vld1q_u16_x3", "arguments": [ - "uint32_t const * ptr", - "uint32x2x2_t src", - "const int lane" + "uint16_t const * ptr" ], "return_type": { - "value": "uint32x2x2_t" + "value": "uint16x8x3_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt2.2S" } }, "Architectures": [ @@ -40326,63 +235003,47 @@ ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_lane_u64", + "name": "vld1q_u16_x4", "arguments": [ - "uint64_t const * ptr", - "uint64x1x2_t src", - "const int lane" + "uint16_t const * ptr" ], "return_type": { - "value": "uint64x1x2_t" + "value": "uint16x8x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt2.1D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_lane_u8", + "name": "vld1q_u32", "arguments": [ - "uint8_t const * ptr", - "uint8x8x2_t src", - "const int lane" + "uint32_t const * ptr" ], "return_type": { - "value": "uint8x8x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt2.8B" } }, "Architectures": [ @@ -40392,18 +235053,18 @@ ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_p16", + "name": "vld1q_u32_x2", "arguments": [ - "poly16_t const * ptr" + "uint32_t const * ptr" ], "return_type": { - "value": "poly16x4x2_t" + "value": "uint32x4x2_t" }, "Arguments_Preparation": { "ptr": { @@ -40417,18 +235078,18 @@ ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_p64", + "name": "vld1q_u32_x3", "arguments": [ - "poly64_t const * ptr" + "uint32_t const * ptr" ], "return_type": { - "value": "poly64x1x2_t" + "value": "uint32x4x3_t" }, "Arguments_Preparation": { "ptr": { @@ -40436,6 +235097,7 @@ } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -40447,12 +235109,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2_p8", + "name": "vld1q_u32_x4", "arguments": [ - "poly8_t const * ptr" + "uint32_t const * ptr" ], "return_type": { - "value": "poly8x8x2_t" + "value": "uint32x4x4_t" }, "Arguments_Preparation": { "ptr": { @@ -40466,18 +235128,18 @@ ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_s16", + "name": "vld1q_u64", "arguments": [ - "int16_t const * ptr" + "uint64_t const * ptr" ], "return_type": { - "value": "int16x4x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "ptr": { @@ -40491,18 +235153,18 @@ ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_s32", + "name": "vld1q_u64_x2", "arguments": [ - "int32_t const * ptr" + "uint64_t const * ptr" ], "return_type": { - "value": "int32x2x2_t" + "value": "uint64x2x2_t" }, "Arguments_Preparation": { "ptr": { @@ -40516,18 +235178,18 @@ ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_s64", + "name": "vld1q_u64_x3", "arguments": [ - "int64_t const * ptr" + "uint64_t const * ptr" ], "return_type": { - "value": "int64x1x2_t" + "value": "uint64x2x3_t" }, "Arguments_Preparation": { "ptr": { @@ -40547,12 +235209,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2_s8", + "name": "vld1q_u64_x4", "arguments": [ - "int8_t const * ptr" + "uint64_t const * ptr" ], "return_type": { - "value": "int8x8x2_t" + "value": "uint64x2x4_t" }, "Arguments_Preparation": { "ptr": { @@ -40566,18 +235228,18 @@ ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_u16", + "name": "vld1q_u8", "arguments": [ - "uint16_t const * ptr" + "uint8_t const * ptr" ], "return_type": { - "value": "uint16x4x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "ptr": { @@ -40591,18 +235253,18 @@ ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_u32", + "name": "vld1q_u8_x2", "arguments": [ - "uint32_t const * ptr" + "uint8_t const * ptr" ], "return_type": { - "value": "uint32x2x2_t" + "value": "uint8x16x2_t" }, "Arguments_Preparation": { "ptr": { @@ -40616,18 +235278,18 @@ ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2_u64", + "name": "vld1q_u8_x3", "arguments": [ - "uint64_t const * ptr" + "uint8_t const * ptr" ], "return_type": { - "value": "uint64x1x2_t" + "value": "uint8x16x3_t" }, "Arguments_Preparation": { "ptr": { @@ -40647,12 +235309,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2_u8", + "name": "vld1q_u8_x4", "arguments": [ "uint8_t const * ptr" ], "return_type": { - "value": "uint8x8x2_t" + "value": "uint8x16x4_t" }, "Arguments_Preparation": { "ptr": { @@ -40666,18 +235328,18 @@ ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2q_dup_f16", + "name": "vld2_dup_f16", "arguments": [ "float16_t const * ptr" ], "return_type": { - "value": "float16x8x2_t" + "value": "float16x4x2_t" }, "Arguments_Preparation": { "ptr": { @@ -40697,12 +235359,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_dup_f32", + "name": "vld2_dup_f32", "arguments": [ "float32_t const * ptr" ], "return_type": { - "value": "float32x4x2_t" + "value": "float32x2x2_t" }, "Arguments_Preparation": { "ptr": { @@ -40722,12 +235384,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_dup_f64", + "name": "vld2_dup_f64", "arguments": [ "float64_t const * ptr" ], "return_type": { - "value": "float64x2x2_t" + "value": "float64x1x2_t" }, "Arguments_Preparation": { "ptr": { @@ -40745,12 +235407,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_dup_p16", + "name": "vld2_dup_p16", "arguments": [ "poly16_t const * ptr" ], "return_type": { - "value": "poly16x8x2_t" + "value": "poly16x4x2_t" }, "Arguments_Preparation": { "ptr": { @@ -40770,12 +235432,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_dup_p64", + "name": "vld2_dup_p64", "arguments": [ "poly64_t const * ptr" ], "return_type": { - "value": "poly64x2x2_t" + "value": "poly64x1x2_t" }, "Arguments_Preparation": { "ptr": { @@ -40783,6 +235445,7 @@ } }, "Architectures": [ + "A32", "A64" ], "instructions": [ @@ -40793,12 +235456,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_dup_p8", + "name": "vld2_dup_p8", "arguments": [ "poly8_t const * ptr" ], "return_type": { - "value": "poly8x16x2_t" + "value": "poly8x8x2_t" }, "Arguments_Preparation": { "ptr": { @@ -40818,12 +235481,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_dup_s16", + "name": "vld2_dup_s16", "arguments": [ "int16_t const * ptr" ], "return_type": { - "value": "int16x8x2_t" + "value": "int16x4x2_t" }, "Arguments_Preparation": { "ptr": { @@ -40843,12 +235506,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_dup_s32", + "name": "vld2_dup_s32", "arguments": [ "int32_t const * ptr" ], "return_type": { - "value": "int32x4x2_t" + "value": "int32x2x2_t" }, "Arguments_Preparation": { "ptr": { @@ -40868,12 +235531,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_dup_s64", + "name": "vld2_dup_s64", "arguments": [ "int64_t const * ptr" ], "return_type": { - "value": "int64x2x2_t" + "value": "int64x1x2_t" }, "Arguments_Preparation": { "ptr": { @@ -40881,6 +235544,8 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -40891,12 +235556,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_dup_s8", + "name": "vld2_dup_s8", "arguments": [ "int8_t const * ptr" ], "return_type": { - "value": "int8x16x2_t" + "value": "int8x8x2_t" }, "Arguments_Preparation": { "ptr": { @@ -40916,12 +235581,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_dup_u16", + "name": "vld2_dup_u16", "arguments": [ "uint16_t const * ptr" ], "return_type": { - "value": "uint16x8x2_t" + "value": "uint16x4x2_t" }, "Arguments_Preparation": { "ptr": { @@ -40941,12 +235606,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_dup_u32", + "name": "vld2_dup_u32", "arguments": [ "uint32_t const * ptr" ], "return_type": { - "value": "uint32x4x2_t" + "value": "uint32x2x2_t" }, "Arguments_Preparation": { "ptr": { @@ -40966,12 +235631,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_dup_u64", + "name": "vld2_dup_u64", "arguments": [ "uint64_t const * ptr" ], "return_type": { - "value": "uint64x2x2_t" + "value": "uint64x1x2_t" }, "Arguments_Preparation": { "ptr": { @@ -40979,6 +235644,8 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -40989,12 +235656,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_dup_u8", + "name": "vld2_dup_u8", "arguments": [ "uint8_t const * ptr" ], "return_type": { - "value": "uint8x16x2_t" + "value": "uint8x8x2_t" }, "Arguments_Preparation": { "ptr": { @@ -41014,12 +235681,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_f16", + "name": "vld2_f16", "arguments": [ "float16_t const * ptr" ], "return_type": { - "value": "float16x8x2_t" + "value": "float16x4x2_t" }, "Arguments_Preparation": { "ptr": { @@ -41039,12 +235706,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_f32", + "name": "vld2_f32", "arguments": [ "float32_t const * ptr" ], "return_type": { - "value": "float32x4x2_t" + "value": "float32x2x2_t" }, "Arguments_Preparation": { "ptr": { @@ -41064,12 +235731,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_f64", + "name": "vld2_f64", "arguments": [ "float64_t const * ptr" ], "return_type": { - "value": "float64x2x2_t" + "value": "float64x1x2_t" }, "Arguments_Preparation": { "ptr": { @@ -41081,31 +235748,34 @@ ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2q_lane_f16", + "name": "vld2_lane_f16", "arguments": [ "float16_t const * ptr", - "float16x8x2_t src", + "float16x4x2_t src", "const int lane" ], "return_type": { - "value": "float16x8x2_t" + "value": "float16x4x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt2.8H" + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -41121,25 +235791,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_lane_f32", + "name": "vld2_lane_f32", "arguments": [ "float32_t const * ptr", - "float32x4x2_t src", + "float32x2x2_t src", "const int lane" ], "return_type": { - "value": "float32x4x2_t" + "value": "float32x2x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt2.4S" + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" } }, "Architectures": [ @@ -41155,25 +235828,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_lane_f64", + "name": "vld2_lane_f64", "arguments": [ "float64_t const * ptr", - "float64x2x2_t src", + "float64x1x2_t src", "const int lane" ], "return_type": { - "value": "float64x2x2_t" + "value": "float64x1x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt2.2D" + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ @@ -41187,25 +235863,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_lane_p16", + "name": "vld2_lane_p16", "arguments": [ "poly16_t const * ptr", - "poly16x8x2_t src", + "poly16x4x2_t src", "const int lane" ], "return_type": { - "value": "poly16x8x2_t" + "value": "poly16x4x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt2.8H" + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -41221,25 +235900,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_lane_p64", + "name": "vld2_lane_p64", "arguments": [ "poly64_t const * ptr", - "poly64x2x2_t src", + "poly64x1x2_t src", "const int lane" ], "return_type": { - "value": "poly64x2x2_t" + "value": "poly64x1x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt2.2D" + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ @@ -41253,28 +235935,33 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_lane_p8", + "name": "vld2_lane_p8", "arguments": [ "poly8_t const * ptr", - "poly8x16x2_t src", + "poly8x8x2_t src", "const int lane" ], "return_type": { - "value": "poly8x16x2_t" + "value": "poly8x8x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 15 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt2.16B" + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -41285,25 +235972,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_lane_s16", + "name": "vld2_lane_s16", "arguments": [ "int16_t const * ptr", - "int16x8x2_t src", + "int16x4x2_t src", "const int lane" ], "return_type": { - "value": "int16x8x2_t" + "value": "int16x4x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt2.8H" + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -41319,25 +236009,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_lane_s32", + "name": "vld2_lane_s32", "arguments": [ "int32_t const * ptr", - "int32x4x2_t src", + "int32x2x2_t src", "const int lane" ], "return_type": { - "value": "int32x4x2_t" + "value": "int32x2x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt2.4S" + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" } }, "Architectures": [ @@ -41353,25 +236046,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_lane_s64", + "name": "vld2_lane_s64", "arguments": [ "int64_t const * ptr", - "int64x2x2_t src", + "int64x1x2_t src", "const int lane" ], "return_type": { - "value": "int64x2x2_t" + "value": "int64x1x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt2.2D" + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ @@ -41385,28 +236081,33 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_lane_s8", + "name": "vld2_lane_s8", "arguments": [ "int8_t const * ptr", - "int8x16x2_t src", + "int8x8x2_t src", "const int lane" ], "return_type": { - "value": "int8x16x2_t" + "value": "int8x8x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 15 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt2.16B" + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -41417,25 +236118,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_lane_u16", + "name": "vld2_lane_u16", "arguments": [ "uint16_t const * ptr", - "uint16x8x2_t src", + "uint16x4x2_t src", "const int lane" ], "return_type": { - "value": "uint16x8x2_t" + "value": "uint16x4x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt2.8H" + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -41451,25 +236155,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_lane_u32", + "name": "vld2_lane_u32", "arguments": [ "uint32_t const * ptr", - "uint32x4x2_t src", + "uint32x2x2_t src", "const int lane" ], "return_type": { - "value": "uint32x4x2_t" + "value": "uint32x2x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt2.4S" + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" } }, "Architectures": [ @@ -41485,25 +236192,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_lane_u64", + "name": "vld2_lane_u64", "arguments": [ "uint64_t const * ptr", - "uint64x2x2_t src", + "uint64x1x2_t src", "const int lane" ], "return_type": { - "value": "uint64x2x2_t" + "value": "uint64x1x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt2.2D" + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ @@ -41517,28 +236227,33 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_lane_u8", + "name": "vld2_lane_u8", "arguments": [ "uint8_t const * ptr", - "uint8x16x2_t src", + "uint8x8x2_t src", "const int lane" ], "return_type": { - "value": "uint8x16x2_t" + "value": "uint8x8x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 15 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt2.16B" + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -41549,12 +236264,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_p16", + "name": "vld2_p16", "arguments": [ "poly16_t const * ptr" ], "return_type": { - "value": "poly16x8x2_t" + "value": "poly16x4x2_t" }, "Arguments_Preparation": { "ptr": { @@ -41574,12 +236289,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_p64", + "name": "vld2_p64", "arguments": [ "poly64_t const * ptr" ], "return_type": { - "value": "poly64x2x2_t" + "value": "poly64x1x2_t" }, "Arguments_Preparation": { "ptr": { @@ -41587,22 +236302,23 @@ } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2q_p8", + "name": "vld2_p8", "arguments": [ "poly8_t const * ptr" ], "return_type": { - "value": "poly8x16x2_t" + "value": "poly8x8x2_t" }, "Arguments_Preparation": { "ptr": { @@ -41622,12 +236338,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_s16", + "name": "vld2_s16", "arguments": [ "int16_t const * ptr" ], "return_type": { - "value": "int16x8x2_t" + "value": "int16x4x2_t" }, "Arguments_Preparation": { "ptr": { @@ -41647,12 +236363,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_s32", + "name": "vld2_s32", "arguments": [ "int32_t const * ptr" ], "return_type": { - "value": "int32x4x2_t" + "value": "int32x2x2_t" }, "Arguments_Preparation": { "ptr": { @@ -41672,12 +236388,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_s64", + "name": "vld2_s64", "arguments": [ "int64_t const * ptr" ], "return_type": { - "value": "int64x2x2_t" + "value": "int64x1x2_t" }, "Arguments_Preparation": { "ptr": { @@ -41685,22 +236401,24 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2q_s8", + "name": "vld2_s8", "arguments": [ "int8_t const * ptr" ], "return_type": { - "value": "int8x16x2_t" + "value": "int8x8x2_t" }, "Arguments_Preparation": { "ptr": { @@ -41720,12 +236438,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_u16", + "name": "vld2_u16", "arguments": [ "uint16_t const * ptr" ], "return_type": { - "value": "uint16x8x2_t" + "value": "uint16x4x2_t" }, "Arguments_Preparation": { "ptr": { @@ -41745,12 +236463,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_u32", + "name": "vld2_u32", "arguments": [ "uint32_t const * ptr" ], "return_type": { - "value": "uint32x4x2_t" + "value": "uint32x2x2_t" }, "Arguments_Preparation": { "ptr": { @@ -41770,12 +236488,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld2q_u64", + "name": "vld2_u64", "arguments": [ "uint64_t const * ptr" ], "return_type": { - "value": "uint64x2x2_t" + "value": "uint64x1x2_t" }, "Arguments_Preparation": { "ptr": { @@ -41783,22 +236501,24 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LD2" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld2q_u8", + "name": "vld2_u8", "arguments": [ "uint8_t const * ptr" ], "return_type": { - "value": "uint8x16x2_t" + "value": "uint8x8x2_t" }, "Arguments_Preparation": { "ptr": { @@ -41818,12 +236538,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3_dup_f16", + "name": "vld2q_dup_f16", "arguments": [ "float16_t const * ptr" ], "return_type": { - "value": "float16x4x3_t" + "value": "float16x8x2_t" }, "Arguments_Preparation": { "ptr": { @@ -41837,18 +236557,18 @@ ], "instructions": [ [ - "LD3R" + "LD2R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_dup_f32", + "name": "vld2q_dup_f32", "arguments": [ "float32_t const * ptr" ], "return_type": { - "value": "float32x2x3_t" + "value": "float32x4x2_t" }, "Arguments_Preparation": { "ptr": { @@ -41862,18 +236582,18 @@ ], "instructions": [ [ - "LD3R" + "LD2R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_dup_f64", + "name": "vld2q_dup_f64", "arguments": [ "float64_t const * ptr" ], "return_type": { - "value": "float64x1x3_t" + "value": "float64x2x2_t" }, "Arguments_Preparation": { "ptr": { @@ -41885,18 +236605,18 @@ ], "instructions": [ [ - "LD3R" + "LD2R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_dup_p16", + "name": "vld2q_dup_p16", "arguments": [ "poly16_t const * ptr" ], "return_type": { - "value": "poly16x4x3_t" + "value": "poly16x8x2_t" }, "Arguments_Preparation": { "ptr": { @@ -41910,18 +236630,18 @@ ], "instructions": [ [ - "LD3R" + "LD2R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_dup_p64", + "name": "vld2q_dup_p64", "arguments": [ "poly64_t const * ptr" ], "return_type": { - "value": "poly64x1x3_t" + "value": "poly64x2x2_t" }, "Arguments_Preparation": { "ptr": { @@ -41929,23 +236649,22 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "LD3R" + "LD2R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_dup_p8", + "name": "vld2q_dup_p8", "arguments": [ "poly8_t const * ptr" ], "return_type": { - "value": "poly8x8x3_t" + "value": "poly8x16x2_t" }, "Arguments_Preparation": { "ptr": { @@ -41959,18 +236678,18 @@ ], "instructions": [ [ - "LD3R" + "LD2R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_dup_s16", + "name": "vld2q_dup_s16", "arguments": [ "int16_t const * ptr" ], "return_type": { - "value": "int16x4x3_t" + "value": "int16x8x2_t" }, "Arguments_Preparation": { "ptr": { @@ -41984,18 +236703,18 @@ ], "instructions": [ [ - "LD3R" + "LD2R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_dup_s32", + "name": "vld2q_dup_s32", "arguments": [ "int32_t const * ptr" ], "return_type": { - "value": "int32x2x3_t" + "value": "int32x4x2_t" }, "Arguments_Preparation": { "ptr": { @@ -42009,18 +236728,18 @@ ], "instructions": [ [ - "LD3R" + "LD2R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_dup_s64", + "name": "vld2q_dup_s64", "arguments": [ "int64_t const * ptr" ], "return_type": { - "value": "int64x1x3_t" + "value": "int64x2x2_t" }, "Arguments_Preparation": { "ptr": { @@ -42028,24 +236747,22 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "LD3R" + "LD2R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_dup_s8", + "name": "vld2q_dup_s8", "arguments": [ "int8_t const * ptr" ], "return_type": { - "value": "int8x8x3_t" + "value": "int8x16x2_t" }, "Arguments_Preparation": { "ptr": { @@ -42059,18 +236776,18 @@ ], "instructions": [ [ - "LD3R" + "LD2R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_dup_u16", + "name": "vld2q_dup_u16", "arguments": [ "uint16_t const * ptr" ], "return_type": { - "value": "uint16x4x3_t" + "value": "uint16x8x2_t" }, "Arguments_Preparation": { "ptr": { @@ -42084,18 +236801,18 @@ ], "instructions": [ [ - "LD3R" + "LD2R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_dup_u32", + "name": "vld2q_dup_u32", "arguments": [ "uint32_t const * ptr" ], "return_type": { - "value": "uint32x2x3_t" + "value": "uint32x4x2_t" }, "Arguments_Preparation": { "ptr": { @@ -42109,18 +236826,18 @@ ], "instructions": [ [ - "LD3R" + "LD2R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_dup_u64", + "name": "vld2q_dup_u64", "arguments": [ "uint64_t const * ptr" ], "return_type": { - "value": "uint64x1x3_t" + "value": "uint64x2x2_t" }, "Arguments_Preparation": { "ptr": { @@ -42128,24 +236845,22 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "LD3R" + "LD2R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_dup_u8", + "name": "vld2q_dup_u8", "arguments": [ "uint8_t const * ptr" ], "return_type": { - "value": "uint8x8x3_t" + "value": "uint8x16x2_t" }, "Arguments_Preparation": { "ptr": { @@ -42159,18 +236874,18 @@ ], "instructions": [ [ - "LD3R" + "LD2R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_f16", + "name": "vld2q_f16", "arguments": [ "float16_t const * ptr" ], "return_type": { - "value": "float16x4x3_t" + "value": "float16x8x2_t" }, "Arguments_Preparation": { "ptr": { @@ -42184,18 +236899,18 @@ ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_f32", + "name": "vld2q_f32", "arguments": [ "float32_t const * ptr" ], "return_type": { - "value": "float32x2x3_t" + "value": "float32x4x2_t" }, "Arguments_Preparation": { "ptr": { @@ -42209,18 +236924,18 @@ ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_f64", + "name": "vld2q_f64", "arguments": [ "float64_t const * ptr" ], "return_type": { - "value": "float64x1x3_t" + "value": "float64x2x2_t" }, "Arguments_Preparation": { "ptr": { @@ -42232,31 +236947,34 @@ ], "instructions": [ [ - "LD1" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_lane_f16", + "name": "vld2q_lane_f16", "arguments": [ "float16_t const * ptr", - "float16x4x3_t src", + "float16x8x2_t src", "const int lane" ], "return_type": { - "value": "float16x4x3_t" + "value": "float16x8x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.4H" + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -42266,31 +236984,34 @@ ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_lane_f32", + "name": "vld2q_lane_f32", "arguments": [ "float32_t const * ptr", - "float32x2x3_t src", + "float32x4x2_t src", "const int lane" ], "return_type": { - "value": "float32x2x3_t" + "value": "float32x4x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.2S" + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" } }, "Architectures": [ @@ -42300,31 +237021,34 @@ ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_lane_f64", + "name": "vld2q_lane_f64", "arguments": [ "float64_t const * ptr", - "float64x1x3_t src", + "float64x2x2_t src", "const int lane" ], "return_type": { - "value": "float64x1x3_t" + "value": "float64x2x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 0 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.1D" + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ @@ -42332,31 +237056,34 @@ ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_lane_p16", + "name": "vld2q_lane_p16", "arguments": [ "poly16_t const * ptr", - "poly16x4x3_t src", + "poly16x8x2_t src", "const int lane" ], "return_type": { - "value": "poly16x4x3_t" + "value": "poly16x8x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.4H" + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -42366,31 +237093,34 @@ ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_lane_p64", + "name": "vld2q_lane_p64", "arguments": [ "poly64_t const * ptr", - "poly64x1x3_t src", + "poly64x2x2_t src", "const int lane" ], "return_type": { - "value": "poly64x1x3_t" + "value": "poly64x2x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 0 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.1D" + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ @@ -42398,65 +237128,69 @@ ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_lane_p8", + "name": "vld2q_lane_p8", "arguments": [ "poly8_t const * ptr", - "poly8x8x3_t src", + "poly8x16x2_t src", "const int lane" ], "return_type": { - "value": "poly8x8x3_t" + "value": "poly8x16x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 15 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.8B" + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_lane_s16", + "name": "vld2q_lane_s16", "arguments": [ "int16_t const * ptr", - "int16x4x3_t src", + "int16x8x2_t src", "const int lane" ], "return_type": { - "value": "int16x4x3_t" + "value": "int16x8x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.4H" + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -42466,31 +237200,34 @@ ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_lane_s32", + "name": "vld2q_lane_s32", "arguments": [ "int32_t const * ptr", - "int32x2x3_t src", + "int32x4x2_t src", "const int lane" ], "return_type": { - "value": "int32x2x3_t" + "value": "int32x4x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.2S" + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" } }, "Architectures": [ @@ -42500,31 +237237,34 @@ ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_lane_s64", + "name": "vld2q_lane_s64", "arguments": [ "int64_t const * ptr", - "int64x1x3_t src", + "int64x2x2_t src", "const int lane" ], "return_type": { - "value": "int64x1x3_t" + "value": "int64x2x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 0 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.1D" + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ @@ -42532,65 +237272,69 @@ ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_lane_s8", + "name": "vld2q_lane_s8", "arguments": [ "int8_t const * ptr", - "int8x8x3_t src", + "int8x16x2_t src", "const int lane" ], "return_type": { - "value": "int8x8x3_t" + "value": "int8x16x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 15 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.8B" + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_lane_u16", + "name": "vld2q_lane_u16", "arguments": [ "uint16_t const * ptr", - "uint16x4x3_t src", + "uint16x8x2_t src", "const int lane" ], "return_type": { - "value": "uint16x4x3_t" + "value": "uint16x8x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.4H" + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -42600,31 +237344,34 @@ ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_lane_u32", + "name": "vld2q_lane_u32", "arguments": [ "uint32_t const * ptr", - "uint32x2x3_t src", + "uint32x4x2_t src", "const int lane" ], "return_type": { - "value": "uint32x2x3_t" + "value": "uint32x4x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.2S" + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" } }, "Architectures": [ @@ -42634,31 +237381,34 @@ ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_lane_u64", + "name": "vld2q_lane_u64", "arguments": [ "uint64_t const * ptr", - "uint64x1x3_t src", + "uint64x2x2_t src", "const int lane" ], "return_type": { - "value": "uint64x1x3_t" + "value": "uint64x2x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 0 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.1D" + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ @@ -42666,52 +237416,53 @@ ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_lane_u8", + "name": "vld2q_lane_u8", "arguments": [ "uint8_t const * ptr", - "uint8x8x3_t src", + "uint8x16x2_t src", "const int lane" ], "return_type": { - "value": "uint8x8x3_t" + "value": "uint8x16x2_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 15 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.8B" + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_p16", + "name": "vld2q_p16", "arguments": [ "poly16_t const * ptr" ], "return_type": { - "value": "poly16x4x3_t" + "value": "poly16x8x2_t" }, "Arguments_Preparation": { "ptr": { @@ -42725,18 +237476,18 @@ ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_p64", + "name": "vld2q_p64", "arguments": [ "poly64_t const * ptr" ], "return_type": { - "value": "poly64x1x3_t" + "value": "poly64x2x2_t" }, "Arguments_Preparation": { "ptr": { @@ -42744,23 +237495,22 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "LD1" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_p8", + "name": "vld2q_p8", "arguments": [ "poly8_t const * ptr" ], "return_type": { - "value": "poly8x8x3_t" + "value": "poly8x16x2_t" }, "Arguments_Preparation": { "ptr": { @@ -42774,18 +237524,18 @@ ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_s16", + "name": "vld2q_s16", "arguments": [ "int16_t const * ptr" ], "return_type": { - "value": "int16x4x3_t" + "value": "int16x8x2_t" }, "Arguments_Preparation": { "ptr": { @@ -42799,18 +237549,18 @@ ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_s32", + "name": "vld2q_s32", "arguments": [ "int32_t const * ptr" ], "return_type": { - "value": "int32x2x3_t" + "value": "int32x4x2_t" }, "Arguments_Preparation": { "ptr": { @@ -42824,18 +237574,18 @@ ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_s64", + "name": "vld2q_s64", "arguments": [ "int64_t const * ptr" ], "return_type": { - "value": "int64x1x3_t" + "value": "int64x2x2_t" }, "Arguments_Preparation": { "ptr": { @@ -42843,24 +237593,22 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "LD1" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_s8", + "name": "vld2q_s8", "arguments": [ "int8_t const * ptr" ], "return_type": { - "value": "int8x8x3_t" + "value": "int8x16x2_t" }, "Arguments_Preparation": { "ptr": { @@ -42874,18 +237622,18 @@ ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_u16", + "name": "vld2q_u16", "arguments": [ "uint16_t const * ptr" ], "return_type": { - "value": "uint16x4x3_t" + "value": "uint16x8x2_t" }, "Arguments_Preparation": { "ptr": { @@ -42899,18 +237647,18 @@ ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_u32", + "name": "vld2q_u32", "arguments": [ "uint32_t const * ptr" ], "return_type": { - "value": "uint32x2x3_t" + "value": "uint32x4x2_t" }, "Arguments_Preparation": { "ptr": { @@ -42924,18 +237672,18 @@ ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_u64", + "name": "vld2q_u64", "arguments": [ "uint64_t const * ptr" ], "return_type": { - "value": "uint64x1x3_t" + "value": "uint64x2x2_t" }, "Arguments_Preparation": { "ptr": { @@ -42943,24 +237691,22 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "LD1" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3_u8", + "name": "vld2q_u8", "arguments": [ "uint8_t const * ptr" ], "return_type": { - "value": "uint8x8x3_t" + "value": "uint8x16x2_t" }, "Arguments_Preparation": { "ptr": { @@ -42974,18 +237720,18 @@ ], "instructions": [ [ - "LD3" + "LD2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3q_dup_f16", + "name": "vld3_dup_f16", "arguments": [ "float16_t const * ptr" ], "return_type": { - "value": "float16x8x3_t" + "value": "float16x4x3_t" }, "Arguments_Preparation": { "ptr": { @@ -43005,12 +237751,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_dup_f32", + "name": "vld3_dup_f32", "arguments": [ "float32_t const * ptr" ], "return_type": { - "value": "float32x4x3_t" + "value": "float32x2x3_t" }, "Arguments_Preparation": { "ptr": { @@ -43030,12 +237776,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_dup_f64", + "name": "vld3_dup_f64", "arguments": [ "float64_t const * ptr" ], "return_type": { - "value": "float64x2x3_t" + "value": "float64x1x3_t" }, "Arguments_Preparation": { "ptr": { @@ -43053,12 +237799,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_dup_p16", + "name": "vld3_dup_p16", "arguments": [ "poly16_t const * ptr" ], "return_type": { - "value": "poly16x8x3_t" + "value": "poly16x4x3_t" }, "Arguments_Preparation": { "ptr": { @@ -43078,12 +237824,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_dup_p64", + "name": "vld3_dup_p64", "arguments": [ "poly64_t const * ptr" ], "return_type": { - "value": "poly64x2x3_t" + "value": "poly64x1x3_t" }, "Arguments_Preparation": { "ptr": { @@ -43091,6 +237837,7 @@ } }, "Architectures": [ + "A32", "A64" ], "instructions": [ @@ -43101,12 +237848,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_dup_p8", + "name": "vld3_dup_p8", "arguments": [ "poly8_t const * ptr" ], "return_type": { - "value": "poly8x16x3_t" + "value": "poly8x8x3_t" }, "Arguments_Preparation": { "ptr": { @@ -43126,12 +237873,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_dup_s16", + "name": "vld3_dup_s16", "arguments": [ "int16_t const * ptr" ], "return_type": { - "value": "int16x8x3_t" + "value": "int16x4x3_t" }, "Arguments_Preparation": { "ptr": { @@ -43151,12 +237898,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_dup_s32", + "name": "vld3_dup_s32", "arguments": [ "int32_t const * ptr" ], "return_type": { - "value": "int32x4x3_t" + "value": "int32x2x3_t" }, "Arguments_Preparation": { "ptr": { @@ -43176,12 +237923,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_dup_s64", + "name": "vld3_dup_s64", "arguments": [ "int64_t const * ptr" ], "return_type": { - "value": "int64x2x3_t" + "value": "int64x1x3_t" }, "Arguments_Preparation": { "ptr": { @@ -43189,6 +237936,8 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -43199,12 +237948,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_dup_s8", + "name": "vld3_dup_s8", "arguments": [ "int8_t const * ptr" ], "return_type": { - "value": "int8x16x3_t" + "value": "int8x8x3_t" }, "Arguments_Preparation": { "ptr": { @@ -43224,12 +237973,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_dup_u16", + "name": "vld3_dup_u16", "arguments": [ "uint16_t const * ptr" ], "return_type": { - "value": "uint16x8x3_t" + "value": "uint16x4x3_t" }, "Arguments_Preparation": { "ptr": { @@ -43249,12 +237998,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_dup_u32", + "name": "vld3_dup_u32", "arguments": [ "uint32_t const * ptr" ], "return_type": { - "value": "uint32x4x3_t" + "value": "uint32x2x3_t" }, "Arguments_Preparation": { "ptr": { @@ -43274,12 +238023,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_dup_u64", + "name": "vld3_dup_u64", "arguments": [ "uint64_t const * ptr" ], "return_type": { - "value": "uint64x2x3_t" + "value": "uint64x1x3_t" }, "Arguments_Preparation": { "ptr": { @@ -43287,6 +238036,8 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -43297,12 +238048,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_dup_u8", + "name": "vld3_dup_u8", "arguments": [ "uint8_t const * ptr" ], "return_type": { - "value": "uint8x16x3_t" + "value": "uint8x8x3_t" }, "Arguments_Preparation": { "ptr": { @@ -43322,12 +238073,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_f16", + "name": "vld3_f16", "arguments": [ "float16_t const * ptr" ], "return_type": { - "value": "float16x8x3_t" + "value": "float16x4x3_t" }, "Arguments_Preparation": { "ptr": { @@ -43347,12 +238098,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_f32", + "name": "vld3_f32", "arguments": [ "float32_t const * ptr" ], "return_type": { - "value": "float32x4x3_t" + "value": "float32x2x3_t" }, "Arguments_Preparation": { "ptr": { @@ -43372,12 +238123,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_f64", + "name": "vld3_f64", "arguments": [ "float64_t const * ptr" ], "return_type": { - "value": "float64x2x3_t" + "value": "float64x1x3_t" }, "Arguments_Preparation": { "ptr": { @@ -43389,31 +238140,37 @@ ], "instructions": [ [ - "LD3" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3q_lane_f16", + "name": "vld3_lane_f16", "arguments": [ "float16_t const * ptr", - "float16x8x3_t src", + "float16x4x3_t src", "const int lane" ], "return_type": { - "value": "float16x8x3_t" + "value": "float16x4x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.8H" + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -43429,25 +238186,31 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_lane_f32", + "name": "vld3_lane_f32", "arguments": [ "float32_t const * ptr", - "float32x4x3_t src", + "float32x2x3_t src", "const int lane" ], "return_type": { - "value": "float32x4x3_t" + "value": "float32x2x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.4S" + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { + "register": "Vt3.2S" } }, "Architectures": [ @@ -43463,25 +238226,31 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_lane_f64", + "name": "vld3_lane_f64", "arguments": [ "float64_t const * ptr", - "float64x2x3_t src", + "float64x1x3_t src", "const int lane" ], "return_type": { - "value": "float64x2x3_t" + "value": "float64x1x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.2D" + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ @@ -43495,25 +238264,31 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_lane_p16", + "name": "vld3_lane_p16", "arguments": [ "poly16_t const * ptr", - "poly16x8x3_t src", + "poly16x4x3_t src", "const int lane" ], "return_type": { - "value": "poly16x8x3_t" + "value": "poly16x4x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.8H" + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -43529,25 +238304,31 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_lane_p64", + "name": "vld3_lane_p64", "arguments": [ "poly64_t const * ptr", - "poly64x2x3_t src", + "poly64x1x3_t src", "const int lane" ], "return_type": { - "value": "poly64x2x3_t" + "value": "poly64x1x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.2D" + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ @@ -43561,28 +238342,36 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_lane_p8", + "name": "vld3_lane_p8", "arguments": [ "poly8_t const * ptr", - "poly8x16x3_t src", + "poly8x8x3_t src", "const int lane" ], "return_type": { - "value": "poly8x16x3_t" + "value": "poly8x8x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 15 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.16B" + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { + "register": "Vt3.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -43593,25 +238382,31 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_lane_s16", + "name": "vld3_lane_s16", "arguments": [ "int16_t const * ptr", - "int16x8x3_t src", + "int16x4x3_t src", "const int lane" ], "return_type": { - "value": "int16x8x3_t" + "value": "int16x4x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.8H" + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -43627,25 +238422,31 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_lane_s32", + "name": "vld3_lane_s32", "arguments": [ "int32_t const * ptr", - "int32x4x3_t src", + "int32x2x3_t src", "const int lane" ], "return_type": { - "value": "int32x4x3_t" + "value": "int32x2x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.4S" + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { + "register": "Vt3.2S" } }, "Architectures": [ @@ -43661,25 +238462,31 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_lane_s64", + "name": "vld3_lane_s64", "arguments": [ "int64_t const * ptr", - "int64x2x3_t src", + "int64x1x3_t src", "const int lane" ], "return_type": { - "value": "int64x2x3_t" + "value": "int64x1x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.2D" + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ @@ -43693,28 +238500,36 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_lane_s8", + "name": "vld3_lane_s8", "arguments": [ "int8_t const * ptr", - "int8x16x3_t src", + "int8x8x3_t src", "const int lane" ], "return_type": { - "value": "int8x16x3_t" + "value": "int8x8x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 15 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.16B" + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { + "register": "Vt3.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -43725,25 +238540,31 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_lane_u16", + "name": "vld3_lane_u16", "arguments": [ "uint16_t const * ptr", - "uint16x8x3_t src", + "uint16x4x3_t src", "const int lane" ], "return_type": { - "value": "uint16x8x3_t" + "value": "uint16x4x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.8H" + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -43759,25 +238580,31 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_lane_u32", + "name": "vld3_lane_u32", "arguments": [ "uint32_t const * ptr", - "uint32x4x3_t src", + "uint32x2x3_t src", "const int lane" ], "return_type": { - "value": "uint32x4x3_t" + "value": "uint32x2x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.4S" + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { + "register": "Vt3.2S" } }, "Architectures": [ @@ -43793,25 +238620,31 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_lane_u64", + "name": "vld3_lane_u64", "arguments": [ "uint64_t const * ptr", - "uint64x2x3_t src", + "uint64x1x3_t src", "const int lane" ], "return_type": { - "value": "uint64x2x3_t" + "value": "uint64x1x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.2D" + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ @@ -43825,28 +238658,36 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_lane_u8", + "name": "vld3_lane_u8", "arguments": [ "uint8_t const * ptr", - "uint8x16x3_t src", + "uint8x8x3_t src", "const int lane" ], "return_type": { - "value": "uint8x16x3_t" + "value": "uint8x8x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 15 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt3.16B" + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { + "register": "Vt3.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -43857,12 +238698,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_p16", + "name": "vld3_p16", "arguments": [ "poly16_t const * ptr" ], "return_type": { - "value": "poly16x8x3_t" + "value": "poly16x4x3_t" }, "Arguments_Preparation": { "ptr": { @@ -43882,12 +238723,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_p64", + "name": "vld3_p64", "arguments": [ "poly64_t const * ptr" ], "return_type": { - "value": "poly64x2x3_t" + "value": "poly64x1x3_t" }, "Arguments_Preparation": { "ptr": { @@ -43895,22 +238736,23 @@ } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "LD3" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3q_p8", + "name": "vld3_p8", "arguments": [ "poly8_t const * ptr" ], "return_type": { - "value": "poly8x16x3_t" + "value": "poly8x8x3_t" }, "Arguments_Preparation": { "ptr": { @@ -43930,12 +238772,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_s16", + "name": "vld3_s16", "arguments": [ "int16_t const * ptr" ], "return_type": { - "value": "int16x8x3_t" + "value": "int16x4x3_t" }, "Arguments_Preparation": { "ptr": { @@ -43955,12 +238797,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_s32", + "name": "vld3_s32", "arguments": [ "int32_t const * ptr" ], "return_type": { - "value": "int32x4x3_t" + "value": "int32x2x3_t" }, "Arguments_Preparation": { "ptr": { @@ -43980,12 +238822,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_s64", + "name": "vld3_s64", "arguments": [ "int64_t const * ptr" ], "return_type": { - "value": "int64x2x3_t" + "value": "int64x1x3_t" }, "Arguments_Preparation": { "ptr": { @@ -43993,22 +238835,24 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LD3" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3q_s8", + "name": "vld3_s8", "arguments": [ "int8_t const * ptr" ], "return_type": { - "value": "int8x16x3_t" + "value": "int8x8x3_t" }, "Arguments_Preparation": { "ptr": { @@ -44028,12 +238872,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_u16", + "name": "vld3_u16", "arguments": [ "uint16_t const * ptr" ], "return_type": { - "value": "uint16x8x3_t" + "value": "uint16x4x3_t" }, "Arguments_Preparation": { "ptr": { @@ -44053,12 +238897,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_u32", + "name": "vld3_u32", "arguments": [ "uint32_t const * ptr" ], "return_type": { - "value": "uint32x4x3_t" + "value": "uint32x2x3_t" }, "Arguments_Preparation": { "ptr": { @@ -44078,12 +238922,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld3q_u64", + "name": "vld3_u64", "arguments": [ "uint64_t const * ptr" ], "return_type": { - "value": "uint64x2x3_t" + "value": "uint64x1x3_t" }, "Arguments_Preparation": { "ptr": { @@ -44091,22 +238935,24 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LD3" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld3q_u8", + "name": "vld3_u8", "arguments": [ "uint8_t const * ptr" ], "return_type": { - "value": "uint8x16x3_t" + "value": "uint8x8x3_t" }, "Arguments_Preparation": { "ptr": { @@ -44126,12 +238972,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4_dup_f16", + "name": "vld3q_dup_f16", "arguments": [ "float16_t const * ptr" ], "return_type": { - "value": "float16x4x4_t" + "value": "float16x8x3_t" }, "Arguments_Preparation": { "ptr": { @@ -44145,18 +238991,18 @@ ], "instructions": [ [ - "LD4R" + "LD3R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_dup_f32", + "name": "vld3q_dup_f32", "arguments": [ "float32_t const * ptr" ], "return_type": { - "value": "float32x2x4_t" + "value": "float32x4x3_t" }, "Arguments_Preparation": { "ptr": { @@ -44170,18 +239016,18 @@ ], "instructions": [ [ - "LD4R" + "LD3R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_dup_f64", + "name": "vld3q_dup_f64", "arguments": [ "float64_t const * ptr" ], "return_type": { - "value": "float64x1x4_t" + "value": "float64x2x3_t" }, "Arguments_Preparation": { "ptr": { @@ -44193,18 +239039,18 @@ ], "instructions": [ [ - "LD4R" + "LD3R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_dup_p16", + "name": "vld3q_dup_p16", "arguments": [ "poly16_t const * ptr" ], "return_type": { - "value": "poly16x4x4_t" + "value": "poly16x8x3_t" }, "Arguments_Preparation": { "ptr": { @@ -44218,18 +239064,18 @@ ], "instructions": [ [ - "LD4R" + "LD3R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_dup_p64", + "name": "vld3q_dup_p64", "arguments": [ "poly64_t const * ptr" ], "return_type": { - "value": "poly64x1x4_t" + "value": "poly64x2x3_t" }, "Arguments_Preparation": { "ptr": { @@ -44237,23 +239083,22 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "LD4R" + "LD3R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_dup_p8", + "name": "vld3q_dup_p8", "arguments": [ "poly8_t const * ptr" ], "return_type": { - "value": "poly8x8x4_t" + "value": "poly8x16x3_t" }, "Arguments_Preparation": { "ptr": { @@ -44267,18 +239112,18 @@ ], "instructions": [ [ - "LD4R" + "LD3R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_dup_s16", + "name": "vld3q_dup_s16", "arguments": [ "int16_t const * ptr" ], "return_type": { - "value": "int16x4x4_t" + "value": "int16x8x3_t" }, "Arguments_Preparation": { "ptr": { @@ -44292,18 +239137,18 @@ ], "instructions": [ [ - "LD4R" + "LD3R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_dup_s32", + "name": "vld3q_dup_s32", "arguments": [ "int32_t const * ptr" ], "return_type": { - "value": "int32x2x4_t" + "value": "int32x4x3_t" }, "Arguments_Preparation": { "ptr": { @@ -44317,18 +239162,18 @@ ], "instructions": [ [ - "LD4R" + "LD3R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_dup_s64", + "name": "vld3q_dup_s64", "arguments": [ "int64_t const * ptr" ], "return_type": { - "value": "int64x1x4_t" + "value": "int64x2x3_t" }, "Arguments_Preparation": { "ptr": { @@ -44336,24 +239181,22 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "LD4R" + "LD3R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_dup_s8", + "name": "vld3q_dup_s8", "arguments": [ "int8_t const * ptr" ], "return_type": { - "value": "int8x8x4_t" + "value": "int8x16x3_t" }, "Arguments_Preparation": { "ptr": { @@ -44367,18 +239210,18 @@ ], "instructions": [ [ - "LD4R" + "LD3R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_dup_u16", + "name": "vld3q_dup_u16", "arguments": [ "uint16_t const * ptr" ], "return_type": { - "value": "uint16x4x4_t" + "value": "uint16x8x3_t" }, "Arguments_Preparation": { "ptr": { @@ -44392,18 +239235,18 @@ ], "instructions": [ [ - "LD4R" + "LD3R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_dup_u32", + "name": "vld3q_dup_u32", "arguments": [ "uint32_t const * ptr" ], "return_type": { - "value": "uint32x2x4_t" + "value": "uint32x4x3_t" }, "Arguments_Preparation": { "ptr": { @@ -44417,18 +239260,18 @@ ], "instructions": [ [ - "LD4R" + "LD3R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_dup_u64", + "name": "vld3q_dup_u64", "arguments": [ "uint64_t const * ptr" ], "return_type": { - "value": "uint64x1x4_t" + "value": "uint64x2x3_t" }, "Arguments_Preparation": { "ptr": { @@ -44436,24 +239279,22 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "LD4R" + "LD3R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_dup_u8", + "name": "vld3q_dup_u8", "arguments": [ "uint8_t const * ptr" ], "return_type": { - "value": "uint8x8x4_t" + "value": "uint8x16x3_t" }, "Arguments_Preparation": { "ptr": { @@ -44467,18 +239308,18 @@ ], "instructions": [ [ - "LD4R" + "LD3R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_f16", + "name": "vld3q_f16", "arguments": [ "float16_t const * ptr" ], "return_type": { - "value": "float16x4x4_t" + "value": "float16x8x3_t" }, "Arguments_Preparation": { "ptr": { @@ -44492,18 +239333,18 @@ ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_f32", + "name": "vld3q_f32", "arguments": [ "float32_t const * ptr" ], "return_type": { - "value": "float32x2x4_t" + "value": "float32x4x3_t" }, "Arguments_Preparation": { "ptr": { @@ -44517,18 +239358,18 @@ ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_f64", + "name": "vld3q_f64", "arguments": [ "float64_t const * ptr" ], "return_type": { - "value": "float64x1x4_t" + "value": "float64x2x3_t" }, "Arguments_Preparation": { "ptr": { @@ -44540,31 +239381,37 @@ ], "instructions": [ [ - "LD1" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_lane_f16", + "name": "vld3q_lane_f16", "arguments": [ "float16_t const * ptr", - "float16x4x4_t src", + "float16x8x3_t src", "const int lane" ], "return_type": { - "value": "float16x4x4_t" + "value": "float16x8x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt4.4H" + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ @@ -44574,31 +239421,37 @@ ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_lane_f32", + "name": "vld3q_lane_f32", "arguments": [ "float32_t const * ptr", - "float32x2x4_t src", + "float32x4x3_t src", "const int lane" ], "return_type": { - "value": "float32x2x4_t" + "value": "float32x4x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt4.2S" + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { + "register": "Vt3.4S" } }, "Architectures": [ @@ -44608,31 +239461,37 @@ ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_lane_f64", + "name": "vld3q_lane_f64", "arguments": [ "float64_t const * ptr", - "float64x1x4_t src", + "float64x2x3_t src", "const int lane" ], "return_type": { - "value": "float64x1x4_t" + "value": "float64x2x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 0 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt4.1D" + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ @@ -44640,31 +239499,37 @@ ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_lane_p16", + "name": "vld3q_lane_p16", "arguments": [ "poly16_t const * ptr", - "poly16x4x4_t src", + "poly16x8x3_t src", "const int lane" ], "return_type": { - "value": "poly16x4x4_t" + "value": "poly16x8x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt4.4H" + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ @@ -44674,31 +239539,37 @@ ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_lane_p64", + "name": "vld3q_lane_p64", "arguments": [ "poly64_t const * ptr", - "poly64x1x4_t src", + "poly64x2x3_t src", "const int lane" ], "return_type": { - "value": "poly64x1x4_t" + "value": "poly64x2x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 0 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt4.1D" + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ @@ -44706,65 +239577,75 @@ ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_lane_p8", + "name": "vld3q_lane_p8", "arguments": [ "poly8_t const * ptr", - "poly8x8x4_t src", + "poly8x16x3_t src", "const int lane" ], "return_type": { - "value": "poly8x8x4_t" + "value": "poly8x16x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 15 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt4.8B" + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { + "register": "Vt3.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_lane_s16", + "name": "vld3q_lane_s16", "arguments": [ "int16_t const * ptr", - "int16x4x4_t src", + "int16x8x3_t src", "const int lane" ], "return_type": { - "value": "int16x4x4_t" + "value": "int16x8x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt4.4H" + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ @@ -44774,31 +239655,37 @@ ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_lane_s32", + "name": "vld3q_lane_s32", "arguments": [ "int32_t const * ptr", - "int32x2x4_t src", + "int32x4x3_t src", "const int lane" ], "return_type": { - "value": "int32x2x4_t" + "value": "int32x4x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt4.2S" + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { + "register": "Vt3.4S" } }, "Architectures": [ @@ -44808,31 +239695,37 @@ ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_lane_s64", + "name": "vld3q_lane_s64", "arguments": [ "int64_t const * ptr", - "int64x1x4_t src", + "int64x2x3_t src", "const int lane" ], "return_type": { - "value": "int64x1x4_t" + "value": "int64x2x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 0 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt4.1D" + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ @@ -44840,65 +239733,75 @@ ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_lane_s8", + "name": "vld3q_lane_s8", "arguments": [ "int8_t const * ptr", - "int8x8x4_t src", + "int8x16x3_t src", "const int lane" ], "return_type": { - "value": "int8x8x4_t" + "value": "int8x16x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 15 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt4.8B" + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { + "register": "Vt3.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_lane_u16", + "name": "vld3q_lane_u16", "arguments": [ "uint16_t const * ptr", - "uint16x4x4_t src", + "uint16x8x3_t src", "const int lane" ], "return_type": { - "value": "uint16x4x4_t" + "value": "uint16x8x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt4.4H" + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ @@ -44908,31 +239811,37 @@ ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_lane_u32", + "name": "vld3q_lane_u32", "arguments": [ "uint32_t const * ptr", - "uint32x2x4_t src", + "uint32x4x3_t src", "const int lane" ], "return_type": { - "value": "uint32x2x4_t" + "value": "uint32x4x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt4.2S" + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { + "register": "Vt3.4S" } }, "Architectures": [ @@ -44942,31 +239851,37 @@ ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_lane_u64", + "name": "vld3q_lane_u64", "arguments": [ "uint64_t const * ptr", - "uint64x1x4_t src", + "uint64x2x3_t src", "const int lane" ], "return_type": { - "value": "uint64x1x4_t" + "value": "uint64x2x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 0 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt4.1D" + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ @@ -44974,52 +239889,56 @@ ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_lane_u8", + "name": "vld3q_lane_u8", "arguments": [ "uint8_t const * ptr", - "uint8x8x4_t src", + "uint8x16x3_t src", "const int lane" ], "return_type": { - "value": "uint8x8x4_t" + "value": "uint8x16x3_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 15 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt4.8B" + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { + "register": "Vt3.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_p16", + "name": "vld3q_p16", "arguments": [ "poly16_t const * ptr" ], "return_type": { - "value": "poly16x4x4_t" + "value": "poly16x8x3_t" }, "Arguments_Preparation": { "ptr": { @@ -45033,18 +239952,18 @@ ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_p64", + "name": "vld3q_p64", "arguments": [ "poly64_t const * ptr" ], "return_type": { - "value": "poly64x1x4_t" + "value": "poly64x2x3_t" }, "Arguments_Preparation": { "ptr": { @@ -45052,23 +239971,22 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "LD1" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_p8", + "name": "vld3q_p8", "arguments": [ "poly8_t const * ptr" ], "return_type": { - "value": "poly8x8x4_t" + "value": "poly8x16x3_t" }, "Arguments_Preparation": { "ptr": { @@ -45082,18 +240000,18 @@ ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_s16", + "name": "vld3q_s16", "arguments": [ "int16_t const * ptr" ], "return_type": { - "value": "int16x4x4_t" + "value": "int16x8x3_t" }, "Arguments_Preparation": { "ptr": { @@ -45107,18 +240025,18 @@ ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_s32", + "name": "vld3q_s32", "arguments": [ "int32_t const * ptr" ], "return_type": { - "value": "int32x2x4_t" + "value": "int32x4x3_t" }, "Arguments_Preparation": { "ptr": { @@ -45132,18 +240050,18 @@ ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_s64", + "name": "vld3q_s64", "arguments": [ "int64_t const * ptr" ], "return_type": { - "value": "int64x1x4_t" + "value": "int64x2x3_t" }, "Arguments_Preparation": { "ptr": { @@ -45151,24 +240069,22 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "LD1" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_s8", + "name": "vld3q_s8", "arguments": [ "int8_t const * ptr" ], "return_type": { - "value": "int8x8x4_t" + "value": "int8x16x3_t" }, "Arguments_Preparation": { "ptr": { @@ -45182,18 +240098,18 @@ ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_u16", + "name": "vld3q_u16", "arguments": [ "uint16_t const * ptr" ], "return_type": { - "value": "uint16x4x4_t" + "value": "uint16x8x3_t" }, "Arguments_Preparation": { "ptr": { @@ -45207,18 +240123,18 @@ ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_u32", + "name": "vld3q_u32", "arguments": [ "uint32_t const * ptr" ], "return_type": { - "value": "uint32x2x4_t" + "value": "uint32x4x3_t" }, "Arguments_Preparation": { "ptr": { @@ -45232,18 +240148,18 @@ ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_u64", + "name": "vld3q_u64", "arguments": [ "uint64_t const * ptr" ], "return_type": { - "value": "uint64x1x4_t" + "value": "uint64x2x3_t" }, "Arguments_Preparation": { "ptr": { @@ -45251,24 +240167,22 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "LD1" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4_u8", + "name": "vld3q_u8", "arguments": [ "uint8_t const * ptr" ], "return_type": { - "value": "uint8x8x4_t" + "value": "uint8x16x3_t" }, "Arguments_Preparation": { "ptr": { @@ -45282,18 +240196,18 @@ ], "instructions": [ [ - "LD4" + "LD3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_dup_f16", + "name": "vld4_dup_f16", "arguments": [ "float16_t const * ptr" ], "return_type": { - "value": "float16x8x4_t" + "value": "float16x4x4_t" }, "Arguments_Preparation": { "ptr": { @@ -45313,12 +240227,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_dup_f32", + "name": "vld4_dup_f32", "arguments": [ "float32_t const * ptr" ], "return_type": { - "value": "float32x4x4_t" + "value": "float32x2x4_t" }, "Arguments_Preparation": { "ptr": { @@ -45338,12 +240252,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_dup_f64", + "name": "vld4_dup_f64", "arguments": [ "float64_t const * ptr" ], "return_type": { - "value": "float64x2x4_t" + "value": "float64x1x4_t" }, "Arguments_Preparation": { "ptr": { @@ -45361,12 +240275,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_dup_p16", + "name": "vld4_dup_p16", "arguments": [ "poly16_t const * ptr" ], "return_type": { - "value": "poly16x8x4_t" + "value": "poly16x4x4_t" }, "Arguments_Preparation": { "ptr": { @@ -45386,12 +240300,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_dup_p64", + "name": "vld4_dup_p64", "arguments": [ "poly64_t const * ptr" ], "return_type": { - "value": "poly64x2x4_t" + "value": "poly64x1x4_t" }, "Arguments_Preparation": { "ptr": { @@ -45399,6 +240313,7 @@ } }, "Architectures": [ + "A32", "A64" ], "instructions": [ @@ -45409,12 +240324,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_dup_p8", + "name": "vld4_dup_p8", "arguments": [ "poly8_t const * ptr" ], "return_type": { - "value": "poly8x16x4_t" + "value": "poly8x8x4_t" }, "Arguments_Preparation": { "ptr": { @@ -45434,12 +240349,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_dup_s16", + "name": "vld4_dup_s16", "arguments": [ "int16_t const * ptr" ], "return_type": { - "value": "int16x8x4_t" + "value": "int16x4x4_t" }, "Arguments_Preparation": { "ptr": { @@ -45459,12 +240374,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_dup_s32", + "name": "vld4_dup_s32", "arguments": [ "int32_t const * ptr" ], "return_type": { - "value": "int32x4x4_t" + "value": "int32x2x4_t" }, "Arguments_Preparation": { "ptr": { @@ -45484,12 +240399,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_dup_s64", + "name": "vld4_dup_s64", "arguments": [ "int64_t const * ptr" ], "return_type": { - "value": "int64x2x4_t" + "value": "int64x1x4_t" }, "Arguments_Preparation": { "ptr": { @@ -45497,6 +240412,8 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -45507,12 +240424,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_dup_s8", + "name": "vld4_dup_s8", "arguments": [ "int8_t const * ptr" ], "return_type": { - "value": "int8x16x4_t" + "value": "int8x8x4_t" }, "Arguments_Preparation": { "ptr": { @@ -45532,12 +240449,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_dup_u16", + "name": "vld4_dup_u16", "arguments": [ "uint16_t const * ptr" ], "return_type": { - "value": "uint16x8x4_t" + "value": "uint16x4x4_t" }, "Arguments_Preparation": { "ptr": { @@ -45557,12 +240474,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_dup_u32", + "name": "vld4_dup_u32", "arguments": [ "uint32_t const * ptr" ], "return_type": { - "value": "uint32x4x4_t" + "value": "uint32x2x4_t" }, "Arguments_Preparation": { "ptr": { @@ -45582,12 +240499,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_dup_u64", + "name": "vld4_dup_u64", "arguments": [ "uint64_t const * ptr" ], "return_type": { - "value": "uint64x2x4_t" + "value": "uint64x1x4_t" }, "Arguments_Preparation": { "ptr": { @@ -45595,6 +240512,8 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -45605,12 +240524,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_dup_u8", + "name": "vld4_dup_u8", "arguments": [ "uint8_t const * ptr" ], "return_type": { - "value": "uint8x16x4_t" + "value": "uint8x8x4_t" }, "Arguments_Preparation": { "ptr": { @@ -45630,12 +240549,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_f16", + "name": "vld4_f16", "arguments": [ "float16_t const * ptr" ], "return_type": { - "value": "float16x8x4_t" + "value": "float16x4x4_t" }, "Arguments_Preparation": { "ptr": { @@ -45655,12 +240574,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_f32", + "name": "vld4_f32", "arguments": [ "float32_t const * ptr" ], "return_type": { - "value": "float32x4x4_t" + "value": "float32x2x4_t" }, "Arguments_Preparation": { "ptr": { @@ -45680,12 +240599,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_f64", + "name": "vld4_f64", "arguments": [ "float64_t const * ptr" ], "return_type": { - "value": "float64x2x4_t" + "value": "float64x1x4_t" }, "Arguments_Preparation": { "ptr": { @@ -45697,31 +240616,40 @@ ], "instructions": [ [ - "LD4" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_lane_f16", + "name": "vld4_lane_f16", "arguments": [ "float16_t const * ptr", - "float16x8x4_t src", + "float16x4x4_t src", "const int lane" ], "return_type": { - "value": "float16x8x4_t" + "value": "float16x4x4_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt4.8H" + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { + "register": "Vt3.4H" + }, + "src.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ @@ -45737,25 +240665,34 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_lane_f32", + "name": "vld4_lane_f32", "arguments": [ "float32_t const * ptr", - "float32x4x4_t src", + "float32x2x4_t src", "const int lane" ], "return_type": { - "value": "float32x4x4_t" + "value": "float32x2x4_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt4.4S" + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { + "register": "Vt3.2S" + }, + "src.val[3]": { + "register": "Vt4.2S" } }, "Architectures": [ @@ -45771,25 +240708,34 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_lane_f64", + "name": "vld4_lane_f64", "arguments": [ "float64_t const * ptr", - "float64x2x4_t src", + "float64x1x4_t src", "const int lane" ], "return_type": { - "value": "float64x2x4_t" + "value": "float64x1x4_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt4.2D" + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { + "register": "Vt3.1D" + }, + "src.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ @@ -45803,25 +240749,34 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_lane_p16", + "name": "vld4_lane_p16", "arguments": [ "poly16_t const * ptr", - "poly16x8x4_t src", + "poly16x4x4_t src", "const int lane" ], "return_type": { - "value": "poly16x8x4_t" + "value": "poly16x4x4_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt4.8H" + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { + "register": "Vt3.4H" + }, + "src.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ @@ -45837,25 +240792,34 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_lane_p64", + "name": "vld4_lane_p64", "arguments": [ "poly64_t const * ptr", - "poly64x2x4_t src", + "poly64x1x4_t src", "const int lane" ], "return_type": { - "value": "poly64x2x4_t" + "value": "poly64x1x4_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt4.2D" + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { + "register": "Vt3.1D" + }, + "src.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ @@ -45869,28 +240833,39 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_lane_p8", + "name": "vld4_lane_p8", "arguments": [ "poly8_t const * ptr", - "poly8x16x4_t src", + "poly8x8x4_t src", "const int lane" ], "return_type": { - "value": "poly8x16x4_t" + "value": "poly8x8x4_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 15 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt4.16B" + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { + "register": "Vt3.8B" + }, + "src.val[3]": { + "register": "Vt4.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -45901,25 +240876,34 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_lane_s16", + "name": "vld4_lane_s16", "arguments": [ "int16_t const * ptr", - "int16x8x4_t src", + "int16x4x4_t src", "const int lane" ], "return_type": { - "value": "int16x8x4_t" + "value": "int16x4x4_t" }, "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "src": { - "register": "Vt4.8H" + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { + "register": "Vt3.4H" + }, + "src.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ @@ -45935,14 +240919,141 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_lane_s32", + "name": "vld4_lane_s32", "arguments": [ "int32_t const * ptr", - "int32x4x4_t src", + "int32x2x4_t src", "const int lane" ], "return_type": { - "value": "int32x4x4_t" + "value": "int32x2x4_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { + "register": "Vt3.2S" + }, + "src.val[3]": { + "register": "Vt4.2S" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD4" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vld4_lane_s64", + "arguments": [ + "int64_t const * ptr", + "int64x1x4_t src", + "const int lane" + ], + "return_type": { + "value": "int64x1x4_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { + "register": "Vt3.1D" + }, + "src.val[3]": { + "register": "Vt4.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vld4_lane_s8", + "arguments": [ + "int8_t const * ptr", + "int8x8x4_t src", + "const int lane" + ], + "return_type": { + "value": "int8x8x4_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { + "register": "Vt3.8B" + }, + "src.val[3]": { + "register": "Vt4.8B" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD4" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vld4_lane_u16", + "arguments": [ + "uint16_t const * ptr", + "uint16x4x4_t src", + "const int lane" + ], + "return_type": { + "value": "uint16x4x4_t" }, "Arguments_Preparation": { "lane": { @@ -45952,8 +241063,17 @@ "ptr": { "register": "Xn" }, - "src": { - "register": "Vt4.4S" + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { + "register": "Vt3.4H" + }, + "src.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ @@ -45969,28 +241089,247 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_lane_s64", + "name": "vld4_lane_u32", + "arguments": [ + "uint32_t const * ptr", + "uint32x2x4_t src", + "const int lane" + ], + "return_type": { + "value": "uint32x2x4_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { + "register": "Vt3.2S" + }, + "src.val[3]": { + "register": "Vt4.2S" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD4" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vld4_lane_u64", + "arguments": [ + "uint64_t const * ptr", + "uint64x1x4_t src", + "const int lane" + ], + "return_type": { + "value": "uint64x1x4_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { + "register": "Vt3.1D" + }, + "src.val[3]": { + "register": "Vt4.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vld4_lane_u8", + "arguments": [ + "uint8_t const * ptr", + "uint8x8x4_t src", + "const int lane" + ], + "return_type": { + "value": "uint8x8x4_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { + "register": "Vt3.8B" + }, + "src.val[3]": { + "register": "Vt4.8B" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD4" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vld4_p16", + "arguments": [ + "poly16_t const * ptr" + ], + "return_type": { + "value": "poly16x4x4_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD4" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vld4_p64", + "arguments": [ + "poly64_t const * ptr" + ], + "return_type": { + "value": "poly64x1x4_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "LD1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vld4_p8", + "arguments": [ + "poly8_t const * ptr" + ], + "return_type": { + "value": "poly8x8x4_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD4" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vld4_s16", + "arguments": [ + "int16_t const * ptr" + ], + "return_type": { + "value": "int16x4x4_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD4" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vld4_s32", "arguments": [ - "int64_t const * ptr", - "int64x2x4_t src", - "const int lane" + "int32_t const * ptr" ], "return_type": { - "value": "int64x2x4_t" + "value": "int32x2x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt4.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -46001,57 +241340,41 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_lane_s8", + "name": "vld4_s64", "arguments": [ - "int8_t const * ptr", - "int8x16x4_t src", - "const int lane" + "int64_t const * ptr" ], "return_type": { - "value": "int8x16x4_t" + "value": "int64x1x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt4.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LD4" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_lane_u16", + "name": "vld4_s8", "arguments": [ - "uint16_t const * ptr", - "uint16x8x4_t src", - "const int lane" + "int8_t const * ptr" ], "return_type": { - "value": "uint16x8x4_t" + "value": "int8x8x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt4.8H" } }, "Architectures": [ @@ -46067,25 +241390,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_lane_u32", + "name": "vld4_u16", "arguments": [ - "uint32_t const * ptr", - "uint32x4x4_t src", - "const int lane" + "uint16_t const * ptr" ], "return_type": { - "value": "uint32x4x4_t" + "value": "uint16x4x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt4.4S" } }, "Architectures": [ @@ -46101,28 +241415,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_lane_u64", + "name": "vld4_u32", "arguments": [ - "uint64_t const * ptr", - "uint64x2x4_t src", - "const int lane" + "uint32_t const * ptr" ], "return_type": { - "value": "uint64x2x4_t" + "value": "uint32x2x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt4.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -46133,44 +241440,37 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_lane_u8", + "name": "vld4_u64", "arguments": [ - "uint8_t const * ptr", - "uint8x16x4_t src", - "const int lane" + "uint64_t const * ptr" ], "return_type": { - "value": "uint8x16x4_t" + "value": "uint64x1x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt4.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LD4" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_p16", + "name": "vld4_u8", "arguments": [ - "poly16_t const * ptr" + "uint8_t const * ptr" ], "return_type": { - "value": "poly16x8x4_t" + "value": "uint8x8x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46190,12 +241490,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_p64", + "name": "vld4q_dup_f16", "arguments": [ - "poly64_t const * ptr" + "float16_t const * ptr" ], "return_type": { - "value": "poly64x2x4_t" + "value": "float16x8x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46203,22 +241503,24 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LD4" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_p8", + "name": "vld4q_dup_f32", "arguments": [ - "poly8_t const * ptr" + "float32_t const * ptr" ], "return_type": { - "value": "poly8x16x4_t" + "value": "float32x4x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46232,18 +241534,18 @@ ], "instructions": [ [ - "LD4" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_s16", + "name": "vld4q_dup_f64", "arguments": [ - "int16_t const * ptr" + "float64_t const * ptr" ], "return_type": { - "value": "int16x8x4_t" + "value": "float64x2x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46251,24 +241553,22 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "LD4" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_s32", + "name": "vld4q_dup_p16", "arguments": [ - "int32_t const * ptr" + "poly16_t const * ptr" ], "return_type": { - "value": "int32x4x4_t" + "value": "poly16x8x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46282,18 +241582,18 @@ ], "instructions": [ [ - "LD4" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_s64", + "name": "vld4q_dup_p64", "arguments": [ - "int64_t const * ptr" + "poly64_t const * ptr" ], "return_type": { - "value": "int64x2x4_t" + "value": "poly64x2x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46305,18 +241605,18 @@ ], "instructions": [ [ - "LD4" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_s8", + "name": "vld4q_dup_p8", "arguments": [ - "int8_t const * ptr" + "poly8_t const * ptr" ], "return_type": { - "value": "int8x16x4_t" + "value": "poly8x16x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46330,18 +241630,18 @@ ], "instructions": [ [ - "LD4" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_u16", + "name": "vld4q_dup_s16", "arguments": [ - "uint16_t const * ptr" + "int16_t const * ptr" ], "return_type": { - "value": "uint16x8x4_t" + "value": "int16x8x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46355,18 +241655,18 @@ ], "instructions": [ [ - "LD4" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_u32", + "name": "vld4q_dup_s32", "arguments": [ - "uint32_t const * ptr" + "int32_t const * ptr" ], "return_type": { - "value": "uint32x4x4_t" + "value": "int32x4x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46380,18 +241680,18 @@ ], "instructions": [ [ - "LD4" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_u64", + "name": "vld4q_dup_s64", "arguments": [ - "uint64_t const * ptr" + "int64_t const * ptr" ], "return_type": { - "value": "uint64x2x4_t" + "value": "int64x2x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46403,18 +241703,18 @@ ], "instructions": [ [ - "LD4" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_u8", + "name": "vld4q_dup_s8", "arguments": [ - "uint8_t const * ptr" + "int8_t const * ptr" ], "return_type": { - "value": "uint8x16x4_t" + "value": "int8x16x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46428,18 +241728,18 @@ ], "instructions": [ [ - "LD4" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vldrq_p128", + "name": "vld4q_dup_u16", "arguments": [ - "poly128_t const * ptr" + "uint16_t const * ptr" ], "return_type": { - "value": "poly128_t" + "value": "uint16x8x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46447,115 +241747,101 @@ } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "LDR" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmax_f16", + "name": "vld4q_dup_u32", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "uint32_t const * ptr" ], "return_type": { - "value": "float16x4_t" + "value": "uint32x4x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "ptr": { + "register": "Xn" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMAX" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmax_f32", + "name": "vld4q_dup_u64", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "uint64_t const * ptr" ], "return_type": { - "value": "float32x2_t" + "value": "uint64x2x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" + "ptr": { + "register": "Xn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FMAX" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmax_f64", + "name": "vld4q_dup_u8", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "uint8_t const * ptr" ], "return_type": { - "value": "float64x1_t" + "value": "uint8x16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" - }, - "b": { - "register": "Dm" + "ptr": { + "register": "Xn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAX" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmax_s16", + "name": "vld4q_f16", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "float16_t const * ptr" ], "return_type": { - "value": "int16x4_t" + "value": "float16x8x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "ptr": { + "register": "Xn" } }, "Architectures": [ @@ -46565,26 +241851,22 @@ ], "instructions": [ [ - "SMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmax_s32", + "name": "vld4q_f32", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "float32_t const * ptr" ], "return_type": { - "value": "int32x2_t" + "value": "float32x4x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" + "ptr": { + "register": "Xn" } }, "Architectures": [ @@ -46594,55 +241876,63 @@ ], "instructions": [ [ - "SMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmax_s8", + "name": "vld4q_f64", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "float64_t const * ptr" ], "return_type": { - "value": "int8x8_t" + "value": "float64x2x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" + "ptr": { + "register": "Xn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmax_u16", + "name": "vld4q_lane_f16", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "float16_t const * ptr", + "float16x8x4_t src", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "float16x8x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.4H" + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { + "register": "Vt3.8H" + }, + "src.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ @@ -46652,26 +241942,40 @@ ], "instructions": [ [ - "UMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmax_u32", + "name": "vld4q_lane_f32", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "float32_t const * ptr", + "float32x4x4_t src", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "float32x4x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.2S" + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { + "register": "Vt3.4S" + }, + "src.val[3]": { + "register": "Vt4.4S" } }, "Architectures": [ @@ -46681,295 +241985,460 @@ ], "instructions": [ [ - "UMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmax_u8", + "name": "vld4q_lane_f64", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "float64_t const * ptr", + "float64x2x4_t src", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "float64x2x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.8B" + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { + "register": "Vt3.2D" + }, + "src.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxh_f16", + "name": "vld4q_lane_p16", "arguments": [ - "float16_t a", - "float16_t b" + "poly16_t const * ptr", + "poly16x8x4_t src", + "const int lane" ], "return_type": { - "value": "float16_t" + "value": "poly16x8x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Hm" + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { + "register": "Vt3.8H" + }, + "src.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnm_f16", + "name": "vld4q_lane_p64", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "poly64_t const * ptr", + "poly64x2x4_t src", + "const int lane" ], "return_type": { - "value": "float16x4_t" + "value": "poly64x2x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.4H" + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { + "register": "Vt3.2D" + }, + "src.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMAXNM" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnm_f32", + "name": "vld4q_lane_p8", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "poly8_t const * ptr", + "poly8x16x4_t src", + "const int lane" ], "return_type": { - "value": "float32x2_t" + "value": "poly8x16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 15 }, - "b": { - "register": "Vm.2S" + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { + "register": "Vt3.16B" + }, + "src.val[3]": { + "register": "Vt4.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMAXNM" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnm_f64", + "name": "vld4q_lane_s16", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "int16_t const * ptr", + "int16x8x4_t src", + "const int lane" ], "return_type": { - "value": "float64x1_t" + "value": "int16x8x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Dm" + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { + "register": "Vt3.8H" + }, + "src.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAXNM" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnmh_f16", + "name": "vld4q_lane_s32", "arguments": [ - "float16_t a", - "float16_t b" + "int32_t const * ptr", + "int32x4x4_t src", + "const int lane" ], "return_type": { - "value": "float16_t" + "value": "int32x4x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Hm" + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { + "register": "Vt3.4S" + }, + "src.val[3]": { + "register": "Vt4.4S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMAXNM" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnmq_f16", + "name": "vld4q_lane_s64", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "int64_t const * ptr", + "int64x2x4_t src", + "const int lane" ], "return_type": { - "value": "float16x8_t" + "value": "int64x2x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.8H" + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { + "register": "Vt3.2D" + }, + "src.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMAXNM" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnmq_f32", + "name": "vld4q_lane_s8", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "int8_t const * ptr", + "int8x16x4_t src", + "const int lane" ], "return_type": { - "value": "float32x4_t" + "value": "int8x16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "lane": { + "minimum": 0, + "maximum": 15 }, - "b": { - "register": "Vm.4S" + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { + "register": "Vt3.16B" + }, + "src.val[3]": { + "register": "Vt4.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMAXNM" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnmq_f64", + "name": "vld4q_lane_u16", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "uint16_t const * ptr", + "uint16x8x4_t src", + "const int lane" ], "return_type": { - "value": "float64x2_t" + "value": "uint16x8x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.2D" + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { + "register": "Vt3.8H" + }, + "src.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAXNM" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnmv_f16", + "name": "vld4q_lane_u32", "arguments": [ - "float16x4_t a" + "uint32_t const * ptr", + "uint32x4x4_t src", + "const int lane" ], "return_type": { - "value": "float16_t" + "value": "uint32x4x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { + "register": "Vt3.4S" + }, + "src.val[3]": { + "register": "Vt4.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAXNMP" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnmv_f32", + "name": "vld4q_lane_u64", "arguments": [ - "float32x2_t a" + "uint64_t const * ptr", + "uint64x2x4_t src", + "const int lane" ], "return_type": { - "value": "float32_t" + "value": "uint64x2x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { + "register": "Vt3.2D" + }, + "src.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ @@ -46977,22 +242446,40 @@ ], "instructions": [ [ - "FMAXNMP" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnmvq_f16", + "name": "vld4q_lane_u8", "arguments": [ - "float16x8_t a" + "uint8_t const * ptr", + "uint8x16x4_t src", + "const int lane" ], "return_type": { - "value": "float16_t" + "value": "uint8x16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "lane": { + "minimum": 0, + "maximum": 15 + }, + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { + "register": "Vt3.16B" + }, + "src.val[3]": { + "register": "Vt4.16B" } }, "Architectures": [ @@ -47000,45 +242487,47 @@ ], "instructions": [ [ - "FMAXNMP" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnmvq_f32", + "name": "vld4q_p16", "arguments": [ - "float32x4_t a" + "poly16_t const * ptr" ], "return_type": { - "value": "float32_t" + "value": "poly16x8x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "ptr": { + "register": "Xn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAXNMV" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnmvq_f64", + "name": "vld4q_p64", "arguments": [ - "float64x2_t a" + "poly64_t const * ptr" ], "return_type": { - "value": "float64_t" + "value": "poly64x2x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "ptr": { + "register": "Xn" } }, "Architectures": [ @@ -47046,54 +242535,47 @@ ], "instructions": [ [ - "FMAXNMP" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxq_f16", + "name": "vld4q_p8", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "poly8_t const * ptr" ], "return_type": { - "value": "float16x8_t" + "value": "poly8x16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "ptr": { + "register": "Xn" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxq_f32", + "name": "vld4q_s16", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "int16_t const * ptr" ], "return_type": { - "value": "float32x4_t" + "value": "int16x8x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "ptr": { + "register": "Xn" } }, "Architectures": [ @@ -47103,82 +242585,70 @@ ], "instructions": [ [ - "FMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxq_f64", + "name": "vld4q_s32", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "int32_t const * ptr" ], "return_type": { - "value": "float64x2_t" + "value": "int32x4x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "ptr": { + "register": "Xn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxq_s16", + "name": "vld4q_s64", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int64_t const * ptr" ], "return_type": { - "value": "int16x8_t" + "value": "int64x2x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "ptr": { + "register": "Xn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxq_s32", + "name": "vld4q_s8", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int8_t const * ptr" ], "return_type": { - "value": "int32x4_t" + "value": "int8x16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "ptr": { + "register": "Xn" } }, "Architectures": [ @@ -47188,26 +242658,22 @@ ], "instructions": [ [ - "SMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxq_s8", + "name": "vld4q_u16", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "uint16_t const * ptr" ], "return_type": { - "value": "int8x16_t" + "value": "uint16x8x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "ptr": { + "register": "Xn" } }, "Architectures": [ @@ -47217,26 +242683,22 @@ ], "instructions": [ [ - "SMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxq_u16", + "name": "vld4q_u32", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "uint32_t const * ptr" ], "return_type": { - "value": "uint16x8_t" + "value": "uint32x4x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "ptr": { + "register": "Xn" } }, "Architectures": [ @@ -47246,55 +242708,45 @@ ], "instructions": [ [ - "UMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxq_u32", + "name": "vld4q_u64", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "uint64_t const * ptr" ], "return_type": { - "value": "uint32x4_t" + "value": "uint64x2x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "ptr": { + "register": "Xn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxq_u8", + "name": "vld4q_u8", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "uint8_t const * ptr" ], "return_type": { - "value": "uint8x16_t" + "value": "uint8x16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "ptr": { + "register": "Xn" } }, "Architectures": [ @@ -47304,22 +242756,31 @@ ], "instructions": [ [ - "UMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxv_f16", + "name": "vldap1_lane_f64", "arguments": [ - "float16x4_t a" + "float64_t const * ptr", + "float64x1_t src", + "const int lane" ], "return_type": { - "value": "float16_t" + "value": "float64x1_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.1D" } }, "Architectures": [ @@ -47327,22 +242788,31 @@ ], "instructions": [ [ - "FMAXP" + "LDAP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxv_f32", + "name": "vldap1_lane_p64", "arguments": [ - "float32x2_t a" + "poly64_t const * ptr", + "poly64x1_t src", + "const int lane" ], "return_type": { - "value": "float32_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.1D" } }, "Architectures": [ @@ -47350,22 +242820,31 @@ ], "instructions": [ [ - "FMAXP" + "LDAP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxv_s16", + "name": "vldap1_lane_s64", "arguments": [ - "int16x4_t a" + "int64_t const * ptr", + "int64x1_t src", + "const int lane" ], "return_type": { - "value": "int16_t" + "value": "int64x1_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.1D" } }, "Architectures": [ @@ -47373,22 +242852,31 @@ ], "instructions": [ [ - "SMAXV" + "LDAP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxv_s32", + "name": "vldap1_lane_u64", "arguments": [ - "int32x2_t a" + "uint64_t const * ptr", + "uint64x1_t src", + "const int lane" ], "return_type": { - "value": "int32_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.1D" } }, "Architectures": [ @@ -47396,22 +242884,31 @@ ], "instructions": [ [ - "SMAXP" + "LDAP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxv_s8", + "name": "vldap1q_lane_f64", "arguments": [ - "int8x8_t a" + "float64_t const * ptr", + "float64x2_t src", + "const int lane" ], "return_type": { - "value": "int8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" } }, "Architectures": [ @@ -47419,22 +242916,31 @@ ], "instructions": [ [ - "SMAXV" + "LDAP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxv_u16", + "name": "vldap1q_lane_p64", "arguments": [ - "uint16x4_t a" + "poly64_t const * ptr", + "poly64x2_t src", + "const int lane" ], "return_type": { - "value": "uint16_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" } }, "Architectures": [ @@ -47442,22 +242948,31 @@ ], "instructions": [ [ - "UMAXV" + "LDAP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxv_u32", + "name": "vldap1q_lane_s64", "arguments": [ - "uint32x2_t a" + "int64_t const * ptr", + "int64x2_t src", + "const int lane" ], "return_type": { - "value": "uint32_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" } }, "Architectures": [ @@ -47465,22 +242980,31 @@ ], "instructions": [ [ - "UMAXP" + "LDAP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxv_u8", + "name": "vldap1q_lane_u64", "arguments": [ - "uint8x8_t a" + "uint64_t const * ptr", + "uint64x2_t src", + "const int lane" ], "return_type": { - "value": "uint8_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" } }, "Architectures": [ @@ -47488,45 +243012,55 @@ ], "instructions": [ [ - "UMAXV" + "LDAP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxvq_f16", + "name": "vldrq_p128", "arguments": [ - "float16x8_t a" + "poly128_t const * ptr" ], "return_type": { - "value": "float16_t" + "value": "poly128_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "ptr": { + "register": "Xn" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FMAXP" + "LDR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxvq_f32", + "name": "vluti2_lane_f16", "arguments": [ - "float32x4_t a" + "float16x4_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "float32_t" + "value": "float16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ @@ -47534,22 +243068,31 @@ ], "instructions": [ [ - "FMAXV" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxvq_f64", + "name": "vluti2_lane_p16", "arguments": [ - "float64x2_t a" + "poly16x4_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "float64_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ @@ -47557,22 +243100,31 @@ ], "instructions": [ [ - "FMAXP" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxvq_s16", + "name": "vluti2_lane_p8", "arguments": [ - "int16x8_t a" + "poly8x8_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "int16_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ @@ -47580,22 +243132,31 @@ ], "instructions": [ [ - "SMAXV" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxvq_s32", + "name": "vluti2_lane_s16", "arguments": [ - "int32x4_t a" + "int16x4_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "int32_t" + "value": "int16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ @@ -47603,21 +243164,30 @@ ], "instructions": [ [ - "SMAXV" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxvq_s8", + "name": "vluti2_lane_s8", "arguments": [ - "int8x16_t a" + "int8x8_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "int8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn": { "register": "Vn.16B" } }, @@ -47626,21 +243196,30 @@ ], "instructions": [ [ - "SMAXV" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxvq_u16", + "name": "vluti2_lane_u16", "arguments": [ - "uint16x8_t a" + "uint16x4_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "uint16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "a": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { "register": "Vn.8H" } }, @@ -47649,22 +243228,31 @@ ], "instructions": [ [ - "UMAXV" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxvq_u32", + "name": "vluti2_lane_u8", "arguments": [ - "uint32x4_t a" + "uint8x8_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "uint32_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ @@ -47672,22 +243260,31 @@ ], "instructions": [ [ - "UMAXV" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxvq_u8", + "name": "vluti2_laneq_f16", "arguments": [ - "uint8x16_t a" + "float16x4_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "uint8_t" + "value": "float16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "index": { + "minimum": 0, + "maximum": 7 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ @@ -47695,83 +243292,95 @@ ], "instructions": [ [ - "UMAXV" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmin_f16", + "name": "vluti2_laneq_p16", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "poly16x4_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float16x4_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "index": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.4H" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMIN" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmin_f32", + "name": "vluti2_laneq_p8", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "poly8x8_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float32x2_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.2S" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FMIN" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmin_f64", + "name": "vluti2_laneq_s16", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "int16x4_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float64x1_t" + "value": "int16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "index": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Dm" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ @@ -47779,200 +243388,223 @@ ], "instructions": [ [ - "FMIN" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmin_s16", + "name": "vluti2_laneq_s8", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "int8x8_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "int16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.4H" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMIN" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmin_s32", + "name": "vluti2_laneq_u16", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "uint16x4_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "int32x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "index": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.2S" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMIN" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmin_s8", + "name": "vluti2_laneq_u8", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "uint8x8_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "int8x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.8B" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMIN" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmin_u16", + "name": "vluti2q_lane_f16", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "float16x8_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "uint16x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.4H" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMIN" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmin_u32", + "name": "vluti2q_lane_p16", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "poly16x8_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "uint32x2_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.2S" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMIN" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmin_u8", + "name": "vluti2q_lane_p8", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "poly8x16_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "uint8x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "index": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.8B" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMIN" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminh_f16", + "name": "vluti2q_lane_s16", "arguments": [ - "float16_t a", - "float16_t b" + "int16x8_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "float16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Hm" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ @@ -47980,82 +243612,95 @@ ], "instructions": [ [ - "FMIN" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnm_f16", + "name": "vluti2q_lane_s8", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "int8x16_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "float16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "index": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.4H" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMINNM" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnm_f32", + "name": "vluti2q_lane_u16", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "uint16x8_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "float32x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.2S" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMINNM" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnm_f64", + "name": "vluti2q_lane_u8", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "uint8x16_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "float64x1_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "index": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Dm" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ @@ -48063,110 +243708,127 @@ ], "instructions": [ [ - "FMINNM" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnmh_f16", + "name": "vluti2q_laneq_f16", "arguments": [ - "float16_t a", - "float16_t b" + "float16x8_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "index": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Hm" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMINNM" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnmq_f16", + "name": "vluti2q_laneq_p16", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "poly16x8_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float16x8_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "index": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.8H" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMINNM" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnmq_f32", + "name": "vluti2q_laneq_p8", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "poly8x16_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float32x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.4S" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMINNM" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnmq_f64", + "name": "vluti2q_laneq_s16", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "int16x8_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "index": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.2D" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ @@ -48174,22 +243836,31 @@ ], "instructions": [ [ - "FMINNM" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnmv_f16", + "name": "vluti2q_laneq_s8", "arguments": [ - "float16x4_t a" + "int8x16_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float16_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ @@ -48197,22 +243868,31 @@ ], "instructions": [ [ - "FMINNMP" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnmv_f32", + "name": "vluti2q_laneq_u16", "arguments": [ - "float32x2_t a" + "uint16x8_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float32_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "index": { + "minimum": 0, + "maximum": 7 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ @@ -48220,22 +243900,31 @@ ], "instructions": [ [ - "FMINNMP" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnmvq_f16", + "name": "vluti2q_laneq_u8", "arguments": [ - "float16x8_t a" + "uint8x16_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float16_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ @@ -48243,22 +243932,34 @@ ], "instructions": [ [ - "FMINNMP" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnmvq_f32", + "name": "vluti4q_lane_f16_x2", "arguments": [ - "float32x4_t a" + "float16x8x2_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "float32_t" + "value": "float16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" } }, "Architectures": [ @@ -48266,22 +243967,34 @@ ], "instructions": [ [ - "FMINNMV" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnmvq_f64", + "name": "vluti4q_lane_p16_x2", "arguments": [ - "float64x2_t a" + "poly16x8x2_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "float64_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" } }, "Architectures": [ @@ -48289,83 +244002,98 @@ ], "instructions": [ [ - "FMINNMP" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminq_f16", + "name": "vluti4q_lane_p8", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "poly8x16_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "float16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "index": { + "minimum": 0, + "maximum": 0 }, - "b": { - "register": "Vm.8H" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMIN" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminq_f32", + "name": "vluti4q_lane_s16_x2", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "int16x8x2_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "float32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "index": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.4S" + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FMIN" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminq_f64", + "name": "vluti4q_lane_s8", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "int8x16_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "float64x2_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "index": { + "minimum": 0, + "maximum": 0 }, - "b": { - "register": "Vm.2D" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ @@ -48373,196 +244101,235 @@ ], "instructions": [ [ - "FMIN" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminq_s16", + "name": "vluti4q_lane_u16_x2", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "uint16x8x2_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "int16x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "index": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.8H" + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMIN" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminq_s32", + "name": "vluti4q_lane_u8", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "uint8x16_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "int32x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "index": { + "minimum": 0, + "maximum": 0 }, - "b": { - "register": "Vm.4S" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMIN" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminq_s8", + "name": "vluti4q_laneq_f16_x2", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "float16x8x2_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "int8x16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.16B" + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMIN" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminq_u16", + "name": "vluti4q_laneq_p16_x2", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "poly16x8x2_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "uint16x8_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.8H" + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMIN" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminq_u32", + "name": "vluti4q_laneq_p8", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "poly8x16_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "uint32x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "index": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.4S" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMIN" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminq_u8", + "name": "vluti4q_laneq_s16_x2", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "int16x8x2_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "uint8x16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.16B" + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMIN" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminv_f16", + "name": "vluti4q_laneq_s8", "arguments": [ - "float16x4_t a" + "int8x16_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float16_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ @@ -48570,22 +244337,34 @@ ], "instructions": [ [ - "FMINP" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminv_f32", + "name": "vluti4q_laneq_u16_x2", "arguments": [ - "float32x2_t a" + "uint16x8x2_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float32_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" } }, "Architectures": [ @@ -48593,22 +244372,31 @@ ], "instructions": [ [ - "FMINP" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminv_s16", + "name": "vluti4q_laneq_u8", "arguments": [ - "int16x4_t a" + "uint8x16_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "int16_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ @@ -48616,68 +244404,83 @@ ], "instructions": [ [ - "SMINV" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminv_s32", + "name": "vmax_f16", "arguments": [ - "int32x2_t a" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "int32_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "SMINP" + "FMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminv_s8", + "name": "vmax_f32", "arguments": [ - "int8x8_t a" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "int8_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMINV" + "FMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminv_u16", + "name": "vmax_f64", "arguments": [ - "uint16x4_t a" + "float64x1_t a", + "float64x1_t b" ], "return_type": { - "value": "uint16_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Dn" + }, + "b": { + "register": "Dm" } }, "Architectures": [ @@ -48685,160 +244488,200 @@ ], "instructions": [ [ - "UMINV" + "FMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminv_u32", + "name": "vmax_s16", "arguments": [ - "uint32x2_t a" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "uint32_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMINP" + "SMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminv_u8", + "name": "vmax_s32", "arguments": [ - "uint8x8_t a" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "uint8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMINV" + "SMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminvq_f16", + "name": "vmax_s8", "arguments": [ - "float16x8_t a" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "float16_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINP" + "SMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminvq_f32", + "name": "vmax_u16", "arguments": [ - "float32x4_t a" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "float32_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINV" + "UMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminvq_f64", + "name": "vmax_u32", "arguments": [ - "float64x2_t a" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "float64_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINP" + "UMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminvq_s16", + "name": "vmax_u8", "arguments": [ - "int16x8_t a" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "int16_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMINV" + "UMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminvq_s32", + "name": "vmaxh_f16", "arguments": [ - "int32x4_t a" + "float16_t a", + "float16_t b" ], "return_type": { - "value": "int32_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Hn" + }, + "b": { + "register": "Hm" } }, "Architectures": [ @@ -48846,68 +244689,82 @@ ], "instructions": [ [ - "SMINV" + "FMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminvq_s8", + "name": "vmaxnm_f16", "arguments": [ - "int8x16_t a" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "int8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "SMINV" + "FMAXNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminvq_u16", + "name": "vmaxnm_f32", "arguments": [ - "uint16x8_t a" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "uint16_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "UMINV" + "FMAXNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminvq_u32", + "name": "vmaxnm_f64", "arguments": [ - "uint32x4_t a" + "float64x1_t a", + "float64x1_t b" ], "return_type": { - "value": "uint32_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Dn" + }, + "b": { + "register": "Dm" } }, "Architectures": [ @@ -48915,408 +244772,309 @@ ], "instructions": [ [ - "UMINV" + "FMAXNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminvq_u8", + "name": "vmaxnmh_f16", "arguments": [ - "uint8x16_t a" + "float16_t a", + "float16_t b" ], "return_type": { - "value": "uint8_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Hn" + }, + "b": { + "register": "Hm" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "UMINV" + "FMAXNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_f32", + "name": "vmaxnmq_f16", "arguments": [ - "float32x2_t a", - "float32x2_t b", - "float32x2_t c" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "float32x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "N/A" + "register": "Vn.8H" }, "b": { - "register": "N/A" - }, - "c": { - "register": "N/A" + "register": "Vm.8H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "RESULT[I]" + "FMAXNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_f64", + "name": "vmaxnmq_f32", "arguments": [ - "float64x1_t a", - "float64x1_t b", - "float64x1_t c" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "float64x1_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "N/A" + "register": "Vn.4S" }, "b": { - "register": "N/A" - }, - "c": { - "register": "N/A" + "register": "Vm.4S" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "RESULT[I]" + "FMAXNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_lane_f32", + "name": "vmaxnmq_f64", "arguments": [ - "float32x2_t a", - "float32x2_t b", - "float32x2_t v", - "const int lane" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "float32x2_t" + "value": "float64x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 1 + "a": { + "register": "Vn.2D" }, - "v": {} + "b": { + "register": "Vm.2D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "RESULT[I]" + "FMAXNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_lane_s16", + "name": "vmaxnmv_f16", "arguments": [ - "int16x4_t a", - "int16x4_t b", - "int16x4_t v", - "const int lane" + "float16x4_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "FMAXNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_lane_s32", + "name": "vmaxnmv_f32", "arguments": [ - "int32x2_t a", - "int32x2_t b", - "int32x2_t v", - "const int lane" + "float32x2_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "FMAXNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_lane_u16", + "name": "vmaxnmvq_f16", "arguments": [ - "uint16x4_t a", - "uint16x4_t b", - "uint16x4_t v", - "const int lane" + "float16x8_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "register": "Vn.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "FMAXNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_lane_u32", + "name": "vmaxnmvq_f32", "arguments": [ - "uint32x2_t a", - "uint32x2_t b", - "uint32x2_t v", - "const int lane" + "float32x4_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Vn.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "FMAXNMV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_laneq_f32", + "name": "vmaxnmvq_f64", "arguments": [ - "float32x2_t a", - "float32x2_t b", - "float32x4_t v", - "const int lane" + "float64x2_t a" ], "return_type": { - "value": "float32x2_t" + "value": "float64_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": {} + "a": { + "register": "Vn.2D" + } }, "Architectures": [ "A64" ], "instructions": [ [ - "RESULT[I]" + "FMAXNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_laneq_s16", + "name": "vmaxq_f16", "arguments": [ - "int16x4_t a", - "int16x4_t b", - "int16x8_t v", - "const int lane" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "int16x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.8H" }, "b": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { "register": "Vm.8H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "MLA" + "FMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_laneq_s32", + "name": "vmaxq_f32", "arguments": [ - "int32x2_t a", - "int32x2_t b", - "int32x4_t v", - "const int lane" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "int32x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.4S" }, "b": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "MLA" + "FMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_laneq_u16", + "name": "vmaxq_f64", "arguments": [ - "uint16x4_t a", - "uint16x4_t b", - "uint16x8_t v", - "const int lane" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.2D" }, "b": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vm.2D" } }, "Architectures": [ @@ -49324,66 +245082,55 @@ ], "instructions": [ [ - "MLA" + "FMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_laneq_u32", + "name": "vmaxq_s16", "arguments": [ - "uint32x2_t a", - "uint32x2_t b", - "uint32x4_t v", - "const int lane" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.8H" }, "b": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "MLA" + "SMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_n_f32", + "name": "vmaxq_s32", "arguments": [ - "float32x2_t a", - "float32x2_t b", - "float32_t c" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "float32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "N/A" + "register": "Vn.4S" }, "b": { - "register": "N/A" - }, - "c": { - "register": "N/A" + "register": "Vm.4S" } }, "Architectures": [ @@ -49393,30 +245140,26 @@ ], "instructions": [ [ - "RESULT[I]" + "SMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_n_s16", + "name": "vmaxq_s8", "arguments": [ - "int16x4_t a", - "int16x4_t b", - "int16_t c" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "int16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.16B" }, "b": { - "register": "Vn.4H" - }, - "c": { - "register": "Vm.H[0]" + "register": "Vm.16B" } }, "Architectures": [ @@ -49426,30 +245169,26 @@ ], "instructions": [ [ - "MLA" + "SMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_n_s32", + "name": "vmaxq_u16", "arguments": [ - "int32x2_t a", - "int32x2_t b", - "int32_t c" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int32x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.8H" }, "b": { - "register": "Vn.2S" - }, - "c": { - "register": "Vm.S[0]" + "register": "Vm.8H" } }, "Architectures": [ @@ -49459,30 +245198,26 @@ ], "instructions": [ [ - "MLA" + "UMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_n_u16", + "name": "vmaxq_u32", "arguments": [ - "uint16x4_t a", - "uint16x4_t b", - "uint16_t c" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.4S" }, "b": { - "register": "Vn.4H" - }, - "c": { - "register": "Vm.H[0]" + "register": "Vm.4S" } }, "Architectures": [ @@ -49492,30 +245227,26 @@ ], "instructions": [ [ - "MLA" + "UMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_n_u32", + "name": "vmaxq_u8", "arguments": [ - "uint32x2_t a", - "uint32x2_t b", - "uint32_t c" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.16B" }, "b": { - "register": "Vn.2S" - }, - "c": { - "register": "Vm.S[0]" + "register": "Vm.16B" } }, "Architectures": [ @@ -49525,233 +245256,160 @@ ], "instructions": [ [ - "MLA" + "UMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_s16", + "name": "vmaxv_f16", "arguments": [ - "int16x4_t a", - "int16x4_t b", - "int16x4_t c" + "float16x4_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { "register": "Vn.4H" - }, - "c": { - "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "FMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_s32", + "name": "vmaxv_f32", "arguments": [ - "int32x2_t a", - "int32x2_t b", - "int32x2_t c" + "float32x2_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { "register": "Vn.2S" - }, - "c": { - "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "FMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_s8", + "name": "vmaxv_s16", "arguments": [ - "int8x8_t a", - "int8x8_t b", - "int8x8_t c" + "int16x4_t a" ], "return_type": { - "value": "int8x8_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "b": { - "register": "Vn.8B" - }, - "c": { - "register": "Vm.8B" + "register": "Vn.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "SMAXV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_u16", + "name": "vmaxv_s32", "arguments": [ - "uint16x4_t a", - "uint16x4_t b", - "uint16x4_t c" + "int32x2_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" - }, - "c": { - "register": "Vm.4H" + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "SMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_u32", + "name": "vmaxv_s8", "arguments": [ - "uint32x2_t a", - "uint32x2_t b", - "uint32x2_t c" + "int8x8_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "int8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.2S" - }, - "c": { - "register": "Vm.2S" + "register": "Vn.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "SMAXV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_u8", + "name": "vmaxv_u16", "arguments": [ - "uint8x8_t a", - "uint8x8_t b", - "uint8x8_t c" + "uint16x4_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "b": { - "register": "Vn.8B" - }, - "c": { - "register": "Vm.8B" + "register": "Vn.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "UMAXV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_lane_s16", + "name": "vmaxv_u32", "arguments": [ - "int32x4_t a", - "int16x8_t b", - "int16x4_t v", - "const int lane" + "uint32x2_t a" ], "return_type": { - "value": "int32x4_t" + "value": "uint32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "register": "Vm.2S" } }, "Architectures": [ @@ -49759,35 +245417,22 @@ ], "instructions": [ [ - "SMLAL2" + "UMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_lane_s32", + "name": "vmaxv_u8", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32x2_t v", - "const int lane" + "uint8x8_t a" ], "return_type": { - "value": "int64x2_t" + "value": "uint8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Vn.8B" } }, "Architectures": [ @@ -49795,35 +245440,22 @@ ], "instructions": [ [ - "SMLAL2" + "UMAXV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_lane_u16", + "name": "vmaxvq_f16", "arguments": [ - "uint32x4_t a", - "uint16x8_t b", - "uint16x4_t v", - "const int lane" + "float16x8_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" } }, "Architectures": [ @@ -49831,35 +245463,22 @@ ], "instructions": [ [ - "UMLAL2" + "FMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_lane_u32", + "name": "vmaxvq_f32", "arguments": [ - "uint64x2_t a", - "uint32x4_t b", - "uint32x2_t v", - "const int lane" + "float32x4_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" } }, "Architectures": [ @@ -49867,35 +245486,22 @@ ], "instructions": [ [ - "UMLAL2" + "FMAXV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_laneq_s16", + "name": "vmaxvq_f64", "arguments": [ - "int32x4_t a", - "int16x8_t b", - "int16x8_t v", - "const int lane" + "float64x2_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vn.2D" } }, "Architectures": [ @@ -49903,35 +245509,22 @@ ], "instructions": [ [ - "SMLAL2" + "FMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_laneq_s32", + "name": "vmaxvq_s16", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32x4_t v", - "const int lane" + "int16x8_t a" ], "return_type": { - "value": "int64x2_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vn.8H" } }, "Architectures": [ @@ -49939,35 +245532,22 @@ ], "instructions": [ [ - "SMLAL2" + "SMAXV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_laneq_u16", + "name": "vmaxvq_s32", "arguments": [ - "uint32x4_t a", - "uint16x8_t b", - "uint16x8_t v", - "const int lane" + "int32x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vn.4S" } }, "Architectures": [ @@ -49975,35 +245555,22 @@ ], "instructions": [ [ - "UMLAL2" + "SMAXV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_laneq_u32", + "name": "vmaxvq_s8", "arguments": [ - "uint64x2_t a", - "uint32x4_t b", - "uint32x4_t v", - "const int lane" + "int8x16_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vn.16B" } }, "Architectures": [ @@ -50011,30 +245578,22 @@ ], "instructions": [ [ - "UMLAL2" + "SMAXV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_n_s16", + "name": "vmaxvq_u16", "arguments": [ - "int32x4_t a", - "int16x8_t b", - "int16_t c" + "uint16x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.8H" - }, - "c": { - "register": "Vm.H[0]" } }, "Architectures": [ @@ -50042,30 +245601,22 @@ ], "instructions": [ [ - "SMLAL2" + "UMAXV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_n_s32", + "name": "vmaxvq_u32", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32_t c" + "uint32x4_t a" ], "return_type": { - "value": "int64x2_t" + "value": "uint32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { "register": "Vn.4S" - }, - "c": { - "register": "Vm.S[0]" } }, "Architectures": [ @@ -50073,30 +245624,22 @@ ], "instructions": [ [ - "SMLAL2" + "UMAXV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_n_u16", + "name": "vmaxvq_u8", "arguments": [ - "uint32x4_t a", - "uint16x8_t b", - "uint16_t c" + "uint8x16_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "uint8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.8H" - }, - "c": { - "register": "Vm.H[0]" + "register": "Vn.16B" } }, "Architectures": [ @@ -50104,92 +245647,83 @@ ], "instructions": [ [ - "UMLAL2" + "UMAXV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_n_u32", + "name": "vmin_f16", "arguments": [ - "uint64x2_t a", - "uint32x4_t b", - "uint32_t c" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.4H" }, "b": { - "register": "Vn.4S" - }, - "c": { - "register": "Vm.S[0]" + "register": "Vm.4H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "UMLAL2" + "FMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_s16", + "name": "vmin_f32", "arguments": [ - "int32x4_t a", - "int16x8_t b", - "int16x8_t c" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "int32x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.2S" }, "b": { - "register": "Vn.8H" - }, - "c": { - "register": "Vm.8H" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMLAL2" + "FMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_s32", + "name": "vmin_f64", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32x4_t c" + "float64x1_t a", + "float64x1_t b" ], "return_type": { - "value": "int64x2_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Dn" }, "b": { - "register": "Vn.4S" - }, - "c": { - "register": "Vm.4S" + "register": "Dm" } }, "Architectures": [ @@ -50197,159 +245731,142 @@ ], "instructions": [ [ - "SMLAL2" + "FMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_s8", + "name": "vmin_s16", "arguments": [ - "int16x8_t a", - "int8x16_t b", - "int8x16_t c" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vn.4H" }, "b": { - "register": "Vn.16B" - }, - "c": { - "register": "Vm.16B" + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMLAL2" + "SMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_u16", + "name": "vmin_s32", "arguments": [ - "uint32x4_t a", - "uint16x8_t b", - "uint16x8_t c" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.2S" }, "b": { - "register": "Vn.8H" - }, - "c": { - "register": "Vm.8H" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMLAL2" + "SMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_u32", + "name": "vmin_s8", "arguments": [ - "uint64x2_t a", - "uint32x4_t b", - "uint32x4_t c" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.8B" }, "b": { - "register": "Vn.4S" - }, - "c": { - "register": "Vm.4S" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMLAL2" + "SMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_u8", + "name": "vmin_u16", "arguments": [ - "uint16x8_t a", - "uint8x16_t b", - "uint8x16_t c" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vn.4H" }, "b": { - "register": "Vn.16B" - }, - "c": { - "register": "Vm.16B" + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMLAL2" + "UMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_lane_s16", + "name": "vmin_u32", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16x4_t v", - "const int lane" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "a": { + "register": "Vn.2S" }, - "v": { - "register": "Vm.4H" + "b": { + "register": "Vm.2S" } }, "Architectures": [ @@ -50359,35 +245876,26 @@ ], "instructions": [ [ - "SMLAL" + "UMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_lane_s32", + "name": "vmin_u8", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32x2_t v", - "const int lane" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.8B" }, "b": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Vm.8B" } }, "Architectures": [ @@ -50397,147 +245905,109 @@ ], "instructions": [ [ - "SMLAL" + "UMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_lane_u16", + "name": "vminh_f16", "arguments": [ - "uint32x4_t a", - "uint16x4_t b", - "uint16x4_t v", - "const int lane" + "float16_t a", + "float16_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Hn" }, "b": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "register": "Hm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMLAL" + "FMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_lane_u32", + "name": "vminnm_f16", "arguments": [ - "uint64x2_t a", - "uint32x2_t b", - "uint32x2_t v", - "const int lane" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.4H" }, "b": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Vm.4H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "UMLAL" + "FMINNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_laneq_s16", + "name": "vminnm_f32", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16x8_t v", - "const int lane" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "int32x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.2S" }, "b": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vm.2S" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "SMLAL" + "FMINNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_laneq_s32", + "name": "vminnm_f64", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32x4_t v", - "const int lane" + "float64x1_t a", + "float64x1_t b" ], "return_type": { - "value": "int64x2_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Dn" }, "b": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Dm" } }, "Architectures": [ @@ -50545,366 +246015,280 @@ ], "instructions": [ [ - "SMLAL" + "FMINNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_laneq_u16", + "name": "vminnmh_f16", "arguments": [ - "uint32x4_t a", - "uint16x4_t b", - "uint16x8_t v", - "const int lane" + "float16_t a", + "float16_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Hn" }, "b": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Hm" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "UMLAL" + "FMINNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_laneq_u32", + "name": "vminnmq_f16", "arguments": [ - "uint64x2_t a", - "uint32x2_t b", - "uint32x4_t v", - "const int lane" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.8H" }, "b": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vm.8H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "UMLAL" + "FMINNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_n_s16", + "name": "vminnmq_f32", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16_t c" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.4S" }, "b": { - "register": "Vn.4H" - }, - "c": { - "register": "Vm.H[0]" + "register": "Vm.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SMLAL" + "FMINNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_n_s32", + "name": "vminnmq_f64", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32_t c" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "int64x2_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.2D" }, "b": { - "register": "Vn.2S" - }, - "c": { - "register": "Vm.S[0]" + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMLAL" + "FMINNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_n_u16", + "name": "vminnmv_f16", "arguments": [ - "uint32x4_t a", - "uint16x4_t b", - "uint16_t c" + "float16x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.4H" - }, - "c": { - "register": "Vm.H[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMLAL" + "FMINNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_n_u32", + "name": "vminnmv_f32", "arguments": [ - "uint64x2_t a", - "uint32x2_t b", - "uint32_t c" + "float32x2_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { "register": "Vn.2S" - }, - "c": { - "register": "Vm.S[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMLAL" + "FMINNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_s16", + "name": "vminnmvq_f16", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16x4_t c" + "float16x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4H" - }, - "c": { - "register": "Vm.4H" + "register": "Vn.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMLAL" + "FMINNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_s32", + "name": "vminnmvq_f32", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32x2_t c" + "float32x4_t a" ], "return_type": { - "value": "int64x2_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.2S" - }, - "c": { - "register": "Vm.2S" + "register": "Vn.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMLAL" + "FMINNMV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_s8", + "name": "vminnmvq_f64", "arguments": [ - "int16x8_t a", - "int8x8_t b", - "int8x8_t c" + "float64x2_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.8B" - }, - "c": { - "register": "Vm.8B" + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMLAL" + "FMINNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_u16", + "name": "vminq_f16", "arguments": [ - "uint32x4_t a", - "uint16x4_t b", - "uint16x4_t c" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.8H" }, "b": { - "register": "Vn.4H" - }, - "c": { - "register": "Vm.4H" + "register": "Vm.8H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "UMLAL" + "FMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_u32", + "name": "vminq_f32", "arguments": [ - "uint64x2_t a", - "uint32x2_t b", - "uint32x2_t c" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.4S" }, "b": { - "register": "Vn.2S" - }, - "c": { - "register": "Vm.2S" + "register": "Vm.4S" } }, "Architectures": [ @@ -50914,63 +246298,53 @@ ], "instructions": [ [ - "UMLAL" + "FMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_u8", + "name": "vminq_f64", "arguments": [ - "uint16x8_t a", - "uint8x8_t b", - "uint8x8_t c" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vn.2D" }, "b": { - "register": "Vn.8B" - }, - "c": { - "register": "Vm.8B" + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMLAL" + "FMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_f32", + "name": "vminq_s16", "arguments": [ - "float32x4_t a", - "float32x4_t b", - "float32x4_t c" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "float32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "N/A" + "register": "Vn.8H" }, "b": { - "register": "N/A" - }, - "c": { - "register": "N/A" + "register": "Vm.8H" } }, "Architectures": [ @@ -50980,61 +246354,56 @@ ], "instructions": [ [ - "RESULT[I]" + "SMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_f64", + "name": "vminq_s32", "arguments": [ - "float64x2_t a", - "float64x2_t b", - "float64x2_t c" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "float64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "N/A" + "register": "Vn.4S" }, "b": { - "register": "N/A" - }, - "c": { - "register": "N/A" + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "RESULT[I]" + "SMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_lane_f32", + "name": "vminq_s8", "arguments": [ - "float32x4_t a", - "float32x4_t b", - "float32x2_t v", - "const int lane" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "float32x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 1 + "a": { + "register": "Vn.16B" }, - "v": {} + "b": { + "register": "Vm.16B" + } }, "Architectures": [ "v7", @@ -51043,35 +246412,26 @@ ], "instructions": [ [ - "RESULT[I]" + "SMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_lane_s16", + "name": "vminq_u16", "arguments": [ - "int16x8_t a", - "int16x8_t b", - "int16x4_t v", - "const int lane" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int16x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { "register": "Vn.8H" }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "b": { + "register": "Vm.8H" } }, "Architectures": [ @@ -51081,35 +246441,26 @@ ], "instructions": [ [ - "MLA" + "UMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_lane_s32", + "name": "vminq_u32", "arguments": [ - "int32x4_t a", - "int32x4_t b", - "int32x2_t v", - "const int lane" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.4S" }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "b": { + "register": "Vm.4S" } }, "Architectures": [ @@ -51119,35 +246470,26 @@ ], "instructions": [ [ - "MLA" + "UMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_lane_u16", + "name": "vminq_u8", "arguments": [ - "uint16x8_t a", - "uint16x8_t b", - "uint16x4_t v", - "const int lane" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vn.16B" }, "b": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "register": "Vm.16B" } }, "Architectures": [ @@ -51157,103 +246499,68 @@ ], "instructions": [ [ - "MLA" + "UMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_lane_u32", + "name": "vminv_f16", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x2_t v", - "const int lane" + "float16x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Vn.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "FMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_laneq_f32", + "name": "vminv_f32", "arguments": [ - "float32x4_t a", - "float32x4_t b", - "float32x4_t v", - "const int lane" + "float32x2_t a" ], "return_type": { - "value": "float32x4_t" + "value": "float32_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": {} + "a": { + "register": "Vn.2S" + } }, "Architectures": [ "A64" ], "instructions": [ [ - "RESULT[I]" + "FMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_laneq_s16", + "name": "vminv_s16", "arguments": [ - "int16x8_t a", - "int16x8_t b", - "int16x8_t v", - "const int lane" + "int16x4_t a" ], "return_type": { - "value": "int16x8_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vn.4H" } }, "Architectures": [ @@ -51261,35 +246568,22 @@ ], "instructions": [ [ - "MLA" + "SMINV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_laneq_s32", + "name": "vminv_s32", "arguments": [ - "int32x4_t a", - "int32x4_t b", - "int32x4_t v", - "const int lane" + "int32x2_t a" ], "return_type": { - "value": "int32x4_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vm.2S" } }, "Architectures": [ @@ -51297,35 +246591,22 @@ ], "instructions": [ [ - "MLA" + "SMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_laneq_u16", + "name": "vminv_s8", "arguments": [ - "uint16x8_t a", - "uint16x8_t b", - "uint16x8_t v", - "const int lane" + "int8x8_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "int8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vn.8B" } }, "Architectures": [ @@ -51333,35 +246614,22 @@ ], "instructions": [ [ - "MLA" + "SMINV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_laneq_u32", + "name": "vminv_u16", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t v", - "const int lane" + "uint16x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vn.4H" } }, "Architectures": [ @@ -51369,376 +246637,266 @@ ], "instructions": [ [ - "MLA" + "UMINV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_n_f32", + "name": "vminv_u32", "arguments": [ - "float32x4_t a", - "float32x4_t b", - "float32_t c" + "uint32x2_t a" ], "return_type": { - "value": "float32x4_t" + "value": "uint32_t" }, "Arguments_Preparation": { "a": { - "register": "N/A" - }, - "b": { - "register": "N/A" - }, - "c": { - "register": "N/A" + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "RESULT[I]" + "UMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_n_s16", + "name": "vminv_u8", "arguments": [ - "int16x8_t a", - "int16x8_t b", - "int16_t c" + "uint8x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "uint8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.8H" - }, - "c": { - "register": "Vm.H[0]" + "register": "Vn.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "UMINV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_n_s32", + "name": "vminvq_f16", "arguments": [ - "int32x4_t a", - "int32x4_t b", - "int32_t c" + "float16x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4S" - }, - "c": { - "register": "Vm.S[0]" + "register": "Vn.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "FMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_n_u16", + "name": "vminvq_f32", "arguments": [ - "uint16x8_t a", - "uint16x8_t b", - "uint16_t c" + "float32x4_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.8H" - }, - "c": { - "register": "Vm.H[0]" + "register": "Vn.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "FMINV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_n_u32", + "name": "vminvq_f64", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32_t c" + "float64x2_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4S" - }, - "c": { - "register": "Vm.S[0]" + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "FMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_s16", + "name": "vminvq_s16", "arguments": [ - "int16x8_t a", - "int16x8_t b", - "int16x8_t c" + "int16x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { "register": "Vn.8H" - }, - "c": { - "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "SMINV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_s32", + "name": "vminvq_s32", "arguments": [ - "int32x4_t a", - "int32x4_t b", - "int32x4_t c" + "int32x4_t a" ], "return_type": { - "value": "int32x4_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.4S" - }, - "c": { - "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "SMINV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_s8", + "name": "vminvq_s8", "arguments": [ - "int8x16_t a", - "int8x16_t b", - "int8x16_t c" + "int8x16_t a" ], "return_type": { - "value": "int8x16_t" + "value": "int8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "b": { "register": "Vn.16B" - }, - "c": { - "register": "Vm.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "SMINV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_u16", + "name": "vminvq_u16", "arguments": [ - "uint16x8_t a", - "uint16x8_t b", - "uint16x8_t c" + "uint16x8_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { "register": "Vn.8H" - }, - "c": { - "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "UMINV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_u32", + "name": "vminvq_u32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t c" + "uint32x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "uint32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.4S" - }, - "c": { - "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "UMINV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_u8", + "name": "vminvq_u8", "arguments": [ - "uint8x16_t a", - "uint8x16_t b", - "uint8x16_t c" + "uint8x16_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "uint8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "b": { "register": "Vn.16B" - }, - "c": { - "register": "Vm.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "UMINV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_f32", + "name": "vmla_f32", "arguments": [ "float32x2_t a", "float32x2_t b", @@ -51765,13 +246923,13 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_f64", + "name": "vmla_f64", "arguments": [ "float64x1_t a", "float64x1_t b", @@ -51796,13 +246954,13 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_lane_f32", + "name": "vmla_lane_f32", "arguments": [ "float32x2_t a", "float32x2_t b", @@ -51813,13 +246971,10 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 1 - }, - "v": {} + } }, "Architectures": [ "v7", @@ -51828,13 +246983,13 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_lane_s16", + "name": "vmla_lane_s16", "arguments": [ "int16x4_t a", "int16x4_t b", @@ -51866,13 +247021,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_lane_s32", + "name": "vmla_lane_s32", "arguments": [ "int32x2_t a", "int32x2_t b", @@ -51904,13 +247059,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_lane_u16", + "name": "vmla_lane_u16", "arguments": [ "uint16x4_t a", "uint16x4_t b", @@ -51942,13 +247097,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_lane_u32", + "name": "vmla_lane_u32", "arguments": [ "uint32x2_t a", "uint32x2_t b", @@ -51980,13 +247135,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_laneq_f32", + "name": "vmla_laneq_f32", "arguments": [ "float32x2_t a", "float32x2_t b", @@ -51997,26 +247152,23 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 3 - }, - "v": {} + } }, "Architectures": [ "A64" ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_laneq_s16", + "name": "vmla_laneq_s16", "arguments": [ "int16x4_t a", "int16x4_t b", @@ -52046,13 +247198,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_laneq_s32", + "name": "vmla_laneq_s32", "arguments": [ "int32x2_t a", "int32x2_t b", @@ -52082,13 +247234,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_laneq_u16", + "name": "vmla_laneq_u16", "arguments": [ "uint16x4_t a", "uint16x4_t b", @@ -52118,13 +247270,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_laneq_u32", + "name": "vmla_laneq_u32", "arguments": [ "uint32x2_t a", "uint32x2_t b", @@ -52154,13 +247306,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_n_f32", + "name": "vmla_n_f32", "arguments": [ "float32x2_t a", "float32x2_t b", @@ -52187,13 +247339,13 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_n_s16", + "name": "vmla_n_s16", "arguments": [ "int16x4_t a", "int16x4_t b", @@ -52220,13 +247372,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_n_s32", + "name": "vmla_n_s32", "arguments": [ "int32x2_t a", "int32x2_t b", @@ -52253,13 +247405,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_n_u16", + "name": "vmla_n_u16", "arguments": [ "uint16x4_t a", "uint16x4_t b", @@ -52286,13 +247438,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_n_u32", + "name": "vmla_n_u32", "arguments": [ "uint32x2_t a", "uint32x2_t b", @@ -52319,13 +247471,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_s16", + "name": "vmla_s16", "arguments": [ "int16x4_t a", "int16x4_t b", @@ -52352,13 +247504,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_s32", + "name": "vmla_s32", "arguments": [ "int32x2_t a", "int32x2_t b", @@ -52385,13 +247537,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_s8", + "name": "vmla_s8", "arguments": [ "int8x8_t a", "int8x8_t b", @@ -52418,13 +247570,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_u16", + "name": "vmla_u16", "arguments": [ "uint16x4_t a", "uint16x4_t b", @@ -52451,13 +247603,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_u32", + "name": "vmla_u32", "arguments": [ "uint32x2_t a", "uint32x2_t b", @@ -52484,13 +247636,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_u8", + "name": "vmla_u8", "arguments": [ "uint8x8_t a", "uint8x8_t b", @@ -52517,13 +247669,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_lane_s16", + "name": "vmlal_high_lane_s16", "arguments": [ "int32x4_t a", "int16x8_t b", @@ -52553,13 +247705,13 @@ ], "instructions": [ [ - "SMLSL2" + "SMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_lane_s32", + "name": "vmlal_high_lane_s32", "arguments": [ "int64x2_t a", "int32x4_t b", @@ -52589,13 +247741,13 @@ ], "instructions": [ [ - "SMLSL2" + "SMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_lane_u16", + "name": "vmlal_high_lane_u16", "arguments": [ "uint32x4_t a", "uint16x8_t b", @@ -52625,13 +247777,13 @@ ], "instructions": [ [ - "UMLSL2" + "UMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_lane_u32", + "name": "vmlal_high_lane_u32", "arguments": [ "uint64x2_t a", "uint32x4_t b", @@ -52661,13 +247813,13 @@ ], "instructions": [ [ - "UMLSL2" + "UMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_laneq_s16", + "name": "vmlal_high_laneq_s16", "arguments": [ "int32x4_t a", "int16x8_t b", @@ -52697,13 +247849,13 @@ ], "instructions": [ [ - "SMLSL2" + "SMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_laneq_s32", + "name": "vmlal_high_laneq_s32", "arguments": [ "int64x2_t a", "int32x4_t b", @@ -52733,13 +247885,13 @@ ], "instructions": [ [ - "SMLSL2" + "SMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_laneq_u16", + "name": "vmlal_high_laneq_u16", "arguments": [ "uint32x4_t a", "uint16x8_t b", @@ -52769,13 +247921,13 @@ ], "instructions": [ [ - "UMLSL2" + "UMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_laneq_u32", + "name": "vmlal_high_laneq_u32", "arguments": [ "uint64x2_t a", "uint32x4_t b", @@ -52805,13 +247957,13 @@ ], "instructions": [ [ - "UMLSL2" + "UMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_n_s16", + "name": "vmlal_high_n_s16", "arguments": [ "int32x4_t a", "int16x8_t b", @@ -52836,13 +247988,13 @@ ], "instructions": [ [ - "SMLSL2" + "SMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_n_s32", + "name": "vmlal_high_n_s32", "arguments": [ "int64x2_t a", "int32x4_t b", @@ -52867,13 +248019,13 @@ ], "instructions": [ [ - "SMLSL2" + "SMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_n_u16", + "name": "vmlal_high_n_u16", "arguments": [ "uint32x4_t a", "uint16x8_t b", @@ -52898,13 +248050,13 @@ ], "instructions": [ [ - "UMLSL2" + "UMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_n_u32", + "name": "vmlal_high_n_u32", "arguments": [ "uint64x2_t a", "uint32x4_t b", @@ -52929,13 +248081,13 @@ ], "instructions": [ [ - "UMLSL2" + "UMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_s16", + "name": "vmlal_high_s16", "arguments": [ "int32x4_t a", "int16x8_t b", @@ -52960,13 +248112,13 @@ ], "instructions": [ [ - "SMLSL2" + "SMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_s32", + "name": "vmlal_high_s32", "arguments": [ "int64x2_t a", "int32x4_t b", @@ -52991,13 +248143,13 @@ ], "instructions": [ [ - "SMLSL2" + "SMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_s8", + "name": "vmlal_high_s8", "arguments": [ "int16x8_t a", "int8x16_t b", @@ -53022,13 +248174,13 @@ ], "instructions": [ [ - "SMLSL2" + "SMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_u16", + "name": "vmlal_high_u16", "arguments": [ "uint32x4_t a", "uint16x8_t b", @@ -53053,13 +248205,13 @@ ], "instructions": [ [ - "UMLSL2" + "UMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_u32", + "name": "vmlal_high_u32", "arguments": [ "uint64x2_t a", "uint32x4_t b", @@ -53084,13 +248236,13 @@ ], "instructions": [ [ - "UMLSL2" + "UMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_u8", + "name": "vmlal_high_u8", "arguments": [ "uint16x8_t a", "uint8x16_t b", @@ -53115,13 +248267,13 @@ ], "instructions": [ [ - "UMLSL2" + "UMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_lane_s16", + "name": "vmlal_lane_s16", "arguments": [ "int32x4_t a", "int16x4_t b", @@ -53153,13 +248305,13 @@ ], "instructions": [ [ - "SMLSL" + "SMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_lane_s32", + "name": "vmlal_lane_s32", "arguments": [ "int64x2_t a", "int32x2_t b", @@ -53191,13 +248343,13 @@ ], "instructions": [ [ - "SMLSL" + "SMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_lane_u16", + "name": "vmlal_lane_u16", "arguments": [ "uint32x4_t a", "uint16x4_t b", @@ -53229,13 +248381,13 @@ ], "instructions": [ [ - "UMLSL" + "UMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_lane_u32", + "name": "vmlal_lane_u32", "arguments": [ "uint64x2_t a", "uint32x2_t b", @@ -53267,13 +248419,13 @@ ], "instructions": [ [ - "UMLSL" + "UMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_laneq_s16", + "name": "vmlal_laneq_s16", "arguments": [ "int32x4_t a", "int16x4_t b", @@ -53303,13 +248455,13 @@ ], "instructions": [ [ - "SMLSL" + "SMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_laneq_s32", + "name": "vmlal_laneq_s32", "arguments": [ "int64x2_t a", "int32x2_t b", @@ -53339,13 +248491,13 @@ ], "instructions": [ [ - "SMLSL" + "SMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_laneq_u16", + "name": "vmlal_laneq_u16", "arguments": [ "uint32x4_t a", "uint16x4_t b", @@ -53375,13 +248527,13 @@ ], "instructions": [ [ - "UMLSL" + "UMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_laneq_u32", + "name": "vmlal_laneq_u32", "arguments": [ "uint64x2_t a", "uint32x2_t b", @@ -53411,13 +248563,13 @@ ], "instructions": [ [ - "UMLSL" + "UMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_n_s16", + "name": "vmlal_n_s16", "arguments": [ "int32x4_t a", "int16x4_t b", @@ -53444,13 +248596,13 @@ ], "instructions": [ [ - "SMLSL" + "SMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_n_s32", + "name": "vmlal_n_s32", "arguments": [ "int64x2_t a", "int32x2_t b", @@ -53477,13 +248629,13 @@ ], "instructions": [ [ - "SMLSL" + "SMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_n_u16", + "name": "vmlal_n_u16", "arguments": [ "uint32x4_t a", "uint16x4_t b", @@ -53510,13 +248662,13 @@ ], "instructions": [ [ - "UMLSL" + "UMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_n_u32", + "name": "vmlal_n_u32", "arguments": [ "uint64x2_t a", "uint32x2_t b", @@ -53543,13 +248695,13 @@ ], "instructions": [ [ - "UMLSL" + "UMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_s16", + "name": "vmlal_s16", "arguments": [ "int32x4_t a", "int16x4_t b", @@ -53576,13 +248728,13 @@ ], "instructions": [ [ - "SMLSL" + "SMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_s32", + "name": "vmlal_s32", "arguments": [ "int64x2_t a", "int32x2_t b", @@ -53609,13 +248761,13 @@ ], "instructions": [ [ - "SMLSL" + "SMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_s8", + "name": "vmlal_s8", "arguments": [ "int16x8_t a", "int8x8_t b", @@ -53642,13 +248794,13 @@ ], "instructions": [ [ - "SMLSL" + "SMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_u16", + "name": "vmlal_u16", "arguments": [ "uint32x4_t a", "uint16x4_t b", @@ -53675,13 +248827,13 @@ ], "instructions": [ [ - "UMLSL" + "UMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_u32", + "name": "vmlal_u32", "arguments": [ "uint64x2_t a", "uint32x2_t b", @@ -53708,13 +248860,13 @@ ], "instructions": [ [ - "UMLSL" + "UMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_u8", + "name": "vmlal_u8", "arguments": [ "uint16x8_t a", "uint8x8_t b", @@ -53741,13 +248893,13 @@ ], "instructions": [ [ - "UMLSL" + "UMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_f32", + "name": "vmlaq_f32", "arguments": [ "float32x4_t a", "float32x4_t b", @@ -53774,13 +248926,13 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_f64", + "name": "vmlaq_f64", "arguments": [ "float64x2_t a", "float64x2_t b", @@ -53805,13 +248957,13 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_lane_f32", + "name": "vmlaq_lane_f32", "arguments": [ "float32x4_t a", "float32x4_t b", @@ -53822,13 +248974,10 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 1 - }, - "v": {} + } }, "Architectures": [ "v7", @@ -53837,13 +248986,13 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_lane_s16", + "name": "vmlaq_lane_s16", "arguments": [ "int16x8_t a", "int16x8_t b", @@ -53875,13 +249024,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_lane_s32", + "name": "vmlaq_lane_s32", "arguments": [ "int32x4_t a", "int32x4_t b", @@ -53913,13 +249062,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_lane_u16", + "name": "vmlaq_lane_u16", "arguments": [ "uint16x8_t a", "uint16x8_t b", @@ -53951,13 +249100,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_lane_u32", + "name": "vmlaq_lane_u32", "arguments": [ "uint32x4_t a", "uint32x4_t b", @@ -53989,13 +249138,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_laneq_f32", + "name": "vmlaq_laneq_f32", "arguments": [ "float32x4_t a", "float32x4_t b", @@ -54006,26 +249155,23 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 3 - }, - "v": {} + } }, "Architectures": [ "A64" ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_laneq_s16", + "name": "vmlaq_laneq_s16", "arguments": [ "int16x8_t a", "int16x8_t b", @@ -54055,13 +249201,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_laneq_s32", + "name": "vmlaq_laneq_s32", "arguments": [ "int32x4_t a", "int32x4_t b", @@ -54091,13 +249237,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_laneq_u16", + "name": "vmlaq_laneq_u16", "arguments": [ "uint16x8_t a", "uint16x8_t b", @@ -54127,13 +249273,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_laneq_u32", + "name": "vmlaq_laneq_u32", "arguments": [ "uint32x4_t a", "uint32x4_t b", @@ -54163,13 +249309,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_n_f32", + "name": "vmlaq_n_f32", "arguments": [ "float32x4_t a", "float32x4_t b", @@ -54196,13 +249342,13 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_n_s16", + "name": "vmlaq_n_s16", "arguments": [ "int16x8_t a", "int16x8_t b", @@ -54229,13 +249375,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_n_s32", + "name": "vmlaq_n_s32", "arguments": [ "int32x4_t a", "int32x4_t b", @@ -54262,13 +249408,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_n_u16", + "name": "vmlaq_n_u16", "arguments": [ "uint16x8_t a", "uint16x8_t b", @@ -54295,13 +249441,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_n_u32", + "name": "vmlaq_n_u32", "arguments": [ "uint32x4_t a", "uint32x4_t b", @@ -54328,13 +249474,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_s16", + "name": "vmlaq_s16", "arguments": [ "int16x8_t a", "int16x8_t b", @@ -54361,13 +249507,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_s32", + "name": "vmlaq_s32", "arguments": [ "int32x4_t a", "int32x4_t b", @@ -54394,13 +249540,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_s8", + "name": "vmlaq_s8", "arguments": [ "int8x16_t a", "int8x16_t b", @@ -54427,13 +249573,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_u16", + "name": "vmlaq_u16", "arguments": [ "uint16x8_t a", "uint16x8_t b", @@ -54460,13 +249606,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_u32", + "name": "vmlaq_u32", "arguments": [ "uint32x4_t a", "uint32x4_t b", @@ -54493,13 +249639,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_u8", + "name": "vmlaq_u8", "arguments": [ "uint8x16_t a", "uint8x16_t b", @@ -54526,384 +249672,90 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmmlaq_s32", + "name": "vmls_f32", "arguments": [ - "int32x4_t r", - "int8x16_t a", - "int8x16_t b" + "float32x2_t a", + "float32x2_t b", + "float32x2_t c" ], "return_type": { - "value": "int32x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "N/A" }, "b": { - "register": "Vm.16B" + "register": "N/A" }, - "r": { - "register": "Vd.4S" + "c": { + "register": "N/A" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "SMMLA" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmmlaq_u32", + "name": "vmls_f64", "arguments": [ - "uint32x4_t r", - "uint8x16_t a", - "uint8x16_t b" + "float64x1_t a", + "float64x1_t b", + "float64x1_t c" ], "return_type": { - "value": "uint32x4_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "N/A" }, "b": { - "register": "Vm.16B" + "register": "N/A" }, - "r": { - "register": "Vd.4S" + "c": { + "register": "N/A" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "UMMLA" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmov_n_f16", - "arguments": [ - "float16_t value" - ], - "return_type": { - "value": "float16x4_t" - }, - "Arguments_Preparation": { - "value": { - "register": "rn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "DUP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmov_n_f32", + "name": "vmls_lane_f32", "arguments": [ - "float32_t value" + "float32x2_t a", + "float32x2_t b", + "float32x2_t v", + "const int lane" ], "return_type": { "value": "float32x2_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "DUP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmov_n_f64", - "arguments": [ - "float64_t value" - ], - "return_type": { - "value": "float64x1_t" - }, - "Arguments_Preparation": { - "value": { - "register": "rn" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "DUP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmov_n_p16", - "arguments": [ - "poly16_t value" - ], - "return_type": { - "value": "poly16x4_t" - }, - "Arguments_Preparation": { - "value": { - "register": "rn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "DUP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmov_n_p8", - "arguments": [ - "poly8_t value" - ], - "return_type": { - "value": "poly8x8_t" - }, - "Arguments_Preparation": { - "value": { - "register": "rn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "DUP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmov_n_s16", - "arguments": [ - "int16_t value" - ], - "return_type": { - "value": "int16x4_t" - }, - "Arguments_Preparation": { - "value": { - "register": "rn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "DUP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmov_n_s32", - "arguments": [ - "int32_t value" - ], - "return_type": { - "value": "int32x2_t" - }, - "Arguments_Preparation": { - "value": { - "register": "rn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "DUP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmov_n_s64", - "arguments": [ - "int64_t value" - ], - "return_type": { - "value": "int64x1_t" - }, - "Arguments_Preparation": { - "value": { - "register": "rn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "DUP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmov_n_s8", - "arguments": [ - "int8_t value" - ], - "return_type": { - "value": "int8x8_t" - }, - "Arguments_Preparation": { - "value": { - "register": "rn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "DUP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmov_n_u16", - "arguments": [ - "uint16_t value" - ], - "return_type": { - "value": "uint16x4_t" - }, - "Arguments_Preparation": { - "value": { - "register": "rn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "DUP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmov_n_u32", - "arguments": [ - "uint32_t value" - ], - "return_type": { - "value": "uint32x2_t" - }, - "Arguments_Preparation": { - "value": { - "register": "rn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "DUP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmov_n_u64", - "arguments": [ - "uint64_t value" - ], - "return_type": { - "value": "uint64x1_t" - }, - "Arguments_Preparation": { - "value": { - "register": "rn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "DUP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmov_n_u8", - "arguments": [ - "uint8_t value" - ], - "return_type": { - "value": "uint8x8_t" - }, - "Arguments_Preparation": { - "value": { - "register": "rn" + "lane": { + "minimum": 0, + "maximum": 1 } }, "Architectures": [ @@ -54913,160 +249765,73 @@ ], "instructions": [ [ - "DUP" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovl_high_s16", - "arguments": [ - "int16x8_t a" - ], - "return_type": { - "value": "int32x4_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "SSHLL2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmovl_high_s32", - "arguments": [ - "int32x4_t a" - ], - "return_type": { - "value": "int64x2_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "SSHLL2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmovl_high_s8", - "arguments": [ - "int8x16_t a" - ], - "return_type": { - "value": "int16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "SSHLL2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmovl_high_u16", - "arguments": [ - "uint16x8_t a" - ], - "return_type": { - "value": "uint32x4_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "USHLL2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmovl_high_u32", - "arguments": [ - "uint32x4_t a" - ], - "return_type": { - "value": "uint64x2_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "USHLL2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmovl_high_u8", + "name": "vmls_lane_s16", "arguments": [ - "uint8x16_t a" + "int16x4_t a", + "int16x4_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vd.4H" + }, + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USHLL2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovl_s16", + "name": "vmls_lane_s32", "arguments": [ - "int16x4_t a" + "int32x2_t a", + "int32x2_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.2S" + }, + "b": { + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -55076,22 +249841,35 @@ ], "instructions": [ [ - "SSHLL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovl_s32", + "name": "vmls_lane_u16", "arguments": [ - "int32x2_t a" + "uint16x4_t a", + "uint16x4_t b", + "uint16x4_t v", + "const int lane" ], "return_type": { - "value": "int64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.4H" + }, + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -55101,22 +249879,35 @@ ], "instructions": [ [ - "SSHLL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovl_s8", + "name": "vmls_lane_u32", "arguments": [ - "int8x8_t a" + "uint32x2_t a", + "uint32x2_t b", + "uint32x2_t v", + "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vd.2S" + }, + "b": { + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -55126,159 +249917,201 @@ ], "instructions": [ [ - "SSHLL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovl_u16", + "name": "vmls_laneq_f32", "arguments": [ - "uint16x4_t a" + "float32x2_t a", + "float32x2_t b", + "float32x4_t v", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 3 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USHLL" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovl_u32", + "name": "vmls_laneq_s16", "arguments": [ - "uint32x2_t a" + "int16x4_t a", + "int16x4_t b", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.4H" + }, + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USHLL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovl_u8", + "name": "vmls_laneq_s32", "arguments": [ - "uint8x8_t a" + "int32x2_t a", + "int32x2_t b", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vd.2S" + }, + "b": { + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USHLL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_high_s16", + "name": "vmls_laneq_u16", "arguments": [ - "int8x8_t r", - "int16x8_t a" + "uint16x4_t a", + "uint16x4_t b", + "uint16x8_t v", + "const int lane" ], "return_type": { - "value": "int8x16_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.4H" }, - "r": { - "register": "Vd.8B" + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "XTN2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_high_s32", + "name": "vmls_laneq_u32", "arguments": [ - "int16x4_t r", - "int32x4_t a" + "uint32x2_t a", + "uint32x2_t b", + "uint32x4_t v", + "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.2S" }, - "r": { - "register": "Vd.4H" + "b": { + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "XTN2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_high_s64", + "name": "vmls_n_f32", "arguments": [ - "int32x2_t r", - "int64x2_t a" + "float32x2_t a", + "float32x2_t b", + "float32_t c" ], "return_type": { - "value": "int32x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "N/A" }, - "r": { - "register": "Vd.2S" + "b": { + "register": "N/A" + }, + "c": { + "register": "N/A" } }, "Architectures": [ @@ -55288,26 +250121,30 @@ ], "instructions": [ [ - "XTN2" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_high_u16", + "name": "vmls_n_s16", "arguments": [ - "uint8x8_t r", - "uint16x8_t a" + "int16x4_t a", + "int16x4_t b", + "int16_t c" ], "return_type": { - "value": "uint8x16_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.4H" }, - "r": { - "register": "Vd.8B" + "b": { + "register": "Vn.4H" + }, + "c": { + "register": "Vm.H[0]" } }, "Architectures": [ @@ -55317,26 +250154,30 @@ ], "instructions": [ [ - "XTN2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_high_u32", + "name": "vmls_n_s32", "arguments": [ - "uint16x4_t r", - "uint32x4_t a" + "int32x2_t a", + "int32x2_t b", + "int32_t c" ], "return_type": { - "value": "uint16x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.2S" }, - "r": { - "register": "Vd.4H" + "b": { + "register": "Vn.2S" + }, + "c": { + "register": "Vm.S[0]" } }, "Architectures": [ @@ -55346,26 +250187,30 @@ ], "instructions": [ [ - "XTN2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_high_u64", + "name": "vmls_n_u16", "arguments": [ - "uint32x2_t r", - "uint64x2_t a" + "uint16x4_t a", + "uint16x4_t b", + "uint16_t c" ], "return_type": { - "value": "uint32x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.4H" }, - "r": { - "register": "Vd.2S" + "b": { + "register": "Vn.4H" + }, + "c": { + "register": "Vm.H[0]" } }, "Architectures": [ @@ -55375,22 +250220,30 @@ ], "instructions": [ [ - "XTN2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_s16", + "name": "vmls_n_u32", "arguments": [ - "int16x8_t a" + "uint32x2_t a", + "uint32x2_t b", + "uint32_t c" ], "return_type": { - "value": "int8x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.2S" + }, + "b": { + "register": "Vn.2S" + }, + "c": { + "register": "Vm.S[0]" } }, "Architectures": [ @@ -55400,22 +250253,30 @@ ], "instructions": [ [ - "XTN" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_s32", + "name": "vmls_s16", "arguments": [ - "int32x4_t a" + "int16x4_t a", + "int16x4_t b", + "int16x4_t c" ], "return_type": { "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.4H" + }, + "b": { + "register": "Vn.4H" + }, + "c": { + "register": "Vm.4H" } }, "Architectures": [ @@ -55425,22 +250286,30 @@ ], "instructions": [ [ - "XTN" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_s64", + "name": "vmls_s32", "arguments": [ - "int64x2_t a" + "int32x2_t a", + "int32x2_t b", + "int32x2_t c" ], "return_type": { "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.2S" + }, + "b": { + "register": "Vn.2S" + }, + "c": { + "register": "Vm.2S" } }, "Architectures": [ @@ -55450,22 +250319,30 @@ ], "instructions": [ [ - "XTN" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_u16", + "name": "vmls_s8", "arguments": [ - "uint16x8_t a" + "int8x8_t a", + "int8x8_t b", + "int8x8_t c" ], "return_type": { - "value": "uint8x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.8B" + }, + "b": { + "register": "Vn.8B" + }, + "c": { + "register": "Vm.8B" } }, "Architectures": [ @@ -55475,22 +250352,30 @@ ], "instructions": [ [ - "XTN" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_u32", + "name": "vmls_u16", "arguments": [ - "uint32x4_t a" + "uint16x4_t a", + "uint16x4_t b", + "uint16x4_t c" ], "return_type": { "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.4H" + }, + "b": { + "register": "Vn.4H" + }, + "c": { + "register": "Vm.4H" } }, "Architectures": [ @@ -55500,22 +250385,30 @@ ], "instructions": [ [ - "XTN" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_u64", + "name": "vmls_u32", "arguments": [ - "uint64x2_t a" + "uint32x2_t a", + "uint32x2_t b", + "uint32x2_t c" ], "return_type": { "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.2S" + }, + "b": { + "register": "Vn.2S" + }, + "c": { + "register": "Vm.2S" } }, "Architectures": [ @@ -55525,22 +250418,30 @@ ], "instructions": [ [ - "XTN" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_f16", + "name": "vmls_u8", "arguments": [ - "float16_t value" + "uint8x8_t a", + "uint8x8_t b", + "uint8x8_t c" ], "return_type": { - "value": "float16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.8B" + }, + "b": { + "register": "Vn.8B" + }, + "c": { + "register": "Vm.8B" } }, "Architectures": [ @@ -55550,47 +250451,71 @@ ], "instructions": [ [ - "DUP" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_f32", + "name": "vmlsl_high_lane_s16", "arguments": [ - "float32_t value" + "int32x4_t a", + "int16x8_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "float32x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "SMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_f64", + "name": "vmlsl_high_lane_s32", "arguments": [ - "float64_t value" + "int64x2_t a", + "int32x4_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "float64x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -55598,333 +250523,432 @@ ], "instructions": [ [ - "DUP" + "SMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_p16", + "name": "vmlsl_high_lane_u16", "arguments": [ - "poly16_t value" + "uint32x4_t a", + "uint16x8_t b", + "uint16x4_t v", + "const int lane" ], "return_type": { - "value": "poly16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "UMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_p8", + "name": "vmlsl_high_lane_u32", "arguments": [ - "poly8_t value" + "uint64x2_t a", + "uint32x4_t b", + "uint32x2_t v", + "const int lane" ], "return_type": { - "value": "poly8x16_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "UMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_s16", + "name": "vmlsl_high_laneq_s16", "arguments": [ - "int16_t value" + "int32x4_t a", + "int16x8_t b", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "SMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_s32", + "name": "vmlsl_high_laneq_s32", "arguments": [ - "int32_t value" + "int64x2_t a", + "int32x4_t b", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "SMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_s64", + "name": "vmlsl_high_laneq_u16", "arguments": [ - "int64_t value" + "uint32x4_t a", + "uint16x8_t b", + "uint16x8_t v", + "const int lane" ], "return_type": { - "value": "int64x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "UMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_s8", + "name": "vmlsl_high_laneq_u32", "arguments": [ - "int8_t value" + "uint64x2_t a", + "uint32x4_t b", + "uint32x4_t v", + "const int lane" ], "return_type": { - "value": "int8x16_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "UMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_u16", + "name": "vmlsl_high_n_s16", "arguments": [ - "uint16_t value" + "int32x4_t a", + "int16x8_t b", + "int16_t c" ], "return_type": { - "value": "uint16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "c": { + "register": "Vm.H[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "SMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_u32", + "name": "vmlsl_high_n_s32", "arguments": [ - "uint32_t value" + "int64x2_t a", + "int32x4_t b", + "int32_t c" ], "return_type": { - "value": "uint32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.S[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "SMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_u64", + "name": "vmlsl_high_n_u16", "arguments": [ - "uint64_t value" + "uint32x4_t a", + "uint16x8_t b", + "uint16_t c" ], "return_type": { - "value": "uint64x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "c": { + "register": "Vm.H[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "UMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_u8", + "name": "vmlsl_high_n_u32", "arguments": [ - "uint8_t value" + "uint64x2_t a", + "uint32x4_t b", + "uint32_t c" ], "return_type": { - "value": "uint8x16_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.S[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "UMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_f16", + "name": "vmlsl_high_s16", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "int32x4_t a", + "int16x8_t b", + "int16x8_t c" ], "return_type": { - "value": "float16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.4S" }, "b": { - "register": "Vm.4H" + "register": "Vn.8H" + }, + "c": { + "register": "Vm.8H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMUL" + "SMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_f32", + "name": "vmlsl_high_s32", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "int64x2_t a", + "int32x4_t b", + "int32x4_t c" ], "return_type": { - "value": "float32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.2D" }, "b": { - "register": "Vm.2S" + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FMUL" + "SMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_f64", + "name": "vmlsl_high_s8", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "int16x8_t a", + "int8x16_t b", + "int8x16_t c" ], "return_type": { - "value": "float64x1_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.8H" }, "b": { - "register": "Dm" + "register": "Vn.16B" + }, + "c": { + "register": "Vm.16B" } }, "Architectures": [ @@ -55932,98 +250956,92 @@ ], "instructions": [ [ - "FMUL" + "SMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_lane_f16", + "name": "vmlsl_high_u16", "arguments": [ - "float16x4_t a", - "float16x4_t v", - "const int lane" + "uint32x4_t a", + "uint16x8_t b", + "uint16x8_t c" ], "return_type": { - "value": "float16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.4S" }, - "lane": { - "minimum": 0, - "maximum": 3 + "b": { + "register": "Vn.8H" }, - "v": { - "register": "Vm.4H" + "c": { + "register": "Vm.8H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMUL" + "UMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_lane_f32", + "name": "vmlsl_high_u32", "arguments": [ - "float32x2_t a", - "float32x2_t v", - "const int lane" + "uint64x2_t a", + "uint32x4_t b", + "uint32x4_t c" ], "return_type": { - "value": "float32x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.2D" }, - "lane": { - "minimum": 0, - "maximum": 1 + "b": { + "register": "Vn.4S" }, - "v": { - "register": "Vm.2S" + "c": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FMUL" + "UMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_lane_f64", + "name": "vmlsl_high_u8", "arguments": [ - "float64x1_t a", - "float64x1_t v", - "const int lane" + "uint16x8_t a", + "uint8x16_t b", + "uint8x16_t c" ], "return_type": { - "value": "float64x1_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.8H" }, - "lane": { - "minimum": 0, - "maximum": 0 + "b": { + "register": "Vn.16B" }, - "v": { - "register": "Vm.1D" + "c": { + "register": "Vm.16B" } }, "Architectures": [ @@ -56031,23 +251049,27 @@ ], "instructions": [ [ - "FMUL" + "UMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_lane_s16", + "name": "vmlsl_lane_s16", "arguments": [ - "int16x4_t a", + "int32x4_t a", + "int16x4_t b", "int16x4_t v", "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.4S" + }, + "b": { "register": "Vn.4H" }, "lane": { @@ -56065,23 +251087,27 @@ ], "instructions": [ [ - "MUL" + "SMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_lane_s32", + "name": "vmlsl_lane_s32", "arguments": [ - "int32x2_t a", + "int64x2_t a", + "int32x2_t b", "int32x2_t v", "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.2D" + }, + "b": { "register": "Vn.2S" }, "lane": { @@ -56099,23 +251125,27 @@ ], "instructions": [ [ - "MUL" + "SMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_lane_u16", + "name": "vmlsl_lane_u16", "arguments": [ - "uint16x4_t a", + "uint32x4_t a", + "uint16x4_t b", "uint16x4_t v", "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.4S" + }, + "b": { "register": "Vn.4H" }, "lane": { @@ -56133,23 +251163,27 @@ ], "instructions": [ [ - "MUL" + "UMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_lane_u32", + "name": "vmlsl_lane_u32", "arguments": [ - "uint32x2_t a", + "uint64x2_t a", + "uint32x2_t b", "uint32x2_t v", "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.2D" + }, + "b": { "register": "Vn.2S" }, "lane": { @@ -56167,23 +251201,27 @@ ], "instructions": [ [ - "MUL" + "UMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_laneq_f16", + "name": "vmlsl_laneq_s16", "arguments": [ - "float16x4_t a", - "float16x8_t v", + "int32x4_t a", + "int16x4_t b", + "int16x8_t v", "const int lane" ], "return_type": { - "value": "float16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.4S" + }, + "b": { "register": "Vn.4H" }, "lane": { @@ -56199,23 +251237,27 @@ ], "instructions": [ [ - "FMUL" + "SMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_laneq_f32", + "name": "vmlsl_laneq_s32", "arguments": [ - "float32x2_t a", - "float32x4_t v", + "int64x2_t a", + "int32x2_t b", + "int32x4_t v", "const int lane" ], "return_type": { - "value": "float32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.2D" + }, + "b": { "register": "Vn.2S" }, "lane": { @@ -56231,31 +251273,35 @@ ], "instructions": [ [ - "FMUL" + "SMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_laneq_f64", + "name": "vmlsl_laneq_u16", "arguments": [ - "float64x1_t a", - "float64x2_t v", + "uint32x4_t a", + "uint16x4_t b", + "uint16x8_t v", "const int lane" ], "return_type": { - "value": "float64x1_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.4H" }, "lane": { "minimum": 0, - "maximum": 1 + "maximum": 7 }, "v": { - "register": "Vm.2D" + "register": "Vm.8H" } }, "Architectures": [ @@ -56263,31 +251309,35 @@ ], "instructions": [ [ - "FMUL" + "UMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_laneq_s16", + "name": "vmlsl_laneq_u32", "arguments": [ - "int16x4_t a", - "int16x8_t v", + "uint64x2_t a", + "uint32x2_t b", + "uint32x4_t v", "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.2S" }, "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "v": { - "register": "Vm.8H" + "register": "Vm.4S" } }, "Architectures": [ @@ -56295,150 +251345,195 @@ ], "instructions": [ [ - "MUL" + "UMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_laneq_s32", + "name": "vmlsl_n_s16", "arguments": [ - "int32x2_t a", - "int32x4_t v", - "const int lane" + "int32x4_t a", + "int16x4_t b", + "int16_t c" ], "return_type": { - "value": "int32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.4S" }, - "lane": { - "minimum": 0, - "maximum": 3 + "b": { + "register": "Vn.4H" }, - "v": { - "register": "Vm.4S" + "c": { + "register": "Vm.H[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "MUL" + "SMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_laneq_u16", + "name": "vmlsl_n_s32", "arguments": [ - "uint16x4_t a", - "uint16x8_t v", - "const int lane" + "int64x2_t a", + "int32x2_t b", + "int32_t c" ], "return_type": { - "value": "uint16x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.2S" + }, + "c": { + "register": "Vm.S[0]" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SMLSL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vmlsl_n_u16", + "arguments": [ + "uint32x4_t a", + "uint16x4_t b", + "uint16_t c" + ], + "return_type": { + "value": "uint32x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4S" }, - "lane": { - "minimum": 0, - "maximum": 7 + "b": { + "register": "Vn.4H" }, - "v": { - "register": "Vm.8H" + "c": { + "register": "Vm.H[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "MUL" + "UMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_laneq_u32", + "name": "vmlsl_n_u32", "arguments": [ - "uint32x2_t a", - "uint32x4_t v", - "const int lane" + "uint64x2_t a", + "uint32x2_t b", + "uint32_t c" ], "return_type": { - "value": "uint32x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.2D" }, - "lane": { - "minimum": 0, - "maximum": 3 + "b": { + "register": "Vn.2S" }, - "v": { - "register": "Vm.4S" + "c": { + "register": "Vm.S[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "MUL" + "UMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_n_f16", + "name": "vmlsl_s16", "arguments": [ - "float16x4_t a", - "float16_t n" + "int32x4_t a", + "int16x4_t b", + "int16x4_t c" ], "return_type": { - "value": "float16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.4S" + }, + "b": { "register": "Vn.4H" }, - "n": { - "register": "Vm.H[0]" + "c": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMUL" + "SMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_n_f32", + "name": "vmlsl_s32", "arguments": [ - "float32x2_t a", - "float32_t b" + "int64x2_t a", + "int32x2_t b", + "int32x2_t c" ], "return_type": { - "value": "float32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.2D" }, "b": { - "register": "Vm.S[0]" + "register": "Vn.2S" + }, + "c": { + "register": "Vm.2S" } }, "Architectures": [ @@ -56448,53 +251543,63 @@ ], "instructions": [ [ - "FMUL" + "SMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_n_f64", + "name": "vmlsl_s8", "arguments": [ - "float64x1_t a", - "float64_t b" + "int16x8_t a", + "int8x8_t b", + "int8x8_t c" ], "return_type": { - "value": "float64x1_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.8H" }, "b": { - "register": "Vm.D[0]" + "register": "Vn.8B" + }, + "c": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMUL" + "SMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_n_s16", + "name": "vmlsl_u16", "arguments": [ - "int16x4_t a", - "int16_t b" + "uint32x4_t a", + "uint16x4_t b", + "uint16x4_t c" ], "return_type": { - "value": "int16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.4S" }, "b": { - "register": "Vm.H[0]" + "register": "Vn.4H" + }, + "c": { + "register": "Vm.4H" } }, "Architectures": [ @@ -56504,26 +251609,30 @@ ], "instructions": [ [ - "MUL" + "UMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_n_s32", + "name": "vmlsl_u32", "arguments": [ - "int32x2_t a", - "int32_t b" + "uint64x2_t a", + "uint32x2_t b", + "uint32x2_t c" ], "return_type": { - "value": "int32x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.2D" }, "b": { - "register": "Vm.S[0]" + "register": "Vn.2S" + }, + "c": { + "register": "Vm.2S" } }, "Architectures": [ @@ -56533,26 +251642,30 @@ ], "instructions": [ [ - "MUL" + "UMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_n_u16", + "name": "vmlsl_u8", "arguments": [ - "uint16x4_t a", - "uint16_t b" + "uint16x8_t a", + "uint8x8_t b", + "uint8x8_t c" ], "return_type": { - "value": "uint16x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.8H" }, "b": { - "register": "Vm.H[0]" + "register": "Vn.8B" + }, + "c": { + "register": "Vm.8B" } }, "Architectures": [ @@ -56562,26 +251675,30 @@ ], "instructions": [ [ - "MUL" + "UMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_n_u32", + "name": "vmlsq_f32", "arguments": [ - "uint32x2_t a", - "uint32_t b" + "float32x4_t a", + "float32x4_t b", + "float32x4_t c" ], "return_type": { - "value": "uint32x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "N/A" }, "b": { - "register": "Vm.S[0]" + "register": "N/A" + }, + "c": { + "register": "N/A" } }, "Architectures": [ @@ -56591,55 +251708,57 @@ ], "instructions": [ [ - "MUL" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_p8", + "name": "vmlsq_f64", "arguments": [ - "poly8x8_t a", - "poly8x8_t b" + "float64x2_t a", + "float64x2_t b", + "float64x2_t c" ], "return_type": { - "value": "poly8x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "N/A" }, "b": { - "register": "Vm.8B" + "register": "N/A" + }, + "c": { + "register": "N/A" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "PMUL" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_s16", + "name": "vmlsq_lane_f32", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "float32x4_t a", + "float32x4_t b", + "float32x2_t v", + "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "float32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "lane": { + "minimum": 0, + "maximum": 1 } }, "Architectures": [ @@ -56649,26 +251768,35 @@ ], "instructions": [ [ - "MUL" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_s32", + "name": "vmlsq_lane_s16", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "int16x8_t a", + "int16x8_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.8H" }, "b": { - "register": "Vm.2S" + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -56678,26 +251806,35 @@ ], "instructions": [ [ - "MUL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_s8", + "name": "vmlsq_lane_s32", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "int32x4_t a", + "int32x4_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "int8x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vd.4S" }, "b": { - "register": "Vm.8B" + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -56707,25 +251844,34 @@ ], "instructions": [ [ - "MUL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_u16", + "name": "vmlsq_lane_u16", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "uint16x8_t a", + "uint16x8_t b", + "uint16x4_t v", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.8H" }, "b": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { "register": "Vm.4H" } }, @@ -56736,25 +251882,34 @@ ], "instructions": [ [ - "MUL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_u32", + "name": "vmlsq_lane_u32", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "uint32x4_t a", + "uint32x4_t b", + "uint32x2_t v", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.4S" }, "b": { + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { "register": "Vm.2S" } }, @@ -56765,60 +251920,62 @@ ], "instructions": [ [ - "MUL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_u8", + "name": "vmlsq_laneq_f32", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "float32x4_t a", + "float32x4_t b", + "float32x4_t v", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" + "lane": { + "minimum": 0, + "maximum": 3 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MUL" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmuld_lane_f64", + "name": "vmlsq_laneq_s16", "arguments": [ - "float64_t a", - "float64x1_t v", + "int16x8_t a", + "int16x8_t b", + "int16x8_t v", "const int lane" ], "return_type": { - "value": "float64_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.8H" + }, + "b": { + "register": "Vn.8H" }, "lane": { "minimum": 0, - "maximum": 0 + "maximum": 7 }, "v": { - "register": "Vm.1D" + "register": "Vm.8H" } }, "Architectures": [ @@ -56826,31 +251983,35 @@ ], "instructions": [ [ - "FMUL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmuld_laneq_f64", + "name": "vmlsq_laneq_s32", "arguments": [ - "float64_t a", - "float64x2_t v", + "int32x4_t a", + "int32x4_t b", + "int32x4_t v", "const int lane" ], "return_type": { - "value": "float64_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.4S" }, "lane": { "minimum": 0, - "maximum": 1 + "maximum": 3 }, "v": { - "register": "Vm.2D" + "register": "Vm.4S" } }, "Architectures": [ @@ -56858,59 +252019,71 @@ ], "instructions": [ [ - "FMUL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulh_f16", + "name": "vmlsq_laneq_u16", "arguments": [ - "float16_t a", - "float16_t b" + "uint16x8_t a", + "uint16x8_t b", + "uint16x8_t v", + "const int lane" ], "return_type": { - "value": "float16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vd.8H" }, "b": { - "register": "Hm" + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMUL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulh_lane_f16", + "name": "vmlsq_laneq_u32", "arguments": [ - "float16_t a", - "float16x4_t v", + "uint32x4_t a", + "uint32x4_t b", + "uint32x4_t v", "const int lane" ], "return_type": { - "value": "float16_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.4S" }, "lane": { "minimum": 0, "maximum": 3 }, "v": { - "register": "Vm.4H" + "register": "Vm.4S" } }, "Architectures": [ @@ -56918,477 +252091,499 @@ ], "instructions": [ [ - "FMUL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulh_laneq_f16", + "name": "vmlsq_n_f32", "arguments": [ - "float16_t a", - "float16x8_t v", - "const int lane" + "float32x4_t a", + "float32x4_t b", + "float32_t c" ], "return_type": { - "value": "float16_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "N/A" }, - "lane": { - "minimum": 0, - "maximum": 7 + "b": { + "register": "N/A" }, - "v": { - "register": "Vm.8H" + "c": { + "register": "N/A" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMUL" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_lane_s16", + "name": "vmlsq_n_s16", "arguments": [ "int16x8_t a", - "int16x4_t v", - "const int lane" + "int16x8_t b", + "int16_t c" ], "return_type": { - "value": "int32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.8H" }, - "lane": { - "minimum": 0, - "maximum": 3 + "b": { + "register": "Vn.8H" }, - "v": { - "register": "Vm.4H" + "c": { + "register": "Vm.H[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMULL2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_lane_s32", + "name": "vmlsq_n_s32", "arguments": [ "int32x4_t a", - "int32x2_t v", - "const int lane" + "int32x4_t b", + "int32_t c" ], "return_type": { - "value": "int64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.4S" }, - "lane": { - "minimum": 0, - "maximum": 1 + "b": { + "register": "Vn.4S" }, - "v": { - "register": "Vm.2S" + "c": { + "register": "Vm.S[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMULL2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_lane_u16", + "name": "vmlsq_n_u16", "arguments": [ "uint16x8_t a", - "uint16x4_t v", - "const int lane" + "uint16x8_t b", + "uint16_t c" ], "return_type": { - "value": "uint32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.8H" }, - "lane": { - "minimum": 0, - "maximum": 3 + "b": { + "register": "Vn.8H" }, - "v": { - "register": "Vm.4H" + "c": { + "register": "Vm.H[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMULL2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_lane_u32", + "name": "vmlsq_n_u32", "arguments": [ "uint32x4_t a", - "uint32x2_t v", - "const int lane" + "uint32x4_t b", + "uint32_t c" ], "return_type": { - "value": "uint64x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.4S" }, - "lane": { - "minimum": 0, - "maximum": 1 + "b": { + "register": "Vn.4S" }, - "v": { - "register": "Vm.2S" + "c": { + "register": "Vm.S[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMULL2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_laneq_s16", + "name": "vmlsq_s16", "arguments": [ "int16x8_t a", - "int16x8_t v", - "const int lane" + "int16x8_t b", + "int16x8_t c" ], "return_type": { - "value": "int32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.8H" }, - "lane": { - "minimum": 0, - "maximum": 7 + "b": { + "register": "Vn.8H" }, - "v": { + "c": { "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMULL2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_laneq_s32", + "name": "vmlsq_s32", "arguments": [ "int32x4_t a", - "int32x4_t v", - "const int lane" + "int32x4_t b", + "int32x4_t c" ], "return_type": { - "value": "int64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.4S" }, - "lane": { - "minimum": 0, - "maximum": 3 + "b": { + "register": "Vn.4S" }, - "v": { + "c": { "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMULL2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_laneq_u16", + "name": "vmlsq_s8", "arguments": [ - "uint16x8_t a", - "uint16x8_t v", - "const int lane" + "int8x16_t a", + "int8x16_t b", + "int8x16_t c" ], "return_type": { - "value": "uint32x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.16B" }, - "lane": { - "minimum": 0, - "maximum": 7 + "b": { + "register": "Vn.16B" }, - "v": { - "register": "Vm.8H" + "c": { + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMULL2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_laneq_u32", + "name": "vmlsq_u16", "arguments": [ - "uint32x4_t a", - "uint32x4_t v", - "const int lane" + "uint16x8_t a", + "uint16x8_t b", + "uint16x8_t c" ], "return_type": { - "value": "uint64x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.8H" }, - "lane": { - "minimum": 0, - "maximum": 3 + "b": { + "register": "Vn.8H" }, - "v": { - "register": "Vm.4S" + "c": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMULL2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_n_s16", + "name": "vmlsq_u32", "arguments": [ - "int16x8_t a", - "int16_t b" + "uint32x4_t a", + "uint32x4_t b", + "uint32x4_t c" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.4S" }, "b": { - "register": "Vm.H[0]" + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMULL2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_n_s32", + "name": "vmlsq_u8", "arguments": [ - "int32x4_t a", - "int32_t b" + "uint8x16_t a", + "uint8x16_t b", + "uint8x16_t c" ], "return_type": { - "value": "int64x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.16B" }, "b": { - "register": "Vm.S[0]" + "register": "Vn.16B" + }, + "c": { + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMULL2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_n_u16", + "name": "vmmlaq_s32", "arguments": [ - "uint16x8_t a", - "uint16_t b" + "int32x4_t r", + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { - "register": "Vm.H[0]" + "register": "Vm.16B" + }, + "r": { + "register": "Vd.4S" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "UMULL2" + "SMMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_n_u32", + "name": "vmmlaq_u32", "arguments": [ - "uint32x4_t a", - "uint32_t b" + "uint32x4_t r", + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.16B" }, "b": { - "register": "Vm.S[0]" + "register": "Vm.16B" + }, + "r": { + "register": "Vd.4S" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "UMULL2" + "UMMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_p64", + "name": "vmov_n_f16", "arguments": [ - "poly64x2_t a", - "poly64x2_t b" + "float16_t value" ], "return_type": { - "value": "poly128_t" + "value": "float16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "PMULL2" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_p8", + "name": "vmov_n_f32", "arguments": [ - "poly8x16_t a", - "poly8x16_t b" + "float32_t value" ], "return_type": { - "value": "poly16x8_t" + "value": "float32x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "PMULL2" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_s16", + "name": "vmov_n_f64", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "float64_t value" ], "return_type": { - "value": "int32x4_t" + "value": "float64x1_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "value": { + "register": "rn" } }, "Architectures": [ @@ -57396,166 +252591,147 @@ ], "instructions": [ [ - "SMULL2" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_s32", + "name": "vmov_n_p16", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "poly16_t value" ], "return_type": { - "value": "int64x2_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMULL2" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_s8", + "name": "vmov_n_p8", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "poly8_t value" ], "return_type": { - "value": "int16x8_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMULL2" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_u16", + "name": "vmov_n_s16", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "int16_t value" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMULL2" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_u32", + "name": "vmov_n_s32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "int32_t value" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMULL2" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_u8", + "name": "vmov_n_s64", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "int64_t value" ], "return_type": { - "value": "uint16x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMULL2" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_lane_s16", + "name": "vmov_n_s8", "arguments": [ - "int16x4_t a", - "int16x4_t v", - "const int lane" + "int8_t value" ], "return_type": { - "value": "int32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "value": { + "register": "rn" } }, "Architectures": [ @@ -57565,31 +252741,22 @@ ], "instructions": [ [ - "SMULL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_lane_s32", + "name": "vmov_n_u16", "arguments": [ - "int32x2_t a", - "int32x2_t v", - "const int lane" + "uint16_t value" ], "return_type": { - "value": "int64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "value": { + "register": "rn" } }, "Architectures": [ @@ -57599,31 +252766,22 @@ ], "instructions": [ [ - "SMULL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_lane_u16", + "name": "vmov_n_u32", "arguments": [ - "uint16x4_t a", - "uint16x4_t v", - "const int lane" + "uint32_t value" ], "return_type": { - "value": "uint32x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "value": { + "register": "rn" } }, "Architectures": [ @@ -57633,31 +252791,22 @@ ], "instructions": [ [ - "UMULL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_lane_u32", + "name": "vmov_n_u64", "arguments": [ - "uint32x2_t a", - "uint32x2_t v", - "const int lane" + "uint64_t value" ], "return_type": { - "value": "uint64x2_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "value": { + "register": "rn" } }, "Architectures": [ @@ -57667,63 +252816,47 @@ ], "instructions": [ [ - "UMULL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_laneq_s16", + "name": "vmov_n_u8", "arguments": [ - "int16x4_t a", - "int16x8_t v", - "const int lane" + "uint8_t value" ], "return_type": { - "value": "int32x4_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMULL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_laneq_s32", + "name": "vmovl_high_s16", "arguments": [ - "int32x2_t a", - "int32x4_t v", - "const int lane" + "int16x8_t a" ], "return_type": { - "value": "int64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vn.8H" } }, "Architectures": [ @@ -57731,31 +252864,22 @@ ], "instructions": [ [ - "SMULL" + "SSHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_laneq_u16", + "name": "vmovl_high_s32", "arguments": [ - "uint16x4_t a", - "uint16x8_t v", - "const int lane" + "int32x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vn.4S" } }, "Architectures": [ @@ -57763,31 +252887,22 @@ ], "instructions": [ [ - "UMULL" + "SSHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_laneq_u32", + "name": "vmovl_high_s8", "arguments": [ - "uint32x2_t a", - "uint32x4_t v", - "const int lane" + "int8x16_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vn.16B" } }, "Architectures": [ @@ -57795,113 +252910,91 @@ ], "instructions": [ [ - "UMULL" + "SSHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_n_s16", + "name": "vmovl_high_u16", "arguments": [ - "int16x4_t a", - "int16_t b" + "uint16x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.H[0]" + "register": "Vn.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMULL" + "USHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_n_s32", + "name": "vmovl_high_u32", "arguments": [ - "int32x2_t a", - "int32_t b" + "uint32x4_t a" ], "return_type": { - "value": "int64x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.S[0]" + "register": "Vn.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMULL" + "USHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_n_u16", + "name": "vmovl_high_u8", "arguments": [ - "uint16x4_t a", - "uint16_t b" + "uint8x16_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.H[0]" + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMULL" + "USHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_n_u32", + "name": "vmovl_s16", "arguments": [ - "uint32x2_t a", - "uint32_t b" + "int16x4_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.S[0]" + "register": "Vn.4H" } }, "Architectures": [ @@ -57911,54 +253004,47 @@ ], "instructions": [ [ - "UMULL" + "SSHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_p64", + "name": "vmovl_s32", "arguments": [ - "poly64_t a", - "poly64_t b" + "int32x2_t a" ], "return_type": { - "value": "poly128_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.1D" - }, - "b": { - "register": "Vm.1D" + "register": "Vn.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "PMULL" + "SSHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_p8", + "name": "vmovl_s8", "arguments": [ - "poly8x8_t a", - "poly8x8_t b" + "int8x8_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" } }, "Architectures": [ @@ -57968,26 +253054,22 @@ ], "instructions": [ [ - "PMULL" + "SSHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_s16", + "name": "vmovl_u16", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "uint16x4_t a" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" } }, "Architectures": [ @@ -57997,26 +253079,22 @@ ], "instructions": [ [ - "SMULL" + "USHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_s32", + "name": "vmovl_u32", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "uint32x2_t a" ], "return_type": { - "value": "int64x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" } }, "Architectures": [ @@ -58026,26 +253104,22 @@ ], "instructions": [ [ - "SMULL" + "USHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_s8", + "name": "vmovl_u8", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "uint8x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" } }, "Architectures": [ @@ -58055,26 +253129,26 @@ ], "instructions": [ [ - "SMULL" + "USHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_u16", + "name": "vmovn_high_s16", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "int8x8_t r", + "int16x8_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.8H" }, - "b": { - "register": "Vm.4H" + "r": { + "register": "Vd.8B" } }, "Architectures": [ @@ -58084,26 +253158,26 @@ ], "instructions": [ [ - "UMULL" + "XTN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_u32", + "name": "vmovn_high_s32", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "int16x4_t r", + "int32x4_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4S" }, - "b": { - "register": "Vm.2S" + "r": { + "register": "Vd.4H" } }, "Architectures": [ @@ -58113,26 +253187,26 @@ ], "instructions": [ [ - "UMULL" + "XTN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_u8", + "name": "vmovn_high_s64", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "int32x2_t r", + "int64x2_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2D" }, - "b": { - "register": "Vm.8B" + "r": { + "register": "Vd.2S" } }, "Architectures": [ @@ -58142,54 +253216,55 @@ ], "instructions": [ [ - "UMULL" + "XTN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_f16", + "name": "vmovn_high_u16", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "uint8x8_t r", + "uint16x8_t a" ], "return_type": { - "value": "float16x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" }, - "b": { - "register": "Vm.8H" + "r": { + "register": "Vd.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMUL" + "XTN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_f32", + "name": "vmovn_high_u32", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "uint16x4_t r", + "uint32x4_t a" ], "return_type": { - "value": "float32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" }, - "b": { - "register": "Vm.4S" + "r": { + "register": "Vd.4H" } }, "Architectures": [ @@ -58199,91 +253274,76 @@ ], "instructions": [ [ - "FMUL" + "XTN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_f64", + "name": "vmovn_high_u64", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "uint32x2_t r", + "uint64x2_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2D" }, - "b": { - "register": "Vm.2D" + "r": { + "register": "Vd.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMUL" + "XTN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_lane_f16", + "name": "vmovn_s16", "arguments": [ - "float16x8_t a", - "float16x4_t v", - "const int lane" + "int16x8_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMUL" + "XTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_lane_f32", + "name": "vmovn_s32", "arguments": [ - "float32x4_t a", - "float32x2_t v", - "const int lane" + "int32x4_t a" ], "return_type": { - "value": "float32x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" } }, "Architectures": [ @@ -58293,63 +253353,47 @@ ], "instructions": [ [ - "FMUL" + "XTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_lane_f64", + "name": "vmovn_s64", "arguments": [ - "float64x2_t a", - "float64x1_t v", - "const int lane" + "int64x2_t a" ], "return_type": { - "value": "float64x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2D" - }, - "lane": { - "minimum": 0, - "maximum": 0 - }, - "v": { - "register": "Vm.1D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMUL" + "XTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_lane_s16", + "name": "vmovn_u16", "arguments": [ - "int16x8_t a", - "int16x4_t v", - "const int lane" + "uint16x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" } }, "Architectures": [ @@ -58359,31 +253403,22 @@ ], "instructions": [ [ - "MUL" + "XTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_lane_s32", + "name": "vmovn_u32", "arguments": [ - "int32x4_t a", - "int32x2_t v", - "const int lane" + "uint32x4_t a" ], "return_type": { - "value": "int32x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" } }, "Architectures": [ @@ -58393,31 +253428,22 @@ ], "instructions": [ [ - "MUL" + "XTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_lane_u16", + "name": "vmovn_u64", "arguments": [ - "uint16x8_t a", - "uint16x4_t v", - "const int lane" + "uint64x2_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "register": "Vn.2D" } }, "Architectures": [ @@ -58427,31 +253453,22 @@ ], "instructions": [ [ - "MUL" + "XTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_lane_u32", + "name": "vmovq_n_f16", "arguments": [ - "uint32x4_t a", - "uint32x2_t v", - "const int lane" + "float16_t value" ], "return_type": { - "value": "uint32x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "value": { + "register": "rn" } }, "Architectures": [ @@ -58461,63 +253478,47 @@ ], "instructions": [ [ - "MUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_laneq_f16", + "name": "vmovq_n_f32", "arguments": [ - "float16x8_t a", - "float16x8_t v", - "const int lane" + "float32_t value" ], "return_type": { - "value": "float16x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_laneq_f32", + "name": "vmovq_n_f64", "arguments": [ - "float32x4_t a", - "float32x4_t v", - "const int lane" + "float64_t value" ], "return_type": { - "value": "float32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "value": { + "register": "rn" } }, "Architectures": [ @@ -58525,214 +253526,172 @@ ], "instructions": [ [ - "FMUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_laneq_f64", + "name": "vmovq_n_p16", "arguments": [ - "float64x2_t a", - "float64x2_t v", - "const int lane" + "poly16_t value" ], "return_type": { - "value": "float64x2_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2D" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_laneq_s16", + "name": "vmovq_n_p8", "arguments": [ - "int16x8_t a", - "int16x8_t v", - "const int lane" + "poly8_t value" ], "return_type": { - "value": "int16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "MUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_laneq_s32", + "name": "vmovq_n_s16", "arguments": [ - "int32x4_t a", - "int32x4_t v", - "const int lane" + "int16_t value" ], "return_type": { - "value": "int32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "MUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_laneq_u16", + "name": "vmovq_n_s32", "arguments": [ - "uint16x8_t a", - "uint16x8_t v", - "const int lane" + "int32_t value" ], "return_type": { - "value": "uint16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "MUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_laneq_u32", + "name": "vmovq_n_s64", "arguments": [ - "uint32x4_t a", - "uint32x4_t v", - "const int lane" + "int64_t value" ], "return_type": { - "value": "uint32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "MUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_n_f16", + "name": "vmovq_n_s8", "arguments": [ - "float16x8_t a", - "float16_t n" + "int8_t value" ], "return_type": { - "value": "float16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "n": { - "register": "Vm.H[0]" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_n_f32", + "name": "vmovq_n_u16", "arguments": [ - "float32x4_t a", - "float32_t b" + "uint16_t value" ], "return_type": { - "value": "float32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.S[0]" + "value": { + "register": "rn" } }, "Architectures": [ @@ -58742,53 +253701,47 @@ ], "instructions": [ [ - "FMUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_n_f64", + "name": "vmovq_n_u32", "arguments": [ - "float64x2_t a", - "float64_t b" + "uint32_t value" ], "return_type": { - "value": "float64x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.D[0]" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_n_s16", + "name": "vmovq_n_u64", "arguments": [ - "int16x8_t a", - "int16_t b" + "uint64_t value" ], "return_type": { - "value": "int16x8_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.H[0]" + "value": { + "register": "rn" } }, "Architectures": [ @@ -58798,26 +253751,22 @@ ], "instructions": [ [ - "MUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_n_s32", + "name": "vmovq_n_u8", "arguments": [ - "int32x4_t a", - "int32_t b" + "uint8_t value" ], "return_type": { - "value": "int32x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.S[0]" + "value": { + "register": "rn" } }, "Architectures": [ @@ -58827,55 +253776,54 @@ ], "instructions": [ [ - "MUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_n_u16", + "name": "vmul_f16", "arguments": [ - "uint16x8_t a", - "uint16_t b" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4H" }, "b": { - "register": "Vm.H[0]" + "register": "Vm.4H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "MUL" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_n_u32", + "name": "vmul_f32", "arguments": [ - "uint32x4_t a", - "uint32_t b" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2S" }, "b": { - "register": "Vm.S[0]" + "register": "Vm.2S" } }, "Architectures": [ @@ -58885,84 +253833,91 @@ ], "instructions": [ [ - "MUL" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_p8", + "name": "vmul_f64", "arguments": [ - "poly8x16_t a", - "poly8x16_t b" + "float64x1_t a", + "float64x1_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Dn" }, "b": { - "register": "Vm.16B" + "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "PMUL" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_s16", + "name": "vmul_lane_f16", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "float16x4_t a", + "float16x4_t v", + "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4H" }, - "b": { - "register": "Vm.8H" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "MUL" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_s32", + "name": "vmul_lane_f32", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "float32x2_t a", + "float32x2_t v", + "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2S" }, - "b": { - "register": "Vm.4S" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -58972,55 +253927,63 @@ ], "instructions": [ [ - "MUL" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_s8", + "name": "vmul_lane_f64", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "float64x1_t a", + "float64x1_t v", + "const int lane" ], "return_type": { - "value": "int8x16_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Dn" }, - "b": { - "register": "Vm.16B" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "v": { + "register": "Vm.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MUL" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_u16", + "name": "vmul_lane_s16", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "int16x4_t a", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4H" }, - "b": { - "register": "Vm.8H" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -59036,20 +253999,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vmulq_u32", + "name": "vmul_lane_s32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "int32x2_t a", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2S" }, - "b": { - "register": "Vm.4S" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -59065,20 +254033,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vmulq_u8", + "name": "vmul_lane_u16", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "uint16x4_t a", + "uint16x4_t v", + "const int lane" ], "return_type": { - "value": "uint8x16_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4H" }, - "b": { - "register": "Vm.16B" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -59094,18 +254067,18 @@ }, { "SIMD_ISA": "Neon", - "name": "vmuls_lane_f32", + "name": "vmul_lane_u32", "arguments": [ - "float32_t a", - "float32x2_t v", + "uint32x2_t a", + "uint32x2_t v", "const int lane" ], "return_type": { - "value": "float32_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vn.2S" }, "lane": { "minimum": 0, @@ -59116,35 +254089,37 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMUL" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmuls_laneq_f32", + "name": "vmul_laneq_f16", "arguments": [ - "float32_t a", - "float32x4_t v", + "float16x4_t a", + "float16x8_t v", "const int lane" ], "return_type": { - "value": "float32_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vn.4H" }, "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "v": { - "register": "Vm.4S" + "register": "Vm.8H" } }, "Architectures": [ @@ -59158,20 +254133,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vmulx_f16", + "name": "vmul_laneq_f32", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "float32x2_t a", + "float32x4_t v", + "const int lane" ], "return_type": { - "value": "float16x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.2S" }, - "b": { - "register": "Vm.4H" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ @@ -59179,26 +254159,31 @@ ], "instructions": [ [ - "FMULX" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulx_f32", + "name": "vmul_laneq_f64", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "float64x1_t a", + "float64x2_t v", + "const int lane" ], "return_type": { - "value": "float32x2_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Dn" }, - "b": { - "register": "Vm.2S" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2D" } }, "Architectures": [ @@ -59206,26 +254191,31 @@ ], "instructions": [ [ - "FMULX" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulx_f64", + "name": "vmul_laneq_s16", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "int16x4_t a", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "float64x1_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.4H" }, - "b": { - "register": "Dm" + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ @@ -59233,31 +254223,31 @@ ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulx_lane_f16", + "name": "vmul_laneq_s32", "arguments": [ - "float16x4_t a", - "float16x4_t v", + "int32x2_t a", + "int32x4_t v", "const int lane" ], "return_type": { - "value": "float16x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.2S" }, "lane": { "minimum": 0, "maximum": 3 }, "v": { - "register": "Vm.4H" + "register": "Vm.4S" } }, "Architectures": [ @@ -59265,31 +254255,31 @@ ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulx_lane_f32", + "name": "vmul_laneq_u16", "arguments": [ - "float32x2_t a", - "float32x2_t v", + "uint16x4_t a", + "uint16x8_t v", "const int lane" ], "return_type": { - "value": "float32x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4H" }, "lane": { "minimum": 0, - "maximum": 1 + "maximum": 7 }, "v": { - "register": "Vm.2S" + "register": "Vm.8H" } }, "Architectures": [ @@ -59297,31 +254287,31 @@ ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulx_lane_f64", + "name": "vmul_laneq_u32", "arguments": [ - "float64x1_t a", - "float64x1_t v", + "uint32x2_t a", + "uint32x4_t v", "const int lane" ], "return_type": { - "value": "float64x1_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.2S" }, "lane": { "minimum": 0, - "maximum": 0 + "maximum": 3 }, "v": { - "register": "Vm.1D" + "register": "Vm.4S" } }, "Architectures": [ @@ -59329,17 +254319,16 @@ ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulx_laneq_f16", + "name": "vmul_n_f16", "arguments": [ "float16x4_t a", - "float16x8_t v", - "const int lane" + "float16_t n" ], "return_type": { "value": "float16x4_t" @@ -59348,30 +254337,26 @@ "a": { "register": "Vn.4H" }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "n": { + "register": "Vm.H[0]" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FMULX" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulx_laneq_f32", + "name": "vmul_n_f32", "arguments": [ "float32x2_t a", - "float32x4_t v", - "const int lane" + "float32_t b" ], "return_type": { "value": "float32x2_t" @@ -59380,30 +254365,27 @@ "a": { "register": "Vn.2S" }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "b": { + "register": "Vm.S[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMULX" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulx_laneq_f64", + "name": "vmul_n_f64", "arguments": [ "float64x1_t a", - "float64x2_t v", - "const int lane" + "float64_t b" ], "return_type": { "value": "float64x1_t" @@ -59412,12 +254394,8 @@ "a": { "register": "Dn" }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2D" + "b": { + "register": "Vm.D[0]" } }, "Architectures": [ @@ -59425,321 +254403,350 @@ ], "instructions": [ [ - "FMULX" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulx_n_f16", + "name": "vmul_n_s16", "arguments": [ - "float16x4_t a", - "float16_t n" + "int16x4_t a", + "int16_t b" ], "return_type": { - "value": "float16x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4H" }, - "n": { + "b": { "register": "Vm.H[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxd_f64", + "name": "vmul_n_s32", "arguments": [ - "float64_t a", - "float64_t b" + "int32x2_t a", + "int32_t b" ], "return_type": { - "value": "float64_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.2S" }, "b": { - "register": "Dm" + "register": "Vm.S[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxd_lane_f64", + "name": "vmul_n_u16", "arguments": [ - "float64_t a", - "float64x1_t v", - "const int lane" + "uint16x4_t a", + "uint16_t b" ], "return_type": { - "value": "float64_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "lane": { - "minimum": 0, - "maximum": 0 + "register": "Vn.4H" }, - "v": { - "register": "Vm.1D" + "b": { + "register": "Vm.H[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxd_laneq_f64", + "name": "vmul_n_u32", "arguments": [ - "float64_t a", - "float64x2_t v", - "const int lane" + "uint32x2_t a", + "uint32_t b" ], "return_type": { - "value": "float64_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.2S" }, - "lane": { - "minimum": 0, - "maximum": 1 + "b": { + "register": "Vm.S[0]" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "MUL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vmul_p8", + "arguments": [ + "poly8x8_t a", + "poly8x8_t b" + ], + "return_type": { + "value": "poly8x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8B" }, - "v": { - "register": "Vm.2D" + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMULX" + "PMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxh_f16", + "name": "vmul_s16", "arguments": [ - "float16_t a", - "float16_t b" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "float16_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vn.4H" }, "b": { - "register": "Hm" + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxh_lane_f16", + "name": "vmul_s32", "arguments": [ - "float16_t a", - "float16x4_t v", - "const int lane" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "float16_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Vn.2S" }, - "v": { - "register": "Vm.4H" + "b": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxh_laneq_f16", + "name": "vmul_s8", "arguments": [ - "float16_t a", - "float16x8_t v", - "const int lane" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "float16_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" - }, - "lane": { - "minimum": 0, - "maximum": 7 + "register": "Vn.8B" }, - "v": { - "register": "Vm.8H" + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxq_f16", + "name": "vmul_u16", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "float16x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4H" }, "b": { - "register": "Vm.8H" + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxq_f32", + "name": "vmul_u32", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "float32x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2S" }, "b": { - "register": "Vm.4S" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxq_f64", + "name": "vmul_u8", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "float64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.8B" }, "b": { - "register": "Vm.2D" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxq_lane_f16", + "name": "vmuld_lane_f64", "arguments": [ - "float16x8_t a", - "float16x4_t v", + "float64_t a", + "float64x1_t v", "const int lane" ], "return_type": { - "value": "float16x8_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Dn" }, "lane": { "minimum": 0, - "maximum": 3 + "maximum": 0 }, "v": { - "register": "Vm.4H" + "register": "Vm.1D" } }, "Architectures": [ @@ -59747,31 +254754,31 @@ ], "instructions": [ [ - "FMULX" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxq_lane_f32", + "name": "vmuld_laneq_f64", "arguments": [ - "float32x4_t a", - "float32x2_t v", + "float64_t a", + "float64x2_t v", "const int lane" ], "return_type": { - "value": "float32x4_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Dn" }, "lane": { "minimum": 0, "maximum": 1 }, "v": { - "register": "Vm.2S" + "register": "Vm.2D" } }, "Architectures": [ @@ -59779,63 +254786,59 @@ ], "instructions": [ [ - "FMULX" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxq_lane_f64", + "name": "vmulh_f16", "arguments": [ - "float64x2_t a", - "float64x1_t v", - "const int lane" + "float16_t a", + "float16_t b" ], "return_type": { - "value": "float64x2_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "lane": { - "minimum": 0, - "maximum": 0 + "register": "Hn" }, - "v": { - "register": "Vm.1D" + "b": { + "register": "Hm" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FMULX" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxq_laneq_f16", + "name": "vmulh_lane_f16", "arguments": [ - "float16x8_t a", - "float16x8_t v", + "float16_t a", + "float16x4_t v", "const int lane" ], "return_type": { - "value": "float16x8_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Hn" }, "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "v": { - "register": "Vm.8H" + "register": "Vm.4H" } }, "Architectures": [ @@ -59843,31 +254846,31 @@ ], "instructions": [ [ - "FMULX" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxq_laneq_f32", + "name": "vmulh_laneq_f16", "arguments": [ - "float32x4_t a", - "float32x4_t v", + "float16_t a", + "float16x8_t v", "const int lane" ], "return_type": { - "value": "float32x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Hn" }, "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "v": { - "register": "Vm.4S" + "register": "Vm.8H" } }, "Architectures": [ @@ -59875,31 +254878,31 @@ ], "instructions": [ [ - "FMULX" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxq_laneq_f64", + "name": "vmull_high_lane_s16", "arguments": [ - "float64x2_t a", - "float64x2_t v", + "int16x8_t a", + "int16x4_t v", "const int lane" ], "return_type": { - "value": "float64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.8H" }, "lane": { "minimum": 0, - "maximum": 1 + "maximum": 3 }, "v": { - "register": "Vm.2D" + "register": "Vm.4H" } }, "Architectures": [ @@ -59907,26 +254910,31 @@ ], "instructions": [ [ - "FMULX" + "SMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxq_n_f16", + "name": "vmull_high_lane_s32", "arguments": [ - "float16x8_t a", - "float16_t n" + "int32x4_t a", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "float16x8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4S" }, - "n": { - "register": "Vm.H[0]" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -59934,26 +254942,31 @@ ], "instructions": [ [ - "FMULX" + "SMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxs_f32", + "name": "vmull_high_lane_u16", "arguments": [ - "float32_t a", - "float32_t b" + "uint16x8_t a", + "uint16x4_t v", + "const int lane" ], "return_type": { - "value": "float32_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vn.8H" }, - "b": { - "register": "Sm" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -59961,24 +254974,24 @@ ], "instructions": [ [ - "FMULX" + "UMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxs_lane_f32", + "name": "vmull_high_lane_u32", "arguments": [ - "float32_t a", - "float32x2_t v", + "uint32x4_t a", + "uint32x2_t v", "const int lane" ], "return_type": { - "value": "float32_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vn.4S" }, "lane": { "minimum": 0, @@ -59993,31 +255006,31 @@ ], "instructions": [ [ - "FMULX" + "UMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxs_laneq_f32", + "name": "vmull_high_laneq_s16", "arguments": [ - "float32_t a", - "float32x4_t v", + "int16x8_t a", + "int16x8_t v", "const int lane" ], "return_type": { - "value": "float32_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vn.8H" }, "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "v": { - "register": "Vm.4S" + "register": "Vm.8H" } }, "Architectures": [ @@ -60025,396 +255038,452 @@ ], "instructions": [ [ - "FMULX" + "SMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvn_p8", + "name": "vmull_high_laneq_s32", "arguments": [ - "poly8x8_t a" + "int32x4_t a", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "poly8x8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "SMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvn_s16", + "name": "vmull_high_laneq_u16", "arguments": [ - "int16x4_t a" + "uint16x8_t a", + "uint16x8_t v", + "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "UMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvn_s32", + "name": "vmull_high_laneq_u32", "arguments": [ - "int32x2_t a" + "uint32x4_t a", + "uint32x4_t v", + "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "UMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvn_s8", + "name": "vmull_high_n_s16", "arguments": [ - "int8x8_t a" + "int16x8_t a", + "int16_t b" ], "return_type": { - "value": "int8x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" + }, + "b": { + "register": "Vm.H[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "SMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvn_u16", + "name": "vmull_high_n_s32", "arguments": [ - "uint16x4_t a" + "int32x4_t a", + "int32_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.S[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "SMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvn_u32", + "name": "vmull_high_n_u16", "arguments": [ - "uint32x2_t a" + "uint16x8_t a", + "uint16_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" + }, + "b": { + "register": "Vm.H[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "UMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvn_u8", + "name": "vmull_high_n_u32", "arguments": [ - "uint8x8_t a" + "uint32x4_t a", + "uint32_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.S[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "UMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvnq_p8", + "name": "vmull_high_p64", "arguments": [ - "poly8x16_t a" + "poly64x2_t a", + "poly64x2_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "MVN" + "PMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvnq_s16", + "name": "vmull_high_p8", "arguments": [ - "int16x8_t a" + "poly8x16_t a", + "poly8x16_t b" ], "return_type": { - "value": "int16x8_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "PMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvnq_s32", + "name": "vmull_high_s16", "arguments": [ - "int32x4_t a" + "int16x8_t a", + "int16x8_t b" ], "return_type": { "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "SMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvnq_s8", + "name": "vmull_high_s32", "arguments": [ - "int8x16_t a" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "int8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "SMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvnq_u16", + "name": "vmull_high_s8", "arguments": [ - "uint16x8_t a" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "SMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvnq_u32", + "name": "vmull_high_u16", "arguments": [ - "uint32x4_t a" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "UMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvnq_u8", + "name": "vmull_high_u32", "arguments": [ - "uint8x16_t a" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "UMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vneg_f16", + "name": "vmull_high_u8", "arguments": [ - "float16x4_t a" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "float16x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FNEG" + "UMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vneg_f32", + "name": "vmull_lane_s16", "arguments": [ - "float32x2_t a" + "int16x4_t a", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "float32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -60424,45 +255493,65 @@ ], "instructions": [ [ - "FNEG" + "SMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vneg_f64", + "name": "vmull_lane_s32", "arguments": [ - "float64x1_t a" + "int32x2_t a", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "float64x1_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FNEG" + "SMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vneg_s16", + "name": "vmull_lane_u16", "arguments": [ - "int16x4_t a" + "uint16x4_t a", + "uint16x4_t v", + "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -60472,22 +255561,31 @@ ], "instructions": [ [ - "NEG" + "UMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vneg_s32", + "name": "vmull_lane_u32", "arguments": [ - "int32x2_t a" + "uint32x2_t a", + "uint32x2_t v", + "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -60497,22 +255595,31 @@ ], "instructions": [ [ - "NEG" + "UMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vneg_s64", + "name": "vmull_laneq_s16", "arguments": [ - "int64x1_t a" + "int16x4_t a", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "int64x1_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ @@ -60520,47 +255627,63 @@ ], "instructions": [ [ - "NEG" + "SMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vneg_s8", + "name": "vmull_laneq_s32", "arguments": [ - "int8x8_t a" + "int32x2_t a", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "int8x8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NEG" + "SMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vnegd_s64", + "name": "vmull_laneq_u16", "arguments": [ - "int64_t a" + "uint16x4_t a", + "uint16x8_t v", + "const int lane" ], "return_type": { - "value": "int64_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ @@ -60568,70 +255691,87 @@ ], "instructions": [ [ - "NEG" + "UMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vnegh_f16", + "name": "vmull_laneq_u32", "arguments": [ - "float16_t a" + "uint32x2_t a", + "uint32x4_t v", + "const int lane" ], "return_type": { - "value": "float16_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FNEG" + "UMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vnegq_f16", + "name": "vmull_n_s16", "arguments": [ - "float16x8_t a" + "int16x4_t a", + "int16_t b" ], "return_type": { - "value": "float16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4H" + }, + "b": { + "register": "Vm.H[0]" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FNEG" + "SMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vnegq_f32", + "name": "vmull_n_s32", "arguments": [ - "float32x4_t a" + "int32x2_t a", + "int32_t b" ], "return_type": { - "value": "float32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2S" + }, + "b": { + "register": "Vm.S[0]" } }, "Architectures": [ @@ -60641,45 +255781,26 @@ ], "instructions": [ [ - "FNEG" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vnegq_f64", - "arguments": [ - "float64x2_t a" - ], - "return_type": { - "value": "float64x2_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "FNEG" + "SMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vnegq_s16", + "name": "vmull_n_u16", "arguments": [ - "int16x8_t a" + "uint16x4_t a", + "uint16_t b" ], "return_type": { - "value": "int16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4H" + }, + "b": { + "register": "Vm.H[0]" } }, "Architectures": [ @@ -60689,22 +255810,26 @@ ], "instructions": [ [ - "NEG" + "UMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vnegq_s32", + "name": "vmull_n_u32", "arguments": [ - "int32x4_t a" + "uint32x2_t a", + "uint32_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2S" + }, + "b": { + "register": "Vm.S[0]" } }, "Architectures": [ @@ -60714,45 +255839,54 @@ ], "instructions": [ [ - "NEG" + "UMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vnegq_s64", + "name": "vmull_p64", "arguments": [ - "int64x2_t a" + "poly64_t a", + "poly64_t b" ], "return_type": { - "value": "int64x2_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.1D" + }, + "b": { + "register": "Vm.1D" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "NEG" + "PMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vnegq_s8", + "name": "vmull_p8", "arguments": [ - "int8x16_t a" + "poly8x8_t a", + "poly8x8_t b" ], "return_type": { - "value": "int8x16_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" } }, "Architectures": [ @@ -60762,26 +255896,26 @@ ], "instructions": [ [ - "NEG" + "PMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorn_s16", + "name": "vmull_s16", "arguments": [ "int16x4_t a", "int16x4_t b" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4H" }, "b": { - "register": "Vm.8B" + "register": "Vm.4H" } }, "Architectures": [ @@ -60791,26 +255925,26 @@ ], "instructions": [ [ - "ORN" + "SMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorn_s32", + "name": "vmull_s32", "arguments": [ "int32x2_t a", "int32x2_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2S" }, "b": { - "register": "Vm.8B" + "register": "Vm.2S" } }, "Architectures": [ @@ -60820,19 +255954,19 @@ ], "instructions": [ [ - "ORN" + "SMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorn_s64", + "name": "vmull_s8", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "int64x1_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -60849,26 +255983,26 @@ ], "instructions": [ [ - "ORN" + "SMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorn_s8", + "name": "vmull_u16", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "int8x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4H" }, "b": { - "register": "Vm.8B" + "register": "Vm.4H" } }, "Architectures": [ @@ -60878,26 +256012,26 @@ ], "instructions": [ [ - "ORN" + "UMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorn_u16", + "name": "vmull_u32", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2S" }, "b": { - "register": "Vm.8B" + "register": "Vm.2S" } }, "Architectures": [ @@ -60907,19 +256041,19 @@ ], "instructions": [ [ - "ORN" + "UMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorn_u32", + "name": "vmull_u8", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { @@ -60936,55 +256070,54 @@ ], "instructions": [ [ - "ORN" + "UMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorn_u64", + "name": "vmulq_f16", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "uint64x1_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" }, "b": { - "register": "Vm.8B" + "register": "Vm.8H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "ORN" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorn_u8", + "name": "vmulq_f32", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4S" }, "b": { - "register": "Vm.8B" + "register": "Vm.4S" } }, "Architectures": [ @@ -60994,84 +256127,91 @@ ], "instructions": [ [ - "ORN" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vornq_s16", + "name": "vmulq_f64", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "int16x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.2D" }, "b": { - "register": "Vm.16B" + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ORN" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vornq_s32", + "name": "vmulq_lane_f16", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "float16x8_t a", + "float16x4_t v", + "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, - "b": { - "register": "Vm.16B" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "ORN" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vornq_s64", + "name": "vmulq_lane_f32", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "float32x4_t a", + "float32x2_t v", + "const int lane" ], "return_type": { - "value": "int64x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" }, - "b": { - "register": "Vm.16B" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -61081,55 +256221,63 @@ ], "instructions": [ [ - "ORN" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vornq_s8", + "name": "vmulq_lane_f64", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "float64x2_t a", + "float64x1_t v", + "const int lane" ], "return_type": { - "value": "int8x16_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.2D" }, - "b": { - "register": "Vm.16B" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "v": { + "register": "Vm.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ORN" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vornq_u16", + "name": "vmulq_lane_s16", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "int16x8_t a", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, - "b": { - "register": "Vm.16B" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -61139,26 +256287,31 @@ ], "instructions": [ [ - "ORN" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vornq_u32", + "name": "vmulq_lane_s32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "int32x4_t a", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" }, - "b": { - "register": "Vm.16B" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -61168,26 +256321,31 @@ ], "instructions": [ [ - "ORN" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vornq_u64", + "name": "vmulq_lane_u16", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "uint16x8_t a", + "uint16x4_t v", + "const int lane" ], "return_type": { - "value": "uint64x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, - "b": { - "register": "Vm.16B" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -61197,26 +256355,31 @@ ], "instructions": [ [ - "ORN" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vornq_u8", + "name": "vmulq_lane_u32", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "uint32x4_t a", + "uint32x2_t v", + "const int lane" ], "return_type": { - "value": "uint8x16_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.16B" + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -61226,258 +256389,278 @@ ], "instructions": [ [ - "ORN" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorr_s16", + "name": "vmulq_laneq_f16", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "float16x8_t a", + "float16x8_t v", + "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" }, - "b": { - "register": "Vm.8B" + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ORR" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorr_s32", + "name": "vmulq_laneq_f32", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "float32x4_t a", + "float32x4_t v", + "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4S" }, - "b": { - "register": "Vm.8B" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ORR" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorr_s64", + "name": "vmulq_laneq_f64", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "float64x2_t a", + "float64x2_t v", + "const int lane" ], "return_type": { - "value": "int64x1_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2D" }, - "b": { - "register": "Vm.8B" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ORR" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorr_s8", + "name": "vmulq_laneq_s16", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "int16x8_t a", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "int8x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" }, - "b": { - "register": "Vm.8B" + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ORR" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorr_u16", + "name": "vmulq_laneq_s32", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "int32x4_t a", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4S" }, - "b": { - "register": "Vm.8B" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ORR" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorr_u32", + "name": "vmulq_laneq_u16", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "uint16x8_t a", + "uint16x8_t v", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" }, - "b": { - "register": "Vm.8B" + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ORR" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorr_u64", + "name": "vmulq_laneq_u32", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "uint32x4_t a", + "uint32x4_t v", + "const int lane" ], "return_type": { - "value": "uint64x1_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4S" }, - "b": { - "register": "Vm.8B" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ORR" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorr_u8", + "name": "vmulq_n_f16", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "float16x8_t a", + "float16_t n" ], "return_type": { - "value": "uint8x8_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" }, - "b": { - "register": "Vm.8B" + "n": { + "register": "Vm.H[0]" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "ORR" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorrq_s16", + "name": "vmulq_n_f32", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "float32x4_t a", + "float32_t b" ], "return_type": { - "value": "int16x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" }, "b": { - "register": "Vm.16B" + "register": "Vm.S[0]" } }, "Architectures": [ @@ -61487,55 +256670,53 @@ ], "instructions": [ [ - "ORR" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorrq_s32", + "name": "vmulq_n_f64", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "float64x2_t a", + "float64_t b" ], "return_type": { - "value": "int32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.2D" }, "b": { - "register": "Vm.16B" + "register": "Vm.D[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ORR" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorrq_s64", + "name": "vmulq_n_s16", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "int16x8_t a", + "int16_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, "b": { - "register": "Vm.16B" + "register": "Vm.H[0]" } }, "Architectures": [ @@ -61545,26 +256726,26 @@ ], "instructions": [ [ - "ORR" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorrq_s8", + "name": "vmulq_n_s32", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "int32x4_t a", + "int32_t b" ], "return_type": { - "value": "int8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" }, "b": { - "register": "Vm.16B" + "register": "Vm.S[0]" } }, "Architectures": [ @@ -61574,26 +256755,26 @@ ], "instructions": [ [ - "ORR" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorrq_u16", + "name": "vmulq_n_u16", "arguments": [ "uint16x8_t a", - "uint16x8_t b" + "uint16_t b" ], "return_type": { "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, "b": { - "register": "Vm.16B" + "register": "Vm.H[0]" } }, "Architectures": [ @@ -61603,26 +256784,26 @@ ], "instructions": [ [ - "ORR" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorrq_u32", + "name": "vmulq_n_u32", "arguments": [ "uint32x4_t a", - "uint32x4_t b" + "uint32_t b" ], "return_type": { "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" }, "b": { - "register": "Vm.16B" + "register": "Vm.S[0]" } }, "Architectures": [ @@ -61632,19 +256813,19 @@ ], "instructions": [ [ - "ORR" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorrq_u64", + "name": "vmulq_p8", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "poly8x16_t a", + "poly8x16_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { @@ -61661,26 +256842,26 @@ ], "instructions": [ [ - "ORR" + "PMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorrq_u8", + "name": "vmulq_s16", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, "b": { - "register": "Vm.16B" + "register": "Vm.8H" } }, "Architectures": [ @@ -61690,26 +256871,26 @@ ], "instructions": [ [ - "ORR" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadal_s16", + "name": "vmulq_s32", "arguments": [ - "int32x2_t a", - "int16x4_t b" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.4S" }, "b": { - "register": "Vn.4H" + "register": "Vm.4S" } }, "Architectures": [ @@ -61719,26 +256900,26 @@ ], "instructions": [ [ - "SADALP" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadal_s32", + "name": "vmulq_s8", "arguments": [ - "int64x1_t a", - "int32x2_t b" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "int64x1_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vn.16B" }, "b": { - "register": "Vn.2S" + "register": "Vm.16B" } }, "Architectures": [ @@ -61748,26 +256929,26 @@ ], "instructions": [ [ - "SADALP" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadal_s8", + "name": "vmulq_u16", "arguments": [ - "int16x4_t a", - "int8x8_t b" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int16x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.8H" }, "b": { - "register": "Vn.8B" + "register": "Vm.8H" } }, "Architectures": [ @@ -61777,26 +256958,26 @@ ], "instructions": [ [ - "SADALP" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadal_u16", + "name": "vmulq_u32", "arguments": [ - "uint32x2_t a", - "uint16x4_t b" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.4S" }, "b": { - "register": "Vn.4H" + "register": "Vm.4S" } }, "Architectures": [ @@ -61806,26 +256987,26 @@ ], "instructions": [ [ - "UADALP" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadal_u32", + "name": "vmulq_u8", "arguments": [ - "uint64x1_t a", - "uint32x2_t b" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "uint64x1_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vn.16B" }, "b": { - "register": "Vn.2S" + "register": "Vm.16B" } }, "Architectures": [ @@ -61835,456 +257016,481 @@ ], "instructions": [ [ - "UADALP" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadal_u8", + "name": "vmuls_lane_f32", "arguments": [ - "uint16x4_t a", - "uint8x8_t b" + "float32_t a", + "float32x2_t v", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Sn" }, - "b": { - "register": "Vn.8B" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADALP" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadalq_s16", + "name": "vmuls_laneq_f32", "arguments": [ - "int32x4_t a", - "int16x8_t b" + "float32_t a", + "float32x4_t v", + "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Sn" }, - "b": { - "register": "Vn.8H" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADALP" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadalq_s32", + "name": "vmulx_f16", "arguments": [ - "int64x2_t a", - "int32x4_t b" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "int64x2_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.4H" }, "b": { - "register": "Vn.4S" + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADALP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadalq_s8", + "name": "vmulx_f32", "arguments": [ - "int16x8_t a", - "int8x16_t b" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "int16x8_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vn.2S" }, "b": { - "register": "Vn.16B" + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADALP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadalq_u16", + "name": "vmulx_f64", "arguments": [ - "uint32x4_t a", - "uint16x8_t b" + "float64x1_t a", + "float64x1_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Dn" }, "b": { - "register": "Vn.8H" + "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADALP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadalq_u32", + "name": "vmulx_lane_f16", "arguments": [ - "uint64x2_t a", - "uint32x4_t b" + "float16x4_t a", + "float16x4_t v", + "const int lane" ], "return_type": { - "value": "uint64x2_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.4H" }, - "b": { - "register": "Vn.4S" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADALP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadalq_u8", + "name": "vmulx_lane_f32", "arguments": [ - "uint16x8_t a", - "uint8x16_t b" + "float32x2_t a", + "float32x2_t v", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vn.2S" }, - "b": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADALP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadd_f16", + "name": "vmulx_lane_f64", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "float64x1_t a", + "float64x1_t v", + "const int lane" ], "return_type": { - "value": "float16x4_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Dn" }, - "b": { - "register": "Vm.4H" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "v": { + "register": "Vm.1D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FADDP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadd_f32", + "name": "vmulx_laneq_f16", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "float16x4_t a", + "float16x8_t v", + "const int lane" ], "return_type": { - "value": "float32x2_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4H" }, - "b": { - "register": "Vm.2S" + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FADDP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadd_s16", + "name": "vmulx_laneq_f32", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "float32x2_t a", + "float32x4_t v", + "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.2S" }, - "b": { - "register": "Vm.4H" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadd_s32", + "name": "vmulx_laneq_f64", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "float64x1_t a", + "float64x2_t v", + "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Dn" }, - "b": { - "register": "Vm.2S" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadd_s8", + "name": "vmulx_n_f16", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "float16x4_t a", + "float16_t n" ], "return_type": { - "value": "int8x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4H" }, - "b": { - "register": "Vm.8B" + "n": { + "register": "Vm.H[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadd_u16", + "name": "vmulxd_f64", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "float64_t a", + "float64_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Dn" }, "b": { - "register": "Vm.4H" + "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadd_u32", + "name": "vmulxd_lane_f64", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "float64_t a", + "float64x1_t v", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Dn" }, - "b": { - "register": "Vm.2S" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "v": { + "register": "Vm.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadd_u8", + "name": "vmulxd_laneq_f64", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "float64_t a", + "float64x2_t v", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Dn" }, - "b": { - "register": "Vm.8B" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddd_f64", + "name": "vmulxh_f16", "arguments": [ - "float64x2_t a" + "float16_t a", + "float16_t b" ], "return_type": { - "value": "float64_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Hn" + }, + "b": { + "register": "Hm" } }, "Architectures": [ @@ -62292,22 +257498,31 @@ ], "instructions": [ [ - "FADDP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddd_s64", + "name": "vmulxh_lane_f16", "arguments": [ - "int64x2_t a" + "float16_t a", + "float16x4_t v", + "const int lane" ], "return_type": { - "value": "int64_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Hn" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -62315,22 +257530,31 @@ ], "instructions": [ [ - "ADDP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddd_u64", + "name": "vmulxh_laneq_f16", "arguments": [ - "uint64x2_t a" + "float16_t a", + "float16x8_t v", + "const int lane" ], "return_type": { - "value": "uint64_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Hn" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ @@ -62338,326 +257562,390 @@ ], "instructions": [ [ - "ADDP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddl_s16", + "name": "vmulxq_f16", "arguments": [ - "int16x4_t a" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "int32x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddl_s32", + "name": "vmulxq_f32", "arguments": [ - "int32x2_t a" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "int64x1_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddl_s8", + "name": "vmulxq_f64", "arguments": [ - "int8x8_t a" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "int16x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddl_u16", + "name": "vmulxq_lane_f16", "arguments": [ - "uint16x4_t a" + "float16x8_t a", + "float16x4_t v", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddl_u32", + "name": "vmulxq_lane_f32", "arguments": [ - "uint32x2_t a" + "float32x4_t a", + "float32x2_t v", + "const int lane" ], "return_type": { - "value": "uint64x1_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddl_u8", + "name": "vmulxq_lane_f64", "arguments": [ - "uint8x8_t a" + "float64x2_t a", + "float64x1_t v", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2D" + }, + "lane": { + "minimum": 0, + "maximum": 0 + }, + "v": { + "register": "Vm.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddlq_s16", + "name": "vmulxq_laneq_f16", "arguments": [ - "int16x8_t a" + "float16x8_t a", + "float16x8_t v", + "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddlq_s32", + "name": "vmulxq_laneq_f32", "arguments": [ - "int32x4_t a" + "float32x4_t a", + "float32x4_t v", + "const int lane" ], "return_type": { - "value": "int64x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddlq_s8", + "name": "vmulxq_laneq_f64", "arguments": [ - "int8x16_t a" + "float64x2_t a", + "float64x2_t v", + "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.2D" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddlq_u16", + "name": "vmulxq_n_f16", "arguments": [ - "uint16x8_t a" + "float16x8_t a", + "float16_t n" ], "return_type": { - "value": "uint32x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" + }, + "n": { + "register": "Vm.H[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddlq_u32", + "name": "vmulxs_f32", "arguments": [ - "uint32x4_t a" + "float32_t a", + "float32_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Sn" + }, + "b": { + "register": "Sm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddlq_u8", + "name": "vmulxs_lane_f32", "arguments": [ - "uint8x16_t a" + "float32_t a", + "float32x2_t v", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Sn" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddq_f16", + "name": "vmulxs_laneq_f32", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "float32_t a", + "float32x4_t v", + "const int lane" ], "return_type": { - "value": "float16x8_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Sn" }, - "b": { - "register": "Vm.8H" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ @@ -62665,347 +257953,322 @@ ], "instructions": [ [ - "FADDP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddq_f32", + "name": "vmvn_p8", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "poly8x8_t a" ], "return_type": { - "value": "float32x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Vn.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FADDP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddq_f64", + "name": "vmvn_s16", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "int16x4_t a" ], "return_type": { - "value": "float64x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "register": "Vn.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FADDP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddq_s16", + "name": "vmvn_s32", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int32x2_t a" ], "return_type": { - "value": "int16x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Vn.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ADDP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddq_s32", + "name": "vmvn_s8", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int8x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "a": { + "register": "Vn.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ADDP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddq_s64", + "name": "vmvn_u16", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "uint16x4_t a" ], "return_type": { - "value": "int64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "register": "Vn.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ADDP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddq_s8", + "name": "vmvn_u32", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "uint32x2_t a" ], "return_type": { - "value": "int8x16_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "register": "Vn.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ADDP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddq_u16", + "name": "vmvn_u8", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "uint8x8_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Vn.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ADDP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddq_u32", + "name": "vmvnq_p8", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "poly8x16_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Vn.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ADDP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddq_u64", + "name": "vmvnq_s16", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "int16x8_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "register": "Vn.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ADDP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddq_u8", + "name": "vmvnq_s32", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "int32x4_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ADDP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadds_f32", + "name": "vmvnq_s8", "arguments": [ - "float32x2_t a" + "int8x16_t a" ], "return_type": { - "value": "float32_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FADDP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmax_f16", + "name": "vmvnq_u16", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "uint16x8_t a" ], "return_type": { - "value": "float16x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "register": "Vn.16B" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMAXP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmax_f32", + "name": "vmvnq_u32", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "uint32x4_t a" ], "return_type": { - "value": "float32x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" + "register": "Vn.16B" } }, "Architectures": [ @@ -63015,26 +258278,22 @@ ], "instructions": [ [ - "FMAXP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmax_s16", + "name": "vmvnq_u8", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "uint8x16_t a" ], "return_type": { - "value": "int16x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "register": "Vn.16B" } }, "Architectures": [ @@ -63044,55 +258303,46 @@ ], "instructions": [ [ - "SMAXP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmax_s32", + "name": "vneg_f16", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "float16x4_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" + "register": "Vn.4H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SMAXP" + "FNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmax_s8", + "name": "vneg_f32", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "float32x2_t a" ], "return_type": { - "value": "int8x8_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" + "register": "Vn.2S" } }, "Architectures": [ @@ -63102,55 +258352,45 @@ ], "instructions": [ [ - "SMAXP" + "FNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmax_u16", + "name": "vneg_f64", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "float64x1_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMAXP" + "FNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmax_u32", + "name": "vneg_s16", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "int16x4_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" + "register": "Vn.4H" } }, "Architectures": [ @@ -63160,26 +258400,22 @@ ], "instructions": [ [ - "UMAXP" + "NEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmax_u8", + "name": "vneg_s32", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "int32x2_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" + "register": "Vn.2S" } }, "Architectures": [ @@ -63189,26 +258425,22 @@ ], "instructions": [ [ - "UMAXP" + "NEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxnm_f16", + "name": "vneg_s64", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "int64x1_t a" ], "return_type": { - "value": "float16x4_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "register": "Dn" } }, "Architectures": [ @@ -63216,53 +258448,47 @@ ], "instructions": [ [ - "FMAXNMP" + "NEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxnm_f32", + "name": "vneg_s8", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "int8x8_t a" ], "return_type": { - "value": "float32x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" + "register": "Vn.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAXNMP" + "NEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxnmq_f16", + "name": "vnegd_s64", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "int64_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Dn" } }, "Architectures": [ @@ -63270,99 +258496,95 @@ ], "instructions": [ [ - "FMAXNMP" + "NEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxnmq_f32", + "name": "vnegh_f16", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "float16_t a" ], "return_type": { - "value": "float32x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Hn" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FMAXNMP" + "FNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxnmq_f64", + "name": "vnegq_f16", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "float16x8_t a" ], "return_type": { - "value": "float64x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "register": "Vn.8H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FMAXNMP" + "FNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxnmqd_f64", + "name": "vnegq_f32", "arguments": [ - "float64x2_t a" + "float32x4_t a" ], "return_type": { - "value": "float64_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAXNMP" + "FNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxnms_f32", + "name": "vnegq_f64", "arguments": [ - "float32x2_t a" + "float64x2_t a" ], "return_type": { - "value": "float32_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.2D" } }, "Architectures": [ @@ -63370,80 +258592,72 @@ ], "instructions": [ [ - "FMAXNMP" + "FNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxq_f16", + "name": "vnegq_s16", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "int16x8_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAXP" + "NEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxq_f32", + "name": "vnegq_s32", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "int32x4_t a" ], "return_type": { - "value": "float32x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAXP" + "NEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxq_f64", + "name": "vnegq_s64", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "int64x2_t a" ], "return_type": { - "value": "float64x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" } }, "Architectures": [ @@ -63451,262 +258665,283 @@ ], "instructions": [ [ - "FMAXP" + "NEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxq_s16", + "name": "vnegq_s8", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int8x16_t a" ], "return_type": { - "value": "int16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Vn.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMAXP" + "NEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxq_s32", + "name": "vorn_s16", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.8B" }, "b": { - "register": "Vm.4S" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMAXP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxq_s8", + "name": "vorn_s32", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "int8x16_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8B" }, "b": { - "register": "Vm.16B" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMAXP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxq_u16", + "name": "vorn_s64", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "int64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" }, "b": { - "register": "Vm.8H" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMAXP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxq_u32", + "name": "vorn_s8", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.8B" }, "b": { - "register": "Vm.4S" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMAXP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxq_u8", + "name": "vorn_u16", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8B" }, "b": { - "register": "Vm.16B" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMAXP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxqd_f64", + "name": "vorn_u32", "arguments": [ - "float64x2_t a" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "float64_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAXP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxs_f32", + "name": "vorn_u64", "arguments": [ - "float32x2_t a" + "uint64x1_t a", + "uint64x1_t b" ], "return_type": { - "value": "float32_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAXP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmin_f16", + "name": "vorn_u8", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "float16x4_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.8B" }, "b": { - "register": "Vm.4H" + "register": "Vm.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMINP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmin_f32", + "name": "vornq_s16", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "float32x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.16B" }, "b": { - "register": "Vm.2S" + "register": "Vm.16B" } }, "Architectures": [ @@ -63716,26 +258951,26 @@ ], "instructions": [ [ - "FMINP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmin_s16", + "name": "vornq_s32", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.16B" }, "b": { - "register": "Vm.4H" + "register": "Vm.16B" } }, "Architectures": [ @@ -63745,26 +258980,26 @@ ], "instructions": [ [ - "SMINP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmin_s32", + "name": "vornq_s64", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.16B" }, "b": { - "register": "Vm.2S" + "register": "Vm.16B" } }, "Architectures": [ @@ -63774,26 +259009,26 @@ ], "instructions": [ [ - "SMINP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmin_s8", + "name": "vornq_s8", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "int8x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.16B" }, "b": { - "register": "Vm.8B" + "register": "Vm.16B" } }, "Architectures": [ @@ -63803,26 +259038,26 @@ ], "instructions": [ [ - "SMINP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmin_u16", + "name": "vornq_u16", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.16B" }, "b": { - "register": "Vm.4H" + "register": "Vm.16B" } }, "Architectures": [ @@ -63832,26 +259067,26 @@ ], "instructions": [ [ - "UMINP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmin_u32", + "name": "vornq_u32", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.16B" }, "b": { - "register": "Vm.2S" + "register": "Vm.16B" } }, "Architectures": [ @@ -63861,26 +259096,26 @@ ], "instructions": [ [ - "UMINP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmin_u8", + "name": "vornq_u64", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.16B" }, "b": { - "register": "Vm.8B" + "register": "Vm.16B" } }, "Architectures": [ @@ -63890,329 +259125,361 @@ ], "instructions": [ [ - "UMINP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminnm_f16", + "name": "vornq_u8", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "float16x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.16B" }, "b": { - "register": "Vm.4H" + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINNMP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminnm_f32", + "name": "vorr_s16", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "float32x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.8B" }, "b": { - "register": "Vm.2S" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINNMP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminnmq_f16", + "name": "vorr_s32", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "float16x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" }, "b": { - "register": "Vm.8H" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINNMP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminnmq_f32", + "name": "vorr_s64", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "int64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "float32x4_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.8B" }, "b": { - "register": "Vm.4S" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINNMP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminnmq_f64", + "name": "vorr_s8", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "float64x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.8B" }, "b": { - "register": "Vm.2D" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINNMP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminnmqd_f64", + "name": "vorr_u16", "arguments": [ - "float64x2_t a" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "float64_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINNMP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminnms_f32", + "name": "vorr_u32", "arguments": [ - "float32x2_t a" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "float32_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINNMP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminq_f16", + "name": "vorr_u64", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "uint64x1_t a", + "uint64x1_t b" ], "return_type": { - "value": "float16x8_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" }, "b": { - "register": "Vm.8H" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminq_f32", + "name": "vorr_u8", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "float32x4_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.8B" }, "b": { - "register": "Vm.4S" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminq_f64", + "name": "vorrq_s16", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "float64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.16B" }, "b": { - "register": "Vm.2D" + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminq_s16", + "name": "vorrq_s32", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { - "register": "Vm.8H" + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMINP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminq_s32", + "name": "vorrq_s64", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.16B" }, "b": { - "register": "Vm.4S" + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMINP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminq_s8", + "name": "vorrq_s8", "arguments": [ "int8x16_t a", "int8x16_t b" @@ -64229,17 +259496,19 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMINP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminq_u16", + "name": "vorrq_u16", "arguments": [ "uint16x8_t a", "uint16x8_t b" @@ -64249,24 +259518,26 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { - "register": "Vm.8H" + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMINP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminq_u32", + "name": "vorrq_u32", "arguments": [ "uint32x4_t a", "uint32x4_t b" @@ -64276,30 +259547,32 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.16B" }, "b": { - "register": "Vm.4S" + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMINP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminq_u8", + "name": "vorrq_u64", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { @@ -64310,72 +259583,90 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMINP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminqd_f64", + "name": "vorrq_u8", "arguments": [ - "float64x2_t a" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "float64_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmins_f32", + "name": "vpadal_s16", "arguments": [ - "float32x2_t a" + "int32x2_t a", + "int16x4_t b" ], "return_type": { - "value": "float32_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.2S" + }, + "b": { + "register": "Vn.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINP" + "SADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabs_s16", + "name": "vpadal_s32", "arguments": [ - "int16x4_t a" + "int64x1_t a", + "int32x2_t b" ], "return_type": { - "value": "int16x4_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.1D" + }, + "b": { + "register": "Vn.2S" } }, "Architectures": [ @@ -64385,22 +259676,26 @@ ], "instructions": [ [ - "SQABS" + "SADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabs_s32", + "name": "vpadal_s8", "arguments": [ - "int32x2_t a" + "int16x4_t a", + "int8x8_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.4H" + }, + "b": { + "register": "Vn.8B" } }, "Architectures": [ @@ -64410,45 +259705,55 @@ ], "instructions": [ [ - "SQABS" + "SADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabs_s64", + "name": "vpadal_u16", "arguments": [ - "int64x1_t a" + "uint32x2_t a", + "uint16x4_t b" ], "return_type": { - "value": "int64x1_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.2S" + }, + "b": { + "register": "Vn.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQABS" + "UADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabs_s8", + "name": "vpadal_u32", "arguments": [ - "int8x8_t a" + "uint64x1_t a", + "uint32x2_t b" ], "return_type": { - "value": "int8x8_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vd.1D" + }, + "b": { + "register": "Vn.2S" } }, "Architectures": [ @@ -64458,91 +259763,113 @@ ], "instructions": [ [ - "SQABS" + "UADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabsb_s8", + "name": "vpadal_u8", "arguments": [ - "int8_t a" + "uint16x4_t a", + "uint8x8_t b" ], "return_type": { - "value": "int8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Bn" + "register": "Vd.4H" + }, + "b": { + "register": "Vn.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQABS" + "UADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabsd_s64", + "name": "vpadalq_s16", "arguments": [ - "int64_t a" + "int32x4_t a", + "int16x8_t b" ], "return_type": { - "value": "int64_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQABS" + "SADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabsh_s16", + "name": "vpadalq_s32", "arguments": [ - "int16_t a" + "int64x2_t a", + "int32x4_t b" ], "return_type": { - "value": "int16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQABS" + "SADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabsq_s16", + "name": "vpadalq_s8", "arguments": [ - "int16x8_t a" + "int16x8_t a", + "int8x16_t b" ], "return_type": { "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.8H" + }, + "b": { + "register": "Vn.16B" } }, "Architectures": [ @@ -64552,22 +259879,26 @@ ], "instructions": [ [ - "SQABS" + "SADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabsq_s32", + "name": "vpadalq_u16", "arguments": [ - "int32x4_t a" + "uint32x4_t a", + "uint16x8_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" } }, "Architectures": [ @@ -64577,44 +259908,54 @@ ], "instructions": [ [ - "SQABS" + "UADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabsq_s64", + "name": "vpadalq_u32", "arguments": [ - "int64x2_t a" + "uint64x2_t a", + "uint32x4_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQABS" + "UADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabsq_s8", + "name": "vpadalq_u8", "arguments": [ - "int8x16_t a" + "uint16x8_t a", + "uint8x16_t b" ], "return_type": { - "value": "int8x16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.8H" + }, + "b": { "register": "Vn.16B" } }, @@ -64625,49 +259966,54 @@ ], "instructions": [ [ - "SQABS" + "UADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabss_s32", + "name": "vpadd_f16", "arguments": [ - "int32_t a" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "int32_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "SQABS" + "FADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqadd_s16", + "name": "vpadd_f32", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "int16x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.2S" }, "b": { - "register": "Vm.4H" + "register": "Vm.2S" } }, "Architectures": [ @@ -64677,26 +260023,26 @@ ], "instructions": [ [ - "SQADD" + "FADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqadd_s32", + "name": "vpadd_s16", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4H" }, "b": { - "register": "Vm.2S" + "register": "Vm.4H" } }, "Architectures": [ @@ -64706,26 +260052,26 @@ ], "instructions": [ [ - "SQADD" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqadd_s64", + "name": "vpadd_s32", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "int64x1_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.2S" }, "b": { - "register": "Dm" + "register": "Vm.2S" } }, "Architectures": [ @@ -64735,13 +260081,13 @@ ], "instructions": [ [ - "SQADD" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqadd_s8", + "name": "vpadd_s8", "arguments": [ "int8x8_t a", "int8x8_t b" @@ -64764,13 +260110,13 @@ ], "instructions": [ [ - "SQADD" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqadd_u16", + "name": "vpadd_u16", "arguments": [ "uint16x4_t a", "uint16x4_t b" @@ -64793,13 +260139,13 @@ ], "instructions": [ [ - "UQADD" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqadd_u32", + "name": "vpadd_u32", "arguments": [ "uint32x2_t a", "uint32x2_t b" @@ -64822,26 +260168,26 @@ ], "instructions": [ [ - "UQADD" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqadd_u64", + "name": "vpadd_u8", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "uint64x1_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.8B" }, "b": { - "register": "Dm" + "register": "Vm.8B" } }, "Architectures": [ @@ -64851,55 +260197,45 @@ ], "instructions": [ [ - "UQADD" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqadd_u8", + "name": "vpaddd_f64", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "float64x2_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQADD" + "FADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddb_s8", + "name": "vpaddd_s64", "arguments": [ - "int8_t a", - "int8_t b" + "int64x2_t a" ], "return_type": { - "value": "int8_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Bn" - }, - "b": { - "register": "Bm" + "register": "Vn.2D" } }, "Architectures": [ @@ -64907,26 +260243,22 @@ ], "instructions": [ [ - "SQADD" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddb_u8", + "name": "vpaddd_u64", "arguments": [ - "uint8_t a", - "uint8_t b" + "uint64x2_t a" ], "return_type": { - "value": "uint8_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Bn" - }, - "b": { - "register": "Bm" + "register": "Vn.2D" } }, "Architectures": [ @@ -64934,134 +260266,122 @@ ], "instructions": [ [ - "UQADD" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddd_s64", + "name": "vpaddl_s16", "arguments": [ - "int64_t a", - "int64_t b" + "int16x4_t a" ], "return_type": { - "value": "int64_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "b": { - "register": "Dm" + "register": "Vn.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQADD" + "SADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddd_u64", + "name": "vpaddl_s32", "arguments": [ - "uint64_t a", - "uint64_t b" + "int32x2_t a" ], "return_type": { - "value": "uint64_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "b": { - "register": "Dm" + "register": "Vn.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQADD" + "SADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddh_s16", + "name": "vpaddl_s8", "arguments": [ - "int16_t a", - "int16_t b" + "int8x8_t a" ], "return_type": { - "value": "int16_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" - }, - "b": { - "register": "Hm" + "register": "Vn.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQADD" + "SADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddh_u16", + "name": "vpaddl_u16", "arguments": [ - "uint16_t a", - "uint16_t b" + "uint16x4_t a" ], "return_type": { - "value": "uint16_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" - }, - "b": { - "register": "Hm" + "register": "Vn.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQADD" + "UADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddq_s16", + "name": "vpaddl_u32", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "uint32x2_t a" ], "return_type": { - "value": "int16x8_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Vn.2S" } }, "Architectures": [ @@ -65071,26 +260391,22 @@ ], "instructions": [ [ - "SQADD" + "UADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddq_s32", + "name": "vpaddl_u8", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "uint8x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Vn.8B" } }, "Architectures": [ @@ -65100,26 +260416,22 @@ ], "instructions": [ [ - "SQADD" + "UADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddq_s64", + "name": "vpaddlq_s16", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "int16x8_t a" ], "return_type": { - "value": "int64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "register": "Vn.8H" } }, "Architectures": [ @@ -65129,26 +260441,22 @@ ], "instructions": [ [ - "SQADD" + "SADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddq_s8", + "name": "vpaddlq_s32", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "int32x4_t a" ], "return_type": { - "value": "int8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "register": "Vn.4S" } }, "Architectures": [ @@ -65158,26 +260466,22 @@ ], "instructions": [ [ - "SQADD" + "SADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddq_u16", + "name": "vpaddlq_s8", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "int8x16_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Vn.16B" } }, "Architectures": [ @@ -65187,26 +260491,22 @@ ], "instructions": [ [ - "UQADD" + "SADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddq_u32", + "name": "vpaddlq_u16", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "uint16x8_t a" ], "return_type": { "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Vn.8H" } }, "Architectures": [ @@ -65216,26 +260516,22 @@ ], "instructions": [ [ - "UQADD" + "UADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddq_u64", + "name": "vpaddlq_u32", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "uint32x4_t a" ], "return_type": { "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "register": "Vn.4S" } }, "Architectures": [ @@ -65245,26 +260541,22 @@ ], "instructions": [ [ - "UQADD" + "UADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddq_u8", + "name": "vpaddlq_u8", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "uint8x16_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" } }, "Architectures": [ @@ -65274,26 +260566,26 @@ ], "instructions": [ [ - "UQADD" + "UADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqadds_s32", + "name": "vpaddq_f16", "arguments": [ - "int32_t a", - "int32_t b" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "int32_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vn.8H" }, "b": { - "register": "Sm" + "register": "Vm.8H" } }, "Architectures": [ @@ -65301,26 +260593,26 @@ ], "instructions": [ [ - "SQADD" + "FADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqadds_u32", + "name": "vpaddq_f32", "arguments": [ - "uint32_t a", - "uint32_t b" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "uint32_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vn.4S" }, "b": { - "register": "Sm" + "register": "Vm.4S" } }, "Architectures": [ @@ -65328,35 +260620,26 @@ ], "instructions": [ [ - "UQADD" + "FADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_high_lane_s16", + "name": "vpaddq_f64", "arguments": [ - "int32x4_t a", - "int16x8_t b", - "int16x4_t v", - "const int lane" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "int32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.2D" }, "b": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "register": "Vm.2D" } }, "Architectures": [ @@ -65364,35 +260647,26 @@ ], "instructions": [ [ - "SQDMLAL2" + "FADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_high_lane_s32", + "name": "vpaddq_s16", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32x2_t v", - "const int lane" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.8H" }, "b": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Vm.8H" } }, "Architectures": [ @@ -65400,35 +260674,26 @@ ], "instructions": [ [ - "SQDMLAL2" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_high_laneq_s16", + "name": "vpaddq_s32", "arguments": [ "int32x4_t a", - "int16x8_t b", - "int16x8_t v", - "const int lane" + "int32x4_t b" ], "return_type": { "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.4S" }, "b": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vm.4S" } }, "Architectures": [ @@ -65436,35 +260701,26 @@ ], "instructions": [ [ - "SQDMLAL2" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_high_laneq_s32", + "name": "vpaddq_s64", "arguments": [ "int64x2_t a", - "int32x4_t b", - "int32x4_t v", - "const int lane" + "int64x2_t b" ], "return_type": { "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.2D" }, "b": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vm.2D" } }, "Architectures": [ @@ -65472,30 +260728,26 @@ ], "instructions": [ [ - "SQDMLAL2" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_high_n_s16", + "name": "vpaddq_s8", "arguments": [ - "int32x4_t a", - "int16x8_t b", - "int16_t c" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.16B" }, "b": { - "register": "Vn.8H" - }, - "c": { - "register": "Vm.H[0]" + "register": "Vm.16B" } }, "Architectures": [ @@ -65503,30 +260755,26 @@ ], "instructions": [ [ - "SQDMLAL2" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_high_n_s32", + "name": "vpaddq_u16", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32_t c" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.8H" }, "b": { - "register": "Vn.4S" - }, - "c": { - "register": "Vm.S[0]" + "register": "Vm.8H" } }, "Architectures": [ @@ -65534,30 +260782,26 @@ ], "instructions": [ [ - "SQDMLAL2" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_high_s16", + "name": "vpaddq_u32", "arguments": [ - "int32x4_t a", - "int16x8_t b", - "int16x8_t c" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.4S" }, "b": { - "register": "Vn.8H" - }, - "c": { - "register": "Vm.8H" + "register": "Vm.4S" } }, "Architectures": [ @@ -65565,30 +260809,26 @@ ], "instructions": [ [ - "SQDMLAL2" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_high_s32", + "name": "vpaddq_u64", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32x4_t c" + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.2D" }, "b": { - "register": "Vn.4S" - }, - "c": { - "register": "Vm.4S" + "register": "Vm.2D" } }, "Architectures": [ @@ -65596,178 +260836,133 @@ ], "instructions": [ [ - "SQDMLAL2" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_lane_s16", + "name": "vpaddq_u8", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16x4_t v", - "const int lane" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.16B" }, "b": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "register": "Vm.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMLAL" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_lane_s32", + "name": "vpadds_f32", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32x2_t v", - "const int lane" + "float32x2_t a" ], "return_type": { - "value": "int64x2_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMLAL" + "FADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_laneq_s16", + "name": "vpmax_f16", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16x8_t v", - "const int lane" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.4H" }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "b": { + "register": "Vm.4H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "SQDMLAL" + "FMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_laneq_s32", + "name": "vpmax_f32", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32x4_t v", - "const int lane" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "int64x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { "register": "Vn.2S" }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "b": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMLAL" + "FMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_n_s16", + "name": "vpmax_s16", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16_t c" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.4H" }, - "c": { - "register": "Vm.H[0]" + "b": { + "register": "Vm.4H" } }, "Architectures": [ @@ -65777,30 +260972,26 @@ ], "instructions": [ [ - "SQDMLAL" + "SMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_n_s32", + "name": "vpmax_s32", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32_t c" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { "register": "Vn.2S" }, - "c": { - "register": "Vm.S[0]" + "b": { + "register": "Vm.2S" } }, "Architectures": [ @@ -65810,30 +261001,26 @@ ], "instructions": [ [ - "SQDMLAL" + "SMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_s16", + "name": "vpmax_s8", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16x4_t c" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.8B" }, "b": { - "register": "Vn.4H" - }, - "c": { - "register": "Vm.4H" + "register": "Vm.8B" } }, "Architectures": [ @@ -65843,30 +261030,26 @@ ], "instructions": [ [ - "SQDMLAL" + "SMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_s32", + "name": "vpmax_u16", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32x2_t c" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.4H" }, "b": { - "register": "Vn.2S" - }, - "c": { - "register": "Vm.2S" + "register": "Vm.4H" } }, "Architectures": [ @@ -65876,102 +261059,84 @@ ], "instructions": [ [ - "SQDMLAL" + "UMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlalh_lane_s16", + "name": "vpmax_u32", "arguments": [ - "int32_t a", - "int16_t b", - "int16x4_t v", - "const int lane" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "int32_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" + "register": "Vn.2S" }, "b": { - "register": "Hn" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMLAL" + "UMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlalh_laneq_s16", + "name": "vpmax_u8", "arguments": [ - "int32_t a", - "int16_t b", - "int16x8_t v", - "const int lane" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "int32_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" + "register": "Vn.8B" }, "b": { - "register": "Hn" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMLAL" + "UMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlalh_s16", + "name": "vpmaxnm_f16", "arguments": [ - "int32_t a", - "int16_t b", - "int16_t c" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "int32_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" + "register": "Vn.4H" }, "b": { - "register": "Hn" - }, - "c": { - "register": "Hm" + "register": "Vm.4H" } }, "Architectures": [ @@ -65979,34 +261144,25 @@ ], "instructions": [ [ - "SQDMLAL" + "FMAXNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlals_lane_s32", + "name": "vpmaxnm_f32", "arguments": [ - "int64_t a", - "int32_t b", - "int32x2_t v", - "const int lane" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "int64_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.2S" }, "b": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { "register": "Vm.2S" } }, @@ -66015,35 +261171,26 @@ ], "instructions": [ [ - "SQDMLAL" + "FMAXNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlals_laneq_s32", + "name": "vpmaxnmq_f16", "arguments": [ - "int64_t a", - "int32_t b", - "int32x4_t v", - "const int lane" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "int64_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.8H" }, "b": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vm.8H" } }, "Architectures": [ @@ -66051,30 +261198,26 @@ ], "instructions": [ [ - "SQDMLAL" + "FMAXNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlals_s32", + "name": "vpmaxnmq_f32", "arguments": [ - "int64_t a", - "int32_t b", - "int32_t c" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "int64_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.4S" }, "b": { - "register": "Sn" - }, - "c": { - "register": "Sm" + "register": "Vm.4S" } }, "Architectures": [ @@ -66082,35 +261225,26 @@ ], "instructions": [ [ - "SQDMLAL" + "FMAXNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_high_lane_s16", + "name": "vpmaxnmq_f64", "arguments": [ - "int32x4_t a", - "int16x8_t b", - "int16x4_t v", - "const int lane" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "int32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.2D" }, "b": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "register": "Vm.2D" } }, "Architectures": [ @@ -66118,35 +261252,22 @@ ], "instructions": [ [ - "SQDMLSL2" + "FMAXNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_high_lane_s32", + "name": "vpmaxnmqd_f64", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32x2_t v", - "const int lane" + "float64x2_t a" ], "return_type": { - "value": "int64x2_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Vn.2D" } }, "Architectures": [ @@ -66154,35 +261275,22 @@ ], "instructions": [ [ - "SQDMLSL2" + "FMAXNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_high_laneq_s16", + "name": "vpmaxnms_f32", "arguments": [ - "int32x4_t a", - "int16x8_t b", - "int16x8_t v", - "const int lane" + "float32x2_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vn.2S" } }, "Architectures": [ @@ -66190,35 +261298,26 @@ ], "instructions": [ [ - "SQDMLSL2" + "FMAXNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_high_laneq_s32", + "name": "vpmaxq_f16", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32x4_t v", - "const int lane" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "int64x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.8H" }, "b": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vm.8H" } }, "Architectures": [ @@ -66226,30 +261325,26 @@ ], "instructions": [ [ - "SQDMLSL2" + "FMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_high_n_s16", + "name": "vpmaxq_f32", "arguments": [ - "int32x4_t a", - "int16x8_t b", - "int16_t c" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.4S" }, "b": { - "register": "Vn.8H" - }, - "c": { - "register": "Vm.H[0]" + "register": "Vm.4S" } }, "Architectures": [ @@ -66257,30 +261352,26 @@ ], "instructions": [ [ - "SQDMLSL2" + "FMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_high_n_s32", + "name": "vpmaxq_f64", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32_t c" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "int64x2_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.2D" }, "b": { - "register": "Vn.4S" - }, - "c": { - "register": "Vm.S[0]" + "register": "Vm.2D" } }, "Architectures": [ @@ -66288,29 +261379,25 @@ ], "instructions": [ [ - "SQDMLSL2" + "FMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_high_s16", + "name": "vpmaxq_s16", "arguments": [ - "int32x4_t a", - "int16x8_t b", - "int16x8_t c" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.8H" }, - "c": { + "b": { "register": "Vm.8H" } }, @@ -66319,29 +261406,25 @@ ], "instructions": [ [ - "SQDMLSL2" + "SMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_high_s32", + "name": "vpmaxq_s32", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32x4_t c" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { "register": "Vn.4S" }, - "c": { + "b": { "register": "Vm.4S" } }, @@ -66350,111 +261433,80 @@ ], "instructions": [ [ - "SQDMLSL2" + "SMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_lane_s16", + "name": "vpmaxq_s8", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16x4_t v", - "const int lane" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.16B" }, "b": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "register": "Vm.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMLSL" + "SMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_lane_s32", + "name": "vpmaxq_u16", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32x2_t v", - "const int lane" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.8H" }, "b": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMLSL" + "UMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_laneq_s16", + "name": "vpmaxq_u32", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16x8_t v", - "const int lane" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.4S" }, "b": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vm.4S" } }, "Architectures": [ @@ -66462,35 +261514,26 @@ ], "instructions": [ [ - "SQDMLSL" + "UMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_laneq_s32", + "name": "vpmaxq_u8", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32x4_t v", - "const int lane" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.16B" }, "b": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vm.16B" } }, "Architectures": [ @@ -66498,128 +261541,99 @@ ], "instructions": [ [ - "SQDMLSL" + "UMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_n_s16", + "name": "vpmaxqd_f64", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16_t c" + "float64x2_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4H" - }, - "c": { - "register": "Vm.H[0]" + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMLSL" + "FMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_n_s32", + "name": "vpmaxs_f32", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32_t c" + "float32x2_t a" ], "return_type": { - "value": "int64x2_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { "register": "Vn.2S" - }, - "c": { - "register": "Vm.S[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMLSL" + "FMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_s16", + "name": "vpmin_f16", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16x4_t c" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.4H" }, - "c": { + "b": { "register": "Vm.4H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SQDMLSL" + "FMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_s32", + "name": "vpmin_f32", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32x2_t c" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "int64x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { "register": "Vn.2S" }, - "c": { + "b": { "register": "Vm.2S" } }, @@ -66630,304 +261644,253 @@ ], "instructions": [ [ - "SQDMLSL" + "FMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlslh_lane_s16", + "name": "vpmin_s16", "arguments": [ - "int32_t a", - "int16_t b", - "int16x4_t v", - "const int lane" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "int32_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" + "register": "Vn.4H" }, "b": { - "register": "Hn" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMLSL" + "SMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlslh_laneq_s16", + "name": "vpmin_s32", "arguments": [ - "int32_t a", - "int16_t b", - "int16x8_t v", - "const int lane" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "int32_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" + "register": "Vn.2S" }, "b": { - "register": "Hn" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMLSL" + "SMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlslh_s16", + "name": "vpmin_s8", "arguments": [ - "int32_t a", - "int16_t b", - "int16_t c" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "int32_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" + "register": "Vn.8B" }, "b": { - "register": "Hn" - }, - "c": { - "register": "Hm" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMLSL" + "SMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsls_lane_s32", + "name": "vpmin_u16", "arguments": [ - "int64_t a", - "int32_t b", - "int32x2_t v", - "const int lane" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "int64_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.4H" }, "b": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMLSL" + "UMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsls_laneq_s32", + "name": "vpmin_u32", "arguments": [ - "int64_t a", - "int32_t b", - "int32x4_t v", - "const int lane" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "int64_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.2S" }, "b": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMLSL" + "UMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsls_s32", + "name": "vpmin_u8", "arguments": [ - "int64_t a", - "int32_t b", - "int32_t c" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "int64_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.8B" }, "b": { - "register": "Sn" - }, - "c": { - "register": "Sm" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMLSL" + "UMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulh_lane_s16", + "name": "vpminnm_f16", "arguments": [ - "int16x4_t a", - "int16x4_t v", - "const int lane" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "int16x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4H" }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { + "b": { "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMULH" + "FMINNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulh_lane_s32", + "name": "vpminnm_f32", "arguments": [ - "int32x2_t a", - "int32x2_t v", - "const int lane" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "int32x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2S" }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { + "b": { "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMULH" + "FMINNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulh_laneq_s16", + "name": "vpminnmq_f16", "arguments": [ - "int16x4_t a", - "int16x8_t v", - "const int lane" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "int16x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 7 + "register": "Vn.8H" }, - "v": { + "b": { "register": "Vm.8H" } }, @@ -66936,30 +261899,25 @@ ], "instructions": [ [ - "SQDMULH" + "FMINNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulh_laneq_s32", + "name": "vpminnmq_f32", "arguments": [ - "int32x2_t a", - "int32x4_t v", - "const int lane" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "int32x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Vn.4S" }, - "v": { + "b": { "register": "Vm.4S" } }, @@ -66968,147 +261926,126 @@ ], "instructions": [ [ - "SQDMULH" + "FMINNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulh_n_s16", + "name": "vpminnmq_f64", "arguments": [ - "int16x4_t a", - "int16_t b" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "int16x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.2D" }, "b": { - "register": "Vm.H[0]" + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMULH" + "FMINNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulh_n_s32", + "name": "vpminnmqd_f64", "arguments": [ - "int32x2_t a", - "int32_t b" + "float64x2_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.S[0]" + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMULH" + "FMINNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulh_s16", + "name": "vpminnms_f32", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "float32x2_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "register": "Vn.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMULH" + "FMINNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulh_s32", + "name": "vpminq_f16", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "int32x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.8H" }, "b": { - "register": "Vm.2S" + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMULH" + "FMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhh_lane_s16", + "name": "vpminq_f32", "arguments": [ - "int16_t a", - "int16x4_t v", - "const int lane" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "int16_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Vn.4S" }, - "v": { - "register": "Vm.4H" + "b": { + "register": "Vm.4S" } }, "Architectures": [ @@ -67116,31 +262053,26 @@ ], "instructions": [ [ - "SQDMULH" + "FMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhh_laneq_s16", + "name": "vpminq_f64", "arguments": [ - "int16_t a", - "int16x8_t v", - "const int lane" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "int16_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" - }, - "lane": { - "minimum": 0, - "maximum": 7 + "register": "Vn.2D" }, - "v": { - "register": "Vm.8H" + "b": { + "register": "Vm.2D" } }, "Architectures": [ @@ -67148,26 +262080,26 @@ ], "instructions": [ [ - "SQDMULH" + "FMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhh_s16", + "name": "vpminq_s16", "arguments": [ - "int16_t a", - "int16_t b" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "int16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vn.8H" }, "b": { - "register": "Hm" + "register": "Vm.8H" } }, "Architectures": [ @@ -67175,98 +262107,79 @@ ], "instructions": [ [ - "SQDMULH" + "SMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhq_lane_s16", + "name": "vpminq_s32", "arguments": [ - "int16x8_t a", - "int16x4_t v", - "const int lane" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Vn.4S" }, - "v": { - "register": "Vm.4H" + "b": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMULH" + "SMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhq_lane_s32", + "name": "vpminq_s8", "arguments": [ - "int32x4_t a", - "int32x2_t v", - "const int lane" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 1 + "register": "Vn.16B" }, - "v": { - "register": "Vm.2S" + "b": { + "register": "Vm.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMULH" + "SMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhq_laneq_s16", + "name": "vpminq_u16", "arguments": [ - "int16x8_t a", - "int16x8_t v", - "const int lane" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int16x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { + "b": { "register": "Vm.8H" } }, @@ -67275,30 +262188,25 @@ ], "instructions": [ [ - "SQDMULH" + "UMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhq_laneq_s32", + "name": "vpminq_u32", "arguments": [ - "int32x4_t a", - "int32x4_t v", - "const int lane" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { + "b": { "register": "Vm.4S" } }, @@ -67307,113 +262215,95 @@ ], "instructions": [ [ - "SQDMULH" + "UMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhq_n_s16", + "name": "vpminq_u8", "arguments": [ - "int16x8_t a", - "int16_t b" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "int16x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { - "register": "Vm.H[0]" + "register": "Vm.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMULH" + "UMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhq_n_s32", + "name": "vpminqd_f64", "arguments": [ - "int32x4_t a", - "int32_t b" + "float64x2_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.S[0]" + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMULH" + "FMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhq_s16", + "name": "vpmins_f32", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "float32x2_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Vn.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMULH" + "FMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhq_s32", + "name": "vqabs_s16", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int16x4_t a" ], "return_type": { - "value": "int32x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Vn.4H" } }, "Architectures": [ @@ -67423,63 +262313,47 @@ ], "instructions": [ [ - "SQDMULH" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhs_lane_s32", + "name": "vqabs_s32", "arguments": [ - "int32_t a", - "int32x2_t v", - "const int lane" + "int32x2_t a" ], "return_type": { - "value": "int32_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Vn.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMULH" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhs_laneq_s32", + "name": "vqabs_s64", "arguments": [ - "int32_t a", - "int32x4_t v", - "const int lane" + "int64x1_t a" ], "return_type": { - "value": "int32_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Dn" } }, "Architectures": [ @@ -67487,58 +262361,47 @@ ], "instructions": [ [ - "SQDMULH" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhs_s32", + "name": "vqabs_s8", "arguments": [ - "int32_t a", - "int32_t b" + "int8x8_t a" ], "return_type": { - "value": "int32_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" - }, - "b": { - "register": "Sm" + "register": "Vn.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMULH" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_high_lane_s16", + "name": "vqabsb_s8", "arguments": [ - "int16x8_t a", - "int16x4_t v", - "const int lane" + "int8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "int8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "register": "Bn" } }, "Architectures": [ @@ -67546,31 +262409,22 @@ ], "instructions": [ [ - "SQDMULL2" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_high_lane_s32", + "name": "vqabsd_s64", "arguments": [ - "int32x4_t a", - "int32x2_t v", - "const int lane" + "int64_t a" ], "return_type": { - "value": "int64x2_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Dn" } }, "Architectures": [ @@ -67578,31 +262432,22 @@ ], "instructions": [ [ - "SQDMULL2" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_high_laneq_s16", + "name": "vqabsh_s16", "arguments": [ - "int16x8_t a", - "int16x8_t v", - "const int lane" + "int16_t a" ], "return_type": { - "value": "int32x4_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Hn" } }, "Architectures": [ @@ -67610,85 +262455,72 @@ ], "instructions": [ [ - "SQDMULL2" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_high_laneq_s32", + "name": "vqabsq_s16", "arguments": [ - "int32x4_t a", - "int32x4_t v", - "const int lane" + "int16x8_t a" ], "return_type": { - "value": "int64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vn.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMULL2" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_high_n_s16", + "name": "vqabsq_s32", "arguments": [ - "int16x8_t a", - "int16_t b" + "int32x4_t a" ], "return_type": { "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.H[0]" + "register": "Vn.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMULL2" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_high_n_s32", + "name": "vqabsq_s64", "arguments": [ - "int32x4_t a", - "int32_t b" + "int64x2_t a" ], "return_type": { "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.S[0]" + "register": "Vn.2D" } }, "Architectures": [ @@ -67696,53 +262528,47 @@ ], "instructions": [ [ - "SQDMULL2" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_high_s16", + "name": "vqabsq_s8", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int8x16_t a" ], "return_type": { - "value": "int32x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Vn.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMULL2" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_high_s32", + "name": "vqabss_s32", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int32_t a" ], "return_type": { - "value": "int64x2_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Sn" } }, "Architectures": [ @@ -67750,30 +262576,25 @@ ], "instructions": [ [ - "SQDMULL2" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_lane_s16", + "name": "vqadd_s16", "arguments": [ "int16x4_t a", - "int16x4_t v", - "const int lane" + "int16x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4H" }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { + "b": { "register": "Vm.4H" } }, @@ -67784,30 +262605,25 @@ ], "instructions": [ [ - "SQDMULL" + "SQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_lane_s32", + "name": "vqadd_s32", "arguments": [ "int32x2_t a", - "int32x2_t v", - "const int lane" + "int32x2_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2S" }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { + "b": { "register": "Vm.2S" } }, @@ -67818,90 +262634,84 @@ ], "instructions": [ [ - "SQDMULL" + "SQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_laneq_s16", + "name": "vqadd_s64", "arguments": [ - "int16x4_t a", - "int16x8_t v", - "const int lane" + "int64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 7 + "register": "Dn" }, - "v": { - "register": "Vm.8H" + "b": { + "register": "Dm" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMULL" + "SQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_laneq_s32", + "name": "vqadd_s8", "arguments": [ - "int32x2_t a", - "int32x4_t v", - "const int lane" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Vn.8B" }, - "v": { - "register": "Vm.4S" + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMULL" + "SQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_n_s16", + "name": "vqadd_u16", "arguments": [ - "int16x4_t a", - "int16_t b" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4H" }, "b": { - "register": "Vm.H[0]" + "register": "Vm.4H" } }, "Architectures": [ @@ -67911,26 +262721,26 @@ ], "instructions": [ [ - "SQDMULL" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_n_s32", + "name": "vqadd_u32", "arguments": [ - "int32x2_t a", - "int32_t b" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2S" }, "b": { - "register": "Vm.S[0]" + "register": "Vm.2S" } }, "Architectures": [ @@ -67940,26 +262750,26 @@ ], "instructions": [ [ - "SQDMULL" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_s16", + "name": "vqadd_u64", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "uint64x1_t a", + "uint64x1_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Dn" }, "b": { - "register": "Vm.4H" + "register": "Dm" } }, "Architectures": [ @@ -67969,26 +262779,26 @@ ], "instructions": [ [ - "SQDMULL" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_s32", + "name": "vqadd_u8", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.8B" }, "b": { - "register": "Vm.2S" + "register": "Vm.8B" } }, "Architectures": [ @@ -67998,31 +262808,26 @@ ], "instructions": [ [ - "SQDMULL" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmullh_lane_s16", + "name": "vqaddb_s8", "arguments": [ - "int16_t a", - "int16x4_t v", - "const int lane" + "int8_t a", + "int8_t b" ], "return_type": { - "value": "int32_t" + "value": "int8_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Bn" }, - "v": { - "register": "Vm.4H" + "b": { + "register": "Bm" } }, "Architectures": [ @@ -68030,31 +262835,26 @@ ], "instructions": [ [ - "SQDMULL" + "SQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmullh_laneq_s16", + "name": "vqaddb_u8", "arguments": [ - "int16_t a", - "int16x8_t v", - "const int lane" + "uint8_t a", + "uint8_t b" ], "return_type": { - "value": "int32_t" + "value": "uint8_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" - }, - "lane": { - "minimum": 0, - "maximum": 7 + "register": "Bn" }, - "v": { - "register": "Vm.8H" + "b": { + "register": "Bm" } }, "Architectures": [ @@ -68062,26 +262862,26 @@ ], "instructions": [ [ - "SQDMULL" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmullh_s16", + "name": "vqaddd_s64", "arguments": [ - "int16_t a", - "int16_t b" + "int64_t a", + "int64_t b" ], "return_type": { - "value": "int32_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Dn" }, "b": { - "register": "Hm" + "register": "Dm" } }, "Architectures": [ @@ -68089,31 +262889,26 @@ ], "instructions": [ [ - "SQDMULL" + "SQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulls_lane_s32", + "name": "vqaddd_u64", "arguments": [ - "int32_t a", - "int32x2_t v", - "const int lane" + "uint64_t a", + "uint64_t b" ], "return_type": { - "value": "int64_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 1 + "register": "Dn" }, - "v": { - "register": "Vm.2S" + "b": { + "register": "Dm" } }, "Architectures": [ @@ -68121,31 +262916,26 @@ ], "instructions": [ [ - "SQDMULL" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulls_laneq_s32", + "name": "vqaddh_s16", "arguments": [ - "int32_t a", - "int32x4_t v", - "const int lane" + "int16_t a", + "int16_t b" ], "return_type": { - "value": "int64_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Hn" }, - "v": { - "register": "Vm.4S" + "b": { + "register": "Hm" } }, "Architectures": [ @@ -68153,26 +262943,26 @@ ], "instructions": [ [ - "SQDMULL" + "SQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulls_s32", + "name": "vqaddh_u16", "arguments": [ - "int32_t a", - "int32_t b" + "uint16_t a", + "uint16_t b" ], "return_type": { - "value": "int64_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Hn" }, "b": { - "register": "Sm" + "register": "Hm" } }, "Architectures": [ @@ -68180,184 +262970,229 @@ ], "instructions": [ [ - "SQDMULL" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_high_s16", + "name": "vqaddq_s16", "arguments": [ - "int8x8_t r", - "int16x8_t a" + "int16x8_t a", + "int16x8_t b" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqaddq_s32", + "arguments": [ + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "int8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4S" }, - "r": { - "register": "Vd.8B" + "b": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQXTN2" + "SQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_high_s32", + "name": "vqaddq_s64", "arguments": [ - "int16x4_t r", - "int32x4_t a" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2D" }, - "r": { - "register": "Vd.4H" + "b": { + "register": "Vm.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQXTN2" + "SQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_high_s64", + "name": "vqaddq_s8", "arguments": [ - "int32x2_t r", - "int64x2_t a" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.16B" }, - "r": { - "register": "Vd.2S" + "b": { + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQXTN2" + "SQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_high_u16", + "name": "vqaddq_u16", "arguments": [ - "uint8x8_t r", - "uint16x8_t a" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" }, - "r": { - "register": "Vd.8B" + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQXTN2" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_high_u32", + "name": "vqaddq_u32", "arguments": [ - "uint16x4_t r", - "uint32x4_t a" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" }, - "r": { - "register": "Vd.4H" + "b": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQXTN2" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_high_u64", + "name": "vqaddq_u64", "arguments": [ - "uint32x2_t r", - "uint64x2_t a" + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2D" }, - "r": { - "register": "Vd.2S" + "b": { + "register": "Vm.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQXTN2" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_s16", + "name": "vqaddq_u8", "arguments": [ - "int16x8_t a" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "int8x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" } }, "Architectures": [ @@ -68367,147 +263202,197 @@ ], "instructions": [ [ - "SQXTN" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_s32", + "name": "vqadds_s32", "arguments": [ - "int32x4_t a" + "int32_t a", + "int32_t b" ], "return_type": { - "value": "int16x4_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Sn" + }, + "b": { + "register": "Sm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQXTN" + "SQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_s64", + "name": "vqadds_u32", "arguments": [ - "int64x2_t a" + "uint32_t a", + "uint32_t b" ], "return_type": { - "value": "int32x2_t" + "value": "uint32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Sn" + }, + "b": { + "register": "Sm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQXTN" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_u16", + "name": "vqdmlal_high_lane_s16", "arguments": [ - "uint16x8_t a" + "int32x4_t a", + "int16x8_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.4S" + }, + "b": { "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQXTN" + "SQDMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_u32", + "name": "vqdmlal_high_lane_s32", "arguments": [ - "uint32x4_t a" + "int64x2_t a", + "int32x4_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.2D" + }, + "b": { "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQXTN" + "SQDMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_u64", + "name": "vqdmlal_high_laneq_s16", "arguments": [ - "uint64x2_t a" + "int32x4_t a", + "int16x8_t b", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQXTN" + "SQDMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovnd_s64", + "name": "vqdmlal_high_laneq_s32", "arguments": [ - "int64_t a" + "int64x2_t a", + "int32x4_t b", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "int32_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ @@ -68515,22 +263400,30 @@ ], "instructions": [ [ - "SQXTN" + "SQDMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovnd_u64", + "name": "vqdmlal_high_n_s16", "arguments": [ - "uint64_t a" + "int32x4_t a", + "int16x8_t b", + "int16_t c" ], "return_type": { - "value": "uint32_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "c": { + "register": "Vm.H[0]" } }, "Architectures": [ @@ -68538,22 +263431,30 @@ ], "instructions": [ [ - "UQXTN" + "SQDMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovnh_s16", + "name": "vqdmlal_high_n_s32", "arguments": [ - "int16_t a" + "int64x2_t a", + "int32x4_t b", + "int32_t c" ], "return_type": { - "value": "int8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.S[0]" } }, "Architectures": [ @@ -68561,22 +263462,30 @@ ], "instructions": [ [ - "SQXTN" + "SQDMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovnh_u16", + "name": "vqdmlal_high_s16", "arguments": [ - "uint16_t a" + "int32x4_t a", + "int16x8_t b", + "int16x8_t c" ], "return_type": { - "value": "uint8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "c": { + "register": "Vm.8H" } }, "Architectures": [ @@ -68584,22 +263493,30 @@ ], "instructions": [ [ - "UQXTN" + "SQDMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovns_s32", + "name": "vqdmlal_high_s32", "arguments": [ - "int32_t a" + "int64x2_t a", + "int32x4_t b", + "int32x4_t c" ], "return_type": { - "value": "int16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" } }, "Architectures": [ @@ -68607,76 +263524,111 @@ ], "instructions": [ [ - "SQXTN" + "SQDMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovns_u32", + "name": "vqdmlal_lane_s16", "arguments": [ - "uint32_t a" + "int32x4_t a", + "int16x4_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "uint16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQXTN" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovun_high_s16", + "name": "vqdmlal_lane_s32", "arguments": [ - "uint8x8_t r", - "int16x8_t a" + "int64x2_t a", + "int32x2_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "uint8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.2D" }, - "r": { - "register": "Vd.8B" + "b": { + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQXTUN2" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovun_high_s32", + "name": "vqdmlal_laneq_s16", "arguments": [ - "uint16x4_t r", - "int32x4_t a" + "int32x4_t a", + "int16x4_t b", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.4S" }, - "r": { - "register": "Vd.4H" + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ @@ -68684,26 +263636,35 @@ ], "instructions": [ [ - "SQXTUN2" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovun_high_s64", + "name": "vqdmlal_laneq_s32", "arguments": [ - "uint32x2_t r", - "int64x2_t a" + "int64x2_t a", + "int32x2_t b", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.2D" }, - "r": { - "register": "Vd.2S" + "b": { + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ @@ -68711,22 +263672,30 @@ ], "instructions": [ [ - "SQXTUN2" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovun_s16", + "name": "vqdmlal_n_s16", "arguments": [ - "int16x8_t a" + "int32x4_t a", + "int16x4_t b", + "int16_t c" ], "return_type": { - "value": "uint8x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.4H" + }, + "c": { + "register": "Vm.H[0]" } }, "Architectures": [ @@ -68736,22 +263705,30 @@ ], "instructions": [ [ - "SQXTUN" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovun_s32", + "name": "vqdmlal_n_s32", "arguments": [ - "int32x4_t a" + "int64x2_t a", + "int32x2_t b", + "int32_t c" ], "return_type": { - "value": "uint16x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.2S" + }, + "c": { + "register": "Vm.S[0]" } }, "Architectures": [ @@ -68761,22 +263738,30 @@ ], "instructions": [ [ - "SQXTUN" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovun_s64", + "name": "vqdmlal_s16", "arguments": [ - "int64x2_t a" + "int32x4_t a", + "int16x4_t b", + "int16x4_t c" ], "return_type": { - "value": "uint32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.4H" + }, + "c": { + "register": "Vm.4H" } }, "Architectures": [ @@ -68786,45 +263771,68 @@ ], "instructions": [ [ - "SQXTUN" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovund_s64", + "name": "vqdmlal_s32", "arguments": [ - "int64_t a" + "int64x2_t a", + "int32x2_t b", + "int32x2_t c" ], "return_type": { - "value": "uint32_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.2S" + }, + "c": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQXTUN" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovunh_s16", + "name": "vqdmlalh_lane_s16", "arguments": [ - "int16_t a" + "int32_t a", + "int16_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "uint8_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { + "register": "Sd" + }, + "b": { "register": "Hn" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -68832,22 +263840,35 @@ ], "instructions": [ [ - "SQXTUN" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovuns_s32", + "name": "vqdmlalh_laneq_s16", "arguments": [ - "int32_t a" + "int32_t a", + "int16_t b", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "uint16_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Sd" + }, + "b": { + "register": "Hn" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ @@ -68855,72 +263876,102 @@ ], "instructions": [ [ - "SQXTUN" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqneg_s16", + "name": "vqdmlalh_s16", "arguments": [ - "int16x4_t a" + "int32_t a", + "int16_t b", + "int16_t c" ], "return_type": { - "value": "int16x4_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Sd" + }, + "b": { + "register": "Hn" + }, + "c": { + "register": "Hm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQNEG" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqneg_s32", + "name": "vqdmlals_lane_s32", "arguments": [ - "int32x2_t a" + "int64_t a", + "int32_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Dd" + }, + "b": { + "register": "Sn" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQNEG" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqneg_s64", + "name": "vqdmlals_laneq_s32", "arguments": [ - "int64x1_t a" + "int64_t a", + "int32_t b", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "int64x1_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Dd" + }, + "b": { + "register": "Sn" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ @@ -68928,47 +263979,66 @@ ], "instructions": [ [ - "SQNEG" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqneg_s8", + "name": "vqdmlals_s32", "arguments": [ - "int8x8_t a" + "int64_t a", + "int32_t b", + "int32_t c" ], "return_type": { - "value": "int8x8_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Dd" + }, + "b": { + "register": "Sn" + }, + "c": { + "register": "Sm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQNEG" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqnegb_s8", + "name": "vqdmlsl_high_lane_s16", "arguments": [ - "int8_t a" + "int32x4_t a", + "int16x8_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "int8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Bn" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -68976,22 +264046,35 @@ ], "instructions": [ [ - "SQNEG" + "SQDMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqnegd_s64", + "name": "vqdmlsl_high_lane_s32", "arguments": [ - "int64_t a" + "int64x2_t a", + "int32x4_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "int64_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -68999,22 +264082,35 @@ ], "instructions": [ [ - "SQNEG" + "SQDMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqnegh_s16", + "name": "vqdmlsl_high_laneq_s16", "arguments": [ - "int16_t a" + "int32x4_t a", + "int16x8_t b", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "int16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ @@ -69022,72 +264118,97 @@ ], "instructions": [ [ - "SQNEG" + "SQDMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqnegq_s16", + "name": "vqdmlsl_high_laneq_s32", "arguments": [ - "int16x8_t a" + "int64x2_t a", + "int32x4_t b", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQNEG" + "SQDMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqnegq_s32", + "name": "vqdmlsl_high_n_s16", "arguments": [ - "int32x4_t a" + "int32x4_t a", + "int16x8_t b", + "int16_t c" ], "return_type": { "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "c": { + "register": "Vm.H[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQNEG" + "SQDMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqnegq_s64", + "name": "vqdmlsl_high_n_s32", "arguments": [ - "int64x2_t a" + "int64x2_t a", + "int32x4_t b", + "int32_t c" ], "return_type": { "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.S[0]" } }, "Architectures": [ @@ -69095,47 +264216,61 @@ ], "instructions": [ [ - "SQNEG" + "SQDMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqnegq_s8", + "name": "vqdmlsl_high_s16", "arguments": [ - "int8x16_t a" + "int32x4_t a", + "int16x8_t b", + "int16x8_t c" ], "return_type": { - "value": "int8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "c": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQNEG" + "SQDMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqnegs_s32", + "name": "vqdmlsl_high_s32", "arguments": [ - "int32_t a" + "int64x2_t a", + "int32x4_t b", + "int32x4_t c" ], "return_type": { - "value": "int32_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" } }, "Architectures": [ @@ -69143,25 +264278,25 @@ ], "instructions": [ [ - "SQNEG" + "SQDMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlah_lane_s16", + "name": "vqdmlsl_lane_s16", "arguments": [ - "int16x4_t a", + "int32x4_t a", "int16x4_t b", "int16x4_t v", "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.4S" }, "b": { "register": "Vn.4H" @@ -69175,29 +264310,31 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLAH" + "SQDMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlah_lane_s32", + "name": "vqdmlsl_lane_s32", "arguments": [ - "int32x2_t a", + "int64x2_t a", "int32x2_t b", "int32x2_t v", "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.2D" }, "b": { "register": "Vn.2S" @@ -69211,29 +264348,31 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLAH" + "SQDMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlah_laneq_s16", + "name": "vqdmlsl_laneq_s16", "arguments": [ - "int16x4_t a", + "int32x4_t a", "int16x4_t b", "int16x8_t v", "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.4S" }, "b": { "register": "Vn.4H" @@ -69251,25 +264390,25 @@ ], "instructions": [ [ - "SQRDMLAH" + "SQDMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlah_laneq_s32", + "name": "vqdmlsl_laneq_s32", "arguments": [ - "int32x2_t a", + "int64x2_t a", "int32x2_t b", "int32x4_t v", "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.2D" }, "b": { "register": "Vn.2S" @@ -69287,24 +264426,90 @@ ], "instructions": [ [ - "SQRDMLAH" + "SQDMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlah_s16", + "name": "vqdmlsl_n_s16", "arguments": [ - "int16x4_t a", + "int32x4_t a", + "int16x4_t b", + "int16_t c" + ], + "return_type": { + "value": "int32x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4S" + }, + "b": { + "register": "Vn.4H" + }, + "c": { + "register": "Vm.H[0]" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQDMLSL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqdmlsl_n_s32", + "arguments": [ + "int64x2_t a", + "int32x2_t b", + "int32_t c" + ], + "return_type": { + "value": "int64x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.2D" + }, + "b": { + "register": "Vn.2S" + }, + "c": { + "register": "Vm.S[0]" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQDMLSL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqdmlsl_s16", + "arguments": [ + "int32x4_t a", "int16x4_t b", "int16x4_t c" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.4S" }, "b": { "register": "Vn.4H" @@ -69314,28 +264519,30 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLAH" + "SQDMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlah_s32", + "name": "vqdmlsl_s32", "arguments": [ - "int32x2_t a", + "int64x2_t a", "int32x2_t b", "int32x2_t c" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.2D" }, "b": { "register": "Vn.2S" @@ -69345,39 +264552,144 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLAH" + "SQDMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahh_lane_s16", + "name": "vqdmlslh_lane_s16", "arguments": [ - "int16_t a", + "int32_t a", "int16_t b", "int16x4_t v", "const int lane" ], "return_type": { - "value": "int16_t" + "value": "int32_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Sd" + }, + "b": { + "register": "Hn" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqdmlslh_laneq_s16", + "arguments": [ + "int32_t a", + "int16_t b", + "int16x8_t v", + "const int lane" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Sd" + }, + "b": { + "register": "Hn" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqdmlslh_s16", + "arguments": [ + "int32_t a", + "int16_t b", + "int16_t c" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Sd" + }, + "b": { + "register": "Hn" + }, + "c": { + "register": "Hm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqdmlsls_lane_s32", + "arguments": [ + "int64_t a", + "int32_t b", + "int32x2_t v", + "const int lane" + ], + "return_type": { + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Hd" + "register": "Dd" }, "b": { - "register": "Hn" + "register": "Sn" }, "lane": { "minimum": 0, - "maximum": 3 + "maximum": 1 }, "v": { - "register": "Vm.4H" + "register": "Vm.2S" } }, "Architectures": [ @@ -69385,35 +264697,35 @@ ], "instructions": [ [ - "SQRDMLAH" + "SQDMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahh_laneq_s16", + "name": "vqdmlsls_laneq_s32", "arguments": [ - "int16_t a", - "int16_t b", - "int16x8_t v", + "int64_t a", + "int32_t b", + "int32x4_t v", "const int lane" ], "return_type": { - "value": "int16_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Hd" + "register": "Dd" }, "b": { - "register": "Hn" + "register": "Sn" }, "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "v": { - "register": "Vm.8H" + "register": "Vm.4S" } }, "Architectures": [ @@ -69421,30 +264733,30 @@ ], "instructions": [ [ - "SQRDMLAH" + "SQDMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahh_s16", + "name": "vqdmlsls_s32", "arguments": [ - "int16_t a", - "int16_t b", - "int16_t c" + "int64_t a", + "int32_t b", + "int32_t c" ], "return_type": { - "value": "int16_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Hd" + "register": "Dd" }, "b": { - "register": "Hn" + "register": "Sn" }, "c": { - "register": "Hm" + "register": "Sm" } }, "Architectures": [ @@ -69452,28 +264764,24 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahq_lane_s16", + "name": "vqdmulh_lane_s16", "arguments": [ - "int16x8_t a", - "int16x8_t b", + "int16x4_t a", "int16x4_t v", "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.8H" + "register": "Vn.4H" }, "lane": { "minimum": 0, @@ -69484,32 +264792,30 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLAH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahq_lane_s32", + "name": "vqdmulh_lane_s32", "arguments": [ - "int32x4_t a", - "int32x4_t b", + "int32x2_t a", "int32x2_t v", "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4S" + "register": "Vn.2S" }, "lane": { "minimum": 0, @@ -69520,31 +264826,29 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLAH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahq_laneq_s16", + "name": "vqdmulh_laneq_s16", "arguments": [ - "int16x8_t a", - "int16x8_t b", + "int16x4_t a", "int16x8_t v", "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { "register": "Vn.4H" }, "lane": { @@ -69560,27 +264864,23 @@ ], "instructions": [ [ - "SQRDMLAH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahq_laneq_s32", + "name": "vqdmulh_laneq_s32", "arguments": [ - "int32x4_t a", - "int32x4_t b", + "int32x2_t a", "int32x4_t v", "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { "register": "Vn.2S" }, "lane": { @@ -69596,97 +264896,147 @@ ], "instructions": [ [ - "SQRDMLAH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahq_s16", + "name": "vqdmulh_n_s16", "arguments": [ - "int16x8_t a", - "int16x8_t b", - "int16x8_t c" + "int16x4_t a", + "int16_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vn.4H" }, "b": { - "register": "Vn.8H" - }, - "c": { - "register": "Vm.8H" + "register": "Vm.H[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLAH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahq_s32", + "name": "vqdmulh_n_s32", "arguments": [ - "int32x4_t a", - "int32x4_t b", - "int32x4_t c" + "int32x2_t a", + "int32_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.2S" }, "b": { - "register": "Vn.4S" + "register": "Vm.S[0]" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQDMULH" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqdmulh_s16", + "arguments": [ + "int16x4_t a", + "int16x4_t b" + ], + "return_type": { + "value": "int16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" }, - "c": { - "register": "Vm.4S" + "b": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLAH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahs_lane_s32", + "name": "vqdmulh_s32", "arguments": [ - "int32_t a", - "int32_t b", - "int32x2_t v", - "const int lane" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "int32_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" + "register": "Vn.2S" }, "b": { - "register": "Sn" + "register": "Vm.2S" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQDMULH" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqdmulhh_lane_s16", + "arguments": [ + "int16_t a", + "int16x4_t v", + "const int lane" + ], + "return_type": { + "value": "int16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" }, "lane": { "minimum": 0, - "maximum": 1 + "maximum": 3 }, "v": { - "register": "Vm.2S" + "register": "Vm.4H" } }, "Architectures": [ @@ -69694,35 +265044,31 @@ ], "instructions": [ [ - "SQRDMLAH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahs_laneq_s32", + "name": "vqdmulhh_laneq_s16", "arguments": [ - "int32_t a", - "int32_t b", - "int32x4_t v", + "int16_t a", + "int16x8_t v", "const int lane" ], "return_type": { - "value": "int32_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" - }, - "b": { - "register": "Sn" + "register": "Hn" }, "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "v": { - "register": "Vm.4S" + "register": "Vm.8H" } }, "Architectures": [ @@ -69730,30 +265076,26 @@ ], "instructions": [ [ - "SQRDMLAH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahs_s32", + "name": "vqdmulhh_s16", "arguments": [ - "int32_t a", - "int32_t b", - "int32_t c" + "int16_t a", + "int16_t b" ], "return_type": { - "value": "int32_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" + "register": "Hn" }, "b": { - "register": "Sn" - }, - "c": { - "register": "Sm" + "register": "Hm" } }, "Architectures": [ @@ -69761,28 +265103,24 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlsh_lane_s16", + "name": "vqdmulhq_lane_s16", "arguments": [ - "int16x4_t a", - "int16x4_t b", + "int16x8_t a", "int16x4_t v", "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" + "register": "Vn.8H" }, "lane": { "minimum": 0, @@ -69793,32 +265131,30 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLSH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlsh_lane_s32", + "name": "vqdmulhq_lane_s32", "arguments": [ - "int32x2_t a", - "int32x2_t b", + "int32x4_t a", "int32x2_t v", "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.2S" + "register": "Vn.4S" }, "lane": { "minimum": 0, @@ -69829,32 +265165,30 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLSH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlsh_laneq_s16", + "name": "vqdmulhq_laneq_s16", "arguments": [ - "int16x4_t a", - "int16x4_t b", + "int16x8_t a", "int16x8_t v", "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" + "register": "Vn.8H" }, "lane": { "minimum": 0, @@ -69869,28 +265203,24 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlsh_laneq_s32", + "name": "vqdmulhq_laneq_s32", "arguments": [ - "int32x2_t a", - "int32x2_t b", + "int32x4_t a", "int32x4_t v", "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.2S" + "register": "Vn.4S" }, "lane": { "minimum": 0, @@ -69905,97 +265235,147 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlsh_s16", + "name": "vqdmulhq_n_s16", "arguments": [ - "int16x4_t a", - "int16x4_t b", - "int16x4_t c" + "int16x8_t a", + "int16_t b" ], "return_type": { - "value": "int16x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.8H" }, "b": { - "register": "Vn.4H" - }, - "c": { - "register": "Vm.4H" + "register": "Vm.H[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLSH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlsh_s32", + "name": "vqdmulhq_n_s32", "arguments": [ - "int32x2_t a", - "int32x2_t b", - "int32x2_t c" + "int32x4_t a", + "int32_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.4S" }, "b": { - "register": "Vn.2S" + "register": "Vm.S[0]" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQDMULH" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqdmulhq_s16", + "arguments": [ + "int16x8_t a", + "int16x8_t b" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" }, - "c": { - "register": "Vm.2S" + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLSH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlshh_lane_s16", + "name": "vqdmulhq_s32", "arguments": [ - "int16_t a", - "int16_t b", - "int16x4_t v", - "const int lane" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "int16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Hd" + "register": "Vn.4S" }, "b": { - "register": "Hn" + "register": "Vm.4S" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQDMULH" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqdmulhs_lane_s32", + "arguments": [ + "int32_t a", + "int32x2_t v", + "const int lane" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Sn" }, "lane": { "minimum": 0, - "maximum": 3 + "maximum": 1 }, "v": { - "register": "Vm.4H" + "register": "Vm.2S" } }, "Architectures": [ @@ -70003,35 +265383,31 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlshh_laneq_s16", + "name": "vqdmulhs_laneq_s32", "arguments": [ - "int16_t a", - "int16_t b", - "int16x8_t v", + "int32_t a", + "int32x4_t v", "const int lane" ], "return_type": { - "value": "int16_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Hd" - }, - "b": { - "register": "Hn" + "register": "Sn" }, "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "v": { - "register": "Vm.8H" + "register": "Vm.4S" } }, "Architectures": [ @@ -70039,30 +265415,26 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlshh_s16", + "name": "vqdmulhs_s32", "arguments": [ - "int16_t a", - "int16_t b", - "int16_t c" + "int32_t a", + "int32_t b" ], "return_type": { - "value": "int16_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Hd" + "register": "Sn" }, "b": { - "register": "Hn" - }, - "c": { - "register": "Hm" + "register": "Sm" } }, "Architectures": [ @@ -70070,27 +265442,23 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlshq_lane_s16", + "name": "vqdmull_high_lane_s16", "arguments": [ "int16x8_t a", - "int16x8_t b", "int16x4_t v", "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { "register": "Vn.8H" }, "lane": { @@ -70106,27 +265474,23 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlshq_lane_s32", + "name": "vqdmull_high_lane_s32", "arguments": [ "int32x4_t a", - "int32x4_t b", "int32x2_t v", "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.4S" }, "lane": { @@ -70142,28 +265506,24 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlshq_laneq_s16", + "name": "vqdmull_high_laneq_s16", "arguments": [ "int16x8_t a", - "int16x8_t b", "int16x8_t v", "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" + "register": "Vn.8H" }, "lane": { "minimum": 0, @@ -70178,28 +265538,24 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlshq_laneq_s32", + "name": "vqdmull_high_laneq_s32", "arguments": [ "int32x4_t a", - "int32x4_t b", "int32x4_t v", "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.2S" + "register": "Vn.4S" }, "lane": { "minimum": 0, @@ -70214,30 +265570,26 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlshq_s16", + "name": "vqdmull_high_n_s16", "arguments": [ "int16x8_t a", - "int16x8_t b", - "int16x8_t c" + "int16_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { "register": "Vn.8H" }, - "c": { - "register": "Vm.8H" + "b": { + "register": "Vm.H[0]" } }, "Architectures": [ @@ -70245,66 +265597,26 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlshq_s32", + "name": "vqdmull_high_n_s32", "arguments": [ "int32x4_t a", - "int32x4_t b", - "int32x4_t c" + "int32_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.4S" }, - "c": { - "register": "Vm.4S" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "SQRDMLSH" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vqrdmlshs_lane_s32", - "arguments": [ - "int32_t a", - "int32_t b", - "int32x2_t v", - "const int lane" - ], - "return_type": { - "value": "int32_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Sd" - }, "b": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Vm.S[0]" } }, "Architectures": [ @@ -70312,35 +265624,26 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlshs_laneq_s32", + "name": "vqdmull_high_s16", "arguments": [ - "int32_t a", - "int32_t b", - "int32x4_t v", - "const int lane" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "int32_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" + "register": "Vn.8H" }, "b": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vm.8H" } }, "Architectures": [ @@ -70348,30 +265651,26 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlshs_s32", + "name": "vqdmull_high_s32", "arguments": [ - "int32_t a", - "int32_t b", - "int32_t c" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "int32_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" + "register": "Vn.4S" }, "b": { - "register": "Sn" - }, - "c": { - "register": "Sm" + "register": "Vm.4S" } }, "Architectures": [ @@ -70379,20 +265678,20 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulh_lane_s16", + "name": "vqdmull_lane_s16", "arguments": [ "int16x4_t a", "int16x4_t v", "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -70413,20 +265712,20 @@ ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulh_lane_s32", + "name": "vqdmull_lane_s32", "arguments": [ "int32x2_t a", "int32x2_t v", "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { @@ -70447,20 +265746,20 @@ ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulh_laneq_s16", + "name": "vqdmull_laneq_s16", "arguments": [ "int16x4_t a", "int16x8_t v", "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -70479,20 +265778,20 @@ ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulh_laneq_s32", + "name": "vqdmull_laneq_s32", "arguments": [ "int32x2_t a", "int32x4_t v", "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { @@ -70511,19 +265810,19 @@ ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulh_n_s16", + "name": "vqdmull_n_s16", "arguments": [ "int16x4_t a", "int16_t b" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -70540,19 +265839,19 @@ ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulh_n_s32", + "name": "vqdmull_n_s32", "arguments": [ "int32x2_t a", "int32_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { @@ -70569,19 +265868,19 @@ ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulh_s16", + "name": "vqdmull_s16", "arguments": [ "int16x4_t a", "int16x4_t b" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -70598,19 +265897,19 @@ ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulh_s32", + "name": "vqdmull_s32", "arguments": [ "int32x2_t a", "int32x2_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { @@ -70627,20 +265926,20 @@ ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhh_lane_s16", + "name": "vqdmullh_lane_s16", "arguments": [ "int16_t a", "int16x4_t v", "const int lane" ], "return_type": { - "value": "int16_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { @@ -70659,20 +265958,20 @@ ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhh_laneq_s16", + "name": "vqdmullh_laneq_s16", "arguments": [ "int16_t a", "int16x8_t v", "const int lane" ], "return_type": { - "value": "int16_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { @@ -70691,19 +265990,19 @@ ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhh_s16", + "name": "vqdmullh_s16", "arguments": [ "int16_t a", "int16_t b" ], "return_type": { - "value": "int16_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { @@ -70718,58 +266017,24 @@ ], "instructions": [ [ - "SQRDMULH" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vqrdmulhq_lane_s16", - "arguments": [ - "int16x8_t a", - "int16x4_t v", - "const int lane" - ], - "return_type": { - "value": "int16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhq_lane_s32", + "name": "vqdmulls_lane_s32", "arguments": [ - "int32x4_t a", + "int32_t a", "int32x2_t v", "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Sn" }, "lane": { "minimum": 0, @@ -70780,37 +266045,35 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhq_laneq_s16", + "name": "vqdmulls_laneq_s32", "arguments": [ - "int16x8_t a", - "int16x8_t v", + "int32_t a", + "int32x4_t v", "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Sn" }, "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "v": { - "register": "Vm.8H" + "register": "Vm.4S" } }, "Architectures": [ @@ -70818,31 +266081,26 @@ ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhq_laneq_s32", + "name": "vqdmulls_s32", "arguments": [ - "int32x4_t a", - "int32x4_t v", - "const int lane" + "int32_t a", + "int32_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Sn" }, - "v": { - "register": "Vm.4S" + "b": { + "register": "Sm" } }, "Architectures": [ @@ -70850,147 +266108,134 @@ ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhq_n_s16", + "name": "vqmovn_high_s16", "arguments": [ - "int16x8_t a", - "int16_t b" + "int8x8_t r", + "int16x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" }, - "b": { - "register": "Vm.H[0]" + "r": { + "register": "Vd.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRDMULH" + "SQXTN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhq_n_s32", + "name": "vqmovn_high_s32", "arguments": [ - "int32x4_t a", - "int32_t b" + "int16x4_t r", + "int32x4_t a" ], "return_type": { - "value": "int32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" }, - "b": { - "register": "Vm.S[0]" + "r": { + "register": "Vd.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRDMULH" + "SQXTN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhq_s16", + "name": "vqmovn_high_s64", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int32x2_t r", + "int64x2_t a" ], "return_type": { - "value": "int16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2D" }, - "b": { - "register": "Vm.8H" + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRDMULH" + "SQXTN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhq_s32", + "name": "vqmovn_high_u16", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "uint8x8_t r", + "uint16x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.8H" }, - "b": { - "register": "Vm.4S" + "r": { + "register": "Vd.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRDMULH" + "UQXTN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhs_lane_s32", + "name": "vqmovn_high_u32", "arguments": [ - "int32_t a", - "int32x2_t v", - "const int lane" + "uint16x4_t r", + "uint32x4_t a" ], "return_type": { - "value": "int32_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 1 + "register": "Vn.4S" }, - "v": { - "register": "Vm.2S" + "r": { + "register": "Vd.4H" } }, "Architectures": [ @@ -70998,31 +266243,26 @@ ], "instructions": [ [ - "SQRDMULH" + "UQXTN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhs_laneq_s32", + "name": "vqmovn_high_u64", "arguments": [ - "int32_t a", - "int32x4_t v", - "const int lane" + "uint32x2_t r", + "uint64x2_t a" ], "return_type": { - "value": "int32_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Vn.2D" }, - "v": { - "register": "Vm.4S" + "r": { + "register": "Vd.2S" } }, "Architectures": [ @@ -71030,53 +266270,47 @@ ], "instructions": [ [ - "SQRDMULH" + "UQXTN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhs_s32", + "name": "vqmovn_s16", "arguments": [ - "int32_t a", - "int32_t b" + "int16x8_t a" ], "return_type": { - "value": "int32_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" - }, - "b": { - "register": "Sm" + "register": "Vn.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMULH" + "SQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshl_s16", + "name": "vqmovn_s32", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "int32x4_t a" ], "return_type": { "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "register": "Vn.4S" } }, "Architectures": [ @@ -71086,26 +266320,22 @@ ], "instructions": [ [ - "SQRSHL" + "SQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshl_s32", + "name": "vqmovn_s64", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "int64x2_t a" ], "return_type": { "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" + "register": "Vn.2D" } }, "Architectures": [ @@ -71115,26 +266345,22 @@ ], "instructions": [ [ - "SQRSHL" + "SQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshl_s64", + "name": "vqmovn_u16", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "uint16x8_t a" ], "return_type": { - "value": "int64x1_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "b": { - "register": "Dm" + "register": "Vn.8H" } }, "Architectures": [ @@ -71144,26 +266370,22 @@ ], "instructions": [ [ - "SQRSHL" + "UQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshl_s8", + "name": "vqmovn_u32", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "uint32x4_t a" ], "return_type": { - "value": "int8x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" + "register": "Vn.4S" } }, "Architectures": [ @@ -71173,26 +266395,22 @@ ], "instructions": [ [ - "SQRSHL" + "UQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshl_u16", + "name": "vqmovn_u64", "arguments": [ - "uint16x4_t a", - "int16x4_t b" + "uint64x2_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "register": "Vn.2D" } }, "Architectures": [ @@ -71202,113 +266420,91 @@ ], "instructions": [ [ - "UQRSHL" + "UQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshl_u32", + "name": "vqmovnd_s64", "arguments": [ - "uint32x2_t a", - "int32x2_t b" + "int64_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQRSHL" + "SQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshl_u64", + "name": "vqmovnd_u64", "arguments": [ - "uint64x1_t a", - "int64x1_t b" + "uint64_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "uint32_t" }, "Arguments_Preparation": { "a": { "register": "Dn" - }, - "b": { - "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQRSHL" + "UQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshl_u8", + "name": "vqmovnh_s16", "arguments": [ - "uint8x8_t a", - "int8x8_t b" + "int16_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" + "register": "Hn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQRSHL" + "SQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlb_s8", + "name": "vqmovnh_u16", "arguments": [ - "int8_t a", - "int8_t b" + "uint16_t a" ], "return_type": { - "value": "int8_t" + "value": "uint8_t" }, "Arguments_Preparation": { "a": { - "register": "Bn" - }, - "b": { - "register": "Bm" + "register": "Hn" } }, "Architectures": [ @@ -71316,26 +266512,22 @@ ], "instructions": [ [ - "SQRSHL" + "UQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlb_u8", + "name": "vqmovns_s32", "arguments": [ - "uint8_t a", - "int8_t b" + "int32_t a" ], "return_type": { - "value": "uint8_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Bn" - }, - "b": { - "register": "Bm" + "register": "Sn" } }, "Architectures": [ @@ -71343,26 +266535,22 @@ ], "instructions": [ [ - "UQRSHL" + "SQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshld_s64", + "name": "vqmovns_u32", "arguments": [ - "int64_t a", - "int64_t b" + "uint32_t a" ], "return_type": { - "value": "int64_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "b": { - "register": "Dm" + "register": "Sn" } }, "Architectures": [ @@ -71370,26 +266558,26 @@ ], "instructions": [ [ - "SQRSHL" + "UQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshld_u64", + "name": "vqmovun_high_s16", "arguments": [ - "uint64_t a", - "int64_t b" + "uint8x8_t r", + "int16x8_t a" ], "return_type": { - "value": "uint64_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.8H" }, - "b": { - "register": "Dm" + "r": { + "register": "Vd.8B" } }, "Architectures": [ @@ -71397,26 +266585,26 @@ ], "instructions": [ [ - "UQRSHL" + "SQXTUN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlh_s16", + "name": "vqmovun_high_s32", "arguments": [ - "int16_t a", - "int16_t b" + "uint16x4_t r", + "int32x4_t a" ], "return_type": { - "value": "int16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vn.4S" }, - "b": { - "register": "Hm" + "r": { + "register": "Vd.4H" } }, "Architectures": [ @@ -71424,26 +266612,26 @@ ], "instructions": [ [ - "SQRSHL" + "SQXTUN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlh_u16", + "name": "vqmovun_high_s64", "arguments": [ - "uint16_t a", - "int16_t b" + "uint32x2_t r", + "int64x2_t a" ], "return_type": { - "value": "uint16_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vn.2D" }, - "b": { - "register": "Hm" + "r": { + "register": "Vd.2S" } }, "Architectures": [ @@ -71451,26 +266639,22 @@ ], "instructions": [ [ - "UQRSHL" + "SQXTUN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlq_s16", + "name": "vqmovun_s16", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int16x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" } }, "Architectures": [ @@ -71480,26 +266664,22 @@ ], "instructions": [ [ - "SQRSHL" + "SQXTUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlq_s32", + "name": "vqmovun_s32", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int32x4_t a" ], "return_type": { - "value": "int32x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" } }, "Architectures": [ @@ -71509,26 +266689,22 @@ ], "instructions": [ [ - "SQRSHL" + "SQXTUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlq_s64", + "name": "vqmovun_s64", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "int64x2_t a" ], "return_type": { - "value": "int64x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" } }, "Architectures": [ @@ -71538,113 +266714,91 @@ ], "instructions": [ [ - "SQRSHL" + "SQXTUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlq_s8", + "name": "vqmovund_s64", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "int64_t a" ], "return_type": { - "value": "int8x16_t" + "value": "uint32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRSHL" + "SQXTUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlq_u16", + "name": "vqmovunh_s16", "arguments": [ - "uint16x8_t a", - "int16x8_t b" + "int16_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "uint8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Hn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQRSHL" + "SQXTUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlq_u32", + "name": "vqmovuns_s32", "arguments": [ - "uint32x4_t a", - "int32x4_t b" + "int32_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Sn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQRSHL" + "SQXTUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlq_u64", + "name": "vqneg_s16", "arguments": [ - "uint64x2_t a", - "int64x2_t b" + "int16x4_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "register": "Vn.4H" } }, "Architectures": [ @@ -71654,26 +266808,22 @@ ], "instructions": [ [ - "UQRSHL" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlq_u8", + "name": "vqneg_s32", "arguments": [ - "uint8x16_t a", - "int8x16_t b" + "int32x2_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "register": "Vn.2S" } }, "Architectures": [ @@ -71683,26 +266833,22 @@ ], "instructions": [ [ - "UQRSHL" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshls_s32", + "name": "vqneg_s64", "arguments": [ - "int32_t a", - "int32_t b" + "int64x1_t a" ], "return_type": { - "value": "int32_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" - }, - "b": { - "register": "Sm" + "register": "Dn" } }, "Architectures": [ @@ -71710,58 +266856,47 @@ ], "instructions": [ [ - "SQRSHL" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshls_u32", + "name": "vqneg_s8", "arguments": [ - "uint32_t a", - "int32_t b" + "int8x8_t a" ], "return_type": { - "value": "uint32_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" - }, - "b": { - "register": "Sm" + "register": "Vn.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQRSHL" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_high_n_s16", + "name": "vqnegb_s8", "arguments": [ - "int8x8_t r", - "int16x8_t a", - "const int n" + "int8_t a" ], "return_type": { - "value": "int8x16_t" + "value": "int8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "n": { - "minimum": 1, - "maximum": 8 - }, - "r": { - "register": "Vd.8B" + "register": "Bn" } }, "Architectures": [ @@ -71769,31 +266904,22 @@ ], "instructions": [ [ - "SQRSHRN2" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_high_n_s32", + "name": "vqnegd_s64", "arguments": [ - "int16x4_t r", - "int32x4_t a", - "const int n" + "int64_t a" ], "return_type": { - "value": "int16x8_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "n": { - "minimum": 1, - "maximum": 16 - }, - "r": { - "register": "Vd.4H" + "register": "Dn" } }, "Architectures": [ @@ -71801,31 +266927,22 @@ ], "instructions": [ [ - "SQRSHRN2" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_high_n_s64", + "name": "vqnegh_s16", "arguments": [ - "int32x2_t r", - "int64x2_t a", - "const int n" + "int16_t a" ], "return_type": { - "value": "int32x4_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "n": { - "minimum": 1, - "maximum": 32 - }, - "r": { - "register": "Vd.2S" + "register": "Hn" } }, "Architectures": [ @@ -71833,95 +266950,72 @@ ], "instructions": [ [ - "SQRSHRN2" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_high_n_u16", + "name": "vqnegq_s16", "arguments": [ - "uint8x8_t r", - "uint16x8_t a", - "const int n" + "int16x8_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" - }, - "n": { - "minimum": 1, - "maximum": 8 - }, - "r": { - "register": "Vd.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQRSHRN2" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_high_n_u32", + "name": "vqnegq_s32", "arguments": [ - "uint16x4_t r", - "uint32x4_t a", - "const int n" + "int32x4_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" - }, - "n": { - "minimum": 1, - "maximum": 16 - }, - "r": { - "register": "Vd.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQRSHRN2" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_high_n_u64", + "name": "vqnegq_s64", "arguments": [ - "uint32x2_t r", - "uint64x2_t a", - "const int n" + "int64x2_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2D" - }, - "n": { - "minimum": 1, - "maximum": 32 - }, - "r": { - "register": "Vd.2S" } }, "Architectures": [ @@ -71929,27 +267023,22 @@ ], "instructions": [ [ - "UQRSHRN2" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_n_s16", + "name": "vqnegq_s8", "arguments": [ - "int16x8_t a", - "const int n" + "int8x16_t a" ], "return_type": { - "value": "int8x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "n": { - "minimum": 1, - "maximum": 8 + "register": "Vn.16B" } }, "Architectures": [ @@ -71959,177 +267048,197 @@ ], "instructions": [ [ - "SQRSHRN" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_n_s32", + "name": "vqnegs_s32", "arguments": [ - "int32x4_t a", - "const int n" + "int32_t a" ], "return_type": { - "value": "int16x4_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "n": { - "minimum": 1, - "maximum": 16 + "register": "Sn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRSHRN" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_n_s64", + "name": "vqrdmlah_lane_s16", "arguments": [ - "int64x2_t a", - "const int n" + "int16x4_t a", + "int16x4_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.4H" }, - "n": { - "minimum": 1, - "maximum": 32 + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRSHRN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_n_u16", + "name": "vqrdmlah_lane_s32", "arguments": [ - "uint16x8_t a", - "const int n" + "int32x2_t a", + "int32x2_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.2S" }, - "n": { - "minimum": 1, - "maximum": 8 + "b": { + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQRSHRN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_n_u32", + "name": "vqrdmlah_laneq_s16", "arguments": [ - "uint32x4_t a", - "const int n" + "int16x4_t a", + "int16x4_t b", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.4H" }, - "n": { - "minimum": 1, - "maximum": 16 + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQRSHRN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_n_u64", + "name": "vqrdmlah_laneq_s32", "arguments": [ - "uint64x2_t a", - "const int n" + "int32x2_t a", + "int32x2_t b", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.2S" }, - "n": { - "minimum": 1, - "maximum": 32 + "b": { + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQRSHRN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrnd_n_s64", + "name": "vqrdmlah_s16", "arguments": [ - "int64_t a", - "const int n" + "int16x4_t a", + "int16x4_t b", + "int16x4_t c" ], "return_type": { - "value": "int32_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.4H" }, - "n": { - "minimum": 1, - "maximum": 32 + "b": { + "register": "Vn.4H" + }, + "c": { + "register": "Vm.4H" } }, "Architectures": [ @@ -72137,27 +267246,30 @@ ], "instructions": [ [ - "SQRSHRN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrnd_n_u64", + "name": "vqrdmlah_s32", "arguments": [ - "uint64_t a", - "const int n" + "int32x2_t a", + "int32x2_t b", + "int32x2_t c" ], "return_type": { - "value": "uint32_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.2S" }, - "n": { - "minimum": 1, - "maximum": 32 + "b": { + "register": "Vn.2S" + }, + "c": { + "register": "Vm.2S" } }, "Architectures": [ @@ -72165,27 +267277,35 @@ ], "instructions": [ [ - "UQRSHRN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrnh_n_s16", + "name": "vqrdmlahh_lane_s16", "arguments": [ "int16_t a", - "const int n" + "int16_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "int8_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { + "register": "Hd" + }, + "b": { "register": "Hn" }, - "n": { - "minimum": 1, - "maximum": 8 + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -72193,27 +267313,35 @@ ], "instructions": [ [ - "SQRSHRN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrnh_n_u16", + "name": "vqrdmlahh_laneq_s16", "arguments": [ - "uint16_t a", - "const int n" + "int16_t a", + "int16_t b", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "uint8_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { + "register": "Hd" + }, + "b": { "register": "Hn" }, - "n": { - "minimum": 1, - "maximum": 8 + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ @@ -72221,27 +267349,30 @@ ], "instructions": [ [ - "UQRSHRN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrns_n_s32", + "name": "vqrdmlahh_s16", "arguments": [ - "int32_t a", - "const int n" + "int16_t a", + "int16_t b", + "int16_t c" ], "return_type": { "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Hd" }, - "n": { - "minimum": 1, - "maximum": 16 + "b": { + "register": "Hn" + }, + "c": { + "register": "Hm" } }, "Architectures": [ @@ -72249,27 +267380,35 @@ ], "instructions": [ [ - "SQRSHRN" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrns_n_u32", + "name": "vqrdmlahq_lane_s16", "arguments": [ - "uint32_t a", - "const int n" + "int16x8_t a", + "int16x8_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "uint16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vd.8H" }, - "n": { - "minimum": 1, - "maximum": 16 + "b": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -72277,31 +267416,35 @@ ], "instructions": [ [ - "UQRSHRN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrun_high_n_s16", + "name": "vqrdmlahq_lane_s32", "arguments": [ - "uint8x8_t r", - "int16x8_t a", - "const int n" + "int32x4_t a", + "int32x4_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "uint8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.4S" }, - "n": { - "minimum": 1, - "maximum": 8 + "b": { + "register": "Vn.4S" }, - "r": { - "register": "Vd.8B" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -72309,31 +267452,35 @@ ], "instructions": [ [ - "SQRSHRUN2" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrun_high_n_s32", + "name": "vqrdmlahq_laneq_s16", "arguments": [ - "uint16x4_t r", - "int32x4_t a", - "const int n" + "int16x8_t a", + "int16x8_t b", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.4H" }, - "n": { - "minimum": 1, - "maximum": 16 + "b": { + "register": "Vn.4H" }, - "r": { - "register": "Vd.4H" + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ @@ -72341,31 +267488,35 @@ ], "instructions": [ [ - "SQRSHRUN2" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrun_high_n_s64", + "name": "vqrdmlahq_laneq_s32", "arguments": [ - "uint32x2_t r", - "int64x2_t a", - "const int n" + "int32x4_t a", + "int32x4_t b", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.2S" }, - "n": { - "minimum": 1, - "maximum": 32 + "b": { + "register": "Vn.2S" }, - "r": { - "register": "Vd.2S" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ @@ -72373,117 +267524,133 @@ ], "instructions": [ [ - "SQRSHRUN2" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrun_n_s16", + "name": "vqrdmlahq_s16", "arguments": [ "int16x8_t a", - "const int n" + "int16x8_t b", + "int16x8_t c" ], "return_type": { - "value": "uint8x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.8H" + }, + "b": { "register": "Vn.8H" }, - "n": { - "minimum": 1, - "maximum": 8 + "c": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRSHRUN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrun_n_s32", + "name": "vqrdmlahq_s32", "arguments": [ "int32x4_t a", - "const int n" + "int32x4_t b", + "int32x4_t c" ], "return_type": { - "value": "uint16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.4S" + }, + "b": { "register": "Vn.4S" }, - "n": { - "minimum": 1, - "maximum": 16 + "c": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRSHRUN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrun_n_s64", + "name": "vqrdmlahs_lane_s32", "arguments": [ - "int64x2_t a", - "const int n" + "int32_t a", + "int32_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Sd" }, - "n": { - "minimum": 1, - "maximum": 32 + "b": { + "register": "Sn" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRSHRUN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrund_n_s64", + "name": "vqrdmlahs_laneq_s32", "arguments": [ - "int64_t a", - "const int n" + "int32_t a", + "int32_t b", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "uint32_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Sd" }, - "n": { - "minimum": 1, - "maximum": 32 + "b": { + "register": "Sn" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ @@ -72491,27 +267658,30 @@ ], "instructions": [ [ - "SQRSHRUN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrunh_n_s16", + "name": "vqrdmlahs_s32", "arguments": [ - "int16_t a", - "const int n" + "int32_t a", + "int32_t b", + "int32_t c" ], "return_type": { - "value": "uint8_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Sd" }, - "n": { - "minimum": 1, - "maximum": 8 + "b": { + "register": "Sn" + }, + "c": { + "register": "Sm" } }, "Architectures": [ @@ -72519,27 +267689,35 @@ ], "instructions": [ [ - "SQRSHRUN" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshruns_n_s32", + "name": "vqrdmlsh_lane_s16", "arguments": [ - "int32_t a", - "const int n" + "int16x4_t a", + "int16x4_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "uint16_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vd.4H" }, - "n": { - "minimum": 1, - "maximum": 16 + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -72547,469 +267725,613 @@ ], "instructions": [ [ - "SQRSHRUN" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_n_s16", + "name": "vqrdmlsh_lane_s32", + "arguments": [ + "int32x2_t a", + "int32x2_t b", + "int32x2_t v", + "const int lane" + ], + "return_type": { + "value": "int32x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.2S" + }, + "b": { + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLSH" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqrdmlsh_laneq_s16", "arguments": [ "int16x4_t a", - "const int n" + "int16x4_t b", + "int16x8_t v", + "const int lane" ], "return_type": { "value": "int16x4_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.4H" + }, + "b": { "register": "Vn.4H" }, - "n": { + "lane": { "minimum": 0, - "maximum": 15 + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_n_s32", + "name": "vqrdmlsh_laneq_s32", "arguments": [ "int32x2_t a", - "const int n" + "int32x2_t b", + "int32x4_t v", + "const int lane" ], "return_type": { "value": "int32x2_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.2S" + }, + "b": { "register": "Vn.2S" }, - "n": { + "lane": { "minimum": 0, - "maximum": 31 + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_n_s64", + "name": "vqrdmlsh_s16", "arguments": [ - "int64x1_t a", - "const int n" + "int16x4_t a", + "int16x4_t b", + "int16x4_t c" ], "return_type": { - "value": "int64x1_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.4H" }, - "n": { - "minimum": 0, - "maximum": 63 + "b": { + "register": "Vn.4H" + }, + "c": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_n_s8", + "name": "vqrdmlsh_s32", "arguments": [ - "int8x8_t a", - "const int n" + "int32x2_t a", + "int32x2_t b", + "int32x2_t c" ], "return_type": { - "value": "int8x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vd.2S" }, - "n": { + "b": { + "register": "Vn.2S" + }, + "c": { + "register": "Vm.2S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLSH" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqrdmlshh_lane_s16", + "arguments": [ + "int16_t a", + "int16_t b", + "int16x4_t v", + "const int lane" + ], + "return_type": { + "value": "int16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hd" + }, + "b": { + "register": "Hn" + }, + "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_n_u16", + "name": "vqrdmlshh_laneq_s16", "arguments": [ - "uint16x4_t a", - "const int n" + "int16_t a", + "int16_t b", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Hd" }, - "n": { + "b": { + "register": "Hn" + }, + "lane": { "minimum": 0, - "maximum": 15 + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_n_u32", + "name": "vqrdmlshh_s16", "arguments": [ - "uint32x2_t a", - "const int n" + "int16_t a", + "int16_t b", + "int16_t c" ], "return_type": { - "value": "uint32x2_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Hd" + }, + "b": { + "register": "Hn" }, - "n": { - "minimum": 0, - "maximum": 31 + "c": { + "register": "Hm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_n_u64", + "name": "vqrdmlshq_lane_s16", "arguments": [ - "uint64x1_t a", - "const int n" + "int16x8_t a", + "int16x8_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "uint64x1_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.8H" }, - "n": { + "b": { + "register": "Vn.8H" + }, + "lane": { "minimum": 0, - "maximum": 63 + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_n_u8", + "name": "vqrdmlshq_lane_s32", "arguments": [ - "uint8x8_t a", - "const int n" + "int32x4_t a", + "int32x4_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vd.4S" }, - "n": { + "b": { + "register": "Vn.4S" + }, + "lane": { "minimum": 0, - "maximum": 7 + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_s16", + "name": "vqrdmlshq_laneq_s16", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "int16x8_t a", + "int16x8_t b", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.4H" }, "b": { - "register": "Vm.4H" + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_s32", + "name": "vqrdmlshq_laneq_s32", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "int32x4_t a", + "int32x4_t b", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.2S" }, "b": { - "register": "Vm.2S" + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_s64", + "name": "vqrdmlshq_s16", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "int16x8_t a", + "int16x8_t b", + "int16x8_t c" ], "return_type": { - "value": "int64x1_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.8H" }, "b": { - "register": "Dm" + "register": "Vn.8H" + }, + "c": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_s8", + "name": "vqrdmlshq_s32", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "int32x4_t a", + "int32x4_t b", + "int32x4_t c" ], "return_type": { - "value": "int8x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vd.4S" }, "b": { - "register": "Vm.8B" + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_u16", + "name": "vqrdmlshs_lane_s32", "arguments": [ - "uint16x4_t a", - "int16x4_t b" + "int32_t a", + "int32_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Sd" }, "b": { - "register": "Vm.4H" + "register": "Sn" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_u32", + "name": "vqrdmlshs_laneq_s32", "arguments": [ - "uint32x2_t a", - "int32x2_t b" + "int32_t a", + "int32_t b", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Sd" }, "b": { - "register": "Vm.2S" + "register": "Sn" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_u64", + "name": "vqrdmlshs_s32", "arguments": [ - "uint64x1_t a", - "int64x1_t b" + "int32_t a", + "int32_t b", + "int32_t c" ], "return_type": { - "value": "uint64x1_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Sd" }, "b": { - "register": "Dm" + "register": "Sn" + }, + "c": { + "register": "Sm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_u8", + "name": "vqrdmulh_lane_s16", "arguments": [ - "uint8x8_t a", - "int8x8_t b" + "int16x4_t a", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4H" }, - "b": { - "register": "Vm.8B" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -73019,55 +268341,65 @@ ], "instructions": [ [ - "UQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlb_n_s8", + "name": "vqrdmulh_lane_s32", "arguments": [ - "int8_t a", - "const int n" + "int32x2_t a", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "int8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Bn" + "register": "Vn.2S" }, - "n": { + "lane": { "minimum": 0, - "maximum": 7 + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlb_n_u8", + "name": "vqrdmulh_laneq_s16", "arguments": [ - "uint8_t a", - "const int n" + "int16x4_t a", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "uint8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Bn" + "register": "Vn.4H" }, - "n": { + "lane": { "minimum": 0, "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ @@ -73075,26 +268407,31 @@ ], "instructions": [ [ - "UQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlb_s8", + "name": "vqrdmulh_laneq_s32", "arguments": [ - "int8_t a", - "int8_t b" + "int32x2_t a", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "int8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Bn" + "register": "Vn.2S" }, - "b": { - "register": "Bm" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ @@ -73102,136 +268439,147 @@ ], "instructions": [ [ - "SQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlb_u8", + "name": "vqrdmulh_n_s16", "arguments": [ - "uint8_t a", - "int8_t b" + "int16x4_t a", + "int16_t b" ], "return_type": { - "value": "uint8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Bn" + "register": "Vn.4H" }, "b": { - "register": "Bm" + "register": "Vm.H[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshld_n_s64", + "name": "vqrdmulh_n_s32", "arguments": [ - "int64_t a", - "const int n" + "int32x2_t a", + "int32_t b" ], "return_type": { - "value": "int64_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.2S" }, - "n": { - "minimum": 0, - "maximum": 63 + "b": { + "register": "Vm.S[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshld_n_u64", + "name": "vqrdmulh_s16", "arguments": [ - "uint64_t a", - "const int n" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "uint64_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.4H" }, - "n": { - "minimum": 0, - "maximum": 63 + "b": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshld_s64", + "name": "vqrdmulh_s32", "arguments": [ - "int64_t a", - "int64_t b" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "int64_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.2S" }, "b": { - "register": "Dm" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshld_u64", + "name": "vqrdmulhh_lane_s16", "arguments": [ - "uint64_t a", - "int64_t b" + "int16_t a", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "uint64_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Hn" }, - "b": { - "register": "Dm" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -73239,16 +268587,17 @@ ], "instructions": [ [ - "UQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlh_n_s16", + "name": "vqrdmulhh_laneq_s16", "arguments": [ "int16_t a", - "const int n" + "int16x8_t v", + "const int lane" ], "return_type": { "value": "int16_t" @@ -73257,9 +268606,12 @@ "a": { "register": "Hn" }, - "n": { + "lane": { "minimum": 0, - "maximum": 15 + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ @@ -73267,27 +268619,26 @@ ], "instructions": [ [ - "SQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlh_n_u16", + "name": "vqrdmulhh_s16", "arguments": [ - "uint16_t a", - "const int n" + "int16_t a", + "int16_t b" ], "return_type": { - "value": "uint16_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { "register": "Hn" }, - "n": { - "minimum": 0, - "maximum": 15 + "b": { + "register": "Hm" } }, "Architectures": [ @@ -73295,70 +268646,85 @@ ], "instructions": [ [ - "UQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlh_s16", + "name": "vqrdmulhq_lane_s16", "arguments": [ - "int16_t a", - "int16_t b" + "int16x8_t a", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "int16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vn.8H" }, - "b": { - "register": "Hm" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlh_u16", + "name": "vqrdmulhq_lane_s32", "arguments": [ - "uint16_t a", - "int16_t b" + "int32x4_t a", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "uint16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vn.4S" }, - "b": { - "register": "Hm" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_n_s16", + "name": "vqrdmulhq_laneq_s16", "arguments": [ "int16x8_t a", - "const int n" + "int16x8_t v", + "const int lane" ], "return_type": { "value": "int16x8_t" @@ -73367,28 +268733,30 @@ "a": { "register": "Vn.8H" }, - "n": { + "lane": { "minimum": 0, - "maximum": 15 + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_n_s32", + "name": "vqrdmulhq_laneq_s32", "arguments": [ "int32x4_t a", - "const int n" + "int32x4_t v", + "const int lane" ], "return_type": { "value": "int32x4_t" @@ -73397,39 +268765,39 @@ "a": { "register": "Vn.4S" }, - "n": { + "lane": { "minimum": 0, - "maximum": 31 + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_n_s64", + "name": "vqrdmulhq_n_s16", "arguments": [ - "int64x2_t a", - "const int n" + "int16x8_t a", + "int16_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.8H" }, - "n": { - "minimum": 0, - "maximum": 63 + "b": { + "register": "Vm.H[0]" } }, "Architectures": [ @@ -73439,27 +268807,26 @@ ], "instructions": [ [ - "SQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_n_s8", + "name": "vqrdmulhq_n_s32", "arguments": [ - "int8x16_t a", - "const int n" + "int32x4_t a", + "int32_t b" ], "return_type": { - "value": "int8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" }, - "n": { - "minimum": 0, - "maximum": 7 + "b": { + "register": "Vm.S[0]" } }, "Architectures": [ @@ -73469,27 +268836,26 @@ ], "instructions": [ [ - "SQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_n_u16", + "name": "vqrdmulhq_s16", "arguments": [ - "uint16x8_t a", - "const int n" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" }, - "n": { - "minimum": 0, - "maximum": 15 + "b": { + "register": "Vm.8H" } }, "Architectures": [ @@ -73499,27 +268865,26 @@ ], "instructions": [ [ - "UQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_n_u32", + "name": "vqrdmulhq_s32", "arguments": [ - "uint32x4_t a", - "const int n" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" }, - "n": { - "minimum": 0, - "maximum": 31 + "b": { + "register": "Vm.4S" } }, "Architectures": [ @@ -73529,115 +268894,117 @@ ], "instructions": [ [ - "UQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_n_u64", + "name": "vqrdmulhs_lane_s32", "arguments": [ - "uint64x2_t a", - "const int n" + "int32_t a", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "uint64x2_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Sn" }, - "n": { + "lane": { "minimum": 0, - "maximum": 63 + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_n_u8", + "name": "vqrdmulhs_laneq_s32", "arguments": [ - "uint8x16_t a", - "const int n" + "int32_t a", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "uint8x16_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Sn" }, - "n": { + "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_s16", + "name": "vqrdmulhs_s32", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int32_t a", + "int32_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Sn" }, "b": { - "register": "Vm.8H" + "register": "Sm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_s32", + "name": "vqrshl_s16", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.4H" }, "b": { - "register": "Vm.4S" + "register": "Vm.4H" } }, "Architectures": [ @@ -73647,26 +269014,26 @@ ], "instructions": [ [ - "SQSHL" + "SQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_s64", + "name": "vqrshl_s32", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.2S" }, "b": { - "register": "Vm.2D" + "register": "Vm.2S" } }, "Architectures": [ @@ -73676,26 +269043,26 @@ ], "instructions": [ [ - "SQSHL" + "SQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_s8", + "name": "vqrshl_s64", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "int64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "int8x16_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Dn" }, "b": { - "register": "Vm.16B" + "register": "Dm" } }, "Architectures": [ @@ -73705,26 +269072,26 @@ ], "instructions": [ [ - "SQSHL" + "SQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_u16", + "name": "vqrshl_s8", "arguments": [ - "uint16x8_t a", - "int16x8_t b" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" }, "b": { - "register": "Vm.8H" + "register": "Vm.8B" } }, "Architectures": [ @@ -73734,26 +269101,26 @@ ], "instructions": [ [ - "UQSHL" + "SQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_u32", + "name": "vqrshl_u16", "arguments": [ - "uint32x4_t a", - "int32x4_t b" + "uint16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.4H" }, "b": { - "register": "Vm.4S" + "register": "Vm.4H" } }, "Architectures": [ @@ -73763,26 +269130,26 @@ ], "instructions": [ [ - "UQSHL" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_u64", + "name": "vqrshl_u32", "arguments": [ - "uint64x2_t a", - "int64x2_t b" + "uint32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.2S" }, "b": { - "register": "Vm.2D" + "register": "Vm.2S" } }, "Architectures": [ @@ -73792,26 +269159,26 @@ ], "instructions": [ [ - "UQSHL" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_u8", + "name": "vqrshl_u64", "arguments": [ - "uint8x16_t a", - "int8x16_t b" + "uint64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Dn" }, "b": { - "register": "Vm.16B" + "register": "Dm" } }, "Architectures": [ @@ -73821,55 +269188,55 @@ ], "instructions": [ [ - "UQSHL" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshls_n_s32", + "name": "vqrshl_u8", "arguments": [ - "int32_t a", - "const int n" + "uint8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "int32_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vn.8B" }, - "n": { - "minimum": 0, - "maximum": 31 + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQSHL" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshls_n_u32", + "name": "vqrshlb_s8", "arguments": [ - "uint32_t a", - "const int n" + "int8_t a", + "int8_t b" ], "return_type": { - "value": "uint32_t" + "value": "int8_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Bn" }, - "n": { - "minimum": 0, - "maximum": 31 + "b": { + "register": "Bm" } }, "Architectures": [ @@ -73877,26 +269244,26 @@ ], "instructions": [ [ - "UQSHL" + "SQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshls_s32", + "name": "vqrshlb_u8", "arguments": [ - "int32_t a", - "int32_t b" + "uint8_t a", + "int8_t b" ], "return_type": { - "value": "int32_t" + "value": "uint8_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Bn" }, "b": { - "register": "Sm" + "register": "Bm" } }, "Architectures": [ @@ -73904,26 +269271,26 @@ ], "instructions": [ [ - "SQSHL" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshls_u32", + "name": "vqrshld_s64", "arguments": [ - "uint32_t a", - "int32_t b" + "int64_t a", + "int64_t b" ], "return_type": { - "value": "uint32_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Dn" }, "b": { - "register": "Sm" + "register": "Dm" } }, "Architectures": [ @@ -73931,117 +269298,107 @@ ], "instructions": [ [ - "UQSHL" + "SQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlu_n_s16", + "name": "vqrshld_u64", "arguments": [ - "int16x4_t a", - "const int n" + "uint64_t a", + "int64_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Dn" }, - "n": { - "minimum": 0, - "maximum": 15 + "b": { + "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHLU" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlu_n_s32", + "name": "vqrshlh_s16", "arguments": [ - "int32x2_t a", - "const int n" + "int16_t a", + "int16_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Hn" }, - "n": { - "minimum": 0, - "maximum": 31 + "b": { + "register": "Hm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHLU" + "SQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlu_n_s64", + "name": "vqrshlh_u16", "arguments": [ - "int64x1_t a", - "const int n" + "uint16_t a", + "int16_t b" ], "return_type": { - "value": "uint64x1_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Hn" }, - "n": { - "minimum": 0, - "maximum": 63 + "b": { + "register": "Hm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHLU" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlu_n_s8", + "name": "vqrshlq_s16", "arguments": [ - "int8x8_t a", - "const int n" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" }, - "n": { - "minimum": 0, - "maximum": 7 + "b": { + "register": "Vm.8H" } }, "Architectures": [ @@ -74051,100 +269408,103 @@ ], "instructions": [ [ - "SQSHLU" + "SQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlub_n_s8", + "name": "vqrshlq_s32", "arguments": [ - "int8_t a", - "const int n" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "uint8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Bn" + "register": "Vn.4S" }, - "n": { - "minimum": 0, - "maximum": 7 + "b": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQSHLU" + "SQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlud_n_s64", + "name": "vqrshlq_s64", "arguments": [ - "int64_t a", - "const int n" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "uint64_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.2D" }, - "n": { - "minimum": 0, - "maximum": 63 + "b": { + "register": "Vm.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQSHLU" + "SQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshluh_n_s16", + "name": "vqrshlq_s8", "arguments": [ - "int16_t a", - "const int n" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "uint16_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vn.16B" }, - "n": { - "minimum": 0, - "maximum": 15 + "b": { + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQSHLU" + "SQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshluq_n_s16", + "name": "vqrshlq_u16", "arguments": [ - "int16x8_t a", - "const int n" + "uint16x8_t a", + "int16x8_t b" ], "return_type": { "value": "uint16x8_t" @@ -74153,9 +269513,8 @@ "a": { "register": "Vn.8H" }, - "n": { - "minimum": 0, - "maximum": 15 + "b": { + "register": "Vm.8H" } }, "Architectures": [ @@ -74165,16 +269524,16 @@ ], "instructions": [ [ - "SQSHLU" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshluq_n_s32", + "name": "vqrshlq_u32", "arguments": [ - "int32x4_t a", - "const int n" + "uint32x4_t a", + "int32x4_t b" ], "return_type": { "value": "uint32x4_t" @@ -74183,9 +269542,8 @@ "a": { "register": "Vn.4S" }, - "n": { - "minimum": 0, - "maximum": 31 + "b": { + "register": "Vm.4S" } }, "Architectures": [ @@ -74195,16 +269553,16 @@ ], "instructions": [ [ - "SQSHLU" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshluq_n_s64", + "name": "vqrshlq_u64", "arguments": [ - "int64x2_t a", - "const int n" + "uint64x2_t a", + "int64x2_t b" ], "return_type": { "value": "uint64x2_t" @@ -74213,9 +269571,8 @@ "a": { "register": "Vn.2D" }, - "n": { - "minimum": 0, - "maximum": 63 + "b": { + "register": "Vm.2D" } }, "Architectures": [ @@ -74225,16 +269582,16 @@ ], "instructions": [ [ - "SQSHLU" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshluq_n_s8", + "name": "vqrshlq_u8", "arguments": [ - "int8x16_t a", - "const int n" + "uint8x16_t a", + "int8x16_t b" ], "return_type": { "value": "uint8x16_t" @@ -74243,9 +269600,8 @@ "a": { "register": "Vn.16B" }, - "n": { - "minimum": 0, - "maximum": 7 + "b": { + "register": "Vm.16B" } }, "Architectures": [ @@ -74255,16 +269611,43 @@ ], "instructions": [ [ - "SQSHLU" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlus_n_s32", + "name": "vqrshls_s32", "arguments": [ "int32_t a", - "const int n" + "int32_t b" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Sn" + }, + "b": { + "register": "Sm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqrshls_u32", + "arguments": [ + "uint32_t a", + "int32_t b" ], "return_type": { "value": "uint32_t" @@ -74273,9 +269656,8 @@ "a": { "register": "Sn" }, - "n": { - "minimum": 0, - "maximum": 31 + "b": { + "register": "Sm" } }, "Architectures": [ @@ -74283,13 +269665,13 @@ ], "instructions": [ [ - "SQSHLU" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_high_n_s16", + "name": "vqrshrn_high_n_s16", "arguments": [ "int8x8_t r", "int16x8_t a", @@ -74315,13 +269697,13 @@ ], "instructions": [ [ - "SQSHRN2" + "SQRSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_high_n_s32", + "name": "vqrshrn_high_n_s32", "arguments": [ "int16x4_t r", "int32x4_t a", @@ -74347,13 +269729,13 @@ ], "instructions": [ [ - "SQSHRN2" + "SQRSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_high_n_s64", + "name": "vqrshrn_high_n_s64", "arguments": [ "int32x2_t r", "int64x2_t a", @@ -74379,13 +269761,13 @@ ], "instructions": [ [ - "SQSHRN2" + "SQRSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_high_n_u16", + "name": "vqrshrn_high_n_u16", "arguments": [ "uint8x8_t r", "uint16x8_t a", @@ -74411,13 +269793,13 @@ ], "instructions": [ [ - "UQSHRN2" + "UQRSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_high_n_u32", + "name": "vqrshrn_high_n_u32", "arguments": [ "uint16x4_t r", "uint32x4_t a", @@ -74443,13 +269825,13 @@ ], "instructions": [ [ - "UQSHRN2" + "UQRSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_high_n_u64", + "name": "vqrshrn_high_n_u64", "arguments": [ "uint32x2_t r", "uint64x2_t a", @@ -74475,13 +269857,13 @@ ], "instructions": [ [ - "UQSHRN2" + "UQRSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_n_s16", + "name": "vqrshrn_n_s16", "arguments": [ "int16x8_t a", "const int n" @@ -74505,13 +269887,13 @@ ], "instructions": [ [ - "SQSHRN" + "SQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_n_s32", + "name": "vqrshrn_n_s32", "arguments": [ "int32x4_t a", "const int n" @@ -74535,13 +269917,13 @@ ], "instructions": [ [ - "SQSHRN" + "SQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_n_s64", + "name": "vqrshrn_n_s64", "arguments": [ "int64x2_t a", "const int n" @@ -74565,13 +269947,13 @@ ], "instructions": [ [ - "SQSHRN" + "SQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_n_u16", + "name": "vqrshrn_n_u16", "arguments": [ "uint16x8_t a", "const int n" @@ -74595,13 +269977,13 @@ ], "instructions": [ [ - "UQSHRN" + "UQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_n_u32", + "name": "vqrshrn_n_u32", "arguments": [ "uint32x4_t a", "const int n" @@ -74625,13 +270007,13 @@ ], "instructions": [ [ - "UQSHRN" + "UQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_n_u64", + "name": "vqrshrn_n_u64", "arguments": [ "uint64x2_t a", "const int n" @@ -74655,13 +270037,13 @@ ], "instructions": [ [ - "UQSHRN" + "UQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrnd_n_s64", + "name": "vqrshrnd_n_s64", "arguments": [ "int64_t a", "const int n" @@ -74683,13 +270065,13 @@ ], "instructions": [ [ - "SQSHRN" + "SQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrnd_n_u64", + "name": "vqrshrnd_n_u64", "arguments": [ "uint64_t a", "const int n" @@ -74711,13 +270093,13 @@ ], "instructions": [ [ - "UQSHRN" + "UQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrnh_n_s16", + "name": "vqrshrnh_n_s16", "arguments": [ "int16_t a", "const int n" @@ -74739,13 +270121,13 @@ ], "instructions": [ [ - "SQSHRN" + "SQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrnh_n_u16", + "name": "vqrshrnh_n_u16", "arguments": [ "uint16_t a", "const int n" @@ -74767,13 +270149,13 @@ ], "instructions": [ [ - "UQSHRN" + "UQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrns_n_s32", + "name": "vqrshrns_n_s32", "arguments": [ "int32_t a", "const int n" @@ -74795,13 +270177,13 @@ ], "instructions": [ [ - "SQSHRN" + "SQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrns_n_u32", + "name": "vqrshrns_n_u32", "arguments": [ "uint32_t a", "const int n" @@ -74823,13 +270205,13 @@ ], "instructions": [ [ - "UQSHRN" + "UQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrun_high_n_s16", + "name": "vqrshrun_high_n_s16", "arguments": [ "uint8x8_t r", "int16x8_t a", @@ -74855,13 +270237,13 @@ ], "instructions": [ [ - "SQSHRUN2" + "SQRSHRUN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrun_high_n_s32", + "name": "vqrshrun_high_n_s32", "arguments": [ "uint16x4_t r", "int32x4_t a", @@ -74887,13 +270269,13 @@ ], "instructions": [ [ - "SQSHRUN2" + "SQRSHRUN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrun_high_n_s64", + "name": "vqrshrun_high_n_s64", "arguments": [ "uint32x2_t r", "int64x2_t a", @@ -74919,13 +270301,13 @@ ], "instructions": [ [ - "SQSHRUN2" + "SQRSHRUN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrun_n_s16", + "name": "vqrshrun_n_s16", "arguments": [ "int16x8_t a", "const int n" @@ -74949,13 +270331,13 @@ ], "instructions": [ [ - "SQSHRUN" + "SQRSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrun_n_s32", + "name": "vqrshrun_n_s32", "arguments": [ "int32x4_t a", "const int n" @@ -74979,13 +270361,13 @@ ], "instructions": [ [ - "SQSHRUN" + "SQRSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrun_n_s64", + "name": "vqrshrun_n_s64", "arguments": [ "int64x2_t a", "const int n" @@ -75009,13 +270391,13 @@ ], "instructions": [ [ - "SQSHRUN" + "SQRSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrund_n_s64", + "name": "vqrshrund_n_s64", "arguments": [ "int64_t a", "const int n" @@ -75037,13 +270419,13 @@ ], "instructions": [ [ - "SQSHRUN" + "SQRSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrunh_n_s16", + "name": "vqrshrunh_n_s16", "arguments": [ "int16_t a", "const int n" @@ -75065,13 +270447,13 @@ ], "instructions": [ [ - "SQSHRUN" + "SQRSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshruns_n_s32", + "name": "vqrshruns_n_s32", "arguments": [ "int32_t a", "const int n" @@ -75093,13 +270475,253 @@ ], "instructions": [ [ - "SQSHRUN" + "SQRSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsub_s16", + "name": "vqshl_n_s16", + "arguments": [ + "int16x4_t a", + "const int n" + ], + "return_type": { + "value": "int16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "n": { + "minimum": 0, + "maximum": 15 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshl_n_s32", + "arguments": [ + "int32x2_t a", + "const int n" + ], + "return_type": { + "value": "int32x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2S" + }, + "n": { + "minimum": 0, + "maximum": 31 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshl_n_s64", + "arguments": [ + "int64x1_t a", + "const int n" + ], + "return_type": { + "value": "int64x1_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Dn" + }, + "n": { + "minimum": 0, + "maximum": 63 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshl_n_s8", + "arguments": [ + "int8x8_t a", + "const int n" + ], + "return_type": { + "value": "int8x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8B" + }, + "n": { + "minimum": 0, + "maximum": 7 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshl_n_u16", + "arguments": [ + "uint16x4_t a", + "const int n" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "n": { + "minimum": 0, + "maximum": 15 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshl_n_u32", + "arguments": [ + "uint32x2_t a", + "const int n" + ], + "return_type": { + "value": "uint32x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2S" + }, + "n": { + "minimum": 0, + "maximum": 31 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshl_n_u64", + "arguments": [ + "uint64x1_t a", + "const int n" + ], + "return_type": { + "value": "uint64x1_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Dn" + }, + "n": { + "minimum": 0, + "maximum": 63 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshl_n_u8", + "arguments": [ + "uint8x8_t a", + "const int n" + ], + "return_type": { + "value": "uint8x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8B" + }, + "n": { + "minimum": 0, + "maximum": 7 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshl_s16", "arguments": [ "int16x4_t a", "int16x4_t b" @@ -75122,13 +270744,13 @@ ], "instructions": [ [ - "SQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsub_s32", + "name": "vqshl_s32", "arguments": [ "int32x2_t a", "int32x2_t b" @@ -75151,13 +270773,13 @@ ], "instructions": [ [ - "SQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsub_s64", + "name": "vqshl_s64", "arguments": [ "int64x1_t a", "int64x1_t b" @@ -75180,13 +270802,13 @@ ], "instructions": [ [ - "SQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsub_s8", + "name": "vqshl_s8", "arguments": [ "int8x8_t a", "int8x8_t b" @@ -75209,16 +270831,16 @@ ], "instructions": [ [ - "SQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsub_u16", + "name": "vqshl_u16", "arguments": [ "uint16x4_t a", - "uint16x4_t b" + "int16x4_t b" ], "return_type": { "value": "uint16x4_t" @@ -75238,16 +270860,16 @@ ], "instructions": [ [ - "UQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsub_u32", + "name": "vqshl_u32", "arguments": [ "uint32x2_t a", - "uint32x2_t b" + "int32x2_t b" ], "return_type": { "value": "uint32x2_t" @@ -75267,16 +270889,16 @@ ], "instructions": [ [ - "UQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsub_u64", + "name": "vqshl_u64", "arguments": [ "uint64x1_t a", - "uint64x1_t b" + "int64x1_t b" ], "return_type": { "value": "uint64x1_t" @@ -75296,16 +270918,16 @@ ], "instructions": [ [ - "UQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsub_u8", + "name": "vqshl_u8", "arguments": [ "uint8x8_t a", - "uint8x8_t b" + "int8x8_t b" ], "return_type": { "value": "uint8x8_t" @@ -75325,13 +270947,69 @@ ], "instructions": [ [ - "UQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubb_s8", + "name": "vqshlb_n_s8", + "arguments": [ + "int8_t a", + "const int n" + ], + "return_type": { + "value": "int8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Bn" + }, + "n": { + "minimum": 0, + "maximum": 7 + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshlb_n_u8", + "arguments": [ + "uint8_t a", + "const int n" + ], + "return_type": { + "value": "uint8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Bn" + }, + "n": { + "minimum": 0, + "maximum": 7 + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshlb_s8", "arguments": [ "int8_t a", "int8_t b" @@ -75352,16 +271030,16 @@ ], "instructions": [ [ - "SQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubb_u8", + "name": "vqshlb_u8", "arguments": [ "uint8_t a", - "uint8_t b" + "int8_t b" ], "return_type": { "value": "uint8_t" @@ -75379,16 +271057,16 @@ ], "instructions": [ [ - "UQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubd_s64", + "name": "vqshld_n_s64", "arguments": [ "int64_t a", - "int64_t b" + "const int n" ], "return_type": { "value": "int64_t" @@ -75397,8 +271075,9 @@ "a": { "register": "Dn" }, - "b": { - "register": "Dm" + "n": { + "minimum": 0, + "maximum": 63 } }, "Architectures": [ @@ -75406,16 +271085,16 @@ ], "instructions": [ [ - "SQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubd_u64", + "name": "vqshld_n_u64", "arguments": [ "uint64_t a", - "uint64_t b" + "const int n" ], "return_type": { "value": "uint64_t" @@ -75424,8 +271103,9 @@ "a": { "register": "Dn" }, - "b": { - "register": "Dm" + "n": { + "minimum": 0, + "maximum": 63 } }, "Architectures": [ @@ -75433,26 +271113,26 @@ ], "instructions": [ [ - "UQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubh_s16", + "name": "vqshld_s64", "arguments": [ - "int16_t a", - "int16_t b" + "int64_t a", + "int64_t b" ], "return_type": { - "value": "int16_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Dn" }, "b": { - "register": "Hm" + "register": "Dm" } }, "Architectures": [ @@ -75460,26 +271140,26 @@ ], "instructions": [ [ - "SQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubh_u16", + "name": "vqshld_u64", "arguments": [ - "uint16_t a", - "uint16_t b" + "uint64_t a", + "int64_t b" ], "return_type": { - "value": "uint16_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Dn" }, "b": { - "register": "Hm" + "register": "Dm" } }, "Architectures": [ @@ -75487,142 +271167,137 @@ ], "instructions": [ [ - "UQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubq_s16", + "name": "vqshlh_n_s16", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int16_t a", + "const int n" ], "return_type": { - "value": "int16x8_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Hn" }, - "b": { - "register": "Vm.8H" + "n": { + "minimum": 0, + "maximum": 15 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubq_s32", + "name": "vqshlh_n_u16", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "uint16_t a", + "const int n" ], "return_type": { - "value": "int32x4_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Hn" }, - "b": { - "register": "Vm.4S" + "n": { + "minimum": 0, + "maximum": 15 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubq_s64", + "name": "vqshlh_s16", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "int16_t a", + "int16_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Hn" }, "b": { - "register": "Vm.2D" + "register": "Hm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubq_s8", + "name": "vqshlh_u16", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "uint16_t a", + "int16_t b" ], "return_type": { - "value": "int8x16_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Hn" }, "b": { - "register": "Vm.16B" + "register": "Hm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubq_u16", + "name": "vqshlq_n_s16", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "int16x8_t a", + "const int n" ], "return_type": { - "value": "uint16x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" }, - "b": { - "register": "Vm.8H" + "n": { + "minimum": 0, + "maximum": 15 } }, "Architectures": [ @@ -75632,26 +271307,27 @@ ], "instructions": [ [ - "UQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubq_u32", + "name": "vqshlq_n_s32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "int32x4_t a", + "const int n" ], "return_type": { - "value": "uint32x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" }, - "b": { - "register": "Vm.4S" + "n": { + "minimum": 0, + "maximum": 31 } }, "Architectures": [ @@ -75661,26 +271337,27 @@ ], "instructions": [ [ - "UQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubq_u64", + "name": "vqshlq_n_s64", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "int64x2_t a", + "const int n" ], "return_type": { - "value": "uint64x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2D" }, - "b": { - "register": "Vm.2D" + "n": { + "minimum": 0, + "maximum": 63 } }, "Architectures": [ @@ -75690,26 +271367,27 @@ ], "instructions": [ [ - "UQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubq_u8", + "name": "vqshlq_n_s8", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "int8x16_t a", + "const int n" ], "return_type": { - "value": "uint8x16_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { "register": "Vn.16B" }, - "b": { - "register": "Vm.16B" + "n": { + "minimum": 0, + "maximum": 7 } }, "Architectures": [ @@ -75719,350 +271397,379 @@ ], "instructions": [ [ - "UQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubs_s32", + "name": "vqshlq_n_u16", "arguments": [ - "int32_t a", - "int32_t b" + "uint16x8_t a", + "const int n" ], "return_type": { - "value": "int32_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vn.8H" }, - "b": { - "register": "Sm" + "n": { + "minimum": 0, + "maximum": 15 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubs_u32", + "name": "vqshlq_n_u32", "arguments": [ - "uint32_t a", - "uint32_t b" + "uint32x4_t a", + "const int n" ], "return_type": { - "value": "uint32_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vn.4S" }, - "b": { - "register": "Sm" + "n": { + "minimum": 0, + "maximum": 31 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl1_p8", + "name": "vqshlq_n_u64", "arguments": [ - "poly8x16_t t", - "uint8x8_t idx" + "uint64x2_t a", + "const int n" ], "return_type": { - "value": "poly8x8_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" + "a": { + "register": "Vn.2D" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 63 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl1_s8", + "name": "vqshlq_n_u8", "arguments": [ - "int8x16_t t", - "uint8x8_t idx" + "uint8x16_t a", + "const int n" ], "return_type": { - "value": "int8x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" - }, - "t": { + "a": { "register": "Vn.16B" + }, + "n": { + "minimum": 0, + "maximum": 7 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl1_u8", + "name": "vqshlq_s16", "arguments": [ - "uint8x16_t t", - "uint8x8_t idx" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" + "a": { + "register": "Vn.8H" }, - "t": { - "register": "Vn.16B" + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl1q_p8", + "name": "vqshlq_s32", "arguments": [ - "poly8x16_t t", - "uint8x16_t idx" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" - }, - "t": { - "register": "Vn.16B" + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl1q_s8", + "name": "vqshlq_s64", "arguments": [ - "int8x16_t t", - "uint8x16_t idx" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "int8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" + "a": { + "register": "Vn.2D" }, - "t": { - "register": "Vn.16B" + "b": { + "register": "Vm.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl1q_u8", + "name": "vqshlq_s8", "arguments": [ - "uint8x16_t t", - "uint8x16_t idx" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" - }, - "t": { + "a": { "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl2_p8", + "name": "vqshlq_u16", "arguments": [ - "poly8x16x2_t t", - "uint8x8_t idx" + "uint16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" + "a": { + "register": "Vn.8H" }, - "t": { - "register": "Vn.16B" + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl2_s8", + "name": "vqshlq_u32", "arguments": [ - "int8x16x2_t t", - "uint8x8_t idx" + "uint32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "int8x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" + "a": { + "register": "Vn.4S" }, - "t": { - "register": "Vn.16B" + "b": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl2_u8", + "name": "vqshlq_u64", "arguments": [ - "uint8x16x2_t t", - "uint8x8_t idx" + "uint64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" + "a": { + "register": "Vn.2D" }, - "t": { - "register": "Vn.16B" + "b": { + "register": "Vm.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl2q_p8", + "name": "vqshlq_u8", "arguments": [ - "poly8x16x2_t t", - "uint8x16_t idx" + "uint8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" - }, - "t": { + "a": { "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl2q_s8", + "name": "vqshls_n_s32", "arguments": [ - "int8x16x2_t t", - "uint8x16_t idx" + "int32_t a", + "const int n" ], "return_type": { - "value": "int8x16_t" + "value": "int32_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" + "a": { + "register": "Sn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 31 } }, "Architectures": [ @@ -76070,26 +271777,27 @@ ], "instructions": [ [ - "TBL" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl2q_u8", + "name": "vqshls_n_u32", "arguments": [ - "uint8x16x2_t t", - "uint8x16_t idx" + "uint32_t a", + "const int n" ], "return_type": { - "value": "uint8x16_t" + "value": "uint32_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" + "a": { + "register": "Sn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 31 } }, "Architectures": [ @@ -76097,26 +271805,26 @@ ], "instructions": [ [ - "TBL" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl3_p8", + "name": "vqshls_s32", "arguments": [ - "poly8x16x3_t t", - "uint8x8_t idx" + "int32_t a", + "int32_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "int32_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" + "a": { + "register": "Sn" }, - "t": { - "register": "Vn.16B" + "b": { + "register": "Sm" } }, "Architectures": [ @@ -76124,26 +271832,26 @@ ], "instructions": [ [ - "TBL" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl3_s8", + "name": "vqshls_u32", "arguments": [ - "int8x16x3_t t", - "uint8x8_t idx" + "uint32_t a", + "int32_t b" ], "return_type": { - "value": "int8x8_t" + "value": "uint32_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" + "a": { + "register": "Sn" }, - "t": { - "register": "Vn.16B" + "b": { + "register": "Sm" } }, "Architectures": [ @@ -76151,134 +271859,147 @@ ], "instructions": [ [ - "TBL" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl3_u8", + "name": "vqshlu_n_s16", "arguments": [ - "uint8x16x3_t t", - "uint8x8_t idx" + "int16x4_t a", + "const int n" ], "return_type": { - "value": "uint8x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" + "a": { + "register": "Vn.4H" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 15 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl3q_p8", + "name": "vqshlu_n_s32", "arguments": [ - "poly8x16x3_t t", - "uint8x16_t idx" + "int32x2_t a", + "const int n" ], "return_type": { - "value": "poly8x16_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" + "a": { + "register": "Vn.2S" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 31 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl3q_s8", + "name": "vqshlu_n_s64", "arguments": [ - "int8x16x3_t t", - "uint8x16_t idx" + "int64x1_t a", + "const int n" ], "return_type": { - "value": "int8x16_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" + "a": { + "register": "Dn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 63 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl3q_u8", + "name": "vqshlu_n_s8", "arguments": [ - "uint8x16x3_t t", - "uint8x16_t idx" + "int8x8_t a", + "const int n" ], "return_type": { - "value": "uint8x16_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" + "a": { + "register": "Vn.8B" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 7 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl4_p8", + "name": "vqshlub_n_s8", "arguments": [ - "poly8x16x4_t t", - "uint8x8_t idx" + "int8_t a", + "const int n" ], "return_type": { - "value": "poly8x8_t" + "value": "uint8_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" + "a": { + "register": "Bn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 7 } }, "Architectures": [ @@ -76286,26 +272007,27 @@ ], "instructions": [ [ - "TBL" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl4_s8", + "name": "vqshlud_n_s64", "arguments": [ - "int8x16x4_t t", - "uint8x8_t idx" + "int64_t a", + "const int n" ], "return_type": { - "value": "int8x8_t" + "value": "uint64_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" + "a": { + "register": "Dn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 63 } }, "Architectures": [ @@ -76313,26 +272035,27 @@ ], "instructions": [ [ - "TBL" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl4_u8", + "name": "vqshluh_n_s16", "arguments": [ - "uint8x16x4_t t", - "uint8x8_t idx" + "int16_t a", + "const int n" ], "return_type": { - "value": "uint8x8_t" + "value": "uint16_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" + "a": { + "register": "Hn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 15 } }, "Architectures": [ @@ -76340,142 +272063,147 @@ ], "instructions": [ [ - "TBL" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl4q_p8", + "name": "vqshluq_n_s16", "arguments": [ - "poly8x16x4_t t", - "uint8x16_t idx" + "int16x8_t a", + "const int n" ], "return_type": { - "value": "poly8x16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" + "a": { + "register": "Vn.8H" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 15 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl4q_s8", + "name": "vqshluq_n_s32", "arguments": [ - "int8x16x4_t t", - "uint8x16_t idx" + "int32x4_t a", + "const int n" ], "return_type": { - "value": "int8x16_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" + "a": { + "register": "Vn.4S" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 31 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl4q_u8", + "name": "vqshluq_n_s64", "arguments": [ - "uint8x16x4_t t", - "uint8x16_t idx" + "int64x2_t a", + "const int n" ], "return_type": { - "value": "uint8x16_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" + "a": { + "register": "Vn.2D" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 63 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx1_p8", + "name": "vqshluq_n_s8", "arguments": [ - "poly8x8_t a", - "poly8x16_t t", - "uint8x8_t idx" + "int8x16_t a", + "const int n" ], "return_type": { - "value": "poly8x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "idx": { - "register": "Vm.8B" - }, - "t": { "register": "Vn.16B" + }, + "n": { + "minimum": 0, + "maximum": 7 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBX" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx1_s8", + "name": "vqshlus_n_s32", "arguments": [ - "int8x8_t a", - "int8x16_t t", - "uint8x8_t idx" + "int32_t a", + "const int n" ], "return_type": { - "value": "int8x8_t" + "value": "uint32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "idx": { - "register": "Vm.8B" + "register": "Sn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 31 } }, "Architectures": [ @@ -76483,30 +272211,31 @@ ], "instructions": [ [ - "TBX" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx1_u8", + "name": "vqshrn_high_n_s16", "arguments": [ - "uint8x8_t a", - "uint8x16_t t", - "uint8x8_t idx" + "int8x8_t r", + "int16x8_t a", + "const int n" ], "return_type": { - "value": "uint8x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vn.8H" }, - "idx": { - "register": "Vm.8B" + "n": { + "minimum": 1, + "maximum": 8 }, - "t": { - "register": "Vn.16B" + "r": { + "register": "Vd.8B" } }, "Architectures": [ @@ -76514,30 +272243,31 @@ ], "instructions": [ [ - "TBX" + "SQSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx1q_p8", + "name": "vqshrn_high_n_s32", "arguments": [ - "poly8x16_t a", - "poly8x16_t t", - "uint8x16_t idx" + "int16x4_t r", + "int32x4_t a", + "const int n" ], "return_type": { - "value": "poly8x16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vn.4S" }, - "idx": { - "register": "Vm.16B" + "n": { + "minimum": 1, + "maximum": 16 }, - "t": { - "register": "Vn.16B" + "r": { + "register": "Vd.4H" } }, "Architectures": [ @@ -76545,30 +272275,31 @@ ], "instructions": [ [ - "TBX" + "SQSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx1q_s8", + "name": "vqshrn_high_n_s64", "arguments": [ - "int8x16_t a", - "int8x16_t t", - "uint8x16_t idx" + "int32x2_t r", + "int64x2_t a", + "const int n" ], "return_type": { - "value": "int8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vn.2D" }, - "idx": { - "register": "Vm.16B" + "n": { + "minimum": 1, + "maximum": 32 }, - "t": { - "register": "Vn.16B" + "r": { + "register": "Vd.2S" } }, "Architectures": [ @@ -76576,30 +272307,31 @@ ], "instructions": [ [ - "TBX" + "SQSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx1q_u8", + "name": "vqshrn_high_n_u16", "arguments": [ - "uint8x16_t a", - "uint8x16_t t", - "uint8x16_t idx" + "uint8x8_t r", + "uint16x8_t a", + "const int n" ], "return_type": { "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vn.8H" }, - "idx": { - "register": "Vm.16B" + "n": { + "minimum": 1, + "maximum": 8 }, - "t": { - "register": "Vn.16B" + "r": { + "register": "Vd.8B" } }, "Architectures": [ @@ -76607,30 +272339,31 @@ ], "instructions": [ [ - "TBX" + "UQSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx2_p8", + "name": "vqshrn_high_n_u32", "arguments": [ - "poly8x8_t a", - "poly8x16x2_t t", - "uint8x8_t idx" + "uint16x4_t r", + "uint32x4_t a", + "const int n" ], "return_type": { - "value": "poly8x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vn.4S" }, - "idx": { - "register": "Vm.8B" + "n": { + "minimum": 1, + "maximum": 16 }, - "t": { - "register": "Vn.16B" + "r": { + "register": "Vd.4H" } }, "Architectures": [ @@ -76638,30 +272371,31 @@ ], "instructions": [ [ - "TBX" + "UQSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx2_s8", + "name": "vqshrn_high_n_u64", "arguments": [ - "int8x8_t a", - "int8x16x2_t t", - "uint8x8_t idx" + "uint32x2_t r", + "uint64x2_t a", + "const int n" ], "return_type": { - "value": "int8x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vn.2D" }, - "idx": { - "register": "Vm.8B" + "n": { + "minimum": 1, + "maximum": 32 }, - "t": { - "register": "Vn.16B" + "r": { + "register": "Vd.2S" } }, "Architectures": [ @@ -76669,216 +272403,207 @@ ], "instructions": [ [ - "TBX" + "UQSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx2_u8", + "name": "vqshrn_n_s16", "arguments": [ - "uint8x8_t a", - "uint8x16x2_t t", - "uint8x8_t idx" + "int16x8_t a", + "const int n" ], "return_type": { - "value": "uint8x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "idx": { - "register": "Vm.8B" + "register": "Vn.8H" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBX" + "SQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx2q_p8", + "name": "vqshrn_n_s32", "arguments": [ - "poly8x16_t a", - "poly8x16x2_t t", - "uint8x16_t idx" + "int32x4_t a", + "const int n" ], "return_type": { - "value": "poly8x16_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "idx": { - "register": "Vm.16B" + "register": "Vn.4S" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBX" + "SQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx2q_s8", + "name": "vqshrn_n_s64", "arguments": [ - "int8x16_t a", - "int8x16x2_t t", - "uint8x16_t idx" + "int64x2_t a", + "const int n" ], "return_type": { - "value": "int8x16_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "idx": { - "register": "Vm.16B" + "register": "Vn.2D" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBX" + "SQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx2q_u8", + "name": "vqshrn_n_u16", "arguments": [ - "uint8x16_t a", - "uint8x16x2_t t", - "uint8x16_t idx" + "uint16x8_t a", + "const int n" ], "return_type": { - "value": "uint8x16_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "idx": { - "register": "Vm.16B" + "register": "Vn.8H" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBX" + "UQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx3_p8", + "name": "vqshrn_n_u32", "arguments": [ - "poly8x8_t a", - "poly8x16x3_t t", - "uint8x8_t idx" + "uint32x4_t a", + "const int n" ], "return_type": { - "value": "poly8x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "idx": { - "register": "Vm.8B" + "register": "Vn.4S" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBX" + "UQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx3_s8", + "name": "vqshrn_n_u64", "arguments": [ - "int8x8_t a", - "int8x16x3_t t", - "uint8x8_t idx" + "uint64x2_t a", + "const int n" ], "return_type": { - "value": "int8x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "idx": { - "register": "Vm.8B" + "register": "Vn.2D" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBX" + "UQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx3_u8", + "name": "vqshrnd_n_s64", "arguments": [ - "uint8x8_t a", - "uint8x16x3_t t", - "uint8x8_t idx" + "int64_t a", + "const int n" ], "return_type": { - "value": "uint8x8_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "idx": { - "register": "Vm.8B" + "register": "Dn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -76886,30 +272611,27 @@ ], "instructions": [ [ - "TBX" + "SQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx3q_p8", + "name": "vqshrnd_n_u64", "arguments": [ - "poly8x16_t a", - "poly8x16x3_t t", - "uint8x16_t idx" + "uint64_t a", + "const int n" ], "return_type": { - "value": "poly8x16_t" + "value": "uint32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "idx": { - "register": "Vm.16B" + "register": "Dn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -76917,30 +272639,27 @@ ], "instructions": [ [ - "TBX" + "UQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx3q_s8", + "name": "vqshrnh_n_s16", "arguments": [ - "int8x16_t a", - "int8x16x3_t t", - "uint8x16_t idx" + "int16_t a", + "const int n" ], "return_type": { - "value": "int8x16_t" + "value": "int8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "idx": { - "register": "Vm.16B" + "register": "Hn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -76948,30 +272667,27 @@ ], "instructions": [ [ - "TBX" + "SQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx3q_u8", + "name": "vqshrnh_n_u16", "arguments": [ - "uint8x16_t a", - "uint8x16x3_t t", - "uint8x16_t idx" + "uint16_t a", + "const int n" ], "return_type": { - "value": "uint8x16_t" + "value": "uint8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "idx": { - "register": "Vm.16B" + "register": "Hn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -76979,30 +272695,27 @@ ], "instructions": [ [ - "TBX" + "UQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx4_p8", + "name": "vqshrns_n_s32", "arguments": [ - "poly8x8_t a", - "poly8x16x4_t t", - "uint8x8_t idx" + "int32_t a", + "const int n" ], "return_type": { - "value": "poly8x8_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "idx": { - "register": "Vm.8B" + "register": "Sn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -77010,30 +272723,27 @@ ], "instructions": [ [ - "TBX" + "SQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx4_s8", + "name": "vqshrns_n_u32", "arguments": [ - "int8x8_t a", - "int8x16x4_t t", - "uint8x8_t idx" + "uint32_t a", + "const int n" ], "return_type": { - "value": "int8x8_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "idx": { - "register": "Vm.8B" + "register": "Sn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -77041,30 +272751,31 @@ ], "instructions": [ [ - "TBX" + "UQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx4_u8", + "name": "vqshrun_high_n_s16", "arguments": [ - "uint8x8_t a", - "uint8x16x4_t t", - "uint8x8_t idx" + "uint8x8_t r", + "int16x8_t a", + "const int n" ], "return_type": { - "value": "uint8x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vn.8H" }, - "idx": { - "register": "Vm.8B" + "n": { + "minimum": 1, + "maximum": 8 }, - "t": { - "register": "Vn.16B" + "r": { + "register": "Vd.8B" } }, "Architectures": [ @@ -77072,30 +272783,31 @@ ], "instructions": [ [ - "TBX" + "SQSHRUN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx4q_p8", + "name": "vqshrun_high_n_s32", "arguments": [ - "poly8x16_t a", - "poly8x16x4_t t", - "uint8x16_t idx" + "uint16x4_t r", + "int32x4_t a", + "const int n" ], "return_type": { - "value": "poly8x16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vn.4S" }, - "idx": { - "register": "Vm.16B" + "n": { + "minimum": 1, + "maximum": 16 }, - "t": { - "register": "Vn.16B" + "r": { + "register": "Vd.4H" } }, "Architectures": [ @@ -77103,30 +272815,31 @@ ], "instructions": [ [ - "TBX" + "SQSHRUN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx4q_s8", + "name": "vqshrun_high_n_s64", "arguments": [ - "int8x16_t a", - "int8x16x4_t t", - "uint8x16_t idx" + "uint32x2_t r", + "int64x2_t a", + "const int n" ], "return_type": { - "value": "int8x16_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vn.2D" }, - "idx": { - "register": "Vm.16B" + "n": { + "minimum": 1, + "maximum": 32 }, - "t": { - "register": "Vn.16B" + "r": { + "register": "Vd.2S" } }, "Architectures": [ @@ -77134,123 +272847,117 @@ ], "instructions": [ [ - "TBX" + "SQSHRUN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx4q_u8", + "name": "vqshrun_n_s16", "arguments": [ - "uint8x16_t a", - "uint8x16x4_t t", - "uint8x16_t idx" + "int16x8_t a", + "const int n" ], "return_type": { - "value": "uint8x16_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "idx": { - "register": "Vm.16B" + "register": "Vn.8H" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBX" + "SQSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_high_s16", + "name": "vqshrun_n_s32", "arguments": [ - "int8x8_t r", - "int16x8_t a", - "int16x8_t b" + "int32x4_t a", + "const int n" ], "return_type": { - "value": "int8x16_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Vn.4S" }, - "r": { - "register": "Vd.8B" + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "RADDHN2" + "SQSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_high_s32", + "name": "vqshrun_n_s64", "arguments": [ - "int16x4_t r", - "int32x4_t a", - "int32x4_t b" + "int64x2_t a", + "const int n" ], "return_type": { - "value": "int16x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Vn.2D" }, - "r": { - "register": "Vd.4H" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "RADDHN2" + "SQSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_high_s64", + "name": "vqshrund_n_s64", "arguments": [ - "int32x2_t r", - "int64x2_t a", - "int64x2_t b" + "int64_t a", + "const int n" ], "return_type": { - "value": "int32x4_t" + "value": "uint32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "register": "Dn" }, - "r": { - "register": "Vd.2S" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -77258,30 +272965,27 @@ ], "instructions": [ [ - "RADDHN2" + "SQSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_high_u16", + "name": "vqshrunh_n_s16", "arguments": [ - "uint8x8_t r", - "uint16x8_t a", - "uint16x8_t b" + "int16_t a", + "const int n" ], "return_type": { - "value": "uint8x16_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "value": "uint8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" }, - "r": { - "register": "Vd.8B" + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -77289,30 +272993,27 @@ ], "instructions": [ [ - "RADDHN2" + "SQSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_high_u32", + "name": "vqshruns_n_s32", "arguments": [ - "uint16x4_t r", - "uint32x4_t a", - "uint32x4_t b" + "int32_t a", + "const int n" ], "return_type": { - "value": "uint16x8_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Sn" }, - "r": { - "register": "Vd.4H" + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -77320,57 +273021,55 @@ ], "instructions": [ [ - "RADDHN2" + "SQSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_high_u64", + "name": "vqsub_s16", "arguments": [ - "uint32x2_t r", - "uint64x2_t a", - "uint64x2_t b" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.4H" }, "b": { - "register": "Vm.2D" - }, - "r": { - "register": "Vd.2S" + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "RADDHN2" + "SQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_s16", + "name": "vqsub_s32", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "int8x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2S" }, "b": { - "register": "Vm.8H" + "register": "Vm.2S" } }, "Architectures": [ @@ -77380,26 +273079,26 @@ ], "instructions": [ [ - "RADDHN" + "SQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_s32", + "name": "vqsub_s64", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "int16x4_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Dn" }, "b": { - "register": "Vm.4S" + "register": "Dm" } }, "Architectures": [ @@ -77409,26 +273108,26 @@ ], "instructions": [ [ - "RADDHN" + "SQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_s64", + "name": "vqsub_s8", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.8B" }, "b": { - "register": "Vm.2D" + "register": "Vm.8B" } }, "Architectures": [ @@ -77438,26 +273137,26 @@ ], "instructions": [ [ - "RADDHN" + "SQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_u16", + "name": "vqsub_u16", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4H" }, "b": { - "register": "Vm.8H" + "register": "Vm.4H" } }, "Architectures": [ @@ -77467,26 +273166,26 @@ ], "instructions": [ [ - "RADDHN" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_u32", + "name": "vqsub_u32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2S" }, "b": { - "register": "Vm.4S" + "register": "Vm.2S" } }, "Architectures": [ @@ -77496,26 +273195,26 @@ ], "instructions": [ [ - "RADDHN" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_u64", + "name": "vqsub_u64", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "uint64x1_t a", + "uint64x1_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Dn" }, "b": { - "register": "Vm.2D" + "register": "Dm" } }, "Architectures": [ @@ -77525,47 +273224,55 @@ ], "instructions": [ [ - "RADDHN" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrax1q_u64", + "name": "vqsub_u8", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.8B" }, - "b": {} + "b": { + "register": "Vm.8B" + } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "RAX1" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrbit_p8", + "name": "vqsubb_s8", "arguments": [ - "poly8x8_t a" + "int8_t a", + "int8_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "int8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Bn" + }, + "b": { + "register": "Bm" } }, "Architectures": [ @@ -77573,22 +273280,26 @@ ], "instructions": [ [ - "RBIT" + "SQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrbit_s8", + "name": "vqsubb_u8", "arguments": [ - "int8x8_t a" + "uint8_t a", + "uint8_t b" ], "return_type": { - "value": "int8x8_t" + "value": "uint8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Bn" + }, + "b": { + "register": "Bm" } }, "Architectures": [ @@ -77596,22 +273307,26 @@ ], "instructions": [ [ - "RBIT" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrbit_u8", + "name": "vqsubd_s64", "arguments": [ - "uint8x8_t a" + "int64_t a", + "int64_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Dn" + }, + "b": { + "register": "Dm" } }, "Architectures": [ @@ -77619,22 +273334,26 @@ ], "instructions": [ [ - "RBIT" + "SQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrbitq_p8", + "name": "vqsubd_u64", "arguments": [ - "poly8x16_t a" + "uint64_t a", + "uint64_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Dn" + }, + "b": { + "register": "Dm" } }, "Architectures": [ @@ -77642,22 +273361,26 @@ ], "instructions": [ [ - "RBIT" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrbitq_s8", + "name": "vqsubh_s16", "arguments": [ - "int8x16_t a" + "int16_t a", + "int16_t b" ], "return_type": { - "value": "int8x16_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Hn" + }, + "b": { + "register": "Hm" } }, "Architectures": [ @@ -77665,22 +273388,26 @@ ], "instructions": [ [ - "RBIT" + "SQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrbitq_u8", + "name": "vqsubh_u16", "arguments": [ - "uint8x16_t a" + "uint16_t a", + "uint16_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Hn" + }, + "b": { + "register": "Hm" } }, "Architectures": [ @@ -77688,46 +273415,55 @@ ], "instructions": [ [ - "RBIT" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpe_f16", + "name": "vqsubq_s16", "arguments": [ - "float16x4_t a" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "float16x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FRECPE" + "SQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpe_f32", + "name": "vqsubq_s32", "arguments": [ - "float32x2_t a" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "float32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" } }, "Architectures": [ @@ -77737,45 +273473,55 @@ ], "instructions": [ [ - "FRECPE" + "SQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpe_f64", + "name": "vqsubq_s64", "arguments": [ - "float64x1_t a" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "float64x1_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRECPE" + "SQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpe_u32", + "name": "vqsubq_s8", "arguments": [ - "uint32x2_t a" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" } }, "Architectures": [ @@ -77785,92 +273531,113 @@ ], "instructions": [ [ - "URECPE" + "SQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecped_f64", + "name": "vqsubq_u16", "arguments": [ - "float64_t a" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "float64_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRECPE" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpeh_f16", + "name": "vqsubq_u32", "arguments": [ - "float16_t a" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "float16_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRECPE" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpeq_f16", + "name": "vqsubq_u64", "arguments": [ - "float16x8_t a" + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "float16x8_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FRECPE" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpeq_f32", + "name": "vqsubq_u8", "arguments": [ - "float32x4_t a" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "float32x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" } }, "Architectures": [ @@ -77880,22 +273647,26 @@ ], "instructions": [ [ - "FRECPE" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpeq_f64", + "name": "vqsubs_s32", "arguments": [ - "float64x2_t a" + "int32_t a", + "int32_t b" ], "return_type": { - "value": "float64x2_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Sn" + }, + "b": { + "register": "Sm" } }, "Architectures": [ @@ -77903,47 +273674,53 @@ ], "instructions": [ [ - "FRECPE" + "SQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpeq_u32", + "name": "vqsubs_u32", "arguments": [ - "uint32x4_t a" + "uint32_t a", + "uint32_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "uint32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Sn" + }, + "b": { + "register": "Sm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URECPE" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpes_f32", + "name": "vqtbl1_p8", "arguments": [ - "float32_t a" + "poly8x16_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float32_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "idx": { + "register": "Vm.8B" + }, + "t": { + "register": "Vn.16B" } }, "Architectures": [ @@ -77951,83 +273728,80 @@ ], "instructions": [ [ - "FRECPE" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecps_f16", + "name": "vqtbl1_s8", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "int8x16_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "idx": { + "register": "Vm.8B" }, - "b": { - "register": "Vm.4H" + "t": { + "register": "Vn.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FRECPS" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecps_f32", + "name": "vqtbl1_u8", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "uint8x16_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float32x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "idx": { + "register": "Vm.8B" }, - "b": { - "register": "Vm.2S" + "t": { + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FRECPS" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecps_f64", + "name": "vqtbl1q_p8", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "poly8x16_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float64x1_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "idx": { + "register": "Vm.16B" }, - "b": { - "register": "Dm" + "t": { + "register": "Vn.16B" } }, "Architectures": [ @@ -78035,26 +273809,26 @@ ], "instructions": [ [ - "FRECPS" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpsd_f64", + "name": "vqtbl1q_s8", "arguments": [ - "float64_t a", - "float64_t b" + "int8x16_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float64_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "idx": { + "register": "Vm.16B" }, - "b": { - "register": "Dm" + "t": { + "register": "Vn.16B" } }, "Architectures": [ @@ -78062,26 +273836,26 @@ ], "instructions": [ [ - "FRECPS" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpsh_f16", + "name": "vqtbl1q_u8", "arguments": [ - "float16_t a", - "float16_t b" + "uint8x16_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float16_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "idx": { + "register": "Vm.16B" }, - "b": { - "register": "Hm" + "t": { + "register": "Vn.16B" } }, "Architectures": [ @@ -78089,83 +273863,89 @@ ], "instructions": [ [ - "FRECPS" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpsq_f16", + "name": "vqtbl2_p8", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "poly8x16x2_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float16x8_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "idx": { + "register": "Vm.8B" }, - "b": { - "register": "Vm.8H" + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FRECPS" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpsq_f32", + "name": "vqtbl2_s8", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "int8x16x2_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "idx": { + "register": "Vm.8B" }, - "b": { - "register": "Vm.4S" + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FRECPS" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpsq_f64", + "name": "vqtbl2_u8", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "uint8x16x2_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "idx": { + "register": "Vm.8B" }, - "b": { - "register": "Vm.2D" + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -78173,26 +273953,29 @@ ], "instructions": [ [ - "FRECPS" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpss_f32", + "name": "vqtbl2q_p8", "arguments": [ - "float32_t a", - "float32_t b" + "poly8x16x2_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float32_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "idx": { + "register": "Vm.16B" }, - "b": { - "register": "Sm" + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -78200,22 +273983,29 @@ ], "instructions": [ [ - "FRECPS" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpxd_f64", + "name": "vqtbl2q_s8", "arguments": [ - "float64_t a" + "int8x16x2_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float64_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -78223,22 +274013,29 @@ ], "instructions": [ [ - "FRECPX" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpxh_f16", + "name": "vqtbl2q_u8", "arguments": [ - "float16_t a" + "uint8x16x2_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float16_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -78246,22 +274043,32 @@ ], "instructions": [ [ - "FRECPX" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpxs_f32", + "name": "vqtbl3_p8", "arguments": [ - "float32_t a" + "poly8x16x3_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float32_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -78269,47 +274076,65 @@ ], "instructions": [ [ - "FRECPX" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_f32", + "name": "vqtbl3_s8", "arguments": [ - "float32x2_t a" + "int8x16x3_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2S" + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_f64", + "name": "vqtbl3_u8", "arguments": [ - "float64x1_t a" + "uint8x16x3_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.1D" + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -78317,321 +274142,438 @@ ], "instructions": [ [ - "NOP" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_p16", + "name": "vqtbl3q_p8", "arguments": [ - "poly16x4_t a" + "poly8x16x3_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4H" + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_p64", + "name": "vqtbl3q_s8", "arguments": [ - "poly64x1_t a" + "int8x16x3_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.1D" + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_p8", + "name": "vqtbl3q_u8", "arguments": [ - "poly8x8_t a" + "uint8x16x3_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_s16", + "name": "vqtbl4_p8", "arguments": [ - "int16x4_t a" + "poly8x16x4_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4H" + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_s32", + "name": "vqtbl4_s8", "arguments": [ - "int32x2_t a" + "int8x16x4_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2S" + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_s64", + "name": "vqtbl4_u8", "arguments": [ - "int64x1_t a" + "uint8x16x4_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.1D" + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_s8", + "name": "vqtbl4q_p8", "arguments": [ - "int8x8_t a" + "poly8x16x4_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_u16", + "name": "vqtbl4q_s8", "arguments": [ - "uint16x4_t a" + "int8x16x4_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4H" + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_u32", + "name": "vqtbl4q_u8", "arguments": [ - "uint32x2_t a" + "uint8x16x4_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2S" + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_u64", + "name": "vqtbx1_p8", "arguments": [ - "uint64x1_t a" + "poly8x8_t a", + "poly8x16_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t": { + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_u8", + "name": "vqtbx1_s8", "arguments": [ - "uint8x8_t a" + "int8x8_t a", + "int8x16_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t": { + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_f16", + "name": "vqtbx1_u8", "arguments": [ - "float16x4_t a" + "uint8x8_t a", + "uint8x16_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float32x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t": { + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_f64", + "name": "vqtbx1q_p8", "arguments": [ - "float64x1_t a" + "poly8x16_t a", + "poly8x16_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float32x2_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t": { + "register": "Vn.16B" } }, "Architectures": [ @@ -78639,272 +274581,376 @@ ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_p16", + "name": "vqtbx1q_s8", "arguments": [ - "poly16x4_t a" + "int8x16_t a", + "int8x16_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float32x2_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t": { + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_p8", + "name": "vqtbx1q_u8", "arguments": [ - "poly8x8_t a" + "uint8x16_t a", + "uint8x16_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float32x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t": { + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_s16", + "name": "vqtbx2_p8", "arguments": [ - "int16x4_t a" + "poly8x8_t a", + "poly8x16x2_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float32x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_s32", + "name": "vqtbx2_s8", "arguments": [ - "int32x2_t a" + "int8x8_t a", + "int8x16x2_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float32x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_s64", + "name": "vqtbx2_u8", "arguments": [ - "int64x1_t a" + "uint8x8_t a", + "uint8x16x2_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float32x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_s8", + "name": "vqtbx2q_p8", "arguments": [ - "int8x8_t a" + "poly8x16_t a", + "poly8x16x2_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float32x2_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_u16", + "name": "vqtbx2q_s8", "arguments": [ - "uint16x4_t a" + "int8x16_t a", + "int8x16x2_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float32x2_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_u32", + "name": "vqtbx2q_u8", "arguments": [ - "uint32x2_t a" + "uint8x16_t a", + "uint8x16x2_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float32x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_u64", + "name": "vqtbx3_p8", "arguments": [ - "uint64x1_t a" + "poly8x8_t a", + "poly8x16x3_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float32x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_u8", + "name": "vqtbx3_s8", "arguments": [ - "uint8x8_t a" + "int8x8_t a", + "int8x16x3_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float32x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_f16", + "name": "vqtbx3_u8", "arguments": [ - "float16x4_t a" + "uint8x8_t a", + "uint8x16x3_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float64x1_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -78912,22 +274958,36 @@ ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_f32", + "name": "vqtbx3q_p8", "arguments": [ - "float32x2_t a" + "poly8x16_t a", + "poly8x16x3_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float64x1_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -78935,22 +274995,36 @@ ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_p16", + "name": "vqtbx3q_s8", "arguments": [ - "poly16x4_t a" + "int8x16_t a", + "int8x16x3_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float64x1_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -78958,22 +275032,36 @@ ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_p64", + "name": "vqtbx3q_u8", "arguments": [ - "poly64x1_t a" + "uint8x16_t a", + "uint8x16x3_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float64x1_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -78981,22 +275069,39 @@ ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_p8", + "name": "vqtbx4_p8", "arguments": [ - "poly8x8_t a" + "poly8x8_t a", + "poly8x16x4_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float64x1_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -79004,22 +275109,39 @@ ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_s16", + "name": "vqtbx4_s8", "arguments": [ - "int16x4_t a" + "int8x8_t a", + "int8x16x4_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float64x1_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -79027,22 +275149,39 @@ ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_s32", + "name": "vqtbx4_u8", "arguments": [ - "int32x2_t a" + "uint8x8_t a", + "uint8x16x4_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float64x1_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -79050,22 +275189,39 @@ ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_s64", + "name": "vqtbx4q_p8", "arguments": [ - "int64x1_t a" + "poly8x16_t a", + "poly8x16x4_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float64x1_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -79073,22 +275229,39 @@ ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_s8", + "name": "vqtbx4q_s8", "arguments": [ - "int8x8_t a" + "int8x16_t a", + "int8x16x4_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float64x1_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -79096,22 +275269,39 @@ ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_u16", + "name": "vqtbx4q_u8", "arguments": [ - "uint16x4_t a" + "uint8x16_t a", + "uint8x16x4_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float64x1_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -79119,22 +275309,30 @@ ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_u32", + "name": "vraddhn_high_s16", "arguments": [ - "uint32x2_t a" + "int8x8_t r", + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "float64x1_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + }, + "r": { + "register": "Vd.8B" } }, "Architectures": [ @@ -79142,22 +275340,30 @@ ], "instructions": [ [ - "NOP" + "RADDHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_u64", + "name": "vraddhn_high_s32", "arguments": [ - "uint64x1_t a" + "int16x4_t r", + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "float64x1_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" + }, + "r": { + "register": "Vd.4H" } }, "Architectures": [ @@ -79165,22 +275371,30 @@ ], "instructions": [ [ - "NOP" + "RADDHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_u8", + "name": "vraddhn_high_s64", "arguments": [ - "uint8x8_t a" + "int32x2_t r", + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "float64x1_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ @@ -79188,72 +275402,92 @@ ], "instructions": [ [ - "NOP" + "RADDHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_f16", + "name": "vraddhn_high_u16", "arguments": [ - "float16x4_t a" + "uint8x8_t r", + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "poly16x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + }, + "r": { + "register": "Vd.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "RADDHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_f32", + "name": "vraddhn_high_u32", "arguments": [ - "float32x2_t a" + "uint16x4_t r", + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "poly16x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" + }, + "r": { + "register": "Vd.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "RADDHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_f64", + "name": "vraddhn_high_u64", "arguments": [ - "float64x1_t a" + "uint32x2_t r", + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "poly16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ @@ -79261,46 +275495,55 @@ ], "instructions": [ [ - "NOP" + "RADDHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_p64", + "name": "vraddhn_s16", "arguments": [ - "poly64x1_t a" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "poly16x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "NOP" + "RADDHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_p8", + "name": "vraddhn_s32", "arguments": [ - "poly8x8_t a" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "poly16x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" } }, "Architectures": [ @@ -79310,22 +275553,26 @@ ], "instructions": [ [ - "NOP" + "RADDHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_s16", + "name": "vraddhn_s64", "arguments": [ - "int16x4_t a" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "poly16x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" } }, "Architectures": [ @@ -79335,22 +275582,26 @@ ], "instructions": [ [ - "NOP" + "RADDHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_s32", + "name": "vraddhn_u16", "arguments": [ - "int32x2_t a" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "poly16x4_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" } }, "Architectures": [ @@ -79360,22 +275611,26 @@ ], "instructions": [ [ - "NOP" + "RADDHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_s64", + "name": "vraddhn_u32", "arguments": [ - "int64x1_t a" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "poly16x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" } }, "Architectures": [ @@ -79385,22 +275640,26 @@ ], "instructions": [ [ - "NOP" + "RADDHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_s8", + "name": "vraddhn_u64", "arguments": [ - "int8x8_t a" + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "poly16x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" } }, "Architectures": [ @@ -79410,170 +275669,164 @@ ], "instructions": [ [ - "NOP" + "RADDHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_u16", + "name": "vrax1q_u64", "arguments": [ - "uint16x4_t a" + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "poly16x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "RAX1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_u32", + "name": "vrbit_p8", "arguments": [ - "uint32x2_t a" + "poly8x8_t a" ], "return_type": { - "value": "poly16x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "RBIT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_u64", + "name": "vrbit_s8", "arguments": [ - "uint64x1_t a" + "int8x8_t a" ], "return_type": { - "value": "poly16x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vn.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "RBIT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_u8", + "name": "vrbit_u8", "arguments": [ "uint8x8_t a" ], "return_type": { - "value": "poly16x4_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vn.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "RBIT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_f16", + "name": "vrbitq_p8", "arguments": [ - "float16x4_t a" + "poly8x16_t a" ], "return_type": { - "value": "poly64x1_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "NOP" + "RBIT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_f32", + "name": "vrbitq_s8", "arguments": [ - "float32x2_t a" + "int8x16_t a" ], "return_type": { - "value": "poly64x1_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "NOP" + "RBIT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_f64", + "name": "vrbitq_u8", "arguments": [ - "float64x1_t a" + "uint8x16_t a" ], "return_type": { - "value": "poly64x1_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vn.16B" } }, "Architectures": [ @@ -79581,22 +275834,22 @@ ], "instructions": [ [ - "NOP" + "RBIT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_p16", + "name": "vrecpe_f16", "arguments": [ - "poly16x4_t a" + "float16x4_t a" ], "return_type": { - "value": "poly64x1_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.4H" } }, "Architectures": [ @@ -79605,142 +275858,141 @@ ], "instructions": [ [ - "NOP" + "FRECPE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_p8", + "name": "vrecpe_f32", "arguments": [ - "poly8x8_t a" + "float32x2_t a" ], "return_type": { - "value": "poly64x1_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vn.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_s16", + "name": "vrecpe_f64", "arguments": [ - "int16x4_t a" + "float64x1_t a" ], "return_type": { - "value": "poly64x1_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Dn" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_s32", + "name": "vrecpe_u32", "arguments": [ - "int32x2_t a" + "uint32x2_t a" ], "return_type": { - "value": "poly64x1_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "NOP" + "URECPE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_s8", + "name": "vrecped_f64", "arguments": [ - "int8x8_t a" + "float64_t a" ], "return_type": { - "value": "poly64x1_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Dn" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_u16", + "name": "vrecpeh_f16", "arguments": [ - "uint16x4_t a" + "float16_t a" ], "return_type": { - "value": "poly64x1_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Hn" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_u32", + "name": "vrecpeq_f16", "arguments": [ - "uint32x2_t a" + "float16x8_t a" ], "return_type": { - "value": "poly64x1_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.8H" } }, "Architectures": [ @@ -79749,70 +276001,70 @@ ], "instructions": [ [ - "NOP" + "FRECPE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_u64", + "name": "vrecpeq_f32", "arguments": [ - "uint64x1_t a" + "float32x4_t a" ], "return_type": { - "value": "poly64x1_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vn.4S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_u8", + "name": "vrecpeq_f64", "arguments": [ - "uint8x8_t a" + "float64x2_t a" ], "return_type": { - "value": "poly64x1_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vn.2D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_f16", + "name": "vrecpeq_u32", "arguments": [ - "float16x4_t a" + "uint32x4_t a" ], "return_type": { - "value": "poly8x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.4S" } }, "Architectures": [ @@ -79822,70 +276074,77 @@ ], "instructions": [ [ - "NOP" + "URECPE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_f32", + "name": "vrecpes_f32", "arguments": [ - "float32x2_t a" + "float32_t a" ], "return_type": { - "value": "poly8x8_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Sn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_f64", + "name": "vrecps_f16", "arguments": [ - "float64x1_t a" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_p16", + "name": "vrecps_f32", "arguments": [ - "poly16x4_t a" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" } }, "Architectures": [ @@ -79895,121 +276154,135 @@ ], "instructions": [ [ - "NOP" + "FRECPS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_p64", + "name": "vrecps_f64", "arguments": [ - "poly64x1_t a" + "float64x1_t a", + "float64x1_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Dn" + }, + "b": { + "register": "Dm" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_s16", + "name": "vrecpsd_f64", "arguments": [ - "int16x4_t a" + "float64_t a", + "float64_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Dn" + }, + "b": { + "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_s32", + "name": "vrecpsh_f16", "arguments": [ - "int32x2_t a" + "float16_t a", + "float16_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Hn" + }, + "b": { + "register": "Hm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_s64", + "name": "vrecpsq_f16", "arguments": [ - "int64x1_t a" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_s8", + "name": "vrecpsq_f32", "arguments": [ - "int8x8_t a" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" } }, "Architectures": [ @@ -80019,143 +276292,141 @@ ], "instructions": [ [ - "NOP" + "FRECPS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_u16", + "name": "vrecpsq_f64", "arguments": [ - "uint16x4_t a" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_u32", + "name": "vrecpss_f32", "arguments": [ - "uint32x2_t a" + "float32_t a", + "float32_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Sn" + }, + "b": { + "register": "Sm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_u64", + "name": "vrecpxd_f64", "arguments": [ - "uint64x1_t a" + "float64_t a" ], "return_type": { - "value": "poly8x8_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_u8", + "name": "vrecpxh_f16", "arguments": [ - "uint8x8_t a" + "float16_t a" ], "return_type": { - "value": "poly8x8_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Hn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_f16", + "name": "vrecpxs_f32", "arguments": [ - "float16x4_t a" + "float32_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Sn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_f32", + "name": "vreinterpret_f16_f32", "arguments": [ "float32x2_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { @@ -80175,12 +276446,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_f64", + "name": "vreinterpret_f16_f64", "arguments": [ "float64x1_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { @@ -80198,12 +276469,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_p16", + "name": "vreinterpret_f16_p16", "arguments": [ "poly16x4_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { @@ -80223,12 +276494,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_p64", + "name": "vreinterpret_f16_p64", "arguments": [ "poly64x1_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { @@ -80247,12 +276518,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_p8", + "name": "vreinterpret_f16_p8", "arguments": [ "poly8x8_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { @@ -80272,16 +276543,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_s32", + "name": "vreinterpret_f16_s16", "arguments": [ - "int32x2_t a" + "int16x4_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.4H" } }, "Architectures": [ @@ -80297,16 +276568,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_s64", + "name": "vreinterpret_f16_s32", "arguments": [ - "int64x1_t a" + "int32x2_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.2S" } }, "Architectures": [ @@ -80322,16 +276593,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_s8", + "name": "vreinterpret_f16_s64", "arguments": [ - "int8x8_t a" + "int64x1_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vd.1D" } }, "Architectures": [ @@ -80347,16 +276618,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_u16", + "name": "vreinterpret_f16_s8", "arguments": [ - "uint16x4_t a" + "int8x8_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.8B" } }, "Architectures": [ @@ -80372,16 +276643,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_u32", + "name": "vreinterpret_f16_u16", "arguments": [ - "uint32x2_t a" + "uint16x4_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.4H" } }, "Architectures": [ @@ -80397,16 +276668,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_u64", + "name": "vreinterpret_f16_u32", "arguments": [ - "uint64x1_t a" + "uint32x2_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.2S" } }, "Architectures": [ @@ -80422,16 +276693,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_u8", + "name": "vreinterpret_f16_u64", "arguments": [ - "uint8x8_t a" + "uint64x1_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vd.1D" } }, "Architectures": [ @@ -80447,16 +276718,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_f16", + "name": "vreinterpret_f16_u8", "arguments": [ - "float16x4_t a" + "uint8x8_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.8B" } }, "Architectures": [ @@ -80472,16 +276743,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_f32", + "name": "vreinterpret_f32_f16", "arguments": [ - "float32x2_t a" + "float16x4_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.4H" } }, "Architectures": [ @@ -80497,12 +276768,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_f64", + "name": "vreinterpret_f32_f64", "arguments": [ "float64x1_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { @@ -80520,12 +276791,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_p16", + "name": "vreinterpret_f32_p16", "arguments": [ "poly16x4_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { @@ -80545,19 +276816,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_p64", + "name": "vreinterpret_f32_p8", "arguments": [ - "poly64x1_t a" + "poly8x8_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -80569,16 +276841,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_p8", + "name": "vreinterpret_f32_s16", "arguments": [ - "poly8x8_t a" + "int16x4_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vd.4H" } }, "Architectures": [ @@ -80594,16 +276866,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_s16", + "name": "vreinterpret_f32_s32", "arguments": [ - "int16x4_t a" + "int32x2_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.2S" } }, "Architectures": [ @@ -80619,12 +276891,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_s64", + "name": "vreinterpret_f32_s64", "arguments": [ "int64x1_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { @@ -80644,12 +276916,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_s8", + "name": "vreinterpret_f32_s8", "arguments": [ "int8x8_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { @@ -80669,12 +276941,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_u16", + "name": "vreinterpret_f32_u16", "arguments": [ "uint16x4_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { @@ -80694,12 +276966,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_u32", + "name": "vreinterpret_f32_u32", "arguments": [ "uint32x2_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { @@ -80719,12 +276991,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_u64", + "name": "vreinterpret_f32_u64", "arguments": [ "uint64x1_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { @@ -80744,12 +277016,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_u8", + "name": "vreinterpret_f32_u8", "arguments": [ "uint8x8_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { @@ -80769,12 +277041,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_f16", + "name": "vreinterpret_f64_f16", "arguments": [ "float16x4_t a" ], "return_type": { - "value": "int64x1_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { @@ -80782,8 +277054,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -80794,12 +277064,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_f32", + "name": "vreinterpret_f64_f32", "arguments": [ "float32x2_t a" ], "return_type": { - "value": "int64x1_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { @@ -80807,8 +277077,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -80819,16 +277087,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_f64", + "name": "vreinterpret_f64_p16", "arguments": [ - "float64x1_t a" + "poly16x4_t a" ], "return_type": { - "value": "int64x1_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.4H" } }, "Architectures": [ @@ -80842,21 +277110,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_p16", + "name": "vreinterpret_f64_p64", "arguments": [ - "poly16x4_t a" + "poly64x1_t a" ], "return_type": { - "value": "int64x1_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -80867,20 +277133,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_p64", + "name": "vreinterpret_f64_p8", "arguments": [ - "poly64x1_t a" + "poly8x8_t a" ], "return_type": { - "value": "int64x1_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.8B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -80891,21 +277156,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_p8", + "name": "vreinterpret_f64_s16", "arguments": [ - "poly8x8_t a" + "int16x4_t a" ], "return_type": { - "value": "int64x1_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vd.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -80916,21 +277179,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_s16", + "name": "vreinterpret_f64_s32", "arguments": [ - "int16x4_t a" + "int32x2_t a" ], "return_type": { - "value": "int64x1_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -80941,21 +277202,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_s32", + "name": "vreinterpret_f64_s64", "arguments": [ - "int32x2_t a" + "int64x1_t a" ], "return_type": { - "value": "int64x1_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -80966,12 +277225,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_s8", + "name": "vreinterpret_f64_s8", "arguments": [ "int8x8_t a" ], "return_type": { - "value": "int64x1_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { @@ -80979,8 +277238,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -80991,12 +277248,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_u16", + "name": "vreinterpret_f64_u16", "arguments": [ "uint16x4_t a" ], "return_type": { - "value": "int64x1_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { @@ -81004,8 +277261,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -81016,12 +277271,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_u32", + "name": "vreinterpret_f64_u32", "arguments": [ "uint32x2_t a" ], "return_type": { - "value": "int64x1_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { @@ -81029,8 +277284,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -81041,12 +277294,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_u64", + "name": "vreinterpret_f64_u64", "arguments": [ "uint64x1_t a" ], "return_type": { - "value": "int64x1_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { @@ -81054,8 +277307,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -81066,12 +277317,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_u8", + "name": "vreinterpret_f64_u8", "arguments": [ "uint8x8_t a" ], "return_type": { - "value": "int64x1_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { @@ -81079,8 +277330,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -81091,12 +277340,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_f16", + "name": "vreinterpret_p16_f16", "arguments": [ "float16x4_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { @@ -81116,12 +277365,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_f32", + "name": "vreinterpret_p16_f32", "arguments": [ "float32x2_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { @@ -81141,12 +277390,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_f64", + "name": "vreinterpret_p16_f64", "arguments": [ "float64x1_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { @@ -81164,20 +277413,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_p16", + "name": "vreinterpret_p16_p64", "arguments": [ - "poly16x4_t a" + "poly64x1_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -81189,19 +277437,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_p64", + "name": "vreinterpret_p16_p8", "arguments": [ - "poly64x1_t a" + "poly8x8_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -81213,16 +277462,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_p8", + "name": "vreinterpret_p16_s16", "arguments": [ - "poly8x8_t a" + "int16x4_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vd.4H" } }, "Architectures": [ @@ -81238,16 +277487,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_s16", + "name": "vreinterpret_p16_s32", "arguments": [ - "int16x4_t a" + "int32x2_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.2S" } }, "Architectures": [ @@ -81263,16 +277512,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_s32", + "name": "vreinterpret_p16_s64", "arguments": [ - "int32x2_t a" + "int64x1_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.1D" } }, "Architectures": [ @@ -81288,16 +277537,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_s64", + "name": "vreinterpret_p16_s8", "arguments": [ - "int64x1_t a" + "int8x8_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.8B" } }, "Architectures": [ @@ -81313,12 +277562,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_u16", + "name": "vreinterpret_p16_u16", "arguments": [ "uint16x4_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { @@ -81338,12 +277587,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_u32", + "name": "vreinterpret_p16_u32", "arguments": [ "uint32x2_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { @@ -81363,12 +277612,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_u64", + "name": "vreinterpret_p16_u64", "arguments": [ "uint64x1_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { @@ -81388,12 +277637,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_u8", + "name": "vreinterpret_p16_u8", "arguments": [ "uint8x8_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { @@ -81413,12 +277662,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_f16", + "name": "vreinterpret_p64_f16", "arguments": [ "float16x4_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { @@ -81426,7 +277675,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -81438,12 +277686,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_f32", + "name": "vreinterpret_p64_f32", "arguments": [ "float32x2_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { @@ -81451,7 +277699,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -81463,12 +277710,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_f64", + "name": "vreinterpret_p64_f64", "arguments": [ "float64x1_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { @@ -81486,43 +277733,18 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_p16", + "name": "vreinterpret_p64_p16", "arguments": [ "poly16x4_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { "register": "Vd.4H" } }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "NOP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_p64", - "arguments": [ - "poly64x1_t a" - ], - "return_type": { - "value": "uint16x4_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.1D" - } - }, "Architectures": [ "A32", "A64" @@ -81535,12 +277757,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_p8", + "name": "vreinterpret_p64_p8", "arguments": [ "poly8x8_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { @@ -81548,7 +277770,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -81560,12 +277781,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_s16", + "name": "vreinterpret_p64_s16", "arguments": [ "int16x4_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { @@ -81573,7 +277794,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -81585,12 +277805,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_s32", + "name": "vreinterpret_p64_s32", "arguments": [ "int32x2_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { @@ -81598,7 +277818,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -81610,20 +277829,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_s64", + "name": "vreinterpret_p64_s8", "arguments": [ - "int64x1_t a" + "int8x8_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.8B" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -81635,20 +277853,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_s8", + "name": "vreinterpret_p64_u16", "arguments": [ - "int8x8_t a" + "uint16x4_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vd.4H" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -81660,12 +277877,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_u32", + "name": "vreinterpret_p64_u32", "arguments": [ "uint32x2_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { @@ -81673,7 +277890,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -81685,12 +277901,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_u64", + "name": "vreinterpret_p64_u64", "arguments": [ "uint64x1_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { @@ -81698,7 +277914,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -81710,12 +277925,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_u8", + "name": "vreinterpret_p64_u8", "arguments": [ "uint8x8_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { @@ -81723,7 +277938,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -81735,12 +277949,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_f16", + "name": "vreinterpret_p8_f16", "arguments": [ "float16x4_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { @@ -81760,12 +277974,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_f32", + "name": "vreinterpret_p8_f32", "arguments": [ "float32x2_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { @@ -81785,12 +277999,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_f64", + "name": "vreinterpret_p8_f64", "arguments": [ "float64x1_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { @@ -81808,12 +278022,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_p16", + "name": "vreinterpret_p8_p16", "arguments": [ "poly16x4_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { @@ -81833,12 +278047,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_p64", + "name": "vreinterpret_p8_p64", "arguments": [ "poly64x1_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { @@ -81857,16 +278071,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_p8", + "name": "vreinterpret_p8_s16", "arguments": [ - "poly8x8_t a" + "int16x4_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vd.4H" } }, "Architectures": [ @@ -81882,16 +278096,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_s16", + "name": "vreinterpret_p8_s32", "arguments": [ - "int16x4_t a" + "int32x2_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.2S" } }, "Architectures": [ @@ -81907,16 +278121,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_s32", + "name": "vreinterpret_p8_s64", "arguments": [ - "int32x2_t a" + "int64x1_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.1D" } }, "Architectures": [ @@ -81932,16 +278146,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_s64", + "name": "vreinterpret_p8_s8", "arguments": [ - "int64x1_t a" + "int8x8_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.8B" } }, "Architectures": [ @@ -81957,16 +278171,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_s8", + "name": "vreinterpret_p8_u16", "arguments": [ - "int8x8_t a" + "uint16x4_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vd.4H" } }, "Architectures": [ @@ -81982,16 +278196,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_u16", + "name": "vreinterpret_p8_u32", "arguments": [ - "uint16x4_t a" + "uint32x2_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.2S" } }, "Architectures": [ @@ -82007,12 +278221,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_u64", + "name": "vreinterpret_p8_u64", "arguments": [ "uint64x1_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { @@ -82032,12 +278246,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_u8", + "name": "vreinterpret_p8_u8", "arguments": [ "uint8x8_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { @@ -82057,12 +278271,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_f16", + "name": "vreinterpret_s16_f16", "arguments": [ "float16x4_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { @@ -82082,12 +278296,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_f32", + "name": "vreinterpret_s16_f32", "arguments": [ "float32x2_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { @@ -82107,12 +278321,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_f64", + "name": "vreinterpret_s16_f64", "arguments": [ "float64x1_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { @@ -82130,12 +278344,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_p16", + "name": "vreinterpret_s16_p16", "arguments": [ "poly16x4_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { @@ -82155,12 +278369,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_p64", + "name": "vreinterpret_s16_p64", "arguments": [ "poly64x1_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { @@ -82179,12 +278393,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_p8", + "name": "vreinterpret_s16_p8", "arguments": [ "poly8x8_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { @@ -82204,16 +278418,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_s16", + "name": "vreinterpret_s16_s32", "arguments": [ - "int16x4_t a" + "int32x2_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.2S" } }, "Architectures": [ @@ -82229,16 +278443,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_s32", + "name": "vreinterpret_s16_s64", "arguments": [ - "int32x2_t a" + "int64x1_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.1D" } }, "Architectures": [ @@ -82254,16 +278468,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_s64", + "name": "vreinterpret_s16_s8", "arguments": [ - "int64x1_t a" + "int8x8_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.8B" } }, "Architectures": [ @@ -82279,16 +278493,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_s8", + "name": "vreinterpret_s16_u16", "arguments": [ - "int8x8_t a" + "uint16x4_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vd.4H" } }, "Architectures": [ @@ -82304,16 +278518,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_u16", + "name": "vreinterpret_s16_u32", "arguments": [ - "uint16x4_t a" + "uint32x2_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.2S" } }, "Architectures": [ @@ -82329,16 +278543,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_u32", + "name": "vreinterpret_s16_u64", "arguments": [ - "uint32x2_t a" + "uint64x1_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.1D" } }, "Architectures": [ @@ -82354,12 +278568,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_u8", + "name": "vreinterpret_s16_u8", "arguments": [ "uint8x8_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { @@ -82379,12 +278593,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_f16", + "name": "vreinterpret_s32_f16", "arguments": [ "float16x4_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -82404,12 +278618,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_f32", + "name": "vreinterpret_s32_f32", "arguments": [ "float32x2_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -82429,12 +278643,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_f64", + "name": "vreinterpret_s32_f64", "arguments": [ "float64x1_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -82452,12 +278666,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_p16", + "name": "vreinterpret_s32_p16", "arguments": [ "poly16x4_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -82477,12 +278691,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_p64", + "name": "vreinterpret_s32_p64", "arguments": [ "poly64x1_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -82501,12 +278715,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_p8", + "name": "vreinterpret_s32_p8", "arguments": [ "poly8x8_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -82526,12 +278740,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_s16", + "name": "vreinterpret_s32_s16", "arguments": [ "int16x4_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -82551,37 +278765,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_s32", - "arguments": [ - "int32x2_t a" - ], - "return_type": { - "value": "uint8x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.2S" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "NOP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_s64", + "name": "vreinterpret_s32_s64", "arguments": [ "int64x1_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -82601,12 +278790,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_s8", + "name": "vreinterpret_s32_s8", "arguments": [ "int8x8_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -82626,12 +278815,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_u16", + "name": "vreinterpret_s32_u16", "arguments": [ "uint16x4_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -82651,12 +278840,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_u32", + "name": "vreinterpret_s32_u32", "arguments": [ "uint32x2_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -82676,12 +278865,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_u64", + "name": "vreinterpret_s32_u64", "arguments": [ "uint64x1_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -82701,16 +278890,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_f32", + "name": "vreinterpret_s32_u8", "arguments": [ - "float32x4_t a" + "uint8x8_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.8B" } }, "Architectures": [ @@ -82726,42 +278915,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_f64", - "arguments": [ - "float64x2_t a" - ], - "return_type": { - "value": "float16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "NOP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_p128", + "name": "vreinterpret_s64_f16", "arguments": [ - "poly128_t a" + "float16x4_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1Q" + "register": "Vd.4H" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -82773,16 +278940,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_p16", + "name": "vreinterpret_s64_f32", "arguments": [ - "poly16x8_t a" + "float32x2_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.2S" } }, "Architectures": [ @@ -82798,20 +278965,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_p64", + "name": "vreinterpret_s64_f64", "arguments": [ - "poly64x2_t a" + "float64x1_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.1D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -82822,16 +278988,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_p8", + "name": "vreinterpret_s64_p16", "arguments": [ - "poly8x16_t a" + "poly16x4_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.4H" } }, "Architectures": [ @@ -82847,20 +279013,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_s16", + "name": "vreinterpret_s64_p64", "arguments": [ - "int16x8_t a" + "poly64x1_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -82872,16 +279037,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_s32", + "name": "vreinterpret_s64_p8", "arguments": [ - "int32x4_t a" + "poly8x8_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.8B" } }, "Architectures": [ @@ -82897,16 +279062,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_s64", + "name": "vreinterpret_s64_s16", "arguments": [ - "int64x2_t a" + "int16x4_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.4H" } }, "Architectures": [ @@ -82922,16 +279087,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_s8", + "name": "vreinterpret_s64_s32", "arguments": [ - "int8x16_t a" + "int32x2_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.2S" } }, "Architectures": [ @@ -82947,16 +279112,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_u16", + "name": "vreinterpret_s64_s8", "arguments": [ - "uint16x8_t a" + "int8x8_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.8B" } }, "Architectures": [ @@ -82972,16 +279137,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_u32", + "name": "vreinterpret_s64_u16", "arguments": [ - "uint32x4_t a" + "uint16x4_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.4H" } }, "Architectures": [ @@ -82997,16 +279162,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_u64", + "name": "vreinterpret_s64_u32", "arguments": [ - "uint64x2_t a" + "uint32x2_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.2S" } }, "Architectures": [ @@ -83022,16 +279187,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_u8", + "name": "vreinterpret_s64_u64", "arguments": [ - "uint8x16_t a" + "uint64x1_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.1D" } }, "Architectures": [ @@ -83047,16 +279212,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_f16", + "name": "vreinterpret_s64_u8", "arguments": [ - "float16x8_t a" + "uint8x8_t a" ], "return_type": { - "value": "float32x4_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.8B" } }, "Architectures": [ @@ -83072,39 +279237,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_f64", - "arguments": [ - "float64x2_t a" - ], - "return_type": { - "value": "float32x4_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "NOP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_p16", + "name": "vreinterpret_s8_f16", "arguments": [ - "poly16x8_t a" + "float16x4_t a" ], "return_type": { - "value": "float32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4H" } }, "Architectures": [ @@ -83120,16 +279262,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_p8", + "name": "vreinterpret_s8_f32", "arguments": [ - "poly8x16_t a" + "float32x2_t a" ], "return_type": { - "value": "float32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.2S" } }, "Architectures": [ @@ -83145,21 +279287,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_s16", + "name": "vreinterpret_s8_f64", "arguments": [ - "int16x8_t a" + "float64x1_t a" ], "return_type": { - "value": "float32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -83170,16 +279310,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_s32", + "name": "vreinterpret_s8_p16", "arguments": [ - "int32x4_t a" + "poly16x4_t a" ], "return_type": { - "value": "float32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.4H" } }, "Architectures": [ @@ -83195,20 +279335,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_s64", + "name": "vreinterpret_s8_p64", "arguments": [ - "int64x2_t a" + "poly64x1_t a" ], "return_type": { - "value": "float32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -83220,16 +279359,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_s8", + "name": "vreinterpret_s8_p8", "arguments": [ - "int8x16_t a" + "poly8x8_t a" ], "return_type": { - "value": "float32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.8B" } }, "Architectures": [ @@ -83245,16 +279384,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_u16", + "name": "vreinterpret_s8_s16", "arguments": [ - "uint16x8_t a" + "int16x4_t a" ], "return_type": { - "value": "float32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4H" } }, "Architectures": [ @@ -83270,16 +279409,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_u32", + "name": "vreinterpret_s8_s32", "arguments": [ - "uint32x4_t a" + "int32x2_t a" ], "return_type": { - "value": "float32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.2S" } }, "Architectures": [ @@ -83295,16 +279434,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_u64", + "name": "vreinterpret_s8_s64", "arguments": [ - "uint64x2_t a" + "int64x1_t a" ], "return_type": { - "value": "float32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.1D" } }, "Architectures": [ @@ -83320,16 +279459,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_u8", + "name": "vreinterpret_s8_u16", "arguments": [ - "uint8x16_t a" + "uint16x4_t a" ], "return_type": { - "value": "float32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.4H" } }, "Architectures": [ @@ -83345,19 +279484,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_f16", + "name": "vreinterpret_s8_u32", "arguments": [ - "float16x8_t a" + "uint32x2_t a" ], "return_type": { - "value": "float64x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83368,19 +279509,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_f32", + "name": "vreinterpret_s8_u64", "arguments": [ - "float32x4_t a" + "uint64x1_t a" ], "return_type": { - "value": "float64x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.1D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83391,19 +279534,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_p128", + "name": "vreinterpret_s8_u8", "arguments": [ - "poly128_t a" + "uint8x8_t a" ], "return_type": { - "value": "float64x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1Q" + "register": "Vd.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83414,19 +279559,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_p16", + "name": "vreinterpret_u16_f16", "arguments": [ - "poly16x8_t a" + "float16x4_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83437,19 +279584,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_p64", + "name": "vreinterpret_u16_f32", "arguments": [ - "poly64x2_t a" + "float32x2_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83460,16 +279609,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_p8", + "name": "vreinterpret_u16_f64", "arguments": [ - "poly8x16_t a" + "float64x1_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.1D" } }, "Architectures": [ @@ -83483,19 +279632,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_s16", + "name": "vreinterpret_u16_p16", "arguments": [ - "int16x8_t a" + "poly16x4_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83506,19 +279657,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_s32", + "name": "vreinterpret_u16_p64", "arguments": [ - "int32x4_t a" + "poly64x1_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.1D" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ @@ -83529,19 +279681,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_s64", + "name": "vreinterpret_u16_p8", "arguments": [ - "int64x2_t a" + "poly8x8_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83552,19 +279706,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_s8", + "name": "vreinterpret_u16_s16", "arguments": [ - "int8x16_t a" + "int16x4_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83575,19 +279731,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_u16", + "name": "vreinterpret_u16_s32", "arguments": [ - "uint16x8_t a" + "int32x2_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83598,19 +279756,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_u32", + "name": "vreinterpret_u16_s64", "arguments": [ - "uint32x4_t a" + "int64x1_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.1D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83621,16 +279781,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_u64", + "name": "vreinterpret_u16_s8", "arguments": [ - "uint64x2_t a" + "int8x8_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.8B" } }, "Architectures": [ @@ -83646,19 +279806,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_u8", + "name": "vreinterpret_u16_u32", "arguments": [ - "uint8x16_t a" + "uint32x2_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83669,19 +279831,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_f16", + "name": "vreinterpret_u16_u64", "arguments": [ - "float16x8_t a" + "uint64x1_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.1D" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -83693,19 +279856,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_f32", + "name": "vreinterpret_u16_u8", "arguments": [ - "float32x4_t a" + "uint8x8_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -83717,19 +279881,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_f64", + "name": "vreinterpret_u32_f16", "arguments": [ - "float64x2_t a" + "float16x4_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1Q" + "register": "Vd.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83740,19 +279906,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_p16", + "name": "vreinterpret_u32_f32", "arguments": [ - "poly16x8_t a" + "float32x2_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -83764,20 +279931,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_p8", + "name": "vreinterpret_u32_f64", "arguments": [ - "poly8x16_t a" + "float64x1_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.1D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -83788,19 +279954,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_s16", + "name": "vreinterpret_u32_p16", "arguments": [ - "int16x8_t a" + "poly16x4_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4H" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -83812,16 +279979,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_s32", + "name": "vreinterpret_u32_p64", "arguments": [ - "int32x4_t a" + "poly64x1_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.1D" } }, "Architectures": [ @@ -83836,19 +280003,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_s64", + "name": "vreinterpret_u32_p8", "arguments": [ - "int64x2_t a" + "poly8x8_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1Q" + "register": "Vd.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -83860,19 +280028,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_s8", + "name": "vreinterpret_u32_s16", "arguments": [ - "int8x16_t a" + "int16x4_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.4H" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -83884,19 +280053,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_u16", + "name": "vreinterpret_u32_s32", "arguments": [ - "uint16x8_t a" + "int32x2_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -83908,19 +280078,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_u32", + "name": "vreinterpret_u32_s64", "arguments": [ - "uint32x4_t a" + "int64x1_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.1D" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -83932,19 +280103,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_u64", + "name": "vreinterpret_u32_s8", "arguments": [ - "uint64x2_t a" + "int8x8_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1Q" + "register": "Vd.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -83956,19 +280128,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_u8", + "name": "vreinterpret_u32_u16", "arguments": [ - "uint8x16_t a" + "uint16x4_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.4H" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -83980,16 +280153,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_f16", + "name": "vreinterpret_u32_u64", "arguments": [ - "float16x8_t a" + "uint64x1_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.1D" } }, "Architectures": [ @@ -84005,16 +280178,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_f32", + "name": "vreinterpret_u32_u8", "arguments": [ - "float32x4_t a" + "uint8x8_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.8B" } }, "Architectures": [ @@ -84030,19 +280203,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_f64", + "name": "vreinterpret_u64_f16", "arguments": [ - "float64x2_t a" + "float16x4_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -84053,19 +280228,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_p128", + "name": "vreinterpret_u64_f32", "arguments": [ - "poly128_t a" + "float32x2_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1Q" + "register": "Vd.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -84077,20 +280253,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_p64", + "name": "vreinterpret_u64_f64", "arguments": [ - "poly64x2_t a" + "float64x1_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.1D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -84101,16 +280276,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_p8", + "name": "vreinterpret_u64_p16", "arguments": [ - "poly8x16_t a" + "poly16x4_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.4H" } }, "Architectures": [ @@ -84126,20 +280301,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_s16", + "name": "vreinterpret_u64_p64", "arguments": [ - "int16x8_t a" + "poly64x1_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -84151,16 +280325,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_s32", + "name": "vreinterpret_u64_p8", "arguments": [ - "int32x4_t a" + "poly8x8_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.8B" } }, "Architectures": [ @@ -84176,16 +280350,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_s64", + "name": "vreinterpret_u64_s16", "arguments": [ - "int64x2_t a" + "int16x4_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.4H" } }, "Architectures": [ @@ -84201,16 +280375,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_s8", + "name": "vreinterpret_u64_s32", "arguments": [ - "int8x16_t a" + "int32x2_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.2S" } }, "Architectures": [ @@ -84226,16 +280400,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_u16", + "name": "vreinterpret_u64_s64", "arguments": [ - "uint16x8_t a" + "int64x1_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.1D" } }, "Architectures": [ @@ -84251,16 +280425,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_u32", + "name": "vreinterpret_u64_s8", "arguments": [ - "uint32x4_t a" + "int8x8_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.8B" } }, "Architectures": [ @@ -84276,16 +280450,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_u64", + "name": "vreinterpret_u64_u16", "arguments": [ - "uint64x2_t a" + "uint16x4_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.4H" } }, "Architectures": [ @@ -84301,16 +280475,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_u8", + "name": "vreinterpret_u64_u32", "arguments": [ - "uint8x16_t a" + "uint32x2_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.2S" } }, "Architectures": [ @@ -84326,19 +280500,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_f16", + "name": "vreinterpret_u64_u8", "arguments": [ - "float16x8_t a" + "uint8x8_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -84350,19 +280525,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_f32", + "name": "vreinterpret_u8_f16", "arguments": [ - "float32x4_t a" + "float16x4_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.4H" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -84374,19 +280550,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_f64", + "name": "vreinterpret_u8_f32", "arguments": [ - "float64x2_t a" + "float32x2_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -84397,20 +280575,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_p16", + "name": "vreinterpret_u8_f64", "arguments": [ - "poly16x8_t a" + "float64x1_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.1D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -84421,19 +280598,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_p8", + "name": "vreinterpret_u8_p16", "arguments": [ - "poly8x16_t a" + "poly16x4_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.4H" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -84445,16 +280623,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_s16", + "name": "vreinterpret_u8_p64", "arguments": [ - "int16x8_t a" + "poly64x1_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.1D" } }, "Architectures": [ @@ -84469,19 +280647,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_s32", + "name": "vreinterpret_u8_p8", "arguments": [ - "int32x4_t a" + "poly8x8_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -84493,19 +280672,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_s64", + "name": "vreinterpret_u8_s16", "arguments": [ - "int64x2_t a" + "int16x4_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.4H" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -84517,19 +280697,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_s8", + "name": "vreinterpret_u8_s32", "arguments": [ - "int8x16_t a" + "int32x2_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -84541,19 +280722,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_u16", + "name": "vreinterpret_u8_s64", "arguments": [ - "uint16x8_t a" + "int64x1_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.1D" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -84565,19 +280747,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_u32", + "name": "vreinterpret_u8_s8", "arguments": [ - "uint32x4_t a" + "int8x8_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -84589,19 +280772,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_u64", + "name": "vreinterpret_u8_u16", "arguments": [ - "uint64x2_t a" + "uint16x4_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.4H" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -84613,19 +280797,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_u8", + "name": "vreinterpret_u8_u32", "arguments": [ - "uint8x16_t a" + "uint32x2_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -84637,16 +280822,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_f16", + "name": "vreinterpret_u8_u64", "arguments": [ - "float16x8_t a" + "uint64x1_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.1D" } }, "Architectures": [ @@ -84662,12 +280847,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_f32", + "name": "vreinterpretq_f16_f32", "arguments": [ "float32x4_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { @@ -84687,12 +280872,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_f64", + "name": "vreinterpretq_f16_f64", "arguments": [ "float64x2_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { @@ -84710,12 +280895,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_p128", + "name": "vreinterpretq_f16_p128", "arguments": [ "poly128_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { @@ -84734,12 +280919,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_p16", + "name": "vreinterpretq_f16_p16", "arguments": [ "poly16x8_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { @@ -84759,12 +280944,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_p64", + "name": "vreinterpretq_f16_p64", "arguments": [ "poly64x2_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { @@ -84783,16 +280968,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_s16", + "name": "vreinterpretq_f16_p8", "arguments": [ - "int16x8_t a" + "poly8x16_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.16B" } }, "Architectures": [ @@ -84808,16 +280993,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_s32", + "name": "vreinterpretq_f16_s16", "arguments": [ - "int32x4_t a" + "int16x8_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.8H" } }, "Architectures": [ @@ -84833,16 +281018,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_s64", + "name": "vreinterpretq_f16_s32", "arguments": [ - "int64x2_t a" + "int32x4_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.4S" } }, "Architectures": [ @@ -84858,16 +281043,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_s8", + "name": "vreinterpretq_f16_s64", "arguments": [ - "int8x16_t a" + "int64x2_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.2D" } }, "Architectures": [ @@ -84883,16 +281068,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_u16", + "name": "vreinterpretq_f16_s8", "arguments": [ - "uint16x8_t a" + "int8x16_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.16B" } }, "Architectures": [ @@ -84908,16 +281093,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_u32", + "name": "vreinterpretq_f16_u16", "arguments": [ - "uint32x4_t a" + "uint16x8_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.8H" } }, "Architectures": [ @@ -84933,16 +281118,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_u64", + "name": "vreinterpretq_f16_u32", "arguments": [ - "uint64x2_t a" + "uint32x4_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.4S" } }, "Architectures": [ @@ -84958,16 +281143,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_u8", + "name": "vreinterpretq_f16_u64", "arguments": [ - "uint8x16_t a" + "uint64x2_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.2D" } }, "Architectures": [ @@ -84983,16 +281168,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_f16", + "name": "vreinterpretq_f16_u8", "arguments": [ - "float16x8_t a" + "uint8x16_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.16B" } }, "Architectures": [ @@ -85008,16 +281193,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_f32", + "name": "vreinterpretq_f32_f16", "arguments": [ - "float32x4_t a" + "float16x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.8H" } }, "Architectures": [ @@ -85033,12 +281218,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_f64", + "name": "vreinterpretq_f32_f64", "arguments": [ "float64x2_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { @@ -85056,36 +281241,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_p128", - "arguments": [ - "poly128_t a" - ], - "return_type": { - "value": "int16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.1Q" - } - }, - "Architectures": [ - "A32", - "A64" - ], - "instructions": [ - [ - "NOP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_p16", + "name": "vreinterpretq_f32_p16", "arguments": [ "poly16x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { @@ -85105,19 +281266,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_p64", + "name": "vreinterpretq_f32_p8", "arguments": [ - "poly64x2_t a" + "poly8x16_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.16B" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -85129,16 +281291,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_p8", + "name": "vreinterpretq_f32_s16", "arguments": [ - "poly8x16_t a" + "int16x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.8H" } }, "Architectures": [ @@ -85154,12 +281316,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_s32", + "name": "vreinterpretq_f32_s32", "arguments": [ "int32x4_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { @@ -85179,12 +281341,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_s64", + "name": "vreinterpretq_f32_s64", "arguments": [ "int64x2_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { @@ -85204,12 +281366,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_s8", + "name": "vreinterpretq_f32_s8", "arguments": [ "int8x16_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { @@ -85229,12 +281391,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_u16", + "name": "vreinterpretq_f32_u16", "arguments": [ "uint16x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { @@ -85254,12 +281416,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_u32", + "name": "vreinterpretq_f32_u32", "arguments": [ "uint32x4_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { @@ -85279,12 +281441,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_u64", + "name": "vreinterpretq_f32_u64", "arguments": [ "uint64x2_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { @@ -85304,12 +281466,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_u8", + "name": "vreinterpretq_f32_u8", "arguments": [ "uint8x16_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { @@ -85329,12 +281491,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_f16", + "name": "vreinterpretq_f64_f16", "arguments": [ "float16x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { @@ -85342,8 +281504,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -85354,12 +281514,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_f32", + "name": "vreinterpretq_f64_f32", "arguments": [ "float32x4_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { @@ -85367,8 +281527,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -85379,16 +281537,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_f64", + "name": "vreinterpretq_f64_p128", "arguments": [ - "float64x2_t a" + "poly128_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.1Q" } }, "Architectures": [ @@ -85402,20 +281560,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_p128", + "name": "vreinterpretq_f64_p16", "arguments": [ - "poly128_t a" + "poly16x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1Q" + "register": "Vd.8H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -85426,21 +281583,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_p16", + "name": "vreinterpretq_f64_p64", "arguments": [ - "poly16x8_t a" + "poly64x2_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -85451,20 +281606,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_p64", + "name": "vreinterpretq_f64_p8", "arguments": [ - "poly64x2_t a" + "poly8x16_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -85475,21 +281629,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_p8", + "name": "vreinterpretq_f64_s16", "arguments": [ - "poly8x16_t a" + "int16x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -85500,21 +281652,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_s16", + "name": "vreinterpretq_f64_s32", "arguments": [ - "int16x8_t a" + "int32x4_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -85525,12 +281675,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_s64", + "name": "vreinterpretq_f64_s64", "arguments": [ "int64x2_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { @@ -85538,8 +281688,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -85550,12 +281698,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_s8", + "name": "vreinterpretq_f64_s8", "arguments": [ "int8x16_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { @@ -85563,8 +281711,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -85575,12 +281721,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_u16", + "name": "vreinterpretq_f64_u16", "arguments": [ "uint16x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { @@ -85588,8 +281734,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -85600,12 +281744,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_u32", + "name": "vreinterpretq_f64_u32", "arguments": [ "uint32x4_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { @@ -85613,8 +281757,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -85625,12 +281767,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_u64", + "name": "vreinterpretq_f64_u64", "arguments": [ "uint64x2_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { @@ -85650,12 +281792,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_u8", + "name": "vreinterpretq_f64_u8", "arguments": [ "uint8x16_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { @@ -85663,8 +281805,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -85675,12 +281815,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_f16", + "name": "vreinterpretq_p128_f16", "arguments": [ "float16x8_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { @@ -85688,7 +281828,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -85700,12 +281839,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_f32", + "name": "vreinterpretq_p128_f32", "arguments": [ "float32x4_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { @@ -85713,7 +281852,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -85725,35 +281863,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_f64", + "name": "vreinterpretq_p128_f64", "arguments": [ "float64x2_t a" ], "return_type": { - "value": "int64x2_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "NOP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_p128", - "arguments": [ - "poly128_t a" - ], - "return_type": { - "value": "int64x2_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { @@ -85761,7 +281876,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -85772,12 +281886,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_p16", + "name": "vreinterpretq_p128_p16", "arguments": [ "poly16x8_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { @@ -85785,7 +281899,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -85797,16 +281910,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_p64", + "name": "vreinterpretq_p128_p8", "arguments": [ - "poly64x2_t a" + "poly8x16_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.16B" } }, "Architectures": [ @@ -85821,20 +281934,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_p8", + "name": "vreinterpretq_p128_s16", "arguments": [ - "poly8x16_t a" + "int16x8_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.8H" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -85846,20 +281958,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_s16", + "name": "vreinterpretq_p128_s32", "arguments": [ - "int16x8_t a" + "int32x4_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -85871,20 +281982,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_s32", + "name": "vreinterpretq_p128_s64", "arguments": [ - "int32x4_t a" + "int64x2_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.1Q" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -85896,12 +282006,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_s8", + "name": "vreinterpretq_p128_s8", "arguments": [ "int8x16_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { @@ -85909,7 +282019,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -85921,12 +282030,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_u16", + "name": "vreinterpretq_p128_u16", "arguments": [ "uint16x8_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { @@ -85934,7 +282043,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -85946,12 +282054,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_u32", + "name": "vreinterpretq_p128_u32", "arguments": [ "uint32x4_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { @@ -85959,7 +282067,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -85971,20 +282078,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_u64", + "name": "vreinterpretq_p128_u64", "arguments": [ "uint64x2_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.1Q" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -85996,12 +282102,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_u8", + "name": "vreinterpretq_p128_u8", "arguments": [ "uint8x16_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { @@ -86009,7 +282115,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86021,12 +282126,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_f16", + "name": "vreinterpretq_p16_f16", "arguments": [ "float16x8_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { @@ -86046,12 +282151,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_f32", + "name": "vreinterpretq_p16_f32", "arguments": [ "float32x4_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { @@ -86071,12 +282176,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_f64", + "name": "vreinterpretq_p16_f64", "arguments": [ "float64x2_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { @@ -86094,12 +282199,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_p128", + "name": "vreinterpretq_p16_p128", "arguments": [ "poly128_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { @@ -86118,20 +282223,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_p16", + "name": "vreinterpretq_p16_p64", "arguments": [ - "poly16x8_t a" + "poly64x2_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86143,19 +282247,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_p64", + "name": "vreinterpretq_p16_p8", "arguments": [ - "poly64x2_t a" + "poly8x16_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.16B" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -86167,16 +282272,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_p8", + "name": "vreinterpretq_p16_s16", "arguments": [ - "poly8x16_t a" + "int16x8_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.8H" } }, "Architectures": [ @@ -86192,16 +282297,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_s16", + "name": "vreinterpretq_p16_s32", "arguments": [ - "int16x8_t a" + "int32x4_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4S" } }, "Architectures": [ @@ -86217,16 +282322,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_s32", + "name": "vreinterpretq_p16_s64", "arguments": [ - "int32x4_t a" + "int64x2_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.2D" } }, "Architectures": [ @@ -86242,16 +282347,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_s64", + "name": "vreinterpretq_p16_s8", "arguments": [ - "int64x2_t a" + "int8x16_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.16B" } }, "Architectures": [ @@ -86267,12 +282372,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_u16", + "name": "vreinterpretq_p16_u16", "arguments": [ "uint16x8_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { @@ -86292,12 +282397,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_u32", + "name": "vreinterpretq_p16_u32", "arguments": [ "uint32x4_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { @@ -86317,12 +282422,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_u64", + "name": "vreinterpretq_p16_u64", "arguments": [ "uint64x2_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { @@ -86342,12 +282447,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_u8", + "name": "vreinterpretq_p16_u8", "arguments": [ "uint8x16_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { @@ -86367,12 +282472,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_f16", + "name": "vreinterpretq_p64_f16", "arguments": [ "float16x8_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { @@ -86380,7 +282485,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86392,12 +282496,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_f32", + "name": "vreinterpretq_p64_f32", "arguments": [ "float32x4_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { @@ -86405,7 +282509,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86417,12 +282520,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_f64", + "name": "vreinterpretq_p64_f64", "arguments": [ "float64x2_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { @@ -86440,36 +282543,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_p128", - "arguments": [ - "poly128_t a" - ], - "return_type": { - "value": "uint16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.1Q" - } - }, - "Architectures": [ - "A32", - "A64" - ], - "instructions": [ - [ - "NOP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_p16", + "name": "vreinterpretq_p64_p16", "arguments": [ "poly16x8_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { @@ -86477,7 +282556,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86489,16 +282567,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_p64", + "name": "vreinterpretq_p64_p8", "arguments": [ - "poly64x2_t a" + "poly8x16_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.16B" } }, "Architectures": [ @@ -86513,20 +282591,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_p8", + "name": "vreinterpretq_p64_s16", "arguments": [ - "poly8x16_t a" + "int16x8_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.8H" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86538,20 +282615,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_s16", + "name": "vreinterpretq_p64_s32", "arguments": [ - "int16x8_t a" + "int32x4_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86563,20 +282639,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_s32", + "name": "vreinterpretq_p64_s64", "arguments": [ - "int32x4_t a" + "int64x2_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86588,20 +282663,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_s64", + "name": "vreinterpretq_p64_s8", "arguments": [ - "int64x2_t a" + "int8x16_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.16B" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86613,20 +282687,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_s8", + "name": "vreinterpretq_p64_u16", "arguments": [ - "int8x16_t a" + "uint16x8_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.8H" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86638,12 +282711,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_u32", + "name": "vreinterpretq_p64_u32", "arguments": [ "uint32x4_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { @@ -86651,7 +282724,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86663,12 +282735,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_u64", + "name": "vreinterpretq_p64_u64", "arguments": [ "uint64x2_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { @@ -86676,7 +282748,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86688,12 +282759,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_u8", + "name": "vreinterpretq_p64_u8", "arguments": [ "uint8x16_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { @@ -86701,7 +282772,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86713,12 +282783,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_f16", + "name": "vreinterpretq_p8_f16", "arguments": [ "float16x8_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { @@ -86738,12 +282808,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_f32", + "name": "vreinterpretq_p8_f32", "arguments": [ "float32x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { @@ -86763,12 +282833,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_f64", + "name": "vreinterpretq_p8_f64", "arguments": [ "float64x2_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { @@ -86786,12 +282856,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_p128", + "name": "vreinterpretq_p8_p128", "arguments": [ "poly128_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { @@ -86810,12 +282880,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_p16", + "name": "vreinterpretq_p8_p16", "arguments": [ "poly16x8_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { @@ -86835,12 +282905,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_p64", + "name": "vreinterpretq_p8_p64", "arguments": [ "poly64x2_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { @@ -86859,16 +282929,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_p8", + "name": "vreinterpretq_p8_s16", "arguments": [ - "poly8x16_t a" + "int16x8_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.8H" } }, "Architectures": [ @@ -86884,16 +282954,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_s16", + "name": "vreinterpretq_p8_s32", "arguments": [ - "int16x8_t a" + "int32x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4S" } }, "Architectures": [ @@ -86909,16 +282979,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_s32", + "name": "vreinterpretq_p8_s64", "arguments": [ - "int32x4_t a" + "int64x2_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.2D" } }, "Architectures": [ @@ -86934,16 +283004,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_s64", + "name": "vreinterpretq_p8_s8", "arguments": [ - "int64x2_t a" + "int8x16_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.16B" } }, "Architectures": [ @@ -86959,16 +283029,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_s8", + "name": "vreinterpretq_p8_u16", "arguments": [ - "int8x16_t a" + "uint16x8_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.8H" } }, "Architectures": [ @@ -86984,16 +283054,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_u16", + "name": "vreinterpretq_p8_u32", "arguments": [ - "uint16x8_t a" + "uint32x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4S" } }, "Architectures": [ @@ -87009,12 +283079,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_u64", + "name": "vreinterpretq_p8_u64", "arguments": [ "uint64x2_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { @@ -87034,12 +283104,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_u8", + "name": "vreinterpretq_p8_u8", "arguments": [ "uint8x16_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { @@ -87059,12 +283129,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_f16", + "name": "vreinterpretq_s16_f16", "arguments": [ "float16x8_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -87084,12 +283154,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_f32", + "name": "vreinterpretq_s16_f32", "arguments": [ "float32x4_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -87109,12 +283179,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_f64", + "name": "vreinterpretq_s16_f64", "arguments": [ "float64x2_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -87132,12 +283202,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_p128", + "name": "vreinterpretq_s16_p128", "arguments": [ "poly128_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -87156,12 +283226,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_p16", + "name": "vreinterpretq_s16_p16", "arguments": [ "poly16x8_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -87181,12 +283251,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_p64", + "name": "vreinterpretq_s16_p64", "arguments": [ "poly64x2_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -87205,12 +283275,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_p8", + "name": "vreinterpretq_s16_p8", "arguments": [ "poly8x16_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -87230,16 +283300,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_s16", + "name": "vreinterpretq_s16_s32", "arguments": [ - "int16x8_t a" + "int32x4_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4S" } }, "Architectures": [ @@ -87255,16 +283325,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_s32", + "name": "vreinterpretq_s16_s64", "arguments": [ - "int32x4_t a" + "int64x2_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.2D" } }, "Architectures": [ @@ -87280,16 +283350,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_s64", + "name": "vreinterpretq_s16_s8", "arguments": [ - "int64x2_t a" + "int8x16_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.16B" } }, "Architectures": [ @@ -87305,16 +283375,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_s8", + "name": "vreinterpretq_s16_u16", "arguments": [ - "int8x16_t a" + "uint16x8_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.8H" } }, "Architectures": [ @@ -87330,16 +283400,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_u16", + "name": "vreinterpretq_s16_u32", "arguments": [ - "uint16x8_t a" + "uint32x4_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4S" } }, "Architectures": [ @@ -87355,16 +283425,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_u32", + "name": "vreinterpretq_s16_u64", "arguments": [ - "uint32x4_t a" + "uint64x2_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.2D" } }, "Architectures": [ @@ -87380,12 +283450,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_u8", + "name": "vreinterpretq_s16_u8", "arguments": [ "uint8x16_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -87405,12 +283475,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_f16", + "name": "vreinterpretq_s32_f16", "arguments": [ "float16x8_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -87430,12 +283500,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_f32", + "name": "vreinterpretq_s32_f32", "arguments": [ "float32x4_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -87455,12 +283525,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_f64", + "name": "vreinterpretq_s32_f64", "arguments": [ "float64x2_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -87478,12 +283548,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_p128", + "name": "vreinterpretq_s32_p128", "arguments": [ "poly128_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -87502,12 +283572,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_p16", + "name": "vreinterpretq_s32_p16", "arguments": [ "poly16x8_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -87527,12 +283597,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_p64", + "name": "vreinterpretq_s32_p64", "arguments": [ "poly64x2_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -87551,12 +283621,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_p8", + "name": "vreinterpretq_s32_p8", "arguments": [ "poly8x16_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -87576,12 +283646,87 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_s16", + "name": "vreinterpretq_s32_s16", "arguments": [ "int16x8_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int32x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_s32_s64", + "arguments": [ + "int64x2_t a" + ], + "return_type": { + "value": "int32x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.2D" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_s32_s8", + "arguments": [ + "int8x16_t a" + ], + "return_type": { + "value": "int32x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.16B" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_s32_u16", + "arguments": [ + "uint16x8_t a" + ], + "return_type": { + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -87601,12 +283746,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_s32", + "name": "vreinterpretq_s32_u32", "arguments": [ - "int32x4_t a" + "uint32x4_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -87626,12 +283771,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_s64", + "name": "vreinterpretq_s32_u64", "arguments": [ - "int64x2_t a" + "uint64x2_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -87651,12 +283796,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_s8", + "name": "vreinterpretq_s32_u8", "arguments": [ - "int8x16_t a" + "uint8x16_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -87676,12 +283821,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_u16", + "name": "vreinterpretq_s64_f16", "arguments": [ - "uint16x8_t a" + "float16x8_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { @@ -87701,12 +283846,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_u32", + "name": "vreinterpretq_s64_f32", "arguments": [ - "uint32x4_t a" + "float32x4_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { @@ -87726,12 +283871,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_u64", + "name": "vreinterpretq_s64_f64", "arguments": [ - "uint64x2_t a" + "float64x2_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { @@ -87739,8 +283884,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -87751,41 +283894,40 @@ }, { "SIMD_ISA": "Neon", - "name": "vrev16_p8", + "name": "vreinterpretq_s64_p128", "arguments": [ - "poly8x8_t vec" + "poly128_t a" ], "return_type": { - "value": "poly8x8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8B" + "a": { + "register": "Vd.1Q" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "REV16" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev16_s8", + "name": "vreinterpretq_s64_p16", "arguments": [ - "int8x8_t vec" + "poly16x8_t a" ], "return_type": { - "value": "int8x8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8B" + "a": { + "register": "Vd.8H" } }, "Architectures": [ @@ -87795,47 +283937,46 @@ ], "instructions": [ [ - "REV16" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev16_u8", + "name": "vreinterpretq_s64_p64", "arguments": [ - "uint8x8_t vec" + "poly64x2_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8B" + "a": { + "register": "Vd.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "REV16" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev16q_p8", + "name": "vreinterpretq_s64_p8", "arguments": [ - "poly8x16_t vec" + "poly8x16_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.16B" + "a": { + "register": "Vd.16B" } }, "Architectures": [ @@ -87845,22 +283986,22 @@ ], "instructions": [ [ - "REV16" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev16q_s8", + "name": "vreinterpretq_s64_s16", "arguments": [ - "int8x16_t vec" + "int16x8_t a" ], "return_type": { - "value": "int8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.16B" + "a": { + "register": "Vd.8H" } }, "Architectures": [ @@ -87870,22 +284011,22 @@ ], "instructions": [ [ - "REV16" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev16q_u8", + "name": "vreinterpretq_s64_s32", "arguments": [ - "uint8x16_t vec" + "int32x4_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.16B" + "a": { + "register": "Vd.4S" } }, "Architectures": [ @@ -87895,22 +284036,22 @@ ], "instructions": [ [ - "REV16" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32_p16", + "name": "vreinterpretq_s64_s8", "arguments": [ - "poly16x4_t vec" + "int8x16_t a" ], "return_type": { - "value": "poly16x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.4H" + "a": { + "register": "Vd.16B" } }, "Architectures": [ @@ -87920,22 +284061,22 @@ ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32_p8", + "name": "vreinterpretq_s64_u16", "arguments": [ - "poly8x8_t vec" + "uint16x8_t a" ], "return_type": { - "value": "poly8x8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8B" + "a": { + "register": "Vd.8H" } }, "Architectures": [ @@ -87945,22 +284086,22 @@ ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32_s16", + "name": "vreinterpretq_s64_u32", "arguments": [ - "int16x4_t vec" + "uint32x4_t a" ], "return_type": { - "value": "int16x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.4H" + "a": { + "register": "Vd.4S" } }, "Architectures": [ @@ -87970,22 +284111,22 @@ ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32_s8", + "name": "vreinterpretq_s64_u64", "arguments": [ - "int8x8_t vec" + "uint64x2_t a" ], "return_type": { - "value": "int8x8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8B" + "a": { + "register": "Vd.2D" } }, "Architectures": [ @@ -87995,22 +284136,22 @@ ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32_u16", + "name": "vreinterpretq_s64_u8", "arguments": [ - "uint16x4_t vec" + "uint8x16_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.4H" + "a": { + "register": "Vd.16B" } }, "Architectures": [ @@ -88020,22 +284161,22 @@ ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32_u8", + "name": "vreinterpretq_s8_f16", "arguments": [ - "uint8x8_t vec" + "float16x8_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8B" + "a": { + "register": "Vd.8H" } }, "Architectures": [ @@ -88045,22 +284186,22 @@ ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32q_p16", + "name": "vreinterpretq_s8_f32", "arguments": [ - "poly16x8_t vec" + "float32x4_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8H" + "a": { + "register": "Vd.4S" } }, "Architectures": [ @@ -88070,72 +284211,69 @@ ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32q_p8", + "name": "vreinterpretq_s8_f64", "arguments": [ - "poly8x16_t vec" + "float64x2_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.16B" + "a": { + "register": "Vd.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32q_s16", + "name": "vreinterpretq_s8_p128", "arguments": [ - "int16x8_t vec" + "poly128_t a" ], "return_type": { - "value": "int16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8H" + "a": { + "register": "Vd.1Q" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32q_s8", + "name": "vreinterpretq_s8_p16", "arguments": [ - "int8x16_t vec" + "poly16x8_t a" ], "return_type": { "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.16B" + "a": { + "register": "Vd.8H" } }, "Architectures": [ @@ -88145,47 +284283,46 @@ ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32q_u16", + "name": "vreinterpretq_s8_p64", "arguments": [ - "uint16x8_t vec" + "poly64x2_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8H" + "a": { + "register": "Vd.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32q_u8", + "name": "vreinterpretq_s8_p8", "arguments": [ - "uint8x16_t vec" + "poly8x16_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.16B" + "a": { + "register": "Vd.16B" } }, "Architectures": [ @@ -88195,22 +284332,22 @@ ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64_f16", + "name": "vreinterpretq_s8_s16", "arguments": [ - "float16x4_t vec" + "int16x8_t a" ], "return_type": { - "value": "float16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.4H" + "a": { + "register": "Vd.8H" } }, "Architectures": [ @@ -88220,22 +284357,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64_f32", + "name": "vreinterpretq_s8_s32", "arguments": [ - "float32x2_t vec" + "int32x4_t a" ], "return_type": { - "value": "float32x2_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.2S" + "a": { + "register": "Vd.4S" } }, "Architectures": [ @@ -88245,22 +284382,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64_p16", + "name": "vreinterpretq_s8_s64", "arguments": [ - "poly16x4_t vec" + "int64x2_t a" ], "return_type": { - "value": "poly16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.4H" + "a": { + "register": "Vd.2D" } }, "Architectures": [ @@ -88270,22 +284407,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64_p8", + "name": "vreinterpretq_s8_u16", "arguments": [ - "poly8x8_t vec" + "uint16x8_t a" ], "return_type": { - "value": "poly8x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8B" + "a": { + "register": "Vd.8H" } }, "Architectures": [ @@ -88295,22 +284432,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64_s16", + "name": "vreinterpretq_s8_u32", "arguments": [ - "int16x4_t vec" + "uint32x4_t a" ], "return_type": { - "value": "int16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.4H" + "a": { + "register": "Vd.4S" } }, "Architectures": [ @@ -88320,22 +284457,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64_s32", + "name": "vreinterpretq_s8_u64", "arguments": [ - "int32x2_t vec" + "uint64x2_t a" ], "return_type": { - "value": "int32x2_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.2S" + "a": { + "register": "Vd.2D" } }, "Architectures": [ @@ -88345,22 +284482,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64_s8", + "name": "vreinterpretq_s8_u8", "arguments": [ - "int8x8_t vec" + "uint8x16_t a" ], "return_type": { - "value": "int8x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8B" + "a": { + "register": "Vd.16B" } }, "Architectures": [ @@ -88370,22 +284507,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64_u16", + "name": "vreinterpretq_u16_f16", "arguments": [ - "uint16x4_t vec" + "float16x8_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.4H" + "a": { + "register": "Vd.8H" } }, "Architectures": [ @@ -88395,22 +284532,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64_u32", + "name": "vreinterpretq_u16_f32", "arguments": [ - "uint32x2_t vec" + "float32x4_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.2S" + "a": { + "register": "Vd.4S" } }, "Architectures": [ @@ -88420,72 +284557,69 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64_u8", + "name": "vreinterpretq_u16_f64", "arguments": [ - "uint8x8_t vec" + "float64x2_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8B" + "a": { + "register": "Vd.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64q_f16", + "name": "vreinterpretq_u16_p128", "arguments": [ - "float16x8_t vec" + "poly128_t a" ], "return_type": { - "value": "float16x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8H" + "a": { + "register": "Vd.1Q" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64q_f32", + "name": "vreinterpretq_u16_p16", "arguments": [ - "float32x4_t vec" + "poly16x8_t a" ], "return_type": { - "value": "float32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.4S" + "a": { + "register": "Vd.8H" } }, "Architectures": [ @@ -88495,47 +284629,46 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64q_p16", + "name": "vreinterpretq_u16_p64", "arguments": [ - "poly16x8_t vec" + "poly64x2_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8H" + "a": { + "register": "Vd.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64q_p8", + "name": "vreinterpretq_u16_p8", "arguments": [ - "poly8x16_t vec" + "poly8x16_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.16B" + "a": { + "register": "Vd.16B" } }, "Architectures": [ @@ -88545,22 +284678,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64q_s16", + "name": "vreinterpretq_u16_s16", "arguments": [ - "int16x8_t vec" + "int16x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8H" + "a": { + "register": "Vd.8H" } }, "Architectures": [ @@ -88570,22 +284703,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64q_s32", + "name": "vreinterpretq_u16_s32", "arguments": [ - "int32x4_t vec" + "int32x4_t a" ], "return_type": { - "value": "int32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.4S" + "a": { + "register": "Vd.4S" } }, "Architectures": [ @@ -88595,22 +284728,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64q_s8", + "name": "vreinterpretq_u16_s64", "arguments": [ - "int8x16_t vec" + "int64x2_t a" ], "return_type": { - "value": "int8x16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.16B" + "a": { + "register": "Vd.2D" } }, "Architectures": [ @@ -88620,22 +284753,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64q_u16", + "name": "vreinterpretq_u16_s8", "arguments": [ - "uint16x8_t vec" + "int8x16_t a" ], "return_type": { "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8H" + "a": { + "register": "Vd.16B" } }, "Architectures": [ @@ -88645,22 +284778,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64q_u32", + "name": "vreinterpretq_u16_u32", "arguments": [ - "uint32x4_t vec" + "uint32x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.4S" + "a": { + "register": "Vd.4S" } }, "Architectures": [ @@ -88670,22 +284803,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64q_u8", + "name": "vreinterpretq_u16_u64", "arguments": [ - "uint8x16_t vec" + "uint64x2_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.16B" + "a": { + "register": "Vd.2D" } }, "Architectures": [ @@ -88695,26 +284828,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhadd_s16", + "name": "vreinterpretq_u16_u8", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "uint8x16_t a" ], "return_type": { - "value": "int16x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "register": "Vd.16B" } }, "Architectures": [ @@ -88724,26 +284853,22 @@ ], "instructions": [ [ - "SRHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhadd_s32", + "name": "vreinterpretq_u32_f16", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "float16x8_t a" ], "return_type": { - "value": "int32x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" + "register": "Vd.8H" } }, "Architectures": [ @@ -88753,26 +284878,22 @@ ], "instructions": [ [ - "SRHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhadd_s8", + "name": "vreinterpretq_u32_f32", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "float32x4_t a" ], "return_type": { - "value": "int8x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" + "register": "Vd.4S" } }, "Architectures": [ @@ -88782,84 +284903,69 @@ ], "instructions": [ [ - "SRHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhadd_u16", + "name": "vreinterpretq_u32_f64", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "float64x2_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "register": "Vd.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhadd_u32", + "name": "vreinterpretq_u32_p128", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "poly128_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" + "register": "Vd.1Q" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "URHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhadd_u8", + "name": "vreinterpretq_u32_p16", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "poly16x8_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" + "register": "Vd.8H" } }, "Architectures": [ @@ -88869,55 +284975,46 @@ ], "instructions": [ [ - "URHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhaddq_s16", + "name": "vreinterpretq_u32_p64", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "poly64x2_t a" ], "return_type": { - "value": "int16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Vd.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SRHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhaddq_s32", + "name": "vreinterpretq_u32_p8", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "poly8x16_t a" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Vd.16B" } }, "Architectures": [ @@ -88927,26 +285024,22 @@ ], "instructions": [ [ - "SRHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhaddq_s8", + "name": "vreinterpretq_u32_s16", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "int16x8_t a" ], "return_type": { - "value": "int8x16_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "register": "Vd.8H" } }, "Architectures": [ @@ -88956,26 +285049,22 @@ ], "instructions": [ [ - "SRHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhaddq_u16", + "name": "vreinterpretq_u32_s32", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "int32x4_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Vd.4S" } }, "Architectures": [ @@ -88985,26 +285074,22 @@ ], "instructions": [ [ - "URHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhaddq_u32", + "name": "vreinterpretq_u32_s64", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "int64x2_t a" ], "return_type": { "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Vd.2D" } }, "Architectures": [ @@ -89014,26 +285099,22 @@ ], "instructions": [ [ - "URHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhaddq_u8", + "name": "vreinterpretq_u32_s8", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "int8x16_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "register": "Vd.16B" } }, "Architectures": [ @@ -89043,137 +285124,147 @@ ], "instructions": [ [ - "URHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd32x_f32", + "name": "vreinterpretq_u32_u16", "arguments": [ - "float32x2_t a" + "uint16x8_t a" ], "return_type": { - "value": "float32x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn" + "register": "Vd.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINT32X" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd32x_f64", + "name": "vreinterpretq_u32_u64", "arguments": [ - "float64x1_t a" + "uint64x2_t a" ], "return_type": { - "value": "float64x1_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINT32X" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd32xq_f32", + "name": "vreinterpretq_u32_u8", "arguments": [ - "float32x4_t a" + "uint8x16_t a" ], "return_type": { - "value": "float32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn" + "register": "Vd.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINT32X" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd32xq_f64", + "name": "vreinterpretq_u64_f16", "arguments": [ - "float64x2_t a" + "float16x8_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn" + "register": "Vd.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINT32X" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd32z_f32", + "name": "vreinterpretq_u64_f32", "arguments": [ - "float32x2_t a" + "float32x4_t a" ], "return_type": { - "value": "float32x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn" + "register": "Vd.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINT32Z" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd32z_f64", + "name": "vreinterpretq_u64_f64", "arguments": [ - "float64x1_t a" + "float64x2_t a" ], "return_type": { - "value": "float64x1_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.2D" } }, "Architectures": [ @@ -89181,347 +285272,368 @@ ], "instructions": [ [ - "FRINT32Z" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd32zq_f32", + "name": "vreinterpretq_u64_p128", "arguments": [ - "float32x4_t a" + "poly128_t a" ], "return_type": { - "value": "float32x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn" + "register": "Vd.1Q" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FRINT32Z" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd32zq_f64", + "name": "vreinterpretq_u64_p16", "arguments": [ - "float64x2_t a" + "poly16x8_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn" + "register": "Vd.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINT32Z" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd64x_f32", + "name": "vreinterpretq_u64_p64", "arguments": [ - "float32x2_t a" + "poly64x2_t a" ], "return_type": { - "value": "float32x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn" + "register": "Vd.2D" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FRINT64X" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd64x_f64", + "name": "vreinterpretq_u64_p8", "arguments": [ - "float64x1_t a" + "poly8x16_t a" ], "return_type": { - "value": "float64x1_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINT64X" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd64xq_f32", + "name": "vreinterpretq_u64_s16", "arguments": [ - "float32x4_t a" + "int16x8_t a" ], "return_type": { - "value": "float32x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn" + "register": "Vd.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINT64X" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd64xq_f64", + "name": "vreinterpretq_u64_s32", "arguments": [ - "float64x2_t a" + "int32x4_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn" + "register": "Vd.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINT64X" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd64z_f32", + "name": "vreinterpretq_u64_s64", "arguments": [ - "float32x2_t a" + "int64x2_t a" ], "return_type": { - "value": "float32x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn" + "register": "Vd.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINT64Z" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd64z_f64", + "name": "vreinterpretq_u64_s8", "arguments": [ - "float64x1_t a" + "int8x16_t a" ], "return_type": { - "value": "float64x1_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINT64Z" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd64zq_f32", + "name": "vreinterpretq_u64_u16", "arguments": [ - "float32x4_t a" + "uint16x8_t a" ], "return_type": { - "value": "float32x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn" + "register": "Vd.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINT64Z" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd64zq_f64", + "name": "vreinterpretq_u64_u32", "arguments": [ - "float64x2_t a" + "uint32x4_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn" + "register": "Vd.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINT64Z" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd_f16", + "name": "vreinterpretq_u64_u8", "arguments": [ - "float16x4_t a" + "uint8x16_t a" ], "return_type": { - "value": "float16x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.16B" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FRINTZ" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd_f32", + "name": "vreinterpretq_u8_f16", "arguments": [ - "float32x2_t a" + "float16x8_t a" ], "return_type": { - "value": "float32x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.8H" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FRINTZ" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd_f64", + "name": "vreinterpretq_u8_f32", "arguments": [ - "float64x1_t a" + "float32x4_t a" ], "return_type": { - "value": "float64x1_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINTZ" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnda_f16", + "name": "vreinterpretq_u8_f64", "arguments": [ - "float16x4_t a" + "float64x2_t a" ], "return_type": { - "value": "float16x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.2D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FRINTA" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnda_f32", + "name": "vreinterpretq_u8_p128", "arguments": [ - "float32x2_t a" + "poly128_t a" ], "return_type": { - "value": "float32x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.1Q" } }, "Architectures": [ @@ -89530,45 +285642,47 @@ ], "instructions": [ [ - "FRINTA" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnda_f64", + "name": "vreinterpretq_u8_p16", "arguments": [ - "float64x1_t a" + "poly16x8_t a" ], "return_type": { - "value": "float64x1_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINTA" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndah_f16", + "name": "vreinterpretq_u8_p64", "arguments": [ - "float16_t a" + "poly64x2_t a" ], "return_type": { - "value": "float16_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vd.2D" } }, "Architectures": [ @@ -89577,1046 +285691,1072 @@ ], "instructions": [ [ - "FRINTA" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndaq_f16", + "name": "vreinterpretq_u8_p8", "arguments": [ - "float16x8_t a" + "poly8x16_t a" ], "return_type": { - "value": "float16x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.16B" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FRINTA" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndaq_f32", + "name": "vreinterpretq_u8_s16", "arguments": [ - "float32x4_t a" + "int16x8_t a" ], "return_type": { - "value": "float32x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.8H" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FRINTA" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndaq_f64", + "name": "vreinterpretq_u8_s32", "arguments": [ - "float64x2_t a" + "int32x4_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINTA" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndh_f16", + "name": "vreinterpretq_u8_s64", "arguments": [ - "float16_t a" + "int64x2_t a" ], "return_type": { - "value": "float16_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vd.2D" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FRINTZ" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndi_f16", + "name": "vreinterpretq_u8_s8", "arguments": [ - "float16x4_t a" + "int8x16_t a" ], "return_type": { - "value": "float16x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINTI" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndi_f32", + "name": "vreinterpretq_u8_u16", "arguments": [ - "float32x2_t a" + "uint16x8_t a" ], "return_type": { - "value": "float32x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.8H" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FRINTI" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndi_f64", + "name": "vreinterpretq_u8_u32", "arguments": [ - "float64x1_t a" + "uint32x4_t a" ], "return_type": { - "value": "float64x1_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.4S" } }, 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"instructions": [ [ - "FRINTP" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndpq_f32", + "name": "vrev64_s32", "arguments": [ - "float32x4_t a" + "int32x2_t vec" ], "return_type": { - "value": "float32x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "vec": { + "register": "Vn.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FRINTP" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndpq_f64", + "name": "vrev64_s8", "arguments": [ - "float64x2_t a" + "int8x8_t vec" ], "return_type": { - "value": "float64x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "vec": { + "register": "Vn.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINTP" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndq_f16", + "name": "vrev64_u16", "arguments": [ - "float16x8_t a" + "uint16x4_t vec" ], "return_type": { - "value": "float16x8_t" + "value": "uint16x4_t" }, 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"Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINTX" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndxh_f16", + "name": "vrev64q_p8", "arguments": [ - "float16_t a" + "poly8x16_t vec" ], "return_type": { - "value": "float16_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "vec": { + "register": "Vn.16B" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FRINTX" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndxq_f16", + "name": "vrev64q_s16", "arguments": [ - "float16x8_t a" + "int16x8_t vec" ], "return_type": { - "value": "float16x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { - "a": { + "vec": { "register": "Vn.8H" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FRINTX" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndxq_f32", + "name": "vrev64q_s32", "arguments": [ - "float32x4_t a" + "int32x4_t vec" ], "return_type": { - "value": "float32x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { - "a": { + "vec": { "register": "Vn.4S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FRINTX" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vrndxq_f64", - "arguments": [ - "float64x2_t a" - ], - "return_type": { - "value": "float64x2_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "FRINTX" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshl_s16", + "name": "vrev64q_s8", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "int8x16_t vec" ], "return_type": { - "value": "int16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "vec": { + "register": "Vn.16B" } }, "Architectures": [ @@ -90626,26 +286766,22 @@ ], "instructions": [ [ - "SRSHL" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshl_s32", + "name": "vrev64q_u16", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "uint16x8_t vec" ], "return_type": { - "value": "int32x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" + "vec": { + "register": "Vn.8H" } }, "Architectures": [ @@ -90655,26 +286791,22 @@ ], "instructions": [ [ - "SRSHL" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshl_s64", + "name": "vrev64q_u32", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "uint32x4_t vec" ], "return_type": { - "value": "int64x1_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" - }, - "b": { - "register": "Dm" + "vec": { + "register": "Vn.4S" } }, "Architectures": [ @@ -90684,26 +286816,22 @@ ], "instructions": [ [ - "SRSHL" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshl_s8", + "name": "vrev64q_u8", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "uint8x16_t vec" ], "return_type": { - "value": "int8x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" + "vec": { + "register": "Vn.16B" } }, "Architectures": [ @@ -90713,19 +286841,19 @@ ], "instructions": [ [ - "SRSHL" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshl_u16", + "name": "vrhadd_s16", "arguments": [ - "uint16x4_t a", + "int16x4_t a", "int16x4_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { @@ -90742,19 +286870,19 @@ ], "instructions": [ [ - "URSHL" + "SRHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshl_u32", + "name": "vrhadd_s32", "arguments": [ - "uint32x2_t a", + "int32x2_t a", "int32x2_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -90771,26 +286899,26 @@ ], "instructions": [ [ - "URSHL" + "SRHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshl_u64", + "name": "vrhadd_s8", "arguments": [ - "uint64x1_t a", - "int64x1_t b" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "uint64x1_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.8B" }, "b": { - "register": "Dm" + "register": "Vm.8B" } }, "Architectures": [ @@ -90800,26 +286928,26 @@ ], "instructions": [ [ - "URSHL" + "SRHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshl_u8", + "name": "vrhadd_u16", "arguments": [ - "uint8x8_t a", - "int8x8_t b" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4H" }, "b": { - "register": "Vm.8B" + "register": "Vm.4H" } }, "Architectures": [ @@ -90829,67 +286957,71 @@ ], "instructions": [ [ - "URSHL" + "URHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshld_s64", + "name": "vrhadd_u32", "arguments": [ - "int64_t a", - "int64_t b" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "int64_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.2S" }, "b": { - "register": "Dm" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SRSHL" + "URHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshld_u64", + "name": "vrhadd_u8", "arguments": [ - "uint64_t a", - "int64_t b" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "uint64_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.8B" }, "b": { - "register": "Dm" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "URSHL" + "URHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshlq_s16", + "name": "vrhaddq_s16", "arguments": [ "int16x8_t a", "int16x8_t b" @@ -90912,13 +287044,13 @@ ], "instructions": [ [ - "SRSHL" + "SRHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshlq_s32", + "name": "vrhaddq_s32", "arguments": [ "int32x4_t a", "int32x4_t b" @@ -90941,26 +287073,26 @@ ], "instructions": [ [ - "SRSHL" + "SRHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshlq_s64", + "name": "vrhaddq_s8", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.16B" }, "b": { - "register": "Vm.2D" + "register": "Vm.16B" } }, "Architectures": [ @@ -90970,26 +287102,26 @@ ], "instructions": [ [ - "SRSHL" + "SRHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshlq_s8", + "name": "vrhaddq_u16", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int8x16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, "b": { - "register": "Vm.16B" + "register": "Vm.8H" } }, "Architectures": [ @@ -90999,26 +287131,26 @@ ], "instructions": [ [ - "SRSHL" + "URHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshlq_u16", + "name": "vrhaddq_u32", "arguments": [ - "uint16x8_t a", - "int16x8_t b" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4S" }, "b": { - "register": "Vm.8H" + "register": "Vm.4S" } }, "Architectures": [ @@ -91028,26 +287160,26 @@ ], "instructions": [ [ - "URSHL" + "URHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshlq_u32", + "name": "vrhaddq_u8", "arguments": [ - "uint32x4_t a", - "int32x4_t b" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.16B" }, "b": { - "register": "Vm.4S" + "register": "Vm.16B" } }, "Architectures": [ @@ -91057,325 +287189,252 @@ ], "instructions": [ [ - "URSHL" + "URHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshlq_u64", + "name": "vrnd32x_f32", "arguments": [ - "uint64x2_t a", - "int64x2_t b" + "float32x2_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "register": "Vn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URSHL" + "FRINT32X" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshlq_u8", + "name": "vrnd32x_f64", "arguments": [ - "uint8x16_t a", - "int8x16_t b" + "float64x1_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URSHL" + "FRINT32X" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshr_n_s16", + "name": "vrnd32xq_f32", "arguments": [ - "int16x4_t a", - "const int n" + "float32x4_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "n": { - "minimum": 1, - "maximum": 16 + "register": "Vn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SRSHR" + "FRINT32X" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshr_n_s32", + "name": "vrnd32xq_f64", "arguments": [ - "int32x2_t a", - "const int n" + "float64x2_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "n": { - "minimum": 1, - "maximum": 32 + "register": "Vn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SRSHR" + "FRINT32X" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshr_n_s64", + "name": "vrnd32z_f32", "arguments": [ - "int64x1_t a", - "const int n" + "float32x2_t a" ], "return_type": { - "value": "int64x1_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "n": { - "minimum": 1, - "maximum": 64 + "register": "Vn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SRSHR" + "FRINT32Z" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshr_n_s8", + "name": "vrnd32z_f64", "arguments": [ - "int8x8_t a", - "const int n" + "float64x1_t a" ], "return_type": { - "value": "int8x8_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" - }, - "n": { - "minimum": 1, - "maximum": 8 + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SRSHR" + "FRINT32Z" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshr_n_u16", + "name": "vrnd32zq_f32", "arguments": [ - "uint16x4_t a", - "const int n" + "float32x4_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "n": { - "minimum": 1, - "maximum": 16 + "register": "Vn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URSHR" + "FRINT32Z" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshr_n_u32", + "name": "vrnd32zq_f64", "arguments": [ - "uint32x2_t a", - "const int n" + "float64x2_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "n": { - "minimum": 1, - "maximum": 32 + "register": "Vn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URSHR" + "FRINT32Z" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshr_n_u64", + "name": "vrnd64x_f32", "arguments": [ - "uint64x1_t a", - "const int n" + "float32x2_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "n": { - "minimum": 1, - "maximum": 64 + "register": "Vn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URSHR" + "FRINT64X" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshr_n_u8", + "name": "vrnd64x_f64", "arguments": [ - "uint8x8_t a", - "const int n" + "float64x1_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" - }, - "n": { - "minimum": 1, - "maximum": 8 + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URSHR" + "FRINT64X" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrd_n_s64", + "name": "vrnd64xq_f32", "arguments": [ - "int64_t a", - "const int n" + "float32x4_t a" ], "return_type": { - "value": "int64_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "n": { - "minimum": 1, - "maximum": 64 + "register": "Vn" } }, "Architectures": [ @@ -91383,27 +287442,22 @@ ], "instructions": [ [ - "SRSHR" + "FRINT64X" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrd_n_u64", + "name": "vrnd64xq_f64", "arguments": [ - "uint64_t a", - "const int n" + "float64x2_t a" ], "return_type": { - "value": "uint64_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "n": { - "minimum": 1, - "maximum": 64 + "register": "Vn" } }, "Architectures": [ @@ -91411,31 +287465,22 @@ ], "instructions": [ [ - "URSHR" + "FRINT64X" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_high_n_s16", + "name": "vrnd64z_f32", "arguments": [ - "int8x8_t r", - "int16x8_t a", - "const int n" + "float32x2_t a" ], "return_type": { - "value": "int8x16_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "n": { - "minimum": 1, - "maximum": 8 - }, - "r": { - "register": "Vd.8B" + "register": "Vn" } }, "Architectures": [ @@ -91443,31 +287488,22 @@ ], "instructions": [ [ - "RSHRN2" + "FRINT64Z" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_high_n_s32", + "name": "vrnd64z_f64", "arguments": [ - "int16x4_t r", - "int32x4_t a", - "const int n" + "float64x1_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "n": { - "minimum": 1, - "maximum": 16 - }, - "r": { - "register": "Vd.4H" + "register": "Dn" } }, "Architectures": [ @@ -91475,31 +287511,22 @@ ], "instructions": [ [ - "RSHRN2" + "FRINT64Z" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_high_n_s64", + "name": "vrnd64zq_f32", "arguments": [ - "int32x2_t r", - "int64x2_t a", - "const int n" + "float32x4_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "n": { - "minimum": 1, - "maximum": 32 - }, - "r": { - "register": "Vd.2S" + "register": "Vn" } }, "Architectures": [ @@ -91507,31 +287534,22 @@ ], "instructions": [ [ - "RSHRN2" + "FRINT64Z" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_high_n_u16", + "name": "vrnd64zq_f64", "arguments": [ - "uint8x8_t r", - "uint16x8_t a", - "const int n" + "float64x2_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "n": { - "minimum": 1, - "maximum": 8 - }, - "r": { - "register": "Vd.8B" + "register": "Vn" } }, "Architectures": [ @@ -91539,506 +287557,400 @@ ], "instructions": [ [ - "RSHRN2" + "FRINT64Z" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_high_n_u32", + "name": "vrnd_f16", "arguments": [ - "uint16x4_t r", - "uint32x4_t a", - "const int n" + "float16x4_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "n": { - "minimum": 1, - "maximum": 16 - }, - "r": { - "register": "Vd.4H" + "register": "Vn.4H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "RSHRN2" + "FRINTZ" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_high_n_u64", + "name": "vrnd_f32", "arguments": [ - "uint32x2_t r", - "uint64x2_t a", - "const int n" + "float32x2_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "n": { - "minimum": 1, - "maximum": 32 - }, - "r": { - "register": "32(Vd)" + "register": "Vn.2S" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "RSHRN2" + "FRINTZ" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_n_s16", + "name": "vrnd_f64", "arguments": [ - "int16x8_t a", - "const int n" + "float64x1_t a" ], "return_type": { - "value": "int8x8_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "n": { - "minimum": 1, - "maximum": 8 + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "RSHRN" + "FRINTZ" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_n_s32", + "name": "vrnda_f16", "arguments": [ - "int32x4_t a", - "const int n" + "float16x4_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "n": { - "minimum": 1, - "maximum": 16 + "register": "Vn.4H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "RSHRN" + "FRINTA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_n_s64", + "name": "vrnda_f32", "arguments": [ - "int64x2_t a", - "const int n" + "float32x2_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" - }, - "n": { - "minimum": 1, - "maximum": 32 + "a": { + "register": "Vn.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "RSHRN" + "FRINTA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_n_u16", + "name": "vrnda_f64", "arguments": [ - "uint16x8_t a", - "const int n" + "float64x1_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "n": { - "minimum": 1, - "maximum": 8 + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "RSHRN" + "FRINTA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_n_u32", + "name": "vrndah_f16", "arguments": [ - "uint32x4_t a", - "const int n" + "float16_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "n": { - "minimum": 1, - "maximum": 16 + "register": "Hn" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "RSHRN" + "FRINTA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_n_u64", + "name": "vrndaq_f16", "arguments": [ - "uint64x2_t a", - "const int n" + "float16x8_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "n": { - "minimum": 1, - "maximum": 32 + "register": "Vn.8H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "RSHRN" + "FRINTA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrq_n_s16", + "name": "vrndaq_f32", "arguments": [ - "int16x8_t a", - "const int n" + "float32x4_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "n": { - "minimum": 1, - "maximum": 16 + "register": "Vn.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SRSHR" + "FRINTA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrq_n_s32", + "name": "vrndaq_f64", "arguments": [ - "int32x4_t a", - "const int n" + "float64x2_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "n": { - "minimum": 1, - "maximum": 32 + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SRSHR" + "FRINTA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrq_n_s64", + "name": "vrndh_f16", "arguments": [ - "int64x2_t a", - "const int n" + "float16_t a" ], "return_type": { - "value": "int64x2_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "n": { - "minimum": 1, - "maximum": 64 + "register": "Hn" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SRSHR" + "FRINTZ" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrq_n_s8", + "name": "vrndi_f16", "arguments": [ - "int8x16_t a", - "const int n" + "float16x4_t a" ], "return_type": { - "value": "int8x16_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" - }, - "n": { - "minimum": 1, - "maximum": 8 + "register": "Vn.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SRSHR" + "FRINTI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrq_n_u16", + "name": "vrndi_f32", "arguments": [ - "uint16x8_t a", - "const int n" + "float32x2_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "n": { - "minimum": 1, - "maximum": 16 + "register": "Vn.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "URSHR" + "FRINTI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrq_n_u32", + "name": "vrndi_f64", "arguments": [ - "uint32x4_t a", - "const int n" + "float64x1_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "n": { - "minimum": 1, - "maximum": 32 + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URSHR" + "FRINTI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrq_n_u64", + "name": "vrndih_f16", "arguments": [ - "uint64x2_t a", - "const int n" + "float16_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "n": { - "minimum": 1, - "maximum": 64 + "register": "Hn" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "URSHR" + "FRINTI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrq_n_u8", + "name": "vrndiq_f16", "arguments": [ - "uint8x16_t a", - "const int n" + "float16x8_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" - }, - "n": { - "minimum": 1, - "maximum": 8 + "register": "Vn.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URSHR" + "FRINTI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrte_f16", + "name": "vrndiq_f32", "arguments": [ - "float16x4_t a" + "float32x4_t a" ], "return_type": { - "value": "float16x4_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.4S" } }, "Architectures": [ @@ -92047,66 +287959,65 @@ ], "instructions": [ [ - "FRSQRTE" + "FRINTI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrte_f32", + "name": "vrndiq_f64", "arguments": [ - "float32x2_t a" + "float64x2_t a" ], "return_type": { - "value": "float32x2_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FRSQRTE" + "FRINTI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrte_f64", + "name": "vrndm_f16", "arguments": [ - "float64x1_t a" + "float16x4_t a" ], "return_type": { - "value": "float64x1_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.4H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FRSQRTE" + "FRINTM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrte_u32", + "name": "vrndm_f32", "arguments": [ - "uint32x2_t a" + "float32x2_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { @@ -92114,24 +288025,23 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "URSQRTE" + "FRINTM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrted_f64", + "name": "vrndm_f64", "arguments": [ - "float64_t a" + "float64x1_t a" ], "return_type": { - "value": "float64_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { @@ -92143,13 +288053,13 @@ ], "instructions": [ [ - "FRSQRTE" + "FRINTM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrteh_f16", + "name": "vrndmh_f16", "arguments": [ "float16_t a" ], @@ -92162,17 +288072,18 @@ } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FRSQRTE" + "FRINTM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrteq_f16", + "name": "vrndmq_f16", "arguments": [ "float16x8_t a" ], @@ -92190,13 +288101,13 @@ ], "instructions": [ [ - "FRSQRTE" + "FRINTM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrteq_f32", + "name": "vrndmq_f32", "arguments": [ "float32x4_t a" ], @@ -92209,19 +288120,18 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "FRSQRTE" + "FRINTM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrteq_f64", + "name": "vrndmq_f64", "arguments": [ "float64x2_t a" ], @@ -92238,74 +288148,70 @@ ], "instructions": [ [ - "FRSQRTE" + "FRINTM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrteq_u32", + "name": "vrndn_f16", "arguments": [ - "uint32x4_t a" + "float16x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.4H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "URSQRTE" + "FRINTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrtes_f32", + "name": "vrndn_f32", "arguments": [ - "float32_t a" + "float32x2_t a" ], "return_type": { - "value": "float32_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vn.2S" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FRSQRTE" + "FRINTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrts_f16", + "name": "vrndn_f64", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "float64x1_t a" ], "return_type": { - "value": "float16x4_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "register": "Dn" } }, "Architectures": [ @@ -92314,136 +288220,118 @@ ], "instructions": [ [ - "FRSQRTS" + "FRINTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrts_f32", + "name": "vrndnh_f16", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "float16_t a" ], "return_type": { - "value": "float32x2_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" + "register": "Hn" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "FRSQRTS" + "FRINTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrts_f64", + "name": "vrndnq_f16", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "float16x8_t a" ], "return_type": { - "value": "float64x1_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "b": { - "register": "Dm" + "register": "Vn.8H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FRSQRTS" + "FRINTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrtsd_f64", + "name": "vrndnq_f32", "arguments": [ - "float64_t a", - "float64_t b" + "float32x4_t a" ], "return_type": { - "value": "float64_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "b": { - "register": "Dm" + "register": "Vn.4S" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FRSQRTS" + "FRINTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrtsh_f16", + "name": "vrndnq_f64", "arguments": [ - "float16_t a", - "float16_t b" + "float64x2_t a" ], "return_type": { - "value": "float16_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" - }, - "b": { - "register": "Hm" + "register": "Vn.2D" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FRSQRTS" + "FRINTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrtsq_f16", + "name": "vrndns_f32", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "float32_t a" ], "return_type": { - "value": "float16x8_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Sn" } }, "Architectures": [ @@ -92452,82 +288340,70 @@ ], "instructions": [ [ - "FRSQRTS" + "FRINTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrtsq_f32", + "name": "vrndp_f16", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "float16x4_t a" ], "return_type": { - "value": "float32x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Vn.4H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "FRSQRTS" + "FRINTP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrtsq_f64", + "name": "vrndp_f32", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "float32x2_t a" ], "return_type": { - "value": "float64x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "register": "Vn.2S" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FRSQRTS" + "FRINTP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrtss_f32", + "name": "vrndp_f64", "arguments": [ - "float32_t a", - "float32_t b" + "float64x1_t a" ], "return_type": { - "value": "float32_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" - }, - "b": { - "register": "Sm" + "register": "Dn" } }, "Architectures": [ @@ -92535,335 +288411,236 @@ ], "instructions": [ [ - "FRSQRTS" + "FRINTP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsra_n_s16", + "name": "vrndph_f16", "arguments": [ - "int16x4_t a", - "int16x4_t b", - "const int n" + "float16_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" - }, - "n": { - "minimum": 1, - "maximum": 16 + "register": "Hn" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SRSRA" + "FRINTP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsra_n_s32", + "name": "vrndpq_f16", "arguments": [ - "int32x2_t a", - "int32x2_t b", - "const int n" + "float16x8_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.2S" - }, - "n": { - "minimum": 1, - "maximum": 32 + "register": "Vn.8H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SRSRA" + "FRINTP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsra_n_s64", + "name": "vrndpq_f32", "arguments": [ - "int64x1_t a", - "int64x1_t b", - "const int n" + "float32x4_t a" ], "return_type": { - "value": "int64x1_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { - "register": "Dn" - }, - "n": { - "minimum": 1, - "maximum": 64 + "register": "Vn.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SRSRA" + "FRINTP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsra_n_s8", + "name": "vrndpq_f64", "arguments": [ - "int8x8_t a", - "int8x8_t b", - "const int n" + "float64x2_t a" ], "return_type": { - "value": "int8x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "b": { - "register": "Vn.8B" - }, - "n": { - "minimum": 1, - "maximum": 8 + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SRSRA" + "FRINTP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsra_n_u16", + "name": "vrndq_f16", "arguments": [ - "uint16x4_t a", - "uint16x4_t b", - "const int n" + "float16x8_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" - }, - "n": { - "minimum": 1, - "maximum": 16 + "register": "Vn.8H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "URSRA" + "FRINTZ" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsra_n_u32", + "name": "vrndq_f32", "arguments": [ - "uint32x2_t a", - "uint32x2_t b", - "const int n" + "float32x4_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.2S" - }, - "n": { - "minimum": 1, - "maximum": 32 + "register": "Vn.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "URSRA" + "FRINTZ" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsra_n_u64", + "name": "vrndq_f64", "arguments": [ - "uint64x1_t a", - "uint64x1_t b", - "const int n" + "float64x2_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { - "register": "Dn" - }, - "n": { - "minimum": 1, - "maximum": 64 + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URSRA" + "FRINTZ" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsra_n_u8", + "name": "vrndx_f16", "arguments": [ - "uint8x8_t a", - "uint8x8_t b", - "const int n" + "float16x4_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "b": { - "register": "Vn.8B" - }, - "n": { - "minimum": 1, - "maximum": 8 + "register": "Vn.4H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "URSRA" + "FRINTX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsrad_n_s64", + "name": "vrndx_f32", "arguments": [ - "int64_t a", - "int64_t b", - "const int n" + "float32x2_t a" ], "return_type": { - "value": "int64_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { - "register": "Dn" - }, - "n": { - "minimum": 1, - "maximum": 64 + "register": "Vn.2S" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "SRSRA" + "FRINTX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsrad_n_u64", + "name": "vrndx_f64", "arguments": [ - "uint64_t a", - "uint64_t b", - "const int n" + "float64x1_t a" ], "return_type": { - "value": "uint64_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { "register": "Dn" - }, - "n": { - "minimum": 1, - "maximum": 64 } }, "Architectures": [ @@ -92871,167 +288648,121 @@ ], "instructions": [ [ - "URSRA" + "FRINTX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsraq_n_s16", + "name": "vrndxh_f16", "arguments": [ - "int16x8_t a", - "int16x8_t b", - "const int n" + "float16_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.8H" - }, - "n": { - "minimum": 1, - "maximum": 16 + "register": "Hn" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SRSRA" + "FRINTX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsraq_n_s32", + "name": "vrndxq_f16", "arguments": [ - "int32x4_t a", - "int32x4_t b", - "const int n" + "float16x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4S" - }, - "n": { - "minimum": 1, - "maximum": 32 + "register": "Vn.8H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SRSRA" + "FRINTX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsraq_n_s64", + "name": "vrndxq_f32", "arguments": [ - "int64x2_t a", - "int64x2_t b", - "const int n" + "float32x4_t a" ], "return_type": { - "value": "int64x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.2D" - }, - "n": { - "minimum": 1, - "maximum": 64 + "register": "Vn.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SRSRA" + "FRINTX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsraq_n_s8", + "name": "vrndxq_f64", "arguments": [ - "int8x16_t a", - "int8x16_t b", - "const int n" + "float64x2_t a" ], "return_type": { - "value": "int8x16_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "b": { - "register": "Vn.16B" - }, - "n": { - "minimum": 1, - "maximum": 8 + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SRSRA" + "FRINTX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsraq_n_u16", + "name": "vrshl_s16", "arguments": [ - "uint16x8_t a", - "uint16x8_t b", - "const int n" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vn.4H" }, "b": { - "register": "Vn.8H" - }, - "n": { - "minimum": 1, - "maximum": 16 + "register": "Vm.4H" } }, "Architectures": [ @@ -93041,31 +288772,26 @@ ], "instructions": [ [ - "URSRA" + "SRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsraq_n_u32", + "name": "vrshl_s32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "const int n" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.2S" }, "b": { - "register": "Vn.4S" - }, - "n": { - "minimum": 1, - "maximum": 32 + "register": "Vm.2S" } }, "Architectures": [ @@ -93075,31 +288801,26 @@ ], "instructions": [ [ - "URSRA" + "SRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsraq_n_u64", + "name": "vrshl_s64", "arguments": [ - "uint64x2_t a", - "uint64x2_t b", - "const int n" + "int64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Dn" }, "b": { - "register": "Vn.2D" - }, - "n": { - "minimum": 1, - "maximum": 64 + "register": "Dm" } }, "Architectures": [ @@ -93109,31 +288830,26 @@ ], "instructions": [ [ - "URSRA" + "SRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsraq_n_u8", + "name": "vrshl_s8", "arguments": [ - "uint8x16_t a", - "uint8x16_t b", - "const int n" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vn.8B" }, "b": { - "register": "Vn.16B" - }, - "n": { - "minimum": 1, - "maximum": 8 + "register": "Vm.8B" } }, "Architectures": [ @@ -93143,154 +288859,142 @@ ], "instructions": [ [ - "URSRA" + "SRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_high_s16", + "name": "vrshl_u16", "arguments": [ - "int8x8_t r", - "int16x8_t a", - "int16x8_t b" + "uint16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "int8x16_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4H" }, "b": { - "register": "Vm.8H" - }, - "r": { - "register": "Vd.8B" + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "RSUBHN2" + "URSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_high_s32", + "name": "vrshl_u32", "arguments": [ - "int16x4_t r", - "int32x4_t a", - "int32x4_t b" + "uint32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "int16x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2S" }, "b": { - "register": "Vm.4S" - }, - "r": { - "register": "Vd.4H" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "RSUBHN2" + "URSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_high_s64", + "name": "vrshl_u64", "arguments": [ - "int32x2_t r", - "int64x2_t a", - "int64x2_t b" + "uint64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Dn" }, "b": { - "register": "Vm.2D" - }, - "r": { - "register": "Vd.2S" + "register": "Dm" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "RSUBHN2" + "URSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_high_u16", + "name": "vrshl_u8", "arguments": [ - "uint8x8_t r", - "uint16x8_t a", - "uint16x8_t b" + "uint8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" }, "b": { - "register": "Vm.8H" - }, - "r": { - "register": "Vd.8B" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "RSUBHN2" + "URSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_high_u32", + "name": "vrshld_s64", "arguments": [ - "uint16x4_t r", - "uint32x4_t a", - "uint32x4_t b" + "int64_t a", + "int64_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Dn" }, "b": { - "register": "Vm.4S" - }, - "r": { - "register": "Vd.4H" + "register": "Dm" } }, "Architectures": [ @@ -93298,30 +289002,26 @@ ], "instructions": [ [ - "RSUBHN2" + "SRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_high_u64", + "name": "vrshld_u64", "arguments": [ - "uint32x2_t r", - "uint64x2_t a", - "uint64x2_t b" + "uint64_t a", + "int64_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Dn" }, "b": { - "register": "Vm.2D" - }, - "r": { - "register": "Vd.2S" + "register": "Dm" } }, "Architectures": [ @@ -93329,19 +289029,19 @@ ], "instructions": [ [ - "RSUBHN2" + "URSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_s16", + "name": "vrshlq_s16", "arguments": [ "int16x8_t a", "int16x8_t b" ], "return_type": { - "value": "int8x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -93358,19 +289058,19 @@ ], "instructions": [ [ - "RSUBHN" + "SRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_s32", + "name": "vrshlq_s32", "arguments": [ "int32x4_t a", "int32x4_t b" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -93387,19 +289087,19 @@ ], "instructions": [ [ - "RSUBHN" + "SRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_s64", + "name": "vrshlq_s64", "arguments": [ "int64x2_t a", "int64x2_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { @@ -93416,19 +289116,48 @@ ], "instructions": [ [ - "RSUBHN" + "SRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_u16", + "name": "vrshlq_s8", + "arguments": [ + "int8x16_t a", + "int8x16_t b" + ], + "return_type": { + "value": "int8x16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SRSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vrshlq_u16", "arguments": [ "uint16x8_t a", - "uint16x8_t b" + "int16x8_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { @@ -93445,19 +289174,19 @@ ], "instructions": [ [ - "RSUBHN" + "URSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_u32", + "name": "vrshlq_u32", "arguments": [ "uint32x4_t a", - "uint32x4_t b" + "int32x4_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { @@ -93474,19 +289203,19 @@ ], "instructions": [ [ - "RSUBHN" + "URSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_u64", + "name": "vrshlq_u64", "arguments": [ "uint64x2_t a", - "uint64x2_t b" + "int64x2_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { @@ -93503,31 +289232,26 @@ ], "instructions": [ [ - "RSUBHN" + "URSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_f16", + "name": "vrshlq_u8", "arguments": [ - "float16_t a", - "float16x4_t v", - "const int lane" + "uint8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "float16x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "VnH" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Vn.16B" }, - "v": { - "register": "Vd.4H" + "b": { + "register": "Vm.16B" } }, "Architectures": [ @@ -93537,31 +289261,57 @@ ], "instructions": [ [ - "MOV" + "URSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_f32", + "name": "vrshr_n_s16", "arguments": [ - "float32_t a", - "float32x2_t v", - "const int lane" + "int16x4_t a", + "const int n" ], "return_type": { - "value": "float32x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" + "register": "Vn.4H" }, - "lane": { - "minimum": 0, - "maximum": 1 + "n": { + "minimum": 1, + "maximum": 16 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SRSHR" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vrshr_n_s32", + "arguments": [ + "int32x2_t a", + "const int n" + ], + "return_type": { + "value": "int32x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2S" }, - "v": { - "register": "Vd.2S" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -93571,63 +289321,57 @@ ], "instructions": [ [ - "MOV" + "SRSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_f64", + "name": "vrshr_n_s64", "arguments": [ - "float64_t a", - "float64x1_t v", - "const int lane" + "int64x1_t a", + "const int n" ], "return_type": { - "value": "float64x1_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 0 + "register": "Dn" }, - "v": { - "register": "Vd.1D" + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "MOV" + "SRSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_p16", + "name": "vrshr_n_s8", "arguments": [ - "poly16_t a", - "poly16x4_t v", - "const int lane" + "int8x8_t a", + "const int n" ], "return_type": { - "value": "poly16x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Vn.8B" }, - "v": { - "register": "Vd.4H" + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -93637,64 +289381,57 @@ ], "instructions": [ [ - "MOV" + "SRSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_p64", + "name": "vrshr_n_u16", "arguments": [ - "poly64_t a", - "poly64x1_t v", - "const int lane" + "uint16x4_t a", + "const int n" ], "return_type": { - "value": "poly64x1_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 0 + "register": "Vn.4H" }, - "v": { - "register": "Vd.1D" + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "MOV" + "URSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_p8", + "name": "vrshr_n_u32", "arguments": [ - "poly8_t a", - "poly8x8_t v", - "const int lane" + "uint32x2_t a", + "const int n" ], "return_type": { - "value": "poly8x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 7 + "register": "Vn.2S" }, - "v": { - "register": "Vd.8B" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -93704,31 +289441,27 @@ ], "instructions": [ [ - "MOV" + "URSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_s16", + "name": "vrshr_n_u64", "arguments": [ - "int16_t a", - "int16x4_t v", - "const int lane" + "uint64x1_t a", + "const int n" ], "return_type": { - "value": "int16x4_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Dn" }, - "v": { - "register": "Vd.4H" + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -93738,31 +289471,27 @@ ], "instructions": [ [ - "MOV" + "URSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_s32", + "name": "vrshr_n_u8", "arguments": [ - "int32_t a", - "int32x2_t v", - "const int lane" + "uint8x8_t a", + "const int n" ], "return_type": { - "value": "int32x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 1 + "register": "Vn.8B" }, - "v": { - "register": "Vd.2S" + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -93772,335 +289501,305 @@ ], "instructions": [ [ - "MOV" + "URSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_s64", + "name": "vrshrd_n_s64", "arguments": [ "int64_t a", - "int64x1_t v", - "const int lane" + "const int n" ], "return_type": { - "value": "int64x1_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 0 + "register": "Dn" }, - "v": { - "register": "Vd.1D" + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MOV" + "SRSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_s8", + "name": "vrshrd_n_u64", "arguments": [ - "int8_t a", - "int8x8_t v", - "const int lane" + "uint64_t a", + "const int n" ], "return_type": { - "value": "int8x8_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 7 + "register": "Dn" }, - "v": { - "register": "Vd.8B" + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MOV" + "URSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_u16", + "name": "vrshrn_high_n_s16", "arguments": [ - "uint16_t a", - "uint16x4_t v", - "const int lane" + "int8x8_t r", + "int16x8_t a", + "const int n" ], "return_type": { - "value": "uint16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" + "register": "Vn.8H" }, - "lane": { - "minimum": 0, - "maximum": 3 + "n": { + "minimum": 1, + "maximum": 8 }, - "v": { - "register": "Vd.4H" + "r": { + "register": "Vd.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MOV" + "RSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_u32", + "name": "vrshrn_high_n_s32", "arguments": [ - "uint32_t a", - "uint32x2_t v", - "const int lane" + "int16x4_t r", + "int32x4_t a", + "const int n" ], "return_type": { - "value": "uint32x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" + "register": "Vn.4S" }, - "lane": { - "minimum": 0, - "maximum": 1 + "n": { + "minimum": 1, + "maximum": 16 }, - "v": { - "register": "Vd.2S" + "r": { + "register": "Vd.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MOV" + "RSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_u64", + "name": "vrshrn_high_n_s64", "arguments": [ - "uint64_t a", - "uint64x1_t v", - "const int lane" + "int32x2_t r", + "int64x2_t a", + "const int n" ], "return_type": { - "value": "uint64x1_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" + "register": "Vn.2D" }, - "lane": { - "minimum": 0, - "maximum": 0 + "n": { + "minimum": 1, + "maximum": 32 }, - "v": { - "register": "Vd.1D" + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MOV" + "RSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_u8", + "name": "vrshrn_high_n_u16", "arguments": [ - "uint8_t a", - "uint8x8_t v", - "const int lane" + "uint8x8_t r", + "uint16x8_t a", + "const int n" ], "return_type": { - "value": "uint8x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" + "register": "Vn.8H" }, - "lane": { - "minimum": 0, - "maximum": 7 + "n": { + "minimum": 1, + "maximum": 8 }, - "v": { + "r": { "register": "Vd.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MOV" + "RSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_f16", + "name": "vrshrn_high_n_u32", "arguments": [ - "float16_t a", - "float16x8_t v", - "const int lane" + "uint16x4_t r", + "uint32x4_t a", + "const int n" ], "return_type": { - "value": "float16x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "VnH" + "register": "Vn.4S" }, - "lane": { - "minimum": 0, - "maximum": 7 + "n": { + "minimum": 1, + "maximum": 16 }, - "v": { - "register": "Vd.8H" + "r": { + "register": "Vd.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MOV" + "RSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_f32", + "name": "vrshrn_high_n_u64", "arguments": [ - "float32_t a", - "float32x4_t v", - "const int lane" + "uint32x2_t r", + "uint64x2_t a", + "const int n" ], "return_type": { - "value": "float32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" + "register": "Vn.2D" }, - "lane": { - "minimum": 0, - "maximum": 3 + "n": { + "minimum": 1, + "maximum": 32 }, - "v": { - "register": "Vd.4S" + "r": { + "register": "32(Vd)" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MOV" + "RSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_f64", + "name": "vrshrn_n_s16", "arguments": [ - "float64_t a", - "float64x2_t v", - "const int lane" + "int16x8_t a", + "const int n" ], "return_type": { - "value": "float64x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 1 + "register": "Vn.8H" }, - "v": { - "register": "Vd.2D" + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "MOV" + "RSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_p16", + "name": "vrshrn_n_s32", "arguments": [ - "poly16_t a", - "poly16x8_t v", - "const int lane" + "int32x4_t a", + "const int n" ], "return_type": { - "value": "poly16x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 7 + "register": "Vn.4S" }, - "v": { - "register": "Vd.8H" + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -94110,64 +289809,57 @@ ], "instructions": [ [ - "MOV" + "RSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_p64", + "name": "vrshrn_n_s64", "arguments": [ - "poly64_t a", - "poly64x2_t v", - "const int lane" + "int64x2_t a", + "const int n" ], "return_type": { - "value": "poly64x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 1 + "register": "Vn.2D" }, - "v": { - "register": "Vd.2D" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "MOV" + "RSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_p8", + "name": "vrshrn_n_u16", "arguments": [ - "poly8_t a", - "poly8x16_t v", - "const int lane" + "uint16x8_t a", + "const int n" ], "return_type": { - "value": "poly8x16_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 15 + "register": "Vn.8H" }, - "v": { - "register": "Vd.16B" + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -94177,31 +289869,27 @@ ], "instructions": [ [ - "MOV" + "RSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_s16", + "name": "vrshrn_n_u32", "arguments": [ - "int16_t a", - "int16x8_t v", - "const int lane" + "uint32x4_t a", + "const int n" ], "return_type": { - "value": "int16x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 7 + "register": "Vn.4S" }, - "v": { - "register": "Vd.8H" + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -94211,31 +289899,27 @@ ], "instructions": [ [ - "MOV" + "RSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_s32", + "name": "vrshrn_n_u64", "arguments": [ - "int32_t a", - "int32x4_t v", - "const int lane" + "uint64x2_t a", + "const int n" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Vn.2D" }, - "v": { - "register": "Vd.4S" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -94245,31 +289929,27 @@ ], "instructions": [ [ - "MOV" + "RSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_s64", + "name": "vrshrq_n_s16", "arguments": [ - "int64_t a", - "int64x2_t v", - "const int lane" + "int16x8_t a", + "const int n" ], "return_type": { - "value": "int64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 1 + "register": "Vn.8H" }, - "v": { - "register": "Vd.2D" + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -94279,31 +289959,27 @@ ], "instructions": [ [ - "MOV" + "SRSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_s8", + "name": "vrshrq_n_s32", "arguments": [ - "int8_t a", - "int8x16_t v", - "const int lane" + "int32x4_t a", + "const int n" ], "return_type": { - "value": "int8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 15 + "register": "Vn.4S" }, - "v": { - "register": "Vd.16B" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -94313,31 +289989,27 @@ ], "instructions": [ [ - "MOV" + "SRSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_u16", + "name": "vrshrq_n_s64", "arguments": [ - "uint16_t a", - "uint16x8_t v", - "const int lane" + "int64x2_t a", + "const int n" ], "return_type": { - "value": "uint16x8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 7 + "register": "Vn.2D" }, - "v": { - "register": "Vd.8H" + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -94347,31 +290019,27 @@ ], "instructions": [ [ - "MOV" + "SRSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_u32", + "name": "vrshrq_n_s8", "arguments": [ - "uint32_t a", - "uint32x4_t v", - "const int lane" + "int8x16_t a", + "const int n" ], "return_type": { - "value": "uint32x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Vn.16B" }, - "v": { - "register": "Vd.4S" + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -94381,31 +290049,27 @@ ], "instructions": [ [ - "MOV" + "SRSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_u64", + "name": "vrshrq_n_u16", "arguments": [ - "uint64_t a", - "uint64x2_t v", - "const int lane" + "uint16x8_t a", + "const int n" ], "return_type": { - "value": "uint64x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 1 + "register": "Vn.8H" }, - "v": { - "register": "Vd.2D" + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -94415,31 +290079,27 @@ ], "instructions": [ [ - "MOV" + "URSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_u8", + "name": "vrshrq_n_u32", "arguments": [ - "uint8_t a", - "uint8x16_t v", - "const int lane" + "uint32x4_t a", + "const int n" ], "return_type": { - "value": "uint8x16_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 15 + "register": "Vn.4S" }, - "v": { - "register": "Vd.16B" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -94449,86 +290109,82 @@ ], "instructions": [ [ - "MOV" + "URSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha1cq_u32", + "name": "vrshrq_n_u64", "arguments": [ - "uint32x4_t hash_abcd", - "uint32_t hash_e", - "uint32x4_t wk" + "uint64x2_t a", + "const int n" ], "return_type": { - "value": "uint32x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "hash_abcd": { - "register": "Qd" - }, - "hash_e": { - "register": "Sn" + "a": { + "register": "Vn.2D" }, - "wk": { - "register": "Vm.4S" + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "SHA1C" + "URSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha1h_u32", + "name": "vrshrq_n_u8", "arguments": [ - "uint32_t hash_e" + "uint8x16_t a", + "const int n" ], "return_type": { - "value": "uint32_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "hash_e": { - "register": "Sn" + "a": { + "register": "Vn.16B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "SHA1H" + "URSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha1mq_u32", + "name": "vrsqrte_f16", "arguments": [ - "uint32x4_t hash_abcd", - "uint32_t hash_e", - "uint32x4_t wk" + "float16x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { - "hash_abcd": { - "register": "Qd" - }, - "hash_e": { - "register": "Sn" - }, - "wk": { - "register": "Vm.4S" + "a": { + "register": "Vn.4H" } }, "Architectures": [ @@ -94537,182 +290193,141 @@ ], "instructions": [ [ - "SHA1M" + "FRSQRTE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha1pq_u32", + "name": "vrsqrte_f32", "arguments": [ - "uint32x4_t hash_abcd", - "uint32_t hash_e", - "uint32x4_t wk" + "float32x2_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { - "hash_abcd": { - "register": "Qd" - }, - "hash_e": { - "register": "Sn" - }, - "wk": { - "register": "Vm.4S" + "a": { + "register": "Vn.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "SHA1P" + "FRSQRTE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha1su0q_u32", + "name": "vrsqrte_f64", "arguments": [ - "uint32x4_t w0_3", - "uint32x4_t w4_7", - "uint32x4_t w8_11" + "float64x1_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float64x1_t" }, "Arguments_Preparation": { - "w0_3": { - "register": "Vd.4S" - }, - "w4_7": { - "register": "Vn.4S" - }, - "w8_11": { - "register": "Vm.4S" + "a": { + "register": "Dn" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SHA1SU0" + "FRSQRTE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha1su1q_u32", + "name": "vrsqrte_u32", "arguments": [ - "uint32x4_t tw0_3", - "uint32x4_t w12_15" + "uint32x2_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { - "tw0_3": { - "register": "Vd.4S" - }, - "w12_15": { - "register": "Vn.4S" + "a": { + "register": "Vn.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "SHA1SU1" + "URSQRTE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha256h2q_u32", + "name": "vrsqrted_f64", "arguments": [ - "uint32x4_t hash_efgh", - "uint32x4_t hash_abcd", - "uint32x4_t wk" + "float64_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float64_t" }, "Arguments_Preparation": { - "hash_abcd": { - "register": "Qn" - }, - "hash_efgh": { - "register": "Qd" - }, - "wk": { - "register": "Vm.4S" + "a": { + "register": "Dn" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SHA256H2" + "FRSQRTE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha256hq_u32", + "name": "vrsqrteh_f16", "arguments": [ - "uint32x4_t hash_abcd", - "uint32x4_t hash_efgh", - "uint32x4_t wk" + "float16_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float16_t" }, "Arguments_Preparation": { - "hash_abcd": { - "register": "Qd" - }, - "hash_efgh": { - "register": "Qn" - }, - "wk": { - "register": "Vm.4S" + "a": { + "register": "Hn" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SHA256H" + "FRSQRTE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha256su0q_u32", + "name": "vrsqrteq_f16", "arguments": [ - "uint32x4_t w0_3", - "uint32x4_t w4_7" + "float16x8_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { - "w0_3": { - "register": "Vd.4S" - }, - "w4_7": { - "register": "Vn.4S" + "a": { + "register": "Vn.8H" } }, "Architectures": [ @@ -94721,60 +290336,47 @@ ], "instructions": [ [ - "SHA256SU0" + "FRSQRTE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha256su1q_u32", + "name": "vrsqrteq_f32", "arguments": [ - "uint32x4_t tw0_3", - "uint32x4_t w8_11", - "uint32x4_t w12_15" + "float32x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float32x4_t" }, "Arguments_Preparation": { - "tw0_3": { - "register": "Vd.4S" - }, - "w12_15": { - "register": "Vm.4S" - }, - "w8_11": { + "a": { "register": "Vn.4S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "SHA256SU1" + "FRSQRTE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha512h2q_u64", + "name": "vrsqrteq_f64", "arguments": [ - "uint64x2_t sum_ab", - "uint64x2_t hash_c_", - "uint64x2_t hash_ab" + "float64x2_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "float64x2_t" }, "Arguments_Preparation": { - "hash_ab": {}, - "hash_c_": { - "register": "Qn" - }, - "sum_ab": { - "register": "Qd" + "a": { + "register": "Vn.2D" } }, "Architectures": [ @@ -94782,55 +290384,47 @@ ], "instructions": [ [ - "SHA512H2" + "FRSQRTE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha512hq_u64", + "name": "vrsqrteq_u32", "arguments": [ - "uint64x2_t hash_ed", - "uint64x2_t hash_gf", - "uint64x2_t kwh_kwh2" + "uint32x4_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "hash_ed": { - "register": "Qd" - }, - "hash_gf": { - "register": "Qn" - }, - "kwh_kwh2": {} + "a": { + "register": "Vn.4S" + } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SHA512H" + "URSQRTE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha512su0q_u64", + "name": "vrsqrtes_f32", "arguments": [ - "uint64x2_t w0_1", - "uint64x2_t w2_" + "float32_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "float32_t" }, "Arguments_Preparation": { - "w0_1": { - "register": "Vd.2D" - }, - "w2_": { - "register": "Vn.2D" + "a": { + "register": "Sn" } }, "Architectures": [ @@ -94838,56 +290432,54 @@ ], "instructions": [ [ - "SHA512SU0" + "FRSQRTE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha512su1q_u64", + "name": "vrsqrts_f16", "arguments": [ - "uint64x2_t s01_s02", - "uint64x2_t w14_15", - "uint64x2_t w9_10" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "float16x4_t" }, "Arguments_Preparation": { - "s01_s02": { - "register": "Vd.2D" - }, - "w14_15": { - "register": "Vn.2D" + "a": { + "register": "Vn.4H" }, - "w9_10": {} + "b": { + "register": "Vm.4H" + } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "SHA512SU1" + "FRSQRTS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_n_s16", + "name": "vrsqrts_f32", "arguments": [ - "int16x4_t a", - "const int n" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "int16x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.2S" }, - "n": { - "minimum": 0, - "maximum": 15 + "b": { + "register": "Vm.2S" } }, "Architectures": [ @@ -94897,147 +290489,135 @@ ], "instructions": [ [ - "SHL" + "FRSQRTS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_n_s32", + "name": "vrsqrts_f64", "arguments": [ - "int32x2_t a", - "const int n" + "float64x1_t a", + "float64x1_t b" ], "return_type": { - "value": "int32x2_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Dn" }, - "n": { - "minimum": 0, - "maximum": 31 + "b": { + "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SHL" + "FRSQRTS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_n_s64", + "name": "vrsqrtsd_f64", "arguments": [ - "int64x1_t a", - "const int n" + "float64_t a", + "float64_t b" ], "return_type": { - "value": "int64x1_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { "register": "Dn" }, - "n": { - "minimum": 0, - "maximum": 63 + "b": { + "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SHL" + "FRSQRTS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_n_s8", + "name": "vrsqrtsh_f16", "arguments": [ - "int8x8_t a", - "const int n" + "float16_t a", + "float16_t b" ], "return_type": { - "value": "int8x8_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Hn" }, - "n": { - "minimum": 0, - "maximum": 7 + "b": { + "register": "Hm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SHL" + "FRSQRTS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_n_u16", + "name": "vrsqrtsq_f16", "arguments": [ - "uint16x4_t a", - "const int n" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.8H" }, - "n": { - "minimum": 0, - "maximum": 15 + "b": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SHL" + "FRSQRTS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_n_u32", + "name": "vrsqrtsq_f32", "arguments": [ - "uint32x2_t a", - "const int n" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4S" }, - "n": { - "minimum": 0, - "maximum": 31 + "b": { + "register": "Vm.4S" } }, "Architectures": [ @@ -95047,86 +290627,85 @@ ], "instructions": [ [ - "SHL" + "FRSQRTS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_n_u64", + "name": "vrsqrtsq_f64", "arguments": [ - "uint64x1_t a", - "const int n" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "uint64x1_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.2D" }, - "n": { - "minimum": 0, - "maximum": 63 + "b": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SHL" + "FRSQRTS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_n_u8", + "name": "vrsqrtss_f32", "arguments": [ - "uint8x8_t a", - "const int n" + "float32_t a", + "float32_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Sn" }, - "n": { - "minimum": 0, - "maximum": 7 + "b": { + "register": "Sm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SHL" + "FRSQRTS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_s16", + "name": "vrsra_n_s16", "arguments": [ "int16x4_t a", - "int16x4_t b" + "int16x4_t b", + "const int n" ], "return_type": { "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.4H" }, "b": { - "register": "Vm.4H" + "register": "Vn.4H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -95136,26 +290715,31 @@ ], "instructions": [ [ - "SSHL" + "SRSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_s32", + "name": "vrsra_n_s32", "arguments": [ "int32x2_t a", - "int32x2_t b" + "int32x2_t b", + "const int n" ], "return_type": { "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.2S" }, "b": { - "register": "Vm.2S" + "register": "Vn.2S" + }, + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -95165,26 +290749,31 @@ ], "instructions": [ [ - "SSHL" + "SRSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_s64", + "name": "vrsra_n_s64", "arguments": [ "int64x1_t a", - "int64x1_t b" + "int64x1_t b", + "const int n" ], "return_type": { "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Dd" }, "b": { - "register": "Dm" + "register": "Dn" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -95194,26 +290783,31 @@ ], "instructions": [ [ - "SSHL" + "SRSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_s8", + "name": "vrsra_n_s8", "arguments": [ "int8x8_t a", - "int8x8_t b" + "int8x8_t b", + "const int n" ], "return_type": { "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vd.8B" }, "b": { - "register": "Vm.8B" + "register": "Vn.8B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -95223,26 +290817,31 @@ ], "instructions": [ [ - "SSHL" + "SRSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_u16", + "name": "vrsra_n_u16", "arguments": [ "uint16x4_t a", - "int16x4_t b" + "uint16x4_t b", + "const int n" ], "return_type": { "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.4H" }, "b": { - "register": "Vm.4H" + "register": "Vn.4H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -95252,26 +290851,31 @@ ], "instructions": [ [ - "USHL" + "URSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_u32", + "name": "vrsra_n_u32", "arguments": [ "uint32x2_t a", - "int32x2_t b" + "uint32x2_t b", + "const int n" ], "return_type": { "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.2S" }, "b": { - "register": "Vm.2S" + "register": "Vn.2S" + }, + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -95281,26 +290885,31 @@ ], "instructions": [ [ - "USHL" + "URSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_u64", + "name": "vrsra_n_u64", "arguments": [ "uint64x1_t a", - "int64x1_t b" + "uint64x1_t b", + "const int n" ], "return_type": { "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Dd" }, "b": { - "register": "Dm" + "register": "Dn" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -95310,26 +290919,31 @@ ], "instructions": [ [ - "USHL" + "URSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_u8", + "name": "vrsra_n_u8", "arguments": [ "uint8x8_t a", - "int8x8_t b" + "uint8x8_t b", + "const int n" ], "return_type": { "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vd.8B" }, "b": { - "register": "Vm.8B" + "register": "Vn.8B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -95339,15 +290953,16 @@ ], "instructions": [ [ - "USHL" + "URSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshld_n_s64", + "name": "vrsrad_n_s64", "arguments": [ "int64_t a", + "int64_t b", "const int n" ], "return_type": { @@ -95355,11 +290970,14 @@ }, "Arguments_Preparation": { "a": { + "register": "Dd" + }, + "b": { "register": "Dn" }, "n": { - "minimum": 0, - "maximum": 63 + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -95367,15 +290985,16 @@ ], "instructions": [ [ - "SHL" + "SRSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshld_n_u64", + "name": "vrsrad_n_u64", "arguments": [ "uint64_t a", + "uint64_t b", "const int n" ], "return_type": { @@ -95383,11 +291002,14 @@ }, "Arguments_Preparation": { "a": { + "register": "Dd" + }, + "b": { "register": "Dn" }, "n": { - "minimum": 0, - "maximum": 63 + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -95395,153 +291017,186 @@ ], "instructions": [ [ - "SHL" + "URSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshld_s64", + "name": "vrsraq_n_s16", "arguments": [ - "int64_t a", - "int64_t b" + "int16x8_t a", + "int16x8_t b", + "const int n" ], "return_type": { - "value": "int64_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.8H" }, "b": { - "register": "Dm" + "register": "Vn.8H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SSHL" + "SRSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshld_u64", + "name": "vrsraq_n_s32", "arguments": [ - "uint64_t a", - "int64_t b" + "int32x4_t a", + "int32x4_t b", + "const int n" ], "return_type": { - "value": "uint64_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.4S" }, "b": { - "register": "Dm" + "register": "Vn.4S" + }, + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USHL" + "SRSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_high_n_s16", + "name": "vrsraq_n_s64", "arguments": [ - "int16x8_t a", + "int64x2_t a", + "int64x2_t b", "const int n" ], "return_type": { - "value": "int32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.2D" }, "n": { - "minimum": 0, - "maximum": 16 + "minimum": 1, + "maximum": 64 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SSHLL2" + "SRSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_high_n_s32", + "name": "vrsraq_n_s8", "arguments": [ - "int32x4_t a", + "int8x16_t a", + "int8x16_t b", "const int n" ], "return_type": { - "value": "int64x2_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.16B" + }, + "b": { + "register": "Vn.16B" }, "n": { - "minimum": 0, - "maximum": 32 + "minimum": 1, + "maximum": 8 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SSHLL2" + "SRSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_high_n_s8", + "name": "vrsraq_n_u16", "arguments": [ - "int8x16_t a", + "uint16x8_t a", + "uint16x8_t b", "const int n" ], "return_type": { - "value": "int16x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vd.8H" + }, + "b": { + "register": "Vn.8H" }, "n": { - "minimum": 0, - "maximum": 8 + "minimum": 1, + "maximum": 16 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SSHLL2" + "URSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_high_n_u16", + "name": "vrsraq_n_u32", "arguments": [ - "uint16x8_t a", + "uint32x4_t a", + "uint32x4_t b", "const int n" ], "return_type": { @@ -95549,27 +291204,33 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.4S" }, "n": { - "minimum": 0, - "maximum": 16 + "minimum": 1, + "maximum": 32 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USHLL2" + "URSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_high_n_u32", + "name": "vrsraq_n_u64", "arguments": [ - "uint32x4_t a", + "uint64x2_t a", + "uint64x2_t b", "const int n" ], "return_type": { @@ -95577,247 +291238,263 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.2D" }, "n": { - "minimum": 0, - "maximum": 32 + "minimum": 1, + "maximum": 64 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USHLL2" + "URSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_high_n_u8", + "name": "vrsraq_n_u8", "arguments": [ "uint8x16_t a", + "uint8x16_t b", "const int n" ], "return_type": { - "value": "uint16x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.16B" + }, + "b": { "register": "Vn.16B" }, "n": { - "minimum": 0, + "minimum": 1, "maximum": 8 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USHLL2" + "URSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_n_s16", + "name": "vrsubhn_high_s16", "arguments": [ - "int16x4_t a", - "const int n" + "int8x8_t r", + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.8H" }, - "n": { - "minimum": 0, - "maximum": 16 + "b": { + "register": "Vm.8H" + }, + "r": { + "register": "Vd.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SSHLL" + "RSUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_n_s32", + "name": "vrsubhn_high_s32", "arguments": [ - "int32x2_t a", - "const int n" + "int16x4_t r", + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4S" }, - "n": { - "minimum": 0, - "maximum": 32 + "b": { + "register": "Vm.4S" + }, + "r": { + "register": "Vd.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SSHLL" + "RSUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_n_s8", + "name": "vrsubhn_high_s64", "arguments": [ - "int8x8_t a", - "const int n" + "int32x2_t r", + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2D" }, - "n": { - "minimum": 0, - "maximum": 8 + "b": { + "register": "Vm.2D" + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SSHLL" + "RSUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_n_u16", + "name": "vrsubhn_high_u16", "arguments": [ - "uint16x4_t a", - "const int n" + "uint8x8_t r", + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.8H" }, - "n": { - "minimum": 0, - "maximum": 16 + "b": { + "register": "Vm.8H" + }, + "r": { + "register": "Vd.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USHLL" + "RSUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_n_u32", + "name": "vrsubhn_high_u32", "arguments": [ - "uint32x2_t a", - "const int n" + "uint16x4_t r", + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4S" }, - "n": { - "minimum": 0, - "maximum": 32 + "b": { + "register": "Vm.4S" + }, + "r": { + "register": "Vd.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USHLL" + "RSUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_n_u8", + "name": "vrsubhn_high_u64", "arguments": [ - "uint8x8_t a", - "const int n" + "uint32x2_t r", + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2D" }, - "n": { - "minimum": 0, - "maximum": 8 + "b": { + "register": "Vm.2D" + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USHLL" + "RSUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_n_s16", + "name": "vrsubhn_s16", "arguments": [ "int16x8_t a", - "const int n" + "int16x8_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" }, - "n": { - "minimum": 0, - "maximum": 15 + "b": { + "register": "Vm.8H" } }, "Architectures": [ @@ -95827,27 +291504,26 @@ ], "instructions": [ [ - "SHL" + "RSUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_n_s32", + "name": "vrsubhn_s32", "arguments": [ "int32x4_t a", - "const int n" + "int32x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" }, - "n": { - "minimum": 0, - "maximum": 31 + "b": { + "register": "Vm.4S" } }, "Architectures": [ @@ -95857,27 +291533,26 @@ ], "instructions": [ [ - "SHL" + "RSUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_n_s64", + "name": "vrsubhn_s64", "arguments": [ "int64x2_t a", - "const int n" + "int64x2_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2D" }, - "n": { - "minimum": 0, - "maximum": 63 + "b": { + "register": "Vm.2D" } }, "Architectures": [ @@ -95887,27 +291562,26 @@ ], "instructions": [ [ - "SHL" + "RSUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_n_s8", + "name": "vrsubhn_u16", "arguments": [ - "int8x16_t a", - "const int n" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int8x16_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, - "n": { - "minimum": 0, - "maximum": 7 + "b": { + "register": "Vm.8H" } }, "Architectures": [ @@ -95917,27 +291591,26 @@ ], "instructions": [ [ - "SHL" + "RSUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_n_u16", + "name": "vrsubhn_u32", "arguments": [ - "uint16x8_t a", - "const int n" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4S" }, - "n": { - "minimum": 0, - "maximum": 15 + "b": { + "register": "Vm.4S" } }, "Architectures": [ @@ -95947,27 +291620,26 @@ ], "instructions": [ [ - "SHL" + "RSUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_n_u32", + "name": "vrsubhn_u64", "arguments": [ - "uint32x4_t a", - "const int n" + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2D" }, - "n": { - "minimum": 0, - "maximum": 31 + "b": { + "register": "Vm.2D" } }, "Architectures": [ @@ -95977,144 +291649,166 @@ ], "instructions": [ [ - "SHL" + "RSUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_n_u64", + "name": "vscale_f16", "arguments": [ - "uint64x2_t a", - "const int n" + "float16x4_t vn", + "int16x4_t vm" ], "return_type": { - "value": "uint64x2_t" + "value": "float16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "vm": { + "register": "Vm.4H" }, - "n": { - "minimum": 0, - "maximum": 63 + "vn": { + "register": "Vn.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SHL" + "FSCALE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_n_u8", + "name": "vscale_f32", "arguments": [ - "uint8x16_t a", - "const int n" + "float32x2_t vn", + "int32x2_t vm" ], "return_type": { - "value": "uint8x16_t" + "value": "float32x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "vm": { + "register": "Vm.2S" }, - "n": { - "minimum": 0, - "maximum": 7 + "vn": { + "register": "Vn.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SHL" + "FSCALE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_s16", + "name": "vscaleq_f16", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "float16x8_t vn", + "int16x8_t vm" ], "return_type": { - "value": "int16x8_t" + "value": "float16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { + "vm": { "register": "Vm.8H" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SSHL" + "FSCALE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_s32", + "name": "vscaleq_f32", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "float32x4_t vn", + "int32x4_t vm" ], "return_type": { - "value": "int32x4_t" + "value": "float32x4_t" }, "Arguments_Preparation": { - "a": { + "vm": { + "register": "Vm.4S" + }, + "vn": { "register": "Vn.4S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vscaleq_f64", + "arguments": [ + "float64x2_t vn", + "int64x2_t vm" + ], + "return_type": { + "value": "float64x2_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.2D" }, - "b": { - "register": "Vm.4S" + "vn": { + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SSHL" + "FSCALE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_s64", + "name": "vset_lane_f16", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "float16_t a", + "float16x4_t v", + "const int lane" ], "return_type": { - "value": "int64x2_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "VnH" }, - "b": { - "register": "Vm.2D" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vd.4H" } }, "Architectures": [ @@ -96124,26 +291818,31 @@ ], "instructions": [ [ - "SSHL" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_s8", + "name": "vset_lane_f32", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "float32_t a", + "float32x2_t v", + "const int lane" ], "return_type": { - "value": "int8x16_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Rn" }, - "b": { - "register": "Vm.16B" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vd.2S" } }, "Architectures": [ @@ -96153,55 +291852,63 @@ ], "instructions": [ [ - "SSHL" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_u16", + "name": "vset_lane_f64", "arguments": [ - "uint16x8_t a", - "int16x8_t b" + "float64_t a", + "float64x1_t v", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Rn" }, - "b": { - "register": "Vm.8H" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "v": { + "register": "Vd.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USHL" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_u32", + "name": "vset_lane_p16", "arguments": [ - "uint32x4_t a", - "int32x4_t b" + "poly16_t a", + "poly16x4_t v", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Rn" }, - "b": { - "register": "Vm.4S" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vd.4H" } }, "Architectures": [ @@ -96211,55 +291918,64 @@ ], "instructions": [ [ - "USHL" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_u64", + "name": "vset_lane_p64", "arguments": [ - "uint64x2_t a", - "int64x2_t b" + "poly64_t a", + "poly64x1_t v", + "const int lane" ], "return_type": { - "value": "uint64x2_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Rn" }, - "b": { - "register": "Vm.2D" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "v": { + "register": "Vd.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "USHL" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_u8", + "name": "vset_lane_p8", "arguments": [ - "uint8x16_t a", - "int8x16_t b" + "poly8_t a", + "poly8x8_t v", + "const int lane" ], "return_type": { - "value": "uint8x16_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Rn" }, - "b": { - "register": "Vm.16B" + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vd.8B" } }, "Architectures": [ @@ -96269,27 +291985,31 @@ ], "instructions": [ [ - "USHL" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshr_n_s16", + "name": "vset_lane_s16", "arguments": [ - "int16x4_t a", - "const int n" + "int16_t a", + "int16x4_t v", + "const int lane" ], "return_type": { "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 16 + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vd.4H" } }, "Architectures": [ @@ -96299,27 +292019,31 @@ ], "instructions": [ [ - "SSHR" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshr_n_s32", + "name": "vset_lane_s32", "arguments": [ - "int32x2_t a", - "const int n" + "int32_t a", + "int32x2_t v", + "const int lane" ], "return_type": { "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 32 + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vd.2S" } }, "Architectures": [ @@ -96329,27 +292053,31 @@ ], "instructions": [ [ - "SSHR" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshr_n_s64", + "name": "vset_lane_s64", "arguments": [ - "int64x1_t a", - "const int n" + "int64_t a", + "int64x1_t v", + "const int lane" ], "return_type": { "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 64 + "lane": { + "minimum": 0, + "maximum": 0 + }, + "v": { + "register": "Vd.1D" } }, "Architectures": [ @@ -96359,27 +292087,31 @@ ], "instructions": [ [ - "SSHR" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshr_n_s8", + "name": "vset_lane_s8", "arguments": [ - "int8x8_t a", - "const int n" + "int8_t a", + "int8x8_t v", + "const int lane" ], "return_type": { "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 8 + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vd.8B" } }, "Architectures": [ @@ -96389,27 +292121,31 @@ ], "instructions": [ [ - "SSHR" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshr_n_u16", + "name": "vset_lane_u16", "arguments": [ - "uint16x4_t a", - "const int n" + "uint16_t a", + "uint16x4_t v", + "const int lane" ], "return_type": { "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 16 + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vd.4H" } }, "Architectures": [ @@ -96419,27 +292155,31 @@ ], "instructions": [ [ - "USHR" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshr_n_u32", + "name": "vset_lane_u32", "arguments": [ - "uint32x2_t a", - "const int n" + "uint32_t a", + "uint32x2_t v", + "const int lane" ], "return_type": { "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 32 + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vd.2S" } }, "Architectures": [ @@ -96449,27 +292189,31 @@ ], "instructions": [ [ - "USHR" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshr_n_u64", + "name": "vset_lane_u64", "arguments": [ - "uint64x1_t a", - "const int n" + "uint64_t a", + "uint64x1_t v", + "const int lane" ], "return_type": { "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 64 + "lane": { + "minimum": 0, + "maximum": 0 + }, + "v": { + "register": "Vd.1D" } }, "Architectures": [ @@ -96479,27 +292223,31 @@ ], "instructions": [ [ - "USHR" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshr_n_u8", + "name": "vset_lane_u8", "arguments": [ - "uint8x8_t a", - "const int n" + "uint8_t a", + "uint8x8_t v", + "const int lane" ], "return_type": { "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 8 + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vd.8B" } }, "Architectures": [ @@ -96509,275 +292257,402 @@ ], "instructions": [ [ - "USHR" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrd_n_s64", + "name": "vsetq_lane_f16", "arguments": [ - "int64_t a", - "const int n" + "float16_t a", + "float16x8_t v", + "const int lane" ], "return_type": { - "value": "int64_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "VnH" }, - "n": { - "minimum": 1, - "maximum": 64 + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "MOV" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vsetq_lane_f32", + "arguments": [ + "float32_t a", + "float32x4_t v", + "const int lane" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Rn" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vd.4S" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "MOV" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vsetq_lane_f64", + "arguments": [ + "float64_t a", + "float64x2_t v", + "const int lane" + ], + "return_type": { + "value": "float64x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Rn" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vd.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOV" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vsetq_lane_p16", + "arguments": [ + "poly16_t a", + "poly16x8_t v", + "const int lane" + ], + "return_type": { + "value": "poly16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Rn" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vd.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SSHR" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrd_n_u64", + "name": "vsetq_lane_p64", "arguments": [ - "uint64_t a", - "const int n" + "poly64_t a", + "poly64x2_t v", + "const int lane" ], "return_type": { - "value": "uint64_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 64 + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vd.2D" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "USHR" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_high_n_s16", + "name": "vsetq_lane_p8", "arguments": [ - "int8x8_t r", - "int16x8_t a", - "const int n" + "poly8_t a", + "poly8x16_t v", + "const int lane" ], "return_type": { - "value": "int8x16_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 8 + "lane": { + "minimum": 0, + "maximum": 15 }, - "r": { - "register": "Vd.8B" + "v": { + "register": "Vd.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SHRN2" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_high_n_s32", + "name": "vsetq_lane_s16", "arguments": [ - "int16x4_t r", - "int32x4_t a", - "const int n" + "int16_t a", + "int16x8_t v", + "const int lane" ], "return_type": { "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 16 + "lane": { + "minimum": 0, + "maximum": 7 }, - "r": { - "register": "Vd.4H" + "v": { + "register": "Vd.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SHRN2" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_high_n_s64", + "name": "vsetq_lane_s32", "arguments": [ - "int32x2_t r", - "int64x2_t a", - "const int n" + "int32_t a", + "int32x4_t v", + "const int lane" ], "return_type": { "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 32 + "lane": { + "minimum": 0, + "maximum": 3 }, - "r": { - "register": "Vd.2S" + "v": { + "register": "Vd.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SHRN2" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_high_n_u16", + "name": "vsetq_lane_s64", "arguments": [ - "uint8x8_t r", - "uint16x8_t a", - "const int n" + "int64_t a", + "int64x2_t v", + "const int lane" ], "return_type": { - "value": "uint8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 8 + "lane": { + "minimum": 0, + "maximum": 1 }, - "r": { - "register": "Vd.8B" + "v": { + "register": "Vd.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SHRN2" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_high_n_u32", + "name": "vsetq_lane_s8", "arguments": [ - "uint16x4_t r", - "uint32x4_t a", - "const int n" + "int8_t a", + "int8x16_t v", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 16 + "lane": { + "minimum": 0, + "maximum": 15 }, - "r": { - "register": "Vd.4H" + "v": { + "register": "Vd.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SHRN2" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_high_n_u64", + "name": "vsetq_lane_u16", "arguments": [ - "uint32x2_t r", - "uint64x2_t a", - "const int n" + "uint16_t a", + "uint16x8_t v", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 32 + "lane": { + "minimum": 0, + "maximum": 7 }, - "r": { - "register": "Vd.2S" + "v": { + "register": "Vd.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SHRN2" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_n_s16", + "name": "vsetq_lane_u32", "arguments": [ - "int16x8_t a", - "const int n" + "uint32_t a", + "uint32x4_t v", + "const int lane" ], "return_type": { - "value": "int8x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 8 + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vd.4S" } }, "Architectures": [ @@ -96787,27 +292662,31 @@ ], "instructions": [ [ - "SHRN" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_n_s32", + "name": "vsetq_lane_u64", "arguments": [ - "int32x4_t a", - "const int n" + "uint64_t a", + "uint64x2_t v", + "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 16 + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vd.2D" } }, "Architectures": [ @@ -96817,27 +292696,31 @@ ], "instructions": [ [ - "SHRN" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_n_s64", + "name": "vsetq_lane_u8", "arguments": [ - "int64x2_t a", - "const int n" + "uint8_t a", + "uint8x16_t v", + "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 32 + "lane": { + "minimum": 0, + "maximum": 15 + }, + "v": { + "register": "Vd.16B" } }, "Architectures": [ @@ -96847,447 +292730,439 @@ ], "instructions": [ [ - "SHRN" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_n_u16", + "name": "vsha1cq_u32", "arguments": [ - "uint16x8_t a", - "const int n" + "uint32x4_t hash_abcd", + "uint32_t hash_e", + "uint32x4_t wk" ], "return_type": { - "value": "uint8x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "hash_abcd": { + "register": "Qd" }, - "n": { - "minimum": 1, - "maximum": 8 + "hash_e": { + "register": "Sn" + }, + "wk": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SHRN" + "SHA1C" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_n_u32", + "name": "vsha1h_u32", "arguments": [ - "uint32x4_t a", - "const int n" + "uint32_t hash_e" ], "return_type": { - "value": "uint16x4_t" + "value": "uint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "n": { - "minimum": 1, - "maximum": 16 + "hash_e": { + "register": "Sn" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SHRN" + "SHA1H" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_n_u64", + "name": "vsha1mq_u32", "arguments": [ - "uint64x2_t a", - "const int n" + "uint32x4_t hash_abcd", + "uint32_t hash_e", + "uint32x4_t wk" ], "return_type": { - "value": "uint32x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "hash_abcd": { + "register": "Qd" }, - "n": { - "minimum": 1, - "maximum": 32 + "hash_e": { + "register": "Sn" + }, + "wk": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SHRN" + "SHA1M" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrq_n_s16", + "name": "vsha1pq_u32", "arguments": [ - "int16x8_t a", - "const int n" + "uint32x4_t hash_abcd", + "uint32_t hash_e", + "uint32x4_t wk" ], "return_type": { - "value": "int16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "hash_abcd": { + "register": "Qd" }, - "n": { - "minimum": 1, - "maximum": 16 + "hash_e": { + "register": "Sn" + }, + "wk": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SSHR" + "SHA1P" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrq_n_s32", + "name": "vsha1su0q_u32", "arguments": [ - "int32x4_t a", - "const int n" + "uint32x4_t w0_3", + "uint32x4_t w4_7", + "uint32x4_t w8_11" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { + "w0_3": { + "register": "Vd.4S" + }, + "w4_7": { "register": "Vn.4S" }, - "n": { - "minimum": 1, - "maximum": 32 + "w8_11": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SSHR" + "SHA1SU0" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrq_n_s64", + "name": "vsha1su1q_u32", "arguments": [ - "int64x2_t a", - "const int n" + "uint32x4_t tw0_3", + "uint32x4_t w12_15" ], "return_type": { - "value": "int64x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "tw0_3": { + "register": "Vd.4S" }, - "n": { - "minimum": 1, - "maximum": 64 + "w12_15": { + "register": "Vn.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SSHR" + "SHA1SU1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrq_n_s8", + "name": "vsha256h2q_u32", "arguments": [ - "int8x16_t a", - "const int n" + "uint32x4_t hash_efgh", + "uint32x4_t hash_abcd", + "uint32x4_t wk" ], "return_type": { - "value": "int8x16_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "hash_abcd": { + "register": "Qn" }, - "n": { - "minimum": 1, - "maximum": 8 + "hash_efgh": { + "register": "Qd" + }, + "wk": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SSHR" + "SHA256H2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrq_n_u16", + "name": "vsha256hq_u32", "arguments": [ - "uint16x8_t a", - "const int n" + "uint32x4_t hash_abcd", + "uint32x4_t hash_efgh", + "uint32x4_t wk" ], "return_type": { - "value": "uint16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "hash_abcd": { + "register": "Qd" }, - "n": { - "minimum": 1, - "maximum": 16 + "hash_efgh": { + "register": "Qn" + }, + "wk": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "USHR" + "SHA256H" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrq_n_u32", + "name": "vsha256su0q_u32", "arguments": [ - "uint32x4_t a", - "const int n" + "uint32x4_t w0_3", + "uint32x4_t w4_7" ], "return_type": { "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "w0_3": { + "register": "Vd.4S" }, - "n": { - "minimum": 1, - "maximum": 32 + "w4_7": { + "register": "Vn.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "USHR" + "SHA256SU0" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrq_n_u64", + "name": "vsha256su1q_u32", "arguments": [ - "uint64x2_t a", - "const int n" + "uint32x4_t tw0_3", + "uint32x4_t w8_11", + "uint32x4_t w12_15" ], "return_type": { - "value": "uint64x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "tw0_3": { + "register": "Vd.4S" }, - "n": { - "minimum": 1, - "maximum": 64 + "w12_15": { + "register": "Vm.4S" + }, + "w8_11": { + "register": "Vn.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "USHR" + "SHA256SU1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrq_n_u8", + "name": "vsha512h2q_u64", "arguments": [ - "uint8x16_t a", - "const int n" + "uint64x2_t sum_ab", + "uint64x2_t hash_c_", + "uint64x2_t hash_ab" ], "return_type": { - "value": "uint8x16_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "hash_ab": { + "register": "Vm.2D" }, - "n": { - "minimum": 1, - "maximum": 8 + "hash_c_": { + "register": "Qn" + }, + "sum_ab": { + "register": "Qd" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USHR" + "SHA512H2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsli_n_p16", + "name": "vsha512hq_u64", "arguments": [ - "poly16x4_t a", - "poly16x4_t b", - "const int n" + "uint64x2_t hash_ed", + "uint64x2_t hash_gf", + "uint64x2_t kwh_kwh2" ], "return_type": { - "value": "poly16x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4H" + "hash_ed": { + "register": "Qd" }, - "b": { - "register": "Vn.4H" + "hash_gf": { + "register": "Qn" }, - "n": { - "minimum": 0, - "maximum": 15 + "kwh_kwh2": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SLI" + "SHA512H" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsli_n_p64", + "name": "vsha512su0q_u64", "arguments": [ - "poly64x1_t a", - "poly64x1_t b", - "const int n" + "uint64x2_t w0_1", + "uint64x2_t w2_" ], "return_type": { - "value": "poly64x1_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Dd" - }, - "b": { - "register": "Dn" + "w0_1": { + "register": "Vd.2D" }, - "n": { - "minimum": 0, - "maximum": 63 + "w2_": { + "register": "Vn.2D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SLI" + "SHA512SU0" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsli_n_p8", + "name": "vsha512su1q_u64", "arguments": [ - "poly8x8_t a", - "poly8x8_t b", - "const int n" + "uint64x2_t s01_s02", + "uint64x2_t w14_15", + "uint64x2_t w9_10" ], "return_type": { - "value": "poly8x8_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "s01_s02": { + "register": "Vd.2D" }, - "b": { - "register": "Vn.8B" + "w14_15": { + "register": "Vn.2D" }, - "n": { - "minimum": 0, - "maximum": 7 + "w9_10": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SLI" + "SHA512SU1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsli_n_s16", + "name": "vshl_n_s16", "arguments": [ "int16x4_t a", - "int16x4_t b", "const int n" ], "return_type": { @@ -97295,9 +293170,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { "register": "Vn.4H" }, "n": { @@ -97312,16 +293184,15 @@ ], "instructions": [ [ - "SLI" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsli_n_s32", + "name": "vshl_n_s32", "arguments": [ "int32x2_t a", - "int32x2_t b", "const int n" ], "return_type": { @@ -97329,9 +293200,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { "register": "Vn.2S" }, "n": { @@ -97346,16 +293214,15 @@ ], "instructions": [ [ - "SLI" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsli_n_s64", + "name": "vshl_n_s64", "arguments": [ "int64x1_t a", - "int64x1_t b", "const int n" ], "return_type": { @@ -97363,9 +293230,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { "register": "Dn" }, "n": { @@ -97380,16 +293244,15 @@ ], "instructions": [ [ - "SLI" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsli_n_s8", + "name": "vshl_n_s8", "arguments": [ "int8x8_t a", - "int8x8_t b", "const int n" ], "return_type": { @@ -97397,9 +293260,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "b": { "register": "Vn.8B" }, "n": { @@ -97414,16 +293274,15 @@ ], "instructions": [ [ - "SLI" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsli_n_u16", + "name": "vshl_n_u16", "arguments": [ "uint16x4_t a", - "uint16x4_t b", "const int n" ], "return_type": { @@ -97431,9 +293290,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { "register": "Vn.4H" }, "n": { @@ -97448,16 +293304,15 @@ ], "instructions": [ [ - "SLI" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsli_n_u32", + "name": "vshl_n_u32", "arguments": [ "uint32x2_t a", - "uint32x2_t b", "const int n" ], "return_type": { @@ -97465,9 +293320,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { "register": "Vn.2S" }, "n": { @@ -97482,16 +293334,15 @@ ], "instructions": [ [ - "SLI" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsli_n_u64", + "name": "vshl_n_u64", "arguments": [ "uint64x1_t a", - "uint64x1_t b", "const int n" ], "return_type": { @@ -97499,9 +293350,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { "register": "Dn" }, "n": { @@ -97516,16 +293364,15 @@ ], "instructions": [ [ - "SLI" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsli_n_u8", + "name": "vshl_n_u8", "arguments": [ "uint8x8_t a", - "uint8x8_t b", "const int n" ], "return_type": { @@ -97533,9 +293380,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "b": { "register": "Vn.8B" }, "n": { @@ -97550,95 +293394,84 @@ ], "instructions": [ [ - "SLI" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vslid_n_s64", + "name": "vshl_s16", "arguments": [ - "int64_t a", - "int64_t b", - "const int n" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "int64_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.4H" }, "b": { - "register": "Dn" - }, - "n": { - "minimum": 0, - "maximum": 63 + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SLI" + "SSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vslid_n_u64", + "name": "vshl_s32", "arguments": [ - "uint64_t a", - "uint64_t b", - "const int n" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "uint64_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.2S" }, "b": { - "register": "Dn" - }, - "n": { - "minimum": 0, - "maximum": 63 + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SLI" + "SSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsliq_n_p16", + "name": "vshl_s64", "arguments": [ - "poly16x8_t a", - "poly16x8_t b", - "const int n" + "int64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "poly16x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Dn" }, "b": { - "register": "Vn.8H" - }, - "n": { - "minimum": 0, - "maximum": 15 + "register": "Dm" } }, "Architectures": [ @@ -97648,64 +293481,55 @@ ], "instructions": [ [ - "SLI" + "SSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsliq_n_p64", + "name": "vshl_s8", "arguments": [ - "poly64x2_t a", - "poly64x2_t b", - "const int n" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "poly64x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.8B" }, "b": { - "register": "Vn.2D" - }, - "n": { - "minimum": 0, - "maximum": 63 + "register": "Vm.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "SLI" + "SSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsliq_n_p8", + "name": "vshl_u16", "arguments": [ - "poly8x16_t a", - "poly8x16_t b", - "const int n" + "uint16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vn.4H" }, "b": { - "register": "Vn.16B" - }, - "n": { - "minimum": 0, - "maximum": 7 + "register": "Vm.4H" } }, "Architectures": [ @@ -97715,31 +293539,26 @@ ], "instructions": [ [ - "SLI" + "USHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsliq_n_s16", + "name": "vshl_u32", "arguments": [ - "int16x8_t a", - "int16x8_t b", - "const int n" + "uint32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "int16x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vn.2S" }, "b": { - "register": "Vn.8H" - }, - "n": { - "minimum": 0, - "maximum": 15 + "register": "Vm.2S" } }, "Architectures": [ @@ -97749,31 +293568,26 @@ ], "instructions": [ [ - "SLI" + "USHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsliq_n_s32", + "name": "vshl_u64", "arguments": [ - "int32x4_t a", - "int32x4_t b", - "const int n" + "uint64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Dn" }, "b": { - "register": "Vn.4S" - }, - "n": { - "minimum": 0, - "maximum": 31 + "register": "Dm" } }, "Architectures": [ @@ -97783,31 +293597,26 @@ ], "instructions": [ [ - "SLI" + "USHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsliq_n_s64", + "name": "vshl_u8", "arguments": [ - "int64x2_t a", - "int64x2_t b", - "const int n" + "uint8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.8B" }, "b": { - "register": "Vn.2D" - }, - "n": { - "minimum": 0, - "maximum": 63 + "register": "Vm.8B" } }, "Architectures": [ @@ -97817,282 +293626,221 @@ ], "instructions": [ [ - "SLI" + "USHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsliq_n_s8", + "name": "vshld_n_s64", "arguments": [ - "int8x16_t a", - "int8x16_t b", + "int64_t a", "const int n" ], "return_type": { - "value": "int8x16_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "b": { - "register": "Vn.16B" + "register": "Dn" }, "n": { "minimum": 0, - "maximum": 7 + "maximum": 63 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SLI" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsliq_n_u16", + "name": "vshld_n_u64", "arguments": [ - "uint16x8_t a", - "uint16x8_t b", + "uint64_t a", "const int n" ], "return_type": { - "value": "uint16x8_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.8H" + "register": "Dn" }, "n": { "minimum": 0, - "maximum": 15 + "maximum": 63 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SLI" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsliq_n_u32", + "name": "vshld_s64", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "const int n" + "int64_t a", + "int64_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Dn" }, "b": { - "register": "Vn.4S" - }, - "n": { - "minimum": 0, - "maximum": 31 + "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SLI" + "SSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsliq_n_u64", + "name": "vshld_u64", "arguments": [ - "uint64x2_t a", - "uint64x2_t b", - "const int n" + "uint64_t a", + "int64_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Dn" }, "b": { - "register": "Vn.2D" - }, - "n": { - "minimum": 0, - "maximum": 63 + "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SLI" + "USHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsliq_n_u8", + "name": "vshll_high_n_s16", "arguments": [ - "uint8x16_t a", - "uint8x16_t b", + "int16x8_t a", "const int n" ], "return_type": { - "value": "uint8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "b": { - "register": "Vn.16B" + "register": "Vn.8H" }, "n": { "minimum": 0, - "maximum": 7 + "maximum": 16 } }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "SLI" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vsm3partw1q_u32", - "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t c" - ], - "return_type": { - "value": "uint32x4_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.4S" - }, - "b": {}, - "c": {} - }, "Architectures": [ "A64" ], "instructions": [ [ - "SM3PARTW1" + "SSHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsm3partw2q_u32", + "name": "vshll_high_n_s32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t c" + "int32x4_t a", + "const int n" ], "return_type": { - "value": "uint32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.4S" }, - "b": {}, - "c": {} + "n": { + "minimum": 0, + "maximum": 32 + } }, "Architectures": [ "A64" ], "instructions": [ [ - "SM3PARTW2" + "SSHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsm3ss1q_u32", + "name": "vshll_high_n_s8", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t c" + "int8x16_t a", + "const int n" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.16B" }, - "b": {}, - "c": {} + "n": { + "minimum": 0, + "maximum": 8 + } }, "Architectures": [ "A64" ], "instructions": [ [ - "SM3SS1" + "SSHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsm3tt1aq_u32", + "name": "vshll_high_n_u16", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t c", - "const int imm2" + "uint16x8_t a", + "const int n" ], "return_type": { "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.8H" }, - "b": {}, - "c": {}, - "imm2": { + "n": { "minimum": 0, - "maximum": 3 + "maximum": 16 } }, "Architectures": [ @@ -98100,31 +293848,27 @@ ], "instructions": [ [ - "SM3TT1A" + "USHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsm3tt1bq_u32", + "name": "vshll_high_n_u32", "arguments": [ "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t c", - "const int imm2" + "const int n" ], "return_type": { - "value": "uint32x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.4S" }, - "b": {}, - "c": {}, - "imm2": { + "n": { "minimum": 0, - "maximum": 3 + "maximum": 32 } }, "Architectures": [ @@ -98132,31 +293876,27 @@ ], "instructions": [ [ - "SM3TT1B" + "USHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsm3tt2aq_u32", + "name": "vshll_high_n_u8", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t c", - "const int imm2" + "uint8x16_t a", + "const int n" ], "return_type": { - "value": "uint32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.16B" }, - "b": {}, - "c": {}, - "imm2": { + "n": { "minimum": 0, - "maximum": 3 + "maximum": 8 } }, "Architectures": [ @@ -98164,584 +293904,667 @@ ], "instructions": [ [ - "SM3TT2A" + "USHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsm3tt2bq_u32", + "name": "vshll_n_s16", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t c", - "const int imm2" + "int16x4_t a", + "const int n" ], "return_type": { - "value": "uint32x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.4H" }, - "b": {}, - "c": {}, - "imm2": { + "n": { "minimum": 0, - "maximum": 3 + "maximum": 16 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SM3TT2B" + "SSHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsm4ekeyq_u32", + "name": "vshll_n_s32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "int32x2_t a", + "const int n" ], "return_type": { - "value": "uint32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2S" }, - "b": {} + "n": { + "minimum": 0, + "maximum": 32 + } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SM4EKEY" + "SSHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsm4eq_u32", + "name": "vshll_n_s8", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "int8x8_t a", + "const int n" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.8B" }, - "b": {} + "n": { + "minimum": 0, + "maximum": 8 + } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SM4E" + "SSHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqadd_u16", + "name": "vshll_n_u16", "arguments": [ "uint16x4_t a", - "int16x4_t b" + "const int n" ], "return_type": { - "value": "uint16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { "register": "Vn.4H" + }, + "n": { + "minimum": 0, + "maximum": 16 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USQADD" + "USHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqadd_u32", + "name": "vshll_n_u32", "arguments": [ "uint32x2_t a", - "int32x2_t b" + "const int n" ], "return_type": { - "value": "uint32x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { "register": "Vn.2S" + }, + "n": { + "minimum": 0, + "maximum": 32 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USQADD" + "USHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqadd_u64", + "name": "vshll_n_u8", "arguments": [ - "uint64x1_t a", - "int64x1_t b" + "uint8x8_t a", + "const int n" ], "return_type": { - "value": "uint64x1_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.8B" }, - "b": { - "register": "Dn" + "n": { + "minimum": 0, + "maximum": 8 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USQADD" + "USHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqadd_u8", + "name": "vshlq_n_s16", "arguments": [ - "uint8x8_t a", - "int8x8_t b" + "int16x8_t a", + "const int n" ], "return_type": { - "value": "uint8x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vn.8H" }, - "b": { - "register": "Vn.8B" + "n": { + "minimum": 0, + "maximum": 15 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USQADD" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqaddb_u8", + "name": "vshlq_n_s32", "arguments": [ - "uint8_t a", - "int8_t b" + "int32x4_t a", + "const int n" ], "return_type": { - "value": "uint8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Bd" + "register": "Vn.4S" }, - "b": { - "register": "Bn" + "n": { + "minimum": 0, + "maximum": 31 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USQADD" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqaddd_u64", + "name": "vshlq_n_s64", "arguments": [ - "uint64_t a", - "int64_t b" + "int64x2_t a", + "const int n" ], "return_type": { - "value": "uint64_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.2D" }, - "b": { - "register": "Dn" + "n": { + "minimum": 0, + "maximum": 63 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USQADD" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqaddh_u16", + "name": "vshlq_n_s8", "arguments": [ - "uint16_t a", - "int16_t b" + "int8x16_t a", + "const int n" ], "return_type": { - "value": "uint16_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Hd" + "register": "Vn.16B" }, - "b": { - "register": "Hn" + "n": { + "minimum": 0, + "maximum": 7 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USQADD" + 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} }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USQADD" + "SSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqrt_f16", + "name": "vshlq_s32", "arguments": [ - "float16x4_t a" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "float16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FSQRT" + "SSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqrt_f32", + "name": "vshlq_s64", "arguments": [ - "float32x2_t a" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "float32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FSQRT" + "SSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqrt_f64", + "name": "vshlq_s8", "arguments": [ - "float64x1_t a" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "float64x1_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FSQRT" + "SSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqrth_f16", + "name": "vshlq_u16", "arguments": [ - "float16_t a" + "uint16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "float16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FSQRT" + "USHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqrtq_f16", + "name": "vshlq_u32", "arguments": [ - "float16x8_t a" + "uint32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "float16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FSQRT" + "USHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqrtq_f32", + "name": "vshlq_u64", "arguments": [ - "float32x4_t a" + "uint64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "float32x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FSQRT" + "USHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqrtq_f64", + "name": "vshlq_u8", "arguments": [ - "float64x2_t a" + "uint8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "float64x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FSQRT" + "USHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsra_n_s16", + "name": "vshr_n_s16", "arguments": [ "int16x4_t a", - "int16x4_t b", "const int n" ], "return_type": { @@ -98749,9 +294572,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { "register": "Vn.4H" }, "n": { @@ -98766,16 +294586,15 @@ ], "instructions": [ [ - "SSRA" + "SSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsra_n_s32", + "name": "vshr_n_s32", "arguments": [ "int32x2_t a", - "int32x2_t b", "const int n" ], "return_type": { @@ -98783,9 +294602,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { "register": "Vn.2S" }, "n": { @@ -98800,16 +294616,15 @@ ], "instructions": [ [ - "SSRA" + "SSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsra_n_s64", + "name": "vshr_n_s64", "arguments": [ "int64x1_t a", - "int64x1_t b", "const int n" ], "return_type": { @@ -98817,9 +294632,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { "register": "Dn" }, "n": { @@ -98834,16 +294646,15 @@ ], "instructions": [ [ - "SSRA" + "SSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsra_n_s8", + "name": "vshr_n_s8", "arguments": [ "int8x8_t a", - "int8x8_t b", "const int n" ], "return_type": { @@ -98851,9 +294662,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "b": { "register": "Vn.8B" }, "n": { @@ -98868,16 +294676,15 @@ ], "instructions": [ [ - "SSRA" + "SSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsra_n_u16", + "name": "vshr_n_u16", "arguments": [ "uint16x4_t a", - "uint16x4_t b", "const int n" ], "return_type": { @@ -98885,9 +294692,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { "register": "Vn.4H" }, "n": { @@ -98902,16 +294706,15 @@ ], "instructions": [ [ - "USRA" + "USHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsra_n_u32", + "name": "vshr_n_u32", "arguments": [ "uint32x2_t a", - "uint32x2_t b", "const int n" ], "return_type": { @@ -98919,9 +294722,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { "register": "Vn.2S" }, "n": { @@ -98936,16 +294736,15 @@ ], "instructions": [ [ - "USRA" + "USHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsra_n_u64", + "name": "vshr_n_u64", "arguments": [ "uint64x1_t a", - "uint64x1_t b", "const int n" ], "return_type": { @@ -98953,9 +294752,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { "register": "Dn" }, "n": { @@ -98970,16 +294766,15 @@ ], "instructions": [ [ - "USRA" + "USHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsra_n_u8", + "name": "vshr_n_u8", "arguments": [ "uint8x8_t a", - "uint8x8_t b", "const int n" ], "return_type": { @@ -98987,9 +294782,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "b": { "register": "Vn.8B" }, "n": { @@ -99004,16 +294796,15 @@ ], "instructions": [ [ - "USRA" + "USHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsrad_n_s64", + "name": "vshrd_n_s64", "arguments": [ "int64_t a", - "int64_t b", "const int n" ], "return_type": { @@ -99021,9 +294812,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { "register": "Dn" }, "n": { @@ -99036,16 +294824,15 @@ ], "instructions": [ [ - "SSRA" + "SSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsrad_n_u64", + "name": "vshrd_n_u64", "arguments": [ "uint64_t a", - "uint64_t b", "const int n" ], "return_type": { @@ -99053,9 +294840,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { "register": "Dn" }, "n": { @@ -99068,152 +294852,144 @@ ], "instructions": [ [ - "USRA" + "USHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsraq_n_s16", + "name": "vshrn_high_n_s16", "arguments": [ + "int8x8_t r", "int16x8_t a", - "int16x8_t b", "const int n" ], "return_type": { - "value": "int16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { "register": "Vn.8H" }, "n": { "minimum": 1, - "maximum": 16 + "maximum": 8 + }, + "r": { + "register": "Vd.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SSRA" + "SHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsraq_n_s32", + "name": "vshrn_high_n_s32", "arguments": [ + "int16x4_t r", "int32x4_t a", - "int32x4_t b", "const int n" ], "return_type": { - "value": "int32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.4S" }, "n": { "minimum": 1, - "maximum": 32 + "maximum": 16 + }, + "r": { + "register": "Vd.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SSRA" + "SHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsraq_n_s64", + "name": "vshrn_high_n_s64", "arguments": [ + "int32x2_t r", "int64x2_t a", - "int64x2_t b", "const int n" ], "return_type": { - "value": "int64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { "register": "Vn.2D" }, "n": { "minimum": 1, - "maximum": 64 + "maximum": 32 + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SSRA" + "SHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsraq_n_s8", + "name": "vshrn_high_n_u16", "arguments": [ - "int8x16_t a", - "int8x16_t b", + "uint8x8_t r", + "uint16x8_t a", "const int n" ], "return_type": { - "value": "int8x16_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "b": { - "register": "Vn.16B" + "register": "Vn.8H" }, "n": { "minimum": 1, "maximum": 8 + }, + "r": { + "register": "Vd.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SSRA" + "SHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsraq_n_u16", + "name": "vshrn_high_n_u32", "arguments": [ - "uint16x8_t a", - "uint16x8_t b", + "uint16x4_t r", + "uint32x4_t a", "const int n" ], "return_type": { @@ -99221,33 +294997,31 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.8H" + "register": "Vn.4S" }, "n": { "minimum": 1, "maximum": 16 + }, + "r": { + "register": "Vd.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USRA" + "SHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsraq_n_u32", + "name": "vshrn_high_n_u64", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", + "uint32x2_t r", + "uint64x2_t a", "const int n" ], "return_type": { @@ -99255,14 +295029,42 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4S" + "register": "Vn.2D" }, "n": { "minimum": 1, "maximum": 32 + }, + "r": { + "register": "Vd.2S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHRN2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vshrn_n_s16", + "arguments": [ + "int16x8_t a", + "const int n" + ], + "return_type": { + "value": "int8x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -99272,31 +295074,27 @@ ], "instructions": [ [ - "USRA" + "SHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsraq_n_u64", + "name": "vshrn_n_s32", "arguments": [ - "uint64x2_t a", - "uint64x2_t b", + "int32x4_t a", "const int n" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.2D" + "register": "Vn.4S" }, "n": { "minimum": 1, - "maximum": 64 + "maximum": 16 } }, "Architectures": [ @@ -99306,31 +295104,27 @@ ], "instructions": [ [ - "USRA" + "SHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsraq_n_u8", + "name": "vshrn_n_s64", "arguments": [ - "uint8x16_t a", - "uint8x16_t b", + "int64x2_t a", "const int n" ], "return_type": { - "value": "uint8x16_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "b": { - "register": "Vn.16B" + "register": "Vn.2D" }, "n": { "minimum": 1, - "maximum": 8 + "maximum": 32 } }, "Architectures": [ @@ -99340,31 +295134,27 @@ ], "instructions": [ [ - "USRA" + "SHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsri_n_p16", + "name": "vshrn_n_u16", "arguments": [ - "poly16x4_t a", - "poly16x4_t b", + "uint16x8_t a", "const int n" ], "return_type": { - "value": "poly16x4_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" + "register": "Vn.8H" }, "n": { "minimum": 1, - "maximum": 16 + "maximum": 8 } }, "Architectures": [ @@ -99374,64 +295164,57 @@ ], "instructions": [ [ - "SRI" + "SHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsri_n_p64", + "name": "vshrn_n_u32", "arguments": [ - "poly64x1_t a", - "poly64x1_t b", + "uint32x4_t a", "const int n" ], "return_type": { - "value": "poly64x1_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { - "register": "Dn" + "register": "Vn.4S" }, "n": { "minimum": 1, - "maximum": 64 + "maximum": 16 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "SRI" + "SHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsri_n_p8", + "name": "vshrn_n_u64", "arguments": [ - "poly8x8_t a", - "poly8x8_t b", + "uint64x2_t a", "const int n" ], "return_type": { - "value": "poly8x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "b": { - "register": "Vn.8B" + "register": "Vn.2D" }, "n": { "minimum": 1, - "maximum": 8 + "maximum": 32 } }, "Architectures": [ @@ -99441,27 +295224,23 @@ ], "instructions": [ [ - "SRI" + "SHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsri_n_s16", + "name": "vshrq_n_s16", "arguments": [ - "int16x4_t a", - "int16x4_t b", + "int16x8_t a", "const int n" ], "return_type": { - "value": "int16x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" + "register": "Vn.8H" }, "n": { "minimum": 1, @@ -99475,27 +295254,23 @@ ], "instructions": [ [ - "SRI" + "SSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsri_n_s32", + "name": "vshrq_n_s32", "arguments": [ - "int32x2_t a", - "int32x2_t b", + "int32x4_t a", "const int n" ], "return_type": { - "value": "int32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.2S" + "register": "Vn.4S" }, "n": { "minimum": 1, @@ -99509,27 +295284,23 @@ ], "instructions": [ [ - "SRI" + "SSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsri_n_s64", + "name": "vshrq_n_s64", "arguments": [ - "int64x1_t a", - "int64x1_t b", + "int64x2_t a", "const int n" ], "return_type": { - "value": "int64x1_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { - "register": "Dn" + "register": "Vn.2D" }, "n": { "minimum": 1, @@ -99543,27 +295314,23 @@ ], "instructions": [ [ - "SRI" + "SSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsri_n_s8", + "name": "vshrq_n_s8", "arguments": [ - "int8x8_t a", - "int8x8_t b", + "int8x16_t a", "const int n" ], "return_type": { - "value": "int8x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "b": { - "register": "Vn.8B" + "register": "Vn.16B" }, "n": { "minimum": 1, @@ -99577,27 +295344,23 @@ ], "instructions": [ [ - "SRI" + "SSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsri_n_u16", + "name": "vshrq_n_u16", "arguments": [ - "uint16x4_t a", - "uint16x4_t b", + "uint16x8_t a", "const int n" ], "return_type": { - "value": "uint16x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" + "register": "Vn.8H" }, "n": { "minimum": 1, @@ -99611,27 +295374,23 @@ ], "instructions": [ [ - "SRI" + "USHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsri_n_u32", + "name": "vshrq_n_u32", "arguments": [ - "uint32x2_t a", - "uint32x2_t b", + "uint32x4_t a", "const int n" ], "return_type": { - "value": "uint32x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.2S" + "register": "Vn.4S" }, "n": { "minimum": 1, @@ -99645,27 +295404,23 @@ ], "instructions": [ [ - "SRI" + "USHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsri_n_u64", + "name": "vshrq_n_u64", "arguments": [ - "uint64x1_t a", - "uint64x1_t b", + "uint64x2_t a", "const int n" ], "return_type": { - "value": "uint64x1_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { - "register": "Dn" + "register": "Vn.2D" }, "n": { "minimum": 1, @@ -99679,27 +295434,23 @@ ], "instructions": [ [ - "SRI" + "USHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsri_n_u8", + "name": "vshrq_n_u8", "arguments": [ - "uint8x8_t a", - "uint8x8_t b", + "uint8x16_t a", "const int n" ], "return_type": { - "value": "uint8x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "b": { - "register": "Vn.8B" + "register": "Vn.16B" }, "n": { "minimum": 1, @@ -99713,52 +295464,54 @@ ], "instructions": [ [ - "SRI" + "USHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsrid_n_s64", + "name": "vsli_n_p16", "arguments": [ - "int64_t a", - "int64_t b", + "poly16x4_t a", + "poly16x4_t b", "const int n" ], "return_type": { - "value": "int64_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vd.4H" }, "b": { - "register": "Dn" + "register": "Vn.4H" }, "n": { - "minimum": 1, - "maximum": 64 + "minimum": 0, + "maximum": 15 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsrid_n_u64", + "name": "vsli_n_p64", "arguments": [ - "uint64_t a", - "uint64_t b", + "poly64x1_t a", + "poly64x1_t b", "const int n" ], "return_type": { - "value": "uint64_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { @@ -99768,40 +295521,41 @@ "register": "Dn" }, "n": { - "minimum": 1, - "maximum": 64 + "minimum": 0, + "maximum": 63 } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsriq_n_p16", + "name": "vsli_n_p8", "arguments": [ - "poly16x8_t a", - "poly16x8_t b", + "poly8x8_t a", + "poly8x8_t b", "const int n" ], "return_type": { - "value": "poly16x8_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.8B" }, "b": { - "register": "Vn.8H" + "register": "Vn.8B" }, "n": { - "minimum": 1, - "maximum": 16 + "minimum": 0, + "maximum": 7 } }, "Architectures": [ @@ -99811,64 +295565,65 @@ ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsriq_n_p64", + "name": "vsli_n_s16", "arguments": [ - "poly64x2_t a", - "poly64x2_t b", + "int16x4_t a", + "int16x4_t b", "const int n" ], "return_type": { - "value": "poly64x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.4H" }, "b": { - "register": "Vn.2D" + "register": "Vn.4H" }, "n": { - "minimum": 1, - "maximum": 64 + "minimum": 0, + "maximum": 15 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsriq_n_p8", + "name": "vsli_n_s32", "arguments": [ - "poly8x16_t a", - "poly8x16_t b", + "int32x2_t a", + "int32x2_t b", "const int n" ], "return_type": { - "value": "poly8x16_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.2S" }, "b": { - "register": "Vn.16B" + "register": "Vn.2S" }, "n": { - "minimum": 1, - "maximum": 8 + "minimum": 0, + "maximum": 31 } }, "Architectures": [ @@ -99878,31 +295633,31 @@ ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsriq_n_s16", + "name": "vsli_n_s64", "arguments": [ - "int16x8_t a", - "int16x8_t b", + "int64x1_t a", + "int64x1_t b", "const int n" ], "return_type": { - "value": "int16x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Dd" }, "b": { - "register": "Vn.8H" + "register": "Dn" }, "n": { - "minimum": 1, - "maximum": 16 + "minimum": 0, + "maximum": 63 } }, "Architectures": [ @@ -99912,31 +295667,31 @@ ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsriq_n_s32", + "name": "vsli_n_s8", "arguments": [ - "int32x4_t a", - "int32x4_t b", + "int8x8_t a", + "int8x8_t b", "const int n" ], "return_type": { - "value": "int32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.8B" }, "b": { - "register": "Vn.4S" + "register": "Vn.8B" }, "n": { - "minimum": 1, - "maximum": 32 + "minimum": 0, + "maximum": 7 } }, "Architectures": [ @@ -99946,31 +295701,31 @@ ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsriq_n_s64", + "name": "vsli_n_u16", "arguments": [ - "int64x2_t a", - "int64x2_t b", + "uint16x4_t a", + "uint16x4_t b", "const int n" ], "return_type": { - "value": "int64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.4H" }, "b": { - "register": "Vn.2D" + "register": "Vn.4H" }, "n": { - "minimum": 1, - "maximum": 64 + "minimum": 0, + "maximum": 15 } }, "Architectures": [ @@ -99980,31 +295735,31 @@ ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsriq_n_s8", + "name": "vsli_n_u32", "arguments": [ - "int8x16_t a", - "int8x16_t b", + "uint32x2_t a", + "uint32x2_t b", "const int n" ], "return_type": { - "value": "int8x16_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.2S" }, "b": { - "register": "Vn.16B" + "register": "Vn.2S" }, "n": { - "minimum": 1, - "maximum": 8 + "minimum": 0, + "maximum": 31 } }, "Architectures": [ @@ -100014,31 +295769,31 @@ ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsriq_n_u16", + "name": "vsli_n_u64", "arguments": [ - "uint16x8_t a", - "uint16x8_t b", + "uint64x1_t a", + "uint64x1_t b", "const int n" ], "return_type": { - "value": "uint16x8_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Dd" }, "b": { - "register": "Vn.8H" + "register": "Dn" }, "n": { - "minimum": 1, - "maximum": 16 + "minimum": 0, + "maximum": 63 } }, "Architectures": [ @@ -100048,31 +295803,31 @@ ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsriq_n_u32", + "name": "vsli_n_u8", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", + "uint8x8_t a", + "uint8x8_t b", "const int n" ], "return_type": { - "value": "uint32x4_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.8B" }, "b": { - "register": "Vn.4S" + "register": "Vn.8B" }, "n": { - "minimum": 1, - "maximum": 32 + "minimum": 0, + "maximum": 7 } }, "Architectures": [ @@ -100082,94 +295837,95 @@ ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsriq_n_u64", + "name": "vslid_n_s64", "arguments": [ - "uint64x2_t a", - "uint64x2_t b", + "int64_t a", + "int64_t b", "const int n" ], "return_type": { - "value": "uint64x2_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Dd" }, "b": { - "register": "Vn.2D" + "register": "Dn" }, "n": { - "minimum": 1, - "maximum": 64 + "minimum": 0, + "maximum": 63 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsriq_n_u8", + "name": "vslid_n_u64", "arguments": [ - "uint8x16_t a", - "uint8x16_t b", + "uint64_t a", + "uint64_t b", "const int n" ], "return_type": { - "value": "uint8x16_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Dd" }, "b": { - "register": "Vn.16B" + "register": "Dn" }, "n": { - "minimum": 1, - "maximum": 8 + "minimum": 0, + "maximum": 63 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f16", + "name": "vsliq_n_p16", "arguments": [ - "float16_t * ptr", - "float16x4_t val" + "poly16x8_t a", + "poly16x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "poly16x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8H" }, - "val": { - "register": "Vt.4H" + "b": { + "register": "Vn.8H" + }, + "n": { + "minimum": 0, + "maximum": 15 } }, "Architectures": [ @@ -100179,55 +295935,64 @@ ], "instructions": [ [ - "ST1" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f16_x2", + "name": "vsliq_n_p64", "arguments": [ - "float16_t * ptr", - "float16x4x2_t val" + "poly64x2_t a", + "poly64x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "poly64x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2D" }, - "val": { - "register": "Vt2.4H" + "b": { + "register": "Vn.2D" + }, + "n": { + "minimum": 0, + "maximum": 63 } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "ST1" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f16_x3", + "name": "vsliq_n_p8", "arguments": [ - "float16_t * ptr", - "float16x4x3_t val" + "poly8x16_t a", + "poly8x16_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.16B" }, - "val": { - "register": "Vt3.4H" + "b": { + "register": "Vn.16B" + }, + "n": { + "minimum": 0, + "maximum": 7 } }, "Architectures": [ @@ -100237,26 +296002,31 @@ ], "instructions": [ [ - "ST1" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f16_x4", + "name": "vsliq_n_s16", "arguments": [ - "float16_t * ptr", - "float16x4x4_t val" + "int16x8_t a", + "int16x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int16x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8H" }, - "val": { - "register": "Vt4.4H" + "b": { + "register": "Vn.8H" + }, + "n": { + "minimum": 0, + "maximum": 15 } }, "Architectures": [ @@ -100266,26 +296036,31 @@ ], "instructions": [ [ - "ST1" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f32", + "name": "vsliq_n_s32", "arguments": [ - "float32_t * ptr", - "float32x2_t val" + "int32x4_t a", + "int32x4_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int32x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4S" }, - "val": { - "register": "Vt.2S" + "b": { + "register": "Vn.4S" + }, + "n": { + "minimum": 0, + "maximum": 31 } }, "Architectures": [ @@ -100295,26 +296070,31 @@ ], "instructions": [ [ - "ST1" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f32_x2", + "name": "vsliq_n_s64", "arguments": [ - "float32_t * ptr", - "float32x2x2_t val" + "int64x2_t a", + "int64x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int64x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2D" }, - "val": { - "register": "Vt2.2S" + "b": { + "register": "Vn.2D" + }, + "n": { + "minimum": 0, + "maximum": 63 } }, "Architectures": [ @@ -100324,26 +296104,31 @@ ], "instructions": [ [ - "ST1" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f32_x3", + "name": "vsliq_n_s8", "arguments": [ - "float32_t * ptr", - "float32x2x3_t val" + "int8x16_t a", + "int8x16_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int8x16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.16B" }, - "val": { - "register": "Vt3.2S" + "b": { + "register": "Vn.16B" + }, + "n": { + "minimum": 0, + "maximum": 7 } }, "Architectures": [ @@ -100353,26 +296138,31 @@ ], "instructions": [ [ - "ST1" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f32_x4", + "name": "vsliq_n_u16", "arguments": [ - "float32_t * ptr", - "float32x2x4_t val" + "uint16x8_t a", + "uint16x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8H" }, - "val": { - "register": "Vt4.2S" + "b": { + "register": "Vn.8H" + }, + "n": { + "minimum": 0, + "maximum": 15 } }, "Architectures": [ @@ -100382,107 +296172,132 @@ ], "instructions": [ [ - "ST1" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f64", + "name": "vsliq_n_u32", "arguments": [ - "float64_t * ptr", - "float64x1_t val" + "uint32x4_t a", + "uint32x4_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4S" }, - "val": { - "register": "Vt.1D" + "b": { + "register": "Vn.4S" + }, + "n": { + "minimum": 0, + "maximum": 31 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST1" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f64_x2", + "name": "vsliq_n_u64", "arguments": [ - "float64_t * ptr", - "float64x1x2_t val" + "uint64x2_t a", + "uint64x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2D" }, - "val": { - "register": "Vt2.1D" + "b": { + "register": "Vn.2D" + }, + "n": { + "minimum": 0, + "maximum": 63 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST1" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f64_x3", + "name": "vsliq_n_u8", "arguments": [ - "float64_t * ptr", - "float64x1x3_t val" + "uint8x16_t a", + "uint8x16_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.16B" }, - "val": { - "register": "Vt3.1D" + "b": { + "register": "Vn.16B" + }, + "n": { + "minimum": 0, + "maximum": 7 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST1" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f64_x4", + "name": "vsm3partw1q_u32", "arguments": [ - "float64_t * ptr", - "float64x1x4_t val" + "uint32x4_t a", + "uint32x4_t b", + "uint32x4_t c" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4S" }, - "val": { - "register": "Vt4.1D" + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" } }, "Architectures": [ @@ -100490,99 +296305,97 @@ ], "instructions": [ [ - "ST1" + "SM3PARTW1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_f16", + "name": "vsm3partw2q_u32", "arguments": [ - "float16_t * ptr", - "float16x4_t val", - "const int lane" + "uint32x4_t a", + "uint32x4_t b", + "uint32x4_t c" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "a": { + "register": "Vd.4S" }, - "ptr": { - "register": "Xn" + "b": { + "register": "Vn.4S" }, - "val": { - "register": "Vt.4H" + "c": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "SM3PARTW2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_f32", + "name": "vsm3ss1q_u32", "arguments": [ - "float32_t * ptr", - "float32x2_t val", - "const int lane" + "uint32x4_t a", + "uint32x4_t b", + "uint32x4_t c" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "a": { + "register": "Vn.4S" }, - "ptr": { - "register": "Xn" + "b": { + "register": "Vm.4S" }, - "val": { - "register": "Vt.2S" + "c": { + "register": "Va.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "SM3SS1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_f64", + "name": "vsm3tt1aq_u32", "arguments": [ - "float64_t * ptr", - "float64x1_t val", - "const int lane" + "uint32x4_t a", + "uint32x4_t b", + "uint32x4_t c", + "const int imm2" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "a": { + "register": "Vd.4S" }, - "ptr": { - "register": "Xn" + "b": { + "register": "Vn.4S" }, - "val": { - "register": "Vt.1D" + "c": { + "register": "Vm.4S" + }, + "imm2": { + "minimum": 0, + "maximum": 3 } }, "Architectures": [ @@ -100590,772 +296403,679 @@ ], "instructions": [ [ - "ST1" + "SM3TT1A" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_p16", + "name": "vsm3tt1bq_u32", "arguments": [ - "poly16_t * ptr", - "poly16x4_t val", - "const int lane" + "uint32x4_t a", + "uint32x4_t b", + "uint32x4_t c", + "const int imm2" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "a": { + "register": "Vd.4S" }, - "ptr": { - "register": "Xn" + "b": { + "register": "Vn.4S" }, - "val": { - "register": "Vt.4H" + "c": { + "register": "Vm.4S" + }, + "imm2": { + "minimum": 0, + "maximum": 3 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "SM3TT1B" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_p64", + "name": "vsm3tt2aq_u32", "arguments": [ - "poly64_t * ptr", - "poly64x1_t val", - "const int lane" + "uint32x4_t a", + "uint32x4_t b", + "uint32x4_t c", + "const int imm2" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "a": { + "register": "Vd.4S" }, - "ptr": { - "register": "Xn" + "b": { + "register": "Vn.4S" }, - "val": { - "register": "Vt.1D" + "c": { + "register": "Vm.4S" + }, + "imm2": { + "minimum": 0, + "maximum": 3 } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "ST1" + "SM3TT2A" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_p8", + "name": "vsm3tt2bq_u32", "arguments": [ - "poly8_t * ptr", - "poly8x8_t val", - "const int lane" + "uint32x4_t a", + "uint32x4_t b", + "uint32x4_t c", + "const int imm2" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "a": { + "register": "Vd.4S" }, - "ptr": { - "register": "Xn" + "b": { + "register": "Vn.4S" }, - "val": { - "register": "Vt.8B" + "c": { + "register": "Vm.4S" + }, + "imm2": { + "minimum": 0, + "maximum": 3 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "SM3TT2B" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_s16", + "name": "vsm4ekeyq_u32", "arguments": [ - "int16_t * ptr", - "int16x4_t val", - "const int lane" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.4S" }, - "val": { - "register": "Vt.4H" + "b": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "SM4EKEY" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_s32", + "name": "vsm4eq_u32", "arguments": [ - "int32_t * ptr", - "int32x2_t val", - "const int lane" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4S" }, - "val": { - "register": "Vt.2S" + "b": { + "register": "Vn.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "SM4E" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_s64", + "name": "vsqadd_u16", "arguments": [ - "int64_t * ptr", - "int64x1_t val", - "const int lane" + "uint16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "void" + "value": "uint16x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4H" }, - "val": { - "register": "Vt.1D" + "b": { + "register": "Vn.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "USQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_s8", + "name": "vsqadd_u32", "arguments": [ - "int8_t * ptr", - "int8x8_t val", - "const int lane" + "uint32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "void" + "value": "uint32x2_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2S" }, - "val": { - "register": "Vt.8B" + "b": { + "register": "Vn.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "USQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_u16", + "name": "vsqadd_u64", "arguments": [ - "uint16_t * ptr", - "uint16x4_t val", - "const int lane" + "uint64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "void" + "value": "uint64x1_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Dd" }, - "val": { - "register": "Vt.4H" + "b": { + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "USQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_u32", + "name": "vsqadd_u8", "arguments": [ - "uint32_t * ptr", - "uint32x2_t val", - "const int lane" + "uint8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "void" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8B" }, - "val": { - "register": "Vt.2S" + "b": { + "register": "Vn.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "USQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_u64", + "name": "vsqaddb_u8", "arguments": [ - "uint64_t * ptr", - "uint64x1_t val", - "const int lane" + "uint8_t a", + "int8_t b" ], "return_type": { - "value": "void" + "value": "uint8_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Bd" }, - "val": { - "register": "Vt.1D" + "b": { + "register": "Bn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "USQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_u8", + "name": "vsqaddd_u64", "arguments": [ - "uint8_t * ptr", - "uint8x8_t val", - "const int lane" + "uint64_t a", + "int64_t b" ], "return_type": { - "value": "void" + "value": "uint64_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Dd" }, - "val": { - "register": "Vt.8B" + "b": { + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "USQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_p16", + "name": "vsqaddh_u16", "arguments": [ - "poly16_t * ptr", - "poly16x4_t val" + "uint16_t a", + "int16_t b" ], "return_type": { - "value": "void" + "value": "uint16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Hd" }, - "val": { - "register": "Vt.4H" + "b": { + "register": "Hn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "USQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_p16_x2", + "name": "vsqaddq_u16", "arguments": [ - "poly16_t * ptr", - "poly16x4x2_t val" + "uint16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "void" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8H" }, - "val": { - "register": "Vt2.4H" + "b": { + "register": "Vn.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "USQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_p16_x3", + "name": "vsqaddq_u32", "arguments": [ - "poly16_t * ptr", - "poly16x4x3_t val" + "uint32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4S" }, - "val": { - "register": "Vt3.4H" + "b": { + "register": "Vn.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "USQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_p16_x4", + "name": "vsqaddq_u64", "arguments": [ - "poly16_t * ptr", - "poly16x4x4_t val" + "uint64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "void" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2D" }, - "val": { - "register": "Vt4.4H" + "b": { + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "USQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_p64", + "name": "vsqaddq_u8", "arguments": [ - "poly64_t * ptr", - "poly64x1_t val" + "uint8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "void" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.16B" }, - "val": { - "register": "Vt.1D" + "b": { + "register": "Vn.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "ST1" + "USQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_p64_x2", + "name": "vsqadds_u32", "arguments": [ - "poly64_t * ptr", - "poly64x1x2_t val" + "uint32_t a", + "int32_t b" ], "return_type": { - "value": "void" + "value": "uint32_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Sd" }, - "val": { - "register": "Vt2.1D" + "b": { + "register": "Sn" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "ST1" + "USQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_p64_x3", + "name": "vsqrt_f16", "arguments": [ - "poly64_t * ptr", - "poly64x1x3_t val" + "float16x4_t a" ], "return_type": { - "value": "void" + "value": "float16x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" - }, - "val": { - "register": "Vt3.1D" + "a": { + "register": "Vn.4H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "ST1" + "FSQRT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_p64_x4", + "name": "vsqrt_f32", "arguments": [ - "poly64_t * ptr", - "poly64x1x4_t val" + "float32x2_t a" ], "return_type": { - "value": "void" + "value": "float32x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" - }, - "val": { - "register": "Vt4.1D" + "a": { + "register": "Vn.2S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "ST1" + "FSQRT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_p8", + "name": "vsqrt_f64", "arguments": [ - "poly8_t * ptr", - "poly8x8_t val" + "float64x1_t a" ], "return_type": { - "value": "void" + "value": "float64x1_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" - }, - "val": { - "register": "Vt.8B" + "a": { + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "FSQRT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_p8_x2", + "name": "vsqrth_f16", "arguments": [ - "poly8_t * ptr", - "poly8x8x2_t val" + "float16_t a" ], "return_type": { - "value": "void" + "value": "float16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" - }, - "val": { - "register": "Vt2.8B" + "a": { + "register": "Hn" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "ST1" + "FSQRT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_p8_x3", + "name": "vsqrtq_f16", "arguments": [ - "poly8_t * ptr", - "poly8x8x3_t val" + "float16x8_t a" ], "return_type": { - "value": "void" + "value": "float16x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" - }, - "val": { - "register": "Vt3.8B" + "a": { + "register": "Vn.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "FSQRT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_p8_x4", + "name": "vsqrtq_f32", "arguments": [ - "poly8_t * ptr", - "poly8x8x4_t val" + "float32x4_t a" ], "return_type": { - "value": "void" + "value": "float32x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" - }, - "val": { - "register": "Vt4.8B" + "a": { + "register": "Vn.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "FSQRT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s16", + "name": "vsqrtq_f64", "arguments": [ - "int16_t * ptr", - "int16x4_t val" + "float64x2_t a" ], "return_type": { - "value": "void" + "value": "float64x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" - }, - "val": { - "register": "Vt.4H" + "a": { + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "FSQRT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s16_x2", + "name": "vsra_n_s16", "arguments": [ - "int16_t * ptr", - "int16x4x2_t val" + "int16x4_t a", + "int16x4_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int16x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4H" }, - "val": { - "register": "Vt2.4H" + "b": { + "register": "Vn.4H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -101365,26 +297085,31 @@ ], "instructions": [ [ - "ST1" + "SSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s16_x3", + "name": "vsra_n_s32", "arguments": [ - "int16_t * ptr", - "int16x4x3_t val" + "int32x2_t a", + "int32x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int32x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2S" }, - "val": { - "register": "Vt3.4H" + "b": { + "register": "Vn.2S" + }, + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -101394,26 +297119,31 @@ ], "instructions": [ [ - "ST1" + "SSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s16_x4", + "name": "vsra_n_s64", "arguments": [ - "int16_t * ptr", - "int16x4x4_t val" + "int64x1_t a", + "int64x1_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int64x1_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Dd" }, - "val": { - "register": "Vt4.4H" + "b": { + "register": "Dn" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -101423,26 +297153,31 @@ ], "instructions": [ [ - "ST1" + "SSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s32", + "name": "vsra_n_s8", "arguments": [ - "int32_t * ptr", - "int32x2_t val" + "int8x8_t a", + "int8x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int8x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8B" }, - "val": { - "register": "Vt.2S" + "b": { + "register": "Vn.8B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -101452,26 +297187,31 @@ ], "instructions": [ [ - "ST1" + "SSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s32_x2", + "name": "vsra_n_u16", "arguments": [ - "int32_t * ptr", - "int32x2x2_t val" + "uint16x4_t a", + "uint16x4_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint16x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4H" }, - "val": { - "register": "Vt2.2S" + "b": { + "register": "Vn.4H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -101481,26 +297221,31 @@ ], "instructions": [ [ - "ST1" + "USRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s32_x3", + "name": "vsra_n_u32", "arguments": [ - "int32_t * ptr", - "int32x2x3_t val" + "uint32x2_t a", + "uint32x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint32x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2S" }, - "val": { - "register": "Vt3.2S" + "b": { + "register": "Vn.2S" + }, + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -101510,26 +297255,31 @@ ], "instructions": [ [ - "ST1" + "USRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s32_x4", + "name": "vsra_n_u64", "arguments": [ - "int32_t * ptr", - "int32x2x4_t val" + "uint64x1_t a", + "uint64x1_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint64x1_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Dd" }, - "val": { - "register": "Vt4.2S" + "b": { + "register": "Dn" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -101539,26 +297289,31 @@ ], "instructions": [ [ - "ST1" + "USRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s64", + "name": "vsra_n_u8", "arguments": [ - "int64_t * ptr", - "int64x1_t val" + "uint8x8_t a", + "uint8x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8B" }, - "val": { - "register": "Vt.1D" + "b": { + "register": "Vn.8B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -101568,84 +297323,95 @@ ], "instructions": [ [ - "ST1" + "USRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s64_x2", + "name": "vsrad_n_s64", "arguments": [ - "int64_t * ptr", - "int64x1x2_t val" + "int64_t a", + "int64_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int64_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Dd" }, - "val": { - "register": "Vt2.1D" + "b": { + "register": "Dn" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "SSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s64_x3", + "name": "vsrad_n_u64", "arguments": [ - "int64_t * ptr", - "int64x1x3_t val" + "uint64_t a", + "uint64_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint64_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Dd" }, - "val": { - "register": "Vt3.1D" + "b": { + "register": "Dn" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "USRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s64_x4", + "name": "vsraq_n_s16", "arguments": [ - "int64_t * ptr", - "int64x1x4_t val" + "int16x8_t a", + "int16x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int16x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8H" }, - "val": { - "register": "Vt4.1D" + "b": { + "register": "Vn.8H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -101655,26 +297421,31 @@ ], "instructions": [ [ - "ST1" + "SSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s8", + "name": "vsraq_n_s32", "arguments": [ - "int8_t * ptr", - "int8x8_t val" + "int32x4_t a", + "int32x4_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int32x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4S" }, - "val": { - "register": "Vt.8B" + "b": { + "register": "Vn.4S" + }, + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -101684,26 +297455,31 @@ ], "instructions": [ [ - "ST1" + "SSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s8_x2", + "name": "vsraq_n_s64", "arguments": [ - "int8_t * ptr", - "int8x8x2_t val" + "int64x2_t a", + "int64x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int64x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2D" }, - "val": { - "register": "Vt2.8B" + "b": { + "register": "Vn.2D" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -101713,26 +297489,31 @@ ], "instructions": [ [ - "ST1" + "SSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s8_x3", + "name": "vsraq_n_s8", "arguments": [ - "int8_t * ptr", - "int8x8x3_t val" + "int8x16_t a", + "int8x16_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int8x16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.16B" }, - "val": { - "register": "Vt3.8B" + "b": { + "register": "Vn.16B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -101742,26 +297523,31 @@ ], "instructions": [ [ - "ST1" + "SSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s8_x4", + "name": "vsraq_n_u16", "arguments": [ - "int8_t * ptr", - "int8x8x4_t val" + "uint16x8_t a", + "uint16x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8H" }, - "val": { - "register": "Vt4.8B" + "b": { + "register": "Vn.8H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -101771,26 +297557,31 @@ ], "instructions": [ [ - "ST1" + "USRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u16", + "name": "vsraq_n_u32", "arguments": [ - "uint16_t * ptr", - "uint16x4_t val" + "uint32x4_t a", + "uint32x4_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4S" }, - "val": { - "register": "Vt.4H" + "b": { + "register": "Vn.4S" + }, + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -101800,26 +297591,31 @@ ], "instructions": [ [ - "ST1" + "USRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u16_x2", + "name": "vsraq_n_u64", "arguments": [ - "uint16_t * ptr", - "uint16x4x2_t val" + "uint64x2_t a", + "uint64x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2D" }, - "val": { - "register": "Vt2.4H" + "b": { + "register": "Vn.2D" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -101829,26 +297625,31 @@ ], "instructions": [ [ - "ST1" + "USRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u16_x3", + "name": "vsraq_n_u8", "arguments": [ - "uint16_t * ptr", - "uint16x4x3_t val" + "uint8x16_t a", + "uint8x16_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.16B" }, - "val": { - "register": "Vt3.4H" + "b": { + "register": "Vn.16B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -101858,26 +297659,31 @@ ], "instructions": [ [ - "ST1" + "USRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u16_x4", + "name": "vsri_n_p16", "arguments": [ - "uint16_t * ptr", - "uint16x4x4_t val" + "poly16x4_t a", + "poly16x4_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "poly16x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4H" }, - "val": { - "register": "Vt4.4H" + "b": { + "register": "Vn.4H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -101887,55 +297693,64 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u32", + "name": "vsri_n_p64", "arguments": [ - "uint32_t * ptr", - "uint32x2_t val" + "poly64x1_t a", + "poly64x1_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "poly64x1_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Dd" }, - "val": { - "register": "Vt.2S" + "b": { + "register": "Dn" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u32_x2", + "name": "vsri_n_p8", "arguments": [ - "uint32_t * ptr", - "uint32x2x2_t val" + "poly8x8_t a", + "poly8x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "poly8x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8B" }, - "val": { - "register": "Vt2.2S" + "b": { + "register": "Vn.8B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -101945,26 +297760,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u32_x3", + "name": "vsri_n_s16", "arguments": [ - "uint32_t * ptr", - "uint32x2x3_t val" + "int16x4_t a", + "int16x4_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int16x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4H" }, - "val": { - "register": "Vt3.2S" + "b": { + "register": "Vn.4H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -101974,26 +297794,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u32_x4", + "name": "vsri_n_s32", "arguments": [ - "uint32_t * ptr", - "uint32x2x4_t val" + "int32x2_t a", + "int32x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int32x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2S" }, - "val": { - "register": "Vt4.2S" + "b": { + "register": "Vn.2S" + }, + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -102003,26 +297828,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u64", + "name": "vsri_n_s64", "arguments": [ - "uint64_t * ptr", - "uint64x1_t val" + "int64x1_t a", + "int64x1_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int64x1_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Dd" }, - "val": { - "register": "Vt.1D" + "b": { + "register": "Dn" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -102032,26 +297862,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u64_x2", + "name": "vsri_n_s8", "arguments": [ - "uint64_t * ptr", - "uint64x1x2_t val" + "int8x8_t a", + "int8x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int8x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8B" }, - "val": { - "register": "Vt2.1D" + "b": { + "register": "Vn.8B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -102061,26 +297896,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u64_x3", + "name": "vsri_n_u16", "arguments": [ - "uint64_t * ptr", - "uint64x1x3_t val" + "uint16x4_t a", + "uint16x4_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint16x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4H" }, - "val": { - "register": "Vt3.1D" + "b": { + "register": "Vn.4H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -102090,26 +297930,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u64_x4", + "name": "vsri_n_u32", "arguments": [ - "uint64_t * ptr", - "uint64x1x4_t val" + "uint32x2_t a", + "uint32x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint32x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2S" }, - "val": { - "register": "Vt4.1D" + "b": { + "register": "Vn.2S" + }, + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -102119,26 +297964,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u8", + "name": "vsri_n_u64", "arguments": [ - "uint8_t * ptr", - "uint8x8_t val" + "uint64x1_t a", + "uint64x1_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint64x1_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Dd" }, - "val": { - "register": "Vt.8B" + "b": { + "register": "Dn" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -102148,26 +297998,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u8_x2", + "name": "vsri_n_u8", "arguments": [ - "uint8_t * ptr", - "uint8x8x2_t val" + "uint8x8_t a", + "uint8x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8B" }, - "val": { - "register": "Vt2.8B" + "b": { + "register": "Vn.8B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -102177,84 +298032,95 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u8_x3", + "name": "vsrid_n_s64", "arguments": [ - "uint8_t * ptr", - "uint8x8x3_t val" + "int64_t a", + "int64_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int64_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Dd" }, - "val": { - "register": "Vt3.8B" + "b": { + "register": "Dn" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u8_x4", + "name": "vsrid_n_u64", "arguments": [ - "uint8_t * ptr", - "uint8x8x4_t val" + "uint64_t a", + "uint64_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint64_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Dd" }, - "val": { - "register": "Vt4.8B" + "b": { + "register": "Dn" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f16", + "name": "vsriq_n_p16", "arguments": [ - "float16_t * ptr", - "float16x8_t val" + "poly16x8_t a", + "poly16x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "poly16x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8H" }, - "val": { - "register": "Vt.8H" + "b": { + "register": "Vn.8H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -102264,55 +298130,64 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f16_x2", + "name": "vsriq_n_p64", "arguments": [ - "float16_t * ptr", - "float16x8x2_t val" + "poly64x2_t a", + "poly64x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "poly64x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2D" }, - "val": { - "register": "Vt2.8H" + "b": { + "register": "Vn.2D" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f16_x3", + "name": "vsriq_n_p8", "arguments": [ - "float16_t * ptr", - "float16x8x3_t val" + "poly8x16_t a", + "poly8x16_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.16B" }, - "val": { - "register": "Vt3.8H" + "b": { + "register": "Vn.16B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -102322,26 +298197,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f16_x4", + "name": "vsriq_n_s16", "arguments": [ - "float16_t * ptr", - "float16x8x4_t val" + "int16x8_t a", + "int16x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int16x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8H" }, - "val": { - "register": "Vt4.8H" + "b": { + "register": "Vn.8H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -102351,26 +298231,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f32", + "name": "vsriq_n_s32", "arguments": [ - "float32_t * ptr", - "float32x4_t val" + "int32x4_t a", + "int32x4_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int32x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4S" }, - "val": { - "register": "Vt.4S" + "b": { + "register": "Vn.4S" + }, + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -102380,26 +298265,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f32_x2", + "name": "vsriq_n_s64", "arguments": [ - "float32_t * ptr", - "float32x4x2_t val" + "int64x2_t a", + "int64x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int64x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2D" }, - "val": { - "register": "Vt2.4S" + "b": { + "register": "Vn.2D" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -102409,26 +298299,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f32_x3", + "name": "vsriq_n_s8", "arguments": [ - "float32_t * ptr", - "float32x4x3_t val" + "int8x16_t a", + "int8x16_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int8x16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.16B" }, - "val": { - "register": "Vt3.4S" + "b": { + "register": "Vn.16B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -102438,26 +298333,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f32_x4", + "name": "vsriq_n_u16", "arguments": [ - "float32_t * ptr", - "float32x4x4_t val" + "uint16x8_t a", + "uint16x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8H" }, - "val": { - "register": "Vt4.4S" + "b": { + "register": "Vn.8H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -102467,97 +298367,118 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f64", + "name": "vsriq_n_u32", "arguments": [ - "float64_t * ptr", - "float64x2_t val" + "uint32x4_t a", + "uint32x4_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4S" }, - "val": { - "register": "Vt.2D" + "b": { + "register": "Vn.4S" + }, + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f64_x2", + "name": "vsriq_n_u64", "arguments": [ - "float64_t * ptr", - "float64x2x2_t val" + "uint64x2_t a", + "uint64x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2D" }, - "val": { - "register": "Vt2.2D" + "b": { + "register": "Vn.2D" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f64_x3", + "name": "vsriq_n_u8", "arguments": [ - "float64_t * ptr", - "float64x2x3_t val" + "uint8x16_t a", + "uint8x16_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.16B" }, - "val": { - "register": "Vt3.2D" + "b": { + "register": "Vn.16B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f64_x4", + "name": "vst1_f16", "arguments": [ - "float64_t * ptr", - "float64x2x4_t val" + "float16_t * ptr", + "float16x4_t val" ], "return_type": { "value": "void" @@ -102567,10 +298488,12 @@ "register": "Xn" }, "val": { - "register": "Vt4.2D" + "register": "Vt.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -102581,25 +298504,23 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_f16", + "name": "vst1_f16_x2", "arguments": [ "float16_t * ptr", - "float16x8_t val", - "const int lane" + "float16x4x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -102615,25 +298536,26 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_f32", + "name": "vst1_f16_x3", "arguments": [ - "float32_t * ptr", - "float32x4_t val", - "const int lane" + "float16_t * ptr", + "float16x4x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.4S" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -102649,28 +298571,34 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_f64", + "name": "vst1_f16_x4", "arguments": [ - "float64_t * ptr", - "float64x2_t val", - "const int lane" + "float16_t * ptr", + "float16x4x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.2D" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -102681,25 +298609,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_p16", + "name": "vst1_f32", "arguments": [ - "poly16_t * ptr", - "poly16x8_t val", - "const int lane" + "float32_t * ptr", + "float32x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt.8H" + "register": "Vt.2S" } }, "Architectures": [ @@ -102715,28 +298638,27 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_p64", + "name": "vst1_f32_x2", "arguments": [ - "poly64_t * ptr", - "poly64x2_t val", - "const int lane" + "float32_t * ptr", + "float32x2x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.2D" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -102748,25 +298670,26 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_p8", + "name": "vst1_f32_x3", "arguments": [ - "poly8_t * ptr", - "poly8x16_t val", - "const int lane" + "float32_t * ptr", + "float32x2x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.16B" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" } }, "Architectures": [ @@ -102782,25 +298705,29 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_s16", + "name": "vst1_f32_x4", "arguments": [ - "int16_t * ptr", - "int16x8_t val", - "const int lane" + "float32_t * ptr", + "float32x2x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.8H" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { + "register": "Vt4.2S" } }, "Architectures": [ @@ -102816,30 +298743,23 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_s32", + "name": "vst1_f64", "arguments": [ - "int32_t * ptr", - "int32x4_t val", - "const int lane" + "float64_t * ptr", + "float64x1_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt.4S" + "register": "Vt.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -102850,30 +298770,26 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_s64", + "name": "vst1_f64_x2", "arguments": [ - "int64_t * ptr", - "int64x2_t val", - "const int lane" + "float64_t * ptr", + "float64x1x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -102884,30 +298800,29 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_s8", + "name": "vst1_f64_x3", "arguments": [ - "int8_t * ptr", - "int8x16_t val", - "const int lane" + "float64_t * ptr", + "float64x1x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.16B" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -102918,30 +298833,32 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_u16", + "name": "vst1_f64_x4", "arguments": [ - "uint16_t * ptr", - "uint16x8_t val", - "const int lane" + "float64_t * ptr", + "float64x1x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" }, - "ptr": { - "register": "Xn" + "val.val[2]": { + "register": "Vt3.1D" }, - "val": { - "register": "Vt.8H" + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -102952,10 +298869,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_u32", + "name": "vst1_lane_f16", "arguments": [ - "uint32_t * ptr", - "uint32x4_t val", + "float16_t * ptr", + "float16x4_t val", "const int lane" ], "return_type": { @@ -102970,7 +298887,7 @@ "register": "Xn" }, "val": { - "register": "Vt.4S" + "register": "Vt.4H" } }, "Architectures": [ @@ -102986,10 +298903,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_u64", + "name": "vst1_lane_f32", "arguments": [ - "uint64_t * ptr", - "uint64x2_t val", + "float32_t * ptr", + "float32x2_t val", "const int lane" ], "return_type": { @@ -103004,7 +298921,7 @@ "register": "Xn" }, "val": { - "register": "Vt.2D" + "register": "Vt.2S" } }, "Architectures": [ @@ -103020,10 +298937,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_u8", + "name": "vst1_lane_f64", "arguments": [ - "uint8_t * ptr", - "uint8x16_t val", + "float64_t * ptr", + "float64x1_t val", "const int lane" ], "return_type": { @@ -103032,18 +298949,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 15 + "maximum": 0 }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt.16B" + "register": "Vt.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -103054,20 +298969,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p16", + "name": "vst1_lane_p16", "arguments": [ "poly16_t * ptr", - "poly16x8_t val" + "poly16x4_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt.8H" + "register": "Vt.4H" } }, "Architectures": [ @@ -103083,24 +299003,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p16_x2", + "name": "vst1_lane_p64", "arguments": [ - "poly16_t * ptr", - "poly16x8x2_t val" + "poly64_t * ptr", + "poly64x1_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.8H" + "register": "Vt.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -103112,20 +299036,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p16_x3", + "name": "vst1_lane_p8", "arguments": [ - "poly16_t * ptr", - "poly16x8x3_t val" + "poly8_t * ptr", + "poly8x8_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt3.8H" + "register": "Vt.8B" } }, "Architectures": [ @@ -103141,20 +299070,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p16_x4", + "name": "vst1_lane_s16", "arguments": [ - "poly16_t * ptr", - "poly16x8x4_t val" + "int16_t * ptr", + "int16x4_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt4.8H" + "register": "Vt.4H" } }, "Architectures": [ @@ -103170,23 +299104,29 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p64", + "name": "vst1_lane_s32", "arguments": [ - "poly64_t * ptr", - "poly64x2_t val" + "int32_t * ptr", + "int32x2_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt.2D" + "register": "Vt.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -103198,23 +299138,29 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p64_x2", + "name": "vst1_lane_s64", "arguments": [ - "poly64_t * ptr", - "poly64x2x2_t val" + "int64_t * ptr", + "int64x1_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.2D" + "register": "Vt.1D" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -103226,20 +299172,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p64_x3", + "name": "vst1_lane_s8", "arguments": [ - "poly64_t * ptr", - "poly64x2x3_t val" + "int8_t * ptr", + "int8x8_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt3.2D" + "register": "Vt.8B" } }, "Architectures": [ @@ -103255,23 +299206,29 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p64_x4", + "name": "vst1_lane_u16", "arguments": [ - "poly64_t * ptr", - "poly64x2x4_t val" + "uint16_t * ptr", + "uint16x4_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt4.2D" + "register": "Vt.4H" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -103283,20 +299240,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p8", + "name": "vst1_lane_u32", "arguments": [ - "poly8_t * ptr", - "poly8x16_t val" + "uint32_t * ptr", + "uint32x2_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt.16B" + "register": "Vt.2S" } }, "Architectures": [ @@ -103312,20 +299274,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p8_x2", + "name": "vst1_lane_u64", "arguments": [ - "poly8_t * ptr", - "poly8x16x2_t val" + "uint64_t * ptr", + "uint64x1_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.16B" + "register": "Vt.1D" } }, "Architectures": [ @@ -103341,20 +299308,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p8_x3", + "name": "vst1_lane_u8", "arguments": [ - "poly8_t * ptr", - "poly8x16x3_t val" + "uint8_t * ptr", + "uint8x8_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt3.16B" + "register": "Vt.8B" } }, "Architectures": [ @@ -103370,10 +299342,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p8_x4", + "name": "vst1_mf8_x4", "arguments": [ - "poly8_t * ptr", - "poly8x16x4_t val" + "int8_t * ptr", + "int8x8x4_t val" ], "return_type": { "value": "void" @@ -103382,13 +299354,20 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { + "register": "Vt4.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -103399,10 +299378,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s16", + "name": "vst1_p16", "arguments": [ - "int16_t * ptr", - "int16x8_t val" + "poly16_t * ptr", + "poly16x4_t val" ], "return_type": { "value": "void" @@ -103412,7 +299391,7 @@ "register": "Xn" }, "val": { - "register": "Vt.8H" + "register": "Vt.4H" } }, "Architectures": [ @@ -103428,10 +299407,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s16_x2", + "name": "vst1_p16_x2", "arguments": [ - "int16_t * ptr", - "int16x8x2_t val" + "poly16_t * ptr", + "poly16x4x2_t val" ], "return_type": { "value": "void" @@ -103440,8 +299419,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -103457,10 +299439,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s16_x3", + "name": "vst1_p16_x3", "arguments": [ - "int16_t * ptr", - "int16x8x3_t val" + "poly16_t * ptr", + "poly16x4x3_t val" ], "return_type": { "value": "void" @@ -103469,8 +299451,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -103486,10 +299474,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s16_x4", + "name": "vst1_p16_x4", "arguments": [ - "int16_t * ptr", - "int16x8x4_t val" + "poly16_t * ptr", + "poly16x4x4_t val" ], "return_type": { "value": "void" @@ -103498,8 +299486,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ @@ -103515,10 +299512,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s32", + "name": "vst1_p64", "arguments": [ - "int32_t * ptr", - "int32x4_t val" + "poly64_t * ptr", + "poly64x1_t val" ], "return_type": { "value": "void" @@ -103528,11 +299525,10 @@ "register": "Xn" }, "val": { - "register": "Vt.4S" + "register": "Vt.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -103544,10 +299540,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s32_x2", + "name": "vst1_p64_x2", "arguments": [ - "int32_t * ptr", - "int32x4x2_t val" + "poly64_t * ptr", + "poly64x1x2_t val" ], "return_type": { "value": "void" @@ -103556,12 +299552,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.4S" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -103573,10 +299571,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s32_x3", + "name": "vst1_p64_x3", "arguments": [ - "int32_t * ptr", - "int32x4x3_t val" + "poly64_t * ptr", + "poly64x1x3_t val" ], "return_type": { "value": "void" @@ -103585,12 +299583,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4S" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -103602,10 +299605,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s32_x4", + "name": "vst1_p64_x4", "arguments": [ - "int32_t * ptr", - "int32x4x4_t val" + "poly64_t * ptr", + "poly64x1x4_t val" ], "return_type": { "value": "void" @@ -103614,12 +299617,20 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4S" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -103631,10 +299642,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s64", + "name": "vst1_p8", "arguments": [ - "int64_t * ptr", - "int64x2_t val" + "poly8_t * ptr", + "poly8x8_t val" ], "return_type": { "value": "void" @@ -103644,7 +299655,7 @@ "register": "Xn" }, "val": { - "register": "Vt.2D" + "register": "Vt.8B" } }, "Architectures": [ @@ -103660,10 +299671,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s64_x2", + "name": "vst1_p8_x2", "arguments": [ - "int64_t * ptr", - "int64x2x2_t val" + "poly8_t * ptr", + "poly8x8x2_t val" ], "return_type": { "value": "void" @@ -103672,8 +299683,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.2D" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" } }, "Architectures": [ @@ -103689,10 +299703,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s64_x3", + "name": "vst1_p8_x3", "arguments": [ - "int64_t * ptr", - "int64x2x3_t val" + "poly8_t * ptr", + "poly8x8x3_t val" ], "return_type": { "value": "void" @@ -103701,8 +299715,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2D" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" } }, "Architectures": [ @@ -103718,10 +299738,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s64_x4", + "name": "vst1_p8_x4", "arguments": [ - "int64_t * ptr", - "int64x2x4_t val" + "poly8_t * ptr", + "poly8x8x4_t val" ], "return_type": { "value": "void" @@ -103730,8 +299750,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2D" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { + "register": "Vt4.8B" } }, "Architectures": [ @@ -103747,10 +299776,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s8", + "name": "vst1_s16", "arguments": [ - "int8_t * ptr", - "int8x16_t val" + "int16_t * ptr", + "int16x4_t val" ], "return_type": { "value": "void" @@ -103760,7 +299789,7 @@ "register": "Xn" }, "val": { - "register": "Vt.16B" + "register": "Vt.4H" } }, "Architectures": [ @@ -103776,10 +299805,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s8_x2", + "name": "vst1_s16_x2", "arguments": [ - "int8_t * ptr", - "int8x16x2_t val" + "int16_t * ptr", + "int16x4x2_t val" ], "return_type": { "value": "void" @@ -103788,8 +299817,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.16B" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -103805,10 +299837,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s8_x3", + "name": "vst1_s16_x3", "arguments": [ - "int8_t * ptr", - "int8x16x3_t val" + "int16_t * ptr", + "int16x4x3_t val" ], "return_type": { "value": "void" @@ -103817,8 +299849,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.16B" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -103834,10 +299872,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s8_x4", + "name": "vst1_s16_x4", "arguments": [ - "int8_t * ptr", - "int8x16x4_t val" + "int16_t * ptr", + "int16x4x4_t val" ], "return_type": { "value": "void" @@ -103846,8 +299884,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.16B" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ @@ -103863,10 +299910,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u16", + "name": "vst1_s32", "arguments": [ - "uint16_t * ptr", - "uint16x8_t val" + "int32_t * ptr", + "int32x2_t val" ], "return_type": { "value": "void" @@ -103876,7 +299923,7 @@ "register": "Xn" }, "val": { - "register": "Vt.8H" + "register": "Vt.2S" } }, "Architectures": [ @@ -103892,10 +299939,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u16_x2", + "name": "vst1_s32_x2", "arguments": [ - "uint16_t * ptr", - "uint16x8x2_t val" + "int32_t * ptr", + "int32x2x2_t val" ], "return_type": { "value": "void" @@ -103904,8 +299951,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.8H" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" } }, "Architectures": [ @@ -103921,10 +299971,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u16_x3", + "name": "vst1_s32_x3", "arguments": [ - "uint16_t * ptr", - "uint16x8x3_t val" + "int32_t * ptr", + "int32x2x3_t val" ], "return_type": { "value": "void" @@ -103933,8 +299983,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8H" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" } }, "Architectures": [ @@ -103950,10 +300006,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u16_x4", + "name": "vst1_s32_x4", "arguments": [ - "uint16_t * ptr", - "uint16x8x4_t val" + "int32_t * ptr", + "int32x2x4_t val" ], "return_type": { "value": "void" @@ -103962,8 +300018,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8H" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { + "register": "Vt4.2S" } }, "Architectures": [ @@ -103979,10 +300044,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u32", + "name": "vst1_s64", "arguments": [ - "uint32_t * ptr", - "uint32x4_t val" + "int64_t * ptr", + "int64x1_t val" ], "return_type": { "value": "void" @@ -103992,7 +300057,7 @@ "register": "Xn" }, "val": { - "register": "Vt.4S" + "register": "Vt.1D" } }, "Architectures": [ @@ -104008,10 +300073,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u32_x2", + "name": "vst1_s64_x2", "arguments": [ - "uint32_t * ptr", - "uint32x4x2_t val" + "int64_t * ptr", + "int64x1x2_t val" ], "return_type": { "value": "void" @@ -104020,8 +300085,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.4S" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ @@ -104037,10 +300105,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u32_x3", + "name": "vst1_s64_x3", "arguments": [ - "uint32_t * ptr", - "uint32x4x3_t val" + "int64_t * ptr", + "int64x1x3_t val" ], "return_type": { "value": "void" @@ -104049,8 +300117,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4S" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ @@ -104066,10 +300140,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u32_x4", + "name": "vst1_s64_x4", "arguments": [ - "uint32_t * ptr", - "uint32x4x4_t val" + "int64_t * ptr", + "int64x1x4_t val" ], "return_type": { "value": "void" @@ -104078,8 +300152,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4S" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ @@ -104095,10 +300178,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u64", + "name": "vst1_s8", "arguments": [ - "uint64_t * ptr", - "uint64x2_t val" + "int8_t * ptr", + "int8x8_t val" ], "return_type": { "value": "void" @@ -104108,7 +300191,7 @@ "register": "Xn" }, "val": { - "register": "Vt.2D" + "register": "Vt.8B" } }, "Architectures": [ @@ -104124,10 +300207,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u64_x2", + "name": "vst1_s8_x2", "arguments": [ - "uint64_t * ptr", - "uint64x2x2_t val" + "int8_t * ptr", + "int8x8x2_t val" ], "return_type": { "value": "void" @@ -104136,8 +300219,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.2D" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" } }, "Architectures": [ @@ -104153,10 +300239,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u64_x3", + "name": "vst1_s8_x3", "arguments": [ - "uint64_t * ptr", - "uint64x2x3_t val" + "int8_t * ptr", + "int8x8x3_t val" ], "return_type": { "value": "void" @@ -104165,8 +300251,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2D" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" } }, "Architectures": [ @@ -104182,10 +300274,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u64_x4", + "name": "vst1_s8_x4", "arguments": [ - "uint64_t * ptr", - "uint64x2x4_t val" + "int8_t * ptr", + "int8x8x4_t val" ], "return_type": { "value": "void" @@ -104194,8 +300286,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2D" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { + "register": "Vt4.8B" } }, "Architectures": [ @@ -104211,10 +300312,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u8", + "name": "vst1_u16", "arguments": [ - "uint8_t * ptr", - "uint8x16_t val" + "uint16_t * ptr", + "uint16x4_t val" ], "return_type": { "value": "void" @@ -104224,7 +300325,7 @@ "register": "Xn" }, "val": { - "register": "Vt.16B" + "register": "Vt.4H" } }, "Architectures": [ @@ -104240,10 +300341,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u8_x2", + "name": "vst1_u16_x2", "arguments": [ - "uint8_t * ptr", - "uint8x16x2_t val" + "uint16_t * ptr", + "uint16x4x2_t val" ], "return_type": { "value": "void" @@ -104252,8 +300353,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.16B" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -104269,10 +300373,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u8_x3", + "name": "vst1_u16_x3", "arguments": [ - "uint8_t * ptr", - "uint8x16x3_t val" + "uint16_t * ptr", + "uint16x4x3_t val" ], "return_type": { "value": "void" @@ -104281,8 +300385,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.16B" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -104298,10 +300408,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u8_x4", + "name": "vst1_u16_x4", "arguments": [ - "uint8_t * ptr", - "uint8x16x4_t val" + "uint16_t * ptr", + "uint16x4x4_t val" ], "return_type": { "value": "void" @@ -104310,8 +300420,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.16B" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ @@ -104327,10 +300446,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst2_f16", + "name": "vst1_u32", "arguments": [ - "float16_t * ptr", - "float16x4x2_t val" + "uint32_t * ptr", + "uint32x2_t val" ], "return_type": { "value": "void" @@ -104340,7 +300459,7 @@ "register": "Xn" }, "val": { - "register": "Vt2.4H" + "register": "Vt.2S" } }, "Architectures": [ @@ -104350,16 +300469,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_f32", + "name": "vst1_u32_x2", "arguments": [ - "float32_t * ptr", - "float32x2x2_t val" + "uint32_t * ptr", + "uint32x2x2_t val" ], "return_type": { "value": "void" @@ -104368,7 +300487,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { "register": "Vt2.2S" } }, @@ -104379,16 +300501,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_f64", + "name": "vst1_u32_x3", "arguments": [ - "float64_t * ptr", - "float64x1x2_t val" + "uint32_t * ptr", + "uint32x2x3_t val" ], "return_type": { "value": "void" @@ -104397,11 +300519,19 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.1D" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -104412,25 +300542,29 @@ }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_f16", + "name": "vst1_u32_x4", "arguments": [ - "float16_t * ptr", - "float16x4x2_t val", - "const int lane" + "uint32_t * ptr", + "uint32x2x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.4H" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { + "register": "Vt4.2S" } }, "Architectures": [ @@ -104440,31 +300574,26 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_f32", + "name": "vst1_u64", "arguments": [ - "float32_t * ptr", - "float32x2x2_t val", - "const int lane" + "uint64_t * ptr", + "uint64x1_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.2S" + "register": "Vt.1D" } }, "Architectures": [ @@ -104474,63 +300603,64 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_f64", + "name": "vst1_u64_x2", "arguments": [ - "float64_t * ptr", - "float64x1x2_t val", - "const int lane" + "uint64_t * ptr", + "uint64x1x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_p16", + "name": "vst1_u64_x3", "arguments": [ - "poly16_t * ptr", - "poly16x4x2_t val", - "const int lane" + "uint64_t * ptr", + "uint64x1x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.4H" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ @@ -104540,63 +300670,35 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_p64", + "name": "vst1_u64_x4", "arguments": [ - "poly64_t * ptr", - "poly64x1x2_t val", - "const int lane" + "uint64_t * ptr", + "uint64x1x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "ST2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vst2_lane_p8", - "arguments": [ - "poly8_t * ptr", - "poly8x8x2_t val", - "const int lane" - ], - "return_type": { - "value": "void" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 }, - "ptr": { - "register": "Xn" + "val.val[2]": { + "register": "Vt3.1D" }, - "val": { - "register": "Vt2.8B" + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ @@ -104606,31 +300708,26 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_s16", + "name": "vst1_u8", "arguments": [ - "int16_t * ptr", - "int16x4x2_t val", - "const int lane" + "uint8_t * ptr", + "uint8x8_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.4H" + "register": "Vt.8B" } }, "Architectures": [ @@ -104640,31 +300737,29 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_s32", + "name": "vst1_u8_x2", "arguments": [ - "int32_t * ptr", - "int32x2x2_t val", - "const int lane" + "uint8_t * ptr", + "uint8x8x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.2S" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" } }, "Architectures": [ @@ -104674,63 +300769,70 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_s64", + "name": "vst1_u8_x3", "arguments": [ - "int64_t * ptr", - "int64x1x2_t val", - "const int lane" + "uint8_t * ptr", + "uint8x8x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.1D" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_s8", + "name": "vst1_u8_x4", "arguments": [ - "int8_t * ptr", - "int8x8x2_t val", - "const int lane" + "uint8_t * ptr", + "uint8x8x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { + "register": "Vt4.8B" } }, "Architectures": [ @@ -104740,31 +300842,26 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_u16", + "name": "vst1q_f16", "arguments": [ - "uint16_t * ptr", - "uint16x4x2_t val", - "const int lane" + "float16_t * ptr", + "float16x8_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.4H" + "register": "Vt.8H" } }, "Architectures": [ @@ -104774,31 +300871,29 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_u32", + "name": "vst1q_f16_x2", "arguments": [ - "uint32_t * ptr", - "uint32x2x2_t val", - "const int lane" + "float16_t * ptr", + "float16x8x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.2S" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -104808,63 +300903,70 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_u64", + "name": "vst1q_f16_x3", "arguments": [ - "uint64_t * ptr", - "uint64x1x2_t val", - "const int lane" + "float16_t * ptr", + "float16x8x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.1D" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_u8", + "name": "vst1q_f16_x4", "arguments": [ - "uint8_t * ptr", - "uint8x8x2_t val", - "const int lane" + "float16_t * ptr", + "float16x8x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.8B" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ @@ -104874,16 +300976,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_p16", + "name": "vst1q_f32", "arguments": [ - "poly16_t * ptr", - "poly16x4x2_t val" + "float32_t * ptr", + "float32x4_t val" ], "return_type": { "value": "void" @@ -104893,7 +300995,7 @@ "register": "Xn" }, "val": { - "register": "Vt2.4H" + "register": "Vt.4S" } }, "Architectures": [ @@ -104903,16 +301005,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_p64", + "name": "vst1q_f32_x2", "arguments": [ - "poly64_t * ptr", - "poly64x1x2_t val" + "float32_t * ptr", + "float32x4x2_t val" ], "return_type": { "value": "void" @@ -104921,11 +301023,15 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.1D" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -104937,10 +301043,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst2_p8", + "name": "vst1q_f32_x3", "arguments": [ - "poly8_t * ptr", - "poly8x8x2_t val" + "float32_t * ptr", + "float32x4x3_t val" ], "return_type": { "value": "void" @@ -104949,8 +301055,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.8B" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" } }, "Architectures": [ @@ -104960,16 +301072,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_s16", + "name": "vst1q_f32_x4", "arguments": [ - "int16_t * ptr", - "int16x4x2_t val" + "float32_t * ptr", + "float32x4x4_t val" ], "return_type": { "value": "void" @@ -104978,8 +301090,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.4H" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { + "register": "Vt4.4S" } }, "Architectures": [ @@ -104989,16 +301110,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_s32", + "name": "vst1q_f64", "arguments": [ - "int32_t * ptr", - "int32x2x2_t val" + "float64_t * ptr", + "float64x2_t val" ], "return_type": { "value": "void" @@ -105008,26 +301129,24 @@ "register": "Xn" }, "val": { - "register": "Vt2.2S" + "register": "Vt.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_s64", + "name": "vst1q_f64_x2", "arguments": [ - "int64_t * ptr", - "int64x1x2_t val" + "float64_t * ptr", + "float64x2x2_t val" ], "return_type": { "value": "void" @@ -105036,13 +301155,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -105053,10 +301173,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst2_s8", + "name": "vst1q_f64_x3", "arguments": [ - "int8_t * ptr", - "int8x8x2_t val" + "float64_t * ptr", + "float64x2x3_t val" ], "return_type": { "value": "void" @@ -105065,27 +301185,31 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.8B" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_u16", + "name": "vst1q_f64_x4", "arguments": [ - "uint16_t * ptr", - "uint16x4x2_t val" + "float64_t * ptr", + "float64x2x4_t val" ], "return_type": { "value": "void" @@ -105094,37 +301218,49 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.4H" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_u32", + "name": "vst1q_lane_f16", "arguments": [ - "uint32_t * ptr", - "uint32x2x2_t val" + "float16_t * ptr", + "float16x8_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.2S" + "register": "Vt.8H" } }, "Architectures": [ @@ -105134,26 +301270,31 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_u64", + "name": "vst1q_lane_f32", "arguments": [ - "uint64_t * ptr", - "uint64x1x2_t val" + "float32_t * ptr", + "float32x4_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.1D" + "register": "Vt.4S" } }, "Architectures": [ @@ -105169,49 +301310,57 @@ }, { "SIMD_ISA": "Neon", - "name": "vst2_u8", + "name": "vst1q_lane_f64", "arguments": [ - "uint8_t * ptr", - "uint8x8x2_t val" + "float64_t * ptr", + "float64x2_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.8B" + "register": "Vt.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_f16", + "name": "vst1q_lane_p16", "arguments": [ - "float16_t * ptr", - "float16x8x2_t val" + "poly16_t * ptr", + "poly16x8_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.8H" + "register": "Vt.8H" } }, "Architectures": [ @@ -105221,72 +301370,83 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_f32", + "name": "vst1q_lane_p64", "arguments": [ - "float32_t * ptr", - "float32x4x2_t val" + "poly64_t * ptr", + "poly64x2_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.4S" + "register": "Vt.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_f64", + "name": "vst1q_lane_p8", "arguments": [ - "float64_t * ptr", - "float64x2x2_t val" + "poly8_t * ptr", + "poly8x16_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 15 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.2D" + "register": "Vt.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_f16", + "name": "vst1q_lane_s16", "arguments": [ - "float16_t * ptr", - "float16x8x2_t val", + "int16_t * ptr", + "int16x8_t val", "const int lane" ], "return_type": { @@ -105301,7 +301461,7 @@ "register": "Xn" }, "val": { - "register": "Vt2.8H" + "register": "Vt.8H" } }, "Architectures": [ @@ -105311,16 +301471,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_f32", + "name": "vst1q_lane_s32", "arguments": [ - "float32_t * ptr", - "float32x4x2_t val", + "int32_t * ptr", + "int32x4_t val", "const int lane" ], "return_type": { @@ -105335,7 +301495,7 @@ "register": "Xn" }, "val": { - "register": "Vt2.4S" + "register": "Vt.4S" } }, "Architectures": [ @@ -105345,16 +301505,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_f64", + "name": "vst1q_lane_s64", "arguments": [ - "float64_t * ptr", - "float64x2x2_t val", + "int64_t * ptr", + "int64x2_t val", "const int lane" ], "return_type": { @@ -105363,30 +301523,32 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 2 + "maximum": 1 }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.2D" + "register": "Vt.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_p16", + "name": "vst1q_lane_s8", "arguments": [ - "poly16_t * ptr", - "poly16x8x2_t val", + "int8_t * ptr", + "int8x16_t val", "const int lane" ], "return_type": { @@ -105395,13 +301557,13 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 15 }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.8H" + "register": "Vt.16B" } }, "Architectures": [ @@ -105411,16 +301573,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_p64", + "name": "vst1q_lane_u16", "arguments": [ - "poly64_t * ptr", - "poly64x2x2_t val", + "uint16_t * ptr", + "uint16x8_t val", "const int lane" ], "return_type": { @@ -105429,30 +301591,32 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 7 }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.2D" + "register": "Vt.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_p8", + "name": "vst1q_lane_u32", "arguments": [ - "poly8_t * ptr", - "poly8x16x2_t val", + "uint32_t * ptr", + "uint32x4_t val", "const int lane" ], "return_type": { @@ -105461,30 +301625,32 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 15 + "maximum": 3 }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.16B" + "register": "Vt.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_s16", + "name": "vst1q_lane_u64", "arguments": [ - "int16_t * ptr", - "int16x8x2_t val", + "uint64_t * ptr", + "uint64x2_t val", "const int lane" ], "return_type": { @@ -105493,13 +301659,13 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 1 }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.8H" + "register": "Vt.2D" } }, "Architectures": [ @@ -105509,16 +301675,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_s32", + "name": "vst1q_lane_u8", "arguments": [ - "int32_t * ptr", - "int32x4x2_t val", + "uint8_t * ptr", + "uint8x16_t val", "const int lane" ], "return_type": { @@ -105527,13 +301693,13 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 15 }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.4S" + "register": "Vt.16B" } }, "Architectures": [ @@ -105543,31 +301709,35 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_s64", + "name": "vst1q_mf8_x4", "arguments": [ - "int64_t * ptr", - "int64x2x2_t val", - "const int lane" + "int8_t * ptr", + "int8x16x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.2D" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { + "register": "Vt4.16B" } }, "Architectures": [ @@ -105575,62 +301745,57 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_s8", + "name": "vst1q_p16", "arguments": [ - "int8_t * ptr", - "int8x16x2_t val", - "const int lane" + "poly16_t * ptr", + "poly16x8_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.16B" + "register": "Vt.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_u16", + "name": "vst1q_p16_x2", "arguments": [ - "uint16_t * ptr", - "uint16x8x2_t val", - "const int lane" + "poly16_t * ptr", + "poly16x8x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -105641,31 +301806,32 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_u32", + "name": "vst1q_p16_x3", "arguments": [ - "uint32_t * ptr", - "uint32x4x2_t val", - "const int lane" + "poly16_t * ptr", + "poly16x8x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.4S" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ @@ -105675,80 +301841,82 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_u64", + "name": "vst1q_p16_x4", "arguments": [ - "uint64_t * ptr", - "uint64x2x2_t val", - "const int lane" + "poly16_t * ptr", + "poly16x8x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.2D" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_u8", + "name": "vst1q_p64", "arguments": [ - "uint8_t * ptr", - "uint8x16x2_t val", - "const int lane" + "poly64_t * ptr", + "poly64x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.16B" + "register": "Vt.2D" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_p16", + "name": "vst1q_p64_x2", "arguments": [ - "poly16_t * ptr", - "poly16x8x2_t val" + "poly64_t * ptr", + "poly64x2x2_t val" ], "return_type": { "value": "void" @@ -105757,27 +301925,29 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.8H" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_p64", + "name": "vst1q_p64_x3", "arguments": [ "poly64_t * ptr", - "poly64x2x2_t val" + "poly64x2x3_t val" ], "return_type": { "value": "void" @@ -105786,25 +301956,33 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_p8", + "name": "vst1q_p64_x4", "arguments": [ - "poly8_t * ptr", - "poly8x16x2_t val" + "poly64_t * ptr", + "poly64x2x4_t val" ], "return_type": { "value": "void" @@ -105813,27 +301991,35 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.16B" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_s16", + "name": "vst1q_p8", "arguments": [ - "int16_t * ptr", - "int16x8x2_t val" + "poly8_t * ptr", + "poly8x16_t val" ], "return_type": { "value": "void" @@ -105843,7 +302029,7 @@ "register": "Xn" }, "val": { - "register": "Vt2.8H" + "register": "Vt.16B" } }, "Architectures": [ @@ -105853,16 +302039,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_s32", + "name": "vst1q_p8_x2", "arguments": [ - "int32_t * ptr", - "int32x4x2_t val" + "poly8_t * ptr", + "poly8x16x2_t val" ], "return_type": { "value": "void" @@ -105871,8 +302057,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.4S" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" } }, "Architectures": [ @@ -105882,16 +302071,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_s64", + "name": "vst1q_p8_x3", "arguments": [ - "int64_t * ptr", - "int64x2x2_t val" + "poly8_t * ptr", + "poly8x16x3_t val" ], "return_type": { "value": "void" @@ -105900,25 +302089,33 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.2D" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_s8", + "name": "vst1q_p8_x4", "arguments": [ - "int8_t * ptr", - "int8x16x2_t val" + "poly8_t * ptr", + "poly8x16x4_t val" ], "return_type": { "value": "void" @@ -105927,8 +302124,17 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { + "register": "Vt4.16B" } }, "Architectures": [ @@ -105938,16 +302144,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_u16", + "name": "vst1q_s16", "arguments": [ - "uint16_t * ptr", - "uint16x8x2_t val" + "int16_t * ptr", + "int16x8_t val" ], "return_type": { "value": "void" @@ -105957,7 +302163,7 @@ "register": "Xn" }, "val": { - "register": "Vt2.8H" + "register": "Vt.8H" } }, "Architectures": [ @@ -105967,16 +302173,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_u32", + "name": "vst1q_s16_x2", "arguments": [ - "uint32_t * ptr", - "uint32x4x2_t val" + "int16_t * ptr", + "int16x8x2_t val" ], "return_type": { "value": "void" @@ -105985,8 +302191,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.4S" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -105996,16 +302205,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_u64", + "name": "vst1q_s16_x3", "arguments": [ - "uint64_t * ptr", - "uint64x2x2_t val" + "int16_t * ptr", + "int16x8x3_t val" ], "return_type": { "value": "void" @@ -106014,25 +302223,33 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.2D" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_u8", + "name": "vst1q_s16_x4", "arguments": [ - "uint8_t * ptr", - "uint8x16x2_t val" + "int16_t * ptr", + "int16x8x4_t val" ], "return_type": { "value": "void" @@ -106041,8 +302258,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.16B" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ @@ -106052,16 +302278,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_f16", + "name": "vst1q_s32", "arguments": [ - "float16_t * ptr", - "float16x4x3_t val" + "int32_t * ptr", + "int32x4_t val" ], "return_type": { "value": "void" @@ -106071,7 +302297,7 @@ "register": "Xn" }, "val": { - "register": "Vt3.4H" + "register": "Vt.4S" } }, "Architectures": [ @@ -106081,16 +302307,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_f32", + "name": "vst1q_s32_x2", "arguments": [ - "float32_t * ptr", - "float32x2x3_t val" + "int32_t * ptr", + "int32x4x2_t val" ], "return_type": { "value": "void" @@ -106099,8 +302325,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2S" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" } }, "Architectures": [ @@ -106110,16 +302339,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_f64", + "name": "vst1q_s32_x3", "arguments": [ - "float64_t * ptr", - "float64x1x3_t val" + "int32_t * ptr", + "int32x4x3_t val" ], "return_type": { "value": "void" @@ -106128,11 +302357,19 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.1D" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -106143,25 +302380,29 @@ }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_f16", + "name": "vst1q_s32_x4", "arguments": [ - "float16_t * ptr", - "float16x4x3_t val", - "const int lane" + "int32_t * ptr", + "int32x4x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4H" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { + "register": "Vt4.4S" } }, "Architectures": [ @@ -106171,31 +302412,26 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_f32", + "name": "vst1q_s64", "arguments": [ - "float32_t * ptr", - "float32x2x3_t val", - "const int lane" + "int64_t * ptr", + "int64x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt3.2S" + "register": "Vt.2D" } }, "Architectures": [ @@ -106205,63 +302441,64 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_f64", + "name": "vst1q_s64_x2", "arguments": [ - "float64_t * ptr", - "float64x1x3_t val", - "const int lane" + "int64_t * ptr", + "int64x2x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_p16", + "name": "vst1q_s64_x3", "arguments": [ - "poly16_t * ptr", - "poly16x4x3_t val", - "const int lane" + "int64_t * ptr", + "int64x2x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4H" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ @@ -106271,63 +302508,64 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_p64", + "name": "vst1q_s64_x4", "arguments": [ - "poly64_t * ptr", - "poly64x1x3_t val", - "const int lane" + "int64_t * ptr", + "int64x2x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_p8", + "name": "vst1q_s8", "arguments": [ - "poly8_t * ptr", - "poly8x8x3_t val", - "const int lane" + "int8_t * ptr", + "int8x16_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt3.8B" + "register": "Vt.16B" } }, "Architectures": [ @@ -106337,31 +302575,29 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_s16", + "name": "vst1q_s8_x2", "arguments": [ - "int16_t * ptr", - "int16x4x3_t val", - "const int lane" + "int8_t * ptr", + "int8x16x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4H" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" } }, "Architectures": [ @@ -106371,31 +302607,32 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_s32", + "name": "vst1q_s8_x3", "arguments": [ - "int32_t * ptr", - "int32x2x3_t val", - "const int lane" + "int8_t * ptr", + "int8x16x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2S" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" } }, "Architectures": [ @@ -106405,63 +302642,64 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_s64", + "name": "vst1q_s8_x4", "arguments": [ - "int64_t * ptr", - "int64x1x3_t val", - "const int lane" + "int8_t * ptr", + "int8x16x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.1D" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { + "register": "Vt4.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_s8", + "name": "vst1q_u16", "arguments": [ - "int8_t * ptr", - "int8x8x3_t val", - "const int lane" + "uint16_t * ptr", + "uint16x8_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt3.8B" + "register": "Vt.8H" } }, "Architectures": [ @@ -106471,31 +302709,29 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_u16", + "name": "vst1q_u16_x2", "arguments": [ "uint16_t * ptr", - "uint16x4x3_t val", - "const int lane" + "uint16x8x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4H" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -106505,31 +302741,32 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_u32", + "name": "vst1q_u16_x3", "arguments": [ - "uint32_t * ptr", - "uint32x2x3_t val", - "const int lane" + "uint16_t * ptr", + "uint16x8x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2S" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ @@ -106539,63 +302776,64 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_u64", + "name": "vst1q_u16_x4", "arguments": [ - "uint64_t * ptr", - "uint64x1x3_t val", - "const int lane" + "uint16_t * ptr", + "uint16x8x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.1D" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_u8", + "name": "vst1q_u32", "arguments": [ - "uint8_t * ptr", - "uint8x8x3_t val", - "const int lane" + "uint32_t * ptr", + "uint32x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt3.8B" + "register": "Vt.4S" } }, "Architectures": [ @@ -106605,16 +302843,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_p16", + "name": "vst1q_u32_x2", "arguments": [ - "poly16_t * ptr", - "poly16x4x3_t val" + "uint32_t * ptr", + "uint32x4x2_t val" ], "return_type": { "value": "void" @@ -106623,8 +302861,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4H" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" } }, "Architectures": [ @@ -106634,16 +302875,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_p64", + "name": "vst1q_u32_x3", "arguments": [ - "poly64_t * ptr", - "poly64x1x3_t val" + "uint32_t * ptr", + "uint32x4x3_t val" ], "return_type": { "value": "void" @@ -106652,11 +302893,18 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.1D" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -106668,10 +302916,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst3_p8", + "name": "vst1q_u32_x4", "arguments": [ - "poly8_t * ptr", - "poly8x8x3_t val" + "uint32_t * ptr", + "uint32x4x4_t val" ], "return_type": { "value": "void" @@ -106680,8 +302928,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8B" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { + "register": "Vt4.4S" } }, "Architectures": [ @@ -106691,16 +302948,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_s16", + "name": "vst1q_u64", "arguments": [ - "int16_t * ptr", - "int16x4x3_t val" + "uint64_t * ptr", + "uint64x2_t val" ], "return_type": { "value": "void" @@ -106710,7 +302967,7 @@ "register": "Xn" }, "val": { - "register": "Vt3.4H" + "register": "Vt.2D" } }, "Architectures": [ @@ -106720,16 +302977,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_s32", + "name": "vst1q_u64_x2", "arguments": [ - "int32_t * ptr", - "int32x2x3_t val" + "uint64_t * ptr", + "uint64x2x2_t val" ], "return_type": { "value": "void" @@ -106738,8 +302995,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2S" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ @@ -106749,16 +303009,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_s64", + "name": "vst1q_u64_x3", "arguments": [ - "int64_t * ptr", - "int64x1x3_t val" + "uint64_t * ptr", + "uint64x2x3_t val" ], "return_type": { "value": "void" @@ -106767,8 +303027,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ @@ -106784,10 +303050,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst3_s8", + "name": "vst1q_u64_x4", "arguments": [ - "int8_t * ptr", - "int8x8x3_t val" + "uint64_t * ptr", + "uint64x2x4_t val" ], "return_type": { "value": "void" @@ -106796,8 +303062,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8B" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ @@ -106807,16 +303082,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_u16", + "name": "vst1q_u8", "arguments": [ - "uint16_t * ptr", - "uint16x4x3_t val" + "uint8_t * ptr", + "uint8x16_t val" ], "return_type": { "value": "void" @@ -106826,7 +303101,7 @@ "register": "Xn" }, "val": { - "register": "Vt3.4H" + "register": "Vt.16B" } }, "Architectures": [ @@ -106836,16 +303111,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_u32", + "name": "vst1q_u8_x2", "arguments": [ - "uint32_t * ptr", - "uint32x2x3_t val" + "uint8_t * ptr", + "uint8x16x2_t val" ], "return_type": { "value": "void" @@ -106854,8 +303129,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2S" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" } }, "Architectures": [ @@ -106865,16 +303143,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_u64", + "name": "vst1q_u8_x3", "arguments": [ - "uint64_t * ptr", - "uint64x1x3_t val" + "uint8_t * ptr", + "uint8x16x3_t val" ], "return_type": { "value": "void" @@ -106883,8 +303161,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.1D" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" } }, "Architectures": [ @@ -106900,10 +303184,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst3_u8", + "name": "vst1q_u8_x4", "arguments": [ "uint8_t * ptr", - "uint8x8x3_t val" + "uint8x16x4_t val" ], "return_type": { "value": "void" @@ -106912,8 +303196,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8B" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { + "register": "Vt4.16B" } }, "Architectures": [ @@ -106923,16 +303216,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_f16", + "name": "vst2_f16", "arguments": [ "float16_t * ptr", - "float16x8x3_t val" + "float16x4x2_t val" ], "return_type": { "value": "void" @@ -106941,8 +303234,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -106952,16 +303248,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_f32", + "name": "vst2_f32", "arguments": [ "float32_t * ptr", - "float32x4x3_t val" + "float32x2x2_t val" ], "return_type": { "value": "void" @@ -106970,8 +303266,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" } }, "Architectures": [ @@ -106981,16 +303280,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_f64", + "name": "vst2_f64", "arguments": [ "float64_t * ptr", - "float64x2x3_t val" + "float64x1x2_t val" ], "return_type": { "value": "void" @@ -106999,8 +303298,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ @@ -107008,16 +303310,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_f16", + "name": "vst2_lane_f16", "arguments": [ "float16_t * ptr", - "float16x8x3_t val", + "float16x4x2_t val", "const int lane" ], "return_type": { @@ -107026,13 +303328,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -107042,16 +303347,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_f32", + "name": "vst2_lane_f32", "arguments": [ "float32_t * ptr", - "float32x4x3_t val", + "float32x2x2_t val", "const int lane" ], "return_type": { @@ -107060,13 +303365,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" } }, "Architectures": [ @@ -107076,16 +303384,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_f64", + "name": "vst2_lane_f64", "arguments": [ "float64_t * ptr", - "float64x2x3_t val", + "float64x1x2_t val", "const int lane" ], "return_type": { @@ -107094,13 +303402,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ @@ -107108,16 +303419,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_p16", + "name": "vst2_lane_p16", "arguments": [ "poly16_t * ptr", - "poly16x8x3_t val", + "poly16x4x2_t val", "const int lane" ], "return_type": { @@ -107126,13 +303437,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -107142,16 +303456,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_p64", + "name": "vst2_lane_p64", "arguments": [ "poly64_t * ptr", - "poly64x2x3_t val", + "poly64x1x2_t val", "const int lane" ], "return_type": { @@ -107160,13 +303474,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ @@ -107174,16 +303491,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_p8", + "name": "vst2_lane_p8", "arguments": [ "poly8_t * ptr", - "poly8x16x3_t val", + "poly8x8x2_t val", "const int lane" ], "return_type": { @@ -107192,13 +303509,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 15 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" } }, "Architectures": [ @@ -107208,16 +303528,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_s16", + "name": "vst2_lane_s16", "arguments": [ "int16_t * ptr", - "int16x8x3_t val", + "int16x4x2_t val", "const int lane" ], "return_type": { @@ -107226,13 +303546,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -107242,16 +303565,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_s32", + "name": "vst2_lane_s32", "arguments": [ "int32_t * ptr", - "int32x4x3_t val", + "int32x2x2_t val", "const int lane" ], "return_type": { @@ -107260,13 +303583,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" } }, "Architectures": [ @@ -107276,16 +303602,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_s64", + "name": "vst2_lane_s64", "arguments": [ "int64_t * ptr", - "int64x2x3_t val", + "int64x1x2_t val", "const int lane" ], "return_type": { @@ -107294,13 +303620,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ @@ -107308,16 +303637,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_s8", + "name": "vst2_lane_s8", "arguments": [ "int8_t * ptr", - "int8x16x3_t val", + "int8x8x2_t val", "const int lane" ], "return_type": { @@ -107326,13 +303655,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 15 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" } }, "Architectures": [ @@ -107342,16 +303674,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_u16", + "name": "vst2_lane_u16", "arguments": [ "uint16_t * ptr", - "uint16x8x3_t val", + "uint16x4x2_t val", "const int lane" ], "return_type": { @@ -107360,13 +303692,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -107376,16 +303711,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_u32", + "name": "vst2_lane_u32", "arguments": [ "uint32_t * ptr", - "uint32x4x3_t val", + "uint32x2x2_t val", "const int lane" ], "return_type": { @@ -107394,13 +303729,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" } }, "Architectures": [ @@ -107410,16 +303748,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_u64", + "name": "vst2_lane_u64", "arguments": [ "uint64_t * ptr", - "uint64x2x3_t val", + "uint64x1x2_t val", "const int lane" ], "return_type": { @@ -107428,13 +303766,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ @@ -107442,16 +303783,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_u8", + "name": "vst2_lane_u8", "arguments": [ "uint8_t * ptr", - "uint8x16x3_t val", + "uint8x8x2_t val", "const int lane" ], "return_type": { @@ -107460,13 +303801,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 15 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" } }, "Architectures": [ @@ -107476,16 +303820,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_p16", + "name": "vst2_p16", "arguments": [ "poly16_t * ptr", - "poly16x8x3_t val" + "poly16x4x2_t val" ], "return_type": { "value": "void" @@ -107494,8 +303838,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -107505,16 +303852,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_p64", + "name": "vst2_p64", "arguments": [ "poly64_t * ptr", - "poly64x2x3_t val" + "poly64x1x2_t val" ], "return_type": { "value": "void" @@ -107523,25 +303870,29 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_p8", + "name": "vst2_p8", "arguments": [ "poly8_t * ptr", - "poly8x16x3_t val" + "poly8x8x2_t val" ], "return_type": { "value": "void" @@ -107550,8 +303901,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" } }, "Architectures": [ @@ -107561,16 +303915,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_s16", + "name": "vst2_s16", "arguments": [ "int16_t * ptr", - "int16x8x3_t val" + "int16x4x2_t val" ], "return_type": { "value": "void" @@ -107579,8 +303933,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -107590,16 +303947,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_s32", + "name": "vst2_s32", "arguments": [ "int32_t * ptr", - "int32x4x3_t val" + "int32x2x2_t val" ], "return_type": { "value": "void" @@ -107608,8 +303965,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" } }, "Architectures": [ @@ -107619,16 +303979,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_s64", + "name": "vst2_s64", "arguments": [ "int64_t * ptr", - "int64x2x3_t val" + "int64x1x2_t val" ], "return_type": { "value": "void" @@ -107637,25 +303997,30 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_s8", + "name": "vst2_s8", "arguments": [ "int8_t * ptr", - "int8x16x3_t val" + "int8x8x2_t val" ], "return_type": { "value": "void" @@ -107664,8 +304029,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" } }, "Architectures": [ @@ -107675,16 +304043,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_u16", + "name": "vst2_u16", "arguments": [ "uint16_t * ptr", - "uint16x8x3_t val" + "uint16x4x2_t val" ], "return_type": { "value": "void" @@ -107693,8 +304061,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -107704,16 +304075,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_u32", + "name": "vst2_u32", "arguments": [ "uint32_t * ptr", - "uint32x4x3_t val" + "uint32x2x2_t val" ], "return_type": { "value": "void" @@ -107722,8 +304093,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" } }, "Architectures": [ @@ -107733,16 +304107,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_u64", + "name": "vst2_u64", "arguments": [ "uint64_t * ptr", - "uint64x2x3_t val" + "uint64x1x2_t val" ], "return_type": { "value": "void" @@ -107751,25 +304125,30 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_u8", + "name": "vst2_u8", "arguments": [ "uint8_t * ptr", - "uint8x16x3_t val" + "uint8x8x2_t val" ], "return_type": { "value": "void" @@ -107778,8 +304157,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" } }, "Architectures": [ @@ -107789,16 +304171,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_f16", + "name": "vst2q_f16", "arguments": [ "float16_t * ptr", - "float16x4x4_t val" + "float16x8x2_t val" ], "return_type": { "value": "void" @@ -107807,8 +304189,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4H" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -107818,16 +304203,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_f32", + "name": "vst2q_f32", "arguments": [ "float32_t * ptr", - "float32x2x4_t val" + "float32x4x2_t val" ], "return_type": { "value": "void" @@ -107836,8 +304221,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2S" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" } }, "Architectures": [ @@ -107847,16 +304235,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_f64", + "name": "vst2q_f64", "arguments": [ "float64_t * ptr", - "float64x1x4_t val" + "float64x2x2_t val" ], "return_type": { "value": "void" @@ -107865,8 +304253,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ @@ -107874,16 +304265,16 @@ ], "instructions": [ [ - "ST1" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_f16", + "name": "vst2q_lane_f16", "arguments": [ "float16_t * ptr", - "float16x4x4_t val", + "float16x8x2_t val", "const int lane" ], "return_type": { @@ -107892,13 +304283,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4H" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -107908,16 +304302,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_f32", + "name": "vst2q_lane_f32", "arguments": [ "float32_t * ptr", - "float32x2x4_t val", + "float32x4x2_t val", "const int lane" ], "return_type": { @@ -107926,13 +304320,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2S" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" } }, "Architectures": [ @@ -107942,16 +304339,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_f64", + "name": "vst2q_lane_f64", "arguments": [ "float64_t * ptr", - "float64x1x4_t val", + "float64x2x2_t val", "const int lane" ], "return_type": { @@ -107960,13 +304357,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 0 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ @@ -107974,16 +304374,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_p16", + "name": "vst2q_lane_p16", "arguments": [ "poly16_t * ptr", - "poly16x4x4_t val", + "poly16x8x2_t val", "const int lane" ], "return_type": { @@ -107992,13 +304392,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4H" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -108008,16 +304411,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_p64", + "name": "vst2q_lane_p64", "arguments": [ "poly64_t * ptr", - "poly64x1x4_t val", + "poly64x2x2_t val", "const int lane" ], "return_type": { @@ -108026,13 +304429,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 0 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ @@ -108040,16 +304446,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_p8", + "name": "vst2q_lane_p8", "arguments": [ "poly8_t * ptr", - "poly8x8x4_t val", + "poly8x16x2_t val", "const int lane" ], "return_type": { @@ -108058,32 +304464,33 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 15 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8B" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_s16", + "name": "vst2q_lane_s16", "arguments": [ "int16_t * ptr", - "int16x4x4_t val", + "int16x8x2_t val", "const int lane" ], "return_type": { @@ -108092,13 +304499,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4H" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -108108,16 +304518,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_s32", + "name": "vst2q_lane_s32", "arguments": [ "int32_t * ptr", - "int32x2x4_t val", + "int32x4x2_t val", "const int lane" ], "return_type": { @@ -108126,13 +304536,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2S" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" } }, "Architectures": [ @@ -108142,16 +304555,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_s64", + "name": "vst2q_lane_s64", "arguments": [ "int64_t * ptr", - "int64x1x4_t val", + "int64x2x2_t val", "const int lane" ], "return_type": { @@ -108160,13 +304573,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 0 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ @@ -108174,16 +304590,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_s8", + "name": "vst2q_lane_s8", "arguments": [ "int8_t * ptr", - "int8x8x4_t val", + "int8x16x2_t val", "const int lane" ], "return_type": { @@ -108192,32 +304608,33 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 15 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8B" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_u16", + "name": "vst2q_lane_u16", "arguments": [ "uint16_t * ptr", - "uint16x4x4_t val", + "uint16x8x2_t val", "const int lane" ], "return_type": { @@ -108226,13 +304643,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4H" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -108242,16 +304662,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_u32", + "name": "vst2q_lane_u32", "arguments": [ "uint32_t * ptr", - "uint32x2x4_t val", + "uint32x4x2_t val", "const int lane" ], "return_type": { @@ -108260,13 +304680,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2S" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" } }, "Architectures": [ @@ -108276,16 +304699,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_u64", + "name": "vst2q_lane_u64", "arguments": [ "uint64_t * ptr", - "uint64x1x4_t val", + "uint64x2x2_t val", "const int lane" ], "return_type": { @@ -108294,13 +304717,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 0 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ @@ -108308,16 +304734,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_u8", + "name": "vst2q_lane_u8", "arguments": [ "uint8_t * ptr", - "uint8x8x4_t val", + "uint8x16x2_t val", "const int lane" ], "return_type": { @@ -108326,32 +304752,33 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 15 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8B" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_p16", + "name": "vst2q_p16", "arguments": [ "poly16_t * ptr", - "poly16x4x4_t val" + "poly16x8x2_t val" ], "return_type": { "value": "void" @@ -108360,8 +304787,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4H" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -108371,16 +304801,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_p64", + "name": "vst2q_p64", "arguments": [ "poly64_t * ptr", - "poly64x1x4_t val" + "poly64x2x2_t val" ], "return_type": { "value": "void" @@ -108389,26 +304819,28 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "ST1" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_p8", + "name": "vst2q_p8", "arguments": [ "poly8_t * ptr", - "poly8x8x4_t val" + "poly8x16x2_t val" ], "return_type": { "value": "void" @@ -108417,8 +304849,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8B" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" } }, "Architectures": [ @@ -108428,16 +304863,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_s16", + "name": "vst2q_s16", "arguments": [ "int16_t * ptr", - "int16x4x4_t val" + "int16x8x2_t val" ], "return_type": { "value": "void" @@ -108446,8 +304881,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4H" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -108457,16 +304895,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_s32", + "name": "vst2q_s32", "arguments": [ "int32_t * ptr", - "int32x2x4_t val" + "int32x4x2_t val" ], "return_type": { "value": "void" @@ -108475,8 +304913,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2S" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" } }, "Architectures": [ @@ -108486,16 +304927,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_s64", + "name": "vst2q_s64", "arguments": [ "int64_t * ptr", - "int64x1x4_t val" + "int64x2x2_t val" ], "return_type": { "value": "void" @@ -108504,27 +304945,28 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_s8", + "name": "vst2q_s8", "arguments": [ "int8_t * ptr", - "int8x8x4_t val" + "int8x16x2_t val" ], "return_type": { "value": "void" @@ -108533,8 +304975,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8B" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" } }, "Architectures": [ @@ -108544,16 +304989,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_u16", + "name": "vst2q_u16", "arguments": [ "uint16_t * ptr", - "uint16x4x4_t val" + "uint16x8x2_t val" ], "return_type": { "value": "void" @@ -108562,8 +305007,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4H" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -108573,16 +305021,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_u32", + "name": "vst2q_u32", "arguments": [ "uint32_t * ptr", - "uint32x2x4_t val" + "uint32x4x2_t val" ], "return_type": { "value": "void" @@ -108591,8 +305039,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2S" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" } }, "Architectures": [ @@ -108602,16 +305053,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_u64", + "name": "vst2q_u64", "arguments": [ "uint64_t * ptr", - "uint64x1x4_t val" + "uint64x2x2_t val" ], "return_type": { "value": "void" @@ -108620,27 +305071,28 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_u8", + "name": "vst2q_u8", "arguments": [ "uint8_t * ptr", - "uint8x8x4_t val" + "uint8x16x2_t val" ], "return_type": { "value": "void" @@ -108649,8 +305101,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8B" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" } }, "Architectures": [ @@ -108660,16 +305115,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_f16", + "name": "vst3_f16", "arguments": [ "float16_t * ptr", - "float16x8x4_t val" + "float16x4x3_t val" ], "return_type": { "value": "void" @@ -108678,8 +305133,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -108689,16 +305150,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_f32", + "name": "vst3_f32", "arguments": [ "float32_t * ptr", - "float32x4x4_t val" + "float32x2x3_t val" ], "return_type": { "value": "void" @@ -108707,8 +305168,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" } }, "Architectures": [ @@ -108718,16 +305185,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_f64", + "name": "vst3_f64", "arguments": [ "float64_t * ptr", - "float64x2x4_t val" + "float64x1x3_t val" ], "return_type": { "value": "void" @@ -108736,8 +305203,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ @@ -108745,16 +305218,16 @@ ], "instructions": [ [ - "ST4" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_f16", + "name": "vst3_lane_f16", "arguments": [ "float16_t * ptr", - "float16x8x4_t val", + "float16x4x3_t val", "const int lane" ], "return_type": { @@ -108763,13 +305236,19 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -108779,16 +305258,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_f32", + "name": "vst3_lane_f32", "arguments": [ "float32_t * ptr", - "float32x4x4_t val", + "float32x2x3_t val", "const int lane" ], "return_type": { @@ -108797,13 +305276,19 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" } }, "Architectures": [ @@ -108813,16 +305298,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_f64", + "name": "vst3_lane_f64", "arguments": [ "float64_t * ptr", - "float64x2x4_t val", + "float64x1x3_t val", "const int lane" ], "return_type": { @@ -108831,13 +305316,19 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ @@ -108845,16 +305336,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_p16", + "name": "vst3_lane_p16", "arguments": [ "poly16_t * ptr", - "poly16x8x4_t val", + "poly16x4x3_t val", "const int lane" ], "return_type": { @@ -108863,13 +305354,19 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -108879,16 +305376,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_p64", + "name": "vst3_lane_p64", "arguments": [ "poly64_t * ptr", - "poly64x2x4_t val", + "poly64x1x3_t val", "const int lane" ], "return_type": { @@ -108897,13 +305394,19 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ @@ -108911,16 +305414,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_p8", + "name": "vst3_lane_p8", "arguments": [ "poly8_t * ptr", - "poly8x16x4_t val", + "poly8x8x3_t val", "const int lane" ], "return_type": { @@ -108929,30 +305432,38 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 15 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_s16", + "name": "vst3_lane_s16", "arguments": [ "int16_t * ptr", - "int16x8x4_t val", + "int16x4x3_t val", "const int lane" ], "return_type": { @@ -108961,13 +305472,19 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -108977,16 +305494,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_s32", + "name": "vst3_lane_s32", "arguments": [ "int32_t * ptr", - "int32x4x4_t val", + "int32x2x3_t val", "const int lane" ], "return_type": { @@ -108995,13 +305512,19 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" } }, "Architectures": [ @@ -109011,16 +305534,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_s64", + "name": "vst3_lane_s64", "arguments": [ "int64_t * ptr", - "int64x2x4_t val", + "int64x1x3_t val", "const int lane" ], "return_type": { @@ -109029,13 +305552,19 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ @@ -109043,16 +305572,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_s8", + "name": "vst3_lane_s8", "arguments": [ "int8_t * ptr", - "int8x16x4_t val", + "int8x8x3_t val", "const int lane" ], "return_type": { @@ -109061,30 +305590,38 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 15 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_u16", + "name": "vst3_lane_u16", "arguments": [ "uint16_t * ptr", - "uint16x8x4_t val", + "uint16x4x3_t val", "const int lane" ], "return_type": { @@ -109093,13 +305630,19 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -109109,16 +305652,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_u32", + "name": "vst3_lane_u32", "arguments": [ "uint32_t * ptr", - "uint32x4x4_t val", + "uint32x2x3_t val", "const int lane" ], "return_type": { @@ -109127,13 +305670,19 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" } }, "Architectures": [ @@ -109143,16 +305692,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_u64", + "name": "vst3_lane_u64", "arguments": [ "uint64_t * ptr", - "uint64x2x4_t val", + "uint64x1x3_t val", "const int lane" ], "return_type": { @@ -109161,13 +305710,19 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ @@ -109175,16 +305730,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_u8", + "name": "vst3_lane_u8", "arguments": [ "uint8_t * ptr", - "uint8x16x4_t val", + "uint8x8x3_t val", "const int lane" ], "return_type": { @@ -109193,30 +305748,38 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 15 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_p16", + "name": "vst3_p16", "arguments": [ "poly16_t * ptr", - "poly16x8x4_t val" + "poly16x4x3_t val" ], "return_type": { "value": "void" @@ -109225,8 +305788,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -109236,16 +305805,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_p64", + "name": "vst3_p64", "arguments": [ "poly64_t * ptr", - "poly64x2x4_t val" + "poly64x1x3_t val" ], "return_type": { "value": "void" @@ -109254,25 +305823,32 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "ST4" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_p8", + "name": "vst3_p8", "arguments": [ "poly8_t * ptr", - "poly8x16x4_t val" + "poly8x8x3_t val" ], "return_type": { "value": "void" @@ -109281,8 +305857,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" } }, "Architectures": [ @@ -109292,16 +305874,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_s16", + "name": "vst3_s16", "arguments": [ "int16_t * ptr", - "int16x8x4_t val" + "int16x4x3_t val" ], "return_type": { "value": "void" @@ -109310,8 +305892,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -109321,16 +305909,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_s32", + "name": "vst3_s32", "arguments": [ "int32_t * ptr", - "int32x4x4_t val" + "int32x2x3_t val" ], "return_type": { "value": "void" @@ -109339,8 +305927,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" } }, "Architectures": [ @@ -109350,16 +305944,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_s64", + "name": "vst3_s64", "arguments": [ "int64_t * ptr", - "int64x2x4_t val" + "int64x1x3_t val" ], "return_type": { "value": "void" @@ -109368,25 +305962,33 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST4" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_s8", + "name": "vst3_s8", "arguments": [ "int8_t * ptr", - "int8x16x4_t val" + "int8x8x3_t val" ], "return_type": { "value": "void" @@ -109395,8 +305997,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" } }, "Architectures": [ @@ -109406,16 +306014,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_u16", + "name": "vst3_u16", "arguments": [ "uint16_t * ptr", - "uint16x8x4_t val" + "uint16x4x3_t val" ], "return_type": { "value": "void" @@ -109424,8 +306032,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -109435,16 +306049,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_u32", + "name": "vst3_u32", "arguments": [ "uint32_t * ptr", - "uint32x4x4_t val" + "uint32x2x3_t val" ], "return_type": { "value": "void" @@ -109453,8 +306067,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" } }, "Architectures": [ @@ -109464,16 +306084,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_u64", + "name": "vst3_u64", "arguments": [ "uint64_t * ptr", - "uint64x2x4_t val" + "uint64x1x3_t val" ], "return_type": { "value": "void" @@ -109482,25 +306102,33 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST4" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_u8", + "name": "vst3_u8", "arguments": [ "uint8_t * ptr", - "uint8x16x4_t val" + "uint8x8x3_t val" ], "return_type": { "value": "void" @@ -109509,8 +306137,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" } }, "Architectures": [ @@ -109520,16 +306154,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vstrq_p128", + "name": "vst3q_f16", "arguments": [ - "poly128_t * ptr", - "poly128_t val" + "float16_t * ptr", + "float16x8x3_t val" ], "return_type": { "value": "void" @@ -109538,105 +306172,84 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Qt" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "STR" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vstl1_lane_f64", + "name": "vst3q_f32", "arguments": [ - "float64_t * ptr", - "float64x1_t val", - "const int lane" + "float32_t * ptr", + "float32x4x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.1D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "STL1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vstl1q_lane_f64", - "arguments": [ - "float64_t * ptr", - "float64x2_t val", - "const int lane" - ], - "return_type": { - "value": "void" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "val.val[0]": { + "register": "Vt.4S" }, - "ptr": { - "register": "Xn" + "val.val[1]": { + "register": "Vt2.4S" }, - "val": { - "register": "Vt.2D" + "val.val[2]": { + "register": "Vt3.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "STL1" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vstl1_lane_p64", + "name": "vst3q_f64", "arguments": [ - "poly64_t * ptr", - "poly64x1_t val", - "const int lane" + "float64_t * ptr", + "float64x2x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ @@ -109644,16 +306257,16 @@ ], "instructions": [ [ - "STL1" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vstl1q_lane_p64", + "name": "vst3q_lane_f16", "arguments": [ - "poly64_t * ptr", - "poly64x2_t val", + "float16_t * ptr", + "float16x8x3_t val", "const int lane" ], "return_type": { @@ -109662,30 +306275,38 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.2D" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "STL1" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vstl1_lane_u64", + "name": "vst3q_lane_f32", "arguments": [ - "uint64_t * ptr", - "uint64x1_t val", + "float32_t * ptr", + "float32x4x3_t val", "const int lane" ], "return_type": { @@ -109694,30 +306315,38 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 0 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.1D" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "STL1" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vstl1q_lane_u64", + "name": "vst3q_lane_f64", "arguments": [ - "uint64_t * ptr", - "uint64x2_t val", + "float64_t * ptr", + "float64x2x3_t val", "const int lane" ], "return_type": { @@ -109731,8 +306360,14 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ @@ -109740,16 +306375,16 @@ ], "instructions": [ [ - "STL1" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vstl1_lane_s64", + "name": "vst3q_lane_p16", "arguments": [ - "int64_t * ptr", - "int64x1_t val", + "poly16_t * ptr", + "poly16x8x3_t val", "const int lane" ], "return_type": { @@ -109758,30 +306393,38 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 0 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.1D" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "STL1" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vstl1q_lane_s64", + "name": "vst3q_lane_p64", "arguments": [ - "int64_t * ptr", - "int64x2_t val", + "poly64_t * ptr", + "poly64x2x3_t val", "const int lane" ], "return_type": { @@ -109795,8 +306438,14 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ @@ -109804,54 +306453,77 @@ ], "instructions": [ [ - "STL1" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsub_f16", + "name": "vst3q_lane_p8", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "poly8_t * ptr", + "poly8x16x3_t val", + "const int lane" ], "return_type": { - "value": "float16x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 15 }, - "b": { - "register": "Vm.4H" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FSUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsub_f32", + "name": "vst3q_lane_s16", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "int16_t * ptr", + "int16x8x3_t val", + "const int lane" ], "return_type": { - "value": "float32x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.2S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ @@ -109861,82 +306533,115 @@ ], "instructions": [ [ - "FSUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsub_f64", + "name": "vst3q_lane_s32", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "int32_t * ptr", + "int32x4x3_t val", + "const int lane" ], "return_type": { - "value": "float64x1_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Dm" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FSUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsub_s16", + "name": "vst3q_lane_s64", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "int64_t * ptr", + "int64x2x3_t val", + "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.4H" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsub_s32", + "name": "vst3q_lane_s8", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "int8_t * ptr", + "int8x16x3_t val", + "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 15 }, - "b": { - "register": "Vm.2S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" } }, "Architectures": [ @@ -109946,26 +306651,37 @@ ], "instructions": [ [ - "SUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsub_s64", + "name": "vst3q_lane_u16", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "uint16_t * ptr", + "uint16x8x3_t val", + "const int lane" ], "return_type": { - "value": "int64x1_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Dm" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ @@ -109975,26 +306691,37 @@ ], "instructions": [ [ - "SUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsub_s8", + "name": "vst3q_lane_u32", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "uint32_t * ptr", + "uint32x4x3_t val", + "const int lane" ], "return_type": { - "value": "int8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.8B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" } }, "Architectures": [ @@ -110004,55 +306731,75 @@ ], "instructions": [ [ - "SUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsub_u16", + "name": "vst3q_lane_u64", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "uint64_t * ptr", + "uint64x2x3_t val", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.4H" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsub_u32", + "name": "vst3q_lane_u8", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "uint8_t * ptr", + "uint8x16x3_t val", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 15 }, - "b": { - "register": "Vm.2S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" } }, "Architectures": [ @@ -110062,26 +306809,32 @@ ], "instructions": [ [ - "SUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsub_u64", + "name": "vst3q_p16", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "poly16_t * ptr", + "poly16x8x3_t val" ], "return_type": { - "value": "uint64x1_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Dm" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ @@ -110091,141 +306844,170 @@ ], "instructions": [ [ - "SUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsub_u8", + "name": "vst3q_p64", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "poly64_t * ptr", + "poly64x2x3_t val" ], "return_type": { - "value": "uint8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.8B" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubd_s64", + "name": "vst3q_p8", "arguments": [ - "int64_t a", - "int64_t b" + "poly8_t * ptr", + "poly8x16x3_t val" ], "return_type": { - "value": "int64_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Dm" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubd_u64", + "name": "vst3q_s16", "arguments": [ - "uint64_t a", - "uint64_t b" + "int16_t * ptr", + "int16x8x3_t val" ], "return_type": { - "value": "uint64_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Dm" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubh_f16", + "name": "vst3q_s32", "arguments": [ - "float16_t a", - "float16_t b" + "int32_t * ptr", + "int32x4x3_t val" ], "return_type": { - "value": "float16_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Hm" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FSUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_high_s16", + "name": "vst3q_s64", "arguments": [ - "int8x8_t r", - "int16x8_t a", - "int16x8_t b" + "int64_t * ptr", + "int64x2x3_t val" ], "return_type": { - "value": "int8x16_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.8H" + "val.val[0]": { + "register": "Vt.2D" }, - "r": { - "register": "Vd.8B" + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ @@ -110233,123 +307015,137 @@ ], "instructions": [ [ - "SUBHN2" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_high_s32", + "name": "vst3q_s8", "arguments": [ - "int16x4_t r", - "int32x4_t a", - "int32x4_t b" + "int8_t * ptr", + "int8x16x3_t val" ], "return_type": { - "value": "int16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.4S" + "val.val[0]": { + "register": "Vt.16B" }, - "r": { - "register": "Vd.4H" + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SUBHN2" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_high_s64", + "name": "vst3q_u16", "arguments": [ - "int32x2_t r", - "int64x2_t a", - "int64x2_t b" + "uint16_t * ptr", + "uint16x8x3_t val" ], "return_type": { - "value": "int32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.2D" + "val.val[0]": { + "register": "Vt.8H" }, - "r": { - "register": "Vd.2S" + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SUBHN2" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_high_u16", + "name": "vst3q_u32", "arguments": [ - "uint8x8_t r", - "uint16x8_t a", - "uint16x8_t b" + "uint32_t * ptr", + "uint32x4x3_t val" ], "return_type": { - "value": "uint8x16_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.8H" + "val.val[0]": { + "register": "Vt.4S" }, - "r": { - "register": "Vd.8B" + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SUBHN2" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_high_u32", + "name": "vst3q_u64", "arguments": [ - "uint16x4_t r", - "uint32x4_t a", - "uint32x4_t b" + "uint64_t * ptr", + "uint64x2x3_t val" ], "return_type": { - "value": "uint16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.4S" + "val.val[0]": { + "register": "Vt.2D" }, - "r": { - "register": "Vd.4H" + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ @@ -110357,57 +307153,70 @@ ], "instructions": [ [ - "SUBHN2" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_high_u64", + "name": "vst3q_u8", "arguments": [ - "uint32x2_t r", - "uint64x2_t a", - "uint64x2_t b" + "uint8_t * ptr", + "uint8x16x3_t val" ], "return_type": { - "value": "uint32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.2D" + "val.val[0]": { + "register": "Vt.16B" }, - "r": { - "register": "Vd.2S" + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SUBHN2" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_s16", + "name": "vst4_f16", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "float16_t * ptr", + "float16x4x4_t val" ], "return_type": { - "value": "int8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ @@ -110417,26 +307226,35 @@ ], "instructions": [ [ - "SUBHN" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_s32", + "name": "vst4_f32", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "float32_t * ptr", + "float32x2x4_t val" ], "return_type": { - "value": "int16x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { + "register": "Vt4.2S" } }, "Architectures": [ @@ -110446,55 +307264,76 @@ ], "instructions": [ [ - "SUBHN" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_s64", + "name": "vst4_f64", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "float64_t * ptr", + "float64x1x4_t val" ], "return_type": { - "value": "int32x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SUBHN" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_u16", + "name": "vst4_lane_f16", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "float16_t * ptr", + "float16x4x4_t val", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.8H" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ @@ -110504,26 +307343,40 @@ ], "instructions": [ [ - "SUBHN" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_u32", + "name": "vst4_lane_f32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "float32_t * ptr", + "float32x2x4_t val", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.4S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { + "register": "Vt4.2S" } }, "Architectures": [ @@ -110533,82 +307386,124 @@ ], "instructions": [ [ - "SUBHN" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_u64", + "name": "vst4_lane_f64", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "float64_t * ptr", + "float64x1x4_t val", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "lane": { + "minimum": 0, + "maximum": 0 }, - "b": { - "register": "Vm.2D" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SUBHN" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_high_s16", + "name": "vst4_lane_p16", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "poly16_t * ptr", + "poly16x4x4_t val", + "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.8H" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SSUBL2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_high_s32", + "name": "vst4_lane_p64", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "poly64_t * ptr", + "poly64x1x4_t val", + "const int lane" ], "return_type": { - "value": "int64x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "lane": { + "minimum": 0, + "maximum": 0 }, - "b": { - "register": "Vm.4S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ @@ -110616,107 +307511,169 @@ ], "instructions": [ [ - "SSUBL2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_high_s8", + "name": "vst4_lane_p8", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "poly8_t * ptr", + "poly8x8x4_t val", + "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { + "register": "Vt4.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SSUBL2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_high_u16", + "name": "vst4_lane_s16", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "int16_t * ptr", + "int16x4x4_t val", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.8H" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USUBL2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_high_u32", + "name": "vst4_lane_s32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "int32_t * ptr", + "int32x2x4_t val", + "const int lane" ], "return_type": { - "value": "uint64x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.4S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { + "register": "Vt4.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USUBL2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_high_u8", + "name": "vst4_lane_s64", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "int64_t * ptr", + "int64x1x4_t val", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 0 }, - "b": { - "register": "Vm.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ @@ -110724,26 +307681,40 @@ ], "instructions": [ [ - "USUBL2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_s16", + "name": "vst4_lane_s8", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "int8_t * ptr", + "int8x8x4_t val", + "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.4H" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { + "register": "Vt4.8B" } }, "Architectures": [ @@ -110753,26 +307724,40 @@ ], "instructions": [ [ - "SSUBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_s32", + "name": "vst4_lane_u16", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "uint16_t * ptr", + "uint16x4x4_t val", + "const int lane" ], "return_type": { - "value": "int64x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.2S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ @@ -110782,26 +307767,40 @@ ], "instructions": [ [ - "SSUBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_s8", + "name": "vst4_lane_u32", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "uint32_t * ptr", + "uint32x2x4_t val", + "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.8B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { + "register": "Vt4.2S" } }, "Architectures": [ @@ -110811,55 +307810,81 @@ ], "instructions": [ [ - "SSUBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_u16", + "name": "vst4_lane_u64", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "uint64_t * ptr", + "uint64x1x4_t val", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 0 }, - "b": { - "register": "Vm.4H" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USUBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_u32", + "name": "vst4_lane_u8", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "uint8_t * ptr", + "uint8x8x4_t val", + "const int lane" ], "return_type": { - "value": "uint64x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.2S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { + "register": "Vt4.8B" } }, "Architectures": [ @@ -110869,26 +307894,35 @@ ], "instructions": [ [ - "USUBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_u8", + "name": "vst4_p16", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "poly16_t * ptr", + "poly16x4x4_t val" ], "return_type": { - "value": "uint16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.8B" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ @@ -110898,26 +307932,35 @@ ], "instructions": [ [ - "USUBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubq_f16", + "name": "vst4_p64", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "poly64_t * ptr", + "poly64x1x4_t val" ], "return_type": { - "value": "float16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.8H" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ @@ -110926,26 +307969,35 @@ ], "instructions": [ [ - "FSUB" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubq_f32", + "name": "vst4_p8", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "poly8_t * ptr", + "poly8x8x4_t val" ], "return_type": { - "value": "float32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.4S" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { + "register": "Vt4.8B" } }, "Architectures": [ @@ -110955,53 +308007,73 @@ ], "instructions": [ [ - "FSUB" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubq_f64", + "name": "vst4_s16", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "int16_t * ptr", + "int16x4x4_t val" ], "return_type": { - "value": "float64x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.2D" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FSUB" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubq_s16", + "name": "vst4_s32", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int32_t * ptr", + "int32x2x4_t val" ], "return_type": { - "value": "int16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.8H" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { + "register": "Vt4.2S" } }, "Architectures": [ @@ -111011,26 +308083,35 @@ ], "instructions": [ [ - "SUB" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubq_s32", + "name": "vst4_s64", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int64_t * ptr", + "int64x1x4_t val" ], "return_type": { - "value": "int32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.4S" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ @@ -111040,26 +308121,35 @@ ], "instructions": [ [ - "SUB" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubq_s64", + "name": "vst4_s8", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "int8_t * ptr", + "int8x8x4_t val" ], "return_type": { - "value": "int64x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.2D" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { + "register": "Vt4.8B" } }, "Architectures": [ @@ -111069,26 +308159,35 @@ ], "instructions": [ [ - "SUB" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubq_s8", + "name": "vst4_u16", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "uint16_t * ptr", + "uint16x4x4_t val" ], "return_type": { - "value": "int8x16_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.16B" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ @@ -111098,26 +308197,35 @@ ], "instructions": [ [ - "SUB" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubq_u16", + "name": "vst4_u32", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "uint32_t * ptr", + "uint32x2x4_t val" ], "return_type": { - "value": "uint16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.8H" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { + "register": "Vt4.2S" } }, "Architectures": [ @@ -111127,26 +308235,35 @@ ], "instructions": [ [ - "SUB" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubq_u32", + "name": "vst4_u64", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "uint64_t * ptr", + "uint64x1x4_t val" ], "return_type": { - "value": "uint32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.4S" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ @@ -111156,26 +308273,35 @@ ], "instructions": [ [ - "SUB" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubq_u64", + "name": "vst4_u8", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "uint8_t * ptr", + "uint8x8x4_t val" ], "return_type": { - "value": "uint64x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.2D" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { + "register": "Vt4.8B" } }, "Architectures": [ @@ -111185,26 +308311,35 @@ ], "instructions": [ [ - "SUB" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubq_u8", + "name": "vst4q_f16", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "float16_t * ptr", + "float16x8x4_t val" ], "return_type": { - "value": "uint8x16_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.16B" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ @@ -111214,53 +308349,73 @@ ], "instructions": [ [ - "SUB" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_high_s16", + "name": "vst4q_f32", "arguments": [ - "int32x4_t a", - "int16x8_t b" + "float32_t * ptr", + "float32x4x4_t val" ], "return_type": { - "value": "int32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.8H" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { + "register": "Vt4.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SSUBW2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_high_s32", + "name": "vst4q_f64", "arguments": [ - "int64x2_t a", - "int32x4_t b" + "float64_t * ptr", + "float64x2x4_t val" ], "return_type": { - "value": "int64x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.4S" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ @@ -111268,80 +308423,126 @@ ], "instructions": [ [ - "SSUBW2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_high_s8", + "name": "vst4q_lane_f16", "arguments": [ - "int16x8_t a", - "int8x16_t b" + "float16_t * ptr", + "float16x8x4_t val", + "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SSUBW2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_high_u16", + "name": "vst4q_lane_f32", "arguments": [ - "uint32x4_t a", - "uint16x8_t b" + "float32_t * ptr", + "float32x4x4_t val", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.8H" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { + "register": "Vt4.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USUBW2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_high_u32", + "name": "vst4q_lane_f64", "arguments": [ - "uint64x2_t a", - "uint32x4_t b" + "float64_t * ptr", + "float64x2x4_t val", + "const int lane" ], "return_type": { - "value": "uint64x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.4S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ @@ -111349,111 +308550,165 @@ ], "instructions": [ [ - "USUBW2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_high_u8", + "name": "vst4q_lane_p16", "arguments": [ - "uint16x8_t a", - "uint8x16_t b" + "poly16_t * ptr", + "poly16x8x4_t val", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USUBW2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_s16", + "name": "vst4q_lane_p64", "arguments": [ - "int32x4_t a", - "int16x4_t b" + "poly64_t * ptr", + "poly64x2x4_t val", + "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.4H" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SSUBW" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_s32", + "name": "vst4q_lane_p8", "arguments": [ - "int64x2_t a", - "int32x2_t b" + "poly8_t * ptr", + "poly8x16x4_t val", + "const int lane" ], "return_type": { - "value": "int64x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "lane": { + "minimum": 0, + "maximum": 15 }, - "b": { - "register": "Vm.2S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { + "register": "Vt4.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SSUBW" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_s8", + "name": "vst4q_lane_s16", "arguments": [ - "int16x8_t a", - "int8x8_t b" + "int16_t * ptr", + "int16x8x4_t val", + "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.8B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ @@ -111463,26 +308718,40 @@ ], "instructions": [ [ - "SSUBW" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_u16", + "name": "vst4q_lane_s32", "arguments": [ - "uint32x4_t a", - "uint16x4_t b" + "int32_t * ptr", + "int32x4x4_t val", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.4H" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { + "register": "Vt4.4S" } }, "Architectures": [ @@ -111492,203 +308761,249 @@ ], "instructions": [ [ - "USUBW" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_u32", + "name": "vst4q_lane_s64", "arguments": [ - "uint64x2_t a", - "uint32x2_t b" + "int64_t * ptr", + "int64x2x4_t val", + "const int lane" ], "return_type": { - "value": "uint64x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.2S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USUBW" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_u8", + "name": "vst4q_lane_s8", "arguments": [ - "uint16x8_t a", - "uint8x8_t b" + "int8_t * ptr", + "int8x16x4_t val", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "lane": { + "minimum": 0, + "maximum": 15 }, - "b": { - "register": "Vm.8B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { + "register": "Vt4.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USUBW" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsudot_lane_s32", + "name": "vst4q_lane_u16", "arguments": [ - "int32x2_t r", - "int8x8_t a", - "uint8x8_t b", + "uint16_t * ptr", + "uint16x8x4_t val", "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.4B" - }, "lane": { "minimum": 0, - "maximum": 1 + "maximum": 7 }, - "r": { - "register": "Vd.2S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "SUDOT" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsudot_laneq_s32", + "name": "vst4q_lane_u32", "arguments": [ - "int32x2_t r", - "int8x8_t a", - "uint8x16_t b", + "uint32_t * ptr", + "uint32x4x4_t val", "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.4B" - }, "lane": { "minimum": 0, "maximum": 3 }, - "r": { - "register": "Vd.2S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { + "register": "Vt4.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SUDOT" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsudotq_lane_s32", + "name": "vst4q_lane_u64", "arguments": [ - "int32x4_t r", - "int8x16_t a", - "uint8x8_t b", + "uint64_t * ptr", + "uint64x2x4_t val", "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.4B" - }, "lane": { "minimum": 0, "maximum": 1 }, - "r": { - "register": "Vd.4S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SUDOT" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsudotq_laneq_s32", + "name": "vst4q_lane_u8", "arguments": [ - "int32x4_t r", - "int8x16_t a", - "uint8x16_t b", + "uint8_t * ptr", + "uint8x16x4_t val", "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.4B" - }, "lane": { "minimum": 0, - "maximum": 3 + "maximum": 15 }, - "r": { - "register": "Vd.4S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { + "register": "Vt4.16B" } }, "Architectures": [ @@ -111696,25 +309011,36 @@ ], "instructions": [ [ - "SUDOT" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl1_p8", + "name": "vst4q_p16", "arguments": [ - "poly8x8_t a", - "uint8x8_t idx" + "poly16_t * ptr", + "poly16x8x4_t val" ], "return_type": { - "value": "poly8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8H" }, - "idx": {} + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { + "register": "Vt4.8H" + } }, "Architectures": [ "v7", @@ -111723,52 +309049,72 @@ ], "instructions": [ [ - "TBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl1_s8", + "name": "vst4q_p64", "arguments": [ - "int8x8_t a", - "int8x8_t idx" + "poly64_t * ptr", + "poly64x2x4_t val" ], "return_type": { - "value": "int8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" }, - "idx": {} + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "TBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl1_u8", + "name": "vst4q_p8", "arguments": [ - "uint8x8_t a", - "uint8x8_t idx" + "poly8_t * ptr", + "poly8x16x4_t val" ], "return_type": { - "value": "uint8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" }, - "idx": {} + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { + "register": "Vt4.16B" + } }, "Architectures": [ "v7", @@ -111777,25 +309123,36 @@ ], "instructions": [ [ - "TBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl2_p8", + "name": "vst4q_s16", "arguments": [ - "poly8x8x2_t a", - "uint8x8_t idx" + "int16_t * ptr", + "int16x8x4_t val" ], "return_type": { - "value": "poly8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" }, - "idx": {} + "val.val[3]": { + "register": "Vt4.8H" + } }, "Architectures": [ "v7", @@ -111804,25 +309161,36 @@ ], "instructions": [ [ - "TBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl2_s8", + "name": "vst4q_s32", "arguments": [ - "int8x8x2_t a", - "int8x8_t idx" + "int32_t * ptr", + "int32x4x4_t val" ], "return_type": { - "value": "int8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" }, - "idx": {} + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { + "register": "Vt4.4S" + } }, "Architectures": [ "v7", @@ -111831,52 +309199,72 @@ ], "instructions": [ [ - "TBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl2_u8", + "name": "vst4q_s64", "arguments": [ - "uint8x8x2_t a", - "uint8x8_t idx" + "int64_t * ptr", + "int64x2x4_t val" ], "return_type": { - "value": "uint8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.2D" }, - "idx": {} + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "TBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl3_p8", + "name": "vst4q_s8", "arguments": [ - "poly8x8x3_t a", - "uint8x8_t idx" + "int8_t * ptr", + "int8x16x4_t val" ], "return_type": { - "value": "poly8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.16B" }, - "idx": {} + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { + "register": "Vt4.16B" + } }, "Architectures": [ "v7", @@ -111885,25 +309273,36 @@ ], "instructions": [ [ - "TBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl3_s8", + "name": "vst4q_u16", "arguments": [ - "int8x8x3_t a", - "int8x8_t idx" + "uint16_t * ptr", + "uint16x8x4_t val" ], "return_type": { - "value": "int8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" }, - "idx": {} + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { + "register": "Vt4.8H" + } }, "Architectures": [ "v7", @@ -111912,25 +309311,36 @@ ], "instructions": [ [ - "TBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl3_u8", + "name": "vst4q_u32", "arguments": [ - "uint8x8x3_t a", - "uint8x8_t idx" + "uint32_t * ptr", + "uint32x4x4_t val" ], "return_type": { - "value": "uint8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" }, - "idx": {} + "val.val[3]": { + "register": "Vt4.4S" + } }, "Architectures": [ "v7", @@ -111939,52 +309349,72 @@ ], "instructions": [ [ - "TBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl4_p8", + "name": "vst4q_u64", "arguments": [ - "poly8x8x4_t a", - "uint8x8_t idx" + "uint64_t * ptr", + "uint64x2x4_t val" ], "return_type": { - "value": "poly8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" }, - "idx": {} + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "TBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl4_s8", + "name": "vst4q_u8", "arguments": [ - "int8x8x4_t a", - "int8x8_t idx" + "uint8_t * ptr", + "uint8x16x4_t val" ], "return_type": { - "value": "int8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" }, - "idx": {} + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { + "register": "Vt4.16B" + } }, "Architectures": [ "v7", @@ -111993,333 +309423,339 @@ ], "instructions": [ [ - "TBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl4_u8", + "name": "vstl1_lane_f64", "arguments": [ - "uint8x8x4_t a", - "uint8x8_t idx" + "float64_t * ptr", + "float64x1_t val", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 0 }, - "idx": {} + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.1D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "TBL" + "STL1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx1_p8", + "name": "vstl1_lane_p64", "arguments": [ - "poly8x8_t a", - "poly8x8_t b", - "uint8x8_t idx" + "poly64_t * ptr", + "poly64x1_t val", + "const int lane" ], "return_type": { - "value": "poly8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" }, - "idx": {} + "val": { + "register": "Vt.1D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MOVI", - "CMHS", - "TBL", - "BIF" + "STL1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx1_s8", + "name": "vstl1_lane_s64", "arguments": [ - "int8x8_t a", - "int8x8_t b", - "int8x8_t idx" + "int64_t * ptr", + "int64x1_t val", + "const int lane" ], "return_type": { - "value": "int8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" }, - "idx": {} + "val": { + "register": "Vt.1D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MOVI", - "CMHS", - "TBL", - "BIF" + "STL1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx1_u8", + "name": "vstl1_lane_u64", "arguments": [ - "uint8x8_t a", - "uint8x8_t b", - "uint8x8_t idx" + "uint64_t * ptr", + "uint64x1_t val", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" }, - "idx": {} + "val": { + "register": "Vt.1D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MOVI", - "CMHS", - "TBL", - "BIF" + "STL1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx2_p8", + "name": "vstl1q_lane_f64", "arguments": [ - "poly8x8_t a", - "poly8x8x2_t b", - "uint8x8_t idx" + "float64_t * ptr", + "float64x2_t val", + "const int lane" ], "return_type": { - "value": "poly8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" }, - "idx": {} + "val": { + "register": "Vt.2D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "TBX" + "STL1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx2_s8", + "name": "vstl1q_lane_p64", "arguments": [ - "int8x8_t a", - "int8x8x2_t b", - "int8x8_t idx" + "poly64_t * ptr", + "poly64x2_t val", + "const int lane" ], "return_type": { - "value": "int8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" }, - "idx": {} + "val": { + "register": "Vt.2D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "TBX" + "STL1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx2_u8", + "name": "vstl1q_lane_s64", "arguments": [ - "uint8x8_t a", - "uint8x8x2_t b", - "uint8x8_t idx" + "int64_t * ptr", + "int64x2_t val", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" }, - "idx": {} + "val": { + "register": "Vt.2D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "TBX" + "STL1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx3_p8", + "name": "vstl1q_lane_u64", "arguments": [ - "poly8x8_t a", - "poly8x8x3_t b", - "uint8x8_t idx" + "uint64_t * ptr", + "uint64x2_t val", + "const int lane" ], "return_type": { - "value": "poly8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 1 }, - "idx": {} + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.2D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MOVI", - "CMHS", - "TBL", - "BIF" + "STL1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx3_s8", + "name": "vstrq_p128", "arguments": [ - "int8x8_t a", - "int8x8x3_t b", - "int8x8_t idx" + "poly128_t * ptr", + "poly128_t val" ], "return_type": { - "value": "int8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" }, - "idx": {} + "val": { + "register": "Qt" + } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "MOVI", - "CMHS", - "TBL", - "BIF" + "STR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx3_u8", + "name": "vsub_f16", "arguments": [ - "uint8x8_t a", - "uint8x8x3_t b", - "uint8x8_t idx" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "a": { + "register": "Vn.4H" }, - "idx": {} + "b": { + "register": "Vm.4H" + } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "MOVI", - "CMHS", - "TBL", - "BIF" + "FSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx4_p8", + "name": "vsub_f32", "arguments": [ - "poly8x8_t a", - "poly8x8x4_t b", - "uint8x8_t idx" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "a": { + "register": "Vn.2S" }, - "idx": {} + "b": { + "register": "Vm.2S" + } }, "Architectures": [ "v7", @@ -112328,56 +309764,54 @@ ], "instructions": [ [ - "TBX" + "FSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx4_s8", + "name": "vsub_f64", "arguments": [ - "int8x8_t a", - "int8x8x4_t b", - "int8x8_t idx" + "float64x1_t a", + "float64x1_t b" ], "return_type": { - "value": "int8x8_t" + "value": "float64x1_t" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "a": { + "register": "Dn" }, - "idx": {} + "b": { + "register": "Dm" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "TBX" + "FSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx4_u8", + "name": "vsub_s16", "arguments": [ - "uint8x8_t a", - "uint8x8x4_t b", - "uint8x8_t idx" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "a": { + "register": "Vn.4H" }, - "idx": {} + "b": { + "register": "Vm.4H" + } }, "Architectures": [ "v7", @@ -112386,181 +309820,193 @@ ], "instructions": [ [ - "TBX" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1_f16", + "name": "vsub_s32", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "float16x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.2S" }, "b": { - "register": "Vm.4H" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1_f32", + "name": "vsub_s64", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "int64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "float32x2_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Dn" }, "b": { - "register": "Vm.2S" + "register": "Dm" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1_p16", + "name": "vsub_s8", "arguments": [ - "poly16x4_t a", - "poly16x4_t b" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "poly16x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.8B" }, "b": { - "register": "Vm.4H" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1_p8", + "name": "vsub_u16", "arguments": [ - "poly8x8_t a", - "poly8x8_t b" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4H" }, "b": { - "register": "Vm.8B" + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1_s16", + "name": "vsub_u32", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "int16x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.2S" }, "b": { - "register": "Vm.4H" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1_s32", + "name": "vsub_u64", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "uint64x1_t a", + "uint64x1_t b" ], "return_type": { - "value": "int32x2_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Dn" }, "b": { - "register": "Vm.2S" + "register": "Dm" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1_s8", + "name": "vsub_u8", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "int8x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { @@ -112571,30 +310017,32 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1_u16", + "name": "vsubd_s64", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "int64_t a", + "int64_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Dn" }, "b": { - "register": "Vm.4H" + "register": "Dm" } }, "Architectures": [ @@ -112602,26 +310050,26 @@ ], "instructions": [ [ - "TRN1" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1_u32", + "name": "vsubd_u64", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "uint64_t a", + "uint64_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Dn" }, "b": { - "register": "Vm.2S" + "register": "Dm" } }, "Architectures": [ @@ -112629,46 +310077,48 @@ ], "instructions": [ [ - "TRN1" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1_u8", + "name": "vsubh_f16", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "float16_t a", + "float16_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Hn" }, "b": { - "register": "Vm.8B" + "register": "Hm" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "TRN1" + "FSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_f16", + "name": "vsubhn_high_s16", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "int8x8_t r", + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "float16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { @@ -112676,6 +310126,9 @@ }, "b": { "register": "Vm.8H" + }, + "r": { + "register": "Vd.8B" } }, "Architectures": [ @@ -112683,19 +310136,20 @@ ], "instructions": [ [ - "TRN1" + "SUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_f32", + "name": "vsubhn_high_s32", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "int16x4_t r", + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "float32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -112703,6 +310157,9 @@ }, "b": { "register": "Vm.4S" + }, + "r": { + "register": "Vd.4H" } }, "Architectures": [ @@ -112710,19 +310167,20 @@ ], "instructions": [ [ - "TRN1" + "SUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_f64", + "name": "vsubhn_high_s64", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "int32x2_t r", + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "float64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -112730,6 +310188,9 @@ }, "b": { "register": "Vm.2D" + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ @@ -112737,19 +310198,20 @@ ], "instructions": [ [ - "TRN1" + "SUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_p16", + "name": "vsubhn_high_u16", "arguments": [ - "poly16x8_t a", - "poly16x8_t b" + "uint8x8_t r", + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "poly16x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { @@ -112757,6 +310219,9 @@ }, "b": { "register": "Vm.8H" + }, + "r": { + "register": "Vd.8B" } }, "Architectures": [ @@ -112764,26 +310229,30 @@ ], "instructions": [ [ - "TRN1" + "SUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_p64", + "name": "vsubhn_high_u32", "arguments": [ - "poly64x2_t a", - "poly64x2_t b" + "uint16x4_t r", + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "poly64x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.4S" }, "b": { - "register": "Vm.2D" + "register": "Vm.4S" + }, + "r": { + "register": "Vd.4H" } }, "Architectures": [ @@ -112791,26 +310260,30 @@ ], "instructions": [ [ - "TRN1" + "SUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_p8", + "name": "vsubhn_high_u64", "arguments": [ - "poly8x16_t a", - "poly8x16_t b" + "uint32x2_t r", + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.2D" }, "b": { - "register": "Vm.16B" + "register": "Vm.2D" + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ @@ -112818,19 +310291,19 @@ ], "instructions": [ [ - "TRN1" + "SUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_s16", + "name": "vsubhn_s16", "arguments": [ "int16x8_t a", "int16x8_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { @@ -112841,23 +310314,25 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_s32", + "name": "vsubhn_s32", "arguments": [ "int32x4_t a", "int32x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { @@ -112868,23 +310343,25 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_s64", + "name": "vsubhn_s64", "arguments": [ "int64x2_t a", "int64x2_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -112895,111 +310372,119 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_s8", + "name": "vsubhn_u16", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int8x16_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, "b": { - "register": "Vm.16B" + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_u16", + "name": "vsubhn_u32", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4S" }, "b": { - "register": "Vm.8H" + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_u32", + "name": "vsubhn_u64", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2D" }, "b": { - "register": "Vm.4S" + "register": "Vm.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_u64", + "name": "vsubl_high_s16", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.8H" }, "b": { - "register": "Vm.2D" + "register": "Vm.8H" } }, "Architectures": [ @@ -113007,26 +310492,26 @@ ], "instructions": [ [ - "TRN1" + "SSUBL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_u8", + "name": "vsubl_high_s32", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" }, "b": { - "register": "Vm.16B" + "register": "Vm.4S" } }, "Architectures": [ @@ -113034,26 +310519,26 @@ ], "instructions": [ [ - "TRN1" + "SSUBL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2_f16", + "name": "vsubl_high_s8", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "float16x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.16B" }, "b": { - "register": "Vm.4H" + "register": "Vm.16B" } }, "Architectures": [ @@ -113061,26 +310546,26 @@ ], "instructions": [ [ - "TRN2" + "SSUBL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2_f32", + "name": "vsubl_high_u16", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "float32x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.8H" }, "b": { - "register": "Vm.2S" + "register": "Vm.8H" } }, "Architectures": [ @@ -113088,26 +310573,26 @@ ], "instructions": [ [ - "TRN2" + "USUBL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2_p16", + "name": "vsubl_high_u32", "arguments": [ - "poly16x4_t a", - "poly16x4_t b" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "poly16x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.4S" }, "b": { - "register": "Vm.4H" + "register": "Vm.4S" } }, "Architectures": [ @@ -113115,26 +310600,26 @@ ], "instructions": [ [ - "TRN2" + "USUBL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2_p8", + "name": "vsubl_high_u8", "arguments": [ - "poly8x8_t a", - "poly8x8_t b" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.16B" }, "b": { - "register": "Vm.8B" + "register": "Vm.16B" } }, "Architectures": [ @@ -113142,19 +310627,19 @@ ], "instructions": [ [ - "TRN2" + "USUBL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2_s16", + "name": "vsubl_s16", "arguments": [ "int16x4_t a", "int16x4_t b" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -113165,23 +310650,25 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "SSUBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2_s32", + "name": "vsubl_s32", "arguments": [ "int32x2_t a", "int32x2_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { @@ -113192,23 +310679,25 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "SSUBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2_s8", + "name": "vsubl_s8", "arguments": [ "int8x8_t a", "int8x8_t b" ], "return_type": { - "value": "int8x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -113219,23 +310708,25 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "SSUBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2_u16", + "name": "vsubl_u16", "arguments": [ "uint16x4_t a", "uint16x4_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { @@ -113246,23 +310737,25 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "USUBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2_u32", + "name": "vsubl_u32", "arguments": [ "uint32x2_t a", "uint32x2_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { @@ -113273,23 +310766,25 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "USUBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2_u8", + "name": "vsubl_u8", "arguments": [ "uint8x8_t a", "uint8x8_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { @@ -113300,17 +310795,19 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "USUBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_f16", + "name": "vsubq_f16", "arguments": [ "float16x8_t a", "float16x8_t b" @@ -113327,17 +310824,18 @@ } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "TRN2" + "FSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_f32", + "name": "vsubq_f32", "arguments": [ "float32x4_t a", "float32x4_t b" @@ -113354,17 +310852,19 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "FSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_f64", + "name": "vsubq_f64", "arguments": [ "float64x2_t a", "float64x2_t b" @@ -113385,19 +310885,19 @@ ], "instructions": [ [ - "TRN2" + "FSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_p16", + "name": "vsubq_s16", "arguments": [ - "poly16x8_t a", - "poly16x8_t b" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "poly16x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -113408,219 +310908,235 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_p64", + "name": "vsubq_s32", "arguments": [ - "poly64x2_t a", - "poly64x2_t b" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "poly64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.4S" }, "b": { - "register": "Vm.2D" + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_p8", + "name": "vsubq_s64", "arguments": [ - "poly8x16_t a", - "poly8x16_t b" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.2D" }, "b": { - "register": "Vm.16B" + "register": "Vm.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_s16", + "name": "vsubq_s8", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { - "register": "Vm.8H" + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_s32", + "name": "vsubq_u16", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.8H" }, "b": { - "register": "Vm.4S" + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_s64", + "name": "vsubq_u32", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.4S" }, "b": { - "register": "Vm.2D" + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_s8", + "name": "vsubq_u64", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "int8x16_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.2D" }, "b": { - "register": "Vm.16B" + "register": "Vm.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_u16", + "name": "vsubq_u8", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { - "register": "Vm.8H" + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_u32", + "name": "vsubw_high_s16", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "int32x4_t a", + "int16x8_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" }, "b": { - "register": "Vm.4S" + "register": "Vm.8H" } }, "Architectures": [ @@ -113628,26 +311144,26 @@ ], "instructions": [ [ - "TRN2" + "SSUBW2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_u64", + "name": "vsubw_high_s32", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "int64x2_t a", + "int32x4_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2D" }, "b": { - "register": "Vm.2D" + "register": "Vm.4S" } }, "Architectures": [ @@ -113655,23 +311171,23 @@ ], "instructions": [ [ - "TRN2" + "SSUBW2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_u8", + "name": "vsubw_high_s8", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "int16x8_t a", + "int8x16_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, "b": { "register": "Vm.16B" @@ -113682,143 +311198,104 @@ ], "instructions": [ [ - "TRN2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vtrn_f16", - "arguments": [ - "float16x4_t a", - "float16x4_t b" - ], - "return_type": { - "value": "float16x4x2_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "TRN1", - "TRN2" + "SSUBW2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn_f32", + "name": "vsubw_high_u16", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "uint32x4_t a", + "uint16x8_t b" ], "return_type": { - "value": "float32x2x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4S" }, "b": { - "register": "Vm.2S" + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "TRN1", - "TRN2" + "USUBW2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn_p16", + "name": "vsubw_high_u32", "arguments": [ - "poly16x4_t a", - "poly16x4_t b" + "uint64x2_t a", + "uint32x4_t b" ], "return_type": { - "value": "poly16x4x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.2D" }, "b": { - "register": "Vm.4H" + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "TRN1", - "TRN2" + "USUBW2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn_p8", + "name": "vsubw_high_u8", "arguments": [ - "poly8x8_t a", - "poly8x8_t b" + "uint16x8_t a", + "uint8x16_t b" ], "return_type": { - "value": "poly8x8x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" }, "b": { - "register": "Vm.8B" + "register": "Vm.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "TRN1", - "TRN2" + "USUBW2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn_s16", + "name": "vsubw_s16", "arguments": [ - "int16x4_t a", + "int32x4_t a", "int16x4_t b" ], "return_type": { - "value": "int16x4x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.4S" }, "b": { "register": "Vm.4H" @@ -113831,24 +311308,23 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "SSUBW" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn_s32", + "name": "vsubw_s32", "arguments": [ - "int32x2_t a", + "int64x2_t a", "int32x2_t b" ], "return_type": { - "value": "int32x2x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.2D" }, "b": { "register": "Vm.2S" @@ -113861,24 +311337,23 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "SSUBW" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn_s8", + "name": "vsubw_s8", "arguments": [ - "int8x8_t a", + "int16x8_t a", "int8x8_t b" ], "return_type": { - "value": "int8x8x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" }, "b": { "register": "Vm.8B" @@ -113891,24 +311366,23 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "SSUBW" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn_u16", + "name": "vsubw_u16", "arguments": [ - "uint16x4_t a", + "uint32x4_t a", "uint16x4_t b" ], "return_type": { - "value": "uint16x4x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.4S" }, "b": { "register": "Vm.4H" @@ -113921,24 +311395,23 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "USUBW" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn_u32", + "name": "vsubw_u32", "arguments": [ - "uint32x2_t a", + "uint64x2_t a", "uint32x2_t b" ], "return_type": { - "value": "uint32x2x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.2D" }, "b": { "register": "Vm.2S" @@ -113951,24 +311424,23 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "USUBW" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn_u8", + "name": "vsubw_u8", "arguments": [ - "uint8x8_t a", + "uint16x8_t a", "uint8x8_t b" ], "return_type": { - "value": "uint8x8x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" }, "b": { "register": "Vm.8B" @@ -113981,147 +311453,174 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "USUBW" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrnq_f16", + "name": "vsudot_lane_s32", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "int32x2_t r", + "int8x8_t a", + "uint8x8_t b", + "const int lane" ], "return_type": { - "value": "float16x8x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" }, "b": { - "register": "Vm.8H" + "register": "Vm.4B" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "TRN1", - "TRN2" + "SUDOT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrnq_f32", + "name": "vsudot_laneq_s32", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "int32x2_t r", + "int8x8_t a", + "uint8x16_t b", + "const int lane" ], "return_type": { - "value": "float32x4x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.8B" }, "b": { - "register": "Vm.4S" + "register": "Vm.4B" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "TRN1", - "TRN2" + "SUDOT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrnq_p16", + "name": "vsudotq_lane_s32", "arguments": [ - "poly16x8_t a", - "poly16x8_t b" + "int32x4_t r", + "int8x16_t a", + "uint8x8_t b", + "const int lane" ], "return_type": { - "value": "poly16x8x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" }, "b": { - "register": "Vm.8H" + "register": "Vm.4B" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "r": { + "register": "Vd.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "TRN1", - "TRN2" + "SUDOT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrnq_p8", + "name": "vsudotq_laneq_s32", "arguments": [ - "poly8x16_t a", - "poly8x16_t b" + "int32x4_t r", + "int8x16_t a", + "uint8x16_t b", + "const int lane" ], "return_type": { - "value": "poly8x16x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8B" }, "b": { - "register": "Vm.16B" + "register": "Vm.4B" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "TRN1", - "TRN2" + "SUDOT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrnq_s16", + "name": "vtbl1_p8", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "poly8x8_t a", + "uint8x8_t idx" ], "return_type": { - "value": "int16x8x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "Zeros(64):a": { + "register": "Vn.16B" }, - "b": { - "register": "Vm.8H" + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114131,27 +311630,26 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrnq_s32", + "name": "vtbl1_s8", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int8x8_t a", + "int8x8_t idx" ], "return_type": { - "value": "int32x4x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "Zeros(64):a": { + "register": "Vn.16B" }, - "b": { - "register": "Vm.4S" + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114161,27 +311659,26 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrnq_s8", + "name": "vtbl1_u8", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "uint8x8_t a", + "uint8x8_t idx" ], "return_type": { - "value": "int8x16x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { + "Zeros(64):a": { "register": "Vn.16B" }, - "b": { - "register": "Vm.16B" + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114191,27 +311688,26 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrnq_u16", + "name": "vtbl2_p8", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "poly8x8x2_t a", + "uint8x8_t idx" ], "return_type": { - "value": "uint16x8x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "a.val[1]:a.val[0]": { + "register": "Vn.16B" }, - "b": { - "register": "Vm.8H" + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114221,27 +311717,26 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrnq_u32", + "name": "vtbl2_s8", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "int8x8x2_t a", + "int8x8_t idx" ], "return_type": { - "value": "uint32x4x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "a.val[1]:a.val[0]": { + "register": "Vn.16B" }, - "b": { - "register": "Vm.4S" + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114251,27 +311746,26 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrnq_u8", + "name": "vtbl2_u8", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "uint8x8x2_t a", + "uint8x8_t idx" ], "return_type": { - "value": "uint8x16x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { + "a.val[1]:a.val[0]": { "register": "Vn.16B" }, - "b": { - "register": "Vm.16B" + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114281,54 +311775,60 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtst_p64", + "name": "vtbl3_p8", "arguments": [ - "poly64x1_t a", - "poly64x1_t b" + "poly8x8x3_t a", + "uint8x8_t idx" ], "return_type": { - "value": "uint64x1_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "Zeros(64):a.val[2]": { + "register": "Vn+1.16B" }, - "b": { - "register": "Dm" + "a.val[1]:a.val[0]": { + "register": "Vn.16B" + }, + "idx": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "CMTST" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtst_p8", + "name": "vtbl3_s8", "arguments": [ - "poly8x8_t a", - "poly8x8_t b" + "int8x8x3_t a", + "int8x8_t idx" ], "return_type": { - "value": "uint8x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "Zeros(64):a.val[2]": { + "register": "Vn+1.16B" }, - "b": { + "a.val[1]:a.val[0]": { + "register": "Vn.16B" + }, + "idx": { "register": "Vm.8B" } }, @@ -114339,26 +311839,29 @@ ], "instructions": [ [ - "CMTST" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtst_s16", + "name": "vtbl3_u8", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "uint8x8x3_t a", + "uint8x8_t idx" ], "return_type": { - "value": "uint16x4_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "Zeros(64):a.val[2]": { + "register": "Vn+1.16B" }, - "b": { - "register": "Vm.4H" + "a.val[1]:a.val[0]": { + "register": "Vn.16B" + }, + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114368,26 +311871,29 @@ ], "instructions": [ [ - "CMTST" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtst_s32", + "name": "vtbl4_p8", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "poly8x8x4_t a", + "uint8x8_t idx" ], "return_type": { - "value": "uint32x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "a.val[1]:a.val[0]": { + "register": "Vn.16B" }, - "b": { - "register": "Vm.2S" + "a.val[3]:a.val[2]": { + "register": "Vn+1.16B" + }, + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114397,52 +311903,60 @@ ], "instructions": [ [ - "CMTST" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtst_s64", + "name": "vtbl4_s8", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "int8x8x4_t a", + "int8x8_t idx" ], "return_type": { - "value": "uint64x1_t" + "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "a.val[1]:a.val[0]": { + "register": "Vn.16B" }, - "b": { - "register": "Dm" + "a.val[3]:a.val[2]": { + "register": "Vn+1.16B" + }, + "idx": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "CMTST" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtst_s8", + "name": "vtbl4_u8", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "uint8x8x4_t a", + "uint8x8_t idx" ], "return_type": { "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "a.val[1]:a.val[0]": { + "register": "Vn.16B" }, - "b": { + "a.val[3]:a.val[2]": { + "register": "Vn+1.16B" + }, + "idx": { "register": "Vm.8B" } }, @@ -114453,26 +311967,30 @@ ], "instructions": [ [ - "CMTST" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtst_u16", + "name": "vtbx1_p8", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "poly8x8_t a", + "poly8x8_t b", + "uint8x8_t idx" ], "return_type": { - "value": "uint16x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { + "Zeros(64):b": { + "register": "Vn.16B" + }, "a": { - "register": "Vn.4H" + "register": "Vd.8B" }, - "b": { - "register": "Vm.4H" + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114482,26 +312000,33 @@ ], "instructions": [ [ - "CMTST" + "MOVI", + "CMHS", + "TBL", + "BIF" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtst_u32", + "name": "vtbx1_s8", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "int8x8_t a", + "int8x8_t b", + "int8x8_t idx" ], "return_type": { - "value": "uint32x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { + "Zeros(64):b": { + "register": "Vn.16B" + }, "a": { - "register": "Vn.2S" + "register": "Vd.8B" }, - "b": { - "register": "Vm.2S" + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114511,52 +312036,68 @@ ], "instructions": [ [ - "CMTST" + "MOVI", + "CMHS", + "TBL", + "BIF" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtst_u64", + "name": "vtbx1_u8", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "uint8x8_t a", + "uint8x8_t b", + "uint8x8_t idx" ], "return_type": { - "value": "uint64x1_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { + "Zeros(64):b": { + "register": "Vn.16B" + }, "a": { - "register": "Dn" + "register": "Vd.8B" }, - "b": { - "register": "Dm" + "idx": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "CMTST" + "MOVI", + "CMHS", + "TBL", + "BIF" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtst_u8", + "name": "vtbx2_p8", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "poly8x8_t a", + "poly8x8x2_t b", + "uint8x8_t idx" ], "return_type": { - "value": "uint8x8_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vd.8B" }, - "b": { + "b.val[1]:b.val[0]": { + "register": "Vn.16B" + }, + "idx": { "register": "Vm.8B" } }, @@ -114567,108 +312108,138 @@ ], "instructions": [ [ - "CMTST" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstd_s64", + "name": "vtbx2_s8", "arguments": [ - "int64_t a", - "int64_t b" + "int8x8_t a", + "int8x8x2_t b", + "int8x8_t idx" ], "return_type": { - "value": "uint64_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.8B" }, - "b": { - "register": "Dm" + "b.val[1]:b.val[0]": { + "register": "Vn.16B" + }, + "idx": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "CMTST" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstd_u64", + "name": "vtbx2_u8", "arguments": [ - "uint64_t a", - "uint64_t b" + "uint8x8_t a", + "uint8x8x2_t b", + "uint8x8_t idx" ], "return_type": { - "value": "uint64_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.8B" }, - "b": { - "register": "Dm" + "b.val[1]:b.val[0]": { + "register": "Vn.16B" + }, + "idx": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "CMTST" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstq_p64", + "name": "vtbx3_p8", "arguments": [ - "poly64x2_t a", - "poly64x2_t b" + "poly8x8_t a", + "poly8x8x3_t b", + "uint8x8_t idx" ], "return_type": { - "value": "uint64x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { + "Zeros(64):b.val[2]": { + "register": "Vn+1.16B" + }, "a": { - "register": "Vn.2D" + "register": "Vd.8B" }, - "b": { - "register": "Vm.2D" + "b.val[1]:b.val[0]": { + "register": "Vn.16B" + }, + "idx": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "CMTST" + "MOVI", + "CMHS", + "TBL", + "BIF" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstq_p8", + "name": "vtbx3_s8", "arguments": [ - "poly8x16_t a", - "poly8x16_t b" + "int8x8_t a", + "int8x8x3_t b", + "int8x8_t idx" ], "return_type": { - "value": "uint8x16_t" + "value": "int8x8_t" }, "Arguments_Preparation": { + "Zeros(64):b.val[2]": { + "register": "Vn+1.16B" + }, "a": { + "register": "Vd.8B" + }, + "b.val[1]:b.val[0]": { "register": "Vn.16B" }, - "b": { - "register": "Vm.16B" + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114678,26 +312249,36 @@ ], "instructions": [ [ - "CMTST" + "MOVI", + "CMHS", + "TBL", + "BIF" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstq_s16", + "name": "vtbx3_u8", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "uint8x8_t a", + "uint8x8x3_t b", + "uint8x8_t idx" ], "return_type": { - "value": "uint16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { + "Zeros(64):b.val[2]": { + "register": "Vn+1.16B" + }, "a": { - "register": "Vn.8H" + "register": "Vd.8B" }, - "b": { - "register": "Vm.8H" + "b.val[1]:b.val[0]": { + "register": "Vn.16B" + }, + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114707,26 +312288,36 @@ ], "instructions": [ [ - "CMTST" + "MOVI", + "CMHS", + "TBL", + "BIF" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstq_s32", + "name": "vtbx4_p8", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "poly8x8_t a", + "poly8x8x4_t b", + "uint8x8_t idx" ], "return_type": { - "value": "uint32x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.8B" }, - "b": { - "register": "Vm.4S" + "b.val[1]:b.val[0]": { + "register": "Vn.16B" + }, + "b.val[3]:b.val[2]": { + "register": "Vn+1.16B" + }, + "c": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114736,53 +312327,69 @@ ], "instructions": [ [ - "CMTST" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstq_s64", + "name": "vtbx4_s8", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "int8x8_t a", + "int8x8x4_t b", + "int8x8_t idx" ], "return_type": { - "value": "uint64x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.8B" }, - "b": { - "register": "Vm.2D" + "b.val[1]:b.val[0]": { + "register": "Vn.16B" + }, + "b.val[3]:b.val[2]": { + "register": "Vn+1.16B" + }, + "c": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "CMTST" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstq_s8", + "name": "vtbx4_u8", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "uint8x8_t a", + "uint8x8x4_t b", + "uint8x8_t idx" ], "return_type": { - "value": "uint8x16_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.8B" + }, + "b.val[1]:b.val[0]": { "register": "Vn.16B" }, - "b": { - "register": "Vm.16B" + "b.val[3]:b.val[2]": { + "register": "Vn+1.16B" + }, + "c": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114792,84 +312399,80 @@ ], "instructions": [ [ - "CMTST" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstq_u16", + "name": "vtrn1_f16", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4H" }, "b": { - "register": "Vm.8H" + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMTST" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstq_u32", + "name": "vtrn1_f32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2S" }, "b": { - "register": "Vm.4S" + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMTST" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstq_u64", + "name": "vtrn1_p16", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "poly16x4_t a", + "poly16x4_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.4H" }, "b": { - "register": "Vm.2D" + "register": "Vm.4H" } }, "Architectures": [ @@ -114877,55 +312480,53 @@ ], "instructions": [ [ - "CMTST" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstq_u8", + "name": "vtrn1_p8", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "poly8x8_t a", + "poly8x8_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8B" }, "b": { - "register": "Vm.16B" + "register": "Vm.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMTST" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqadd_s16", + "name": "vtrn1_s16", "arguments": [ "int16x4_t a", - "uint16x4_t b" + "int16x4_t b" ], "return_type": { "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.4H" }, "b": { - "register": "Vn.4H" + "register": "Vm.4H" } }, "Architectures": [ @@ -114933,26 +312534,26 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqadd_s32", + "name": "vtrn1_s32", "arguments": [ "int32x2_t a", - "uint32x2_t b" + "int32x2_t b" ], "return_type": { "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.2S" }, "b": { - "register": "Vn.2S" + "register": "Vm.2S" } }, "Architectures": [ @@ -114960,26 +312561,26 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqadd_s64", + "name": "vtrn1_s8", "arguments": [ - "int64x1_t a", - "uint64x1_t b" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "int64x1_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.8B" }, "b": { - "register": "Dn" + "register": "Vm.8B" } }, "Architectures": [ @@ -114987,26 +312588,26 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqadd_s8", + "name": "vtrn1_u16", "arguments": [ - "int8x8_t a", - "uint8x8_t b" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "int8x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vn.4H" }, "b": { - "register": "Vn.8B" + "register": "Vm.4H" } }, "Architectures": [ @@ -115014,26 +312615,26 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqaddb_s8", + "name": "vtrn1_u32", "arguments": [ - "int8_t a", - "uint8_t b" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "int8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Bd" + "register": "Vn.2S" }, "b": { - "register": "Bn" + "register": "Vm.2S" } }, "Architectures": [ @@ -115041,26 +312642,26 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqaddd_s64", + "name": "vtrn1_u8", "arguments": [ - "int64_t a", - "uint64_t b" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "int64_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.8B" }, "b": { - "register": "Dn" + "register": "Vm.8B" } }, "Architectures": [ @@ -115068,26 +312669,26 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqaddh_s16", + "name": "vtrn1q_f16", "arguments": [ - "int16_t a", - "uint16_t b" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "int16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Hd" + "register": "Vn.8H" }, "b": { - "register": "Hn" + "register": "Vm.8H" } }, "Architectures": [ @@ -115095,26 +312696,26 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqaddq_s16", + "name": "vtrn1q_f32", "arguments": [ - "int16x8_t a", - "uint16x8_t b" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "int16x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vn.4S" }, "b": { - "register": "Vn.8H" + "register": "Vm.4S" } }, "Architectures": [ @@ -115122,26 +312723,26 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqaddq_s32", + "name": "vtrn1q_f64", "arguments": [ - "int32x4_t a", - "uint32x4_t b" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "int32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.2D" }, "b": { - "register": "Vn.4S" + "register": "Vm.2D" } }, "Architectures": [ @@ -115149,26 +312750,26 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqaddq_s64", + "name": "vtrn1q_p16", "arguments": [ - "int64x2_t a", - "uint64x2_t b" + "poly16x8_t a", + "poly16x8_t b" ], "return_type": { - "value": "int64x2_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.8H" }, "b": { - "register": "Vn.2D" + "register": "Vm.8H" } }, "Architectures": [ @@ -115176,26 +312777,26 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqaddq_s8", + "name": "vtrn1q_p64", "arguments": [ - "int8x16_t a", - "uint8x16_t b" + "poly64x2_t a", + "poly64x2_t b" ], "return_type": { - "value": "int8x16_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vn.2D" }, "b": { - "register": "Vn.16B" + "register": "Vm.2D" } }, "Architectures": [ @@ -115203,26 +312804,26 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqadds_s32", + "name": "vtrn1q_p8", "arguments": [ - "int32_t a", - "uint32_t b" + "poly8x16_t a", + "poly8x16_t b" ], "return_type": { - "value": "int32_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" + "register": "Vn.16B" }, "b": { - "register": "Sn" + "register": "Vm.16B" } }, "Architectures": [ @@ -115230,72 +312831,53 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vusdot_lane_s32", + "name": "vtrn1q_s16", "arguments": [ - "int32x2_t r", - "uint8x8_t a", - "int8x8_t b", - "const int lane" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" }, "b": { - "register": "Vm.4B" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.2S" + "register": "Vm.8H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "USDOT" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vusdot_laneq_s32", + "name": "vtrn1q_s32", "arguments": [ - "int32x2_t r", - "uint8x8_t a", - "int8x16_t b", - "const int lane" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4S" }, "b": { - "register": "Vm.4B" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.2S" + "register": "Vm.4S" } }, "Architectures": [ @@ -115303,104 +312885,80 @@ ], "instructions": [ [ - "USDOT" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vusdot_s32", + "name": "vtrn1q_s64", "arguments": [ - "int32x2_t r", - "uint8x8_t a", - "int8x8_t b" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2D" }, "b": { - "register": "Vm.8B" - }, - "r": { - "register": "Vd.2S" + "register": "Vm.2D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "USDOT" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vusdotq_lane_s32", + "name": "vtrn1q_s8", "arguments": [ - "int32x4_t r", - "uint8x16_t a", - "int8x8_t b", - "const int lane" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { "register": "Vn.16B" }, "b": { - "register": "Vm.4B" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.4S" + "register": "Vm.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "USDOT" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vusdotq_laneq_s32", + "name": "vtrn1q_u16", "arguments": [ - "int32x4_t r", - "uint8x16_t a", - "int8x16_t b", - "const int lane" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, "b": { - "register": "Vm.4B" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.4S" + "register": "Vm.8H" } }, "Architectures": [ @@ -115408,30 +312966,53 @@ ], "instructions": [ [ - "USDOT" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vusdotq_s32", + "name": "vtrn1q_u32", "arguments": [ - "int32x4_t r", - "uint8x16_t a", - "int8x16_t b" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" }, "b": { - "register": "Vm.16B" + "register": "Vm.4S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vtrn1q_u64", + "arguments": [ + "uint64x2_t a", + "uint64x2_t b" + ], + "return_type": { + "value": "uint64x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2D" }, - "r": { - "register": "Vd.4S" + "b": { + "register": "Vm.2D" } }, "Architectures": [ @@ -115439,20 +313020,19 @@ ], "instructions": [ [ - "USDOT" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vusmmlaq_s32", + "name": "vtrn1q_u8", "arguments": [ - "int32x4_t r", "uint8x16_t a", - "int8x16_t b" + "uint8x16_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { @@ -115460,24 +313040,20 @@ }, "b": { "register": "Vm.16B" - }, - "r": { - "register": "Vd.4S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "USMMLA" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1_f16", + "name": "vtrn2_f16", "arguments": [ "float16x4_t a", "float16x4_t b" @@ -115498,13 +313074,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1_f32", + "name": "vtrn2_f32", "arguments": [ "float32x2_t a", "float32x2_t b" @@ -115525,13 +313101,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1_p16", + "name": "vtrn2_p16", "arguments": [ "poly16x4_t a", "poly16x4_t b" @@ -115552,13 +313128,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1_p8", + "name": "vtrn2_p8", "arguments": [ "poly8x8_t a", "poly8x8_t b" @@ -115579,13 +313155,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1_s16", + "name": "vtrn2_s16", "arguments": [ "int16x4_t a", "int16x4_t b" @@ -115606,13 +313182,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1_s32", + "name": "vtrn2_s32", "arguments": [ "int32x2_t a", "int32x2_t b" @@ -115633,13 +313209,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1_s8", + "name": "vtrn2_s8", "arguments": [ "int8x8_t a", "int8x8_t b" @@ -115660,13 +313236,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1_u16", + "name": "vtrn2_u16", "arguments": [ "uint16x4_t a", "uint16x4_t b" @@ -115687,13 +313263,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1_u32", + "name": "vtrn2_u32", "arguments": [ "uint32x2_t a", "uint32x2_t b" @@ -115714,13 +313290,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1_u8", + "name": "vtrn2_u8", "arguments": [ "uint8x8_t a", "uint8x8_t b" @@ -115741,13 +313317,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_f16", + "name": "vtrn2q_f16", "arguments": [ "float16x8_t a", "float16x8_t b" @@ -115768,13 +313344,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_f32", + "name": "vtrn2q_f32", "arguments": [ "float32x4_t a", "float32x4_t b" @@ -115795,13 +313371,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_f64", + "name": "vtrn2q_f64", "arguments": [ "float64x2_t a", "float64x2_t b" @@ -115822,13 +313398,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_p16", + "name": "vtrn2q_p16", "arguments": [ "poly16x8_t a", "poly16x8_t b" @@ -115849,13 +313425,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_p64", + "name": "vtrn2q_p64", "arguments": [ "poly64x2_t a", "poly64x2_t b" @@ -115876,13 +313452,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_p8", + "name": "vtrn2q_p8", "arguments": [ "poly8x16_t a", "poly8x16_t b" @@ -115903,13 +313479,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_s16", + "name": "vtrn2q_s16", "arguments": [ "int16x8_t a", "int16x8_t b" @@ -115930,13 +313506,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_s32", + "name": "vtrn2q_s32", "arguments": [ "int32x4_t a", "int32x4_t b" @@ -115957,13 +313533,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_s64", + "name": "vtrn2q_s64", "arguments": [ "int64x2_t a", "int64x2_t b" @@ -115984,13 +313560,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_s8", + "name": "vtrn2q_s8", "arguments": [ "int8x16_t a", "int8x16_t b" @@ -116011,13 +313587,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_u16", + "name": "vtrn2q_u16", "arguments": [ "uint16x8_t a", "uint16x8_t b" @@ -116038,13 +313614,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_u32", + "name": "vtrn2q_u32", "arguments": [ "uint32x4_t a", "uint32x4_t b" @@ -116065,13 +313641,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_u64", + "name": "vtrn2q_u64", "arguments": [ "uint64x2_t a", "uint64x2_t b" @@ -116092,13 +313668,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_u8", + "name": "vtrn2q_u8", "arguments": [ "uint8x16_t a", "uint8x16_t b" @@ -116119,19 +313695,19 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2_f16", + "name": "vtrn_f16", "arguments": [ "float16x4_t a", "float16x4_t b" ], "return_type": { - "value": "float16x4_t" + "value": "float16x4x2_t" }, "Arguments_Preparation": { "a": { @@ -116142,23 +313718,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2_f32", + "name": "vtrn_f32", "arguments": [ "float32x2_t a", "float32x2_t b" ], "return_type": { - "value": "float32x2_t" + "value": "float32x2x2_t" }, "Arguments_Preparation": { "a": { @@ -116169,23 +313748,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2_p16", + "name": "vtrn_p16", "arguments": [ "poly16x4_t a", "poly16x4_t b" ], "return_type": { - "value": "poly16x4_t" + "value": "poly16x4x2_t" }, "Arguments_Preparation": { "a": { @@ -116196,23 +313778,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2_p8", + "name": "vtrn_p8", "arguments": [ "poly8x8_t a", "poly8x8_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "poly8x8x2_t" }, "Arguments_Preparation": { "a": { @@ -116223,23 +313808,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2_s16", + "name": "vtrn_s16", "arguments": [ "int16x4_t a", "int16x4_t b" ], "return_type": { - "value": "int16x4_t" + "value": "int16x4x2_t" }, "Arguments_Preparation": { "a": { @@ -116250,23 +313838,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2_s32", + "name": "vtrn_s32", "arguments": [ "int32x2_t a", "int32x2_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int32x2x2_t" }, "Arguments_Preparation": { "a": { @@ -116277,23 +313868,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2_s8", + "name": "vtrn_s8", "arguments": [ "int8x8_t a", "int8x8_t b" ], "return_type": { - "value": "int8x8_t" + "value": "int8x8x2_t" }, "Arguments_Preparation": { "a": { @@ -116304,23 +313898,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2_u16", + "name": "vtrn_u16", "arguments": [ "uint16x4_t a", "uint16x4_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "uint16x4x2_t" }, "Arguments_Preparation": { "a": { @@ -116331,23 +313928,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2_u32", + "name": "vtrn_u32", "arguments": [ "uint32x2_t a", "uint32x2_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "uint32x2x2_t" }, "Arguments_Preparation": { "a": { @@ -116358,23 +313958,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2_u8", + "name": "vtrn_u8", "arguments": [ "uint8x8_t a", "uint8x8_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "uint8x8x2_t" }, "Arguments_Preparation": { "a": { @@ -116385,23 +313988,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_f16", + "name": "vtrnq_f16", "arguments": [ "float16x8_t a", "float16x8_t b" ], "return_type": { - "value": "float16x8_t" + "value": "float16x8x2_t" }, "Arguments_Preparation": { "a": { @@ -116412,23 +314018,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_f32", + "name": "vtrnq_f32", "arguments": [ "float32x4_t a", "float32x4_t b" ], "return_type": { - "value": "float32x4_t" + "value": "float32x4x2_t" }, "Arguments_Preparation": { "a": { @@ -116439,50 +314048,86 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_f64", + "name": "vtrnq_p16", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "poly16x8_t a", + "poly16x8_t b" ], "return_type": { - "value": "float64x2_t" + "value": "poly16x8x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.8H" }, "b": { - "register": "Vm.2D" + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_p16", + "name": "vtrnq_p8", "arguments": [ - "poly16x8_t a", - "poly16x8_t b" + "poly8x16_t a", + "poly8x16_t b" ], "return_type": { - "value": "poly16x8_t" + "value": "poly8x16x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "TRN1", + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vtrnq_s16", + "arguments": [ + "int16x8_t a", + "int16x8_t b" + ], + "return_type": { + "value": "int16x8x2_t" }, "Arguments_Preparation": { "a": { @@ -116493,50 +314138,56 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_p64", + "name": "vtrnq_s32", "arguments": [ - "poly64x2_t a", - "poly64x2_t b" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "poly64x2_t" + "value": "int32x4x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.4S" }, "b": { - "register": "Vm.2D" + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_p8", + "name": "vtrnq_s8", "arguments": [ - "poly8x16_t a", - "poly8x16_t b" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "int8x16x2_t" }, "Arguments_Preparation": { "a": { @@ -116547,23 +314198,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_s16", + "name": "vtrnq_u16", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int16x8_t" + "value": "uint16x8x2_t" }, "Arguments_Preparation": { "a": { @@ -116574,23 +314228,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_s32", + "name": "vtrnq_u32", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4x2_t" }, "Arguments_Preparation": { "a": { @@ -116601,165 +314258,178 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_s64", + "name": "vtrnq_u8", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint8x16x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.16B" }, "b": { - "register": "Vm.2D" + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_s8", + "name": "vtst_p64", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "poly64x1_t a", + "poly64x1_t b" ], "return_type": { - "value": "int8x16_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Dn" }, "b": { - "register": "Vm.16B" + "register": "Dm" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_u16", + "name": "vtst_p8", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "poly8x8_t a", + "poly8x8_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" }, "b": { - "register": "Vm.8H" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_u32", + "name": "vtst_s16", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.4H" }, "b": { - "register": "Vm.4S" + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_u64", + "name": "vtst_s32", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.2S" }, "b": { - "register": "Vm.2D" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_u8", + "name": "vtst_s64", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "int64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Dn" }, "b": { - "register": "Vm.16B" + "register": "Dm" } }, "Architectures": [ @@ -116767,19 +314437,48 @@ ], "instructions": [ [ - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp_f16", + "name": "vtst_s8", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "float16x4x2_t" + "value": "uint8x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "CMTST" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vtst_u16", + "arguments": [ + "uint16x4_t a", + "uint16x4_t b" + ], + "return_type": { + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { @@ -116796,20 +314495,19 @@ ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp_f32", + "name": "vtst_u32", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "float32x2x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { @@ -116826,50 +314524,46 @@ ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp_p16", + "name": "vtst_u64", "arguments": [ - "poly16x4_t a", - "poly16x4_t b" + "uint64x1_t a", + "uint64x1_t b" ], "return_type": { - "value": "poly16x4x2_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Dn" }, "b": { - "register": "Vm.4H" + "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp_p8", + "name": "vtst_u8", "arguments": [ - "poly8x8_t a", - "poly8x8_t b" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "poly8x8x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { @@ -116886,87 +314580,108 @@ ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp_s16", + "name": "vtstd_s64", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "int64_t a", + "int64_t b" ], "return_type": { - "value": "int16x4x2_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Dn" }, "b": { - "register": "Vm.4H" + "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp_s32", + "name": "vtstd_u64", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "uint64_t a", + "uint64_t b" ], "return_type": { - "value": "int32x2x2_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Dn" }, "b": { - "register": "Vm.2S" + "register": "Dm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMTST" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vtstq_p64", + "arguments": [ + "poly64x2_t a", + "poly64x2_t b" + ], + "return_type": { + "value": "uint64x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp_s8", + "name": "vtstq_p8", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "poly8x16_t a", + "poly8x16_t b" ], "return_type": { - "value": "int8x8x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.16B" }, "b": { - "register": "Vm.8B" + "register": "Vm.16B" } }, "Architectures": [ @@ -116976,27 +314691,26 @@ ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp_u16", + "name": "vtstq_s16", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "uint16x4x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.8H" }, "b": { - "register": "Vm.4H" + "register": "Vm.8H" } }, "Architectures": [ @@ -117006,27 +314720,26 @@ ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp_u32", + "name": "vtstq_s32", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "uint32x2x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4S" }, "b": { - "register": "Vm.2S" + "register": "Vm.4S" } }, "Architectures": [ @@ -117036,27 +314749,53 @@ ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp_u8", + "name": "vtstq_s64", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "uint8x8x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2D" }, "b": { - "register": "Vm.8B" + "register": "Vm.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMTST" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vtstq_s8", + "arguments": [ + "int8x16_t a", + "int8x16_t b" + ], + "return_type": { + "value": "uint8x16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" } }, "Architectures": [ @@ -117066,20 +314805,19 @@ ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzpq_f16", + "name": "vtstq_u16", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "float16x8x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { @@ -117096,20 +314834,19 @@ ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzpq_f32", + "name": "vtstq_u32", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "float32x4x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { @@ -117126,50 +314863,46 @@ ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzpq_p16", + "name": "vtstq_u64", "arguments": [ - "poly16x8_t a", - "poly16x8_t b" + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "poly16x8x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2D" }, "b": { - "register": "Vm.8H" + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzpq_p8", + "name": "vtstq_u8", "arguments": [ - "poly8x16_t a", - "poly8x16_t b" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "poly8x16x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { @@ -117186,170 +314919,524 @@ ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqadd_s16", + "arguments": [ + "int16x4_t a", + "uint16x4_t b" + ], + "return_type": { + "value": "int16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqadd_s32", + "arguments": [ + "int32x2_t a", + "uint32x2_t b" + ], + "return_type": { + "value": "int32x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.2S" + }, + "b": { + "register": "Vn.2S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqadd_s64", + "arguments": [ + "int64x1_t a", + "uint64x1_t b" + ], + "return_type": { + "value": "int64x1_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Dd" + }, + "b": { + "register": "Dn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqadd_s8", + "arguments": [ + "int8x8_t a", + "uint8x8_t b" + ], + "return_type": { + "value": "int8x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8B" + }, + "b": { + "register": "Vn.8B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqaddb_s8", + "arguments": [ + "int8_t a", + "uint8_t b" + ], + "return_type": { + "value": "int8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Bd" + }, + "b": { + "register": "Bn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqaddd_s64", + "arguments": [ + "int64_t a", + "uint64_t b" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Dd" + }, + "b": { + "register": "Dn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqaddh_s16", + "arguments": [ + "int16_t a", + "uint16_t b" + ], + "return_type": { + "value": "int16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hd" + }, + "b": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqaddq_s16", + "arguments": [ + "int16x8_t a", + "uint16x8_t b" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + }, + "b": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqaddq_s32", + "arguments": [ + "int32x4_t a", + "uint32x4_t b" + ], + "return_type": { + "value": "int32x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4S" + }, + "b": { + "register": "Vn.4S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqaddq_s64", + "arguments": [ + "int64x2_t a", + "uint64x2_t b" + ], + "return_type": { + "value": "int64x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.2D" + }, + "b": { + "register": "Vn.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqaddq_s8", + "arguments": [ + "int8x16_t a", + "uint8x16_t b" + ], + "return_type": { + "value": "int8x16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.16B" + }, + "b": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqadds_s32", + "arguments": [ + "int32_t a", + "uint32_t b" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Sd" + }, + "b": { + "register": "Sn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzpq_s16", + "name": "vusdot_lane_s32", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int32x2_t r", + "uint8x8_t a", + "int8x8_t b", + "const int lane" ], "return_type": { - "value": "int16x8x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" }, "b": { - "register": "Vm.8H" + "register": "Vm.4B" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "UZP1", - "UZP2" + "USDOT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzpq_s32", + "name": "vusdot_laneq_s32", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int32x2_t r", + "uint8x8_t a", + "int8x16_t b", + "const int lane" ], "return_type": { - "value": "int32x4x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.8B" }, "b": { - "register": "Vm.4S" + "register": "Vm.4B" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "UZP1", - "UZP2" + "USDOT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzpq_s8", + "name": "vusdot_s32", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "int32x2_t r", + "uint8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "int8x16x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8B" }, "b": { - "register": "Vm.16B" + "register": "Vm.8B" + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "UZP1", - "UZP2" + "USDOT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzpq_u16", + "name": "vusdotq_lane_s32", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "int32x4_t r", + "uint8x16_t a", + "int8x8_t b", + "const int lane" ], "return_type": { - "value": "uint16x8x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { - "register": "Vm.8H" + "register": "Vm.4B" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "r": { + "register": "Vd.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "UZP1", - "UZP2" + "USDOT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzpq_u32", + "name": "vusdotq_laneq_s32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "int32x4_t r", + "uint8x16_t a", + "int8x16_t b", + "const int lane" ], "return_type": { - "value": "uint32x4x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.16B" }, "b": { - "register": "Vm.4S" + "register": "Vm.4B" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "UZP1", - "UZP2" + "USDOT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzpq_u8", + "name": "vusdotq_s32", "arguments": [ + "int32x4_t r", "uint8x16_t a", - "uint8x16_t b" + "int8x16_t b" ], "return_type": { - "value": "uint8x16x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -117357,53 +315444,56 @@ }, "b": { "register": "Vm.16B" + }, + "r": { + "register": "Vd.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "UZP1", - "UZP2" + "USDOT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vxarq_u64", + "name": "vusmmlaq_s32", "arguments": [ - "uint64x2_t a", - "uint64x2_t b", - "const int imm6" + "int32x4_t r", + "uint8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.16B" }, - "b": {}, - "imm6": { - "minimum": 0, - "maximum": 63 + "b": { + "register": "Vm.16B" + }, + "r": { + "register": "Vd.4S" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "XAR" + "USMMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1_f16", + "name": "vuzp1_f16", "arguments": [ "float16x4_t a", "float16x4_t b" @@ -117424,13 +315514,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1_f32", + "name": "vuzp1_f32", "arguments": [ "float32x2_t a", "float32x2_t b" @@ -117451,13 +315541,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1_p16", + "name": "vuzp1_p16", "arguments": [ "poly16x4_t a", "poly16x4_t b" @@ -117478,13 +315568,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1_p8", + "name": "vuzp1_p8", "arguments": [ "poly8x8_t a", "poly8x8_t b" @@ -117505,13 +315595,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1_s16", + "name": "vuzp1_s16", "arguments": [ "int16x4_t a", "int16x4_t b" @@ -117532,13 +315622,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1_s32", + "name": "vuzp1_s32", "arguments": [ "int32x2_t a", "int32x2_t b" @@ -117559,13 +315649,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1_s8", + "name": "vuzp1_s8", "arguments": [ "int8x8_t a", "int8x8_t b" @@ -117586,13 +315676,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1_u16", + "name": "vuzp1_u16", "arguments": [ "uint16x4_t a", "uint16x4_t b" @@ -117613,13 +315703,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1_u32", + "name": "vuzp1_u32", "arguments": [ "uint32x2_t a", "uint32x2_t b" @@ -117640,13 +315730,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1_u8", + "name": "vuzp1_u8", "arguments": [ "uint8x8_t a", "uint8x8_t b" @@ -117667,13 +315757,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_f16", + "name": "vuzp1q_f16", "arguments": [ "float16x8_t a", "float16x8_t b" @@ -117694,13 +315784,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_f32", + "name": "vuzp1q_f32", "arguments": [ "float32x4_t a", "float32x4_t b" @@ -117721,13 +315811,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_f64", + "name": "vuzp1q_f64", "arguments": [ "float64x2_t a", "float64x2_t b" @@ -117748,13 +315838,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_p16", + "name": "vuzp1q_p16", "arguments": [ "poly16x8_t a", "poly16x8_t b" @@ -117775,13 +315865,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_p64", + "name": "vuzp1q_p64", "arguments": [ "poly64x2_t a", "poly64x2_t b" @@ -117802,13 +315892,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_p8", + "name": "vuzp1q_p8", "arguments": [ "poly8x16_t a", "poly8x16_t b" @@ -117829,13 +315919,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_s16", + "name": "vuzp1q_s16", "arguments": [ "int16x8_t a", "int16x8_t b" @@ -117856,13 +315946,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_s32", + "name": "vuzp1q_s32", "arguments": [ "int32x4_t a", "int32x4_t b" @@ -117883,13 +315973,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_s64", + "name": "vuzp1q_s64", "arguments": [ "int64x2_t a", "int64x2_t b" @@ -117910,13 +316000,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_s8", + "name": "vuzp1q_s8", "arguments": [ "int8x16_t a", "int8x16_t b" @@ -117937,13 +316027,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_u16", + "name": "vuzp1q_u16", "arguments": [ "uint16x8_t a", "uint16x8_t b" @@ -117964,13 +316054,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_u32", + "name": "vuzp1q_u32", "arguments": [ "uint32x4_t a", "uint32x4_t b" @@ -117991,13 +316081,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_u64", + "name": "vuzp1q_u64", "arguments": [ "uint64x2_t a", "uint64x2_t b" @@ -118018,13 +316108,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_u8", + "name": "vuzp1q_u8", "arguments": [ "uint8x16_t a", "uint8x16_t b" @@ -118045,13 +316135,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2_f16", + "name": "vuzp2_f16", "arguments": [ "float16x4_t a", "float16x4_t b" @@ -118072,13 +316162,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2_f32", + "name": "vuzp2_f32", "arguments": [ "float32x2_t a", "float32x2_t b" @@ -118099,13 +316189,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2_p16", + "name": "vuzp2_p16", "arguments": [ "poly16x4_t a", "poly16x4_t b" @@ -118126,13 +316216,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2_p8", + "name": "vuzp2_p8", "arguments": [ "poly8x8_t a", "poly8x8_t b" @@ -118153,13 +316243,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2_s16", + "name": "vuzp2_s16", "arguments": [ "int16x4_t a", "int16x4_t b" @@ -118180,13 +316270,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2_s32", + "name": "vuzp2_s32", "arguments": [ "int32x2_t a", "int32x2_t b" @@ -118207,13 +316297,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2_s8", + "name": "vuzp2_s8", "arguments": [ "int8x8_t a", "int8x8_t b" @@ -118234,13 +316324,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2_u16", + "name": "vuzp2_u16", "arguments": [ "uint16x4_t a", "uint16x4_t b" @@ -118261,13 +316351,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2_u32", + "name": "vuzp2_u32", "arguments": [ "uint32x2_t a", "uint32x2_t b" @@ -118288,13 +316378,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2_u8", + "name": "vuzp2_u8", "arguments": [ "uint8x8_t a", "uint8x8_t b" @@ -118315,13 +316405,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_f16", + "name": "vuzp2q_f16", "arguments": [ "float16x8_t a", "float16x8_t b" @@ -118342,13 +316432,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_f32", + "name": "vuzp2q_f32", "arguments": [ "float32x4_t a", "float32x4_t b" @@ -118369,13 +316459,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_f64", + "name": "vuzp2q_f64", "arguments": [ "float64x2_t a", "float64x2_t b" @@ -118396,13 +316486,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_p16", + "name": "vuzp2q_p16", "arguments": [ "poly16x8_t a", "poly16x8_t b" @@ -118423,13 +316513,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_p64", + "name": "vuzp2q_p64", "arguments": [ "poly64x2_t a", "poly64x2_t b" @@ -118450,13 +316540,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_p8", + "name": "vuzp2q_p8", "arguments": [ "poly8x16_t a", "poly8x16_t b" @@ -118477,13 +316567,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_s16", + "name": "vuzp2q_s16", "arguments": [ "int16x8_t a", "int16x8_t b" @@ -118504,13 +316594,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_s32", + "name": "vuzp2q_s32", "arguments": [ "int32x4_t a", "int32x4_t b" @@ -118531,13 +316621,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_s64", + "name": "vuzp2q_s64", "arguments": [ "int64x2_t a", "int64x2_t b" @@ -118558,13 +316648,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_s8", + "name": "vuzp2q_s8", "arguments": [ "int8x16_t a", "int8x16_t b" @@ -118585,13 +316675,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_u16", + "name": "vuzp2q_u16", "arguments": [ "uint16x8_t a", "uint16x8_t b" @@ -118612,13 +316702,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_u32", + "name": "vuzp2q_u32", "arguments": [ "uint32x4_t a", "uint32x4_t b" @@ -118639,13 +316729,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_u64", + "name": "vuzp2q_u64", "arguments": [ "uint64x2_t a", "uint64x2_t b" @@ -118666,13 +316756,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_u8", + "name": "vuzp2q_u8", "arguments": [ "uint8x16_t a", "uint8x16_t b" @@ -118693,13 +316783,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip_f16", + "name": "vuzp_f16", "arguments": [ "float16x4_t a", "float16x4_t b" @@ -118722,14 +316812,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip_f32", + "name": "vuzp_f32", "arguments": [ "float32x2_t a", "float32x2_t b" @@ -118752,14 +316842,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip_p16", + "name": "vuzp_p16", "arguments": [ "poly16x4_t a", "poly16x4_t b" @@ -118782,14 +316872,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip_p8", + "name": "vuzp_p8", "arguments": [ "poly8x8_t a", "poly8x8_t b" @@ -118812,14 +316902,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip_s16", + "name": "vuzp_s16", "arguments": [ "int16x4_t a", "int16x4_t b" @@ -118842,14 +316932,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip_s32", + "name": "vuzp_s32", "arguments": [ "int32x2_t a", "int32x2_t b" @@ -118872,14 +316962,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip_s8", + "name": "vuzp_s8", "arguments": [ "int8x8_t a", "int8x8_t b" @@ -118902,14 +316992,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip_u16", + "name": "vuzp_u16", "arguments": [ "uint16x4_t a", "uint16x4_t b" @@ -118932,14 +317022,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip_u32", + "name": "vuzp_u32", "arguments": [ "uint32x2_t a", "uint32x2_t b" @@ -118962,14 +317052,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip_u8", + "name": "vuzp_u8", "arguments": [ "uint8x8_t a", "uint8x8_t b" @@ -118992,14 +317082,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzipq_f16", + "name": "vuzpq_f16", "arguments": [ "float16x8_t a", "float16x8_t b" @@ -119022,14 +317112,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzipq_f32", + "name": "vuzpq_f32", "arguments": [ "float32x4_t a", "float32x4_t b" @@ -119052,14 +317142,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzipq_p16", + "name": "vuzpq_p16", "arguments": [ "poly16x8_t a", "poly16x8_t b" @@ -119082,14 +317172,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzipq_p8", + "name": "vuzpq_p8", "arguments": [ "poly8x16_t a", "poly8x16_t b" @@ -119112,14 +317202,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzipq_s16", + "name": "vuzpq_s16", "arguments": [ "int16x8_t a", "int16x8_t b" @@ -119142,14 +317232,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzipq_s32", + "name": "vuzpq_s32", "arguments": [ "int32x4_t a", "int32x4_t b" @@ -119172,14 +317262,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzipq_s8", + "name": "vuzpq_s8", "arguments": [ "int8x16_t a", "int8x16_t b" @@ -119202,14 +317292,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzipq_u16", + "name": "vuzpq_u16", "arguments": [ "uint16x8_t a", "uint16x8_t b" @@ -119232,14 +317322,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzipq_u32", + "name": "vuzpq_u32", "arguments": [ "uint32x4_t a", "uint32x4_t b" @@ -119262,14 +317352,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzipq_u8", + "name": "vuzpq_u8", "arguments": [ "uint8x16_t a", "uint8x16_t b" @@ -119292,14 +317382,46 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vamin_f16", + "name": "vxarq_u64", + "arguments": [ + "uint64x2_t a", + "uint64x2_t b", + "const int imm6" + ], + "return_type": { + "value": "uint64x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" + }, + "imm6": { + "minimum": 0, + "maximum": 63 + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "XAR" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1_f16", "arguments": [ "float16x4_t a", "float16x4_t b" @@ -119320,26 +317442,26 @@ ], "instructions": [ [ - "FAMIN" + "ZIP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vaminq_f16", + "name": "vzip1_f32", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "float16x8_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2S" }, "b": { - "register": "Vm.8H" + "register": "Vm.2S" } }, "Architectures": [ @@ -119347,19 +317469,100 @@ ], "instructions": [ [ - "FAMIN" + "ZIP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vamin_f32", + "name": "vzip1_p16", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "poly16x4_t a", + "poly16x4_t b" ], "return_type": { - "value": "float32x2_t" + "value": "poly16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1_p8", + "arguments": [ + "poly8x8_t a", + "poly8x8_t b" + ], + "return_type": { + "value": "poly8x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1_s16", + "arguments": [ + "int16x4_t a", + "int16x4_t b" + ], + "return_type": { + "value": "int16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1_s32", + "arguments": [ + "int32x2_t a", + "int32x2_t b" + ], + "return_type": { + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -119374,13 +317577,148 @@ ], "instructions": [ [ - "FAMIN" + "ZIP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vaminq_f32", + "name": "vzip1_s8", + "arguments": [ + "int8x8_t a", + "int8x8_t b" + ], + "return_type": { + "value": "int8x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1_u16", + "arguments": [ + "uint16x4_t a", + "uint16x4_t b" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1_u32", + "arguments": [ + "uint32x2_t a", + "uint32x2_t b" + ], + "return_type": { + "value": "uint32x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1_u8", + "arguments": [ + "uint8x8_t a", + "uint8x8_t b" + ], + "return_type": { + "value": "uint8x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1q_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1q_f32", "arguments": [ "float32x4_t a", "float32x4_t b" @@ -119401,13 +317739,13 @@ ], "instructions": [ [ - "FAMIN" + "ZIP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vaminq_f64", + "name": "vzip1q_f64", "arguments": [ "float64x2_t a", "float64x2_t b" @@ -119428,26 +317766,26 @@ ], "instructions": [ [ - "FAMIN" + "ZIP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vamax_f16", + "name": "vzip1q_p16", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "poly16x8_t a", + "poly16x8_t b" ], "return_type": { - "value": "float16x4_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.8H" }, "b": { - "register": "Vm.4H" + "register": "Vm.8H" } }, "Architectures": [ @@ -119455,19 +317793,73 @@ ], "instructions": [ [ - "FAMAX" + "ZIP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vamaxq_f16", + "name": "vzip1q_p64", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "poly64x2_t a", + "poly64x2_t b" ], "return_type": { - "value": "float16x8_t" + "value": "poly64x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1q_p8", + "arguments": [ + "poly8x16_t a", + "poly8x16_t b" + ], + "return_type": { + "value": "poly8x16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1q_s16", + "arguments": [ + "int16x8_t a", + "int16x8_t b" + ], + "return_type": { + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -119482,26 +317874,26 @@ ], "instructions": [ [ - "FAMAX" + "ZIP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vamax_f32", + "name": "vzip1q_s32", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "float32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4S" }, "b": { - "register": "Vm.2S" + "register": "Vm.4S" } }, "Architectures": [ @@ -119509,19 +317901,100 @@ ], "instructions": [ [ - "FAMAX" + "ZIP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vamaxq_f32", + "name": "vzip1q_s64", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "float32x4_t" + "value": "int64x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1q_s8", + "arguments": [ + "int8x16_t a", + "int8x16_t b" + ], + "return_type": { + "value": "int8x16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1q_u16", + "arguments": [ + "uint16x8_t a", + "uint16x8_t b" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1q_u32", + "arguments": [ + "uint32x4_t a", + "uint32x4_t b" + ], + "return_type": { + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { @@ -119536,26 +318009,107 @@ ], "instructions": [ [ - "FAMAX" + "ZIP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vamaxq_f64", + "name": "vzip1q_u64", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "uint64x2_t a", + "uint64x2_t b" + ], + "return_type": { + "value": "uint64x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1q_u8", + "arguments": [ + "uint8x16_t a", + "uint8x16_t b" + ], + "return_type": { + "value": "uint8x16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip2_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip2_f32", + "arguments": [ + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "float64x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.2S" }, "b": { - "register": "Vm.2D" + "register": "Vm.2S" } }, "Architectures": [ @@ -119563,34 +318117,26 @@ ], "instructions": [ [ - "FAMAX" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_lane_f16", + "name": "vzip2_p16", "arguments": [ - "float16x4_t a", - "uint8x8_t b", - "const int index" + "poly16x4_t a", + "poly16x4_t b" ], "return_type": { - "value": "float16x8_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4H" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.4H" } }, "Architectures": [ @@ -119598,34 +318144,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_lane_s16", + "name": "vzip2_p8", "arguments": [ - "int16x4_t a", - "uint8x8_t b", - "const int index" + "poly8x8_t a", + "poly8x8_t b" ], "return_type": { - "value": "int16x8_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.8B" } }, "Architectures": [ @@ -119633,34 +318171,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_lane_u16", + "name": "vzip2_s16", "arguments": [ - "uint16x4_t a", - "uint8x8_t b", - "const int index" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4H" }, "b": { - "register": "Vm" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.4H" } }, "Architectures": [ @@ -119668,34 +318198,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_lane_p16", + "name": "vzip2_s32", "arguments": [ - "poly16x4_t a", - "uint8x8_t b", - "const int index" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "poly16x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2S" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.2S" } }, "Architectures": [ @@ -119703,34 +318225,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_laneq_f16", + "name": "vzip2_s8", "arguments": [ - "float16x4_t a", - "uint8x16_t b", - "const int index" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "float16x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.8B" } }, "Architectures": [ @@ -119738,34 +318252,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_laneq_s16", + "name": "vzip2_u16", "arguments": [ - "int16x4_t a", - "uint8x16_t b", - "const int index" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "int16x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4H" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.4H" } }, "Architectures": [ @@ -119773,34 +318279,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_laneq_u16", + "name": "vzip2_u32", "arguments": [ - "uint16x4_t a", - "uint8x16_t b", - "const int index" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2S" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.2S" } }, "Architectures": [ @@ -119808,34 +318306,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_laneq_p16", + "name": "vzip2_u8", "arguments": [ - "poly16x4_t a", - "uint8x16_t b", - "const int index" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "poly16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.8B" } }, "Architectures": [ @@ -119843,17 +318333,16 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_lane_f16", + "name": "vzip2q_f16", "arguments": [ "float16x8_t a", - "uint8x8_t b", - "const int index" + "float16x8_t b" ], "return_type": { "value": "float16x8_t" @@ -119863,14 +318352,7 @@ "register": "Vn.8H" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.8H" } }, "Architectures": [ @@ -119878,34 +318360,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_lane_s16", + "name": "vzip2q_f32", "arguments": [ - "int16x8_t a", - "uint8x8_t b", - "const int index" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "int16x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4S" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.4S" } }, "Architectures": [ @@ -119913,34 +318387,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_lane_u16", + "name": "vzip2q_f64", "arguments": [ - "uint16x8_t a", - "uint8x8_t b", - "const int index" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2D" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.2D" } }, "Architectures": [ @@ -119948,17 +318414,16 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_lane_p16", + "name": "vzip2q_p16", "arguments": [ "poly16x8_t a", - "uint8x8_t b", - "const int index" + "poly16x8_t b" ], "return_type": { "value": "poly16x8_t" @@ -119968,14 +318433,7 @@ "register": "Vn.8H" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.8H" } }, "Architectures": [ @@ -119983,34 +318441,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_laneq_f16", + "name": "vzip2q_p64", "arguments": [ - "float16x8_t a", - "uint8x16_t b", - "const int index" + "poly64x2_t a", + "poly64x2_t b" ], "return_type": { - "value": "float16x8_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2D" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.2D" } }, "Architectures": [ @@ -120018,34 +318468,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_laneq_s16", + "name": "vzip2q_p8", "arguments": [ - "int16x8_t a", - "uint8x16_t b", - "const int index" + "poly8x16_t a", + "poly8x16_t b" ], "return_type": { - "value": "int16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.16B" } }, "Architectures": [ @@ -120053,34 +318495,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_laneq_u16", + "name": "vzip2q_s16", "arguments": [ - "uint16x8_t a", - "uint8x16_t b", - "const int index" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.8H" } }, "Architectures": [ @@ -120088,34 +318522,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_lane_u8", + "name": "vzip2q_s32", "arguments": [ - "uint8x8_t a", - "uint8x8_t b", - "const int lane" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.4S" } }, "Architectures": [ @@ -120123,34 +318549,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_lane_u8", + "name": "vzip2q_s64", "arguments": [ - "uint8x16_t a", - "uint8x8_t b", - "const int lane" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.2D" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.2D" } }, "Architectures": [ @@ -120158,17 +318576,16 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_lane_s8", + "name": "vzip2q_s8", "arguments": [ - "int8x8_t a", - "uint8x8_t b", - "const int lane" + "int8x16_t a", + "int8x16_t b" ], "return_type": { "value": "int8x16_t" @@ -120178,14 +318595,7 @@ "register": "Vn.16B" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.16B" } }, "Architectures": [ @@ -120193,34 +318603,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_lane_s8", + "name": "vzip2q_u16", "arguments": [ - "int8x16_t a", - "uint8x8_t b", - "const int lane" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int8x16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.8H" } }, "Architectures": [ @@ -120228,34 +318630,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_lane_p8", + "name": "vzip2q_u32", "arguments": [ - "poly8x8_t a", - "uint8x8_t b", - "const int lane" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.4S" } }, "Architectures": [ @@ -120263,34 +318657,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_lane_p8", + "name": "vzip2q_u64", "arguments": [ - "poly8x16_t a", - "uint8x8_t b", - "const int lane" + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.2D" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.2D" } }, "Architectures": [ @@ -120298,17 +318684,16 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_laneq_u8", + "name": "vzip2q_u8", "arguments": [ - "uint8x8_t a", - "uint8x16_t b", - "const int index" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { "value": "uint8x16_t" @@ -120318,14 +318703,7 @@ "register": "Vn.16B" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.16B" } }, "Architectures": [ @@ -120333,707 +318711,607 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_laneq_u8", + "name": "vzip_f16", "arguments": [ - "uint8x16_t a", - "uint8x16_t b", - "const int index" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "float16x4x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4H" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI2" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_laneq_s8", + "name": "vzip_f32", "arguments": [ - "int8x8_t a", - "uint8x16_t b", - "const int index" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "int8x16_t" + "value": "float32x2x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.2S" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI2" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_laneq_s8", + "name": "vzip_p16", "arguments": [ - "int8x16_t a", - "uint8x16_t b", - "const int index" + "poly16x4_t a", + "poly16x4_t b" ], "return_type": { - "value": "int8x16_t" + "value": "poly16x4x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4H" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI2" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_laneq_p8", + "name": "vzip_p8", "arguments": [ "poly8x8_t a", - "uint8x16_t b", - "const int index" + "poly8x8_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "poly8x8x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8B" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI2" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_laneq_p8", + "name": "vzip_s16", "arguments": [ - "poly8x16_t a", - "uint8x16_t b", - "const int index" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "int16x4x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4H" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI2" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_laneq_p16", + "name": "vzip_s32", "arguments": [ - "poly16x8_t a", - "uint8x16_t b", - "const int index" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "poly16x8_t" + "value": "int32x2x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2S" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI2" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_lane_u8", + "name": "vzip_s8", "arguments": [ - "uint8x16_t vn", - "uint8x8_t vm", - "const int index" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "int8x8x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn.16B" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 0 + "a": { + "register": "Vn.8B" }, - "r": { - "register": "Vd.16B" + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_laneq_u8", + "name": "vzip_u16", "arguments": [ - "uint8x16_t vn", - "uint8x16_t vm", - "const int index" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "uint16x4x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn.16B" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 + "a": { + "register": "Vn.4H" }, - "r": { - "register": "Vd.16B" + "b": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_lane_s8", + "name": "vzip_u32", "arguments": [ - "int8x16_t vn", - "uint8x8_t vm", - "const int index" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "int8x16_t" + "value": "uint32x2x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn.16B" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 0 + "a": { + "register": "Vn.2S" }, - "r": { - "register": "Vd.16B" + "b": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_laneq_s8", + "name": "vzip_u8", "arguments": [ - "int8x16_t vn", - "uint8x16_t vm", - "const int index" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "int8x16_t" + "value": "uint8x8x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn.16B" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 + "a": { + "register": "Vn.8B" }, - "r": { - "register": "Vd.16B" + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_lane_p8", + "name": "vzipq_f16", "arguments": [ - "poly8x16_t vn", - "uint8x8_t vm", - "const int index" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "float16x8x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn.16B" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 0 + "a": { + "register": "Vn.8H" }, - "r": { - "register": "Vd.16B" + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_laneq_p8", + "name": "vzipq_f32", "arguments": [ - "poly8x16_t vn", - "uint8x16_t vm", - "const int index" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "float32x4x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn.16B" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 + "a": { + "register": "Vn.4S" }, - "r": { - "register": "Vd.16B" + "b": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_lane_u16_x2", + "name": "vzipq_p16", "arguments": [ - "uint16x8x2_t vn", - "uint8x8_t vm", - "const int index" + "poly16x8_t a", + "poly16x8_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "poly16x8x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 + "a": { + "register": "Vn.8H" }, - "r": { - "register": "Vd.8H" + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_laneq_u16_x2", + "name": "vzipq_p8", "arguments": [ - "uint16x8x2_t vn", - "uint8x16_t vm", - "const int index" + "poly8x16_t a", + "poly8x16_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "poly8x16x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 + "a": { + "register": "Vn.16B" }, - "r": { - "register": "Vd.8H" + "b": { + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_lane_s16_x2", + "name": "vzipq_s16", "arguments": [ - "int16x8x2_t vn", - "uint8x8_t vm", - "const int index" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int16x8x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 + "a": { + "register": "Vn.8H" }, - "r": { - "register": "Vd.8H" + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_laneq_s16_x2", + "name": "vzipq_s32", "arguments": [ - "int16x8x2_t vn", - "uint8x16_t vm", - "const int index" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int32x4x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 + "a": { + "register": "Vn.4S" }, - "r": { - "register": "Vd.8H" + "b": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_lane_f16_x2", + "name": "vzipq_s8", "arguments": [ - "float16x8x2_t vn", - "uint8x8_t vm", - "const int index" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "float16x8_t" + "value": "int8x16x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 + "a": { + "register": "Vn.16B" }, - "r": { - "register": "Vd.8H" + "b": { + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_laneq_f16_x2", + "name": "vzipq_u16", "arguments": [ - "float16x8x2_t vn", - "uint8x16_t vm", - "const int index" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "float16x8_t" + "value": "uint16x8x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 + "a": { + "register": "Vn.8H" }, - "r": { - "register": "Vd.8H" + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_lane_p16_x2", + "name": "vzipq_u32", "arguments": [ - "poly16x8x2_t vn", - "uint8x8_t vm", - "const int index" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "poly16x8_t" + "value": "uint32x4x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 + "a": { + "register": "Vn.4S" }, - "r": { - "register": "Vd.8H" + "b": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_laneq_p16_x2", + "name": "vzipq_u8", "arguments": [ - "poly16x8x2_t vn", - "uint8x16_t vm", - "const int index" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "poly16x8_t" + "value": "uint8x16x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 + "a": { + "register": "Vn.16B" }, - "r": { - "register": "Vd.8H" + "b": { + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, diff --git a/library/stdarch/rust-version b/library/stdarch/rust-version index ccc0b55d4dc55..61a4b2d8c095f 100644 --- a/library/stdarch/rust-version +++ b/library/stdarch/rust-version @@ -1 +1 @@ -873d4682c7d285540b8f28bfe637006cef8918a6 +1e5ee356374211706221b71b6106d297a646ee57 diff --git a/library/stdarch/triagebot.toml b/library/stdarch/triagebot.toml index 621f39b2cbbf3..5b178f0cdf456 100644 --- a/library/stdarch/triagebot.toml +++ b/library/stdarch/triagebot.toml @@ -1,7 +1,7 @@ [assign] [assign.owners] -"*" = ["@Amanieu", "@folkertdev", "@sayantn"] +"*" = ["@Amanieu", "@folkertdev", "@sayantn", "@davidtwco", "@adamgemmell"] [ping.windows] message = """\ diff --git a/library/sysroot/Cargo.toml b/library/sysroot/Cargo.toml index b2069ef6a613b..10562389d62d3 100644 --- a/library/sysroot/Cargo.toml +++ b/library/sysroot/Cargo.toml @@ -32,4 +32,3 @@ optimize_for_size = ["std/optimize_for_size"] panic-unwind = ["std/panic-unwind"] profiler = ["dep:profiler_builtins"] windows_raw_dylib = ["std/windows_raw_dylib"] -llvm_enzyme = ["std/llvm_enzyme"] diff --git a/library/test/src/console.rs b/library/test/src/console.rs index 13b2b3d502c81..b1c5404a7160c 100644 --- a/library/test/src/console.rs +++ b/library/test/src/console.rs @@ -16,7 +16,7 @@ use super::helpers::metrics::MetricMap; use super::options::{Options, OutputFormat}; use super::test_result::TestResult; use super::time::{TestExecTime, TestSuiteExecTime}; -use super::types::{NamePadding, TestDesc, TestDescAndFn}; +use super::types::{NamePadding, TestDesc, TestDescAndFn, TestList}; use super::{filter_tests, run_tests, term}; /// Generic wrapper over stdout. @@ -170,7 +170,7 @@ impl ConsoleTestState { } // List the tests to console, and optionally to logfile. Filters are honored. -pub(crate) fn list_tests_console(opts: &TestOpts, tests: Vec) -> io::Result<()> { +pub(crate) fn list_tests_console(opts: &TestOpts, tests: TestList) -> io::Result<()> { let output = match term::stdout() { None => OutputLocation::Raw(io::stdout().lock()), Some(t) => OutputLocation::Pretty(t), @@ -186,7 +186,7 @@ pub(crate) fn list_tests_console(opts: &TestOpts, tests: Vec) -> let mut st = ConsoleTestDiscoveryState::new(opts)?; out.write_discovery_start()?; - for test in filter_tests(opts, tests).into_iter() { + for test in filter_tests(opts, tests) { use crate::TestFn::*; let TestDescAndFn { desc, testfn } = test; @@ -307,8 +307,9 @@ pub(crate) fn get_formatter(opts: &TestOpts, max_name_len: usize) -> Box) -> io::Result { +pub fn run_tests_console(opts: &TestOpts, tests: TestList) -> io::Result { let max_name_len = tests + .tests .iter() .max_by_key(|t| len_if_padded(t)) .map(|t| t.desc.name.as_slice().len()) diff --git a/library/test/src/formatters/junit.rs b/library/test/src/formatters/junit.rs index 74d99e0f1270e..2772222a05c9a 100644 --- a/library/test/src/formatters/junit.rs +++ b/library/test/src/formatters/junit.rs @@ -1,5 +1,5 @@ +use std::io; use std::io::prelude::Write; -use std::io::{self}; use std::time::Duration; use super::OutputFormatter; diff --git a/library/test/src/lib.rs b/library/test/src/lib.rs index d554807bbde70..e4280520bd8ba 100644 --- a/library/test/src/lib.rs +++ b/library/test/src/lib.rs @@ -24,7 +24,7 @@ #![feature(staged_api)] #![feature(process_exitcode_internals)] #![feature(panic_can_unwind)] -#![feature(test)] +#![cfg_attr(test, feature(test))] #![feature(thread_spawn_hook)] #![allow(internal_features)] #![warn(rustdoc::unescaped_backticks)] @@ -49,7 +49,7 @@ pub mod test { pub use crate::time::{TestExecTime, TestTimeOptions}; pub use crate::types::{ DynTestFn, DynTestName, StaticBenchFn, StaticTestFn, StaticTestName, TestDesc, - TestDescAndFn, TestId, TestName, TestType, + TestDescAndFn, TestId, TestList, TestListOrder, TestName, TestType, }; pub use crate::{assert_test_result, filter_tests, run_test, test_main, test_main_static}; } @@ -106,6 +106,16 @@ pub fn test_main_with_exit_callback( tests: Vec, options: Option, exit_callback: F, +) { + let tests = TestList::new(tests, TestListOrder::Unsorted); + test_main_inner(args, tests, options, exit_callback) +} + +fn test_main_inner( + args: &[String], + tests: TestList, + options: Option, + exit_callback: F, ) { let mut opts = match cli::parse_opts(args) { Some(Ok(o)) => o, @@ -180,7 +190,9 @@ pub fn test_main_with_exit_callback( pub fn test_main_static(tests: &[&TestDescAndFn]) { let args = env::args().collect::>(); let owned_tests: Vec<_> = tests.iter().map(make_owned_test).collect(); - test_main(&args, owned_tests, None) + // Tests are sorted by name at compile time by mk_tests_slice. + let tests = TestList::new(owned_tests, TestListOrder::Sorted); + test_main_inner(&args, tests, None, || {}) } /// A variant optimized for invocation with a static test vector. @@ -195,6 +207,14 @@ pub fn test_main_static_abort(tests: &[&TestDescAndFn]) { // If we're being run in SpawnedSecondary mode, run the test here. run_test // will then exit the process. if let Ok(name) = env::var(SECONDARY_TEST_INVOKER_VAR) { + // SAFETY: Technically, this is a racy access that we probably shouldn't do? + // In practice, this is completely fine as long as the test harness is made of Rust, + // as std will synchronize the racy accesses that occur when they happen through std::env. + // Any unsoundness can only be exposed in practice if e.g. C code also takes an interest + // in these variables. + // + // If we ever grow an actual story for libtest and start documenting custom harness reqs, + // we should either fix this being racy or say "write it in Rust, please". unsafe { env::remove_var(SECONDARY_TEST_INVOKER_VAR); } @@ -202,6 +222,7 @@ pub fn test_main_static_abort(tests: &[&TestDescAndFn]) { // Convert benchmarks to tests if we're not benchmarking. let mut tests = tests.iter().map(make_owned_test).collect::>(); if env::var(SECONDARY_TEST_BENCH_BENCHMARKS_VAR).is_ok() { + // SAFETY: Same as for SECONDARY_TEST_INVOKER_VAR unsafe { env::remove_var(SECONDARY_TEST_BENCH_BENCHMARKS_VAR); } @@ -229,7 +250,9 @@ pub fn test_main_static_abort(tests: &[&TestDescAndFn]) { let args = env::args().collect::>(); let owned_tests: Vec<_> = tests.iter().map(make_owned_test).collect(); - test_main(&args, owned_tests, Some(Options::new().panic_abort(true))) + // Tests are sorted by name at compile time by mk_tests_slice. + let tests = TestList::new(owned_tests, TestListOrder::Sorted); + test_main_inner(&args, tests, Some(Options::new().panic_abort(true)), || {}) } /// Clones static values for putting into a dynamic vector, which test_main() @@ -298,7 +321,7 @@ impl FilteredTests { pub fn run_tests( opts: &TestOpts, - tests: Vec, + tests: TestList, mut notify_about_test_event: F, ) -> io::Result<()> where @@ -334,7 +357,7 @@ where timeout: Instant, } - let tests_len = tests.len(); + let tests_len = tests.tests.len(); let mut filtered = FilteredTests { tests: Vec::new(), benches: Vec::new(), next_id: 0 }; @@ -512,25 +535,48 @@ where Ok(()) } -pub fn filter_tests(opts: &TestOpts, tests: Vec) -> Vec { +pub fn filter_tests(opts: &TestOpts, tests: TestList) -> Vec { + let TestList { tests, order } = tests; let mut filtered = tests; - let matches_filter = |test: &TestDescAndFn, filter: &str| { - let test_name = test.desc.name.as_slice(); - - match opts.filter_exact { - true => test_name == filter, - false => test_name.contains(filter), - } - }; - // Remove tests that don't match the test filter + // Remove tests that don't match the test filter. if !opts.filters.is_empty() { - filtered.retain(|test| opts.filters.iter().any(|filter| matches_filter(test, filter))); + if opts.filter_exact && order == TestListOrder::Sorted { + // Let's say that `f` is the number of filters and `n` is the number + // of tests. + // + // The test array is sorted by name (guaranteed by the caller via + // TestListOrder::Sorted), so use binary search for O(f log n) + // exact-match lookups instead of an O(n) linear scan. + // + // This is important for Miri, where the interpreted execution makes + // the linear scan very expensive. + filtered = filter_exact_match(filtered, &opts.filters); + } else { + filtered.retain(|test| { + let test_name = test.desc.name.as_slice(); + opts.filters.iter().any(|filter| { + if opts.filter_exact { + test_name == filter.as_str() + } else { + test_name.contains(filter.as_str()) + } + }) + }); + } } // Skip tests that match any of the skip filters + // + // After exact positive filtering above, the filtered set is small, so a + // linear scan is acceptable even under Miri. if !opts.skip.is_empty() { - filtered.retain(|test| !opts.skip.iter().any(|sf| matches_filter(test, sf))); + filtered.retain(|test| { + let name = test.desc.name.as_slice(); + !opts.skip.iter().any(|sf| { + if opts.filter_exact { name == sf.as_str() } else { name.contains(sf.as_str()) } + }) + }); } // Excludes #[should_panic] tests @@ -553,6 +599,30 @@ pub fn filter_tests(opts: &TestOpts, tests: Vec) -> Vec, filters: &[String]) -> Vec { + // Binary search for each filter in the sorted test list. + let mut indexes: Vec = filters + .iter() + .filter_map(|f| tests.binary_search_by(|t| t.desc.name.as_slice().cmp(f.as_str())).ok()) + .collect(); + indexes.sort_unstable(); + indexes.dedup(); + + // Extract matching tests. Process indexes in descending order so that + // swap_remove (which replaces the removed element with the last) does not + // invalidate indexes we haven't visited yet. + let mut result = Vec::with_capacity(indexes.len()); + for &idx in indexes.iter().rev() { + result.push(tests.swap_remove(idx)); + } + // Reverse to restore the original sorted order, since we extracted the + // matching tests in descending index order. + result.reverse(); + result +} + pub fn convert_benchmarks_to_tests(tests: Vec) -> Vec { // convert benchmarks to tests, if we're not benchmarking them tests diff --git a/library/test/src/term.rs b/library/test/src/term.rs index d9880a776406d..1e4c7bc879cf7 100644 --- a/library/test/src/term.rs +++ b/library/test/src/term.rs @@ -12,8 +12,8 @@ #![deny(missing_docs)] +use std::io; use std::io::prelude::*; -use std::io::{self}; pub(crate) use terminfo::TerminfoTerminal; #[cfg(windows)] diff --git a/library/test/src/tests.rs b/library/test/src/tests.rs index d986bd74f772b..b25462cce1f99 100644 --- a/library/test/src/tests.rs +++ b/library/test/src/tests.rs @@ -477,7 +477,7 @@ fn filter_for_ignored_option() { opts.run_tests = true; opts.run_ignored = RunIgnored::Only; - let tests = one_ignored_one_unignored_test(); + let tests = TestList::new(one_ignored_one_unignored_test(), TestListOrder::Unsorted); let filtered = filter_tests(&opts, tests); assert_eq!(filtered.len(), 1); @@ -494,7 +494,7 @@ fn run_include_ignored_option() { opts.run_tests = true; opts.run_ignored = RunIgnored::Yes; - let tests = one_ignored_one_unignored_test(); + let tests = TestList::new(one_ignored_one_unignored_test(), TestListOrder::Unsorted); let filtered = filter_tests(&opts, tests); assert_eq!(filtered.len(), 2); @@ -527,7 +527,7 @@ fn exclude_should_panic_option() { testfn: DynTestFn(Box::new(move || Ok(()))), }); - let filtered = filter_tests(&opts, tests); + let filtered = filter_tests(&opts, TestList::new(tests, TestListOrder::Unsorted)); assert_eq!(filtered.len(), 2); assert!(filtered.iter().all(|test| test.desc.should_panic == ShouldPanic::No)); @@ -535,8 +535,8 @@ fn exclude_should_panic_option() { #[test] fn exact_filter_match() { - fn tests() -> Vec { - ["base", "base::test", "base::test1", "base::test2"] + fn tests() -> TestList { + let tests = ["base", "base::test", "base::test1", "base::test2"] .into_iter() .map(|name| TestDescAndFn { desc: TestDesc { @@ -555,7 +555,8 @@ fn exact_filter_match() { }, testfn: DynTestFn(Box::new(move || Ok(()))), }) - .collect() + .collect(); + TestList::new(tests, TestListOrder::Sorted) } let substr = @@ -908,7 +909,8 @@ fn test_dyn_bench_returning_err_fails_when_run_as_test() { } Ok(()) }; - run_tests(&TestOpts { run_tests: true, ..TestOpts::new() }, vec![desc], notify).unwrap(); + let tests = TestList::new(vec![desc], TestListOrder::Unsorted); + run_tests(&TestOpts { run_tests: true, ..TestOpts::new() }, tests, notify).unwrap(); let result = rx.recv().unwrap().result; assert_eq!(result, TrFailed); } diff --git a/library/test/src/types.rs b/library/test/src/types.rs index 802cab989c6a9..14c81bc2d1cf1 100644 --- a/library/test/src/types.rs +++ b/library/test/src/types.rs @@ -284,3 +284,30 @@ impl TestDescAndFn { } } } + +/// Whether a [`TestList`]'s tests are known to be sorted by name. +/// +/// When tests are sorted, `filter_tests` can use binary search for `--exact` +/// matches instead of a linear scan. +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TestListOrder { + /// Tests are sorted by name. This is guaranteed for tests generated by + /// `rustc --test` (see `mk_tests_slice` in + /// `compiler/rustc_builtin_macros/src/test_harness.rs`). + Sorted, + /// Test order is unknown; binary search must not be used. + Unsorted, +} + +/// A list of tests, tagged with whether they are sorted by name. +#[derive(Debug)] +pub struct TestList { + pub tests: Vec, + pub order: TestListOrder, +} + +impl TestList { + pub fn new(tests: Vec, order: TestListOrder) -> Self { + Self { tests, order } + } +} diff --git a/library/unwind/Cargo.toml b/library/unwind/Cargo.toml index f02744a107082..628b9d5e8c3ec 100644 --- a/library/unwind/Cargo.toml +++ b/library/unwind/Cargo.toml @@ -4,9 +4,6 @@ version = "0.0.0" license = "MIT OR Apache-2.0" repository = "https://github.com/rust-lang/rust.git" edition = "2024" -include = [ - '/libunwind/*', -] [lib] test = false @@ -35,4 +32,4 @@ system-llvm-libunwind = [] [lints.rust.unexpected_cfgs] level = "warn" -check-cfg = ['cfg(emscripten_wasm_eh)', 'cfg(target_arch, values("loongarch32"))'] +check-cfg = ['cfg(target_arch, values("loongarch32"))'] diff --git a/library/unwind/src/lib.rs b/library/unwind/src/lib.rs index cff2aa7b08b93..a64049a440d58 100644 --- a/library/unwind/src/lib.rs +++ b/library/unwind/src/lib.rs @@ -1,15 +1,13 @@ #![no_std] #![unstable(feature = "panic_unwind", issue = "32837")] -#![feature(cfg_emscripten_wasm_eh)] -#![feature(cfg_select)] #![feature(link_cfg)] #![feature(staged_api)] -#![cfg_attr(not(target_env = "msvc"), feature(libc))] #![cfg_attr( - all(target_family = "wasm", any(not(target_os = "emscripten"), emscripten_wasm_eh)), - feature(link_llvm_intrinsics, simd_wasm64) + target_family = "wasm", + feature(link_llvm_intrinsics, simd_wasm64, asm_experimental_arch) )] #![allow(internal_features)] +#![allow(unused_features)] #![deny(unsafe_op_in_unsafe_fn)] // Force libc to be included even if unused. This is required by many platforms. @@ -20,12 +18,7 @@ cfg_select! { target_env = "msvc" => { // Windows MSVC no extra unwinder support needed } - any( - target_os = "l4re", - target_os = "none", - target_os = "espidf", - target_os = "nuttx", - ) => { + any(target_os = "none", target_os = "espidf", target_os = "nuttx") => { // These "unix" family members do not have unwinder. } any( @@ -33,16 +26,17 @@ cfg_select! { windows, target_os = "psp", target_os = "solid_asp3", + target_os = "l4re", all(target_vendor = "fortanix", target_env = "sgx"), + all(target_os = "wasi", panic = "unwind"), + target_os = "xous", ) => { mod libunwind; pub use libunwind::*; - } - target_os = "xous" => { - mod unwinding; - pub use unwinding::*; + mod types; } target_family = "wasm" => { + mod types; mod wasm; pub use wasm::*; } @@ -50,6 +44,7 @@ cfg_select! { // no unwinder on the system! // - os=none ("bare metal" targets) // - os=hermit + // - os=motor // - os=uefi // - os=cuda // - nvptx64-nvidia-cuda @@ -57,23 +52,45 @@ cfg_select! { } } -#[cfg(target_env = "musl")] +// `target_abi = "pauthtest"` is currently only used by the Linux/musl +// `aarch64-unknown-linux-pauthtest` target. That target only supports unwinding +// via libunwind. +#[cfg(target_abi = "pauthtest")] +#[link(name = "unwind")] +unsafe extern "C" {} + +#[cfg(all(target_env = "musl", not(target_abi = "pauthtest")))] cfg_select! { all(feature = "llvm-libunwind", feature = "system-llvm-libunwind") => { - compile_error!("`llvm-libunwind` and `system-llvm-libunwind` cannot be enabled at the same time"); + compile_error!( + "`llvm-libunwind` and `system-llvm-libunwind` cannot be enabled at the same time" + ); } feature = "llvm-libunwind" => { #[link(name = "unwind", kind = "static", modifiers = "-bundle")] unsafe extern "C" {} } feature = "system-llvm-libunwind" => { - #[link(name = "unwind", kind = "static", modifiers = "-bundle", cfg(target_feature = "crt-static"))] + #[link( + name = "unwind", + kind = "static", + modifiers = "-bundle", + cfg(target_feature = "crt-static") + )] #[link(name = "unwind", cfg(not(target_feature = "crt-static")))] unsafe extern "C" {} } _ => { - #[link(name = "unwind", kind = "static", modifiers = "-bundle", cfg(target_feature = "crt-static"))] - #[link(name = "gcc_s", cfg(all(not(target_feature = "crt-static"), not(target_arch = "hexagon"))))] + #[link( + name = "unwind", + kind = "static", + modifiers = "-bundle", + cfg(target_feature = "crt-static") + )] + #[link( + name = "gcc_s", + cfg(all(not(target_feature = "crt-static"), not(target_arch = "hexagon"))) + )] unsafe extern "C" {} } } @@ -86,7 +103,12 @@ cfg_select! { unsafe extern "C" {} } feature = "system-llvm-libunwind" => { - #[link(name = "unwind", kind = "static", modifiers = "-bundle", cfg(target_feature = "crt-static"))] + #[link( + name = "unwind", + kind = "static", + modifiers = "-bundle", + cfg(target_feature = "crt-static") + )] #[link(name = "unwind", cfg(not(target_feature = "crt-static")))] unsafe extern "C" {} } @@ -100,14 +122,21 @@ cfg_select! { #[cfg(target_env = "ohos")] cfg_select! { all(feature = "llvm-libunwind", feature = "system-llvm-libunwind") => { - compile_error!("`llvm-libunwind` and `system-llvm-libunwind` cannot be enabled at the same time"); + compile_error!( + "`llvm-libunwind` and `system-llvm-libunwind` cannot be enabled at the same time" + ); } feature = "llvm-libunwind" => { #[link(name = "unwind", kind = "static", modifiers = "-bundle")] unsafe extern "C" {} } _ => { - #[link(name = "unwind", kind = "static", modifiers = "-bundle", cfg(target_feature = "crt-static"))] + #[link( + name = "unwind", + kind = "static", + modifiers = "-bundle", + cfg(target_feature = "crt-static") + )] #[link(name = "unwind", cfg(not(target_feature = "crt-static")))] unsafe extern "C" {} } @@ -119,7 +148,12 @@ cfg_select! { compile_error!("`llvm-libunwind` is not supported for Android targets"); } _ => { - #[link(name = "unwind", kind = "static", modifiers = "-bundle", cfg(target_feature = "crt-static"))] + #[link( + name = "unwind", + kind = "static", + modifiers = "-bundle", + cfg(target_feature = "crt-static") + )] #[link(name = "unwind", cfg(not(target_feature = "crt-static")))] unsafe extern "C" {} } @@ -194,7 +228,7 @@ unsafe extern "C" {} #[link(name = "unwind")] unsafe extern "C" {} -#[cfg(target_os = "nto")] +#[cfg(any(target_os = "nto", target_os = "qnx"))] cfg_select! { target_env = "nto70" => { #[link(name = "gcc")] @@ -210,6 +244,10 @@ cfg_select! { #[link(name = "gcc_s")] unsafe extern "C" {} +#[cfg(all(target_os = "wasi", panic = "unwind"))] +#[link(name = "unwind")] +unsafe extern "C" {} + #[cfg(all(target_os = "windows", target_env = "gnu", target_abi = "llvm"))] #[link(name = "unwind", kind = "static", modifiers = "-bundle", cfg(target_feature = "crt-static"))] #[link(name = "unwind", cfg(not(target_feature = "crt-static")))] diff --git a/library/unwind/src/libunwind.rs b/library/unwind/src/libunwind.rs index 091efa9c51292..4dc3cb393181c 100644 --- a/library/unwind/src/libunwind.rs +++ b/library/unwind/src/libunwind.rs @@ -2,100 +2,18 @@ use core::ffi::{c_int, c_void}; -#[repr(C)] -#[derive(Debug, Copy, Clone, PartialEq)] -pub enum _Unwind_Reason_Code { - _URC_NO_REASON = 0, - _URC_FOREIGN_EXCEPTION_CAUGHT = 1, - _URC_FATAL_PHASE2_ERROR = 2, - _URC_FATAL_PHASE1_ERROR = 3, - _URC_NORMAL_STOP = 4, - _URC_END_OF_STACK = 5, - _URC_HANDLER_FOUND = 6, - _URC_INSTALL_CONTEXT = 7, - _URC_CONTINUE_UNWIND = 8, - _URC_FAILURE = 9, // used only by ARM EHABI -} -pub use _Unwind_Reason_Code::*; - -pub type _Unwind_Exception_Class = u64; -pub type _Unwind_Word = *const u8; -pub type _Unwind_Ptr = *const u8; -pub type _Unwind_Trace_Fn = - extern "C" fn(ctx: *mut _Unwind_Context, arg: *mut c_void) -> _Unwind_Reason_Code; - -#[cfg(target_arch = "x86")] -pub const unwinder_private_data_size: usize = 5; - -#[cfg(all(target_arch = "x86_64", not(any(target_os = "windows", target_os = "cygwin"))))] -pub const unwinder_private_data_size: usize = 2; - -#[cfg(all(target_arch = "x86_64", any(target_os = "windows", target_os = "cygwin")))] -pub const unwinder_private_data_size: usize = 6; - -#[cfg(all(target_arch = "arm", not(target_vendor = "apple")))] -pub const unwinder_private_data_size: usize = 20; - -#[cfg(all(target_arch = "arm", target_vendor = "apple"))] -pub const unwinder_private_data_size: usize = 5; - -#[cfg(all(target_arch = "aarch64", target_pointer_width = "64", not(target_os = "windows")))] -pub const unwinder_private_data_size: usize = 2; - -#[cfg(all(target_arch = "aarch64", target_pointer_width = "64", target_os = "windows"))] -pub const unwinder_private_data_size: usize = 6; - -#[cfg(all(target_arch = "aarch64", target_pointer_width = "32"))] -pub const unwinder_private_data_size: usize = 5; - -#[cfg(target_arch = "m68k")] -pub const unwinder_private_data_size: usize = 2; - -#[cfg(any(target_arch = "mips", target_arch = "mips32r6"))] -pub const unwinder_private_data_size: usize = 2; - -#[cfg(target_arch = "csky")] -pub const unwinder_private_data_size: usize = 2; - -#[cfg(any(target_arch = "mips64", target_arch = "mips64r6"))] -pub const unwinder_private_data_size: usize = 2; +// Use the unwinding crate as unwinder on Xous +#[cfg(target_os = "xous")] +pub use unwinding::custom_eh_frame_finder::{ + EhFrameFinder, FrameInfo, FrameInfoKind, set_custom_eh_frame_finder, +}; -#[cfg(any(target_arch = "powerpc", target_arch = "powerpc64"))] -pub const unwinder_private_data_size: usize = 2; +pub use crate::types::*; -#[cfg(target_arch = "s390x")] -pub const unwinder_private_data_size: usize = 2; - -#[cfg(any(target_arch = "sparc", target_arch = "sparc64"))] -pub const unwinder_private_data_size: usize = 2; - -#[cfg(any(target_arch = "riscv64", target_arch = "riscv32"))] -pub const unwinder_private_data_size: usize = 2; - -#[cfg(all(target_arch = "wasm32", target_os = "emscripten"))] -pub const unwinder_private_data_size: usize = 20; - -#[cfg(all(target_arch = "wasm32", target_os = "linux"))] -pub const unwinder_private_data_size: usize = 2; - -#[cfg(target_arch = "hexagon")] -pub const unwinder_private_data_size: usize = 5; - -#[cfg(any(target_arch = "loongarch32", target_arch = "loongarch64"))] -pub const unwinder_private_data_size: usize = 2; - -#[repr(C)] -pub struct _Unwind_Exception { - pub exception_class: _Unwind_Exception_Class, - pub exception_cleanup: _Unwind_Exception_Cleanup_Fn, - pub private: [_Unwind_Word; unwinder_private_data_size], -} +pub type _Unwind_Ptr = *const u8; pub enum _Unwind_Context {} -pub type _Unwind_Exception_Cleanup_Fn = - Option; - // FIXME: The `#[link]` attributes on `extern "C"` block marks those symbols declared in // the block are reexported in dylib build of std. This is needed when build rustc with // feature `llvm-libunwind`, as no other cdylib will provided those _Unwind_* symbols. @@ -105,10 +23,7 @@ pub type _Unwind_Exception_Cleanup_Fn = // rustc_codegen_ssa::src::back::symbol_export, rustc_middle::middle::exported_symbols // and RFC 2841 #[cfg_attr( - all( - feature = "llvm-libunwind", - any(target_os = "fuchsia", target_os = "linux", target_os = "xous") - ), + all(feature = "llvm-libunwind", any(target_os = "fuchsia", target_os = "linux")), link(name = "unwind", kind = "static", modifiers = "-bundle") )] unsafe extern "C-unwind" { @@ -131,25 +46,24 @@ cfg_select! { pub type _Unwind_Action = c_int; pub const _UA_SEARCH_PHASE: c_int = 1; - pub const _UA_CLEANUP_PHASE: c_int = 2; - pub const _UA_HANDLER_FRAME: c_int = 4; + //pub const _UA_CLEANUP_PHASE: c_int = 2; + //pub const _UA_HANDLER_FRAME: c_int = 4; pub const _UA_FORCE_UNWIND: c_int = 8; - pub const _UA_END_OF_STACK: c_int = 16; + //pub const _UA_END_OF_STACK: c_int = 16; #[cfg_attr( - all(feature = "llvm-libunwind", any(target_os = "fuchsia", target_os = "linux", target_os = "xous")), + all(feature = "llvm-libunwind", any(target_os = "fuchsia", target_os = "linux")), link(name = "unwind", kind = "static", modifiers = "-bundle") )] unsafe extern "C" { pub fn _Unwind_GetGR(ctx: *mut _Unwind_Context, reg_index: c_int) -> _Unwind_Word; pub fn _Unwind_SetGR(ctx: *mut _Unwind_Context, reg_index: c_int, value: _Unwind_Word); - pub fn _Unwind_GetIP(ctx: *mut _Unwind_Context) -> _Unwind_Word; pub fn _Unwind_SetIP(ctx: *mut _Unwind_Context, value: _Unwind_Word); - pub fn _Unwind_GetIPInfo(ctx: *mut _Unwind_Context, ip_before_insn: *mut c_int) - -> _Unwind_Word; - pub fn _Unwind_FindEnclosingFunction(pc: *mut c_void) -> *mut c_void; + pub fn _Unwind_GetIPInfo( + ctx: *mut _Unwind_Context, + ip_before_insn: *mut c_int, + ) -> _Unwind_Word; } - } _ => { // ARM EHABI @@ -196,102 +110,91 @@ cfg_select! { pub const UNWIND_IP_REG: c_int = 15; #[cfg_attr( - all(feature = "llvm-libunwind", any(target_os = "fuchsia", target_os = "linux", target_os = "xous")), + all(feature = "llvm-libunwind", any(target_os = "fuchsia", target_os = "linux")), link(name = "unwind", kind = "static", modifiers = "-bundle") )] unsafe extern "C" { - fn _Unwind_VRS_Get(ctx: *mut _Unwind_Context, - regclass: _Unwind_VRS_RegClass, - regno: _Unwind_Word, - repr: _Unwind_VRS_DataRepresentation, - data: *mut c_void) - -> _Unwind_VRS_Result; - - fn _Unwind_VRS_Set(ctx: *mut _Unwind_Context, - regclass: _Unwind_VRS_RegClass, - regno: _Unwind_Word, - repr: _Unwind_VRS_DataRepresentation, - data: *mut c_void) - -> _Unwind_VRS_Result; + fn _Unwind_VRS_Get( + ctx: *mut _Unwind_Context, + regclass: _Unwind_VRS_RegClass, + regno: _Unwind_Word, + repr: _Unwind_VRS_DataRepresentation, + data: *mut c_void, + ) -> _Unwind_VRS_Result; + + fn _Unwind_VRS_Set( + ctx: *mut _Unwind_Context, + regclass: _Unwind_VRS_RegClass, + regno: _Unwind_Word, + repr: _Unwind_VRS_DataRepresentation, + data: *mut c_void, + ) -> _Unwind_VRS_Result; } // On Android or ARM/Linux, these are implemented as macros: pub unsafe fn _Unwind_GetGR(ctx: *mut _Unwind_Context, reg_index: c_int) -> _Unwind_Word { let mut val: _Unwind_Word = core::ptr::null(); - unsafe { _Unwind_VRS_Get(ctx, _UVRSC_CORE, reg_index as _Unwind_Word, _UVRSD_UINT32, - (&raw mut val) as *mut c_void); } + unsafe { + _Unwind_VRS_Get( + ctx, + _UVRSC_CORE, + reg_index as _Unwind_Word, + _UVRSD_UINT32, + (&raw mut val) as *mut c_void, + ); + } val } pub unsafe fn _Unwind_SetGR( ctx: *mut _Unwind_Context, reg_index: c_int, - value: _Unwind_Word + value: _Unwind_Word, ) { let mut value = value; - unsafe { _Unwind_VRS_Set(ctx, _UVRSC_CORE, reg_index as _Unwind_Word, _UVRSD_UINT32, - (&raw mut value) as *mut c_void); } - } - - pub unsafe fn _Unwind_GetIP(ctx: *mut _Unwind_Context) - -> _Unwind_Word { - let val = unsafe { _Unwind_GetGR(ctx, UNWIND_IP_REG) }; - val.map_addr(|v| v & !1) + unsafe { + _Unwind_VRS_Set( + ctx, + _UVRSC_CORE, + reg_index as _Unwind_Word, + _UVRSD_UINT32, + (&raw mut value) as *mut c_void, + ); + } } - pub unsafe fn _Unwind_SetIP(ctx: *mut _Unwind_Context, - value: _Unwind_Word) { + pub unsafe fn _Unwind_SetIP(ctx: *mut _Unwind_Context, value: _Unwind_Word) { // Propagate thumb bit to instruction pointer let thumb_state = unsafe { _Unwind_GetGR(ctx, UNWIND_IP_REG).addr() & 1 }; let value = value.map_addr(|v| v | thumb_state); - unsafe { _Unwind_SetGR(ctx, UNWIND_IP_REG, value); } - } - - pub unsafe fn _Unwind_GetIPInfo(ctx: *mut _Unwind_Context, - ip_before_insn: *mut c_int) - -> _Unwind_Word { unsafe { - *ip_before_insn = 0; - _Unwind_GetIP(ctx) + _Unwind_SetGR(ctx, UNWIND_IP_REG, value); } } - // This function also doesn't exist on Android or ARM/Linux, so make it a no-op - pub unsafe fn _Unwind_FindEnclosingFunction(pc: *mut c_void) -> *mut c_void { - pc + pub unsafe fn _Unwind_GetIPInfo( + ctx: *mut _Unwind_Context, + ip_before_insn: *mut c_int, + ) -> _Unwind_Word { + unsafe { *ip_before_insn = 0 }; + let val = unsafe { _Unwind_GetGR(ctx, UNWIND_IP_REG) }; + val.map_addr(|v| v & !1) } } } -cfg_select! { - all(target_vendor = "apple", not(target_os = "watchos"), target_arch = "arm") => { - // 32-bit ARM Apple (except for watchOS armv7k specifically) uses SjLj and - // does not provide _Unwind_Backtrace() - unsafe extern "C-unwind" { - pub fn _Unwind_SjLj_RaiseException(e: *mut _Unwind_Exception) -> _Unwind_Reason_Code; - } - - pub use _Unwind_SjLj_RaiseException as _Unwind_RaiseException; - } - _ => { - #[cfg_attr( - all(feature = "llvm-libunwind", any(target_os = "fuchsia", target_os = "linux", target_os = "xous")), - link(name = "unwind", kind = "static", modifiers = "-bundle") - )] - unsafe extern "C-unwind" { - pub fn _Unwind_RaiseException(exception: *mut _Unwind_Exception) -> _Unwind_Reason_Code; - } - #[cfg_attr( - all(feature = "llvm-libunwind", any(target_os = "fuchsia", target_os = "linux", target_os = "xous")), - link(name = "unwind", kind = "static", modifiers = "-bundle") - )] - unsafe extern "C" { - pub fn _Unwind_Backtrace(trace: _Unwind_Trace_Fn, - trace_argument: *mut c_void) - -> _Unwind_Reason_Code; - } - } +#[cfg_attr( + all(feature = "llvm-libunwind", any(target_os = "fuchsia", target_os = "linux")), + link(name = "unwind", kind = "static", modifiers = "-bundle") +)] +unsafe extern "C-unwind" { + // 32-bit ARM Apple (except for watchOS armv7k specifically) uses SjLj + #[cfg_attr( + all(target_vendor = "apple", not(target_os = "watchos"), target_arch = "arm"), + link_name = "_Unwind_SjLj_RaiseException" + )] + pub fn _Unwind_RaiseException(exception: *mut _Unwind_Exception) -> _Unwind_Reason_Code; } cfg_select! { @@ -306,20 +209,22 @@ cfg_select! { pub enum CONTEXT {} pub enum DISPATCHER_CONTEXT {} pub type EXCEPTION_DISPOSITION = c_int; - type PersonalityFn = unsafe extern "C" fn(version: c_int, - actions: _Unwind_Action, - exception_class: _Unwind_Exception_Class, - exception_object: *mut _Unwind_Exception, - context: *mut _Unwind_Context) - -> _Unwind_Reason_Code; + type PersonalityFn = unsafe extern "C" fn( + version: c_int, + actions: _Unwind_Action, + exception_class: _Unwind_Exception_Class, + exception_object: *mut _Unwind_Exception, + context: *mut _Unwind_Context, + ) -> _Unwind_Reason_Code; unsafe extern "C" { - pub fn _GCC_specific_handler(exceptionRecord: *mut EXCEPTION_RECORD, - establisherFrame: LPVOID, - contextRecord: *mut CONTEXT, - dispatcherContext: *mut DISPATCHER_CONTEXT, - personality: PersonalityFn) - -> EXCEPTION_DISPOSITION; + pub fn _GCC_specific_handler( + exceptionRecord: *mut EXCEPTION_RECORD, + establisherFrame: LPVOID, + contextRecord: *mut CONTEXT, + dispatcherContext: *mut DISPATCHER_CONTEXT, + personality: PersonalityFn, + ) -> EXCEPTION_DISPOSITION; } } _ => {} diff --git a/library/unwind/src/types.rs b/library/unwind/src/types.rs new file mode 100644 index 0000000000000..f7aa2554f6ee8 --- /dev/null +++ b/library/unwind/src/types.rs @@ -0,0 +1,59 @@ +#![allow(nonstandard_style)] + +#[repr(C)] +#[derive(Debug, Copy, Clone, PartialEq)] +pub enum _Unwind_Reason_Code { + _URC_NO_REASON = 0, + _URC_FOREIGN_EXCEPTION_CAUGHT = 1, + _URC_FATAL_PHASE2_ERROR = 2, + _URC_FATAL_PHASE1_ERROR = 3, + _URC_NORMAL_STOP = 4, + _URC_END_OF_STACK = 5, + _URC_HANDLER_FOUND = 6, + _URC_INSTALL_CONTEXT = 7, + _URC_CONTINUE_UNWIND = 8, + _URC_FAILURE = 9, // used only by ARM EHABI +} +pub use _Unwind_Reason_Code::*; + +pub type _Unwind_Exception_Class = u64; +pub type _Unwind_Word = *const u8; + +pub const unwinder_private_data_size: usize = + cfg_select! { + target_arch = "x86" => 5, + all(target_arch = "x86_64", not(any(target_os = "windows", target_os = "cygwin"))) => 2, + all(target_arch = "x86_64", any(target_os = "windows", target_os = "cygwin")) => 6, + all(target_arch = "arm", not(target_vendor = "apple")) => 20, + all(target_arch = "arm", target_vendor = "apple") => 5, + all(target_arch = "aarch64", target_pointer_width = "64", not(target_os = "windows")) => 2, + all(target_arch = "aarch64", target_pointer_width = "64", target_os = "windows") => 6, + all(target_arch = "aarch64", target_pointer_width = "32") => 5, + target_arch = "m68k" => 2, + any(target_arch = "mips", target_arch = "mips32r6") => 2, + target_arch = "csky" => 2, + any(target_arch = "mips64", target_arch = "mips64r6") => 2, + any(target_arch = "powerpc", target_arch = "powerpc64") => 2, + target_arch = "s390x" => 2, + any(target_arch = "sparc", target_arch = "sparc64") => 2, + any(target_arch = "riscv64", target_arch = "riscv32") => 2, + target_family = "wasm" => 2, + target_arch = "hexagon" => 5, + any(target_arch = "loongarch32", target_arch = "loongarch64") => 2, + }; + +#[repr(C)] +pub struct _Unwind_Exception { + pub exception_class: _Unwind_Exception_Class, + pub exception_cleanup: _Unwind_Exception_Cleanup_Fn, + pub private: [_Unwind_Word; unwinder_private_data_size], +} + +// Check the size of _Unwind_Exception against the source of truth when using the unwinding crate. +#[cfg(target_os = "xous")] +const _: () = { + assert!(size_of::() == size_of::<_Unwind_Exception>()); +}; + +pub type _Unwind_Exception_Cleanup_Fn = + Option; diff --git a/library/unwind/src/unwinding.rs b/library/unwind/src/unwinding.rs deleted file mode 100644 index 36120bc868ee9..0000000000000 --- a/library/unwind/src/unwinding.rs +++ /dev/null @@ -1,100 +0,0 @@ -#![allow(nonstandard_style)] - -use core::ffi::{c_int, c_void}; - -pub type _Unwind_Action = c_int; - -pub const _UA_SEARCH_PHASE: c_int = 1; -pub const _UA_CLEANUP_PHASE: c_int = 2; -pub const _UA_HANDLER_FRAME: c_int = 4; -pub const _UA_FORCE_UNWIND: c_int = 8; -pub const _UA_END_OF_STACK: c_int = 16; - -#[repr(C)] -#[derive(Debug, Copy, Clone, PartialEq)] -pub enum _Unwind_Reason_Code { - _URC_NO_REASON = 0, - _URC_FOREIGN_EXCEPTION_CAUGHT = 1, - _URC_FATAL_PHASE2_ERROR = 2, - _URC_FATAL_PHASE1_ERROR = 3, - _URC_NORMAL_STOP = 4, - _URC_END_OF_STACK = 5, - _URC_HANDLER_FOUND = 6, - _URC_INSTALL_CONTEXT = 7, - _URC_CONTINUE_UNWIND = 8, - _URC_FAILURE = 9, // used only by ARM EHABI -} -pub use _Unwind_Reason_Code::*; -pub use unwinding::abi::{UnwindContext, UnwindException}; -pub enum _Unwind_Context {} - -pub use unwinding::custom_eh_frame_finder::{ - EhFrameFinder, FrameInfo, FrameInfoKind, set_custom_eh_frame_finder, -}; - -pub type _Unwind_Exception_Class = u64; -pub type _Unwind_Word = *const u8; -pub type _Unwind_Ptr = *const u8; - -pub const unwinder_private_data_size: usize = size_of::() - - size_of::<_Unwind_Exception_Class>() - - size_of::<_Unwind_Exception_Cleanup_Fn>(); - -pub type _Unwind_Exception_Cleanup_Fn = - Option; - -#[repr(C)] -pub struct _Unwind_Exception { - pub exception_class: _Unwind_Exception_Class, - pub exception_cleanup: _Unwind_Exception_Cleanup_Fn, - pub private: [_Unwind_Word; unwinder_private_data_size], -} - -pub unsafe fn _Unwind_GetDataRelBase(ctx: *mut _Unwind_Context) -> _Unwind_Ptr { - let ctx = unsafe { &mut *(ctx as *mut UnwindContext<'_>) }; - unwinding::abi::_Unwind_GetDataRelBase(ctx) as _Unwind_Ptr -} - -pub unsafe fn _Unwind_GetTextRelBase(ctx: *mut _Unwind_Context) -> _Unwind_Ptr { - let ctx = unsafe { &mut *(ctx as *mut UnwindContext<'_>) }; - unwinding::abi::_Unwind_GetTextRelBase(ctx) as _Unwind_Ptr -} - -pub unsafe fn _Unwind_GetRegionStart(ctx: *mut _Unwind_Context) -> _Unwind_Ptr { - let ctx = unsafe { &mut *(ctx as *mut UnwindContext<'_>) }; - unwinding::abi::_Unwind_GetRegionStart(ctx) as _Unwind_Ptr -} - -pub unsafe fn _Unwind_SetGR(ctx: *mut _Unwind_Context, reg_index: c_int, value: _Unwind_Word) { - let ctx = unsafe { &mut *(ctx as *mut UnwindContext<'_>) }; - unwinding::abi::_Unwind_SetGR(ctx, reg_index, value as usize) -} - -pub unsafe fn _Unwind_SetIP(ctx: *mut _Unwind_Context, value: _Unwind_Word) { - let ctx = unsafe { &mut *(ctx as *mut UnwindContext<'_>) }; - unwinding::abi::_Unwind_SetIP(ctx, value as usize) -} - -pub unsafe fn _Unwind_GetIPInfo( - ctx: *mut _Unwind_Context, - ip_before_insn: *mut c_int, -) -> _Unwind_Word { - let ctx = unsafe { &mut *(ctx as *mut UnwindContext<'_>) }; - let ip_before_insn = unsafe { &mut *(ip_before_insn as *mut c_int) }; - unsafe { &*(unwinding::abi::_Unwind_GetIPInfo(ctx, ip_before_insn) as _Unwind_Word) } -} - -pub unsafe fn _Unwind_GetLanguageSpecificData(ctx: *mut _Unwind_Context) -> *mut c_void { - let ctx = unsafe { &mut *(ctx as *mut UnwindContext<'_>) }; - unwinding::abi::_Unwind_GetLanguageSpecificData(ctx) -} - -pub unsafe fn _Unwind_RaiseException(exception: *mut _Unwind_Exception) -> _Unwind_Reason_Code { - let exception = unsafe { &mut *(exception as *mut UnwindException) }; - unsafe { core::mem::transmute(unwinding::abi::_Unwind_RaiseException(exception)) } -} - -pub unsafe fn _Unwind_DeleteException(exception: *mut _Unwind_Exception) { - let exception = unsafe { &mut *(exception as *mut UnwindException) }; - unsafe { unwinding::abi::_Unwind_DeleteException(exception) } -} diff --git a/library/unwind/src/wasm.rs b/library/unwind/src/wasm.rs index 2bff306af293f..ef961ae6410a4 100644 --- a/library/unwind/src/wasm.rs +++ b/library/unwind/src/wasm.rs @@ -2,36 +2,31 @@ #![allow(nonstandard_style)] -#[repr(C)] -#[derive(Debug, Copy, Clone, PartialEq)] -pub enum _Unwind_Reason_Code { - _URC_NO_REASON = 0, - _URC_FOREIGN_EXCEPTION_CAUGHT = 1, - _URC_FATAL_PHASE2_ERROR = 2, - _URC_FATAL_PHASE1_ERROR = 3, - _URC_NORMAL_STOP = 4, - _URC_END_OF_STACK = 5, - _URC_HANDLER_FOUND = 6, - _URC_INSTALL_CONTEXT = 7, - _URC_CONTINUE_UNWIND = 8, - _URC_FAILURE = 9, // used only by ARM EHABI -} -pub use _Unwind_Reason_Code::*; - -pub type _Unwind_Exception_Class = u64; -pub type _Unwind_Word = *const u8; - -pub const unwinder_private_data_size: usize = 2; - -#[repr(C)] -pub struct _Unwind_Exception { - pub exception_class: _Unwind_Exception_Class, - pub exception_cleanup: _Unwind_Exception_Cleanup_Fn, - pub private: [_Unwind_Word; unwinder_private_data_size], -} +// Define the __cpp_exception tag that LLVM's wasm exception handling requires. +// In particular it is required to use either of: +// 1. the wasm_throw llvm intrinsic, or +// 2. the Rust try intrinsic. +// +// This must be provided since LLVM commit +// aee99e8015daa9f53ab1fd4e5b24cc4c694bdc4a which changed the tag from being +// weakly defined in each object file to being an external reference that must +// be linked from somewhere. +// +// We only define this for wasm32-unknown-unknown because on Emscripten/WASI +// targets, this symbol should be defined by the external toolchain. In +// particular, defining this on Emscripten would break Emscripten dynamic +// libraries. +#[cfg(all(target_os = "unknown", panic = "unwind"))] +core::arch::global_asm!( + ".globl __cpp_exception", + #[cfg(target_pointer_width = "64")] + ".tagtype __cpp_exception i64", + #[cfg(target_pointer_width = "32")] + ".tagtype __cpp_exception i32", + "__cpp_exception:", +); -pub type _Unwind_Exception_Cleanup_Fn = - Option; +pub use crate::types::*; pub unsafe fn _Unwind_DeleteException(exception: *mut _Unwind_Exception) { if let Some(exception_cleanup) = unsafe { (*exception).exception_cleanup } { @@ -73,7 +68,7 @@ pub unsafe fn _Unwind_RaiseException(exception: *mut _Unwind_Exception) -> _Unwi // corresponds with llvm::WebAssembly::Tag::CPP_EXCEPTION // in llvm-project/llvm/include/llvm/CodeGen/WasmEHFuncInfo.h const CPP_EXCEPTION_TAG: i32 = 0; - wasm_throw(CPP_EXCEPTION_TAG, exception.cast()) + unsafe { wasm_throw(CPP_EXCEPTION_TAG, exception.cast()) } } _ => { let _ = exception; diff --git a/library/windows-sys/Cargo.toml b/library/windows-sys/Cargo.toml new file mode 100644 index 0000000000000..eb27eff15e842 --- /dev/null +++ b/library/windows-sys/Cargo.toml @@ -0,0 +1,16 @@ +# dlmalloc has a dependency on windows-sys for when it gets compiled for Windows. +# std however never actually uses dlmalloc on Windows. As dlmalloc is the only +# user of windows-sys in the standard library, the windows-sys crate unnecessarily +# increases the size of the vendored crates. By replacing it with an empty crate +# we save about 19MB. + +[package] +name = "windows-sys" +version = "0.61.100" +edition = "2024" + +[features] +Win32_Foundation = [] +Win32_System_Memory = [] +Win32_System_Threading = [] +Win32_System_SystemInformation = [] diff --git a/library/windows-sys/src/lib.rs b/library/windows-sys/src/lib.rs new file mode 100644 index 0000000000000..112740ab2d1b4 --- /dev/null +++ b/library/windows-sys/src/lib.rs @@ -0,0 +1 @@ +compile_error!("This crate should never be compiled"); diff --git a/rust-toolchain.toml b/rust-toolchain.toml index d7a05c65d581f..bb13fc5c81fce 100644 --- a/rust-toolchain.toml +++ b/rust-toolchain.toml @@ -2,5 +2,5 @@ # standard library we currently track. [toolchain] -channel = "nightly-2026-02-05" +channel = "nightly-2026-08-21" components = ["llvm-tools-preview", "rustc-dev", "rust-src", "rustfmt"] diff --git a/tool_config/kani-version.toml b/tool_config/kani-version.toml index 37dd95386b80f..e2f476cede9a8 100644 --- a/tool_config/kani-version.toml +++ b/tool_config/kani-version.toml @@ -2,4 +2,4 @@ # incompatible with the verify-std repo. [kani] -commit = "152c6a8c875d9886a67e229247b4826d6105ccfd" +commit = "ebed1d11545d0efd1aac24fbeee2a2e6621ab075" diff --git a/verifast-proofs/alloc/collections/linked_list.rs-negative/original/linked_list.rs b/verifast-proofs/alloc/collections/linked_list.rs-negative/original/linked_list.rs index 3889fca30bc87..788609f740d07 100644 --- a/verifast-proofs/alloc/collections/linked_list.rs-negative/original/linked_list.rs +++ b/verifast-proofs/alloc/collections/linked_list.rs-negative/original/linked_list.rs @@ -12,6 +12,7 @@ #![stable(feature = "rust1", since = "1.0.0")] +use core::alloc::AllocatorClone; use core::cmp::Ordering; use core::hash::{Hash, Hasher}; use core::iter::FusedIterator; @@ -340,7 +341,7 @@ impl LinkedList { at: usize, ) -> Self where - A: Clone, + A: AllocatorClone, { // The split node is the new head node of the second part if let Some(mut split_node) = split_node { @@ -383,7 +384,7 @@ impl LinkedList { at: usize, ) -> Self where - A: Clone, + A: AllocatorClone, { // The split node is the new tail node of the first part and owns // the head of the second part. @@ -509,7 +510,7 @@ impl LinkedList { /// use std::alloc::System; /// use std::collections::LinkedList; /// - /// let list: LinkedList = LinkedList::new_in(System); + /// let list: LinkedList = LinkedList::new_in(System); /// ``` #[inline] #[unstable(feature = "allocator_api", issue = "32838")] @@ -862,7 +863,7 @@ impl LinkedList { /// *ptr += 4; /// assert_eq!(dl.front().unwrap(), &6); /// ``` - #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "push_mut", since = "1.95.0")] #[must_use = "if you don't need a reference to the value, use `LinkedList::push_front` instead"] pub fn push_front_mut(&mut self, elt: T) -> &mut T { let mut node = @@ -933,7 +934,7 @@ impl LinkedList { /// *ptr += 4; /// assert_eq!(dl.back().unwrap(), &6); /// ``` - #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "push_mut", since = "1.95.0")] #[must_use = "if you don't need a reference to the value, use `LinkedList::push_back` instead"] pub fn push_back_mut(&mut self, elt: T) -> &mut T { let mut node = @@ -994,7 +995,7 @@ impl LinkedList { #[stable(feature = "rust1", since = "1.0.0")] pub fn split_off(&mut self, at: usize) -> LinkedList where - A: Clone, + A: AllocatorClone, { let len = self.len(); assert!(at <= len, "Cannot split off at a nonexistent index"); @@ -1748,7 +1749,7 @@ impl<'a, T, A: Allocator> CursorMut<'a, T, A> { #[unstable(feature = "linked_list_cursors", issue = "58533")] pub fn remove_current_as_list(&mut self) -> Option> where - A: Clone, + A: AllocatorClone, { let mut unlinked_node = self.current?; unsafe { @@ -1776,7 +1777,7 @@ impl<'a, T, A: Allocator> CursorMut<'a, T, A> { #[unstable(feature = "linked_list_cursors", issue = "58533")] pub fn split_after(&mut self) -> LinkedList where - A: Clone, + A: AllocatorClone, { let split_off_idx = if self.index == self.list.len { 0 } else { self.index + 1 }; if self.index == self.list.len { @@ -1795,7 +1796,7 @@ impl<'a, T, A: Allocator> CursorMut<'a, T, A> { #[unstable(feature = "linked_list_cursors", issue = "58533")] pub fn split_before(&mut self) -> LinkedList where - A: Clone, + A: AllocatorClone, { let split_off_idx = self.index; self.index = 0; @@ -1942,7 +1943,9 @@ impl<'a, T, A: Allocator> CursorMut<'a, T, A> { } } -/// An iterator produced by calling `extract_if` on LinkedList. +/// This `struct` is created by the [`extract_if`] method on [`LinkedList`]. +/// +/// [`extract_if`]: LinkedList::extract_if #[stable(feature = "extract_if", since = "1.87.0")] #[must_use = "iterators are lazy and do nothing unless consumed; \ use `extract_if().for_each(drop)` to remove and discard elements"] @@ -2165,12 +2168,15 @@ impl Clone for LinkedList { /// resources of `self`'s elements as well. fn clone_from(&mut self, source: &Self) { let mut source_iter = source.iter(); - if self.len() > source.len() { - self.split_off(source.len()); - } - for (elem, source_elem) in self.iter_mut().zip(&mut source_iter) { + for elem in self.iter_mut() { + let Some(source_elem) = source_iter.next() else { + break; + }; elem.clone_from(source_elem); } + while self.len() > source.len() { + self.pop_back(); + } if !source_iter.is_empty() { self.extend(source_iter.cloned()); } diff --git a/verifast-proofs/alloc/collections/linked_list.rs-negative/verified/linked_list.rs b/verifast-proofs/alloc/collections/linked_list.rs-negative/verified/linked_list.rs index 373c4d60f2f51..4073606cf841c 100644 --- a/verifast-proofs/alloc/collections/linked_list.rs-negative/verified/linked_list.rs +++ b/verifast-proofs/alloc/collections/linked_list.rs-negative/verified/linked_list.rs @@ -12,6 +12,7 @@ #![stable(feature = "rust1", since = "1.0.0")] +use core::alloc::AllocatorClone; use core::cmp::Ordering; use core::hash::{Hash, Hasher}; use core::iter::FusedIterator; @@ -505,7 +506,7 @@ impl LinkedList { at: usize, ) -> Self where - A: Clone, + A: AllocatorClone, { // The split node is the new head node of the second part if let Some(mut split_node) = split_node { @@ -548,7 +549,7 @@ impl LinkedList { at: usize, ) -> Self where - A: Clone, + A: AllocatorClone, { // The split node is the new tail node of the first part and owns // the head of the second part. @@ -674,7 +675,7 @@ impl LinkedList { /// use std::alloc::System; /// use std::collections::LinkedList; /// - /// let list: LinkedList = LinkedList::new_in(System); + /// let list: LinkedList = LinkedList::new_in(System); /// ``` #[inline] #[unstable(feature = "allocator_api", issue = "32838")] @@ -1027,7 +1028,7 @@ impl LinkedList { /// *ptr += 4; /// assert_eq!(dl.front().unwrap(), &6); /// ``` - #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "push_mut", since = "1.95.0")] #[must_use = "if you don't need a reference to the value, use `LinkedList::push_front` instead"] pub fn push_front_mut(&mut self, elt: T) -> &mut T { let mut node = @@ -1098,7 +1099,7 @@ impl LinkedList { /// *ptr += 4; /// assert_eq!(dl.back().unwrap(), &6); /// ``` - #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "push_mut", since = "1.95.0")] #[must_use = "if you don't need a reference to the value, use `LinkedList::push_back` instead"] pub fn push_back_mut(&mut self, elt: T) -> &mut T { let mut node = @@ -1159,7 +1160,7 @@ impl LinkedList { #[stable(feature = "rust1", since = "1.0.0")] pub fn split_off(&mut self, at: usize) -> LinkedList where - A: Clone, + A: AllocatorClone, { let len = self.len(); assert!(at <= len, "Cannot split off at a nonexistent index"); @@ -1913,7 +1914,7 @@ impl<'a, T, A: Allocator> CursorMut<'a, T, A> { #[unstable(feature = "linked_list_cursors", issue = "58533")] pub fn remove_current_as_list(&mut self) -> Option> where - A: Clone, + A: AllocatorClone, { let mut unlinked_node = self.current?; unsafe { @@ -1941,7 +1942,7 @@ impl<'a, T, A: Allocator> CursorMut<'a, T, A> { #[unstable(feature = "linked_list_cursors", issue = "58533")] pub fn split_after(&mut self) -> LinkedList where - A: Clone, + A: AllocatorClone, { let split_off_idx = if self.index == self.list.len { 0 } else { self.index + 1 }; if self.index == self.list.len { @@ -1960,7 +1961,7 @@ impl<'a, T, A: Allocator> CursorMut<'a, T, A> { #[unstable(feature = "linked_list_cursors", issue = "58533")] pub fn split_before(&mut self) -> LinkedList where - A: Clone, + A: AllocatorClone, { let split_off_idx = self.index; self.index = 0; @@ -2107,7 +2108,9 @@ impl<'a, T, A: Allocator> CursorMut<'a, T, A> { } } -/// An iterator produced by calling `extract_if` on LinkedList. +/// This `struct` is created by the [`extract_if`] method on [`LinkedList`]. +/// +/// [`extract_if`]: LinkedList::extract_if #[stable(feature = "extract_if", since = "1.87.0")] #[must_use = "iterators are lazy and do nothing unless consumed; \ use `extract_if().for_each(drop)` to remove and discard elements"] @@ -2330,12 +2333,15 @@ impl Clone for LinkedList { /// resources of `self`'s elements as well. fn clone_from(&mut self, source: &Self) { let mut source_iter = source.iter(); - if self.len() > source.len() { - self.split_off(source.len()); - } - for (elem, source_elem) in self.iter_mut().zip(&mut source_iter) { + for elem in self.iter_mut() { + let Some(source_elem) = source_iter.next() else { + break; + }; elem.clone_from(source_elem); } + while self.len() > source.len() { + self.pop_back(); + } if !source_iter.is_empty() { self.extend(source_iter.cloned()); }

::Metadata ); -define!("mir_retag", fn Retag(place: T)); define!("mir_move", fn Move(place: T) -> T); define!("mir_static", fn Static(s: T) -> &'static T); define!("mir_static_mut", fn StaticMut(s: T) -> *mut T); diff --git a/library/core/src/intrinsics/mod.rs b/library/core/src/intrinsics/mod.rs index c87e94eff9995..440b687ac759e 100644 --- a/library/core/src/intrinsics/mod.rs +++ b/library/core/src/intrinsics/mod.rs @@ -55,10 +55,11 @@ use safety::{ensures, requires}; -use crate::ffi::va_list::{VaArgSafe, VaList}; +use crate::ffi::{VaArgSafe, VaList}; #[cfg(kani)] use crate::kani; use crate::marker::{ConstParamTy, DiscriminantKind, PointeeSized, Tuple}; +use crate::num::imp::libm; #[cfg(kani)] use crate::ub_checks; use crate::{mem, ptr}; @@ -100,7 +101,7 @@ pub enum AtomicOrdering { /// For example, [`AtomicBool::compare_exchange`]. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn atomic_cxchg< +pub const unsafe fn atomic_cxchg< T: Copy, const ORD_SUCC: AtomicOrdering, const ORD_FAIL: AtomicOrdering, @@ -118,7 +119,7 @@ pub unsafe fn atomic_cxchg< /// For example, [`AtomicBool::compare_exchange_weak`]. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn atomic_cxchgweak< +pub const unsafe fn atomic_cxchgweak< T: Copy, const ORD_SUCC: AtomicOrdering, const ORD_FAIL: AtomicOrdering, @@ -135,7 +136,9 @@ pub unsafe fn atomic_cxchgweak< /// [`atomic`] types via the `load` method. For example, [`AtomicBool::load`]. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn atomic_load(src: *const T) -> T; +pub const unsafe fn atomic_load( + src: *const T, +) -> T; /// Stores the value at the specified memory location. /// `T` must be an integer or pointer type. @@ -144,7 +147,10 @@ pub unsafe fn atomic_load(src: *const T) -> /// [`atomic`] types via the `store` method. For example, [`AtomicBool::store`]. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn atomic_store(dst: *mut T, val: T); +pub const unsafe fn atomic_store( + dst: *mut T, + val: T, +); /// Stores the value at the specified memory location, returning the old value. /// `T` must be an integer or pointer type. @@ -153,7 +159,7 @@ pub unsafe fn atomic_store(dst: *mut T, val: /// [`atomic`] types via the `swap` method. For example, [`AtomicBool::swap`]. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn atomic_xchg(dst: *mut T, src: T) -> T; +pub const unsafe fn atomic_xchg(dst: *mut T, src: T) -> T; /// Adds to the current value, returning the previous value. /// `T` must be an integer or pointer type. @@ -163,7 +169,10 @@ pub unsafe fn atomic_xchg(dst: *mut T, src: /// [`atomic`] types via the `fetch_add` method. For example, [`AtomicIsize::fetch_add`]. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn atomic_xadd(dst: *mut T, src: U) -> T; +pub const unsafe fn atomic_xadd( + dst: *mut T, + src: U, +) -> T; /// Subtract from the current value, returning the previous value. /// `T` must be an integer or pointer type. @@ -173,7 +182,10 @@ pub unsafe fn atomic_xadd(dst: *mut /// [`atomic`] types via the `fetch_sub` method. For example, [`AtomicIsize::fetch_sub`]. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn atomic_xsub(dst: *mut T, src: U) -> T; +pub const unsafe fn atomic_xsub( + dst: *mut T, + src: U, +) -> T; /// Bitwise and with the current value, returning the previous value. /// `T` must be an integer or pointer type. @@ -183,7 +195,10 @@ pub unsafe fn atomic_xsub(dst: *mut /// [`atomic`] types via the `fetch_and` method. For example, [`AtomicBool::fetch_and`]. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn atomic_and(dst: *mut T, src: U) -> T; +pub const unsafe fn atomic_and( + dst: *mut T, + src: U, +) -> T; /// Bitwise nand with the current value, returning the previous value. /// `T` must be an integer or pointer type. @@ -193,7 +208,10 @@ pub unsafe fn atomic_and(dst: *mut /// [`AtomicBool`] type via the `fetch_nand` method. For example, [`AtomicBool::fetch_nand`]. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn atomic_nand(dst: *mut T, src: U) -> T; +pub const unsafe fn atomic_nand( + dst: *mut T, + src: U, +) -> T; /// Bitwise or with the current value, returning the previous value. /// `T` must be an integer or pointer type. @@ -203,7 +221,10 @@ pub unsafe fn atomic_nand(dst: *mut /// [`atomic`] types via the `fetch_or` method. For example, [`AtomicBool::fetch_or`]. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn atomic_or(dst: *mut T, src: U) -> T; +pub const unsafe fn atomic_or( + dst: *mut T, + src: U, +) -> T; /// Bitwise xor with the current value, returning the previous value. /// `T` must be an integer or pointer type. @@ -213,7 +234,10 @@ pub unsafe fn atomic_or(dst: *mut T /// [`atomic`] types via the `fetch_xor` method. For example, [`AtomicBool::fetch_xor`]. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn atomic_xor(dst: *mut T, src: U) -> T; +pub const unsafe fn atomic_xor( + dst: *mut T, + src: U, +) -> T; /// Maximum with the current value using a signed comparison. /// `T` must be a signed integer type. @@ -222,7 +246,7 @@ pub unsafe fn atomic_xor(dst: *mut /// [`atomic`] signed integer types via the `fetch_max` method. For example, [`AtomicI32::fetch_max`]. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn atomic_max(dst: *mut T, src: T) -> T; +pub const unsafe fn atomic_max(dst: *mut T, src: T) -> T; /// Minimum with the current value using a signed comparison. /// `T` must be a signed integer type. @@ -231,7 +255,7 @@ pub unsafe fn atomic_max(dst: *mut T, src: T /// [`atomic`] signed integer types via the `fetch_min` method. For example, [`AtomicI32::fetch_min`]. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn atomic_min(dst: *mut T, src: T) -> T; +pub const unsafe fn atomic_min(dst: *mut T, src: T) -> T; /// Minimum with the current value using an unsigned comparison. /// `T` must be an unsigned integer type. @@ -240,7 +264,7 @@ pub unsafe fn atomic_min(dst: *mut T, src: T /// [`atomic`] unsigned integer types via the `fetch_min` method. For example, [`AtomicU32::fetch_min`]. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn atomic_umin(dst: *mut T, src: T) -> T; +pub const unsafe fn atomic_umin(dst: *mut T, src: T) -> T; /// Maximum with the current value using an unsigned comparison. /// `T` must be an unsigned integer type. @@ -249,7 +273,7 @@ pub unsafe fn atomic_umin(dst: *mut T, src: /// [`atomic`] unsigned integer types via the `fetch_max` method. For example, [`AtomicU32::fetch_max`]. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn atomic_umax(dst: *mut T, src: T) -> T; +pub const unsafe fn atomic_umax(dst: *mut T, src: T) -> T; /// An atomic fence. /// @@ -257,7 +281,7 @@ pub unsafe fn atomic_umax(dst: *mut T, src: /// [`atomic::fence`]. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn atomic_fence(); +pub const unsafe fn atomic_fence(); /// An atomic fence for synchronization within a single thread. /// @@ -265,7 +289,7 @@ pub unsafe fn atomic_fence(); /// [`atomic::compiler_fence`]. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn atomic_singlethreadfence(); +pub const unsafe fn atomic_singlethreadfence(); /// The `prefetch` intrinsic is a hint to the code generator to insert a prefetch instruction /// for the given address if supported; otherwise, it is a no-op. @@ -370,6 +394,8 @@ pub fn rustc_peek(_: T) -> T; /// On Unix, the /// process will probably terminate with a signal like `SIGABRT`, `SIGILL`, `SIGTRAP`, `SIGSEGV` or /// `SIGBUS`. The precise behavior is not guaranteed and not stable. +/// +/// The stabilization-track version of this intrinsic is [`core::process::abort_immediate`]. #[rustc_nounwind] #[rustc_intrinsic] pub fn abort() -> !; @@ -415,8 +441,7 @@ pub const unsafe fn assume(b: bool) { /// Therefore, implementations must not require the user to uphold /// any safety invariants. /// -/// This intrinsic does not have a stable counterpart. -#[unstable(feature = "core_intrinsics", issue = "none")] +/// The stabilized version of this intrinsic is [`core::hint::cold_path`]. #[rustc_intrinsic] #[rustc_nounwind] #[miri::intrinsic_fallback_is_spec] @@ -823,19 +848,19 @@ pub const fn forget(_: T); /// /// // This is how the standard library does it. This is the best method, if /// // you need to do something like this -/// fn split_at_stdlib(slice: &mut [T], mid: usize) +/// fn split_at_stdlib(to_split: &mut [T], mid: usize) /// -> (&mut [T], &mut [T]) { -/// let len = slice.len(); +/// let len = to_split.len(); /// assert!(mid <= len); /// unsafe { -/// let ptr = slice.as_mut_ptr(); -/// // This now has three mutable references pointing at the same -/// // memory. `slice`, the rvalue ret.0, and the rvalue ret.1. -/// // `slice` is never used after `let ptr = ...`, and so one can -/// // treat it as "dead", and therefore, you only have two real -/// // mutable slices. -/// (slice::from_raw_parts_mut(ptr, mid), -/// slice::from_raw_parts_mut(ptr.add(mid), len - mid)) +/// let ptr = to_split.as_mut_ptr(); +/// let fst = slice::from_raw_parts_mut(ptr, mid); +/// let snd = slice::from_raw_parts_mut(ptr.add(mid), len - mid); +/// // The function now has three mutable references to overlapping memory: +/// // `to_split`, `fst`, and `snd`. +/// // `to_split` is never used after `let ptr = ...` so it can be treated as "dead". +/// // This leaves two "live" mutable slice references, `fst` and `snd`, with no overlap. +/// (fst, snd) /// } /// } /// ``` @@ -877,7 +902,8 @@ pub const unsafe fn transmute_unchecked(src: Src) -> Dst; #[rustc_intrinsic_const_stable_indirect] #[rustc_nounwind] #[rustc_intrinsic] -pub const fn needs_drop() -> bool; +#[rustc_comptime] +pub fn needs_drop() -> bool; /// Calculates the offset from a pointer. /// @@ -994,20 +1020,20 @@ pub unsafe fn volatile_copy_memory(dst: *mut T, src: *const T, count: usize); /// [`write_bytes`]: ptr::write_bytes #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn volatile_set_memory(dst: *mut T, val: u8, count: usize); +pub const unsafe fn volatile_set_memory(dst: *mut T, val: u8, count: usize); /// Performs a volatile load from the `src` pointer. /// /// The stabilized version of this intrinsic is [`core::ptr::read_volatile`]. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn volatile_load(src: *const T) -> T; +pub const unsafe fn volatile_load(src: *const T) -> T; /// Performs a volatile store to the `dst` pointer. /// /// The stabilized version of this intrinsic is [`core::ptr::write_volatile`]. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn volatile_store(dst: *mut T, val: T); +pub const unsafe fn volatile_store(dst: *mut T, val: T); /// Performs a volatile load from the `src` pointer /// The pointer is not required to be aligned. @@ -1030,9 +1056,12 @@ pub unsafe fn unaligned_volatile_store(dst: *mut T, val: T); /// /// The stabilized version of this intrinsic is /// [`f16::sqrt`](../../std/primitive.f16.html#method.sqrt) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn sqrtf16(x: f16) -> f16; +pub fn sqrtf16(x: f16) -> f16 { + sqrtf32(x as f32) as f16 +} /// Returns the square root of an `f32` /// /// The stabilized version of this intrinsic is @@ -1059,9 +1088,12 @@ pub fn sqrtf128(x: f128) -> f128; /// /// The stabilized version of this intrinsic is /// [`f16::powi`](../../std/primitive.f16.html#method.powi) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn powif16(a: f16, x: i32) -> f16; +pub fn powif16(a: f16, x: i32) -> f16 { + powif32(a as f32, x) as f16 +} /// Raises an `f32` to an integer power. /// /// The stabilized version of this intrinsic is @@ -1088,243 +1120,368 @@ pub fn powif128(a: f128, x: i32) -> f128; /// /// The stabilized version of this intrinsic is /// [`f16::sin`](../../std/primitive.f16.html#method.sin) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn sinf16(x: f16) -> f16; +pub fn sinf16(x: f16) -> f16 { + sinf32(x as f32) as f16 +} /// Returns the sine of an `f32`. /// /// The stabilized version of this intrinsic is /// [`f32::sin`](../../std/primitive.f32.html#method.sin) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn sinf32(x: f32) -> f32; +pub fn sinf32(x: f32) -> f32 { + cfg_select! { + all(target_env = "msvc", target_arch = "x86") => sinf64(x as f64) as f32, + _ => libm::likely_available::sinf(x), + } +} /// Returns the sine of an `f64`. /// /// The stabilized version of this intrinsic is /// [`f64::sin`](../../std/primitive.f64.html#method.sin) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn sinf64(x: f64) -> f64; +pub fn sinf64(x: f64) -> f64 { + libm::likely_available::sin(x) +} /// Returns the sine of an `f128`. /// /// The stabilized version of this intrinsic is /// [`f128::sin`](../../std/primitive.f128.html#method.sin) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn sinf128(x: f128) -> f128; +pub fn sinf128(x: f128) -> f128 { + libm::maybe_available::sinf128(x) +} /// Returns the cosine of an `f16`. /// /// The stabilized version of this intrinsic is /// [`f16::cos`](../../std/primitive.f16.html#method.cos) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn cosf16(x: f16) -> f16; +pub fn cosf16(x: f16) -> f16 { + cosf32(x as f32) as f16 +} /// Returns the cosine of an `f32`. /// /// The stabilized version of this intrinsic is /// [`f32::cos`](../../std/primitive.f32.html#method.cos) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn cosf32(x: f32) -> f32; +pub fn cosf32(x: f32) -> f32 { + cfg_select! { + all(target_env = "msvc", target_arch = "x86") => cosf64(x as f64) as f32, + _ => libm::likely_available::cosf(x), + } +} /// Returns the cosine of an `f64`. /// /// The stabilized version of this intrinsic is /// [`f64::cos`](../../std/primitive.f64.html#method.cos) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn cosf64(x: f64) -> f64; +pub fn cosf64(x: f64) -> f64 { + libm::likely_available::cos(x) +} /// Returns the cosine of an `f128`. /// /// The stabilized version of this intrinsic is /// [`f128::cos`](../../std/primitive.f128.html#method.cos) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn cosf128(x: f128) -> f128; +pub fn cosf128(x: f128) -> f128 { + libm::maybe_available::cosf128(x) +} /// Raises an `f16` to an `f16` power. /// /// The stabilized version of this intrinsic is /// [`f16::powf`](../../std/primitive.f16.html#method.powf) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn powf16(a: f16, x: f16) -> f16; +pub fn powf16(a: f16, x: f16) -> f16 { + powf32(a as f32, x as f32) as f16 +} /// Raises an `f32` to an `f32` power. /// /// The stabilized version of this intrinsic is /// [`f32::powf`](../../std/primitive.f32.html#method.powf) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn powf32(a: f32, x: f32) -> f32; +pub fn powf32(a: f32, x: f32) -> f32 { + cfg_select! { + all(target_env = "msvc", target_arch = "x86") => powf64(a as f64, x as f64) as f32, + _ => libm::likely_available::powf(a, x), + } +} /// Raises an `f64` to an `f64` power. /// /// The stabilized version of this intrinsic is /// [`f64::powf`](../../std/primitive.f64.html#method.powf) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn powf64(a: f64, x: f64) -> f64; +pub fn powf64(a: f64, x: f64) -> f64 { + libm::likely_available::pow(a, x) +} /// Raises an `f128` to an `f128` power. /// /// The stabilized version of this intrinsic is /// [`f128::powf`](../../std/primitive.f128.html#method.powf) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn powf128(a: f128, x: f128) -> f128; +pub fn powf128(a: f128, x: f128) -> f128 { + libm::maybe_available::powf128(a, x) +} /// Returns the exponential of an `f16`. /// /// The stabilized version of this intrinsic is /// [`f16::exp`](../../std/primitive.f16.html#method.exp) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn expf16(x: f16) -> f16; +pub fn expf16(x: f16) -> f16 { + expf32(x as f32) as f16 +} /// Returns the exponential of an `f32`. /// /// The stabilized version of this intrinsic is /// [`f32::exp`](../../std/primitive.f32.html#method.exp) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn expf32(x: f32) -> f32; +pub fn expf32(x: f32) -> f32 { + cfg_select! { + all(target_env = "msvc", target_arch = "x86") => expf64(x as f64) as f32, + _ => libm::likely_available::expf(x), + } +} /// Returns the exponential of an `f64`. /// /// The stabilized version of this intrinsic is /// [`f64::exp`](../../std/primitive.f64.html#method.exp) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn expf64(x: f64) -> f64; +pub fn expf64(x: f64) -> f64 { + libm::likely_available::exp(x) +} /// Returns the exponential of an `f128`. /// /// The stabilized version of this intrinsic is /// [`f128::exp`](../../std/primitive.f128.html#method.exp) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn expf128(x: f128) -> f128; +pub fn expf128(x: f128) -> f128 { + libm::maybe_available::expf128(x) +} /// Returns 2 raised to the power of an `f16`. /// /// The stabilized version of this intrinsic is /// [`f16::exp2`](../../std/primitive.f16.html#method.exp2) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn exp2f16(x: f16) -> f16; +pub fn exp2f16(x: f16) -> f16 { + exp2f32(x as f32) as f16 +} /// Returns 2 raised to the power of an `f32`. /// /// The stabilized version of this intrinsic is /// [`f32::exp2`](../../std/primitive.f32.html#method.exp2) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn exp2f32(x: f32) -> f32; +pub fn exp2f32(x: f32) -> f32 { + cfg_select! { + all(target_env = "msvc", target_arch = "x86") => exp2f64(x as f64) as f32, + _ => libm::likely_available::exp2f(x), + } +} /// Returns 2 raised to the power of an `f64`. /// /// The stabilized version of this intrinsic is /// [`f64::exp2`](../../std/primitive.f64.html#method.exp2) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn exp2f64(x: f64) -> f64; +pub fn exp2f64(x: f64) -> f64 { + libm::likely_available::exp2(x) +} /// Returns 2 raised to the power of an `f128`. /// /// The stabilized version of this intrinsic is /// [`f128::exp2`](../../std/primitive.f128.html#method.exp2) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn exp2f128(x: f128) -> f128; +pub fn exp2f128(x: f128) -> f128 { + libm::maybe_available::exp2f128(x) +} /// Returns the natural logarithm of an `f16`. /// /// The stabilized version of this intrinsic is /// [`f16::ln`](../../std/primitive.f16.html#method.ln) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn logf16(x: f16) -> f16; +pub fn logf16(x: f16) -> f16 { + logf32(x as f32) as f16 +} /// Returns the natural logarithm of an `f32`. /// /// The stabilized version of this intrinsic is /// [`f32::ln`](../../std/primitive.f32.html#method.ln) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn logf32(x: f32) -> f32; +pub fn logf32(x: f32) -> f32 { + cfg_select! { + all(target_env = "msvc", target_arch = "x86") => logf64(x as f64) as f32, + _ => libm::likely_available::logf(x), + } +} /// Returns the natural logarithm of an `f64`. /// /// The stabilized version of this intrinsic is /// [`f64::ln`](../../std/primitive.f64.html#method.ln) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn logf64(x: f64) -> f64; +pub fn logf64(x: f64) -> f64 { + libm::likely_available::log(x) +} /// Returns the natural logarithm of an `f128`. /// /// The stabilized version of this intrinsic is /// [`f128::ln`](../../std/primitive.f128.html#method.ln) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn logf128(x: f128) -> f128; +pub fn logf128(x: f128) -> f128 { + libm::maybe_available::logf128(x) +} /// Returns the base 10 logarithm of an `f16`. /// /// The stabilized version of this intrinsic is /// [`f16::log10`](../../std/primitive.f16.html#method.log10) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn log10f16(x: f16) -> f16; +pub fn log10f16(x: f16) -> f16 { + log10f32(x as f32) as f16 +} /// Returns the base 10 logarithm of an `f32`. /// /// The stabilized version of this intrinsic is /// [`f32::log10`](../../std/primitive.f32.html#method.log10) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn log10f32(x: f32) -> f32; +pub fn log10f32(x: f32) -> f32 { + cfg_select! { + all(target_env = "msvc", target_arch = "x86") => log10f64(x as f64) as f32, + _ => libm::likely_available::log10f(x), + } +} /// Returns the base 10 logarithm of an `f64`. /// /// The stabilized version of this intrinsic is /// [`f64::log10`](../../std/primitive.f64.html#method.log10) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn log10f64(x: f64) -> f64; +pub fn log10f64(x: f64) -> f64 { + libm::likely_available::log10(x) +} /// Returns the base 10 logarithm of an `f128`. /// /// The stabilized version of this intrinsic is /// [`f128::log10`](../../std/primitive.f128.html#method.log10) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn log10f128(x: f128) -> f128; +pub fn log10f128(x: f128) -> f128 { + libm::maybe_available::log10f128(x) +} /// Returns the base 2 logarithm of an `f16`. /// /// The stabilized version of this intrinsic is /// [`f16::log2`](../../std/primitive.f16.html#method.log2) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn log2f16(x: f16) -> f16; +pub fn log2f16(x: f16) -> f16 { + log2f32(x as f32) as f16 +} /// Returns the base 2 logarithm of an `f32`. /// /// The stabilized version of this intrinsic is /// [`f32::log2`](../../std/primitive.f32.html#method.log2) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn log2f32(x: f32) -> f32; +pub fn log2f32(x: f32) -> f32 { + cfg_select! { + all(target_env = "msvc", target_arch = "x86") => log2f64(x as f64) as f32, + _ => libm::likely_available::log2f(x), + } +} /// Returns the base 2 logarithm of an `f64`. /// /// The stabilized version of this intrinsic is /// [`f64::log2`](../../std/primitive.f64.html#method.log2) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn log2f64(x: f64) -> f64; +pub fn log2f64(x: f64) -> f64 { + libm::likely_available::log2(x) +} /// Returns the base 2 logarithm of an `f128`. /// /// The stabilized version of this intrinsic is /// [`f128::log2`](../../std/primitive.f128.html#method.log2) +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub fn log2f128(x: f128) -> f128; +pub fn log2f128(x: f128) -> f128 { + libm::maybe_available::log2f128(x) +} -/// Returns `a * b + c` for `f16` values. +/// Returns `a * b + c` without rounding the intermediate result for `f16` values. /// /// The stabilized version of this intrinsic is /// [`f16::mul_add`](../../std/primitive.f16.html#method.mul_add) #[rustc_intrinsic_const_stable_indirect] +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub const fn fmaf16(a: f16, b: f16, c: f16) -> f16; -/// Returns `a * b + c` for `f32` values. +pub const fn fmaf16(a: f16, b: f16, c: f16) -> f16 { + // NOTE: f32 does not have sufficient precision, so use f64 instead. + // see also https://github.com/llvm/llvm-project/issues/128450#issuecomment-2727540179. + fmaf64(a as f64, b as f64, c as f64) as f16 +} +/// Returns `a * b + c` without rounding the intermediate result for `f32` values. /// /// The stabilized version of this intrinsic is /// [`f32::mul_add`](../../std/primitive.f32.html#method.mul_add) @@ -1332,7 +1489,7 @@ pub const fn fmaf16(a: f16, b: f16, c: f16) -> f16; #[rustc_intrinsic] #[rustc_nounwind] pub const fn fmaf32(a: f32, b: f32, c: f32) -> f32; -/// Returns `a * b + c` for `f64` values. +/// Returns `a * b + c` without rounding the intermediate result for `f64` values. /// /// The stabilized version of this intrinsic is /// [`f64::mul_add`](../../std/primitive.f64.html#method.mul_add) @@ -1340,7 +1497,7 @@ pub const fn fmaf32(a: f32, b: f32, c: f32) -> f32; #[rustc_intrinsic] #[rustc_nounwind] pub const fn fmaf64(a: f64, b: f64, c: f64) -> f64; -/// Returns `a * b + c` for `f128` values. +/// Returns `a * b + c` without rounding the intermediate result for `f128` values. /// /// The stabilized version of this intrinsic is /// [`f128::mul_add`](../../std/primitive.f128.html#method.mul_add) @@ -1359,9 +1516,12 @@ pub const fn fmaf128(a: f128, b: f128, c: f128) -> f128; /// and add instructions. It is unspecified whether or not a fused operation /// is selected, and that may depend on optimization level and context, for /// example. +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub const fn fmuladdf16(a: f16, b: f16, c: f16) -> f16; +pub const fn fmuladdf16(a: f16, b: f16, c: f16) -> f16 { + a * b + c +} /// Returns `a * b + c` for `f32` values, non-deterministically executing /// either a fused multiply-add or two operations with rounding of the /// intermediate result. @@ -1372,9 +1532,12 @@ pub const fn fmuladdf16(a: f16, b: f16, c: f16) -> f16; /// and add instructions. It is unspecified whether or not a fused operation /// is selected, and that may depend on optimization level and context, for /// example. +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub const fn fmuladdf32(a: f32, b: f32, c: f32) -> f32; +pub const fn fmuladdf32(a: f32, b: f32, c: f32) -> f32 { + a * b + c +} /// Returns `a * b + c` for `f64` values, non-deterministically executing /// either a fused multiply-add or two operations with rounding of the /// intermediate result. @@ -1385,9 +1548,12 @@ pub const fn fmuladdf32(a: f32, b: f32, c: f32) -> f32; /// and add instructions. It is unspecified whether or not a fused operation /// is selected, and that may depend on optimization level and context, for /// example. +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub const fn fmuladdf64(a: f64, b: f64, c: f64) -> f64; +pub const fn fmuladdf64(a: f64, b: f64, c: f64) -> f64 { + a * b + c +} /// Returns `a * b + c` for `f128` values, non-deterministically executing /// either a fused multiply-add or two operations with rounding of the /// intermediate result. @@ -1398,18 +1564,24 @@ pub const fn fmuladdf64(a: f64, b: f64, c: f64) -> f64; /// and add instructions. It is unspecified whether or not a fused operation /// is selected, and that may depend on optimization level and context, for /// example. +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub const fn fmuladdf128(a: f128, b: f128, c: f128) -> f128; +pub const fn fmuladdf128(a: f128, b: f128, c: f128) -> f128 { + a * b + c +} /// Returns the largest integer less than or equal to an `f16`. /// /// The stabilized version of this intrinsic is /// [`f16::floor`](../../std/primitive.f16.html#method.floor) #[rustc_intrinsic_const_stable_indirect] +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub const fn floorf16(x: f16) -> f16; +pub const fn floorf16(x: f16) -> f16 { + floorf32(x as f32) as f16 +} /// Returns the largest integer less than or equal to an `f32`. /// /// The stabilized version of this intrinsic is @@ -1440,9 +1612,12 @@ pub const fn floorf128(x: f128) -> f128; /// The stabilized version of this intrinsic is /// [`f16::ceil`](../../std/primitive.f16.html#method.ceil) #[rustc_intrinsic_const_stable_indirect] +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub const fn ceilf16(x: f16) -> f16; +pub const fn ceilf16(x: f16) -> f16 { + ceilf32(x as f32) as f16 +} /// Returns the smallest integer greater than or equal to an `f32`. /// /// The stabilized version of this intrinsic is @@ -1473,9 +1648,12 @@ pub const fn ceilf128(x: f128) -> f128; /// The stabilized version of this intrinsic is /// [`f16::trunc`](../../std/primitive.f16.html#method.trunc) #[rustc_intrinsic_const_stable_indirect] +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub const fn truncf16(x: f16) -> f16; +pub const fn truncf16(x: f16) -> f16 { + truncf32(x as f32) as f16 +} /// Returns the integer part of an `f32`. /// /// The stabilized version of this intrinsic is @@ -1507,9 +1685,12 @@ pub const fn truncf128(x: f128) -> f128; /// The stabilized version of this intrinsic is /// [`f16::round_ties_even`](../../std/primitive.f16.html#method.round_ties_even) #[rustc_intrinsic_const_stable_indirect] +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub const fn round_ties_even_f16(x: f16) -> f16; +pub const fn round_ties_even_f16(x: f16) -> f16 { + round_ties_even_f32(x as f32) as f16 +} /// Returns the nearest integer to an `f32`. Rounds half-way cases to the number with an even /// least significant digit. @@ -1546,9 +1727,12 @@ pub const fn round_ties_even_f128(x: f128) -> f128; /// The stabilized version of this intrinsic is /// [`f16::round`](../../std/primitive.f16.html#method.round) #[rustc_intrinsic_const_stable_indirect] +#[inline] #[rustc_intrinsic] #[rustc_nounwind] -pub const fn roundf16(x: f16) -> f16; +pub const fn roundf16(x: f16) -> f16 { + roundf32(x as f32) as f16 +} /// Returns the nearest integer to an `f32`. Rounds half-way cases away from zero. /// /// The stabilized version of this intrinsic is @@ -1580,7 +1764,7 @@ pub const fn roundf128(x: f128) -> f128; /// This intrinsic does not have a stable counterpart. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn fadd_fast(a: T, b: T) -> T; +pub unsafe fn fadd_fast(a: T, b: T) -> T; /// Float subtraction that allows optimizations based on algebraic rules. /// Requires that inputs and output of the operation are finite, causing UB otherwise. @@ -1588,7 +1772,7 @@ pub unsafe fn fadd_fast(a: T, b: T) -> T; /// This intrinsic does not have a stable counterpart. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn fsub_fast(a: T, b: T) -> T; +pub unsafe fn fsub_fast(a: T, b: T) -> T; /// Float multiplication that allows optimizations based on algebraic rules. /// Requires that inputs and output of the operation are finite, causing UB otherwise. @@ -1596,7 +1780,7 @@ pub unsafe fn fsub_fast(a: T, b: T) -> T; /// This intrinsic does not have a stable counterpart. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn fmul_fast(a: T, b: T) -> T; +pub unsafe fn fmul_fast(a: T, b: T) -> T; /// Float division that allows optimizations based on algebraic rules. /// Requires that inputs and output of the operation are finite, causing UB otherwise. @@ -1604,7 +1788,7 @@ pub unsafe fn fmul_fast(a: T, b: T) -> T; /// This intrinsic does not have a stable counterpart. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn fdiv_fast(a: T, b: T) -> T; +pub unsafe fn fdiv_fast(a: T, b: T) -> T; /// Float remainder that allows optimizations based on algebraic rules. /// Requires that inputs and output of the operation are finite, causing UB otherwise. @@ -1612,7 +1796,7 @@ pub unsafe fn fdiv_fast(a: T, b: T) -> T; /// This intrinsic does not have a stable counterpart. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn frem_fast(a: T, b: T) -> T; +pub unsafe fn frem_fast(a: T, b: T) -> T; /// Converts with LLVM’s fptoui/fptosi, which may return undef for values out of range /// () @@ -1620,42 +1804,48 @@ pub unsafe fn frem_fast(a: T, b: T) -> T; /// Stabilized as [`f32::to_int_unchecked`] and [`f64::to_int_unchecked`]. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn float_to_int_unchecked(value: Float) -> Int; +pub unsafe fn float_to_int_unchecked(value: Float) +-> Int; /// Float addition that allows optimizations based on algebraic rules. /// /// Stabilized as [`f16::algebraic_add`], [`f32::algebraic_add`], [`f64::algebraic_add`] and [`f128::algebraic_add`]. +#[rustc_intrinsic_const_stable_indirect] #[rustc_nounwind] #[rustc_intrinsic] -pub const fn fadd_algebraic(a: T, b: T) -> T; +pub const fn fadd_algebraic(a: T, b: T) -> T; /// Float subtraction that allows optimizations based on algebraic rules. /// /// Stabilized as [`f16::algebraic_sub`], [`f32::algebraic_sub`], [`f64::algebraic_sub`] and [`f128::algebraic_sub`]. +#[rustc_intrinsic_const_stable_indirect] #[rustc_nounwind] #[rustc_intrinsic] -pub const fn fsub_algebraic(a: T, b: T) -> T; +pub const fn fsub_algebraic(a: T, b: T) -> T; /// Float multiplication that allows optimizations based on algebraic rules. /// /// Stabilized as [`f16::algebraic_mul`], [`f32::algebraic_mul`], [`f64::algebraic_mul`] and [`f128::algebraic_mul`]. +#[rustc_intrinsic_const_stable_indirect] #[rustc_nounwind] #[rustc_intrinsic] -pub const fn fmul_algebraic(a: T, b: T) -> T; +pub const fn fmul_algebraic(a: T, b: T) -> T; /// Float division that allows optimizations based on algebraic rules. /// /// Stabilized as [`f16::algebraic_div`], [`f32::algebraic_div`], [`f64::algebraic_div`] and [`f128::algebraic_div`]. +#[rustc_intrinsic_const_stable_indirect] #[rustc_nounwind] #[rustc_intrinsic] -pub const fn fdiv_algebraic(a: T, b: T) -> T; +pub const fn fdiv_algebraic(a: T, b: T) -> T; /// Float remainder that allows optimizations based on algebraic rules. /// /// Stabilized as [`f16::algebraic_rem`], [`f32::algebraic_rem`], [`f64::algebraic_rem`] and [`f128::algebraic_rem`]. +#[rustc_intrinsic_const_stable_indirect] #[rustc_nounwind] #[rustc_intrinsic] -pub const fn frem_algebraic(a: T, b: T) -> T; +pub const fn frem_algebraic(a: T, b: T) -> T; /// Returns the number of bits set in an integer type `T` /// @@ -2058,7 +2248,8 @@ pub const fn rotate_right(x: T, shift: u32) -> unsafe { unchecked_funnel_shr(x, x, shift % (mem::size_of::() as u32 * 8)) } } -/// Returns (a + b) mod 2N, where N is the width of T in bits. +/// Wrapping (modular) addition. Computes `a + b`, +/// wrapping around at the boundary of the type. /// /// Note that, unlike most intrinsics, this is safe to call; /// it does not require an `unsafe` block. @@ -2072,7 +2263,8 @@ pub const fn rotate_right(x: T, shift: u32) -> #[rustc_nounwind] #[rustc_intrinsic] pub const fn wrapping_add(a: T, b: T) -> T; -/// Returns (a - b) mod 2N, where N is the width of T in bits. +/// Wrapping (modular) subtraction. Computes `a - b`, +/// wrapping around at the boundary of the type. /// /// Note that, unlike most intrinsics, this is safe to call; /// it does not require an `unsafe` block. @@ -2086,7 +2278,8 @@ pub const fn wrapping_add(a: T, b: T) -> T; #[rustc_nounwind] #[rustc_intrinsic] pub const fn wrapping_sub(a: T, b: T) -> T; -/// Returns (a * b) mod 2N, where N is the width of T in bits. +/// Wrapping (modular) multiplication. Computes `a * +/// b`, wrapping around at the boundary of the type. /// /// Note that, unlike most intrinsics, this is safe to call; /// it does not require an `unsafe` block. @@ -2185,6 +2378,19 @@ pub const unsafe fn unchecked_funnel_shr( unsafe { a.unchecked_funnel_shr(b, shift) } } +/// Carryless multiply. +/// +/// Safe versions of this intrinsic are available on the integer primitives +/// via the `carryless_mul` method. For example, [`u32::carryless_mul`]. +#[rustc_intrinsic] +#[rustc_nounwind] +#[rustc_const_unstable(feature = "uint_carryless_mul", issue = "152080")] +#[unstable(feature = "uint_carryless_mul", issue = "152080")] +#[miri::intrinsic_fallback_is_spec] +pub const fn carryless_mul(a: T, b: T) -> T { + a.carryless_mul(b) +} + /// This is an implementation detail of [`crate::ptr::read`] and should /// not be used anywhere else. See its comments for why this exists. /// @@ -2223,7 +2429,7 @@ pub const fn discriminant_value(v: &T) -> ::Discrimina /// Rust's "try catch" construct for unwinding. Invokes the function pointer `try_fn` with the /// data pointer `data`, and calls `catch_fn` if unwinding occurs while `try_fn` runs. -/// Returns `1` if unwinding occurred and `catch_fn` was called; returns `0` otherwise. +/// Returns `true` if unwinding occurred and `catch_fn` was called; returns `false` otherwise. /// /// `catch_fn` must not unwind. /// @@ -2240,11 +2446,11 @@ pub const fn discriminant_value(v: &T) -> ::Discrimina /// version of this intrinsic, `std::panic::catch_unwind`. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn catch_unwind( - _try_fn: fn(*mut u8), - _data: *mut u8, - _catch_fn: fn(*mut u8, *mut u8), -) -> i32; +pub unsafe fn catch_unwind( + _try_fn: unsafe fn(*mut Data), + _data: *mut Data, + _catch_fn: unsafe fn(*mut Data, *mut u8), +) -> bool; /// Emits a `nontemporal` store, which gives a hint to the CPU that the data should not be held /// in cache. Except for performance, this is fully equivalent to `ptr.write(val)`. @@ -2496,14 +2702,6 @@ pub(crate) macro const_eval_select { /// particular value, ever. However, the compiler will generally make it /// return `true` only if the value of the argument is actually known. /// -/// # Stability concerns -/// -/// While it is safe to call, this intrinsic may behave differently in -/// a `const` context than otherwise. See the [`const_eval_select()`] -/// documentation for an explanation of the issues this can cause. Unlike -/// `const_eval_select`, this intrinsic isn't guaranteed to behave -/// deterministically even in a `const` context. -/// /// # Type Requirements /// /// `T` must be either a `bool`, a `char`, a primitive numeric type (e.g. `f32`, @@ -2570,7 +2768,7 @@ pub const fn is_val_statically_known(_arg: T) -> bool { #[requires(ub_checks::can_dereference(x) && ub_checks::can_write(x))] #[requires(ub_checks::can_dereference(y) && ub_checks::can_write(y))] #[requires(x.addr() != y.addr() || core::mem::size_of::() == 0)] -#[requires(ub_checks::maybe_is_nonoverlapping(x as *const (), y as *const (), size_of::(), 1))] +#[requires(ub_checks::maybe_is_nonoverlapping(x as *const (), y as *const (), const { size_of::() }, 1))] #[ensures(|_| ub_checks::can_dereference(x) && ub_checks::can_dereference(y))] pub const unsafe fn typed_swap_nonoverlapping(x: *mut T, y: *mut T) { // SAFETY: The caller provided single non-overlapping items behind @@ -2591,6 +2789,12 @@ pub const unsafe fn typed_swap_nonoverlapping(x: *mut T, y: *mut T) { /// assertions are enabled whenever the *user crate* has UB checks enabled. However, if the /// user has UB checks disabled, the checks will still get optimized out. This intrinsic is /// primarily used by [`crate::ub_checks::assert_unsafe_precondition`]. +/// +/// # Consteval +/// +/// In consteval, this function currently returns `true`. This is because the value of the `ub_checks` +/// configuration can differ across crates, but we need this function to always return the same +/// value in consteval in order to avoid unsoundness. #[rustc_intrinsic_const_stable_indirect] // just for UB checks #[inline(always)] #[rustc_intrinsic] @@ -2610,6 +2814,12 @@ pub const fn ub_checks() -> bool { /// `#[inline]`), gating assertions on `overflow_checks()` rather than `cfg!(overflow_checks)` means that /// assertions are enabled whenever the *user crate* has overflow checks enabled. However if the /// user has overflow checks disabled, the checks will still get optimized out. +/// +/// # Consteval +/// +/// In consteval, this function currently returns `true`. This is because the value of the `overflow_checks` +/// configuration can differ across crates, but we need this function to always return the same +/// value in consteval in order to avoid unsoundness. #[inline(always)] #[rustc_intrinsic] pub const fn overflow_checks() -> bool { @@ -2764,18 +2974,6 @@ pub unsafe fn vtable_size(_ptr: *const ()) -> usize; // #[requires(ub_checks::can_dereference(_ptr as *const [usize; 3]))] pub unsafe fn vtable_align(_ptr: *const ()) -> usize; -/// The intrinsic returns the `U` vtable for `T` if `T` can be coerced to the trait object type `U`. -/// -/// # Compile-time failures -/// Determining whether `T` can be coerced to the trait object type `U` requires trait resolution by the compiler. -/// In some cases, that resolution can exceed the recursion limit, -/// and compilation will fail instead of this function returning `None`. -#[rustc_nounwind] -#[unstable(feature = "core_intrinsics", issue = "none")] -#[rustc_intrinsic] -pub const fn vtable_for> + ?Sized>() --> Option>; - /// The size of a type in bytes. /// /// Note that, unlike most intrinsics, this is safe to call; @@ -2796,7 +2994,8 @@ pub const fn vtable_for> + ?Si #[unstable(feature = "core_intrinsics", issue = "none")] #[rustc_intrinsic_const_stable_indirect] #[rustc_intrinsic] -pub const fn size_of() -> usize; +#[rustc_comptime] +pub fn size_of() -> usize; /// The minimum alignment of a type. /// @@ -2815,7 +3014,8 @@ pub const fn size_of() -> usize; #[unstable(feature = "core_intrinsics", issue = "none")] #[rustc_intrinsic_const_stable_indirect] #[rustc_intrinsic] -pub const fn align_of() -> usize; +#[rustc_comptime] +pub fn align_of() -> usize; /// The offset of a field inside a type. /// @@ -2835,7 +3035,23 @@ pub const fn align_of() -> usize; #[rustc_intrinsic_const_stable_indirect] #[rustc_intrinsic] #[lang = "offset_of"] -pub const fn offset_of(variant: u32, field: u32) -> usize; +#[rustc_comptime] +pub fn offset_of(variant: u32, field: u32) -> usize; + +/// The offset of a field queried by its field representing type. +/// +/// Returns the offset of the field represented by `F`. This function essentially does the same as +/// the [`offset_of`] intrinsic, but expects the field to be represented by a generic rather than +/// the variant and field indices. This also is a safe intrinsic and can only be evaluated at +/// compile-time, so it should only appear in constants or inline const blocks. +/// +/// There should be no need to call this intrinsic manually, as its value is used to define +/// [`Field::OFFSET`](crate::field::Field::OFFSET), which is publicly accessible. +#[rustc_intrinsic] +#[unstable(feature = "field_projections", issue = "145383")] +#[rustc_const_unstable(feature = "field_projections", issue = "145383")] +#[rustc_comptime] +pub fn field_offset() -> usize; /// Returns the number of variants of the type `T` cast to a `usize`; /// if `T` has no variants, returns `0`. Uninhabited variants will be counted. @@ -2849,7 +3065,8 @@ pub const fn offset_of(variant: u32, field: u32) -> usize; #[rustc_nounwind] #[unstable(feature = "core_intrinsics", issue = "none")] #[rustc_intrinsic] -pub const fn variant_count() -> usize; +#[rustc_comptime] +pub fn variant_count() -> usize; /// The size of the referenced value in bytes. /// @@ -2877,14 +3094,24 @@ pub const unsafe fn size_of_val(ptr: *const T) -> usize; #[rustc_intrinsic_const_stable_indirect] pub const unsafe fn align_of_val(ptr: *const T) -> usize; +#[rustc_intrinsic] +#[rustc_comptime] +#[unstable(feature = "core_intrinsics", issue = "none")] +/// Check if a type represented by a `TypeId` implements a trait represented by a `TypeId`. +/// It can only be called at compile time, the backends do +/// not implement it. If it implements the trait the dyn metadata gets returned for vtable access. +pub fn type_id_vtable( + _id: crate::any::TypeId, + _trait: crate::any::TypeId, +) -> Option>; + /// Compute the type information of a concrete type. /// It can only be called at compile time, the backends do /// not implement it. #[rustc_intrinsic] #[unstable(feature = "core_intrinsics", issue = "none")] -pub const fn type_of(_id: crate::any::TypeId) -> crate::mem::type_info::Type { - panic!("`TypeId::info` can only be called at compile-time") -} +#[rustc_comptime] +pub fn type_of(_id: crate::any::TypeId) -> crate::mem::type_info::Type; /// Gets a static string slice containing the name of a type. /// @@ -2897,7 +3124,8 @@ pub const fn type_of(_id: crate::any::TypeId) -> crate::mem::type_info::Type { #[rustc_nounwind] #[unstable(feature = "core_intrinsics", issue = "none")] #[rustc_intrinsic] -pub const fn type_name() -> &'static str; +#[rustc_comptime] +pub fn type_name() -> &'static str; /// Gets an identifier which is globally unique to the specified type. This /// function will return the same value for a type regardless of whichever @@ -2912,7 +3140,8 @@ pub const fn type_name() -> &'static str; #[rustc_nounwind] #[unstable(feature = "core_intrinsics", issue = "none")] #[rustc_intrinsic] -pub const fn type_id() -> crate::any::TypeId; +#[rustc_comptime] +pub fn type_id() -> crate::any::TypeId; /// Tests (at compile-time) if two [`crate::any::TypeId`] instances identify the /// same type. This is necessary because at const-eval time the actual discriminating @@ -2924,9 +3153,124 @@ pub const fn type_id() -> crate::any::TypeId; #[rustc_intrinsic] #[rustc_do_not_const_check] pub const fn type_id_eq(a: crate::any::TypeId, b: crate::any::TypeId) -> bool { - a.data == b.data + // SAFETY: we know `TypeId` is 16 bytes of initialized data. + // This is runtime-only code so we do not have to worry about provenance. + unsafe { crate::mem::transmute::<_, u128>(a) == crate::mem::transmute::<_, u128>(b) } } +/// Returns whether the type represented by this `TypeId` is a signed integer. +/// +/// The more user-friendly version of this intrinsic is [`core::any::TypeId::is_signed`]. +#[rustc_intrinsic] +#[unstable(feature = "core_intrinsics", issue = "none")] +#[rustc_comptime] +pub fn type_id_is_signed(_id: crate::any::TypeId) -> bool; + +/// Gets the size of the type represented by this `TypeId`. +/// +/// The more user-friendly version of this intrinsic is [`core::any::TypeId::size`]. +#[rustc_intrinsic] +#[unstable(feature = "core_intrinsics", issue = "none")] +#[rustc_comptime] +pub fn size_of_type_id(_id: crate::any::TypeId) -> Option; + +/// Gets the number of variants of the type represented by this `TypeId`. +/// +/// The more user-friendly version of this intrinsic is [`core::any::TypeId::variants`]. +#[rustc_intrinsic] +#[unstable(feature = "core_intrinsics", issue = "none")] +#[rustc_comptime] +pub fn type_id_variants(_id: crate::any::TypeId) -> usize; + +/// Gets the name of the variant represented by the base `TypeId` and variant_idx. +/// +/// The more user-friendly version of this intrinsic is [`core::mem::type_info::VariantId::name`]. +/// +/// [`TypeId`]: crate::any::TypeId +#[rustc_intrinsic] +#[unstable(feature = "core_intrinsics", issue = "none")] +#[rustc_comptime] +pub fn variant_name(_base: crate::any::TypeId, _variant_index: usize) -> &'static str; + +/// Returns true when the variant represented by the base `TypeId` and variant_idx is non +/// exhaustive. +/// +/// The more user-friendly version of this intrinsic is +/// [`core::mem::type_info::VariantId::non_exhaustive`]. +/// +/// [`TypeId`]: crate::any::TypeId +#[rustc_intrinsic] +#[unstable(feature = "core_intrinsics", issue = "none")] +#[rustc_comptime] +pub fn variant_non_exhaustive(base: crate::any::TypeId, variant: usize) -> bool; + +/// Gets the number of fields at the given `variant_index` represented by this `TypeId`. +/// +/// The more user-friendly version of this intrinsic is [`core::any::TypeId::fields`]. +#[rustc_intrinsic] +#[unstable(feature = "core_intrinsics", issue = "none")] +#[rustc_comptime] +pub fn type_id_fields(_id: crate::any::TypeId, _variant_index: usize) -> usize; + +/// Gets the [`FieldRepresentingType`]'s `TypeId` at the given index of the type represented by this `TypeId`. +/// +/// The more user-friendly version of this intrinsic is [`core::any::TypeId::field`]. +/// +/// [`FieldRepresentingType`]: crate::field::FieldRepresentingType +#[rustc_intrinsic] +#[unstable(feature = "core_intrinsics", issue = "none")] +#[rustc_comptime] +pub fn type_id_field_representing_type( + _id: crate::any::TypeId, + _variant_index: usize, + _field_index: usize, +) -> crate::any::TypeId; + +/// Gets the actual field `TypeId` of the [`FieldRepresentingType`]'s `TypeId`. +/// +/// The more user-friendly version of this intrinsic is [`core::mem::type_info::FieldId::type_id`]. +/// +/// [`FieldRepresentingType`]: crate::field::FieldRepresentingType +#[rustc_intrinsic] +#[unstable(feature = "core_intrinsics", issue = "none")] +#[rustc_comptime] +pub fn field_representing_type_actual_type_id( + _frt_type_id: crate::any::TypeId, +) -> crate::any::TypeId; + +/// Gets the name of the field represented by the [`FieldRepresentingType`]'s `TypeId`. +/// +/// The more user-friendly version of this intrinsic is [`core::mem::type_info::FieldId::name`]. +/// +/// [`FieldRepresentingType`]: crate::field::FieldRepresentingType +#[rustc_intrinsic] +#[unstable(feature = "core_intrinsics", issue = "none")] +#[rustc_comptime] +pub fn field_representing_type_name(_frt_type_id: crate::any::TypeId) -> &'static str; + +/// Gets the name of the field represented by the [`FieldRepresentingType`]'s `TypeId`. +/// +/// The more user-friendly version of this intrinsic is [`core::mem::type_info::FieldId::name`]. +/// +/// [`FieldRepresentingType`]: crate::field::FieldRepresentingType +#[rustc_intrinsic] +#[unstable(feature = "core_intrinsics", issue = "none")] +#[rustc_comptime] +pub fn field_representing_type_offset(_frt_type_id: crate::any::TypeId) -> usize; + +/// Checks whether this type is non-exhaustive. +#[rustc_intrinsic] +#[unstable(feature = "core_intrinsics", issue = "none")] +#[rustc_comptime] +pub fn non_exhaustive(_id: crate::any::TypeId) -> bool; + +/// Returns the list of generic args on this type. +/// Only meaningful for Adts, closures, ... Everything else returns an empty slice. +#[rustc_intrinsic] +#[unstable(feature = "core_intrinsics", issue = "none")] +#[rustc_comptime] +pub fn type_id_generics(_id: crate::any::TypeId) -> &'static [crate::mem::type_info::Generic]; + /// Lowers in MIR to `Rvalue::Aggregate` with `AggregateKind::RawPtr`. /// /// This is used to implement functions like `slice::from_raw_parts_mut` and @@ -2965,7 +3309,7 @@ fn check_copy_untyped(src: *const T, dst: *mut T, count: usize) -> bool { #[cfg(kani)] if count > 0 { // Inspect a non-deterministically chosen byte in the copy. - let byte = kani::any_where(|sz: &usize| *sz < size_of::()); + let byte = kani::any_where(|sz: &usize| *sz < const { size_of::() }); // Instead of checking each of the `count`-many copies, non-deterministically pick one of // them and check it. Using quantifiers would not add value as we can rely on the solver to // pick an uninitialized element if such an element exists. @@ -3040,6 +3384,8 @@ pub const unsafe fn write_bytes(dst: *mut T, val: u8, count: usize); /// Returns the minimum of two `f16` values, ignoring NaN. /// +/// This behaves like IEEE 754-2019 minimumNumber, *except* that it does not order signed +/// zeros deterministically. In particular: /// If one of the arguments is NaN (quiet or signaling), then the other argument is returned. If /// both arguments are NaN, returns NaN. If the inputs compare equal (such as for the case of `+0.0` /// and `-0.0`), either input may be returned non-deterministically. @@ -3052,10 +3398,19 @@ pub const unsafe fn write_bytes(dst: *mut T, val: u8, count: usize); /// The stabilized version of this intrinsic is [`f16::min`]. #[rustc_nounwind] #[rustc_intrinsic] -pub const fn minnumf16(x: f16, y: f16) -> f16; +pub const fn minimum_number_nsz_f16(x: f16, y: f16) -> f16 { + if x.is_nan() || y <= x { + y + } else { + // Either y > x or y is a NaN. + x + } +} /// Returns the minimum of two `f32` values, ignoring NaN. /// +/// This behaves like IEEE 754-2019 minimumNumber, *except* that it does not order signed +/// zeros deterministically. In particular: /// If one of the arguments is NaN (quiet or signaling), then the other argument is returned. If /// both arguments are NaN, returns NaN. If the inputs compare equal (such as for the case of `+0.0` /// and `-0.0`), either input may be returned non-deterministically. @@ -3069,10 +3424,19 @@ pub const fn minnumf16(x: f16, y: f16) -> f16; #[rustc_nounwind] #[rustc_intrinsic_const_stable_indirect] #[rustc_intrinsic] -pub const fn minnumf32(x: f32, y: f32) -> f32; +pub const fn minimum_number_nsz_f32(x: f32, y: f32) -> f32 { + if x.is_nan() || y <= x { + y + } else { + // Either y > x or y is a NaN. + x + } +} /// Returns the minimum of two `f64` values, ignoring NaN. /// +/// This behaves like IEEE 754-2019 minimumNumber, *except* that it does not order signed +/// zeros deterministically. In particular: /// If one of the arguments is NaN (quiet or signaling), then the other argument is returned. If /// both arguments are NaN, returns NaN. If the inputs compare equal (such as for the case of `+0.0` /// and `-0.0`), either input may be returned non-deterministically. @@ -3086,10 +3450,19 @@ pub const fn minnumf32(x: f32, y: f32) -> f32; #[rustc_nounwind] #[rustc_intrinsic_const_stable_indirect] #[rustc_intrinsic] -pub const fn minnumf64(x: f64, y: f64) -> f64; +pub const fn minimum_number_nsz_f64(x: f64, y: f64) -> f64 { + if x.is_nan() || y <= x { + y + } else { + // Either y > x or y is a NaN. + x + } +} /// Returns the minimum of two `f128` values, ignoring NaN. /// +/// This behaves like IEEE 754-2019 minimumNumber, *except* that it does not order signed +/// zeros deterministically. In particular: /// If one of the arguments is NaN (quiet or signaling), then the other argument is returned. If /// both arguments are NaN, returns NaN. If the inputs compare equal (such as for the case of `+0.0` /// and `-0.0`), either input may be returned non-deterministically. @@ -3102,7 +3475,14 @@ pub const fn minnumf64(x: f64, y: f64) -> f64; /// The stabilized version of this intrinsic is [`f128::min`]. #[rustc_nounwind] #[rustc_intrinsic] -pub const fn minnumf128(x: f128, y: f128) -> f128; +pub const fn minimum_number_nsz_f128(x: f128, y: f128) -> f128 { + if x.is_nan() || y <= x { + y + } else { + // Either y > x or y is a NaN. + x + } +} /// Returns the minimum of two `f16` values, propagating NaN. /// @@ -3206,6 +3586,8 @@ pub const fn minimumf128(x: f128, y: f128) -> f128 { /// Returns the maximum of two `f16` values, ignoring NaN. /// +/// This behaves like IEEE 754-2019 maximumNumber, *except* that it does not order signed +/// zeros deterministically. In particular: /// If one of the arguments is NaN (quiet or signaling), then the other argument is returned. If /// both arguments are NaN, returns NaN. If the inputs compare equal (such as for the case of `+0.0` /// and `-0.0`), either input may be returned non-deterministically. @@ -3218,10 +3600,19 @@ pub const fn minimumf128(x: f128, y: f128) -> f128 { /// The stabilized version of this intrinsic is [`f16::max`]. #[rustc_nounwind] #[rustc_intrinsic] -pub const fn maxnumf16(x: f16, y: f16) -> f16; +pub const fn maximum_number_nsz_f16(x: f16, y: f16) -> f16 { + if x.is_nan() || y >= x { + y + } else { + // Either y < x or y is a NaN. + x + } +} /// Returns the maximum of two `f32` values, ignoring NaN. /// +/// This behaves like IEEE 754-2019 maximumNumber, *except* that it does not order signed +/// zeros deterministically. In particular: /// If one of the arguments is NaN (quiet or signaling), then the other argument is returned. If /// both arguments are NaN, returns NaN. If the inputs compare equal (such as for the case of `+0.0` /// and `-0.0`), either input may be returned non-deterministically. @@ -3235,10 +3626,19 @@ pub const fn maxnumf16(x: f16, y: f16) -> f16; #[rustc_nounwind] #[rustc_intrinsic_const_stable_indirect] #[rustc_intrinsic] -pub const fn maxnumf32(x: f32, y: f32) -> f32; +pub const fn maximum_number_nsz_f32(x: f32, y: f32) -> f32 { + if x.is_nan() || y >= x { + y + } else { + // Either y < x or y is a NaN. + x + } +} /// Returns the maximum of two `f64` values, ignoring NaN. /// +/// This behaves like IEEE 754-2019 maximumNumber, *except* that it does not order signed +/// zeros deterministically. In particular: /// If one of the arguments is NaN (quiet or signaling), then the other argument is returned. If /// both arguments are NaN, returns NaN. If the inputs compare equal (such as for the case of `+0.0` /// and `-0.0`), either input may be returned non-deterministically. @@ -3252,10 +3652,19 @@ pub const fn maxnumf32(x: f32, y: f32) -> f32; #[rustc_nounwind] #[rustc_intrinsic_const_stable_indirect] #[rustc_intrinsic] -pub const fn maxnumf64(x: f64, y: f64) -> f64; +pub const fn maximum_number_nsz_f64(x: f64, y: f64) -> f64 { + if x.is_nan() || y >= x { + y + } else { + // Either y < x or y is a NaN. + x + } +} /// Returns the maximum of two `f128` values, ignoring NaN. /// +/// This behaves like IEEE 754-2019 maximumNumber, *except* that it does not order signed +/// zeros deterministically. In particular: /// If one of the arguments is NaN (quiet or signaling), then the other argument is returned. If /// both arguments are NaN, returns NaN. If the inputs compare equal (such as for the case of `+0.0` /// and `-0.0`), either input may be returned non-deterministically. @@ -3268,7 +3677,14 @@ pub const fn maxnumf64(x: f64, y: f64) -> f64; /// The stabilized version of this intrinsic is [`f128::max`]. #[rustc_nounwind] #[rustc_intrinsic] -pub const fn maxnumf128(x: f128, y: f128) -> f128; +pub const fn maximum_number_nsz_f128(x: f128, y: f128) -> f128 { + if x.is_nan() || y >= x { + y + } else { + // Either y < x or y is a NaN. + x + } +} /// Returns the maximum of two `f16` values, propagating NaN. /// @@ -3366,72 +3782,63 @@ pub const fn maximumf128(x: f128, y: f128) -> f128 { } } -/// Returns the absolute value of an `f16`. -/// -/// The stabilized version of this intrinsic is -/// [`f16::abs`](../../std/primitive.f16.html#method.abs) -#[rustc_nounwind] -#[rustc_intrinsic] -pub const fn fabsf16(x: f16) -> f16; - -/// Returns the absolute value of an `f32`. +/// Returns the absolute value of a floating-point value. /// -/// The stabilized version of this intrinsic is -/// [`f32::abs`](../../std/primitive.f32.html#method.abs) -#[rustc_nounwind] -#[rustc_intrinsic_const_stable_indirect] -#[rustc_intrinsic] -pub const fn fabsf32(x: f32) -> f32; - -/// Returns the absolute value of an `f64`. -/// -/// The stabilized version of this intrinsic is -/// [`f64::abs`](../../std/primitive.f64.html#method.abs) +/// The stabilized versions of this intrinsic are available on the float +/// primitives via the `abs` method. For example, [`f32::abs`]. #[rustc_nounwind] +#[rustc_const_unstable(feature = "core_intrinsics", issue = "none")] #[rustc_intrinsic_const_stable_indirect] #[rustc_intrinsic] -pub const fn fabsf64(x: f64) -> f64; - -/// Returns the absolute value of an `f128`. -/// -/// The stabilized version of this intrinsic is -/// [`f128::abs`](../../std/primitive.f128.html#method.abs) -#[rustc_nounwind] -#[rustc_intrinsic] -pub const fn fabsf128(x: f128) -> f128; +#[miri::intrinsic_fallback_is_spec] +pub const fn fabs(x: T) -> T { + T::from_bits(x.to_bits() & !T::SIGN_MASK) +} /// Copies the sign from `y` to `x` for `f16` values. /// /// The stabilized version of this intrinsic is /// [`f16::copysign`](../../std/primitive.f16.html#method.copysign) +#[inline] #[rustc_nounwind] #[rustc_intrinsic] -pub const fn copysignf16(x: f16, y: f16) -> f16; +pub const fn copysignf16(x: f16, y: f16) -> f16 { + f16::from_bits((x.to_bits() & !f16::SIGN_MASK) | (y.to_bits() & f16::SIGN_MASK)) +} /// Copies the sign from `y` to `x` for `f32` values. /// /// The stabilized version of this intrinsic is /// [`f32::copysign`](../../std/primitive.f32.html#method.copysign) +#[inline] #[rustc_nounwind] #[rustc_intrinsic_const_stable_indirect] #[rustc_intrinsic] -pub const fn copysignf32(x: f32, y: f32) -> f32; +pub const fn copysignf32(x: f32, y: f32) -> f32 { + f32::from_bits((x.to_bits() & !f32::SIGN_MASK) | (y.to_bits() & f32::SIGN_MASK)) +} /// Copies the sign from `y` to `x` for `f64` values. /// /// The stabilized version of this intrinsic is /// [`f64::copysign`](../../std/primitive.f64.html#method.copysign) +#[inline] #[rustc_nounwind] #[rustc_intrinsic_const_stable_indirect] #[rustc_intrinsic] -pub const fn copysignf64(x: f64, y: f64) -> f64; +pub const fn copysignf64(x: f64, y: f64) -> f64 { + f64::from_bits((x.to_bits() & !f64::SIGN_MASK) | (y.to_bits() & f64::SIGN_MASK)) +} /// Copies the sign from `y` to `x` for `f128` values. /// /// The stabilized version of this intrinsic is /// [`f128::copysign`](../../std/primitive.f128.html#method.copysign) +#[inline] #[rustc_nounwind] #[rustc_intrinsic] -pub const fn copysignf128(x: f128, y: f128) -> f128; +pub const fn copysignf128(x: f128, y: f128) -> f128 { + f128::from_bits((x.to_bits() & !f128::SIGN_MASK) | (y.to_bits() & f128::SIGN_MASK)) +} /// Generates the LLVM body for the automatic differentiation of `f` using Enzyme, /// with `df` as the derivative function and `args` as its arguments. @@ -3511,6 +3918,7 @@ pub const fn offload( f: F, workgroup_dim: [u32; 3], thread_dim: [u32; 3], + dyn_cache: u32, args: T, ) -> R; @@ -3554,7 +3962,7 @@ pub(crate) const fn miri_promise_symbolic_alignment(ptr: *const (), align: usize /// #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn va_arg(ap: &mut VaList<'_>) -> T; +pub const unsafe fn va_arg(ap: &mut VaList<'_>) -> T; /// Duplicates a variable argument list. The returned list is initially at the same position as /// the one in `src`, but can be advanced independently. @@ -3566,7 +3974,11 @@ pub unsafe fn va_arg(ap: &mut VaList<'_>) -> T; /// when a variable argument list is used incorrectly. #[rustc_intrinsic] #[rustc_nounwind] -pub fn va_copy<'f>(src: &VaList<'f>) -> VaList<'f> { +pub const fn va_copy<'f>(src: &VaList<'f>) -> VaList<'f> { + // This fallback body exploits the fact that our codegen backends all just use + // a plain memcpy to duplicate VaList. This assumption is wrong for Miri. + assert!(!cfg!(miri), "fallback body is incorrect under Miri"); + src.duplicate() } @@ -3585,7 +3997,7 @@ pub fn va_copy<'f>(src: &VaList<'f>) -> VaList<'f> { /// #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn va_end(ap: &mut VaList<'_>) { +pub const unsafe fn va_end(ap: &mut VaList<'_>) { /* deliberately does nothing */ } @@ -4270,3 +4682,16 @@ mod verify { status != AllocationStatus::Dangling && status != AllocationStatus::DeadObject } } + +/// Returns the return address of the caller function (after inlining) in a best-effort manner or a null pointer if it is not supported on the current backend. +/// Returning an accurate value is a quality-of-implementation concern, but no hard guarantees are +/// made about the return value: formally, the intrinsic non-deterministically returns +/// an arbitrary pointer without provenance. +/// +/// Note that unlike most intrinsics, this is safe to call. This is because it only finds the return address of the immediate caller, which is guaranteed to be possible. +/// Other forms of the corresponding gcc or llvm intrinsic (which can have wildly unpredictable results or even crash at runtime) are not exposed. +#[rustc_intrinsic] +#[rustc_nounwind] +pub fn return_address() -> *const () { + core::ptr::null() +} diff --git a/library/core/src/intrinsics/simd.rs b/library/core/src/intrinsics/simd/mod.rs similarity index 90% rename from library/core/src/intrinsics/simd.rs rename to library/core/src/intrinsics/simd/mod.rs index f70262c38ae50..e9488a6bdb263 100644 --- a/library/core/src/intrinsics/simd.rs +++ b/library/core/src/intrinsics/simd/mod.rs @@ -2,6 +2,8 @@ //! //! In this module, a "vector" is any `repr(simd)` type. +pub mod scalable; + use crate::marker::ConstParamTy; /// Inserts an element into a vector, returning the updated vector. @@ -62,6 +64,7 @@ pub const unsafe fn simd_splat(value: U) -> T; /// Adds two simd vectors elementwise. /// /// `T` must be a vector of integers or floats. +/// For integers, wrapping arithmetic is used. #[rustc_intrinsic] #[rustc_nounwind] pub const unsafe fn simd_add(x: T, y: T) -> T; @@ -69,6 +72,7 @@ pub const unsafe fn simd_add(x: T, y: T) -> T; /// Subtracts `rhs` from `lhs` elementwise. /// /// `T` must be a vector of integers or floats. +/// For integers, wrapping arithmetic is used. #[rustc_intrinsic] #[rustc_nounwind] pub const unsafe fn simd_sub(lhs: T, rhs: T) -> T; @@ -76,6 +80,7 @@ pub const unsafe fn simd_sub(lhs: T, rhs: T) -> T; /// Multiplies two simd vectors elementwise. /// /// `T` must be a vector of integers or floats. +/// For integers, wrapping arithmetic is used. #[rustc_intrinsic] #[rustc_nounwind] pub const unsafe fn simd_mul(x: T, y: T) -> T; @@ -104,13 +109,13 @@ pub const unsafe fn simd_rem(lhs: T, rhs: T) -> T; /// Shifts vector left elementwise, with UB on overflow. /// -/// Shifts `lhs` left by `rhs`, shifting in sign bits for signed types. +/// Shifts `lhs` left by `rhs`, shifting in zeros. /// /// `T` must be a vector of integers. /// /// # Safety /// -/// Each element of `rhs` must be less than `::BITS`. +/// Each element of `rhs` must be in `0..::BITS`. #[rustc_intrinsic] #[rustc_nounwind] pub const unsafe fn simd_shl(lhs: T, rhs: T) -> T; @@ -123,7 +128,7 @@ pub const unsafe fn simd_shl(lhs: T, rhs: T) -> T; /// /// # Safety /// -/// Each element of `rhs` must be less than `::BITS`. +/// Each element of `rhs` must be in `0..::BITS`. #[rustc_intrinsic] #[rustc_nounwind] pub const unsafe fn simd_shr(lhs: T, rhs: T) -> T; @@ -140,7 +145,7 @@ pub const unsafe fn simd_shr(lhs: T, rhs: T) -> T; /// /// # Safety /// -/// Each element of `shift` must be less than `::BITS`. +/// Each element of `shift` must be in `0..::BITS`. #[rustc_intrinsic] #[rustc_nounwind] pub const unsafe fn simd_funnel_shl(a: T, b: T, shift: T) -> T; @@ -157,11 +162,23 @@ pub const unsafe fn simd_funnel_shl(a: T, b: T, shift: T) -> T; /// /// # Safety /// -/// Each element of `shift` must be less than `::BITS`. +/// Each element of `shift` must be in `0..::BITS`. #[rustc_intrinsic] #[rustc_nounwind] pub const unsafe fn simd_funnel_shr(a: T, b: T, shift: T) -> T; +/// Compute the carry-less product. +/// +/// This is similar to long multiplication except that the carry is discarded. +/// +/// This operation can be used to model multiplication in `GF(2)[X]`, the polynomial +/// ring over `GF(2)`. +/// +/// `T` must be a vector of integers. +#[rustc_intrinsic] +#[rustc_nounwind] +pub unsafe fn simd_carryless_mul(a: T, b: T) -> T; + /// "And"s vectors elementwise. /// /// `T` must be a vector of integers. @@ -221,8 +238,7 @@ pub const unsafe fn simd_as(x: T) -> U; /// Negates a vector elementwise. /// /// `T` must be a vector of integers or floats. -/// -/// Rust panics for `-::Min` due to overflow, but it is not UB with this intrinsic. +/// For integers, wrapping arithmetic is used. #[rustc_intrinsic] #[rustc_nounwind] pub const unsafe fn simd_neg(x: T) -> T; @@ -238,19 +254,27 @@ pub const unsafe fn simd_fabs(x: T) -> T; /// /// `T` must be a vector of floating-point primitive types. /// -/// Follows IEEE-754 `minNum` semantics. +/// This behaves like IEEE 754-2019 minimumNumber, *except* that it does not order signed +/// zeros deterministically. In particular, for each vector lane: +/// If one of the arguments is NaN (quiet or signaling), then the other argument is returned. If +/// both arguments are NaN, returns NaN. If the inputs compare equal (such as for the case of `+0.0` +/// and `-0.0`), either input may be returned non-deterministically. #[rustc_intrinsic] #[rustc_nounwind] -pub const unsafe fn simd_fmin(x: T, y: T) -> T; +pub const unsafe fn simd_minimum_number_nsz(x: T, y: T) -> T; /// Returns the maximum of two vectors, elementwise. /// /// `T` must be a vector of floating-point primitive types. /// -/// Follows IEEE-754 `maxNum` semantics. +/// This behaves like IEEE 754-2019 maximumNumber, *except* that it does not order signed +/// zeros deterministically. In particular, for each vector lane: +/// If one of the arguments is NaN (quiet or signaling), then the other argument is returned. If +/// both arguments are NaN, returns NaN. If the inputs compare equal (such as for the case of `+0.0` +/// and `-0.0`), either input may be returned non-deterministically. #[rustc_intrinsic] #[rustc_nounwind] -pub const unsafe fn simd_fmax(x: T, y: T) -> T; +pub const unsafe fn simd_maximum_number_nsz(x: T, y: T) -> T; /// Tests elementwise equality of two vectors. /// @@ -347,8 +371,8 @@ pub const unsafe fn simd_shuffle(x: T, y: T, idx: U) -> V; /// `val`. /// /// # Safety -/// Unmasked values in `T` must be readable as if by `::read` (e.g. aligned to the element -/// type). +/// Each pointer in `ptr` whose corresponding value in `mask` is `!0` must be readable as if by +/// [`ptr::read`][crate::ptr::read] (e.g. aligned to the element type). /// /// `mask` must only contain `0` or `!0` values. #[rustc_intrinsic] @@ -371,8 +395,8 @@ pub const unsafe fn simd_gather(val: T, ptr: U, mask: V) -> T; /// (This is relevant in case two of the stores overlap.) /// /// # Safety -/// Unmasked values in `T` must be writeable as if by `::write` (e.g. aligned to the element -/// type). +/// Each pointer in `ptr` whose corresponding value in `mask` is `!0` must be writable as if by +/// [`ptr::write`][crate::ptr::write] (e.g. aligned to the element type). /// /// `mask` must only contain `0` or `!0` values. #[rustc_intrinsic] @@ -409,6 +433,9 @@ pub enum SimdAlign { /// # Safety /// `ptr` must be aligned according to the `ALIGN` parameter, see [`SimdAlign`] for details. /// +/// Each pointer offset from `ptr` whose corresponding value in `mask` is `!0` must be readable as if +/// by [`ptr::read`][crate::ptr::read]. +/// /// `mask` must only contain `0` or `!0` values. #[rustc_intrinsic] #[rustc_nounwind] @@ -431,6 +458,9 @@ pub const unsafe fn simd_masked_load(mask: V, p /// # Safety /// `ptr` must be aligned according to the `ALIGN` parameter, see [`SimdAlign`] for details. /// +/// Each pointer offset from `ptr` whose corresponding value in `mask` is `!0` must be writable as if +/// by [`ptr::write`][crate::ptr::write]. +/// /// `mask` must only contain `0` or `!0` values. #[rustc_intrinsic] #[rustc_nounwind] @@ -496,7 +526,7 @@ pub unsafe fn simd_reduce_mul_unordered(x: T) -> U; /// Checks if all mask values are true. /// -/// `T` must be a vector of integer primitive types. +/// `T` must be a vector of integers. /// /// # Safety /// `x` must contain only `0` or `!0`. @@ -506,7 +536,7 @@ pub const unsafe fn simd_reduce_all(x: T) -> bool; /// Checks if any mask value is true. /// -/// `T` must be a vector of integer primitive types. +/// `T` must be a vector of integers. /// /// # Safety /// `x` must contain only `0` or `!0`. @@ -516,29 +546,25 @@ pub const unsafe fn simd_reduce_any(x: T) -> bool; /// Returns the maximum element of a vector. /// -/// `T` must be a vector of integers or floats. +/// `T` must be a vector of integers. /// /// `U` must be the element type of `T`. -/// -/// For floating-point values, uses IEEE-754 `maxNum`. #[rustc_intrinsic] #[rustc_nounwind] pub const unsafe fn simd_reduce_max(x: T) -> U; /// Returns the minimum element of a vector. /// -/// `T` must be a vector of integers or floats. +/// `T` must be a vector of integers. /// /// `U` must be the element type of `T`. -/// -/// For floating-point values, uses IEEE-754 `minNum`. #[rustc_intrinsic] #[rustc_nounwind] pub const unsafe fn simd_reduce_min(x: T) -> U; /// Logical "and"s all elements together. /// -/// `T` must be a vector of integers or floats. +/// `T` must be a vector of integers. /// /// `U` must be the element type of `T`. #[rustc_intrinsic] @@ -547,7 +573,7 @@ pub const unsafe fn simd_reduce_and(x: T) -> U; /// Logical "ors" all elements together. /// -/// `T` must be a vector of integers or floats. +/// `T` must be a vector of integers. /// /// `U` must be the element type of `T`. #[rustc_intrinsic] @@ -556,7 +582,7 @@ pub const unsafe fn simd_reduce_or(x: T) -> U; /// Logical "exclusive ors" all elements together. /// -/// `T` must be a vector of integers or floats. +/// `T` must be a vector of integers. /// /// `U` must be the element type of `T`. #[rustc_intrinsic] diff --git a/library/core/src/intrinsics/simd/scalable.rs b/library/core/src/intrinsics/simd/scalable.rs new file mode 100644 index 0000000000000..a8984b3a2f7db --- /dev/null +++ b/library/core/src/intrinsics/simd/scalable.rs @@ -0,0 +1,66 @@ +//! Scalable vector compiler intrinsics. +//! +//! In this module, a "vector" is any `#[rustc_scalable_vector]`-annotated type. + +/// Create a tuple of two vectors. +/// +/// `SVecTup` must be a scalable vector tuple (`#[rustc_scalable_vector]`) and `SVec` must be a +/// scalable vector (`#[rustc_scalable_vector(N)]`). `SVecTup` must be a tuple of vectors of +/// type `SVec`. +/// +/// Corresponds to Clang's `__builtin_sve_svcreate2*` builtins. +#[rustc_nounwind] +#[rustc_intrinsic] +pub unsafe fn sve_tuple_create2(x0: SVec, x1: SVec) -> SVecTup; + +/// Create a tuple of three vectors. +/// +/// `SVecTup` must be a scalable vector tuple (`#[rustc_scalable_vector]`) and `SVec` must be a +/// scalable vector (`#[rustc_scalable_vector(N)]`). `SVecTup` must be a tuple of vectors of +/// type `SVec`. +/// +/// Corresponds to Clang's `__builtin_sve_svcreate3*` builtins. +#[rustc_intrinsic] +#[rustc_nounwind] +pub unsafe fn sve_tuple_create3(x0: SVec, x1: SVec, x2: SVec) -> SVecTup; + +/// Create a tuple of four vectors. +/// +/// `SVecTup` must be a scalable vector tuple (`#[rustc_scalable_vector]`) and `SVec` must be a +/// scalable vector (`#[rustc_scalable_vector(N)]`). `SVecTup` must be a tuple of vectors of +/// type `SVec`. +/// +/// Corresponds to Clang's `__builtin_sve_svcreate4*` builtins. +#[rustc_intrinsic] +#[rustc_nounwind] +pub unsafe fn sve_tuple_create4(x0: SVec, x1: SVec, x2: SVec, x3: SVec) -> SVecTup; + +/// Get one vector from a tuple of vectors. +/// +/// `SVecTup` must be a scalable vector tuple (`#[rustc_scalable_vector]`) and `SVec` must be a +/// scalable vector (`#[rustc_scalable_vector(N)]`). `SVecTup` must be a tuple of vectors of +/// type `SVec`. +/// +/// Corresponds to Clang's `__builtin_sve_svget*` builtins. +/// +/// # Safety +/// +/// `IDX` must be in-bounds of the tuple. +#[rustc_intrinsic] +#[rustc_nounwind] +pub unsafe fn sve_tuple_get(tuple: SVecTup) -> SVec; + +/// Change one vector in a tuple of vectors. +/// +/// `SVecTup` must be a scalable vector tuple (`#[rustc_scalable_vector]`) and `SVec` must be a +/// scalable vector (`#[rustc_scalable_vector(N)]`). `SVecTup` must be a tuple of vectors of +/// type `SVec`. +/// +/// Corresponds to Clang's `__builtin_sve_svset*` builtins. +/// +/// # Safety +/// +/// `IDX` must be in-bounds of the tuple. +#[rustc_intrinsic] +#[rustc_nounwind] +pub unsafe fn sve_tuple_set(tuple: SVecTup, x: SVec) -> SVecTup; diff --git a/library/core/src/io/borrowed_buf.rs b/library/core/src/io/borrowed_buf.rs index 088dea7812945..f2926f1ce7cf9 100644 --- a/library/core/src/io/borrowed_buf.rs +++ b/library/core/src/io/borrowed_buf.rs @@ -2,39 +2,38 @@ use crate::fmt::{self, Debug, Formatter}; use crate::mem::{self, MaybeUninit}; -use crate::{cmp, ptr}; -/// A borrowed byte buffer which is incrementally filled and initialized. +/// A borrowed buffer of initially uninitialized elements, which is incrementally filled. /// -/// This type is a sort of "double cursor". It tracks three regions in the buffer: a region at the beginning of the -/// buffer that has been logically filled with data, a region that has been initialized at some point but not yet -/// logically filled, and a region at the end that is fully uninitialized. The filled region is guaranteed to be a -/// subset of the initialized region. +/// This type makes it safer to work with `MaybeUninit` buffers, such as to read into a buffer +/// without having to initialize it first. It tracks the region of elements that have been filled +/// and whether the unfilled region was initialized. /// /// In summary, the contents of the buffer can be visualized as: /// ```not_rust -/// [ capacity ] -/// [ filled | unfilled ] -/// [ initialized | uninitialized ] +/// [ capacity ] +/// [ filled | unfilled (may be initialized) ] /// ``` /// -/// A `BorrowedBuf` is created around some existing data (or capacity for data) via a unique reference -/// (`&mut`). The `BorrowedBuf` can be configured (e.g., using `clear` or `set_init`), but cannot be -/// directly written. To write into the buffer, use `unfilled` to create a `BorrowedCursor`. The cursor -/// has write-only access to the unfilled portion of the buffer (you can think of it as a -/// write-only iterator). +/// A `BorrowedBuf` is created around some existing elements (or capacity for elements) via a unique +/// reference (`&mut`). The `BorrowedBuf` can be configured (e.g., using `clear` or `set_init`), but +/// cannot be directly written. To write into the buffer, use `unfilled` to create a +/// `BorrowedCursor`. The cursor has write-only access to the unfilled portion of the buffer (you +/// can think of it as a write-only iterator). /// -/// The lifetime `'data` is a bound on the lifetime of the underlying data. -pub struct BorrowedBuf<'data> { - /// The buffer's underlying data. - buf: &'data mut [MaybeUninit], - /// The length of `self.buf` which is known to be filled. +/// The lifetime `'data` is a bound on the lifetime of the underlying elements. +/// +/// The type is most commonly used to manage bytes, but can manage any type of elements. +pub struct BorrowedBuf<'data, T> { + /// The buffer's underlying elements. + buf: &'data mut [MaybeUninit], + /// The number of elements of `self.buf` that are known to be filled. filled: usize, - /// The length of `self.buf` which is known to be initialized. - init: usize, + /// Whether the entire unfilled part of `self.buf` has explicitly been initialized. + init: bool, } -impl Debug for BorrowedBuf<'_> { +impl Debug for BorrowedBuf<'_, T> { fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { f.debug_struct("BorrowedBuf") .field("init", &self.init) @@ -45,48 +44,42 @@ impl Debug for BorrowedBuf<'_> { } /// Creates a new `BorrowedBuf` from a fully initialized slice. -impl<'data> From<&'data mut [u8]> for BorrowedBuf<'data> { +impl<'data, T: Copy> From<&'data mut [T]> for BorrowedBuf<'data, T> { #[inline] - fn from(slice: &'data mut [u8]) -> BorrowedBuf<'data> { - let len = slice.len(); - + fn from(slice: &'data mut [T]) -> BorrowedBuf<'data, T> { BorrowedBuf { - // SAFETY: initialized data never becoming uninitialized is an invariant of BorrowedBuf - buf: unsafe { (slice as *mut [u8]).as_uninit_slice_mut().unwrap() }, + // SAFETY: no initialized element is ever uninitialized as per `BorrowedBuf`'s invariant + buf: unsafe { &mut *(slice as *mut [T] as *mut [MaybeUninit]) }, filled: 0, - init: len, + init: true, } } } /// Creates a new `BorrowedBuf` from an uninitialized buffer. -/// -/// Use `set_init` if part of the buffer is known to be already initialized. -impl<'data> From<&'data mut [MaybeUninit]> for BorrowedBuf<'data> { +impl<'data, T: Copy> From<&'data mut [MaybeUninit]> for BorrowedBuf<'data, T> { #[inline] - fn from(buf: &'data mut [MaybeUninit]) -> BorrowedBuf<'data> { - BorrowedBuf { buf, filled: 0, init: 0 } + fn from(buf: &'data mut [MaybeUninit]) -> BorrowedBuf<'data, T> { + BorrowedBuf { buf, filled: 0, init: false } } } /// Creates a new `BorrowedBuf` from a cursor. /// /// Use `BorrowedCursor::with_unfilled_buf` instead for a safer alternative. -impl<'data> From> for BorrowedBuf<'data> { +impl<'data, T: Copy> From> for BorrowedBuf<'data, T> { #[inline] - fn from(mut buf: BorrowedCursor<'data>) -> BorrowedBuf<'data> { - let init = buf.init_mut().len(); + fn from(buf: BorrowedCursor<'data, T>) -> BorrowedBuf<'data, T> { BorrowedBuf { - // SAFETY: no initialized byte is ever uninitialized as per - // `BorrowedBuf`'s invariant + // SAFETY: no initialized element is ever uninitialized as per `BorrowedBuf`'s invariant buf: unsafe { buf.buf.buf.get_unchecked_mut(buf.buf.filled..) }, filled: 0, - init, + init: buf.buf.init, } } } -impl<'data> BorrowedBuf<'data> { +impl<'data, T> BorrowedBuf<'data, T> { /// Returns the total capacity of the buffer. #[inline] pub fn capacity(&self) -> usize { @@ -99,15 +92,18 @@ impl<'data> BorrowedBuf<'data> { self.filled } - /// Returns the length of the initialized part of the buffer. + /// Returns `true` if the buffer is initialized. + #[unstable(feature = "borrowed_buf_init", issue = "160476")] #[inline] - pub fn init_len(&self) -> usize { + pub fn is_init(&self) -> bool { self.init } +} +impl<'data, T: Copy> BorrowedBuf<'data, T> { /// Returns a shared reference to the filled portion of the buffer. #[inline] - pub fn filled(&self) -> &[u8] { + pub fn filled(&self) -> &[T] { // SAFETY: We only slice the filled part of the buffer, which is always valid unsafe { let buf = self.buf.get_unchecked(..self.filled); @@ -117,7 +113,7 @@ impl<'data> BorrowedBuf<'data> { /// Returns a mutable reference to the filled portion of the buffer. #[inline] - pub fn filled_mut(&mut self) -> &mut [u8] { + pub fn filled_mut(&mut self) -> &mut [T] { // SAFETY: We only slice the filled part of the buffer, which is always valid unsafe { let buf = self.buf.get_unchecked_mut(..self.filled); @@ -127,7 +123,7 @@ impl<'data> BorrowedBuf<'data> { /// Returns a shared reference to the filled portion of the buffer with its original lifetime. #[inline] - pub fn into_filled(self) -> &'data [u8] { + pub fn into_filled(self) -> &'data [T] { // SAFETY: We only slice the filled part of the buffer, which is always valid unsafe { let buf = self.buf.get_unchecked(..self.filled); @@ -137,7 +133,7 @@ impl<'data> BorrowedBuf<'data> { /// Returns a mutable reference to the filled portion of the buffer with its original lifetime. #[inline] - pub fn into_filled_mut(self) -> &'data mut [u8] { + pub fn into_filled_mut(self) -> &'data mut [T] { // SAFETY: We only slice the filled part of the buffer, which is always valid unsafe { let buf = self.buf.get_unchecked_mut(..self.filled); @@ -147,77 +143,81 @@ impl<'data> BorrowedBuf<'data> { /// Returns a cursor over the unfilled part of the buffer. #[inline] - pub fn unfilled<'this>(&'this mut self) -> BorrowedCursor<'this> { + pub fn unfilled<'this>(&'this mut self) -> BorrowedCursor<'this, T> { BorrowedCursor { // SAFETY: we never assign into `BorrowedCursor::buf`, so treating its // lifetime covariantly is safe. buf: unsafe { - mem::transmute::<&'this mut BorrowedBuf<'data>, &'this mut BorrowedBuf<'this>>(self) + mem::transmute::<&'this mut BorrowedBuf<'data, T>, &'this mut BorrowedBuf<'this, T>>( + self, + ) }, } } /// Clears the buffer, resetting the filled region to empty. /// - /// The number of initialized bytes is not changed, and the contents of the buffer are not modified. + /// The contents of the buffer are not modified. #[inline] pub fn clear(&mut self) -> &mut Self { self.filled = 0; self } - /// Asserts that the first `n` bytes of the buffer are initialized. - /// - /// `BorrowedBuf` assumes that bytes are never de-initialized, so this method does nothing when called with fewer - /// bytes than are already known to be initialized. + /// Asserts that the unfilled part of the buffer is initialized. /// /// # Safety /// - /// The caller must ensure that the first `n` unfilled bytes of the buffer have already been initialized. + /// All the elements of the buffer must be initialized. + #[unstable(feature = "borrowed_buf_init", issue = "160476")] #[inline] - pub unsafe fn set_init(&mut self, n: usize) -> &mut Self { - self.init = cmp::max(self.init, n); + pub unsafe fn set_init(&mut self) -> &mut Self { + self.init = true; self } } /// A writeable view of the unfilled portion of a [`BorrowedBuf`]. /// -/// The unfilled portion consists of an initialized and an uninitialized part; see [`BorrowedBuf`] -/// for details. +/// The unfilled portion may be uninitialized; see [`BorrowedBuf`] for details. /// /// Data can be written directly to the cursor by using [`append`](BorrowedCursor::append) or /// indirectly by getting a slice of part or all of the cursor and writing into the slice. In the /// indirect case, the caller must call [`advance`](BorrowedCursor::advance) after writing to inform -/// the cursor how many bytes have been written. +/// the cursor how many elements have been written. /// -/// Once data is written to the cursor, it becomes part of the filled portion of the underlying -/// `BorrowedBuf` and can no longer be accessed or re-written by the cursor. I.e., the cursor tracks -/// the unfilled part of the underlying `BorrowedBuf`. +/// Once elements are written to the cursor, they become part of the filled portion of the +/// underlying `BorrowedBuf` and can no longer be accessed or re-written by the cursor. In other +/// words, the cursor tracks the unfilled part of the underlying `BorrowedBuf`. /// /// The lifetime `'a` is a bound on the lifetime of the underlying buffer (which means it is a bound -/// on the data in that buffer by transitivity). -#[derive(Debug)] -pub struct BorrowedCursor<'a> { +/// on the elements in that buffer by transitivity). +pub struct BorrowedCursor<'a, T> { /// The underlying buffer. // Safety invariant: we treat the type of buf as covariant in the lifetime of `BorrowedBuf` when // we create a `BorrowedCursor`. This is only safe if we never replace `buf` by assigning into // it, so don't do that! - buf: &'a mut BorrowedBuf<'a>, + buf: &'a mut BorrowedBuf<'a, T>, } -impl<'a> BorrowedCursor<'a> { +impl Debug for BorrowedCursor<'_, T> { + fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { + f.debug_struct("BorrowedCursor").field("buf", &self.buf).finish() + } +} + +impl<'a, T: Copy> BorrowedCursor<'a, T> { /// Reborrows this cursor by cloning it with a smaller lifetime. /// /// Since a cursor maintains unique access to its underlying buffer, the borrowed cursor is /// not accessible while the new cursor exists. #[inline] - pub fn reborrow<'this>(&'this mut self) -> BorrowedCursor<'this> { + pub fn reborrow<'this>(&'this mut self) -> BorrowedCursor<'this, T> { BorrowedCursor { // SAFETY: we never assign into `BorrowedCursor::buf`, so treating its // lifetime covariantly is safe. buf: unsafe { - mem::transmute::<&'this mut BorrowedBuf<'a>, &'this mut BorrowedBuf<'this>>( + mem::transmute::<&'this mut BorrowedBuf<'a, T>, &'this mut BorrowedBuf<'this, T>>( self.buf, ) }, @@ -230,7 +230,7 @@ impl<'a> BorrowedCursor<'a> { self.buf.capacity() - self.buf.filled } - /// Returns the number of bytes written to the `BorrowedBuf` this cursor was created from. + /// Returns the number of elements written to the `BorrowedBuf` this cursor was created from. /// /// In particular, the count returned is shared by all reborrows of the cursor. #[inline] @@ -238,102 +238,80 @@ impl<'a> BorrowedCursor<'a> { self.buf.filled } - /// Returns a mutable reference to the initialized portion of the cursor. + /// Returns `true` if the buffer is initialized. + #[unstable(feature = "borrowed_buf_init", issue = "160476")] #[inline] - pub fn init_mut(&mut self) -> &mut [u8] { - // SAFETY: We only slice the initialized part of the buffer, which is always valid - unsafe { - let buf = self.buf.buf.get_unchecked_mut(self.buf.filled..self.buf.init); - buf.assume_init_mut() - } + pub fn is_init(&self) -> bool { + self.buf.init + } + + /// Set the buffer as fully initialized. + /// + /// # Safety + /// + /// All the elements of the cursor must be initialized. + #[unstable(feature = "borrowed_buf_init", issue = "160476")] + #[inline] + pub unsafe fn set_init(&mut self) { + self.buf.init = true; } /// Returns a mutable reference to the whole cursor. /// /// # Safety /// - /// The caller must not uninitialize any bytes in the initialized portion of the cursor. + /// The caller must not uninitialize any elements of the cursor if it is initialized. #[inline] - pub unsafe fn as_mut(&mut self) -> &mut [MaybeUninit] { + pub unsafe fn as_mut(&mut self) -> &mut [MaybeUninit] { // SAFETY: always in bounds unsafe { self.buf.buf.get_unchecked_mut(self.buf.filled..) } } - /// Advances the cursor by asserting that `n` bytes have been filled. + /// Advances the cursor by asserting that `n` elements have been filled. /// - /// After advancing, the `n` bytes are no longer accessible via the cursor and can only be + /// After advancing, the `n` elements are no longer accessible via the cursor and can only be /// accessed via the underlying buffer. I.e., the buffer's filled portion grows by `n` elements /// and its unfilled portion (and the capacity of this cursor) shrinks by `n` elements. /// - /// If less than `n` bytes initialized (by the cursor's point of view), `set_init` should be + /// If less than `n` elements initialized (by the cursor's point of view), `set_init` should be /// called first. /// /// # Panics /// - /// Panics if there are less than `n` bytes initialized. + /// Panics if there are less than `n` elements initialized. + #[unstable(feature = "borrowed_buf_init", issue = "160476")] #[inline] - pub fn advance(&mut self, n: usize) -> &mut Self { + pub fn advance_checked(&mut self, n: usize) -> &mut Self { // The subtraction cannot underflow by invariant of this type. - assert!(n <= self.buf.init - self.buf.filled); + let init_unfilled = if self.buf.init { self.buf.buf.len() - self.buf.filled } else { 0 }; + assert!(n <= init_unfilled); self.buf.filled += n; self } - /// Advances the cursor by asserting that `n` bytes have been filled. + /// Advances the cursor by asserting that `n` elements have been filled. /// - /// After advancing, the `n` bytes are no longer accessible via the cursor and can only be + /// After advancing, the `n` elements are no longer accessible via the cursor and can only be /// accessed via the underlying buffer. I.e., the buffer's filled portion grows by `n` elements /// and its unfilled portion (and the capacity of this cursor) shrinks by `n` elements. /// /// # Safety /// - /// The caller must ensure that the first `n` bytes of the cursor have been properly - /// initialised. + /// The caller must ensure that the first `n` elements of the cursor have been initialized. #[inline] - pub unsafe fn advance_unchecked(&mut self, n: usize) -> &mut Self { + pub unsafe fn advance(&mut self, n: usize) -> &mut Self { self.buf.filled += n; - self.buf.init = cmp::max(self.buf.init, self.buf.filled); - self - } - - /// Initializes all bytes in the cursor. - #[inline] - pub fn ensure_init(&mut self) -> &mut Self { - // SAFETY: always in bounds and we never uninitialize these bytes. - let uninit = unsafe { self.buf.buf.get_unchecked_mut(self.buf.init..) }; - - // SAFETY: 0 is a valid value for MaybeUninit and the length matches the allocation - // since it is comes from a slice reference. - unsafe { - ptr::write_bytes(uninit.as_mut_ptr(), 0, uninit.len()); - } - self.buf.init = self.buf.capacity(); - - self - } - - /// Asserts that the first `n` unfilled bytes of the cursor are initialized. - /// - /// `BorrowedBuf` assumes that bytes are never de-initialized, so this method does nothing when - /// called with fewer bytes than are already known to be initialized. - /// - /// # Safety - /// - /// The caller must ensure that the first `n` bytes of the buffer have already been initialized. - #[inline] - pub unsafe fn set_init(&mut self, n: usize) -> &mut Self { - self.buf.init = cmp::max(self.buf.init, self.buf.filled + n); self } - /// Appends data to the cursor, advancing position within its buffer. + /// Append elements to the cursor, advancing position within its buffer. /// /// # Panics /// /// Panics if `self.capacity()` is less than `buf.len()`. #[inline] - pub fn append(&mut self, buf: &[u8]) { + pub fn append(&mut self, buf: &[T]) { assert!(self.capacity() >= buf.len()); // SAFETY: we do not de-initialize any of the elements of the slice @@ -341,10 +319,6 @@ impl<'a> BorrowedCursor<'a> { self.as_mut()[..buf.len()].write_copy_of_slice(buf); } - // SAFETY: We just added the entire contents of buf to the filled section. - unsafe { - self.set_init(buf.len()); - } self.buf.filled += buf.len(); } @@ -357,15 +331,15 @@ impl<'a> BorrowedCursor<'a> { /// /// Panics if the `BorrowedBuf` given to the closure is replaced by another /// one. - pub fn with_unfilled_buf(&mut self, f: impl FnOnce(&mut BorrowedBuf<'_>) -> T) -> T { + pub fn with_unfilled_buf(&mut self, f: impl FnOnce(&mut BorrowedBuf<'_, T>) -> R) -> R { let mut buf = BorrowedBuf::from(self.reborrow()); let prev_ptr = buf.buf as *const _; let res = f(&mut buf); // Check that the caller didn't replace the `BorrowedBuf`. // This is necessary for the safety of the code below: if the check wasn't - // there, one could mark some bytes as initialized even though there aren't. - assert!(core::ptr::addr_eq(prev_ptr, buf.buf)); + // there, one could mark some elements as initialized even though they aren't. + assert!(core::ptr::eq(prev_ptr, buf.buf)); let filled = buf.filled; let init = buf.init; @@ -373,12 +347,30 @@ impl<'a> BorrowedCursor<'a> { // Update `init` and `filled` fields with what was written to the buffer. // `self.buf.filled` was the starting length of the `BorrowedBuf`. // - // SAFETY: These amounts of bytes were initialized/filled in the `BorrowedBuf`, - // and therefore they are initialized/filled in the cursor too, because the - // buffer wasn't replaced. - self.buf.init = self.buf.filled + init; + // SAFETY: These elements were initialized/filled in the `BorrowedBuf`, and therefore they + // are initialized/filled in the cursor too, because the buffer wasn't replaced. + self.buf.init = init; self.buf.filled += filled; res } } + +impl<'a, T: Default + Copy> BorrowedCursor<'a, T> { + /// Initializes all elements in the cursor with their default value and + /// returns them. + #[unstable(feature = "borrowed_buf_init", issue = "160476")] + #[inline] + pub fn ensure_init(&mut self) -> &mut [T] { + // SAFETY: always in bounds and we never uninitialize these elements. + let unfilled = unsafe { self.buf.buf.get_unchecked_mut(self.buf.filled..) }; + + if !self.buf.init { + unfilled.write_default(); + self.buf.init = true; + } + + // SAFETY: these elements have just been initialized if they weren't before + unsafe { unfilled.assume_init_mut() } + } +} diff --git a/library/std/src/io/cursor.rs b/library/core/src/io/cursor.rs similarity index 52% rename from library/std/src/io/cursor.rs rename to library/core/src/io/cursor.rs index d7131e2fe92fd..704900f9c590e 100644 --- a/library/std/src/io/cursor.rs +++ b/library/core/src/io/cursor.rs @@ -1,10 +1,5 @@ -#[cfg(test)] -mod tests; - -use crate::alloc::Allocator; use crate::cmp; -use crate::io::prelude::*; -use crate::io::{self, BorrowedCursor, ErrorKind, IoSlice, IoSliceMut, SeekFrom}; +use crate::io::{self, ErrorKind, IoSlice, SeekFrom, Write}; /// A `Cursor` wraps an in-memory buffer and provides it with a /// [`Seek`] implementation. @@ -24,8 +19,13 @@ use crate::io::{self, BorrowedCursor, ErrorKind, IoSlice, IoSliceMut, SeekFrom}; /// code, but use an in-memory buffer in our tests. We can do this with /// `Cursor`: /// +// FIXME(#74481): Hard-links required to link from `core` to `std` /// [bytes]: crate::slice "slice" -/// [`File`]: crate::fs::File +/// [`File`]: ../../std/fs/struct.File.html +/// [`Read`]: ../../std/io/trait.Read.html +/// [`Write`]: crate::io::Write +/// [`Seek`]: crate::io::Seek +/// [Vec]: ../../alloc/vec/struct.Vec.html /// /// ```no_run /// use std::io::prelude::*; @@ -84,6 +84,9 @@ impl Cursor { /// is not empty. So writing to cursor starts with overwriting [`Vec`] /// content, not with appending to it. /// + // FIXME(#74481): Hard-links required to link from `core` to `alloc` + /// [`Vec`]: ../../alloc/vec/struct.Vec.html + /// /// # Examples /// /// ``` @@ -205,6 +208,13 @@ impl Cursor { pub const fn set_position(&mut self, pos: u64) { self.pos = pos; } + + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + #[inline] + pub const fn into_parts_mut(&mut self) -> (&mut u64, &mut T) { + (&mut self.pos, &mut self.inner) + } } impl Cursor @@ -285,145 +295,26 @@ where } } -#[stable(feature = "rust1", since = "1.0.0")] -impl io::Seek for Cursor -where - T: AsRef<[u8]>, -{ - fn seek(&mut self, style: SeekFrom) -> io::Result { - let (base_pos, offset) = match style { - SeekFrom::Start(n) => { - self.pos = n; - return Ok(n); - } - SeekFrom::End(n) => (self.inner.as_ref().len() as u64, n), - SeekFrom::Current(n) => (self.pos, n), - }; - match base_pos.checked_add_signed(offset) { - Some(n) => { - self.pos = n; - Ok(self.pos) - } - None => Err(io::const_error!( - ErrorKind::InvalidInput, - "invalid seek to a negative or overflowing position", - )), - } - } - - fn stream_len(&mut self) -> io::Result { - Ok(self.inner.as_ref().len() as u64) - } - - fn stream_position(&mut self) -> io::Result { - Ok(self.pos) - } -} - -#[stable(feature = "rust1", since = "1.0.0")] -impl Read for Cursor -where - T: AsRef<[u8]>, -{ - fn read(&mut self, buf: &mut [u8]) -> io::Result { - let n = Read::read(&mut Cursor::split(self).1, buf)?; - self.pos += n as u64; - Ok(n) - } - - fn read_buf(&mut self, mut cursor: BorrowedCursor<'_>) -> io::Result<()> { - let prev_written = cursor.written(); - - Read::read_buf(&mut Cursor::split(self).1, cursor.reborrow())?; - - self.pos += (cursor.written() - prev_written) as u64; - - Ok(()) - } - - fn read_vectored(&mut self, bufs: &mut [IoSliceMut<'_>]) -> io::Result { - let mut nread = 0; - for buf in bufs { - let n = self.read(buf)?; - nread += n; - if n < buf.len() { - break; - } - } - Ok(nread) - } - - fn is_read_vectored(&self) -> bool { - true - } - - fn read_exact(&mut self, buf: &mut [u8]) -> io::Result<()> { - let result = Read::read_exact(&mut Cursor::split(self).1, buf); - - match result { - Ok(_) => self.pos += buf.len() as u64, - // The only possible error condition is EOF, so place the cursor at "EOF" - Err(_) => self.pos = self.inner.as_ref().len() as u64, - } - - result - } - - fn read_buf_exact(&mut self, mut cursor: BorrowedCursor<'_>) -> io::Result<()> { - let prev_written = cursor.written(); - - let result = Read::read_buf_exact(&mut Cursor::split(self).1, cursor.reborrow()); - self.pos += (cursor.written() - prev_written) as u64; - - result - } - - fn read_to_end(&mut self, buf: &mut Vec) -> io::Result { - let content = Cursor::split(self).1; - let len = content.len(); - buf.try_reserve(len)?; - buf.extend_from_slice(content); - self.pos += len as u64; - - Ok(len) - } - - fn read_to_string(&mut self, buf: &mut String) -> io::Result { - let content = - crate::str::from_utf8(Cursor::split(self).1).map_err(|_| io::Error::INVALID_UTF8)?; - let len = content.len(); - buf.try_reserve(len)?; - buf.push_str(content); - self.pos += len as u64; - - Ok(len) - } -} - -#[stable(feature = "rust1", since = "1.0.0")] -impl BufRead for Cursor -where - T: AsRef<[u8]>, -{ - fn fill_buf(&mut self) -> io::Result<&[u8]> { - Ok(Cursor::split(self).1) - } - fn consume(&mut self, amt: usize) { - self.pos += amt as u64; - } -} - -// Non-resizing write implementation +/// Non-resizing [`Write::write`] implementation for slices. +/// Exported for `Cursor>`'s implementation of [`Write`]. #[inline] -fn slice_write(pos_mut: &mut u64, slice: &mut [u8], buf: &[u8]) -> io::Result { +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +pub fn slice_write(pos_mut: &mut u64, slice: &mut [u8], buf: &[u8]) -> io::Result { let pos = cmp::min(*pos_mut, slice.len() as u64); - let amt = (&mut slice[(pos as usize)..]).write(buf)?; + let dst = &mut slice[(pos as usize)..]; + let amt = cmp::min(buf.len(), dst.len()); + dst[..amt].copy_from_slice(&buf[..amt]); *pos_mut += amt as u64; Ok(amt) } +/// Non-resizing [`Write::write_vectored`] implementation for slices. +/// Exported for `Cursor>`'s implementation of [`Write`]. #[inline] -fn slice_write_vectored( +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +pub fn slice_write_vectored( pos_mut: &mut u64, slice: &mut [u8], bufs: &[IoSlice<'_>], @@ -439,14 +330,22 @@ fn slice_write_vectored( Ok(nwritten) } +/// Non-resizing [`Write::write_all`] implementation for slices. +/// Exported for `Cursor>`'s implementation of [`Write`]. #[inline] -fn slice_write_all(pos_mut: &mut u64, slice: &mut [u8], buf: &[u8]) -> io::Result<()> { +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +pub fn slice_write_all(pos_mut: &mut u64, slice: &mut [u8], buf: &[u8]) -> io::Result<()> { let n = slice_write(pos_mut, slice, buf)?; if n < buf.len() { Err(io::Error::WRITE_ALL_EOF) } else { Ok(()) } } +/// Non-resizing [`Write::write_all_vectored`] implementation for slices. +/// Exported for `Cursor>`'s implementation of [`Write`]. #[inline] -fn slice_write_all_vectored( +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +pub fn slice_write_all_vectored( pos_mut: &mut u64, slice: &mut [u8], bufs: &[IoSlice<'_>], @@ -460,142 +359,18 @@ fn slice_write_all_vectored( Ok(()) } -/// Reserves the required space, and pads the vec with 0s if necessary. -fn reserve_and_pad( - pos_mut: &mut u64, - vec: &mut Vec, - buf_len: usize, -) -> io::Result { - let pos: usize = (*pos_mut).try_into().map_err(|_| { - io::const_error!( - ErrorKind::InvalidInput, - "cursor position exceeds maximum possible vector length", - ) - })?; - - // For safety reasons, we don't want these numbers to overflow - // otherwise our allocation won't be enough - let desired_cap = pos.saturating_add(buf_len); - if desired_cap > vec.capacity() { - // We want our vec's total capacity - // to have room for (pos+buf_len) bytes. Reserve allocates - // based on additional elements from the length, so we need to - // reserve the difference - vec.reserve(desired_cap - vec.len()); - } - // Pad if pos is above the current len. - if pos > vec.len() { - let diff = pos - vec.len(); - // Unfortunately, `resize()` would suffice but the optimiser does not - // realise the `reserve` it does can be eliminated. So we do it manually - // to eliminate that extra branch - let spare = vec.spare_capacity_mut(); - debug_assert!(spare.len() >= diff); - // Safety: we have allocated enough capacity for this. - // And we are only writing, not reading - unsafe { - spare.get_unchecked_mut(..diff).fill(core::mem::MaybeUninit::new(0)); - vec.set_len(pos); - } - } - - Ok(pos) -} - -/// Writes the slice to the vec without allocating. -/// -/// # Safety -/// -/// `vec` must have `buf.len()` spare capacity. -unsafe fn vec_write_all_unchecked(pos: usize, vec: &mut Vec, buf: &[u8]) -> usize -where - A: Allocator, -{ - debug_assert!(vec.capacity() >= pos + buf.len()); - unsafe { vec.as_mut_ptr().add(pos).copy_from(buf.as_ptr(), buf.len()) }; - pos + buf.len() -} - -/// Resizing `write_all` implementation for [`Cursor`]. -/// -/// Cursor is allowed to have a pre-allocated and initialised -/// vector body, but with a position of 0. This means the [`Write`] -/// will overwrite the contents of the vec. -/// -/// This also allows for the vec body to be empty, but with a position of N. -/// This means that [`Write`] will pad the vec with 0 initially, -/// before writing anything from that point -fn vec_write_all(pos_mut: &mut u64, vec: &mut Vec, buf: &[u8]) -> io::Result -where - A: Allocator, -{ - let buf_len = buf.len(); - let mut pos = reserve_and_pad(pos_mut, vec, buf_len)?; - - // Write the buf then progress the vec forward if necessary - // Safety: we have ensured that the capacity is available - // and that all bytes get written up to pos - unsafe { - pos = vec_write_all_unchecked(pos, vec, buf); - if pos > vec.len() { - vec.set_len(pos); - } - }; - - // Bump us forward - *pos_mut += buf_len as u64; - Ok(buf_len) -} - -/// Resizing `write_all_vectored` implementation for [`Cursor`]. -/// -/// Cursor is allowed to have a pre-allocated and initialised -/// vector body, but with a position of 0. This means the [`Write`] -/// will overwrite the contents of the vec. -/// -/// This also allows for the vec body to be empty, but with a position of N. -/// This means that [`Write`] will pad the vec with 0 initially, -/// before writing anything from that point -fn vec_write_all_vectored( - pos_mut: &mut u64, - vec: &mut Vec, - bufs: &[IoSlice<'_>], -) -> io::Result -where - A: Allocator, -{ - // For safety reasons, we don't want this sum to overflow ever. - // If this saturates, the reserve should panic to avoid any unsound writing. - let buf_len = bufs.iter().fold(0usize, |a, b| a.saturating_add(b.len())); - let mut pos = reserve_and_pad(pos_mut, vec, buf_len)?; - - // Write the buf then progress the vec forward if necessary - // Safety: we have ensured that the capacity is available - // and that all bytes get written up to the last pos - unsafe { - for buf in bufs { - pos = vec_write_all_unchecked(pos, vec, buf); - } - if pos > vec.len() { - vec.set_len(pos); - } - } - - // Bump us forward - *pos_mut += buf_len as u64; - Ok(buf_len) -} - #[stable(feature = "rust1", since = "1.0.0")] impl Write for Cursor<&mut [u8]> { #[inline] fn write(&mut self, buf: &[u8]) -> io::Result { - slice_write(&mut self.pos, self.inner, buf) + let (pos, inner) = self.into_parts_mut(); + slice_write(pos, inner, buf) } #[inline] fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { - slice_write_vectored(&mut self.pos, self.inner, bufs) + let (pos, inner) = self.into_parts_mut(); + slice_write_vectored(pos, inner, bufs) } #[inline] @@ -605,12 +380,14 @@ impl Write for Cursor<&mut [u8]> { #[inline] fn write_all(&mut self, buf: &[u8]) -> io::Result<()> { - slice_write_all(&mut self.pos, self.inner, buf) + let (pos, inner) = self.into_parts_mut(); + slice_write_all(pos, inner, buf) } #[inline] fn write_all_vectored(&mut self, bufs: &mut [IoSlice<'_>]) -> io::Result<()> { - slice_write_all_vectored(&mut self.pos, self.inner, bufs) + let (pos, inner) = self.into_parts_mut(); + slice_write_all_vectored(pos, inner, bufs) } #[inline] @@ -619,17 +396,18 @@ impl Write for Cursor<&mut [u8]> { } } -#[stable(feature = "cursor_mut_vec", since = "1.25.0")] -impl Write for Cursor<&mut Vec> -where - A: Allocator, -{ +#[stable(feature = "cursor_array", since = "1.61.0")] +impl Write for Cursor<[u8; N]> { + #[inline] fn write(&mut self, buf: &[u8]) -> io::Result { - vec_write_all(&mut self.pos, self.inner, buf) + let (pos, inner) = self.into_parts_mut(); + slice_write(pos, inner, buf) } + #[inline] fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { - vec_write_all_vectored(&mut self.pos, self.inner, bufs) + let (pos, inner) = self.into_parts_mut(); + slice_write_vectored(pos, inner, bufs) } #[inline] @@ -637,14 +415,16 @@ where true } + #[inline] fn write_all(&mut self, buf: &[u8]) -> io::Result<()> { - vec_write_all(&mut self.pos, self.inner, buf)?; - Ok(()) + let (pos, inner) = self.into_parts_mut(); + slice_write_all(pos, inner, buf) } + #[inline] fn write_all_vectored(&mut self, bufs: &mut [IoSlice<'_>]) -> io::Result<()> { - vec_write_all_vectored(&mut self.pos, self.inner, bufs)?; - Ok(()) + let (pos, inner) = self.into_parts_mut(); + slice_write_all_vectored(pos, inner, bufs) } #[inline] @@ -654,104 +434,87 @@ where } #[stable(feature = "rust1", since = "1.0.0")] -impl Write for Cursor> +impl io::Seek for Cursor where - A: Allocator, + T: AsRef<[u8]>, { - fn write(&mut self, buf: &[u8]) -> io::Result { - vec_write_all(&mut self.pos, &mut self.inner, buf) - } - - fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { - vec_write_all_vectored(&mut self.pos, &mut self.inner, bufs) - } - - #[inline] - fn is_write_vectored(&self) -> bool { - true - } - - fn write_all(&mut self, buf: &[u8]) -> io::Result<()> { - vec_write_all(&mut self.pos, &mut self.inner, buf)?; - Ok(()) + fn seek(&mut self, style: SeekFrom) -> io::Result { + let (base_pos, offset) = match style { + SeekFrom::Start(n) => { + self.set_position(n); + return Ok(n); + } + SeekFrom::End(n) => (self.get_ref().as_ref().len() as u64, n), + SeekFrom::Current(n) => (self.position(), n), + }; + match base_pos.checked_add_signed(offset) { + Some(n) => { + self.set_position(n); + Ok(n) + } + None => Err(io::const_error!( + ErrorKind::InvalidInput, + "invalid seek to a negative or overflowing position", + )), + } } - fn write_all_vectored(&mut self, bufs: &mut [IoSlice<'_>]) -> io::Result<()> { - vec_write_all_vectored(&mut self.pos, &mut self.inner, bufs)?; - Ok(()) + fn stream_len(&mut self) -> io::Result { + Ok(self.get_ref().as_ref().len() as u64) } - #[inline] - fn flush(&mut self) -> io::Result<()> { - Ok(()) + fn stream_position(&mut self) -> io::Result { + Ok(self.position()) } } -#[stable(feature = "cursor_box_slice", since = "1.5.0")] -impl Write for Cursor> -where - A: Allocator, -{ - #[inline] - fn write(&mut self, buf: &[u8]) -> io::Result { - slice_write(&mut self.pos, &mut self.inner, buf) - } - - #[inline] - fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { - slice_write_vectored(&mut self.pos, &mut self.inner, bufs) - } - - #[inline] - fn is_write_vectored(&self) -> bool { - true - } - - #[inline] - fn write_all(&mut self, buf: &[u8]) -> io::Result<()> { - slice_write_all(&mut self.pos, &mut self.inner, buf) - } - - #[inline] - fn write_all_vectored(&mut self, bufs: &mut [IoSlice<'_>]) -> io::Result<()> { - slice_write_all_vectored(&mut self.pos, &mut self.inner, bufs) - } - - #[inline] - fn flush(&mut self) -> io::Result<()> { - Ok(()) - } +/// Trait used to allow indirect implementation of `Write` for `Cursor`. +/// Since [`Cursor`] is not a foundational type, it is not possible to implement +/// `Write` for `Cursor` if `Write` is defined in `libcore` and `T` is in a +/// downstream crate (e.g., `liballoc` or `libstd`). +/// +/// Methods are identical in purpose and meaning to their `Write` namesakes. +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +pub trait WriteThroughCursor: Sized { + fn write(this: &mut Cursor, buf: &[u8]) -> io::Result; + fn write_vectored(this: &mut Cursor, bufs: &[IoSlice<'_>]) -> io::Result; + fn is_write_vectored(this: &Cursor) -> bool; + fn write_all(this: &mut Cursor, buf: &[u8]) -> io::Result<()>; + fn write_all_vectored(this: &mut Cursor, bufs: &mut [IoSlice<'_>]) -> io::Result<()>; + fn flush(this: &mut Cursor) -> io::Result<()>; } -#[stable(feature = "cursor_array", since = "1.61.0")] -impl Write for Cursor<[u8; N]> { +#[doc(hidden)] +#[stable(feature = "rust1", since = "1.0.0")] +impl Write for Cursor { #[inline] fn write(&mut self, buf: &[u8]) -> io::Result { - slice_write(&mut self.pos, &mut self.inner, buf) + WriteThroughCursor::write(self, buf) } #[inline] fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { - slice_write_vectored(&mut self.pos, &mut self.inner, bufs) + WriteThroughCursor::write_vectored(self, bufs) } #[inline] fn is_write_vectored(&self) -> bool { - true + WriteThroughCursor::is_write_vectored(self) } #[inline] fn write_all(&mut self, buf: &[u8]) -> io::Result<()> { - slice_write_all(&mut self.pos, &mut self.inner, buf) + WriteThroughCursor::write_all(self, buf) } #[inline] fn write_all_vectored(&mut self, bufs: &mut [IoSlice<'_>]) -> io::Result<()> { - slice_write_all_vectored(&mut self.pos, &mut self.inner, bufs) + WriteThroughCursor::write_all_vectored(self, bufs) } #[inline] fn flush(&mut self) -> io::Result<()> { - Ok(()) + WriteThroughCursor::flush(self) } } diff --git a/library/core/src/io/error.rs b/library/core/src/io/error.rs new file mode 100644 index 0000000000000..8491a42537092 --- /dev/null +++ b/library/core/src/io/error.rs @@ -0,0 +1,1143 @@ +#![unstable(feature = "core_io", issue = "154046")] + +// On 64-bit platforms, `io::Error` may use a bit-packed representation to +// reduce size. However, this representation assumes that error codes are +// always 32-bit wide. +// +// This assumption is invalid on 64-bit UEFI, where error codes are 64-bit. +// Therefore, the packed representation is explicitly disabled for UEFI +// targets, and the unpacked representation must be used instead. +#[cfg_attr( + all(target_pointer_width = "64", not(target_os = "uefi")), + path = "error/repr_bitpacked.rs" +)] +#[cfg_attr( + not(all(target_pointer_width = "64", not(target_os = "uefi"))), + path = "error/repr_unpacked.rs" +)] +mod repr; + +#[cfg_attr( + all(target_has_atomic_load_store = "ptr", not(no_io_statics)), + path = "error/os_functions_atomic.rs" +)] +#[cfg_attr( + not(all(target_has_atomic_load_store = "ptr", not(no_io_statics))), + path = "error/os_functions.rs" +)] +mod os_functions; + +use self::os_functions::{decode_error_kind, format_os_error, is_interrupted, set_functions}; +use self::repr::Repr; +use crate::ptr::NonNull; +use crate::{error, fmt, mem, result}; + +/// A specialized [`Result`] type for I/O operations. +/// +/// This type is broadly used across [`std::io`] for any operation which may +/// produce an error. +/// +/// This type alias is generally used to avoid writing out [`io::Error`] directly and +/// is otherwise a direct mapping to [`Result`]. +/// +/// While usual Rust style is to import types directly, aliases of [`Result`] +/// often are not, to make it easier to distinguish between them. [`Result`] is +/// generally assumed to be [`core::result::Result`][`Result`], and so users of this alias +/// will generally use `io::Result` instead of shadowing the [prelude]'s import +/// of [`core::result::Result`][`Result`]. +/// +// FIXME(#74481): Hard-links required to link from `core` to `std` +/// [`std::io`]: ../../std/io/index.html +/// [`io::Error`]: Error +/// [`Result`]: crate::result::Result +/// [prelude]: crate::prelude +/// +/// # Examples +/// +/// A convenience function that bubbles an `io::Result` to its caller: +/// +/// ``` +/// use std::io; +/// +/// fn get_string() -> io::Result { +/// let mut buffer = String::new(); +/// +/// io::stdin().read_line(&mut buffer)?; +/// +/// Ok(buffer) +/// } +/// ``` +#[stable(feature = "rust1", since = "1.0.0")] +#[doc(search_unbox)] +pub type Result = result::Result; + +/// The error type for I/O operations of the [`Read`][Read], [`Write`][Write], [`Seek`][Seek], and +/// associated traits. +/// +/// Errors mostly originate from the underlying OS, but custom instances of +/// `Error` can be created with crafted error messages and a particular value of +/// [`ErrorKind`]. +/// +// FIXME(#74481): Hard-links required to link from `core` to `std` +/// [Read]: ../../std/io/trait.Read.html +/// [Write]: crate::io::Write +/// [Seek]: crate::io::Seek +#[stable(feature = "rust1", since = "1.0.0")] +#[rustc_has_incoherent_inherent_impls] +pub struct Error { + repr: Repr, +} + +#[stable(feature = "rust1", since = "1.0.0")] +impl fmt::Debug for Error { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + fmt::Debug::fmt(&self.repr, f) + } +} + +/// Common errors constants for use in std +#[doc(hidden)] +impl Error { + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub const INVALID_UTF8: Self = + const_error!(ErrorKind::InvalidData, "stream did not contain valid UTF-8"); + + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub const READ_EXACT_EOF: Self = + const_error!(ErrorKind::UnexpectedEof, "failed to fill whole buffer"); + + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub const UNKNOWN_THREAD_COUNT: Self = const_error!( + ErrorKind::NotFound, + "the number of hardware threads is not known for the target platform", + ); + + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub const UNSUPPORTED_PLATFORM: Self = + const_error!(ErrorKind::Unsupported, "operation not supported on this platform"); + + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub const WRITE_ALL_EOF: Self = + const_error!(ErrorKind::WriteZero, "failed to write whole buffer"); + + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub const ZERO_TIMEOUT: Self = + const_error!(ErrorKind::InvalidInput, "cannot set a 0 duration timeout"); + + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub const NO_ADDRESSES: Self = + const_error!(ErrorKind::InvalidInput, "could not resolve to any addresses"); +} + +// Only derive debug in tests, to make sure it +// doesn't accidentally get printed. +#[cfg_attr(test, derive(Debug))] +enum ErrorData { + Os(RawOsError), + Simple(ErrorKind), + SimpleMessage(&'static SimpleMessage), + Custom(C), +} + +// `#[repr(align(4))]` is probably redundant, it should have that value or +// higher already. We include it just because repr_bitpacked.rs's encoding +// requires an alignment >= 4 (note that `#[repr(align)]` will not reduce the +// alignment required by the struct, only increase it). +// +// If we add more variants to ErrorData, this can be increased to 8, but it +// should probably be behind `#[cfg_attr(target_pointer_width = "64", ...)]` or +// whatever cfg we're using to enable the `repr_bitpacked` code, since only the +// that version needs the alignment, and 8 is higher than the alignment we'll +// have on 32 bit platforms. +// +// (For the sake of being explicit: the alignment requirement here only matters +// if `error/repr_bitpacked.rs` is in use — for the unpacked repr it doesn't +// matter at all) +#[doc(hidden)] +#[unstable(feature = "io_const_error_internals", issue = "none")] +#[repr(align(4))] +#[derive(Debug)] +pub struct SimpleMessage { + pub kind: ErrorKind, + pub message: &'static str, +} + +/// Creates a new I/O error from a known kind of error and a string literal. +/// +/// Contrary to [`Error::new`][new], this macro does not allocate and can be used in +/// `const` contexts. +/// +// FIXME(#74481): Hard-links required to link from `core` to `alloc` for incoherent method +/// [new]: ../../alloc/io/struct.Error.html#method.new +/// +/// # Example +/// ``` +/// #![feature(io_const_error)] +/// use std::io::{const_error, Error, ErrorKind}; +/// +/// const FAIL: Error = const_error!(ErrorKind::Unsupported, "tried something that never works"); +/// +/// fn not_here() -> Result<(), Error> { +/// Err(FAIL) +/// } +/// ``` +#[rustc_macro_transparency = "semiopaque"] +#[unstable(feature = "io_const_error", issue = "133448")] +#[allow_internal_unstable(core_io, hint_must_use, io_const_error_internals)] +pub macro const_error($kind:expr, $message:expr $(,)?) { + $crate::hint::must_use($crate::io::Error::from_static_message( + const { &$crate::io::SimpleMessage { kind: $kind, message: $message } }, + )) +} + +/// Intended for use for errors not exposed to the user, where allocating onto +/// the heap (for normal construction via Error::new) is too costly. +#[stable(feature = "io_error_from_errorkind", since = "1.14.0")] +impl From for Error { + /// Converts an [`ErrorKind`] into an [`Error`]. + /// + /// This conversion creates a new error with a simple representation of error kind. + /// + /// # Examples + /// + /// ``` + /// use std::io::{Error, ErrorKind}; + /// + /// let not_found = ErrorKind::NotFound; + /// let error = Error::from(not_found); + /// assert_eq!("entity not found", format!("{error}")); + /// ``` + #[inline] + fn from(kind: ErrorKind) -> Error { + Error { repr: Repr::new_simple(kind) } + } +} + +impl Error { + /// # Safety + /// + /// The provided `CustomOwner` must have been constructed from a `Box` from the `alloc` crate. + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + #[must_use] + #[inline] + pub unsafe fn from_custom_owner(custom: CustomOwner) -> Error { + Error { repr: Repr::new_custom(custom) } + } + + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + #[must_use] + #[inline] + pub fn into_custom_owner(self) -> result::Result { + if matches!(self.repr.data(), ErrorData::Custom(..)) { + let ErrorData::Custom(c) = self.repr.into_data() else { + // SAFETY: Checked above using `matches!`. + unsafe { crate::hint::unreachable_unchecked() } + }; + Ok(c) + } else { + Err(self) + } + } + + /// Creates a new I/O error from a known kind of error as well as a constant + /// message. + /// + /// This function does not allocate. + /// + /// You should not use this directly, and instead use the `const_error!` + /// macro: `io::const_error!(ErrorKind::Something, "some_message")`. + /// + /// This function should maybe change to `from_static_message(kind: ErrorKind)` in the future, when const generics allow that. + #[inline] + #[doc(hidden)] + #[unstable(feature = "io_const_error_internals", issue = "none")] + pub const fn from_static_message(msg: &'static SimpleMessage) -> Error { + Self { repr: Repr::new_simple_message(msg) } + } + + /// # Safety + /// + /// `functions` must point to data that is entirely constant; it must + /// not be created during runtime. + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + #[must_use] + #[inline] + pub unsafe fn from_raw_os_error_with_functions( + code: RawOsError, + functions: &'static OsFunctions, + ) -> Error { + // SAFETY: Caller ensures `functions` is a constant not created at runtime. + unsafe { + set_functions(functions); + } + Error { repr: Repr::new_os(code) } + } + + /// Returns the OS error that this error represents (if any). + /// + /// If this [`Error`] was constructed via [`last_os_error`][last_os_error] or + /// [`from_raw_os_error`][from_raw_os_error], then this function will return [`Some`], otherwise + /// it will return [`None`]. + /// + // FIXME(#74481): Hard-links required to link from `core` to `std` for incoherent method + /// [last_os_error]: ../../std/io/struct.Error.html#method.last_os_error + /// [from_raw_os_error]: ../../std/io/struct.Error.html#method.from_raw_os_error + /// + /// # Examples + /// + /// ``` + /// use std::io::{Error, ErrorKind}; + /// + /// fn print_os_error(err: &Error) { + /// if let Some(raw_os_err) = err.raw_os_error() { + /// println!("raw OS error: {raw_os_err:?}"); + /// } else { + /// println!("Not an OS error"); + /// } + /// } + /// + /// fn main() { + /// // Will print "raw OS error: ...". + /// print_os_error(&Error::last_os_error()); + /// // Will print "Not an OS error". + /// print_os_error(&Error::new(ErrorKind::Other, "oh no!")); + /// } + /// ``` + #[stable(feature = "rust1", since = "1.0.0")] + #[must_use] + #[inline] + pub fn raw_os_error(&self) -> Option { + match self.repr.data() { + ErrorData::Os(i) => Some(i), + ErrorData::Custom(..) => None, + ErrorData::Simple(..) => None, + ErrorData::SimpleMessage(..) => None, + } + } + + /// Returns a reference to the inner error wrapped by this error (if any). + /// + /// If this [`Error`] was constructed via [`new`][new] then this function will + /// return [`Some`], otherwise it will return [`None`]. + /// + /// [new]: ../../alloc/io/struct.Error.html#method.new + /// + /// # Examples + /// + /// ``` + /// use std::io::{Error, ErrorKind}; + /// + /// fn print_error(err: &Error) { + /// if let Some(inner_err) = err.get_ref() { + /// println!("Inner error: {inner_err:?}"); + /// } else { + /// println!("No inner error"); + /// } + /// } + /// + /// fn main() { + /// // Will print "No inner error". + /// print_error(&Error::last_os_error()); + /// // Will print "Inner error: ...". + /// print_error(&Error::new(ErrorKind::Other, "oh no!")); + /// } + /// ``` + #[stable(feature = "io_error_inner", since = "1.3.0")] + #[must_use] + #[inline] + pub fn get_ref(&self) -> Option<&(dyn error::Error + Send + Sync + 'static)> { + match self.repr.data() { + ErrorData::Os(..) => None, + ErrorData::Simple(..) => None, + ErrorData::SimpleMessage(..) => None, + ErrorData::Custom(c) => Some(c.error_ref()), + } + } + + /// Returns a mutable reference to the inner error wrapped by this error + /// (if any). + /// + /// If this [`Error`] was constructed via [`new`][new] then this function will + /// return [`Some`], otherwise it will return [`None`]. + /// + // FIXME(#74481): Hard-links required to link from `core` to `std` + /// [new]: ../../alloc/io/struct.Error.html#method.new + /// + /// # Examples + /// + /// ``` + /// use std::io::{Error, ErrorKind}; + /// use std::{error, fmt}; + /// use std::fmt::Display; + /// + /// #[derive(Debug)] + /// struct MyError { + /// v: String, + /// } + /// + /// impl MyError { + /// fn new() -> MyError { + /// MyError { + /// v: "oh no!".to_string() + /// } + /// } + /// + /// fn change_message(&mut self, new_message: &str) { + /// self.v = new_message.to_string(); + /// } + /// } + /// + /// impl error::Error for MyError {} + /// + /// impl Display for MyError { + /// fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + /// write!(f, "MyError: {}", self.v) + /// } + /// } + /// + /// fn change_error(mut err: Error) -> Error { + /// if let Some(inner_err) = err.get_mut() { + /// inner_err.downcast_mut::().unwrap().change_message("I've been changed!"); + /// } + /// err + /// } + /// + /// fn print_error(err: &Error) { + /// if let Some(inner_err) = err.get_ref() { + /// println!("Inner error: {inner_err}"); + /// } else { + /// println!("No inner error"); + /// } + /// } + /// + /// fn main() { + /// // Will print "No inner error". + /// print_error(&change_error(Error::last_os_error())); + /// // Will print "Inner error: ...". + /// print_error(&change_error(Error::new(ErrorKind::Other, MyError::new()))); + /// } + /// ``` + #[stable(feature = "io_error_inner", since = "1.3.0")] + #[must_use] + #[inline] + pub fn get_mut(&mut self) -> Option<&mut (dyn error::Error + Send + Sync + 'static)> { + match self.repr.data_mut() { + ErrorData::Os(..) => None, + ErrorData::Simple(..) => None, + ErrorData::SimpleMessage(..) => None, + ErrorData::Custom(c) => Some(c.error_mut()), + } + } + + /// Returns the corresponding [`ErrorKind`] for this error. + /// + /// This may be a value set by Rust code constructing custom `io::Error`s, + /// or if this `io::Error` was sourced from the operating system, + /// it will be a value inferred from the system's error encoding. + /// See [`last_os_error`][last_os_error] for more details. + /// + // FIXME(#74481): Hard-links required to link from `core` to `std` + /// [last_os_error]: ../../std/io/struct.Error.html#method.last_os_error + /// + /// # Examples + /// + /// ``` + /// use std::io::{Error, ErrorKind}; + /// + /// fn print_error(err: Error) { + /// println!("{:?}", err.kind()); + /// } + /// + /// fn main() { + /// // As no error has (visibly) occurred, this may print anything! + /// // It likely prints a placeholder for unidentified (non-)errors. + /// print_error(Error::last_os_error()); + /// // Will print "AddrInUse". + /// print_error(Error::new(ErrorKind::AddrInUse, "oh no!")); + /// } + /// ``` + #[stable(feature = "rust1", since = "1.0.0")] + #[must_use] + #[inline] + pub fn kind(&self) -> ErrorKind { + match self.repr.data() { + ErrorData::Os(code) => decode_error_kind(code), + ErrorData::Custom(c) => c.kind, + ErrorData::Simple(kind) => kind, + ErrorData::SimpleMessage(m) => m.kind, + } + } + + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + #[doc(hidden)] + #[inline] + pub fn is_interrupted(&self) -> bool { + match self.repr.data() { + ErrorData::Os(code) => is_interrupted(code), + ErrorData::Custom(c) => c.kind == ErrorKind::Interrupted, + ErrorData::Simple(kind) => kind == ErrorKind::Interrupted, + ErrorData::SimpleMessage(m) => m.kind == ErrorKind::Interrupted, + } + } +} + +impl fmt::Debug for Repr { + fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { + match self.data() { + ErrorData::Os(code) => fmt + .debug_struct("Os") + .field("code", &code) + .field("kind", &decode_error_kind(code)) + .field( + "message", + &fmt::from_fn(|fmt| { + write!(fmt, "\"{}\"", fmt::from_fn(|fmt| format_os_error(code, fmt))) + }), + ) + .finish(), + ErrorData::Custom(c) => fmt::Debug::fmt(&c, fmt), + ErrorData::Simple(kind) => fmt.debug_tuple("Kind").field(&kind).finish(), + ErrorData::SimpleMessage(msg) => fmt + .debug_struct("Error") + .field("kind", &msg.kind) + .field("message", &msg.message) + .finish(), + } + } +} + +#[stable(feature = "rust1", since = "1.0.0")] +impl fmt::Display for Error { + fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { + match self.repr.data() { + ErrorData::Os(code) => { + let detail = fmt::from_fn(|fmt| format_os_error(code, fmt)); + write!(fmt, "{detail} (os error {code})") + } + ErrorData::Custom(c) => fmt::Display::fmt(c.error_ref(), fmt), + ErrorData::Simple(kind) => kind.fmt(fmt), + ErrorData::SimpleMessage(msg) => msg.message.fmt(fmt), + } + } +} + +#[stable(feature = "rust1", since = "1.0.0")] +impl error::Error for Error { + #[allow(deprecated)] + fn cause(&self) -> Option<&dyn error::Error> { + match self.repr.data() { + ErrorData::Os(..) => None, + ErrorData::Simple(..) => None, + ErrorData::SimpleMessage(..) => None, + ErrorData::Custom(c) => c.error_ref().cause(), + } + } + + fn source(&self) -> Option<&(dyn error::Error + 'static)> { + match self.repr.data() { + ErrorData::Os(..) => None, + ErrorData::Simple(..) => None, + ErrorData::SimpleMessage(..) => None, + ErrorData::Custom(c) => c.error_ref().source(), + } + } +} + +fn _assert_error_is_sync_send() { + fn _is_sync_send() {} + _is_sync_send::(); +} + +#[doc(hidden)] +#[derive(Debug)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +pub struct OsFunctions { + pub format_os_error: fn(_: RawOsError, _: &mut fmt::Formatter<'_>) -> fmt::Result, + pub decode_error_kind: fn(_: RawOsError) -> ErrorKind, + pub is_interrupted: fn(_: RawOsError) -> bool, +} + +impl OsFunctions { + const DEFAULT: &'static OsFunctions = &OsFunctions { + format_os_error: |_, _| Ok(()), + decode_error_kind: |_| ErrorKind::Uncategorized, + is_interrupted: |_| false, + }; +} + +/// A user-created allocated error. +// As with `SimpleMessage`: `#[repr(align(4))]` here is just because +// repr_bitpacked's encoding requires it. In practice it almost certainly be +// already be this high or higher. +#[doc(hidden)] +#[repr(align(4))] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +pub struct Custom { + kind: ErrorKind, + /// `Box` without `alloc`. + // INVARIANT: `error` must be a valid pointer and it must be safe to call `error_drop` + // with it once. + error: NonNull, + error_drop: unsafe fn(NonNull), + /// Call to drop a pointer to `Custom`. + // INVARIANT: must be safe to call once with a pointer to `Self` in `CustomOwner`. + outer_drop: unsafe fn(NonNull), +} + +// SAFETY: All members of `Custom` are `Send` +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +unsafe impl Send for Custom {} + +// SAFETY: All members of `Custom` are `Sync` +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +unsafe impl Sync for Custom {} + +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +impl fmt::Debug for Custom { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("Custom").field("kind", &self.kind).field("error", self.error_ref()).finish() + } +} + +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +impl Drop for Custom { + fn drop(&mut self) { + // SAFETY: by `Custom` invariants, this is a drop call on a valid pointer. + unsafe { + (self.error_drop)(self.error); + } + } +} + +impl Custom { + /// # Safety + /// + /// * `error` must be valid for up to a static lifetime, and own its pointee. + /// * `error_drop` must be safe to call for the pointer `error` exactly once. + /// * `outer_drop` must be safe to call on a pointer to this instance of `Custom` + /// (the pointer is likely stored within a [`CustomOwner`]). + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub unsafe fn from_raw( + kind: ErrorKind, + error: NonNull, + error_drop: unsafe fn(NonNull), + outer_drop: unsafe fn(NonNull), + ) -> Custom { + // INVARIANT: function preconditions match type invariants. + Custom { kind, error, error_drop, outer_drop } + } + + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub fn into_raw(self) -> NonNull { + let ptr = self.error; + // Avoid `Custom::drop` which would free the error pointer. + mem::forget(self); + ptr + } + + fn error_ref(&self) -> &(dyn error::Error + Send + Sync + 'static) { + // SAFETY: + // `from_raw` ensures `error` is a valid pointer up to a static lifetime + // and is owned by `self` + unsafe { self.error.as_ref() } + } + + fn error_mut(&mut self) -> &mut (dyn error::Error + Send + Sync + 'static) { + // SAFETY: + // `from_raw` ensures `error` is a valid pointer up to a static lifetime + // and is owned by `self` + unsafe { self.error.as_mut() } + } +} + +/// Effectively a `Box` without `alloc`. The `Custom` holds the call to free this pointer. +// INVARIANT: `self.0.outer_drop` must be safe to call once with `self.0`. +#[derive(Debug)] +#[repr(transparent)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +#[doc(hidden)] +pub struct CustomOwner(NonNull); + +// SAFETY: Custom is `Send` +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +unsafe impl Send for CustomOwner {} + +// SAFETY: Custom is `Sync` +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +unsafe impl Sync for CustomOwner {} + +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +impl Drop for CustomOwner { + fn drop(&mut self) { + // SAFETY: by `CustomOwner` invariants, this is a drop call on a valid pointer. + unsafe { + (self.0.as_ref().outer_drop)(self.0); + } + } +} + +impl CustomOwner { + /// # Safety + /// + /// * `custom` must point to valid `Custom`. + /// * The `outer_drop` of the provided `custom` must be the drop function for this pointer. + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub unsafe fn from_raw(custom: NonNull) -> CustomOwner { + // INVARIANT: by the preconditions, `custom.outer_drop` is the drop for `custom`. + CustomOwner(custom) + } + + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub fn into_raw(self) -> NonNull { + let ptr = self.0; + // Avoid `CustomOwner::drop`, which would free the pointer. + mem::forget(self); + ptr + } + + #[allow(dead_code, reason = "only used for unpacked representation")] + fn custom_ref(&self) -> &Custom { + // SAFETY: + // `from_raw` ensures `0` is a valid pointer up to a static lifetime + // and is owned by `self` + unsafe { self.0.as_ref() } + } + + #[allow(dead_code, reason = "only used for unpacked representation")] + fn custom_mut(&mut self) -> &mut Custom { + // SAFETY: + // `from_raw` ensures `0` is a valid pointer up to a static lifetime + // and is owned by `self` + unsafe { self.0.as_mut() } + } +} + +/// The type of raw OS error codes. +/// +/// This is an [`i32`] on all currently supported platforms, but platforms +/// added in the future (such as UEFI) may use a different primitive type like +/// [`usize`] or [`i16`]. Use `as` or [`into`] conversions where applicable to +/// ensure maximum portability. +/// +/// [`into`]: Into::into +#[unstable(feature = "raw_os_error_ty", issue = "107792")] +pub type RawOsError = cfg_select! { + target_os = "uefi" => usize, + // For 16-bit AVR and MSP430, i16 is equivalent to c_int. + // Using i16 to be explicit. + target_pointer_width = "16" => i16, + _ => i32, +}; + +/// A list specifying general categories of I/O error. +/// +/// This list is intended to grow over time and it is not recommended to +/// exhaustively match against it. +/// +/// It is used with the [`io::Error`][error] type. +/// +/// [error]: Error +/// +/// # Handling errors and matching on `ErrorKind` +/// +/// In application code, use `match` for the `ErrorKind` values you are +/// expecting; use `_` to match "all other errors". +/// +/// In comprehensive and thorough tests that want to verify that a test doesn't +/// return any known incorrect error kind, you may want to cut-and-paste the +/// current full list of errors from here into your test code, and then match +/// `_` as the correct case. This seems counterintuitive, but it will make your +/// tests more robust. In particular, if you want to verify that your code does +/// produce an unrecognized error kind, the robust solution is to check for all +/// the recognized error kinds and fail in those cases. +#[derive(Clone, Copy, Debug, Eq, Hash, Ord, PartialEq, PartialOrd)] +#[stable(feature = "rust1", since = "1.0.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "io_errorkind")] +#[allow(deprecated)] +#[non_exhaustive] +pub enum ErrorKind { + /// An entity was not found, often a file. + #[stable(feature = "rust1", since = "1.0.0")] + NotFound, + /// The operation lacked the necessary privileges to complete. + #[stable(feature = "rust1", since = "1.0.0")] + PermissionDenied, + /// The connection was refused by the remote server. + #[stable(feature = "rust1", since = "1.0.0")] + ConnectionRefused, + /// The connection was reset by the remote server. + #[stable(feature = "rust1", since = "1.0.0")] + ConnectionReset, + /// The remote host is not reachable. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + HostUnreachable, + /// The network containing the remote host is not reachable. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + NetworkUnreachable, + /// The connection was aborted (terminated) by the remote server. + #[stable(feature = "rust1", since = "1.0.0")] + ConnectionAborted, + /// The network operation failed because it was not connected yet. + #[stable(feature = "rust1", since = "1.0.0")] + NotConnected, + /// A socket address could not be bound because the address is already in + /// use elsewhere. + #[stable(feature = "rust1", since = "1.0.0")] + AddrInUse, + /// A nonexistent interface was requested or the requested address was not + /// local. + #[stable(feature = "rust1", since = "1.0.0")] + AddrNotAvailable, + /// The system's networking is down. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + NetworkDown, + /// The operation failed because a pipe was closed. + #[stable(feature = "rust1", since = "1.0.0")] + BrokenPipe, + /// An entity already exists, often a file. + #[stable(feature = "rust1", since = "1.0.0")] + AlreadyExists, + /// The operation needs to block to complete, but the blocking operation was + /// requested to not occur. + #[stable(feature = "rust1", since = "1.0.0")] + WouldBlock, + /// A filesystem object is, unexpectedly, not a directory. + /// + /// For example, a filesystem path was specified where one of the intermediate directory + /// components was, in fact, a plain file. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + NotADirectory, + /// The filesystem object is, unexpectedly, a directory. + /// + /// A directory was specified when a non-directory was expected. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + IsADirectory, + /// A non-empty directory was specified where an empty directory was expected. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + DirectoryNotEmpty, + /// The filesystem or storage medium is read-only, but a write operation was attempted. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + ReadOnlyFilesystem, + /// Loop in the filesystem or IO subsystem; often, too many levels of symbolic links. + /// + /// There was a loop (or excessively long chain) resolving a filesystem object + /// or file IO object. + /// + /// On Unix this is usually the result of a symbolic link loop; or, of exceeding the + /// system-specific limit on the depth of symlink traversal. + #[unstable(feature = "io_error_more", issue = "86442")] + FilesystemLoop, + /// Stale network file handle. + /// + /// With some network filesystems, notably NFS, an open file (or directory) can be invalidated + /// by problems with the network or server. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + StaleNetworkFileHandle, + /// A parameter was incorrect. + #[stable(feature = "rust1", since = "1.0.0")] + InvalidInput, + /// Data not valid for the operation were encountered. + /// + /// Unlike [`InvalidInput`], this typically means that the operation + /// parameters were valid, however the error was caused by malformed + /// input data. + /// + /// For example, a function that reads a file into a string will error with + /// `InvalidData` if the file's contents are not valid UTF-8. + /// + /// [`InvalidInput`]: ErrorKind::InvalidInput + #[stable(feature = "io_invalid_data", since = "1.2.0")] + InvalidData, + /// The I/O operation's timeout expired, causing it to be canceled. + #[stable(feature = "rust1", since = "1.0.0")] + TimedOut, + /// An error returned when an operation could not be completed because a + /// call to [`write`][write] returned [`Ok(0)`]. + /// + /// This typically means that an operation could only succeed if it wrote a + /// particular number of bytes but only a smaller number of bytes could be + /// written. + /// + /// [write]: crate::io::Write::write + /// [`Ok(0)`]: Ok + #[stable(feature = "rust1", since = "1.0.0")] + WriteZero, + /// The underlying storage (typically, a filesystem) is full. + /// + /// This does not include out of quota errors. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + StorageFull, + /// Seek on unseekable file. + /// + /// Seeking was attempted on an open file handle which is not suitable for seeking - for + /// example, on Unix, a named pipe opened with `File::open`. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + NotSeekable, + /// Filesystem quota or some other kind of quota was exceeded. + #[stable(feature = "io_error_quota_exceeded", since = "1.85.0")] + QuotaExceeded, + /// File larger than allowed or supported. + /// + /// This might arise from a hard limit of the underlying filesystem or file access API, or from + /// an administratively imposed resource limitation. Simple disk full, and out of quota, have + /// their own errors. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + FileTooLarge, + /// Resource is busy. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + ResourceBusy, + /// Executable file is busy. + /// + /// An attempt was made to write to a file which is also in use as a running program. (Not all + /// operating systems detect this situation.) + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + ExecutableFileBusy, + /// Deadlock (avoided). + /// + /// A file locking operation would result in deadlock. This situation is typically detected, if + /// at all, on a best-effort basis. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + Deadlock, + /// Cross-device or cross-filesystem (hard) link or rename. + #[stable(feature = "io_error_crosses_devices", since = "1.85.0")] + CrossesDevices, + /// Too many (hard) links to the same filesystem object. + /// + /// The filesystem does not support making so many hardlinks to the same file. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + TooManyLinks, + /// A filename was invalid. + /// + /// This error can also occur if a length limit for a name was exceeded. + #[stable(feature = "io_error_invalid_filename", since = "1.87.0")] + InvalidFilename, + /// Program argument list too long. + /// + /// When trying to run an external program, a system or process limit on the size of the + /// arguments would have been exceeded. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + ArgumentListTooLong, + /// This operation was interrupted. + /// + /// Interrupted operations can typically be retried. + #[stable(feature = "rust1", since = "1.0.0")] + Interrupted, + + /// This operation is unsupported on this platform. + /// + /// This means that the operation can never succeed. + #[stable(feature = "unsupported_error", since = "1.53.0")] + Unsupported, + + // ErrorKinds which are primarily categorisations for OS error + // codes should be added above. + // + /// An error returned when an operation could not be completed because an + /// "end of file" was reached prematurely. + /// + /// This typically means that an operation could only succeed if it read a + /// particular number of bytes but only a smaller number of bytes could be + /// read. + #[stable(feature = "read_exact", since = "1.6.0")] + UnexpectedEof, + + /// An operation could not be completed, because it failed + /// to allocate enough memory. + #[stable(feature = "out_of_memory_error", since = "1.54.0")] + OutOfMemory, + + /// The operation was partially successful and needs to be checked + /// later on due to not blocking. + #[unstable(feature = "io_error_inprogress", issue = "130840")] + InProgress, + + /// The process or the whole system has reached its limit on the number of + /// open files or sockets. + #[unstable(feature = "io_error_too_many_open_files", issue = "158319")] + TooManyOpenFiles, + + /// A low-level input/output error. + /// + /// This usually indicates a hardware or device-level failure, such as a bad + /// disk sector or a removed device, but the operating system may also report + /// it for other low-level I/O conditions. + #[unstable(feature = "io_error_input_output_error", issue = "159066")] + InputOutputError, + + // "Unusual" error kinds which do not correspond simply to (sets + // of) OS error codes, should be added just above this comment. + // `Other` and `Uncategorized` should remain at the end: + // + /// A custom error that does not fall under any other I/O error kind. + /// + /// This can be used to construct your own [`Error`][error]s that do not match any + /// [`ErrorKind`]. + /// + /// This [`ErrorKind`] is not used by the standard library. + /// + /// Errors from the standard library that do not fall under any of the I/O + /// error kinds cannot be `match`ed on, and will only match a wildcard (`_`) pattern. + /// New [`ErrorKind`]s might be added in the future for some of those. + /// + /// [error]: Error + #[stable(feature = "rust1", since = "1.0.0")] + Other, + + /// Any I/O error from the standard library that's not part of this list. + /// + /// Errors that are `Uncategorized` now may move to a different or a new + /// [`ErrorKind`] variant in the future. It is not recommended to match + /// an error against `Uncategorized`; use a wildcard match (`_`) instead. + #[unstable(feature = "io_error_uncategorized", issue = "none")] + #[doc(hidden)] + Uncategorized, +} + +impl ErrorKind { + const fn as_str(&self) -> &'static str { + use ErrorKind::*; + match *self { + // tidy-alphabetical-start + AddrInUse => "address in use", + AddrNotAvailable => "address not available", + AlreadyExists => "entity already exists", + ArgumentListTooLong => "argument list too long", + BrokenPipe => "broken pipe", + ConnectionAborted => "connection aborted", + ConnectionRefused => "connection refused", + ConnectionReset => "connection reset", + CrossesDevices => "cross-device link or rename", + Deadlock => "deadlock", + DirectoryNotEmpty => "directory not empty", + ExecutableFileBusy => "executable file busy", + FileTooLarge => "file too large", + FilesystemLoop => "filesystem loop or indirection limit (e.g. symlink loop)", + HostUnreachable => "host unreachable", + InProgress => "in progress", + InputOutputError => "input/output error", + Interrupted => "operation interrupted", + InvalidData => "invalid data", + InvalidFilename => "invalid filename", + InvalidInput => "invalid input parameter", + IsADirectory => "is a directory", + NetworkDown => "network down", + NetworkUnreachable => "network unreachable", + NotADirectory => "not a directory", + NotConnected => "not connected", + NotFound => "entity not found", + NotSeekable => "seek on unseekable file", + Other => "other error", + OutOfMemory => "out of memory", + PermissionDenied => "permission denied", + QuotaExceeded => "quota exceeded", + ReadOnlyFilesystem => "read-only filesystem or storage medium", + ResourceBusy => "resource busy", + StaleNetworkFileHandle => "stale network file handle", + StorageFull => "no storage space", + TimedOut => "timed out", + TooManyLinks => "too many links", + TooManyOpenFiles => "too many open files", + Uncategorized => "uncategorized error", + UnexpectedEof => "unexpected end of file", + Unsupported => "unsupported", + WouldBlock => "operation would block", + WriteZero => "write zero", + // tidy-alphabetical-end + } + } + + // This compiles to the same code as the check+transmute, but doesn't require + // unsafe, or to hard-code max ErrorKind or its size in a way the compiler + // couldn't verify. + #[inline] + #[allow(dead_code, reason = "only used for packed representation")] + const fn from_prim(ek: u32) -> Option { + macro_rules! from_prim { + ($prim:expr => $Enum:ident { $($Variant:ident),* $(,)? }) => {{ + // Force a compile error if the list gets out of date. + const _: fn(e: $Enum) = |e: $Enum| match e { + $($Enum::$Variant => (),)* + }; + match $prim { + $(v if v == ($Enum::$Variant as _) => Some($Enum::$Variant),)* + _ => None, + } + }} + } + from_prim!(ek => ErrorKind { + NotFound, + PermissionDenied, + ConnectionRefused, + ConnectionReset, + HostUnreachable, + NetworkUnreachable, + ConnectionAborted, + NotConnected, + AddrInUse, + AddrNotAvailable, + NetworkDown, + BrokenPipe, + AlreadyExists, + WouldBlock, + NotADirectory, + IsADirectory, + DirectoryNotEmpty, + ReadOnlyFilesystem, + FilesystemLoop, + StaleNetworkFileHandle, + InvalidInput, + InvalidData, + TimedOut, + WriteZero, + StorageFull, + NotSeekable, + QuotaExceeded, + FileTooLarge, + ResourceBusy, + ExecutableFileBusy, + Deadlock, + CrossesDevices, + TooManyLinks, + InvalidFilename, + ArgumentListTooLong, + Interrupted, + Other, + UnexpectedEof, + Unsupported, + OutOfMemory, + InProgress, + TooManyOpenFiles, + InputOutputError, + Uncategorized, + }) + } +} + +#[stable(feature = "io_errorkind_display", since = "1.60.0")] +impl fmt::Display for ErrorKind { + /// Shows a human-readable description of the [`ErrorKind`]. + /// + /// This is similar to `impl Display for Error`, but doesn't require first converting to Error. + /// + /// # Examples + /// + /// ``` + /// use core::io::ErrorKind; + /// assert_eq!("entity not found", ErrorKind::NotFound.to_string()); + /// ``` + fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { + fmt.write_str(self.as_str()) + } +} diff --git a/library/core/src/io/error/os_functions.rs b/library/core/src/io/error/os_functions.rs new file mode 100644 index 0000000000000..b34b7c7dc7926 --- /dev/null +++ b/library/core/src/io/error/os_functions.rs @@ -0,0 +1,30 @@ +use super::{ErrorKind, OsFunctions, RawOsError}; +use crate::fmt; + +/// # Safety +/// +/// The provided reference must point to data that is entirely constant; it must +/// not be created during runtime. +#[inline] +pub(super) unsafe fn set_functions(f: &'static OsFunctions) { + // FIXME: externally implementable items may allow for weak linkage, allowing + // these methods to be overridden even when atomic pointers are not supported. +} + +#[inline] +pub(super) fn format_os_error(errno: RawOsError, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { + let f = OsFunctions::DEFAULT; + (f.format_os_error)(errno, fmt) +} + +#[inline] +pub(super) fn decode_error_kind(errno: RawOsError) -> ErrorKind { + let f = OsFunctions::DEFAULT; + (f.decode_error_kind)(errno) +} + +#[inline] +pub(super) fn is_interrupted(errno: RawOsError) -> bool { + let f = OsFunctions::DEFAULT; + (f.is_interrupted)(errno) +} diff --git a/library/core/src/io/error/os_functions_atomic.rs b/library/core/src/io/error/os_functions_atomic.rs new file mode 100644 index 0000000000000..dfaf59ae742de --- /dev/null +++ b/library/core/src/io/error/os_functions_atomic.rs @@ -0,0 +1,61 @@ +//! OS-dependent functions +//! +//! `Error` needs OS functionalities to work interpret raw OS errors, but +//! we can't link to anythink here in `alloc`. Therefore, we restrict +//! creation of `Error` from raw OS errors in `std`, and require providing +//! a vtable of operations when creating one. + +// FIXME: replace this with externally implementable items once they are more stable + +use super::{ErrorKind, OsFunctions, RawOsError}; +use crate::fmt; +use crate::sync::atomic; + +/// These default functions are not reachable, but have them just to be safe. +static OS_FUNCTIONS: atomic::AtomicPtr = + atomic::AtomicPtr::new(OsFunctions::DEFAULT as *const _ as *mut _); + +fn get_os_functions() -> &'static OsFunctions { + // SAFETY: + // * `OS_FUNCTIONS` is initially a pointer to `OsFunctions::DEFAULT`, which is valid for a static lifetime. + // * `OS_FUNCTIONS` can only be changed by `set_functions`, which only accepts `&'static OsFunctions`. + // * Therefore, `OS_FUNCTIONS` must always contain a valid non-null pointer with a static lifetime. + // * `Relaxed` ordering is sufficient as the only way to write to `OS_FUNCTIONS` is through + // `set_functions`, which has as a safety precondition that any value passed in must + // be constant and not created during runtime. + unsafe { &*OS_FUNCTIONS.load(atomic::Ordering::Relaxed) } +} + +/// # Safety +/// +/// The provided reference must point to data that is entirely constant; it must +/// not be created during runtime. +#[inline] +pub(super) unsafe fn set_functions(f: &'static OsFunctions) { + #[cold] + fn set_functions_inner(f: &'static OsFunctions) { + OS_FUNCTIONS.store(f as *const _ as *mut _, atomic::Ordering::Relaxed); + } + + if OS_FUNCTIONS.load(atomic::Ordering::Relaxed) != f as *const _ as *mut _ { + set_functions_inner(f); + } +} + +#[inline] +pub(super) fn format_os_error(errno: RawOsError, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { + let f = get_os_functions(); + (f.format_os_error)(errno, fmt) +} + +#[inline] +pub(super) fn decode_error_kind(errno: RawOsError) -> ErrorKind { + let f = get_os_functions(); + (f.decode_error_kind)(errno) +} + +#[inline] +pub(super) fn is_interrupted(errno: RawOsError) -> bool { + let f = get_os_functions(); + (f.is_interrupted)(errno) +} diff --git a/library/std/src/io/error/repr_bitpacked.rs b/library/core/src/io/error/repr_bitpacked.rs similarity index 79% rename from library/std/src/io/error/repr_bitpacked.rs rename to library/core/src/io/error/repr_bitpacked.rs index 7353816a8171b..7b1c2b6902010 100644 --- a/library/std/src/io/error/repr_bitpacked.rs +++ b/library/core/src/io/error/repr_bitpacked.rs @@ -106,7 +106,7 @@ use core::marker::PhantomData; use core::num::NonZeroUsize; use core::ptr::NonNull; -use super::{Custom, ErrorData, ErrorKind, RawOsError, SimpleMessage}; +use super::{Custom, CustomOwner, ErrorData, ErrorKind, RawOsError, SimpleMessage}; // The 2 least-significant bits are used as tag. const TAG_MASK: usize = 0b11; @@ -126,15 +126,15 @@ const TAG_SIMPLE: usize = 0b11; /// ``` #[repr(transparent)] #[rustc_insignificant_dtor] -pub(super) struct Repr(NonNull<()>, PhantomData>>); +pub(super) struct Repr(NonNull<()>, PhantomData>); // All the types `Repr` stores internally are Send + Sync, and so is it. unsafe impl Send for Repr {} unsafe impl Sync for Repr {} impl Repr { - pub(super) fn new_custom(b: Box) -> Self { - let p = Box::into_raw(b).cast::(); + pub(super) fn new_custom(b: CustomOwner) -> Self { + let p = b.into_raw().as_ptr().cast::(); // Should only be possible if an allocator handed out a pointer with // wrong alignment. debug_assert_eq!(p.addr() & TAG_MASK, 0); @@ -146,7 +146,8 @@ impl Repr { // (rather than `ptr::wrapping_add`), but it's unclear this would give // any benefit, so we just use `wrapping_add` instead. let tagged = p.wrapping_add(TAG_CUSTOM).cast::<()>(); - // Safety: `TAG_CUSTOM + p` is the same as `TAG_CUSTOM | p`, + // SAFETY: + // `TAG_CUSTOM + p` is the same as `TAG_CUSTOM | p`, // because `p`'s alignment means it isn't allowed to have any of the // `TAG_BITS` set (you can verify that addition and bitwise-or are the // same when the operands have no bits in common using a truth table). @@ -156,7 +157,8 @@ impl Repr { // box, and `TAG_CUSTOM` just... isn't zero -- it's `0b01`). Therefore, // `TAG_CUSTOM + p` isn't zero and so `tagged` can't be, and the // `new_unchecked` is safe. - let res = Self(unsafe { NonNull::new_unchecked(tagged) }, PhantomData); + let ptr = unsafe { NonNull::new_unchecked(tagged) }; + let res = Self(ptr, PhantomData); // quickly smoke-check we encoded the right thing (This generally will // only run in std's tests, unless the user uses -Zbuild-std) debug_assert!(matches!(res.data(), ErrorData::Custom(_)), "repr(custom) encoding failed"); @@ -166,11 +168,9 @@ impl Repr { #[inline] pub(super) fn new_os(code: RawOsError) -> Self { let utagged = ((code as usize) << 32) | TAG_OS; - // Safety: `TAG_OS` is not zero, so the result of the `|` is not 0. - let res = Self( - NonNull::without_provenance(unsafe { NonZeroUsize::new_unchecked(utagged) }), - PhantomData, - ); + // SAFETY: `TAG_OS` is not zero, so the result of the `|` is not 0. + let utagged = unsafe { NonZeroUsize::new_unchecked(utagged) }; + let res = Self(NonNull::without_provenance(utagged), PhantomData); // quickly smoke-check we encoded the right thing (This generally will // only run in std's tests, unless the user uses -Zbuild-std) debug_assert!( @@ -183,11 +183,9 @@ impl Repr { #[inline] pub(super) fn new_simple(kind: ErrorKind) -> Self { let utagged = ((kind as usize) << 32) | TAG_SIMPLE; - // Safety: `TAG_SIMPLE` is not zero, so the result of the `|` is not 0. - let res = Self( - NonNull::without_provenance(unsafe { NonZeroUsize::new_unchecked(utagged) }), - PhantomData, - ); + // SAFETY: `TAG_SIMPLE` is not zero, so the result of the `|` is not 0. + let utagged = unsafe { NonZeroUsize::new_unchecked(utagged) }; + let res = Self(NonNull::without_provenance(utagged), PhantomData); // quickly smoke-check we encoded the right thing (This generally will // only run in std's tests, unless the user uses -Zbuild-std) debug_assert!( @@ -200,38 +198,43 @@ impl Repr { #[inline] pub(super) const fn new_simple_message(m: &'static SimpleMessage) -> Self { - // Safety: References are never null. - Self(unsafe { NonNull::new_unchecked(m as *const _ as *mut ()) }, PhantomData) + // SAFETY: References are never null. + let ptr = unsafe { NonNull::new_unchecked(m as *const _ as *mut ()) }; + Self(ptr, PhantomData) } #[inline] pub(super) fn data(&self) -> ErrorData<&Custom> { - // Safety: We're a Repr, decode_repr is fine. + // SAFETY: We're a Repr, decode_repr is fine. unsafe { decode_repr(self.0, |c| &*c) } } #[inline] pub(super) fn data_mut(&mut self) -> ErrorData<&mut Custom> { - // Safety: We're a Repr, decode_repr is fine. + // SAFETY: We're a Repr, decode_repr is fine. unsafe { decode_repr(self.0, |c| &mut *c) } } #[inline] - pub(super) fn into_data(self) -> ErrorData> { + pub(super) fn into_data(self) -> ErrorData { let this = core::mem::ManuallyDrop::new(self); - // Safety: We're a Repr, decode_repr is fine. The `Box::from_raw` is + // SAFETY: We're a Repr, decode_repr is fine. The `Box::from_raw` is // safe because we prevent double-drop using `ManuallyDrop`. - unsafe { decode_repr(this.0, |p| Box::from_raw(p)) } + unsafe { + decode_repr(this.0, |p| CustomOwner::from_raw(core::ptr::NonNull::new_unchecked(p))) + } } } impl Drop for Repr { #[inline] fn drop(&mut self) { - // Safety: We're a Repr, decode_repr is fine. The `Box::from_raw` is + // SAFETY: We're a Repr, decode_repr is fine. The `Box::from_raw` is // safe because we're being dropped. unsafe { - let _ = decode_repr(self.0, |p| Box::::from_raw(p)); + let _ = decode_repr(self.0, |p| { + CustomOwner::from_raw(core::ptr::NonNull::new_unchecked(p)) + }); } } } @@ -253,9 +256,9 @@ where } TAG_SIMPLE => { let kind_bits = (bits >> 32) as u32; - let kind = kind_from_prim(kind_bits).unwrap_or_else(|| { + let kind = ErrorKind::from_prim(kind_bits).unwrap_or_else(|| { debug_assert!(false, "Invalid io::error::Repr bits: `Repr({:#018x})`", bits); - // This means the `ptr` passed in was not valid, which violates + // SAFETY: This means the `ptr` passed in was not valid, which violates // the unsafe contract of `decode_repr`. // // Using this rather than unwrap meaningfully improves the code @@ -283,69 +286,6 @@ where } } -// This compiles to the same code as the check+transmute, but doesn't require -// unsafe, or to hard-code max ErrorKind or its size in a way the compiler -// couldn't verify. -#[inline] -fn kind_from_prim(ek: u32) -> Option { - macro_rules! from_prim { - ($prim:expr => $Enum:ident { $($Variant:ident),* $(,)? }) => {{ - // Force a compile error if the list gets out of date. - const _: fn(e: $Enum) = |e: $Enum| match e { - $($Enum::$Variant => ()),* - }; - match $prim { - $(v if v == ($Enum::$Variant as _) => Some($Enum::$Variant),)* - _ => None, - } - }} - } - from_prim!(ek => ErrorKind { - NotFound, - PermissionDenied, - ConnectionRefused, - ConnectionReset, - HostUnreachable, - NetworkUnreachable, - ConnectionAborted, - NotConnected, - AddrInUse, - AddrNotAvailable, - NetworkDown, - BrokenPipe, - AlreadyExists, - WouldBlock, - NotADirectory, - IsADirectory, - DirectoryNotEmpty, - ReadOnlyFilesystem, - FilesystemLoop, - StaleNetworkFileHandle, - InvalidInput, - InvalidData, - TimedOut, - WriteZero, - StorageFull, - NotSeekable, - QuotaExceeded, - FileTooLarge, - ResourceBusy, - ExecutableFileBusy, - Deadlock, - CrossesDevices, - TooManyLinks, - InvalidFilename, - ArgumentListTooLong, - Interrupted, - Other, - UnexpectedEof, - Unsupported, - OutOfMemory, - InProgress, - Uncategorized, - }) -} - // Some static checking to alert us if a change breaks any of the assumptions // that our encoding relies on for correctness and soundness. (Some of these are // a bit overly thorough/cautious, admittedly) @@ -369,12 +309,12 @@ static_assert!(@usize_eq: size_of::>(), size_of::()); // `Custom` and `SimpleMessage` need to be thin pointers. static_assert!(@usize_eq: size_of::<&'static SimpleMessage>(), 8); -static_assert!(@usize_eq: size_of::>(), 8); +static_assert!(@usize_eq: size_of::(), 8); static_assert!((TAG_MASK + 1).is_power_of_two()); // And they must have sufficient alignment. -static_assert!(align_of::() >= TAG_MASK + 1); -static_assert!(align_of::() >= TAG_MASK + 1); +static_assert!(align_of::() > TAG_MASK); +static_assert!(align_of::() > TAG_MASK); static_assert!(@usize_eq: TAG_MASK & TAG_SIMPLE_MESSAGE, TAG_SIMPLE_MESSAGE); static_assert!(@usize_eq: TAG_MASK & TAG_CUSTOM, TAG_CUSTOM); diff --git a/library/std/src/io/error/repr_unpacked.rs b/library/core/src/io/error/repr_unpacked.rs similarity index 76% rename from library/std/src/io/error/repr_unpacked.rs rename to library/core/src/io/error/repr_unpacked.rs index b3e7b5f024ea0..a32ed58ce1b74 100644 --- a/library/std/src/io/error/repr_unpacked.rs +++ b/library/core/src/io/error/repr_unpacked.rs @@ -2,15 +2,15 @@ //! non-64bit targets, where the packed 64 bit representation wouldn't work, and //! would have no benefit. -use super::{Custom, ErrorData, ErrorKind, RawOsError, SimpleMessage}; +use super::{Custom, CustomOwner, ErrorData, ErrorKind, RawOsError, SimpleMessage}; -type Inner = ErrorData>; +type Inner = ErrorData; pub(super) struct Repr(Inner); impl Repr { #[inline] - pub(super) fn new_custom(b: Box) -> Self { + pub(super) fn new_custom(b: CustomOwner) -> Self { Self(Inner::Custom(b)) } #[inline] @@ -26,7 +26,7 @@ impl Repr { Self(Inner::SimpleMessage(m)) } #[inline] - pub(super) fn into_data(self) -> ErrorData> { + pub(super) fn into_data(self) -> ErrorData { self.0 } #[inline] @@ -35,7 +35,7 @@ impl Repr { Inner::Os(c) => ErrorData::Os(*c), Inner::Simple(k) => ErrorData::Simple(*k), Inner::SimpleMessage(m) => ErrorData::SimpleMessage(*m), - Inner::Custom(m) => ErrorData::Custom(&*m), + Inner::Custom(m) => ErrorData::Custom(m.custom_ref()), } } #[inline] @@ -44,7 +44,7 @@ impl Repr { Inner::Os(c) => ErrorData::Os(*c), Inner::Simple(k) => ErrorData::Simple(*k), Inner::SimpleMessage(m) => ErrorData::SimpleMessage(*m), - Inner::Custom(m) => ErrorData::Custom(&mut *m), + Inner::Custom(m) => ErrorData::Custom(m.custom_mut()), } } } diff --git a/library/core/src/io/impls.rs b/library/core/src/io/impls.rs new file mode 100644 index 0000000000000..218bd7adc2a55 --- /dev/null +++ b/library/core/src/io/impls.rs @@ -0,0 +1,208 @@ +use crate::io::{self, IoSlice, Seek, SeekFrom, SizeHint, Write}; +use crate::{cmp, fmt, mem}; + +// ============================================================================= +// Forwarding implementations + +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +impl SizeHint for &mut T { + #[inline] + fn lower_bound(&self) -> usize { + SizeHint::lower_bound(*self) + } + + #[inline] + fn upper_bound(&self) -> Option { + SizeHint::upper_bound(*self) + } +} + +#[stable(feature = "rust1", since = "1.0.0")] +impl Write for &mut W { + #[inline] + fn write(&mut self, buf: &[u8]) -> io::Result { + (**self).write(buf) + } + + #[inline] + fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { + (**self).write_vectored(bufs) + } + + #[inline] + fn is_write_vectored(&self) -> bool { + (**self).is_write_vectored() + } + + #[inline] + fn flush(&mut self) -> io::Result<()> { + (**self).flush() + } + + #[inline] + fn write_all(&mut self, buf: &[u8]) -> io::Result<()> { + (**self).write_all(buf) + } + + #[inline] + fn write_all_vectored(&mut self, bufs: &mut [IoSlice<'_>]) -> io::Result<()> { + (**self).write_all_vectored(bufs) + } + + #[inline] + fn write_fmt(&mut self, fmt: fmt::Arguments<'_>) -> io::Result<()> { + (**self).write_fmt(fmt) + } +} +#[stable(feature = "rust1", since = "1.0.0")] +impl Seek for &mut S { + #[inline] + fn seek(&mut self, pos: SeekFrom) -> io::Result { + (**self).seek(pos) + } + + #[inline] + fn rewind(&mut self) -> io::Result<()> { + (**self).rewind() + } + + #[inline] + fn stream_len(&mut self) -> io::Result { + (**self).stream_len() + } + + #[inline] + fn stream_position(&mut self) -> io::Result { + (**self).stream_position() + } + + #[inline] + fn seek_relative(&mut self, offset: i64) -> io::Result<()> { + (**self).seek_relative(offset) + } +} + +// ============================================================================= +// In-memory buffer implementations + +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +impl SizeHint for &[u8] { + #[inline] + fn lower_bound(&self) -> usize { + self.len() + } + + #[inline] + fn upper_bound(&self) -> Option { + Some(self.len()) + } +} + +/// Write is implemented for `&mut [u8]` by copying into the slice, overwriting +/// its data. +/// +/// Note that writing updates the slice to point to the yet unwritten part. +/// The slice will be empty when it has been completely overwritten. +/// +/// If the number of bytes to be written exceeds the size of the slice, write operations will +/// return short writes: ultimately, `Ok(0)`; in this situation, `write_all` returns an error of +/// kind `ErrorKind::WriteZero`. +#[stable(feature = "rust1", since = "1.0.0")] +impl Write for &mut [u8] { + #[inline] + fn write(&mut self, data: &[u8]) -> io::Result { + let amt = cmp::min(data.len(), self.len()); + let (a, b) = mem::take(self).split_at_mut(amt); + a.copy_from_slice(&data[..amt]); + *self = b; + Ok(amt) + } + + #[inline] + fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { + let mut nwritten = 0; + for buf in bufs { + nwritten += self.write(buf)?; + if self.is_empty() { + break; + } + } + + Ok(nwritten) + } + + #[inline] + fn is_write_vectored(&self) -> bool { + true + } + + #[inline] + fn write_all(&mut self, data: &[u8]) -> io::Result<()> { + if self.write(data)? < data.len() { Err(io::Error::WRITE_ALL_EOF) } else { Ok(()) } + } + + #[inline] + fn write_all_vectored(&mut self, bufs: &mut [IoSlice<'_>]) -> io::Result<()> { + for buf in bufs { + if self.write(buf)? < buf.len() { + return Err(io::Error::WRITE_ALL_EOF); + } + } + Ok(()) + } + + #[inline] + fn flush(&mut self) -> io::Result<()> { + Ok(()) + } +} + +#[unstable(feature = "read_buf", issue = "78485")] +impl<'a> io::Write for core::io::BorrowedCursor<'a, u8> { + #[inline] + fn write(&mut self, buf: &[u8]) -> io::Result { + let amt = cmp::min(buf.len(), self.capacity()); + self.append(&buf[..amt]); + Ok(amt) + } + + #[inline] + fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { + let mut nwritten = 0; + for buf in bufs { + let n = self.write(buf)?; + nwritten += n; + if n < buf.len() { + break; + } + } + Ok(nwritten) + } + + #[inline] + fn is_write_vectored(&self) -> bool { + true + } + + #[inline] + fn write_all(&mut self, buf: &[u8]) -> io::Result<()> { + if self.write(buf)? < buf.len() { Err(io::Error::WRITE_ALL_EOF) } else { Ok(()) } + } + + #[inline] + fn write_all_vectored(&mut self, bufs: &mut [IoSlice<'_>]) -> io::Result<()> { + for buf in bufs { + if self.write(buf)? < buf.len() { + return Err(io::Error::WRITE_ALL_EOF); + } + } + Ok(()) + } + + #[inline] + fn flush(&mut self) -> io::Result<()> { + Ok(()) + } +} diff --git a/library/core/src/io/io_slice.rs b/library/core/src/io/io_slice.rs new file mode 100644 index 0000000000000..17f4fc4da940a --- /dev/null +++ b/library/core/src/io/io_slice.rs @@ -0,0 +1,345 @@ +use crate::fmt; +use crate::mem::take; +use crate::ops::{Deref, DerefMut}; + +cfg_select! { + any( + target_family = "unix", + target_os = "hermit", + target_os = "solid_asp3", + target_os = "trusty", + target_os = "wasi" + ) => { + #[path = "io_slice/repr_iovec.rs"] + mod repr; + } + target_os = "windows" => { + #[path = "io_slice/repr_windows.rs"] + mod repr; + } + target_os = "uefi" => { + #[path = "io_slice/repr_uefi.rs"] + mod repr; + } + _ => { + #[path = "io_slice/repr_generic.rs"] + mod repr; + } +} + +/// A buffer type used with `Read::read_vectored`. +/// +/// It is semantically a wrapper around a `&mut [u8]`, but is guaranteed to be +/// ABI compatible with the `iovec` type on Unix platforms and `WSABUF` on +/// Windows. +#[stable(feature = "iovec", since = "1.36.0")] +#[repr(transparent)] +pub struct IoSliceMut<'a>(repr::IoSliceMut<'a>); + +#[stable(feature = "iovec_send_sync", since = "1.44.0")] +unsafe impl<'a> Send for IoSliceMut<'a> {} + +#[stable(feature = "iovec_send_sync", since = "1.44.0")] +unsafe impl<'a> Sync for IoSliceMut<'a> {} + +#[stable(feature = "iovec", since = "1.36.0")] +impl<'a> fmt::Debug for IoSliceMut<'a> { + fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { + fmt::Debug::fmt(self.0.as_slice(), fmt) + } +} + +impl<'a> IoSliceMut<'a> { + /// Creates a new `IoSliceMut` wrapping a byte slice. + /// + /// # Panics + /// + /// Panics on Windows if the slice is larger than 4GB. + #[stable(feature = "iovec", since = "1.36.0")] + #[inline] + pub fn new(buf: &'a mut [u8]) -> IoSliceMut<'a> { + IoSliceMut(repr::IoSliceMut::new(buf)) + } + + /// Advance the internal cursor of the slice. + /// + /// Also see [`IoSliceMut::advance_slices`] to advance the cursors of + /// multiple buffers. + /// + /// # Panics + /// + /// Panics when trying to advance beyond the end of the slice. + /// + /// # Examples + /// + /// ``` + /// use std::io::IoSliceMut; + /// use std::ops::Deref; + /// + /// let mut data = [1; 8]; + /// let mut buf = IoSliceMut::new(&mut data); + /// + /// // Mark 3 bytes as read. + /// buf.advance(3); + /// assert_eq!(buf.deref(), [1; 5].as_ref()); + /// ``` + #[stable(feature = "io_slice_advance", since = "1.81.0")] + #[inline] + pub fn advance(&mut self, n: usize) { + self.0.advance(n) + } + + /// Advance a slice of slices. + /// + /// Shrinks the slice to remove any `IoSliceMut`s that are fully advanced over. + /// If the cursor ends up in the middle of an `IoSliceMut`, it is modified + /// to start at that cursor. + /// + /// For example, if we have a slice of two 8-byte `IoSliceMut`s, and we advance by 10 bytes, + /// the result will only include the second `IoSliceMut`, advanced by 2 bytes. + /// + /// # Panics + /// + /// Panics when trying to advance beyond the end of the slices. + /// + /// # Examples + /// + /// ``` + /// use std::io::IoSliceMut; + /// use std::ops::Deref; + /// + /// let mut buf1 = [1; 8]; + /// let mut buf2 = [2; 16]; + /// let mut buf3 = [3; 8]; + /// let mut bufs = &mut [ + /// IoSliceMut::new(&mut buf1), + /// IoSliceMut::new(&mut buf2), + /// IoSliceMut::new(&mut buf3), + /// ][..]; + /// + /// // Mark 10 bytes as read. + /// IoSliceMut::advance_slices(&mut bufs, 10); + /// assert_eq!(bufs[0].deref(), [2; 14].as_ref()); + /// assert_eq!(bufs[1].deref(), [3; 8].as_ref()); + /// ``` + #[stable(feature = "io_slice_advance", since = "1.81.0")] + #[inline] + pub fn advance_slices(bufs: &mut &mut [IoSliceMut<'a>], n: usize) { + // Number of buffers to remove. + let mut remove = 0; + // Remaining length before reaching n. + let mut left = n; + for buf in bufs.iter() { + if let Some(remainder) = left.checked_sub(buf.len()) { + left = remainder; + remove += 1; + } else { + break; + } + } + + *bufs = &mut take(bufs)[remove..]; + if bufs.is_empty() { + assert!(left == 0, "advancing io slices beyond their length"); + } else { + bufs[0].advance(left); + } + } + + /// Get the underlying bytes as a mutable slice with the original lifetime. + /// + /// # Examples + /// + /// ``` + /// #![feature(io_slice_as_bytes)] + /// use std::io::IoSliceMut; + /// + /// let mut data = *b"abcdef"; + /// let io_slice = IoSliceMut::new(&mut data); + /// io_slice.into_slice()[0] = b'A'; + /// + /// assert_eq!(&data, b"Abcdef"); + /// ``` + #[unstable(feature = "io_slice_as_bytes", issue = "132818")] + pub const fn into_slice(self) -> &'a mut [u8] { + self.0.into_slice() + } +} + +#[stable(feature = "iovec", since = "1.36.0")] +impl<'a> Deref for IoSliceMut<'a> { + type Target = [u8]; + + #[inline] + fn deref(&self) -> &[u8] { + self.0.as_slice() + } +} + +#[stable(feature = "iovec", since = "1.36.0")] +impl<'a> DerefMut for IoSliceMut<'a> { + #[inline] + fn deref_mut(&mut self) -> &mut [u8] { + self.0.as_mut_slice() + } +} + +/// A buffer type used with `Write::write_vectored`. +/// +/// It is semantically a wrapper around a `&[u8]`, but is guaranteed to be +/// ABI compatible with the `iovec` type on Unix platforms and `WSABUF` on +/// Windows. +#[stable(feature = "iovec", since = "1.36.0")] +#[derive(Copy, Clone)] +#[repr(transparent)] +pub struct IoSlice<'a>(repr::IoSlice<'a>); + +#[stable(feature = "iovec_send_sync", since = "1.44.0")] +unsafe impl<'a> Send for IoSlice<'a> {} + +#[stable(feature = "iovec_send_sync", since = "1.44.0")] +unsafe impl<'a> Sync for IoSlice<'a> {} + +#[stable(feature = "iovec", since = "1.36.0")] +impl<'a> fmt::Debug for IoSlice<'a> { + fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { + fmt::Debug::fmt(self.0.as_slice(), fmt) + } +} + +impl<'a> IoSlice<'a> { + /// Creates a new `IoSlice` wrapping a byte slice. + /// + /// # Panics + /// + /// Panics on Windows if the slice is larger than 4GB. + #[stable(feature = "iovec", since = "1.36.0")] + #[must_use] + #[inline] + pub fn new(buf: &'a [u8]) -> IoSlice<'a> { + IoSlice(repr::IoSlice::new(buf)) + } + + /// Advance the internal cursor of the slice. + /// + /// Also see [`IoSlice::advance_slices`] to advance the cursors of multiple + /// buffers. + /// + /// # Panics + /// + /// Panics when trying to advance beyond the end of the slice. + /// + /// # Examples + /// + /// ``` + /// use std::io::IoSlice; + /// use std::ops::Deref; + /// + /// let data = [1; 8]; + /// let mut buf = IoSlice::new(&data); + /// + /// // Mark 3 bytes as read. + /// buf.advance(3); + /// assert_eq!(buf.deref(), [1; 5].as_ref()); + /// ``` + #[stable(feature = "io_slice_advance", since = "1.81.0")] + #[inline] + pub fn advance(&mut self, n: usize) { + self.0.advance(n) + } + + /// Advance a slice of slices. + /// + /// Shrinks the slice to remove any `IoSlice`s that are fully advanced over. + /// If the cursor ends up in the middle of an `IoSlice`, it is modified + /// to start at that cursor. + /// + /// For example, if we have a slice of two 8-byte `IoSlice`s, and we advance by 10 bytes, + /// the result will only include the second `IoSlice`, advanced by 2 bytes. + /// + /// # Panics + /// + /// Panics when trying to advance beyond the end of the slices. + /// + /// # Examples + /// + /// ``` + /// use std::io::IoSlice; + /// use std::ops::Deref; + /// + /// let buf1 = [1; 8]; + /// let buf2 = [2; 16]; + /// let buf3 = [3; 8]; + /// let mut bufs = &mut [ + /// IoSlice::new(&buf1), + /// IoSlice::new(&buf2), + /// IoSlice::new(&buf3), + /// ][..]; + /// + /// // Mark 10 bytes as written. + /// IoSlice::advance_slices(&mut bufs, 10); + /// assert_eq!(bufs[0].deref(), [2; 14].as_ref()); + /// assert_eq!(bufs[1].deref(), [3; 8].as_ref()); + #[stable(feature = "io_slice_advance", since = "1.81.0")] + #[inline] + pub fn advance_slices(bufs: &mut &mut [IoSlice<'a>], n: usize) { + // Number of buffers to remove. + let mut remove = 0; + // Remaining length before reaching n. This prevents overflow + // that could happen if the length of slices in `bufs` were instead + // accumulated. Those slice may be aliased and, if they are large + // enough, their added length may overflow a `usize`. + let mut left = n; + for buf in bufs.iter() { + if let Some(remainder) = left.checked_sub(buf.len()) { + left = remainder; + remove += 1; + } else { + break; + } + } + + *bufs = &mut take(bufs)[remove..]; + if bufs.is_empty() { + assert!(left == 0, "advancing io slices beyond their length"); + } else { + bufs[0].advance(left); + } + } + + /// Get the underlying bytes as a slice with the original lifetime. + /// + /// This doesn't borrow from `self`, so is less restrictive than calling + /// `.deref()`, which does. + /// + /// # Examples + /// + /// ``` + /// #![feature(io_slice_as_bytes)] + /// use std::io::IoSlice; + /// + /// let data = b"abcdef"; + /// + /// let mut io_slice = IoSlice::new(data); + /// let tail = &io_slice.as_slice()[3..]; + /// + /// // This works because `tail` doesn't borrow `io_slice` + /// io_slice = IoSlice::new(tail); + /// + /// assert_eq!(io_slice.as_slice(), b"def"); + /// ``` + #[unstable(feature = "io_slice_as_bytes", issue = "132818")] + pub const fn as_slice(self) -> &'a [u8] { + self.0.as_slice() + } +} + +#[stable(feature = "iovec", since = "1.36.0")] +impl<'a> Deref for IoSlice<'a> { + type Target = [u8]; + + #[inline] + fn deref(&self) -> &[u8] { + self.0.as_slice() + } +} diff --git a/library/std/src/sys/io/io_slice/unsupported.rs b/library/core/src/io/io_slice/repr_generic.rs similarity index 50% rename from library/std/src/sys/io/io_slice/unsupported.rs rename to library/core/src/io/io_slice/repr_generic.rs index 1572cac6cd771..fdeb4978aedea 100644 --- a/library/std/src/sys/io/io_slice/unsupported.rs +++ b/library/core/src/io/io_slice/repr_generic.rs @@ -1,52 +1,52 @@ use crate::mem; #[derive(Copy, Clone)] -pub struct IoSlice<'a>(&'a [u8]); +pub(crate) struct IoSlice<'a>(&'a [u8]); impl<'a> IoSlice<'a> { #[inline] - pub fn new(buf: &'a [u8]) -> IoSlice<'a> { + pub(crate) fn new(buf: &'a [u8]) -> IoSlice<'a> { IoSlice(buf) } #[inline] - pub fn advance(&mut self, n: usize) { + pub(crate) fn advance(&mut self, n: usize) { self.0 = &self.0[n..] } #[inline] - pub const fn as_slice(&self) -> &'a [u8] { + pub(crate) const fn as_slice(&self) -> &'a [u8] { self.0 } } -pub struct IoSliceMut<'a>(&'a mut [u8]); +pub(crate) struct IoSliceMut<'a>(&'a mut [u8]); impl<'a> IoSliceMut<'a> { #[inline] - pub fn new(buf: &'a mut [u8]) -> IoSliceMut<'a> { + pub(crate) fn new(buf: &'a mut [u8]) -> IoSliceMut<'a> { IoSliceMut(buf) } #[inline] - pub fn advance(&mut self, n: usize) { + pub(crate) fn advance(&mut self, n: usize) { let slice = mem::take(&mut self.0); let (_, remaining) = slice.split_at_mut(n); self.0 = remaining; } #[inline] - pub fn as_slice(&self) -> &[u8] { + pub(crate) fn as_slice(&self) -> &[u8] { self.0 } #[inline] - pub const fn into_slice(self) -> &'a mut [u8] { + pub(crate) const fn into_slice(self) -> &'a mut [u8] { self.0 } #[inline] - pub fn as_mut_slice(&mut self) -> &mut [u8] { + pub(crate) fn as_mut_slice(&mut self) -> &mut [u8] { self.0 } } diff --git a/library/std/src/sys/io/io_slice/iovec.rs b/library/core/src/io/io_slice/repr_iovec.rs similarity index 54% rename from library/std/src/sys/io/io_slice/iovec.rs rename to library/core/src/io/io_slice/repr_iovec.rs index d549aca250d5f..cd8f5d539ecce 100644 --- a/library/std/src/sys/io/io_slice/iovec.rs +++ b/library/core/src/io/io_slice/repr_iovec.rs @@ -1,24 +1,24 @@ -#[cfg(target_os = "hermit")] -use hermit_abi::iovec; -#[cfg(any(target_family = "unix", target_os = "trusty", target_os = "wasi"))] -use libc::iovec; - use crate::ffi::c_void; use crate::marker::PhantomData; use crate::slice; -#[cfg(target_os = "solid_asp3")] -use crate::sys::pal::abi::sockets::iovec; + +#[derive(Copy, Clone)] +#[repr(C)] +struct iovec { + iov_base: *mut c_void, + iov_len: usize, +} #[derive(Copy, Clone)] #[repr(transparent)] -pub struct IoSlice<'a> { +pub(crate) struct IoSlice<'a> { vec: iovec, _p: PhantomData<&'a [u8]>, } impl<'a> IoSlice<'a> { #[inline] - pub fn new(buf: &'a [u8]) -> IoSlice<'a> { + pub(crate) fn new(buf: &'a [u8]) -> IoSlice<'a> { IoSlice { vec: iovec { iov_base: buf.as_ptr() as *mut u8 as *mut c_void, iov_len: buf.len() }, _p: PhantomData, @@ -26,11 +26,14 @@ impl<'a> IoSlice<'a> { } #[inline] - pub fn advance(&mut self, n: usize) { + pub(crate) fn advance(&mut self, n: usize) { if self.vec.iov_len < n { panic!("advancing IoSlice beyond its length"); } + // SAFETY: + // * `n <= iov_len` as asserted above. + // * The allocation pointed to by `iov_base` is valid up to `iov_base + iov_len`. unsafe { self.vec.iov_len -= n; self.vec.iov_base = self.vec.iov_base.add(n); @@ -38,20 +41,22 @@ impl<'a> IoSlice<'a> { } #[inline] - pub const fn as_slice(&self) -> &'a [u8] { + pub(crate) const fn as_slice(&self) -> &'a [u8] { + // SAFETY: + // * `iov_base` and `iov_len` come from a prior decomposition of a valid slice. unsafe { slice::from_raw_parts(self.vec.iov_base as *mut u8, self.vec.iov_len) } } } #[repr(transparent)] -pub struct IoSliceMut<'a> { +pub(crate) struct IoSliceMut<'a> { vec: iovec, _p: PhantomData<&'a mut [u8]>, } impl<'a> IoSliceMut<'a> { #[inline] - pub fn new(buf: &'a mut [u8]) -> IoSliceMut<'a> { + pub(crate) fn new(buf: &'a mut [u8]) -> IoSliceMut<'a> { IoSliceMut { vec: iovec { iov_base: buf.as_mut_ptr() as *mut c_void, iov_len: buf.len() }, _p: PhantomData, @@ -59,11 +64,14 @@ impl<'a> IoSliceMut<'a> { } #[inline] - pub fn advance(&mut self, n: usize) { + pub(crate) fn advance(&mut self, n: usize) { if self.vec.iov_len < n { panic!("advancing IoSliceMut beyond its length"); } + // SAFETY: + // * `n <= iov_len` as asserted above. + // * The allocation pointed to by `iov_base` is valid up to `iov_base + iov_len`. unsafe { self.vec.iov_len -= n; self.vec.iov_base = self.vec.iov_base.add(n); @@ -71,17 +79,23 @@ impl<'a> IoSliceMut<'a> { } #[inline] - pub fn as_slice(&self) -> &[u8] { + pub(crate) fn as_slice(&self) -> &[u8] { + // SAFETY: + // * `iov_base` and `iov_len` come from a prior decomposition of a valid slice. unsafe { slice::from_raw_parts(self.vec.iov_base as *mut u8, self.vec.iov_len) } } #[inline] - pub const fn into_slice(self) -> &'a mut [u8] { + pub(crate) const fn into_slice(self) -> &'a mut [u8] { + // SAFETY: + // * `iov_base` and `iov_len` come from a prior decomposition of a valid slice. unsafe { slice::from_raw_parts_mut(self.vec.iov_base as *mut u8, self.vec.iov_len) } } #[inline] - pub fn as_mut_slice(&mut self) -> &mut [u8] { + pub(crate) fn as_mut_slice(&mut self) -> &mut [u8] { + // SAFETY: + // * `iov_base` and `iov_len` come from a prior decomposition of a valid slice. unsafe { slice::from_raw_parts_mut(self.vec.iov_base as *mut u8, self.vec.iov_len) } } } diff --git a/library/std/src/sys/io/io_slice/uefi.rs b/library/core/src/io/io_slice/repr_uefi.rs similarity index 56% rename from library/std/src/sys/io/io_slice/uefi.rs rename to library/core/src/io/io_slice/repr_uefi.rs index 909cfbea0b7ba..3698eea733837 100644 --- a/library/std/src/sys/io/io_slice/uefi.rs +++ b/library/core/src/io/io_slice/repr_uefi.rs @@ -6,7 +6,7 @@ use crate::slice; #[derive(Copy, Clone)] #[repr(C)] -pub struct IoSlice<'a> { +pub(crate) struct IoSlice<'a> { len: u32, data: *const u8, _p: PhantomData<&'a [u8]>, @@ -14,28 +14,34 @@ pub struct IoSlice<'a> { impl<'a> IoSlice<'a> { #[inline] - pub fn new(buf: &'a [u8]) -> IoSlice<'a> { + pub(crate) fn new(buf: &'a [u8]) -> IoSlice<'a> { let len = buf.len().try_into().unwrap(); Self { len, data: buf.as_ptr(), _p: PhantomData } } #[inline] - pub fn advance(&mut self, n: usize) { + pub(crate) fn advance(&mut self, n: usize) { self.len = u32::try_from(n) .ok() .and_then(|n| self.len.checked_sub(n)) .expect("advancing IoSlice beyond its length"); + + // SAFETY: + // * `n <= len` as asserted above. + // * The allocation pointed to by `data` is valid up to `data + len`. unsafe { self.data = self.data.add(n) }; } #[inline] - pub const fn as_slice(&self) -> &'a [u8] { + pub(crate) const fn as_slice(&self) -> &'a [u8] { + // SAFETY: + // * `data` and `len` come from a prior decomposition of a valid slice. unsafe { slice::from_raw_parts(self.data, self.len as usize) } } } #[repr(C)] -pub struct IoSliceMut<'a> { +pub(crate) struct IoSliceMut<'a> { len: u32, data: *mut u8, _p: PhantomData<&'a mut [u8]>, @@ -43,32 +49,42 @@ pub struct IoSliceMut<'a> { impl<'a> IoSliceMut<'a> { #[inline] - pub fn new(buf: &'a mut [u8]) -> IoSliceMut<'a> { + pub(crate) fn new(buf: &'a mut [u8]) -> IoSliceMut<'a> { let len = buf.len().try_into().unwrap(); Self { len, data: buf.as_mut_ptr(), _p: PhantomData } } #[inline] - pub fn advance(&mut self, n: usize) { + pub(crate) fn advance(&mut self, n: usize) { self.len = u32::try_from(n) .ok() .and_then(|n| self.len.checked_sub(n)) .expect("advancing IoSlice beyond its length"); + + // SAFETY: + // * `n <= len` as asserted above. + // * The allocation pointed to by `data` is valid up to `data + len`. unsafe { self.data = self.data.add(n) }; } #[inline] - pub fn as_slice(&self) -> &[u8] { + pub(crate) fn as_slice(&self) -> &[u8] { + // SAFETY: + // * `data` and `len` come from a prior decomposition of a valid slice. unsafe { slice::from_raw_parts(self.data, self.len as usize) } } #[inline] - pub const fn into_slice(self) -> &'a mut [u8] { + pub(crate) const fn into_slice(self) -> &'a mut [u8] { + // SAFETY: + // * `data` and `len` come from a prior decomposition of a valid slice. unsafe { slice::from_raw_parts_mut(self.data, self.len as usize) } } #[inline] - pub fn as_mut_slice(&mut self) -> &mut [u8] { + pub(crate) fn as_mut_slice(&mut self) -> &mut [u8] { + // SAFETY: + // * `data` and `len` come from a prior decomposition of a valid slice. unsafe { slice::from_raw_parts_mut(self.data, self.len as usize) } } } diff --git a/library/core/src/io/io_slice/repr_windows.rs b/library/core/src/io/io_slice/repr_windows.rs new file mode 100644 index 0000000000000..6162d86de8e59 --- /dev/null +++ b/library/core/src/io/io_slice/repr_windows.rs @@ -0,0 +1,99 @@ +use crate::marker::PhantomData; +use crate::slice; + +#[repr(C)] +#[derive(Clone, Copy)] +struct WSABUF { + len: u32, + buf: *mut u8, +} + +#[derive(Copy, Clone)] +#[repr(transparent)] +pub(crate) struct IoSlice<'a> { + vec: WSABUF, + _p: PhantomData<&'a [u8]>, +} + +impl<'a> IoSlice<'a> { + #[inline] + pub(crate) fn new(buf: &'a [u8]) -> IoSlice<'a> { + assert!(buf.len() <= u32::MAX as usize); + IoSlice { + vec: WSABUF { len: buf.len() as u32, buf: buf.as_ptr() as *mut u8 }, + _p: PhantomData, + } + } + + #[inline] + pub(crate) fn advance(&mut self, n: usize) { + if (self.vec.len as usize) < n { + panic!("advancing IoSlice beyond its length"); + } + + // SAFETY: + // * `n <= len` as asserted above. + // * The allocation pointed to by `buf` is valid up to `buf + len`. + unsafe { + self.vec.len -= n as u32; + self.vec.buf = self.vec.buf.add(n); + } + } + + #[inline] + pub(crate) const fn as_slice(&self) -> &'a [u8] { + // SAFETY: + // * `buf` and `len` come from a prior decomposition of a valid slice. + unsafe { slice::from_raw_parts(self.vec.buf, self.vec.len as usize) } + } +} + +#[repr(transparent)] +pub(crate) struct IoSliceMut<'a> { + vec: WSABUF, + _p: PhantomData<&'a mut [u8]>, +} + +impl<'a> IoSliceMut<'a> { + #[inline] + pub(crate) fn new(buf: &'a mut [u8]) -> IoSliceMut<'a> { + assert!(buf.len() <= u32::MAX as usize); + IoSliceMut { vec: WSABUF { len: buf.len() as u32, buf: buf.as_mut_ptr() }, _p: PhantomData } + } + + #[inline] + pub(crate) fn advance(&mut self, n: usize) { + if (self.vec.len as usize) < n { + panic!("advancing IoSliceMut beyond its length"); + } + + // SAFETY: + // * `n <= len` as asserted above. + // * The allocation pointed to by `buf` is valid up to `buf + len`. + unsafe { + self.vec.len -= n as u32; + self.vec.buf = self.vec.buf.add(n); + } + } + + #[inline] + pub(crate) fn as_slice(&self) -> &[u8] { + // SAFETY: + // * `buf` and `len` come from a prior decomposition of a valid slice. + unsafe { slice::from_raw_parts(self.vec.buf, self.vec.len as usize) } + } + + #[inline] + pub(crate) const fn into_slice(self) -> &'a mut [u8] { + // SAFETY: + // * `buf` and `len` come from a prior decomposition of a valid slice. + unsafe { slice::from_raw_parts_mut(self.vec.buf, self.vec.len as usize) } + } + + #[inline] + pub(crate) fn as_mut_slice(&mut self) -> &mut [u8] { + // SAFETY: + // * `buf` and `len` come from a prior decomposition of a valid slice. + unsafe { slice::from_raw_parts_mut(self.vec.buf, self.vec.len as usize) } + } +} diff --git a/library/core/src/io/mod.rs b/library/core/src/io/mod.rs index 2f20180cdc9a2..a44d271535a9e 100644 --- a/library/core/src/io/mod.rs +++ b/library/core/src/io/mod.rs @@ -1,6 +1,64 @@ //! Traits, helpers, and type definitions for core I/O functionality. mod borrowed_buf; +mod cursor; +mod error; +mod impls; +mod io_slice; +#[unstable(feature = "core_io", issue = "154046")] +pub mod prelude; +mod seek; +mod size_hint; +mod util; +mod write; #[unstable(feature = "core_io_borrowed_buf", issue = "117693")] pub use self::borrowed_buf::{BorrowedBuf, BorrowedCursor}; +#[unstable(feature = "raw_os_error_ty", issue = "107792")] +pub use self::error::RawOsError; +#[unstable(feature = "io_const_error_internals", issue = "none")] +pub use self::error::SimpleMessage; +#[unstable(feature = "io_const_error", issue = "133448")] +pub use self::error::const_error; +#[unstable(feature = "core_io", issue = "154046")] +pub use self::{ + cursor::Cursor, + error::{Error, ErrorKind, Result}, + io_slice::{IoSlice, IoSliceMut}, + seek::{Seek, SeekFrom}, + util::{Chain, Empty, Repeat, Sink, Take, empty, repeat, sink}, + write::Write, +}; +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +pub use self::{ + cursor::{ + WriteThroughCursor, slice_write, slice_write_all, slice_write_all_vectored, + slice_write_vectored, + }, + error::{Custom, CustomOwner, OsFunctions}, + seek::stream_len_default, + size_hint::SizeHint, + util::{chain, take}, + write::default_write_vectored, +}; + +/// Marks that a type `T` can have IO traits such as [`Seek`], [`Write`], etc. automatically +/// implemented for handle types like [`Arc`][arc] as well. +/// +/// This trait should only be implemented for types where `<&T as Trait>::method(&mut &value, ..)` +/// would be identical to `::method(&mut value, ..)`. +/// +/// [`File`][file] passes this test, as operations on `&File` and `File` both affect +/// the same underlying file. +/// `[u8]` fails, because any modification to `&mut &[u8]` would only affect a temporary +/// and be lost after the method has been called. +/// +// FIXME(#74481): Hard-links required to link from `core` to `std` +/// [file]: ../../std/fs/struct.File.html +/// [arc]: ../../alloc/sync/struct.Arc.html +/// [`Write`]: crate::io::Write +/// [`Seek`]: crate::io::Seek +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +pub trait IoHandle {} diff --git a/library/core/src/io/prelude.rs b/library/core/src/io/prelude.rs new file mode 100644 index 0000000000000..3ff5833fb6331 --- /dev/null +++ b/library/core/src/io/prelude.rs @@ -0,0 +1,13 @@ +//! The I/O Prelude. +//! +//! The purpose of this module is to alleviate imports of many common I/O traits +//! by adding a glob import to the top of I/O heavy modules: +//! +//! ``` +//! # #![feature(core_io)] +//! # #![allow(unused_imports)] +//! use core::io::prelude::*; +//! ``` + +#[stable(feature = "rust1", since = "1.0.0")] +pub use crate::io::{Seek, Write}; diff --git a/library/core/src/io/seek.rs b/library/core/src/io/seek.rs new file mode 100644 index 0000000000000..4c242c761dfe6 --- /dev/null +++ b/library/core/src/io/seek.rs @@ -0,0 +1,221 @@ +use crate::io::Result; + +/// The `Seek` trait provides a cursor which can be moved within a stream of +/// bytes. +/// +/// The stream typically has a fixed size, allowing seeking relative to either +/// end or the current offset. +/// +/// # Examples +/// +/// `File`s implement `Seek`: +/// +/// ```no_run +/// use std::io; +/// use std::io::prelude::*; +/// use std::fs::File; +/// use std::io::SeekFrom; +/// +/// fn main() -> io::Result<()> { +/// let mut f = File::open("foo.txt")?; +/// +/// // move the cursor 42 bytes from the start of the file +/// f.seek(SeekFrom::Start(42))?; +/// Ok(()) +/// } +/// ``` +#[stable(feature = "rust1", since = "1.0.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "IoSeek")] +pub trait Seek { + /// Seek to an offset, in bytes, in a stream. + /// + /// A seek beyond the end of a stream is allowed, but behavior is defined + /// by the implementation. + /// + /// If the seek operation completed successfully, + /// this method returns the new position from the start of the stream. + /// That position can be used later with [`SeekFrom::Start`]. + /// + /// # Errors + /// + /// Seeking can fail, for example because it might involve flushing a buffer. + /// + /// Seeking to a negative offset is considered an error. + #[stable(feature = "rust1", since = "1.0.0")] + fn seek(&mut self, pos: SeekFrom) -> Result; + + /// Rewind to the beginning of a stream. + /// + /// This is a convenience method, equivalent to `seek(SeekFrom::Start(0))`. + /// + /// # Errors + /// + /// Rewinding can fail, for example because it might involve flushing a buffer. + /// + /// # Example + /// + /// ```no_run + /// use std::io::{Read, Seek, Write}; + /// use std::fs::OpenOptions; + /// + /// let mut f = OpenOptions::new() + /// .write(true) + /// .read(true) + /// .create(true) + /// .open("foo.txt")?; + /// + /// let hello = "Hello!\n"; + /// write!(f, "{hello}")?; + /// f.rewind()?; + /// + /// let mut buf = String::new(); + /// f.read_to_string(&mut buf)?; + /// assert_eq!(&buf, hello); + /// # std::io::Result::Ok(()) + /// ``` + #[stable(feature = "seek_rewind", since = "1.55.0")] + fn rewind(&mut self) -> Result<()> { + self.seek(SeekFrom::Start(0))?; + Ok(()) + } + + /// Returns the length of this stream (in bytes). + /// + /// The default implementation uses up to three seek operations. If this + /// method returns successfully, the seek position is unchanged (i.e. the + /// position before calling this method is the same as afterwards). + /// However, if this method returns an error, the seek position is + /// unspecified. + /// + /// If you need to obtain the length of *many* streams and you don't care + /// about the seek position afterwards, you can reduce the number of seek + /// operations by simply calling `seek(SeekFrom::End(0))` and using its + /// return value (it is also the stream length). + /// + /// Note that length of a stream can change over time (for example, when + /// data is appended to a file). So calling this method multiple times does + /// not necessarily return the same length each time. + /// + /// # Example + /// + /// ```no_run + /// #![feature(seek_stream_len)] + /// use std::{ + /// io::{self, Seek}, + /// fs::File, + /// }; + /// + /// fn main() -> io::Result<()> { + /// let mut f = File::open("foo.txt")?; + /// + /// let len = f.stream_len()?; + /// println!("The file is currently {len} bytes long"); + /// Ok(()) + /// } + /// ``` + #[unstable(feature = "seek_stream_len", issue = "59359")] + fn stream_len(&mut self) -> Result { + stream_len_default(self) + } + + /// Returns the current seek position from the start of the stream. + /// + /// This is equivalent to `self.seek(SeekFrom::Current(0))`. + /// + /// # Example + /// + /// ```no_run + /// use std::{ + /// io::{self, BufRead, BufReader, Seek}, + /// fs::File, + /// }; + /// + /// fn main() -> io::Result<()> { + /// let mut f = BufReader::new(File::open("foo.txt")?); + /// + /// let before = f.stream_position()?; + /// f.read_line(&mut String::new())?; + /// let after = f.stream_position()?; + /// + /// println!("The first line was {} bytes long", after - before); + /// Ok(()) + /// } + /// ``` + #[stable(feature = "seek_convenience", since = "1.51.0")] + fn stream_position(&mut self) -> Result { + self.seek(SeekFrom::Current(0)) + } + + /// Seeks relative to the current position. + /// + /// This is equivalent to `self.seek(SeekFrom::Current(offset))` but + /// doesn't return the new position which can allow some implementations + /// such as `BufReader` to perform more efficient seeks. + /// + /// # Example + /// + /// ```no_run + /// use std::{ + /// io::{self, Seek}, + /// fs::File, + /// }; + /// + /// fn main() -> io::Result<()> { + /// let mut f = File::open("foo.txt")?; + /// f.seek_relative(10)?; + /// assert_eq!(f.stream_position()?, 10); + /// Ok(()) + /// } + /// ``` + #[stable(feature = "seek_seek_relative", since = "1.80.0")] + fn seek_relative(&mut self, offset: i64) -> Result<()> { + self.seek(SeekFrom::Current(offset))?; + Ok(()) + } +} + +/// The default implementation of [`Seek::stream_len`]. +/// This may be desirable in `libstd` where the default implementation is desirable, +/// but additional work needs to be done before or after. +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +pub fn stream_len_default(self_: &mut T) -> Result { + let old_pos = self_.stream_position()?; + let len = self_.seek(SeekFrom::End(0))?; + + // Avoid seeking a third time when we were already at the end of the + // stream. The branch is usually way cheaper than a seek operation. + if old_pos != len { + self_.seek(SeekFrom::Start(old_pos))?; + } + + Ok(len) +} + +/// Enumeration of possible methods to seek within an I/O object. +/// +/// It is used by the [`Seek`] trait. +#[derive(Copy, PartialEq, Eq, Clone, Debug)] +#[stable(feature = "rust1", since = "1.0.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "SeekFrom")] +pub enum SeekFrom { + /// Sets the offset to the provided number of bytes. + #[stable(feature = "rust1", since = "1.0.0")] + Start(#[stable(feature = "rust1", since = "1.0.0")] u64), + + /// Sets the offset to the size of this object plus the specified number of + /// bytes. + /// + /// It is possible to seek beyond the end of an object, but it's an error to + /// seek before byte 0. + #[stable(feature = "rust1", since = "1.0.0")] + End(#[stable(feature = "rust1", since = "1.0.0")] i64), + + /// Sets the offset to the current position plus the specified number of + /// bytes. + /// + /// It is possible to seek beyond the end of an object, but it's an error to + /// seek before byte 0. + #[stable(feature = "rust1", since = "1.0.0")] + Current(#[stable(feature = "rust1", since = "1.0.0")] i64), +} diff --git a/library/core/src/io/size_hint.rs b/library/core/src/io/size_hint.rs new file mode 100644 index 0000000000000..fa4e25c62f6d0 --- /dev/null +++ b/library/core/src/io/size_hint.rs @@ -0,0 +1,60 @@ +/// Internal trait used to allow for specialization in `Read::size_hint` and +/// `Iterator::size_hint`. +/// +/// All types implement this through a blanket default implementation returning +/// a hint of `(0, None)`. +/// +/// Implementors should only provide [`lower_bound`](SizeHint::lower_bound) and +/// [`upper_bound`](SizeHint::upper_bound). +/// [`size_hint`](SizeHint::size_hint) is provided as a `final` method to enforce +/// correctness. +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +pub trait SizeHint { + /// Returns a lower bound on the number of elements this container-like item + /// contains. + /// For example, an array `[u8; 12]` could return any value between `0` and + /// `12` inclusively as a correct implementation. + /// + /// Through specialization, all types implement this method returning a default + /// value of `0`. + /// + /// Implementations *must* ensure the returned value is less than or equal to + /// the true element count. + fn lower_bound(&self) -> usize; + + /// Returns an upper bound on the number of elements this container-like item + /// contains if it can be determined, otherwise `None`. + /// + /// Through specialization, all types implement this method returning a default + /// value of `None`. + /// + /// Implementations *must* ensure the returned value is greater than or equal + /// to the true element count. + fn upper_bound(&self) -> Option; + + /// Returns an estimate for the number of elements this container like type + /// contains. + /// + /// This is a `final` method, and is guaranteed to return + /// `(self.lower_bound(), self.upper_bound())`. + /// + /// Without specialization, types implementing this trait will return `(0, None)`. + final fn size_hint(&self) -> (usize, Option) { + (self.lower_bound(), self.upper_bound()) + } +} + +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +impl SizeHint for T { + #[inline] + default fn lower_bound(&self) -> usize { + 0 + } + + #[inline] + default fn upper_bound(&self) -> Option { + None + } +} diff --git a/library/core/src/io/util.rs b/library/core/src/io/util.rs new file mode 100644 index 0000000000000..07173f13eb08b --- /dev/null +++ b/library/core/src/io/util.rs @@ -0,0 +1,690 @@ +use crate::io::{self, ErrorKind, IoSlice, Result, Seek, SeekFrom, SizeHint, Write}; +use crate::{cmp, fmt}; + +/// `Empty` ignores any data written via [`Write`], and will always be empty +/// (returning zero bytes) when read via [`Read`]. +/// +/// [`Write`]: crate::io::Write +/// [`Read`]: ../../std/io/trait.Read.html +/// +/// This struct is generally created by calling [`empty()`]. Please +/// see the documentation of [`empty()`] for more details. +#[stable(feature = "rust1", since = "1.0.0")] +#[non_exhaustive] +#[derive(Copy, Clone, Debug, Default)] +pub struct Empty; + +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +impl SizeHint for Empty { + #[inline] + fn upper_bound(&self) -> Option { + Some(0) + } +} + +#[stable(feature = "empty_write", since = "1.73.0")] +impl Write for Empty { + #[inline] + fn write(&mut self, buf: &[u8]) -> io::Result { + Ok(buf.len()) + } + + #[inline] + fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { + let total_len = bufs.iter().map(|b| b.len()).sum(); + Ok(total_len) + } + + #[inline] + fn is_write_vectored(&self) -> bool { + true + } + + #[inline] + fn write_all(&mut self, _buf: &[u8]) -> io::Result<()> { + Ok(()) + } + + #[inline] + fn write_all_vectored(&mut self, _bufs: &mut [IoSlice<'_>]) -> io::Result<()> { + Ok(()) + } + + #[inline] + fn write_fmt(&mut self, _args: fmt::Arguments<'_>) -> io::Result<()> { + Ok(()) + } + + #[inline] + fn flush(&mut self) -> io::Result<()> { + Ok(()) + } +} + +#[stable(feature = "empty_write", since = "1.73.0")] +impl Write for &Empty { + #[inline] + fn write(&mut self, buf: &[u8]) -> io::Result { + Ok(buf.len()) + } + + #[inline] + fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { + let total_len = bufs.iter().map(|b| b.len()).sum(); + Ok(total_len) + } + + #[inline] + fn is_write_vectored(&self) -> bool { + true + } + + #[inline] + fn write_all(&mut self, _buf: &[u8]) -> io::Result<()> { + Ok(()) + } + + #[inline] + fn write_all_vectored(&mut self, _bufs: &mut [IoSlice<'_>]) -> io::Result<()> { + Ok(()) + } + + #[inline] + fn write_fmt(&mut self, _args: fmt::Arguments<'_>) -> io::Result<()> { + Ok(()) + } + + #[inline] + fn flush(&mut self) -> io::Result<()> { + Ok(()) + } +} + +#[stable(feature = "empty_seek", since = "1.51.0")] +impl Seek for Empty { + #[inline] + fn seek(&mut self, _pos: SeekFrom) -> Result { + Ok(0) + } + + #[inline] + fn stream_len(&mut self) -> Result { + Ok(0) + } + + #[inline] + fn stream_position(&mut self) -> Result { + Ok(0) + } +} + +/// Creates a value that is always at EOF for reads, and ignores all data written. +/// +/// All calls to [`write`] on the returned instance will return [`Ok(buf.len())`] +/// and the contents of the buffer will not be inspected. +/// +/// All calls to [`read`] from the returned reader will return [`Ok(0)`]. +/// +/// [`Ok(buf.len())`]: Ok +/// [`Ok(0)`]: Ok +/// +/// [`write`]: crate::io::Write::write +/// [`read`]: ../../std/io/trait.Read.html#method.read +/// +/// # Examples +/// +/// ```rust +/// use std::io::{self, Write}; +/// +/// let buffer = vec![1, 2, 3, 5, 8]; +/// let num_bytes = io::empty().write(&buffer).unwrap(); +/// assert_eq!(num_bytes, 5); +/// ``` +/// +/// +/// ```rust +/// use std::io::{self, Read}; +/// +/// let mut buffer = String::new(); +/// io::empty().read_to_string(&mut buffer).unwrap(); +/// assert!(buffer.is_empty()); +/// ``` +#[must_use] +#[stable(feature = "rust1", since = "1.0.0")] +#[rustc_const_stable(feature = "const_io_structs", since = "1.79.0")] +pub const fn empty() -> Empty { + Empty +} + +/// A reader which yields one byte over and over and over and over and over and... +/// +/// This struct is generally created by calling [`repeat()`]. Please +/// see the documentation of [`repeat()`] for more details. +#[stable(feature = "rust1", since = "1.0.0")] +#[non_exhaustive] +pub struct Repeat { + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub byte: u8, +} + +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +impl SizeHint for Repeat { + #[inline] + fn lower_bound(&self) -> usize { + usize::MAX + } + + #[inline] + fn upper_bound(&self) -> Option { + None + } +} + +/// Creates an instance of a reader that infinitely repeats one byte. +/// +/// All reads from this reader will succeed by filling the specified buffer with +/// the given byte. +/// +/// # Examples +/// +/// ``` +/// use std::io::{self, Read}; +/// +/// let mut buffer = [0; 3]; +/// io::repeat(0b101).read_exact(&mut buffer).unwrap(); +/// assert_eq!(buffer, [0b101, 0b101, 0b101]); +/// ``` +#[must_use] +#[stable(feature = "rust1", since = "1.0.0")] +#[rustc_const_stable(feature = "const_io_structs", since = "1.79.0")] +pub const fn repeat(byte: u8) -> Repeat { + Repeat { byte } +} + +#[stable(feature = "std_debug", since = "1.16.0")] +impl fmt::Debug for Repeat { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("Repeat").finish_non_exhaustive() + } +} + +/// A writer which will move data into the void. +/// +/// This struct is generally created by calling [`sink()`]. Please +/// see the documentation of [`sink()`] for more details. +#[stable(feature = "rust1", since = "1.0.0")] +#[non_exhaustive] +#[derive(Copy, Clone, Debug, Default)] +pub struct Sink; + +#[stable(feature = "rust1", since = "1.0.0")] +impl Write for Sink { + #[inline] + fn write(&mut self, buf: &[u8]) -> io::Result { + Ok(buf.len()) + } + + #[inline] + fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { + let total_len = bufs.iter().map(|b| b.len()).sum(); + Ok(total_len) + } + + #[inline] + fn is_write_vectored(&self) -> bool { + true + } + + #[inline] + fn write_all(&mut self, _buf: &[u8]) -> io::Result<()> { + Ok(()) + } + + #[inline] + fn write_all_vectored(&mut self, _bufs: &mut [IoSlice<'_>]) -> io::Result<()> { + Ok(()) + } + + #[inline] + fn write_fmt(&mut self, _args: fmt::Arguments<'_>) -> io::Result<()> { + Ok(()) + } + + #[inline] + fn flush(&mut self) -> io::Result<()> { + Ok(()) + } +} + +#[stable(feature = "write_mt", since = "1.48.0")] +impl Write for &Sink { + #[inline] + fn write(&mut self, buf: &[u8]) -> io::Result { + Ok(buf.len()) + } + + #[inline] + fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { + let total_len = bufs.iter().map(|b| b.len()).sum(); + Ok(total_len) + } + + #[inline] + fn is_write_vectored(&self) -> bool { + true + } + + #[inline] + fn write_all(&mut self, _buf: &[u8]) -> io::Result<()> { + Ok(()) + } + + #[inline] + fn write_all_vectored(&mut self, _bufs: &mut [IoSlice<'_>]) -> io::Result<()> { + Ok(()) + } + + #[inline] + fn write_fmt(&mut self, _args: fmt::Arguments<'_>) -> io::Result<()> { + Ok(()) + } + + #[inline] + fn flush(&mut self) -> io::Result<()> { + Ok(()) + } +} + +/// Creates an instance of a writer which will successfully consume all data. +/// +/// All calls to [`write`] on the returned instance will return [`Ok(buf.len())`] +/// and the contents of the buffer will not be inspected. +/// +/// [`write`]: crate::io::Write::write +/// [`Ok(buf.len())`]: Ok +/// +/// # Examples +/// +/// ```rust +/// use std::io::{self, Write}; +/// +/// let buffer = vec![1, 2, 3, 5, 8]; +/// let num_bytes = io::sink().write(&buffer).unwrap(); +/// assert_eq!(num_bytes, 5); +/// ``` +#[must_use] +#[stable(feature = "rust1", since = "1.0.0")] +#[rustc_const_stable(feature = "const_io_structs", since = "1.79.0")] +pub const fn sink() -> Sink { + Sink +} + +/// Adapter to chain together two readers. +/// +/// This struct is generally created by calling [`chain`] on a reader. +/// Please see the documentation of [`chain`] for more details. +/// +/// [`chain`]: ../../std/io/trait.Read.html#method.chain +#[stable(feature = "rust1", since = "1.0.0")] +#[derive(Debug)] +#[non_exhaustive] +pub struct Chain { + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub first: T, + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub second: U, + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub done_first: bool, +} + +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +impl SizeHint for Chain { + #[inline] + fn lower_bound(&self) -> usize { + SizeHint::lower_bound(&self.first) + SizeHint::lower_bound(&self.second) + } + + #[inline] + fn upper_bound(&self) -> Option { + match (SizeHint::upper_bound(&self.first), SizeHint::upper_bound(&self.second)) { + (Some(first), Some(second)) => first.checked_add(second), + _ => None, + } + } +} + +impl Chain { + /// Consumes the `Chain`, returning the wrapped readers. + /// + /// # Examples + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let mut foo_file = File::open("foo.txt")?; + /// let mut bar_file = File::open("bar.txt")?; + /// + /// let chain = foo_file.chain(bar_file); + /// let (foo_file, bar_file) = chain.into_inner(); + /// Ok(()) + /// } + /// ``` + #[stable(feature = "more_io_inner_methods", since = "1.20.0")] + pub fn into_inner(self) -> (T, U) { + (self.first, self.second) + } + + /// Gets references to the underlying readers in this `Chain`. + /// + /// Care should be taken to avoid modifying the internal I/O state of the + /// underlying readers as doing so may corrupt the internal state of this + /// `Chain`. + /// + /// # Examples + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let mut foo_file = File::open("foo.txt")?; + /// let mut bar_file = File::open("bar.txt")?; + /// + /// let chain = foo_file.chain(bar_file); + /// let (foo_file, bar_file) = chain.get_ref(); + /// Ok(()) + /// } + /// ``` + #[stable(feature = "more_io_inner_methods", since = "1.20.0")] + pub fn get_ref(&self) -> (&T, &U) { + (&self.first, &self.second) + } + + /// Gets mutable references to the underlying readers in this `Chain`. + /// + /// Care should be taken to avoid modifying the internal I/O state of the + /// underlying readers as doing so may corrupt the internal state of this + /// `Chain`. + /// + /// # Examples + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let mut foo_file = File::open("foo.txt")?; + /// let mut bar_file = File::open("bar.txt")?; + /// + /// let mut chain = foo_file.chain(bar_file); + /// let (foo_file, bar_file) = chain.get_mut(); + /// Ok(()) + /// } + /// ``` + #[stable(feature = "more_io_inner_methods", since = "1.20.0")] + pub fn get_mut(&mut self) -> (&mut T, &mut U) { + (&mut self.first, &mut self.second) + } +} + +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +#[must_use] +#[inline] +pub const fn chain(first: T, second: U) -> Chain { + Chain { first, second, done_first: false } +} + +/// Reader adapter which limits the bytes read from an underlying reader. +/// +/// This struct is generally created by calling [`take`] on a reader. +/// Please see the documentation of [`take`] for more details. +/// +/// [`take`]: ../../std/io/trait.Read.html#method.take +#[stable(feature = "rust1", since = "1.0.0")] +#[derive(Debug)] +#[non_exhaustive] +pub struct Take { + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub inner: T, + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub len: u64, + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub limit: u64, +} + +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +impl SizeHint for Take { + #[inline] + fn lower_bound(&self) -> usize { + cmp::min(SizeHint::lower_bound(&self.inner) as u64, self.limit) as usize + } + + #[inline] + fn upper_bound(&self) -> Option { + match SizeHint::upper_bound(&self.inner) { + Some(upper_bound) => Some(cmp::min(upper_bound as u64, self.limit) as usize), + None => self.limit.try_into().ok(), + } + } +} + +impl Take { + /// Returns the number of bytes that can be read before this instance will + /// return EOF. + /// + /// # Note + /// + /// This instance may reach `EOF` after reading fewer bytes than indicated by + /// this method if the underlying [`Read`] instance reaches EOF. + /// + /// [`Read`]: ../../std/io/trait.Read.html + /// + /// # Examples + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let f = File::open("foo.txt")?; + /// + /// // read at most five bytes + /// let handle = f.take(5); + /// + /// println!("limit: {}", handle.limit()); + /// Ok(()) + /// } + /// ``` + #[stable(feature = "rust1", since = "1.0.0")] + pub fn limit(&self) -> u64 { + self.limit + } + + /// Returns the number of bytes read so far. + #[unstable(feature = "seek_io_take_position", issue = "97227")] + #[inline] + pub fn position(&self) -> u64 { + self.len - self.limit + } + + /// Sets the number of bytes that can be read before this instance will + /// return EOF. This is the same as constructing a new `Take` instance, so + /// the amount of bytes read and the previous limit value don't matter when + /// calling this method. + /// + /// # Examples + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let f = File::open("foo.txt")?; + /// + /// // read at most five bytes + /// let mut handle = f.take(5); + /// handle.set_limit(10); + /// + /// assert_eq!(handle.limit(), 10); + /// Ok(()) + /// } + /// ``` + #[stable(feature = "take_set_limit", since = "1.27.0")] + pub fn set_limit(&mut self, limit: u64) { + self.len = limit; + self.limit = limit; + } + + /// Consumes the `Take`, returning the wrapped reader. + /// + /// # Examples + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let mut file = File::open("foo.txt")?; + /// + /// let mut buffer = [0; 5]; + /// let mut handle = file.take(5); + /// handle.read(&mut buffer)?; + /// + /// let file = handle.into_inner(); + /// Ok(()) + /// } + /// ``` + #[stable(feature = "io_take_into_inner", since = "1.15.0")] + pub fn into_inner(self) -> T { + self.inner + } + + /// Gets a reference to the underlying reader. + /// + /// Care should be taken to avoid modifying the internal I/O state of the + /// underlying reader as doing so may corrupt the internal limit of this + /// `Take`. + /// + /// # Examples + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let mut file = File::open("foo.txt")?; + /// + /// let mut buffer = [0; 5]; + /// let mut handle = file.take(5); + /// handle.read(&mut buffer)?; + /// + /// let file = handle.get_ref(); + /// Ok(()) + /// } + /// ``` + #[stable(feature = "more_io_inner_methods", since = "1.20.0")] + pub fn get_ref(&self) -> &T { + &self.inner + } + + /// Gets a mutable reference to the underlying reader. + /// + /// Care should be taken to avoid modifying the internal I/O state of the + /// underlying reader as doing so may corrupt the internal limit of this + /// `Take`. + /// + /// # Examples + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let mut file = File::open("foo.txt")?; + /// + /// let mut buffer = [0; 5]; + /// let mut handle = file.take(5); + /// handle.read(&mut buffer)?; + /// + /// let file = handle.get_mut(); + /// Ok(()) + /// } + /// ``` + #[stable(feature = "more_io_inner_methods", since = "1.20.0")] + pub fn get_mut(&mut self) -> &mut T { + &mut self.inner + } +} + +#[stable(feature = "seek_io_take", since = "1.89.0")] +impl Seek for Take { + fn seek(&mut self, pos: SeekFrom) -> Result { + let new_position = match pos { + SeekFrom::Start(v) => Some(v), + SeekFrom::Current(v) => self.position().checked_add_signed(v), + SeekFrom::End(v) => self.len.checked_add_signed(v), + }; + let new_position = match new_position { + Some(v) if v <= self.len => v, + _ => return Err(ErrorKind::InvalidInput.into()), + }; + while new_position != self.position() { + if let Some(offset) = new_position.checked_signed_diff(self.position()) { + self.inner.seek_relative(offset)?; + self.limit = self.limit.wrapping_sub(offset as u64); + break; + } + let offset = if new_position > self.position() { i64::MAX } else { i64::MIN }; + self.inner.seek_relative(offset)?; + self.limit = self.limit.wrapping_sub(offset as u64); + } + Ok(new_position) + } + + fn stream_len(&mut self) -> Result { + Ok(self.len) + } + + fn stream_position(&mut self) -> Result { + Ok(self.position()) + } + + fn seek_relative(&mut self, offset: i64) -> Result<()> { + if !self.position().checked_add_signed(offset).is_some_and(|p| p <= self.len) { + return Err(ErrorKind::InvalidInput.into()); + } + self.inner.seek_relative(offset)?; + self.limit = self.limit.wrapping_sub(offset as u64); + Ok(()) + } +} + +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +#[must_use] +#[inline] +pub const fn take(inner: T, limit: u64) -> Take { + Take { inner, limit, len: limit } +} diff --git a/library/core/src/io/write.rs b/library/core/src/io/write.rs new file mode 100644 index 0000000000000..cdddd380885f4 --- /dev/null +++ b/library/core/src/io/write.rs @@ -0,0 +1,417 @@ +use crate::fmt; +use crate::io::{Error, IoSlice, Result}; + +/// A trait for objects which are byte-oriented sinks. +/// +/// Implementors of the `Write` trait are sometimes called 'writers'. +/// +/// Writers are defined by two required methods, [`write`] and [`flush`]: +/// +/// * The [`write`] method will attempt to write some data into the object, +/// returning how many bytes were successfully written. +/// +/// * The [`flush`] method is useful for adapters and explicit buffers +/// themselves for ensuring that all buffered data has been pushed out to the +/// 'true sink'. +/// +/// Writers are intended to be composable with one another. Many implementors +/// throughout [`std::io`] take and provide types which implement the `Write` +/// trait. +/// +/// [`write`]: Write::write +/// [`flush`]: Write::flush +/// [`std::io`]: crate::io +/// +/// # Examples +/// +/// ```no_run +/// use std::io::prelude::*; +/// use std::fs::File; +/// +/// fn main() -> std::io::Result<()> { +/// let data = b"some bytes"; +/// +/// let mut pos = 0; +/// let mut buffer = File::create("foo.txt")?; +/// +/// while pos < data.len() { +/// let bytes_written = buffer.write(&data[pos..])?; +/// pos += bytes_written; +/// } +/// Ok(()) +/// } +/// ``` +/// +/// The trait also provides convenience methods like [`write_all`], which calls +/// `write` in a loop until its entire input has been written. +/// +/// [`write_all`]: Write::write_all +#[stable(feature = "rust1", since = "1.0.0")] +#[doc(notable_trait)] +#[cfg_attr(not(test), rustc_diagnostic_item = "IoWrite")] +pub trait Write { + /// Writes a buffer into this writer, returning how many bytes were written. + /// + /// This function will attempt to write the entire contents of `buf`, but + /// the entire write might not succeed, or the write may also generate an + /// error. Typically, a call to `write` represents one attempt to write to + /// any wrapped object. + /// + /// Calls to `write` are not guaranteed to block waiting for data to be + /// written, and a write which would otherwise block can be indicated through + /// an [`Err`] variant. + /// + /// If this method consumed `n > 0` bytes of `buf` it must return [`Ok(n)`]. + /// If the return value is `Ok(n)` then `n` must satisfy `n <= buf.len()`. + /// A return value of `Ok(0)` typically means that the underlying object is + /// no longer able to accept bytes and will likely not be able to in the + /// future as well, or that the buffer provided is empty. + /// + /// # Errors + /// + /// Each call to `write` may generate an I/O error indicating that the + /// operation could not be completed. If an error is returned then no bytes + /// in the buffer were written to this writer. + /// + /// It is **not** considered an error if the entire buffer could not be + /// written to this writer. + /// + /// An error of the [`ErrorKind::Interrupted`] kind is non-fatal and the + /// write operation should be retried if there is nothing else to do. + /// + /// [`ErrorKind::Interrupted`]: crate::io::ErrorKind::Interrupted + /// + /// # Examples + /// + /// ```no_run + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> std::io::Result<()> { + /// let mut buffer = File::create("foo.txt")?; + /// + /// // Writes some prefix of the byte string, not necessarily all of it. + /// buffer.write(b"some bytes")?; + /// Ok(()) + /// } + /// ``` + /// + /// [`Ok(n)`]: Ok + #[stable(feature = "rust1", since = "1.0.0")] + fn write(&mut self, buf: &[u8]) -> Result; + + /// Like [`write`], except that it writes from a slice of buffers. + /// + /// Data is copied from each buffer in order, with the final buffer + /// read from possibly being only partially consumed. This method must + /// behave as a call to [`write`] with the buffers concatenated would. + /// + /// The default implementation calls [`write`] with either the first nonempty + /// buffer provided, or an empty one if none exists. + /// + /// # Examples + /// + /// ```no_run + /// use std::io::IoSlice; + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> std::io::Result<()> { + /// let data1 = [1; 8]; + /// let data2 = [15; 8]; + /// let io_slice1 = IoSlice::new(&data1); + /// let io_slice2 = IoSlice::new(&data2); + /// + /// let mut buffer = File::create("foo.txt")?; + /// + /// // Writes some prefix of the byte string, not necessarily all of it. + /// buffer.write_vectored(&[io_slice1, io_slice2])?; + /// Ok(()) + /// } + /// ``` + /// + /// [`write`]: Write::write + #[stable(feature = "iovec", since = "1.36.0")] + fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> Result { + default_write_vectored(|b| self.write(b), bufs) + } + + /// Determines if this `Write`r has an efficient [`write_vectored`] + /// implementation. + /// + /// If a `Write`r does not override the default [`write_vectored`] + /// implementation, code using it may want to avoid the method all together + /// and coalesce writes into a single buffer for higher performance. + /// + /// The default implementation returns `false`. + /// + /// [`write_vectored`]: Write::write_vectored + #[unstable(feature = "can_vector", issue = "69941")] + fn is_write_vectored(&self) -> bool { + false + } + + /// Flushes this output stream, ensuring that all intermediately buffered + /// contents reach their destination. + /// + /// # Errors + /// + /// It is considered an error if not all bytes could be written due to + /// I/O errors or EOF being reached. + /// + /// # Examples + /// + /// ```no_run + /// use std::io::prelude::*; + /// use std::io::BufWriter; + /// use std::fs::File; + /// + /// fn main() -> std::io::Result<()> { + /// let mut buffer = BufWriter::new(File::create("foo.txt")?); + /// + /// buffer.write_all(b"some bytes")?; + /// buffer.flush()?; + /// Ok(()) + /// } + /// ``` + #[stable(feature = "rust1", since = "1.0.0")] + fn flush(&mut self) -> Result<()>; + + /// Attempts to write an entire buffer into this writer. + /// + /// This method will continuously call [`write`] until there is no more data + /// to be written or an error of non-[`ErrorKind::Interrupted`] kind is + /// returned. This method will not return until the entire buffer has been + /// successfully written or such an error occurs. The first error that is + /// not of [`ErrorKind::Interrupted`] kind generated from this method will be + /// returned. + /// + /// [`ErrorKind::Interrupted`]: crate::io::ErrorKind::Interrupted + /// + /// If the buffer contains no data, this will never call [`write`]. + /// + /// # Errors + /// + /// This function will return the first error of + /// non-[`ErrorKind::Interrupted`] kind that [`write`] returns. + /// + /// [`write`]: Write::write + /// + /// # Examples + /// + /// ```no_run + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> std::io::Result<()> { + /// let mut buffer = File::create("foo.txt")?; + /// + /// buffer.write_all(b"some bytes")?; + /// Ok(()) + /// } + /// ``` + #[stable(feature = "rust1", since = "1.0.0")] + fn write_all(&mut self, mut buf: &[u8]) -> Result<()> { + while !buf.is_empty() { + match self.write(buf) { + Ok(0) => { + return Err(Error::WRITE_ALL_EOF); + } + Ok(n) => buf = &buf[n..], + Err(ref e) if e.is_interrupted() => {} + Err(e) => return Err(e), + } + } + Ok(()) + } + + /// Attempts to write multiple buffers into this writer. + /// + /// This method will continuously call [`write_vectored`] until there is no + /// more data to be written or an error of non-[`ErrorKind::Interrupted`] + /// kind is returned. This method will not return until all buffers have + /// been successfully written or such an error occurs. The first error that + /// is not of [`ErrorKind::Interrupted`] kind generated from this method + /// will be returned. + /// + /// [`ErrorKind::Interrupted`]: crate::io::ErrorKind::Interrupted + /// + /// If the buffer contains no data, this will never call [`write_vectored`]. + /// + /// # Notes + /// + /// Unlike [`write_vectored`], this takes a *mutable* reference to + /// a slice of [`IoSlice`]s, not an immutable one. That's because we need to + /// modify the slice to keep track of the bytes already written. + /// + /// Once this function returns, the contents of `bufs` are unspecified, as + /// this depends on how many calls to [`write_vectored`] were necessary. It is + /// best to understand this function as taking ownership of `bufs` and to + /// not use `bufs` afterwards. The underlying buffers, to which the + /// [`IoSlice`]s point (but not the [`IoSlice`]s themselves), are unchanged and + /// can be reused. + /// + /// [`write_vectored`]: Write::write_vectored + /// + /// # Examples + /// + /// ``` + /// #![feature(write_all_vectored)] + /// # fn main() -> std::io::Result<()> { + /// + /// use std::io::{Write, IoSlice}; + /// + /// let mut writer = Vec::new(); + /// let bufs = &mut [ + /// IoSlice::new(&[1]), + /// IoSlice::new(&[2, 3]), + /// IoSlice::new(&[4, 5, 6]), + /// ]; + /// + /// writer.write_all_vectored(bufs)?; + /// // Note: the contents of `bufs` is now undefined, see the Notes section. + /// + /// assert_eq!(writer, &[1, 2, 3, 4, 5, 6]); + /// # Ok(()) } + /// ``` + #[unstable(feature = "write_all_vectored", issue = "70436")] + fn write_all_vectored(&mut self, mut bufs: &mut [IoSlice<'_>]) -> Result<()> { + // Guarantee that bufs is empty if it contains no data, + // to avoid calling write_vectored if there is no data to be written. + IoSlice::advance_slices(&mut bufs, 0); + while !bufs.is_empty() { + match self.write_vectored(bufs) { + Ok(0) => { + return Err(Error::WRITE_ALL_EOF); + } + Ok(n) => IoSlice::advance_slices(&mut bufs, n), + Err(ref e) if e.is_interrupted() => {} + Err(e) => return Err(e), + } + } + Ok(()) + } + + /// Writes a formatted string into this writer, returning any error + /// encountered. + /// + /// This method is primarily used to interface with the + /// [`format_args!()`] macro, and it is rare that this should + /// explicitly be called. The [`write!()`] macro should be favored to + /// invoke this method instead. + /// + /// This function internally uses the [`write_all`] method on + /// this trait and hence will continuously write data so long as no errors + /// are received. This also means that partial writes are not indicated in + /// this signature. + /// + /// [`write_all`]: Write::write_all + /// + /// # Errors + /// + /// This function will return any I/O error reported while formatting. + /// + /// # Examples + /// + /// ```no_run + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> std::io::Result<()> { + /// let mut buffer = File::create("foo.txt")?; + /// + /// // this call + /// write!(buffer, "{:.*}", 2, 1.234567)?; + /// // turns into this: + /// buffer.write_fmt(format_args!("{:.*}", 2, 1.234567))?; + /// Ok(()) + /// } + /// ``` + #[stable(feature = "rust1", since = "1.0.0")] + fn write_fmt(&mut self, args: fmt::Arguments<'_>) -> Result<()> { + if let Some(s) = args.as_statically_known_str() { + self.write_all(s.as_bytes()) + } else { + default_write_fmt(self, args) + } + } + + /// Creates a "by reference" adapter for this instance of `Write`. + /// + /// The returned adapter also implements `Write` and will simply borrow this + /// current writer. + /// + /// # Examples + /// + /// ```no_run + /// use std::io::Write; + /// use std::fs::File; + /// + /// fn main() -> std::io::Result<()> { + /// let mut buffer = File::create("foo.txt")?; + /// + /// let reference = buffer.by_ref(); + /// + /// // we can use reference just like our original buffer + /// reference.write_all(b"some bytes")?; + /// Ok(()) + /// } + /// ``` + #[stable(feature = "rust1", since = "1.0.0")] + fn by_ref(&mut self) -> &mut Self + where + Self: Sized, + { + self + } +} + +/// Default implementation of [`Write::write_vectored`], which is currently used +/// in `libstd` for file system implementations of similar methods. +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +pub fn default_write_vectored(write: F, bufs: &[IoSlice<'_>]) -> Result +where + F: FnOnce(&[u8]) -> Result, +{ + let buf = bufs.iter().find(|b| !b.is_empty()).map_or(&[][..], |b| &**b); + write(buf) +} + +fn default_write_fmt(this: &mut W, args: fmt::Arguments<'_>) -> Result<()> { + // Create a shim which translates a `Write` to a `fmt::Write` and saves off + // I/O errors, instead of discarding them. + struct Adapter<'a, T: ?Sized + 'a> { + inner: &'a mut T, + error: Result<()>, + } + + impl fmt::Write for Adapter<'_, T> { + fn write_str(&mut self, s: &str) -> fmt::Result { + match self.inner.write_all(s.as_bytes()) { + Ok(()) => Ok(()), + Err(e) => { + self.error = Err(e); + Err(fmt::Error) + } + } + } + } + + let mut output = Adapter { inner: this, error: Ok(()) }; + match fmt::write(&mut output, args) { + Ok(()) => Ok(()), + Err(..) => { + // Check whether the error came from the underlying `Write`. + if output.error.is_err() { + output.error + } else { + // This shouldn't happen: the underlying stream did not error, + // but somehow the formatter still errored? + panic!( + "a formatting trait implementation returned an error when the underlying stream did not" + ); + } + } + } +} diff --git a/library/core/src/iter/adapters/array_chunks.rs b/library/core/src/iter/adapters/array_chunks.rs index 7c003cff10c7b..6c502ee75e17f 100644 --- a/library/core/src/iter/adapters/array_chunks.rs +++ b/library/core/src/iter/adapters/array_chunks.rs @@ -1,8 +1,6 @@ use crate::array; use crate::iter::adapters::SourceIter; -use crate::iter::{ - ByRefSized, FusedIterator, InPlaceIterable, TrustedFused, TrustedRandomAccessNoCoerce, -}; +use crate::iter::{FusedIterator, InPlaceIterable, TrustedFused, TrustedRandomAccessNoCoerce}; use crate::num::NonZero; use crate::ops::{ControlFlow, NeverShortCircuit, Try}; @@ -26,7 +24,7 @@ where I: Iterator, { #[track_caller] - pub(in crate::iter) fn new(iter: I) -> Self { + pub(in crate::iter) const fn new(iter: I) -> Self { assert!(N != 0, "chunk size must be non-zero"); Self { iter, remainder: None } } @@ -128,15 +126,11 @@ where self.next_back_remainder(); let mut acc = init; - let mut iter = ByRefSized(&mut self.iter).rev(); // NB remainder is handled by `next_back_remainder`, so - // `next_chunk` can't return `Err` with non-empty remainder + // `next_chunk_back` can't return `Err` with non-empty remainder // (assuming correct `I as ExactSizeIterator` impl). - while let Ok(mut chunk) = iter.next_chunk() { - // FIXME: do not do double reverse - // (we could instead add `next_chunk_back` for example) - chunk.reverse(); + while let Ok(chunk) = self.iter.next_chunk_back() { acc = f(acc, chunk)? } diff --git a/library/core/src/iter/adapters/chain.rs b/library/core/src/iter/adapters/chain.rs index 0ece54554d464..d143b67fd4353 100644 --- a/library/core/src/iter/adapters/chain.rs +++ b/library/core/src/iter/adapters/chain.rs @@ -33,7 +33,7 @@ pub struct Chain { b: Option, } impl Chain { - pub(in super::super) fn new(a: A, b: B) -> Chain { + pub(in super::super) const fn new(a: A, b: B) -> Chain { Chain { a: Some(a), b: Some(b) } } } diff --git a/library/core/src/iter/adapters/cloned.rs b/library/core/src/iter/adapters/cloned.rs index 0f05260059880..86d92b56c3984 100644 --- a/library/core/src/iter/adapters/cloned.rs +++ b/library/core/src/iter/adapters/cloned.rs @@ -4,7 +4,7 @@ use safety::requires; use crate::iter::adapters::zip::try_get_unchecked; use crate::iter::adapters::{SourceIter, TrustedRandomAccess, TrustedRandomAccessNoCoerce}; -use crate::iter::{FusedIterator, InPlaceIterable, TrustedLen, UncheckedIterator}; +use crate::iter::{FusedIterator, InPlaceIterable, TrustedLen}; #[cfg(kani)] use crate::kani; use crate::ops::Try; @@ -24,7 +24,7 @@ pub struct Cloned { } impl Cloned { - pub(in crate::iter) fn new(it: I) -> Cloned { + pub(in crate::iter) const fn new(it: I) -> Cloned { Cloned { it } } } @@ -147,19 +147,6 @@ where { } -impl<'a, I, T: 'a> UncheckedIterator for Cloned -where - I: UncheckedIterator, - T: Clone, -{ - unsafe fn next_unchecked(&mut self) -> T { - // SAFETY: `Cloned` is 1:1 with the inner iterator, so if the caller promised - // that there's an element left, the inner iterator has one too. - let item = unsafe { self.it.next_unchecked() }; - item.clone() - } -} - #[stable(feature = "default_iters", since = "1.70.0")] impl Default for Cloned { /// Creates a `Cloned` iterator from the default value of `I` diff --git a/library/core/src/iter/adapters/copied.rs b/library/core/src/iter/adapters/copied.rs index 3db6c5dafd400..a8592c8e3c671 100644 --- a/library/core/src/iter/adapters/copied.rs +++ b/library/core/src/iter/adapters/copied.rs @@ -25,7 +25,7 @@ pub struct Copied { } impl Copied { - pub(in crate::iter) fn new(it: I) -> Copied { + pub(in crate::iter) const fn new(it: I) -> Copied { Copied { it } } diff --git a/library/core/src/iter/adapters/cycle.rs b/library/core/src/iter/adapters/cycle.rs index 6cb1a3a46763e..86a6966ebf85b 100644 --- a/library/core/src/iter/adapters/cycle.rs +++ b/library/core/src/iter/adapters/cycle.rs @@ -17,7 +17,8 @@ pub struct Cycle { iter: I, } -impl Cycle { +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] +const impl Cycle { pub(in crate::iter) fn new(iter: I) -> Cycle { Cycle { orig: iter.clone(), iter } } diff --git a/library/core/src/iter/adapters/enumerate.rs b/library/core/src/iter/adapters/enumerate.rs index e7e18d178031f..8d83a8caaf53f 100644 --- a/library/core/src/iter/adapters/enumerate.rs +++ b/library/core/src/iter/adapters/enumerate.rs @@ -24,7 +24,7 @@ pub struct Enumerate { count: usize, } impl Enumerate { - pub(in crate::iter) fn new(iter: I) -> Enumerate { + pub(in crate::iter) const fn new(iter: I) -> Enumerate { Enumerate { iter, count: 0 } } diff --git a/library/core/src/iter/adapters/filter.rs b/library/core/src/iter/adapters/filter.rs index b22419ccf080a..cf21536784a28 100644 --- a/library/core/src/iter/adapters/filter.rs +++ b/library/core/src/iter/adapters/filter.rs @@ -24,7 +24,7 @@ pub struct Filter { predicate: P, } impl Filter { - pub(in crate::iter) fn new(iter: I, predicate: P) -> Filter { + pub(in crate::iter) const fn new(iter: I, predicate: P) -> Filter { Filter { iter, predicate } } } diff --git a/library/core/src/iter/adapters/filter_map.rs b/library/core/src/iter/adapters/filter_map.rs index 24ec6b1741ce1..3fd7e16d1c148 100644 --- a/library/core/src/iter/adapters/filter_map.rs +++ b/library/core/src/iter/adapters/filter_map.rs @@ -20,7 +20,7 @@ pub struct FilterMap { f: F, } impl FilterMap { - pub(in crate::iter) fn new(iter: I, f: F) -> FilterMap { + pub(in crate::iter) const fn new(iter: I, f: F) -> FilterMap { FilterMap { iter, f } } } diff --git a/library/core/src/iter/adapters/flatten.rs b/library/core/src/iter/adapters/flatten.rs index c50f07ff6bb66..7e3c69e29e96f 100644 --- a/library/core/src/iter/adapters/flatten.rs +++ b/library/core/src/iter/adapters/flatten.rs @@ -185,7 +185,8 @@ pub struct Flatten> { inner: FlattenCompat::IntoIter>, } -impl> Flatten { +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] +const impl> Flatten { pub(in super::super) fn new(iter: I) -> Flatten { Flatten { inner: FlattenCompat::new(iter) } } @@ -358,9 +359,11 @@ struct FlattenCompat { frontiter: Option, backiter: Option, } -impl FlattenCompat + +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] +const impl FlattenCompat where - I: Iterator, + I: [const] Iterator, { /// Adapts an iterator by flattening it, for use in `flatten()` and `flat_map()`. fn new(iter: I) -> FlattenCompat { diff --git a/library/core/src/iter/adapters/fuse.rs b/library/core/src/iter/adapters/fuse.rs index fcad6168d85cd..837cd43c12226 100644 --- a/library/core/src/iter/adapters/fuse.rs +++ b/library/core/src/iter/adapters/fuse.rs @@ -8,6 +8,7 @@ use crate::iter::{ }; #[cfg(kani)] use crate::kani; +use crate::num::NonZero; use crate::ops::Try; /// An iterator that yields `None` forever after the underlying iterator @@ -25,7 +26,7 @@ pub struct Fuse { iter: Option, } impl Fuse { - pub(in crate::iter) fn new(iter: I) -> Fuse { + pub(in crate::iter) const fn new(iter: I) -> Fuse { Fuse { iter: Some(iter) } } @@ -54,6 +55,10 @@ where FuseImpl::next(self) } + fn advance_by(&mut self, n: usize) -> Result<(), NonZero> { + FuseImpl::advance_by(self, n) + } + #[inline] fn nth(&mut self, n: usize) -> Option { FuseImpl::nth(self, n) @@ -265,6 +270,7 @@ trait FuseImpl { // Functions specific to any normal Iterators fn next(&mut self) -> Option; + fn advance_by(&mut self, n: usize) -> Result<(), NonZero>; fn nth(&mut self, n: usize) -> Option; fn try_fold(&mut self, acc: Acc, fold: Fold) -> R where @@ -307,6 +313,22 @@ where and_then_or_clear(&mut self.iter, Iterator::next) } + #[inline] + default fn advance_by(&mut self, n: usize) -> Result<(), NonZero> { + let Some(iter) = &mut self.iter else { + return match NonZero::new(n) { + Some(n) => Err(n), + None => Ok(()), + }; + }; + + let res = iter.advance_by(n); + if res.is_err() { + self.iter = None; + } + res + } + #[inline] default fn nth(&mut self, n: usize) -> Option { and_then_or_clear(&mut self.iter, |iter| iter.nth(n)) @@ -387,6 +409,17 @@ where self.iter.as_mut()?.next() } + #[inline] + fn advance_by(&mut self, n: usize) -> Result<(), NonZero> { + match &mut self.iter { + Some(iter) => iter.advance_by(n), + None => match NonZero::new(n) { + Some(n) => Err(n), + None => Ok(()), + }, + } + } + #[inline] fn nth(&mut self, n: usize) -> Option { self.iter.as_mut()?.nth(n) diff --git a/library/core/src/iter/adapters/inspect.rs b/library/core/src/iter/adapters/inspect.rs index 0e2a68a503e44..de94951bc80ff 100644 --- a/library/core/src/iter/adapters/inspect.rs +++ b/library/core/src/iter/adapters/inspect.rs @@ -20,7 +20,7 @@ pub struct Inspect { f: F, } impl Inspect { - pub(in crate::iter) fn new(iter: I, f: F) -> Inspect { + pub(in crate::iter) const fn new(iter: I, f: F) -> Inspect { Inspect { iter, f } } } diff --git a/library/core/src/iter/adapters/intersperse.rs b/library/core/src/iter/adapters/intersperse.rs index bb94ed0a0a170..1669a32ae77d2 100644 --- a/library/core/src/iter/adapters/intersperse.rs +++ b/library/core/src/iter/adapters/intersperse.rs @@ -1,5 +1,4 @@ use crate::fmt; -use crate::iter::{Fuse, FusedIterator}; /// An iterator adapter that places a separator between all elements. /// @@ -14,23 +13,15 @@ where started: bool, separator: I::Item, next_item: Option, - iter: Fuse, -} - -#[unstable(feature = "iter_intersperse", issue = "79524")] -impl FusedIterator for Intersperse -where - I: FusedIterator, - I::Item: Clone, -{ + iter: I, } impl Intersperse where I::Item: Clone, { - pub(in crate::iter) fn new(iter: I, separator: I::Item) -> Self { - Self { started: false, separator, next_item: None, iter: iter.fuse() } + pub(in crate::iter) const fn new(iter: I, separator: I::Item) -> Self { + Self { started: false, separator, next_item: None, iter } } } @@ -57,8 +48,9 @@ where } } } else { - self.started = true; - self.iter.next() + let item = self.iter.next(); + self.started = item.is_some(); + item } } @@ -95,15 +87,7 @@ where started: bool, separator: G, next_item: Option, - iter: Fuse, -} - -#[unstable(feature = "iter_intersperse", issue = "79524")] -impl FusedIterator for IntersperseWith -where - I: FusedIterator, - G: FnMut() -> I::Item, -{ + iter: I, } #[unstable(feature = "iter_intersperse", issue = "79524")] @@ -145,8 +129,8 @@ where I: Iterator, G: FnMut() -> I::Item, { - pub(in crate::iter) fn new(iter: I, separator: G) -> Self { - Self { started: false, separator, next_item: None, iter: iter.fuse() } + pub(in crate::iter) const fn new(iter: I, separator: G) -> Self { + Self { started: false, separator, next_item: None, iter } } } @@ -173,8 +157,9 @@ where } } } else { - self.started = true; - self.iter.next() + let item = self.iter.next(); + self.started = item.is_some(); + item } } diff --git a/library/core/src/iter/adapters/map.rs b/library/core/src/iter/adapters/map.rs index bf9f0c48fec3b..0bc4dac44b9a6 100644 --- a/library/core/src/iter/adapters/map.rs +++ b/library/core/src/iter/adapters/map.rs @@ -3,7 +3,7 @@ use safety::requires; use crate::fmt; use crate::iter::adapters::zip::try_get_unchecked; use crate::iter::adapters::{SourceIter, TrustedRandomAccess, TrustedRandomAccessNoCoerce}; -use crate::iter::{FusedIterator, InPlaceIterable, TrustedFused, TrustedLen, UncheckedIterator}; +use crate::iter::{FusedIterator, InPlaceIterable, TrustedFused, TrustedLen}; #[cfg(kani)] use crate::kani; use crate::num::NonZero; @@ -69,7 +69,7 @@ pub struct Map { } impl Map { - pub(in crate::iter) fn new(iter: I, f: F) -> Map { + pub(in crate::iter) const fn new(iter: I, f: F) -> Map { Map { iter, f } } @@ -199,20 +199,6 @@ where { } -impl UncheckedIterator for Map -where - I: UncheckedIterator, - F: FnMut(I::Item) -> B, -{ - #[requires(self.iter.size_hint().0 > 0)] - unsafe fn next_unchecked(&mut self) -> B { - // SAFETY: `Map` is 1:1 with the inner iterator, so if the caller promised - // that there's an element left, the inner iterator has one too. - let item = unsafe { self.iter.next_unchecked() }; - (self.f)(item) - } -} - #[doc(hidden)] #[unstable(feature = "trusted_random_access", issue = "none")] unsafe impl TrustedRandomAccess for Map where I: TrustedRandomAccess {} diff --git a/library/core/src/iter/adapters/map_while.rs b/library/core/src/iter/adapters/map_while.rs index c047c40de050e..3e34427da6142 100644 --- a/library/core/src/iter/adapters/map_while.rs +++ b/library/core/src/iter/adapters/map_while.rs @@ -20,7 +20,7 @@ pub struct MapWhile { } impl MapWhile { - pub(in crate::iter) fn new(iter: I, predicate: P) -> MapWhile { + pub(in crate::iter) const fn new(iter: I, predicate: P) -> MapWhile { MapWhile { iter, predicate } } } diff --git a/library/core/src/iter/adapters/map_windows.rs b/library/core/src/iter/adapters/map_windows.rs index 3d5918a552c61..cbde6c92b752e 100644 --- a/library/core/src/iter/adapters/map_windows.rs +++ b/library/core/src/iter/adapters/map_windows.rs @@ -1,5 +1,5 @@ use crate::iter::FusedIterator; -use crate::mem::MaybeUninit; +use crate::mem::{ManuallyDrop, MaybeUninit, SizedTypeProperties}; use crate::ub_checks::Invariant; use crate::{fmt, ptr}; @@ -15,10 +15,7 @@ pub struct MapWindows { } struct MapWindowsInner { - // We fuse the inner iterator because there shouldn't be "holes" in - // the sliding window. Once the iterator returns a `None`, we make - // our `MapWindows` iterator return `None` forever. - iter: Option, + iter: I, // Since iterators are assumed lazy, i.e. it only yields an item when // `Iterator::next()` is called, and `MapWindows` is not an exception. // @@ -27,31 +24,34 @@ struct MapWindowsInner { // we collect the first `N` items yielded from the inner iterator and // put it into the buffer. // - // When the inner iterator has returned a `None` (i.e. fused), we take + // When the inner iterator has returned a `None`, we take // away this `buffer` and leave it `None` to reclaim its resources. // // FIXME: should we shrink the size of `buffer` using niche optimization? buffer: Option>, } -// `Buffer` uses two times of space to reduce moves among the iterations. -// `Buffer` is semantically `[MaybeUninit; 2 * N]`. However, due -// to limitations of const generics, we use this different type. Note that -// it has the same underlying memory layout. +/// `Buffer` is semantically `[MaybeUninit; 2 * N]`. This helps +/// reduce moves while iterating. However, due +/// to limitations of const generics, we use this different type. Note that +/// it has the same underlying memory layout. +/// +/// # Safety invariant +/// +/// `self.buffer[self.start..self.start + N]` must be initialized, +/// with all other elements being uninitialized. This also +/// implies that `self.start <= N`. struct Buffer { - // Invariant: `self.buffer[self.start..self.start + N]` is initialized, - // with all other elements being uninitialized. This also - // implies that `self.start <= N`. buffer: [[MaybeUninit; N]; 2], start: usize, } impl MapWindows { - pub(in crate::iter) fn new(iter: I, f: F) -> Self { + pub(in crate::iter) const fn new(iter: I, f: F) -> Self { assert!(N != 0, "array in `Iterator::map_windows` must contain more than 0 elements"); // Only ZST arrays' length can be so large. - if size_of::() == 0 { + if I::Item::IS_ZST { assert!( N.checked_mul(2).is_some(), "array size of `Iterator::map_windows` is too large" @@ -64,20 +64,17 @@ impl MapWindows { impl MapWindowsInner { #[inline] - fn new(iter: I) -> Self { - Self { iter: Some(iter), buffer: None } + const fn new(iter: I) -> Self { + Self { iter, buffer: None } } fn next_window(&mut self) -> Option<&[I::Item; N]> { - let iter = self.iter.as_mut()?; match self.buffer { // It is the first time to advance. We collect // the first `N` items from `self.iter` to initialize `self.buffer`. - None => self.buffer = Buffer::try_from_iter(iter), - Some(ref mut buffer) => match iter.next() { + None => self.buffer = Buffer::try_from_iter(&mut self.iter), + Some(ref mut buffer) => match self.iter.next() { None => { - // Fuse the inner iterator since it yields a `None`. - self.iter.take(); self.buffer.take(); } // Advance the iterator. We first call `next` before changing our buffer @@ -90,8 +87,7 @@ impl MapWindowsInner { } fn size_hint(&self) -> (usize, Option) { - let Some(ref iter) = self.iter else { return (0, Some(0)) }; - let (lo, hi) = iter.size_hint(); + let (lo, hi) = self.iter.size_hint(); if self.buffer.is_some() { // If the first `N` items are already yielded by the inner iterator, // the size hint is then equal to the that of the inner iterator's. @@ -202,12 +198,18 @@ impl Buffer { impl Clone for Buffer { fn clone(&self) -> Self { - let mut buffer = Buffer { + // Use `ManuallyDrop` until buffer is fully written to avoid dropping uninitialized elements on panic. + // (See `Buffer` rustdoc for safety invariant) + let mut buffer = ManuallyDrop::new(Buffer { buffer: [[const { MaybeUninit::uninit() }; N], [const { MaybeUninit::uninit() }; N]], start: self.start, - }; + }); + + // `clone()` could panic; `ManuallyDrop` guards against that. buffer.as_uninit_array_mut().write(self.as_array_ref().clone()); - buffer + + // We initialized the buffer above, so we are good now + ManuallyDrop::into_inner(buffer) } } @@ -226,10 +228,8 @@ impl Drop for Buffer { // SAFETY: our invariant guarantees that N elements starting from // `self.start` are initialized. We drop them here. unsafe { - let initialized_part: *mut [T] = crate::ptr::slice_from_raw_parts_mut( - self.buffer_mut_ptr().add(self.start).cast(), - N, - ); + let initialized_part: *mut [T] = + self.buffer_mut_ptr().add(self.start).cast::().cast_slice(N); ptr::drop_in_place(initialized_part); } } @@ -254,12 +254,10 @@ where } } -// Note that even if the inner iterator not fused, the `MapWindows` is still fused, -// because we don't allow "holes" in the mapping window. #[unstable(feature = "iter_map_windows", issue = "87155")] impl FusedIterator for MapWindows where - I: Iterator, + I: FusedIterator, F: FnMut(&[I::Item; N]) -> R, { } diff --git a/library/core/src/iter/adapters/mod.rs b/library/core/src/iter/adapters/mod.rs index d0b89fdbb5843..ca950a138f31c 100644 --- a/library/core/src/iter/adapters/mod.rs +++ b/library/core/src/iter/adapters/mod.rs @@ -155,6 +155,9 @@ where for<'a> F: FnMut(GenericShunt<'a, I, R>) -> U, R: Residual, { + // FIXME(#11084): we might be able to get rid of GenericShunt in favor of + // Iterator::scan, as performance should be comparable + let mut residual = None; let shunt = GenericShunt { iter, residual: &mut residual }; let value = f(shunt); diff --git a/library/core/src/iter/adapters/peekable.rs b/library/core/src/iter/adapters/peekable.rs index 9f6d1df57dbe8..4bddc2025c26e 100644 --- a/library/core/src/iter/adapters/peekable.rs +++ b/library/core/src/iter/adapters/peekable.rs @@ -21,7 +21,7 @@ pub struct Peekable { } impl Peekable { - pub(in crate::iter) fn new(iter: I) -> Peekable { + pub(in crate::iter) const fn new(iter: I) -> Peekable { Peekable { iter, peeked: None } } } diff --git a/library/core/src/iter/adapters/rev.rs b/library/core/src/iter/adapters/rev.rs index 17d3eef597dcb..b9ada504525f9 100644 --- a/library/core/src/iter/adapters/rev.rs +++ b/library/core/src/iter/adapters/rev.rs @@ -17,7 +17,7 @@ pub struct Rev { } impl Rev { - pub(in crate::iter) fn new(iter: T) -> Rev { + pub(in crate::iter) const fn new(iter: T) -> Rev { Rev { iter } } diff --git a/library/core/src/iter/adapters/scan.rs b/library/core/src/iter/adapters/scan.rs index e12375c94e067..7d084a89bd940 100644 --- a/library/core/src/iter/adapters/scan.rs +++ b/library/core/src/iter/adapters/scan.rs @@ -21,7 +21,7 @@ pub struct Scan { } impl Scan { - pub(in crate::iter) fn new(iter: I, state: St, f: F) -> Scan { + pub(in crate::iter) const fn new(iter: I, state: St, f: F) -> Scan { Scan { iter, state, f } } } diff --git a/library/core/src/iter/adapters/skip.rs b/library/core/src/iter/adapters/skip.rs index ac3cc4c4f1152..9173489531107 100644 --- a/library/core/src/iter/adapters/skip.rs +++ b/library/core/src/iter/adapters/skip.rs @@ -28,7 +28,7 @@ pub struct Skip { } impl Skip { - pub(in crate::iter) fn new(iter: I, n: usize) -> Skip { + pub(in crate::iter) const fn new(iter: I, n: usize) -> Skip { Skip { iter, n } } } diff --git a/library/core/src/iter/adapters/skip_while.rs b/library/core/src/iter/adapters/skip_while.rs index 8ae453e76fa0d..ced4fd8f2abc4 100644 --- a/library/core/src/iter/adapters/skip_while.rs +++ b/library/core/src/iter/adapters/skip_while.rs @@ -21,7 +21,7 @@ pub struct SkipWhile { } impl SkipWhile { - pub(in crate::iter) fn new(iter: I, predicate: P) -> SkipWhile { + pub(in crate::iter) const fn new(iter: I, predicate: P) -> SkipWhile { SkipWhile { iter, flag: false, predicate } } } diff --git a/library/core/src/iter/adapters/step_by.rs b/library/core/src/iter/adapters/step_by.rs index 32604a07ca40c..f1e54b9cdd322 100644 --- a/library/core/src/iter/adapters/step_by.rs +++ b/library/core/src/iter/adapters/step_by.rs @@ -1,9 +1,10 @@ use crate::intrinsics; -use crate::iter::{TrustedLen, TrustedRandomAccess, from_fn}; +use crate::iter::{FusedIterator, TrustedLen, TrustedRandomAccess, from_fn}; #[cfg(kani)] use crate::kani; use crate::num::NonZero; use crate::ops::{Range, Try}; +use crate::range::RangeIter; use crate::ub_checks::Invariant; /// An iterator for stepping iterators by a custom amount. @@ -145,6 +146,11 @@ where #[stable(feature = "iterator_step_by", since = "1.28.0")] impl ExactSizeIterator for StepBy where I: ExactSizeIterator {} +// StepBy stops yielding items once the underlying iterator does, so it is fused +// whenever the underlying iterator is fused. +#[stable(feature = "step_by_fused", since = "1.99.0")] +impl FusedIterator for StepBy where I: FusedIterator {} + // SAFETY: This adapter is shortening. TrustedLen requires the upper bound to be calculated correctly. // These requirements can only be satisfied when the upper bound of the inner iterator's upper // bound is never `None`. I: TrustedRandomAccess happens to provide this guarantee while @@ -263,9 +269,9 @@ unsafe impl StepByImpl for StepBy { default fn spec_nth(&mut self, mut n: usize) -> Option { if self.first_take { self.first_take = false; - let first = self.iter.next(); + let first = self.iter.next()?; if n == 0 { - return first; + return Some(first); } n -= 1; } @@ -275,7 +281,7 @@ unsafe impl StepByImpl for StepBy { // n + 1 could overflow // thus, if n is usize::MAX, instead of adding one, we call .nth(step) if n == usize::MAX { - self.iter.nth(step - 1); + self.iter.nth(step - 1)?; } else { n += 1; } @@ -299,7 +305,8 @@ unsafe impl StepByImpl for StepBy { n -= div_step; nth_step }; - self.iter.nth(nth - 1); + + self.iter.nth(nth - 1)?; } } @@ -428,37 +435,71 @@ unsafe impl StepByBackImpl for St /// and we must consistently specialize backwards and forwards iteration /// that makes the situation complicated enough that it's not covered /// for now. +/// +/// After `SpecRangeSetup::setup`, both `Range` and its new-range wrapper +/// `RangeIter` carry the cursor and countdown in the same underlying legacy +/// `Range`. This accessor exposes that shared range so one specialization can +/// serve both: it is an identity for `Range` and unwraps the newtype for +/// `RangeIter`, so it compiles away. +trait AsLegacyRange { + fn as_legacy_range(&self) -> &Range; + fn as_legacy_range_mut(&mut self) -> &mut Range; +} + +impl AsLegacyRange for Range { + #[inline] + fn as_legacy_range(&self) -> &Range { + self + } + #[inline] + fn as_legacy_range_mut(&mut self) -> &mut Range { + self + } +} + +impl AsLegacyRange for RangeIter { + #[inline] + fn as_legacy_range(&self) -> &Range { + &self.0 + } + #[inline] + fn as_legacy_range_mut(&mut self) -> &mut Range { + &mut self.0 + } +} + macro_rules! spec_int_ranges { - ($($t:ty)*) => ($( + ($ctor:ident; $($t:ty)*) => ($( const _: () = assert!(usize::BITS >= <$t>::BITS); - impl SpecRangeSetup> for Range<$t> { + impl SpecRangeSetup<$ctor<$t>> for $ctor<$t> { #[inline] - fn setup(mut r: Range<$t>, step: usize) -> Range<$t> { + fn setup(mut r: $ctor<$t>, step: usize) -> $ctor<$t> { let inner_len = r.size_hint().0; // If step exceeds $t::MAX, then the count will be at most 1 and // thus always fit into $t. let yield_count = inner_len.div_ceil(step); // Turn the range end into an iteration counter - r.end = yield_count as $t; + r.as_legacy_range_mut().end = yield_count as $t; r } } - unsafe impl StepByImpl> for StepBy> { + unsafe impl StepByImpl<$ctor<$t>> for StepBy<$ctor<$t>> { #[inline] fn spec_next(&mut self) -> Option<$t> { // if a step size larger than the type has been specified fall back to // t::MAX, in which case remaining will be at most 1. let step = <$t>::try_from(self.original_step().get()).unwrap_or(<$t>::MAX); - let remaining = self.iter.end; + let r = self.iter.as_legacy_range_mut(); + let remaining = r.end; if remaining > 0 { - let val = self.iter.start; + let val = r.start; // this can only overflow during the last step, after which the value // will not be used - self.iter.start = val.wrapping_add(step); - self.iter.end = remaining - 1; + r.start = val.wrapping_add(step); + r.end = remaining - 1; Some(val) } else { None @@ -467,7 +508,7 @@ macro_rules! spec_int_ranges { #[inline] fn spec_size_hint(&self) -> (usize, Option) { - let remaining = self.iter.end as usize; + let remaining = self.iter.as_legacy_range().end as usize; (remaining, Some(remaining)) } @@ -501,9 +542,10 @@ macro_rules! spec_int_ranges { // if a step size larger than the type has been specified fall back to // t::MAX, in which case remaining will be at most 1. let step = <$t>::try_from(self.original_step().get()).unwrap_or(<$t>::MAX); - let remaining = self.iter.end; + let r = self.iter.as_legacy_range(); + let remaining = r.end; let mut acc = init; - let mut val = self.iter.start; + let mut val = r.start; for _ in 0..remaining { acc = f(acc, val); // this can only overflow during the last step, after which the value @@ -517,18 +559,19 @@ macro_rules! spec_int_ranges { } macro_rules! spec_int_ranges_r { - ($($t:ty)*) => ($( + ($ctor:ident; $($t:ty)*) => ($( const _: () = assert!(usize::BITS >= <$t>::BITS); - unsafe impl StepByBackImpl> for StepBy> { + unsafe impl StepByBackImpl<$ctor<$t>> for StepBy<$ctor<$t>> { #[inline] fn spec_next_back(&mut self) -> Option { let step = self.original_step().get() as $t; - let remaining = self.iter.end; + let r = self.iter.as_legacy_range_mut(); + let remaining = r.end; if remaining > 0 { - let start = self.iter.start; - self.iter.end = remaining - 1; + let start = r.start; + r.end = remaining - 1; Some(start + step * (remaining - 1)) } else { None @@ -574,18 +617,37 @@ macro_rules! spec_int_ranges_r { )*) } +// The same specialization covers `Range<{integer}>` and the new-range iterator +// `RangeIter<{integer}>`, which wraps a `Range` (see `AsLegacyRange`). +// +// The backward (`_r`) specialization requires `ExactSizeIterator`. `RangeIter` +// implements it only for `usize`/`u8`/`u16` (see `range_exact_iter_impl!` in +// `range::iter`), narrower than `Range`, so `RangeIter`'s backward set omits +// `u32` even where `Range` includes it; `Range` is likewise omitted on +// 64-bit since its length can exceed `usize`. #[cfg(target_pointer_width = "64")] -spec_int_ranges!(u8 u16 u32 u64 usize); -// DoubleEndedIterator requires ExactSizeIterator, which isn't implemented for Range -#[cfg(target_pointer_width = "64")] -spec_int_ranges_r!(u8 u16 u32 usize); +mod step_by_spec { + use super::*; + spec_int_ranges!(Range; u8 u16 u32 u64 usize); + spec_int_ranges!(RangeIter; u8 u16 u32 u64 usize); + spec_int_ranges_r!(Range; u8 u16 u32 usize); + spec_int_ranges_r!(RangeIter; u8 u16 usize); +} #[cfg(target_pointer_width = "32")] -spec_int_ranges!(u8 u16 u32 usize); -#[cfg(target_pointer_width = "32")] -spec_int_ranges_r!(u8 u16 u32 usize); +mod step_by_spec { + use super::*; + spec_int_ranges!(Range; u8 u16 u32 usize); + spec_int_ranges!(RangeIter; u8 u16 u32 usize); + spec_int_ranges_r!(Range; u8 u16 u32 usize); + spec_int_ranges_r!(RangeIter; u8 u16 usize); +} #[cfg(target_pointer_width = "16")] -spec_int_ranges!(u8 u16 usize); -#[cfg(target_pointer_width = "16")] -spec_int_ranges_r!(u8 u16 usize); +mod step_by_spec { + use super::*; + spec_int_ranges!(Range; u8 u16 usize); + spec_int_ranges!(RangeIter; u8 u16 usize); + spec_int_ranges_r!(Range; u8 u16 usize); + spec_int_ranges_r!(RangeIter; u8 u16 usize); +} diff --git a/library/core/src/iter/adapters/take.rs b/library/core/src/iter/adapters/take.rs index b96335f415257..3df2c70801644 100644 --- a/library/core/src/iter/adapters/take.rs +++ b/library/core/src/iter/adapters/take.rs @@ -20,7 +20,7 @@ pub struct Take { } impl Take { - pub(in crate::iter) fn new(iter: I, n: usize) -> Take { + pub(in crate::iter) const fn new(iter: I, n: usize) -> Take { Take { iter, n } } } @@ -56,6 +56,19 @@ where } } + #[inline] + fn count(mut self) -> usize { + if self.n == 0 { + return 0; + } + // Advancing consumes the same elements `next` would have yielded, + // while benefiting from the inner iterator's `advance_by` fast path. + match self.iter.advance_by(self.n) { + Ok(()) => self.n, + Err(remaining) => self.n - remaining.get(), + } + } + #[inline] fn size_hint(&self) -> (usize, Option) { if self.n == 0 { diff --git a/library/core/src/iter/adapters/take_while.rs b/library/core/src/iter/adapters/take_while.rs index 06028ea98e7fd..6e40629567a83 100644 --- a/library/core/src/iter/adapters/take_while.rs +++ b/library/core/src/iter/adapters/take_while.rs @@ -21,7 +21,7 @@ pub struct TakeWhile { } impl TakeWhile { - pub(in crate::iter) fn new(iter: I, predicate: P) -> TakeWhile { + pub(in crate::iter) const fn new(iter: I, predicate: P) -> TakeWhile { TakeWhile { iter, flag: false, predicate } } } diff --git a/library/core/src/iter/adapters/zip.rs b/library/core/src/iter/adapters/zip.rs index e39f1535bd95d..a5dc7e59096f6 100644 --- a/library/core/src/iter/adapters/zip.rs +++ b/library/core/src/iter/adapters/zip.rs @@ -2,9 +2,7 @@ use safety::requires; use crate::cmp; use crate::fmt::{self, Debug}; -use crate::iter::{ - FusedIterator, InPlaceIterable, SourceIter, TrustedFused, TrustedLen, UncheckedIterator, -}; +use crate::iter::{FusedIterator, InPlaceIterable, SourceIter, TrustedFused, TrustedLen}; #[cfg(kani)] use crate::kani; use crate::num::NonZero; @@ -133,7 +131,6 @@ where } // Zip specialization trait -#[doc(hidden)] trait ZipImpl { type Item; fn new(a: A, b: B) -> Self; @@ -212,7 +209,6 @@ macro_rules! zip_impl_general_defaults { } // General Zip impl -#[doc(hidden)] impl ZipImpl for Zip where A: Iterator, @@ -255,7 +251,6 @@ where } } -#[doc(hidden)] impl ZipImpl for Zip where A: TrustedRandomAccessNoCoerce + Iterator, @@ -297,7 +292,6 @@ where } } -#[doc(hidden)] impl ZipImpl for Zip where A: TrustedRandomAccess + Iterator, @@ -463,13 +457,6 @@ where { } -impl UncheckedIterator for Zip -where - A: UncheckedIterator, - B: UncheckedIterator, -{ -} - // Arbitrarily selects the left side of the zip iteration as extractable "source" // it would require negative trait bounds to be able to try both #[unstable(issue = "none", feature = "inplace_iteration")] diff --git a/library/core/src/iter/mod.rs b/library/core/src/iter/mod.rs index d532f1e568071..9ddafd47807f2 100644 --- a/library/core/src/iter/mod.rs +++ b/library/core/src/iter/mod.rs @@ -458,7 +458,6 @@ pub use self::traits::TrustedFused; pub use self::traits::TrustedLen; #[unstable(feature = "trusted_step", issue = "85731")] pub use self::traits::TrustedStep; -pub(crate) use self::traits::UncheckedIterator; #[stable(feature = "rust1", since = "1.0.0")] pub use self::traits::{ DoubleEndedIterator, ExactSizeIterator, Extend, FromIterator, IntoIterator, Product, Sum, diff --git a/library/core/src/iter/range.rs b/library/core/src/iter/range.rs index 8e71150aef552..979901ffa6712 100644 --- a/library/core/src/iter/range.rs +++ b/library/core/src/iter/range.rs @@ -19,13 +19,14 @@ macro_rules! unsafe_impl_trusted_step { )*}; } unsafe_impl_trusted_step![AsciiChar char i8 i16 i32 i64 i128 isize u8 u16 u32 u64 u128 usize Ipv4Addr Ipv6Addr]; +unsafe_impl_trusted_step![NonZero NonZero NonZero NonZero NonZero NonZero]; /// Objects that have a notion of *successor* and *predecessor* operations. /// /// The *successor* operation moves towards values that compare greater. /// The *predecessor* operation moves towards values that compare lesser. #[rustc_diagnostic_item = "range_step"] -#[rustc_on_unimplemented( +#[diagnostic::on_unimplemented( message = "`std::ops::Range<{Self}>` is not an iterator", label = "`Range<{Self}>` is not an iterator", note = "`Range` only implements `Iterator` for select types in the standard library, \ @@ -33,7 +34,8 @@ unsafe_impl_trusted_step![AsciiChar char i8 i16 i32 i64 i128 isize u8 u16 u32 u6 unstable `Step` trait" )] #[unstable(feature = "step_trait", issue = "42168")] -pub trait Step: Clone + PartialOrd + Sized { +#[rustc_const_unstable(feature = "step_trait", issue = "42168")] +pub const trait Step: [const] Clone + [const] PartialOrd + Sized { /// Returns the bounds on the number of *successor* steps required to get from `start` to `end` /// like [`Iterator::size_hint()`][Iterator::size_hint()]. /// @@ -68,6 +70,31 @@ pub trait Step: Clone + PartialOrd + Sized { /// * Corollary: `Step::forward_checked(a, 0) == Some(a)` fn forward_checked(start: Self, count: usize) -> Option; + /// Returns the value that would be obtained by taking the *successor* + /// of `self` `count` times along with a boolean tracking whether overflow + /// occurred. + /// + /// If this would overflow the range of values supported by `Self`, the + /// value returned is unspecified and should not be relied on, though + /// typically wrapping (modular arithmetic) is the most effective + /// implementation to enable optimizations. + /// + /// # Invariants + /// + /// For any `a`, `n`, and `m`, where no overflow occurs: + /// + /// * `Step::forward_overflowing(Step::forward_overflowing(a, n).0, m) == Step::forward_overflowing(a, n + m)` + /// + /// For any `a` and `n`, where no overflow occurs: + /// + /// * `Step::forward_overflowing(a, n) == (Step::forward_checked(a, n).unwrap(), false)` + /// + /// For any `a` and `n`: + /// + /// * `Step::forward_overflowing(a, n) == (0..n).fold((a, false), |(x, y), _| { let (s, o) = Step::forward_overflowing(x, 1); (s, y || o) })` + /// * Corollary: `Step::forward_overflowing(a, 0) == (a, false)` + fn forward_overflowing(start: Self, count: usize) -> (Self, bool); + /// Returns the value that would be obtained by taking the *successor* /// of `self` `count` times. /// @@ -138,6 +165,31 @@ pub trait Step: Clone + PartialOrd + Sized { /// * Corollary: `Step::backward_checked(a, 0) == Some(a)` fn backward_checked(start: Self, count: usize) -> Option; + /// Returns the value that would be obtained by taking the *successor* + /// of `self` `count` times along with a boolean tracking whether overflow + /// occurred. + /// + /// If this would overflow the range of values supported by `Self`, the + /// value returned is unspecified and should not be relied on, though + /// typically wrapping (modular arithmetic) is the most effective + /// implementation to enable optimizations. + /// + /// # Invariants + /// + /// For any `a`, `n`, and `m`, where no overflow occurs: + /// + /// * `Step::backward_overflowing(Step::backward_overflowing(a, n).0, m) == Step::backward_overflowing(a, n + m)` + /// + /// For any `a` and `n`, where no overflow occurs: + /// + /// * `Step::backward_overflowing(a, n) == (Step::backward_checked(a, n).unwrap(), false)` + /// + /// For any `a` and `n`: + /// + /// * `Step::backward_overflowing(a, n) == (0..n).fold((a, false), |(x, y), _| { let (s, o) = Step::backward_overflowing(x, 1); (s, y || o) })` + /// * Corollary: `Step::backward_overflowing(a, 0) == (a, false)` + fn backward_overflowing(start: Self, count: usize) -> (Self, bool); + /// Returns the value that would be obtained by taking the *predecessor* /// of `self` `count` times. /// @@ -262,15 +314,14 @@ macro_rules! step_identical_methods { macro_rules! step_integer_impls { { - narrower than or same width as usize: - $( [ $u_narrower:ident $i_narrower:ident ] ),+; - wider than usize: - $( [ $u_wider:ident $i_wider:ident ] ),+; + [ $( [ $u_narrower:ident $i_narrower:ident ] ),+ ] <= usize < + [ $( [ $u_wider:ident $i_wider:ident ] ),+ ] } => { $( #[allow(unreachable_patterns)] #[unstable(feature = "step_trait", issue = "42168")] - impl Step for $u_narrower { + #[rustc_const_unstable(feature = "step_trait", issue = "42168")] + const impl Step for $u_narrower { step_identical_methods!(); step_unsigned_methods!(); @@ -300,11 +351,30 @@ macro_rules! step_integer_impls { Err(_) => None, // if n is out of range, `unsigned_start - n` is too } } + + #[inline] + fn forward_overflowing(start: Self, n: usize) -> (Self, bool) { + match Self::try_from(n) { + Ok(n) => start.overflowing_add(n), + // if n is out of range, `start + n` must overflow + Err(_) => (start.wrapping_add(n as Self), true), + } + } + + #[inline] + fn backward_overflowing(start: Self, n: usize) -> (Self, bool) { + match Self::try_from(n) { + Ok(n) => start.overflowing_sub(n), + // if n is out of range, `start - n` must overflow + Err(_) => (start.wrapping_sub(n as Self), true), + } + } } #[allow(unreachable_patterns)] #[unstable(feature = "step_trait", issue = "42168")] - impl Step for $i_narrower { + #[rustc_const_unstable(feature = "step_trait", issue = "42168")] + const impl Step for $i_narrower { step_identical_methods!(); step_signed_methods!($u_narrower); @@ -364,13 +434,36 @@ macro_rules! step_integer_impls { Err(_) => None, } } + + #[inline] + fn forward_overflowing(start: Self, n: usize) -> (Self, bool) { + match $u_narrower::try_from(n) { + Ok(n) => start.overflowing_add_unsigned(n), + // If n is out of range of e.g. u8, + // then it is bigger than the entire range for i8 is wide + // so `any_i8 + n` necessarily overflows i8. + Err(_) => (start.wrapping_add_unsigned(n as $u_narrower), true), + } + } + + #[inline] + fn backward_overflowing(start: Self, n: usize) -> (Self, bool) { + match $u_narrower::try_from(n) { + Ok(n) => start.overflowing_sub_unsigned(n), + // If n is out of range of e.g. u8, + // then it is bigger than the entire range for i8 is wide + // so `any_i8 - n` necessarily overflows i8. + Err(_) => (start.wrapping_sub_unsigned(n as $u_narrower), true), + } + } } )+ $( #[allow(unreachable_patterns)] #[unstable(feature = "step_trait", issue = "42168")] - impl Step for $u_wider { + #[rustc_const_unstable(feature = "step_trait", issue = "42168")] + const impl Step for $u_wider { step_identical_methods!(); step_unsigned_methods!(); @@ -396,11 +489,22 @@ macro_rules! step_integer_impls { fn backward_checked(start: Self, n: usize) -> Option { start.checked_sub(n as Self) } + + #[inline] + fn forward_overflowing(start: Self, n: usize) -> (Self, bool) { + start.overflowing_add(n as Self) + } + + #[inline] + fn backward_overflowing(start: Self, n: usize) -> (Self, bool) { + start.overflowing_sub(n as Self) + } } #[allow(unreachable_patterns)] #[unstable(feature = "step_trait", issue = "42168")] - impl Step for $i_wider { + #[rustc_const_unstable(feature = "step_trait", issue = "42168")] + const impl Step for $i_wider { step_identical_methods!(); step_signed_methods!($u_wider); @@ -433,6 +537,16 @@ macro_rules! step_integer_impls { fn backward_checked(start: Self, n: usize) -> Option { start.checked_sub(n as Self) } + + #[inline] + fn forward_overflowing(start: Self, n: usize) -> (Self, bool) { + start.overflowing_add_unsigned(n as $u_wider) + } + + #[inline] + fn backward_overflowing(start: Self, n: usize) -> (Self, bool) { + start.overflowing_sub_unsigned(n as $u_wider) + } } )+ }; @@ -440,24 +554,170 @@ macro_rules! step_integer_impls { #[cfg(target_pointer_width = "64")] step_integer_impls! { - narrower than or same width as usize: [u8 i8], [u16 i16], [u32 i32], [u64 i64], [usize isize]; - wider than usize: [u128 i128]; + [ [u8 i8], [u16 i16], [u32 i32], [u64 i64], [usize isize] ] <= usize < [ [u128 i128] ] } #[cfg(target_pointer_width = "32")] step_integer_impls! { - narrower than or same width as usize: [u8 i8], [u16 i16], [u32 i32], [usize isize]; - wider than usize: [u64 i64], [u128 i128]; + [ [u8 i8], [u16 i16], [u32 i32], [usize isize] ] <= usize < [ [u64 i64], [u128 i128] ] } #[cfg(target_pointer_width = "16")] step_integer_impls! { - narrower than or same width as usize: [u8 i8], [u16 i16], [usize isize]; - wider than usize: [u32 i32], [u64 i64], [u128 i128]; + [ [u8 i8], [u16 i16], [usize isize] ] <= usize < [ [u32 i32], [u64 i64], [u128 i128] ] +} + +// These are still macro-generated because the integer literals resolve to different types. +macro_rules! step_nonzero_identical_methods { + ($int:ident) => { + #[inline] + unsafe fn forward_unchecked(start: Self, n: usize) -> Self { + // SAFETY: the caller has to guarantee that `start + n` doesn't overflow. + unsafe { Self::new_unchecked(start.get().unchecked_add(n as $int)) } + } + + #[inline] + unsafe fn backward_unchecked(start: Self, n: usize) -> Self { + // SAFETY: the caller has to guarantee that `start - n` doesn't overflow or hit zero. + unsafe { Self::new_unchecked(start.get().unchecked_sub(n as $int)) } + } + + #[inline] + #[allow(arithmetic_overflow)] + #[rustc_inherit_overflow_checks] + fn forward(start: Self, n: usize) -> Self { + // In debug builds, trigger a panic on overflow. + // This should optimize completely out in release builds. + if Self::forward_checked(start, n).is_none() { + let _ = $int::MAX + 1; + } + // Do saturating math (wrapping math causes UB if it wraps to Zero) + start.saturating_add(n as $int) + } + + #[inline] + #[allow(arithmetic_overflow)] + #[rustc_inherit_overflow_checks] + fn backward(start: Self, n: usize) -> Self { + // In debug builds, trigger a panic on overflow. + // This should optimize completely out in release builds. + if Self::backward_checked(start, n).is_none() { + let _ = $int::MIN - 1; + } + // Do saturating math (wrapping math causes UB if it wraps to Zero) + Self::new(start.get().saturating_sub(n as $int)).unwrap_or(Self::MIN) + } + + // Note: These NonZero overflowing implementations were chosen for + // code simplicity. Many alternative impls were examined, and some + // yielded marginally simpler assembly, but none resulted in the same + // loop -> arithmetic optimizations seen with the bare integers. + + #[inline] + fn forward_overflowing(start: Self, n: usize) -> (Self, bool) { + // Wrapping to Zero causes UB, so saturate to MAX instead. + if let Some(s) = Step::forward_checked(start, n) { + (s, false) + } else { + (Self::MAX, true) + } + } + + #[inline] + fn backward_overflowing(start: Self, n: usize) -> (Self, bool) { + // Subtracting to Zero causes UB, so saturate to MIN instead. + if let Some(s) = Step::backward_checked(start, n) { + (s, false) + } else { + (Self::MIN, true) + } + } + + #[inline] + fn steps_between(start: &Self, end: &Self) -> (usize, Option) { + if *start <= *end { + #[allow(irrefutable_let_patterns, reason = "happens on usize or narrower")] + if let Ok(steps) = usize::try_from(end.get() - start.get()) { + (steps, Some(steps)) + } else { + (usize::MAX, None) + } + } else { + (0, None) + } + } + }; +} + +macro_rules! step_nonzero_impls { + { + [$( $narrower:ident ),+] <= usize < [$( $wider:ident ),+] + } => { + $( + #[allow(unreachable_patterns)] + #[unstable(feature = "step_trait", reason = "recently redesigned", issue = "42168")] + #[rustc_const_unstable(feature = "step_trait", issue = "42168")] + const impl Step for NonZero<$narrower> { + step_nonzero_identical_methods!($narrower); + + #[inline] + fn forward_checked(start: Self, n: usize) -> Option { + match $narrower::try_from(n) { + Ok(n) => start.checked_add(n), + Err(_) => None, // if n is out of range, `unsigned_start + n` is too + } + } + + #[inline] + fn backward_checked(start: Self, n: usize) -> Option { + match $narrower::try_from(n) { + // *_sub() is not implemented on NonZero + Ok(n) => start.get().checked_sub(n).and_then(Self::new), + Err(_) => None, // if n is out of range, `unsigned_start - n` is too + } + } + } + )+ + + $( + #[allow(unreachable_patterns)] + #[unstable(feature = "step_trait", reason = "recently redesigned", issue = "42168")] + #[rustc_const_unstable(feature = "step_trait", issue = "42168")] + const impl Step for NonZero<$wider> { + step_nonzero_identical_methods!($wider); + + #[inline] + fn forward_checked(start: Self, n: usize) -> Option { + start.checked_add(n as $wider) + } + + #[inline] + fn backward_checked(start: Self, n: usize) -> Option { + start.get().checked_sub(n as $wider).and_then(Self::new) + } + } + )+ + }; +} + +#[cfg(target_pointer_width = "64")] +step_nonzero_impls! { + [u8, u16, u32, u64, usize] <= usize < [u128] +} + +#[cfg(target_pointer_width = "32")] +step_nonzero_impls! { + [u8, u16, u32, usize] <= usize < [u64, u128] +} + +#[cfg(target_pointer_width = "16")] +step_nonzero_impls! { + [u8, u16, usize] <= usize < [u32, u64, u128] } #[unstable(feature = "step_trait", issue = "42168")] -impl Step for char { +#[rustc_const_unstable(feature = "step_trait", issue = "42168")] +const impl Step for char { #[inline] fn steps_between(&start: &char, &end: &char) -> (usize, Option) { let start = start as u32; @@ -510,6 +770,29 @@ impl Step for char { Some(unsafe { char::from_u32_unchecked(res) }) } + // Note: These char overflowing implementations were chosen for + // code simplicity. Alternative impls were examined, and some + // yielded marginally simpler assembly, but none resulted in the same + // loop -> arithmetic optimizations seen with the bare integers. + + #[inline] + fn forward_overflowing(start: Self, count: usize) -> (Self, bool) { + if let Some(c) = Step::forward_checked(start, count) { + (c, false) + } else { + (Self::MAX, true) + } + } + + #[inline] + fn backward_overflowing(start: Self, count: usize) -> (Self, bool) { + if let Some(c) = Step::backward_checked(start, count) { + (c, false) + } else { + (Self::MIN, true) + } + } + #[requires({ (start as u32).checked_add(count as u32).is_some_and(|dist| (start as u32) >= 0xD800 || @@ -558,7 +841,8 @@ impl Step for char { } #[unstable(feature = "step_trait", issue = "42168")] -impl Step for AsciiChar { +#[rustc_const_unstable(feature = "step_trait", issue = "42168")] +const impl Step for AsciiChar { #[inline] fn steps_between(&start: &AsciiChar, &end: &AsciiChar) -> (usize, Option) { Step::steps_between(&start.to_u8(), &end.to_u8()) @@ -579,6 +863,24 @@ impl Step for AsciiChar { } #[requires(count < 256 && start.to_u8().checked_add(count as u8).is_some())] + #[inline] + fn forward_overflowing(start: Self, count: usize) -> (Self, bool) { + let (s, o) = (start as usize).overflowing_add(count); + let ret = s & (AsciiChar::MAX as usize); + + // SAFETY: Clamped to [0, MAX], must be valid ASCII + (unsafe { AsciiChar::from_u8_unchecked(ret as u8) }, o || ret < s) + } + + #[inline] + fn backward_overflowing(start: Self, count: usize) -> (Self, bool) { + let (s, o) = (start as usize).overflowing_sub(count); + let ret = s & (AsciiChar::MAX as usize); + + // SAFETY: Clamped to [0, MAX], must be valid ASCII + (unsafe { AsciiChar::from_u8_unchecked(ret as u8) }, o || ret < s) + } + #[inline] unsafe fn forward_unchecked(start: AsciiChar, count: usize) -> AsciiChar { // SAFETY: Caller asserts that result is a valid ASCII character, @@ -602,7 +904,8 @@ impl Step for AsciiChar { } #[unstable(feature = "step_trait", issue = "42168")] -impl Step for Ipv4Addr { +#[rustc_const_unstable(feature = "step_trait", issue = "42168")] +const impl Step for Ipv4Addr { #[inline] fn steps_between(&start: &Ipv4Addr, &end: &Ipv4Addr) -> (usize, Option) { u32::steps_between(&start.to_bits(), &end.to_bits()) @@ -619,6 +922,18 @@ impl Step for Ipv4Addr { } #[requires(start.to_bits().checked_add(count as u32).is_some())] + #[inline] + fn forward_overflowing(start: Self, count: usize) -> (Self, bool) { + let (s, o) = u32::forward_overflowing(start.to_bits(), count); + (Ipv4Addr::from_bits(s), o) + } + + #[inline] + fn backward_overflowing(start: Self, count: usize) -> (Self, bool) { + let (s, o) = u32::backward_overflowing(start.to_bits(), count); + (Ipv4Addr::from_bits(s), o) + } + #[inline] unsafe fn forward_unchecked(start: Ipv4Addr, count: usize) -> Ipv4Addr { // SAFETY: Since u32 and Ipv4Addr are losslessly convertible, @@ -636,7 +951,8 @@ impl Step for Ipv4Addr { } #[unstable(feature = "step_trait", issue = "42168")] -impl Step for Ipv6Addr { +#[rustc_const_unstable(feature = "step_trait", issue = "42168")] +const impl Step for Ipv6Addr { #[inline] fn steps_between(&start: &Ipv6Addr, &end: &Ipv6Addr) -> (usize, Option) { u128::steps_between(&start.to_bits(), &end.to_bits()) @@ -653,6 +969,18 @@ impl Step for Ipv6Addr { } #[requires(start.to_bits().checked_add(count as u128).is_some())] + #[inline] + fn forward_overflowing(start: Self, count: usize) -> (Self, bool) { + let (s, o) = u128::forward_overflowing(start.to_bits(), count); + (Ipv6Addr::from_bits(s), o) + } + + #[inline] + fn backward_overflowing(start: Self, count: usize) -> (Self, bool) { + let (s, o) = u128::backward_overflowing(start.to_bits(), count); + (Ipv6Addr::from_bits(s), o) + } + #[inline] unsafe fn forward_unchecked(start: Ipv6Addr, count: usize) -> Ipv6Addr { // SAFETY: Since u128 and Ipv6Addr are losslessly convertible, @@ -964,6 +1292,7 @@ impl Iterator for ops::Range { range_exact_iter_impl! { usize u8 u16 isize i8 i16 + NonZero NonZero NonZero // These are incorrect per the reasoning above, // but removing them would be a breaking change as they were stabilized in Rust 1.0.0. @@ -976,22 +1305,30 @@ range_exact_iter_impl! { unsafe_range_trusted_random_access_impl! { usize u8 u16 isize i8 i16 + NonZero NonZero NonZero } #[cfg(target_pointer_width = "32")] unsafe_range_trusted_random_access_impl! { u32 i32 + NonZero } #[cfg(target_pointer_width = "64")] unsafe_range_trusted_random_access_impl! { u32 i32 u64 i64 + NonZero + NonZero } range_incl_exact_iter_impl! { u8 i8 + NonZero + // Since RangeInclusive> can only be 1..=uN::MAX the length of this range is always + // <= uN::MAX, so they are always valid ExactSizeIterator unlike the ranges that include zero. + NonZero NonZero // These are incorrect per the reasoning above, // but removing them would be a breaking change as they were stabilized in Rust 1.26.0. @@ -1078,7 +1415,6 @@ trait RangeInclusiveIteratorImpl { type Item; // Iterator - fn spec_next(&mut self) -> Option; fn spec_try_fold(&mut self, init: B, f: F) -> R where Self: Sized, @@ -1086,7 +1422,6 @@ trait RangeInclusiveIteratorImpl { R: Try; // DoubleEndedIterator - fn spec_next_back(&mut self) -> Option; fn spec_try_rfold(&mut self, init: B, f: F) -> R where Self: Sized, @@ -1097,22 +1432,6 @@ trait RangeInclusiveIteratorImpl { impl RangeInclusiveIteratorImpl for ops::RangeInclusive { type Item = A; - #[inline] - default fn spec_next(&mut self) -> Option { - if self.is_empty() { - return None; - } - let is_iterating = self.start < self.end; - Some(if is_iterating { - let n = - Step::forward_checked(self.start.clone(), 1).expect("`Step` invariants not upheld"); - mem::replace(&mut self.start, n) - } else { - self.exhausted = true; - self.start.clone() - }) - } - #[inline] default fn spec_try_fold(&mut self, init: B, mut f: F) -> R where @@ -1142,22 +1461,6 @@ impl RangeInclusiveIteratorImpl for ops::RangeInclusive { try { accum } } - #[inline] - default fn spec_next_back(&mut self) -> Option { - if self.is_empty() { - return None; - } - let is_iterating = self.start < self.end; - Some(if is_iterating { - let n = - Step::backward_checked(self.end.clone(), 1).expect("`Step` invariants not upheld"); - mem::replace(&mut self.end, n) - } else { - self.exhausted = true; - self.end.clone() - }) - } - #[inline] default fn spec_try_rfold(&mut self, init: B, mut f: F) -> R where @@ -1189,22 +1492,6 @@ impl RangeInclusiveIteratorImpl for ops::RangeInclusive { } impl RangeInclusiveIteratorImpl for ops::RangeInclusive { - #[inline] - fn spec_next(&mut self) -> Option { - if self.is_empty() { - return None; - } - let is_iterating = self.start < self.end; - Some(if is_iterating { - // SAFETY: just checked precondition - let n = unsafe { Step::forward_unchecked(self.start, 1) }; - mem::replace(&mut self.start, n) - } else { - self.exhausted = true; - self.start - }) - } - #[inline] fn spec_try_fold(&mut self, init: B, mut f: F) -> R where @@ -1234,22 +1521,6 @@ impl RangeInclusiveIteratorImpl for ops::RangeInclusive { try { accum } } - #[inline] - fn spec_next_back(&mut self) -> Option { - if self.is_empty() { - return None; - } - let is_iterating = self.start < self.end; - Some(if is_iterating { - // SAFETY: just checked precondition - let n = unsafe { Step::backward_unchecked(self.end, 1) }; - mem::replace(&mut self.end, n) - } else { - self.exhausted = true; - self.end - }) - } - #[inline] fn spec_try_rfold(&mut self, init: B, mut f: F) -> R where @@ -1286,7 +1557,14 @@ impl Iterator for ops::RangeInclusive { #[inline] fn next(&mut self) -> Option { - self.spec_next() + if self.is_empty() { + return None; + } + + let (n, o) = Step::forward_overflowing(self.start.clone(), 1); + + self.exhausted = o; + Some(mem::replace(&mut self.start, n)) } #[inline] @@ -1317,26 +1595,13 @@ impl Iterator for ops::RangeInclusive { return None; } - if let Some(plus_n) = Step::forward_checked(self.start.clone(), n) { - use crate::cmp::Ordering::*; + let (plus_n, on) = Step::forward_overflowing(self.start.clone(), n); + let (plus_1, o1) = Step::forward_overflowing(plus_n.clone(), 1); - match plus_n.partial_cmp(&self.end) { - Some(Less) => { - self.start = Step::forward(plus_n.clone(), 1); - return Some(plus_n); - } - Some(Equal) => { - self.start = plus_n.clone(); - self.exhausted = true; - return Some(plus_n); - } - _ => {} - } - } + self.start = plus_1; + self.exhausted = on | o1; - self.start = self.end.clone(); - self.exhausted = true; - None + if !on && plus_n <= self.end { Some(plus_n) } else { None } } #[inline] @@ -1382,7 +1647,14 @@ impl Iterator for ops::RangeInclusive { impl DoubleEndedIterator for ops::RangeInclusive { #[inline] fn next_back(&mut self) -> Option { - self.spec_next_back() + if self.is_empty() { + return None; + } + + let (n, o) = Step::backward_overflowing(self.end.clone(), 1); + + self.exhausted = o; + Some(mem::replace(&mut self.end, n)) } #[inline] @@ -1391,26 +1663,13 @@ impl DoubleEndedIterator for ops::RangeInclusive { return None; } - if let Some(minus_n) = Step::backward_checked(self.end.clone(), n) { - use crate::cmp::Ordering::*; + let (minus_n, on) = Step::backward_overflowing(self.end.clone(), n); + let (minus_1, o1) = Step::backward_overflowing(minus_n.clone(), 1); - match minus_n.partial_cmp(&self.start) { - Some(Greater) => { - self.end = Step::backward(minus_n.clone(), 1); - return Some(minus_n); - } - Some(Equal) => { - self.end = minus_n.clone(); - self.exhausted = true; - return Some(minus_n); - } - _ => {} - } - } + self.end = minus_1; + self.exhausted = on | o1; - self.end = self.start.clone(); - self.exhausted = true; - None + if !on && minus_n >= self.start { Some(minus_n) } else { None } } #[inline] diff --git a/library/core/src/iter/sources/empty.rs b/library/core/src/iter/sources/empty.rs index 1844c76e5df7e..7733c2babc550 100644 --- a/library/core/src/iter/sources/empty.rs +++ b/library/core/src/iter/sources/empty.rs @@ -82,7 +82,7 @@ impl Clone for Empty { // which isn't necessary. #[stable(feature = "iter_empty", since = "1.2.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for Empty { +const impl Default for Empty { fn default() -> Empty { Empty(marker::PhantomData) } diff --git a/library/core/src/iter/sources/repeat.rs b/library/core/src/iter/sources/repeat.rs index f578ae86a9fce..bdad4adccabac 100644 --- a/library/core/src/iter/sources/repeat.rs +++ b/library/core/src/iter/sources/repeat.rs @@ -101,11 +101,21 @@ impl Iterator for Repeat { Some(self.element.clone()) } + /// Consumes the iterator and panics. + /// + /// # Panics + /// + /// This method always panics because `Repeat` is infinite. #[track_caller] fn last(self) -> Option { panic!("iterator is infinite"); } + /// Consumes the iterator and panics. + /// + /// # Panics + /// + /// This method always panics because `Repeat` is infinite. #[track_caller] fn count(self) -> usize { panic!("iterator is infinite"); diff --git a/library/core/src/iter/sources/repeat_n.rs b/library/core/src/iter/sources/repeat_n.rs index c29ab24a08357..d19ff6b7e024f 100644 --- a/library/core/src/iter/sources/repeat_n.rs +++ b/library/core/src/iter/sources/repeat_n.rs @@ -1,5 +1,5 @@ use crate::fmt; -use crate::iter::{FusedIterator, TrustedLen, UncheckedIterator}; +use crate::iter::{FusedIterator, TrustedLen}; use crate::num::NonZero; use crate::ops::Try; @@ -102,6 +102,15 @@ impl fmt::Debug for RepeatN { } } +/// Creates an empty iterator, like [`repeat_n(value, 0)`][`repeat_n`] +/// but without needing any such value at hand. +#[stable(feature = "iter_repeat_n_default", since = "1.97.0")] +impl Default for RepeatN { + fn default() -> Self { + RepeatN { inner: None } + } +} + #[stable(feature = "iter_repeat_n", since = "1.82.0")] impl Iterator for RepeatN { type Item = A; @@ -118,7 +127,7 @@ impl Iterator for RepeatN { return Some(tmp); } - return self.take_element(); + self.take_element() } #[inline] @@ -141,7 +150,7 @@ impl Iterator for RepeatN { } self.inner = None; - return NonZero::::new(skip - len).map(Err).unwrap_or(Ok(())); + NonZero::::new(skip - len).map(Err).unwrap_or(Ok(())) } #[inline] @@ -202,5 +211,3 @@ impl FusedIterator for RepeatN {} #[unstable(feature = "trusted_len", issue = "37572")] unsafe impl TrustedLen for RepeatN {} -#[stable(feature = "iter_repeat_n", since = "1.82.0")] -impl UncheckedIterator for RepeatN {} diff --git a/library/core/src/iter/traits/accum.rs b/library/core/src/iter/traits/accum.rs index 375b5ef52859f..3787e41f0a0b1 100644 --- a/library/core/src/iter/traits/accum.rs +++ b/library/core/src/iter/traits/accum.rs @@ -10,11 +10,12 @@ use crate::num::{Saturating, Wrapping}; /// [`sum()`]: Iterator::sum /// [`FromIterator`]: iter::FromIterator #[stable(feature = "iter_arith_traits", since = "1.12.0")] +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] #[diagnostic::on_unimplemented( message = "a value of type `{Self}` cannot be made by summing an iterator over elements of type `{A}`", label = "value of type `{Self}` cannot be made by summing a `std::iter::Iterator`" )] -pub trait Sum: Sized { +pub const trait Sum: Sized { /// Takes an iterator and generates `Self` from the elements by "summing up" /// the items. #[stable(feature = "iter_arith_traits", since = "1.12.0")] @@ -31,11 +32,12 @@ pub trait Sum: Sized { /// [`product()`]: Iterator::product /// [`FromIterator`]: iter::FromIterator #[stable(feature = "iter_arith_traits", since = "1.12.0")] +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] #[diagnostic::on_unimplemented( message = "a value of type `{Self}` cannot be made by multiplying all elements of type `{A}` from an iterator", label = "value of type `{Self}` cannot be made by multiplying all elements from a `std::iter::Iterator`" )] -pub trait Product: Sized { +pub const trait Product: Sized { /// Takes an iterator and generates `Self` from the elements by multiplying /// the items. #[stable(feature = "iter_arith_traits", since = "1.12.0")] diff --git a/library/core/src/iter/traits/collect.rs b/library/core/src/iter/traits/collect.rs index 9c3edfd4192d5..e7e5e30b4eff5 100644 --- a/library/core/src/iter/traits/collect.rs +++ b/library/core/src/iter/traits/collect.rs @@ -314,7 +314,7 @@ pub const trait IntoIterator { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_iter", issue = "92476")] -impl const IntoIterator for I { +const impl IntoIterator for I { type Item = I::Item; type IntoIter = I; diff --git a/library/core/src/iter/traits/double_ended.rs b/library/core/src/iter/traits/double_ended.rs index 9f7ac7da2dbda..a16732e1d8c74 100644 --- a/library/core/src/iter/traits/double_ended.rs +++ b/library/core/src/iter/traits/double_ended.rs @@ -1,3 +1,5 @@ +use crate::array; +use crate::marker::Destruct; use crate::num::NonZero; use crate::ops::{ControlFlow, Try}; @@ -38,7 +40,8 @@ use crate::ops::{ControlFlow, Try}; /// ``` #[stable(feature = "rust1", since = "1.0.0")] #[rustc_diagnostic_item = "DoubleEndedIterator"] -pub trait DoubleEndedIterator: Iterator { +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] +pub const trait DoubleEndedIterator: [const] Iterator { /// Removes and returns an element from the end of the iterator. /// /// Returns `None` when there are no more elements. @@ -93,6 +96,53 @@ pub trait DoubleEndedIterator: Iterator { #[stable(feature = "rust1", since = "1.0.0")] fn next_back(&mut self) -> Option; + /// Advances from the back of the iterator and returns an array containing the next + /// `N` values in sequence. + /// + /// If there are not enough elements to fill the array then `Err` is returned + /// containing an iterator over the remaining elements. + /// + /// Note: This is not equivalent to doing `iter.rev().next_chunk()` as this method + /// takes elements from the back of the iterator and preserves the order that the + /// elements were seen in the original iterator. + /// + /// # Examples + /// + /// Basic usage: + /// + /// ``` + /// #![feature(iter_next_chunk)] + /// + /// let mut iter = "lorem".chars(); + /// + /// assert_eq!(iter.next_chunk_back().unwrap(), ['e', 'm']); // N is inferred as 2 + /// assert_eq!(iter.next_chunk_back().unwrap(), ['l', 'o', 'r']); // N is inferred as 3 + /// assert_eq!(iter.next_chunk_back::<4>().unwrap_err().as_slice(), &[]); // N is explicitly 4 + /// ``` + /// + /// Split a string and get the last three items in sequence. + /// + /// ``` + /// #![feature(iter_next_chunk)] + /// + /// let quote = "not all those who wander are lost"; + /// let [first, second, third] = quote.split_whitespace().next_chunk_back().unwrap(); + /// assert_eq!(first, "wander"); + /// assert_eq!(second, "are"); + /// assert_eq!(third, "lost"); + /// ``` + #[inline] + #[unstable(feature = "iter_next_chunk", issue = "98326")] + #[rustc_non_const_trait_method] + fn next_chunk_back( + &mut self, + ) -> Result<[Self::Item; N], array::IntoIter> + where + Self: Sized, + { + crate::array::iter_next_chunk_back(self) + } + /// Advances the iterator from the back by `n` elements. /// /// `advance_back_by` is the reverse version of [`advance_by`]. This method will @@ -135,6 +185,7 @@ pub trait DoubleEndedIterator: Iterator { /// [`Err(k)`]: Err #[inline] #[unstable(feature = "iter_advance_by", issue = "77404")] + #[rustc_non_const_trait_method] fn advance_back_by(&mut self, n: usize) -> Result<(), NonZero> { for i in 0..n { if self.next_back().is_none() { @@ -188,6 +239,7 @@ pub trait DoubleEndedIterator: Iterator { /// ``` #[inline] #[stable(feature = "iter_nth_back", since = "1.37.0")] + #[rustc_non_const_trait_method] fn nth_back(&mut self, n: usize) -> Option { if self.advance_back_by(n).is_err() { return None; @@ -230,8 +282,8 @@ pub trait DoubleEndedIterator: Iterator { fn try_rfold(&mut self, init: B, mut f: F) -> R where Self: Sized, - F: FnMut(B, Self::Item) -> R, - R: Try, + F: [const] FnMut(B, Self::Item) -> R + [const] Destruct, + R: [const] Try, { let mut accum = init; while let Some(x) = self.next_back() { @@ -300,8 +352,8 @@ pub trait DoubleEndedIterator: Iterator { #[stable(feature = "iter_rfold", since = "1.27.0")] fn rfold(mut self, init: B, mut f: F) -> B where - Self: Sized, - F: FnMut(B, Self::Item) -> B, + Self: Sized + [const] Destruct, + F: [const] FnMut(B, Self::Item) -> B + [const] Destruct, { let mut accum = init; while let Some(x) = self.next_back() { @@ -363,6 +415,7 @@ pub trait DoubleEndedIterator: Iterator { /// ``` #[inline] #[stable(feature = "iter_rfind", since = "1.27.0")] + #[rustc_non_const_trait_method] fn rfind